openbcm

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allregs_b.i (2119986B)

      1 /*
      2  * DO NOT EDIT THIS FILE!
      3  * This file is auto-generated from the registers file.
      4  * Edits to this file will be lost when it is regenerated.
      5  *
      6  * 
      7  * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
      8  * 
      9  * Copyright 2007-2020 Broadcom Inc. All rights reserved.
     10  *
     11  * File:        allregs_b.i
     12  * Purpose:     Independent register descriptions.
     13  */
     14 
     15 #if defined(BCM_53570_A0)
     16     { /* SOC_REG_INT_BASE_TIME_FRACr */
     17         soc_block_list[4],
     18         soc_portreg,
     19         2,
     20         0,
     21         0x11a800,
     22         SOC_REG_FLAG_ARRAY,
     23         0,
     24         1,
     25         soc_BASE_TIME_FRACr_fields,
     26         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     27         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
     28         -1,
     29         103,
     30     },
     31 #endif /* chips */
     32 
     33 #if defined(BCM_53570_B0)
     34     { /* SOC_REG_INT_BASE_TIME_FRAC_BCM53570_B0r */
     35         soc_block_list[4],
     36         soc_portreg,
     37         2,
     38         0,
     39         0x11ab00,
     40         SOC_REG_FLAG_ARRAY,
     41         0,
     42         1,
     43         soc_BASE_TIME_FRACr_fields,
     44         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     45         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
     46         -1,
     47         103,
     48     },
     49 #endif /* chips */
     50 
     51 #if defined(BCM_53570_A0)
     52     { /* SOC_REG_INT_BASE_TIME_SECr */
     53         soc_block_list[4],
     54         soc_portreg,
     55         2,
     56         0,
     57         0x11a000,
     58         SOC_REG_FLAG_ARRAY,
     59         0,
     60         1,
     61         soc_BASE_TIME_SECr_fields,
     62         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     63         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
     64         -1,
     65         103,
     66     },
     67 #endif /* chips */
     68 
     69 #if defined(BCM_53570_B0)
     70     { /* SOC_REG_INT_BASE_TIME_SEC_BCM53570_B0r */
     71         soc_block_list[4],
     72         soc_portreg,
     73         2,
     74         0,
     75         0x11a300,
     76         SOC_REG_FLAG_ARRAY,
     77         0,
     78         1,
     79         soc_BASE_TIME_SECr_fields,
     80         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
     81         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
     82         -1,
     83         103,
     84     },
     85 #endif /* chips */
     86 
     87 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
     88     defined(BCM_56504_B0) || defined(BCM_56514_A0)
     89     { /* SOC_REG_INT_BCAST_BLOCK_MASKr */
     90         soc_block_list[5],
     91         soc_portreg,
     92         1,
     93         0,
     94         0xe000102,
     95         0,
     96         0,
     97         1,
     98         soc_BCAST_BLOCK_MASKr_fields,
     99         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    100         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
    101         -1,
    102         -1,
    103     },
    104 #endif /* chips */
    105 
    106 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
    107     defined(BCM_56680_A0) || defined(BCM_56680_B0)
    108     { /* SOC_REG_INT_BCAST_BLOCK_MASK_64r */
    109         soc_block_list[5],
    110         soc_portreg,
    111         1,
    112         0,
    113         0x11000042,
    114         SOC_REG_FLAG_64_BITS,
    115         0,
    116         3,
    117         soc_BCAST_BLOCK_MASK_64r_fields,
    118         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    119         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
    120         -1,
    121         -1,
    122     },
    123 #endif /* chips */
    124 
    125 #if defined(BCM_53400_A0)
    126     { /* SOC_REG_INT_BCAST_BLOCK_MASK_64_BCM53400_A0r */
    127         soc_block_list[5],
    128         soc_portreg,
    129         1,
    130         0,
    131         0x40000400,
    132         0,
    133         0,
    134         2,
    135         soc_BCAST_BLOCK_MASK_64_BCM53400_A0r_fields,
    136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    137         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    138         -1,
    139         -1,
    140     },
    141 #endif /* chips */
    142 
    143 #if defined(BCM_56142_A0)
    144     { /* SOC_REG_INT_BCAST_BLOCK_MASK_64_BCM56142_A0r */
    145         soc_block_list[5],
    146         soc_portreg,
    147         1,
    148         0,
    149         0x11000062,
    150         0,
    151         0,
    152         2,
    153         soc_BCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
    154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    155         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
    156         -1,
    157         -1,
    158     },
    159 #endif /* chips */
    160 
    161 #if defined(BCM_56150_A0)
    162     { /* SOC_REG_INT_BCAST_BLOCK_MASK_64_BCM56150_A0r */
    163         soc_block_list[5],
    164         soc_portreg,
    165         1,
    166         0,
    167         0x44000400,
    168         0,
    169         0,
    170         2,
    171         soc_BCAST_BLOCK_MASK_64_BCM56150_A0r_fields,
    172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    174         -1,
    175         -1,
    176     },
    177 #endif /* chips */
    178 
    179 #if defined(BCM_53540_A0) || defined(BCM_56160_A0)
    180     { /* SOC_REG_INT_BCAST_BLOCK_MASK_64_BCM56160_A0r */
    181         soc_block_list[5],
    182         soc_portreg,
    183         1,
    184         0,
    185         0x40000400,
    186         0,
    187         0,
    188         2,
    189         soc_BCAST_BLOCK_MASK_64_BCM56160_A0r_fields,
    190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    191         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    192         -1,
    193         -1,
    194     },
    195 #endif /* chips */
    196 
    197 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
    198     { /* SOC_REG_INT_BCAST_BLOCK_MASK_64_BCM56334_A0r */
    199         soc_block_list[5],
    200         soc_portreg,
    201         1,
    202         0,
    203         0x11000042,
    204         0,
    205         0,
    206         2,
    207         soc_BCAST_BLOCK_MASK_64_BCM56334_A0r_fields,
    208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    209         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
    210         -1,
    211         -1,
    212     },
    213 #endif /* chips */
    214 
    215 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    216     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    217     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    218     { /* SOC_REG_INT_BCAST_BLOCK_MASK_64_BCM56634_A0r */
    219         soc_block_list[5],
    220         soc_portreg,
    221         1,
    222         0,
    223         0xe000042,
    224         SOC_REG_FLAG_64_BITS,
    225         0,
    226         4,
    227         soc_BCAST_BLOCK_MASK_64_BCM56634_A0r_fields,
    228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    229         SOC_RESET_MASK_DEC(0xffffffff, 0x007fffff)
    230         -1,
    231         -1,
    232     },
    233 #endif /* chips */
    234 
    235 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
    236     { /* SOC_REG_INT_BCAST_BLOCK_MASK_BCM53314_A0r */
    237         soc_block_list[5],
    238         soc_portreg,
    239         1,
    240         0,
    241         0xf000104,
    242         0,
    243         0,
    244         1,
    245         soc_BCAST_BLOCK_MASK_BCM53314_A0r_fields,
    246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    247         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
    248         -1,
    249         -1,
    250     },
    251 #endif /* chips */
    252 
    253 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
    254     { /* SOC_REG_INT_BCAST_BLOCK_MASK_BCM56224_A0r */
    255         soc_block_list[5],
    256         soc_portreg,
    257         1,
    258         0,
    259         0xf000104,
    260         0,
    261         0,
    262         1,
    263         soc_BCAST_BLOCK_MASK_BCM56224_A0r_fields,
    264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    265         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
    266         -1,
    267         -1,
    268     },
    269 #endif /* chips */
    270 
    271 #if defined(BCM_56800_A0)
    272     { /* SOC_REG_INT_BCAST_BLOCK_MASK_BCM56800_A0r */
    273         soc_block_list[5],
    274         soc_portreg,
    275         1,
    276         0,
    277         0xe000042,
    278         0,
    279         0,
    280         1,
    281         soc_BCAST_BLOCK_MASK_BCM56800_A0r_fields,
    282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    283         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
    284         -1,
    285         -1,
    286     },
    287 #endif /* chips */
    288 
    289 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
    290     { /* SOC_REG_INT_BCAST_BLOCK_MASK_BCM56820_A0r */
    291         soc_block_list[5],
    292         soc_portreg,
    293         1,
    294         0,
    295         0xf000042,
    296         0,
    297         0,
    298         1,
    299         soc_BCAST_BLOCK_MASKr_fields,
    300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    301         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
    302         -1,
    303         -1,
    304     },
    305 #endif /* chips */
    306 
    307 #if defined(BCM_88732_A0)
    308     { /* SOC_REG_INT_BCAST_BLOCK_MASK_BCM88732_A0r */
    309         soc_block_list[5],
    310         soc_portreg,
    311         1,
    312         0,
    313         0x8000068,
    314         0,
    315         0,
    316         1,
    317         soc_BCAST_BLOCK_MASK_BCM88732_A0r_fields,
    318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    319         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
    320         -1,
    321         -1,
    322     },
    323 #endif /* chips */
    324 
    325 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
    326     { /* SOC_REG_INT_BCAST_BLOCK_MASK_HIr */
    327         soc_block_list[5],
    328         soc_portreg,
    329         1,
    330         0,
    331         0xf000105,
    332         0,
    333         0,
    334         1,
    335         soc_BCAST_BLOCK_MASK_HIr_fields,
    336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    337         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    338         -1,
    339         -1,
    340     },
    341 #endif /* chips */
    342 
    343 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
    344     { /* SOC_REG_INT_BCAST_BLOCK_MASK_HI_64r */
    345         soc_block_list[5],
    346         soc_portreg,
    347         1,
    348         0,
    349         0x40002700,
    350         SOC_REG_FLAG_64_BITS,
    351         0,
    352         5,
    353         soc_BCAST_BLOCK_MASK_HI_64r_fields,
    354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    355         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
    356         -1,
    357         -1,
    358     },
    359 #endif /* chips */
    360 
    361 #if defined(BCM_53570_B0)
    362     { /* SOC_REG_INT_BCAST_BLOCK_MASK_HI_64_BCM53570_B0r */
    363         soc_block_list[5],
    364         soc_portreg,
    365         1,
    366         0,
    367         0x40002b00,
    368         SOC_REG_FLAG_64_BITS,
    369         0,
    370         5,
    371         soc_BCAST_BLOCK_MASK_HI_64r_fields,
    372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    373         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
    374         -1,
    375         -1,
    376     },
    377 #endif /* chips */
    378 
    379 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
    380     { /* SOC_REG_INT_BCAST_BLOCK_MASK_HI_BCM53314_A0r */
    381         soc_block_list[5],
    382         soc_portreg,
    383         1,
    384         0,
    385         0xf000105,
    386         0,
    387         0,
    388         1,
    389         soc_BCAST_BLOCK_MASK_HIr_fields,
    390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    391         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    392         -1,
    393         -1,
    394     },
    395 #endif /* chips */
    396 
    397 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
    398     { /* SOC_REG_INT_BCAST_BLOCK_MASK_LO_64r */
    399         soc_block_list[5],
    400         soc_portreg,
    401         1,
    402         0,
    403         0x40002600,
    404         SOC_REG_FLAG_64_BITS,
    405         0,
    406         4,
    407         soc_BCAST_BLOCK_MASK_LO_64r_fields,
    408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    409         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
    410         -1,
    411         -1,
    412     },
    413 #endif /* chips */
    414 
    415 #if defined(BCM_53570_B0)
    416     { /* SOC_REG_INT_BCAST_BLOCK_MASK_LO_64_BCM53570_B0r */
    417         soc_block_list[5],
    418         soc_portreg,
    419         1,
    420         0,
    421         0x40002a00,
    422         SOC_REG_FLAG_64_BITS,
    423         0,
    424         4,
    425         soc_BCAST_BLOCK_MASK_LO_64r_fields,
    426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    427         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
    428         -1,
    429         -1,
    430     },
    431 #endif /* chips */
    432 
    433 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    434     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    435     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    436     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_CONTROLr */
    437         soc_block_list[5],
    438         soc_genreg,
    439         1,
    440         0,
    441         0xe08028e,
    442         0,
    443         0,
    444         1,
    445         soc_EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr_fields,
    446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    447         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    448         -1,
    449         -1,
    450     },
    451 #endif /* chips */
    452 
    453 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
    454     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_CONTROL_BCM56260_A0r */
    455         soc_block_list[5],
    456         soc_genreg,
    457         1,
    458         0,
    459         0x3e015e00,
    460         0,
    461         0,
    462         1,
    463         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
    464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    466         -1,
    467         -1,
    468     },
    469 #endif /* chips */
    470 
    471 #if defined(BCM_56270_A0)
    472     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_CONTROL_BCM56270_A0r */
    473         soc_block_list[5],
    474         soc_genreg,
    475         1,
    476         0,
    477         0x3e014e00,
    478         0,
    479         0,
    480         1,
    481         soc_L2_USER_ENTRY_DATA_PARITY_CONTROLr_fields,
    482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    484         -1,
    485         -1,
    486     },
    487 #endif /* chips */
    488 
    489 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    490     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_CONTROL_BCM56440_A0r */
    491         soc_block_list[5],
    492         soc_genreg,
    493         1,
    494         0,
    495         0xf080d5d,
    496         0,
    497         0,
    498         1,
    499         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
    500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    502         -1,
    503         -1,
    504     },
    505 #endif /* chips */
    506 
    507 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    508     defined(BCM_56450_B1)
    509     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_CONTROL_BCM56450_A0r */
    510         soc_block_list[5],
    511         soc_genreg,
    512         1,
    513         0,
    514         0x3e015d00,
    515         0,
    516         0,
    517         1,
    518         soc_FT_CNTR_SER_CONTROLr_fields,
    519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    520         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    521         -1,
    522         -1,
    523     },
    524 #endif /* chips */
    525 
    526 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    527     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_CONTROL_BCM56840_A0r */
    528         soc_block_list[5],
    529         soc_genreg,
    530         1,
    531         0,
    532         0xf080d5e,
    533         0,
    534         0,
    535         1,
    536         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr_fields,
    537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    539         -1,
    540         -1,
    541     },
    542 #endif /* chips */
    543 
    544 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    545     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    546     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    547     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr */
    548         soc_block_list[5],
    549         soc_genreg,
    550         1,
    551         0,
    552         0xe08028f,
    553         0,
    554         0,
    555         3,
    556         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
    557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    558         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    559         -1,
    560         -1,
    561     },
    562 #endif /* chips */
    563 
    564 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    565     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56440_A0r */
    566         soc_block_list[5],
    567         soc_genreg,
    568         1,
    569         0,
    570         0xf080d5e,
    571         0,
    572         0,
    573         3,
    574         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
    575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    577         -1,
    578         -1,
    579     },
    580 #endif /* chips */
    581 
    582 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    583     defined(BCM_56450_B1)
    584     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56450_A0r */
    585         soc_block_list[5],
    586         soc_genreg,
    587         1,
    588         0,
    589         0x3e015e00,
    590         0,
    591         0,
    592         3,
    593         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
    594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    595         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    596         -1,
    597         -1,
    598     },
    599 #endif /* chips */
    600 
    601 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    602     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r */
    603         soc_block_list[5],
    604         soc_genreg,
    605         1,
    606         0,
    607         0xf080d5f,
    608         0,
    609         0,
    610         3,
    611         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
    612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    613         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    614         -1,
    615         -1,
    616     },
    617 #endif /* chips */
    618 
    619 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
    620     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
    621     defined(BCM_56685_A0) || defined(BCM_56685_B0)
    622     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_NACKr */
    623         soc_block_list[5],
    624         soc_genreg,
    625         1,
    626         0,
    627         0xe080290,
    628         0,
    629         0,
    630         3,
    631         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTRr_fields,
    632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    633         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
    634         -1,
    635         -1,
    636     },
    637 #endif /* chips */
    638 
    639 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
    640     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56440_A0r */
    641         soc_block_list[5],
    642         soc_genreg,
    643         1,
    644         0,
    645         0xf080d5f,
    646         0,
    647         0,
    648         3,
    649         soc_IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTRr_fields,
    650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    651         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    652         -1,
    653         -1,
    654     },
    655 #endif /* chips */
    656 
    657 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
    658     defined(BCM_56450_B1)
    659     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56450_A0r */
    660         soc_block_list[5],
    661         soc_genreg,
    662         1,
    663         0,
    664         0x3e015f00,
    665         0,
    666         0,
    667         3,
    668         soc_ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR_BCM56450_A0r_fields,
    669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    670         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    671         -1,
    672         -1,
    673     },
    674 #endif /* chips */
    675 
    676 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
    677     { /* SOC_REG_INT_BCAST_BLOCK_MASK_PARITY_STATUS_NACK_BCM56840_A0r */
    678         soc_block_list[5],
    679         soc_genreg,
    680         1,
    681         0,
    682         0xf080d60,
    683         0,
    684         0,
    685         3,
    686         soc_BCAST_BLOCK_MASK_PARITY_STATUS_INTR_BCM56840_A0r_fields,
    687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    688         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    689         -1,
    690         -1,
    691     },
    692 #endif /* chips */
    693 
    694 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
    695     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
    696     defined(BCM_56800_A0)
    697     { /* SOC_REG_INT_BCAST_STORM_CONTROLr */
    698         soc_block_list[5],
    699         soc_portreg,
    700         1,
    701         0,
    702         0xb000001,
    703         0,
    704         0,
    705         2,
    706         soc_BCAST_STORM_CONTROLr_fields,
    707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    708         SOC_RESET_MASK_DEC(0x02000000, 0x00000000)
    709         -1,
    710         -1,
    711     },
    712 #endif /* chips */
    713 
    714 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
    715     defined(BCM_56224_A0) || defined(BCM_56224_B0)
    716     { /* SOC_REG_INT_BCAST_STORM_CONTROL_BCM56224_A0r */
    717         soc_block_list[5],
    718         soc_portreg,
    719         1,
    720         0,
    721         0xc000001,
    722         0,
    723         0,
    724         2,
    725         soc_BCAST_STORM_CONTROLr_fields,
    726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    727         SOC_RESET_MASK_DEC(0x02000000, 0x00000000)
    728         -1,
    729         -1,
    730     },
    731 #endif /* chips */
    732 
    733 #if defined(BCM_88690_A0)
    734     { /* SOC_REG_INT_BDM_BDB_CONFIGr */
    735         soc_block_list[168],
    736         soc_genreg,
    737         1,
    738         0,
    739         0x100,
    740         0,
    741         0,
    742         7,
    743         soc_BDM_BDB_CONFIGr_fields,
    744         SOC_RESET_VAL_DEC(0x00001000, 0x00000000)
    745         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
    746         -1,
    747         -1,
    748     },
    749 #endif /* chips */
    750 
    751 #if defined(BCM_88690_B0)
    752     { /* SOC_REG_INT_BDM_BDB_CONFIG_BCM88690_B0r */
    753         soc_block_list[168],
    754         soc_genreg,
    755         1,
    756         0,
    757         0x100,
    758         0,
    759         0,
    760         7,
    761         soc_BDM_BDB_CONFIG_BCM88690_B0r_fields,
    762         SOC_RESET_VAL_DEC(0x00001000, 0x00000000)
    763         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
    764         -1,
    765         -1,
    766     },
    767 #endif /* chips */
    768 
    769 #if defined(BCM_88690_A0)
    770     { /* SOC_REG_INT_BDM_BDB_STATUSr */
    771         soc_block_list[168],
    772         soc_genreg,
    773         1,
    774         0,
    775         0x101,
    776         SOC_REG_FLAG_RO,
    777         0,
    778         1,
    779         soc_BDM_BDB_STATUSr_fields,
    780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    781         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    782         -1,
    783         -1,
    784     },
    785 #endif /* chips */
    786 
    787 #if defined(BCM_88690_B0)
    788     { /* SOC_REG_INT_BDM_BDB_STATUS_BCM88690_B0r */
    789         soc_block_list[168],
    790         soc_genreg,
    791         1,
    792         0,
    793         0x101,
    794         SOC_REG_FLAG_RO,
    795         0,
    796         1,
    797         soc_BDM_BDB_STATUS_BCM88690_B0r_fields,
    798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    799         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
    800         -1,
    801         -1,
    802     },
    803 #endif /* chips */
    804 
    805 #if defined(BCM_88690_A0)
    806     { /* SOC_REG_INT_BDM_BD_DATA_DEBUGr */
    807         soc_block_list[168],
    808         soc_genreg,
    809         1,
    810         0,
    811         0x104,
    812         SOC_REG_FLAG_ABOVE_64_BITS |
    813                           SOC_REG_FLAG_RO,
    814         SOC_REG_FLAG_COUNTER_FEILDS,
    815         5,
    816         soc_BDM_BD_DATA_DEBUGr_fields,
    817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    818         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    819         -1,
    820         -1,
    821     },
    822 #endif /* chips */
    823 
    824 #if defined(BCM_88690_B0)
    825     { /* SOC_REG_INT_BDM_BD_DATA_DEBUG_BCM88690_B0r */
    826         soc_block_list[168],
    827         soc_genreg,
    828         1,
    829         0,
    830         0x104,
    831         SOC_REG_FLAG_ABOVE_64_BITS |
    832                           SOC_REG_FLAG_RO,
    833         SOC_REG_FLAG_COUNTER_FEILDS,
    834         5,
    835         soc_BDM_BD_DATA_DEBUG_BCM88690_B0r_fields,
    836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
    838         -1,
    839         -1,
    840     },
    841 #endif /* chips */
    842 
    843 #if defined(BCM_88690_A0)
    844     { /* SOC_REG_INT_BDM_ECC_1B_ERR_CNTr */
    845         soc_block_list[168],
    846         soc_genreg,
    847         1,
    848         0,
    849         0x94,
    850         SOC_REG_FLAG_64_BITS |
    851                           SOC_REG_FLAG_RO,
    852         SOC_REG_FLAG_COUNTER_FEILDS |
    853                           SOC_REG_FLAG_INIT_ON_READ,
    854         4,
    855         soc_BDM_ECC_1B_ERR_CNTr_fields,
    856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    857         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    858         -1,
    859         -1,
    860     },
    861 #endif /* chips */
    862 
    863 #if defined(BCM_88690_B0)
    864     { /* SOC_REG_INT_BDM_ECC_1B_ERR_CNT_BCM88690_B0r */
    865         soc_block_list[168],
    866         soc_genreg,
    867         1,
    868         0,
    869         0x94,
    870         SOC_REG_FLAG_64_BITS |
    871                           SOC_REG_FLAG_RO,
    872         SOC_REG_FLAG_COUNTER_FEILDS |
    873                           SOC_REG_FLAG_INIT_ON_READ,
    874         4,
    875         soc_BDM_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
    876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    877         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    878         -1,
    879         -1,
    880     },
    881 #endif /* chips */
    882 
    883 #if defined(BCM_88690_A0)
    884     { /* SOC_REG_INT_BDM_ECC_2B_ERR_CNTr */
    885         soc_block_list[168],
    886         soc_genreg,
    887         1,
    888         0,
    889         0x96,
    890         SOC_REG_FLAG_64_BITS |
    891                           SOC_REG_FLAG_RO,
    892         SOC_REG_FLAG_COUNTER_FEILDS |
    893                           SOC_REG_FLAG_INIT_ON_READ,
    894         4,
    895         soc_BDM_ECC_2B_ERR_CNTr_fields,
    896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    897         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    898         -1,
    899         -1,
    900     },
    901 #endif /* chips */
    902 
    903 #if defined(BCM_88690_B0)
    904     { /* SOC_REG_INT_BDM_ECC_2B_ERR_CNT_BCM88690_B0r */
    905         soc_block_list[168],
    906         soc_genreg,
    907         1,
    908         0,
    909         0x96,
    910         SOC_REG_FLAG_64_BITS |
    911                           SOC_REG_FLAG_RO,
    912         SOC_REG_FLAG_COUNTER_FEILDS |
    913                           SOC_REG_FLAG_INIT_ON_READ,
    914         4,
    915         soc_BDM_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
    916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    917         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
    918         -1,
    919         -1,
    920     },
    921 #endif /* chips */
    922 
    923 #if defined(BCM_88690_A0)
    924     { /* SOC_REG_INT_BDM_ECC_ERR_1B_MONITOR_MEM_MASKr */
    925         soc_block_list[168],
    926         soc_genreg,
    927         1,
    928         0,
    929         0x9a,
    930         0,
    931         0,
    932         20,
    933         soc_BDM_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
    934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    935         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    936         -1,
    937         -1,
    938     },
    939 #endif /* chips */
    940 
    941 #if defined(BCM_88690_B0)
    942     { /* SOC_REG_INT_BDM_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
    943         soc_block_list[168],
    944         soc_genreg,
    945         1,
    946         0,
    947         0x9a,
    948         0,
    949         0,
    950         20,
    951         soc_BDM_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
    952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    953         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    954         -1,
    955         -1,
    956     },
    957 #endif /* chips */
    958 
    959 #if defined(BCM_88690_A0)
    960     { /* SOC_REG_INT_BDM_ECC_ERR_2B_MONITOR_MEM_MASKr */
    961         soc_block_list[168],
    962         soc_genreg,
    963         1,
    964         0,
    965         0x9c,
    966         0,
    967         0,
    968         20,
    969         soc_BDM_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
    970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    971         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    972         -1,
    973         -1,
    974     },
    975 #endif /* chips */
    976 
    977 #if defined(BCM_88690_B0)
    978     { /* SOC_REG_INT_BDM_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
    979         soc_block_list[168],
    980         soc_genreg,
    981         1,
    982         0,
    983         0x9c,
    984         0,
    985         0,
    986         20,
    987         soc_BDM_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
    988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
    989         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
    990         -1,
    991         -1,
    992     },
    993 #endif /* chips */
    994 
    995 #if defined(BCM_88690_A0)
    996     { /* SOC_REG_INT_BDM_ECC_INTERRUPT_REGISTERr */
    997         soc_block_list[168],
    998         soc_genreg,
    999         1,
   1000         0,
   1001         0x7,
   1002         SOC_REG_FLAG_INTERRUPT |
   1003                           SOC_REG_FLAG_SIGNAL,
   1004         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1005         3,
   1006         soc_BDM_ECC_INTERRUPT_REGISTERr_fields,
   1007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1008         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1009         -1,
   1010         -1,
   1011     },
   1012 #endif /* chips */
   1013 
   1014 #if defined(BCM_88690_B0)
   1015     { /* SOC_REG_INT_BDM_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
   1016         soc_block_list[168],
   1017         soc_genreg,
   1018         1,
   1019         0,
   1020         0x7,
   1021         SOC_REG_FLAG_INTERRUPT |
   1022                           SOC_REG_FLAG_SIGNAL,
   1023         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1024         3,
   1025         soc_BDM_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   1026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1027         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1028         -1,
   1029         -1,
   1030     },
   1031 #endif /* chips */
   1032 
   1033 #if defined(BCM_88690_A0)
   1034     { /* SOC_REG_INT_BDM_ECC_INTERRUPT_REGISTER_MASKr */
   1035         soc_block_list[168],
   1036         soc_genreg,
   1037         1,
   1038         0,
   1039         0x17,
   1040         0,
   1041         0,
   1042         3,
   1043         soc_BDM_ECC_INTERRUPT_REGISTER_MASKr_fields,
   1044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1045         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1046         -1,
   1047         -1,
   1048     },
   1049 #endif /* chips */
   1050 
   1051 #if defined(BCM_88690_B0)
   1052     { /* SOC_REG_INT_BDM_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
   1053         soc_block_list[168],
   1054         soc_genreg,
   1055         1,
   1056         0,
   1057         0x17,
   1058         0,
   1059         0,
   1060         3,
   1061         soc_BDM_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
   1062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1063         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1064         -1,
   1065         -1,
   1066     },
   1067 #endif /* chips */
   1068 
   1069 #if defined(BCM_88690_A0)
   1070     { /* SOC_REG_INT_BDM_ECC_INTERRUPT_REGISTER_TESTr */
   1071         soc_block_list[168],
   1072         soc_genreg,
   1073         1,
   1074         0,
   1075         0x1f,
   1076         0,
   1077         0,
   1078         1,
   1079         soc_BDM_ECC_INTERRUPT_REGISTER_TESTr_fields,
   1080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1081         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1082         -1,
   1083         -1,
   1084     },
   1085 #endif /* chips */
   1086 
   1087 #if defined(BCM_88690_B0)
   1088     { /* SOC_REG_INT_BDM_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   1089         soc_block_list[168],
   1090         soc_genreg,
   1091         1,
   1092         0,
   1093         0x1f,
   1094         0,
   1095         0,
   1096         1,
   1097         soc_BDM_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   1098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1099         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1100         -1,
   1101         -1,
   1102     },
   1103 #endif /* chips */
   1104 
   1105 #if defined(BCM_88690_A0)
   1106     { /* SOC_REG_INT_BDM_ERROR_INITIATION_DATAr */
   1107         soc_block_list[168],
   1108         soc_genreg,
   1109         1,
   1110         0,
   1111         0xa3,
   1112         0,
   1113         0,
   1114         1,
   1115         soc_BDM_ERROR_INITIATION_DATAr_fields,
   1116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1117         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   1118         -1,
   1119         -1,
   1120     },
   1121 #endif /* chips */
   1122 
   1123 #if defined(BCM_88690_A0)
   1124     { /* SOC_REG_INT_BDM_FPC_CONFIGr */
   1125         soc_block_list[168],
   1126         soc_genreg,
   1127         1,
   1128         0,
   1129         0x102,
   1130         0,
   1131         0,
   1132         2,
   1133         soc_BDM_FPC_CONFIGr_fields,
   1134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1135         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1136         -1,
   1137         -1,
   1138     },
   1139 #endif /* chips */
   1140 
   1141 #if defined(BCM_88690_B0)
   1142     { /* SOC_REG_INT_BDM_FPC_CONFIG_BCM88690_B0r */
   1143         soc_block_list[168],
   1144         soc_genreg,
   1145         1,
   1146         0,
   1147         0x102,
   1148         0,
   1149         0,
   1150         2,
   1151         soc_BDM_FPC_CONFIG_BCM88690_B0r_fields,
   1152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1153         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   1154         -1,
   1155         -1,
   1156     },
   1157 #endif /* chips */
   1158 
   1159 #if defined(BCM_88690_A0)
   1160     { /* SOC_REG_INT_BDM_FPC_CONTROLr */
   1161         soc_block_list[168],
   1162         soc_genreg,
   1163         4,
   1164         0,
   1165         0x105,
   1166         SOC_REG_FLAG_ARRAY |
   1167                           SOC_REG_FLAG_REG_ARRAY,
   1168         0,
   1169         2,
   1170         soc_BDM_FPC_CONTROLr_fields,
   1171         SOC_RESET_VAL_DEC(0x3fff8000, 0x00000000)
   1172         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   1173         -1,
   1174         -1,
   1175     },
   1176 #endif /* chips */
   1177 
   1178 #if defined(BCM_88690_B0)
   1179     { /* SOC_REG_INT_BDM_FPC_CONTROL_BCM88690_B0r */
   1180         soc_block_list[168],
   1181         soc_genreg,
   1182         4,
   1183         0,
   1184         0x105,
   1185         SOC_REG_FLAG_ARRAY |
   1186                           SOC_REG_FLAG_REG_ARRAY,
   1187         0,
   1188         2,
   1189         soc_BDM_FPC_CONTROL_BCM88690_B0r_fields,
   1190         SOC_RESET_VAL_DEC(0x3fff8000, 0x00000000)
   1191         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   1192         -1,
   1193         -1,
   1194     },
   1195 #endif /* chips */
   1196 
   1197 #if defined(BCM_88690_B0)
   1198     { /* SOC_REG_INT_BDM_FPC_DELETEr */
   1199         soc_block_list[168],
   1200         soc_genreg,
   1201         1,
   1202         0,
   1203         0x111,
   1204         0,
   1205         0,
   1206         2,
   1207         soc_BDM_FPC_DELETEr_fields,
   1208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1209         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
   1210         -1,
   1211         -1,
   1212     },
   1213 #endif /* chips */
   1214 
   1215 #if defined(BCM_88690_A0)
   1216     { /* SOC_REG_INT_BDM_FPC_MODULE_STATUSr */
   1217         soc_block_list[168],
   1218         soc_genreg,
   1219         4,
   1220         0,
   1221         0x109,
   1222         SOC_REG_FLAG_64_BITS |
   1223                           SOC_REG_FLAG_ARRAY |
   1224                           SOC_REG_FLAG_RO |
   1225                           SOC_REG_FLAG_REG_ARRAY,
   1226         SOC_REG_FLAG_INIT_ON_READ,
   1227         4,
   1228         soc_BDM_FPC_MODULE_STATUSr_fields,
   1229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1230         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
   1231         -1,
   1232         -1,
   1233     },
   1234 #endif /* chips */
   1235 
   1236 #if defined(BCM_88690_B0)
   1237     { /* SOC_REG_INT_BDM_FPC_MODULE_STATUS_BCM88690_B0r */
   1238         soc_block_list[168],
   1239         soc_genreg,
   1240         4,
   1241         0,
   1242         0x109,
   1243         SOC_REG_FLAG_64_BITS |
   1244                           SOC_REG_FLAG_ARRAY |
   1245                           SOC_REG_FLAG_RO |
   1246                           SOC_REG_FLAG_REG_ARRAY,
   1247         SOC_REG_FLAG_INIT_ON_READ,
   1248         4,
   1249         soc_BDM_FPC_MODULE_STATUS_BCM88690_B0r_fields,
   1250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1251         SOC_RESET_MASK_DEC(0xffffffff, 0x0001ffff)
   1252         -1,
   1253         -1,
   1254     },
   1255 #endif /* chips */
   1256 
   1257 #if defined(BCM_88690_A0)
   1258     { /* SOC_REG_INT_BDM_FPC_STATUSr */
   1259         soc_block_list[168],
   1260         soc_genreg,
   1261         1,
   1262         0,
   1263         0x103,
   1264         SOC_REG_FLAG_ABOVE_64_BITS |
   1265                           SOC_REG_FLAG_RO,
   1266         SOC_REG_FLAG_COUNTER_FEILDS |
   1267                           SOC_REG_FLAG_INIT_ON_READ,
   1268         11,
   1269         soc_BDM_FPC_STATUSr_fields,
   1270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1271         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1272         -1,
   1273         -1,
   1274     },
   1275 #endif /* chips */
   1276 
   1277 #if defined(BCM_88690_B0)
   1278     { /* SOC_REG_INT_BDM_FPC_STATUS_BCM88690_B0r */
   1279         soc_block_list[168],
   1280         soc_genreg,
   1281         1,
   1282         0,
   1283         0x103,
   1284         SOC_REG_FLAG_ABOVE_64_BITS |
   1285                           SOC_REG_FLAG_RO,
   1286         SOC_REG_FLAG_COUNTER_FEILDS |
   1287                           SOC_REG_FLAG_INIT_ON_READ,
   1288         11,
   1289         soc_BDM_FPC_STATUS_BCM88690_B0r_fields,
   1290         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1291         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   1292         -1,
   1293         -1,
   1294     },
   1295 #endif /* chips */
   1296 
   1297 #if defined(BCM_88690_A0)
   1298     { /* SOC_REG_INT_BDM_GTIMER_CONFIGURATIONr */
   1299         soc_block_list[168],
   1300         soc_genreg,
   1301         1,
   1302         0,
   1303         0x89,
   1304         0,
   1305         0,
   1306         3,
   1307         soc_BDM_GTIMER_CONFIGURATIONr_fields,
   1308         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1309         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1310         -1,
   1311         -1,
   1312     },
   1313 #endif /* chips */
   1314 
   1315 #if defined(BCM_88690_B0)
   1316     { /* SOC_REG_INT_BDM_GTIMER_CONFIGURATION_BCM88690_B0r */
   1317         soc_block_list[168],
   1318         soc_genreg,
   1319         1,
   1320         0,
   1321         0x89,
   1322         0,
   1323         0,
   1324         3,
   1325         soc_BDM_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
   1326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1327         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   1328         -1,
   1329         -1,
   1330     },
   1331 #endif /* chips */
   1332 
   1333 #if defined(BCM_88690_A0)
   1334     { /* SOC_REG_INT_BDM_GTIMER_CYCLEr */
   1335         soc_block_list[168],
   1336         soc_genreg,
   1337         1,
   1338         0,
   1339         0x88,
   1340         0,
   1341         0,
   1342         1,
   1343         soc_BDM_GTIMER_CYCLEr_fields,
   1344         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1346         -1,
   1347         -1,
   1348     },
   1349 #endif /* chips */
   1350 
   1351 #if defined(BCM_88690_B0)
   1352     { /* SOC_REG_INT_BDM_GTIMER_CYCLE_BCM88690_B0r */
   1353         soc_block_list[168],
   1354         soc_genreg,
   1355         1,
   1356         0,
   1357         0x88,
   1358         0,
   1359         0,
   1360         1,
   1361         soc_BDM_GTIMER_CYCLE_BCM88690_B0r_fields,
   1362         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1364         -1,
   1365         -1,
   1366     },
   1367 #endif /* chips */
   1368 
   1369 #if defined(BCM_88690_A0)
   1370     { /* SOC_REG_INT_BDM_INTERRUPT_MASK_REGISTERr */
   1371         soc_block_list[168],
   1372         soc_genreg,
   1373         1,
   1374         0,
   1375         0x10,
   1376         0,
   1377         0,
   1378         5,
   1379         soc_BDM_INTERRUPT_MASK_REGISTERr_fields,
   1380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1381         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1382         -1,
   1383         -1,
   1384     },
   1385 #endif /* chips */
   1386 
   1387 #if defined(BCM_88690_B0)
   1388     { /* SOC_REG_INT_BDM_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
   1389         soc_block_list[168],
   1390         soc_genreg,
   1391         1,
   1392         0,
   1393         0x10,
   1394         0,
   1395         0,
   1396         5,
   1397         soc_BDM_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
   1398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1399         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1400         -1,
   1401         -1,
   1402     },
   1403 #endif /* chips */
   1404 
   1405 #if defined(BCM_88690_A0)
   1406     { /* SOC_REG_INT_BDM_INTERRUPT_REGISTERr */
   1407         soc_block_list[168],
   1408         soc_genreg,
   1409         1,
   1410         0,
   1411         0,
   1412         SOC_REG_FLAG_INTERRUPT |
   1413                           SOC_REG_FLAG_SIGNAL,
   1414         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1415         5,
   1416         soc_BDM_INTERRUPT_REGISTERr_fields,
   1417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1418         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1419         -1,
   1420         -1,
   1421     },
   1422 #endif /* chips */
   1423 
   1424 #if defined(BCM_88690_B0)
   1425     { /* SOC_REG_INT_BDM_INTERRUPT_REGISTER_BCM88690_B0r */
   1426         soc_block_list[168],
   1427         soc_genreg,
   1428         1,
   1429         0,
   1430         0,
   1431         SOC_REG_FLAG_INTERRUPT |
   1432                           SOC_REG_FLAG_SIGNAL,
   1433         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
   1434         5,
   1435         soc_BDM_INTERRUPT_REGISTER_BCM88690_B0r_fields,
   1436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1437         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1438         -1,
   1439         -1,
   1440     },
   1441 #endif /* chips */
   1442 
   1443 #if defined(BCM_88690_A0)
   1444     { /* SOC_REG_INT_BDM_INTERRUPT_REGISTER_TESTr */
   1445         soc_block_list[168],
   1446         soc_genreg,
   1447         1,
   1448         0,
   1449         0x18,
   1450         0,
   1451         0,
   1452         1,
   1453         soc_BDM_INTERRUPT_REGISTER_TESTr_fields,
   1454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1455         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1456         -1,
   1457         -1,
   1458     },
   1459 #endif /* chips */
   1460 
   1461 #if defined(BCM_88690_B0)
   1462     { /* SOC_REG_INT_BDM_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
   1463         soc_block_list[168],
   1464         soc_genreg,
   1465         1,
   1466         0,
   1467         0x18,
   1468         0,
   1469         0,
   1470         1,
   1471         soc_BDM_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
   1472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1473         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   1474         -1,
   1475         -1,
   1476     },
   1477 #endif /* chips */
   1478 
   1479 #if defined(BCM_88690_A0)
   1480     { /* SOC_REG_INT_BDM_PCMI_0r */
   1481         soc_block_list[168],
   1482         soc_genreg,
   1483         1,
   1484         0,
   1485         0xb0,
   1486         0,
   1487         0,
   1488         1,
   1489         soc_BDM_PCMI_0r_fields,
   1490         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1492         -1,
   1493         -1,
   1494     },
   1495 #endif /* chips */
   1496 
   1497 #if defined(BCM_88690_A0)
   1498     { /* SOC_REG_INT_BDM_PCMI_1r */
   1499         soc_block_list[168],
   1500         soc_genreg,
   1501         1,
   1502         0,
   1503         0xb3,
   1504         0,
   1505         0,
   1506         1,
   1507         soc_BDM_PCMI_1r_fields,
   1508         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1509         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1510         -1,
   1511         -1,
   1512     },
   1513 #endif /* chips */
   1514 
   1515 #if defined(BCM_88690_A0)
   1516     { /* SOC_REG_INT_BDM_PCMI_2r */
   1517         soc_block_list[168],
   1518         soc_genreg,
   1519         1,
   1520         0,
   1521         0xb6,
   1522         0,
   1523         0,
   1524         1,
   1525         soc_BDM_PCMI_2r_fields,
   1526         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1528         -1,
   1529         -1,
   1530     },
   1531 #endif /* chips */
   1532 
   1533 #if defined(BCM_88690_A0)
   1534     { /* SOC_REG_INT_BDM_PCMI_3r */
   1535         soc_block_list[168],
   1536         soc_genreg,
   1537         1,
   1538         0,
   1539         0xb9,
   1540         0,
   1541         0,
   1542         1,
   1543         soc_BDM_PCMI_3r_fields,
   1544         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1546         -1,
   1547         -1,
   1548     },
   1549 #endif /* chips */
   1550 
   1551 #if defined(BCM_88690_A0)
   1552     { /* SOC_REG_INT_BDM_PCMI_4r */
   1553         soc_block_list[168],
   1554         soc_genreg,
   1555         1,
   1556         0,
   1557         0xbc,
   1558         0,
   1559         0,
   1560         1,
   1561         soc_BDM_PCMI_4r_fields,
   1562         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1564         -1,
   1565         -1,
   1566     },
   1567 #endif /* chips */
   1568 
   1569 #if defined(BCM_88690_B0)
   1570     { /* SOC_REG_INT_BDM_PCMI_0_BCM88690_B0r */
   1571         soc_block_list[168],
   1572         soc_genreg,
   1573         1,
   1574         0,
   1575         0xb0,
   1576         0,
   1577         0,
   1578         1,
   1579         soc_BDM_PCMI_0_BCM88690_B0r_fields,
   1580         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1582         -1,
   1583         -1,
   1584     },
   1585 #endif /* chips */
   1586 
   1587 #if defined(BCM_88690_A0)
   1588     { /* SOC_REG_INT_BDM_PCMI_0_Sr */
   1589         soc_block_list[168],
   1590         soc_genreg,
   1591         1,
   1592         0,
   1593         0xb1,
   1594         SOC_REG_FLAG_RO,
   1595         0,
   1596         3,
   1597         soc_BDM_PCMI_0_Sr_fields,
   1598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1600         -1,
   1601         -1,
   1602     },
   1603 #endif /* chips */
   1604 
   1605 #if defined(BCM_88690_B0)
   1606     { /* SOC_REG_INT_BDM_PCMI_0_S_BCM88690_B0r */
   1607         soc_block_list[168],
   1608         soc_genreg,
   1609         1,
   1610         0,
   1611         0xb1,
   1612         SOC_REG_FLAG_RO,
   1613         0,
   1614         3,
   1615         soc_BDM_PCMI_0_S_BCM88690_B0r_fields,
   1616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1618         -1,
   1619         -1,
   1620     },
   1621 #endif /* chips */
   1622 
   1623 #if defined(BCM_88690_A0)
   1624     { /* SOC_REG_INT_BDM_PCMI_0_Tr */
   1625         soc_block_list[168],
   1626         soc_genreg,
   1627         1,
   1628         0,
   1629         0xb2,
   1630         0,
   1631         0,
   1632         2,
   1633         soc_BDM_PCMI_0_Tr_fields,
   1634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1635         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1636         -1,
   1637         -1,
   1638     },
   1639 #endif /* chips */
   1640 
   1641 #if defined(BCM_88690_B0)
   1642     { /* SOC_REG_INT_BDM_PCMI_0_T_BCM88690_B0r */
   1643         soc_block_list[168],
   1644         soc_genreg,
   1645         1,
   1646         0,
   1647         0xb2,
   1648         0,
   1649         0,
   1650         2,
   1651         soc_BDM_PCMI_0_T_BCM88690_B0r_fields,
   1652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1653         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1654         -1,
   1655         -1,
   1656     },
   1657 #endif /* chips */
   1658 
   1659 #if defined(BCM_88690_B0)
   1660     { /* SOC_REG_INT_BDM_PCMI_1_BCM88690_B0r */
   1661         soc_block_list[168],
   1662         soc_genreg,
   1663         1,
   1664         0,
   1665         0xb3,
   1666         0,
   1667         0,
   1668         1,
   1669         soc_BDM_PCMI_1_BCM88690_B0r_fields,
   1670         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1672         -1,
   1673         -1,
   1674     },
   1675 #endif /* chips */
   1676 
   1677 #if defined(BCM_88690_A0)
   1678     { /* SOC_REG_INT_BDM_PCMI_1_Sr */
   1679         soc_block_list[168],
   1680         soc_genreg,
   1681         1,
   1682         0,
   1683         0xb4,
   1684         SOC_REG_FLAG_RO,
   1685         0,
   1686         3,
   1687         soc_BDM_PCMI_1_Sr_fields,
   1688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1690         -1,
   1691         -1,
   1692     },
   1693 #endif /* chips */
   1694 
   1695 #if defined(BCM_88690_B0)
   1696     { /* SOC_REG_INT_BDM_PCMI_1_S_BCM88690_B0r */
   1697         soc_block_list[168],
   1698         soc_genreg,
   1699         1,
   1700         0,
   1701         0xb4,
   1702         SOC_REG_FLAG_RO,
   1703         0,
   1704         3,
   1705         soc_BDM_PCMI_1_S_BCM88690_B0r_fields,
   1706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1708         -1,
   1709         -1,
   1710     },
   1711 #endif /* chips */
   1712 
   1713 #if defined(BCM_88690_A0)
   1714     { /* SOC_REG_INT_BDM_PCMI_1_Tr */
   1715         soc_block_list[168],
   1716         soc_genreg,
   1717         1,
   1718         0,
   1719         0xb5,
   1720         0,
   1721         0,
   1722         2,
   1723         soc_BDM_PCMI_1_Tr_fields,
   1724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1725         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1726         -1,
   1727         -1,
   1728     },
   1729 #endif /* chips */
   1730 
   1731 #if defined(BCM_88690_B0)
   1732     { /* SOC_REG_INT_BDM_PCMI_1_T_BCM88690_B0r */
   1733         soc_block_list[168],
   1734         soc_genreg,
   1735         1,
   1736         0,
   1737         0xb5,
   1738         0,
   1739         0,
   1740         2,
   1741         soc_BDM_PCMI_1_T_BCM88690_B0r_fields,
   1742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1743         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1744         -1,
   1745         -1,
   1746     },
   1747 #endif /* chips */
   1748 
   1749 #if defined(BCM_88690_B0)
   1750     { /* SOC_REG_INT_BDM_PCMI_2_BCM88690_B0r */
   1751         soc_block_list[168],
   1752         soc_genreg,
   1753         1,
   1754         0,
   1755         0xb6,
   1756         0,
   1757         0,
   1758         1,
   1759         soc_BDM_PCMI_2_BCM88690_B0r_fields,
   1760         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1762         -1,
   1763         -1,
   1764     },
   1765 #endif /* chips */
   1766 
   1767 #if defined(BCM_88690_A0)
   1768     { /* SOC_REG_INT_BDM_PCMI_2_Sr */
   1769         soc_block_list[168],
   1770         soc_genreg,
   1771         1,
   1772         0,
   1773         0xb7,
   1774         SOC_REG_FLAG_RO,
   1775         0,
   1776         3,
   1777         soc_BDM_PCMI_2_Sr_fields,
   1778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1779         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1780         -1,
   1781         -1,
   1782     },
   1783 #endif /* chips */
   1784 
   1785 #if defined(BCM_88690_B0)
   1786     { /* SOC_REG_INT_BDM_PCMI_2_S_BCM88690_B0r */
   1787         soc_block_list[168],
   1788         soc_genreg,
   1789         1,
   1790         0,
   1791         0xb7,
   1792         SOC_REG_FLAG_RO,
   1793         0,
   1794         3,
   1795         soc_BDM_PCMI_2_S_BCM88690_B0r_fields,
   1796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1798         -1,
   1799         -1,
   1800     },
   1801 #endif /* chips */
   1802 
   1803 #if defined(BCM_88690_A0)
   1804     { /* SOC_REG_INT_BDM_PCMI_2_Tr */
   1805         soc_block_list[168],
   1806         soc_genreg,
   1807         1,
   1808         0,
   1809         0xb8,
   1810         0,
   1811         0,
   1812         2,
   1813         soc_BDM_PCMI_2_Tr_fields,
   1814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1815         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1816         -1,
   1817         -1,
   1818     },
   1819 #endif /* chips */
   1820 
   1821 #if defined(BCM_88690_B0)
   1822     { /* SOC_REG_INT_BDM_PCMI_2_T_BCM88690_B0r */
   1823         soc_block_list[168],
   1824         soc_genreg,
   1825         1,
   1826         0,
   1827         0xb8,
   1828         0,
   1829         0,
   1830         2,
   1831         soc_BDM_PCMI_2_T_BCM88690_B0r_fields,
   1832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1833         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1834         -1,
   1835         -1,
   1836     },
   1837 #endif /* chips */
   1838 
   1839 #if defined(BCM_88690_B0)
   1840     { /* SOC_REG_INT_BDM_PCMI_3_BCM88690_B0r */
   1841         soc_block_list[168],
   1842         soc_genreg,
   1843         1,
   1844         0,
   1845         0xb9,
   1846         0,
   1847         0,
   1848         1,
   1849         soc_BDM_PCMI_3_BCM88690_B0r_fields,
   1850         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1852         -1,
   1853         -1,
   1854     },
   1855 #endif /* chips */
   1856 
   1857 #if defined(BCM_88690_A0)
   1858     { /* SOC_REG_INT_BDM_PCMI_3_Sr */
   1859         soc_block_list[168],
   1860         soc_genreg,
   1861         1,
   1862         0,
   1863         0xba,
   1864         SOC_REG_FLAG_RO,
   1865         0,
   1866         3,
   1867         soc_BDM_PCMI_3_Sr_fields,
   1868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1870         -1,
   1871         -1,
   1872     },
   1873 #endif /* chips */
   1874 
   1875 #if defined(BCM_88690_B0)
   1876     { /* SOC_REG_INT_BDM_PCMI_3_S_BCM88690_B0r */
   1877         soc_block_list[168],
   1878         soc_genreg,
   1879         1,
   1880         0,
   1881         0xba,
   1882         SOC_REG_FLAG_RO,
   1883         0,
   1884         3,
   1885         soc_BDM_PCMI_3_S_BCM88690_B0r_fields,
   1886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1887         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1888         -1,
   1889         -1,
   1890     },
   1891 #endif /* chips */
   1892 
   1893 #if defined(BCM_88690_A0)
   1894     { /* SOC_REG_INT_BDM_PCMI_3_Tr */
   1895         soc_block_list[168],
   1896         soc_genreg,
   1897         1,
   1898         0,
   1899         0xbb,
   1900         0,
   1901         0,
   1902         2,
   1903         soc_BDM_PCMI_3_Tr_fields,
   1904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1905         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1906         -1,
   1907         -1,
   1908     },
   1909 #endif /* chips */
   1910 
   1911 #if defined(BCM_88690_B0)
   1912     { /* SOC_REG_INT_BDM_PCMI_3_T_BCM88690_B0r */
   1913         soc_block_list[168],
   1914         soc_genreg,
   1915         1,
   1916         0,
   1917         0xbb,
   1918         0,
   1919         0,
   1920         2,
   1921         soc_BDM_PCMI_3_T_BCM88690_B0r_fields,
   1922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1923         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1924         -1,
   1925         -1,
   1926     },
   1927 #endif /* chips */
   1928 
   1929 #if defined(BCM_88690_B0)
   1930     { /* SOC_REG_INT_BDM_PCMI_4_BCM88690_B0r */
   1931         soc_block_list[168],
   1932         soc_genreg,
   1933         1,
   1934         0,
   1935         0xbc,
   1936         0,
   1937         0,
   1938         1,
   1939         soc_BDM_PCMI_4_BCM88690_B0r_fields,
   1940         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
   1941         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1942         -1,
   1943         -1,
   1944     },
   1945 #endif /* chips */
   1946 
   1947 #if defined(BCM_88690_A0)
   1948     { /* SOC_REG_INT_BDM_PCMI_4_Sr */
   1949         soc_block_list[168],
   1950         soc_genreg,
   1951         1,
   1952         0,
   1953         0xbd,
   1954         SOC_REG_FLAG_RO,
   1955         0,
   1956         3,
   1957         soc_BDM_PCMI_4_Sr_fields,
   1958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1959         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1960         -1,
   1961         -1,
   1962     },
   1963 #endif /* chips */
   1964 
   1965 #if defined(BCM_88690_B0)
   1966     { /* SOC_REG_INT_BDM_PCMI_4_S_BCM88690_B0r */
   1967         soc_block_list[168],
   1968         soc_genreg,
   1969         1,
   1970         0,
   1971         0xbd,
   1972         SOC_REG_FLAG_RO,
   1973         0,
   1974         3,
   1975         soc_BDM_PCMI_4_S_BCM88690_B0r_fields,
   1976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1977         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   1978         -1,
   1979         -1,
   1980     },
   1981 #endif /* chips */
   1982 
   1983 #if defined(BCM_88690_A0)
   1984     { /* SOC_REG_INT_BDM_PCMI_4_Tr */
   1985         soc_block_list[168],
   1986         soc_genreg,
   1987         1,
   1988         0,
   1989         0xbe,
   1990         0,
   1991         0,
   1992         2,
   1993         soc_BDM_PCMI_4_Tr_fields,
   1994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   1995         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   1996         -1,
   1997         -1,
   1998     },
   1999 #endif /* chips */
   2000 
   2001 #if defined(BCM_88690_B0)
   2002     { /* SOC_REG_INT_BDM_PCMI_4_T_BCM88690_B0r */
   2003         soc_block_list[168],
   2004         soc_genreg,
   2005         1,
   2006         0,
   2007         0xbe,
   2008         0,
   2009         0,
   2010         2,
   2011         soc_BDM_PCMI_4_T_BCM88690_B0r_fields,
   2012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2013         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   2014         -1,
   2015         -1,
   2016     },
   2017 #endif /* chips */
   2018 
   2019 #if defined(BCM_88690_A0)
   2020     { /* SOC_REG_INT_BDM_REG_00A4r */
   2021         soc_block_list[168],
   2022         soc_genreg,
   2023         1,
   2024         0,
   2025         0xa4,
   2026         0,
   2027         0,
   2028         20,
   2029         soc_BDM_REG_00A4r_fields,
   2030         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2031         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   2032         -1,
   2033         -1,
   2034     },
   2035 #endif /* chips */
   2036 
   2037 #if defined(BCM_88690_A0)
   2038     { /* SOC_REG_INT_BDM_REG_00A6r */
   2039         soc_block_list[168],
   2040         soc_genreg,
   2041         1,
   2042         0,
   2043         0xa6,
   2044         0,
   2045         0,
   2046         20,
   2047         soc_BDM_REG_00A6r_fields,
   2048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2049         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   2050         -1,
   2051         -1,
   2052     },
   2053 #endif /* chips */
   2054 
   2055 #if defined(BCM_88690_A0)
   2056     { /* SOC_REG_INT_BDM_REG_00C2r */
   2057         soc_block_list[168],
   2058         soc_genreg,
   2059         1,
   2060         0,
   2061         0xc2,
   2062         0,
   2063         0,
   2064         6,
   2065         soc_BDM_REG_00C2r_fields,
   2066         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   2067         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2068         -1,
   2069         -1,
   2070     },
   2071 #endif /* chips */
   2072 
   2073 #if defined(BCM_88690_B0)
   2074     { /* SOC_REG_INT_BDM_REG_00C2_BCM88690_B0r */
   2075         soc_block_list[168],
   2076         soc_genreg,
   2077         1,
   2078         0,
   2079         0xc2,
   2080         0,
   2081         0,
   2082         6,
   2083         soc_BDM_REG_00C2_BCM88690_B0r_fields,
   2084         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   2085         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2086         -1,
   2087         -1,
   2088     },
   2089 #endif /* chips */
   2090 
   2091 #if defined(BCM_88690_A0)
   2092     { /* SOC_REG_INT_BDM_RESERVED_MIRROR_ADDRr */
   2093         soc_block_list[168],
   2094         soc_genreg,
   2095         1,
   2096         0,
   2097         0x85,
   2098         0,
   2099         0,
   2100         2,
   2101         soc_BDM_RESERVED_MIRROR_ADDRr_fields,
   2102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2103         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   2104         -1,
   2105         -1,
   2106     },
   2107 #endif /* chips */
   2108 
   2109 #if defined(BCM_88690_B0)
   2110     { /* SOC_REG_INT_BDM_RESERVED_MIRROR_ADDR_BCM88690_B0r */
   2111         soc_block_list[168],
   2112         soc_genreg,
   2113         1,
   2114         0,
   2115         0x85,
   2116         0,
   2117         0,
   2118         2,
   2119         soc_BDM_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
   2120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2121         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   2122         -1,
   2123         -1,
   2124     },
   2125 #endif /* chips */
   2126 
   2127 #if defined(BCM_88690_A0)
   2128     { /* SOC_REG_INT_BDM_RESERVED_MTCDr */
   2129         soc_block_list[168],
   2130         soc_genreg,
   2131         1,
   2132         0,
   2133         0xae,
   2134         0,
   2135         0,
   2136         6,
   2137         soc_BDM_RESERVED_MTCDr_fields,
   2138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2139         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2140         -1,
   2141         -1,
   2142     },
   2143 #endif /* chips */
   2144 
   2145 #if defined(BCM_88690_B0)
   2146     { /* SOC_REG_INT_BDM_RESERVED_MTCD_BCM88690_B0r */
   2147         soc_block_list[168],
   2148         soc_genreg,
   2149         1,
   2150         0,
   2151         0xae,
   2152         0,
   2153         0,
   2154         6,
   2155         soc_BDM_RESERVED_MTCD_BCM88690_B0r_fields,
   2156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2157         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   2158         -1,
   2159         -1,
   2160     },
   2161 #endif /* chips */
   2162 
   2163 #if defined(BCM_88690_A0)
   2164     { /* SOC_REG_INT_BDM_RESERVED_MTCPr */
   2165         soc_block_list[168],
   2166         soc_genreg,
   2167         1,
   2168         0,
   2169         0xad,
   2170         SOC_REG_FLAG_64_BITS,
   2171         0,
   2172         17,
   2173         soc_BDM_RESERVED_MTCPr_fields,
   2174         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   2175         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   2176         -1,
   2177         -1,
   2178     },
   2179 #endif /* chips */
   2180 
   2181 #if defined(BCM_88690_B0)
   2182     { /* SOC_REG_INT_BDM_RESERVED_MTCP_BCM88690_B0r */
   2183         soc_block_list[168],
   2184         soc_genreg,
   2185         1,
   2186         0,
   2187         0xad,
   2188         SOC_REG_FLAG_64_BITS,
   2189         0,
   2190         17,
   2191         soc_BDM_RESERVED_MTCP_BCM88690_B0r_fields,
   2192         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   2193         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   2194         -1,
   2195         -1,
   2196     },
   2197 #endif /* chips */
   2198 
   2199 #if defined(BCM_88690_A0)
   2200     { /* SOC_REG_INT_BDM_RESERVED_SPARE_0r */
   2201         soc_block_list[168],
   2202         soc_genreg,
   2203         1,
   2204         0,
   2205         0x90,
   2206         0,
   2207         0,
   2208         1,
   2209         soc_BDM_RESERVED_SPARE_0r_fields,
   2210         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   2211         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2212         -1,
   2213         -1,
   2214     },
   2215 #endif /* chips */
   2216 
   2217 #if defined(BCM_88690_A0)
   2218     { /* SOC_REG_INT_BDM_RESERVED_SPARE_1r */
   2219         soc_block_list[168],
   2220         soc_genreg,
   2221         1,
   2222         0,
   2223         0x91,
   2224         0,
   2225         0,
   2226         1,
   2227         soc_BDM_RESERVED_SPARE_1r_fields,
   2228         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   2229         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2230         -1,
   2231         -1,
   2232     },
   2233 #endif /* chips */
   2234 
   2235 #if defined(BCM_88690_A0)
   2236     { /* SOC_REG_INT_BDM_RESERVED_SPARE_2r */
   2237         soc_block_list[168],
   2238         soc_genreg,
   2239         1,
   2240         0,
   2241         0x92,
   2242         0,
   2243         0,
   2244         1,
   2245         soc_BDM_RESERVED_SPARE_2r_fields,
   2246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2247         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2248         -1,
   2249         -1,
   2250     },
   2251 #endif /* chips */
   2252 
   2253 #if defined(BCM_88690_A0)
   2254     { /* SOC_REG_INT_BDM_RESERVED_SPARE_3r */
   2255         soc_block_list[168],
   2256         soc_genreg,
   2257         1,
   2258         0,
   2259         0x93,
   2260         0,
   2261         0,
   2262         1,
   2263         soc_BDM_RESERVED_SPARE_3r_fields,
   2264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2266         -1,
   2267         -1,
   2268     },
   2269 #endif /* chips */
   2270 
   2271 #if defined(BCM_88690_B0)
   2272     { /* SOC_REG_INT_BDM_RESERVED_SPARE_0_BCM88690_B0r */
   2273         soc_block_list[168],
   2274         soc_genreg,
   2275         1,
   2276         0,
   2277         0x90,
   2278         0,
   2279         0,
   2280         1,
   2281         soc_BDM_RESERVED_SPARE_0_BCM88690_B0r_fields,
   2282         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   2283         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2284         -1,
   2285         -1,
   2286     },
   2287 #endif /* chips */
   2288 
   2289 #if defined(BCM_88690_B0)
   2290     { /* SOC_REG_INT_BDM_RESERVED_SPARE_1_BCM88690_B0r */
   2291         soc_block_list[168],
   2292         soc_genreg,
   2293         1,
   2294         0,
   2295         0x91,
   2296         0,
   2297         0,
   2298         1,
   2299         soc_BDM_RESERVED_SPARE_1_BCM88690_B0r_fields,
   2300         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   2301         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2302         -1,
   2303         -1,
   2304     },
   2305 #endif /* chips */
   2306 
   2307 #if defined(BCM_88690_B0)
   2308     { /* SOC_REG_INT_BDM_RESERVED_SPARE_2_BCM88690_B0r */
   2309         soc_block_list[168],
   2310         soc_genreg,
   2311         1,
   2312         0,
   2313         0x92,
   2314         0,
   2315         0,
   2316         1,
   2317         soc_BDM_RESERVED_SPARE_2_BCM88690_B0r_fields,
   2318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2319         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2320         -1,
   2321         -1,
   2322     },
   2323 #endif /* chips */
   2324 
   2325 #if defined(BCM_88690_B0)
   2326     { /* SOC_REG_INT_BDM_RESERVED_SPARE_3_BCM88690_B0r */
   2327         soc_block_list[168],
   2328         soc_genreg,
   2329         1,
   2330         0,
   2331         0x93,
   2332         0,
   2333         0,
   2334         1,
   2335         soc_BDM_RESERVED_SPARE_3_BCM88690_B0r_fields,
   2336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2337         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2338         -1,
   2339         -1,
   2340     },
   2341 #endif /* chips */
   2342 
   2343 #if defined(BCM_88690_A0)
   2344     { /* SOC_REG_INT_BDM_SBUS_BROADCAST_IDr */
   2345         soc_block_list[168],
   2346         soc_genreg,
   2347         1,
   2348         0,
   2349         0x86,
   2350         0,
   2351         0,
   2352         1,
   2353         soc_BDM_SBUS_BROADCAST_IDr_fields,
   2354         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   2355         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   2356         -1,
   2357         -1,
   2358     },
   2359 #endif /* chips */
   2360 
   2361 #if defined(BCM_88690_B0)
   2362     { /* SOC_REG_INT_BDM_SBUS_BROADCAST_ID_BCM88690_B0r */
   2363         soc_block_list[168],
   2364         soc_genreg,
   2365         1,
   2366         0,
   2367         0x86,
   2368         0,
   2369         0,
   2370         1,
   2371         soc_BDM_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
   2372         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
   2373         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   2374         -1,
   2375         -1,
   2376     },
   2377 #endif /* chips */
   2378 
   2379 #if defined(BCM_88690_A0)
   2380     { /* SOC_REG_INT_BDM_SBUS_LAST_IN_CHAINr */
   2381         soc_block_list[168],
   2382         soc_genreg,
   2383         1,
   2384         0,
   2385         0x87,
   2386         0,
   2387         0,
   2388         1,
   2389         soc_BDM_SBUS_LAST_IN_CHAINr_fields,
   2390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2391         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2392         -1,
   2393         -1,
   2394     },
   2395 #endif /* chips */
   2396 
   2397 #if defined(BCM_88690_B0)
   2398     { /* SOC_REG_INT_BDM_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
   2399         soc_block_list[168],
   2400         soc_genreg,
   2401         1,
   2402         0,
   2403         0x87,
   2404         0,
   2405         0,
   2406         1,
   2407         soc_BDM_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
   2408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2409         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   2410         -1,
   2411         -1,
   2412     },
   2413 #endif /* chips */
   2414 
   2415 #if defined(BCM_88690_B0)
   2416     { /* SOC_REG_INT_BDM_SPECIAL_CLOCK_CONTROLSr */
   2417         soc_block_list[168],
   2418         soc_genreg,
   2419         1,
   2420         0,
   2421         0xc1,
   2422         0,
   2423         0,
   2424         1,
   2425         soc_BDM_SPECIAL_CLOCK_CONTROLSr_fields,
   2426         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   2427         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
   2428         -1,
   2429         -1,
   2430     },
   2431 #endif /* chips */
   2432 
   2433 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2434     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0r */
   2435         soc_block_list[5],
   2436         soc_genreg,
   2437         1,
   2438         0,
   2439         0x5080606,
   2440         0,
   2441         0,
   2442         2,
   2443         soc_BFD_RX_ACH_TYPE_CONTROL0r_fields,
   2444         SOC_RESET_VAL_DEC(0x00210057, 0x00000000)
   2445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2446         -1,
   2447         -1,
   2448     },
   2449 #endif /* chips */
   2450 
   2451 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2452     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1r */
   2453         soc_block_list[5],
   2454         soc_genreg,
   2455         1,
   2456         0,
   2457         0x5080607,
   2458         0,
   2459         0,
   2460         1,
   2461         soc_BFD_RX_ACH_TYPE_CONTROL1r_fields,
   2462         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2463         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2464         -1,
   2465         -1,
   2466     },
   2467 #endif /* chips */
   2468 
   2469 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2470     defined(BCM_56450_B1)
   2471     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0_BCM56450_A0r */
   2472         soc_block_list[5],
   2473         soc_genreg,
   2474         1,
   2475         0,
   2476         0x16000600,
   2477         0,
   2478         0,
   2479         2,
   2480         soc_BFD_RX_ACH_TYPE_CONTROL0_BCM56450_A0r_fields,
   2481         SOC_RESET_VAL_DEC(0x00210057, 0x00000000)
   2482         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2483         -1,
   2484         -1,
   2485     },
   2486 #endif /* chips */
   2487 
   2488 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   2489     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2490     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0_BCM56560_A0r */
   2491         soc_block_list[5],
   2492         soc_genreg,
   2493         1,
   2494         0,
   2495         0x16004a00,
   2496         0,
   2497         0,
   2498         2,
   2499         soc_BFD_RX_ACH_TYPE_CONTROL0_BCM56960_A0r_fields,
   2500         SOC_RESET_VAL_DEC(0x00570021, 0x00000000)
   2501         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2502         -1,
   2503         -1,
   2504     },
   2505 #endif /* chips */
   2506 
   2507 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2508     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0_BCM56640_A0r */
   2509         soc_block_list[5],
   2510         soc_genreg,
   2511         1,
   2512         0,
   2513         0x16002a00,
   2514         0,
   2515         0,
   2516         2,
   2517         soc_BFD_RX_ACH_TYPE_CONTROL0_BCM56640_A0r_fields,
   2518         SOC_RESET_VAL_DEC(0x00570021, 0x00000000)
   2519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2520         -1,
   2521         -1,
   2522     },
   2523 #endif /* chips */
   2524 
   2525 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   2526     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0_BCM56850_A0r */
   2527         soc_block_list[5],
   2528         soc_genreg,
   2529         1,
   2530         0,
   2531         0x16004a00,
   2532         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2533         0,
   2534         2,
   2535         soc_BFD_RX_ACH_TYPE_CONTROL0_BCM56640_A0r_fields,
   2536         SOC_RESET_VAL_DEC(0x00570021, 0x00000000)
   2537         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2538         -1,
   2539         -1,
   2540     },
   2541 #endif /* chips */
   2542 
   2543 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2544     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0_BCM56960_A0r */
   2545         soc_block_list[5],
   2546         soc_genreg,
   2547         1,
   2548         0,
   2549         0x36000b00,
   2550         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2551         0,
   2552         2,
   2553         soc_BFD_RX_ACH_TYPE_CONTROL0_BCM56960_A0r_fields,
   2554         SOC_RESET_VAL_DEC(0x00570021, 0x00000000)
   2555         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2556         -1,
   2557         -1,
   2558         0,
   2559     },
   2560 #endif /* chips */
   2561 
   2562 #if defined(BCM_56970_A0)
   2563     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0_BCM56970_A0r */
   2564         soc_block_list[5],
   2565         soc_genreg,
   2566         1,
   2567         0,
   2568         0x5a000a00,
   2569         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2570         0,
   2571         2,
   2572         soc_BFD_RX_ACH_TYPE_CONTROL0_BCM56960_A0r_fields,
   2573         SOC_RESET_VAL_DEC(0x00570021, 0x00000000)
   2574         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2575         -1,
   2576         -1,
   2577         0,
   2578     },
   2579 #endif /* chips */
   2580 
   2581 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2582     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL0_BCM56980_A0r */
   2583         soc_block_list[5],
   2584         soc_genreg,
   2585         1,
   2586         0,
   2587         0x6000400,
   2588         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2589         0,
   2590         2,
   2591         soc_BFD_RX_ACH_TYPE_CONTROL0_BCM56960_A0r_fields,
   2592         SOC_RESET_VAL_DEC(0x00570021, 0x00000000)
   2593         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2594         -1,
   2595         -1,
   2596         3,
   2597     },
   2598 #endif /* chips */
   2599 
   2600 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2601     defined(BCM_56450_B1)
   2602     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1_BCM56450_A0r */
   2603         soc_block_list[5],
   2604         soc_genreg,
   2605         1,
   2606         0,
   2607         0x16000700,
   2608         0,
   2609         0,
   2610         1,
   2611         soc_BFD_RX_ACH_TYPE_CONTROL1_BCM56640_A0r_fields,
   2612         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2613         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2614         -1,
   2615         -1,
   2616     },
   2617 #endif /* chips */
   2618 
   2619 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   2620     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2621     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1_BCM56560_A0r */
   2622         soc_block_list[5],
   2623         soc_genreg,
   2624         1,
   2625         0,
   2626         0x16004b00,
   2627         0,
   2628         0,
   2629         1,
   2630         soc_BFD_RX_ACH_TYPE_CONTROL1_BCM56960_A0r_fields,
   2631         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2632         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2633         -1,
   2634         -1,
   2635     },
   2636 #endif /* chips */
   2637 
   2638 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2639     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1_BCM56640_A0r */
   2640         soc_block_list[5],
   2641         soc_genreg,
   2642         1,
   2643         0,
   2644         0x16002b00,
   2645         0,
   2646         0,
   2647         1,
   2648         soc_BFD_RX_ACH_TYPE_CONTROL1_BCM56640_A0r_fields,
   2649         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2650         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2651         -1,
   2652         -1,
   2653     },
   2654 #endif /* chips */
   2655 
   2656 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   2657     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1_BCM56850_A0r */
   2658         soc_block_list[5],
   2659         soc_genreg,
   2660         1,
   2661         0,
   2662         0x16004b00,
   2663         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2664         0,
   2665         1,
   2666         soc_BFD_RX_ACH_TYPE_CONTROL1_BCM56640_A0r_fields,
   2667         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2668         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2669         -1,
   2670         -1,
   2671     },
   2672 #endif /* chips */
   2673 
   2674 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2675     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1_BCM56960_A0r */
   2676         soc_block_list[5],
   2677         soc_genreg,
   2678         1,
   2679         0,
   2680         0x36000c00,
   2681         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2682         0,
   2683         1,
   2684         soc_BFD_RX_ACH_TYPE_CONTROL1_BCM56960_A0r_fields,
   2685         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2686         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2687         -1,
   2688         -1,
   2689         0,
   2690     },
   2691 #endif /* chips */
   2692 
   2693 #if defined(BCM_56970_A0)
   2694     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1_BCM56970_A0r */
   2695         soc_block_list[5],
   2696         soc_genreg,
   2697         1,
   2698         0,
   2699         0x5a000b00,
   2700         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2701         0,
   2702         1,
   2703         soc_BFD_RX_ACH_TYPE_CONTROL1_BCM56960_A0r_fields,
   2704         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2705         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2706         -1,
   2707         -1,
   2708         0,
   2709     },
   2710 #endif /* chips */
   2711 
   2712 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2713     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_CONTROL1_BCM56980_A0r */
   2714         soc_block_list[5],
   2715         soc_genreg,
   2716         1,
   2717         0,
   2718         0x6000500,
   2719         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2720         0,
   2721         1,
   2722         soc_BFD_RX_ACH_TYPE_CONTROL1_BCM56960_A0r_fields,
   2723         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
   2724         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2725         -1,
   2726         -1,
   2727         3,
   2728     },
   2729 #endif /* chips */
   2730 
   2731 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   2732     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTPr */
   2733         soc_block_list[5],
   2734         soc_genreg,
   2735         1,
   2736         0,
   2737         0x5080608,
   2738         0,
   2739         0,
   2740         2,
   2741         soc_BFD_RX_ACH_TYPE_MPLSTPr_fields,
   2742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2744         -1,
   2745         -1,
   2746     },
   2747 #endif /* chips */
   2748 
   2749 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2750     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP1r */
   2751         soc_block_list[5],
   2752         soc_genreg,
   2753         1,
   2754         0,
   2755         0x16003000,
   2756         SOC_REG_FLAG_64_BITS,
   2757         0,
   2758         1,
   2759         soc_BFD_RX_ACH_TYPE_MPLSTP1r_fields,
   2760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2761         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2762         -1,
   2763         -1,
   2764     },
   2765 #endif /* chips */
   2766 
   2767 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2768     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP1_32r */
   2769         soc_block_list[5],
   2770         soc_genreg,
   2771         1,
   2772         0,
   2773         0x36000e00,
   2774         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2775         0,
   2776         1,
   2777         soc_BFD_RX_ACH_TYPE_MPLSTP1_32r_fields,
   2778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2779         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2780         -1,
   2781         -1,
   2782         0,
   2783     },
   2784 #endif /* chips */
   2785 
   2786 #if defined(BCM_56970_A0)
   2787     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP1_32_BCM56970_A0r */
   2788         soc_block_list[5],
   2789         soc_genreg,
   2790         1,
   2791         0,
   2792         0x5a000d00,
   2793         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2794         0,
   2795         1,
   2796         soc_BFD_RX_ACH_TYPE_MPLSTP1_32r_fields,
   2797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2798         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2799         -1,
   2800         -1,
   2801         0,
   2802     },
   2803 #endif /* chips */
   2804 
   2805 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2806     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP1_32_BCM56980_A0r */
   2807         soc_block_list[5],
   2808         soc_genreg,
   2809         1,
   2810         0,
   2811         0x6000700,
   2812         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2813         0,
   2814         1,
   2815         soc_BFD_RX_ACH_TYPE_MPLSTP1_32r_fields,
   2816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2817         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2818         -1,
   2819         -1,
   2820         3,
   2821     },
   2822 #endif /* chips */
   2823 
   2824 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   2825     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2826     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP1_BCM56560_A0r */
   2827         soc_block_list[5],
   2828         soc_genreg,
   2829         1,
   2830         0,
   2831         0x16005300,
   2832         SOC_REG_FLAG_64_BITS,
   2833         0,
   2834         1,
   2835         soc_BFD_RX_ACH_TYPE_MPLSTP1_32r_fields,
   2836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2837         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2838         -1,
   2839         -1,
   2840     },
   2841 #endif /* chips */
   2842 
   2843 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   2844     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP1_BCM56850_A0r */
   2845         soc_block_list[5],
   2846         soc_genreg,
   2847         1,
   2848         0,
   2849         0x16005300,
   2850         SOC_REG_FLAG_64_BITS |
   2851                           (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2852         0,
   2853         1,
   2854         soc_BFD_RX_ACH_TYPE_MPLSTP1r_fields,
   2855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2856         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2857         -1,
   2858         -1,
   2859     },
   2860 #endif /* chips */
   2861 
   2862 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2863     defined(BCM_56450_B1)
   2864     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_1r */
   2865         soc_block_list[5],
   2866         soc_genreg,
   2867         1,
   2868         0,
   2869         0x16000900,
   2870         0,
   2871         0,
   2872         1,
   2873         soc_BFD_RX_ACH_TYPE_MPLSTP1r_fields,
   2874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2875         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   2876         -1,
   2877         -1,
   2878     },
   2879 #endif /* chips */
   2880 
   2881 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   2882     defined(BCM_56450_B1)
   2883     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_BCM56450_A0r */
   2884         soc_block_list[5],
   2885         soc_genreg,
   2886         1,
   2887         0,
   2888         0x16000800,
   2889         0,
   2890         0,
   2891         2,
   2892         soc_BFD_RX_ACH_TYPE_MPLSTP_BCM56640_A0r_fields,
   2893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2894         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2895         -1,
   2896         -1,
   2897     },
   2898 #endif /* chips */
   2899 
   2900 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   2901     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   2902     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_BCM56560_A0r */
   2903         soc_block_list[5],
   2904         soc_genreg,
   2905         1,
   2906         0,
   2907         0x16004c00,
   2908         0,
   2909         0,
   2910         2,
   2911         soc_BFD_RX_ACH_TYPE_MPLSTP_BCM56960_A0r_fields,
   2912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2914         -1,
   2915         -1,
   2916     },
   2917 #endif /* chips */
   2918 
   2919 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   2920     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_BCM56640_A0r */
   2921         soc_block_list[5],
   2922         soc_genreg,
   2923         1,
   2924         0,
   2925         0x16002c00,
   2926         0,
   2927         0,
   2928         2,
   2929         soc_BFD_RX_ACH_TYPE_MPLSTP_BCM56640_A0r_fields,
   2930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2932         -1,
   2933         -1,
   2934     },
   2935 #endif /* chips */
   2936 
   2937 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   2938     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_BCM56850_A0r */
   2939         soc_block_list[5],
   2940         soc_genreg,
   2941         1,
   2942         0,
   2943         0x16004c00,
   2944         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2945         0,
   2946         2,
   2947         soc_BFD_RX_ACH_TYPE_MPLSTP_BCM56640_A0r_fields,
   2948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2949         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2950         -1,
   2951         -1,
   2952     },
   2953 #endif /* chips */
   2954 
   2955 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   2956     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_BCM56960_A0r */
   2957         soc_block_list[5],
   2958         soc_genreg,
   2959         1,
   2960         0,
   2961         0x36000d00,
   2962         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2963         0,
   2964         2,
   2965         soc_BFD_RX_ACH_TYPE_MPLSTP_BCM56960_A0r_fields,
   2966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2967         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2968         -1,
   2969         -1,
   2970         0,
   2971     },
   2972 #endif /* chips */
   2973 
   2974 #if defined(BCM_56970_A0)
   2975     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_BCM56970_A0r */
   2976         soc_block_list[5],
   2977         soc_genreg,
   2978         1,
   2979         0,
   2980         0x5a000c00,
   2981         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   2982         0,
   2983         2,
   2984         soc_BFD_RX_ACH_TYPE_MPLSTP_BCM56960_A0r_fields,
   2985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   2986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   2987         -1,
   2988         -1,
   2989         0,
   2990     },
   2991 #endif /* chips */
   2992 
   2993 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   2994     { /* SOC_REG_INT_BFD_RX_ACH_TYPE_MPLSTP_BCM56980_A0r */
   2995         soc_block_list[5],
   2996         soc_genreg,
   2997         1,
   2998         0,
   2999         0x6000600,
   3000         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3001         0,
   3002         2,
   3003         soc_BFD_RX_ACH_TYPE_MPLSTP_BCM56980_A0r_fields,
   3004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3006         -1,
   3007         -1,
   3008         3,
   3009     },
   3010 #endif /* chips */
   3011 
   3012 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3013     { /* SOC_REG_INT_BFD_RX_UDP_CONTROLr */
   3014         soc_block_list[5],
   3015         soc_genreg,
   3016         1,
   3017         0,
   3018         0x208060e,
   3019         0,
   3020         0,
   3021         2,
   3022         soc_BFD_RX_UDP_CONTROLr_fields,
   3023         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3024         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3025         -1,
   3026         -1,
   3027     },
   3028 #endif /* chips */
   3029 
   3030 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   3031     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1r */
   3032         soc_block_list[5],
   3033         soc_genreg,
   3034         1,
   3035         0,
   3036         0x5080605,
   3037         0,
   3038         0,
   3039         2,
   3040         soc_BFD_RX_UDP_CONTROLr_fields,
   3041         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3043         -1,
   3044         -1,
   3045     },
   3046 #endif /* chips */
   3047 
   3048 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   3049     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   3050     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_64r */
   3051         soc_block_list[5],
   3052         soc_genreg,
   3053         1,
   3054         0,
   3055         0xa009900,
   3056         SOC_REG_FLAG_64_BITS,
   3057         0,
   3058         3,
   3059         soc_BFD_RX_UDP_CONTROL_1_64r_fields,
   3060         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00001a80)
   3061         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   3062         -1,
   3063         -1,
   3064     },
   3065 #endif /* chips */
   3066 
   3067 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
   3068     defined(BCM_56670_A0) || defined(BCM_56670_B0)
   3069     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_64r */
   3070         soc_block_list[5],
   3071         soc_genreg,
   3072         1,
   3073         0,
   3074         0x16004900,
   3075         SOC_REG_FLAG_64_BITS,
   3076         0,
   3077         3,
   3078         soc_BFD_RX_UDP_CONTROL_1_64r_fields,
   3079         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00001a80)
   3080         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   3081         -1,
   3082         -1,
   3083     },
   3084 #endif /* chips */
   3085 
   3086 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   3087     defined(BCM_56270_A0)
   3088     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_BCM56260_A0r */
   3089         soc_block_list[5],
   3090         soc_genreg,
   3091         1,
   3092         0,
   3093         0x16000500,
   3094         0,
   3095         0,
   3096         2,
   3097         soc_BFD_RX_UDP_CONTROL_BCM56960_A0r_fields,
   3098         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3099         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3100         -1,
   3101         -1,
   3102     },
   3103 #endif /* chips */
   3104 
   3105 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3106     defined(BCM_56450_B1)
   3107     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_BCM56450_A0r */
   3108         soc_block_list[5],
   3109         soc_genreg,
   3110         1,
   3111         0,
   3112         0x16000500,
   3113         0,
   3114         0,
   3115         2,
   3116         soc_BFD_RX_UDP_CONTROL_BCM56640_A0r_fields,
   3117         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3118         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3119         -1,
   3120         -1,
   3121     },
   3122 #endif /* chips */
   3123 
   3124 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   3125     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_BCM56640_A0r */
   3126         soc_block_list[5],
   3127         soc_genreg,
   3128         1,
   3129         0,
   3130         0x16002900,
   3131         0,
   3132         0,
   3133         2,
   3134         soc_BFD_RX_UDP_CONTROL_BCM56640_A0r_fields,
   3135         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3137         -1,
   3138         -1,
   3139     },
   3140 #endif /* chips */
   3141 
   3142 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   3143     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_BCM56850_A0r */
   3144         soc_block_list[5],
   3145         soc_genreg,
   3146         1,
   3147         0,
   3148         0x16004900,
   3149         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3150         0,
   3151         2,
   3152         soc_BFD_RX_UDP_CONTROL_BCM56640_A0r_fields,
   3153         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3154         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3155         -1,
   3156         -1,
   3157     },
   3158 #endif /* chips */
   3159 
   3160 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3161     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_BCM56960_A0r */
   3162         soc_block_list[5],
   3163         soc_genreg,
   3164         1,
   3165         0,
   3166         0x3a001e00,
   3167         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3168         0,
   3169         2,
   3170         soc_BFD_RX_UDP_CONTROL_BCM56960_A0r_fields,
   3171         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3173         -1,
   3174         -1,
   3175         3,
   3176     },
   3177 #endif /* chips */
   3178 
   3179 #if defined(BCM_56970_A0)
   3180     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_BCM56970_A0r */
   3181         soc_block_list[5],
   3182         soc_genreg,
   3183         1,
   3184         0,
   3185         0x5e001f00,
   3186         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3187         0,
   3188         2,
   3189         soc_BFD_RX_UDP_CONTROL_BCM56960_A0r_fields,
   3190         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3192         -1,
   3193         -1,
   3194         3,
   3195     },
   3196 #endif /* chips */
   3197 
   3198 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3199     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_1_BCM56980_A0r */
   3200         soc_block_list[5],
   3201         soc_genreg,
   3202         1,
   3203         0,
   3204         0xe000000,
   3205         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3206         0,
   3207         2,
   3208         soc_BFD_RX_UDP_CONTROL_BCM56980_A0r_fields,
   3209         SOC_RESET_VAL_DEC(0x12b00ec8, 0x00000000)
   3210         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3211         -1,
   3212         -1,
   3213         3,
   3214     },
   3215 #endif /* chips */
   3216 
   3217 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   3218     defined(BCM_56270_A0)
   3219     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56260_A0r */
   3220         soc_block_list[5],
   3221         soc_genreg,
   3222         1,
   3223         0,
   3224         0xa000c00,
   3225         0,
   3226         0,
   3227         2,
   3228         soc_BFD_RX_UDP_CONTROL_BCM56960_A0r_fields,
   3229         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3230         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3231         -1,
   3232         -1,
   3233     },
   3234 #endif /* chips */
   3235 
   3236 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3237     defined(BCM_56450_B1)
   3238     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56450_A0r */
   3239         soc_block_list[5],
   3240         soc_genreg,
   3241         1,
   3242         0,
   3243         0xa000c00,
   3244         0,
   3245         0,
   3246         2,
   3247         soc_BFD_RX_UDP_CONTROL_BCM56640_A0r_fields,
   3248         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3249         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3250         -1,
   3251         -1,
   3252     },
   3253 #endif /* chips */
   3254 
   3255 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   3256     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56640_A0r */
   3257         soc_block_list[5],
   3258         soc_genreg,
   3259         1,
   3260         0,
   3261         0xa003200,
   3262         0,
   3263         0,
   3264         2,
   3265         soc_BFD_RX_UDP_CONTROL_BCM56640_A0r_fields,
   3266         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3267         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3268         -1,
   3269         -1,
   3270     },
   3271 #endif /* chips */
   3272 
   3273 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   3274     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56850_A0r */
   3275         soc_block_list[5],
   3276         soc_genreg,
   3277         1,
   3278         0,
   3279         0xa009900,
   3280         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3281         0,
   3282         2,
   3283         soc_BFD_RX_UDP_CONTROL_BCM56640_A0r_fields,
   3284         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3285         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3286         -1,
   3287         -1,
   3288     },
   3289 #endif /* chips */
   3290 
   3291 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \
   3292     defined(BCM_56870_A0)
   3293     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56870_A0r */
   3294         soc_block_list[115],
   3295         soc_genreg,
   3296         1,
   3297         0,
   3298         0x2001800,
   3299         (3 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3300         SOC_REG_FLAG_CCH,
   3301         2,
   3302         soc_BFD_RX_UDP_CONTROL_BCM56960_A0r_fields,
   3303         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3304         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3305         -1,
   3306         -1,
   3307         3,
   3308     },
   3309 #endif /* chips */
   3310 
   3311 #if defined(BCM_56960_A0) || defined(BCM_56965_A0)
   3312     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56960_A0r */
   3313         soc_block_list[5],
   3314         soc_genreg,
   3315         1,
   3316         0,
   3317         0x2e001f00,
   3318         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3319         0,
   3320         2,
   3321         soc_BFD_RX_UDP_CONTROL_BCM56960_A0r_fields,
   3322         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3323         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3324         -1,
   3325         -1,
   3326         0,
   3327     },
   3328 #endif /* chips */
   3329 
   3330 #if defined(BCM_56970_A0)
   3331     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56970_A0r */
   3332         soc_block_list[5],
   3333         soc_genreg,
   3334         1,
   3335         0,
   3336         0x52001f00,
   3337         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3338         0,
   3339         2,
   3340         soc_BFD_RX_UDP_CONTROL_BCM56960_A0r_fields,
   3341         SOC_RESET_VAL_DEC(0x0ec812b0, 0x00000000)
   3342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3343         -1,
   3344         -1,
   3345         0,
   3346     },
   3347 #endif /* chips */
   3348 
   3349 #if defined(BCM_56980_A0) || defined(BCM_56980_B0)
   3350     { /* SOC_REG_INT_BFD_RX_UDP_CONTROL_BCM56980_A0r */
   3351         soc_block_list[5],
   3352         soc_genreg,
   3353         1,
   3354         0,
   3355         0x6000800,
   3356         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
   3357         0,
   3358         2,
   3359         soc_BFD_RX_UDP_CONTROL_BCM56980_A0r_fields,
   3360         SOC_RESET_VAL_DEC(0x12b00ec8, 0x00000000)
   3361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3362         -1,
   3363         -1,
   3364         3,
   3365     },
   3366 #endif /* chips */
   3367 
   3368 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3369     defined(BCM_56450_B1)
   3370     { /* SOC_REG_INT_BFD_VERSION_CONTROLr */
   3371         soc_block_list[5],
   3372         soc_genreg,
   3373         1,
   3374         0,
   3375         0xa003000,
   3376         0,
   3377         0,
   3378         1,
   3379         soc_BFD_VERSION_CONTROLr_fields,
   3380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3381         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3382         -1,
   3383         -1,
   3384     },
   3385 #endif /* chips */
   3386 
   3387 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   3388     defined(BCM_56270_A0)
   3389     { /* SOC_REG_INT_BFD_VERSION_CONTROL_BCM56260_A0r */
   3390         soc_block_list[5],
   3391         soc_genreg,
   3392         1,
   3393         0,
   3394         0xa003000,
   3395         0,
   3396         0,
   3397         1,
   3398         soc_BFD_VERSION_CONTROL_BCM56260_A0r_fields,
   3399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3400         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   3401         -1,
   3402         -1,
   3403     },
   3404 #endif /* chips */
   3405 
   3406 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3407     defined(BCM_56450_B1)
   3408     { /* SOC_REG_INT_BHH_RX_ACH_TYPEr */
   3409         soc_block_list[5],
   3410         soc_genreg,
   3411         1,
   3412         0,
   3413         0x16002900,
   3414         0,
   3415         0,
   3416         1,
   3417         soc_BHH_RX_ACH_TYPEr_fields,
   3418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3419         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   3420         -1,
   3421         -1,
   3422     },
   3423 #endif /* chips */
   3424 
   3425 #if defined(BCM_56150_A0)
   3426     { /* SOC_REG_INT_BISR_DEBUG_DATAr */
   3427         soc_block_list[122],
   3428         soc_genreg,
   3429         1,
   3430         0,
   3431         0x2022000,
   3432         SOC_REG_FLAG_RO,
   3433         0,
   3434         1,
   3435         soc_BISR_DEBUG_DATAr_fields,
   3436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3437         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3438         -1,
   3439         -1,
   3440     },
   3441 #endif /* chips */
   3442 
   3443 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3444     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   3445     defined(BCM_56160_A0)
   3446     { /* SOC_REG_INT_BISR_DEBUG_DATA_BCM53400_A0r */
   3447         soc_block_list[122],
   3448         soc_genreg,
   3449         1,
   3450         0,
   3451         0x2022000,
   3452         SOC_REG_FLAG_RO,
   3453         0,
   3454         1,
   3455         soc_BISR_DEBUG_DATA_BCM53400_A0r_fields,
   3456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3457         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3458         -1,
   3459         -1,
   3460     },
   3461 #endif /* chips */
   3462 
   3463 #if defined(BCM_56150_A0)
   3464     { /* SOC_REG_INT_BISR_LOAD_DONE_STATUSr */
   3465         soc_block_list[122],
   3466         soc_genreg,
   3467         1,
   3468         0,
   3469         0x2023000,
   3470         SOC_REG_FLAG_RO,
   3471         0,
   3472         2,
   3473         soc_BISR_LOAD_DONE_STATUSr_fields,
   3474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3475         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3476         -1,
   3477         -1,
   3478     },
   3479 #endif /* chips */
   3480 
   3481 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3482     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   3483     defined(BCM_56160_A0)
   3484     { /* SOC_REG_INT_BISR_LOAD_DONE_STATUS_BCM53400_A0r */
   3485         soc_block_list[122],
   3486         soc_genreg,
   3487         1,
   3488         0,
   3489         0x2023000,
   3490         SOC_REG_FLAG_RO,
   3491         0,
   3492         2,
   3493         soc_BISR_LOAD_DONE_STATUS_BCM53400_A0r_fields,
   3494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3496         -1,
   3497         -1,
   3498     },
   3499 #endif /* chips */
   3500 
   3501 #if defined(BCM_56150_A0)
   3502     { /* SOC_REG_INT_BISR_LOAD_STATUSr */
   3503         soc_block_list[122],
   3504         soc_genreg,
   3505         1,
   3506         0,
   3507         0x2021c00,
   3508         SOC_REG_FLAG_RO,
   3509         0,
   3510         7,
   3511         soc_BISR_LOAD_STATUSr_fields,
   3512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3514         -1,
   3515         -1,
   3516     },
   3517 #endif /* chips */
   3518 
   3519 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   3520     defined(BCM_53570_A0) || defined(BCM_53570_B0) || \
   3521     defined(BCM_56160_A0)
   3522     { /* SOC_REG_INT_BISR_LOAD_STATUS_BCM53400_A0r */
   3523         soc_block_list[122],
   3524         soc_genreg,
   3525         1,
   3526         0,
   3527         0x2021c00,
   3528         SOC_REG_FLAG_RO,
   3529         0,
   3530         7,
   3531         soc_BISR_LOAD_STATUS_BCM53400_A0r_fields,
   3532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   3534         -1,
   3535         -1,
   3536     },
   3537 #endif /* chips */
   3538 
   3539 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3540     defined(BCM_56450_B1)
   3541     { /* SOC_REG_INT_BISTCONFIGr */
   3542         soc_block_list[84],
   3543         soc_genreg,
   3544         1,
   3545         0,
   3546         0x2003000,
   3547         0,
   3548         0,
   3549         3,
   3550         soc_BISTCONFIGr_fields,
   3551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3552         SOC_RESET_MASK_DEC(0x01ff0001, 0x00000000)
   3553         -1,
   3554         -1,
   3555     },
   3556 #endif /* chips */
   3557 
   3558 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3559     defined(BCM_56450_B1)
   3560     { /* SOC_REG_INT_BISTCONFIG2r */
   3561         soc_block_list[84],
   3562         soc_genreg,
   3563         1,
   3564         0,
   3565         0x2003100,
   3566         0,
   3567         0,
   3568         3,
   3569         soc_BISTCONFIG2r_fields,
   3570         SOC_RESET_VAL_DEC(0x00060202, 0x00000000)
   3571         SOC_RESET_MASK_DEC(0x00070707, 0x00000000)
   3572         -1,
   3573         -1,
   3574     },
   3575 #endif /* chips */
   3576 
   3577 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3578     { /* SOC_REG_INT_BISTCONFIG2_BCM56260_A0r */
   3579         soc_block_list[84],
   3580         soc_genreg,
   3581         1,
   3582         0,
   3583         0x2002300,
   3584         0,
   3585         0,
   3586         3,
   3587         soc_BISTCONFIG2_BCM56260_A0r_fields,
   3588         SOC_RESET_VAL_DEC(0x00060202, 0x00000000)
   3589         SOC_RESET_MASK_DEC(0x00070707, 0x00000000)
   3590         -1,
   3591         -1,
   3592     },
   3593 #endif /* chips */
   3594 
   3595 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3596     defined(BCM_56450_B1)
   3597     { /* SOC_REG_INT_BISTCONFIGURATIONSr */
   3598         soc_block_list[84],
   3599         soc_genreg,
   3600         1,
   3601         0,
   3602         0x2003300,
   3603         0,
   3604         0,
   3605         12,
   3606         soc_BISTCONFIGURATIONSr_fields,
   3607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3608         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   3609         -1,
   3610         -1,
   3611     },
   3612 #endif /* chips */
   3613 
   3614 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3615     { /* SOC_REG_INT_BISTCONFIGURATIONS_BCM56260_A0r */
   3616         soc_block_list[84],
   3617         soc_genreg,
   3618         1,
   3619         0,
   3620         0x2002500,
   3621         0,
   3622         0,
   3623         12,
   3624         soc_BISTCONFIGURATIONS_BCM56260_A0r_fields,
   3625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3626         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   3627         -1,
   3628         -1,
   3629     },
   3630 #endif /* chips */
   3631 
   3632 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3633     { /* SOC_REG_INT_BISTCONFIG_BCM56260_A0r */
   3634         soc_block_list[84],
   3635         soc_genreg,
   3636         1,
   3637         0,
   3638         0x2002200,
   3639         0,
   3640         0,
   3641         3,
   3642         soc_BISTCONFIG_BCM56260_A0r_fields,
   3643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3644         SOC_RESET_MASK_DEC(0x01ff0001, 0x00000000)
   3645         -1,
   3646         -1,
   3647     },
   3648 #endif /* chips */
   3649 
   3650 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3651     defined(BCM_56450_B1)
   3652     { /* SOC_REG_INT_BISTENDADDRESSr */
   3653         soc_block_list[84],
   3654         soc_genreg,
   3655         1,
   3656         0,
   3657         0x2003600,
   3658         0,
   3659         0,
   3660         1,
   3661         soc_BISTENDADDRESSr_fields,
   3662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3663         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   3664         -1,
   3665         -1,
   3666     },
   3667 #endif /* chips */
   3668 
   3669 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3670     { /* SOC_REG_INT_BISTENDADDRESS_BCM56260_A0r */
   3671         soc_block_list[84],
   3672         soc_genreg,
   3673         1,
   3674         0,
   3675         0x2002800,
   3676         0,
   3677         0,
   3678         1,
   3679         soc_BISTENDADDRESS_BCM56260_A0r_fields,
   3680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3681         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   3682         -1,
   3683         -1,
   3684     },
   3685 #endif /* chips */
   3686 
   3687 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3688     defined(BCM_56450_B1)
   3689     { /* SOC_REG_INT_BISTERROROCCURREDr */
   3690         soc_block_list[84],
   3691         soc_genreg,
   3692         1,
   3693         0,
   3694         0x2004b00,
   3695         0,
   3696         0,
   3697         1,
   3698         soc_BISTERROROCCURREDr_fields,
   3699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3700         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3701         -1,
   3702         -1,
   3703     },
   3704 #endif /* chips */
   3705 
   3706 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3707     { /* SOC_REG_INT_BISTERROROCCURRED_BCM56260_A0r */
   3708         soc_block_list[84],
   3709         soc_genreg,
   3710         1,
   3711         0,
   3712         0x2003d00,
   3713         0,
   3714         0,
   3715         1,
   3716         soc_BISTERROROCCURRED_BCM56260_A0r_fields,
   3717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3718         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3719         -1,
   3720         -1,
   3721     },
   3722 #endif /* chips */
   3723 
   3724 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3725     defined(BCM_56450_B1)
   3726     { /* SOC_REG_INT_BISTFULLMASKERRORCOUNTERr */
   3727         soc_block_list[84],
   3728         soc_genreg,
   3729         1,
   3730         0,
   3731         0x2004900,
   3732         0,
   3733         0,
   3734         1,
   3735         soc_BISTFULLMASKERRORCOUNTERr_fields,
   3736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3738         -1,
   3739         -1,
   3740     },
   3741 #endif /* chips */
   3742 
   3743 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3744     { /* SOC_REG_INT_BISTFULLMASKERRORCOUNTER_BCM56260_A0r */
   3745         soc_block_list[84],
   3746         soc_genreg,
   3747         1,
   3748         0,
   3749         0x2003b00,
   3750         0,
   3751         0,
   3752         1,
   3753         soc_BISTFULLMASKERRORCOUNTER_BCM56260_A0r_fields,
   3754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   3755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3756         -1,
   3757         -1,
   3758     },
   3759 #endif /* chips */
   3760 
   3761 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3762     defined(BCM_56450_B1)
   3763     { /* SOC_REG_INT_BISTFULLMASKWORD0r */
   3764         soc_block_list[84],
   3765         soc_genreg,
   3766         1,
   3767         0,
   3768         0x2004700,
   3769         0,
   3770         0,
   3771         1,
   3772         soc_BISTFULLMASKWORD0r_fields,
   3773         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3774         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3775         -1,
   3776         -1,
   3777     },
   3778 #endif /* chips */
   3779 
   3780 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3781     defined(BCM_56450_B1)
   3782     { /* SOC_REG_INT_BISTFULLMASKWORD1r */
   3783         soc_block_list[84],
   3784         soc_genreg,
   3785         1,
   3786         0,
   3787         0x2004600,
   3788         0,
   3789         0,
   3790         1,
   3791         soc_BISTFULLMASKWORD1r_fields,
   3792         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3793         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3794         -1,
   3795         -1,
   3796     },
   3797 #endif /* chips */
   3798 
   3799 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3800     defined(BCM_56450_B1)
   3801     { /* SOC_REG_INT_BISTFULLMASKWORD2r */
   3802         soc_block_list[84],
   3803         soc_genreg,
   3804         1,
   3805         0,
   3806         0x2004500,
   3807         0,
   3808         0,
   3809         1,
   3810         soc_BISTFULLMASKWORD2r_fields,
   3811         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3812         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3813         -1,
   3814         -1,
   3815     },
   3816 #endif /* chips */
   3817 
   3818 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3819     defined(BCM_56450_B1)
   3820     { /* SOC_REG_INT_BISTFULLMASKWORD3r */
   3821         soc_block_list[84],
   3822         soc_genreg,
   3823         1,
   3824         0,
   3825         0x2004400,
   3826         0,
   3827         0,
   3828         1,
   3829         soc_BISTFULLMASKWORD3r_fields,
   3830         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3831         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3832         -1,
   3833         -1,
   3834     },
   3835 #endif /* chips */
   3836 
   3837 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3838     defined(BCM_56450_B1)
   3839     { /* SOC_REG_INT_BISTFULLMASKWORD4r */
   3840         soc_block_list[84],
   3841         soc_genreg,
   3842         1,
   3843         0,
   3844         0x2004300,
   3845         0,
   3846         0,
   3847         1,
   3848         soc_BISTFULLMASKWORD4r_fields,
   3849         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3851         -1,
   3852         -1,
   3853     },
   3854 #endif /* chips */
   3855 
   3856 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3857     defined(BCM_56450_B1)
   3858     { /* SOC_REG_INT_BISTFULLMASKWORD5r */
   3859         soc_block_list[84],
   3860         soc_genreg,
   3861         1,
   3862         0,
   3863         0x2004200,
   3864         0,
   3865         0,
   3866         1,
   3867         soc_BISTFULLMASKWORD5r_fields,
   3868         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3870         -1,
   3871         -1,
   3872     },
   3873 #endif /* chips */
   3874 
   3875 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3876     defined(BCM_56450_B1)
   3877     { /* SOC_REG_INT_BISTFULLMASKWORD6r */
   3878         soc_block_list[84],
   3879         soc_genreg,
   3880         1,
   3881         0,
   3882         0x2004100,
   3883         0,
   3884         0,
   3885         1,
   3886         soc_BISTFULLMASKWORD6r_fields,
   3887         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3888         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3889         -1,
   3890         -1,
   3891     },
   3892 #endif /* chips */
   3893 
   3894 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   3895     defined(BCM_56450_B1)
   3896     { /* SOC_REG_INT_BISTFULLMASKWORD7r */
   3897         soc_block_list[84],
   3898         soc_genreg,
   3899         1,
   3900         0,
   3901         0x2004000,
   3902         0,
   3903         0,
   3904         1,
   3905         soc_BISTFULLMASKWORD7r_fields,
   3906         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3907         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3908         -1,
   3909         -1,
   3910     },
   3911 #endif /* chips */
   3912 
   3913 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3914     { /* SOC_REG_INT_BISTFULLMASKWORD0_BCM56260_A0r */
   3915         soc_block_list[84],
   3916         soc_genreg,
   3917         1,
   3918         0,
   3919         0x2003900,
   3920         0,
   3921         0,
   3922         1,
   3923         soc_BISTFULLMASKWORD0_BCM56260_A0r_fields,
   3924         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3925         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3926         -1,
   3927         -1,
   3928     },
   3929 #endif /* chips */
   3930 
   3931 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3932     { /* SOC_REG_INT_BISTFULLMASKWORD1_BCM56260_A0r */
   3933         soc_block_list[84],
   3934         soc_genreg,
   3935         1,
   3936         0,
   3937         0x2003800,
   3938         0,
   3939         0,
   3940         1,
   3941         soc_BISTFULLMASKWORD1_BCM56260_A0r_fields,
   3942         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3943         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3944         -1,
   3945         -1,
   3946     },
   3947 #endif /* chips */
   3948 
   3949 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3950     { /* SOC_REG_INT_BISTFULLMASKWORD2_BCM56260_A0r */
   3951         soc_block_list[84],
   3952         soc_genreg,
   3953         1,
   3954         0,
   3955         0x2003700,
   3956         0,
   3957         0,
   3958         1,
   3959         soc_BISTFULLMASKWORD2_BCM56260_A0r_fields,
   3960         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3962         -1,
   3963         -1,
   3964     },
   3965 #endif /* chips */
   3966 
   3967 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3968     { /* SOC_REG_INT_BISTFULLMASKWORD3_BCM56260_A0r */
   3969         soc_block_list[84],
   3970         soc_genreg,
   3971         1,
   3972         0,
   3973         0x2003600,
   3974         0,
   3975         0,
   3976         1,
   3977         soc_BISTFULLMASKWORD3_BCM56260_A0r_fields,
   3978         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3979         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3980         -1,
   3981         -1,
   3982     },
   3983 #endif /* chips */
   3984 
   3985 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   3986     { /* SOC_REG_INT_BISTFULLMASKWORD4_BCM56260_A0r */
   3987         soc_block_list[84],
   3988         soc_genreg,
   3989         1,
   3990         0,
   3991         0x2003500,
   3992         0,
   3993         0,
   3994         1,
   3995         soc_BISTFULLMASKWORD4_BCM56260_A0r_fields,
   3996         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   3997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   3998         -1,
   3999         -1,
   4000     },
   4001 #endif /* chips */
   4002 
   4003 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4004     { /* SOC_REG_INT_BISTFULLMASKWORD5_BCM56260_A0r */
   4005         soc_block_list[84],
   4006         soc_genreg,
   4007         1,
   4008         0,
   4009         0x2003400,
   4010         0,
   4011         0,
   4012         1,
   4013         soc_BISTFULLMASKWORD5_BCM56260_A0r_fields,
   4014         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4016         -1,
   4017         -1,
   4018     },
   4019 #endif /* chips */
   4020 
   4021 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4022     { /* SOC_REG_INT_BISTFULLMASKWORD6_BCM56260_A0r */
   4023         soc_block_list[84],
   4024         soc_genreg,
   4025         1,
   4026         0,
   4027         0x2003300,
   4028         0,
   4029         0,
   4030         1,
   4031         soc_BISTFULLMASKWORD6_BCM56260_A0r_fields,
   4032         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4034         -1,
   4035         -1,
   4036     },
   4037 #endif /* chips */
   4038 
   4039 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4040     { /* SOC_REG_INT_BISTFULLMASKWORD7_BCM56260_A0r */
   4041         soc_block_list[84],
   4042         soc_genreg,
   4043         1,
   4044         0,
   4045         0x2003200,
   4046         0,
   4047         0,
   4048         1,
   4049         soc_BISTFULLMASKWORD7_BCM56260_A0r_fields,
   4050         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4051         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4052         -1,
   4053         -1,
   4054     },
   4055 #endif /* chips */
   4056 
   4057 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4058     defined(BCM_56450_B1)
   4059     { /* SOC_REG_INT_BISTGENERALCONFIGURATIONSr */
   4060         soc_block_list[84],
   4061         soc_genreg,
   4062         1,
   4063         0,
   4064         0x2003200,
   4065         0,
   4066         0,
   4067         1,
   4068         soc_BISTGENERALCONFIGURATIONSr_fields,
   4069         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   4070         SOC_RESET_MASK_DEC(0x00000070, 0x00000000)
   4071         -1,
   4072         -1,
   4073     },
   4074 #endif /* chips */
   4075 
   4076 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4077     { /* SOC_REG_INT_BISTGENERALCONFIGURATIONS_BCM56260_A0r */
   4078         soc_block_list[84],
   4079         soc_genreg,
   4080         1,
   4081         0,
   4082         0x2002400,
   4083         0,
   4084         0,
   4085         1,
   4086         soc_BISTGENERALCONFIGURATIONS_BCM56260_A0r_fields,
   4087         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   4088         SOC_RESET_MASK_DEC(0x00000070, 0x00000000)
   4089         -1,
   4090         -1,
   4091     },
   4092 #endif /* chips */
   4093 
   4094 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4095     defined(BCM_56450_B1)
   4096     { /* SOC_REG_INT_BISTGLOBALERRORCOUNTERr */
   4097         soc_block_list[84],
   4098         soc_genreg,
   4099         1,
   4100         0,
   4101         0x2004c00,
   4102         0,
   4103         0,
   4104         1,
   4105         soc_BISTGLOBALERRORCOUNTERr_fields,
   4106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4107         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4108         -1,
   4109         -1,
   4110     },
   4111 #endif /* chips */
   4112 
   4113 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4114     { /* SOC_REG_INT_BISTGLOBALERRORCOUNTER_BCM56260_A0r */
   4115         soc_block_list[84],
   4116         soc_genreg,
   4117         1,
   4118         0,
   4119         0x2003e00,
   4120         0,
   4121         0,
   4122         1,
   4123         soc_BISTGLOBALERRORCOUNTER_BCM56260_A0r_fields,
   4124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4125         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4126         -1,
   4127         -1,
   4128     },
   4129 #endif /* chips */
   4130 
   4131 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4132     defined(BCM_56450_B1)
   4133     { /* SOC_REG_INT_BISTLASTADDRERRr */
   4134         soc_block_list[84],
   4135         soc_genreg,
   4136         1,
   4137         0,
   4138         0x2004d00,
   4139         0,
   4140         0,
   4141         1,
   4142         soc_BISTLASTADDRERRr_fields,
   4143         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
   4144         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   4145         -1,
   4146         -1,
   4147     },
   4148 #endif /* chips */
   4149 
   4150 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4151     { /* SOC_REG_INT_BISTLASTADDRERR_BCM56260_A0r */
   4152         soc_block_list[84],
   4153         soc_genreg,
   4154         1,
   4155         0,
   4156         0x2003f00,
   4157         0,
   4158         0,
   4159         1,
   4160         soc_BISTLASTADDRERR_BCM56260_A0r_fields,
   4161         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
   4162         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   4163         -1,
   4164         -1,
   4165     },
   4166 #endif /* chips */
   4167 
   4168 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4169     defined(BCM_56450_B1)
   4170     { /* SOC_REG_INT_BISTLASTDATAERRWORD0r */
   4171         soc_block_list[84],
   4172         soc_genreg,
   4173         1,
   4174         0,
   4175         0x2005500,
   4176         0,
   4177         0,
   4178         1,
   4179         soc_BISTLASTDATAERRWORD0r_fields,
   4180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4181         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4182         -1,
   4183         -1,
   4184     },
   4185 #endif /* chips */
   4186 
   4187 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4188     defined(BCM_56450_B1)
   4189     { /* SOC_REG_INT_BISTLASTDATAERRWORD1r */
   4190         soc_block_list[84],
   4191         soc_genreg,
   4192         1,
   4193         0,
   4194         0x2005400,
   4195         0,
   4196         0,
   4197         1,
   4198         soc_BISTLASTDATAERRWORD1r_fields,
   4199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4200         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4201         -1,
   4202         -1,
   4203     },
   4204 #endif /* chips */
   4205 
   4206 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4207     defined(BCM_56450_B1)
   4208     { /* SOC_REG_INT_BISTLASTDATAERRWORD2r */
   4209         soc_block_list[84],
   4210         soc_genreg,
   4211         1,
   4212         0,
   4213         0x2005300,
   4214         0,
   4215         0,
   4216         1,
   4217         soc_BISTLASTDATAERRWORD2r_fields,
   4218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4219         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4220         -1,
   4221         -1,
   4222     },
   4223 #endif /* chips */
   4224 
   4225 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4226     defined(BCM_56450_B1)
   4227     { /* SOC_REG_INT_BISTLASTDATAERRWORD3r */
   4228         soc_block_list[84],
   4229         soc_genreg,
   4230         1,
   4231         0,
   4232         0x2005200,
   4233         0,
   4234         0,
   4235         1,
   4236         soc_BISTLASTDATAERRWORD3r_fields,
   4237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4238         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4239         -1,
   4240         -1,
   4241     },
   4242 #endif /* chips */
   4243 
   4244 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4245     defined(BCM_56450_B1)
   4246     { /* SOC_REG_INT_BISTLASTDATAERRWORD4r */
   4247         soc_block_list[84],
   4248         soc_genreg,
   4249         1,
   4250         0,
   4251         0x2005100,
   4252         0,
   4253         0,
   4254         1,
   4255         soc_BISTLASTDATAERRWORD4r_fields,
   4256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4258         -1,
   4259         -1,
   4260     },
   4261 #endif /* chips */
   4262 
   4263 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4264     defined(BCM_56450_B1)
   4265     { /* SOC_REG_INT_BISTLASTDATAERRWORD5r */
   4266         soc_block_list[84],
   4267         soc_genreg,
   4268         1,
   4269         0,
   4270         0x2005000,
   4271         0,
   4272         0,
   4273         1,
   4274         soc_BISTLASTDATAERRWORD5r_fields,
   4275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4276         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4277         -1,
   4278         -1,
   4279     },
   4280 #endif /* chips */
   4281 
   4282 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4283     defined(BCM_56450_B1)
   4284     { /* SOC_REG_INT_BISTLASTDATAERRWORD6r */
   4285         soc_block_list[84],
   4286         soc_genreg,
   4287         1,
   4288         0,
   4289         0x2004f00,
   4290         0,
   4291         0,
   4292         1,
   4293         soc_BISTLASTDATAERRWORD6r_fields,
   4294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4295         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4296         -1,
   4297         -1,
   4298     },
   4299 #endif /* chips */
   4300 
   4301 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4302     defined(BCM_56450_B1)
   4303     { /* SOC_REG_INT_BISTLASTDATAERRWORD7r */
   4304         soc_block_list[84],
   4305         soc_genreg,
   4306         1,
   4307         0,
   4308         0x2004e00,
   4309         0,
   4310         0,
   4311         1,
   4312         soc_BISTLASTDATAERRWORD7r_fields,
   4313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4314         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4315         -1,
   4316         -1,
   4317     },
   4318 #endif /* chips */
   4319 
   4320 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4321     { /* SOC_REG_INT_BISTLASTDATAERRWORD0_BCM56260_A0r */
   4322         soc_block_list[84],
   4323         soc_genreg,
   4324         1,
   4325         0,
   4326         0x2004700,
   4327         0,
   4328         0,
   4329         1,
   4330         soc_BISTLASTDATAERRWORD0_BCM56260_A0r_fields,
   4331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4333         -1,
   4334         -1,
   4335     },
   4336 #endif /* chips */
   4337 
   4338 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4339     { /* SOC_REG_INT_BISTLASTDATAERRWORD1_BCM56260_A0r */
   4340         soc_block_list[84],
   4341         soc_genreg,
   4342         1,
   4343         0,
   4344         0x2004600,
   4345         0,
   4346         0,
   4347         1,
   4348         soc_BISTLASTDATAERRWORD1_BCM56260_A0r_fields,
   4349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4350         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4351         -1,
   4352         -1,
   4353     },
   4354 #endif /* chips */
   4355 
   4356 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4357     { /* SOC_REG_INT_BISTLASTDATAERRWORD2_BCM56260_A0r */
   4358         soc_block_list[84],
   4359         soc_genreg,
   4360         1,
   4361         0,
   4362         0x2004500,
   4363         0,
   4364         0,
   4365         1,
   4366         soc_BISTLASTDATAERRWORD2_BCM56260_A0r_fields,
   4367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4369         -1,
   4370         -1,
   4371     },
   4372 #endif /* chips */
   4373 
   4374 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4375     { /* SOC_REG_INT_BISTLASTDATAERRWORD3_BCM56260_A0r */
   4376         soc_block_list[84],
   4377         soc_genreg,
   4378         1,
   4379         0,
   4380         0x2004400,
   4381         0,
   4382         0,
   4383         1,
   4384         soc_BISTLASTDATAERRWORD3_BCM56260_A0r_fields,
   4385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4387         -1,
   4388         -1,
   4389     },
   4390 #endif /* chips */
   4391 
   4392 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4393     { /* SOC_REG_INT_BISTLASTDATAERRWORD4_BCM56260_A0r */
   4394         soc_block_list[84],
   4395         soc_genreg,
   4396         1,
   4397         0,
   4398         0x2004300,
   4399         0,
   4400         0,
   4401         1,
   4402         soc_BISTLASTDATAERRWORD4_BCM56260_A0r_fields,
   4403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4404         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4405         -1,
   4406         -1,
   4407     },
   4408 #endif /* chips */
   4409 
   4410 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4411     { /* SOC_REG_INT_BISTLASTDATAERRWORD5_BCM56260_A0r */
   4412         soc_block_list[84],
   4413         soc_genreg,
   4414         1,
   4415         0,
   4416         0x2004200,
   4417         0,
   4418         0,
   4419         1,
   4420         soc_BISTLASTDATAERRWORD5_BCM56260_A0r_fields,
   4421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4422         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4423         -1,
   4424         -1,
   4425     },
   4426 #endif /* chips */
   4427 
   4428 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4429     { /* SOC_REG_INT_BISTLASTDATAERRWORD6_BCM56260_A0r */
   4430         soc_block_list[84],
   4431         soc_genreg,
   4432         1,
   4433         0,
   4434         0x2004100,
   4435         0,
   4436         0,
   4437         1,
   4438         soc_BISTLASTDATAERRWORD6_BCM56260_A0r_fields,
   4439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4440         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4441         -1,
   4442         -1,
   4443     },
   4444 #endif /* chips */
   4445 
   4446 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4447     { /* SOC_REG_INT_BISTLASTDATAERRWORD7_BCM56260_A0r */
   4448         soc_block_list[84],
   4449         soc_genreg,
   4450         1,
   4451         0,
   4452         0x2004000,
   4453         0,
   4454         0,
   4455         1,
   4456         soc_BISTLASTDATAERRWORD7_BCM56260_A0r_fields,
   4457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4458         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4459         -1,
   4460         -1,
   4461     },
   4462 #endif /* chips */
   4463 
   4464 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4465     defined(BCM_56450_B1)
   4466     { /* SOC_REG_INT_BISTNUMBEROFACTIONSr */
   4467         soc_block_list[84],
   4468         soc_genreg,
   4469         1,
   4470         0,
   4471         0x2003400,
   4472         0,
   4473         0,
   4474         1,
   4475         soc_BISTNUMBEROFACTIONSr_fields,
   4476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4478         -1,
   4479         -1,
   4480     },
   4481 #endif /* chips */
   4482 
   4483 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4484     { /* SOC_REG_INT_BISTNUMBEROFACTIONS_BCM56260_A0r */
   4485         soc_block_list[84],
   4486         soc_genreg,
   4487         1,
   4488         0,
   4489         0x2002600,
   4490         0,
   4491         0,
   4492         1,
   4493         soc_BISTNUMBEROFACTIONS_BCM56260_A0r_fields,
   4494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4495         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4496         -1,
   4497         -1,
   4498     },
   4499 #endif /* chips */
   4500 
   4501 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4502     defined(BCM_56450_B1)
   4503     { /* SOC_REG_INT_BISTPATTERNWORD0r */
   4504         soc_block_list[84],
   4505         soc_genreg,
   4506         1,
   4507         0,
   4508         0x2003f00,
   4509         0,
   4510         0,
   4511         1,
   4512         soc_BISTPATTERNWORD0r_fields,
   4513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4514         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4515         -1,
   4516         -1,
   4517     },
   4518 #endif /* chips */
   4519 
   4520 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4521     defined(BCM_56450_B1)
   4522     { /* SOC_REG_INT_BISTPATTERNWORD1r */
   4523         soc_block_list[84],
   4524         soc_genreg,
   4525         1,
   4526         0,
   4527         0x2003e00,
   4528         0,
   4529         0,
   4530         1,
   4531         soc_BISTPATTERNWORD1r_fields,
   4532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4534         -1,
   4535         -1,
   4536     },
   4537 #endif /* chips */
   4538 
   4539 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4540     defined(BCM_56450_B1)
   4541     { /* SOC_REG_INT_BISTPATTERNWORD2r */
   4542         soc_block_list[84],
   4543         soc_genreg,
   4544         1,
   4545         0,
   4546         0x2003d00,
   4547         0,
   4548         0,
   4549         1,
   4550         soc_BISTPATTERNWORD2r_fields,
   4551         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4552         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4553         -1,
   4554         -1,
   4555     },
   4556 #endif /* chips */
   4557 
   4558 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4559     defined(BCM_56450_B1)
   4560     { /* SOC_REG_INT_BISTPATTERNWORD3r */
   4561         soc_block_list[84],
   4562         soc_genreg,
   4563         1,
   4564         0,
   4565         0x2003c00,
   4566         0,
   4567         0,
   4568         1,
   4569         soc_BISTPATTERNWORD3r_fields,
   4570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4572         -1,
   4573         -1,
   4574     },
   4575 #endif /* chips */
   4576 
   4577 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4578     defined(BCM_56450_B1)
   4579     { /* SOC_REG_INT_BISTPATTERNWORD4r */
   4580         soc_block_list[84],
   4581         soc_genreg,
   4582         1,
   4583         0,
   4584         0x2003b00,
   4585         0,
   4586         0,
   4587         1,
   4588         soc_BISTPATTERNWORD4r_fields,
   4589         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4590         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4591         -1,
   4592         -1,
   4593     },
   4594 #endif /* chips */
   4595 
   4596 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4597     defined(BCM_56450_B1)
   4598     { /* SOC_REG_INT_BISTPATTERNWORD5r */
   4599         soc_block_list[84],
   4600         soc_genreg,
   4601         1,
   4602         0,
   4603         0x2003a00,
   4604         0,
   4605         0,
   4606         1,
   4607         soc_BISTPATTERNWORD5r_fields,
   4608         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4610         -1,
   4611         -1,
   4612     },
   4613 #endif /* chips */
   4614 
   4615 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4616     defined(BCM_56450_B1)
   4617     { /* SOC_REG_INT_BISTPATTERNWORD6r */
   4618         soc_block_list[84],
   4619         soc_genreg,
   4620         1,
   4621         0,
   4622         0x2003900,
   4623         0,
   4624         0,
   4625         1,
   4626         soc_BISTPATTERNWORD6r_fields,
   4627         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4629         -1,
   4630         -1,
   4631     },
   4632 #endif /* chips */
   4633 
   4634 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4635     defined(BCM_56450_B1)
   4636     { /* SOC_REG_INT_BISTPATTERNWORD7r */
   4637         soc_block_list[84],
   4638         soc_genreg,
   4639         1,
   4640         0,
   4641         0x2003800,
   4642         0,
   4643         0,
   4644         1,
   4645         soc_BISTPATTERNWORD7r_fields,
   4646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4647         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4648         -1,
   4649         -1,
   4650     },
   4651 #endif /* chips */
   4652 
   4653 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4654     { /* SOC_REG_INT_BISTPATTERNWORD0_BCM56260_A0r */
   4655         soc_block_list[84],
   4656         soc_genreg,
   4657         1,
   4658         0,
   4659         0x2003100,
   4660         0,
   4661         0,
   4662         1,
   4663         soc_BISTPATTERNWORD0_BCM56260_A0r_fields,
   4664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4665         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4666         -1,
   4667         -1,
   4668     },
   4669 #endif /* chips */
   4670 
   4671 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4672     { /* SOC_REG_INT_BISTPATTERNWORD1_BCM56260_A0r */
   4673         soc_block_list[84],
   4674         soc_genreg,
   4675         1,
   4676         0,
   4677         0x2003000,
   4678         0,
   4679         0,
   4680         1,
   4681         soc_BISTPATTERNWORD1_BCM56260_A0r_fields,
   4682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4684         -1,
   4685         -1,
   4686     },
   4687 #endif /* chips */
   4688 
   4689 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4690     { /* SOC_REG_INT_BISTPATTERNWORD2_BCM56260_A0r */
   4691         soc_block_list[84],
   4692         soc_genreg,
   4693         1,
   4694         0,
   4695         0x2002f00,
   4696         0,
   4697         0,
   4698         1,
   4699         soc_BISTPATTERNWORD2_BCM56260_A0r_fields,
   4700         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4702         -1,
   4703         -1,
   4704     },
   4705 #endif /* chips */
   4706 
   4707 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4708     { /* SOC_REG_INT_BISTPATTERNWORD3_BCM56260_A0r */
   4709         soc_block_list[84],
   4710         soc_genreg,
   4711         1,
   4712         0,
   4713         0x2002e00,
   4714         0,
   4715         0,
   4716         1,
   4717         soc_BISTPATTERNWORD3_BCM56260_A0r_fields,
   4718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4720         -1,
   4721         -1,
   4722     },
   4723 #endif /* chips */
   4724 
   4725 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4726     { /* SOC_REG_INT_BISTPATTERNWORD4_BCM56260_A0r */
   4727         soc_block_list[84],
   4728         soc_genreg,
   4729         1,
   4730         0,
   4731         0x2002d00,
   4732         0,
   4733         0,
   4734         1,
   4735         soc_BISTPATTERNWORD4_BCM56260_A0r_fields,
   4736         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4737         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4738         -1,
   4739         -1,
   4740     },
   4741 #endif /* chips */
   4742 
   4743 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4744     { /* SOC_REG_INT_BISTPATTERNWORD5_BCM56260_A0r */
   4745         soc_block_list[84],
   4746         soc_genreg,
   4747         1,
   4748         0,
   4749         0x2002c00,
   4750         0,
   4751         0,
   4752         1,
   4753         soc_BISTPATTERNWORD5_BCM56260_A0r_fields,
   4754         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4756         -1,
   4757         -1,
   4758     },
   4759 #endif /* chips */
   4760 
   4761 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4762     { /* SOC_REG_INT_BISTPATTERNWORD6_BCM56260_A0r */
   4763         soc_block_list[84],
   4764         soc_genreg,
   4765         1,
   4766         0,
   4767         0x2002b00,
   4768         0,
   4769         0,
   4770         1,
   4771         soc_BISTPATTERNWORD6_BCM56260_A0r_fields,
   4772         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4773         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4774         -1,
   4775         -1,
   4776     },
   4777 #endif /* chips */
   4778 
   4779 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4780     { /* SOC_REG_INT_BISTPATTERNWORD7_BCM56260_A0r */
   4781         soc_block_list[84],
   4782         soc_genreg,
   4783         1,
   4784         0,
   4785         0x2002a00,
   4786         0,
   4787         0,
   4788         1,
   4789         soc_BISTPATTERNWORD7_BCM56260_A0r_fields,
   4790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4791         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4792         -1,
   4793         -1,
   4794     },
   4795 #endif /* chips */
   4796 
   4797 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4798     defined(BCM_56450_B1)
   4799     { /* SOC_REG_INT_BISTSINGLEBITMASKr */
   4800         soc_block_list[84],
   4801         soc_genreg,
   4802         1,
   4803         0,
   4804         0x2003700,
   4805         0,
   4806         0,
   4807         1,
   4808         soc_BISTSINGLEBITMASKr_fields,
   4809         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4810         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4811         -1,
   4812         -1,
   4813     },
   4814 #endif /* chips */
   4815 
   4816 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4817     defined(BCM_56450_B1)
   4818     { /* SOC_REG_INT_BISTSINGLEBITMASKERRORCOUNTERr */
   4819         soc_block_list[84],
   4820         soc_genreg,
   4821         1,
   4822         0,
   4823         0x2004a00,
   4824         0,
   4825         0,
   4826         1,
   4827         soc_BISTSINGLEBITMASKERRORCOUNTERr_fields,
   4828         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4829         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4830         -1,
   4831         -1,
   4832     },
   4833 #endif /* chips */
   4834 
   4835 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4836     { /* SOC_REG_INT_BISTSINGLEBITMASKERRORCOUNTER_BCM56260_A0r */
   4837         soc_block_list[84],
   4838         soc_genreg,
   4839         1,
   4840         0,
   4841         0x2003c00,
   4842         0,
   4843         0,
   4844         1,
   4845         soc_BISTSINGLEBITMASKERRORCOUNTER_BCM56260_A0r_fields,
   4846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4847         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4848         -1,
   4849         -1,
   4850     },
   4851 #endif /* chips */
   4852 
   4853 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4854     { /* SOC_REG_INT_BISTSINGLEBITMASK_BCM56260_A0r */
   4855         soc_block_list[84],
   4856         soc_genreg,
   4857         1,
   4858         0,
   4859         0x2002900,
   4860         0,
   4861         0,
   4862         1,
   4863         soc_BISTSINGLEBITMASK_BCM56260_A0r_fields,
   4864         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   4865         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   4866         -1,
   4867         -1,
   4868     },
   4869 #endif /* chips */
   4870 
   4871 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4872     defined(BCM_56450_B1)
   4873     { /* SOC_REG_INT_BISTSTARTADDRESSr */
   4874         soc_block_list[84],
   4875         soc_genreg,
   4876         1,
   4877         0,
   4878         0x2003500,
   4879         0,
   4880         0,
   4881         1,
   4882         soc_BISTSTARTADDRESSr_fields,
   4883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4884         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   4885         -1,
   4886         -1,
   4887     },
   4888 #endif /* chips */
   4889 
   4890 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4891     { /* SOC_REG_INT_BISTSTARTADDRESS_BCM56260_A0r */
   4892         soc_block_list[84],
   4893         soc_genreg,
   4894         1,
   4895         0,
   4896         0x2002700,
   4897         0,
   4898         0,
   4899         1,
   4900         soc_BISTSTARTADDRESS_BCM56260_A0r_fields,
   4901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4902         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   4903         -1,
   4904         -1,
   4905     },
   4906 #endif /* chips */
   4907 
   4908 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   4909     defined(BCM_56450_B1)
   4910     { /* SOC_REG_INT_BISTSTATUSESr */
   4911         soc_block_list[84],
   4912         soc_genreg,
   4913         1,
   4914         0,
   4915         0x2004800,
   4916         0,
   4917         0,
   4918         4,
   4919         soc_BISTSTATUSESr_fields,
   4920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4921         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4922         -1,
   4923         -1,
   4924     },
   4925 #endif /* chips */
   4926 
   4927 #if defined(BCM_56260_A0) || defined(BCM_56260_B0)
   4928     { /* SOC_REG_INT_BISTSTATUSES_BCM56260_A0r */
   4929         soc_block_list[84],
   4930         soc_genreg,
   4931         1,
   4932         0,
   4933         0x2003a00,
   4934         0,
   4935         0,
   4936         4,
   4937         soc_BISTSTATUSES_BCM56260_A0r_fields,
   4938         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4939         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   4940         -1,
   4941         -1,
   4942     },
   4943 #endif /* chips */
   4944 
   4945 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   4946     defined(BCM_56504_B0)
   4947     { /* SOC_REG_INT_BKPMETERINGBUCKETr */
   4948         soc_block_list[4],
   4949         soc_portreg,
   4950         1,
   4951         0,
   4952         0xb,
   4953         0,
   4954         0,
   4955         2,
   4956         soc_BKPMETERINGBUCKETr_fields,
   4957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4958         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   4959         -1,
   4960         -1,
   4961     },
   4962 #endif /* chips */
   4963 
   4964 #if defined(BCM_53400_A0)
   4965     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM53400_A0r */
   4966         soc_block_list[4],
   4967         soc_portreg,
   4968         1,
   4969         0,
   4970         0x700,
   4971         0,
   4972         0,
   4973         2,
   4974         soc_BKPMETERINGBUCKET_BCM53400_A0r_fields,
   4975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4976         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   4977         -1,
   4978         79,
   4979     },
   4980 #endif /* chips */
   4981 
   4982 #if defined(BCM_53540_A0)
   4983     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM53540_A0r */
   4984         soc_block_list[4],
   4985         soc_portreg,
   4986         1,
   4987         0,
   4988         0x2000,
   4989         0,
   4990         0,
   4991         2,
   4992         soc_BKPMETERINGBUCKET_BCM53400_A0r_fields,
   4993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   4994         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   4995         -1,
   4996         91,
   4997     },
   4998 #endif /* chips */
   4999 
   5000 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5001     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM53570_A0r */
   5002         soc_block_list[4],
   5003         soc_portreg,
   5004         1,
   5005         0,
   5006         0x2800,
   5007         0,
   5008         0,
   5009         2,
   5010         soc_BKPMETERINGBUCKET_BCM53400_A0r_fields,
   5011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5012         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5013         -1,
   5014         101,
   5015     },
   5016 #endif /* chips */
   5017 
   5018 #if defined(BCM_56142_A0)
   5019     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56142_A0r */
   5020         soc_block_list[4],
   5021         soc_portreg,
   5022         1,
   5023         0,
   5024         0x7,
   5025         0,
   5026         0,
   5027         2,
   5028         soc_BKPMETERINGBUCKETr_fields,
   5029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5030         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5031         -1,
   5032         -1,
   5033     },
   5034 #endif /* chips */
   5035 
   5036 #if defined(BCM_56150_A0)
   5037     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56150_A0r */
   5038         soc_block_list[4],
   5039         soc_portreg,
   5040         1,
   5041         0,
   5042         0x700,
   5043         0,
   5044         0,
   5045         2,
   5046         soc_BKPMETERINGBUCKET_BCM56150_A0r_fields,
   5047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5048         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5049         -1,
   5050         79,
   5051     },
   5052 #endif /* chips */
   5053 
   5054 #if defined(BCM_56160_A0)
   5055     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56160_A0r */
   5056         soc_block_list[4],
   5057         soc_portreg,
   5058         1,
   5059         0,
   5060         0x700,
   5061         0,
   5062         0,
   5063         2,
   5064         soc_BKPMETERINGBUCKET_BCM53400_A0r_fields,
   5065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5066         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5067         -1,
   5068         91,
   5069     },
   5070 #endif /* chips */
   5071 
   5072 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5073     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   5074     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56224_A0r */
   5075         soc_block_list[4],
   5076         soc_portreg,
   5077         1,
   5078         0,
   5079         0x6,
   5080         0,
   5081         0,
   5082         2,
   5083         soc_BKPMETERINGBUCKETr_fields,
   5084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5085         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5086         -1,
   5087         -1,
   5088     },
   5089 #endif /* chips */
   5090 
   5091 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   5092     defined(BCM_56270_A0)
   5093     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56260_A0r */
   5094         soc_block_list[4],
   5095         soc_portreg,
   5096         1,
   5097         0,
   5098         0x24000100,
   5099         0,
   5100         0,
   5101         3,
   5102         soc_BKPMETERINGBUCKET_BCM56260_A0r_fields,
   5103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5104         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5105         -1,
   5106         32,
   5107     },
   5108 #endif /* chips */
   5109 
   5110 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5111     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56440_A0r */
   5112         soc_block_list[4],
   5113         soc_portreg,
   5114         1,
   5115         0,
   5116         0x9000001,
   5117         0,
   5118         0,
   5119         3,
   5120         soc_BKPMETERINGBUCKET_BCM56800_A0r_fields,
   5121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5122         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5123         -1,
   5124         56,
   5125     },
   5126 #endif /* chips */
   5127 
   5128 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5129     defined(BCM_56450_B1)
   5130     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56450_A0r */
   5131         soc_block_list[4],
   5132         soc_portreg,
   5133         1,
   5134         0,
   5135         0x24000100,
   5136         0,
   5137         0,
   5138         3,
   5139         soc_BKPMETERINGBUCKET_BCM56640_A0r_fields,
   5140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5141         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5142         -1,
   5143         77,
   5144     },
   5145 #endif /* chips */
   5146 
   5147 #if defined(BCM_56514_A0)
   5148     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56514_A0r */
   5149         soc_block_list[4],
   5150         soc_portreg,
   5151         1,
   5152         0,
   5153         0xc,
   5154         0,
   5155         0,
   5156         2,
   5157         soc_BKPMETERINGBUCKETr_fields,
   5158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5159         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5160         -1,
   5161         -1,
   5162     },
   5163 #endif /* chips */
   5164 
   5165 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5166     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5167     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5168     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56634_A0r */
   5169         soc_block_list[4],
   5170         soc_portreg,
   5171         1,
   5172         0,
   5173         0x9000001,
   5174         0,
   5175         0,
   5176         3,
   5177         soc_BKPMETERINGBUCKET_BCM56800_A0r_fields,
   5178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5179         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5180         -1,
   5181         16,
   5182     },
   5183 #endif /* chips */
   5184 
   5185 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5186     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56640_A0r */
   5187         soc_block_list[4],
   5188         soc_portreg,
   5189         1,
   5190         0,
   5191         0x24000100,
   5192         0,
   5193         0,
   5194         3,
   5195         soc_BKPMETERINGBUCKET_BCM56640_A0r_fields,
   5196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5197         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5198         -1,
   5199         59,
   5200     },
   5201 #endif /* chips */
   5202 
   5203 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   5204     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5205     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   5206     defined(BCM_56800_A0)
   5207     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56800_A0r */
   5208         soc_block_list[4],
   5209         soc_portreg,
   5210         1,
   5211         0,
   5212         0x9000001,
   5213         0,
   5214         0,
   5215         3,
   5216         soc_BKPMETERINGBUCKET_BCM56800_A0r_fields,
   5217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5218         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5219         -1,
   5220         -1,
   5221     },
   5222 #endif /* chips */
   5223 
   5224 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) || \
   5225     defined(BCM_88732_A0)
   5226     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56820_A0r */
   5227         soc_block_list[4],
   5228         soc_portreg,
   5229         1,
   5230         0,
   5231         0x9000008,
   5232         0,
   5233         0,
   5234         3,
   5235         soc_BKPMETERINGBUCKET_BCM56800_A0r_fields,
   5236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5237         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5238         -1,
   5239         -1,
   5240     },
   5241 #endif /* chips */
   5242 
   5243 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5244     { /* SOC_REG_INT_BKPMETERINGBUCKET_BCM56840_A0r */
   5245         soc_block_list[4],
   5246         soc_portreg,
   5247         1,
   5248         0,
   5249         0x9000001,
   5250         0,
   5251         0,
   5252         3,
   5253         soc_BKPMETERINGBUCKET_BCM56800_A0r_fields,
   5254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5255         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5256         -1,
   5257         37,
   5258     },
   5259 #endif /* chips */
   5260 
   5261 #if defined(BCM_56504_A0) || defined(BCM_56504_B0)
   5262     { /* SOC_REG_INT_BKPMETERINGCONFIGr */
   5263         soc_block_list[4],
   5264         soc_portreg,
   5265         1,
   5266         0,
   5267         0xa,
   5268         0,
   5269         0,
   5270         5,
   5271         soc_BKPMETERINGCONFIGr_fields,
   5272         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5273         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   5274         -1,
   5275         -1,
   5276     },
   5277 #endif /* chips */
   5278 
   5279 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) || \
   5280     defined(BCM_88732_A0)
   5281     { /* SOC_REG_INT_BKPMETERINGCONFIG1r */
   5282         soc_block_list[4],
   5283         soc_portreg,
   5284         1,
   5285         0,
   5286         0x9000004,
   5287         0,
   5288         0,
   5289         2,
   5290         soc_BKPMETERINGCONFIG1r_fields,
   5291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5292         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   5293         -1,
   5294         -1,
   5295     },
   5296 #endif /* chips */
   5297 
   5298 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   5299     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5300     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   5301     { /* SOC_REG_INT_BKPMETERINGCONFIG_64r */
   5302         soc_block_list[4],
   5303         soc_portreg,
   5304         1,
   5305         0,
   5306         0x9000000,
   5307         SOC_REG_FLAG_64_BITS,
   5308         0,
   5309         6,
   5310         soc_BKPMETERINGCONFIG_64r_fields,
   5311         SOC_RESET_VAL_DEC(0x00000000, 0x00000018)
   5312         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5313         -1,
   5314         -1,
   5315     },
   5316 #endif /* chips */
   5317 
   5318 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   5319     defined(BCM_56270_A0)
   5320     { /* SOC_REG_INT_BKPMETERINGCONFIG_64_BCM56260_A0r */
   5321         soc_block_list[4],
   5322         soc_portreg,
   5323         1,
   5324         0,
   5325         0x24000000,
   5326         SOC_REG_FLAG_64_BITS,
   5327         0,
   5328         6,
   5329         soc_BKPMETERINGCONFIG_64_BCM56260_A0r_fields,
   5330         SOC_RESET_VAL_DEC(0x00000000, 0x00000018)
   5331         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5332         -1,
   5333         32,
   5334     },
   5335 #endif /* chips */
   5336 
   5337 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   5338     { /* SOC_REG_INT_BKPMETERINGCONFIG_64_BCM56440_A0r */
   5339         soc_block_list[4],
   5340         soc_portreg,
   5341         1,
   5342         0,
   5343         0x9000000,
   5344         SOC_REG_FLAG_64_BITS,
   5345         0,
   5346         6,
   5347         soc_BKPMETERINGCONFIG_64r_fields,
   5348         SOC_RESET_VAL_DEC(0x00000000, 0x00000018)
   5349         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5350         -1,
   5351         56,
   5352     },
   5353 #endif /* chips */
   5354 
   5355 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   5356     defined(BCM_56450_B1)
   5357     { /* SOC_REG_INT_BKPMETERINGCONFIG_64_BCM56450_A0r */
   5358         soc_block_list[4],
   5359         soc_portreg,
   5360         1,
   5361         0,
   5362         0x24000000,
   5363         SOC_REG_FLAG_64_BITS,
   5364         0,
   5365         6,
   5366         soc_BKPMETERINGCONFIG_64_BCM56640_A0r_fields,
   5367         SOC_RESET_VAL_DEC(0x00000000, 0x00000018)
   5368         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5369         -1,
   5370         77,
   5371     },
   5372 #endif /* chips */
   5373 
   5374 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5375     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5376     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5377     { /* SOC_REG_INT_BKPMETERINGCONFIG_64_BCM56634_A0r */
   5378         soc_block_list[4],
   5379         soc_portreg,
   5380         1,
   5381         0,
   5382         0x9000000,
   5383         SOC_REG_FLAG_64_BITS,
   5384         0,
   5385         6,
   5386         soc_BKPMETERINGCONFIG_64r_fields,
   5387         SOC_RESET_VAL_DEC(0x00000000, 0x00000018)
   5388         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5389         -1,
   5390         16,
   5391     },
   5392 #endif /* chips */
   5393 
   5394 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5395     { /* SOC_REG_INT_BKPMETERINGCONFIG_64_BCM56640_A0r */
   5396         soc_block_list[4],
   5397         soc_portreg,
   5398         1,
   5399         0,
   5400         0x24000000,
   5401         SOC_REG_FLAG_64_BITS,
   5402         0,
   5403         6,
   5404         soc_BKPMETERINGCONFIG_64_BCM56640_A0r_fields,
   5405         SOC_RESET_VAL_DEC(0x00000000, 0x00000018)
   5406         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5407         -1,
   5408         59,
   5409     },
   5410 #endif /* chips */
   5411 
   5412 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5413     { /* SOC_REG_INT_BKPMETERINGCONFIG_64_BCM56840_A0r */
   5414         soc_block_list[4],
   5415         soc_portreg,
   5416         1,
   5417         0,
   5418         0x9000000,
   5419         SOC_REG_FLAG_64_BITS,
   5420         0,
   5421         6,
   5422         soc_BKPMETERINGCONFIG_64r_fields,
   5423         SOC_RESET_VAL_DEC(0x00000000, 0x00000018)
   5424         SOC_RESET_MASK_DEC(0xffffffff, 0x0000003f)
   5425         -1,
   5426         37,
   5427     },
   5428 #endif /* chips */
   5429 
   5430 #if defined(BCM_53400_A0)
   5431     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM53400_A0r */
   5432         soc_block_list[4],
   5433         soc_portreg,
   5434         1,
   5435         0,
   5436         0x500,
   5437         0,
   5438         0,
   5439         2,
   5440         soc_BKPMETERINGCONFIG_BCM53400_A0r_fields,
   5441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5442         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5443         -1,
   5444         79,
   5445     },
   5446 #endif /* chips */
   5447 
   5448 #if defined(BCM_53540_A0)
   5449     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM53540_A0r */
   5450         soc_block_list[4],
   5451         soc_portreg,
   5452         1,
   5453         0,
   5454         0x1000,
   5455         0,
   5456         0,
   5457         2,
   5458         soc_BKPMETERINGCONFIG_BCM53400_A0r_fields,
   5459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5460         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5461         -1,
   5462         91,
   5463     },
   5464 #endif /* chips */
   5465 
   5466 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5467     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM53570_A0r */
   5468         soc_block_list[4],
   5469         soc_portreg,
   5470         1,
   5471         0,
   5472         0x1800,
   5473         0,
   5474         0,
   5475         2,
   5476         soc_BKPMETERINGCONFIG_BCM53400_A0r_fields,
   5477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5478         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5479         -1,
   5480         101,
   5481     },
   5482 #endif /* chips */
   5483 
   5484 #if defined(BCM_56150_A0)
   5485     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM56150_A0r */
   5486         soc_block_list[4],
   5487         soc_portreg,
   5488         1,
   5489         0,
   5490         0x500,
   5491         0,
   5492         0,
   5493         2,
   5494         soc_BKPMETERINGCONFIG_BCM56150_A0r_fields,
   5495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5496         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5497         -1,
   5498         79,
   5499     },
   5500 #endif /* chips */
   5501 
   5502 #if defined(BCM_56160_A0)
   5503     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM56160_A0r */
   5504         soc_block_list[4],
   5505         soc_portreg,
   5506         1,
   5507         0,
   5508         0x500,
   5509         0,
   5510         0,
   5511         2,
   5512         soc_BKPMETERINGCONFIG_BCM53400_A0r_fields,
   5513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5514         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5515         -1,
   5516         91,
   5517     },
   5518 #endif /* chips */
   5519 
   5520 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5521     defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   5522     defined(BCM_56224_B0)
   5523     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM56224_A0r */
   5524         soc_block_list[4],
   5525         soc_portreg,
   5526         1,
   5527         0,
   5528         0x5,
   5529         0,
   5530         0,
   5531         2,
   5532         soc_BKPMETERINGCONFIG_BCM56514_A0r_fields,
   5533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5534         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5535         -1,
   5536         -1,
   5537     },
   5538 #endif /* chips */
   5539 
   5540 #if defined(BCM_56314_A0)
   5541     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM56314_A0r */
   5542         soc_block_list[4],
   5543         soc_portreg,
   5544         1,
   5545         0,
   5546         0xa,
   5547         0,
   5548         0,
   5549         7,
   5550         soc_BKPMETERINGCONFIG_BCM56314_A0r_fields,
   5551         SOC_RESET_VAL_DEC(0x08000000, 0x00000000)
   5552         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5553         -1,
   5554         -1,
   5555     },
   5556 #endif /* chips */
   5557 
   5558 #if defined(BCM_56514_A0)
   5559     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM56514_A0r */
   5560         soc_block_list[4],
   5561         soc_portreg,
   5562         1,
   5563         0,
   5564         0xa,
   5565         0,
   5566         0,
   5567         2,
   5568         soc_BKPMETERINGCONFIG_BCM56514_A0r_fields,
   5569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5570         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   5571         -1,
   5572         -1,
   5573     },
   5574 #endif /* chips */
   5575 
   5576 #if defined(BCM_56800_A0)
   5577     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM56800_A0r */
   5578         soc_block_list[4],
   5579         soc_portreg,
   5580         1,
   5581         0,
   5582         0x9000000,
   5583         0,
   5584         0,
   5585         5,
   5586         soc_BKPMETERINGCONFIGr_fields,
   5587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5588         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
   5589         -1,
   5590         -1,
   5591     },
   5592 #endif /* chips */
   5593 
   5594 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) || \
   5595     defined(BCM_88732_A0)
   5596     { /* SOC_REG_INT_BKPMETERINGCONFIG_BCM56820_A0r */
   5597         soc_block_list[4],
   5598         soc_portreg,
   5599         1,
   5600         0,
   5601         0x9000000,
   5602         0,
   5603         0,
   5604         5,
   5605         soc_BKPMETERINGCONFIG_BCM56820_A0r_fields,
   5606         SOC_RESET_VAL_DEC(0x00030000, 0x00000000)
   5607         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   5608         -1,
   5609         -1,
   5610     },
   5611 #endif /* chips */
   5612 
   5613 #if defined(BCM_56514_A0)
   5614     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXTr */
   5615         soc_block_list[4],
   5616         soc_portreg,
   5617         1,
   5618         0,
   5619         0xb,
   5620         0,
   5621         0,
   5622         5,
   5623         soc_BKPMETERINGCONFIG_EXTr_fields,
   5624         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5625         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5626         -1,
   5627         -1,
   5628     },
   5629 #endif /* chips */
   5630 
   5631 #if defined(BCM_53400_A0)
   5632     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXT_BCM53400_A0r */
   5633         soc_block_list[4],
   5634         soc_portreg,
   5635         1,
   5636         0,
   5637         0x600,
   5638         0,
   5639         0,
   5640         5,
   5641         soc_BKPMETERINGCONFIG_EXT_BCM53400_A0r_fields,
   5642         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5643         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5644         -1,
   5645         79,
   5646     },
   5647 #endif /* chips */
   5648 
   5649 #if defined(BCM_53540_A0)
   5650     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXT_BCM53540_A0r */
   5651         soc_block_list[4],
   5652         soc_portreg,
   5653         1,
   5654         0,
   5655         0x1800,
   5656         0,
   5657         0,
   5658         5,
   5659         soc_BKPMETERINGCONFIG_EXT_BCM53400_A0r_fields,
   5660         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5661         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5662         -1,
   5663         91,
   5664     },
   5665 #endif /* chips */
   5666 
   5667 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5668     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXT_BCM53570_A0r */
   5669         soc_block_list[4],
   5670         soc_portreg,
   5671         1,
   5672         0,
   5673         0x2000,
   5674         0,
   5675         0,
   5676         5,
   5677         soc_BKPMETERINGCONFIG_EXT_BCM53400_A0r_fields,
   5678         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5679         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5680         -1,
   5681         101,
   5682     },
   5683 #endif /* chips */
   5684 
   5685 #if defined(BCM_56142_A0)
   5686     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXT_BCM56142_A0r */
   5687         soc_block_list[4],
   5688         soc_portreg,
   5689         1,
   5690         0,
   5691         0x6,
   5692         0,
   5693         0,
   5694         5,
   5695         soc_BKPMETERINGCONFIG_EXTr_fields,
   5696         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5697         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5698         -1,
   5699         -1,
   5700     },
   5701 #endif /* chips */
   5702 
   5703 #if defined(BCM_56150_A0)
   5704     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXT_BCM56150_A0r */
   5705         soc_block_list[4],
   5706         soc_portreg,
   5707         1,
   5708         0,
   5709         0x600,
   5710         0,
   5711         0,
   5712         5,
   5713         soc_BKPMETERINGCONFIG_EXT_BCM56150_A0r_fields,
   5714         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5715         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5716         -1,
   5717         79,
   5718     },
   5719 #endif /* chips */
   5720 
   5721 #if defined(BCM_56160_A0)
   5722     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXT_BCM56160_A0r */
   5723         soc_block_list[4],
   5724         soc_portreg,
   5725         1,
   5726         0,
   5727         0x600,
   5728         0,
   5729         0,
   5730         5,
   5731         soc_BKPMETERINGCONFIG_EXT_BCM53400_A0r_fields,
   5732         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5733         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5734         -1,
   5735         91,
   5736     },
   5737 #endif /* chips */
   5738 
   5739 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \
   5740     defined(BCM_56224_A0) || defined(BCM_56224_B0)
   5741     { /* SOC_REG_INT_BKPMETERINGCONFIG_EXT_BCM56224_A0r */
   5742         soc_block_list[4],
   5743         soc_portreg,
   5744         1,
   5745         0,
   5746         0xa4,
   5747         0,
   5748         0,
   5749         5,
   5750         soc_BKPMETERINGCONFIG_EXTr_fields,
   5751         SOC_RESET_VAL_DEC(0x00000020, 0x00000000)
   5752         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   5753         -1,
   5754         -1,
   5755     },
   5756 #endif /* chips */
   5757 
   5758 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   5759     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   5760     { /* SOC_REG_INT_BKPMETERINGDISCSTATUSr */
   5761         soc_block_list[4],
   5762         soc_genreg,
   5763         1,
   5764         0,
   5765         0x80006,
   5766         SOC_REG_FLAG_RO,
   5767         0,
   5768         1,
   5769         soc_BKPMETERINGDISCSTATUSr_fields,
   5770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5771         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   5772         -1,
   5773         -1,
   5774     },
   5775 #endif /* chips */
   5776 
   5777 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   5778     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS0r */
   5779         soc_block_list[4],
   5780         soc_genreg,
   5781         1,
   5782         0,
   5783         0x26001500,
   5784         SOC_REG_FLAG_64_BITS |
   5785                           SOC_REG_FLAG_RO,
   5786         0,
   5787         1,
   5788         soc_BKPMETERINGDISCSTATUS0r_fields,
   5789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5790         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   5791         -1,
   5792         -1,
   5793     },
   5794 #endif /* chips */
   5795 
   5796 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   5797     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS1r */
   5798         soc_block_list[4],
   5799         soc_genreg,
   5800         1,
   5801         0,
   5802         0x26001600,
   5803         SOC_REG_FLAG_64_BITS |
   5804                           SOC_REG_FLAG_RO,
   5805         0,
   5806         1,
   5807         soc_BKPMETERINGDISCSTATUS0r_fields,
   5808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5809         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   5810         -1,
   5811         -1,
   5812     },
   5813 #endif /* chips */
   5814 
   5815 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5816     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS0_64r */
   5817         soc_block_list[4],
   5818         soc_genreg,
   5819         1,
   5820         0,
   5821         0x9080014,
   5822         SOC_REG_FLAG_64_BITS |
   5823                           SOC_REG_FLAG_RO,
   5824         0,
   5825         1,
   5826         soc_BKPMETERINGDISCSTATUS0_64r_fields,
   5827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5828         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   5829         -1,
   5830         -1,
   5831     },
   5832 #endif /* chips */
   5833 
   5834 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   5835     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS0_64_BCM56640_A0r */
   5836         soc_block_list[4],
   5837         soc_genreg,
   5838         1,
   5839         0,
   5840         0x26001400,
   5841         SOC_REG_FLAG_64_BITS |
   5842                           SOC_REG_FLAG_RO,
   5843         0,
   5844         1,
   5845         soc_BKPMETERINGDISCSTATUS0_64_BCM56640_A0r_fields,
   5846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5847         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
   5848         -1,
   5849         -1,
   5850     },
   5851 #endif /* chips */
   5852 
   5853 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   5854     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS0_BCM56560_A0r */
   5855         soc_block_list[4],
   5856         soc_genreg,
   5857         1,
   5858         0,
   5859         0x26001500,
   5860         SOC_REG_FLAG_64_BITS |
   5861                           SOC_REG_FLAG_RO,
   5862         0,
   5863         1,
   5864         soc_BKPMETERINGDISCSTATUS0_BCM56560_A0r_fields,
   5865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5866         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   5867         -1,
   5868         -1,
   5869     },
   5870 #endif /* chips */
   5871 
   5872 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   5873     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS1_64r */
   5874         soc_block_list[4],
   5875         soc_genreg,
   5876         1,
   5877         0,
   5878         0x9080016,
   5879         SOC_REG_FLAG_64_BITS |
   5880                           SOC_REG_FLAG_RO,
   5881         0,
   5882         1,
   5883         soc_BKPMETERINGDISCSTATUS0_64r_fields,
   5884         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5885         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   5886         -1,
   5887         -1,
   5888     },
   5889 #endif /* chips */
   5890 
   5891 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   5892     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS1_BCM56560_A0r */
   5893         soc_block_list[4],
   5894         soc_genreg,
   5895         1,
   5896         0,
   5897         0x26001600,
   5898         SOC_REG_FLAG_64_BITS |
   5899                           SOC_REG_FLAG_RO,
   5900         0,
   5901         1,
   5902         soc_BKPMETERINGDISCSTATUS1r_fields,
   5903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5904         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   5905         -1,
   5906         -1,
   5907     },
   5908 #endif /* chips */
   5909 
   5910 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5911     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_0r */
   5912         soc_block_list[4],
   5913         soc_genreg,
   5914         1,
   5915         0,
   5916         0x2033600,
   5917         SOC_REG_FLAG_RO,
   5918         0,
   5919         1,
   5920         soc_BKPMETERINGDISCSTATUS_BCM56160_A0r_fields,
   5921         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   5922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5923         -1,
   5924         -1,
   5925     },
   5926 #endif /* chips */
   5927 
   5928 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5929     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_1r */
   5930         soc_block_list[4],
   5931         soc_genreg,
   5932         1,
   5933         0,
   5934         0x2033700,
   5935         SOC_REG_FLAG_RO,
   5936         0,
   5937         1,
   5938         soc_BKPMETERINGSTATUS_BCM56160_A0r_fields,
   5939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   5941         -1,
   5942         -1,
   5943     },
   5944 #endif /* chips */
   5945 
   5946 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   5947     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_2r */
   5948         soc_block_list[4],
   5949         soc_genreg,
   5950         1,
   5951         0,
   5952         0x2033800,
   5953         SOC_REG_FLAG_RO,
   5954         0,
   5955         1,
   5956         soc_BKPMETERINGDISCSTATUS_2r_fields,
   5957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5958         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   5959         -1,
   5960         -1,
   5961     },
   5962 #endif /* chips */
   5963 
   5964 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   5965     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   5966     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   5967     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   5968     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   5969     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_64r */
   5970         soc_block_list[4],
   5971         soc_genreg,
   5972         1,
   5973         0,
   5974         0x9080011,
   5975         SOC_REG_FLAG_64_BITS |
   5976                           SOC_REG_FLAG_RO,
   5977         0,
   5978         1,
   5979         soc_BKPMETERINGDISCSTATUS_64r_fields,
   5980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   5981         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   5982         -1,
   5983         -1,
   5984     },
   5985 #endif /* chips */
   5986 
   5987 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   5988     defined(BCM_56270_A0)
   5989     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_64_BCM56260_A0r */
   5990         soc_block_list[4],
   5991         soc_genreg,
   5992         1,
   5993         0,
   5994         0x26001400,
   5995         SOC_REG_FLAG_64_BITS |
   5996                           SOC_REG_FLAG_RO,
   5997         0,
   5998         1,
   5999         soc_BKPMETERINGSTATUS_BCM53400_A0r_fields,
   6000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6001         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6002         -1,
   6003         -1,
   6004     },
   6005 #endif /* chips */
   6006 
   6007 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6008     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_64_BCM56440_A0r */
   6009         soc_block_list[4],
   6010         soc_genreg,
   6011         1,
   6012         0,
   6013         0x9080014,
   6014         SOC_REG_FLAG_64_BITS |
   6015                           SOC_REG_FLAG_RO,
   6016         0,
   6017         1,
   6018         soc_BKPMETERINGDISCSTATUS_64_BCM56440_A0r_fields,
   6019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6020         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
   6021         -1,
   6022         -1,
   6023     },
   6024 #endif /* chips */
   6025 
   6026 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6027     defined(BCM_56450_B1)
   6028     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_64_BCM56450_A0r */
   6029         soc_block_list[4],
   6030         soc_genreg,
   6031         1,
   6032         0,
   6033         0x26001400,
   6034         SOC_REG_FLAG_64_BITS |
   6035                           SOC_REG_FLAG_RO,
   6036         0,
   6037         1,
   6038         soc_BKPMETERINGDISCSTATUS_64_BCM56450_A0r_fields,
   6039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6040         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
   6041         -1,
   6042         -1,
   6043     },
   6044 #endif /* chips */
   6045 
   6046 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   6047     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM53314_A0r */
   6048         soc_block_list[4],
   6049         soc_genreg,
   6050         1,
   6051         0,
   6052         0x80004,
   6053         SOC_REG_FLAG_RO,
   6054         0,
   6055         1,
   6056         soc_BKPMETERINGDISCSTATUS_BCM53314_A0r_fields,
   6057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6058         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   6059         -1,
   6060         -1,
   6061     },
   6062 #endif /* chips */
   6063 
   6064 #if defined(BCM_53400_A0)
   6065     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM53400_A0r */
   6066         soc_block_list[4],
   6067         soc_genreg,
   6068         1,
   6069         0,
   6070         0x2024400,
   6071         SOC_REG_FLAG_RO,
   6072         0,
   6073         1,
   6074         soc_BKPMETERINGDISCSTATUS_BCM53400_A0r_fields,
   6075         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   6076         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6077         -1,
   6078         -1,
   6079     },
   6080 #endif /* chips */
   6081 
   6082 #if defined(BCM_53540_A0)
   6083     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM53540_A0r */
   6084         soc_block_list[4],
   6085         soc_genreg,
   6086         1,
   6087         0,
   6088         0x2024000,
   6089         SOC_REG_FLAG_RO,
   6090         0,
   6091         1,
   6092         soc_BKPMETERINGDISCSTATUS_BCM56160_A0r_fields,
   6093         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   6094         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6095         -1,
   6096         -1,
   6097     },
   6098 #endif /* chips */
   6099 
   6100 #if defined(BCM_56142_A0)
   6101     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM56142_A0r */
   6102         soc_block_list[4],
   6103         soc_genreg,
   6104         1,
   6105         0,
   6106         0x80004,
   6107         SOC_REG_FLAG_RO,
   6108         0,
   6109         1,
   6110         soc_BKPMETERINGDISCSTATUS_BCM56142_A0r_fields,
   6111         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   6112         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6113         -1,
   6114         -1,
   6115     },
   6116 #endif /* chips */
   6117 
   6118 #if defined(BCM_56150_A0)
   6119     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM56150_A0r */
   6120         soc_block_list[4],
   6121         soc_genreg,
   6122         1,
   6123         0,
   6124         0x2024400,
   6125         SOC_REG_FLAG_RO,
   6126         0,
   6127         1,
   6128         soc_BKPMETERINGDISCSTATUS_BCM56150_A0r_fields,
   6129         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   6130         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6131         -1,
   6132         -1,
   6133     },
   6134 #endif /* chips */
   6135 
   6136 #if defined(BCM_56160_A0)
   6137     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM56160_A0r */
   6138         soc_block_list[4],
   6139         soc_genreg,
   6140         1,
   6141         0,
   6142         0x2024400,
   6143         SOC_REG_FLAG_RO,
   6144         0,
   6145         1,
   6146         soc_BKPMETERINGDISCSTATUS_BCM56160_A0r_fields,
   6147         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   6148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6149         -1,
   6150         -1,
   6151     },
   6152 #endif /* chips */
   6153 
   6154 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   6155     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM56224_A0r */
   6156         soc_block_list[4],
   6157         soc_genreg,
   6158         1,
   6159         0,
   6160         0x80004,
   6161         SOC_REG_FLAG_RO,
   6162         0,
   6163         1,
   6164         soc_BKPMETERINGDISCSTATUS_BCM56224_A0r_fields,
   6165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6166         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6167         -1,
   6168         -1,
   6169     },
   6170 #endif /* chips */
   6171 
   6172 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6173     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM56334_A0r */
   6174         soc_block_list[4],
   6175         soc_genreg,
   6176         1,
   6177         0,
   6178         0x9080011,
   6179         SOC_REG_FLAG_RO,
   6180         0,
   6181         1,
   6182         soc_BKPMETERINGDISCSTATUS_BCM56224_A0r_fields,
   6183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6184         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6185         -1,
   6186         -1,
   6187     },
   6188 #endif /* chips */
   6189 
   6190 #if defined(BCM_56800_A0)
   6191     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM56800_A0r */
   6192         soc_block_list[4],
   6193         soc_genreg,
   6194         1,
   6195         0,
   6196         0x9080011,
   6197         SOC_REG_FLAG_RO,
   6198         0,
   6199         1,
   6200         soc_BKPMETERINGDISCSTATUS_BCM56800_A0r_fields,
   6201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6202         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   6203         -1,
   6204         -1,
   6205     },
   6206 #endif /* chips */
   6207 
   6208 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6209     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM56820_A0r */
   6210         soc_block_list[4],
   6211         soc_genreg,
   6212         1,
   6213         0,
   6214         0x9080014,
   6215         SOC_REG_FLAG_RO,
   6216         0,
   6217         1,
   6218         soc_BKPMETERINGDISCSTATUSr_fields,
   6219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6220         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   6221         -1,
   6222         -1,
   6223     },
   6224 #endif /* chips */
   6225 
   6226 #if defined(BCM_88732_A0)
   6227     { /* SOC_REG_INT_BKPMETERINGDISCSTATUS_BCM88732_A0r */
   6228         soc_block_list[4],
   6229         soc_genreg,
   6230         1,
   6231         0,
   6232         0x9080014,
   6233         SOC_REG_FLAG_RO,
   6234         0,
   6235         1,
   6236         soc_BKPMETERINGDISCSTATUS_BCM88732_A0r_fields,
   6237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6238         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   6239         -1,
   6240         -1,
   6241     },
   6242 #endif /* chips */
   6243 
   6244 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   6245     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   6246     { /* SOC_REG_INT_BKPMETERINGSTATUSr */
   6247         soc_block_list[4],
   6248         soc_genreg,
   6249         1,
   6250         0,
   6251         0x80003,
   6252         SOC_REG_FLAG_RO,
   6253         0,
   6254         1,
   6255         soc_BKPMETERINGDISCSTATUSr_fields,
   6256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6257         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   6258         -1,
   6259         -1,
   6260     },
   6261 #endif /* chips */
   6262 
   6263 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6264     { /* SOC_REG_INT_BKPMETERINGSTATUS_0r */
   6265         soc_block_list[4],
   6266         soc_genreg,
   6267         1,
   6268         0,
   6269         0x2032c00,
   6270         SOC_REG_FLAG_RO,
   6271         0,
   6272         1,
   6273         soc_BKPMETERINGSTATUS_BCM56160_A0r_fields,
   6274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6276         -1,
   6277         -1,
   6278     },
   6279 #endif /* chips */
   6280 
   6281 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6282     { /* SOC_REG_INT_BKPMETERINGSTATUS_1r */
   6283         soc_block_list[4],
   6284         soc_genreg,
   6285         1,
   6286         0,
   6287         0x2032d00,
   6288         SOC_REG_FLAG_RO,
   6289         0,
   6290         1,
   6291         soc_BKPMETERINGSTATUS_BCM56160_A0r_fields,
   6292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6293         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6294         -1,
   6295         -1,
   6296     },
   6297 #endif /* chips */
   6298 
   6299 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6300     { /* SOC_REG_INT_BKPMETERINGSTATUS_2r */
   6301         soc_block_list[4],
   6302         soc_genreg,
   6303         1,
   6304         0,
   6305         0x2032e00,
   6306         SOC_REG_FLAG_RO,
   6307         0,
   6308         1,
   6309         soc_BKPMETERINGDISCSTATUS_2r_fields,
   6310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6311         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   6312         -1,
   6313         -1,
   6314     },
   6315 #endif /* chips */
   6316 
   6317 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   6318     { /* SOC_REG_INT_BKPMETERINGSTATUS_BCM53314_A0r */
   6319         soc_block_list[4],
   6320         soc_genreg,
   6321         1,
   6322         0,
   6323         0x80002,
   6324         SOC_REG_FLAG_RO,
   6325         0,
   6326         1,
   6327         soc_BKPMETERINGDISCSTATUS_BCM53314_A0r_fields,
   6328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6329         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   6330         -1,
   6331         -1,
   6332     },
   6333 #endif /* chips */
   6334 
   6335 #if defined(BCM_53400_A0)
   6336     { /* SOC_REG_INT_BKPMETERINGSTATUS_BCM53400_A0r */
   6337         soc_block_list[4],
   6338         soc_genreg,
   6339         1,
   6340         0,
   6341         0x2024200,
   6342         SOC_REG_FLAG_RO,
   6343         0,
   6344         1,
   6345         soc_BKPMETERINGSTATUS_BCM53400_A0r_fields,
   6346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6347         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6348         -1,
   6349         -1,
   6350     },
   6351 #endif /* chips */
   6352 
   6353 #if defined(BCM_53540_A0)
   6354     { /* SOC_REG_INT_BKPMETERINGSTATUS_BCM53540_A0r */
   6355         soc_block_list[4],
   6356         soc_genreg,
   6357         1,
   6358         0,
   6359         0x2023800,
   6360         SOC_REG_FLAG_RO,
   6361         0,
   6362         1,
   6363         soc_BKPMETERINGSTATUS_BCM56160_A0r_fields,
   6364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6365         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6366         -1,
   6367         -1,
   6368     },
   6369 #endif /* chips */
   6370 
   6371 #if defined(BCM_53570_A0) || defined(BCM_53570_B0)
   6372     { /* SOC_REG_INT_BKPMETERINGSTATUS_BCM53570_A0r */
   6373         soc_block_list[4],
   6374         soc_genreg,
   6375         1,
   6376         0,
   6377         0x2032400,
   6378         SOC_REG_FLAG_RO,
   6379         0,
   6380         1,
   6381         soc_BKPMETERINGSTATUS_BCM56160_A0r_fields,
   6382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6383         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6384         -1,
   6385         -1,
   6386     },
   6387 #endif /* chips */
   6388 
   6389 #if defined(BCM_56150_A0)
   6390     { /* SOC_REG_INT_BKPMETERINGSTATUS_BCM56150_A0r */
   6391         soc_block_list[4],
   6392         soc_genreg,
   6393         1,
   6394         0,
   6395         0x2024200,
   6396         SOC_REG_FLAG_RO,
   6397         0,
   6398         1,
   6399         soc_BKPMETERINGSTATUSr_fields,
   6400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6401         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6402         -1,
   6403         -1,
   6404     },
   6405 #endif /* chips */
   6406 
   6407 #if defined(BCM_56160_A0)
   6408     { /* SOC_REG_INT_BKPMETERINGSTATUS_BCM56160_A0r */
   6409         soc_block_list[4],
   6410         soc_genreg,
   6411         1,
   6412         0,
   6413         0x2024200,
   6414         SOC_REG_FLAG_RO,
   6415         0,
   6416         1,
   6417         soc_BKPMETERINGSTATUS_BCM56160_A0r_fields,
   6418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   6420         -1,
   6421         -1,
   6422     },
   6423 #endif /* chips */
   6424 
   6425 #if defined(BCM_56142_A0) || defined(BCM_56224_A0) || \
   6426     defined(BCM_56224_B0)
   6427     { /* SOC_REG_INT_BKPMETERINGSTATUS_BCM56224_A0r */
   6428         soc_block_list[4],
   6429         soc_genreg,
   6430         1,
   6431         0,
   6432         0x80002,
   6433         SOC_REG_FLAG_RO,
   6434         0,
   6435         1,
   6436         soc_BKPMETERINGDISCSTATUS_BCM56224_A0r_fields,
   6437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6438         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6439         -1,
   6440         -1,
   6441     },
   6442 #endif /* chips */
   6443 
   6444 #if defined(BCM_56800_A0)
   6445     { /* SOC_REG_INT_BKPMETERINGWARNSTATUSr */
   6446         soc_block_list[4],
   6447         soc_genreg,
   6448         1,
   6449         0,
   6450         0x9080010,
   6451         SOC_REG_FLAG_RO,
   6452         0,
   6453         1,
   6454         soc_BKPMETERINGDISCSTATUS_BCM56800_A0r_fields,
   6455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6456         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
   6457         -1,
   6458         -1,
   6459     },
   6460 #endif /* chips */
   6461 
   6462 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   6463     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS0r */
   6464         soc_block_list[4],
   6465         soc_genreg,
   6466         1,
   6467         0,
   6468         0x26001000,
   6469         SOC_REG_FLAG_64_BITS |
   6470                           SOC_REG_FLAG_RO,
   6471         0,
   6472         1,
   6473         soc_BKPMETERINGDISCSTATUS0r_fields,
   6474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6475         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   6476         -1,
   6477         -1,
   6478     },
   6479 #endif /* chips */
   6480 
   6481 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
   6482     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS1r */
   6483         soc_block_list[4],
   6484         soc_genreg,
   6485         1,
   6486         0,
   6487         0x26001100,
   6488         SOC_REG_FLAG_64_BITS |
   6489                           SOC_REG_FLAG_RO,
   6490         0,
   6491         1,
   6492         soc_BKPMETERINGDISCSTATUS0r_fields,
   6493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6494         SOC_RESET_MASK_DEC(0xffffffff, 0x001fffff)
   6495         -1,
   6496         -1,
   6497     },
   6498 #endif /* chips */
   6499 
   6500 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6501     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS0_64r */
   6502         soc_block_list[4],
   6503         soc_genreg,
   6504         1,
   6505         0,
   6506         0x9080010,
   6507         SOC_REG_FLAG_64_BITS |
   6508                           SOC_REG_FLAG_RO,
   6509         0,
   6510         1,
   6511         soc_BKPMETERINGWARNSTATUS0_64r_fields,
   6512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6513         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
   6514         -1,
   6515         -1,
   6516     },
   6517 #endif /* chips */
   6518 
   6519 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
   6520     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS0_64_BCM56640_A0r */
   6521         soc_block_list[4],
   6522         soc_genreg,
   6523         1,
   6524         0,
   6525         0x26001000,
   6526         SOC_REG_FLAG_64_BITS |
   6527                           SOC_REG_FLAG_RO,
   6528         0,
   6529         1,
   6530         soc_BKPMETERINGDISCSTATUS0_64_BCM56640_A0r_fields,
   6531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6532         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
   6533         -1,
   6534         -1,
   6535     },
   6536 #endif /* chips */
   6537 
   6538 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6539     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS0_BCM56560_A0r */
   6540         soc_block_list[4],
   6541         soc_genreg,
   6542         1,
   6543         0,
   6544         0x26001000,
   6545         SOC_REG_FLAG_64_BITS |
   6546                           SOC_REG_FLAG_RO,
   6547         0,
   6548         1,
   6549         soc_BKPMETERINGDISCSTATUS0_BCM56560_A0r_fields,
   6550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6551         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   6552         -1,
   6553         -1,
   6554     },
   6555 #endif /* chips */
   6556 
   6557 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
   6558     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS1_64r */
   6559         soc_block_list[4],
   6560         soc_genreg,
   6561         1,
   6562         0,
   6563         0x9080012,
   6564         SOC_REG_FLAG_64_BITS |
   6565                           SOC_REG_FLAG_RO,
   6566         0,
   6567         1,
   6568         soc_BKPMETERINGDISCSTATUS0_64r_fields,
   6569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6570         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   6571         -1,
   6572         -1,
   6573     },
   6574 #endif /* chips */
   6575 
   6576 #if defined(BCM_56560_A0) || defined(BCM_56560_B0)
   6577     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS1_BCM56560_A0r */
   6578         soc_block_list[4],
   6579         soc_genreg,
   6580         1,
   6581         0,
   6582         0x26001100,
   6583         SOC_REG_FLAG_64_BITS |
   6584                           SOC_REG_FLAG_RO,
   6585         0,
   6586         1,
   6587         soc_BKPMETERINGDISCSTATUS1r_fields,
   6588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6589         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
   6590         -1,
   6591         -1,
   6592     },
   6593 #endif /* chips */
   6594 
   6595 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
   6596     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6597     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
   6598     defined(BCM_56680_A0) || defined(BCM_56680_B0) || \
   6599     defined(BCM_56685_A0) || defined(BCM_56685_B0)
   6600     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS_64r */
   6601         soc_block_list[4],
   6602         soc_genreg,
   6603         1,
   6604         0,
   6605         0x9080010,
   6606         SOC_REG_FLAG_64_BITS |
   6607                           SOC_REG_FLAG_RO,
   6608         0,
   6609         1,
   6610         soc_BKPMETERINGDISCSTATUS_64r_fields,
   6611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6612         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
   6613         -1,
   6614         -1,
   6615     },
   6616 #endif /* chips */
   6617 
   6618 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
   6619     defined(BCM_56270_A0)
   6620     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS_64_BCM56260_A0r */
   6621         soc_block_list[4],
   6622         soc_genreg,
   6623         1,
   6624         0,
   6625         0x26001000,
   6626         SOC_REG_FLAG_64_BITS |
   6627                           SOC_REG_FLAG_RO,
   6628         0,
   6629         1,
   6630         soc_BKPMETERINGSTATUS_BCM53400_A0r_fields,
   6631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6632         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6633         -1,
   6634         -1,
   6635     },
   6636 #endif /* chips */
   6637 
   6638 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
   6639     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS_64_BCM56440_A0r */
   6640         soc_block_list[4],
   6641         soc_genreg,
   6642         1,
   6643         0,
   6644         0x9080010,
   6645         SOC_REG_FLAG_64_BITS |
   6646                           SOC_REG_FLAG_RO,
   6647         0,
   6648         1,
   6649         soc_BKPMETERINGDISCSTATUS_64_BCM56440_A0r_fields,
   6650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6651         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
   6652         -1,
   6653         -1,
   6654     },
   6655 #endif /* chips */
   6656 
   6657 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
   6658     defined(BCM_56450_B1)
   6659     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS_64_BCM56450_A0r */
   6660         soc_block_list[4],
   6661         soc_genreg,
   6662         1,
   6663         0,
   6664         0x26001000,
   6665         SOC_REG_FLAG_64_BITS |
   6666                           SOC_REG_FLAG_RO,
   6667         0,
   6668         1,
   6669         soc_BKPMETERINGDISCSTATUS_64_BCM56450_A0r_fields,
   6670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6671         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
   6672         -1,
   6673         -1,
   6674     },
   6675 #endif /* chips */
   6676 
   6677 #if defined(BCM_56334_A0) || defined(BCM_56334_B0)
   6678     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS_BCM56334_A0r */
   6679         soc_block_list[4],
   6680         soc_genreg,
   6681         1,
   6682         0,
   6683         0x9080010,
   6684         SOC_REG_FLAG_RO,
   6685         0,
   6686         1,
   6687         soc_BKPMETERINGDISCSTATUS_BCM56224_A0r_fields,
   6688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6689         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
   6690         -1,
   6691         -1,
   6692     },
   6693 #endif /* chips */
   6694 
   6695 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6696     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS_BCM56820_A0r */
   6697         soc_block_list[4],
   6698         soc_genreg,
   6699         1,
   6700         0,
   6701         0x9080010,
   6702         SOC_REG_FLAG_RO,
   6703         0,
   6704         1,
   6705         soc_BKPMETERINGDISCSTATUSr_fields,
   6706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6707         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
   6708         -1,
   6709         -1,
   6710     },
   6711 #endif /* chips */
   6712 
   6713 #if defined(BCM_88732_A0)
   6714     { /* SOC_REG_INT_BKPMETERINGWARNSTATUS_BCM88732_A0r */
   6715         soc_block_list[4],
   6716         soc_genreg,
   6717         1,
   6718         0,
   6719         0x9080010,
   6720         SOC_REG_FLAG_RO,
   6721         0,
   6722         1,
   6723         soc_BKPMETERINGDISCSTATUS_BCM88732_A0r_fields,
   6724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6725         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   6726         -1,
   6727         -1,
   6728     },
   6729 #endif /* chips */
   6730 
   6731 #if defined(BCM_88732_A0)
   6732     { /* SOC_REG_INT_BKP_CONFIGr */
   6733         soc_block_list[5],
   6734         soc_genreg,
   6735         1,
   6736         0,
   6737         0x8010b,
   6738         0,
   6739         0,
   6740         2,
   6741         soc_BKP_CONFIGr_fields,
   6742         SOC_RESET_VAL_DEC(0x000a3b80, 0x00000000)
   6743         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
   6744         -1,
   6745         -1,
   6746     },
   6747 #endif /* chips */
   6748 
   6749 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
   6750     defined(BCM_56504_B0) || defined(BCM_56514_A0)
   6751     { /* SOC_REG_INT_BKP_DISC_BMAPr */
   6752         soc_block_list[5],
   6753         soc_genreg,
   6754         1,
   6755         0,
   6756         0xe08010c,
   6757         0,
   6758         0,
   6759         1,
   6760         soc_BKP_DISC_BMAPr_fields,
   6761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6763         -1,
   6764         -1,
   6765     },
   6766 #endif /* chips */
   6767 
   6768 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   6769     { /* SOC_REG_INT_BKP_DISC_BMAP_BCM53314_A0r */
   6770         soc_block_list[5],
   6771         soc_genreg,
   6772         1,
   6773         0,
   6774         0xf080112,
   6775         0,
   6776         0,
   6777         1,
   6778         soc_BKP_DISC_BMAP_BCM53314_A0r_fields,
   6779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6781         -1,
   6782         -1,
   6783     },
   6784 #endif /* chips */
   6785 
   6786 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   6787     { /* SOC_REG_INT_BKP_DISC_BMAP_BCM56224_A0r */
   6788         soc_block_list[5],
   6789         soc_genreg,
   6790         1,
   6791         0,
   6792         0xf080112,
   6793         0,
   6794         0,
   6795         1,
   6796         soc_BKP_DISC_BMAP_BCM56224_A0r_fields,
   6797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6798         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6799         -1,
   6800         -1,
   6801     },
   6802 #endif /* chips */
   6803 
   6804 #if defined(BCM_56224_A0) || defined(BCM_56224_B0)
   6805     { /* SOC_REG_INT_BKP_DISC_BMAP_HIr */
   6806         soc_block_list[5],
   6807         soc_genreg,
   6808         1,
   6809         0,
   6810         0xf080113,
   6811         0,
   6812         0,
   6813         1,
   6814         soc_BKP_DISC_BMAP_HIr_fields,
   6815         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6816         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6817         -1,
   6818         -1,
   6819     },
   6820 #endif /* chips */
   6821 
   6822 #if defined(BCM_53314_A0) || defined(BCM_53324_A0)
   6823     { /* SOC_REG_INT_BKP_DISC_BMAP_HI_BCM53314_A0r */
   6824         soc_block_list[5],
   6825         soc_genreg,
   6826         1,
   6827         0,
   6828         0xf080113,
   6829         0,
   6830         0,
   6831         1,
   6832         soc_BKP_DISC_BMAP_HIr_fields,
   6833         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6834         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6835         -1,
   6836         -1,
   6837     },
   6838 #endif /* chips */
   6839 
   6840 #if defined(BCM_56800_A0)
   6841     { /* SOC_REG_INT_BKP_DISC_PRIORITYr */
   6842         soc_block_list[5],
   6843         soc_portreg,
   6844         1,
   6845         0,
   6846         0xe000063,
   6847         0,
   6848         0,
   6849         1,
   6850         soc_BKP_DISC_PRIORITYr_fields,
   6851         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6852         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6853         -1,
   6854         -1,
   6855     },
   6856 #endif /* chips */
   6857 
   6858 #if defined(BCM_53400_A0) || defined(BCM_53540_A0) || \
   6859     defined(BCM_56160_A0)
   6860     { /* SOC_REG_INT_BKP_DISC_PRIORITY_BCM53400_A0r */
   6861         soc_block_list[5],
   6862         soc_portreg,
   6863         1,
   6864         0,
   6865         0x40001c00,
   6866         0,
   6867         0,
   6868         1,
   6869         soc_BKP_DISC_PRIORITY_BCM53400_A0r_fields,
   6870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6871         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6872         -1,
   6873         -1,
   6874     },
   6875 #endif /* chips */
   6876 
   6877 #if defined(BCM_53570_A0)
   6878     { /* SOC_REG_INT_BKP_DISC_PRIORITY_BCM53570_A0r */
   6879         soc_block_list[5],
   6880         soc_portreg,
   6881         1,
   6882         0,
   6883         0x40004c00,
   6884         0,
   6885         0,
   6886         1,
   6887         soc_BKP_DISC_PRIORITY_BCM53400_A0r_fields,
   6888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6889         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6890         -1,
   6891         -1,
   6892     },
   6893 #endif /* chips */
   6894 
   6895 #if defined(BCM_53570_B0)
   6896     { /* SOC_REG_INT_BKP_DISC_PRIORITY_BCM53570_B0r */
   6897         soc_block_list[5],
   6898         soc_portreg,
   6899         1,
   6900         0,
   6901         0x40005000,
   6902         0,
   6903         0,
   6904         1,
   6905         soc_BKP_DISC_PRIORITY_BCM53400_A0r_fields,
   6906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6907         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6908         -1,
   6909         -1,
   6910     },
   6911 #endif /* chips */
   6912 
   6913 #if defined(BCM_56142_A0)
   6914     { /* SOC_REG_INT_BKP_DISC_PRIORITY_BCM56142_A0r */
   6915         soc_block_list[5],
   6916         soc_portreg,
   6917         1,
   6918         0,
   6919         0x11000080,
   6920         0,
   6921         0,
   6922         1,
   6923         soc_BKP_DISC_PRIORITYr_fields,
   6924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6925         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6926         -1,
   6927         -1,
   6928     },
   6929 #endif /* chips */
   6930 
   6931 #if defined(BCM_56150_A0)
   6932     { /* SOC_REG_INT_BKP_DISC_PRIORITY_BCM56150_A0r */
   6933         soc_block_list[5],
   6934         soc_portreg,
   6935         1,
   6936         0,
   6937         0x44001c00,
   6938         0,
   6939         0,
   6940         1,
   6941         soc_BKP_DISC_PRIORITY_BCM56150_A0r_fields,
   6942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6943         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6944         -1,
   6945         -1,
   6946     },
   6947 #endif /* chips */
   6948 
   6949 #if defined(BCM_56334_A0) || defined(BCM_56334_B0) || \
   6950     defined(BCM_56624_A0) || defined(BCM_56624_B0) || \
   6951     defined(BCM_56680_A0) || defined(BCM_56680_B0)
   6952     { /* SOC_REG_INT_BKP_DISC_PRIORITY_BCM56624_A0r */
   6953         soc_block_list[5],
   6954         soc_portreg,
   6955         1,
   6956         0,
   6957         0x11000063,
   6958         0,
   6959         0,
   6960         1,
   6961         soc_BKP_DISC_PRIORITYr_fields,
   6962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6963         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   6964         -1,
   6965         -1,
   6966     },
   6967 #endif /* chips */
   6968 
   6969 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   6970     { /* SOC_REG_INT_BKP_DISC_PRIORITY_BCM56820_A0r */
   6971         soc_block_list[5],
   6972         soc_portreg,
   6973         1,
   6974         0,
   6975         0xf000063,
   6976         SOC_REG_FLAG_RO,
   6977         0,
   6978         1,
   6979         soc_BKP_DISC_PRIORITY_BCM56820_A0r_fields,
   6980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6981         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   6982         -1,
   6983         -1,
   6984     },
   6985 #endif /* chips */
   6986 
   6987 #if defined(BCM_88732_A0)
   6988     { /* SOC_REG_INT_BKP_STATUSr */
   6989         soc_block_list[5],
   6990         soc_genreg,
   6991         1,
   6992         0,
   6993         0x8010c,
   6994         0,
   6995         0,
   6996         2,
   6997         soc_BKP_STATUSr_fields,
   6998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   6999         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   7000         -1,
   7001         -1,
   7002     },
   7003 #endif /* chips */
   7004 
   7005 #if defined(BCM_83208_A0)
   7006     { /* SOC_REG_INT_BLH_ECC_1B_ERR_CNTr */
   7007         soc_block_list[76],
   7008         soc_genreg,
   7009         1,
   7010         0,
   7011         0x94,
   7012         SOC_REG_FLAG_64_BITS |
   7013                           SOC_REG_FLAG_RO,
   7014         0,
   7015         4,
   7016         soc_AM_TOP_ECC_1B_ERR_CNTr_fields,
   7017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7018         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7019         -1,
   7020         -1,
   7021     },
   7022 #endif /* chips */
   7023 
   7024 #if defined(BCM_83208_A0)
   7025     { /* SOC_REG_INT_BLH_ECC_2B_ERR_CNTr */
   7026         soc_block_list[76],
   7027         soc_genreg,
   7028         1,
   7029         0,
   7030         0x96,
   7031         SOC_REG_FLAG_64_BITS |
   7032                           SOC_REG_FLAG_RO,
   7033         0,
   7034         4,
   7035         soc_AM_TOP_ECC_2B_ERR_CNTr_fields,
   7036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7037         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7038         -1,
   7039         -1,
   7040     },
   7041 #endif /* chips */
   7042 
   7043 #if defined(BCM_83208_A0)
   7044     { /* SOC_REG_INT_BLH_ECC_ERR_1B_INITIATEr */
   7045         soc_block_list[76],
   7046         soc_genreg,
   7047         1,
   7048         0,
   7049         0xa4,
   7050         0,
   7051         0,
   7052         1,
   7053         soc_AM_TOP_ECC_ERR_1B_INITIATEr_fields,
   7054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7055         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7056         -1,
   7057         -1,
   7058     },
   7059 #endif /* chips */
   7060 
   7061 #if defined(BCM_83208_A0)
   7062     { /* SOC_REG_INT_BLH_ECC_ERR_1B_MONITOR_MEM_MASKr */
   7063         soc_block_list[76],
   7064         soc_genreg,
   7065         1,
   7066         0,
   7067         0x9a,
   7068         0,
   7069         0,
   7070         1,
   7071         soc_AM_TOP_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
   7072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7073         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7074         -1,
   7075         -1,
   7076     },
   7077 #endif /* chips */
   7078 
   7079 #if defined(BCM_83208_A0)
   7080     { /* SOC_REG_INT_BLH_ECC_ERR_2B_INITIATEr */
   7081         soc_block_list[76],
   7082         soc_genreg,
   7083         1,
   7084         0,
   7085         0xa6,
   7086         0,
   7087         0,
   7088         1,
   7089         soc_AM_TOP_ECC_ERR_2B_INITIATEr_fields,
   7090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7091         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7092         -1,
   7093         -1,
   7094     },
   7095 #endif /* chips */
   7096 
   7097 #if defined(BCM_83208_A0)
   7098     { /* SOC_REG_INT_BLH_ECC_ERR_2B_MONITOR_MEM_MASKr */
   7099         soc_block_list[76],
   7100         soc_genreg,
   7101         1,
   7102         0,
   7103         0x9c,
   7104         0,
   7105         0,
   7106         1,
   7107         soc_AM_TOP_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
   7108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7109         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7110         -1,
   7111         -1,
   7112     },
   7113 #endif /* chips */
   7114 
   7115 #if defined(BCM_83208_A0)
   7116     { /* SOC_REG_INT_BLH_ECC_INTERRUPT_REGISTERr */
   7117         soc_block_list[76],
   7118         soc_genreg,
   7119         1,
   7120         0,
   7121         0x7,
   7122         SOC_REG_FLAG_INTERRUPT,
   7123         0,
   7124         3,
   7125         soc_AM_TOP_ECC_INTERRUPT_REGISTERr_fields,
   7126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7127         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7128         -1,
   7129         -1,
   7130     },
   7131 #endif /* chips */
   7132 
   7133 #if defined(BCM_83208_A0)
   7134     { /* SOC_REG_INT_BLH_ECC_INTERRUPT_REGISTER_MASKr */
   7135         soc_block_list[76],
   7136         soc_genreg,
   7137         1,
   7138         0,
   7139         0x17,
   7140         0,
   7141         0,
   7142         3,
   7143         soc_AM_TOP_ECC_INTERRUPT_REGISTER_MASKr_fields,
   7144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7145         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7146         -1,
   7147         -1,
   7148     },
   7149 #endif /* chips */
   7150 
   7151 #if defined(BCM_83208_A0)
   7152     { /* SOC_REG_INT_BLH_ECC_INTERRUPT_REGISTER_TESTr */
   7153         soc_block_list[76],
   7154         soc_genreg,
   7155         1,
   7156         0,
   7157         0x1f,
   7158         0,
   7159         0,
   7160         1,
   7161         soc_AM_TOP_ECC_INTERRUPT_REGISTER_TESTr_fields,
   7162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7163         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7164         -1,
   7165         -1,
   7166     },
   7167 #endif /* chips */
   7168 
   7169 #if defined(BCM_83208_A0)
   7170     { /* SOC_REG_INT_BLH_ENABLE_DYNAMIC_MEMORY_ACCESSr */
   7171         soc_block_list[76],
   7172         soc_genreg,
   7173         1,
   7174         0,
   7175         0x84,
   7176         0,
   7177         0,
   7178         1,
   7179         soc_AM_TOP_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
   7180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7181         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7182         -1,
   7183         -1,
   7184     },
   7185 #endif /* chips */
   7186 
   7187 #if defined(BCM_83208_A0)
   7188     { /* SOC_REG_INT_BLH_ERROR_INITIATION_DATAr */
   7189         soc_block_list[76],
   7190         soc_genreg,
   7191         1,
   7192         0,
   7193         0xa3,
   7194         0,
   7195         0,
   7196         1,
   7197         soc_AM_TOP_ERROR_INITIATION_DATAr_fields,
   7198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7199         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7200         -1,
   7201         -1,
   7202     },
   7203 #endif /* chips */
   7204 
   7205 #if defined(BCM_83208_A0)
   7206     { /* SOC_REG_INT_BLH_FSRDCONFIG_ALL_LANES_0r */
   7207         soc_block_list[76],
   7208         soc_genreg,
   7209         1,
   7210         0,
   7211         0x250,
   7212         0,
   7213         0,
   7214         4,
   7215         soc_BLH_FSRDCONFIG_ALL_LANES_0r_fields,
   7216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7217         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
   7218         -1,
   7219         -1,
   7220     },
   7221 #endif /* chips */
   7222 
   7223 #if defined(BCM_83208_A0)
   7224     { /* SOC_REG_INT_BLH_F_0_LN_0_MODE_0r */
   7225         soc_block_list[76],
   7226         soc_genreg,
   7227         1,
   7228         0,
   7229         0x140,
   7230         0,
   7231         0,
   7232         2,
   7233         soc_BLH_F_0_LN_0_MODE_0r_fields,
   7234         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7235         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7236         -1,
   7237         -1,
   7238     },
   7239 #endif /* chips */
   7240 
   7241 #if defined(BCM_83208_A0)
   7242     { /* SOC_REG_INT_BLH_F_0_LN_1_MODE_0r */
   7243         soc_block_list[76],
   7244         soc_genreg,
   7245         1,
   7246         0,
   7247         0x150,
   7248         0,
   7249         0,
   7250         2,
   7251         soc_BLH_F_0_LN_1_MODE_0r_fields,
   7252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7253         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7254         -1,
   7255         -1,
   7256     },
   7257 #endif /* chips */
   7258 
   7259 #if defined(BCM_83208_A0)
   7260     { /* SOC_REG_INT_BLH_F_0_LN_2_MODE_0r */
   7261         soc_block_list[76],
   7262         soc_genreg,
   7263         1,
   7264         0,
   7265         0x160,
   7266         0,
   7267         0,
   7268         2,
   7269         soc_BLH_F_0_LN_2_MODE_0r_fields,
   7270         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7271         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7272         -1,
   7273         -1,
   7274     },
   7275 #endif /* chips */
   7276 
   7277 #if defined(BCM_83208_A0)
   7278     { /* SOC_REG_INT_BLH_F_0_LN_3_MODE_0r */
   7279         soc_block_list[76],
   7280         soc_genreg,
   7281         1,
   7282         0,
   7283         0x170,
   7284         0,
   7285         0,
   7286         2,
   7287         soc_BLH_F_0_LN_3_MODE_0r_fields,
   7288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7289         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7290         -1,
   7291         -1,
   7292     },
   7293 #endif /* chips */
   7294 
   7295 #if defined(BCM_83208_A0)
   7296     { /* SOC_REG_INT_BLH_F_0_LN_4_MODE_0r */
   7297         soc_block_list[76],
   7298         soc_genreg,
   7299         1,
   7300         0,
   7301         0x180,
   7302         0,
   7303         0,
   7304         2,
   7305         soc_BLH_F_0_LN_4_MODE_0r_fields,
   7306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7307         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7308         -1,
   7309         -1,
   7310     },
   7311 #endif /* chips */
   7312 
   7313 #if defined(BCM_83208_A0)
   7314     { /* SOC_REG_INT_BLH_F_0_LN_5_MODE_0r */
   7315         soc_block_list[76],
   7316         soc_genreg,
   7317         1,
   7318         0,
   7319         0x190,
   7320         0,
   7321         0,
   7322         2,
   7323         soc_BLH_F_0_LN_5_MODE_0r_fields,
   7324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7326         -1,
   7327         -1,
   7328     },
   7329 #endif /* chips */
   7330 
   7331 #if defined(BCM_83208_A0)
   7332     { /* SOC_REG_INT_BLH_F_0_LN_6_MODE_0r */
   7333         soc_block_list[76],
   7334         soc_genreg,
   7335         1,
   7336         0,
   7337         0x200,
   7338         0,
   7339         0,
   7340         2,
   7341         soc_BLH_F_0_LN_6_MODE_0r_fields,
   7342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7344         -1,
   7345         -1,
   7346     },
   7347 #endif /* chips */
   7348 
   7349 #if defined(BCM_83208_A0)
   7350     { /* SOC_REG_INT_BLH_F_0_LN_7_MODE_0r */
   7351         soc_block_list[76],
   7352         soc_genreg,
   7353         1,
   7354         0,
   7355         0x210,
   7356         0,
   7357         0,
   7358         2,
   7359         soc_BLH_F_0_LN_7_MODE_0r_fields,
   7360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7362         -1,
   7363         -1,
   7364     },
   7365 #endif /* chips */
   7366 
   7367 #if defined(BCM_83208_A0)
   7368     { /* SOC_REG_INT_BLH_GLOBAL_MEM_OPTIONSr */
   7369         soc_block_list[76],
   7370         soc_genreg,
   7371         1,
   7372         0,
   7373         0xc0,
   7374         0,
   7375         0,
   7376         6,
   7377         soc_AM_TOP_GLOBAL_MEM_OPTIONSr_fields,
   7378         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
   7379         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   7380         -1,
   7381         -1,
   7382     },
   7383 #endif /* chips */
   7384 
   7385 #if defined(BCM_83208_A0)
   7386     { /* SOC_REG_INT_BLH_GTIMER_CONFIGURATIONr */
   7387         soc_block_list[76],
   7388         soc_genreg,
   7389         1,
   7390         0,
   7391         0x88,
   7392         0,
   7393         0,
   7394         4,
   7395         soc_AM_TOP_GTIMER_CONFIGURATIONr_fields,
   7396         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   7398         -1,
   7399         -1,
   7400     },
   7401 #endif /* chips */
   7402 
   7403 #if defined(BCM_83208_A0)
   7404     { /* SOC_REG_INT_BLH_INDIRECT_COMMANDr */
   7405         soc_block_list[76],
   7406         soc_genreg,
   7407         1,
   7408         0,
   7409         0x80,
   7410         0,
   7411         0,
   7412         5,
   7413         soc_AM_TOP_INDIRECT_COMMANDr_fields,
   7414         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
   7415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7416         -1,
   7417         -1,
   7418     },
   7419 #endif /* chips */
   7420 
   7421 #if defined(BCM_83208_A0)
   7422     { /* SOC_REG_INT_BLH_INDIRECT_COMMAND_ADDRESSr */
   7423         soc_block_list[76],
   7424         soc_genreg,
   7425         1,
   7426         0,
   7427         0x81,
   7428         0,
   7429         0,
   7430         2,
   7431         soc_ECI_INDIRECT_COMMAND_ADDRESS_BCM83207_A0r_fields,
   7432         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7434         -1,
   7435         -1,
   7436     },
   7437 #endif /* chips */
   7438 
   7439 #if defined(BCM_83208_A0)
   7440     { /* SOC_REG_INT_BLH_INDIRECT_COMMAND_DATA_INCREMENTr */
   7441         soc_block_list[76],
   7442         soc_genreg,
   7443         1,
   7444         0,
   7445         0x82,
   7446         SOC_REG_FLAG_64_BITS,
   7447         0,
   7448         1,
   7449         soc_ECI_INDIRECT_COMMAND_DATA_INCREMENT_BCM83207_A0r_fields,
   7450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7451         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   7452         -1,
   7453         -1,
   7454     },
   7455 #endif /* chips */
   7456 
   7457 #if defined(BCM_83208_A0)
   7458     { /* SOC_REG_INT_BLH_INDIRECT_COMMAND_RD_DATAr */
   7459         soc_block_list[76],
   7460         soc_genreg,
   7461         1,
   7462         0,
   7463         0x60,
   7464         SOC_REG_FLAG_ABOVE_64_BITS |
   7465                           SOC_REG_FLAG_RO |
   7466                           SOC_REG_FLAG_SIGNAL,
   7467         0,
   7468         1,
   7469         soc_AM_TOP_INDIRECT_COMMAND_RD_DATAr_fields,
   7470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7471         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7472         -1,
   7473         -1,
   7474     },
   7475 #endif /* chips */
   7476 
   7477 #if defined(BCM_83208_A0)
   7478     { /* SOC_REG_INT_BLH_INDIRECT_COMMAND_WIDE_MEMr */
   7479         soc_block_list[76],
   7480         soc_genreg,
   7481         1,
   7482         0,
   7483         0x41,
   7484         0,
   7485         0,
   7486         1,
   7487         soc_AM_TOP_INDIRECT_COMMAND_WIDE_MEMr_fields,
   7488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7489         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7490         -1,
   7491         -1,
   7492     },
   7493 #endif /* chips */
   7494 
   7495 #if defined(BCM_83208_A0)
   7496     { /* SOC_REG_INT_BLH_INDIRECT_COMMAND_WR_DATAr */
   7497         soc_block_list[76],
   7498         soc_genreg,
   7499         1,
   7500         0,
   7501         0x20,
   7502         SOC_REG_FLAG_ABOVE_64_BITS,
   7503         0,
   7504         1,
   7505         soc_AM_TOP_INDIRECT_COMMAND_WR_DATAr_fields,
   7506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7507         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
   7508         -1,
   7509         -1,
   7510     },
   7511 #endif /* chips */
   7512 
   7513 #if defined(BCM_83208_A0)
   7514     { /* SOC_REG_INT_BLH_INDIRECT_FORCE_BUBBLEr */
   7515         soc_block_list[76],
   7516         soc_genreg,
   7517         1,
   7518         0,
   7519         0x83,
   7520         0,
   7521         0,
   7522         4,
   7523         soc_AM_TOP_INDIRECT_FORCE_BUBBLEr_fields,
   7524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7525         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
   7526         -1,
   7527         -1,
   7528     },
   7529 #endif /* chips */
   7530 
   7531 #if defined(BCM_83208_A0)
   7532     { /* SOC_REG_INT_BLH_INDIRECT_WR_MASKr */
   7533         soc_block_list[76],
   7534         soc_genreg,
   7535         1,
   7536         0,
   7537         0x40,
   7538         0,
   7539         0,
   7540         1,
   7541         soc_AM_TOP_INDIRECT_WR_MASKr_fields,
   7542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7544         -1,
   7545         -1,
   7546     },
   7547 #endif /* chips */
   7548 
   7549 #if defined(BCM_83208_A0)
   7550     { /* SOC_REG_INT_BLH_INTERRUPT_MASK_REGISTERr */
   7551         soc_block_list[76],
   7552         soc_genreg,
   7553         1,
   7554         0,
   7555         0x10,
   7556         0,
   7557         0,
   7558         1,
   7559         soc_AM_TOP_INTERRUPT_MASK_REGISTERr_fields,
   7560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7561         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7562         -1,
   7563         -1,
   7564     },
   7565 #endif /* chips */
   7566 
   7567 #if defined(BCM_83208_A0)
   7568     { /* SOC_REG_INT_BLH_INTERRUPT_REGISTERr */
   7569         soc_block_list[76],
   7570         soc_genreg,
   7571         1,
   7572         0,
   7573         0,
   7574         SOC_REG_FLAG_INTERRUPT,
   7575         0,
   7576         3,
   7577         soc_BLH_INTERRUPT_REGISTERr_fields,
   7578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7579         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   7580         -1,
   7581         -1,
   7582     },
   7583 #endif /* chips */
   7584 
   7585 #if defined(BCM_83208_A0)
   7586     { /* SOC_REG_INT_BLH_INTERRUPT_REGISTER_TESTr */
   7587         soc_block_list[76],
   7588         soc_genreg,
   7589         1,
   7590         0,
   7591         0x18,
   7592         0,
   7593         0,
   7594         1,
   7595         soc_ECI_INTERRUPT_REGISTER_TEST_BCM83207_A0r_fields,
   7596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7597         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7598         -1,
   7599         -1,
   7600     },
   7601 #endif /* chips */
   7602 
   7603 #if defined(BCM_83208_A0)
   7604     { /* SOC_REG_INT_BLH_LANES_RX_RESET_0r */
   7605         soc_block_list[76],
   7606         soc_genreg,
   7607         1,
   7608         0,
   7609         0x220,
   7610         0,
   7611         0,
   7612         3,
   7613         soc_BLH_LANES_RX_RESET_0r_fields,
   7614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7615         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7616         -1,
   7617         -1,
   7618     },
   7619 #endif /* chips */
   7620 
   7621 #if defined(BCM_83208_A0)
   7622     { /* SOC_REG_INT_BLH_LANES_TX_RESET_0r */
   7623         soc_block_list[76],
   7624         soc_genreg,
   7625         1,
   7626         0,
   7627         0x230,
   7628         0,
   7629         0,
   7630         3,
   7631         soc_BLH_LANES_TX_RESET_0r_fields,
   7632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7633         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   7634         -1,
   7635         -1,
   7636     },
   7637 #endif /* chips */
   7638 
   7639 #if defined(BCM_83208_A0)
   7640     { /* SOC_REG_INT_BLH_MASK_SIGNAL_DETRECT_0r */
   7641         soc_block_list[76],
   7642         soc_genreg,
   7643         1,
   7644         0,
   7645         0x260,
   7646         0,
   7647         0,
   7648         1,
   7649         soc_BLH_MASK_SIGNAL_DETRECT_0r_fields,
   7650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7651         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
   7652         -1,
   7653         -1,
   7654     },
   7655 #endif /* chips */
   7656 
   7657 #if defined(BCM_83208_A0)
   7658     { /* SOC_REG_INT_BLH_PARITY_ERR_CNTr */
   7659         soc_block_list[76],
   7660         soc_genreg,
   7661         1,
   7662         0,
   7663         0x98,
   7664         SOC_REG_FLAG_64_BITS |
   7665                           SOC_REG_FLAG_RO,
   7666         0,
   7667         4,
   7668         soc_BLH_PARITY_ERR_CNTr_fields,
   7669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7670         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
   7671         -1,
   7672         -1,
   7673     },
   7674 #endif /* chips */
   7675 
   7676 #if defined(BCM_83208_A0)
   7677     { /* SOC_REG_INT_BLH_PAR_ERR_INITIATEr */
   7678         soc_block_list[76],
   7679         soc_genreg,
   7680         1,
   7681         0,
   7682         0xaa,
   7683         0,
   7684         0,
   7685         1,
   7686         soc_BLH_PAR_ERR_INITIATEr_fields,
   7687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7688         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7689         -1,
   7690         -1,
   7691     },
   7692 #endif /* chips */
   7693 
   7694 #if defined(BCM_83208_A0)
   7695     { /* SOC_REG_INT_BLH_PAR_ERR_MEM_MASKr */
   7696         soc_block_list[76],
   7697         soc_genreg,
   7698         1,
   7699         0,
   7700         0xa0,
   7701         0,
   7702         0,
   7703         1,
   7704         soc_BLH_PAR_ERR_MEM_MASKr_fields,
   7705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7706         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   7707         -1,
   7708         -1,
   7709     },
   7710 #endif /* chips */
   7711 
   7712 #if defined(BCM_83208_A0)
   7713     { /* SOC_REG_INT_BLH_PCMI_0r */
   7714         soc_block_list[76],
   7715         soc_genreg,
   7716         1,
   7717         0,
   7718         0xb0,
   7719         0,
   7720         0,
   7721         1,
   7722         soc_BLH_PCMI_0r_fields,
   7723         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7724         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7725         -1,
   7726         -1,
   7727     },
   7728 #endif /* chips */
   7729 
   7730 #if defined(BCM_83208_A0)
   7731     { /* SOC_REG_INT_BLH_PCMI_1r */
   7732         soc_block_list[76],
   7733         soc_genreg,
   7734         1,
   7735         0,
   7736         0xb3,
   7737         0,
   7738         0,
   7739         1,
   7740         soc_BLH_PCMI_0r_fields,
   7741         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7743         -1,
   7744         -1,
   7745     },
   7746 #endif /* chips */
   7747 
   7748 #if defined(BCM_83208_A0)
   7749     { /* SOC_REG_INT_BLH_PCMI_2r */
   7750         soc_block_list[76],
   7751         soc_genreg,
   7752         1,
   7753         0,
   7754         0xb6,
   7755         0,
   7756         0,
   7757         1,
   7758         soc_BLH_PCMI_0r_fields,
   7759         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7760         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7761         -1,
   7762         -1,
   7763     },
   7764 #endif /* chips */
   7765 
   7766 #if defined(BCM_83208_A0)
   7767     { /* SOC_REG_INT_BLH_PCMI_3r */
   7768         soc_block_list[76],
   7769         soc_genreg,
   7770         1,
   7771         0,
   7772         0xb9,
   7773         0,
   7774         0,
   7775         1,
   7776         soc_BLH_PCMI_0r_fields,
   7777         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7778         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7779         -1,
   7780         -1,
   7781     },
   7782 #endif /* chips */
   7783 
   7784 #if defined(BCM_83208_A0)
   7785     { /* SOC_REG_INT_BLH_PCMI_4r */
   7786         soc_block_list[76],
   7787         soc_genreg,
   7788         1,
   7789         0,
   7790         0xbc,
   7791         0,
   7792         0,
   7793         1,
   7794         soc_BLH_PCMI_0r_fields,
   7795         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
   7796         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7797         -1,
   7798         -1,
   7799     },
   7800 #endif /* chips */
   7801 
   7802 #if defined(BCM_83208_A0)
   7803     { /* SOC_REG_INT_BLH_PCMI_0_Sr */
   7804         soc_block_list[76],
   7805         soc_genreg,
   7806         1,
   7807         0,
   7808         0xb1,
   7809         SOC_REG_FLAG_RO,
   7810         0,
   7811         3,
   7812         soc_DRCA_REG_00B1_BCM83207_A0r_fields,
   7813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7814         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7815         -1,
   7816         -1,
   7817     },
   7818 #endif /* chips */
   7819 
   7820 #if defined(BCM_83208_A0)
   7821     { /* SOC_REG_INT_BLH_PCMI_0_Tr */
   7822         soc_block_list[76],
   7823         soc_genreg,
   7824         1,
   7825         0,
   7826         0xb2,
   7827         0,
   7828         0,
   7829         2,
   7830         soc_BLH_PCMI_0_Tr_fields,
   7831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7832         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7833         -1,
   7834         -1,
   7835     },
   7836 #endif /* chips */
   7837 
   7838 #if defined(BCM_83208_A0)
   7839     { /* SOC_REG_INT_BLH_PCMI_1_Sr */
   7840         soc_block_list[76],
   7841         soc_genreg,
   7842         1,
   7843         0,
   7844         0xb4,
   7845         SOC_REG_FLAG_RO,
   7846         0,
   7847         3,
   7848         soc_DRCA_REG_00B1_BCM83207_A0r_fields,
   7849         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7850         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7851         -1,
   7852         -1,
   7853     },
   7854 #endif /* chips */
   7855 
   7856 #if defined(BCM_83208_A0)
   7857     { /* SOC_REG_INT_BLH_PCMI_1_Tr */
   7858         soc_block_list[76],
   7859         soc_genreg,
   7860         1,
   7861         0,
   7862         0xb5,
   7863         0,
   7864         0,
   7865         2,
   7866         soc_BLH_PCMI_0_Tr_fields,
   7867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7868         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7869         -1,
   7870         -1,
   7871     },
   7872 #endif /* chips */
   7873 
   7874 #if defined(BCM_83208_A0)
   7875     { /* SOC_REG_INT_BLH_PCMI_2_Sr */
   7876         soc_block_list[76],
   7877         soc_genreg,
   7878         1,
   7879         0,
   7880         0xb7,
   7881         SOC_REG_FLAG_RO,
   7882         0,
   7883         3,
   7884         soc_DRCA_REG_00B1_BCM83207_A0r_fields,
   7885         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7886         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7887         -1,
   7888         -1,
   7889     },
   7890 #endif /* chips */
   7891 
   7892 #if defined(BCM_83208_A0)
   7893     { /* SOC_REG_INT_BLH_PCMI_2_Tr */
   7894         soc_block_list[76],
   7895         soc_genreg,
   7896         1,
   7897         0,
   7898         0xb8,
   7899         0,
   7900         0,
   7901         2,
   7902         soc_BLH_PCMI_0_Tr_fields,
   7903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7904         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7905         -1,
   7906         -1,
   7907     },
   7908 #endif /* chips */
   7909 
   7910 #if defined(BCM_83208_A0)
   7911     { /* SOC_REG_INT_BLH_PCMI_3_Sr */
   7912         soc_block_list[76],
   7913         soc_genreg,
   7914         1,
   7915         0,
   7916         0xba,
   7917         SOC_REG_FLAG_RO,
   7918         0,
   7919         3,
   7920         soc_DRCA_REG_00B1_BCM83207_A0r_fields,
   7921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7922         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7923         -1,
   7924         -1,
   7925     },
   7926 #endif /* chips */
   7927 
   7928 #if defined(BCM_83208_A0)
   7929     { /* SOC_REG_INT_BLH_PCMI_3_Tr */
   7930         soc_block_list[76],
   7931         soc_genreg,
   7932         1,
   7933         0,
   7934         0xbb,
   7935         0,
   7936         0,
   7937         2,
   7938         soc_BLH_PCMI_0_Tr_fields,
   7939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7940         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7941         -1,
   7942         -1,
   7943     },
   7944 #endif /* chips */
   7945 
   7946 #if defined(BCM_83208_A0)
   7947     { /* SOC_REG_INT_BLH_PCMI_4_Sr */
   7948         soc_block_list[76],
   7949         soc_genreg,
   7950         1,
   7951         0,
   7952         0xbd,
   7953         SOC_REG_FLAG_RO,
   7954         0,
   7955         3,
   7956         soc_DRCA_REG_00B1_BCM83207_A0r_fields,
   7957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7959         -1,
   7960         -1,
   7961     },
   7962 #endif /* chips */
   7963 
   7964 #if defined(BCM_83208_A0)
   7965     { /* SOC_REG_INT_BLH_PCMI_4_Tr */
   7966         soc_block_list[76],
   7967         soc_genreg,
   7968         1,
   7969         0,
   7970         0xbe,
   7971         0,
   7972         0,
   7973         2,
   7974         soc_BLH_PCMI_0_Tr_fields,
   7975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7976         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
   7977         -1,
   7978         -1,
   7979     },
   7980 #endif /* chips */
   7981 
   7982 #if defined(BCM_83208_A0)
   7983     { /* SOC_REG_INT_BLH_PLL_CORE_MODE_0r */
   7984         soc_block_list[76],
   7985         soc_genreg,
   7986         1,
   7987         0,
   7988         0x280,
   7989         0,
   7990         0,
   7991         2,
   7992         soc_BLH_PLL_CORE_MODE_0r_fields,
   7993         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   7994         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   7995         -1,
   7996         -1,
   7997     },
   7998 #endif /* chips */
   7999 
   8000 #if defined(BCM_83208_A0)
   8001     { /* SOC_REG_INT_BLH_PLL_REF_CFG_0r */
   8002         soc_block_list[76],
   8003         soc_genreg,
   8004         1,
   8005         0,
   8006         0x270,
   8007         0,
   8008         0,
   8009         15,
   8010         soc_BLH_PLL_REF_CFG_0r_fields,
   8011         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8012         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
   8013         -1,
   8014         -1,
   8015     },
   8016 #endif /* chips */
   8017 
   8018 #if defined(BCM_83208_A0)
   8019     { /* SOC_REG_INT_BLH_REG_0901r */
   8020         soc_block_list[76],
   8021         soc_genreg,
   8022         1,
   8023         0,
   8024         0x901,
   8025         0,
   8026         0,
   8027         1,
   8028         soc_BLH_REG_0901r_fields,
   8029         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
   8030         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8031         -1,
   8032         -1,
   8033     },
   8034 #endif /* chips */
   8035 
   8036 #if defined(BCM_83208_A0)
   8037     { /* SOC_REG_INT_BLH_RESCAL_CFG_0r */
   8038         soc_block_list[76],
   8039         soc_genreg,
   8040         1,
   8041         0,
   8042         0x300,
   8043         0,
   8044         0,
   8045         2,
   8046         soc_BLH_RESCAL_CFG_0r_fields,
   8047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8048         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   8049         -1,
   8050         -1,
   8051     },
   8052 #endif /* chips */
   8053 
   8054 #if defined(BCM_83208_A0)
   8055     { /* SOC_REG_INT_BLH_RESERVED_MIRROR_ADDRr */
   8056         soc_block_list[76],
   8057         soc_genreg,
   8058         1,
   8059         0,
   8060         0x85,
   8061         0,
   8062         0,
   8063         2,
   8064         soc_DRCA_REG_0085_BCM83207_A0r_fields,
   8065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8066         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
   8067         -1,
   8068         -1,
   8069     },
   8070 #endif /* chips */
   8071 
   8072 #if defined(BCM_83208_A0)
   8073     { /* SOC_REG_INT_BLH_RESERVED_MTCDr */
   8074         soc_block_list[76],
   8075         soc_genreg,
   8076         1,
   8077         0,
   8078         0xae,
   8079         0,
   8080         0,
   8081         6,
   8082         soc_AM_TOP_RESERVED_MTCDr_fields,
   8083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8084         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
   8085         -1,
   8086         -1,
   8087     },
   8088 #endif /* chips */
   8089 
   8090 #if defined(BCM_83208_A0)
   8091     { /* SOC_REG_INT_BLH_RESERVED_MTCPr */
   8092         soc_block_list[76],
   8093         soc_genreg,
   8094         1,
   8095         0,
   8096         0xad,
   8097         SOC_REG_FLAG_64_BITS,
   8098         0,
   8099         17,
   8100         soc_AM_TOP_RESERVED_MTCPr_fields,
   8101         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
   8102         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
   8103         -1,
   8104         -1,
   8105     },
   8106 #endif /* chips */
   8107 
   8108 #if defined(BCM_83208_A0)
   8109     { /* SOC_REG_INT_BLH_RESERVED_SPARE_0r */
   8110         soc_block_list[76],
   8111         soc_genreg,
   8112         1,
   8113         0,
   8114         0x90,
   8115         0,
   8116         0,
   8117         1,
   8118         soc_AM_TOP_RESERVED_SPARE_0r_fields,
   8119         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8120         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8121         -1,
   8122         -1,
   8123     },
   8124 #endif /* chips */
   8125 
   8126 #if defined(BCM_83208_A0)
   8127     { /* SOC_REG_INT_BLH_RESERVED_SPARE_1r */
   8128         soc_block_list[76],
   8129         soc_genreg,
   8130         1,
   8131         0,
   8132         0x91,
   8133         0,
   8134         0,
   8135         1,
   8136         soc_AM_TOP_RESERVED_SPARE_1r_fields,
   8137         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
   8138         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8139         -1,
   8140         -1,
   8141     },
   8142 #endif /* chips */
   8143 
   8144 #if defined(BCM_83208_A0)
   8145     { /* SOC_REG_INT_BLH_RESERVED_SPARE_2r */
   8146         soc_block_list[76],
   8147         soc_genreg,
   8148         1,
   8149         0,
   8150         0x92,
   8151         0,
   8152         0,
   8153         1,
   8154         soc_AM_TOP_RESERVED_SPARE_2r_fields,
   8155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8157         -1,
   8158         -1,
   8159     },
   8160 #endif /* chips */
   8161 
   8162 #if defined(BCM_83208_A0)
   8163     { /* SOC_REG_INT_BLH_RESERVED_SPARE_3r */
   8164         soc_block_list[76],
   8165         soc_genreg,
   8166         1,
   8167         0,
   8168         0x93,
   8169         0,
   8170         0,
   8171         1,
   8172         soc_AM_TOP_RESERVED_SPARE_3r_fields,
   8173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8174         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8175         -1,
   8176         -1,
   8177     },
   8178 #endif /* chips */
   8179 
   8180 #if defined(BCM_83208_A0)
   8181     { /* SOC_REG_INT_BLH_RX_OVER_SAMPLING_MODE_0r */
   8182         soc_block_list[76],
   8183         soc_genreg,
   8184         1,
   8185         0,
   8186         0x110,
   8187         0,
   8188         0,
   8189         8,
   8190         soc_BLH_RX_OVER_SAMPLING_MODE_0r_fields,
   8191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8192         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8193         -1,
   8194         -1,
   8195     },
   8196 #endif /* chips */
   8197 
   8198 #if defined(BCM_83208_A0)
   8199     { /* SOC_REG_INT_BLH_RX_PAM_4_MODE_0r */
   8200         soc_block_list[76],
   8201         soc_genreg,
   8202         1,
   8203         0,
   8204         0x130,
   8205         0,
   8206         0,
   8207         8,
   8208         soc_BLH_RX_PAM_4_MODE_0r_fields,
   8209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8210         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   8211         -1,
   8212         -1,
   8213     },
   8214 #endif /* chips */
   8215 
   8216 #if defined(BCM_83208_A0)
   8217     { /* SOC_REG_INT_BLH_SBUS_BROADCAST_IDr */
   8218         soc_block_list[76],
   8219         soc_genreg,
   8220         1,
   8221         0,
   8222         0x86,
   8223         0,
   8224         0,
   8225         1,
   8226         soc_AM_TOP_SBUS_BROADCAST_IDr_fields,
   8227         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
   8228         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
   8229         -1,
   8230         -1,
   8231     },
   8232 #endif /* chips */
   8233 
   8234 #if defined(BCM_83208_A0)
   8235     { /* SOC_REG_INT_BLH_SBUS_LAST_IN_CHAINr */
   8236         soc_block_list[76],
   8237         soc_genreg,
   8238         1,
   8239         0,
   8240         0x87,
   8241         0,
   8242         0,
   8243         1,
   8244         soc_ECI_SBUS_LAST_IN_CHAIN_BCM83207_A0r_fields,
   8245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8246         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8247         -1,
   8248         -1,
   8249     },
   8250 #endif /* chips */
   8251 
   8252 #if defined(BCM_83208_A0)
   8253     { /* SOC_REG_INT_BLH_SRD_STATUS_0r */
   8254         soc_block_list[76],
   8255         soc_genreg,
   8256         1,
   8257         0,
   8258         0x310,
   8259         SOC_REG_FLAG_RO,
   8260         0,
   8261         5,
   8262         soc_BLH_SRD_STATUS_0r_fields,
   8263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8264         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   8265         -1,
   8266         -1,
   8267     },
   8268 #endif /* chips */
   8269 
   8270 #if defined(BCM_83208_A0)
   8271     { /* SOC_REG_INT_BLH_SRD_STATUS_CHANGED_0r */
   8272         soc_block_list[76],
   8273         soc_genreg,
   8274         1,
   8275         0,
   8276         0x320,
   8277         0,
   8278         0,
   8279         5,
   8280         soc_BLH_SRD_STATUS_CHANGED_0r_fields,
   8281         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8282         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   8283         -1,
   8284         -1,
   8285     },
   8286 #endif /* chips */
   8287 
   8288 #if defined(BCM_83208_A0)
   8289     { /* SOC_REG_INT_BLH_SRD_STATUS_CHANGED_0_MASKr */
   8290         soc_block_list[76],
   8291         soc_genreg,
   8292         1,
   8293         0,
   8294         0x330,
   8295         0,
   8296         0,
   8297         5,
   8298         soc_BLH_SRD_STATUS_CHANGED_0_MASKr_fields,
   8299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8300         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   8301         -1,
   8302         -1,
   8303     },
   8304 #endif /* chips */
   8305 
   8306 #if defined(BCM_83208_A0)
   8307     { /* SOC_REG_INT_BLH_SRD_STATUS_CHANGED_0_TESTr */
   8308         soc_block_list[76],
   8309         soc_genreg,
   8310         1,
   8311         0,
   8312         0x332,
   8313         0,
   8314         0,
   8315         1,
   8316         soc_BLH_SRD_STATUS_CHANGED_0_TESTr_fields,
   8317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8318         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8319         -1,
   8320         -1,
   8321     },
   8322 #endif /* chips */
   8323 
   8324 #if defined(BCM_83208_A0)
   8325     { /* SOC_REG_INT_BLH_TX_DRV_HV_DIS_0r */
   8326         soc_block_list[76],
   8327         soc_genreg,
   8328         1,
   8329         0,
   8330         0x290,
   8331         0,
   8332         0,
   8333         1,
   8334         soc_BLH_TX_DRV_HV_DIS_0r_fields,
   8335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8336         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   8337         -1,
   8338         -1,
   8339     },
   8340 #endif /* chips */
   8341 
   8342 #if defined(BCM_83208_A0)
   8343     { /* SOC_REG_INT_BLH_TX_OVER_SAMPLING_MODE_0r */
   8344         soc_block_list[76],
   8345         soc_genreg,
   8346         1,
   8347         0,
   8348         0x100,
   8349         0,
   8350         0,
   8351         8,
   8352         soc_BLH_TX_OVER_SAMPLING_MODE_0r_fields,
   8353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8354         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8355         -1,
   8356         -1,
   8357     },
   8358 #endif /* chips */
   8359 
   8360 #if defined(BCM_83208_A0)
   8361     { /* SOC_REG_INT_BLH_TX_PAM_4_MODE_0r */
   8362         soc_block_list[76],
   8363         soc_genreg,
   8364         1,
   8365         0,
   8366         0x120,
   8367         0,
   8368         0,
   8369         8,
   8370         soc_BLH_TX_PAM_4_MODE_0r_fields,
   8371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8372         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   8373         -1,
   8374         -1,
   8375     },
   8376 #endif /* chips */
   8377 
   8378 #if defined(BCM_83208_A0)
   8379     { /* SOC_REG_INT_BLH_WC_UC_MEM_ACCESSr */
   8380         soc_block_list[76],
   8381         soc_genreg,
   8382         1,
   8383         0,
   8384         0x900,
   8385         0,
   8386         0,
   8387         2,
   8388         soc_BLH_WC_UC_MEM_ACCESSr_fields,
   8389         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
   8390         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   8391         -1,
   8392         -1,
   8393     },
   8394 #endif /* chips */
   8395 
   8396 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8397     { /* SOC_REG_INT_BMAC_PFC_COS0_XOFF_CNTr */
   8398         soc_block_list[9],
   8399         soc_portreg,
   8400         1,
   8401         0,
   8402         0x59,
   8403         SOC_REG_FLAG_64_BITS |
   8404                           SOC_REG_FLAG_COUNTER,
   8405         0,
   8406         1,
   8407         soc_XTHOLr_fields,
   8408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8409         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8410         141,
   8411         -1,
   8412     },
   8413 #endif /* chips */
   8414 
   8415 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8416     { /* SOC_REG_INT_BMAC_PFC_COS10_XOFF_CNTr */
   8417         soc_block_list[9],
   8418         soc_portreg,
   8419         1,
   8420         0,
   8421         0x63,
   8422         SOC_REG_FLAG_64_BITS |
   8423                           SOC_REG_FLAG_COUNTER,
   8424         0,
   8425         1,
   8426         soc_XTHOLr_fields,
   8427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8428         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8429         151,
   8430         -1,
   8431     },
   8432 #endif /* chips */
   8433 
   8434 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8435     { /* SOC_REG_INT_BMAC_PFC_COS11_XOFF_CNTr */
   8436         soc_block_list[9],
   8437         soc_portreg,
   8438         1,
   8439         0,
   8440         0x64,
   8441         SOC_REG_FLAG_64_BITS |
   8442                           SOC_REG_FLAG_COUNTER,
   8443         0,
   8444         1,
   8445         soc_XTHOLr_fields,
   8446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8448         152,
   8449         -1,
   8450     },
   8451 #endif /* chips */
   8452 
   8453 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8454     { /* SOC_REG_INT_BMAC_PFC_COS12_XOFF_CNTr */
   8455         soc_block_list[9],
   8456         soc_portreg,
   8457         1,
   8458         0,
   8459         0x65,
   8460         SOC_REG_FLAG_64_BITS |
   8461                           SOC_REG_FLAG_COUNTER,
   8462         0,
   8463         1,
   8464         soc_XTHOLr_fields,
   8465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8466         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8467         153,
   8468         -1,
   8469     },
   8470 #endif /* chips */
   8471 
   8472 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8473     { /* SOC_REG_INT_BMAC_PFC_COS13_XOFF_CNTr */
   8474         soc_block_list[9],
   8475         soc_portreg,
   8476         1,
   8477         0,
   8478         0x66,
   8479         SOC_REG_FLAG_64_BITS |
   8480                           SOC_REG_FLAG_COUNTER,
   8481         0,
   8482         1,
   8483         soc_XTHOLr_fields,
   8484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8485         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8486         154,
   8487         -1,
   8488     },
   8489 #endif /* chips */
   8490 
   8491 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8492     { /* SOC_REG_INT_BMAC_PFC_COS14_XOFF_CNTr */
   8493         soc_block_list[9],
   8494         soc_portreg,
   8495         1,
   8496         0,
   8497         0x67,
   8498         SOC_REG_FLAG_64_BITS |
   8499                           SOC_REG_FLAG_COUNTER,
   8500         0,
   8501         1,
   8502         soc_XTHOLr_fields,
   8503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8504         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8505         155,
   8506         -1,
   8507     },
   8508 #endif /* chips */
   8509 
   8510 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8511     { /* SOC_REG_INT_BMAC_PFC_COS15_XOFF_CNTr */
   8512         soc_block_list[9],
   8513         soc_portreg,
   8514         1,
   8515         0,
   8516         0x68,
   8517         SOC_REG_FLAG_64_BITS |
   8518                           SOC_REG_FLAG_COUNTER,
   8519         0,
   8520         1,
   8521         soc_XTHOLr_fields,
   8522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8523         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8524         156,
   8525         -1,
   8526     },
   8527 #endif /* chips */
   8528 
   8529 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8530     { /* SOC_REG_INT_BMAC_PFC_COS1_XOFF_CNTr */
   8531         soc_block_list[9],
   8532         soc_portreg,
   8533         1,
   8534         0,
   8535         0x5a,
   8536         SOC_REG_FLAG_64_BITS |
   8537                           SOC_REG_FLAG_COUNTER,
   8538         0,
   8539         1,
   8540         soc_XTHOLr_fields,
   8541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8542         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8543         142,
   8544         -1,
   8545     },
   8546 #endif /* chips */
   8547 
   8548 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8549     { /* SOC_REG_INT_BMAC_PFC_COS2_XOFF_CNTr */
   8550         soc_block_list[9],
   8551         soc_portreg,
   8552         1,
   8553         0,
   8554         0x5b,
   8555         SOC_REG_FLAG_64_BITS |
   8556                           SOC_REG_FLAG_COUNTER,
   8557         0,
   8558         1,
   8559         soc_XTHOLr_fields,
   8560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8561         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8562         143,
   8563         -1,
   8564     },
   8565 #endif /* chips */
   8566 
   8567 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8568     { /* SOC_REG_INT_BMAC_PFC_COS3_XOFF_CNTr */
   8569         soc_block_list[9],
   8570         soc_portreg,
   8571         1,
   8572         0,
   8573         0x5c,
   8574         SOC_REG_FLAG_64_BITS |
   8575                           SOC_REG_FLAG_COUNTER,
   8576         0,
   8577         1,
   8578         soc_XTHOLr_fields,
   8579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8580         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8581         144,
   8582         -1,
   8583     },
   8584 #endif /* chips */
   8585 
   8586 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8587     { /* SOC_REG_INT_BMAC_PFC_COS4_XOFF_CNTr */
   8588         soc_block_list[9],
   8589         soc_portreg,
   8590         1,
   8591         0,
   8592         0x5d,
   8593         SOC_REG_FLAG_64_BITS |
   8594                           SOC_REG_FLAG_COUNTER,
   8595         0,
   8596         1,
   8597         soc_XTHOLr_fields,
   8598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8600         145,
   8601         -1,
   8602     },
   8603 #endif /* chips */
   8604 
   8605 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8606     { /* SOC_REG_INT_BMAC_PFC_COS5_XOFF_CNTr */
   8607         soc_block_list[9],
   8608         soc_portreg,
   8609         1,
   8610         0,
   8611         0x5e,
   8612         SOC_REG_FLAG_64_BITS |
   8613                           SOC_REG_FLAG_COUNTER,
   8614         0,
   8615         1,
   8616         soc_XTHOLr_fields,
   8617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8618         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8619         146,
   8620         -1,
   8621     },
   8622 #endif /* chips */
   8623 
   8624 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8625     { /* SOC_REG_INT_BMAC_PFC_COS6_XOFF_CNTr */
   8626         soc_block_list[9],
   8627         soc_portreg,
   8628         1,
   8629         0,
   8630         0x5f,
   8631         SOC_REG_FLAG_64_BITS |
   8632                           SOC_REG_FLAG_COUNTER,
   8633         0,
   8634         1,
   8635         soc_XTHOLr_fields,
   8636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8637         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8638         147,
   8639         -1,
   8640     },
   8641 #endif /* chips */
   8642 
   8643 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8644     { /* SOC_REG_INT_BMAC_PFC_COS7_XOFF_CNTr */
   8645         soc_block_list[9],
   8646         soc_portreg,
   8647         1,
   8648         0,
   8649         0x60,
   8650         SOC_REG_FLAG_64_BITS |
   8651                           SOC_REG_FLAG_COUNTER,
   8652         0,
   8653         1,
   8654         soc_XTHOLr_fields,
   8655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8657         148,
   8658         -1,
   8659     },
   8660 #endif /* chips */
   8661 
   8662 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8663     { /* SOC_REG_INT_BMAC_PFC_COS8_XOFF_CNTr */
   8664         soc_block_list[9],
   8665         soc_portreg,
   8666         1,
   8667         0,
   8668         0x61,
   8669         SOC_REG_FLAG_64_BITS |
   8670                           SOC_REG_FLAG_COUNTER,
   8671         0,
   8672         1,
   8673         soc_XTHOLr_fields,
   8674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8675         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8676         149,
   8677         -1,
   8678     },
   8679 #endif /* chips */
   8680 
   8681 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8682     { /* SOC_REG_INT_BMAC_PFC_COS9_XOFF_CNTr */
   8683         soc_block_list[9],
   8684         soc_portreg,
   8685         1,
   8686         0,
   8687         0x62,
   8688         SOC_REG_FLAG_64_BITS |
   8689                           SOC_REG_FLAG_COUNTER,
   8690         0,
   8691         1,
   8692         soc_XTHOLr_fields,
   8693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8694         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8695         150,
   8696         -1,
   8697     },
   8698 #endif /* chips */
   8699 
   8700 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8701     { /* SOC_REG_INT_BMAC_PFC_CTRLr */
   8702         soc_block_list[9],
   8703         soc_portreg,
   8704         1,
   8705         0,
   8706         0x54,
   8707         SOC_REG_FLAG_64_BITS,
   8708         0,
   8709         4,
   8710         soc_BMAC_PFC_CTRLr_fields,
   8711         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
   8712         SOC_RESET_MASK_DEC(0x0000000e, 0x00000000)
   8713         -1,
   8714         -1,
   8715     },
   8716 #endif /* chips */
   8717 
   8718 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8719     { /* SOC_REG_INT_BMAC_PFC_DA_HIr */
   8720         soc_block_list[9],
   8721         soc_portreg,
   8722         1,
   8723         0,
   8724         0x58,
   8725         SOC_REG_FLAG_64_BITS,
   8726         0,
   8727         1,
   8728         soc_BMAC_PFC_DA_HIr_fields,
   8729         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
   8730         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8731         -1,
   8732         -1,
   8733     },
   8734 #endif /* chips */
   8735 
   8736 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8737     { /* SOC_REG_INT_BMAC_PFC_DA_LOr */
   8738         soc_block_list[9],
   8739         soc_portreg,
   8740         1,
   8741         0,
   8742         0x57,
   8743         SOC_REG_FLAG_64_BITS,
   8744         0,
   8745         1,
   8746         soc_BMAC_PFC_DA_LOr_fields,
   8747         SOC_RESET_VAL_DEC(0xc2000001, 0x00000000)
   8748         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8749         -1,
   8750         -1,
   8751     },
   8752 #endif /* chips */
   8753 
   8754 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8755     { /* SOC_REG_INT_BMAC_PFC_OPCODEr */
   8756         soc_block_list[9],
   8757         soc_portreg,
   8758         1,
   8759         0,
   8760         0x56,
   8761         SOC_REG_FLAG_64_BITS,
   8762         0,
   8763         1,
   8764         soc_BMAC_PFC_OPCODEr_fields,
   8765         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
   8766         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8767         -1,
   8768         -1,
   8769     },
   8770 #endif /* chips */
   8771 
   8772 #if defined(BCM_56725_A0) || defined(BCM_56820_A0)
   8773     { /* SOC_REG_INT_BMAC_PFC_TYPEr */
   8774         soc_block_list[9],
   8775         soc_portreg,
   8776         1,
   8777         0,
   8778         0x55,
   8779         SOC_REG_FLAG_64_BITS,
   8780         0,
   8781         1,
   8782         soc_BMAC_PFC_TYPEr_fields,
   8783         SOC_RESET_VAL_DEC(0x00008808, 0x00000000)
   8784         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   8785         -1,
   8786         -1,
   8787     },
   8788 #endif /* chips */
   8789 
   8790 #if defined(BCM_56370_A0)
   8791     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_ERROR_LOG_ADDR_LSBr */
   8792         soc_block_list[61],
   8793         soc_iprocreg,
   8794         1,
   8795         0,
   8796         0x1025890c,
   8797         SOC_REG_FLAG_RO,
   8798         0,
   8799         1,
   8800         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB_BCM53400_A0r_fields,
   8801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8802         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8803         -1,
   8804         -1,
   8805         3,
   8806     },
   8807 #endif /* chips */
   8808 
   8809 #if defined(BCM_56370_A0)
   8810     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_ERROR_LOG_COMPLETEr */
   8811         soc_block_list[61],
   8812         soc_iprocreg,
   8813         1,
   8814         0,
   8815         0x10258904,
   8816         SOC_REG_FLAG_RO,
   8817         0,
   8818         3,
   8819         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE_BCM53400_A0r_fields,
   8820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8822         -1,
   8823         -1,
   8824         3,
   8825     },
   8826 #endif /* chips */
   8827 
   8828 #if defined(BCM_56370_A0)
   8829     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_ERROR_LOG_CONTROLr */
   8830         soc_block_list[61],
   8831         soc_iprocreg,
   8832         1,
   8833         0,
   8834         0x10258900,
   8835         0,
   8836         0,
   8837         7,
   8838         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL_BCM53400_A0r_fields,
   8839         SOC_RESET_VAL_DEC(0x00000040, 0x00000000)
   8840         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8841         -1,
   8842         -1,
   8843         3,
   8844     },
   8845 #endif /* chips */
   8846 
   8847 #if defined(BCM_56370_A0)
   8848     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_ERROR_LOG_FLAGSr */
   8849         soc_block_list[61],
   8850         soc_iprocreg,
   8851         1,
   8852         0,
   8853         0x1025891c,
   8854         SOC_REG_FLAG_RO,
   8855         0,
   8856         11,
   8857         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS_BCM53400_A0r_fields,
   8858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8860         -1,
   8861         -1,
   8862         3,
   8863     },
   8864 #endif /* chips */
   8865 
   8866 #if defined(BCM_56370_A0)
   8867     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_ERROR_LOG_IDr */
   8868         soc_block_list[61],
   8869         soc_iprocreg,
   8870         1,
   8871         0,
   8872         0x10258914,
   8873         SOC_REG_FLAG_RO,
   8874         0,
   8875         2,
   8876         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
   8877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8878         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8879         -1,
   8880         -1,
   8881         3,
   8882     },
   8883 #endif /* chips */
   8884 
   8885 #if defined(BCM_56370_A0)
   8886     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_ERROR_LOG_STATUSr */
   8887         soc_block_list[61],
   8888         soc_iprocreg,
   8889         1,
   8890         0,
   8891         0x10258908,
   8892         SOC_REG_FLAG_RO,
   8893         0,
   8894         3,
   8895         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS_BCM53400_A0r_fields,
   8896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8898         -1,
   8899         -1,
   8900         3,
   8901     },
   8902 #endif /* chips */
   8903 
   8904 #if defined(BCM_56370_A0)
   8905     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_INTERRUPT_STATUSr */
   8906         soc_block_list[61],
   8907         soc_iprocreg,
   8908         1,
   8909         0,
   8910         0x10258a00,
   8911         SOC_REG_FLAG_RO,
   8912         0,
   8913         3,
   8914         soc_A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS_BCM53400_A0r_fields,
   8915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8917         -1,
   8918         -1,
   8919         3,
   8920     },
   8921 #endif /* chips */
   8922 
   8923 #if defined(BCM_56370_A0)
   8924     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_RESET_CONTROLr */
   8925         soc_block_list[61],
   8926         soc_iprocreg,
   8927         1,
   8928         0,
   8929         0x10258800,
   8930         0,
   8931         0,
   8932         2,
   8933         soc_A9JTAG_M0_IDM_RESET_CONTROL_BCM53400_A0r_fields,
   8934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8935         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8936         -1,
   8937         -1,
   8938         3,
   8939     },
   8940 #endif /* chips */
   8941 
   8942 #if defined(BCM_56370_A0)
   8943     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_RESET_READ_IDr */
   8944         soc_block_list[61],
   8945         soc_iprocreg,
   8946         1,
   8947         0,
   8948         0x10258808,
   8949         SOC_REG_FLAG_RO,
   8950         0,
   8951         2,
   8952         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
   8953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8954         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8955         -1,
   8956         -1,
   8957         3,
   8958     },
   8959 #endif /* chips */
   8960 
   8961 #if defined(BCM_56370_A0)
   8962     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_RESET_STATUSr */
   8963         soc_block_list[61],
   8964         soc_iprocreg,
   8965         1,
   8966         0,
   8967         0x10258804,
   8968         SOC_REG_FLAG_RO,
   8969         0,
   8970         5,
   8971         soc_A9JTAG_M0_IDM_IDM_RESET_STATUS_BCM53400_A0r_fields,
   8972         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8973         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8974         -1,
   8975         -1,
   8976         3,
   8977     },
   8978 #endif /* chips */
   8979 
   8980 #if defined(BCM_56370_A0)
   8981     { /* SOC_REG_INT_BOOT_NIC_S0_IDM_IDM_RESET_WRITE_IDr */
   8982         soc_block_list[61],
   8983         soc_iprocreg,
   8984         1,
   8985         0,
   8986         0x1025880c,
   8987         SOC_REG_FLAG_RO,
   8988         0,
   8989         2,
   8990         soc_A9JTAG_S0_IDM_IDM_ERROR_LOG_ID_BCM53400_A0r_fields,
   8991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   8992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   8993         -1,
   8994         -1,
   8995         3,
   8996     },
   8997 #endif /* chips */
   8998 
   8999 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9000     { /* SOC_REG_INT_BRCM_RESERVED_CPM_0r */
   9001         soc_block_list[200],
   9002         soc_portreg,
   9003         1,
   9004         0,
   9005         0x85500,
   9006         SOC_REG_FLAG_64_BITS,
   9007         0,
   9008         4,
   9009         soc_BRCM_RESERVED_CPM_0r_fields,
   9010         SOC_RESET_VAL_DEC(0x0001fe10, 0x00000000)
   9011         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
   9012         -1,
   9013         -1,
   9014     },
   9015 #endif /* chips */
   9016 
   9017 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9018     { /* SOC_REG_INT_BRCM_RESERVED_CPM_1r */
   9019         soc_block_list[200],
   9020         soc_portreg,
   9021         1,
   9022         0,
   9023         0x85600,
   9024         SOC_REG_FLAG_COUNTER |
   9025                           SOC_REG_FLAG_RO,
   9026         0,
   9027         1,
   9028         soc_BRCM_RESERVED_CPM_1r_fields,
   9029         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9030         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9031         134,
   9032         -1,
   9033     },
   9034 #endif /* chips */
   9035 
   9036 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9037     { /* SOC_REG_INT_BRCM_RESERVED_CPM_2r */
   9038         soc_block_list[200],
   9039         soc_portreg,
   9040         1,
   9041         0,
   9042         0x86700,
   9043         SOC_REG_FLAG_64_BITS,
   9044         0,
   9045         1,
   9046         soc_BRCM_RESERVED_CPM_2r_fields,
   9047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9048         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9049         -1,
   9050         -1,
   9051     },
   9052 #endif /* chips */
   9053 
   9054 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9055     { /* SOC_REG_INT_BRCM_RESERVED_CPM_3r */
   9056         soc_block_list[200],
   9057         soc_portreg,
   9058         1,
   9059         0,
   9060         0x86800,
   9061         SOC_REG_FLAG_64_BITS,
   9062         0,
   9063         5,
   9064         soc_BRCM_RESERVED_CPM_3r_fields,
   9065         SOC_RESET_VAL_DEC(0x07800015, 0x00000006)
   9066         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
   9067         -1,
   9068         -1,
   9069     },
   9070 #endif /* chips */
   9071 
   9072 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9073     { /* SOC_REG_INT_BRCM_RESERVED_CPM_4r */
   9074         soc_block_list[200],
   9075         soc_portreg,
   9076         1,
   9077         0,
   9078         0x86900,
   9079         SOC_REG_FLAG_64_BITS,
   9080         0,
   9081         2,
   9082         soc_BRCM_RESERVED_CPM_4r_fields,
   9083         SOC_RESET_VAL_DEC(0x000257ff, 0x00001dff)
   9084         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9085         -1,
   9086         -1,
   9087     },
   9088 #endif /* chips */
   9089 
   9090 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9091     { /* SOC_REG_INT_BRCM_RESERVED_CPM_5r */
   9092         soc_block_list[200],
   9093         soc_portreg,
   9094         1,
   9095         0,
   9096         0x86a00,
   9097         SOC_REG_FLAG_64_BITS,
   9098         0,
   9099         7,
   9100         soc_BRCM_RESERVED_CPM_5r_fields,
   9101         SOC_RESET_VAL_DEC(0x00000000, 0x00000001)
   9102         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   9103         -1,
   9104         -1,
   9105     },
   9106 #endif /* chips */
   9107 
   9108 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9109     { /* SOC_REG_INT_BRCM_RESERVED_CPM_6r */
   9110         soc_block_list[200],
   9111         soc_portreg,
   9112         1,
   9113         0,
   9114         0x86b00,
   9115         SOC_REG_FLAG_COUNTER |
   9116                           SOC_REG_FLAG_RO,
   9117         0,
   9118         1,
   9119         soc_BRCM_RESERVED_CPM_6r_fields,
   9120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9121         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9122         155,
   9123         -1,
   9124     },
   9125 #endif /* chips */
   9126 
   9127 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9128     { /* SOC_REG_INT_BRCM_RESERVED_CPM_7r */
   9129         soc_block_list[200],
   9130         soc_portreg,
   9131         1,
   9132         0,
   9133         0x86c00,
   9134         SOC_REG_FLAG_COUNTER |
   9135                           SOC_REG_FLAG_RO,
   9136         0,
   9137         1,
   9138         soc_BRCM_RESERVED_CPM_7r_fields,
   9139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9141         156,
   9142         -1,
   9143     },
   9144 #endif /* chips */
   9145 
   9146 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9147     { /* SOC_REG_INT_BRCM_RESERVED_CPM_8r */
   9148         soc_block_list[200],
   9149         soc_portreg,
   9150         1,
   9151         0,
   9152         0x86d00,
   9153         SOC_REG_FLAG_COUNTER |
   9154                           SOC_REG_FLAG_RO,
   9155         0,
   9156         1,
   9157         soc_BRCM_RESERVED_CPM_8r_fields,
   9158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9159         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9160         157,
   9161         -1,
   9162     },
   9163 #endif /* chips */
   9164 
   9165 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9166     { /* SOC_REG_INT_BRCM_RESERVED_CPM_9r */
   9167         soc_block_list[200],
   9168         soc_portreg,
   9169         1,
   9170         0,
   9171         0x86e00,
   9172         SOC_REG_FLAG_COUNTER |
   9173                           SOC_REG_FLAG_RO,
   9174         0,
   9175         1,
   9176         soc_BRCM_RESERVED_CPM_9r_fields,
   9177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9178         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9179         158,
   9180         -1,
   9181     },
   9182 #endif /* chips */
   9183 
   9184 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9185     { /* SOC_REG_INT_BRCM_RESERVED_CPM_12r */
   9186         soc_block_list[200],
   9187         soc_portreg,
   9188         1,
   9189         0,
   9190         0x87900,
   9191         SOC_REG_FLAG_64_BITS,
   9192         0,
   9193         9,
   9194         soc_BRCM_RESERVED_CPM_12r_fields,
   9195         SOC_RESET_VAL_DEC(0x00035420, 0x00000000)
   9196         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
   9197         -1,
   9198         -1,
   9199     },
   9200 #endif /* chips */
   9201 
   9202 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9203     { /* SOC_REG_INT_BRCM_RESERVED_CPM_13r */
   9204         soc_block_list[200],
   9205         soc_portreg,
   9206         1,
   9207         0,
   9208         0x87a00,
   9209         SOC_REG_FLAG_64_BITS,
   9210         0,
   9211         1,
   9212         soc_BRCM_RESERVED_CPM_13r_fields,
   9213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9214         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9215         -1,
   9216         -1,
   9217     },
   9218 #endif /* chips */
   9219 
   9220 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9221     { /* SOC_REG_INT_BRCM_RESERVED_CPM_14r */
   9222         soc_block_list[200],
   9223         soc_portreg,
   9224         1,
   9225         0,
   9226         0x87b00,
   9227         SOC_REG_FLAG_64_BITS,
   9228         0,
   9229         10,
   9230         soc_BRCM_RESERVED_CPM_14r_fields,
   9231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9232         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9233         -1,
   9234         -1,
   9235     },
   9236 #endif /* chips */
   9237 
   9238 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9239     { /* SOC_REG_INT_BRCM_RESERVED_CPM_15r */
   9240         soc_block_list[200],
   9241         soc_portreg,
   9242         1,
   9243         0,
   9244         0x87c00,
   9245         SOC_REG_FLAG_RO,
   9246         0,
   9247         5,
   9248         soc_BRCM_RESERVED_CPM_15r_fields,
   9249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9250         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
   9251         -1,
   9252         -1,
   9253     },
   9254 #endif /* chips */
   9255 
   9256 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9257     { /* SOC_REG_INT_BRCM_RESERVED_CPM_16r */
   9258         soc_block_list[200],
   9259         soc_portreg,
   9260         1,
   9261         0,
   9262         0x87d00,
   9263         SOC_REG_FLAG_RO,
   9264         0,
   9265         1,
   9266         soc_BRCM_RESERVED_CPM_16r_fields,
   9267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9268         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9269         -1,
   9270         -1,
   9271     },
   9272 #endif /* chips */
   9273 
   9274 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9275     { /* SOC_REG_INT_BRCM_RESERVED_CPM_300r */
   9276         soc_block_list[200],
   9277         soc_portreg,
   9278         1,
   9279         0,
   9280         0x20400,
   9281         0,
   9282         0,
   9283         2,
   9284         soc_BRCM_RESERVED_CPM_300r_fields,
   9285         SOC_RESET_VAL_DEC(0x000021c2, 0x00000000)
   9286         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
   9287         -1,
   9288         -1,
   9289     },
   9290 #endif /* chips */
   9291 
   9292 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9293     { /* SOC_REG_INT_BRCM_RESERVED_CPM_302r */
   9294         soc_block_list[200],
   9295         soc_portreg,
   9296         1,
   9297         0,
   9298         0x23600,
   9299         SOC_REG_FLAG_64_BITS,
   9300         0,
   9301         64,
   9302         soc_BRCM_RESERVED_CPM_302r_fields,
   9303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9304         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9305         -1,
   9306         -1,
   9307     },
   9308 #endif /* chips */
   9309 
   9310 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9311     { /* SOC_REG_INT_BRCM_RESERVED_CPM_303r */
   9312         soc_block_list[200],
   9313         soc_portreg,
   9314         1,
   9315         0,
   9316         0x23700,
   9317         SOC_REG_FLAG_64_BITS,
   9318         0,
   9319         64,
   9320         soc_BRCM_RESERVED_CPM_303r_fields,
   9321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9322         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9323         -1,
   9324         -1,
   9325     },
   9326 #endif /* chips */
   9327 
   9328 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9329     { /* SOC_REG_INT_BRCM_RESERVED_CPM_304r */
   9330         soc_block_list[200],
   9331         soc_portreg,
   9332         1,
   9333         0,
   9334         0x23800,
   9335         SOC_REG_FLAG_64_BITS,
   9336         0,
   9337         64,
   9338         soc_BRCM_RESERVED_CPM_304r_fields,
   9339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9340         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9341         -1,
   9342         -1,
   9343     },
   9344 #endif /* chips */
   9345 
   9346 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9347     { /* SOC_REG_INT_BRCM_RESERVED_CPM_305r */
   9348         soc_block_list[200],
   9349         soc_portreg,
   9350         1,
   9351         0,
   9352         0x23900,
   9353         SOC_REG_FLAG_64_BITS,
   9354         0,
   9355         64,
   9356         soc_BRCM_RESERVED_CPM_305r_fields,
   9357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9358         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9359         -1,
   9360         -1,
   9361     },
   9362 #endif /* chips */
   9363 
   9364 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9365     { /* SOC_REG_INT_BRCM_RESERVED_CPM_307r */
   9366         soc_block_list[200],
   9367         soc_portreg,
   9368         1,
   9369         0,
   9370         0x26c00,
   9371         SOC_REG_FLAG_64_BITS,
   9372         0,
   9373         9,
   9374         soc_BRCM_RESERVED_CPM_307r_fields,
   9375         SOC_RESET_VAL_DEC(0x0ff00ff8, 0x00101900)
   9376         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
   9377         -1,
   9378         -1,
   9379     },
   9380 #endif /* chips */
   9381 
   9382 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9383     { /* SOC_REG_INT_BRCM_RESERVED_CPM_308r */
   9384         soc_block_list[200],
   9385         soc_portreg,
   9386         1,
   9387         0,
   9388         0x26d00,
   9389         SOC_REG_FLAG_64_BITS,
   9390         0,
   9391         4,
   9392         soc_BRCM_RESERVED_CPM_308r_fields,
   9393         SOC_RESET_VAL_DEC(0x00800780, 0x07800015)
   9394         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9395         -1,
   9396         -1,
   9397     },
   9398 #endif /* chips */
   9399 
   9400 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9401     { /* SOC_REG_INT_BRCM_RESERVED_CPM_309r */
   9402         soc_block_list[200],
   9403         soc_portreg,
   9404         1,
   9405         0,
   9406         0x26e00,
   9407         SOC_REG_FLAG_64_BITS,
   9408         0,
   9409         1,
   9410         soc_BRCM_RESERVED_CPM_309r_fields,
   9411         SOC_RESET_VAL_DEC(0x002ee000, 0x00000000)
   9412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9413         -1,
   9414         -1,
   9415     },
   9416 #endif /* chips */
   9417 
   9418 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9419     { /* SOC_REG_INT_BRCM_RESERVED_CPM_310r */
   9420         soc_block_list[200],
   9421         soc_portreg,
   9422         1,
   9423         0,
   9424         0x26f00,
   9425         SOC_REG_FLAG_64_BITS,
   9426         0,
   9427         1,
   9428         soc_BRCM_RESERVED_CPM_310r_fields,
   9429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9430         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9431         -1,
   9432         -1,
   9433     },
   9434 #endif /* chips */
   9435 
   9436 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9437     { /* SOC_REG_INT_BRCM_RESERVED_CPM_311r */
   9438         soc_block_list[200],
   9439         soc_portreg,
   9440         1,
   9441         0,
   9442         0x27000,
   9443         SOC_REG_FLAG_64_BITS,
   9444         0,
   9445         12,
   9446         soc_BRCM_RESERVED_CPM_311r_fields,
   9447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9448         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   9449         -1,
   9450         -1,
   9451     },
   9452 #endif /* chips */
   9453 
   9454 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9455     { /* SOC_REG_INT_BRCM_RESERVED_CPM_312r */
   9456         soc_block_list[200],
   9457         soc_portreg,
   9458         1,
   9459         0,
   9460         0x27100,
   9461         SOC_REG_FLAG_64_BITS |
   9462                           SOC_REG_FLAG_RO,
   9463         0,
   9464         7,
   9465         soc_BRCM_RESERVED_CPM_312r_fields,
   9466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9467         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
   9468         -1,
   9469         -1,
   9470     },
   9471 #endif /* chips */
   9472 
   9473 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9474     { /* SOC_REG_INT_BRCM_RESERVED_CPM_313r */
   9475         soc_block_list[200],
   9476         soc_portreg,
   9477         1,
   9478         0,
   9479         0x27200,
   9480         SOC_REG_FLAG_64_BITS |
   9481                           SOC_REG_FLAG_RO,
   9482         0,
   9483         1,
   9484         soc_BRCM_RESERVED_CPM_313r_fields,
   9485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9486         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
   9487         -1,
   9488         -1,
   9489     },
   9490 #endif /* chips */
   9491 
   9492 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9493     { /* SOC_REG_INT_BRCM_RESERVED_CPM_314r */
   9494         soc_block_list[200],
   9495         soc_portreg,
   9496         1,
   9497         0,
   9498         0x27300,
   9499         SOC_REG_FLAG_64_BITS |
   9500                           SOC_REG_FLAG_RO,
   9501         0,
   9502         2,
   9503         soc_BRCM_RESERVED_CPM_314r_fields,
   9504         SOC_RESET_VAL_DEC(0x000257ff, 0x00001dff)
   9505         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9506         -1,
   9507         -1,
   9508     },
   9509 #endif /* chips */
   9510 
   9511 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9512     { /* SOC_REG_INT_BRCM_RESERVED_CPM_315r */
   9513         soc_block_list[200],
   9514         soc_portreg,
   9515         1,
   9516         0,
   9517         0x28700,
   9518         0,
   9519         0,
   9520         3,
   9521         soc_BRCM_RESERVED_CPM_315r_fields,
   9522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9523         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
   9524         -1,
   9525         -1,
   9526     },
   9527 #endif /* chips */
   9528 
   9529 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9530     { /* SOC_REG_INT_BRCM_RESERVED_CPM_316r */
   9531         soc_block_list[200],
   9532         soc_portreg,
   9533         1,
   9534         0,
   9535         0x28800,
   9536         SOC_REG_FLAG_COUNTER |
   9537                           SOC_REG_FLAG_RO,
   9538         0,
   9539         1,
   9540         soc_BRCM_RESERVED_CPM_316r_fields,
   9541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9542         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9543         168,
   9544         -1,
   9545     },
   9546 #endif /* chips */
   9547 
   9548 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9549     { /* SOC_REG_INT_BRCM_RESERVED_CPM_317r */
   9550         soc_block_list[200],
   9551         soc_portreg,
   9552         1,
   9553         0,
   9554         0x28900,
   9555         SOC_REG_FLAG_64_BITS,
   9556         0,
   9557         2,
   9558         soc_BRCM_RESERVED_CPM_317r_fields,
   9559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9560         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
   9561         -1,
   9562         -1,
   9563     },
   9564 #endif /* chips */
   9565 
   9566 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9567     { /* SOC_REG_INT_BRCM_RESERVED_CPM_318r */
   9568         soc_block_list[200],
   9569         soc_portreg,
   9570         1,
   9571         0,
   9572         0x28a00,
   9573         0,
   9574         0,
   9575         3,
   9576         soc_BRCM_RESERVED_CPM_318r_fields,
   9577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9578         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
   9579         -1,
   9580         -1,
   9581     },
   9582 #endif /* chips */
   9583 
   9584 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9585     { /* SOC_REG_INT_BRCM_RESERVED_CPM_319r */
   9586         soc_block_list[200],
   9587         soc_portreg,
   9588         1,
   9589         0,
   9590         0x28b00,
   9591         SOC_REG_FLAG_64_BITS,
   9592         0,
   9593         3,
   9594         soc_BRCM_RESERVED_CPM_319r_fields,
   9595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9596         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   9597         -1,
   9598         -1,
   9599     },
   9600 #endif /* chips */
   9601 
   9602 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9603     { /* SOC_REG_INT_BRCM_RESERVED_CPM_320r */
   9604         soc_block_list[200],
   9605         soc_portreg,
   9606         1,
   9607         0,
   9608         0x28c00,
   9609         SOC_REG_FLAG_64_BITS,
   9610         0,
   9611         3,
   9612         soc_BRCM_RESERVED_CPM_320r_fields,
   9613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9614         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   9615         -1,
   9616         -1,
   9617     },
   9618 #endif /* chips */
   9619 
   9620 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9621     { /* SOC_REG_INT_BRCM_RESERVED_CPM_321r */
   9622         soc_block_list[200],
   9623         soc_portreg,
   9624         1,
   9625         0,
   9626         0x28d00,
   9627         SOC_REG_FLAG_64_BITS,
   9628         0,
   9629         3,
   9630         soc_BRCM_RESERVED_CPM_321r_fields,
   9631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   9633         -1,
   9634         -1,
   9635     },
   9636 #endif /* chips */
   9637 
   9638 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9639     { /* SOC_REG_INT_BRCM_RESERVED_CPM_322r */
   9640         soc_block_list[200],
   9641         soc_portreg,
   9642         1,
   9643         0,
   9644         0x28e00,
   9645         SOC_REG_FLAG_64_BITS,
   9646         0,
   9647         3,
   9648         soc_BRCM_RESERVED_CPM_322r_fields,
   9649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
   9651         -1,
   9652         -1,
   9653     },
   9654 #endif /* chips */
   9655 
   9656 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9657     { /* SOC_REG_INT_BRCM_RESERVED_CPM_323r */
   9658         soc_block_list[200],
   9659         soc_portreg,
   9660         1,
   9661         0,
   9662         0x28f00,
   9663         SOC_REG_FLAG_COUNTER |
   9664                           SOC_REG_FLAG_RO,
   9665         0,
   9666         1,
   9667         soc_BRCM_RESERVED_CPM_323r_fields,
   9668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9670         191,
   9671         -1,
   9672     },
   9673 #endif /* chips */
   9674 
   9675 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9676     { /* SOC_REG_INT_BRCM_RESERVED_CPM_324r */
   9677         soc_block_list[200],
   9678         soc_portreg,
   9679         1,
   9680         0,
   9681         0x29000,
   9682         SOC_REG_FLAG_COUNTER |
   9683                           SOC_REG_FLAG_RO,
   9684         0,
   9685         1,
   9686         soc_BRCM_RESERVED_CPM_324r_fields,
   9687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9689         192,
   9690         -1,
   9691     },
   9692 #endif /* chips */
   9693 
   9694 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9695     { /* SOC_REG_INT_BRCM_RESERVED_CPM_325r */
   9696         soc_block_list[200],
   9697         soc_portreg,
   9698         1,
   9699         0,
   9700         0x29100,
   9701         SOC_REG_FLAG_COUNTER |
   9702                           SOC_REG_FLAG_RO,
   9703         0,
   9704         1,
   9705         soc_BRCM_RESERVED_CPM_325r_fields,
   9706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9708         193,
   9709         -1,
   9710     },
   9711 #endif /* chips */
   9712 
   9713 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9714     { /* SOC_REG_INT_BRCM_RESERVED_CPM_326r */
   9715         soc_block_list[200],
   9716         soc_portreg,
   9717         1,
   9718         0,
   9719         0x29200,
   9720         SOC_REG_FLAG_COUNTER |
   9721                           SOC_REG_FLAG_RO,
   9722         0,
   9723         1,
   9724         soc_BRCM_RESERVED_CPM_326r_fields,
   9725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9726         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9727         146,
   9728         -1,
   9729     },
   9730 #endif /* chips */
   9731 
   9732 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9733     { /* SOC_REG_INT_BRCM_RESERVED_CPM_327r */
   9734         soc_block_list[200],
   9735         soc_portreg,
   9736         1,
   9737         0,
   9738         0x29300,
   9739         SOC_REG_FLAG_COUNTER |
   9740                           SOC_REG_FLAG_RO,
   9741         0,
   9742         1,
   9743         soc_BRCM_RESERVED_CPM_327r_fields,
   9744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9746         195,
   9747         -1,
   9748     },
   9749 #endif /* chips */
   9750 
   9751 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9752     { /* SOC_REG_INT_BRCM_RESERVED_EP_1r */
   9753         soc_block_list[3],
   9754         soc_genreg,
   9755         1,
   9756         0,
   9757         0x6002700,
   9758         0,
   9759         0,
   9760         1,
   9761         soc_BRCM_RESERVED_EP_1r_fields,
   9762         SOC_RESET_VAL_DEC(0x00008951, 0x00000000)
   9763         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9764         -1,
   9765         -1,
   9766     },
   9767 #endif /* chips */
   9768 
   9769 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9770     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_4r */
   9771         soc_block_list[61],
   9772         soc_iprocreg,
   9773         1,
   9774         0,
   9775         0x326e000,
   9776         0,
   9777         0,
   9778         1,
   9779         soc_BRCM_RESERVED_IPROC_4r_fields,
   9780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9781         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
   9782         -1,
   9783         -1,
   9784     },
   9785 #endif /* chips */
   9786 
   9787 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9788     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_5r */
   9789         soc_block_list[61],
   9790         soc_iprocreg,
   9791         1,
   9792         0,
   9793         0x326e004,
   9794         0,
   9795         0,
   9796         1,
   9797         soc_BRCM_RESERVED_IPROC_5r_fields,
   9798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9799         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9800         -1,
   9801         -1,
   9802     },
   9803 #endif /* chips */
   9804 
   9805 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9806     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_6r */
   9807         soc_block_list[61],
   9808         soc_iprocreg,
   9809         1,
   9810         0,
   9811         0x326e008,
   9812         SOC_REG_FLAG_RO,
   9813         0,
   9814         2,
   9815         soc_BRCM_RESERVED_IPROC_6r_fields,
   9816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9817         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
   9818         -1,
   9819         -1,
   9820     },
   9821 #endif /* chips */
   9822 
   9823 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9824     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_7r */
   9825         soc_block_list[61],
   9826         soc_iprocreg,
   9827         1,
   9828         0,
   9829         0x326e00c,
   9830         SOC_REG_FLAG_RO,
   9831         0,
   9832         1,
   9833         soc_BRCM_RESERVED_IPROC_7r_fields,
   9834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9835         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9836         -1,
   9837         -1,
   9838     },
   9839 #endif /* chips */
   9840 
   9841 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9842     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_8r */
   9843         soc_block_list[61],
   9844         soc_iprocreg,
   9845         1,
   9846         0,
   9847         0x326e010,
   9848         SOC_REG_FLAG_RO,
   9849         0,
   9850         1,
   9851         soc_BRCM_RESERVED_IPROC_8r_fields,
   9852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9854         -1,
   9855         -1,
   9856     },
   9857 #endif /* chips */
   9858 
   9859 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9860     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_9r */
   9861         soc_block_list[61],
   9862         soc_iprocreg,
   9863         1,
   9864         0,
   9865         0x326e014,
   9866         0,
   9867         0,
   9868         2,
   9869         soc_BRCM_RESERVED_IPROC_9r_fields,
   9870         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9871         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9872         -1,
   9873         -1,
   9874     },
   9875 #endif /* chips */
   9876 
   9877 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9878     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_10r */
   9879         soc_block_list[61],
   9880         soc_iprocreg,
   9881         1,
   9882         0,
   9883         0x326e018,
   9884         0,
   9885         0,
   9886         1,
   9887         soc_BRCM_RESERVED_IPROC_10r_fields,
   9888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9889         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
   9890         -1,
   9891         -1,
   9892     },
   9893 #endif /* chips */
   9894 
   9895 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9896     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_11r */
   9897         soc_block_list[61],
   9898         soc_iprocreg,
   9899         1,
   9900         0,
   9901         0x326e01c,
   9902         0,
   9903         0,
   9904         1,
   9905         soc_BRCM_RESERVED_IPROC_11r_fields,
   9906         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9907         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
   9908         -1,
   9909         -1,
   9910     },
   9911 #endif /* chips */
   9912 
   9913 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9914     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_12r */
   9915         soc_block_list[61],
   9916         soc_iprocreg,
   9917         1,
   9918         0,
   9919         0x326e020,
   9920         0,
   9921         0,
   9922         1,
   9923         soc_BRCM_RESERVED_IPROC_12r_fields,
   9924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9925         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
   9926         -1,
   9927         -1,
   9928     },
   9929 #endif /* chips */
   9930 
   9931 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9932     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_13r */
   9933         soc_block_list[61],
   9934         soc_iprocreg,
   9935         1,
   9936         0,
   9937         0x326e024,
   9938         0,
   9939         0,
   9940         1,
   9941         soc_BRCM_RESERVED_IPROC_13r_fields,
   9942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9943         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9944         -1,
   9945         -1,
   9946     },
   9947 #endif /* chips */
   9948 
   9949 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9950     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_14r */
   9951         soc_block_list[61],
   9952         soc_iprocreg,
   9953         1,
   9954         0,
   9955         0x326e028,
   9956         0,
   9957         0,
   9958         2,
   9959         soc_BRCM_RESERVED_IPROC_14r_fields,
   9960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9961         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
   9962         -1,
   9963         -1,
   9964     },
   9965 #endif /* chips */
   9966 
   9967 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9968     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_15r */
   9969         soc_block_list[61],
   9970         soc_iprocreg,
   9971         1,
   9972         0,
   9973         0x326e02c,
   9974         SOC_REG_FLAG_RO,
   9975         0,
   9976         1,
   9977         soc_BRCM_RESERVED_IPROC_15r_fields,
   9978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9979         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
   9980         -1,
   9981         -1,
   9982     },
   9983 #endif /* chips */
   9984 
   9985 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
   9986     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_16r */
   9987         soc_block_list[61],
   9988         soc_iprocreg,
   9989         1,
   9990         0,
   9991         0x326e030,
   9992         0,
   9993         0,
   9994         1,
   9995         soc_BRCM_RESERVED_IPROC_16r_fields,
   9996         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
   9997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
   9998         -1,
   9999         -1,
  10000     },
  10001 #endif /* chips */
  10002 
  10003 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10004     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_17r */
  10005         soc_block_list[61],
  10006         soc_iprocreg,
  10007         1,
  10008         0,
  10009         0x326e034,
  10010         0,
  10011         0,
  10012         1,
  10013         soc_BRCM_RESERVED_IPROC_17r_fields,
  10014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10015         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10016         -1,
  10017         -1,
  10018     },
  10019 #endif /* chips */
  10020 
  10021 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10022     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_18r */
  10023         soc_block_list[61],
  10024         soc_iprocreg,
  10025         1,
  10026         0,
  10027         0x326e038,
  10028         0,
  10029         0,
  10030         1,
  10031         soc_BRCM_RESERVED_IPROC_18r_fields,
  10032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10034         -1,
  10035         -1,
  10036     },
  10037 #endif /* chips */
  10038 
  10039 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10040     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_19r */
  10041         soc_block_list[61],
  10042         soc_iprocreg,
  10043         1,
  10044         0,
  10045         0x326e03c,
  10046         0,
  10047         0,
  10048         1,
  10049         soc_BRCM_RESERVED_IPROC_19r_fields,
  10050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10051         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  10052         -1,
  10053         -1,
  10054     },
  10055 #endif /* chips */
  10056 
  10057 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10058     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_20r */
  10059         soc_block_list[61],
  10060         soc_iprocreg,
  10061         1,
  10062         0,
  10063         0x326e040,
  10064         SOC_REG_FLAG_RO,
  10065         0,
  10066         1,
  10067         soc_BRCM_RESERVED_IPROC_20r_fields,
  10068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10069         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10070         -1,
  10071         -1,
  10072     },
  10073 #endif /* chips */
  10074 
  10075 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10076     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_21r */
  10077         soc_block_list[61],
  10078         soc_iprocreg,
  10079         1,
  10080         0,
  10081         0x326e044,
  10082         SOC_REG_FLAG_RO,
  10083         0,
  10084         1,
  10085         soc_BRCM_RESERVED_IPROC_21r_fields,
  10086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10087         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10088         -1,
  10089         -1,
  10090     },
  10091 #endif /* chips */
  10092 
  10093 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10094     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_22r */
  10095         soc_block_list[61],
  10096         soc_iprocreg,
  10097         1,
  10098         0,
  10099         0x326e048,
  10100         SOC_REG_FLAG_RO,
  10101         0,
  10102         1,
  10103         soc_BRCM_RESERVED_IPROC_22r_fields,
  10104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10105         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10106         -1,
  10107         -1,
  10108     },
  10109 #endif /* chips */
  10110 
  10111 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10112     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_23r */
  10113         soc_block_list[61],
  10114         soc_iprocreg,
  10115         1,
  10116         0,
  10117         0x326e04c,
  10118         SOC_REG_FLAG_RO,
  10119         0,
  10120         1,
  10121         soc_BRCM_RESERVED_IPROC_23r_fields,
  10122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10123         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  10124         -1,
  10125         -1,
  10126     },
  10127 #endif /* chips */
  10128 
  10129 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10130     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_24r */
  10131         soc_block_list[61],
  10132         soc_iprocreg,
  10133         1,
  10134         0,
  10135         0x326e050,
  10136         SOC_REG_FLAG_RO,
  10137         0,
  10138         1,
  10139         soc_BRCM_RESERVED_IPROC_24r_fields,
  10140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10141         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10142         -1,
  10143         -1,
  10144     },
  10145 #endif /* chips */
  10146 
  10147 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10148     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_25r */
  10149         soc_block_list[61],
  10150         soc_iprocreg,
  10151         1,
  10152         0,
  10153         0x326e054,
  10154         SOC_REG_FLAG_RO,
  10155         0,
  10156         1,
  10157         soc_BRCM_RESERVED_IPROC_25r_fields,
  10158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10159         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10160         -1,
  10161         -1,
  10162     },
  10163 #endif /* chips */
  10164 
  10165 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10166     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_26r */
  10167         soc_block_list[61],
  10168         soc_iprocreg,
  10169         1,
  10170         0,
  10171         0x326e058,
  10172         0,
  10173         0,
  10174         2,
  10175         soc_BRCM_RESERVED_IPROC_26r_fields,
  10176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10177         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10178         -1,
  10179         -1,
  10180     },
  10181 #endif /* chips */
  10182 
  10183 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10184     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_27r */
  10185         soc_block_list[61],
  10186         soc_iprocreg,
  10187         1,
  10188         0,
  10189         0x326e05c,
  10190         0,
  10191         0,
  10192         1,
  10193         soc_BRCM_RESERVED_IPROC_27r_fields,
  10194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10195         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  10196         -1,
  10197         -1,
  10198     },
  10199 #endif /* chips */
  10200 
  10201 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10202     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_28r */
  10203         soc_block_list[61],
  10204         soc_iprocreg,
  10205         1,
  10206         0,
  10207         0x326e060,
  10208         0,
  10209         0,
  10210         1,
  10211         soc_BRCM_RESERVED_IPROC_28r_fields,
  10212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10213         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10214         -1,
  10215         -1,
  10216     },
  10217 #endif /* chips */
  10218 
  10219 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10220     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_29r */
  10221         soc_block_list[61],
  10222         soc_iprocreg,
  10223         1,
  10224         0,
  10225         0x326e064,
  10226         0,
  10227         0,
  10228         1,
  10229         soc_BRCM_RESERVED_IPROC_29r_fields,
  10230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10231         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  10232         -1,
  10233         -1,
  10234     },
  10235 #endif /* chips */
  10236 
  10237 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10238     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_30r */
  10239         soc_block_list[61],
  10240         soc_iprocreg,
  10241         1,
  10242         0,
  10243         0x326e068,
  10244         0,
  10245         0,
  10246         1,
  10247         soc_BRCM_RESERVED_IPROC_30r_fields,
  10248         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10249         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10250         -1,
  10251         -1,
  10252     },
  10253 #endif /* chips */
  10254 
  10255 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10256     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_31r */
  10257         soc_block_list[61],
  10258         soc_iprocreg,
  10259         1,
  10260         0,
  10261         0x326e06c,
  10262         0,
  10263         0,
  10264         1,
  10265         soc_BRCM_RESERVED_IPROC_31r_fields,
  10266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10267         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10268         -1,
  10269         -1,
  10270     },
  10271 #endif /* chips */
  10272 
  10273 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10274     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_32r */
  10275         soc_block_list[61],
  10276         soc_iprocreg,
  10277         1,
  10278         0,
  10279         0x326e070,
  10280         0,
  10281         0,
  10282         2,
  10283         soc_BRCM_RESERVED_IPROC_32r_fields,
  10284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10285         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10286         -1,
  10287         -1,
  10288     },
  10289 #endif /* chips */
  10290 
  10291 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10292     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_33r */
  10293         soc_block_list[61],
  10294         soc_iprocreg,
  10295         1,
  10296         0,
  10297         0x326e074,
  10298         0,
  10299         0,
  10300         2,
  10301         soc_BRCM_RESERVED_IPROC_33r_fields,
  10302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10303         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  10304         -1,
  10305         -1,
  10306     },
  10307 #endif /* chips */
  10308 
  10309 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10310     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_34r */
  10311         soc_block_list[61],
  10312         soc_iprocreg,
  10313         1,
  10314         0,
  10315         0x326e078,
  10316         0,
  10317         0,
  10318         1,
  10319         soc_BRCM_RESERVED_IPROC_34r_fields,
  10320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10321         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  10322         -1,
  10323         -1,
  10324     },
  10325 #endif /* chips */
  10326 
  10327 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10328     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_35r */
  10329         soc_block_list[61],
  10330         soc_iprocreg,
  10331         1,
  10332         0,
  10333         0x326e07c,
  10334         0,
  10335         0,
  10336         1,
  10337         soc_BRCM_RESERVED_IPROC_35r_fields,
  10338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10339         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10340         -1,
  10341         -1,
  10342     },
  10343 #endif /* chips */
  10344 
  10345 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10346     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_36r */
  10347         soc_block_list[61],
  10348         soc_iprocreg,
  10349         1,
  10350         0,
  10351         0x326e080,
  10352         0,
  10353         0,
  10354         1,
  10355         soc_BRCM_RESERVED_IPROC_36r_fields,
  10356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10357         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  10358         -1,
  10359         -1,
  10360     },
  10361 #endif /* chips */
  10362 
  10363 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10364     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_37r */
  10365         soc_block_list[61],
  10366         soc_iprocreg,
  10367         1,
  10368         0,
  10369         0x326e084,
  10370         0,
  10371         0,
  10372         1,
  10373         soc_BRCM_RESERVED_IPROC_37r_fields,
  10374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10375         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10376         -1,
  10377         -1,
  10378     },
  10379 #endif /* chips */
  10380 
  10381 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10382     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_38r */
  10383         soc_block_list[61],
  10384         soc_iprocreg,
  10385         1,
  10386         0,
  10387         0x326e088,
  10388         0,
  10389         0,
  10390         1,
  10391         soc_BRCM_RESERVED_IPROC_38r_fields,
  10392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10393         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10394         -1,
  10395         -1,
  10396     },
  10397 #endif /* chips */
  10398 
  10399 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10400     { /* SOC_REG_INT_BRCM_RESERVED_IPROC_39r */
  10401         soc_block_list[61],
  10402         soc_iprocreg,
  10403         1,
  10404         0,
  10405         0x326e08c,
  10406         0,
  10407         0,
  10408         2,
  10409         soc_BRCM_RESERVED_IPROC_39r_fields,
  10410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10411         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10412         -1,
  10413         -1,
  10414     },
  10415 #endif /* chips */
  10416 
  10417 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10418     { /* SOC_REG_INT_BRCM_RESERVED_IP_1r */
  10419         soc_block_list[5],
  10420         soc_genreg,
  10421         1,
  10422         0,
  10423         0xa00ab00,
  10424         0,
  10425         0,
  10426         1,
  10427         soc_BRCM_RESERVED_IP_1r_fields,
  10428         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10429         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10430         -1,
  10431         -1,
  10432     },
  10433 #endif /* chips */
  10434 
  10435 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10436     { /* SOC_REG_INT_BRCM_RESERVED_TOP_3r */
  10437         soc_block_list[82],
  10438         soc_genreg,
  10439         1,
  10440         0,
  10441         0x2030c00,
  10442         0,
  10443         0,
  10444         25,
  10445         soc_BRCM_RESERVED_TOP_3r_fields,
  10446         SOC_RESET_VAL_DEC(0x04411044, 0x00000000)
  10447         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10448         -1,
  10449         -1,
  10450     },
  10451 #endif /* chips */
  10452 
  10453 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10454     { /* SOC_REG_INT_BRCM_RESERVED_TOP_4r */
  10455         soc_block_list[82],
  10456         soc_genreg,
  10457         1,
  10458         0,
  10459         0x2035100,
  10460         0,
  10461         0,
  10462         14,
  10463         soc_BRCM_RESERVED_TOP_4r_fields,
  10464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10465         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10466         -1,
  10467         -1,
  10468     },
  10469 #endif /* chips */
  10470 
  10471 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10472     { /* SOC_REG_INT_BRCM_RESERVED_TOP_5r */
  10473         soc_block_list[82],
  10474         soc_genreg,
  10475         1,
  10476         0,
  10477         0x2035200,
  10478         0,
  10479         0,
  10480         5,
  10481         soc_BRCM_RESERVED_TOP_5r_fields,
  10482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10483         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10484         -1,
  10485         -1,
  10486     },
  10487 #endif /* chips */
  10488 
  10489 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10490     { /* SOC_REG_INT_BRCM_RESERVED_TOP_6r */
  10491         soc_block_list[82],
  10492         soc_genreg,
  10493         1,
  10494         0,
  10495         0x2035300,
  10496         0,
  10497         0,
  10498         7,
  10499         soc_BRCM_RESERVED_TOP_6r_fields,
  10500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10501         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10502         -1,
  10503         -1,
  10504     },
  10505 #endif /* chips */
  10506 
  10507 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10508     { /* SOC_REG_INT_BRCM_RESERVED_TOP_7r */
  10509         soc_block_list[82],
  10510         soc_genreg,
  10511         1,
  10512         0,
  10513         0x2035400,
  10514         0,
  10515         0,
  10516         7,
  10517         soc_BRCM_RESERVED_TOP_7r_fields,
  10518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10520         -1,
  10521         -1,
  10522     },
  10523 #endif /* chips */
  10524 
  10525 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10526     { /* SOC_REG_INT_BRCM_RESERVED_TOP_8r */
  10527         soc_block_list[82],
  10528         soc_genreg,
  10529         1,
  10530         0,
  10531         0x2035500,
  10532         0,
  10533         0,
  10534         3,
  10535         soc_BRCM_RESERVED_TOP_8r_fields,
  10536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10537         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10538         -1,
  10539         -1,
  10540     },
  10541 #endif /* chips */
  10542 
  10543 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10544     { /* SOC_REG_INT_BRCM_RESERVED_TOP_9r */
  10545         soc_block_list[82],
  10546         soc_genreg,
  10547         1,
  10548         0,
  10549         0x2035600,
  10550         0,
  10551         0,
  10552         7,
  10553         soc_BRCM_RESERVED_TOP_9r_fields,
  10554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10555         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10556         -1,
  10557         -1,
  10558     },
  10559 #endif /* chips */
  10560 
  10561 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10562     { /* SOC_REG_INT_BRCM_RESERVED_TOP_10r */
  10563         soc_block_list[82],
  10564         soc_genreg,
  10565         1,
  10566         0,
  10567         0x2035700,
  10568         SOC_REG_FLAG_RO,
  10569         0,
  10570         5,
  10571         soc_BRCM_RESERVED_TOP_10r_fields,
  10572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10573         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10574         -1,
  10575         -1,
  10576     },
  10577 #endif /* chips */
  10578 
  10579 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10580     { /* SOC_REG_INT_BRCM_RESERVED_TOP_11r */
  10581         soc_block_list[82],
  10582         soc_genreg,
  10583         1,
  10584         0,
  10585         0x203ef00,
  10586         0,
  10587         0,
  10588         2,
  10589         soc_BRCM_RESERVED_TOP_11r_fields,
  10590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10592         -1,
  10593         -1,
  10594     },
  10595 #endif /* chips */
  10596 
  10597 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10598     { /* SOC_REG_INT_BRCM_RESERVED_TOP_12r */
  10599         soc_block_list[82],
  10600         soc_genreg,
  10601         1,
  10602         0,
  10603         0x203f000,
  10604         0,
  10605         0,
  10606         2,
  10607         soc_BRCM_RESERVED_TOP_12r_fields,
  10608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10609         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10610         -1,
  10611         -1,
  10612     },
  10613 #endif /* chips */
  10614 
  10615 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10616     { /* SOC_REG_INT_BRCM_RESERVED_TOP_13r */
  10617         soc_block_list[82],
  10618         soc_genreg,
  10619         1,
  10620         0,
  10621         0x203f100,
  10622         0,
  10623         0,
  10624         3,
  10625         soc_BRCM_RESERVED_TOP_13r_fields,
  10626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10627         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10628         -1,
  10629         -1,
  10630     },
  10631 #endif /* chips */
  10632 
  10633 #if defined(BCM_56670_A0) || defined(BCM_56670_B0)
  10634     { /* SOC_REG_INT_BRCM_RESERVED_TOP_14r */
  10635         soc_block_list[82],
  10636         soc_genreg,
  10637         1,
  10638         0,
  10639         0x203f200,
  10640         0,
  10641         0,
  10642         3,
  10643         soc_BRCM_RESERVED_TOP_14r_fields,
  10644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10646         -1,
  10647         -1,
  10648     },
  10649 #endif /* chips */
  10650 
  10651 #if defined(BCM_88790_A0)
  10652     { /* SOC_REG_INT_BRDC_CCH_ARAD_BMPr */
  10653         soc_block_list[108],
  10654         soc_genreg,
  10655         1,
  10656         0,
  10657         0x165,
  10658         0,
  10659         0,
  10660         1,
  10661         soc_BRDC_CCH_ARAD_BMPr_fields,
  10662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10663         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  10664         -1,
  10665         -1,
  10666     },
  10667 #endif /* chips */
  10668 
  10669 #if defined(BCM_88790_A0)
  10670     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_6r */
  10671         soc_block_list[108],
  10672         soc_genreg,
  10673         1,
  10674         0,
  10675         0x102,
  10676         SOC_REG_FLAG_RO,
  10677         SOC_REG_FLAG_COUNTER_FEILDS,
  10678         2,
  10679         soc_BRDC_CCH_AUTO_DOC_NAME_6r_fields,
  10680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10681         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10682         -1,
  10683         -1,
  10684     },
  10685 #endif /* chips */
  10686 
  10687 #if defined(BCM_88790_A0)
  10688     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_7r */
  10689         soc_block_list[108],
  10690         soc_genreg,
  10691         1,
  10692         0,
  10693         0x104,
  10694         SOC_REG_FLAG_RO,
  10695         SOC_REG_FLAG_COUNTER_FEILDS,
  10696         2,
  10697         soc_BRDC_CCH_AUTO_DOC_NAME_7r_fields,
  10698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10699         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  10700         -1,
  10701         -1,
  10702     },
  10703 #endif /* chips */
  10704 
  10705 #if defined(BCM_88790_A0)
  10706     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_12r */
  10707         soc_block_list[108],
  10708         soc_genreg,
  10709         1,
  10710         0,
  10711         0x129,
  10712         SOC_REG_FLAG_RO,
  10713         SOC_REG_FLAG_COUNTER_FEILDS,
  10714         2,
  10715         soc_BRDC_CCH_AUTO_DOC_NAME_12r_fields,
  10716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10718         -1,
  10719         -1,
  10720     },
  10721 #endif /* chips */
  10722 
  10723 #if defined(BCM_88790_A0)
  10724     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_13r */
  10725         soc_block_list[108],
  10726         soc_genreg,
  10727         1,
  10728         0,
  10729         0x12a,
  10730         SOC_REG_FLAG_RO,
  10731         SOC_REG_FLAG_COUNTER_FEILDS,
  10732         2,
  10733         soc_BRDC_CCH_AUTO_DOC_NAME_13r_fields,
  10734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10736         -1,
  10737         -1,
  10738     },
  10739 #endif /* chips */
  10740 
  10741 #if defined(BCM_88790_A0)
  10742     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_14r */
  10743         soc_block_list[108],
  10744         soc_genreg,
  10745         1,
  10746         0,
  10747         0x12b,
  10748         SOC_REG_FLAG_RO,
  10749         SOC_REG_FLAG_COUNTER_FEILDS,
  10750         2,
  10751         soc_BRDC_CCH_AUTO_DOC_NAME_14r_fields,
  10752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10754         -1,
  10755         -1,
  10756     },
  10757 #endif /* chips */
  10758 
  10759 #if defined(BCM_88790_A0)
  10760     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_15r */
  10761         soc_block_list[108],
  10762         soc_genreg,
  10763         1,
  10764         0,
  10765         0x12e,
  10766         SOC_REG_FLAG_ABOVE_64_BITS,
  10767         0,
  10768         1,
  10769         soc_BRDC_CCH_AUTO_DOC_NAME_15r_fields,
  10770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10771         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10772         -1,
  10773         -1,
  10774     },
  10775 #endif /* chips */
  10776 
  10777 #if defined(BCM_88790_A0)
  10778     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_16r */
  10779         soc_block_list[108],
  10780         soc_genreg,
  10781         1,
  10782         0,
  10783         0x134,
  10784         SOC_REG_FLAG_ABOVE_64_BITS,
  10785         0,
  10786         1,
  10787         soc_BRDC_CCH_AUTO_DOC_NAME_16r_fields,
  10788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10790         -1,
  10791         -1,
  10792     },
  10793 #endif /* chips */
  10794 
  10795 #if defined(BCM_88790_A0)
  10796     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_17r */
  10797         soc_block_list[108],
  10798         soc_genreg,
  10799         1,
  10800         0,
  10801         0x13a,
  10802         SOC_REG_FLAG_ABOVE_64_BITS,
  10803         0,
  10804         1,
  10805         soc_BRDC_CCH_AUTO_DOC_NAME_17r_fields,
  10806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10808         -1,
  10809         -1,
  10810     },
  10811 #endif /* chips */
  10812 
  10813 #if defined(BCM_88790_A0)
  10814     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_18r */
  10815         soc_block_list[108],
  10816         soc_genreg,
  10817         1,
  10818         0,
  10819         0x140,
  10820         SOC_REG_FLAG_ABOVE_64_BITS,
  10821         0,
  10822         1,
  10823         soc_BRDC_CCH_AUTO_DOC_NAME_18r_fields,
  10824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10825         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10826         -1,
  10827         -1,
  10828     },
  10829 #endif /* chips */
  10830 
  10831 #if defined(BCM_88790_A0)
  10832     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_19r */
  10833         soc_block_list[108],
  10834         soc_genreg,
  10835         1,
  10836         0,
  10837         0x146,
  10838         0,
  10839         0,
  10840         1,
  10841         soc_BRDC_CCH_AUTO_DOC_NAME_19r_fields,
  10842         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10843         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10844         -1,
  10845         -1,
  10846     },
  10847 #endif /* chips */
  10848 
  10849 #if defined(BCM_88790_A0)
  10850     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_20r */
  10851         soc_block_list[108],
  10852         soc_genreg,
  10853         1,
  10854         0,
  10855         0x148,
  10856         SOC_REG_FLAG_RO,
  10857         SOC_REG_FLAG_COUNTER_FEILDS,
  10858         4,
  10859         soc_BRDC_CCH_AUTO_DOC_NAME_20r_fields,
  10860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10861         SOC_RESET_MASK_DEC(0x87ffffff, 0x00000000)
  10862         -1,
  10863         -1,
  10864     },
  10865 #endif /* chips */
  10866 
  10867 #if defined(BCM_88790_A0)
  10868     { /* SOC_REG_INT_BRDC_CCH_AUTO_DOC_NAME_21r */
  10869         soc_block_list[108],
  10870         soc_genreg,
  10871         1,
  10872         0,
  10873         0x163,
  10874         0,
  10875         0,
  10876         1,
  10877         soc_BRDC_CCH_AUTO_DOC_NAME_21r_fields,
  10878         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  10879         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  10880         -1,
  10881         -1,
  10882     },
  10883 #endif /* chips */
  10884 
  10885 #if defined(BCM_88790_A0)
  10886     { /* SOC_REG_INT_BRDC_CCH_CAPTURED_CELLr */
  10887         soc_block_list[108],
  10888         soc_genreg,
  10889         1,
  10890         0,
  10891         0x15e,
  10892         SOC_REG_FLAG_ABOVE_64_BITS |
  10893                           SOC_REG_FLAG_RO,
  10894         0,
  10895         1,
  10896         soc_BRDC_CCH_CAPTURED_CELLr_fields,
  10897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10899         -1,
  10900         -1,
  10901     },
  10902 #endif /* chips */
  10903 
  10904 #if defined(BCM_88790_A0)
  10905     { /* SOC_REG_INT_BRDC_CCH_CAPTURED_CELL_VALIDr */
  10906         soc_block_list[108],
  10907         soc_genreg,
  10908         1,
  10909         0,
  10910         0x15d,
  10911         SOC_REG_FLAG_RO,
  10912         0,
  10913         1,
  10914         soc_BRDC_CCH_CAPTURED_CELL_VALIDr_fields,
  10915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10916         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  10917         -1,
  10918         -1,
  10919     },
  10920 #endif /* chips */
  10921 
  10922 #if defined(BCM_88790_A0)
  10923     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_FIFO_DISCARD_CNTr */
  10924         soc_block_list[108],
  10925         soc_genreg,
  10926         1,
  10927         0,
  10928         0x149,
  10929         SOC_REG_FLAG_RO,
  10930         SOC_REG_FLAG_COUNTER_FEILDS,
  10931         2,
  10932         soc_BRDC_CCH_CAPTURE_FIFO_DISCARD_CNTr_fields,
  10933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  10935         -1,
  10936         -1,
  10937     },
  10938 #endif /* chips */
  10939 
  10940 #if defined(BCM_88790_A0)
  10941     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_FILTER_CELL_0r */
  10942         soc_block_list[108],
  10943         soc_genreg,
  10944         1,
  10945         0,
  10946         0x14d,
  10947         SOC_REG_FLAG_ABOVE_64_BITS,
  10948         0,
  10949         1,
  10950         soc_BRDC_CCH_CAPTURE_FILTER_CELL_0r_fields,
  10951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10953         -1,
  10954         -1,
  10955     },
  10956 #endif /* chips */
  10957 
  10958 #if defined(BCM_88790_A0)
  10959     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_FILTER_CELL_1r */
  10960         soc_block_list[108],
  10961         soc_genreg,
  10962         1,
  10963         0,
  10964         0x155,
  10965         SOC_REG_FLAG_ABOVE_64_BITS,
  10966         0,
  10967         1,
  10968         soc_BRDC_CCH_CAPTURE_FILTER_CELL_1r_fields,
  10969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10970         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10971         -1,
  10972         -1,
  10973     },
  10974 #endif /* chips */
  10975 
  10976 #if defined(BCM_88790_A0)
  10977     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_FILTER_MASK_0r */
  10978         soc_block_list[108],
  10979         soc_genreg,
  10980         1,
  10981         0,
  10982         0x151,
  10983         SOC_REG_FLAG_ABOVE_64_BITS,
  10984         0,
  10985         1,
  10986         soc_BRDC_CCH_CAPTURE_FILTER_MASK_0r_fields,
  10987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  10988         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  10989         -1,
  10990         -1,
  10991     },
  10992 #endif /* chips */
  10993 
  10994 #if defined(BCM_88790_A0)
  10995     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_FILTER_MASK_1r */
  10996         soc_block_list[108],
  10997         soc_genreg,
  10998         1,
  10999         0,
  11000         0x159,
  11001         SOC_REG_FLAG_ABOVE_64_BITS,
  11002         0,
  11003         1,
  11004         soc_BRDC_CCH_CAPTURE_FILTER_MASK_1r_fields,
  11005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11006         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  11007         -1,
  11008         -1,
  11009     },
  11010 #endif /* chips */
  11011 
  11012 #if defined(BCM_88790_A0)
  11013     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_HIT_CNTr */
  11014         soc_block_list[108],
  11015         soc_genreg,
  11016         1,
  11017         0,
  11018         0x14a,
  11019         SOC_REG_FLAG_RO,
  11020         SOC_REG_FLAG_COUNTER_FEILDS,
  11021         2,
  11022         soc_BRDC_CCH_CAPTURE_HIT_CNTr_fields,
  11023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11024         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11025         -1,
  11026         -1,
  11027     },
  11028 #endif /* chips */
  11029 
  11030 #if defined(BCM_88790_A0)
  11031     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_HIT_MASK_0_CNTr */
  11032         soc_block_list[108],
  11033         soc_genreg,
  11034         1,
  11035         0,
  11036         0x14b,
  11037         SOC_REG_FLAG_RO,
  11038         SOC_REG_FLAG_COUNTER_FEILDS,
  11039         2,
  11040         soc_BRDC_CCH_CAPTURE_HIT_MASK_0_CNTr_fields,
  11041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11043         -1,
  11044         -1,
  11045     },
  11046 #endif /* chips */
  11047 
  11048 #if defined(BCM_88790_A0)
  11049     { /* SOC_REG_INT_BRDC_CCH_CAPTURE_HIT_MASK_1_CNTr */
  11050         soc_block_list[108],
  11051         soc_genreg,
  11052         1,
  11053         0,
  11054         0x14c,
  11055         SOC_REG_FLAG_RO,
  11056         SOC_REG_FLAG_COUNTER_FEILDS,
  11057         2,
  11058         soc_BRDC_CCH_CAPTURE_HIT_MASK_1_CNTr_fields,
  11059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11061         -1,
  11062         -1,
  11063     },
  11064 #endif /* chips */
  11065 
  11066 #if defined(BCM_88790_A0)
  11067     { /* SOC_REG_INT_BRDC_CCH_CCH_CONFIGURATIONSr */
  11068         soc_block_list[108],
  11069         soc_genreg,
  11070         1,
  11071         0,
  11072         0x100,
  11073         0,
  11074         0,
  11075         6,
  11076         soc_BRDC_CCH_CCH_CONFIGURATIONSr_fields,
  11077         SOC_RESET_VAL_DEC(0x0000001e, 0x00000000)
  11078         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11079         -1,
  11080         -1,
  11081     },
  11082 #endif /* chips */
  11083 
  11084 #if defined(BCM_88790_A0)
  11085     { /* SOC_REG_INT_BRDC_CCH_CCP_0_DSCRD_CNTr */
  11086         soc_block_list[108],
  11087         soc_genreg,
  11088         1,
  11089         0,
  11090         0x106,
  11091         SOC_REG_FLAG_RO,
  11092         SOC_REG_FLAG_COUNTER_FEILDS,
  11093         4,
  11094         soc_BRDC_CCH_CCP_0_DSCRD_CNTr_fields,
  11095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11097         -1,
  11098         -1,
  11099     },
  11100 #endif /* chips */
  11101 
  11102 #if defined(BCM_88790_A0)
  11103     { /* SOC_REG_INT_BRDC_CCH_CCP_0_ILLEGAL_CELLS_DATAr */
  11104         soc_block_list[108],
  11105         soc_genreg,
  11106         1,
  11107         0,
  11108         0x103,
  11109         SOC_REG_FLAG_RO,
  11110         0,
  11111         4,
  11112         soc_BRDC_CCH_CCP_0_ILLEGAL_CELLS_DATAr_fields,
  11113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11114         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  11115         -1,
  11116         -1,
  11117     },
  11118 #endif /* chips */
  11119 
  11120 #if defined(BCM_88790_A0)
  11121     { /* SOC_REG_INT_BRDC_CCH_CCP_0_PROGRAMMABLE_CELLS_COUNTERr */
  11122         soc_block_list[108],
  11123         soc_genreg,
  11124         1,
  11125         0,
  11126         0x10a,
  11127         SOC_REG_FLAG_RO,
  11128         SOC_REG_FLAG_COUNTER_FEILDS,
  11129         2,
  11130         soc_BRDC_CCH_CCP_0_PROGRAMMABLE_CELLS_COUNTERr_fields,
  11131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11132         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11133         -1,
  11134         -1,
  11135     },
  11136 #endif /* chips */
  11137 
  11138 #if defined(BCM_88790_A0)
  11139     { /* SOC_REG_INT_BRDC_CCH_CCP_1_DSCRD_CNTr */
  11140         soc_block_list[108],
  11141         soc_genreg,
  11142         1,
  11143         0,
  11144         0x107,
  11145         SOC_REG_FLAG_RO,
  11146         SOC_REG_FLAG_COUNTER_FEILDS,
  11147         4,
  11148         soc_BRDC_CCH_CCP_1_DSCRD_CNTr_fields,
  11149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11150         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11151         -1,
  11152         -1,
  11153     },
  11154 #endif /* chips */
  11155 
  11156 #if defined(BCM_88790_A0)
  11157     { /* SOC_REG_INT_BRDC_CCH_CCP_1_ILLEGAL_CELLS_DATAr */
  11158         soc_block_list[108],
  11159         soc_genreg,
  11160         1,
  11161         0,
  11162         0x105,
  11163         SOC_REG_FLAG_RO,
  11164         0,
  11165         4,
  11166         soc_BRDC_CCH_CCP_1_ILLEGAL_CELLS_DATAr_fields,
  11167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11168         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  11169         -1,
  11170         -1,
  11171     },
  11172 #endif /* chips */
  11173 
  11174 #if defined(BCM_88790_A0)
  11175     { /* SOC_REG_INT_BRDC_CCH_CCP_1_PROGRAMMABLE_CELLS_COUNTERr */
  11176         soc_block_list[108],
  11177         soc_genreg,
  11178         1,
  11179         0,
  11180         0x10b,
  11181         SOC_REG_FLAG_RO,
  11182         SOC_REG_FLAG_COUNTER_FEILDS,
  11183         2,
  11184         soc_BRDC_CCH_CCP_1_PROGRAMMABLE_CELLS_COUNTERr_fields,
  11185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11186         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11187         -1,
  11188         -1,
  11189     },
  11190 #endif /* chips */
  11191 
  11192 #if defined(BCM_88790_A0)
  11193     { /* SOC_REG_INT_BRDC_CCH_CCP_FIFOS_WATER_MARKr */
  11194         soc_block_list[108],
  11195         soc_genreg,
  11196         1,
  11197         0,
  11198         0x108,
  11199         SOC_REG_FLAG_RO,
  11200         0,
  11201         4,
  11202         soc_BRDC_CCH_CCP_FIFOS_WATER_MARKr_fields,
  11203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11204         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11205         -1,
  11206         -1,
  11207     },
  11208 #endif /* chips */
  11209 
  11210 #if defined(BCM_88790_A0)
  11211     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINKS_EVENTSr */
  11212         soc_block_list[108],
  11213         soc_genreg,
  11214         1,
  11215         0,
  11216         0x10c,
  11217         SOC_REG_FLAG_RO,
  11218         0,
  11219         1,
  11220         soc_BRDC_CCH_CONNECTIVITY_LINKS_EVENTSr_fields,
  11221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11222         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  11223         -1,
  11224         -1,
  11225     },
  11226 #endif /* chips */
  11227 
  11228 #if defined(BCM_88790_A0)
  11229     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_0r */
  11230         soc_block_list[108],
  11231         soc_genreg,
  11232         1,
  11233         0,
  11234         0x10d,
  11235         SOC_REG_FLAG_RO,
  11236         0,
  11237         1,
  11238         soc_BRDC_CCH_CONNECTIVITY_LINK_0r_fields,
  11239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11240         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11241         -1,
  11242         -1,
  11243     },
  11244 #endif /* chips */
  11245 
  11246 #if defined(BCM_88790_A0)
  11247     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_1r */
  11248         soc_block_list[108],
  11249         soc_genreg,
  11250         1,
  11251         0,
  11252         0x10e,
  11253         SOC_REG_FLAG_RO,
  11254         0,
  11255         1,
  11256         soc_BRDC_CCH_CONNECTIVITY_LINK_1r_fields,
  11257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11258         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11259         -1,
  11260         -1,
  11261     },
  11262 #endif /* chips */
  11263 
  11264 #if defined(BCM_88790_A0)
  11265     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_2r */
  11266         soc_block_list[108],
  11267         soc_genreg,
  11268         1,
  11269         0,
  11270         0x10f,
  11271         SOC_REG_FLAG_RO,
  11272         0,
  11273         1,
  11274         soc_BRDC_CCH_CONNECTIVITY_LINK_2r_fields,
  11275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11276         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11277         -1,
  11278         -1,
  11279     },
  11280 #endif /* chips */
  11281 
  11282 #if defined(BCM_88790_A0)
  11283     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_3r */
  11284         soc_block_list[108],
  11285         soc_genreg,
  11286         1,
  11287         0,
  11288         0x110,
  11289         SOC_REG_FLAG_RO,
  11290         0,
  11291         1,
  11292         soc_BRDC_CCH_CONNECTIVITY_LINK_3r_fields,
  11293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11294         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11295         -1,
  11296         -1,
  11297     },
  11298 #endif /* chips */
  11299 
  11300 #if defined(BCM_88790_A0)
  11301     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_4r */
  11302         soc_block_list[108],
  11303         soc_genreg,
  11304         1,
  11305         0,
  11306         0x111,
  11307         SOC_REG_FLAG_RO,
  11308         0,
  11309         1,
  11310         soc_BRDC_CCH_CONNECTIVITY_LINK_4r_fields,
  11311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11312         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11313         -1,
  11314         -1,
  11315     },
  11316 #endif /* chips */
  11317 
  11318 #if defined(BCM_88790_A0)
  11319     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_5r */
  11320         soc_block_list[108],
  11321         soc_genreg,
  11322         1,
  11323         0,
  11324         0x112,
  11325         SOC_REG_FLAG_RO,
  11326         0,
  11327         1,
  11328         soc_BRDC_CCH_CONNECTIVITY_LINK_5r_fields,
  11329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11330         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11331         -1,
  11332         -1,
  11333     },
  11334 #endif /* chips */
  11335 
  11336 #if defined(BCM_88790_A0)
  11337     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_6r */
  11338         soc_block_list[108],
  11339         soc_genreg,
  11340         1,
  11341         0,
  11342         0x113,
  11343         SOC_REG_FLAG_RO,
  11344         0,
  11345         1,
  11346         soc_BRDC_CCH_CONNECTIVITY_LINK_6r_fields,
  11347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11348         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11349         -1,
  11350         -1,
  11351     },
  11352 #endif /* chips */
  11353 
  11354 #if defined(BCM_88790_A0)
  11355     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_7r */
  11356         soc_block_list[108],
  11357         soc_genreg,
  11358         1,
  11359         0,
  11360         0x114,
  11361         SOC_REG_FLAG_RO,
  11362         0,
  11363         1,
  11364         soc_BRDC_CCH_CONNECTIVITY_LINK_7r_fields,
  11365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11366         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11367         -1,
  11368         -1,
  11369     },
  11370 #endif /* chips */
  11371 
  11372 #if defined(BCM_88790_A0)
  11373     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_8r */
  11374         soc_block_list[108],
  11375         soc_genreg,
  11376         1,
  11377         0,
  11378         0x115,
  11379         SOC_REG_FLAG_RO,
  11380         0,
  11381         1,
  11382         soc_BRDC_CCH_CONNECTIVITY_LINK_8r_fields,
  11383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11384         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11385         -1,
  11386         -1,
  11387     },
  11388 #endif /* chips */
  11389 
  11390 #if defined(BCM_88790_A0)
  11391     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_9r */
  11392         soc_block_list[108],
  11393         soc_genreg,
  11394         1,
  11395         0,
  11396         0x116,
  11397         SOC_REG_FLAG_RO,
  11398         0,
  11399         1,
  11400         soc_BRDC_CCH_CONNECTIVITY_LINK_9r_fields,
  11401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11402         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11403         -1,
  11404         -1,
  11405     },
  11406 #endif /* chips */
  11407 
  11408 #if defined(BCM_88790_A0)
  11409     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_10r */
  11410         soc_block_list[108],
  11411         soc_genreg,
  11412         1,
  11413         0,
  11414         0x117,
  11415         SOC_REG_FLAG_RO,
  11416         0,
  11417         1,
  11418         soc_BRDC_CCH_CONNECTIVITY_LINK_10r_fields,
  11419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11420         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11421         -1,
  11422         -1,
  11423     },
  11424 #endif /* chips */
  11425 
  11426 #if defined(BCM_88790_A0)
  11427     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_11r */
  11428         soc_block_list[108],
  11429         soc_genreg,
  11430         1,
  11431         0,
  11432         0x118,
  11433         SOC_REG_FLAG_RO,
  11434         0,
  11435         1,
  11436         soc_BRDC_CCH_CONNECTIVITY_LINK_11r_fields,
  11437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11438         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11439         -1,
  11440         -1,
  11441     },
  11442 #endif /* chips */
  11443 
  11444 #if defined(BCM_88790_A0)
  11445     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_12r */
  11446         soc_block_list[108],
  11447         soc_genreg,
  11448         1,
  11449         0,
  11450         0x119,
  11451         SOC_REG_FLAG_RO,
  11452         0,
  11453         1,
  11454         soc_BRDC_CCH_CONNECTIVITY_LINK_12r_fields,
  11455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11456         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11457         -1,
  11458         -1,
  11459     },
  11460 #endif /* chips */
  11461 
  11462 #if defined(BCM_88790_A0)
  11463     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_13r */
  11464         soc_block_list[108],
  11465         soc_genreg,
  11466         1,
  11467         0,
  11468         0x11a,
  11469         SOC_REG_FLAG_RO,
  11470         0,
  11471         1,
  11472         soc_BRDC_CCH_CONNECTIVITY_LINK_13r_fields,
  11473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11474         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11475         -1,
  11476         -1,
  11477     },
  11478 #endif /* chips */
  11479 
  11480 #if defined(BCM_88790_A0)
  11481     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_14r */
  11482         soc_block_list[108],
  11483         soc_genreg,
  11484         1,
  11485         0,
  11486         0x11b,
  11487         SOC_REG_FLAG_RO,
  11488         0,
  11489         1,
  11490         soc_BRDC_CCH_CONNECTIVITY_LINK_14r_fields,
  11491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11492         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11493         -1,
  11494         -1,
  11495     },
  11496 #endif /* chips */
  11497 
  11498 #if defined(BCM_88790_A0)
  11499     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_15r */
  11500         soc_block_list[108],
  11501         soc_genreg,
  11502         1,
  11503         0,
  11504         0x11c,
  11505         SOC_REG_FLAG_RO,
  11506         0,
  11507         1,
  11508         soc_BRDC_CCH_CONNECTIVITY_LINK_15r_fields,
  11509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11510         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11511         -1,
  11512         -1,
  11513     },
  11514 #endif /* chips */
  11515 
  11516 #if defined(BCM_88790_A0)
  11517     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_16r */
  11518         soc_block_list[108],
  11519         soc_genreg,
  11520         1,
  11521         0,
  11522         0x11d,
  11523         SOC_REG_FLAG_RO,
  11524         0,
  11525         1,
  11526         soc_BRDC_CCH_CONNECTIVITY_LINK_16r_fields,
  11527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11528         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11529         -1,
  11530         -1,
  11531     },
  11532 #endif /* chips */
  11533 
  11534 #if defined(BCM_88790_A0)
  11535     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_17r */
  11536         soc_block_list[108],
  11537         soc_genreg,
  11538         1,
  11539         0,
  11540         0x11e,
  11541         SOC_REG_FLAG_RO,
  11542         0,
  11543         1,
  11544         soc_BRDC_CCH_CONNECTIVITY_LINK_17r_fields,
  11545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11546         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11547         -1,
  11548         -1,
  11549     },
  11550 #endif /* chips */
  11551 
  11552 #if defined(BCM_88790_A0)
  11553     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_18r */
  11554         soc_block_list[108],
  11555         soc_genreg,
  11556         1,
  11557         0,
  11558         0x11f,
  11559         SOC_REG_FLAG_RO,
  11560         0,
  11561         1,
  11562         soc_BRDC_CCH_CONNECTIVITY_LINK_18r_fields,
  11563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11564         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11565         -1,
  11566         -1,
  11567     },
  11568 #endif /* chips */
  11569 
  11570 #if defined(BCM_88790_A0)
  11571     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_19r */
  11572         soc_block_list[108],
  11573         soc_genreg,
  11574         1,
  11575         0,
  11576         0x120,
  11577         SOC_REG_FLAG_RO,
  11578         0,
  11579         1,
  11580         soc_BRDC_CCH_CONNECTIVITY_LINK_19r_fields,
  11581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11582         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11583         -1,
  11584         -1,
  11585     },
  11586 #endif /* chips */
  11587 
  11588 #if defined(BCM_88790_A0)
  11589     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_20r */
  11590         soc_block_list[108],
  11591         soc_genreg,
  11592         1,
  11593         0,
  11594         0x121,
  11595         SOC_REG_FLAG_RO,
  11596         0,
  11597         1,
  11598         soc_BRDC_CCH_CONNECTIVITY_LINK_20r_fields,
  11599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11600         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11601         -1,
  11602         -1,
  11603     },
  11604 #endif /* chips */
  11605 
  11606 #if defined(BCM_88790_A0)
  11607     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_21r */
  11608         soc_block_list[108],
  11609         soc_genreg,
  11610         1,
  11611         0,
  11612         0x122,
  11613         SOC_REG_FLAG_RO,
  11614         0,
  11615         1,
  11616         soc_BRDC_CCH_CONNECTIVITY_LINK_21r_fields,
  11617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11618         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11619         -1,
  11620         -1,
  11621     },
  11622 #endif /* chips */
  11623 
  11624 #if defined(BCM_88790_A0)
  11625     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_22r */
  11626         soc_block_list[108],
  11627         soc_genreg,
  11628         1,
  11629         0,
  11630         0x123,
  11631         SOC_REG_FLAG_RO,
  11632         0,
  11633         1,
  11634         soc_BRDC_CCH_CONNECTIVITY_LINK_22r_fields,
  11635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11636         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11637         -1,
  11638         -1,
  11639     },
  11640 #endif /* chips */
  11641 
  11642 #if defined(BCM_88790_A0)
  11643     { /* SOC_REG_INT_BRDC_CCH_CONNECTIVITY_LINK_23r */
  11644         soc_block_list[108],
  11645         soc_genreg,
  11646         1,
  11647         0,
  11648         0x124,
  11649         SOC_REG_FLAG_RO,
  11650         0,
  11651         1,
  11652         soc_BRDC_CCH_CONNECTIVITY_LINK_23r_fields,
  11653         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11654         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11655         -1,
  11656         -1,
  11657     },
  11658 #endif /* chips */
  11659 
  11660 #if defined(BCM_88790_A0)
  11661     { /* SOC_REG_INT_BRDC_CCH_CREDIT_CELLS_CNTr */
  11662         soc_block_list[108],
  11663         soc_genreg,
  11664         1,
  11665         0,
  11666         0x126,
  11667         SOC_REG_FLAG_RO,
  11668         SOC_REG_FLAG_COUNTER_FEILDS,
  11669         2,
  11670         soc_BRDC_CCH_CREDIT_CELLS_CNTr_fields,
  11671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11672         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11673         -1,
  11674         -1,
  11675     },
  11676 #endif /* chips */
  11677 
  11678 #if defined(BCM_88790_A0)
  11679     { /* SOC_REG_INT_BRDC_CCH_CRP_FIFO_WATER_MARKr */
  11680         soc_block_list[108],
  11681         soc_genreg,
  11682         1,
  11683         0,
  11684         0x162,
  11685         SOC_REG_FLAG_RO,
  11686         0,
  11687         2,
  11688         soc_BRDC_CCH_CRP_FIFO_WATER_MARKr_fields,
  11689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11690         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  11691         -1,
  11692         -1,
  11693     },
  11694 #endif /* chips */
  11695 
  11696 #if defined(BCM_88790_A0)
  11697     { /* SOC_REG_INT_BRDC_CCH_CRP_UNREACHABLE_CELL_DATAr */
  11698         soc_block_list[108],
  11699         soc_genreg,
  11700         1,
  11701         0,
  11702         0x147,
  11703         SOC_REG_FLAG_RO,
  11704         0,
  11705         4,
  11706         soc_BRDC_CCH_CRP_UNREACHABLE_CELL_DATAr_fields,
  11707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11708         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  11709         -1,
  11710         -1,
  11711     },
  11712 #endif /* chips */
  11713 
  11714 #if defined(BCM_88790_A0)
  11715     { /* SOC_REG_INT_BRDC_CCH_DEBUG_CONFIGURATIONSr */
  11716         soc_block_list[108],
  11717         soc_genreg,
  11718         1,
  11719         0,
  11720         0x101,
  11721         0,
  11722         0,
  11723         6,
  11724         soc_BRDC_CCH_DEBUG_CONFIGURATIONSr_fields,
  11725         SOC_RESET_VAL_DEC(0x00000c80, 0x00000000)
  11726         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  11727         -1,
  11728         -1,
  11729     },
  11730 #endif /* chips */
  11731 
  11732 #if defined(BCM_88790_A0)
  11733     { /* SOC_REG_INT_BRDC_CCH_ECC_1B_ERR_CNTr */
  11734         soc_block_list[108],
  11735         soc_genreg,
  11736         1,
  11737         0,
  11738         0x94,
  11739         SOC_REG_FLAG_64_BITS |
  11740                           SOC_REG_FLAG_RO,
  11741         SOC_REG_FLAG_COUNTER_FEILDS,
  11742         4,
  11743         soc_BRDC_CCH_ECC_1B_ERR_CNTr_fields,
  11744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11745         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  11746         -1,
  11747         -1,
  11748     },
  11749 #endif /* chips */
  11750 
  11751 #if defined(BCM_88790_A0)
  11752     { /* SOC_REG_INT_BRDC_CCH_ECC_2B_ERR_CNTr */
  11753         soc_block_list[108],
  11754         soc_genreg,
  11755         1,
  11756         0,
  11757         0x96,
  11758         SOC_REG_FLAG_64_BITS |
  11759                           SOC_REG_FLAG_RO,
  11760         SOC_REG_FLAG_COUNTER_FEILDS,
  11761         4,
  11762         soc_BRDC_CCH_ECC_2B_ERR_CNTr_fields,
  11763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11764         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  11765         -1,
  11766         -1,
  11767     },
  11768 #endif /* chips */
  11769 
  11770 #if defined(BCM_88790_A0)
  11771     { /* SOC_REG_INT_BRDC_CCH_ECC_ERR_1B_INITIATEr */
  11772         soc_block_list[108],
  11773         soc_genreg,
  11774         1,
  11775         0,
  11776         0xa4,
  11777         0,
  11778         0,
  11779         6,
  11780         soc_BRDC_CCH_ECC_ERR_1B_INITIATEr_fields,
  11781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11782         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11783         -1,
  11784         -1,
  11785     },
  11786 #endif /* chips */
  11787 
  11788 #if defined(BCM_88790_A0)
  11789     { /* SOC_REG_INT_BRDC_CCH_ECC_ERR_1B_MONITOR_MEM_MASKr */
  11790         soc_block_list[108],
  11791         soc_genreg,
  11792         1,
  11793         0,
  11794         0x9a,
  11795         0,
  11796         0,
  11797         6,
  11798         soc_BRDC_CCH_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  11799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11800         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11801         -1,
  11802         -1,
  11803     },
  11804 #endif /* chips */
  11805 
  11806 #if defined(BCM_88790_A0)
  11807     { /* SOC_REG_INT_BRDC_CCH_ECC_ERR_2B_INITIATEr */
  11808         soc_block_list[108],
  11809         soc_genreg,
  11810         1,
  11811         0,
  11812         0xa6,
  11813         0,
  11814         0,
  11815         6,
  11816         soc_BRDC_CCH_ECC_ERR_2B_INITIATEr_fields,
  11817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11818         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11819         -1,
  11820         -1,
  11821     },
  11822 #endif /* chips */
  11823 
  11824 #if defined(BCM_88790_A0)
  11825     { /* SOC_REG_INT_BRDC_CCH_ECC_ERR_2B_MONITOR_MEM_MASKr */
  11826         soc_block_list[108],
  11827         soc_genreg,
  11828         1,
  11829         0,
  11830         0x9c,
  11831         0,
  11832         0,
  11833         6,
  11834         soc_BRDC_CCH_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  11835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11836         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11837         -1,
  11838         -1,
  11839     },
  11840 #endif /* chips */
  11841 
  11842 #if defined(BCM_88790_A0)
  11843     { /* SOC_REG_INT_BRDC_CCH_ECC_INTERRUPT_REGISTERr */
  11844         soc_block_list[108],
  11845         soc_genreg,
  11846         1,
  11847         0,
  11848         0x7,
  11849         SOC_REG_FLAG_INTERRUPT |
  11850                           SOC_REG_FLAG_SIGNAL,
  11851         0,
  11852         3,
  11853         soc_BRDC_CCH_ECC_INTERRUPT_REGISTERr_fields,
  11854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11855         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11856         -1,
  11857         -1,
  11858     },
  11859 #endif /* chips */
  11860 
  11861 #if defined(BCM_88790_A0)
  11862     { /* SOC_REG_INT_BRDC_CCH_ECC_INTERRUPT_REGISTER_MASKr */
  11863         soc_block_list[108],
  11864         soc_genreg,
  11865         1,
  11866         0,
  11867         0x17,
  11868         0,
  11869         0,
  11870         3,
  11871         soc_BRDC_CCH_ECC_INTERRUPT_REGISTER_MASKr_fields,
  11872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11873         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11874         -1,
  11875         -1,
  11876     },
  11877 #endif /* chips */
  11878 
  11879 #if defined(BCM_88790_A0)
  11880     { /* SOC_REG_INT_BRDC_CCH_ECC_INTERRUPT_REGISTER_TESTr */
  11881         soc_block_list[108],
  11882         soc_genreg,
  11883         1,
  11884         0,
  11885         0x1f,
  11886         0,
  11887         0,
  11888         1,
  11889         soc_BRDC_CCH_ECC_INTERRUPT_REGISTER_TESTr_fields,
  11890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11891         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  11892         -1,
  11893         -1,
  11894     },
  11895 #endif /* chips */
  11896 
  11897 #if defined(BCM_88790_A0)
  11898     { /* SOC_REG_INT_BRDC_CCH_ERROR_INITIATION_DATAr */
  11899         soc_block_list[108],
  11900         soc_genreg,
  11901         1,
  11902         0,
  11903         0xa3,
  11904         0,
  11905         0,
  11906         1,
  11907         soc_BRDC_CCH_ERROR_INITIATION_DATAr_fields,
  11908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11909         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  11910         -1,
  11911         -1,
  11912     },
  11913 #endif /* chips */
  11914 
  11915 #if defined(BCM_88790_A0)
  11916     { /* SOC_REG_INT_BRDC_CCH_FE_GLOBAL_GENERAL_CFG_1r */
  11917         soc_block_list[108],
  11918         soc_genreg,
  11919         1,
  11920         0,
  11921         0xf4,
  11922         0,
  11923         0,
  11924         4,
  11925         soc_BRDC_CCH_FE_GLOBAL_GENERAL_CFG_1r_fields,
  11926         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  11927         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  11928         -1,
  11929         -1,
  11930     },
  11931 #endif /* chips */
  11932 
  11933 #if defined(BCM_88790_A0)
  11934     { /* SOC_REG_INT_BRDC_CCH_FILTERED_CELLS_CONFIGURATIONSr */
  11935         soc_block_list[108],
  11936         soc_genreg,
  11937         1,
  11938         0,
  11939         0x164,
  11940         0,
  11941         0,
  11942         2,
  11943         soc_BRDC_CCH_FILTERED_CELLS_CONFIGURATIONSr_fields,
  11944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11945         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  11946         -1,
  11947         -1,
  11948     },
  11949 #endif /* chips */
  11950 
  11951 #if defined(BCM_88790_A0)
  11952     { /* SOC_REG_INT_BRDC_CCH_FLOW_STATUS_CELLS_CNTr */
  11953         soc_block_list[108],
  11954         soc_genreg,
  11955         1,
  11956         0,
  11957         0x125,
  11958         SOC_REG_FLAG_RO,
  11959         SOC_REG_FLAG_COUNTER_FEILDS,
  11960         2,
  11961         soc_BRDC_CCH_FLOW_STATUS_CELLS_CNTr_fields,
  11962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  11964         -1,
  11965         -1,
  11966     },
  11967 #endif /* chips */
  11968 
  11969 #if defined(BCM_88790_A0)
  11970     { /* SOC_REG_INT_BRDC_CCH_GLOBAL_MEM_OPTIONSr */
  11971         soc_block_list[108],
  11972         soc_genreg,
  11973         1,
  11974         0,
  11975         0xc2,
  11976         0,
  11977         0,
  11978         6,
  11979         soc_BRDC_CCH_GLOBAL_MEM_OPTIONSr_fields,
  11980         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  11981         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  11982         -1,
  11983         -1,
  11984     },
  11985 #endif /* chips */
  11986 
  11987 #if defined(BCM_88790_A0)
  11988     { /* SOC_REG_INT_BRDC_CCH_GTIMER_CONFIGURATIONr */
  11989         soc_block_list[108],
  11990         soc_genreg,
  11991         1,
  11992         0,
  11993         0x89,
  11994         0,
  11995         0,
  11996         3,
  11997         soc_BRDC_CCH_GTIMER_CONFIGURATIONr_fields,
  11998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  11999         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  12000         -1,
  12001         -1,
  12002     },
  12003 #endif /* chips */
  12004 
  12005 #if defined(BCM_88790_A0)
  12006     { /* SOC_REG_INT_BRDC_CCH_GTIMER_CYCLEr */
  12007         soc_block_list[108],
  12008         soc_genreg,
  12009         1,
  12010         0,
  12011         0x88,
  12012         0,
  12013         0,
  12014         1,
  12015         soc_BRDC_CCH_GTIMER_CYCLEr_fields,
  12016         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  12017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12018         -1,
  12019         -1,
  12020     },
  12021 #endif /* chips */
  12022 
  12023 #if defined(BCM_88790_A0)
  12024     { /* SOC_REG_INT_BRDC_CCH_INTERRUPT_MASK_REGISTERr */
  12025         soc_block_list[108],
  12026         soc_genreg,
  12027         1,
  12028         0,
  12029         0x10,
  12030         0,
  12031         0,
  12032         12,
  12033         soc_BRDC_CCH_INTERRUPT_MASK_REGISTERr_fields,
  12034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12035         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  12036         -1,
  12037         -1,
  12038     },
  12039 #endif /* chips */
  12040 
  12041 #if defined(BCM_88790_A0)
  12042     { /* SOC_REG_INT_BRDC_CCH_INTERRUPT_REGISTERr */
  12043         soc_block_list[108],
  12044         soc_genreg,
  12045         1,
  12046         0,
  12047         0,
  12048         SOC_REG_FLAG_INTERRUPT |
  12049                           SOC_REG_FLAG_SIGNAL,
  12050         0,
  12051         12,
  12052         soc_BRDC_CCH_INTERRUPT_REGISTERr_fields,
  12053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12054         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  12055         -1,
  12056         -1,
  12057     },
  12058 #endif /* chips */
  12059 
  12060 #if defined(BCM_88790_A0)
  12061     { /* SOC_REG_INT_BRDC_CCH_INTERRUPT_REGISTER_TESTr */
  12062         soc_block_list[108],
  12063         soc_genreg,
  12064         1,
  12065         0,
  12066         0x18,
  12067         0,
  12068         0,
  12069         1,
  12070         soc_BRDC_CCH_INTERRUPT_REGISTER_TESTr_fields,
  12071         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12072         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  12073         -1,
  12074         -1,
  12075     },
  12076 #endif /* chips */
  12077 
  12078 #if defined(BCM_88790_A0)
  12079     { /* SOC_REG_INT_BRDC_CCH_PAR_ERR_INITIATEr */
  12080         soc_block_list[108],
  12081         soc_genreg,
  12082         1,
  12083         0,
  12084         0xaa,
  12085         0,
  12086         0,
  12087         1,
  12088         soc_BRDC_CCH_PAR_ERR_INITIATEr_fields,
  12089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12090         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12091         -1,
  12092         -1,
  12093     },
  12094 #endif /* chips */
  12095 
  12096 #if defined(BCM_88790_A0)
  12097     { /* SOC_REG_INT_BRDC_CCH_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTERr */
  12098         soc_block_list[108],
  12099         soc_genreg,
  12100         1,
  12101         0,
  12102         0x109,
  12103         0,
  12104         0,
  12105         8,
  12106         soc_BRDC_CCH_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTERr_fields,
  12107         SOC_RESET_VAL_DEC(0x00030180, 0x00000000)
  12108         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  12109         -1,
  12110         -1,
  12111     },
  12112 #endif /* chips */
  12113 
  12114 #if defined(BCM_88790_A0)
  12115     { /* SOC_REG_INT_BRDC_CCH_REACHABILITY_CELLS_CNTr */
  12116         soc_block_list[108],
  12117         soc_genreg,
  12118         1,
  12119         0,
  12120         0x127,
  12121         SOC_REG_FLAG_RO,
  12122         SOC_REG_FLAG_COUNTER_FEILDS,
  12123         2,
  12124         soc_BRDC_CCH_REACHABILITY_CELLS_CNTr_fields,
  12125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12127         -1,
  12128         -1,
  12129     },
  12130 #endif /* chips */
  12131 
  12132 #if defined(BCM_88790_A0)
  12133     { /* SOC_REG_INT_BRDC_CCH_RESERVED_MIRROR_ADDRr */
  12134         soc_block_list[108],
  12135         soc_genreg,
  12136         1,
  12137         0,
  12138         0x85,
  12139         0,
  12140         0,
  12141         2,
  12142         soc_BRDC_CCH_RESERVED_MIRROR_ADDRr_fields,
  12143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12144         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  12145         -1,
  12146         -1,
  12147     },
  12148 #endif /* chips */
  12149 
  12150 #if defined(BCM_88790_A0)
  12151     { /* SOC_REG_INT_BRDC_CCH_RESERVED_MTCDr */
  12152         soc_block_list[108],
  12153         soc_genreg,
  12154         1,
  12155         0,
  12156         0xae,
  12157         0,
  12158         0,
  12159         6,
  12160         soc_BRDC_CCH_RESERVED_MTCDr_fields,
  12161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12162         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  12163         -1,
  12164         -1,
  12165     },
  12166 #endif /* chips */
  12167 
  12168 #if defined(BCM_88790_A0)
  12169     { /* SOC_REG_INT_BRDC_CCH_RESERVED_MTCPr */
  12170         soc_block_list[108],
  12171         soc_genreg,
  12172         1,
  12173         0,
  12174         0xad,
  12175         SOC_REG_FLAG_64_BITS,
  12176         0,
  12177         17,
  12178         soc_BRDC_CCH_RESERVED_MTCPr_fields,
  12179         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  12180         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  12181         -1,
  12182         -1,
  12183     },
  12184 #endif /* chips */
  12185 
  12186 #if defined(BCM_88790_A0)
  12187     { /* SOC_REG_INT_BRDC_CCH_RESERVED_SPARE_0r */
  12188         soc_block_list[108],
  12189         soc_genreg,
  12190         1,
  12191         0,
  12192         0x90,
  12193         0,
  12194         0,
  12195         1,
  12196         soc_BRDC_CCH_RESERVED_SPARE_0r_fields,
  12197         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  12198         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12199         -1,
  12200         -1,
  12201     },
  12202 #endif /* chips */
  12203 
  12204 #if defined(BCM_88790_A0)
  12205     { /* SOC_REG_INT_BRDC_CCH_RESERVED_SPARE_1r */
  12206         soc_block_list[108],
  12207         soc_genreg,
  12208         1,
  12209         0,
  12210         0x91,
  12211         0,
  12212         0,
  12213         1,
  12214         soc_BRDC_CCH_RESERVED_SPARE_1r_fields,
  12215         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  12216         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12217         -1,
  12218         -1,
  12219     },
  12220 #endif /* chips */
  12221 
  12222 #if defined(BCM_88790_A0)
  12223     { /* SOC_REG_INT_BRDC_CCH_RESERVED_SPARE_2r */
  12224         soc_block_list[108],
  12225         soc_genreg,
  12226         1,
  12227         0,
  12228         0x92,
  12229         0,
  12230         0,
  12231         1,
  12232         soc_BRDC_CCH_RESERVED_SPARE_2r_fields,
  12233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12234         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12235         -1,
  12236         -1,
  12237     },
  12238 #endif /* chips */
  12239 
  12240 #if defined(BCM_88790_A0)
  12241     { /* SOC_REG_INT_BRDC_CCH_RESERVED_SPARE_3r */
  12242         soc_block_list[108],
  12243         soc_genreg,
  12244         1,
  12245         0,
  12246         0x93,
  12247         0,
  12248         0,
  12249         1,
  12250         soc_BRDC_CCH_RESERVED_SPARE_3r_fields,
  12251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12253         -1,
  12254         -1,
  12255     },
  12256 #endif /* chips */
  12257 
  12258 #if defined(BCM_88790_A0)
  12259     { /* SOC_REG_INT_BRDC_CCH_SBUS_BROADCAST_IDr */
  12260         soc_block_list[108],
  12261         soc_genreg,
  12262         1,
  12263         0,
  12264         0x86,
  12265         0,
  12266         0,
  12267         1,
  12268         soc_BRDC_CCH_SBUS_BROADCAST_IDr_fields,
  12269         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  12270         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  12271         -1,
  12272         -1,
  12273     },
  12274 #endif /* chips */
  12275 
  12276 #if defined(BCM_88790_A0)
  12277     { /* SOC_REG_INT_BRDC_CCH_SBUS_LAST_IN_CHAINr */
  12278         soc_block_list[108],
  12279         soc_genreg,
  12280         1,
  12281         0,
  12282         0x87,
  12283         0,
  12284         0,
  12285         1,
  12286         soc_BRDC_CCH_SBUS_LAST_IN_CHAINr_fields,
  12287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12288         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12289         -1,
  12290         -1,
  12291     },
  12292 #endif /* chips */
  12293 
  12294 #if defined(BCM_88790_A0)
  12295     { /* SOC_REG_INT_BRDC_CCH_SELF_ROUTED_CELLS_CNTr */
  12296         soc_block_list[108],
  12297         soc_genreg,
  12298         1,
  12299         0,
  12300         0x128,
  12301         SOC_REG_FLAG_RO,
  12302         SOC_REG_FLAG_COUNTER_FEILDS,
  12303         2,
  12304         soc_BRDC_CCH_SELF_ROUTED_CELLS_CNTr_fields,
  12305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12307         -1,
  12308         -1,
  12309     },
  12310 #endif /* chips */
  12311 
  12312 #if defined(BCM_88790_A0)
  12313     { /* SOC_REG_INT_BRDC_CCH_TOTAL_CELLS_CNTr */
  12314         soc_block_list[108],
  12315         soc_genreg,
  12316         1,
  12317         0,
  12318         0x12c,
  12319         SOC_REG_FLAG_RO,
  12320         SOC_REG_FLAG_COUNTER_FEILDS,
  12321         2,
  12322         soc_BRDC_CCH_TOTAL_CELLS_CNTr_fields,
  12323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12324         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12325         -1,
  12326         -1,
  12327     },
  12328 #endif /* chips */
  12329 
  12330 #if defined(BCM_88790_A0)
  12331     { /* SOC_REG_INT_BRDC_CCH_UNREACHABLE_DESTINATION_CELLS_CNTr */
  12332         soc_block_list[108],
  12333         soc_genreg,
  12334         1,
  12335         0,
  12336         0x12d,
  12337         SOC_REG_FLAG_RO,
  12338         SOC_REG_FLAG_COUNTER_FEILDS,
  12339         2,
  12340         soc_BRDC_CCH_UNREACHABLE_DESTINATION_CELLS_CNTr_fields,
  12341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12343         -1,
  12344         -1,
  12345     },
  12346 #endif /* chips */
  12347 
  12348 #if defined(BCM_88950_A0)
  12349     { /* SOC_REG_INT_BRDC_CCS_ARAD_BMPr */
  12350         soc_block_list[103],
  12351         soc_genreg,
  12352         1,
  12353         0,
  12354         0x14e,
  12355         SOC_REG_FLAG_64_BITS |
  12356                           SOC_REG_FLAG_WO,
  12357         0,
  12358         1,
  12359         soc_BRDC_CCS_ARAD_BMPr_fields,
  12360         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12361         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  12362         -1,
  12363         -1,
  12364     },
  12365 #endif /* chips */
  12366 
  12367 #if defined(BCM_88950_A0)
  12368     { /* SOC_REG_INT_BRDC_CCS_CAPTURED_CELLr */
  12369         soc_block_list[103],
  12370         soc_genreg,
  12371         1,
  12372         0,
  12373         0x13a,
  12374         SOC_REG_FLAG_ABOVE_64_BITS |
  12375                           SOC_REG_FLAG_RO |
  12376                           SOC_REG_FLAG_WO,
  12377         0,
  12378         1,
  12379         soc_BRDC_CCS_CAPTURED_CELLr_fields,
  12380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12381         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12382         -1,
  12383         -1,
  12384     },
  12385 #endif /* chips */
  12386 
  12387 #if defined(BCM_88950_A0)
  12388     { /* SOC_REG_INT_BRDC_CCS_CAPTURED_CELL_VALIDr */
  12389         soc_block_list[103],
  12390         soc_genreg,
  12391         1,
  12392         0,
  12393         0x139,
  12394         SOC_REG_FLAG_RO |
  12395                           SOC_REG_FLAG_WO,
  12396         0,
  12397         1,
  12398         soc_BRDC_CCS_CAPTURED_CELL_VALIDr_fields,
  12399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12400         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12401         -1,
  12402         -1,
  12403     },
  12404 #endif /* chips */
  12405 
  12406 #if defined(BCM_88950_A0)
  12407     { /* SOC_REG_INT_BRDC_CCS_CAPTURE_FIFO_DISCARD_CNTr */
  12408         soc_block_list[103],
  12409         soc_genreg,
  12410         1,
  12411         0,
  12412         0x121,
  12413         SOC_REG_FLAG_RO |
  12414                           SOC_REG_FLAG_WO,
  12415         0,
  12416         2,
  12417         soc_BRDC_CCS_CAPTURE_FIFO_DISCARD_CNTr_fields,
  12418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12420         -1,
  12421         -1,
  12422     },
  12423 #endif /* chips */
  12424 
  12425 #if defined(BCM_88950_A0)
  12426     { /* SOC_REG_INT_BRDC_CCS_CAPTURE_FILTER_CELL_0r */
  12427         soc_block_list[103],
  12428         soc_genreg,
  12429         1,
  12430         0,
  12431         0x129,
  12432         SOC_REG_FLAG_ABOVE_64_BITS |
  12433                           SOC_REG_FLAG_WO,
  12434         0,
  12435         1,
  12436         soc_BRDC_CCS_CAPTURE_FILTER_CELL_0r_fields,
  12437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12438         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12439         -1,
  12440         -1,
  12441     },
  12442 #endif /* chips */
  12443 
  12444 #if defined(BCM_88950_A0)
  12445     { /* SOC_REG_INT_BRDC_CCS_CAPTURE_FILTER_CELL_1r */
  12446         soc_block_list[103],
  12447         soc_genreg,
  12448         1,
  12449         0,
  12450         0x131,
  12451         SOC_REG_FLAG_ABOVE_64_BITS |
  12452                           SOC_REG_FLAG_WO,
  12453         0,
  12454         1,
  12455         soc_BRDC_CCS_CAPTURE_FILTER_CELL_1r_fields,
  12456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12457         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12458         -1,
  12459         -1,
  12460     },
  12461 #endif /* chips */
  12462 
  12463 #if defined(BCM_88950_A0)
  12464     { /* SOC_REG_INT_BRDC_CCS_CAPTURE_FILTER_MASK_0r */
  12465         soc_block_list[103],
  12466         soc_genreg,
  12467         1,
  12468         0,
  12469         0x12d,
  12470         SOC_REG_FLAG_ABOVE_64_BITS |
  12471                           SOC_REG_FLAG_WO,
  12472         0,
  12473         1,
  12474         soc_BRDC_CCS_CAPTURE_FILTER_MASK_0r_fields,
  12475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12476         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12477         -1,
  12478         -1,
  12479     },
  12480 #endif /* chips */
  12481 
  12482 #if defined(BCM_88950_A0)
  12483     { /* SOC_REG_INT_BRDC_CCS_CAPTURE_FILTER_MASK_1r */
  12484         soc_block_list[103],
  12485         soc_genreg,
  12486         1,
  12487         0,
  12488         0x135,
  12489         SOC_REG_FLAG_ABOVE_64_BITS |
  12490                           SOC_REG_FLAG_WO,
  12491         0,
  12492         1,
  12493         soc_BRDC_CCS_CAPTURE_FILTER_MASK_1r_fields,
  12494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12496         -1,
  12497         -1,
  12498     },
  12499 #endif /* chips */
  12500 
  12501 #if defined(BCM_88950_A0)
  12502     { /* SOC_REG_INT_BRDC_CCS_CAPTURE_HIT_CNTr */
  12503         soc_block_list[103],
  12504         soc_genreg,
  12505         1,
  12506         0,
  12507         0x122,
  12508         SOC_REG_FLAG_RO |
  12509                           SOC_REG_FLAG_WO,
  12510         0,
  12511         2,
  12512         soc_BRDC_CCS_CAPTURE_HIT_CNTr_fields,
  12513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12514         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12515         -1,
  12516         -1,
  12517     },
  12518 #endif /* chips */
  12519 
  12520 #if defined(BCM_88950_A0)
  12521     { /* SOC_REG_INT_BRDC_CCS_CCS_CONFIGURATIONSr */
  12522         soc_block_list[103],
  12523         soc_genreg,
  12524         1,
  12525         0,
  12526         0x100,
  12527         SOC_REG_FLAG_WO,
  12528         0,
  12529         8,
  12530         soc_BRDC_CCS_CCS_CONFIGURATIONSr_fields,
  12531         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  12532         SOC_RESET_MASK_DEC(0x000001fd, 0x00000000)
  12533         -1,
  12534         -1,
  12535     },
  12536 #endif /* chips */
  12537 
  12538 #if defined(BCM_88950_A0)
  12539     { /* SOC_REG_INT_BRDC_CCS_CDMA_LP_CELLS_DISCARD_CNTr */
  12540         soc_block_list[103],
  12541         soc_genreg,
  12542         1,
  12543         0,
  12544         0x123,
  12545         SOC_REG_FLAG_RO |
  12546                           SOC_REG_FLAG_WO,
  12547         0,
  12548         2,
  12549         soc_BRDC_CCS_CDMA_LP_CELLS_DISCARD_CNTr_fields,
  12550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12552         -1,
  12553         -1,
  12554     },
  12555 #endif /* chips */
  12556 
  12557 #if defined(BCM_88950_A0)
  12558     { /* SOC_REG_INT_BRDC_CCS_CDMB_LP_CELLS_DISCARD_CNTr */
  12559         soc_block_list[103],
  12560         soc_genreg,
  12561         1,
  12562         0,
  12563         0x124,
  12564         SOC_REG_FLAG_RO |
  12565                           SOC_REG_FLAG_WO,
  12566         0,
  12567         2,
  12568         soc_BRDC_CCS_CDMB_LP_CELLS_DISCARD_CNTr_fields,
  12569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12570         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12571         -1,
  12572         -1,
  12573     },
  12574 #endif /* chips */
  12575 
  12576 #if defined(BCM_88950_A0)
  12577     { /* SOC_REG_INT_BRDC_CCS_CDMC_LP_CELLS_DISCARD_CNTr */
  12578         soc_block_list[103],
  12579         soc_genreg,
  12580         1,
  12581         0,
  12582         0x125,
  12583         SOC_REG_FLAG_RO |
  12584                           SOC_REG_FLAG_WO,
  12585         0,
  12586         2,
  12587         soc_BRDC_CCS_CDMC_LP_CELLS_DISCARD_CNTr_fields,
  12588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12589         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12590         -1,
  12591         -1,
  12592     },
  12593 #endif /* chips */
  12594 
  12595 #if defined(BCM_88950_A0)
  12596     { /* SOC_REG_INT_BRDC_CCS_CDMD_LP_CELLS_DISCARD_CNTr */
  12597         soc_block_list[103],
  12598         soc_genreg,
  12599         1,
  12600         0,
  12601         0x126,
  12602         SOC_REG_FLAG_RO |
  12603                           SOC_REG_FLAG_WO,
  12604         0,
  12605         2,
  12606         soc_BRDC_CCS_CDMD_LP_CELLS_DISCARD_CNTr_fields,
  12607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12608         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12609         -1,
  12610         -1,
  12611     },
  12612 #endif /* chips */
  12613 
  12614 #if defined(BCM_88950_A0)
  12615     { /* SOC_REG_INT_BRDC_CCS_CDM_OVERFLOW_FIFO_NUMBERr */
  12616         soc_block_list[103],
  12617         soc_genreg,
  12618         1,
  12619         0,
  12620         0x107,
  12621         SOC_REG_FLAG_64_BITS |
  12622                           SOC_REG_FLAG_RO |
  12623                           SOC_REG_FLAG_WO,
  12624         0,
  12625         8,
  12626         soc_BRDC_CCS_CDM_OVERFLOW_FIFO_NUMBERr_fields,
  12627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12628         SOC_RESET_MASK_DEC(0x3f13f13f, 0x000013f1)
  12629         -1,
  12630         -1,
  12631     },
  12632 #endif /* chips */
  12633 
  12634 #if defined(BCM_88950_A0)
  12635     { /* SOC_REG_INT_BRDC_CCS_CPU_SOURCE_CELL_DATAr */
  12636         soc_block_list[103],
  12637         soc_genreg,
  12638         1,
  12639         0,
  12640         0x109,
  12641         SOC_REG_FLAG_ABOVE_64_BITS |
  12642                           SOC_REG_FLAG_WO,
  12643         0,
  12644         2,
  12645         soc_BRDC_CCS_CPU_SOURCE_CELL_DATAr_fields,
  12646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12647         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  12648         -1,
  12649         -1,
  12650     },
  12651 #endif /* chips */
  12652 
  12653 #if defined(BCM_88950_A0)
  12654     { /* SOC_REG_INT_BRDC_CCS_CPU_SOURCE_CELL_TRIGGERr */
  12655         soc_block_list[103],
  12656         soc_genreg,
  12657         1,
  12658         0,
  12659         0x10d,
  12660         SOC_REG_FLAG_WO,
  12661         0,
  12662         1,
  12663         soc_BRDC_CCS_CPU_SOURCE_CELL_TRIGGERr_fields,
  12664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12665         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12666         -1,
  12667         -1,
  12668     },
  12669 #endif /* chips */
  12670 
  12671 #if defined(BCM_88950_A0)
  12672     { /* SOC_REG_INT_BRDC_CCS_CREDIT_CELLS_CNTr */
  12673         soc_block_list[103],
  12674         soc_genreg,
  12675         1,
  12676         0,
  12677         0x10f,
  12678         SOC_REG_FLAG_RO |
  12679                           SOC_REG_FLAG_WO,
  12680         0,
  12681         2,
  12682         soc_BRDC_CCS_CREDIT_CELLS_CNTr_fields,
  12683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12685         -1,
  12686         -1,
  12687     },
  12688 #endif /* chips */
  12689 
  12690 #if defined(BCM_88950_A0)
  12691     { /* SOC_REG_INT_BRDC_CCS_CRP_FIFO_WATER_MARKr */
  12692         soc_block_list[103],
  12693         soc_genreg,
  12694         1,
  12695         0,
  12696         0x143,
  12697         SOC_REG_FLAG_RO |
  12698                           SOC_REG_FLAG_WO,
  12699         0,
  12700         2,
  12701         soc_BRDC_CCS_CRP_FIFO_WATER_MARKr_fields,
  12702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12703         SOC_RESET_MASK_DEC(0x00003f1f, 0x00000000)
  12704         -1,
  12705         -1,
  12706     },
  12707 #endif /* chips */
  12708 
  12709 #if defined(BCM_88950_A0)
  12710     { /* SOC_REG_INT_BRDC_CCS_CRP_PARITY_ERR_CNTr */
  12711         soc_block_list[103],
  12712         soc_genreg,
  12713         1,
  12714         0,
  12715         0x14d,
  12716         SOC_REG_FLAG_RO |
  12717                           SOC_REG_FLAG_WO,
  12718         0,
  12719         2,
  12720         soc_BRDC_CCS_CRP_PARITY_ERR_CNTr_fields,
  12721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12722         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12723         -1,
  12724         -1,
  12725     },
  12726 #endif /* chips */
  12727 
  12728 #if defined(BCM_88950_A0)
  12729     { /* SOC_REG_INT_BRDC_CCS_CRP_UNREACHABLE_CELL_DATAr */
  12730         soc_block_list[103],
  12731         soc_genreg,
  12732         1,
  12733         0,
  12734         0x11f,
  12735         SOC_REG_FLAG_RO |
  12736                           SOC_REG_FLAG_WO,
  12737         0,
  12738         4,
  12739         soc_BRDC_CCS_CRP_UNREACHABLE_CELL_DATAr_fields,
  12740         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12741         SOC_RESET_MASK_DEC(0x01ff77ff, 0x00000000)
  12742         -1,
  12743         -1,
  12744     },
  12745 #endif /* chips */
  12746 
  12747 #if defined(BCM_88950_A0)
  12748     { /* SOC_REG_INT_BRDC_CCS_CTP_INTERNAL_REACHABILITY_CELLS_CNTr */
  12749         soc_block_list[103],
  12750         soc_genreg,
  12751         1,
  12752         0,
  12753         0x127,
  12754         SOC_REG_FLAG_RO |
  12755                           SOC_REG_FLAG_WO,
  12756         0,
  12757         2,
  12758         soc_BRDC_CCS_CTP_INTERNAL_REACHABILITY_CELLS_CNTr_fields,
  12759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12760         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12761         -1,
  12762         -1,
  12763     },
  12764 #endif /* chips */
  12765 
  12766 #if defined(BCM_88950_A0)
  12767     { /* SOC_REG_INT_BRDC_CCS_DEBUG_CONFIGURATIONSr */
  12768         soc_block_list[103],
  12769         soc_genreg,
  12770         1,
  12771         0,
  12772         0x101,
  12773         SOC_REG_FLAG_WO,
  12774         0,
  12775         9,
  12776         soc_BRDC_CCS_DEBUG_CONFIGURATIONSr_fields,
  12777         SOC_RESET_VAL_DEC(0x00006480, 0x00000000)
  12778         SOC_RESET_MASK_DEC(0x011fffff, 0x00000000)
  12779         -1,
  12780         -1,
  12781     },
  12782 #endif /* chips */
  12783 
  12784 #if defined(BCM_88950_A0)
  12785     { /* SOC_REG_INT_BRDC_CCS_ECC_1B_ERR_CNTr */
  12786         soc_block_list[103],
  12787         soc_genreg,
  12788         1,
  12789         0,
  12790         0x94,
  12791         SOC_REG_FLAG_64_BITS |
  12792                           SOC_REG_FLAG_RO |
  12793                           SOC_REG_FLAG_WO,
  12794         0,
  12795         4,
  12796         soc_BRDC_CCS_ECC_1B_ERR_CNTr_fields,
  12797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12798         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  12799         -1,
  12800         -1,
  12801     },
  12802 #endif /* chips */
  12803 
  12804 #if defined(BCM_88950_A0)
  12805     { /* SOC_REG_INT_BRDC_CCS_ECC_2B_ERR_CNTr */
  12806         soc_block_list[103],
  12807         soc_genreg,
  12808         1,
  12809         0,
  12810         0x96,
  12811         SOC_REG_FLAG_64_BITS |
  12812                           SOC_REG_FLAG_RO |
  12813                           SOC_REG_FLAG_WO,
  12814         0,
  12815         4,
  12816         soc_BRDC_CCS_ECC_2B_ERR_CNTr_fields,
  12817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12818         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  12819         -1,
  12820         -1,
  12821     },
  12822 #endif /* chips */
  12823 
  12824 #if defined(BCM_88950_A0)
  12825     { /* SOC_REG_INT_BRDC_CCS_ECC_ERR_1B_INITIATEr */
  12826         soc_block_list[103],
  12827         soc_genreg,
  12828         1,
  12829         0,
  12830         0xa4,
  12831         SOC_REG_FLAG_WO,
  12832         0,
  12833         6,
  12834         soc_BRDC_CCS_ECC_ERR_1B_INITIATEr_fields,
  12835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12836         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  12837         -1,
  12838         -1,
  12839     },
  12840 #endif /* chips */
  12841 
  12842 #if defined(BCM_88950_A0)
  12843     { /* SOC_REG_INT_BRDC_CCS_ECC_ERR_1B_MONITOR_MEM_MASKr */
  12844         soc_block_list[103],
  12845         soc_genreg,
  12846         1,
  12847         0,
  12848         0x9a,
  12849         SOC_REG_FLAG_WO,
  12850         0,
  12851         6,
  12852         soc_BRDC_CCS_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  12853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12854         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  12855         -1,
  12856         -1,
  12857     },
  12858 #endif /* chips */
  12859 
  12860 #if defined(BCM_88950_A0)
  12861     { /* SOC_REG_INT_BRDC_CCS_ECC_ERR_2B_INITIATEr */
  12862         soc_block_list[103],
  12863         soc_genreg,
  12864         1,
  12865         0,
  12866         0xa6,
  12867         SOC_REG_FLAG_WO,
  12868         0,
  12869         6,
  12870         soc_BRDC_CCS_ECC_ERR_2B_INITIATEr_fields,
  12871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12872         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  12873         -1,
  12874         -1,
  12875     },
  12876 #endif /* chips */
  12877 
  12878 #if defined(BCM_88950_A0)
  12879     { /* SOC_REG_INT_BRDC_CCS_ECC_ERR_2B_MONITOR_MEM_MASKr */
  12880         soc_block_list[103],
  12881         soc_genreg,
  12882         1,
  12883         0,
  12884         0x9c,
  12885         SOC_REG_FLAG_WO,
  12886         0,
  12887         6,
  12888         soc_BRDC_CCS_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  12889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12890         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  12891         -1,
  12892         -1,
  12893     },
  12894 #endif /* chips */
  12895 
  12896 #if defined(BCM_88950_A0)
  12897     { /* SOC_REG_INT_BRDC_CCS_ECC_INTERRUPT_REGISTERr */
  12898         soc_block_list[103],
  12899         soc_genreg,
  12900         1,
  12901         0,
  12902         0x7,
  12903         SOC_REG_FLAG_WO |
  12904                           SOC_REG_FLAG_INTERRUPT,
  12905         0,
  12906         2,
  12907         soc_BRDC_CCS_ECC_INTERRUPT_REGISTERr_fields,
  12908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12909         SOC_RESET_MASK_DEC(0x00000006, 0x00000000)
  12910         -1,
  12911         -1,
  12912     },
  12913 #endif /* chips */
  12914 
  12915 #if defined(BCM_88950_A0)
  12916     { /* SOC_REG_INT_BRDC_CCS_ECC_INTERRUPT_REGISTER_MASKr */
  12917         soc_block_list[103],
  12918         soc_genreg,
  12919         1,
  12920         0,
  12921         0x17,
  12922         SOC_REG_FLAG_WO,
  12923         0,
  12924         3,
  12925         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_MASKr_fields,
  12926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12927         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  12928         -1,
  12929         -1,
  12930     },
  12931 #endif /* chips */
  12932 
  12933 #if defined(BCM_88950_A0)
  12934     { /* SOC_REG_INT_BRDC_CCS_ECC_INTERRUPT_REGISTER_TESTr */
  12935         soc_block_list[103],
  12936         soc_genreg,
  12937         1,
  12938         0,
  12939         0x1f,
  12940         SOC_REG_FLAG_WO,
  12941         0,
  12942         1,
  12943         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_TESTr_fields,
  12944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12946         -1,
  12947         -1,
  12948     },
  12949 #endif /* chips */
  12950 
  12951 #if defined(BCM_88950_A0)
  12952     { /* SOC_REG_INT_BRDC_CCS_ERROR_INITIATION_DATAr */
  12953         soc_block_list[103],
  12954         soc_genreg,
  12955         1,
  12956         0,
  12957         0xa3,
  12958         SOC_REG_FLAG_WO,
  12959         0,
  12960         1,
  12961         soc_BRDC_CCS_ERROR_INITIATION_DATAr_fields,
  12962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12963         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  12964         -1,
  12965         -1,
  12966     },
  12967 #endif /* chips */
  12968 
  12969 #if defined(BCM_88950_A0)
  12970     { /* SOC_REG_INT_BRDC_CCS_FE_13_LINKS_CREDIT_CELLS_CNTr */
  12971         soc_block_list[103],
  12972         soc_genreg,
  12973         1,
  12974         0,
  12975         0x117,
  12976         SOC_REG_FLAG_RO |
  12977                           SOC_REG_FLAG_WO,
  12978         0,
  12979         2,
  12980         soc_BRDC_CCS_FE_13_LINKS_CREDIT_CELLS_CNTr_fields,
  12981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  12982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  12983         -1,
  12984         -1,
  12985     },
  12986 #endif /* chips */
  12987 
  12988 #if defined(BCM_88950_A0)
  12989     { /* SOC_REG_INT_BRDC_CCS_FE_13_LINKS_FLOW_STATUS_CELLS_CNTr */
  12990         soc_block_list[103],
  12991         soc_genreg,
  12992         1,
  12993         0,
  12994         0x116,
  12995         SOC_REG_FLAG_RO |
  12996                           SOC_REG_FLAG_WO,
  12997         0,
  12998         2,
  12999         soc_BRDC_CCS_FE_13_LINKS_FLOW_STATUS_CELLS_CNTr_fields,
  13000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13002         -1,
  13003         -1,
  13004     },
  13005 #endif /* chips */
  13006 
  13007 #if defined(BCM_88950_A0)
  13008     { /* SOC_REG_INT_BRDC_CCS_FE_13_LINKS_REACHABILITY_CELLS_CNTr */
  13009         soc_block_list[103],
  13010         soc_genreg,
  13011         1,
  13012         0,
  13013         0x118,
  13014         SOC_REG_FLAG_RO |
  13015                           SOC_REG_FLAG_WO,
  13016         0,
  13017         2,
  13018         soc_BRDC_CCS_FE_13_LINKS_REACHABILITY_CELLS_CNTr_fields,
  13019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13020         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13021         -1,
  13022         -1,
  13023     },
  13024 #endif /* chips */
  13025 
  13026 #if defined(BCM_88950_A0)
  13027     { /* SOC_REG_INT_BRDC_CCS_FE_13_LINKS_SELF_ROUTED_CELLS_CNTr */
  13028         soc_block_list[103],
  13029         soc_genreg,
  13030         1,
  13031         0,
  13032         0x119,
  13033         SOC_REG_FLAG_RO |
  13034                           SOC_REG_FLAG_WO,
  13035         0,
  13036         2,
  13037         soc_BRDC_CCS_FE_13_LINKS_SELF_ROUTED_CELLS_CNTr_fields,
  13038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13040         -1,
  13041         -1,
  13042     },
  13043 #endif /* chips */
  13044 
  13045 #if defined(BCM_88950_A0)
  13046     { /* SOC_REG_INT_BRDC_CCS_FE_13_LINKS_TOTAL_CELLS_CNTr */
  13047         soc_block_list[103],
  13048         soc_genreg,
  13049         1,
  13050         0,
  13051         0x11d,
  13052         SOC_REG_FLAG_RO |
  13053                           SOC_REG_FLAG_WO,
  13054         0,
  13055         2,
  13056         soc_BRDC_CCS_FE_13_LINKS_TOTAL_CELLS_CNTr_fields,
  13057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13059         -1,
  13060         -1,
  13061     },
  13062 #endif /* chips */
  13063 
  13064 #if defined(BCM_88950_A0)
  13065     { /* SOC_REG_INT_BRDC_CCS_FILTERED_CELLS_CONFIGURATIONSr */
  13066         soc_block_list[103],
  13067         soc_genreg,
  13068         1,
  13069         0,
  13070         0x14c,
  13071         SOC_REG_FLAG_WO,
  13072         0,
  13073         2,
  13074         soc_BRDC_CCS_FILTERED_CELLS_CONFIGURATIONSr_fields,
  13075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13076         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13077         -1,
  13078         -1,
  13079     },
  13080 #endif /* chips */
  13081 
  13082 #if defined(BCM_88950_A0)
  13083     { /* SOC_REG_INT_BRDC_CCS_FLOW_STATUS_CELLS_CNTr */
  13084         soc_block_list[103],
  13085         soc_genreg,
  13086         1,
  13087         0,
  13088         0x10e,
  13089         SOC_REG_FLAG_RO |
  13090                           SOC_REG_FLAG_WO,
  13091         0,
  13092         2,
  13093         soc_BRDC_CCS_FLOW_STATUS_CELLS_CNTr_fields,
  13094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13096         -1,
  13097         -1,
  13098     },
  13099 #endif /* chips */
  13100 
  13101 #if defined(BCM_88950_A0)
  13102     { /* SOC_REG_INT_BRDC_CCS_GLOBAL_GENERAL_CFG_2r */
  13103         soc_block_list[103],
  13104         soc_genreg,
  13105         1,
  13106         0,
  13107         0xc2,
  13108         SOC_REG_FLAG_WO,
  13109         0,
  13110         1,
  13111         soc_BRDC_CCS_GLOBAL_GENERAL_CFG_2r_fields,
  13112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13113         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  13114         -1,
  13115         -1,
  13116     },
  13117 #endif /* chips */
  13118 
  13119 #if defined(BCM_88950_A0)
  13120     { /* SOC_REG_INT_BRDC_CCS_GLOBAL_GENERAL_FE_CFG_1r */
  13121         soc_block_list[103],
  13122         soc_genreg,
  13123         1,
  13124         0,
  13125         0xf4,
  13126         SOC_REG_FLAG_WO,
  13127         0,
  13128         3,
  13129         soc_BRDC_CCS_GLOBAL_GENERAL_FE_CFG_1r_fields,
  13130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13131         SOC_RESET_MASK_DEC(0x000003e2, 0x00000000)
  13132         -1,
  13133         -1,
  13134     },
  13135 #endif /* chips */
  13136 
  13137 #if defined(BCM_88950_A0)
  13138     { /* SOC_REG_INT_BRDC_CCS_GLOBAL_MEM_OPTIONSr */
  13139         soc_block_list[103],
  13140         soc_genreg,
  13141         1,
  13142         0,
  13143         0xc0,
  13144         SOC_REG_FLAG_WO,
  13145         0,
  13146         2,
  13147         soc_BRDC_CCS_GLOBAL_MEM_OPTIONSr_fields,
  13148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13149         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13150         -1,
  13151         -1,
  13152     },
  13153 #endif /* chips */
  13154 
  13155 #if defined(BCM_88950_A0)
  13156     { /* SOC_REG_INT_BRDC_CCS_GTIMER_CONFIGURATIONr */
  13157         soc_block_list[103],
  13158         soc_genreg,
  13159         1,
  13160         0,
  13161         0x88,
  13162         SOC_REG_FLAG_WO,
  13163         0,
  13164         3,
  13165         soc_BRDC_CCS_GTIMER_CONFIGURATIONr_fields,
  13166         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  13167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13168         -1,
  13169         -1,
  13170     },
  13171 #endif /* chips */
  13172 
  13173 #if defined(BCM_88950_A0)
  13174     { /* SOC_REG_INT_BRDC_CCS_GTIMER_TRIGGERr */
  13175         soc_block_list[103],
  13176         soc_genreg,
  13177         1,
  13178         0,
  13179         0x89,
  13180         SOC_REG_FLAG_RO |
  13181                           SOC_REG_FLAG_WO,
  13182         0,
  13183         1,
  13184         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  13185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13186         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13187         -1,
  13188         -1,
  13189     },
  13190 #endif /* chips */
  13191 
  13192 #if defined(BCM_88950_A0)
  13193     { /* SOC_REG_INT_BRDC_CCS_INTERRUPT_MASK_REGISTERr */
  13194         soc_block_list[103],
  13195         soc_genreg,
  13196         1,
  13197         0,
  13198         0x10,
  13199         SOC_REG_FLAG_WO,
  13200         0,
  13201         9,
  13202         soc_BRDC_CCS_INTERRUPT_MASK_REGISTERr_fields,
  13203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13204         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13205         -1,
  13206         -1,
  13207     },
  13208 #endif /* chips */
  13209 
  13210 #if defined(BCM_88950_A0)
  13211     { /* SOC_REG_INT_BRDC_CCS_INTERRUPT_REGISTERr */
  13212         soc_block_list[103],
  13213         soc_genreg,
  13214         1,
  13215         0,
  13216         0,
  13217         SOC_REG_FLAG_WO |
  13218                           SOC_REG_FLAG_INTERRUPT,
  13219         0,
  13220         9,
  13221         soc_BRDC_CCS_INTERRUPT_REGISTERr_fields,
  13222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13223         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  13224         -1,
  13225         -1,
  13226     },
  13227 #endif /* chips */
  13228 
  13229 #if defined(BCM_88950_A0)
  13230     { /* SOC_REG_INT_BRDC_CCS_INTERRUPT_REGISTER_TESTr */
  13231         soc_block_list[103],
  13232         soc_genreg,
  13233         1,
  13234         0,
  13235         0x18,
  13236         SOC_REG_FLAG_WO,
  13237         0,
  13238         1,
  13239         soc_BRDC_CCS_INTERRUPT_REGISTER_TESTr_fields,
  13240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13242         -1,
  13243         -1,
  13244     },
  13245 #endif /* chips */
  13246 
  13247 #if defined(BCM_88950_A0)
  13248     { /* SOC_REG_INT_BRDC_CCS_MID_FIFOS_LP_WATER_MARKr */
  13249         soc_block_list[103],
  13250         soc_genreg,
  13251         1,
  13252         0,
  13253         0x13e,
  13254         SOC_REG_FLAG_64_BITS |
  13255                           SOC_REG_FLAG_RO |
  13256                           SOC_REG_FLAG_WO,
  13257         0,
  13258         8,
  13259         soc_BRDC_CCS_MID_FIFOS_LP_WATER_MARKr_fields,
  13260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13261         SOC_RESET_MASK_DEC(0x3f3f3f3f, 0x3f3f3f3f)
  13262         -1,
  13263         -1,
  13264     },
  13265 #endif /* chips */
  13266 
  13267 #if defined(BCM_88950_A0)
  13268     { /* SOC_REG_INT_BRDC_CCS_PAR_ERR_INITIATEr */
  13269         soc_block_list[103],
  13270         soc_genreg,
  13271         1,
  13272         0,
  13273         0xaa,
  13274         SOC_REG_FLAG_WO,
  13275         0,
  13276         3,
  13277         soc_BRDC_CCS_PAR_ERR_INITIATEr_fields,
  13278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13279         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  13280         -1,
  13281         -1,
  13282     },
  13283 #endif /* chips */
  13284 
  13285 #if defined(BCM_88950_A0)
  13286     { /* SOC_REG_INT_BRDC_CCS_PROGRAMMABLE_MID_FIFOS_WATER_MARKr */
  13287         soc_block_list[103],
  13288         soc_genreg,
  13289         1,
  13290         0,
  13291         0x142,
  13292         SOC_REG_FLAG_RO |
  13293                           SOC_REG_FLAG_WO,
  13294         0,
  13295         4,
  13296         soc_BRDC_CCS_PROGRAMMABLE_MID_FIFOS_WATER_MARKr_fields,
  13297         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13298         SOC_RESET_MASK_DEC(0x3f3f3f3f, 0x00000000)
  13299         -1,
  13300         -1,
  13301     },
  13302 #endif /* chips */
  13303 
  13304 #if defined(BCM_88950_A0)
  13305     { /* SOC_REG_INT_BRDC_CCS_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARKr */
  13306         soc_block_list[103],
  13307         soc_genreg,
  13308         1,
  13309         0,
  13310         0x141,
  13311         SOC_REG_FLAG_WO,
  13312         0,
  13313         4,
  13314         soc_BRDC_CCS_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARKr_fields,
  13315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13316         SOC_RESET_MASK_DEC(0x3f3f3f3f, 0x00000000)
  13317         -1,
  13318         -1,
  13319     },
  13320 #endif /* chips */
  13321 
  13322 #if defined(BCM_88950_A0)
  13323     { /* SOC_REG_INT_BRDC_CCS_REACHABILITY_CELLS_CNTr */
  13324         soc_block_list[103],
  13325         soc_genreg,
  13326         1,
  13327         0,
  13328         0x110,
  13329         SOC_REG_FLAG_RO |
  13330                           SOC_REG_FLAG_WO,
  13331         0,
  13332         2,
  13333         soc_BRDC_CCS_REACHABILITY_CELLS_CNTr_fields,
  13334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13335         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13336         -1,
  13337         -1,
  13338     },
  13339 #endif /* chips */
  13340 
  13341 #if defined(BCM_88950_A0)
  13342     { /* SOC_REG_INT_BRDC_CCS_REG_0102r */
  13343         soc_block_list[103],
  13344         soc_genreg,
  13345         1,
  13346         0,
  13347         0x102,
  13348         SOC_REG_FLAG_ABOVE_64_BITS |
  13349                           SOC_REG_FLAG_WO,
  13350         0,
  13351         1,
  13352         soc_BRDC_CCS_REG_0102r_fields,
  13353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13354         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13355         -1,
  13356         -1,
  13357     },
  13358 #endif /* chips */
  13359 
  13360 #if defined(BCM_88950_A0)
  13361     { /* SOC_REG_INT_BRDC_CCS_REG_0112r */
  13362         soc_block_list[103],
  13363         soc_genreg,
  13364         1,
  13365         0,
  13366         0x112,
  13367         SOC_REG_FLAG_RO |
  13368                           SOC_REG_FLAG_WO,
  13369         0,
  13370         2,
  13371         soc_BRDC_CCS_REG_0112r_fields,
  13372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13373         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13374         -1,
  13375         -1,
  13376     },
  13377 #endif /* chips */
  13378 
  13379 #if defined(BCM_88950_A0)
  13380     { /* SOC_REG_INT_BRDC_CCS_REG_0113r */
  13381         soc_block_list[103],
  13382         soc_genreg,
  13383         1,
  13384         0,
  13385         0x113,
  13386         SOC_REG_FLAG_RO |
  13387                           SOC_REG_FLAG_WO,
  13388         0,
  13389         2,
  13390         soc_BRDC_CCS_REG_0112r_fields,
  13391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13392         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13393         -1,
  13394         -1,
  13395     },
  13396 #endif /* chips */
  13397 
  13398 #if defined(BCM_88950_A0)
  13399     { /* SOC_REG_INT_BRDC_CCS_REG_0114r */
  13400         soc_block_list[103],
  13401         soc_genreg,
  13402         1,
  13403         0,
  13404         0x114,
  13405         SOC_REG_FLAG_RO |
  13406                           SOC_REG_FLAG_WO,
  13407         0,
  13408         2,
  13409         soc_BRDC_CCS_REG_0112r_fields,
  13410         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13411         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13412         -1,
  13413         -1,
  13414     },
  13415 #endif /* chips */
  13416 
  13417 #if defined(BCM_88950_A0)
  13418     { /* SOC_REG_INT_BRDC_CCS_REG_0120r */
  13419         soc_block_list[103],
  13420         soc_genreg,
  13421         1,
  13422         0,
  13423         0x120,
  13424         SOC_REG_FLAG_RO |
  13425                           SOC_REG_FLAG_WO,
  13426         0,
  13427         4,
  13428         soc_BRDC_CCS_REG_0120r_fields,
  13429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13430         SOC_RESET_MASK_DEC(0x87ffffff, 0x00000000)
  13431         -1,
  13432         -1,
  13433     },
  13434 #endif /* chips */
  13435 
  13436 #if defined(BCM_88950_A0)
  13437     { /* SOC_REG_INT_BRDC_CCS_REG_0128r */
  13438         soc_block_list[103],
  13439         soc_genreg,
  13440         1,
  13441         0,
  13442         0x128,
  13443         SOC_REG_FLAG_RO |
  13444                           SOC_REG_FLAG_WO,
  13445         0,
  13446         2,
  13447         soc_BRDC_CCS_REG_0112r_fields,
  13448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13449         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13450         -1,
  13451         -1,
  13452     },
  13453 #endif /* chips */
  13454 
  13455 #if defined(BCM_88950_A0)
  13456     { /* SOC_REG_INT_BRDC_CCS_REG_0140r */
  13457         soc_block_list[103],
  13458         soc_genreg,
  13459         1,
  13460         0,
  13461         0x140,
  13462         SOC_REG_FLAG_RO |
  13463                           SOC_REG_FLAG_WO,
  13464         0,
  13465         4,
  13466         soc_BRDC_CCS_REG_0140r_fields,
  13467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13468         SOC_RESET_MASK_DEC(0x3f3f3f3f, 0x00000000)
  13469         -1,
  13470         -1,
  13471     },
  13472 #endif /* chips */
  13473 
  13474 #if defined(BCM_88950_A0)
  13475     { /* SOC_REG_INT_BRDC_CCS_REG_0144r */
  13476         soc_block_list[103],
  13477         soc_genreg,
  13478         1,
  13479         0,
  13480         0x144,
  13481         SOC_REG_FLAG_ABOVE_64_BITS |
  13482                           SOC_REG_FLAG_WO,
  13483         0,
  13484         1,
  13485         soc_BRDC_CCS_REG_0102r_fields,
  13486         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13487         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  13488         -1,
  13489         -1,
  13490     },
  13491 #endif /* chips */
  13492 
  13493 #if defined(BCM_88950_A0)
  13494     { /* SOC_REG_INT_BRDC_CCS_REG_0149r */
  13495         soc_block_list[103],
  13496         soc_genreg,
  13497         1,
  13498         0,
  13499         0x149,
  13500         SOC_REG_FLAG_WO,
  13501         0,
  13502         4,
  13503         soc_BRDC_CCS_REG_0149r_fields,
  13504         SOC_RESET_VAL_DEC(0x13131316, 0x00000000)
  13505         SOC_RESET_MASK_DEC(0x3f3f3f3f, 0x00000000)
  13506         -1,
  13507         -1,
  13508     },
  13509 #endif /* chips */
  13510 
  13511 #if defined(BCM_88950_A0)
  13512     { /* SOC_REG_INT_BRDC_CCS_REG_011Ar */
  13513         soc_block_list[103],
  13514         soc_genreg,
  13515         1,
  13516         0,
  13517         0x11a,
  13518         SOC_REG_FLAG_RO |
  13519                           SOC_REG_FLAG_WO,
  13520         0,
  13521         2,
  13522         soc_BRDC_CCS_REG_0112r_fields,
  13523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13524         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13525         -1,
  13526         -1,
  13527     },
  13528 #endif /* chips */
  13529 
  13530 #if defined(BCM_88950_A0)
  13531     { /* SOC_REG_INT_BRDC_CCS_REG_011Br */
  13532         soc_block_list[103],
  13533         soc_genreg,
  13534         1,
  13535         0,
  13536         0x11b,
  13537         SOC_REG_FLAG_RO |
  13538                           SOC_REG_FLAG_WO,
  13539         0,
  13540         2,
  13541         soc_BRDC_CCS_REG_0112r_fields,
  13542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13543         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13544         -1,
  13545         -1,
  13546     },
  13547 #endif /* chips */
  13548 
  13549 #if defined(BCM_88950_A0)
  13550     { /* SOC_REG_INT_BRDC_CCS_REG_011Cr */
  13551         soc_block_list[103],
  13552         soc_genreg,
  13553         1,
  13554         0,
  13555         0x11c,
  13556         SOC_REG_FLAG_RO |
  13557                           SOC_REG_FLAG_WO,
  13558         0,
  13559         2,
  13560         soc_BRDC_CCS_REG_0112r_fields,
  13561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13562         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13563         -1,
  13564         -1,
  13565     },
  13566 #endif /* chips */
  13567 
  13568 #if defined(BCM_88950_A0)
  13569     { /* SOC_REG_INT_BRDC_CCS_REG_014Ar */
  13570         soc_block_list[103],
  13571         soc_genreg,
  13572         1,
  13573         0,
  13574         0x14a,
  13575         SOC_REG_FLAG_WO,
  13576         0,
  13577         1,
  13578         soc_BRDC_CCS_REG_014Ar_fields,
  13579         SOC_RESET_VAL_DEC(0x0000001c, 0x00000000)
  13580         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  13581         -1,
  13582         -1,
  13583     },
  13584 #endif /* chips */
  13585 
  13586 #if defined(BCM_88950_A0)
  13587     { /* SOC_REG_INT_BRDC_CCS_REG_014Br */
  13588         soc_block_list[103],
  13589         soc_genreg,
  13590         1,
  13591         0,
  13592         0x14b,
  13593         SOC_REG_FLAG_WO,
  13594         0,
  13595         1,
  13596         soc_BRDC_CCS_REG_014Br_fields,
  13597         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  13598         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13599         -1,
  13600         -1,
  13601     },
  13602 #endif /* chips */
  13603 
  13604 #if defined(BCM_88950_A0)
  13605     { /* SOC_REG_INT_BRDC_CCS_RESERVED_MIRROR_ADDRr */
  13606         soc_block_list[103],
  13607         soc_genreg,
  13608         1,
  13609         0,
  13610         0x85,
  13611         SOC_REG_FLAG_WO,
  13612         0,
  13613         2,
  13614         soc_BRDC_CCS_RESERVED_MIRROR_ADDRr_fields,
  13615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13616         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  13617         -1,
  13618         -1,
  13619     },
  13620 #endif /* chips */
  13621 
  13622 #if defined(BCM_88950_A0)
  13623     { /* SOC_REG_INT_BRDC_CCS_RESERVED_MTCPr */
  13624         soc_block_list[103],
  13625         soc_genreg,
  13626         1,
  13627         0,
  13628         0xad,
  13629         SOC_REG_FLAG_64_BITS |
  13630                           SOC_REG_FLAG_WO,
  13631         0,
  13632         18,
  13633         soc_BRDC_CCS_RESERVED_MTCPr_fields,
  13634         SOC_RESET_VAL_DEC(0x80000000, 0x00000001)
  13635         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
  13636         -1,
  13637         -1,
  13638     },
  13639 #endif /* chips */
  13640 
  13641 #if defined(BCM_88950_A0)
  13642     { /* SOC_REG_INT_BRDC_CCS_RESERVED_SPARE_0r */
  13643         soc_block_list[103],
  13644         soc_genreg,
  13645         1,
  13646         0,
  13647         0x90,
  13648         SOC_REG_FLAG_WO,
  13649         0,
  13650         1,
  13651         soc_BRDC_CCS_RESERVED_SPARE_0r_fields,
  13652         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  13653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13654         -1,
  13655         -1,
  13656     },
  13657 #endif /* chips */
  13658 
  13659 #if defined(BCM_88950_A0)
  13660     { /* SOC_REG_INT_BRDC_CCS_RESERVED_SPARE_1r */
  13661         soc_block_list[103],
  13662         soc_genreg,
  13663         1,
  13664         0,
  13665         0x91,
  13666         SOC_REG_FLAG_WO,
  13667         0,
  13668         1,
  13669         soc_BRDC_CCS_RESERVED_SPARE_1r_fields,
  13670         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  13671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13672         -1,
  13673         -1,
  13674     },
  13675 #endif /* chips */
  13676 
  13677 #if defined(BCM_88950_A0)
  13678     { /* SOC_REG_INT_BRDC_CCS_RESERVED_SPARE_2r */
  13679         soc_block_list[103],
  13680         soc_genreg,
  13681         1,
  13682         0,
  13683         0x92,
  13684         SOC_REG_FLAG_WO,
  13685         0,
  13686         1,
  13687         soc_BRDC_CCS_RESERVED_SPARE_2r_fields,
  13688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13690         -1,
  13691         -1,
  13692     },
  13693 #endif /* chips */
  13694 
  13695 #if defined(BCM_88950_A0)
  13696     { /* SOC_REG_INT_BRDC_CCS_RESERVED_SPARE_3r */
  13697         soc_block_list[103],
  13698         soc_genreg,
  13699         1,
  13700         0,
  13701         0x93,
  13702         SOC_REG_FLAG_WO,
  13703         0,
  13704         1,
  13705         soc_BRDC_CCS_RESERVED_SPARE_3r_fields,
  13706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13708         -1,
  13709         -1,
  13710     },
  13711 #endif /* chips */
  13712 
  13713 #if defined(BCM_88950_A0)
  13714     { /* SOC_REG_INT_BRDC_CCS_SBUS_BROADCAST_IDr */
  13715         soc_block_list[103],
  13716         soc_genreg,
  13717         1,
  13718         0,
  13719         0x86,
  13720         SOC_REG_FLAG_WO,
  13721         0,
  13722         1,
  13723         soc_BRDC_CCS_SBUS_BROADCAST_IDr_fields,
  13724         SOC_RESET_VAL_DEC(0x00000051, 0x00000000)
  13725         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  13726         -1,
  13727         -1,
  13728     },
  13729 #endif /* chips */
  13730 
  13731 #if defined(BCM_88950_A0)
  13732     { /* SOC_REG_INT_BRDC_CCS_SBUS_LAST_IN_CHAINr */
  13733         soc_block_list[103],
  13734         soc_genreg,
  13735         1,
  13736         0,
  13737         0x87,
  13738         SOC_REG_FLAG_WO,
  13739         0,
  13740         1,
  13741         soc_BRDC_CCS_SBUS_LAST_IN_CHAINr_fields,
  13742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13743         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  13744         -1,
  13745         -1,
  13746     },
  13747 #endif /* chips */
  13748 
  13749 #if defined(BCM_88950_A0)
  13750     { /* SOC_REG_INT_BRDC_CCS_SELF_ROUTED_CELLS_CNTr */
  13751         soc_block_list[103],
  13752         soc_genreg,
  13753         1,
  13754         0,
  13755         0x111,
  13756         SOC_REG_FLAG_RO |
  13757                           SOC_REG_FLAG_WO,
  13758         0,
  13759         2,
  13760         soc_BRDC_CCS_SELF_ROUTED_CELLS_CNTr_fields,
  13761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13763         -1,
  13764         -1,
  13765     },
  13766 #endif /* chips */
  13767 
  13768 #if defined(BCM_88950_A0)
  13769     { /* SOC_REG_INT_BRDC_CCS_TOTAL_CELLS_CNTr */
  13770         soc_block_list[103],
  13771         soc_genreg,
  13772         1,
  13773         0,
  13774         0x115,
  13775         SOC_REG_FLAG_RO |
  13776                           SOC_REG_FLAG_WO,
  13777         0,
  13778         2,
  13779         soc_BRDC_CCS_TOTAL_CELLS_CNTr_fields,
  13780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13782         -1,
  13783         -1,
  13784     },
  13785 #endif /* chips */
  13786 
  13787 #if defined(BCM_88950_A0)
  13788     { /* SOC_REG_INT_BRDC_CCS_UNREACHABLE_DESTINATION_CELLS_CNTr */
  13789         soc_block_list[103],
  13790         soc_genreg,
  13791         1,
  13792         0,
  13793         0x11e,
  13794         SOC_REG_FLAG_RO |
  13795                           SOC_REG_FLAG_WO,
  13796         0,
  13797         2,
  13798         soc_BRDC_CCS_UNREACHABLE_DESTINATION_CELLS_CNTr_fields,
  13799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  13801         -1,
  13802         -1,
  13803     },
  13804 #endif /* chips */
  13805 
  13806 #if defined(BCM_88790_A0)
  13807     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_0r */
  13808         soc_block_list[106],
  13809         soc_genreg,
  13810         1,
  13811         0,
  13812         0x102,
  13813         SOC_REG_FLAG_WO,
  13814         0,
  13815         2,
  13816         soc_BRDC_DCH_AUTO_DOC_NAME_0r_fields,
  13817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13818         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  13819         -1,
  13820         -1,
  13821     },
  13822 #endif /* chips */
  13823 
  13824 #if defined(BCM_88790_A0)
  13825     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_13r */
  13826         soc_block_list[106],
  13827         soc_genreg,
  13828         3,
  13829         0,
  13830         0x10a,
  13831         SOC_REG_FLAG_ARRAY |
  13832                           SOC_REG_FLAG_WO |
  13833                           SOC_REG_FLAG_REG_ARRAY,
  13834         0,
  13835         1,
  13836         soc_BRDC_DCH_AUTO_DOC_NAME_13r_fields,
  13837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13838         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  13839         -1,
  13840         -1,
  13841     },
  13842 #endif /* chips */
  13843 
  13844 #if defined(BCM_88790_A0)
  13845     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_15r */
  13846         soc_block_list[106],
  13847         soc_genreg,
  13848         1,
  13849         0,
  13850         0x10d,
  13851         SOC_REG_FLAG_WO,
  13852         0,
  13853         1,
  13854         soc_BRDC_DCH_AUTO_DOC_NAME_15r_fields,
  13855         SOC_RESET_VAL_DEC(0x0007ffff, 0x00000000)
  13856         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  13857         -1,
  13858         -1,
  13859     },
  13860 #endif /* chips */
  13861 
  13862 #if defined(BCM_88790_A0)
  13863     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_16r */
  13864         soc_block_list[106],
  13865         soc_genreg,
  13866         1,
  13867         0,
  13868         0x116,
  13869         SOC_REG_FLAG_WO,
  13870         0,
  13871         1,
  13872         soc_BRDC_DCH_AUTO_DOC_NAME_16r_fields,
  13873         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  13874         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13875         -1,
  13876         -1,
  13877     },
  13878 #endif /* chips */
  13879 
  13880 #if defined(BCM_88790_A0)
  13881     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_17r */
  13882         soc_block_list[106],
  13883         soc_genreg,
  13884         3,
  13885         0,
  13886         0x117,
  13887         SOC_REG_FLAG_ARRAY |
  13888                           SOC_REG_FLAG_WO |
  13889                           SOC_REG_FLAG_REG_ARRAY,
  13890         0,
  13891         1,
  13892         soc_BRDC_DCH_AUTO_DOC_NAME_17r_fields,
  13893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13894         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  13895         -1,
  13896         -1,
  13897     },
  13898 #endif /* chips */
  13899 
  13900 #if defined(BCM_88790_A0)
  13901     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_29r */
  13902         soc_block_list[106],
  13903         soc_genreg,
  13904         3,
  13905         0,
  13906         0x186,
  13907         SOC_REG_FLAG_64_BITS |
  13908                           SOC_REG_FLAG_ARRAY |
  13909                           SOC_REG_FLAG_RO |
  13910                           SOC_REG_FLAG_WO |
  13911                           SOC_REG_FLAG_REG_ARRAY,
  13912         0,
  13913         1,
  13914         soc_BRDC_DCH_AUTO_DOC_NAME_29r_fields,
  13915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13916         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  13917         -1,
  13918         -1,
  13919     },
  13920 #endif /* chips */
  13921 
  13922 #if defined(BCM_88790_A0)
  13923     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_31r */
  13924         soc_block_list[106],
  13925         soc_genreg,
  13926         3,
  13927         0,
  13928         0x18c,
  13929         SOC_REG_FLAG_64_BITS |
  13930                           SOC_REG_FLAG_ARRAY |
  13931                           SOC_REG_FLAG_RO |
  13932                           SOC_REG_FLAG_WO |
  13933                           SOC_REG_FLAG_REG_ARRAY,
  13934         0,
  13935         1,
  13936         soc_BRDC_DCH_AUTO_DOC_NAME_31r_fields,
  13937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13938         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  13939         -1,
  13940         -1,
  13941     },
  13942 #endif /* chips */
  13943 
  13944 #if defined(BCM_88790_A0)
  13945     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_33r */
  13946         soc_block_list[106],
  13947         soc_genreg,
  13948         3,
  13949         0,
  13950         0x192,
  13951         SOC_REG_FLAG_64_BITS |
  13952                           SOC_REG_FLAG_ARRAY |
  13953                           SOC_REG_FLAG_RO |
  13954                           SOC_REG_FLAG_WO |
  13955                           SOC_REG_FLAG_REG_ARRAY,
  13956         0,
  13957         1,
  13958         soc_BRDC_DCH_AUTO_DOC_NAME_33r_fields,
  13959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  13960         SOC_RESET_MASK_DEC(0xffffffff, 0x000007ff)
  13961         -1,
  13962         -1,
  13963     },
  13964 #endif /* chips */
  13965 
  13966 #if defined(BCM_88790_A0)
  13967     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_35r */
  13968         soc_block_list[106],
  13969         soc_genreg,
  13970         3,
  13971         0,
  13972         0x1a9,
  13973         SOC_REG_FLAG_ARRAY |
  13974                           SOC_REG_FLAG_WO |
  13975                           SOC_REG_FLAG_REG_ARRAY,
  13976         0,
  13977         2,
  13978         soc_BRDC_DCH_AUTO_DOC_NAME_35r_fields,
  13979         SOC_RESET_VAL_DEC(0x00004001, 0x00000000)
  13980         SOC_RESET_MASK_DEC(0x007ffff1, 0x00000000)
  13981         -1,
  13982         -1,
  13983     },
  13984 #endif /* chips */
  13985 
  13986 #if defined(BCM_88790_A0)
  13987     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_36r */
  13988         soc_block_list[106],
  13989         soc_genreg,
  13990         3,
  13991         0,
  13992         0x1ac,
  13993         SOC_REG_FLAG_ARRAY |
  13994                           SOC_REG_FLAG_WO |
  13995                           SOC_REG_FLAG_REG_ARRAY,
  13996         0,
  13997         1,
  13998         soc_BRDC_DCH_AUTO_DOC_NAME_36r_fields,
  13999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14000         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  14001         -1,
  14002         -1,
  14003     },
  14004 #endif /* chips */
  14005 
  14006 #if defined(BCM_88790_A0)
  14007     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_37r */
  14008         soc_block_list[106],
  14009         soc_genreg,
  14010         3,
  14011         0,
  14012         0x1af,
  14013         SOC_REG_FLAG_ARRAY |
  14014                           SOC_REG_FLAG_WO |
  14015                           SOC_REG_FLAG_REG_ARRAY,
  14016         0,
  14017         2,
  14018         soc_BRDC_DCH_AUTO_DOC_NAME_37r_fields,
  14019         SOC_RESET_VAL_DEC(0x00004000, 0x00000000)
  14020         SOC_RESET_MASK_DEC(0x007ffff1, 0x00000000)
  14021         -1,
  14022         -1,
  14023     },
  14024 #endif /* chips */
  14025 
  14026 #if defined(BCM_88790_A0)
  14027     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_38r */
  14028         soc_block_list[106],
  14029         soc_genreg,
  14030         3,
  14031         0,
  14032         0x1b2,
  14033         SOC_REG_FLAG_ARRAY |
  14034                           SOC_REG_FLAG_WO |
  14035                           SOC_REG_FLAG_REG_ARRAY,
  14036         0,
  14037         1,
  14038         soc_BRDC_DCH_AUTO_DOC_NAME_38r_fields,
  14039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14040         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  14041         -1,
  14042         -1,
  14043     },
  14044 #endif /* chips */
  14045 
  14046 #if defined(BCM_88790_A0)
  14047     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_39r */
  14048         soc_block_list[106],
  14049         soc_genreg,
  14050         3,
  14051         0,
  14052         0x1ce,
  14053         SOC_REG_FLAG_ARRAY |
  14054                           SOC_REG_FLAG_WO |
  14055                           SOC_REG_FLAG_REG_ARRAY,
  14056         0,
  14057         1,
  14058         soc_BRDC_DCH_AUTO_DOC_NAME_39r_fields,
  14059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14060         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  14061         -1,
  14062         -1,
  14063     },
  14064 #endif /* chips */
  14065 
  14066 #if defined(BCM_88790_A0)
  14067     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_40r */
  14068         soc_block_list[106],
  14069         soc_genreg,
  14070         3,
  14071         0,
  14072         0x1d2,
  14073         SOC_REG_FLAG_ARRAY |
  14074                           SOC_REG_FLAG_RO |
  14075                           SOC_REG_FLAG_WO |
  14076                           SOC_REG_FLAG_REG_ARRAY,
  14077         SOC_REG_FLAG_COUNTER_FEILDS,
  14078         1,
  14079         soc_BRDC_DCH_AUTO_DOC_NAME_40r_fields,
  14080         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14081         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14082         -1,
  14083         -1,
  14084     },
  14085 #endif /* chips */
  14086 
  14087 #if defined(BCM_88790_A0)
  14088     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_41r */
  14089         soc_block_list[106],
  14090         soc_genreg,
  14091         3,
  14092         0,
  14093         0x1de,
  14094         SOC_REG_FLAG_ARRAY |
  14095                           SOC_REG_FLAG_RO |
  14096                           SOC_REG_FLAG_WO |
  14097                           SOC_REG_FLAG_REG_ARRAY,
  14098         SOC_REG_FLAG_COUNTER_FEILDS,
  14099         1,
  14100         soc_BRDC_DCH_AUTO_DOC_NAME_41r_fields,
  14101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14102         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14103         -1,
  14104         -1,
  14105     },
  14106 #endif /* chips */
  14107 
  14108 #if defined(BCM_88790_A0)
  14109     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_42r */
  14110         soc_block_list[106],
  14111         soc_genreg,
  14112         3,
  14113         0,
  14114         0x1e1,
  14115         SOC_REG_FLAG_64_BITS |
  14116                           SOC_REG_FLAG_ARRAY |
  14117                           SOC_REG_FLAG_RO |
  14118                           SOC_REG_FLAG_WO |
  14119                           SOC_REG_FLAG_REG_ARRAY,
  14120         0,
  14121         1,
  14122         soc_BRDC_DCH_AUTO_DOC_NAME_42r_fields,
  14123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14124         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14125         -1,
  14126         -1,
  14127     },
  14128 #endif /* chips */
  14129 
  14130 #if defined(BCM_88790_A0)
  14131     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_43r */
  14132         soc_block_list[106],
  14133         soc_genreg,
  14134         3,
  14135         0,
  14136         0x1e7,
  14137         SOC_REG_FLAG_64_BITS |
  14138                           SOC_REG_FLAG_ARRAY |
  14139                           SOC_REG_FLAG_RO |
  14140                           SOC_REG_FLAG_WO |
  14141                           SOC_REG_FLAG_REG_ARRAY,
  14142         0,
  14143         1,
  14144         soc_BRDC_DCH_AUTO_DOC_NAME_43r_fields,
  14145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14146         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14147         -1,
  14148         -1,
  14149     },
  14150 #endif /* chips */
  14151 
  14152 #if defined(BCM_88790_A0)
  14153     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_44r */
  14154         soc_block_list[106],
  14155         soc_genreg,
  14156         3,
  14157         0,
  14158         0x1ed,
  14159         SOC_REG_FLAG_64_BITS |
  14160                           SOC_REG_FLAG_ARRAY |
  14161                           SOC_REG_FLAG_RO |
  14162                           SOC_REG_FLAG_WO |
  14163                           SOC_REG_FLAG_REG_ARRAY,
  14164         0,
  14165         1,
  14166         soc_BRDC_DCH_AUTO_DOC_NAME_44r_fields,
  14167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14168         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  14169         -1,
  14170         -1,
  14171     },
  14172 #endif /* chips */
  14173 
  14174 #if defined(BCM_88790_A0)
  14175     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_45r */
  14176         soc_block_list[106],
  14177         soc_genreg,
  14178         1,
  14179         0,
  14180         0x1f8,
  14181         SOC_REG_FLAG_RO |
  14182                           SOC_REG_FLAG_WO,
  14183         0,
  14184         1,
  14185         soc_BRDC_DCH_AUTO_DOC_NAME_45r_fields,
  14186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14187         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  14188         -1,
  14189         -1,
  14190     },
  14191 #endif /* chips */
  14192 
  14193 #if defined(BCM_88790_A0)
  14194     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_46r */
  14195         soc_block_list[106],
  14196         soc_genreg,
  14197         1,
  14198         0,
  14199         0x1f9,
  14200         SOC_REG_FLAG_RO |
  14201                           SOC_REG_FLAG_WO,
  14202         0,
  14203         1,
  14204         soc_BRDC_DCH_AUTO_DOC_NAME_46r_fields,
  14205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14206         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  14207         -1,
  14208         -1,
  14209     },
  14210 #endif /* chips */
  14211 
  14212 #if defined(BCM_88790_A0)
  14213     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_47r */
  14214         soc_block_list[106],
  14215         soc_genreg,
  14216         1,
  14217         0,
  14218         0x1fa,
  14219         SOC_REG_FLAG_RO |
  14220                           SOC_REG_FLAG_WO,
  14221         0,
  14222         1,
  14223         soc_BRDC_DCH_AUTO_DOC_NAME_47r_fields,
  14224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14225         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  14226         -1,
  14227         -1,
  14228     },
  14229 #endif /* chips */
  14230 
  14231 #if defined(BCM_88790_A0)
  14232     { /* SOC_REG_INT_BRDC_DCH_AUTO_DOC_NAME_48r */
  14233         soc_block_list[106],
  14234         soc_genreg,
  14235         1,
  14236         0,
  14237         0x242,
  14238         SOC_REG_FLAG_WO,
  14239         0,
  14240         1,
  14241         soc_BRDC_DCH_AUTO_DOC_NAME_48r_fields,
  14242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14243         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  14244         -1,
  14245         -1,
  14246     },
  14247 #endif /* chips */
  14248 
  14249 #if defined(BCM_88950_A0)
  14250     { /* SOC_REG_INT_BRDC_DCH_CAPTURED_CELL_Ar */
  14251         soc_block_list[106],
  14252         soc_genreg,
  14253         1,
  14254         0,
  14255         0x13d,
  14256         SOC_REG_FLAG_ABOVE_64_BITS |
  14257                           SOC_REG_FLAG_RO |
  14258                           SOC_REG_FLAG_WO,
  14259         0,
  14260         1,
  14261         soc_BRDC_DCH_CAPTURED_CELL_Ar_fields,
  14262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14263         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14264         -1,
  14265         -1,
  14266     },
  14267 #endif /* chips */
  14268 
  14269 #if defined(BCM_88950_A0)
  14270     { /* SOC_REG_INT_BRDC_DCH_CAPTURED_CELL_Br */
  14271         soc_block_list[106],
  14272         soc_genreg,
  14273         1,
  14274         0,
  14275         0x150,
  14276         SOC_REG_FLAG_ABOVE_64_BITS |
  14277                           SOC_REG_FLAG_RO |
  14278                           SOC_REG_FLAG_WO,
  14279         0,
  14280         1,
  14281         soc_BRDC_DCH_CAPTURED_CELL_Br_fields,
  14282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14283         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14284         -1,
  14285         -1,
  14286     },
  14287 #endif /* chips */
  14288 
  14289 #if defined(BCM_88950_A0)
  14290     { /* SOC_REG_INT_BRDC_DCH_CAPTURED_CELL_Cr */
  14291         soc_block_list[106],
  14292         soc_genreg,
  14293         1,
  14294         0,
  14295         0x163,
  14296         SOC_REG_FLAG_ABOVE_64_BITS |
  14297                           SOC_REG_FLAG_RO |
  14298                           SOC_REG_FLAG_WO,
  14299         0,
  14300         1,
  14301         soc_BRDC_DCH_CAPTURED_CELL_Cr_fields,
  14302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14303         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14304         -1,
  14305         -1,
  14306     },
  14307 #endif /* chips */
  14308 
  14309 #if defined(BCM_88950_A0)
  14310     { /* SOC_REG_INT_BRDC_DCH_CAPTURED_CELL_Dr */
  14311         soc_block_list[106],
  14312         soc_genreg,
  14313         1,
  14314         0,
  14315         0x176,
  14316         SOC_REG_FLAG_ABOVE_64_BITS |
  14317                           SOC_REG_FLAG_RO |
  14318                           SOC_REG_FLAG_WO,
  14319         0,
  14320         1,
  14321         soc_BRDC_DCH_CAPTURED_CELL_Dr_fields,
  14322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14324         -1,
  14325         -1,
  14326     },
  14327 #endif /* chips */
  14328 
  14329 #if defined(BCM_88790_A0)
  14330     { /* SOC_REG_INT_BRDC_DCH_CAPTURED_CELL_DATA_0r */
  14331         soc_block_list[106],
  14332         soc_genreg,
  14333         1,
  14334         0,
  14335         0x143,
  14336         SOC_REG_FLAG_ABOVE_64_BITS |
  14337                           SOC_REG_FLAG_RO |
  14338                           SOC_REG_FLAG_WO,
  14339         0,
  14340         1,
  14341         soc_BRDC_DCH_CAPTURED_CELL_DATA_0r_fields,
  14342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14343         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14344         -1,
  14345         -1,
  14346     },
  14347 #endif /* chips */
  14348 
  14349 #if defined(BCM_88790_A0)
  14350     { /* SOC_REG_INT_BRDC_DCH_CAPTURED_CELL_DATA_1r */
  14351         soc_block_list[106],
  14352         soc_genreg,
  14353         1,
  14354         0,
  14355         0x156,
  14356         SOC_REG_FLAG_ABOVE_64_BITS |
  14357                           SOC_REG_FLAG_RO |
  14358                           SOC_REG_FLAG_WO,
  14359         0,
  14360         1,
  14361         soc_BRDC_DCH_CAPTURED_CELL_DATA_1r_fields,
  14362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14364         -1,
  14365         -1,
  14366     },
  14367 #endif /* chips */
  14368 
  14369 #if defined(BCM_88790_A0)
  14370     { /* SOC_REG_INT_BRDC_DCH_CAPTURED_CELL_DATA_2r */
  14371         soc_block_list[106],
  14372         soc_genreg,
  14373         1,
  14374         0,
  14375         0x169,
  14376         SOC_REG_FLAG_ABOVE_64_BITS |
  14377                           SOC_REG_FLAG_RO |
  14378                           SOC_REG_FLAG_WO,
  14379         0,
  14380         1,
  14381         soc_BRDC_DCH_CAPTURED_CELL_DATA_2r_fields,
  14382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  14384         -1,
  14385         -1,
  14386     },
  14387 #endif /* chips */
  14388 
  14389 #if defined(BCM_88950_A0)
  14390     { /* SOC_REG_INT_BRDC_DCH_CELL_TYPE_ERR_SRCr */
  14391         soc_block_list[106],
  14392         soc_genreg,
  14393         1,
  14394         0,
  14395         0x189,
  14396         SOC_REG_FLAG_RO |
  14397                           SOC_REG_FLAG_WO,
  14398         0,
  14399         1,
  14400         soc_BRDC_DCH_CELL_TYPE_ERR_SRCr_fields,
  14401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14402         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  14403         -1,
  14404         -1,
  14405     },
  14406 #endif /* chips */
  14407 
  14408 #if defined(BCM_88790_A0)
  14409     { /* SOC_REG_INT_BRDC_DCH_CELL_TYPE_ERR_SRC_BCM88790_A0r */
  14410         soc_block_list[106],
  14411         soc_genreg,
  14412         1,
  14413         0,
  14414         0x17c,
  14415         SOC_REG_FLAG_RO |
  14416                           SOC_REG_FLAG_WO,
  14417         0,
  14418         1,
  14419         soc_BRDC_DCH_CELL_TYPE_ERR_SRC_BCM88790_A0r_fields,
  14420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14421         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  14422         -1,
  14423         -1,
  14424     },
  14425 #endif /* chips */
  14426 
  14427 #if defined(BCM_88950_A0)
  14428     { /* SOC_REG_INT_BRDC_DCH_DCH_ENABLERS_REGISTER_1r */
  14429         soc_block_list[106],
  14430         soc_genreg,
  14431         1,
  14432         0,
  14433         0x104,
  14434         SOC_REG_FLAG_64_BITS |
  14435                           SOC_REG_FLAG_WO,
  14436         0,
  14437         13,
  14438         soc_BRDC_DCH_DCH_ENABLERS_REGISTER_1r_fields,
  14439         SOC_RESET_VAL_DEC(0x00e01002, 0x00007c00)
  14440         SOC_RESET_MASK_DEC(0xfffffffe, 0x00007fff)
  14441         -1,
  14442         -1,
  14443     },
  14444 #endif /* chips */
  14445 
  14446 #if defined(BCM_88950_A0)
  14447     { /* SOC_REG_INT_BRDC_DCH_DCH_ENABLERS_REGISTER_2r */
  14448         soc_block_list[106],
  14449         soc_genreg,
  14450         1,
  14451         0,
  14452         0x106,
  14453         SOC_REG_FLAG_WO,
  14454         0,
  14455         11,
  14456         soc_BRDC_DCH_DCH_ENABLERS_REGISTER_2r_fields,
  14457         SOC_RESET_VAL_DEC(0x3301d07f, 0x00000000)
  14458         SOC_RESET_MASK_DEC(0x3bffffff, 0x00000000)
  14459         -1,
  14460         -1,
  14461     },
  14462 #endif /* chips */
  14463 
  14464 #if defined(BCM_88790_A0)
  14465     { /* SOC_REG_INT_BRDC_DCH_DCH_ENABLERS_REGISTER_1_BCM88790_A0r */
  14466         soc_block_list[106],
  14467         soc_genreg,
  14468         1,
  14469         0,
  14470         0x103,
  14471         SOC_REG_FLAG_WO,
  14472         0,
  14473         14,
  14474         soc_BRDC_DCH_DCH_ENABLERS_REGISTER_1_BCM88790_A0r_fields,
  14475         SOC_RESET_VAL_DEC(0x07c00000, 0x00000000)
  14476         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  14477         -1,
  14478         -1,
  14479     },
  14480 #endif /* chips */
  14481 
  14482 #if defined(BCM_88790_A0)
  14483     { /* SOC_REG_INT_BRDC_DCH_DCH_ENABLERS_REGISTER_2_Pr */
  14484         soc_block_list[106],
  14485         soc_genreg,
  14486         3,
  14487         0,
  14488         0x104,
  14489         SOC_REG_FLAG_ARRAY |
  14490                           SOC_REG_FLAG_WO |
  14491                           SOC_REG_FLAG_REG_ARRAY,
  14492         0,
  14493         3,
  14494         soc_BRDC_DCH_DCH_ENABLERS_REGISTER_2_Pr_fields,
  14495         SOC_RESET_VAL_DEC(0x00e01002, 0x00000000)
  14496         SOC_RESET_MASK_DEC(0x07fffffe, 0x00000000)
  14497         -1,
  14498         -1,
  14499     },
  14500 #endif /* chips */
  14501 
  14502 #if defined(BCM_88790_A0)
  14503     { /* SOC_REG_INT_BRDC_DCH_DCH_ENABLERS_REGISTER_3_Pr */
  14504         soc_block_list[106],
  14505         soc_genreg,
  14506         3,
  14507         0,
  14508         0x107,
  14509         SOC_REG_FLAG_ARRAY |
  14510                           SOC_REG_FLAG_WO |
  14511                           SOC_REG_FLAG_REG_ARRAY,
  14512         0,
  14513         1,
  14514         soc_BRDC_DCH_DCH_ENABLERS_REGISTER_3_Pr_fields,
  14515         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  14516         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  14517         -1,
  14518         -1,
  14519     },
  14520 #endif /* chips */
  14521 
  14522 #if defined(BCM_88950_A0)
  14523     { /* SOC_REG_INT_BRDC_DCH_DCH_ERROR_INITIATION_DATAr */
  14524         soc_block_list[106],
  14525         soc_genreg,
  14526         1,
  14527         0,
  14528         0x209,
  14529         SOC_REG_FLAG_WO,
  14530         0,
  14531         2,
  14532         soc_BRDC_DCH_DCH_ERROR_INITIATION_DATAr_fields,
  14533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14534         SOC_RESET_MASK_DEC(0x00000006, 0x00000000)
  14535         -1,
  14536         -1,
  14537     },
  14538 #endif /* chips */
  14539 
  14540 #if defined(BCM_88790_A0)
  14541     { /* SOC_REG_INT_BRDC_DCH_DCH_ERROR_INITIATION_DATA_BCM88790_A0r */
  14542         soc_block_list[106],
  14543         soc_genreg,
  14544         1,
  14545         0,
  14546         0x1f7,
  14547         SOC_REG_FLAG_WO,
  14548         0,
  14549         2,
  14550         soc_BRDC_DCH_DCH_ERROR_INITIATION_DATA_BCM88790_A0r_fields,
  14551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14552         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  14553         -1,
  14554         -1,
  14555     },
  14556 #endif /* chips */
  14557 
  14558 #if defined(BCM_88950_A0)
  14559     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_0r */
  14560         soc_block_list[106],
  14561         soc_genreg,
  14562         1,
  14563         0,
  14564         0x1b8,
  14565         SOC_REG_FLAG_RO |
  14566                           SOC_REG_FLAG_WO,
  14567         0,
  14568         2,
  14569         soc_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_0r_fields,
  14570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14571         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14572         -1,
  14573         -1,
  14574     },
  14575 #endif /* chips */
  14576 
  14577 #if defined(BCM_88950_A0)
  14578     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_1r */
  14579         soc_block_list[106],
  14580         soc_genreg,
  14581         1,
  14582         0,
  14583         0x1b9,
  14584         SOC_REG_FLAG_RO |
  14585                           SOC_REG_FLAG_WO,
  14586         0,
  14587         2,
  14588         soc_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_1r_fields,
  14589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14590         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14591         -1,
  14592         -1,
  14593     },
  14594 #endif /* chips */
  14595 
  14596 #if defined(BCM_88950_A0)
  14597     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_2r */
  14598         soc_block_list[106],
  14599         soc_genreg,
  14600         1,
  14601         0,
  14602         0x1ba,
  14603         SOC_REG_FLAG_RO |
  14604                           SOC_REG_FLAG_WO,
  14605         0,
  14606         2,
  14607         soc_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_2r_fields,
  14608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14610         -1,
  14611         -1,
  14612     },
  14613 #endif /* chips */
  14614 
  14615 #if defined(BCM_88790_A0)
  14616     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_0_BCM88790_A0r */
  14617         soc_block_list[106],
  14618         soc_genreg,
  14619         1,
  14620         0,
  14621         0x1a3,
  14622         SOC_REG_FLAG_RO |
  14623                           SOC_REG_FLAG_WO,
  14624         SOC_REG_FLAG_COUNTER_FEILDS,
  14625         1,
  14626         soc_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_0_BCM88790_A0r_fields,
  14627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14629         -1,
  14630         -1,
  14631     },
  14632 #endif /* chips */
  14633 
  14634 #if defined(BCM_88790_A0)
  14635     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_1_BCM88790_A0r */
  14636         soc_block_list[106],
  14637         soc_genreg,
  14638         1,
  14639         0,
  14640         0x1a4,
  14641         SOC_REG_FLAG_RO |
  14642                           SOC_REG_FLAG_WO,
  14643         SOC_REG_FLAG_COUNTER_FEILDS,
  14644         1,
  14645         soc_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_1_BCM88790_A0r_fields,
  14646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14647         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14648         -1,
  14649         -1,
  14650     },
  14651 #endif /* chips */
  14652 
  14653 #if defined(BCM_88790_A0)
  14654     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_2_BCM88790_A0r */
  14655         soc_block_list[106],
  14656         soc_genreg,
  14657         1,
  14658         0,
  14659         0x1a5,
  14660         SOC_REG_FLAG_RO |
  14661                           SOC_REG_FLAG_WO,
  14662         SOC_REG_FLAG_COUNTER_FEILDS,
  14663         1,
  14664         soc_BRDC_DCH_DCH_TOTAL_CELL_CNT_P_2_BCM88790_A0r_fields,
  14665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14666         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14667         -1,
  14668         -1,
  14669     },
  14670 #endif /* chips */
  14671 
  14672 #if defined(BCM_88950_A0)
  14673     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_0r */
  14674         soc_block_list[106],
  14675         soc_genreg,
  14676         1,
  14677         0,
  14678         0x1bb,
  14679         SOC_REG_FLAG_RO |
  14680                           SOC_REG_FLAG_WO,
  14681         0,
  14682         2,
  14683         soc_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_0r_fields,
  14684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14685         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14686         -1,
  14687         -1,
  14688     },
  14689 #endif /* chips */
  14690 
  14691 #if defined(BCM_88950_A0)
  14692     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_1r */
  14693         soc_block_list[106],
  14694         soc_genreg,
  14695         1,
  14696         0,
  14697         0x1bc,
  14698         SOC_REG_FLAG_RO |
  14699                           SOC_REG_FLAG_WO,
  14700         0,
  14701         2,
  14702         soc_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_1r_fields,
  14703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14705         -1,
  14706         -1,
  14707     },
  14708 #endif /* chips */
  14709 
  14710 #if defined(BCM_88950_A0)
  14711     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_2r */
  14712         soc_block_list[106],
  14713         soc_genreg,
  14714         1,
  14715         0,
  14716         0x1bd,
  14717         SOC_REG_FLAG_RO |
  14718                           SOC_REG_FLAG_WO,
  14719         0,
  14720         2,
  14721         soc_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_2r_fields,
  14722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14724         -1,
  14725         -1,
  14726     },
  14727 #endif /* chips */
  14728 
  14729 #if defined(BCM_88790_A0)
  14730     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_0_BCM88790_A0r */
  14731         soc_block_list[106],
  14732         soc_genreg,
  14733         1,
  14734         0,
  14735         0x1a6,
  14736         SOC_REG_FLAG_RO |
  14737                           SOC_REG_FLAG_WO,
  14738         SOC_REG_FLAG_COUNTER_FEILDS,
  14739         1,
  14740         soc_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_0_BCM88790_A0r_fields,
  14741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14743         -1,
  14744         -1,
  14745     },
  14746 #endif /* chips */
  14747 
  14748 #if defined(BCM_88790_A0)
  14749     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_1_BCM88790_A0r */
  14750         soc_block_list[106],
  14751         soc_genreg,
  14752         1,
  14753         0,
  14754         0x1a7,
  14755         SOC_REG_FLAG_RO |
  14756                           SOC_REG_FLAG_WO,
  14757         SOC_REG_FLAG_COUNTER_FEILDS,
  14758         1,
  14759         soc_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_1_BCM88790_A0r_fields,
  14760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14762         -1,
  14763         -1,
  14764     },
  14765 #endif /* chips */
  14766 
  14767 #if defined(BCM_88790_A0)
  14768     { /* SOC_REG_INT_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_2_BCM88790_A0r */
  14769         soc_block_list[106],
  14770         soc_genreg,
  14771         1,
  14772         0,
  14773         0x1a8,
  14774         SOC_REG_FLAG_RO |
  14775                           SOC_REG_FLAG_WO,
  14776         SOC_REG_FLAG_COUNTER_FEILDS,
  14777         1,
  14778         soc_BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_2_BCM88790_A0r_fields,
  14779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14781         -1,
  14782         -1,
  14783     },
  14784 #endif /* chips */
  14785 
  14786 #if defined(BCM_88950_A0)
  14787     { /* SOC_REG_INT_BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_0r */
  14788         soc_block_list[106],
  14789         soc_genreg,
  14790         1,
  14791         0,
  14792         0x20a,
  14793         SOC_REG_FLAG_RO |
  14794                           SOC_REG_FLAG_WO,
  14795         0,
  14796         2,
  14797         soc_BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_0r_fields,
  14798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14800         -1,
  14801         -1,
  14802     },
  14803 #endif /* chips */
  14804 
  14805 #if defined(BCM_88950_A0)
  14806     { /* SOC_REG_INT_BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_1r */
  14807         soc_block_list[106],
  14808         soc_genreg,
  14809         1,
  14810         0,
  14811         0x20b,
  14812         SOC_REG_FLAG_RO |
  14813                           SOC_REG_FLAG_WO,
  14814         0,
  14815         2,
  14816         soc_BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_1r_fields,
  14817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14819         -1,
  14820         -1,
  14821     },
  14822 #endif /* chips */
  14823 
  14824 #if defined(BCM_88950_A0)
  14825     { /* SOC_REG_INT_BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_2r */
  14826         soc_block_list[106],
  14827         soc_genreg,
  14828         1,
  14829         0,
  14830         0x20c,
  14831         SOC_REG_FLAG_RO |
  14832                           SOC_REG_FLAG_WO,
  14833         0,
  14834         2,
  14835         soc_BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_2r_fields,
  14836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14838         -1,
  14839         -1,
  14840     },
  14841 #endif /* chips */
  14842 
  14843 #if defined(BCM_88950_A0)
  14844     { /* SOC_REG_INT_BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_0r */
  14845         soc_block_list[106],
  14846         soc_genreg,
  14847         1,
  14848         0,
  14849         0x20d,
  14850         SOC_REG_FLAG_RO |
  14851                           SOC_REG_FLAG_WO,
  14852         0,
  14853         2,
  14854         soc_BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_0r_fields,
  14855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14857         -1,
  14858         -1,
  14859     },
  14860 #endif /* chips */
  14861 
  14862 #if defined(BCM_88950_A0)
  14863     { /* SOC_REG_INT_BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_1r */
  14864         soc_block_list[106],
  14865         soc_genreg,
  14866         1,
  14867         0,
  14868         0x20e,
  14869         SOC_REG_FLAG_RO |
  14870                           SOC_REG_FLAG_WO,
  14871         0,
  14872         2,
  14873         soc_BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_1r_fields,
  14874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14876         -1,
  14877         -1,
  14878     },
  14879 #endif /* chips */
  14880 
  14881 #if defined(BCM_88950_A0)
  14882     { /* SOC_REG_INT_BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_2r */
  14883         soc_block_list[106],
  14884         soc_genreg,
  14885         1,
  14886         0,
  14887         0x20f,
  14888         SOC_REG_FLAG_RO |
  14889                           SOC_REG_FLAG_WO,
  14890         0,
  14891         2,
  14892         soc_BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_2r_fields,
  14893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14894         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14895         -1,
  14896         -1,
  14897     },
  14898 #endif /* chips */
  14899 
  14900 #if defined(BCM_88790_A0)
  14901     { /* SOC_REG_INT_BRDC_DCH_DROP_FILTER_CNTr */
  14902         soc_block_list[106],
  14903         soc_genreg,
  14904         1,
  14905         0,
  14906         0x1a2,
  14907         SOC_REG_FLAG_RO |
  14908                           SOC_REG_FLAG_WO,
  14909         SOC_REG_FLAG_COUNTER_FEILDS,
  14910         1,
  14911         soc_BRDC_DCH_DROP_FILTER_CNTr_fields,
  14912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14914         -1,
  14915         -1,
  14916     },
  14917 #endif /* chips */
  14918 
  14919 #if defined(BCM_88950_A0)
  14920     { /* SOC_REG_INT_BRDC_DCH_DROP_LOW_PRIORITY_CNT_Pr */
  14921         soc_block_list[106],
  14922         soc_genreg,
  14923         3,
  14924         0,
  14925         0x205,
  14926         SOC_REG_FLAG_ARRAY |
  14927                           SOC_REG_FLAG_RO |
  14928                           SOC_REG_FLAG_WO |
  14929                           SOC_REG_FLAG_REG_ARRAY,
  14930         0,
  14931         2,
  14932         soc_BRDC_DCH_DROP_LOW_PRIORITY_CNT_Pr_fields,
  14933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14935         -1,
  14936         -1,
  14937     },
  14938 #endif /* chips */
  14939 
  14940 #if defined(BCM_88790_A0)
  14941     { /* SOC_REG_INT_BRDC_DCH_DROP_LOW_PRIORITY_CNT_P_BCM88790_A0r */
  14942         soc_block_list[106],
  14943         soc_genreg,
  14944         3,
  14945         0,
  14946         0x1f3,
  14947         SOC_REG_FLAG_ARRAY |
  14948                           SOC_REG_FLAG_RO |
  14949                           SOC_REG_FLAG_WO |
  14950                           SOC_REG_FLAG_REG_ARRAY,
  14951         SOC_REG_FLAG_COUNTER_FEILDS,
  14952         1,
  14953         soc_BRDC_DCH_DROP_LOW_PRIORITY_CNT_P_BCM88790_A0r_fields,
  14954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  14955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  14956         -1,
  14957         -1,
  14958     },
  14959 #endif /* chips */
  14960 
  14961 #if defined(BCM_88950_A0)
  14962     { /* SOC_REG_INT_BRDC_DCH_DYN_PIPES_WEIGHTS_REGISTERr */
  14963         soc_block_list[106],
  14964         soc_genreg,
  14965         1,
  14966         0,
  14967         0x122,
  14968         SOC_REG_FLAG_WO,
  14969         0,
  14970         4,
  14971         soc_BRDC_DCH_DYN_PIPES_WEIGHTS_REGISTERr_fields,
  14972         SOC_RESET_VAL_DEC(0x00204081, 0x00000000)
  14973         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  14974         -1,
  14975         -1,
  14976     },
  14977 #endif /* chips */
  14978 
  14979 #if defined(BCM_88790_A0)
  14980     { /* SOC_REG_INT_BRDC_DCH_DYN_PIPES_WEIGHTS_REGISTER_BCM88790_A0r */
  14981         soc_block_list[106],
  14982         soc_genreg,
  14983         1,
  14984         0,
  14985         0x127,
  14986         SOC_REG_FLAG_WO,
  14987         0,
  14988         4,
  14989         soc_BRDC_DCH_DYN_PIPES_WEIGHTS_REGISTER_BCM88790_A0r_fields,
  14990         SOC_RESET_VAL_DEC(0x01010101, 0x00000000)
  14991         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  14992         -1,
  14993         -1,
  14994     },
  14995 #endif /* chips */
  14996 
  14997 #if defined(BCM_88950_A0)
  14998     { /* SOC_REG_INT_BRDC_DCH_DYN_WFQ_WEIGHT_THD_REGISTEr */
  14999         soc_block_list[106],
  15000         soc_genreg,
  15001         1,
  15002         0,
  15003         0x123,
  15004         SOC_REG_FLAG_WO,
  15005         0,
  15006         2,
  15007         soc_BRDC_DCH_DYN_WFQ_WEIGHT_THD_REGISTEr_fields,
  15008         SOC_RESET_VAL_DEC(0x0003ffff, 0x00000000)
  15009         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  15010         -1,
  15011         -1,
  15012     },
  15013 #endif /* chips */
  15014 
  15015 #if defined(BCM_88950_A0)
  15016     { /* SOC_REG_INT_BRDC_DCH_ECC_1B_ERR_CNTr */
  15017         soc_block_list[106],
  15018         soc_genreg,
  15019         1,
  15020         0,
  15021         0x94,
  15022         SOC_REG_FLAG_64_BITS |
  15023                           SOC_REG_FLAG_RO |
  15024                           SOC_REG_FLAG_WO,
  15025         0,
  15026         4,
  15027         soc_BRDC_CCS_ECC_1B_ERR_CNTr_fields,
  15028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15029         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  15030         -1,
  15031         -1,
  15032     },
  15033 #endif /* chips */
  15034 
  15035 #if defined(BCM_88790_A0)
  15036     { /* SOC_REG_INT_BRDC_DCH_ECC_1B_ERR_CNT_BCM88790_A0r */
  15037         soc_block_list[106],
  15038         soc_genreg,
  15039         1,
  15040         0,
  15041         0x94,
  15042         SOC_REG_FLAG_64_BITS |
  15043                           SOC_REG_FLAG_RO |
  15044                           SOC_REG_FLAG_WO,
  15045         SOC_REG_FLAG_COUNTER_FEILDS,
  15046         4,
  15047         soc_BRDC_DCH_ECC_1B_ERR_CNTr_fields,
  15048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15049         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  15050         -1,
  15051         -1,
  15052     },
  15053 #endif /* chips */
  15054 
  15055 #if defined(BCM_88950_A0)
  15056     { /* SOC_REG_INT_BRDC_DCH_ECC_2B_ERR_CNTr */
  15057         soc_block_list[106],
  15058         soc_genreg,
  15059         1,
  15060         0,
  15061         0x96,
  15062         SOC_REG_FLAG_64_BITS |
  15063                           SOC_REG_FLAG_RO |
  15064                           SOC_REG_FLAG_WO,
  15065         0,
  15066         4,
  15067         soc_BRDC_CCS_ECC_2B_ERR_CNTr_fields,
  15068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15069         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  15070         -1,
  15071         -1,
  15072     },
  15073 #endif /* chips */
  15074 
  15075 #if defined(BCM_88790_A0)
  15076     { /* SOC_REG_INT_BRDC_DCH_ECC_2B_ERR_CNT_BCM88790_A0r */
  15077         soc_block_list[106],
  15078         soc_genreg,
  15079         1,
  15080         0,
  15081         0x96,
  15082         SOC_REG_FLAG_64_BITS |
  15083                           SOC_REG_FLAG_RO |
  15084                           SOC_REG_FLAG_WO,
  15085         SOC_REG_FLAG_COUNTER_FEILDS,
  15086         4,
  15087         soc_BRDC_DCH_ECC_2B_ERR_CNTr_fields,
  15088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15089         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  15090         -1,
  15091         -1,
  15092     },
  15093 #endif /* chips */
  15094 
  15095 #if defined(BCM_88950_A0)
  15096     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_1B_INITIATEr */
  15097         soc_block_list[106],
  15098         soc_genreg,
  15099         1,
  15100         0,
  15101         0xa4,
  15102         SOC_REG_FLAG_WO,
  15103         0,
  15104         29,
  15105         soc_BRDC_DCH_ECC_ERR_1B_INITIATEr_fields,
  15106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15107         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  15108         -1,
  15109         -1,
  15110     },
  15111 #endif /* chips */
  15112 
  15113 #if defined(BCM_88790_A0)
  15114     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_1B_INITIATE_BCM88790_A0r */
  15115         soc_block_list[106],
  15116         soc_genreg,
  15117         1,
  15118         0,
  15119         0xa4,
  15120         SOC_REG_FLAG_64_BITS |
  15121                           SOC_REG_FLAG_WO,
  15122         0,
  15123         33,
  15124         soc_BRDC_DCH_ECC_ERR_1B_INITIATE_BCM88790_A0r_fields,
  15125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  15127         -1,
  15128         -1,
  15129     },
  15130 #endif /* chips */
  15131 
  15132 #if defined(BCM_88950_A0)
  15133     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_1B_MONITOR_MEM_MASKr */
  15134         soc_block_list[106],
  15135         soc_genreg,
  15136         1,
  15137         0,
  15138         0x9a,
  15139         SOC_REG_FLAG_64_BITS |
  15140                           SOC_REG_FLAG_WO,
  15141         0,
  15142         41,
  15143         soc_BRDC_DCH_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  15144         SOC_RESET_VAL_DEC(0xffffffff, 0x000001ff)
  15145         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  15146         -1,
  15147         -1,
  15148     },
  15149 #endif /* chips */
  15150 
  15151 #if defined(BCM_88790_A0)
  15152     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88790_A0r */
  15153         soc_block_list[106],
  15154         soc_genreg,
  15155         1,
  15156         0,
  15157         0x9a,
  15158         SOC_REG_FLAG_64_BITS |
  15159                           SOC_REG_FLAG_WO,
  15160         0,
  15161         33,
  15162         soc_BRDC_DCH_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88790_A0r_fields,
  15163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  15165         -1,
  15166         -1,
  15167     },
  15168 #endif /* chips */
  15169 
  15170 #if defined(BCM_88950_A0)
  15171     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_2B_INITIATEr */
  15172         soc_block_list[106],
  15173         soc_genreg,
  15174         1,
  15175         0,
  15176         0xa6,
  15177         SOC_REG_FLAG_WO,
  15178         0,
  15179         29,
  15180         soc_BRDC_DCH_ECC_ERR_2B_INITIATEr_fields,
  15181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15182         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  15183         -1,
  15184         -1,
  15185     },
  15186 #endif /* chips */
  15187 
  15188 #if defined(BCM_88790_A0)
  15189     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_2B_INITIATE_BCM88790_A0r */
  15190         soc_block_list[106],
  15191         soc_genreg,
  15192         1,
  15193         0,
  15194         0xa6,
  15195         SOC_REG_FLAG_64_BITS |
  15196                           SOC_REG_FLAG_WO,
  15197         0,
  15198         33,
  15199         soc_BRDC_DCH_ECC_ERR_2B_INITIATE_BCM88790_A0r_fields,
  15200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15201         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  15202         -1,
  15203         -1,
  15204     },
  15205 #endif /* chips */
  15206 
  15207 #if defined(BCM_88950_A0)
  15208     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_2B_MONITOR_MEM_MASKr */
  15209         soc_block_list[106],
  15210         soc_genreg,
  15211         1,
  15212         0,
  15213         0x9c,
  15214         SOC_REG_FLAG_64_BITS |
  15215                           SOC_REG_FLAG_WO,
  15216         0,
  15217         41,
  15218         soc_BRDC_DCH_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  15219         SOC_RESET_VAL_DEC(0xffffffff, 0x000001ff)
  15220         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  15221         -1,
  15222         -1,
  15223     },
  15224 #endif /* chips */
  15225 
  15226 #if defined(BCM_88790_A0)
  15227     { /* SOC_REG_INT_BRDC_DCH_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88790_A0r */
  15228         soc_block_list[106],
  15229         soc_genreg,
  15230         1,
  15231         0,
  15232         0x9c,
  15233         SOC_REG_FLAG_64_BITS |
  15234                           SOC_REG_FLAG_WO,
  15235         0,
  15236         33,
  15237         soc_BRDC_DCH_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88790_A0r_fields,
  15238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  15240         -1,
  15241         -1,
  15242     },
  15243 #endif /* chips */
  15244 
  15245 #if defined(BCM_88950_A0)
  15246     { /* SOC_REG_INT_BRDC_DCH_ECC_INTERRUPT_REGISTERr */
  15247         soc_block_list[106],
  15248         soc_genreg,
  15249         1,
  15250         0,
  15251         0x7,
  15252         SOC_REG_FLAG_WO |
  15253                           SOC_REG_FLAG_INTERRUPT,
  15254         0,
  15255         3,
  15256         soc_BRDC_DCH_ECC_INTERRUPT_REGISTERr_fields,
  15257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15258         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15259         -1,
  15260         -1,
  15261     },
  15262 #endif /* chips */
  15263 
  15264 #if defined(BCM_88790_A0)
  15265     { /* SOC_REG_INT_BRDC_DCH_ECC_INTERRUPT_REGISTER_BCM88790_A0r */
  15266         soc_block_list[106],
  15267         soc_genreg,
  15268         1,
  15269         0,
  15270         0x7,
  15271         SOC_REG_FLAG_WO |
  15272                           SOC_REG_FLAG_INTERRUPT |
  15273                           SOC_REG_FLAG_SIGNAL,
  15274         0,
  15275         3,
  15276         soc_BRDC_DCH_ECC_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  15277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15278         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15279         -1,
  15280         -1,
  15281     },
  15282 #endif /* chips */
  15283 
  15284 #if defined(BCM_88950_A0)
  15285     { /* SOC_REG_INT_BRDC_DCH_ECC_INTERRUPT_REGISTER_MASKr */
  15286         soc_block_list[106],
  15287         soc_genreg,
  15288         1,
  15289         0,
  15290         0x17,
  15291         SOC_REG_FLAG_WO,
  15292         0,
  15293         3,
  15294         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_MASKr_fields,
  15295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15296         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15297         -1,
  15298         -1,
  15299     },
  15300 #endif /* chips */
  15301 
  15302 #if defined(BCM_88790_A0)
  15303     { /* SOC_REG_INT_BRDC_DCH_ECC_INTERRUPT_REGISTER_MASK_BCM88790_A0r */
  15304         soc_block_list[106],
  15305         soc_genreg,
  15306         1,
  15307         0,
  15308         0x17,
  15309         SOC_REG_FLAG_WO,
  15310         0,
  15311         3,
  15312         soc_BRDC_DCH_ECC_INTERRUPT_REGISTER_MASKr_fields,
  15313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15314         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15315         -1,
  15316         -1,
  15317     },
  15318 #endif /* chips */
  15319 
  15320 #if defined(BCM_88950_A0)
  15321     { /* SOC_REG_INT_BRDC_DCH_ECC_INTERRUPT_REGISTER_TESTr */
  15322         soc_block_list[106],
  15323         soc_genreg,
  15324         1,
  15325         0,
  15326         0x1f,
  15327         SOC_REG_FLAG_WO,
  15328         0,
  15329         1,
  15330         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_TESTr_fields,
  15331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15333         -1,
  15334         -1,
  15335     },
  15336 #endif /* chips */
  15337 
  15338 #if defined(BCM_88790_A0)
  15339     { /* SOC_REG_INT_BRDC_DCH_ECC_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  15340         soc_block_list[106],
  15341         soc_genreg,
  15342         1,
  15343         0,
  15344         0x1f,
  15345         SOC_REG_FLAG_WO,
  15346         0,
  15347         1,
  15348         soc_BRDC_DCH_ECC_INTERRUPT_REGISTER_TESTr_fields,
  15349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15350         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15351         -1,
  15352         -1,
  15353     },
  15354 #endif /* chips */
  15355 
  15356 #if defined(BCM_88950_A0)
  15357     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTERr */
  15358         soc_block_list[106],
  15359         soc_genreg,
  15360         1,
  15361         0,
  15362         0x1c8,
  15363         SOC_REG_FLAG_ABOVE_64_BITS |
  15364                           SOC_REG_FLAG_WO,
  15365         0,
  15366         1,
  15367         soc_BRDC_DCH_ERROR_FILTERr_fields,
  15368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15369         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15370         -1,
  15371         -1,
  15372     },
  15373 #endif /* chips */
  15374 
  15375 #if defined(BCM_88950_A0)
  15376     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_2r */
  15377         soc_block_list[106],
  15378         soc_genreg,
  15379         1,
  15380         0,
  15381         0x1d2,
  15382         SOC_REG_FLAG_ABOVE_64_BITS |
  15383                           SOC_REG_FLAG_WO,
  15384         0,
  15385         1,
  15386         soc_BRDC_DCH_ERROR_FILTER_2r_fields,
  15387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15388         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15389         -1,
  15390         -1,
  15391     },
  15392 #endif /* chips */
  15393 
  15394 #if defined(BCM_88790_A0)
  15395     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_2_BCM88790_A0r */
  15396         soc_block_list[106],
  15397         soc_genreg,
  15398         1,
  15399         0,
  15400         0x1c3,
  15401         SOC_REG_FLAG_ABOVE_64_BITS |
  15402                           SOC_REG_FLAG_WO,
  15403         0,
  15404         1,
  15405         soc_BRDC_DCH_ERROR_FILTER_2_BCM88790_A0r_fields,
  15406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15407         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15408         -1,
  15409         -1,
  15410     },
  15411 #endif /* chips */
  15412 
  15413 #if defined(BCM_88790_A0)
  15414     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_BCM88790_A0r */
  15415         soc_block_list[106],
  15416         soc_genreg,
  15417         1,
  15418         0,
  15419         0x1b9,
  15420         SOC_REG_FLAG_ABOVE_64_BITS |
  15421                           SOC_REG_FLAG_WO,
  15422         0,
  15423         1,
  15424         soc_BRDC_DCH_ERROR_FILTER_BCM88790_A0r_fields,
  15425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15426         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15427         -1,
  15428         -1,
  15429     },
  15430 #endif /* chips */
  15431 
  15432 #if defined(BCM_88950_A0)
  15433     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_CNTr */
  15434         soc_block_list[106],
  15435         soc_genreg,
  15436         1,
  15437         0,
  15438         0x1b7,
  15439         SOC_REG_FLAG_RO |
  15440                           SOC_REG_FLAG_WO,
  15441         0,
  15442         2,
  15443         soc_BRDC_DCH_ERROR_FILTER_CNTr_fields,
  15444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15446         -1,
  15447         -1,
  15448     },
  15449 #endif /* chips */
  15450 
  15451 #if defined(BCM_88790_A0)
  15452     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_CNT_BCM88790_A0r */
  15453         soc_block_list[106],
  15454         soc_genreg,
  15455         1,
  15456         0,
  15457         0x1a1,
  15458         SOC_REG_FLAG_RO |
  15459                           SOC_REG_FLAG_WO,
  15460         SOC_REG_FLAG_COUNTER_FEILDS,
  15461         1,
  15462         soc_BRDC_DCH_ERROR_FILTER_CNT_BCM88790_A0r_fields,
  15463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15464         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15465         -1,
  15466         -1,
  15467     },
  15468 #endif /* chips */
  15469 
  15470 #if defined(BCM_88950_A0)
  15471     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_ENr */
  15472         soc_block_list[106],
  15473         soc_genreg,
  15474         1,
  15475         0,
  15476         0x1dc,
  15477         SOC_REG_FLAG_WO,
  15478         0,
  15479         2,
  15480         soc_BRDC_DCH_ERROR_FILTER_ENr_fields,
  15481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15482         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  15483         -1,
  15484         -1,
  15485     },
  15486 #endif /* chips */
  15487 
  15488 #if defined(BCM_88790_A0)
  15489     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_EN_BCM88790_A0r */
  15490         soc_block_list[106],
  15491         soc_genreg,
  15492         1,
  15493         0,
  15494         0x1cd,
  15495         SOC_REG_FLAG_WO,
  15496         0,
  15497         2,
  15498         soc_BRDC_DCH_ERROR_FILTER_EN_BCM88790_A0r_fields,
  15499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15500         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  15501         -1,
  15502         -1,
  15503     },
  15504 #endif /* chips */
  15505 
  15506 #if defined(BCM_88950_A0)
  15507     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_MASKr */
  15508         soc_block_list[106],
  15509         soc_genreg,
  15510         1,
  15511         0,
  15512         0x1cd,
  15513         SOC_REG_FLAG_ABOVE_64_BITS |
  15514                           SOC_REG_FLAG_WO,
  15515         0,
  15516         1,
  15517         soc_BRDC_DCH_ERROR_FILTER_MASKr_fields,
  15518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15519         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15520         -1,
  15521         -1,
  15522     },
  15523 #endif /* chips */
  15524 
  15525 #if defined(BCM_88950_A0)
  15526     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_MASK_2r */
  15527         soc_block_list[106],
  15528         soc_genreg,
  15529         1,
  15530         0,
  15531         0x1d7,
  15532         SOC_REG_FLAG_ABOVE_64_BITS |
  15533                           SOC_REG_FLAG_WO,
  15534         0,
  15535         1,
  15536         soc_BRDC_DCH_ERROR_FILTER_MASK_2r_fields,
  15537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15539         -1,
  15540         -1,
  15541     },
  15542 #endif /* chips */
  15543 
  15544 #if defined(BCM_88790_A0)
  15545     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_MASK_2_BCM88790_A0r */
  15546         soc_block_list[106],
  15547         soc_genreg,
  15548         1,
  15549         0,
  15550         0x1c8,
  15551         SOC_REG_FLAG_ABOVE_64_BITS |
  15552                           SOC_REG_FLAG_WO,
  15553         0,
  15554         1,
  15555         soc_BRDC_DCH_ERROR_FILTER_MASK_2_BCM88790_A0r_fields,
  15556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15557         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15558         -1,
  15559         -1,
  15560     },
  15561 #endif /* chips */
  15562 
  15563 #if defined(BCM_88790_A0)
  15564     { /* SOC_REG_INT_BRDC_DCH_ERROR_FILTER_MASK_BCM88790_A0r */
  15565         soc_block_list[106],
  15566         soc_genreg,
  15567         1,
  15568         0,
  15569         0x1be,
  15570         SOC_REG_FLAG_ABOVE_64_BITS |
  15571                           SOC_REG_FLAG_WO,
  15572         0,
  15573         1,
  15574         soc_BRDC_DCH_ERROR_FILTER_MASK_BCM88790_A0r_fields,
  15575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15576         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  15577         -1,
  15578         -1,
  15579     },
  15580 #endif /* chips */
  15581 
  15582 #if defined(BCM_88950_A0)
  15583     { /* SOC_REG_INT_BRDC_DCH_ERROR_INITIATION_DATAr */
  15584         soc_block_list[106],
  15585         soc_genreg,
  15586         1,
  15587         0,
  15588         0xa3,
  15589         SOC_REG_FLAG_WO,
  15590         0,
  15591         1,
  15592         soc_BRDC_CCS_ERROR_INITIATION_DATAr_fields,
  15593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15594         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  15595         -1,
  15596         -1,
  15597     },
  15598 #endif /* chips */
  15599 
  15600 #if defined(BCM_88790_A0)
  15601     { /* SOC_REG_INT_BRDC_DCH_ERROR_INITIATION_DATA_BCM88790_A0r */
  15602         soc_block_list[106],
  15603         soc_genreg,
  15604         1,
  15605         0,
  15606         0xa3,
  15607         SOC_REG_FLAG_WO,
  15608         0,
  15609         1,
  15610         soc_BRDC_DCH_ERROR_INITIATION_DATAr_fields,
  15611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15612         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  15613         -1,
  15614         -1,
  15615     },
  15616 #endif /* chips */
  15617 
  15618 #if defined(BCM_88790_A0)
  15619     { /* SOC_REG_INT_BRDC_DCH_FAP_GLOBAL_GENERAL_CFG_1r */
  15620         soc_block_list[106],
  15621         soc_genreg,
  15622         1,
  15623         0,
  15624         0xc3,
  15625         SOC_REG_FLAG_WO,
  15626         0,
  15627         2,
  15628         soc_BRDC_DCH_FAP_GLOBAL_GENERAL_CFG_1r_fields,
  15629         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  15630         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15631         -1,
  15632         -1,
  15633     },
  15634 #endif /* chips */
  15635 
  15636 #if defined(BCM_88790_A0)
  15637     { /* SOC_REG_INT_BRDC_DCH_FE_GLOBAL_GENERAL_CFG_1r */
  15638         soc_block_list[106],
  15639         soc_genreg,
  15640         1,
  15641         0,
  15642         0xf4,
  15643         SOC_REG_FLAG_WO,
  15644         0,
  15645         4,
  15646         soc_BRDC_DCH_FE_GLOBAL_GENERAL_CFG_1r_fields,
  15647         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  15648         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  15649         -1,
  15650         -1,
  15651     },
  15652 #endif /* chips */
  15653 
  15654 #if defined(BCM_88950_A0)
  15655     { /* SOC_REG_INT_BRDC_DCH_FIFOS_DEPTH_TYPEr */
  15656         soc_block_list[106],
  15657         soc_genreg,
  15658         2,
  15659         0,
  15660         0x10a,
  15661         SOC_REG_FLAG_ARRAY |
  15662                           SOC_REG_FLAG_WO |
  15663                           SOC_REG_FLAG_REG_ARRAY,
  15664         0,
  15665         3,
  15666         soc_BRDC_DCH_FIFOS_DEPTH_TYPEr_fields,
  15667         SOC_RESET_VAL_DEC(0x02010080, 0x00000000)
  15668         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  15669         -1,
  15670         -1,
  15671     },
  15672 #endif /* chips */
  15673 
  15674 #if defined(BCM_88790_A0)
  15675     { /* SOC_REG_INT_BRDC_DCH_FIFOS_DEPTH_TYPE_BCM88790_A0r */
  15676         soc_block_list[106],
  15677         soc_genreg,
  15678         2,
  15679         0,
  15680         0x10f,
  15681         SOC_REG_FLAG_ARRAY |
  15682                           SOC_REG_FLAG_WO |
  15683                           SOC_REG_FLAG_REG_ARRAY,
  15684         0,
  15685         3,
  15686         soc_BRDC_DCH_FIFOS_DEPTH_TYPE_BCM88790_A0r_fields,
  15687         SOC_RESET_VAL_DEC(0x10040100, 0x00000000)
  15688         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  15689         -1,
  15690         -1,
  15691     },
  15692 #endif /* chips */
  15693 
  15694 #if defined(BCM_88790_A0)
  15695     { /* SOC_REG_INT_BRDC_DCH_FIFO_DISCARD_CNT_Pr */
  15696         soc_block_list[106],
  15697         soc_genreg,
  15698         3,
  15699         0,
  15700         0x198,
  15701         SOC_REG_FLAG_ARRAY |
  15702                           SOC_REG_FLAG_RO |
  15703                           SOC_REG_FLAG_WO |
  15704                           SOC_REG_FLAG_REG_ARRAY,
  15705         SOC_REG_FLAG_COUNTER_FEILDS,
  15706         1,
  15707         soc_BRDC_DCH_FIFO_DISCARD_CNT_Pr_fields,
  15708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15710         -1,
  15711         -1,
  15712     },
  15713 #endif /* chips */
  15714 
  15715 #if defined(BCM_88950_A0)
  15716     { /* SOC_REG_INT_BRDC_DCH_FIFO_DISCARD_COUNTER_Pr */
  15717         soc_block_list[106],
  15718         soc_genreg,
  15719         3,
  15720         0,
  15721         0x1ae,
  15722         SOC_REG_FLAG_ARRAY |
  15723                           SOC_REG_FLAG_RO |
  15724                           SOC_REG_FLAG_WO |
  15725                           SOC_REG_FLAG_REG_ARRAY,
  15726         0,
  15727         2,
  15728         soc_BRDC_DCH_FIFO_DISCARD_COUNTER_Pr_fields,
  15729         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15730         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15731         -1,
  15732         -1,
  15733     },
  15734 #endif /* chips */
  15735 
  15736 #if defined(BCM_88950_A0)
  15737     { /* SOC_REG_INT_BRDC_DCH_FILTER_MATCH_INPUT_LINKr */
  15738         soc_block_list[106],
  15739         soc_genreg,
  15740         1,
  15741         0,
  15742         0x13a,
  15743         SOC_REG_FLAG_WO,
  15744         0,
  15745         3,
  15746         soc_BRDC_DCH_FILTER_MATCH_INPUT_LINKr_fields,
  15747         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15748         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  15749         -1,
  15750         -1,
  15751     },
  15752 #endif /* chips */
  15753 
  15754 #if defined(BCM_88790_A0)
  15755     { /* SOC_REG_INT_BRDC_DCH_FILTER_MATCH_INPUT_LINK_BCM88790_A0r */
  15756         soc_block_list[106],
  15757         soc_genreg,
  15758         1,
  15759         0,
  15760         0x13f,
  15761         SOC_REG_FLAG_WO,
  15762         0,
  15763         2,
  15764         soc_BRDC_DCH_FILTER_MATCH_INPUT_LINK_BCM88790_A0r_fields,
  15765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15766         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  15767         -1,
  15768         -1,
  15769     },
  15770 #endif /* chips */
  15771 
  15772 #if defined(BCM_88950_A0)
  15773     { /* SOC_REG_INT_BRDC_DCH_GEN_ERR_MEMr */
  15774         soc_block_list[106],
  15775         soc_genreg,
  15776         1,
  15777         0,
  15778         0x208,
  15779         SOC_REG_FLAG_WO,
  15780         0,
  15781         16,
  15782         soc_BRDC_DCH_GEN_ERR_MEMr_fields,
  15783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15784         SOC_RESET_MASK_DEC(0x003fffc0, 0x00000000)
  15785         -1,
  15786         -1,
  15787     },
  15788 #endif /* chips */
  15789 
  15790 #if defined(BCM_88790_A0)
  15791     { /* SOC_REG_INT_BRDC_DCH_GEN_ERR_MEM_BCM88790_A0r */
  15792         soc_block_list[106],
  15793         soc_genreg,
  15794         1,
  15795         0,
  15796         0x1f6,
  15797         SOC_REG_FLAG_WO,
  15798         0,
  15799         12,
  15800         soc_BRDC_DCH_GEN_ERR_MEM_BCM88790_A0r_fields,
  15801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15802         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  15803         -1,
  15804         -1,
  15805     },
  15806 #endif /* chips */
  15807 
  15808 #if defined(BCM_88950_A0)
  15809     { /* SOC_REG_INT_BRDC_DCH_GLOBAL_FE_DEST_IDS_1r */
  15810         soc_block_list[106],
  15811         soc_genreg,
  15812         1,
  15813         0,
  15814         0xf6,
  15815         SOC_REG_FLAG_WO,
  15816         0,
  15817         4,
  15818         soc_BRDC_DCH_GLOBAL_FE_DEST_IDS_1r_fields,
  15819         SOC_RESET_VAL_DEC(0x007fd7fc, 0x00000000)
  15820         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  15821         -1,
  15822         -1,
  15823     },
  15824 #endif /* chips */
  15825 
  15826 #if defined(BCM_88950_A0)
  15827     { /* SOC_REG_INT_BRDC_DCH_GLOBAL_FE_DEST_IDS_2r */
  15828         soc_block_list[106],
  15829         soc_genreg,
  15830         1,
  15831         0,
  15832         0xf7,
  15833         SOC_REG_FLAG_WO,
  15834         0,
  15835         4,
  15836         soc_BRDC_DCH_GLOBAL_FE_DEST_IDS_2r_fields,
  15837         SOC_RESET_VAL_DEC(0x007ff7fe, 0x00000000)
  15838         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  15839         -1,
  15840         -1,
  15841     },
  15842 #endif /* chips */
  15843 
  15844 #if defined(BCM_88950_A0)
  15845     { /* SOC_REG_INT_BRDC_DCH_GLOBAL_GENERAL_CFG_1r */
  15846         soc_block_list[106],
  15847         soc_genreg,
  15848         1,
  15849         0,
  15850         0xc1,
  15851         SOC_REG_FLAG_WO,
  15852         0,
  15853         3,
  15854         soc_BRDC_DCH_GLOBAL_GENERAL_CFG_1r_fields,
  15855         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  15856         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  15857         -1,
  15858         -1,
  15859     },
  15860 #endif /* chips */
  15861 
  15862 #if defined(BCM_88950_A0)
  15863     { /* SOC_REG_INT_BRDC_DCH_GLOBAL_GENERAL_FE_CFG_1r */
  15864         soc_block_list[106],
  15865         soc_genreg,
  15866         1,
  15867         0,
  15868         0xf4,
  15869         SOC_REG_FLAG_WO,
  15870         0,
  15871         8,
  15872         soc_BRDC_DCH_GLOBAL_GENERAL_FE_CFG_1r_fields,
  15873         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  15874         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  15875         -1,
  15876         -1,
  15877     },
  15878 #endif /* chips */
  15879 
  15880 #if defined(BCM_88950_A0)
  15881     { /* SOC_REG_INT_BRDC_DCH_GLOBAL_MEM_OPTIONSr */
  15882         soc_block_list[106],
  15883         soc_genreg,
  15884         1,
  15885         0,
  15886         0xc0,
  15887         SOC_REG_FLAG_WO,
  15888         0,
  15889         3,
  15890         soc_BRDC_DCH_GLOBAL_MEM_OPTIONSr_fields,
  15891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15892         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15893         -1,
  15894         -1,
  15895     },
  15896 #endif /* chips */
  15897 
  15898 #if defined(BCM_88790_A0)
  15899     { /* SOC_REG_INT_BRDC_DCH_GLOBAL_MEM_OPTIONS_BCM88790_A0r */
  15900         soc_block_list[106],
  15901         soc_genreg,
  15902         1,
  15903         0,
  15904         0xc2,
  15905         SOC_REG_FLAG_WO,
  15906         0,
  15907         6,
  15908         soc_BRDC_DCH_GLOBAL_MEM_OPTIONS_BCM88790_A0r_fields,
  15909         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  15910         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  15911         -1,
  15912         -1,
  15913     },
  15914 #endif /* chips */
  15915 
  15916 #if defined(BCM_88950_A0)
  15917     { /* SOC_REG_INT_BRDC_DCH_GTIMER_CONFIGURATIONr */
  15918         soc_block_list[106],
  15919         soc_genreg,
  15920         1,
  15921         0,
  15922         0x88,
  15923         SOC_REG_FLAG_WO,
  15924         0,
  15925         3,
  15926         soc_BRDC_CCS_GTIMER_CONFIGURATIONr_fields,
  15927         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  15928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15929         -1,
  15930         -1,
  15931     },
  15932 #endif /* chips */
  15933 
  15934 #if defined(BCM_88790_A0)
  15935     { /* SOC_REG_INT_BRDC_DCH_GTIMER_CONFIGURATION_BCM88790_A0r */
  15936         soc_block_list[106],
  15937         soc_genreg,
  15938         1,
  15939         0,
  15940         0x89,
  15941         SOC_REG_FLAG_WO,
  15942         0,
  15943         3,
  15944         soc_BRDC_DCH_GTIMER_CONFIGURATIONr_fields,
  15945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15946         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  15947         -1,
  15948         -1,
  15949     },
  15950 #endif /* chips */
  15951 
  15952 #if defined(BCM_88790_A0)
  15953     { /* SOC_REG_INT_BRDC_DCH_GTIMER_CYCLEr */
  15954         soc_block_list[106],
  15955         soc_genreg,
  15956         1,
  15957         0,
  15958         0x88,
  15959         SOC_REG_FLAG_WO,
  15960         0,
  15961         1,
  15962         soc_BRDC_DCH_GTIMER_CYCLEr_fields,
  15963         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  15964         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  15965         -1,
  15966         -1,
  15967     },
  15968 #endif /* chips */
  15969 
  15970 #if defined(BCM_88950_A0)
  15971     { /* SOC_REG_INT_BRDC_DCH_GTIMER_TRIGGERr */
  15972         soc_block_list[106],
  15973         soc_genreg,
  15974         1,
  15975         0,
  15976         0x89,
  15977         SOC_REG_FLAG_RO |
  15978                           SOC_REG_FLAG_WO,
  15979         0,
  15980         1,
  15981         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  15982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  15983         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  15984         -1,
  15985         -1,
  15986     },
  15987 #endif /* chips */
  15988 
  15989 #if defined(BCM_88950_A0)
  15990     { /* SOC_REG_INT_BRDC_DCH_IFM_MAX_OCCUP_P_0r */
  15991         soc_block_list[106],
  15992         soc_genreg,
  15993         1,
  15994         0,
  15995         0x190,
  15996         SOC_REG_FLAG_64_BITS |
  15997                           SOC_REG_FLAG_RO |
  15998                           SOC_REG_FLAG_WO,
  15999         0,
  16000         8,
  16001         soc_BRDC_DCH_IFM_MAX_OCCUP_P_0r_fields,
  16002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16003         SOC_RESET_MASK_DEC(0xffffffff, 0x000fffff)
  16004         -1,
  16005         -1,
  16006     },
  16007 #endif /* chips */
  16008 
  16009 #if defined(BCM_88950_A0)
  16010     { /* SOC_REG_INT_BRDC_DCH_IFM_MAX_OCCUP_P_1r */
  16011         soc_block_list[106],
  16012         soc_genreg,
  16013         1,
  16014         0,
  16015         0x192,
  16016         SOC_REG_FLAG_64_BITS |
  16017                           SOC_REG_FLAG_RO |
  16018                           SOC_REG_FLAG_WO,
  16019         0,
  16020         8,
  16021         soc_BRDC_DCH_IFM_MAX_OCCUP_P_1r_fields,
  16022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16023         SOC_RESET_MASK_DEC(0xffffffff, 0x000fffff)
  16024         -1,
  16025         -1,
  16026     },
  16027 #endif /* chips */
  16028 
  16029 #if defined(BCM_88950_A0)
  16030     { /* SOC_REG_INT_BRDC_DCH_IFM_MAX_OCCUP_P_2r */
  16031         soc_block_list[106],
  16032         soc_genreg,
  16033         1,
  16034         0,
  16035         0x194,
  16036         SOC_REG_FLAG_64_BITS |
  16037                           SOC_REG_FLAG_RO |
  16038                           SOC_REG_FLAG_WO,
  16039         0,
  16040         8,
  16041         soc_BRDC_DCH_IFM_MAX_OCCUP_P_2r_fields,
  16042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16043         SOC_RESET_MASK_DEC(0xffffffff, 0x000fffff)
  16044         -1,
  16045         -1,
  16046     },
  16047 #endif /* chips */
  16048 
  16049 #if defined(BCM_88790_A0)
  16050     { /* SOC_REG_INT_BRDC_DCH_IFM_MAX_OCCUP_P_0_BCM88790_A0r */
  16051         soc_block_list[106],
  16052         soc_genreg,
  16053         1,
  16054         0,
  16055         0x180,
  16056         SOC_REG_FLAG_64_BITS |
  16057                           SOC_REG_FLAG_RO |
  16058                           SOC_REG_FLAG_WO,
  16059         0,
  16060         6,
  16061         soc_BRDC_DCH_IFM_MAX_OCCUP_P_0_BCM88790_A0r_fields,
  16062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16063         SOC_RESET_MASK_DEC(0x73ff73ff, 0x000073ff)
  16064         -1,
  16065         -1,
  16066     },
  16067 #endif /* chips */
  16068 
  16069 #if defined(BCM_88790_A0)
  16070     { /* SOC_REG_INT_BRDC_DCH_IFM_MAX_OCCUP_P_1_BCM88790_A0r */
  16071         soc_block_list[106],
  16072         soc_genreg,
  16073         1,
  16074         0,
  16075         0x182,
  16076         SOC_REG_FLAG_64_BITS |
  16077                           SOC_REG_FLAG_RO |
  16078                           SOC_REG_FLAG_WO,
  16079         0,
  16080         6,
  16081         soc_BRDC_DCH_IFM_MAX_OCCUP_P_1_BCM88790_A0r_fields,
  16082         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16083         SOC_RESET_MASK_DEC(0x73ff73ff, 0x000073ff)
  16084         -1,
  16085         -1,
  16086     },
  16087 #endif /* chips */
  16088 
  16089 #if defined(BCM_88790_A0)
  16090     { /* SOC_REG_INT_BRDC_DCH_IFM_MAX_OCCUP_P_2_BCM88790_A0r */
  16091         soc_block_list[106],
  16092         soc_genreg,
  16093         1,
  16094         0,
  16095         0x184,
  16096         SOC_REG_FLAG_64_BITS |
  16097                           SOC_REG_FLAG_RO |
  16098                           SOC_REG_FLAG_WO,
  16099         0,
  16100         6,
  16101         soc_BRDC_DCH_IFM_MAX_OCCUP_P_2_BCM88790_A0r_fields,
  16102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16103         SOC_RESET_MASK_DEC(0x73ff73ff, 0x000073ff)
  16104         -1,
  16105         -1,
  16106     },
  16107 #endif /* chips */
  16108 
  16109 #if defined(BCM_88950_A0)
  16110     { /* SOC_REG_INT_BRDC_DCH_INTERRUPT_MASK_REGISTERr */
  16111         soc_block_list[106],
  16112         soc_genreg,
  16113         1,
  16114         0,
  16115         0x10,
  16116         SOC_REG_FLAG_WO,
  16117         0,
  16118         29,
  16119         soc_BRDC_DCH_INTERRUPT_MASK_REGISTERr_fields,
  16120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16121         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  16122         -1,
  16123         -1,
  16124     },
  16125 #endif /* chips */
  16126 
  16127 #if defined(BCM_88790_A0)
  16128     { /* SOC_REG_INT_BRDC_DCH_INTERRUPT_MASK_REGISTER_BCM88790_A0r */
  16129         soc_block_list[106],
  16130         soc_genreg,
  16131         1,
  16132         0,
  16133         0x10,
  16134         SOC_REG_FLAG_WO,
  16135         0,
  16136         30,
  16137         soc_BRDC_DCH_INTERRUPT_MASK_REGISTER_BCM88790_A0r_fields,
  16138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16139         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  16140         -1,
  16141         -1,
  16142     },
  16143 #endif /* chips */
  16144 
  16145 #if defined(BCM_88950_A0)
  16146     { /* SOC_REG_INT_BRDC_DCH_INTERRUPT_REGISTERr */
  16147         soc_block_list[106],
  16148         soc_genreg,
  16149         1,
  16150         0,
  16151         0,
  16152         SOC_REG_FLAG_WO |
  16153                           SOC_REG_FLAG_INTERRUPT,
  16154         0,
  16155         29,
  16156         soc_BRDC_DCH_INTERRUPT_REGISTERr_fields,
  16157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16158         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  16159         -1,
  16160         -1,
  16161     },
  16162 #endif /* chips */
  16163 
  16164 #if defined(BCM_88790_A0)
  16165     { /* SOC_REG_INT_BRDC_DCH_INTERRUPT_REGISTER_BCM88790_A0r */
  16166         soc_block_list[106],
  16167         soc_genreg,
  16168         1,
  16169         0,
  16170         0,
  16171         SOC_REG_FLAG_WO |
  16172                           SOC_REG_FLAG_INTERRUPT |
  16173                           SOC_REG_FLAG_SIGNAL,
  16174         0,
  16175         30,
  16176         soc_BRDC_DCH_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  16177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16178         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  16179         -1,
  16180         -1,
  16181     },
  16182 #endif /* chips */
  16183 
  16184 #if defined(BCM_88950_A0)
  16185     { /* SOC_REG_INT_BRDC_DCH_INTERRUPT_REGISTER_TESTr */
  16186         soc_block_list[106],
  16187         soc_genreg,
  16188         1,
  16189         0,
  16190         0x18,
  16191         SOC_REG_FLAG_WO,
  16192         0,
  16193         1,
  16194         soc_BRDC_CCS_INTERRUPT_REGISTER_TESTr_fields,
  16195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16197         -1,
  16198         -1,
  16199     },
  16200 #endif /* chips */
  16201 
  16202 #if defined(BCM_88790_A0)
  16203     { /* SOC_REG_INT_BRDC_DCH_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  16204         soc_block_list[106],
  16205         soc_genreg,
  16206         1,
  16207         0,
  16208         0x18,
  16209         SOC_REG_FLAG_WO,
  16210         0,
  16211         1,
  16212         soc_BRDC_DCH_INTERRUPT_REGISTER_TESTr_fields,
  16213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16214         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  16215         -1,
  16216         -1,
  16217     },
  16218 #endif /* chips */
  16219 
  16220 #if defined(BCM_88950_A0)
  16221     { /* SOC_REG_INT_BRDC_DCH_LINK_CELL_PACKING_ENr */
  16222         soc_block_list[106],
  16223         soc_genreg,
  16224         1,
  16225         0,
  16226         0x11c,
  16227         SOC_REG_FLAG_64_BITS |
  16228                           SOC_REG_FLAG_WO,
  16229         0,
  16230         1,
  16231         soc_BRDC_DCH_LINK_CELL_PACKING_ENr_fields,
  16232         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  16233         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  16234         -1,
  16235         -1,
  16236     },
  16237 #endif /* chips */
  16238 
  16239 #if defined(BCM_88790_A0)
  16240     { /* SOC_REG_INT_BRDC_DCH_LINK_CELL_PACKING_EN_BCM88790_A0r */
  16241         soc_block_list[106],
  16242         soc_genreg,
  16243         1,
  16244         0,
  16245         0x11d,
  16246         SOC_REG_FLAG_WO,
  16247         0,
  16248         1,
  16249         soc_BRDC_DCH_LINK_CELL_PACKING_EN_BCM88790_A0r_fields,
  16250         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  16251         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16252         -1,
  16253         -1,
  16254     },
  16255 #endif /* chips */
  16256 
  16257 #if defined(BCM_88950_A0)
  16258     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_BMPr */
  16259         soc_block_list[106],
  16260         soc_genreg,
  16261         1,
  16262         0,
  16263         0x1c6,
  16264         SOC_REG_FLAG_64_BITS |
  16265                           SOC_REG_FLAG_WO,
  16266         0,
  16267         1,
  16268         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_BMPr_fields,
  16269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16270         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  16271         -1,
  16272         -1,
  16273     },
  16274 #endif /* chips */
  16275 
  16276 #if defined(BCM_88790_A0)
  16277     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_BMP_BCM88790_A0r */
  16278         soc_block_list[106],
  16279         soc_genreg,
  16280         1,
  16281         0,
  16282         0x1b8,
  16283         SOC_REG_FLAG_WO,
  16284         0,
  16285         1,
  16286         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_BMP_BCM88790_A0r_fields,
  16287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16288         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16289         -1,
  16290         -1,
  16291     },
  16292 #endif /* chips */
  16293 
  16294 #if defined(BCM_88950_A0)
  16295     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_0r */
  16296         soc_block_list[106],
  16297         soc_genreg,
  16298         1,
  16299         0,
  16300         0x12e,
  16301         SOC_REG_FLAG_64_BITS |
  16302                           SOC_REG_FLAG_WO,
  16303         0,
  16304         5,
  16305         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_0r_fields,
  16306         SOC_RESET_VAL_DEC(0xe7ffffff, 0x00000011)
  16307         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  16308         -1,
  16309         -1,
  16310     },
  16311 #endif /* chips */
  16312 
  16313 #if defined(BCM_88950_A0)
  16314     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_1r */
  16315         soc_block_list[106],
  16316         soc_genreg,
  16317         1,
  16318         0,
  16319         0x130,
  16320         SOC_REG_FLAG_64_BITS |
  16321                           SOC_REG_FLAG_WO,
  16322         0,
  16323         5,
  16324         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_1r_fields,
  16325         SOC_RESET_VAL_DEC(0xe7ffffff, 0x00000011)
  16326         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  16327         -1,
  16328         -1,
  16329     },
  16330 #endif /* chips */
  16331 
  16332 #if defined(BCM_88950_A0)
  16333     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_2r */
  16334         soc_block_list[106],
  16335         soc_genreg,
  16336         1,
  16337         0,
  16338         0x132,
  16339         SOC_REG_FLAG_64_BITS |
  16340                           SOC_REG_FLAG_WO,
  16341         0,
  16342         5,
  16343         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_2r_fields,
  16344         SOC_RESET_VAL_DEC(0xe7ffffff, 0x00000011)
  16345         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  16346         -1,
  16347         -1,
  16348     },
  16349 #endif /* chips */
  16350 
  16351 #if defined(BCM_88790_A0)
  16352     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_0_BCM88790_A0r */
  16353         soc_block_list[106],
  16354         soc_genreg,
  16355         1,
  16356         0,
  16357         0x133,
  16358         SOC_REG_FLAG_64_BITS |
  16359                           SOC_REG_FLAG_WO,
  16360         0,
  16361         5,
  16362         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_0_BCM88790_A0r_fields,
  16363         SOC_RESET_VAL_DEC(0x00300300, 0x0043c300)
  16364         SOC_RESET_MASK_DEC(0x003ff3ff, 0x007ff3ff)
  16365         -1,
  16366         -1,
  16367     },
  16368 #endif /* chips */
  16369 
  16370 #if defined(BCM_88790_A0)
  16371     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_1_BCM88790_A0r */
  16372         soc_block_list[106],
  16373         soc_genreg,
  16374         1,
  16375         0,
  16376         0x135,
  16377         SOC_REG_FLAG_64_BITS |
  16378                           SOC_REG_FLAG_WO,
  16379         0,
  16380         5,
  16381         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_1_BCM88790_A0r_fields,
  16382         SOC_RESET_VAL_DEC(0x00300300, 0x0043c300)
  16383         SOC_RESET_MASK_DEC(0x003ff3ff, 0x007ff3ff)
  16384         -1,
  16385         -1,
  16386     },
  16387 #endif /* chips */
  16388 
  16389 #if defined(BCM_88790_A0)
  16390     { /* SOC_REG_INT_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_2_BCM88790_A0r */
  16391         soc_block_list[106],
  16392         soc_genreg,
  16393         1,
  16394         0,
  16395         0x137,
  16396         SOC_REG_FLAG_64_BITS |
  16397                           SOC_REG_FLAG_WO,
  16398         0,
  16399         5,
  16400         soc_BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_2_BCM88790_A0r_fields,
  16401         SOC_RESET_VAL_DEC(0x00300300, 0x0043c300)
  16402         SOC_RESET_MASK_DEC(0x003ff3ff, 0x007ff3ff)
  16403         -1,
  16404         -1,
  16405     },
  16406 #endif /* chips */
  16407 
  16408 #if defined(BCM_88950_A0)
  16409     { /* SOC_REG_INT_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_0r */
  16410         soc_block_list[106],
  16411         soc_genreg,
  16412         1,
  16413         0,
  16414         0x18a,
  16415         SOC_REG_FLAG_64_BITS |
  16416                           SOC_REG_FLAG_RO |
  16417                           SOC_REG_FLAG_WO,
  16418         0,
  16419         1,
  16420         soc_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_0r_fields,
  16421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16422         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  16423         -1,
  16424         -1,
  16425     },
  16426 #endif /* chips */
  16427 
  16428 #if defined(BCM_88950_A0)
  16429     { /* SOC_REG_INT_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_1r */
  16430         soc_block_list[106],
  16431         soc_genreg,
  16432         1,
  16433         0,
  16434         0x18c,
  16435         SOC_REG_FLAG_64_BITS |
  16436                           SOC_REG_FLAG_RO |
  16437                           SOC_REG_FLAG_WO,
  16438         0,
  16439         1,
  16440         soc_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_1r_fields,
  16441         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16442         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  16443         -1,
  16444         -1,
  16445     },
  16446 #endif /* chips */
  16447 
  16448 #if defined(BCM_88950_A0)
  16449     { /* SOC_REG_INT_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_2r */
  16450         soc_block_list[106],
  16451         soc_genreg,
  16452         1,
  16453         0,
  16454         0x18e,
  16455         SOC_REG_FLAG_64_BITS |
  16456                           SOC_REG_FLAG_RO |
  16457                           SOC_REG_FLAG_WO,
  16458         0,
  16459         1,
  16460         soc_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_2r_fields,
  16461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16462         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  16463         -1,
  16464         -1,
  16465     },
  16466 #endif /* chips */
  16467 
  16468 #if defined(BCM_88790_A0)
  16469     { /* SOC_REG_INT_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_0_BCM88790_A0r */
  16470         soc_block_list[106],
  16471         soc_genreg,
  16472         1,
  16473         0,
  16474         0x17d,
  16475         SOC_REG_FLAG_RO |
  16476                           SOC_REG_FLAG_WO,
  16477         0,
  16478         1,
  16479         soc_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_0_BCM88790_A0r_fields,
  16480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16481         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16482         -1,
  16483         -1,
  16484     },
  16485 #endif /* chips */
  16486 
  16487 #if defined(BCM_88790_A0)
  16488     { /* SOC_REG_INT_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_1_BCM88790_A0r */
  16489         soc_block_list[106],
  16490         soc_genreg,
  16491         1,
  16492         0,
  16493         0x17e,
  16494         SOC_REG_FLAG_RO |
  16495                           SOC_REG_FLAG_WO,
  16496         0,
  16497         1,
  16498         soc_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_1_BCM88790_A0r_fields,
  16499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16500         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16501         -1,
  16502         -1,
  16503     },
  16504 #endif /* chips */
  16505 
  16506 #if defined(BCM_88790_A0)
  16507     { /* SOC_REG_INT_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_2_BCM88790_A0r */
  16508         soc_block_list[106],
  16509         soc_genreg,
  16510         1,
  16511         0,
  16512         0x17f,
  16513         SOC_REG_FLAG_RO |
  16514                           SOC_REG_FLAG_WO,
  16515         0,
  16516         1,
  16517         soc_BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_2_BCM88790_A0r_fields,
  16518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16519         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16520         -1,
  16521         -1,
  16522     },
  16523 #endif /* chips */
  16524 
  16525 #if defined(BCM_88950_A0)
  16526     { /* SOC_REG_INT_BRDC_DCH_LOCAL_GCI_RCI_TYPE_0_Pr */
  16527         soc_block_list[106],
  16528         soc_genreg,
  16529         3,
  16530         0,
  16531         0x134,
  16532         SOC_REG_FLAG_ARRAY |
  16533                           SOC_REG_FLAG_WO |
  16534                           SOC_REG_FLAG_REG_ARRAY,
  16535         0,
  16536         4,
  16537         soc_BRDC_DCH_LOCAL_GCI_RCI_TYPE_0_Pr_fields,
  16538         SOC_RESET_VAL_DEC(0x0fffffff, 0x00000000)
  16539         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  16540         -1,
  16541         -1,
  16542     },
  16543 #endif /* chips */
  16544 
  16545 #if defined(BCM_88950_A0)
  16546     { /* SOC_REG_INT_BRDC_DCH_LOCAL_GCI_RCI_TYPE_1_Pr */
  16547         soc_block_list[106],
  16548         soc_genreg,
  16549         3,
  16550         0,
  16551         0x137,
  16552         SOC_REG_FLAG_ARRAY |
  16553                           SOC_REG_FLAG_WO |
  16554                           SOC_REG_FLAG_REG_ARRAY,
  16555         0,
  16556         3,
  16557         soc_BRDC_DCH_LOCAL_GCI_RCI_TYPE_1_Pr_fields,
  16558         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  16559         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  16560         -1,
  16561         -1,
  16562     },
  16563 #endif /* chips */
  16564 
  16565 #if defined(BCM_88790_A0)
  16566     { /* SOC_REG_INT_BRDC_DCH_LOCAL_GCI_TYPE_0_Pr */
  16567         soc_block_list[106],
  16568         soc_genreg,
  16569         3,
  16570         0,
  16571         0x139,
  16572         SOC_REG_FLAG_ARRAY |
  16573                           SOC_REG_FLAG_WO |
  16574                           SOC_REG_FLAG_REG_ARRAY,
  16575         0,
  16576         4,
  16577         soc_BRDC_DCH_LOCAL_GCI_TYPE_0_Pr_fields,
  16578         SOC_RESET_VAL_DEC(0x700c0300, 0x00000000)
  16579         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  16580         -1,
  16581         -1,
  16582     },
  16583 #endif /* chips */
  16584 
  16585 #if defined(BCM_88790_A0)
  16586     { /* SOC_REG_INT_BRDC_DCH_LOCAL_GCI_TYPE_1_Pr */
  16587         soc_block_list[106],
  16588         soc_genreg,
  16589         3,
  16590         0,
  16591         0x13c,
  16592         SOC_REG_FLAG_ARRAY |
  16593                           SOC_REG_FLAG_WO |
  16594                           SOC_REG_FLAG_REG_ARRAY,
  16595         0,
  16596         3,
  16597         soc_BRDC_DCH_LOCAL_GCI_TYPE_1_Pr_fields,
  16598         SOC_RESET_VAL_DEC(0x300c0300, 0x00000000)
  16599         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  16600         -1,
  16601         -1,
  16602     },
  16603 #endif /* chips */
  16604 
  16605 #if defined(BCM_88950_A0)
  16606     { /* SOC_REG_INT_BRDC_DCH_LOW_PR_MUL_0r */
  16607         soc_block_list[106],
  16608         soc_genreg,
  16609         1,
  16610         0,
  16611         0x1b3,
  16612         SOC_REG_FLAG_WO,
  16613         0,
  16614         1,
  16615         soc_BRDC_DCH_LOW_PR_MUL_0r_fields,
  16616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16617         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16618         -1,
  16619         -1,
  16620     },
  16621 #endif /* chips */
  16622 
  16623 #if defined(BCM_88950_A0)
  16624     { /* SOC_REG_INT_BRDC_DCH_LOW_PR_MUL_1r */
  16625         soc_block_list[106],
  16626         soc_genreg,
  16627         1,
  16628         0,
  16629         0x1b4,
  16630         SOC_REG_FLAG_WO,
  16631         0,
  16632         1,
  16633         soc_BRDC_DCH_LOW_PR_MUL_1r_fields,
  16634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16635         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16636         -1,
  16637         -1,
  16638     },
  16639 #endif /* chips */
  16640 
  16641 #if defined(BCM_88790_A0)
  16642     { /* SOC_REG_INT_BRDC_DCH_LOW_PR_MUL_0_BCM88790_A0r */
  16643         soc_block_list[106],
  16644         soc_genreg,
  16645         1,
  16646         0,
  16647         0x19d,
  16648         SOC_REG_FLAG_WO,
  16649         0,
  16650         1,
  16651         soc_BRDC_DCH_LOW_PR_MUL_0_BCM88790_A0r_fields,
  16652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16653         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16654         -1,
  16655         -1,
  16656     },
  16657 #endif /* chips */
  16658 
  16659 #if defined(BCM_88790_A0)
  16660     { /* SOC_REG_INT_BRDC_DCH_LOW_PR_MUL_1_BCM88790_A0r */
  16661         soc_block_list[106],
  16662         soc_genreg,
  16663         1,
  16664         0,
  16665         0x19e,
  16666         SOC_REG_FLAG_WO,
  16667         0,
  16668         1,
  16669         soc_BRDC_DCH_LOW_PR_MUL_1_BCM88790_A0r_fields,
  16670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16671         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16672         -1,
  16673         -1,
  16674     },
  16675 #endif /* chips */
  16676 
  16677 #if defined(BCM_88950_A0)
  16678     { /* SOC_REG_INT_BRDC_DCH_LP_PIPE_SHAPER_REGISTERr */
  16679         soc_block_list[106],
  16680         soc_genreg,
  16681         1,
  16682         0,
  16683         0x120,
  16684         SOC_REG_FLAG_WO,
  16685         0,
  16686         2,
  16687         soc_BRDC_DCH_LP_PIPE_SHAPER_REGISTERr_fields,
  16688         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  16689         SOC_RESET_MASK_DEC(0x000000f3, 0x00000000)
  16690         -1,
  16691         -1,
  16692     },
  16693 #endif /* chips */
  16694 
  16695 #if defined(BCM_88950_A0)
  16696     { /* SOC_REG_INT_BRDC_DCH_MATCH_FILTr */
  16697         soc_block_list[106],
  16698         soc_genreg,
  16699         1,
  16700         0,
  16701         0x124,
  16702         SOC_REG_FLAG_ABOVE_64_BITS |
  16703                           SOC_REG_FLAG_WO,
  16704         0,
  16705         1,
  16706         soc_BRDC_DCH_MATCH_FILTr_fields,
  16707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16708         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16709         -1,
  16710         -1,
  16711     },
  16712 #endif /* chips */
  16713 
  16714 #if defined(BCM_88790_A0)
  16715     { /* SOC_REG_INT_BRDC_DCH_MATCH_FILT_BCM88790_A0r */
  16716         soc_block_list[106],
  16717         soc_genreg,
  16718         1,
  16719         0,
  16720         0x129,
  16721         SOC_REG_FLAG_ABOVE_64_BITS |
  16722                           SOC_REG_FLAG_WO,
  16723         0,
  16724         1,
  16725         soc_BRDC_DCH_MATCH_FILT_BCM88790_A0r_fields,
  16726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16727         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16728         -1,
  16729         -1,
  16730     },
  16731 #endif /* chips */
  16732 
  16733 #if defined(BCM_88950_A0)
  16734     { /* SOC_REG_INT_BRDC_DCH_MATCH_FILT_MASKr */
  16735         soc_block_list[106],
  16736         soc_genreg,
  16737         1,
  16738         0,
  16739         0x129,
  16740         SOC_REG_FLAG_ABOVE_64_BITS |
  16741                           SOC_REG_FLAG_WO,
  16742         0,
  16743         1,
  16744         soc_BRDC_DCH_MATCH_FILT_MASKr_fields,
  16745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16746         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16747         -1,
  16748         -1,
  16749     },
  16750 #endif /* chips */
  16751 
  16752 #if defined(BCM_88790_A0)
  16753     { /* SOC_REG_INT_BRDC_DCH_MATCH_FILT_MASK_BCM88790_A0r */
  16754         soc_block_list[106],
  16755         soc_genreg,
  16756         1,
  16757         0,
  16758         0x12e,
  16759         SOC_REG_FLAG_ABOVE_64_BITS |
  16760                           SOC_REG_FLAG_WO,
  16761         0,
  16762         1,
  16763         soc_BRDC_DCH_MATCH_FILT_MASK_BCM88790_A0r_fields,
  16764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16765         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  16766         -1,
  16767         -1,
  16768     },
  16769 #endif /* chips */
  16770 
  16771 #if defined(BCM_88950_A0)
  16772     { /* SOC_REG_INT_BRDC_DCH_MC_EST_NOF_REPr */
  16773         soc_block_list[106],
  16774         soc_genreg,
  16775         1,
  16776         0,
  16777         0x11e,
  16778         SOC_REG_FLAG_WO,
  16779         0,
  16780         3,
  16781         soc_BRDC_DCH_MC_EST_NOF_REPr_fields,
  16782         SOC_RESET_VAL_DEC(0x00040404, 0x00000000)
  16783         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16784         -1,
  16785         -1,
  16786     },
  16787 #endif /* chips */
  16788 
  16789 #if defined(BCM_88790_A0)
  16790     { /* SOC_REG_INT_BRDC_DCH_MC_EST_NOF_REP_BCM88790_A0r */
  16791         soc_block_list[106],
  16792         soc_genreg,
  16793         1,
  16794         0,
  16795         0x11e,
  16796         SOC_REG_FLAG_WO,
  16797         0,
  16798         3,
  16799         soc_BRDC_DCH_MC_EST_NOF_REP_BCM88790_A0r_fields,
  16800         SOC_RESET_VAL_DEC(0x00080808, 0x00000000)
  16801         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  16802         -1,
  16803         -1,
  16804     },
  16805 #endif /* chips */
  16806 
  16807 #if defined(BCM_88950_A0)
  16808     { /* SOC_REG_INT_BRDC_DCH_MID_PR_MUL_0r */
  16809         soc_block_list[106],
  16810         soc_genreg,
  16811         1,
  16812         0,
  16813         0x1b5,
  16814         SOC_REG_FLAG_WO,
  16815         0,
  16816         1,
  16817         soc_BRDC_DCH_MID_PR_MUL_0r_fields,
  16818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16819         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16820         -1,
  16821         -1,
  16822     },
  16823 #endif /* chips */
  16824 
  16825 #if defined(BCM_88950_A0)
  16826     { /* SOC_REG_INT_BRDC_DCH_MID_PR_MUL_1r */
  16827         soc_block_list[106],
  16828         soc_genreg,
  16829         1,
  16830         0,
  16831         0x1b6,
  16832         SOC_REG_FLAG_WO,
  16833         0,
  16834         1,
  16835         soc_BRDC_DCH_MID_PR_MUL_1r_fields,
  16836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16837         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16838         -1,
  16839         -1,
  16840     },
  16841 #endif /* chips */
  16842 
  16843 #if defined(BCM_88790_A0)
  16844     { /* SOC_REG_INT_BRDC_DCH_MID_PR_MUL_0_BCM88790_A0r */
  16845         soc_block_list[106],
  16846         soc_genreg,
  16847         1,
  16848         0,
  16849         0x19f,
  16850         SOC_REG_FLAG_WO,
  16851         0,
  16852         1,
  16853         soc_BRDC_DCH_MID_PR_MUL_0_BCM88790_A0r_fields,
  16854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16855         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16856         -1,
  16857         -1,
  16858     },
  16859 #endif /* chips */
  16860 
  16861 #if defined(BCM_88790_A0)
  16862     { /* SOC_REG_INT_BRDC_DCH_MID_PR_MUL_1_BCM88790_A0r */
  16863         soc_block_list[106],
  16864         soc_genreg,
  16865         1,
  16866         0,
  16867         0x1a0,
  16868         SOC_REG_FLAG_WO,
  16869         0,
  16870         1,
  16871         soc_BRDC_DCH_MID_PR_MUL_1_BCM88790_A0r_fields,
  16872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16873         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  16874         -1,
  16875         -1,
  16876     },
  16877 #endif /* chips */
  16878 
  16879 #if defined(BCM_88790_A0)
  16880     { /* SOC_REG_INT_BRDC_DCH_PCMI_0r */
  16881         soc_block_list[106],
  16882         soc_genreg,
  16883         1,
  16884         0,
  16885         0xb0,
  16886         SOC_REG_FLAG_WO,
  16887         0,
  16888         1,
  16889         soc_BRDC_DCH_PCMI_0r_fields,
  16890         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  16891         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16892         -1,
  16893         -1,
  16894     },
  16895 #endif /* chips */
  16896 
  16897 #if defined(BCM_88790_A0)
  16898     { /* SOC_REG_INT_BRDC_DCH_PCMI_1r */
  16899         soc_block_list[106],
  16900         soc_genreg,
  16901         1,
  16902         0,
  16903         0xb3,
  16904         SOC_REG_FLAG_WO,
  16905         0,
  16906         1,
  16907         soc_BRDC_DCH_PCMI_1r_fields,
  16908         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  16909         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16910         -1,
  16911         -1,
  16912     },
  16913 #endif /* chips */
  16914 
  16915 #if defined(BCM_88790_A0)
  16916     { /* SOC_REG_INT_BRDC_DCH_PCMI_2r */
  16917         soc_block_list[106],
  16918         soc_genreg,
  16919         1,
  16920         0,
  16921         0xb6,
  16922         SOC_REG_FLAG_WO,
  16923         0,
  16924         1,
  16925         soc_BRDC_DCH_PCMI_2r_fields,
  16926         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  16927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16928         -1,
  16929         -1,
  16930     },
  16931 #endif /* chips */
  16932 
  16933 #if defined(BCM_88790_A0)
  16934     { /* SOC_REG_INT_BRDC_DCH_PCMI_3r */
  16935         soc_block_list[106],
  16936         soc_genreg,
  16937         1,
  16938         0,
  16939         0xb9,
  16940         SOC_REG_FLAG_WO,
  16941         0,
  16942         1,
  16943         soc_BRDC_DCH_PCMI_3r_fields,
  16944         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  16945         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16946         -1,
  16947         -1,
  16948     },
  16949 #endif /* chips */
  16950 
  16951 #if defined(BCM_88790_A0)
  16952     { /* SOC_REG_INT_BRDC_DCH_PCMI_0_Sr */
  16953         soc_block_list[106],
  16954         soc_genreg,
  16955         1,
  16956         0,
  16957         0xb1,
  16958         SOC_REG_FLAG_RO |
  16959                           SOC_REG_FLAG_WO,
  16960         0,
  16961         3,
  16962         soc_BRDC_DCH_PCMI_0_Sr_fields,
  16963         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16964         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  16965         -1,
  16966         -1,
  16967     },
  16968 #endif /* chips */
  16969 
  16970 #if defined(BCM_88790_A0)
  16971     { /* SOC_REG_INT_BRDC_DCH_PCMI_0_Tr */
  16972         soc_block_list[106],
  16973         soc_genreg,
  16974         1,
  16975         0,
  16976         0xb2,
  16977         SOC_REG_FLAG_WO,
  16978         0,
  16979         2,
  16980         soc_BRDC_DCH_PCMI_0_Tr_fields,
  16981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  16982         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  16983         -1,
  16984         -1,
  16985     },
  16986 #endif /* chips */
  16987 
  16988 #if defined(BCM_88790_A0)
  16989     { /* SOC_REG_INT_BRDC_DCH_PCMI_1_Sr */
  16990         soc_block_list[106],
  16991         soc_genreg,
  16992         1,
  16993         0,
  16994         0xb4,
  16995         SOC_REG_FLAG_RO |
  16996                           SOC_REG_FLAG_WO,
  16997         0,
  16998         3,
  16999         soc_BRDC_DCH_PCMI_1_Sr_fields,
  17000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17001         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17002         -1,
  17003         -1,
  17004     },
  17005 #endif /* chips */
  17006 
  17007 #if defined(BCM_88790_A0)
  17008     { /* SOC_REG_INT_BRDC_DCH_PCMI_1_Tr */
  17009         soc_block_list[106],
  17010         soc_genreg,
  17011         1,
  17012         0,
  17013         0xb5,
  17014         SOC_REG_FLAG_WO,
  17015         0,
  17016         2,
  17017         soc_BRDC_DCH_PCMI_1_Tr_fields,
  17018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17019         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  17020         -1,
  17021         -1,
  17022     },
  17023 #endif /* chips */
  17024 
  17025 #if defined(BCM_88790_A0)
  17026     { /* SOC_REG_INT_BRDC_DCH_PCMI_2_Sr */
  17027         soc_block_list[106],
  17028         soc_genreg,
  17029         1,
  17030         0,
  17031         0xb7,
  17032         SOC_REG_FLAG_RO |
  17033                           SOC_REG_FLAG_WO,
  17034         0,
  17035         3,
  17036         soc_BRDC_DCH_PCMI_2_Sr_fields,
  17037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17039         -1,
  17040         -1,
  17041     },
  17042 #endif /* chips */
  17043 
  17044 #if defined(BCM_88790_A0)
  17045     { /* SOC_REG_INT_BRDC_DCH_PCMI_2_Tr */
  17046         soc_block_list[106],
  17047         soc_genreg,
  17048         1,
  17049         0,
  17050         0xb8,
  17051         SOC_REG_FLAG_WO,
  17052         0,
  17053         2,
  17054         soc_BRDC_DCH_PCMI_2_Tr_fields,
  17055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17056         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  17057         -1,
  17058         -1,
  17059     },
  17060 #endif /* chips */
  17061 
  17062 #if defined(BCM_88790_A0)
  17063     { /* SOC_REG_INT_BRDC_DCH_PCMI_3_Sr */
  17064         soc_block_list[106],
  17065         soc_genreg,
  17066         1,
  17067         0,
  17068         0xba,
  17069         SOC_REG_FLAG_RO |
  17070                           SOC_REG_FLAG_WO,
  17071         0,
  17072         3,
  17073         soc_BRDC_DCH_PCMI_3_Sr_fields,
  17074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17075         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17076         -1,
  17077         -1,
  17078     },
  17079 #endif /* chips */
  17080 
  17081 #if defined(BCM_88790_A0)
  17082     { /* SOC_REG_INT_BRDC_DCH_PCMI_3_Tr */
  17083         soc_block_list[106],
  17084         soc_genreg,
  17085         1,
  17086         0,
  17087         0xbb,
  17088         SOC_REG_FLAG_WO,
  17089         0,
  17090         2,
  17091         soc_BRDC_DCH_PCMI_3_Tr_fields,
  17092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17093         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  17094         -1,
  17095         -1,
  17096     },
  17097 #endif /* chips */
  17098 
  17099 #if defined(BCM_88790_A0)
  17100     { /* SOC_REG_INT_BRDC_DCH_PIPES_MAPPING_ENr */
  17101         soc_block_list[106],
  17102         soc_genreg,
  17103         1,
  17104         0,
  17105         0x111,
  17106         SOC_REG_FLAG_WO,
  17107         0,
  17108         1,
  17109         soc_BRDC_DCH_PIPES_MAPPING_ENr_fields,
  17110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17111         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  17112         -1,
  17113         -1,
  17114     },
  17115 #endif /* chips */
  17116 
  17117 #if defined(BCM_88950_A0)
  17118     { /* SOC_REG_INT_BRDC_DCH_PIPES_MAP_ENr */
  17119         soc_block_list[106],
  17120         soc_genreg,
  17121         1,
  17122         0,
  17123         0x10c,
  17124         SOC_REG_FLAG_64_BITS |
  17125                           SOC_REG_FLAG_WO,
  17126         0,
  17127         1,
  17128         soc_BRDC_DCH_PIPES_MAP_ENr_fields,
  17129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17130         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  17131         -1,
  17132         -1,
  17133     },
  17134 #endif /* chips */
  17135 
  17136 #if defined(BCM_88950_A0)
  17137     { /* SOC_REG_INT_BRDC_DCH_PIPES_SEPARATION_REGISTERr */
  17138         soc_block_list[106],
  17139         soc_genreg,
  17140         1,
  17141         0,
  17142         0x11f,
  17143         SOC_REG_FLAG_WO,
  17144         0,
  17145         9,
  17146         soc_BRDC_DCH_PIPES_SEPARATION_REGISTERr_fields,
  17147         SOC_RESET_VAL_DEC(0x00008095, 0x00000000)
  17148         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  17149         -1,
  17150         -1,
  17151     },
  17152 #endif /* chips */
  17153 
  17154 #if defined(BCM_88790_A0)
  17155     { /* SOC_REG_INT_BRDC_DCH_PIPES_SEPARATION_REGISTER_BCM88790_A0r */
  17156         soc_block_list[106],
  17157         soc_genreg,
  17158         1,
  17159         0,
  17160         0x11f,
  17161         SOC_REG_FLAG_WO,
  17162         0,
  17163         15,
  17164         soc_BRDC_DCH_PIPES_SEPARATION_REGISTER_BCM88790_A0r_fields,
  17165         SOC_RESET_VAL_DEC(0x06208095, 0x00000000)
  17166         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  17167         -1,
  17168         -1,
  17169     },
  17170 #endif /* chips */
  17171 
  17172 #if defined(BCM_88790_A0)
  17173     { /* SOC_REG_INT_BRDC_DCH_PIPES_WEIGHTS_COUNTER_PNr */
  17174         soc_block_list[106],
  17175         soc_genreg,
  17176         3,
  17177         0,
  17178         0x124,
  17179         SOC_REG_FLAG_ARRAY |
  17180                           SOC_REG_FLAG_RO |
  17181                           SOC_REG_FLAG_WO |
  17182                           SOC_REG_FLAG_REG_ARRAY,
  17183         0,
  17184         1,
  17185         soc_BRDC_DCH_PIPES_WEIGHTS_COUNTER_PNr_fields,
  17186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17187         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  17188         -1,
  17189         -1,
  17190     },
  17191 #endif /* chips */
  17192 
  17193 #if defined(BCM_88950_A0)
  17194     { /* SOC_REG_INT_BRDC_DCH_PIPES_WEIGHTS_REGISTERr */
  17195         soc_block_list[106],
  17196         soc_genreg,
  17197         1,
  17198         0,
  17199         0x121,
  17200         SOC_REG_FLAG_WO,
  17201         0,
  17202         4,
  17203         soc_BRDC_DCH_PIPES_WEIGHTS_REGISTERr_fields,
  17204         SOC_RESET_VAL_DEC(0x00004081, 0x00000000)
  17205         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  17206         -1,
  17207         -1,
  17208     },
  17209 #endif /* chips */
  17210 
  17211 #if defined(BCM_88790_A0)
  17212     { /* SOC_REG_INT_BRDC_DCH_PIPES_WEIGHTS_REGISTER_2r */
  17213         soc_block_list[106],
  17214         soc_genreg,
  17215         1,
  17216         0,
  17217         0x122,
  17218         SOC_REG_FLAG_WO,
  17219         0,
  17220         1,
  17221         soc_BRDC_DCH_PIPES_WEIGHTS_REGISTER_2r_fields,
  17222         SOC_RESET_VAL_DEC(0x1fffffff, 0x00000000)
  17223         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  17224         -1,
  17225         -1,
  17226     },
  17227 #endif /* chips */
  17228 
  17229 #if defined(BCM_88790_A0)
  17230     { /* SOC_REG_INT_BRDC_DCH_PIPES_WEIGHTS_REGISTER_3r */
  17231         soc_block_list[106],
  17232         soc_genreg,
  17233         1,
  17234         0,
  17235         0x123,
  17236         SOC_REG_FLAG_WO,
  17237         0,
  17238         1,
  17239         soc_BRDC_DCH_PIPES_WEIGHTS_REGISTER_3r_fields,
  17240         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  17241         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  17242         -1,
  17243         -1,
  17244     },
  17245 #endif /* chips */
  17246 
  17247 #if defined(BCM_88790_A0)
  17248     { /* SOC_REG_INT_BRDC_DCH_PIPES_WEIGHTS_REGISTER_BCM88790_A0r */
  17249         soc_block_list[106],
  17250         soc_genreg,
  17251         1,
  17252         0,
  17253         0x121,
  17254         SOC_REG_FLAG_WO,
  17255         0,
  17256         7,
  17257         soc_BRDC_DCH_PIPES_WEIGHTS_REGISTER_BCM88790_A0r_fields,
  17258         SOC_RESET_VAL_DEC(0x18010101, 0x00000000)
  17259         SOC_RESET_MASK_DEC(0x3f7f7f7f, 0x00000000)
  17260         -1,
  17261         -1,
  17262     },
  17263 #endif /* chips */
  17264 
  17265 #if defined(BCM_88790_A0)
  17266     { /* SOC_REG_INT_BRDC_DCH_PRG_CELL_CNT_0r */
  17267         soc_block_list[106],
  17268         soc_genreg,
  17269         1,
  17270         0,
  17271         0x140,
  17272         SOC_REG_FLAG_RO |
  17273                           SOC_REG_FLAG_WO,
  17274         SOC_REG_FLAG_COUNTER_FEILDS,
  17275         1,
  17276         soc_BRDC_DCH_PRG_CELL_CNT_0r_fields,
  17277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17278         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17279         -1,
  17280         -1,
  17281     },
  17282 #endif /* chips */
  17283 
  17284 #if defined(BCM_88790_A0)
  17285     { /* SOC_REG_INT_BRDC_DCH_PRG_CELL_CNT_1r */
  17286         soc_block_list[106],
  17287         soc_genreg,
  17288         1,
  17289         0,
  17290         0x141,
  17291         SOC_REG_FLAG_RO |
  17292                           SOC_REG_FLAG_WO,
  17293         SOC_REG_FLAG_COUNTER_FEILDS,
  17294         1,
  17295         soc_BRDC_DCH_PRG_CELL_CNT_1r_fields,
  17296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17298         -1,
  17299         -1,
  17300     },
  17301 #endif /* chips */
  17302 
  17303 #if defined(BCM_88790_A0)
  17304     { /* SOC_REG_INT_BRDC_DCH_PRG_CELL_CNT_2r */
  17305         soc_block_list[106],
  17306         soc_genreg,
  17307         1,
  17308         0,
  17309         0x142,
  17310         SOC_REG_FLAG_RO |
  17311                           SOC_REG_FLAG_WO,
  17312         SOC_REG_FLAG_COUNTER_FEILDS,
  17313         1,
  17314         soc_BRDC_DCH_PRG_CELL_CNT_2r_fields,
  17315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17316         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17317         -1,
  17318         -1,
  17319     },
  17320 #endif /* chips */
  17321 
  17322 #if defined(BCM_88950_A0)
  17323     { /* SOC_REG_INT_BRDC_DCH_PRIORITY_TRANSLATIONr */
  17324         soc_block_list[106],
  17325         soc_genreg,
  17326         1,
  17327         0,
  17328         0x100,
  17329         SOC_REG_FLAG_WO,
  17330         0,
  17331         6,
  17332         soc_BRDC_DCH_PRIORITY_TRANSLATIONr_fields,
  17333         SOC_RESET_VAL_DEC(0x00000398, 0x00000000)
  17334         SOC_RESET_MASK_DEC(0x000003fe, 0x00000000)
  17335         -1,
  17336         -1,
  17337     },
  17338 #endif /* chips */
  17339 
  17340 #if defined(BCM_88790_A0)
  17341     { /* SOC_REG_INT_BRDC_DCH_PRIORITY_TRANSLATION_BCM88790_A0r */
  17342         soc_block_list[106],
  17343         soc_genreg,
  17344         1,
  17345         0,
  17346         0x100,
  17347         SOC_REG_FLAG_WO,
  17348         0,
  17349         3,
  17350         soc_BRDC_DCH_PRIORITY_TRANSLATION_BCM88790_A0r_fields,
  17351         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  17352         SOC_RESET_MASK_DEC(0x0000000e, 0x00000000)
  17353         -1,
  17354         -1,
  17355     },
  17356 #endif /* chips */
  17357 
  17358 #if defined(BCM_88950_A0)
  17359     { /* SOC_REG_INT_BRDC_DCH_PROGRAMMABLE_CELLS_COUNTER_1r */
  17360         soc_block_list[106],
  17361         soc_genreg,
  17362         1,
  17363         0,
  17364         0x13b,
  17365         SOC_REG_FLAG_RO |
  17366                           SOC_REG_FLAG_WO,
  17367         0,
  17368         4,
  17369         soc_BRDC_DCH_PROGRAMMABLE_CELLS_COUNTER_1r_fields,
  17370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17371         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17372         -1,
  17373         -1,
  17374     },
  17375 #endif /* chips */
  17376 
  17377 #if defined(BCM_88950_A0)
  17378     { /* SOC_REG_INT_BRDC_DCH_PROGRAMMABLE_CELLS_COUNTER_2r */
  17379         soc_block_list[106],
  17380         soc_genreg,
  17381         1,
  17382         0,
  17383         0x13c,
  17384         SOC_REG_FLAG_RO |
  17385                           SOC_REG_FLAG_WO,
  17386         0,
  17387         4,
  17388         soc_BRDC_DCH_PROGRAMMABLE_CELLS_COUNTER_2r_fields,
  17389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17390         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17391         -1,
  17392         -1,
  17393     },
  17394 #endif /* chips */
  17395 
  17396 #if defined(BCM_88790_A0)
  17397     { /* SOC_REG_INT_BRDC_DCH_RATE_LIMITERr */
  17398         soc_block_list[106],
  17399         soc_genreg,
  17400         1,
  17401         0,
  17402         0x120,
  17403         SOC_REG_FLAG_WO,
  17404         0,
  17405         2,
  17406         soc_BRDC_DCH_RATE_LIMITERr_fields,
  17407         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  17408         SOC_RESET_MASK_DEC(0x000000f3, 0x00000000)
  17409         -1,
  17410         -1,
  17411     },
  17412 #endif /* chips */
  17413 
  17414 #if defined(BCM_88950_A0)
  17415     { /* SOC_REG_INT_BRDC_DCH_REG_0103r */
  17416         soc_block_list[106],
  17417         soc_genreg,
  17418         1,
  17419         0,
  17420         0x103,
  17421         SOC_REG_FLAG_WO,
  17422         0,
  17423         2,
  17424         soc_BRDC_DCH_REG_0103r_fields,
  17425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17426         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  17427         -1,
  17428         -1,
  17429     },
  17430 #endif /* chips */
  17431 
  17432 #if defined(BCM_88950_A0)
  17433     { /* SOC_REG_INT_BRDC_DCH_REG_0107r */
  17434         soc_block_list[106],
  17435         soc_genreg,
  17436         1,
  17437         0,
  17438         0x107,
  17439         SOC_REG_FLAG_WO,
  17440         0,
  17441         1,
  17442         soc_BRDC_DCH_REG_0107r_fields,
  17443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17444         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  17445         -1,
  17446         -1,
  17447     },
  17448 #endif /* chips */
  17449 
  17450 #if defined(BCM_88950_A0)
  17451     { /* SOC_REG_INT_BRDC_DCH_REG_0108r */
  17452         soc_block_list[106],
  17453         soc_genreg,
  17454         1,
  17455         0,
  17456         0x108,
  17457         SOC_REG_FLAG_WO,
  17458         0,
  17459         1,
  17460         soc_BRDC_DCH_REG_0108r_fields,
  17461         SOC_RESET_VAL_DEC(0x0007ffff, 0x00000000)
  17462         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  17463         -1,
  17464         -1,
  17465     },
  17466 #endif /* chips */
  17467 
  17468 #if defined(BCM_88950_A0)
  17469     { /* SOC_REG_INT_BRDC_DCH_REG_0114r */
  17470         soc_block_list[106],
  17471         soc_genreg,
  17472         1,
  17473         0,
  17474         0x114,
  17475         SOC_REG_FLAG_64_BITS |
  17476                           SOC_REG_FLAG_WO,
  17477         0,
  17478         1,
  17479         soc_BRDC_DCH_REG_0114r_fields,
  17480         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  17481         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  17482         -1,
  17483         -1,
  17484     },
  17485 #endif /* chips */
  17486 
  17487 #if defined(BCM_88950_A0)
  17488     { /* SOC_REG_INT_BRDC_DCH_REG_0116r */
  17489         soc_block_list[106],
  17490         soc_genreg,
  17491         3,
  17492         0,
  17493         0x116,
  17494         SOC_REG_FLAG_64_BITS |
  17495                           SOC_REG_FLAG_ARRAY |
  17496                           SOC_REG_FLAG_WO |
  17497                           SOC_REG_FLAG_REG_ARRAY,
  17498         0,
  17499         1,
  17500         soc_BRDC_DCH_REG_0116r_fields,
  17501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17502         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  17503         -1,
  17504         -1,
  17505     },
  17506 #endif /* chips */
  17507 
  17508 #if defined(BCM_88950_A0)
  17509     { /* SOC_REG_INT_BRDC_DCH_REG_0196r */
  17510         soc_block_list[106],
  17511         soc_genreg,
  17512         3,
  17513         0,
  17514         0x196,
  17515         SOC_REG_FLAG_64_BITS |
  17516                           SOC_REG_FLAG_ARRAY |
  17517                           SOC_REG_FLAG_RO |
  17518                           SOC_REG_FLAG_WO |
  17519                           SOC_REG_FLAG_REG_ARRAY,
  17520         0,
  17521         1,
  17522         soc_BRDC_DCH_REG_0196r_fields,
  17523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17524         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  17525         -1,
  17526         -1,
  17527     },
  17528 #endif /* chips */
  17529 
  17530 #if defined(BCM_88950_A0)
  17531     { /* SOC_REG_INT_BRDC_DCH_REG_0210r */
  17532         soc_block_list[106],
  17533         soc_genreg,
  17534         1,
  17535         0,
  17536         0x210,
  17537         SOC_REG_FLAG_64_BITS |
  17538                           SOC_REG_FLAG_RO |
  17539                           SOC_REG_FLAG_WO,
  17540         0,
  17541         1,
  17542         soc_BRDC_DCH_REG_0210r_fields,
  17543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17544         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  17545         -1,
  17546         -1,
  17547     },
  17548 #endif /* chips */
  17549 
  17550 #if defined(BCM_88950_A0)
  17551     { /* SOC_REG_INT_BRDC_DCH_REG_0212r */
  17552         soc_block_list[106],
  17553         soc_genreg,
  17554         1,
  17555         0,
  17556         0x212,
  17557         SOC_REG_FLAG_64_BITS |
  17558                           SOC_REG_FLAG_RO |
  17559                           SOC_REG_FLAG_WO,
  17560         0,
  17561         1,
  17562         soc_BRDC_DCH_REG_0210r_fields,
  17563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17564         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  17565         -1,
  17566         -1,
  17567     },
  17568 #endif /* chips */
  17569 
  17570 #if defined(BCM_88950_A0)
  17571     { /* SOC_REG_INT_BRDC_DCH_REG_0214r */
  17572         soc_block_list[106],
  17573         soc_genreg,
  17574         1,
  17575         0,
  17576         0x214,
  17577         SOC_REG_FLAG_64_BITS |
  17578                           SOC_REG_FLAG_RO |
  17579                           SOC_REG_FLAG_WO,
  17580         0,
  17581         1,
  17582         soc_BRDC_DCH_REG_0210r_fields,
  17583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17584         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  17585         -1,
  17586         -1,
  17587     },
  17588 #endif /* chips */
  17589 
  17590 #if defined(BCM_88950_A0)
  17591     { /* SOC_REG_INT_BRDC_DCH_REG_019Cr */
  17592         soc_block_list[106],
  17593         soc_genreg,
  17594         3,
  17595         0,
  17596         0x19c,
  17597         SOC_REG_FLAG_64_BITS |
  17598                           SOC_REG_FLAG_ARRAY |
  17599                           SOC_REG_FLAG_RO |
  17600                           SOC_REG_FLAG_WO |
  17601                           SOC_REG_FLAG_REG_ARRAY,
  17602         0,
  17603         1,
  17604         soc_BRDC_DCH_REG_0196r_fields,
  17605         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17606         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  17607         -1,
  17608         -1,
  17609     },
  17610 #endif /* chips */
  17611 
  17612 #if defined(BCM_88950_A0)
  17613     { /* SOC_REG_INT_BRDC_DCH_REG_01A2r */
  17614         soc_block_list[106],
  17615         soc_genreg,
  17616         3,
  17617         0,
  17618         0x1a2,
  17619         SOC_REG_FLAG_64_BITS |
  17620                           SOC_REG_FLAG_ARRAY |
  17621                           SOC_REG_FLAG_RO |
  17622                           SOC_REG_FLAG_WO |
  17623                           SOC_REG_FLAG_REG_ARRAY,
  17624         0,
  17625         1,
  17626         soc_BRDC_DCH_REG_0196r_fields,
  17627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17628         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  17629         -1,
  17630         -1,
  17631     },
  17632 #endif /* chips */
  17633 
  17634 #if defined(BCM_88950_A0)
  17635     { /* SOC_REG_INT_BRDC_DCH_REG_01A8r */
  17636         soc_block_list[106],
  17637         soc_genreg,
  17638         3,
  17639         0,
  17640         0x1a8,
  17641         SOC_REG_FLAG_64_BITS |
  17642                           SOC_REG_FLAG_ARRAY |
  17643                           SOC_REG_FLAG_RO |
  17644                           SOC_REG_FLAG_WO |
  17645                           SOC_REG_FLAG_REG_ARRAY,
  17646         0,
  17647         1,
  17648         soc_BRDC_DCH_REG_0196r_fields,
  17649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17650         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  17651         -1,
  17652         -1,
  17653     },
  17654 #endif /* chips */
  17655 
  17656 #if defined(BCM_88950_A0)
  17657     { /* SOC_REG_INT_BRDC_DCH_REG_01BEr */
  17658         soc_block_list[106],
  17659         soc_genreg,
  17660         1,
  17661         0,
  17662         0x1be,
  17663         SOC_REG_FLAG_WO,
  17664         0,
  17665         2,
  17666         soc_BRDC_DCH_REG_01BEr_fields,
  17667         SOC_RESET_VAL_DEC(0x00004001, 0x00000000)
  17668         SOC_RESET_MASK_DEC(0x007ffff1, 0x00000000)
  17669         -1,
  17670         -1,
  17671     },
  17672 #endif /* chips */
  17673 
  17674 #if defined(BCM_88950_A0)
  17675     { /* SOC_REG_INT_BRDC_DCH_REG_01BFr */
  17676         soc_block_list[106],
  17677         soc_genreg,
  17678         1,
  17679         0,
  17680         0x1bf,
  17681         SOC_REG_FLAG_WO,
  17682         0,
  17683         1,
  17684         soc_BRDC_DCH_REG_01BFr_fields,
  17685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17686         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  17687         -1,
  17688         -1,
  17689     },
  17690 #endif /* chips */
  17691 
  17692 #if defined(BCM_88950_A0)
  17693     { /* SOC_REG_INT_BRDC_DCH_REG_01C0r */
  17694         soc_block_list[106],
  17695         soc_genreg,
  17696         1,
  17697         0,
  17698         0x1c0,
  17699         SOC_REG_FLAG_64_BITS |
  17700                           SOC_REG_FLAG_WO,
  17701         0,
  17702         1,
  17703         soc_BRDC_DCH_REG_01C0r_fields,
  17704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17705         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  17706         -1,
  17707         -1,
  17708     },
  17709 #endif /* chips */
  17710 
  17711 #if defined(BCM_88950_A0)
  17712     { /* SOC_REG_INT_BRDC_DCH_REG_01DEr */
  17713         soc_block_list[106],
  17714         soc_genreg,
  17715         3,
  17716         0,
  17717         0x1de,
  17718         SOC_REG_FLAG_ARRAY |
  17719                           SOC_REG_FLAG_RO |
  17720                           SOC_REG_FLAG_WO |
  17721                           SOC_REG_FLAG_REG_ARRAY,
  17722         0,
  17723         2,
  17724         soc_BRDC_CCS_REG_0112r_fields,
  17725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17726         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17727         -1,
  17728         -1,
  17729     },
  17730 #endif /* chips */
  17731 
  17732 #if defined(BCM_88950_A0)
  17733     { /* SOC_REG_INT_BRDC_DCH_REG_01EAr */
  17734         soc_block_list[106],
  17735         soc_genreg,
  17736         3,
  17737         0,
  17738         0x1ea,
  17739         SOC_REG_FLAG_ARRAY |
  17740                           SOC_REG_FLAG_RO |
  17741                           SOC_REG_FLAG_WO |
  17742                           SOC_REG_FLAG_REG_ARRAY,
  17743         0,
  17744         2,
  17745         soc_BRDC_CCS_REG_0112r_fields,
  17746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17747         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  17748         -1,
  17749         -1,
  17750     },
  17751 #endif /* chips */
  17752 
  17753 #if defined(BCM_88950_A0)
  17754     { /* SOC_REG_INT_BRDC_DCH_REG_01EDr */
  17755         soc_block_list[106],
  17756         soc_genreg,
  17757         3,
  17758         0,
  17759         0x1ed,
  17760         SOC_REG_FLAG_64_BITS |
  17761                           SOC_REG_FLAG_ARRAY |
  17762                           SOC_REG_FLAG_RO |
  17763                           SOC_REG_FLAG_WO |
  17764                           SOC_REG_FLAG_REG_ARRAY,
  17765         0,
  17766         1,
  17767         soc_BRDC_DCH_REG_01EDr_fields,
  17768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17769         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  17770         -1,
  17771         -1,
  17772     },
  17773 #endif /* chips */
  17774 
  17775 #if defined(BCM_88950_A0)
  17776     { /* SOC_REG_INT_BRDC_DCH_REG_01F3r */
  17777         soc_block_list[106],
  17778         soc_genreg,
  17779         3,
  17780         0,
  17781         0x1f3,
  17782         SOC_REG_FLAG_64_BITS |
  17783                           SOC_REG_FLAG_ARRAY |
  17784                           SOC_REG_FLAG_RO |
  17785                           SOC_REG_FLAG_WO |
  17786                           SOC_REG_FLAG_REG_ARRAY,
  17787         0,
  17788         1,
  17789         soc_BRDC_DCH_REG_01EDr_fields,
  17790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17791         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  17792         -1,
  17793         -1,
  17794     },
  17795 #endif /* chips */
  17796 
  17797 #if defined(BCM_88950_A0)
  17798     { /* SOC_REG_INT_BRDC_DCH_REG_01F9r */
  17799         soc_block_list[106],
  17800         soc_genreg,
  17801         3,
  17802         0,
  17803         0x1f9,
  17804         SOC_REG_FLAG_64_BITS |
  17805                           SOC_REG_FLAG_ARRAY |
  17806                           SOC_REG_FLAG_RO |
  17807                           SOC_REG_FLAG_WO |
  17808                           SOC_REG_FLAG_REG_ARRAY,
  17809         0,
  17810         1,
  17811         soc_BRDC_DCH_REG_01EDr_fields,
  17812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17813         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  17814         -1,
  17815         -1,
  17816     },
  17817 #endif /* chips */
  17818 
  17819 #if defined(BCM_88950_A0)
  17820     { /* SOC_REG_INT_BRDC_DCH_REG_01FFr */
  17821         soc_block_list[106],
  17822         soc_genreg,
  17823         3,
  17824         0,
  17825         0x1ff,
  17826         SOC_REG_FLAG_64_BITS |
  17827                           SOC_REG_FLAG_ARRAY |
  17828                           SOC_REG_FLAG_RO |
  17829                           SOC_REG_FLAG_WO |
  17830                           SOC_REG_FLAG_REG_ARRAY,
  17831         0,
  17832         1,
  17833         soc_BRDC_DCH_REG_01EDr_fields,
  17834         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17835         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  17836         -1,
  17837         -1,
  17838     },
  17839 #endif /* chips */
  17840 
  17841 #if defined(BCM_88950_A0)
  17842     { /* SOC_REG_INT_BRDC_DCH_REMOTE_PRI_PIPE_IDXr */
  17843         soc_block_list[106],
  17844         soc_genreg,
  17845         1,
  17846         0,
  17847         0x10e,
  17848         SOC_REG_FLAG_ABOVE_64_BITS |
  17849                           SOC_REG_FLAG_WO,
  17850         0,
  17851         1,
  17852         soc_BRDC_DCH_REMOTE_PRI_PIPE_IDXr_fields,
  17853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17854         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17855         -1,
  17856         -1,
  17857     },
  17858 #endif /* chips */
  17859 
  17860 #if defined(BCM_88790_A0)
  17861     { /* SOC_REG_INT_BRDC_DCH_REMOTE_PRI_PIPE_IDX_BCM88790_A0r */
  17862         soc_block_list[106],
  17863         soc_genreg,
  17864         1,
  17865         0,
  17866         0x112,
  17867         SOC_REG_FLAG_64_BITS |
  17868                           SOC_REG_FLAG_WO,
  17869         0,
  17870         1,
  17871         soc_BRDC_DCH_REMOTE_PRI_PIPE_IDX_BCM88790_A0r_fields,
  17872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17873         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17874         -1,
  17875         -1,
  17876     },
  17877 #endif /* chips */
  17878 
  17879 #if defined(BCM_88950_A0)
  17880     { /* SOC_REG_INT_BRDC_DCH_REMOTE_SEC_PIPE_IDXr */
  17881         soc_block_list[106],
  17882         soc_genreg,
  17883         1,
  17884         0,
  17885         0x111,
  17886         SOC_REG_FLAG_ABOVE_64_BITS |
  17887                           SOC_REG_FLAG_WO,
  17888         0,
  17889         1,
  17890         soc_BRDC_DCH_REMOTE_SEC_PIPE_IDXr_fields,
  17891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17892         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  17893         -1,
  17894         -1,
  17895     },
  17896 #endif /* chips */
  17897 
  17898 #if defined(BCM_88790_A0)
  17899     { /* SOC_REG_INT_BRDC_DCH_REMOTE_SEC_PIPE_IDX_BCM88790_A0r */
  17900         soc_block_list[106],
  17901         soc_genreg,
  17902         1,
  17903         0,
  17904         0x114,
  17905         SOC_REG_FLAG_64_BITS |
  17906                           SOC_REG_FLAG_WO,
  17907         0,
  17908         1,
  17909         soc_BRDC_DCH_REMOTE_SEC_PIPE_IDX_BCM88790_A0r_fields,
  17910         SOC_RESET_VAL_DEC(0x55555555, 0x00005555)
  17911         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  17912         -1,
  17913         -1,
  17914     },
  17915 #endif /* chips */
  17916 
  17917 #if defined(BCM_88950_A0)
  17918     { /* SOC_REG_INT_BRDC_DCH_RESERVED_MIRROR_ADDRr */
  17919         soc_block_list[106],
  17920         soc_genreg,
  17921         1,
  17922         0,
  17923         0x85,
  17924         SOC_REG_FLAG_WO,
  17925         0,
  17926         2,
  17927         soc_BRDC_CCS_RESERVED_MIRROR_ADDRr_fields,
  17928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17929         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  17930         -1,
  17931         -1,
  17932     },
  17933 #endif /* chips */
  17934 
  17935 #if defined(BCM_88790_A0)
  17936     { /* SOC_REG_INT_BRDC_DCH_RESERVED_MIRROR_ADDR_BCM88790_A0r */
  17937         soc_block_list[106],
  17938         soc_genreg,
  17939         1,
  17940         0,
  17941         0x85,
  17942         SOC_REG_FLAG_WO,
  17943         0,
  17944         2,
  17945         soc_BRDC_DCH_RESERVED_MIRROR_ADDRr_fields,
  17946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17947         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  17948         -1,
  17949         -1,
  17950     },
  17951 #endif /* chips */
  17952 
  17953 #if defined(BCM_88790_A0)
  17954     { /* SOC_REG_INT_BRDC_DCH_RESERVED_MTCDr */
  17955         soc_block_list[106],
  17956         soc_genreg,
  17957         1,
  17958         0,
  17959         0xae,
  17960         SOC_REG_FLAG_WO,
  17961         0,
  17962         6,
  17963         soc_BRDC_DCH_RESERVED_MTCDr_fields,
  17964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  17965         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  17966         -1,
  17967         -1,
  17968     },
  17969 #endif /* chips */
  17970 
  17971 #if defined(BCM_88950_A0)
  17972     { /* SOC_REG_INT_BRDC_DCH_RESERVED_MTCPr */
  17973         soc_block_list[106],
  17974         soc_genreg,
  17975         1,
  17976         0,
  17977         0xad,
  17978         SOC_REG_FLAG_64_BITS |
  17979                           SOC_REG_FLAG_WO,
  17980         0,
  17981         18,
  17982         soc_BRDC_CCS_RESERVED_MTCPr_fields,
  17983         SOC_RESET_VAL_DEC(0x80000000, 0x00000001)
  17984         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
  17985         -1,
  17986         -1,
  17987     },
  17988 #endif /* chips */
  17989 
  17990 #if defined(BCM_88790_A0)
  17991     { /* SOC_REG_INT_BRDC_DCH_RESERVED_MTCP_BCM88790_A0r */
  17992         soc_block_list[106],
  17993         soc_genreg,
  17994         1,
  17995         0,
  17996         0xad,
  17997         SOC_REG_FLAG_64_BITS |
  17998                           SOC_REG_FLAG_WO,
  17999         0,
  18000         17,
  18001         soc_BRDC_DCH_RESERVED_MTCPr_fields,
  18002         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  18003         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  18004         -1,
  18005         -1,
  18006     },
  18007 #endif /* chips */
  18008 
  18009 #if defined(BCM_88950_A0)
  18010     { /* SOC_REG_INT_BRDC_DCH_RESERVED_PCMI_2r */
  18011         soc_block_list[106],
  18012         soc_genreg,
  18013         1,
  18014         0,
  18015         0xb6,
  18016         SOC_REG_FLAG_WO,
  18017         0,
  18018         1,
  18019         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  18020         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  18021         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18022         -1,
  18023         -1,
  18024     },
  18025 #endif /* chips */
  18026 
  18027 #if defined(BCM_88950_A0)
  18028     { /* SOC_REG_INT_BRDC_DCH_RESERVED_PCMI_4r */
  18029         soc_block_list[106],
  18030         soc_genreg,
  18031         1,
  18032         0,
  18033         0xbc,
  18034         SOC_REG_FLAG_WO,
  18035         0,
  18036         1,
  18037         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  18038         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  18039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18040         -1,
  18041         -1,
  18042     },
  18043 #endif /* chips */
  18044 
  18045 #if defined(BCM_88950_A0)
  18046     { /* SOC_REG_INT_BRDC_DCH_RESERVED_PCMI_2_Sr */
  18047         soc_block_list[106],
  18048         soc_genreg,
  18049         1,
  18050         0,
  18051         0xb7,
  18052         SOC_REG_FLAG_RO |
  18053                           SOC_REG_FLAG_WO,
  18054         0,
  18055         3,
  18056         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  18057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18058         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18059         -1,
  18060         -1,
  18061     },
  18062 #endif /* chips */
  18063 
  18064 #if defined(BCM_88950_A0)
  18065     { /* SOC_REG_INT_BRDC_DCH_RESERVED_PCMI_2_Tr */
  18066         soc_block_list[106],
  18067         soc_genreg,
  18068         1,
  18069         0,
  18070         0xb8,
  18071         SOC_REG_FLAG_WO,
  18072         0,
  18073         2,
  18074         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  18075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18076         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18077         -1,
  18078         -1,
  18079     },
  18080 #endif /* chips */
  18081 
  18082 #if defined(BCM_88950_A0)
  18083     { /* SOC_REG_INT_BRDC_DCH_RESERVED_PCMI_4_Sr */
  18084         soc_block_list[106],
  18085         soc_genreg,
  18086         1,
  18087         0,
  18088         0xbd,
  18089         SOC_REG_FLAG_RO |
  18090                           SOC_REG_FLAG_WO,
  18091         0,
  18092         3,
  18093         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  18094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18096         -1,
  18097         -1,
  18098     },
  18099 #endif /* chips */
  18100 
  18101 #if defined(BCM_88950_A0)
  18102     { /* SOC_REG_INT_BRDC_DCH_RESERVED_PCMI_4_Tr */
  18103         soc_block_list[106],
  18104         soc_genreg,
  18105         1,
  18106         0,
  18107         0xbe,
  18108         SOC_REG_FLAG_WO,
  18109         0,
  18110         2,
  18111         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  18112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18113         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  18114         -1,
  18115         -1,
  18116     },
  18117 #endif /* chips */
  18118 
  18119 #if defined(BCM_88950_A0)
  18120     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_0r */
  18121         soc_block_list[106],
  18122         soc_genreg,
  18123         1,
  18124         0,
  18125         0x90,
  18126         SOC_REG_FLAG_WO,
  18127         0,
  18128         1,
  18129         soc_BRDC_CCS_RESERVED_SPARE_0r_fields,
  18130         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  18131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18132         -1,
  18133         -1,
  18134     },
  18135 #endif /* chips */
  18136 
  18137 #if defined(BCM_88950_A0)
  18138     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_1r */
  18139         soc_block_list[106],
  18140         soc_genreg,
  18141         1,
  18142         0,
  18143         0x91,
  18144         SOC_REG_FLAG_WO,
  18145         0,
  18146         1,
  18147         soc_BRDC_CCS_RESERVED_SPARE_1r_fields,
  18148         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  18149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18150         -1,
  18151         -1,
  18152     },
  18153 #endif /* chips */
  18154 
  18155 #if defined(BCM_88950_A0)
  18156     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_2r */
  18157         soc_block_list[106],
  18158         soc_genreg,
  18159         1,
  18160         0,
  18161         0x92,
  18162         SOC_REG_FLAG_WO,
  18163         0,
  18164         1,
  18165         soc_BRDC_CCS_RESERVED_SPARE_2r_fields,
  18166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18168         -1,
  18169         -1,
  18170     },
  18171 #endif /* chips */
  18172 
  18173 #if defined(BCM_88950_A0)
  18174     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_3r */
  18175         soc_block_list[106],
  18176         soc_genreg,
  18177         1,
  18178         0,
  18179         0x93,
  18180         SOC_REG_FLAG_WO,
  18181         0,
  18182         1,
  18183         soc_BRDC_CCS_RESERVED_SPARE_3r_fields,
  18184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18186         -1,
  18187         -1,
  18188     },
  18189 #endif /* chips */
  18190 
  18191 #if defined(BCM_88790_A0)
  18192     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_0_BCM88790_A0r */
  18193         soc_block_list[106],
  18194         soc_genreg,
  18195         1,
  18196         0,
  18197         0x90,
  18198         SOC_REG_FLAG_WO,
  18199         0,
  18200         1,
  18201         soc_BRDC_DCH_RESERVED_SPARE_0r_fields,
  18202         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  18203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18204         -1,
  18205         -1,
  18206     },
  18207 #endif /* chips */
  18208 
  18209 #if defined(BCM_88790_A0)
  18210     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_1_BCM88790_A0r */
  18211         soc_block_list[106],
  18212         soc_genreg,
  18213         1,
  18214         0,
  18215         0x91,
  18216         SOC_REG_FLAG_WO,
  18217         0,
  18218         1,
  18219         soc_BRDC_DCH_RESERVED_SPARE_1r_fields,
  18220         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  18221         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18222         -1,
  18223         -1,
  18224     },
  18225 #endif /* chips */
  18226 
  18227 #if defined(BCM_88790_A0)
  18228     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_2_BCM88790_A0r */
  18229         soc_block_list[106],
  18230         soc_genreg,
  18231         1,
  18232         0,
  18233         0x92,
  18234         SOC_REG_FLAG_WO,
  18235         0,
  18236         1,
  18237         soc_BRDC_DCH_RESERVED_SPARE_2r_fields,
  18238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18240         -1,
  18241         -1,
  18242     },
  18243 #endif /* chips */
  18244 
  18245 #if defined(BCM_88790_A0)
  18246     { /* SOC_REG_INT_BRDC_DCH_RESERVED_SPARE_3_BCM88790_A0r */
  18247         soc_block_list[106],
  18248         soc_genreg,
  18249         1,
  18250         0,
  18251         0x93,
  18252         SOC_REG_FLAG_WO,
  18253         0,
  18254         1,
  18255         soc_BRDC_DCH_RESERVED_SPARE_3r_fields,
  18256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18258         -1,
  18259         -1,
  18260     },
  18261 #endif /* chips */
  18262 
  18263 #if defined(BCM_88950_A0)
  18264     { /* SOC_REG_INT_BRDC_DCH_SBUS_BROADCAST_IDr */
  18265         soc_block_list[106],
  18266         soc_genreg,
  18267         1,
  18268         0,
  18269         0x86,
  18270         SOC_REG_FLAG_WO,
  18271         0,
  18272         1,
  18273         soc_BRDC_DCH_SBUS_BROADCAST_IDr_fields,
  18274         SOC_RESET_VAL_DEC(0x0000004e, 0x00000000)
  18275         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  18276         -1,
  18277         -1,
  18278     },
  18279 #endif /* chips */
  18280 
  18281 #if defined(BCM_88790_A0)
  18282     { /* SOC_REG_INT_BRDC_DCH_SBUS_BROADCAST_ID_BCM88790_A0r */
  18283         soc_block_list[106],
  18284         soc_genreg,
  18285         1,
  18286         0,
  18287         0x86,
  18288         SOC_REG_FLAG_WO,
  18289         0,
  18290         1,
  18291         soc_BRDC_DCH_SBUS_BROADCAST_ID_BCM88790_A0r_fields,
  18292         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  18293         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  18294         -1,
  18295         -1,
  18296     },
  18297 #endif /* chips */
  18298 
  18299 #if defined(BCM_88950_A0)
  18300     { /* SOC_REG_INT_BRDC_DCH_SBUS_LAST_IN_CHAINr */
  18301         soc_block_list[106],
  18302         soc_genreg,
  18303         1,
  18304         0,
  18305         0x87,
  18306         SOC_REG_FLAG_WO,
  18307         0,
  18308         1,
  18309         soc_BRDC_CCS_SBUS_LAST_IN_CHAINr_fields,
  18310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18311         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18312         -1,
  18313         -1,
  18314     },
  18315 #endif /* chips */
  18316 
  18317 #if defined(BCM_88790_A0)
  18318     { /* SOC_REG_INT_BRDC_DCH_SBUS_LAST_IN_CHAIN_BCM88790_A0r */
  18319         soc_block_list[106],
  18320         soc_genreg,
  18321         1,
  18322         0,
  18323         0x87,
  18324         SOC_REG_FLAG_WO,
  18325         0,
  18326         1,
  18327         soc_BRDC_DCH_SBUS_LAST_IN_CHAINr_fields,
  18328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18329         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18330         -1,
  18331         -1,
  18332     },
  18333 #endif /* chips */
  18334 
  18335 #if defined(BCM_88950_A0)
  18336     { /* SOC_REG_INT_BRDC_DCH_TDM_PRIORITYr */
  18337         soc_block_list[106],
  18338         soc_genreg,
  18339         1,
  18340         0,
  18341         0x109,
  18342         SOC_REG_FLAG_WO,
  18343         0,
  18344         2,
  18345         soc_BRDC_DCH_TDM_PRIORITYr_fields,
  18346         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  18347         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  18348         -1,
  18349         -1,
  18350     },
  18351 #endif /* chips */
  18352 
  18353 #if defined(BCM_88790_A0)
  18354     { /* SOC_REG_INT_BRDC_DCH_TDM_PRIORITY_BCM88790_A0r */
  18355         soc_block_list[106],
  18356         soc_genreg,
  18357         1,
  18358         0,
  18359         0x10e,
  18360         SOC_REG_FLAG_WO,
  18361         0,
  18362         2,
  18363         soc_BRDC_DCH_TDM_PRIORITY_BCM88790_A0r_fields,
  18364         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  18365         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  18366         -1,
  18367         -1,
  18368     },
  18369 #endif /* chips */
  18370 
  18371 #if defined(BCM_88950_A0)
  18372     { /* SOC_REG_INT_BRDC_DCH_THREE_PIPES_BMPr */
  18373         soc_block_list[106],
  18374         soc_genreg,
  18375         1,
  18376         0,
  18377         0x1c4,
  18378         SOC_REG_FLAG_64_BITS |
  18379                           SOC_REG_FLAG_WO,
  18380         0,
  18381         1,
  18382         soc_BRDC_DCH_THREE_PIPES_BMPr_fields,
  18383         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  18384         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  18385         -1,
  18386         -1,
  18387     },
  18388 #endif /* chips */
  18389 
  18390 #if defined(BCM_88790_A0)
  18391     { /* SOC_REG_INT_BRDC_DCH_THREE_PIPES_BMP_BCM88790_A0r */
  18392         soc_block_list[106],
  18393         soc_genreg,
  18394         1,
  18395         0,
  18396         0x1b7,
  18397         SOC_REG_FLAG_WO,
  18398         0,
  18399         1,
  18400         soc_BRDC_DCH_THREE_PIPES_BMP_BCM88790_A0r_fields,
  18401         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  18402         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  18403         -1,
  18404         -1,
  18405     },
  18406 #endif /* chips */
  18407 
  18408 #if defined(BCM_88950_A0)
  18409     { /* SOC_REG_INT_BRDC_DCH_TWO_PIPES_BMPr */
  18410         soc_block_list[106],
  18411         soc_genreg,
  18412         1,
  18413         0,
  18414         0x1c2,
  18415         SOC_REG_FLAG_64_BITS |
  18416                           SOC_REG_FLAG_WO,
  18417         0,
  18418         1,
  18419         soc_BRDC_DCH_TWO_PIPES_BMPr_fields,
  18420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18421         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  18422         -1,
  18423         -1,
  18424     },
  18425 #endif /* chips */
  18426 
  18427 #if defined(BCM_88790_A0)
  18428     { /* SOC_REG_INT_BRDC_DCH_TWO_PIPES_BMP_BCM88790_A0r */
  18429         soc_block_list[106],
  18430         soc_genreg,
  18431         1,
  18432         0,
  18433         0x1b6,
  18434         SOC_REG_FLAG_WO,
  18435         0,
  18436         1,
  18437         soc_BRDC_DCH_TWO_PIPES_BMP_BCM88790_A0r_fields,
  18438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18439         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  18440         -1,
  18441         -1,
  18442     },
  18443 #endif /* chips */
  18444 
  18445 #if defined(BCM_88790_A0)
  18446     { /* SOC_REG_INT_BRDC_DCH_TX_CPU_CELL_CNTr */
  18447         soc_block_list[106],
  18448         soc_genreg,
  18449         1,
  18450         0,
  18451         0x241,
  18452         SOC_REG_FLAG_RO |
  18453                           SOC_REG_FLAG_WO,
  18454         SOC_REG_FLAG_COUNTER_FEILDS,
  18455         1,
  18456         soc_BRDC_DCH_TX_CPU_CELL_CNTr_fields,
  18457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18458         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18459         -1,
  18460         -1,
  18461     },
  18462 #endif /* chips */
  18463 
  18464 #if defined(BCM_88790_A0)
  18465     { /* SOC_REG_INT_BRDC_DCH_TX_CPU_CELL_DATAr */
  18466         soc_block_list[106],
  18467         soc_genreg,
  18468         8,
  18469         0,
  18470         0x1fd,
  18471         SOC_REG_FLAG_ABOVE_64_BITS |
  18472                           SOC_REG_FLAG_ARRAY |
  18473                           SOC_REG_FLAG_WO |
  18474                           SOC_REG_FLAG_REG_ARRAY,
  18475         0,
  18476         1,
  18477         soc_BRDC_DCH_TX_CPU_CELL_DATAr_fields,
  18478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18479         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18480         -1,
  18481         -1,
  18482     },
  18483 #endif /* chips */
  18484 
  18485 #if defined(BCM_88790_A0)
  18486     { /* SOC_REG_INT_BRDC_DCH_TX_CPU_CELL_HEADERr */
  18487         soc_block_list[106],
  18488         soc_genreg,
  18489         1,
  18490         0,
  18491         0x23d,
  18492         SOC_REG_FLAG_ABOVE_64_BITS |
  18493                           SOC_REG_FLAG_WO,
  18494         0,
  18495         1,
  18496         soc_BRDC_DCH_TX_CPU_CELL_HEADERr_fields,
  18497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18498         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  18499         -1,
  18500         -1,
  18501     },
  18502 #endif /* chips */
  18503 
  18504 #if defined(BCM_88790_A0)
  18505     { /* SOC_REG_INT_BRDC_DCH_TX_CPU_CELL_INFOr */
  18506         soc_block_list[106],
  18507         soc_genreg,
  18508         1,
  18509         0,
  18510         0x1fc,
  18511         SOC_REG_FLAG_WO,
  18512         0,
  18513         4,
  18514         soc_BRDC_DCH_TX_CPU_CELL_INFOr_fields,
  18515         SOC_RESET_VAL_DEC(0x0000067f, 0x00000000)
  18516         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  18517         -1,
  18518         -1,
  18519     },
  18520 #endif /* chips */
  18521 
  18522 #if defined(BCM_88790_A0)
  18523     { /* SOC_REG_INT_BRDC_DCH_TX_CPU_CELL_TRGr */
  18524         soc_block_list[106],
  18525         soc_genreg,
  18526         1,
  18527         0,
  18528         0x1fb,
  18529         SOC_REG_FLAG_WO |
  18530                           SOC_REG_FLAG_SIGNAL,
  18531         0,
  18532         1,
  18533         soc_BRDC_DCH_TX_CPU_CELL_TRGr_fields,
  18534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18535         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18536         -1,
  18537         -1,
  18538     },
  18539 #endif /* chips */
  18540 
  18541 #if defined(BCM_88950_A0)
  18542     { /* SOC_REG_INT_BRDC_DCH_TYPE_ERR_DROP_CNTr */
  18543         soc_block_list[106],
  18544         soc_genreg,
  18545         1,
  18546         0,
  18547         0x1dd,
  18548         SOC_REG_FLAG_RO |
  18549                           SOC_REG_FLAG_WO,
  18550         0,
  18551         2,
  18552         soc_BRDC_DCH_TYPE_ERR_DROP_CNTr_fields,
  18553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18554         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18555         -1,
  18556         -1,
  18557     },
  18558 #endif /* chips */
  18559 
  18560 #if defined(BCM_88790_A0)
  18561     { /* SOC_REG_INT_BRDC_DCH_TYPE_ERR_DROP_CNT_BCM88790_A0r */
  18562         soc_block_list[106],
  18563         soc_genreg,
  18564         1,
  18565         0,
  18566         0x1d1,
  18567         SOC_REG_FLAG_RO |
  18568                           SOC_REG_FLAG_WO,
  18569         SOC_REG_FLAG_COUNTER_FEILDS,
  18570         1,
  18571         soc_BRDC_DCH_TYPE_ERR_DROP_CNT_BCM88790_A0r_fields,
  18572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18574         -1,
  18575         -1,
  18576     },
  18577 #endif /* chips */
  18578 
  18579 #if defined(BCM_88790_A0)
  18580     { /* SOC_REG_INT_BRDC_DCH_UNREACH_DESTr */
  18581         soc_block_list[106],
  18582         soc_genreg,
  18583         1,
  18584         0,
  18585         0x19b,
  18586         SOC_REG_FLAG_RO |
  18587                           SOC_REG_FLAG_WO,
  18588         0,
  18589         1,
  18590         soc_BRDC_DCH_UNREACH_DESTr_fields,
  18591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18592         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  18593         -1,
  18594         -1,
  18595     },
  18596 #endif /* chips */
  18597 
  18598 #if defined(BCM_88790_A0)
  18599     { /* SOC_REG_INT_BRDC_DCH_UNREACH_DEST_CNTr */
  18600         soc_block_list[106],
  18601         soc_genreg,
  18602         1,
  18603         0,
  18604         0x19c,
  18605         SOC_REG_FLAG_RO |
  18606                           SOC_REG_FLAG_WO,
  18607         SOC_REG_FLAG_COUNTER_FEILDS,
  18608         1,
  18609         soc_BRDC_DCH_UNREACH_DEST_CNTr_fields,
  18610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18611         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18612         -1,
  18613         -1,
  18614     },
  18615 #endif /* chips */
  18616 
  18617 #if defined(BCM_88790_A0)
  18618     { /* SOC_REG_INT_BRDC_DCH_UN_EXP_DISC_CNT_3r */
  18619         soc_block_list[106],
  18620         soc_genreg,
  18621         1,
  18622         0,
  18623         0x1b5,
  18624         SOC_REG_FLAG_RO |
  18625                           SOC_REG_FLAG_WO,
  18626         SOC_REG_FLAG_COUNTER_FEILDS,
  18627         1,
  18628         soc_BRDC_DCH_UN_EXP_DISC_CNT_3r_fields,
  18629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18630         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18631         -1,
  18632         -1,
  18633     },
  18634 #endif /* chips */
  18635 
  18636 #if defined(BCM_88790_A0)
  18637     { /* SOC_REG_INT_BRDC_DCH_UN_EXP_DISC_CNT_2_PNr */
  18638         soc_block_list[106],
  18639         soc_genreg,
  18640         3,
  18641         0,
  18642         0x1d5,
  18643         SOC_REG_FLAG_ARRAY |
  18644                           SOC_REG_FLAG_RO |
  18645                           SOC_REG_FLAG_WO |
  18646                           SOC_REG_FLAG_REG_ARRAY,
  18647         SOC_REG_FLAG_COUNTER_FEILDS,
  18648         1,
  18649         soc_BRDC_DCH_UN_EXP_DISC_CNT_2_PNr_fields,
  18650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18651         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18652         -1,
  18653         -1,
  18654     },
  18655 #endif /* chips */
  18656 
  18657 #if defined(BCM_88950_A0)
  18658     { /* SOC_REG_INT_BRDC_DCH_UN_EXP_DISC_CNT_2_P_Nr */
  18659         soc_block_list[106],
  18660         soc_genreg,
  18661         3,
  18662         0,
  18663         0x1e1,
  18664         SOC_REG_FLAG_ARRAY |
  18665                           SOC_REG_FLAG_RO |
  18666                           SOC_REG_FLAG_WO |
  18667                           SOC_REG_FLAG_REG_ARRAY,
  18668         0,
  18669         2,
  18670         soc_BRDC_DCH_UN_EXP_DISC_CNT_2_P_Nr_fields,
  18671         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18672         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18673         -1,
  18674         -1,
  18675     },
  18676 #endif /* chips */
  18677 
  18678 #if defined(BCM_88790_A0)
  18679     { /* SOC_REG_INT_BRDC_DCH_UN_EXP_DISC_CNT_3_PNr */
  18680         soc_block_list[106],
  18681         soc_genreg,
  18682         3,
  18683         0,
  18684         0x1db,
  18685         SOC_REG_FLAG_ARRAY |
  18686                           SOC_REG_FLAG_RO |
  18687                           SOC_REG_FLAG_WO |
  18688                           SOC_REG_FLAG_REG_ARRAY,
  18689         SOC_REG_FLAG_COUNTER_FEILDS,
  18690         1,
  18691         soc_BRDC_DCH_UN_EXP_DISC_CNT_3_PNr_fields,
  18692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18693         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18694         -1,
  18695         -1,
  18696     },
  18697 #endif /* chips */
  18698 
  18699 #if defined(BCM_88950_A0)
  18700     { /* SOC_REG_INT_BRDC_DCH_UN_EXP_DISC_CNT_3_P_Nr */
  18701         soc_block_list[106],
  18702         soc_genreg,
  18703         3,
  18704         0,
  18705         0x1e7,
  18706         SOC_REG_FLAG_ARRAY |
  18707                           SOC_REG_FLAG_RO |
  18708                           SOC_REG_FLAG_WO |
  18709                           SOC_REG_FLAG_REG_ARRAY,
  18710         0,
  18711         2,
  18712         soc_BRDC_DCH_UN_EXP_DISC_CNT_3_P_Nr_fields,
  18713         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18714         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18715         -1,
  18716         -1,
  18717     },
  18718 #endif /* chips */
  18719 
  18720 #if defined(BCM_88790_A0)
  18721     { /* SOC_REG_INT_BRDC_DCH_UN_EXP_DISC_CNT_PNr */
  18722         soc_block_list[106],
  18723         soc_genreg,
  18724         3,
  18725         0,
  18726         0x1d8,
  18727         SOC_REG_FLAG_ARRAY |
  18728                           SOC_REG_FLAG_RO |
  18729                           SOC_REG_FLAG_WO |
  18730                           SOC_REG_FLAG_REG_ARRAY,
  18731         SOC_REG_FLAG_COUNTER_FEILDS,
  18732         1,
  18733         soc_BRDC_DCH_UN_EXP_DISC_CNT_PNr_fields,
  18734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18736         -1,
  18737         -1,
  18738     },
  18739 #endif /* chips */
  18740 
  18741 #if defined(BCM_88950_A0)
  18742     { /* SOC_REG_INT_BRDC_DCH_UN_EXP_DISC_CNT_P_Nr */
  18743         soc_block_list[106],
  18744         soc_genreg,
  18745         3,
  18746         0,
  18747         0x1e4,
  18748         SOC_REG_FLAG_ARRAY |
  18749                           SOC_REG_FLAG_RO |
  18750                           SOC_REG_FLAG_WO |
  18751                           SOC_REG_FLAG_REG_ARRAY,
  18752         0,
  18753         2,
  18754         soc_BRDC_DCH_UN_EXP_DISC_CNT_P_Nr_fields,
  18755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18756         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18757         -1,
  18758         -1,
  18759     },
  18760 #endif /* chips */
  18761 
  18762 #if defined(BCM_88950_A0)
  18763     { /* SOC_REG_INT_BRDC_DCH_UN_REACH_DESTr */
  18764         soc_block_list[106],
  18765         soc_genreg,
  18766         1,
  18767         0,
  18768         0x1b1,
  18769         SOC_REG_FLAG_64_BITS |
  18770                           SOC_REG_FLAG_RO |
  18771                           SOC_REG_FLAG_WO,
  18772         0,
  18773         3,
  18774         soc_BRDC_DCH_UN_REACH_DESTr_fields,
  18775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18776         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  18777         -1,
  18778         -1,
  18779     },
  18780 #endif /* chips */
  18781 
  18782 #if defined(BCM_88950_A0)
  18783     { /* SOC_REG_INT_BRDC_DCH_USE_MC_CELL_PRIO_BMPr */
  18784         soc_block_list[106],
  18785         soc_genreg,
  18786         1,
  18787         0,
  18788         0x101,
  18789         SOC_REG_FLAG_64_BITS |
  18790                           SOC_REG_FLAG_WO,
  18791         0,
  18792         1,
  18793         soc_BRDC_DCH_USE_MC_CELL_PRIO_BMPr_fields,
  18794         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  18795         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  18796         -1,
  18797         -1,
  18798     },
  18799 #endif /* chips */
  18800 
  18801 #if defined(BCM_88790_A0)
  18802     { /* SOC_REG_INT_BRDC_DCH_USE_MC_CELL_PRIO_BMP_BCM88790_A0r */
  18803         soc_block_list[106],
  18804         soc_genreg,
  18805         1,
  18806         0,
  18807         0x101,
  18808         SOC_REG_FLAG_WO,
  18809         0,
  18810         1,
  18811         soc_BRDC_DCH_USE_MC_CELL_PRIO_BMP_BCM88790_A0r_fields,
  18812         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  18813         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  18814         -1,
  18815         -1,
  18816     },
  18817 #endif /* chips */
  18818 
  18819 #if defined(BCM_88790_A0)
  18820     { /* SOC_REG_INT_BRDC_DCH_WFQ_DYN_WEIGHT_THD_REGISTEr */
  18821         soc_block_list[106],
  18822         soc_genreg,
  18823         1,
  18824         0,
  18825         0x128,
  18826         SOC_REG_FLAG_WO,
  18827         0,
  18828         2,
  18829         soc_BRDC_DCH_WFQ_DYN_WEIGHT_THD_REGISTEr_fields,
  18830         SOC_RESET_VAL_DEC(0x00300300, 0x00000000)
  18831         SOC_RESET_MASK_DEC(0x003ff3ff, 0x00000000)
  18832         -1,
  18833         -1,
  18834     },
  18835 #endif /* chips */
  18836 
  18837 #if defined(BCM_88950_A0)
  18838     { /* SOC_REG_INT_BRDC_DCL_ALM_FULL_Pr */
  18839         soc_block_list[104],
  18840         soc_genreg,
  18841         3,
  18842         0,
  18843         0x136,
  18844         SOC_REG_FLAG_ARRAY |
  18845                           SOC_REG_FLAG_WO |
  18846                           SOC_REG_FLAG_REG_ARRAY,
  18847         0,
  18848         2,
  18849         soc_BRDC_DCL_ALM_FULL_Pr_fields,
  18850         SOC_RESET_VAL_DEC(0x000370dc, 0x00000000)
  18851         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  18852         -1,
  18853         -1,
  18854     },
  18855 #endif /* chips */
  18856 
  18857 #if defined(BCM_88950_A0)
  18858     { /* SOC_REG_INT_BRDC_DCL_CCP_0_DSCRD_CNTr */
  18859         soc_block_list[104],
  18860         soc_genreg,
  18861         1,
  18862         0,
  18863         0x242,
  18864         SOC_REG_FLAG_RO |
  18865                           SOC_REG_FLAG_WO,
  18866         0,
  18867         4,
  18868         soc_BRDC_DCL_CCP_0_DSCRD_CNTr_fields,
  18869         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18870         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18871         -1,
  18872         -1,
  18873     },
  18874 #endif /* chips */
  18875 
  18876 #if defined(BCM_88950_A0)
  18877     { /* SOC_REG_INT_BRDC_DCL_CCP_0_ILLEGAL_CELLS_DATAr */
  18878         soc_block_list[104],
  18879         soc_genreg,
  18880         1,
  18881         0,
  18882         0x23f,
  18883         SOC_REG_FLAG_RO |
  18884                           SOC_REG_FLAG_WO,
  18885         0,
  18886         4,
  18887         soc_BRDC_DCL_CCP_0_ILLEGAL_CELLS_DATAr_fields,
  18888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18889         SOC_RESET_MASK_DEC(0x001ff7ff, 0x00000000)
  18890         -1,
  18891         -1,
  18892     },
  18893 #endif /* chips */
  18894 
  18895 #if defined(BCM_88950_A0)
  18896     { /* SOC_REG_INT_BRDC_DCL_CCP_0_PROGRAMMABLE_CELLS_COUNTERr */
  18897         soc_block_list[104],
  18898         soc_genreg,
  18899         1,
  18900         0,
  18901         0x246,
  18902         SOC_REG_FLAG_RO |
  18903                           SOC_REG_FLAG_WO,
  18904         0,
  18905         2,
  18906         soc_BRDC_DCL_CCP_0_PROGRAMMABLE_CELLS_COUNTERr_fields,
  18907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18908         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18909         -1,
  18910         -1,
  18911     },
  18912 #endif /* chips */
  18913 
  18914 #if defined(BCM_88950_A0)
  18915     { /* SOC_REG_INT_BRDC_DCL_CCP_1_DSCRD_CNTr */
  18916         soc_block_list[104],
  18917         soc_genreg,
  18918         1,
  18919         0,
  18920         0x243,
  18921         SOC_REG_FLAG_RO |
  18922                           SOC_REG_FLAG_WO,
  18923         0,
  18924         4,
  18925         soc_BRDC_DCL_CCP_1_DSCRD_CNTr_fields,
  18926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18927         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18928         -1,
  18929         -1,
  18930     },
  18931 #endif /* chips */
  18932 
  18933 #if defined(BCM_88950_A0)
  18934     { /* SOC_REG_INT_BRDC_DCL_CCP_1_ILLEGAL_CELLS_DATAr */
  18935         soc_block_list[104],
  18936         soc_genreg,
  18937         1,
  18938         0,
  18939         0x241,
  18940         SOC_REG_FLAG_RO |
  18941                           SOC_REG_FLAG_WO,
  18942         0,
  18943         4,
  18944         soc_BRDC_DCL_CCP_1_ILLEGAL_CELLS_DATAr_fields,
  18945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18946         SOC_RESET_MASK_DEC(0x001ff7ff, 0x00000000)
  18947         -1,
  18948         -1,
  18949     },
  18950 #endif /* chips */
  18951 
  18952 #if defined(BCM_88950_A0)
  18953     { /* SOC_REG_INT_BRDC_DCL_CCP_1_PROGRAMMABLE_CELLS_COUNTERr */
  18954         soc_block_list[104],
  18955         soc_genreg,
  18956         1,
  18957         0,
  18958         0x247,
  18959         SOC_REG_FLAG_RO |
  18960                           SOC_REG_FLAG_WO,
  18961         0,
  18962         2,
  18963         soc_BRDC_DCL_CCP_1_PROGRAMMABLE_CELLS_COUNTERr_fields,
  18964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18965         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  18966         -1,
  18967         -1,
  18968     },
  18969 #endif /* chips */
  18970 
  18971 #if defined(BCM_88950_A0)
  18972     { /* SOC_REG_INT_BRDC_DCL_CCP_CONFIGURATIONSr */
  18973         soc_block_list[104],
  18974         soc_genreg,
  18975         1,
  18976         0,
  18977         0x23d,
  18978         SOC_REG_FLAG_WO,
  18979         0,
  18980         1,
  18981         soc_BRDC_DCL_CCP_CONFIGURATIONSr_fields,
  18982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  18983         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  18984         -1,
  18985         -1,
  18986     },
  18987 #endif /* chips */
  18988 
  18989 #if defined(BCM_88950_A0)
  18990     { /* SOC_REG_INT_BRDC_DCL_CCP_FIFOS_WATER_MARKr */
  18991         soc_block_list[104],
  18992         soc_genreg,
  18993         1,
  18994         0,
  18995         0x244,
  18996         SOC_REG_FLAG_RO |
  18997                           SOC_REG_FLAG_WO,
  18998         0,
  18999         4,
  19000         soc_BRDC_DCL_CCP_FIFOS_WATER_MARKr_fields,
  19001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19002         SOC_RESET_MASK_DEC(0x7f1f7f1f, 0x00000000)
  19003         -1,
  19004         -1,
  19005     },
  19006 #endif /* chips */
  19007 
  19008 #if defined(BCM_88950_A0)
  19009     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINKS_EVENTSr */
  19010         soc_block_list[104],
  19011         soc_genreg,
  19012         1,
  19013         0,
  19014         0x248,
  19015         SOC_REG_FLAG_64_BITS |
  19016                           SOC_REG_FLAG_RO |
  19017                           SOC_REG_FLAG_WO,
  19018         0,
  19019         1,
  19020         soc_BRDC_DCL_CONNECTIVITY_LINKS_EVENTSr_fields,
  19021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19022         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  19023         -1,
  19024         -1,
  19025     },
  19026 #endif /* chips */
  19027 
  19028 #if defined(BCM_88950_A0)
  19029     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_0r */
  19030         soc_block_list[104],
  19031         soc_genreg,
  19032         1,
  19033         0,
  19034         0x24a,
  19035         SOC_REG_FLAG_RO |
  19036                           SOC_REG_FLAG_WO,
  19037         0,
  19038         1,
  19039         soc_BRDC_DCL_CONNECTIVITY_LINK_0r_fields,
  19040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19041         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19042         -1,
  19043         -1,
  19044     },
  19045 #endif /* chips */
  19046 
  19047 #if defined(BCM_88950_A0)
  19048     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_1r */
  19049         soc_block_list[104],
  19050         soc_genreg,
  19051         1,
  19052         0,
  19053         0x24b,
  19054         SOC_REG_FLAG_RO |
  19055                           SOC_REG_FLAG_WO,
  19056         0,
  19057         1,
  19058         soc_BRDC_DCL_CONNECTIVITY_LINK_1r_fields,
  19059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19060         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19061         -1,
  19062         -1,
  19063     },
  19064 #endif /* chips */
  19065 
  19066 #if defined(BCM_88950_A0)
  19067     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_2r */
  19068         soc_block_list[104],
  19069         soc_genreg,
  19070         1,
  19071         0,
  19072         0x24c,
  19073         SOC_REG_FLAG_RO |
  19074                           SOC_REG_FLAG_WO,
  19075         0,
  19076         1,
  19077         soc_BRDC_DCL_CONNECTIVITY_LINK_2r_fields,
  19078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19079         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19080         -1,
  19081         -1,
  19082     },
  19083 #endif /* chips */
  19084 
  19085 #if defined(BCM_88950_A0)
  19086     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_3r */
  19087         soc_block_list[104],
  19088         soc_genreg,
  19089         1,
  19090         0,
  19091         0x24d,
  19092         SOC_REG_FLAG_RO |
  19093                           SOC_REG_FLAG_WO,
  19094         0,
  19095         1,
  19096         soc_BRDC_DCL_CONNECTIVITY_LINK_3r_fields,
  19097         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19098         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19099         -1,
  19100         -1,
  19101     },
  19102 #endif /* chips */
  19103 
  19104 #if defined(BCM_88950_A0)
  19105     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_4r */
  19106         soc_block_list[104],
  19107         soc_genreg,
  19108         1,
  19109         0,
  19110         0x24e,
  19111         SOC_REG_FLAG_RO |
  19112                           SOC_REG_FLAG_WO,
  19113         0,
  19114         1,
  19115         soc_BRDC_DCL_CONNECTIVITY_LINK_4r_fields,
  19116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19117         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19118         -1,
  19119         -1,
  19120     },
  19121 #endif /* chips */
  19122 
  19123 #if defined(BCM_88950_A0)
  19124     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_5r */
  19125         soc_block_list[104],
  19126         soc_genreg,
  19127         1,
  19128         0,
  19129         0x24f,
  19130         SOC_REG_FLAG_RO |
  19131                           SOC_REG_FLAG_WO,
  19132         0,
  19133         1,
  19134         soc_BRDC_DCL_CONNECTIVITY_LINK_5r_fields,
  19135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19136         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19137         -1,
  19138         -1,
  19139     },
  19140 #endif /* chips */
  19141 
  19142 #if defined(BCM_88950_A0)
  19143     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_6r */
  19144         soc_block_list[104],
  19145         soc_genreg,
  19146         1,
  19147         0,
  19148         0x250,
  19149         SOC_REG_FLAG_RO |
  19150                           SOC_REG_FLAG_WO,
  19151         0,
  19152         1,
  19153         soc_BRDC_DCL_CONNECTIVITY_LINK_6r_fields,
  19154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19155         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19156         -1,
  19157         -1,
  19158     },
  19159 #endif /* chips */
  19160 
  19161 #if defined(BCM_88950_A0)
  19162     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_7r */
  19163         soc_block_list[104],
  19164         soc_genreg,
  19165         1,
  19166         0,
  19167         0x251,
  19168         SOC_REG_FLAG_RO |
  19169                           SOC_REG_FLAG_WO,
  19170         0,
  19171         1,
  19172         soc_BRDC_DCL_CONNECTIVITY_LINK_7r_fields,
  19173         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19174         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19175         -1,
  19176         -1,
  19177     },
  19178 #endif /* chips */
  19179 
  19180 #if defined(BCM_88950_A0)
  19181     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_8r */
  19182         soc_block_list[104],
  19183         soc_genreg,
  19184         1,
  19185         0,
  19186         0x252,
  19187         SOC_REG_FLAG_RO |
  19188                           SOC_REG_FLAG_WO,
  19189         0,
  19190         1,
  19191         soc_BRDC_DCL_CONNECTIVITY_LINK_8r_fields,
  19192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19193         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19194         -1,
  19195         -1,
  19196     },
  19197 #endif /* chips */
  19198 
  19199 #if defined(BCM_88950_A0)
  19200     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_9r */
  19201         soc_block_list[104],
  19202         soc_genreg,
  19203         1,
  19204         0,
  19205         0x253,
  19206         SOC_REG_FLAG_RO |
  19207                           SOC_REG_FLAG_WO,
  19208         0,
  19209         1,
  19210         soc_BRDC_DCL_CONNECTIVITY_LINK_9r_fields,
  19211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19212         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19213         -1,
  19214         -1,
  19215     },
  19216 #endif /* chips */
  19217 
  19218 #if defined(BCM_88950_A0)
  19219     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_10r */
  19220         soc_block_list[104],
  19221         soc_genreg,
  19222         1,
  19223         0,
  19224         0x254,
  19225         SOC_REG_FLAG_RO |
  19226                           SOC_REG_FLAG_WO,
  19227         0,
  19228         1,
  19229         soc_BRDC_DCL_CONNECTIVITY_LINK_10r_fields,
  19230         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19231         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19232         -1,
  19233         -1,
  19234     },
  19235 #endif /* chips */
  19236 
  19237 #if defined(BCM_88950_A0)
  19238     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_11r */
  19239         soc_block_list[104],
  19240         soc_genreg,
  19241         1,
  19242         0,
  19243         0x255,
  19244         SOC_REG_FLAG_RO |
  19245                           SOC_REG_FLAG_WO,
  19246         0,
  19247         1,
  19248         soc_BRDC_DCL_CONNECTIVITY_LINK_11r_fields,
  19249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19250         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19251         -1,
  19252         -1,
  19253     },
  19254 #endif /* chips */
  19255 
  19256 #if defined(BCM_88950_A0)
  19257     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_12r */
  19258         soc_block_list[104],
  19259         soc_genreg,
  19260         1,
  19261         0,
  19262         0x256,
  19263         SOC_REG_FLAG_RO |
  19264                           SOC_REG_FLAG_WO,
  19265         0,
  19266         1,
  19267         soc_BRDC_DCL_CONNECTIVITY_LINK_12r_fields,
  19268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19269         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19270         -1,
  19271         -1,
  19272     },
  19273 #endif /* chips */
  19274 
  19275 #if defined(BCM_88950_A0)
  19276     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_13r */
  19277         soc_block_list[104],
  19278         soc_genreg,
  19279         1,
  19280         0,
  19281         0x257,
  19282         SOC_REG_FLAG_RO |
  19283                           SOC_REG_FLAG_WO,
  19284         0,
  19285         1,
  19286         soc_BRDC_DCL_CONNECTIVITY_LINK_13r_fields,
  19287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19288         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19289         -1,
  19290         -1,
  19291     },
  19292 #endif /* chips */
  19293 
  19294 #if defined(BCM_88950_A0)
  19295     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_14r */
  19296         soc_block_list[104],
  19297         soc_genreg,
  19298         1,
  19299         0,
  19300         0x258,
  19301         SOC_REG_FLAG_RO |
  19302                           SOC_REG_FLAG_WO,
  19303         0,
  19304         1,
  19305         soc_BRDC_DCL_CONNECTIVITY_LINK_14r_fields,
  19306         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19307         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19308         -1,
  19309         -1,
  19310     },
  19311 #endif /* chips */
  19312 
  19313 #if defined(BCM_88950_A0)
  19314     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_15r */
  19315         soc_block_list[104],
  19316         soc_genreg,
  19317         1,
  19318         0,
  19319         0x259,
  19320         SOC_REG_FLAG_RO |
  19321                           SOC_REG_FLAG_WO,
  19322         0,
  19323         1,
  19324         soc_BRDC_DCL_CONNECTIVITY_LINK_15r_fields,
  19325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19326         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19327         -1,
  19328         -1,
  19329     },
  19330 #endif /* chips */
  19331 
  19332 #if defined(BCM_88950_A0)
  19333     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_16r */
  19334         soc_block_list[104],
  19335         soc_genreg,
  19336         1,
  19337         0,
  19338         0x25a,
  19339         SOC_REG_FLAG_RO |
  19340                           SOC_REG_FLAG_WO,
  19341         0,
  19342         1,
  19343         soc_BRDC_DCL_CONNECTIVITY_LINK_16r_fields,
  19344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19345         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19346         -1,
  19347         -1,
  19348     },
  19349 #endif /* chips */
  19350 
  19351 #if defined(BCM_88950_A0)
  19352     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_17r */
  19353         soc_block_list[104],
  19354         soc_genreg,
  19355         1,
  19356         0,
  19357         0x25b,
  19358         SOC_REG_FLAG_RO |
  19359                           SOC_REG_FLAG_WO,
  19360         0,
  19361         1,
  19362         soc_BRDC_DCL_CONNECTIVITY_LINK_17r_fields,
  19363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19364         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19365         -1,
  19366         -1,
  19367     },
  19368 #endif /* chips */
  19369 
  19370 #if defined(BCM_88950_A0)
  19371     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_18r */
  19372         soc_block_list[104],
  19373         soc_genreg,
  19374         1,
  19375         0,
  19376         0x25c,
  19377         SOC_REG_FLAG_RO |
  19378                           SOC_REG_FLAG_WO,
  19379         0,
  19380         1,
  19381         soc_BRDC_DCL_CONNECTIVITY_LINK_18r_fields,
  19382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19383         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19384         -1,
  19385         -1,
  19386     },
  19387 #endif /* chips */
  19388 
  19389 #if defined(BCM_88950_A0)
  19390     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_19r */
  19391         soc_block_list[104],
  19392         soc_genreg,
  19393         1,
  19394         0,
  19395         0x25d,
  19396         SOC_REG_FLAG_RO |
  19397                           SOC_REG_FLAG_WO,
  19398         0,
  19399         1,
  19400         soc_BRDC_DCL_CONNECTIVITY_LINK_19r_fields,
  19401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19402         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19403         -1,
  19404         -1,
  19405     },
  19406 #endif /* chips */
  19407 
  19408 #if defined(BCM_88950_A0)
  19409     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_20r */
  19410         soc_block_list[104],
  19411         soc_genreg,
  19412         1,
  19413         0,
  19414         0x25e,
  19415         SOC_REG_FLAG_RO |
  19416                           SOC_REG_FLAG_WO,
  19417         0,
  19418         1,
  19419         soc_BRDC_DCL_CONNECTIVITY_LINK_20r_fields,
  19420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19421         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19422         -1,
  19423         -1,
  19424     },
  19425 #endif /* chips */
  19426 
  19427 #if defined(BCM_88950_A0)
  19428     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_21r */
  19429         soc_block_list[104],
  19430         soc_genreg,
  19431         1,
  19432         0,
  19433         0x25f,
  19434         SOC_REG_FLAG_RO |
  19435                           SOC_REG_FLAG_WO,
  19436         0,
  19437         1,
  19438         soc_BRDC_DCL_CONNECTIVITY_LINK_21r_fields,
  19439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19440         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19441         -1,
  19442         -1,
  19443     },
  19444 #endif /* chips */
  19445 
  19446 #if defined(BCM_88950_A0)
  19447     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_22r */
  19448         soc_block_list[104],
  19449         soc_genreg,
  19450         1,
  19451         0,
  19452         0x260,
  19453         SOC_REG_FLAG_RO |
  19454                           SOC_REG_FLAG_WO,
  19455         0,
  19456         1,
  19457         soc_BRDC_DCL_CONNECTIVITY_LINK_22r_fields,
  19458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19459         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19460         -1,
  19461         -1,
  19462     },
  19463 #endif /* chips */
  19464 
  19465 #if defined(BCM_88950_A0)
  19466     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_23r */
  19467         soc_block_list[104],
  19468         soc_genreg,
  19469         1,
  19470         0,
  19471         0x261,
  19472         SOC_REG_FLAG_RO |
  19473                           SOC_REG_FLAG_WO,
  19474         0,
  19475         1,
  19476         soc_BRDC_DCL_CONNECTIVITY_LINK_23r_fields,
  19477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19478         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19479         -1,
  19480         -1,
  19481     },
  19482 #endif /* chips */
  19483 
  19484 #if defined(BCM_88950_A0)
  19485     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_24r */
  19486         soc_block_list[104],
  19487         soc_genreg,
  19488         1,
  19489         0,
  19490         0x262,
  19491         SOC_REG_FLAG_RO |
  19492                           SOC_REG_FLAG_WO,
  19493         0,
  19494         1,
  19495         soc_BRDC_DCL_CONNECTIVITY_LINK_24r_fields,
  19496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19497         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19498         -1,
  19499         -1,
  19500     },
  19501 #endif /* chips */
  19502 
  19503 #if defined(BCM_88950_A0)
  19504     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_25r */
  19505         soc_block_list[104],
  19506         soc_genreg,
  19507         1,
  19508         0,
  19509         0x263,
  19510         SOC_REG_FLAG_RO |
  19511                           SOC_REG_FLAG_WO,
  19512         0,
  19513         1,
  19514         soc_BRDC_DCL_CONNECTIVITY_LINK_25r_fields,
  19515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19516         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19517         -1,
  19518         -1,
  19519     },
  19520 #endif /* chips */
  19521 
  19522 #if defined(BCM_88950_A0)
  19523     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_26r */
  19524         soc_block_list[104],
  19525         soc_genreg,
  19526         1,
  19527         0,
  19528         0x264,
  19529         SOC_REG_FLAG_RO |
  19530                           SOC_REG_FLAG_WO,
  19531         0,
  19532         1,
  19533         soc_BRDC_DCL_CONNECTIVITY_LINK_26r_fields,
  19534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19535         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19536         -1,
  19537         -1,
  19538     },
  19539 #endif /* chips */
  19540 
  19541 #if defined(BCM_88950_A0)
  19542     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_27r */
  19543         soc_block_list[104],
  19544         soc_genreg,
  19545         1,
  19546         0,
  19547         0x265,
  19548         SOC_REG_FLAG_RO |
  19549                           SOC_REG_FLAG_WO,
  19550         0,
  19551         1,
  19552         soc_BRDC_DCL_CONNECTIVITY_LINK_27r_fields,
  19553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19554         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19555         -1,
  19556         -1,
  19557     },
  19558 #endif /* chips */
  19559 
  19560 #if defined(BCM_88950_A0)
  19561     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_28r */
  19562         soc_block_list[104],
  19563         soc_genreg,
  19564         1,
  19565         0,
  19566         0x266,
  19567         SOC_REG_FLAG_RO |
  19568                           SOC_REG_FLAG_WO,
  19569         0,
  19570         1,
  19571         soc_BRDC_DCL_CONNECTIVITY_LINK_28r_fields,
  19572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19573         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19574         -1,
  19575         -1,
  19576     },
  19577 #endif /* chips */
  19578 
  19579 #if defined(BCM_88950_A0)
  19580     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_29r */
  19581         soc_block_list[104],
  19582         soc_genreg,
  19583         1,
  19584         0,
  19585         0x267,
  19586         SOC_REG_FLAG_RO |
  19587                           SOC_REG_FLAG_WO,
  19588         0,
  19589         1,
  19590         soc_BRDC_DCL_CONNECTIVITY_LINK_29r_fields,
  19591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19592         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19593         -1,
  19594         -1,
  19595     },
  19596 #endif /* chips */
  19597 
  19598 #if defined(BCM_88950_A0)
  19599     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_30r */
  19600         soc_block_list[104],
  19601         soc_genreg,
  19602         1,
  19603         0,
  19604         0x268,
  19605         SOC_REG_FLAG_RO |
  19606                           SOC_REG_FLAG_WO,
  19607         0,
  19608         1,
  19609         soc_BRDC_DCL_CONNECTIVITY_LINK_30r_fields,
  19610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19611         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19612         -1,
  19613         -1,
  19614     },
  19615 #endif /* chips */
  19616 
  19617 #if defined(BCM_88950_A0)
  19618     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_31r */
  19619         soc_block_list[104],
  19620         soc_genreg,
  19621         1,
  19622         0,
  19623         0x269,
  19624         SOC_REG_FLAG_RO |
  19625                           SOC_REG_FLAG_WO,
  19626         0,
  19627         1,
  19628         soc_BRDC_DCL_CONNECTIVITY_LINK_31r_fields,
  19629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19630         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19631         -1,
  19632         -1,
  19633     },
  19634 #endif /* chips */
  19635 
  19636 #if defined(BCM_88950_A0)
  19637     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_32r */
  19638         soc_block_list[104],
  19639         soc_genreg,
  19640         1,
  19641         0,
  19642         0x26a,
  19643         SOC_REG_FLAG_RO |
  19644                           SOC_REG_FLAG_WO,
  19645         0,
  19646         1,
  19647         soc_BRDC_DCL_CONNECTIVITY_LINK_32r_fields,
  19648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19649         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19650         -1,
  19651         -1,
  19652     },
  19653 #endif /* chips */
  19654 
  19655 #if defined(BCM_88950_A0)
  19656     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_33r */
  19657         soc_block_list[104],
  19658         soc_genreg,
  19659         1,
  19660         0,
  19661         0x26b,
  19662         SOC_REG_FLAG_RO |
  19663                           SOC_REG_FLAG_WO,
  19664         0,
  19665         1,
  19666         soc_BRDC_DCL_CONNECTIVITY_LINK_33r_fields,
  19667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19668         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19669         -1,
  19670         -1,
  19671     },
  19672 #endif /* chips */
  19673 
  19674 #if defined(BCM_88950_A0)
  19675     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_34r */
  19676         soc_block_list[104],
  19677         soc_genreg,
  19678         1,
  19679         0,
  19680         0x26c,
  19681         SOC_REG_FLAG_RO |
  19682                           SOC_REG_FLAG_WO,
  19683         0,
  19684         1,
  19685         soc_BRDC_DCL_CONNECTIVITY_LINK_34r_fields,
  19686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19687         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19688         -1,
  19689         -1,
  19690     },
  19691 #endif /* chips */
  19692 
  19693 #if defined(BCM_88950_A0)
  19694     { /* SOC_REG_INT_BRDC_DCL_CONNECTIVITY_LINK_35r */
  19695         soc_block_list[104],
  19696         soc_genreg,
  19697         1,
  19698         0,
  19699         0x26d,
  19700         SOC_REG_FLAG_RO |
  19701                           SOC_REG_FLAG_WO,
  19702         0,
  19703         1,
  19704         soc_BRDC_DCL_CONNECTIVITY_LINK_35r_fields,
  19705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19706         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  19707         -1,
  19708         -1,
  19709     },
  19710 #endif /* chips */
  19711 
  19712 #if defined(BCM_88950_A0)
  19713     { /* SOC_REG_INT_BRDC_DCL_CPU_CELL_CNTr */
  19714         soc_block_list[104],
  19715         soc_genreg,
  19716         1,
  19717         0,
  19718         0x157,
  19719         SOC_REG_FLAG_RO |
  19720                           SOC_REG_FLAG_WO,
  19721         0,
  19722         2,
  19723         soc_BRDC_DCL_CPU_CELL_CNTr_fields,
  19724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19726         -1,
  19727         -1,
  19728     },
  19729 #endif /* chips */
  19730 
  19731 #if defined(BCM_88950_A0)
  19732     { /* SOC_REG_INT_BRDC_DCL_CPU_DATA_CELL_0r */
  19733         soc_block_list[104],
  19734         soc_genreg,
  19735         1,
  19736         0,
  19737         0x194,
  19738         SOC_REG_FLAG_ABOVE_64_BITS |
  19739                           SOC_REG_FLAG_WO,
  19740         0,
  19741         1,
  19742         soc_BRDC_DCL_CPU_DATA_CELL_0r_fields,
  19743         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19744         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19745         -1,
  19746         -1,
  19747     },
  19748 #endif /* chips */
  19749 
  19750 #if defined(BCM_88950_A0)
  19751     { /* SOC_REG_INT_BRDC_DCL_CPU_DATA_CELL_1r */
  19752         soc_block_list[104],
  19753         soc_genreg,
  19754         1,
  19755         0,
  19756         0x198,
  19757         SOC_REG_FLAG_ABOVE_64_BITS |
  19758                           SOC_REG_FLAG_WO,
  19759         0,
  19760         1,
  19761         soc_BRDC_DCL_CPU_DATA_CELL_1r_fields,
  19762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19763         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19764         -1,
  19765         -1,
  19766     },
  19767 #endif /* chips */
  19768 
  19769 #if defined(BCM_88950_A0)
  19770     { /* SOC_REG_INT_BRDC_DCL_CPU_DATA_CELL_2r */
  19771         soc_block_list[104],
  19772         soc_genreg,
  19773         1,
  19774         0,
  19775         0x19c,
  19776         SOC_REG_FLAG_ABOVE_64_BITS |
  19777                           SOC_REG_FLAG_WO,
  19778         0,
  19779         1,
  19780         soc_BRDC_DCL_CPU_DATA_CELL_2r_fields,
  19781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19782         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19783         -1,
  19784         -1,
  19785     },
  19786 #endif /* chips */
  19787 
  19788 #if defined(BCM_88950_A0)
  19789     { /* SOC_REG_INT_BRDC_DCL_CPU_DATA_CELL_3r */
  19790         soc_block_list[104],
  19791         soc_genreg,
  19792         1,
  19793         0,
  19794         0x1a0,
  19795         SOC_REG_FLAG_ABOVE_64_BITS |
  19796                           SOC_REG_FLAG_WO,
  19797         0,
  19798         1,
  19799         soc_BRDC_DCL_CPU_DATA_CELL_3r_fields,
  19800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19802         -1,
  19803         -1,
  19804     },
  19805 #endif /* chips */
  19806 
  19807 #if defined(BCM_88950_A0)
  19808     { /* SOC_REG_INT_BRDC_DCL_CPU_DATA_CELL_4r */
  19809         soc_block_list[104],
  19810         soc_genreg,
  19811         1,
  19812         0,
  19813         0x1a4,
  19814         SOC_REG_FLAG_ABOVE_64_BITS |
  19815                           SOC_REG_FLAG_WO,
  19816         0,
  19817         1,
  19818         soc_BRDC_DCL_CPU_DATA_CELL_4r_fields,
  19819         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19820         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  19821         -1,
  19822         -1,
  19823     },
  19824 #endif /* chips */
  19825 
  19826 #if defined(BCM_88950_A0)
  19827     { /* SOC_REG_INT_BRDC_DCL_DATA_CRC_ERR_CNTr */
  19828         soc_block_list[104],
  19829         soc_genreg,
  19830         1,
  19831         0,
  19832         0x21b,
  19833         SOC_REG_FLAG_RO |
  19834                           SOC_REG_FLAG_WO,
  19835         0,
  19836         2,
  19837         soc_BRDC_DCL_DATA_CRC_ERR_CNTr_fields,
  19838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19840         -1,
  19841         -1,
  19842     },
  19843 #endif /* chips */
  19844 
  19845 #if defined(BCM_88950_A0)
  19846     { /* SOC_REG_INT_BRDC_DCL_DCL_ENABLERS_REGISTERr */
  19847         soc_block_list[104],
  19848         soc_genreg,
  19849         1,
  19850         0,
  19851         0x101,
  19852         SOC_REG_FLAG_64_BITS |
  19853                           SOC_REG_FLAG_WO,
  19854         0,
  19855         5,
  19856         soc_BRDC_DCL_DCL_ENABLERS_REGISTERr_fields,
  19857         SOC_RESET_VAL_DEC(0x00000001, 0x00000003)
  19858         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000007)
  19859         -1,
  19860         -1,
  19861     },
  19862 #endif /* chips */
  19863 
  19864 #if defined(BCM_88950_A0)
  19865     { /* SOC_REG_INT_BRDC_DCL_DCL_LLFC_THr */
  19866         soc_block_list[104],
  19867         soc_genreg,
  19868         1,
  19869         0,
  19870         0x12a,
  19871         SOC_REG_FLAG_64_BITS |
  19872                           SOC_REG_FLAG_WO,
  19873         0,
  19874         6,
  19875         soc_BRDC_DCL_DCL_LLFC_THr_fields,
  19876         SOC_RESET_VAL_DEC(0xffffffff, 0x0fffffff)
  19877         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  19878         -1,
  19879         -1,
  19880     },
  19881 #endif /* chips */
  19882 
  19883 #if defined(BCM_88950_A0)
  19884     { /* SOC_REG_INT_BRDC_DCL_DCMB_ALM_FULL_Pr */
  19885         soc_block_list[104],
  19886         soc_genreg,
  19887         3,
  19888         0,
  19889         0x139,
  19890         SOC_REG_FLAG_ARRAY |
  19891                           SOC_REG_FLAG_WO |
  19892                           SOC_REG_FLAG_REG_ARRAY,
  19893         0,
  19894         2,
  19895         soc_BRDC_DCL_DCMB_ALM_FULL_Pr_fields,
  19896         SOC_RESET_VAL_DEC(0x000370dc, 0x00000000)
  19897         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  19898         -1,
  19899         -1,
  19900     },
  19901 #endif /* chips */
  19902 
  19903 #if defined(BCM_88950_A0)
  19904     { /* SOC_REG_INT_BRDC_DCL_DCMB_DCL_LLFC_THr */
  19905         soc_block_list[104],
  19906         soc_genreg,
  19907         1,
  19908         0,
  19909         0x12c,
  19910         SOC_REG_FLAG_64_BITS |
  19911                           SOC_REG_FLAG_WO,
  19912         0,
  19913         6,
  19914         soc_BRDC_DCL_DCMB_DCL_LLFC_THr_fields,
  19915         SOC_RESET_VAL_DEC(0xffffffff, 0x0fffffff)
  19916         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  19917         -1,
  19918         -1,
  19919     },
  19920 #endif /* chips */
  19921 
  19922 #if defined(BCM_88950_A0)
  19923     { /* SOC_REG_INT_BRDC_DCL_DCMB_DROPPED_IP_PR_P_0_CNTr */
  19924         soc_block_list[104],
  19925         soc_genreg,
  19926         4,
  19927         0,
  19928         0x17c,
  19929         SOC_REG_FLAG_ARRAY |
  19930                           SOC_REG_FLAG_RO |
  19931                           SOC_REG_FLAG_WO |
  19932                           SOC_REG_FLAG_REG_ARRAY,
  19933         0,
  19934         2,
  19935         soc_BRDC_DCL_DCMB_DROPPED_IP_PR_P_0_CNTr_fields,
  19936         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19937         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19938         -1,
  19939         -1,
  19940     },
  19941 #endif /* chips */
  19942 
  19943 #if defined(BCM_88950_A0)
  19944     { /* SOC_REG_INT_BRDC_DCL_DCMB_DROPPED_IP_PR_P_1_CNTr */
  19945         soc_block_list[104],
  19946         soc_genreg,
  19947         4,
  19948         0,
  19949         0x180,
  19950         SOC_REG_FLAG_ARRAY |
  19951                           SOC_REG_FLAG_RO |
  19952                           SOC_REG_FLAG_WO |
  19953                           SOC_REG_FLAG_REG_ARRAY,
  19954         0,
  19955         2,
  19956         soc_BRDC_DCL_DCMB_DROPPED_IP_PR_P_1_CNTr_fields,
  19957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19958         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19959         -1,
  19960         -1,
  19961     },
  19962 #endif /* chips */
  19963 
  19964 #if defined(BCM_88950_A0)
  19965     { /* SOC_REG_INT_BRDC_DCL_DCMB_DROPPED_IP_PR_P_2_CNTr */
  19966         soc_block_list[104],
  19967         soc_genreg,
  19968         4,
  19969         0,
  19970         0x184,
  19971         SOC_REG_FLAG_ARRAY |
  19972                           SOC_REG_FLAG_RO |
  19973                           SOC_REG_FLAG_WO |
  19974                           SOC_REG_FLAG_REG_ARRAY,
  19975         0,
  19976         2,
  19977         soc_BRDC_DCL_DCMB_DROPPED_IP_PR_P_2_CNTr_fields,
  19978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  19979         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  19980         -1,
  19981         -1,
  19982     },
  19983 #endif /* chips */
  19984 
  19985 #if defined(BCM_88950_A0)
  19986     { /* SOC_REG_INT_BRDC_DCL_DCMB_DROPPED_SRC_P_CNTr */
  19987         soc_block_list[104],
  19988         soc_genreg,
  19989         3,
  19990         0,
  19991         0x18b,
  19992         SOC_REG_FLAG_ARRAY |
  19993                           SOC_REG_FLAG_RO |
  19994                           SOC_REG_FLAG_WO |
  19995                           SOC_REG_FLAG_REG_ARRAY,
  19996         0,
  19997         2,
  19998         soc_BRDC_DCL_DCMB_DROPPED_SRC_P_CNTr_fields,
  19999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20001         -1,
  20002         -1,
  20003     },
  20004 #endif /* chips */
  20005 
  20006 #if defined(BCM_88950_A0)
  20007     { /* SOC_REG_INT_BRDC_DCL_DCMB_FIFO_DEPTH_TYPEr */
  20008         soc_block_list[104],
  20009         soc_genreg,
  20010         2,
  20011         0,
  20012         0x128,
  20013         SOC_REG_FLAG_ARRAY |
  20014                           SOC_REG_FLAG_WO |
  20015                           SOC_REG_FLAG_REG_ARRAY,
  20016         0,
  20017         3,
  20018         soc_BRDC_DCL_DCMB_FIFO_DEPTH_TYPEr_fields,
  20019         SOC_RESET_VAL_DEC(0x10040100, 0x00000000)
  20020         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  20021         -1,
  20022         -1,
  20023     },
  20024 #endif /* chips */
  20025 
  20026 #if defined(BCM_88950_A0)
  20027     { /* SOC_REG_INT_BRDC_DCL_DCMB_LINK_WEIGHT_CONFIG_THRESHOLDSr */
  20028         soc_block_list[104],
  20029         soc_genreg,
  20030         1,
  20031         0,
  20032         0x216,
  20033         SOC_REG_FLAG_WO,
  20034         0,
  20035         2,
  20036         soc_BRDC_DCL_DCMB_LINK_WEIGHT_CONFIG_THRESHOLDSr_fields,
  20037         SOC_RESET_VAL_DEC(0x000fffff, 0x00000000)
  20038         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  20039         -1,
  20040         -1,
  20041     },
  20042 #endif /* chips */
  20043 
  20044 #if defined(BCM_88950_A0)
  20045     { /* SOC_REG_INT_BRDC_DCL_DCMB_MAX_OCCUPANCY_FIFO_Pr */
  20046         soc_block_list[104],
  20047         soc_genreg,
  20048         3,
  20049         0,
  20050         0x191,
  20051         SOC_REG_FLAG_ARRAY |
  20052                           SOC_REG_FLAG_RO |
  20053                           SOC_REG_FLAG_WO |
  20054                           SOC_REG_FLAG_REG_ARRAY,
  20055         0,
  20056         2,
  20057         soc_BRDC_DCL_DCMB_MAX_OCCUPANCY_FIFO_Pr_fields,
  20058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20059         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  20060         -1,
  20061         -1,
  20062     },
  20063 #endif /* chips */
  20064 
  20065 #if defined(BCM_88950_A0)
  20066     { /* SOC_REG_INT_BRDC_DCL_DCMB_TOTAL_IN_CELL_P_CNTr */
  20067         soc_block_list[104],
  20068         soc_genreg,
  20069         3,
  20070         0,
  20071         0x15b,
  20072         SOC_REG_FLAG_ARRAY |
  20073                           SOC_REG_FLAG_RO |
  20074                           SOC_REG_FLAG_WO |
  20075                           SOC_REG_FLAG_REG_ARRAY,
  20076         0,
  20077         2,
  20078         soc_BRDC_DCL_DCMB_TOTAL_IN_CELL_P_CNTr_fields,
  20079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20080         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20081         -1,
  20082         -1,
  20083     },
  20084 #endif /* chips */
  20085 
  20086 #if defined(BCM_88950_A0)
  20087     { /* SOC_REG_INT_BRDC_DCL_DCMB_TOTAL_OUT_CELL_P_CNTr */
  20088         soc_block_list[104],
  20089         soc_genreg,
  20090         3,
  20091         0,
  20092         0x164,
  20093         SOC_REG_FLAG_ARRAY |
  20094                           SOC_REG_FLAG_RO |
  20095                           SOC_REG_FLAG_WO |
  20096                           SOC_REG_FLAG_REG_ARRAY,
  20097         0,
  20098         2,
  20099         soc_BRDC_DCL_DCMB_TOTAL_OUT_CELL_P_CNTr_fields,
  20100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20101         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20102         -1,
  20103         -1,
  20104     },
  20105 #endif /* chips */
  20106 
  20107 #if defined(BCM_88950_A0)
  20108     { /* SOC_REG_INT_BRDC_DCL_DCMB_TOTAL_OUT_WORD_P_CNTr */
  20109         soc_block_list[104],
  20110         soc_genreg,
  20111         3,
  20112         0,
  20113         0x16a,
  20114         SOC_REG_FLAG_ARRAY |
  20115                           SOC_REG_FLAG_RO |
  20116                           SOC_REG_FLAG_WO |
  20117                           SOC_REG_FLAG_REG_ARRAY,
  20118         0,
  20119         2,
  20120         soc_BRDC_DCL_DCMB_TOTAL_OUT_WORD_P_CNTr_fields,
  20121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20122         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20123         -1,
  20124         -1,
  20125     },
  20126 #endif /* chips */
  20127 
  20128 #if defined(BCM_88950_A0)
  20129     { /* SOC_REG_INT_BRDC_DCL_DCMB_TYPE_0_DRP_PRI_Pr */
  20130         soc_block_list[104],
  20131         soc_genreg,
  20132         3,
  20133         0,
  20134         0x231,
  20135         SOC_REG_FLAG_64_BITS |
  20136                           SOC_REG_FLAG_ARRAY |
  20137                           SOC_REG_FLAG_WO |
  20138                           SOC_REG_FLAG_REG_ARRAY,
  20139         0,
  20140         4,
  20141         soc_BRDC_DCL_DCMB_TYPE_0_DRP_PRI_Pr_fields,
  20142         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  20143         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  20144         -1,
  20145         -1,
  20146     },
  20147 #endif /* chips */
  20148 
  20149 #if defined(BCM_88950_A0)
  20150     { /* SOC_REG_INT_BRDC_DCL_DCMB_TYPE_0_GCI_TH_Pr */
  20151         soc_block_list[104],
  20152         soc_genreg,
  20153         3,
  20154         0,
  20155         0x148,
  20156         SOC_REG_FLAG_ARRAY |
  20157                           SOC_REG_FLAG_WO |
  20158                           SOC_REG_FLAG_REG_ARRAY,
  20159         0,
  20160         3,
  20161         soc_BRDC_DCL_DCMB_TYPE_0_GCI_TH_Pr_fields,
  20162         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  20163         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  20164         -1,
  20165         -1,
  20166     },
  20167 #endif /* chips */
  20168 
  20169 #if defined(BCM_88950_A0)
  20170     { /* SOC_REG_INT_BRDC_DCL_DCMB_TYPE_0_RCI_TH_Pr */
  20171         soc_block_list[104],
  20172         soc_genreg,
  20173         3,
  20174         0,
  20175         0x14e,
  20176         SOC_REG_FLAG_ARRAY |
  20177                           SOC_REG_FLAG_WO |
  20178                           SOC_REG_FLAG_REG_ARRAY,
  20179         0,
  20180         3,
  20181         soc_BRDC_DCL_DCMB_TYPE_0_RCI_TH_Pr_fields,
  20182         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  20183         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  20184         -1,
  20185         -1,
  20186     },
  20187 #endif /* chips */
  20188 
  20189 #if defined(BCM_88950_A0)
  20190     { /* SOC_REG_INT_BRDC_DCL_DCMB_TYPE_1_DRP_PRI_Pr */
  20191         soc_block_list[104],
  20192         soc_genreg,
  20193         3,
  20194         0,
  20195         0x237,
  20196         SOC_REG_FLAG_64_BITS |
  20197                           SOC_REG_FLAG_ARRAY |
  20198                           SOC_REG_FLAG_WO |
  20199                           SOC_REG_FLAG_REG_ARRAY,
  20200         0,
  20201         4,
  20202         soc_BRDC_DCL_DCMB_TYPE_1_DRP_PRI_Pr_fields,
  20203         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  20204         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  20205         -1,
  20206         -1,
  20207     },
  20208 #endif /* chips */
  20209 
  20210 #if defined(BCM_88950_A0)
  20211     { /* SOC_REG_INT_BRDC_DCL_DCMB_TYPE_1_GCI_TH_Pr */
  20212         soc_block_list[104],
  20213         soc_genreg,
  20214         3,
  20215         0,
  20216         0x14b,
  20217         SOC_REG_FLAG_ARRAY |
  20218                           SOC_REG_FLAG_WO |
  20219                           SOC_REG_FLAG_REG_ARRAY,
  20220         0,
  20221         3,
  20222         soc_BRDC_DCL_DCMB_TYPE_1_GCI_TH_Pr_fields,
  20223         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  20224         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  20225         -1,
  20226         -1,
  20227     },
  20228 #endif /* chips */
  20229 
  20230 #if defined(BCM_88950_A0)
  20231     { /* SOC_REG_INT_BRDC_DCL_DCMB_TYPE_1_RCI_TH_Pr */
  20232         soc_block_list[104],
  20233         soc_genreg,
  20234         3,
  20235         0,
  20236         0x151,
  20237         SOC_REG_FLAG_ARRAY |
  20238                           SOC_REG_FLAG_WO |
  20239                           SOC_REG_FLAG_REG_ARRAY,
  20240         0,
  20241         3,
  20242         soc_BRDC_DCL_DCMB_TYPE_1_RCI_TH_Pr_fields,
  20243         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  20244         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  20245         -1,
  20246         -1,
  20247     },
  20248 #endif /* chips */
  20249 
  20250 #if defined(BCM_88950_A0)
  20251     { /* SOC_REG_INT_BRDC_DCL_DCMB_UNPACKED_CELL_P_CNTr */
  20252         soc_block_list[104],
  20253         soc_genreg,
  20254         3,
  20255         0,
  20256         0x161,
  20257         SOC_REG_FLAG_ARRAY |
  20258                           SOC_REG_FLAG_RO |
  20259                           SOC_REG_FLAG_WO |
  20260                           SOC_REG_FLAG_REG_ARRAY,
  20261         0,
  20262         2,
  20263         soc_BRDC_DCL_DCMB_UNPACKED_CELL_P_CNTr_fields,
  20264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20266         -1,
  20267         -1,
  20268     },
  20269 #endif /* chips */
  20270 
  20271 #if defined(BCM_88950_A0)
  20272     { /* SOC_REG_INT_BRDC_DCL_DLOP_RR_ENABLERSr */
  20273         soc_block_list[104],
  20274         soc_genreg,
  20275         1,
  20276         0,
  20277         0x103,
  20278         SOC_REG_FLAG_64_BITS |
  20279                           SOC_REG_FLAG_WO,
  20280         0,
  20281         6,
  20282         soc_BRDC_DCL_DLOP_RR_ENABLERSr_fields,
  20283         SOC_RESET_VAL_DEC(0xfffffff0, 0x000000ff)
  20284         SOC_RESET_MASK_DEC(0xfffffff7, 0x000000ff)
  20285         -1,
  20286         -1,
  20287     },
  20288 #endif /* chips */
  20289 
  20290 #if defined(BCM_88950_A0)
  20291     { /* SOC_REG_INT_BRDC_DCL_DROPPED_IP_PR_P_0_CNTr */
  20292         soc_block_list[104],
  20293         soc_genreg,
  20294         4,
  20295         0,
  20296         0x170,
  20297         SOC_REG_FLAG_ARRAY |
  20298                           SOC_REG_FLAG_RO |
  20299                           SOC_REG_FLAG_WO |
  20300                           SOC_REG_FLAG_REG_ARRAY,
  20301         0,
  20302         2,
  20303         soc_BRDC_DCL_DROPPED_IP_PR_P_0_CNTr_fields,
  20304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20306         -1,
  20307         -1,
  20308     },
  20309 #endif /* chips */
  20310 
  20311 #if defined(BCM_88950_A0)
  20312     { /* SOC_REG_INT_BRDC_DCL_DROPPED_IP_PR_P_1_CNTr */
  20313         soc_block_list[104],
  20314         soc_genreg,
  20315         4,
  20316         0,
  20317         0x174,
  20318         SOC_REG_FLAG_ARRAY |
  20319                           SOC_REG_FLAG_RO |
  20320                           SOC_REG_FLAG_WO |
  20321                           SOC_REG_FLAG_REG_ARRAY,
  20322         0,
  20323         2,
  20324         soc_BRDC_DCL_DROPPED_IP_PR_P_1_CNTr_fields,
  20325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20327         -1,
  20328         -1,
  20329     },
  20330 #endif /* chips */
  20331 
  20332 #if defined(BCM_88950_A0)
  20333     { /* SOC_REG_INT_BRDC_DCL_DROPPED_IP_PR_P_2_CNTr */
  20334         soc_block_list[104],
  20335         soc_genreg,
  20336         4,
  20337         0,
  20338         0x178,
  20339         SOC_REG_FLAG_ARRAY |
  20340                           SOC_REG_FLAG_RO |
  20341                           SOC_REG_FLAG_WO |
  20342                           SOC_REG_FLAG_REG_ARRAY,
  20343         0,
  20344         2,
  20345         soc_BRDC_DCL_DROPPED_IP_PR_P_2_CNTr_fields,
  20346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20347         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20348         -1,
  20349         -1,
  20350     },
  20351 #endif /* chips */
  20352 
  20353 #if defined(BCM_88950_A0)
  20354     { /* SOC_REG_INT_BRDC_DCL_DROPPED_SRC_P_CNTr */
  20355         soc_block_list[104],
  20356         soc_genreg,
  20357         3,
  20358         0,
  20359         0x188,
  20360         SOC_REG_FLAG_ARRAY |
  20361                           SOC_REG_FLAG_RO |
  20362                           SOC_REG_FLAG_WO |
  20363                           SOC_REG_FLAG_REG_ARRAY,
  20364         0,
  20365         2,
  20366         soc_BRDC_DCL_DROPPED_SRC_P_CNTr_fields,
  20367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20368         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20369         -1,
  20370         -1,
  20371     },
  20372 #endif /* chips */
  20373 
  20374 #if defined(BCM_88950_A0)
  20375     { /* SOC_REG_INT_BRDC_DCL_DROP_CPU_CELL_CNTr */
  20376         soc_block_list[104],
  20377         soc_genreg,
  20378         1,
  20379         0,
  20380         0x156,
  20381         SOC_REG_FLAG_RO |
  20382                           SOC_REG_FLAG_WO,
  20383         0,
  20384         2,
  20385         soc_BRDC_DCL_DROP_CPU_CELL_CNTr_fields,
  20386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20388         -1,
  20389         -1,
  20390     },
  20391 #endif /* chips */
  20392 
  20393 #if defined(BCM_88950_A0)
  20394     { /* SOC_REG_INT_BRDC_DCL_ECC_1B_ERR_CNTr */
  20395         soc_block_list[104],
  20396         soc_genreg,
  20397         1,
  20398         0,
  20399         0x94,
  20400         SOC_REG_FLAG_64_BITS |
  20401                           SOC_REG_FLAG_RO |
  20402                           SOC_REG_FLAG_WO,
  20403         0,
  20404         4,
  20405         soc_BRDC_CCS_ECC_1B_ERR_CNTr_fields,
  20406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20407         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  20408         -1,
  20409         -1,
  20410     },
  20411 #endif /* chips */
  20412 
  20413 #if defined(BCM_88950_A0)
  20414     { /* SOC_REG_INT_BRDC_DCL_ECC_2B_ERR_CNTr */
  20415         soc_block_list[104],
  20416         soc_genreg,
  20417         1,
  20418         0,
  20419         0x96,
  20420         SOC_REG_FLAG_64_BITS |
  20421                           SOC_REG_FLAG_RO |
  20422                           SOC_REG_FLAG_WO,
  20423         0,
  20424         4,
  20425         soc_BRDC_CCS_ECC_2B_ERR_CNTr_fields,
  20426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20427         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  20428         -1,
  20429         -1,
  20430     },
  20431 #endif /* chips */
  20432 
  20433 #if defined(BCM_88950_A0)
  20434     { /* SOC_REG_INT_BRDC_DCL_ECC_ERR_1B_INITIATEr */
  20435         soc_block_list[104],
  20436         soc_genreg,
  20437         1,
  20438         0,
  20439         0xa4,
  20440         SOC_REG_FLAG_WO,
  20441         0,
  20442         15,
  20443         soc_BRDC_DCL_ECC_ERR_1B_INITIATEr_fields,
  20444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20445         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  20446         -1,
  20447         -1,
  20448     },
  20449 #endif /* chips */
  20450 
  20451 #if defined(BCM_88950_A0)
  20452     { /* SOC_REG_INT_BRDC_DCL_ECC_ERR_1B_MONITOR_MEM_MASKr */
  20453         soc_block_list[104],
  20454         soc_genreg,
  20455         1,
  20456         0,
  20457         0x9a,
  20458         SOC_REG_FLAG_WO,
  20459         0,
  20460         23,
  20461         soc_BRDC_DCL_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  20462         SOC_RESET_VAL_DEC(0x007fffff, 0x00000000)
  20463         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  20464         -1,
  20465         -1,
  20466     },
  20467 #endif /* chips */
  20468 
  20469 #if defined(BCM_88950_A0)
  20470     { /* SOC_REG_INT_BRDC_DCL_ECC_ERR_2B_INITIATEr */
  20471         soc_block_list[104],
  20472         soc_genreg,
  20473         1,
  20474         0,
  20475         0xa6,
  20476         SOC_REG_FLAG_WO,
  20477         0,
  20478         15,
  20479         soc_BRDC_DCL_ECC_ERR_2B_INITIATEr_fields,
  20480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20481         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  20482         -1,
  20483         -1,
  20484     },
  20485 #endif /* chips */
  20486 
  20487 #if defined(BCM_88950_A0)
  20488     { /* SOC_REG_INT_BRDC_DCL_ECC_ERR_2B_MONITOR_MEM_MASKr */
  20489         soc_block_list[104],
  20490         soc_genreg,
  20491         1,
  20492         0,
  20493         0x9c,
  20494         SOC_REG_FLAG_WO,
  20495         0,
  20496         23,
  20497         soc_BRDC_DCL_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  20498         SOC_RESET_VAL_DEC(0x007fffff, 0x00000000)
  20499         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  20500         -1,
  20501         -1,
  20502     },
  20503 #endif /* chips */
  20504 
  20505 #if defined(BCM_88950_A0)
  20506     { /* SOC_REG_INT_BRDC_DCL_ECC_INTERRUPT_REGISTERr */
  20507         soc_block_list[104],
  20508         soc_genreg,
  20509         1,
  20510         0,
  20511         0x7,
  20512         SOC_REG_FLAG_WO |
  20513                           SOC_REG_FLAG_INTERRUPT,
  20514         0,
  20515         3,
  20516         soc_BRDC_DCH_ECC_INTERRUPT_REGISTERr_fields,
  20517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20518         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  20519         -1,
  20520         -1,
  20521     },
  20522 #endif /* chips */
  20523 
  20524 #if defined(BCM_88950_A0)
  20525     { /* SOC_REG_INT_BRDC_DCL_ECC_INTERRUPT_REGISTER_MASKr */
  20526         soc_block_list[104],
  20527         soc_genreg,
  20528         1,
  20529         0,
  20530         0x17,
  20531         SOC_REG_FLAG_WO,
  20532         0,
  20533         3,
  20534         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_MASKr_fields,
  20535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20536         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  20537         -1,
  20538         -1,
  20539     },
  20540 #endif /* chips */
  20541 
  20542 #if defined(BCM_88950_A0)
  20543     { /* SOC_REG_INT_BRDC_DCL_ECC_INTERRUPT_REGISTER_TESTr */
  20544         soc_block_list[104],
  20545         soc_genreg,
  20546         1,
  20547         0,
  20548         0x1f,
  20549         SOC_REG_FLAG_WO,
  20550         0,
  20551         1,
  20552         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_TESTr_fields,
  20553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20554         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20555         -1,
  20556         -1,
  20557     },
  20558 #endif /* chips */
  20559 
  20560 #if defined(BCM_88950_A0)
  20561     { /* SOC_REG_INT_BRDC_DCL_ENABLE_DYNAMIC_MEMORY_ACCESSr */
  20562         soc_block_list[104],
  20563         soc_genreg,
  20564         1,
  20565         0,
  20566         0x84,
  20567         SOC_REG_FLAG_WO,
  20568         0,
  20569         1,
  20570         soc_BRDC_DCL_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  20571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20572         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20573         -1,
  20574         -1,
  20575     },
  20576 #endif /* chips */
  20577 
  20578 #if defined(BCM_88950_A0)
  20579     { /* SOC_REG_INT_BRDC_DCL_ERROR_INITIATION_DATAr */
  20580         soc_block_list[104],
  20581         soc_genreg,
  20582         1,
  20583         0,
  20584         0xa3,
  20585         SOC_REG_FLAG_WO,
  20586         0,
  20587         1,
  20588         soc_BRDC_CCS_ERROR_INITIATION_DATAr_fields,
  20589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20590         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20591         -1,
  20592         -1,
  20593     },
  20594 #endif /* chips */
  20595 
  20596 #if defined(BCM_88950_A0)
  20597     { /* SOC_REG_INT_BRDC_DCL_FIFO_DEPTH_TYPEr */
  20598         soc_block_list[104],
  20599         soc_genreg,
  20600         2,
  20601         0,
  20602         0x126,
  20603         SOC_REG_FLAG_ARRAY |
  20604                           SOC_REG_FLAG_WO |
  20605                           SOC_REG_FLAG_REG_ARRAY,
  20606         0,
  20607         3,
  20608         soc_BRDC_DCL_FIFO_DEPTH_TYPEr_fields,
  20609         SOC_RESET_VAL_DEC(0x10040100, 0x00000000)
  20610         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  20611         -1,
  20612         -1,
  20613     },
  20614 #endif /* chips */
  20615 
  20616 #if defined(BCM_88950_A0)
  20617     { /* SOC_REG_INT_BRDC_DCL_GLOBAL_GENERAL_FE_CFG_1r */
  20618         soc_block_list[104],
  20619         soc_genreg,
  20620         1,
  20621         0,
  20622         0xf4,
  20623         SOC_REG_FLAG_WO,
  20624         0,
  20625         8,
  20626         soc_BRDC_DCH_GLOBAL_GENERAL_FE_CFG_1r_fields,
  20627         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  20628         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  20629         -1,
  20630         -1,
  20631     },
  20632 #endif /* chips */
  20633 
  20634 #if defined(BCM_88950_A0)
  20635     { /* SOC_REG_INT_BRDC_DCL_GLOBAL_MEM_OPTIONSr */
  20636         soc_block_list[104],
  20637         soc_genreg,
  20638         1,
  20639         0,
  20640         0xc0,
  20641         SOC_REG_FLAG_WO,
  20642         0,
  20643         3,
  20644         soc_BRDC_DCH_GLOBAL_MEM_OPTIONSr_fields,
  20645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20646         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  20647         -1,
  20648         -1,
  20649     },
  20650 #endif /* chips */
  20651 
  20652 #if defined(BCM_88950_A0)
  20653     { /* SOC_REG_INT_BRDC_DCL_GTIMER_CONFIGURATIONr */
  20654         soc_block_list[104],
  20655         soc_genreg,
  20656         1,
  20657         0,
  20658         0x88,
  20659         SOC_REG_FLAG_WO,
  20660         0,
  20661         3,
  20662         soc_BRDC_CCS_GTIMER_CONFIGURATIONr_fields,
  20663         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  20664         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20665         -1,
  20666         -1,
  20667     },
  20668 #endif /* chips */
  20669 
  20670 #if defined(BCM_88950_A0)
  20671     { /* SOC_REG_INT_BRDC_DCL_GTIMER_TRIGGERr */
  20672         soc_block_list[104],
  20673         soc_genreg,
  20674         1,
  20675         0,
  20676         0x89,
  20677         SOC_REG_FLAG_RO |
  20678                           SOC_REG_FLAG_WO,
  20679         0,
  20680         1,
  20681         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  20682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20683         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20684         -1,
  20685         -1,
  20686     },
  20687 #endif /* chips */
  20688 
  20689 #if defined(BCM_88950_A0)
  20690     { /* SOC_REG_INT_BRDC_DCL_INDIRECT_COMMANDr */
  20691         soc_block_list[104],
  20692         soc_genreg,
  20693         1,
  20694         0,
  20695         0x80,
  20696         SOC_REG_FLAG_WO,
  20697         0,
  20698         5,
  20699         soc_BRDC_DCL_INDIRECT_COMMANDr_fields,
  20700         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  20701         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20702         -1,
  20703         -1,
  20704     },
  20705 #endif /* chips */
  20706 
  20707 #if defined(BCM_88950_A0)
  20708     { /* SOC_REG_INT_BRDC_DCL_INDIRECT_COMMAND_ADDRESSr */
  20709         soc_block_list[104],
  20710         soc_genreg,
  20711         1,
  20712         0,
  20713         0x81,
  20714         SOC_REG_FLAG_WO,
  20715         0,
  20716         2,
  20717         soc_BRDC_DCL_INDIRECT_COMMAND_ADDRESSr_fields,
  20718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20719         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20720         -1,
  20721         -1,
  20722     },
  20723 #endif /* chips */
  20724 
  20725 #if defined(BCM_88950_A0)
  20726     { /* SOC_REG_INT_BRDC_DCL_INDIRECT_COMMAND_DATA_INCREMENTr */
  20727         soc_block_list[104],
  20728         soc_genreg,
  20729         1,
  20730         0,
  20731         0x82,
  20732         SOC_REG_FLAG_64_BITS |
  20733                           SOC_REG_FLAG_WO,
  20734         0,
  20735         1,
  20736         soc_BRDC_DCL_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  20737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20738         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  20739         -1,
  20740         -1,
  20741     },
  20742 #endif /* chips */
  20743 
  20744 #if defined(BCM_88950_A0)
  20745     { /* SOC_REG_INT_BRDC_DCL_INDIRECT_COMMAND_WIDE_MEMr */
  20746         soc_block_list[104],
  20747         soc_genreg,
  20748         1,
  20749         0,
  20750         0x41,
  20751         SOC_REG_FLAG_WO,
  20752         0,
  20753         1,
  20754         soc_BRDC_DCL_INDIRECT_COMMAND_WIDE_MEMr_fields,
  20755         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20756         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  20757         -1,
  20758         -1,
  20759     },
  20760 #endif /* chips */
  20761 
  20762 #if defined(BCM_88950_A0)
  20763     { /* SOC_REG_INT_BRDC_DCL_INDIRECT_COMMAND_WR_DATAr */
  20764         soc_block_list[104],
  20765         soc_genreg,
  20766         1,
  20767         0,
  20768         0x20,
  20769         SOC_REG_FLAG_ABOVE_64_BITS |
  20770                           SOC_REG_FLAG_WO,
  20771         0,
  20772         1,
  20773         soc_BRDC_DCL_INDIRECT_COMMAND_WR_DATAr_fields,
  20774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20775         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  20776         -1,
  20777         -1,
  20778     },
  20779 #endif /* chips */
  20780 
  20781 #if defined(BCM_88950_A0)
  20782     { /* SOC_REG_INT_BRDC_DCL_INDIRECT_FORCE_BUBBLEr */
  20783         soc_block_list[104],
  20784         soc_genreg,
  20785         1,
  20786         0,
  20787         0x83,
  20788         SOC_REG_FLAG_WO,
  20789         0,
  20790         4,
  20791         soc_BRDC_DCL_INDIRECT_FORCE_BUBBLEr_fields,
  20792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20793         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  20794         -1,
  20795         -1,
  20796     },
  20797 #endif /* chips */
  20798 
  20799 #if defined(BCM_88950_A0)
  20800     { /* SOC_REG_INT_BRDC_DCL_INTERRUPT_MASK_REGISTERr */
  20801         soc_block_list[104],
  20802         soc_genreg,
  20803         1,
  20804         0,
  20805         0x10,
  20806         SOC_REG_FLAG_WO,
  20807         0,
  20808         27,
  20809         soc_BRDC_DCL_INTERRUPT_MASK_REGISTERr_fields,
  20810         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20811         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  20812         -1,
  20813         -1,
  20814     },
  20815 #endif /* chips */
  20816 
  20817 #if defined(BCM_88950_A0)
  20818     { /* SOC_REG_INT_BRDC_DCL_INTERRUPT_REGISTERr */
  20819         soc_block_list[104],
  20820         soc_genreg,
  20821         1,
  20822         0,
  20823         0,
  20824         SOC_REG_FLAG_WO |
  20825                           SOC_REG_FLAG_INTERRUPT,
  20826         0,
  20827         27,
  20828         soc_BRDC_DCL_INTERRUPT_REGISTERr_fields,
  20829         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20830         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  20831         -1,
  20832         -1,
  20833     },
  20834 #endif /* chips */
  20835 
  20836 #if defined(BCM_88950_A0)
  20837     { /* SOC_REG_INT_BRDC_DCL_INTERRUPT_REGISTER_TESTr */
  20838         soc_block_list[104],
  20839         soc_genreg,
  20840         1,
  20841         0,
  20842         0x18,
  20843         SOC_REG_FLAG_WO,
  20844         0,
  20845         1,
  20846         soc_BRDC_CCS_INTERRUPT_REGISTER_TESTr_fields,
  20847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20848         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  20849         -1,
  20850         -1,
  20851     },
  20852 #endif /* chips */
  20853 
  20854 #if defined(BCM_88950_A0)
  20855     { /* SOC_REG_INT_BRDC_DCL_LINKS_WEIGHT_CONFIGr */
  20856         soc_block_list[104],
  20857         soc_genreg,
  20858         36,
  20859         0,
  20860         0x1a9,
  20861         SOC_REG_FLAG_ARRAY |
  20862                           SOC_REG_FLAG_WO |
  20863                           SOC_REG_FLAG_REG_ARRAY,
  20864         0,
  20865         1,
  20866         soc_BRDC_DCL_LINKS_WEIGHT_CONFIGr_fields,
  20867         SOC_RESET_VAL_DEC(0x001fffff, 0x00000000)
  20868         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  20869         -1,
  20870         -1,
  20871     },
  20872 #endif /* chips */
  20873 
  20874 #if defined(BCM_88950_A0)
  20875     { /* SOC_REG_INT_BRDC_DCL_LINKS_WEIGHT_CONFIG_P_0_GT_P_1r */
  20876         soc_block_list[104],
  20877         soc_genreg,
  20878         36,
  20879         0,
  20880         0x1cd,
  20881         SOC_REG_FLAG_ARRAY |
  20882                           SOC_REG_FLAG_WO |
  20883                           SOC_REG_FLAG_REG_ARRAY,
  20884         0,
  20885         1,
  20886         soc_BRDC_DCL_LINKS_WEIGHT_CONFIG_P_0_GT_P_1r_fields,
  20887         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  20888         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  20889         -1,
  20890         -1,
  20891     },
  20892 #endif /* chips */
  20893 
  20894 #if defined(BCM_88950_A0)
  20895     { /* SOC_REG_INT_BRDC_DCL_LINKS_WEIGHT_CONFIG_P_1_GT_P_0r */
  20896         soc_block_list[104],
  20897         soc_genreg,
  20898         36,
  20899         0,
  20900         0x1f1,
  20901         SOC_REG_FLAG_ARRAY |
  20902                           SOC_REG_FLAG_WO |
  20903                           SOC_REG_FLAG_REG_ARRAY,
  20904         0,
  20905         1,
  20906         soc_BRDC_DCL_LINKS_WEIGHT_CONFIG_P_1_GT_P_0r_fields,
  20907         SOC_RESET_VAL_DEC(0x00003fff, 0x00000000)
  20908         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  20909         -1,
  20910         -1,
  20911     },
  20912 #endif /* chips */
  20913 
  20914 #if defined(BCM_88950_A0)
  20915     { /* SOC_REG_INT_BRDC_DCL_LINK_CELL_PACKING_ENr */
  20916         soc_block_list[104],
  20917         soc_genreg,
  20918         1,
  20919         0,
  20920         0x114,
  20921         SOC_REG_FLAG_64_BITS |
  20922                           SOC_REG_FLAG_WO,
  20923         0,
  20924         1,
  20925         soc_BRDC_DCL_LINK_CELL_PACKING_ENr_fields,
  20926         SOC_RESET_VAL_DEC(0xffffffff, 0x0000000f)
  20927         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  20928         -1,
  20929         -1,
  20930     },
  20931 #endif /* chips */
  20932 
  20933 #if defined(BCM_88950_A0)
  20934     { /* SOC_REG_INT_BRDC_DCL_LINK_EN_SIMPLE_UNPACKr */
  20935         soc_block_list[104],
  20936         soc_genreg,
  20937         1,
  20938         0,
  20939         0x116,
  20940         SOC_REG_FLAG_64_BITS |
  20941                           SOC_REG_FLAG_WO,
  20942         0,
  20943         1,
  20944         soc_BRDC_DCL_LINK_EN_SIMPLE_UNPACKr_fields,
  20945         SOC_RESET_VAL_DEC(0xffffffff, 0x0000000f)
  20946         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  20947         -1,
  20948         -1,
  20949     },
  20950 #endif /* chips */
  20951 
  20952 #if defined(BCM_88950_A0)
  20953     { /* SOC_REG_INT_BRDC_DCL_LINK_LEVEL_FLOW_CONTROL_Pr */
  20954         soc_block_list[104],
  20955         soc_genreg,
  20956         3,
  20957         0,
  20958         0x21c,
  20959         SOC_REG_FLAG_64_BITS |
  20960                           SOC_REG_FLAG_ARRAY |
  20961                           SOC_REG_FLAG_RO |
  20962                           SOC_REG_FLAG_WO |
  20963                           SOC_REG_FLAG_REG_ARRAY,
  20964         0,
  20965         1,
  20966         soc_BRDC_DCL_LINK_LEVEL_FLOW_CONTROL_Pr_fields,
  20967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20968         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  20969         -1,
  20970         -1,
  20971     },
  20972 #endif /* chips */
  20973 
  20974 #if defined(BCM_88950_A0)
  20975     { /* SOC_REG_INT_BRDC_DCL_LINK_TYPEr */
  20976         soc_block_list[104],
  20977         soc_genreg,
  20978         1,
  20979         0,
  20980         0x130,
  20981         SOC_REG_FLAG_64_BITS |
  20982                           SOC_REG_FLAG_WO,
  20983         0,
  20984         1,
  20985         soc_BRDC_DCL_LINK_TYPEr_fields,
  20986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  20987         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  20988         -1,
  20989         -1,
  20990     },
  20991 #endif /* chips */
  20992 
  20993 #if defined(BCM_88950_A0)
  20994     { /* SOC_REG_INT_BRDC_DCL_LINK_WEIGHT_CONFIG_THRESHOLDSr */
  20995         soc_block_list[104],
  20996         soc_genreg,
  20997         1,
  20998         0,
  20999         0x215,
  21000         SOC_REG_FLAG_WO,
  21001         0,
  21002         2,
  21003         soc_BRDC_DCL_LINK_WEIGHT_CONFIG_THRESHOLDSr_fields,
  21004         SOC_RESET_VAL_DEC(0x000fffff, 0x00000000)
  21005         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  21006         -1,
  21007         -1,
  21008     },
  21009 #endif /* chips */
  21010 
  21011 #if defined(BCM_88950_A0)
  21012     { /* SOC_REG_INT_BRDC_DCL_LLFC_RATE_CNT_Pr */
  21013         soc_block_list[104],
  21014         soc_genreg,
  21015         3,
  21016         0,
  21017         0x222,
  21018         SOC_REG_FLAG_ARRAY |
  21019                           SOC_REG_FLAG_RO |
  21020                           SOC_REG_FLAG_WO |
  21021                           SOC_REG_FLAG_REG_ARRAY,
  21022         0,
  21023         2,
  21024         soc_BRDC_DCL_LLFC_RATE_CNT_Pr_fields,
  21025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21026         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21027         -1,
  21028         -1,
  21029     },
  21030 #endif /* chips */
  21031 
  21032 #if defined(BCM_88950_A0)
  21033     { /* SOC_REG_INT_BRDC_DCL_MAX_OCCUPANCY_FIFO_Pr */
  21034         soc_block_list[104],
  21035         soc_genreg,
  21036         3,
  21037         0,
  21038         0x18e,
  21039         SOC_REG_FLAG_ARRAY |
  21040                           SOC_REG_FLAG_WO |
  21041                           SOC_REG_FLAG_REG_ARRAY,
  21042         0,
  21043         4,
  21044         soc_BRDC_DCL_MAX_OCCUPANCY_FIFO_Pr_fields,
  21045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21046         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21047         -1,
  21048         -1,
  21049     },
  21050 #endif /* chips */
  21051 
  21052 #if defined(BCM_88950_A0)
  21053     { /* SOC_REG_INT_BRDC_DCL_PCP_ERR_INFORMATIONr */
  21054         soc_block_list[104],
  21055         soc_genreg,
  21056         1,
  21057         0,
  21058         0x107,
  21059         SOC_REG_FLAG_RO |
  21060                           SOC_REG_FLAG_WO,
  21061         0,
  21062         6,
  21063         soc_BRDC_DCL_PCP_ERR_INFORMATIONr_fields,
  21064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21065         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21066         -1,
  21067         -1,
  21068     },
  21069 #endif /* chips */
  21070 
  21071 #if defined(BCM_88950_A0)
  21072     { /* SOC_REG_INT_BRDC_DCL_PCP_VALIDITY_CHECK_ENABLERSr */
  21073         soc_block_list[104],
  21074         soc_genreg,
  21075         1,
  21076         0,
  21077         0x106,
  21078         SOC_REG_FLAG_WO,
  21079         0,
  21080         4,
  21081         soc_BRDC_DCL_PCP_VALIDITY_CHECK_ENABLERSr_fields,
  21082         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  21083         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  21084         -1,
  21085         -1,
  21086     },
  21087 #endif /* chips */
  21088 
  21089 #if defined(BCM_88950_A0)
  21090     { /* SOC_REG_INT_BRDC_DCL_PIPES_MAP_ENr */
  21091         soc_block_list[104],
  21092         soc_genreg,
  21093         1,
  21094         0,
  21095         0x12e,
  21096         SOC_REG_FLAG_64_BITS |
  21097                           SOC_REG_FLAG_WO,
  21098         0,
  21099         1,
  21100         soc_BRDC_DCL_PIPES_MAP_ENr_fields,
  21101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21102         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  21103         -1,
  21104         -1,
  21105     },
  21106 #endif /* chips */
  21107 
  21108 #if defined(BCM_88950_A0)
  21109     { /* SOC_REG_INT_BRDC_DCL_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTERr */
  21110         soc_block_list[104],
  21111         soc_genreg,
  21112         1,
  21113         0,
  21114         0x245,
  21115         SOC_REG_FLAG_WO,
  21116         0,
  21117         6,
  21118         soc_BRDC_DCL_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTERr_fields,
  21119         SOC_RESET_VAL_DEC(0x01001000, 0x00000000)
  21120         SOC_RESET_MASK_DEC(0x01ff171f, 0x00000000)
  21121         -1,
  21122         -1,
  21123     },
  21124 #endif /* chips */
  21125 
  21126 #if defined(BCM_88950_A0)
  21127     { /* SOC_REG_INT_BRDC_DCL_REG_0100r */
  21128         soc_block_list[104],
  21129         soc_genreg,
  21130         1,
  21131         0,
  21132         0x100,
  21133         SOC_REG_FLAG_WO,
  21134         0,
  21135         1,
  21136         soc_BRDC_DCL_REG_0100r_fields,
  21137         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21138         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  21139         -1,
  21140         -1,
  21141     },
  21142 #endif /* chips */
  21143 
  21144 #if defined(BCM_88950_A0)
  21145     { /* SOC_REG_INT_BRDC_DCL_REG_0105r */
  21146         soc_block_list[104],
  21147         soc_genreg,
  21148         1,
  21149         0,
  21150         0x105,
  21151         SOC_REG_FLAG_WO,
  21152         0,
  21153         3,
  21154         soc_BRDC_DCL_REG_0105r_fields,
  21155         SOC_RESET_VAL_DEC(0x00002381, 0x00000000)
  21156         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  21157         -1,
  21158         -1,
  21159     },
  21160 #endif /* chips */
  21161 
  21162 #if defined(BCM_88950_A0)
  21163     { /* SOC_REG_INT_BRDC_DCL_REG_0108r */
  21164         soc_block_list[104],
  21165         soc_genreg,
  21166         1,
  21167         0,
  21168         0x108,
  21169         SOC_REG_FLAG_64_BITS |
  21170                           SOC_REG_FLAG_WO,
  21171         0,
  21172         1,
  21173         soc_BRDC_DCL_REG_0108r_fields,
  21174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21175         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  21176         -1,
  21177         -1,
  21178     },
  21179 #endif /* chips */
  21180 
  21181 #if defined(BCM_88950_A0)
  21182     { /* SOC_REG_INT_BRDC_DCL_REG_0118r */
  21183         soc_block_list[104],
  21184         soc_genreg,
  21185         1,
  21186         0,
  21187         0x118,
  21188         SOC_REG_FLAG_64_BITS |
  21189                           SOC_REG_FLAG_WO,
  21190         0,
  21191         8,
  21192         soc_BRDC_DCL_REG_0118r_fields,
  21193         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  21194         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  21195         -1,
  21196         -1,
  21197     },
  21198 #endif /* chips */
  21199 
  21200 #if defined(BCM_88950_A0)
  21201     { /* SOC_REG_INT_BRDC_DCL_REG_0120r */
  21202         soc_block_list[104],
  21203         soc_genreg,
  21204         1,
  21205         0,
  21206         0x120,
  21207         SOC_REG_FLAG_RO |
  21208                           SOC_REG_FLAG_WO,
  21209         0,
  21210         2,
  21211         soc_BRDC_CCS_REG_0112r_fields,
  21212         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21213         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21214         -1,
  21215         -1,
  21216     },
  21217 #endif /* chips */
  21218 
  21219 #if defined(BCM_88950_A0)
  21220     { /* SOC_REG_INT_BRDC_DCL_REG_0240r */
  21221         soc_block_list[104],
  21222         soc_genreg,
  21223         1,
  21224         0,
  21225         0x240,
  21226         SOC_REG_FLAG_RO |
  21227                           SOC_REG_FLAG_WO,
  21228         0,
  21229         2,
  21230         soc_BRDC_DCL_REG_023Er_fields,
  21231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21232         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21233         -1,
  21234         -1,
  21235     },
  21236 #endif /* chips */
  21237 
  21238 #if defined(BCM_88950_A0)
  21239     { /* SOC_REG_INT_BRDC_DCL_REG_011Ar */
  21240         soc_block_list[104],
  21241         soc_genreg,
  21242         1,
  21243         0,
  21244         0x11a,
  21245         SOC_REG_FLAG_ABOVE_64_BITS |
  21246                           SOC_REG_FLAG_WO,
  21247         0,
  21248         1,
  21249         soc_BRDC_DCL_REG_011Ar_fields,
  21250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21251         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21252         -1,
  21253         -1,
  21254     },
  21255 #endif /* chips */
  21256 
  21257 #if defined(BCM_88950_A0)
  21258     { /* SOC_REG_INT_BRDC_DCL_REG_011Dr */
  21259         soc_block_list[104],
  21260         soc_genreg,
  21261         1,
  21262         0,
  21263         0x11d,
  21264         SOC_REG_FLAG_ABOVE_64_BITS |
  21265                           SOC_REG_FLAG_WO,
  21266         0,
  21267         1,
  21268         soc_BRDC_DCL_REG_011Ar_fields,
  21269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21270         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21271         -1,
  21272         -1,
  21273     },
  21274 #endif /* chips */
  21275 
  21276 #if defined(BCM_88950_A0)
  21277     { /* SOC_REG_INT_BRDC_DCL_REG_023Er */
  21278         soc_block_list[104],
  21279         soc_genreg,
  21280         1,
  21281         0,
  21282         0x23e,
  21283         SOC_REG_FLAG_RO |
  21284                           SOC_REG_FLAG_WO,
  21285         0,
  21286         2,
  21287         soc_BRDC_DCL_REG_023Er_fields,
  21288         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21289         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  21290         -1,
  21291         -1,
  21292     },
  21293 #endif /* chips */
  21294 
  21295 #if defined(BCM_88950_A0)
  21296     { /* SOC_REG_INT_BRDC_DCL_REMOTE_PRI_PIPE_IDXr */
  21297         soc_block_list[104],
  21298         soc_genreg,
  21299         1,
  21300         0,
  21301         0x10e,
  21302         SOC_REG_FLAG_ABOVE_64_BITS |
  21303                           SOC_REG_FLAG_WO,
  21304         0,
  21305         1,
  21306         soc_BRDC_DCL_REMOTE_PRI_PIPE_IDXr_fields,
  21307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21308         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21309         -1,
  21310         -1,
  21311     },
  21312 #endif /* chips */
  21313 
  21314 #if defined(BCM_88950_A0)
  21315     { /* SOC_REG_INT_BRDC_DCL_REMOTE_SEC_PIPE_IDXr */
  21316         soc_block_list[104],
  21317         soc_genreg,
  21318         1,
  21319         0,
  21320         0x111,
  21321         SOC_REG_FLAG_ABOVE_64_BITS |
  21322                           SOC_REG_FLAG_WO,
  21323         0,
  21324         1,
  21325         soc_BRDC_DCL_REMOTE_SEC_PIPE_IDXr_fields,
  21326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21328         -1,
  21329         -1,
  21330     },
  21331 #endif /* chips */
  21332 
  21333 #if defined(BCM_88950_A0)
  21334     { /* SOC_REG_INT_BRDC_DCL_RESERVED_MIRROR_ADDRr */
  21335         soc_block_list[104],
  21336         soc_genreg,
  21337         1,
  21338         0,
  21339         0x85,
  21340         SOC_REG_FLAG_WO,
  21341         0,
  21342         2,
  21343         soc_BRDC_CCS_RESERVED_MIRROR_ADDRr_fields,
  21344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21345         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  21346         -1,
  21347         -1,
  21348     },
  21349 #endif /* chips */
  21350 
  21351 #if defined(BCM_88950_A0)
  21352     { /* SOC_REG_INT_BRDC_DCL_RESERVED_MTCPr */
  21353         soc_block_list[104],
  21354         soc_genreg,
  21355         1,
  21356         0,
  21357         0xad,
  21358         SOC_REG_FLAG_64_BITS |
  21359                           SOC_REG_FLAG_WO,
  21360         0,
  21361         18,
  21362         soc_BRDC_CCS_RESERVED_MTCPr_fields,
  21363         SOC_RESET_VAL_DEC(0x80000000, 0x00000001)
  21364         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
  21365         -1,
  21366         -1,
  21367     },
  21368 #endif /* chips */
  21369 
  21370 #if defined(BCM_88950_A0)
  21371     { /* SOC_REG_INT_BRDC_DCL_RESERVED_PCMI_0r */
  21372         soc_block_list[104],
  21373         soc_genreg,
  21374         1,
  21375         0,
  21376         0xb0,
  21377         SOC_REG_FLAG_WO,
  21378         0,
  21379         1,
  21380         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  21381         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  21382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21383         -1,
  21384         -1,
  21385     },
  21386 #endif /* chips */
  21387 
  21388 #if defined(BCM_88950_A0)
  21389     { /* SOC_REG_INT_BRDC_DCL_RESERVED_PCMI_1r */
  21390         soc_block_list[104],
  21391         soc_genreg,
  21392         1,
  21393         0,
  21394         0xb3,
  21395         SOC_REG_FLAG_WO,
  21396         0,
  21397         1,
  21398         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  21399         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  21400         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21401         -1,
  21402         -1,
  21403     },
  21404 #endif /* chips */
  21405 
  21406 #if defined(BCM_88950_A0)
  21407     { /* SOC_REG_INT_BRDC_DCL_RESERVED_PCMI_0_Sr */
  21408         soc_block_list[104],
  21409         soc_genreg,
  21410         1,
  21411         0,
  21412         0xb1,
  21413         SOC_REG_FLAG_RO |
  21414                           SOC_REG_FLAG_WO,
  21415         0,
  21416         3,
  21417         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  21418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21420         -1,
  21421         -1,
  21422     },
  21423 #endif /* chips */
  21424 
  21425 #if defined(BCM_88950_A0)
  21426     { /* SOC_REG_INT_BRDC_DCL_RESERVED_PCMI_0_Tr */
  21427         soc_block_list[104],
  21428         soc_genreg,
  21429         1,
  21430         0,
  21431         0xb2,
  21432         SOC_REG_FLAG_WO,
  21433         0,
  21434         2,
  21435         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  21436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21437         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  21438         -1,
  21439         -1,
  21440     },
  21441 #endif /* chips */
  21442 
  21443 #if defined(BCM_88950_A0)
  21444     { /* SOC_REG_INT_BRDC_DCL_RESERVED_PCMI_1_Sr */
  21445         soc_block_list[104],
  21446         soc_genreg,
  21447         1,
  21448         0,
  21449         0xb4,
  21450         SOC_REG_FLAG_RO |
  21451                           SOC_REG_FLAG_WO,
  21452         0,
  21453         3,
  21454         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  21455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21456         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21457         -1,
  21458         -1,
  21459     },
  21460 #endif /* chips */
  21461 
  21462 #if defined(BCM_88950_A0)
  21463     { /* SOC_REG_INT_BRDC_DCL_RESERVED_PCMI_1_Tr */
  21464         soc_block_list[104],
  21465         soc_genreg,
  21466         1,
  21467         0,
  21468         0xb5,
  21469         SOC_REG_FLAG_WO,
  21470         0,
  21471         2,
  21472         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  21473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21474         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  21475         -1,
  21476         -1,
  21477     },
  21478 #endif /* chips */
  21479 
  21480 #if defined(BCM_88950_A0)
  21481     { /* SOC_REG_INT_BRDC_DCL_RESERVED_SPARE_0r */
  21482         soc_block_list[104],
  21483         soc_genreg,
  21484         1,
  21485         0,
  21486         0x90,
  21487         SOC_REG_FLAG_WO,
  21488         0,
  21489         1,
  21490         soc_BRDC_CCS_RESERVED_SPARE_0r_fields,
  21491         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21492         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21493         -1,
  21494         -1,
  21495     },
  21496 #endif /* chips */
  21497 
  21498 #if defined(BCM_88950_A0)
  21499     { /* SOC_REG_INT_BRDC_DCL_RESERVED_SPARE_1r */
  21500         soc_block_list[104],
  21501         soc_genreg,
  21502         1,
  21503         0,
  21504         0x91,
  21505         SOC_REG_FLAG_WO,
  21506         0,
  21507         1,
  21508         soc_BRDC_CCS_RESERVED_SPARE_1r_fields,
  21509         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  21510         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21511         -1,
  21512         -1,
  21513     },
  21514 #endif /* chips */
  21515 
  21516 #if defined(BCM_88950_A0)
  21517     { /* SOC_REG_INT_BRDC_DCL_RESERVED_SPARE_2r */
  21518         soc_block_list[104],
  21519         soc_genreg,
  21520         1,
  21521         0,
  21522         0x92,
  21523         SOC_REG_FLAG_WO,
  21524         0,
  21525         1,
  21526         soc_BRDC_CCS_RESERVED_SPARE_2r_fields,
  21527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21528         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21529         -1,
  21530         -1,
  21531     },
  21532 #endif /* chips */
  21533 
  21534 #if defined(BCM_88950_A0)
  21535     { /* SOC_REG_INT_BRDC_DCL_RESERVED_SPARE_3r */
  21536         soc_block_list[104],
  21537         soc_genreg,
  21538         1,
  21539         0,
  21540         0x93,
  21541         SOC_REG_FLAG_WO,
  21542         0,
  21543         1,
  21544         soc_BRDC_CCS_RESERVED_SPARE_3r_fields,
  21545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21546         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21547         -1,
  21548         -1,
  21549     },
  21550 #endif /* chips */
  21551 
  21552 #if defined(BCM_88950_A0)
  21553     { /* SOC_REG_INT_BRDC_DCL_SBUS_BROADCAST_IDr */
  21554         soc_block_list[104],
  21555         soc_genreg,
  21556         1,
  21557         0,
  21558         0x86,
  21559         SOC_REG_FLAG_WO,
  21560         0,
  21561         1,
  21562         soc_BRDC_DCL_SBUS_BROADCAST_IDr_fields,
  21563         SOC_RESET_VAL_DEC(0x0000004f, 0x00000000)
  21564         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  21565         -1,
  21566         -1,
  21567     },
  21568 #endif /* chips */
  21569 
  21570 #if defined(BCM_88950_A0)
  21571     { /* SOC_REG_INT_BRDC_DCL_SBUS_LAST_IN_CHAINr */
  21572         soc_block_list[104],
  21573         soc_genreg,
  21574         1,
  21575         0,
  21576         0x87,
  21577         SOC_REG_FLAG_WO,
  21578         0,
  21579         1,
  21580         soc_BRDC_CCS_SBUS_LAST_IN_CHAINr_fields,
  21581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21582         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21583         -1,
  21584         -1,
  21585     },
  21586 #endif /* chips */
  21587 
  21588 #if defined(BCM_88950_A0)
  21589     { /* SOC_REG_INT_BRDC_DCL_SHAPER_AND_WFQ_CFGr */
  21590         soc_block_list[104],
  21591         soc_genreg,
  21592         1,
  21593         0,
  21594         0x217,
  21595         SOC_REG_FLAG_WO,
  21596         0,
  21597         5,
  21598         soc_BRDC_DCL_SHAPER_AND_WFQ_CFGr_fields,
  21599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21600         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  21601         -1,
  21602         -1,
  21603     },
  21604 #endif /* chips */
  21605 
  21606 #if defined(BCM_88950_A0)
  21607     { /* SOC_REG_INT_BRDC_DCL_TAG_PAR_ERR_CNT_Pr */
  21608         soc_block_list[104],
  21609         soc_genreg,
  21610         3,
  21611         0,
  21612         0x218,
  21613         SOC_REG_FLAG_ARRAY |
  21614                           SOC_REG_FLAG_RO |
  21615                           SOC_REG_FLAG_WO |
  21616                           SOC_REG_FLAG_REG_ARRAY,
  21617         0,
  21618         2,
  21619         soc_BRDC_DCL_TAG_PAR_ERR_CNT_Pr_fields,
  21620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21621         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21622         -1,
  21623         -1,
  21624     },
  21625 #endif /* chips */
  21626 
  21627 #if defined(BCM_88950_A0)
  21628     { /* SOC_REG_INT_BRDC_DCL_THREE_PIPES_BMPr */
  21629         soc_block_list[104],
  21630         soc_genreg,
  21631         1,
  21632         0,
  21633         0x10c,
  21634         SOC_REG_FLAG_64_BITS |
  21635                           SOC_REG_FLAG_WO,
  21636         0,
  21637         1,
  21638         soc_BRDC_DCL_THREE_PIPES_BMPr_fields,
  21639         SOC_RESET_VAL_DEC(0xffffffff, 0x0000000f)
  21640         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  21641         -1,
  21642         -1,
  21643     },
  21644 #endif /* chips */
  21645 
  21646 #if defined(BCM_88950_A0)
  21647     { /* SOC_REG_INT_BRDC_DCL_TOTAL_IN_CELL_P_CNTr */
  21648         soc_block_list[104],
  21649         soc_genreg,
  21650         3,
  21651         0,
  21652         0x158,
  21653         SOC_REG_FLAG_ARRAY |
  21654                           SOC_REG_FLAG_RO |
  21655                           SOC_REG_FLAG_WO |
  21656                           SOC_REG_FLAG_REG_ARRAY,
  21657         0,
  21658         2,
  21659         soc_BRDC_DCL_TOTAL_IN_CELL_P_CNTr_fields,
  21660         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21661         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21662         -1,
  21663         -1,
  21664     },
  21665 #endif /* chips */
  21666 
  21667 #if defined(BCM_88950_A0)
  21668     { /* SOC_REG_INT_BRDC_DCL_TOTAL_OUT_CELL_P_CNTr */
  21669         soc_block_list[104],
  21670         soc_genreg,
  21671         3,
  21672         0,
  21673         0x167,
  21674         SOC_REG_FLAG_ARRAY |
  21675                           SOC_REG_FLAG_RO |
  21676                           SOC_REG_FLAG_WO |
  21677                           SOC_REG_FLAG_REG_ARRAY,
  21678         0,
  21679         2,
  21680         soc_BRDC_DCL_TOTAL_OUT_CELL_P_CNTr_fields,
  21681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21682         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21683         -1,
  21684         -1,
  21685     },
  21686 #endif /* chips */
  21687 
  21688 #if defined(BCM_88950_A0)
  21689     { /* SOC_REG_INT_BRDC_DCL_TOTAL_OUT_WORD_P_CNTr */
  21690         soc_block_list[104],
  21691         soc_genreg,
  21692         3,
  21693         0,
  21694         0x16d,
  21695         SOC_REG_FLAG_ARRAY |
  21696                           SOC_REG_FLAG_RO |
  21697                           SOC_REG_FLAG_WO |
  21698                           SOC_REG_FLAG_REG_ARRAY,
  21699         0,
  21700         2,
  21701         soc_BRDC_DCL_TOTAL_OUT_WORD_P_CNTr_fields,
  21702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21703         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21704         -1,
  21705         -1,
  21706     },
  21707 #endif /* chips */
  21708 
  21709 #if defined(BCM_88950_A0)
  21710     { /* SOC_REG_INT_BRDC_DCL_TRANSMIT_CELL_OUTPUT_LINK_NUMBERr */
  21711         soc_block_list[104],
  21712         soc_genreg,
  21713         1,
  21714         0,
  21715         0x154,
  21716         SOC_REG_FLAG_WO,
  21717         0,
  21718         2,
  21719         soc_BRDC_DCL_TRANSMIT_CELL_OUTPUT_LINK_NUMBERr_fields,
  21720         SOC_RESET_VAL_DEC(0x00007f00, 0x00000000)
  21721         SOC_RESET_MASK_DEC(0x0000ff3f, 0x00000000)
  21722         -1,
  21723         -1,
  21724     },
  21725 #endif /* chips */
  21726 
  21727 #if defined(BCM_88950_A0)
  21728     { /* SOC_REG_INT_BRDC_DCL_TRANSMIT_DATA_CELL_TRIGGERr */
  21729         soc_block_list[104],
  21730         soc_genreg,
  21731         1,
  21732         0,
  21733         0x155,
  21734         SOC_REG_FLAG_WO,
  21735         0,
  21736         1,
  21737         soc_BRDC_DCL_TRANSMIT_DATA_CELL_TRIGGERr_fields,
  21738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21739         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  21740         -1,
  21741         -1,
  21742     },
  21743 #endif /* chips */
  21744 
  21745 #if defined(BCM_88950_A0)
  21746     { /* SOC_REG_INT_BRDC_DCL_TWO_PIPES_BMPr */
  21747         soc_block_list[104],
  21748         soc_genreg,
  21749         1,
  21750         0,
  21751         0x10a,
  21752         SOC_REG_FLAG_64_BITS |
  21753                           SOC_REG_FLAG_WO,
  21754         0,
  21755         1,
  21756         soc_BRDC_DCL_TWO_PIPES_BMPr_fields,
  21757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21758         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  21759         -1,
  21760         -1,
  21761     },
  21762 #endif /* chips */
  21763 
  21764 #if defined(BCM_88950_A0)
  21765     { /* SOC_REG_INT_BRDC_DCL_TYPE_0_DRP_PRI_Pr */
  21766         soc_block_list[104],
  21767         soc_genreg,
  21768         3,
  21769         0,
  21770         0x225,
  21771         SOC_REG_FLAG_64_BITS |
  21772                           SOC_REG_FLAG_ARRAY |
  21773                           SOC_REG_FLAG_WO |
  21774                           SOC_REG_FLAG_REG_ARRAY,
  21775         0,
  21776         4,
  21777         soc_BRDC_DCL_TYPE_0_DRP_PRI_Pr_fields,
  21778         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  21779         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  21780         -1,
  21781         -1,
  21782     },
  21783 #endif /* chips */
  21784 
  21785 #if defined(BCM_88950_A0)
  21786     { /* SOC_REG_INT_BRDC_DCL_TYPE_0_GCI_TH_Pr */
  21787         soc_block_list[104],
  21788         soc_genreg,
  21789         3,
  21790         0,
  21791         0x13c,
  21792         SOC_REG_FLAG_ARRAY |
  21793                           SOC_REG_FLAG_WO |
  21794                           SOC_REG_FLAG_REG_ARRAY,
  21795         0,
  21796         3,
  21797         soc_BRDC_DCL_TYPE_0_GCI_TH_Pr_fields,
  21798         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  21799         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  21800         -1,
  21801         -1,
  21802     },
  21803 #endif /* chips */
  21804 
  21805 #if defined(BCM_88950_A0)
  21806     { /* SOC_REG_INT_BRDC_DCL_TYPE_0_RCI_TH_Pr */
  21807         soc_block_list[104],
  21808         soc_genreg,
  21809         3,
  21810         0,
  21811         0x142,
  21812         SOC_REG_FLAG_ARRAY |
  21813                           SOC_REG_FLAG_WO |
  21814                           SOC_REG_FLAG_REG_ARRAY,
  21815         0,
  21816         3,
  21817         soc_BRDC_DCL_TYPE_0_RCI_TH_Pr_fields,
  21818         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  21819         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  21820         -1,
  21821         -1,
  21822     },
  21823 #endif /* chips */
  21824 
  21825 #if defined(BCM_88950_A0)
  21826     { /* SOC_REG_INT_BRDC_DCL_TYPE_1_DRP_PRI_Pr */
  21827         soc_block_list[104],
  21828         soc_genreg,
  21829         3,
  21830         0,
  21831         0x22b,
  21832         SOC_REG_FLAG_64_BITS |
  21833                           SOC_REG_FLAG_ARRAY |
  21834                           SOC_REG_FLAG_WO |
  21835                           SOC_REG_FLAG_REG_ARRAY,
  21836         0,
  21837         4,
  21838         soc_BRDC_DCL_TYPE_1_DRP_PRI_Pr_fields,
  21839         SOC_RESET_VAL_DEC(0xffffffff, 0x000000ff)
  21840         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  21841         -1,
  21842         -1,
  21843     },
  21844 #endif /* chips */
  21845 
  21846 #if defined(BCM_88950_A0)
  21847     { /* SOC_REG_INT_BRDC_DCL_TYPE_1_GCI_TH_Pr */
  21848         soc_block_list[104],
  21849         soc_genreg,
  21850         3,
  21851         0,
  21852         0x13f,
  21853         SOC_REG_FLAG_ARRAY |
  21854                           SOC_REG_FLAG_WO |
  21855                           SOC_REG_FLAG_REG_ARRAY,
  21856         0,
  21857         3,
  21858         soc_BRDC_DCL_TYPE_1_GCI_TH_Pr_fields,
  21859         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  21860         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  21861         -1,
  21862         -1,
  21863     },
  21864 #endif /* chips */
  21865 
  21866 #if defined(BCM_88950_A0)
  21867     { /* SOC_REG_INT_BRDC_DCL_TYPE_1_RCI_TH_Pr */
  21868         soc_block_list[104],
  21869         soc_genreg,
  21870         3,
  21871         0,
  21872         0x145,
  21873         SOC_REG_FLAG_ARRAY |
  21874                           SOC_REG_FLAG_WO |
  21875                           SOC_REG_FLAG_REG_ARRAY,
  21876         0,
  21877         3,
  21878         soc_BRDC_DCL_TYPE_1_RCI_TH_Pr_fields,
  21879         SOC_RESET_VAL_DEC(0x0c828078, 0x00000000)
  21880         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  21881         -1,
  21882         -1,
  21883     },
  21884 #endif /* chips */
  21885 
  21886 #if defined(BCM_88950_A0)
  21887     { /* SOC_REG_INT_BRDC_DCL_UNPACKED_CELL_P_CNTr */
  21888         soc_block_list[104],
  21889         soc_genreg,
  21890         3,
  21891         0,
  21892         0x15e,
  21893         SOC_REG_FLAG_ARRAY |
  21894                           SOC_REG_FLAG_RO |
  21895                           SOC_REG_FLAG_WO |
  21896                           SOC_REG_FLAG_REG_ARRAY,
  21897         0,
  21898         2,
  21899         soc_BRDC_DCL_UNPACKED_CELL_P_CNTr_fields,
  21900         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21901         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21902         -1,
  21903         -1,
  21904     },
  21905 #endif /* chips */
  21906 
  21907 #if defined(BCM_88790_A0)
  21908     { /* SOC_REG_INT_BRDC_DCML_AUTO_DOC_NAME_1r */
  21909         soc_block_list[112],
  21910         soc_genreg,
  21911         1,
  21912         0,
  21913         0x12c,
  21914         SOC_REG_FLAG_ABOVE_64_BITS,
  21915         0,
  21916         32,
  21917         soc_BRDC_DCML_AUTO_DOC_NAME_1r_fields,
  21918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21919         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  21920         -1,
  21921         -1,
  21922     },
  21923 #endif /* chips */
  21924 
  21925 #if defined(BCM_88790_A0)
  21926     { /* SOC_REG_INT_BRDC_DCML_AUTO_DOC_NAME_34r */
  21927         soc_block_list[112],
  21928         soc_genreg,
  21929         1,
  21930         0,
  21931         0x133,
  21932         0,
  21933         0,
  21934         2,
  21935         soc_BRDC_DCML_AUTO_DOC_NAME_34r_fields,
  21936         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  21937         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  21938         -1,
  21939         -1,
  21940     },
  21941 #endif /* chips */
  21942 
  21943 #if defined(BCM_88790_A0)
  21944     { /* SOC_REG_INT_BRDC_DCML_AUTO_DOC_NAME_37r */
  21945         soc_block_list[112],
  21946         soc_genreg,
  21947         1,
  21948         0,
  21949         0x188,
  21950         SOC_REG_FLAG_64_BITS |
  21951                           SOC_REG_FLAG_RO,
  21952         0,
  21953         8,
  21954         soc_BRDC_DCML_AUTO_DOC_NAME_37r_fields,
  21955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21956         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21957         -1,
  21958         -1,
  21959     },
  21960 #endif /* chips */
  21961 
  21962 #if defined(BCM_88790_A0)
  21963     { /* SOC_REG_INT_BRDC_DCML_AUTO_DOC_NAME_38r */
  21964         soc_block_list[112],
  21965         soc_genreg,
  21966         1,
  21967         0,
  21968         0x18e,
  21969         SOC_REG_FLAG_64_BITS,
  21970         0,
  21971         8,
  21972         soc_BRDC_DCML_AUTO_DOC_NAME_38r_fields,
  21973         SOC_RESET_VAL_DEC(0xd34d34d3, 0x00004d34)
  21974         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  21975         -1,
  21976         -1,
  21977     },
  21978 #endif /* chips */
  21979 
  21980 #if defined(BCM_88790_A0)
  21981     { /* SOC_REG_INT_BRDC_DCML_AUTO_DOC_NAME_47r */
  21982         soc_block_list[112],
  21983         soc_genreg,
  21984         1,
  21985         0,
  21986         0x196,
  21987         SOC_REG_FLAG_RO,
  21988         SOC_REG_FLAG_COUNTER_FEILDS,
  21989         2,
  21990         soc_BRDC_DCML_AUTO_DOC_NAME_47r_fields,
  21991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  21992         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  21993         -1,
  21994         -1,
  21995     },
  21996 #endif /* chips */
  21997 
  21998 #if defined(BCM_88790_A0)
  21999     { /* SOC_REG_INT_BRDC_DCML_AUTO_DOC_NAME_48r */
  22000         soc_block_list[112],
  22001         soc_genreg,
  22002         1,
  22003         0,
  22004         0x199,
  22005         SOC_REG_FLAG_RO,
  22006         SOC_REG_FLAG_COUNTER_FEILDS,
  22007         2,
  22008         soc_BRDC_DCML_AUTO_DOC_NAME_48r_fields,
  22009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22010         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22011         -1,
  22012         -1,
  22013     },
  22014 #endif /* chips */
  22015 
  22016 #if defined(BCM_88790_A0)
  22017     { /* SOC_REG_INT_BRDC_DCML_AUTO_DOC_NAME_49r */
  22018         soc_block_list[112],
  22019         soc_genreg,
  22020         1,
  22021         0,
  22022         0x19a,
  22023         SOC_REG_FLAG_RO,
  22024         0,
  22025         2,
  22026         soc_BRDC_DCML_AUTO_DOC_NAME_49r_fields,
  22027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22028         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  22029         -1,
  22030         -1,
  22031     },
  22032 #endif /* chips */
  22033 
  22034 #if defined(BCM_88790_A0)
  22035     { /* SOC_REG_INT_BRDC_DCML_CCML_CONFIGURATIONSr */
  22036         soc_block_list[112],
  22037         soc_genreg,
  22038         1,
  22039         0,
  22040         0x152,
  22041         0,
  22042         0,
  22043         8,
  22044         soc_BRDC_DCML_CCML_CONFIGURATIONSr_fields,
  22045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22046         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  22047         -1,
  22048         -1,
  22049     },
  22050 #endif /* chips */
  22051 
  22052 #if defined(BCM_88790_A0)
  22053     { /* SOC_REG_INT_BRDC_DCML_CDMA_LP_CELLS_DISCARD_CNTr */
  22054         soc_block_list[112],
  22055         soc_genreg,
  22056         1,
  22057         0,
  22058         0x155,
  22059         SOC_REG_FLAG_RO,
  22060         SOC_REG_FLAG_COUNTER_FEILDS,
  22061         2,
  22062         soc_BRDC_DCML_CDMA_LP_CELLS_DISCARD_CNTr_fields,
  22063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22064         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22065         -1,
  22066         -1,
  22067     },
  22068 #endif /* chips */
  22069 
  22070 #if defined(BCM_88790_A0)
  22071     { /* SOC_REG_INT_BRDC_DCML_CDMB_LP_CELLS_DISCARD_CNTr */
  22072         soc_block_list[112],
  22073         soc_genreg,
  22074         1,
  22075         0,
  22076         0x156,
  22077         SOC_REG_FLAG_RO,
  22078         SOC_REG_FLAG_COUNTER_FEILDS,
  22079         2,
  22080         soc_BRDC_DCML_CDMB_LP_CELLS_DISCARD_CNTr_fields,
  22081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22082         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22083         -1,
  22084         -1,
  22085     },
  22086 #endif /* chips */
  22087 
  22088 #if defined(BCM_88790_A0)
  22089     { /* SOC_REG_INT_BRDC_DCML_CDMC_LP_CELLS_DISCARD_CNTr */
  22090         soc_block_list[112],
  22091         soc_genreg,
  22092         1,
  22093         0,
  22094         0x157,
  22095         SOC_REG_FLAG_RO,
  22096         SOC_REG_FLAG_COUNTER_FEILDS,
  22097         2,
  22098         soc_BRDC_DCML_CDMC_LP_CELLS_DISCARD_CNTr_fields,
  22099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22100         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22101         -1,
  22102         -1,
  22103     },
  22104 #endif /* chips */
  22105 
  22106 #if defined(BCM_88790_A0)
  22107     { /* SOC_REG_INT_BRDC_DCML_CDMD_LP_CELLS_DISCARD_CNTr */
  22108         soc_block_list[112],
  22109         soc_genreg,
  22110         1,
  22111         0,
  22112         0x158,
  22113         SOC_REG_FLAG_RO,
  22114         SOC_REG_FLAG_COUNTER_FEILDS,
  22115         2,
  22116         soc_BRDC_DCML_CDMD_LP_CELLS_DISCARD_CNTr_fields,
  22117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22118         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22119         -1,
  22120         -1,
  22121     },
  22122 #endif /* chips */
  22123 
  22124 #if defined(BCM_88790_A0)
  22125     { /* SOC_REG_INT_BRDC_DCML_CDME_LP_CELLS_DISCARD_CNTr */
  22126         soc_block_list[112],
  22127         soc_genreg,
  22128         1,
  22129         0,
  22130         0x159,
  22131         SOC_REG_FLAG_RO,
  22132         SOC_REG_FLAG_COUNTER_FEILDS,
  22133         2,
  22134         soc_BRDC_DCML_CDME_LP_CELLS_DISCARD_CNTr_fields,
  22135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22137         -1,
  22138         -1,
  22139     },
  22140 #endif /* chips */
  22141 
  22142 #if defined(BCM_88790_A0)
  22143     { /* SOC_REG_INT_BRDC_DCML_CDMF_LP_CELLS_DISCARD_CNTr */
  22144         soc_block_list[112],
  22145         soc_genreg,
  22146         1,
  22147         0,
  22148         0x15a,
  22149         SOC_REG_FLAG_RO,
  22150         SOC_REG_FLAG_COUNTER_FEILDS,
  22151         2,
  22152         soc_BRDC_DCML_CDMF_LP_CELLS_DISCARD_CNTr_fields,
  22153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22154         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22155         -1,
  22156         -1,
  22157     },
  22158 #endif /* chips */
  22159 
  22160 #if defined(BCM_88790_A0)
  22161     { /* SOC_REG_INT_BRDC_DCML_CDMG_LP_CELLS_DISCARD_CNTr */
  22162         soc_block_list[112],
  22163         soc_genreg,
  22164         1,
  22165         0,
  22166         0x15b,
  22167         SOC_REG_FLAG_RO,
  22168         SOC_REG_FLAG_COUNTER_FEILDS,
  22169         2,
  22170         soc_BRDC_DCML_CDMG_LP_CELLS_DISCARD_CNTr_fields,
  22171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22172         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22173         -1,
  22174         -1,
  22175     },
  22176 #endif /* chips */
  22177 
  22178 #if defined(BCM_88790_A0)
  22179     { /* SOC_REG_INT_BRDC_DCML_CDMH_LP_CELLS_DISCARD_CNTr */
  22180         soc_block_list[112],
  22181         soc_genreg,
  22182         1,
  22183         0,
  22184         0x15c,
  22185         SOC_REG_FLAG_RO,
  22186         SOC_REG_FLAG_COUNTER_FEILDS,
  22187         2,
  22188         soc_BRDC_DCML_CDMH_LP_CELLS_DISCARD_CNTr_fields,
  22189         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22190         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22191         -1,
  22192         -1,
  22193     },
  22194 #endif /* chips */
  22195 
  22196 #if defined(BCM_88790_A0)
  22197     { /* SOC_REG_INT_BRDC_DCML_CDM_OVERFLOW_FIFO_NUMBERr */
  22198         soc_block_list[112],
  22199         soc_genreg,
  22200         1,
  22201         0,
  22202         0x153,
  22203         SOC_REG_FLAG_64_BITS |
  22204                           SOC_REG_FLAG_RO,
  22205         0,
  22206         16,
  22207         soc_BRDC_DCML_CDM_OVERFLOW_FIFO_NUMBERr_fields,
  22208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22209         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22210         -1,
  22211         -1,
  22212     },
  22213 #endif /* chips */
  22214 
  22215 #if defined(BCM_88790_A0)
  22216     { /* SOC_REG_INT_BRDC_DCML_CPU_FORCE_MAC_LINK_IREADYr */
  22217         soc_block_list[112],
  22218         soc_genreg,
  22219         1,
  22220         0,
  22221         0x19b,
  22222         0,
  22223         0,
  22224         1,
  22225         soc_BRDC_DCML_CPU_FORCE_MAC_LINK_IREADYr_fields,
  22226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22227         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22228         -1,
  22229         -1,
  22230     },
  22231 #endif /* chips */
  22232 
  22233 #if defined(BCM_88790_A0)
  22234     { /* SOC_REG_INT_BRDC_DCML_CPU_SOURCE_CELL_DATAr */
  22235         soc_block_list[112],
  22236         soc_genreg,
  22237         1,
  22238         0,
  22239         0x190,
  22240         SOC_REG_FLAG_ABOVE_64_BITS,
  22241         0,
  22242         2,
  22243         soc_BRDC_DCML_CPU_SOURCE_CELL_DATAr_fields,
  22244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22245         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22246         -1,
  22247         -1,
  22248     },
  22249 #endif /* chips */
  22250 
  22251 #if defined(BCM_88790_A0)
  22252     { /* SOC_REG_INT_BRDC_DCML_CPU_SOURCE_CELL_TRIGGERr */
  22253         soc_block_list[112],
  22254         soc_genreg,
  22255         1,
  22256         0,
  22257         0x194,
  22258         0,
  22259         0,
  22260         1,
  22261         soc_BRDC_DCML_CPU_SOURCE_CELL_TRIGGERr_fields,
  22262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22263         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22264         -1,
  22265         -1,
  22266     },
  22267 #endif /* chips */
  22268 
  22269 #if defined(BCM_88790_A0)
  22270     { /* SOC_REG_INT_BRDC_DCML_CTP_CREDIT_CELLS_CNTr */
  22271         soc_block_list[112],
  22272         soc_genreg,
  22273         1,
  22274         0,
  22275         0x197,
  22276         SOC_REG_FLAG_RO,
  22277         SOC_REG_FLAG_COUNTER_FEILDS,
  22278         2,
  22279         soc_BRDC_DCML_CTP_CREDIT_CELLS_CNTr_fields,
  22280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22282         -1,
  22283         -1,
  22284     },
  22285 #endif /* chips */
  22286 
  22287 #if defined(BCM_88790_A0)
  22288     { /* SOC_REG_INT_BRDC_DCML_CTP_FS_CELLS_CNTr */
  22289         soc_block_list[112],
  22290         soc_genreg,
  22291         1,
  22292         0,
  22293         0x198,
  22294         SOC_REG_FLAG_RO,
  22295         SOC_REG_FLAG_COUNTER_FEILDS,
  22296         2,
  22297         soc_BRDC_DCML_CTP_FS_CELLS_CNTr_fields,
  22298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22300         -1,
  22301         -1,
  22302     },
  22303 #endif /* chips */
  22304 
  22305 #if defined(BCM_88790_A0)
  22306     { /* SOC_REG_INT_BRDC_DCML_CTP_INTERNAL_REACHABILITY_CELLS_CNTr */
  22307         soc_block_list[112],
  22308         soc_genreg,
  22309         1,
  22310         0,
  22311         0x195,
  22312         SOC_REG_FLAG_RO,
  22313         SOC_REG_FLAG_COUNTER_FEILDS,
  22314         2,
  22315         soc_BRDC_DCML_CTP_INTERNAL_REACHABILITY_CELLS_CNTr_fields,
  22316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22318         -1,
  22319         -1,
  22320     },
  22321 #endif /* chips */
  22322 
  22323 #if defined(BCM_88790_A0)
  22324     { /* SOC_REG_INT_BRDC_DCML_DCML_ENABLERSr */
  22325         soc_block_list[112],
  22326         soc_genreg,
  22327         1,
  22328         0,
  22329         0x106,
  22330         0,
  22331         0,
  22332         1,
  22333         soc_BRDC_DCML_DCML_ENABLERSr_fields,
  22334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22335         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  22336         -1,
  22337         -1,
  22338     },
  22339 #endif /* chips */
  22340 
  22341 #if defined(BCM_88790_A0)
  22342     { /* SOC_REG_INT_BRDC_DCML_DCML_SEPARATION_REGISTERr */
  22343         soc_block_list[112],
  22344         soc_genreg,
  22345         1,
  22346         0,
  22347         0x107,
  22348         0,
  22349         0,
  22350         3,
  22351         soc_BRDC_DCML_DCML_SEPARATION_REGISTERr_fields,
  22352         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  22353         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22354         -1,
  22355         -1,
  22356     },
  22357 #endif /* chips */
  22358 
  22359 #if defined(BCM_88790_A0)
  22360     { /* SOC_REG_INT_BRDC_DCML_DFL_ECC_ERR_CFGr */
  22361         soc_block_list[112],
  22362         soc_genreg,
  22363         1,
  22364         0,
  22365         0x19f,
  22366         0,
  22367         0,
  22368         3,
  22369         soc_BRDC_DCML_DFL_ECC_ERR_CFGr_fields,
  22370         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  22371         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22372         -1,
  22373         -1,
  22374     },
  22375 #endif /* chips */
  22376 
  22377 #if defined(BCM_88790_A0)
  22378     { /* SOC_REG_INT_BRDC_DCML_ECC_1B_ERR_CNTr */
  22379         soc_block_list[112],
  22380         soc_genreg,
  22381         1,
  22382         0,
  22383         0x94,
  22384         SOC_REG_FLAG_64_BITS |
  22385                           SOC_REG_FLAG_RO,
  22386         SOC_REG_FLAG_COUNTER_FEILDS,
  22387         4,
  22388         soc_BRDC_DCML_ECC_1B_ERR_CNTr_fields,
  22389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22390         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22391         -1,
  22392         -1,
  22393     },
  22394 #endif /* chips */
  22395 
  22396 #if defined(BCM_88790_A0)
  22397     { /* SOC_REG_INT_BRDC_DCML_ECC_2B_ERR_CNTr */
  22398         soc_block_list[112],
  22399         soc_genreg,
  22400         1,
  22401         0,
  22402         0x96,
  22403         SOC_REG_FLAG_64_BITS |
  22404                           SOC_REG_FLAG_RO,
  22405         SOC_REG_FLAG_COUNTER_FEILDS,
  22406         4,
  22407         soc_BRDC_DCML_ECC_2B_ERR_CNTr_fields,
  22408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22409         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  22410         -1,
  22411         -1,
  22412     },
  22413 #endif /* chips */
  22414 
  22415 #if defined(BCM_88790_A0)
  22416     { /* SOC_REG_INT_BRDC_DCML_ECC_ERR_1B_INITIATEr */
  22417         soc_block_list[112],
  22418         soc_genreg,
  22419         1,
  22420         0,
  22421         0xa4,
  22422         SOC_REG_FLAG_ABOVE_64_BITS,
  22423         0,
  22424         13,
  22425         soc_BRDC_DCML_ECC_ERR_1B_INITIATEr_fields,
  22426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22427         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22428         -1,
  22429         -1,
  22430     },
  22431 #endif /* chips */
  22432 
  22433 #if defined(BCM_88790_A0)
  22434     { /* SOC_REG_INT_BRDC_DCML_ECC_ERR_1B_MONITOR_MEM_MASKr */
  22435         soc_block_list[112],
  22436         soc_genreg,
  22437         1,
  22438         0,
  22439         0x9a,
  22440         SOC_REG_FLAG_ABOVE_64_BITS,
  22441         0,
  22442         13,
  22443         soc_BRDC_DCML_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  22444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22445         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22446         -1,
  22447         -1,
  22448     },
  22449 #endif /* chips */
  22450 
  22451 #if defined(BCM_88790_A0)
  22452     { /* SOC_REG_INT_BRDC_DCML_ECC_ERR_2B_INITIATEr */
  22453         soc_block_list[112],
  22454         soc_genreg,
  22455         1,
  22456         0,
  22457         0xa6,
  22458         SOC_REG_FLAG_ABOVE_64_BITS,
  22459         0,
  22460         13,
  22461         soc_BRDC_DCML_ECC_ERR_2B_INITIATEr_fields,
  22462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22464         -1,
  22465         -1,
  22466     },
  22467 #endif /* chips */
  22468 
  22469 #if defined(BCM_88790_A0)
  22470     { /* SOC_REG_INT_BRDC_DCML_ECC_ERR_2B_MONITOR_MEM_MASKr */
  22471         soc_block_list[112],
  22472         soc_genreg,
  22473         1,
  22474         0,
  22475         0x9c,
  22476         SOC_REG_FLAG_ABOVE_64_BITS,
  22477         0,
  22478         13,
  22479         soc_BRDC_DCML_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  22480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22481         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22482         -1,
  22483         -1,
  22484     },
  22485 #endif /* chips */
  22486 
  22487 #if defined(BCM_88790_A0)
  22488     { /* SOC_REG_INT_BRDC_DCML_ECC_INTERRUPT_REGISTERr */
  22489         soc_block_list[112],
  22490         soc_genreg,
  22491         1,
  22492         0,
  22493         0x7,
  22494         SOC_REG_FLAG_INTERRUPT |
  22495                           SOC_REG_FLAG_SIGNAL,
  22496         0,
  22497         3,
  22498         soc_BRDC_DCML_ECC_INTERRUPT_REGISTERr_fields,
  22499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22500         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22501         -1,
  22502         -1,
  22503     },
  22504 #endif /* chips */
  22505 
  22506 #if defined(BCM_88790_A0)
  22507     { /* SOC_REG_INT_BRDC_DCML_ECC_INTERRUPT_REGISTER_MASKr */
  22508         soc_block_list[112],
  22509         soc_genreg,
  22510         1,
  22511         0,
  22512         0x17,
  22513         0,
  22514         0,
  22515         3,
  22516         soc_BRDC_DCML_ECC_INTERRUPT_REGISTER_MASKr_fields,
  22517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22518         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22519         -1,
  22520         -1,
  22521     },
  22522 #endif /* chips */
  22523 
  22524 #if defined(BCM_88790_A0)
  22525     { /* SOC_REG_INT_BRDC_DCML_ECC_INTERRUPT_REGISTER_TESTr */
  22526         soc_block_list[112],
  22527         soc_genreg,
  22528         1,
  22529         0,
  22530         0x1f,
  22531         0,
  22532         0,
  22533         1,
  22534         soc_BRDC_DCML_ECC_INTERRUPT_REGISTER_TESTr_fields,
  22535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22536         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22537         -1,
  22538         -1,
  22539     },
  22540 #endif /* chips */
  22541 
  22542 #if defined(BCM_88790_A0)
  22543     { /* SOC_REG_INT_BRDC_DCML_ENABLE_DYNAMIC_MEMORY_ACCESSr */
  22544         soc_block_list[112],
  22545         soc_genreg,
  22546         1,
  22547         0,
  22548         0x84,
  22549         0,
  22550         0,
  22551         1,
  22552         soc_BRDC_DCML_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  22553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22554         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22555         -1,
  22556         -1,
  22557     },
  22558 #endif /* chips */
  22559 
  22560 #if defined(BCM_88790_A0)
  22561     { /* SOC_REG_INT_BRDC_DCML_ERROR_INITIATION_DATAr */
  22562         soc_block_list[112],
  22563         soc_genreg,
  22564         1,
  22565         0,
  22566         0xa3,
  22567         0,
  22568         0,
  22569         1,
  22570         soc_BRDC_DCML_ERROR_INITIATION_DATAr_fields,
  22571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22572         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22573         -1,
  22574         -1,
  22575     },
  22576 #endif /* chips */
  22577 
  22578 #if defined(BCM_88790_A0)
  22579     { /* SOC_REG_INT_BRDC_DCML_FAP_GLOBAL_GENERAL_CFG_1r */
  22580         soc_block_list[112],
  22581         soc_genreg,
  22582         1,
  22583         0,
  22584         0xc3,
  22585         0,
  22586         0,
  22587         2,
  22588         soc_BRDC_DCML_FAP_GLOBAL_GENERAL_CFG_1r_fields,
  22589         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  22590         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22591         -1,
  22592         -1,
  22593     },
  22594 #endif /* chips */
  22595 
  22596 #if defined(BCM_88790_A0)
  22597     { /* SOC_REG_INT_BRDC_DCML_FBC_BANK_STATr */
  22598         soc_block_list[112],
  22599         soc_genreg,
  22600         10,
  22601         0,
  22602         0x134,
  22603         SOC_REG_FLAG_ABOVE_64_BITS |
  22604                           SOC_REG_FLAG_ARRAY |
  22605                           SOC_REG_FLAG_RO |
  22606                           SOC_REG_FLAG_REG_ARRAY,
  22607         0,
  22608         6,
  22609         soc_BRDC_DCML_FBC_BANK_STATr_fields,
  22610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22611         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22612         -1,
  22613         -1,
  22614     },
  22615 #endif /* chips */
  22616 
  22617 #if defined(BCM_88790_A0)
  22618     { /* SOC_REG_INT_BRDC_DCML_FBC_BANK_STAT_DIFFr */
  22619         soc_block_list[112],
  22620         soc_genreg,
  22621         1,
  22622         0,
  22623         0x19c,
  22624         SOC_REG_FLAG_ABOVE_64_BITS |
  22625                           SOC_REG_FLAG_RO,
  22626         0,
  22627         8,
  22628         soc_BRDC_DCML_FBC_BANK_STAT_DIFFr_fields,
  22629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22631         -1,
  22632         -1,
  22633     },
  22634 #endif /* chips */
  22635 
  22636 #if defined(BCM_88790_A0)
  22637     { /* SOC_REG_INT_BRDC_DCML_FE_GLOBAL_GENERAL_CFG_1r */
  22638         soc_block_list[112],
  22639         soc_genreg,
  22640         1,
  22641         0,
  22642         0xf4,
  22643         0,
  22644         0,
  22645         4,
  22646         soc_BRDC_DCML_FE_GLOBAL_GENERAL_CFG_1r_fields,
  22647         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  22648         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  22649         -1,
  22650         -1,
  22651     },
  22652 #endif /* chips */
  22653 
  22654 #if defined(BCM_88790_A0)
  22655     { /* SOC_REG_INT_BRDC_DCML_FE_GLOBAL_GENERAL_CFG_2r */
  22656         soc_block_list[112],
  22657         soc_genreg,
  22658         1,
  22659         0,
  22660         0xf3,
  22661         0,
  22662         0,
  22663         1,
  22664         soc_BRDC_DCML_FE_GLOBAL_GENERAL_CFG_2r_fields,
  22665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22666         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  22667         -1,
  22668         -1,
  22669     },
  22670 #endif /* chips */
  22671 
  22672 #if defined(BCM_88790_A0)
  22673     { /* SOC_REG_INT_BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTERr */
  22674         soc_block_list[112],
  22675         soc_genreg,
  22676         1,
  22677         0,
  22678         0x103,
  22679         SOC_REG_FLAG_INTERRUPT |
  22680                           SOC_REG_FLAG_SIGNAL,
  22681         0,
  22682         1,
  22683         soc_BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTERr_fields,
  22684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22685         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  22686         -1,
  22687         -1,
  22688     },
  22689 #endif /* chips */
  22690 
  22691 #if defined(BCM_88790_A0)
  22692     { /* SOC_REG_INT_BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_MASKr */
  22693         soc_block_list[112],
  22694         soc_genreg,
  22695         1,
  22696         0,
  22697         0x104,
  22698         0,
  22699         0,
  22700         1,
  22701         soc_BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_MASKr_fields,
  22702         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22703         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  22704         -1,
  22705         -1,
  22706     },
  22707 #endif /* chips */
  22708 
  22709 #if defined(BCM_88790_A0)
  22710     { /* SOC_REG_INT_BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_TESTr */
  22711         soc_block_list[112],
  22712         soc_genreg,
  22713         1,
  22714         0,
  22715         0x105,
  22716         0,
  22717         0,
  22718         1,
  22719         soc_BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_TESTr_fields,
  22720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22721         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  22722         -1,
  22723         -1,
  22724     },
  22725 #endif /* chips */
  22726 
  22727 #if defined(BCM_88790_A0)
  22728     { /* SOC_REG_INT_BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTERr */
  22729         soc_block_list[112],
  22730         soc_genreg,
  22731         1,
  22732         0,
  22733         0x100,
  22734         SOC_REG_FLAG_INTERRUPT |
  22735                           SOC_REG_FLAG_SIGNAL,
  22736         0,
  22737         1,
  22738         soc_BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTERr_fields,
  22739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22740         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  22741         -1,
  22742         -1,
  22743     },
  22744 #endif /* chips */
  22745 
  22746 #if defined(BCM_88790_A0)
  22747     { /* SOC_REG_INT_BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_MASKr */
  22748         soc_block_list[112],
  22749         soc_genreg,
  22750         1,
  22751         0,
  22752         0x101,
  22753         0,
  22754         0,
  22755         1,
  22756         soc_BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_MASKr_fields,
  22757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22758         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  22759         -1,
  22760         -1,
  22761     },
  22762 #endif /* chips */
  22763 
  22764 #if defined(BCM_88790_A0)
  22765     { /* SOC_REG_INT_BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_TESTr */
  22766         soc_block_list[112],
  22767         soc_genreg,
  22768         1,
  22769         0,
  22770         0x102,
  22771         0,
  22772         0,
  22773         1,
  22774         soc_BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_TESTr_fields,
  22775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22776         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  22777         -1,
  22778         -1,
  22779     },
  22780 #endif /* chips */
  22781 
  22782 #if defined(BCM_88790_A0)
  22783     { /* SOC_REG_INT_BRDC_DCML_GLOBAL_MEM_OPTIONSr */
  22784         soc_block_list[112],
  22785         soc_genreg,
  22786         1,
  22787         0,
  22788         0xc2,
  22789         0,
  22790         0,
  22791         6,
  22792         soc_BRDC_DCML_GLOBAL_MEM_OPTIONSr_fields,
  22793         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  22794         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  22795         -1,
  22796         -1,
  22797     },
  22798 #endif /* chips */
  22799 
  22800 #if defined(BCM_88790_A0)
  22801     { /* SOC_REG_INT_BRDC_DCML_GTIMER_CONFIGURATIONr */
  22802         soc_block_list[112],
  22803         soc_genreg,
  22804         1,
  22805         0,
  22806         0x89,
  22807         0,
  22808         0,
  22809         3,
  22810         soc_BRDC_DCML_GTIMER_CONFIGURATIONr_fields,
  22811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22812         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  22813         -1,
  22814         -1,
  22815     },
  22816 #endif /* chips */
  22817 
  22818 #if defined(BCM_88790_A0)
  22819     { /* SOC_REG_INT_BRDC_DCML_GTIMER_CYCLEr */
  22820         soc_block_list[112],
  22821         soc_genreg,
  22822         1,
  22823         0,
  22824         0x88,
  22825         0,
  22826         0,
  22827         1,
  22828         soc_BRDC_DCML_GTIMER_CYCLEr_fields,
  22829         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  22830         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22831         -1,
  22832         -1,
  22833     },
  22834 #endif /* chips */
  22835 
  22836 #if defined(BCM_88790_A0)
  22837     { /* SOC_REG_INT_BRDC_DCML_INDIRECT_COMMANDr */
  22838         soc_block_list[112],
  22839         soc_genreg,
  22840         1,
  22841         0,
  22842         0x80,
  22843         0,
  22844         0,
  22845         5,
  22846         soc_BRDC_DCML_INDIRECT_COMMANDr_fields,
  22847         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  22848         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22849         -1,
  22850         -1,
  22851     },
  22852 #endif /* chips */
  22853 
  22854 #if defined(BCM_88790_A0)
  22855     { /* SOC_REG_INT_BRDC_DCML_INDIRECT_COMMAND_ADDRESSr */
  22856         soc_block_list[112],
  22857         soc_genreg,
  22858         1,
  22859         0,
  22860         0x81,
  22861         0,
  22862         0,
  22863         2,
  22864         soc_BRDC_DCML_INDIRECT_COMMAND_ADDRESSr_fields,
  22865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22866         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22867         -1,
  22868         -1,
  22869     },
  22870 #endif /* chips */
  22871 
  22872 #if defined(BCM_88790_A0)
  22873     { /* SOC_REG_INT_BRDC_DCML_INDIRECT_COMMAND_DATA_INCREMENTr */
  22874         soc_block_list[112],
  22875         soc_genreg,
  22876         1,
  22877         0,
  22878         0x82,
  22879         SOC_REG_FLAG_64_BITS,
  22880         0,
  22881         1,
  22882         soc_BRDC_DCML_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  22883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22884         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  22885         -1,
  22886         -1,
  22887     },
  22888 #endif /* chips */
  22889 
  22890 #if defined(BCM_88790_A0)
  22891     { /* SOC_REG_INT_BRDC_DCML_INDIRECT_COMMAND_RD_DATAr */
  22892         soc_block_list[112],
  22893         soc_genreg,
  22894         1,
  22895         0,
  22896         0x60,
  22897         SOC_REG_FLAG_ABOVE_64_BITS |
  22898                           SOC_REG_FLAG_RO |
  22899                           SOC_REG_FLAG_SIGNAL,
  22900         0,
  22901         1,
  22902         soc_BRDC_DCML_INDIRECT_COMMAND_RD_DATAr_fields,
  22903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22904         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  22905         -1,
  22906         -1,
  22907     },
  22908 #endif /* chips */
  22909 
  22910 #if defined(BCM_88790_A0)
  22911     { /* SOC_REG_INT_BRDC_DCML_INDIRECT_COMMAND_WIDE_MEMr */
  22912         soc_block_list[112],
  22913         soc_genreg,
  22914         1,
  22915         0,
  22916         0x41,
  22917         0,
  22918         0,
  22919         1,
  22920         soc_BRDC_DCML_INDIRECT_COMMAND_WIDE_MEMr_fields,
  22921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22922         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  22923         -1,
  22924         -1,
  22925     },
  22926 #endif /* chips */
  22927 
  22928 #if defined(BCM_88790_A0)
  22929     { /* SOC_REG_INT_BRDC_DCML_INDIRECT_COMMAND_WR_DATAr */
  22930         soc_block_list[112],
  22931         soc_genreg,
  22932         1,
  22933         0,
  22934         0x20,
  22935         0,
  22936         0,
  22937         1,
  22938         soc_BRDC_DCML_INDIRECT_COMMAND_WR_DATAr_fields,
  22939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  22941         -1,
  22942         -1,
  22943     },
  22944 #endif /* chips */
  22945 
  22946 #if defined(BCM_88790_A0)
  22947     { /* SOC_REG_INT_BRDC_DCML_INDIRECT_FORCE_BUBBLEr */
  22948         soc_block_list[112],
  22949         soc_genreg,
  22950         1,
  22951         0,
  22952         0x83,
  22953         0,
  22954         0,
  22955         4,
  22956         soc_BRDC_DCML_INDIRECT_FORCE_BUBBLEr_fields,
  22957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22958         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  22959         -1,
  22960         -1,
  22961     },
  22962 #endif /* chips */
  22963 
  22964 #if defined(BCM_88790_A0)
  22965     { /* SOC_REG_INT_BRDC_DCML_INTERRUPT_MASK_REGISTERr */
  22966         soc_block_list[112],
  22967         soc_genreg,
  22968         1,
  22969         0,
  22970         0x10,
  22971         0,
  22972         0,
  22973         12,
  22974         soc_BRDC_DCML_INTERRUPT_MASK_REGISTERr_fields,
  22975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22976         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22977         -1,
  22978         -1,
  22979     },
  22980 #endif /* chips */
  22981 
  22982 #if defined(BCM_88790_A0)
  22983     { /* SOC_REG_INT_BRDC_DCML_INTERRUPT_REGISTERr */
  22984         soc_block_list[112],
  22985         soc_genreg,
  22986         1,
  22987         0,
  22988         0,
  22989         SOC_REG_FLAG_INTERRUPT |
  22990                           SOC_REG_FLAG_SIGNAL,
  22991         0,
  22992         12,
  22993         soc_BRDC_DCML_INTERRUPT_REGISTERr_fields,
  22994         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  22995         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  22996         -1,
  22997         -1,
  22998     },
  22999 #endif /* chips */
  23000 
  23001 #if defined(BCM_88790_A0)
  23002     { /* SOC_REG_INT_BRDC_DCML_INTERRUPT_REGISTER_TESTr */
  23003         soc_block_list[112],
  23004         soc_genreg,
  23005         1,
  23006         0,
  23007         0x18,
  23008         0,
  23009         0,
  23010         1,
  23011         soc_BRDC_DCML_INTERRUPT_REGISTER_TESTr_fields,
  23012         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23013         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  23014         -1,
  23015         -1,
  23016     },
  23017 #endif /* chips */
  23018 
  23019 #if defined(BCM_88790_A0)
  23020     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_LP_WATER_MARKr */
  23021         soc_block_list[112],
  23022         soc_genreg,
  23023         1,
  23024         0,
  23025         0x185,
  23026         SOC_REG_FLAG_ABOVE_64_BITS |
  23027                           SOC_REG_FLAG_RO,
  23028         0,
  23029         16,
  23030         soc_BRDC_DCML_MID_FIFOS_LP_WATER_MARKr_fields,
  23031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23032         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23033         -1,
  23034         -1,
  23035     },
  23036 #endif /* chips */
  23037 
  23038 #if defined(BCM_88790_A0)
  23039     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMAr */
  23040         soc_block_list[112],
  23041         soc_genreg,
  23042         1,
  23043         0,
  23044         0x15d,
  23045         SOC_REG_FLAG_ABOVE_64_BITS |
  23046                           SOC_REG_FLAG_RO,
  23047         0,
  23048         25,
  23049         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMAr_fields,
  23050         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23051         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23052         -1,
  23053         -1,
  23054     },
  23055 #endif /* chips */
  23056 
  23057 #if defined(BCM_88790_A0)
  23058     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMADr */
  23059         soc_block_list[112],
  23060         soc_genreg,
  23061         1,
  23062         0,
  23063         0x16c,
  23064         SOC_REG_FLAG_ABOVE_64_BITS |
  23065                           SOC_REG_FLAG_RO,
  23066         0,
  23067         25,
  23068         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMADr_fields,
  23069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23070         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23071         -1,
  23072         -1,
  23073     },
  23074 #endif /* chips */
  23075 
  23076 #if defined(BCM_88790_A0)
  23077     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMAHr */
  23078         soc_block_list[112],
  23079         soc_genreg,
  23080         1,
  23081         0,
  23082         0x180,
  23083         SOC_REG_FLAG_ABOVE_64_BITS |
  23084                           SOC_REG_FLAG_RO,
  23085         0,
  23086         25,
  23087         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMAHr_fields,
  23088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23089         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23090         -1,
  23091         -1,
  23092     },
  23093 #endif /* chips */
  23094 
  23095 #if defined(BCM_88790_A0)
  23096     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMBr */
  23097         soc_block_list[112],
  23098         soc_genreg,
  23099         1,
  23100         0,
  23101         0x162,
  23102         SOC_REG_FLAG_ABOVE_64_BITS |
  23103                           SOC_REG_FLAG_RO,
  23104         0,
  23105         25,
  23106         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMBr_fields,
  23107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23109         -1,
  23110         -1,
  23111     },
  23112 #endif /* chips */
  23113 
  23114 #if defined(BCM_88790_A0)
  23115     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMCr */
  23116         soc_block_list[112],
  23117         soc_genreg,
  23118         1,
  23119         0,
  23120         0x167,
  23121         SOC_REG_FLAG_ABOVE_64_BITS |
  23122                           SOC_REG_FLAG_RO,
  23123         0,
  23124         25,
  23125         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMCr_fields,
  23126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23127         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23128         -1,
  23129         -1,
  23130     },
  23131 #endif /* chips */
  23132 
  23133 #if defined(BCM_88790_A0)
  23134     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMEr */
  23135         soc_block_list[112],
  23136         soc_genreg,
  23137         1,
  23138         0,
  23139         0x171,
  23140         SOC_REG_FLAG_ABOVE_64_BITS |
  23141                           SOC_REG_FLAG_RO,
  23142         0,
  23143         25,
  23144         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMEr_fields,
  23145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23146         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23147         -1,
  23148         -1,
  23149     },
  23150 #endif /* chips */
  23151 
  23152 #if defined(BCM_88790_A0)
  23153     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMFr */
  23154         soc_block_list[112],
  23155         soc_genreg,
  23156         1,
  23157         0,
  23158         0x176,
  23159         SOC_REG_FLAG_ABOVE_64_BITS |
  23160                           SOC_REG_FLAG_RO,
  23161         0,
  23162         25,
  23163         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMFr_fields,
  23164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23165         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23166         -1,
  23167         -1,
  23168     },
  23169 #endif /* chips */
  23170 
  23171 #if defined(BCM_88790_A0)
  23172     { /* SOC_REG_INT_BRDC_DCML_MID_FIFOS_SATTUS_CDMGr */
  23173         soc_block_list[112],
  23174         soc_genreg,
  23175         1,
  23176         0,
  23177         0x17b,
  23178         SOC_REG_FLAG_ABOVE_64_BITS |
  23179                           SOC_REG_FLAG_RO,
  23180         0,
  23181         25,
  23182         soc_BRDC_DCML_MID_FIFOS_SATTUS_CDMGr_fields,
  23183         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23184         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23185         -1,
  23186         -1,
  23187     },
  23188 #endif /* chips */
  23189 
  23190 #if defined(BCM_88790_A0)
  23191     { /* SOC_REG_INT_BRDC_DCML_PCMI_0r */
  23192         soc_block_list[112],
  23193         soc_genreg,
  23194         1,
  23195         0,
  23196         0xb0,
  23197         0,
  23198         0,
  23199         1,
  23200         soc_BRDC_DCML_PCMI_0r_fields,
  23201         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  23202         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23203         -1,
  23204         -1,
  23205     },
  23206 #endif /* chips */
  23207 
  23208 #if defined(BCM_88790_A0)
  23209     { /* SOC_REG_INT_BRDC_DCML_PCMI_1r */
  23210         soc_block_list[112],
  23211         soc_genreg,
  23212         1,
  23213         0,
  23214         0xb3,
  23215         0,
  23216         0,
  23217         1,
  23218         soc_BRDC_DCML_PCMI_1r_fields,
  23219         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  23220         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23221         -1,
  23222         -1,
  23223     },
  23224 #endif /* chips */
  23225 
  23226 #if defined(BCM_88790_A0)
  23227     { /* SOC_REG_INT_BRDC_DCML_PCMI_2r */
  23228         soc_block_list[112],
  23229         soc_genreg,
  23230         1,
  23231         0,
  23232         0xb6,
  23233         0,
  23234         0,
  23235         1,
  23236         soc_BRDC_DCML_PCMI_2r_fields,
  23237         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  23238         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23239         -1,
  23240         -1,
  23241     },
  23242 #endif /* chips */
  23243 
  23244 #if defined(BCM_88790_A0)
  23245     { /* SOC_REG_INT_BRDC_DCML_PCMI_3r */
  23246         soc_block_list[112],
  23247         soc_genreg,
  23248         1,
  23249         0,
  23250         0xb9,
  23251         0,
  23252         0,
  23253         1,
  23254         soc_BRDC_DCML_PCMI_3r_fields,
  23255         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  23256         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23257         -1,
  23258         -1,
  23259     },
  23260 #endif /* chips */
  23261 
  23262 #if defined(BCM_88790_A0)
  23263     { /* SOC_REG_INT_BRDC_DCML_PCMI_0_Sr */
  23264         soc_block_list[112],
  23265         soc_genreg,
  23266         1,
  23267         0,
  23268         0xb1,
  23269         SOC_REG_FLAG_RO,
  23270         0,
  23271         3,
  23272         soc_BRDC_DCML_PCMI_0_Sr_fields,
  23273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23274         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23275         -1,
  23276         -1,
  23277     },
  23278 #endif /* chips */
  23279 
  23280 #if defined(BCM_88790_A0)
  23281     { /* SOC_REG_INT_BRDC_DCML_PCMI_0_Tr */
  23282         soc_block_list[112],
  23283         soc_genreg,
  23284         1,
  23285         0,
  23286         0xb2,
  23287         0,
  23288         0,
  23289         2,
  23290         soc_BRDC_DCML_PCMI_0_Tr_fields,
  23291         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23292         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  23293         -1,
  23294         -1,
  23295     },
  23296 #endif /* chips */
  23297 
  23298 #if defined(BCM_88790_A0)
  23299     { /* SOC_REG_INT_BRDC_DCML_PCMI_1_Sr */
  23300         soc_block_list[112],
  23301         soc_genreg,
  23302         1,
  23303         0,
  23304         0xb4,
  23305         SOC_REG_FLAG_RO,
  23306         0,
  23307         3,
  23308         soc_BRDC_DCML_PCMI_1_Sr_fields,
  23309         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23310         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23311         -1,
  23312         -1,
  23313     },
  23314 #endif /* chips */
  23315 
  23316 #if defined(BCM_88790_A0)
  23317     { /* SOC_REG_INT_BRDC_DCML_PCMI_1_Tr */
  23318         soc_block_list[112],
  23319         soc_genreg,
  23320         1,
  23321         0,
  23322         0xb5,
  23323         0,
  23324         0,
  23325         2,
  23326         soc_BRDC_DCML_PCMI_1_Tr_fields,
  23327         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23328         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  23329         -1,
  23330         -1,
  23331     },
  23332 #endif /* chips */
  23333 
  23334 #if defined(BCM_88790_A0)
  23335     { /* SOC_REG_INT_BRDC_DCML_PCMI_2_Sr */
  23336         soc_block_list[112],
  23337         soc_genreg,
  23338         1,
  23339         0,
  23340         0xb7,
  23341         SOC_REG_FLAG_RO,
  23342         0,
  23343         3,
  23344         soc_BRDC_DCML_PCMI_2_Sr_fields,
  23345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23346         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23347         -1,
  23348         -1,
  23349     },
  23350 #endif /* chips */
  23351 
  23352 #if defined(BCM_88790_A0)
  23353     { /* SOC_REG_INT_BRDC_DCML_PCMI_2_Tr */
  23354         soc_block_list[112],
  23355         soc_genreg,
  23356         1,
  23357         0,
  23358         0xb8,
  23359         0,
  23360         0,
  23361         2,
  23362         soc_BRDC_DCML_PCMI_2_Tr_fields,
  23363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23364         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  23365         -1,
  23366         -1,
  23367     },
  23368 #endif /* chips */
  23369 
  23370 #if defined(BCM_88790_A0)
  23371     { /* SOC_REG_INT_BRDC_DCML_PCMI_3_Sr */
  23372         soc_block_list[112],
  23373         soc_genreg,
  23374         1,
  23375         0,
  23376         0xba,
  23377         SOC_REG_FLAG_RO,
  23378         0,
  23379         3,
  23380         soc_BRDC_DCML_PCMI_3_Sr_fields,
  23381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23383         -1,
  23384         -1,
  23385     },
  23386 #endif /* chips */
  23387 
  23388 #if defined(BCM_88790_A0)
  23389     { /* SOC_REG_INT_BRDC_DCML_PCMI_3_Tr */
  23390         soc_block_list[112],
  23391         soc_genreg,
  23392         1,
  23393         0,
  23394         0xbb,
  23395         0,
  23396         0,
  23397         2,
  23398         soc_BRDC_DCML_PCMI_3_Tr_fields,
  23399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23400         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  23401         -1,
  23402         -1,
  23403     },
  23404 #endif /* chips */
  23405 
  23406 #if defined(BCM_88790_A0)
  23407     { /* SOC_REG_INT_BRDC_DCML_PIPES_MAPPING_ENr */
  23408         soc_block_list[112],
  23409         soc_genreg,
  23410         1,
  23411         0,
  23412         0x108,
  23413         0,
  23414         0,
  23415         1,
  23416         soc_BRDC_DCML_PIPES_MAPPING_ENr_fields,
  23417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23418         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  23419         -1,
  23420         -1,
  23421     },
  23422 #endif /* chips */
  23423 
  23424 #if defined(BCM_88790_A0)
  23425     { /* SOC_REG_INT_BRDC_DCML_PROGRAMMABLE_MID_FIFOS_WATER_MARKr */
  23426         soc_block_list[112],
  23427         soc_genreg,
  23428         1,
  23429         0,
  23430         0x18c,
  23431         SOC_REG_FLAG_64_BITS |
  23432                           SOC_REG_FLAG_RO,
  23433         0,
  23434         8,
  23435         soc_BRDC_DCML_PROGRAMMABLE_MID_FIFOS_WATER_MARKr_fields,
  23436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23437         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  23438         -1,
  23439         -1,
  23440     },
  23441 #endif /* chips */
  23442 
  23443 #if defined(BCM_88790_A0)
  23444     { /* SOC_REG_INT_BRDC_DCML_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARKr */
  23445         soc_block_list[112],
  23446         soc_genreg,
  23447         1,
  23448         0,
  23449         0x18a,
  23450         SOC_REG_FLAG_64_BITS,
  23451         0,
  23452         8,
  23453         soc_BRDC_DCML_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARKr_fields,
  23454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23455         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  23456         -1,
  23457         -1,
  23458     },
  23459 #endif /* chips */
  23460 
  23461 #if defined(BCM_88790_A0)
  23462     { /* SOC_REG_INT_BRDC_DCML_REMOTE_PRI_PIPE_IDXr */
  23463         soc_block_list[112],
  23464         soc_genreg,
  23465         1,
  23466         0,
  23467         0x109,
  23468         SOC_REG_FLAG_64_BITS,
  23469         0,
  23470         1,
  23471         soc_BRDC_DCML_REMOTE_PRI_PIPE_IDXr_fields,
  23472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23473         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  23474         -1,
  23475         -1,
  23476     },
  23477 #endif /* chips */
  23478 
  23479 #if defined(BCM_88790_A0)
  23480     { /* SOC_REG_INT_BRDC_DCML_REMOTE_SEC_PIPE_IDXr */
  23481         soc_block_list[112],
  23482         soc_genreg,
  23483         1,
  23484         0,
  23485         0x10b,
  23486         SOC_REG_FLAG_64_BITS,
  23487         0,
  23488         1,
  23489         soc_BRDC_DCML_REMOTE_SEC_PIPE_IDXr_fields,
  23490         SOC_RESET_VAL_DEC(0x55555555, 0x00005555)
  23491         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  23492         -1,
  23493         -1,
  23494     },
  23495 #endif /* chips */
  23496 
  23497 #if defined(BCM_88790_A0)
  23498     { /* SOC_REG_INT_BRDC_DCML_RESERVED_MIRROR_ADDRr */
  23499         soc_block_list[112],
  23500         soc_genreg,
  23501         1,
  23502         0,
  23503         0x85,
  23504         0,
  23505         0,
  23506         2,
  23507         soc_BRDC_DCML_RESERVED_MIRROR_ADDRr_fields,
  23508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23509         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  23510         -1,
  23511         -1,
  23512     },
  23513 #endif /* chips */
  23514 
  23515 #if defined(BCM_88790_A0)
  23516     { /* SOC_REG_INT_BRDC_DCML_RESERVED_MTCDr */
  23517         soc_block_list[112],
  23518         soc_genreg,
  23519         1,
  23520         0,
  23521         0xae,
  23522         0,
  23523         0,
  23524         6,
  23525         soc_BRDC_DCML_RESERVED_MTCDr_fields,
  23526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23527         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  23528         -1,
  23529         -1,
  23530     },
  23531 #endif /* chips */
  23532 
  23533 #if defined(BCM_88790_A0)
  23534     { /* SOC_REG_INT_BRDC_DCML_RESERVED_MTCPr */
  23535         soc_block_list[112],
  23536         soc_genreg,
  23537         1,
  23538         0,
  23539         0xad,
  23540         SOC_REG_FLAG_64_BITS,
  23541         0,
  23542         17,
  23543         soc_BRDC_DCML_RESERVED_MTCPr_fields,
  23544         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  23545         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  23546         -1,
  23547         -1,
  23548     },
  23549 #endif /* chips */
  23550 
  23551 #if defined(BCM_88790_A0)
  23552     { /* SOC_REG_INT_BRDC_DCML_RESERVED_SPARE_0r */
  23553         soc_block_list[112],
  23554         soc_genreg,
  23555         1,
  23556         0,
  23557         0x90,
  23558         0,
  23559         0,
  23560         1,
  23561         soc_BRDC_DCML_RESERVED_SPARE_0r_fields,
  23562         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  23563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23564         -1,
  23565         -1,
  23566     },
  23567 #endif /* chips */
  23568 
  23569 #if defined(BCM_88790_A0)
  23570     { /* SOC_REG_INT_BRDC_DCML_RESERVED_SPARE_1r */
  23571         soc_block_list[112],
  23572         soc_genreg,
  23573         1,
  23574         0,
  23575         0x91,
  23576         0,
  23577         0,
  23578         1,
  23579         soc_BRDC_DCML_RESERVED_SPARE_1r_fields,
  23580         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  23581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23582         -1,
  23583         -1,
  23584     },
  23585 #endif /* chips */
  23586 
  23587 #if defined(BCM_88790_A0)
  23588     { /* SOC_REG_INT_BRDC_DCML_RESERVED_SPARE_2r */
  23589         soc_block_list[112],
  23590         soc_genreg,
  23591         1,
  23592         0,
  23593         0x92,
  23594         0,
  23595         0,
  23596         1,
  23597         soc_BRDC_DCML_RESERVED_SPARE_2r_fields,
  23598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23600         -1,
  23601         -1,
  23602     },
  23603 #endif /* chips */
  23604 
  23605 #if defined(BCM_88790_A0)
  23606     { /* SOC_REG_INT_BRDC_DCML_RESERVED_SPARE_3r */
  23607         soc_block_list[112],
  23608         soc_genreg,
  23609         1,
  23610         0,
  23611         0x93,
  23612         0,
  23613         0,
  23614         1,
  23615         soc_BRDC_DCML_RESERVED_SPARE_3r_fields,
  23616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23618         -1,
  23619         -1,
  23620     },
  23621 #endif /* chips */
  23622 
  23623 #if defined(BCM_88790_A0)
  23624     { /* SOC_REG_INT_BRDC_DCML_SBUS_BROADCAST_IDr */
  23625         soc_block_list[112],
  23626         soc_genreg,
  23627         1,
  23628         0,
  23629         0x86,
  23630         0,
  23631         0,
  23632         1,
  23633         soc_BRDC_DCML_SBUS_BROADCAST_IDr_fields,
  23634         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  23635         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  23636         -1,
  23637         -1,
  23638     },
  23639 #endif /* chips */
  23640 
  23641 #if defined(BCM_88790_A0)
  23642     { /* SOC_REG_INT_BRDC_DCML_SBUS_LAST_IN_CHAINr */
  23643         soc_block_list[112],
  23644         soc_genreg,
  23645         1,
  23646         0,
  23647         0x87,
  23648         0,
  23649         0,
  23650         1,
  23651         soc_BRDC_DCML_SBUS_LAST_IN_CHAINr_fields,
  23652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23653         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  23654         -1,
  23655         -1,
  23656     },
  23657 #endif /* chips */
  23658 
  23659 #if defined(BCM_88790_A0)
  23660     { /* SOC_REG_INT_BRDC_DCML_THREE_PIPES_BMPr */
  23661         soc_block_list[112],
  23662         soc_genreg,
  23663         1,
  23664         0,
  23665         0x10e,
  23666         0,
  23667         0,
  23668         1,
  23669         soc_BRDC_DCML_THREE_PIPES_BMPr_fields,
  23670         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  23671         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  23672         -1,
  23673         -1,
  23674     },
  23675 #endif /* chips */
  23676 
  23677 #if defined(BCM_88790_A0)
  23678     { /* SOC_REG_INT_BRDC_DCML_TOTAL_OUT_CELL_P_CNTr */
  23679         soc_block_list[112],
  23680         soc_genreg,
  23681         3,
  23682         0,
  23683         0x10f,
  23684         SOC_REG_FLAG_ARRAY |
  23685                           SOC_REG_FLAG_RO |
  23686                           SOC_REG_FLAG_REG_ARRAY,
  23687         SOC_REG_FLAG_COUNTER_FEILDS,
  23688         1,
  23689         soc_BRDC_DCML_TOTAL_OUT_CELL_P_CNTr_fields,
  23690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23691         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23692         -1,
  23693         -1,
  23694     },
  23695 #endif /* chips */
  23696 
  23697 #if defined(BCM_88790_A0)
  23698     { /* SOC_REG_INT_BRDC_DCML_TOTAL_OUT_CPU_CAPTURE_CELL_CNTr */
  23699         soc_block_list[112],
  23700         soc_genreg,
  23701         1,
  23702         0,
  23703         0x116,
  23704         SOC_REG_FLAG_RO,
  23705         SOC_REG_FLAG_COUNTER_FEILDS,
  23706         1,
  23707         soc_BRDC_DCML_TOTAL_OUT_CPU_CAPTURE_CELL_CNTr_fields,
  23708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23710         -1,
  23711         -1,
  23712     },
  23713 #endif /* chips */
  23714 
  23715 #if defined(BCM_88790_A0)
  23716     { /* SOC_REG_INT_BRDC_DCML_TOTAL_OUT_CPU_TRANSMIT_CELL_CNTr */
  23717         soc_block_list[112],
  23718         soc_genreg,
  23719         1,
  23720         0,
  23721         0x115,
  23722         SOC_REG_FLAG_RO,
  23723         SOC_REG_FLAG_COUNTER_FEILDS,
  23724         1,
  23725         soc_BRDC_DCML_TOTAL_OUT_CPU_TRANSMIT_CELL_CNTr_fields,
  23726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23728         -1,
  23729         -1,
  23730     },
  23731 #endif /* chips */
  23732 
  23733 #if defined(BCM_88790_A0)
  23734     { /* SOC_REG_INT_BRDC_DCML_TOTAL_OUT_INBAND_CELL_CNTr */
  23735         soc_block_list[112],
  23736         soc_genreg,
  23737         1,
  23738         0,
  23739         0x117,
  23740         SOC_REG_FLAG_RO,
  23741         SOC_REG_FLAG_COUNTER_FEILDS,
  23742         1,
  23743         soc_BRDC_DCML_TOTAL_OUT_INBAND_CELL_CNTr_fields,
  23744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23746         -1,
  23747         -1,
  23748     },
  23749 #endif /* chips */
  23750 
  23751 #if defined(BCM_88790_A0)
  23752     { /* SOC_REG_INT_BRDC_DCML_TOTAL_OUT_WORD_P_CNTr */
  23753         soc_block_list[112],
  23754         soc_genreg,
  23755         3,
  23756         0,
  23757         0x112,
  23758         SOC_REG_FLAG_ARRAY |
  23759                           SOC_REG_FLAG_RO |
  23760                           SOC_REG_FLAG_REG_ARRAY,
  23761         SOC_REG_FLAG_COUNTER_FEILDS,
  23762         1,
  23763         soc_BRDC_DCML_TOTAL_OUT_WORD_P_CNTr_fields,
  23764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23765         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23766         -1,
  23767         -1,
  23768     },
  23769 #endif /* chips */
  23770 
  23771 #if defined(BCM_88790_A0)
  23772     { /* SOC_REG_INT_BRDC_DCML_TWO_PIPES_BMPr */
  23773         soc_block_list[112],
  23774         soc_genreg,
  23775         1,
  23776         0,
  23777         0x10d,
  23778         0,
  23779         0,
  23780         1,
  23781         soc_BRDC_DCML_TWO_PIPES_BMPr_fields,
  23782         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23783         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  23784         -1,
  23785         -1,
  23786     },
  23787 #endif /* chips */
  23788 
  23789 #if defined(BCM_88790_A0)
  23790     { /* SOC_REG_INT_BRDC_DCML_TX_CPU_CELL_DATA_0r */
  23791         soc_block_list[112],
  23792         soc_genreg,
  23793         1,
  23794         0,
  23795         0x118,
  23796         SOC_REG_FLAG_ABOVE_64_BITS,
  23797         0,
  23798         1,
  23799         soc_BRDC_DCML_TX_CPU_CELL_DATA_0r_fields,
  23800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23801         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23802         -1,
  23803         -1,
  23804     },
  23805 #endif /* chips */
  23806 
  23807 #if defined(BCM_88790_A0)
  23808     { /* SOC_REG_INT_BRDC_DCML_TX_CPU_CELL_DATA_1r */
  23809         soc_block_list[112],
  23810         soc_genreg,
  23811         1,
  23812         0,
  23813         0x120,
  23814         SOC_REG_FLAG_ABOVE_64_BITS,
  23815         0,
  23816         1,
  23817         soc_BRDC_DCML_TX_CPU_CELL_DATA_1r_fields,
  23818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23819         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23820         -1,
  23821         -1,
  23822     },
  23823 #endif /* chips */
  23824 
  23825 #if defined(BCM_88790_A0)
  23826     { /* SOC_REG_INT_BRDC_DCML_TX_CPU_CELL_HEADERr */
  23827         soc_block_list[112],
  23828         soc_genreg,
  23829         1,
  23830         0,
  23831         0x128,
  23832         SOC_REG_FLAG_ABOVE_64_BITS,
  23833         0,
  23834         1,
  23835         soc_BRDC_DCML_TX_CPU_CELL_HEADERr_fields,
  23836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23837         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  23838         -1,
  23839         -1,
  23840     },
  23841 #endif /* chips */
  23842 
  23843 #if defined(BCM_88950_A0)
  23844     { /* SOC_REG_INT_BRDC_DCM_DCL_FLOW_CONTROL_CNT_Pr */
  23845         soc_block_list[100],
  23846         soc_genreg,
  23847         3,
  23848         0,
  23849         0x15f,
  23850         SOC_REG_FLAG_ARRAY |
  23851                           SOC_REG_FLAG_RO |
  23852                           SOC_REG_FLAG_WO |
  23853                           SOC_REG_FLAG_REG_ARRAY,
  23854         0,
  23855         2,
  23856         soc_BRDC_DCM_DCL_FLOW_CONTROL_CNT_Pr_fields,
  23857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23859         -1,
  23860         -1,
  23861     },
  23862 #endif /* chips */
  23863 
  23864 #if defined(BCM_88950_A0)
  23865     { /* SOC_REG_INT_BRDC_DCM_DCM_ENABLERS_REGISTERr */
  23866         soc_block_list[100],
  23867         soc_genreg,
  23868         1,
  23869         0,
  23870         0x101,
  23871         SOC_REG_FLAG_WO,
  23872         0,
  23873         7,
  23874         soc_BRDC_DCM_DCM_ENABLERS_REGISTERr_fields,
  23875         SOC_RESET_VAL_DEC(0x00201000, 0x00000000)
  23876         SOC_RESET_MASK_DEC(0x00371fff, 0x00000000)
  23877         -1,
  23878         -1,
  23879     },
  23880 #endif /* chips */
  23881 
  23882 #if defined(BCM_88950_A0)
  23883     { /* SOC_REG_INT_BRDC_DCM_DCM_MAX_OCUP_Pr */
  23884         soc_block_list[100],
  23885         soc_genreg,
  23886         3,
  23887         0,
  23888         0x150,
  23889         SOC_REG_FLAG_64_BITS |
  23890                           SOC_REG_FLAG_ARRAY |
  23891                           SOC_REG_FLAG_RO |
  23892                           SOC_REG_FLAG_WO |
  23893                           SOC_REG_FLAG_REG_ARRAY,
  23894         0,
  23895         4,
  23896         soc_BRDC_DCM_DCM_MAX_OCUP_Pr_fields,
  23897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23898         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00007ff7)
  23899         -1,
  23900         -1,
  23901     },
  23902 #endif /* chips */
  23903 
  23904 #if defined(BCM_88950_A0)
  23905     { /* SOC_REG_INT_BRDC_DCM_DROP_IP_PRI_P_0_CNTr */
  23906         soc_block_list[100],
  23907         soc_genreg,
  23908         4,
  23909         0,
  23910         0x13b,
  23911         SOC_REG_FLAG_ARRAY |
  23912                           SOC_REG_FLAG_RO |
  23913                           SOC_REG_FLAG_WO |
  23914                           SOC_REG_FLAG_REG_ARRAY,
  23915         0,
  23916         2,
  23917         soc_BRDC_DCM_DROP_IP_PRI_P_0_CNTr_fields,
  23918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23919         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23920         -1,
  23921         -1,
  23922     },
  23923 #endif /* chips */
  23924 
  23925 #if defined(BCM_88950_A0)
  23926     { /* SOC_REG_INT_BRDC_DCM_DROP_IP_PRI_P_1_CNTr */
  23927         soc_block_list[100],
  23928         soc_genreg,
  23929         4,
  23930         0,
  23931         0x13f,
  23932         SOC_REG_FLAG_ARRAY |
  23933                           SOC_REG_FLAG_RO |
  23934                           SOC_REG_FLAG_WO |
  23935                           SOC_REG_FLAG_REG_ARRAY,
  23936         0,
  23937         2,
  23938         soc_BRDC_DCM_DROP_IP_PRI_P_1_CNTr_fields,
  23939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23940         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23941         -1,
  23942         -1,
  23943     },
  23944 #endif /* chips */
  23945 
  23946 #if defined(BCM_88950_A0)
  23947     { /* SOC_REG_INT_BRDC_DCM_DROP_IP_PRI_P_2_CNTr */
  23948         soc_block_list[100],
  23949         soc_genreg,
  23950         4,
  23951         0,
  23952         0x143,
  23953         SOC_REG_FLAG_ARRAY |
  23954                           SOC_REG_FLAG_RO |
  23955                           SOC_REG_FLAG_WO |
  23956                           SOC_REG_FLAG_REG_ARRAY,
  23957         0,
  23958         2,
  23959         soc_BRDC_DCM_DROP_IP_PRI_P_2_CNTr_fields,
  23960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23962         -1,
  23963         -1,
  23964     },
  23965 #endif /* chips */
  23966 
  23967 #if defined(BCM_88950_A0)
  23968     { /* SOC_REG_INT_BRDC_DCM_DROP_TOTAL_P_CNTr */
  23969         soc_block_list[100],
  23970         soc_genreg,
  23971         3,
  23972         0,
  23973         0x147,
  23974         SOC_REG_FLAG_ARRAY |
  23975                           SOC_REG_FLAG_RO |
  23976                           SOC_REG_FLAG_WO |
  23977                           SOC_REG_FLAG_REG_ARRAY,
  23978         0,
  23979         2,
  23980         soc_BRDC_DCM_DROP_TOTAL_P_CNTr_fields,
  23981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  23982         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  23983         -1,
  23984         -1,
  23985     },
  23986 #endif /* chips */
  23987 
  23988 #if defined(BCM_88950_A0)
  23989     { /* SOC_REG_INT_BRDC_DCM_DYN_PIPES_WEIGHTS_REGISTERr */
  23990         soc_block_list[100],
  23991         soc_genreg,
  23992         1,
  23993         0,
  23994         0x121,
  23995         SOC_REG_FLAG_WO,
  23996         0,
  23997         4,
  23998         soc_BRDC_DCM_DYN_PIPES_WEIGHTS_REGISTERr_fields,
  23999         SOC_RESET_VAL_DEC(0x01010101, 0x00000000)
  24000         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  24001         -1,
  24002         -1,
  24003     },
  24004 #endif /* chips */
  24005 
  24006 #if defined(BCM_88950_A0)
  24007     { /* SOC_REG_INT_BRDC_DCM_DYN_WFQ_WEIGHT_THD_REGISTERr */
  24008         soc_block_list[100],
  24009         soc_genreg,
  24010         1,
  24011         0,
  24012         0x122,
  24013         SOC_REG_FLAG_WO,
  24014         0,
  24015         2,
  24016         soc_BRDC_DCM_DYN_WFQ_WEIGHT_THD_REGISTERr_fields,
  24017         SOC_RESET_VAL_DEC(0x007ff7ff, 0x00000000)
  24018         SOC_RESET_MASK_DEC(0x007ff7ff, 0x00000000)
  24019         -1,
  24020         -1,
  24021     },
  24022 #endif /* chips */
  24023 
  24024 #if defined(BCM_88950_A0)
  24025     { /* SOC_REG_INT_BRDC_DCM_ECC_1B_ERR_CNTr */
  24026         soc_block_list[100],
  24027         soc_genreg,
  24028         1,
  24029         0,
  24030         0x94,
  24031         SOC_REG_FLAG_64_BITS |
  24032                           SOC_REG_FLAG_RO |
  24033                           SOC_REG_FLAG_WO,
  24034         0,
  24035         4,
  24036         soc_BRDC_CCS_ECC_1B_ERR_CNTr_fields,
  24037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24038         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  24039         -1,
  24040         -1,
  24041     },
  24042 #endif /* chips */
  24043 
  24044 #if defined(BCM_88950_A0)
  24045     { /* SOC_REG_INT_BRDC_DCM_ECC_2B_ERR_CNTr */
  24046         soc_block_list[100],
  24047         soc_genreg,
  24048         1,
  24049         0,
  24050         0x96,
  24051         SOC_REG_FLAG_64_BITS |
  24052                           SOC_REG_FLAG_RO |
  24053                           SOC_REG_FLAG_WO,
  24054         0,
  24055         4,
  24056         soc_BRDC_CCS_ECC_2B_ERR_CNTr_fields,
  24057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24058         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  24059         -1,
  24060         -1,
  24061     },
  24062 #endif /* chips */
  24063 
  24064 #if defined(BCM_88950_A0)
  24065     { /* SOC_REG_INT_BRDC_DCM_ECC_ERR_1B_INITIATEr */
  24066         soc_block_list[100],
  24067         soc_genreg,
  24068         1,
  24069         0,
  24070         0xa4,
  24071         SOC_REG_FLAG_WO,
  24072         0,
  24073         14,
  24074         soc_BRDC_DCM_ECC_ERR_1B_INITIATEr_fields,
  24075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24076         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24077         -1,
  24078         -1,
  24079     },
  24080 #endif /* chips */
  24081 
  24082 #if defined(BCM_88950_A0)
  24083     { /* SOC_REG_INT_BRDC_DCM_ECC_ERR_1B_MONITOR_MEM_MASKr */
  24084         soc_block_list[100],
  24085         soc_genreg,
  24086         1,
  24087         0,
  24088         0x9a,
  24089         SOC_REG_FLAG_WO,
  24090         0,
  24091         20,
  24092         soc_BRDC_DCM_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  24093         SOC_RESET_VAL_DEC(0x000fffff, 0x00000000)
  24094         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  24095         -1,
  24096         -1,
  24097     },
  24098 #endif /* chips */
  24099 
  24100 #if defined(BCM_88950_A0)
  24101     { /* SOC_REG_INT_BRDC_DCM_ECC_ERR_2B_INITIATEr */
  24102         soc_block_list[100],
  24103         soc_genreg,
  24104         1,
  24105         0,
  24106         0xa6,
  24107         SOC_REG_FLAG_WO,
  24108         0,
  24109         14,
  24110         soc_BRDC_DCM_ECC_ERR_2B_INITIATEr_fields,
  24111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24112         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  24113         -1,
  24114         -1,
  24115     },
  24116 #endif /* chips */
  24117 
  24118 #if defined(BCM_88950_A0)
  24119     { /* SOC_REG_INT_BRDC_DCM_ECC_ERR_2B_MONITOR_MEM_MASKr */
  24120         soc_block_list[100],
  24121         soc_genreg,
  24122         1,
  24123         0,
  24124         0x9c,
  24125         SOC_REG_FLAG_WO,
  24126         0,
  24127         20,
  24128         soc_BRDC_DCM_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  24129         SOC_RESET_VAL_DEC(0x000fffff, 0x00000000)
  24130         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  24131         -1,
  24132         -1,
  24133     },
  24134 #endif /* chips */
  24135 
  24136 #if defined(BCM_88950_A0)
  24137     { /* SOC_REG_INT_BRDC_DCM_ECC_INTERRUPT_REGISTERr */
  24138         soc_block_list[100],
  24139         soc_genreg,
  24140         1,
  24141         0,
  24142         0x7,
  24143         SOC_REG_FLAG_WO |
  24144                           SOC_REG_FLAG_INTERRUPT,
  24145         0,
  24146         3,
  24147         soc_BRDC_DCH_ECC_INTERRUPT_REGISTERr_fields,
  24148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24149         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  24150         -1,
  24151         -1,
  24152     },
  24153 #endif /* chips */
  24154 
  24155 #if defined(BCM_88950_A0)
  24156     { /* SOC_REG_INT_BRDC_DCM_ECC_INTERRUPT_REGISTER_MASKr */
  24157         soc_block_list[100],
  24158         soc_genreg,
  24159         1,
  24160         0,
  24161         0x17,
  24162         SOC_REG_FLAG_WO,
  24163         0,
  24164         3,
  24165         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_MASKr_fields,
  24166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24167         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  24168         -1,
  24169         -1,
  24170     },
  24171 #endif /* chips */
  24172 
  24173 #if defined(BCM_88950_A0)
  24174     { /* SOC_REG_INT_BRDC_DCM_ECC_INTERRUPT_REGISTER_TESTr */
  24175         soc_block_list[100],
  24176         soc_genreg,
  24177         1,
  24178         0,
  24179         0x1f,
  24180         SOC_REG_FLAG_WO,
  24181         0,
  24182         1,
  24183         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_TESTr_fields,
  24184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24186         -1,
  24187         -1,
  24188     },
  24189 #endif /* chips */
  24190 
  24191 #if defined(BCM_88950_A0)
  24192     { /* SOC_REG_INT_BRDC_DCM_ERROR_INITIATION_DATAr */
  24193         soc_block_list[100],
  24194         soc_genreg,
  24195         1,
  24196         0,
  24197         0xa3,
  24198         SOC_REG_FLAG_WO,
  24199         0,
  24200         1,
  24201         soc_BRDC_CCS_ERROR_INITIATION_DATAr_fields,
  24202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24203         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24204         -1,
  24205         -1,
  24206     },
  24207 #endif /* chips */
  24208 
  24209 #if defined(BCM_88950_A0)
  24210     { /* SOC_REG_INT_BRDC_DCM_FIFOS_DEPTH_TYPEr */
  24211         soc_block_list[100],
  24212         soc_genreg,
  24213         2,
  24214         0,
  24215         0x106,
  24216         SOC_REG_FLAG_ARRAY |
  24217                           SOC_REG_FLAG_WO |
  24218                           SOC_REG_FLAG_REG_ARRAY,
  24219         0,
  24220         2,
  24221         soc_BRDC_DCM_FIFOS_DEPTH_TYPEr_fields,
  24222         SOC_RESET_VAL_DEC(0x00180180, 0x00000000)
  24223         SOC_RESET_MASK_DEC(0x007ff7ff, 0x00000000)
  24224         -1,
  24225         -1,
  24226     },
  24227 #endif /* chips */
  24228 
  24229 #if defined(BCM_88950_A0)
  24230     { /* SOC_REG_INT_BRDC_DCM_FIFOS_THRESHOLDS_P_TYPE_0r */
  24231         soc_block_list[100],
  24232         soc_genreg,
  24233         3,
  24234         0,
  24235         0x114,
  24236         SOC_REG_FLAG_64_BITS |
  24237                           SOC_REG_FLAG_ARRAY |
  24238                           SOC_REG_FLAG_WO |
  24239                           SOC_REG_FLAG_REG_ARRAY,
  24240         0,
  24241         3,
  24242         soc_BRDC_DCM_FIFOS_THRESHOLDS_P_TYPE_0r_fields,
  24243         SOC_RESET_VAL_DEC(0xff168168, 0x00000007)
  24244         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  24245         -1,
  24246         -1,
  24247     },
  24248 #endif /* chips */
  24249 
  24250 #if defined(BCM_88950_A0)
  24251     { /* SOC_REG_INT_BRDC_DCM_FIFOS_THRESHOLDS_P_TYPE_1r */
  24252         soc_block_list[100],
  24253         soc_genreg,
  24254         3,
  24255         0,
  24256         0x11a,
  24257         SOC_REG_FLAG_64_BITS |
  24258                           SOC_REG_FLAG_ARRAY |
  24259                           SOC_REG_FLAG_WO |
  24260                           SOC_REG_FLAG_REG_ARRAY,
  24261         0,
  24262         3,
  24263         soc_BRDC_DCM_FIFOS_THRESHOLDS_P_TYPE_1r_fields,
  24264         SOC_RESET_VAL_DEC(0xff168168, 0x00000007)
  24265         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  24266         -1,
  24267         -1,
  24268     },
  24269 #endif /* chips */
  24270 
  24271 #if defined(BCM_88950_A0)
  24272     { /* SOC_REG_INT_BRDC_DCM_FIFO_TYPEr */
  24273         soc_block_list[100],
  24274         soc_genreg,
  24275         1,
  24276         0,
  24277         0x102,
  24278         SOC_REG_FLAG_WO,
  24279         0,
  24280         1,
  24281         soc_BRDC_DCM_FIFO_TYPEr_fields,
  24282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24283         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  24284         -1,
  24285         -1,
  24286     },
  24287 #endif /* chips */
  24288 
  24289 #if defined(BCM_88950_A0)
  24290     { /* SOC_REG_INT_BRDC_DCM_GCI_TH_P_TYPE_0r */
  24291         soc_block_list[100],
  24292         soc_genreg,
  24293         3,
  24294         0,
  24295         0x123,
  24296         SOC_REG_FLAG_64_BITS |
  24297                           SOC_REG_FLAG_ARRAY |
  24298                           SOC_REG_FLAG_WO |
  24299                           SOC_REG_FLAG_REG_ARRAY,
  24300         0,
  24301         3,
  24302         soc_BRDC_DCM_GCI_TH_P_TYPE_0r_fields,
  24303         SOC_RESET_VAL_DEC(0x68140118, 0x00000001)
  24304         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  24305         -1,
  24306         -1,
  24307     },
  24308 #endif /* chips */
  24309 
  24310 #if defined(BCM_88950_A0)
  24311     { /* SOC_REG_INT_BRDC_DCM_GCI_TH_P_TYPE_1r */
  24312         soc_block_list[100],
  24313         soc_genreg,
  24314         3,
  24315         0,
  24316         0x129,
  24317         SOC_REG_FLAG_64_BITS |
  24318                           SOC_REG_FLAG_ARRAY |
  24319                           SOC_REG_FLAG_WO |
  24320                           SOC_REG_FLAG_REG_ARRAY,
  24321         0,
  24322         3,
  24323         soc_BRDC_DCM_GCI_TH_P_TYPE_1r_fields,
  24324         SOC_RESET_VAL_DEC(0x68140118, 0x00000001)
  24325         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  24326         -1,
  24327         -1,
  24328     },
  24329 #endif /* chips */
  24330 
  24331 #if defined(BCM_88950_A0)
  24332     { /* SOC_REG_INT_BRDC_DCM_GLOBAL_DCH_CAPTURE_CELLS_DCLr */
  24333         soc_block_list[100],
  24334         soc_genreg,
  24335         1,
  24336         0,
  24337         0xf5,
  24338         SOC_REG_FLAG_WO,
  24339         0,
  24340         4,
  24341         soc_BRDC_DCM_GLOBAL_DCH_CAPTURE_CELLS_DCLr_fields,
  24342         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
  24343         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  24344         -1,
  24345         -1,
  24346     },
  24347 #endif /* chips */
  24348 
  24349 #if defined(BCM_88950_A0)
  24350     { /* SOC_REG_INT_BRDC_DCM_GLOBAL_GENERAL_CFG_1r */
  24351         soc_block_list[100],
  24352         soc_genreg,
  24353         1,
  24354         0,
  24355         0xc1,
  24356         SOC_REG_FLAG_WO,
  24357         0,
  24358         3,
  24359         soc_BRDC_DCH_GLOBAL_GENERAL_CFG_1r_fields,
  24360         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  24361         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  24362         -1,
  24363         -1,
  24364     },
  24365 #endif /* chips */
  24366 
  24367 #if defined(BCM_88950_A0)
  24368     { /* SOC_REG_INT_BRDC_DCM_GLOBAL_GENERAL_FE_CFG_1r */
  24369         soc_block_list[100],
  24370         soc_genreg,
  24371         1,
  24372         0,
  24373         0xf4,
  24374         SOC_REG_FLAG_WO,
  24375         0,
  24376         8,
  24377         soc_BRDC_DCH_GLOBAL_GENERAL_FE_CFG_1r_fields,
  24378         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  24379         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  24380         -1,
  24381         -1,
  24382     },
  24383 #endif /* chips */
  24384 
  24385 #if defined(BCM_88950_A0)
  24386     { /* SOC_REG_INT_BRDC_DCM_GLOBAL_MEM_OPTIONSr */
  24387         soc_block_list[100],
  24388         soc_genreg,
  24389         1,
  24390         0,
  24391         0xc0,
  24392         SOC_REG_FLAG_WO,
  24393         0,
  24394         3,
  24395         soc_BRDC_DCH_GLOBAL_MEM_OPTIONSr_fields,
  24396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24397         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  24398         -1,
  24399         -1,
  24400     },
  24401 #endif /* chips */
  24402 
  24403 #if defined(BCM_88950_A0)
  24404     { /* SOC_REG_INT_BRDC_DCM_GTIMER_CONFIGURATIONr */
  24405         soc_block_list[100],
  24406         soc_genreg,
  24407         1,
  24408         0,
  24409         0x88,
  24410         SOC_REG_FLAG_WO,
  24411         0,
  24412         3,
  24413         soc_BRDC_CCS_GTIMER_CONFIGURATIONr_fields,
  24414         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  24415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24416         -1,
  24417         -1,
  24418     },
  24419 #endif /* chips */
  24420 
  24421 #if defined(BCM_88950_A0)
  24422     { /* SOC_REG_INT_BRDC_DCM_GTIMER_TRIGGERr */
  24423         soc_block_list[100],
  24424         soc_genreg,
  24425         1,
  24426         0,
  24427         0x89,
  24428         SOC_REG_FLAG_RO |
  24429                           SOC_REG_FLAG_WO,
  24430         0,
  24431         1,
  24432         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  24433         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24434         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24435         -1,
  24436         -1,
  24437     },
  24438 #endif /* chips */
  24439 
  24440 #if defined(BCM_88950_A0)
  24441     { /* SOC_REG_INT_BRDC_DCM_INTERRUPT_MASK_REGISTERr */
  24442         soc_block_list[100],
  24443         soc_genreg,
  24444         1,
  24445         0,
  24446         0x10,
  24447         SOC_REG_FLAG_WO,
  24448         0,
  24449         13,
  24450         soc_BRDC_DCM_INTERRUPT_MASK_REGISTERr_fields,
  24451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24452         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  24453         -1,
  24454         -1,
  24455     },
  24456 #endif /* chips */
  24457 
  24458 #if defined(BCM_88950_A0)
  24459     { /* SOC_REG_INT_BRDC_DCM_INTERRUPT_REGISTERr */
  24460         soc_block_list[100],
  24461         soc_genreg,
  24462         1,
  24463         0,
  24464         0,
  24465         SOC_REG_FLAG_WO |
  24466                           SOC_REG_FLAG_INTERRUPT,
  24467         0,
  24468         13,
  24469         soc_BRDC_DCM_INTERRUPT_REGISTERr_fields,
  24470         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24471         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  24472         -1,
  24473         -1,
  24474     },
  24475 #endif /* chips */
  24476 
  24477 #if defined(BCM_88950_A0)
  24478     { /* SOC_REG_INT_BRDC_DCM_INTERRUPT_REGISTER_TESTr */
  24479         soc_block_list[100],
  24480         soc_genreg,
  24481         1,
  24482         0,
  24483         0x18,
  24484         SOC_REG_FLAG_WO,
  24485         0,
  24486         1,
  24487         soc_BRDC_CCS_INTERRUPT_REGISTER_TESTr_fields,
  24488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24490         -1,
  24491         -1,
  24492     },
  24493 #endif /* chips */
  24494 
  24495 #if defined(BCM_88950_A0)
  24496     { /* SOC_REG_INT_BRDC_DCM_MC_LOW_PRIO_REP_THD_P_TYPE_0r */
  24497         soc_block_list[100],
  24498         soc_genreg,
  24499         3,
  24500         0,
  24501         0x156,
  24502         SOC_REG_FLAG_ARRAY |
  24503                           SOC_REG_FLAG_WO |
  24504                           SOC_REG_FLAG_REG_ARRAY,
  24505         0,
  24506         2,
  24507         soc_BRDC_DCM_MC_LOW_PRIO_REP_THD_P_TYPE_0r_fields,
  24508         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  24509         SOC_RESET_MASK_DEC(0x000f1fff, 0x00000000)
  24510         -1,
  24511         -1,
  24512     },
  24513 #endif /* chips */
  24514 
  24515 #if defined(BCM_88950_A0)
  24516     { /* SOC_REG_INT_BRDC_DCM_MC_LOW_PRIO_REP_THD_P_TYPE_1r */
  24517         soc_block_list[100],
  24518         soc_genreg,
  24519         3,
  24520         0,
  24521         0x159,
  24522         SOC_REG_FLAG_ARRAY |
  24523                           SOC_REG_FLAG_WO |
  24524                           SOC_REG_FLAG_REG_ARRAY,
  24525         0,
  24526         2,
  24527         soc_BRDC_DCM_MC_LOW_PRIO_REP_THD_P_TYPE_1r_fields,
  24528         SOC_RESET_VAL_DEC(0x00000180, 0x00000000)
  24529         SOC_RESET_MASK_DEC(0x000f1fff, 0x00000000)
  24530         -1,
  24531         -1,
  24532     },
  24533 #endif /* chips */
  24534 
  24535 #if defined(BCM_88950_A0)
  24536     { /* SOC_REG_INT_BRDC_DCM_MC_LP_CELL_DRP_CNT_Pr */
  24537         soc_block_list[100],
  24538         soc_genreg,
  24539         3,
  24540         0,
  24541         0x15c,
  24542         SOC_REG_FLAG_ARRAY |
  24543                           SOC_REG_FLAG_RO |
  24544                           SOC_REG_FLAG_WO |
  24545                           SOC_REG_FLAG_REG_ARRAY,
  24546         0,
  24547         2,
  24548         soc_BRDC_DCM_MC_LP_CELL_DRP_CNT_Pr_fields,
  24549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24550         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24551         -1,
  24552         -1,
  24553     },
  24554 #endif /* chips */
  24555 
  24556 #if defined(BCM_88950_A0)
  24557     { /* SOC_REG_INT_BRDC_DCM_PIPES_WEIGHTS_REGISTERr */
  24558         soc_block_list[100],
  24559         soc_genreg,
  24560         1,
  24561         0,
  24562         0x120,
  24563         SOC_REG_FLAG_WO,
  24564         0,
  24565         4,
  24566         soc_BRDC_DCM_PIPES_WEIGHTS_REGISTERr_fields,
  24567         SOC_RESET_VAL_DEC(0x00010101, 0x00000000)
  24568         SOC_RESET_MASK_DEC(0x077f7f7f, 0x00000000)
  24569         -1,
  24570         -1,
  24571     },
  24572 #endif /* chips */
  24573 
  24574 #if defined(BCM_88950_A0)
  24575     { /* SOC_REG_INT_BRDC_DCM_PIPE_0_PRIORITY_DROP_THRESHOLD_TYPEr */
  24576         soc_block_list[100],
  24577         soc_genreg,
  24578         2,
  24579         0,
  24580         0x108,
  24581         SOC_REG_FLAG_64_BITS |
  24582                           SOC_REG_FLAG_ARRAY |
  24583                           SOC_REG_FLAG_WO |
  24584                           SOC_REG_FLAG_REG_ARRAY,
  24585         0,
  24586         4,
  24587         soc_BRDC_DCM_PIPE_0_PRIORITY_DROP_THRESHOLD_TYPEr_fields,
  24588         SOC_RESET_VAL_DEC(0x2c122118, 0x00001681)
  24589         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00007ff7)
  24590         -1,
  24591         -1,
  24592     },
  24593 #endif /* chips */
  24594 
  24595 #if defined(BCM_88950_A0)
  24596     { /* SOC_REG_INT_BRDC_DCM_PIPE_1_PRIORITY_DROP_THRESHOLD_TYPEr */
  24597         soc_block_list[100],
  24598         soc_genreg,
  24599         2,
  24600         0,
  24601         0x10c,
  24602         SOC_REG_FLAG_64_BITS |
  24603                           SOC_REG_FLAG_ARRAY |
  24604                           SOC_REG_FLAG_WO |
  24605                           SOC_REG_FLAG_REG_ARRAY,
  24606         0,
  24607         4,
  24608         soc_BRDC_DCM_PIPE_1_PRIORITY_DROP_THRESHOLD_TYPEr_fields,
  24609         SOC_RESET_VAL_DEC(0x2c122118, 0x00001681)
  24610         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00007ff7)
  24611         -1,
  24612         -1,
  24613     },
  24614 #endif /* chips */
  24615 
  24616 #if defined(BCM_88950_A0)
  24617     { /* SOC_REG_INT_BRDC_DCM_PIPE_2_PRIORITY_DROP_THRESHOLD_TYPEr */
  24618         soc_block_list[100],
  24619         soc_genreg,
  24620         2,
  24621         0,
  24622         0x110,
  24623         SOC_REG_FLAG_64_BITS |
  24624                           SOC_REG_FLAG_ARRAY |
  24625                           SOC_REG_FLAG_WO |
  24626                           SOC_REG_FLAG_REG_ARRAY,
  24627         0,
  24628         4,
  24629         soc_BRDC_DCM_PIPE_2_PRIORITY_DROP_THRESHOLD_TYPEr_fields,
  24630         SOC_RESET_VAL_DEC(0x2c122118, 0x00001681)
  24631         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00007ff7)
  24632         -1,
  24633         -1,
  24634     },
  24635 #endif /* chips */
  24636 
  24637 #if defined(BCM_88950_A0)
  24638     { /* SOC_REG_INT_BRDC_DCM_RCI_TH_P_TYPE_0r */
  24639         soc_block_list[100],
  24640         soc_genreg,
  24641         3,
  24642         0,
  24643         0x12f,
  24644         SOC_REG_FLAG_64_BITS |
  24645                           SOC_REG_FLAG_ARRAY |
  24646                           SOC_REG_FLAG_WO |
  24647                           SOC_REG_FLAG_REG_ARRAY,
  24648         0,
  24649         3,
  24650         soc_BRDC_DCM_RCI_TH_P_TYPE_0r_fields,
  24651         SOC_RESET_VAL_DEC(0x68140118, 0x00000001)
  24652         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  24653         -1,
  24654         -1,
  24655     },
  24656 #endif /* chips */
  24657 
  24658 #if defined(BCM_88950_A0)
  24659     { /* SOC_REG_INT_BRDC_DCM_RCI_TH_P_TYPE_1r */
  24660         soc_block_list[100],
  24661         soc_genreg,
  24662         3,
  24663         0,
  24664         0x135,
  24665         SOC_REG_FLAG_64_BITS |
  24666                           SOC_REG_FLAG_ARRAY |
  24667                           SOC_REG_FLAG_WO |
  24668                           SOC_REG_FLAG_REG_ARRAY,
  24669         0,
  24670         3,
  24671         soc_BRDC_DCM_RCI_TH_P_TYPE_1r_fields,
  24672         SOC_RESET_VAL_DEC(0x68140118, 0x00000001)
  24673         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  24674         -1,
  24675         -1,
  24676     },
  24677 #endif /* chips */
  24678 
  24679 #if defined(BCM_88950_A0)
  24680     { /* SOC_REG_INT_BRDC_DCM_REG_0100r */
  24681         soc_block_list[100],
  24682         soc_genreg,
  24683         1,
  24684         0,
  24685         0x100,
  24686         SOC_REG_FLAG_WO,
  24687         0,
  24688         1,
  24689         soc_BRDC_DCM_REG_0100r_fields,
  24690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24691         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  24692         -1,
  24693         -1,
  24694     },
  24695 #endif /* chips */
  24696 
  24697 #if defined(BCM_88950_A0)
  24698     { /* SOC_REG_INT_BRDC_DCM_REG_0103r */
  24699         soc_block_list[100],
  24700         soc_genreg,
  24701         3,
  24702         0,
  24703         0x103,
  24704         SOC_REG_FLAG_ARRAY |
  24705                           SOC_REG_FLAG_WO |
  24706                           SOC_REG_FLAG_REG_ARRAY,
  24707         0,
  24708         1,
  24709         soc_BRDC_DCM_REG_0103r_fields,
  24710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24711         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  24712         -1,
  24713         -1,
  24714     },
  24715 #endif /* chips */
  24716 
  24717 #if defined(BCM_88950_A0)
  24718     { /* SOC_REG_INT_BRDC_DCM_RESERVED_MIRROR_ADDRr */
  24719         soc_block_list[100],
  24720         soc_genreg,
  24721         1,
  24722         0,
  24723         0x85,
  24724         SOC_REG_FLAG_WO,
  24725         0,
  24726         2,
  24727         soc_BRDC_CCS_RESERVED_MIRROR_ADDRr_fields,
  24728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24729         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  24730         -1,
  24731         -1,
  24732     },
  24733 #endif /* chips */
  24734 
  24735 #if defined(BCM_88950_A0)
  24736     { /* SOC_REG_INT_BRDC_DCM_RESERVED_MTCPr */
  24737         soc_block_list[100],
  24738         soc_genreg,
  24739         1,
  24740         0,
  24741         0xad,
  24742         SOC_REG_FLAG_64_BITS |
  24743                           SOC_REG_FLAG_WO,
  24744         0,
  24745         18,
  24746         soc_BRDC_CCS_RESERVED_MTCPr_fields,
  24747         SOC_RESET_VAL_DEC(0x80000000, 0x00000001)
  24748         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
  24749         -1,
  24750         -1,
  24751     },
  24752 #endif /* chips */
  24753 
  24754 #if defined(BCM_88950_A0)
  24755     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_0r */
  24756         soc_block_list[100],
  24757         soc_genreg,
  24758         1,
  24759         0,
  24760         0xb0,
  24761         SOC_REG_FLAG_WO,
  24762         0,
  24763         1,
  24764         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  24765         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  24766         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24767         -1,
  24768         -1,
  24769     },
  24770 #endif /* chips */
  24771 
  24772 #if defined(BCM_88950_A0)
  24773     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_1r */
  24774         soc_block_list[100],
  24775         soc_genreg,
  24776         1,
  24777         0,
  24778         0xb3,
  24779         SOC_REG_FLAG_WO,
  24780         0,
  24781         1,
  24782         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  24783         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  24784         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24785         -1,
  24786         -1,
  24787     },
  24788 #endif /* chips */
  24789 
  24790 #if defined(BCM_88950_A0)
  24791     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_2r */
  24792         soc_block_list[100],
  24793         soc_genreg,
  24794         1,
  24795         0,
  24796         0xb6,
  24797         SOC_REG_FLAG_WO,
  24798         0,
  24799         1,
  24800         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  24801         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  24802         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24803         -1,
  24804         -1,
  24805     },
  24806 #endif /* chips */
  24807 
  24808 #if defined(BCM_88950_A0)
  24809     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_4r */
  24810         soc_block_list[100],
  24811         soc_genreg,
  24812         1,
  24813         0,
  24814         0xbc,
  24815         SOC_REG_FLAG_WO,
  24816         0,
  24817         1,
  24818         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  24819         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  24820         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24821         -1,
  24822         -1,
  24823     },
  24824 #endif /* chips */
  24825 
  24826 #if defined(BCM_88950_A0)
  24827     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_0_Sr */
  24828         soc_block_list[100],
  24829         soc_genreg,
  24830         1,
  24831         0,
  24832         0xb1,
  24833         SOC_REG_FLAG_RO |
  24834                           SOC_REG_FLAG_WO,
  24835         0,
  24836         3,
  24837         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  24838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24840         -1,
  24841         -1,
  24842     },
  24843 #endif /* chips */
  24844 
  24845 #if defined(BCM_88950_A0)
  24846     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_0_Tr */
  24847         soc_block_list[100],
  24848         soc_genreg,
  24849         1,
  24850         0,
  24851         0xb2,
  24852         SOC_REG_FLAG_WO,
  24853         0,
  24854         2,
  24855         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  24856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24857         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  24858         -1,
  24859         -1,
  24860     },
  24861 #endif /* chips */
  24862 
  24863 #if defined(BCM_88950_A0)
  24864     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_1_Sr */
  24865         soc_block_list[100],
  24866         soc_genreg,
  24867         1,
  24868         0,
  24869         0xb4,
  24870         SOC_REG_FLAG_RO |
  24871                           SOC_REG_FLAG_WO,
  24872         0,
  24873         3,
  24874         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  24875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24877         -1,
  24878         -1,
  24879     },
  24880 #endif /* chips */
  24881 
  24882 #if defined(BCM_88950_A0)
  24883     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_1_Tr */
  24884         soc_block_list[100],
  24885         soc_genreg,
  24886         1,
  24887         0,
  24888         0xb5,
  24889         SOC_REG_FLAG_WO,
  24890         0,
  24891         2,
  24892         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  24893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24894         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  24895         -1,
  24896         -1,
  24897     },
  24898 #endif /* chips */
  24899 
  24900 #if defined(BCM_88950_A0)
  24901     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_2_Sr */
  24902         soc_block_list[100],
  24903         soc_genreg,
  24904         1,
  24905         0,
  24906         0xb7,
  24907         SOC_REG_FLAG_RO |
  24908                           SOC_REG_FLAG_WO,
  24909         0,
  24910         3,
  24911         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  24912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24914         -1,
  24915         -1,
  24916     },
  24917 #endif /* chips */
  24918 
  24919 #if defined(BCM_88950_A0)
  24920     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_2_Tr */
  24921         soc_block_list[100],
  24922         soc_genreg,
  24923         1,
  24924         0,
  24925         0xb8,
  24926         SOC_REG_FLAG_WO,
  24927         0,
  24928         2,
  24929         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  24930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24931         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  24932         -1,
  24933         -1,
  24934     },
  24935 #endif /* chips */
  24936 
  24937 #if defined(BCM_88950_A0)
  24938     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_4_Sr */
  24939         soc_block_list[100],
  24940         soc_genreg,
  24941         1,
  24942         0,
  24943         0xbd,
  24944         SOC_REG_FLAG_RO |
  24945                           SOC_REG_FLAG_WO,
  24946         0,
  24947         3,
  24948         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  24949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24950         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24951         -1,
  24952         -1,
  24953     },
  24954 #endif /* chips */
  24955 
  24956 #if defined(BCM_88950_A0)
  24957     { /* SOC_REG_INT_BRDC_DCM_RESERVED_PCMI_4_Tr */
  24958         soc_block_list[100],
  24959         soc_genreg,
  24960         1,
  24961         0,
  24962         0xbe,
  24963         SOC_REG_FLAG_WO,
  24964         0,
  24965         2,
  24966         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  24967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  24968         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  24969         -1,
  24970         -1,
  24971     },
  24972 #endif /* chips */
  24973 
  24974 #if defined(BCM_88950_A0)
  24975     { /* SOC_REG_INT_BRDC_DCM_RESERVED_SPARE_0r */
  24976         soc_block_list[100],
  24977         soc_genreg,
  24978         1,
  24979         0,
  24980         0x90,
  24981         SOC_REG_FLAG_WO,
  24982         0,
  24983         1,
  24984         soc_BRDC_CCS_RESERVED_SPARE_0r_fields,
  24985         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  24986         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  24987         -1,
  24988         -1,
  24989     },
  24990 #endif /* chips */
  24991 
  24992 #if defined(BCM_88950_A0)
  24993     { /* SOC_REG_INT_BRDC_DCM_RESERVED_SPARE_1r */
  24994         soc_block_list[100],
  24995         soc_genreg,
  24996         1,
  24997         0,
  24998         0x91,
  24999         SOC_REG_FLAG_WO,
  25000         0,
  25001         1,
  25002         soc_BRDC_CCS_RESERVED_SPARE_1r_fields,
  25003         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  25004         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25005         -1,
  25006         -1,
  25007     },
  25008 #endif /* chips */
  25009 
  25010 #if defined(BCM_88950_A0)
  25011     { /* SOC_REG_INT_BRDC_DCM_RESERVED_SPARE_2r */
  25012         soc_block_list[100],
  25013         soc_genreg,
  25014         1,
  25015         0,
  25016         0x92,
  25017         SOC_REG_FLAG_WO,
  25018         0,
  25019         1,
  25020         soc_BRDC_CCS_RESERVED_SPARE_2r_fields,
  25021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25023         -1,
  25024         -1,
  25025     },
  25026 #endif /* chips */
  25027 
  25028 #if defined(BCM_88950_A0)
  25029     { /* SOC_REG_INT_BRDC_DCM_RESERVED_SPARE_3r */
  25030         soc_block_list[100],
  25031         soc_genreg,
  25032         1,
  25033         0,
  25034         0x93,
  25035         SOC_REG_FLAG_WO,
  25036         0,
  25037         1,
  25038         soc_BRDC_CCS_RESERVED_SPARE_3r_fields,
  25039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25040         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25041         -1,
  25042         -1,
  25043     },
  25044 #endif /* chips */
  25045 
  25046 #if defined(BCM_88950_A0)
  25047     { /* SOC_REG_INT_BRDC_DCM_SBUS_BROADCAST_IDr */
  25048         soc_block_list[100],
  25049         soc_genreg,
  25050         1,
  25051         0,
  25052         0x86,
  25053         SOC_REG_FLAG_WO,
  25054         0,
  25055         1,
  25056         soc_BRDC_DCM_SBUS_BROADCAST_IDr_fields,
  25057         SOC_RESET_VAL_DEC(0x00000050, 0x00000000)
  25058         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  25059         -1,
  25060         -1,
  25061     },
  25062 #endif /* chips */
  25063 
  25064 #if defined(BCM_88950_A0)
  25065     { /* SOC_REG_INT_BRDC_DCM_SBUS_LAST_IN_CHAINr */
  25066         soc_block_list[100],
  25067         soc_genreg,
  25068         1,
  25069         0,
  25070         0x87,
  25071         SOC_REG_FLAG_WO,
  25072         0,
  25073         1,
  25074         soc_BRDC_CCS_SBUS_LAST_IN_CHAINr_fields,
  25075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25076         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25077         -1,
  25078         -1,
  25079     },
  25080 #endif /* chips */
  25081 
  25082 #if defined(BCM_88950_A0)
  25083     { /* SOC_REG_INT_BRDC_DCM_TOTAL_IN_CELL_CNT_PABr */
  25084         soc_block_list[100],
  25085         soc_genreg,
  25086         3,
  25087         0,
  25088         0x14a,
  25089         SOC_REG_FLAG_ARRAY |
  25090                           SOC_REG_FLAG_RO |
  25091                           SOC_REG_FLAG_WO |
  25092                           SOC_REG_FLAG_REG_ARRAY,
  25093         0,
  25094         4,
  25095         soc_BRDC_DCM_TOTAL_IN_CELL_CNT_PABr_fields,
  25096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25097         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25098         -1,
  25099         -1,
  25100     },
  25101 #endif /* chips */
  25102 
  25103 #if defined(BCM_88950_A0)
  25104     { /* SOC_REG_INT_BRDC_DCM_TOTAL_IN_CELL_CNT_PCDr */
  25105         soc_block_list[100],
  25106         soc_genreg,
  25107         3,
  25108         0,
  25109         0x14d,
  25110         SOC_REG_FLAG_ARRAY |
  25111                           SOC_REG_FLAG_RO |
  25112                           SOC_REG_FLAG_WO |
  25113                           SOC_REG_FLAG_REG_ARRAY,
  25114         0,
  25115         4,
  25116         soc_BRDC_DCM_TOTAL_IN_CELL_CNT_PCDr_fields,
  25117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25118         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25119         -1,
  25120         -1,
  25121     },
  25122 #endif /* chips */
  25123 
  25124 #if defined(BCM_88754_A0)
  25125     { /* SOC_REG_INT_BRDC_FMACH_ASYNC_FIFO_ACCESS_READ_DATAr */
  25126         soc_block_list[93],
  25127         soc_genreg,
  25128         1,
  25129         0,
  25130         0xb2,
  25131         SOC_REG_FLAG_RO |
  25132                           SOC_REG_FLAG_WO,
  25133         0,
  25134         5,
  25135         soc_BRDC_FMACH_ASYNC_FIFO_ACCESS_READ_DATAr_fields,
  25136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25137         SOC_RESET_MASK_DEC(0x80ff1f1f, 0x00000000)
  25138         -1,
  25139         -1,
  25140     },
  25141 #endif /* chips */
  25142 
  25143 #if defined(BCM_88754_A0)
  25144     { /* SOC_REG_INT_BRDC_FMACH_ASYNC_FIFO_ACCESS_TRIGGERr */
  25145         soc_block_list[93],
  25146         soc_genreg,
  25147         1,
  25148         0,
  25149         0xb1,
  25150         SOC_REG_FLAG_WO,
  25151         0,
  25152         1,
  25153         soc_BRDC_FMACH_ASYNC_FIFO_ACCESS_TRIGGERr_fields,
  25154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25155         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25156         -1,
  25157         -1,
  25158     },
  25159 #endif /* chips */
  25160 
  25161 #if defined(BCM_88750_A0)
  25162     { /* SOC_REG_INT_BRDC_FMACH_ASYNC_FIFO_CONFIGURATIONr */
  25163         soc_block_list[93],
  25164         soc_genreg,
  25165         4,
  25166         0,
  25167         0xb0,
  25168         SOC_REG_FLAG_64_BITS |
  25169                           SOC_REG_FLAG_ARRAY |
  25170                           SOC_REG_FLAG_WO |
  25171                           SOC_REG_FLAG_REG_ARRAY,
  25172         0,
  25173         14,
  25174         soc_BRDC_FMACH_ASYNC_FIFO_CONFIGURATIONr_fields,
  25175         SOC_RESET_VAL_DEC(0x002a01d5, 0x00000000)
  25176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  25177         -1,
  25178         -1,
  25179     },
  25180 #endif /* chips */
  25181 
  25182 #if defined(BCM_88750_B0)
  25183     { /* SOC_REG_INT_BRDC_FMACH_ASYNC_FIFO_CONFIGURATION_BCM88750_B0r */
  25184         soc_block_list[93],
  25185         soc_genreg,
  25186         4,
  25187         0,
  25188         0xb0,
  25189         SOC_REG_FLAG_64_BITS |
  25190                           SOC_REG_FLAG_ARRAY |
  25191                           SOC_REG_FLAG_WO |
  25192                           SOC_REG_FLAG_REG_ARRAY,
  25193         0,
  25194         16,
  25195         soc_BRDC_FMACH_ASYNC_FIFO_CONFIGURATION_BCM88750_B0r_fields,
  25196         SOC_RESET_VAL_DEC(0x045403d5, 0x00000000)
  25197         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  25198         -1,
  25199         -1,
  25200     },
  25201 #endif /* chips */
  25202 
  25203 #if defined(BCM_88754_A0)
  25204     { /* SOC_REG_INT_BRDC_FMACH_ASYNC_FIFO_CONFIGURATION_BCM88754_A0r */
  25205         soc_block_list[93],
  25206         soc_genreg,
  25207         1,
  25208         0,
  25209         0xb0,
  25210         SOC_REG_FLAG_WO |
  25211                           SOC_REG_FLAG_SIGNAL,
  25212         0,
  25213         19,
  25214         soc_BRDC_FMACH_ASYNC_FIFO_CONFIGURATION_BCM88754_A0r_fields,
  25215         SOC_RESET_VAL_DEC(0x00b4a550, 0x00000000)
  25216         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  25217         -1,
  25218         -1,
  25219     },
  25220 #endif /* chips */
  25221 
  25222 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25223     defined(BCM_88754_A0)
  25224     { /* SOC_REG_INT_BRDC_FMACH_BEC_CONFIGURATIONr */
  25225         soc_block_list[93],
  25226         soc_genreg,
  25227         4,
  25228         0,
  25229         0x1a0,
  25230         SOC_REG_FLAG_ARRAY |
  25231                           SOC_REG_FLAG_WO |
  25232                           SOC_REG_FLAG_REG_ARRAY,
  25233         0,
  25234         7,
  25235         soc_BRDC_FMACH_BEC_CONFIGURATIONr_fields,
  25236         SOC_RESET_VAL_DEC(0xf1015084, 0x00000000)
  25237         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25238         -1,
  25239         -1,
  25240     },
  25241 #endif /* chips */
  25242 
  25243 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25244     defined(BCM_88754_A0)
  25245     { /* SOC_REG_INT_BRDC_FMACH_BEC_STATUSr */
  25246         soc_block_list[93],
  25247         soc_genreg,
  25248         4,
  25249         0,
  25250         0x1a4,
  25251         SOC_REG_FLAG_ARRAY |
  25252                           SOC_REG_FLAG_RO |
  25253                           SOC_REG_FLAG_WO |
  25254                           SOC_REG_FLAG_REG_ARRAY,
  25255         0,
  25256         9,
  25257         soc_BRDC_FMACH_BEC_STATUSr_fields,
  25258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25259         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  25260         -1,
  25261         -1,
  25262     },
  25263 #endif /* chips */
  25264 
  25265 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25266     defined(BCM_88754_A0)
  25267     { /* SOC_REG_INT_BRDC_FMACH_BER_GEN_BITMAPr */
  25268         soc_block_list[93],
  25269         soc_genreg,
  25270         1,
  25271         0,
  25272         0x9b,
  25273         SOC_REG_FLAG_64_BITS |
  25274                           SOC_REG_FLAG_WO,
  25275         0,
  25276         1,
  25277         soc_BRDC_FMACH_BER_GEN_BITMAPr_fields,
  25278         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  25279         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  25280         -1,
  25281         -1,
  25282     },
  25283 #endif /* chips */
  25284 
  25285 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25286     defined(BCM_88754_A0)
  25287     { /* SOC_REG_INT_BRDC_FMACH_BER_GEN_PERIODr */
  25288         soc_block_list[93],
  25289         soc_genreg,
  25290         1,
  25291         0,
  25292         0x9a,
  25293         SOC_REG_FLAG_WO,
  25294         0,
  25295         1,
  25296         soc_FMAC_BER_GEN_PERIOD_BCM83208_A0r_fields,
  25297         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  25298         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25299         -1,
  25300         -1,
  25301     },
  25302 #endif /* chips */
  25303 
  25304 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25305     defined(BCM_88754_A0)
  25306     { /* SOC_REG_INT_BRDC_FMACH_CNTRL_INTRLVD_MODE_REGr */
  25307         soc_block_list[93],
  25308         soc_genreg,
  25309         1,
  25310         0,
  25311         0x22,
  25312         SOC_REG_FLAG_WO,
  25313         0,
  25314         1,
  25315         soc_BRDC_FMACH_CNTRL_INTRLVD_MODE_REGr_fields,
  25316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25317         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  25318         -1,
  25319         -1,
  25320     },
  25321 #endif /* chips */
  25322 
  25323 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25324     defined(BCM_88754_A0)
  25325     { /* SOC_REG_INT_BRDC_FMACH_CONTROL_CELL_BURST_REGISTERr */
  25326         soc_block_list[93],
  25327         soc_genreg,
  25328         1,
  25329         0,
  25330         0x62,
  25331         SOC_REG_FLAG_WO,
  25332         0,
  25333         3,
  25334         soc_BRDC_FMACH_CONTROL_CELL_BURST_REGISTERr_fields,
  25335         SOC_RESET_VAL_DEC(0x0001c008, 0x00000000)
  25336         SOC_RESET_MASK_DEC(0x000ff3ff, 0x00000000)
  25337         -1,
  25338         -1,
  25339     },
  25340 #endif /* chips */
  25341 
  25342 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25343     defined(BCM_88754_A0)
  25344     { /* SOC_REG_INT_BRDC_FMACH_ECC_1B_ERR_ADDRr */
  25345         soc_block_list[93],
  25346         soc_genreg,
  25347         1,
  25348         0,
  25349         0x1e1,
  25350         SOC_REG_FLAG_RO |
  25351                           SOC_REG_FLAG_WO,
  25352         0,
  25353         2,
  25354         soc_BRDC_FMACH_ECC_1B_ERR_ADDRr_fields,
  25355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25356         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25357         -1,
  25358         -1,
  25359     },
  25360 #endif /* chips */
  25361 
  25362 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25363     defined(BCM_88754_A0)
  25364     { /* SOC_REG_INT_BRDC_FMACH_ECC_1B_ERR_CNTr */
  25365         soc_block_list[93],
  25366         soc_genreg,
  25367         1,
  25368         0,
  25369         0x1dd,
  25370         SOC_REG_FLAG_RO |
  25371                           SOC_REG_FLAG_WO,
  25372         0,
  25373         2,
  25374         soc_BRDC_FMACH_ECC_1B_ERR_CNTr_fields,
  25375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25377         -1,
  25378         -1,
  25379     },
  25380 #endif /* chips */
  25381 
  25382 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25383     defined(BCM_88754_A0)
  25384     { /* SOC_REG_INT_BRDC_FMACH_ECC_1B_ERR_MONITOR_MEM_MASKr */
  25385         soc_block_list[93],
  25386         soc_genreg,
  25387         1,
  25388         0,
  25389         0x1df,
  25390         SOC_REG_FLAG_WO,
  25391         0,
  25392         12,
  25393         soc_BRDC_FMACH_ECC_1B_ERR_MONITOR_MEM_MASKr_fields,
  25394         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  25395         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  25396         -1,
  25397         -1,
  25398     },
  25399 #endif /* chips */
  25400 
  25401 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25402     defined(BCM_88754_A0)
  25403     { /* SOC_REG_INT_BRDC_FMACH_ECC_2B_ERR_ADDRr */
  25404         soc_block_list[93],
  25405         soc_genreg,
  25406         1,
  25407         0,
  25408         0x1e2,
  25409         SOC_REG_FLAG_RO |
  25410                           SOC_REG_FLAG_WO,
  25411         0,
  25412         2,
  25413         soc_BRDC_FMACH_ECC_2B_ERR_ADDRr_fields,
  25414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25416         -1,
  25417         -1,
  25418     },
  25419 #endif /* chips */
  25420 
  25421 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25422     defined(BCM_88754_A0)
  25423     { /* SOC_REG_INT_BRDC_FMACH_ECC_2B_ERR_CNTr */
  25424         soc_block_list[93],
  25425         soc_genreg,
  25426         1,
  25427         0,
  25428         0x1de,
  25429         SOC_REG_FLAG_RO |
  25430                           SOC_REG_FLAG_WO,
  25431         0,
  25432         2,
  25433         soc_BRDC_FMACH_ECC_2B_ERR_CNTr_fields,
  25434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25435         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25436         -1,
  25437         -1,
  25438     },
  25439 #endif /* chips */
  25440 
  25441 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25442     defined(BCM_88754_A0)
  25443     { /* SOC_REG_INT_BRDC_FMACH_ECC_2B_ERR_MONITOR_MEM_MASKr */
  25444         soc_block_list[93],
  25445         soc_genreg,
  25446         1,
  25447         0,
  25448         0x1e0,
  25449         SOC_REG_FLAG_WO,
  25450         0,
  25451         12,
  25452         soc_BRDC_FMACH_ECC_2B_ERR_MONITOR_MEM_MASKr_fields,
  25453         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  25454         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  25455         -1,
  25456         -1,
  25457     },
  25458 #endif /* chips */
  25459 
  25460 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25461     defined(BCM_88754_A0)
  25462     { /* SOC_REG_INT_BRDC_FMACH_EDS_CONFIGURATIONr */
  25463         soc_block_list[93],
  25464         soc_genreg,
  25465         4,
  25466         0,
  25467         0xb8,
  25468         SOC_REG_FLAG_ARRAY |
  25469                           SOC_REG_FLAG_WO |
  25470                           SOC_REG_FLAG_REG_ARRAY,
  25471         0,
  25472         14,
  25473         soc_BRDC_FMACH_EDS_CONFIGURATIONr_fields,
  25474         SOC_RESET_VAL_DEC(0x0022001f, 0x00000000)
  25475         SOC_RESET_MASK_DEC(0x33ff001f, 0x00000000)
  25476         -1,
  25477         -1,
  25478     },
  25479 #endif /* chips */
  25480 
  25481 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25482     defined(BCM_88754_A0)
  25483     { /* SOC_REG_INT_BRDC_FMACH_EDS_STATUSr */
  25484         soc_block_list[93],
  25485         soc_genreg,
  25486         4,
  25487         0,
  25488         0xd0,
  25489         SOC_REG_FLAG_ARRAY |
  25490                           SOC_REG_FLAG_RO |
  25491                           SOC_REG_FLAG_WO |
  25492                           SOC_REG_FLAG_REG_ARRAY,
  25493         0,
  25494         5,
  25495         soc_BRDC_FMACH_EDS_STATUSr_fields,
  25496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25497         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  25498         -1,
  25499         -1,
  25500     },
  25501 #endif /* chips */
  25502 
  25503 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25504     defined(BCM_88754_A0)
  25505     { /* SOC_REG_INT_BRDC_FMACH_ERROR_INITIATIONr */
  25506         soc_block_list[93],
  25507         soc_genreg,
  25508         4,
  25509         0,
  25510         0x1e4,
  25511         SOC_REG_FLAG_ARRAY |
  25512                           SOC_REG_FLAG_WO |
  25513                           SOC_REG_FLAG_REG_ARRAY,
  25514         0,
  25515         6,
  25516         soc_BRDC_FMACH_ERROR_INITIATIONr_fields,
  25517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25518         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  25519         -1,
  25520         -1,
  25521     },
  25522 #endif /* chips */
  25523 
  25524 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25525     defined(BCM_88754_A0)
  25526     { /* SOC_REG_INT_BRDC_FMACH_ERROR_INITIATION_DATAr */
  25527         soc_block_list[93],
  25528         soc_genreg,
  25529         1,
  25530         0,
  25531         0x1e3,
  25532         SOC_REG_FLAG_RO |
  25533                           SOC_REG_FLAG_WO,
  25534         0,
  25535         1,
  25536         soc_BRDC_FMACH_ERROR_INITIATION_DATAr_fields,
  25537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25538         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25539         -1,
  25540         -1,
  25541     },
  25542 #endif /* chips */
  25543 
  25544 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25545     defined(BCM_88754_A0)
  25546     { /* SOC_REG_INT_BRDC_FMACH_FBIST_CONFIGURATION_Ar */
  25547         soc_block_list[93],
  25548         soc_genreg,
  25549         1,
  25550         0,
  25551         0x1da,
  25552         SOC_REG_FLAG_WO,
  25553         0,
  25554         8,
  25555         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM83208_A0r_fields,
  25556         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  25557         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  25558         -1,
  25559         -1,
  25560     },
  25561 #endif /* chips */
  25562 
  25563 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25564     defined(BCM_88754_A0)
  25565     { /* SOC_REG_INT_BRDC_FMACH_FBIST_CONFIGURATION_Br */
  25566         soc_block_list[93],
  25567         soc_genreg,
  25568         1,
  25569         0,
  25570         0x1db,
  25571         SOC_REG_FLAG_WO,
  25572         0,
  25573         1,
  25574         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM83208_A0r_fields,
  25575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25576         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  25577         -1,
  25578         -1,
  25579     },
  25580 #endif /* chips */
  25581 
  25582 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25583     defined(BCM_88754_A0)
  25584     { /* SOC_REG_INT_BRDC_FMACH_FBIST_STATUSr */
  25585         soc_block_list[93],
  25586         soc_genreg,
  25587         1,
  25588         0,
  25589         0x1dc,
  25590         SOC_REG_FLAG_RO |
  25591                           SOC_REG_FLAG_WO,
  25592         0,
  25593         1,
  25594         soc_BRDC_FMACH_FBIST_STATUSr_fields,
  25595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25596         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  25597         -1,
  25598         -1,
  25599     },
  25600 #endif /* chips */
  25601 
  25602 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25603     defined(BCM_88754_A0)
  25604     { /* SOC_REG_INT_BRDC_FMACH_FMAL_COMMA_BURST_CONFIGURATIONr */
  25605         soc_block_list[93],
  25606         soc_genreg,
  25607         4,
  25608         0,
  25609         0xa4,
  25610         SOC_REG_FLAG_ARRAY |
  25611                           SOC_REG_FLAG_WO |
  25612                           SOC_REG_FLAG_REG_ARRAY,
  25613         0,
  25614         6,
  25615         soc_BRDC_FMACH_FMAL_COMMA_BURST_CONFIGURATIONr_fields,
  25616         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  25617         SOC_RESET_MASK_DEC(0x8fffffff, 0x00000000)
  25618         -1,
  25619         -1,
  25620     },
  25621 #endif /* chips */
  25622 
  25623 #if defined(BCM_88750_A0)
  25624     { /* SOC_REG_INT_BRDC_FMACH_FMAL_GENERAL_CONFIGURATIONr */
  25625         soc_block_list[93],
  25626         soc_genreg,
  25627         4,
  25628         0,
  25629         0xa0,
  25630         SOC_REG_FLAG_ARRAY |
  25631                           SOC_REG_FLAG_WO |
  25632                           SOC_REG_FLAG_REG_ARRAY,
  25633         0,
  25634         8,
  25635         soc_BRDC_FMACH_FMAL_GENERAL_CONFIGURATIONr_fields,
  25636         SOC_RESET_VAL_DEC(0x00000022, 0x00000000)
  25637         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  25638         -1,
  25639         -1,
  25640     },
  25641 #endif /* chips */
  25642 
  25643 #if defined(BCM_88750_B0)
  25644     { /* SOC_REG_INT_BRDC_FMACH_FMAL_GENERAL_CONFIGURATION_BCM88750_B0r */
  25645         soc_block_list[93],
  25646         soc_genreg,
  25647         4,
  25648         0,
  25649         0xa0,
  25650         SOC_REG_FLAG_ARRAY |
  25651                           SOC_REG_FLAG_WO |
  25652                           SOC_REG_FLAG_REG_ARRAY,
  25653         0,
  25654         11,
  25655         soc_BRDC_FMACH_FMAL_GENERAL_CONFIGURATION_BCM88750_B0r_fields,
  25656         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  25657         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  25658         -1,
  25659         -1,
  25660     },
  25661 #endif /* chips */
  25662 
  25663 #if defined(BCM_88754_A0)
  25664     { /* SOC_REG_INT_BRDC_FMACH_FMAL_GENERAL_CONFIGURATION_BCM88754_A0r */
  25665         soc_block_list[93],
  25666         soc_genreg,
  25667         4,
  25668         0,
  25669         0xa0,
  25670         SOC_REG_FLAG_ARRAY |
  25671                           SOC_REG_FLAG_WO |
  25672                           SOC_REG_FLAG_REG_ARRAY,
  25673         0,
  25674         12,
  25675         soc_BRDC_FMACH_FMAL_GENERAL_CONFIGURATION_BCM88754_A0r_fields,
  25676         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  25677         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  25678         -1,
  25679         -1,
  25680     },
  25681 #endif /* chips */
  25682 
  25683 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25684     defined(BCM_88754_A0)
  25685     { /* SOC_REG_INT_BRDC_FMACH_FMAL_STATISTICS_COUNT_CONTROLr */
  25686         soc_block_list[93],
  25687         soc_genreg,
  25688         1,
  25689         0,
  25690         0x90,
  25691         SOC_REG_FLAG_WO,
  25692         0,
  25693         2,
  25694         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM83208_A0r_fields,
  25695         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25696         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  25697         -1,
  25698         -1,
  25699     },
  25700 #endif /* chips */
  25701 
  25702 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25703     defined(BCM_88754_A0)
  25704     { /* SOC_REG_INT_BRDC_FMACH_FMAL_STATISTICS_GTIMERr */
  25705         soc_block_list[93],
  25706         soc_genreg,
  25707         1,
  25708         0,
  25709         0x91,
  25710         SOC_REG_FLAG_64_BITS |
  25711                           SOC_REG_FLAG_WO,
  25712         0,
  25713         4,
  25714         soc_BRDC_FMACH_FMAL_STATISTICS_GTIMERr_fields,
  25715         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  25716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  25717         -1,
  25718         -1,
  25719     },
  25720 #endif /* chips */
  25721 
  25722 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25723     defined(BCM_88754_A0)
  25724     { /* SOC_REG_INT_BRDC_FMACH_FMAL_STATISTICS_OUTPUTr */
  25725         soc_block_list[93],
  25726         soc_genreg,
  25727         1,
  25728         0,
  25729         0x94,
  25730         SOC_REG_FLAG_64_BITS |
  25731                           SOC_REG_FLAG_RO |
  25732                           SOC_REG_FLAG_WO,
  25733         0,
  25734         2,
  25735         soc_BRDC_FMACH_FMAL_STATISTICS_OUTPUTr_fields,
  25736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25737         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  25738         -1,
  25739         -1,
  25740     },
  25741 #endif /* chips */
  25742 
  25743 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25744     defined(BCM_88754_A0)
  25745     { /* SOC_REG_INT_BRDC_FMACH_FMAL_STATISTICS_OUTPUT_CONTROLr */
  25746         soc_block_list[93],
  25747         soc_genreg,
  25748         1,
  25749         0,
  25750         0x93,
  25751         SOC_REG_FLAG_WO,
  25752         0,
  25753         5,
  25754         soc_BRDC_FMACH_FMAL_STATISTICS_OUTPUT_CONTROLr_fields,
  25755         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  25756         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  25757         -1,
  25758         -1,
  25759     },
  25760 #endif /* chips */
  25761 
  25762 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25763     defined(BCM_88754_A0)
  25764     { /* SOC_REG_INT_BRDC_FMACH_FPS_CONFIGURATION_BERr */
  25765         soc_block_list[93],
  25766         soc_genreg,
  25767         4,
  25768         0,
  25769         0xf0,
  25770         SOC_REG_FLAG_ARRAY |
  25771                           SOC_REG_FLAG_WO |
  25772                           SOC_REG_FLAG_REG_ARRAY,
  25773         0,
  25774         6,
  25775         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM83208_A0r_fields,
  25776         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  25777         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  25778         -1,
  25779         -1,
  25780     },
  25781 #endif /* chips */
  25782 
  25783 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25784     defined(BCM_88754_A0)
  25785     { /* SOC_REG_INT_BRDC_FMACH_FPS_CONFIGURATION_RX_SYNCr */
  25786         soc_block_list[93],
  25787         soc_genreg,
  25788         4,
  25789         0,
  25790         0x100,
  25791         SOC_REG_FLAG_ARRAY |
  25792                           SOC_REG_FLAG_WO |
  25793                           SOC_REG_FLAG_REG_ARRAY,
  25794         0,
  25795         7,
  25796         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM83208_A0r_fields,
  25797         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  25798         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  25799         -1,
  25800         -1,
  25801     },
  25802 #endif /* chips */
  25803 
  25804 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25805     defined(BCM_88754_A0)
  25806     { /* SOC_REG_INT_BRDC_FMACH_FPS_RX_FEC_CONFIGURATIONr */
  25807         soc_block_list[93],
  25808         soc_genreg,
  25809         4,
  25810         0,
  25811         0x110,
  25812         SOC_REG_FLAG_ARRAY |
  25813                           SOC_REG_FLAG_WO |
  25814                           SOC_REG_FLAG_REG_ARRAY,
  25815         0,
  25816         17,
  25817         soc_BRDC_FMACH_FPS_RX_FEC_CONFIGURATIONr_fields,
  25818         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  25819         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25820         -1,
  25821         -1,
  25822     },
  25823 #endif /* chips */
  25824 
  25825 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25826     defined(BCM_88754_A0)
  25827     { /* SOC_REG_INT_BRDC_FMACH_FPS_RX_STATUSr */
  25828         soc_block_list[93],
  25829         soc_genreg,
  25830         4,
  25831         0,
  25832         0x130,
  25833         SOC_REG_FLAG_ARRAY |
  25834                           SOC_REG_FLAG_RO |
  25835                           SOC_REG_FLAG_WO |
  25836                           SOC_REG_FLAG_REG_ARRAY,
  25837         0,
  25838         7,
  25839         soc_BRDC_FMACH_FPS_RX_STATUSr_fields,
  25840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25841         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  25842         -1,
  25843         -1,
  25844     },
  25845 #endif /* chips */
  25846 
  25847 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25848     defined(BCM_88754_A0)
  25849     { /* SOC_REG_INT_BRDC_FMACH_FPS_TX_CONFIGURATIONr */
  25850         soc_block_list[93],
  25851         soc_genreg,
  25852         4,
  25853         0,
  25854         0x120,
  25855         SOC_REG_FLAG_ARRAY |
  25856                           SOC_REG_FLAG_WO |
  25857                           SOC_REG_FLAG_REG_ARRAY,
  25858         0,
  25859         9,
  25860         soc_BRDC_FMACH_FPS_TX_CONFIGURATIONr_fields,
  25861         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  25862         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  25863         -1,
  25864         -1,
  25865     },
  25866 #endif /* chips */
  25867 
  25868 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  25869     { /* SOC_REG_INT_BRDC_FMACH_GENERAL_CONFIGURATION_REGISTERr */
  25870         soc_block_list[93],
  25871         soc_genreg,
  25872         1,
  25873         0,
  25874         0x60,
  25875         SOC_REG_FLAG_WO,
  25876         0,
  25877         13,
  25878         soc_BRDC_FMACH_GENERAL_CONFIGURATION_REGISTERr_fields,
  25879         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  25880         SOC_RESET_MASK_DEC(0x07780f0f, 0x00000000)
  25881         -1,
  25882         -1,
  25883     },
  25884 #endif /* chips */
  25885 
  25886 #if defined(BCM_88754_A0)
  25887     { /* SOC_REG_INT_BRDC_FMACH_GENERAL_CONFIGURATION_REGISTER_BCM88754_A0r */
  25888         soc_block_list[93],
  25889         soc_genreg,
  25890         1,
  25891         0,
  25892         0x60,
  25893         SOC_REG_FLAG_WO,
  25894         0,
  25895         12,
  25896         soc_BRDC_FMACH_GENERAL_CONFIGURATION_REGISTER_BCM88754_A0r_fields,
  25897         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  25898         SOC_RESET_MASK_DEC(0x06780f0f, 0x00000000)
  25899         -1,
  25900         -1,
  25901     },
  25902 #endif /* chips */
  25903 
  25904 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25905     defined(BCM_88754_A0)
  25906     { /* SOC_REG_INT_BRDC_FMACH_GLOBAL_TEST_RX_IDL_PTRNr */
  25907         soc_block_list[93],
  25908         soc_genreg,
  25909         1,
  25910         0,
  25911         0x1d7,
  25912         SOC_REG_FLAG_ABOVE_64_BITS |
  25913                           SOC_REG_FLAG_WO,
  25914         0,
  25915         1,
  25916         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM83208_A0r_fields,
  25917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25918         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25919         -1,
  25920         -1,
  25921     },
  25922 #endif /* chips */
  25923 
  25924 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25925     defined(BCM_88754_A0)
  25926     { /* SOC_REG_INT_BRDC_FMACH_GLOBAL_TEST_TX_IDL_PTRNr */
  25927         soc_block_list[93],
  25928         soc_genreg,
  25929         1,
  25930         0,
  25931         0x1d4,
  25932         SOC_REG_FLAG_ABOVE_64_BITS |
  25933                           SOC_REG_FLAG_WO,
  25934         0,
  25935         1,
  25936         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM83208_A0r_fields,
  25937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  25938         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  25939         -1,
  25940         -1,
  25941     },
  25942 #endif /* chips */
  25943 
  25944 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25945     defined(BCM_88754_A0)
  25946     { /* SOC_REG_INT_BRDC_FMACH_GLOBAL_TEST_TX_PR_SEED_Ar */
  25947         soc_block_list[93],
  25948         soc_genreg,
  25949         1,
  25950         0,
  25951         0x1d0,
  25952         SOC_REG_FLAG_64_BITS |
  25953                           SOC_REG_FLAG_WO,
  25954         0,
  25955         1,
  25956         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM83208_A0r_fields,
  25957         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  25958         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  25959         -1,
  25960         -1,
  25961     },
  25962 #endif /* chips */
  25963 
  25964 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25965     defined(BCM_88754_A0)
  25966     { /* SOC_REG_INT_BRDC_FMACH_GLOBAL_TEST_TX_PR_SEED_Br */
  25967         soc_block_list[93],
  25968         soc_genreg,
  25969         1,
  25970         0,
  25971         0x1d2,
  25972         SOC_REG_FLAG_64_BITS |
  25973                           SOC_REG_FLAG_WO,
  25974         0,
  25975         1,
  25976         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM83208_A0r_fields,
  25977         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  25978         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  25979         -1,
  25980         -1,
  25981     },
  25982 #endif /* chips */
  25983 
  25984 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  25985     defined(BCM_88754_A0)
  25986     { /* SOC_REG_INT_BRDC_FMACH_GTIMER_CONFIGURATIONr */
  25987         soc_block_list[93],
  25988         soc_genreg,
  25989         1,
  25990         0,
  25991         0x56,
  25992         SOC_REG_FLAG_WO,
  25993         0,
  25994         3,
  25995         soc_BRDC_FMACH_GTIMER_CONFIGURATIONr_fields,
  25996         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  25997         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  25998         -1,
  25999         -1,
  26000     },
  26001 #endif /* chips */
  26002 
  26003 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26004     defined(BCM_88754_A0)
  26005     { /* SOC_REG_INT_BRDC_FMACH_GTIMER_TRIGGERr */
  26006         soc_block_list[93],
  26007         soc_genreg,
  26008         1,
  26009         0,
  26010         0x57,
  26011         SOC_REG_FLAG_WO,
  26012         0,
  26013         1,
  26014         soc_BRDC_FMACH_GTIMER_TRIGGERr_fields,
  26015         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26016         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26017         -1,
  26018         -1,
  26019     },
  26020 #endif /* chips */
  26021 
  26022 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26023     defined(BCM_88754_A0)
  26024     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTERr */
  26025         soc_block_list[93],
  26026         soc_genreg,
  26027         1,
  26028         0,
  26029         0x10,
  26030         SOC_REG_FLAG_WO,
  26031         0,
  26032         9,
  26033         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTERr_fields,
  26034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26035         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  26036         -1,
  26037         -1,
  26038     },
  26039 #endif /* chips */
  26040 
  26041 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26042     defined(BCM_88754_A0)
  26043     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_1r */
  26044         soc_block_list[93],
  26045         soc_genreg,
  26046         1,
  26047         0,
  26048         0x11,
  26049         SOC_REG_FLAG_WO,
  26050         0,
  26051         2,
  26052         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM83208_A0r_fields,
  26053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26054         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26055         -1,
  26056         -1,
  26057     },
  26058 #endif /* chips */
  26059 
  26060 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26061     defined(BCM_88754_A0)
  26062     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_2r */
  26063         soc_block_list[93],
  26064         soc_genreg,
  26065         1,
  26066         0,
  26067         0x12,
  26068         SOC_REG_FLAG_WO,
  26069         0,
  26070         2,
  26071         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM83208_A0r_fields,
  26072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26073         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26074         -1,
  26075         -1,
  26076     },
  26077 #endif /* chips */
  26078 
  26079 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26080     defined(BCM_88754_A0)
  26081     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_3r */
  26082         soc_block_list[93],
  26083         soc_genreg,
  26084         1,
  26085         0,
  26086         0x13,
  26087         SOC_REG_FLAG_WO,
  26088         0,
  26089         2,
  26090         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM83208_A0r_fields,
  26091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26092         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26093         -1,
  26094         -1,
  26095     },
  26096 #endif /* chips */
  26097 
  26098 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26099     defined(BCM_88754_A0)
  26100     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_4r */
  26101         soc_block_list[93],
  26102         soc_genreg,
  26103         1,
  26104         0,
  26105         0x14,
  26106         SOC_REG_FLAG_WO,
  26107         0,
  26108         2,
  26109         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM83208_A0r_fields,
  26110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26111         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26112         -1,
  26113         -1,
  26114     },
  26115 #endif /* chips */
  26116 
  26117 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26118     defined(BCM_88754_A0)
  26119     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_5r */
  26120         soc_block_list[93],
  26121         soc_genreg,
  26122         1,
  26123         0,
  26124         0x15,
  26125         SOC_REG_FLAG_WO,
  26126         0,
  26127         2,
  26128         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_5r_fields,
  26129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26130         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26131         -1,
  26132         -1,
  26133     },
  26134 #endif /* chips */
  26135 
  26136 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26137     defined(BCM_88754_A0)
  26138     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_6r */
  26139         soc_block_list[93],
  26140         soc_genreg,
  26141         1,
  26142         0,
  26143         0x16,
  26144         SOC_REG_FLAG_WO,
  26145         0,
  26146         1,
  26147         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_6r_fields,
  26148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26149         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  26150         -1,
  26151         -1,
  26152     },
  26153 #endif /* chips */
  26154 
  26155 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26156     defined(BCM_88754_A0)
  26157     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_7r */
  26158         soc_block_list[93],
  26159         soc_genreg,
  26160         1,
  26161         0,
  26162         0x17,
  26163         SOC_REG_FLAG_WO,
  26164         0,
  26165         1,
  26166         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_7r_fields,
  26167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26168         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  26169         -1,
  26170         -1,
  26171     },
  26172 #endif /* chips */
  26173 
  26174 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26175     defined(BCM_88754_A0)
  26176     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_8r */
  26177         soc_block_list[93],
  26178         soc_genreg,
  26179         1,
  26180         0,
  26181         0x18,
  26182         SOC_REG_FLAG_WO,
  26183         0,
  26184         3,
  26185         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_8r_fields,
  26186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26187         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  26188         -1,
  26189         -1,
  26190     },
  26191 #endif /* chips */
  26192 
  26193 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26194     defined(BCM_88754_A0)
  26195     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_MASK_REGISTER_9r */
  26196         soc_block_list[93],
  26197         soc_genreg,
  26198         1,
  26199         0,
  26200         0x19,
  26201         SOC_REG_FLAG_WO,
  26202         0,
  26203         2,
  26204         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_9r_fields,
  26205         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26206         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  26207         -1,
  26208         -1,
  26209     },
  26210 #endif /* chips */
  26211 
  26212 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26213     defined(BCM_88754_A0)
  26214     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTERr */
  26215         soc_block_list[93],
  26216         soc_genreg,
  26217         1,
  26218         0,
  26219         0,
  26220         SOC_REG_FLAG_WO |
  26221                           SOC_REG_FLAG_INTERRUPT,
  26222         0,
  26223         9,
  26224         soc_BRDC_FMACH_INTERRUPT_REGISTERr_fields,
  26225         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26226         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  26227         -1,
  26228         -1,
  26229     },
  26230 #endif /* chips */
  26231 
  26232 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26233     defined(BCM_88754_A0)
  26234     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_1r */
  26235         soc_block_list[93],
  26236         soc_genreg,
  26237         1,
  26238         0,
  26239         0x1,
  26240         SOC_REG_FLAG_WO |
  26241                           SOC_REG_FLAG_INTERRUPT,
  26242         0,
  26243         2,
  26244         soc_BRDC_FMACH_INTERRUPT_REGISTER_1r_fields,
  26245         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26246         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26247         -1,
  26248         -1,
  26249     },
  26250 #endif /* chips */
  26251 
  26252 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26253     defined(BCM_88754_A0)
  26254     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_2r */
  26255         soc_block_list[93],
  26256         soc_genreg,
  26257         1,
  26258         0,
  26259         0x2,
  26260         SOC_REG_FLAG_WO |
  26261                           SOC_REG_FLAG_INTERRUPT,
  26262         0,
  26263         2,
  26264         soc_BRDC_FMACH_INTERRUPT_REGISTER_2r_fields,
  26265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26266         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26267         -1,
  26268         -1,
  26269     },
  26270 #endif /* chips */
  26271 
  26272 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26273     defined(BCM_88754_A0)
  26274     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_3r */
  26275         soc_block_list[93],
  26276         soc_genreg,
  26277         1,
  26278         0,
  26279         0x3,
  26280         SOC_REG_FLAG_WO |
  26281                           SOC_REG_FLAG_INTERRUPT,
  26282         0,
  26283         2,
  26284         soc_BRDC_FMACH_INTERRUPT_REGISTER_3r_fields,
  26285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26286         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26287         -1,
  26288         -1,
  26289     },
  26290 #endif /* chips */
  26291 
  26292 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26293     defined(BCM_88754_A0)
  26294     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_4r */
  26295         soc_block_list[93],
  26296         soc_genreg,
  26297         1,
  26298         0,
  26299         0x4,
  26300         SOC_REG_FLAG_WO |
  26301                           SOC_REG_FLAG_INTERRUPT,
  26302         0,
  26303         2,
  26304         soc_BRDC_FMACH_INTERRUPT_REGISTER_4r_fields,
  26305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26306         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26307         -1,
  26308         -1,
  26309     },
  26310 #endif /* chips */
  26311 
  26312 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26313     defined(BCM_88754_A0)
  26314     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_5r */
  26315         soc_block_list[93],
  26316         soc_genreg,
  26317         1,
  26318         0,
  26319         0x5,
  26320         SOC_REG_FLAG_WO |
  26321                           SOC_REG_FLAG_INTERRUPT,
  26322         0,
  26323         2,
  26324         soc_BRDC_FMACH_INTERRUPT_REGISTER_5r_fields,
  26325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26326         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26327         -1,
  26328         -1,
  26329     },
  26330 #endif /* chips */
  26331 
  26332 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26333     defined(BCM_88754_A0)
  26334     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_6r */
  26335         soc_block_list[93],
  26336         soc_genreg,
  26337         1,
  26338         0,
  26339         0x6,
  26340         SOC_REG_FLAG_WO |
  26341                           SOC_REG_FLAG_INTERRUPT,
  26342         0,
  26343         1,
  26344         soc_BRDC_FMACH_INTERRUPT_REGISTER_6r_fields,
  26345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26346         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  26347         -1,
  26348         -1,
  26349     },
  26350 #endif /* chips */
  26351 
  26352 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26353     defined(BCM_88754_A0)
  26354     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_7r */
  26355         soc_block_list[93],
  26356         soc_genreg,
  26357         1,
  26358         0,
  26359         0x7,
  26360         SOC_REG_FLAG_WO |
  26361                           SOC_REG_FLAG_INTERRUPT,
  26362         0,
  26363         1,
  26364         soc_BRDC_FMACH_INTERRUPT_REGISTER_7r_fields,
  26365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26366         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  26367         -1,
  26368         -1,
  26369     },
  26370 #endif /* chips */
  26371 
  26372 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26373     defined(BCM_88754_A0)
  26374     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_8r */
  26375         soc_block_list[93],
  26376         soc_genreg,
  26377         1,
  26378         0,
  26379         0x8,
  26380         SOC_REG_FLAG_WO |
  26381                           SOC_REG_FLAG_INTERRUPT,
  26382         0,
  26383         3,
  26384         soc_BRDC_FMACH_INTERRUPT_REGISTER_8r_fields,
  26385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26386         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  26387         -1,
  26388         -1,
  26389     },
  26390 #endif /* chips */
  26391 
  26392 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26393     defined(BCM_88754_A0)
  26394     { /* SOC_REG_INT_BRDC_FMACH_INTERRUPT_REGISTER_9r */
  26395         soc_block_list[93],
  26396         soc_genreg,
  26397         1,
  26398         0,
  26399         0x9,
  26400         SOC_REG_FLAG_WO |
  26401                           SOC_REG_FLAG_INTERRUPT,
  26402         0,
  26403         2,
  26404         soc_BRDC_FMACH_INTERRUPT_REGISTER_9r_fields,
  26405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26406         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  26407         -1,
  26408         -1,
  26409     },
  26410 #endif /* chips */
  26411 
  26412 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26413     defined(BCM_88754_A0)
  26414     { /* SOC_REG_INT_BRDC_FMACH_KPCS_CONFIGURATIONr */
  26415         soc_block_list[93],
  26416         soc_genreg,
  26417         4,
  26418         0,
  26419         0x160,
  26420         SOC_REG_FLAG_ARRAY |
  26421                           SOC_REG_FLAG_WO |
  26422                           SOC_REG_FLAG_REG_ARRAY,
  26423         0,
  26424         10,
  26425         soc_BRDC_FMACH_KPCS_CONFIGURATIONr_fields,
  26426         SOC_RESET_VAL_DEC(0x001f000f, 0x00000000)
  26427         SOC_RESET_MASK_DEC(0x003f000f, 0x00000000)
  26428         -1,
  26429         -1,
  26430     },
  26431 #endif /* chips */
  26432 
  26433 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26434     defined(BCM_88754_A0)
  26435     { /* SOC_REG_INT_BRDC_FMACH_KPCS_RX_STATUSr */
  26436         soc_block_list[93],
  26437         soc_genreg,
  26438         4,
  26439         0,
  26440         0x164,
  26441         SOC_REG_FLAG_ARRAY |
  26442                           SOC_REG_FLAG_RO |
  26443                           SOC_REG_FLAG_WO |
  26444                           SOC_REG_FLAG_REG_ARRAY,
  26445         0,
  26446         2,
  26447         soc_BRDC_FMACH_KPCS_RX_STATUSr_fields,
  26448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26449         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  26450         -1,
  26451         -1,
  26452     },
  26453 #endif /* chips */
  26454 
  26455 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26456     defined(BCM_88754_A0)
  26457     { /* SOC_REG_INT_BRDC_FMACH_KPCS_TEST_RX_CONFIGURATIONr */
  26458         soc_block_list[93],
  26459         soc_genreg,
  26460         4,
  26461         0,
  26462         0x180,
  26463         SOC_REG_FLAG_ARRAY |
  26464                           SOC_REG_FLAG_WO |
  26465                           SOC_REG_FLAG_REG_ARRAY,
  26466         0,
  26467         4,
  26468         soc_BRDC_FMACH_KPCS_TEST_RX_CONFIGURATIONr_fields,
  26469         SOC_RESET_VAL_DEC(0x000007f2, 0x00000000)
  26470         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  26471         -1,
  26472         -1,
  26473     },
  26474 #endif /* chips */
  26475 
  26476 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26477     defined(BCM_88754_A0)
  26478     { /* SOC_REG_INT_BRDC_FMACH_KPCS_TEST_RX_STATUSr */
  26479         soc_block_list[93],
  26480         soc_genreg,
  26481         4,
  26482         0,
  26483         0x190,
  26484         SOC_REG_FLAG_ARRAY |
  26485                           SOC_REG_FLAG_RO |
  26486                           SOC_REG_FLAG_WO |
  26487                           SOC_REG_FLAG_REG_ARRAY,
  26488         0,
  26489         1,
  26490         soc_BRDC_FMACH_KPCS_TEST_RX_STATUSr_fields,
  26491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26492         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26493         -1,
  26494         -1,
  26495     },
  26496 #endif /* chips */
  26497 
  26498 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26499     defined(BCM_88754_A0)
  26500     { /* SOC_REG_INT_BRDC_FMACH_KPCS_TEST_TX_CONFIGURATIONr */
  26501         soc_block_list[93],
  26502         soc_genreg,
  26503         4,
  26504         0,
  26505         0x170,
  26506         SOC_REG_FLAG_ARRAY |
  26507                           SOC_REG_FLAG_WO |
  26508                           SOC_REG_FLAG_REG_ARRAY,
  26509         0,
  26510         7,
  26511         soc_BRDC_FMACH_KPCS_TEST_TX_CONFIGURATIONr_fields,
  26512         SOC_RESET_VAL_DEC(0x00401fc2, 0x00000000)
  26513         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  26514         -1,
  26515         -1,
  26516     },
  26517 #endif /* chips */
  26518 
  26519 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26520     defined(BCM_88754_A0)
  26521     { /* SOC_REG_INT_BRDC_FMACH_LEAKY_BUCKETr */
  26522         soc_block_list[93],
  26523         soc_genreg,
  26524         4,
  26525         0,
  26526         0x70,
  26527         SOC_REG_FLAG_ARRAY |
  26528                           SOC_REG_FLAG_RO |
  26529                           SOC_REG_FLAG_WO |
  26530                           SOC_REG_FLAG_REG_ARRAY,
  26531         0,
  26532         2,
  26533         soc_BRDC_FMACH_LEAKY_BUCKETr_fields,
  26534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26535         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  26536         -1,
  26537         -1,
  26538     },
  26539 #endif /* chips */
  26540 
  26541 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26542     defined(BCM_88754_A0)
  26543     { /* SOC_REG_INT_BRDC_FMACH_LEAKY_BUCKET_CONTROL_REGISTERr */
  26544         soc_block_list[93],
  26545         soc_genreg,
  26546         1,
  26547         0,
  26548         0x61,
  26549         SOC_REG_FLAG_WO,
  26550         0,
  26551         6,
  26552         soc_BRDC_FMACH_LEAKY_BUCKET_CONTROL_REGISTERr_fields,
  26553         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  26554         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  26555         -1,
  26556         -1,
  26557     },
  26558 #endif /* chips */
  26559 
  26560 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26561     defined(BCM_88754_A0)
  26562     { /* SOC_REG_INT_BRDC_FMACH_LFEC_CONFIGURATIONr */
  26563         soc_block_list[93],
  26564         soc_genreg,
  26565         4,
  26566         0,
  26567         0xe0,
  26568         SOC_REG_FLAG_ARRAY |
  26569                           SOC_REG_FLAG_WO |
  26570                           SOC_REG_FLAG_REG_ARRAY,
  26571         0,
  26572         10,
  26573         soc_BRDC_FMACH_LFEC_CONFIGURATIONr_fields,
  26574         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  26575         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  26576         -1,
  26577         -1,
  26578     },
  26579 #endif /* chips */
  26580 
  26581 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26582     defined(BCM_88754_A0)
  26583     { /* SOC_REG_INT_BRDC_FMACH_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr */
  26584         soc_block_list[93],
  26585         soc_genreg,
  26586         1,
  26587         0,
  26588         0x64,
  26589         SOC_REG_FLAG_WO,
  26590         0,
  26591         4,
  26592         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM83208_A0r_fields,
  26593         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  26594         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  26595         -1,
  26596         -1,
  26597     },
  26598 #endif /* chips */
  26599 
  26600 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26601     defined(BCM_88754_A0)
  26602     { /* SOC_REG_INT_BRDC_FMACH_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr */
  26603         soc_block_list[93],
  26604         soc_genreg,
  26605         1,
  26606         0,
  26607         0x21,
  26608         SOC_REG_FLAG_WO,
  26609         0,
  26610         2,
  26611         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM83208_A0r_fields,
  26612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26613         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26614         -1,
  26615         -1,
  26616     },
  26617 #endif /* chips */
  26618 
  26619 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  26620     { /* SOC_REG_INT_BRDC_FMACH_LOOPBACK_ENABLE_REGISTERr */
  26621         soc_block_list[93],
  26622         soc_genreg,
  26623         1,
  26624         0,
  26625         0x20,
  26626         SOC_REG_FLAG_WO,
  26627         0,
  26628         1,
  26629         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM83208_A0r_fields,
  26630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26631         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  26632         -1,
  26633         -1,
  26634     },
  26635 #endif /* chips */
  26636 
  26637 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26638     defined(BCM_88754_A0)
  26639     { /* SOC_REG_INT_BRDC_FMACH_RECEIVE_RESET_REGISTERr */
  26640         soc_block_list[93],
  26641         soc_genreg,
  26642         1,
  26643         0,
  26644         0x63,
  26645         SOC_REG_FLAG_WO,
  26646         0,
  26647         2,
  26648         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM83208_A0r_fields,
  26649         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  26650         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  26651         -1,
  26652         -1,
  26653     },
  26654 #endif /* chips */
  26655 
  26656 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26657     defined(BCM_88754_A0)
  26658     { /* SOC_REG_INT_BRDC_FMACH_REG_0050r */
  26659         soc_block_list[93],
  26660         soc_genreg,
  26661         1,
  26662         0,
  26663         0x50,
  26664         SOC_REG_FLAG_WO,
  26665         0,
  26666         1,
  26667         soc_ECI_REG_0050r_fields,
  26668         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  26669         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26670         -1,
  26671         -1,
  26672     },
  26673 #endif /* chips */
  26674 
  26675 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26676     defined(BCM_88754_A0)
  26677     { /* SOC_REG_INT_BRDC_FMACH_REG_0051r */
  26678         soc_block_list[93],
  26679         soc_genreg,
  26680         1,
  26681         0,
  26682         0x51,
  26683         SOC_REG_FLAG_WO,
  26684         0,
  26685         1,
  26686         soc_ECI_REG_0051r_fields,
  26687         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  26688         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26689         -1,
  26690         -1,
  26691     },
  26692 #endif /* chips */
  26693 
  26694 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26695     defined(BCM_88754_A0)
  26696     { /* SOC_REG_INT_BRDC_FMACH_REG_0052r */
  26697         soc_block_list[93],
  26698         soc_genreg,
  26699         1,
  26700         0,
  26701         0x52,
  26702         SOC_REG_FLAG_WO,
  26703         0,
  26704         1,
  26705         soc_ECI_REG_0052r_fields,
  26706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26708         -1,
  26709         -1,
  26710     },
  26711 #endif /* chips */
  26712 
  26713 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26714     defined(BCM_88754_A0)
  26715     { /* SOC_REG_INT_BRDC_FMACH_REG_0054r */
  26716         soc_block_list[93],
  26717         soc_genreg,
  26718         1,
  26719         0,
  26720         0x54,
  26721         SOC_REG_FLAG_WO,
  26722         0,
  26723         2,
  26724         soc_DRCBROADCAST_REG_0085_BCM83207_A0r_fields,
  26725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26726         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  26727         -1,
  26728         -1,
  26729     },
  26730 #endif /* chips */
  26731 
  26732 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26733     defined(BCM_88754_A0)
  26734     { /* SOC_REG_INT_BRDC_FMACH_REG_0065r */
  26735         soc_block_list[93],
  26736         soc_genreg,
  26737         1,
  26738         0,
  26739         0x65,
  26740         SOC_REG_FLAG_WO,
  26741         0,
  26742         2,
  26743         soc_BRDC_FMACH_REG_0065r_fields,
  26744         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  26745         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26746         -1,
  26747         -1,
  26748     },
  26749 #endif /* chips */
  26750 
  26751 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26752     defined(BCM_88754_A0)
  26753     { /* SOC_REG_INT_BRDC_FMACH_REG_0066r */
  26754         soc_block_list[93],
  26755         soc_genreg,
  26756         1,
  26757         0,
  26758         0x66,
  26759         SOC_REG_FLAG_WO,
  26760         0,
  26761         1,
  26762         soc_BRDC_FMAC_REG_0102_BCM83208_A0r_fields,
  26763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26764         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  26765         -1,
  26766         -1,
  26767     },
  26768 #endif /* chips */
  26769 
  26770 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26771     defined(BCM_88754_A0)
  26772     { /* SOC_REG_INT_BRDC_FMACH_REG_0096r */
  26773         soc_block_list[93],
  26774         soc_genreg,
  26775         1,
  26776         0,
  26777         0x96,
  26778         SOC_REG_FLAG_64_BITS |
  26779                           SOC_REG_FLAG_WO,
  26780         0,
  26781         1,
  26782         soc_BRDC_FMACH_REG_0096r_fields,
  26783         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  26784         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  26785         -1,
  26786         -1,
  26787     },
  26788 #endif /* chips */
  26789 
  26790 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26791     defined(BCM_88754_A0)
  26792     { /* SOC_REG_INT_BRDC_FMACH_REG_0098r */
  26793         soc_block_list[93],
  26794         soc_genreg,
  26795         1,
  26796         0,
  26797         0x98,
  26798         SOC_REG_FLAG_WO,
  26799         0,
  26800         8,
  26801         soc_BRDC_FMACH_REG_0098r_fields,
  26802         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  26803         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  26804         -1,
  26805         -1,
  26806     },
  26807 #endif /* chips */
  26808 
  26809 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26810     defined(BCM_88754_A0)
  26811     { /* SOC_REG_INT_BRDC_FMACH_REG_0099r */
  26812         soc_block_list[93],
  26813         soc_genreg,
  26814         1,
  26815         0,
  26816         0x99,
  26817         SOC_REG_FLAG_WO,
  26818         0,
  26819         1,
  26820         soc_BRDC_FMACH_REG_0099r_fields,
  26821         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  26822         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  26823         -1,
  26824         -1,
  26825     },
  26826 #endif /* chips */
  26827 
  26828 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26829     defined(BCM_88754_A0)
  26830     { /* SOC_REG_INT_BRDC_FMACH_REG_0140r */
  26831         soc_block_list[93],
  26832         soc_genreg,
  26833         4,
  26834         0,
  26835         0x140,
  26836         SOC_REG_FLAG_64_BITS |
  26837                           SOC_REG_FLAG_ARRAY |
  26838                           SOC_REG_FLAG_WO |
  26839                           SOC_REG_FLAG_REG_ARRAY |
  26840                           SOC_REG_FLAG_SIGNAL,
  26841         0,
  26842         2,
  26843         soc_BRDC_FMACH_REG_0140r_fields,
  26844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  26846         -1,
  26847         -1,
  26848     },
  26849 #endif /* chips */
  26850 
  26851 #if defined(BCM_88750_A0) || defined(BCM_88754_A0)
  26852     { /* SOC_REG_INT_BRDC_FMACH_REG_005Ar */
  26853         soc_block_list[93],
  26854         soc_genreg,
  26855         1,
  26856         0,
  26857         0x5a,
  26858         SOC_REG_FLAG_WO,
  26859         0,
  26860         6,
  26861         soc_BRDC_FMACH_REG_005Ar_fields,
  26862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26863         SOC_RESET_MASK_DEC(0x0000074b, 0x00000000)
  26864         -1,
  26865         -1,
  26866     },
  26867 #endif /* chips */
  26868 
  26869 #if defined(BCM_88750_B0)
  26870     { /* SOC_REG_INT_BRDC_FMACH_REG_005A_BCM88750_B0r */
  26871         soc_block_list[93],
  26872         soc_genreg,
  26873         1,
  26874         0,
  26875         0x5a,
  26876         SOC_REG_FLAG_WO,
  26877         0,
  26878         6,
  26879         soc_BRDC_FMACH_REG_005A_BCM88750_B0r_fields,
  26880         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  26881         SOC_RESET_MASK_DEC(0x0000074b, 0x00000000)
  26882         -1,
  26883         -1,
  26884     },
  26885 #endif /* chips */
  26886 
  26887 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26888     defined(BCM_88754_A0)
  26889     { /* SOC_REG_INT_BRDC_FMACH_REG_005Br */
  26890         soc_block_list[93],
  26891         soc_genreg,
  26892         1,
  26893         0,
  26894         0x5b,
  26895         SOC_REG_FLAG_WO,
  26896         0,
  26897         1,
  26898         soc_BRDC_FMACH_REG_005Br_fields,
  26899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26900         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26901         -1,
  26902         -1,
  26903     },
  26904 #endif /* chips */
  26905 
  26906 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26907     defined(BCM_88754_A0)
  26908     { /* SOC_REG_INT_BRDC_FMACH_REG_01A8r */
  26909         soc_block_list[93],
  26910         soc_genreg,
  26911         4,
  26912         0,
  26913         0x1a8,
  26914         SOC_REG_FLAG_ARRAY |
  26915                           SOC_REG_FLAG_WO |
  26916                           SOC_REG_FLAG_REG_ARRAY,
  26917         0,
  26918         1,
  26919         soc_BRDC_FMACH_REG_01A8r_fields,
  26920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26921         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26922         -1,
  26923         -1,
  26924     },
  26925 #endif /* chips */
  26926 
  26927 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  26928     defined(BCM_88754_A0)
  26929     { /* SOC_REG_INT_BRDC_FMACH_REG_01ACr */
  26930         soc_block_list[93],
  26931         soc_genreg,
  26932         4,
  26933         0,
  26934         0x1ac,
  26935         SOC_REG_FLAG_ARRAY |
  26936                           SOC_REG_FLAG_WO |
  26937                           SOC_REG_FLAG_REG_ARRAY,
  26938         0,
  26939         3,
  26940         soc_BRDC_FMACH_REG_01ACr_fields,
  26941         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  26942         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  26943         -1,
  26944         -1,
  26945     },
  26946 #endif /* chips */
  26947 
  26948 #if defined(BCM_88754_A0)
  26949     { /* SOC_REG_INT_BRDC_FMACH_REG_01E9r */
  26950         soc_block_list[93],
  26951         soc_genreg,
  26952         1,
  26953         0,
  26954         0x1e9,
  26955         SOC_REG_FLAG_RO |
  26956                           SOC_REG_FLAG_WO,
  26957         0,
  26958         3,
  26959         soc_BRDC_FMACH_REG_01E9r_fields,
  26960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26961         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  26962         -1,
  26963         -1,
  26964     },
  26965 #endif /* chips */
  26966 
  26967 #if defined(BCM_88754_A0)
  26968     { /* SOC_REG_INT_BRDC_FMACH_REG_01EAr */
  26969         soc_block_list[93],
  26970         soc_genreg,
  26971         1,
  26972         0,
  26973         0x1ea,
  26974         SOC_REG_FLAG_WO,
  26975         0,
  26976         1,
  26977         soc_DRCBROADCAST_REG_00B2_BCM83207_A0r_fields,
  26978         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26979         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  26980         -1,
  26981         -1,
  26982     },
  26983 #endif /* chips */
  26984 
  26985 #if defined(BCM_88754_A0)
  26986     { /* SOC_REG_INT_BRDC_FMACH_REG_01EBr */
  26987         soc_block_list[93],
  26988         soc_genreg,
  26989         1,
  26990         0,
  26991         0x1eb,
  26992         SOC_REG_FLAG_RO |
  26993                           SOC_REG_FLAG_WO,
  26994         0,
  26995         1,
  26996         soc_BRDC_FMACH_REG_01EBr_fields,
  26997         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  26998         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  26999         -1,
  27000         -1,
  27001     },
  27002 #endif /* chips */
  27003 
  27004 #if defined(BCM_88754_A0)
  27005     { /* SOC_REG_INT_BRDC_FMACH_REG_01ECr */
  27006         soc_block_list[93],
  27007         soc_genreg,
  27008         1,
  27009         0,
  27010         0x1ec,
  27011         SOC_REG_FLAG_RO |
  27012                           SOC_REG_FLAG_WO,
  27013         0,
  27014         1,
  27015         soc_BRDC_FMACH_REG_01ECr_fields,
  27016         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  27017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27018         -1,
  27019         -1,
  27020     },
  27021 #endif /* chips */
  27022 
  27023 #if defined(BCM_88754_A0)
  27024     { /* SOC_REG_INT_BRDC_FMACH_REG_01EDr */
  27025         soc_block_list[93],
  27026         soc_genreg,
  27027         1,
  27028         0,
  27029         0x1ed,
  27030         SOC_REG_FLAG_RO |
  27031                           SOC_REG_FLAG_WO,
  27032         0,
  27033         3,
  27034         soc_BRDC_FMACH_REG_01E9r_fields,
  27035         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27036         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27037         -1,
  27038         -1,
  27039     },
  27040 #endif /* chips */
  27041 
  27042 #if defined(BCM_88754_A0)
  27043     { /* SOC_REG_INT_BRDC_FMACH_REG_01EEr */
  27044         soc_block_list[93],
  27045         soc_genreg,
  27046         1,
  27047         0,
  27048         0x1ee,
  27049         SOC_REG_FLAG_WO,
  27050         0,
  27051         1,
  27052         soc_DRCBROADCAST_REG_00B2_BCM83207_A0r_fields,
  27053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27054         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  27055         -1,
  27056         -1,
  27057     },
  27058 #endif /* chips */
  27059 
  27060 #if defined(BCM_88754_A0)
  27061     { /* SOC_REG_INT_BRDC_FMACH_REG_01EFr */
  27062         soc_block_list[93],
  27063         soc_genreg,
  27064         1,
  27065         0,
  27066         0x1ef,
  27067         SOC_REG_FLAG_RO |
  27068                           SOC_REG_FLAG_WO,
  27069         0,
  27070         1,
  27071         soc_BRDC_FMACH_REG_01EBr_fields,
  27072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27073         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  27074         -1,
  27075         -1,
  27076     },
  27077 #endif /* chips */
  27078 
  27079 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27080     defined(BCM_88754_A0)
  27081     { /* SOC_REG_INT_BRDC_FMACH_REG_01FAr */
  27082         soc_block_list[93],
  27083         soc_genreg,
  27084         1,
  27085         0,
  27086         0x1fa,
  27087         SOC_REG_FLAG_WO,
  27088         0,
  27089         6,
  27090         soc_BRDC_FMACH_REG_01FAr_fields,
  27091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27092         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  27093         -1,
  27094         -1,
  27095     },
  27096 #endif /* chips */
  27097 
  27098 #if defined(BCM_88754_A0)
  27099     { /* SOC_REG_INT_BRDC_FMACH_REG_1E8r */
  27100         soc_block_list[93],
  27101         soc_genreg,
  27102         1,
  27103         0,
  27104         0x1e8,
  27105         SOC_REG_FLAG_RO |
  27106                           SOC_REG_FLAG_WO,
  27107         0,
  27108         1,
  27109         soc_BRDC_FMACH_REG_01ECr_fields,
  27110         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  27111         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27112         -1,
  27113         -1,
  27114     },
  27115 #endif /* chips */
  27116 
  27117 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27118     defined(BCM_88754_A0)
  27119     { /* SOC_REG_INT_BRDC_FMACH_SBUS_BROADCAST_IDr */
  27120         soc_block_list[93],
  27121         soc_genreg,
  27122         1,
  27123         0,
  27124         0x55,
  27125         SOC_REG_FLAG_WO,
  27126         0,
  27127         1,
  27128         soc_BRDC_FMACH_SBUS_BROADCAST_IDr_fields,
  27129         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27130         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27131         -1,
  27132         -1,
  27133     },
  27134 #endif /* chips */
  27135 
  27136 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27137     defined(BCM_88754_A0)
  27138     { /* SOC_REG_INT_BRDC_FMACH_SBUS_LAST_IN_CHAINr */
  27139         soc_block_list[93],
  27140         soc_genreg,
  27141         1,
  27142         0,
  27143         0x58,
  27144         SOC_REG_FLAG_WO,
  27145         0,
  27146         1,
  27147         soc_ECI_SBUS_LAST_IN_CHAIN_BCM83207_A0r_fields,
  27148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27149         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  27150         -1,
  27151         -1,
  27152     },
  27153 #endif /* chips */
  27154 
  27155 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27156     defined(BCM_88754_A0)
  27157     { /* SOC_REG_INT_BRDC_FMACH_SPARE_REGISTER_3r */
  27158         soc_block_list[93],
  27159         soc_genreg,
  27160         1,
  27161         0,
  27162         0x53,
  27163         SOC_REG_FLAG_WO,
  27164         0,
  27165         2,
  27166         soc_BRDC_FMACH_SPARE_REGISTER_3r_fields,
  27167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27168         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27169         -1,
  27170         -1,
  27171     },
  27172 #endif /* chips */
  27173 
  27174 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27175     defined(BCM_88754_A0)
  27176     { /* SOC_REG_INT_BRDC_FMACH_TEST_CONFIGURATIONr */
  27177         soc_block_list[93],
  27178         soc_genreg,
  27179         4,
  27180         0,
  27181         0x1b0,
  27182         SOC_REG_FLAG_ARRAY |
  27183                           SOC_REG_FLAG_WO |
  27184                           SOC_REG_FLAG_REG_ARRAY,
  27185         0,
  27186         4,
  27187         soc_BRDC_FMACH_TEST_CONFIGURATIONr_fields,
  27188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27189         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  27190         -1,
  27191         -1,
  27192     },
  27193 #endif /* chips */
  27194 
  27195 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27196     defined(BCM_88754_A0)
  27197     { /* SOC_REG_INT_BRDC_FMACH_TEST_STATUSr */
  27198         soc_block_list[93],
  27199         soc_genreg,
  27200         4,
  27201         0,
  27202         0x1b4,
  27203         SOC_REG_FLAG_ARRAY |
  27204                           SOC_REG_FLAG_RO |
  27205                           SOC_REG_FLAG_WO |
  27206                           SOC_REG_FLAG_REG_ARRAY,
  27207         0,
  27208         3,
  27209         soc_BRDC_FMACH_TEST_STATUSr_fields,
  27210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27211         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27212         -1,
  27213         -1,
  27214     },
  27215 #endif /* chips */
  27216 
  27217 #if defined(BCM_88750_A0)
  27218     { /* SOC_REG_INT_BRDC_FMACH_TX_CELL_LIMITr */
  27219         soc_block_list[93],
  27220         soc_genreg,
  27221         1,
  27222         0,
  27223         0x67,
  27224         SOC_REG_FLAG_WO,
  27225         0,
  27226         2,
  27227         soc_BRDC_FMACH_TX_CELL_LIMITr_fields,
  27228         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  27229         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27230         -1,
  27231         -1,
  27232     },
  27233 #endif /* chips */
  27234 
  27235 #if defined(BCM_88750_B0) || defined(BCM_88754_A0)
  27236     { /* SOC_REG_INT_BRDC_FMACH_TX_CELL_LIMIT_BCM88750_B0r */
  27237         soc_block_list[93],
  27238         soc_genreg,
  27239         1,
  27240         0,
  27241         0x67,
  27242         SOC_REG_FLAG_WO,
  27243         0,
  27244         2,
  27245         soc_BRDC_FMACH_TX_CELL_LIMIT_BCM88750_B0r_fields,
  27246         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  27247         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27248         -1,
  27249         -1,
  27250     },
  27251 #endif /* chips */
  27252 
  27253 #if defined(BCM_88754_A0)
  27254     { /* SOC_REG_INT_BRDC_FMACL_ASYNC_FIFO_ACCESS_READ_DATAr */
  27255         soc_block_list[91],
  27256         soc_genreg,
  27257         1,
  27258         0,
  27259         0xb2,
  27260         SOC_REG_FLAG_RO |
  27261                           SOC_REG_FLAG_WO,
  27262         0,
  27263         5,
  27264         soc_BRDC_FMACH_ASYNC_FIFO_ACCESS_READ_DATAr_fields,
  27265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27266         SOC_RESET_MASK_DEC(0x80ff1f1f, 0x00000000)
  27267         -1,
  27268         -1,
  27269     },
  27270 #endif /* chips */
  27271 
  27272 #if defined(BCM_88754_A0)
  27273     { /* SOC_REG_INT_BRDC_FMACL_ASYNC_FIFO_ACCESS_TRIGGERr */
  27274         soc_block_list[91],
  27275         soc_genreg,
  27276         1,
  27277         0,
  27278         0xb1,
  27279         SOC_REG_FLAG_WO,
  27280         0,
  27281         1,
  27282         soc_BRDC_FMACH_ASYNC_FIFO_ACCESS_TRIGGERr_fields,
  27283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27284         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  27285         -1,
  27286         -1,
  27287     },
  27288 #endif /* chips */
  27289 
  27290 #if defined(BCM_88750_A0)
  27291     { /* SOC_REG_INT_BRDC_FMACL_ASYNC_FIFO_CONFIGURATIONr */
  27292         soc_block_list[91],
  27293         soc_genreg,
  27294         4,
  27295         0,
  27296         0xb0,
  27297         SOC_REG_FLAG_64_BITS |
  27298                           SOC_REG_FLAG_ARRAY |
  27299                           SOC_REG_FLAG_WO |
  27300                           SOC_REG_FLAG_REG_ARRAY,
  27301         0,
  27302         14,
  27303         soc_BRDC_FMACH_ASYNC_FIFO_CONFIGURATIONr_fields,
  27304         SOC_RESET_VAL_DEC(0x002a01d5, 0x00000000)
  27305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  27306         -1,
  27307         -1,
  27308     },
  27309 #endif /* chips */
  27310 
  27311 #if defined(BCM_88750_B0)
  27312     { /* SOC_REG_INT_BRDC_FMACL_ASYNC_FIFO_CONFIGURATION_BCM88750_B0r */
  27313         soc_block_list[91],
  27314         soc_genreg,
  27315         4,
  27316         0,
  27317         0xb0,
  27318         SOC_REG_FLAG_64_BITS |
  27319                           SOC_REG_FLAG_ARRAY |
  27320                           SOC_REG_FLAG_WO |
  27321                           SOC_REG_FLAG_REG_ARRAY,
  27322         0,
  27323         16,
  27324         soc_BRDC_FMACH_ASYNC_FIFO_CONFIGURATION_BCM88750_B0r_fields,
  27325         SOC_RESET_VAL_DEC(0x045403d5, 0x00000000)
  27326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  27327         -1,
  27328         -1,
  27329     },
  27330 #endif /* chips */
  27331 
  27332 #if defined(BCM_88754_A0)
  27333     { /* SOC_REG_INT_BRDC_FMACL_ASYNC_FIFO_CONFIGURATION_BCM88754_A0r */
  27334         soc_block_list[91],
  27335         soc_genreg,
  27336         1,
  27337         0,
  27338         0xb0,
  27339         SOC_REG_FLAG_WO |
  27340                           SOC_REG_FLAG_SIGNAL,
  27341         0,
  27342         19,
  27343         soc_BRDC_FMACH_ASYNC_FIFO_CONFIGURATION_BCM88754_A0r_fields,
  27344         SOC_RESET_VAL_DEC(0x00b4a550, 0x00000000)
  27345         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  27346         -1,
  27347         -1,
  27348     },
  27349 #endif /* chips */
  27350 
  27351 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27352     defined(BCM_88754_A0)
  27353     { /* SOC_REG_INT_BRDC_FMACL_BEC_CONFIGURATIONr */
  27354         soc_block_list[91],
  27355         soc_genreg,
  27356         4,
  27357         0,
  27358         0x1a0,
  27359         SOC_REG_FLAG_ARRAY |
  27360                           SOC_REG_FLAG_WO |
  27361                           SOC_REG_FLAG_REG_ARRAY,
  27362         0,
  27363         7,
  27364         soc_BRDC_FMACH_BEC_CONFIGURATIONr_fields,
  27365         SOC_RESET_VAL_DEC(0xf1015084, 0x00000000)
  27366         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27367         -1,
  27368         -1,
  27369     },
  27370 #endif /* chips */
  27371 
  27372 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27373     defined(BCM_88754_A0)
  27374     { /* SOC_REG_INT_BRDC_FMACL_BEC_STATUSr */
  27375         soc_block_list[91],
  27376         soc_genreg,
  27377         4,
  27378         0,
  27379         0x1a4,
  27380         SOC_REG_FLAG_ARRAY |
  27381                           SOC_REG_FLAG_RO |
  27382                           SOC_REG_FLAG_WO |
  27383                           SOC_REG_FLAG_REG_ARRAY,
  27384         0,
  27385         9,
  27386         soc_BRDC_FMACH_BEC_STATUSr_fields,
  27387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27388         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  27389         -1,
  27390         -1,
  27391     },
  27392 #endif /* chips */
  27393 
  27394 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27395     defined(BCM_88754_A0)
  27396     { /* SOC_REG_INT_BRDC_FMACL_BER_GEN_BITMAPr */
  27397         soc_block_list[91],
  27398         soc_genreg,
  27399         1,
  27400         0,
  27401         0x9b,
  27402         SOC_REG_FLAG_64_BITS |
  27403                           SOC_REG_FLAG_WO,
  27404         0,
  27405         1,
  27406         soc_BRDC_FMACH_BER_GEN_BITMAPr_fields,
  27407         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  27408         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  27409         -1,
  27410         -1,
  27411     },
  27412 #endif /* chips */
  27413 
  27414 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27415     defined(BCM_88754_A0)
  27416     { /* SOC_REG_INT_BRDC_FMACL_BER_GEN_PERIODr */
  27417         soc_block_list[91],
  27418         soc_genreg,
  27419         1,
  27420         0,
  27421         0x9a,
  27422         SOC_REG_FLAG_WO,
  27423         0,
  27424         1,
  27425         soc_FMAC_BER_GEN_PERIOD_BCM83208_A0r_fields,
  27426         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  27427         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27428         -1,
  27429         -1,
  27430     },
  27431 #endif /* chips */
  27432 
  27433 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27434     defined(BCM_88754_A0)
  27435     { /* SOC_REG_INT_BRDC_FMACL_CNTRL_INTRLVD_MODE_REGr */
  27436         soc_block_list[91],
  27437         soc_genreg,
  27438         1,
  27439         0,
  27440         0x22,
  27441         SOC_REG_FLAG_WO,
  27442         0,
  27443         1,
  27444         soc_BRDC_FMACH_CNTRL_INTRLVD_MODE_REGr_fields,
  27445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27446         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  27447         -1,
  27448         -1,
  27449     },
  27450 #endif /* chips */
  27451 
  27452 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27453     defined(BCM_88754_A0)
  27454     { /* SOC_REG_INT_BRDC_FMACL_CONTROL_CELL_BURST_REGISTERr */
  27455         soc_block_list[91],
  27456         soc_genreg,
  27457         1,
  27458         0,
  27459         0x62,
  27460         SOC_REG_FLAG_WO,
  27461         0,
  27462         3,
  27463         soc_BRDC_FMACH_CONTROL_CELL_BURST_REGISTERr_fields,
  27464         SOC_RESET_VAL_DEC(0x0001c008, 0x00000000)
  27465         SOC_RESET_MASK_DEC(0x000ff3ff, 0x00000000)
  27466         -1,
  27467         -1,
  27468     },
  27469 #endif /* chips */
  27470 
  27471 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27472     defined(BCM_88754_A0)
  27473     { /* SOC_REG_INT_BRDC_FMACL_ECC_1B_ERR_ADDRr */
  27474         soc_block_list[91],
  27475         soc_genreg,
  27476         1,
  27477         0,
  27478         0x1e1,
  27479         SOC_REG_FLAG_RO |
  27480                           SOC_REG_FLAG_WO,
  27481         0,
  27482         2,
  27483         soc_BRDC_FMACH_ECC_1B_ERR_ADDRr_fields,
  27484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27485         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27486         -1,
  27487         -1,
  27488     },
  27489 #endif /* chips */
  27490 
  27491 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27492     defined(BCM_88754_A0)
  27493     { /* SOC_REG_INT_BRDC_FMACL_ECC_1B_ERR_CNTr */
  27494         soc_block_list[91],
  27495         soc_genreg,
  27496         1,
  27497         0,
  27498         0x1dd,
  27499         SOC_REG_FLAG_RO |
  27500                           SOC_REG_FLAG_WO,
  27501         0,
  27502         2,
  27503         soc_BRDC_FMACH_ECC_1B_ERR_CNTr_fields,
  27504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27505         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27506         -1,
  27507         -1,
  27508     },
  27509 #endif /* chips */
  27510 
  27511 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27512     defined(BCM_88754_A0)
  27513     { /* SOC_REG_INT_BRDC_FMACL_ECC_1B_ERR_MONITOR_MEM_MASKr */
  27514         soc_block_list[91],
  27515         soc_genreg,
  27516         1,
  27517         0,
  27518         0x1df,
  27519         SOC_REG_FLAG_WO,
  27520         0,
  27521         12,
  27522         soc_BRDC_FMACH_ECC_1B_ERR_MONITOR_MEM_MASKr_fields,
  27523         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  27524         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  27525         -1,
  27526         -1,
  27527     },
  27528 #endif /* chips */
  27529 
  27530 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27531     defined(BCM_88754_A0)
  27532     { /* SOC_REG_INT_BRDC_FMACL_ECC_2B_ERR_ADDRr */
  27533         soc_block_list[91],
  27534         soc_genreg,
  27535         1,
  27536         0,
  27537         0x1e2,
  27538         SOC_REG_FLAG_RO |
  27539                           SOC_REG_FLAG_WO,
  27540         0,
  27541         2,
  27542         soc_BRDC_FMACH_ECC_2B_ERR_ADDRr_fields,
  27543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27544         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27545         -1,
  27546         -1,
  27547     },
  27548 #endif /* chips */
  27549 
  27550 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27551     defined(BCM_88754_A0)
  27552     { /* SOC_REG_INT_BRDC_FMACL_ECC_2B_ERR_CNTr */
  27553         soc_block_list[91],
  27554         soc_genreg,
  27555         1,
  27556         0,
  27557         0x1de,
  27558         SOC_REG_FLAG_RO |
  27559                           SOC_REG_FLAG_WO,
  27560         0,
  27561         2,
  27562         soc_BRDC_FMACH_ECC_2B_ERR_CNTr_fields,
  27563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27564         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27565         -1,
  27566         -1,
  27567     },
  27568 #endif /* chips */
  27569 
  27570 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27571     defined(BCM_88754_A0)
  27572     { /* SOC_REG_INT_BRDC_FMACL_ECC_2B_ERR_MONITOR_MEM_MASKr */
  27573         soc_block_list[91],
  27574         soc_genreg,
  27575         1,
  27576         0,
  27577         0x1e0,
  27578         SOC_REG_FLAG_WO,
  27579         0,
  27580         12,
  27581         soc_BRDC_FMACH_ECC_2B_ERR_MONITOR_MEM_MASKr_fields,
  27582         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  27583         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  27584         -1,
  27585         -1,
  27586     },
  27587 #endif /* chips */
  27588 
  27589 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27590     defined(BCM_88754_A0)
  27591     { /* SOC_REG_INT_BRDC_FMACL_EDS_CONFIGURATIONr */
  27592         soc_block_list[91],
  27593         soc_genreg,
  27594         4,
  27595         0,
  27596         0xb8,
  27597         SOC_REG_FLAG_ARRAY |
  27598                           SOC_REG_FLAG_WO |
  27599                           SOC_REG_FLAG_REG_ARRAY,
  27600         0,
  27601         14,
  27602         soc_BRDC_FMACH_EDS_CONFIGURATIONr_fields,
  27603         SOC_RESET_VAL_DEC(0x0022001f, 0x00000000)
  27604         SOC_RESET_MASK_DEC(0x33ff001f, 0x00000000)
  27605         -1,
  27606         -1,
  27607     },
  27608 #endif /* chips */
  27609 
  27610 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27611     defined(BCM_88754_A0)
  27612     { /* SOC_REG_INT_BRDC_FMACL_EDS_STATUSr */
  27613         soc_block_list[91],
  27614         soc_genreg,
  27615         4,
  27616         0,
  27617         0xd0,
  27618         SOC_REG_FLAG_ARRAY |
  27619                           SOC_REG_FLAG_RO |
  27620                           SOC_REG_FLAG_WO |
  27621                           SOC_REG_FLAG_REG_ARRAY,
  27622         0,
  27623         5,
  27624         soc_BRDC_FMACH_EDS_STATUSr_fields,
  27625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27626         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  27627         -1,
  27628         -1,
  27629     },
  27630 #endif /* chips */
  27631 
  27632 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27633     defined(BCM_88754_A0)
  27634     { /* SOC_REG_INT_BRDC_FMACL_ERROR_INITIATIONr */
  27635         soc_block_list[91],
  27636         soc_genreg,
  27637         4,
  27638         0,
  27639         0x1e4,
  27640         SOC_REG_FLAG_ARRAY |
  27641                           SOC_REG_FLAG_WO |
  27642                           SOC_REG_FLAG_REG_ARRAY,
  27643         0,
  27644         6,
  27645         soc_BRDC_FMACH_ERROR_INITIATIONr_fields,
  27646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27647         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  27648         -1,
  27649         -1,
  27650     },
  27651 #endif /* chips */
  27652 
  27653 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27654     defined(BCM_88754_A0)
  27655     { /* SOC_REG_INT_BRDC_FMACL_ERROR_INITIATION_DATAr */
  27656         soc_block_list[91],
  27657         soc_genreg,
  27658         1,
  27659         0,
  27660         0x1e3,
  27661         SOC_REG_FLAG_RO |
  27662                           SOC_REG_FLAG_WO,
  27663         0,
  27664         1,
  27665         soc_BRDC_FMACH_ERROR_INITIATION_DATAr_fields,
  27666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27667         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  27668         -1,
  27669         -1,
  27670     },
  27671 #endif /* chips */
  27672 
  27673 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27674     defined(BCM_88754_A0)
  27675     { /* SOC_REG_INT_BRDC_FMACL_FBIST_CONFIGURATION_Ar */
  27676         soc_block_list[91],
  27677         soc_genreg,
  27678         1,
  27679         0,
  27680         0x1da,
  27681         SOC_REG_FLAG_WO,
  27682         0,
  27683         8,
  27684         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM83208_A0r_fields,
  27685         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  27686         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  27687         -1,
  27688         -1,
  27689     },
  27690 #endif /* chips */
  27691 
  27692 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27693     defined(BCM_88754_A0)
  27694     { /* SOC_REG_INT_BRDC_FMACL_FBIST_CONFIGURATION_Br */
  27695         soc_block_list[91],
  27696         soc_genreg,
  27697         1,
  27698         0,
  27699         0x1db,
  27700         SOC_REG_FLAG_WO,
  27701         0,
  27702         1,
  27703         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM83208_A0r_fields,
  27704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27705         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  27706         -1,
  27707         -1,
  27708     },
  27709 #endif /* chips */
  27710 
  27711 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27712     defined(BCM_88754_A0)
  27713     { /* SOC_REG_INT_BRDC_FMACL_FBIST_STATUSr */
  27714         soc_block_list[91],
  27715         soc_genreg,
  27716         1,
  27717         0,
  27718         0x1dc,
  27719         SOC_REG_FLAG_RO |
  27720                           SOC_REG_FLAG_WO,
  27721         0,
  27722         1,
  27723         soc_BRDC_FMACH_FBIST_STATUSr_fields,
  27724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27725         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  27726         -1,
  27727         -1,
  27728     },
  27729 #endif /* chips */
  27730 
  27731 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27732     defined(BCM_88754_A0)
  27733     { /* SOC_REG_INT_BRDC_FMACL_FMAL_COMMA_BURST_CONFIGURATIONr */
  27734         soc_block_list[91],
  27735         soc_genreg,
  27736         4,
  27737         0,
  27738         0xa4,
  27739         SOC_REG_FLAG_ARRAY |
  27740                           SOC_REG_FLAG_WO |
  27741                           SOC_REG_FLAG_REG_ARRAY,
  27742         0,
  27743         6,
  27744         soc_BRDC_FMACH_FMAL_COMMA_BURST_CONFIGURATIONr_fields,
  27745         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  27746         SOC_RESET_MASK_DEC(0x8fffffff, 0x00000000)
  27747         -1,
  27748         -1,
  27749     },
  27750 #endif /* chips */
  27751 
  27752 #if defined(BCM_88750_A0)
  27753     { /* SOC_REG_INT_BRDC_FMACL_FMAL_GENERAL_CONFIGURATIONr */
  27754         soc_block_list[91],
  27755         soc_genreg,
  27756         4,
  27757         0,
  27758         0xa0,
  27759         SOC_REG_FLAG_ARRAY |
  27760                           SOC_REG_FLAG_WO |
  27761                           SOC_REG_FLAG_REG_ARRAY,
  27762         0,
  27763         8,
  27764         soc_BRDC_FMACH_FMAL_GENERAL_CONFIGURATIONr_fields,
  27765         SOC_RESET_VAL_DEC(0x00000022, 0x00000000)
  27766         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  27767         -1,
  27768         -1,
  27769     },
  27770 #endif /* chips */
  27771 
  27772 #if defined(BCM_88750_B0)
  27773     { /* SOC_REG_INT_BRDC_FMACL_FMAL_GENERAL_CONFIGURATION_BCM88750_B0r */
  27774         soc_block_list[91],
  27775         soc_genreg,
  27776         4,
  27777         0,
  27778         0xa0,
  27779         SOC_REG_FLAG_ARRAY |
  27780                           SOC_REG_FLAG_WO |
  27781                           SOC_REG_FLAG_REG_ARRAY,
  27782         0,
  27783         11,
  27784         soc_BRDC_FMACH_FMAL_GENERAL_CONFIGURATION_BCM88750_B0r_fields,
  27785         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  27786         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  27787         -1,
  27788         -1,
  27789     },
  27790 #endif /* chips */
  27791 
  27792 #if defined(BCM_88754_A0)
  27793     { /* SOC_REG_INT_BRDC_FMACL_FMAL_GENERAL_CONFIGURATION_BCM88754_A0r */
  27794         soc_block_list[91],
  27795         soc_genreg,
  27796         4,
  27797         0,
  27798         0xa0,
  27799         SOC_REG_FLAG_ARRAY |
  27800                           SOC_REG_FLAG_WO |
  27801                           SOC_REG_FLAG_REG_ARRAY,
  27802         0,
  27803         12,
  27804         soc_BRDC_FMACH_FMAL_GENERAL_CONFIGURATION_BCM88754_A0r_fields,
  27805         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  27806         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  27807         -1,
  27808         -1,
  27809     },
  27810 #endif /* chips */
  27811 
  27812 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27813     defined(BCM_88754_A0)
  27814     { /* SOC_REG_INT_BRDC_FMACL_FMAL_STATISTICS_COUNT_CONTROLr */
  27815         soc_block_list[91],
  27816         soc_genreg,
  27817         1,
  27818         0,
  27819         0x90,
  27820         SOC_REG_FLAG_WO,
  27821         0,
  27822         2,
  27823         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM83208_A0r_fields,
  27824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27825         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  27826         -1,
  27827         -1,
  27828     },
  27829 #endif /* chips */
  27830 
  27831 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27832     defined(BCM_88754_A0)
  27833     { /* SOC_REG_INT_BRDC_FMACL_FMAL_STATISTICS_GTIMERr */
  27834         soc_block_list[91],
  27835         soc_genreg,
  27836         1,
  27837         0,
  27838         0x91,
  27839         SOC_REG_FLAG_64_BITS |
  27840                           SOC_REG_FLAG_WO,
  27841         0,
  27842         4,
  27843         soc_BRDC_FMACH_FMAL_STATISTICS_GTIMERr_fields,
  27844         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  27845         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  27846         -1,
  27847         -1,
  27848     },
  27849 #endif /* chips */
  27850 
  27851 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27852     defined(BCM_88754_A0)
  27853     { /* SOC_REG_INT_BRDC_FMACL_FMAL_STATISTICS_OUTPUTr */
  27854         soc_block_list[91],
  27855         soc_genreg,
  27856         1,
  27857         0,
  27858         0x94,
  27859         SOC_REG_FLAG_64_BITS |
  27860                           SOC_REG_FLAG_RO |
  27861                           SOC_REG_FLAG_WO,
  27862         0,
  27863         2,
  27864         soc_BRDC_FMACH_FMAL_STATISTICS_OUTPUTr_fields,
  27865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27866         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  27867         -1,
  27868         -1,
  27869     },
  27870 #endif /* chips */
  27871 
  27872 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27873     defined(BCM_88754_A0)
  27874     { /* SOC_REG_INT_BRDC_FMACL_FMAL_STATISTICS_OUTPUT_CONTROLr */
  27875         soc_block_list[91],
  27876         soc_genreg,
  27877         1,
  27878         0,
  27879         0x93,
  27880         SOC_REG_FLAG_WO,
  27881         0,
  27882         5,
  27883         soc_BRDC_FMACH_FMAL_STATISTICS_OUTPUT_CONTROLr_fields,
  27884         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  27885         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  27886         -1,
  27887         -1,
  27888     },
  27889 #endif /* chips */
  27890 
  27891 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27892     defined(BCM_88754_A0)
  27893     { /* SOC_REG_INT_BRDC_FMACL_FPS_CONFIGURATION_BERr */
  27894         soc_block_list[91],
  27895         soc_genreg,
  27896         4,
  27897         0,
  27898         0xf0,
  27899         SOC_REG_FLAG_ARRAY |
  27900                           SOC_REG_FLAG_WO |
  27901                           SOC_REG_FLAG_REG_ARRAY,
  27902         0,
  27903         6,
  27904         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM83208_A0r_fields,
  27905         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  27906         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  27907         -1,
  27908         -1,
  27909     },
  27910 #endif /* chips */
  27911 
  27912 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27913     defined(BCM_88754_A0)
  27914     { /* SOC_REG_INT_BRDC_FMACL_FPS_CONFIGURATION_RX_SYNCr */
  27915         soc_block_list[91],
  27916         soc_genreg,
  27917         4,
  27918         0,
  27919         0x100,
  27920         SOC_REG_FLAG_ARRAY |
  27921                           SOC_REG_FLAG_WO |
  27922                           SOC_REG_FLAG_REG_ARRAY,
  27923         0,
  27924         7,
  27925         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM83208_A0r_fields,
  27926         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  27927         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  27928         -1,
  27929         -1,
  27930     },
  27931 #endif /* chips */
  27932 
  27933 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27934     defined(BCM_88754_A0)
  27935     { /* SOC_REG_INT_BRDC_FMACL_FPS_RX_FEC_CONFIGURATIONr */
  27936         soc_block_list[91],
  27937         soc_genreg,
  27938         4,
  27939         0,
  27940         0x110,
  27941         SOC_REG_FLAG_ARRAY |
  27942                           SOC_REG_FLAG_WO |
  27943                           SOC_REG_FLAG_REG_ARRAY,
  27944         0,
  27945         17,
  27946         soc_BRDC_FMACH_FPS_RX_FEC_CONFIGURATIONr_fields,
  27947         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  27948         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  27949         -1,
  27950         -1,
  27951     },
  27952 #endif /* chips */
  27953 
  27954 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27955     defined(BCM_88754_A0)
  27956     { /* SOC_REG_INT_BRDC_FMACL_FPS_RX_STATUSr */
  27957         soc_block_list[91],
  27958         soc_genreg,
  27959         4,
  27960         0,
  27961         0x130,
  27962         SOC_REG_FLAG_ARRAY |
  27963                           SOC_REG_FLAG_RO |
  27964                           SOC_REG_FLAG_WO |
  27965                           SOC_REG_FLAG_REG_ARRAY,
  27966         0,
  27967         7,
  27968         soc_BRDC_FMACH_FPS_RX_STATUSr_fields,
  27969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  27970         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  27971         -1,
  27972         -1,
  27973     },
  27974 #endif /* chips */
  27975 
  27976 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  27977     defined(BCM_88754_A0)
  27978     { /* SOC_REG_INT_BRDC_FMACL_FPS_TX_CONFIGURATIONr */
  27979         soc_block_list[91],
  27980         soc_genreg,
  27981         4,
  27982         0,
  27983         0x120,
  27984         SOC_REG_FLAG_ARRAY |
  27985                           SOC_REG_FLAG_WO |
  27986                           SOC_REG_FLAG_REG_ARRAY,
  27987         0,
  27988         9,
  27989         soc_BRDC_FMACH_FPS_TX_CONFIGURATIONr_fields,
  27990         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  27991         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  27992         -1,
  27993         -1,
  27994     },
  27995 #endif /* chips */
  27996 
  27997 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  27998     { /* SOC_REG_INT_BRDC_FMACL_GENERAL_CONFIGURATION_REGISTERr */
  27999         soc_block_list[91],
  28000         soc_genreg,
  28001         1,
  28002         0,
  28003         0x60,
  28004         SOC_REG_FLAG_WO,
  28005         0,
  28006         13,
  28007         soc_BRDC_FMACH_GENERAL_CONFIGURATION_REGISTERr_fields,
  28008         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  28009         SOC_RESET_MASK_DEC(0x07780f0f, 0x00000000)
  28010         -1,
  28011         -1,
  28012     },
  28013 #endif /* chips */
  28014 
  28015 #if defined(BCM_88754_A0)
  28016     { /* SOC_REG_INT_BRDC_FMACL_GENERAL_CONFIGURATION_REGISTER_BCM88754_A0r */
  28017         soc_block_list[91],
  28018         soc_genreg,
  28019         1,
  28020         0,
  28021         0x60,
  28022         SOC_REG_FLAG_WO,
  28023         0,
  28024         12,
  28025         soc_BRDC_FMACH_GENERAL_CONFIGURATION_REGISTER_BCM88754_A0r_fields,
  28026         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  28027         SOC_RESET_MASK_DEC(0x06780f0f, 0x00000000)
  28028         -1,
  28029         -1,
  28030     },
  28031 #endif /* chips */
  28032 
  28033 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28034     defined(BCM_88754_A0)
  28035     { /* SOC_REG_INT_BRDC_FMACL_GLOBAL_TEST_RX_IDL_PTRNr */
  28036         soc_block_list[91],
  28037         soc_genreg,
  28038         1,
  28039         0,
  28040         0x1d7,
  28041         SOC_REG_FLAG_ABOVE_64_BITS |
  28042                           SOC_REG_FLAG_WO,
  28043         0,
  28044         1,
  28045         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM83208_A0r_fields,
  28046         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28047         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28048         -1,
  28049         -1,
  28050     },
  28051 #endif /* chips */
  28052 
  28053 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28054     defined(BCM_88754_A0)
  28055     { /* SOC_REG_INT_BRDC_FMACL_GLOBAL_TEST_TX_IDL_PTRNr */
  28056         soc_block_list[91],
  28057         soc_genreg,
  28058         1,
  28059         0,
  28060         0x1d4,
  28061         SOC_REG_FLAG_ABOVE_64_BITS |
  28062                           SOC_REG_FLAG_WO,
  28063         0,
  28064         1,
  28065         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM83208_A0r_fields,
  28066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28067         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  28068         -1,
  28069         -1,
  28070     },
  28071 #endif /* chips */
  28072 
  28073 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28074     defined(BCM_88754_A0)
  28075     { /* SOC_REG_INT_BRDC_FMACL_GLOBAL_TEST_TX_PR_SEED_Ar */
  28076         soc_block_list[91],
  28077         soc_genreg,
  28078         1,
  28079         0,
  28080         0x1d0,
  28081         SOC_REG_FLAG_64_BITS |
  28082                           SOC_REG_FLAG_WO,
  28083         0,
  28084         1,
  28085         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM83208_A0r_fields,
  28086         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  28087         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  28088         -1,
  28089         -1,
  28090     },
  28091 #endif /* chips */
  28092 
  28093 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28094     defined(BCM_88754_A0)
  28095     { /* SOC_REG_INT_BRDC_FMACL_GLOBAL_TEST_TX_PR_SEED_Br */
  28096         soc_block_list[91],
  28097         soc_genreg,
  28098         1,
  28099         0,
  28100         0x1d2,
  28101         SOC_REG_FLAG_64_BITS |
  28102                           SOC_REG_FLAG_WO,
  28103         0,
  28104         1,
  28105         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM83208_A0r_fields,
  28106         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  28107         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  28108         -1,
  28109         -1,
  28110     },
  28111 #endif /* chips */
  28112 
  28113 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28114     defined(BCM_88754_A0)
  28115     { /* SOC_REG_INT_BRDC_FMACL_GTIMER_CONFIGURATIONr */
  28116         soc_block_list[91],
  28117         soc_genreg,
  28118         1,
  28119         0,
  28120         0x56,
  28121         SOC_REG_FLAG_WO,
  28122         0,
  28123         3,
  28124         soc_BRDC_FMACH_GTIMER_CONFIGURATIONr_fields,
  28125         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  28126         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28127         -1,
  28128         -1,
  28129     },
  28130 #endif /* chips */
  28131 
  28132 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28133     defined(BCM_88754_A0)
  28134     { /* SOC_REG_INT_BRDC_FMACL_GTIMER_TRIGGERr */
  28135         soc_block_list[91],
  28136         soc_genreg,
  28137         1,
  28138         0,
  28139         0x57,
  28140         SOC_REG_FLAG_WO,
  28141         0,
  28142         1,
  28143         soc_BRDC_FMACH_GTIMER_TRIGGERr_fields,
  28144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28145         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  28146         -1,
  28147         -1,
  28148     },
  28149 #endif /* chips */
  28150 
  28151 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28152     defined(BCM_88754_A0)
  28153     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTERr */
  28154         soc_block_list[91],
  28155         soc_genreg,
  28156         1,
  28157         0,
  28158         0x10,
  28159         SOC_REG_FLAG_WO,
  28160         0,
  28161         9,
  28162         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTERr_fields,
  28163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28164         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  28165         -1,
  28166         -1,
  28167     },
  28168 #endif /* chips */
  28169 
  28170 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28171     defined(BCM_88754_A0)
  28172     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_1r */
  28173         soc_block_list[91],
  28174         soc_genreg,
  28175         1,
  28176         0,
  28177         0x11,
  28178         SOC_REG_FLAG_WO,
  28179         0,
  28180         2,
  28181         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM83208_A0r_fields,
  28182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28183         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28184         -1,
  28185         -1,
  28186     },
  28187 #endif /* chips */
  28188 
  28189 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28190     defined(BCM_88754_A0)
  28191     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_2r */
  28192         soc_block_list[91],
  28193         soc_genreg,
  28194         1,
  28195         0,
  28196         0x12,
  28197         SOC_REG_FLAG_WO,
  28198         0,
  28199         2,
  28200         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM83208_A0r_fields,
  28201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28202         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28203         -1,
  28204         -1,
  28205     },
  28206 #endif /* chips */
  28207 
  28208 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28209     defined(BCM_88754_A0)
  28210     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_3r */
  28211         soc_block_list[91],
  28212         soc_genreg,
  28213         1,
  28214         0,
  28215         0x13,
  28216         SOC_REG_FLAG_WO,
  28217         0,
  28218         2,
  28219         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM83208_A0r_fields,
  28220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28221         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28222         -1,
  28223         -1,
  28224     },
  28225 #endif /* chips */
  28226 
  28227 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28228     defined(BCM_88754_A0)
  28229     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_4r */
  28230         soc_block_list[91],
  28231         soc_genreg,
  28232         1,
  28233         0,
  28234         0x14,
  28235         SOC_REG_FLAG_WO,
  28236         0,
  28237         2,
  28238         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM83208_A0r_fields,
  28239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28240         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28241         -1,
  28242         -1,
  28243     },
  28244 #endif /* chips */
  28245 
  28246 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28247     defined(BCM_88754_A0)
  28248     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_5r */
  28249         soc_block_list[91],
  28250         soc_genreg,
  28251         1,
  28252         0,
  28253         0x15,
  28254         SOC_REG_FLAG_WO,
  28255         0,
  28256         2,
  28257         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_5r_fields,
  28258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28259         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28260         -1,
  28261         -1,
  28262     },
  28263 #endif /* chips */
  28264 
  28265 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28266     defined(BCM_88754_A0)
  28267     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_6r */
  28268         soc_block_list[91],
  28269         soc_genreg,
  28270         1,
  28271         0,
  28272         0x16,
  28273         SOC_REG_FLAG_WO,
  28274         0,
  28275         1,
  28276         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_6r_fields,
  28277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28278         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  28279         -1,
  28280         -1,
  28281     },
  28282 #endif /* chips */
  28283 
  28284 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28285     defined(BCM_88754_A0)
  28286     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_7r */
  28287         soc_block_list[91],
  28288         soc_genreg,
  28289         1,
  28290         0,
  28291         0x17,
  28292         SOC_REG_FLAG_WO,
  28293         0,
  28294         1,
  28295         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_7r_fields,
  28296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28297         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  28298         -1,
  28299         -1,
  28300     },
  28301 #endif /* chips */
  28302 
  28303 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28304     defined(BCM_88754_A0)
  28305     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_8r */
  28306         soc_block_list[91],
  28307         soc_genreg,
  28308         1,
  28309         0,
  28310         0x18,
  28311         SOC_REG_FLAG_WO,
  28312         0,
  28313         3,
  28314         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_8r_fields,
  28315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28316         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  28317         -1,
  28318         -1,
  28319     },
  28320 #endif /* chips */
  28321 
  28322 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28323     defined(BCM_88754_A0)
  28324     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_MASK_REGISTER_9r */
  28325         soc_block_list[91],
  28326         soc_genreg,
  28327         1,
  28328         0,
  28329         0x19,
  28330         SOC_REG_FLAG_WO,
  28331         0,
  28332         2,
  28333         soc_BRDC_FMACH_INTERRUPT_MASK_REGISTER_9r_fields,
  28334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28335         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28336         -1,
  28337         -1,
  28338     },
  28339 #endif /* chips */
  28340 
  28341 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28342     defined(BCM_88754_A0)
  28343     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTERr */
  28344         soc_block_list[91],
  28345         soc_genreg,
  28346         1,
  28347         0,
  28348         0,
  28349         SOC_REG_FLAG_WO |
  28350                           SOC_REG_FLAG_INTERRUPT,
  28351         0,
  28352         9,
  28353         soc_BRDC_FMACH_INTERRUPT_REGISTERr_fields,
  28354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28355         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  28356         -1,
  28357         -1,
  28358     },
  28359 #endif /* chips */
  28360 
  28361 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28362     defined(BCM_88754_A0)
  28363     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_1r */
  28364         soc_block_list[91],
  28365         soc_genreg,
  28366         1,
  28367         0,
  28368         0x1,
  28369         SOC_REG_FLAG_WO |
  28370                           SOC_REG_FLAG_INTERRUPT,
  28371         0,
  28372         2,
  28373         soc_BRDC_FMACH_INTERRUPT_REGISTER_1r_fields,
  28374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28375         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28376         -1,
  28377         -1,
  28378     },
  28379 #endif /* chips */
  28380 
  28381 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28382     defined(BCM_88754_A0)
  28383     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_2r */
  28384         soc_block_list[91],
  28385         soc_genreg,
  28386         1,
  28387         0,
  28388         0x2,
  28389         SOC_REG_FLAG_WO |
  28390                           SOC_REG_FLAG_INTERRUPT,
  28391         0,
  28392         2,
  28393         soc_BRDC_FMACH_INTERRUPT_REGISTER_2r_fields,
  28394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28395         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28396         -1,
  28397         -1,
  28398     },
  28399 #endif /* chips */
  28400 
  28401 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28402     defined(BCM_88754_A0)
  28403     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_3r */
  28404         soc_block_list[91],
  28405         soc_genreg,
  28406         1,
  28407         0,
  28408         0x3,
  28409         SOC_REG_FLAG_WO |
  28410                           SOC_REG_FLAG_INTERRUPT,
  28411         0,
  28412         2,
  28413         soc_BRDC_FMACH_INTERRUPT_REGISTER_3r_fields,
  28414         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28415         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28416         -1,
  28417         -1,
  28418     },
  28419 #endif /* chips */
  28420 
  28421 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28422     defined(BCM_88754_A0)
  28423     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_4r */
  28424         soc_block_list[91],
  28425         soc_genreg,
  28426         1,
  28427         0,
  28428         0x4,
  28429         SOC_REG_FLAG_WO |
  28430                           SOC_REG_FLAG_INTERRUPT,
  28431         0,
  28432         2,
  28433         soc_BRDC_FMACH_INTERRUPT_REGISTER_4r_fields,
  28434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28435         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28436         -1,
  28437         -1,
  28438     },
  28439 #endif /* chips */
  28440 
  28441 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28442     defined(BCM_88754_A0)
  28443     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_5r */
  28444         soc_block_list[91],
  28445         soc_genreg,
  28446         1,
  28447         0,
  28448         0x5,
  28449         SOC_REG_FLAG_WO |
  28450                           SOC_REG_FLAG_INTERRUPT,
  28451         0,
  28452         2,
  28453         soc_BRDC_FMACH_INTERRUPT_REGISTER_5r_fields,
  28454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28455         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28456         -1,
  28457         -1,
  28458     },
  28459 #endif /* chips */
  28460 
  28461 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28462     defined(BCM_88754_A0)
  28463     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_6r */
  28464         soc_block_list[91],
  28465         soc_genreg,
  28466         1,
  28467         0,
  28468         0x6,
  28469         SOC_REG_FLAG_WO |
  28470                           SOC_REG_FLAG_INTERRUPT,
  28471         0,
  28472         1,
  28473         soc_BRDC_FMACH_INTERRUPT_REGISTER_6r_fields,
  28474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28475         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  28476         -1,
  28477         -1,
  28478     },
  28479 #endif /* chips */
  28480 
  28481 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28482     defined(BCM_88754_A0)
  28483     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_7r */
  28484         soc_block_list[91],
  28485         soc_genreg,
  28486         1,
  28487         0,
  28488         0x7,
  28489         SOC_REG_FLAG_WO |
  28490                           SOC_REG_FLAG_INTERRUPT,
  28491         0,
  28492         1,
  28493         soc_BRDC_FMACH_INTERRUPT_REGISTER_7r_fields,
  28494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28495         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  28496         -1,
  28497         -1,
  28498     },
  28499 #endif /* chips */
  28500 
  28501 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28502     defined(BCM_88754_A0)
  28503     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_8r */
  28504         soc_block_list[91],
  28505         soc_genreg,
  28506         1,
  28507         0,
  28508         0x8,
  28509         SOC_REG_FLAG_WO |
  28510                           SOC_REG_FLAG_INTERRUPT,
  28511         0,
  28512         3,
  28513         soc_BRDC_FMACH_INTERRUPT_REGISTER_8r_fields,
  28514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28515         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  28516         -1,
  28517         -1,
  28518     },
  28519 #endif /* chips */
  28520 
  28521 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28522     defined(BCM_88754_A0)
  28523     { /* SOC_REG_INT_BRDC_FMACL_INTERRUPT_REGISTER_9r */
  28524         soc_block_list[91],
  28525         soc_genreg,
  28526         1,
  28527         0,
  28528         0x9,
  28529         SOC_REG_FLAG_WO |
  28530                           SOC_REG_FLAG_INTERRUPT,
  28531         0,
  28532         2,
  28533         soc_BRDC_FMACH_INTERRUPT_REGISTER_9r_fields,
  28534         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28535         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  28536         -1,
  28537         -1,
  28538     },
  28539 #endif /* chips */
  28540 
  28541 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28542     defined(BCM_88754_A0)
  28543     { /* SOC_REG_INT_BRDC_FMACL_KPCS_CONFIGURATIONr */
  28544         soc_block_list[91],
  28545         soc_genreg,
  28546         4,
  28547         0,
  28548         0x160,
  28549         SOC_REG_FLAG_ARRAY |
  28550                           SOC_REG_FLAG_WO |
  28551                           SOC_REG_FLAG_REG_ARRAY,
  28552         0,
  28553         10,
  28554         soc_BRDC_FMACH_KPCS_CONFIGURATIONr_fields,
  28555         SOC_RESET_VAL_DEC(0x001f000f, 0x00000000)
  28556         SOC_RESET_MASK_DEC(0x003f000f, 0x00000000)
  28557         -1,
  28558         -1,
  28559     },
  28560 #endif /* chips */
  28561 
  28562 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28563     defined(BCM_88754_A0)
  28564     { /* SOC_REG_INT_BRDC_FMACL_KPCS_RX_STATUSr */
  28565         soc_block_list[91],
  28566         soc_genreg,
  28567         4,
  28568         0,
  28569         0x164,
  28570         SOC_REG_FLAG_ARRAY |
  28571                           SOC_REG_FLAG_RO |
  28572                           SOC_REG_FLAG_WO |
  28573                           SOC_REG_FLAG_REG_ARRAY,
  28574         0,
  28575         2,
  28576         soc_BRDC_FMACH_KPCS_RX_STATUSr_fields,
  28577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28578         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  28579         -1,
  28580         -1,
  28581     },
  28582 #endif /* chips */
  28583 
  28584 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28585     defined(BCM_88754_A0)
  28586     { /* SOC_REG_INT_BRDC_FMACL_KPCS_TEST_RX_CONFIGURATIONr */
  28587         soc_block_list[91],
  28588         soc_genreg,
  28589         4,
  28590         0,
  28591         0x180,
  28592         SOC_REG_FLAG_ARRAY |
  28593                           SOC_REG_FLAG_WO |
  28594                           SOC_REG_FLAG_REG_ARRAY,
  28595         0,
  28596         4,
  28597         soc_BRDC_FMACH_KPCS_TEST_RX_CONFIGURATIONr_fields,
  28598         SOC_RESET_VAL_DEC(0x000007f2, 0x00000000)
  28599         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  28600         -1,
  28601         -1,
  28602     },
  28603 #endif /* chips */
  28604 
  28605 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28606     defined(BCM_88754_A0)
  28607     { /* SOC_REG_INT_BRDC_FMACL_KPCS_TEST_RX_STATUSr */
  28608         soc_block_list[91],
  28609         soc_genreg,
  28610         4,
  28611         0,
  28612         0x190,
  28613         SOC_REG_FLAG_ARRAY |
  28614                           SOC_REG_FLAG_RO |
  28615                           SOC_REG_FLAG_WO |
  28616                           SOC_REG_FLAG_REG_ARRAY,
  28617         0,
  28618         1,
  28619         soc_BRDC_FMACH_KPCS_TEST_RX_STATUSr_fields,
  28620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28621         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28622         -1,
  28623         -1,
  28624     },
  28625 #endif /* chips */
  28626 
  28627 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28628     defined(BCM_88754_A0)
  28629     { /* SOC_REG_INT_BRDC_FMACL_KPCS_TEST_TX_CONFIGURATIONr */
  28630         soc_block_list[91],
  28631         soc_genreg,
  28632         4,
  28633         0,
  28634         0x170,
  28635         SOC_REG_FLAG_ARRAY |
  28636                           SOC_REG_FLAG_WO |
  28637                           SOC_REG_FLAG_REG_ARRAY,
  28638         0,
  28639         7,
  28640         soc_BRDC_FMACH_KPCS_TEST_TX_CONFIGURATIONr_fields,
  28641         SOC_RESET_VAL_DEC(0x00401fc2, 0x00000000)
  28642         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  28643         -1,
  28644         -1,
  28645     },
  28646 #endif /* chips */
  28647 
  28648 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28649     defined(BCM_88754_A0)
  28650     { /* SOC_REG_INT_BRDC_FMACL_LEAKY_BUCKETr */
  28651         soc_block_list[91],
  28652         soc_genreg,
  28653         4,
  28654         0,
  28655         0x70,
  28656         SOC_REG_FLAG_ARRAY |
  28657                           SOC_REG_FLAG_RO |
  28658                           SOC_REG_FLAG_WO |
  28659                           SOC_REG_FLAG_REG_ARRAY,
  28660         0,
  28661         2,
  28662         soc_BRDC_FMACH_LEAKY_BUCKETr_fields,
  28663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28664         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  28665         -1,
  28666         -1,
  28667     },
  28668 #endif /* chips */
  28669 
  28670 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28671     defined(BCM_88754_A0)
  28672     { /* SOC_REG_INT_BRDC_FMACL_LEAKY_BUCKET_CONTROL_REGISTERr */
  28673         soc_block_list[91],
  28674         soc_genreg,
  28675         1,
  28676         0,
  28677         0x61,
  28678         SOC_REG_FLAG_WO,
  28679         0,
  28680         6,
  28681         soc_BRDC_FMACH_LEAKY_BUCKET_CONTROL_REGISTERr_fields,
  28682         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  28683         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  28684         -1,
  28685         -1,
  28686     },
  28687 #endif /* chips */
  28688 
  28689 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28690     defined(BCM_88754_A0)
  28691     { /* SOC_REG_INT_BRDC_FMACL_LFEC_CONFIGURATIONr */
  28692         soc_block_list[91],
  28693         soc_genreg,
  28694         4,
  28695         0,
  28696         0xe0,
  28697         SOC_REG_FLAG_ARRAY |
  28698                           SOC_REG_FLAG_WO |
  28699                           SOC_REG_FLAG_REG_ARRAY,
  28700         0,
  28701         10,
  28702         soc_BRDC_FMACH_LFEC_CONFIGURATIONr_fields,
  28703         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  28704         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  28705         -1,
  28706         -1,
  28707     },
  28708 #endif /* chips */
  28709 
  28710 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28711     defined(BCM_88754_A0)
  28712     { /* SOC_REG_INT_BRDC_FMACL_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr */
  28713         soc_block_list[91],
  28714         soc_genreg,
  28715         1,
  28716         0,
  28717         0x64,
  28718         SOC_REG_FLAG_WO,
  28719         0,
  28720         4,
  28721         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM83208_A0r_fields,
  28722         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  28723         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  28724         -1,
  28725         -1,
  28726     },
  28727 #endif /* chips */
  28728 
  28729 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28730     defined(BCM_88754_A0)
  28731     { /* SOC_REG_INT_BRDC_FMACL_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr */
  28732         soc_block_list[91],
  28733         soc_genreg,
  28734         1,
  28735         0,
  28736         0x21,
  28737         SOC_REG_FLAG_WO,
  28738         0,
  28739         2,
  28740         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM83208_A0r_fields,
  28741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28742         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28743         -1,
  28744         -1,
  28745     },
  28746 #endif /* chips */
  28747 
  28748 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  28749     { /* SOC_REG_INT_BRDC_FMACL_LOOPBACK_ENABLE_REGISTERr */
  28750         soc_block_list[91],
  28751         soc_genreg,
  28752         1,
  28753         0,
  28754         0x20,
  28755         SOC_REG_FLAG_WO,
  28756         0,
  28757         1,
  28758         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM83208_A0r_fields,
  28759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28760         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  28761         -1,
  28762         -1,
  28763     },
  28764 #endif /* chips */
  28765 
  28766 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28767     defined(BCM_88754_A0)
  28768     { /* SOC_REG_INT_BRDC_FMACL_RECEIVE_RESET_REGISTERr */
  28769         soc_block_list[91],
  28770         soc_genreg,
  28771         1,
  28772         0,
  28773         0x63,
  28774         SOC_REG_FLAG_WO,
  28775         0,
  28776         2,
  28777         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM83208_A0r_fields,
  28778         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  28779         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  28780         -1,
  28781         -1,
  28782     },
  28783 #endif /* chips */
  28784 
  28785 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28786     defined(BCM_88754_A0)
  28787     { /* SOC_REG_INT_BRDC_FMACL_REG_0050r */
  28788         soc_block_list[91],
  28789         soc_genreg,
  28790         1,
  28791         0,
  28792         0x50,
  28793         SOC_REG_FLAG_WO,
  28794         0,
  28795         1,
  28796         soc_ECI_REG_0050r_fields,
  28797         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  28798         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28799         -1,
  28800         -1,
  28801     },
  28802 #endif /* chips */
  28803 
  28804 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28805     defined(BCM_88754_A0)
  28806     { /* SOC_REG_INT_BRDC_FMACL_REG_0051r */
  28807         soc_block_list[91],
  28808         soc_genreg,
  28809         1,
  28810         0,
  28811         0x51,
  28812         SOC_REG_FLAG_WO,
  28813         0,
  28814         1,
  28815         soc_ECI_REG_0051r_fields,
  28816         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  28817         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28818         -1,
  28819         -1,
  28820     },
  28821 #endif /* chips */
  28822 
  28823 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28824     defined(BCM_88754_A0)
  28825     { /* SOC_REG_INT_BRDC_FMACL_REG_0052r */
  28826         soc_block_list[91],
  28827         soc_genreg,
  28828         1,
  28829         0,
  28830         0x52,
  28831         SOC_REG_FLAG_WO,
  28832         0,
  28833         1,
  28834         soc_ECI_REG_0052r_fields,
  28835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28836         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  28837         -1,
  28838         -1,
  28839     },
  28840 #endif /* chips */
  28841 
  28842 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28843     defined(BCM_88754_A0)
  28844     { /* SOC_REG_INT_BRDC_FMACL_REG_0054r */
  28845         soc_block_list[91],
  28846         soc_genreg,
  28847         1,
  28848         0,
  28849         0x54,
  28850         SOC_REG_FLAG_WO,
  28851         0,
  28852         2,
  28853         soc_DRCBROADCAST_REG_0085_BCM83207_A0r_fields,
  28854         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28855         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  28856         -1,
  28857         -1,
  28858     },
  28859 #endif /* chips */
  28860 
  28861 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28862     defined(BCM_88754_A0)
  28863     { /* SOC_REG_INT_BRDC_FMACL_REG_0065r */
  28864         soc_block_list[91],
  28865         soc_genreg,
  28866         1,
  28867         0,
  28868         0x65,
  28869         SOC_REG_FLAG_WO,
  28870         0,
  28871         2,
  28872         soc_BRDC_FMACH_REG_0065r_fields,
  28873         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  28874         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28875         -1,
  28876         -1,
  28877     },
  28878 #endif /* chips */
  28879 
  28880 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28881     defined(BCM_88754_A0)
  28882     { /* SOC_REG_INT_BRDC_FMACL_REG_0066r */
  28883         soc_block_list[91],
  28884         soc_genreg,
  28885         1,
  28886         0,
  28887         0x66,
  28888         SOC_REG_FLAG_WO,
  28889         0,
  28890         1,
  28891         soc_BRDC_FMAC_REG_0102_BCM83208_A0r_fields,
  28892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28893         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  28894         -1,
  28895         -1,
  28896     },
  28897 #endif /* chips */
  28898 
  28899 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28900     defined(BCM_88754_A0)
  28901     { /* SOC_REG_INT_BRDC_FMACL_REG_0096r */
  28902         soc_block_list[91],
  28903         soc_genreg,
  28904         1,
  28905         0,
  28906         0x96,
  28907         SOC_REG_FLAG_64_BITS |
  28908                           SOC_REG_FLAG_WO,
  28909         0,
  28910         1,
  28911         soc_BRDC_FMACH_REG_0096r_fields,
  28912         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  28913         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  28914         -1,
  28915         -1,
  28916     },
  28917 #endif /* chips */
  28918 
  28919 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28920     defined(BCM_88754_A0)
  28921     { /* SOC_REG_INT_BRDC_FMACL_REG_0098r */
  28922         soc_block_list[91],
  28923         soc_genreg,
  28924         1,
  28925         0,
  28926         0x98,
  28927         SOC_REG_FLAG_WO,
  28928         0,
  28929         8,
  28930         soc_BRDC_FMACH_REG_0098r_fields,
  28931         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  28932         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  28933         -1,
  28934         -1,
  28935     },
  28936 #endif /* chips */
  28937 
  28938 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28939     defined(BCM_88754_A0)
  28940     { /* SOC_REG_INT_BRDC_FMACL_REG_0099r */
  28941         soc_block_list[91],
  28942         soc_genreg,
  28943         1,
  28944         0,
  28945         0x99,
  28946         SOC_REG_FLAG_WO,
  28947         0,
  28948         1,
  28949         soc_BRDC_FMACH_REG_0099r_fields,
  28950         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  28951         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  28952         -1,
  28953         -1,
  28954     },
  28955 #endif /* chips */
  28956 
  28957 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  28958     defined(BCM_88754_A0)
  28959     { /* SOC_REG_INT_BRDC_FMACL_REG_0140r */
  28960         soc_block_list[91],
  28961         soc_genreg,
  28962         4,
  28963         0,
  28964         0x140,
  28965         SOC_REG_FLAG_64_BITS |
  28966                           SOC_REG_FLAG_ARRAY |
  28967                           SOC_REG_FLAG_WO |
  28968                           SOC_REG_FLAG_REG_ARRAY |
  28969                           SOC_REG_FLAG_SIGNAL,
  28970         0,
  28971         2,
  28972         soc_BRDC_FMACH_REG_0140r_fields,
  28973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28974         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  28975         -1,
  28976         -1,
  28977     },
  28978 #endif /* chips */
  28979 
  28980 #if defined(BCM_88750_A0) || defined(BCM_88754_A0)
  28981     { /* SOC_REG_INT_BRDC_FMACL_REG_005Ar */
  28982         soc_block_list[91],
  28983         soc_genreg,
  28984         1,
  28985         0,
  28986         0x5a,
  28987         SOC_REG_FLAG_WO,
  28988         0,
  28989         6,
  28990         soc_BRDC_FMACH_REG_005Ar_fields,
  28991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  28992         SOC_RESET_MASK_DEC(0x0000074b, 0x00000000)
  28993         -1,
  28994         -1,
  28995     },
  28996 #endif /* chips */
  28997 
  28998 #if defined(BCM_88750_B0)
  28999     { /* SOC_REG_INT_BRDC_FMACL_REG_005A_BCM88750_B0r */
  29000         soc_block_list[91],
  29001         soc_genreg,
  29002         1,
  29003         0,
  29004         0x5a,
  29005         SOC_REG_FLAG_WO,
  29006         0,
  29007         6,
  29008         soc_BRDC_FMACH_REG_005A_BCM88750_B0r_fields,
  29009         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  29010         SOC_RESET_MASK_DEC(0x0000074b, 0x00000000)
  29011         -1,
  29012         -1,
  29013     },
  29014 #endif /* chips */
  29015 
  29016 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29017     defined(BCM_88754_A0)
  29018     { /* SOC_REG_INT_BRDC_FMACL_REG_005Br */
  29019         soc_block_list[91],
  29020         soc_genreg,
  29021         1,
  29022         0,
  29023         0x5b,
  29024         SOC_REG_FLAG_WO,
  29025         0,
  29026         1,
  29027         soc_BRDC_FMACH_REG_005Br_fields,
  29028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29029         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29030         -1,
  29031         -1,
  29032     },
  29033 #endif /* chips */
  29034 
  29035 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29036     defined(BCM_88754_A0)
  29037     { /* SOC_REG_INT_BRDC_FMACL_REG_01A8r */
  29038         soc_block_list[91],
  29039         soc_genreg,
  29040         4,
  29041         0,
  29042         0x1a8,
  29043         SOC_REG_FLAG_ARRAY |
  29044                           SOC_REG_FLAG_WO |
  29045                           SOC_REG_FLAG_REG_ARRAY,
  29046         0,
  29047         1,
  29048         soc_BRDC_FMACH_REG_01A8r_fields,
  29049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29050         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29051         -1,
  29052         -1,
  29053     },
  29054 #endif /* chips */
  29055 
  29056 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29057     defined(BCM_88754_A0)
  29058     { /* SOC_REG_INT_BRDC_FMACL_REG_01ACr */
  29059         soc_block_list[91],
  29060         soc_genreg,
  29061         4,
  29062         0,
  29063         0x1ac,
  29064         SOC_REG_FLAG_ARRAY |
  29065                           SOC_REG_FLAG_WO |
  29066                           SOC_REG_FLAG_REG_ARRAY,
  29067         0,
  29068         3,
  29069         soc_BRDC_FMACH_REG_01ACr_fields,
  29070         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  29071         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  29072         -1,
  29073         -1,
  29074     },
  29075 #endif /* chips */
  29076 
  29077 #if defined(BCM_88754_A0)
  29078     { /* SOC_REG_INT_BRDC_FMACL_REG_01E9r */
  29079         soc_block_list[91],
  29080         soc_genreg,
  29081         1,
  29082         0,
  29083         0x1e9,
  29084         SOC_REG_FLAG_RO |
  29085                           SOC_REG_FLAG_WO,
  29086         0,
  29087         3,
  29088         soc_BRDC_FMACH_REG_01E9r_fields,
  29089         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29090         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29091         -1,
  29092         -1,
  29093     },
  29094 #endif /* chips */
  29095 
  29096 #if defined(BCM_88754_A0)
  29097     { /* SOC_REG_INT_BRDC_FMACL_REG_01EAr */
  29098         soc_block_list[91],
  29099         soc_genreg,
  29100         1,
  29101         0,
  29102         0x1ea,
  29103         SOC_REG_FLAG_WO,
  29104         0,
  29105         1,
  29106         soc_DRCBROADCAST_REG_00B2_BCM83207_A0r_fields,
  29107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29108         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  29109         -1,
  29110         -1,
  29111     },
  29112 #endif /* chips */
  29113 
  29114 #if defined(BCM_88754_A0)
  29115     { /* SOC_REG_INT_BRDC_FMACL_REG_01EBr */
  29116         soc_block_list[91],
  29117         soc_genreg,
  29118         1,
  29119         0,
  29120         0x1eb,
  29121         SOC_REG_FLAG_RO |
  29122                           SOC_REG_FLAG_WO,
  29123         0,
  29124         1,
  29125         soc_BRDC_FMACH_REG_01EBr_fields,
  29126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29127         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29128         -1,
  29129         -1,
  29130     },
  29131 #endif /* chips */
  29132 
  29133 #if defined(BCM_88754_A0)
  29134     { /* SOC_REG_INT_BRDC_FMACL_REG_01ECr */
  29135         soc_block_list[91],
  29136         soc_genreg,
  29137         1,
  29138         0,
  29139         0x1ec,
  29140         SOC_REG_FLAG_RO |
  29141                           SOC_REG_FLAG_WO,
  29142         0,
  29143         1,
  29144         soc_BRDC_FMACH_REG_01ECr_fields,
  29145         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  29146         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29147         -1,
  29148         -1,
  29149     },
  29150 #endif /* chips */
  29151 
  29152 #if defined(BCM_88754_A0)
  29153     { /* SOC_REG_INT_BRDC_FMACL_REG_01EDr */
  29154         soc_block_list[91],
  29155         soc_genreg,
  29156         1,
  29157         0,
  29158         0x1ed,
  29159         SOC_REG_FLAG_RO |
  29160                           SOC_REG_FLAG_WO,
  29161         0,
  29162         3,
  29163         soc_BRDC_FMACH_REG_01E9r_fields,
  29164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29165         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29166         -1,
  29167         -1,
  29168     },
  29169 #endif /* chips */
  29170 
  29171 #if defined(BCM_88754_A0)
  29172     { /* SOC_REG_INT_BRDC_FMACL_REG_01EEr */
  29173         soc_block_list[91],
  29174         soc_genreg,
  29175         1,
  29176         0,
  29177         0x1ee,
  29178         SOC_REG_FLAG_WO,
  29179         0,
  29180         1,
  29181         soc_DRCBROADCAST_REG_00B2_BCM83207_A0r_fields,
  29182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29183         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  29184         -1,
  29185         -1,
  29186     },
  29187 #endif /* chips */
  29188 
  29189 #if defined(BCM_88754_A0)
  29190     { /* SOC_REG_INT_BRDC_FMACL_REG_01EFr */
  29191         soc_block_list[91],
  29192         soc_genreg,
  29193         1,
  29194         0,
  29195         0x1ef,
  29196         SOC_REG_FLAG_RO |
  29197                           SOC_REG_FLAG_WO,
  29198         0,
  29199         1,
  29200         soc_BRDC_FMACH_REG_01EBr_fields,
  29201         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29202         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29203         -1,
  29204         -1,
  29205     },
  29206 #endif /* chips */
  29207 
  29208 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29209     defined(BCM_88754_A0)
  29210     { /* SOC_REG_INT_BRDC_FMACL_REG_01FAr */
  29211         soc_block_list[91],
  29212         soc_genreg,
  29213         1,
  29214         0,
  29215         0x1fa,
  29216         SOC_REG_FLAG_WO,
  29217         0,
  29218         6,
  29219         soc_BRDC_FMACH_REG_01FAr_fields,
  29220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29221         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  29222         -1,
  29223         -1,
  29224     },
  29225 #endif /* chips */
  29226 
  29227 #if defined(BCM_88754_A0)
  29228     { /* SOC_REG_INT_BRDC_FMACL_REG_1E8r */
  29229         soc_block_list[91],
  29230         soc_genreg,
  29231         1,
  29232         0,
  29233         0x1e8,
  29234         SOC_REG_FLAG_RO |
  29235                           SOC_REG_FLAG_WO,
  29236         0,
  29237         1,
  29238         soc_BRDC_FMACH_REG_01ECr_fields,
  29239         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  29240         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29241         -1,
  29242         -1,
  29243     },
  29244 #endif /* chips */
  29245 
  29246 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29247     defined(BCM_88754_A0)
  29248     { /* SOC_REG_INT_BRDC_FMACL_SBUS_BROADCAST_IDr */
  29249         soc_block_list[91],
  29250         soc_genreg,
  29251         1,
  29252         0,
  29253         0x55,
  29254         SOC_REG_FLAG_WO,
  29255         0,
  29256         1,
  29257         soc_BRDC_FMACH_SBUS_BROADCAST_IDr_fields,
  29258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29259         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  29260         -1,
  29261         -1,
  29262     },
  29263 #endif /* chips */
  29264 
  29265 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29266     defined(BCM_88754_A0)
  29267     { /* SOC_REG_INT_BRDC_FMACL_SBUS_LAST_IN_CHAINr */
  29268         soc_block_list[91],
  29269         soc_genreg,
  29270         1,
  29271         0,
  29272         0x58,
  29273         SOC_REG_FLAG_WO,
  29274         0,
  29275         1,
  29276         soc_ECI_SBUS_LAST_IN_CHAIN_BCM83207_A0r_fields,
  29277         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29278         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29279         -1,
  29280         -1,
  29281     },
  29282 #endif /* chips */
  29283 
  29284 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29285     defined(BCM_88754_A0)
  29286     { /* SOC_REG_INT_BRDC_FMACL_SPARE_REGISTER_3r */
  29287         soc_block_list[91],
  29288         soc_genreg,
  29289         1,
  29290         0,
  29291         0x53,
  29292         SOC_REG_FLAG_WO,
  29293         0,
  29294         2,
  29295         soc_BRDC_FMACH_SPARE_REGISTER_3r_fields,
  29296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29297         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29298         -1,
  29299         -1,
  29300     },
  29301 #endif /* chips */
  29302 
  29303 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29304     defined(BCM_88754_A0)
  29305     { /* SOC_REG_INT_BRDC_FMACL_TEST_CONFIGURATIONr */
  29306         soc_block_list[91],
  29307         soc_genreg,
  29308         4,
  29309         0,
  29310         0x1b0,
  29311         SOC_REG_FLAG_ARRAY |
  29312                           SOC_REG_FLAG_WO |
  29313                           SOC_REG_FLAG_REG_ARRAY,
  29314         0,
  29315         4,
  29316         soc_BRDC_FMACH_TEST_CONFIGURATIONr_fields,
  29317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29318         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  29319         -1,
  29320         -1,
  29321     },
  29322 #endif /* chips */
  29323 
  29324 #if defined(BCM_88750_A0) || defined(BCM_88750_B0) || \
  29325     defined(BCM_88754_A0)
  29326     { /* SOC_REG_INT_BRDC_FMACL_TEST_STATUSr */
  29327         soc_block_list[91],
  29328         soc_genreg,
  29329         4,
  29330         0,
  29331         0x1b4,
  29332         SOC_REG_FLAG_ARRAY |
  29333                           SOC_REG_FLAG_RO |
  29334                           SOC_REG_FLAG_WO |
  29335                           SOC_REG_FLAG_REG_ARRAY,
  29336         0,
  29337         3,
  29338         soc_BRDC_FMACH_TEST_STATUSr_fields,
  29339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29340         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29341         -1,
  29342         -1,
  29343     },
  29344 #endif /* chips */
  29345 
  29346 #if defined(BCM_88750_A0)
  29347     { /* SOC_REG_INT_BRDC_FMACL_TX_CELL_LIMITr */
  29348         soc_block_list[91],
  29349         soc_genreg,
  29350         1,
  29351         0,
  29352         0x67,
  29353         SOC_REG_FLAG_WO,
  29354         0,
  29355         2,
  29356         soc_BRDC_FMACH_TX_CELL_LIMITr_fields,
  29357         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  29358         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29359         -1,
  29360         -1,
  29361     },
  29362 #endif /* chips */
  29363 
  29364 #if defined(BCM_88750_B0) || defined(BCM_88754_A0)
  29365     { /* SOC_REG_INT_BRDC_FMACL_TX_CELL_LIMIT_BCM88750_B0r */
  29366         soc_block_list[91],
  29367         soc_genreg,
  29368         1,
  29369         0,
  29370         0x67,
  29371         SOC_REG_FLAG_WO,
  29372         0,
  29373         2,
  29374         soc_BRDC_FMACH_TX_CELL_LIMIT_BCM88750_B0r_fields,
  29375         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  29376         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29377         -1,
  29378         -1,
  29379     },
  29380 #endif /* chips */
  29381 
  29382 #if defined(BCM_88950_A0)
  29383     { /* SOC_REG_INT_BRDC_FMAC_AC_ASYNC_FIFO_CONFIGURATIONr */
  29384         soc_block_list[102],
  29385         soc_genreg,
  29386         4,
  29387         0,
  29388         0x131,
  29389         SOC_REG_FLAG_64_BITS |
  29390                           SOC_REG_FLAG_ARRAY |
  29391                           SOC_REG_FLAG_WO |
  29392                           SOC_REG_FLAG_REG_ARRAY,
  29393         0,
  29394         16,
  29395         soc_BRDC_FMAC_AC_ASYNC_FIFO_CONFIGURATIONr_fields,
  29396         SOC_RESET_VAL_DEC(0x005401d5, 0x00000000)
  29397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  29398         -1,
  29399         -1,
  29400     },
  29401 #endif /* chips */
  29402 
  29403 #if defined(BCM_88950_A0)
  29404     { /* SOC_REG_INT_BRDC_FMAC_AC_BER_GEN_BITMAPr */
  29405         soc_block_list[102],
  29406         soc_genreg,
  29407         1,
  29408         0,
  29409         0x11b,
  29410         SOC_REG_FLAG_64_BITS |
  29411                           SOC_REG_FLAG_WO,
  29412         0,
  29413         1,
  29414         soc_BRDC_FMAC_AC_BER_GEN_BITMAPr_fields,
  29415         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  29416         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  29417         -1,
  29418         -1,
  29419     },
  29420 #endif /* chips */
  29421 
  29422 #if defined(BCM_88950_A0)
  29423     { /* SOC_REG_INT_BRDC_FMAC_AC_BER_GEN_PERIODr */
  29424         soc_block_list[102],
  29425         soc_genreg,
  29426         1,
  29427         0,
  29428         0x11a,
  29429         SOC_REG_FLAG_WO,
  29430         0,
  29431         1,
  29432         soc_BRDC_FMAC_AC_BER_GEN_PERIODr_fields,
  29433         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  29434         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29435         -1,
  29436         -1,
  29437     },
  29438 #endif /* chips */
  29439 
  29440 #if defined(BCM_88950_A0)
  29441     { /* SOC_REG_INT_BRDC_FMAC_AC_FBIST_CONFIGURATION_Ar */
  29442         soc_block_list[102],
  29443         soc_genreg,
  29444         1,
  29445         0,
  29446         0x1da,
  29447         SOC_REG_FLAG_WO,
  29448         0,
  29449         8,
  29450         soc_BRDC_FMAC_AC_FBIST_CONFIGURATION_Ar_fields,
  29451         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  29452         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  29453         -1,
  29454         -1,
  29455     },
  29456 #endif /* chips */
  29457 
  29458 #if defined(BCM_88950_A0)
  29459     { /* SOC_REG_INT_BRDC_FMAC_AC_FBIST_CONFIGURATION_Br */
  29460         soc_block_list[102],
  29461         soc_genreg,
  29462         1,
  29463         0,
  29464         0x1db,
  29465         SOC_REG_FLAG_WO,
  29466         0,
  29467         1,
  29468         soc_BRDC_FMAC_AC_FBIST_CONFIGURATION_Br_fields,
  29469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29470         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  29471         -1,
  29472         -1,
  29473     },
  29474 #endif /* chips */
  29475 
  29476 #if defined(BCM_88950_A0)
  29477     { /* SOC_REG_INT_BRDC_FMAC_AC_FBIST_STATUSr */
  29478         soc_block_list[102],
  29479         soc_genreg,
  29480         1,
  29481         0,
  29482         0x1dc,
  29483         SOC_REG_FLAG_RO |
  29484                           SOC_REG_FLAG_WO,
  29485         0,
  29486         1,
  29487         soc_BRDC_FMAC_AC_FBIST_STATUSr_fields,
  29488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29489         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  29490         -1,
  29491         -1,
  29492     },
  29493 #endif /* chips */
  29494 
  29495 #if defined(BCM_88950_A0)
  29496     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_1r */
  29497         soc_block_list[102],
  29498         soc_genreg,
  29499         1,
  29500         0,
  29501         0x211,
  29502         SOC_REG_FLAG_WO,
  29503         0,
  29504         2,
  29505         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_1r_fields,
  29506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29507         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29508         -1,
  29509         -1,
  29510     },
  29511 #endif /* chips */
  29512 
  29513 #if defined(BCM_88950_A0)
  29514     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_2r */
  29515         soc_block_list[102],
  29516         soc_genreg,
  29517         1,
  29518         0,
  29519         0x212,
  29520         SOC_REG_FLAG_WO,
  29521         0,
  29522         2,
  29523         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_2r_fields,
  29524         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29525         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29526         -1,
  29527         -1,
  29528     },
  29529 #endif /* chips */
  29530 
  29531 #if defined(BCM_88950_A0)
  29532     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_3r */
  29533         soc_block_list[102],
  29534         soc_genreg,
  29535         1,
  29536         0,
  29537         0x213,
  29538         SOC_REG_FLAG_WO,
  29539         0,
  29540         2,
  29541         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_3r_fields,
  29542         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29543         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29544         -1,
  29545         -1,
  29546     },
  29547 #endif /* chips */
  29548 
  29549 #if defined(BCM_88950_A0)
  29550     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_4r */
  29551         soc_block_list[102],
  29552         soc_genreg,
  29553         1,
  29554         0,
  29555         0x214,
  29556         SOC_REG_FLAG_WO,
  29557         0,
  29558         2,
  29559         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_4r_fields,
  29560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29561         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29562         -1,
  29563         -1,
  29564     },
  29565 #endif /* chips */
  29566 
  29567 #if defined(BCM_88950_A0)
  29568     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_5r */
  29569         soc_block_list[102],
  29570         soc_genreg,
  29571         1,
  29572         0,
  29573         0x215,
  29574         SOC_REG_FLAG_WO,
  29575         0,
  29576         2,
  29577         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_5r_fields,
  29578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29579         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29580         -1,
  29581         -1,
  29582     },
  29583 #endif /* chips */
  29584 
  29585 #if defined(BCM_88950_A0)
  29586     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_6r */
  29587         soc_block_list[102],
  29588         soc_genreg,
  29589         1,
  29590         0,
  29591         0x216,
  29592         SOC_REG_FLAG_WO,
  29593         0,
  29594         2,
  29595         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_6r_fields,
  29596         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29597         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29598         -1,
  29599         -1,
  29600     },
  29601 #endif /* chips */
  29602 
  29603 #if defined(BCM_88950_A0)
  29604     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_7r */
  29605         soc_block_list[102],
  29606         soc_genreg,
  29607         1,
  29608         0,
  29609         0x217,
  29610         SOC_REG_FLAG_WO,
  29611         0,
  29612         2,
  29613         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_7r_fields,
  29614         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29615         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29616         -1,
  29617         -1,
  29618     },
  29619 #endif /* chips */
  29620 
  29621 #if defined(BCM_88950_A0)
  29622     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_8r */
  29623         soc_block_list[102],
  29624         soc_genreg,
  29625         1,
  29626         0,
  29627         0x218,
  29628         SOC_REG_FLAG_WO,
  29629         0,
  29630         3,
  29631         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_8r_fields,
  29632         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29633         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  29634         -1,
  29635         -1,
  29636     },
  29637 #endif /* chips */
  29638 
  29639 #if defined(BCM_88950_A0)
  29640     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1r */
  29641         soc_block_list[102],
  29642         soc_genreg,
  29643         1,
  29644         0,
  29645         0x201,
  29646         SOC_REG_FLAG_WO |
  29647                           SOC_REG_FLAG_INTERRUPT,
  29648         0,
  29649         2,
  29650         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1r_fields,
  29651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29652         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29653         -1,
  29654         -1,
  29655     },
  29656 #endif /* chips */
  29657 
  29658 #if defined(BCM_88950_A0)
  29659     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2r */
  29660         soc_block_list[102],
  29661         soc_genreg,
  29662         1,
  29663         0,
  29664         0x202,
  29665         SOC_REG_FLAG_WO |
  29666                           SOC_REG_FLAG_INTERRUPT,
  29667         0,
  29668         2,
  29669         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2r_fields,
  29670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29671         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29672         -1,
  29673         -1,
  29674     },
  29675 #endif /* chips */
  29676 
  29677 #if defined(BCM_88950_A0)
  29678     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3r */
  29679         soc_block_list[102],
  29680         soc_genreg,
  29681         1,
  29682         0,
  29683         0x203,
  29684         SOC_REG_FLAG_WO |
  29685                           SOC_REG_FLAG_INTERRUPT,
  29686         0,
  29687         2,
  29688         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3r_fields,
  29689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29690         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29691         -1,
  29692         -1,
  29693     },
  29694 #endif /* chips */
  29695 
  29696 #if defined(BCM_88950_A0)
  29697     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4r */
  29698         soc_block_list[102],
  29699         soc_genreg,
  29700         1,
  29701         0,
  29702         0x204,
  29703         SOC_REG_FLAG_WO |
  29704                           SOC_REG_FLAG_INTERRUPT,
  29705         0,
  29706         2,
  29707         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4r_fields,
  29708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29709         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29710         -1,
  29711         -1,
  29712     },
  29713 #endif /* chips */
  29714 
  29715 #if defined(BCM_88950_A0)
  29716     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5r */
  29717         soc_block_list[102],
  29718         soc_genreg,
  29719         1,
  29720         0,
  29721         0x205,
  29722         SOC_REG_FLAG_WO |
  29723                           SOC_REG_FLAG_INTERRUPT,
  29724         0,
  29725         2,
  29726         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5r_fields,
  29727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29728         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29729         -1,
  29730         -1,
  29731     },
  29732 #endif /* chips */
  29733 
  29734 #if defined(BCM_88950_A0)
  29735     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6r */
  29736         soc_block_list[102],
  29737         soc_genreg,
  29738         1,
  29739         0,
  29740         0x206,
  29741         SOC_REG_FLAG_WO |
  29742                           SOC_REG_FLAG_INTERRUPT,
  29743         0,
  29744         2,
  29745         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6r_fields,
  29746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29747         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29748         -1,
  29749         -1,
  29750     },
  29751 #endif /* chips */
  29752 
  29753 #if defined(BCM_88950_A0)
  29754     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7r */
  29755         soc_block_list[102],
  29756         soc_genreg,
  29757         1,
  29758         0,
  29759         0x207,
  29760         SOC_REG_FLAG_WO |
  29761                           SOC_REG_FLAG_INTERRUPT,
  29762         0,
  29763         2,
  29764         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7r_fields,
  29765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29766         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29767         -1,
  29768         -1,
  29769     },
  29770 #endif /* chips */
  29771 
  29772 #if defined(BCM_88950_A0)
  29773     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8r */
  29774         soc_block_list[102],
  29775         soc_genreg,
  29776         1,
  29777         0,
  29778         0x208,
  29779         SOC_REG_FLAG_WO |
  29780                           SOC_REG_FLAG_INTERRUPT,
  29781         0,
  29782         3,
  29783         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8r_fields,
  29784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29785         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  29786         -1,
  29787         -1,
  29788     },
  29789 #endif /* chips */
  29790 
  29791 #if defined(BCM_88950_A0)
  29792     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1_TESTr */
  29793         soc_block_list[102],
  29794         soc_genreg,
  29795         1,
  29796         0,
  29797         0x221,
  29798         SOC_REG_FLAG_WO,
  29799         0,
  29800         1,
  29801         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1_TESTr_fields,
  29802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29804         -1,
  29805         -1,
  29806     },
  29807 #endif /* chips */
  29808 
  29809 #if defined(BCM_88950_A0)
  29810     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2_TESTr */
  29811         soc_block_list[102],
  29812         soc_genreg,
  29813         1,
  29814         0,
  29815         0x222,
  29816         SOC_REG_FLAG_WO,
  29817         0,
  29818         1,
  29819         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2_TESTr_fields,
  29820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29822         -1,
  29823         -1,
  29824     },
  29825 #endif /* chips */
  29826 
  29827 #if defined(BCM_88950_A0)
  29828     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3_TESTr */
  29829         soc_block_list[102],
  29830         soc_genreg,
  29831         1,
  29832         0,
  29833         0x223,
  29834         SOC_REG_FLAG_WO,
  29835         0,
  29836         1,
  29837         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3_TESTr_fields,
  29838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29840         -1,
  29841         -1,
  29842     },
  29843 #endif /* chips */
  29844 
  29845 #if defined(BCM_88950_A0)
  29846     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4_TESTr */
  29847         soc_block_list[102],
  29848         soc_genreg,
  29849         1,
  29850         0,
  29851         0x224,
  29852         SOC_REG_FLAG_WO,
  29853         0,
  29854         1,
  29855         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4_TESTr_fields,
  29856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29858         -1,
  29859         -1,
  29860     },
  29861 #endif /* chips */
  29862 
  29863 #if defined(BCM_88950_A0)
  29864     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5_TESTr */
  29865         soc_block_list[102],
  29866         soc_genreg,
  29867         1,
  29868         0,
  29869         0x225,
  29870         SOC_REG_FLAG_WO,
  29871         0,
  29872         1,
  29873         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5_TESTr_fields,
  29874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29876         -1,
  29877         -1,
  29878     },
  29879 #endif /* chips */
  29880 
  29881 #if defined(BCM_88950_A0)
  29882     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6_TESTr */
  29883         soc_block_list[102],
  29884         soc_genreg,
  29885         1,
  29886         0,
  29887         0x226,
  29888         SOC_REG_FLAG_WO,
  29889         0,
  29890         1,
  29891         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6_TESTr_fields,
  29892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29894         -1,
  29895         -1,
  29896     },
  29897 #endif /* chips */
  29898 
  29899 #if defined(BCM_88950_A0)
  29900     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7_TESTr */
  29901         soc_block_list[102],
  29902         soc_genreg,
  29903         1,
  29904         0,
  29905         0x227,
  29906         SOC_REG_FLAG_WO,
  29907         0,
  29908         1,
  29909         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7_TESTr_fields,
  29910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29912         -1,
  29913         -1,
  29914     },
  29915 #endif /* chips */
  29916 
  29917 #if defined(BCM_88950_A0)
  29918     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8_TESTr */
  29919         soc_block_list[102],
  29920         soc_genreg,
  29921         1,
  29922         0,
  29923         0x228,
  29924         SOC_REG_FLAG_WO,
  29925         0,
  29926         1,
  29927         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8_TESTr_fields,
  29928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29929         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  29930         -1,
  29931         -1,
  29932     },
  29933 #endif /* chips */
  29934 
  29935 #if defined(BCM_88950_A0)
  29936     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_GENERAL_CONFIGURATIONr */
  29937         soc_block_list[102],
  29938         soc_genreg,
  29939         4,
  29940         0,
  29941         0x11d,
  29942         SOC_REG_FLAG_ARRAY |
  29943                           SOC_REG_FLAG_WO |
  29944                           SOC_REG_FLAG_REG_ARRAY,
  29945         0,
  29946         6,
  29947         soc_BRDC_FMAC_AC_FMAL_GENERAL_CONFIGURATIONr_fields,
  29948         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  29949         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  29950         -1,
  29951         -1,
  29952     },
  29953 #endif /* chips */
  29954 
  29955 #if defined(BCM_88950_A0)
  29956     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_RX_GENERAL_CONFIGURATIONr */
  29957         soc_block_list[102],
  29958         soc_genreg,
  29959         4,
  29960         0,
  29961         0x125,
  29962         SOC_REG_FLAG_ARRAY |
  29963                           SOC_REG_FLAG_WO |
  29964                           SOC_REG_FLAG_REG_ARRAY,
  29965         0,
  29966         8,
  29967         soc_BRDC_FMAC_AC_FMAL_RX_GENERAL_CONFIGURATIONr_fields,
  29968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29969         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  29970         -1,
  29971         -1,
  29972     },
  29973 #endif /* chips */
  29974 
  29975 #if defined(BCM_88950_A0)
  29976     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_STATISTICS_COUNT_CONTROLr */
  29977         soc_block_list[102],
  29978         soc_genreg,
  29979         1,
  29980         0,
  29981         0x110,
  29982         SOC_REG_FLAG_WO,
  29983         0,
  29984         2,
  29985         soc_BRDC_FMAC_AC_FMAL_STATISTICS_COUNT_CONTROLr_fields,
  29986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  29987         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  29988         -1,
  29989         -1,
  29990     },
  29991 #endif /* chips */
  29992 
  29993 #if defined(BCM_88950_A0)
  29994     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_STATISTICS_GTIMERr */
  29995         soc_block_list[102],
  29996         soc_genreg,
  29997         1,
  29998         0,
  29999         0x111,
  30000         SOC_REG_FLAG_64_BITS |
  30001                           SOC_REG_FLAG_WO,
  30002         0,
  30003         4,
  30004         soc_BRDC_FMAC_AC_FMAL_STATISTICS_GTIMERr_fields,
  30005         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  30006         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  30007         -1,
  30008         -1,
  30009     },
  30010 #endif /* chips */
  30011 
  30012 #if defined(BCM_88950_A0)
  30013     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_STATISTICS_OUTPUT_CONTROLr */
  30014         soc_block_list[102],
  30015         soc_genreg,
  30016         1,
  30017         0,
  30018         0x113,
  30019         SOC_REG_FLAG_WO,
  30020         0,
  30021         5,
  30022         soc_BRDC_FMAC_AC_FMAL_STATISTICS_OUTPUT_CONTROLr_fields,
  30023         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  30024         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  30025         -1,
  30026         -1,
  30027     },
  30028 #endif /* chips */
  30029 
  30030 #if defined(BCM_88950_A0)
  30031     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_TX_COMMA_BURST_CONFIGURATIONr */
  30032         soc_block_list[102],
  30033         soc_genreg,
  30034         4,
  30035         0,
  30036         0x129,
  30037         SOC_REG_FLAG_ARRAY |
  30038                           SOC_REG_FLAG_WO |
  30039                           SOC_REG_FLAG_REG_ARRAY,
  30040         0,
  30041         6,
  30042         soc_BRDC_FMAC_AC_FMAL_TX_COMMA_BURST_CONFIGURATIONr_fields,
  30043         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  30044         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  30045         -1,
  30046         -1,
  30047     },
  30048 #endif /* chips */
  30049 
  30050 #if defined(BCM_88950_A0)
  30051     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_TX_CONTROL_BURST_CONFIGURATIONr */
  30052         soc_block_list[102],
  30053         soc_genreg,
  30054         4,
  30055         0,
  30056         0x12d,
  30057         SOC_REG_FLAG_ARRAY |
  30058                           SOC_REG_FLAG_WO |
  30059                           SOC_REG_FLAG_REG_ARRAY,
  30060         0,
  30061         2,
  30062         soc_BRDC_FMAC_AC_FMAL_TX_CONTROL_BURST_CONFIGURATIONr_fields,
  30063         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  30064         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  30065         -1,
  30066         -1,
  30067     },
  30068 #endif /* chips */
  30069 
  30070 #if defined(BCM_88950_A0)
  30071     { /* SOC_REG_INT_BRDC_FMAC_AC_FMAL_TX_GENERAL_CONFIGURATIONr */
  30072         soc_block_list[102],
  30073         soc_genreg,
  30074         4,
  30075         0,
  30076         0x121,
  30077         SOC_REG_FLAG_ARRAY |
  30078                           SOC_REG_FLAG_WO |
  30079                           SOC_REG_FLAG_REG_ARRAY,
  30080         0,
  30081         11,
  30082         soc_BRDC_FMAC_AC_FMAL_TX_GENERAL_CONFIGURATIONr_fields,
  30083         SOC_RESET_VAL_DEC(0x04060008, 0x00000000)
  30084         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30085         -1,
  30086         -1,
  30087     },
  30088 #endif /* chips */
  30089 
  30090 #if defined(BCM_88950_A0)
  30091     { /* SOC_REG_INT_BRDC_FMAC_AC_FPS_CONFIGURATION_BERr */
  30092         soc_block_list[102],
  30093         soc_genreg,
  30094         4,
  30095         0,
  30096         0x13d,
  30097         SOC_REG_FLAG_ARRAY |
  30098                           SOC_REG_FLAG_WO |
  30099                           SOC_REG_FLAG_REG_ARRAY,
  30100         0,
  30101         6,
  30102         soc_BRDC_FMAC_AC_FPS_CONFIGURATION_BERr_fields,
  30103         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  30104         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  30105         -1,
  30106         -1,
  30107     },
  30108 #endif /* chips */
  30109 
  30110 #if defined(BCM_88950_A0)
  30111     { /* SOC_REG_INT_BRDC_FMAC_AC_FPS_CONFIGURATION_RX_SYNCr */
  30112         soc_block_list[102],
  30113         soc_genreg,
  30114         4,
  30115         0,
  30116         0x141,
  30117         SOC_REG_FLAG_ARRAY |
  30118                           SOC_REG_FLAG_WO |
  30119                           SOC_REG_FLAG_REG_ARRAY,
  30120         0,
  30121         7,
  30122         soc_BRDC_FMAC_AC_FPS_CONFIGURATION_RX_SYNCr_fields,
  30123         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  30124         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  30125         -1,
  30126         -1,
  30127     },
  30128 #endif /* chips */
  30129 
  30130 #if defined(BCM_88950_A0)
  30131     { /* SOC_REG_INT_BRDC_FMAC_AC_FPS_RX_FEC_CONFIGURATIONr */
  30132         soc_block_list[102],
  30133         soc_genreg,
  30134         4,
  30135         0,
  30136         0x145,
  30137         SOC_REG_FLAG_ARRAY |
  30138                           SOC_REG_FLAG_WO |
  30139                           SOC_REG_FLAG_REG_ARRAY,
  30140         0,
  30141         17,
  30142         soc_BRDC_FMAC_AC_FPS_RX_FEC_CONFIGURATIONr_fields,
  30143         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  30144         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30145         -1,
  30146         -1,
  30147     },
  30148 #endif /* chips */
  30149 
  30150 #if defined(BCM_88950_A0)
  30151     { /* SOC_REG_INT_BRDC_FMAC_AC_FPS_RX_STATUSr */
  30152         soc_block_list[102],
  30153         soc_genreg,
  30154         4,
  30155         0,
  30156         0x14d,
  30157         SOC_REG_FLAG_ARRAY |
  30158                           SOC_REG_FLAG_RO |
  30159                           SOC_REG_FLAG_WO |
  30160                           SOC_REG_FLAG_REG_ARRAY,
  30161         0,
  30162         7,
  30163         soc_BRDC_FMAC_AC_FPS_RX_STATUSr_fields,
  30164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30165         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  30166         -1,
  30167         -1,
  30168     },
  30169 #endif /* chips */
  30170 
  30171 #if defined(BCM_88950_A0)
  30172     { /* SOC_REG_INT_BRDC_FMAC_AC_FPS_TX_CONFIGURATIONr */
  30173         soc_block_list[102],
  30174         soc_genreg,
  30175         4,
  30176         0,
  30177         0x149,
  30178         SOC_REG_FLAG_ARRAY |
  30179                           SOC_REG_FLAG_WO |
  30180                           SOC_REG_FLAG_REG_ARRAY,
  30181         0,
  30182         9,
  30183         soc_BRDC_FMAC_AC_FPS_TX_CONFIGURATIONr_fields,
  30184         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  30185         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  30186         -1,
  30187         -1,
  30188     },
  30189 #endif /* chips */
  30190 
  30191 #if defined(BCM_88950_A0)
  30192     { /* SOC_REG_INT_BRDC_FMAC_AC_GENERAL_CONFIGURATION_REGISTERr */
  30193         soc_block_list[102],
  30194         soc_genreg,
  30195         1,
  30196         0,
  30197         0x103,
  30198         SOC_REG_FLAG_WO,
  30199         0,
  30200         15,
  30201         soc_BRDC_FMAC_AC_GENERAL_CONFIGURATION_REGISTERr_fields,
  30202         SOC_RESET_VAL_DEC(0x000060f3, 0x00000000)
  30203         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  30204         -1,
  30205         -1,
  30206     },
  30207 #endif /* chips */
  30208 
  30209 #if defined(BCM_88950_A0)
  30210     { /* SOC_REG_INT_BRDC_FMAC_AC_GLOBAL_GENERAL_CFG_1r */
  30211         soc_block_list[102],
  30212         soc_genreg,
  30213         1,
  30214         0,
  30215         0xc1,
  30216         SOC_REG_FLAG_WO,
  30217         0,
  30218         3,
  30219         soc_BRDC_DCH_GLOBAL_GENERAL_CFG_1r_fields,
  30220         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  30221         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  30222         -1,
  30223         -1,
  30224     },
  30225 #endif /* chips */
  30226 
  30227 #if defined(BCM_88950_A0)
  30228     { /* SOC_REG_INT_BRDC_FMAC_AC_GLOBAL_GENERAL_FE_CFG_1r */
  30229         soc_block_list[102],
  30230         soc_genreg,
  30231         1,
  30232         0,
  30233         0xf4,
  30234         SOC_REG_FLAG_WO,
  30235         0,
  30236         8,
  30237         soc_BRDC_DCH_GLOBAL_GENERAL_FE_CFG_1r_fields,
  30238         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  30239         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  30240         -1,
  30241         -1,
  30242     },
  30243 #endif /* chips */
  30244 
  30245 #if defined(BCM_88950_A0)
  30246     { /* SOC_REG_INT_BRDC_FMAC_AC_GLOBAL_MEM_OPTIONSr */
  30247         soc_block_list[102],
  30248         soc_genreg,
  30249         1,
  30250         0,
  30251         0xc0,
  30252         SOC_REG_FLAG_WO,
  30253         0,
  30254         3,
  30255         soc_BRDC_DCH_GLOBAL_MEM_OPTIONSr_fields,
  30256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30257         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  30258         -1,
  30259         -1,
  30260     },
  30261 #endif /* chips */
  30262 
  30263 #if defined(BCM_88950_A0)
  30264     { /* SOC_REG_INT_BRDC_FMAC_AC_GLOBAL_TEST_RX_IDL_PTRNr */
  30265         soc_block_list[102],
  30266         soc_genreg,
  30267         1,
  30268         0,
  30269         0x1d7,
  30270         SOC_REG_FLAG_ABOVE_64_BITS |
  30271                           SOC_REG_FLAG_WO,
  30272         0,
  30273         1,
  30274         soc_BRDC_FMAC_AC_GLOBAL_TEST_RX_IDL_PTRNr_fields,
  30275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30277         -1,
  30278         -1,
  30279     },
  30280 #endif /* chips */
  30281 
  30282 #if defined(BCM_88950_A0)
  30283     { /* SOC_REG_INT_BRDC_FMAC_AC_GLOBAL_TEST_TX_IDL_PTRNr */
  30284         soc_block_list[102],
  30285         soc_genreg,
  30286         1,
  30287         0,
  30288         0x1d4,
  30289         SOC_REG_FLAG_ABOVE_64_BITS |
  30290                           SOC_REG_FLAG_WO,
  30291         0,
  30292         1,
  30293         soc_BRDC_FMAC_AC_GLOBAL_TEST_TX_IDL_PTRNr_fields,
  30294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  30296         -1,
  30297         -1,
  30298     },
  30299 #endif /* chips */
  30300 
  30301 #if defined(BCM_88950_A0)
  30302     { /* SOC_REG_INT_BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_Ar */
  30303         soc_block_list[102],
  30304         soc_genreg,
  30305         1,
  30306         0,
  30307         0x1d0,
  30308         SOC_REG_FLAG_64_BITS |
  30309                           SOC_REG_FLAG_WO,
  30310         0,
  30311         1,
  30312         soc_BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_Ar_fields,
  30313         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  30314         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  30315         -1,
  30316         -1,
  30317     },
  30318 #endif /* chips */
  30319 
  30320 #if defined(BCM_88950_A0)
  30321     { /* SOC_REG_INT_BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_Br */
  30322         soc_block_list[102],
  30323         soc_genreg,
  30324         1,
  30325         0,
  30326         0x1d2,
  30327         SOC_REG_FLAG_64_BITS |
  30328                           SOC_REG_FLAG_WO,
  30329         0,
  30330         1,
  30331         soc_BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_Br_fields,
  30332         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  30333         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  30334         -1,
  30335         -1,
  30336     },
  30337 #endif /* chips */
  30338 
  30339 #if defined(BCM_88950_A0)
  30340     { /* SOC_REG_INT_BRDC_FMAC_AC_GRACEFULL_POWER_ON_OFFr */
  30341         soc_block_list[102],
  30342         soc_genreg,
  30343         1,
  30344         0,
  30345         0x105,
  30346         SOC_REG_FLAG_WO,
  30347         0,
  30348         3,
  30349         soc_BRDC_FMAC_AC_GRACEFULL_POWER_ON_OFFr_fields,
  30350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30351         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  30352         -1,
  30353         -1,
  30354     },
  30355 #endif /* chips */
  30356 
  30357 #if defined(BCM_88950_A0)
  30358     { /* SOC_REG_INT_BRDC_FMAC_AC_GTIMER_CONFIGURATIONr */
  30359         soc_block_list[102],
  30360         soc_genreg,
  30361         1,
  30362         0,
  30363         0x88,
  30364         SOC_REG_FLAG_WO,
  30365         0,
  30366         3,
  30367         soc_BRDC_CCS_GTIMER_CONFIGURATIONr_fields,
  30368         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  30369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30370         -1,
  30371         -1,
  30372     },
  30373 #endif /* chips */
  30374 
  30375 #if defined(BCM_88950_A0)
  30376     { /* SOC_REG_INT_BRDC_FMAC_AC_GTIMER_TRIGGERr */
  30377         soc_block_list[102],
  30378         soc_genreg,
  30379         1,
  30380         0,
  30381         0x89,
  30382         SOC_REG_FLAG_RO |
  30383                           SOC_REG_FLAG_WO,
  30384         0,
  30385         1,
  30386         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  30387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30388         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30389         -1,
  30390         -1,
  30391     },
  30392 #endif /* chips */
  30393 
  30394 #if defined(BCM_88950_A0)
  30395     { /* SOC_REG_INT_BRDC_FMAC_AC_INTERRUPT_MASK_REGISTERr */
  30396         soc_block_list[102],
  30397         soc_genreg,
  30398         1,
  30399         0,
  30400         0x10,
  30401         SOC_REG_FLAG_WO,
  30402         0,
  30403         9,
  30404         soc_BRDC_FMAC_AC_INTERRUPT_MASK_REGISTERr_fields,
  30405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30406         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  30407         -1,
  30408         -1,
  30409     },
  30410 #endif /* chips */
  30411 
  30412 #if defined(BCM_88950_A0)
  30413     { /* SOC_REG_INT_BRDC_FMAC_AC_INTERRUPT_REGISTERr */
  30414         soc_block_list[102],
  30415         soc_genreg,
  30416         1,
  30417         0,
  30418         0,
  30419         SOC_REG_FLAG_RO |
  30420                           SOC_REG_FLAG_WO |
  30421                           SOC_REG_FLAG_INTERRUPT,
  30422         0,
  30423         9,
  30424         soc_BRDC_FMAC_AC_INTERRUPT_REGISTERr_fields,
  30425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30426         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  30427         -1,
  30428         -1,
  30429     },
  30430 #endif /* chips */
  30431 
  30432 #if defined(BCM_88950_A0)
  30433     { /* SOC_REG_INT_BRDC_FMAC_AC_INTERRUPT_REGISTER_TESTr */
  30434         soc_block_list[102],
  30435         soc_genreg,
  30436         1,
  30437         0,
  30438         0x18,
  30439         SOC_REG_FLAG_WO,
  30440         0,
  30441         1,
  30442         soc_BRDC_CCS_INTERRUPT_REGISTER_TESTr_fields,
  30443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30444         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30445         -1,
  30446         -1,
  30447     },
  30448 #endif /* chips */
  30449 
  30450 #if defined(BCM_88950_A0)
  30451     { /* SOC_REG_INT_BRDC_FMAC_AC_KPCS_CONFIGURATIONr */
  30452         soc_block_list[102],
  30453         soc_genreg,
  30454         4,
  30455         0,
  30456         0x160,
  30457         SOC_REG_FLAG_ARRAY |
  30458                           SOC_REG_FLAG_WO |
  30459                           SOC_REG_FLAG_REG_ARRAY,
  30460         0,
  30461         11,
  30462         soc_BRDC_FMAC_AC_KPCS_CONFIGURATIONr_fields,
  30463         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  30464         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  30465         -1,
  30466         -1,
  30467     },
  30468 #endif /* chips */
  30469 
  30470 #if defined(BCM_88950_A0)
  30471     { /* SOC_REG_INT_BRDC_FMAC_AC_KPCS_RX_STATUSr */
  30472         soc_block_list[102],
  30473         soc_genreg,
  30474         4,
  30475         0,
  30476         0x164,
  30477         SOC_REG_FLAG_ARRAY |
  30478                           SOC_REG_FLAG_RO |
  30479                           SOC_REG_FLAG_WO |
  30480                           SOC_REG_FLAG_REG_ARRAY,
  30481         0,
  30482         2,
  30483         soc_BRDC_FMAC_AC_KPCS_RX_STATUSr_fields,
  30484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30485         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  30486         -1,
  30487         -1,
  30488     },
  30489 #endif /* chips */
  30490 
  30491 #if defined(BCM_88950_A0)
  30492     { /* SOC_REG_INT_BRDC_FMAC_AC_KPCS_TEST_RX_CONFIGURATIONr */
  30493         soc_block_list[102],
  30494         soc_genreg,
  30495         4,
  30496         0,
  30497         0x180,
  30498         SOC_REG_FLAG_ARRAY |
  30499                           SOC_REG_FLAG_WO |
  30500                           SOC_REG_FLAG_REG_ARRAY,
  30501         0,
  30502         4,
  30503         soc_BRDC_FMAC_AC_KPCS_TEST_RX_CONFIGURATIONr_fields,
  30504         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  30505         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  30506         -1,
  30507         -1,
  30508     },
  30509 #endif /* chips */
  30510 
  30511 #if defined(BCM_88950_A0)
  30512     { /* SOC_REG_INT_BRDC_FMAC_AC_KPCS_TEST_RX_STATUSr */
  30513         soc_block_list[102],
  30514         soc_genreg,
  30515         4,
  30516         0,
  30517         0x190,
  30518         SOC_REG_FLAG_ARRAY |
  30519                           SOC_REG_FLAG_RO |
  30520                           SOC_REG_FLAG_WO |
  30521                           SOC_REG_FLAG_REG_ARRAY,
  30522         0,
  30523         1,
  30524         soc_BRDC_FMAC_AC_KPCS_TEST_RX_STATUSr_fields,
  30525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30526         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30527         -1,
  30528         -1,
  30529     },
  30530 #endif /* chips */
  30531 
  30532 #if defined(BCM_88950_A0)
  30533     { /* SOC_REG_INT_BRDC_FMAC_AC_KPCS_TEST_TX_CONFIGURATIONr */
  30534         soc_block_list[102],
  30535         soc_genreg,
  30536         4,
  30537         0,
  30538         0x170,
  30539         SOC_REG_FLAG_ARRAY |
  30540                           SOC_REG_FLAG_WO |
  30541                           SOC_REG_FLAG_REG_ARRAY,
  30542         0,
  30543         7,
  30544         soc_BRDC_FMAC_AC_KPCS_TEST_TX_CONFIGURATIONr_fields,
  30545         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  30546         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  30547         -1,
  30548         -1,
  30549     },
  30550 #endif /* chips */
  30551 
  30552 #if defined(BCM_88950_A0)
  30553     { /* SOC_REG_INT_BRDC_FMAC_AC_LEAKY_BUCKETr */
  30554         soc_block_list[102],
  30555         soc_genreg,
  30556         4,
  30557         0,
  30558         0x10c,
  30559         SOC_REG_FLAG_ARRAY |
  30560                           SOC_REG_FLAG_RO |
  30561                           SOC_REG_FLAG_WO |
  30562                           SOC_REG_FLAG_REG_ARRAY,
  30563         0,
  30564         2,
  30565         soc_BRDC_FMAC_AC_LEAKY_BUCKETr_fields,
  30566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30567         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  30568         -1,
  30569         -1,
  30570     },
  30571 #endif /* chips */
  30572 
  30573 #if defined(BCM_88950_A0)
  30574     { /* SOC_REG_INT_BRDC_FMAC_AC_LEAKY_BUCKET_CONTROL_REGISTERr */
  30575         soc_block_list[102],
  30576         soc_genreg,
  30577         1,
  30578         0,
  30579         0x104,
  30580         SOC_REG_FLAG_WO,
  30581         0,
  30582         6,
  30583         soc_BRDC_FMAC_AC_LEAKY_BUCKET_CONTROL_REGISTERr_fields,
  30584         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  30585         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  30586         -1,
  30587         -1,
  30588     },
  30589 #endif /* chips */
  30590 
  30591 #if defined(BCM_88950_A0)
  30592     { /* SOC_REG_INT_BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr */
  30593         soc_block_list[102],
  30594         soc_genreg,
  30595         1,
  30596         0,
  30597         0x107,
  30598         SOC_REG_FLAG_WO,
  30599         0,
  30600         4,
  30601         soc_BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr_fields,
  30602         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  30603         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  30604         -1,
  30605         -1,
  30606     },
  30607 #endif /* chips */
  30608 
  30609 #if defined(BCM_88950_A0)
  30610     { /* SOC_REG_INT_BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr */
  30611         soc_block_list[102],
  30612         soc_genreg,
  30613         1,
  30614         0,
  30615         0x101,
  30616         SOC_REG_FLAG_WO,
  30617         0,
  30618         2,
  30619         soc_BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr_fields,
  30620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30621         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  30622         -1,
  30623         -1,
  30624     },
  30625 #endif /* chips */
  30626 
  30627 #if defined(BCM_88950_A0)
  30628     { /* SOC_REG_INT_BRDC_FMAC_AC_LINK_TOPO_MODE_REG_0r */
  30629         soc_block_list[102],
  30630         soc_genreg,
  30631         1,
  30632         0,
  30633         0x108,
  30634         SOC_REG_FLAG_WO,
  30635         0,
  30636         2,
  30637         soc_BRDC_FMAC_AC_LINK_TOPO_MODE_REG_0r_fields,
  30638         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  30639         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  30640         -1,
  30641         -1,
  30642     },
  30643 #endif /* chips */
  30644 
  30645 #if defined(BCM_88950_A0)
  30646     { /* SOC_REG_INT_BRDC_FMAC_AC_LINK_TOPO_MODE_REG_2r */
  30647         soc_block_list[102],
  30648         soc_genreg,
  30649         1,
  30650         0,
  30651         0x109,
  30652         SOC_REG_FLAG_WO,
  30653         0,
  30654         1,
  30655         soc_BRDC_FMAC_AC_LINK_TOPO_MODE_REG_2r_fields,
  30656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30657         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  30658         -1,
  30659         -1,
  30660     },
  30661 #endif /* chips */
  30662 
  30663 #if defined(BCM_88950_A0)
  30664     { /* SOC_REG_INT_BRDC_FMAC_AC_LOOPBACK_ENABLE_REGISTERr */
  30665         soc_block_list[102],
  30666         soc_genreg,
  30667         1,
  30668         0,
  30669         0x100,
  30670         SOC_REG_FLAG_WO,
  30671         0,
  30672         1,
  30673         soc_BRDC_FMAC_AC_LOOPBACK_ENABLE_REGISTERr_fields,
  30674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30675         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  30676         -1,
  30677         -1,
  30678     },
  30679 #endif /* chips */
  30680 
  30681 #if defined(BCM_88950_A0)
  30682     { /* SOC_REG_INT_BRDC_FMAC_AC_RECEIVE_RESET_REGISTERr */
  30683         soc_block_list[102],
  30684         soc_genreg,
  30685         1,
  30686         0,
  30687         0x106,
  30688         SOC_REG_FLAG_WO,
  30689         0,
  30690         2,
  30691         soc_BRDC_FMAC_AC_RECEIVE_RESET_REGISTERr_fields,
  30692         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  30693         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  30694         -1,
  30695         -1,
  30696     },
  30697 #endif /* chips */
  30698 
  30699 #if defined(BCM_88950_A0)
  30700     { /* SOC_REG_INT_BRDC_FMAC_AC_REG_0102r */
  30701         soc_block_list[102],
  30702         soc_genreg,
  30703         1,
  30704         0,
  30705         0x102,
  30706         SOC_REG_FLAG_WO,
  30707         0,
  30708         1,
  30709         soc_BRDC_FMAC_AC_REG_0102r_fields,
  30710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30711         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  30712         -1,
  30713         -1,
  30714     },
  30715 #endif /* chips */
  30716 
  30717 #if defined(BCM_88950_A0)
  30718     { /* SOC_REG_INT_BRDC_FMAC_AC_REG_0116r */
  30719         soc_block_list[102],
  30720         soc_genreg,
  30721         1,
  30722         0,
  30723         0x116,
  30724         SOC_REG_FLAG_64_BITS |
  30725                           SOC_REG_FLAG_WO,
  30726         0,
  30727         1,
  30728         soc_BRDC_FMAC_AC_REG_0116r_fields,
  30729         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  30730         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  30731         -1,
  30732         -1,
  30733     },
  30734 #endif /* chips */
  30735 
  30736 #if defined(BCM_88950_A0)
  30737     { /* SOC_REG_INT_BRDC_FMAC_AC_REG_0118r */
  30738         soc_block_list[102],
  30739         soc_genreg,
  30740         1,
  30741         0,
  30742         0x118,
  30743         SOC_REG_FLAG_WO,
  30744         0,
  30745         8,
  30746         soc_BRDC_FMAC_AC_REG_0118r_fields,
  30747         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  30748         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  30749         -1,
  30750         -1,
  30751     },
  30752 #endif /* chips */
  30753 
  30754 #if defined(BCM_88950_A0)
  30755     { /* SOC_REG_INT_BRDC_FMAC_AC_REG_0119r */
  30756         soc_block_list[102],
  30757         soc_genreg,
  30758         1,
  30759         0,
  30760         0x119,
  30761         SOC_REG_FLAG_WO,
  30762         0,
  30763         1,
  30764         soc_BRDC_FMAC_AC_REG_0119r_fields,
  30765         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  30766         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  30767         -1,
  30768         -1,
  30769     },
  30770 #endif /* chips */
  30771 
  30772 #if defined(BCM_88950_A0)
  30773     { /* SOC_REG_INT_BRDC_FMAC_AC_REG_0139r */
  30774         soc_block_list[102],
  30775         soc_genreg,
  30776         4,
  30777         0,
  30778         0x139,
  30779         SOC_REG_FLAG_ARRAY |
  30780                           SOC_REG_FLAG_WO |
  30781                           SOC_REG_FLAG_REG_ARRAY,
  30782         0,
  30783         10,
  30784         soc_BRDC_FMAC_AC_REG_0139r_fields,
  30785         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  30786         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  30787         -1,
  30788         -1,
  30789     },
  30790 #endif /* chips */
  30791 
  30792 #if defined(BCM_88950_A0)
  30793     { /* SOC_REG_INT_BRDC_FMAC_AC_RESERVED_MIRROR_ADDRr */
  30794         soc_block_list[102],
  30795         soc_genreg,
  30796         1,
  30797         0,
  30798         0x85,
  30799         SOC_REG_FLAG_WO,
  30800         0,
  30801         2,
  30802         soc_BRDC_CCS_RESERVED_MIRROR_ADDRr_fields,
  30803         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30804         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  30805         -1,
  30806         -1,
  30807     },
  30808 #endif /* chips */
  30809 
  30810 #if defined(BCM_88950_A0)
  30811     { /* SOC_REG_INT_BRDC_FMAC_AC_RESERVED_MTCPr */
  30812         soc_block_list[102],
  30813         soc_genreg,
  30814         1,
  30815         0,
  30816         0xad,
  30817         SOC_REG_FLAG_64_BITS |
  30818                           SOC_REG_FLAG_WO,
  30819         0,
  30820         18,
  30821         soc_BRDC_CCS_RESERVED_MTCPr_fields,
  30822         SOC_RESET_VAL_DEC(0x80000000, 0x00000001)
  30823         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
  30824         -1,
  30825         -1,
  30826     },
  30827 #endif /* chips */
  30828 
  30829 #if defined(BCM_88950_A0)
  30830     { /* SOC_REG_INT_BRDC_FMAC_AC_RESERVED_SPARE_0r */
  30831         soc_block_list[102],
  30832         soc_genreg,
  30833         1,
  30834         0,
  30835         0x90,
  30836         SOC_REG_FLAG_WO,
  30837         0,
  30838         1,
  30839         soc_BRDC_CCS_RESERVED_SPARE_0r_fields,
  30840         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  30841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30842         -1,
  30843         -1,
  30844     },
  30845 #endif /* chips */
  30846 
  30847 #if defined(BCM_88950_A0)
  30848     { /* SOC_REG_INT_BRDC_FMAC_AC_RESERVED_SPARE_1r */
  30849         soc_block_list[102],
  30850         soc_genreg,
  30851         1,
  30852         0,
  30853         0x91,
  30854         SOC_REG_FLAG_WO,
  30855         0,
  30856         1,
  30857         soc_BRDC_CCS_RESERVED_SPARE_1r_fields,
  30858         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  30859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30860         -1,
  30861         -1,
  30862     },
  30863 #endif /* chips */
  30864 
  30865 #if defined(BCM_88950_A0)
  30866     { /* SOC_REG_INT_BRDC_FMAC_AC_RESERVED_SPARE_2r */
  30867         soc_block_list[102],
  30868         soc_genreg,
  30869         1,
  30870         0,
  30871         0x92,
  30872         SOC_REG_FLAG_WO,
  30873         0,
  30874         1,
  30875         soc_BRDC_CCS_RESERVED_SPARE_2r_fields,
  30876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30878         -1,
  30879         -1,
  30880     },
  30881 #endif /* chips */
  30882 
  30883 #if defined(BCM_88950_A0)
  30884     { /* SOC_REG_INT_BRDC_FMAC_AC_RESERVED_SPARE_3r */
  30885         soc_block_list[102],
  30886         soc_genreg,
  30887         1,
  30888         0,
  30889         0x93,
  30890         SOC_REG_FLAG_WO,
  30891         0,
  30892         1,
  30893         soc_BRDC_CCS_RESERVED_SPARE_3r_fields,
  30894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  30896         -1,
  30897         -1,
  30898     },
  30899 #endif /* chips */
  30900 
  30901 #if defined(BCM_88950_A0)
  30902     { /* SOC_REG_INT_BRDC_FMAC_AC_RSF_CONFIGURATIONr */
  30903         soc_block_list[102],
  30904         soc_genreg,
  30905         4,
  30906         0,
  30907         0x194,
  30908         SOC_REG_FLAG_64_BITS |
  30909                           SOC_REG_FLAG_ARRAY |
  30910                           SOC_REG_FLAG_WO |
  30911                           SOC_REG_FLAG_REG_ARRAY,
  30912         0,
  30913         20,
  30914         soc_BRDC_FMAC_AC_RSF_CONFIGURATIONr_fields,
  30915         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  30916         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  30917         -1,
  30918         -1,
  30919     },
  30920 #endif /* chips */
  30921 
  30922 #if defined(BCM_88950_A0)
  30923     { /* SOC_REG_INT_BRDC_FMAC_AC_RSF_STATUSr */
  30924         soc_block_list[102],
  30925         soc_genreg,
  30926         4,
  30927         0,
  30928         0x19c,
  30929         SOC_REG_FLAG_64_BITS |
  30930                           SOC_REG_FLAG_ARRAY |
  30931                           SOC_REG_FLAG_RO |
  30932                           SOC_REG_FLAG_WO |
  30933                           SOC_REG_FLAG_REG_ARRAY,
  30934         0,
  30935         2,
  30936         soc_BRDC_FMAC_AC_RSF_STATUSr_fields,
  30937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30938         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  30939         -1,
  30940         -1,
  30941     },
  30942 #endif /* chips */
  30943 
  30944 #if defined(BCM_88950_A0)
  30945     { /* SOC_REG_INT_BRDC_FMAC_AC_SBUS_BROADCAST_IDr */
  30946         soc_block_list[102],
  30947         soc_genreg,
  30948         1,
  30949         0,
  30950         0x86,
  30951         SOC_REG_FLAG_WO,
  30952         0,
  30953         1,
  30954         soc_BRDC_FMAC_AC_SBUS_BROADCAST_IDr_fields,
  30955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30956         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  30957         -1,
  30958         -1,
  30959     },
  30960 #endif /* chips */
  30961 
  30962 #if defined(BCM_88950_A0)
  30963     { /* SOC_REG_INT_BRDC_FMAC_AC_SBUS_LAST_IN_CHAINr */
  30964         soc_block_list[102],
  30965         soc_genreg,
  30966         1,
  30967         0,
  30968         0x87,
  30969         SOC_REG_FLAG_WO,
  30970         0,
  30971         1,
  30972         soc_BRDC_CCS_SBUS_LAST_IN_CHAINr_fields,
  30973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  30974         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  30975         -1,
  30976         -1,
  30977     },
  30978 #endif /* chips */
  30979 
  30980 #if defined(BCM_88950_A0)
  30981     { /* SOC_REG_INT_BRDC_FMAC_AC_TX_CELL_LIMITr */
  30982         soc_block_list[102],
  30983         soc_genreg,
  30984         1,
  30985         0,
  30986         0x10a,
  30987         SOC_REG_FLAG_64_BITS |
  30988                           SOC_REG_FLAG_WO,
  30989         0,
  30990         3,
  30991         soc_BRDC_FMAC_AC_TX_CELL_LIMITr_fields,
  30992         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  30993         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  30994         -1,
  30995         -1,
  30996     },
  30997 #endif /* chips */
  30998 
  30999 #if defined(BCM_88650_A0)
  31000     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATIONr */
  31001         soc_block_list[23],
  31002         soc_genreg,
  31003         4,
  31004         0,
  31005         0xb0,
  31006         SOC_REG_FLAG_64_BITS |
  31007                           SOC_REG_FLAG_ARRAY |
  31008                           SOC_REG_FLAG_WO |
  31009                           SOC_REG_FLAG_REG_ARRAY,
  31010         0,
  31011         16,
  31012         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATIONr_fields,
  31013         SOC_RESET_VAL_DEC(0x045403d5, 0x00000000)
  31014         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31015         -1,
  31016         -1,
  31017     },
  31018 #endif /* chips */
  31019 
  31020 #if defined(BCM_83208_A0)
  31021     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM83208_A0r */
  31022         soc_block_list[23],
  31023         soc_genreg,
  31024         4,
  31025         0,
  31026         0x146,
  31027         SOC_REG_FLAG_64_BITS |
  31028                           SOC_REG_FLAG_ARRAY |
  31029                           SOC_REG_FLAG_WO |
  31030                           SOC_REG_FLAG_REG_ARRAY,
  31031         0,
  31032         16,
  31033         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM83208_A0r_fields,
  31034         SOC_RESET_VAL_DEC(0x00a801d5, 0x00000000)
  31035         SOC_RESET_MASK_DEC(0xffffffff, 0x0000001f)
  31036         -1,
  31037         -1,
  31038     },
  31039 #endif /* chips */
  31040 
  31041 #if defined(BCM_88202_A0)
  31042     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88202_A0r */
  31043         soc_block_list[23],
  31044         soc_genreg,
  31045         4,
  31046         0,
  31047         0xb0,
  31048         SOC_REG_FLAG_64_BITS |
  31049                           SOC_REG_FLAG_ARRAY |
  31050                           SOC_REG_FLAG_WO |
  31051                           SOC_REG_FLAG_REG_ARRAY,
  31052         0,
  31053         16,
  31054         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88202_A0r_fields,
  31055         SOC_RESET_VAL_DEC(0x045403d5, 0x00000000)
  31056         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31057         -1,
  31058         -1,
  31059     },
  31060 #endif /* chips */
  31061 
  31062 #if defined(BCM_88375_A0)
  31063     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88375_A0r */
  31064         soc_block_list[23],
  31065         soc_genreg,
  31066         4,
  31067         0,
  31068         0x131,
  31069         SOC_REG_FLAG_64_BITS |
  31070                           SOC_REG_FLAG_ARRAY |
  31071                           SOC_REG_FLAG_WO |
  31072                           SOC_REG_FLAG_REG_ARRAY,
  31073         0,
  31074         16,
  31075         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88375_A0r_fields,
  31076         SOC_RESET_VAL_DEC(0x005401d5, 0x00000000)
  31077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31078         -1,
  31079         -1,
  31080     },
  31081 #endif /* chips */
  31082 
  31083 #if defined(BCM_88375_B0)
  31084     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88375_B0r */
  31085         soc_block_list[23],
  31086         soc_genreg,
  31087         4,
  31088         0,
  31089         0x131,
  31090         SOC_REG_FLAG_64_BITS |
  31091                           SOC_REG_FLAG_ARRAY |
  31092                           SOC_REG_FLAG_WO |
  31093                           SOC_REG_FLAG_REG_ARRAY,
  31094         0,
  31095         16,
  31096         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88375_B0r_fields,
  31097         SOC_RESET_VAL_DEC(0x005401d5, 0x00000000)
  31098         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31099         -1,
  31100         -1,
  31101     },
  31102 #endif /* chips */
  31103 
  31104 #if defined(BCM_88650_B0)
  31105     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88650_B0r */
  31106         soc_block_list[23],
  31107         soc_genreg,
  31108         4,
  31109         0,
  31110         0xb0,
  31111         SOC_REG_FLAG_64_BITS |
  31112                           SOC_REG_FLAG_ARRAY |
  31113                           SOC_REG_FLAG_WO |
  31114                           SOC_REG_FLAG_REG_ARRAY,
  31115         0,
  31116         16,
  31117         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88650_B0r_fields,
  31118         SOC_RESET_VAL_DEC(0x045403d5, 0x00000000)
  31119         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31120         -1,
  31121         -1,
  31122     },
  31123 #endif /* chips */
  31124 
  31125 #if defined(BCM_88660_A0)
  31126     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88660_A0r */
  31127         soc_block_list[23],
  31128         soc_genreg,
  31129         4,
  31130         0,
  31131         0xb0,
  31132         SOC_REG_FLAG_64_BITS |
  31133                           SOC_REG_FLAG_ARRAY |
  31134                           SOC_REG_FLAG_WO |
  31135                           SOC_REG_FLAG_REG_ARRAY,
  31136         0,
  31137         16,
  31138         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88660_A0r_fields,
  31139         SOC_RESET_VAL_DEC(0x045403d5, 0x00000000)
  31140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31141         -1,
  31142         -1,
  31143     },
  31144 #endif /* chips */
  31145 
  31146 #if defined(BCM_88675_A0)
  31147     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88675_A0r */
  31148         soc_block_list[23],
  31149         soc_genreg,
  31150         4,
  31151         0,
  31152         0x131,
  31153         SOC_REG_FLAG_64_BITS |
  31154                           SOC_REG_FLAG_ARRAY |
  31155                           SOC_REG_FLAG_WO |
  31156                           SOC_REG_FLAG_REG_ARRAY,
  31157         0,
  31158         16,
  31159         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88675_A0r_fields,
  31160         SOC_RESET_VAL_DEC(0x005401d5, 0x00000000)
  31161         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31162         -1,
  31163         -1,
  31164     },
  31165 #endif /* chips */
  31166 
  31167 #if defined(BCM_88675_B0)
  31168     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88675_B0r */
  31169         soc_block_list[23],
  31170         soc_genreg,
  31171         4,
  31172         0,
  31173         0x131,
  31174         SOC_REG_FLAG_64_BITS |
  31175                           SOC_REG_FLAG_ARRAY |
  31176                           SOC_REG_FLAG_WO |
  31177                           SOC_REG_FLAG_REG_ARRAY,
  31178         0,
  31179         16,
  31180         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88675_B0r_fields,
  31181         SOC_RESET_VAL_DEC(0x005401d5, 0x00000000)
  31182         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31183         -1,
  31184         -1,
  31185     },
  31186 #endif /* chips */
  31187 
  31188 #if defined(BCM_88680_A0)
  31189     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88680_A0r */
  31190         soc_block_list[23],
  31191         soc_genreg,
  31192         4,
  31193         0,
  31194         0x131,
  31195         SOC_REG_FLAG_64_BITS |
  31196                           SOC_REG_FLAG_ARRAY |
  31197                           SOC_REG_FLAG_WO |
  31198                           SOC_REG_FLAG_REG_ARRAY,
  31199         0,
  31200         16,
  31201         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88680_A0r_fields,
  31202         SOC_RESET_VAL_DEC(0x005401d5, 0x00000000)
  31203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31204         -1,
  31205         -1,
  31206     },
  31207 #endif /* chips */
  31208 
  31209 #if defined(BCM_88690_A0)
  31210     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88690_A0r */
  31211         soc_block_list[23],
  31212         soc_genreg,
  31213         4,
  31214         0,
  31215         0x182,
  31216         SOC_REG_FLAG_64_BITS |
  31217                           SOC_REG_FLAG_ARRAY |
  31218                           SOC_REG_FLAG_WO |
  31219                           SOC_REG_FLAG_REG_ARRAY,
  31220         SOC_REG_FLAG_INIT_ON_READ,
  31221         16,
  31222         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88690_A0r_fields,
  31223         SOC_RESET_VAL_DEC(0x088001d0, 0x00000000)
  31224         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  31225         -1,
  31226         -1,
  31227     },
  31228 #endif /* chips */
  31229 
  31230 #if defined(BCM_88690_B0)
  31231     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88690_B0r */
  31232         soc_block_list[23],
  31233         soc_genreg,
  31234         4,
  31235         0,
  31236         0x182,
  31237         SOC_REG_FLAG_64_BITS |
  31238                           SOC_REG_FLAG_ARRAY |
  31239                           SOC_REG_FLAG_WO |
  31240                           SOC_REG_FLAG_REG_ARRAY,
  31241         SOC_REG_FLAG_INIT_ON_READ,
  31242         16,
  31243         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88690_B0r_fields,
  31244         SOC_RESET_VAL_DEC(0x088001d0, 0x00000000)
  31245         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  31246         -1,
  31247         -1,
  31248     },
  31249 #endif /* chips */
  31250 
  31251 #if defined(BCM_88790_A0)
  31252     { /* SOC_REG_INT_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88790_A0r */
  31253         soc_block_list[23],
  31254         soc_genreg,
  31255         4,
  31256         0,
  31257         0x182,
  31258         SOC_REG_FLAG_64_BITS |
  31259                           SOC_REG_FLAG_ARRAY |
  31260                           SOC_REG_FLAG_WO |
  31261                           SOC_REG_FLAG_REG_ARRAY,
  31262         0,
  31263         16,
  31264         soc_BRDC_FMAC_ASYNC_FIFO_CONFIGURATION_BCM88790_A0r_fields,
  31265         SOC_RESET_VAL_DEC(0x088001d0, 0x00000000)
  31266         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  31267         -1,
  31268         -1,
  31269     },
  31270 #endif /* chips */
  31271 
  31272 #if defined(BCM_88790_A0)
  31273     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_12r */
  31274         soc_block_list[23],
  31275         soc_genreg,
  31276         1,
  31277         0,
  31278         0x11a,
  31279         SOC_REG_FLAG_WO,
  31280         0,
  31281         1,
  31282         soc_BRDC_FMAC_AUTO_DOC_NAME_12r_fields,
  31283         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  31284         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  31285         -1,
  31286         -1,
  31287     },
  31288 #endif /* chips */
  31289 
  31290 #if defined(BCM_88790_A0)
  31291     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_36r */
  31292         soc_block_list[23],
  31293         soc_genreg,
  31294         4,
  31295         0,
  31296         0x148,
  31297         SOC_REG_FLAG_ARRAY |
  31298                           SOC_REG_FLAG_RO |
  31299                           SOC_REG_FLAG_WO |
  31300                           SOC_REG_FLAG_REG_ARRAY,
  31301         SOC_REG_FLAG_COUNTER_FEILDS,
  31302         1,
  31303         soc_BRDC_FMAC_AUTO_DOC_NAME_36r_fields,
  31304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31305         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31306         -1,
  31307         -1,
  31308     },
  31309 #endif /* chips */
  31310 
  31311 #if defined(BCM_88790_A0)
  31312     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_37r */
  31313         soc_block_list[23],
  31314         soc_genreg,
  31315         1,
  31316         0,
  31317         0x150,
  31318         SOC_REG_FLAG_WO,
  31319         0,
  31320         5,
  31321         soc_BRDC_FMAC_AUTO_DOC_NAME_37r_fields,
  31322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31323         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  31324         -1,
  31325         -1,
  31326     },
  31327 #endif /* chips */
  31328 
  31329 #if defined(BCM_88790_A0)
  31330     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_38r */
  31331         soc_block_list[23],
  31332         soc_genreg,
  31333         1,
  31334         0,
  31335         0x155,
  31336         SOC_REG_FLAG_WO,
  31337         0,
  31338         3,
  31339         soc_BRDC_FMAC_AUTO_DOC_NAME_38r_fields,
  31340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31341         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  31342         -1,
  31343         -1,
  31344     },
  31345 #endif /* chips */
  31346 
  31347 #if defined(BCM_88790_A0)
  31348     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_39r */
  31349         soc_block_list[23],
  31350         soc_genreg,
  31351         1,
  31352         0,
  31353         0x156,
  31354         SOC_REG_FLAG_WO,
  31355         0,
  31356         2,
  31357         soc_BRDC_FMAC_AUTO_DOC_NAME_39r_fields,
  31358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31359         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  31360         -1,
  31361         -1,
  31362     },
  31363 #endif /* chips */
  31364 
  31365 #if defined(BCM_88790_A0)
  31366     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_40r */
  31367         soc_block_list[23],
  31368         soc_genreg,
  31369         1,
  31370         0,
  31371         0x157,
  31372         SOC_REG_FLAG_WO,
  31373         0,
  31374         1,
  31375         soc_BRDC_FMAC_AUTO_DOC_NAME_40r_fields,
  31376         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  31377         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  31378         -1,
  31379         -1,
  31380     },
  31381 #endif /* chips */
  31382 
  31383 #if defined(BCM_88790_A0)
  31384     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_41r */
  31385         soc_block_list[23],
  31386         soc_genreg,
  31387         1,
  31388         0,
  31389         0x162,
  31390         SOC_REG_FLAG_64_BITS |
  31391                           SOC_REG_FLAG_WO,
  31392         0,
  31393         1,
  31394         soc_BRDC_FMAC_AUTO_DOC_NAME_41r_fields,
  31395         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  31396         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  31397         -1,
  31398         -1,
  31399     },
  31400 #endif /* chips */
  31401 
  31402 #if defined(BCM_88790_A0)
  31403     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_42r */
  31404         soc_block_list[23],
  31405         soc_genreg,
  31406         1,
  31407         0,
  31408         0x164,
  31409         SOC_REG_FLAG_WO,
  31410         0,
  31411         8,
  31412         soc_BRDC_FMAC_AUTO_DOC_NAME_42r_fields,
  31413         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  31414         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31415         -1,
  31416         -1,
  31417     },
  31418 #endif /* chips */
  31419 
  31420 #if defined(BCM_88790_A0)
  31421     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_43r */
  31422         soc_block_list[23],
  31423         soc_genreg,
  31424         1,
  31425         0,
  31426         0x165,
  31427         SOC_REG_FLAG_WO,
  31428         0,
  31429         1,
  31430         soc_BRDC_FMAC_AUTO_DOC_NAME_43r_fields,
  31431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31432         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  31433         -1,
  31434         -1,
  31435     },
  31436 #endif /* chips */
  31437 
  31438 #if defined(BCM_88690_A0)
  31439     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_12_BCM88690_A0r */
  31440         soc_block_list[23],
  31441         soc_genreg,
  31442         1,
  31443         0,
  31444         0x11a,
  31445         SOC_REG_FLAG_WO,
  31446         0,
  31447         1,
  31448         soc_BRDC_FMAC_AUTO_DOC_NAME_12_BCM88690_A0r_fields,
  31449         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  31450         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  31451         -1,
  31452         -1,
  31453     },
  31454 #endif /* chips */
  31455 
  31456 #if defined(BCM_88690_B0)
  31457     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_12_BCM88690_B0r */
  31458         soc_block_list[23],
  31459         soc_genreg,
  31460         1,
  31461         0,
  31462         0x11a,
  31463         SOC_REG_FLAG_WO,
  31464         0,
  31465         1,
  31466         soc_BRDC_FMAC_AUTO_DOC_NAME_12_BCM88690_B0r_fields,
  31467         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  31468         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  31469         -1,
  31470         -1,
  31471     },
  31472 #endif /* chips */
  31473 
  31474 #if defined(BCM_88690_A0)
  31475     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_36_BCM88690_A0r */
  31476         soc_block_list[23],
  31477         soc_genreg,
  31478         4,
  31479         0,
  31480         0x148,
  31481         SOC_REG_FLAG_ARRAY |
  31482                           SOC_REG_FLAG_RO |
  31483                           SOC_REG_FLAG_WO |
  31484                           SOC_REG_FLAG_REG_ARRAY,
  31485         SOC_REG_FLAG_COUNTER_FEILDS,
  31486         1,
  31487         soc_BRDC_FMAC_AUTO_DOC_NAME_36_BCM88690_A0r_fields,
  31488         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31489         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31490         -1,
  31491         -1,
  31492     },
  31493 #endif /* chips */
  31494 
  31495 #if defined(BCM_88690_B0)
  31496     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_36_BCM88690_B0r */
  31497         soc_block_list[23],
  31498         soc_genreg,
  31499         4,
  31500         0,
  31501         0x148,
  31502         SOC_REG_FLAG_ARRAY |
  31503                           SOC_REG_FLAG_RO |
  31504                           SOC_REG_FLAG_WO |
  31505                           SOC_REG_FLAG_REG_ARRAY,
  31506         SOC_REG_FLAG_COUNTER_FEILDS,
  31507         1,
  31508         soc_BRDC_FMAC_AUTO_DOC_NAME_36_BCM88690_B0r_fields,
  31509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31510         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31511         -1,
  31512         -1,
  31513     },
  31514 #endif /* chips */
  31515 
  31516 #if defined(BCM_88690_A0)
  31517     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_37_BCM88690_A0r */
  31518         soc_block_list[23],
  31519         soc_genreg,
  31520         1,
  31521         0,
  31522         0x150,
  31523         SOC_REG_FLAG_WO,
  31524         0,
  31525         5,
  31526         soc_BRDC_FMAC_AUTO_DOC_NAME_37_BCM88690_A0r_fields,
  31527         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31528         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  31529         -1,
  31530         -1,
  31531     },
  31532 #endif /* chips */
  31533 
  31534 #if defined(BCM_88690_B0)
  31535     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_37_BCM88690_B0r */
  31536         soc_block_list[23],
  31537         soc_genreg,
  31538         1,
  31539         0,
  31540         0x150,
  31541         SOC_REG_FLAG_WO,
  31542         0,
  31543         5,
  31544         soc_BRDC_FMAC_AUTO_DOC_NAME_37_BCM88690_B0r_fields,
  31545         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31546         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  31547         -1,
  31548         -1,
  31549     },
  31550 #endif /* chips */
  31551 
  31552 #if defined(BCM_88690_A0)
  31553     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_38_BCM88690_A0r */
  31554         soc_block_list[23],
  31555         soc_genreg,
  31556         1,
  31557         0,
  31558         0x155,
  31559         SOC_REG_FLAG_WO,
  31560         0,
  31561         3,
  31562         soc_BRDC_FMAC_AUTO_DOC_NAME_38_BCM88690_A0r_fields,
  31563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31564         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  31565         -1,
  31566         -1,
  31567     },
  31568 #endif /* chips */
  31569 
  31570 #if defined(BCM_88690_B0)
  31571     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_38_BCM88690_B0r */
  31572         soc_block_list[23],
  31573         soc_genreg,
  31574         1,
  31575         0,
  31576         0x155,
  31577         SOC_REG_FLAG_WO,
  31578         0,
  31579         3,
  31580         soc_BRDC_FMAC_AUTO_DOC_NAME_38_BCM88690_B0r_fields,
  31581         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31582         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  31583         -1,
  31584         -1,
  31585     },
  31586 #endif /* chips */
  31587 
  31588 #if defined(BCM_88690_A0)
  31589     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_39_BCM88690_A0r */
  31590         soc_block_list[23],
  31591         soc_genreg,
  31592         1,
  31593         0,
  31594         0x156,
  31595         SOC_REG_FLAG_WO,
  31596         0,
  31597         2,
  31598         soc_BRDC_FMAC_AUTO_DOC_NAME_39_BCM88690_A0r_fields,
  31599         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31600         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  31601         -1,
  31602         -1,
  31603     },
  31604 #endif /* chips */
  31605 
  31606 #if defined(BCM_88690_B0)
  31607     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_39_BCM88690_B0r */
  31608         soc_block_list[23],
  31609         soc_genreg,
  31610         1,
  31611         0,
  31612         0x156,
  31613         SOC_REG_FLAG_WO,
  31614         0,
  31615         2,
  31616         soc_BRDC_FMAC_AUTO_DOC_NAME_39_BCM88690_B0r_fields,
  31617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31618         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  31619         -1,
  31620         -1,
  31621     },
  31622 #endif /* chips */
  31623 
  31624 #if defined(BCM_88690_A0)
  31625     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_40_BCM88690_A0r */
  31626         soc_block_list[23],
  31627         soc_genreg,
  31628         1,
  31629         0,
  31630         0x157,
  31631         SOC_REG_FLAG_WO,
  31632         0,
  31633         1,
  31634         soc_BRDC_FMAC_AUTO_DOC_NAME_40_BCM88690_A0r_fields,
  31635         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  31636         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  31637         -1,
  31638         -1,
  31639     },
  31640 #endif /* chips */
  31641 
  31642 #if defined(BCM_88690_B0)
  31643     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_40_BCM88690_B0r */
  31644         soc_block_list[23],
  31645         soc_genreg,
  31646         1,
  31647         0,
  31648         0x157,
  31649         SOC_REG_FLAG_WO,
  31650         0,
  31651         1,
  31652         soc_BRDC_FMAC_AUTO_DOC_NAME_40_BCM88690_B0r_fields,
  31653         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  31654         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  31655         -1,
  31656         -1,
  31657     },
  31658 #endif /* chips */
  31659 
  31660 #if defined(BCM_88690_A0)
  31661     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_41_BCM88690_A0r */
  31662         soc_block_list[23],
  31663         soc_genreg,
  31664         1,
  31665         0,
  31666         0x162,
  31667         SOC_REG_FLAG_64_BITS |
  31668                           SOC_REG_FLAG_WO,
  31669         0,
  31670         1,
  31671         soc_BRDC_FMAC_AUTO_DOC_NAME_41_BCM88690_A0r_fields,
  31672         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  31673         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  31674         -1,
  31675         -1,
  31676     },
  31677 #endif /* chips */
  31678 
  31679 #if defined(BCM_88690_B0)
  31680     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_41_BCM88690_B0r */
  31681         soc_block_list[23],
  31682         soc_genreg,
  31683         1,
  31684         0,
  31685         0x162,
  31686         SOC_REG_FLAG_64_BITS |
  31687                           SOC_REG_FLAG_WO,
  31688         0,
  31689         1,
  31690         soc_BRDC_FMAC_AUTO_DOC_NAME_41_BCM88690_B0r_fields,
  31691         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  31692         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  31693         -1,
  31694         -1,
  31695     },
  31696 #endif /* chips */
  31697 
  31698 #if defined(BCM_88690_A0)
  31699     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_42_BCM88690_A0r */
  31700         soc_block_list[23],
  31701         soc_genreg,
  31702         1,
  31703         0,
  31704         0x164,
  31705         SOC_REG_FLAG_WO,
  31706         0,
  31707         8,
  31708         soc_BRDC_FMAC_AUTO_DOC_NAME_42_BCM88690_A0r_fields,
  31709         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  31710         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31711         -1,
  31712         -1,
  31713     },
  31714 #endif /* chips */
  31715 
  31716 #if defined(BCM_88690_B0)
  31717     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_42_BCM88690_B0r */
  31718         soc_block_list[23],
  31719         soc_genreg,
  31720         1,
  31721         0,
  31722         0x164,
  31723         SOC_REG_FLAG_WO,
  31724         0,
  31725         8,
  31726         soc_BRDC_FMAC_AUTO_DOC_NAME_42_BCM88690_B0r_fields,
  31727         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  31728         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31729         -1,
  31730         -1,
  31731     },
  31732 #endif /* chips */
  31733 
  31734 #if defined(BCM_88690_A0)
  31735     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_43_BCM88690_A0r */
  31736         soc_block_list[23],
  31737         soc_genreg,
  31738         1,
  31739         0,
  31740         0x165,
  31741         SOC_REG_FLAG_WO,
  31742         0,
  31743         1,
  31744         soc_BRDC_FMAC_AUTO_DOC_NAME_43_BCM88690_A0r_fields,
  31745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31746         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  31747         -1,
  31748         -1,
  31749     },
  31750 #endif /* chips */
  31751 
  31752 #if defined(BCM_88690_B0)
  31753     { /* SOC_REG_INT_BRDC_FMAC_AUTO_DOC_NAME_43_BCM88690_B0r */
  31754         soc_block_list[23],
  31755         soc_genreg,
  31756         1,
  31757         0,
  31758         0x165,
  31759         SOC_REG_FLAG_WO,
  31760         0,
  31761         1,
  31762         soc_BRDC_FMAC_AUTO_DOC_NAME_43_BCM88690_B0r_fields,
  31763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31764         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  31765         -1,
  31766         -1,
  31767     },
  31768 #endif /* chips */
  31769 
  31770 #if defined(BCM_88950_A0)
  31771     { /* SOC_REG_INT_BRDC_FMAC_BD_ASYNC_FIFO_CONFIGURATIONr */
  31772         soc_block_list[101],
  31773         soc_genreg,
  31774         4,
  31775         0,
  31776         0x131,
  31777         SOC_REG_FLAG_64_BITS |
  31778                           SOC_REG_FLAG_ARRAY |
  31779                           SOC_REG_FLAG_WO |
  31780                           SOC_REG_FLAG_REG_ARRAY,
  31781         0,
  31782         16,
  31783         soc_BRDC_FMAC_AC_ASYNC_FIFO_CONFIGURATIONr_fields,
  31784         SOC_RESET_VAL_DEC(0x005401d5, 0x00000000)
  31785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000007)
  31786         -1,
  31787         -1,
  31788     },
  31789 #endif /* chips */
  31790 
  31791 #if defined(BCM_88950_A0)
  31792     { /* SOC_REG_INT_BRDC_FMAC_BD_BER_GEN_BITMAPr */
  31793         soc_block_list[101],
  31794         soc_genreg,
  31795         1,
  31796         0,
  31797         0x11b,
  31798         SOC_REG_FLAG_64_BITS |
  31799                           SOC_REG_FLAG_WO,
  31800         0,
  31801         1,
  31802         soc_BRDC_FMAC_AC_BER_GEN_BITMAPr_fields,
  31803         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  31804         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  31805         -1,
  31806         -1,
  31807     },
  31808 #endif /* chips */
  31809 
  31810 #if defined(BCM_88950_A0)
  31811     { /* SOC_REG_INT_BRDC_FMAC_BD_BER_GEN_PERIODr */
  31812         soc_block_list[101],
  31813         soc_genreg,
  31814         1,
  31815         0,
  31816         0x11a,
  31817         SOC_REG_FLAG_WO,
  31818         0,
  31819         1,
  31820         soc_BRDC_FMAC_AC_BER_GEN_PERIODr_fields,
  31821         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  31822         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  31823         -1,
  31824         -1,
  31825     },
  31826 #endif /* chips */
  31827 
  31828 #if defined(BCM_88950_A0)
  31829     { /* SOC_REG_INT_BRDC_FMAC_BD_FBIST_CONFIGURATION_Ar */
  31830         soc_block_list[101],
  31831         soc_genreg,
  31832         1,
  31833         0,
  31834         0x1da,
  31835         SOC_REG_FLAG_WO,
  31836         0,
  31837         8,
  31838         soc_BRDC_FMAC_AC_FBIST_CONFIGURATION_Ar_fields,
  31839         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  31840         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  31841         -1,
  31842         -1,
  31843     },
  31844 #endif /* chips */
  31845 
  31846 #if defined(BCM_88950_A0)
  31847     { /* SOC_REG_INT_BRDC_FMAC_BD_FBIST_CONFIGURATION_Br */
  31848         soc_block_list[101],
  31849         soc_genreg,
  31850         1,
  31851         0,
  31852         0x1db,
  31853         SOC_REG_FLAG_WO,
  31854         0,
  31855         1,
  31856         soc_BRDC_FMAC_AC_FBIST_CONFIGURATION_Br_fields,
  31857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31858         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  31859         -1,
  31860         -1,
  31861     },
  31862 #endif /* chips */
  31863 
  31864 #if defined(BCM_88950_A0)
  31865     { /* SOC_REG_INT_BRDC_FMAC_BD_FBIST_STATUSr */
  31866         soc_block_list[101],
  31867         soc_genreg,
  31868         1,
  31869         0,
  31870         0x1dc,
  31871         SOC_REG_FLAG_RO |
  31872                           SOC_REG_FLAG_WO,
  31873         0,
  31874         1,
  31875         soc_BRDC_FMAC_AC_FBIST_STATUSr_fields,
  31876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31877         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  31878         -1,
  31879         -1,
  31880     },
  31881 #endif /* chips */
  31882 
  31883 #if defined(BCM_88950_A0)
  31884     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_1r */
  31885         soc_block_list[101],
  31886         soc_genreg,
  31887         1,
  31888         0,
  31889         0x211,
  31890         SOC_REG_FLAG_WO,
  31891         0,
  31892         2,
  31893         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_1r_fields,
  31894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31895         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31896         -1,
  31897         -1,
  31898     },
  31899 #endif /* chips */
  31900 
  31901 #if defined(BCM_88950_A0)
  31902     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_2r */
  31903         soc_block_list[101],
  31904         soc_genreg,
  31905         1,
  31906         0,
  31907         0x212,
  31908         SOC_REG_FLAG_WO,
  31909         0,
  31910         2,
  31911         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_2r_fields,
  31912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31913         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31914         -1,
  31915         -1,
  31916     },
  31917 #endif /* chips */
  31918 
  31919 #if defined(BCM_88950_A0)
  31920     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_3r */
  31921         soc_block_list[101],
  31922         soc_genreg,
  31923         1,
  31924         0,
  31925         0x213,
  31926         SOC_REG_FLAG_WO,
  31927         0,
  31928         2,
  31929         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_3r_fields,
  31930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31931         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31932         -1,
  31933         -1,
  31934     },
  31935 #endif /* chips */
  31936 
  31937 #if defined(BCM_88950_A0)
  31938     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_4r */
  31939         soc_block_list[101],
  31940         soc_genreg,
  31941         1,
  31942         0,
  31943         0x214,
  31944         SOC_REG_FLAG_WO,
  31945         0,
  31946         2,
  31947         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_4r_fields,
  31948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31949         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31950         -1,
  31951         -1,
  31952     },
  31953 #endif /* chips */
  31954 
  31955 #if defined(BCM_88950_A0)
  31956     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_5r */
  31957         soc_block_list[101],
  31958         soc_genreg,
  31959         1,
  31960         0,
  31961         0x215,
  31962         SOC_REG_FLAG_WO,
  31963         0,
  31964         2,
  31965         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_5r_fields,
  31966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31967         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31968         -1,
  31969         -1,
  31970     },
  31971 #endif /* chips */
  31972 
  31973 #if defined(BCM_88950_A0)
  31974     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_6r */
  31975         soc_block_list[101],
  31976         soc_genreg,
  31977         1,
  31978         0,
  31979         0x216,
  31980         SOC_REG_FLAG_WO,
  31981         0,
  31982         2,
  31983         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_6r_fields,
  31984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  31985         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  31986         -1,
  31987         -1,
  31988     },
  31989 #endif /* chips */
  31990 
  31991 #if defined(BCM_88950_A0)
  31992     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_7r */
  31993         soc_block_list[101],
  31994         soc_genreg,
  31995         1,
  31996         0,
  31997         0x217,
  31998         SOC_REG_FLAG_WO,
  31999         0,
  32000         2,
  32001         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_7r_fields,
  32002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32003         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32004         -1,
  32005         -1,
  32006     },
  32007 #endif /* chips */
  32008 
  32009 #if defined(BCM_88950_A0)
  32010     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_8r */
  32011         soc_block_list[101],
  32012         soc_genreg,
  32013         1,
  32014         0,
  32015         0x218,
  32016         SOC_REG_FLAG_WO,
  32017         0,
  32018         3,
  32019         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_8r_fields,
  32020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32021         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  32022         -1,
  32023         -1,
  32024     },
  32025 #endif /* chips */
  32026 
  32027 #if defined(BCM_88950_A0)
  32028     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_1r */
  32029         soc_block_list[101],
  32030         soc_genreg,
  32031         1,
  32032         0,
  32033         0x201,
  32034         SOC_REG_FLAG_WO |
  32035                           SOC_REG_FLAG_INTERRUPT,
  32036         0,
  32037         2,
  32038         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1r_fields,
  32039         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32040         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32041         -1,
  32042         -1,
  32043     },
  32044 #endif /* chips */
  32045 
  32046 #if defined(BCM_88950_A0)
  32047     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_2r */
  32048         soc_block_list[101],
  32049         soc_genreg,
  32050         1,
  32051         0,
  32052         0x202,
  32053         SOC_REG_FLAG_WO |
  32054                           SOC_REG_FLAG_INTERRUPT,
  32055         0,
  32056         2,
  32057         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2r_fields,
  32058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32059         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32060         -1,
  32061         -1,
  32062     },
  32063 #endif /* chips */
  32064 
  32065 #if defined(BCM_88950_A0)
  32066     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_3r */
  32067         soc_block_list[101],
  32068         soc_genreg,
  32069         1,
  32070         0,
  32071         0x203,
  32072         SOC_REG_FLAG_WO |
  32073                           SOC_REG_FLAG_INTERRUPT,
  32074         0,
  32075         2,
  32076         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3r_fields,
  32077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32078         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32079         -1,
  32080         -1,
  32081     },
  32082 #endif /* chips */
  32083 
  32084 #if defined(BCM_88950_A0)
  32085     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_4r */
  32086         soc_block_list[101],
  32087         soc_genreg,
  32088         1,
  32089         0,
  32090         0x204,
  32091         SOC_REG_FLAG_WO |
  32092                           SOC_REG_FLAG_INTERRUPT,
  32093         0,
  32094         2,
  32095         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4r_fields,
  32096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32097         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32098         -1,
  32099         -1,
  32100     },
  32101 #endif /* chips */
  32102 
  32103 #if defined(BCM_88950_A0)
  32104     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_5r */
  32105         soc_block_list[101],
  32106         soc_genreg,
  32107         1,
  32108         0,
  32109         0x205,
  32110         SOC_REG_FLAG_WO |
  32111                           SOC_REG_FLAG_INTERRUPT,
  32112         0,
  32113         2,
  32114         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5r_fields,
  32115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32116         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32117         -1,
  32118         -1,
  32119     },
  32120 #endif /* chips */
  32121 
  32122 #if defined(BCM_88950_A0)
  32123     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_6r */
  32124         soc_block_list[101],
  32125         soc_genreg,
  32126         1,
  32127         0,
  32128         0x206,
  32129         SOC_REG_FLAG_WO |
  32130                           SOC_REG_FLAG_INTERRUPT,
  32131         0,
  32132         2,
  32133         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6r_fields,
  32134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32135         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32136         -1,
  32137         -1,
  32138     },
  32139 #endif /* chips */
  32140 
  32141 #if defined(BCM_88950_A0)
  32142     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_7r */
  32143         soc_block_list[101],
  32144         soc_genreg,
  32145         1,
  32146         0,
  32147         0x207,
  32148         SOC_REG_FLAG_WO |
  32149                           SOC_REG_FLAG_INTERRUPT,
  32150         0,
  32151         2,
  32152         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7r_fields,
  32153         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32154         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32155         -1,
  32156         -1,
  32157     },
  32158 #endif /* chips */
  32159 
  32160 #if defined(BCM_88950_A0)
  32161     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_8r */
  32162         soc_block_list[101],
  32163         soc_genreg,
  32164         1,
  32165         0,
  32166         0x208,
  32167         SOC_REG_FLAG_WO |
  32168                           SOC_REG_FLAG_INTERRUPT,
  32169         0,
  32170         3,
  32171         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8r_fields,
  32172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32173         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  32174         -1,
  32175         -1,
  32176     },
  32177 #endif /* chips */
  32178 
  32179 #if defined(BCM_88950_A0)
  32180     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_1_TESTr */
  32181         soc_block_list[101],
  32182         soc_genreg,
  32183         1,
  32184         0,
  32185         0x221,
  32186         SOC_REG_FLAG_WO,
  32187         0,
  32188         1,
  32189         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1_TESTr_fields,
  32190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32191         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32192         -1,
  32193         -1,
  32194     },
  32195 #endif /* chips */
  32196 
  32197 #if defined(BCM_88950_A0)
  32198     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_2_TESTr */
  32199         soc_block_list[101],
  32200         soc_genreg,
  32201         1,
  32202         0,
  32203         0x222,
  32204         SOC_REG_FLAG_WO,
  32205         0,
  32206         1,
  32207         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2_TESTr_fields,
  32208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32210         -1,
  32211         -1,
  32212     },
  32213 #endif /* chips */
  32214 
  32215 #if defined(BCM_88950_A0)
  32216     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_3_TESTr */
  32217         soc_block_list[101],
  32218         soc_genreg,
  32219         1,
  32220         0,
  32221         0x223,
  32222         SOC_REG_FLAG_WO,
  32223         0,
  32224         1,
  32225         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3_TESTr_fields,
  32226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32227         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32228         -1,
  32229         -1,
  32230     },
  32231 #endif /* chips */
  32232 
  32233 #if defined(BCM_88950_A0)
  32234     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_4_TESTr */
  32235         soc_block_list[101],
  32236         soc_genreg,
  32237         1,
  32238         0,
  32239         0x224,
  32240         SOC_REG_FLAG_WO,
  32241         0,
  32242         1,
  32243         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4_TESTr_fields,
  32244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32246         -1,
  32247         -1,
  32248     },
  32249 #endif /* chips */
  32250 
  32251 #if defined(BCM_88950_A0)
  32252     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_5_TESTr */
  32253         soc_block_list[101],
  32254         soc_genreg,
  32255         1,
  32256         0,
  32257         0x225,
  32258         SOC_REG_FLAG_WO,
  32259         0,
  32260         1,
  32261         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5_TESTr_fields,
  32262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32263         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32264         -1,
  32265         -1,
  32266     },
  32267 #endif /* chips */
  32268 
  32269 #if defined(BCM_88950_A0)
  32270     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_6_TESTr */
  32271         soc_block_list[101],
  32272         soc_genreg,
  32273         1,
  32274         0,
  32275         0x226,
  32276         SOC_REG_FLAG_WO,
  32277         0,
  32278         1,
  32279         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6_TESTr_fields,
  32280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32281         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32282         -1,
  32283         -1,
  32284     },
  32285 #endif /* chips */
  32286 
  32287 #if defined(BCM_88950_A0)
  32288     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_7_TESTr */
  32289         soc_block_list[101],
  32290         soc_genreg,
  32291         1,
  32292         0,
  32293         0x227,
  32294         SOC_REG_FLAG_WO,
  32295         0,
  32296         1,
  32297         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7_TESTr_fields,
  32298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32299         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32300         -1,
  32301         -1,
  32302     },
  32303 #endif /* chips */
  32304 
  32305 #if defined(BCM_88950_A0)
  32306     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_8_TESTr */
  32307         soc_block_list[101],
  32308         soc_genreg,
  32309         1,
  32310         0,
  32311         0x228,
  32312         SOC_REG_FLAG_WO,
  32313         0,
  32314         1,
  32315         soc_BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8_TESTr_fields,
  32316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32317         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32318         -1,
  32319         -1,
  32320     },
  32321 #endif /* chips */
  32322 
  32323 #if defined(BCM_88950_A0)
  32324     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_GENERAL_CONFIGURATIONr */
  32325         soc_block_list[101],
  32326         soc_genreg,
  32327         4,
  32328         0,
  32329         0x11d,
  32330         SOC_REG_FLAG_ARRAY |
  32331                           SOC_REG_FLAG_WO |
  32332                           SOC_REG_FLAG_REG_ARRAY,
  32333         0,
  32334         6,
  32335         soc_BRDC_FMAC_AC_FMAL_GENERAL_CONFIGURATIONr_fields,
  32336         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  32337         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  32338         -1,
  32339         -1,
  32340     },
  32341 #endif /* chips */
  32342 
  32343 #if defined(BCM_88950_A0)
  32344     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_RX_GENERAL_CONFIGURATIONr */
  32345         soc_block_list[101],
  32346         soc_genreg,
  32347         4,
  32348         0,
  32349         0x125,
  32350         SOC_REG_FLAG_ARRAY |
  32351                           SOC_REG_FLAG_WO |
  32352                           SOC_REG_FLAG_REG_ARRAY,
  32353         0,
  32354         8,
  32355         soc_BRDC_FMAC_AC_FMAL_RX_GENERAL_CONFIGURATIONr_fields,
  32356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32357         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  32358         -1,
  32359         -1,
  32360     },
  32361 #endif /* chips */
  32362 
  32363 #if defined(BCM_88950_A0)
  32364     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_STATISTICS_COUNT_CONTROLr */
  32365         soc_block_list[101],
  32366         soc_genreg,
  32367         1,
  32368         0,
  32369         0x110,
  32370         SOC_REG_FLAG_WO,
  32371         0,
  32372         2,
  32373         soc_BRDC_FMAC_AC_FMAL_STATISTICS_COUNT_CONTROLr_fields,
  32374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32375         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  32376         -1,
  32377         -1,
  32378     },
  32379 #endif /* chips */
  32380 
  32381 #if defined(BCM_88950_A0)
  32382     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_STATISTICS_GTIMERr */
  32383         soc_block_list[101],
  32384         soc_genreg,
  32385         1,
  32386         0,
  32387         0x111,
  32388         SOC_REG_FLAG_64_BITS |
  32389                           SOC_REG_FLAG_WO,
  32390         0,
  32391         4,
  32392         soc_BRDC_FMAC_AC_FMAL_STATISTICS_GTIMERr_fields,
  32393         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  32394         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  32395         -1,
  32396         -1,
  32397     },
  32398 #endif /* chips */
  32399 
  32400 #if defined(BCM_88950_A0)
  32401     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_STATISTICS_OUTPUT_CONTROLr */
  32402         soc_block_list[101],
  32403         soc_genreg,
  32404         1,
  32405         0,
  32406         0x113,
  32407         SOC_REG_FLAG_WO,
  32408         0,
  32409         5,
  32410         soc_BRDC_FMAC_AC_FMAL_STATISTICS_OUTPUT_CONTROLr_fields,
  32411         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  32412         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  32413         -1,
  32414         -1,
  32415     },
  32416 #endif /* chips */
  32417 
  32418 #if defined(BCM_88950_A0)
  32419     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_TX_COMMA_BURST_CONFIGURATIONr */
  32420         soc_block_list[101],
  32421         soc_genreg,
  32422         4,
  32423         0,
  32424         0x129,
  32425         SOC_REG_FLAG_ARRAY |
  32426                           SOC_REG_FLAG_WO |
  32427                           SOC_REG_FLAG_REG_ARRAY,
  32428         0,
  32429         6,
  32430         soc_BRDC_FMAC_AC_FMAL_TX_COMMA_BURST_CONFIGURATIONr_fields,
  32431         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  32432         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  32433         -1,
  32434         -1,
  32435     },
  32436 #endif /* chips */
  32437 
  32438 #if defined(BCM_88950_A0)
  32439     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_TX_CONTROL_BURST_CONFIGURATIONr */
  32440         soc_block_list[101],
  32441         soc_genreg,
  32442         4,
  32443         0,
  32444         0x12d,
  32445         SOC_REG_FLAG_ARRAY |
  32446                           SOC_REG_FLAG_WO |
  32447                           SOC_REG_FLAG_REG_ARRAY,
  32448         0,
  32449         2,
  32450         soc_BRDC_FMAC_AC_FMAL_TX_CONTROL_BURST_CONFIGURATIONr_fields,
  32451         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  32452         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  32453         -1,
  32454         -1,
  32455     },
  32456 #endif /* chips */
  32457 
  32458 #if defined(BCM_88950_A0)
  32459     { /* SOC_REG_INT_BRDC_FMAC_BD_FMAL_TX_GENERAL_CONFIGURATIONr */
  32460         soc_block_list[101],
  32461         soc_genreg,
  32462         4,
  32463         0,
  32464         0x121,
  32465         SOC_REG_FLAG_ARRAY |
  32466                           SOC_REG_FLAG_WO |
  32467                           SOC_REG_FLAG_REG_ARRAY,
  32468         0,
  32469         11,
  32470         soc_BRDC_FMAC_AC_FMAL_TX_GENERAL_CONFIGURATIONr_fields,
  32471         SOC_RESET_VAL_DEC(0x04060008, 0x00000000)
  32472         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32473         -1,
  32474         -1,
  32475     },
  32476 #endif /* chips */
  32477 
  32478 #if defined(BCM_88950_A0)
  32479     { /* SOC_REG_INT_BRDC_FMAC_BD_FPS_CONFIGURATION_BERr */
  32480         soc_block_list[101],
  32481         soc_genreg,
  32482         4,
  32483         0,
  32484         0x13d,
  32485         SOC_REG_FLAG_ARRAY |
  32486                           SOC_REG_FLAG_WO |
  32487                           SOC_REG_FLAG_REG_ARRAY,
  32488         0,
  32489         6,
  32490         soc_BRDC_FMAC_AC_FPS_CONFIGURATION_BERr_fields,
  32491         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  32492         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  32493         -1,
  32494         -1,
  32495     },
  32496 #endif /* chips */
  32497 
  32498 #if defined(BCM_88950_A0)
  32499     { /* SOC_REG_INT_BRDC_FMAC_BD_FPS_CONFIGURATION_RX_SYNCr */
  32500         soc_block_list[101],
  32501         soc_genreg,
  32502         4,
  32503         0,
  32504         0x141,
  32505         SOC_REG_FLAG_ARRAY |
  32506                           SOC_REG_FLAG_WO |
  32507                           SOC_REG_FLAG_REG_ARRAY,
  32508         0,
  32509         7,
  32510         soc_BRDC_FMAC_AC_FPS_CONFIGURATION_RX_SYNCr_fields,
  32511         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  32512         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  32513         -1,
  32514         -1,
  32515     },
  32516 #endif /* chips */
  32517 
  32518 #if defined(BCM_88950_A0)
  32519     { /* SOC_REG_INT_BRDC_FMAC_BD_FPS_RX_FEC_CONFIGURATIONr */
  32520         soc_block_list[101],
  32521         soc_genreg,
  32522         4,
  32523         0,
  32524         0x145,
  32525         SOC_REG_FLAG_ARRAY |
  32526                           SOC_REG_FLAG_WO |
  32527                           SOC_REG_FLAG_REG_ARRAY,
  32528         0,
  32529         17,
  32530         soc_BRDC_FMAC_AC_FPS_RX_FEC_CONFIGURATIONr_fields,
  32531         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  32532         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32533         -1,
  32534         -1,
  32535     },
  32536 #endif /* chips */
  32537 
  32538 #if defined(BCM_88950_A0)
  32539     { /* SOC_REG_INT_BRDC_FMAC_BD_FPS_RX_STATUSr */
  32540         soc_block_list[101],
  32541         soc_genreg,
  32542         4,
  32543         0,
  32544         0x14d,
  32545         SOC_REG_FLAG_ARRAY |
  32546                           SOC_REG_FLAG_RO |
  32547                           SOC_REG_FLAG_WO |
  32548                           SOC_REG_FLAG_REG_ARRAY,
  32549         0,
  32550         7,
  32551         soc_BRDC_FMAC_AC_FPS_RX_STATUSr_fields,
  32552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32553         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  32554         -1,
  32555         -1,
  32556     },
  32557 #endif /* chips */
  32558 
  32559 #if defined(BCM_88950_A0)
  32560     { /* SOC_REG_INT_BRDC_FMAC_BD_FPS_TX_CONFIGURATIONr */
  32561         soc_block_list[101],
  32562         soc_genreg,
  32563         4,
  32564         0,
  32565         0x149,
  32566         SOC_REG_FLAG_ARRAY |
  32567                           SOC_REG_FLAG_WO |
  32568                           SOC_REG_FLAG_REG_ARRAY,
  32569         0,
  32570         9,
  32571         soc_BRDC_FMAC_AC_FPS_TX_CONFIGURATIONr_fields,
  32572         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  32573         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  32574         -1,
  32575         -1,
  32576     },
  32577 #endif /* chips */
  32578 
  32579 #if defined(BCM_88950_A0)
  32580     { /* SOC_REG_INT_BRDC_FMAC_BD_GENERAL_CONFIGURATION_REGISTERr */
  32581         soc_block_list[101],
  32582         soc_genreg,
  32583         1,
  32584         0,
  32585         0x103,
  32586         SOC_REG_FLAG_WO,
  32587         0,
  32588         15,
  32589         soc_BRDC_FMAC_AC_GENERAL_CONFIGURATION_REGISTERr_fields,
  32590         SOC_RESET_VAL_DEC(0x000060f3, 0x00000000)
  32591         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  32592         -1,
  32593         -1,
  32594     },
  32595 #endif /* chips */
  32596 
  32597 #if defined(BCM_88950_A0)
  32598     { /* SOC_REG_INT_BRDC_FMAC_BD_GLOBAL_GENERAL_CFG_1r */
  32599         soc_block_list[101],
  32600         soc_genreg,
  32601         1,
  32602         0,
  32603         0xc1,
  32604         SOC_REG_FLAG_WO,
  32605         0,
  32606         3,
  32607         soc_BRDC_DCH_GLOBAL_GENERAL_CFG_1r_fields,
  32608         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  32609         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  32610         -1,
  32611         -1,
  32612     },
  32613 #endif /* chips */
  32614 
  32615 #if defined(BCM_88950_A0)
  32616     { /* SOC_REG_INT_BRDC_FMAC_BD_GLOBAL_GENERAL_FE_CFG_1r */
  32617         soc_block_list[101],
  32618         soc_genreg,
  32619         1,
  32620         0,
  32621         0xf4,
  32622         SOC_REG_FLAG_WO,
  32623         0,
  32624         8,
  32625         soc_BRDC_DCH_GLOBAL_GENERAL_FE_CFG_1r_fields,
  32626         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  32627         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  32628         -1,
  32629         -1,
  32630     },
  32631 #endif /* chips */
  32632 
  32633 #if defined(BCM_88950_A0)
  32634     { /* SOC_REG_INT_BRDC_FMAC_BD_GLOBAL_MEM_OPTIONSr */
  32635         soc_block_list[101],
  32636         soc_genreg,
  32637         1,
  32638         0,
  32639         0xc0,
  32640         SOC_REG_FLAG_WO,
  32641         0,
  32642         3,
  32643         soc_BRDC_DCH_GLOBAL_MEM_OPTIONSr_fields,
  32644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32645         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  32646         -1,
  32647         -1,
  32648     },
  32649 #endif /* chips */
  32650 
  32651 #if defined(BCM_88950_A0)
  32652     { /* SOC_REG_INT_BRDC_FMAC_BD_GLOBAL_TEST_RX_IDL_PTRNr */
  32653         soc_block_list[101],
  32654         soc_genreg,
  32655         1,
  32656         0,
  32657         0x1d7,
  32658         SOC_REG_FLAG_ABOVE_64_BITS |
  32659                           SOC_REG_FLAG_WO,
  32660         0,
  32661         1,
  32662         soc_BRDC_FMAC_AC_GLOBAL_TEST_RX_IDL_PTRNr_fields,
  32663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32665         -1,
  32666         -1,
  32667     },
  32668 #endif /* chips */
  32669 
  32670 #if defined(BCM_88950_A0)
  32671     { /* SOC_REG_INT_BRDC_FMAC_BD_GLOBAL_TEST_TX_IDL_PTRNr */
  32672         soc_block_list[101],
  32673         soc_genreg,
  32674         1,
  32675         0,
  32676         0x1d4,
  32677         SOC_REG_FLAG_ABOVE_64_BITS |
  32678                           SOC_REG_FLAG_WO,
  32679         0,
  32680         1,
  32681         soc_BRDC_FMAC_AC_GLOBAL_TEST_TX_IDL_PTRNr_fields,
  32682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32683         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  32684         -1,
  32685         -1,
  32686     },
  32687 #endif /* chips */
  32688 
  32689 #if defined(BCM_88950_A0)
  32690     { /* SOC_REG_INT_BRDC_FMAC_BD_GLOBAL_TEST_TX_PR_SEED_Ar */
  32691         soc_block_list[101],
  32692         soc_genreg,
  32693         1,
  32694         0,
  32695         0x1d0,
  32696         SOC_REG_FLAG_64_BITS |
  32697                           SOC_REG_FLAG_WO,
  32698         0,
  32699         1,
  32700         soc_BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_Ar_fields,
  32701         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  32702         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  32703         -1,
  32704         -1,
  32705     },
  32706 #endif /* chips */
  32707 
  32708 #if defined(BCM_88950_A0)
  32709     { /* SOC_REG_INT_BRDC_FMAC_BD_GLOBAL_TEST_TX_PR_SEED_Br */
  32710         soc_block_list[101],
  32711         soc_genreg,
  32712         1,
  32713         0,
  32714         0x1d2,
  32715         SOC_REG_FLAG_64_BITS |
  32716                           SOC_REG_FLAG_WO,
  32717         0,
  32718         1,
  32719         soc_BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_Br_fields,
  32720         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  32721         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  32722         -1,
  32723         -1,
  32724     },
  32725 #endif /* chips */
  32726 
  32727 #if defined(BCM_88950_A0)
  32728     { /* SOC_REG_INT_BRDC_FMAC_BD_GRACEFULL_POWER_ON_OFFr */
  32729         soc_block_list[101],
  32730         soc_genreg,
  32731         1,
  32732         0,
  32733         0x105,
  32734         SOC_REG_FLAG_WO,
  32735         0,
  32736         3,
  32737         soc_BRDC_FMAC_AC_GRACEFULL_POWER_ON_OFFr_fields,
  32738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32739         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  32740         -1,
  32741         -1,
  32742     },
  32743 #endif /* chips */
  32744 
  32745 #if defined(BCM_88950_A0)
  32746     { /* SOC_REG_INT_BRDC_FMAC_BD_GTIMER_CONFIGURATIONr */
  32747         soc_block_list[101],
  32748         soc_genreg,
  32749         1,
  32750         0,
  32751         0x88,
  32752         SOC_REG_FLAG_WO,
  32753         0,
  32754         3,
  32755         soc_BRDC_CCS_GTIMER_CONFIGURATIONr_fields,
  32756         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  32757         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32758         -1,
  32759         -1,
  32760     },
  32761 #endif /* chips */
  32762 
  32763 #if defined(BCM_88950_A0)
  32764     { /* SOC_REG_INT_BRDC_FMAC_BD_GTIMER_TRIGGERr */
  32765         soc_block_list[101],
  32766         soc_genreg,
  32767         1,
  32768         0,
  32769         0x89,
  32770         SOC_REG_FLAG_RO |
  32771                           SOC_REG_FLAG_WO,
  32772         0,
  32773         1,
  32774         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  32775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32776         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  32777         -1,
  32778         -1,
  32779     },
  32780 #endif /* chips */
  32781 
  32782 #if defined(BCM_88950_A0)
  32783     { /* SOC_REG_INT_BRDC_FMAC_BD_INTERRUPT_MASK_REGISTERr */
  32784         soc_block_list[101],
  32785         soc_genreg,
  32786         1,
  32787         0,
  32788         0x10,
  32789         SOC_REG_FLAG_WO,
  32790         0,
  32791         9,
  32792         soc_BRDC_FMAC_AC_INTERRUPT_MASK_REGISTERr_fields,
  32793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32794         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  32795         -1,
  32796         -1,
  32797     },
  32798 #endif /* chips */
  32799 
  32800 #if defined(BCM_88950_A0)
  32801     { /* SOC_REG_INT_BRDC_FMAC_BD_INTERRUPT_REGISTERr */
  32802         soc_block_list[101],
  32803         soc_genreg,
  32804         1,
  32805         0,
  32806         0,
  32807         SOC_REG_FLAG_RO |
  32808                           SOC_REG_FLAG_WO |
  32809                           SOC_REG_FLAG_INTERRUPT,
  32810         0,
  32811         9,
  32812         soc_BRDC_FMAC_AC_INTERRUPT_REGISTERr_fields,
  32813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32814         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  32815         -1,
  32816         -1,
  32817     },
  32818 #endif /* chips */
  32819 
  32820 #if defined(BCM_88950_A0)
  32821     { /* SOC_REG_INT_BRDC_FMAC_BD_INTERRUPT_REGISTER_TESTr */
  32822         soc_block_list[101],
  32823         soc_genreg,
  32824         1,
  32825         0,
  32826         0x18,
  32827         SOC_REG_FLAG_WO,
  32828         0,
  32829         1,
  32830         soc_BRDC_CCS_INTERRUPT_REGISTER_TESTr_fields,
  32831         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32832         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32833         -1,
  32834         -1,
  32835     },
  32836 #endif /* chips */
  32837 
  32838 #if defined(BCM_88950_A0)
  32839     { /* SOC_REG_INT_BRDC_FMAC_BD_KPCS_CONFIGURATIONr */
  32840         soc_block_list[101],
  32841         soc_genreg,
  32842         4,
  32843         0,
  32844         0x160,
  32845         SOC_REG_FLAG_ARRAY |
  32846                           SOC_REG_FLAG_WO |
  32847                           SOC_REG_FLAG_REG_ARRAY,
  32848         0,
  32849         11,
  32850         soc_BRDC_FMAC_AC_KPCS_CONFIGURATIONr_fields,
  32851         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  32852         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  32853         -1,
  32854         -1,
  32855     },
  32856 #endif /* chips */
  32857 
  32858 #if defined(BCM_88950_A0)
  32859     { /* SOC_REG_INT_BRDC_FMAC_BD_KPCS_RX_STATUSr */
  32860         soc_block_list[101],
  32861         soc_genreg,
  32862         4,
  32863         0,
  32864         0x164,
  32865         SOC_REG_FLAG_ARRAY |
  32866                           SOC_REG_FLAG_RO |
  32867                           SOC_REG_FLAG_WO |
  32868                           SOC_REG_FLAG_REG_ARRAY,
  32869         0,
  32870         2,
  32871         soc_BRDC_FMAC_AC_KPCS_RX_STATUSr_fields,
  32872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32873         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  32874         -1,
  32875         -1,
  32876     },
  32877 #endif /* chips */
  32878 
  32879 #if defined(BCM_88950_A0)
  32880     { /* SOC_REG_INT_BRDC_FMAC_BD_KPCS_TEST_RX_CONFIGURATIONr */
  32881         soc_block_list[101],
  32882         soc_genreg,
  32883         4,
  32884         0,
  32885         0x180,
  32886         SOC_REG_FLAG_ARRAY |
  32887                           SOC_REG_FLAG_WO |
  32888                           SOC_REG_FLAG_REG_ARRAY,
  32889         0,
  32890         4,
  32891         soc_BRDC_FMAC_AC_KPCS_TEST_RX_CONFIGURATIONr_fields,
  32892         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  32893         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  32894         -1,
  32895         -1,
  32896     },
  32897 #endif /* chips */
  32898 
  32899 #if defined(BCM_88950_A0)
  32900     { /* SOC_REG_INT_BRDC_FMAC_BD_KPCS_TEST_RX_STATUSr */
  32901         soc_block_list[101],
  32902         soc_genreg,
  32903         4,
  32904         0,
  32905         0x190,
  32906         SOC_REG_FLAG_ARRAY |
  32907                           SOC_REG_FLAG_RO |
  32908                           SOC_REG_FLAG_WO |
  32909                           SOC_REG_FLAG_REG_ARRAY,
  32910         0,
  32911         1,
  32912         soc_BRDC_FMAC_AC_KPCS_TEST_RX_STATUSr_fields,
  32913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32914         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  32915         -1,
  32916         -1,
  32917     },
  32918 #endif /* chips */
  32919 
  32920 #if defined(BCM_88950_A0)
  32921     { /* SOC_REG_INT_BRDC_FMAC_BD_KPCS_TEST_TX_CONFIGURATIONr */
  32922         soc_block_list[101],
  32923         soc_genreg,
  32924         4,
  32925         0,
  32926         0x170,
  32927         SOC_REG_FLAG_ARRAY |
  32928                           SOC_REG_FLAG_WO |
  32929                           SOC_REG_FLAG_REG_ARRAY,
  32930         0,
  32931         7,
  32932         soc_BRDC_FMAC_AC_KPCS_TEST_TX_CONFIGURATIONr_fields,
  32933         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  32934         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  32935         -1,
  32936         -1,
  32937     },
  32938 #endif /* chips */
  32939 
  32940 #if defined(BCM_88950_A0)
  32941     { /* SOC_REG_INT_BRDC_FMAC_BD_LEAKY_BUCKETr */
  32942         soc_block_list[101],
  32943         soc_genreg,
  32944         4,
  32945         0,
  32946         0x10c,
  32947         SOC_REG_FLAG_ARRAY |
  32948                           SOC_REG_FLAG_RO |
  32949                           SOC_REG_FLAG_WO |
  32950                           SOC_REG_FLAG_REG_ARRAY,
  32951         0,
  32952         2,
  32953         soc_BRDC_FMAC_AC_LEAKY_BUCKETr_fields,
  32954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  32955         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  32956         -1,
  32957         -1,
  32958     },
  32959 #endif /* chips */
  32960 
  32961 #if defined(BCM_88950_A0)
  32962     { /* SOC_REG_INT_BRDC_FMAC_BD_LEAKY_BUCKET_CONTROL_REGISTERr */
  32963         soc_block_list[101],
  32964         soc_genreg,
  32965         1,
  32966         0,
  32967         0x104,
  32968         SOC_REG_FLAG_WO,
  32969         0,
  32970         6,
  32971         soc_BRDC_FMAC_AC_LEAKY_BUCKET_CONTROL_REGISTERr_fields,
  32972         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  32973         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  32974         -1,
  32975         -1,
  32976     },
  32977 #endif /* chips */
  32978 
  32979 #if defined(BCM_88950_A0)
  32980     { /* SOC_REG_INT_BRDC_FMAC_BD_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr */
  32981         soc_block_list[101],
  32982         soc_genreg,
  32983         1,
  32984         0,
  32985         0x107,
  32986         SOC_REG_FLAG_WO,
  32987         0,
  32988         4,
  32989         soc_BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr_fields,
  32990         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  32991         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  32992         -1,
  32993         -1,
  32994     },
  32995 #endif /* chips */
  32996 
  32997 #if defined(BCM_88950_A0)
  32998     { /* SOC_REG_INT_BRDC_FMAC_BD_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr */
  32999         soc_block_list[101],
  33000         soc_genreg,
  33001         1,
  33002         0,
  33003         0x101,
  33004         SOC_REG_FLAG_WO,
  33005         0,
  33006         2,
  33007         soc_BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr_fields,
  33008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33009         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  33010         -1,
  33011         -1,
  33012     },
  33013 #endif /* chips */
  33014 
  33015 #if defined(BCM_88950_A0)
  33016     { /* SOC_REG_INT_BRDC_FMAC_BD_LINK_TOPO_MODE_REG_0r */
  33017         soc_block_list[101],
  33018         soc_genreg,
  33019         1,
  33020         0,
  33021         0x108,
  33022         SOC_REG_FLAG_WO,
  33023         0,
  33024         2,
  33025         soc_BRDC_FMAC_AC_LINK_TOPO_MODE_REG_0r_fields,
  33026         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  33027         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  33028         -1,
  33029         -1,
  33030     },
  33031 #endif /* chips */
  33032 
  33033 #if defined(BCM_88950_A0)
  33034     { /* SOC_REG_INT_BRDC_FMAC_BD_LINK_TOPO_MODE_REG_2r */
  33035         soc_block_list[101],
  33036         soc_genreg,
  33037         1,
  33038         0,
  33039         0x109,
  33040         SOC_REG_FLAG_WO,
  33041         0,
  33042         1,
  33043         soc_BRDC_FMAC_AC_LINK_TOPO_MODE_REG_2r_fields,
  33044         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33045         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  33046         -1,
  33047         -1,
  33048     },
  33049 #endif /* chips */
  33050 
  33051 #if defined(BCM_88950_A0)
  33052     { /* SOC_REG_INT_BRDC_FMAC_BD_LOOPBACK_ENABLE_REGISTERr */
  33053         soc_block_list[101],
  33054         soc_genreg,
  33055         1,
  33056         0,
  33057         0x100,
  33058         SOC_REG_FLAG_WO,
  33059         0,
  33060         1,
  33061         soc_BRDC_FMAC_AC_LOOPBACK_ENABLE_REGISTERr_fields,
  33062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33063         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  33064         -1,
  33065         -1,
  33066     },
  33067 #endif /* chips */
  33068 
  33069 #if defined(BCM_88950_A0)
  33070     { /* SOC_REG_INT_BRDC_FMAC_BD_RECEIVE_RESET_REGISTERr */
  33071         soc_block_list[101],
  33072         soc_genreg,
  33073         1,
  33074         0,
  33075         0x106,
  33076         SOC_REG_FLAG_WO,
  33077         0,
  33078         2,
  33079         soc_BRDC_FMAC_AC_RECEIVE_RESET_REGISTERr_fields,
  33080         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  33081         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  33082         -1,
  33083         -1,
  33084     },
  33085 #endif /* chips */
  33086 
  33087 #if defined(BCM_88950_A0)
  33088     { /* SOC_REG_INT_BRDC_FMAC_BD_REG_0102r */
  33089         soc_block_list[101],
  33090         soc_genreg,
  33091         1,
  33092         0,
  33093         0x102,
  33094         SOC_REG_FLAG_WO,
  33095         0,
  33096         1,
  33097         soc_BRDC_FMAC_AC_REG_0102r_fields,
  33098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33099         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  33100         -1,
  33101         -1,
  33102     },
  33103 #endif /* chips */
  33104 
  33105 #if defined(BCM_88950_A0)
  33106     { /* SOC_REG_INT_BRDC_FMAC_BD_REG_0116r */
  33107         soc_block_list[101],
  33108         soc_genreg,
  33109         1,
  33110         0,
  33111         0x116,
  33112         SOC_REG_FLAG_64_BITS |
  33113                           SOC_REG_FLAG_WO,
  33114         0,
  33115         1,
  33116         soc_BRDC_FMAC_AC_REG_0116r_fields,
  33117         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  33118         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  33119         -1,
  33120         -1,
  33121     },
  33122 #endif /* chips */
  33123 
  33124 #if defined(BCM_88950_A0)
  33125     { /* SOC_REG_INT_BRDC_FMAC_BD_REG_0118r */
  33126         soc_block_list[101],
  33127         soc_genreg,
  33128         1,
  33129         0,
  33130         0x118,
  33131         SOC_REG_FLAG_WO,
  33132         0,
  33133         8,
  33134         soc_BRDC_FMAC_AC_REG_0118r_fields,
  33135         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  33136         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  33137         -1,
  33138         -1,
  33139     },
  33140 #endif /* chips */
  33141 
  33142 #if defined(BCM_88950_A0)
  33143     { /* SOC_REG_INT_BRDC_FMAC_BD_REG_0119r */
  33144         soc_block_list[101],
  33145         soc_genreg,
  33146         1,
  33147         0,
  33148         0x119,
  33149         SOC_REG_FLAG_WO,
  33150         0,
  33151         1,
  33152         soc_BRDC_FMAC_AC_REG_0119r_fields,
  33153         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33154         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  33155         -1,
  33156         -1,
  33157     },
  33158 #endif /* chips */
  33159 
  33160 #if defined(BCM_88950_A0)
  33161     { /* SOC_REG_INT_BRDC_FMAC_BD_REG_0139r */
  33162         soc_block_list[101],
  33163         soc_genreg,
  33164         4,
  33165         0,
  33166         0x139,
  33167         SOC_REG_FLAG_ARRAY |
  33168                           SOC_REG_FLAG_WO |
  33169                           SOC_REG_FLAG_REG_ARRAY,
  33170         0,
  33171         10,
  33172         soc_BRDC_FMAC_AC_REG_0139r_fields,
  33173         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  33174         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  33175         -1,
  33176         -1,
  33177     },
  33178 #endif /* chips */
  33179 
  33180 #if defined(BCM_88950_A0)
  33181     { /* SOC_REG_INT_BRDC_FMAC_BD_RESERVED_MIRROR_ADDRr */
  33182         soc_block_list[101],
  33183         soc_genreg,
  33184         1,
  33185         0,
  33186         0x85,
  33187         SOC_REG_FLAG_WO,
  33188         0,
  33189         2,
  33190         soc_BRDC_CCS_RESERVED_MIRROR_ADDRr_fields,
  33191         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33192         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  33193         -1,
  33194         -1,
  33195     },
  33196 #endif /* chips */
  33197 
  33198 #if defined(BCM_88950_A0)
  33199     { /* SOC_REG_INT_BRDC_FMAC_BD_RESERVED_MTCPr */
  33200         soc_block_list[101],
  33201         soc_genreg,
  33202         1,
  33203         0,
  33204         0xad,
  33205         SOC_REG_FLAG_64_BITS |
  33206                           SOC_REG_FLAG_WO,
  33207         0,
  33208         18,
  33209         soc_BRDC_CCS_RESERVED_MTCPr_fields,
  33210         SOC_RESET_VAL_DEC(0x80000000, 0x00000001)
  33211         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
  33212         -1,
  33213         -1,
  33214     },
  33215 #endif /* chips */
  33216 
  33217 #if defined(BCM_88950_A0)
  33218     { /* SOC_REG_INT_BRDC_FMAC_BD_RESERVED_SPARE_0r */
  33219         soc_block_list[101],
  33220         soc_genreg,
  33221         1,
  33222         0,
  33223         0x90,
  33224         SOC_REG_FLAG_WO,
  33225         0,
  33226         1,
  33227         soc_BRDC_CCS_RESERVED_SPARE_0r_fields,
  33228         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  33229         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33230         -1,
  33231         -1,
  33232     },
  33233 #endif /* chips */
  33234 
  33235 #if defined(BCM_88950_A0)
  33236     { /* SOC_REG_INT_BRDC_FMAC_BD_RESERVED_SPARE_1r */
  33237         soc_block_list[101],
  33238         soc_genreg,
  33239         1,
  33240         0,
  33241         0x91,
  33242         SOC_REG_FLAG_WO,
  33243         0,
  33244         1,
  33245         soc_BRDC_CCS_RESERVED_SPARE_1r_fields,
  33246         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  33247         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33248         -1,
  33249         -1,
  33250     },
  33251 #endif /* chips */
  33252 
  33253 #if defined(BCM_88950_A0)
  33254     { /* SOC_REG_INT_BRDC_FMAC_BD_RESERVED_SPARE_2r */
  33255         soc_block_list[101],
  33256         soc_genreg,
  33257         1,
  33258         0,
  33259         0x92,
  33260         SOC_REG_FLAG_WO,
  33261         0,
  33262         1,
  33263         soc_BRDC_CCS_RESERVED_SPARE_2r_fields,
  33264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33266         -1,
  33267         -1,
  33268     },
  33269 #endif /* chips */
  33270 
  33271 #if defined(BCM_88950_A0)
  33272     { /* SOC_REG_INT_BRDC_FMAC_BD_RESERVED_SPARE_3r */
  33273         soc_block_list[101],
  33274         soc_genreg,
  33275         1,
  33276         0,
  33277         0x93,
  33278         SOC_REG_FLAG_WO,
  33279         0,
  33280         1,
  33281         soc_BRDC_CCS_RESERVED_SPARE_3r_fields,
  33282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33283         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33284         -1,
  33285         -1,
  33286     },
  33287 #endif /* chips */
  33288 
  33289 #if defined(BCM_88950_A0)
  33290     { /* SOC_REG_INT_BRDC_FMAC_BD_RSF_CONFIGURATIONr */
  33291         soc_block_list[101],
  33292         soc_genreg,
  33293         4,
  33294         0,
  33295         0x194,
  33296         SOC_REG_FLAG_64_BITS |
  33297                           SOC_REG_FLAG_ARRAY |
  33298                           SOC_REG_FLAG_WO |
  33299                           SOC_REG_FLAG_REG_ARRAY,
  33300         0,
  33301         20,
  33302         soc_BRDC_FMAC_AC_RSF_CONFIGURATIONr_fields,
  33303         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  33304         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  33305         -1,
  33306         -1,
  33307     },
  33308 #endif /* chips */
  33309 
  33310 #if defined(BCM_88950_A0)
  33311     { /* SOC_REG_INT_BRDC_FMAC_BD_RSF_STATUSr */
  33312         soc_block_list[101],
  33313         soc_genreg,
  33314         4,
  33315         0,
  33316         0x19c,
  33317         SOC_REG_FLAG_64_BITS |
  33318                           SOC_REG_FLAG_ARRAY |
  33319                           SOC_REG_FLAG_RO |
  33320                           SOC_REG_FLAG_WO |
  33321                           SOC_REG_FLAG_REG_ARRAY,
  33322         0,
  33323         2,
  33324         soc_BRDC_FMAC_AC_RSF_STATUSr_fields,
  33325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33326         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  33327         -1,
  33328         -1,
  33329     },
  33330 #endif /* chips */
  33331 
  33332 #if defined(BCM_88950_A0)
  33333     { /* SOC_REG_INT_BRDC_FMAC_BD_SBUS_BROADCAST_IDr */
  33334         soc_block_list[101],
  33335         soc_genreg,
  33336         1,
  33337         0,
  33338         0x86,
  33339         SOC_REG_FLAG_WO,
  33340         0,
  33341         1,
  33342         soc_BRDC_FMAC_AC_SBUS_BROADCAST_IDr_fields,
  33343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33344         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  33345         -1,
  33346         -1,
  33347     },
  33348 #endif /* chips */
  33349 
  33350 #if defined(BCM_88950_A0)
  33351     { /* SOC_REG_INT_BRDC_FMAC_BD_SBUS_LAST_IN_CHAINr */
  33352         soc_block_list[101],
  33353         soc_genreg,
  33354         1,
  33355         0,
  33356         0x87,
  33357         SOC_REG_FLAG_WO,
  33358         0,
  33359         1,
  33360         soc_BRDC_CCS_SBUS_LAST_IN_CHAINr_fields,
  33361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33362         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  33363         -1,
  33364         -1,
  33365     },
  33366 #endif /* chips */
  33367 
  33368 #if defined(BCM_88950_A0)
  33369     { /* SOC_REG_INT_BRDC_FMAC_BD_TX_CELL_LIMITr */
  33370         soc_block_list[101],
  33371         soc_genreg,
  33372         1,
  33373         0,
  33374         0x10a,
  33375         SOC_REG_FLAG_64_BITS |
  33376                           SOC_REG_FLAG_WO,
  33377         0,
  33378         3,
  33379         soc_BRDC_FMAC_AC_TX_CELL_LIMITr_fields,
  33380         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  33381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  33382         -1,
  33383         -1,
  33384     },
  33385 #endif /* chips */
  33386 
  33387 #if defined(BCM_88650_A0)
  33388     { /* SOC_REG_INT_BRDC_FMAC_BEC_CONFIGURATIONr */
  33389         soc_block_list[23],
  33390         soc_genreg,
  33391         4,
  33392         0,
  33393         0x1a0,
  33394         SOC_REG_FLAG_ARRAY |
  33395                           SOC_REG_FLAG_WO |
  33396                           SOC_REG_FLAG_REG_ARRAY,
  33397         0,
  33398         7,
  33399         soc_BRDC_FMAC_BEC_CONFIGURATIONr_fields,
  33400         SOC_RESET_VAL_DEC(0xf1015084, 0x00000000)
  33401         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33402         -1,
  33403         -1,
  33404     },
  33405 #endif /* chips */
  33406 
  33407 #if defined(BCM_88202_A0)
  33408     { /* SOC_REG_INT_BRDC_FMAC_BEC_CONFIGURATION_BCM88202_A0r */
  33409         soc_block_list[23],
  33410         soc_genreg,
  33411         4,
  33412         0,
  33413         0x1a0,
  33414         SOC_REG_FLAG_ARRAY |
  33415                           SOC_REG_FLAG_WO |
  33416                           SOC_REG_FLAG_REG_ARRAY,
  33417         0,
  33418         7,
  33419         soc_BRDC_FMAC_BEC_CONFIGURATION_BCM88202_A0r_fields,
  33420         SOC_RESET_VAL_DEC(0xf1015084, 0x00000000)
  33421         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33422         -1,
  33423         -1,
  33424     },
  33425 #endif /* chips */
  33426 
  33427 #if defined(BCM_88650_B0)
  33428     { /* SOC_REG_INT_BRDC_FMAC_BEC_CONFIGURATION_BCM88650_B0r */
  33429         soc_block_list[23],
  33430         soc_genreg,
  33431         4,
  33432         0,
  33433         0x1a0,
  33434         SOC_REG_FLAG_ARRAY |
  33435                           SOC_REG_FLAG_WO |
  33436                           SOC_REG_FLAG_REG_ARRAY,
  33437         0,
  33438         7,
  33439         soc_BRDC_FMAC_BEC_CONFIGURATION_BCM88650_B0r_fields,
  33440         SOC_RESET_VAL_DEC(0xf1015084, 0x00000000)
  33441         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33442         -1,
  33443         -1,
  33444     },
  33445 #endif /* chips */
  33446 
  33447 #if defined(BCM_88660_A0)
  33448     { /* SOC_REG_INT_BRDC_FMAC_BEC_CONFIGURATION_BCM88660_A0r */
  33449         soc_block_list[23],
  33450         soc_genreg,
  33451         4,
  33452         0,
  33453         0x1a0,
  33454         SOC_REG_FLAG_ARRAY |
  33455                           SOC_REG_FLAG_WO |
  33456                           SOC_REG_FLAG_REG_ARRAY,
  33457         0,
  33458         7,
  33459         soc_BRDC_FMAC_BEC_CONFIGURATION_BCM88660_A0r_fields,
  33460         SOC_RESET_VAL_DEC(0xf1015084, 0x00000000)
  33461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33462         -1,
  33463         -1,
  33464     },
  33465 #endif /* chips */
  33466 
  33467 #if defined(BCM_88650_A0)
  33468     { /* SOC_REG_INT_BRDC_FMAC_BEC_STATUSr */
  33469         soc_block_list[23],
  33470         soc_genreg,
  33471         4,
  33472         0,
  33473         0x1a4,
  33474         SOC_REG_FLAG_ARRAY |
  33475                           SOC_REG_FLAG_WO |
  33476                           SOC_REG_FLAG_REG_ARRAY,
  33477         0,
  33478         9,
  33479         soc_BRDC_FMAC_BEC_STATUSr_fields,
  33480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33481         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  33482         -1,
  33483         -1,
  33484     },
  33485 #endif /* chips */
  33486 
  33487 #if defined(BCM_88202_A0)
  33488     { /* SOC_REG_INT_BRDC_FMAC_BEC_STATUS_BCM88202_A0r */
  33489         soc_block_list[23],
  33490         soc_genreg,
  33491         4,
  33492         0,
  33493         0x1a4,
  33494         SOC_REG_FLAG_ARRAY |
  33495                           SOC_REG_FLAG_WO |
  33496                           SOC_REG_FLAG_REG_ARRAY,
  33497         0,
  33498         9,
  33499         soc_BRDC_FMAC_BEC_STATUS_BCM88202_A0r_fields,
  33500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33501         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  33502         -1,
  33503         -1,
  33504     },
  33505 #endif /* chips */
  33506 
  33507 #if defined(BCM_88650_B0)
  33508     { /* SOC_REG_INT_BRDC_FMAC_BEC_STATUS_BCM88650_B0r */
  33509         soc_block_list[23],
  33510         soc_genreg,
  33511         4,
  33512         0,
  33513         0x1a4,
  33514         SOC_REG_FLAG_ARRAY |
  33515                           SOC_REG_FLAG_WO |
  33516                           SOC_REG_FLAG_REG_ARRAY,
  33517         0,
  33518         9,
  33519         soc_BRDC_FMAC_BEC_STATUS_BCM88650_B0r_fields,
  33520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33521         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  33522         -1,
  33523         -1,
  33524     },
  33525 #endif /* chips */
  33526 
  33527 #if defined(BCM_88660_A0)
  33528     { /* SOC_REG_INT_BRDC_FMAC_BEC_STATUS_BCM88660_A0r */
  33529         soc_block_list[23],
  33530         soc_genreg,
  33531         4,
  33532         0,
  33533         0x1a4,
  33534         SOC_REG_FLAG_ARRAY |
  33535                           SOC_REG_FLAG_WO |
  33536                           SOC_REG_FLAG_REG_ARRAY,
  33537         0,
  33538         9,
  33539         soc_BRDC_FMAC_BEC_STATUS_BCM88660_A0r_fields,
  33540         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33541         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  33542         -1,
  33543         -1,
  33544     },
  33545 #endif /* chips */
  33546 
  33547 #if defined(BCM_88650_A0)
  33548     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAPr */
  33549         soc_block_list[23],
  33550         soc_genreg,
  33551         1,
  33552         0,
  33553         0x9b,
  33554         SOC_REG_FLAG_64_BITS |
  33555                           SOC_REG_FLAG_WO,
  33556         0,
  33557         1,
  33558         soc_BRDC_FMAC_BER_GEN_BITMAPr_fields,
  33559         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33560         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  33561         -1,
  33562         -1,
  33563     },
  33564 #endif /* chips */
  33565 
  33566 #if defined(BCM_83208_A0)
  33567     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM83208_A0r */
  33568         soc_block_list[23],
  33569         soc_genreg,
  33570         1,
  33571         0,
  33572         0x12f,
  33573         SOC_REG_FLAG_ABOVE_64_BITS |
  33574                           SOC_REG_FLAG_WO,
  33575         0,
  33576         1,
  33577         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM83208_A0r_fields,
  33578         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33579         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33580         -1,
  33581         -1,
  33582     },
  33583 #endif /* chips */
  33584 
  33585 #if defined(BCM_88202_A0)
  33586     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88202_A0r */
  33587         soc_block_list[23],
  33588         soc_genreg,
  33589         1,
  33590         0,
  33591         0x9b,
  33592         SOC_REG_FLAG_64_BITS |
  33593                           SOC_REG_FLAG_WO,
  33594         0,
  33595         1,
  33596         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88202_A0r_fields,
  33597         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33598         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  33599         -1,
  33600         -1,
  33601     },
  33602 #endif /* chips */
  33603 
  33604 #if defined(BCM_88375_A0)
  33605     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88375_A0r */
  33606         soc_block_list[23],
  33607         soc_genreg,
  33608         1,
  33609         0,
  33610         0x11b,
  33611         SOC_REG_FLAG_64_BITS |
  33612                           SOC_REG_FLAG_WO,
  33613         0,
  33614         1,
  33615         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88375_A0r_fields,
  33616         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33617         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  33618         -1,
  33619         -1,
  33620     },
  33621 #endif /* chips */
  33622 
  33623 #if defined(BCM_88375_B0)
  33624     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88375_B0r */
  33625         soc_block_list[23],
  33626         soc_genreg,
  33627         1,
  33628         0,
  33629         0x11b,
  33630         SOC_REG_FLAG_64_BITS |
  33631                           SOC_REG_FLAG_WO,
  33632         0,
  33633         1,
  33634         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88375_B0r_fields,
  33635         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33636         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  33637         -1,
  33638         -1,
  33639     },
  33640 #endif /* chips */
  33641 
  33642 #if defined(BCM_88470_A0)
  33643     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88470_A0r */
  33644         soc_block_list[23],
  33645         soc_genreg,
  33646         1,
  33647         0,
  33648         0x11f,
  33649         SOC_REG_FLAG_64_BITS |
  33650                           SOC_REG_FLAG_WO,
  33651         0,
  33652         1,
  33653         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88470_A0r_fields,
  33654         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33655         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  33656         -1,
  33657         -1,
  33658     },
  33659 #endif /* chips */
  33660 
  33661 #if defined(BCM_88470_B0)
  33662     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88470_B0r */
  33663         soc_block_list[23],
  33664         soc_genreg,
  33665         1,
  33666         0,
  33667         0x11f,
  33668         SOC_REG_FLAG_64_BITS |
  33669                           SOC_REG_FLAG_WO,
  33670         0,
  33671         1,
  33672         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88470_B0r_fields,
  33673         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33674         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  33675         -1,
  33676         -1,
  33677     },
  33678 #endif /* chips */
  33679 
  33680 #if defined(BCM_88650_B0)
  33681     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88650_B0r */
  33682         soc_block_list[23],
  33683         soc_genreg,
  33684         1,
  33685         0,
  33686         0x9b,
  33687         SOC_REG_FLAG_64_BITS |
  33688                           SOC_REG_FLAG_WO,
  33689         0,
  33690         1,
  33691         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88650_B0r_fields,
  33692         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33693         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  33694         -1,
  33695         -1,
  33696     },
  33697 #endif /* chips */
  33698 
  33699 #if defined(BCM_88660_A0)
  33700     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88660_A0r */
  33701         soc_block_list[23],
  33702         soc_genreg,
  33703         1,
  33704         0,
  33705         0x9b,
  33706         SOC_REG_FLAG_64_BITS |
  33707                           SOC_REG_FLAG_WO,
  33708         0,
  33709         1,
  33710         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88660_A0r_fields,
  33711         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33712         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  33713         -1,
  33714         -1,
  33715     },
  33716 #endif /* chips */
  33717 
  33718 #if defined(BCM_88675_A0)
  33719     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88675_A0r */
  33720         soc_block_list[23],
  33721         soc_genreg,
  33722         1,
  33723         0,
  33724         0x11b,
  33725         SOC_REG_FLAG_64_BITS |
  33726                           SOC_REG_FLAG_WO,
  33727         0,
  33728         1,
  33729         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88675_A0r_fields,
  33730         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33731         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  33732         -1,
  33733         -1,
  33734     },
  33735 #endif /* chips */
  33736 
  33737 #if defined(BCM_88675_B0)
  33738     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88675_B0r */
  33739         soc_block_list[23],
  33740         soc_genreg,
  33741         1,
  33742         0,
  33743         0x11b,
  33744         SOC_REG_FLAG_64_BITS |
  33745                           SOC_REG_FLAG_WO,
  33746         0,
  33747         1,
  33748         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88675_B0r_fields,
  33749         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33750         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  33751         -1,
  33752         -1,
  33753     },
  33754 #endif /* chips */
  33755 
  33756 #if defined(BCM_88680_A0)
  33757     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88680_A0r */
  33758         soc_block_list[23],
  33759         soc_genreg,
  33760         1,
  33761         0,
  33762         0x11b,
  33763         SOC_REG_FLAG_64_BITS |
  33764                           SOC_REG_FLAG_WO,
  33765         0,
  33766         1,
  33767         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88680_A0r_fields,
  33768         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  33769         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  33770         -1,
  33771         -1,
  33772     },
  33773 #endif /* chips */
  33774 
  33775 #if defined(BCM_88690_A0)
  33776     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88690_A0r */
  33777         soc_block_list[23],
  33778         soc_genreg,
  33779         1,
  33780         0,
  33781         0x167,
  33782         SOC_REG_FLAG_ABOVE_64_BITS |
  33783                           SOC_REG_FLAG_WO,
  33784         0,
  33785         1,
  33786         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88690_A0r_fields,
  33787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33788         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33789         -1,
  33790         -1,
  33791     },
  33792 #endif /* chips */
  33793 
  33794 #if defined(BCM_88690_B0)
  33795     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88690_B0r */
  33796         soc_block_list[23],
  33797         soc_genreg,
  33798         1,
  33799         0,
  33800         0x167,
  33801         SOC_REG_FLAG_ABOVE_64_BITS |
  33802                           SOC_REG_FLAG_WO,
  33803         0,
  33804         1,
  33805         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88690_B0r_fields,
  33806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33807         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33808         -1,
  33809         -1,
  33810     },
  33811 #endif /* chips */
  33812 
  33813 #if defined(BCM_88790_A0)
  33814     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_BITMAP_BCM88790_A0r */
  33815         soc_block_list[23],
  33816         soc_genreg,
  33817         1,
  33818         0,
  33819         0x167,
  33820         SOC_REG_FLAG_ABOVE_64_BITS |
  33821                           SOC_REG_FLAG_WO,
  33822         0,
  33823         1,
  33824         soc_BRDC_FMAC_BER_GEN_BITMAP_BCM88790_A0r_fields,
  33825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  33826         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  33827         -1,
  33828         -1,
  33829     },
  33830 #endif /* chips */
  33831 
  33832 #if defined(BCM_88650_A0)
  33833     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIODr */
  33834         soc_block_list[23],
  33835         soc_genreg,
  33836         1,
  33837         0,
  33838         0x9a,
  33839         SOC_REG_FLAG_WO,
  33840         0,
  33841         1,
  33842         soc_BRDC_FMAC_BER_GEN_PERIODr_fields,
  33843         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33844         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33845         -1,
  33846         -1,
  33847     },
  33848 #endif /* chips */
  33849 
  33850 #if defined(BCM_83208_A0)
  33851     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM83208_A0r */
  33852         soc_block_list[23],
  33853         soc_genreg,
  33854         1,
  33855         0,
  33856         0x12e,
  33857         SOC_REG_FLAG_WO,
  33858         0,
  33859         1,
  33860         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM83208_A0r_fields,
  33861         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33862         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33863         -1,
  33864         -1,
  33865     },
  33866 #endif /* chips */
  33867 
  33868 #if defined(BCM_88202_A0)
  33869     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88202_A0r */
  33870         soc_block_list[23],
  33871         soc_genreg,
  33872         1,
  33873         0,
  33874         0x9a,
  33875         SOC_REG_FLAG_WO,
  33876         0,
  33877         1,
  33878         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88202_A0r_fields,
  33879         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33880         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33881         -1,
  33882         -1,
  33883     },
  33884 #endif /* chips */
  33885 
  33886 #if defined(BCM_88375_A0)
  33887     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88375_A0r */
  33888         soc_block_list[23],
  33889         soc_genreg,
  33890         1,
  33891         0,
  33892         0x11a,
  33893         SOC_REG_FLAG_WO,
  33894         0,
  33895         1,
  33896         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88375_A0r_fields,
  33897         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33898         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33899         -1,
  33900         -1,
  33901     },
  33902 #endif /* chips */
  33903 
  33904 #if defined(BCM_88375_B0)
  33905     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88375_B0r */
  33906         soc_block_list[23],
  33907         soc_genreg,
  33908         1,
  33909         0,
  33910         0x11a,
  33911         SOC_REG_FLAG_WO,
  33912         0,
  33913         1,
  33914         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88375_B0r_fields,
  33915         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33916         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33917         -1,
  33918         -1,
  33919     },
  33920 #endif /* chips */
  33921 
  33922 #if defined(BCM_88470_A0)
  33923     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88470_A0r */
  33924         soc_block_list[23],
  33925         soc_genreg,
  33926         1,
  33927         0,
  33928         0x11e,
  33929         SOC_REG_FLAG_WO,
  33930         0,
  33931         1,
  33932         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88470_A0r_fields,
  33933         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33935         -1,
  33936         -1,
  33937     },
  33938 #endif /* chips */
  33939 
  33940 #if defined(BCM_88470_B0)
  33941     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88470_B0r */
  33942         soc_block_list[23],
  33943         soc_genreg,
  33944         1,
  33945         0,
  33946         0x11e,
  33947         SOC_REG_FLAG_WO,
  33948         0,
  33949         1,
  33950         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88470_B0r_fields,
  33951         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33952         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33953         -1,
  33954         -1,
  33955     },
  33956 #endif /* chips */
  33957 
  33958 #if defined(BCM_88650_B0)
  33959     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88650_B0r */
  33960         soc_block_list[23],
  33961         soc_genreg,
  33962         1,
  33963         0,
  33964         0x9a,
  33965         SOC_REG_FLAG_WO,
  33966         0,
  33967         1,
  33968         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88650_B0r_fields,
  33969         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33971         -1,
  33972         -1,
  33973     },
  33974 #endif /* chips */
  33975 
  33976 #if defined(BCM_88660_A0)
  33977     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88660_A0r */
  33978         soc_block_list[23],
  33979         soc_genreg,
  33980         1,
  33981         0,
  33982         0x9a,
  33983         SOC_REG_FLAG_WO,
  33984         0,
  33985         1,
  33986         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88660_A0r_fields,
  33987         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  33988         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  33989         -1,
  33990         -1,
  33991     },
  33992 #endif /* chips */
  33993 
  33994 #if defined(BCM_88675_A0)
  33995     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88675_A0r */
  33996         soc_block_list[23],
  33997         soc_genreg,
  33998         1,
  33999         0,
  34000         0x11a,
  34001         SOC_REG_FLAG_WO,
  34002         0,
  34003         1,
  34004         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88675_A0r_fields,
  34005         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  34006         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34007         -1,
  34008         -1,
  34009     },
  34010 #endif /* chips */
  34011 
  34012 #if defined(BCM_88675_B0)
  34013     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88675_B0r */
  34014         soc_block_list[23],
  34015         soc_genreg,
  34016         1,
  34017         0,
  34018         0x11a,
  34019         SOC_REG_FLAG_WO,
  34020         0,
  34021         1,
  34022         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88675_B0r_fields,
  34023         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  34024         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34025         -1,
  34026         -1,
  34027     },
  34028 #endif /* chips */
  34029 
  34030 #if defined(BCM_88680_A0)
  34031     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88680_A0r */
  34032         soc_block_list[23],
  34033         soc_genreg,
  34034         1,
  34035         0,
  34036         0x11a,
  34037         SOC_REG_FLAG_WO,
  34038         0,
  34039         1,
  34040         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88680_A0r_fields,
  34041         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  34042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34043         -1,
  34044         -1,
  34045     },
  34046 #endif /* chips */
  34047 
  34048 #if defined(BCM_88690_A0)
  34049     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88690_A0r */
  34050         soc_block_list[23],
  34051         soc_genreg,
  34052         1,
  34053         0,
  34054         0x166,
  34055         SOC_REG_FLAG_WO,
  34056         0,
  34057         1,
  34058         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88690_A0r_fields,
  34059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34060         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34061         -1,
  34062         -1,
  34063     },
  34064 #endif /* chips */
  34065 
  34066 #if defined(BCM_88690_B0)
  34067     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88690_B0r */
  34068         soc_block_list[23],
  34069         soc_genreg,
  34070         1,
  34071         0,
  34072         0x166,
  34073         SOC_REG_FLAG_WO,
  34074         0,
  34075         1,
  34076         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88690_B0r_fields,
  34077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34079         -1,
  34080         -1,
  34081     },
  34082 #endif /* chips */
  34083 
  34084 #if defined(BCM_88790_A0)
  34085     { /* SOC_REG_INT_BRDC_FMAC_BER_GEN_PERIOD_BCM88790_A0r */
  34086         soc_block_list[23],
  34087         soc_genreg,
  34088         1,
  34089         0,
  34090         0x166,
  34091         SOC_REG_FLAG_WO,
  34092         0,
  34093         1,
  34094         soc_BRDC_FMAC_BER_GEN_PERIOD_BCM88790_A0r_fields,
  34095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34097         -1,
  34098         -1,
  34099     },
  34100 #endif /* chips */
  34101 
  34102 #if defined(BCM_88650_A0)
  34103     { /* SOC_REG_INT_BRDC_FMAC_CNTRL_INTRLVD_MODE_REGr */
  34104         soc_block_list[23],
  34105         soc_genreg,
  34106         1,
  34107         0,
  34108         0x32,
  34109         SOC_REG_FLAG_WO,
  34110         0,
  34111         1,
  34112         soc_BRDC_FMAC_CNTRL_INTRLVD_MODE_REGr_fields,
  34113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34114         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  34115         -1,
  34116         -1,
  34117     },
  34118 #endif /* chips */
  34119 
  34120 #if defined(BCM_88202_A0)
  34121     { /* SOC_REG_INT_BRDC_FMAC_CNTRL_INTRLVD_MODE_REG_BCM88202_A0r */
  34122         soc_block_list[23],
  34123         soc_genreg,
  34124         1,
  34125         0,
  34126         0x32,
  34127         SOC_REG_FLAG_WO,
  34128         0,
  34129         1,
  34130         soc_BRDC_FMAC_CNTRL_INTRLVD_MODE_REG_BCM88202_A0r_fields,
  34131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34132         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  34133         -1,
  34134         -1,
  34135     },
  34136 #endif /* chips */
  34137 
  34138 #if defined(BCM_88650_B0)
  34139     { /* SOC_REG_INT_BRDC_FMAC_CNTRL_INTRLVD_MODE_REG_BCM88650_B0r */
  34140         soc_block_list[23],
  34141         soc_genreg,
  34142         1,
  34143         0,
  34144         0x32,
  34145         SOC_REG_FLAG_WO,
  34146         0,
  34147         1,
  34148         soc_BRDC_FMAC_CNTRL_INTRLVD_MODE_REG_BCM88650_B0r_fields,
  34149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34150         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  34151         -1,
  34152         -1,
  34153     },
  34154 #endif /* chips */
  34155 
  34156 #if defined(BCM_88660_A0)
  34157     { /* SOC_REG_INT_BRDC_FMAC_CNTRL_INTRLVD_MODE_REG_BCM88660_A0r */
  34158         soc_block_list[23],
  34159         soc_genreg,
  34160         1,
  34161         0,
  34162         0x32,
  34163         SOC_REG_FLAG_WO,
  34164         0,
  34165         1,
  34166         soc_BRDC_FMAC_CNTRL_INTRLVD_MODE_REG_BCM88660_A0r_fields,
  34167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34168         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  34169         -1,
  34170         -1,
  34171     },
  34172 #endif /* chips */
  34173 
  34174 #if defined(BCM_88650_A0)
  34175     { /* SOC_REG_INT_BRDC_FMAC_CONTROL_CELL_BURST_REGISTERr */
  34176         soc_block_list[23],
  34177         soc_genreg,
  34178         1,
  34179         0,
  34180         0x62,
  34181         SOC_REG_FLAG_WO,
  34182         0,
  34183         3,
  34184         soc_BRDC_FMAC_CONTROL_CELL_BURST_REGISTERr_fields,
  34185         SOC_RESET_VAL_DEC(0x0001c008, 0x00000000)
  34186         SOC_RESET_MASK_DEC(0x000ff3ff, 0x00000000)
  34187         -1,
  34188         -1,
  34189     },
  34190 #endif /* chips */
  34191 
  34192 #if defined(BCM_88202_A0)
  34193     { /* SOC_REG_INT_BRDC_FMAC_CONTROL_CELL_BURST_REGISTER_BCM88202_A0r */
  34194         soc_block_list[23],
  34195         soc_genreg,
  34196         1,
  34197         0,
  34198         0x62,
  34199         SOC_REG_FLAG_WO,
  34200         0,
  34201         3,
  34202         soc_BRDC_FMAC_CONTROL_CELL_BURST_REGISTER_BCM88202_A0r_fields,
  34203         SOC_RESET_VAL_DEC(0x0001c008, 0x00000000)
  34204         SOC_RESET_MASK_DEC(0x000ff3ff, 0x00000000)
  34205         -1,
  34206         -1,
  34207     },
  34208 #endif /* chips */
  34209 
  34210 #if defined(BCM_88650_B0)
  34211     { /* SOC_REG_INT_BRDC_FMAC_CONTROL_CELL_BURST_REGISTER_BCM88650_B0r */
  34212         soc_block_list[23],
  34213         soc_genreg,
  34214         1,
  34215         0,
  34216         0x62,
  34217         SOC_REG_FLAG_WO,
  34218         0,
  34219         3,
  34220         soc_BRDC_FMAC_CONTROL_CELL_BURST_REGISTER_BCM88650_B0r_fields,
  34221         SOC_RESET_VAL_DEC(0x0001c008, 0x00000000)
  34222         SOC_RESET_MASK_DEC(0x000ff3ff, 0x00000000)
  34223         -1,
  34224         -1,
  34225     },
  34226 #endif /* chips */
  34227 
  34228 #if defined(BCM_88660_A0)
  34229     { /* SOC_REG_INT_BRDC_FMAC_CONTROL_CELL_BURST_REGISTER_BCM88660_A0r */
  34230         soc_block_list[23],
  34231         soc_genreg,
  34232         1,
  34233         0,
  34234         0x62,
  34235         SOC_REG_FLAG_WO,
  34236         0,
  34237         3,
  34238         soc_BRDC_FMAC_CONTROL_CELL_BURST_REGISTER_BCM88660_A0r_fields,
  34239         SOC_RESET_VAL_DEC(0x0001c008, 0x00000000)
  34240         SOC_RESET_MASK_DEC(0x000ff3ff, 0x00000000)
  34241         -1,
  34242         -1,
  34243     },
  34244 #endif /* chips */
  34245 
  34246 #if defined(BCM_88790_A0)
  34247     { /* SOC_REG_INT_BRDC_FMAC_DATA_FIFO_WMKr */
  34248         soc_block_list[23],
  34249         soc_genreg,
  34250         4,
  34251         0,
  34252         0x11d,
  34253         SOC_REG_FLAG_ARRAY |
  34254                           SOC_REG_FLAG_WO |
  34255                           SOC_REG_FLAG_REG_ARRAY,
  34256         0,
  34257         4,
  34258         soc_BRDC_FMAC_DATA_FIFO_WMKr_fields,
  34259         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34260         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34261         -1,
  34262         -1,
  34263     },
  34264 #endif /* chips */
  34265 
  34266 #if defined(BCM_88690_A0)
  34267     { /* SOC_REG_INT_BRDC_FMAC_DATA_FIFO_WMK_BCM88690_A0r */
  34268         soc_block_list[23],
  34269         soc_genreg,
  34270         4,
  34271         0,
  34272         0x11d,
  34273         SOC_REG_FLAG_ARRAY |
  34274                           SOC_REG_FLAG_WO |
  34275                           SOC_REG_FLAG_REG_ARRAY,
  34276         SOC_REG_FLAG_INIT_ON_READ,
  34277         4,
  34278         soc_BRDC_FMAC_DATA_FIFO_WMK_BCM88690_A0r_fields,
  34279         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34280         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34281         -1,
  34282         -1,
  34283     },
  34284 #endif /* chips */
  34285 
  34286 #if defined(BCM_88690_B0)
  34287     { /* SOC_REG_INT_BRDC_FMAC_DATA_FIFO_WMK_BCM88690_B0r */
  34288         soc_block_list[23],
  34289         soc_genreg,
  34290         4,
  34291         0,
  34292         0x11d,
  34293         SOC_REG_FLAG_ARRAY |
  34294                           SOC_REG_FLAG_WO |
  34295                           SOC_REG_FLAG_REG_ARRAY,
  34296         SOC_REG_FLAG_INIT_ON_READ,
  34297         4,
  34298         soc_BRDC_FMAC_DATA_FIFO_WMK_BCM88690_B0r_fields,
  34299         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34300         SOC_RESET_MASK_DEC(0x00000ff7, 0x00000000)
  34301         -1,
  34302         -1,
  34303     },
  34304 #endif /* chips */
  34305 
  34306 #if defined(BCM_88650_A0)
  34307     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_ADDRr */
  34308         soc_block_list[23],
  34309         soc_genreg,
  34310         1,
  34311         0,
  34312         0x1e1,
  34313         SOC_REG_FLAG_WO,
  34314         0,
  34315         2,
  34316         soc_BRDC_FMAC_ECC_1B_ERR_ADDRr_fields,
  34317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34318         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34319         -1,
  34320         -1,
  34321     },
  34322 #endif /* chips */
  34323 
  34324 #if defined(BCM_88202_A0)
  34325     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_ADDR_BCM88202_A0r */
  34326         soc_block_list[23],
  34327         soc_genreg,
  34328         1,
  34329         0,
  34330         0x1e1,
  34331         SOC_REG_FLAG_WO,
  34332         0,
  34333         2,
  34334         soc_BRDC_FMAC_ECC_1B_ERR_ADDR_BCM88202_A0r_fields,
  34335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34336         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34337         -1,
  34338         -1,
  34339     },
  34340 #endif /* chips */
  34341 
  34342 #if defined(BCM_88650_B0)
  34343     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_ADDR_BCM88650_B0r */
  34344         soc_block_list[23],
  34345         soc_genreg,
  34346         1,
  34347         0,
  34348         0x1e1,
  34349         SOC_REG_FLAG_WO,
  34350         0,
  34351         2,
  34352         soc_BRDC_FMAC_ECC_1B_ERR_ADDR_BCM88650_B0r_fields,
  34353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34354         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34355         -1,
  34356         -1,
  34357     },
  34358 #endif /* chips */
  34359 
  34360 #if defined(BCM_88660_A0)
  34361     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_ADDR_BCM88660_A0r */
  34362         soc_block_list[23],
  34363         soc_genreg,
  34364         1,
  34365         0,
  34366         0x1e1,
  34367         SOC_REG_FLAG_WO,
  34368         0,
  34369         2,
  34370         soc_BRDC_FMAC_ECC_1B_ERR_ADDR_BCM88660_A0r_fields,
  34371         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34372         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34373         -1,
  34374         -1,
  34375     },
  34376 #endif /* chips */
  34377 
  34378 #if defined(BCM_88675_A0)
  34379     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNTr */
  34380         soc_block_list[23],
  34381         soc_genreg,
  34382         1,
  34383         0,
  34384         0x94,
  34385         SOC_REG_FLAG_64_BITS |
  34386                           SOC_REG_FLAG_RO |
  34387                           SOC_REG_FLAG_WO,
  34388         0,
  34389         4,
  34390         soc_BRDC_FMAC_ECC_1B_ERR_CNTr_fields,
  34391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34392         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34393         -1,
  34394         -1,
  34395     },
  34396 #endif /* chips */
  34397 
  34398 #if defined(BCM_83208_A0)
  34399     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM83208_A0r */
  34400         soc_block_list[23],
  34401         soc_genreg,
  34402         1,
  34403         0,
  34404         0x94,
  34405         SOC_REG_FLAG_64_BITS |
  34406                           SOC_REG_FLAG_RO |
  34407                           SOC_REG_FLAG_WO,
  34408         0,
  34409         4,
  34410         soc_AM_TOP_ECC_1B_ERR_CNTr_fields,
  34411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34412         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34413         -1,
  34414         -1,
  34415     },
  34416 #endif /* chips */
  34417 
  34418 #if defined(BCM_88375_A0)
  34419     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88375_A0r */
  34420         soc_block_list[23],
  34421         soc_genreg,
  34422         1,
  34423         0,
  34424         0x94,
  34425         SOC_REG_FLAG_64_BITS |
  34426                           SOC_REG_FLAG_RO |
  34427                           SOC_REG_FLAG_WO,
  34428         0,
  34429         4,
  34430         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88375_A0r_fields,
  34431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34432         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34433         -1,
  34434         -1,
  34435     },
  34436 #endif /* chips */
  34437 
  34438 #if defined(BCM_88375_B0)
  34439     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88375_B0r */
  34440         soc_block_list[23],
  34441         soc_genreg,
  34442         1,
  34443         0,
  34444         0x94,
  34445         SOC_REG_FLAG_64_BITS |
  34446                           SOC_REG_FLAG_RO |
  34447                           SOC_REG_FLAG_WO,
  34448         0,
  34449         4,
  34450         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88375_B0r_fields,
  34451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34452         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34453         -1,
  34454         -1,
  34455     },
  34456 #endif /* chips */
  34457 
  34458 #if defined(BCM_88470_A0)
  34459     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88470_A0r */
  34460         soc_block_list[23],
  34461         soc_genreg,
  34462         1,
  34463         0,
  34464         0x94,
  34465         SOC_REG_FLAG_64_BITS |
  34466                           SOC_REG_FLAG_RO |
  34467                           SOC_REG_FLAG_WO,
  34468         0,
  34469         4,
  34470         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88470_A0r_fields,
  34471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34472         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34473         -1,
  34474         -1,
  34475     },
  34476 #endif /* chips */
  34477 
  34478 #if defined(BCM_88470_B0)
  34479     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88470_B0r */
  34480         soc_block_list[23],
  34481         soc_genreg,
  34482         1,
  34483         0,
  34484         0x94,
  34485         SOC_REG_FLAG_64_BITS |
  34486                           SOC_REG_FLAG_RO |
  34487                           SOC_REG_FLAG_WO,
  34488         0,
  34489         4,
  34490         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88470_B0r_fields,
  34491         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34492         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34493         -1,
  34494         -1,
  34495     },
  34496 #endif /* chips */
  34497 
  34498 #if defined(BCM_88675_B0)
  34499     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88675_B0r */
  34500         soc_block_list[23],
  34501         soc_genreg,
  34502         1,
  34503         0,
  34504         0x94,
  34505         SOC_REG_FLAG_64_BITS |
  34506                           SOC_REG_FLAG_RO |
  34507                           SOC_REG_FLAG_WO,
  34508         0,
  34509         4,
  34510         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88675_B0r_fields,
  34511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34512         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34513         -1,
  34514         -1,
  34515     },
  34516 #endif /* chips */
  34517 
  34518 #if defined(BCM_88680_A0)
  34519     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88680_A0r */
  34520         soc_block_list[23],
  34521         soc_genreg,
  34522         1,
  34523         0,
  34524         0x94,
  34525         SOC_REG_FLAG_64_BITS |
  34526                           SOC_REG_FLAG_RO |
  34527                           SOC_REG_FLAG_WO,
  34528         0,
  34529         4,
  34530         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88680_A0r_fields,
  34531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34532         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34533         -1,
  34534         -1,
  34535     },
  34536 #endif /* chips */
  34537 
  34538 #if defined(BCM_88690_A0)
  34539     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88690_A0r */
  34540         soc_block_list[23],
  34541         soc_genreg,
  34542         1,
  34543         0,
  34544         0x94,
  34545         SOC_REG_FLAG_64_BITS |
  34546                           SOC_REG_FLAG_RO |
  34547                           SOC_REG_FLAG_WO,
  34548         SOC_REG_FLAG_COUNTER_FEILDS |
  34549                           SOC_REG_FLAG_INIT_ON_READ,
  34550         4,
  34551         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88690_A0r_fields,
  34552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34553         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34554         -1,
  34555         -1,
  34556     },
  34557 #endif /* chips */
  34558 
  34559 #if defined(BCM_88690_B0)
  34560     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88690_B0r */
  34561         soc_block_list[23],
  34562         soc_genreg,
  34563         1,
  34564         0,
  34565         0x94,
  34566         SOC_REG_FLAG_64_BITS |
  34567                           SOC_REG_FLAG_RO |
  34568                           SOC_REG_FLAG_WO,
  34569         SOC_REG_FLAG_COUNTER_FEILDS |
  34570                           SOC_REG_FLAG_INIT_ON_READ,
  34571         4,
  34572         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
  34573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34574         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34575         -1,
  34576         -1,
  34577     },
  34578 #endif /* chips */
  34579 
  34580 #if defined(BCM_88790_A0)
  34581     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88790_A0r */
  34582         soc_block_list[23],
  34583         soc_genreg,
  34584         1,
  34585         0,
  34586         0x94,
  34587         SOC_REG_FLAG_64_BITS |
  34588                           SOC_REG_FLAG_RO |
  34589                           SOC_REG_FLAG_WO,
  34590         SOC_REG_FLAG_COUNTER_FEILDS,
  34591         4,
  34592         soc_BRDC_FMAC_ECC_1B_ERR_CNT_BCM88790_A0r_fields,
  34593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34594         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34595         -1,
  34596         -1,
  34597     },
  34598 #endif /* chips */
  34599 
  34600 #if defined(BCM_88650_A0)
  34601     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASKr */
  34602         soc_block_list[23],
  34603         soc_genreg,
  34604         1,
  34605         0,
  34606         0x1df,
  34607         SOC_REG_FLAG_WO,
  34608         0,
  34609         12,
  34610         soc_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASKr_fields,
  34611         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  34612         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34613         -1,
  34614         -1,
  34615     },
  34616 #endif /* chips */
  34617 
  34618 #if defined(BCM_88202_A0)
  34619     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASK_BCM88202_A0r */
  34620         soc_block_list[23],
  34621         soc_genreg,
  34622         1,
  34623         0,
  34624         0x1df,
  34625         SOC_REG_FLAG_WO,
  34626         0,
  34627         12,
  34628         soc_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASK_BCM88202_A0r_fields,
  34629         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  34630         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34631         -1,
  34632         -1,
  34633     },
  34634 #endif /* chips */
  34635 
  34636 #if defined(BCM_88650_B0)
  34637     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASK_BCM88650_B0r */
  34638         soc_block_list[23],
  34639         soc_genreg,
  34640         1,
  34641         0,
  34642         0x1df,
  34643         SOC_REG_FLAG_WO,
  34644         0,
  34645         12,
  34646         soc_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASK_BCM88650_B0r_fields,
  34647         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  34648         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34649         -1,
  34650         -1,
  34651     },
  34652 #endif /* chips */
  34653 
  34654 #if defined(BCM_88660_A0)
  34655     { /* SOC_REG_INT_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASK_BCM88660_A0r */
  34656         soc_block_list[23],
  34657         soc_genreg,
  34658         1,
  34659         0,
  34660         0x1df,
  34661         SOC_REG_FLAG_WO,
  34662         0,
  34663         12,
  34664         soc_BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASK_BCM88660_A0r_fields,
  34665         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  34666         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34667         -1,
  34668         -1,
  34669     },
  34670 #endif /* chips */
  34671 
  34672 #if defined(BCM_88650_A0)
  34673     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_ADDRr */
  34674         soc_block_list[23],
  34675         soc_genreg,
  34676         1,
  34677         0,
  34678         0x1e2,
  34679         SOC_REG_FLAG_WO,
  34680         0,
  34681         2,
  34682         soc_BRDC_FMAC_ECC_2B_ERR_ADDRr_fields,
  34683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34684         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34685         -1,
  34686         -1,
  34687     },
  34688 #endif /* chips */
  34689 
  34690 #if defined(BCM_88202_A0)
  34691     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_ADDR_BCM88202_A0r */
  34692         soc_block_list[23],
  34693         soc_genreg,
  34694         1,
  34695         0,
  34696         0x1e2,
  34697         SOC_REG_FLAG_WO,
  34698         0,
  34699         2,
  34700         soc_BRDC_FMAC_ECC_2B_ERR_ADDR_BCM88202_A0r_fields,
  34701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34702         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34703         -1,
  34704         -1,
  34705     },
  34706 #endif /* chips */
  34707 
  34708 #if defined(BCM_88650_B0)
  34709     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_ADDR_BCM88650_B0r */
  34710         soc_block_list[23],
  34711         soc_genreg,
  34712         1,
  34713         0,
  34714         0x1e2,
  34715         SOC_REG_FLAG_WO,
  34716         0,
  34717         2,
  34718         soc_BRDC_FMAC_ECC_2B_ERR_ADDR_BCM88650_B0r_fields,
  34719         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34720         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34721         -1,
  34722         -1,
  34723     },
  34724 #endif /* chips */
  34725 
  34726 #if defined(BCM_88660_A0)
  34727     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_ADDR_BCM88660_A0r */
  34728         soc_block_list[23],
  34729         soc_genreg,
  34730         1,
  34731         0,
  34732         0x1e2,
  34733         SOC_REG_FLAG_WO,
  34734         0,
  34735         2,
  34736         soc_BRDC_FMAC_ECC_2B_ERR_ADDR_BCM88660_A0r_fields,
  34737         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34738         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  34739         -1,
  34740         -1,
  34741     },
  34742 #endif /* chips */
  34743 
  34744 #if defined(BCM_88675_A0)
  34745     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNTr */
  34746         soc_block_list[23],
  34747         soc_genreg,
  34748         1,
  34749         0,
  34750         0x96,
  34751         SOC_REG_FLAG_64_BITS |
  34752                           SOC_REG_FLAG_RO |
  34753                           SOC_REG_FLAG_WO,
  34754         0,
  34755         4,
  34756         soc_BRDC_FMAC_ECC_2B_ERR_CNTr_fields,
  34757         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34758         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34759         -1,
  34760         -1,
  34761     },
  34762 #endif /* chips */
  34763 
  34764 #if defined(BCM_83208_A0)
  34765     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM83208_A0r */
  34766         soc_block_list[23],
  34767         soc_genreg,
  34768         1,
  34769         0,
  34770         0x96,
  34771         SOC_REG_FLAG_64_BITS |
  34772                           SOC_REG_FLAG_RO |
  34773                           SOC_REG_FLAG_WO,
  34774         0,
  34775         4,
  34776         soc_AM_TOP_ECC_2B_ERR_CNTr_fields,
  34777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34778         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34779         -1,
  34780         -1,
  34781     },
  34782 #endif /* chips */
  34783 
  34784 #if defined(BCM_88375_A0)
  34785     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88375_A0r */
  34786         soc_block_list[23],
  34787         soc_genreg,
  34788         1,
  34789         0,
  34790         0x96,
  34791         SOC_REG_FLAG_64_BITS |
  34792                           SOC_REG_FLAG_RO |
  34793                           SOC_REG_FLAG_WO,
  34794         0,
  34795         4,
  34796         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88375_A0r_fields,
  34797         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34798         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34799         -1,
  34800         -1,
  34801     },
  34802 #endif /* chips */
  34803 
  34804 #if defined(BCM_88375_B0)
  34805     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88375_B0r */
  34806         soc_block_list[23],
  34807         soc_genreg,
  34808         1,
  34809         0,
  34810         0x96,
  34811         SOC_REG_FLAG_64_BITS |
  34812                           SOC_REG_FLAG_RO |
  34813                           SOC_REG_FLAG_WO,
  34814         0,
  34815         4,
  34816         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88375_B0r_fields,
  34817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34818         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34819         -1,
  34820         -1,
  34821     },
  34822 #endif /* chips */
  34823 
  34824 #if defined(BCM_88470_A0)
  34825     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88470_A0r */
  34826         soc_block_list[23],
  34827         soc_genreg,
  34828         1,
  34829         0,
  34830         0x96,
  34831         SOC_REG_FLAG_64_BITS |
  34832                           SOC_REG_FLAG_RO |
  34833                           SOC_REG_FLAG_WO,
  34834         0,
  34835         4,
  34836         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88470_A0r_fields,
  34837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34838         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34839         -1,
  34840         -1,
  34841     },
  34842 #endif /* chips */
  34843 
  34844 #if defined(BCM_88470_B0)
  34845     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88470_B0r */
  34846         soc_block_list[23],
  34847         soc_genreg,
  34848         1,
  34849         0,
  34850         0x96,
  34851         SOC_REG_FLAG_64_BITS |
  34852                           SOC_REG_FLAG_RO |
  34853                           SOC_REG_FLAG_WO,
  34854         0,
  34855         4,
  34856         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88470_B0r_fields,
  34857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34858         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34859         -1,
  34860         -1,
  34861     },
  34862 #endif /* chips */
  34863 
  34864 #if defined(BCM_88675_B0)
  34865     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88675_B0r */
  34866         soc_block_list[23],
  34867         soc_genreg,
  34868         1,
  34869         0,
  34870         0x96,
  34871         SOC_REG_FLAG_64_BITS |
  34872                           SOC_REG_FLAG_RO |
  34873                           SOC_REG_FLAG_WO,
  34874         0,
  34875         4,
  34876         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88675_B0r_fields,
  34877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34878         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34879         -1,
  34880         -1,
  34881     },
  34882 #endif /* chips */
  34883 
  34884 #if defined(BCM_88680_A0)
  34885     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88680_A0r */
  34886         soc_block_list[23],
  34887         soc_genreg,
  34888         1,
  34889         0,
  34890         0x96,
  34891         SOC_REG_FLAG_64_BITS |
  34892                           SOC_REG_FLAG_RO |
  34893                           SOC_REG_FLAG_WO,
  34894         0,
  34895         4,
  34896         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88680_A0r_fields,
  34897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34898         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34899         -1,
  34900         -1,
  34901     },
  34902 #endif /* chips */
  34903 
  34904 #if defined(BCM_88690_A0)
  34905     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88690_A0r */
  34906         soc_block_list[23],
  34907         soc_genreg,
  34908         1,
  34909         0,
  34910         0x96,
  34911         SOC_REG_FLAG_64_BITS |
  34912                           SOC_REG_FLAG_RO |
  34913                           SOC_REG_FLAG_WO,
  34914         SOC_REG_FLAG_COUNTER_FEILDS |
  34915                           SOC_REG_FLAG_INIT_ON_READ,
  34916         4,
  34917         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88690_A0r_fields,
  34918         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34919         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34920         -1,
  34921         -1,
  34922     },
  34923 #endif /* chips */
  34924 
  34925 #if defined(BCM_88690_B0)
  34926     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88690_B0r */
  34927         soc_block_list[23],
  34928         soc_genreg,
  34929         1,
  34930         0,
  34931         0x96,
  34932         SOC_REG_FLAG_64_BITS |
  34933                           SOC_REG_FLAG_RO |
  34934                           SOC_REG_FLAG_WO,
  34935         SOC_REG_FLAG_COUNTER_FEILDS |
  34936                           SOC_REG_FLAG_INIT_ON_READ,
  34937         4,
  34938         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
  34939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34940         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34941         -1,
  34942         -1,
  34943     },
  34944 #endif /* chips */
  34945 
  34946 #if defined(BCM_88790_A0)
  34947     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88790_A0r */
  34948         soc_block_list[23],
  34949         soc_genreg,
  34950         1,
  34951         0,
  34952         0x96,
  34953         SOC_REG_FLAG_64_BITS |
  34954                           SOC_REG_FLAG_RO |
  34955                           SOC_REG_FLAG_WO,
  34956         SOC_REG_FLAG_COUNTER_FEILDS,
  34957         4,
  34958         soc_BRDC_FMAC_ECC_2B_ERR_CNT_BCM88790_A0r_fields,
  34959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  34960         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  34961         -1,
  34962         -1,
  34963     },
  34964 #endif /* chips */
  34965 
  34966 #if defined(BCM_88650_A0)
  34967     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASKr */
  34968         soc_block_list[23],
  34969         soc_genreg,
  34970         1,
  34971         0,
  34972         0x1e0,
  34973         SOC_REG_FLAG_WO,
  34974         0,
  34975         12,
  34976         soc_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASKr_fields,
  34977         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  34978         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34979         -1,
  34980         -1,
  34981     },
  34982 #endif /* chips */
  34983 
  34984 #if defined(BCM_88202_A0)
  34985     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASK_BCM88202_A0r */
  34986         soc_block_list[23],
  34987         soc_genreg,
  34988         1,
  34989         0,
  34990         0x1e0,
  34991         SOC_REG_FLAG_WO,
  34992         0,
  34993         12,
  34994         soc_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASK_BCM88202_A0r_fields,
  34995         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  34996         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  34997         -1,
  34998         -1,
  34999     },
  35000 #endif /* chips */
  35001 
  35002 #if defined(BCM_88650_B0)
  35003     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASK_BCM88650_B0r */
  35004         soc_block_list[23],
  35005         soc_genreg,
  35006         1,
  35007         0,
  35008         0x1e0,
  35009         SOC_REG_FLAG_WO,
  35010         0,
  35011         12,
  35012         soc_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASK_BCM88650_B0r_fields,
  35013         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  35014         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  35015         -1,
  35016         -1,
  35017     },
  35018 #endif /* chips */
  35019 
  35020 #if defined(BCM_88660_A0)
  35021     { /* SOC_REG_INT_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASK_BCM88660_A0r */
  35022         soc_block_list[23],
  35023         soc_genreg,
  35024         1,
  35025         0,
  35026         0x1e0,
  35027         SOC_REG_FLAG_WO,
  35028         0,
  35029         12,
  35030         soc_BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASK_BCM88660_A0r_fields,
  35031         SOC_RESET_VAL_DEC(0x00000fff, 0x00000000)
  35032         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  35033         -1,
  35034         -1,
  35035     },
  35036 #endif /* chips */
  35037 
  35038 #if defined(BCM_88675_A0)
  35039     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATEr */
  35040         soc_block_list[23],
  35041         soc_genreg,
  35042         1,
  35043         0,
  35044         0xa4,
  35045         SOC_REG_FLAG_WO,
  35046         0,
  35047         8,
  35048         soc_BRDC_FMAC_ECC_ERR_1B_INITIATEr_fields,
  35049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35050         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35051         -1,
  35052         -1,
  35053     },
  35054 #endif /* chips */
  35055 
  35056 #if defined(BCM_83208_A0)
  35057     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM83208_A0r */
  35058         soc_block_list[23],
  35059         soc_genreg,
  35060         1,
  35061         0,
  35062         0xa4,
  35063         SOC_REG_FLAG_WO,
  35064         0,
  35065         1,
  35066         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM83208_A0r_fields,
  35067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35068         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35069         -1,
  35070         -1,
  35071     },
  35072 #endif /* chips */
  35073 
  35074 #if defined(BCM_88375_A0)
  35075     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88375_A0r */
  35076         soc_block_list[23],
  35077         soc_genreg,
  35078         1,
  35079         0,
  35080         0xa4,
  35081         SOC_REG_FLAG_WO,
  35082         0,
  35083         8,
  35084         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88375_A0r_fields,
  35085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35086         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35087         -1,
  35088         -1,
  35089     },
  35090 #endif /* chips */
  35091 
  35092 #if defined(BCM_88375_B0)
  35093     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88375_B0r */
  35094         soc_block_list[23],
  35095         soc_genreg,
  35096         1,
  35097         0,
  35098         0xa4,
  35099         SOC_REG_FLAG_WO,
  35100         0,
  35101         8,
  35102         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88375_B0r_fields,
  35103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35104         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35105         -1,
  35106         -1,
  35107     },
  35108 #endif /* chips */
  35109 
  35110 #if defined(BCM_88470_A0)
  35111     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88470_A0r */
  35112         soc_block_list[23],
  35113         soc_genreg,
  35114         1,
  35115         0,
  35116         0xa4,
  35117         SOC_REG_FLAG_WO,
  35118         0,
  35119         8,
  35120         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88470_A0r_fields,
  35121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35122         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35123         -1,
  35124         -1,
  35125     },
  35126 #endif /* chips */
  35127 
  35128 #if defined(BCM_88470_B0)
  35129     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88470_B0r */
  35130         soc_block_list[23],
  35131         soc_genreg,
  35132         1,
  35133         0,
  35134         0xa4,
  35135         SOC_REG_FLAG_WO,
  35136         0,
  35137         8,
  35138         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88470_B0r_fields,
  35139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35140         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35141         -1,
  35142         -1,
  35143     },
  35144 #endif /* chips */
  35145 
  35146 #if defined(BCM_88675_B0)
  35147     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88675_B0r */
  35148         soc_block_list[23],
  35149         soc_genreg,
  35150         1,
  35151         0,
  35152         0xa4,
  35153         SOC_REG_FLAG_WO,
  35154         0,
  35155         8,
  35156         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88675_B0r_fields,
  35157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35158         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35159         -1,
  35160         -1,
  35161     },
  35162 #endif /* chips */
  35163 
  35164 #if defined(BCM_88680_A0)
  35165     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88680_A0r */
  35166         soc_block_list[23],
  35167         soc_genreg,
  35168         1,
  35169         0,
  35170         0xa4,
  35171         SOC_REG_FLAG_WO,
  35172         0,
  35173         8,
  35174         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88680_A0r_fields,
  35175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35176         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35177         -1,
  35178         -1,
  35179     },
  35180 #endif /* chips */
  35181 
  35182 #if defined(BCM_88690_A0)
  35183     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88690_A0r */
  35184         soc_block_list[23],
  35185         soc_genreg,
  35186         1,
  35187         0,
  35188         0xa4,
  35189         SOC_REG_FLAG_WO,
  35190         0,
  35191         17,
  35192         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88690_A0r_fields,
  35193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35194         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35195         -1,
  35196         -1,
  35197     },
  35198 #endif /* chips */
  35199 
  35200 #if defined(BCM_88790_A0)
  35201     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88790_A0r */
  35202         soc_block_list[23],
  35203         soc_genreg,
  35204         1,
  35205         0,
  35206         0xa4,
  35207         SOC_REG_FLAG_WO,
  35208         0,
  35209         17,
  35210         soc_BRDC_FMAC_ECC_ERR_1B_INITIATE_BCM88790_A0r_fields,
  35211         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35212         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35213         -1,
  35214         -1,
  35215     },
  35216 #endif /* chips */
  35217 
  35218 #if defined(BCM_88675_A0)
  35219     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASKr */
  35220         soc_block_list[23],
  35221         soc_genreg,
  35222         1,
  35223         0,
  35224         0x9a,
  35225         SOC_REG_FLAG_WO,
  35226         0,
  35227         8,
  35228         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  35229         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35230         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35231         -1,
  35232         -1,
  35233     },
  35234 #endif /* chips */
  35235 
  35236 #if defined(BCM_83208_A0)
  35237     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM83208_A0r */
  35238         soc_block_list[23],
  35239         soc_genreg,
  35240         1,
  35241         0,
  35242         0x9a,
  35243         SOC_REG_FLAG_WO,
  35244         0,
  35245         1,
  35246         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM83208_A0r_fields,
  35247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35248         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35249         -1,
  35250         -1,
  35251     },
  35252 #endif /* chips */
  35253 
  35254 #if defined(BCM_88375_A0)
  35255     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r */
  35256         soc_block_list[23],
  35257         soc_genreg,
  35258         1,
  35259         0,
  35260         0x9a,
  35261         SOC_REG_FLAG_WO,
  35262         0,
  35263         8,
  35264         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  35265         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35266         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35267         -1,
  35268         -1,
  35269     },
  35270 #endif /* chips */
  35271 
  35272 #if defined(BCM_88375_B0)
  35273     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r */
  35274         soc_block_list[23],
  35275         soc_genreg,
  35276         1,
  35277         0,
  35278         0x9a,
  35279         SOC_REG_FLAG_WO,
  35280         0,
  35281         8,
  35282         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  35283         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35284         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35285         -1,
  35286         -1,
  35287     },
  35288 #endif /* chips */
  35289 
  35290 #if defined(BCM_88470_A0)
  35291     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_A0r */
  35292         soc_block_list[23],
  35293         soc_genreg,
  35294         1,
  35295         0,
  35296         0x9a,
  35297         SOC_REG_FLAG_WO,
  35298         0,
  35299         8,
  35300         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_A0r_fields,
  35301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35302         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35303         -1,
  35304         -1,
  35305     },
  35306 #endif /* chips */
  35307 
  35308 #if defined(BCM_88470_B0)
  35309     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r */
  35310         soc_block_list[23],
  35311         soc_genreg,
  35312         1,
  35313         0,
  35314         0x9a,
  35315         SOC_REG_FLAG_WO,
  35316         0,
  35317         8,
  35318         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
  35319         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35320         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35321         -1,
  35322         -1,
  35323     },
  35324 #endif /* chips */
  35325 
  35326 #if defined(BCM_88675_B0)
  35327     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r */
  35328         soc_block_list[23],
  35329         soc_genreg,
  35330         1,
  35331         0,
  35332         0x9a,
  35333         SOC_REG_FLAG_WO,
  35334         0,
  35335         8,
  35336         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  35337         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35338         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35339         -1,
  35340         -1,
  35341     },
  35342 #endif /* chips */
  35343 
  35344 #if defined(BCM_88680_A0)
  35345     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r */
  35346         soc_block_list[23],
  35347         soc_genreg,
  35348         1,
  35349         0,
  35350         0x9a,
  35351         SOC_REG_FLAG_WO,
  35352         0,
  35353         8,
  35354         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  35355         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35356         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35357         -1,
  35358         -1,
  35359     },
  35360 #endif /* chips */
  35361 
  35362 #if defined(BCM_88690_A0)
  35363     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r */
  35364         soc_block_list[23],
  35365         soc_genreg,
  35366         1,
  35367         0,
  35368         0x9a,
  35369         SOC_REG_FLAG_WO,
  35370         0,
  35371         17,
  35372         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  35373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35374         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35375         -1,
  35376         -1,
  35377     },
  35378 #endif /* chips */
  35379 
  35380 #if defined(BCM_88690_B0)
  35381     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
  35382         soc_block_list[23],
  35383         soc_genreg,
  35384         1,
  35385         0,
  35386         0x9a,
  35387         SOC_REG_FLAG_WO,
  35388         0,
  35389         17,
  35390         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  35391         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35392         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35393         -1,
  35394         -1,
  35395     },
  35396 #endif /* chips */
  35397 
  35398 #if defined(BCM_88790_A0)
  35399     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88790_A0r */
  35400         soc_block_list[23],
  35401         soc_genreg,
  35402         1,
  35403         0,
  35404         0x9a,
  35405         SOC_REG_FLAG_WO,
  35406         0,
  35407         17,
  35408         soc_BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88790_A0r_fields,
  35409         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35410         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35411         -1,
  35412         -1,
  35413     },
  35414 #endif /* chips */
  35415 
  35416 #if defined(BCM_88675_A0)
  35417     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATEr */
  35418         soc_block_list[23],
  35419         soc_genreg,
  35420         1,
  35421         0,
  35422         0xa6,
  35423         SOC_REG_FLAG_WO,
  35424         0,
  35425         8,
  35426         soc_BRDC_FMAC_ECC_ERR_2B_INITIATEr_fields,
  35427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35428         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35429         -1,
  35430         -1,
  35431     },
  35432 #endif /* chips */
  35433 
  35434 #if defined(BCM_83208_A0)
  35435     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM83208_A0r */
  35436         soc_block_list[23],
  35437         soc_genreg,
  35438         1,
  35439         0,
  35440         0xa6,
  35441         SOC_REG_FLAG_WO,
  35442         0,
  35443         1,
  35444         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM83208_A0r_fields,
  35445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35446         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35447         -1,
  35448         -1,
  35449     },
  35450 #endif /* chips */
  35451 
  35452 #if defined(BCM_88375_A0)
  35453     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88375_A0r */
  35454         soc_block_list[23],
  35455         soc_genreg,
  35456         1,
  35457         0,
  35458         0xa6,
  35459         SOC_REG_FLAG_WO,
  35460         0,
  35461         8,
  35462         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88375_A0r_fields,
  35463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35464         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35465         -1,
  35466         -1,
  35467     },
  35468 #endif /* chips */
  35469 
  35470 #if defined(BCM_88375_B0)
  35471     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88375_B0r */
  35472         soc_block_list[23],
  35473         soc_genreg,
  35474         1,
  35475         0,
  35476         0xa6,
  35477         SOC_REG_FLAG_WO,
  35478         0,
  35479         8,
  35480         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88375_B0r_fields,
  35481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35482         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35483         -1,
  35484         -1,
  35485     },
  35486 #endif /* chips */
  35487 
  35488 #if defined(BCM_88470_A0)
  35489     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88470_A0r */
  35490         soc_block_list[23],
  35491         soc_genreg,
  35492         1,
  35493         0,
  35494         0xa6,
  35495         SOC_REG_FLAG_WO,
  35496         0,
  35497         8,
  35498         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88470_A0r_fields,
  35499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35500         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35501         -1,
  35502         -1,
  35503     },
  35504 #endif /* chips */
  35505 
  35506 #if defined(BCM_88470_B0)
  35507     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88470_B0r */
  35508         soc_block_list[23],
  35509         soc_genreg,
  35510         1,
  35511         0,
  35512         0xa6,
  35513         SOC_REG_FLAG_WO,
  35514         0,
  35515         8,
  35516         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88470_B0r_fields,
  35517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35518         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35519         -1,
  35520         -1,
  35521     },
  35522 #endif /* chips */
  35523 
  35524 #if defined(BCM_88675_B0)
  35525     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88675_B0r */
  35526         soc_block_list[23],
  35527         soc_genreg,
  35528         1,
  35529         0,
  35530         0xa6,
  35531         SOC_REG_FLAG_WO,
  35532         0,
  35533         8,
  35534         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88675_B0r_fields,
  35535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35536         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35537         -1,
  35538         -1,
  35539     },
  35540 #endif /* chips */
  35541 
  35542 #if defined(BCM_88680_A0)
  35543     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88680_A0r */
  35544         soc_block_list[23],
  35545         soc_genreg,
  35546         1,
  35547         0,
  35548         0xa6,
  35549         SOC_REG_FLAG_WO,
  35550         0,
  35551         8,
  35552         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88680_A0r_fields,
  35553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35554         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35555         -1,
  35556         -1,
  35557     },
  35558 #endif /* chips */
  35559 
  35560 #if defined(BCM_88690_A0)
  35561     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88690_A0r */
  35562         soc_block_list[23],
  35563         soc_genreg,
  35564         1,
  35565         0,
  35566         0xa6,
  35567         SOC_REG_FLAG_WO,
  35568         0,
  35569         17,
  35570         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88690_A0r_fields,
  35571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35572         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35573         -1,
  35574         -1,
  35575     },
  35576 #endif /* chips */
  35577 
  35578 #if defined(BCM_88790_A0)
  35579     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88790_A0r */
  35580         soc_block_list[23],
  35581         soc_genreg,
  35582         1,
  35583         0,
  35584         0xa6,
  35585         SOC_REG_FLAG_WO,
  35586         0,
  35587         17,
  35588         soc_BRDC_FMAC_ECC_ERR_2B_INITIATE_BCM88790_A0r_fields,
  35589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35590         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35591         -1,
  35592         -1,
  35593     },
  35594 #endif /* chips */
  35595 
  35596 #if defined(BCM_88675_A0)
  35597     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASKr */
  35598         soc_block_list[23],
  35599         soc_genreg,
  35600         1,
  35601         0,
  35602         0x9c,
  35603         SOC_REG_FLAG_WO,
  35604         0,
  35605         8,
  35606         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  35607         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35608         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35609         -1,
  35610         -1,
  35611     },
  35612 #endif /* chips */
  35613 
  35614 #if defined(BCM_83208_A0)
  35615     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM83208_A0r */
  35616         soc_block_list[23],
  35617         soc_genreg,
  35618         1,
  35619         0,
  35620         0x9c,
  35621         SOC_REG_FLAG_WO,
  35622         0,
  35623         1,
  35624         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM83208_A0r_fields,
  35625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35626         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  35627         -1,
  35628         -1,
  35629     },
  35630 #endif /* chips */
  35631 
  35632 #if defined(BCM_88375_A0)
  35633     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r */
  35634         soc_block_list[23],
  35635         soc_genreg,
  35636         1,
  35637         0,
  35638         0x9c,
  35639         SOC_REG_FLAG_WO,
  35640         0,
  35641         8,
  35642         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  35643         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35644         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35645         -1,
  35646         -1,
  35647     },
  35648 #endif /* chips */
  35649 
  35650 #if defined(BCM_88375_B0)
  35651     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r */
  35652         soc_block_list[23],
  35653         soc_genreg,
  35654         1,
  35655         0,
  35656         0x9c,
  35657         SOC_REG_FLAG_WO,
  35658         0,
  35659         8,
  35660         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  35661         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35662         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35663         -1,
  35664         -1,
  35665     },
  35666 #endif /* chips */
  35667 
  35668 #if defined(BCM_88470_A0)
  35669     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_A0r */
  35670         soc_block_list[23],
  35671         soc_genreg,
  35672         1,
  35673         0,
  35674         0x9c,
  35675         SOC_REG_FLAG_WO,
  35676         0,
  35677         8,
  35678         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_A0r_fields,
  35679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35680         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35681         -1,
  35682         -1,
  35683     },
  35684 #endif /* chips */
  35685 
  35686 #if defined(BCM_88470_B0)
  35687     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r */
  35688         soc_block_list[23],
  35689         soc_genreg,
  35690         1,
  35691         0,
  35692         0x9c,
  35693         SOC_REG_FLAG_WO,
  35694         0,
  35695         8,
  35696         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88470_B0r_fields,
  35697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35698         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35699         -1,
  35700         -1,
  35701     },
  35702 #endif /* chips */
  35703 
  35704 #if defined(BCM_88675_B0)
  35705     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r */
  35706         soc_block_list[23],
  35707         soc_genreg,
  35708         1,
  35709         0,
  35710         0x9c,
  35711         SOC_REG_FLAG_WO,
  35712         0,
  35713         8,
  35714         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  35715         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35716         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35717         -1,
  35718         -1,
  35719     },
  35720 #endif /* chips */
  35721 
  35722 #if defined(BCM_88680_A0)
  35723     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r */
  35724         soc_block_list[23],
  35725         soc_genreg,
  35726         1,
  35727         0,
  35728         0x9c,
  35729         SOC_REG_FLAG_WO,
  35730         0,
  35731         8,
  35732         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  35733         SOC_RESET_VAL_DEC(0x000000ff, 0x00000000)
  35734         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  35735         -1,
  35736         -1,
  35737     },
  35738 #endif /* chips */
  35739 
  35740 #if defined(BCM_88690_A0)
  35741     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r */
  35742         soc_block_list[23],
  35743         soc_genreg,
  35744         1,
  35745         0,
  35746         0x9c,
  35747         SOC_REG_FLAG_WO,
  35748         0,
  35749         17,
  35750         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  35751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35752         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35753         -1,
  35754         -1,
  35755     },
  35756 #endif /* chips */
  35757 
  35758 #if defined(BCM_88690_B0)
  35759     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
  35760         soc_block_list[23],
  35761         soc_genreg,
  35762         1,
  35763         0,
  35764         0x9c,
  35765         SOC_REG_FLAG_WO,
  35766         0,
  35767         17,
  35768         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  35769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35770         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35771         -1,
  35772         -1,
  35773     },
  35774 #endif /* chips */
  35775 
  35776 #if defined(BCM_88790_A0)
  35777     { /* SOC_REG_INT_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88790_A0r */
  35778         soc_block_list[23],
  35779         soc_genreg,
  35780         1,
  35781         0,
  35782         0x9c,
  35783         SOC_REG_FLAG_WO,
  35784         0,
  35785         17,
  35786         soc_BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88790_A0r_fields,
  35787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35788         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  35789         -1,
  35790         -1,
  35791     },
  35792 #endif /* chips */
  35793 
  35794 #if defined(BCM_88675_A0)
  35795     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTERr */
  35796         soc_block_list[23],
  35797         soc_genreg,
  35798         1,
  35799         0,
  35800         0x7,
  35801         SOC_REG_FLAG_WO |
  35802                           SOC_REG_FLAG_INTERRUPT,
  35803         0,
  35804         3,
  35805         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTERr_fields,
  35806         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35807         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35808         -1,
  35809         -1,
  35810     },
  35811 #endif /* chips */
  35812 
  35813 #if defined(BCM_83208_A0)
  35814     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM83208_A0r */
  35815         soc_block_list[23],
  35816         soc_genreg,
  35817         1,
  35818         0,
  35819         0x7,
  35820         SOC_REG_FLAG_WO |
  35821                           SOC_REG_FLAG_INTERRUPT,
  35822         0,
  35823         3,
  35824         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM83208_A0r_fields,
  35825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35826         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35827         -1,
  35828         -1,
  35829     },
  35830 #endif /* chips */
  35831 
  35832 #if defined(BCM_88375_A0)
  35833     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88375_A0r */
  35834         soc_block_list[23],
  35835         soc_genreg,
  35836         1,
  35837         0,
  35838         0x7,
  35839         SOC_REG_FLAG_WO |
  35840                           SOC_REG_FLAG_INTERRUPT,
  35841         0,
  35842         3,
  35843         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  35844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35845         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35846         -1,
  35847         -1,
  35848     },
  35849 #endif /* chips */
  35850 
  35851 #if defined(BCM_88375_B0)
  35852     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88375_B0r */
  35853         soc_block_list[23],
  35854         soc_genreg,
  35855         1,
  35856         0,
  35857         0x7,
  35858         SOC_REG_FLAG_WO |
  35859                           SOC_REG_FLAG_INTERRUPT,
  35860         0,
  35861         3,
  35862         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  35863         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35864         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35865         -1,
  35866         -1,
  35867     },
  35868 #endif /* chips */
  35869 
  35870 #if defined(BCM_88470_A0)
  35871     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88470_A0r */
  35872         soc_block_list[23],
  35873         soc_genreg,
  35874         1,
  35875         0,
  35876         0x7,
  35877         SOC_REG_FLAG_WO |
  35878                           SOC_REG_FLAG_INTERRUPT |
  35879                           SOC_REG_FLAG_SIGNAL,
  35880         0,
  35881         3,
  35882         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88470_A0r_fields,
  35883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35884         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35885         -1,
  35886         -1,
  35887     },
  35888 #endif /* chips */
  35889 
  35890 #if defined(BCM_88470_B0)
  35891     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88470_B0r */
  35892         soc_block_list[23],
  35893         soc_genreg,
  35894         1,
  35895         0,
  35896         0x7,
  35897         SOC_REG_FLAG_WO |
  35898                           SOC_REG_FLAG_INTERRUPT |
  35899                           SOC_REG_FLAG_SIGNAL,
  35900         0,
  35901         3,
  35902         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88470_B0r_fields,
  35903         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35904         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35905         -1,
  35906         -1,
  35907     },
  35908 #endif /* chips */
  35909 
  35910 #if defined(BCM_88675_B0)
  35911     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88675_B0r */
  35912         soc_block_list[23],
  35913         soc_genreg,
  35914         1,
  35915         0,
  35916         0x7,
  35917         SOC_REG_FLAG_WO |
  35918                           SOC_REG_FLAG_INTERRUPT,
  35919         0,
  35920         3,
  35921         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  35922         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35923         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35924         -1,
  35925         -1,
  35926     },
  35927 #endif /* chips */
  35928 
  35929 #if defined(BCM_88680_A0)
  35930     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88680_A0r */
  35931         soc_block_list[23],
  35932         soc_genreg,
  35933         1,
  35934         0,
  35935         0x7,
  35936         SOC_REG_FLAG_WO |
  35937                           SOC_REG_FLAG_INTERRUPT,
  35938         0,
  35939         3,
  35940         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  35941         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35942         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35943         -1,
  35944         -1,
  35945     },
  35946 #endif /* chips */
  35947 
  35948 #if defined(BCM_88690_A0)
  35949     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88690_A0r */
  35950         soc_block_list[23],
  35951         soc_genreg,
  35952         1,
  35953         0,
  35954         0x7,
  35955         SOC_REG_FLAG_WO |
  35956                           SOC_REG_FLAG_INTERRUPT |
  35957                           SOC_REG_FLAG_SIGNAL,
  35958         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  35959         3,
  35960         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  35961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35962         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35963         -1,
  35964         -1,
  35965     },
  35966 #endif /* chips */
  35967 
  35968 #if defined(BCM_88690_B0)
  35969     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
  35970         soc_block_list[23],
  35971         soc_genreg,
  35972         1,
  35973         0,
  35974         0x7,
  35975         SOC_REG_FLAG_WO |
  35976                           SOC_REG_FLAG_INTERRUPT |
  35977                           SOC_REG_FLAG_SIGNAL,
  35978         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  35979         3,
  35980         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  35981         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  35982         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  35983         -1,
  35984         -1,
  35985     },
  35986 #endif /* chips */
  35987 
  35988 #if defined(BCM_88790_A0)
  35989     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88790_A0r */
  35990         soc_block_list[23],
  35991         soc_genreg,
  35992         1,
  35993         0,
  35994         0x7,
  35995         SOC_REG_FLAG_WO |
  35996                           SOC_REG_FLAG_INTERRUPT |
  35997                           SOC_REG_FLAG_SIGNAL,
  35998         0,
  35999         3,
  36000         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  36001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36002         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36003         -1,
  36004         -1,
  36005     },
  36006 #endif /* chips */
  36007 
  36008 #if defined(BCM_88675_A0)
  36009     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASKr */
  36010         soc_block_list[23],
  36011         soc_genreg,
  36012         1,
  36013         0,
  36014         0x17,
  36015         SOC_REG_FLAG_WO,
  36016         0,
  36017         3,
  36018         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASKr_fields,
  36019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36020         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36021         -1,
  36022         -1,
  36023     },
  36024 #endif /* chips */
  36025 
  36026 #if defined(BCM_83208_A0)
  36027     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM83208_A0r */
  36028         soc_block_list[23],
  36029         soc_genreg,
  36030         1,
  36031         0,
  36032         0x17,
  36033         SOC_REG_FLAG_WO,
  36034         0,
  36035         3,
  36036         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM83208_A0r_fields,
  36037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36038         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36039         -1,
  36040         -1,
  36041     },
  36042 #endif /* chips */
  36043 
  36044 #if defined(BCM_88375_A0)
  36045     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r */
  36046         soc_block_list[23],
  36047         soc_genreg,
  36048         1,
  36049         0,
  36050         0x17,
  36051         SOC_REG_FLAG_WO,
  36052         0,
  36053         3,
  36054         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r_fields,
  36055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36056         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36057         -1,
  36058         -1,
  36059     },
  36060 #endif /* chips */
  36061 
  36062 #if defined(BCM_88375_B0)
  36063     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r */
  36064         soc_block_list[23],
  36065         soc_genreg,
  36066         1,
  36067         0,
  36068         0x17,
  36069         SOC_REG_FLAG_WO,
  36070         0,
  36071         3,
  36072         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r_fields,
  36073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36074         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36075         -1,
  36076         -1,
  36077     },
  36078 #endif /* chips */
  36079 
  36080 #if defined(BCM_88470_A0)
  36081     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88470_A0r */
  36082         soc_block_list[23],
  36083         soc_genreg,
  36084         1,
  36085         0,
  36086         0x17,
  36087         SOC_REG_FLAG_WO,
  36088         0,
  36089         3,
  36090         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88470_A0r_fields,
  36091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36092         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36093         -1,
  36094         -1,
  36095     },
  36096 #endif /* chips */
  36097 
  36098 #if defined(BCM_88470_B0)
  36099     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r */
  36100         soc_block_list[23],
  36101         soc_genreg,
  36102         1,
  36103         0,
  36104         0x17,
  36105         SOC_REG_FLAG_WO,
  36106         0,
  36107         3,
  36108         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88470_B0r_fields,
  36109         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36110         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36111         -1,
  36112         -1,
  36113     },
  36114 #endif /* chips */
  36115 
  36116 #if defined(BCM_88675_B0)
  36117     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r */
  36118         soc_block_list[23],
  36119         soc_genreg,
  36120         1,
  36121         0,
  36122         0x17,
  36123         SOC_REG_FLAG_WO,
  36124         0,
  36125         3,
  36126         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r_fields,
  36127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36128         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36129         -1,
  36130         -1,
  36131     },
  36132 #endif /* chips */
  36133 
  36134 #if defined(BCM_88680_A0)
  36135     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r */
  36136         soc_block_list[23],
  36137         soc_genreg,
  36138         1,
  36139         0,
  36140         0x17,
  36141         SOC_REG_FLAG_WO,
  36142         0,
  36143         3,
  36144         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r_fields,
  36145         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36146         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36147         -1,
  36148         -1,
  36149     },
  36150 #endif /* chips */
  36151 
  36152 #if defined(BCM_88690_A0)
  36153     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r */
  36154         soc_block_list[23],
  36155         soc_genreg,
  36156         1,
  36157         0,
  36158         0x17,
  36159         SOC_REG_FLAG_WO,
  36160         0,
  36161         3,
  36162         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r_fields,
  36163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36164         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36165         -1,
  36166         -1,
  36167     },
  36168 #endif /* chips */
  36169 
  36170 #if defined(BCM_88690_B0)
  36171     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
  36172         soc_block_list[23],
  36173         soc_genreg,
  36174         1,
  36175         0,
  36176         0x17,
  36177         SOC_REG_FLAG_WO,
  36178         0,
  36179         3,
  36180         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
  36181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36182         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36183         -1,
  36184         -1,
  36185     },
  36186 #endif /* chips */
  36187 
  36188 #if defined(BCM_88790_A0)
  36189     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88790_A0r */
  36190         soc_block_list[23],
  36191         soc_genreg,
  36192         1,
  36193         0,
  36194         0x17,
  36195         SOC_REG_FLAG_WO,
  36196         0,
  36197         3,
  36198         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK_BCM88790_A0r_fields,
  36199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36200         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36201         -1,
  36202         -1,
  36203     },
  36204 #endif /* chips */
  36205 
  36206 #if defined(BCM_88675_A0)
  36207     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TESTr */
  36208         soc_block_list[23],
  36209         soc_genreg,
  36210         1,
  36211         0,
  36212         0x1f,
  36213         SOC_REG_FLAG_WO,
  36214         0,
  36215         1,
  36216         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TESTr_fields,
  36217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36218         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36219         -1,
  36220         -1,
  36221     },
  36222 #endif /* chips */
  36223 
  36224 #if defined(BCM_83208_A0)
  36225     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM83208_A0r */
  36226         soc_block_list[23],
  36227         soc_genreg,
  36228         1,
  36229         0,
  36230         0x1f,
  36231         SOC_REG_FLAG_WO,
  36232         0,
  36233         1,
  36234         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM83208_A0r_fields,
  36235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36236         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36237         -1,
  36238         -1,
  36239     },
  36240 #endif /* chips */
  36241 
  36242 #if defined(BCM_88375_A0)
  36243     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  36244         soc_block_list[23],
  36245         soc_genreg,
  36246         1,
  36247         0,
  36248         0x1f,
  36249         SOC_REG_FLAG_WO,
  36250         0,
  36251         1,
  36252         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  36253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36254         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36255         -1,
  36256         -1,
  36257     },
  36258 #endif /* chips */
  36259 
  36260 #if defined(BCM_88375_B0)
  36261     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  36262         soc_block_list[23],
  36263         soc_genreg,
  36264         1,
  36265         0,
  36266         0x1f,
  36267         SOC_REG_FLAG_WO,
  36268         0,
  36269         1,
  36270         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  36271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36272         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36273         -1,
  36274         -1,
  36275     },
  36276 #endif /* chips */
  36277 
  36278 #if defined(BCM_88470_A0)
  36279     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88470_A0r */
  36280         soc_block_list[23],
  36281         soc_genreg,
  36282         1,
  36283         0,
  36284         0x1f,
  36285         SOC_REG_FLAG_WO,
  36286         0,
  36287         1,
  36288         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88470_A0r_fields,
  36289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36290         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36291         -1,
  36292         -1,
  36293     },
  36294 #endif /* chips */
  36295 
  36296 #if defined(BCM_88470_B0)
  36297     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
  36298         soc_block_list[23],
  36299         soc_genreg,
  36300         1,
  36301         0,
  36302         0x1f,
  36303         SOC_REG_FLAG_WO,
  36304         0,
  36305         1,
  36306         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
  36307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36308         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36309         -1,
  36310         -1,
  36311     },
  36312 #endif /* chips */
  36313 
  36314 #if defined(BCM_88675_B0)
  36315     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  36316         soc_block_list[23],
  36317         soc_genreg,
  36318         1,
  36319         0,
  36320         0x1f,
  36321         SOC_REG_FLAG_WO,
  36322         0,
  36323         1,
  36324         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  36325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36327         -1,
  36328         -1,
  36329     },
  36330 #endif /* chips */
  36331 
  36332 #if defined(BCM_88680_A0)
  36333     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  36334         soc_block_list[23],
  36335         soc_genreg,
  36336         1,
  36337         0,
  36338         0x1f,
  36339         SOC_REG_FLAG_WO,
  36340         0,
  36341         1,
  36342         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  36343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36344         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  36345         -1,
  36346         -1,
  36347     },
  36348 #endif /* chips */
  36349 
  36350 #if defined(BCM_88690_A0)
  36351     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  36352         soc_block_list[23],
  36353         soc_genreg,
  36354         1,
  36355         0,
  36356         0x1f,
  36357         SOC_REG_FLAG_WO,
  36358         0,
  36359         1,
  36360         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  36361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36362         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36363         -1,
  36364         -1,
  36365     },
  36366 #endif /* chips */
  36367 
  36368 #if defined(BCM_88690_B0)
  36369     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  36370         soc_block_list[23],
  36371         soc_genreg,
  36372         1,
  36373         0,
  36374         0x1f,
  36375         SOC_REG_FLAG_WO,
  36376         0,
  36377         1,
  36378         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  36379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36380         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36381         -1,
  36382         -1,
  36383     },
  36384 #endif /* chips */
  36385 
  36386 #if defined(BCM_88790_A0)
  36387     { /* SOC_REG_INT_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  36388         soc_block_list[23],
  36389         soc_genreg,
  36390         1,
  36391         0,
  36392         0x1f,
  36393         SOC_REG_FLAG_WO,
  36394         0,
  36395         1,
  36396         soc_BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST_BCM88790_A0r_fields,
  36397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36398         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36399         -1,
  36400         -1,
  36401     },
  36402 #endif /* chips */
  36403 
  36404 #if defined(BCM_88650_A0)
  36405     { /* SOC_REG_INT_BRDC_FMAC_EDS_CONFIGURATIONr */
  36406         soc_block_list[23],
  36407         soc_genreg,
  36408         4,
  36409         0,
  36410         0xb8,
  36411         SOC_REG_FLAG_ARRAY |
  36412                           SOC_REG_FLAG_WO |
  36413                           SOC_REG_FLAG_REG_ARRAY,
  36414         0,
  36415         14,
  36416         soc_BRDC_FMAC_EDS_CONFIGURATIONr_fields,
  36417         SOC_RESET_VAL_DEC(0x0022001f, 0x00000000)
  36418         SOC_RESET_MASK_DEC(0x33ff001f, 0x00000000)
  36419         -1,
  36420         -1,
  36421     },
  36422 #endif /* chips */
  36423 
  36424 #if defined(BCM_88202_A0)
  36425     { /* SOC_REG_INT_BRDC_FMAC_EDS_CONFIGURATION_BCM88202_A0r */
  36426         soc_block_list[23],
  36427         soc_genreg,
  36428         4,
  36429         0,
  36430         0xb8,
  36431         SOC_REG_FLAG_ARRAY |
  36432                           SOC_REG_FLAG_WO |
  36433                           SOC_REG_FLAG_REG_ARRAY,
  36434         0,
  36435         14,
  36436         soc_BRDC_FMAC_EDS_CONFIGURATION_BCM88202_A0r_fields,
  36437         SOC_RESET_VAL_DEC(0x0022001f, 0x00000000)
  36438         SOC_RESET_MASK_DEC(0x33ff001f, 0x00000000)
  36439         -1,
  36440         -1,
  36441     },
  36442 #endif /* chips */
  36443 
  36444 #if defined(BCM_88650_B0)
  36445     { /* SOC_REG_INT_BRDC_FMAC_EDS_CONFIGURATION_BCM88650_B0r */
  36446         soc_block_list[23],
  36447         soc_genreg,
  36448         4,
  36449         0,
  36450         0xb8,
  36451         SOC_REG_FLAG_ARRAY |
  36452                           SOC_REG_FLAG_WO |
  36453                           SOC_REG_FLAG_REG_ARRAY,
  36454         0,
  36455         14,
  36456         soc_BRDC_FMAC_EDS_CONFIGURATION_BCM88650_B0r_fields,
  36457         SOC_RESET_VAL_DEC(0x0022001f, 0x00000000)
  36458         SOC_RESET_MASK_DEC(0x33ff001f, 0x00000000)
  36459         -1,
  36460         -1,
  36461     },
  36462 #endif /* chips */
  36463 
  36464 #if defined(BCM_88660_A0)
  36465     { /* SOC_REG_INT_BRDC_FMAC_EDS_CONFIGURATION_BCM88660_A0r */
  36466         soc_block_list[23],
  36467         soc_genreg,
  36468         4,
  36469         0,
  36470         0xb8,
  36471         SOC_REG_FLAG_ARRAY |
  36472                           SOC_REG_FLAG_WO |
  36473                           SOC_REG_FLAG_REG_ARRAY,
  36474         0,
  36475         14,
  36476         soc_BRDC_FMAC_EDS_CONFIGURATION_BCM88660_A0r_fields,
  36477         SOC_RESET_VAL_DEC(0x0022001f, 0x00000000)
  36478         SOC_RESET_MASK_DEC(0x33ff001f, 0x00000000)
  36479         -1,
  36480         -1,
  36481     },
  36482 #endif /* chips */
  36483 
  36484 #if defined(BCM_88650_A0)
  36485     { /* SOC_REG_INT_BRDC_FMAC_EDS_STATUSr */
  36486         soc_block_list[23],
  36487         soc_genreg,
  36488         4,
  36489         0,
  36490         0xd0,
  36491         SOC_REG_FLAG_ARRAY |
  36492                           SOC_REG_FLAG_WO |
  36493                           SOC_REG_FLAG_REG_ARRAY,
  36494         0,
  36495         5,
  36496         soc_BRDC_FMAC_EDS_STATUSr_fields,
  36497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36498         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  36499         -1,
  36500         -1,
  36501     },
  36502 #endif /* chips */
  36503 
  36504 #if defined(BCM_88202_A0)
  36505     { /* SOC_REG_INT_BRDC_FMAC_EDS_STATUS_BCM88202_A0r */
  36506         soc_block_list[23],
  36507         soc_genreg,
  36508         4,
  36509         0,
  36510         0xd0,
  36511         SOC_REG_FLAG_ARRAY |
  36512                           SOC_REG_FLAG_WO |
  36513                           SOC_REG_FLAG_REG_ARRAY,
  36514         0,
  36515         5,
  36516         soc_BRDC_FMAC_EDS_STATUS_BCM88202_A0r_fields,
  36517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36518         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  36519         -1,
  36520         -1,
  36521     },
  36522 #endif /* chips */
  36523 
  36524 #if defined(BCM_88650_B0)
  36525     { /* SOC_REG_INT_BRDC_FMAC_EDS_STATUS_BCM88650_B0r */
  36526         soc_block_list[23],
  36527         soc_genreg,
  36528         4,
  36529         0,
  36530         0xd0,
  36531         SOC_REG_FLAG_ARRAY |
  36532                           SOC_REG_FLAG_WO |
  36533                           SOC_REG_FLAG_REG_ARRAY,
  36534         0,
  36535         5,
  36536         soc_BRDC_FMAC_EDS_STATUS_BCM88650_B0r_fields,
  36537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36538         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  36539         -1,
  36540         -1,
  36541     },
  36542 #endif /* chips */
  36543 
  36544 #if defined(BCM_88660_A0)
  36545     { /* SOC_REG_INT_BRDC_FMAC_EDS_STATUS_BCM88660_A0r */
  36546         soc_block_list[23],
  36547         soc_genreg,
  36548         4,
  36549         0,
  36550         0xd0,
  36551         SOC_REG_FLAG_ARRAY |
  36552                           SOC_REG_FLAG_WO |
  36553                           SOC_REG_FLAG_REG_ARRAY,
  36554         0,
  36555         5,
  36556         soc_BRDC_FMAC_EDS_STATUS_BCM88660_A0r_fields,
  36557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36558         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  36559         -1,
  36560         -1,
  36561     },
  36562 #endif /* chips */
  36563 
  36564 #if defined(BCM_88650_A0)
  36565     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATIONr */
  36566         soc_block_list[23],
  36567         soc_genreg,
  36568         4,
  36569         0,
  36570         0x1e4,
  36571         SOC_REG_FLAG_ARRAY |
  36572                           SOC_REG_FLAG_WO |
  36573                           SOC_REG_FLAG_REG_ARRAY,
  36574         0,
  36575         6,
  36576         soc_BRDC_FMAC_ERROR_INITIATIONr_fields,
  36577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36578         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  36579         -1,
  36580         -1,
  36581     },
  36582 #endif /* chips */
  36583 
  36584 #if defined(BCM_88202_A0)
  36585     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_BCM88202_A0r */
  36586         soc_block_list[23],
  36587         soc_genreg,
  36588         4,
  36589         0,
  36590         0x1e4,
  36591         SOC_REG_FLAG_ARRAY |
  36592                           SOC_REG_FLAG_WO |
  36593                           SOC_REG_FLAG_REG_ARRAY,
  36594         0,
  36595         6,
  36596         soc_BRDC_FMAC_ERROR_INITIATION_BCM88202_A0r_fields,
  36597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36598         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  36599         -1,
  36600         -1,
  36601     },
  36602 #endif /* chips */
  36603 
  36604 #if defined(BCM_88650_B0)
  36605     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_BCM88650_B0r */
  36606         soc_block_list[23],
  36607         soc_genreg,
  36608         4,
  36609         0,
  36610         0x1e4,
  36611         SOC_REG_FLAG_ARRAY |
  36612                           SOC_REG_FLAG_WO |
  36613                           SOC_REG_FLAG_REG_ARRAY,
  36614         0,
  36615         6,
  36616         soc_BRDC_FMAC_ERROR_INITIATION_BCM88650_B0r_fields,
  36617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36618         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  36619         -1,
  36620         -1,
  36621     },
  36622 #endif /* chips */
  36623 
  36624 #if defined(BCM_88660_A0)
  36625     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_BCM88660_A0r */
  36626         soc_block_list[23],
  36627         soc_genreg,
  36628         4,
  36629         0,
  36630         0x1e4,
  36631         SOC_REG_FLAG_ARRAY |
  36632                           SOC_REG_FLAG_WO |
  36633                           SOC_REG_FLAG_REG_ARRAY,
  36634         0,
  36635         6,
  36636         soc_BRDC_FMAC_ERROR_INITIATION_BCM88660_A0r_fields,
  36637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36638         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  36639         -1,
  36640         -1,
  36641     },
  36642 #endif /* chips */
  36643 
  36644 #if defined(BCM_88675_A0)
  36645     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATAr */
  36646         soc_block_list[23],
  36647         soc_genreg,
  36648         1,
  36649         0,
  36650         0xa3,
  36651         SOC_REG_FLAG_WO,
  36652         0,
  36653         1,
  36654         soc_BRDC_FMAC_ERROR_INITIATION_DATAr_fields,
  36655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36656         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36657         -1,
  36658         -1,
  36659     },
  36660 #endif /* chips */
  36661 
  36662 #if defined(BCM_83208_A0)
  36663     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM83208_A0r */
  36664         soc_block_list[23],
  36665         soc_genreg,
  36666         1,
  36667         0,
  36668         0xa3,
  36669         SOC_REG_FLAG_WO,
  36670         0,
  36671         1,
  36672         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM83208_A0r_fields,
  36673         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36674         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36675         -1,
  36676         -1,
  36677     },
  36678 #endif /* chips */
  36679 
  36680 #if defined(BCM_88375_A0)
  36681     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88375_A0r */
  36682         soc_block_list[23],
  36683         soc_genreg,
  36684         1,
  36685         0,
  36686         0xa3,
  36687         SOC_REG_FLAG_WO,
  36688         0,
  36689         1,
  36690         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88375_A0r_fields,
  36691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36692         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36693         -1,
  36694         -1,
  36695     },
  36696 #endif /* chips */
  36697 
  36698 #if defined(BCM_88375_B0)
  36699     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88375_B0r */
  36700         soc_block_list[23],
  36701         soc_genreg,
  36702         1,
  36703         0,
  36704         0xa3,
  36705         SOC_REG_FLAG_WO,
  36706         0,
  36707         1,
  36708         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88375_B0r_fields,
  36709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36710         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36711         -1,
  36712         -1,
  36713     },
  36714 #endif /* chips */
  36715 
  36716 #if defined(BCM_88470_A0)
  36717     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88470_A0r */
  36718         soc_block_list[23],
  36719         soc_genreg,
  36720         1,
  36721         0,
  36722         0xa3,
  36723         SOC_REG_FLAG_WO,
  36724         0,
  36725         1,
  36726         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88470_A0r_fields,
  36727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36728         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36729         -1,
  36730         -1,
  36731     },
  36732 #endif /* chips */
  36733 
  36734 #if defined(BCM_88470_B0)
  36735     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88470_B0r */
  36736         soc_block_list[23],
  36737         soc_genreg,
  36738         1,
  36739         0,
  36740         0xa3,
  36741         SOC_REG_FLAG_WO,
  36742         0,
  36743         1,
  36744         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88470_B0r_fields,
  36745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36746         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36747         -1,
  36748         -1,
  36749     },
  36750 #endif /* chips */
  36751 
  36752 #if defined(BCM_88675_B0)
  36753     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88675_B0r */
  36754         soc_block_list[23],
  36755         soc_genreg,
  36756         1,
  36757         0,
  36758         0xa3,
  36759         SOC_REG_FLAG_WO,
  36760         0,
  36761         1,
  36762         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88675_B0r_fields,
  36763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36764         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36765         -1,
  36766         -1,
  36767     },
  36768 #endif /* chips */
  36769 
  36770 #if defined(BCM_88680_A0)
  36771     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88680_A0r */
  36772         soc_block_list[23],
  36773         soc_genreg,
  36774         1,
  36775         0,
  36776         0xa3,
  36777         SOC_REG_FLAG_WO,
  36778         0,
  36779         1,
  36780         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88680_A0r_fields,
  36781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36782         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36783         -1,
  36784         -1,
  36785     },
  36786 #endif /* chips */
  36787 
  36788 #if defined(BCM_88690_A0)
  36789     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88690_A0r */
  36790         soc_block_list[23],
  36791         soc_genreg,
  36792         1,
  36793         0,
  36794         0xa3,
  36795         SOC_REG_FLAG_WO,
  36796         0,
  36797         1,
  36798         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88690_A0r_fields,
  36799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36800         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36801         -1,
  36802         -1,
  36803     },
  36804 #endif /* chips */
  36805 
  36806 #if defined(BCM_88790_A0)
  36807     { /* SOC_REG_INT_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88790_A0r */
  36808         soc_block_list[23],
  36809         soc_genreg,
  36810         1,
  36811         0,
  36812         0xa3,
  36813         SOC_REG_FLAG_WO,
  36814         0,
  36815         1,
  36816         soc_BRDC_FMAC_ERROR_INITIATION_DATA_BCM88790_A0r_fields,
  36817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36818         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  36819         -1,
  36820         -1,
  36821     },
  36822 #endif /* chips */
  36823 
  36824 #if defined(BCM_88650_A0)
  36825     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0r */
  36826         soc_block_list[23],
  36827         soc_genreg,
  36828         1,
  36829         0,
  36830         0x65,
  36831         SOC_REG_FLAG_WO,
  36832         0,
  36833         2,
  36834         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0r_fields,
  36835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36836         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  36837         -1,
  36838         -1,
  36839     },
  36840 #endif /* chips */
  36841 
  36842 #if defined(BCM_88650_A0)
  36843     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1r */
  36844         soc_block_list[23],
  36845         soc_genreg,
  36846         1,
  36847         0,
  36848         0x66,
  36849         SOC_REG_FLAG_WO,
  36850         0,
  36851         1,
  36852         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1r_fields,
  36853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36854         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  36855         -1,
  36856         -1,
  36857     },
  36858 #endif /* chips */
  36859 
  36860 #if defined(BCM_88202_A0)
  36861     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0_BCM88202_A0r */
  36862         soc_block_list[23],
  36863         soc_genreg,
  36864         1,
  36865         0,
  36866         0x65,
  36867         SOC_REG_FLAG_WO,
  36868         0,
  36869         2,
  36870         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0_BCM88202_A0r_fields,
  36871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36872         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  36873         -1,
  36874         -1,
  36875     },
  36876 #endif /* chips */
  36877 
  36878 #if defined(BCM_88650_B0)
  36879     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0_BCM88650_B0r */
  36880         soc_block_list[23],
  36881         soc_genreg,
  36882         1,
  36883         0,
  36884         0x65,
  36885         SOC_REG_FLAG_WO,
  36886         0,
  36887         2,
  36888         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0_BCM88650_B0r_fields,
  36889         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36890         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  36891         -1,
  36892         -1,
  36893     },
  36894 #endif /* chips */
  36895 
  36896 #if defined(BCM_88660_A0)
  36897     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0_BCM88660_A0r */
  36898         soc_block_list[23],
  36899         soc_genreg,
  36900         1,
  36901         0,
  36902         0x65,
  36903         SOC_REG_FLAG_WO,
  36904         0,
  36905         2,
  36906         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0_BCM88660_A0r_fields,
  36907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36908         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  36909         -1,
  36910         -1,
  36911     },
  36912 #endif /* chips */
  36913 
  36914 #if defined(BCM_88202_A0)
  36915     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1_BCM88202_A0r */
  36916         soc_block_list[23],
  36917         soc_genreg,
  36918         1,
  36919         0,
  36920         0x66,
  36921         SOC_REG_FLAG_WO,
  36922         0,
  36923         1,
  36924         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1_BCM88202_A0r_fields,
  36925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36926         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  36927         -1,
  36928         -1,
  36929     },
  36930 #endif /* chips */
  36931 
  36932 #if defined(BCM_88650_B0)
  36933     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1_BCM88650_B0r */
  36934         soc_block_list[23],
  36935         soc_genreg,
  36936         1,
  36937         0,
  36938         0x66,
  36939         SOC_REG_FLAG_WO,
  36940         0,
  36941         1,
  36942         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1_BCM88650_B0r_fields,
  36943         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36944         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  36945         -1,
  36946         -1,
  36947     },
  36948 #endif /* chips */
  36949 
  36950 #if defined(BCM_88660_A0)
  36951     { /* SOC_REG_INT_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1_BCM88660_A0r */
  36952         soc_block_list[23],
  36953         soc_genreg,
  36954         1,
  36955         0,
  36956         0x66,
  36957         SOC_REG_FLAG_WO,
  36958         0,
  36959         1,
  36960         soc_BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1_BCM88660_A0r_fields,
  36961         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  36962         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  36963         -1,
  36964         -1,
  36965     },
  36966 #endif /* chips */
  36967 
  36968 #if defined(BCM_83208_A0)
  36969     { /* SOC_REG_INT_BRDC_FMAC_FAP_GLOBAL_GENERAL_CFG_1r */
  36970         soc_block_list[23],
  36971         soc_genreg,
  36972         1,
  36973         0,
  36974         0xc1,
  36975         SOC_REG_FLAG_WO,
  36976         0,
  36977         2,
  36978         soc_BRDC_FMAC_FAP_GLOBAL_GENERAL_CFG_1r_fields,
  36979         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  36980         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36981         -1,
  36982         -1,
  36983     },
  36984 #endif /* chips */
  36985 
  36986 #if defined(BCM_88690_A0)
  36987     { /* SOC_REG_INT_BRDC_FMAC_FAP_GLOBAL_GENERAL_CFG_1_BCM88690_A0r */
  36988         soc_block_list[23],
  36989         soc_genreg,
  36990         1,
  36991         0,
  36992         0xc3,
  36993         SOC_REG_FLAG_WO,
  36994         0,
  36995         2,
  36996         soc_BRDC_FMAC_FAP_GLOBAL_GENERAL_CFG_1_BCM88690_A0r_fields,
  36997         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  36998         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  36999         -1,
  37000         -1,
  37001     },
  37002 #endif /* chips */
  37003 
  37004 #if defined(BCM_88790_A0)
  37005     { /* SOC_REG_INT_BRDC_FMAC_FAP_GLOBAL_GENERAL_CFG_1_BCM88790_A0r */
  37006         soc_block_list[23],
  37007         soc_genreg,
  37008         1,
  37009         0,
  37010         0xc3,
  37011         SOC_REG_FLAG_WO,
  37012         0,
  37013         2,
  37014         soc_BRDC_FMAC_FAP_GLOBAL_GENERAL_CFG_1_BCM88790_A0r_fields,
  37015         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  37016         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  37017         -1,
  37018         -1,
  37019     },
  37020 #endif /* chips */
  37021 
  37022 #if defined(BCM_88650_A0)
  37023     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_Ar */
  37024         soc_block_list[23],
  37025         soc_genreg,
  37026         1,
  37027         0,
  37028         0x1da,
  37029         SOC_REG_FLAG_WO,
  37030         0,
  37031         8,
  37032         soc_BRDC_FMAC_FBIST_CONFIGURATION_Ar_fields,
  37033         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37034         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37035         -1,
  37036         -1,
  37037     },
  37038 #endif /* chips */
  37039 
  37040 #if defined(BCM_83208_A0)
  37041     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM83208_A0r */
  37042         soc_block_list[23],
  37043         soc_genreg,
  37044         1,
  37045         0,
  37046         0x1da,
  37047         SOC_REG_FLAG_WO,
  37048         0,
  37049         8,
  37050         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM83208_A0r_fields,
  37051         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37052         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37053         -1,
  37054         -1,
  37055     },
  37056 #endif /* chips */
  37057 
  37058 #if defined(BCM_88202_A0)
  37059     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88202_A0r */
  37060         soc_block_list[23],
  37061         soc_genreg,
  37062         1,
  37063         0,
  37064         0x1da,
  37065         SOC_REG_FLAG_WO,
  37066         0,
  37067         8,
  37068         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88202_A0r_fields,
  37069         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37070         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37071         -1,
  37072         -1,
  37073     },
  37074 #endif /* chips */
  37075 
  37076 #if defined(BCM_88375_A0)
  37077     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88375_A0r */
  37078         soc_block_list[23],
  37079         soc_genreg,
  37080         1,
  37081         0,
  37082         0x1da,
  37083         SOC_REG_FLAG_WO,
  37084         0,
  37085         8,
  37086         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88375_A0r_fields,
  37087         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37088         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37089         -1,
  37090         -1,
  37091     },
  37092 #endif /* chips */
  37093 
  37094 #if defined(BCM_88375_B0)
  37095     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88375_B0r */
  37096         soc_block_list[23],
  37097         soc_genreg,
  37098         1,
  37099         0,
  37100         0x1da,
  37101         SOC_REG_FLAG_WO,
  37102         0,
  37103         8,
  37104         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88375_B0r_fields,
  37105         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37106         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37107         -1,
  37108         -1,
  37109     },
  37110 #endif /* chips */
  37111 
  37112 #if defined(BCM_88470_A0)
  37113     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88470_A0r */
  37114         soc_block_list[23],
  37115         soc_genreg,
  37116         1,
  37117         0,
  37118         0x1da,
  37119         SOC_REG_FLAG_WO,
  37120         0,
  37121         8,
  37122         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88470_A0r_fields,
  37123         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37124         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37125         -1,
  37126         -1,
  37127     },
  37128 #endif /* chips */
  37129 
  37130 #if defined(BCM_88470_B0)
  37131     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88470_B0r */
  37132         soc_block_list[23],
  37133         soc_genreg,
  37134         1,
  37135         0,
  37136         0x1da,
  37137         SOC_REG_FLAG_WO,
  37138         0,
  37139         8,
  37140         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88470_B0r_fields,
  37141         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37142         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37143         -1,
  37144         -1,
  37145     },
  37146 #endif /* chips */
  37147 
  37148 #if defined(BCM_88650_B0)
  37149     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88650_B0r */
  37150         soc_block_list[23],
  37151         soc_genreg,
  37152         1,
  37153         0,
  37154         0x1da,
  37155         SOC_REG_FLAG_WO,
  37156         0,
  37157         8,
  37158         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88650_B0r_fields,
  37159         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37160         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37161         -1,
  37162         -1,
  37163     },
  37164 #endif /* chips */
  37165 
  37166 #if defined(BCM_88660_A0)
  37167     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88660_A0r */
  37168         soc_block_list[23],
  37169         soc_genreg,
  37170         1,
  37171         0,
  37172         0x1da,
  37173         SOC_REG_FLAG_WO,
  37174         0,
  37175         8,
  37176         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88660_A0r_fields,
  37177         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37178         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37179         -1,
  37180         -1,
  37181     },
  37182 #endif /* chips */
  37183 
  37184 #if defined(BCM_88675_A0)
  37185     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88675_A0r */
  37186         soc_block_list[23],
  37187         soc_genreg,
  37188         1,
  37189         0,
  37190         0x1da,
  37191         SOC_REG_FLAG_WO,
  37192         0,
  37193         8,
  37194         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88675_A0r_fields,
  37195         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37196         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37197         -1,
  37198         -1,
  37199     },
  37200 #endif /* chips */
  37201 
  37202 #if defined(BCM_88675_B0)
  37203     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88675_B0r */
  37204         soc_block_list[23],
  37205         soc_genreg,
  37206         1,
  37207         0,
  37208         0x1da,
  37209         SOC_REG_FLAG_WO,
  37210         0,
  37211         8,
  37212         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88675_B0r_fields,
  37213         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37214         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37215         -1,
  37216         -1,
  37217     },
  37218 #endif /* chips */
  37219 
  37220 #if defined(BCM_88680_A0)
  37221     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88680_A0r */
  37222         soc_block_list[23],
  37223         soc_genreg,
  37224         1,
  37225         0,
  37226         0x1da,
  37227         SOC_REG_FLAG_WO,
  37228         0,
  37229         8,
  37230         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88680_A0r_fields,
  37231         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37232         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37233         -1,
  37234         -1,
  37235     },
  37236 #endif /* chips */
  37237 
  37238 #if defined(BCM_88690_A0)
  37239     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88690_A0r */
  37240         soc_block_list[23],
  37241         soc_genreg,
  37242         1,
  37243         0,
  37244         0x1e4,
  37245         SOC_REG_FLAG_WO,
  37246         0,
  37247         8,
  37248         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88690_A0r_fields,
  37249         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37250         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37251         -1,
  37252         -1,
  37253     },
  37254 #endif /* chips */
  37255 
  37256 #if defined(BCM_88690_B0)
  37257     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88690_B0r */
  37258         soc_block_list[23],
  37259         soc_genreg,
  37260         1,
  37261         0,
  37262         0x1e4,
  37263         SOC_REG_FLAG_WO,
  37264         0,
  37265         8,
  37266         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88690_B0r_fields,
  37267         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37268         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37269         -1,
  37270         -1,
  37271     },
  37272 #endif /* chips */
  37273 
  37274 #if defined(BCM_88790_A0)
  37275     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88790_A0r */
  37276         soc_block_list[23],
  37277         soc_genreg,
  37278         1,
  37279         0,
  37280         0x1e4,
  37281         SOC_REG_FLAG_WO,
  37282         0,
  37283         8,
  37284         soc_BRDC_FMAC_FBIST_CONFIGURATION_A_BCM88790_A0r_fields,
  37285         SOC_RESET_VAL_DEC(0x00004021, 0x00000000)
  37286         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  37287         -1,
  37288         -1,
  37289     },
  37290 #endif /* chips */
  37291 
  37292 #if defined(BCM_88650_A0)
  37293     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_Br */
  37294         soc_block_list[23],
  37295         soc_genreg,
  37296         1,
  37297         0,
  37298         0x1db,
  37299         SOC_REG_FLAG_WO,
  37300         0,
  37301         1,
  37302         soc_BRDC_FMAC_FBIST_CONFIGURATION_Br_fields,
  37303         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37304         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37305         -1,
  37306         -1,
  37307     },
  37308 #endif /* chips */
  37309 
  37310 #if defined(BCM_83208_A0)
  37311     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM83208_A0r */
  37312         soc_block_list[23],
  37313         soc_genreg,
  37314         1,
  37315         0,
  37316         0x1db,
  37317         SOC_REG_FLAG_WO,
  37318         0,
  37319         1,
  37320         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM83208_A0r_fields,
  37321         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37322         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37323         -1,
  37324         -1,
  37325     },
  37326 #endif /* chips */
  37327 
  37328 #if defined(BCM_88202_A0)
  37329     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88202_A0r */
  37330         soc_block_list[23],
  37331         soc_genreg,
  37332         1,
  37333         0,
  37334         0x1db,
  37335         SOC_REG_FLAG_WO,
  37336         0,
  37337         1,
  37338         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88202_A0r_fields,
  37339         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37340         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37341         -1,
  37342         -1,
  37343     },
  37344 #endif /* chips */
  37345 
  37346 #if defined(BCM_88375_A0)
  37347     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88375_A0r */
  37348         soc_block_list[23],
  37349         soc_genreg,
  37350         1,
  37351         0,
  37352         0x1db,
  37353         SOC_REG_FLAG_WO,
  37354         0,
  37355         1,
  37356         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88375_A0r_fields,
  37357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37358         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37359         -1,
  37360         -1,
  37361     },
  37362 #endif /* chips */
  37363 
  37364 #if defined(BCM_88375_B0)
  37365     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88375_B0r */
  37366         soc_block_list[23],
  37367         soc_genreg,
  37368         1,
  37369         0,
  37370         0x1db,
  37371         SOC_REG_FLAG_WO,
  37372         0,
  37373         1,
  37374         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88375_B0r_fields,
  37375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37376         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37377         -1,
  37378         -1,
  37379     },
  37380 #endif /* chips */
  37381 
  37382 #if defined(BCM_88470_A0)
  37383     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88470_A0r */
  37384         soc_block_list[23],
  37385         soc_genreg,
  37386         1,
  37387         0,
  37388         0x1db,
  37389         SOC_REG_FLAG_WO,
  37390         0,
  37391         1,
  37392         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88470_A0r_fields,
  37393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37394         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37395         -1,
  37396         -1,
  37397     },
  37398 #endif /* chips */
  37399 
  37400 #if defined(BCM_88470_B0)
  37401     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88470_B0r */
  37402         soc_block_list[23],
  37403         soc_genreg,
  37404         1,
  37405         0,
  37406         0x1db,
  37407         SOC_REG_FLAG_WO,
  37408         0,
  37409         1,
  37410         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88470_B0r_fields,
  37411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37412         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37413         -1,
  37414         -1,
  37415     },
  37416 #endif /* chips */
  37417 
  37418 #if defined(BCM_88650_B0)
  37419     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88650_B0r */
  37420         soc_block_list[23],
  37421         soc_genreg,
  37422         1,
  37423         0,
  37424         0x1db,
  37425         SOC_REG_FLAG_WO,
  37426         0,
  37427         1,
  37428         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88650_B0r_fields,
  37429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37430         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37431         -1,
  37432         -1,
  37433     },
  37434 #endif /* chips */
  37435 
  37436 #if defined(BCM_88660_A0)
  37437     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88660_A0r */
  37438         soc_block_list[23],
  37439         soc_genreg,
  37440         1,
  37441         0,
  37442         0x1db,
  37443         SOC_REG_FLAG_WO,
  37444         0,
  37445         1,
  37446         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88660_A0r_fields,
  37447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37448         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37449         -1,
  37450         -1,
  37451     },
  37452 #endif /* chips */
  37453 
  37454 #if defined(BCM_88675_A0)
  37455     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88675_A0r */
  37456         soc_block_list[23],
  37457         soc_genreg,
  37458         1,
  37459         0,
  37460         0x1db,
  37461         SOC_REG_FLAG_WO,
  37462         0,
  37463         1,
  37464         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88675_A0r_fields,
  37465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37466         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37467         -1,
  37468         -1,
  37469     },
  37470 #endif /* chips */
  37471 
  37472 #if defined(BCM_88675_B0)
  37473     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88675_B0r */
  37474         soc_block_list[23],
  37475         soc_genreg,
  37476         1,
  37477         0,
  37478         0x1db,
  37479         SOC_REG_FLAG_WO,
  37480         0,
  37481         1,
  37482         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88675_B0r_fields,
  37483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37484         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37485         -1,
  37486         -1,
  37487     },
  37488 #endif /* chips */
  37489 
  37490 #if defined(BCM_88680_A0)
  37491     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88680_A0r */
  37492         soc_block_list[23],
  37493         soc_genreg,
  37494         1,
  37495         0,
  37496         0x1db,
  37497         SOC_REG_FLAG_WO,
  37498         0,
  37499         1,
  37500         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88680_A0r_fields,
  37501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37502         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37503         -1,
  37504         -1,
  37505     },
  37506 #endif /* chips */
  37507 
  37508 #if defined(BCM_88690_A0)
  37509     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88690_A0r */
  37510         soc_block_list[23],
  37511         soc_genreg,
  37512         1,
  37513         0,
  37514         0x1e5,
  37515         SOC_REG_FLAG_WO,
  37516         0,
  37517         1,
  37518         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88690_A0r_fields,
  37519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37520         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37521         -1,
  37522         -1,
  37523     },
  37524 #endif /* chips */
  37525 
  37526 #if defined(BCM_88690_B0)
  37527     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88690_B0r */
  37528         soc_block_list[23],
  37529         soc_genreg,
  37530         1,
  37531         0,
  37532         0x1e5,
  37533         SOC_REG_FLAG_WO,
  37534         0,
  37535         1,
  37536         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88690_B0r_fields,
  37537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37538         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37539         -1,
  37540         -1,
  37541     },
  37542 #endif /* chips */
  37543 
  37544 #if defined(BCM_88790_A0)
  37545     { /* SOC_REG_INT_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88790_A0r */
  37546         soc_block_list[23],
  37547         soc_genreg,
  37548         1,
  37549         0,
  37550         0x1e5,
  37551         SOC_REG_FLAG_WO,
  37552         0,
  37553         1,
  37554         soc_BRDC_FMAC_FBIST_CONFIGURATION_B_BCM88790_A0r_fields,
  37555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37556         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  37557         -1,
  37558         -1,
  37559     },
  37560 #endif /* chips */
  37561 
  37562 #if defined(BCM_88650_A0)
  37563     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUSr */
  37564         soc_block_list[23],
  37565         soc_genreg,
  37566         1,
  37567         0,
  37568         0x1dc,
  37569         SOC_REG_FLAG_WO,
  37570         0,
  37571         1,
  37572         soc_BRDC_FMAC_FBIST_STATUSr_fields,
  37573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37574         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37575         -1,
  37576         -1,
  37577     },
  37578 #endif /* chips */
  37579 
  37580 #if defined(BCM_83208_A0)
  37581     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM83208_A0r */
  37582         soc_block_list[23],
  37583         soc_genreg,
  37584         1,
  37585         0,
  37586         0x1dc,
  37587         SOC_REG_FLAG_RO |
  37588                           SOC_REG_FLAG_WO,
  37589         0,
  37590         1,
  37591         soc_BRDC_FMAC_FBIST_STATUS_BCM83208_A0r_fields,
  37592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37593         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37594         -1,
  37595         -1,
  37596     },
  37597 #endif /* chips */
  37598 
  37599 #if defined(BCM_88202_A0)
  37600     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88202_A0r */
  37601         soc_block_list[23],
  37602         soc_genreg,
  37603         1,
  37604         0,
  37605         0x1dc,
  37606         SOC_REG_FLAG_WO,
  37607         0,
  37608         1,
  37609         soc_BRDC_FMAC_FBIST_STATUS_BCM88202_A0r_fields,
  37610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37611         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37612         -1,
  37613         -1,
  37614     },
  37615 #endif /* chips */
  37616 
  37617 #if defined(BCM_88375_A0)
  37618     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88375_A0r */
  37619         soc_block_list[23],
  37620         soc_genreg,
  37621         1,
  37622         0,
  37623         0x1dc,
  37624         SOC_REG_FLAG_RO |
  37625                           SOC_REG_FLAG_WO,
  37626         0,
  37627         1,
  37628         soc_BRDC_FMAC_FBIST_STATUS_BCM88375_A0r_fields,
  37629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37630         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37631         -1,
  37632         -1,
  37633     },
  37634 #endif /* chips */
  37635 
  37636 #if defined(BCM_88375_B0)
  37637     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88375_B0r */
  37638         soc_block_list[23],
  37639         soc_genreg,
  37640         1,
  37641         0,
  37642         0x1dc,
  37643         SOC_REG_FLAG_RO |
  37644                           SOC_REG_FLAG_WO,
  37645         0,
  37646         1,
  37647         soc_BRDC_FMAC_FBIST_STATUS_BCM88375_B0r_fields,
  37648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37649         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37650         -1,
  37651         -1,
  37652     },
  37653 #endif /* chips */
  37654 
  37655 #if defined(BCM_88470_A0)
  37656     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88470_A0r */
  37657         soc_block_list[23],
  37658         soc_genreg,
  37659         1,
  37660         0,
  37661         0x1dc,
  37662         SOC_REG_FLAG_RO |
  37663                           SOC_REG_FLAG_WO,
  37664         0,
  37665         1,
  37666         soc_BRDC_FMAC_FBIST_STATUS_BCM88470_A0r_fields,
  37667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37668         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37669         -1,
  37670         -1,
  37671     },
  37672 #endif /* chips */
  37673 
  37674 #if defined(BCM_88470_B0)
  37675     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88470_B0r */
  37676         soc_block_list[23],
  37677         soc_genreg,
  37678         1,
  37679         0,
  37680         0x1dc,
  37681         SOC_REG_FLAG_RO |
  37682                           SOC_REG_FLAG_WO,
  37683         0,
  37684         1,
  37685         soc_BRDC_FMAC_FBIST_STATUS_BCM88470_B0r_fields,
  37686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37687         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37688         -1,
  37689         -1,
  37690     },
  37691 #endif /* chips */
  37692 
  37693 #if defined(BCM_88650_B0)
  37694     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88650_B0r */
  37695         soc_block_list[23],
  37696         soc_genreg,
  37697         1,
  37698         0,
  37699         0x1dc,
  37700         SOC_REG_FLAG_WO,
  37701         0,
  37702         1,
  37703         soc_BRDC_FMAC_FBIST_STATUS_BCM88650_B0r_fields,
  37704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37705         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37706         -1,
  37707         -1,
  37708     },
  37709 #endif /* chips */
  37710 
  37711 #if defined(BCM_88660_A0)
  37712     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88660_A0r */
  37713         soc_block_list[23],
  37714         soc_genreg,
  37715         1,
  37716         0,
  37717         0x1dc,
  37718         SOC_REG_FLAG_WO,
  37719         0,
  37720         1,
  37721         soc_BRDC_FMAC_FBIST_STATUS_BCM88660_A0r_fields,
  37722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37723         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37724         -1,
  37725         -1,
  37726     },
  37727 #endif /* chips */
  37728 
  37729 #if defined(BCM_88675_A0)
  37730     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88675_A0r */
  37731         soc_block_list[23],
  37732         soc_genreg,
  37733         1,
  37734         0,
  37735         0x1dc,
  37736         SOC_REG_FLAG_RO |
  37737                           SOC_REG_FLAG_WO,
  37738         0,
  37739         1,
  37740         soc_BRDC_FMAC_FBIST_STATUS_BCM88675_A0r_fields,
  37741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37742         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37743         -1,
  37744         -1,
  37745     },
  37746 #endif /* chips */
  37747 
  37748 #if defined(BCM_88675_B0)
  37749     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88675_B0r */
  37750         soc_block_list[23],
  37751         soc_genreg,
  37752         1,
  37753         0,
  37754         0x1dc,
  37755         SOC_REG_FLAG_RO |
  37756                           SOC_REG_FLAG_WO,
  37757         0,
  37758         1,
  37759         soc_BRDC_FMAC_FBIST_STATUS_BCM88675_B0r_fields,
  37760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37761         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37762         -1,
  37763         -1,
  37764     },
  37765 #endif /* chips */
  37766 
  37767 #if defined(BCM_88680_A0)
  37768     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88680_A0r */
  37769         soc_block_list[23],
  37770         soc_genreg,
  37771         1,
  37772         0,
  37773         0x1dc,
  37774         SOC_REG_FLAG_RO |
  37775                           SOC_REG_FLAG_WO,
  37776         0,
  37777         1,
  37778         soc_BRDC_FMAC_FBIST_STATUS_BCM88680_A0r_fields,
  37779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37780         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37781         -1,
  37782         -1,
  37783     },
  37784 #endif /* chips */
  37785 
  37786 #if defined(BCM_88690_A0)
  37787     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88690_A0r */
  37788         soc_block_list[23],
  37789         soc_genreg,
  37790         1,
  37791         0,
  37792         0x1e6,
  37793         SOC_REG_FLAG_RO |
  37794                           SOC_REG_FLAG_WO,
  37795         0,
  37796         1,
  37797         soc_BRDC_FMAC_FBIST_STATUS_BCM88690_A0r_fields,
  37798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37799         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37800         -1,
  37801         -1,
  37802     },
  37803 #endif /* chips */
  37804 
  37805 #if defined(BCM_88690_B0)
  37806     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88690_B0r */
  37807         soc_block_list[23],
  37808         soc_genreg,
  37809         1,
  37810         0,
  37811         0x1e6,
  37812         SOC_REG_FLAG_RO |
  37813                           SOC_REG_FLAG_WO,
  37814         0,
  37815         1,
  37816         soc_BRDC_FMAC_FBIST_STATUS_BCM88690_B0r_fields,
  37817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37818         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37819         -1,
  37820         -1,
  37821     },
  37822 #endif /* chips */
  37823 
  37824 #if defined(BCM_88790_A0)
  37825     { /* SOC_REG_INT_BRDC_FMAC_FBIST_STATUS_BCM88790_A0r */
  37826         soc_block_list[23],
  37827         soc_genreg,
  37828         1,
  37829         0,
  37830         0x1e6,
  37831         SOC_REG_FLAG_RO |
  37832                           SOC_REG_FLAG_WO,
  37833         0,
  37834         1,
  37835         soc_BRDC_FMAC_FBIST_STATUS_BCM88790_A0r_fields,
  37836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37837         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  37838         -1,
  37839         -1,
  37840     },
  37841 #endif /* chips */
  37842 
  37843 #if defined(BCM_83208_A0)
  37844     { /* SOC_REG_INT_BRDC_FMAC_FE_GLOBAL_GENERAL_CFG_1r */
  37845         soc_block_list[23],
  37846         soc_genreg,
  37847         1,
  37848         0,
  37849         0xf1,
  37850         SOC_REG_FLAG_WO,
  37851         0,
  37852         4,
  37853         soc_BRDC_FMAC_FE_GLOBAL_GENERAL_CFG_1r_fields,
  37854         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  37855         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  37856         -1,
  37857         -1,
  37858     },
  37859 #endif /* chips */
  37860 
  37861 #if defined(BCM_88690_A0)
  37862     { /* SOC_REG_INT_BRDC_FMAC_FE_GLOBAL_GENERAL_CFG_1_BCM88690_A0r */
  37863         soc_block_list[23],
  37864         soc_genreg,
  37865         1,
  37866         0,
  37867         0xf4,
  37868         SOC_REG_FLAG_WO,
  37869         0,
  37870         4,
  37871         soc_BRDC_FMAC_FE_GLOBAL_GENERAL_CFG_1_BCM88690_A0r_fields,
  37872         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  37873         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  37874         -1,
  37875         -1,
  37876     },
  37877 #endif /* chips */
  37878 
  37879 #if defined(BCM_88790_A0)
  37880     { /* SOC_REG_INT_BRDC_FMAC_FE_GLOBAL_GENERAL_CFG_1_BCM88790_A0r */
  37881         soc_block_list[23],
  37882         soc_genreg,
  37883         1,
  37884         0,
  37885         0xf4,
  37886         SOC_REG_FLAG_WO,
  37887         0,
  37888         4,
  37889         soc_BRDC_FMAC_FE_GLOBAL_GENERAL_CFG_1_BCM88790_A0r_fields,
  37890         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  37891         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  37892         -1,
  37893         -1,
  37894     },
  37895 #endif /* chips */
  37896 
  37897 #if defined(BCM_88675_A0)
  37898     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1r */
  37899         soc_block_list[23],
  37900         soc_genreg,
  37901         1,
  37902         0,
  37903         0x211,
  37904         SOC_REG_FLAG_WO,
  37905         0,
  37906         2,
  37907         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1r_fields,
  37908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37909         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  37910         -1,
  37911         -1,
  37912     },
  37913 #endif /* chips */
  37914 
  37915 #if defined(BCM_88675_A0)
  37916     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2r */
  37917         soc_block_list[23],
  37918         soc_genreg,
  37919         1,
  37920         0,
  37921         0x212,
  37922         SOC_REG_FLAG_WO,
  37923         0,
  37924         2,
  37925         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2r_fields,
  37926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37927         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  37928         -1,
  37929         -1,
  37930     },
  37931 #endif /* chips */
  37932 
  37933 #if defined(BCM_88675_A0)
  37934     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3r */
  37935         soc_block_list[23],
  37936         soc_genreg,
  37937         1,
  37938         0,
  37939         0x213,
  37940         SOC_REG_FLAG_WO,
  37941         0,
  37942         2,
  37943         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3r_fields,
  37944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37945         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  37946         -1,
  37947         -1,
  37948     },
  37949 #endif /* chips */
  37950 
  37951 #if defined(BCM_88675_A0)
  37952     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4r */
  37953         soc_block_list[23],
  37954         soc_genreg,
  37955         1,
  37956         0,
  37957         0x214,
  37958         SOC_REG_FLAG_WO,
  37959         0,
  37960         2,
  37961         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4r_fields,
  37962         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37963         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  37964         -1,
  37965         -1,
  37966     },
  37967 #endif /* chips */
  37968 
  37969 #if defined(BCM_88675_A0)
  37970     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5r */
  37971         soc_block_list[23],
  37972         soc_genreg,
  37973         1,
  37974         0,
  37975         0x215,
  37976         SOC_REG_FLAG_WO,
  37977         0,
  37978         2,
  37979         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5r_fields,
  37980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37981         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  37982         -1,
  37983         -1,
  37984     },
  37985 #endif /* chips */
  37986 
  37987 #if defined(BCM_88675_A0)
  37988     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6r */
  37989         soc_block_list[23],
  37990         soc_genreg,
  37991         1,
  37992         0,
  37993         0x216,
  37994         SOC_REG_FLAG_WO,
  37995         0,
  37996         2,
  37997         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6r_fields,
  37998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  37999         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38000         -1,
  38001         -1,
  38002     },
  38003 #endif /* chips */
  38004 
  38005 #if defined(BCM_88675_A0)
  38006     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7r */
  38007         soc_block_list[23],
  38008         soc_genreg,
  38009         1,
  38010         0,
  38011         0x217,
  38012         SOC_REG_FLAG_WO,
  38013         0,
  38014         2,
  38015         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7r_fields,
  38016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38017         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38018         -1,
  38019         -1,
  38020     },
  38021 #endif /* chips */
  38022 
  38023 #if defined(BCM_88675_A0)
  38024     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8r */
  38025         soc_block_list[23],
  38026         soc_genreg,
  38027         1,
  38028         0,
  38029         0x218,
  38030         SOC_REG_FLAG_WO,
  38031         0,
  38032         3,
  38033         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8r_fields,
  38034         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38035         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  38036         -1,
  38037         -1,
  38038     },
  38039 #endif /* chips */
  38040 
  38041 #if defined(BCM_83208_A0)
  38042     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM83208_A0r */
  38043         soc_block_list[23],
  38044         soc_genreg,
  38045         1,
  38046         0,
  38047         0x211,
  38048         SOC_REG_FLAG_WO,
  38049         0,
  38050         2,
  38051         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM83208_A0r_fields,
  38052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38053         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38054         -1,
  38055         -1,
  38056     },
  38057 #endif /* chips */
  38058 
  38059 #if defined(BCM_88375_A0)
  38060     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88375_A0r */
  38061         soc_block_list[23],
  38062         soc_genreg,
  38063         1,
  38064         0,
  38065         0x211,
  38066         SOC_REG_FLAG_WO,
  38067         0,
  38068         2,
  38069         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88375_A0r_fields,
  38070         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38071         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38072         -1,
  38073         -1,
  38074     },
  38075 #endif /* chips */
  38076 
  38077 #if defined(BCM_88375_B0)
  38078     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88375_B0r */
  38079         soc_block_list[23],
  38080         soc_genreg,
  38081         1,
  38082         0,
  38083         0x211,
  38084         SOC_REG_FLAG_WO,
  38085         0,
  38086         2,
  38087         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88375_B0r_fields,
  38088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38089         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38090         -1,
  38091         -1,
  38092     },
  38093 #endif /* chips */
  38094 
  38095 #if defined(BCM_88470_A0)
  38096     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88470_A0r */
  38097         soc_block_list[23],
  38098         soc_genreg,
  38099         1,
  38100         0,
  38101         0x211,
  38102         SOC_REG_FLAG_WO,
  38103         0,
  38104         2,
  38105         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88470_A0r_fields,
  38106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38107         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38108         -1,
  38109         -1,
  38110     },
  38111 #endif /* chips */
  38112 
  38113 #if defined(BCM_88470_B0)
  38114     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88470_B0r */
  38115         soc_block_list[23],
  38116         soc_genreg,
  38117         1,
  38118         0,
  38119         0x211,
  38120         SOC_REG_FLAG_WO,
  38121         0,
  38122         2,
  38123         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88470_B0r_fields,
  38124         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38125         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38126         -1,
  38127         -1,
  38128     },
  38129 #endif /* chips */
  38130 
  38131 #if defined(BCM_88675_B0)
  38132     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88675_B0r */
  38133         soc_block_list[23],
  38134         soc_genreg,
  38135         1,
  38136         0,
  38137         0x211,
  38138         SOC_REG_FLAG_WO,
  38139         0,
  38140         2,
  38141         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88675_B0r_fields,
  38142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38143         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38144         -1,
  38145         -1,
  38146     },
  38147 #endif /* chips */
  38148 
  38149 #if defined(BCM_88680_A0)
  38150     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88680_A0r */
  38151         soc_block_list[23],
  38152         soc_genreg,
  38153         1,
  38154         0,
  38155         0x211,
  38156         SOC_REG_FLAG_WO,
  38157         0,
  38158         2,
  38159         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88680_A0r_fields,
  38160         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38161         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38162         -1,
  38163         -1,
  38164     },
  38165 #endif /* chips */
  38166 
  38167 #if defined(BCM_88690_A0)
  38168     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88690_A0r */
  38169         soc_block_list[23],
  38170         soc_genreg,
  38171         1,
  38172         0,
  38173         0x101,
  38174         SOC_REG_FLAG_WO,
  38175         0,
  38176         2,
  38177         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88690_A0r_fields,
  38178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38179         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38180         -1,
  38181         -1,
  38182     },
  38183 #endif /* chips */
  38184 
  38185 #if defined(BCM_88690_B0)
  38186     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88690_B0r */
  38187         soc_block_list[23],
  38188         soc_genreg,
  38189         1,
  38190         0,
  38191         0x101,
  38192         SOC_REG_FLAG_WO,
  38193         0,
  38194         2,
  38195         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88690_B0r_fields,
  38196         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38197         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38198         -1,
  38199         -1,
  38200     },
  38201 #endif /* chips */
  38202 
  38203 #if defined(BCM_88790_A0)
  38204     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88790_A0r */
  38205         soc_block_list[23],
  38206         soc_genreg,
  38207         1,
  38208         0,
  38209         0x101,
  38210         SOC_REG_FLAG_WO,
  38211         0,
  38212         2,
  38213         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88790_A0r_fields,
  38214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38215         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38216         -1,
  38217         -1,
  38218     },
  38219 #endif /* chips */
  38220 
  38221 #if defined(BCM_83208_A0)
  38222     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM83208_A0r */
  38223         soc_block_list[23],
  38224         soc_genreg,
  38225         1,
  38226         0,
  38227         0x212,
  38228         SOC_REG_FLAG_WO,
  38229         0,
  38230         2,
  38231         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM83208_A0r_fields,
  38232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38233         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38234         -1,
  38235         -1,
  38236     },
  38237 #endif /* chips */
  38238 
  38239 #if defined(BCM_88375_A0)
  38240     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88375_A0r */
  38241         soc_block_list[23],
  38242         soc_genreg,
  38243         1,
  38244         0,
  38245         0x212,
  38246         SOC_REG_FLAG_WO,
  38247         0,
  38248         2,
  38249         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88375_A0r_fields,
  38250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38251         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38252         -1,
  38253         -1,
  38254     },
  38255 #endif /* chips */
  38256 
  38257 #if defined(BCM_88375_B0)
  38258     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88375_B0r */
  38259         soc_block_list[23],
  38260         soc_genreg,
  38261         1,
  38262         0,
  38263         0x212,
  38264         SOC_REG_FLAG_WO,
  38265         0,
  38266         2,
  38267         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88375_B0r_fields,
  38268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38269         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38270         -1,
  38271         -1,
  38272     },
  38273 #endif /* chips */
  38274 
  38275 #if defined(BCM_88470_A0)
  38276     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88470_A0r */
  38277         soc_block_list[23],
  38278         soc_genreg,
  38279         1,
  38280         0,
  38281         0x212,
  38282         SOC_REG_FLAG_WO,
  38283         0,
  38284         2,
  38285         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88470_A0r_fields,
  38286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38287         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38288         -1,
  38289         -1,
  38290     },
  38291 #endif /* chips */
  38292 
  38293 #if defined(BCM_88470_B0)
  38294     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88470_B0r */
  38295         soc_block_list[23],
  38296         soc_genreg,
  38297         1,
  38298         0,
  38299         0x212,
  38300         SOC_REG_FLAG_WO,
  38301         0,
  38302         2,
  38303         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88470_B0r_fields,
  38304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38305         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38306         -1,
  38307         -1,
  38308     },
  38309 #endif /* chips */
  38310 
  38311 #if defined(BCM_88675_B0)
  38312     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88675_B0r */
  38313         soc_block_list[23],
  38314         soc_genreg,
  38315         1,
  38316         0,
  38317         0x212,
  38318         SOC_REG_FLAG_WO,
  38319         0,
  38320         2,
  38321         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88675_B0r_fields,
  38322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38323         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38324         -1,
  38325         -1,
  38326     },
  38327 #endif /* chips */
  38328 
  38329 #if defined(BCM_88680_A0)
  38330     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88680_A0r */
  38331         soc_block_list[23],
  38332         soc_genreg,
  38333         1,
  38334         0,
  38335         0x212,
  38336         SOC_REG_FLAG_WO,
  38337         0,
  38338         2,
  38339         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88680_A0r_fields,
  38340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38341         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38342         -1,
  38343         -1,
  38344     },
  38345 #endif /* chips */
  38346 
  38347 #if defined(BCM_88690_A0)
  38348     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88690_A0r */
  38349         soc_block_list[23],
  38350         soc_genreg,
  38351         1,
  38352         0,
  38353         0x104,
  38354         SOC_REG_FLAG_WO,
  38355         0,
  38356         2,
  38357         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88690_A0r_fields,
  38358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38359         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38360         -1,
  38361         -1,
  38362     },
  38363 #endif /* chips */
  38364 
  38365 #if defined(BCM_88690_B0)
  38366     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88690_B0r */
  38367         soc_block_list[23],
  38368         soc_genreg,
  38369         1,
  38370         0,
  38371         0x104,
  38372         SOC_REG_FLAG_WO,
  38373         0,
  38374         2,
  38375         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88690_B0r_fields,
  38376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38377         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38378         -1,
  38379         -1,
  38380     },
  38381 #endif /* chips */
  38382 
  38383 #if defined(BCM_88790_A0)
  38384     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88790_A0r */
  38385         soc_block_list[23],
  38386         soc_genreg,
  38387         1,
  38388         0,
  38389         0x104,
  38390         SOC_REG_FLAG_WO,
  38391         0,
  38392         2,
  38393         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88790_A0r_fields,
  38394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38395         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38396         -1,
  38397         -1,
  38398     },
  38399 #endif /* chips */
  38400 
  38401 #if defined(BCM_83208_A0)
  38402     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM83208_A0r */
  38403         soc_block_list[23],
  38404         soc_genreg,
  38405         1,
  38406         0,
  38407         0x213,
  38408         SOC_REG_FLAG_WO,
  38409         0,
  38410         2,
  38411         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM83208_A0r_fields,
  38412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38413         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38414         -1,
  38415         -1,
  38416     },
  38417 #endif /* chips */
  38418 
  38419 #if defined(BCM_88375_A0)
  38420     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88375_A0r */
  38421         soc_block_list[23],
  38422         soc_genreg,
  38423         1,
  38424         0,
  38425         0x213,
  38426         SOC_REG_FLAG_WO,
  38427         0,
  38428         2,
  38429         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88375_A0r_fields,
  38430         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38431         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38432         -1,
  38433         -1,
  38434     },
  38435 #endif /* chips */
  38436 
  38437 #if defined(BCM_88375_B0)
  38438     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88375_B0r */
  38439         soc_block_list[23],
  38440         soc_genreg,
  38441         1,
  38442         0,
  38443         0x213,
  38444         SOC_REG_FLAG_WO,
  38445         0,
  38446         2,
  38447         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88375_B0r_fields,
  38448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38449         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38450         -1,
  38451         -1,
  38452     },
  38453 #endif /* chips */
  38454 
  38455 #if defined(BCM_88470_A0)
  38456     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88470_A0r */
  38457         soc_block_list[23],
  38458         soc_genreg,
  38459         1,
  38460         0,
  38461         0x213,
  38462         SOC_REG_FLAG_WO,
  38463         0,
  38464         2,
  38465         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88470_A0r_fields,
  38466         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38467         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38468         -1,
  38469         -1,
  38470     },
  38471 #endif /* chips */
  38472 
  38473 #if defined(BCM_88470_B0)
  38474     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88470_B0r */
  38475         soc_block_list[23],
  38476         soc_genreg,
  38477         1,
  38478         0,
  38479         0x213,
  38480         SOC_REG_FLAG_WO,
  38481         0,
  38482         2,
  38483         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88470_B0r_fields,
  38484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38485         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38486         -1,
  38487         -1,
  38488     },
  38489 #endif /* chips */
  38490 
  38491 #if defined(BCM_88675_B0)
  38492     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88675_B0r */
  38493         soc_block_list[23],
  38494         soc_genreg,
  38495         1,
  38496         0,
  38497         0x213,
  38498         SOC_REG_FLAG_WO,
  38499         0,
  38500         2,
  38501         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88675_B0r_fields,
  38502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38503         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38504         -1,
  38505         -1,
  38506     },
  38507 #endif /* chips */
  38508 
  38509 #if defined(BCM_88680_A0)
  38510     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88680_A0r */
  38511         soc_block_list[23],
  38512         soc_genreg,
  38513         1,
  38514         0,
  38515         0x213,
  38516         SOC_REG_FLAG_WO,
  38517         0,
  38518         2,
  38519         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88680_A0r_fields,
  38520         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38521         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38522         -1,
  38523         -1,
  38524     },
  38525 #endif /* chips */
  38526 
  38527 #if defined(BCM_88690_A0)
  38528     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88690_A0r */
  38529         soc_block_list[23],
  38530         soc_genreg,
  38531         1,
  38532         0,
  38533         0x107,
  38534         SOC_REG_FLAG_WO,
  38535         0,
  38536         2,
  38537         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88690_A0r_fields,
  38538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38539         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38540         -1,
  38541         -1,
  38542     },
  38543 #endif /* chips */
  38544 
  38545 #if defined(BCM_88690_B0)
  38546     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88690_B0r */
  38547         soc_block_list[23],
  38548         soc_genreg,
  38549         1,
  38550         0,
  38551         0x107,
  38552         SOC_REG_FLAG_WO,
  38553         0,
  38554         2,
  38555         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88690_B0r_fields,
  38556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38557         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38558         -1,
  38559         -1,
  38560     },
  38561 #endif /* chips */
  38562 
  38563 #if defined(BCM_88790_A0)
  38564     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88790_A0r */
  38565         soc_block_list[23],
  38566         soc_genreg,
  38567         1,
  38568         0,
  38569         0x107,
  38570         SOC_REG_FLAG_WO,
  38571         0,
  38572         2,
  38573         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88790_A0r_fields,
  38574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38575         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38576         -1,
  38577         -1,
  38578     },
  38579 #endif /* chips */
  38580 
  38581 #if defined(BCM_83208_A0)
  38582     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM83208_A0r */
  38583         soc_block_list[23],
  38584         soc_genreg,
  38585         1,
  38586         0,
  38587         0x214,
  38588         SOC_REG_FLAG_WO,
  38589         0,
  38590         2,
  38591         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM83208_A0r_fields,
  38592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38593         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38594         -1,
  38595         -1,
  38596     },
  38597 #endif /* chips */
  38598 
  38599 #if defined(BCM_88375_A0)
  38600     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88375_A0r */
  38601         soc_block_list[23],
  38602         soc_genreg,
  38603         1,
  38604         0,
  38605         0x214,
  38606         SOC_REG_FLAG_WO,
  38607         0,
  38608         2,
  38609         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88375_A0r_fields,
  38610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38611         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38612         -1,
  38613         -1,
  38614     },
  38615 #endif /* chips */
  38616 
  38617 #if defined(BCM_88375_B0)
  38618     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88375_B0r */
  38619         soc_block_list[23],
  38620         soc_genreg,
  38621         1,
  38622         0,
  38623         0x214,
  38624         SOC_REG_FLAG_WO,
  38625         0,
  38626         2,
  38627         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88375_B0r_fields,
  38628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38629         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38630         -1,
  38631         -1,
  38632     },
  38633 #endif /* chips */
  38634 
  38635 #if defined(BCM_88470_A0)
  38636     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88470_A0r */
  38637         soc_block_list[23],
  38638         soc_genreg,
  38639         1,
  38640         0,
  38641         0x214,
  38642         SOC_REG_FLAG_WO,
  38643         0,
  38644         2,
  38645         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88470_A0r_fields,
  38646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38647         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38648         -1,
  38649         -1,
  38650     },
  38651 #endif /* chips */
  38652 
  38653 #if defined(BCM_88470_B0)
  38654     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88470_B0r */
  38655         soc_block_list[23],
  38656         soc_genreg,
  38657         1,
  38658         0,
  38659         0x214,
  38660         SOC_REG_FLAG_WO,
  38661         0,
  38662         2,
  38663         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88470_B0r_fields,
  38664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38665         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38666         -1,
  38667         -1,
  38668     },
  38669 #endif /* chips */
  38670 
  38671 #if defined(BCM_88675_B0)
  38672     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88675_B0r */
  38673         soc_block_list[23],
  38674         soc_genreg,
  38675         1,
  38676         0,
  38677         0x214,
  38678         SOC_REG_FLAG_WO,
  38679         0,
  38680         2,
  38681         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88675_B0r_fields,
  38682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38683         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38684         -1,
  38685         -1,
  38686     },
  38687 #endif /* chips */
  38688 
  38689 #if defined(BCM_88680_A0)
  38690     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88680_A0r */
  38691         soc_block_list[23],
  38692         soc_genreg,
  38693         1,
  38694         0,
  38695         0x214,
  38696         SOC_REG_FLAG_WO,
  38697         0,
  38698         2,
  38699         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88680_A0r_fields,
  38700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38701         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38702         -1,
  38703         -1,
  38704     },
  38705 #endif /* chips */
  38706 
  38707 #if defined(BCM_88690_A0)
  38708     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88690_A0r */
  38709         soc_block_list[23],
  38710         soc_genreg,
  38711         1,
  38712         0,
  38713         0x10a,
  38714         SOC_REG_FLAG_WO,
  38715         0,
  38716         2,
  38717         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88690_A0r_fields,
  38718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38719         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38720         -1,
  38721         -1,
  38722     },
  38723 #endif /* chips */
  38724 
  38725 #if defined(BCM_88690_B0)
  38726     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88690_B0r */
  38727         soc_block_list[23],
  38728         soc_genreg,
  38729         1,
  38730         0,
  38731         0x10a,
  38732         SOC_REG_FLAG_WO,
  38733         0,
  38734         2,
  38735         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88690_B0r_fields,
  38736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38737         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38738         -1,
  38739         -1,
  38740     },
  38741 #endif /* chips */
  38742 
  38743 #if defined(BCM_88790_A0)
  38744     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88790_A0r */
  38745         soc_block_list[23],
  38746         soc_genreg,
  38747         1,
  38748         0,
  38749         0x10a,
  38750         SOC_REG_FLAG_WO,
  38751         0,
  38752         2,
  38753         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88790_A0r_fields,
  38754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38755         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38756         -1,
  38757         -1,
  38758     },
  38759 #endif /* chips */
  38760 
  38761 #if defined(BCM_83208_A0)
  38762     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM83208_A0r */
  38763         soc_block_list[23],
  38764         soc_genreg,
  38765         1,
  38766         0,
  38767         0x215,
  38768         SOC_REG_FLAG_WO,
  38769         0,
  38770         1,
  38771         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM83208_A0r_fields,
  38772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38773         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38774         -1,
  38775         -1,
  38776     },
  38777 #endif /* chips */
  38778 
  38779 #if defined(BCM_88375_A0)
  38780     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88375_A0r */
  38781         soc_block_list[23],
  38782         soc_genreg,
  38783         1,
  38784         0,
  38785         0x215,
  38786         SOC_REG_FLAG_WO,
  38787         0,
  38788         2,
  38789         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88375_A0r_fields,
  38790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38791         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38792         -1,
  38793         -1,
  38794     },
  38795 #endif /* chips */
  38796 
  38797 #if defined(BCM_88375_B0)
  38798     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88375_B0r */
  38799         soc_block_list[23],
  38800         soc_genreg,
  38801         1,
  38802         0,
  38803         0x215,
  38804         SOC_REG_FLAG_WO,
  38805         0,
  38806         2,
  38807         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88375_B0r_fields,
  38808         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38809         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38810         -1,
  38811         -1,
  38812     },
  38813 #endif /* chips */
  38814 
  38815 #if defined(BCM_88470_A0)
  38816     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88470_A0r */
  38817         soc_block_list[23],
  38818         soc_genreg,
  38819         1,
  38820         0,
  38821         0x215,
  38822         SOC_REG_FLAG_WO,
  38823         0,
  38824         3,
  38825         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88470_A0r_fields,
  38826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38827         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  38828         -1,
  38829         -1,
  38830     },
  38831 #endif /* chips */
  38832 
  38833 #if defined(BCM_88470_B0)
  38834     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88470_B0r */
  38835         soc_block_list[23],
  38836         soc_genreg,
  38837         1,
  38838         0,
  38839         0x215,
  38840         SOC_REG_FLAG_WO,
  38841         0,
  38842         3,
  38843         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88470_B0r_fields,
  38844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38845         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  38846         -1,
  38847         -1,
  38848     },
  38849 #endif /* chips */
  38850 
  38851 #if defined(BCM_88675_B0)
  38852     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88675_B0r */
  38853         soc_block_list[23],
  38854         soc_genreg,
  38855         1,
  38856         0,
  38857         0x215,
  38858         SOC_REG_FLAG_WO,
  38859         0,
  38860         2,
  38861         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88675_B0r_fields,
  38862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38863         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38864         -1,
  38865         -1,
  38866     },
  38867 #endif /* chips */
  38868 
  38869 #if defined(BCM_88680_A0)
  38870     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88680_A0r */
  38871         soc_block_list[23],
  38872         soc_genreg,
  38873         1,
  38874         0,
  38875         0x215,
  38876         SOC_REG_FLAG_WO,
  38877         0,
  38878         2,
  38879         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88680_A0r_fields,
  38880         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38881         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38882         -1,
  38883         -1,
  38884     },
  38885 #endif /* chips */
  38886 
  38887 #if defined(BCM_88690_A0)
  38888     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88690_A0r */
  38889         soc_block_list[23],
  38890         soc_genreg,
  38891         1,
  38892         0,
  38893         0x10d,
  38894         SOC_REG_FLAG_WO,
  38895         0,
  38896         1,
  38897         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88690_A0r_fields,
  38898         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38899         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38900         -1,
  38901         -1,
  38902     },
  38903 #endif /* chips */
  38904 
  38905 #if defined(BCM_88690_B0)
  38906     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88690_B0r */
  38907         soc_block_list[23],
  38908         soc_genreg,
  38909         1,
  38910         0,
  38911         0x10d,
  38912         SOC_REG_FLAG_WO,
  38913         0,
  38914         1,
  38915         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88690_B0r_fields,
  38916         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38917         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38918         -1,
  38919         -1,
  38920     },
  38921 #endif /* chips */
  38922 
  38923 #if defined(BCM_88790_A0)
  38924     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88790_A0r */
  38925         soc_block_list[23],
  38926         soc_genreg,
  38927         1,
  38928         0,
  38929         0x10d,
  38930         SOC_REG_FLAG_WO,
  38931         0,
  38932         1,
  38933         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88790_A0r_fields,
  38934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38935         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  38936         -1,
  38937         -1,
  38938     },
  38939 #endif /* chips */
  38940 
  38941 #if defined(BCM_83208_A0)
  38942     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM83208_A0r */
  38943         soc_block_list[23],
  38944         soc_genreg,
  38945         1,
  38946         0,
  38947         0x216,
  38948         SOC_REG_FLAG_WO,
  38949         0,
  38950         2,
  38951         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM83208_A0r_fields,
  38952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38953         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38954         -1,
  38955         -1,
  38956     },
  38957 #endif /* chips */
  38958 
  38959 #if defined(BCM_88375_A0)
  38960     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88375_A0r */
  38961         soc_block_list[23],
  38962         soc_genreg,
  38963         1,
  38964         0,
  38965         0x216,
  38966         SOC_REG_FLAG_WO,
  38967         0,
  38968         2,
  38969         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88375_A0r_fields,
  38970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38971         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38972         -1,
  38973         -1,
  38974     },
  38975 #endif /* chips */
  38976 
  38977 #if defined(BCM_88375_B0)
  38978     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88375_B0r */
  38979         soc_block_list[23],
  38980         soc_genreg,
  38981         1,
  38982         0,
  38983         0x216,
  38984         SOC_REG_FLAG_WO,
  38985         0,
  38986         2,
  38987         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88375_B0r_fields,
  38988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  38989         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  38990         -1,
  38991         -1,
  38992     },
  38993 #endif /* chips */
  38994 
  38995 #if defined(BCM_88470_A0)
  38996     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88470_A0r */
  38997         soc_block_list[23],
  38998         soc_genreg,
  38999         1,
  39000         0,
  39001         0x216,
  39002         SOC_REG_FLAG_WO,
  39003         0,
  39004         2,
  39005         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88470_A0r_fields,
  39006         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39007         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39008         -1,
  39009         -1,
  39010     },
  39011 #endif /* chips */
  39012 
  39013 #if defined(BCM_88470_B0)
  39014     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88470_B0r */
  39015         soc_block_list[23],
  39016         soc_genreg,
  39017         1,
  39018         0,
  39019         0x216,
  39020         SOC_REG_FLAG_WO,
  39021         0,
  39022         2,
  39023         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88470_B0r_fields,
  39024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39025         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39026         -1,
  39027         -1,
  39028     },
  39029 #endif /* chips */
  39030 
  39031 #if defined(BCM_88675_B0)
  39032     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88675_B0r */
  39033         soc_block_list[23],
  39034         soc_genreg,
  39035         1,
  39036         0,
  39037         0x216,
  39038         SOC_REG_FLAG_WO,
  39039         0,
  39040         2,
  39041         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88675_B0r_fields,
  39042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39043         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39044         -1,
  39045         -1,
  39046     },
  39047 #endif /* chips */
  39048 
  39049 #if defined(BCM_88680_A0)
  39050     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88680_A0r */
  39051         soc_block_list[23],
  39052         soc_genreg,
  39053         1,
  39054         0,
  39055         0x216,
  39056         SOC_REG_FLAG_WO,
  39057         0,
  39058         2,
  39059         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88680_A0r_fields,
  39060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39061         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39062         -1,
  39063         -1,
  39064     },
  39065 #endif /* chips */
  39066 
  39067 #if defined(BCM_88690_A0)
  39068     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88690_A0r */
  39069         soc_block_list[23],
  39070         soc_genreg,
  39071         1,
  39072         0,
  39073         0x110,
  39074         SOC_REG_FLAG_WO,
  39075         0,
  39076         2,
  39077         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88690_A0r_fields,
  39078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39079         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39080         -1,
  39081         -1,
  39082     },
  39083 #endif /* chips */
  39084 
  39085 #if defined(BCM_88690_B0)
  39086     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88690_B0r */
  39087         soc_block_list[23],
  39088         soc_genreg,
  39089         1,
  39090         0,
  39091         0x110,
  39092         SOC_REG_FLAG_WO,
  39093         0,
  39094         2,
  39095         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88690_B0r_fields,
  39096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39097         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39098         -1,
  39099         -1,
  39100     },
  39101 #endif /* chips */
  39102 
  39103 #if defined(BCM_88790_A0)
  39104     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88790_A0r */
  39105         soc_block_list[23],
  39106         soc_genreg,
  39107         1,
  39108         0,
  39109         0x110,
  39110         SOC_REG_FLAG_WO,
  39111         0,
  39112         2,
  39113         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88790_A0r_fields,
  39114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39115         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39116         -1,
  39117         -1,
  39118     },
  39119 #endif /* chips */
  39120 
  39121 #if defined(BCM_83208_A0)
  39122     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM83208_A0r */
  39123         soc_block_list[23],
  39124         soc_genreg,
  39125         1,
  39126         0,
  39127         0x217,
  39128         SOC_REG_FLAG_WO,
  39129         0,
  39130         2,
  39131         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM83208_A0r_fields,
  39132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39133         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39134         -1,
  39135         -1,
  39136     },
  39137 #endif /* chips */
  39138 
  39139 #if defined(BCM_88375_A0)
  39140     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88375_A0r */
  39141         soc_block_list[23],
  39142         soc_genreg,
  39143         1,
  39144         0,
  39145         0x217,
  39146         SOC_REG_FLAG_WO,
  39147         0,
  39148         2,
  39149         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88375_A0r_fields,
  39150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39151         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39152         -1,
  39153         -1,
  39154     },
  39155 #endif /* chips */
  39156 
  39157 #if defined(BCM_88375_B0)
  39158     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88375_B0r */
  39159         soc_block_list[23],
  39160         soc_genreg,
  39161         1,
  39162         0,
  39163         0x217,
  39164         SOC_REG_FLAG_WO,
  39165         0,
  39166         2,
  39167         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88375_B0r_fields,
  39168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39169         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39170         -1,
  39171         -1,
  39172     },
  39173 #endif /* chips */
  39174 
  39175 #if defined(BCM_88470_A0)
  39176     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88470_A0r */
  39177         soc_block_list[23],
  39178         soc_genreg,
  39179         1,
  39180         0,
  39181         0x217,
  39182         SOC_REG_FLAG_WO,
  39183         0,
  39184         2,
  39185         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88470_A0r_fields,
  39186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39187         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39188         -1,
  39189         -1,
  39190     },
  39191 #endif /* chips */
  39192 
  39193 #if defined(BCM_88470_B0)
  39194     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88470_B0r */
  39195         soc_block_list[23],
  39196         soc_genreg,
  39197         1,
  39198         0,
  39199         0x217,
  39200         SOC_REG_FLAG_WO,
  39201         0,
  39202         2,
  39203         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88470_B0r_fields,
  39204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39205         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39206         -1,
  39207         -1,
  39208     },
  39209 #endif /* chips */
  39210 
  39211 #if defined(BCM_88675_B0)
  39212     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88675_B0r */
  39213         soc_block_list[23],
  39214         soc_genreg,
  39215         1,
  39216         0,
  39217         0x217,
  39218         SOC_REG_FLAG_WO,
  39219         0,
  39220         2,
  39221         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88675_B0r_fields,
  39222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39223         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39224         -1,
  39225         -1,
  39226     },
  39227 #endif /* chips */
  39228 
  39229 #if defined(BCM_88680_A0)
  39230     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88680_A0r */
  39231         soc_block_list[23],
  39232         soc_genreg,
  39233         1,
  39234         0,
  39235         0x217,
  39236         SOC_REG_FLAG_WO,
  39237         0,
  39238         2,
  39239         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88680_A0r_fields,
  39240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39241         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39242         -1,
  39243         -1,
  39244     },
  39245 #endif /* chips */
  39246 
  39247 #if defined(BCM_88690_A0)
  39248     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88690_A0r */
  39249         soc_block_list[23],
  39250         soc_genreg,
  39251         1,
  39252         0,
  39253         0x113,
  39254         SOC_REG_FLAG_WO,
  39255         0,
  39256         2,
  39257         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88690_A0r_fields,
  39258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39259         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39260         -1,
  39261         -1,
  39262     },
  39263 #endif /* chips */
  39264 
  39265 #if defined(BCM_88690_B0)
  39266     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88690_B0r */
  39267         soc_block_list[23],
  39268         soc_genreg,
  39269         1,
  39270         0,
  39271         0x113,
  39272         SOC_REG_FLAG_WO,
  39273         0,
  39274         2,
  39275         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88690_B0r_fields,
  39276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39277         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39278         -1,
  39279         -1,
  39280     },
  39281 #endif /* chips */
  39282 
  39283 #if defined(BCM_88790_A0)
  39284     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88790_A0r */
  39285         soc_block_list[23],
  39286         soc_genreg,
  39287         1,
  39288         0,
  39289         0x113,
  39290         SOC_REG_FLAG_WO,
  39291         0,
  39292         2,
  39293         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88790_A0r_fields,
  39294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39295         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39296         -1,
  39297         -1,
  39298     },
  39299 #endif /* chips */
  39300 
  39301 #if defined(BCM_83208_A0)
  39302     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM83208_A0r */
  39303         soc_block_list[23],
  39304         soc_genreg,
  39305         1,
  39306         0,
  39307         0x218,
  39308         SOC_REG_FLAG_WO,
  39309         0,
  39310         3,
  39311         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM83208_A0r_fields,
  39312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39313         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39314         -1,
  39315         -1,
  39316     },
  39317 #endif /* chips */
  39318 
  39319 #if defined(BCM_88375_A0)
  39320     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88375_A0r */
  39321         soc_block_list[23],
  39322         soc_genreg,
  39323         1,
  39324         0,
  39325         0x218,
  39326         SOC_REG_FLAG_WO,
  39327         0,
  39328         3,
  39329         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88375_A0r_fields,
  39330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39331         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39332         -1,
  39333         -1,
  39334     },
  39335 #endif /* chips */
  39336 
  39337 #if defined(BCM_88375_B0)
  39338     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88375_B0r */
  39339         soc_block_list[23],
  39340         soc_genreg,
  39341         1,
  39342         0,
  39343         0x218,
  39344         SOC_REG_FLAG_WO,
  39345         0,
  39346         3,
  39347         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88375_B0r_fields,
  39348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39349         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39350         -1,
  39351         -1,
  39352     },
  39353 #endif /* chips */
  39354 
  39355 #if defined(BCM_88470_A0)
  39356     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88470_A0r */
  39357         soc_block_list[23],
  39358         soc_genreg,
  39359         1,
  39360         0,
  39361         0x218,
  39362         SOC_REG_FLAG_WO,
  39363         0,
  39364         3,
  39365         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88470_A0r_fields,
  39366         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39367         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39368         -1,
  39369         -1,
  39370     },
  39371 #endif /* chips */
  39372 
  39373 #if defined(BCM_88470_B0)
  39374     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88470_B0r */
  39375         soc_block_list[23],
  39376         soc_genreg,
  39377         1,
  39378         0,
  39379         0x218,
  39380         SOC_REG_FLAG_WO,
  39381         0,
  39382         3,
  39383         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88470_B0r_fields,
  39384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39385         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39386         -1,
  39387         -1,
  39388     },
  39389 #endif /* chips */
  39390 
  39391 #if defined(BCM_88675_B0)
  39392     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88675_B0r */
  39393         soc_block_list[23],
  39394         soc_genreg,
  39395         1,
  39396         0,
  39397         0x218,
  39398         SOC_REG_FLAG_WO,
  39399         0,
  39400         3,
  39401         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88675_B0r_fields,
  39402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39403         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39404         -1,
  39405         -1,
  39406     },
  39407 #endif /* chips */
  39408 
  39409 #if defined(BCM_88680_A0)
  39410     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88680_A0r */
  39411         soc_block_list[23],
  39412         soc_genreg,
  39413         1,
  39414         0,
  39415         0x218,
  39416         SOC_REG_FLAG_WO,
  39417         0,
  39418         3,
  39419         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88680_A0r_fields,
  39420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39421         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39422         -1,
  39423         -1,
  39424     },
  39425 #endif /* chips */
  39426 
  39427 #if defined(BCM_88690_A0)
  39428     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88690_A0r */
  39429         soc_block_list[23],
  39430         soc_genreg,
  39431         1,
  39432         0,
  39433         0x116,
  39434         SOC_REG_FLAG_WO,
  39435         0,
  39436         3,
  39437         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88690_A0r_fields,
  39438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39439         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39440         -1,
  39441         -1,
  39442     },
  39443 #endif /* chips */
  39444 
  39445 #if defined(BCM_88690_B0)
  39446     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88690_B0r */
  39447         soc_block_list[23],
  39448         soc_genreg,
  39449         1,
  39450         0,
  39451         0x116,
  39452         SOC_REG_FLAG_WO,
  39453         0,
  39454         3,
  39455         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88690_B0r_fields,
  39456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39457         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39458         -1,
  39459         -1,
  39460     },
  39461 #endif /* chips */
  39462 
  39463 #if defined(BCM_88790_A0)
  39464     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88790_A0r */
  39465         soc_block_list[23],
  39466         soc_genreg,
  39467         1,
  39468         0,
  39469         0x116,
  39470         SOC_REG_FLAG_WO,
  39471         0,
  39472         3,
  39473         soc_BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88790_A0r_fields,
  39474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39475         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39476         -1,
  39477         -1,
  39478     },
  39479 #endif /* chips */
  39480 
  39481 #if defined(BCM_88675_A0)
  39482     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1r */
  39483         soc_block_list[23],
  39484         soc_genreg,
  39485         1,
  39486         0,
  39487         0x201,
  39488         SOC_REG_FLAG_WO |
  39489                           SOC_REG_FLAG_INTERRUPT,
  39490         0,
  39491         2,
  39492         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1r_fields,
  39493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39494         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39495         -1,
  39496         -1,
  39497     },
  39498 #endif /* chips */
  39499 
  39500 #if defined(BCM_88675_A0)
  39501     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2r */
  39502         soc_block_list[23],
  39503         soc_genreg,
  39504         1,
  39505         0,
  39506         0x202,
  39507         SOC_REG_FLAG_WO |
  39508                           SOC_REG_FLAG_INTERRUPT,
  39509         0,
  39510         2,
  39511         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2r_fields,
  39512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39513         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39514         -1,
  39515         -1,
  39516     },
  39517 #endif /* chips */
  39518 
  39519 #if defined(BCM_88675_A0)
  39520     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3r */
  39521         soc_block_list[23],
  39522         soc_genreg,
  39523         1,
  39524         0,
  39525         0x203,
  39526         SOC_REG_FLAG_WO |
  39527                           SOC_REG_FLAG_INTERRUPT,
  39528         0,
  39529         2,
  39530         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3r_fields,
  39531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39532         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39533         -1,
  39534         -1,
  39535     },
  39536 #endif /* chips */
  39537 
  39538 #if defined(BCM_88675_A0)
  39539     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4r */
  39540         soc_block_list[23],
  39541         soc_genreg,
  39542         1,
  39543         0,
  39544         0x204,
  39545         SOC_REG_FLAG_WO |
  39546                           SOC_REG_FLAG_INTERRUPT,
  39547         0,
  39548         2,
  39549         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4r_fields,
  39550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39551         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39552         -1,
  39553         -1,
  39554     },
  39555 #endif /* chips */
  39556 
  39557 #if defined(BCM_88675_A0)
  39558     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5r */
  39559         soc_block_list[23],
  39560         soc_genreg,
  39561         1,
  39562         0,
  39563         0x205,
  39564         SOC_REG_FLAG_WO |
  39565                           SOC_REG_FLAG_INTERRUPT,
  39566         0,
  39567         2,
  39568         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5r_fields,
  39569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39570         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39571         -1,
  39572         -1,
  39573     },
  39574 #endif /* chips */
  39575 
  39576 #if defined(BCM_88675_A0)
  39577     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6r */
  39578         soc_block_list[23],
  39579         soc_genreg,
  39580         1,
  39581         0,
  39582         0x206,
  39583         SOC_REG_FLAG_WO |
  39584                           SOC_REG_FLAG_INTERRUPT,
  39585         0,
  39586         2,
  39587         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6r_fields,
  39588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39589         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39590         -1,
  39591         -1,
  39592     },
  39593 #endif /* chips */
  39594 
  39595 #if defined(BCM_88675_A0)
  39596     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7r */
  39597         soc_block_list[23],
  39598         soc_genreg,
  39599         1,
  39600         0,
  39601         0x207,
  39602         SOC_REG_FLAG_WO |
  39603                           SOC_REG_FLAG_INTERRUPT,
  39604         0,
  39605         2,
  39606         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7r_fields,
  39607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39608         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39609         -1,
  39610         -1,
  39611     },
  39612 #endif /* chips */
  39613 
  39614 #if defined(BCM_88675_A0)
  39615     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8r */
  39616         soc_block_list[23],
  39617         soc_genreg,
  39618         1,
  39619         0,
  39620         0x208,
  39621         SOC_REG_FLAG_WO |
  39622                           SOC_REG_FLAG_INTERRUPT,
  39623         0,
  39624         3,
  39625         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8r_fields,
  39626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39627         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  39628         -1,
  39629         -1,
  39630     },
  39631 #endif /* chips */
  39632 
  39633 #if defined(BCM_83208_A0)
  39634     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM83208_A0r */
  39635         soc_block_list[23],
  39636         soc_genreg,
  39637         1,
  39638         0,
  39639         0x201,
  39640         SOC_REG_FLAG_WO |
  39641                           SOC_REG_FLAG_INTERRUPT,
  39642         0,
  39643         2,
  39644         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM83208_A0r_fields,
  39645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39646         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39647         -1,
  39648         -1,
  39649     },
  39650 #endif /* chips */
  39651 
  39652 #if defined(BCM_88375_A0)
  39653     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88375_A0r */
  39654         soc_block_list[23],
  39655         soc_genreg,
  39656         1,
  39657         0,
  39658         0x201,
  39659         SOC_REG_FLAG_WO |
  39660                           SOC_REG_FLAG_INTERRUPT,
  39661         0,
  39662         2,
  39663         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88375_A0r_fields,
  39664         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39665         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39666         -1,
  39667         -1,
  39668     },
  39669 #endif /* chips */
  39670 
  39671 #if defined(BCM_88375_B0)
  39672     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88375_B0r */
  39673         soc_block_list[23],
  39674         soc_genreg,
  39675         1,
  39676         0,
  39677         0x201,
  39678         SOC_REG_FLAG_WO |
  39679                           SOC_REG_FLAG_INTERRUPT,
  39680         0,
  39681         2,
  39682         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88375_B0r_fields,
  39683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39684         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39685         -1,
  39686         -1,
  39687     },
  39688 #endif /* chips */
  39689 
  39690 #if defined(BCM_88470_A0)
  39691     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88470_A0r */
  39692         soc_block_list[23],
  39693         soc_genreg,
  39694         1,
  39695         0,
  39696         0x201,
  39697         SOC_REG_FLAG_WO |
  39698                           SOC_REG_FLAG_INTERRUPT |
  39699                           SOC_REG_FLAG_SIGNAL,
  39700         0,
  39701         2,
  39702         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88470_A0r_fields,
  39703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39704         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39705         -1,
  39706         -1,
  39707     },
  39708 #endif /* chips */
  39709 
  39710 #if defined(BCM_88470_B0)
  39711     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88470_B0r */
  39712         soc_block_list[23],
  39713         soc_genreg,
  39714         1,
  39715         0,
  39716         0x201,
  39717         SOC_REG_FLAG_WO |
  39718                           SOC_REG_FLAG_INTERRUPT |
  39719                           SOC_REG_FLAG_SIGNAL,
  39720         0,
  39721         2,
  39722         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88470_B0r_fields,
  39723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39724         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39725         -1,
  39726         -1,
  39727     },
  39728 #endif /* chips */
  39729 
  39730 #if defined(BCM_88675_B0)
  39731     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88675_B0r */
  39732         soc_block_list[23],
  39733         soc_genreg,
  39734         1,
  39735         0,
  39736         0x201,
  39737         SOC_REG_FLAG_WO |
  39738                           SOC_REG_FLAG_INTERRUPT,
  39739         0,
  39740         2,
  39741         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88675_B0r_fields,
  39742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39743         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39744         -1,
  39745         -1,
  39746     },
  39747 #endif /* chips */
  39748 
  39749 #if defined(BCM_88680_A0)
  39750     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88680_A0r */
  39751         soc_block_list[23],
  39752         soc_genreg,
  39753         1,
  39754         0,
  39755         0x201,
  39756         SOC_REG_FLAG_WO |
  39757                           SOC_REG_FLAG_INTERRUPT,
  39758         0,
  39759         2,
  39760         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88680_A0r_fields,
  39761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39762         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39763         -1,
  39764         -1,
  39765     },
  39766 #endif /* chips */
  39767 
  39768 #if defined(BCM_88690_A0)
  39769     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88690_A0r */
  39770         soc_block_list[23],
  39771         soc_genreg,
  39772         1,
  39773         0,
  39774         0x100,
  39775         SOC_REG_FLAG_WO |
  39776                           SOC_REG_FLAG_INTERRUPT |
  39777                           SOC_REG_FLAG_SIGNAL,
  39778         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  39779         2,
  39780         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88690_A0r_fields,
  39781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39782         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39783         -1,
  39784         -1,
  39785     },
  39786 #endif /* chips */
  39787 
  39788 #if defined(BCM_88690_B0)
  39789     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88690_B0r */
  39790         soc_block_list[23],
  39791         soc_genreg,
  39792         1,
  39793         0,
  39794         0x100,
  39795         SOC_REG_FLAG_WO |
  39796                           SOC_REG_FLAG_INTERRUPT |
  39797                           SOC_REG_FLAG_SIGNAL,
  39798         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  39799         2,
  39800         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88690_B0r_fields,
  39801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39802         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39803         -1,
  39804         -1,
  39805     },
  39806 #endif /* chips */
  39807 
  39808 #if defined(BCM_88790_A0)
  39809     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88790_A0r */
  39810         soc_block_list[23],
  39811         soc_genreg,
  39812         1,
  39813         0,
  39814         0x100,
  39815         SOC_REG_FLAG_WO |
  39816                           SOC_REG_FLAG_INTERRUPT |
  39817                           SOC_REG_FLAG_SIGNAL,
  39818         0,
  39819         2,
  39820         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_BCM88790_A0r_fields,
  39821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39822         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39823         -1,
  39824         -1,
  39825     },
  39826 #endif /* chips */
  39827 
  39828 #if defined(BCM_88675_A0)
  39829     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TESTr */
  39830         soc_block_list[23],
  39831         soc_genreg,
  39832         1,
  39833         0,
  39834         0x221,
  39835         SOC_REG_FLAG_WO,
  39836         0,
  39837         1,
  39838         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TESTr_fields,
  39839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39840         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39841         -1,
  39842         -1,
  39843     },
  39844 #endif /* chips */
  39845 
  39846 #if defined(BCM_83208_A0)
  39847     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM83208_A0r */
  39848         soc_block_list[23],
  39849         soc_genreg,
  39850         1,
  39851         0,
  39852         0x221,
  39853         SOC_REG_FLAG_WO,
  39854         0,
  39855         1,
  39856         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM83208_A0r_fields,
  39857         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39859         -1,
  39860         -1,
  39861     },
  39862 #endif /* chips */
  39863 
  39864 #if defined(BCM_88375_A0)
  39865     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88375_A0r */
  39866         soc_block_list[23],
  39867         soc_genreg,
  39868         1,
  39869         0,
  39870         0x221,
  39871         SOC_REG_FLAG_WO,
  39872         0,
  39873         1,
  39874         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88375_A0r_fields,
  39875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39877         -1,
  39878         -1,
  39879     },
  39880 #endif /* chips */
  39881 
  39882 #if defined(BCM_88375_B0)
  39883     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88375_B0r */
  39884         soc_block_list[23],
  39885         soc_genreg,
  39886         1,
  39887         0,
  39888         0x221,
  39889         SOC_REG_FLAG_WO,
  39890         0,
  39891         1,
  39892         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88375_B0r_fields,
  39893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39894         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39895         -1,
  39896         -1,
  39897     },
  39898 #endif /* chips */
  39899 
  39900 #if defined(BCM_88470_A0)
  39901     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88470_A0r */
  39902         soc_block_list[23],
  39903         soc_genreg,
  39904         1,
  39905         0,
  39906         0x221,
  39907         SOC_REG_FLAG_WO,
  39908         0,
  39909         1,
  39910         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88470_A0r_fields,
  39911         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39912         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39913         -1,
  39914         -1,
  39915     },
  39916 #endif /* chips */
  39917 
  39918 #if defined(BCM_88470_B0)
  39919     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88470_B0r */
  39920         soc_block_list[23],
  39921         soc_genreg,
  39922         1,
  39923         0,
  39924         0x221,
  39925         SOC_REG_FLAG_WO,
  39926         0,
  39927         1,
  39928         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88470_B0r_fields,
  39929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39930         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39931         -1,
  39932         -1,
  39933     },
  39934 #endif /* chips */
  39935 
  39936 #if defined(BCM_88675_B0)
  39937     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88675_B0r */
  39938         soc_block_list[23],
  39939         soc_genreg,
  39940         1,
  39941         0,
  39942         0x221,
  39943         SOC_REG_FLAG_WO,
  39944         0,
  39945         1,
  39946         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88675_B0r_fields,
  39947         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39948         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39949         -1,
  39950         -1,
  39951     },
  39952 #endif /* chips */
  39953 
  39954 #if defined(BCM_88680_A0)
  39955     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88680_A0r */
  39956         soc_block_list[23],
  39957         soc_genreg,
  39958         1,
  39959         0,
  39960         0x221,
  39961         SOC_REG_FLAG_WO,
  39962         0,
  39963         1,
  39964         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88680_A0r_fields,
  39965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39966         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  39967         -1,
  39968         -1,
  39969     },
  39970 #endif /* chips */
  39971 
  39972 #if defined(BCM_88690_A0)
  39973     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88690_A0r */
  39974         soc_block_list[23],
  39975         soc_genreg,
  39976         1,
  39977         0,
  39978         0x102,
  39979         SOC_REG_FLAG_WO,
  39980         0,
  39981         1,
  39982         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88690_A0r_fields,
  39983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  39984         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  39985         -1,
  39986         -1,
  39987     },
  39988 #endif /* chips */
  39989 
  39990 #if defined(BCM_88690_B0)
  39991     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88690_B0r */
  39992         soc_block_list[23],
  39993         soc_genreg,
  39994         1,
  39995         0,
  39996         0x102,
  39997         SOC_REG_FLAG_WO,
  39998         0,
  39999         1,
  40000         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88690_B0r_fields,
  40001         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40002         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40003         -1,
  40004         -1,
  40005     },
  40006 #endif /* chips */
  40007 
  40008 #if defined(BCM_88790_A0)
  40009     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88790_A0r */
  40010         soc_block_list[23],
  40011         soc_genreg,
  40012         1,
  40013         0,
  40014         0x102,
  40015         SOC_REG_FLAG_WO,
  40016         0,
  40017         1,
  40018         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88790_A0r_fields,
  40019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40020         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40021         -1,
  40022         -1,
  40023     },
  40024 #endif /* chips */
  40025 
  40026 #if defined(BCM_83208_A0)
  40027     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM83208_A0r */
  40028         soc_block_list[23],
  40029         soc_genreg,
  40030         1,
  40031         0,
  40032         0x202,
  40033         SOC_REG_FLAG_WO |
  40034                           SOC_REG_FLAG_INTERRUPT,
  40035         0,
  40036         2,
  40037         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM83208_A0r_fields,
  40038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40039         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40040         -1,
  40041         -1,
  40042     },
  40043 #endif /* chips */
  40044 
  40045 #if defined(BCM_88375_A0)
  40046     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88375_A0r */
  40047         soc_block_list[23],
  40048         soc_genreg,
  40049         1,
  40050         0,
  40051         0x202,
  40052         SOC_REG_FLAG_WO |
  40053                           SOC_REG_FLAG_INTERRUPT,
  40054         0,
  40055         2,
  40056         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88375_A0r_fields,
  40057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40058         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40059         -1,
  40060         -1,
  40061     },
  40062 #endif /* chips */
  40063 
  40064 #if defined(BCM_88375_B0)
  40065     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88375_B0r */
  40066         soc_block_list[23],
  40067         soc_genreg,
  40068         1,
  40069         0,
  40070         0x202,
  40071         SOC_REG_FLAG_WO |
  40072                           SOC_REG_FLAG_INTERRUPT,
  40073         0,
  40074         2,
  40075         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88375_B0r_fields,
  40076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40077         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40078         -1,
  40079         -1,
  40080     },
  40081 #endif /* chips */
  40082 
  40083 #if defined(BCM_88470_A0)
  40084     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88470_A0r */
  40085         soc_block_list[23],
  40086         soc_genreg,
  40087         1,
  40088         0,
  40089         0x202,
  40090         SOC_REG_FLAG_WO |
  40091                           SOC_REG_FLAG_INTERRUPT |
  40092                           SOC_REG_FLAG_SIGNAL,
  40093         0,
  40094         2,
  40095         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88470_A0r_fields,
  40096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40097         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40098         -1,
  40099         -1,
  40100     },
  40101 #endif /* chips */
  40102 
  40103 #if defined(BCM_88470_B0)
  40104     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88470_B0r */
  40105         soc_block_list[23],
  40106         soc_genreg,
  40107         1,
  40108         0,
  40109         0x202,
  40110         SOC_REG_FLAG_WO |
  40111                           SOC_REG_FLAG_INTERRUPT |
  40112                           SOC_REG_FLAG_SIGNAL,
  40113         0,
  40114         2,
  40115         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88470_B0r_fields,
  40116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40117         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40118         -1,
  40119         -1,
  40120     },
  40121 #endif /* chips */
  40122 
  40123 #if defined(BCM_88675_B0)
  40124     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88675_B0r */
  40125         soc_block_list[23],
  40126         soc_genreg,
  40127         1,
  40128         0,
  40129         0x202,
  40130         SOC_REG_FLAG_WO |
  40131                           SOC_REG_FLAG_INTERRUPT,
  40132         0,
  40133         2,
  40134         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88675_B0r_fields,
  40135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40136         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40137         -1,
  40138         -1,
  40139     },
  40140 #endif /* chips */
  40141 
  40142 #if defined(BCM_88680_A0)
  40143     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88680_A0r */
  40144         soc_block_list[23],
  40145         soc_genreg,
  40146         1,
  40147         0,
  40148         0x202,
  40149         SOC_REG_FLAG_WO |
  40150                           SOC_REG_FLAG_INTERRUPT,
  40151         0,
  40152         2,
  40153         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88680_A0r_fields,
  40154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40155         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40156         -1,
  40157         -1,
  40158     },
  40159 #endif /* chips */
  40160 
  40161 #if defined(BCM_88690_A0)
  40162     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88690_A0r */
  40163         soc_block_list[23],
  40164         soc_genreg,
  40165         1,
  40166         0,
  40167         0x103,
  40168         SOC_REG_FLAG_WO |
  40169                           SOC_REG_FLAG_INTERRUPT |
  40170                           SOC_REG_FLAG_SIGNAL,
  40171         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40172         2,
  40173         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88690_A0r_fields,
  40174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40175         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40176         -1,
  40177         -1,
  40178     },
  40179 #endif /* chips */
  40180 
  40181 #if defined(BCM_88690_B0)
  40182     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88690_B0r */
  40183         soc_block_list[23],
  40184         soc_genreg,
  40185         1,
  40186         0,
  40187         0x103,
  40188         SOC_REG_FLAG_WO |
  40189                           SOC_REG_FLAG_INTERRUPT |
  40190                           SOC_REG_FLAG_SIGNAL,
  40191         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40192         2,
  40193         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88690_B0r_fields,
  40194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40195         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40196         -1,
  40197         -1,
  40198     },
  40199 #endif /* chips */
  40200 
  40201 #if defined(BCM_88790_A0)
  40202     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88790_A0r */
  40203         soc_block_list[23],
  40204         soc_genreg,
  40205         1,
  40206         0,
  40207         0x103,
  40208         SOC_REG_FLAG_WO |
  40209                           SOC_REG_FLAG_INTERRUPT |
  40210                           SOC_REG_FLAG_SIGNAL,
  40211         0,
  40212         2,
  40213         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_BCM88790_A0r_fields,
  40214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40215         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40216         -1,
  40217         -1,
  40218     },
  40219 #endif /* chips */
  40220 
  40221 #if defined(BCM_88675_A0)
  40222     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TESTr */
  40223         soc_block_list[23],
  40224         soc_genreg,
  40225         1,
  40226         0,
  40227         0x222,
  40228         SOC_REG_FLAG_WO,
  40229         0,
  40230         1,
  40231         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TESTr_fields,
  40232         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40233         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40234         -1,
  40235         -1,
  40236     },
  40237 #endif /* chips */
  40238 
  40239 #if defined(BCM_83208_A0)
  40240     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM83208_A0r */
  40241         soc_block_list[23],
  40242         soc_genreg,
  40243         1,
  40244         0,
  40245         0x222,
  40246         SOC_REG_FLAG_WO,
  40247         0,
  40248         1,
  40249         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM83208_A0r_fields,
  40250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40251         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40252         -1,
  40253         -1,
  40254     },
  40255 #endif /* chips */
  40256 
  40257 #if defined(BCM_88375_A0)
  40258     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88375_A0r */
  40259         soc_block_list[23],
  40260         soc_genreg,
  40261         1,
  40262         0,
  40263         0x222,
  40264         SOC_REG_FLAG_WO,
  40265         0,
  40266         1,
  40267         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88375_A0r_fields,
  40268         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40269         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40270         -1,
  40271         -1,
  40272     },
  40273 #endif /* chips */
  40274 
  40275 #if defined(BCM_88375_B0)
  40276     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88375_B0r */
  40277         soc_block_list[23],
  40278         soc_genreg,
  40279         1,
  40280         0,
  40281         0x222,
  40282         SOC_REG_FLAG_WO,
  40283         0,
  40284         1,
  40285         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88375_B0r_fields,
  40286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40287         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40288         -1,
  40289         -1,
  40290     },
  40291 #endif /* chips */
  40292 
  40293 #if defined(BCM_88470_A0)
  40294     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88470_A0r */
  40295         soc_block_list[23],
  40296         soc_genreg,
  40297         1,
  40298         0,
  40299         0x222,
  40300         SOC_REG_FLAG_WO,
  40301         0,
  40302         1,
  40303         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88470_A0r_fields,
  40304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40305         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40306         -1,
  40307         -1,
  40308     },
  40309 #endif /* chips */
  40310 
  40311 #if defined(BCM_88470_B0)
  40312     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88470_B0r */
  40313         soc_block_list[23],
  40314         soc_genreg,
  40315         1,
  40316         0,
  40317         0x222,
  40318         SOC_REG_FLAG_WO,
  40319         0,
  40320         1,
  40321         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88470_B0r_fields,
  40322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40323         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40324         -1,
  40325         -1,
  40326     },
  40327 #endif /* chips */
  40328 
  40329 #if defined(BCM_88675_B0)
  40330     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88675_B0r */
  40331         soc_block_list[23],
  40332         soc_genreg,
  40333         1,
  40334         0,
  40335         0x222,
  40336         SOC_REG_FLAG_WO,
  40337         0,
  40338         1,
  40339         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88675_B0r_fields,
  40340         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40341         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40342         -1,
  40343         -1,
  40344     },
  40345 #endif /* chips */
  40346 
  40347 #if defined(BCM_88680_A0)
  40348     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88680_A0r */
  40349         soc_block_list[23],
  40350         soc_genreg,
  40351         1,
  40352         0,
  40353         0x222,
  40354         SOC_REG_FLAG_WO,
  40355         0,
  40356         1,
  40357         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88680_A0r_fields,
  40358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40360         -1,
  40361         -1,
  40362     },
  40363 #endif /* chips */
  40364 
  40365 #if defined(BCM_88690_A0)
  40366     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88690_A0r */
  40367         soc_block_list[23],
  40368         soc_genreg,
  40369         1,
  40370         0,
  40371         0x105,
  40372         SOC_REG_FLAG_WO,
  40373         0,
  40374         1,
  40375         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88690_A0r_fields,
  40376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40377         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40378         -1,
  40379         -1,
  40380     },
  40381 #endif /* chips */
  40382 
  40383 #if defined(BCM_88690_B0)
  40384     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88690_B0r */
  40385         soc_block_list[23],
  40386         soc_genreg,
  40387         1,
  40388         0,
  40389         0x105,
  40390         SOC_REG_FLAG_WO,
  40391         0,
  40392         1,
  40393         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88690_B0r_fields,
  40394         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40395         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40396         -1,
  40397         -1,
  40398     },
  40399 #endif /* chips */
  40400 
  40401 #if defined(BCM_88790_A0)
  40402     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88790_A0r */
  40403         soc_block_list[23],
  40404         soc_genreg,
  40405         1,
  40406         0,
  40407         0x105,
  40408         SOC_REG_FLAG_WO,
  40409         0,
  40410         1,
  40411         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88790_A0r_fields,
  40412         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40413         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40414         -1,
  40415         -1,
  40416     },
  40417 #endif /* chips */
  40418 
  40419 #if defined(BCM_83208_A0)
  40420     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM83208_A0r */
  40421         soc_block_list[23],
  40422         soc_genreg,
  40423         1,
  40424         0,
  40425         0x203,
  40426         SOC_REG_FLAG_WO |
  40427                           SOC_REG_FLAG_INTERRUPT,
  40428         0,
  40429         2,
  40430         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM83208_A0r_fields,
  40431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40432         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40433         -1,
  40434         -1,
  40435     },
  40436 #endif /* chips */
  40437 
  40438 #if defined(BCM_88375_A0)
  40439     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88375_A0r */
  40440         soc_block_list[23],
  40441         soc_genreg,
  40442         1,
  40443         0,
  40444         0x203,
  40445         SOC_REG_FLAG_WO |
  40446                           SOC_REG_FLAG_INTERRUPT,
  40447         0,
  40448         2,
  40449         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88375_A0r_fields,
  40450         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40451         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40452         -1,
  40453         -1,
  40454     },
  40455 #endif /* chips */
  40456 
  40457 #if defined(BCM_88375_B0)
  40458     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88375_B0r */
  40459         soc_block_list[23],
  40460         soc_genreg,
  40461         1,
  40462         0,
  40463         0x203,
  40464         SOC_REG_FLAG_WO |
  40465                           SOC_REG_FLAG_INTERRUPT,
  40466         0,
  40467         2,
  40468         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88375_B0r_fields,
  40469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40470         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40471         -1,
  40472         -1,
  40473     },
  40474 #endif /* chips */
  40475 
  40476 #if defined(BCM_88470_A0)
  40477     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88470_A0r */
  40478         soc_block_list[23],
  40479         soc_genreg,
  40480         1,
  40481         0,
  40482         0x203,
  40483         SOC_REG_FLAG_WO |
  40484                           SOC_REG_FLAG_INTERRUPT |
  40485                           SOC_REG_FLAG_SIGNAL,
  40486         0,
  40487         2,
  40488         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88470_A0r_fields,
  40489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40490         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40491         -1,
  40492         -1,
  40493     },
  40494 #endif /* chips */
  40495 
  40496 #if defined(BCM_88470_B0)
  40497     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88470_B0r */
  40498         soc_block_list[23],
  40499         soc_genreg,
  40500         1,
  40501         0,
  40502         0x203,
  40503         SOC_REG_FLAG_WO |
  40504                           SOC_REG_FLAG_INTERRUPT |
  40505                           SOC_REG_FLAG_SIGNAL,
  40506         0,
  40507         2,
  40508         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88470_B0r_fields,
  40509         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40510         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40511         -1,
  40512         -1,
  40513     },
  40514 #endif /* chips */
  40515 
  40516 #if defined(BCM_88675_B0)
  40517     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88675_B0r */
  40518         soc_block_list[23],
  40519         soc_genreg,
  40520         1,
  40521         0,
  40522         0x203,
  40523         SOC_REG_FLAG_WO |
  40524                           SOC_REG_FLAG_INTERRUPT,
  40525         0,
  40526         2,
  40527         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88675_B0r_fields,
  40528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40529         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40530         -1,
  40531         -1,
  40532     },
  40533 #endif /* chips */
  40534 
  40535 #if defined(BCM_88680_A0)
  40536     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88680_A0r */
  40537         soc_block_list[23],
  40538         soc_genreg,
  40539         1,
  40540         0,
  40541         0x203,
  40542         SOC_REG_FLAG_WO |
  40543                           SOC_REG_FLAG_INTERRUPT,
  40544         0,
  40545         2,
  40546         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88680_A0r_fields,
  40547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40548         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40549         -1,
  40550         -1,
  40551     },
  40552 #endif /* chips */
  40553 
  40554 #if defined(BCM_88690_A0)
  40555     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88690_A0r */
  40556         soc_block_list[23],
  40557         soc_genreg,
  40558         1,
  40559         0,
  40560         0x106,
  40561         SOC_REG_FLAG_WO |
  40562                           SOC_REG_FLAG_INTERRUPT |
  40563                           SOC_REG_FLAG_SIGNAL,
  40564         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40565         2,
  40566         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88690_A0r_fields,
  40567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40568         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40569         -1,
  40570         -1,
  40571     },
  40572 #endif /* chips */
  40573 
  40574 #if defined(BCM_88690_B0)
  40575     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88690_B0r */
  40576         soc_block_list[23],
  40577         soc_genreg,
  40578         1,
  40579         0,
  40580         0x106,
  40581         SOC_REG_FLAG_WO |
  40582                           SOC_REG_FLAG_INTERRUPT |
  40583                           SOC_REG_FLAG_SIGNAL,
  40584         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40585         2,
  40586         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88690_B0r_fields,
  40587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40588         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40589         -1,
  40590         -1,
  40591     },
  40592 #endif /* chips */
  40593 
  40594 #if defined(BCM_88790_A0)
  40595     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88790_A0r */
  40596         soc_block_list[23],
  40597         soc_genreg,
  40598         1,
  40599         0,
  40600         0x106,
  40601         SOC_REG_FLAG_WO |
  40602                           SOC_REG_FLAG_INTERRUPT |
  40603                           SOC_REG_FLAG_SIGNAL,
  40604         0,
  40605         2,
  40606         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_BCM88790_A0r_fields,
  40607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40608         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40609         -1,
  40610         -1,
  40611     },
  40612 #endif /* chips */
  40613 
  40614 #if defined(BCM_88675_A0)
  40615     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TESTr */
  40616         soc_block_list[23],
  40617         soc_genreg,
  40618         1,
  40619         0,
  40620         0x223,
  40621         SOC_REG_FLAG_WO,
  40622         0,
  40623         1,
  40624         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TESTr_fields,
  40625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40626         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40627         -1,
  40628         -1,
  40629     },
  40630 #endif /* chips */
  40631 
  40632 #if defined(BCM_83208_A0)
  40633     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM83208_A0r */
  40634         soc_block_list[23],
  40635         soc_genreg,
  40636         1,
  40637         0,
  40638         0x223,
  40639         SOC_REG_FLAG_WO,
  40640         0,
  40641         1,
  40642         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM83208_A0r_fields,
  40643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40644         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40645         -1,
  40646         -1,
  40647     },
  40648 #endif /* chips */
  40649 
  40650 #if defined(BCM_88375_A0)
  40651     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88375_A0r */
  40652         soc_block_list[23],
  40653         soc_genreg,
  40654         1,
  40655         0,
  40656         0x223,
  40657         SOC_REG_FLAG_WO,
  40658         0,
  40659         1,
  40660         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88375_A0r_fields,
  40661         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40663         -1,
  40664         -1,
  40665     },
  40666 #endif /* chips */
  40667 
  40668 #if defined(BCM_88375_B0)
  40669     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88375_B0r */
  40670         soc_block_list[23],
  40671         soc_genreg,
  40672         1,
  40673         0,
  40674         0x223,
  40675         SOC_REG_FLAG_WO,
  40676         0,
  40677         1,
  40678         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88375_B0r_fields,
  40679         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40680         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40681         -1,
  40682         -1,
  40683     },
  40684 #endif /* chips */
  40685 
  40686 #if defined(BCM_88470_A0)
  40687     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88470_A0r */
  40688         soc_block_list[23],
  40689         soc_genreg,
  40690         1,
  40691         0,
  40692         0x223,
  40693         SOC_REG_FLAG_WO,
  40694         0,
  40695         1,
  40696         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88470_A0r_fields,
  40697         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40698         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40699         -1,
  40700         -1,
  40701     },
  40702 #endif /* chips */
  40703 
  40704 #if defined(BCM_88470_B0)
  40705     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88470_B0r */
  40706         soc_block_list[23],
  40707         soc_genreg,
  40708         1,
  40709         0,
  40710         0x223,
  40711         SOC_REG_FLAG_WO,
  40712         0,
  40713         1,
  40714         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88470_B0r_fields,
  40715         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40716         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40717         -1,
  40718         -1,
  40719     },
  40720 #endif /* chips */
  40721 
  40722 #if defined(BCM_88675_B0)
  40723     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88675_B0r */
  40724         soc_block_list[23],
  40725         soc_genreg,
  40726         1,
  40727         0,
  40728         0x223,
  40729         SOC_REG_FLAG_WO,
  40730         0,
  40731         1,
  40732         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88675_B0r_fields,
  40733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40734         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40735         -1,
  40736         -1,
  40737     },
  40738 #endif /* chips */
  40739 
  40740 #if defined(BCM_88680_A0)
  40741     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88680_A0r */
  40742         soc_block_list[23],
  40743         soc_genreg,
  40744         1,
  40745         0,
  40746         0x223,
  40747         SOC_REG_FLAG_WO,
  40748         0,
  40749         1,
  40750         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88680_A0r_fields,
  40751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40752         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  40753         -1,
  40754         -1,
  40755     },
  40756 #endif /* chips */
  40757 
  40758 #if defined(BCM_88690_A0)
  40759     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88690_A0r */
  40760         soc_block_list[23],
  40761         soc_genreg,
  40762         1,
  40763         0,
  40764         0x108,
  40765         SOC_REG_FLAG_WO,
  40766         0,
  40767         1,
  40768         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88690_A0r_fields,
  40769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40770         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40771         -1,
  40772         -1,
  40773     },
  40774 #endif /* chips */
  40775 
  40776 #if defined(BCM_88690_B0)
  40777     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88690_B0r */
  40778         soc_block_list[23],
  40779         soc_genreg,
  40780         1,
  40781         0,
  40782         0x108,
  40783         SOC_REG_FLAG_WO,
  40784         0,
  40785         1,
  40786         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88690_B0r_fields,
  40787         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40788         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40789         -1,
  40790         -1,
  40791     },
  40792 #endif /* chips */
  40793 
  40794 #if defined(BCM_88790_A0)
  40795     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88790_A0r */
  40796         soc_block_list[23],
  40797         soc_genreg,
  40798         1,
  40799         0,
  40800         0x108,
  40801         SOC_REG_FLAG_WO,
  40802         0,
  40803         1,
  40804         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88790_A0r_fields,
  40805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40806         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40807         -1,
  40808         -1,
  40809     },
  40810 #endif /* chips */
  40811 
  40812 #if defined(BCM_83208_A0)
  40813     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM83208_A0r */
  40814         soc_block_list[23],
  40815         soc_genreg,
  40816         1,
  40817         0,
  40818         0x204,
  40819         SOC_REG_FLAG_WO |
  40820                           SOC_REG_FLAG_INTERRUPT,
  40821         0,
  40822         2,
  40823         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM83208_A0r_fields,
  40824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40825         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40826         -1,
  40827         -1,
  40828     },
  40829 #endif /* chips */
  40830 
  40831 #if defined(BCM_88375_A0)
  40832     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88375_A0r */
  40833         soc_block_list[23],
  40834         soc_genreg,
  40835         1,
  40836         0,
  40837         0x204,
  40838         SOC_REG_FLAG_WO |
  40839                           SOC_REG_FLAG_INTERRUPT,
  40840         0,
  40841         2,
  40842         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88375_A0r_fields,
  40843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40844         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40845         -1,
  40846         -1,
  40847     },
  40848 #endif /* chips */
  40849 
  40850 #if defined(BCM_88375_B0)
  40851     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88375_B0r */
  40852         soc_block_list[23],
  40853         soc_genreg,
  40854         1,
  40855         0,
  40856         0x204,
  40857         SOC_REG_FLAG_WO |
  40858                           SOC_REG_FLAG_INTERRUPT,
  40859         0,
  40860         2,
  40861         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88375_B0r_fields,
  40862         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40863         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40864         -1,
  40865         -1,
  40866     },
  40867 #endif /* chips */
  40868 
  40869 #if defined(BCM_88470_A0)
  40870     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88470_A0r */
  40871         soc_block_list[23],
  40872         soc_genreg,
  40873         1,
  40874         0,
  40875         0x204,
  40876         SOC_REG_FLAG_WO |
  40877                           SOC_REG_FLAG_INTERRUPT |
  40878                           SOC_REG_FLAG_SIGNAL,
  40879         0,
  40880         2,
  40881         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88470_A0r_fields,
  40882         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40883         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40884         -1,
  40885         -1,
  40886     },
  40887 #endif /* chips */
  40888 
  40889 #if defined(BCM_88470_B0)
  40890     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88470_B0r */
  40891         soc_block_list[23],
  40892         soc_genreg,
  40893         1,
  40894         0,
  40895         0x204,
  40896         SOC_REG_FLAG_WO |
  40897                           SOC_REG_FLAG_INTERRUPT |
  40898                           SOC_REG_FLAG_SIGNAL,
  40899         0,
  40900         2,
  40901         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88470_B0r_fields,
  40902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40903         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40904         -1,
  40905         -1,
  40906     },
  40907 #endif /* chips */
  40908 
  40909 #if defined(BCM_88675_B0)
  40910     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88675_B0r */
  40911         soc_block_list[23],
  40912         soc_genreg,
  40913         1,
  40914         0,
  40915         0x204,
  40916         SOC_REG_FLAG_WO |
  40917                           SOC_REG_FLAG_INTERRUPT,
  40918         0,
  40919         2,
  40920         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88675_B0r_fields,
  40921         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40922         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40923         -1,
  40924         -1,
  40925     },
  40926 #endif /* chips */
  40927 
  40928 #if defined(BCM_88680_A0)
  40929     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88680_A0r */
  40930         soc_block_list[23],
  40931         soc_genreg,
  40932         1,
  40933         0,
  40934         0x204,
  40935         SOC_REG_FLAG_WO |
  40936                           SOC_REG_FLAG_INTERRUPT,
  40937         0,
  40938         2,
  40939         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88680_A0r_fields,
  40940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40941         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40942         -1,
  40943         -1,
  40944     },
  40945 #endif /* chips */
  40946 
  40947 #if defined(BCM_88690_A0)
  40948     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88690_A0r */
  40949         soc_block_list[23],
  40950         soc_genreg,
  40951         1,
  40952         0,
  40953         0x109,
  40954         SOC_REG_FLAG_WO |
  40955                           SOC_REG_FLAG_INTERRUPT |
  40956                           SOC_REG_FLAG_SIGNAL,
  40957         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40958         2,
  40959         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88690_A0r_fields,
  40960         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40961         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40962         -1,
  40963         -1,
  40964     },
  40965 #endif /* chips */
  40966 
  40967 #if defined(BCM_88690_B0)
  40968     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88690_B0r */
  40969         soc_block_list[23],
  40970         soc_genreg,
  40971         1,
  40972         0,
  40973         0x109,
  40974         SOC_REG_FLAG_WO |
  40975                           SOC_REG_FLAG_INTERRUPT |
  40976                           SOC_REG_FLAG_SIGNAL,
  40977         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  40978         2,
  40979         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88690_B0r_fields,
  40980         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  40981         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  40982         -1,
  40983         -1,
  40984     },
  40985 #endif /* chips */
  40986 
  40987 #if defined(BCM_88790_A0)
  40988     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88790_A0r */
  40989         soc_block_list[23],
  40990         soc_genreg,
  40991         1,
  40992         0,
  40993         0x109,
  40994         SOC_REG_FLAG_WO |
  40995                           SOC_REG_FLAG_INTERRUPT |
  40996                           SOC_REG_FLAG_SIGNAL,
  40997         0,
  40998         2,
  40999         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_BCM88790_A0r_fields,
  41000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41001         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41002         -1,
  41003         -1,
  41004     },
  41005 #endif /* chips */
  41006 
  41007 #if defined(BCM_88675_A0)
  41008     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TESTr */
  41009         soc_block_list[23],
  41010         soc_genreg,
  41011         1,
  41012         0,
  41013         0x224,
  41014         SOC_REG_FLAG_WO,
  41015         0,
  41016         1,
  41017         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TESTr_fields,
  41018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41019         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41020         -1,
  41021         -1,
  41022     },
  41023 #endif /* chips */
  41024 
  41025 #if defined(BCM_83208_A0)
  41026     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM83208_A0r */
  41027         soc_block_list[23],
  41028         soc_genreg,
  41029         1,
  41030         0,
  41031         0x224,
  41032         SOC_REG_FLAG_WO,
  41033         0,
  41034         1,
  41035         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM83208_A0r_fields,
  41036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41037         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41038         -1,
  41039         -1,
  41040     },
  41041 #endif /* chips */
  41042 
  41043 #if defined(BCM_88375_A0)
  41044     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88375_A0r */
  41045         soc_block_list[23],
  41046         soc_genreg,
  41047         1,
  41048         0,
  41049         0x224,
  41050         SOC_REG_FLAG_WO,
  41051         0,
  41052         1,
  41053         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88375_A0r_fields,
  41054         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41055         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41056         -1,
  41057         -1,
  41058     },
  41059 #endif /* chips */
  41060 
  41061 #if defined(BCM_88375_B0)
  41062     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88375_B0r */
  41063         soc_block_list[23],
  41064         soc_genreg,
  41065         1,
  41066         0,
  41067         0x224,
  41068         SOC_REG_FLAG_WO,
  41069         0,
  41070         1,
  41071         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88375_B0r_fields,
  41072         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41073         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41074         -1,
  41075         -1,
  41076     },
  41077 #endif /* chips */
  41078 
  41079 #if defined(BCM_88470_A0)
  41080     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88470_A0r */
  41081         soc_block_list[23],
  41082         soc_genreg,
  41083         1,
  41084         0,
  41085         0x224,
  41086         SOC_REG_FLAG_WO,
  41087         0,
  41088         1,
  41089         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88470_A0r_fields,
  41090         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41091         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41092         -1,
  41093         -1,
  41094     },
  41095 #endif /* chips */
  41096 
  41097 #if defined(BCM_88470_B0)
  41098     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88470_B0r */
  41099         soc_block_list[23],
  41100         soc_genreg,
  41101         1,
  41102         0,
  41103         0x224,
  41104         SOC_REG_FLAG_WO,
  41105         0,
  41106         1,
  41107         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88470_B0r_fields,
  41108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41109         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41110         -1,
  41111         -1,
  41112     },
  41113 #endif /* chips */
  41114 
  41115 #if defined(BCM_88675_B0)
  41116     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88675_B0r */
  41117         soc_block_list[23],
  41118         soc_genreg,
  41119         1,
  41120         0,
  41121         0x224,
  41122         SOC_REG_FLAG_WO,
  41123         0,
  41124         1,
  41125         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88675_B0r_fields,
  41126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41127         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41128         -1,
  41129         -1,
  41130     },
  41131 #endif /* chips */
  41132 
  41133 #if defined(BCM_88680_A0)
  41134     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88680_A0r */
  41135         soc_block_list[23],
  41136         soc_genreg,
  41137         1,
  41138         0,
  41139         0x224,
  41140         SOC_REG_FLAG_WO,
  41141         0,
  41142         1,
  41143         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88680_A0r_fields,
  41144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41145         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41146         -1,
  41147         -1,
  41148     },
  41149 #endif /* chips */
  41150 
  41151 #if defined(BCM_88690_A0)
  41152     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88690_A0r */
  41153         soc_block_list[23],
  41154         soc_genreg,
  41155         1,
  41156         0,
  41157         0x10b,
  41158         SOC_REG_FLAG_WO,
  41159         0,
  41160         1,
  41161         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88690_A0r_fields,
  41162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41163         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41164         -1,
  41165         -1,
  41166     },
  41167 #endif /* chips */
  41168 
  41169 #if defined(BCM_88690_B0)
  41170     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88690_B0r */
  41171         soc_block_list[23],
  41172         soc_genreg,
  41173         1,
  41174         0,
  41175         0x10b,
  41176         SOC_REG_FLAG_WO,
  41177         0,
  41178         1,
  41179         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88690_B0r_fields,
  41180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41181         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41182         -1,
  41183         -1,
  41184     },
  41185 #endif /* chips */
  41186 
  41187 #if defined(BCM_88790_A0)
  41188     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88790_A0r */
  41189         soc_block_list[23],
  41190         soc_genreg,
  41191         1,
  41192         0,
  41193         0x10b,
  41194         SOC_REG_FLAG_WO,
  41195         0,
  41196         1,
  41197         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88790_A0r_fields,
  41198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41199         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41200         -1,
  41201         -1,
  41202     },
  41203 #endif /* chips */
  41204 
  41205 #if defined(BCM_83208_A0)
  41206     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM83208_A0r */
  41207         soc_block_list[23],
  41208         soc_genreg,
  41209         1,
  41210         0,
  41211         0x205,
  41212         SOC_REG_FLAG_WO |
  41213                           SOC_REG_FLAG_INTERRUPT,
  41214         0,
  41215         1,
  41216         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM83208_A0r_fields,
  41217         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41218         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41219         -1,
  41220         -1,
  41221     },
  41222 #endif /* chips */
  41223 
  41224 #if defined(BCM_88375_A0)
  41225     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88375_A0r */
  41226         soc_block_list[23],
  41227         soc_genreg,
  41228         1,
  41229         0,
  41230         0x205,
  41231         SOC_REG_FLAG_WO |
  41232                           SOC_REG_FLAG_INTERRUPT,
  41233         0,
  41234         2,
  41235         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88375_A0r_fields,
  41236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41237         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41238         -1,
  41239         -1,
  41240     },
  41241 #endif /* chips */
  41242 
  41243 #if defined(BCM_88375_B0)
  41244     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88375_B0r */
  41245         soc_block_list[23],
  41246         soc_genreg,
  41247         1,
  41248         0,
  41249         0x205,
  41250         SOC_REG_FLAG_WO |
  41251                           SOC_REG_FLAG_INTERRUPT,
  41252         0,
  41253         2,
  41254         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88375_B0r_fields,
  41255         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41256         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41257         -1,
  41258         -1,
  41259     },
  41260 #endif /* chips */
  41261 
  41262 #if defined(BCM_88470_A0)
  41263     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88470_A0r */
  41264         soc_block_list[23],
  41265         soc_genreg,
  41266         1,
  41267         0,
  41268         0x205,
  41269         SOC_REG_FLAG_WO |
  41270                           SOC_REG_FLAG_INTERRUPT |
  41271                           SOC_REG_FLAG_SIGNAL,
  41272         0,
  41273         3,
  41274         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88470_A0r_fields,
  41275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41276         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  41277         -1,
  41278         -1,
  41279     },
  41280 #endif /* chips */
  41281 
  41282 #if defined(BCM_88470_B0)
  41283     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88470_B0r */
  41284         soc_block_list[23],
  41285         soc_genreg,
  41286         1,
  41287         0,
  41288         0x205,
  41289         SOC_REG_FLAG_WO |
  41290                           SOC_REG_FLAG_INTERRUPT |
  41291                           SOC_REG_FLAG_SIGNAL,
  41292         0,
  41293         3,
  41294         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88470_B0r_fields,
  41295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41296         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  41297         -1,
  41298         -1,
  41299     },
  41300 #endif /* chips */
  41301 
  41302 #if defined(BCM_88675_B0)
  41303     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88675_B0r */
  41304         soc_block_list[23],
  41305         soc_genreg,
  41306         1,
  41307         0,
  41308         0x205,
  41309         SOC_REG_FLAG_WO |
  41310                           SOC_REG_FLAG_INTERRUPT,
  41311         0,
  41312         2,
  41313         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88675_B0r_fields,
  41314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41315         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41316         -1,
  41317         -1,
  41318     },
  41319 #endif /* chips */
  41320 
  41321 #if defined(BCM_88680_A0)
  41322     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88680_A0r */
  41323         soc_block_list[23],
  41324         soc_genreg,
  41325         1,
  41326         0,
  41327         0x205,
  41328         SOC_REG_FLAG_WO |
  41329                           SOC_REG_FLAG_INTERRUPT,
  41330         0,
  41331         2,
  41332         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88680_A0r_fields,
  41333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41334         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41335         -1,
  41336         -1,
  41337     },
  41338 #endif /* chips */
  41339 
  41340 #if defined(BCM_88690_A0)
  41341     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88690_A0r */
  41342         soc_block_list[23],
  41343         soc_genreg,
  41344         1,
  41345         0,
  41346         0x10c,
  41347         SOC_REG_FLAG_WO |
  41348                           SOC_REG_FLAG_INTERRUPT |
  41349                           SOC_REG_FLAG_SIGNAL,
  41350         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  41351         1,
  41352         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88690_A0r_fields,
  41353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41354         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41355         -1,
  41356         -1,
  41357     },
  41358 #endif /* chips */
  41359 
  41360 #if defined(BCM_88690_B0)
  41361     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88690_B0r */
  41362         soc_block_list[23],
  41363         soc_genreg,
  41364         1,
  41365         0,
  41366         0x10c,
  41367         SOC_REG_FLAG_WO |
  41368                           SOC_REG_FLAG_INTERRUPT |
  41369                           SOC_REG_FLAG_SIGNAL,
  41370         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  41371         1,
  41372         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88690_B0r_fields,
  41373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41374         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41375         -1,
  41376         -1,
  41377     },
  41378 #endif /* chips */
  41379 
  41380 #if defined(BCM_88790_A0)
  41381     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88790_A0r */
  41382         soc_block_list[23],
  41383         soc_genreg,
  41384         1,
  41385         0,
  41386         0x10c,
  41387         SOC_REG_FLAG_WO |
  41388                           SOC_REG_FLAG_INTERRUPT |
  41389                           SOC_REG_FLAG_SIGNAL,
  41390         0,
  41391         1,
  41392         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_BCM88790_A0r_fields,
  41393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41394         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41395         -1,
  41396         -1,
  41397     },
  41398 #endif /* chips */
  41399 
  41400 #if defined(BCM_88675_A0)
  41401     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TESTr */
  41402         soc_block_list[23],
  41403         soc_genreg,
  41404         1,
  41405         0,
  41406         0x225,
  41407         SOC_REG_FLAG_WO,
  41408         0,
  41409         1,
  41410         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TESTr_fields,
  41411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41413         -1,
  41414         -1,
  41415     },
  41416 #endif /* chips */
  41417 
  41418 #if defined(BCM_83208_A0)
  41419     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM83208_A0r */
  41420         soc_block_list[23],
  41421         soc_genreg,
  41422         1,
  41423         0,
  41424         0x225,
  41425         SOC_REG_FLAG_WO,
  41426         0,
  41427         1,
  41428         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM83208_A0r_fields,
  41429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41430         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41431         -1,
  41432         -1,
  41433     },
  41434 #endif /* chips */
  41435 
  41436 #if defined(BCM_88375_A0)
  41437     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88375_A0r */
  41438         soc_block_list[23],
  41439         soc_genreg,
  41440         1,
  41441         0,
  41442         0x225,
  41443         SOC_REG_FLAG_WO,
  41444         0,
  41445         1,
  41446         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88375_A0r_fields,
  41447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41448         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41449         -1,
  41450         -1,
  41451     },
  41452 #endif /* chips */
  41453 
  41454 #if defined(BCM_88375_B0)
  41455     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88375_B0r */
  41456         soc_block_list[23],
  41457         soc_genreg,
  41458         1,
  41459         0,
  41460         0x225,
  41461         SOC_REG_FLAG_WO,
  41462         0,
  41463         1,
  41464         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88375_B0r_fields,
  41465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41466         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41467         -1,
  41468         -1,
  41469     },
  41470 #endif /* chips */
  41471 
  41472 #if defined(BCM_88470_A0)
  41473     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88470_A0r */
  41474         soc_block_list[23],
  41475         soc_genreg,
  41476         1,
  41477         0,
  41478         0x225,
  41479         SOC_REG_FLAG_WO,
  41480         0,
  41481         1,
  41482         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88470_A0r_fields,
  41483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41484         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  41485         -1,
  41486         -1,
  41487     },
  41488 #endif /* chips */
  41489 
  41490 #if defined(BCM_88470_B0)
  41491     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88470_B0r */
  41492         soc_block_list[23],
  41493         soc_genreg,
  41494         1,
  41495         0,
  41496         0x225,
  41497         SOC_REG_FLAG_WO,
  41498         0,
  41499         1,
  41500         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88470_B0r_fields,
  41501         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41502         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  41503         -1,
  41504         -1,
  41505     },
  41506 #endif /* chips */
  41507 
  41508 #if defined(BCM_88675_B0)
  41509     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88675_B0r */
  41510         soc_block_list[23],
  41511         soc_genreg,
  41512         1,
  41513         0,
  41514         0x225,
  41515         SOC_REG_FLAG_WO,
  41516         0,
  41517         1,
  41518         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88675_B0r_fields,
  41519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41520         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41521         -1,
  41522         -1,
  41523     },
  41524 #endif /* chips */
  41525 
  41526 #if defined(BCM_88680_A0)
  41527     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88680_A0r */
  41528         soc_block_list[23],
  41529         soc_genreg,
  41530         1,
  41531         0,
  41532         0x225,
  41533         SOC_REG_FLAG_WO,
  41534         0,
  41535         1,
  41536         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88680_A0r_fields,
  41537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41538         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41539         -1,
  41540         -1,
  41541     },
  41542 #endif /* chips */
  41543 
  41544 #if defined(BCM_88690_A0)
  41545     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88690_A0r */
  41546         soc_block_list[23],
  41547         soc_genreg,
  41548         1,
  41549         0,
  41550         0x10e,
  41551         SOC_REG_FLAG_WO,
  41552         0,
  41553         1,
  41554         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88690_A0r_fields,
  41555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41556         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41557         -1,
  41558         -1,
  41559     },
  41560 #endif /* chips */
  41561 
  41562 #if defined(BCM_88690_B0)
  41563     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88690_B0r */
  41564         soc_block_list[23],
  41565         soc_genreg,
  41566         1,
  41567         0,
  41568         0x10e,
  41569         SOC_REG_FLAG_WO,
  41570         0,
  41571         1,
  41572         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88690_B0r_fields,
  41573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41574         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41575         -1,
  41576         -1,
  41577     },
  41578 #endif /* chips */
  41579 
  41580 #if defined(BCM_88790_A0)
  41581     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88790_A0r */
  41582         soc_block_list[23],
  41583         soc_genreg,
  41584         1,
  41585         0,
  41586         0x10e,
  41587         SOC_REG_FLAG_WO,
  41588         0,
  41589         1,
  41590         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88790_A0r_fields,
  41591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41592         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  41593         -1,
  41594         -1,
  41595     },
  41596 #endif /* chips */
  41597 
  41598 #if defined(BCM_83208_A0)
  41599     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM83208_A0r */
  41600         soc_block_list[23],
  41601         soc_genreg,
  41602         1,
  41603         0,
  41604         0x206,
  41605         SOC_REG_FLAG_WO |
  41606                           SOC_REG_FLAG_INTERRUPT,
  41607         0,
  41608         2,
  41609         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM83208_A0r_fields,
  41610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41611         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41612         -1,
  41613         -1,
  41614     },
  41615 #endif /* chips */
  41616 
  41617 #if defined(BCM_88375_A0)
  41618     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88375_A0r */
  41619         soc_block_list[23],
  41620         soc_genreg,
  41621         1,
  41622         0,
  41623         0x206,
  41624         SOC_REG_FLAG_WO |
  41625                           SOC_REG_FLAG_INTERRUPT,
  41626         0,
  41627         2,
  41628         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88375_A0r_fields,
  41629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41630         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41631         -1,
  41632         -1,
  41633     },
  41634 #endif /* chips */
  41635 
  41636 #if defined(BCM_88375_B0)
  41637     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88375_B0r */
  41638         soc_block_list[23],
  41639         soc_genreg,
  41640         1,
  41641         0,
  41642         0x206,
  41643         SOC_REG_FLAG_WO |
  41644                           SOC_REG_FLAG_INTERRUPT,
  41645         0,
  41646         2,
  41647         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88375_B0r_fields,
  41648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41649         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41650         -1,
  41651         -1,
  41652     },
  41653 #endif /* chips */
  41654 
  41655 #if defined(BCM_88470_A0)
  41656     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88470_A0r */
  41657         soc_block_list[23],
  41658         soc_genreg,
  41659         1,
  41660         0,
  41661         0x206,
  41662         SOC_REG_FLAG_WO |
  41663                           SOC_REG_FLAG_INTERRUPT |
  41664                           SOC_REG_FLAG_SIGNAL,
  41665         0,
  41666         2,
  41667         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88470_A0r_fields,
  41668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41669         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41670         -1,
  41671         -1,
  41672     },
  41673 #endif /* chips */
  41674 
  41675 #if defined(BCM_88470_B0)
  41676     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88470_B0r */
  41677         soc_block_list[23],
  41678         soc_genreg,
  41679         1,
  41680         0,
  41681         0x206,
  41682         SOC_REG_FLAG_WO |
  41683                           SOC_REG_FLAG_INTERRUPT |
  41684                           SOC_REG_FLAG_SIGNAL,
  41685         0,
  41686         2,
  41687         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88470_B0r_fields,
  41688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41689         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41690         -1,
  41691         -1,
  41692     },
  41693 #endif /* chips */
  41694 
  41695 #if defined(BCM_88675_B0)
  41696     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88675_B0r */
  41697         soc_block_list[23],
  41698         soc_genreg,
  41699         1,
  41700         0,
  41701         0x206,
  41702         SOC_REG_FLAG_WO |
  41703                           SOC_REG_FLAG_INTERRUPT,
  41704         0,
  41705         2,
  41706         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88675_B0r_fields,
  41707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41708         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41709         -1,
  41710         -1,
  41711     },
  41712 #endif /* chips */
  41713 
  41714 #if defined(BCM_88680_A0)
  41715     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88680_A0r */
  41716         soc_block_list[23],
  41717         soc_genreg,
  41718         1,
  41719         0,
  41720         0x206,
  41721         SOC_REG_FLAG_WO |
  41722                           SOC_REG_FLAG_INTERRUPT,
  41723         0,
  41724         2,
  41725         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88680_A0r_fields,
  41726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41727         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41728         -1,
  41729         -1,
  41730     },
  41731 #endif /* chips */
  41732 
  41733 #if defined(BCM_88690_A0)
  41734     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88690_A0r */
  41735         soc_block_list[23],
  41736         soc_genreg,
  41737         1,
  41738         0,
  41739         0x10f,
  41740         SOC_REG_FLAG_WO |
  41741                           SOC_REG_FLAG_INTERRUPT |
  41742                           SOC_REG_FLAG_SIGNAL,
  41743         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  41744         2,
  41745         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88690_A0r_fields,
  41746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41747         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41748         -1,
  41749         -1,
  41750     },
  41751 #endif /* chips */
  41752 
  41753 #if defined(BCM_88690_B0)
  41754     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88690_B0r */
  41755         soc_block_list[23],
  41756         soc_genreg,
  41757         1,
  41758         0,
  41759         0x10f,
  41760         SOC_REG_FLAG_WO |
  41761                           SOC_REG_FLAG_INTERRUPT |
  41762                           SOC_REG_FLAG_SIGNAL,
  41763         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  41764         2,
  41765         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88690_B0r_fields,
  41766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41767         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41768         -1,
  41769         -1,
  41770     },
  41771 #endif /* chips */
  41772 
  41773 #if defined(BCM_88790_A0)
  41774     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88790_A0r */
  41775         soc_block_list[23],
  41776         soc_genreg,
  41777         1,
  41778         0,
  41779         0x10f,
  41780         SOC_REG_FLAG_WO |
  41781                           SOC_REG_FLAG_INTERRUPT |
  41782                           SOC_REG_FLAG_SIGNAL,
  41783         0,
  41784         2,
  41785         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_BCM88790_A0r_fields,
  41786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41787         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41788         -1,
  41789         -1,
  41790     },
  41791 #endif /* chips */
  41792 
  41793 #if defined(BCM_88675_A0)
  41794     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TESTr */
  41795         soc_block_list[23],
  41796         soc_genreg,
  41797         1,
  41798         0,
  41799         0x226,
  41800         SOC_REG_FLAG_WO,
  41801         0,
  41802         1,
  41803         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TESTr_fields,
  41804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41805         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41806         -1,
  41807         -1,
  41808     },
  41809 #endif /* chips */
  41810 
  41811 #if defined(BCM_83208_A0)
  41812     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM83208_A0r */
  41813         soc_block_list[23],
  41814         soc_genreg,
  41815         1,
  41816         0,
  41817         0x226,
  41818         SOC_REG_FLAG_WO,
  41819         0,
  41820         1,
  41821         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM83208_A0r_fields,
  41822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41824         -1,
  41825         -1,
  41826     },
  41827 #endif /* chips */
  41828 
  41829 #if defined(BCM_88375_A0)
  41830     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88375_A0r */
  41831         soc_block_list[23],
  41832         soc_genreg,
  41833         1,
  41834         0,
  41835         0x226,
  41836         SOC_REG_FLAG_WO,
  41837         0,
  41838         1,
  41839         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88375_A0r_fields,
  41840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41842         -1,
  41843         -1,
  41844     },
  41845 #endif /* chips */
  41846 
  41847 #if defined(BCM_88375_B0)
  41848     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88375_B0r */
  41849         soc_block_list[23],
  41850         soc_genreg,
  41851         1,
  41852         0,
  41853         0x226,
  41854         SOC_REG_FLAG_WO,
  41855         0,
  41856         1,
  41857         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88375_B0r_fields,
  41858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41860         -1,
  41861         -1,
  41862     },
  41863 #endif /* chips */
  41864 
  41865 #if defined(BCM_88470_A0)
  41866     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88470_A0r */
  41867         soc_block_list[23],
  41868         soc_genreg,
  41869         1,
  41870         0,
  41871         0x226,
  41872         SOC_REG_FLAG_WO,
  41873         0,
  41874         1,
  41875         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88470_A0r_fields,
  41876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41877         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41878         -1,
  41879         -1,
  41880     },
  41881 #endif /* chips */
  41882 
  41883 #if defined(BCM_88470_B0)
  41884     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88470_B0r */
  41885         soc_block_list[23],
  41886         soc_genreg,
  41887         1,
  41888         0,
  41889         0x226,
  41890         SOC_REG_FLAG_WO,
  41891         0,
  41892         1,
  41893         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88470_B0r_fields,
  41894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41895         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41896         -1,
  41897         -1,
  41898     },
  41899 #endif /* chips */
  41900 
  41901 #if defined(BCM_88675_B0)
  41902     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88675_B0r */
  41903         soc_block_list[23],
  41904         soc_genreg,
  41905         1,
  41906         0,
  41907         0x226,
  41908         SOC_REG_FLAG_WO,
  41909         0,
  41910         1,
  41911         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88675_B0r_fields,
  41912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41914         -1,
  41915         -1,
  41916     },
  41917 #endif /* chips */
  41918 
  41919 #if defined(BCM_88680_A0)
  41920     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88680_A0r */
  41921         soc_block_list[23],
  41922         soc_genreg,
  41923         1,
  41924         0,
  41925         0x226,
  41926         SOC_REG_FLAG_WO,
  41927         0,
  41928         1,
  41929         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88680_A0r_fields,
  41930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41931         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  41932         -1,
  41933         -1,
  41934     },
  41935 #endif /* chips */
  41936 
  41937 #if defined(BCM_88690_A0)
  41938     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88690_A0r */
  41939         soc_block_list[23],
  41940         soc_genreg,
  41941         1,
  41942         0,
  41943         0x111,
  41944         SOC_REG_FLAG_WO,
  41945         0,
  41946         1,
  41947         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88690_A0r_fields,
  41948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41949         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41950         -1,
  41951         -1,
  41952     },
  41953 #endif /* chips */
  41954 
  41955 #if defined(BCM_88690_B0)
  41956     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88690_B0r */
  41957         soc_block_list[23],
  41958         soc_genreg,
  41959         1,
  41960         0,
  41961         0x111,
  41962         SOC_REG_FLAG_WO,
  41963         0,
  41964         1,
  41965         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88690_B0r_fields,
  41966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41967         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41968         -1,
  41969         -1,
  41970     },
  41971 #endif /* chips */
  41972 
  41973 #if defined(BCM_88790_A0)
  41974     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88790_A0r */
  41975         soc_block_list[23],
  41976         soc_genreg,
  41977         1,
  41978         0,
  41979         0x111,
  41980         SOC_REG_FLAG_WO,
  41981         0,
  41982         1,
  41983         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88790_A0r_fields,
  41984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  41985         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  41986         -1,
  41987         -1,
  41988     },
  41989 #endif /* chips */
  41990 
  41991 #if defined(BCM_83208_A0)
  41992     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM83208_A0r */
  41993         soc_block_list[23],
  41994         soc_genreg,
  41995         1,
  41996         0,
  41997         0x207,
  41998         SOC_REG_FLAG_WO |
  41999                           SOC_REG_FLAG_INTERRUPT,
  42000         0,
  42001         2,
  42002         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM83208_A0r_fields,
  42003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42004         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42005         -1,
  42006         -1,
  42007     },
  42008 #endif /* chips */
  42009 
  42010 #if defined(BCM_88375_A0)
  42011     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88375_A0r */
  42012         soc_block_list[23],
  42013         soc_genreg,
  42014         1,
  42015         0,
  42016         0x207,
  42017         SOC_REG_FLAG_WO |
  42018                           SOC_REG_FLAG_INTERRUPT,
  42019         0,
  42020         2,
  42021         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88375_A0r_fields,
  42022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42023         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42024         -1,
  42025         -1,
  42026     },
  42027 #endif /* chips */
  42028 
  42029 #if defined(BCM_88375_B0)
  42030     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88375_B0r */
  42031         soc_block_list[23],
  42032         soc_genreg,
  42033         1,
  42034         0,
  42035         0x207,
  42036         SOC_REG_FLAG_WO |
  42037                           SOC_REG_FLAG_INTERRUPT,
  42038         0,
  42039         2,
  42040         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88375_B0r_fields,
  42041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42042         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42043         -1,
  42044         -1,
  42045     },
  42046 #endif /* chips */
  42047 
  42048 #if defined(BCM_88470_A0)
  42049     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88470_A0r */
  42050         soc_block_list[23],
  42051         soc_genreg,
  42052         1,
  42053         0,
  42054         0x207,
  42055         SOC_REG_FLAG_WO |
  42056                           SOC_REG_FLAG_INTERRUPT |
  42057                           SOC_REG_FLAG_SIGNAL,
  42058         0,
  42059         2,
  42060         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88470_A0r_fields,
  42061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42062         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42063         -1,
  42064         -1,
  42065     },
  42066 #endif /* chips */
  42067 
  42068 #if defined(BCM_88470_B0)
  42069     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88470_B0r */
  42070         soc_block_list[23],
  42071         soc_genreg,
  42072         1,
  42073         0,
  42074         0x207,
  42075         SOC_REG_FLAG_WO |
  42076                           SOC_REG_FLAG_INTERRUPT |
  42077                           SOC_REG_FLAG_SIGNAL,
  42078         0,
  42079         2,
  42080         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88470_B0r_fields,
  42081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42082         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42083         -1,
  42084         -1,
  42085     },
  42086 #endif /* chips */
  42087 
  42088 #if defined(BCM_88675_B0)
  42089     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88675_B0r */
  42090         soc_block_list[23],
  42091         soc_genreg,
  42092         1,
  42093         0,
  42094         0x207,
  42095         SOC_REG_FLAG_WO |
  42096                           SOC_REG_FLAG_INTERRUPT,
  42097         0,
  42098         2,
  42099         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88675_B0r_fields,
  42100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42101         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42102         -1,
  42103         -1,
  42104     },
  42105 #endif /* chips */
  42106 
  42107 #if defined(BCM_88680_A0)
  42108     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88680_A0r */
  42109         soc_block_list[23],
  42110         soc_genreg,
  42111         1,
  42112         0,
  42113         0x207,
  42114         SOC_REG_FLAG_WO |
  42115                           SOC_REG_FLAG_INTERRUPT,
  42116         0,
  42117         2,
  42118         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88680_A0r_fields,
  42119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42120         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42121         -1,
  42122         -1,
  42123     },
  42124 #endif /* chips */
  42125 
  42126 #if defined(BCM_88690_A0)
  42127     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88690_A0r */
  42128         soc_block_list[23],
  42129         soc_genreg,
  42130         1,
  42131         0,
  42132         0x112,
  42133         SOC_REG_FLAG_WO |
  42134                           SOC_REG_FLAG_INTERRUPT |
  42135                           SOC_REG_FLAG_SIGNAL,
  42136         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  42137         2,
  42138         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88690_A0r_fields,
  42139         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42140         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42141         -1,
  42142         -1,
  42143     },
  42144 #endif /* chips */
  42145 
  42146 #if defined(BCM_88690_B0)
  42147     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88690_B0r */
  42148         soc_block_list[23],
  42149         soc_genreg,
  42150         1,
  42151         0,
  42152         0x112,
  42153         SOC_REG_FLAG_WO |
  42154                           SOC_REG_FLAG_INTERRUPT |
  42155                           SOC_REG_FLAG_SIGNAL,
  42156         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  42157         2,
  42158         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88690_B0r_fields,
  42159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42160         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42161         -1,
  42162         -1,
  42163     },
  42164 #endif /* chips */
  42165 
  42166 #if defined(BCM_88790_A0)
  42167     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88790_A0r */
  42168         soc_block_list[23],
  42169         soc_genreg,
  42170         1,
  42171         0,
  42172         0x112,
  42173         SOC_REG_FLAG_WO |
  42174                           SOC_REG_FLAG_INTERRUPT |
  42175                           SOC_REG_FLAG_SIGNAL,
  42176         0,
  42177         2,
  42178         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_BCM88790_A0r_fields,
  42179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42180         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42181         -1,
  42182         -1,
  42183     },
  42184 #endif /* chips */
  42185 
  42186 #if defined(BCM_88675_A0)
  42187     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TESTr */
  42188         soc_block_list[23],
  42189         soc_genreg,
  42190         1,
  42191         0,
  42192         0x227,
  42193         SOC_REG_FLAG_WO,
  42194         0,
  42195         1,
  42196         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TESTr_fields,
  42197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42198         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42199         -1,
  42200         -1,
  42201     },
  42202 #endif /* chips */
  42203 
  42204 #if defined(BCM_83208_A0)
  42205     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM83208_A0r */
  42206         soc_block_list[23],
  42207         soc_genreg,
  42208         1,
  42209         0,
  42210         0x227,
  42211         SOC_REG_FLAG_WO,
  42212         0,
  42213         1,
  42214         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM83208_A0r_fields,
  42215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42216         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42217         -1,
  42218         -1,
  42219     },
  42220 #endif /* chips */
  42221 
  42222 #if defined(BCM_88375_A0)
  42223     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88375_A0r */
  42224         soc_block_list[23],
  42225         soc_genreg,
  42226         1,
  42227         0,
  42228         0x227,
  42229         SOC_REG_FLAG_WO,
  42230         0,
  42231         1,
  42232         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88375_A0r_fields,
  42233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42234         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42235         -1,
  42236         -1,
  42237     },
  42238 #endif /* chips */
  42239 
  42240 #if defined(BCM_88375_B0)
  42241     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88375_B0r */
  42242         soc_block_list[23],
  42243         soc_genreg,
  42244         1,
  42245         0,
  42246         0x227,
  42247         SOC_REG_FLAG_WO,
  42248         0,
  42249         1,
  42250         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88375_B0r_fields,
  42251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42252         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42253         -1,
  42254         -1,
  42255     },
  42256 #endif /* chips */
  42257 
  42258 #if defined(BCM_88470_A0)
  42259     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88470_A0r */
  42260         soc_block_list[23],
  42261         soc_genreg,
  42262         1,
  42263         0,
  42264         0x227,
  42265         SOC_REG_FLAG_WO,
  42266         0,
  42267         1,
  42268         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88470_A0r_fields,
  42269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42270         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42271         -1,
  42272         -1,
  42273     },
  42274 #endif /* chips */
  42275 
  42276 #if defined(BCM_88470_B0)
  42277     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88470_B0r */
  42278         soc_block_list[23],
  42279         soc_genreg,
  42280         1,
  42281         0,
  42282         0x227,
  42283         SOC_REG_FLAG_WO,
  42284         0,
  42285         1,
  42286         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88470_B0r_fields,
  42287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42288         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42289         -1,
  42290         -1,
  42291     },
  42292 #endif /* chips */
  42293 
  42294 #if defined(BCM_88675_B0)
  42295     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88675_B0r */
  42296         soc_block_list[23],
  42297         soc_genreg,
  42298         1,
  42299         0,
  42300         0x227,
  42301         SOC_REG_FLAG_WO,
  42302         0,
  42303         1,
  42304         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88675_B0r_fields,
  42305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42307         -1,
  42308         -1,
  42309     },
  42310 #endif /* chips */
  42311 
  42312 #if defined(BCM_88680_A0)
  42313     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88680_A0r */
  42314         soc_block_list[23],
  42315         soc_genreg,
  42316         1,
  42317         0,
  42318         0x227,
  42319         SOC_REG_FLAG_WO,
  42320         0,
  42321         1,
  42322         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88680_A0r_fields,
  42323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42324         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42325         -1,
  42326         -1,
  42327     },
  42328 #endif /* chips */
  42329 
  42330 #if defined(BCM_88690_A0)
  42331     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88690_A0r */
  42332         soc_block_list[23],
  42333         soc_genreg,
  42334         1,
  42335         0,
  42336         0x114,
  42337         SOC_REG_FLAG_WO,
  42338         0,
  42339         1,
  42340         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88690_A0r_fields,
  42341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42342         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42343         -1,
  42344         -1,
  42345     },
  42346 #endif /* chips */
  42347 
  42348 #if defined(BCM_88690_B0)
  42349     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88690_B0r */
  42350         soc_block_list[23],
  42351         soc_genreg,
  42352         1,
  42353         0,
  42354         0x114,
  42355         SOC_REG_FLAG_WO,
  42356         0,
  42357         1,
  42358         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88690_B0r_fields,
  42359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42360         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42361         -1,
  42362         -1,
  42363     },
  42364 #endif /* chips */
  42365 
  42366 #if defined(BCM_88790_A0)
  42367     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88790_A0r */
  42368         soc_block_list[23],
  42369         soc_genreg,
  42370         1,
  42371         0,
  42372         0x114,
  42373         SOC_REG_FLAG_WO,
  42374         0,
  42375         1,
  42376         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88790_A0r_fields,
  42377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42378         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  42379         -1,
  42380         -1,
  42381     },
  42382 #endif /* chips */
  42383 
  42384 #if defined(BCM_83208_A0)
  42385     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM83208_A0r */
  42386         soc_block_list[23],
  42387         soc_genreg,
  42388         1,
  42389         0,
  42390         0x208,
  42391         SOC_REG_FLAG_WO |
  42392                           SOC_REG_FLAG_INTERRUPT,
  42393         0,
  42394         3,
  42395         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM83208_A0r_fields,
  42396         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42397         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42398         -1,
  42399         -1,
  42400     },
  42401 #endif /* chips */
  42402 
  42403 #if defined(BCM_88375_A0)
  42404     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88375_A0r */
  42405         soc_block_list[23],
  42406         soc_genreg,
  42407         1,
  42408         0,
  42409         0x208,
  42410         SOC_REG_FLAG_WO |
  42411                           SOC_REG_FLAG_INTERRUPT,
  42412         0,
  42413         3,
  42414         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88375_A0r_fields,
  42415         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42416         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42417         -1,
  42418         -1,
  42419     },
  42420 #endif /* chips */
  42421 
  42422 #if defined(BCM_88375_B0)
  42423     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88375_B0r */
  42424         soc_block_list[23],
  42425         soc_genreg,
  42426         1,
  42427         0,
  42428         0x208,
  42429         SOC_REG_FLAG_WO |
  42430                           SOC_REG_FLAG_INTERRUPT,
  42431         0,
  42432         3,
  42433         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88375_B0r_fields,
  42434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42435         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42436         -1,
  42437         -1,
  42438     },
  42439 #endif /* chips */
  42440 
  42441 #if defined(BCM_88470_A0)
  42442     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88470_A0r */
  42443         soc_block_list[23],
  42444         soc_genreg,
  42445         1,
  42446         0,
  42447         0x208,
  42448         SOC_REG_FLAG_WO |
  42449                           SOC_REG_FLAG_INTERRUPT |
  42450                           SOC_REG_FLAG_SIGNAL,
  42451         0,
  42452         3,
  42453         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88470_A0r_fields,
  42454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42455         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42456         -1,
  42457         -1,
  42458     },
  42459 #endif /* chips */
  42460 
  42461 #if defined(BCM_88470_B0)
  42462     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88470_B0r */
  42463         soc_block_list[23],
  42464         soc_genreg,
  42465         1,
  42466         0,
  42467         0x208,
  42468         SOC_REG_FLAG_WO |
  42469                           SOC_REG_FLAG_INTERRUPT |
  42470                           SOC_REG_FLAG_SIGNAL,
  42471         0,
  42472         3,
  42473         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88470_B0r_fields,
  42474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42475         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42476         -1,
  42477         -1,
  42478     },
  42479 #endif /* chips */
  42480 
  42481 #if defined(BCM_88675_B0)
  42482     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88675_B0r */
  42483         soc_block_list[23],
  42484         soc_genreg,
  42485         1,
  42486         0,
  42487         0x208,
  42488         SOC_REG_FLAG_WO |
  42489                           SOC_REG_FLAG_INTERRUPT,
  42490         0,
  42491         3,
  42492         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88675_B0r_fields,
  42493         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42494         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42495         -1,
  42496         -1,
  42497     },
  42498 #endif /* chips */
  42499 
  42500 #if defined(BCM_88680_A0)
  42501     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88680_A0r */
  42502         soc_block_list[23],
  42503         soc_genreg,
  42504         1,
  42505         0,
  42506         0x208,
  42507         SOC_REG_FLAG_WO |
  42508                           SOC_REG_FLAG_INTERRUPT,
  42509         0,
  42510         3,
  42511         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88680_A0r_fields,
  42512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42513         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42514         -1,
  42515         -1,
  42516     },
  42517 #endif /* chips */
  42518 
  42519 #if defined(BCM_88690_A0)
  42520     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88690_A0r */
  42521         soc_block_list[23],
  42522         soc_genreg,
  42523         1,
  42524         0,
  42525         0x115,
  42526         SOC_REG_FLAG_WO |
  42527                           SOC_REG_FLAG_INTERRUPT |
  42528                           SOC_REG_FLAG_SIGNAL,
  42529         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  42530         3,
  42531         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88690_A0r_fields,
  42532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42533         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42534         -1,
  42535         -1,
  42536     },
  42537 #endif /* chips */
  42538 
  42539 #if defined(BCM_88690_B0)
  42540     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88690_B0r */
  42541         soc_block_list[23],
  42542         soc_genreg,
  42543         1,
  42544         0,
  42545         0x115,
  42546         SOC_REG_FLAG_WO |
  42547                           SOC_REG_FLAG_INTERRUPT |
  42548                           SOC_REG_FLAG_SIGNAL,
  42549         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  42550         3,
  42551         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88690_B0r_fields,
  42552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42553         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42554         -1,
  42555         -1,
  42556     },
  42557 #endif /* chips */
  42558 
  42559 #if defined(BCM_88790_A0)
  42560     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88790_A0r */
  42561         soc_block_list[23],
  42562         soc_genreg,
  42563         1,
  42564         0,
  42565         0x115,
  42566         SOC_REG_FLAG_WO |
  42567                           SOC_REG_FLAG_INTERRUPT |
  42568                           SOC_REG_FLAG_SIGNAL,
  42569         0,
  42570         3,
  42571         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_BCM88790_A0r_fields,
  42572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42573         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42574         -1,
  42575         -1,
  42576     },
  42577 #endif /* chips */
  42578 
  42579 #if defined(BCM_88675_A0)
  42580     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TESTr */
  42581         soc_block_list[23],
  42582         soc_genreg,
  42583         1,
  42584         0,
  42585         0x228,
  42586         SOC_REG_FLAG_WO,
  42587         0,
  42588         1,
  42589         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TESTr_fields,
  42590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42591         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42592         -1,
  42593         -1,
  42594     },
  42595 #endif /* chips */
  42596 
  42597 #if defined(BCM_83208_A0)
  42598     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM83208_A0r */
  42599         soc_block_list[23],
  42600         soc_genreg,
  42601         1,
  42602         0,
  42603         0x228,
  42604         SOC_REG_FLAG_WO,
  42605         0,
  42606         1,
  42607         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM83208_A0r_fields,
  42608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42610         -1,
  42611         -1,
  42612     },
  42613 #endif /* chips */
  42614 
  42615 #if defined(BCM_88375_A0)
  42616     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88375_A0r */
  42617         soc_block_list[23],
  42618         soc_genreg,
  42619         1,
  42620         0,
  42621         0x228,
  42622         SOC_REG_FLAG_WO,
  42623         0,
  42624         1,
  42625         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88375_A0r_fields,
  42626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42627         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42628         -1,
  42629         -1,
  42630     },
  42631 #endif /* chips */
  42632 
  42633 #if defined(BCM_88375_B0)
  42634     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88375_B0r */
  42635         soc_block_list[23],
  42636         soc_genreg,
  42637         1,
  42638         0,
  42639         0x228,
  42640         SOC_REG_FLAG_WO,
  42641         0,
  42642         1,
  42643         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88375_B0r_fields,
  42644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42646         -1,
  42647         -1,
  42648     },
  42649 #endif /* chips */
  42650 
  42651 #if defined(BCM_88470_A0)
  42652     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88470_A0r */
  42653         soc_block_list[23],
  42654         soc_genreg,
  42655         1,
  42656         0,
  42657         0x228,
  42658         SOC_REG_FLAG_WO,
  42659         0,
  42660         1,
  42661         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88470_A0r_fields,
  42662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42663         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42664         -1,
  42665         -1,
  42666     },
  42667 #endif /* chips */
  42668 
  42669 #if defined(BCM_88470_B0)
  42670     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88470_B0r */
  42671         soc_block_list[23],
  42672         soc_genreg,
  42673         1,
  42674         0,
  42675         0x228,
  42676         SOC_REG_FLAG_WO,
  42677         0,
  42678         1,
  42679         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88470_B0r_fields,
  42680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42681         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42682         -1,
  42683         -1,
  42684     },
  42685 #endif /* chips */
  42686 
  42687 #if defined(BCM_88675_B0)
  42688     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88675_B0r */
  42689         soc_block_list[23],
  42690         soc_genreg,
  42691         1,
  42692         0,
  42693         0x228,
  42694         SOC_REG_FLAG_WO,
  42695         0,
  42696         1,
  42697         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88675_B0r_fields,
  42698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42700         -1,
  42701         -1,
  42702     },
  42703 #endif /* chips */
  42704 
  42705 #if defined(BCM_88680_A0)
  42706     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88680_A0r */
  42707         soc_block_list[23],
  42708         soc_genreg,
  42709         1,
  42710         0,
  42711         0x228,
  42712         SOC_REG_FLAG_WO,
  42713         0,
  42714         1,
  42715         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88680_A0r_fields,
  42716         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  42718         -1,
  42719         -1,
  42720     },
  42721 #endif /* chips */
  42722 
  42723 #if defined(BCM_88690_A0)
  42724     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88690_A0r */
  42725         soc_block_list[23],
  42726         soc_genreg,
  42727         1,
  42728         0,
  42729         0x117,
  42730         SOC_REG_FLAG_WO,
  42731         0,
  42732         1,
  42733         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88690_A0r_fields,
  42734         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42735         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42736         -1,
  42737         -1,
  42738     },
  42739 #endif /* chips */
  42740 
  42741 #if defined(BCM_88690_B0)
  42742     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88690_B0r */
  42743         soc_block_list[23],
  42744         soc_genreg,
  42745         1,
  42746         0,
  42747         0x117,
  42748         SOC_REG_FLAG_WO,
  42749         0,
  42750         1,
  42751         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88690_B0r_fields,
  42752         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42753         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42754         -1,
  42755         -1,
  42756     },
  42757 #endif /* chips */
  42758 
  42759 #if defined(BCM_88790_A0)
  42760     { /* SOC_REG_INT_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88790_A0r */
  42761         soc_block_list[23],
  42762         soc_genreg,
  42763         1,
  42764         0,
  42765         0x117,
  42766         SOC_REG_FLAG_WO,
  42767         0,
  42768         1,
  42769         soc_BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88790_A0r_fields,
  42770         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  42771         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  42772         -1,
  42773         -1,
  42774     },
  42775 #endif /* chips */
  42776 
  42777 #if defined(BCM_88650_A0)
  42778     { /* SOC_REG_INT_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATIONr */
  42779         soc_block_list[23],
  42780         soc_genreg,
  42781         4,
  42782         0,
  42783         0xa4,
  42784         SOC_REG_FLAG_ARRAY |
  42785                           SOC_REG_FLAG_WO |
  42786                           SOC_REG_FLAG_REG_ARRAY,
  42787         0,
  42788         6,
  42789         soc_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATIONr_fields,
  42790         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  42791         SOC_RESET_MASK_DEC(0x8fffffff, 0x00000000)
  42792         -1,
  42793         -1,
  42794     },
  42795 #endif /* chips */
  42796 
  42797 #if defined(BCM_88202_A0)
  42798     { /* SOC_REG_INT_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATION_BCM88202_A0r */
  42799         soc_block_list[23],
  42800         soc_genreg,
  42801         4,
  42802         0,
  42803         0xa4,
  42804         SOC_REG_FLAG_ARRAY |
  42805                           SOC_REG_FLAG_WO |
  42806                           SOC_REG_FLAG_REG_ARRAY,
  42807         0,
  42808         6,
  42809         soc_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATION_BCM88202_A0r_fields,
  42810         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  42811         SOC_RESET_MASK_DEC(0x8fffffff, 0x00000000)
  42812         -1,
  42813         -1,
  42814     },
  42815 #endif /* chips */
  42816 
  42817 #if defined(BCM_88650_B0)
  42818     { /* SOC_REG_INT_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATION_BCM88650_B0r */
  42819         soc_block_list[23],
  42820         soc_genreg,
  42821         4,
  42822         0,
  42823         0xa4,
  42824         SOC_REG_FLAG_ARRAY |
  42825                           SOC_REG_FLAG_WO |
  42826                           SOC_REG_FLAG_REG_ARRAY,
  42827         0,
  42828         6,
  42829         soc_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATION_BCM88650_B0r_fields,
  42830         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  42831         SOC_RESET_MASK_DEC(0x8fffffff, 0x00000000)
  42832         -1,
  42833         -1,
  42834     },
  42835 #endif /* chips */
  42836 
  42837 #if defined(BCM_88660_A0)
  42838     { /* SOC_REG_INT_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATION_BCM88660_A0r */
  42839         soc_block_list[23],
  42840         soc_genreg,
  42841         4,
  42842         0,
  42843         0xa4,
  42844         SOC_REG_FLAG_ARRAY |
  42845                           SOC_REG_FLAG_WO |
  42846                           SOC_REG_FLAG_REG_ARRAY,
  42847         0,
  42848         6,
  42849         soc_BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATION_BCM88660_A0r_fields,
  42850         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  42851         SOC_RESET_MASK_DEC(0x8fffffff, 0x00000000)
  42852         -1,
  42853         -1,
  42854     },
  42855 #endif /* chips */
  42856 
  42857 #if defined(BCM_88650_A0)
  42858     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATIONr */
  42859         soc_block_list[23],
  42860         soc_genreg,
  42861         4,
  42862         0,
  42863         0xa0,
  42864         SOC_REG_FLAG_ARRAY |
  42865                           SOC_REG_FLAG_WO |
  42866                           SOC_REG_FLAG_REG_ARRAY,
  42867         0,
  42868         9,
  42869         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATIONr_fields,
  42870         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  42871         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  42872         -1,
  42873         -1,
  42874     },
  42875 #endif /* chips */
  42876 
  42877 #if defined(BCM_83208_A0)
  42878     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM83208_A0r */
  42879         soc_block_list[23],
  42880         soc_genreg,
  42881         4,
  42882         0,
  42883         0x132,
  42884         SOC_REG_FLAG_ARRAY |
  42885                           SOC_REG_FLAG_WO |
  42886                           SOC_REG_FLAG_REG_ARRAY,
  42887         0,
  42888         7,
  42889         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM83208_A0r_fields,
  42890         SOC_RESET_VAL_DEC(0x0000024a, 0x00000000)
  42891         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  42892         -1,
  42893         -1,
  42894     },
  42895 #endif /* chips */
  42896 
  42897 #if defined(BCM_88202_A0)
  42898     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88202_A0r */
  42899         soc_block_list[23],
  42900         soc_genreg,
  42901         4,
  42902         0,
  42903         0xa0,
  42904         SOC_REG_FLAG_ARRAY |
  42905                           SOC_REG_FLAG_WO |
  42906                           SOC_REG_FLAG_REG_ARRAY,
  42907         0,
  42908         9,
  42909         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88202_A0r_fields,
  42910         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  42911         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  42912         -1,
  42913         -1,
  42914     },
  42915 #endif /* chips */
  42916 
  42917 #if defined(BCM_88375_A0)
  42918     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88375_A0r */
  42919         soc_block_list[23],
  42920         soc_genreg,
  42921         4,
  42922         0,
  42923         0x11d,
  42924         SOC_REG_FLAG_ARRAY |
  42925                           SOC_REG_FLAG_WO |
  42926                           SOC_REG_FLAG_REG_ARRAY,
  42927         0,
  42928         6,
  42929         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88375_A0r_fields,
  42930         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  42931         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42932         -1,
  42933         -1,
  42934     },
  42935 #endif /* chips */
  42936 
  42937 #if defined(BCM_88375_B0)
  42938     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88375_B0r */
  42939         soc_block_list[23],
  42940         soc_genreg,
  42941         4,
  42942         0,
  42943         0x11d,
  42944         SOC_REG_FLAG_ARRAY |
  42945                           SOC_REG_FLAG_WO |
  42946                           SOC_REG_FLAG_REG_ARRAY,
  42947         0,
  42948         6,
  42949         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88375_B0r_fields,
  42950         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  42951         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42952         -1,
  42953         -1,
  42954     },
  42955 #endif /* chips */
  42956 
  42957 #if defined(BCM_88470_A0)
  42958     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88470_A0r */
  42959         soc_block_list[23],
  42960         soc_genreg,
  42961         4,
  42962         0,
  42963         0x121,
  42964         SOC_REG_FLAG_ARRAY |
  42965                           SOC_REG_FLAG_WO |
  42966                           SOC_REG_FLAG_REG_ARRAY,
  42967         0,
  42968         6,
  42969         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88470_A0r_fields,
  42970         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  42971         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42972         -1,
  42973         -1,
  42974     },
  42975 #endif /* chips */
  42976 
  42977 #if defined(BCM_88470_B0)
  42978     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88470_B0r */
  42979         soc_block_list[23],
  42980         soc_genreg,
  42981         4,
  42982         0,
  42983         0x121,
  42984         SOC_REG_FLAG_ARRAY |
  42985                           SOC_REG_FLAG_WO |
  42986                           SOC_REG_FLAG_REG_ARRAY,
  42987         0,
  42988         6,
  42989         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88470_B0r_fields,
  42990         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  42991         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  42992         -1,
  42993         -1,
  42994     },
  42995 #endif /* chips */
  42996 
  42997 #if defined(BCM_88650_B0)
  42998     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88650_B0r */
  42999         soc_block_list[23],
  43000         soc_genreg,
  43001         4,
  43002         0,
  43003         0xa0,
  43004         SOC_REG_FLAG_ARRAY |
  43005                           SOC_REG_FLAG_WO |
  43006                           SOC_REG_FLAG_REG_ARRAY,
  43007         0,
  43008         9,
  43009         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88650_B0r_fields,
  43010         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  43011         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  43012         -1,
  43013         -1,
  43014     },
  43015 #endif /* chips */
  43016 
  43017 #if defined(BCM_88660_A0)
  43018     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88660_A0r */
  43019         soc_block_list[23],
  43020         soc_genreg,
  43021         4,
  43022         0,
  43023         0xa0,
  43024         SOC_REG_FLAG_ARRAY |
  43025                           SOC_REG_FLAG_WO |
  43026                           SOC_REG_FLAG_REG_ARRAY,
  43027         0,
  43028         9,
  43029         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88660_A0r_fields,
  43030         SOC_RESET_VAL_DEC(0x00000422, 0x00000000)
  43031         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  43032         -1,
  43033         -1,
  43034     },
  43035 #endif /* chips */
  43036 
  43037 #if defined(BCM_88675_A0)
  43038     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88675_A0r */
  43039         soc_block_list[23],
  43040         soc_genreg,
  43041         4,
  43042         0,
  43043         0x11d,
  43044         SOC_REG_FLAG_ARRAY |
  43045                           SOC_REG_FLAG_WO |
  43046                           SOC_REG_FLAG_REG_ARRAY,
  43047         0,
  43048         6,
  43049         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88675_A0r_fields,
  43050         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  43051         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43052         -1,
  43053         -1,
  43054     },
  43055 #endif /* chips */
  43056 
  43057 #if defined(BCM_88675_B0)
  43058     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88675_B0r */
  43059         soc_block_list[23],
  43060         soc_genreg,
  43061         4,
  43062         0,
  43063         0x11d,
  43064         SOC_REG_FLAG_ARRAY |
  43065                           SOC_REG_FLAG_WO |
  43066                           SOC_REG_FLAG_REG_ARRAY,
  43067         0,
  43068         6,
  43069         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88675_B0r_fields,
  43070         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  43071         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43072         -1,
  43073         -1,
  43074     },
  43075 #endif /* chips */
  43076 
  43077 #if defined(BCM_88680_A0)
  43078     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88680_A0r */
  43079         soc_block_list[23],
  43080         soc_genreg,
  43081         4,
  43082         0,
  43083         0x11d,
  43084         SOC_REG_FLAG_ARRAY |
  43085                           SOC_REG_FLAG_WO |
  43086                           SOC_REG_FLAG_REG_ARRAY,
  43087         0,
  43088         6,
  43089         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88680_A0r_fields,
  43090         SOC_RESET_VAL_DEC(0x0000004a, 0x00000000)
  43091         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  43092         -1,
  43093         -1,
  43094     },
  43095 #endif /* chips */
  43096 
  43097 #if defined(BCM_88690_A0)
  43098     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88690_A0r */
  43099         soc_block_list[23],
  43100         soc_genreg,
  43101         4,
  43102         0,
  43103         0x16a,
  43104         SOC_REG_FLAG_ARRAY |
  43105                           SOC_REG_FLAG_WO |
  43106                           SOC_REG_FLAG_REG_ARRAY,
  43107         0,
  43108         8,
  43109         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88690_A0r_fields,
  43110         SOC_RESET_VAL_DEC(0x0000224c, 0x00000000)
  43111         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  43112         -1,
  43113         -1,
  43114     },
  43115 #endif /* chips */
  43116 
  43117 #if defined(BCM_88690_B0)
  43118     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88690_B0r */
  43119         soc_block_list[23],
  43120         soc_genreg,
  43121         4,
  43122         0,
  43123         0x16a,
  43124         SOC_REG_FLAG_ARRAY |
  43125                           SOC_REG_FLAG_WO |
  43126                           SOC_REG_FLAG_REG_ARRAY,
  43127         0,
  43128         8,
  43129         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88690_B0r_fields,
  43130         SOC_RESET_VAL_DEC(0x0000224c, 0x00000000)
  43131         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  43132         -1,
  43133         -1,
  43134     },
  43135 #endif /* chips */
  43136 
  43137 #if defined(BCM_88790_A0)
  43138     { /* SOC_REG_INT_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88790_A0r */
  43139         soc_block_list[23],
  43140         soc_genreg,
  43141         4,
  43142         0,
  43143         0x16a,
  43144         SOC_REG_FLAG_ARRAY |
  43145                           SOC_REG_FLAG_WO |
  43146                           SOC_REG_FLAG_REG_ARRAY,
  43147         0,
  43148         8,
  43149         soc_BRDC_FMAC_FMAL_GENERAL_CONFIGURATION_BCM88790_A0r_fields,
  43150         SOC_RESET_VAL_DEC(0x0000224c, 0x00000000)
  43151         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  43152         -1,
  43153         -1,
  43154     },
  43155 #endif /* chips */
  43156 
  43157 #if defined(BCM_88790_A0)
  43158     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RCI_GCI_WMKr */
  43159         soc_block_list[23],
  43160         soc_genreg,
  43161         4,
  43162         0,
  43163         0x130,
  43164         SOC_REG_FLAG_ARRAY |
  43165                           SOC_REG_FLAG_RO |
  43166                           SOC_REG_FLAG_WO |
  43167                           SOC_REG_FLAG_REG_ARRAY,
  43168         0,
  43169         4,
  43170         soc_BRDC_FMAC_FMAL_RCI_GCI_WMKr_fields,
  43171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43172         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43173         -1,
  43174         -1,
  43175     },
  43176 #endif /* chips */
  43177 
  43178 #if defined(BCM_88690_A0)
  43179     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RCI_GCI_WMK_BCM88690_A0r */
  43180         soc_block_list[23],
  43181         soc_genreg,
  43182         4,
  43183         0,
  43184         0x130,
  43185         SOC_REG_FLAG_ARRAY |
  43186                           SOC_REG_FLAG_RO |
  43187                           SOC_REG_FLAG_WO |
  43188                           SOC_REG_FLAG_REG_ARRAY,
  43189         SOC_REG_FLAG_INIT_ON_READ,
  43190         4,
  43191         soc_BRDC_FMAC_FMAL_RCI_GCI_WMK_BCM88690_A0r_fields,
  43192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43193         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43194         -1,
  43195         -1,
  43196     },
  43197 #endif /* chips */
  43198 
  43199 #if defined(BCM_88690_B0)
  43200     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RCI_GCI_WMK_BCM88690_B0r */
  43201         soc_block_list[23],
  43202         soc_genreg,
  43203         4,
  43204         0,
  43205         0x130,
  43206         SOC_REG_FLAG_ARRAY |
  43207                           SOC_REG_FLAG_RO |
  43208                           SOC_REG_FLAG_WO |
  43209                           SOC_REG_FLAG_REG_ARRAY,
  43210         SOC_REG_FLAG_INIT_ON_READ,
  43211         4,
  43212         soc_BRDC_FMAC_FMAL_RCI_GCI_WMK_BCM88690_B0r_fields,
  43213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43214         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43215         -1,
  43216         -1,
  43217     },
  43218 #endif /* chips */
  43219 
  43220 #if defined(BCM_88675_A0)
  43221     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATIONr */
  43222         soc_block_list[23],
  43223         soc_genreg,
  43224         4,
  43225         0,
  43226         0x125,
  43227         SOC_REG_FLAG_ARRAY |
  43228                           SOC_REG_FLAG_WO |
  43229                           SOC_REG_FLAG_REG_ARRAY,
  43230         0,
  43231         8,
  43232         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATIONr_fields,
  43233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43234         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43235         -1,
  43236         -1,
  43237     },
  43238 #endif /* chips */
  43239 
  43240 #if defined(BCM_83208_A0)
  43241     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM83208_A0r */
  43242         soc_block_list[23],
  43243         soc_genreg,
  43244         4,
  43245         0,
  43246         0x13a,
  43247         SOC_REG_FLAG_ARRAY |
  43248                           SOC_REG_FLAG_WO |
  43249                           SOC_REG_FLAG_REG_ARRAY,
  43250         0,
  43251         9,
  43252         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM83208_A0r_fields,
  43253         SOC_RESET_VAL_DEC(0x00080000, 0x00000000)
  43254         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  43255         -1,
  43256         -1,
  43257     },
  43258 #endif /* chips */
  43259 
  43260 #if defined(BCM_88375_A0)
  43261     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88375_A0r */
  43262         soc_block_list[23],
  43263         soc_genreg,
  43264         4,
  43265         0,
  43266         0x125,
  43267         SOC_REG_FLAG_ARRAY |
  43268                           SOC_REG_FLAG_WO |
  43269                           SOC_REG_FLAG_REG_ARRAY,
  43270         0,
  43271         8,
  43272         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88375_A0r_fields,
  43273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43274         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43275         -1,
  43276         -1,
  43277     },
  43278 #endif /* chips */
  43279 
  43280 #if defined(BCM_88375_B0)
  43281     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88375_B0r */
  43282         soc_block_list[23],
  43283         soc_genreg,
  43284         4,
  43285         0,
  43286         0x125,
  43287         SOC_REG_FLAG_ARRAY |
  43288                           SOC_REG_FLAG_WO |
  43289                           SOC_REG_FLAG_REG_ARRAY,
  43290         0,
  43291         8,
  43292         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88375_B0r_fields,
  43293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43294         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43295         -1,
  43296         -1,
  43297     },
  43298 #endif /* chips */
  43299 
  43300 #if defined(BCM_88470_A0)
  43301     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88470_A0r */
  43302         soc_block_list[23],
  43303         soc_genreg,
  43304         4,
  43305         0,
  43306         0x12d,
  43307         SOC_REG_FLAG_ARRAY |
  43308                           SOC_REG_FLAG_WO |
  43309                           SOC_REG_FLAG_REG_ARRAY,
  43310         0,
  43311         8,
  43312         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88470_A0r_fields,
  43313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43314         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43315         -1,
  43316         -1,
  43317     },
  43318 #endif /* chips */
  43319 
  43320 #if defined(BCM_88470_B0)
  43321     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88470_B0r */
  43322         soc_block_list[23],
  43323         soc_genreg,
  43324         4,
  43325         0,
  43326         0x12d,
  43327         SOC_REG_FLAG_ARRAY |
  43328                           SOC_REG_FLAG_WO |
  43329                           SOC_REG_FLAG_REG_ARRAY,
  43330         0,
  43331         8,
  43332         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88470_B0r_fields,
  43333         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43334         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43335         -1,
  43336         -1,
  43337     },
  43338 #endif /* chips */
  43339 
  43340 #if defined(BCM_88675_B0)
  43341     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88675_B0r */
  43342         soc_block_list[23],
  43343         soc_genreg,
  43344         4,
  43345         0,
  43346         0x125,
  43347         SOC_REG_FLAG_ARRAY |
  43348                           SOC_REG_FLAG_WO |
  43349                           SOC_REG_FLAG_REG_ARRAY,
  43350         0,
  43351         8,
  43352         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88675_B0r_fields,
  43353         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43354         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43355         -1,
  43356         -1,
  43357     },
  43358 #endif /* chips */
  43359 
  43360 #if defined(BCM_88680_A0)
  43361     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88680_A0r */
  43362         soc_block_list[23],
  43363         soc_genreg,
  43364         4,
  43365         0,
  43366         0x125,
  43367         SOC_REG_FLAG_ARRAY |
  43368                           SOC_REG_FLAG_WO |
  43369                           SOC_REG_FLAG_REG_ARRAY,
  43370         0,
  43371         8,
  43372         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88680_A0r_fields,
  43373         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43374         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43375         -1,
  43376         -1,
  43377     },
  43378 #endif /* chips */
  43379 
  43380 #if defined(BCM_88690_A0)
  43381     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88690_A0r */
  43382         soc_block_list[23],
  43383         soc_genreg,
  43384         4,
  43385         0,
  43386         0x176,
  43387         SOC_REG_FLAG_ARRAY |
  43388                           SOC_REG_FLAG_WO |
  43389                           SOC_REG_FLAG_REG_ARRAY,
  43390         0,
  43391         8,
  43392         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88690_A0r_fields,
  43393         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  43394         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43395         -1,
  43396         -1,
  43397     },
  43398 #endif /* chips */
  43399 
  43400 #if defined(BCM_88690_B0)
  43401     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88690_B0r */
  43402         soc_block_list[23],
  43403         soc_genreg,
  43404         4,
  43405         0,
  43406         0x176,
  43407         SOC_REG_FLAG_ARRAY |
  43408                           SOC_REG_FLAG_WO |
  43409                           SOC_REG_FLAG_REG_ARRAY,
  43410         0,
  43411         8,
  43412         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88690_B0r_fields,
  43413         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  43414         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43415         -1,
  43416         -1,
  43417     },
  43418 #endif /* chips */
  43419 
  43420 #if defined(BCM_88790_A0)
  43421     { /* SOC_REG_INT_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88790_A0r */
  43422         soc_block_list[23],
  43423         soc_genreg,
  43424         4,
  43425         0,
  43426         0x176,
  43427         SOC_REG_FLAG_ARRAY |
  43428                           SOC_REG_FLAG_WO |
  43429                           SOC_REG_FLAG_REG_ARRAY,
  43430         0,
  43431         8,
  43432         soc_BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION_BCM88790_A0r_fields,
  43433         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  43434         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  43435         -1,
  43436         -1,
  43437     },
  43438 #endif /* chips */
  43439 
  43440 #if defined(BCM_88650_A0)
  43441     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROLr */
  43442         soc_block_list[23],
  43443         soc_genreg,
  43444         1,
  43445         0,
  43446         0x90,
  43447         SOC_REG_FLAG_WO,
  43448         0,
  43449         2,
  43450         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROLr_fields,
  43451         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43452         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43453         -1,
  43454         -1,
  43455     },
  43456 #endif /* chips */
  43457 
  43458 #if defined(BCM_83208_A0)
  43459     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM83208_A0r */
  43460         soc_block_list[23],
  43461         soc_genreg,
  43462         1,
  43463         0,
  43464         0x124,
  43465         SOC_REG_FLAG_WO,
  43466         0,
  43467         2,
  43468         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM83208_A0r_fields,
  43469         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43470         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43471         -1,
  43472         -1,
  43473     },
  43474 #endif /* chips */
  43475 
  43476 #if defined(BCM_88202_A0)
  43477     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88202_A0r */
  43478         soc_block_list[23],
  43479         soc_genreg,
  43480         1,
  43481         0,
  43482         0x90,
  43483         SOC_REG_FLAG_WO,
  43484         0,
  43485         2,
  43486         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88202_A0r_fields,
  43487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43488         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43489         -1,
  43490         -1,
  43491     },
  43492 #endif /* chips */
  43493 
  43494 #if defined(BCM_88375_A0)
  43495     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88375_A0r */
  43496         soc_block_list[23],
  43497         soc_genreg,
  43498         1,
  43499         0,
  43500         0x110,
  43501         SOC_REG_FLAG_WO,
  43502         0,
  43503         2,
  43504         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88375_A0r_fields,
  43505         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43506         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43507         -1,
  43508         -1,
  43509     },
  43510 #endif /* chips */
  43511 
  43512 #if defined(BCM_88375_B0)
  43513     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88375_B0r */
  43514         soc_block_list[23],
  43515         soc_genreg,
  43516         1,
  43517         0,
  43518         0x110,
  43519         SOC_REG_FLAG_WO,
  43520         0,
  43521         2,
  43522         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88375_B0r_fields,
  43523         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43524         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43525         -1,
  43526         -1,
  43527     },
  43528 #endif /* chips */
  43529 
  43530 #if defined(BCM_88470_A0)
  43531     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88470_A0r */
  43532         soc_block_list[23],
  43533         soc_genreg,
  43534         1,
  43535         0,
  43536         0x114,
  43537         SOC_REG_FLAG_WO,
  43538         0,
  43539         2,
  43540         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88470_A0r_fields,
  43541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43542         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43543         -1,
  43544         -1,
  43545     },
  43546 #endif /* chips */
  43547 
  43548 #if defined(BCM_88470_B0)
  43549     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88470_B0r */
  43550         soc_block_list[23],
  43551         soc_genreg,
  43552         1,
  43553         0,
  43554         0x114,
  43555         SOC_REG_FLAG_WO,
  43556         0,
  43557         2,
  43558         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88470_B0r_fields,
  43559         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43560         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43561         -1,
  43562         -1,
  43563     },
  43564 #endif /* chips */
  43565 
  43566 #if defined(BCM_88650_B0)
  43567     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88650_B0r */
  43568         soc_block_list[23],
  43569         soc_genreg,
  43570         1,
  43571         0,
  43572         0x90,
  43573         SOC_REG_FLAG_WO,
  43574         0,
  43575         2,
  43576         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88650_B0r_fields,
  43577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43578         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43579         -1,
  43580         -1,
  43581     },
  43582 #endif /* chips */
  43583 
  43584 #if defined(BCM_88660_A0)
  43585     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88660_A0r */
  43586         soc_block_list[23],
  43587         soc_genreg,
  43588         1,
  43589         0,
  43590         0x90,
  43591         SOC_REG_FLAG_WO,
  43592         0,
  43593         2,
  43594         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88660_A0r_fields,
  43595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43596         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43597         -1,
  43598         -1,
  43599     },
  43600 #endif /* chips */
  43601 
  43602 #if defined(BCM_88675_A0)
  43603     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88675_A0r */
  43604         soc_block_list[23],
  43605         soc_genreg,
  43606         1,
  43607         0,
  43608         0x110,
  43609         SOC_REG_FLAG_WO,
  43610         0,
  43611         2,
  43612         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88675_A0r_fields,
  43613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43614         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43615         -1,
  43616         -1,
  43617     },
  43618 #endif /* chips */
  43619 
  43620 #if defined(BCM_88675_B0)
  43621     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88675_B0r */
  43622         soc_block_list[23],
  43623         soc_genreg,
  43624         1,
  43625         0,
  43626         0x110,
  43627         SOC_REG_FLAG_WO,
  43628         0,
  43629         2,
  43630         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88675_B0r_fields,
  43631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43632         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43633         -1,
  43634         -1,
  43635     },
  43636 #endif /* chips */
  43637 
  43638 #if defined(BCM_88680_A0)
  43639     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88680_A0r */
  43640         soc_block_list[23],
  43641         soc_genreg,
  43642         1,
  43643         0,
  43644         0x110,
  43645         SOC_REG_FLAG_WO,
  43646         0,
  43647         2,
  43648         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88680_A0r_fields,
  43649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43650         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43651         -1,
  43652         -1,
  43653     },
  43654 #endif /* chips */
  43655 
  43656 #if defined(BCM_88690_A0)
  43657     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88690_A0r */
  43658         soc_block_list[23],
  43659         soc_genreg,
  43660         1,
  43661         0,
  43662         0x158,
  43663         SOC_REG_FLAG_WO,
  43664         0,
  43665         2,
  43666         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88690_A0r_fields,
  43667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43668         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43669         -1,
  43670         -1,
  43671     },
  43672 #endif /* chips */
  43673 
  43674 #if defined(BCM_88690_B0)
  43675     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88690_B0r */
  43676         soc_block_list[23],
  43677         soc_genreg,
  43678         1,
  43679         0,
  43680         0x158,
  43681         SOC_REG_FLAG_WO,
  43682         0,
  43683         2,
  43684         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88690_B0r_fields,
  43685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43686         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43687         -1,
  43688         -1,
  43689     },
  43690 #endif /* chips */
  43691 
  43692 #if defined(BCM_88790_A0)
  43693     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88790_A0r */
  43694         soc_block_list[23],
  43695         soc_genreg,
  43696         1,
  43697         0,
  43698         0x158,
  43699         SOC_REG_FLAG_WO,
  43700         0,
  43701         2,
  43702         soc_BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL_BCM88790_A0r_fields,
  43703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  43704         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  43705         -1,
  43706         -1,
  43707     },
  43708 #endif /* chips */
  43709 
  43710 #if defined(BCM_88650_A0)
  43711     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMERr */
  43712         soc_block_list[23],
  43713         soc_genreg,
  43714         1,
  43715         0,
  43716         0x91,
  43717         SOC_REG_FLAG_64_BITS |
  43718                           SOC_REG_FLAG_WO,
  43719         0,
  43720         4,
  43721         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMERr_fields,
  43722         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43724         -1,
  43725         -1,
  43726     },
  43727 #endif /* chips */
  43728 
  43729 #if defined(BCM_83208_A0)
  43730     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM83208_A0r */
  43731         soc_block_list[23],
  43732         soc_genreg,
  43733         1,
  43734         0,
  43735         0x125,
  43736         SOC_REG_FLAG_64_BITS |
  43737                           SOC_REG_FLAG_WO,
  43738         0,
  43739         4,
  43740         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM83208_A0r_fields,
  43741         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43743         -1,
  43744         -1,
  43745     },
  43746 #endif /* chips */
  43747 
  43748 #if defined(BCM_88202_A0)
  43749     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88202_A0r */
  43750         soc_block_list[23],
  43751         soc_genreg,
  43752         1,
  43753         0,
  43754         0x91,
  43755         SOC_REG_FLAG_64_BITS |
  43756                           SOC_REG_FLAG_WO,
  43757         0,
  43758         4,
  43759         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88202_A0r_fields,
  43760         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43762         -1,
  43763         -1,
  43764     },
  43765 #endif /* chips */
  43766 
  43767 #if defined(BCM_88375_A0)
  43768     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88375_A0r */
  43769         soc_block_list[23],
  43770         soc_genreg,
  43771         1,
  43772         0,
  43773         0x111,
  43774         SOC_REG_FLAG_64_BITS |
  43775                           SOC_REG_FLAG_WO,
  43776         0,
  43777         4,
  43778         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88375_A0r_fields,
  43779         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43781         -1,
  43782         -1,
  43783     },
  43784 #endif /* chips */
  43785 
  43786 #if defined(BCM_88375_B0)
  43787     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88375_B0r */
  43788         soc_block_list[23],
  43789         soc_genreg,
  43790         1,
  43791         0,
  43792         0x111,
  43793         SOC_REG_FLAG_64_BITS |
  43794                           SOC_REG_FLAG_WO,
  43795         0,
  43796         4,
  43797         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88375_B0r_fields,
  43798         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43799         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43800         -1,
  43801         -1,
  43802     },
  43803 #endif /* chips */
  43804 
  43805 #if defined(BCM_88470_A0)
  43806     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88470_A0r */
  43807         soc_block_list[23],
  43808         soc_genreg,
  43809         1,
  43810         0,
  43811         0x115,
  43812         SOC_REG_FLAG_64_BITS |
  43813                           SOC_REG_FLAG_WO,
  43814         0,
  43815         4,
  43816         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88470_A0r_fields,
  43817         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43819         -1,
  43820         -1,
  43821     },
  43822 #endif /* chips */
  43823 
  43824 #if defined(BCM_88470_B0)
  43825     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88470_B0r */
  43826         soc_block_list[23],
  43827         soc_genreg,
  43828         1,
  43829         0,
  43830         0x115,
  43831         SOC_REG_FLAG_64_BITS |
  43832                           SOC_REG_FLAG_WO,
  43833         0,
  43834         4,
  43835         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88470_B0r_fields,
  43836         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43837         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43838         -1,
  43839         -1,
  43840     },
  43841 #endif /* chips */
  43842 
  43843 #if defined(BCM_88650_B0)
  43844     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88650_B0r */
  43845         soc_block_list[23],
  43846         soc_genreg,
  43847         1,
  43848         0,
  43849         0x91,
  43850         SOC_REG_FLAG_64_BITS |
  43851                           SOC_REG_FLAG_WO,
  43852         0,
  43853         4,
  43854         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88650_B0r_fields,
  43855         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43857         -1,
  43858         -1,
  43859     },
  43860 #endif /* chips */
  43861 
  43862 #if defined(BCM_88660_A0)
  43863     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88660_A0r */
  43864         soc_block_list[23],
  43865         soc_genreg,
  43866         1,
  43867         0,
  43868         0x91,
  43869         SOC_REG_FLAG_64_BITS |
  43870                           SOC_REG_FLAG_WO,
  43871         0,
  43872         4,
  43873         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88660_A0r_fields,
  43874         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43876         -1,
  43877         -1,
  43878     },
  43879 #endif /* chips */
  43880 
  43881 #if defined(BCM_88675_A0)
  43882     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88675_A0r */
  43883         soc_block_list[23],
  43884         soc_genreg,
  43885         1,
  43886         0,
  43887         0x111,
  43888         SOC_REG_FLAG_64_BITS |
  43889                           SOC_REG_FLAG_WO,
  43890         0,
  43891         4,
  43892         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88675_A0r_fields,
  43893         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43894         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43895         -1,
  43896         -1,
  43897     },
  43898 #endif /* chips */
  43899 
  43900 #if defined(BCM_88675_B0)
  43901     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88675_B0r */
  43902         soc_block_list[23],
  43903         soc_genreg,
  43904         1,
  43905         0,
  43906         0x111,
  43907         SOC_REG_FLAG_64_BITS |
  43908                           SOC_REG_FLAG_WO,
  43909         0,
  43910         4,
  43911         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88675_B0r_fields,
  43912         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43914         -1,
  43915         -1,
  43916     },
  43917 #endif /* chips */
  43918 
  43919 #if defined(BCM_88680_A0)
  43920     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88680_A0r */
  43921         soc_block_list[23],
  43922         soc_genreg,
  43923         1,
  43924         0,
  43925         0x111,
  43926         SOC_REG_FLAG_64_BITS |
  43927                           SOC_REG_FLAG_WO,
  43928         0,
  43929         4,
  43930         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88680_A0r_fields,
  43931         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43932         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43933         -1,
  43934         -1,
  43935     },
  43936 #endif /* chips */
  43937 
  43938 #if defined(BCM_88690_A0)
  43939     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88690_A0r */
  43940         soc_block_list[23],
  43941         soc_genreg,
  43942         1,
  43943         0,
  43944         0x159,
  43945         SOC_REG_FLAG_64_BITS |
  43946                           SOC_REG_FLAG_WO,
  43947         0,
  43948         4,
  43949         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88690_A0r_fields,
  43950         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43952         -1,
  43953         -1,
  43954     },
  43955 #endif /* chips */
  43956 
  43957 #if defined(BCM_88690_B0)
  43958     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88690_B0r */
  43959         soc_block_list[23],
  43960         soc_genreg,
  43961         1,
  43962         0,
  43963         0x159,
  43964         SOC_REG_FLAG_64_BITS |
  43965                           SOC_REG_FLAG_WO,
  43966         0,
  43967         4,
  43968         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88690_B0r_fields,
  43969         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43971         -1,
  43972         -1,
  43973     },
  43974 #endif /* chips */
  43975 
  43976 #if defined(BCM_88790_A0)
  43977     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88790_A0r */
  43978         soc_block_list[23],
  43979         soc_genreg,
  43980         1,
  43981         0,
  43982         0x159,
  43983         SOC_REG_FLAG_64_BITS |
  43984                           SOC_REG_FLAG_WO,
  43985         0,
  43986         4,
  43987         soc_BRDC_FMAC_FMAL_STATISTICS_GTIMER_BCM88790_A0r_fields,
  43988         SOC_RESET_VAL_DEC(0x00000500, 0x00000001)
  43989         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  43990         -1,
  43991         -1,
  43992     },
  43993 #endif /* chips */
  43994 
  43995 #if defined(BCM_88650_A0)
  43996     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUTr */
  43997         soc_block_list[23],
  43998         soc_genreg,
  43999         1,
  44000         0,
  44001         0x94,
  44002         SOC_REG_FLAG_64_BITS |
  44003                           SOC_REG_FLAG_WO,
  44004         0,
  44005         2,
  44006         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUTr_fields,
  44007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44008         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  44009         -1,
  44010         -1,
  44011     },
  44012 #endif /* chips */
  44013 
  44014 #if defined(BCM_88202_A0)
  44015     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_BCM88202_A0r */
  44016         soc_block_list[23],
  44017         soc_genreg,
  44018         1,
  44019         0,
  44020         0x94,
  44021         SOC_REG_FLAG_64_BITS |
  44022                           SOC_REG_FLAG_WO,
  44023         0,
  44024         2,
  44025         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_BCM88202_A0r_fields,
  44026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44027         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  44028         -1,
  44029         -1,
  44030     },
  44031 #endif /* chips */
  44032 
  44033 #if defined(BCM_88650_B0)
  44034     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_BCM88650_B0r */
  44035         soc_block_list[23],
  44036         soc_genreg,
  44037         1,
  44038         0,
  44039         0x94,
  44040         SOC_REG_FLAG_64_BITS |
  44041                           SOC_REG_FLAG_WO,
  44042         0,
  44043         2,
  44044         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_BCM88650_B0r_fields,
  44045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44046         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  44047         -1,
  44048         -1,
  44049     },
  44050 #endif /* chips */
  44051 
  44052 #if defined(BCM_88660_A0)
  44053     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_BCM88660_A0r */
  44054         soc_block_list[23],
  44055         soc_genreg,
  44056         1,
  44057         0,
  44058         0x94,
  44059         SOC_REG_FLAG_64_BITS |
  44060                           SOC_REG_FLAG_WO,
  44061         0,
  44062         2,
  44063         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_BCM88660_A0r_fields,
  44064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  44065         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  44066         -1,
  44067         -1,
  44068     },
  44069 #endif /* chips */
  44070 
  44071 #if defined(BCM_88650_A0)
  44072     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROLr */
  44073         soc_block_list[23],
  44074         soc_genreg,
  44075         1,
  44076         0,
  44077         0x93,
  44078         SOC_REG_FLAG_WO,
  44079         0,
  44080         5,
  44081         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROLr_fields,
  44082         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44083         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44084         -1,
  44085         -1,
  44086     },
  44087 #endif /* chips */
  44088 
  44089 #if defined(BCM_83208_A0)
  44090     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM83208_A0r */
  44091         soc_block_list[23],
  44092         soc_genreg,
  44093         1,
  44094         0,
  44095         0x127,
  44096         SOC_REG_FLAG_WO,
  44097         0,
  44098         5,
  44099         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM83208_A0r_fields,
  44100         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44101         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44102         -1,
  44103         -1,
  44104     },
  44105 #endif /* chips */
  44106 
  44107 #if defined(BCM_88202_A0)
  44108     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88202_A0r */
  44109         soc_block_list[23],
  44110         soc_genreg,
  44111         1,
  44112         0,
  44113         0x93,
  44114         SOC_REG_FLAG_WO,
  44115         0,
  44116         5,
  44117         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88202_A0r_fields,
  44118         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44119         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44120         -1,
  44121         -1,
  44122     },
  44123 #endif /* chips */
  44124 
  44125 #if defined(BCM_88375_A0)
  44126     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88375_A0r */
  44127         soc_block_list[23],
  44128         soc_genreg,
  44129         1,
  44130         0,
  44131         0x113,
  44132         SOC_REG_FLAG_WO,
  44133         0,
  44134         5,
  44135         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88375_A0r_fields,
  44136         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44137         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44138         -1,
  44139         -1,
  44140     },
  44141 #endif /* chips */
  44142 
  44143 #if defined(BCM_88375_B0)
  44144     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88375_B0r */
  44145         soc_block_list[23],
  44146         soc_genreg,
  44147         1,
  44148         0,
  44149         0x113,
  44150         SOC_REG_FLAG_WO,
  44151         0,
  44152         5,
  44153         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88375_B0r_fields,
  44154         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44155         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44156         -1,
  44157         -1,
  44158     },
  44159 #endif /* chips */
  44160 
  44161 #if defined(BCM_88470_A0)
  44162     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88470_A0r */
  44163         soc_block_list[23],
  44164         soc_genreg,
  44165         1,
  44166         0,
  44167         0x117,
  44168         SOC_REG_FLAG_WO,
  44169         0,
  44170         5,
  44171         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88470_A0r_fields,
  44172         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44173         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44174         -1,
  44175         -1,
  44176     },
  44177 #endif /* chips */
  44178 
  44179 #if defined(BCM_88470_B0)
  44180     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88470_B0r */
  44181         soc_block_list[23],
  44182         soc_genreg,
  44183         1,
  44184         0,
  44185         0x117,
  44186         SOC_REG_FLAG_WO,
  44187         0,
  44188         5,
  44189         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88470_B0r_fields,
  44190         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44191         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44192         -1,
  44193         -1,
  44194     },
  44195 #endif /* chips */
  44196 
  44197 #if defined(BCM_88650_B0)
  44198     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88650_B0r */
  44199         soc_block_list[23],
  44200         soc_genreg,
  44201         1,
  44202         0,
  44203         0x93,
  44204         SOC_REG_FLAG_WO,
  44205         0,
  44206         5,
  44207         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88650_B0r_fields,
  44208         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44209         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44210         -1,
  44211         -1,
  44212     },
  44213 #endif /* chips */
  44214 
  44215 #if defined(BCM_88660_A0)
  44216     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88660_A0r */
  44217         soc_block_list[23],
  44218         soc_genreg,
  44219         1,
  44220         0,
  44221         0x93,
  44222         SOC_REG_FLAG_WO,
  44223         0,
  44224         5,
  44225         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88660_A0r_fields,
  44226         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44227         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  44228         -1,
  44229         -1,
  44230     },
  44231 #endif /* chips */
  44232 
  44233 #if defined(BCM_88675_A0)
  44234     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88675_A0r */
  44235         soc_block_list[23],
  44236         soc_genreg,
  44237         1,
  44238         0,
  44239         0x113,
  44240         SOC_REG_FLAG_WO,
  44241         0,
  44242         5,
  44243         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88675_A0r_fields,
  44244         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44245         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44246         -1,
  44247         -1,
  44248     },
  44249 #endif /* chips */
  44250 
  44251 #if defined(BCM_88675_B0)
  44252     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88675_B0r */
  44253         soc_block_list[23],
  44254         soc_genreg,
  44255         1,
  44256         0,
  44257         0x113,
  44258         SOC_REG_FLAG_WO,
  44259         0,
  44260         5,
  44261         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88675_B0r_fields,
  44262         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44263         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44264         -1,
  44265         -1,
  44266     },
  44267 #endif /* chips */
  44268 
  44269 #if defined(BCM_88680_A0)
  44270     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88680_A0r */
  44271         soc_block_list[23],
  44272         soc_genreg,
  44273         1,
  44274         0,
  44275         0x113,
  44276         SOC_REG_FLAG_WO,
  44277         0,
  44278         5,
  44279         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88680_A0r_fields,
  44280         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44281         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44282         -1,
  44283         -1,
  44284     },
  44285 #endif /* chips */
  44286 
  44287 #if defined(BCM_88690_A0)
  44288     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88690_A0r */
  44289         soc_block_list[23],
  44290         soc_genreg,
  44291         1,
  44292         0,
  44293         0x15b,
  44294         SOC_REG_FLAG_WO,
  44295         0,
  44296         5,
  44297         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88690_A0r_fields,
  44298         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44299         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44300         -1,
  44301         -1,
  44302     },
  44303 #endif /* chips */
  44304 
  44305 #if defined(BCM_88690_B0)
  44306     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88690_B0r */
  44307         soc_block_list[23],
  44308         soc_genreg,
  44309         1,
  44310         0,
  44311         0x15b,
  44312         SOC_REG_FLAG_WO,
  44313         0,
  44314         5,
  44315         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88690_B0r_fields,
  44316         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44317         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44318         -1,
  44319         -1,
  44320     },
  44321 #endif /* chips */
  44322 
  44323 #if defined(BCM_88790_A0)
  44324     { /* SOC_REG_INT_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88790_A0r */
  44325         soc_block_list[23],
  44326         soc_genreg,
  44327         1,
  44328         0,
  44329         0x15b,
  44330         SOC_REG_FLAG_WO,
  44331         0,
  44332         5,
  44333         soc_BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL_BCM88790_A0r_fields,
  44334         SOC_RESET_VAL_DEC(0x00000010, 0x00000000)
  44335         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  44336         -1,
  44337         -1,
  44338     },
  44339 #endif /* chips */
  44340 
  44341 #if defined(BCM_88675_A0)
  44342     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATIONr */
  44343         soc_block_list[23],
  44344         soc_genreg,
  44345         4,
  44346         0,
  44347         0x129,
  44348         SOC_REG_FLAG_ARRAY |
  44349                           SOC_REG_FLAG_WO |
  44350                           SOC_REG_FLAG_REG_ARRAY,
  44351         0,
  44352         6,
  44353         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATIONr_fields,
  44354         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44355         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44356         -1,
  44357         -1,
  44358     },
  44359 #endif /* chips */
  44360 
  44361 #if defined(BCM_83208_A0)
  44362     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM83208_A0r */
  44363         soc_block_list[23],
  44364         soc_genreg,
  44365         4,
  44366         0,
  44367         0x13e,
  44368         SOC_REG_FLAG_ARRAY |
  44369                           SOC_REG_FLAG_WO |
  44370                           SOC_REG_FLAG_REG_ARRAY,
  44371         0,
  44372         6,
  44373         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM83208_A0r_fields,
  44374         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44375         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44376         -1,
  44377         -1,
  44378     },
  44379 #endif /* chips */
  44380 
  44381 #if defined(BCM_88375_A0)
  44382     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88375_A0r */
  44383         soc_block_list[23],
  44384         soc_genreg,
  44385         4,
  44386         0,
  44387         0x129,
  44388         SOC_REG_FLAG_ARRAY |
  44389                           SOC_REG_FLAG_WO |
  44390                           SOC_REG_FLAG_REG_ARRAY,
  44391         0,
  44392         6,
  44393         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88375_A0r_fields,
  44394         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44395         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44396         -1,
  44397         -1,
  44398     },
  44399 #endif /* chips */
  44400 
  44401 #if defined(BCM_88375_B0)
  44402     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88375_B0r */
  44403         soc_block_list[23],
  44404         soc_genreg,
  44405         4,
  44406         0,
  44407         0x129,
  44408         SOC_REG_FLAG_ARRAY |
  44409                           SOC_REG_FLAG_WO |
  44410                           SOC_REG_FLAG_REG_ARRAY,
  44411         0,
  44412         6,
  44413         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88375_B0r_fields,
  44414         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44415         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44416         -1,
  44417         -1,
  44418     },
  44419 #endif /* chips */
  44420 
  44421 #if defined(BCM_88470_A0)
  44422     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88470_A0r */
  44423         soc_block_list[23],
  44424         soc_genreg,
  44425         4,
  44426         0,
  44427         0x131,
  44428         SOC_REG_FLAG_ARRAY |
  44429                           SOC_REG_FLAG_WO |
  44430                           SOC_REG_FLAG_REG_ARRAY,
  44431         0,
  44432         6,
  44433         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88470_A0r_fields,
  44434         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44435         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44436         -1,
  44437         -1,
  44438     },
  44439 #endif /* chips */
  44440 
  44441 #if defined(BCM_88470_B0)
  44442     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88470_B0r */
  44443         soc_block_list[23],
  44444         soc_genreg,
  44445         4,
  44446         0,
  44447         0x131,
  44448         SOC_REG_FLAG_ARRAY |
  44449                           SOC_REG_FLAG_WO |
  44450                           SOC_REG_FLAG_REG_ARRAY,
  44451         0,
  44452         6,
  44453         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88470_B0r_fields,
  44454         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44455         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44456         -1,
  44457         -1,
  44458     },
  44459 #endif /* chips */
  44460 
  44461 #if defined(BCM_88675_B0)
  44462     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88675_B0r */
  44463         soc_block_list[23],
  44464         soc_genreg,
  44465         4,
  44466         0,
  44467         0x129,
  44468         SOC_REG_FLAG_ARRAY |
  44469                           SOC_REG_FLAG_WO |
  44470                           SOC_REG_FLAG_REG_ARRAY,
  44471         0,
  44472         6,
  44473         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88675_B0r_fields,
  44474         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44475         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44476         -1,
  44477         -1,
  44478     },
  44479 #endif /* chips */
  44480 
  44481 #if defined(BCM_88680_A0)
  44482     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88680_A0r */
  44483         soc_block_list[23],
  44484         soc_genreg,
  44485         4,
  44486         0,
  44487         0x129,
  44488         SOC_REG_FLAG_ARRAY |
  44489                           SOC_REG_FLAG_WO |
  44490                           SOC_REG_FLAG_REG_ARRAY,
  44491         0,
  44492         6,
  44493         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88680_A0r_fields,
  44494         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44495         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44496         -1,
  44497         -1,
  44498     },
  44499 #endif /* chips */
  44500 
  44501 #if defined(BCM_88690_A0)
  44502     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88690_A0r */
  44503         soc_block_list[23],
  44504         soc_genreg,
  44505         4,
  44506         0,
  44507         0x17a,
  44508         SOC_REG_FLAG_ARRAY |
  44509                           SOC_REG_FLAG_WO |
  44510                           SOC_REG_FLAG_REG_ARRAY,
  44511         0,
  44512         6,
  44513         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88690_A0r_fields,
  44514         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44515         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44516         -1,
  44517         -1,
  44518     },
  44519 #endif /* chips */
  44520 
  44521 #if defined(BCM_88690_B0)
  44522     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88690_B0r */
  44523         soc_block_list[23],
  44524         soc_genreg,
  44525         4,
  44526         0,
  44527         0x17a,
  44528         SOC_REG_FLAG_ARRAY |
  44529                           SOC_REG_FLAG_WO |
  44530                           SOC_REG_FLAG_REG_ARRAY,
  44531         0,
  44532         6,
  44533         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88690_B0r_fields,
  44534         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44535         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44536         -1,
  44537         -1,
  44538     },
  44539 #endif /* chips */
  44540 
  44541 #if defined(BCM_88790_A0)
  44542     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88790_A0r */
  44543         soc_block_list[23],
  44544         soc_genreg,
  44545         4,
  44546         0,
  44547         0x17a,
  44548         SOC_REG_FLAG_ARRAY |
  44549                           SOC_REG_FLAG_WO |
  44550                           SOC_REG_FLAG_REG_ARRAY,
  44551         0,
  44552         6,
  44553         soc_BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION_BCM88790_A0r_fields,
  44554         SOC_RESET_VAL_DEC(0x00a0e507, 0x00000000)
  44555         SOC_RESET_MASK_DEC(0x9fffffff, 0x00000000)
  44556         -1,
  44557         -1,
  44558     },
  44559 #endif /* chips */
  44560 
  44561 #if defined(BCM_88675_A0)
  44562     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATIONr */
  44563         soc_block_list[23],
  44564         soc_genreg,
  44565         4,
  44566         0,
  44567         0x12d,
  44568         SOC_REG_FLAG_ARRAY |
  44569                           SOC_REG_FLAG_WO |
  44570                           SOC_REG_FLAG_REG_ARRAY,
  44571         0,
  44572         2,
  44573         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATIONr_fields,
  44574         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44575         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44576         -1,
  44577         -1,
  44578     },
  44579 #endif /* chips */
  44580 
  44581 #if defined(BCM_83208_A0)
  44582     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM83208_A0r */
  44583         soc_block_list[23],
  44584         soc_genreg,
  44585         4,
  44586         0,
  44587         0x142,
  44588         SOC_REG_FLAG_ARRAY |
  44589                           SOC_REG_FLAG_WO |
  44590                           SOC_REG_FLAG_REG_ARRAY,
  44591         0,
  44592         2,
  44593         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM83208_A0r_fields,
  44594         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44595         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44596         -1,
  44597         -1,
  44598     },
  44599 #endif /* chips */
  44600 
  44601 #if defined(BCM_88375_A0)
  44602     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88375_A0r */
  44603         soc_block_list[23],
  44604         soc_genreg,
  44605         4,
  44606         0,
  44607         0x12d,
  44608         SOC_REG_FLAG_ARRAY |
  44609                           SOC_REG_FLAG_WO |
  44610                           SOC_REG_FLAG_REG_ARRAY,
  44611         0,
  44612         2,
  44613         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88375_A0r_fields,
  44614         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44615         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44616         -1,
  44617         -1,
  44618     },
  44619 #endif /* chips */
  44620 
  44621 #if defined(BCM_88375_B0)
  44622     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88375_B0r */
  44623         soc_block_list[23],
  44624         soc_genreg,
  44625         4,
  44626         0,
  44627         0x12d,
  44628         SOC_REG_FLAG_ARRAY |
  44629                           SOC_REG_FLAG_WO |
  44630                           SOC_REG_FLAG_REG_ARRAY,
  44631         0,
  44632         2,
  44633         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88375_B0r_fields,
  44634         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44635         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44636         -1,
  44637         -1,
  44638     },
  44639 #endif /* chips */
  44640 
  44641 #if defined(BCM_88470_A0)
  44642     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88470_A0r */
  44643         soc_block_list[23],
  44644         soc_genreg,
  44645         4,
  44646         0,
  44647         0x135,
  44648         SOC_REG_FLAG_ARRAY |
  44649                           SOC_REG_FLAG_WO |
  44650                           SOC_REG_FLAG_REG_ARRAY,
  44651         0,
  44652         2,
  44653         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88470_A0r_fields,
  44654         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44655         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44656         -1,
  44657         -1,
  44658     },
  44659 #endif /* chips */
  44660 
  44661 #if defined(BCM_88470_B0)
  44662     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88470_B0r */
  44663         soc_block_list[23],
  44664         soc_genreg,
  44665         4,
  44666         0,
  44667         0x135,
  44668         SOC_REG_FLAG_ARRAY |
  44669                           SOC_REG_FLAG_WO |
  44670                           SOC_REG_FLAG_REG_ARRAY,
  44671         0,
  44672         2,
  44673         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88470_B0r_fields,
  44674         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44675         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44676         -1,
  44677         -1,
  44678     },
  44679 #endif /* chips */
  44680 
  44681 #if defined(BCM_88675_B0)
  44682     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88675_B0r */
  44683         soc_block_list[23],
  44684         soc_genreg,
  44685         4,
  44686         0,
  44687         0x12d,
  44688         SOC_REG_FLAG_ARRAY |
  44689                           SOC_REG_FLAG_WO |
  44690                           SOC_REG_FLAG_REG_ARRAY,
  44691         0,
  44692         2,
  44693         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88675_B0r_fields,
  44694         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44695         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44696         -1,
  44697         -1,
  44698     },
  44699 #endif /* chips */
  44700 
  44701 #if defined(BCM_88680_A0)
  44702     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88680_A0r */
  44703         soc_block_list[23],
  44704         soc_genreg,
  44705         4,
  44706         0,
  44707         0x12d,
  44708         SOC_REG_FLAG_ARRAY |
  44709                           SOC_REG_FLAG_WO |
  44710                           SOC_REG_FLAG_REG_ARRAY,
  44711         0,
  44712         2,
  44713         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88680_A0r_fields,
  44714         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  44715         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44716         -1,
  44717         -1,
  44718     },
  44719 #endif /* chips */
  44720 
  44721 #if defined(BCM_88690_A0)
  44722     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88690_A0r */
  44723         soc_block_list[23],
  44724         soc_genreg,
  44725         4,
  44726         0,
  44727         0x17e,
  44728         SOC_REG_FLAG_ARRAY |
  44729                           SOC_REG_FLAG_WO |
  44730                           SOC_REG_FLAG_REG_ARRAY,
  44731         0,
  44732         2,
  44733         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88690_A0r_fields,
  44734         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  44735         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44736         -1,
  44737         -1,
  44738     },
  44739 #endif /* chips */
  44740 
  44741 #if defined(BCM_88690_B0)
  44742     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88690_B0r */
  44743         soc_block_list[23],
  44744         soc_genreg,
  44745         4,
  44746         0,
  44747         0x17e,
  44748         SOC_REG_FLAG_ARRAY |
  44749                           SOC_REG_FLAG_WO |
  44750                           SOC_REG_FLAG_REG_ARRAY,
  44751         0,
  44752         2,
  44753         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88690_B0r_fields,
  44754         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  44755         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44756         -1,
  44757         -1,
  44758     },
  44759 #endif /* chips */
  44760 
  44761 #if defined(BCM_88790_A0)
  44762     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88790_A0r */
  44763         soc_block_list[23],
  44764         soc_genreg,
  44765         4,
  44766         0,
  44767         0x17e,
  44768         SOC_REG_FLAG_ARRAY |
  44769                           SOC_REG_FLAG_WO |
  44770                           SOC_REG_FLAG_REG_ARRAY,
  44771         0,
  44772         2,
  44773         soc_BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION_BCM88790_A0r_fields,
  44774         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  44775         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  44776         -1,
  44777         -1,
  44778     },
  44779 #endif /* chips */
  44780 
  44781 #if defined(BCM_88790_A0)
  44782     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_DC_AUTO_ADJUSTr */
  44783         soc_block_list[23],
  44784         soc_genreg,
  44785         4,
  44786         0,
  44787         0x140,
  44788         SOC_REG_FLAG_64_BITS |
  44789                           SOC_REG_FLAG_ARRAY |
  44790                           SOC_REG_FLAG_WO |
  44791                           SOC_REG_FLAG_REG_ARRAY,
  44792         0,
  44793         8,
  44794         soc_BRDC_FMAC_FMAL_TX_DC_AUTO_ADJUSTr_fields,
  44795         SOC_RESET_VAL_DEC(0x003e8094, 0x00000000)
  44796         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  44797         -1,
  44798         -1,
  44799     },
  44800 #endif /* chips */
  44801 
  44802 #if defined(BCM_88690_A0)
  44803     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_DC_AUTO_ADJUST_BCM88690_A0r */
  44804         soc_block_list[23],
  44805         soc_genreg,
  44806         4,
  44807         0,
  44808         0x140,
  44809         SOC_REG_FLAG_64_BITS |
  44810                           SOC_REG_FLAG_ARRAY |
  44811                           SOC_REG_FLAG_WO |
  44812                           SOC_REG_FLAG_REG_ARRAY,
  44813         0,
  44814         8,
  44815         soc_BRDC_FMAC_FMAL_TX_DC_AUTO_ADJUST_BCM88690_A0r_fields,
  44816         SOC_RESET_VAL_DEC(0x003e8094, 0x00000000)
  44817         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  44818         -1,
  44819         -1,
  44820     },
  44821 #endif /* chips */
  44822 
  44823 #if defined(BCM_88690_B0)
  44824     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_DC_AUTO_ADJUST_BCM88690_B0r */
  44825         soc_block_list[23],
  44826         soc_genreg,
  44827         4,
  44828         0,
  44829         0x140,
  44830         SOC_REG_FLAG_64_BITS |
  44831                           SOC_REG_FLAG_ARRAY |
  44832                           SOC_REG_FLAG_WO |
  44833                           SOC_REG_FLAG_REG_ARRAY,
  44834         0,
  44835         8,
  44836         soc_BRDC_FMAC_FMAL_TX_DC_AUTO_ADJUST_BCM88690_B0r_fields,
  44837         SOC_RESET_VAL_DEC(0x003e8094, 0x00000000)
  44838         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  44839         -1,
  44840         -1,
  44841     },
  44842 #endif /* chips */
  44843 
  44844 #if defined(BCM_88675_A0)
  44845     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATIONr */
  44846         soc_block_list[23],
  44847         soc_genreg,
  44848         4,
  44849         0,
  44850         0x121,
  44851         SOC_REG_FLAG_ARRAY |
  44852                           SOC_REG_FLAG_WO |
  44853                           SOC_REG_FLAG_REG_ARRAY,
  44854         0,
  44855         11,
  44856         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATIONr_fields,
  44857         SOC_RESET_VAL_DEC(0x04060008, 0x00000000)
  44858         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44859         -1,
  44860         -1,
  44861     },
  44862 #endif /* chips */
  44863 
  44864 #if defined(BCM_83208_A0)
  44865     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM83208_A0r */
  44866         soc_block_list[23],
  44867         soc_genreg,
  44868         4,
  44869         0,
  44870         0x136,
  44871         SOC_REG_FLAG_ARRAY |
  44872                           SOC_REG_FLAG_WO |
  44873                           SOC_REG_FLAG_REG_ARRAY,
  44874         0,
  44875         11,
  44876         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM83208_A0r_fields,
  44877         SOC_RESET_VAL_DEC(0x01060008, 0x00000000)
  44878         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  44879         -1,
  44880         -1,
  44881     },
  44882 #endif /* chips */
  44883 
  44884 #if defined(BCM_88375_A0)
  44885     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88375_A0r */
  44886         soc_block_list[23],
  44887         soc_genreg,
  44888         4,
  44889         0,
  44890         0x121,
  44891         SOC_REG_FLAG_ARRAY |
  44892                           SOC_REG_FLAG_WO |
  44893                           SOC_REG_FLAG_REG_ARRAY,
  44894         0,
  44895         11,
  44896         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88375_A0r_fields,
  44897         SOC_RESET_VAL_DEC(0x04060008, 0x00000000)
  44898         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44899         -1,
  44900         -1,
  44901     },
  44902 #endif /* chips */
  44903 
  44904 #if defined(BCM_88375_B0)
  44905     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88375_B0r */
  44906         soc_block_list[23],
  44907         soc_genreg,
  44908         4,
  44909         0,
  44910         0x121,
  44911         SOC_REG_FLAG_ARRAY |
  44912                           SOC_REG_FLAG_WO |
  44913                           SOC_REG_FLAG_REG_ARRAY,
  44914         0,
  44915         11,
  44916         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88375_B0r_fields,
  44917         SOC_RESET_VAL_DEC(0x04060008, 0x00000000)
  44918         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44919         -1,
  44920         -1,
  44921     },
  44922 #endif /* chips */
  44923 
  44924 #if defined(BCM_88470_A0)
  44925     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88470_A0r */
  44926         soc_block_list[23],
  44927         soc_genreg,
  44928         4,
  44929         0,
  44930         0x125,
  44931         SOC_REG_FLAG_64_BITS |
  44932                           SOC_REG_FLAG_ARRAY |
  44933                           SOC_REG_FLAG_WO |
  44934                           SOC_REG_FLAG_REG_ARRAY,
  44935         0,
  44936         11,
  44937         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88470_A0r_fields,
  44938         SOC_RESET_VAL_DEC(0x08060008, 0x00000000)
  44939         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  44940         -1,
  44941         -1,
  44942     },
  44943 #endif /* chips */
  44944 
  44945 #if defined(BCM_88470_B0)
  44946     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88470_B0r */
  44947         soc_block_list[23],
  44948         soc_genreg,
  44949         4,
  44950         0,
  44951         0x125,
  44952         SOC_REG_FLAG_64_BITS |
  44953                           SOC_REG_FLAG_ARRAY |
  44954                           SOC_REG_FLAG_WO |
  44955                           SOC_REG_FLAG_REG_ARRAY,
  44956         0,
  44957         11,
  44958         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88470_B0r_fields,
  44959         SOC_RESET_VAL_DEC(0x08060008, 0x00000000)
  44960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  44961         -1,
  44962         -1,
  44963     },
  44964 #endif /* chips */
  44965 
  44966 #if defined(BCM_88675_B0)
  44967     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88675_B0r */
  44968         soc_block_list[23],
  44969         soc_genreg,
  44970         4,
  44971         0,
  44972         0x121,
  44973         SOC_REG_FLAG_ARRAY |
  44974                           SOC_REG_FLAG_WO |
  44975                           SOC_REG_FLAG_REG_ARRAY,
  44976         0,
  44977         11,
  44978         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88675_B0r_fields,
  44979         SOC_RESET_VAL_DEC(0x04060008, 0x00000000)
  44980         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  44981         -1,
  44982         -1,
  44983     },
  44984 #endif /* chips */
  44985 
  44986 #if defined(BCM_88680_A0)
  44987     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88680_A0r */
  44988         soc_block_list[23],
  44989         soc_genreg,
  44990         4,
  44991         0,
  44992         0x121,
  44993         SOC_REG_FLAG_ARRAY |
  44994                           SOC_REG_FLAG_WO |
  44995                           SOC_REG_FLAG_REG_ARRAY,
  44996         0,
  44997         11,
  44998         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88680_A0r_fields,
  44999         SOC_RESET_VAL_DEC(0x04060008, 0x00000000)
  45000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45001         -1,
  45002         -1,
  45003     },
  45004 #endif /* chips */
  45005 
  45006 #if defined(BCM_88690_A0)
  45007     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88690_A0r */
  45008         soc_block_list[23],
  45009         soc_genreg,
  45010         4,
  45011         0,
  45012         0x16e,
  45013         SOC_REG_FLAG_64_BITS |
  45014                           SOC_REG_FLAG_ARRAY |
  45015                           SOC_REG_FLAG_WO |
  45016                           SOC_REG_FLAG_REG_ARRAY,
  45017         0,
  45018         12,
  45019         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88690_A0r_fields,
  45020         SOC_RESET_VAL_DEC(0x00450008, 0x00000080)
  45021         SOC_RESET_MASK_DEC(0xffffffff, 0x00003fff)
  45022         -1,
  45023         -1,
  45024     },
  45025 #endif /* chips */
  45026 
  45027 #if defined(BCM_88690_B0)
  45028     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88690_B0r */
  45029         soc_block_list[23],
  45030         soc_genreg,
  45031         4,
  45032         0,
  45033         0x16e,
  45034         SOC_REG_FLAG_64_BITS |
  45035                           SOC_REG_FLAG_ARRAY |
  45036                           SOC_REG_FLAG_WO |
  45037                           SOC_REG_FLAG_REG_ARRAY,
  45038         0,
  45039         12,
  45040         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88690_B0r_fields,
  45041         SOC_RESET_VAL_DEC(0x00450008, 0x00000080)
  45042         SOC_RESET_MASK_DEC(0xffffffff, 0x00003fff)
  45043         -1,
  45044         -1,
  45045     },
  45046 #endif /* chips */
  45047 
  45048 #if defined(BCM_88790_A0)
  45049     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88790_A0r */
  45050         soc_block_list[23],
  45051         soc_genreg,
  45052         4,
  45053         0,
  45054         0x16e,
  45055         SOC_REG_FLAG_64_BITS |
  45056                           SOC_REG_FLAG_ARRAY |
  45057                           SOC_REG_FLAG_WO |
  45058                           SOC_REG_FLAG_REG_ARRAY,
  45059         0,
  45060         12,
  45061         soc_BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION_BCM88790_A0r_fields,
  45062         SOC_RESET_VAL_DEC(0x00450008, 0x00000080)
  45063         SOC_RESET_MASK_DEC(0xffffffff, 0x00003fff)
  45064         -1,
  45065         -1,
  45066     },
  45067 #endif /* chips */
  45068 
  45069 #if defined(BCM_88790_A0)
  45070     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_SIMPLE_UNPACKING_CNTr */
  45071         soc_block_list[23],
  45072         soc_genreg,
  45073         4,
  45074         0,
  45075         0x15e,
  45076         SOC_REG_FLAG_ARRAY |
  45077                           SOC_REG_FLAG_RO |
  45078                           SOC_REG_FLAG_WO |
  45079                           SOC_REG_FLAG_REG_ARRAY,
  45080         SOC_REG_FLAG_COUNTER_FEILDS,
  45081         1,
  45082         soc_BRDC_FMAC_FMAL_TX_SIMPLE_UNPACKING_CNTr_fields,
  45083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45084         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  45085         -1,
  45086         -1,
  45087     },
  45088 #endif /* chips */
  45089 
  45090 #if defined(BCM_88690_A0)
  45091     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_SIMPLE_UNPACKING_CNT_BCM88690_A0r */
  45092         soc_block_list[23],
  45093         soc_genreg,
  45094         4,
  45095         0,
  45096         0x15e,
  45097         SOC_REG_FLAG_ARRAY |
  45098                           SOC_REG_FLAG_RO |
  45099                           SOC_REG_FLAG_WO |
  45100                           SOC_REG_FLAG_REG_ARRAY,
  45101         SOC_REG_FLAG_COUNTER_FEILDS,
  45102         1,
  45103         soc_BRDC_FMAC_FMAL_TX_SIMPLE_UNPACKING_CNT_BCM88690_A0r_fields,
  45104         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45105         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  45106         -1,
  45107         -1,
  45108     },
  45109 #endif /* chips */
  45110 
  45111 #if defined(BCM_88690_B0)
  45112     { /* SOC_REG_INT_BRDC_FMAC_FMAL_TX_SIMPLE_UNPACKING_CNT_BCM88690_B0r */
  45113         soc_block_list[23],
  45114         soc_genreg,
  45115         4,
  45116         0,
  45117         0x15e,
  45118         SOC_REG_FLAG_ARRAY |
  45119                           SOC_REG_FLAG_RO |
  45120                           SOC_REG_FLAG_WO |
  45121                           SOC_REG_FLAG_REG_ARRAY,
  45122         SOC_REG_FLAG_COUNTER_FEILDS,
  45123         1,
  45124         soc_BRDC_FMAC_FMAL_TX_SIMPLE_UNPACKING_CNT_BCM88690_B0r_fields,
  45125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  45126         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  45127         -1,
  45128         -1,
  45129     },
  45130 #endif /* chips */
  45131 
  45132 #if defined(BCM_88650_A0)
  45133     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BERr */
  45134         soc_block_list[23],
  45135         soc_genreg,
  45136         4,
  45137         0,
  45138         0xf0,
  45139         SOC_REG_FLAG_ARRAY |
  45140                           SOC_REG_FLAG_WO |
  45141                           SOC_REG_FLAG_REG_ARRAY,
  45142         0,
  45143         6,
  45144         soc_BRDC_FMAC_FPS_CONFIGURATION_BERr_fields,
  45145         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45146         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45147         -1,
  45148         -1,
  45149     },
  45150 #endif /* chips */
  45151 
  45152 #if defined(BCM_83208_A0)
  45153     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM83208_A0r */
  45154         soc_block_list[23],
  45155         soc_genreg,
  45156         4,
  45157         0,
  45158         0x152,
  45159         SOC_REG_FLAG_ARRAY |
  45160                           SOC_REG_FLAG_WO |
  45161                           SOC_REG_FLAG_REG_ARRAY,
  45162         0,
  45163         6,
  45164         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM83208_A0r_fields,
  45165         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45166         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45167         -1,
  45168         -1,
  45169     },
  45170 #endif /* chips */
  45171 
  45172 #if defined(BCM_88202_A0)
  45173     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88202_A0r */
  45174         soc_block_list[23],
  45175         soc_genreg,
  45176         4,
  45177         0,
  45178         0xf0,
  45179         SOC_REG_FLAG_ARRAY |
  45180                           SOC_REG_FLAG_WO |
  45181                           SOC_REG_FLAG_REG_ARRAY,
  45182         0,
  45183         6,
  45184         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88202_A0r_fields,
  45185         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45186         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45187         -1,
  45188         -1,
  45189     },
  45190 #endif /* chips */
  45191 
  45192 #if defined(BCM_88375_A0)
  45193     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88375_A0r */
  45194         soc_block_list[23],
  45195         soc_genreg,
  45196         4,
  45197         0,
  45198         0x13d,
  45199         SOC_REG_FLAG_ARRAY |
  45200                           SOC_REG_FLAG_WO |
  45201                           SOC_REG_FLAG_REG_ARRAY,
  45202         0,
  45203         6,
  45204         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88375_A0r_fields,
  45205         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45206         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45207         -1,
  45208         -1,
  45209     },
  45210 #endif /* chips */
  45211 
  45212 #if defined(BCM_88375_B0)
  45213     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88375_B0r */
  45214         soc_block_list[23],
  45215         soc_genreg,
  45216         4,
  45217         0,
  45218         0x13d,
  45219         SOC_REG_FLAG_ARRAY |
  45220                           SOC_REG_FLAG_WO |
  45221                           SOC_REG_FLAG_REG_ARRAY,
  45222         0,
  45223         6,
  45224         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88375_B0r_fields,
  45225         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45226         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45227         -1,
  45228         -1,
  45229     },
  45230 #endif /* chips */
  45231 
  45232 #if defined(BCM_88470_A0)
  45233     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88470_A0r */
  45234         soc_block_list[23],
  45235         soc_genreg,
  45236         4,
  45237         0,
  45238         0x13d,
  45239         SOC_REG_FLAG_ARRAY |
  45240                           SOC_REG_FLAG_WO |
  45241                           SOC_REG_FLAG_REG_ARRAY,
  45242         0,
  45243         6,
  45244         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88470_A0r_fields,
  45245         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45246         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45247         -1,
  45248         -1,
  45249     },
  45250 #endif /* chips */
  45251 
  45252 #if defined(BCM_88470_B0)
  45253     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88470_B0r */
  45254         soc_block_list[23],
  45255         soc_genreg,
  45256         4,
  45257         0,
  45258         0x13d,
  45259         SOC_REG_FLAG_ARRAY |
  45260                           SOC_REG_FLAG_WO |
  45261                           SOC_REG_FLAG_REG_ARRAY,
  45262         0,
  45263         6,
  45264         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88470_B0r_fields,
  45265         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45266         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45267         -1,
  45268         -1,
  45269     },
  45270 #endif /* chips */
  45271 
  45272 #if defined(BCM_88650_B0)
  45273     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88650_B0r */
  45274         soc_block_list[23],
  45275         soc_genreg,
  45276         4,
  45277         0,
  45278         0xf0,
  45279         SOC_REG_FLAG_ARRAY |
  45280                           SOC_REG_FLAG_WO |
  45281                           SOC_REG_FLAG_REG_ARRAY,
  45282         0,
  45283         6,
  45284         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88650_B0r_fields,
  45285         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45286         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45287         -1,
  45288         -1,
  45289     },
  45290 #endif /* chips */
  45291 
  45292 #if defined(BCM_88660_A0)
  45293     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88660_A0r */
  45294         soc_block_list[23],
  45295         soc_genreg,
  45296         4,
  45297         0,
  45298         0xf0,
  45299         SOC_REG_FLAG_ARRAY |
  45300                           SOC_REG_FLAG_WO |
  45301                           SOC_REG_FLAG_REG_ARRAY,
  45302         0,
  45303         6,
  45304         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88660_A0r_fields,
  45305         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45306         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45307         -1,
  45308         -1,
  45309     },
  45310 #endif /* chips */
  45311 
  45312 #if defined(BCM_88675_A0)
  45313     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88675_A0r */
  45314         soc_block_list[23],
  45315         soc_genreg,
  45316         4,
  45317         0,
  45318         0x13d,
  45319         SOC_REG_FLAG_ARRAY |
  45320                           SOC_REG_FLAG_WO |
  45321                           SOC_REG_FLAG_REG_ARRAY,
  45322         0,
  45323         6,
  45324         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88675_A0r_fields,
  45325         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45326         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45327         -1,
  45328         -1,
  45329     },
  45330 #endif /* chips */
  45331 
  45332 #if defined(BCM_88675_B0)
  45333     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88675_B0r */
  45334         soc_block_list[23],
  45335         soc_genreg,
  45336         4,
  45337         0,
  45338         0x13d,
  45339         SOC_REG_FLAG_ARRAY |
  45340                           SOC_REG_FLAG_WO |
  45341                           SOC_REG_FLAG_REG_ARRAY,
  45342         0,
  45343         6,
  45344         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88675_B0r_fields,
  45345         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45346         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45347         -1,
  45348         -1,
  45349     },
  45350 #endif /* chips */
  45351 
  45352 #if defined(BCM_88680_A0)
  45353     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88680_A0r */
  45354         soc_block_list[23],
  45355         soc_genreg,
  45356         4,
  45357         0,
  45358         0x13d,
  45359         SOC_REG_FLAG_ARRAY |
  45360                           SOC_REG_FLAG_WO |
  45361                           SOC_REG_FLAG_REG_ARRAY,
  45362         0,
  45363         6,
  45364         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88680_A0r_fields,
  45365         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45366         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45367         -1,
  45368         -1,
  45369     },
  45370 #endif /* chips */
  45371 
  45372 #if defined(BCM_88690_A0)
  45373     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88690_A0r */
  45374         soc_block_list[23],
  45375         soc_genreg,
  45376         4,
  45377         0,
  45378         0x18e,
  45379         SOC_REG_FLAG_ARRAY |
  45380                           SOC_REG_FLAG_WO |
  45381                           SOC_REG_FLAG_REG_ARRAY,
  45382         0,
  45383         6,
  45384         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88690_A0r_fields,
  45385         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45386         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45387         -1,
  45388         -1,
  45389     },
  45390 #endif /* chips */
  45391 
  45392 #if defined(BCM_88690_B0)
  45393     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88690_B0r */
  45394         soc_block_list[23],
  45395         soc_genreg,
  45396         4,
  45397         0,
  45398         0x18e,
  45399         SOC_REG_FLAG_ARRAY |
  45400                           SOC_REG_FLAG_WO |
  45401                           SOC_REG_FLAG_REG_ARRAY,
  45402         0,
  45403         6,
  45404         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88690_B0r_fields,
  45405         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45406         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45407         -1,
  45408         -1,
  45409     },
  45410 #endif /* chips */
  45411 
  45412 #if defined(BCM_88790_A0)
  45413     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88790_A0r */
  45414         soc_block_list[23],
  45415         soc_genreg,
  45416         4,
  45417         0,
  45418         0x18e,
  45419         SOC_REG_FLAG_ARRAY |
  45420                           SOC_REG_FLAG_WO |
  45421                           SOC_REG_FLAG_REG_ARRAY,
  45422         0,
  45423         6,
  45424         soc_BRDC_FMAC_FPS_CONFIGURATION_BER_BCM88790_A0r_fields,
  45425         SOC_RESET_VAL_DEC(0x00007d90, 0x00000000)
  45426         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  45427         -1,
  45428         -1,
  45429     },
  45430 #endif /* chips */
  45431 
  45432 #if defined(BCM_88650_A0)
  45433     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNCr */
  45434         soc_block_list[23],
  45435         soc_genreg,
  45436         4,
  45437         0,
  45438         0x100,
  45439         SOC_REG_FLAG_ARRAY |
  45440                           SOC_REG_FLAG_WO |
  45441                           SOC_REG_FLAG_REG_ARRAY,
  45442         0,
  45443         7,
  45444         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNCr_fields,
  45445         SOC_RESET_VAL_DEC(0x0001c7bf, 0x00000000)
  45446         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45447         -1,
  45448         -1,
  45449     },
  45450 #endif /* chips */
  45451 
  45452 #if defined(BCM_83208_A0)
  45453     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM83208_A0r */
  45454         soc_block_list[23],
  45455         soc_genreg,
  45456         4,
  45457         0,
  45458         0x156,
  45459         SOC_REG_FLAG_ARRAY |
  45460                           SOC_REG_FLAG_WO |
  45461                           SOC_REG_FLAG_REG_ARRAY,
  45462         0,
  45463         7,
  45464         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM83208_A0r_fields,
  45465         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45466         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45467         -1,
  45468         -1,
  45469     },
  45470 #endif /* chips */
  45471 
  45472 #if defined(BCM_88202_A0)
  45473     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88202_A0r */
  45474         soc_block_list[23],
  45475         soc_genreg,
  45476         4,
  45477         0,
  45478         0x100,
  45479         SOC_REG_FLAG_ARRAY |
  45480                           SOC_REG_FLAG_WO |
  45481                           SOC_REG_FLAG_REG_ARRAY,
  45482         0,
  45483         7,
  45484         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88202_A0r_fields,
  45485         SOC_RESET_VAL_DEC(0x0001c7bf, 0x00000000)
  45486         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45487         -1,
  45488         -1,
  45489     },
  45490 #endif /* chips */
  45491 
  45492 #if defined(BCM_88375_A0)
  45493     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88375_A0r */
  45494         soc_block_list[23],
  45495         soc_genreg,
  45496         4,
  45497         0,
  45498         0x141,
  45499         SOC_REG_FLAG_ARRAY |
  45500                           SOC_REG_FLAG_WO |
  45501                           SOC_REG_FLAG_REG_ARRAY,
  45502         0,
  45503         7,
  45504         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88375_A0r_fields,
  45505         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45506         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45507         -1,
  45508         -1,
  45509     },
  45510 #endif /* chips */
  45511 
  45512 #if defined(BCM_88375_B0)
  45513     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88375_B0r */
  45514         soc_block_list[23],
  45515         soc_genreg,
  45516         4,
  45517         0,
  45518         0x141,
  45519         SOC_REG_FLAG_ARRAY |
  45520                           SOC_REG_FLAG_WO |
  45521                           SOC_REG_FLAG_REG_ARRAY,
  45522         0,
  45523         7,
  45524         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88375_B0r_fields,
  45525         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45526         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45527         -1,
  45528         -1,
  45529     },
  45530 #endif /* chips */
  45531 
  45532 #if defined(BCM_88470_A0)
  45533     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88470_A0r */
  45534         soc_block_list[23],
  45535         soc_genreg,
  45536         4,
  45537         0,
  45538         0x141,
  45539         SOC_REG_FLAG_ARRAY |
  45540                           SOC_REG_FLAG_WO |
  45541                           SOC_REG_FLAG_REG_ARRAY,
  45542         0,
  45543         7,
  45544         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88470_A0r_fields,
  45545         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45546         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45547         -1,
  45548         -1,
  45549     },
  45550 #endif /* chips */
  45551 
  45552 #if defined(BCM_88470_B0)
  45553     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88470_B0r */
  45554         soc_block_list[23],
  45555         soc_genreg,
  45556         4,
  45557         0,
  45558         0x141,
  45559         SOC_REG_FLAG_ARRAY |
  45560                           SOC_REG_FLAG_WO |
  45561                           SOC_REG_FLAG_REG_ARRAY,
  45562         0,
  45563         7,
  45564         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88470_B0r_fields,
  45565         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45566         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45567         -1,
  45568         -1,
  45569     },
  45570 #endif /* chips */
  45571 
  45572 #if defined(BCM_88650_B0)
  45573     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88650_B0r */
  45574         soc_block_list[23],
  45575         soc_genreg,
  45576         4,
  45577         0,
  45578         0x100,
  45579         SOC_REG_FLAG_ARRAY |
  45580                           SOC_REG_FLAG_WO |
  45581                           SOC_REG_FLAG_REG_ARRAY,
  45582         0,
  45583         7,
  45584         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88650_B0r_fields,
  45585         SOC_RESET_VAL_DEC(0x0001c7bf, 0x00000000)
  45586         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45587         -1,
  45588         -1,
  45589     },
  45590 #endif /* chips */
  45591 
  45592 #if defined(BCM_88660_A0)
  45593     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88660_A0r */
  45594         soc_block_list[23],
  45595         soc_genreg,
  45596         4,
  45597         0,
  45598         0x100,
  45599         SOC_REG_FLAG_ARRAY |
  45600                           SOC_REG_FLAG_WO |
  45601                           SOC_REG_FLAG_REG_ARRAY,
  45602         0,
  45603         7,
  45604         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88660_A0r_fields,
  45605         SOC_RESET_VAL_DEC(0x0001c7bf, 0x00000000)
  45606         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45607         -1,
  45608         -1,
  45609     },
  45610 #endif /* chips */
  45611 
  45612 #if defined(BCM_88675_A0)
  45613     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88675_A0r */
  45614         soc_block_list[23],
  45615         soc_genreg,
  45616         4,
  45617         0,
  45618         0x141,
  45619         SOC_REG_FLAG_ARRAY |
  45620                           SOC_REG_FLAG_WO |
  45621                           SOC_REG_FLAG_REG_ARRAY,
  45622         0,
  45623         7,
  45624         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88675_A0r_fields,
  45625         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45626         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45627         -1,
  45628         -1,
  45629     },
  45630 #endif /* chips */
  45631 
  45632 #if defined(BCM_88675_B0)
  45633     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88675_B0r */
  45634         soc_block_list[23],
  45635         soc_genreg,
  45636         4,
  45637         0,
  45638         0x141,
  45639         SOC_REG_FLAG_ARRAY |
  45640                           SOC_REG_FLAG_WO |
  45641                           SOC_REG_FLAG_REG_ARRAY,
  45642         0,
  45643         7,
  45644         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88675_B0r_fields,
  45645         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45646         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45647         -1,
  45648         -1,
  45649     },
  45650 #endif /* chips */
  45651 
  45652 #if defined(BCM_88680_A0)
  45653     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88680_A0r */
  45654         soc_block_list[23],
  45655         soc_genreg,
  45656         4,
  45657         0,
  45658         0x141,
  45659         SOC_REG_FLAG_ARRAY |
  45660                           SOC_REG_FLAG_WO |
  45661                           SOC_REG_FLAG_REG_ARRAY,
  45662         0,
  45663         7,
  45664         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88680_A0r_fields,
  45665         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45666         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45667         -1,
  45668         -1,
  45669     },
  45670 #endif /* chips */
  45671 
  45672 #if defined(BCM_88690_A0)
  45673     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88690_A0r */
  45674         soc_block_list[23],
  45675         soc_genreg,
  45676         4,
  45677         0,
  45678         0x192,
  45679         SOC_REG_FLAG_ARRAY |
  45680                           SOC_REG_FLAG_WO |
  45681                           SOC_REG_FLAG_REG_ARRAY,
  45682         0,
  45683         7,
  45684         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88690_A0r_fields,
  45685         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45686         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45687         -1,
  45688         -1,
  45689     },
  45690 #endif /* chips */
  45691 
  45692 #if defined(BCM_88690_B0)
  45693     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88690_B0r */
  45694         soc_block_list[23],
  45695         soc_genreg,
  45696         4,
  45697         0,
  45698         0x192,
  45699         SOC_REG_FLAG_ARRAY |
  45700                           SOC_REG_FLAG_WO |
  45701                           SOC_REG_FLAG_REG_ARRAY,
  45702         0,
  45703         7,
  45704         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88690_B0r_fields,
  45705         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45706         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45707         -1,
  45708         -1,
  45709     },
  45710 #endif /* chips */
  45711 
  45712 #if defined(BCM_88790_A0)
  45713     { /* SOC_REG_INT_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88790_A0r */
  45714         soc_block_list[23],
  45715         soc_genreg,
  45716         4,
  45717         0,
  45718         0x192,
  45719         SOC_REG_FLAG_ARRAY |
  45720                           SOC_REG_FLAG_WO |
  45721                           SOC_REG_FLAG_REG_ARRAY,
  45722         0,
  45723         7,
  45724         soc_BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC_BCM88790_A0r_fields,
  45725         SOC_RESET_VAL_DEC(0x0003c7bf, 0x00000000)
  45726         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  45727         -1,
  45728         -1,
  45729     },
  45730 #endif /* chips */
  45731 
  45732 #if defined(BCM_88650_A0)
  45733     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATIONr */
  45734         soc_block_list[23],
  45735         soc_genreg,
  45736         4,
  45737         0,
  45738         0x110,
  45739         SOC_REG_FLAG_ARRAY |
  45740                           SOC_REG_FLAG_WO |
  45741                           SOC_REG_FLAG_REG_ARRAY,
  45742         0,
  45743         17,
  45744         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATIONr_fields,
  45745         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45746         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45747         -1,
  45748         -1,
  45749     },
  45750 #endif /* chips */
  45751 
  45752 #if defined(BCM_83208_A0)
  45753     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM83208_A0r */
  45754         soc_block_list[23],
  45755         soc_genreg,
  45756         4,
  45757         0,
  45758         0x15a,
  45759         SOC_REG_FLAG_ARRAY |
  45760                           SOC_REG_FLAG_WO |
  45761                           SOC_REG_FLAG_REG_ARRAY,
  45762         0,
  45763         16,
  45764         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM83208_A0r_fields,
  45765         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45766         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  45767         -1,
  45768         -1,
  45769     },
  45770 #endif /* chips */
  45771 
  45772 #if defined(BCM_88202_A0)
  45773     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88202_A0r */
  45774         soc_block_list[23],
  45775         soc_genreg,
  45776         4,
  45777         0,
  45778         0x110,
  45779         SOC_REG_FLAG_ARRAY |
  45780                           SOC_REG_FLAG_WO |
  45781                           SOC_REG_FLAG_REG_ARRAY,
  45782         0,
  45783         17,
  45784         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88202_A0r_fields,
  45785         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45786         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45787         -1,
  45788         -1,
  45789     },
  45790 #endif /* chips */
  45791 
  45792 #if defined(BCM_88375_A0)
  45793     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88375_A0r */
  45794         soc_block_list[23],
  45795         soc_genreg,
  45796         4,
  45797         0,
  45798         0x145,
  45799         SOC_REG_FLAG_ARRAY |
  45800                           SOC_REG_FLAG_WO |
  45801                           SOC_REG_FLAG_REG_ARRAY,
  45802         0,
  45803         17,
  45804         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88375_A0r_fields,
  45805         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45806         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45807         -1,
  45808         -1,
  45809     },
  45810 #endif /* chips */
  45811 
  45812 #if defined(BCM_88375_B0)
  45813     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88375_B0r */
  45814         soc_block_list[23],
  45815         soc_genreg,
  45816         4,
  45817         0,
  45818         0x145,
  45819         SOC_REG_FLAG_ARRAY |
  45820                           SOC_REG_FLAG_WO |
  45821                           SOC_REG_FLAG_REG_ARRAY,
  45822         0,
  45823         17,
  45824         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88375_B0r_fields,
  45825         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45826         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45827         -1,
  45828         -1,
  45829     },
  45830 #endif /* chips */
  45831 
  45832 #if defined(BCM_88470_A0)
  45833     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88470_A0r */
  45834         soc_block_list[23],
  45835         soc_genreg,
  45836         4,
  45837         0,
  45838         0x145,
  45839         SOC_REG_FLAG_ARRAY |
  45840                           SOC_REG_FLAG_WO |
  45841                           SOC_REG_FLAG_REG_ARRAY,
  45842         0,
  45843         17,
  45844         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88470_A0r_fields,
  45845         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45846         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45847         -1,
  45848         -1,
  45849     },
  45850 #endif /* chips */
  45851 
  45852 #if defined(BCM_88470_B0)
  45853     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88470_B0r */
  45854         soc_block_list[23],
  45855         soc_genreg,
  45856         4,
  45857         0,
  45858         0x145,
  45859         SOC_REG_FLAG_ARRAY |
  45860                           SOC_REG_FLAG_WO |
  45861                           SOC_REG_FLAG_REG_ARRAY,
  45862         0,
  45863         17,
  45864         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88470_B0r_fields,
  45865         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45866         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45867         -1,
  45868         -1,
  45869     },
  45870 #endif /* chips */
  45871 
  45872 #if defined(BCM_88650_B0)
  45873     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88650_B0r */
  45874         soc_block_list[23],
  45875         soc_genreg,
  45876         4,
  45877         0,
  45878         0x110,
  45879         SOC_REG_FLAG_ARRAY |
  45880                           SOC_REG_FLAG_WO |
  45881                           SOC_REG_FLAG_REG_ARRAY,
  45882         0,
  45883         17,
  45884         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88650_B0r_fields,
  45885         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45886         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45887         -1,
  45888         -1,
  45889     },
  45890 #endif /* chips */
  45891 
  45892 #if defined(BCM_88660_A0)
  45893     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88660_A0r */
  45894         soc_block_list[23],
  45895         soc_genreg,
  45896         4,
  45897         0,
  45898         0x110,
  45899         SOC_REG_FLAG_ARRAY |
  45900                           SOC_REG_FLAG_WO |
  45901                           SOC_REG_FLAG_REG_ARRAY,
  45902         0,
  45903         17,
  45904         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88660_A0r_fields,
  45905         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45906         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45907         -1,
  45908         -1,
  45909     },
  45910 #endif /* chips */
  45911 
  45912 #if defined(BCM_88675_A0)
  45913     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88675_A0r */
  45914         soc_block_list[23],
  45915         soc_genreg,
  45916         4,
  45917         0,
  45918         0x145,
  45919         SOC_REG_FLAG_ARRAY |
  45920                           SOC_REG_FLAG_WO |
  45921                           SOC_REG_FLAG_REG_ARRAY,
  45922         0,
  45923         17,
  45924         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88675_A0r_fields,
  45925         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45926         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45927         -1,
  45928         -1,
  45929     },
  45930 #endif /* chips */
  45931 
  45932 #if defined(BCM_88675_B0)
  45933     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88675_B0r */
  45934         soc_block_list[23],
  45935         soc_genreg,
  45936         4,
  45937         0,
  45938         0x145,
  45939         SOC_REG_FLAG_ARRAY |
  45940                           SOC_REG_FLAG_WO |
  45941                           SOC_REG_FLAG_REG_ARRAY,
  45942         0,
  45943         17,
  45944         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88675_B0r_fields,
  45945         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45946         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45947         -1,
  45948         -1,
  45949     },
  45950 #endif /* chips */
  45951 
  45952 #if defined(BCM_88680_A0)
  45953     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88680_A0r */
  45954         soc_block_list[23],
  45955         soc_genreg,
  45956         4,
  45957         0,
  45958         0x145,
  45959         SOC_REG_FLAG_ARRAY |
  45960                           SOC_REG_FLAG_WO |
  45961                           SOC_REG_FLAG_REG_ARRAY,
  45962         0,
  45963         17,
  45964         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88680_A0r_fields,
  45965         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45966         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  45967         -1,
  45968         -1,
  45969     },
  45970 #endif /* chips */
  45971 
  45972 #if defined(BCM_88690_A0)
  45973     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88690_A0r */
  45974         soc_block_list[23],
  45975         soc_genreg,
  45976         4,
  45977         0,
  45978         0x196,
  45979         SOC_REG_FLAG_ARRAY |
  45980                           SOC_REG_FLAG_WO |
  45981                           SOC_REG_FLAG_REG_ARRAY,
  45982         0,
  45983         16,
  45984         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88690_A0r_fields,
  45985         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  45986         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  45987         -1,
  45988         -1,
  45989     },
  45990 #endif /* chips */
  45991 
  45992 #if defined(BCM_88690_B0)
  45993     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88690_B0r */
  45994         soc_block_list[23],
  45995         soc_genreg,
  45996         4,
  45997         0,
  45998         0x196,
  45999         SOC_REG_FLAG_ARRAY |
  46000                           SOC_REG_FLAG_WO |
  46001                           SOC_REG_FLAG_REG_ARRAY,
  46002         0,
  46003         16,
  46004         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88690_B0r_fields,
  46005         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  46006         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  46007         -1,
  46008         -1,
  46009     },
  46010 #endif /* chips */
  46011 
  46012 #if defined(BCM_88790_A0)
  46013     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88790_A0r */
  46014         soc_block_list[23],
  46015         soc_genreg,
  46016         4,
  46017         0,
  46018         0x196,
  46019         SOC_REG_FLAG_ARRAY |
  46020                           SOC_REG_FLAG_WO |
  46021                           SOC_REG_FLAG_REG_ARRAY,
  46022         0,
  46023         16,
  46024         soc_BRDC_FMAC_FPS_RX_FEC_CONFIGURATION_BCM88790_A0r_fields,
  46025         SOC_RESET_VAL_DEC(0x20442001, 0x00000000)
  46026         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  46027         -1,
  46028         -1,
  46029     },
  46030 #endif /* chips */
  46031 
  46032 #if defined(BCM_88650_A0)
  46033     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUSr */
  46034         soc_block_list[23],
  46035         soc_genreg,
  46036         4,
  46037         0,
  46038         0x130,
  46039         SOC_REG_FLAG_ARRAY |
  46040                           SOC_REG_FLAG_WO |
  46041                           SOC_REG_FLAG_REG_ARRAY,
  46042         0,
  46043         7,
  46044         soc_BRDC_FMAC_FPS_RX_STATUSr_fields,
  46045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46046         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46047         -1,
  46048         -1,
  46049     },
  46050 #endif /* chips */
  46051 
  46052 #if defined(BCM_83208_A0)
  46053     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM83208_A0r */
  46054         soc_block_list[23],
  46055         soc_genreg,
  46056         4,
  46057         0,
  46058         0x162,
  46059         SOC_REG_FLAG_ARRAY |
  46060                           SOC_REG_FLAG_RO |
  46061                           SOC_REG_FLAG_WO |
  46062                           SOC_REG_FLAG_REG_ARRAY,
  46063         0,
  46064         7,
  46065         soc_BRDC_FMAC_FPS_RX_STATUS_BCM83208_A0r_fields,
  46066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46067         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46068         -1,
  46069         -1,
  46070     },
  46071 #endif /* chips */
  46072 
  46073 #if defined(BCM_88202_A0)
  46074     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88202_A0r */
  46075         soc_block_list[23],
  46076         soc_genreg,
  46077         4,
  46078         0,
  46079         0x130,
  46080         SOC_REG_FLAG_ARRAY |
  46081                           SOC_REG_FLAG_WO |
  46082                           SOC_REG_FLAG_REG_ARRAY,
  46083         0,
  46084         7,
  46085         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88202_A0r_fields,
  46086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46087         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46088         -1,
  46089         -1,
  46090     },
  46091 #endif /* chips */
  46092 
  46093 #if defined(BCM_88375_A0)
  46094     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88375_A0r */
  46095         soc_block_list[23],
  46096         soc_genreg,
  46097         4,
  46098         0,
  46099         0x14d,
  46100         SOC_REG_FLAG_ARRAY |
  46101                           SOC_REG_FLAG_RO |
  46102                           SOC_REG_FLAG_WO |
  46103                           SOC_REG_FLAG_REG_ARRAY,
  46104         0,
  46105         7,
  46106         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88375_A0r_fields,
  46107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46108         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46109         -1,
  46110         -1,
  46111     },
  46112 #endif /* chips */
  46113 
  46114 #if defined(BCM_88375_B0)
  46115     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88375_B0r */
  46116         soc_block_list[23],
  46117         soc_genreg,
  46118         4,
  46119         0,
  46120         0x14d,
  46121         SOC_REG_FLAG_ARRAY |
  46122                           SOC_REG_FLAG_RO |
  46123                           SOC_REG_FLAG_WO |
  46124                           SOC_REG_FLAG_REG_ARRAY,
  46125         0,
  46126         7,
  46127         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88375_B0r_fields,
  46128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46129         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46130         -1,
  46131         -1,
  46132     },
  46133 #endif /* chips */
  46134 
  46135 #if defined(BCM_88470_A0)
  46136     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88470_A0r */
  46137         soc_block_list[23],
  46138         soc_genreg,
  46139         4,
  46140         0,
  46141         0x14d,
  46142         SOC_REG_FLAG_ARRAY |
  46143                           SOC_REG_FLAG_RO |
  46144                           SOC_REG_FLAG_WO |
  46145                           SOC_REG_FLAG_REG_ARRAY,
  46146         0,
  46147         7,
  46148         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88470_A0r_fields,
  46149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46150         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46151         -1,
  46152         -1,
  46153     },
  46154 #endif /* chips */
  46155 
  46156 #if defined(BCM_88470_B0)
  46157     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88470_B0r */
  46158         soc_block_list[23],
  46159         soc_genreg,
  46160         4,
  46161         0,
  46162         0x14d,
  46163         SOC_REG_FLAG_ARRAY |
  46164                           SOC_REG_FLAG_RO |
  46165                           SOC_REG_FLAG_WO |
  46166                           SOC_REG_FLAG_REG_ARRAY,
  46167         0,
  46168         7,
  46169         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88470_B0r_fields,
  46170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46171         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46172         -1,
  46173         -1,
  46174     },
  46175 #endif /* chips */
  46176 
  46177 #if defined(BCM_88650_B0)
  46178     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88650_B0r */
  46179         soc_block_list[23],
  46180         soc_genreg,
  46181         4,
  46182         0,
  46183         0x130,
  46184         SOC_REG_FLAG_ARRAY |
  46185                           SOC_REG_FLAG_WO |
  46186                           SOC_REG_FLAG_REG_ARRAY,
  46187         0,
  46188         7,
  46189         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88650_B0r_fields,
  46190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46191         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46192         -1,
  46193         -1,
  46194     },
  46195 #endif /* chips */
  46196 
  46197 #if defined(BCM_88660_A0)
  46198     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88660_A0r */
  46199         soc_block_list[23],
  46200         soc_genreg,
  46201         4,
  46202         0,
  46203         0x130,
  46204         SOC_REG_FLAG_ARRAY |
  46205                           SOC_REG_FLAG_WO |
  46206                           SOC_REG_FLAG_REG_ARRAY,
  46207         0,
  46208         7,
  46209         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88660_A0r_fields,
  46210         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46211         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46212         -1,
  46213         -1,
  46214     },
  46215 #endif /* chips */
  46216 
  46217 #if defined(BCM_88675_A0)
  46218     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88675_A0r */
  46219         soc_block_list[23],
  46220         soc_genreg,
  46221         4,
  46222         0,
  46223         0x14d,
  46224         SOC_REG_FLAG_ARRAY |
  46225                           SOC_REG_FLAG_RO |
  46226                           SOC_REG_FLAG_WO |
  46227                           SOC_REG_FLAG_REG_ARRAY,
  46228         0,
  46229         7,
  46230         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88675_A0r_fields,
  46231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46232         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46233         -1,
  46234         -1,
  46235     },
  46236 #endif /* chips */
  46237 
  46238 #if defined(BCM_88675_B0)
  46239     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88675_B0r */
  46240         soc_block_list[23],
  46241         soc_genreg,
  46242         4,
  46243         0,
  46244         0x14d,
  46245         SOC_REG_FLAG_ARRAY |
  46246                           SOC_REG_FLAG_RO |
  46247                           SOC_REG_FLAG_WO |
  46248                           SOC_REG_FLAG_REG_ARRAY,
  46249         0,
  46250         7,
  46251         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88675_B0r_fields,
  46252         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46253         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46254         -1,
  46255         -1,
  46256     },
  46257 #endif /* chips */
  46258 
  46259 #if defined(BCM_88680_A0)
  46260     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88680_A0r */
  46261         soc_block_list[23],
  46262         soc_genreg,
  46263         4,
  46264         0,
  46265         0x14d,
  46266         SOC_REG_FLAG_ARRAY |
  46267                           SOC_REG_FLAG_RO |
  46268                           SOC_REG_FLAG_WO |
  46269                           SOC_REG_FLAG_REG_ARRAY,
  46270         0,
  46271         7,
  46272         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88680_A0r_fields,
  46273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46274         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46275         -1,
  46276         -1,
  46277     },
  46278 #endif /* chips */
  46279 
  46280 #if defined(BCM_88690_A0)
  46281     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88690_A0r */
  46282         soc_block_list[23],
  46283         soc_genreg,
  46284         4,
  46285         0,
  46286         0x19e,
  46287         SOC_REG_FLAG_ARRAY |
  46288                           SOC_REG_FLAG_RO |
  46289                           SOC_REG_FLAG_WO |
  46290                           SOC_REG_FLAG_REG_ARRAY,
  46291         SOC_REG_FLAG_INIT_ON_READ,
  46292         7,
  46293         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88690_A0r_fields,
  46294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46295         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46296         -1,
  46297         -1,
  46298     },
  46299 #endif /* chips */
  46300 
  46301 #if defined(BCM_88690_B0)
  46302     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88690_B0r */
  46303         soc_block_list[23],
  46304         soc_genreg,
  46305         4,
  46306         0,
  46307         0x19e,
  46308         SOC_REG_FLAG_ARRAY |
  46309                           SOC_REG_FLAG_RO |
  46310                           SOC_REG_FLAG_WO |
  46311                           SOC_REG_FLAG_REG_ARRAY,
  46312         SOC_REG_FLAG_INIT_ON_READ,
  46313         7,
  46314         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88690_B0r_fields,
  46315         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46316         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46317         -1,
  46318         -1,
  46319     },
  46320 #endif /* chips */
  46321 
  46322 #if defined(BCM_88790_A0)
  46323     { /* SOC_REG_INT_BRDC_FMAC_FPS_RX_STATUS_BCM88790_A0r */
  46324         soc_block_list[23],
  46325         soc_genreg,
  46326         4,
  46327         0,
  46328         0x19e,
  46329         SOC_REG_FLAG_ARRAY |
  46330                           SOC_REG_FLAG_RO |
  46331                           SOC_REG_FLAG_WO |
  46332                           SOC_REG_FLAG_REG_ARRAY,
  46333         0,
  46334         7,
  46335         soc_BRDC_FMAC_FPS_RX_STATUS_BCM88790_A0r_fields,
  46336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  46337         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  46338         -1,
  46339         -1,
  46340     },
  46341 #endif /* chips */
  46342 
  46343 #if defined(BCM_88650_A0)
  46344     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATIONr */
  46345         soc_block_list[23],
  46346         soc_genreg,
  46347         4,
  46348         0,
  46349         0x120,
  46350         SOC_REG_FLAG_ARRAY |
  46351                           SOC_REG_FLAG_WO |
  46352                           SOC_REG_FLAG_REG_ARRAY,
  46353         0,
  46354         9,
  46355         soc_BRDC_FMAC_FPS_TX_CONFIGURATIONr_fields,
  46356         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46357         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46358         -1,
  46359         -1,
  46360     },
  46361 #endif /* chips */
  46362 
  46363 #if defined(BCM_83208_A0)
  46364     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM83208_A0r */
  46365         soc_block_list[23],
  46366         soc_genreg,
  46367         4,
  46368         0,
  46369         0x15e,
  46370         SOC_REG_FLAG_ARRAY |
  46371                           SOC_REG_FLAG_WO |
  46372                           SOC_REG_FLAG_REG_ARRAY,
  46373         0,
  46374         8,
  46375         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM83208_A0r_fields,
  46376         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46377         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  46378         -1,
  46379         -1,
  46380     },
  46381 #endif /* chips */
  46382 
  46383 #if defined(BCM_88202_A0)
  46384     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88202_A0r */
  46385         soc_block_list[23],
  46386         soc_genreg,
  46387         4,
  46388         0,
  46389         0x120,
  46390         SOC_REG_FLAG_ARRAY |
  46391                           SOC_REG_FLAG_WO |
  46392                           SOC_REG_FLAG_REG_ARRAY,
  46393         0,
  46394         9,
  46395         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88202_A0r_fields,
  46396         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46397         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46398         -1,
  46399         -1,
  46400     },
  46401 #endif /* chips */
  46402 
  46403 #if defined(BCM_88375_A0)
  46404     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88375_A0r */
  46405         soc_block_list[23],
  46406         soc_genreg,
  46407         4,
  46408         0,
  46409         0x149,
  46410         SOC_REG_FLAG_ARRAY |
  46411                           SOC_REG_FLAG_WO |
  46412                           SOC_REG_FLAG_REG_ARRAY,
  46413         0,
  46414         9,
  46415         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88375_A0r_fields,
  46416         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46417         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46418         -1,
  46419         -1,
  46420     },
  46421 #endif /* chips */
  46422 
  46423 #if defined(BCM_88375_B0)
  46424     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88375_B0r */
  46425         soc_block_list[23],
  46426         soc_genreg,
  46427         4,
  46428         0,
  46429         0x149,
  46430         SOC_REG_FLAG_ARRAY |
  46431                           SOC_REG_FLAG_WO |
  46432                           SOC_REG_FLAG_REG_ARRAY,
  46433         0,
  46434         9,
  46435         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88375_B0r_fields,
  46436         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46437         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46438         -1,
  46439         -1,
  46440     },
  46441 #endif /* chips */
  46442 
  46443 #if defined(BCM_88470_A0)
  46444     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88470_A0r */
  46445         soc_block_list[23],
  46446         soc_genreg,
  46447         4,
  46448         0,
  46449         0x149,
  46450         SOC_REG_FLAG_ARRAY |
  46451                           SOC_REG_FLAG_WO |
  46452                           SOC_REG_FLAG_REG_ARRAY,
  46453         0,
  46454         9,
  46455         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88470_A0r_fields,
  46456         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46457         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46458         -1,
  46459         -1,
  46460     },
  46461 #endif /* chips */
  46462 
  46463 #if defined(BCM_88470_B0)
  46464     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88470_B0r */
  46465         soc_block_list[23],
  46466         soc_genreg,
  46467         4,
  46468         0,
  46469         0x149,
  46470         SOC_REG_FLAG_ARRAY |
  46471                           SOC_REG_FLAG_WO |
  46472                           SOC_REG_FLAG_REG_ARRAY,
  46473         0,
  46474         9,
  46475         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88470_B0r_fields,
  46476         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46477         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46478         -1,
  46479         -1,
  46480     },
  46481 #endif /* chips */
  46482 
  46483 #if defined(BCM_88650_B0)
  46484     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88650_B0r */
  46485         soc_block_list[23],
  46486         soc_genreg,
  46487         4,
  46488         0,
  46489         0x120,
  46490         SOC_REG_FLAG_ARRAY |
  46491                           SOC_REG_FLAG_WO |
  46492                           SOC_REG_FLAG_REG_ARRAY,
  46493         0,
  46494         9,
  46495         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88650_B0r_fields,
  46496         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46497         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46498         -1,
  46499         -1,
  46500     },
  46501 #endif /* chips */
  46502 
  46503 #if defined(BCM_88660_A0)
  46504     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88660_A0r */
  46505         soc_block_list[23],
  46506         soc_genreg,
  46507         4,
  46508         0,
  46509         0x120,
  46510         SOC_REG_FLAG_ARRAY |
  46511                           SOC_REG_FLAG_WO |
  46512                           SOC_REG_FLAG_REG_ARRAY,
  46513         0,
  46514         9,
  46515         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88660_A0r_fields,
  46516         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46517         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46518         -1,
  46519         -1,
  46520     },
  46521 #endif /* chips */
  46522 
  46523 #if defined(BCM_88675_A0)
  46524     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88675_A0r */
  46525         soc_block_list[23],
  46526         soc_genreg,
  46527         4,
  46528         0,
  46529         0x149,
  46530         SOC_REG_FLAG_ARRAY |
  46531                           SOC_REG_FLAG_WO |
  46532                           SOC_REG_FLAG_REG_ARRAY,
  46533         0,
  46534         9,
  46535         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88675_A0r_fields,
  46536         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46537         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46538         -1,
  46539         -1,
  46540     },
  46541 #endif /* chips */
  46542 
  46543 #if defined(BCM_88675_B0)
  46544     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88675_B0r */
  46545         soc_block_list[23],
  46546         soc_genreg,
  46547         4,
  46548         0,
  46549         0x149,
  46550         SOC_REG_FLAG_ARRAY |
  46551                           SOC_REG_FLAG_WO |
  46552                           SOC_REG_FLAG_REG_ARRAY,
  46553         0,
  46554         9,
  46555         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88675_B0r_fields,
  46556         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46557         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46558         -1,
  46559         -1,
  46560     },
  46561 #endif /* chips */
  46562 
  46563 #if defined(BCM_88680_A0)
  46564     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88680_A0r */
  46565         soc_block_list[23],
  46566         soc_genreg,
  46567         4,
  46568         0,
  46569         0x149,
  46570         SOC_REG_FLAG_ARRAY |
  46571                           SOC_REG_FLAG_WO |
  46572                           SOC_REG_FLAG_REG_ARRAY,
  46573         0,
  46574         9,
  46575         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88680_A0r_fields,
  46576         SOC_RESET_VAL_DEC(0x00000043, 0x00000000)
  46577         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46578         -1,
  46579         -1,
  46580     },
  46581 #endif /* chips */
  46582 
  46583 #if defined(BCM_88690_A0)
  46584     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88690_A0r */
  46585         soc_block_list[23],
  46586         soc_genreg,
  46587         4,
  46588         0,
  46589         0x19a,
  46590         SOC_REG_FLAG_ARRAY |
  46591                           SOC_REG_FLAG_WO |
  46592                           SOC_REG_FLAG_REG_ARRAY,
  46593         0,
  46594         9,
  46595         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88690_A0r_fields,
  46596         SOC_RESET_VAL_DEC(0x00000143, 0x00000000)
  46597         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46598         -1,
  46599         -1,
  46600     },
  46601 #endif /* chips */
  46602 
  46603 #if defined(BCM_88690_B0)
  46604     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88690_B0r */
  46605         soc_block_list[23],
  46606         soc_genreg,
  46607         4,
  46608         0,
  46609         0x19a,
  46610         SOC_REG_FLAG_ARRAY |
  46611                           SOC_REG_FLAG_WO |
  46612                           SOC_REG_FLAG_REG_ARRAY,
  46613         0,
  46614         9,
  46615         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88690_B0r_fields,
  46616         SOC_RESET_VAL_DEC(0x00000143, 0x00000000)
  46617         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46618         -1,
  46619         -1,
  46620     },
  46621 #endif /* chips */
  46622 
  46623 #if defined(BCM_88790_A0)
  46624     { /* SOC_REG_INT_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88790_A0r */
  46625         soc_block_list[23],
  46626         soc_genreg,
  46627         4,
  46628         0,
  46629         0x19a,
  46630         SOC_REG_FLAG_ARRAY |
  46631                           SOC_REG_FLAG_WO |
  46632                           SOC_REG_FLAG_REG_ARRAY,
  46633         0,
  46634         9,
  46635         soc_BRDC_FMAC_FPS_TX_CONFIGURATION_BCM88790_A0r_fields,
  46636         SOC_RESET_VAL_DEC(0x00000143, 0x00000000)
  46637         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  46638         -1,
  46639         -1,
  46640     },
  46641 #endif /* chips */
  46642 
  46643 #if defined(BCM_88650_A0)
  46644     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTERr */
  46645         soc_block_list[23],
  46646         soc_genreg,
  46647         1,
  46648         0,
  46649         0x60,
  46650         SOC_REG_FLAG_WO,
  46651         0,
  46652         14,
  46653         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTERr_fields,
  46654         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  46655         SOC_RESET_MASK_DEC(0x07f80f0f, 0x00000000)
  46656         -1,
  46657         -1,
  46658     },
  46659 #endif /* chips */
  46660 
  46661 #if defined(BCM_83208_A0)
  46662     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM83208_A0r */
  46663         soc_block_list[23],
  46664         soc_genreg,
  46665         1,
  46666         0,
  46667         0x103,
  46668         SOC_REG_FLAG_WO,
  46669         0,
  46670         13,
  46671         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM83208_A0r_fields,
  46672         SOC_RESET_VAL_DEC(0x000030f3, 0x00000000)
  46673         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  46674         -1,
  46675         -1,
  46676     },
  46677 #endif /* chips */
  46678 
  46679 #if defined(BCM_88202_A0)
  46680     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88202_A0r */
  46681         soc_block_list[23],
  46682         soc_genreg,
  46683         1,
  46684         0,
  46685         0x60,
  46686         SOC_REG_FLAG_WO,
  46687         0,
  46688         15,
  46689         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88202_A0r_fields,
  46690         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  46691         SOC_RESET_MASK_DEC(0x07fbff0f, 0x00000000)
  46692         -1,
  46693         -1,
  46694     },
  46695 #endif /* chips */
  46696 
  46697 #if defined(BCM_88375_A0)
  46698     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88375_A0r */
  46699         soc_block_list[23],
  46700         soc_genreg,
  46701         1,
  46702         0,
  46703         0x103,
  46704         SOC_REG_FLAG_WO,
  46705         0,
  46706         15,
  46707         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88375_A0r_fields,
  46708         SOC_RESET_VAL_DEC(0x000040f3, 0x00000000)
  46709         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46710         -1,
  46711         -1,
  46712     },
  46713 #endif /* chips */
  46714 
  46715 #if defined(BCM_88375_B0)
  46716     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88375_B0r */
  46717         soc_block_list[23],
  46718         soc_genreg,
  46719         1,
  46720         0,
  46721         0x103,
  46722         SOC_REG_FLAG_WO,
  46723         0,
  46724         15,
  46725         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88375_B0r_fields,
  46726         SOC_RESET_VAL_DEC(0x000040f3, 0x00000000)
  46727         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46728         -1,
  46729         -1,
  46730     },
  46731 #endif /* chips */
  46732 
  46733 #if defined(BCM_88470_A0)
  46734     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88470_A0r */
  46735         soc_block_list[23],
  46736         soc_genreg,
  46737         1,
  46738         0,
  46739         0x103,
  46740         SOC_REG_FLAG_WO,
  46741         0,
  46742         15,
  46743         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88470_A0r_fields,
  46744         SOC_RESET_VAL_DEC(0x000060f3, 0x00000000)
  46745         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46746         -1,
  46747         -1,
  46748     },
  46749 #endif /* chips */
  46750 
  46751 #if defined(BCM_88470_B0)
  46752     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88470_B0r */
  46753         soc_block_list[23],
  46754         soc_genreg,
  46755         1,
  46756         0,
  46757         0x103,
  46758         SOC_REG_FLAG_WO,
  46759         0,
  46760         15,
  46761         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88470_B0r_fields,
  46762         SOC_RESET_VAL_DEC(0x000060f3, 0x00000000)
  46763         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46764         -1,
  46765         -1,
  46766     },
  46767 #endif /* chips */
  46768 
  46769 #if defined(BCM_88650_B0)
  46770     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88650_B0r */
  46771         soc_block_list[23],
  46772         soc_genreg,
  46773         1,
  46774         0,
  46775         0x60,
  46776         SOC_REG_FLAG_WO,
  46777         0,
  46778         14,
  46779         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88650_B0r_fields,
  46780         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  46781         SOC_RESET_MASK_DEC(0x07f80f0f, 0x00000000)
  46782         -1,
  46783         -1,
  46784     },
  46785 #endif /* chips */
  46786 
  46787 #if defined(BCM_88660_A0)
  46788     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88660_A0r */
  46789         soc_block_list[23],
  46790         soc_genreg,
  46791         1,
  46792         0,
  46793         0x60,
  46794         SOC_REG_FLAG_WO,
  46795         0,
  46796         14,
  46797         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88660_A0r_fields,
  46798         SOC_RESET_VAL_DEC(0x06000f03, 0x00000000)
  46799         SOC_RESET_MASK_DEC(0x07f80f0f, 0x00000000)
  46800         -1,
  46801         -1,
  46802     },
  46803 #endif /* chips */
  46804 
  46805 #if defined(BCM_88675_A0)
  46806     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88675_A0r */
  46807         soc_block_list[23],
  46808         soc_genreg,
  46809         1,
  46810         0,
  46811         0x103,
  46812         SOC_REG_FLAG_WO,
  46813         0,
  46814         15,
  46815         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88675_A0r_fields,
  46816         SOC_RESET_VAL_DEC(0x000040f3, 0x00000000)
  46817         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46818         -1,
  46819         -1,
  46820     },
  46821 #endif /* chips */
  46822 
  46823 #if defined(BCM_88675_B0)
  46824     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88675_B0r */
  46825         soc_block_list[23],
  46826         soc_genreg,
  46827         1,
  46828         0,
  46829         0x103,
  46830         SOC_REG_FLAG_WO,
  46831         0,
  46832         15,
  46833         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88675_B0r_fields,
  46834         SOC_RESET_VAL_DEC(0x000040f3, 0x00000000)
  46835         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46836         -1,
  46837         -1,
  46838     },
  46839 #endif /* chips */
  46840 
  46841 #if defined(BCM_88680_A0)
  46842     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88680_A0r */
  46843         soc_block_list[23],
  46844         soc_genreg,
  46845         1,
  46846         0,
  46847         0x103,
  46848         SOC_REG_FLAG_WO,
  46849         0,
  46850         15,
  46851         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88680_A0r_fields,
  46852         SOC_RESET_VAL_DEC(0x000040f3, 0x00000000)
  46853         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  46854         -1,
  46855         -1,
  46856     },
  46857 #endif /* chips */
  46858 
  46859 #if defined(BCM_88690_A0)
  46860     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88690_A0r */
  46861         soc_block_list[23],
  46862         soc_genreg,
  46863         1,
  46864         0,
  46865         0x11b,
  46866         SOC_REG_FLAG_64_BITS |
  46867                           SOC_REG_FLAG_WO,
  46868         0,
  46869         25,
  46870         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88690_A0r_fields,
  46871         SOC_RESET_VAL_DEC(0x1899b0f3, 0x00001800)
  46872         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  46873         -1,
  46874         -1,
  46875     },
  46876 #endif /* chips */
  46877 
  46878 #if defined(BCM_88690_B0)
  46879     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88690_B0r */
  46880         soc_block_list[23],
  46881         soc_genreg,
  46882         1,
  46883         0,
  46884         0x11b,
  46885         SOC_REG_FLAG_64_BITS |
  46886                           SOC_REG_FLAG_WO,
  46887         0,
  46888         25,
  46889         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88690_B0r_fields,
  46890         SOC_RESET_VAL_DEC(0x1899b0f3, 0x00001800)
  46891         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  46892         -1,
  46893         -1,
  46894     },
  46895 #endif /* chips */
  46896 
  46897 #if defined(BCM_88790_A0)
  46898     { /* SOC_REG_INT_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88790_A0r */
  46899         soc_block_list[23],
  46900         soc_genreg,
  46901         1,
  46902         0,
  46903         0x11b,
  46904         SOC_REG_FLAG_64_BITS |
  46905                           SOC_REG_FLAG_WO,
  46906         0,
  46907         25,
  46908         soc_BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER_BCM88790_A0r_fields,
  46909         SOC_RESET_VAL_DEC(0x1899b0f3, 0x00001800)
  46910         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  46911         -1,
  46912         -1,
  46913     },
  46914 #endif /* chips */
  46915 
  46916 #if defined(BCM_88675_A0)
  46917     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_CFG_1r */
  46918         soc_block_list[23],
  46919         soc_genreg,
  46920         1,
  46921         0,
  46922         0xc1,
  46923         SOC_REG_FLAG_WO,
  46924         0,
  46925         3,
  46926         soc_BRDC_FMAC_GLOBAL_GENERAL_CFG_1r_fields,
  46927         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  46928         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46929         -1,
  46930         -1,
  46931     },
  46932 #endif /* chips */
  46933 
  46934 #if defined(BCM_88375_A0)
  46935     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88375_A0r */
  46936         soc_block_list[23],
  46937         soc_genreg,
  46938         1,
  46939         0,
  46940         0xc1,
  46941         SOC_REG_FLAG_WO,
  46942         0,
  46943         3,
  46944         soc_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88375_A0r_fields,
  46945         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  46946         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46947         -1,
  46948         -1,
  46949     },
  46950 #endif /* chips */
  46951 
  46952 #if defined(BCM_88375_B0)
  46953     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88375_B0r */
  46954         soc_block_list[23],
  46955         soc_genreg,
  46956         1,
  46957         0,
  46958         0xc1,
  46959         SOC_REG_FLAG_WO,
  46960         0,
  46961         3,
  46962         soc_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88375_B0r_fields,
  46963         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  46964         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46965         -1,
  46966         -1,
  46967     },
  46968 #endif /* chips */
  46969 
  46970 #if defined(BCM_88470_A0)
  46971     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88470_A0r */
  46972         soc_block_list[23],
  46973         soc_genreg,
  46974         1,
  46975         0,
  46976         0xc1,
  46977         SOC_REG_FLAG_WO,
  46978         0,
  46979         3,
  46980         soc_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88470_A0r_fields,
  46981         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  46982         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  46983         -1,
  46984         -1,
  46985     },
  46986 #endif /* chips */
  46987 
  46988 #if defined(BCM_88470_B0)
  46989     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88470_B0r */
  46990         soc_block_list[23],
  46991         soc_genreg,
  46992         1,
  46993         0,
  46994         0xc1,
  46995         SOC_REG_FLAG_WO,
  46996         0,
  46997         3,
  46998         soc_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88470_B0r_fields,
  46999         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  47000         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  47001         -1,
  47002         -1,
  47003     },
  47004 #endif /* chips */
  47005 
  47006 #if defined(BCM_88675_B0)
  47007     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88675_B0r */
  47008         soc_block_list[23],
  47009         soc_genreg,
  47010         1,
  47011         0,
  47012         0xc1,
  47013         SOC_REG_FLAG_WO,
  47014         0,
  47015         3,
  47016         soc_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88675_B0r_fields,
  47017         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  47018         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  47019         -1,
  47020         -1,
  47021     },
  47022 #endif /* chips */
  47023 
  47024 #if defined(BCM_88680_A0)
  47025     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88680_A0r */
  47026         soc_block_list[23],
  47027         soc_genreg,
  47028         1,
  47029         0,
  47030         0xc1,
  47031         SOC_REG_FLAG_WO,
  47032         0,
  47033         3,
  47034         soc_BRDC_FMAC_GLOBAL_GENERAL_CFG_1_BCM88680_A0r_fields,
  47035         SOC_RESET_VAL_DEC(0x00000c01, 0x00000000)
  47036         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  47037         -1,
  47038         -1,
  47039     },
  47040 #endif /* chips */
  47041 
  47042 #if defined(BCM_88675_A0)
  47043     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1r */
  47044         soc_block_list[23],
  47045         soc_genreg,
  47046         1,
  47047         0,
  47048         0xf4,
  47049         SOC_REG_FLAG_WO,
  47050         0,
  47051         8,
  47052         soc_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1r_fields,
  47053         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  47054         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  47055         -1,
  47056         -1,
  47057     },
  47058 #endif /* chips */
  47059 
  47060 #if defined(BCM_88375_A0)
  47061     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88375_A0r */
  47062         soc_block_list[23],
  47063         soc_genreg,
  47064         1,
  47065         0,
  47066         0xf4,
  47067         SOC_REG_FLAG_WO,
  47068         0,
  47069         8,
  47070         soc_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88375_A0r_fields,
  47071         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  47072         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  47073         -1,
  47074         -1,
  47075     },
  47076 #endif /* chips */
  47077 
  47078 #if defined(BCM_88375_B0)
  47079     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88375_B0r */
  47080         soc_block_list[23],
  47081         soc_genreg,
  47082         1,
  47083         0,
  47084         0xf4,
  47085         SOC_REG_FLAG_WO,
  47086         0,
  47087         8,
  47088         soc_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88375_B0r_fields,
  47089         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  47090         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  47091         -1,
  47092         -1,
  47093     },
  47094 #endif /* chips */
  47095 
  47096 #if defined(BCM_88675_B0)
  47097     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88675_B0r */
  47098         soc_block_list[23],
  47099         soc_genreg,
  47100         1,
  47101         0,
  47102         0xf4,
  47103         SOC_REG_FLAG_WO,
  47104         0,
  47105         8,
  47106         soc_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88675_B0r_fields,
  47107         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  47108         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  47109         -1,
  47110         -1,
  47111     },
  47112 #endif /* chips */
  47113 
  47114 #if defined(BCM_88680_A0)
  47115     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88680_A0r */
  47116         soc_block_list[23],
  47117         soc_genreg,
  47118         1,
  47119         0,
  47120         0xf4,
  47121         SOC_REG_FLAG_WO,
  47122         0,
  47123         8,
  47124         soc_BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1_BCM88680_A0r_fields,
  47125         SOC_RESET_VAL_DEC(0x00000018, 0x00000000)
  47126         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  47127         -1,
  47128         -1,
  47129     },
  47130 #endif /* chips */
  47131 
  47132 #if defined(BCM_88675_A0)
  47133     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONSr */
  47134         soc_block_list[23],
  47135         soc_genreg,
  47136         1,
  47137         0,
  47138         0xc0,
  47139         SOC_REG_FLAG_WO,
  47140         0,
  47141         4,
  47142         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONSr_fields,
  47143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47144         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47145         -1,
  47146         -1,
  47147     },
  47148 #endif /* chips */
  47149 
  47150 #if defined(BCM_83208_A0)
  47151     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM83208_A0r */
  47152         soc_block_list[23],
  47153         soc_genreg,
  47154         1,
  47155         0,
  47156         0xc0,
  47157         SOC_REG_FLAG_WO,
  47158         0,
  47159         6,
  47160         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM83208_A0r_fields,
  47161         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  47162         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47163         -1,
  47164         -1,
  47165     },
  47166 #endif /* chips */
  47167 
  47168 #if defined(BCM_88375_A0)
  47169     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88375_A0r */
  47170         soc_block_list[23],
  47171         soc_genreg,
  47172         1,
  47173         0,
  47174         0xc0,
  47175         SOC_REG_FLAG_WO,
  47176         0,
  47177         4,
  47178         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88375_A0r_fields,
  47179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47180         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47181         -1,
  47182         -1,
  47183     },
  47184 #endif /* chips */
  47185 
  47186 #if defined(BCM_88375_B0)
  47187     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88375_B0r */
  47188         soc_block_list[23],
  47189         soc_genreg,
  47190         1,
  47191         0,
  47192         0xc0,
  47193         SOC_REG_FLAG_WO,
  47194         0,
  47195         4,
  47196         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88375_B0r_fields,
  47197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47198         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47199         -1,
  47200         -1,
  47201     },
  47202 #endif /* chips */
  47203 
  47204 #if defined(BCM_88470_A0)
  47205     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88470_A0r */
  47206         soc_block_list[23],
  47207         soc_genreg,
  47208         1,
  47209         0,
  47210         0xc0,
  47211         SOC_REG_FLAG_WO,
  47212         0,
  47213         6,
  47214         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88470_A0r_fields,
  47215         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  47216         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47217         -1,
  47218         -1,
  47219     },
  47220 #endif /* chips */
  47221 
  47222 #if defined(BCM_88470_B0)
  47223     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88470_B0r */
  47224         soc_block_list[23],
  47225         soc_genreg,
  47226         1,
  47227         0,
  47228         0xc0,
  47229         SOC_REG_FLAG_WO,
  47230         0,
  47231         6,
  47232         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88470_B0r_fields,
  47233         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  47234         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47235         -1,
  47236         -1,
  47237     },
  47238 #endif /* chips */
  47239 
  47240 #if defined(BCM_88675_B0)
  47241     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88675_B0r */
  47242         soc_block_list[23],
  47243         soc_genreg,
  47244         1,
  47245         0,
  47246         0xc0,
  47247         SOC_REG_FLAG_WO,
  47248         0,
  47249         4,
  47250         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88675_B0r_fields,
  47251         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47252         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47253         -1,
  47254         -1,
  47255     },
  47256 #endif /* chips */
  47257 
  47258 #if defined(BCM_88680_A0)
  47259     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88680_A0r */
  47260         soc_block_list[23],
  47261         soc_genreg,
  47262         1,
  47263         0,
  47264         0xc0,
  47265         SOC_REG_FLAG_WO,
  47266         0,
  47267         4,
  47268         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88680_A0r_fields,
  47269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47270         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  47271         -1,
  47272         -1,
  47273     },
  47274 #endif /* chips */
  47275 
  47276 #if defined(BCM_88690_A0)
  47277     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88690_A0r */
  47278         soc_block_list[23],
  47279         soc_genreg,
  47280         1,
  47281         0,
  47282         0xc2,
  47283         SOC_REG_FLAG_WO,
  47284         0,
  47285         6,
  47286         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88690_A0r_fields,
  47287         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  47288         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47289         -1,
  47290         -1,
  47291     },
  47292 #endif /* chips */
  47293 
  47294 #if defined(BCM_88790_A0)
  47295     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88790_A0r */
  47296         soc_block_list[23],
  47297         soc_genreg,
  47298         1,
  47299         0,
  47300         0xc2,
  47301         SOC_REG_FLAG_WO,
  47302         0,
  47303         6,
  47304         soc_BRDC_FMAC_GLOBAL_MEM_OPTIONS_BCM88790_A0r_fields,
  47305         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  47306         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  47307         -1,
  47308         -1,
  47309     },
  47310 #endif /* chips */
  47311 
  47312 #if defined(BCM_88650_A0)
  47313     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRNr */
  47314         soc_block_list[23],
  47315         soc_genreg,
  47316         1,
  47317         0,
  47318         0x1d7,
  47319         SOC_REG_FLAG_ABOVE_64_BITS |
  47320                           SOC_REG_FLAG_WO,
  47321         0,
  47322         1,
  47323         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRNr_fields,
  47324         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47325         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47326         -1,
  47327         -1,
  47328     },
  47329 #endif /* chips */
  47330 
  47331 #if defined(BCM_83208_A0)
  47332     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM83208_A0r */
  47333         soc_block_list[23],
  47334         soc_genreg,
  47335         1,
  47336         0,
  47337         0x1d7,
  47338         SOC_REG_FLAG_ABOVE_64_BITS |
  47339                           SOC_REG_FLAG_WO,
  47340         0,
  47341         1,
  47342         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM83208_A0r_fields,
  47343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47344         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47345         -1,
  47346         -1,
  47347     },
  47348 #endif /* chips */
  47349 
  47350 #if defined(BCM_88202_A0)
  47351     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88202_A0r */
  47352         soc_block_list[23],
  47353         soc_genreg,
  47354         1,
  47355         0,
  47356         0x1d7,
  47357         SOC_REG_FLAG_ABOVE_64_BITS |
  47358                           SOC_REG_FLAG_WO,
  47359         0,
  47360         1,
  47361         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88202_A0r_fields,
  47362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47363         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47364         -1,
  47365         -1,
  47366     },
  47367 #endif /* chips */
  47368 
  47369 #if defined(BCM_88375_A0)
  47370     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88375_A0r */
  47371         soc_block_list[23],
  47372         soc_genreg,
  47373         1,
  47374         0,
  47375         0x1d7,
  47376         SOC_REG_FLAG_ABOVE_64_BITS |
  47377                           SOC_REG_FLAG_WO,
  47378         0,
  47379         1,
  47380         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88375_A0r_fields,
  47381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47382         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47383         -1,
  47384         -1,
  47385     },
  47386 #endif /* chips */
  47387 
  47388 #if defined(BCM_88375_B0)
  47389     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88375_B0r */
  47390         soc_block_list[23],
  47391         soc_genreg,
  47392         1,
  47393         0,
  47394         0x1d7,
  47395         SOC_REG_FLAG_ABOVE_64_BITS |
  47396                           SOC_REG_FLAG_WO,
  47397         0,
  47398         1,
  47399         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88375_B0r_fields,
  47400         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47401         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47402         -1,
  47403         -1,
  47404     },
  47405 #endif /* chips */
  47406 
  47407 #if defined(BCM_88470_A0)
  47408     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88470_A0r */
  47409         soc_block_list[23],
  47410         soc_genreg,
  47411         1,
  47412         0,
  47413         0x1d7,
  47414         SOC_REG_FLAG_ABOVE_64_BITS |
  47415                           SOC_REG_FLAG_WO,
  47416         0,
  47417         1,
  47418         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88470_A0r_fields,
  47419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47421         -1,
  47422         -1,
  47423     },
  47424 #endif /* chips */
  47425 
  47426 #if defined(BCM_88470_B0)
  47427     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88470_B0r */
  47428         soc_block_list[23],
  47429         soc_genreg,
  47430         1,
  47431         0,
  47432         0x1d7,
  47433         SOC_REG_FLAG_ABOVE_64_BITS |
  47434                           SOC_REG_FLAG_WO,
  47435         0,
  47436         1,
  47437         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88470_B0r_fields,
  47438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47439         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47440         -1,
  47441         -1,
  47442     },
  47443 #endif /* chips */
  47444 
  47445 #if defined(BCM_88650_B0)
  47446     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88650_B0r */
  47447         soc_block_list[23],
  47448         soc_genreg,
  47449         1,
  47450         0,
  47451         0x1d7,
  47452         SOC_REG_FLAG_ABOVE_64_BITS |
  47453                           SOC_REG_FLAG_WO,
  47454         0,
  47455         1,
  47456         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88650_B0r_fields,
  47457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47458         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47459         -1,
  47460         -1,
  47461     },
  47462 #endif /* chips */
  47463 
  47464 #if defined(BCM_88660_A0)
  47465     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88660_A0r */
  47466         soc_block_list[23],
  47467         soc_genreg,
  47468         1,
  47469         0,
  47470         0x1d7,
  47471         SOC_REG_FLAG_ABOVE_64_BITS |
  47472                           SOC_REG_FLAG_WO,
  47473         0,
  47474         1,
  47475         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88660_A0r_fields,
  47476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47477         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47478         -1,
  47479         -1,
  47480     },
  47481 #endif /* chips */
  47482 
  47483 #if defined(BCM_88675_A0)
  47484     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88675_A0r */
  47485         soc_block_list[23],
  47486         soc_genreg,
  47487         1,
  47488         0,
  47489         0x1d7,
  47490         SOC_REG_FLAG_ABOVE_64_BITS |
  47491                           SOC_REG_FLAG_WO,
  47492         0,
  47493         1,
  47494         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88675_A0r_fields,
  47495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47496         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47497         -1,
  47498         -1,
  47499     },
  47500 #endif /* chips */
  47501 
  47502 #if defined(BCM_88675_B0)
  47503     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88675_B0r */
  47504         soc_block_list[23],
  47505         soc_genreg,
  47506         1,
  47507         0,
  47508         0x1d7,
  47509         SOC_REG_FLAG_ABOVE_64_BITS |
  47510                           SOC_REG_FLAG_WO,
  47511         0,
  47512         1,
  47513         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88675_B0r_fields,
  47514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47515         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47516         -1,
  47517         -1,
  47518     },
  47519 #endif /* chips */
  47520 
  47521 #if defined(BCM_88680_A0)
  47522     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88680_A0r */
  47523         soc_block_list[23],
  47524         soc_genreg,
  47525         1,
  47526         0,
  47527         0x1d7,
  47528         SOC_REG_FLAG_ABOVE_64_BITS |
  47529                           SOC_REG_FLAG_WO,
  47530         0,
  47531         1,
  47532         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88680_A0r_fields,
  47533         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47534         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47535         -1,
  47536         -1,
  47537     },
  47538 #endif /* chips */
  47539 
  47540 #if defined(BCM_88690_A0)
  47541     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88690_A0r */
  47542         soc_block_list[23],
  47543         soc_genreg,
  47544         1,
  47545         0,
  47546         0x1e1,
  47547         SOC_REG_FLAG_ABOVE_64_BITS |
  47548                           SOC_REG_FLAG_WO,
  47549         0,
  47550         1,
  47551         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88690_A0r_fields,
  47552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47553         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47554         -1,
  47555         -1,
  47556     },
  47557 #endif /* chips */
  47558 
  47559 #if defined(BCM_88690_B0)
  47560     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88690_B0r */
  47561         soc_block_list[23],
  47562         soc_genreg,
  47563         1,
  47564         0,
  47565         0x1e1,
  47566         SOC_REG_FLAG_ABOVE_64_BITS |
  47567                           SOC_REG_FLAG_WO,
  47568         0,
  47569         1,
  47570         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88690_B0r_fields,
  47571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47572         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47573         -1,
  47574         -1,
  47575     },
  47576 #endif /* chips */
  47577 
  47578 #if defined(BCM_88790_A0)
  47579     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88790_A0r */
  47580         soc_block_list[23],
  47581         soc_genreg,
  47582         1,
  47583         0,
  47584         0x1e1,
  47585         SOC_REG_FLAG_ABOVE_64_BITS |
  47586                           SOC_REG_FLAG_WO,
  47587         0,
  47588         1,
  47589         soc_BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN_BCM88790_A0r_fields,
  47590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47591         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47592         -1,
  47593         -1,
  47594     },
  47595 #endif /* chips */
  47596 
  47597 #if defined(BCM_88650_A0)
  47598     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRNr */
  47599         soc_block_list[23],
  47600         soc_genreg,
  47601         1,
  47602         0,
  47603         0x1d4,
  47604         SOC_REG_FLAG_ABOVE_64_BITS |
  47605                           SOC_REG_FLAG_WO,
  47606         0,
  47607         1,
  47608         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRNr_fields,
  47609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47610         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47611         -1,
  47612         -1,
  47613     },
  47614 #endif /* chips */
  47615 
  47616 #if defined(BCM_83208_A0)
  47617     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM83208_A0r */
  47618         soc_block_list[23],
  47619         soc_genreg,
  47620         1,
  47621         0,
  47622         0x1d4,
  47623         SOC_REG_FLAG_ABOVE_64_BITS |
  47624                           SOC_REG_FLAG_WO,
  47625         0,
  47626         1,
  47627         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM83208_A0r_fields,
  47628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47629         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47630         -1,
  47631         -1,
  47632     },
  47633 #endif /* chips */
  47634 
  47635 #if defined(BCM_88202_A0)
  47636     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88202_A0r */
  47637         soc_block_list[23],
  47638         soc_genreg,
  47639         1,
  47640         0,
  47641         0x1d4,
  47642         SOC_REG_FLAG_ABOVE_64_BITS |
  47643                           SOC_REG_FLAG_WO,
  47644         0,
  47645         1,
  47646         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88202_A0r_fields,
  47647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47649         -1,
  47650         -1,
  47651     },
  47652 #endif /* chips */
  47653 
  47654 #if defined(BCM_88375_A0)
  47655     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88375_A0r */
  47656         soc_block_list[23],
  47657         soc_genreg,
  47658         1,
  47659         0,
  47660         0x1d4,
  47661         SOC_REG_FLAG_ABOVE_64_BITS |
  47662                           SOC_REG_FLAG_WO,
  47663         0,
  47664         1,
  47665         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88375_A0r_fields,
  47666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47667         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47668         -1,
  47669         -1,
  47670     },
  47671 #endif /* chips */
  47672 
  47673 #if defined(BCM_88375_B0)
  47674     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88375_B0r */
  47675         soc_block_list[23],
  47676         soc_genreg,
  47677         1,
  47678         0,
  47679         0x1d4,
  47680         SOC_REG_FLAG_ABOVE_64_BITS |
  47681                           SOC_REG_FLAG_WO,
  47682         0,
  47683         1,
  47684         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88375_B0r_fields,
  47685         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47686         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47687         -1,
  47688         -1,
  47689     },
  47690 #endif /* chips */
  47691 
  47692 #if defined(BCM_88470_A0)
  47693     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88470_A0r */
  47694         soc_block_list[23],
  47695         soc_genreg,
  47696         1,
  47697         0,
  47698         0x1d4,
  47699         SOC_REG_FLAG_ABOVE_64_BITS |
  47700                           SOC_REG_FLAG_WO,
  47701         0,
  47702         1,
  47703         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88470_A0r_fields,
  47704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47705         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47706         -1,
  47707         -1,
  47708     },
  47709 #endif /* chips */
  47710 
  47711 #if defined(BCM_88470_B0)
  47712     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88470_B0r */
  47713         soc_block_list[23],
  47714         soc_genreg,
  47715         1,
  47716         0,
  47717         0x1d4,
  47718         SOC_REG_FLAG_ABOVE_64_BITS |
  47719                           SOC_REG_FLAG_WO,
  47720         0,
  47721         1,
  47722         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88470_B0r_fields,
  47723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47724         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47725         -1,
  47726         -1,
  47727     },
  47728 #endif /* chips */
  47729 
  47730 #if defined(BCM_88650_B0)
  47731     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88650_B0r */
  47732         soc_block_list[23],
  47733         soc_genreg,
  47734         1,
  47735         0,
  47736         0x1d4,
  47737         SOC_REG_FLAG_ABOVE_64_BITS |
  47738                           SOC_REG_FLAG_WO,
  47739         0,
  47740         1,
  47741         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88650_B0r_fields,
  47742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47743         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47744         -1,
  47745         -1,
  47746     },
  47747 #endif /* chips */
  47748 
  47749 #if defined(BCM_88660_A0)
  47750     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88660_A0r */
  47751         soc_block_list[23],
  47752         soc_genreg,
  47753         1,
  47754         0,
  47755         0x1d4,
  47756         SOC_REG_FLAG_ABOVE_64_BITS |
  47757                           SOC_REG_FLAG_WO,
  47758         0,
  47759         1,
  47760         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88660_A0r_fields,
  47761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47762         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47763         -1,
  47764         -1,
  47765     },
  47766 #endif /* chips */
  47767 
  47768 #if defined(BCM_88675_A0)
  47769     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88675_A0r */
  47770         soc_block_list[23],
  47771         soc_genreg,
  47772         1,
  47773         0,
  47774         0x1d4,
  47775         SOC_REG_FLAG_ABOVE_64_BITS |
  47776                           SOC_REG_FLAG_WO,
  47777         0,
  47778         1,
  47779         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88675_A0r_fields,
  47780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47781         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47782         -1,
  47783         -1,
  47784     },
  47785 #endif /* chips */
  47786 
  47787 #if defined(BCM_88675_B0)
  47788     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88675_B0r */
  47789         soc_block_list[23],
  47790         soc_genreg,
  47791         1,
  47792         0,
  47793         0x1d4,
  47794         SOC_REG_FLAG_ABOVE_64_BITS |
  47795                           SOC_REG_FLAG_WO,
  47796         0,
  47797         1,
  47798         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88675_B0r_fields,
  47799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47801         -1,
  47802         -1,
  47803     },
  47804 #endif /* chips */
  47805 
  47806 #if defined(BCM_88680_A0)
  47807     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88680_A0r */
  47808         soc_block_list[23],
  47809         soc_genreg,
  47810         1,
  47811         0,
  47812         0x1d4,
  47813         SOC_REG_FLAG_ABOVE_64_BITS |
  47814                           SOC_REG_FLAG_WO,
  47815         0,
  47816         1,
  47817         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88680_A0r_fields,
  47818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47819         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47820         -1,
  47821         -1,
  47822     },
  47823 #endif /* chips */
  47824 
  47825 #if defined(BCM_88690_A0)
  47826     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88690_A0r */
  47827         soc_block_list[23],
  47828         soc_genreg,
  47829         1,
  47830         0,
  47831         0x1de,
  47832         SOC_REG_FLAG_ABOVE_64_BITS |
  47833                           SOC_REG_FLAG_WO,
  47834         0,
  47835         1,
  47836         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88690_A0r_fields,
  47837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47838         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47839         -1,
  47840         -1,
  47841     },
  47842 #endif /* chips */
  47843 
  47844 #if defined(BCM_88690_B0)
  47845     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88690_B0r */
  47846         soc_block_list[23],
  47847         soc_genreg,
  47848         1,
  47849         0,
  47850         0x1de,
  47851         SOC_REG_FLAG_ABOVE_64_BITS |
  47852                           SOC_REG_FLAG_WO,
  47853         0,
  47854         1,
  47855         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88690_B0r_fields,
  47856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47858         -1,
  47859         -1,
  47860     },
  47861 #endif /* chips */
  47862 
  47863 #if defined(BCM_88790_A0)
  47864     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88790_A0r */
  47865         soc_block_list[23],
  47866         soc_genreg,
  47867         1,
  47868         0,
  47869         0x1de,
  47870         SOC_REG_FLAG_ABOVE_64_BITS |
  47871                           SOC_REG_FLAG_WO,
  47872         0,
  47873         1,
  47874         soc_BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN_BCM88790_A0r_fields,
  47875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  47876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  47877         -1,
  47878         -1,
  47879     },
  47880 #endif /* chips */
  47881 
  47882 #if defined(BCM_88650_A0)
  47883     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_Ar */
  47884         soc_block_list[23],
  47885         soc_genreg,
  47886         1,
  47887         0,
  47888         0x1d0,
  47889         SOC_REG_FLAG_64_BITS |
  47890                           SOC_REG_FLAG_WO,
  47891         0,
  47892         1,
  47893         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_Ar_fields,
  47894         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  47895         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  47896         -1,
  47897         -1,
  47898     },
  47899 #endif /* chips */
  47900 
  47901 #if defined(BCM_83208_A0)
  47902     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM83208_A0r */
  47903         soc_block_list[23],
  47904         soc_genreg,
  47905         1,
  47906         0,
  47907         0x1d0,
  47908         SOC_REG_FLAG_64_BITS |
  47909                           SOC_REG_FLAG_WO,
  47910         0,
  47911         1,
  47912         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM83208_A0r_fields,
  47913         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  47914         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  47915         -1,
  47916         -1,
  47917     },
  47918 #endif /* chips */
  47919 
  47920 #if defined(BCM_88202_A0)
  47921     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88202_A0r */
  47922         soc_block_list[23],
  47923         soc_genreg,
  47924         1,
  47925         0,
  47926         0x1d0,
  47927         SOC_REG_FLAG_64_BITS |
  47928                           SOC_REG_FLAG_WO,
  47929         0,
  47930         1,
  47931         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88202_A0r_fields,
  47932         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  47933         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  47934         -1,
  47935         -1,
  47936     },
  47937 #endif /* chips */
  47938 
  47939 #if defined(BCM_88375_A0)
  47940     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88375_A0r */
  47941         soc_block_list[23],
  47942         soc_genreg,
  47943         1,
  47944         0,
  47945         0x1d0,
  47946         SOC_REG_FLAG_64_BITS |
  47947                           SOC_REG_FLAG_WO,
  47948         0,
  47949         1,
  47950         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88375_A0r_fields,
  47951         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  47952         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  47953         -1,
  47954         -1,
  47955     },
  47956 #endif /* chips */
  47957 
  47958 #if defined(BCM_88375_B0)
  47959     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88375_B0r */
  47960         soc_block_list[23],
  47961         soc_genreg,
  47962         1,
  47963         0,
  47964         0x1d0,
  47965         SOC_REG_FLAG_64_BITS |
  47966                           SOC_REG_FLAG_WO,
  47967         0,
  47968         1,
  47969         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88375_B0r_fields,
  47970         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  47971         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  47972         -1,
  47973         -1,
  47974     },
  47975 #endif /* chips */
  47976 
  47977 #if defined(BCM_88470_A0)
  47978     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88470_A0r */
  47979         soc_block_list[23],
  47980         soc_genreg,
  47981         1,
  47982         0,
  47983         0x1d0,
  47984         SOC_REG_FLAG_64_BITS |
  47985                           SOC_REG_FLAG_WO,
  47986         0,
  47987         1,
  47988         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88470_A0r_fields,
  47989         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  47990         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  47991         -1,
  47992         -1,
  47993     },
  47994 #endif /* chips */
  47995 
  47996 #if defined(BCM_88470_B0)
  47997     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88470_B0r */
  47998         soc_block_list[23],
  47999         soc_genreg,
  48000         1,
  48001         0,
  48002         0x1d0,
  48003         SOC_REG_FLAG_64_BITS |
  48004                           SOC_REG_FLAG_WO,
  48005         0,
  48006         1,
  48007         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88470_B0r_fields,
  48008         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48009         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48010         -1,
  48011         -1,
  48012     },
  48013 #endif /* chips */
  48014 
  48015 #if defined(BCM_88650_B0)
  48016     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88650_B0r */
  48017         soc_block_list[23],
  48018         soc_genreg,
  48019         1,
  48020         0,
  48021         0x1d0,
  48022         SOC_REG_FLAG_64_BITS |
  48023                           SOC_REG_FLAG_WO,
  48024         0,
  48025         1,
  48026         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88650_B0r_fields,
  48027         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48028         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48029         -1,
  48030         -1,
  48031     },
  48032 #endif /* chips */
  48033 
  48034 #if defined(BCM_88660_A0)
  48035     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88660_A0r */
  48036         soc_block_list[23],
  48037         soc_genreg,
  48038         1,
  48039         0,
  48040         0x1d0,
  48041         SOC_REG_FLAG_64_BITS |
  48042                           SOC_REG_FLAG_WO,
  48043         0,
  48044         1,
  48045         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88660_A0r_fields,
  48046         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48047         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48048         -1,
  48049         -1,
  48050     },
  48051 #endif /* chips */
  48052 
  48053 #if defined(BCM_88675_A0)
  48054     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88675_A0r */
  48055         soc_block_list[23],
  48056         soc_genreg,
  48057         1,
  48058         0,
  48059         0x1d0,
  48060         SOC_REG_FLAG_64_BITS |
  48061                           SOC_REG_FLAG_WO,
  48062         0,
  48063         1,
  48064         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88675_A0r_fields,
  48065         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48066         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48067         -1,
  48068         -1,
  48069     },
  48070 #endif /* chips */
  48071 
  48072 #if defined(BCM_88675_B0)
  48073     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88675_B0r */
  48074         soc_block_list[23],
  48075         soc_genreg,
  48076         1,
  48077         0,
  48078         0x1d0,
  48079         SOC_REG_FLAG_64_BITS |
  48080                           SOC_REG_FLAG_WO,
  48081         0,
  48082         1,
  48083         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88675_B0r_fields,
  48084         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48085         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48086         -1,
  48087         -1,
  48088     },
  48089 #endif /* chips */
  48090 
  48091 #if defined(BCM_88680_A0)
  48092     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88680_A0r */
  48093         soc_block_list[23],
  48094         soc_genreg,
  48095         1,
  48096         0,
  48097         0x1d0,
  48098         SOC_REG_FLAG_64_BITS |
  48099                           SOC_REG_FLAG_WO,
  48100         0,
  48101         1,
  48102         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88680_A0r_fields,
  48103         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48104         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48105         -1,
  48106         -1,
  48107     },
  48108 #endif /* chips */
  48109 
  48110 #if defined(BCM_88690_A0)
  48111     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88690_A0r */
  48112         soc_block_list[23],
  48113         soc_genreg,
  48114         1,
  48115         0,
  48116         0x1da,
  48117         SOC_REG_FLAG_64_BITS |
  48118                           SOC_REG_FLAG_WO,
  48119         0,
  48120         1,
  48121         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88690_A0r_fields,
  48122         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48123         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48124         -1,
  48125         -1,
  48126     },
  48127 #endif /* chips */
  48128 
  48129 #if defined(BCM_88690_B0)
  48130     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88690_B0r */
  48131         soc_block_list[23],
  48132         soc_genreg,
  48133         1,
  48134         0,
  48135         0x1da,
  48136         SOC_REG_FLAG_64_BITS |
  48137                           SOC_REG_FLAG_WO,
  48138         0,
  48139         1,
  48140         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88690_B0r_fields,
  48141         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48142         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48143         -1,
  48144         -1,
  48145     },
  48146 #endif /* chips */
  48147 
  48148 #if defined(BCM_88790_A0)
  48149     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88790_A0r */
  48150         soc_block_list[23],
  48151         soc_genreg,
  48152         1,
  48153         0,
  48154         0x1da,
  48155         SOC_REG_FLAG_64_BITS |
  48156                           SOC_REG_FLAG_WO,
  48157         0,
  48158         1,
  48159         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A_BCM88790_A0r_fields,
  48160         SOC_RESET_VAL_DEC(0x0000cccc, 0x00000000)
  48161         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48162         -1,
  48163         -1,
  48164     },
  48165 #endif /* chips */
  48166 
  48167 #if defined(BCM_88650_A0)
  48168     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_Br */
  48169         soc_block_list[23],
  48170         soc_genreg,
  48171         1,
  48172         0,
  48173         0x1d2,
  48174         SOC_REG_FLAG_64_BITS |
  48175                           SOC_REG_FLAG_WO,
  48176         0,
  48177         1,
  48178         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_Br_fields,
  48179         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48180         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48181         -1,
  48182         -1,
  48183     },
  48184 #endif /* chips */
  48185 
  48186 #if defined(BCM_83208_A0)
  48187     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM83208_A0r */
  48188         soc_block_list[23],
  48189         soc_genreg,
  48190         1,
  48191         0,
  48192         0x1d2,
  48193         SOC_REG_FLAG_64_BITS |
  48194                           SOC_REG_FLAG_WO,
  48195         0,
  48196         1,
  48197         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM83208_A0r_fields,
  48198         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48199         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48200         -1,
  48201         -1,
  48202     },
  48203 #endif /* chips */
  48204 
  48205 #if defined(BCM_88202_A0)
  48206     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88202_A0r */
  48207         soc_block_list[23],
  48208         soc_genreg,
  48209         1,
  48210         0,
  48211         0x1d2,
  48212         SOC_REG_FLAG_64_BITS |
  48213                           SOC_REG_FLAG_WO,
  48214         0,
  48215         1,
  48216         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88202_A0r_fields,
  48217         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48218         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48219         -1,
  48220         -1,
  48221     },
  48222 #endif /* chips */
  48223 
  48224 #if defined(BCM_88375_A0)
  48225     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88375_A0r */
  48226         soc_block_list[23],
  48227         soc_genreg,
  48228         1,
  48229         0,
  48230         0x1d2,
  48231         SOC_REG_FLAG_64_BITS |
  48232                           SOC_REG_FLAG_WO,
  48233         0,
  48234         1,
  48235         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88375_A0r_fields,
  48236         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48237         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48238         -1,
  48239         -1,
  48240     },
  48241 #endif /* chips */
  48242 
  48243 #if defined(BCM_88375_B0)
  48244     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88375_B0r */
  48245         soc_block_list[23],
  48246         soc_genreg,
  48247         1,
  48248         0,
  48249         0x1d2,
  48250         SOC_REG_FLAG_64_BITS |
  48251                           SOC_REG_FLAG_WO,
  48252         0,
  48253         1,
  48254         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88375_B0r_fields,
  48255         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48256         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48257         -1,
  48258         -1,
  48259     },
  48260 #endif /* chips */
  48261 
  48262 #if defined(BCM_88470_A0)
  48263     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88470_A0r */
  48264         soc_block_list[23],
  48265         soc_genreg,
  48266         1,
  48267         0,
  48268         0x1d2,
  48269         SOC_REG_FLAG_64_BITS |
  48270                           SOC_REG_FLAG_WO,
  48271         0,
  48272         1,
  48273         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88470_A0r_fields,
  48274         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48275         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48276         -1,
  48277         -1,
  48278     },
  48279 #endif /* chips */
  48280 
  48281 #if defined(BCM_88470_B0)
  48282     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88470_B0r */
  48283         soc_block_list[23],
  48284         soc_genreg,
  48285         1,
  48286         0,
  48287         0x1d2,
  48288         SOC_REG_FLAG_64_BITS |
  48289                           SOC_REG_FLAG_WO,
  48290         0,
  48291         1,
  48292         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88470_B0r_fields,
  48293         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48294         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48295         -1,
  48296         -1,
  48297     },
  48298 #endif /* chips */
  48299 
  48300 #if defined(BCM_88650_B0)
  48301     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88650_B0r */
  48302         soc_block_list[23],
  48303         soc_genreg,
  48304         1,
  48305         0,
  48306         0x1d2,
  48307         SOC_REG_FLAG_64_BITS |
  48308                           SOC_REG_FLAG_WO,
  48309         0,
  48310         1,
  48311         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88650_B0r_fields,
  48312         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48313         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48314         -1,
  48315         -1,
  48316     },
  48317 #endif /* chips */
  48318 
  48319 #if defined(BCM_88660_A0)
  48320     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88660_A0r */
  48321         soc_block_list[23],
  48322         soc_genreg,
  48323         1,
  48324         0,
  48325         0x1d2,
  48326         SOC_REG_FLAG_64_BITS |
  48327                           SOC_REG_FLAG_WO,
  48328         0,
  48329         1,
  48330         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88660_A0r_fields,
  48331         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48332         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48333         -1,
  48334         -1,
  48335     },
  48336 #endif /* chips */
  48337 
  48338 #if defined(BCM_88675_A0)
  48339     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88675_A0r */
  48340         soc_block_list[23],
  48341         soc_genreg,
  48342         1,
  48343         0,
  48344         0x1d2,
  48345         SOC_REG_FLAG_64_BITS |
  48346                           SOC_REG_FLAG_WO,
  48347         0,
  48348         1,
  48349         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88675_A0r_fields,
  48350         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48351         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48352         -1,
  48353         -1,
  48354     },
  48355 #endif /* chips */
  48356 
  48357 #if defined(BCM_88675_B0)
  48358     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88675_B0r */
  48359         soc_block_list[23],
  48360         soc_genreg,
  48361         1,
  48362         0,
  48363         0x1d2,
  48364         SOC_REG_FLAG_64_BITS |
  48365                           SOC_REG_FLAG_WO,
  48366         0,
  48367         1,
  48368         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88675_B0r_fields,
  48369         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48370         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48371         -1,
  48372         -1,
  48373     },
  48374 #endif /* chips */
  48375 
  48376 #if defined(BCM_88680_A0)
  48377     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88680_A0r */
  48378         soc_block_list[23],
  48379         soc_genreg,
  48380         1,
  48381         0,
  48382         0x1d2,
  48383         SOC_REG_FLAG_64_BITS |
  48384                           SOC_REG_FLAG_WO,
  48385         0,
  48386         1,
  48387         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88680_A0r_fields,
  48388         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48389         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48390         -1,
  48391         -1,
  48392     },
  48393 #endif /* chips */
  48394 
  48395 #if defined(BCM_88690_A0)
  48396     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88690_A0r */
  48397         soc_block_list[23],
  48398         soc_genreg,
  48399         1,
  48400         0,
  48401         0x1dc,
  48402         SOC_REG_FLAG_64_BITS |
  48403                           SOC_REG_FLAG_WO,
  48404         0,
  48405         1,
  48406         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88690_A0r_fields,
  48407         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48408         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48409         -1,
  48410         -1,
  48411     },
  48412 #endif /* chips */
  48413 
  48414 #if defined(BCM_88690_B0)
  48415     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88690_B0r */
  48416         soc_block_list[23],
  48417         soc_genreg,
  48418         1,
  48419         0,
  48420         0x1dc,
  48421         SOC_REG_FLAG_64_BITS |
  48422                           SOC_REG_FLAG_WO,
  48423         0,
  48424         1,
  48425         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88690_B0r_fields,
  48426         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48427         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48428         -1,
  48429         -1,
  48430     },
  48431 #endif /* chips */
  48432 
  48433 #if defined(BCM_88790_A0)
  48434     { /* SOC_REG_INT_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88790_A0r */
  48435         soc_block_list[23],
  48436         soc_genreg,
  48437         1,
  48438         0,
  48439         0x1dc,
  48440         SOC_REG_FLAG_64_BITS |
  48441                           SOC_REG_FLAG_WO,
  48442         0,
  48443         1,
  48444         soc_BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B_BCM88790_A0r_fields,
  48445         SOC_RESET_VAL_DEC(0x00003333, 0x00000000)
  48446         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  48447         -1,
  48448         -1,
  48449     },
  48450 #endif /* chips */
  48451 
  48452 #if defined(BCM_88675_A0)
  48453     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFFr */
  48454         soc_block_list[23],
  48455         soc_genreg,
  48456         1,
  48457         0,
  48458         0x105,
  48459         SOC_REG_FLAG_WO,
  48460         0,
  48461         3,
  48462         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFFr_fields,
  48463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48464         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48465         -1,
  48466         -1,
  48467     },
  48468 #endif /* chips */
  48469 
  48470 #if defined(BCM_83208_A0)
  48471     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM83208_A0r */
  48472         soc_block_list[23],
  48473         soc_genreg,
  48474         1,
  48475         0,
  48476         0x105,
  48477         SOC_REG_FLAG_WO,
  48478         0,
  48479         3,
  48480         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM83208_A0r_fields,
  48481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48482         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48483         -1,
  48484         -1,
  48485     },
  48486 #endif /* chips */
  48487 
  48488 #if defined(BCM_88375_A0)
  48489     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88375_A0r */
  48490         soc_block_list[23],
  48491         soc_genreg,
  48492         1,
  48493         0,
  48494         0x105,
  48495         SOC_REG_FLAG_WO,
  48496         0,
  48497         3,
  48498         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88375_A0r_fields,
  48499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48500         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48501         -1,
  48502         -1,
  48503     },
  48504 #endif /* chips */
  48505 
  48506 #if defined(BCM_88375_B0)
  48507     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88375_B0r */
  48508         soc_block_list[23],
  48509         soc_genreg,
  48510         1,
  48511         0,
  48512         0x105,
  48513         SOC_REG_FLAG_WO,
  48514         0,
  48515         3,
  48516         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88375_B0r_fields,
  48517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48518         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48519         -1,
  48520         -1,
  48521     },
  48522 #endif /* chips */
  48523 
  48524 #if defined(BCM_88470_A0)
  48525     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88470_A0r */
  48526         soc_block_list[23],
  48527         soc_genreg,
  48528         1,
  48529         0,
  48530         0x105,
  48531         SOC_REG_FLAG_WO,
  48532         0,
  48533         3,
  48534         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88470_A0r_fields,
  48535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48536         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48537         -1,
  48538         -1,
  48539     },
  48540 #endif /* chips */
  48541 
  48542 #if defined(BCM_88470_B0)
  48543     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88470_B0r */
  48544         soc_block_list[23],
  48545         soc_genreg,
  48546         1,
  48547         0,
  48548         0x105,
  48549         SOC_REG_FLAG_WO,
  48550         0,
  48551         3,
  48552         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88470_B0r_fields,
  48553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48554         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48555         -1,
  48556         -1,
  48557     },
  48558 #endif /* chips */
  48559 
  48560 #if defined(BCM_88675_B0)
  48561     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88675_B0r */
  48562         soc_block_list[23],
  48563         soc_genreg,
  48564         1,
  48565         0,
  48566         0x105,
  48567         SOC_REG_FLAG_WO,
  48568         0,
  48569         3,
  48570         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88675_B0r_fields,
  48571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48572         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48573         -1,
  48574         -1,
  48575     },
  48576 #endif /* chips */
  48577 
  48578 #if defined(BCM_88680_A0)
  48579     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88680_A0r */
  48580         soc_block_list[23],
  48581         soc_genreg,
  48582         1,
  48583         0,
  48584         0x105,
  48585         SOC_REG_FLAG_WO,
  48586         0,
  48587         3,
  48588         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88680_A0r_fields,
  48589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48590         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48591         -1,
  48592         -1,
  48593     },
  48594 #endif /* chips */
  48595 
  48596 #if defined(BCM_88690_A0)
  48597     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88690_A0r */
  48598         soc_block_list[23],
  48599         soc_genreg,
  48600         1,
  48601         0,
  48602         0x125,
  48603         SOC_REG_FLAG_WO,
  48604         0,
  48605         3,
  48606         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88690_A0r_fields,
  48607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48608         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48609         -1,
  48610         -1,
  48611     },
  48612 #endif /* chips */
  48613 
  48614 #if defined(BCM_88690_B0)
  48615     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88690_B0r */
  48616         soc_block_list[23],
  48617         soc_genreg,
  48618         1,
  48619         0,
  48620         0x125,
  48621         SOC_REG_FLAG_WO,
  48622         0,
  48623         3,
  48624         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88690_B0r_fields,
  48625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48626         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48627         -1,
  48628         -1,
  48629     },
  48630 #endif /* chips */
  48631 
  48632 #if defined(BCM_88790_A0)
  48633     { /* SOC_REG_INT_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88790_A0r */
  48634         soc_block_list[23],
  48635         soc_genreg,
  48636         1,
  48637         0,
  48638         0x125,
  48639         SOC_REG_FLAG_WO,
  48640         0,
  48641         3,
  48642         soc_BRDC_FMAC_GRACEFULL_POWER_ON_OFF_BCM88790_A0r_fields,
  48643         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48644         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  48645         -1,
  48646         -1,
  48647     },
  48648 #endif /* chips */
  48649 
  48650 #if defined(BCM_88650_A0)
  48651     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATIONr */
  48652         soc_block_list[23],
  48653         soc_genreg,
  48654         1,
  48655         0,
  48656         0x56,
  48657         SOC_REG_FLAG_WO,
  48658         0,
  48659         3,
  48660         soc_BRDC_FMAC_GTIMER_CONFIGURATIONr_fields,
  48661         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  48662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48663         -1,
  48664         -1,
  48665     },
  48666 #endif /* chips */
  48667 
  48668 #if defined(BCM_83208_A0)
  48669     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM83208_A0r */
  48670         soc_block_list[23],
  48671         soc_genreg,
  48672         1,
  48673         0,
  48674         0x88,
  48675         SOC_REG_FLAG_WO,
  48676         0,
  48677         4,
  48678         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM83208_A0r_fields,
  48679         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48680         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  48681         -1,
  48682         -1,
  48683     },
  48684 #endif /* chips */
  48685 
  48686 #if defined(BCM_88202_A0)
  48687     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88202_A0r */
  48688         soc_block_list[23],
  48689         soc_genreg,
  48690         1,
  48691         0,
  48692         0x56,
  48693         SOC_REG_FLAG_WO,
  48694         0,
  48695         3,
  48696         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88202_A0r_fields,
  48697         SOC_RESET_VAL_DEC(0x1ad27480, 0x00000000)
  48698         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48699         -1,
  48700         -1,
  48701     },
  48702 #endif /* chips */
  48703 
  48704 #if defined(BCM_88375_A0)
  48705     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88375_A0r */
  48706         soc_block_list[23],
  48707         soc_genreg,
  48708         1,
  48709         0,
  48710         0x88,
  48711         SOC_REG_FLAG_WO,
  48712         0,
  48713         3,
  48714         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88375_A0r_fields,
  48715         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48716         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48717         -1,
  48718         -1,
  48719     },
  48720 #endif /* chips */
  48721 
  48722 #if defined(BCM_88375_B0)
  48723     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88375_B0r */
  48724         soc_block_list[23],
  48725         soc_genreg,
  48726         1,
  48727         0,
  48728         0x88,
  48729         SOC_REG_FLAG_WO,
  48730         0,
  48731         3,
  48732         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88375_B0r_fields,
  48733         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48734         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48735         -1,
  48736         -1,
  48737     },
  48738 #endif /* chips */
  48739 
  48740 #if defined(BCM_88470_A0)
  48741     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88470_A0r */
  48742         soc_block_list[23],
  48743         soc_genreg,
  48744         1,
  48745         0,
  48746         0x88,
  48747         SOC_REG_FLAG_64_BITS |
  48748                           SOC_REG_FLAG_WO,
  48749         0,
  48750         4,
  48751         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88470_A0r_fields,
  48752         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  48754         -1,
  48755         -1,
  48756     },
  48757 #endif /* chips */
  48758 
  48759 #if defined(BCM_88470_B0)
  48760     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88470_B0r */
  48761         soc_block_list[23],
  48762         soc_genreg,
  48763         1,
  48764         0,
  48765         0x88,
  48766         SOC_REG_FLAG_64_BITS |
  48767                           SOC_REG_FLAG_WO,
  48768         0,
  48769         4,
  48770         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88470_B0r_fields,
  48771         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48772         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  48773         -1,
  48774         -1,
  48775     },
  48776 #endif /* chips */
  48777 
  48778 #if defined(BCM_88650_B0)
  48779     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88650_B0r */
  48780         soc_block_list[23],
  48781         soc_genreg,
  48782         1,
  48783         0,
  48784         0x56,
  48785         SOC_REG_FLAG_WO,
  48786         0,
  48787         3,
  48788         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88650_B0r_fields,
  48789         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  48790         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48791         -1,
  48792         -1,
  48793     },
  48794 #endif /* chips */
  48795 
  48796 #if defined(BCM_88660_A0)
  48797     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88660_A0r */
  48798         soc_block_list[23],
  48799         soc_genreg,
  48800         1,
  48801         0,
  48802         0x56,
  48803         SOC_REG_FLAG_WO,
  48804         0,
  48805         3,
  48806         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88660_A0r_fields,
  48807         SOC_RESET_VAL_DEC(0x0ee6b280, 0x00000000)
  48808         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48809         -1,
  48810         -1,
  48811     },
  48812 #endif /* chips */
  48813 
  48814 #if defined(BCM_88675_A0)
  48815     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88675_A0r */
  48816         soc_block_list[23],
  48817         soc_genreg,
  48818         1,
  48819         0,
  48820         0x88,
  48821         SOC_REG_FLAG_WO,
  48822         0,
  48823         3,
  48824         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88675_A0r_fields,
  48825         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48826         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48827         -1,
  48828         -1,
  48829     },
  48830 #endif /* chips */
  48831 
  48832 #if defined(BCM_88675_B0)
  48833     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88675_B0r */
  48834         soc_block_list[23],
  48835         soc_genreg,
  48836         1,
  48837         0,
  48838         0x88,
  48839         SOC_REG_FLAG_WO,
  48840         0,
  48841         3,
  48842         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88675_B0r_fields,
  48843         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48844         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48845         -1,
  48846         -1,
  48847     },
  48848 #endif /* chips */
  48849 
  48850 #if defined(BCM_88680_A0)
  48851     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88680_A0r */
  48852         soc_block_list[23],
  48853         soc_genreg,
  48854         1,
  48855         0,
  48856         0x88,
  48857         SOC_REG_FLAG_WO,
  48858         0,
  48859         3,
  48860         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88680_A0r_fields,
  48861         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48862         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48863         -1,
  48864         -1,
  48865     },
  48866 #endif /* chips */
  48867 
  48868 #if defined(BCM_88690_A0)
  48869     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88690_A0r */
  48870         soc_block_list[23],
  48871         soc_genreg,
  48872         1,
  48873         0,
  48874         0x89,
  48875         SOC_REG_FLAG_WO,
  48876         0,
  48877         3,
  48878         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88690_A0r_fields,
  48879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48880         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48881         -1,
  48882         -1,
  48883     },
  48884 #endif /* chips */
  48885 
  48886 #if defined(BCM_88690_B0)
  48887     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88690_B0r */
  48888         soc_block_list[23],
  48889         soc_genreg,
  48890         1,
  48891         0,
  48892         0x89,
  48893         SOC_REG_FLAG_WO,
  48894         0,
  48895         3,
  48896         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
  48897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48898         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48899         -1,
  48900         -1,
  48901     },
  48902 #endif /* chips */
  48903 
  48904 #if defined(BCM_88790_A0)
  48905     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88790_A0r */
  48906         soc_block_list[23],
  48907         soc_genreg,
  48908         1,
  48909         0,
  48910         0x89,
  48911         SOC_REG_FLAG_WO,
  48912         0,
  48913         3,
  48914         soc_BRDC_FMAC_GTIMER_CONFIGURATION_BCM88790_A0r_fields,
  48915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48916         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  48917         -1,
  48918         -1,
  48919     },
  48920 #endif /* chips */
  48921 
  48922 #if defined(BCM_88790_A0)
  48923     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CYCLEr */
  48924         soc_block_list[23],
  48925         soc_genreg,
  48926         1,
  48927         0,
  48928         0x88,
  48929         SOC_REG_FLAG_WO,
  48930         0,
  48931         1,
  48932         soc_BRDC_FMAC_GTIMER_CYCLEr_fields,
  48933         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48935         -1,
  48936         -1,
  48937     },
  48938 #endif /* chips */
  48939 
  48940 #if defined(BCM_88690_A0)
  48941     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CYCLE_BCM88690_A0r */
  48942         soc_block_list[23],
  48943         soc_genreg,
  48944         1,
  48945         0,
  48946         0x88,
  48947         SOC_REG_FLAG_WO,
  48948         0,
  48949         1,
  48950         soc_BRDC_FMAC_GTIMER_CYCLE_BCM88690_A0r_fields,
  48951         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  48952         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48953         -1,
  48954         -1,
  48955     },
  48956 #endif /* chips */
  48957 
  48958 #if defined(BCM_88690_B0)
  48959     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_CYCLE_BCM88690_B0r */
  48960         soc_block_list[23],
  48961         soc_genreg,
  48962         1,
  48963         0,
  48964         0x88,
  48965         SOC_REG_FLAG_WO,
  48966         0,
  48967         1,
  48968         soc_BRDC_FMAC_GTIMER_CYCLE_BCM88690_B0r_fields,
  48969         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  48970         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  48971         -1,
  48972         -1,
  48973     },
  48974 #endif /* chips */
  48975 
  48976 #if defined(BCM_88650_A0)
  48977     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGERr */
  48978         soc_block_list[23],
  48979         soc_genreg,
  48980         1,
  48981         0,
  48982         0x57,
  48983         SOC_REG_FLAG_WO,
  48984         0,
  48985         1,
  48986         soc_BRDC_FMAC_GTIMER_TRIGGERr_fields,
  48987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  48988         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  48989         -1,
  48990         -1,
  48991     },
  48992 #endif /* chips */
  48993 
  48994 #if defined(BCM_88202_A0)
  48995     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88202_A0r */
  48996         soc_block_list[23],
  48997         soc_genreg,
  48998         1,
  48999         0,
  49000         0x57,
  49001         SOC_REG_FLAG_WO,
  49002         0,
  49003         1,
  49004         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88202_A0r_fields,
  49005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49006         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49007         -1,
  49008         -1,
  49009     },
  49010 #endif /* chips */
  49011 
  49012 #if defined(BCM_88375_A0)
  49013     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88375_A0r */
  49014         soc_block_list[23],
  49015         soc_genreg,
  49016         1,
  49017         0,
  49018         0x89,
  49019         SOC_REG_FLAG_RO |
  49020                           SOC_REG_FLAG_WO,
  49021         0,
  49022         1,
  49023         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88375_A0r_fields,
  49024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49025         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49026         -1,
  49027         -1,
  49028     },
  49029 #endif /* chips */
  49030 
  49031 #if defined(BCM_88375_B0)
  49032     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88375_B0r */
  49033         soc_block_list[23],
  49034         soc_genreg,
  49035         1,
  49036         0,
  49037         0x89,
  49038         SOC_REG_FLAG_RO |
  49039                           SOC_REG_FLAG_WO,
  49040         0,
  49041         1,
  49042         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88375_B0r_fields,
  49043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49044         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49045         -1,
  49046         -1,
  49047     },
  49048 #endif /* chips */
  49049 
  49050 #if defined(BCM_88650_B0)
  49051     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88650_B0r */
  49052         soc_block_list[23],
  49053         soc_genreg,
  49054         1,
  49055         0,
  49056         0x57,
  49057         SOC_REG_FLAG_WO,
  49058         0,
  49059         1,
  49060         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88650_B0r_fields,
  49061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49062         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49063         -1,
  49064         -1,
  49065     },
  49066 #endif /* chips */
  49067 
  49068 #if defined(BCM_88660_A0)
  49069     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88660_A0r */
  49070         soc_block_list[23],
  49071         soc_genreg,
  49072         1,
  49073         0,
  49074         0x57,
  49075         SOC_REG_FLAG_WO,
  49076         0,
  49077         1,
  49078         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88660_A0r_fields,
  49079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49080         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49081         -1,
  49082         -1,
  49083     },
  49084 #endif /* chips */
  49085 
  49086 #if defined(BCM_88675_A0)
  49087     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88675_A0r */
  49088         soc_block_list[23],
  49089         soc_genreg,
  49090         1,
  49091         0,
  49092         0x89,
  49093         SOC_REG_FLAG_RO |
  49094                           SOC_REG_FLAG_WO,
  49095         0,
  49096         1,
  49097         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88675_A0r_fields,
  49098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49099         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49100         -1,
  49101         -1,
  49102     },
  49103 #endif /* chips */
  49104 
  49105 #if defined(BCM_88675_B0)
  49106     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88675_B0r */
  49107         soc_block_list[23],
  49108         soc_genreg,
  49109         1,
  49110         0,
  49111         0x89,
  49112         SOC_REG_FLAG_RO |
  49113                           SOC_REG_FLAG_WO,
  49114         0,
  49115         1,
  49116         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88675_B0r_fields,
  49117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49118         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49119         -1,
  49120         -1,
  49121     },
  49122 #endif /* chips */
  49123 
  49124 #if defined(BCM_88680_A0)
  49125     { /* SOC_REG_INT_BRDC_FMAC_GTIMER_TRIGGER_BCM88680_A0r */
  49126         soc_block_list[23],
  49127         soc_genreg,
  49128         1,
  49129         0,
  49130         0x89,
  49131         SOC_REG_FLAG_RO |
  49132                           SOC_REG_FLAG_WO,
  49133         0,
  49134         1,
  49135         soc_BRDC_FMAC_GTIMER_TRIGGER_BCM88680_A0r_fields,
  49136         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49137         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  49138         -1,
  49139         -1,
  49140     },
  49141 #endif /* chips */
  49142 
  49143 #if defined(BCM_88650_A0)
  49144     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTERr */
  49145         soc_block_list[23],
  49146         soc_genreg,
  49147         1,
  49148         0,
  49149         0x10,
  49150         SOC_REG_FLAG_WO,
  49151         0,
  49152         9,
  49153         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTERr_fields,
  49154         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49155         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49156         -1,
  49157         -1,
  49158     },
  49159 #endif /* chips */
  49160 
  49161 #if defined(BCM_88650_A0)
  49162     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1r */
  49163         soc_block_list[23],
  49164         soc_genreg,
  49165         1,
  49166         0,
  49167         0x11,
  49168         SOC_REG_FLAG_WO,
  49169         0,
  49170         2,
  49171         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1r_fields,
  49172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49173         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49174         -1,
  49175         -1,
  49176     },
  49177 #endif /* chips */
  49178 
  49179 #if defined(BCM_88650_A0)
  49180     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2r */
  49181         soc_block_list[23],
  49182         soc_genreg,
  49183         1,
  49184         0,
  49185         0x12,
  49186         SOC_REG_FLAG_WO,
  49187         0,
  49188         2,
  49189         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2r_fields,
  49190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49191         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49192         -1,
  49193         -1,
  49194     },
  49195 #endif /* chips */
  49196 
  49197 #if defined(BCM_88650_A0)
  49198     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3r */
  49199         soc_block_list[23],
  49200         soc_genreg,
  49201         1,
  49202         0,
  49203         0x13,
  49204         SOC_REG_FLAG_WO,
  49205         0,
  49206         2,
  49207         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3r_fields,
  49208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49209         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49210         -1,
  49211         -1,
  49212     },
  49213 #endif /* chips */
  49214 
  49215 #if defined(BCM_88650_A0)
  49216     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4r */
  49217         soc_block_list[23],
  49218         soc_genreg,
  49219         1,
  49220         0,
  49221         0x14,
  49222         SOC_REG_FLAG_WO,
  49223         0,
  49224         2,
  49225         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4r_fields,
  49226         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49227         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49228         -1,
  49229         -1,
  49230     },
  49231 #endif /* chips */
  49232 
  49233 #if defined(BCM_88650_A0)
  49234     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5r */
  49235         soc_block_list[23],
  49236         soc_genreg,
  49237         1,
  49238         0,
  49239         0x15,
  49240         SOC_REG_FLAG_WO,
  49241         0,
  49242         2,
  49243         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5r_fields,
  49244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49245         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49246         -1,
  49247         -1,
  49248     },
  49249 #endif /* chips */
  49250 
  49251 #if defined(BCM_88650_A0)
  49252     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6r */
  49253         soc_block_list[23],
  49254         soc_genreg,
  49255         1,
  49256         0,
  49257         0x16,
  49258         SOC_REG_FLAG_WO,
  49259         0,
  49260         1,
  49261         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6r_fields,
  49262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49263         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49264         -1,
  49265         -1,
  49266     },
  49267 #endif /* chips */
  49268 
  49269 #if defined(BCM_88650_A0)
  49270     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7r */
  49271         soc_block_list[23],
  49272         soc_genreg,
  49273         1,
  49274         0,
  49275         0x17,
  49276         SOC_REG_FLAG_WO,
  49277         0,
  49278         1,
  49279         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7r_fields,
  49280         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49281         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49282         -1,
  49283         -1,
  49284     },
  49285 #endif /* chips */
  49286 
  49287 #if defined(BCM_88650_A0)
  49288     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8r */
  49289         soc_block_list[23],
  49290         soc_genreg,
  49291         1,
  49292         0,
  49293         0x18,
  49294         SOC_REG_FLAG_WO,
  49295         0,
  49296         3,
  49297         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8r_fields,
  49298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49299         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  49300         -1,
  49301         -1,
  49302     },
  49303 #endif /* chips */
  49304 
  49305 #if defined(BCM_88650_A0)
  49306     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9r */
  49307         soc_block_list[23],
  49308         soc_genreg,
  49309         1,
  49310         0,
  49311         0x19,
  49312         SOC_REG_FLAG_WO,
  49313         0,
  49314         2,
  49315         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9r_fields,
  49316         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49317         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49318         -1,
  49319         -1,
  49320     },
  49321 #endif /* chips */
  49322 
  49323 #if defined(BCM_88202_A0)
  49324     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88202_A0r */
  49325         soc_block_list[23],
  49326         soc_genreg,
  49327         1,
  49328         0,
  49329         0x11,
  49330         SOC_REG_FLAG_WO,
  49331         0,
  49332         2,
  49333         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88202_A0r_fields,
  49334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49335         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49336         -1,
  49337         -1,
  49338     },
  49339 #endif /* chips */
  49340 
  49341 #if defined(BCM_88650_B0)
  49342     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88650_B0r */
  49343         soc_block_list[23],
  49344         soc_genreg,
  49345         1,
  49346         0,
  49347         0x11,
  49348         SOC_REG_FLAG_WO,
  49349         0,
  49350         2,
  49351         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88650_B0r_fields,
  49352         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49353         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49354         -1,
  49355         -1,
  49356     },
  49357 #endif /* chips */
  49358 
  49359 #if defined(BCM_88660_A0)
  49360     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88660_A0r */
  49361         soc_block_list[23],
  49362         soc_genreg,
  49363         1,
  49364         0,
  49365         0x11,
  49366         SOC_REG_FLAG_WO,
  49367         0,
  49368         2,
  49369         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_1_BCM88660_A0r_fields,
  49370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49371         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49372         -1,
  49373         -1,
  49374     },
  49375 #endif /* chips */
  49376 
  49377 #if defined(BCM_88202_A0)
  49378     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88202_A0r */
  49379         soc_block_list[23],
  49380         soc_genreg,
  49381         1,
  49382         0,
  49383         0x12,
  49384         SOC_REG_FLAG_WO,
  49385         0,
  49386         2,
  49387         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88202_A0r_fields,
  49388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49389         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49390         -1,
  49391         -1,
  49392     },
  49393 #endif /* chips */
  49394 
  49395 #if defined(BCM_88650_B0)
  49396     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88650_B0r */
  49397         soc_block_list[23],
  49398         soc_genreg,
  49399         1,
  49400         0,
  49401         0x12,
  49402         SOC_REG_FLAG_WO,
  49403         0,
  49404         2,
  49405         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88650_B0r_fields,
  49406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49407         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49408         -1,
  49409         -1,
  49410     },
  49411 #endif /* chips */
  49412 
  49413 #if defined(BCM_88660_A0)
  49414     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88660_A0r */
  49415         soc_block_list[23],
  49416         soc_genreg,
  49417         1,
  49418         0,
  49419         0x12,
  49420         SOC_REG_FLAG_WO,
  49421         0,
  49422         2,
  49423         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_2_BCM88660_A0r_fields,
  49424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49425         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49426         -1,
  49427         -1,
  49428     },
  49429 #endif /* chips */
  49430 
  49431 #if defined(BCM_88202_A0)
  49432     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88202_A0r */
  49433         soc_block_list[23],
  49434         soc_genreg,
  49435         1,
  49436         0,
  49437         0x13,
  49438         SOC_REG_FLAG_WO,
  49439         0,
  49440         2,
  49441         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88202_A0r_fields,
  49442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49443         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49444         -1,
  49445         -1,
  49446     },
  49447 #endif /* chips */
  49448 
  49449 #if defined(BCM_88650_B0)
  49450     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88650_B0r */
  49451         soc_block_list[23],
  49452         soc_genreg,
  49453         1,
  49454         0,
  49455         0x13,
  49456         SOC_REG_FLAG_WO,
  49457         0,
  49458         2,
  49459         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88650_B0r_fields,
  49460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49461         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49462         -1,
  49463         -1,
  49464     },
  49465 #endif /* chips */
  49466 
  49467 #if defined(BCM_88660_A0)
  49468     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88660_A0r */
  49469         soc_block_list[23],
  49470         soc_genreg,
  49471         1,
  49472         0,
  49473         0x13,
  49474         SOC_REG_FLAG_WO,
  49475         0,
  49476         2,
  49477         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_3_BCM88660_A0r_fields,
  49478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49479         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49480         -1,
  49481         -1,
  49482     },
  49483 #endif /* chips */
  49484 
  49485 #if defined(BCM_88202_A0)
  49486     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88202_A0r */
  49487         soc_block_list[23],
  49488         soc_genreg,
  49489         1,
  49490         0,
  49491         0x14,
  49492         SOC_REG_FLAG_WO,
  49493         0,
  49494         2,
  49495         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88202_A0r_fields,
  49496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49497         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49498         -1,
  49499         -1,
  49500     },
  49501 #endif /* chips */
  49502 
  49503 #if defined(BCM_88650_B0)
  49504     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88650_B0r */
  49505         soc_block_list[23],
  49506         soc_genreg,
  49507         1,
  49508         0,
  49509         0x14,
  49510         SOC_REG_FLAG_WO,
  49511         0,
  49512         2,
  49513         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88650_B0r_fields,
  49514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49515         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49516         -1,
  49517         -1,
  49518     },
  49519 #endif /* chips */
  49520 
  49521 #if defined(BCM_88660_A0)
  49522     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88660_A0r */
  49523         soc_block_list[23],
  49524         soc_genreg,
  49525         1,
  49526         0,
  49527         0x14,
  49528         SOC_REG_FLAG_WO,
  49529         0,
  49530         2,
  49531         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_4_BCM88660_A0r_fields,
  49532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49533         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49534         -1,
  49535         -1,
  49536     },
  49537 #endif /* chips */
  49538 
  49539 #if defined(BCM_88202_A0)
  49540     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88202_A0r */
  49541         soc_block_list[23],
  49542         soc_genreg,
  49543         1,
  49544         0,
  49545         0x15,
  49546         SOC_REG_FLAG_WO,
  49547         0,
  49548         2,
  49549         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88202_A0r_fields,
  49550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49551         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49552         -1,
  49553         -1,
  49554     },
  49555 #endif /* chips */
  49556 
  49557 #if defined(BCM_88650_B0)
  49558     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88650_B0r */
  49559         soc_block_list[23],
  49560         soc_genreg,
  49561         1,
  49562         0,
  49563         0x15,
  49564         SOC_REG_FLAG_WO,
  49565         0,
  49566         2,
  49567         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88650_B0r_fields,
  49568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49569         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49570         -1,
  49571         -1,
  49572     },
  49573 #endif /* chips */
  49574 
  49575 #if defined(BCM_88660_A0)
  49576     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88660_A0r */
  49577         soc_block_list[23],
  49578         soc_genreg,
  49579         1,
  49580         0,
  49581         0x15,
  49582         SOC_REG_FLAG_WO,
  49583         0,
  49584         2,
  49585         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_5_BCM88660_A0r_fields,
  49586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49587         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  49588         -1,
  49589         -1,
  49590     },
  49591 #endif /* chips */
  49592 
  49593 #if defined(BCM_88202_A0)
  49594     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88202_A0r */
  49595         soc_block_list[23],
  49596         soc_genreg,
  49597         1,
  49598         0,
  49599         0x16,
  49600         SOC_REG_FLAG_WO,
  49601         0,
  49602         1,
  49603         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88202_A0r_fields,
  49604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49605         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49606         -1,
  49607         -1,
  49608     },
  49609 #endif /* chips */
  49610 
  49611 #if defined(BCM_88650_B0)
  49612     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88650_B0r */
  49613         soc_block_list[23],
  49614         soc_genreg,
  49615         1,
  49616         0,
  49617         0x16,
  49618         SOC_REG_FLAG_WO,
  49619         0,
  49620         1,
  49621         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88650_B0r_fields,
  49622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49623         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49624         -1,
  49625         -1,
  49626     },
  49627 #endif /* chips */
  49628 
  49629 #if defined(BCM_88660_A0)
  49630     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88660_A0r */
  49631         soc_block_list[23],
  49632         soc_genreg,
  49633         1,
  49634         0,
  49635         0x16,
  49636         SOC_REG_FLAG_WO,
  49637         0,
  49638         1,
  49639         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_6_BCM88660_A0r_fields,
  49640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49641         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49642         -1,
  49643         -1,
  49644     },
  49645 #endif /* chips */
  49646 
  49647 #if defined(BCM_88202_A0)
  49648     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88202_A0r */
  49649         soc_block_list[23],
  49650         soc_genreg,
  49651         1,
  49652         0,
  49653         0x17,
  49654         SOC_REG_FLAG_WO,
  49655         0,
  49656         1,
  49657         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88202_A0r_fields,
  49658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49659         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49660         -1,
  49661         -1,
  49662     },
  49663 #endif /* chips */
  49664 
  49665 #if defined(BCM_88650_B0)
  49666     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88650_B0r */
  49667         soc_block_list[23],
  49668         soc_genreg,
  49669         1,
  49670         0,
  49671         0x17,
  49672         SOC_REG_FLAG_WO,
  49673         0,
  49674         1,
  49675         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88650_B0r_fields,
  49676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49677         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49678         -1,
  49679         -1,
  49680     },
  49681 #endif /* chips */
  49682 
  49683 #if defined(BCM_88660_A0)
  49684     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88660_A0r */
  49685         soc_block_list[23],
  49686         soc_genreg,
  49687         1,
  49688         0,
  49689         0x17,
  49690         SOC_REG_FLAG_WO,
  49691         0,
  49692         1,
  49693         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_7_BCM88660_A0r_fields,
  49694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49695         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  49696         -1,
  49697         -1,
  49698     },
  49699 #endif /* chips */
  49700 
  49701 #if defined(BCM_88202_A0)
  49702     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88202_A0r */
  49703         soc_block_list[23],
  49704         soc_genreg,
  49705         1,
  49706         0,
  49707         0x18,
  49708         SOC_REG_FLAG_WO,
  49709         0,
  49710         3,
  49711         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88202_A0r_fields,
  49712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49713         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  49714         -1,
  49715         -1,
  49716     },
  49717 #endif /* chips */
  49718 
  49719 #if defined(BCM_88650_B0)
  49720     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88650_B0r */
  49721         soc_block_list[23],
  49722         soc_genreg,
  49723         1,
  49724         0,
  49725         0x18,
  49726         SOC_REG_FLAG_WO,
  49727         0,
  49728         3,
  49729         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88650_B0r_fields,
  49730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49731         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  49732         -1,
  49733         -1,
  49734     },
  49735 #endif /* chips */
  49736 
  49737 #if defined(BCM_88660_A0)
  49738     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88660_A0r */
  49739         soc_block_list[23],
  49740         soc_genreg,
  49741         1,
  49742         0,
  49743         0x18,
  49744         SOC_REG_FLAG_WO,
  49745         0,
  49746         3,
  49747         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_8_BCM88660_A0r_fields,
  49748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49749         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  49750         -1,
  49751         -1,
  49752     },
  49753 #endif /* chips */
  49754 
  49755 #if defined(BCM_88202_A0)
  49756     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9_BCM88202_A0r */
  49757         soc_block_list[23],
  49758         soc_genreg,
  49759         1,
  49760         0,
  49761         0x19,
  49762         SOC_REG_FLAG_WO,
  49763         0,
  49764         2,
  49765         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9_BCM88202_A0r_fields,
  49766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49767         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49768         -1,
  49769         -1,
  49770     },
  49771 #endif /* chips */
  49772 
  49773 #if defined(BCM_88650_B0)
  49774     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9_BCM88650_B0r */
  49775         soc_block_list[23],
  49776         soc_genreg,
  49777         1,
  49778         0,
  49779         0x19,
  49780         SOC_REG_FLAG_WO,
  49781         0,
  49782         2,
  49783         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9_BCM88650_B0r_fields,
  49784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49785         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49786         -1,
  49787         -1,
  49788     },
  49789 #endif /* chips */
  49790 
  49791 #if defined(BCM_88660_A0)
  49792     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9_BCM88660_A0r */
  49793         soc_block_list[23],
  49794         soc_genreg,
  49795         1,
  49796         0,
  49797         0x19,
  49798         SOC_REG_FLAG_WO,
  49799         0,
  49800         2,
  49801         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_9_BCM88660_A0r_fields,
  49802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49803         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  49804         -1,
  49805         -1,
  49806     },
  49807 #endif /* chips */
  49808 
  49809 #if defined(BCM_83208_A0)
  49810     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM83208_A0r */
  49811         soc_block_list[23],
  49812         soc_genreg,
  49813         1,
  49814         0,
  49815         0x10,
  49816         SOC_REG_FLAG_WO,
  49817         0,
  49818         9,
  49819         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM83208_A0r_fields,
  49820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49821         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49822         -1,
  49823         -1,
  49824     },
  49825 #endif /* chips */
  49826 
  49827 #if defined(BCM_88202_A0)
  49828     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88202_A0r */
  49829         soc_block_list[23],
  49830         soc_genreg,
  49831         1,
  49832         0,
  49833         0x10,
  49834         SOC_REG_FLAG_WO,
  49835         0,
  49836         9,
  49837         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88202_A0r_fields,
  49838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49839         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49840         -1,
  49841         -1,
  49842     },
  49843 #endif /* chips */
  49844 
  49845 #if defined(BCM_88375_A0)
  49846     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88375_A0r */
  49847         soc_block_list[23],
  49848         soc_genreg,
  49849         1,
  49850         0,
  49851         0x10,
  49852         SOC_REG_FLAG_WO,
  49853         0,
  49854         9,
  49855         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88375_A0r_fields,
  49856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49857         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49858         -1,
  49859         -1,
  49860     },
  49861 #endif /* chips */
  49862 
  49863 #if defined(BCM_88375_B0)
  49864     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88375_B0r */
  49865         soc_block_list[23],
  49866         soc_genreg,
  49867         1,
  49868         0,
  49869         0x10,
  49870         SOC_REG_FLAG_WO,
  49871         0,
  49872         9,
  49873         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88375_B0r_fields,
  49874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49875         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49876         -1,
  49877         -1,
  49878     },
  49879 #endif /* chips */
  49880 
  49881 #if defined(BCM_88470_A0)
  49882     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88470_A0r */
  49883         soc_block_list[23],
  49884         soc_genreg,
  49885         1,
  49886         0,
  49887         0x10,
  49888         SOC_REG_FLAG_WO,
  49889         0,
  49890         9,
  49891         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88470_A0r_fields,
  49892         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49893         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49894         -1,
  49895         -1,
  49896     },
  49897 #endif /* chips */
  49898 
  49899 #if defined(BCM_88470_B0)
  49900     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88470_B0r */
  49901         soc_block_list[23],
  49902         soc_genreg,
  49903         1,
  49904         0,
  49905         0x10,
  49906         SOC_REG_FLAG_WO,
  49907         0,
  49908         9,
  49909         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88470_B0r_fields,
  49910         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49911         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49912         -1,
  49913         -1,
  49914     },
  49915 #endif /* chips */
  49916 
  49917 #if defined(BCM_88650_B0)
  49918     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88650_B0r */
  49919         soc_block_list[23],
  49920         soc_genreg,
  49921         1,
  49922         0,
  49923         0x10,
  49924         SOC_REG_FLAG_WO,
  49925         0,
  49926         9,
  49927         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88650_B0r_fields,
  49928         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49929         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49930         -1,
  49931         -1,
  49932     },
  49933 #endif /* chips */
  49934 
  49935 #if defined(BCM_88660_A0)
  49936     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88660_A0r */
  49937         soc_block_list[23],
  49938         soc_genreg,
  49939         1,
  49940         0,
  49941         0x10,
  49942         SOC_REG_FLAG_WO,
  49943         0,
  49944         9,
  49945         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88660_A0r_fields,
  49946         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49947         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49948         -1,
  49949         -1,
  49950     },
  49951 #endif /* chips */
  49952 
  49953 #if defined(BCM_88675_A0)
  49954     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88675_A0r */
  49955         soc_block_list[23],
  49956         soc_genreg,
  49957         1,
  49958         0,
  49959         0x10,
  49960         SOC_REG_FLAG_WO,
  49961         0,
  49962         9,
  49963         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88675_A0r_fields,
  49964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49965         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49966         -1,
  49967         -1,
  49968     },
  49969 #endif /* chips */
  49970 
  49971 #if defined(BCM_88675_B0)
  49972     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88675_B0r */
  49973         soc_block_list[23],
  49974         soc_genreg,
  49975         1,
  49976         0,
  49977         0x10,
  49978         SOC_REG_FLAG_WO,
  49979         0,
  49980         9,
  49981         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88675_B0r_fields,
  49982         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  49983         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  49984         -1,
  49985         -1,
  49986     },
  49987 #endif /* chips */
  49988 
  49989 #if defined(BCM_88680_A0)
  49990     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88680_A0r */
  49991         soc_block_list[23],
  49992         soc_genreg,
  49993         1,
  49994         0,
  49995         0x10,
  49996         SOC_REG_FLAG_WO,
  49997         0,
  49998         9,
  49999         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88680_A0r_fields,
  50000         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50001         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  50002         -1,
  50003         -1,
  50004     },
  50005 #endif /* chips */
  50006 
  50007 #if defined(BCM_88690_A0)
  50008     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88690_A0r */
  50009         soc_block_list[23],
  50010         soc_genreg,
  50011         1,
  50012         0,
  50013         0x10,
  50014         SOC_REG_FLAG_64_BITS |
  50015                           SOC_REG_FLAG_WO,
  50016         0,
  50017         22,
  50018         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88690_A0r_fields,
  50019         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50020         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  50021         -1,
  50022         -1,
  50023     },
  50024 #endif /* chips */
  50025 
  50026 #if defined(BCM_88690_B0)
  50027     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  50028         soc_block_list[23],
  50029         soc_genreg,
  50030         1,
  50031         0,
  50032         0x10,
  50033         SOC_REG_FLAG_64_BITS |
  50034                           SOC_REG_FLAG_WO,
  50035         0,
  50036         22,
  50037         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  50038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50039         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  50040         -1,
  50041         -1,
  50042     },
  50043 #endif /* chips */
  50044 
  50045 #if defined(BCM_88790_A0)
  50046     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88790_A0r */
  50047         soc_block_list[23],
  50048         soc_genreg,
  50049         1,
  50050         0,
  50051         0x10,
  50052         SOC_REG_FLAG_64_BITS |
  50053                           SOC_REG_FLAG_WO,
  50054         0,
  50055         22,
  50056         soc_BRDC_FMAC_INTERRUPT_MASK_REGISTER_BCM88790_A0r_fields,
  50057         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50058         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  50059         -1,
  50060         -1,
  50061     },
  50062 #endif /* chips */
  50063 
  50064 #if defined(BCM_88650_A0)
  50065     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTERr */
  50066         soc_block_list[23],
  50067         soc_genreg,
  50068         1,
  50069         0,
  50070         0,
  50071         SOC_REG_FLAG_WO |
  50072                           SOC_REG_FLAG_INTERRUPT,
  50073         0,
  50074         9,
  50075         soc_BRDC_FMAC_INTERRUPT_REGISTERr_fields,
  50076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50077         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  50078         -1,
  50079         -1,
  50080     },
  50081 #endif /* chips */
  50082 
  50083 #if defined(BCM_88650_A0)
  50084     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1r */
  50085         soc_block_list[23],
  50086         soc_genreg,
  50087         1,
  50088         0,
  50089         0x1,
  50090         SOC_REG_FLAG_WO |
  50091                           SOC_REG_FLAG_INTERRUPT,
  50092         0,
  50093         2,
  50094         soc_BRDC_FMAC_INTERRUPT_REGISTER_1r_fields,
  50095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50096         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50097         -1,
  50098         -1,
  50099     },
  50100 #endif /* chips */
  50101 
  50102 #if defined(BCM_88650_A0)
  50103     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2r */
  50104         soc_block_list[23],
  50105         soc_genreg,
  50106         1,
  50107         0,
  50108         0x2,
  50109         SOC_REG_FLAG_WO |
  50110                           SOC_REG_FLAG_INTERRUPT,
  50111         0,
  50112         2,
  50113         soc_BRDC_FMAC_INTERRUPT_REGISTER_2r_fields,
  50114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50115         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50116         -1,
  50117         -1,
  50118     },
  50119 #endif /* chips */
  50120 
  50121 #if defined(BCM_88650_A0)
  50122     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3r */
  50123         soc_block_list[23],
  50124         soc_genreg,
  50125         1,
  50126         0,
  50127         0x3,
  50128         SOC_REG_FLAG_WO |
  50129                           SOC_REG_FLAG_INTERRUPT,
  50130         0,
  50131         2,
  50132         soc_BRDC_FMAC_INTERRUPT_REGISTER_3r_fields,
  50133         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50134         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50135         -1,
  50136         -1,
  50137     },
  50138 #endif /* chips */
  50139 
  50140 #if defined(BCM_88650_A0)
  50141     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4r */
  50142         soc_block_list[23],
  50143         soc_genreg,
  50144         1,
  50145         0,
  50146         0x4,
  50147         SOC_REG_FLAG_WO |
  50148                           SOC_REG_FLAG_INTERRUPT,
  50149         0,
  50150         2,
  50151         soc_BRDC_FMAC_INTERRUPT_REGISTER_4r_fields,
  50152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50153         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50154         -1,
  50155         -1,
  50156     },
  50157 #endif /* chips */
  50158 
  50159 #if defined(BCM_88650_A0)
  50160     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5r */
  50161         soc_block_list[23],
  50162         soc_genreg,
  50163         1,
  50164         0,
  50165         0x5,
  50166         SOC_REG_FLAG_WO |
  50167                           SOC_REG_FLAG_INTERRUPT,
  50168         0,
  50169         2,
  50170         soc_BRDC_FMAC_INTERRUPT_REGISTER_5r_fields,
  50171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50172         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50173         -1,
  50174         -1,
  50175     },
  50176 #endif /* chips */
  50177 
  50178 #if defined(BCM_88650_A0)
  50179     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6r */
  50180         soc_block_list[23],
  50181         soc_genreg,
  50182         1,
  50183         0,
  50184         0x6,
  50185         SOC_REG_FLAG_WO |
  50186                           SOC_REG_FLAG_INTERRUPT,
  50187         0,
  50188         1,
  50189         soc_BRDC_FMAC_INTERRUPT_REGISTER_6r_fields,
  50190         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50191         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50192         -1,
  50193         -1,
  50194     },
  50195 #endif /* chips */
  50196 
  50197 #if defined(BCM_88650_A0)
  50198     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7r */
  50199         soc_block_list[23],
  50200         soc_genreg,
  50201         1,
  50202         0,
  50203         0x7,
  50204         SOC_REG_FLAG_WO |
  50205                           SOC_REG_FLAG_INTERRUPT,
  50206         0,
  50207         1,
  50208         soc_BRDC_FMAC_INTERRUPT_REGISTER_7r_fields,
  50209         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50210         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50211         -1,
  50212         -1,
  50213     },
  50214 #endif /* chips */
  50215 
  50216 #if defined(BCM_88650_A0)
  50217     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8r */
  50218         soc_block_list[23],
  50219         soc_genreg,
  50220         1,
  50221         0,
  50222         0x8,
  50223         SOC_REG_FLAG_WO |
  50224                           SOC_REG_FLAG_INTERRUPT,
  50225         0,
  50226         3,
  50227         soc_BRDC_FMAC_INTERRUPT_REGISTER_8r_fields,
  50228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50229         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  50230         -1,
  50231         -1,
  50232     },
  50233 #endif /* chips */
  50234 
  50235 #if defined(BCM_88650_A0)
  50236     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9r */
  50237         soc_block_list[23],
  50238         soc_genreg,
  50239         1,
  50240         0,
  50241         0x9,
  50242         SOC_REG_FLAG_WO |
  50243                           SOC_REG_FLAG_INTERRUPT,
  50244         0,
  50245         2,
  50246         soc_BRDC_FMAC_INTERRUPT_REGISTER_9r_fields,
  50247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50248         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  50249         -1,
  50250         -1,
  50251     },
  50252 #endif /* chips */
  50253 
  50254 #if defined(BCM_88202_A0)
  50255     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1_BCM88202_A0r */
  50256         soc_block_list[23],
  50257         soc_genreg,
  50258         1,
  50259         0,
  50260         0x1,
  50261         SOC_REG_FLAG_WO |
  50262                           SOC_REG_FLAG_INTERRUPT,
  50263         0,
  50264         2,
  50265         soc_BRDC_FMAC_INTERRUPT_REGISTER_1_BCM88202_A0r_fields,
  50266         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50267         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50268         -1,
  50269         -1,
  50270     },
  50271 #endif /* chips */
  50272 
  50273 #if defined(BCM_88650_B0)
  50274     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1_BCM88650_B0r */
  50275         soc_block_list[23],
  50276         soc_genreg,
  50277         1,
  50278         0,
  50279         0x1,
  50280         SOC_REG_FLAG_WO |
  50281                           SOC_REG_FLAG_INTERRUPT,
  50282         0,
  50283         2,
  50284         soc_BRDC_FMAC_INTERRUPT_REGISTER_1_BCM88650_B0r_fields,
  50285         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50286         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50287         -1,
  50288         -1,
  50289     },
  50290 #endif /* chips */
  50291 
  50292 #if defined(BCM_88660_A0)
  50293     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1_BCM88660_A0r */
  50294         soc_block_list[23],
  50295         soc_genreg,
  50296         1,
  50297         0,
  50298         0x1,
  50299         SOC_REG_FLAG_WO |
  50300                           SOC_REG_FLAG_INTERRUPT,
  50301         0,
  50302         2,
  50303         soc_BRDC_FMAC_INTERRUPT_REGISTER_1_BCM88660_A0r_fields,
  50304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50305         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50306         -1,
  50307         -1,
  50308     },
  50309 #endif /* chips */
  50310 
  50311 #if defined(BCM_88650_A0)
  50312     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1_TESTr */
  50313         soc_block_list[23],
  50314         soc_genreg,
  50315         1,
  50316         0,
  50317         0x1b,
  50318         SOC_REG_FLAG_WO |
  50319                           SOC_REG_FLAG_INTERRUPT,
  50320         0,
  50321         1,
  50322         soc_BRDC_FMAC_INTERRUPT_REGISTER_1_TESTr_fields,
  50323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50324         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50325         -1,
  50326         -1,
  50327     },
  50328 #endif /* chips */
  50329 
  50330 #if defined(BCM_88202_A0)
  50331     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88202_A0r */
  50332         soc_block_list[23],
  50333         soc_genreg,
  50334         1,
  50335         0,
  50336         0x1b,
  50337         SOC_REG_FLAG_WO |
  50338                           SOC_REG_FLAG_INTERRUPT,
  50339         0,
  50340         1,
  50341         soc_BRDC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88202_A0r_fields,
  50342         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50344         -1,
  50345         -1,
  50346     },
  50347 #endif /* chips */
  50348 
  50349 #if defined(BCM_88650_B0)
  50350     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88650_B0r */
  50351         soc_block_list[23],
  50352         soc_genreg,
  50353         1,
  50354         0,
  50355         0x1b,
  50356         SOC_REG_FLAG_WO |
  50357                           SOC_REG_FLAG_INTERRUPT,
  50358         0,
  50359         1,
  50360         soc_BRDC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88650_B0r_fields,
  50361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50362         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50363         -1,
  50364         -1,
  50365     },
  50366 #endif /* chips */
  50367 
  50368 #if defined(BCM_88660_A0)
  50369     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88660_A0r */
  50370         soc_block_list[23],
  50371         soc_genreg,
  50372         1,
  50373         0,
  50374         0x1b,
  50375         SOC_REG_FLAG_WO |
  50376                           SOC_REG_FLAG_INTERRUPT,
  50377         0,
  50378         1,
  50379         soc_BRDC_FMAC_INTERRUPT_REGISTER_1_TEST_BCM88660_A0r_fields,
  50380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50382         -1,
  50383         -1,
  50384     },
  50385 #endif /* chips */
  50386 
  50387 #if defined(BCM_88202_A0)
  50388     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2_BCM88202_A0r */
  50389         soc_block_list[23],
  50390         soc_genreg,
  50391         1,
  50392         0,
  50393         0x2,
  50394         SOC_REG_FLAG_WO |
  50395                           SOC_REG_FLAG_INTERRUPT,
  50396         0,
  50397         2,
  50398         soc_BRDC_FMAC_INTERRUPT_REGISTER_2_BCM88202_A0r_fields,
  50399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50400         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50401         -1,
  50402         -1,
  50403     },
  50404 #endif /* chips */
  50405 
  50406 #if defined(BCM_88650_B0)
  50407     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2_BCM88650_B0r */
  50408         soc_block_list[23],
  50409         soc_genreg,
  50410         1,
  50411         0,
  50412         0x2,
  50413         SOC_REG_FLAG_WO |
  50414                           SOC_REG_FLAG_INTERRUPT,
  50415         0,
  50416         2,
  50417         soc_BRDC_FMAC_INTERRUPT_REGISTER_2_BCM88650_B0r_fields,
  50418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50419         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50420         -1,
  50421         -1,
  50422     },
  50423 #endif /* chips */
  50424 
  50425 #if defined(BCM_88660_A0)
  50426     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2_BCM88660_A0r */
  50427         soc_block_list[23],
  50428         soc_genreg,
  50429         1,
  50430         0,
  50431         0x2,
  50432         SOC_REG_FLAG_WO |
  50433                           SOC_REG_FLAG_INTERRUPT,
  50434         0,
  50435         2,
  50436         soc_BRDC_FMAC_INTERRUPT_REGISTER_2_BCM88660_A0r_fields,
  50437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50438         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50439         -1,
  50440         -1,
  50441     },
  50442 #endif /* chips */
  50443 
  50444 #if defined(BCM_88650_A0)
  50445     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2_TESTr */
  50446         soc_block_list[23],
  50447         soc_genreg,
  50448         1,
  50449         0,
  50450         0x1c,
  50451         SOC_REG_FLAG_WO |
  50452                           SOC_REG_FLAG_INTERRUPT,
  50453         0,
  50454         1,
  50455         soc_BRDC_FMAC_INTERRUPT_REGISTER_2_TESTr_fields,
  50456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50457         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50458         -1,
  50459         -1,
  50460     },
  50461 #endif /* chips */
  50462 
  50463 #if defined(BCM_88202_A0)
  50464     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88202_A0r */
  50465         soc_block_list[23],
  50466         soc_genreg,
  50467         1,
  50468         0,
  50469         0x1c,
  50470         SOC_REG_FLAG_WO |
  50471                           SOC_REG_FLAG_INTERRUPT,
  50472         0,
  50473         1,
  50474         soc_BRDC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88202_A0r_fields,
  50475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50476         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50477         -1,
  50478         -1,
  50479     },
  50480 #endif /* chips */
  50481 
  50482 #if defined(BCM_88650_B0)
  50483     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88650_B0r */
  50484         soc_block_list[23],
  50485         soc_genreg,
  50486         1,
  50487         0,
  50488         0x1c,
  50489         SOC_REG_FLAG_WO |
  50490                           SOC_REG_FLAG_INTERRUPT,
  50491         0,
  50492         1,
  50493         soc_BRDC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88650_B0r_fields,
  50494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50495         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50496         -1,
  50497         -1,
  50498     },
  50499 #endif /* chips */
  50500 
  50501 #if defined(BCM_88660_A0)
  50502     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88660_A0r */
  50503         soc_block_list[23],
  50504         soc_genreg,
  50505         1,
  50506         0,
  50507         0x1c,
  50508         SOC_REG_FLAG_WO |
  50509                           SOC_REG_FLAG_INTERRUPT,
  50510         0,
  50511         1,
  50512         soc_BRDC_FMAC_INTERRUPT_REGISTER_2_TEST_BCM88660_A0r_fields,
  50513         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50514         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50515         -1,
  50516         -1,
  50517     },
  50518 #endif /* chips */
  50519 
  50520 #if defined(BCM_88202_A0)
  50521     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3_BCM88202_A0r */
  50522         soc_block_list[23],
  50523         soc_genreg,
  50524         1,
  50525         0,
  50526         0x3,
  50527         SOC_REG_FLAG_WO |
  50528                           SOC_REG_FLAG_INTERRUPT,
  50529         0,
  50530         2,
  50531         soc_BRDC_FMAC_INTERRUPT_REGISTER_3_BCM88202_A0r_fields,
  50532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50533         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50534         -1,
  50535         -1,
  50536     },
  50537 #endif /* chips */
  50538 
  50539 #if defined(BCM_88650_B0)
  50540     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3_BCM88650_B0r */
  50541         soc_block_list[23],
  50542         soc_genreg,
  50543         1,
  50544         0,
  50545         0x3,
  50546         SOC_REG_FLAG_WO |
  50547                           SOC_REG_FLAG_INTERRUPT,
  50548         0,
  50549         2,
  50550         soc_BRDC_FMAC_INTERRUPT_REGISTER_3_BCM88650_B0r_fields,
  50551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50552         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50553         -1,
  50554         -1,
  50555     },
  50556 #endif /* chips */
  50557 
  50558 #if defined(BCM_88660_A0)
  50559     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3_BCM88660_A0r */
  50560         soc_block_list[23],
  50561         soc_genreg,
  50562         1,
  50563         0,
  50564         0x3,
  50565         SOC_REG_FLAG_WO |
  50566                           SOC_REG_FLAG_INTERRUPT,
  50567         0,
  50568         2,
  50569         soc_BRDC_FMAC_INTERRUPT_REGISTER_3_BCM88660_A0r_fields,
  50570         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50571         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50572         -1,
  50573         -1,
  50574     },
  50575 #endif /* chips */
  50576 
  50577 #if defined(BCM_88650_A0)
  50578     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3_TESTr */
  50579         soc_block_list[23],
  50580         soc_genreg,
  50581         1,
  50582         0,
  50583         0x1d,
  50584         SOC_REG_FLAG_WO |
  50585                           SOC_REG_FLAG_INTERRUPT,
  50586         0,
  50587         1,
  50588         soc_BRDC_FMAC_INTERRUPT_REGISTER_3_TESTr_fields,
  50589         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50590         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50591         -1,
  50592         -1,
  50593     },
  50594 #endif /* chips */
  50595 
  50596 #if defined(BCM_88202_A0)
  50597     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88202_A0r */
  50598         soc_block_list[23],
  50599         soc_genreg,
  50600         1,
  50601         0,
  50602         0x1d,
  50603         SOC_REG_FLAG_WO |
  50604                           SOC_REG_FLAG_INTERRUPT,
  50605         0,
  50606         1,
  50607         soc_BRDC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88202_A0r_fields,
  50608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50609         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50610         -1,
  50611         -1,
  50612     },
  50613 #endif /* chips */
  50614 
  50615 #if defined(BCM_88650_B0)
  50616     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88650_B0r */
  50617         soc_block_list[23],
  50618         soc_genreg,
  50619         1,
  50620         0,
  50621         0x1d,
  50622         SOC_REG_FLAG_WO |
  50623                           SOC_REG_FLAG_INTERRUPT,
  50624         0,
  50625         1,
  50626         soc_BRDC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88650_B0r_fields,
  50627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50628         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50629         -1,
  50630         -1,
  50631     },
  50632 #endif /* chips */
  50633 
  50634 #if defined(BCM_88660_A0)
  50635     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88660_A0r */
  50636         soc_block_list[23],
  50637         soc_genreg,
  50638         1,
  50639         0,
  50640         0x1d,
  50641         SOC_REG_FLAG_WO |
  50642                           SOC_REG_FLAG_INTERRUPT,
  50643         0,
  50644         1,
  50645         soc_BRDC_FMAC_INTERRUPT_REGISTER_3_TEST_BCM88660_A0r_fields,
  50646         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50647         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50648         -1,
  50649         -1,
  50650     },
  50651 #endif /* chips */
  50652 
  50653 #if defined(BCM_88202_A0)
  50654     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4_BCM88202_A0r */
  50655         soc_block_list[23],
  50656         soc_genreg,
  50657         1,
  50658         0,
  50659         0x4,
  50660         SOC_REG_FLAG_WO |
  50661                           SOC_REG_FLAG_INTERRUPT,
  50662         0,
  50663         2,
  50664         soc_BRDC_FMAC_INTERRUPT_REGISTER_4_BCM88202_A0r_fields,
  50665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50666         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50667         -1,
  50668         -1,
  50669     },
  50670 #endif /* chips */
  50671 
  50672 #if defined(BCM_88650_B0)
  50673     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4_BCM88650_B0r */
  50674         soc_block_list[23],
  50675         soc_genreg,
  50676         1,
  50677         0,
  50678         0x4,
  50679         SOC_REG_FLAG_WO |
  50680                           SOC_REG_FLAG_INTERRUPT,
  50681         0,
  50682         2,
  50683         soc_BRDC_FMAC_INTERRUPT_REGISTER_4_BCM88650_B0r_fields,
  50684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50685         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50686         -1,
  50687         -1,
  50688     },
  50689 #endif /* chips */
  50690 
  50691 #if defined(BCM_88660_A0)
  50692     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4_BCM88660_A0r */
  50693         soc_block_list[23],
  50694         soc_genreg,
  50695         1,
  50696         0,
  50697         0x4,
  50698         SOC_REG_FLAG_WO |
  50699                           SOC_REG_FLAG_INTERRUPT,
  50700         0,
  50701         2,
  50702         soc_BRDC_FMAC_INTERRUPT_REGISTER_4_BCM88660_A0r_fields,
  50703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50704         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50705         -1,
  50706         -1,
  50707     },
  50708 #endif /* chips */
  50709 
  50710 #if defined(BCM_88650_A0)
  50711     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4_TESTr */
  50712         soc_block_list[23],
  50713         soc_genreg,
  50714         1,
  50715         0,
  50716         0x1e,
  50717         SOC_REG_FLAG_WO |
  50718                           SOC_REG_FLAG_INTERRUPT,
  50719         0,
  50720         1,
  50721         soc_BRDC_FMAC_INTERRUPT_REGISTER_4_TESTr_fields,
  50722         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50723         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50724         -1,
  50725         -1,
  50726     },
  50727 #endif /* chips */
  50728 
  50729 #if defined(BCM_88202_A0)
  50730     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88202_A0r */
  50731         soc_block_list[23],
  50732         soc_genreg,
  50733         1,
  50734         0,
  50735         0x1e,
  50736         SOC_REG_FLAG_WO |
  50737                           SOC_REG_FLAG_INTERRUPT,
  50738         0,
  50739         1,
  50740         soc_BRDC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88202_A0r_fields,
  50741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50742         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50743         -1,
  50744         -1,
  50745     },
  50746 #endif /* chips */
  50747 
  50748 #if defined(BCM_88650_B0)
  50749     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88650_B0r */
  50750         soc_block_list[23],
  50751         soc_genreg,
  50752         1,
  50753         0,
  50754         0x1e,
  50755         SOC_REG_FLAG_WO |
  50756                           SOC_REG_FLAG_INTERRUPT,
  50757         0,
  50758         1,
  50759         soc_BRDC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88650_B0r_fields,
  50760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50762         -1,
  50763         -1,
  50764     },
  50765 #endif /* chips */
  50766 
  50767 #if defined(BCM_88660_A0)
  50768     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88660_A0r */
  50769         soc_block_list[23],
  50770         soc_genreg,
  50771         1,
  50772         0,
  50773         0x1e,
  50774         SOC_REG_FLAG_WO |
  50775                           SOC_REG_FLAG_INTERRUPT,
  50776         0,
  50777         1,
  50778         soc_BRDC_FMAC_INTERRUPT_REGISTER_4_TEST_BCM88660_A0r_fields,
  50779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50781         -1,
  50782         -1,
  50783     },
  50784 #endif /* chips */
  50785 
  50786 #if defined(BCM_88202_A0)
  50787     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5_BCM88202_A0r */
  50788         soc_block_list[23],
  50789         soc_genreg,
  50790         1,
  50791         0,
  50792         0x5,
  50793         SOC_REG_FLAG_WO |
  50794                           SOC_REG_FLAG_INTERRUPT,
  50795         0,
  50796         2,
  50797         soc_BRDC_FMAC_INTERRUPT_REGISTER_5_BCM88202_A0r_fields,
  50798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50799         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50800         -1,
  50801         -1,
  50802     },
  50803 #endif /* chips */
  50804 
  50805 #if defined(BCM_88650_B0)
  50806     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5_BCM88650_B0r */
  50807         soc_block_list[23],
  50808         soc_genreg,
  50809         1,
  50810         0,
  50811         0x5,
  50812         SOC_REG_FLAG_WO |
  50813                           SOC_REG_FLAG_INTERRUPT,
  50814         0,
  50815         2,
  50816         soc_BRDC_FMAC_INTERRUPT_REGISTER_5_BCM88650_B0r_fields,
  50817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50818         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50819         -1,
  50820         -1,
  50821     },
  50822 #endif /* chips */
  50823 
  50824 #if defined(BCM_88660_A0)
  50825     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5_BCM88660_A0r */
  50826         soc_block_list[23],
  50827         soc_genreg,
  50828         1,
  50829         0,
  50830         0x5,
  50831         SOC_REG_FLAG_WO |
  50832                           SOC_REG_FLAG_INTERRUPT,
  50833         0,
  50834         2,
  50835         soc_BRDC_FMAC_INTERRUPT_REGISTER_5_BCM88660_A0r_fields,
  50836         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50837         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  50838         -1,
  50839         -1,
  50840     },
  50841 #endif /* chips */
  50842 
  50843 #if defined(BCM_88650_A0)
  50844     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5_TESTr */
  50845         soc_block_list[23],
  50846         soc_genreg,
  50847         1,
  50848         0,
  50849         0x1f,
  50850         SOC_REG_FLAG_WO |
  50851                           SOC_REG_FLAG_INTERRUPT,
  50852         0,
  50853         1,
  50854         soc_BRDC_FMAC_INTERRUPT_REGISTER_5_TESTr_fields,
  50855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50856         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50857         -1,
  50858         -1,
  50859     },
  50860 #endif /* chips */
  50861 
  50862 #if defined(BCM_88202_A0)
  50863     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88202_A0r */
  50864         soc_block_list[23],
  50865         soc_genreg,
  50866         1,
  50867         0,
  50868         0x1f,
  50869         SOC_REG_FLAG_WO |
  50870                           SOC_REG_FLAG_INTERRUPT,
  50871         0,
  50872         1,
  50873         soc_BRDC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88202_A0r_fields,
  50874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50876         -1,
  50877         -1,
  50878     },
  50879 #endif /* chips */
  50880 
  50881 #if defined(BCM_88650_B0)
  50882     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88650_B0r */
  50883         soc_block_list[23],
  50884         soc_genreg,
  50885         1,
  50886         0,
  50887         0x1f,
  50888         SOC_REG_FLAG_WO |
  50889                           SOC_REG_FLAG_INTERRUPT,
  50890         0,
  50891         1,
  50892         soc_BRDC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88650_B0r_fields,
  50893         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50894         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50895         -1,
  50896         -1,
  50897     },
  50898 #endif /* chips */
  50899 
  50900 #if defined(BCM_88660_A0)
  50901     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88660_A0r */
  50902         soc_block_list[23],
  50903         soc_genreg,
  50904         1,
  50905         0,
  50906         0x1f,
  50907         SOC_REG_FLAG_WO |
  50908                           SOC_REG_FLAG_INTERRUPT,
  50909         0,
  50910         1,
  50911         soc_BRDC_FMAC_INTERRUPT_REGISTER_5_TEST_BCM88660_A0r_fields,
  50912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50913         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50914         -1,
  50915         -1,
  50916     },
  50917 #endif /* chips */
  50918 
  50919 #if defined(BCM_88202_A0)
  50920     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6_BCM88202_A0r */
  50921         soc_block_list[23],
  50922         soc_genreg,
  50923         1,
  50924         0,
  50925         0x6,
  50926         SOC_REG_FLAG_WO |
  50927                           SOC_REG_FLAG_INTERRUPT,
  50928         0,
  50929         1,
  50930         soc_BRDC_FMAC_INTERRUPT_REGISTER_6_BCM88202_A0r_fields,
  50931         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50932         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50933         -1,
  50934         -1,
  50935     },
  50936 #endif /* chips */
  50937 
  50938 #if defined(BCM_88650_B0)
  50939     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6_BCM88650_B0r */
  50940         soc_block_list[23],
  50941         soc_genreg,
  50942         1,
  50943         0,
  50944         0x6,
  50945         SOC_REG_FLAG_WO |
  50946                           SOC_REG_FLAG_INTERRUPT,
  50947         0,
  50948         1,
  50949         soc_BRDC_FMAC_INTERRUPT_REGISTER_6_BCM88650_B0r_fields,
  50950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50951         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50952         -1,
  50953         -1,
  50954     },
  50955 #endif /* chips */
  50956 
  50957 #if defined(BCM_88660_A0)
  50958     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6_BCM88660_A0r */
  50959         soc_block_list[23],
  50960         soc_genreg,
  50961         1,
  50962         0,
  50963         0x6,
  50964         SOC_REG_FLAG_WO |
  50965                           SOC_REG_FLAG_INTERRUPT,
  50966         0,
  50967         1,
  50968         soc_BRDC_FMAC_INTERRUPT_REGISTER_6_BCM88660_A0r_fields,
  50969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50970         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  50971         -1,
  50972         -1,
  50973     },
  50974 #endif /* chips */
  50975 
  50976 #if defined(BCM_88650_A0)
  50977     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6_TESTr */
  50978         soc_block_list[23],
  50979         soc_genreg,
  50980         1,
  50981         0,
  50982         0x20,
  50983         SOC_REG_FLAG_WO |
  50984                           SOC_REG_FLAG_INTERRUPT,
  50985         0,
  50986         1,
  50987         soc_BRDC_FMAC_INTERRUPT_REGISTER_6_TESTr_fields,
  50988         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  50989         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  50990         -1,
  50991         -1,
  50992     },
  50993 #endif /* chips */
  50994 
  50995 #if defined(BCM_88202_A0)
  50996     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88202_A0r */
  50997         soc_block_list[23],
  50998         soc_genreg,
  50999         1,
  51000         0,
  51001         0x20,
  51002         SOC_REG_FLAG_WO |
  51003                           SOC_REG_FLAG_INTERRUPT,
  51004         0,
  51005         1,
  51006         soc_BRDC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88202_A0r_fields,
  51007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51008         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51009         -1,
  51010         -1,
  51011     },
  51012 #endif /* chips */
  51013 
  51014 #if defined(BCM_88650_B0)
  51015     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88650_B0r */
  51016         soc_block_list[23],
  51017         soc_genreg,
  51018         1,
  51019         0,
  51020         0x20,
  51021         SOC_REG_FLAG_WO |
  51022                           SOC_REG_FLAG_INTERRUPT,
  51023         0,
  51024         1,
  51025         soc_BRDC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88650_B0r_fields,
  51026         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51027         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51028         -1,
  51029         -1,
  51030     },
  51031 #endif /* chips */
  51032 
  51033 #if defined(BCM_88660_A0)
  51034     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88660_A0r */
  51035         soc_block_list[23],
  51036         soc_genreg,
  51037         1,
  51038         0,
  51039         0x20,
  51040         SOC_REG_FLAG_WO |
  51041                           SOC_REG_FLAG_INTERRUPT,
  51042         0,
  51043         1,
  51044         soc_BRDC_FMAC_INTERRUPT_REGISTER_6_TEST_BCM88660_A0r_fields,
  51045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51046         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51047         -1,
  51048         -1,
  51049     },
  51050 #endif /* chips */
  51051 
  51052 #if defined(BCM_88202_A0)
  51053     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7_BCM88202_A0r */
  51054         soc_block_list[23],
  51055         soc_genreg,
  51056         1,
  51057         0,
  51058         0x7,
  51059         SOC_REG_FLAG_WO |
  51060                           SOC_REG_FLAG_INTERRUPT,
  51061         0,
  51062         1,
  51063         soc_BRDC_FMAC_INTERRUPT_REGISTER_7_BCM88202_A0r_fields,
  51064         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51065         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  51066         -1,
  51067         -1,
  51068     },
  51069 #endif /* chips */
  51070 
  51071 #if defined(BCM_88650_B0)
  51072     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7_BCM88650_B0r */
  51073         soc_block_list[23],
  51074         soc_genreg,
  51075         1,
  51076         0,
  51077         0x7,
  51078         SOC_REG_FLAG_WO |
  51079                           SOC_REG_FLAG_INTERRUPT,
  51080         0,
  51081         1,
  51082         soc_BRDC_FMAC_INTERRUPT_REGISTER_7_BCM88650_B0r_fields,
  51083         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51084         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  51085         -1,
  51086         -1,
  51087     },
  51088 #endif /* chips */
  51089 
  51090 #if defined(BCM_88660_A0)
  51091     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7_BCM88660_A0r */
  51092         soc_block_list[23],
  51093         soc_genreg,
  51094         1,
  51095         0,
  51096         0x7,
  51097         SOC_REG_FLAG_WO |
  51098                           SOC_REG_FLAG_INTERRUPT,
  51099         0,
  51100         1,
  51101         soc_BRDC_FMAC_INTERRUPT_REGISTER_7_BCM88660_A0r_fields,
  51102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51103         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  51104         -1,
  51105         -1,
  51106     },
  51107 #endif /* chips */
  51108 
  51109 #if defined(BCM_88650_A0)
  51110     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7_TESTr */
  51111         soc_block_list[23],
  51112         soc_genreg,
  51113         1,
  51114         0,
  51115         0x21,
  51116         SOC_REG_FLAG_WO |
  51117                           SOC_REG_FLAG_INTERRUPT,
  51118         0,
  51119         1,
  51120         soc_BRDC_FMAC_INTERRUPT_REGISTER_7_TESTr_fields,
  51121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51122         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51123         -1,
  51124         -1,
  51125     },
  51126 #endif /* chips */
  51127 
  51128 #if defined(BCM_88202_A0)
  51129     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88202_A0r */
  51130         soc_block_list[23],
  51131         soc_genreg,
  51132         1,
  51133         0,
  51134         0x21,
  51135         SOC_REG_FLAG_WO |
  51136                           SOC_REG_FLAG_INTERRUPT,
  51137         0,
  51138         1,
  51139         soc_BRDC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88202_A0r_fields,
  51140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51141         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51142         -1,
  51143         -1,
  51144     },
  51145 #endif /* chips */
  51146 
  51147 #if defined(BCM_88650_B0)
  51148     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88650_B0r */
  51149         soc_block_list[23],
  51150         soc_genreg,
  51151         1,
  51152         0,
  51153         0x21,
  51154         SOC_REG_FLAG_WO |
  51155                           SOC_REG_FLAG_INTERRUPT,
  51156         0,
  51157         1,
  51158         soc_BRDC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88650_B0r_fields,
  51159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51160         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51161         -1,
  51162         -1,
  51163     },
  51164 #endif /* chips */
  51165 
  51166 #if defined(BCM_88660_A0)
  51167     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88660_A0r */
  51168         soc_block_list[23],
  51169         soc_genreg,
  51170         1,
  51171         0,
  51172         0x21,
  51173         SOC_REG_FLAG_WO |
  51174                           SOC_REG_FLAG_INTERRUPT,
  51175         0,
  51176         1,
  51177         soc_BRDC_FMAC_INTERRUPT_REGISTER_7_TEST_BCM88660_A0r_fields,
  51178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51179         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51180         -1,
  51181         -1,
  51182     },
  51183 #endif /* chips */
  51184 
  51185 #if defined(BCM_88202_A0)
  51186     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8_BCM88202_A0r */
  51187         soc_block_list[23],
  51188         soc_genreg,
  51189         1,
  51190         0,
  51191         0x8,
  51192         SOC_REG_FLAG_WO |
  51193                           SOC_REG_FLAG_INTERRUPT,
  51194         0,
  51195         3,
  51196         soc_BRDC_FMAC_INTERRUPT_REGISTER_8_BCM88202_A0r_fields,
  51197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51198         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51199         -1,
  51200         -1,
  51201     },
  51202 #endif /* chips */
  51203 
  51204 #if defined(BCM_88650_B0)
  51205     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8_BCM88650_B0r */
  51206         soc_block_list[23],
  51207         soc_genreg,
  51208         1,
  51209         0,
  51210         0x8,
  51211         SOC_REG_FLAG_WO |
  51212                           SOC_REG_FLAG_INTERRUPT,
  51213         0,
  51214         3,
  51215         soc_BRDC_FMAC_INTERRUPT_REGISTER_8_BCM88650_B0r_fields,
  51216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51217         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51218         -1,
  51219         -1,
  51220     },
  51221 #endif /* chips */
  51222 
  51223 #if defined(BCM_88660_A0)
  51224     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8_BCM88660_A0r */
  51225         soc_block_list[23],
  51226         soc_genreg,
  51227         1,
  51228         0,
  51229         0x8,
  51230         SOC_REG_FLAG_WO |
  51231                           SOC_REG_FLAG_INTERRUPT,
  51232         0,
  51233         3,
  51234         soc_BRDC_FMAC_INTERRUPT_REGISTER_8_BCM88660_A0r_fields,
  51235         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51236         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  51237         -1,
  51238         -1,
  51239     },
  51240 #endif /* chips */
  51241 
  51242 #if defined(BCM_88650_A0)
  51243     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8_TESTr */
  51244         soc_block_list[23],
  51245         soc_genreg,
  51246         1,
  51247         0,
  51248         0x22,
  51249         SOC_REG_FLAG_WO |
  51250                           SOC_REG_FLAG_INTERRUPT,
  51251         0,
  51252         1,
  51253         soc_BRDC_FMAC_INTERRUPT_REGISTER_8_TESTr_fields,
  51254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51255         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51256         -1,
  51257         -1,
  51258     },
  51259 #endif /* chips */
  51260 
  51261 #if defined(BCM_88202_A0)
  51262     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88202_A0r */
  51263         soc_block_list[23],
  51264         soc_genreg,
  51265         1,
  51266         0,
  51267         0x22,
  51268         SOC_REG_FLAG_WO |
  51269                           SOC_REG_FLAG_INTERRUPT,
  51270         0,
  51271         1,
  51272         soc_BRDC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88202_A0r_fields,
  51273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51274         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51275         -1,
  51276         -1,
  51277     },
  51278 #endif /* chips */
  51279 
  51280 #if defined(BCM_88650_B0)
  51281     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88650_B0r */
  51282         soc_block_list[23],
  51283         soc_genreg,
  51284         1,
  51285         0,
  51286         0x22,
  51287         SOC_REG_FLAG_WO |
  51288                           SOC_REG_FLAG_INTERRUPT,
  51289         0,
  51290         1,
  51291         soc_BRDC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88650_B0r_fields,
  51292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51293         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51294         -1,
  51295         -1,
  51296     },
  51297 #endif /* chips */
  51298 
  51299 #if defined(BCM_88660_A0)
  51300     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88660_A0r */
  51301         soc_block_list[23],
  51302         soc_genreg,
  51303         1,
  51304         0,
  51305         0x22,
  51306         SOC_REG_FLAG_WO |
  51307                           SOC_REG_FLAG_INTERRUPT,
  51308         0,
  51309         1,
  51310         soc_BRDC_FMAC_INTERRUPT_REGISTER_8_TEST_BCM88660_A0r_fields,
  51311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51312         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51313         -1,
  51314         -1,
  51315     },
  51316 #endif /* chips */
  51317 
  51318 #if defined(BCM_88202_A0)
  51319     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9_BCM88202_A0r */
  51320         soc_block_list[23],
  51321         soc_genreg,
  51322         1,
  51323         0,
  51324         0x9,
  51325         SOC_REG_FLAG_WO |
  51326                           SOC_REG_FLAG_INTERRUPT,
  51327         0,
  51328         2,
  51329         soc_BRDC_FMAC_INTERRUPT_REGISTER_9_BCM88202_A0r_fields,
  51330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51331         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51332         -1,
  51333         -1,
  51334     },
  51335 #endif /* chips */
  51336 
  51337 #if defined(BCM_88650_B0)
  51338     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9_BCM88650_B0r */
  51339         soc_block_list[23],
  51340         soc_genreg,
  51341         1,
  51342         0,
  51343         0x9,
  51344         SOC_REG_FLAG_WO |
  51345                           SOC_REG_FLAG_INTERRUPT,
  51346         0,
  51347         2,
  51348         soc_BRDC_FMAC_INTERRUPT_REGISTER_9_BCM88650_B0r_fields,
  51349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51350         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51351         -1,
  51352         -1,
  51353     },
  51354 #endif /* chips */
  51355 
  51356 #if defined(BCM_88660_A0)
  51357     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9_BCM88660_A0r */
  51358         soc_block_list[23],
  51359         soc_genreg,
  51360         1,
  51361         0,
  51362         0x9,
  51363         SOC_REG_FLAG_WO |
  51364                           SOC_REG_FLAG_INTERRUPT,
  51365         0,
  51366         2,
  51367         soc_BRDC_FMAC_INTERRUPT_REGISTER_9_BCM88660_A0r_fields,
  51368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51369         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  51370         -1,
  51371         -1,
  51372     },
  51373 #endif /* chips */
  51374 
  51375 #if defined(BCM_88650_A0)
  51376     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9_TESTr */
  51377         soc_block_list[23],
  51378         soc_genreg,
  51379         1,
  51380         0,
  51381         0x23,
  51382         SOC_REG_FLAG_WO |
  51383                           SOC_REG_FLAG_INTERRUPT,
  51384         0,
  51385         1,
  51386         soc_BRDC_FMAC_INTERRUPT_REGISTER_9_TESTr_fields,
  51387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51388         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51389         -1,
  51390         -1,
  51391     },
  51392 #endif /* chips */
  51393 
  51394 #if defined(BCM_88202_A0)
  51395     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9_TEST_BCM88202_A0r */
  51396         soc_block_list[23],
  51397         soc_genreg,
  51398         1,
  51399         0,
  51400         0x23,
  51401         SOC_REG_FLAG_WO |
  51402                           SOC_REG_FLAG_INTERRUPT,
  51403         0,
  51404         1,
  51405         soc_BRDC_FMAC_INTERRUPT_REGISTER_9_TEST_BCM88202_A0r_fields,
  51406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51407         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51408         -1,
  51409         -1,
  51410     },
  51411 #endif /* chips */
  51412 
  51413 #if defined(BCM_88650_B0)
  51414     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9_TEST_BCM88650_B0r */
  51415         soc_block_list[23],
  51416         soc_genreg,
  51417         1,
  51418         0,
  51419         0x23,
  51420         SOC_REG_FLAG_WO |
  51421                           SOC_REG_FLAG_INTERRUPT,
  51422         0,
  51423         1,
  51424         soc_BRDC_FMAC_INTERRUPT_REGISTER_9_TEST_BCM88650_B0r_fields,
  51425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51426         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51427         -1,
  51428         -1,
  51429     },
  51430 #endif /* chips */
  51431 
  51432 #if defined(BCM_88660_A0)
  51433     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_9_TEST_BCM88660_A0r */
  51434         soc_block_list[23],
  51435         soc_genreg,
  51436         1,
  51437         0,
  51438         0x23,
  51439         SOC_REG_FLAG_WO |
  51440                           SOC_REG_FLAG_INTERRUPT,
  51441         0,
  51442         1,
  51443         soc_BRDC_FMAC_INTERRUPT_REGISTER_9_TEST_BCM88660_A0r_fields,
  51444         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51445         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51446         -1,
  51447         -1,
  51448     },
  51449 #endif /* chips */
  51450 
  51451 #if defined(BCM_83208_A0)
  51452     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM83208_A0r */
  51453         soc_block_list[23],
  51454         soc_genreg,
  51455         1,
  51456         0,
  51457         0,
  51458         SOC_REG_FLAG_WO |
  51459                           SOC_REG_FLAG_INTERRUPT,
  51460         0,
  51461         14,
  51462         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM83208_A0r_fields,
  51463         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51464         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  51465         -1,
  51466         -1,
  51467     },
  51468 #endif /* chips */
  51469 
  51470 #if defined(BCM_88202_A0)
  51471     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88202_A0r */
  51472         soc_block_list[23],
  51473         soc_genreg,
  51474         1,
  51475         0,
  51476         0,
  51477         SOC_REG_FLAG_WO |
  51478                           SOC_REG_FLAG_INTERRUPT,
  51479         0,
  51480         9,
  51481         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88202_A0r_fields,
  51482         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51483         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51484         -1,
  51485         -1,
  51486     },
  51487 #endif /* chips */
  51488 
  51489 #if defined(BCM_88375_A0)
  51490     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88375_A0r */
  51491         soc_block_list[23],
  51492         soc_genreg,
  51493         1,
  51494         0,
  51495         0,
  51496         SOC_REG_FLAG_RO |
  51497                           SOC_REG_FLAG_WO |
  51498                           SOC_REG_FLAG_INTERRUPT,
  51499         0,
  51500         9,
  51501         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  51502         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51503         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51504         -1,
  51505         -1,
  51506     },
  51507 #endif /* chips */
  51508 
  51509 #if defined(BCM_88375_B0)
  51510     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88375_B0r */
  51511         soc_block_list[23],
  51512         soc_genreg,
  51513         1,
  51514         0,
  51515         0,
  51516         SOC_REG_FLAG_RO |
  51517                           SOC_REG_FLAG_WO |
  51518                           SOC_REG_FLAG_INTERRUPT,
  51519         0,
  51520         9,
  51521         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  51522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51523         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51524         -1,
  51525         -1,
  51526     },
  51527 #endif /* chips */
  51528 
  51529 #if defined(BCM_88470_A0)
  51530     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88470_A0r */
  51531         soc_block_list[23],
  51532         soc_genreg,
  51533         1,
  51534         0,
  51535         0,
  51536         SOC_REG_FLAG_RO |
  51537                           SOC_REG_FLAG_WO |
  51538                           SOC_REG_FLAG_INTERRUPT |
  51539                           SOC_REG_FLAG_SIGNAL,
  51540         0,
  51541         9,
  51542         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88470_A0r_fields,
  51543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51544         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51545         -1,
  51546         -1,
  51547     },
  51548 #endif /* chips */
  51549 
  51550 #if defined(BCM_88470_B0)
  51551     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88470_B0r */
  51552         soc_block_list[23],
  51553         soc_genreg,
  51554         1,
  51555         0,
  51556         0,
  51557         SOC_REG_FLAG_RO |
  51558                           SOC_REG_FLAG_WO |
  51559                           SOC_REG_FLAG_INTERRUPT |
  51560                           SOC_REG_FLAG_SIGNAL,
  51561         0,
  51562         9,
  51563         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88470_B0r_fields,
  51564         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51565         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51566         -1,
  51567         -1,
  51568     },
  51569 #endif /* chips */
  51570 
  51571 #if defined(BCM_88650_B0)
  51572     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88650_B0r */
  51573         soc_block_list[23],
  51574         soc_genreg,
  51575         1,
  51576         0,
  51577         0,
  51578         SOC_REG_FLAG_WO |
  51579                           SOC_REG_FLAG_INTERRUPT,
  51580         0,
  51581         9,
  51582         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88650_B0r_fields,
  51583         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51584         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51585         -1,
  51586         -1,
  51587     },
  51588 #endif /* chips */
  51589 
  51590 #if defined(BCM_88660_A0)
  51591     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88660_A0r */
  51592         soc_block_list[23],
  51593         soc_genreg,
  51594         1,
  51595         0,
  51596         0,
  51597         SOC_REG_FLAG_WO |
  51598                           SOC_REG_FLAG_INTERRUPT,
  51599         0,
  51600         9,
  51601         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88660_A0r_fields,
  51602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51603         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51604         -1,
  51605         -1,
  51606     },
  51607 #endif /* chips */
  51608 
  51609 #if defined(BCM_88675_A0)
  51610     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88675_A0r */
  51611         soc_block_list[23],
  51612         soc_genreg,
  51613         1,
  51614         0,
  51615         0,
  51616         SOC_REG_FLAG_RO |
  51617                           SOC_REG_FLAG_WO |
  51618                           SOC_REG_FLAG_INTERRUPT,
  51619         0,
  51620         9,
  51621         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  51622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51623         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51624         -1,
  51625         -1,
  51626     },
  51627 #endif /* chips */
  51628 
  51629 #if defined(BCM_88675_B0)
  51630     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88675_B0r */
  51631         soc_block_list[23],
  51632         soc_genreg,
  51633         1,
  51634         0,
  51635         0,
  51636         SOC_REG_FLAG_RO |
  51637                           SOC_REG_FLAG_WO |
  51638                           SOC_REG_FLAG_INTERRUPT,
  51639         0,
  51640         9,
  51641         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  51642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51643         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51644         -1,
  51645         -1,
  51646     },
  51647 #endif /* chips */
  51648 
  51649 #if defined(BCM_88680_A0)
  51650     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88680_A0r */
  51651         soc_block_list[23],
  51652         soc_genreg,
  51653         1,
  51654         0,
  51655         0,
  51656         SOC_REG_FLAG_RO |
  51657                           SOC_REG_FLAG_WO |
  51658                           SOC_REG_FLAG_INTERRUPT,
  51659         0,
  51660         9,
  51661         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  51662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51663         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51664         -1,
  51665         -1,
  51666     },
  51667 #endif /* chips */
  51668 
  51669 #if defined(BCM_88690_A0)
  51670     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88690_A0r */
  51671         soc_block_list[23],
  51672         soc_genreg,
  51673         1,
  51674         0,
  51675         0,
  51676         SOC_REG_FLAG_64_BITS |
  51677                           SOC_REG_FLAG_WO |
  51678                           SOC_REG_FLAG_INTERRUPT |
  51679                           SOC_REG_FLAG_SIGNAL,
  51680         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  51681         22,
  51682         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  51683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51684         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  51685         -1,
  51686         -1,
  51687     },
  51688 #endif /* chips */
  51689 
  51690 #if defined(BCM_88690_B0)
  51691     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88690_B0r */
  51692         soc_block_list[23],
  51693         soc_genreg,
  51694         1,
  51695         0,
  51696         0,
  51697         SOC_REG_FLAG_64_BITS |
  51698                           SOC_REG_FLAG_WO |
  51699                           SOC_REG_FLAG_INTERRUPT |
  51700                           SOC_REG_FLAG_SIGNAL,
  51701         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  51702         22,
  51703         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  51704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51705         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  51706         -1,
  51707         -1,
  51708     },
  51709 #endif /* chips */
  51710 
  51711 #if defined(BCM_88790_A0)
  51712     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_BCM88790_A0r */
  51713         soc_block_list[23],
  51714         soc_genreg,
  51715         1,
  51716         0,
  51717         0,
  51718         SOC_REG_FLAG_64_BITS |
  51719                           SOC_REG_FLAG_WO |
  51720                           SOC_REG_FLAG_INTERRUPT |
  51721                           SOC_REG_FLAG_SIGNAL,
  51722         0,
  51723         22,
  51724         soc_BRDC_FMAC_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  51725         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51726         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  51727         -1,
  51728         -1,
  51729     },
  51730 #endif /* chips */
  51731 
  51732 #if defined(BCM_88650_A0)
  51733     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TESTr */
  51734         soc_block_list[23],
  51735         soc_genreg,
  51736         1,
  51737         0,
  51738         0x1a,
  51739         SOC_REG_FLAG_WO |
  51740                           SOC_REG_FLAG_INTERRUPT,
  51741         0,
  51742         1,
  51743         soc_BRDC_FMAC_INTERRUPT_REGISTER_TESTr_fields,
  51744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51745         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51746         -1,
  51747         -1,
  51748     },
  51749 #endif /* chips */
  51750 
  51751 #if defined(BCM_83208_A0)
  51752     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM83208_A0r */
  51753         soc_block_list[23],
  51754         soc_genreg,
  51755         1,
  51756         0,
  51757         0x18,
  51758         SOC_REG_FLAG_WO,
  51759         0,
  51760         1,
  51761         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM83208_A0r_fields,
  51762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51764         -1,
  51765         -1,
  51766     },
  51767 #endif /* chips */
  51768 
  51769 #if defined(BCM_88202_A0)
  51770     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88202_A0r */
  51771         soc_block_list[23],
  51772         soc_genreg,
  51773         1,
  51774         0,
  51775         0x1a,
  51776         SOC_REG_FLAG_WO |
  51777                           SOC_REG_FLAG_INTERRUPT,
  51778         0,
  51779         1,
  51780         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88202_A0r_fields,
  51781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51782         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51783         -1,
  51784         -1,
  51785     },
  51786 #endif /* chips */
  51787 
  51788 #if defined(BCM_88375_A0)
  51789     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  51790         soc_block_list[23],
  51791         soc_genreg,
  51792         1,
  51793         0,
  51794         0x18,
  51795         SOC_REG_FLAG_WO,
  51796         0,
  51797         1,
  51798         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  51799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51801         -1,
  51802         -1,
  51803     },
  51804 #endif /* chips */
  51805 
  51806 #if defined(BCM_88375_B0)
  51807     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  51808         soc_block_list[23],
  51809         soc_genreg,
  51810         1,
  51811         0,
  51812         0x18,
  51813         SOC_REG_FLAG_WO,
  51814         0,
  51815         1,
  51816         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  51817         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51818         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51819         -1,
  51820         -1,
  51821     },
  51822 #endif /* chips */
  51823 
  51824 #if defined(BCM_88470_A0)
  51825     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88470_A0r */
  51826         soc_block_list[23],
  51827         soc_genreg,
  51828         1,
  51829         0,
  51830         0x18,
  51831         SOC_REG_FLAG_WO,
  51832         0,
  51833         1,
  51834         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88470_A0r_fields,
  51835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51836         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51837         -1,
  51838         -1,
  51839     },
  51840 #endif /* chips */
  51841 
  51842 #if defined(BCM_88470_B0)
  51843     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88470_B0r */
  51844         soc_block_list[23],
  51845         soc_genreg,
  51846         1,
  51847         0,
  51848         0x18,
  51849         SOC_REG_FLAG_WO,
  51850         0,
  51851         1,
  51852         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88470_B0r_fields,
  51853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51854         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51855         -1,
  51856         -1,
  51857     },
  51858 #endif /* chips */
  51859 
  51860 #if defined(BCM_88650_B0)
  51861     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88650_B0r */
  51862         soc_block_list[23],
  51863         soc_genreg,
  51864         1,
  51865         0,
  51866         0x1a,
  51867         SOC_REG_FLAG_WO |
  51868                           SOC_REG_FLAG_INTERRUPT,
  51869         0,
  51870         1,
  51871         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88650_B0r_fields,
  51872         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51873         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51874         -1,
  51875         -1,
  51876     },
  51877 #endif /* chips */
  51878 
  51879 #if defined(BCM_88660_A0)
  51880     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88660_A0r */
  51881         soc_block_list[23],
  51882         soc_genreg,
  51883         1,
  51884         0,
  51885         0x1a,
  51886         SOC_REG_FLAG_WO |
  51887                           SOC_REG_FLAG_INTERRUPT,
  51888         0,
  51889         1,
  51890         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88660_A0r_fields,
  51891         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51892         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  51893         -1,
  51894         -1,
  51895     },
  51896 #endif /* chips */
  51897 
  51898 #if defined(BCM_88675_A0)
  51899     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  51900         soc_block_list[23],
  51901         soc_genreg,
  51902         1,
  51903         0,
  51904         0x18,
  51905         SOC_REG_FLAG_WO,
  51906         0,
  51907         1,
  51908         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  51909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51910         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51911         -1,
  51912         -1,
  51913     },
  51914 #endif /* chips */
  51915 
  51916 #if defined(BCM_88675_B0)
  51917     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  51918         soc_block_list[23],
  51919         soc_genreg,
  51920         1,
  51921         0,
  51922         0x18,
  51923         SOC_REG_FLAG_WO,
  51924         0,
  51925         1,
  51926         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  51927         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51928         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51929         -1,
  51930         -1,
  51931     },
  51932 #endif /* chips */
  51933 
  51934 #if defined(BCM_88680_A0)
  51935     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  51936         soc_block_list[23],
  51937         soc_genreg,
  51938         1,
  51939         0,
  51940         0x18,
  51941         SOC_REG_FLAG_WO,
  51942         0,
  51943         1,
  51944         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  51945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51946         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  51947         -1,
  51948         -1,
  51949     },
  51950 #endif /* chips */
  51951 
  51952 #if defined(BCM_88690_A0)
  51953     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  51954         soc_block_list[23],
  51955         soc_genreg,
  51956         1,
  51957         0,
  51958         0x18,
  51959         SOC_REG_FLAG_64_BITS |
  51960                           SOC_REG_FLAG_WO,
  51961         0,
  51962         1,
  51963         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  51964         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51965         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  51966         -1,
  51967         -1,
  51968     },
  51969 #endif /* chips */
  51970 
  51971 #if defined(BCM_88690_B0)
  51972     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  51973         soc_block_list[23],
  51974         soc_genreg,
  51975         1,
  51976         0,
  51977         0x18,
  51978         SOC_REG_FLAG_64_BITS |
  51979                           SOC_REG_FLAG_WO,
  51980         0,
  51981         1,
  51982         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  51983         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  51984         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  51985         -1,
  51986         -1,
  51987     },
  51988 #endif /* chips */
  51989 
  51990 #if defined(BCM_88790_A0)
  51991     { /* SOC_REG_INT_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  51992         soc_block_list[23],
  51993         soc_genreg,
  51994         1,
  51995         0,
  51996         0x18,
  51997         SOC_REG_FLAG_64_BITS |
  51998                           SOC_REG_FLAG_WO,
  51999         0,
  52000         1,
  52001         soc_BRDC_FMAC_INTERRUPT_REGISTER_TEST_BCM88790_A0r_fields,
  52002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52003         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  52004         -1,
  52005         -1,
  52006     },
  52007 #endif /* chips */
  52008 
  52009 #if defined(BCM_88650_A0)
  52010     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATIONr */
  52011         soc_block_list[23],
  52012         soc_genreg,
  52013         4,
  52014         0,
  52015         0x160,
  52016         SOC_REG_FLAG_ARRAY |
  52017                           SOC_REG_FLAG_WO |
  52018                           SOC_REG_FLAG_REG_ARRAY,
  52019         0,
  52020         10,
  52021         soc_BRDC_FMAC_KPCS_CONFIGURATIONr_fields,
  52022         SOC_RESET_VAL_DEC(0x001f000f, 0x00000000)
  52023         SOC_RESET_MASK_DEC(0x003f000f, 0x00000000)
  52024         -1,
  52025         -1,
  52026     },
  52027 #endif /* chips */
  52028 
  52029 #if defined(BCM_83208_A0)
  52030     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM83208_A0r */
  52031         soc_block_list[23],
  52032         soc_genreg,
  52033         4,
  52034         0,
  52035         0x16e,
  52036         SOC_REG_FLAG_ARRAY |
  52037                           SOC_REG_FLAG_WO |
  52038                           SOC_REG_FLAG_REG_ARRAY,
  52039         0,
  52040         11,
  52041         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM83208_A0r_fields,
  52042         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52043         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52044         -1,
  52045         -1,
  52046     },
  52047 #endif /* chips */
  52048 
  52049 #if defined(BCM_88202_A0)
  52050     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88202_A0r */
  52051         soc_block_list[23],
  52052         soc_genreg,
  52053         4,
  52054         0,
  52055         0x160,
  52056         SOC_REG_FLAG_ARRAY |
  52057                           SOC_REG_FLAG_WO |
  52058                           SOC_REG_FLAG_REG_ARRAY,
  52059         0,
  52060         10,
  52061         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88202_A0r_fields,
  52062         SOC_RESET_VAL_DEC(0x001f000f, 0x00000000)
  52063         SOC_RESET_MASK_DEC(0x003f000f, 0x00000000)
  52064         -1,
  52065         -1,
  52066     },
  52067 #endif /* chips */
  52068 
  52069 #if defined(BCM_88375_A0)
  52070     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88375_A0r */
  52071         soc_block_list[23],
  52072         soc_genreg,
  52073         4,
  52074         0,
  52075         0x160,
  52076         SOC_REG_FLAG_ARRAY |
  52077                           SOC_REG_FLAG_WO |
  52078                           SOC_REG_FLAG_REG_ARRAY,
  52079         0,
  52080         11,
  52081         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88375_A0r_fields,
  52082         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52083         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52084         -1,
  52085         -1,
  52086     },
  52087 #endif /* chips */
  52088 
  52089 #if defined(BCM_88375_B0)
  52090     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88375_B0r */
  52091         soc_block_list[23],
  52092         soc_genreg,
  52093         4,
  52094         0,
  52095         0x160,
  52096         SOC_REG_FLAG_ARRAY |
  52097                           SOC_REG_FLAG_WO |
  52098                           SOC_REG_FLAG_REG_ARRAY,
  52099         0,
  52100         11,
  52101         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88375_B0r_fields,
  52102         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52103         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52104         -1,
  52105         -1,
  52106     },
  52107 #endif /* chips */
  52108 
  52109 #if defined(BCM_88470_A0)
  52110     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88470_A0r */
  52111         soc_block_list[23],
  52112         soc_genreg,
  52113         4,
  52114         0,
  52115         0x160,
  52116         SOC_REG_FLAG_ARRAY |
  52117                           SOC_REG_FLAG_WO |
  52118                           SOC_REG_FLAG_REG_ARRAY,
  52119         0,
  52120         11,
  52121         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88470_A0r_fields,
  52122         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52123         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52124         -1,
  52125         -1,
  52126     },
  52127 #endif /* chips */
  52128 
  52129 #if defined(BCM_88470_B0)
  52130     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88470_B0r */
  52131         soc_block_list[23],
  52132         soc_genreg,
  52133         4,
  52134         0,
  52135         0x160,
  52136         SOC_REG_FLAG_ARRAY |
  52137                           SOC_REG_FLAG_WO |
  52138                           SOC_REG_FLAG_REG_ARRAY,
  52139         0,
  52140         11,
  52141         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88470_B0r_fields,
  52142         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52143         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52144         -1,
  52145         -1,
  52146     },
  52147 #endif /* chips */
  52148 
  52149 #if defined(BCM_88650_B0)
  52150     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88650_B0r */
  52151         soc_block_list[23],
  52152         soc_genreg,
  52153         4,
  52154         0,
  52155         0x160,
  52156         SOC_REG_FLAG_ARRAY |
  52157                           SOC_REG_FLAG_WO |
  52158                           SOC_REG_FLAG_REG_ARRAY,
  52159         0,
  52160         10,
  52161         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88650_B0r_fields,
  52162         SOC_RESET_VAL_DEC(0x001f000f, 0x00000000)
  52163         SOC_RESET_MASK_DEC(0x003f000f, 0x00000000)
  52164         -1,
  52165         -1,
  52166     },
  52167 #endif /* chips */
  52168 
  52169 #if defined(BCM_88660_A0)
  52170     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88660_A0r */
  52171         soc_block_list[23],
  52172         soc_genreg,
  52173         4,
  52174         0,
  52175         0x160,
  52176         SOC_REG_FLAG_ARRAY |
  52177                           SOC_REG_FLAG_WO |
  52178                           SOC_REG_FLAG_REG_ARRAY,
  52179         0,
  52180         10,
  52181         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88660_A0r_fields,
  52182         SOC_RESET_VAL_DEC(0x001f000f, 0x00000000)
  52183         SOC_RESET_MASK_DEC(0x003f000f, 0x00000000)
  52184         -1,
  52185         -1,
  52186     },
  52187 #endif /* chips */
  52188 
  52189 #if defined(BCM_88675_A0)
  52190     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88675_A0r */
  52191         soc_block_list[23],
  52192         soc_genreg,
  52193         4,
  52194         0,
  52195         0x160,
  52196         SOC_REG_FLAG_ARRAY |
  52197                           SOC_REG_FLAG_WO |
  52198                           SOC_REG_FLAG_REG_ARRAY,
  52199         0,
  52200         11,
  52201         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88675_A0r_fields,
  52202         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52203         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52204         -1,
  52205         -1,
  52206     },
  52207 #endif /* chips */
  52208 
  52209 #if defined(BCM_88675_B0)
  52210     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88675_B0r */
  52211         soc_block_list[23],
  52212         soc_genreg,
  52213         4,
  52214         0,
  52215         0x160,
  52216         SOC_REG_FLAG_ARRAY |
  52217                           SOC_REG_FLAG_WO |
  52218                           SOC_REG_FLAG_REG_ARRAY,
  52219         0,
  52220         11,
  52221         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88675_B0r_fields,
  52222         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52223         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52224         -1,
  52225         -1,
  52226     },
  52227 #endif /* chips */
  52228 
  52229 #if defined(BCM_88680_A0)
  52230     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88680_A0r */
  52231         soc_block_list[23],
  52232         soc_genreg,
  52233         4,
  52234         0,
  52235         0x160,
  52236         SOC_REG_FLAG_ARRAY |
  52237                           SOC_REG_FLAG_WO |
  52238                           SOC_REG_FLAG_REG_ARRAY,
  52239         0,
  52240         11,
  52241         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88680_A0r_fields,
  52242         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52243         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52244         -1,
  52245         -1,
  52246     },
  52247 #endif /* chips */
  52248 
  52249 #if defined(BCM_88690_A0)
  52250     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88690_A0r */
  52251         soc_block_list[23],
  52252         soc_genreg,
  52253         4,
  52254         0,
  52255         0x1aa,
  52256         SOC_REG_FLAG_ARRAY |
  52257                           SOC_REG_FLAG_WO |
  52258                           SOC_REG_FLAG_REG_ARRAY,
  52259         0,
  52260         11,
  52261         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88690_A0r_fields,
  52262         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52263         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52264         -1,
  52265         -1,
  52266     },
  52267 #endif /* chips */
  52268 
  52269 #if defined(BCM_88690_B0)
  52270     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88690_B0r */
  52271         soc_block_list[23],
  52272         soc_genreg,
  52273         4,
  52274         0,
  52275         0x1aa,
  52276         SOC_REG_FLAG_ARRAY |
  52277                           SOC_REG_FLAG_WO |
  52278                           SOC_REG_FLAG_REG_ARRAY,
  52279         0,
  52280         11,
  52281         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88690_B0r_fields,
  52282         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52283         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52284         -1,
  52285         -1,
  52286     },
  52287 #endif /* chips */
  52288 
  52289 #if defined(BCM_88790_A0)
  52290     { /* SOC_REG_INT_BRDC_FMAC_KPCS_CONFIGURATION_BCM88790_A0r */
  52291         soc_block_list[23],
  52292         soc_genreg,
  52293         4,
  52294         0,
  52295         0x1aa,
  52296         SOC_REG_FLAG_ARRAY |
  52297                           SOC_REG_FLAG_WO |
  52298                           SOC_REG_FLAG_REG_ARRAY,
  52299         0,
  52300         11,
  52301         soc_BRDC_FMAC_KPCS_CONFIGURATION_BCM88790_A0r_fields,
  52302         SOC_RESET_VAL_DEC(0x003f000f, 0x00000000)
  52303         SOC_RESET_MASK_DEC(0x007f000f, 0x00000000)
  52304         -1,
  52305         -1,
  52306     },
  52307 #endif /* chips */
  52308 
  52309 #if defined(BCM_88650_A0)
  52310     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUSr */
  52311         soc_block_list[23],
  52312         soc_genreg,
  52313         4,
  52314         0,
  52315         0x164,
  52316         SOC_REG_FLAG_ARRAY |
  52317                           SOC_REG_FLAG_WO |
  52318                           SOC_REG_FLAG_REG_ARRAY,
  52319         0,
  52320         2,
  52321         soc_BRDC_FMAC_KPCS_RX_STATUSr_fields,
  52322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52323         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52324         -1,
  52325         -1,
  52326     },
  52327 #endif /* chips */
  52328 
  52329 #if defined(BCM_83208_A0)
  52330     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM83208_A0r */
  52331         soc_block_list[23],
  52332         soc_genreg,
  52333         4,
  52334         0,
  52335         0x172,
  52336         SOC_REG_FLAG_ARRAY |
  52337                           SOC_REG_FLAG_RO |
  52338                           SOC_REG_FLAG_WO |
  52339                           SOC_REG_FLAG_REG_ARRAY,
  52340         0,
  52341         2,
  52342         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM83208_A0r_fields,
  52343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52344         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52345         -1,
  52346         -1,
  52347     },
  52348 #endif /* chips */
  52349 
  52350 #if defined(BCM_88202_A0)
  52351     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88202_A0r */
  52352         soc_block_list[23],
  52353         soc_genreg,
  52354         4,
  52355         0,
  52356         0x164,
  52357         SOC_REG_FLAG_ARRAY |
  52358                           SOC_REG_FLAG_WO |
  52359                           SOC_REG_FLAG_REG_ARRAY,
  52360         0,
  52361         2,
  52362         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88202_A0r_fields,
  52363         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52364         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52365         -1,
  52366         -1,
  52367     },
  52368 #endif /* chips */
  52369 
  52370 #if defined(BCM_88375_A0)
  52371     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88375_A0r */
  52372         soc_block_list[23],
  52373         soc_genreg,
  52374         4,
  52375         0,
  52376         0x164,
  52377         SOC_REG_FLAG_ARRAY |
  52378                           SOC_REG_FLAG_RO |
  52379                           SOC_REG_FLAG_WO |
  52380                           SOC_REG_FLAG_REG_ARRAY,
  52381         0,
  52382         2,
  52383         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88375_A0r_fields,
  52384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52385         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52386         -1,
  52387         -1,
  52388     },
  52389 #endif /* chips */
  52390 
  52391 #if defined(BCM_88375_B0)
  52392     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88375_B0r */
  52393         soc_block_list[23],
  52394         soc_genreg,
  52395         4,
  52396         0,
  52397         0x164,
  52398         SOC_REG_FLAG_ARRAY |
  52399                           SOC_REG_FLAG_RO |
  52400                           SOC_REG_FLAG_WO |
  52401                           SOC_REG_FLAG_REG_ARRAY,
  52402         0,
  52403         2,
  52404         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88375_B0r_fields,
  52405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52406         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52407         -1,
  52408         -1,
  52409     },
  52410 #endif /* chips */
  52411 
  52412 #if defined(BCM_88470_A0)
  52413     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88470_A0r */
  52414         soc_block_list[23],
  52415         soc_genreg,
  52416         4,
  52417         0,
  52418         0x164,
  52419         SOC_REG_FLAG_ARRAY |
  52420                           SOC_REG_FLAG_RO |
  52421                           SOC_REG_FLAG_WO |
  52422                           SOC_REG_FLAG_REG_ARRAY,
  52423         0,
  52424         2,
  52425         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88470_A0r_fields,
  52426         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52427         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52428         -1,
  52429         -1,
  52430     },
  52431 #endif /* chips */
  52432 
  52433 #if defined(BCM_88470_B0)
  52434     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88470_B0r */
  52435         soc_block_list[23],
  52436         soc_genreg,
  52437         4,
  52438         0,
  52439         0x164,
  52440         SOC_REG_FLAG_ARRAY |
  52441                           SOC_REG_FLAG_RO |
  52442                           SOC_REG_FLAG_WO |
  52443                           SOC_REG_FLAG_REG_ARRAY,
  52444         0,
  52445         2,
  52446         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88470_B0r_fields,
  52447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52448         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52449         -1,
  52450         -1,
  52451     },
  52452 #endif /* chips */
  52453 
  52454 #if defined(BCM_88650_B0)
  52455     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88650_B0r */
  52456         soc_block_list[23],
  52457         soc_genreg,
  52458         4,
  52459         0,
  52460         0x164,
  52461         SOC_REG_FLAG_ARRAY |
  52462                           SOC_REG_FLAG_WO |
  52463                           SOC_REG_FLAG_REG_ARRAY,
  52464         0,
  52465         2,
  52466         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88650_B0r_fields,
  52467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52468         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52469         -1,
  52470         -1,
  52471     },
  52472 #endif /* chips */
  52473 
  52474 #if defined(BCM_88660_A0)
  52475     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88660_A0r */
  52476         soc_block_list[23],
  52477         soc_genreg,
  52478         4,
  52479         0,
  52480         0x164,
  52481         SOC_REG_FLAG_ARRAY |
  52482                           SOC_REG_FLAG_WO |
  52483                           SOC_REG_FLAG_REG_ARRAY,
  52484         0,
  52485         2,
  52486         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88660_A0r_fields,
  52487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52488         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52489         -1,
  52490         -1,
  52491     },
  52492 #endif /* chips */
  52493 
  52494 #if defined(BCM_88675_A0)
  52495     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88675_A0r */
  52496         soc_block_list[23],
  52497         soc_genreg,
  52498         4,
  52499         0,
  52500         0x164,
  52501         SOC_REG_FLAG_ARRAY |
  52502                           SOC_REG_FLAG_RO |
  52503                           SOC_REG_FLAG_WO |
  52504                           SOC_REG_FLAG_REG_ARRAY,
  52505         0,
  52506         2,
  52507         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88675_A0r_fields,
  52508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52509         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52510         -1,
  52511         -1,
  52512     },
  52513 #endif /* chips */
  52514 
  52515 #if defined(BCM_88675_B0)
  52516     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88675_B0r */
  52517         soc_block_list[23],
  52518         soc_genreg,
  52519         4,
  52520         0,
  52521         0x164,
  52522         SOC_REG_FLAG_ARRAY |
  52523                           SOC_REG_FLAG_RO |
  52524                           SOC_REG_FLAG_WO |
  52525                           SOC_REG_FLAG_REG_ARRAY,
  52526         0,
  52527         2,
  52528         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88675_B0r_fields,
  52529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52530         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52531         -1,
  52532         -1,
  52533     },
  52534 #endif /* chips */
  52535 
  52536 #if defined(BCM_88680_A0)
  52537     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88680_A0r */
  52538         soc_block_list[23],
  52539         soc_genreg,
  52540         4,
  52541         0,
  52542         0x164,
  52543         SOC_REG_FLAG_ARRAY |
  52544                           SOC_REG_FLAG_RO |
  52545                           SOC_REG_FLAG_WO |
  52546                           SOC_REG_FLAG_REG_ARRAY,
  52547         0,
  52548         2,
  52549         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88680_A0r_fields,
  52550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52551         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52552         -1,
  52553         -1,
  52554     },
  52555 #endif /* chips */
  52556 
  52557 #if defined(BCM_88690_A0)
  52558     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88690_A0r */
  52559         soc_block_list[23],
  52560         soc_genreg,
  52561         4,
  52562         0,
  52563         0x1ae,
  52564         SOC_REG_FLAG_ARRAY |
  52565                           SOC_REG_FLAG_RO |
  52566                           SOC_REG_FLAG_WO |
  52567                           SOC_REG_FLAG_REG_ARRAY,
  52568         SOC_REG_FLAG_INIT_ON_READ,
  52569         2,
  52570         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88690_A0r_fields,
  52571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52572         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52573         -1,
  52574         -1,
  52575     },
  52576 #endif /* chips */
  52577 
  52578 #if defined(BCM_88690_B0)
  52579     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88690_B0r */
  52580         soc_block_list[23],
  52581         soc_genreg,
  52582         4,
  52583         0,
  52584         0x1ae,
  52585         SOC_REG_FLAG_ARRAY |
  52586                           SOC_REG_FLAG_RO |
  52587                           SOC_REG_FLAG_WO |
  52588                           SOC_REG_FLAG_REG_ARRAY,
  52589         SOC_REG_FLAG_INIT_ON_READ,
  52590         2,
  52591         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88690_B0r_fields,
  52592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52593         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52594         -1,
  52595         -1,
  52596     },
  52597 #endif /* chips */
  52598 
  52599 #if defined(BCM_88790_A0)
  52600     { /* SOC_REG_INT_BRDC_FMAC_KPCS_RX_STATUS_BCM88790_A0r */
  52601         soc_block_list[23],
  52602         soc_genreg,
  52603         4,
  52604         0,
  52605         0x1ae,
  52606         SOC_REG_FLAG_ARRAY |
  52607                           SOC_REG_FLAG_RO |
  52608                           SOC_REG_FLAG_WO |
  52609                           SOC_REG_FLAG_REG_ARRAY,
  52610         0,
  52611         2,
  52612         soc_BRDC_FMAC_KPCS_RX_STATUS_BCM88790_A0r_fields,
  52613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52614         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  52615         -1,
  52616         -1,
  52617     },
  52618 #endif /* chips */
  52619 
  52620 #if defined(BCM_88650_A0)
  52621     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATIONr */
  52622         soc_block_list[23],
  52623         soc_genreg,
  52624         4,
  52625         0,
  52626         0x180,
  52627         SOC_REG_FLAG_ARRAY |
  52628                           SOC_REG_FLAG_WO |
  52629                           SOC_REG_FLAG_REG_ARRAY,
  52630         0,
  52631         4,
  52632         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATIONr_fields,
  52633         SOC_RESET_VAL_DEC(0x000007f2, 0x00000000)
  52634         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52635         -1,
  52636         -1,
  52637     },
  52638 #endif /* chips */
  52639 
  52640 #if defined(BCM_83208_A0)
  52641     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM83208_A0r */
  52642         soc_block_list[23],
  52643         soc_genreg,
  52644         4,
  52645         0,
  52646         0x17a,
  52647         SOC_REG_FLAG_ARRAY |
  52648                           SOC_REG_FLAG_WO |
  52649                           SOC_REG_FLAG_REG_ARRAY,
  52650         0,
  52651         4,
  52652         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM83208_A0r_fields,
  52653         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52654         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52655         -1,
  52656         -1,
  52657     },
  52658 #endif /* chips */
  52659 
  52660 #if defined(BCM_88202_A0)
  52661     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88202_A0r */
  52662         soc_block_list[23],
  52663         soc_genreg,
  52664         4,
  52665         0,
  52666         0x180,
  52667         SOC_REG_FLAG_ARRAY |
  52668                           SOC_REG_FLAG_WO |
  52669                           SOC_REG_FLAG_REG_ARRAY,
  52670         0,
  52671         4,
  52672         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88202_A0r_fields,
  52673         SOC_RESET_VAL_DEC(0x000007f2, 0x00000000)
  52674         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52675         -1,
  52676         -1,
  52677     },
  52678 #endif /* chips */
  52679 
  52680 #if defined(BCM_88375_A0)
  52681     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88375_A0r */
  52682         soc_block_list[23],
  52683         soc_genreg,
  52684         4,
  52685         0,
  52686         0x180,
  52687         SOC_REG_FLAG_ARRAY |
  52688                           SOC_REG_FLAG_WO |
  52689                           SOC_REG_FLAG_REG_ARRAY,
  52690         0,
  52691         4,
  52692         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88375_A0r_fields,
  52693         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52694         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52695         -1,
  52696         -1,
  52697     },
  52698 #endif /* chips */
  52699 
  52700 #if defined(BCM_88375_B0)
  52701     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88375_B0r */
  52702         soc_block_list[23],
  52703         soc_genreg,
  52704         4,
  52705         0,
  52706         0x180,
  52707         SOC_REG_FLAG_ARRAY |
  52708                           SOC_REG_FLAG_WO |
  52709                           SOC_REG_FLAG_REG_ARRAY,
  52710         0,
  52711         4,
  52712         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88375_B0r_fields,
  52713         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52714         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52715         -1,
  52716         -1,
  52717     },
  52718 #endif /* chips */
  52719 
  52720 #if defined(BCM_88470_A0)
  52721     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88470_A0r */
  52722         soc_block_list[23],
  52723         soc_genreg,
  52724         4,
  52725         0,
  52726         0x180,
  52727         SOC_REG_FLAG_ARRAY |
  52728                           SOC_REG_FLAG_WO |
  52729                           SOC_REG_FLAG_REG_ARRAY,
  52730         0,
  52731         4,
  52732         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88470_A0r_fields,
  52733         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52734         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52735         -1,
  52736         -1,
  52737     },
  52738 #endif /* chips */
  52739 
  52740 #if defined(BCM_88470_B0)
  52741     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88470_B0r */
  52742         soc_block_list[23],
  52743         soc_genreg,
  52744         4,
  52745         0,
  52746         0x180,
  52747         SOC_REG_FLAG_ARRAY |
  52748                           SOC_REG_FLAG_WO |
  52749                           SOC_REG_FLAG_REG_ARRAY,
  52750         0,
  52751         4,
  52752         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88470_B0r_fields,
  52753         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52754         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52755         -1,
  52756         -1,
  52757     },
  52758 #endif /* chips */
  52759 
  52760 #if defined(BCM_88650_B0)
  52761     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88650_B0r */
  52762         soc_block_list[23],
  52763         soc_genreg,
  52764         4,
  52765         0,
  52766         0x180,
  52767         SOC_REG_FLAG_ARRAY |
  52768                           SOC_REG_FLAG_WO |
  52769                           SOC_REG_FLAG_REG_ARRAY,
  52770         0,
  52771         4,
  52772         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88650_B0r_fields,
  52773         SOC_RESET_VAL_DEC(0x000007f2, 0x00000000)
  52774         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52775         -1,
  52776         -1,
  52777     },
  52778 #endif /* chips */
  52779 
  52780 #if defined(BCM_88660_A0)
  52781     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88660_A0r */
  52782         soc_block_list[23],
  52783         soc_genreg,
  52784         4,
  52785         0,
  52786         0x180,
  52787         SOC_REG_FLAG_ARRAY |
  52788                           SOC_REG_FLAG_WO |
  52789                           SOC_REG_FLAG_REG_ARRAY,
  52790         0,
  52791         4,
  52792         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88660_A0r_fields,
  52793         SOC_RESET_VAL_DEC(0x000007f2, 0x00000000)
  52794         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  52795         -1,
  52796         -1,
  52797     },
  52798 #endif /* chips */
  52799 
  52800 #if defined(BCM_88675_A0)
  52801     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88675_A0r */
  52802         soc_block_list[23],
  52803         soc_genreg,
  52804         4,
  52805         0,
  52806         0x180,
  52807         SOC_REG_FLAG_ARRAY |
  52808                           SOC_REG_FLAG_WO |
  52809                           SOC_REG_FLAG_REG_ARRAY,
  52810         0,
  52811         4,
  52812         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88675_A0r_fields,
  52813         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52814         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52815         -1,
  52816         -1,
  52817     },
  52818 #endif /* chips */
  52819 
  52820 #if defined(BCM_88675_B0)
  52821     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88675_B0r */
  52822         soc_block_list[23],
  52823         soc_genreg,
  52824         4,
  52825         0,
  52826         0x180,
  52827         SOC_REG_FLAG_ARRAY |
  52828                           SOC_REG_FLAG_WO |
  52829                           SOC_REG_FLAG_REG_ARRAY,
  52830         0,
  52831         4,
  52832         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88675_B0r_fields,
  52833         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52834         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52835         -1,
  52836         -1,
  52837     },
  52838 #endif /* chips */
  52839 
  52840 #if defined(BCM_88680_A0)
  52841     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88680_A0r */
  52842         soc_block_list[23],
  52843         soc_genreg,
  52844         4,
  52845         0,
  52846         0x180,
  52847         SOC_REG_FLAG_ARRAY |
  52848                           SOC_REG_FLAG_WO |
  52849                           SOC_REG_FLAG_REG_ARRAY,
  52850         0,
  52851         4,
  52852         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88680_A0r_fields,
  52853         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52854         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52855         -1,
  52856         -1,
  52857     },
  52858 #endif /* chips */
  52859 
  52860 #if defined(BCM_88690_A0)
  52861     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88690_A0r */
  52862         soc_block_list[23],
  52863         soc_genreg,
  52864         4,
  52865         0,
  52866         0x1b6,
  52867         SOC_REG_FLAG_ARRAY |
  52868                           SOC_REG_FLAG_WO |
  52869                           SOC_REG_FLAG_REG_ARRAY,
  52870         0,
  52871         4,
  52872         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88690_A0r_fields,
  52873         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52874         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52875         -1,
  52876         -1,
  52877     },
  52878 #endif /* chips */
  52879 
  52880 #if defined(BCM_88690_B0)
  52881     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88690_B0r */
  52882         soc_block_list[23],
  52883         soc_genreg,
  52884         4,
  52885         0,
  52886         0x1b6,
  52887         SOC_REG_FLAG_ARRAY |
  52888                           SOC_REG_FLAG_WO |
  52889                           SOC_REG_FLAG_REG_ARRAY,
  52890         0,
  52891         4,
  52892         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88690_B0r_fields,
  52893         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52894         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52895         -1,
  52896         -1,
  52897     },
  52898 #endif /* chips */
  52899 
  52900 #if defined(BCM_88790_A0)
  52901     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88790_A0r */
  52902         soc_block_list[23],
  52903         soc_genreg,
  52904         4,
  52905         0,
  52906         0x1b6,
  52907         SOC_REG_FLAG_ARRAY |
  52908                           SOC_REG_FLAG_WO |
  52909                           SOC_REG_FLAG_REG_ARRAY,
  52910         0,
  52911         4,
  52912         soc_BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION_BCM88790_A0r_fields,
  52913         SOC_RESET_VAL_DEC(0x00000fe2, 0x00000000)
  52914         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  52915         -1,
  52916         -1,
  52917     },
  52918 #endif /* chips */
  52919 
  52920 #if defined(BCM_88650_A0)
  52921     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUSr */
  52922         soc_block_list[23],
  52923         soc_genreg,
  52924         4,
  52925         0,
  52926         0x190,
  52927         SOC_REG_FLAG_ARRAY |
  52928                           SOC_REG_FLAG_WO |
  52929                           SOC_REG_FLAG_REG_ARRAY,
  52930         0,
  52931         1,
  52932         soc_BRDC_FMAC_KPCS_TEST_RX_STATUSr_fields,
  52933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52934         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52935         -1,
  52936         -1,
  52937     },
  52938 #endif /* chips */
  52939 
  52940 #if defined(BCM_83208_A0)
  52941     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM83208_A0r */
  52942         soc_block_list[23],
  52943         soc_genreg,
  52944         4,
  52945         0,
  52946         0x17e,
  52947         SOC_REG_FLAG_ARRAY |
  52948                           SOC_REG_FLAG_RO |
  52949                           SOC_REG_FLAG_WO |
  52950                           SOC_REG_FLAG_REG_ARRAY,
  52951         0,
  52952         1,
  52953         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM83208_A0r_fields,
  52954         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52955         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52956         -1,
  52957         -1,
  52958     },
  52959 #endif /* chips */
  52960 
  52961 #if defined(BCM_88202_A0)
  52962     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88202_A0r */
  52963         soc_block_list[23],
  52964         soc_genreg,
  52965         4,
  52966         0,
  52967         0x190,
  52968         SOC_REG_FLAG_ARRAY |
  52969                           SOC_REG_FLAG_WO |
  52970                           SOC_REG_FLAG_REG_ARRAY,
  52971         0,
  52972         1,
  52973         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88202_A0r_fields,
  52974         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52975         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52976         -1,
  52977         -1,
  52978     },
  52979 #endif /* chips */
  52980 
  52981 #if defined(BCM_88375_A0)
  52982     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88375_A0r */
  52983         soc_block_list[23],
  52984         soc_genreg,
  52985         4,
  52986         0,
  52987         0x190,
  52988         SOC_REG_FLAG_ARRAY |
  52989                           SOC_REG_FLAG_RO |
  52990                           SOC_REG_FLAG_WO |
  52991                           SOC_REG_FLAG_REG_ARRAY,
  52992         0,
  52993         1,
  52994         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88375_A0r_fields,
  52995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  52996         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  52997         -1,
  52998         -1,
  52999     },
  53000 #endif /* chips */
  53001 
  53002 #if defined(BCM_88375_B0)
  53003     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88375_B0r */
  53004         soc_block_list[23],
  53005         soc_genreg,
  53006         4,
  53007         0,
  53008         0x190,
  53009         SOC_REG_FLAG_ARRAY |
  53010                           SOC_REG_FLAG_RO |
  53011                           SOC_REG_FLAG_WO |
  53012                           SOC_REG_FLAG_REG_ARRAY,
  53013         0,
  53014         1,
  53015         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88375_B0r_fields,
  53016         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53017         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53018         -1,
  53019         -1,
  53020     },
  53021 #endif /* chips */
  53022 
  53023 #if defined(BCM_88470_A0)
  53024     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88470_A0r */
  53025         soc_block_list[23],
  53026         soc_genreg,
  53027         4,
  53028         0,
  53029         0x190,
  53030         SOC_REG_FLAG_ARRAY |
  53031                           SOC_REG_FLAG_RO |
  53032                           SOC_REG_FLAG_WO |
  53033                           SOC_REG_FLAG_REG_ARRAY,
  53034         0,
  53035         1,
  53036         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88470_A0r_fields,
  53037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53039         -1,
  53040         -1,
  53041     },
  53042 #endif /* chips */
  53043 
  53044 #if defined(BCM_88470_B0)
  53045     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88470_B0r */
  53046         soc_block_list[23],
  53047         soc_genreg,
  53048         4,
  53049         0,
  53050         0x190,
  53051         SOC_REG_FLAG_ARRAY |
  53052                           SOC_REG_FLAG_RO |
  53053                           SOC_REG_FLAG_WO |
  53054                           SOC_REG_FLAG_REG_ARRAY,
  53055         0,
  53056         1,
  53057         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88470_B0r_fields,
  53058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53060         -1,
  53061         -1,
  53062     },
  53063 #endif /* chips */
  53064 
  53065 #if defined(BCM_88650_B0)
  53066     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88650_B0r */
  53067         soc_block_list[23],
  53068         soc_genreg,
  53069         4,
  53070         0,
  53071         0x190,
  53072         SOC_REG_FLAG_ARRAY |
  53073                           SOC_REG_FLAG_WO |
  53074                           SOC_REG_FLAG_REG_ARRAY,
  53075         0,
  53076         1,
  53077         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88650_B0r_fields,
  53078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53079         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53080         -1,
  53081         -1,
  53082     },
  53083 #endif /* chips */
  53084 
  53085 #if defined(BCM_88660_A0)
  53086     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88660_A0r */
  53087         soc_block_list[23],
  53088         soc_genreg,
  53089         4,
  53090         0,
  53091         0x190,
  53092         SOC_REG_FLAG_ARRAY |
  53093                           SOC_REG_FLAG_WO |
  53094                           SOC_REG_FLAG_REG_ARRAY,
  53095         0,
  53096         1,
  53097         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88660_A0r_fields,
  53098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53099         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53100         -1,
  53101         -1,
  53102     },
  53103 #endif /* chips */
  53104 
  53105 #if defined(BCM_88675_A0)
  53106     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88675_A0r */
  53107         soc_block_list[23],
  53108         soc_genreg,
  53109         4,
  53110         0,
  53111         0x190,
  53112         SOC_REG_FLAG_ARRAY |
  53113                           SOC_REG_FLAG_RO |
  53114                           SOC_REG_FLAG_WO |
  53115                           SOC_REG_FLAG_REG_ARRAY,
  53116         0,
  53117         1,
  53118         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88675_A0r_fields,
  53119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53120         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53121         -1,
  53122         -1,
  53123     },
  53124 #endif /* chips */
  53125 
  53126 #if defined(BCM_88675_B0)
  53127     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88675_B0r */
  53128         soc_block_list[23],
  53129         soc_genreg,
  53130         4,
  53131         0,
  53132         0x190,
  53133         SOC_REG_FLAG_ARRAY |
  53134                           SOC_REG_FLAG_RO |
  53135                           SOC_REG_FLAG_WO |
  53136                           SOC_REG_FLAG_REG_ARRAY,
  53137         0,
  53138         1,
  53139         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88675_B0r_fields,
  53140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53141         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53142         -1,
  53143         -1,
  53144     },
  53145 #endif /* chips */
  53146 
  53147 #if defined(BCM_88680_A0)
  53148     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88680_A0r */
  53149         soc_block_list[23],
  53150         soc_genreg,
  53151         4,
  53152         0,
  53153         0x190,
  53154         SOC_REG_FLAG_ARRAY |
  53155                           SOC_REG_FLAG_RO |
  53156                           SOC_REG_FLAG_WO |
  53157                           SOC_REG_FLAG_REG_ARRAY,
  53158         0,
  53159         1,
  53160         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88680_A0r_fields,
  53161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53162         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53163         -1,
  53164         -1,
  53165     },
  53166 #endif /* chips */
  53167 
  53168 #if defined(BCM_88690_A0)
  53169     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88690_A0r */
  53170         soc_block_list[23],
  53171         soc_genreg,
  53172         4,
  53173         0,
  53174         0x1ba,
  53175         SOC_REG_FLAG_ARRAY |
  53176                           SOC_REG_FLAG_RO |
  53177                           SOC_REG_FLAG_WO |
  53178                           SOC_REG_FLAG_REG_ARRAY,
  53179         SOC_REG_FLAG_INIT_ON_READ,
  53180         1,
  53181         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88690_A0r_fields,
  53182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53183         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53184         -1,
  53185         -1,
  53186     },
  53187 #endif /* chips */
  53188 
  53189 #if defined(BCM_88690_B0)
  53190     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88690_B0r */
  53191         soc_block_list[23],
  53192         soc_genreg,
  53193         4,
  53194         0,
  53195         0x1ba,
  53196         SOC_REG_FLAG_ARRAY |
  53197                           SOC_REG_FLAG_RO |
  53198                           SOC_REG_FLAG_WO |
  53199                           SOC_REG_FLAG_REG_ARRAY,
  53200         SOC_REG_FLAG_INIT_ON_READ,
  53201         1,
  53202         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88690_B0r_fields,
  53203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53204         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53205         -1,
  53206         -1,
  53207     },
  53208 #endif /* chips */
  53209 
  53210 #if defined(BCM_88790_A0)
  53211     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88790_A0r */
  53212         soc_block_list[23],
  53213         soc_genreg,
  53214         4,
  53215         0,
  53216         0x1ba,
  53217         SOC_REG_FLAG_ARRAY |
  53218                           SOC_REG_FLAG_RO |
  53219                           SOC_REG_FLAG_WO |
  53220                           SOC_REG_FLAG_REG_ARRAY,
  53221         0,
  53222         1,
  53223         soc_BRDC_FMAC_KPCS_TEST_RX_STATUS_BCM88790_A0r_fields,
  53224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  53226         -1,
  53227         -1,
  53228     },
  53229 #endif /* chips */
  53230 
  53231 #if defined(BCM_88650_A0)
  53232     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATIONr */
  53233         soc_block_list[23],
  53234         soc_genreg,
  53235         4,
  53236         0,
  53237         0x170,
  53238         SOC_REG_FLAG_ARRAY |
  53239                           SOC_REG_FLAG_WO |
  53240                           SOC_REG_FLAG_REG_ARRAY,
  53241         0,
  53242         7,
  53243         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATIONr_fields,
  53244         SOC_RESET_VAL_DEC(0x00401fc2, 0x00000000)
  53245         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  53246         -1,
  53247         -1,
  53248     },
  53249 #endif /* chips */
  53250 
  53251 #if defined(BCM_83208_A0)
  53252     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM83208_A0r */
  53253         soc_block_list[23],
  53254         soc_genreg,
  53255         4,
  53256         0,
  53257         0x176,
  53258         SOC_REG_FLAG_ARRAY |
  53259                           SOC_REG_FLAG_WO |
  53260                           SOC_REG_FLAG_REG_ARRAY,
  53261         0,
  53262         7,
  53263         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM83208_A0r_fields,
  53264         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53265         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53266         -1,
  53267         -1,
  53268     },
  53269 #endif /* chips */
  53270 
  53271 #if defined(BCM_88202_A0)
  53272     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88202_A0r */
  53273         soc_block_list[23],
  53274         soc_genreg,
  53275         4,
  53276         0,
  53277         0x170,
  53278         SOC_REG_FLAG_ARRAY |
  53279                           SOC_REG_FLAG_WO |
  53280                           SOC_REG_FLAG_REG_ARRAY,
  53281         0,
  53282         7,
  53283         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88202_A0r_fields,
  53284         SOC_RESET_VAL_DEC(0x00401fc2, 0x00000000)
  53285         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  53286         -1,
  53287         -1,
  53288     },
  53289 #endif /* chips */
  53290 
  53291 #if defined(BCM_88375_A0)
  53292     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88375_A0r */
  53293         soc_block_list[23],
  53294         soc_genreg,
  53295         4,
  53296         0,
  53297         0x170,
  53298         SOC_REG_FLAG_ARRAY |
  53299                           SOC_REG_FLAG_WO |
  53300                           SOC_REG_FLAG_REG_ARRAY,
  53301         0,
  53302         7,
  53303         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88375_A0r_fields,
  53304         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53305         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53306         -1,
  53307         -1,
  53308     },
  53309 #endif /* chips */
  53310 
  53311 #if defined(BCM_88375_B0)
  53312     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88375_B0r */
  53313         soc_block_list[23],
  53314         soc_genreg,
  53315         4,
  53316         0,
  53317         0x170,
  53318         SOC_REG_FLAG_ARRAY |
  53319                           SOC_REG_FLAG_WO |
  53320                           SOC_REG_FLAG_REG_ARRAY,
  53321         0,
  53322         7,
  53323         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88375_B0r_fields,
  53324         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53325         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53326         -1,
  53327         -1,
  53328     },
  53329 #endif /* chips */
  53330 
  53331 #if defined(BCM_88470_A0)
  53332     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88470_A0r */
  53333         soc_block_list[23],
  53334         soc_genreg,
  53335         4,
  53336         0,
  53337         0x170,
  53338         SOC_REG_FLAG_ARRAY |
  53339                           SOC_REG_FLAG_WO |
  53340                           SOC_REG_FLAG_REG_ARRAY,
  53341         0,
  53342         7,
  53343         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88470_A0r_fields,
  53344         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53345         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53346         -1,
  53347         -1,
  53348     },
  53349 #endif /* chips */
  53350 
  53351 #if defined(BCM_88470_B0)
  53352     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88470_B0r */
  53353         soc_block_list[23],
  53354         soc_genreg,
  53355         4,
  53356         0,
  53357         0x170,
  53358         SOC_REG_FLAG_ARRAY |
  53359                           SOC_REG_FLAG_WO |
  53360                           SOC_REG_FLAG_REG_ARRAY,
  53361         0,
  53362         7,
  53363         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88470_B0r_fields,
  53364         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53365         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53366         -1,
  53367         -1,
  53368     },
  53369 #endif /* chips */
  53370 
  53371 #if defined(BCM_88650_B0)
  53372     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88650_B0r */
  53373         soc_block_list[23],
  53374         soc_genreg,
  53375         4,
  53376         0,
  53377         0x170,
  53378         SOC_REG_FLAG_ARRAY |
  53379                           SOC_REG_FLAG_WO |
  53380                           SOC_REG_FLAG_REG_ARRAY,
  53381         0,
  53382         7,
  53383         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88650_B0r_fields,
  53384         SOC_RESET_VAL_DEC(0x00401fc2, 0x00000000)
  53385         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  53386         -1,
  53387         -1,
  53388     },
  53389 #endif /* chips */
  53390 
  53391 #if defined(BCM_88660_A0)
  53392     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88660_A0r */
  53393         soc_block_list[23],
  53394         soc_genreg,
  53395         4,
  53396         0,
  53397         0x170,
  53398         SOC_REG_FLAG_ARRAY |
  53399                           SOC_REG_FLAG_WO |
  53400                           SOC_REG_FLAG_REG_ARRAY,
  53401         0,
  53402         7,
  53403         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88660_A0r_fields,
  53404         SOC_RESET_VAL_DEC(0x00401fc2, 0x00000000)
  53405         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  53406         -1,
  53407         -1,
  53408     },
  53409 #endif /* chips */
  53410 
  53411 #if defined(BCM_88675_A0)
  53412     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88675_A0r */
  53413         soc_block_list[23],
  53414         soc_genreg,
  53415         4,
  53416         0,
  53417         0x170,
  53418         SOC_REG_FLAG_ARRAY |
  53419                           SOC_REG_FLAG_WO |
  53420                           SOC_REG_FLAG_REG_ARRAY,
  53421         0,
  53422         7,
  53423         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88675_A0r_fields,
  53424         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53425         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53426         -1,
  53427         -1,
  53428     },
  53429 #endif /* chips */
  53430 
  53431 #if defined(BCM_88675_B0)
  53432     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88675_B0r */
  53433         soc_block_list[23],
  53434         soc_genreg,
  53435         4,
  53436         0,
  53437         0x170,
  53438         SOC_REG_FLAG_ARRAY |
  53439                           SOC_REG_FLAG_WO |
  53440                           SOC_REG_FLAG_REG_ARRAY,
  53441         0,
  53442         7,
  53443         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88675_B0r_fields,
  53444         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53445         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53446         -1,
  53447         -1,
  53448     },
  53449 #endif /* chips */
  53450 
  53451 #if defined(BCM_88680_A0)
  53452     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88680_A0r */
  53453         soc_block_list[23],
  53454         soc_genreg,
  53455         4,
  53456         0,
  53457         0x170,
  53458         SOC_REG_FLAG_ARRAY |
  53459                           SOC_REG_FLAG_WO |
  53460                           SOC_REG_FLAG_REG_ARRAY,
  53461         0,
  53462         7,
  53463         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88680_A0r_fields,
  53464         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53465         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53466         -1,
  53467         -1,
  53468     },
  53469 #endif /* chips */
  53470 
  53471 #if defined(BCM_88690_A0)
  53472     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88690_A0r */
  53473         soc_block_list[23],
  53474         soc_genreg,
  53475         4,
  53476         0,
  53477         0x1b2,
  53478         SOC_REG_FLAG_ARRAY |
  53479                           SOC_REG_FLAG_WO |
  53480                           SOC_REG_FLAG_REG_ARRAY,
  53481         0,
  53482         7,
  53483         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88690_A0r_fields,
  53484         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53485         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53486         -1,
  53487         -1,
  53488     },
  53489 #endif /* chips */
  53490 
  53491 #if defined(BCM_88690_B0)
  53492     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88690_B0r */
  53493         soc_block_list[23],
  53494         soc_genreg,
  53495         4,
  53496         0,
  53497         0x1b2,
  53498         SOC_REG_FLAG_ARRAY |
  53499                           SOC_REG_FLAG_WO |
  53500                           SOC_REG_FLAG_REG_ARRAY,
  53501         0,
  53502         7,
  53503         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88690_B0r_fields,
  53504         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53505         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53506         -1,
  53507         -1,
  53508     },
  53509 #endif /* chips */
  53510 
  53511 #if defined(BCM_88790_A0)
  53512     { /* SOC_REG_INT_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88790_A0r */
  53513         soc_block_list[23],
  53514         soc_genreg,
  53515         4,
  53516         0,
  53517         0x1b2,
  53518         SOC_REG_FLAG_ARRAY |
  53519                           SOC_REG_FLAG_WO |
  53520                           SOC_REG_FLAG_REG_ARRAY,
  53521         0,
  53522         7,
  53523         soc_BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION_BCM88790_A0r_fields,
  53524         SOC_RESET_VAL_DEC(0x00803f82, 0x00000000)
  53525         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  53526         -1,
  53527         -1,
  53528     },
  53529 #endif /* chips */
  53530 
  53531 #if defined(BCM_88650_A0)
  53532     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKETr */
  53533         soc_block_list[23],
  53534         soc_genreg,
  53535         4,
  53536         0,
  53537         0x70,
  53538         SOC_REG_FLAG_ARRAY |
  53539                           SOC_REG_FLAG_WO |
  53540                           SOC_REG_FLAG_REG_ARRAY,
  53541         0,
  53542         2,
  53543         soc_BRDC_FMAC_LEAKY_BUCKETr_fields,
  53544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53545         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53546         -1,
  53547         -1,
  53548     },
  53549 #endif /* chips */
  53550 
  53551 #if defined(BCM_83208_A0)
  53552     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM83208_A0r */
  53553         soc_block_list[23],
  53554         soc_genreg,
  53555         4,
  53556         0,
  53557         0x10c,
  53558         SOC_REG_FLAG_ARRAY |
  53559                           SOC_REG_FLAG_RO |
  53560                           SOC_REG_FLAG_WO |
  53561                           SOC_REG_FLAG_REG_ARRAY,
  53562         0,
  53563         2,
  53564         soc_BRDC_FMAC_LEAKY_BUCKET_BCM83208_A0r_fields,
  53565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53566         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53567         -1,
  53568         -1,
  53569     },
  53570 #endif /* chips */
  53571 
  53572 #if defined(BCM_88202_A0)
  53573     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88202_A0r */
  53574         soc_block_list[23],
  53575         soc_genreg,
  53576         4,
  53577         0,
  53578         0x70,
  53579         SOC_REG_FLAG_ARRAY |
  53580                           SOC_REG_FLAG_WO |
  53581                           SOC_REG_FLAG_REG_ARRAY,
  53582         0,
  53583         2,
  53584         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88202_A0r_fields,
  53585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53586         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53587         -1,
  53588         -1,
  53589     },
  53590 #endif /* chips */
  53591 
  53592 #if defined(BCM_88375_A0)
  53593     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88375_A0r */
  53594         soc_block_list[23],
  53595         soc_genreg,
  53596         4,
  53597         0,
  53598         0x10c,
  53599         SOC_REG_FLAG_ARRAY |
  53600                           SOC_REG_FLAG_RO |
  53601                           SOC_REG_FLAG_WO |
  53602                           SOC_REG_FLAG_REG_ARRAY,
  53603         0,
  53604         2,
  53605         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88375_A0r_fields,
  53606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53607         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53608         -1,
  53609         -1,
  53610     },
  53611 #endif /* chips */
  53612 
  53613 #if defined(BCM_88375_B0)
  53614     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88375_B0r */
  53615         soc_block_list[23],
  53616         soc_genreg,
  53617         4,
  53618         0,
  53619         0x10c,
  53620         SOC_REG_FLAG_ARRAY |
  53621                           SOC_REG_FLAG_RO |
  53622                           SOC_REG_FLAG_WO |
  53623                           SOC_REG_FLAG_REG_ARRAY,
  53624         0,
  53625         2,
  53626         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88375_B0r_fields,
  53627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53628         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53629         -1,
  53630         -1,
  53631     },
  53632 #endif /* chips */
  53633 
  53634 #if defined(BCM_88470_A0)
  53635     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88470_A0r */
  53636         soc_block_list[23],
  53637         soc_genreg,
  53638         4,
  53639         0,
  53640         0x10c,
  53641         SOC_REG_FLAG_ARRAY |
  53642                           SOC_REG_FLAG_RO |
  53643                           SOC_REG_FLAG_WO |
  53644                           SOC_REG_FLAG_REG_ARRAY,
  53645         0,
  53646         2,
  53647         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88470_A0r_fields,
  53648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53649         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53650         -1,
  53651         -1,
  53652     },
  53653 #endif /* chips */
  53654 
  53655 #if defined(BCM_88470_B0)
  53656     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88470_B0r */
  53657         soc_block_list[23],
  53658         soc_genreg,
  53659         4,
  53660         0,
  53661         0x10c,
  53662         SOC_REG_FLAG_ARRAY |
  53663                           SOC_REG_FLAG_RO |
  53664                           SOC_REG_FLAG_WO |
  53665                           SOC_REG_FLAG_REG_ARRAY,
  53666         0,
  53667         2,
  53668         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88470_B0r_fields,
  53669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53670         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53671         -1,
  53672         -1,
  53673     },
  53674 #endif /* chips */
  53675 
  53676 #if defined(BCM_88650_B0)
  53677     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88650_B0r */
  53678         soc_block_list[23],
  53679         soc_genreg,
  53680         4,
  53681         0,
  53682         0x70,
  53683         SOC_REG_FLAG_ARRAY |
  53684                           SOC_REG_FLAG_WO |
  53685                           SOC_REG_FLAG_REG_ARRAY,
  53686         0,
  53687         2,
  53688         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88650_B0r_fields,
  53689         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53690         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53691         -1,
  53692         -1,
  53693     },
  53694 #endif /* chips */
  53695 
  53696 #if defined(BCM_88660_A0)
  53697     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88660_A0r */
  53698         soc_block_list[23],
  53699         soc_genreg,
  53700         4,
  53701         0,
  53702         0x70,
  53703         SOC_REG_FLAG_ARRAY |
  53704                           SOC_REG_FLAG_WO |
  53705                           SOC_REG_FLAG_REG_ARRAY,
  53706         0,
  53707         2,
  53708         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88660_A0r_fields,
  53709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53710         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53711         -1,
  53712         -1,
  53713     },
  53714 #endif /* chips */
  53715 
  53716 #if defined(BCM_88675_A0)
  53717     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88675_A0r */
  53718         soc_block_list[23],
  53719         soc_genreg,
  53720         4,
  53721         0,
  53722         0x10c,
  53723         SOC_REG_FLAG_ARRAY |
  53724                           SOC_REG_FLAG_RO |
  53725                           SOC_REG_FLAG_WO |
  53726                           SOC_REG_FLAG_REG_ARRAY,
  53727         0,
  53728         2,
  53729         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88675_A0r_fields,
  53730         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53731         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53732         -1,
  53733         -1,
  53734     },
  53735 #endif /* chips */
  53736 
  53737 #if defined(BCM_88675_B0)
  53738     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88675_B0r */
  53739         soc_block_list[23],
  53740         soc_genreg,
  53741         4,
  53742         0,
  53743         0x10c,
  53744         SOC_REG_FLAG_ARRAY |
  53745                           SOC_REG_FLAG_RO |
  53746                           SOC_REG_FLAG_WO |
  53747                           SOC_REG_FLAG_REG_ARRAY,
  53748         0,
  53749         2,
  53750         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88675_B0r_fields,
  53751         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53752         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53753         -1,
  53754         -1,
  53755     },
  53756 #endif /* chips */
  53757 
  53758 #if defined(BCM_88680_A0)
  53759     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88680_A0r */
  53760         soc_block_list[23],
  53761         soc_genreg,
  53762         4,
  53763         0,
  53764         0x10c,
  53765         SOC_REG_FLAG_ARRAY |
  53766                           SOC_REG_FLAG_RO |
  53767                           SOC_REG_FLAG_WO |
  53768                           SOC_REG_FLAG_REG_ARRAY,
  53769         0,
  53770         2,
  53771         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88680_A0r_fields,
  53772         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53773         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53774         -1,
  53775         -1,
  53776     },
  53777 #endif /* chips */
  53778 
  53779 #if defined(BCM_88690_A0)
  53780     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88690_A0r */
  53781         soc_block_list[23],
  53782         soc_genreg,
  53783         4,
  53784         0,
  53785         0x12c,
  53786         SOC_REG_FLAG_ARRAY |
  53787                           SOC_REG_FLAG_RO |
  53788                           SOC_REG_FLAG_WO |
  53789                           SOC_REG_FLAG_REG_ARRAY,
  53790         0,
  53791         2,
  53792         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88690_A0r_fields,
  53793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53794         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53795         -1,
  53796         -1,
  53797     },
  53798 #endif /* chips */
  53799 
  53800 #if defined(BCM_88690_B0)
  53801     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88690_B0r */
  53802         soc_block_list[23],
  53803         soc_genreg,
  53804         4,
  53805         0,
  53806         0x12c,
  53807         SOC_REG_FLAG_ARRAY |
  53808                           SOC_REG_FLAG_RO |
  53809                           SOC_REG_FLAG_WO |
  53810                           SOC_REG_FLAG_REG_ARRAY,
  53811         0,
  53812         2,
  53813         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88690_B0r_fields,
  53814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53815         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53816         -1,
  53817         -1,
  53818     },
  53819 #endif /* chips */
  53820 
  53821 #if defined(BCM_88790_A0)
  53822     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_BCM88790_A0r */
  53823         soc_block_list[23],
  53824         soc_genreg,
  53825         4,
  53826         0,
  53827         0x12c,
  53828         SOC_REG_FLAG_ARRAY |
  53829                           SOC_REG_FLAG_RO |
  53830                           SOC_REG_FLAG_WO |
  53831                           SOC_REG_FLAG_REG_ARRAY,
  53832         0,
  53833         2,
  53834         soc_BRDC_FMAC_LEAKY_BUCKET_BCM88790_A0r_fields,
  53835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  53836         SOC_RESET_MASK_DEC(0x000fff3f, 0x00000000)
  53837         -1,
  53838         -1,
  53839     },
  53840 #endif /* chips */
  53841 
  53842 #if defined(BCM_88650_A0)
  53843     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTERr */
  53844         soc_block_list[23],
  53845         soc_genreg,
  53846         1,
  53847         0,
  53848         0x61,
  53849         SOC_REG_FLAG_WO,
  53850         0,
  53851         6,
  53852         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTERr_fields,
  53853         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53854         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53855         -1,
  53856         -1,
  53857     },
  53858 #endif /* chips */
  53859 
  53860 #if defined(BCM_83208_A0)
  53861     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM83208_A0r */
  53862         soc_block_list[23],
  53863         soc_genreg,
  53864         1,
  53865         0,
  53866         0x104,
  53867         SOC_REG_FLAG_WO,
  53868         0,
  53869         6,
  53870         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM83208_A0r_fields,
  53871         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53872         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53873         -1,
  53874         -1,
  53875     },
  53876 #endif /* chips */
  53877 
  53878 #if defined(BCM_88202_A0)
  53879     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88202_A0r */
  53880         soc_block_list[23],
  53881         soc_genreg,
  53882         1,
  53883         0,
  53884         0x61,
  53885         SOC_REG_FLAG_WO,
  53886         0,
  53887         6,
  53888         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88202_A0r_fields,
  53889         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53890         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53891         -1,
  53892         -1,
  53893     },
  53894 #endif /* chips */
  53895 
  53896 #if defined(BCM_88375_A0)
  53897     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88375_A0r */
  53898         soc_block_list[23],
  53899         soc_genreg,
  53900         1,
  53901         0,
  53902         0x104,
  53903         SOC_REG_FLAG_WO,
  53904         0,
  53905         6,
  53906         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88375_A0r_fields,
  53907         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53908         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53909         -1,
  53910         -1,
  53911     },
  53912 #endif /* chips */
  53913 
  53914 #if defined(BCM_88375_B0)
  53915     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88375_B0r */
  53916         soc_block_list[23],
  53917         soc_genreg,
  53918         1,
  53919         0,
  53920         0x104,
  53921         SOC_REG_FLAG_WO,
  53922         0,
  53923         6,
  53924         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88375_B0r_fields,
  53925         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53926         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53927         -1,
  53928         -1,
  53929     },
  53930 #endif /* chips */
  53931 
  53932 #if defined(BCM_88470_A0)
  53933     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88470_A0r */
  53934         soc_block_list[23],
  53935         soc_genreg,
  53936         1,
  53937         0,
  53938         0x104,
  53939         SOC_REG_FLAG_WO,
  53940         0,
  53941         6,
  53942         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88470_A0r_fields,
  53943         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53944         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53945         -1,
  53946         -1,
  53947     },
  53948 #endif /* chips */
  53949 
  53950 #if defined(BCM_88470_B0)
  53951     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88470_B0r */
  53952         soc_block_list[23],
  53953         soc_genreg,
  53954         1,
  53955         0,
  53956         0x104,
  53957         SOC_REG_FLAG_WO,
  53958         0,
  53959         6,
  53960         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88470_B0r_fields,
  53961         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53962         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53963         -1,
  53964         -1,
  53965     },
  53966 #endif /* chips */
  53967 
  53968 #if defined(BCM_88650_B0)
  53969     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88650_B0r */
  53970         soc_block_list[23],
  53971         soc_genreg,
  53972         1,
  53973         0,
  53974         0x61,
  53975         SOC_REG_FLAG_WO,
  53976         0,
  53977         6,
  53978         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88650_B0r_fields,
  53979         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53980         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53981         -1,
  53982         -1,
  53983     },
  53984 #endif /* chips */
  53985 
  53986 #if defined(BCM_88660_A0)
  53987     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88660_A0r */
  53988         soc_block_list[23],
  53989         soc_genreg,
  53990         1,
  53991         0,
  53992         0x61,
  53993         SOC_REG_FLAG_WO,
  53994         0,
  53995         6,
  53996         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88660_A0r_fields,
  53997         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  53998         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  53999         -1,
  54000         -1,
  54001     },
  54002 #endif /* chips */
  54003 
  54004 #if defined(BCM_88675_A0)
  54005     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88675_A0r */
  54006         soc_block_list[23],
  54007         soc_genreg,
  54008         1,
  54009         0,
  54010         0x104,
  54011         SOC_REG_FLAG_WO,
  54012         0,
  54013         6,
  54014         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88675_A0r_fields,
  54015         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  54016         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  54017         -1,
  54018         -1,
  54019     },
  54020 #endif /* chips */
  54021 
  54022 #if defined(BCM_88675_B0)
  54023     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88675_B0r */
  54024         soc_block_list[23],
  54025         soc_genreg,
  54026         1,
  54027         0,
  54028         0x104,
  54029         SOC_REG_FLAG_WO,
  54030         0,
  54031         6,
  54032         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88675_B0r_fields,
  54033         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  54034         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  54035         -1,
  54036         -1,
  54037     },
  54038 #endif /* chips */
  54039 
  54040 #if defined(BCM_88680_A0)
  54041     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88680_A0r */
  54042         soc_block_list[23],
  54043         soc_genreg,
  54044         1,
  54045         0,
  54046         0x104,
  54047         SOC_REG_FLAG_WO,
  54048         0,
  54049         6,
  54050         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88680_A0r_fields,
  54051         SOC_RESET_VAL_DEC(0x20010200, 0x00000000)
  54052         SOC_RESET_MASK_DEC(0x7003f3ff, 0x00000000)
  54053         -1,
  54054         -1,
  54055     },
  54056 #endif /* chips */
  54057 
  54058 #if defined(BCM_88690_A0)
  54059     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88690_A0r */
  54060         soc_block_list[23],
  54061         soc_genreg,
  54062         4,
  54063         0,
  54064         0x121,
  54065         SOC_REG_FLAG_ARRAY |
  54066                           SOC_REG_FLAG_WO |
  54067                           SOC_REG_FLAG_REG_ARRAY,
  54068         0,
  54069         7,
  54070         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88690_A0r_fields,
  54071         SOC_RESET_VAL_DEC(0x000a4200, 0x00000000)
  54072         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54073         -1,
  54074         -1,
  54075     },
  54076 #endif /* chips */
  54077 
  54078 #if defined(BCM_88690_B0)
  54079     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88690_B0r */
  54080         soc_block_list[23],
  54081         soc_genreg,
  54082         4,
  54083         0,
  54084         0x121,
  54085         SOC_REG_FLAG_ARRAY |
  54086                           SOC_REG_FLAG_WO |
  54087                           SOC_REG_FLAG_REG_ARRAY,
  54088         0,
  54089         7,
  54090         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88690_B0r_fields,
  54091         SOC_RESET_VAL_DEC(0x000a4200, 0x00000000)
  54092         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54093         -1,
  54094         -1,
  54095     },
  54096 #endif /* chips */
  54097 
  54098 #if defined(BCM_88790_A0)
  54099     { /* SOC_REG_INT_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88790_A0r */
  54100         soc_block_list[23],
  54101         soc_genreg,
  54102         4,
  54103         0,
  54104         0x121,
  54105         SOC_REG_FLAG_ARRAY |
  54106                           SOC_REG_FLAG_WO |
  54107                           SOC_REG_FLAG_REG_ARRAY,
  54108         0,
  54109         7,
  54110         soc_BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER_BCM88790_A0r_fields,
  54111         SOC_RESET_VAL_DEC(0x000a4200, 0x00000000)
  54112         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54113         -1,
  54114         -1,
  54115     },
  54116 #endif /* chips */
  54117 
  54118 #if defined(BCM_88650_A0)
  54119     { /* SOC_REG_INT_BRDC_FMAC_LFEC_CONFIGURATIONr */
  54120         soc_block_list[23],
  54121         soc_genreg,
  54122         4,
  54123         0,
  54124         0xe0,
  54125         SOC_REG_FLAG_ARRAY |
  54126                           SOC_REG_FLAG_WO |
  54127                           SOC_REG_FLAG_REG_ARRAY,
  54128         0,
  54129         10,
  54130         soc_BRDC_FMAC_LFEC_CONFIGURATIONr_fields,
  54131         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  54132         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54133         -1,
  54134         -1,
  54135     },
  54136 #endif /* chips */
  54137 
  54138 #if defined(BCM_88202_A0)
  54139     { /* SOC_REG_INT_BRDC_FMAC_LFEC_CONFIGURATION_BCM88202_A0r */
  54140         soc_block_list[23],
  54141         soc_genreg,
  54142         4,
  54143         0,
  54144         0xe0,
  54145         SOC_REG_FLAG_ARRAY |
  54146                           SOC_REG_FLAG_WO |
  54147                           SOC_REG_FLAG_REG_ARRAY,
  54148         0,
  54149         10,
  54150         soc_BRDC_FMAC_LFEC_CONFIGURATION_BCM88202_A0r_fields,
  54151         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  54152         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54153         -1,
  54154         -1,
  54155     },
  54156 #endif /* chips */
  54157 
  54158 #if defined(BCM_88470_A0)
  54159     { /* SOC_REG_INT_BRDC_FMAC_LFEC_CONFIGURATION_BCM88470_A0r */
  54160         soc_block_list[23],
  54161         soc_genreg,
  54162         4,
  54163         0,
  54164         0x139,
  54165         SOC_REG_FLAG_ARRAY |
  54166                           SOC_REG_FLAG_WO |
  54167                           SOC_REG_FLAG_REG_ARRAY,
  54168         0,
  54169         10,
  54170         soc_BRDC_FMAC_LFEC_CONFIGURATION_BCM88470_A0r_fields,
  54171         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  54172         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54173         -1,
  54174         -1,
  54175     },
  54176 #endif /* chips */
  54177 
  54178 #if defined(BCM_88470_B0)
  54179     { /* SOC_REG_INT_BRDC_FMAC_LFEC_CONFIGURATION_BCM88470_B0r */
  54180         soc_block_list[23],
  54181         soc_genreg,
  54182         4,
  54183         0,
  54184         0x139,
  54185         SOC_REG_FLAG_ARRAY |
  54186                           SOC_REG_FLAG_WO |
  54187                           SOC_REG_FLAG_REG_ARRAY,
  54188         0,
  54189         10,
  54190         soc_BRDC_FMAC_LFEC_CONFIGURATION_BCM88470_B0r_fields,
  54191         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  54192         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54193         -1,
  54194         -1,
  54195     },
  54196 #endif /* chips */
  54197 
  54198 #if defined(BCM_88650_B0)
  54199     { /* SOC_REG_INT_BRDC_FMAC_LFEC_CONFIGURATION_BCM88650_B0r */
  54200         soc_block_list[23],
  54201         soc_genreg,
  54202         4,
  54203         0,
  54204         0xe0,
  54205         SOC_REG_FLAG_ARRAY |
  54206                           SOC_REG_FLAG_WO |
  54207                           SOC_REG_FLAG_REG_ARRAY,
  54208         0,
  54209         10,
  54210         soc_BRDC_FMAC_LFEC_CONFIGURATION_BCM88650_B0r_fields,
  54211         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  54212         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54213         -1,
  54214         -1,
  54215     },
  54216 #endif /* chips */
  54217 
  54218 #if defined(BCM_88660_A0)
  54219     { /* SOC_REG_INT_BRDC_FMAC_LFEC_CONFIGURATION_BCM88660_A0r */
  54220         soc_block_list[23],
  54221         soc_genreg,
  54222         4,
  54223         0,
  54224         0xe0,
  54225         SOC_REG_FLAG_ARRAY |
  54226                           SOC_REG_FLAG_WO |
  54227                           SOC_REG_FLAG_REG_ARRAY,
  54228         0,
  54229         10,
  54230         soc_BRDC_FMAC_LFEC_CONFIGURATION_BCM88660_A0r_fields,
  54231         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  54232         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  54233         -1,
  54234         -1,
  54235     },
  54236 #endif /* chips */
  54237 
  54238 #if defined(BCM_88650_A0)
  54239     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr */
  54240         soc_block_list[23],
  54241         soc_genreg,
  54242         1,
  54243         0,
  54244         0x64,
  54245         SOC_REG_FLAG_WO,
  54246         0,
  54247         4,
  54248         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTERr_fields,
  54249         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54250         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54251         -1,
  54252         -1,
  54253     },
  54254 #endif /* chips */
  54255 
  54256 #if defined(BCM_83208_A0)
  54257     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM83208_A0r */
  54258         soc_block_list[23],
  54259         soc_genreg,
  54260         1,
  54261         0,
  54262         0x107,
  54263         SOC_REG_FLAG_WO,
  54264         0,
  54265         4,
  54266         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM83208_A0r_fields,
  54267         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54268         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54269         -1,
  54270         -1,
  54271     },
  54272 #endif /* chips */
  54273 
  54274 #if defined(BCM_88202_A0)
  54275     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88202_A0r */
  54276         soc_block_list[23],
  54277         soc_genreg,
  54278         1,
  54279         0,
  54280         0x64,
  54281         SOC_REG_FLAG_WO,
  54282         0,
  54283         4,
  54284         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88202_A0r_fields,
  54285         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54286         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54287         -1,
  54288         -1,
  54289     },
  54290 #endif /* chips */
  54291 
  54292 #if defined(BCM_88375_A0)
  54293     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88375_A0r */
  54294         soc_block_list[23],
  54295         soc_genreg,
  54296         1,
  54297         0,
  54298         0x107,
  54299         SOC_REG_FLAG_WO,
  54300         0,
  54301         4,
  54302         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88375_A0r_fields,
  54303         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54304         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54305         -1,
  54306         -1,
  54307     },
  54308 #endif /* chips */
  54309 
  54310 #if defined(BCM_88375_B0)
  54311     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88375_B0r */
  54312         soc_block_list[23],
  54313         soc_genreg,
  54314         1,
  54315         0,
  54316         0x107,
  54317         SOC_REG_FLAG_WO,
  54318         0,
  54319         4,
  54320         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88375_B0r_fields,
  54321         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54322         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54323         -1,
  54324         -1,
  54325     },
  54326 #endif /* chips */
  54327 
  54328 #if defined(BCM_88470_A0)
  54329     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88470_A0r */
  54330         soc_block_list[23],
  54331         soc_genreg,
  54332         1,
  54333         0,
  54334         0x107,
  54335         SOC_REG_FLAG_WO,
  54336         0,
  54337         4,
  54338         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88470_A0r_fields,
  54339         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54340         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54341         -1,
  54342         -1,
  54343     },
  54344 #endif /* chips */
  54345 
  54346 #if defined(BCM_88470_B0)
  54347     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88470_B0r */
  54348         soc_block_list[23],
  54349         soc_genreg,
  54350         1,
  54351         0,
  54352         0x107,
  54353         SOC_REG_FLAG_WO,
  54354         0,
  54355         4,
  54356         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88470_B0r_fields,
  54357         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54358         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54359         -1,
  54360         -1,
  54361     },
  54362 #endif /* chips */
  54363 
  54364 #if defined(BCM_88650_B0)
  54365     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88650_B0r */
  54366         soc_block_list[23],
  54367         soc_genreg,
  54368         1,
  54369         0,
  54370         0x64,
  54371         SOC_REG_FLAG_WO,
  54372         0,
  54373         4,
  54374         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88650_B0r_fields,
  54375         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54376         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54377         -1,
  54378         -1,
  54379     },
  54380 #endif /* chips */
  54381 
  54382 #if defined(BCM_88660_A0)
  54383     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88660_A0r */
  54384         soc_block_list[23],
  54385         soc_genreg,
  54386         1,
  54387         0,
  54388         0x64,
  54389         SOC_REG_FLAG_WO,
  54390         0,
  54391         4,
  54392         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88660_A0r_fields,
  54393         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54394         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54395         -1,
  54396         -1,
  54397     },
  54398 #endif /* chips */
  54399 
  54400 #if defined(BCM_88675_A0)
  54401     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88675_A0r */
  54402         soc_block_list[23],
  54403         soc_genreg,
  54404         1,
  54405         0,
  54406         0x107,
  54407         SOC_REG_FLAG_WO,
  54408         0,
  54409         4,
  54410         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88675_A0r_fields,
  54411         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54412         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54413         -1,
  54414         -1,
  54415     },
  54416 #endif /* chips */
  54417 
  54418 #if defined(BCM_88675_B0)
  54419     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88675_B0r */
  54420         soc_block_list[23],
  54421         soc_genreg,
  54422         1,
  54423         0,
  54424         0x107,
  54425         SOC_REG_FLAG_WO,
  54426         0,
  54427         4,
  54428         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88675_B0r_fields,
  54429         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54430         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54431         -1,
  54432         -1,
  54433     },
  54434 #endif /* chips */
  54435 
  54436 #if defined(BCM_88680_A0)
  54437     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88680_A0r */
  54438         soc_block_list[23],
  54439         soc_genreg,
  54440         1,
  54441         0,
  54442         0x107,
  54443         SOC_REG_FLAG_WO,
  54444         0,
  54445         4,
  54446         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88680_A0r_fields,
  54447         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54448         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54449         -1,
  54450         -1,
  54451     },
  54452 #endif /* chips */
  54453 
  54454 #if defined(BCM_88690_A0)
  54455     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88690_A0r */
  54456         soc_block_list[23],
  54457         soc_genreg,
  54458         1,
  54459         0,
  54460         0x127,
  54461         SOC_REG_FLAG_WO,
  54462         0,
  54463         4,
  54464         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88690_A0r_fields,
  54465         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54466         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54467         -1,
  54468         -1,
  54469     },
  54470 #endif /* chips */
  54471 
  54472 #if defined(BCM_88690_B0)
  54473     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88690_B0r */
  54474         soc_block_list[23],
  54475         soc_genreg,
  54476         1,
  54477         0,
  54478         0x127,
  54479         SOC_REG_FLAG_WO,
  54480         0,
  54481         4,
  54482         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88690_B0r_fields,
  54483         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54484         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54485         -1,
  54486         -1,
  54487     },
  54488 #endif /* chips */
  54489 
  54490 #if defined(BCM_88790_A0)
  54491     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88790_A0r */
  54492         soc_block_list[23],
  54493         soc_genreg,
  54494         1,
  54495         0,
  54496         0x127,
  54497         SOC_REG_FLAG_WO,
  54498         0,
  54499         4,
  54500         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER_BCM88790_A0r_fields,
  54501         SOC_RESET_VAL_DEC(0x000c9fff, 0x00000000)
  54502         SOC_RESET_MASK_DEC(0x7fffffff, 0x00000000)
  54503         -1,
  54504         -1,
  54505     },
  54506 #endif /* chips */
  54507 
  54508 #if defined(BCM_88650_A0)
  54509     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr */
  54510         soc_block_list[23],
  54511         soc_genreg,
  54512         1,
  54513         0,
  54514         0x31,
  54515         SOC_REG_FLAG_WO,
  54516         0,
  54517         2,
  54518         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTERr_fields,
  54519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54520         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54521         -1,
  54522         -1,
  54523     },
  54524 #endif /* chips */
  54525 
  54526 #if defined(BCM_83208_A0)
  54527     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM83208_A0r */
  54528         soc_block_list[23],
  54529         soc_genreg,
  54530         1,
  54531         0,
  54532         0x101,
  54533         SOC_REG_FLAG_WO,
  54534         0,
  54535         2,
  54536         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM83208_A0r_fields,
  54537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54538         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54539         -1,
  54540         -1,
  54541     },
  54542 #endif /* chips */
  54543 
  54544 #if defined(BCM_88202_A0)
  54545     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88202_A0r */
  54546         soc_block_list[23],
  54547         soc_genreg,
  54548         1,
  54549         0,
  54550         0x31,
  54551         SOC_REG_FLAG_WO,
  54552         0,
  54553         2,
  54554         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88202_A0r_fields,
  54555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54556         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54557         -1,
  54558         -1,
  54559     },
  54560 #endif /* chips */
  54561 
  54562 #if defined(BCM_88375_A0)
  54563     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88375_A0r */
  54564         soc_block_list[23],
  54565         soc_genreg,
  54566         1,
  54567         0,
  54568         0x101,
  54569         SOC_REG_FLAG_WO,
  54570         0,
  54571         2,
  54572         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88375_A0r_fields,
  54573         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54574         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54575         -1,
  54576         -1,
  54577     },
  54578 #endif /* chips */
  54579 
  54580 #if defined(BCM_88375_B0)
  54581     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88375_B0r */
  54582         soc_block_list[23],
  54583         soc_genreg,
  54584         1,
  54585         0,
  54586         0x101,
  54587         SOC_REG_FLAG_WO,
  54588         0,
  54589         2,
  54590         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88375_B0r_fields,
  54591         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54592         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54593         -1,
  54594         -1,
  54595     },
  54596 #endif /* chips */
  54597 
  54598 #if defined(BCM_88470_A0)
  54599     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88470_A0r */
  54600         soc_block_list[23],
  54601         soc_genreg,
  54602         1,
  54603         0,
  54604         0x101,
  54605         SOC_REG_FLAG_WO,
  54606         0,
  54607         2,
  54608         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88470_A0r_fields,
  54609         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54610         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54611         -1,
  54612         -1,
  54613     },
  54614 #endif /* chips */
  54615 
  54616 #if defined(BCM_88470_B0)
  54617     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88470_B0r */
  54618         soc_block_list[23],
  54619         soc_genreg,
  54620         1,
  54621         0,
  54622         0x101,
  54623         SOC_REG_FLAG_WO,
  54624         0,
  54625         2,
  54626         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88470_B0r_fields,
  54627         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54628         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54629         -1,
  54630         -1,
  54631     },
  54632 #endif /* chips */
  54633 
  54634 #if defined(BCM_88650_B0)
  54635     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88650_B0r */
  54636         soc_block_list[23],
  54637         soc_genreg,
  54638         1,
  54639         0,
  54640         0x31,
  54641         SOC_REG_FLAG_WO,
  54642         0,
  54643         2,
  54644         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88650_B0r_fields,
  54645         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54646         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54647         -1,
  54648         -1,
  54649     },
  54650 #endif /* chips */
  54651 
  54652 #if defined(BCM_88660_A0)
  54653     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88660_A0r */
  54654         soc_block_list[23],
  54655         soc_genreg,
  54656         1,
  54657         0,
  54658         0x31,
  54659         SOC_REG_FLAG_WO,
  54660         0,
  54661         2,
  54662         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88660_A0r_fields,
  54663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54664         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54665         -1,
  54666         -1,
  54667     },
  54668 #endif /* chips */
  54669 
  54670 #if defined(BCM_88675_A0)
  54671     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88675_A0r */
  54672         soc_block_list[23],
  54673         soc_genreg,
  54674         1,
  54675         0,
  54676         0x101,
  54677         SOC_REG_FLAG_WO,
  54678         0,
  54679         2,
  54680         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88675_A0r_fields,
  54681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54682         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54683         -1,
  54684         -1,
  54685     },
  54686 #endif /* chips */
  54687 
  54688 #if defined(BCM_88675_B0)
  54689     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88675_B0r */
  54690         soc_block_list[23],
  54691         soc_genreg,
  54692         1,
  54693         0,
  54694         0x101,
  54695         SOC_REG_FLAG_WO,
  54696         0,
  54697         2,
  54698         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88675_B0r_fields,
  54699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54700         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54701         -1,
  54702         -1,
  54703     },
  54704 #endif /* chips */
  54705 
  54706 #if defined(BCM_88680_A0)
  54707     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88680_A0r */
  54708         soc_block_list[23],
  54709         soc_genreg,
  54710         1,
  54711         0,
  54712         0x101,
  54713         SOC_REG_FLAG_WO,
  54714         0,
  54715         2,
  54716         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88680_A0r_fields,
  54717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54718         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54719         -1,
  54720         -1,
  54721     },
  54722 #endif /* chips */
  54723 
  54724 #if defined(BCM_88690_A0)
  54725     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88690_A0r */
  54726         soc_block_list[23],
  54727         soc_genreg,
  54728         1,
  54729         0,
  54730         0x119,
  54731         SOC_REG_FLAG_WO,
  54732         0,
  54733         2,
  54734         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88690_A0r_fields,
  54735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54736         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54737         -1,
  54738         -1,
  54739     },
  54740 #endif /* chips */
  54741 
  54742 #if defined(BCM_88690_B0)
  54743     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88690_B0r */
  54744         soc_block_list[23],
  54745         soc_genreg,
  54746         1,
  54747         0,
  54748         0x119,
  54749         SOC_REG_FLAG_WO,
  54750         0,
  54751         2,
  54752         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88690_B0r_fields,
  54753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54754         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54755         -1,
  54756         -1,
  54757     },
  54758 #endif /* chips */
  54759 
  54760 #if defined(BCM_88790_A0)
  54761     { /* SOC_REG_INT_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88790_A0r */
  54762         soc_block_list[23],
  54763         soc_genreg,
  54764         1,
  54765         0,
  54766         0x119,
  54767         SOC_REG_FLAG_WO,
  54768         0,
  54769         2,
  54770         soc_BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER_BCM88790_A0r_fields,
  54771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54772         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54773         -1,
  54774         -1,
  54775     },
  54776 #endif /* chips */
  54777 
  54778 #if defined(BCM_88675_A0)
  54779     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0r */
  54780         soc_block_list[23],
  54781         soc_genreg,
  54782         1,
  54783         0,
  54784         0x108,
  54785         SOC_REG_FLAG_WO,
  54786         0,
  54787         2,
  54788         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0r_fields,
  54789         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54790         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54791         -1,
  54792         -1,
  54793     },
  54794 #endif /* chips */
  54795 
  54796 #if defined(BCM_88675_A0)
  54797     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2r */
  54798         soc_block_list[23],
  54799         soc_genreg,
  54800         1,
  54801         0,
  54802         0x109,
  54803         SOC_REG_FLAG_WO,
  54804         0,
  54805         1,
  54806         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2r_fields,
  54807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  54808         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  54809         -1,
  54810         -1,
  54811     },
  54812 #endif /* chips */
  54813 
  54814 #if defined(BCM_83208_A0)
  54815     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM83208_A0r */
  54816         soc_block_list[23],
  54817         soc_genreg,
  54818         1,
  54819         0,
  54820         0x108,
  54821         SOC_REG_FLAG_WO,
  54822         0,
  54823         2,
  54824         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM83208_A0r_fields,
  54825         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54826         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54827         -1,
  54828         -1,
  54829     },
  54830 #endif /* chips */
  54831 
  54832 #if defined(BCM_88375_A0)
  54833     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88375_A0r */
  54834         soc_block_list[23],
  54835         soc_genreg,
  54836         1,
  54837         0,
  54838         0x108,
  54839         SOC_REG_FLAG_WO,
  54840         0,
  54841         2,
  54842         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88375_A0r_fields,
  54843         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54844         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54845         -1,
  54846         -1,
  54847     },
  54848 #endif /* chips */
  54849 
  54850 #if defined(BCM_88375_B0)
  54851     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88375_B0r */
  54852         soc_block_list[23],
  54853         soc_genreg,
  54854         1,
  54855         0,
  54856         0x108,
  54857         SOC_REG_FLAG_WO,
  54858         0,
  54859         2,
  54860         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88375_B0r_fields,
  54861         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54862         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54863         -1,
  54864         -1,
  54865     },
  54866 #endif /* chips */
  54867 
  54868 #if defined(BCM_88470_A0)
  54869     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88470_A0r */
  54870         soc_block_list[23],
  54871         soc_genreg,
  54872         1,
  54873         0,
  54874         0x108,
  54875         SOC_REG_FLAG_WO,
  54876         0,
  54877         2,
  54878         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88470_A0r_fields,
  54879         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54880         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54881         -1,
  54882         -1,
  54883     },
  54884 #endif /* chips */
  54885 
  54886 #if defined(BCM_88470_B0)
  54887     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88470_B0r */
  54888         soc_block_list[23],
  54889         soc_genreg,
  54890         1,
  54891         0,
  54892         0x108,
  54893         SOC_REG_FLAG_WO,
  54894         0,
  54895         2,
  54896         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88470_B0r_fields,
  54897         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54898         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54899         -1,
  54900         -1,
  54901     },
  54902 #endif /* chips */
  54903 
  54904 #if defined(BCM_88675_B0)
  54905     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88675_B0r */
  54906         soc_block_list[23],
  54907         soc_genreg,
  54908         1,
  54909         0,
  54910         0x108,
  54911         SOC_REG_FLAG_WO,
  54912         0,
  54913         2,
  54914         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88675_B0r_fields,
  54915         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54916         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54917         -1,
  54918         -1,
  54919     },
  54920 #endif /* chips */
  54921 
  54922 #if defined(BCM_88680_A0)
  54923     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88680_A0r */
  54924         soc_block_list[23],
  54925         soc_genreg,
  54926         1,
  54927         0,
  54928         0x108,
  54929         SOC_REG_FLAG_WO,
  54930         0,
  54931         2,
  54932         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88680_A0r_fields,
  54933         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54934         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54935         -1,
  54936         -1,
  54937     },
  54938 #endif /* chips */
  54939 
  54940 #if defined(BCM_88690_A0)
  54941     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88690_A0r */
  54942         soc_block_list[23],
  54943         soc_genreg,
  54944         1,
  54945         0,
  54946         0x128,
  54947         SOC_REG_FLAG_WO,
  54948         0,
  54949         2,
  54950         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88690_A0r_fields,
  54951         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54952         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54953         -1,
  54954         -1,
  54955     },
  54956 #endif /* chips */
  54957 
  54958 #if defined(BCM_88690_B0)
  54959     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88690_B0r */
  54960         soc_block_list[23],
  54961         soc_genreg,
  54962         1,
  54963         0,
  54964         0x128,
  54965         SOC_REG_FLAG_WO,
  54966         0,
  54967         2,
  54968         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88690_B0r_fields,
  54969         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54970         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54971         -1,
  54972         -1,
  54973     },
  54974 #endif /* chips */
  54975 
  54976 #if defined(BCM_88790_A0)
  54977     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88790_A0r */
  54978         soc_block_list[23],
  54979         soc_genreg,
  54980         1,
  54981         0,
  54982         0x128,
  54983         SOC_REG_FLAG_WO,
  54984         0,
  54985         2,
  54986         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_0_BCM88790_A0r_fields,
  54987         SOC_RESET_VAL_DEC(0x000000f0, 0x00000000)
  54988         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  54989         -1,
  54990         -1,
  54991     },
  54992 #endif /* chips */
  54993 
  54994 #if defined(BCM_83208_A0)
  54995     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM83208_A0r */
  54996         soc_block_list[23],
  54997         soc_genreg,
  54998         1,
  54999         0,
  55000         0x109,
  55001         SOC_REG_FLAG_WO,
  55002         0,
  55003         1,
  55004         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM83208_A0r_fields,
  55005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55006         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55007         -1,
  55008         -1,
  55009     },
  55010 #endif /* chips */
  55011 
  55012 #if defined(BCM_88375_A0)
  55013     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88375_A0r */
  55014         soc_block_list[23],
  55015         soc_genreg,
  55016         1,
  55017         0,
  55018         0x109,
  55019         SOC_REG_FLAG_WO,
  55020         0,
  55021         1,
  55022         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88375_A0r_fields,
  55023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55024         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55025         -1,
  55026         -1,
  55027     },
  55028 #endif /* chips */
  55029 
  55030 #if defined(BCM_88375_B0)
  55031     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88375_B0r */
  55032         soc_block_list[23],
  55033         soc_genreg,
  55034         1,
  55035         0,
  55036         0x109,
  55037         SOC_REG_FLAG_WO,
  55038         0,
  55039         1,
  55040         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88375_B0r_fields,
  55041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55042         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55043         -1,
  55044         -1,
  55045     },
  55046 #endif /* chips */
  55047 
  55048 #if defined(BCM_88470_A0)
  55049     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88470_A0r */
  55050         soc_block_list[23],
  55051         soc_genreg,
  55052         1,
  55053         0,
  55054         0x109,
  55055         SOC_REG_FLAG_WO,
  55056         0,
  55057         1,
  55058         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88470_A0r_fields,
  55059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55060         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55061         -1,
  55062         -1,
  55063     },
  55064 #endif /* chips */
  55065 
  55066 #if defined(BCM_88470_B0)
  55067     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88470_B0r */
  55068         soc_block_list[23],
  55069         soc_genreg,
  55070         1,
  55071         0,
  55072         0x109,
  55073         SOC_REG_FLAG_WO,
  55074         0,
  55075         1,
  55076         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88470_B0r_fields,
  55077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55078         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55079         -1,
  55080         -1,
  55081     },
  55082 #endif /* chips */
  55083 
  55084 #if defined(BCM_88675_B0)
  55085     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88675_B0r */
  55086         soc_block_list[23],
  55087         soc_genreg,
  55088         1,
  55089         0,
  55090         0x109,
  55091         SOC_REG_FLAG_WO,
  55092         0,
  55093         1,
  55094         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88675_B0r_fields,
  55095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55096         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55097         -1,
  55098         -1,
  55099     },
  55100 #endif /* chips */
  55101 
  55102 #if defined(BCM_88680_A0)
  55103     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88680_A0r */
  55104         soc_block_list[23],
  55105         soc_genreg,
  55106         1,
  55107         0,
  55108         0x109,
  55109         SOC_REG_FLAG_WO,
  55110         0,
  55111         1,
  55112         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88680_A0r_fields,
  55113         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55114         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55115         -1,
  55116         -1,
  55117     },
  55118 #endif /* chips */
  55119 
  55120 #if defined(BCM_88690_A0)
  55121     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88690_A0r */
  55122         soc_block_list[23],
  55123         soc_genreg,
  55124         1,
  55125         0,
  55126         0x129,
  55127         SOC_REG_FLAG_WO,
  55128         0,
  55129         1,
  55130         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88690_A0r_fields,
  55131         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55132         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55133         -1,
  55134         -1,
  55135     },
  55136 #endif /* chips */
  55137 
  55138 #if defined(BCM_88690_B0)
  55139     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88690_B0r */
  55140         soc_block_list[23],
  55141         soc_genreg,
  55142         1,
  55143         0,
  55144         0x129,
  55145         SOC_REG_FLAG_WO,
  55146         0,
  55147         1,
  55148         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88690_B0r_fields,
  55149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55150         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55151         -1,
  55152         -1,
  55153     },
  55154 #endif /* chips */
  55155 
  55156 #if defined(BCM_88790_A0)
  55157     { /* SOC_REG_INT_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88790_A0r */
  55158         soc_block_list[23],
  55159         soc_genreg,
  55160         1,
  55161         0,
  55162         0x129,
  55163         SOC_REG_FLAG_WO,
  55164         0,
  55165         1,
  55166         soc_BRDC_FMAC_LINK_TOPO_MODE_REG_2_BCM88790_A0r_fields,
  55167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55168         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55169         -1,
  55170         -1,
  55171     },
  55172 #endif /* chips */
  55173 
  55174 #if defined(BCM_88650_A0)
  55175     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTERr */
  55176         soc_block_list[23],
  55177         soc_genreg,
  55178         1,
  55179         0,
  55180         0x30,
  55181         SOC_REG_FLAG_WO,
  55182         0,
  55183         1,
  55184         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTERr_fields,
  55185         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55186         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55187         -1,
  55188         -1,
  55189     },
  55190 #endif /* chips */
  55191 
  55192 #if defined(BCM_83208_A0)
  55193     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM83208_A0r */
  55194         soc_block_list[23],
  55195         soc_genreg,
  55196         1,
  55197         0,
  55198         0x100,
  55199         SOC_REG_FLAG_WO,
  55200         0,
  55201         1,
  55202         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM83208_A0r_fields,
  55203         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55204         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55205         -1,
  55206         -1,
  55207     },
  55208 #endif /* chips */
  55209 
  55210 #if defined(BCM_88202_A0)
  55211     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88202_A0r */
  55212         soc_block_list[23],
  55213         soc_genreg,
  55214         1,
  55215         0,
  55216         0x30,
  55217         SOC_REG_FLAG_WO,
  55218         0,
  55219         1,
  55220         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88202_A0r_fields,
  55221         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55222         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55223         -1,
  55224         -1,
  55225     },
  55226 #endif /* chips */
  55227 
  55228 #if defined(BCM_88375_A0)
  55229     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88375_A0r */
  55230         soc_block_list[23],
  55231         soc_genreg,
  55232         1,
  55233         0,
  55234         0x100,
  55235         SOC_REG_FLAG_WO,
  55236         0,
  55237         1,
  55238         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88375_A0r_fields,
  55239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55240         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55241         -1,
  55242         -1,
  55243     },
  55244 #endif /* chips */
  55245 
  55246 #if defined(BCM_88375_B0)
  55247     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88375_B0r */
  55248         soc_block_list[23],
  55249         soc_genreg,
  55250         1,
  55251         0,
  55252         0x100,
  55253         SOC_REG_FLAG_WO,
  55254         0,
  55255         1,
  55256         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88375_B0r_fields,
  55257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55258         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55259         -1,
  55260         -1,
  55261     },
  55262 #endif /* chips */
  55263 
  55264 #if defined(BCM_88470_A0)
  55265     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88470_A0r */
  55266         soc_block_list[23],
  55267         soc_genreg,
  55268         1,
  55269         0,
  55270         0x100,
  55271         SOC_REG_FLAG_WO,
  55272         0,
  55273         1,
  55274         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88470_A0r_fields,
  55275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55276         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55277         -1,
  55278         -1,
  55279     },
  55280 #endif /* chips */
  55281 
  55282 #if defined(BCM_88470_B0)
  55283     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88470_B0r */
  55284         soc_block_list[23],
  55285         soc_genreg,
  55286         1,
  55287         0,
  55288         0x100,
  55289         SOC_REG_FLAG_WO,
  55290         0,
  55291         1,
  55292         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88470_B0r_fields,
  55293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55294         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55295         -1,
  55296         -1,
  55297     },
  55298 #endif /* chips */
  55299 
  55300 #if defined(BCM_88650_B0)
  55301     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88650_B0r */
  55302         soc_block_list[23],
  55303         soc_genreg,
  55304         1,
  55305         0,
  55306         0x30,
  55307         SOC_REG_FLAG_WO,
  55308         0,
  55309         1,
  55310         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88650_B0r_fields,
  55311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55312         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55313         -1,
  55314         -1,
  55315     },
  55316 #endif /* chips */
  55317 
  55318 #if defined(BCM_88660_A0)
  55319     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88660_A0r */
  55320         soc_block_list[23],
  55321         soc_genreg,
  55322         1,
  55323         0,
  55324         0x30,
  55325         SOC_REG_FLAG_WO,
  55326         0,
  55327         1,
  55328         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88660_A0r_fields,
  55329         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55330         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55331         -1,
  55332         -1,
  55333     },
  55334 #endif /* chips */
  55335 
  55336 #if defined(BCM_88675_A0)
  55337     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88675_A0r */
  55338         soc_block_list[23],
  55339         soc_genreg,
  55340         1,
  55341         0,
  55342         0x100,
  55343         SOC_REG_FLAG_WO,
  55344         0,
  55345         1,
  55346         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88675_A0r_fields,
  55347         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55348         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55349         -1,
  55350         -1,
  55351     },
  55352 #endif /* chips */
  55353 
  55354 #if defined(BCM_88675_B0)
  55355     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88675_B0r */
  55356         soc_block_list[23],
  55357         soc_genreg,
  55358         1,
  55359         0,
  55360         0x100,
  55361         SOC_REG_FLAG_WO,
  55362         0,
  55363         1,
  55364         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88675_B0r_fields,
  55365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55366         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55367         -1,
  55368         -1,
  55369     },
  55370 #endif /* chips */
  55371 
  55372 #if defined(BCM_88680_A0)
  55373     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88680_A0r */
  55374         soc_block_list[23],
  55375         soc_genreg,
  55376         1,
  55377         0,
  55378         0x100,
  55379         SOC_REG_FLAG_WO,
  55380         0,
  55381         1,
  55382         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88680_A0r_fields,
  55383         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55384         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55385         -1,
  55386         -1,
  55387     },
  55388 #endif /* chips */
  55389 
  55390 #if defined(BCM_88690_A0)
  55391     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88690_A0r */
  55392         soc_block_list[23],
  55393         soc_genreg,
  55394         1,
  55395         0,
  55396         0x118,
  55397         SOC_REG_FLAG_WO,
  55398         0,
  55399         1,
  55400         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88690_A0r_fields,
  55401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55402         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55403         -1,
  55404         -1,
  55405     },
  55406 #endif /* chips */
  55407 
  55408 #if defined(BCM_88690_B0)
  55409     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88690_B0r */
  55410         soc_block_list[23],
  55411         soc_genreg,
  55412         1,
  55413         0,
  55414         0x118,
  55415         SOC_REG_FLAG_WO,
  55416         0,
  55417         1,
  55418         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88690_B0r_fields,
  55419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55420         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55421         -1,
  55422         -1,
  55423     },
  55424 #endif /* chips */
  55425 
  55426 #if defined(BCM_88790_A0)
  55427     { /* SOC_REG_INT_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88790_A0r */
  55428         soc_block_list[23],
  55429         soc_genreg,
  55430         1,
  55431         0,
  55432         0x118,
  55433         SOC_REG_FLAG_WO,
  55434         0,
  55435         1,
  55436         soc_BRDC_FMAC_LOOPBACK_ENABLE_REGISTER_BCM88790_A0r_fields,
  55437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55438         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  55439         -1,
  55440         -1,
  55441     },
  55442 #endif /* chips */
  55443 
  55444 #if defined(BCM_88470_A0)
  55445     { /* SOC_REG_INT_BRDC_FMAC_MACT_PM_CREDIT_FILTERr */
  55446         soc_block_list[23],
  55447         soc_genreg,
  55448         4,
  55449         0,
  55450         0x110,
  55451         SOC_REG_FLAG_ARRAY |
  55452                           SOC_REG_FLAG_WO |
  55453                           SOC_REG_FLAG_REG_ARRAY,
  55454         0,
  55455         1,
  55456         soc_BRDC_FMAC_MACT_PM_CREDIT_FILTERr_fields,
  55457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55458         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  55459         -1,
  55460         -1,
  55461     },
  55462 #endif /* chips */
  55463 
  55464 #if defined(BCM_88470_B0)
  55465     { /* SOC_REG_INT_BRDC_FMAC_MACT_PM_CREDIT_FILTER_BCM88470_B0r */
  55466         soc_block_list[23],
  55467         soc_genreg,
  55468         4,
  55469         0,
  55470         0x110,
  55471         SOC_REG_FLAG_ARRAY |
  55472                           SOC_REG_FLAG_WO |
  55473                           SOC_REG_FLAG_REG_ARRAY,
  55474         0,
  55475         1,
  55476         soc_BRDC_FMAC_MACT_PM_CREDIT_FILTER_BCM88470_B0r_fields,
  55477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55478         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  55479         -1,
  55480         -1,
  55481     },
  55482 #endif /* chips */
  55483 
  55484 #if defined(BCM_88675_A0)
  55485     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNTr */
  55486         soc_block_list[23],
  55487         soc_genreg,
  55488         1,
  55489         0,
  55490         0x98,
  55491         SOC_REG_FLAG_64_BITS |
  55492                           SOC_REG_FLAG_RO |
  55493                           SOC_REG_FLAG_WO,
  55494         0,
  55495         4,
  55496         soc_BRDC_FMAC_PARITY_ERR_CNTr_fields,
  55497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55498         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55499         -1,
  55500         -1,
  55501     },
  55502 #endif /* chips */
  55503 
  55504 #if defined(BCM_83208_A0)
  55505     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM83208_A0r */
  55506         soc_block_list[23],
  55507         soc_genreg,
  55508         1,
  55509         0,
  55510         0x98,
  55511         SOC_REG_FLAG_64_BITS |
  55512                           SOC_REG_FLAG_RO |
  55513                           SOC_REG_FLAG_WO,
  55514         0,
  55515         4,
  55516         soc_BLH_PARITY_ERR_CNTr_fields,
  55517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55518         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55519         -1,
  55520         -1,
  55521     },
  55522 #endif /* chips */
  55523 
  55524 #if defined(BCM_88375_A0)
  55525     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88375_A0r */
  55526         soc_block_list[23],
  55527         soc_genreg,
  55528         1,
  55529         0,
  55530         0x98,
  55531         SOC_REG_FLAG_64_BITS |
  55532                           SOC_REG_FLAG_RO |
  55533                           SOC_REG_FLAG_WO,
  55534         0,
  55535         4,
  55536         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88375_A0r_fields,
  55537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55538         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55539         -1,
  55540         -1,
  55541     },
  55542 #endif /* chips */
  55543 
  55544 #if defined(BCM_88375_B0)
  55545     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88375_B0r */
  55546         soc_block_list[23],
  55547         soc_genreg,
  55548         1,
  55549         0,
  55550         0x98,
  55551         SOC_REG_FLAG_64_BITS |
  55552                           SOC_REG_FLAG_RO |
  55553                           SOC_REG_FLAG_WO,
  55554         0,
  55555         4,
  55556         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88375_B0r_fields,
  55557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55558         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55559         -1,
  55560         -1,
  55561     },
  55562 #endif /* chips */
  55563 
  55564 #if defined(BCM_88470_A0)
  55565     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88470_A0r */
  55566         soc_block_list[23],
  55567         soc_genreg,
  55568         1,
  55569         0,
  55570         0x98,
  55571         SOC_REG_FLAG_64_BITS |
  55572                           SOC_REG_FLAG_RO |
  55573                           SOC_REG_FLAG_WO,
  55574         0,
  55575         4,
  55576         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88470_A0r_fields,
  55577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55578         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55579         -1,
  55580         -1,
  55581     },
  55582 #endif /* chips */
  55583 
  55584 #if defined(BCM_88470_B0)
  55585     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88470_B0r */
  55586         soc_block_list[23],
  55587         soc_genreg,
  55588         1,
  55589         0,
  55590         0x98,
  55591         SOC_REG_FLAG_64_BITS |
  55592                           SOC_REG_FLAG_RO |
  55593                           SOC_REG_FLAG_WO,
  55594         0,
  55595         4,
  55596         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88470_B0r_fields,
  55597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55598         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55599         -1,
  55600         -1,
  55601     },
  55602 #endif /* chips */
  55603 
  55604 #if defined(BCM_88675_B0)
  55605     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88675_B0r */
  55606         soc_block_list[23],
  55607         soc_genreg,
  55608         1,
  55609         0,
  55610         0x98,
  55611         SOC_REG_FLAG_64_BITS |
  55612                           SOC_REG_FLAG_RO |
  55613                           SOC_REG_FLAG_WO,
  55614         0,
  55615         4,
  55616         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88675_B0r_fields,
  55617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55618         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55619         -1,
  55620         -1,
  55621     },
  55622 #endif /* chips */
  55623 
  55624 #if defined(BCM_88680_A0)
  55625     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88680_A0r */
  55626         soc_block_list[23],
  55627         soc_genreg,
  55628         1,
  55629         0,
  55630         0x98,
  55631         SOC_REG_FLAG_64_BITS |
  55632                           SOC_REG_FLAG_RO |
  55633                           SOC_REG_FLAG_WO,
  55634         0,
  55635         4,
  55636         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88680_A0r_fields,
  55637         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55638         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55639         -1,
  55640         -1,
  55641     },
  55642 #endif /* chips */
  55643 
  55644 #if defined(BCM_88690_A0)
  55645     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88690_A0r */
  55646         soc_block_list[23],
  55647         soc_genreg,
  55648         1,
  55649         0,
  55650         0x98,
  55651         SOC_REG_FLAG_64_BITS |
  55652                           SOC_REG_FLAG_RO |
  55653                           SOC_REG_FLAG_WO,
  55654         SOC_REG_FLAG_COUNTER_FEILDS |
  55655                           SOC_REG_FLAG_INIT_ON_READ,
  55656         4,
  55657         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88690_A0r_fields,
  55658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55659         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55660         -1,
  55661         -1,
  55662     },
  55663 #endif /* chips */
  55664 
  55665 #if defined(BCM_88790_A0)
  55666     { /* SOC_REG_INT_BRDC_FMAC_PARITY_ERR_CNT_BCM88790_A0r */
  55667         soc_block_list[23],
  55668         soc_genreg,
  55669         1,
  55670         0,
  55671         0x98,
  55672         SOC_REG_FLAG_64_BITS |
  55673                           SOC_REG_FLAG_RO |
  55674                           SOC_REG_FLAG_WO,
  55675         SOC_REG_FLAG_COUNTER_FEILDS,
  55676         4,
  55677         soc_BRDC_FMAC_PARITY_ERR_CNT_BCM88790_A0r_fields,
  55678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55679         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  55680         -1,
  55681         -1,
  55682     },
  55683 #endif /* chips */
  55684 
  55685 #if defined(BCM_88675_A0)
  55686     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATEr */
  55687         soc_block_list[23],
  55688         soc_genreg,
  55689         1,
  55690         0,
  55691         0xaa,
  55692         SOC_REG_FLAG_WO,
  55693         0,
  55694         1,
  55695         soc_BRDC_FMAC_PAR_ERR_INITIATEr_fields,
  55696         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55697         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55698         -1,
  55699         -1,
  55700     },
  55701 #endif /* chips */
  55702 
  55703 #if defined(BCM_83208_A0)
  55704     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM83208_A0r */
  55705         soc_block_list[23],
  55706         soc_genreg,
  55707         1,
  55708         0,
  55709         0xaa,
  55710         SOC_REG_FLAG_WO,
  55711         0,
  55712         1,
  55713         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM83208_A0r_fields,
  55714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55715         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55716         -1,
  55717         -1,
  55718     },
  55719 #endif /* chips */
  55720 
  55721 #if defined(BCM_88375_A0)
  55722     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88375_A0r */
  55723         soc_block_list[23],
  55724         soc_genreg,
  55725         1,
  55726         0,
  55727         0xaa,
  55728         SOC_REG_FLAG_WO,
  55729         0,
  55730         1,
  55731         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88375_A0r_fields,
  55732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55733         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55734         -1,
  55735         -1,
  55736     },
  55737 #endif /* chips */
  55738 
  55739 #if defined(BCM_88375_B0)
  55740     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88375_B0r */
  55741         soc_block_list[23],
  55742         soc_genreg,
  55743         1,
  55744         0,
  55745         0xaa,
  55746         SOC_REG_FLAG_WO,
  55747         0,
  55748         1,
  55749         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88375_B0r_fields,
  55750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55751         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55752         -1,
  55753         -1,
  55754     },
  55755 #endif /* chips */
  55756 
  55757 #if defined(BCM_88470_A0)
  55758     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88470_A0r */
  55759         soc_block_list[23],
  55760         soc_genreg,
  55761         1,
  55762         0,
  55763         0xaa,
  55764         SOC_REG_FLAG_WO,
  55765         0,
  55766         1,
  55767         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88470_A0r_fields,
  55768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55769         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55770         -1,
  55771         -1,
  55772     },
  55773 #endif /* chips */
  55774 
  55775 #if defined(BCM_88470_B0)
  55776     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88470_B0r */
  55777         soc_block_list[23],
  55778         soc_genreg,
  55779         1,
  55780         0,
  55781         0xaa,
  55782         SOC_REG_FLAG_WO,
  55783         0,
  55784         1,
  55785         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88470_B0r_fields,
  55786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55787         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55788         -1,
  55789         -1,
  55790     },
  55791 #endif /* chips */
  55792 
  55793 #if defined(BCM_88675_B0)
  55794     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88675_B0r */
  55795         soc_block_list[23],
  55796         soc_genreg,
  55797         1,
  55798         0,
  55799         0xaa,
  55800         SOC_REG_FLAG_WO,
  55801         0,
  55802         1,
  55803         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88675_B0r_fields,
  55804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55805         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55806         -1,
  55807         -1,
  55808     },
  55809 #endif /* chips */
  55810 
  55811 #if defined(BCM_88680_A0)
  55812     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88680_A0r */
  55813         soc_block_list[23],
  55814         soc_genreg,
  55815         1,
  55816         0,
  55817         0xaa,
  55818         SOC_REG_FLAG_WO,
  55819         0,
  55820         1,
  55821         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88680_A0r_fields,
  55822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55823         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55824         -1,
  55825         -1,
  55826     },
  55827 #endif /* chips */
  55828 
  55829 #if defined(BCM_88690_A0)
  55830     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88690_A0r */
  55831         soc_block_list[23],
  55832         soc_genreg,
  55833         1,
  55834         0,
  55835         0xaa,
  55836         SOC_REG_FLAG_WO,
  55837         0,
  55838         1,
  55839         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88690_A0r_fields,
  55840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55841         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55842         -1,
  55843         -1,
  55844     },
  55845 #endif /* chips */
  55846 
  55847 #if defined(BCM_88790_A0)
  55848     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_INITIATE_BCM88790_A0r */
  55849         soc_block_list[23],
  55850         soc_genreg,
  55851         1,
  55852         0,
  55853         0xaa,
  55854         SOC_REG_FLAG_WO,
  55855         0,
  55856         1,
  55857         soc_BRDC_FMAC_PAR_ERR_INITIATE_BCM88790_A0r_fields,
  55858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55859         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55860         -1,
  55861         -1,
  55862     },
  55863 #endif /* chips */
  55864 
  55865 #if defined(BCM_88675_A0)
  55866     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASKr */
  55867         soc_block_list[23],
  55868         soc_genreg,
  55869         1,
  55870         0,
  55871         0xa0,
  55872         SOC_REG_FLAG_WO,
  55873         0,
  55874         1,
  55875         soc_BRDC_FMAC_PAR_ERR_MEM_MASKr_fields,
  55876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55877         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55878         -1,
  55879         -1,
  55880     },
  55881 #endif /* chips */
  55882 
  55883 #if defined(BCM_83208_A0)
  55884     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM83208_A0r */
  55885         soc_block_list[23],
  55886         soc_genreg,
  55887         1,
  55888         0,
  55889         0xa0,
  55890         SOC_REG_FLAG_WO,
  55891         0,
  55892         1,
  55893         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM83208_A0r_fields,
  55894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55895         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55896         -1,
  55897         -1,
  55898     },
  55899 #endif /* chips */
  55900 
  55901 #if defined(BCM_88375_A0)
  55902     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88375_A0r */
  55903         soc_block_list[23],
  55904         soc_genreg,
  55905         1,
  55906         0,
  55907         0xa0,
  55908         SOC_REG_FLAG_WO,
  55909         0,
  55910         1,
  55911         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88375_A0r_fields,
  55912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55913         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55914         -1,
  55915         -1,
  55916     },
  55917 #endif /* chips */
  55918 
  55919 #if defined(BCM_88375_B0)
  55920     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88375_B0r */
  55921         soc_block_list[23],
  55922         soc_genreg,
  55923         1,
  55924         0,
  55925         0xa0,
  55926         SOC_REG_FLAG_WO,
  55927         0,
  55928         1,
  55929         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88375_B0r_fields,
  55930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55931         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55932         -1,
  55933         -1,
  55934     },
  55935 #endif /* chips */
  55936 
  55937 #if defined(BCM_88470_A0)
  55938     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88470_A0r */
  55939         soc_block_list[23],
  55940         soc_genreg,
  55941         1,
  55942         0,
  55943         0xa0,
  55944         SOC_REG_FLAG_WO,
  55945         0,
  55946         1,
  55947         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88470_A0r_fields,
  55948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55949         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55950         -1,
  55951         -1,
  55952     },
  55953 #endif /* chips */
  55954 
  55955 #if defined(BCM_88470_B0)
  55956     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88470_B0r */
  55957         soc_block_list[23],
  55958         soc_genreg,
  55959         1,
  55960         0,
  55961         0xa0,
  55962         SOC_REG_FLAG_WO,
  55963         0,
  55964         1,
  55965         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88470_B0r_fields,
  55966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55967         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55968         -1,
  55969         -1,
  55970     },
  55971 #endif /* chips */
  55972 
  55973 #if defined(BCM_88675_B0)
  55974     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88675_B0r */
  55975         soc_block_list[23],
  55976         soc_genreg,
  55977         1,
  55978         0,
  55979         0xa0,
  55980         SOC_REG_FLAG_WO,
  55981         0,
  55982         1,
  55983         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88675_B0r_fields,
  55984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  55985         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  55986         -1,
  55987         -1,
  55988     },
  55989 #endif /* chips */
  55990 
  55991 #if defined(BCM_88680_A0)
  55992     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88680_A0r */
  55993         soc_block_list[23],
  55994         soc_genreg,
  55995         1,
  55996         0,
  55997         0xa0,
  55998         SOC_REG_FLAG_WO,
  55999         0,
  56000         1,
  56001         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88680_A0r_fields,
  56002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56003         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56004         -1,
  56005         -1,
  56006     },
  56007 #endif /* chips */
  56008 
  56009 #if defined(BCM_88690_A0)
  56010     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88690_A0r */
  56011         soc_block_list[23],
  56012         soc_genreg,
  56013         1,
  56014         0,
  56015         0xa0,
  56016         SOC_REG_FLAG_WO,
  56017         0,
  56018         1,
  56019         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88690_A0r_fields,
  56020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56021         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56022         -1,
  56023         -1,
  56024     },
  56025 #endif /* chips */
  56026 
  56027 #if defined(BCM_88790_A0)
  56028     { /* SOC_REG_INT_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88790_A0r */
  56029         soc_block_list[23],
  56030         soc_genreg,
  56031         1,
  56032         0,
  56033         0xa0,
  56034         SOC_REG_FLAG_WO,
  56035         0,
  56036         1,
  56037         soc_BRDC_FMAC_PAR_ERR_MEM_MASK_BCM88790_A0r_fields,
  56038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56039         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56040         -1,
  56041         -1,
  56042     },
  56043 #endif /* chips */
  56044 
  56045 #if defined(BCM_88650_A0)
  56046     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTERr */
  56047         soc_block_list[23],
  56048         soc_genreg,
  56049         1,
  56050         0,
  56051         0x63,
  56052         SOC_REG_FLAG_WO,
  56053         0,
  56054         2,
  56055         soc_BRDC_FMAC_RECEIVE_RESET_REGISTERr_fields,
  56056         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56057         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56058         -1,
  56059         -1,
  56060     },
  56061 #endif /* chips */
  56062 
  56063 #if defined(BCM_83208_A0)
  56064     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM83208_A0r */
  56065         soc_block_list[23],
  56066         soc_genreg,
  56067         1,
  56068         0,
  56069         0x106,
  56070         SOC_REG_FLAG_WO,
  56071         0,
  56072         2,
  56073         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM83208_A0r_fields,
  56074         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56075         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56076         -1,
  56077         -1,
  56078     },
  56079 #endif /* chips */
  56080 
  56081 #if defined(BCM_88202_A0)
  56082     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88202_A0r */
  56083         soc_block_list[23],
  56084         soc_genreg,
  56085         1,
  56086         0,
  56087         0x63,
  56088         SOC_REG_FLAG_WO,
  56089         0,
  56090         2,
  56091         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88202_A0r_fields,
  56092         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56093         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56094         -1,
  56095         -1,
  56096     },
  56097 #endif /* chips */
  56098 
  56099 #if defined(BCM_88375_A0)
  56100     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88375_A0r */
  56101         soc_block_list[23],
  56102         soc_genreg,
  56103         1,
  56104         0,
  56105         0x106,
  56106         SOC_REG_FLAG_WO,
  56107         0,
  56108         2,
  56109         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88375_A0r_fields,
  56110         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56111         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56112         -1,
  56113         -1,
  56114     },
  56115 #endif /* chips */
  56116 
  56117 #if defined(BCM_88375_B0)
  56118     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88375_B0r */
  56119         soc_block_list[23],
  56120         soc_genreg,
  56121         1,
  56122         0,
  56123         0x106,
  56124         SOC_REG_FLAG_WO,
  56125         0,
  56126         2,
  56127         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88375_B0r_fields,
  56128         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56129         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56130         -1,
  56131         -1,
  56132     },
  56133 #endif /* chips */
  56134 
  56135 #if defined(BCM_88470_A0)
  56136     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88470_A0r */
  56137         soc_block_list[23],
  56138         soc_genreg,
  56139         1,
  56140         0,
  56141         0x106,
  56142         SOC_REG_FLAG_WO,
  56143         0,
  56144         2,
  56145         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88470_A0r_fields,
  56146         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56147         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56148         -1,
  56149         -1,
  56150     },
  56151 #endif /* chips */
  56152 
  56153 #if defined(BCM_88470_B0)
  56154     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88470_B0r */
  56155         soc_block_list[23],
  56156         soc_genreg,
  56157         1,
  56158         0,
  56159         0x106,
  56160         SOC_REG_FLAG_WO,
  56161         0,
  56162         2,
  56163         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88470_B0r_fields,
  56164         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56165         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56166         -1,
  56167         -1,
  56168     },
  56169 #endif /* chips */
  56170 
  56171 #if defined(BCM_88650_B0)
  56172     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88650_B0r */
  56173         soc_block_list[23],
  56174         soc_genreg,
  56175         1,
  56176         0,
  56177         0x63,
  56178         SOC_REG_FLAG_WO,
  56179         0,
  56180         2,
  56181         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88650_B0r_fields,
  56182         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56183         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56184         -1,
  56185         -1,
  56186     },
  56187 #endif /* chips */
  56188 
  56189 #if defined(BCM_88660_A0)
  56190     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88660_A0r */
  56191         soc_block_list[23],
  56192         soc_genreg,
  56193         1,
  56194         0,
  56195         0x63,
  56196         SOC_REG_FLAG_WO,
  56197         0,
  56198         2,
  56199         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88660_A0r_fields,
  56200         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56201         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56202         -1,
  56203         -1,
  56204     },
  56205 #endif /* chips */
  56206 
  56207 #if defined(BCM_88675_A0)
  56208     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88675_A0r */
  56209         soc_block_list[23],
  56210         soc_genreg,
  56211         1,
  56212         0,
  56213         0x106,
  56214         SOC_REG_FLAG_WO,
  56215         0,
  56216         2,
  56217         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88675_A0r_fields,
  56218         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56219         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56220         -1,
  56221         -1,
  56222     },
  56223 #endif /* chips */
  56224 
  56225 #if defined(BCM_88675_B0)
  56226     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88675_B0r */
  56227         soc_block_list[23],
  56228         soc_genreg,
  56229         1,
  56230         0,
  56231         0x106,
  56232         SOC_REG_FLAG_WO,
  56233         0,
  56234         2,
  56235         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88675_B0r_fields,
  56236         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56237         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56238         -1,
  56239         -1,
  56240     },
  56241 #endif /* chips */
  56242 
  56243 #if defined(BCM_88680_A0)
  56244     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88680_A0r */
  56245         soc_block_list[23],
  56246         soc_genreg,
  56247         1,
  56248         0,
  56249         0x106,
  56250         SOC_REG_FLAG_WO,
  56251         0,
  56252         2,
  56253         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88680_A0r_fields,
  56254         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56255         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56256         -1,
  56257         -1,
  56258     },
  56259 #endif /* chips */
  56260 
  56261 #if defined(BCM_88690_A0)
  56262     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88690_A0r */
  56263         soc_block_list[23],
  56264         soc_genreg,
  56265         1,
  56266         0,
  56267         0x126,
  56268         SOC_REG_FLAG_WO,
  56269         0,
  56270         2,
  56271         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88690_A0r_fields,
  56272         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56273         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56274         -1,
  56275         -1,
  56276     },
  56277 #endif /* chips */
  56278 
  56279 #if defined(BCM_88690_B0)
  56280     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88690_B0r */
  56281         soc_block_list[23],
  56282         soc_genreg,
  56283         1,
  56284         0,
  56285         0x126,
  56286         SOC_REG_FLAG_WO,
  56287         0,
  56288         2,
  56289         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88690_B0r_fields,
  56290         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56291         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56292         -1,
  56293         -1,
  56294     },
  56295 #endif /* chips */
  56296 
  56297 #if defined(BCM_88790_A0)
  56298     { /* SOC_REG_INT_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88790_A0r */
  56299         soc_block_list[23],
  56300         soc_genreg,
  56301         1,
  56302         0,
  56303         0x126,
  56304         SOC_REG_FLAG_WO,
  56305         0,
  56306         2,
  56307         soc_BRDC_FMAC_RECEIVE_RESET_REGISTER_BCM88790_A0r_fields,
  56308         SOC_RESET_VAL_DEC(0x000f000f, 0x00000000)
  56309         SOC_RESET_MASK_DEC(0x000f000f, 0x00000000)
  56310         -1,
  56311         -1,
  56312     },
  56313 #endif /* chips */
  56314 
  56315 #if defined(BCM_88650_A0)
  56316     { /* SOC_REG_INT_BRDC_FMAC_REG_0050r */
  56317         soc_block_list[23],
  56318         soc_genreg,
  56319         1,
  56320         0,
  56321         0x50,
  56322         SOC_REG_FLAG_WO,
  56323         0,
  56324         1,
  56325         soc_BRDC_FMAC_REG_0050r_fields,
  56326         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56327         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56328         -1,
  56329         -1,
  56330     },
  56331 #endif /* chips */
  56332 
  56333 #if defined(BCM_88650_A0)
  56334     { /* SOC_REG_INT_BRDC_FMAC_REG_0051r */
  56335         soc_block_list[23],
  56336         soc_genreg,
  56337         1,
  56338         0,
  56339         0x51,
  56340         SOC_REG_FLAG_WO,
  56341         0,
  56342         1,
  56343         soc_BRDC_FMAC_REG_0051r_fields,
  56344         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56345         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56346         -1,
  56347         -1,
  56348     },
  56349 #endif /* chips */
  56350 
  56351 #if defined(BCM_88650_A0)
  56352     { /* SOC_REG_INT_BRDC_FMAC_REG_0052r */
  56353         soc_block_list[23],
  56354         soc_genreg,
  56355         1,
  56356         0,
  56357         0x52,
  56358         SOC_REG_FLAG_WO,
  56359         0,
  56360         1,
  56361         soc_BRDC_FMAC_REG_0052r_fields,
  56362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56363         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56364         -1,
  56365         -1,
  56366     },
  56367 #endif /* chips */
  56368 
  56369 #if defined(BCM_88650_A0)
  56370     { /* SOC_REG_INT_BRDC_FMAC_REG_0053r */
  56371         soc_block_list[23],
  56372         soc_genreg,
  56373         1,
  56374         0,
  56375         0x53,
  56376         SOC_REG_FLAG_WO,
  56377         0,
  56378         1,
  56379         soc_BRDC_FMAC_REG_0053r_fields,
  56380         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56381         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56382         -1,
  56383         -1,
  56384     },
  56385 #endif /* chips */
  56386 
  56387 #if defined(BCM_88650_A0)
  56388     { /* SOC_REG_INT_BRDC_FMAC_REG_0054r */
  56389         soc_block_list[23],
  56390         soc_genreg,
  56391         1,
  56392         0,
  56393         0x54,
  56394         SOC_REG_FLAG_WO,
  56395         0,
  56396         2,
  56397         soc_BRDC_FMAC_REG_0054r_fields,
  56398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56399         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  56400         -1,
  56401         -1,
  56402     },
  56403 #endif /* chips */
  56404 
  56405 #if defined(BCM_88650_A0)
  56406     { /* SOC_REG_INT_BRDC_FMAC_REG_0058r */
  56407         soc_block_list[23],
  56408         soc_genreg,
  56409         1,
  56410         0,
  56411         0x58,
  56412         SOC_REG_FLAG_WO,
  56413         0,
  56414         1,
  56415         soc_BRDC_FMAC_REG_0058r_fields,
  56416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56417         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56418         -1,
  56419         -1,
  56420     },
  56421 #endif /* chips */
  56422 
  56423 #if defined(BCM_88650_A0)
  56424     { /* SOC_REG_INT_BRDC_FMAC_REG_0068r */
  56425         soc_block_list[23],
  56426         soc_genreg,
  56427         1,
  56428         0,
  56429         0x68,
  56430         SOC_REG_FLAG_WO,
  56431         0,
  56432         2,
  56433         soc_BRDC_FMAC_REG_0068r_fields,
  56434         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56435         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  56436         -1,
  56437         -1,
  56438     },
  56439 #endif /* chips */
  56440 
  56441 #if defined(BCM_88650_A0)
  56442     { /* SOC_REG_INT_BRDC_FMAC_REG_0096r */
  56443         soc_block_list[23],
  56444         soc_genreg,
  56445         1,
  56446         0,
  56447         0x96,
  56448         SOC_REG_FLAG_64_BITS |
  56449                           SOC_REG_FLAG_WO,
  56450         0,
  56451         1,
  56452         soc_BRDC_FMAC_REG_0096r_fields,
  56453         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  56454         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  56455         -1,
  56456         -1,
  56457     },
  56458 #endif /* chips */
  56459 
  56460 #if defined(BCM_88650_A0)
  56461     { /* SOC_REG_INT_BRDC_FMAC_REG_0098r */
  56462         soc_block_list[23],
  56463         soc_genreg,
  56464         1,
  56465         0,
  56466         0x98,
  56467         SOC_REG_FLAG_WO,
  56468         0,
  56469         8,
  56470         soc_BRDC_FMAC_REG_0098r_fields,
  56471         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  56472         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  56473         -1,
  56474         -1,
  56475     },
  56476 #endif /* chips */
  56477 
  56478 #if defined(BCM_88650_A0)
  56479     { /* SOC_REG_INT_BRDC_FMAC_REG_0099r */
  56480         soc_block_list[23],
  56481         soc_genreg,
  56482         1,
  56483         0,
  56484         0x99,
  56485         SOC_REG_FLAG_WO,
  56486         0,
  56487         1,
  56488         soc_BRDC_FMAC_REG_0099r_fields,
  56489         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  56490         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56491         -1,
  56492         -1,
  56493     },
  56494 #endif /* chips */
  56495 
  56496 #if defined(BCM_88675_A0)
  56497     { /* SOC_REG_INT_BRDC_FMAC_REG_0102r */
  56498         soc_block_list[23],
  56499         soc_genreg,
  56500         1,
  56501         0,
  56502         0x102,
  56503         SOC_REG_FLAG_WO,
  56504         0,
  56505         1,
  56506         soc_BRDC_FMAC_REG_0102r_fields,
  56507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56508         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  56509         -1,
  56510         -1,
  56511     },
  56512 #endif /* chips */
  56513 
  56514 #if defined(BCM_83208_A0)
  56515     { /* SOC_REG_INT_BRDC_FMAC_REG_0114r */
  56516         soc_block_list[23],
  56517         soc_genreg,
  56518         4,
  56519         0,
  56520         0x114,
  56521         SOC_REG_FLAG_ARRAY |
  56522                           SOC_REG_FLAG_RO |
  56523                           SOC_REG_FLAG_WO |
  56524                           SOC_REG_FLAG_REG_ARRAY,
  56525         0,
  56526         1,
  56527         soc_BRDC_FMAC_REG_0114r_fields,
  56528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56529         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56530         -1,
  56531         -1,
  56532     },
  56533 #endif /* chips */
  56534 
  56535 #if defined(BCM_88675_A0)
  56536     { /* SOC_REG_INT_BRDC_FMAC_REG_0116r */
  56537         soc_block_list[23],
  56538         soc_genreg,
  56539         1,
  56540         0,
  56541         0x116,
  56542         SOC_REG_FLAG_64_BITS |
  56543                           SOC_REG_FLAG_WO,
  56544         0,
  56545         1,
  56546         soc_BRDC_FMAC_REG_0116r_fields,
  56547         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  56548         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  56549         -1,
  56550         -1,
  56551     },
  56552 #endif /* chips */
  56553 
  56554 #if defined(BCM_88675_A0)
  56555     { /* SOC_REG_INT_BRDC_FMAC_REG_0118r */
  56556         soc_block_list[23],
  56557         soc_genreg,
  56558         1,
  56559         0,
  56560         0x118,
  56561         SOC_REG_FLAG_WO,
  56562         0,
  56563         8,
  56564         soc_BRDC_FMAC_REG_0118r_fields,
  56565         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  56566         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  56567         -1,
  56568         -1,
  56569     },
  56570 #endif /* chips */
  56571 
  56572 #if defined(BCM_88675_A0)
  56573     { /* SOC_REG_INT_BRDC_FMAC_REG_0119r */
  56574         soc_block_list[23],
  56575         soc_genreg,
  56576         1,
  56577         0,
  56578         0x119,
  56579         SOC_REG_FLAG_WO,
  56580         0,
  56581         1,
  56582         soc_BRDC_FMAC_REG_0119r_fields,
  56583         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  56584         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  56585         -1,
  56586         -1,
  56587     },
  56588 #endif /* chips */
  56589 
  56590 #if defined(BCM_83208_A0)
  56591     { /* SOC_REG_INT_BRDC_FMAC_REG_0121r */
  56592         soc_block_list[23],
  56593         soc_genreg,
  56594         1,
  56595         0,
  56596         0x121,
  56597         SOC_REG_FLAG_WO,
  56598         0,
  56599         3,
  56600         soc_BRDC_FMAC_REG_0121r_fields,
  56601         SOC_RESET_VAL_DEC(0x00000015, 0x00000000)
  56602         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  56603         -1,
  56604         -1,
  56605     },
  56606 #endif /* chips */
  56607 
  56608 #if defined(BCM_83208_A0)
  56609     { /* SOC_REG_INT_BRDC_FMAC_REG_0122r */
  56610         soc_block_list[23],
  56611         soc_genreg,
  56612         1,
  56613         0,
  56614         0x122,
  56615         SOC_REG_FLAG_WO,
  56616         0,
  56617         2,
  56618         soc_BRDC_FMAC_REG_0122r_fields,
  56619         SOC_RESET_VAL_DEC(0x00000005, 0x00000000)
  56620         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  56621         -1,
  56622         -1,
  56623     },
  56624 #endif /* chips */
  56625 
  56626 #if defined(BCM_83208_A0)
  56627     { /* SOC_REG_INT_BRDC_FMAC_REG_0123r */
  56628         soc_block_list[23],
  56629         soc_genreg,
  56630         1,
  56631         0,
  56632         0x123,
  56633         SOC_REG_FLAG_WO,
  56634         0,
  56635         1,
  56636         soc_BRDC_FMAC_REG_0123r_fields,
  56637         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  56638         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  56639         -1,
  56640         -1,
  56641     },
  56642 #endif /* chips */
  56643 
  56644 #if defined(BCM_88675_A0)
  56645     { /* SOC_REG_INT_BRDC_FMAC_REG_0139r */
  56646         soc_block_list[23],
  56647         soc_genreg,
  56648         4,
  56649         0,
  56650         0x139,
  56651         SOC_REG_FLAG_ARRAY |
  56652                           SOC_REG_FLAG_WO |
  56653                           SOC_REG_FLAG_REG_ARRAY,
  56654         0,
  56655         10,
  56656         soc_BRDC_FMAC_REG_0139r_fields,
  56657         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  56658         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  56659         -1,
  56660         -1,
  56661     },
  56662 #endif /* chips */
  56663 
  56664 #if defined(BCM_88650_A0)
  56665     { /* SOC_REG_INT_BRDC_FMAC_REG_0140r */
  56666         soc_block_list[23],
  56667         soc_genreg,
  56668         4,
  56669         0,
  56670         0x140,
  56671         SOC_REG_FLAG_64_BITS |
  56672                           SOC_REG_FLAG_ARRAY |
  56673                           SOC_REG_FLAG_WO |
  56674                           SOC_REG_FLAG_REG_ARRAY,
  56675         0,
  56676         2,
  56677         soc_BRDC_FMAC_REG_0140r_fields,
  56678         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  56680         -1,
  56681         -1,
  56682     },
  56683 #endif /* chips */
  56684 
  56685 #if defined(BCM_88202_A0)
  56686     { /* SOC_REG_INT_BRDC_FMAC_REG_0050_BCM88202_A0r */
  56687         soc_block_list[23],
  56688         soc_genreg,
  56689         1,
  56690         0,
  56691         0x50,
  56692         SOC_REG_FLAG_WO,
  56693         0,
  56694         1,
  56695         soc_BRDC_FMAC_REG_0050_BCM88202_A0r_fields,
  56696         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56698         -1,
  56699         -1,
  56700     },
  56701 #endif /* chips */
  56702 
  56703 #if defined(BCM_88650_B0)
  56704     { /* SOC_REG_INT_BRDC_FMAC_REG_0050_BCM88650_B0r */
  56705         soc_block_list[23],
  56706         soc_genreg,
  56707         1,
  56708         0,
  56709         0x50,
  56710         SOC_REG_FLAG_WO,
  56711         0,
  56712         1,
  56713         soc_BRDC_FMAC_REG_0050_BCM88650_B0r_fields,
  56714         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56716         -1,
  56717         -1,
  56718     },
  56719 #endif /* chips */
  56720 
  56721 #if defined(BCM_88660_A0)
  56722     { /* SOC_REG_INT_BRDC_FMAC_REG_0050_BCM88660_A0r */
  56723         soc_block_list[23],
  56724         soc_genreg,
  56725         1,
  56726         0,
  56727         0x50,
  56728         SOC_REG_FLAG_WO,
  56729         0,
  56730         1,
  56731         soc_BRDC_FMAC_REG_0050_BCM88660_A0r_fields,
  56732         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56734         -1,
  56735         -1,
  56736     },
  56737 #endif /* chips */
  56738 
  56739 #if defined(BCM_88202_A0)
  56740     { /* SOC_REG_INT_BRDC_FMAC_REG_0051_BCM88202_A0r */
  56741         soc_block_list[23],
  56742         soc_genreg,
  56743         1,
  56744         0,
  56745         0x51,
  56746         SOC_REG_FLAG_WO,
  56747         0,
  56748         1,
  56749         soc_BRDC_FMAC_REG_0051_BCM88202_A0r_fields,
  56750         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56751         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56752         -1,
  56753         -1,
  56754     },
  56755 #endif /* chips */
  56756 
  56757 #if defined(BCM_88650_B0)
  56758     { /* SOC_REG_INT_BRDC_FMAC_REG_0051_BCM88650_B0r */
  56759         soc_block_list[23],
  56760         soc_genreg,
  56761         1,
  56762         0,
  56763         0x51,
  56764         SOC_REG_FLAG_WO,
  56765         0,
  56766         1,
  56767         soc_BRDC_FMAC_REG_0051_BCM88650_B0r_fields,
  56768         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56769         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56770         -1,
  56771         -1,
  56772     },
  56773 #endif /* chips */
  56774 
  56775 #if defined(BCM_88660_A0)
  56776     { /* SOC_REG_INT_BRDC_FMAC_REG_0051_BCM88660_A0r */
  56777         soc_block_list[23],
  56778         soc_genreg,
  56779         1,
  56780         0,
  56781         0x51,
  56782         SOC_REG_FLAG_WO,
  56783         0,
  56784         1,
  56785         soc_BRDC_FMAC_REG_0051_BCM88660_A0r_fields,
  56786         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  56787         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56788         -1,
  56789         -1,
  56790     },
  56791 #endif /* chips */
  56792 
  56793 #if defined(BCM_88202_A0)
  56794     { /* SOC_REG_INT_BRDC_FMAC_REG_0052_BCM88202_A0r */
  56795         soc_block_list[23],
  56796         soc_genreg,
  56797         1,
  56798         0,
  56799         0x52,
  56800         SOC_REG_FLAG_WO,
  56801         0,
  56802         1,
  56803         soc_BRDC_FMAC_REG_0052_BCM88202_A0r_fields,
  56804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56805         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56806         -1,
  56807         -1,
  56808     },
  56809 #endif /* chips */
  56810 
  56811 #if defined(BCM_88650_B0)
  56812     { /* SOC_REG_INT_BRDC_FMAC_REG_0052_BCM88650_B0r */
  56813         soc_block_list[23],
  56814         soc_genreg,
  56815         1,
  56816         0,
  56817         0x52,
  56818         SOC_REG_FLAG_WO,
  56819         0,
  56820         1,
  56821         soc_BRDC_FMAC_REG_0052_BCM88650_B0r_fields,
  56822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56823         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56824         -1,
  56825         -1,
  56826     },
  56827 #endif /* chips */
  56828 
  56829 #if defined(BCM_88202_A0)
  56830     { /* SOC_REG_INT_BRDC_FMAC_REG_0053_BCM88202_A0r */
  56831         soc_block_list[23],
  56832         soc_genreg,
  56833         1,
  56834         0,
  56835         0x53,
  56836         SOC_REG_FLAG_WO,
  56837         0,
  56838         1,
  56839         soc_BRDC_FMAC_REG_0053_BCM88202_A0r_fields,
  56840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56841         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56842         -1,
  56843         -1,
  56844     },
  56845 #endif /* chips */
  56846 
  56847 #if defined(BCM_88650_B0)
  56848     { /* SOC_REG_INT_BRDC_FMAC_REG_0053_BCM88650_B0r */
  56849         soc_block_list[23],
  56850         soc_genreg,
  56851         1,
  56852         0,
  56853         0x53,
  56854         SOC_REG_FLAG_WO,
  56855         0,
  56856         1,
  56857         soc_BRDC_FMAC_REG_0053_BCM88650_B0r_fields,
  56858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56859         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56860         -1,
  56861         -1,
  56862     },
  56863 #endif /* chips */
  56864 
  56865 #if defined(BCM_88660_A0)
  56866     { /* SOC_REG_INT_BRDC_FMAC_REG_0053_BCM88660_A0r */
  56867         soc_block_list[23],
  56868         soc_genreg,
  56869         1,
  56870         0,
  56871         0x53,
  56872         SOC_REG_FLAG_WO,
  56873         0,
  56874         1,
  56875         soc_BRDC_FMAC_REG_0053_BCM88660_A0r_fields,
  56876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56877         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  56878         -1,
  56879         -1,
  56880     },
  56881 #endif /* chips */
  56882 
  56883 #if defined(BCM_88202_A0)
  56884     { /* SOC_REG_INT_BRDC_FMAC_REG_0054_BCM88202_A0r */
  56885         soc_block_list[23],
  56886         soc_genreg,
  56887         1,
  56888         0,
  56889         0x54,
  56890         SOC_REG_FLAG_WO,
  56891         0,
  56892         2,
  56893         soc_BRDC_FMAC_REG_0054_BCM88202_A0r_fields,
  56894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56895         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  56896         -1,
  56897         -1,
  56898     },
  56899 #endif /* chips */
  56900 
  56901 #if defined(BCM_88650_B0)
  56902     { /* SOC_REG_INT_BRDC_FMAC_REG_0054_BCM88650_B0r */
  56903         soc_block_list[23],
  56904         soc_genreg,
  56905         1,
  56906         0,
  56907         0x54,
  56908         SOC_REG_FLAG_WO,
  56909         0,
  56910         2,
  56911         soc_BRDC_FMAC_REG_0054_BCM88650_B0r_fields,
  56912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56913         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  56914         -1,
  56915         -1,
  56916     },
  56917 #endif /* chips */
  56918 
  56919 #if defined(BCM_88660_A0)
  56920     { /* SOC_REG_INT_BRDC_FMAC_REG_0054_BCM88660_A0r */
  56921         soc_block_list[23],
  56922         soc_genreg,
  56923         1,
  56924         0,
  56925         0x54,
  56926         SOC_REG_FLAG_WO,
  56927         0,
  56928         2,
  56929         soc_BRDC_FMAC_REG_0054_BCM88660_A0r_fields,
  56930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56931         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  56932         -1,
  56933         -1,
  56934     },
  56935 #endif /* chips */
  56936 
  56937 #if defined(BCM_88202_A0)
  56938     { /* SOC_REG_INT_BRDC_FMAC_REG_0058_BCM88202_A0r */
  56939         soc_block_list[23],
  56940         soc_genreg,
  56941         1,
  56942         0,
  56943         0x58,
  56944         SOC_REG_FLAG_WO,
  56945         0,
  56946         1,
  56947         soc_BRDC_FMAC_REG_0058_BCM88202_A0r_fields,
  56948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56949         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56950         -1,
  56951         -1,
  56952     },
  56953 #endif /* chips */
  56954 
  56955 #if defined(BCM_88650_B0)
  56956     { /* SOC_REG_INT_BRDC_FMAC_REG_0058_BCM88650_B0r */
  56957         soc_block_list[23],
  56958         soc_genreg,
  56959         1,
  56960         0,
  56961         0x58,
  56962         SOC_REG_FLAG_WO,
  56963         0,
  56964         1,
  56965         soc_BRDC_FMAC_REG_0058_BCM88650_B0r_fields,
  56966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56967         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56968         -1,
  56969         -1,
  56970     },
  56971 #endif /* chips */
  56972 
  56973 #if defined(BCM_88660_A0)
  56974     { /* SOC_REG_INT_BRDC_FMAC_REG_0058_BCM88660_A0r */
  56975         soc_block_list[23],
  56976         soc_genreg,
  56977         1,
  56978         0,
  56979         0x58,
  56980         SOC_REG_FLAG_WO,
  56981         0,
  56982         1,
  56983         soc_BRDC_FMAC_REG_0058_BCM88660_A0r_fields,
  56984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  56985         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  56986         -1,
  56987         -1,
  56988     },
  56989 #endif /* chips */
  56990 
  56991 #if defined(BCM_88650_A0)
  56992     { /* SOC_REG_INT_BRDC_FMAC_REG_005Ar */
  56993         soc_block_list[23],
  56994         soc_genreg,
  56995         1,
  56996         0,
  56997         0x5a,
  56998         SOC_REG_FLAG_WO,
  56999         0,
  57000         1,
  57001         soc_BRDC_FMAC_REG_005Ar_fields,
  57002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57003         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57004         -1,
  57005         -1,
  57006     },
  57007 #endif /* chips */
  57008 
  57009 #if defined(BCM_88202_A0)
  57010     { /* SOC_REG_INT_BRDC_FMAC_REG_005A_BCM88202_A0r */
  57011         soc_block_list[23],
  57012         soc_genreg,
  57013         1,
  57014         0,
  57015         0x5a,
  57016         SOC_REG_FLAG_WO,
  57017         0,
  57018         1,
  57019         soc_BRDC_FMAC_REG_005A_BCM88202_A0r_fields,
  57020         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57021         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57022         -1,
  57023         -1,
  57024     },
  57025 #endif /* chips */
  57026 
  57027 #if defined(BCM_88650_B0)
  57028     { /* SOC_REG_INT_BRDC_FMAC_REG_005A_BCM88650_B0r */
  57029         soc_block_list[23],
  57030         soc_genreg,
  57031         1,
  57032         0,
  57033         0x5a,
  57034         SOC_REG_FLAG_WO,
  57035         0,
  57036         1,
  57037         soc_BRDC_FMAC_REG_005A_BCM88650_B0r_fields,
  57038         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57039         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57040         -1,
  57041         -1,
  57042     },
  57043 #endif /* chips */
  57044 
  57045 #if defined(BCM_88660_A0)
  57046     { /* SOC_REG_INT_BRDC_FMAC_REG_005A_BCM88660_A0r */
  57047         soc_block_list[23],
  57048         soc_genreg,
  57049         1,
  57050         0,
  57051         0x5a,
  57052         SOC_REG_FLAG_WO,
  57053         0,
  57054         1,
  57055         soc_BRDC_FMAC_REG_005A_BCM88660_A0r_fields,
  57056         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57057         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  57058         -1,
  57059         -1,
  57060     },
  57061 #endif /* chips */
  57062 
  57063 #if defined(BCM_88650_A0)
  57064     { /* SOC_REG_INT_BRDC_FMAC_REG_005Br */
  57065         soc_block_list[23],
  57066         soc_genreg,
  57067         1,
  57068         0,
  57069         0x5b,
  57070         SOC_REG_FLAG_WO,
  57071         0,
  57072         3,
  57073         soc_BRDC_FMAC_REG_005Br_fields,
  57074         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57075         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57076         -1,
  57077         -1,
  57078     },
  57079 #endif /* chips */
  57080 
  57081 #if defined(BCM_88202_A0)
  57082     { /* SOC_REG_INT_BRDC_FMAC_REG_005B_BCM88202_A0r */
  57083         soc_block_list[23],
  57084         soc_genreg,
  57085         1,
  57086         0,
  57087         0x5b,
  57088         SOC_REG_FLAG_WO,
  57089         0,
  57090         3,
  57091         soc_BRDC_FMAC_REG_005B_BCM88202_A0r_fields,
  57092         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57093         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57094         -1,
  57095         -1,
  57096     },
  57097 #endif /* chips */
  57098 
  57099 #if defined(BCM_88650_B0)
  57100     { /* SOC_REG_INT_BRDC_FMAC_REG_005B_BCM88650_B0r */
  57101         soc_block_list[23],
  57102         soc_genreg,
  57103         1,
  57104         0,
  57105         0x5b,
  57106         SOC_REG_FLAG_WO,
  57107         0,
  57108         3,
  57109         soc_BRDC_FMAC_REG_005B_BCM88650_B0r_fields,
  57110         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57111         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57112         -1,
  57113         -1,
  57114     },
  57115 #endif /* chips */
  57116 
  57117 #if defined(BCM_88660_A0)
  57118     { /* SOC_REG_INT_BRDC_FMAC_REG_005B_BCM88660_A0r */
  57119         soc_block_list[23],
  57120         soc_genreg,
  57121         1,
  57122         0,
  57123         0x5b,
  57124         SOC_REG_FLAG_WO,
  57125         0,
  57126         3,
  57127         soc_BRDC_FMAC_REG_005B_BCM88660_A0r_fields,
  57128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57129         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57130         -1,
  57131         -1,
  57132     },
  57133 #endif /* chips */
  57134 
  57135 #if defined(BCM_88650_A0)
  57136     { /* SOC_REG_INT_BRDC_FMAC_REG_005Cr */
  57137         soc_block_list[23],
  57138         soc_genreg,
  57139         1,
  57140         0,
  57141         0x5c,
  57142         SOC_REG_FLAG_WO,
  57143         0,
  57144         2,
  57145         soc_BRDC_FMAC_REG_005Cr_fields,
  57146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57147         SOC_RESET_MASK_DEC(0x0000c000, 0x00000000)
  57148         -1,
  57149         -1,
  57150     },
  57151 #endif /* chips */
  57152 
  57153 #if defined(BCM_88202_A0)
  57154     { /* SOC_REG_INT_BRDC_FMAC_REG_005C_BCM88202_A0r */
  57155         soc_block_list[23],
  57156         soc_genreg,
  57157         1,
  57158         0,
  57159         0x5c,
  57160         SOC_REG_FLAG_WO,
  57161         0,
  57162         2,
  57163         soc_BRDC_FMAC_REG_005C_BCM88202_A0r_fields,
  57164         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57165         SOC_RESET_MASK_DEC(0x0000c000, 0x00000000)
  57166         -1,
  57167         -1,
  57168     },
  57169 #endif /* chips */
  57170 
  57171 #if defined(BCM_88650_B0)
  57172     { /* SOC_REG_INT_BRDC_FMAC_REG_005C_BCM88650_B0r */
  57173         soc_block_list[23],
  57174         soc_genreg,
  57175         1,
  57176         0,
  57177         0x5c,
  57178         SOC_REG_FLAG_WO,
  57179         0,
  57180         2,
  57181         soc_BRDC_FMAC_REG_005C_BCM88650_B0r_fields,
  57182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57183         SOC_RESET_MASK_DEC(0x0000c000, 0x00000000)
  57184         -1,
  57185         -1,
  57186     },
  57187 #endif /* chips */
  57188 
  57189 #if defined(BCM_88660_A0)
  57190     { /* SOC_REG_INT_BRDC_FMAC_REG_005C_BCM88660_A0r */
  57191         soc_block_list[23],
  57192         soc_genreg,
  57193         1,
  57194         0,
  57195         0x5c,
  57196         SOC_REG_FLAG_WO,
  57197         0,
  57198         2,
  57199         soc_BRDC_FMAC_REG_005C_BCM88660_A0r_fields,
  57200         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57201         SOC_RESET_MASK_DEC(0x0000c000, 0x00000000)
  57202         -1,
  57203         -1,
  57204     },
  57205 #endif /* chips */
  57206 
  57207 #if defined(BCM_88202_A0)
  57208     { /* SOC_REG_INT_BRDC_FMAC_REG_0068_BCM88202_A0r */
  57209         soc_block_list[23],
  57210         soc_genreg,
  57211         1,
  57212         0,
  57213         0x68,
  57214         SOC_REG_FLAG_WO,
  57215         0,
  57216         2,
  57217         soc_BRDC_FMAC_REG_0068_BCM88202_A0r_fields,
  57218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57219         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  57220         -1,
  57221         -1,
  57222     },
  57223 #endif /* chips */
  57224 
  57225 #if defined(BCM_88650_B0)
  57226     { /* SOC_REG_INT_BRDC_FMAC_REG_0068_BCM88650_B0r */
  57227         soc_block_list[23],
  57228         soc_genreg,
  57229         1,
  57230         0,
  57231         0x68,
  57232         SOC_REG_FLAG_WO,
  57233         0,
  57234         2,
  57235         soc_BRDC_FMAC_REG_0068_BCM88650_B0r_fields,
  57236         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57237         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  57238         -1,
  57239         -1,
  57240     },
  57241 #endif /* chips */
  57242 
  57243 #if defined(BCM_88660_A0)
  57244     { /* SOC_REG_INT_BRDC_FMAC_REG_0068_BCM88660_A0r */
  57245         soc_block_list[23],
  57246         soc_genreg,
  57247         1,
  57248         0,
  57249         0x68,
  57250         SOC_REG_FLAG_WO,
  57251         0,
  57252         2,
  57253         soc_BRDC_FMAC_REG_0068_BCM88660_A0r_fields,
  57254         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57255         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  57256         -1,
  57257         -1,
  57258     },
  57259 #endif /* chips */
  57260 
  57261 #if defined(BCM_88202_A0)
  57262     { /* SOC_REG_INT_BRDC_FMAC_REG_0096_BCM88202_A0r */
  57263         soc_block_list[23],
  57264         soc_genreg,
  57265         1,
  57266         0,
  57267         0x96,
  57268         SOC_REG_FLAG_64_BITS |
  57269                           SOC_REG_FLAG_WO,
  57270         0,
  57271         1,
  57272         soc_BRDC_FMAC_REG_0096_BCM88202_A0r_fields,
  57273         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57274         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57275         -1,
  57276         -1,
  57277     },
  57278 #endif /* chips */
  57279 
  57280 #if defined(BCM_88650_B0)
  57281     { /* SOC_REG_INT_BRDC_FMAC_REG_0096_BCM88650_B0r */
  57282         soc_block_list[23],
  57283         soc_genreg,
  57284         1,
  57285         0,
  57286         0x96,
  57287         SOC_REG_FLAG_64_BITS |
  57288                           SOC_REG_FLAG_WO,
  57289         0,
  57290         1,
  57291         soc_BRDC_FMAC_REG_0096_BCM88650_B0r_fields,
  57292         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57293         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57294         -1,
  57295         -1,
  57296     },
  57297 #endif /* chips */
  57298 
  57299 #if defined(BCM_88660_A0)
  57300     { /* SOC_REG_INT_BRDC_FMAC_REG_0096_BCM88660_A0r */
  57301         soc_block_list[23],
  57302         soc_genreg,
  57303         1,
  57304         0,
  57305         0x96,
  57306         SOC_REG_FLAG_64_BITS |
  57307                           SOC_REG_FLAG_WO,
  57308         0,
  57309         1,
  57310         soc_BRDC_FMAC_REG_0096_BCM88660_A0r_fields,
  57311         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57312         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57313         -1,
  57314         -1,
  57315     },
  57316 #endif /* chips */
  57317 
  57318 #if defined(BCM_88202_A0)
  57319     { /* SOC_REG_INT_BRDC_FMAC_REG_0098_BCM88202_A0r */
  57320         soc_block_list[23],
  57321         soc_genreg,
  57322         1,
  57323         0,
  57324         0x98,
  57325         SOC_REG_FLAG_WO,
  57326         0,
  57327         8,
  57328         soc_BRDC_FMAC_REG_0098_BCM88202_A0r_fields,
  57329         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57330         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57331         -1,
  57332         -1,
  57333     },
  57334 #endif /* chips */
  57335 
  57336 #if defined(BCM_88650_B0)
  57337     { /* SOC_REG_INT_BRDC_FMAC_REG_0098_BCM88650_B0r */
  57338         soc_block_list[23],
  57339         soc_genreg,
  57340         1,
  57341         0,
  57342         0x98,
  57343         SOC_REG_FLAG_WO,
  57344         0,
  57345         8,
  57346         soc_BRDC_FMAC_REG_0098_BCM88650_B0r_fields,
  57347         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57348         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57349         -1,
  57350         -1,
  57351     },
  57352 #endif /* chips */
  57353 
  57354 #if defined(BCM_88660_A0)
  57355     { /* SOC_REG_INT_BRDC_FMAC_REG_0098_BCM88660_A0r */
  57356         soc_block_list[23],
  57357         soc_genreg,
  57358         1,
  57359         0,
  57360         0x98,
  57361         SOC_REG_FLAG_WO,
  57362         0,
  57363         8,
  57364         soc_BRDC_FMAC_REG_0098_BCM88660_A0r_fields,
  57365         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57366         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57367         -1,
  57368         -1,
  57369     },
  57370 #endif /* chips */
  57371 
  57372 #if defined(BCM_88690_B0)
  57373     { /* SOC_REG_INT_BRDC_FMAC_REG_0098_BCM88690_B0r */
  57374         soc_block_list[23],
  57375         soc_genreg,
  57376         1,
  57377         0,
  57378         0x98,
  57379         SOC_REG_FLAG_64_BITS |
  57380                           SOC_REG_FLAG_RO |
  57381                           SOC_REG_FLAG_WO,
  57382         SOC_REG_FLAG_COUNTER_FEILDS |
  57383                           SOC_REG_FLAG_INIT_ON_READ,
  57384         4,
  57385         soc_BRDC_FMAC_REG_0098_BCM88690_B0r_fields,
  57386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57387         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  57388         -1,
  57389         -1,
  57390     },
  57391 #endif /* chips */
  57392 
  57393 #if defined(BCM_88202_A0)
  57394     { /* SOC_REG_INT_BRDC_FMAC_REG_0099_BCM88202_A0r */
  57395         soc_block_list[23],
  57396         soc_genreg,
  57397         1,
  57398         0,
  57399         0x99,
  57400         SOC_REG_FLAG_WO,
  57401         0,
  57402         1,
  57403         soc_BRDC_FMAC_REG_0099_BCM88202_A0r_fields,
  57404         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57405         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57406         -1,
  57407         -1,
  57408     },
  57409 #endif /* chips */
  57410 
  57411 #if defined(BCM_88650_B0)
  57412     { /* SOC_REG_INT_BRDC_FMAC_REG_0099_BCM88650_B0r */
  57413         soc_block_list[23],
  57414         soc_genreg,
  57415         1,
  57416         0,
  57417         0x99,
  57418         SOC_REG_FLAG_WO,
  57419         0,
  57420         1,
  57421         soc_BRDC_FMAC_REG_0099_BCM88650_B0r_fields,
  57422         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57423         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57424         -1,
  57425         -1,
  57426     },
  57427 #endif /* chips */
  57428 
  57429 #if defined(BCM_88660_A0)
  57430     { /* SOC_REG_INT_BRDC_FMAC_REG_0099_BCM88660_A0r */
  57431         soc_block_list[23],
  57432         soc_genreg,
  57433         1,
  57434         0,
  57435         0x99,
  57436         SOC_REG_FLAG_WO,
  57437         0,
  57438         1,
  57439         soc_BRDC_FMAC_REG_0099_BCM88660_A0r_fields,
  57440         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57441         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57442         -1,
  57443         -1,
  57444     },
  57445 #endif /* chips */
  57446 
  57447 #if defined(BCM_88690_B0)
  57448     { /* SOC_REG_INT_BRDC_FMAC_REG_00A0r */
  57449         soc_block_list[23],
  57450         soc_genreg,
  57451         1,
  57452         0,
  57453         0xa0,
  57454         SOC_REG_FLAG_WO,
  57455         0,
  57456         1,
  57457         soc_BRDC_FMAC_REG_00A0r_fields,
  57458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57459         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  57460         -1,
  57461         -1,
  57462     },
  57463 #endif /* chips */
  57464 
  57465 #if defined(BCM_88690_B0)
  57466     { /* SOC_REG_INT_BRDC_FMAC_REG_00C2r */
  57467         soc_block_list[23],
  57468         soc_genreg,
  57469         1,
  57470         0,
  57471         0xc2,
  57472         SOC_REG_FLAG_WO,
  57473         0,
  57474         6,
  57475         soc_BRDC_FMAC_REG_00C2r_fields,
  57476         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  57477         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  57478         -1,
  57479         -1,
  57480     },
  57481 #endif /* chips */
  57482 
  57483 #if defined(BCM_88690_B0)
  57484     { /* SOC_REG_INT_BRDC_FMAC_REG_00C3r */
  57485         soc_block_list[23],
  57486         soc_genreg,
  57487         1,
  57488         0,
  57489         0xc3,
  57490         SOC_REG_FLAG_WO,
  57491         0,
  57492         3,
  57493         soc_BRDC_FMAC_REG_00C3r_fields,
  57494         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  57495         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57496         -1,
  57497         -1,
  57498     },
  57499 #endif /* chips */
  57500 
  57501 #if defined(BCM_88690_B0)
  57502     { /* SOC_REG_INT_BRDC_FMAC_REG_00F4r */
  57503         soc_block_list[23],
  57504         soc_genreg,
  57505         1,
  57506         0,
  57507         0xf4,
  57508         SOC_REG_FLAG_WO,
  57509         0,
  57510         4,
  57511         soc_BRDC_FMAC_REG_00F4r_fields,
  57512         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  57513         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57514         -1,
  57515         -1,
  57516     },
  57517 #endif /* chips */
  57518 
  57519 #if defined(BCM_83208_A0)
  57520     { /* SOC_REG_INT_BRDC_FMAC_REG_0102_BCM83208_A0r */
  57521         soc_block_list[23],
  57522         soc_genreg,
  57523         1,
  57524         0,
  57525         0x102,
  57526         SOC_REG_FLAG_WO,
  57527         0,
  57528         1,
  57529         soc_BRDC_FMAC_REG_0102_BCM83208_A0r_fields,
  57530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57531         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57532         -1,
  57533         -1,
  57534     },
  57535 #endif /* chips */
  57536 
  57537 #if defined(BCM_88375_A0)
  57538     { /* SOC_REG_INT_BRDC_FMAC_REG_0102_BCM88375_A0r */
  57539         soc_block_list[23],
  57540         soc_genreg,
  57541         1,
  57542         0,
  57543         0x102,
  57544         SOC_REG_FLAG_WO,
  57545         0,
  57546         1,
  57547         soc_BRDC_FMAC_REG_0102_BCM88375_A0r_fields,
  57548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57549         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57550         -1,
  57551         -1,
  57552     },
  57553 #endif /* chips */
  57554 
  57555 #if defined(BCM_88375_B0)
  57556     { /* SOC_REG_INT_BRDC_FMAC_REG_0102_BCM88375_B0r */
  57557         soc_block_list[23],
  57558         soc_genreg,
  57559         1,
  57560         0,
  57561         0x102,
  57562         SOC_REG_FLAG_WO,
  57563         0,
  57564         1,
  57565         soc_BRDC_FMAC_REG_0102_BCM88375_B0r_fields,
  57566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57567         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57568         -1,
  57569         -1,
  57570     },
  57571 #endif /* chips */
  57572 
  57573 #if defined(BCM_88470_A0)
  57574     { /* SOC_REG_INT_BRDC_FMAC_REG_0102_BCM88470_A0r */
  57575         soc_block_list[23],
  57576         soc_genreg,
  57577         1,
  57578         0,
  57579         0x102,
  57580         SOC_REG_FLAG_WO,
  57581         0,
  57582         1,
  57583         soc_BRDC_FMAC_REG_0102_BCM88470_A0r_fields,
  57584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57585         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57586         -1,
  57587         -1,
  57588     },
  57589 #endif /* chips */
  57590 
  57591 #if defined(BCM_88470_B0)
  57592     { /* SOC_REG_INT_BRDC_FMAC_REG_0102_BCM88470_B0r */
  57593         soc_block_list[23],
  57594         soc_genreg,
  57595         1,
  57596         0,
  57597         0x102,
  57598         SOC_REG_FLAG_WO,
  57599         0,
  57600         1,
  57601         soc_BRDC_FMAC_REG_0102_BCM88470_B0r_fields,
  57602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57603         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57604         -1,
  57605         -1,
  57606     },
  57607 #endif /* chips */
  57608 
  57609 #if defined(BCM_88675_B0)
  57610     { /* SOC_REG_INT_BRDC_FMAC_REG_0102_BCM88675_B0r */
  57611         soc_block_list[23],
  57612         soc_genreg,
  57613         1,
  57614         0,
  57615         0x102,
  57616         SOC_REG_FLAG_WO,
  57617         0,
  57618         1,
  57619         soc_BRDC_FMAC_REG_0102_BCM88675_B0r_fields,
  57620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57621         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57622         -1,
  57623         -1,
  57624     },
  57625 #endif /* chips */
  57626 
  57627 #if defined(BCM_88680_A0)
  57628     { /* SOC_REG_INT_BRDC_FMAC_REG_0102_BCM88680_A0r */
  57629         soc_block_list[23],
  57630         soc_genreg,
  57631         1,
  57632         0,
  57633         0x102,
  57634         SOC_REG_FLAG_WO,
  57635         0,
  57636         1,
  57637         soc_BRDC_FMAC_REG_0102_BCM88680_A0r_fields,
  57638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  57639         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  57640         -1,
  57641         -1,
  57642     },
  57643 #endif /* chips */
  57644 
  57645 #if defined(BCM_88375_A0)
  57646     { /* SOC_REG_INT_BRDC_FMAC_REG_0116_BCM88375_A0r */
  57647         soc_block_list[23],
  57648         soc_genreg,
  57649         1,
  57650         0,
  57651         0x116,
  57652         SOC_REG_FLAG_64_BITS |
  57653                           SOC_REG_FLAG_WO,
  57654         0,
  57655         1,
  57656         soc_BRDC_FMAC_REG_0116_BCM88375_A0r_fields,
  57657         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57658         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57659         -1,
  57660         -1,
  57661     },
  57662 #endif /* chips */
  57663 
  57664 #if defined(BCM_88375_B0)
  57665     { /* SOC_REG_INT_BRDC_FMAC_REG_0116_BCM88375_B0r */
  57666         soc_block_list[23],
  57667         soc_genreg,
  57668         1,
  57669         0,
  57670         0x116,
  57671         SOC_REG_FLAG_64_BITS |
  57672                           SOC_REG_FLAG_WO,
  57673         0,
  57674         1,
  57675         soc_BRDC_FMAC_REG_0116_BCM88375_B0r_fields,
  57676         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57677         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57678         -1,
  57679         -1,
  57680     },
  57681 #endif /* chips */
  57682 
  57683 #if defined(BCM_88675_B0)
  57684     { /* SOC_REG_INT_BRDC_FMAC_REG_0116_BCM88675_B0r */
  57685         soc_block_list[23],
  57686         soc_genreg,
  57687         1,
  57688         0,
  57689         0x116,
  57690         SOC_REG_FLAG_64_BITS |
  57691                           SOC_REG_FLAG_WO,
  57692         0,
  57693         1,
  57694         soc_BRDC_FMAC_REG_0116_BCM88675_B0r_fields,
  57695         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57696         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57697         -1,
  57698         -1,
  57699     },
  57700 #endif /* chips */
  57701 
  57702 #if defined(BCM_88680_A0)
  57703     { /* SOC_REG_INT_BRDC_FMAC_REG_0116_BCM88680_A0r */
  57704         soc_block_list[23],
  57705         soc_genreg,
  57706         1,
  57707         0,
  57708         0x116,
  57709         SOC_REG_FLAG_64_BITS |
  57710                           SOC_REG_FLAG_WO,
  57711         0,
  57712         1,
  57713         soc_BRDC_FMAC_REG_0116_BCM88680_A0r_fields,
  57714         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57715         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57716         -1,
  57717         -1,
  57718     },
  57719 #endif /* chips */
  57720 
  57721 #if defined(BCM_88375_A0)
  57722     { /* SOC_REG_INT_BRDC_FMAC_REG_0118_BCM88375_A0r */
  57723         soc_block_list[23],
  57724         soc_genreg,
  57725         1,
  57726         0,
  57727         0x118,
  57728         SOC_REG_FLAG_WO,
  57729         0,
  57730         8,
  57731         soc_BRDC_FMAC_REG_0118_BCM88375_A0r_fields,
  57732         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57733         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57734         -1,
  57735         -1,
  57736     },
  57737 #endif /* chips */
  57738 
  57739 #if defined(BCM_88375_B0)
  57740     { /* SOC_REG_INT_BRDC_FMAC_REG_0118_BCM88375_B0r */
  57741         soc_block_list[23],
  57742         soc_genreg,
  57743         1,
  57744         0,
  57745         0x118,
  57746         SOC_REG_FLAG_WO,
  57747         0,
  57748         8,
  57749         soc_BRDC_FMAC_REG_0118_BCM88375_B0r_fields,
  57750         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57751         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57752         -1,
  57753         -1,
  57754     },
  57755 #endif /* chips */
  57756 
  57757 #if defined(BCM_88675_B0)
  57758     { /* SOC_REG_INT_BRDC_FMAC_REG_0118_BCM88675_B0r */
  57759         soc_block_list[23],
  57760         soc_genreg,
  57761         1,
  57762         0,
  57763         0x118,
  57764         SOC_REG_FLAG_WO,
  57765         0,
  57766         8,
  57767         soc_BRDC_FMAC_REG_0118_BCM88675_B0r_fields,
  57768         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57769         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57770         -1,
  57771         -1,
  57772     },
  57773 #endif /* chips */
  57774 
  57775 #if defined(BCM_88680_A0)
  57776     { /* SOC_REG_INT_BRDC_FMAC_REG_0118_BCM88680_A0r */
  57777         soc_block_list[23],
  57778         soc_genreg,
  57779         1,
  57780         0,
  57781         0x118,
  57782         SOC_REG_FLAG_WO,
  57783         0,
  57784         8,
  57785         soc_BRDC_FMAC_REG_0118_BCM88680_A0r_fields,
  57786         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57787         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57788         -1,
  57789         -1,
  57790     },
  57791 #endif /* chips */
  57792 
  57793 #if defined(BCM_88375_A0)
  57794     { /* SOC_REG_INT_BRDC_FMAC_REG_0119_BCM88375_A0r */
  57795         soc_block_list[23],
  57796         soc_genreg,
  57797         1,
  57798         0,
  57799         0x119,
  57800         SOC_REG_FLAG_WO,
  57801         0,
  57802         1,
  57803         soc_BRDC_FMAC_REG_0119_BCM88375_A0r_fields,
  57804         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57805         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57806         -1,
  57807         -1,
  57808     },
  57809 #endif /* chips */
  57810 
  57811 #if defined(BCM_88375_B0)
  57812     { /* SOC_REG_INT_BRDC_FMAC_REG_0119_BCM88375_B0r */
  57813         soc_block_list[23],
  57814         soc_genreg,
  57815         1,
  57816         0,
  57817         0x119,
  57818         SOC_REG_FLAG_WO,
  57819         0,
  57820         1,
  57821         soc_BRDC_FMAC_REG_0119_BCM88375_B0r_fields,
  57822         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57823         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57824         -1,
  57825         -1,
  57826     },
  57827 #endif /* chips */
  57828 
  57829 #if defined(BCM_88675_B0)
  57830     { /* SOC_REG_INT_BRDC_FMAC_REG_0119_BCM88675_B0r */
  57831         soc_block_list[23],
  57832         soc_genreg,
  57833         1,
  57834         0,
  57835         0x119,
  57836         SOC_REG_FLAG_WO,
  57837         0,
  57838         1,
  57839         soc_BRDC_FMAC_REG_0119_BCM88675_B0r_fields,
  57840         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57841         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57842         -1,
  57843         -1,
  57844     },
  57845 #endif /* chips */
  57846 
  57847 #if defined(BCM_88680_A0)
  57848     { /* SOC_REG_INT_BRDC_FMAC_REG_0119_BCM88680_A0r */
  57849         soc_block_list[23],
  57850         soc_genreg,
  57851         1,
  57852         0,
  57853         0x119,
  57854         SOC_REG_FLAG_WO,
  57855         0,
  57856         1,
  57857         soc_BRDC_FMAC_REG_0119_BCM88680_A0r_fields,
  57858         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57859         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57860         -1,
  57861         -1,
  57862     },
  57863 #endif /* chips */
  57864 
  57865 #if defined(BCM_88470_A0)
  57866     { /* SOC_REG_INT_BRDC_FMAC_REG_011Ar */
  57867         soc_block_list[23],
  57868         soc_genreg,
  57869         1,
  57870         0,
  57871         0x11a,
  57872         SOC_REG_FLAG_64_BITS |
  57873                           SOC_REG_FLAG_WO,
  57874         0,
  57875         1,
  57876         soc_BRDC_FMAC_REG_011Ar_fields,
  57877         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57878         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57879         -1,
  57880         -1,
  57881     },
  57882 #endif /* chips */
  57883 
  57884 #if defined(BCM_88470_B0)
  57885     { /* SOC_REG_INT_BRDC_FMAC_REG_011A_BCM88470_B0r */
  57886         soc_block_list[23],
  57887         soc_genreg,
  57888         1,
  57889         0,
  57890         0x11a,
  57891         SOC_REG_FLAG_64_BITS |
  57892                           SOC_REG_FLAG_WO,
  57893         0,
  57894         1,
  57895         soc_BRDC_FMAC_REG_011A_BCM88470_B0r_fields,
  57896         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  57897         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  57898         -1,
  57899         -1,
  57900     },
  57901 #endif /* chips */
  57902 
  57903 #if defined(BCM_83208_A0)
  57904     { /* SOC_REG_INT_BRDC_FMAC_REG_011Cr */
  57905         soc_block_list[23],
  57906         soc_genreg,
  57907         1,
  57908         0,
  57909         0x11c,
  57910         SOC_REG_FLAG_WO,
  57911         0,
  57912         5,
  57913         soc_BRDC_FMAC_REG_011Cr_fields,
  57914         SOC_RESET_VAL_DEC(0x00000055, 0x00000000)
  57915         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  57916         -1,
  57917         -1,
  57918     },
  57919 #endif /* chips */
  57920 
  57921 #if defined(BCM_88470_A0)
  57922     { /* SOC_REG_INT_BRDC_FMAC_REG_011C_BCM88470_A0r */
  57923         soc_block_list[23],
  57924         soc_genreg,
  57925         1,
  57926         0,
  57927         0x11c,
  57928         SOC_REG_FLAG_WO,
  57929         0,
  57930         8,
  57931         soc_BRDC_FMAC_REG_011C_BCM88470_A0r_fields,
  57932         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57933         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57934         -1,
  57935         -1,
  57936     },
  57937 #endif /* chips */
  57938 
  57939 #if defined(BCM_88470_B0)
  57940     { /* SOC_REG_INT_BRDC_FMAC_REG_011C_BCM88470_B0r */
  57941         soc_block_list[23],
  57942         soc_genreg,
  57943         1,
  57944         0,
  57945         0x11c,
  57946         SOC_REG_FLAG_WO,
  57947         0,
  57948         8,
  57949         soc_BRDC_FMAC_REG_011C_BCM88470_B0r_fields,
  57950         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  57951         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  57952         -1,
  57953         -1,
  57954     },
  57955 #endif /* chips */
  57956 
  57957 #if defined(BCM_88470_A0)
  57958     { /* SOC_REG_INT_BRDC_FMAC_REG_011Dr */
  57959         soc_block_list[23],
  57960         soc_genreg,
  57961         1,
  57962         0,
  57963         0x11d,
  57964         SOC_REG_FLAG_WO,
  57965         0,
  57966         1,
  57967         soc_BRDC_FMAC_REG_011Dr_fields,
  57968         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57969         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57970         -1,
  57971         -1,
  57972     },
  57973 #endif /* chips */
  57974 
  57975 #if defined(BCM_88470_B0)
  57976     { /* SOC_REG_INT_BRDC_FMAC_REG_011D_BCM88470_B0r */
  57977         soc_block_list[23],
  57978         soc_genreg,
  57979         1,
  57980         0,
  57981         0x11d,
  57982         SOC_REG_FLAG_WO,
  57983         0,
  57984         1,
  57985         soc_BRDC_FMAC_REG_011D_BCM88470_B0r_fields,
  57986         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  57987         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  57988         -1,
  57989         -1,
  57990     },
  57991 #endif /* chips */
  57992 
  57993 #if defined(BCM_83208_A0)
  57994     { /* SOC_REG_INT_BRDC_FMAC_REG_012Ar */
  57995         soc_block_list[23],
  57996         soc_genreg,
  57997         1,
  57998         0,
  57999         0x12a,
  58000         SOC_REG_FLAG_64_BITS |
  58001                           SOC_REG_FLAG_WO,
  58002         0,
  58003         1,
  58004         soc_BRDC_FMAC_REG_012Ar_fields,
  58005         SOC_RESET_VAL_DEC(0x55555555, 0x01555555)
  58006         SOC_RESET_MASK_DEC(0xffffffff, 0x03ffffff)
  58007         -1,
  58008         -1,
  58009     },
  58010 #endif /* chips */
  58011 
  58012 #if defined(BCM_83208_A0)
  58013     { /* SOC_REG_INT_BRDC_FMAC_REG_012Cr */
  58014         soc_block_list[23],
  58015         soc_genreg,
  58016         1,
  58017         0,
  58018         0x12c,
  58019         SOC_REG_FLAG_WO,
  58020         0,
  58021         8,
  58022         soc_BRDC_FMAC_REG_012Cr_fields,
  58023         SOC_RESET_VAL_DEC(0x000000e0, 0x00000000)
  58024         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  58025         -1,
  58026         -1,
  58027     },
  58028 #endif /* chips */
  58029 
  58030 #if defined(BCM_83208_A0)
  58031     { /* SOC_REG_INT_BRDC_FMAC_REG_012Dr */
  58032         soc_block_list[23],
  58033         soc_genreg,
  58034         1,
  58035         0,
  58036         0x12d,
  58037         SOC_REG_FLAG_WO,
  58038         0,
  58039         1,
  58040         soc_BRDC_FMAC_REG_012Dr_fields,
  58041         SOC_RESET_VAL_DEC(0x000001f4, 0x00000000)
  58042         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  58043         -1,
  58044         -1,
  58045     },
  58046 #endif /* chips */
  58047 
  58048 #if defined(BCM_88375_A0)
  58049     { /* SOC_REG_INT_BRDC_FMAC_REG_0139_BCM88375_A0r */
  58050         soc_block_list[23],
  58051         soc_genreg,
  58052         4,
  58053         0,
  58054         0x139,
  58055         SOC_REG_FLAG_ARRAY |
  58056                           SOC_REG_FLAG_WO |
  58057                           SOC_REG_FLAG_REG_ARRAY,
  58058         0,
  58059         10,
  58060         soc_BRDC_FMAC_REG_0139_BCM88375_A0r_fields,
  58061         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  58062         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58063         -1,
  58064         -1,
  58065     },
  58066 #endif /* chips */
  58067 
  58068 #if defined(BCM_88375_B0)
  58069     { /* SOC_REG_INT_BRDC_FMAC_REG_0139_BCM88375_B0r */
  58070         soc_block_list[23],
  58071         soc_genreg,
  58072         4,
  58073         0,
  58074         0x139,
  58075         SOC_REG_FLAG_ARRAY |
  58076                           SOC_REG_FLAG_WO |
  58077                           SOC_REG_FLAG_REG_ARRAY,
  58078         0,
  58079         10,
  58080         soc_BRDC_FMAC_REG_0139_BCM88375_B0r_fields,
  58081         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  58082         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58083         -1,
  58084         -1,
  58085     },
  58086 #endif /* chips */
  58087 
  58088 #if defined(BCM_88675_B0)
  58089     { /* SOC_REG_INT_BRDC_FMAC_REG_0139_BCM88675_B0r */
  58090         soc_block_list[23],
  58091         soc_genreg,
  58092         4,
  58093         0,
  58094         0x139,
  58095         SOC_REG_FLAG_ARRAY |
  58096                           SOC_REG_FLAG_WO |
  58097                           SOC_REG_FLAG_REG_ARRAY,
  58098         0,
  58099         10,
  58100         soc_BRDC_FMAC_REG_0139_BCM88675_B0r_fields,
  58101         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  58102         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58103         -1,
  58104         -1,
  58105     },
  58106 #endif /* chips */
  58107 
  58108 #if defined(BCM_88680_A0)
  58109     { /* SOC_REG_INT_BRDC_FMAC_REG_0139_BCM88680_A0r */
  58110         soc_block_list[23],
  58111         soc_genreg,
  58112         4,
  58113         0,
  58114         0x139,
  58115         SOC_REG_FLAG_ARRAY |
  58116                           SOC_REG_FLAG_WO |
  58117                           SOC_REG_FLAG_REG_ARRAY,
  58118         0,
  58119         10,
  58120         soc_BRDC_FMAC_REG_0139_BCM88680_A0r_fields,
  58121         SOC_RESET_VAL_DEC(0x000878c4, 0x00000000)
  58122         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  58123         -1,
  58124         -1,
  58125     },
  58126 #endif /* chips */
  58127 
  58128 #if defined(BCM_88202_A0)
  58129     { /* SOC_REG_INT_BRDC_FMAC_REG_0140_BCM88202_A0r */
  58130         soc_block_list[23],
  58131         soc_genreg,
  58132         4,
  58133         0,
  58134         0x140,
  58135         SOC_REG_FLAG_64_BITS |
  58136                           SOC_REG_FLAG_ARRAY |
  58137                           SOC_REG_FLAG_WO |
  58138                           SOC_REG_FLAG_REG_ARRAY,
  58139         0,
  58140         2,
  58141         soc_BRDC_FMAC_REG_0140_BCM88202_A0r_fields,
  58142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58143         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  58144         -1,
  58145         -1,
  58146     },
  58147 #endif /* chips */
  58148 
  58149 #if defined(BCM_88650_B0)
  58150     { /* SOC_REG_INT_BRDC_FMAC_REG_0140_BCM88650_B0r */
  58151         soc_block_list[23],
  58152         soc_genreg,
  58153         4,
  58154         0,
  58155         0x140,
  58156         SOC_REG_FLAG_64_BITS |
  58157                           SOC_REG_FLAG_ARRAY |
  58158                           SOC_REG_FLAG_WO |
  58159                           SOC_REG_FLAG_REG_ARRAY,
  58160         0,
  58161         2,
  58162         soc_BRDC_FMAC_REG_0140_BCM88650_B0r_fields,
  58163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58164         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  58165         -1,
  58166         -1,
  58167     },
  58168 #endif /* chips */
  58169 
  58170 #if defined(BCM_88660_A0)
  58171     { /* SOC_REG_INT_BRDC_FMAC_REG_0140_BCM88660_A0r */
  58172         soc_block_list[23],
  58173         soc_genreg,
  58174         4,
  58175         0,
  58176         0x140,
  58177         SOC_REG_FLAG_64_BITS |
  58178                           SOC_REG_FLAG_ARRAY |
  58179                           SOC_REG_FLAG_WO |
  58180                           SOC_REG_FLAG_REG_ARRAY,
  58181         0,
  58182         2,
  58183         soc_BRDC_FMAC_REG_0140_BCM88660_A0r_fields,
  58184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  58186         -1,
  58187         -1,
  58188     },
  58189 #endif /* chips */
  58190 
  58191 #if defined(BCM_88650_A0)
  58192     { /* SOC_REG_INT_BRDC_FMAC_REG_01A8r */
  58193         soc_block_list[23],
  58194         soc_genreg,
  58195         4,
  58196         0,
  58197         0x1a8,
  58198         SOC_REG_FLAG_ARRAY |
  58199                           SOC_REG_FLAG_WO |
  58200                           SOC_REG_FLAG_REG_ARRAY,
  58201         0,
  58202         1,
  58203         soc_BRDC_FMAC_REG_01A8r_fields,
  58204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58205         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58206         -1,
  58207         -1,
  58208     },
  58209 #endif /* chips */
  58210 
  58211 #if defined(BCM_88202_A0)
  58212     { /* SOC_REG_INT_BRDC_FMAC_REG_01A8_BCM88202_A0r */
  58213         soc_block_list[23],
  58214         soc_genreg,
  58215         4,
  58216         0,
  58217         0x1a8,
  58218         SOC_REG_FLAG_ARRAY |
  58219                           SOC_REG_FLAG_WO |
  58220                           SOC_REG_FLAG_REG_ARRAY,
  58221         0,
  58222         1,
  58223         soc_BRDC_FMAC_REG_01A8_BCM88202_A0r_fields,
  58224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58225         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58226         -1,
  58227         -1,
  58228     },
  58229 #endif /* chips */
  58230 
  58231 #if defined(BCM_88650_B0)
  58232     { /* SOC_REG_INT_BRDC_FMAC_REG_01A8_BCM88650_B0r */
  58233         soc_block_list[23],
  58234         soc_genreg,
  58235         4,
  58236         0,
  58237         0x1a8,
  58238         SOC_REG_FLAG_ARRAY |
  58239                           SOC_REG_FLAG_WO |
  58240                           SOC_REG_FLAG_REG_ARRAY,
  58241         0,
  58242         1,
  58243         soc_BRDC_FMAC_REG_01A8_BCM88650_B0r_fields,
  58244         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58245         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58246         -1,
  58247         -1,
  58248     },
  58249 #endif /* chips */
  58250 
  58251 #if defined(BCM_88660_A0)
  58252     { /* SOC_REG_INT_BRDC_FMAC_REG_01A8_BCM88660_A0r */
  58253         soc_block_list[23],
  58254         soc_genreg,
  58255         4,
  58256         0,
  58257         0x1a8,
  58258         SOC_REG_FLAG_ARRAY |
  58259                           SOC_REG_FLAG_WO |
  58260                           SOC_REG_FLAG_REG_ARRAY,
  58261         0,
  58262         1,
  58263         soc_BRDC_FMAC_REG_01A8_BCM88660_A0r_fields,
  58264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  58266         -1,
  58267         -1,
  58268     },
  58269 #endif /* chips */
  58270 
  58271 #if defined(BCM_88650_A0)
  58272     { /* SOC_REG_INT_BRDC_FMAC_REG_01ACr */
  58273         soc_block_list[23],
  58274         soc_genreg,
  58275         4,
  58276         0,
  58277         0x1ac,
  58278         SOC_REG_FLAG_ARRAY |
  58279                           SOC_REG_FLAG_WO |
  58280                           SOC_REG_FLAG_REG_ARRAY,
  58281         0,
  58282         3,
  58283         soc_BRDC_FMAC_REG_01ACr_fields,
  58284         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  58285         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  58286         -1,
  58287         -1,
  58288     },
  58289 #endif /* chips */
  58290 
  58291 #if defined(BCM_88202_A0)
  58292     { /* SOC_REG_INT_BRDC_FMAC_REG_01AC_BCM88202_A0r */
  58293         soc_block_list[23],
  58294         soc_genreg,
  58295         4,
  58296         0,
  58297         0x1ac,
  58298         SOC_REG_FLAG_ARRAY |
  58299                           SOC_REG_FLAG_WO |
  58300                           SOC_REG_FLAG_REG_ARRAY,
  58301         0,
  58302         3,
  58303         soc_BRDC_FMAC_REG_01AC_BCM88202_A0r_fields,
  58304         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  58305         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  58306         -1,
  58307         -1,
  58308     },
  58309 #endif /* chips */
  58310 
  58311 #if defined(BCM_88650_B0)
  58312     { /* SOC_REG_INT_BRDC_FMAC_REG_01AC_BCM88650_B0r */
  58313         soc_block_list[23],
  58314         soc_genreg,
  58315         4,
  58316         0,
  58317         0x1ac,
  58318         SOC_REG_FLAG_ARRAY |
  58319                           SOC_REG_FLAG_WO |
  58320                           SOC_REG_FLAG_REG_ARRAY,
  58321         0,
  58322         3,
  58323         soc_BRDC_FMAC_REG_01AC_BCM88650_B0r_fields,
  58324         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  58325         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  58326         -1,
  58327         -1,
  58328     },
  58329 #endif /* chips */
  58330 
  58331 #if defined(BCM_88660_A0)
  58332     { /* SOC_REG_INT_BRDC_FMAC_REG_01AC_BCM88660_A0r */
  58333         soc_block_list[23],
  58334         soc_genreg,
  58335         4,
  58336         0,
  58337         0x1ac,
  58338         SOC_REG_FLAG_ARRAY |
  58339                           SOC_REG_FLAG_WO |
  58340                           SOC_REG_FLAG_REG_ARRAY,
  58341         0,
  58342         3,
  58343         soc_BRDC_FMAC_REG_01AC_BCM88660_A0r_fields,
  58344         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  58345         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  58346         -1,
  58347         -1,
  58348     },
  58349 #endif /* chips */
  58350 
  58351 #if defined(BCM_88650_A0)
  58352     { /* SOC_REG_INT_BRDC_FMAC_REG_01FAr */
  58353         soc_block_list[23],
  58354         soc_genreg,
  58355         1,
  58356         0,
  58357         0x1fa,
  58358         SOC_REG_FLAG_WO,
  58359         0,
  58360         6,
  58361         soc_BRDC_FMAC_REG_01FAr_fields,
  58362         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58363         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  58364         -1,
  58365         -1,
  58366     },
  58367 #endif /* chips */
  58368 
  58369 #if defined(BCM_88202_A0)
  58370     { /* SOC_REG_INT_BRDC_FMAC_REG_01FA_BCM88202_A0r */
  58371         soc_block_list[23],
  58372         soc_genreg,
  58373         1,
  58374         0,
  58375         0x1fa,
  58376         SOC_REG_FLAG_64_BITS |
  58377                           SOC_REG_FLAG_WO,
  58378         0,
  58379         6,
  58380         soc_BRDC_FMAC_REG_01FA_BCM88202_A0r_fields,
  58381         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58382         SOC_RESET_MASK_DEC(0xffffffff, 0x00003fff)
  58383         -1,
  58384         -1,
  58385     },
  58386 #endif /* chips */
  58387 
  58388 #if defined(BCM_88650_B0)
  58389     { /* SOC_REG_INT_BRDC_FMAC_REG_01FA_BCM88650_B0r */
  58390         soc_block_list[23],
  58391         soc_genreg,
  58392         1,
  58393         0,
  58394         0x1fa,
  58395         SOC_REG_FLAG_WO,
  58396         0,
  58397         6,
  58398         soc_BRDC_FMAC_REG_01FA_BCM88650_B0r_fields,
  58399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58400         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  58401         -1,
  58402         -1,
  58403     },
  58404 #endif /* chips */
  58405 
  58406 #if defined(BCM_88660_A0)
  58407     { /* SOC_REG_INT_BRDC_FMAC_REG_01FA_BCM88660_A0r */
  58408         soc_block_list[23],
  58409         soc_genreg,
  58410         1,
  58411         0,
  58412         0x1fa,
  58413         SOC_REG_FLAG_WO,
  58414         0,
  58415         6,
  58416         soc_BRDC_FMAC_REG_01FA_BCM88660_A0r_fields,
  58417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58418         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  58419         -1,
  58420         -1,
  58421     },
  58422 #endif /* chips */
  58423 
  58424 #if defined(BCM_88675_A0)
  58425     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDRr */
  58426         soc_block_list[23],
  58427         soc_genreg,
  58428         1,
  58429         0,
  58430         0x85,
  58431         SOC_REG_FLAG_WO,
  58432         0,
  58433         2,
  58434         soc_BRDC_FMAC_RESERVED_MIRROR_ADDRr_fields,
  58435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58436         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58437         -1,
  58438         -1,
  58439     },
  58440 #endif /* chips */
  58441 
  58442 #if defined(BCM_83208_A0)
  58443     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM83208_A0r */
  58444         soc_block_list[23],
  58445         soc_genreg,
  58446         1,
  58447         0,
  58448         0x85,
  58449         SOC_REG_FLAG_WO,
  58450         0,
  58451         2,
  58452         soc_DRCBROADCAST_REG_0085_BCM83207_A0r_fields,
  58453         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58454         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58455         -1,
  58456         -1,
  58457     },
  58458 #endif /* chips */
  58459 
  58460 #if defined(BCM_88375_A0)
  58461     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88375_A0r */
  58462         soc_block_list[23],
  58463         soc_genreg,
  58464         1,
  58465         0,
  58466         0x85,
  58467         SOC_REG_FLAG_WO,
  58468         0,
  58469         2,
  58470         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88375_A0r_fields,
  58471         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58472         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58473         -1,
  58474         -1,
  58475     },
  58476 #endif /* chips */
  58477 
  58478 #if defined(BCM_88375_B0)
  58479     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88375_B0r */
  58480         soc_block_list[23],
  58481         soc_genreg,
  58482         1,
  58483         0,
  58484         0x85,
  58485         SOC_REG_FLAG_WO,
  58486         0,
  58487         2,
  58488         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88375_B0r_fields,
  58489         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58490         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58491         -1,
  58492         -1,
  58493     },
  58494 #endif /* chips */
  58495 
  58496 #if defined(BCM_88470_A0)
  58497     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88470_A0r */
  58498         soc_block_list[23],
  58499         soc_genreg,
  58500         1,
  58501         0,
  58502         0x85,
  58503         SOC_REG_FLAG_WO,
  58504         0,
  58505         2,
  58506         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88470_A0r_fields,
  58507         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58508         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58509         -1,
  58510         -1,
  58511     },
  58512 #endif /* chips */
  58513 
  58514 #if defined(BCM_88470_B0)
  58515     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88470_B0r */
  58516         soc_block_list[23],
  58517         soc_genreg,
  58518         1,
  58519         0,
  58520         0x85,
  58521         SOC_REG_FLAG_WO,
  58522         0,
  58523         2,
  58524         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88470_B0r_fields,
  58525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58526         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58527         -1,
  58528         -1,
  58529     },
  58530 #endif /* chips */
  58531 
  58532 #if defined(BCM_88675_B0)
  58533     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88675_B0r */
  58534         soc_block_list[23],
  58535         soc_genreg,
  58536         1,
  58537         0,
  58538         0x85,
  58539         SOC_REG_FLAG_WO,
  58540         0,
  58541         2,
  58542         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88675_B0r_fields,
  58543         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58544         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58545         -1,
  58546         -1,
  58547     },
  58548 #endif /* chips */
  58549 
  58550 #if defined(BCM_88680_A0)
  58551     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88680_A0r */
  58552         soc_block_list[23],
  58553         soc_genreg,
  58554         1,
  58555         0,
  58556         0x85,
  58557         SOC_REG_FLAG_WO,
  58558         0,
  58559         2,
  58560         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88680_A0r_fields,
  58561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58562         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58563         -1,
  58564         -1,
  58565     },
  58566 #endif /* chips */
  58567 
  58568 #if defined(BCM_88690_A0)
  58569     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88690_A0r */
  58570         soc_block_list[23],
  58571         soc_genreg,
  58572         1,
  58573         0,
  58574         0x85,
  58575         SOC_REG_FLAG_WO,
  58576         0,
  58577         2,
  58578         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88690_A0r_fields,
  58579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58580         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58581         -1,
  58582         -1,
  58583     },
  58584 #endif /* chips */
  58585 
  58586 #if defined(BCM_88690_B0)
  58587     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88690_B0r */
  58588         soc_block_list[23],
  58589         soc_genreg,
  58590         1,
  58591         0,
  58592         0x85,
  58593         SOC_REG_FLAG_WO,
  58594         0,
  58595         2,
  58596         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
  58597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58598         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58599         -1,
  58600         -1,
  58601     },
  58602 #endif /* chips */
  58603 
  58604 #if defined(BCM_88790_A0)
  58605     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88790_A0r */
  58606         soc_block_list[23],
  58607         soc_genreg,
  58608         1,
  58609         0,
  58610         0x85,
  58611         SOC_REG_FLAG_WO,
  58612         0,
  58613         2,
  58614         soc_BRDC_FMAC_RESERVED_MIRROR_ADDR_BCM88790_A0r_fields,
  58615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58616         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  58617         -1,
  58618         -1,
  58619     },
  58620 #endif /* chips */
  58621 
  58622 #if defined(BCM_88675_A0)
  58623     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCDr */
  58624         soc_block_list[23],
  58625         soc_genreg,
  58626         1,
  58627         0,
  58628         0xae,
  58629         SOC_REG_FLAG_WO,
  58630         0,
  58631         6,
  58632         soc_BRDC_FMAC_RESERVED_MTCDr_fields,
  58633         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58634         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58635         -1,
  58636         -1,
  58637     },
  58638 #endif /* chips */
  58639 
  58640 #if defined(BCM_83208_A0)
  58641     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM83208_A0r */
  58642         soc_block_list[23],
  58643         soc_genreg,
  58644         1,
  58645         0,
  58646         0xae,
  58647         SOC_REG_FLAG_WO,
  58648         0,
  58649         6,
  58650         soc_BRDC_FMAC_RESERVED_MTCD_BCM83208_A0r_fields,
  58651         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58652         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58653         -1,
  58654         -1,
  58655     },
  58656 #endif /* chips */
  58657 
  58658 #if defined(BCM_88375_A0)
  58659     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88375_A0r */
  58660         soc_block_list[23],
  58661         soc_genreg,
  58662         1,
  58663         0,
  58664         0xae,
  58665         SOC_REG_FLAG_WO,
  58666         0,
  58667         6,
  58668         soc_BRDC_FMAC_RESERVED_MTCD_BCM88375_A0r_fields,
  58669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58670         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58671         -1,
  58672         -1,
  58673     },
  58674 #endif /* chips */
  58675 
  58676 #if defined(BCM_88375_B0)
  58677     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88375_B0r */
  58678         soc_block_list[23],
  58679         soc_genreg,
  58680         1,
  58681         0,
  58682         0xae,
  58683         SOC_REG_FLAG_WO,
  58684         0,
  58685         6,
  58686         soc_BRDC_FMAC_RESERVED_MTCD_BCM88375_B0r_fields,
  58687         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58688         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58689         -1,
  58690         -1,
  58691     },
  58692 #endif /* chips */
  58693 
  58694 #if defined(BCM_88470_A0)
  58695     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88470_A0r */
  58696         soc_block_list[23],
  58697         soc_genreg,
  58698         1,
  58699         0,
  58700         0xae,
  58701         SOC_REG_FLAG_WO,
  58702         0,
  58703         6,
  58704         soc_BRDC_FMAC_RESERVED_MTCD_BCM88470_A0r_fields,
  58705         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58706         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58707         -1,
  58708         -1,
  58709     },
  58710 #endif /* chips */
  58711 
  58712 #if defined(BCM_88470_B0)
  58713     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88470_B0r */
  58714         soc_block_list[23],
  58715         soc_genreg,
  58716         1,
  58717         0,
  58718         0xae,
  58719         SOC_REG_FLAG_WO,
  58720         0,
  58721         6,
  58722         soc_BRDC_FMAC_RESERVED_MTCD_BCM88470_B0r_fields,
  58723         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58724         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58725         -1,
  58726         -1,
  58727     },
  58728 #endif /* chips */
  58729 
  58730 #if defined(BCM_88675_B0)
  58731     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88675_B0r */
  58732         soc_block_list[23],
  58733         soc_genreg,
  58734         1,
  58735         0,
  58736         0xae,
  58737         SOC_REG_FLAG_WO,
  58738         0,
  58739         6,
  58740         soc_BRDC_FMAC_RESERVED_MTCD_BCM88675_B0r_fields,
  58741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58742         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58743         -1,
  58744         -1,
  58745     },
  58746 #endif /* chips */
  58747 
  58748 #if defined(BCM_88680_A0)
  58749     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88680_A0r */
  58750         soc_block_list[23],
  58751         soc_genreg,
  58752         1,
  58753         0,
  58754         0xae,
  58755         SOC_REG_FLAG_WO,
  58756         0,
  58757         6,
  58758         soc_BRDC_FMAC_RESERVED_MTCD_BCM88680_A0r_fields,
  58759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58760         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58761         -1,
  58762         -1,
  58763     },
  58764 #endif /* chips */
  58765 
  58766 #if defined(BCM_88690_A0)
  58767     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88690_A0r */
  58768         soc_block_list[23],
  58769         soc_genreg,
  58770         1,
  58771         0,
  58772         0xae,
  58773         SOC_REG_FLAG_WO,
  58774         0,
  58775         6,
  58776         soc_BRDC_FMAC_RESERVED_MTCD_BCM88690_A0r_fields,
  58777         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58778         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58779         -1,
  58780         -1,
  58781     },
  58782 #endif /* chips */
  58783 
  58784 #if defined(BCM_88690_B0)
  58785     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88690_B0r */
  58786         soc_block_list[23],
  58787         soc_genreg,
  58788         1,
  58789         0,
  58790         0xae,
  58791         SOC_REG_FLAG_WO,
  58792         0,
  58793         6,
  58794         soc_BRDC_FMAC_RESERVED_MTCD_BCM88690_B0r_fields,
  58795         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58796         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58797         -1,
  58798         -1,
  58799     },
  58800 #endif /* chips */
  58801 
  58802 #if defined(BCM_88790_A0)
  58803     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCD_BCM88790_A0r */
  58804         soc_block_list[23],
  58805         soc_genreg,
  58806         1,
  58807         0,
  58808         0xae,
  58809         SOC_REG_FLAG_WO,
  58810         0,
  58811         6,
  58812         soc_BRDC_FMAC_RESERVED_MTCD_BCM88790_A0r_fields,
  58813         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  58814         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  58815         -1,
  58816         -1,
  58817     },
  58818 #endif /* chips */
  58819 
  58820 #if defined(BCM_88675_A0)
  58821     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCPr */
  58822         soc_block_list[23],
  58823         soc_genreg,
  58824         1,
  58825         0,
  58826         0xad,
  58827         SOC_REG_FLAG_64_BITS |
  58828                           SOC_REG_FLAG_WO,
  58829         0,
  58830         17,
  58831         soc_BRDC_FMAC_RESERVED_MTCPr_fields,
  58832         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58833         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58834         -1,
  58835         -1,
  58836     },
  58837 #endif /* chips */
  58838 
  58839 #if defined(BCM_83208_A0)
  58840     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM83208_A0r */
  58841         soc_block_list[23],
  58842         soc_genreg,
  58843         1,
  58844         0,
  58845         0xad,
  58846         SOC_REG_FLAG_64_BITS |
  58847                           SOC_REG_FLAG_WO,
  58848         0,
  58849         17,
  58850         soc_BRDC_FMAC_RESERVED_MTCP_BCM83208_A0r_fields,
  58851         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58852         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58853         -1,
  58854         -1,
  58855     },
  58856 #endif /* chips */
  58857 
  58858 #if defined(BCM_88375_A0)
  58859     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88375_A0r */
  58860         soc_block_list[23],
  58861         soc_genreg,
  58862         1,
  58863         0,
  58864         0xad,
  58865         SOC_REG_FLAG_64_BITS |
  58866                           SOC_REG_FLAG_WO,
  58867         0,
  58868         17,
  58869         soc_BRDC_FMAC_RESERVED_MTCP_BCM88375_A0r_fields,
  58870         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58871         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58872         -1,
  58873         -1,
  58874     },
  58875 #endif /* chips */
  58876 
  58877 #if defined(BCM_88375_B0)
  58878     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88375_B0r */
  58879         soc_block_list[23],
  58880         soc_genreg,
  58881         1,
  58882         0,
  58883         0xad,
  58884         SOC_REG_FLAG_64_BITS |
  58885                           SOC_REG_FLAG_WO,
  58886         0,
  58887         17,
  58888         soc_BRDC_FMAC_RESERVED_MTCP_BCM88375_B0r_fields,
  58889         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58890         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58891         -1,
  58892         -1,
  58893     },
  58894 #endif /* chips */
  58895 
  58896 #if defined(BCM_88470_A0)
  58897     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88470_A0r */
  58898         soc_block_list[23],
  58899         soc_genreg,
  58900         1,
  58901         0,
  58902         0xad,
  58903         SOC_REG_FLAG_64_BITS |
  58904                           SOC_REG_FLAG_WO,
  58905         0,
  58906         17,
  58907         soc_BRDC_FMAC_RESERVED_MTCP_BCM88470_A0r_fields,
  58908         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58909         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58910         -1,
  58911         -1,
  58912     },
  58913 #endif /* chips */
  58914 
  58915 #if defined(BCM_88470_B0)
  58916     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88470_B0r */
  58917         soc_block_list[23],
  58918         soc_genreg,
  58919         1,
  58920         0,
  58921         0xad,
  58922         SOC_REG_FLAG_64_BITS |
  58923                           SOC_REG_FLAG_WO,
  58924         0,
  58925         17,
  58926         soc_BRDC_FMAC_RESERVED_MTCP_BCM88470_B0r_fields,
  58927         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58928         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58929         -1,
  58930         -1,
  58931     },
  58932 #endif /* chips */
  58933 
  58934 #if defined(BCM_88675_B0)
  58935     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88675_B0r */
  58936         soc_block_list[23],
  58937         soc_genreg,
  58938         1,
  58939         0,
  58940         0xad,
  58941         SOC_REG_FLAG_64_BITS |
  58942                           SOC_REG_FLAG_WO,
  58943         0,
  58944         17,
  58945         soc_BRDC_FMAC_RESERVED_MTCP_BCM88675_B0r_fields,
  58946         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58947         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58948         -1,
  58949         -1,
  58950     },
  58951 #endif /* chips */
  58952 
  58953 #if defined(BCM_88680_A0)
  58954     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88680_A0r */
  58955         soc_block_list[23],
  58956         soc_genreg,
  58957         1,
  58958         0,
  58959         0xad,
  58960         SOC_REG_FLAG_64_BITS |
  58961                           SOC_REG_FLAG_WO,
  58962         0,
  58963         17,
  58964         soc_BRDC_FMAC_RESERVED_MTCP_BCM88680_A0r_fields,
  58965         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58966         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58967         -1,
  58968         -1,
  58969     },
  58970 #endif /* chips */
  58971 
  58972 #if defined(BCM_88690_A0)
  58973     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88690_A0r */
  58974         soc_block_list[23],
  58975         soc_genreg,
  58976         1,
  58977         0,
  58978         0xad,
  58979         SOC_REG_FLAG_64_BITS |
  58980                           SOC_REG_FLAG_WO,
  58981         0,
  58982         17,
  58983         soc_BRDC_FMAC_RESERVED_MTCP_BCM88690_A0r_fields,
  58984         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  58985         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  58986         -1,
  58987         -1,
  58988     },
  58989 #endif /* chips */
  58990 
  58991 #if defined(BCM_88690_B0)
  58992     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88690_B0r */
  58993         soc_block_list[23],
  58994         soc_genreg,
  58995         1,
  58996         0,
  58997         0xad,
  58998         SOC_REG_FLAG_64_BITS |
  58999                           SOC_REG_FLAG_WO,
  59000         0,
  59001         17,
  59002         soc_BRDC_FMAC_RESERVED_MTCP_BCM88690_B0r_fields,
  59003         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  59004         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  59005         -1,
  59006         -1,
  59007     },
  59008 #endif /* chips */
  59009 
  59010 #if defined(BCM_88790_A0)
  59011     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_MTCP_BCM88790_A0r */
  59012         soc_block_list[23],
  59013         soc_genreg,
  59014         1,
  59015         0,
  59016         0xad,
  59017         SOC_REG_FLAG_64_BITS |
  59018                           SOC_REG_FLAG_WO,
  59019         0,
  59020         17,
  59021         soc_BRDC_FMAC_RESERVED_MTCP_BCM88790_A0r_fields,
  59022         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  59023         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  59024         -1,
  59025         -1,
  59026     },
  59027 #endif /* chips */
  59028 
  59029 #if defined(BCM_88675_A0)
  59030     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0r */
  59031         soc_block_list[23],
  59032         soc_genreg,
  59033         1,
  59034         0,
  59035         0x90,
  59036         SOC_REG_FLAG_WO,
  59037         0,
  59038         1,
  59039         soc_BRDC_FMAC_RESERVED_SPARE_0r_fields,
  59040         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59042         -1,
  59043         -1,
  59044     },
  59045 #endif /* chips */
  59046 
  59047 #if defined(BCM_88675_A0)
  59048     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1r */
  59049         soc_block_list[23],
  59050         soc_genreg,
  59051         1,
  59052         0,
  59053         0x91,
  59054         SOC_REG_FLAG_WO,
  59055         0,
  59056         1,
  59057         soc_BRDC_FMAC_RESERVED_SPARE_1r_fields,
  59058         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59060         -1,
  59061         -1,
  59062     },
  59063 #endif /* chips */
  59064 
  59065 #if defined(BCM_88675_A0)
  59066     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2r */
  59067         soc_block_list[23],
  59068         soc_genreg,
  59069         1,
  59070         0,
  59071         0x92,
  59072         SOC_REG_FLAG_WO,
  59073         0,
  59074         1,
  59075         soc_BRDC_FMAC_RESERVED_SPARE_2r_fields,
  59076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59078         -1,
  59079         -1,
  59080     },
  59081 #endif /* chips */
  59082 
  59083 #if defined(BCM_88675_A0)
  59084     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3r */
  59085         soc_block_list[23],
  59086         soc_genreg,
  59087         1,
  59088         0,
  59089         0x93,
  59090         SOC_REG_FLAG_WO,
  59091         0,
  59092         1,
  59093         soc_BRDC_FMAC_RESERVED_SPARE_3r_fields,
  59094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59096         -1,
  59097         -1,
  59098     },
  59099 #endif /* chips */
  59100 
  59101 #if defined(BCM_83208_A0)
  59102     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM83208_A0r */
  59103         soc_block_list[23],
  59104         soc_genreg,
  59105         1,
  59106         0,
  59107         0x90,
  59108         SOC_REG_FLAG_WO,
  59109         0,
  59110         1,
  59111         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM83208_A0r_fields,
  59112         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59114         -1,
  59115         -1,
  59116     },
  59117 #endif /* chips */
  59118 
  59119 #if defined(BCM_88375_A0)
  59120     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88375_A0r */
  59121         soc_block_list[23],
  59122         soc_genreg,
  59123         1,
  59124         0,
  59125         0x90,
  59126         SOC_REG_FLAG_WO,
  59127         0,
  59128         1,
  59129         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88375_A0r_fields,
  59130         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59132         -1,
  59133         -1,
  59134     },
  59135 #endif /* chips */
  59136 
  59137 #if defined(BCM_88375_B0)
  59138     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88375_B0r */
  59139         soc_block_list[23],
  59140         soc_genreg,
  59141         1,
  59142         0,
  59143         0x90,
  59144         SOC_REG_FLAG_WO,
  59145         0,
  59146         1,
  59147         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88375_B0r_fields,
  59148         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59150         -1,
  59151         -1,
  59152     },
  59153 #endif /* chips */
  59154 
  59155 #if defined(BCM_88470_A0)
  59156     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88470_A0r */
  59157         soc_block_list[23],
  59158         soc_genreg,
  59159         1,
  59160         0,
  59161         0x90,
  59162         SOC_REG_FLAG_WO,
  59163         0,
  59164         1,
  59165         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88470_A0r_fields,
  59166         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59168         -1,
  59169         -1,
  59170     },
  59171 #endif /* chips */
  59172 
  59173 #if defined(BCM_88470_B0)
  59174     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88470_B0r */
  59175         soc_block_list[23],
  59176         soc_genreg,
  59177         1,
  59178         0,
  59179         0x90,
  59180         SOC_REG_FLAG_WO,
  59181         0,
  59182         1,
  59183         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88470_B0r_fields,
  59184         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59186         -1,
  59187         -1,
  59188     },
  59189 #endif /* chips */
  59190 
  59191 #if defined(BCM_88675_B0)
  59192     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88675_B0r */
  59193         soc_block_list[23],
  59194         soc_genreg,
  59195         1,
  59196         0,
  59197         0x90,
  59198         SOC_REG_FLAG_WO,
  59199         0,
  59200         1,
  59201         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88675_B0r_fields,
  59202         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59204         -1,
  59205         -1,
  59206     },
  59207 #endif /* chips */
  59208 
  59209 #if defined(BCM_88680_A0)
  59210     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88680_A0r */
  59211         soc_block_list[23],
  59212         soc_genreg,
  59213         1,
  59214         0,
  59215         0x90,
  59216         SOC_REG_FLAG_WO,
  59217         0,
  59218         1,
  59219         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88680_A0r_fields,
  59220         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59221         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59222         -1,
  59223         -1,
  59224     },
  59225 #endif /* chips */
  59226 
  59227 #if defined(BCM_88690_A0)
  59228     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88690_A0r */
  59229         soc_block_list[23],
  59230         soc_genreg,
  59231         1,
  59232         0,
  59233         0x90,
  59234         SOC_REG_FLAG_WO,
  59235         0,
  59236         1,
  59237         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88690_A0r_fields,
  59238         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59240         -1,
  59241         -1,
  59242     },
  59243 #endif /* chips */
  59244 
  59245 #if defined(BCM_88690_B0)
  59246     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88690_B0r */
  59247         soc_block_list[23],
  59248         soc_genreg,
  59249         1,
  59250         0,
  59251         0x90,
  59252         SOC_REG_FLAG_WO,
  59253         0,
  59254         1,
  59255         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88690_B0r_fields,
  59256         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59258         -1,
  59259         -1,
  59260     },
  59261 #endif /* chips */
  59262 
  59263 #if defined(BCM_88790_A0)
  59264     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_0_BCM88790_A0r */
  59265         soc_block_list[23],
  59266         soc_genreg,
  59267         1,
  59268         0,
  59269         0x90,
  59270         SOC_REG_FLAG_WO,
  59271         0,
  59272         1,
  59273         soc_BRDC_FMAC_RESERVED_SPARE_0_BCM88790_A0r_fields,
  59274         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59276         -1,
  59277         -1,
  59278     },
  59279 #endif /* chips */
  59280 
  59281 #if defined(BCM_83208_A0)
  59282     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM83208_A0r */
  59283         soc_block_list[23],
  59284         soc_genreg,
  59285         1,
  59286         0,
  59287         0x91,
  59288         SOC_REG_FLAG_WO,
  59289         0,
  59290         1,
  59291         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM83208_A0r_fields,
  59292         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59293         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59294         -1,
  59295         -1,
  59296     },
  59297 #endif /* chips */
  59298 
  59299 #if defined(BCM_88375_A0)
  59300     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88375_A0r */
  59301         soc_block_list[23],
  59302         soc_genreg,
  59303         1,
  59304         0,
  59305         0x91,
  59306         SOC_REG_FLAG_WO,
  59307         0,
  59308         1,
  59309         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88375_A0r_fields,
  59310         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59311         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59312         -1,
  59313         -1,
  59314     },
  59315 #endif /* chips */
  59316 
  59317 #if defined(BCM_88375_B0)
  59318     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88375_B0r */
  59319         soc_block_list[23],
  59320         soc_genreg,
  59321         1,
  59322         0,
  59323         0x91,
  59324         SOC_REG_FLAG_WO,
  59325         0,
  59326         1,
  59327         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88375_B0r_fields,
  59328         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59329         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59330         -1,
  59331         -1,
  59332     },
  59333 #endif /* chips */
  59334 
  59335 #if defined(BCM_88470_A0)
  59336     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88470_A0r */
  59337         soc_block_list[23],
  59338         soc_genreg,
  59339         1,
  59340         0,
  59341         0x91,
  59342         SOC_REG_FLAG_WO,
  59343         0,
  59344         1,
  59345         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88470_A0r_fields,
  59346         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59347         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59348         -1,
  59349         -1,
  59350     },
  59351 #endif /* chips */
  59352 
  59353 #if defined(BCM_88470_B0)
  59354     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88470_B0r */
  59355         soc_block_list[23],
  59356         soc_genreg,
  59357         1,
  59358         0,
  59359         0x91,
  59360         SOC_REG_FLAG_WO,
  59361         0,
  59362         1,
  59363         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88470_B0r_fields,
  59364         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59365         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59366         -1,
  59367         -1,
  59368     },
  59369 #endif /* chips */
  59370 
  59371 #if defined(BCM_88675_B0)
  59372     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88675_B0r */
  59373         soc_block_list[23],
  59374         soc_genreg,
  59375         1,
  59376         0,
  59377         0x91,
  59378         SOC_REG_FLAG_WO,
  59379         0,
  59380         1,
  59381         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88675_B0r_fields,
  59382         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59383         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59384         -1,
  59385         -1,
  59386     },
  59387 #endif /* chips */
  59388 
  59389 #if defined(BCM_88680_A0)
  59390     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88680_A0r */
  59391         soc_block_list[23],
  59392         soc_genreg,
  59393         1,
  59394         0,
  59395         0x91,
  59396         SOC_REG_FLAG_WO,
  59397         0,
  59398         1,
  59399         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88680_A0r_fields,
  59400         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59401         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59402         -1,
  59403         -1,
  59404     },
  59405 #endif /* chips */
  59406 
  59407 #if defined(BCM_88690_A0)
  59408     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88690_A0r */
  59409         soc_block_list[23],
  59410         soc_genreg,
  59411         1,
  59412         0,
  59413         0x91,
  59414         SOC_REG_FLAG_WO,
  59415         0,
  59416         1,
  59417         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88690_A0r_fields,
  59418         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59420         -1,
  59421         -1,
  59422     },
  59423 #endif /* chips */
  59424 
  59425 #if defined(BCM_88690_B0)
  59426     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88690_B0r */
  59427         soc_block_list[23],
  59428         soc_genreg,
  59429         1,
  59430         0,
  59431         0x91,
  59432         SOC_REG_FLAG_WO,
  59433         0,
  59434         1,
  59435         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88690_B0r_fields,
  59436         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59437         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59438         -1,
  59439         -1,
  59440     },
  59441 #endif /* chips */
  59442 
  59443 #if defined(BCM_88790_A0)
  59444     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_1_BCM88790_A0r */
  59445         soc_block_list[23],
  59446         soc_genreg,
  59447         1,
  59448         0,
  59449         0x91,
  59450         SOC_REG_FLAG_WO,
  59451         0,
  59452         1,
  59453         soc_BRDC_FMAC_RESERVED_SPARE_1_BCM88790_A0r_fields,
  59454         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  59455         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59456         -1,
  59457         -1,
  59458     },
  59459 #endif /* chips */
  59460 
  59461 #if defined(BCM_83208_A0)
  59462     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM83208_A0r */
  59463         soc_block_list[23],
  59464         soc_genreg,
  59465         1,
  59466         0,
  59467         0x92,
  59468         SOC_REG_FLAG_WO,
  59469         0,
  59470         1,
  59471         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM83208_A0r_fields,
  59472         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59473         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59474         -1,
  59475         -1,
  59476     },
  59477 #endif /* chips */
  59478 
  59479 #if defined(BCM_88375_A0)
  59480     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88375_A0r */
  59481         soc_block_list[23],
  59482         soc_genreg,
  59483         1,
  59484         0,
  59485         0x92,
  59486         SOC_REG_FLAG_WO,
  59487         0,
  59488         1,
  59489         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88375_A0r_fields,
  59490         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59491         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59492         -1,
  59493         -1,
  59494     },
  59495 #endif /* chips */
  59496 
  59497 #if defined(BCM_88375_B0)
  59498     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88375_B0r */
  59499         soc_block_list[23],
  59500         soc_genreg,
  59501         1,
  59502         0,
  59503         0x92,
  59504         SOC_REG_FLAG_WO,
  59505         0,
  59506         1,
  59507         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88375_B0r_fields,
  59508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59509         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59510         -1,
  59511         -1,
  59512     },
  59513 #endif /* chips */
  59514 
  59515 #if defined(BCM_88470_A0)
  59516     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88470_A0r */
  59517         soc_block_list[23],
  59518         soc_genreg,
  59519         1,
  59520         0,
  59521         0x92,
  59522         SOC_REG_FLAG_WO,
  59523         0,
  59524         1,
  59525         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88470_A0r_fields,
  59526         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59527         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59528         -1,
  59529         -1,
  59530     },
  59531 #endif /* chips */
  59532 
  59533 #if defined(BCM_88470_B0)
  59534     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88470_B0r */
  59535         soc_block_list[23],
  59536         soc_genreg,
  59537         1,
  59538         0,
  59539         0x92,
  59540         SOC_REG_FLAG_WO,
  59541         0,
  59542         1,
  59543         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88470_B0r_fields,
  59544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59546         -1,
  59547         -1,
  59548     },
  59549 #endif /* chips */
  59550 
  59551 #if defined(BCM_88675_B0)
  59552     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88675_B0r */
  59553         soc_block_list[23],
  59554         soc_genreg,
  59555         1,
  59556         0,
  59557         0x92,
  59558         SOC_REG_FLAG_WO,
  59559         0,
  59560         1,
  59561         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88675_B0r_fields,
  59562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59563         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59564         -1,
  59565         -1,
  59566     },
  59567 #endif /* chips */
  59568 
  59569 #if defined(BCM_88680_A0)
  59570     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88680_A0r */
  59571         soc_block_list[23],
  59572         soc_genreg,
  59573         1,
  59574         0,
  59575         0x92,
  59576         SOC_REG_FLAG_WO,
  59577         0,
  59578         1,
  59579         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88680_A0r_fields,
  59580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59581         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59582         -1,
  59583         -1,
  59584     },
  59585 #endif /* chips */
  59586 
  59587 #if defined(BCM_88690_A0)
  59588     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88690_A0r */
  59589         soc_block_list[23],
  59590         soc_genreg,
  59591         1,
  59592         0,
  59593         0x92,
  59594         SOC_REG_FLAG_WO,
  59595         0,
  59596         1,
  59597         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88690_A0r_fields,
  59598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59600         -1,
  59601         -1,
  59602     },
  59603 #endif /* chips */
  59604 
  59605 #if defined(BCM_88690_B0)
  59606     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88690_B0r */
  59607         soc_block_list[23],
  59608         soc_genreg,
  59609         1,
  59610         0,
  59611         0x92,
  59612         SOC_REG_FLAG_WO,
  59613         0,
  59614         1,
  59615         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88690_B0r_fields,
  59616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59618         -1,
  59619         -1,
  59620     },
  59621 #endif /* chips */
  59622 
  59623 #if defined(BCM_88790_A0)
  59624     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_2_BCM88790_A0r */
  59625         soc_block_list[23],
  59626         soc_genreg,
  59627         1,
  59628         0,
  59629         0x92,
  59630         SOC_REG_FLAG_WO,
  59631         0,
  59632         1,
  59633         soc_BRDC_FMAC_RESERVED_SPARE_2_BCM88790_A0r_fields,
  59634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59636         -1,
  59637         -1,
  59638     },
  59639 #endif /* chips */
  59640 
  59641 #if defined(BCM_83208_A0)
  59642     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM83208_A0r */
  59643         soc_block_list[23],
  59644         soc_genreg,
  59645         1,
  59646         0,
  59647         0x93,
  59648         SOC_REG_FLAG_WO,
  59649         0,
  59650         1,
  59651         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM83208_A0r_fields,
  59652         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59654         -1,
  59655         -1,
  59656     },
  59657 #endif /* chips */
  59658 
  59659 #if defined(BCM_88375_A0)
  59660     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88375_A0r */
  59661         soc_block_list[23],
  59662         soc_genreg,
  59663         1,
  59664         0,
  59665         0x93,
  59666         SOC_REG_FLAG_WO,
  59667         0,
  59668         1,
  59669         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88375_A0r_fields,
  59670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59672         -1,
  59673         -1,
  59674     },
  59675 #endif /* chips */
  59676 
  59677 #if defined(BCM_88375_B0)
  59678     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88375_B0r */
  59679         soc_block_list[23],
  59680         soc_genreg,
  59681         1,
  59682         0,
  59683         0x93,
  59684         SOC_REG_FLAG_WO,
  59685         0,
  59686         1,
  59687         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88375_B0r_fields,
  59688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59690         -1,
  59691         -1,
  59692     },
  59693 #endif /* chips */
  59694 
  59695 #if defined(BCM_88470_A0)
  59696     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88470_A0r */
  59697         soc_block_list[23],
  59698         soc_genreg,
  59699         1,
  59700         0,
  59701         0x93,
  59702         SOC_REG_FLAG_WO,
  59703         0,
  59704         1,
  59705         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88470_A0r_fields,
  59706         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59708         -1,
  59709         -1,
  59710     },
  59711 #endif /* chips */
  59712 
  59713 #if defined(BCM_88470_B0)
  59714     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88470_B0r */
  59715         soc_block_list[23],
  59716         soc_genreg,
  59717         1,
  59718         0,
  59719         0x93,
  59720         SOC_REG_FLAG_WO,
  59721         0,
  59722         1,
  59723         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88470_B0r_fields,
  59724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59726         -1,
  59727         -1,
  59728     },
  59729 #endif /* chips */
  59730 
  59731 #if defined(BCM_88675_B0)
  59732     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88675_B0r */
  59733         soc_block_list[23],
  59734         soc_genreg,
  59735         1,
  59736         0,
  59737         0x93,
  59738         SOC_REG_FLAG_WO,
  59739         0,
  59740         1,
  59741         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88675_B0r_fields,
  59742         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59744         -1,
  59745         -1,
  59746     },
  59747 #endif /* chips */
  59748 
  59749 #if defined(BCM_88680_A0)
  59750     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88680_A0r */
  59751         soc_block_list[23],
  59752         soc_genreg,
  59753         1,
  59754         0,
  59755         0x93,
  59756         SOC_REG_FLAG_WO,
  59757         0,
  59758         1,
  59759         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88680_A0r_fields,
  59760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59762         -1,
  59763         -1,
  59764     },
  59765 #endif /* chips */
  59766 
  59767 #if defined(BCM_88690_A0)
  59768     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88690_A0r */
  59769         soc_block_list[23],
  59770         soc_genreg,
  59771         1,
  59772         0,
  59773         0x93,
  59774         SOC_REG_FLAG_WO,
  59775         0,
  59776         1,
  59777         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88690_A0r_fields,
  59778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59779         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59780         -1,
  59781         -1,
  59782     },
  59783 #endif /* chips */
  59784 
  59785 #if defined(BCM_88690_B0)
  59786     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88690_B0r */
  59787         soc_block_list[23],
  59788         soc_genreg,
  59789         1,
  59790         0,
  59791         0x93,
  59792         SOC_REG_FLAG_WO,
  59793         0,
  59794         1,
  59795         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88690_B0r_fields,
  59796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59798         -1,
  59799         -1,
  59800     },
  59801 #endif /* chips */
  59802 
  59803 #if defined(BCM_88790_A0)
  59804     { /* SOC_REG_INT_BRDC_FMAC_RESERVED_SPARE_3_BCM88790_A0r */
  59805         soc_block_list[23],
  59806         soc_genreg,
  59807         1,
  59808         0,
  59809         0x93,
  59810         SOC_REG_FLAG_WO,
  59811         0,
  59812         1,
  59813         soc_BRDC_FMAC_RESERVED_SPARE_3_BCM88790_A0r_fields,
  59814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59815         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  59816         -1,
  59817         -1,
  59818     },
  59819 #endif /* chips */
  59820 
  59821 #if defined(BCM_83208_A0)
  59822     { /* SOC_REG_INT_BRDC_FMAC_RETIMERr */
  59823         soc_block_list[23],
  59824         soc_genreg,
  59825         4,
  59826         0,
  59827         0x110,
  59828         SOC_REG_FLAG_ARRAY |
  59829                           SOC_REG_FLAG_WO |
  59830                           SOC_REG_FLAG_REG_ARRAY,
  59831         0,
  59832         13,
  59833         soc_BRDC_FMAC_RETIMERr_fields,
  59834         SOC_RESET_VAL_DEC(0x01600052, 0x00000000)
  59835         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  59836         -1,
  59837         -1,
  59838     },
  59839 #endif /* chips */
  59840 
  59841 #if defined(BCM_88690_A0)
  59842     { /* SOC_REG_INT_BRDC_FMAC_RETIMER_BCM88690_A0r */
  59843         soc_block_list[23],
  59844         soc_genreg,
  59845         4,
  59846         0,
  59847         0x134,
  59848         SOC_REG_FLAG_ABOVE_64_BITS |
  59849                           SOC_REG_FLAG_ARRAY |
  59850                           SOC_REG_FLAG_WO |
  59851                           SOC_REG_FLAG_REG_ARRAY,
  59852         SOC_REG_FLAG_INIT_ON_READ,
  59853         27,
  59854         soc_BRDC_FMAC_RETIMER_BCM88690_A0r_fields,
  59855         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59856         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59857         -1,
  59858         -1,
  59859     },
  59860 #endif /* chips */
  59861 
  59862 #if defined(BCM_88690_B0)
  59863     { /* SOC_REG_INT_BRDC_FMAC_RETIMER_BCM88690_B0r */
  59864         soc_block_list[23],
  59865         soc_genreg,
  59866         4,
  59867         0,
  59868         0x134,
  59869         SOC_REG_FLAG_ABOVE_64_BITS |
  59870                           SOC_REG_FLAG_ARRAY |
  59871                           SOC_REG_FLAG_WO |
  59872                           SOC_REG_FLAG_REG_ARRAY,
  59873         SOC_REG_FLAG_INIT_ON_READ,
  59874         27,
  59875         soc_BRDC_FMAC_RETIMER_BCM88690_B0r_fields,
  59876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59878         -1,
  59879         -1,
  59880     },
  59881 #endif /* chips */
  59882 
  59883 #if defined(BCM_88790_A0)
  59884     { /* SOC_REG_INT_BRDC_FMAC_RETIMER_BCM88790_A0r */
  59885         soc_block_list[23],
  59886         soc_genreg,
  59887         4,
  59888         0,
  59889         0x134,
  59890         SOC_REG_FLAG_ABOVE_64_BITS |
  59891                           SOC_REG_FLAG_ARRAY |
  59892                           SOC_REG_FLAG_WO |
  59893                           SOC_REG_FLAG_REG_ARRAY,
  59894         0,
  59895         27,
  59896         soc_BRDC_FMAC_RETIMER_BCM88790_A0r_fields,
  59897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59899         -1,
  59900         -1,
  59901     },
  59902 #endif /* chips */
  59903 
  59904 #if defined(BCM_88675_A0)
  59905     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATIONr */
  59906         soc_block_list[23],
  59907         soc_genreg,
  59908         4,
  59909         0,
  59910         0x194,
  59911         SOC_REG_FLAG_64_BITS |
  59912                           SOC_REG_FLAG_ARRAY |
  59913                           SOC_REG_FLAG_WO |
  59914                           SOC_REG_FLAG_REG_ARRAY,
  59915         0,
  59916         20,
  59917         soc_BRDC_FMAC_RSF_CONFIGURATIONr_fields,
  59918         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  59919         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  59920         -1,
  59921         -1,
  59922     },
  59923 #endif /* chips */
  59924 
  59925 #if defined(BCM_83208_A0)
  59926     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM83208_A0r */
  59927         soc_block_list[23],
  59928         soc_genreg,
  59929         4,
  59930         0,
  59931         0x182,
  59932         SOC_REG_FLAG_ABOVE_64_BITS |
  59933                           SOC_REG_FLAG_ARRAY |
  59934                           SOC_REG_FLAG_WO |
  59935                           SOC_REG_FLAG_REG_ARRAY,
  59936         0,
  59937         25,
  59938         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM83208_A0r_fields,
  59939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  59940         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  59941         -1,
  59942         -1,
  59943     },
  59944 #endif /* chips */
  59945 
  59946 #if defined(BCM_88375_A0)
  59947     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88375_A0r */
  59948         soc_block_list[23],
  59949         soc_genreg,
  59950         4,
  59951         0,
  59952         0x194,
  59953         SOC_REG_FLAG_64_BITS |
  59954                           SOC_REG_FLAG_ARRAY |
  59955                           SOC_REG_FLAG_WO |
  59956                           SOC_REG_FLAG_REG_ARRAY,
  59957         0,
  59958         20,
  59959         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88375_A0r_fields,
  59960         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  59961         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  59962         -1,
  59963         -1,
  59964     },
  59965 #endif /* chips */
  59966 
  59967 #if defined(BCM_88375_B0)
  59968     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88375_B0r */
  59969         soc_block_list[23],
  59970         soc_genreg,
  59971         4,
  59972         0,
  59973         0x194,
  59974         SOC_REG_FLAG_64_BITS |
  59975                           SOC_REG_FLAG_ARRAY |
  59976                           SOC_REG_FLAG_WO |
  59977                           SOC_REG_FLAG_REG_ARRAY,
  59978         0,
  59979         20,
  59980         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88375_B0r_fields,
  59981         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  59982         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  59983         -1,
  59984         -1,
  59985     },
  59986 #endif /* chips */
  59987 
  59988 #if defined(BCM_88470_A0)
  59989     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88470_A0r */
  59990         soc_block_list[23],
  59991         soc_genreg,
  59992         4,
  59993         0,
  59994         0x194,
  59995         SOC_REG_FLAG_64_BITS |
  59996                           SOC_REG_FLAG_ARRAY |
  59997                           SOC_REG_FLAG_WO |
  59998                           SOC_REG_FLAG_REG_ARRAY,
  59999         0,
  60000         20,
  60001         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88470_A0r_fields,
  60002         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  60003         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  60004         -1,
  60005         -1,
  60006     },
  60007 #endif /* chips */
  60008 
  60009 #if defined(BCM_88470_B0)
  60010     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88470_B0r */
  60011         soc_block_list[23],
  60012         soc_genreg,
  60013         4,
  60014         0,
  60015         0x194,
  60016         SOC_REG_FLAG_64_BITS |
  60017                           SOC_REG_FLAG_ARRAY |
  60018                           SOC_REG_FLAG_WO |
  60019                           SOC_REG_FLAG_REG_ARRAY,
  60020         0,
  60021         20,
  60022         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88470_B0r_fields,
  60023         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  60024         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  60025         -1,
  60026         -1,
  60027     },
  60028 #endif /* chips */
  60029 
  60030 #if defined(BCM_88675_B0)
  60031     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88675_B0r */
  60032         soc_block_list[23],
  60033         soc_genreg,
  60034         4,
  60035         0,
  60036         0x194,
  60037         SOC_REG_FLAG_64_BITS |
  60038                           SOC_REG_FLAG_ARRAY |
  60039                           SOC_REG_FLAG_WO |
  60040                           SOC_REG_FLAG_REG_ARRAY,
  60041         0,
  60042         20,
  60043         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88675_B0r_fields,
  60044         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  60045         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  60046         -1,
  60047         -1,
  60048     },
  60049 #endif /* chips */
  60050 
  60051 #if defined(BCM_88680_A0)
  60052     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88680_A0r */
  60053         soc_block_list[23],
  60054         soc_genreg,
  60055         4,
  60056         0,
  60057         0x194,
  60058         SOC_REG_FLAG_64_BITS |
  60059                           SOC_REG_FLAG_ARRAY |
  60060                           SOC_REG_FLAG_WO |
  60061                           SOC_REG_FLAG_REG_ARRAY,
  60062         0,
  60063         20,
  60064         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88680_A0r_fields,
  60065         SOC_RESET_VAL_DEC(0x42000101, 0x00014ef0)
  60066         SOC_RESET_MASK_DEC(0xffffff1f, 0x0003ffff)
  60067         -1,
  60068         -1,
  60069     },
  60070 #endif /* chips */
  60071 
  60072 #if defined(BCM_88690_A0)
  60073     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88690_A0r */
  60074         soc_block_list[23],
  60075         soc_genreg,
  60076         4,
  60077         0,
  60078         0x1be,
  60079         SOC_REG_FLAG_ABOVE_64_BITS |
  60080                           SOC_REG_FLAG_ARRAY |
  60081                           SOC_REG_FLAG_WO |
  60082                           SOC_REG_FLAG_REG_ARRAY,
  60083         0,
  60084         25,
  60085         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88690_A0r_fields,
  60086         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60087         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60088         -1,
  60089         -1,
  60090     },
  60091 #endif /* chips */
  60092 
  60093 #if defined(BCM_88690_B0)
  60094     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88690_B0r */
  60095         soc_block_list[23],
  60096         soc_genreg,
  60097         4,
  60098         0,
  60099         0x1be,
  60100         SOC_REG_FLAG_ABOVE_64_BITS |
  60101                           SOC_REG_FLAG_ARRAY |
  60102                           SOC_REG_FLAG_WO |
  60103                           SOC_REG_FLAG_REG_ARRAY,
  60104         0,
  60105         25,
  60106         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88690_B0r_fields,
  60107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60109         -1,
  60110         -1,
  60111     },
  60112 #endif /* chips */
  60113 
  60114 #if defined(BCM_88790_A0)
  60115     { /* SOC_REG_INT_BRDC_FMAC_RSF_CONFIGURATION_BCM88790_A0r */
  60116         soc_block_list[23],
  60117         soc_genreg,
  60118         4,
  60119         0,
  60120         0x1be,
  60121         SOC_REG_FLAG_ABOVE_64_BITS |
  60122                           SOC_REG_FLAG_ARRAY |
  60123                           SOC_REG_FLAG_WO |
  60124                           SOC_REG_FLAG_REG_ARRAY,
  60125         0,
  60126         25,
  60127         soc_BRDC_FMAC_RSF_CONFIGURATION_BCM88790_A0r_fields,
  60128         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60129         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60130         -1,
  60131         -1,
  60132     },
  60133 #endif /* chips */
  60134 
  60135 #if defined(BCM_88675_A0)
  60136     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUSr */
  60137         soc_block_list[23],
  60138         soc_genreg,
  60139         4,
  60140         0,
  60141         0x19c,
  60142         SOC_REG_FLAG_64_BITS |
  60143                           SOC_REG_FLAG_ARRAY |
  60144                           SOC_REG_FLAG_RO |
  60145                           SOC_REG_FLAG_WO |
  60146                           SOC_REG_FLAG_REG_ARRAY,
  60147         0,
  60148         2,
  60149         soc_BRDC_FMAC_RSF_STATUSr_fields,
  60150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60151         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  60152         -1,
  60153         -1,
  60154     },
  60155 #endif /* chips */
  60156 
  60157 #if defined(BCM_83208_A0)
  60158     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM83208_A0r */
  60159         soc_block_list[23],
  60160         soc_genreg,
  60161         4,
  60162         0,
  60163         0x192,
  60164         SOC_REG_FLAG_ABOVE_64_BITS |
  60165                           SOC_REG_FLAG_ARRAY |
  60166                           SOC_REG_FLAG_RO |
  60167                           SOC_REG_FLAG_WO |
  60168                           SOC_REG_FLAG_REG_ARRAY,
  60169         0,
  60170         2,
  60171         soc_BRDC_FMAC_RSF_STATUS_BCM83208_A0r_fields,
  60172         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60173         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60174         -1,
  60175         -1,
  60176     },
  60177 #endif /* chips */
  60178 
  60179 #if defined(BCM_88375_A0)
  60180     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88375_A0r */
  60181         soc_block_list[23],
  60182         soc_genreg,
  60183         4,
  60184         0,
  60185         0x19c,
  60186         SOC_REG_FLAG_64_BITS |
  60187                           SOC_REG_FLAG_ARRAY |
  60188                           SOC_REG_FLAG_RO |
  60189                           SOC_REG_FLAG_WO |
  60190                           SOC_REG_FLAG_REG_ARRAY,
  60191         0,
  60192         2,
  60193         soc_BRDC_FMAC_RSF_STATUS_BCM88375_A0r_fields,
  60194         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60195         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  60196         -1,
  60197         -1,
  60198     },
  60199 #endif /* chips */
  60200 
  60201 #if defined(BCM_88375_B0)
  60202     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88375_B0r */
  60203         soc_block_list[23],
  60204         soc_genreg,
  60205         4,
  60206         0,
  60207         0x19c,
  60208         SOC_REG_FLAG_64_BITS |
  60209                           SOC_REG_FLAG_ARRAY |
  60210                           SOC_REG_FLAG_RO |
  60211                           SOC_REG_FLAG_WO |
  60212                           SOC_REG_FLAG_REG_ARRAY,
  60213         0,
  60214         2,
  60215         soc_BRDC_FMAC_RSF_STATUS_BCM88375_B0r_fields,
  60216         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60217         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  60218         -1,
  60219         -1,
  60220     },
  60221 #endif /* chips */
  60222 
  60223 #if defined(BCM_88470_A0)
  60224     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88470_A0r */
  60225         soc_block_list[23],
  60226         soc_genreg,
  60227         4,
  60228         0,
  60229         0x19c,
  60230         SOC_REG_FLAG_64_BITS |
  60231                           SOC_REG_FLAG_ARRAY |
  60232                           SOC_REG_FLAG_RO |
  60233                           SOC_REG_FLAG_WO |
  60234                           SOC_REG_FLAG_REG_ARRAY,
  60235         0,
  60236         2,
  60237         soc_BRDC_FMAC_RSF_STATUS_BCM88470_A0r_fields,
  60238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60239         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  60240         -1,
  60241         -1,
  60242     },
  60243 #endif /* chips */
  60244 
  60245 #if defined(BCM_88470_B0)
  60246     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88470_B0r */
  60247         soc_block_list[23],
  60248         soc_genreg,
  60249         4,
  60250         0,
  60251         0x19c,
  60252         SOC_REG_FLAG_64_BITS |
  60253                           SOC_REG_FLAG_ARRAY |
  60254                           SOC_REG_FLAG_RO |
  60255                           SOC_REG_FLAG_WO |
  60256                           SOC_REG_FLAG_REG_ARRAY,
  60257         0,
  60258         2,
  60259         soc_BRDC_FMAC_RSF_STATUS_BCM88470_B0r_fields,
  60260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60261         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  60262         -1,
  60263         -1,
  60264     },
  60265 #endif /* chips */
  60266 
  60267 #if defined(BCM_88675_B0)
  60268     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88675_B0r */
  60269         soc_block_list[23],
  60270         soc_genreg,
  60271         4,
  60272         0,
  60273         0x19c,
  60274         SOC_REG_FLAG_64_BITS |
  60275                           SOC_REG_FLAG_ARRAY |
  60276                           SOC_REG_FLAG_RO |
  60277                           SOC_REG_FLAG_WO |
  60278                           SOC_REG_FLAG_REG_ARRAY,
  60279         0,
  60280         2,
  60281         soc_BRDC_FMAC_RSF_STATUS_BCM88675_B0r_fields,
  60282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60283         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  60284         -1,
  60285         -1,
  60286     },
  60287 #endif /* chips */
  60288 
  60289 #if defined(BCM_88680_A0)
  60290     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88680_A0r */
  60291         soc_block_list[23],
  60292         soc_genreg,
  60293         4,
  60294         0,
  60295         0x19c,
  60296         SOC_REG_FLAG_64_BITS |
  60297                           SOC_REG_FLAG_ARRAY |
  60298                           SOC_REG_FLAG_RO |
  60299                           SOC_REG_FLAG_WO |
  60300                           SOC_REG_FLAG_REG_ARRAY,
  60301         0,
  60302         2,
  60303         soc_BRDC_FMAC_RSF_STATUS_BCM88680_A0r_fields,
  60304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60305         SOC_RESET_MASK_DEC(0xffffffff, 0x0007ffff)
  60306         -1,
  60307         -1,
  60308     },
  60309 #endif /* chips */
  60310 
  60311 #if defined(BCM_88690_A0)
  60312     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88690_A0r */
  60313         soc_block_list[23],
  60314         soc_genreg,
  60315         4,
  60316         0,
  60317         0x1ce,
  60318         SOC_REG_FLAG_ABOVE_64_BITS |
  60319                           SOC_REG_FLAG_ARRAY |
  60320                           SOC_REG_FLAG_RO |
  60321                           SOC_REG_FLAG_WO |
  60322                           SOC_REG_FLAG_REG_ARRAY,
  60323         SOC_REG_FLAG_INIT_ON_READ,
  60324         2,
  60325         soc_BRDC_FMAC_RSF_STATUS_BCM88690_A0r_fields,
  60326         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60327         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60328         -1,
  60329         -1,
  60330     },
  60331 #endif /* chips */
  60332 
  60333 #if defined(BCM_88690_B0)
  60334     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88690_B0r */
  60335         soc_block_list[23],
  60336         soc_genreg,
  60337         4,
  60338         0,
  60339         0x1ce,
  60340         SOC_REG_FLAG_ABOVE_64_BITS |
  60341                           SOC_REG_FLAG_ARRAY |
  60342                           SOC_REG_FLAG_RO |
  60343                           SOC_REG_FLAG_WO |
  60344                           SOC_REG_FLAG_REG_ARRAY,
  60345         SOC_REG_FLAG_INIT_ON_READ,
  60346         2,
  60347         soc_BRDC_FMAC_RSF_STATUS_BCM88690_B0r_fields,
  60348         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60349         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60350         -1,
  60351         -1,
  60352     },
  60353 #endif /* chips */
  60354 
  60355 #if defined(BCM_88790_A0)
  60356     { /* SOC_REG_INT_BRDC_FMAC_RSF_STATUS_BCM88790_A0r */
  60357         soc_block_list[23],
  60358         soc_genreg,
  60359         4,
  60360         0,
  60361         0x1ce,
  60362         SOC_REG_FLAG_ABOVE_64_BITS |
  60363                           SOC_REG_FLAG_ARRAY |
  60364                           SOC_REG_FLAG_RO |
  60365                           SOC_REG_FLAG_WO |
  60366                           SOC_REG_FLAG_REG_ARRAY,
  60367         0,
  60368         2,
  60369         soc_BRDC_FMAC_RSF_STATUS_BCM88790_A0r_fields,
  60370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  60372         -1,
  60373         -1,
  60374     },
  60375 #endif /* chips */
  60376 
  60377 #if defined(BCM_88790_A0)
  60378     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_0r */
  60379         soc_block_list[23],
  60380         soc_genreg,
  60381         1,
  60382         0,
  60383         0x1e7,
  60384         SOC_REG_FLAG_WO,
  60385         0,
  60386         1,
  60387         soc_BRDC_FMAC_RX_LANE_SWAP_0r_fields,
  60388         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60389         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60390         -1,
  60391         -1,
  60392     },
  60393 #endif /* chips */
  60394 
  60395 #if defined(BCM_88790_A0)
  60396     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_1r */
  60397         soc_block_list[23],
  60398         soc_genreg,
  60399         1,
  60400         0,
  60401         0x1e8,
  60402         SOC_REG_FLAG_WO,
  60403         0,
  60404         1,
  60405         soc_BRDC_FMAC_RX_LANE_SWAP_1r_fields,
  60406         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  60407         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60408         -1,
  60409         -1,
  60410     },
  60411 #endif /* chips */
  60412 
  60413 #if defined(BCM_88790_A0)
  60414     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_2r */
  60415         soc_block_list[23],
  60416         soc_genreg,
  60417         1,
  60418         0,
  60419         0x1e9,
  60420         SOC_REG_FLAG_WO,
  60421         0,
  60422         1,
  60423         soc_BRDC_FMAC_RX_LANE_SWAP_2r_fields,
  60424         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  60425         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60426         -1,
  60427         -1,
  60428     },
  60429 #endif /* chips */
  60430 
  60431 #if defined(BCM_88790_A0)
  60432     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_3r */
  60433         soc_block_list[23],
  60434         soc_genreg,
  60435         1,
  60436         0,
  60437         0x1ea,
  60438         SOC_REG_FLAG_WO,
  60439         0,
  60440         1,
  60441         soc_BRDC_FMAC_RX_LANE_SWAP_3r_fields,
  60442         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  60443         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60444         -1,
  60445         -1,
  60446     },
  60447 #endif /* chips */
  60448 
  60449 #if defined(BCM_88690_A0)
  60450     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_0_BCM88690_A0r */
  60451         soc_block_list[23],
  60452         soc_genreg,
  60453         1,
  60454         0,
  60455         0x1e7,
  60456         SOC_REG_FLAG_WO,
  60457         0,
  60458         1,
  60459         soc_BRDC_FMAC_RX_LANE_SWAP_0_BCM88690_A0r_fields,
  60460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60461         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60462         -1,
  60463         -1,
  60464     },
  60465 #endif /* chips */
  60466 
  60467 #if defined(BCM_88690_B0)
  60468     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_0_BCM88690_B0r */
  60469         soc_block_list[23],
  60470         soc_genreg,
  60471         1,
  60472         0,
  60473         0x1e7,
  60474         SOC_REG_FLAG_WO,
  60475         0,
  60476         1,
  60477         soc_BRDC_FMAC_RX_LANE_SWAP_0_BCM88690_B0r_fields,
  60478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60479         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60480         -1,
  60481         -1,
  60482     },
  60483 #endif /* chips */
  60484 
  60485 #if defined(BCM_88690_A0)
  60486     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_1_BCM88690_A0r */
  60487         soc_block_list[23],
  60488         soc_genreg,
  60489         1,
  60490         0,
  60491         0x1e8,
  60492         SOC_REG_FLAG_WO,
  60493         0,
  60494         1,
  60495         soc_BRDC_FMAC_RX_LANE_SWAP_1_BCM88690_A0r_fields,
  60496         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  60497         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60498         -1,
  60499         -1,
  60500     },
  60501 #endif /* chips */
  60502 
  60503 #if defined(BCM_88690_B0)
  60504     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_1_BCM88690_B0r */
  60505         soc_block_list[23],
  60506         soc_genreg,
  60507         1,
  60508         0,
  60509         0x1e8,
  60510         SOC_REG_FLAG_WO,
  60511         0,
  60512         1,
  60513         soc_BRDC_FMAC_RX_LANE_SWAP_1_BCM88690_B0r_fields,
  60514         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  60515         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60516         -1,
  60517         -1,
  60518     },
  60519 #endif /* chips */
  60520 
  60521 #if defined(BCM_88690_A0)
  60522     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_2_BCM88690_A0r */
  60523         soc_block_list[23],
  60524         soc_genreg,
  60525         1,
  60526         0,
  60527         0x1e9,
  60528         SOC_REG_FLAG_WO,
  60529         0,
  60530         1,
  60531         soc_BRDC_FMAC_RX_LANE_SWAP_2_BCM88690_A0r_fields,
  60532         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  60533         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60534         -1,
  60535         -1,
  60536     },
  60537 #endif /* chips */
  60538 
  60539 #if defined(BCM_88690_B0)
  60540     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_2_BCM88690_B0r */
  60541         soc_block_list[23],
  60542         soc_genreg,
  60543         1,
  60544         0,
  60545         0x1e9,
  60546         SOC_REG_FLAG_WO,
  60547         0,
  60548         1,
  60549         soc_BRDC_FMAC_RX_LANE_SWAP_2_BCM88690_B0r_fields,
  60550         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  60551         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60552         -1,
  60553         -1,
  60554     },
  60555 #endif /* chips */
  60556 
  60557 #if defined(BCM_88690_A0)
  60558     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_3_BCM88690_A0r */
  60559         soc_block_list[23],
  60560         soc_genreg,
  60561         1,
  60562         0,
  60563         0x1ea,
  60564         SOC_REG_FLAG_WO,
  60565         0,
  60566         1,
  60567         soc_BRDC_FMAC_RX_LANE_SWAP_3_BCM88690_A0r_fields,
  60568         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  60569         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60570         -1,
  60571         -1,
  60572     },
  60573 #endif /* chips */
  60574 
  60575 #if defined(BCM_88690_B0)
  60576     { /* SOC_REG_INT_BRDC_FMAC_RX_LANE_SWAP_3_BCM88690_B0r */
  60577         soc_block_list[23],
  60578         soc_genreg,
  60579         1,
  60580         0,
  60581         0x1ea,
  60582         SOC_REG_FLAG_WO,
  60583         0,
  60584         1,
  60585         soc_BRDC_FMAC_RX_LANE_SWAP_3_BCM88690_B0r_fields,
  60586         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  60587         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  60588         -1,
  60589         -1,
  60590     },
  60591 #endif /* chips */
  60592 
  60593 #if defined(BCM_83208_A0)
  60594     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNTr */
  60595         soc_block_list[23],
  60596         soc_genreg,
  60597         4,
  60598         0,
  60599         0x11d,
  60600         SOC_REG_FLAG_ARRAY |
  60601                           SOC_REG_FLAG_RO |
  60602                           SOC_REG_FLAG_WO |
  60603                           SOC_REG_FLAG_REG_ARRAY,
  60604         0,
  60605         1,
  60606         soc_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNTr_fields,
  60607         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60608         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60609         -1,
  60610         -1,
  60611     },
  60612 #endif /* chips */
  60613 
  60614 #if defined(BCM_88690_A0)
  60615     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNT_BCM88690_A0r */
  60616         soc_block_list[23],
  60617         soc_genreg,
  60618         4,
  60619         0,
  60620         0x151,
  60621         SOC_REG_FLAG_ARRAY |
  60622                           SOC_REG_FLAG_RO |
  60623                           SOC_REG_FLAG_WO |
  60624                           SOC_REG_FLAG_REG_ARRAY,
  60625         SOC_REG_FLAG_COUNTER_FEILDS,
  60626         1,
  60627         soc_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNT_BCM88690_A0r_fields,
  60628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60629         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60630         -1,
  60631         -1,
  60632     },
  60633 #endif /* chips */
  60634 
  60635 #if defined(BCM_88690_B0)
  60636     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNT_BCM88690_B0r */
  60637         soc_block_list[23],
  60638         soc_genreg,
  60639         4,
  60640         0,
  60641         0x151,
  60642         SOC_REG_FLAG_ARRAY |
  60643                           SOC_REG_FLAG_RO |
  60644                           SOC_REG_FLAG_WO |
  60645                           SOC_REG_FLAG_REG_ARRAY,
  60646         SOC_REG_FLAG_COUNTER_FEILDS,
  60647         1,
  60648         soc_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNT_BCM88690_B0r_fields,
  60649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60650         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60651         -1,
  60652         -1,
  60653     },
  60654 #endif /* chips */
  60655 
  60656 #if defined(BCM_88790_A0)
  60657     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNT_BCM88790_A0r */
  60658         soc_block_list[23],
  60659         soc_genreg,
  60660         4,
  60661         0,
  60662         0x151,
  60663         SOC_REG_FLAG_ARRAY |
  60664                           SOC_REG_FLAG_RO |
  60665                           SOC_REG_FLAG_WO |
  60666                           SOC_REG_FLAG_REG_ARRAY,
  60667         SOC_REG_FLAG_COUNTER_FEILDS,
  60668         1,
  60669         soc_BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNT_BCM88790_A0r_fields,
  60670         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60672         -1,
  60673         -1,
  60674     },
  60675 #endif /* chips */
  60676 
  60677 #if defined(BCM_83208_A0)
  60678     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNTr */
  60679         soc_block_list[23],
  60680         soc_genreg,
  60681         4,
  60682         0,
  60683         0x118,
  60684         SOC_REG_FLAG_ARRAY |
  60685                           SOC_REG_FLAG_RO |
  60686                           SOC_REG_FLAG_WO |
  60687                           SOC_REG_FLAG_REG_ARRAY,
  60688         0,
  60689         1,
  60690         soc_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNTr_fields,
  60691         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60692         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60693         -1,
  60694         -1,
  60695     },
  60696 #endif /* chips */
  60697 
  60698 #if defined(BCM_88690_A0)
  60699     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT_BCM88690_A0r */
  60700         soc_block_list[23],
  60701         soc_genreg,
  60702         4,
  60703         0,
  60704         0x14c,
  60705         SOC_REG_FLAG_ARRAY |
  60706                           SOC_REG_FLAG_RO |
  60707                           SOC_REG_FLAG_WO |
  60708                           SOC_REG_FLAG_REG_ARRAY,
  60709         SOC_REG_FLAG_COUNTER_FEILDS,
  60710         1,
  60711         soc_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT_BCM88690_A0r_fields,
  60712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60713         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60714         -1,
  60715         -1,
  60716     },
  60717 #endif /* chips */
  60718 
  60719 #if defined(BCM_88690_B0)
  60720     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT_BCM88690_B0r */
  60721         soc_block_list[23],
  60722         soc_genreg,
  60723         4,
  60724         0,
  60725         0x14c,
  60726         SOC_REG_FLAG_ARRAY |
  60727                           SOC_REG_FLAG_RO |
  60728                           SOC_REG_FLAG_WO |
  60729                           SOC_REG_FLAG_REG_ARRAY,
  60730         SOC_REG_FLAG_COUNTER_FEILDS,
  60731         1,
  60732         soc_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT_BCM88690_B0r_fields,
  60733         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60734         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60735         -1,
  60736         -1,
  60737     },
  60738 #endif /* chips */
  60739 
  60740 #if defined(BCM_88790_A0)
  60741     { /* SOC_REG_INT_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT_BCM88790_A0r */
  60742         soc_block_list[23],
  60743         soc_genreg,
  60744         4,
  60745         0,
  60746         0x14c,
  60747         SOC_REG_FLAG_ARRAY |
  60748                           SOC_REG_FLAG_RO |
  60749                           SOC_REG_FLAG_WO |
  60750                           SOC_REG_FLAG_REG_ARRAY,
  60751         SOC_REG_FLAG_COUNTER_FEILDS,
  60752         1,
  60753         soc_BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT_BCM88790_A0r_fields,
  60754         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60755         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  60756         -1,
  60757         -1,
  60758     },
  60759 #endif /* chips */
  60760 
  60761 #if defined(BCM_88650_A0)
  60762     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_IDr */
  60763         soc_block_list[23],
  60764         soc_genreg,
  60765         1,
  60766         0,
  60767         0x55,
  60768         SOC_REG_FLAG_WO,
  60769         0,
  60770         1,
  60771         soc_BRDC_FMAC_SBUS_BROADCAST_IDr_fields,
  60772         SOC_RESET_VAL_DEC(0x0000003d, 0x00000000)
  60773         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60774         -1,
  60775         -1,
  60776     },
  60777 #endif /* chips */
  60778 
  60779 #if defined(BCM_83208_A0)
  60780     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM83208_A0r */
  60781         soc_block_list[23],
  60782         soc_genreg,
  60783         1,
  60784         0,
  60785         0x86,
  60786         SOC_REG_FLAG_WO,
  60787         0,
  60788         1,
  60789         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM83208_A0r_fields,
  60790         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60791         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60792         -1,
  60793         -1,
  60794     },
  60795 #endif /* chips */
  60796 
  60797 #if defined(BCM_88202_A0)
  60798     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88202_A0r */
  60799         soc_block_list[23],
  60800         soc_genreg,
  60801         1,
  60802         0,
  60803         0x55,
  60804         SOC_REG_FLAG_WO,
  60805         0,
  60806         1,
  60807         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88202_A0r_fields,
  60808         SOC_RESET_VAL_DEC(0x0000003d, 0x00000000)
  60809         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60810         -1,
  60811         -1,
  60812     },
  60813 #endif /* chips */
  60814 
  60815 #if defined(BCM_88375_A0)
  60816     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88375_A0r */
  60817         soc_block_list[23],
  60818         soc_genreg,
  60819         1,
  60820         0,
  60821         0x86,
  60822         SOC_REG_FLAG_WO,
  60823         0,
  60824         1,
  60825         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88375_A0r_fields,
  60826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60827         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60828         -1,
  60829         -1,
  60830     },
  60831 #endif /* chips */
  60832 
  60833 #if defined(BCM_88375_B0)
  60834     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88375_B0r */
  60835         soc_block_list[23],
  60836         soc_genreg,
  60837         1,
  60838         0,
  60839         0x86,
  60840         SOC_REG_FLAG_WO,
  60841         0,
  60842         1,
  60843         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88375_B0r_fields,
  60844         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60845         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60846         -1,
  60847         -1,
  60848     },
  60849 #endif /* chips */
  60850 
  60851 #if defined(BCM_88470_A0)
  60852     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88470_A0r */
  60853         soc_block_list[23],
  60854         soc_genreg,
  60855         1,
  60856         0,
  60857         0x86,
  60858         SOC_REG_FLAG_WO,
  60859         0,
  60860         1,
  60861         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88470_A0r_fields,
  60862         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  60863         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60864         -1,
  60865         -1,
  60866     },
  60867 #endif /* chips */
  60868 
  60869 #if defined(BCM_88470_B0)
  60870     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88470_B0r */
  60871         soc_block_list[23],
  60872         soc_genreg,
  60873         1,
  60874         0,
  60875         0x86,
  60876         SOC_REG_FLAG_WO,
  60877         0,
  60878         1,
  60879         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88470_B0r_fields,
  60880         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  60881         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60882         -1,
  60883         -1,
  60884     },
  60885 #endif /* chips */
  60886 
  60887 #if defined(BCM_88650_B0)
  60888     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88650_B0r */
  60889         soc_block_list[23],
  60890         soc_genreg,
  60891         1,
  60892         0,
  60893         0x55,
  60894         SOC_REG_FLAG_WO,
  60895         0,
  60896         1,
  60897         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88650_B0r_fields,
  60898         SOC_RESET_VAL_DEC(0x0000003d, 0x00000000)
  60899         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60900         -1,
  60901         -1,
  60902     },
  60903 #endif /* chips */
  60904 
  60905 #if defined(BCM_88660_A0)
  60906     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88660_A0r */
  60907         soc_block_list[23],
  60908         soc_genreg,
  60909         1,
  60910         0,
  60911         0x55,
  60912         SOC_REG_FLAG_WO,
  60913         0,
  60914         1,
  60915         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88660_A0r_fields,
  60916         SOC_RESET_VAL_DEC(0x0000003d, 0x00000000)
  60917         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  60918         -1,
  60919         -1,
  60920     },
  60921 #endif /* chips */
  60922 
  60923 #if defined(BCM_88675_A0)
  60924     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88675_A0r */
  60925         soc_block_list[23],
  60926         soc_genreg,
  60927         1,
  60928         0,
  60929         0x86,
  60930         SOC_REG_FLAG_WO,
  60931         0,
  60932         1,
  60933         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88675_A0r_fields,
  60934         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60935         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60936         -1,
  60937         -1,
  60938     },
  60939 #endif /* chips */
  60940 
  60941 #if defined(BCM_88675_B0)
  60942     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88675_B0r */
  60943         soc_block_list[23],
  60944         soc_genreg,
  60945         1,
  60946         0,
  60947         0x86,
  60948         SOC_REG_FLAG_WO,
  60949         0,
  60950         1,
  60951         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88675_B0r_fields,
  60952         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60953         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60954         -1,
  60955         -1,
  60956     },
  60957 #endif /* chips */
  60958 
  60959 #if defined(BCM_88680_A0)
  60960     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88680_A0r */
  60961         soc_block_list[23],
  60962         soc_genreg,
  60963         1,
  60964         0,
  60965         0x86,
  60966         SOC_REG_FLAG_WO,
  60967         0,
  60968         1,
  60969         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88680_A0r_fields,
  60970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  60971         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60972         -1,
  60973         -1,
  60974     },
  60975 #endif /* chips */
  60976 
  60977 #if defined(BCM_88690_A0)
  60978     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88690_A0r */
  60979         soc_block_list[23],
  60980         soc_genreg,
  60981         1,
  60982         0,
  60983         0x86,
  60984         SOC_REG_FLAG_WO,
  60985         0,
  60986         1,
  60987         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88690_A0r_fields,
  60988         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  60989         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  60990         -1,
  60991         -1,
  60992     },
  60993 #endif /* chips */
  60994 
  60995 #if defined(BCM_88690_B0)
  60996     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88690_B0r */
  60997         soc_block_list[23],
  60998         soc_genreg,
  60999         1,
  61000         0,
  61001         0x86,
  61002         SOC_REG_FLAG_WO,
  61003         0,
  61004         1,
  61005         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
  61006         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  61007         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  61008         -1,
  61009         -1,
  61010     },
  61011 #endif /* chips */
  61012 
  61013 #if defined(BCM_88790_A0)
  61014     { /* SOC_REG_INT_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88790_A0r */
  61015         soc_block_list[23],
  61016         soc_genreg,
  61017         1,
  61018         0,
  61019         0x86,
  61020         SOC_REG_FLAG_WO,
  61021         0,
  61022         1,
  61023         soc_BRDC_FMAC_SBUS_BROADCAST_ID_BCM88790_A0r_fields,
  61024         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  61025         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  61026         -1,
  61027         -1,
  61028     },
  61029 #endif /* chips */
  61030 
  61031 #if defined(BCM_88675_A0)
  61032     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAINr */
  61033         soc_block_list[23],
  61034         soc_genreg,
  61035         1,
  61036         0,
  61037         0x87,
  61038         SOC_REG_FLAG_WO,
  61039         0,
  61040         1,
  61041         soc_BRDC_FMAC_SBUS_LAST_IN_CHAINr_fields,
  61042         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61043         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61044         -1,
  61045         -1,
  61046     },
  61047 #endif /* chips */
  61048 
  61049 #if defined(BCM_83208_A0)
  61050     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM83208_A0r */
  61051         soc_block_list[23],
  61052         soc_genreg,
  61053         1,
  61054         0,
  61055         0x87,
  61056         SOC_REG_FLAG_WO,
  61057         0,
  61058         1,
  61059         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM83208_A0r_fields,
  61060         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61061         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61062         -1,
  61063         -1,
  61064     },
  61065 #endif /* chips */
  61066 
  61067 #if defined(BCM_88375_A0)
  61068     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88375_A0r */
  61069         soc_block_list[23],
  61070         soc_genreg,
  61071         1,
  61072         0,
  61073         0x87,
  61074         SOC_REG_FLAG_WO,
  61075         0,
  61076         1,
  61077         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88375_A0r_fields,
  61078         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61079         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61080         -1,
  61081         -1,
  61082     },
  61083 #endif /* chips */
  61084 
  61085 #if defined(BCM_88375_B0)
  61086     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88375_B0r */
  61087         soc_block_list[23],
  61088         soc_genreg,
  61089         1,
  61090         0,
  61091         0x87,
  61092         SOC_REG_FLAG_WO,
  61093         0,
  61094         1,
  61095         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88375_B0r_fields,
  61096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61097         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61098         -1,
  61099         -1,
  61100     },
  61101 #endif /* chips */
  61102 
  61103 #if defined(BCM_88470_A0)
  61104     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88470_A0r */
  61105         soc_block_list[23],
  61106         soc_genreg,
  61107         1,
  61108         0,
  61109         0x87,
  61110         SOC_REG_FLAG_WO,
  61111         0,
  61112         1,
  61113         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88470_A0r_fields,
  61114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61115         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61116         -1,
  61117         -1,
  61118     },
  61119 #endif /* chips */
  61120 
  61121 #if defined(BCM_88470_B0)
  61122     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88470_B0r */
  61123         soc_block_list[23],
  61124         soc_genreg,
  61125         1,
  61126         0,
  61127         0x87,
  61128         SOC_REG_FLAG_WO,
  61129         0,
  61130         1,
  61131         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88470_B0r_fields,
  61132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61133         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61134         -1,
  61135         -1,
  61136     },
  61137 #endif /* chips */
  61138 
  61139 #if defined(BCM_88675_B0)
  61140     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88675_B0r */
  61141         soc_block_list[23],
  61142         soc_genreg,
  61143         1,
  61144         0,
  61145         0x87,
  61146         SOC_REG_FLAG_WO,
  61147         0,
  61148         1,
  61149         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88675_B0r_fields,
  61150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61151         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61152         -1,
  61153         -1,
  61154     },
  61155 #endif /* chips */
  61156 
  61157 #if defined(BCM_88680_A0)
  61158     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88680_A0r */
  61159         soc_block_list[23],
  61160         soc_genreg,
  61161         1,
  61162         0,
  61163         0x87,
  61164         SOC_REG_FLAG_WO,
  61165         0,
  61166         1,
  61167         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88680_A0r_fields,
  61168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61169         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61170         -1,
  61171         -1,
  61172     },
  61173 #endif /* chips */
  61174 
  61175 #if defined(BCM_88690_A0)
  61176     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88690_A0r */
  61177         soc_block_list[23],
  61178         soc_genreg,
  61179         1,
  61180         0,
  61181         0x87,
  61182         SOC_REG_FLAG_WO,
  61183         0,
  61184         1,
  61185         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88690_A0r_fields,
  61186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61187         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61188         -1,
  61189         -1,
  61190     },
  61191 #endif /* chips */
  61192 
  61193 #if defined(BCM_88690_B0)
  61194     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
  61195         soc_block_list[23],
  61196         soc_genreg,
  61197         1,
  61198         0,
  61199         0x87,
  61200         SOC_REG_FLAG_WO,
  61201         0,
  61202         1,
  61203         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
  61204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61205         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61206         -1,
  61207         -1,
  61208     },
  61209 #endif /* chips */
  61210 
  61211 #if defined(BCM_88790_A0)
  61212     { /* SOC_REG_INT_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88790_A0r */
  61213         soc_block_list[23],
  61214         soc_genreg,
  61215         1,
  61216         0,
  61217         0x87,
  61218         SOC_REG_FLAG_WO,
  61219         0,
  61220         1,
  61221         soc_BRDC_FMAC_SBUS_LAST_IN_CHAIN_BCM88790_A0r_fields,
  61222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61223         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  61224         -1,
  61225         -1,
  61226     },
  61227 #endif /* chips */
  61228 
  61229 #if defined(BCM_88660_A0)
  61230     { /* SOC_REG_INT_BRDC_FMAC_SPARE_REGISTER_2r */
  61231         soc_block_list[23],
  61232         soc_genreg,
  61233         1,
  61234         0,
  61235         0x52,
  61236         SOC_REG_FLAG_WO,
  61237         0,
  61238         6,
  61239         soc_BRDC_FMAC_SPARE_REGISTER_2r_fields,
  61240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61241         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61242         -1,
  61243         -1,
  61244     },
  61245 #endif /* chips */
  61246 
  61247 #if defined(BCM_88690_B0)
  61248     { /* SOC_REG_INT_BRDC_FMAC_SPECIAL_CLOCK_CONTROLSr */
  61249         soc_block_list[23],
  61250         soc_genreg,
  61251         1,
  61252         0,
  61253         0xc1,
  61254         SOC_REG_FLAG_WO,
  61255         0,
  61256         1,
  61257         soc_BRDC_FMAC_SPECIAL_CLOCK_CONTROLSr_fields,
  61258         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  61259         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
  61260         -1,
  61261         -1,
  61262     },
  61263 #endif /* chips */
  61264 
  61265 #if defined(BCM_88650_A0)
  61266     { /* SOC_REG_INT_BRDC_FMAC_TEST_CONFIGURATIONr */
  61267         soc_block_list[23],
  61268         soc_genreg,
  61269         4,
  61270         0,
  61271         0x1b0,
  61272         SOC_REG_FLAG_ARRAY |
  61273                           SOC_REG_FLAG_WO |
  61274                           SOC_REG_FLAG_REG_ARRAY,
  61275         0,
  61276         4,
  61277         soc_BRDC_FMAC_TEST_CONFIGURATIONr_fields,
  61278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61279         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  61280         -1,
  61281         -1,
  61282     },
  61283 #endif /* chips */
  61284 
  61285 #if defined(BCM_88202_A0)
  61286     { /* SOC_REG_INT_BRDC_FMAC_TEST_CONFIGURATION_BCM88202_A0r */
  61287         soc_block_list[23],
  61288         soc_genreg,
  61289         4,
  61290         0,
  61291         0x1b0,
  61292         SOC_REG_FLAG_ARRAY |
  61293                           SOC_REG_FLAG_WO |
  61294                           SOC_REG_FLAG_REG_ARRAY,
  61295         0,
  61296         4,
  61297         soc_BRDC_FMAC_TEST_CONFIGURATION_BCM88202_A0r_fields,
  61298         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61299         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  61300         -1,
  61301         -1,
  61302     },
  61303 #endif /* chips */
  61304 
  61305 #if defined(BCM_88650_B0)
  61306     { /* SOC_REG_INT_BRDC_FMAC_TEST_CONFIGURATION_BCM88650_B0r */
  61307         soc_block_list[23],
  61308         soc_genreg,
  61309         4,
  61310         0,
  61311         0x1b0,
  61312         SOC_REG_FLAG_ARRAY |
  61313                           SOC_REG_FLAG_WO |
  61314                           SOC_REG_FLAG_REG_ARRAY,
  61315         0,
  61316         4,
  61317         soc_BRDC_FMAC_TEST_CONFIGURATION_BCM88650_B0r_fields,
  61318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61319         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  61320         -1,
  61321         -1,
  61322     },
  61323 #endif /* chips */
  61324 
  61325 #if defined(BCM_88660_A0)
  61326     { /* SOC_REG_INT_BRDC_FMAC_TEST_CONFIGURATION_BCM88660_A0r */
  61327         soc_block_list[23],
  61328         soc_genreg,
  61329         4,
  61330         0,
  61331         0x1b0,
  61332         SOC_REG_FLAG_ARRAY |
  61333                           SOC_REG_FLAG_WO |
  61334                           SOC_REG_FLAG_REG_ARRAY,
  61335         0,
  61336         4,
  61337         soc_BRDC_FMAC_TEST_CONFIGURATION_BCM88660_A0r_fields,
  61338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61339         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  61340         -1,
  61341         -1,
  61342     },
  61343 #endif /* chips */
  61344 
  61345 #if defined(BCM_88650_A0)
  61346     { /* SOC_REG_INT_BRDC_FMAC_TEST_STATUSr */
  61347         soc_block_list[23],
  61348         soc_genreg,
  61349         4,
  61350         0,
  61351         0x1b4,
  61352         SOC_REG_FLAG_ARRAY |
  61353                           SOC_REG_FLAG_WO |
  61354                           SOC_REG_FLAG_REG_ARRAY,
  61355         0,
  61356         3,
  61357         soc_BRDC_FMAC_TEST_STATUSr_fields,
  61358         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61359         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61360         -1,
  61361         -1,
  61362     },
  61363 #endif /* chips */
  61364 
  61365 #if defined(BCM_88202_A0)
  61366     { /* SOC_REG_INT_BRDC_FMAC_TEST_STATUS_BCM88202_A0r */
  61367         soc_block_list[23],
  61368         soc_genreg,
  61369         4,
  61370         0,
  61371         0x1b4,
  61372         SOC_REG_FLAG_ARRAY |
  61373                           SOC_REG_FLAG_WO |
  61374                           SOC_REG_FLAG_REG_ARRAY,
  61375         0,
  61376         3,
  61377         soc_BRDC_FMAC_TEST_STATUS_BCM88202_A0r_fields,
  61378         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61380         -1,
  61381         -1,
  61382     },
  61383 #endif /* chips */
  61384 
  61385 #if defined(BCM_88650_B0)
  61386     { /* SOC_REG_INT_BRDC_FMAC_TEST_STATUS_BCM88650_B0r */
  61387         soc_block_list[23],
  61388         soc_genreg,
  61389         4,
  61390         0,
  61391         0x1b4,
  61392         SOC_REG_FLAG_ARRAY |
  61393                           SOC_REG_FLAG_WO |
  61394                           SOC_REG_FLAG_REG_ARRAY,
  61395         0,
  61396         3,
  61397         soc_BRDC_FMAC_TEST_STATUS_BCM88650_B0r_fields,
  61398         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61399         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61400         -1,
  61401         -1,
  61402     },
  61403 #endif /* chips */
  61404 
  61405 #if defined(BCM_88660_A0)
  61406     { /* SOC_REG_INT_BRDC_FMAC_TEST_STATUS_BCM88660_A0r */
  61407         soc_block_list[23],
  61408         soc_genreg,
  61409         4,
  61410         0,
  61411         0x1b4,
  61412         SOC_REG_FLAG_ARRAY |
  61413                           SOC_REG_FLAG_WO |
  61414                           SOC_REG_FLAG_REG_ARRAY,
  61415         0,
  61416         3,
  61417         soc_BRDC_FMAC_TEST_STATUS_BCM88660_A0r_fields,
  61418         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61419         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61420         -1,
  61421         -1,
  61422     },
  61423 #endif /* chips */
  61424 
  61425 #if defined(BCM_88650_A0)
  61426     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMITr */
  61427         soc_block_list[23],
  61428         soc_genreg,
  61429         1,
  61430         0,
  61431         0x67,
  61432         SOC_REG_FLAG_WO,
  61433         0,
  61434         2,
  61435         soc_BRDC_FMAC_TX_CELL_LIMITr_fields,
  61436         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61437         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  61438         -1,
  61439         -1,
  61440     },
  61441 #endif /* chips */
  61442 
  61443 #if defined(BCM_83208_A0)
  61444     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM83208_A0r */
  61445         soc_block_list[23],
  61446         soc_genreg,
  61447         1,
  61448         0,
  61449         0x10a,
  61450         SOC_REG_FLAG_64_BITS |
  61451                           SOC_REG_FLAG_WO,
  61452         0,
  61453         4,
  61454         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM83208_A0r_fields,
  61455         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61456         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  61457         -1,
  61458         -1,
  61459     },
  61460 #endif /* chips */
  61461 
  61462 #if defined(BCM_88202_A0)
  61463     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88202_A0r */
  61464         soc_block_list[23],
  61465         soc_genreg,
  61466         1,
  61467         0,
  61468         0x67,
  61469         SOC_REG_FLAG_WO,
  61470         0,
  61471         2,
  61472         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88202_A0r_fields,
  61473         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61474         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  61475         -1,
  61476         -1,
  61477     },
  61478 #endif /* chips */
  61479 
  61480 #if defined(BCM_88375_A0)
  61481     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88375_A0r */
  61482         soc_block_list[23],
  61483         soc_genreg,
  61484         1,
  61485         0,
  61486         0x10a,
  61487         SOC_REG_FLAG_64_BITS |
  61488                           SOC_REG_FLAG_WO,
  61489         0,
  61490         3,
  61491         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88375_A0r_fields,
  61492         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61493         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  61494         -1,
  61495         -1,
  61496     },
  61497 #endif /* chips */
  61498 
  61499 #if defined(BCM_88375_B0)
  61500     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88375_B0r */
  61501         soc_block_list[23],
  61502         soc_genreg,
  61503         1,
  61504         0,
  61505         0x10a,
  61506         SOC_REG_FLAG_64_BITS |
  61507                           SOC_REG_FLAG_WO,
  61508         0,
  61509         3,
  61510         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88375_B0r_fields,
  61511         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61512         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  61513         -1,
  61514         -1,
  61515     },
  61516 #endif /* chips */
  61517 
  61518 #if defined(BCM_88470_A0)
  61519     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88470_A0r */
  61520         soc_block_list[23],
  61521         soc_genreg,
  61522         1,
  61523         0,
  61524         0x10a,
  61525         SOC_REG_FLAG_64_BITS |
  61526                           SOC_REG_FLAG_WO,
  61527         0,
  61528         3,
  61529         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88470_A0r_fields,
  61530         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61531         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  61532         -1,
  61533         -1,
  61534     },
  61535 #endif /* chips */
  61536 
  61537 #if defined(BCM_88470_B0)
  61538     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88470_B0r */
  61539         soc_block_list[23],
  61540         soc_genreg,
  61541         1,
  61542         0,
  61543         0x10a,
  61544         SOC_REG_FLAG_64_BITS |
  61545                           SOC_REG_FLAG_WO,
  61546         0,
  61547         3,
  61548         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88470_B0r_fields,
  61549         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61550         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  61551         -1,
  61552         -1,
  61553     },
  61554 #endif /* chips */
  61555 
  61556 #if defined(BCM_88650_B0)
  61557     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88650_B0r */
  61558         soc_block_list[23],
  61559         soc_genreg,
  61560         1,
  61561         0,
  61562         0x67,
  61563         SOC_REG_FLAG_WO,
  61564         0,
  61565         2,
  61566         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88650_B0r_fields,
  61567         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61568         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  61569         -1,
  61570         -1,
  61571     },
  61572 #endif /* chips */
  61573 
  61574 #if defined(BCM_88660_A0)
  61575     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88660_A0r */
  61576         soc_block_list[23],
  61577         soc_genreg,
  61578         1,
  61579         0,
  61580         0x67,
  61581         SOC_REG_FLAG_WO,
  61582         0,
  61583         2,
  61584         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88660_A0r_fields,
  61585         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61586         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  61587         -1,
  61588         -1,
  61589     },
  61590 #endif /* chips */
  61591 
  61592 #if defined(BCM_88675_A0)
  61593     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88675_A0r */
  61594         soc_block_list[23],
  61595         soc_genreg,
  61596         1,
  61597         0,
  61598         0x10a,
  61599         SOC_REG_FLAG_64_BITS |
  61600                           SOC_REG_FLAG_WO,
  61601         0,
  61602         3,
  61603         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88675_A0r_fields,
  61604         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61605         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  61606         -1,
  61607         -1,
  61608     },
  61609 #endif /* chips */
  61610 
  61611 #if defined(BCM_88675_B0)
  61612     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88675_B0r */
  61613         soc_block_list[23],
  61614         soc_genreg,
  61615         1,
  61616         0,
  61617         0x10a,
  61618         SOC_REG_FLAG_64_BITS |
  61619                           SOC_REG_FLAG_WO,
  61620         0,
  61621         3,
  61622         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88675_B0r_fields,
  61623         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61624         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  61625         -1,
  61626         -1,
  61627     },
  61628 #endif /* chips */
  61629 
  61630 #if defined(BCM_88680_A0)
  61631     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88680_A0r */
  61632         soc_block_list[23],
  61633         soc_genreg,
  61634         1,
  61635         0,
  61636         0x10a,
  61637         SOC_REG_FLAG_64_BITS |
  61638                           SOC_REG_FLAG_WO,
  61639         0,
  61640         3,
  61641         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88680_A0r_fields,
  61642         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61643         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  61644         -1,
  61645         -1,
  61646     },
  61647 #endif /* chips */
  61648 
  61649 #if defined(BCM_88690_A0)
  61650     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88690_A0r */
  61651         soc_block_list[23],
  61652         soc_genreg,
  61653         1,
  61654         0,
  61655         0x12a,
  61656         SOC_REG_FLAG_64_BITS |
  61657                           SOC_REG_FLAG_WO,
  61658         0,
  61659         4,
  61660         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88690_A0r_fields,
  61661         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61662         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  61663         -1,
  61664         -1,
  61665     },
  61666 #endif /* chips */
  61667 
  61668 #if defined(BCM_88690_B0)
  61669     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88690_B0r */
  61670         soc_block_list[23],
  61671         soc_genreg,
  61672         1,
  61673         0,
  61674         0x12a,
  61675         SOC_REG_FLAG_64_BITS |
  61676                           SOC_REG_FLAG_WO,
  61677         0,
  61678         4,
  61679         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88690_B0r_fields,
  61680         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  61682         -1,
  61683         -1,
  61684     },
  61685 #endif /* chips */
  61686 
  61687 #if defined(BCM_88790_A0)
  61688     { /* SOC_REG_INT_BRDC_FMAC_TX_CELL_LIMIT_BCM88790_A0r */
  61689         soc_block_list[23],
  61690         soc_genreg,
  61691         1,
  61692         0,
  61693         0x12a,
  61694         SOC_REG_FLAG_64_BITS |
  61695                           SOC_REG_FLAG_WO,
  61696         0,
  61697         4,
  61698         soc_BRDC_FMAC_TX_CELL_LIMIT_BCM88790_A0r_fields,
  61699         SOC_RESET_VAL_DEC(0x00000006, 0x00000000)
  61700         SOC_RESET_MASK_DEC(0xffffffff, 0x00000003)
  61701         -1,
  61702         -1,
  61703     },
  61704 #endif /* chips */
  61705 
  61706 #if defined(BCM_83208_A0)
  61707     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_0r */
  61708         soc_block_list[23],
  61709         soc_genreg,
  61710         1,
  61711         0,
  61712         0x14e,
  61713         SOC_REG_FLAG_WO,
  61714         0,
  61715         1,
  61716         soc_BRDC_FMAC_TX_LANE_SWAP_0r_fields,
  61717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61718         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61719         -1,
  61720         -1,
  61721     },
  61722 #endif /* chips */
  61723 
  61724 #if defined(BCM_83208_A0)
  61725     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_1r */
  61726         soc_block_list[23],
  61727         soc_genreg,
  61728         1,
  61729         0,
  61730         0x14f,
  61731         SOC_REG_FLAG_WO,
  61732         0,
  61733         1,
  61734         soc_BRDC_FMAC_TX_LANE_SWAP_1r_fields,
  61735         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  61736         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61737         -1,
  61738         -1,
  61739     },
  61740 #endif /* chips */
  61741 
  61742 #if defined(BCM_83208_A0)
  61743     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_2r */
  61744         soc_block_list[23],
  61745         soc_genreg,
  61746         1,
  61747         0,
  61748         0x150,
  61749         SOC_REG_FLAG_WO,
  61750         0,
  61751         1,
  61752         soc_BRDC_FMAC_TX_LANE_SWAP_2r_fields,
  61753         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  61754         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61755         -1,
  61756         -1,
  61757     },
  61758 #endif /* chips */
  61759 
  61760 #if defined(BCM_83208_A0)
  61761     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_3r */
  61762         soc_block_list[23],
  61763         soc_genreg,
  61764         1,
  61765         0,
  61766         0x151,
  61767         SOC_REG_FLAG_WO,
  61768         0,
  61769         1,
  61770         soc_BRDC_FMAC_TX_LANE_SWAP_3r_fields,
  61771         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  61772         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61773         -1,
  61774         -1,
  61775     },
  61776 #endif /* chips */
  61777 
  61778 #if defined(BCM_88690_A0)
  61779     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_0_BCM88690_A0r */
  61780         soc_block_list[23],
  61781         soc_genreg,
  61782         1,
  61783         0,
  61784         0x18a,
  61785         SOC_REG_FLAG_WO,
  61786         0,
  61787         1,
  61788         soc_BRDC_FMAC_TX_LANE_SWAP_0_BCM88690_A0r_fields,
  61789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61790         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61791         -1,
  61792         -1,
  61793     },
  61794 #endif /* chips */
  61795 
  61796 #if defined(BCM_88690_B0)
  61797     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_0_BCM88690_B0r */
  61798         soc_block_list[23],
  61799         soc_genreg,
  61800         1,
  61801         0,
  61802         0x18a,
  61803         SOC_REG_FLAG_WO,
  61804         0,
  61805         1,
  61806         soc_BRDC_FMAC_TX_LANE_SWAP_0_BCM88690_B0r_fields,
  61807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61808         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61809         -1,
  61810         -1,
  61811     },
  61812 #endif /* chips */
  61813 
  61814 #if defined(BCM_88790_A0)
  61815     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_0_BCM88790_A0r */
  61816         soc_block_list[23],
  61817         soc_genreg,
  61818         1,
  61819         0,
  61820         0x18a,
  61821         SOC_REG_FLAG_WO,
  61822         0,
  61823         1,
  61824         soc_BRDC_FMAC_TX_LANE_SWAP_0_BCM88790_A0r_fields,
  61825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  61826         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61827         -1,
  61828         -1,
  61829     },
  61830 #endif /* chips */
  61831 
  61832 #if defined(BCM_88690_A0)
  61833     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_1_BCM88690_A0r */
  61834         soc_block_list[23],
  61835         soc_genreg,
  61836         1,
  61837         0,
  61838         0x18b,
  61839         SOC_REG_FLAG_WO,
  61840         0,
  61841         1,
  61842         soc_BRDC_FMAC_TX_LANE_SWAP_1_BCM88690_A0r_fields,
  61843         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  61844         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61845         -1,
  61846         -1,
  61847     },
  61848 #endif /* chips */
  61849 
  61850 #if defined(BCM_88690_B0)
  61851     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_1_BCM88690_B0r */
  61852         soc_block_list[23],
  61853         soc_genreg,
  61854         1,
  61855         0,
  61856         0x18b,
  61857         SOC_REG_FLAG_WO,
  61858         0,
  61859         1,
  61860         soc_BRDC_FMAC_TX_LANE_SWAP_1_BCM88690_B0r_fields,
  61861         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  61862         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61863         -1,
  61864         -1,
  61865     },
  61866 #endif /* chips */
  61867 
  61868 #if defined(BCM_88790_A0)
  61869     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_1_BCM88790_A0r */
  61870         soc_block_list[23],
  61871         soc_genreg,
  61872         1,
  61873         0,
  61874         0x18b,
  61875         SOC_REG_FLAG_WO,
  61876         0,
  61877         1,
  61878         soc_BRDC_FMAC_TX_LANE_SWAP_1_BCM88790_A0r_fields,
  61879         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  61880         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61881         -1,
  61882         -1,
  61883     },
  61884 #endif /* chips */
  61885 
  61886 #if defined(BCM_88690_A0)
  61887     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_2_BCM88690_A0r */
  61888         soc_block_list[23],
  61889         soc_genreg,
  61890         1,
  61891         0,
  61892         0x18c,
  61893         SOC_REG_FLAG_WO,
  61894         0,
  61895         1,
  61896         soc_BRDC_FMAC_TX_LANE_SWAP_2_BCM88690_A0r_fields,
  61897         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  61898         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61899         -1,
  61900         -1,
  61901     },
  61902 #endif /* chips */
  61903 
  61904 #if defined(BCM_88690_B0)
  61905     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_2_BCM88690_B0r */
  61906         soc_block_list[23],
  61907         soc_genreg,
  61908         1,
  61909         0,
  61910         0x18c,
  61911         SOC_REG_FLAG_WO,
  61912         0,
  61913         1,
  61914         soc_BRDC_FMAC_TX_LANE_SWAP_2_BCM88690_B0r_fields,
  61915         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  61916         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61917         -1,
  61918         -1,
  61919     },
  61920 #endif /* chips */
  61921 
  61922 #if defined(BCM_88790_A0)
  61923     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_2_BCM88790_A0r */
  61924         soc_block_list[23],
  61925         soc_genreg,
  61926         1,
  61927         0,
  61928         0x18c,
  61929         SOC_REG_FLAG_WO,
  61930         0,
  61931         1,
  61932         soc_BRDC_FMAC_TX_LANE_SWAP_2_BCM88790_A0r_fields,
  61933         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  61934         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61935         -1,
  61936         -1,
  61937     },
  61938 #endif /* chips */
  61939 
  61940 #if defined(BCM_88690_A0)
  61941     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_3_BCM88690_A0r */
  61942         soc_block_list[23],
  61943         soc_genreg,
  61944         1,
  61945         0,
  61946         0x18d,
  61947         SOC_REG_FLAG_WO,
  61948         0,
  61949         1,
  61950         soc_BRDC_FMAC_TX_LANE_SWAP_3_BCM88690_A0r_fields,
  61951         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  61952         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61953         -1,
  61954         -1,
  61955     },
  61956 #endif /* chips */
  61957 
  61958 #if defined(BCM_88690_B0)
  61959     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_3_BCM88690_B0r */
  61960         soc_block_list[23],
  61961         soc_genreg,
  61962         1,
  61963         0,
  61964         0x18d,
  61965         SOC_REG_FLAG_WO,
  61966         0,
  61967         1,
  61968         soc_BRDC_FMAC_TX_LANE_SWAP_3_BCM88690_B0r_fields,
  61969         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  61970         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61971         -1,
  61972         -1,
  61973     },
  61974 #endif /* chips */
  61975 
  61976 #if defined(BCM_88790_A0)
  61977     { /* SOC_REG_INT_BRDC_FMAC_TX_LANE_SWAP_3_BCM88790_A0r */
  61978         soc_block_list[23],
  61979         soc_genreg,
  61980         1,
  61981         0,
  61982         0x18d,
  61983         SOC_REG_FLAG_WO,
  61984         0,
  61985         1,
  61986         soc_BRDC_FMAC_TX_LANE_SWAP_3_BCM88790_A0r_fields,
  61987         SOC_RESET_VAL_DEC(0x00000003, 0x00000000)
  61988         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  61989         -1,
  61990         -1,
  61991     },
  61992 #endif /* chips */
  61993 
  61994 #if defined(BCM_88790_A0)
  61995     { /* SOC_REG_INT_BRDC_FSRD_AUTO_DOC_NAME_2r */
  61996         soc_block_list[27],
  61997         soc_genreg,
  61998         1,
  61999         0,
  62000         0x10d,
  62001         SOC_REG_FLAG_WO,
  62002         0,
  62003         1,
  62004         soc_BRDC_FSRD_AUTO_DOC_NAME_2r_fields,
  62005         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62006         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62007         -1,
  62008         -1,
  62009     },
  62010 #endif /* chips */
  62011 
  62012 #if defined(BCM_88690_A0)
  62013     { /* SOC_REG_INT_BRDC_FSRD_AUTO_DOC_NAME_2_BCM88690_A0r */
  62014         soc_block_list[27],
  62015         soc_genreg,
  62016         1,
  62017         0,
  62018         0x10d,
  62019         SOC_REG_FLAG_WO,
  62020         0,
  62021         1,
  62022         soc_BRDC_FSRD_AUTO_DOC_NAME_2_BCM88690_A0r_fields,
  62023         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62024         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62025         -1,
  62026         -1,
  62027     },
  62028 #endif /* chips */
  62029 
  62030 #if defined(BCM_88690_B0)
  62031     { /* SOC_REG_INT_BRDC_FSRD_AUTO_DOC_NAME_2_BCM88690_B0r */
  62032         soc_block_list[27],
  62033         soc_genreg,
  62034         1,
  62035         0,
  62036         0x10d,
  62037         SOC_REG_FLAG_WO,
  62038         0,
  62039         1,
  62040         soc_BRDC_FSRD_AUTO_DOC_NAME_2_BCM88690_B0r_fields,
  62041         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62042         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62043         -1,
  62044         -1,
  62045     },
  62046 #endif /* chips */
  62047 
  62048 #if defined(BCM_88675_A0)
  62049     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNTr */
  62050         soc_block_list[27],
  62051         soc_genreg,
  62052         1,
  62053         0,
  62054         0x94,
  62055         SOC_REG_FLAG_64_BITS |
  62056                           SOC_REG_FLAG_RO |
  62057                           SOC_REG_FLAG_WO,
  62058         0,
  62059         4,
  62060         soc_BRDC_FSRD_ECC_1B_ERR_CNTr_fields,
  62061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62062         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62063         -1,
  62064         -1,
  62065     },
  62066 #endif /* chips */
  62067 
  62068 #if defined(BCM_88375_A0)
  62069     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88375_A0r */
  62070         soc_block_list[27],
  62071         soc_genreg,
  62072         1,
  62073         0,
  62074         0x94,
  62075         SOC_REG_FLAG_64_BITS |
  62076                           SOC_REG_FLAG_RO |
  62077                           SOC_REG_FLAG_WO,
  62078         0,
  62079         4,
  62080         soc_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88375_A0r_fields,
  62081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62082         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62083         -1,
  62084         -1,
  62085     },
  62086 #endif /* chips */
  62087 
  62088 #if defined(BCM_88375_B0)
  62089     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88375_B0r */
  62090         soc_block_list[27],
  62091         soc_genreg,
  62092         1,
  62093         0,
  62094         0x94,
  62095         SOC_REG_FLAG_64_BITS |
  62096                           SOC_REG_FLAG_RO |
  62097                           SOC_REG_FLAG_WO,
  62098         0,
  62099         4,
  62100         soc_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88375_B0r_fields,
  62101         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62102         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62103         -1,
  62104         -1,
  62105     },
  62106 #endif /* chips */
  62107 
  62108 #if defined(BCM_88675_B0)
  62109     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88675_B0r */
  62110         soc_block_list[27],
  62111         soc_genreg,
  62112         1,
  62113         0,
  62114         0x94,
  62115         SOC_REG_FLAG_64_BITS |
  62116                           SOC_REG_FLAG_RO |
  62117                           SOC_REG_FLAG_WO,
  62118         0,
  62119         4,
  62120         soc_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88675_B0r_fields,
  62121         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62122         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62123         -1,
  62124         -1,
  62125     },
  62126 #endif /* chips */
  62127 
  62128 #if defined(BCM_88680_A0)
  62129     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88680_A0r */
  62130         soc_block_list[27],
  62131         soc_genreg,
  62132         1,
  62133         0,
  62134         0x94,
  62135         SOC_REG_FLAG_64_BITS |
  62136                           SOC_REG_FLAG_RO |
  62137                           SOC_REG_FLAG_WO,
  62138         0,
  62139         4,
  62140         soc_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88680_A0r_fields,
  62141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62142         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62143         -1,
  62144         -1,
  62145     },
  62146 #endif /* chips */
  62147 
  62148 #if defined(BCM_88690_A0)
  62149     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88690_A0r */
  62150         soc_block_list[27],
  62151         soc_genreg,
  62152         1,
  62153         0,
  62154         0x94,
  62155         SOC_REG_FLAG_64_BITS |
  62156                           SOC_REG_FLAG_RO |
  62157                           SOC_REG_FLAG_WO,
  62158         SOC_REG_FLAG_COUNTER_FEILDS |
  62159                           SOC_REG_FLAG_INIT_ON_READ,
  62160         4,
  62161         soc_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88690_A0r_fields,
  62162         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62163         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62164         -1,
  62165         -1,
  62166     },
  62167 #endif /* chips */
  62168 
  62169 #if defined(BCM_88790_A0)
  62170     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88790_A0r */
  62171         soc_block_list[27],
  62172         soc_genreg,
  62173         1,
  62174         0,
  62175         0x94,
  62176         SOC_REG_FLAG_64_BITS |
  62177                           SOC_REG_FLAG_RO |
  62178                           SOC_REG_FLAG_WO,
  62179         SOC_REG_FLAG_COUNTER_FEILDS,
  62180         4,
  62181         soc_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88790_A0r_fields,
  62182         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62183         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62184         -1,
  62185         -1,
  62186     },
  62187 #endif /* chips */
  62188 
  62189 #if defined(BCM_88950_A0)
  62190     { /* SOC_REG_INT_BRDC_FSRD_ECC_1B_ERR_CNT_BCM88950_A0r */
  62191         soc_block_list[27],
  62192         soc_genreg,
  62193         1,
  62194         0,
  62195         0x94,
  62196         SOC_REG_FLAG_64_BITS |
  62197                           SOC_REG_FLAG_RO |
  62198                           SOC_REG_FLAG_WO,
  62199         0,
  62200         4,
  62201         soc_BRDC_CCS_ECC_1B_ERR_CNTr_fields,
  62202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62203         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62204         -1,
  62205         -1,
  62206     },
  62207 #endif /* chips */
  62208 
  62209 #if defined(BCM_88675_A0)
  62210     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNTr */
  62211         soc_block_list[27],
  62212         soc_genreg,
  62213         1,
  62214         0,
  62215         0x96,
  62216         SOC_REG_FLAG_64_BITS |
  62217                           SOC_REG_FLAG_RO |
  62218                           SOC_REG_FLAG_WO,
  62219         0,
  62220         4,
  62221         soc_BRDC_FSRD_ECC_2B_ERR_CNTr_fields,
  62222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62223         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62224         -1,
  62225         -1,
  62226     },
  62227 #endif /* chips */
  62228 
  62229 #if defined(BCM_88375_A0)
  62230     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88375_A0r */
  62231         soc_block_list[27],
  62232         soc_genreg,
  62233         1,
  62234         0,
  62235         0x96,
  62236         SOC_REG_FLAG_64_BITS |
  62237                           SOC_REG_FLAG_RO |
  62238                           SOC_REG_FLAG_WO,
  62239         0,
  62240         4,
  62241         soc_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88375_A0r_fields,
  62242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62243         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62244         -1,
  62245         -1,
  62246     },
  62247 #endif /* chips */
  62248 
  62249 #if defined(BCM_88375_B0)
  62250     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88375_B0r */
  62251         soc_block_list[27],
  62252         soc_genreg,
  62253         1,
  62254         0,
  62255         0x96,
  62256         SOC_REG_FLAG_64_BITS |
  62257                           SOC_REG_FLAG_RO |
  62258                           SOC_REG_FLAG_WO,
  62259         0,
  62260         4,
  62261         soc_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88375_B0r_fields,
  62262         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62263         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62264         -1,
  62265         -1,
  62266     },
  62267 #endif /* chips */
  62268 
  62269 #if defined(BCM_88675_B0)
  62270     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88675_B0r */
  62271         soc_block_list[27],
  62272         soc_genreg,
  62273         1,
  62274         0,
  62275         0x96,
  62276         SOC_REG_FLAG_64_BITS |
  62277                           SOC_REG_FLAG_RO |
  62278                           SOC_REG_FLAG_WO,
  62279         0,
  62280         4,
  62281         soc_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88675_B0r_fields,
  62282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62283         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62284         -1,
  62285         -1,
  62286     },
  62287 #endif /* chips */
  62288 
  62289 #if defined(BCM_88680_A0)
  62290     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88680_A0r */
  62291         soc_block_list[27],
  62292         soc_genreg,
  62293         1,
  62294         0,
  62295         0x96,
  62296         SOC_REG_FLAG_64_BITS |
  62297                           SOC_REG_FLAG_RO |
  62298                           SOC_REG_FLAG_WO,
  62299         0,
  62300         4,
  62301         soc_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88680_A0r_fields,
  62302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62303         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62304         -1,
  62305         -1,
  62306     },
  62307 #endif /* chips */
  62308 
  62309 #if defined(BCM_88690_A0)
  62310     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88690_A0r */
  62311         soc_block_list[27],
  62312         soc_genreg,
  62313         1,
  62314         0,
  62315         0x96,
  62316         SOC_REG_FLAG_64_BITS |
  62317                           SOC_REG_FLAG_RO |
  62318                           SOC_REG_FLAG_WO,
  62319         SOC_REG_FLAG_COUNTER_FEILDS |
  62320                           SOC_REG_FLAG_INIT_ON_READ,
  62321         4,
  62322         soc_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88690_A0r_fields,
  62323         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62324         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62325         -1,
  62326         -1,
  62327     },
  62328 #endif /* chips */
  62329 
  62330 #if defined(BCM_88690_B0)
  62331     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88690_B0r */
  62332         soc_block_list[27],
  62333         soc_genreg,
  62334         1,
  62335         0,
  62336         0x96,
  62337         SOC_REG_FLAG_64_BITS |
  62338                           SOC_REG_FLAG_RO |
  62339                           SOC_REG_FLAG_WO,
  62340         SOC_REG_FLAG_COUNTER_FEILDS |
  62341                           SOC_REG_FLAG_INIT_ON_READ,
  62342         4,
  62343         soc_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
  62344         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62345         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62346         -1,
  62347         -1,
  62348     },
  62349 #endif /* chips */
  62350 
  62351 #if defined(BCM_88790_A0)
  62352     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88790_A0r */
  62353         soc_block_list[27],
  62354         soc_genreg,
  62355         1,
  62356         0,
  62357         0x96,
  62358         SOC_REG_FLAG_64_BITS |
  62359                           SOC_REG_FLAG_RO |
  62360                           SOC_REG_FLAG_WO,
  62361         SOC_REG_FLAG_COUNTER_FEILDS,
  62362         4,
  62363         soc_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88790_A0r_fields,
  62364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62365         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62366         -1,
  62367         -1,
  62368     },
  62369 #endif /* chips */
  62370 
  62371 #if defined(BCM_88950_A0)
  62372     { /* SOC_REG_INT_BRDC_FSRD_ECC_2B_ERR_CNT_BCM88950_A0r */
  62373         soc_block_list[27],
  62374         soc_genreg,
  62375         1,
  62376         0,
  62377         0x96,
  62378         SOC_REG_FLAG_64_BITS |
  62379                           SOC_REG_FLAG_RO |
  62380                           SOC_REG_FLAG_WO,
  62381         0,
  62382         4,
  62383         soc_BRDC_CCS_ECC_2B_ERR_CNTr_fields,
  62384         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62385         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  62386         -1,
  62387         -1,
  62388     },
  62389 #endif /* chips */
  62390 
  62391 #if defined(BCM_88675_A0)
  62392     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATEr */
  62393         soc_block_list[27],
  62394         soc_genreg,
  62395         1,
  62396         0,
  62397         0xa4,
  62398         SOC_REG_FLAG_WO,
  62399         0,
  62400         1,
  62401         soc_BRDC_FSRD_ECC_ERR_1B_INITIATEr_fields,
  62402         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62403         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62404         -1,
  62405         -1,
  62406     },
  62407 #endif /* chips */
  62408 
  62409 #if defined(BCM_88375_A0)
  62410     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88375_A0r */
  62411         soc_block_list[27],
  62412         soc_genreg,
  62413         1,
  62414         0,
  62415         0xa4,
  62416         SOC_REG_FLAG_WO,
  62417         0,
  62418         1,
  62419         soc_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88375_A0r_fields,
  62420         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62421         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62422         -1,
  62423         -1,
  62424     },
  62425 #endif /* chips */
  62426 
  62427 #if defined(BCM_88375_B0)
  62428     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88375_B0r */
  62429         soc_block_list[27],
  62430         soc_genreg,
  62431         1,
  62432         0,
  62433         0xa4,
  62434         SOC_REG_FLAG_WO,
  62435         0,
  62436         1,
  62437         soc_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88375_B0r_fields,
  62438         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62439         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62440         -1,
  62441         -1,
  62442     },
  62443 #endif /* chips */
  62444 
  62445 #if defined(BCM_88675_B0)
  62446     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88675_B0r */
  62447         soc_block_list[27],
  62448         soc_genreg,
  62449         1,
  62450         0,
  62451         0xa4,
  62452         SOC_REG_FLAG_WO,
  62453         0,
  62454         1,
  62455         soc_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88675_B0r_fields,
  62456         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62457         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62458         -1,
  62459         -1,
  62460     },
  62461 #endif /* chips */
  62462 
  62463 #if defined(BCM_88680_A0)
  62464     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88680_A0r */
  62465         soc_block_list[27],
  62466         soc_genreg,
  62467         1,
  62468         0,
  62469         0xa4,
  62470         SOC_REG_FLAG_WO,
  62471         0,
  62472         1,
  62473         soc_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88680_A0r_fields,
  62474         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62475         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62476         -1,
  62477         -1,
  62478     },
  62479 #endif /* chips */
  62480 
  62481 #if defined(BCM_88690_A0)
  62482     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88690_A0r */
  62483         soc_block_list[27],
  62484         soc_genreg,
  62485         1,
  62486         0,
  62487         0xa4,
  62488         SOC_REG_FLAG_WO,
  62489         0,
  62490         1,
  62491         soc_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88690_A0r_fields,
  62492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62493         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62494         -1,
  62495         -1,
  62496     },
  62497 #endif /* chips */
  62498 
  62499 #if defined(BCM_88790_A0)
  62500     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88790_A0r */
  62501         soc_block_list[27],
  62502         soc_genreg,
  62503         1,
  62504         0,
  62505         0xa4,
  62506         SOC_REG_FLAG_WO,
  62507         0,
  62508         1,
  62509         soc_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88790_A0r_fields,
  62510         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62511         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62512         -1,
  62513         -1,
  62514     },
  62515 #endif /* chips */
  62516 
  62517 #if defined(BCM_88950_A0)
  62518     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88950_A0r */
  62519         soc_block_list[27],
  62520         soc_genreg,
  62521         1,
  62522         0,
  62523         0xa4,
  62524         SOC_REG_FLAG_WO,
  62525         0,
  62526         1,
  62527         soc_BRDC_FSRD_ECC_ERR_1B_INITIATE_BCM88950_A0r_fields,
  62528         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62529         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62530         -1,
  62531         -1,
  62532     },
  62533 #endif /* chips */
  62534 
  62535 #if defined(BCM_88675_A0)
  62536     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASKr */
  62537         soc_block_list[27],
  62538         soc_genreg,
  62539         1,
  62540         0,
  62541         0x9a,
  62542         SOC_REG_FLAG_WO,
  62543         0,
  62544         1,
  62545         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  62546         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62547         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62548         -1,
  62549         -1,
  62550     },
  62551 #endif /* chips */
  62552 
  62553 #if defined(BCM_88375_A0)
  62554     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r */
  62555         soc_block_list[27],
  62556         soc_genreg,
  62557         1,
  62558         0,
  62559         0x9a,
  62560         SOC_REG_FLAG_WO,
  62561         0,
  62562         1,
  62563         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  62564         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62565         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62566         -1,
  62567         -1,
  62568     },
  62569 #endif /* chips */
  62570 
  62571 #if defined(BCM_88375_B0)
  62572     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r */
  62573         soc_block_list[27],
  62574         soc_genreg,
  62575         1,
  62576         0,
  62577         0x9a,
  62578         SOC_REG_FLAG_WO,
  62579         0,
  62580         1,
  62581         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  62582         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62583         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62584         -1,
  62585         -1,
  62586     },
  62587 #endif /* chips */
  62588 
  62589 #if defined(BCM_88675_B0)
  62590     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r */
  62591         soc_block_list[27],
  62592         soc_genreg,
  62593         1,
  62594         0,
  62595         0x9a,
  62596         SOC_REG_FLAG_WO,
  62597         0,
  62598         1,
  62599         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  62600         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62601         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62602         -1,
  62603         -1,
  62604     },
  62605 #endif /* chips */
  62606 
  62607 #if defined(BCM_88680_A0)
  62608     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r */
  62609         soc_block_list[27],
  62610         soc_genreg,
  62611         1,
  62612         0,
  62613         0x9a,
  62614         SOC_REG_FLAG_WO,
  62615         0,
  62616         1,
  62617         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  62618         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62619         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62620         -1,
  62621         -1,
  62622     },
  62623 #endif /* chips */
  62624 
  62625 #if defined(BCM_88690_A0)
  62626     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r */
  62627         soc_block_list[27],
  62628         soc_genreg,
  62629         1,
  62630         0,
  62631         0x9a,
  62632         SOC_REG_FLAG_WO,
  62633         0,
  62634         1,
  62635         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  62636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62637         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62638         -1,
  62639         -1,
  62640     },
  62641 #endif /* chips */
  62642 
  62643 #if defined(BCM_88790_A0)
  62644     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88790_A0r */
  62645         soc_block_list[27],
  62646         soc_genreg,
  62647         1,
  62648         0,
  62649         0x9a,
  62650         SOC_REG_FLAG_WO,
  62651         0,
  62652         1,
  62653         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88790_A0r_fields,
  62654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62655         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62656         -1,
  62657         -1,
  62658     },
  62659 #endif /* chips */
  62660 
  62661 #if defined(BCM_88950_A0)
  62662     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88950_A0r */
  62663         soc_block_list[27],
  62664         soc_genreg,
  62665         1,
  62666         0,
  62667         0x9a,
  62668         SOC_REG_FLAG_WO,
  62669         0,
  62670         1,
  62671         soc_BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88950_A0r_fields,
  62672         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62673         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62674         -1,
  62675         -1,
  62676     },
  62677 #endif /* chips */
  62678 
  62679 #if defined(BCM_88675_A0)
  62680     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATEr */
  62681         soc_block_list[27],
  62682         soc_genreg,
  62683         1,
  62684         0,
  62685         0xa6,
  62686         SOC_REG_FLAG_WO,
  62687         0,
  62688         1,
  62689         soc_BRDC_FSRD_ECC_ERR_2B_INITIATEr_fields,
  62690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62691         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62692         -1,
  62693         -1,
  62694     },
  62695 #endif /* chips */
  62696 
  62697 #if defined(BCM_88375_A0)
  62698     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88375_A0r */
  62699         soc_block_list[27],
  62700         soc_genreg,
  62701         1,
  62702         0,
  62703         0xa6,
  62704         SOC_REG_FLAG_WO,
  62705         0,
  62706         1,
  62707         soc_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88375_A0r_fields,
  62708         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62709         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62710         -1,
  62711         -1,
  62712     },
  62713 #endif /* chips */
  62714 
  62715 #if defined(BCM_88375_B0)
  62716     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88375_B0r */
  62717         soc_block_list[27],
  62718         soc_genreg,
  62719         1,
  62720         0,
  62721         0xa6,
  62722         SOC_REG_FLAG_WO,
  62723         0,
  62724         1,
  62725         soc_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88375_B0r_fields,
  62726         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62727         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62728         -1,
  62729         -1,
  62730     },
  62731 #endif /* chips */
  62732 
  62733 #if defined(BCM_88675_B0)
  62734     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88675_B0r */
  62735         soc_block_list[27],
  62736         soc_genreg,
  62737         1,
  62738         0,
  62739         0xa6,
  62740         SOC_REG_FLAG_WO,
  62741         0,
  62742         1,
  62743         soc_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88675_B0r_fields,
  62744         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62745         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62746         -1,
  62747         -1,
  62748     },
  62749 #endif /* chips */
  62750 
  62751 #if defined(BCM_88680_A0)
  62752     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88680_A0r */
  62753         soc_block_list[27],
  62754         soc_genreg,
  62755         1,
  62756         0,
  62757         0xa6,
  62758         SOC_REG_FLAG_WO,
  62759         0,
  62760         1,
  62761         soc_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88680_A0r_fields,
  62762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62763         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62764         -1,
  62765         -1,
  62766     },
  62767 #endif /* chips */
  62768 
  62769 #if defined(BCM_88690_A0)
  62770     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88690_A0r */
  62771         soc_block_list[27],
  62772         soc_genreg,
  62773         1,
  62774         0,
  62775         0xa6,
  62776         SOC_REG_FLAG_WO,
  62777         0,
  62778         1,
  62779         soc_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88690_A0r_fields,
  62780         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62781         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62782         -1,
  62783         -1,
  62784     },
  62785 #endif /* chips */
  62786 
  62787 #if defined(BCM_88790_A0)
  62788     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88790_A0r */
  62789         soc_block_list[27],
  62790         soc_genreg,
  62791         1,
  62792         0,
  62793         0xa6,
  62794         SOC_REG_FLAG_WO,
  62795         0,
  62796         1,
  62797         soc_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88790_A0r_fields,
  62798         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62799         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62800         -1,
  62801         -1,
  62802     },
  62803 #endif /* chips */
  62804 
  62805 #if defined(BCM_88950_A0)
  62806     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88950_A0r */
  62807         soc_block_list[27],
  62808         soc_genreg,
  62809         1,
  62810         0,
  62811         0xa6,
  62812         SOC_REG_FLAG_WO,
  62813         0,
  62814         1,
  62815         soc_BRDC_FSRD_ECC_ERR_2B_INITIATE_BCM88950_A0r_fields,
  62816         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62817         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62818         -1,
  62819         -1,
  62820     },
  62821 #endif /* chips */
  62822 
  62823 #if defined(BCM_88675_A0)
  62824     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASKr */
  62825         soc_block_list[27],
  62826         soc_genreg,
  62827         1,
  62828         0,
  62829         0x9c,
  62830         SOC_REG_FLAG_WO,
  62831         0,
  62832         1,
  62833         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  62834         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62835         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62836         -1,
  62837         -1,
  62838     },
  62839 #endif /* chips */
  62840 
  62841 #if defined(BCM_88375_A0)
  62842     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r */
  62843         soc_block_list[27],
  62844         soc_genreg,
  62845         1,
  62846         0,
  62847         0x9c,
  62848         SOC_REG_FLAG_WO,
  62849         0,
  62850         1,
  62851         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_A0r_fields,
  62852         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62853         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62854         -1,
  62855         -1,
  62856     },
  62857 #endif /* chips */
  62858 
  62859 #if defined(BCM_88375_B0)
  62860     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r */
  62861         soc_block_list[27],
  62862         soc_genreg,
  62863         1,
  62864         0,
  62865         0x9c,
  62866         SOC_REG_FLAG_WO,
  62867         0,
  62868         1,
  62869         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88375_B0r_fields,
  62870         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62871         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62872         -1,
  62873         -1,
  62874     },
  62875 #endif /* chips */
  62876 
  62877 #if defined(BCM_88675_B0)
  62878     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r */
  62879         soc_block_list[27],
  62880         soc_genreg,
  62881         1,
  62882         0,
  62883         0x9c,
  62884         SOC_REG_FLAG_WO,
  62885         0,
  62886         1,
  62887         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88675_B0r_fields,
  62888         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62889         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62890         -1,
  62891         -1,
  62892     },
  62893 #endif /* chips */
  62894 
  62895 #if defined(BCM_88680_A0)
  62896     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r */
  62897         soc_block_list[27],
  62898         soc_genreg,
  62899         1,
  62900         0,
  62901         0x9c,
  62902         SOC_REG_FLAG_WO,
  62903         0,
  62904         1,
  62905         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88680_A0r_fields,
  62906         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62907         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62908         -1,
  62909         -1,
  62910     },
  62911 #endif /* chips */
  62912 
  62913 #if defined(BCM_88690_A0)
  62914     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r */
  62915         soc_block_list[27],
  62916         soc_genreg,
  62917         1,
  62918         0,
  62919         0x9c,
  62920         SOC_REG_FLAG_WO,
  62921         0,
  62922         1,
  62923         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_A0r_fields,
  62924         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62925         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62926         -1,
  62927         -1,
  62928     },
  62929 #endif /* chips */
  62930 
  62931 #if defined(BCM_88790_A0)
  62932     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88790_A0r */
  62933         soc_block_list[27],
  62934         soc_genreg,
  62935         1,
  62936         0,
  62937         0x9c,
  62938         SOC_REG_FLAG_WO,
  62939         0,
  62940         1,
  62941         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88790_A0r_fields,
  62942         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62943         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62944         -1,
  62945         -1,
  62946     },
  62947 #endif /* chips */
  62948 
  62949 #if defined(BCM_88950_A0)
  62950     { /* SOC_REG_INT_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88950_A0r */
  62951         soc_block_list[27],
  62952         soc_genreg,
  62953         1,
  62954         0,
  62955         0x9c,
  62956         SOC_REG_FLAG_WO,
  62957         0,
  62958         1,
  62959         soc_BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88950_A0r_fields,
  62960         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  62961         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  62962         -1,
  62963         -1,
  62964     },
  62965 #endif /* chips */
  62966 
  62967 #if defined(BCM_88675_A0)
  62968     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTERr */
  62969         soc_block_list[27],
  62970         soc_genreg,
  62971         1,
  62972         0,
  62973         0x7,
  62974         SOC_REG_FLAG_WO |
  62975                           SOC_REG_FLAG_INTERRUPT,
  62976         0,
  62977         3,
  62978         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTERr_fields,
  62979         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62980         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  62981         -1,
  62982         -1,
  62983     },
  62984 #endif /* chips */
  62985 
  62986 #if defined(BCM_88375_A0)
  62987     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88375_A0r */
  62988         soc_block_list[27],
  62989         soc_genreg,
  62990         1,
  62991         0,
  62992         0x7,
  62993         SOC_REG_FLAG_WO |
  62994                           SOC_REG_FLAG_INTERRUPT,
  62995         0,
  62996         3,
  62997         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  62998         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  62999         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63000         -1,
  63001         -1,
  63002     },
  63003 #endif /* chips */
  63004 
  63005 #if defined(BCM_88375_B0)
  63006     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88375_B0r */
  63007         soc_block_list[27],
  63008         soc_genreg,
  63009         1,
  63010         0,
  63011         0x7,
  63012         SOC_REG_FLAG_WO |
  63013                           SOC_REG_FLAG_INTERRUPT,
  63014         0,
  63015         3,
  63016         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  63017         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63018         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63019         -1,
  63020         -1,
  63021     },
  63022 #endif /* chips */
  63023 
  63024 #if defined(BCM_88675_B0)
  63025     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88675_B0r */
  63026         soc_block_list[27],
  63027         soc_genreg,
  63028         1,
  63029         0,
  63030         0x7,
  63031         SOC_REG_FLAG_WO |
  63032                           SOC_REG_FLAG_INTERRUPT,
  63033         0,
  63034         3,
  63035         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  63036         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63037         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63038         -1,
  63039         -1,
  63040     },
  63041 #endif /* chips */
  63042 
  63043 #if defined(BCM_88680_A0)
  63044     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88680_A0r */
  63045         soc_block_list[27],
  63046         soc_genreg,
  63047         1,
  63048         0,
  63049         0x7,
  63050         SOC_REG_FLAG_WO |
  63051                           SOC_REG_FLAG_INTERRUPT,
  63052         0,
  63053         3,
  63054         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  63055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63056         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63057         -1,
  63058         -1,
  63059     },
  63060 #endif /* chips */
  63061 
  63062 #if defined(BCM_88690_A0)
  63063     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88690_A0r */
  63064         soc_block_list[27],
  63065         soc_genreg,
  63066         1,
  63067         0,
  63068         0x7,
  63069         SOC_REG_FLAG_WO |
  63070                           SOC_REG_FLAG_INTERRUPT |
  63071                           SOC_REG_FLAG_SIGNAL,
  63072         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  63073         3,
  63074         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  63075         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63076         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63077         -1,
  63078         -1,
  63079     },
  63080 #endif /* chips */
  63081 
  63082 #if defined(BCM_88690_B0)
  63083     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
  63084         soc_block_list[27],
  63085         soc_genreg,
  63086         1,
  63087         0,
  63088         0x7,
  63089         SOC_REG_FLAG_WO |
  63090                           SOC_REG_FLAG_INTERRUPT |
  63091                           SOC_REG_FLAG_SIGNAL,
  63092         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  63093         3,
  63094         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  63095         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63096         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63097         -1,
  63098         -1,
  63099     },
  63100 #endif /* chips */
  63101 
  63102 #if defined(BCM_88790_A0)
  63103     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88790_A0r */
  63104         soc_block_list[27],
  63105         soc_genreg,
  63106         1,
  63107         0,
  63108         0x7,
  63109         SOC_REG_FLAG_WO |
  63110                           SOC_REG_FLAG_INTERRUPT |
  63111                           SOC_REG_FLAG_SIGNAL,
  63112         0,
  63113         3,
  63114         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  63115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63116         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63117         -1,
  63118         -1,
  63119     },
  63120 #endif /* chips */
  63121 
  63122 #if defined(BCM_88950_A0)
  63123     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_BCM88950_A0r */
  63124         soc_block_list[27],
  63125         soc_genreg,
  63126         1,
  63127         0,
  63128         0x7,
  63129         SOC_REG_FLAG_WO |
  63130                           SOC_REG_FLAG_INTERRUPT,
  63131         0,
  63132         3,
  63133         soc_BRDC_DCH_ECC_INTERRUPT_REGISTERr_fields,
  63134         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63135         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63136         -1,
  63137         -1,
  63138     },
  63139 #endif /* chips */
  63140 
  63141 #if defined(BCM_88675_A0)
  63142     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASKr */
  63143         soc_block_list[27],
  63144         soc_genreg,
  63145         1,
  63146         0,
  63147         0x17,
  63148         SOC_REG_FLAG_WO,
  63149         0,
  63150         3,
  63151         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASKr_fields,
  63152         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63153         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63154         -1,
  63155         -1,
  63156     },
  63157 #endif /* chips */
  63158 
  63159 #if defined(BCM_88375_A0)
  63160     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r */
  63161         soc_block_list[27],
  63162         soc_genreg,
  63163         1,
  63164         0,
  63165         0x17,
  63166         SOC_REG_FLAG_WO,
  63167         0,
  63168         3,
  63169         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88375_A0r_fields,
  63170         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63171         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63172         -1,
  63173         -1,
  63174     },
  63175 #endif /* chips */
  63176 
  63177 #if defined(BCM_88375_B0)
  63178     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r */
  63179         soc_block_list[27],
  63180         soc_genreg,
  63181         1,
  63182         0,
  63183         0x17,
  63184         SOC_REG_FLAG_WO,
  63185         0,
  63186         3,
  63187         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88375_B0r_fields,
  63188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63189         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63190         -1,
  63191         -1,
  63192     },
  63193 #endif /* chips */
  63194 
  63195 #if defined(BCM_88675_B0)
  63196     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r */
  63197         soc_block_list[27],
  63198         soc_genreg,
  63199         1,
  63200         0,
  63201         0x17,
  63202         SOC_REG_FLAG_WO,
  63203         0,
  63204         3,
  63205         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88675_B0r_fields,
  63206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63207         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63208         -1,
  63209         -1,
  63210     },
  63211 #endif /* chips */
  63212 
  63213 #if defined(BCM_88680_A0)
  63214     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r */
  63215         soc_block_list[27],
  63216         soc_genreg,
  63217         1,
  63218         0,
  63219         0x17,
  63220         SOC_REG_FLAG_WO,
  63221         0,
  63222         3,
  63223         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88680_A0r_fields,
  63224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63225         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63226         -1,
  63227         -1,
  63228     },
  63229 #endif /* chips */
  63230 
  63231 #if defined(BCM_88690_A0)
  63232     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r */
  63233         soc_block_list[27],
  63234         soc_genreg,
  63235         1,
  63236         0,
  63237         0x17,
  63238         SOC_REG_FLAG_WO,
  63239         0,
  63240         3,
  63241         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88690_A0r_fields,
  63242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63243         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63244         -1,
  63245         -1,
  63246     },
  63247 #endif /* chips */
  63248 
  63249 #if defined(BCM_88690_B0)
  63250     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
  63251         soc_block_list[27],
  63252         soc_genreg,
  63253         1,
  63254         0,
  63255         0x17,
  63256         SOC_REG_FLAG_WO,
  63257         0,
  63258         3,
  63259         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
  63260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63261         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63262         -1,
  63263         -1,
  63264     },
  63265 #endif /* chips */
  63266 
  63267 #if defined(BCM_88790_A0)
  63268     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88790_A0r */
  63269         soc_block_list[27],
  63270         soc_genreg,
  63271         1,
  63272         0,
  63273         0x17,
  63274         SOC_REG_FLAG_WO,
  63275         0,
  63276         3,
  63277         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88790_A0r_fields,
  63278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63279         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63280         -1,
  63281         -1,
  63282     },
  63283 #endif /* chips */
  63284 
  63285 #if defined(BCM_88950_A0)
  63286     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK_BCM88950_A0r */
  63287         soc_block_list[27],
  63288         soc_genreg,
  63289         1,
  63290         0,
  63291         0x17,
  63292         SOC_REG_FLAG_WO,
  63293         0,
  63294         3,
  63295         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_MASKr_fields,
  63296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63297         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63298         -1,
  63299         -1,
  63300     },
  63301 #endif /* chips */
  63302 
  63303 #if defined(BCM_88675_A0)
  63304     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TESTr */
  63305         soc_block_list[27],
  63306         soc_genreg,
  63307         1,
  63308         0,
  63309         0x1f,
  63310         SOC_REG_FLAG_WO,
  63311         0,
  63312         1,
  63313         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TESTr_fields,
  63314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63315         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  63316         -1,
  63317         -1,
  63318     },
  63319 #endif /* chips */
  63320 
  63321 #if defined(BCM_88375_A0)
  63322     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  63323         soc_block_list[27],
  63324         soc_genreg,
  63325         1,
  63326         0,
  63327         0x1f,
  63328         SOC_REG_FLAG_WO,
  63329         0,
  63330         1,
  63331         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  63332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  63334         -1,
  63335         -1,
  63336     },
  63337 #endif /* chips */
  63338 
  63339 #if defined(BCM_88375_B0)
  63340     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  63341         soc_block_list[27],
  63342         soc_genreg,
  63343         1,
  63344         0,
  63345         0x1f,
  63346         SOC_REG_FLAG_WO,
  63347         0,
  63348         1,
  63349         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  63350         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  63352         -1,
  63353         -1,
  63354     },
  63355 #endif /* chips */
  63356 
  63357 #if defined(BCM_88675_B0)
  63358     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  63359         soc_block_list[27],
  63360         soc_genreg,
  63361         1,
  63362         0,
  63363         0x1f,
  63364         SOC_REG_FLAG_WO,
  63365         0,
  63366         1,
  63367         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  63368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  63370         -1,
  63371         -1,
  63372     },
  63373 #endif /* chips */
  63374 
  63375 #if defined(BCM_88680_A0)
  63376     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  63377         soc_block_list[27],
  63378         soc_genreg,
  63379         1,
  63380         0,
  63381         0x1f,
  63382         SOC_REG_FLAG_WO,
  63383         0,
  63384         1,
  63385         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  63386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  63388         -1,
  63389         -1,
  63390     },
  63391 #endif /* chips */
  63392 
  63393 #if defined(BCM_88690_A0)
  63394     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  63395         soc_block_list[27],
  63396         soc_genreg,
  63397         1,
  63398         0,
  63399         0x1f,
  63400         SOC_REG_FLAG_WO,
  63401         0,
  63402         1,
  63403         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  63404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63405         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63406         -1,
  63407         -1,
  63408     },
  63409 #endif /* chips */
  63410 
  63411 #if defined(BCM_88690_B0)
  63412     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  63413         soc_block_list[27],
  63414         soc_genreg,
  63415         1,
  63416         0,
  63417         0x1f,
  63418         SOC_REG_FLAG_WO,
  63419         0,
  63420         1,
  63421         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  63422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63423         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63424         -1,
  63425         -1,
  63426     },
  63427 #endif /* chips */
  63428 
  63429 #if defined(BCM_88790_A0)
  63430     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  63431         soc_block_list[27],
  63432         soc_genreg,
  63433         1,
  63434         0,
  63435         0x1f,
  63436         SOC_REG_FLAG_WO,
  63437         0,
  63438         1,
  63439         soc_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88790_A0r_fields,
  63440         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63441         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  63442         -1,
  63443         -1,
  63444     },
  63445 #endif /* chips */
  63446 
  63447 #if defined(BCM_88950_A0)
  63448     { /* SOC_REG_INT_BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST_BCM88950_A0r */
  63449         soc_block_list[27],
  63450         soc_genreg,
  63451         1,
  63452         0,
  63453         0x1f,
  63454         SOC_REG_FLAG_WO,
  63455         0,
  63456         1,
  63457         soc_BRDC_CCS_ECC_INTERRUPT_REGISTER_TESTr_fields,
  63458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63459         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  63460         -1,
  63461         -1,
  63462     },
  63463 #endif /* chips */
  63464 
  63465 #if defined(BCM_88675_A0)
  63466     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESSr */
  63467         soc_block_list[27],
  63468         soc_genreg,
  63469         1,
  63470         0,
  63471         0x84,
  63472         SOC_REG_FLAG_WO,
  63473         0,
  63474         1,
  63475         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  63476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63477         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63478         -1,
  63479         -1,
  63480     },
  63481 #endif /* chips */
  63482 
  63483 #if defined(BCM_88375_A0)
  63484     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r */
  63485         soc_block_list[27],
  63486         soc_genreg,
  63487         1,
  63488         0,
  63489         0x84,
  63490         SOC_REG_FLAG_WO,
  63491         0,
  63492         1,
  63493         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_A0r_fields,
  63494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63495         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63496         -1,
  63497         -1,
  63498     },
  63499 #endif /* chips */
  63500 
  63501 #if defined(BCM_88375_B0)
  63502     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r */
  63503         soc_block_list[27],
  63504         soc_genreg,
  63505         1,
  63506         0,
  63507         0x84,
  63508         SOC_REG_FLAG_WO,
  63509         0,
  63510         1,
  63511         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88375_B0r_fields,
  63512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63513         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63514         -1,
  63515         -1,
  63516     },
  63517 #endif /* chips */
  63518 
  63519 #if defined(BCM_88675_B0)
  63520     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r */
  63521         soc_block_list[27],
  63522         soc_genreg,
  63523         1,
  63524         0,
  63525         0x84,
  63526         SOC_REG_FLAG_WO,
  63527         0,
  63528         1,
  63529         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88675_B0r_fields,
  63530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63531         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63532         -1,
  63533         -1,
  63534     },
  63535 #endif /* chips */
  63536 
  63537 #if defined(BCM_88680_A0)
  63538     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r */
  63539         soc_block_list[27],
  63540         soc_genreg,
  63541         1,
  63542         0,
  63543         0x84,
  63544         SOC_REG_FLAG_WO,
  63545         0,
  63546         1,
  63547         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88680_A0r_fields,
  63548         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63549         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63550         -1,
  63551         -1,
  63552     },
  63553 #endif /* chips */
  63554 
  63555 #if defined(BCM_88690_A0)
  63556     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r */
  63557         soc_block_list[27],
  63558         soc_genreg,
  63559         1,
  63560         0,
  63561         0x84,
  63562         SOC_REG_FLAG_WO,
  63563         0,
  63564         1,
  63565         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_A0r_fields,
  63566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63567         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63568         -1,
  63569         -1,
  63570     },
  63571 #endif /* chips */
  63572 
  63573 #if defined(BCM_88690_B0)
  63574     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
  63575         soc_block_list[27],
  63576         soc_genreg,
  63577         1,
  63578         0,
  63579         0x84,
  63580         SOC_REG_FLAG_WO,
  63581         0,
  63582         1,
  63583         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
  63584         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63585         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63586         -1,
  63587         -1,
  63588     },
  63589 #endif /* chips */
  63590 
  63591 #if defined(BCM_88790_A0)
  63592     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88790_A0r */
  63593         soc_block_list[27],
  63594         soc_genreg,
  63595         1,
  63596         0,
  63597         0x84,
  63598         SOC_REG_FLAG_WO,
  63599         0,
  63600         1,
  63601         soc_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88790_A0r_fields,
  63602         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63603         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63604         -1,
  63605         -1,
  63606     },
  63607 #endif /* chips */
  63608 
  63609 #if defined(BCM_88950_A0)
  63610     { /* SOC_REG_INT_BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88950_A0r */
  63611         soc_block_list[27],
  63612         soc_genreg,
  63613         1,
  63614         0,
  63615         0x84,
  63616         SOC_REG_FLAG_WO,
  63617         0,
  63618         1,
  63619         soc_BRDC_DCL_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  63620         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63621         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63622         -1,
  63623         -1,
  63624     },
  63625 #endif /* chips */
  63626 
  63627 #if defined(BCM_88675_A0)
  63628     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATAr */
  63629         soc_block_list[27],
  63630         soc_genreg,
  63631         1,
  63632         0,
  63633         0xa3,
  63634         SOC_REG_FLAG_WO,
  63635         0,
  63636         1,
  63637         soc_BRDC_FSRD_ERROR_INITIATION_DATAr_fields,
  63638         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63639         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63640         -1,
  63641         -1,
  63642     },
  63643 #endif /* chips */
  63644 
  63645 #if defined(BCM_88375_A0)
  63646     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88375_A0r */
  63647         soc_block_list[27],
  63648         soc_genreg,
  63649         1,
  63650         0,
  63651         0xa3,
  63652         SOC_REG_FLAG_WO,
  63653         0,
  63654         1,
  63655         soc_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88375_A0r_fields,
  63656         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63657         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63658         -1,
  63659         -1,
  63660     },
  63661 #endif /* chips */
  63662 
  63663 #if defined(BCM_88375_B0)
  63664     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88375_B0r */
  63665         soc_block_list[27],
  63666         soc_genreg,
  63667         1,
  63668         0,
  63669         0xa3,
  63670         SOC_REG_FLAG_WO,
  63671         0,
  63672         1,
  63673         soc_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88375_B0r_fields,
  63674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63675         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63676         -1,
  63677         -1,
  63678     },
  63679 #endif /* chips */
  63680 
  63681 #if defined(BCM_88675_B0)
  63682     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88675_B0r */
  63683         soc_block_list[27],
  63684         soc_genreg,
  63685         1,
  63686         0,
  63687         0xa3,
  63688         SOC_REG_FLAG_WO,
  63689         0,
  63690         1,
  63691         soc_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88675_B0r_fields,
  63692         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63693         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63694         -1,
  63695         -1,
  63696     },
  63697 #endif /* chips */
  63698 
  63699 #if defined(BCM_88680_A0)
  63700     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88680_A0r */
  63701         soc_block_list[27],
  63702         soc_genreg,
  63703         1,
  63704         0,
  63705         0xa3,
  63706         SOC_REG_FLAG_WO,
  63707         0,
  63708         1,
  63709         soc_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88680_A0r_fields,
  63710         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63711         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63712         -1,
  63713         -1,
  63714     },
  63715 #endif /* chips */
  63716 
  63717 #if defined(BCM_88690_A0)
  63718     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88690_A0r */
  63719         soc_block_list[27],
  63720         soc_genreg,
  63721         1,
  63722         0,
  63723         0xa3,
  63724         SOC_REG_FLAG_WO,
  63725         0,
  63726         1,
  63727         soc_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88690_A0r_fields,
  63728         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63729         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63730         -1,
  63731         -1,
  63732     },
  63733 #endif /* chips */
  63734 
  63735 #if defined(BCM_88790_A0)
  63736     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88790_A0r */
  63737         soc_block_list[27],
  63738         soc_genreg,
  63739         1,
  63740         0,
  63741         0xa3,
  63742         SOC_REG_FLAG_WO,
  63743         0,
  63744         1,
  63745         soc_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88790_A0r_fields,
  63746         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63747         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63748         -1,
  63749         -1,
  63750     },
  63751 #endif /* chips */
  63752 
  63753 #if defined(BCM_88950_A0)
  63754     { /* SOC_REG_INT_BRDC_FSRD_ERROR_INITIATION_DATA_BCM88950_A0r */
  63755         soc_block_list[27],
  63756         soc_genreg,
  63757         1,
  63758         0,
  63759         0xa3,
  63760         SOC_REG_FLAG_WO,
  63761         0,
  63762         1,
  63763         soc_BRDC_CCS_ERROR_INITIATION_DATAr_fields,
  63764         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63765         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  63766         -1,
  63767         -1,
  63768     },
  63769 #endif /* chips */
  63770 
  63771 #if defined(BCM_88790_A0)
  63772     { /* SOC_REG_INT_BRDC_FSRD_FSRD_REGISTER_0r */
  63773         soc_block_list[27],
  63774         soc_genreg,
  63775         8,
  63776         0,
  63777         0x115,
  63778         SOC_REG_FLAG_ARRAY |
  63779                           SOC_REG_FLAG_WO |
  63780                           SOC_REG_FLAG_REG_ARRAY,
  63781         0,
  63782         2,
  63783         soc_BRDC_FSRD_FSRD_REGISTER_0r_fields,
  63784         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63785         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  63786         -1,
  63787         -1,
  63788     },
  63789 #endif /* chips */
  63790 
  63791 #if defined(BCM_88690_A0)
  63792     { /* SOC_REG_INT_BRDC_FSRD_FSRD_REGISTER_0_BCM88690_A0r */
  63793         soc_block_list[27],
  63794         soc_genreg,
  63795         8,
  63796         0,
  63797         0x115,
  63798         SOC_REG_FLAG_ARRAY |
  63799                           SOC_REG_FLAG_WO |
  63800                           SOC_REG_FLAG_REG_ARRAY,
  63801         0,
  63802         2,
  63803         soc_BRDC_FSRD_FSRD_REGISTER_0_BCM88690_A0r_fields,
  63804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63805         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  63806         -1,
  63807         -1,
  63808     },
  63809 #endif /* chips */
  63810 
  63811 #if defined(BCM_88690_B0)
  63812     { /* SOC_REG_INT_BRDC_FSRD_FSRD_REGISTER_0_BCM88690_B0r */
  63813         soc_block_list[27],
  63814         soc_genreg,
  63815         8,
  63816         0,
  63817         0x115,
  63818         SOC_REG_FLAG_ARRAY |
  63819                           SOC_REG_FLAG_WO |
  63820                           SOC_REG_FLAG_REG_ARRAY,
  63821         0,
  63822         2,
  63823         soc_BRDC_FSRD_FSRD_REGISTER_0_BCM88690_B0r_fields,
  63824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63825         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  63826         -1,
  63827         -1,
  63828     },
  63829 #endif /* chips */
  63830 
  63831 #if defined(BCM_88675_A0)
  63832     { /* SOC_REG_INT_BRDC_FSRD_GENERAL_CONFIGURTIONr */
  63833         soc_block_list[27],
  63834         soc_genreg,
  63835         1,
  63836         0,
  63837         0x130,
  63838         SOC_REG_FLAG_WO,
  63839         0,
  63840         1,
  63841         soc_BRDC_FSRD_GENERAL_CONFIGURTIONr_fields,
  63842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63843         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  63844         -1,
  63845         -1,
  63846     },
  63847 #endif /* chips */
  63848 
  63849 #if defined(BCM_88375_A0)
  63850     { /* SOC_REG_INT_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88375_A0r */
  63851         soc_block_list[27],
  63852         soc_genreg,
  63853         1,
  63854         0,
  63855         0x130,
  63856         SOC_REG_FLAG_WO,
  63857         0,
  63858         1,
  63859         soc_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88375_A0r_fields,
  63860         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63861         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  63862         -1,
  63863         -1,
  63864     },
  63865 #endif /* chips */
  63866 
  63867 #if defined(BCM_88375_B0)
  63868     { /* SOC_REG_INT_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88375_B0r */
  63869         soc_block_list[27],
  63870         soc_genreg,
  63871         1,
  63872         0,
  63873         0x130,
  63874         SOC_REG_FLAG_WO,
  63875         0,
  63876         1,
  63877         soc_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88375_B0r_fields,
  63878         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63879         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  63880         -1,
  63881         -1,
  63882     },
  63883 #endif /* chips */
  63884 
  63885 #if defined(BCM_88675_B0)
  63886     { /* SOC_REG_INT_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88675_B0r */
  63887         soc_block_list[27],
  63888         soc_genreg,
  63889         1,
  63890         0,
  63891         0x130,
  63892         SOC_REG_FLAG_WO,
  63893         0,
  63894         1,
  63895         soc_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88675_B0r_fields,
  63896         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63897         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  63898         -1,
  63899         -1,
  63900     },
  63901 #endif /* chips */
  63902 
  63903 #if defined(BCM_88680_A0)
  63904     { /* SOC_REG_INT_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88680_A0r */
  63905         soc_block_list[27],
  63906         soc_genreg,
  63907         1,
  63908         0,
  63909         0x130,
  63910         SOC_REG_FLAG_WO,
  63911         0,
  63912         1,
  63913         soc_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88680_A0r_fields,
  63914         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63915         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  63916         -1,
  63917         -1,
  63918     },
  63919 #endif /* chips */
  63920 
  63921 #if defined(BCM_88950_A0)
  63922     { /* SOC_REG_INT_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88950_A0r */
  63923         soc_block_list[27],
  63924         soc_genreg,
  63925         1,
  63926         0,
  63927         0x130,
  63928         SOC_REG_FLAG_WO,
  63929         0,
  63930         1,
  63931         soc_BRDC_FSRD_GENERAL_CONFIGURTION_BCM88950_A0r_fields,
  63932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63933         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  63934         -1,
  63935         -1,
  63936     },
  63937 #endif /* chips */
  63938 
  63939 #if defined(BCM_88675_A0)
  63940     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONSr */
  63941         soc_block_list[27],
  63942         soc_genreg,
  63943         1,
  63944         0,
  63945         0xc0,
  63946         SOC_REG_FLAG_WO,
  63947         0,
  63948         4,
  63949         soc_BRDC_FSRD_GLOBAL_MEM_OPTIONSr_fields,
  63950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63951         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63952         -1,
  63953         -1,
  63954     },
  63955 #endif /* chips */
  63956 
  63957 #if defined(BCM_88375_A0)
  63958     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88375_A0r */
  63959         soc_block_list[27],
  63960         soc_genreg,
  63961         1,
  63962         0,
  63963         0xc0,
  63964         SOC_REG_FLAG_WO,
  63965         0,
  63966         4,
  63967         soc_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88375_A0r_fields,
  63968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63969         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63970         -1,
  63971         -1,
  63972     },
  63973 #endif /* chips */
  63974 
  63975 #if defined(BCM_88375_B0)
  63976     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88375_B0r */
  63977         soc_block_list[27],
  63978         soc_genreg,
  63979         1,
  63980         0,
  63981         0xc0,
  63982         SOC_REG_FLAG_WO,
  63983         0,
  63984         4,
  63985         soc_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88375_B0r_fields,
  63986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  63987         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  63988         -1,
  63989         -1,
  63990     },
  63991 #endif /* chips */
  63992 
  63993 #if defined(BCM_88675_B0)
  63994     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88675_B0r */
  63995         soc_block_list[27],
  63996         soc_genreg,
  63997         1,
  63998         0,
  63999         0xc0,
  64000         SOC_REG_FLAG_WO,
  64001         0,
  64002         4,
  64003         soc_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88675_B0r_fields,
  64004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64005         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  64006         -1,
  64007         -1,
  64008     },
  64009 #endif /* chips */
  64010 
  64011 #if defined(BCM_88680_A0)
  64012     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88680_A0r */
  64013         soc_block_list[27],
  64014         soc_genreg,
  64015         1,
  64016         0,
  64017         0xc0,
  64018         SOC_REG_FLAG_WO,
  64019         0,
  64020         4,
  64021         soc_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88680_A0r_fields,
  64022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64023         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  64024         -1,
  64025         -1,
  64026     },
  64027 #endif /* chips */
  64028 
  64029 #if defined(BCM_88690_A0)
  64030     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88690_A0r */
  64031         soc_block_list[27],
  64032         soc_genreg,
  64033         1,
  64034         0,
  64035         0xc2,
  64036         SOC_REG_FLAG_WO,
  64037         0,
  64038         6,
  64039         soc_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88690_A0r_fields,
  64040         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  64041         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64042         -1,
  64043         -1,
  64044     },
  64045 #endif /* chips */
  64046 
  64047 #if defined(BCM_88790_A0)
  64048     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88790_A0r */
  64049         soc_block_list[27],
  64050         soc_genreg,
  64051         1,
  64052         0,
  64053         0xc2,
  64054         SOC_REG_FLAG_WO,
  64055         0,
  64056         6,
  64057         soc_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88790_A0r_fields,
  64058         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  64059         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  64060         -1,
  64061         -1,
  64062     },
  64063 #endif /* chips */
  64064 
  64065 #if defined(BCM_88950_A0)
  64066     { /* SOC_REG_INT_BRDC_FSRD_GLOBAL_MEM_OPTIONS_BCM88950_A0r */
  64067         soc_block_list[27],
  64068         soc_genreg,
  64069         1,
  64070         0,
  64071         0xc0,
  64072         SOC_REG_FLAG_WO,
  64073         0,
  64074         3,
  64075         soc_BRDC_DCH_GLOBAL_MEM_OPTIONSr_fields,
  64076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64077         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64078         -1,
  64079         -1,
  64080     },
  64081 #endif /* chips */
  64082 
  64083 #if defined(BCM_88675_A0)
  64084     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATIONr */
  64085         soc_block_list[27],
  64086         soc_genreg,
  64087         1,
  64088         0,
  64089         0x88,
  64090         SOC_REG_FLAG_WO,
  64091         0,
  64092         3,
  64093         soc_BRDC_FSRD_GTIMER_CONFIGURATIONr_fields,
  64094         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64096         -1,
  64097         -1,
  64098     },
  64099 #endif /* chips */
  64100 
  64101 #if defined(BCM_88375_A0)
  64102     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88375_A0r */
  64103         soc_block_list[27],
  64104         soc_genreg,
  64105         1,
  64106         0,
  64107         0x88,
  64108         SOC_REG_FLAG_WO,
  64109         0,
  64110         3,
  64111         soc_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88375_A0r_fields,
  64112         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64114         -1,
  64115         -1,
  64116     },
  64117 #endif /* chips */
  64118 
  64119 #if defined(BCM_88375_B0)
  64120     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88375_B0r */
  64121         soc_block_list[27],
  64122         soc_genreg,
  64123         1,
  64124         0,
  64125         0x88,
  64126         SOC_REG_FLAG_WO,
  64127         0,
  64128         3,
  64129         soc_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88375_B0r_fields,
  64130         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64132         -1,
  64133         -1,
  64134     },
  64135 #endif /* chips */
  64136 
  64137 #if defined(BCM_88675_B0)
  64138     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88675_B0r */
  64139         soc_block_list[27],
  64140         soc_genreg,
  64141         1,
  64142         0,
  64143         0x88,
  64144         SOC_REG_FLAG_WO,
  64145         0,
  64146         3,
  64147         soc_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88675_B0r_fields,
  64148         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64150         -1,
  64151         -1,
  64152     },
  64153 #endif /* chips */
  64154 
  64155 #if defined(BCM_88680_A0)
  64156     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88680_A0r */
  64157         soc_block_list[27],
  64158         soc_genreg,
  64159         1,
  64160         0,
  64161         0x88,
  64162         SOC_REG_FLAG_WO,
  64163         0,
  64164         3,
  64165         soc_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88680_A0r_fields,
  64166         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64168         -1,
  64169         -1,
  64170     },
  64171 #endif /* chips */
  64172 
  64173 #if defined(BCM_88690_A0)
  64174     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88690_A0r */
  64175         soc_block_list[27],
  64176         soc_genreg,
  64177         1,
  64178         0,
  64179         0x89,
  64180         SOC_REG_FLAG_WO,
  64181         0,
  64182         3,
  64183         soc_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88690_A0r_fields,
  64184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64185         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64186         -1,
  64187         -1,
  64188     },
  64189 #endif /* chips */
  64190 
  64191 #if defined(BCM_88690_B0)
  64192     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88690_B0r */
  64193         soc_block_list[27],
  64194         soc_genreg,
  64195         1,
  64196         0,
  64197         0x89,
  64198         SOC_REG_FLAG_WO,
  64199         0,
  64200         3,
  64201         soc_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
  64202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64203         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64204         -1,
  64205         -1,
  64206     },
  64207 #endif /* chips */
  64208 
  64209 #if defined(BCM_88790_A0)
  64210     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88790_A0r */
  64211         soc_block_list[27],
  64212         soc_genreg,
  64213         1,
  64214         0,
  64215         0x89,
  64216         SOC_REG_FLAG_WO,
  64217         0,
  64218         3,
  64219         soc_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88790_A0r_fields,
  64220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64221         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  64222         -1,
  64223         -1,
  64224     },
  64225 #endif /* chips */
  64226 
  64227 #if defined(BCM_88950_A0)
  64228     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CONFIGURATION_BCM88950_A0r */
  64229         soc_block_list[27],
  64230         soc_genreg,
  64231         1,
  64232         0,
  64233         0x88,
  64234         SOC_REG_FLAG_WO,
  64235         0,
  64236         3,
  64237         soc_BRDC_CCS_GTIMER_CONFIGURATIONr_fields,
  64238         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64240         -1,
  64241         -1,
  64242     },
  64243 #endif /* chips */
  64244 
  64245 #if defined(BCM_88790_A0)
  64246     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CYCLEr */
  64247         soc_block_list[27],
  64248         soc_genreg,
  64249         1,
  64250         0,
  64251         0x88,
  64252         SOC_REG_FLAG_WO,
  64253         0,
  64254         1,
  64255         soc_BRDC_FSRD_GTIMER_CYCLEr_fields,
  64256         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64258         -1,
  64259         -1,
  64260     },
  64261 #endif /* chips */
  64262 
  64263 #if defined(BCM_88690_A0)
  64264     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CYCLE_BCM88690_A0r */
  64265         soc_block_list[27],
  64266         soc_genreg,
  64267         1,
  64268         0,
  64269         0x88,
  64270         SOC_REG_FLAG_WO,
  64271         0,
  64272         1,
  64273         soc_BRDC_FSRD_GTIMER_CYCLE_BCM88690_A0r_fields,
  64274         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  64275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64276         -1,
  64277         -1,
  64278     },
  64279 #endif /* chips */
  64280 
  64281 #if defined(BCM_88690_B0)
  64282     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_CYCLE_BCM88690_B0r */
  64283         soc_block_list[27],
  64284         soc_genreg,
  64285         1,
  64286         0,
  64287         0x88,
  64288         SOC_REG_FLAG_WO,
  64289         0,
  64290         1,
  64291         soc_BRDC_FSRD_GTIMER_CYCLE_BCM88690_B0r_fields,
  64292         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  64293         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64294         -1,
  64295         -1,
  64296     },
  64297 #endif /* chips */
  64298 
  64299 #if defined(BCM_88675_A0)
  64300     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_TRIGGERr */
  64301         soc_block_list[27],
  64302         soc_genreg,
  64303         1,
  64304         0,
  64305         0x89,
  64306         SOC_REG_FLAG_RO |
  64307                           SOC_REG_FLAG_WO,
  64308         0,
  64309         1,
  64310         soc_BRDC_FSRD_GTIMER_TRIGGERr_fields,
  64311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64312         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  64313         -1,
  64314         -1,
  64315     },
  64316 #endif /* chips */
  64317 
  64318 #if defined(BCM_88375_A0)
  64319     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_TRIGGER_BCM88375_A0r */
  64320         soc_block_list[27],
  64321         soc_genreg,
  64322         1,
  64323         0,
  64324         0x89,
  64325         SOC_REG_FLAG_RO |
  64326                           SOC_REG_FLAG_WO,
  64327         0,
  64328         1,
  64329         soc_BRDC_FSRD_GTIMER_TRIGGER_BCM88375_A0r_fields,
  64330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64331         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  64332         -1,
  64333         -1,
  64334     },
  64335 #endif /* chips */
  64336 
  64337 #if defined(BCM_88375_B0)
  64338     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_TRIGGER_BCM88375_B0r */
  64339         soc_block_list[27],
  64340         soc_genreg,
  64341         1,
  64342         0,
  64343         0x89,
  64344         SOC_REG_FLAG_RO |
  64345                           SOC_REG_FLAG_WO,
  64346         0,
  64347         1,
  64348         soc_BRDC_FSRD_GTIMER_TRIGGER_BCM88375_B0r_fields,
  64349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64350         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  64351         -1,
  64352         -1,
  64353     },
  64354 #endif /* chips */
  64355 
  64356 #if defined(BCM_88675_B0)
  64357     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_TRIGGER_BCM88675_B0r */
  64358         soc_block_list[27],
  64359         soc_genreg,
  64360         1,
  64361         0,
  64362         0x89,
  64363         SOC_REG_FLAG_RO |
  64364                           SOC_REG_FLAG_WO,
  64365         0,
  64366         1,
  64367         soc_BRDC_FSRD_GTIMER_TRIGGER_BCM88675_B0r_fields,
  64368         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64369         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  64370         -1,
  64371         -1,
  64372     },
  64373 #endif /* chips */
  64374 
  64375 #if defined(BCM_88680_A0)
  64376     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_TRIGGER_BCM88680_A0r */
  64377         soc_block_list[27],
  64378         soc_genreg,
  64379         1,
  64380         0,
  64381         0x89,
  64382         SOC_REG_FLAG_RO |
  64383                           SOC_REG_FLAG_WO,
  64384         0,
  64385         1,
  64386         soc_BRDC_FSRD_GTIMER_TRIGGER_BCM88680_A0r_fields,
  64387         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64388         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  64389         -1,
  64390         -1,
  64391     },
  64392 #endif /* chips */
  64393 
  64394 #if defined(BCM_88950_A0)
  64395     { /* SOC_REG_INT_BRDC_FSRD_GTIMER_TRIGGER_BCM88950_A0r */
  64396         soc_block_list[27],
  64397         soc_genreg,
  64398         1,
  64399         0,
  64400         0x89,
  64401         SOC_REG_FLAG_RO |
  64402                           SOC_REG_FLAG_WO,
  64403         0,
  64404         1,
  64405         soc_BRDC_CCS_GTIMER_TRIGGERr_fields,
  64406         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64407         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  64408         -1,
  64409         -1,
  64410     },
  64411 #endif /* chips */
  64412 
  64413 #if defined(BCM_88650_A0)
  64414     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMANDr */
  64415         soc_block_list[27],
  64416         soc_genreg,
  64417         1,
  64418         0,
  64419         0x80,
  64420         SOC_REG_FLAG_WO,
  64421         0,
  64422         5,
  64423         soc_BRDC_FSRD_INDIRECT_COMMANDr_fields,
  64424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64425         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64426         -1,
  64427         -1,
  64428     },
  64429 #endif /* chips */
  64430 
  64431 #if defined(BCM_88650_A0)
  64432     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESSr */
  64433         soc_block_list[27],
  64434         soc_genreg,
  64435         1,
  64436         0,
  64437         0x81,
  64438         SOC_REG_FLAG_WO,
  64439         0,
  64440         2,
  64441         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESSr_fields,
  64442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64444         -1,
  64445         -1,
  64446     },
  64447 #endif /* chips */
  64448 
  64449 #if defined(BCM_88202_A0)
  64450     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88202_A0r */
  64451         soc_block_list[27],
  64452         soc_genreg,
  64453         1,
  64454         0,
  64455         0x81,
  64456         SOC_REG_FLAG_WO,
  64457         0,
  64458         2,
  64459         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88202_A0r_fields,
  64460         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64461         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64462         -1,
  64463         -1,
  64464     },
  64465 #endif /* chips */
  64466 
  64467 #if defined(BCM_88375_A0)
  64468     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r */
  64469         soc_block_list[27],
  64470         soc_genreg,
  64471         1,
  64472         0,
  64473         0x81,
  64474         SOC_REG_FLAG_WO,
  64475         0,
  64476         2,
  64477         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88375_A0r_fields,
  64478         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64479         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64480         -1,
  64481         -1,
  64482     },
  64483 #endif /* chips */
  64484 
  64485 #if defined(BCM_88375_B0)
  64486     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r */
  64487         soc_block_list[27],
  64488         soc_genreg,
  64489         1,
  64490         0,
  64491         0x81,
  64492         SOC_REG_FLAG_WO,
  64493         0,
  64494         2,
  64495         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88375_B0r_fields,
  64496         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64497         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64498         -1,
  64499         -1,
  64500     },
  64501 #endif /* chips */
  64502 
  64503 #if defined(BCM_88650_B0)
  64504     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r */
  64505         soc_block_list[27],
  64506         soc_genreg,
  64507         1,
  64508         0,
  64509         0x81,
  64510         SOC_REG_FLAG_WO,
  64511         0,
  64512         2,
  64513         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88650_B0r_fields,
  64514         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64515         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64516         -1,
  64517         -1,
  64518     },
  64519 #endif /* chips */
  64520 
  64521 #if defined(BCM_88660_A0)
  64522     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r */
  64523         soc_block_list[27],
  64524         soc_genreg,
  64525         1,
  64526         0,
  64527         0x81,
  64528         SOC_REG_FLAG_WO,
  64529         0,
  64530         2,
  64531         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88660_A0r_fields,
  64532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64533         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64534         -1,
  64535         -1,
  64536     },
  64537 #endif /* chips */
  64538 
  64539 #if defined(BCM_88675_A0)
  64540     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r */
  64541         soc_block_list[27],
  64542         soc_genreg,
  64543         1,
  64544         0,
  64545         0x81,
  64546         SOC_REG_FLAG_WO,
  64547         0,
  64548         2,
  64549         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88675_A0r_fields,
  64550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64551         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64552         -1,
  64553         -1,
  64554     },
  64555 #endif /* chips */
  64556 
  64557 #if defined(BCM_88675_B0)
  64558     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r */
  64559         soc_block_list[27],
  64560         soc_genreg,
  64561         1,
  64562         0,
  64563         0x81,
  64564         SOC_REG_FLAG_WO,
  64565         0,
  64566         2,
  64567         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88675_B0r_fields,
  64568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64569         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64570         -1,
  64571         -1,
  64572     },
  64573 #endif /* chips */
  64574 
  64575 #if defined(BCM_88680_A0)
  64576     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r */
  64577         soc_block_list[27],
  64578         soc_genreg,
  64579         1,
  64580         0,
  64581         0x81,
  64582         SOC_REG_FLAG_WO,
  64583         0,
  64584         2,
  64585         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88680_A0r_fields,
  64586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64587         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64588         -1,
  64589         -1,
  64590     },
  64591 #endif /* chips */
  64592 
  64593 #if defined(BCM_88690_A0)
  64594     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r */
  64595         soc_block_list[27],
  64596         soc_genreg,
  64597         1,
  64598         0,
  64599         0x81,
  64600         SOC_REG_FLAG_WO,
  64601         0,
  64602         2,
  64603         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88690_A0r_fields,
  64604         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64605         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64606         -1,
  64607         -1,
  64608     },
  64609 #endif /* chips */
  64610 
  64611 #if defined(BCM_88690_B0)
  64612     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
  64613         soc_block_list[27],
  64614         soc_genreg,
  64615         1,
  64616         0,
  64617         0x81,
  64618         SOC_REG_FLAG_WO,
  64619         0,
  64620         2,
  64621         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
  64622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64623         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64624         -1,
  64625         -1,
  64626     },
  64627 #endif /* chips */
  64628 
  64629 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  64630     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88750_A0r */
  64631         soc_block_list[27],
  64632         soc_genreg,
  64633         1,
  64634         0,
  64635         0x41,
  64636         SOC_REG_FLAG_WO,
  64637         0,
  64638         2,
  64639         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88750_A0r_fields,
  64640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64641         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64642         -1,
  64643         -1,
  64644     },
  64645 #endif /* chips */
  64646 
  64647 #if defined(BCM_88790_A0)
  64648     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88790_A0r */
  64649         soc_block_list[27],
  64650         soc_genreg,
  64651         1,
  64652         0,
  64653         0x81,
  64654         SOC_REG_FLAG_WO,
  64655         0,
  64656         2,
  64657         soc_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88790_A0r_fields,
  64658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64659         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64660         -1,
  64661         -1,
  64662     },
  64663 #endif /* chips */
  64664 
  64665 #if defined(BCM_88950_A0)
  64666     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_ADDRESS_BCM88950_A0r */
  64667         soc_block_list[27],
  64668         soc_genreg,
  64669         1,
  64670         0,
  64671         0x81,
  64672         SOC_REG_FLAG_WO,
  64673         0,
  64674         2,
  64675         soc_BRDC_DCL_INDIRECT_COMMAND_ADDRESSr_fields,
  64676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64677         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64678         -1,
  64679         -1,
  64680     },
  64681 #endif /* chips */
  64682 
  64683 #if defined(BCM_88202_A0)
  64684     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88202_A0r */
  64685         soc_block_list[27],
  64686         soc_genreg,
  64687         1,
  64688         0,
  64689         0x80,
  64690         SOC_REG_FLAG_WO,
  64691         0,
  64692         5,
  64693         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88202_A0r_fields,
  64694         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64695         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64696         -1,
  64697         -1,
  64698     },
  64699 #endif /* chips */
  64700 
  64701 #if defined(BCM_88375_A0)
  64702     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88375_A0r */
  64703         soc_block_list[27],
  64704         soc_genreg,
  64705         1,
  64706         0,
  64707         0x80,
  64708         SOC_REG_FLAG_WO,
  64709         0,
  64710         5,
  64711         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88375_A0r_fields,
  64712         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64713         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64714         -1,
  64715         -1,
  64716     },
  64717 #endif /* chips */
  64718 
  64719 #if defined(BCM_88375_B0)
  64720     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88375_B0r */
  64721         soc_block_list[27],
  64722         soc_genreg,
  64723         1,
  64724         0,
  64725         0x80,
  64726         SOC_REG_FLAG_WO,
  64727         0,
  64728         5,
  64729         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88375_B0r_fields,
  64730         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64731         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64732         -1,
  64733         -1,
  64734     },
  64735 #endif /* chips */
  64736 
  64737 #if defined(BCM_88650_B0)
  64738     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88650_B0r */
  64739         soc_block_list[27],
  64740         soc_genreg,
  64741         1,
  64742         0,
  64743         0x80,
  64744         SOC_REG_FLAG_WO,
  64745         0,
  64746         5,
  64747         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88650_B0r_fields,
  64748         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64749         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64750         -1,
  64751         -1,
  64752     },
  64753 #endif /* chips */
  64754 
  64755 #if defined(BCM_88660_A0)
  64756     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88660_A0r */
  64757         soc_block_list[27],
  64758         soc_genreg,
  64759         1,
  64760         0,
  64761         0x80,
  64762         SOC_REG_FLAG_WO,
  64763         0,
  64764         5,
  64765         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88660_A0r_fields,
  64766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64767         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64768         -1,
  64769         -1,
  64770     },
  64771 #endif /* chips */
  64772 
  64773 #if defined(BCM_88675_A0)
  64774     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88675_A0r */
  64775         soc_block_list[27],
  64776         soc_genreg,
  64777         1,
  64778         0,
  64779         0x80,
  64780         SOC_REG_FLAG_WO,
  64781         0,
  64782         5,
  64783         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88675_A0r_fields,
  64784         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64786         -1,
  64787         -1,
  64788     },
  64789 #endif /* chips */
  64790 
  64791 #if defined(BCM_88675_B0)
  64792     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88675_B0r */
  64793         soc_block_list[27],
  64794         soc_genreg,
  64795         1,
  64796         0,
  64797         0x80,
  64798         SOC_REG_FLAG_WO,
  64799         0,
  64800         5,
  64801         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88675_B0r_fields,
  64802         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64803         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64804         -1,
  64805         -1,
  64806     },
  64807 #endif /* chips */
  64808 
  64809 #if defined(BCM_88680_A0)
  64810     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88680_A0r */
  64811         soc_block_list[27],
  64812         soc_genreg,
  64813         1,
  64814         0,
  64815         0x80,
  64816         SOC_REG_FLAG_WO,
  64817         0,
  64818         5,
  64819         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88680_A0r_fields,
  64820         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64821         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64822         -1,
  64823         -1,
  64824     },
  64825 #endif /* chips */
  64826 
  64827 #if defined(BCM_88690_A0)
  64828     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88690_A0r */
  64829         soc_block_list[27],
  64830         soc_genreg,
  64831         1,
  64832         0,
  64833         0x80,
  64834         SOC_REG_FLAG_WO,
  64835         0,
  64836         5,
  64837         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88690_A0r_fields,
  64838         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64839         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64840         -1,
  64841         -1,
  64842     },
  64843 #endif /* chips */
  64844 
  64845 #if defined(BCM_88690_B0)
  64846     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88690_B0r */
  64847         soc_block_list[27],
  64848         soc_genreg,
  64849         1,
  64850         0,
  64851         0x80,
  64852         SOC_REG_FLAG_WO,
  64853         0,
  64854         5,
  64855         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88690_B0r_fields,
  64856         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  64857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64858         -1,
  64859         -1,
  64860     },
  64861 #endif /* chips */
  64862 
  64863 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  64864     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88750_A0r */
  64865         soc_block_list[27],
  64866         soc_genreg,
  64867         1,
  64868         0,
  64869         0x40,
  64870         SOC_REG_FLAG_WO,
  64871         0,
  64872         5,
  64873         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88750_A0r_fields,
  64874         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64875         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64876         -1,
  64877         -1,
  64878     },
  64879 #endif /* chips */
  64880 
  64881 #if defined(BCM_88790_A0)
  64882     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88790_A0r */
  64883         soc_block_list[27],
  64884         soc_genreg,
  64885         1,
  64886         0,
  64887         0x80,
  64888         SOC_REG_FLAG_WO,
  64889         0,
  64890         5,
  64891         soc_BRDC_FSRD_INDIRECT_COMMAND_BCM88790_A0r_fields,
  64892         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64893         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64894         -1,
  64895         -1,
  64896     },
  64897 #endif /* chips */
  64898 
  64899 #if defined(BCM_88950_A0)
  64900     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_BCM88950_A0r */
  64901         soc_block_list[27],
  64902         soc_genreg,
  64903         1,
  64904         0,
  64905         0x80,
  64906         SOC_REG_FLAG_WO,
  64907         0,
  64908         5,
  64909         soc_BRDC_DCL_INDIRECT_COMMANDr_fields,
  64910         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  64911         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  64912         -1,
  64913         -1,
  64914     },
  64915 #endif /* chips */
  64916 
  64917 #if defined(BCM_88650_A0)
  64918     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENTr */
  64919         soc_block_list[27],
  64920         soc_genreg,
  64921         1,
  64922         0,
  64923         0x82,
  64924         SOC_REG_FLAG_64_BITS |
  64925                           SOC_REG_FLAG_WO,
  64926         0,
  64927         1,
  64928         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  64929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64930         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  64931         -1,
  64932         -1,
  64933     },
  64934 #endif /* chips */
  64935 
  64936 #if defined(BCM_88202_A0)
  64937     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88202_A0r */
  64938         soc_block_list[27],
  64939         soc_genreg,
  64940         1,
  64941         0,
  64942         0x82,
  64943         SOC_REG_FLAG_64_BITS |
  64944                           SOC_REG_FLAG_WO,
  64945         0,
  64946         1,
  64947         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88202_A0r_fields,
  64948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64949         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  64950         -1,
  64951         -1,
  64952     },
  64953 #endif /* chips */
  64954 
  64955 #if defined(BCM_88375_A0)
  64956     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r */
  64957         soc_block_list[27],
  64958         soc_genreg,
  64959         1,
  64960         0,
  64961         0x82,
  64962         SOC_REG_FLAG_64_BITS |
  64963                           SOC_REG_FLAG_WO,
  64964         0,
  64965         1,
  64966         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_A0r_fields,
  64967         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64968         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  64969         -1,
  64970         -1,
  64971     },
  64972 #endif /* chips */
  64973 
  64974 #if defined(BCM_88375_B0)
  64975     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r */
  64976         soc_block_list[27],
  64977         soc_genreg,
  64978         1,
  64979         0,
  64980         0x82,
  64981         SOC_REG_FLAG_64_BITS |
  64982                           SOC_REG_FLAG_WO,
  64983         0,
  64984         1,
  64985         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88375_B0r_fields,
  64986         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  64987         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  64988         -1,
  64989         -1,
  64990     },
  64991 #endif /* chips */
  64992 
  64993 #if defined(BCM_88650_B0)
  64994     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r */
  64995         soc_block_list[27],
  64996         soc_genreg,
  64997         1,
  64998         0,
  64999         0x82,
  65000         SOC_REG_FLAG_64_BITS |
  65001                           SOC_REG_FLAG_WO,
  65002         0,
  65003         1,
  65004         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88650_B0r_fields,
  65005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65006         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65007         -1,
  65008         -1,
  65009     },
  65010 #endif /* chips */
  65011 
  65012 #if defined(BCM_88660_A0)
  65013     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r */
  65014         soc_block_list[27],
  65015         soc_genreg,
  65016         1,
  65017         0,
  65018         0x82,
  65019         SOC_REG_FLAG_64_BITS |
  65020                           SOC_REG_FLAG_WO,
  65021         0,
  65022         1,
  65023         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88660_A0r_fields,
  65024         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65025         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65026         -1,
  65027         -1,
  65028     },
  65029 #endif /* chips */
  65030 
  65031 #if defined(BCM_88675_A0)
  65032     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r */
  65033         soc_block_list[27],
  65034         soc_genreg,
  65035         1,
  65036         0,
  65037         0x82,
  65038         SOC_REG_FLAG_64_BITS |
  65039                           SOC_REG_FLAG_WO,
  65040         0,
  65041         1,
  65042         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_A0r_fields,
  65043         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65044         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65045         -1,
  65046         -1,
  65047     },
  65048 #endif /* chips */
  65049 
  65050 #if defined(BCM_88675_B0)
  65051     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r */
  65052         soc_block_list[27],
  65053         soc_genreg,
  65054         1,
  65055         0,
  65056         0x82,
  65057         SOC_REG_FLAG_64_BITS |
  65058                           SOC_REG_FLAG_WO,
  65059         0,
  65060         1,
  65061         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88675_B0r_fields,
  65062         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65063         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65064         -1,
  65065         -1,
  65066     },
  65067 #endif /* chips */
  65068 
  65069 #if defined(BCM_88680_A0)
  65070     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r */
  65071         soc_block_list[27],
  65072         soc_genreg,
  65073         1,
  65074         0,
  65075         0x82,
  65076         SOC_REG_FLAG_64_BITS |
  65077                           SOC_REG_FLAG_WO,
  65078         0,
  65079         1,
  65080         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88680_A0r_fields,
  65081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65082         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65083         -1,
  65084         -1,
  65085     },
  65086 #endif /* chips */
  65087 
  65088 #if defined(BCM_88690_A0)
  65089     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88690_A0r */
  65090         soc_block_list[27],
  65091         soc_genreg,
  65092         1,
  65093         0,
  65094         0x82,
  65095         SOC_REG_FLAG_64_BITS |
  65096                           SOC_REG_FLAG_WO,
  65097         0,
  65098         1,
  65099         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88690_A0r_fields,
  65100         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65101         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65102         -1,
  65103         -1,
  65104     },
  65105 #endif /* chips */
  65106 
  65107 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  65108     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88750_A0r */
  65109         soc_block_list[27],
  65110         soc_genreg,
  65111         1,
  65112         0,
  65113         0x42,
  65114         SOC_REG_FLAG_64_BITS |
  65115                           SOC_REG_FLAG_WO,
  65116         0,
  65117         1,
  65118         soc_ECI_INDIRECT_COMMAND_DATA_INCREMENT_BCM83207_A0r_fields,
  65119         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65120         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65121         -1,
  65122         -1,
  65123     },
  65124 #endif /* chips */
  65125 
  65126 #if defined(BCM_88790_A0)
  65127     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88790_A0r */
  65128         soc_block_list[27],
  65129         soc_genreg,
  65130         1,
  65131         0,
  65132         0x82,
  65133         SOC_REG_FLAG_64_BITS |
  65134                           SOC_REG_FLAG_WO,
  65135         0,
  65136         1,
  65137         soc_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88790_A0r_fields,
  65138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65139         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65140         -1,
  65141         -1,
  65142     },
  65143 #endif /* chips */
  65144 
  65145 #if defined(BCM_88950_A0)
  65146     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT_BCM88950_A0r */
  65147         soc_block_list[27],
  65148         soc_genreg,
  65149         1,
  65150         0,
  65151         0x82,
  65152         SOC_REG_FLAG_64_BITS |
  65153                           SOC_REG_FLAG_WO,
  65154         0,
  65155         1,
  65156         soc_BRDC_DCL_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  65157         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65158         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  65159         -1,
  65160         -1,
  65161     },
  65162 #endif /* chips */
  65163 
  65164 #if defined(BCM_88650_A0)
  65165     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_RD_DATAr */
  65166         soc_block_list[27],
  65167         soc_genreg,
  65168         1,
  65169         0,
  65170         0x60,
  65171         SOC_REG_FLAG_ABOVE_64_BITS |
  65172                           SOC_REG_FLAG_WO,
  65173         0,
  65174         1,
  65175         soc_BRDC_FSRD_INDIRECT_COMMAND_RD_DATAr_fields,
  65176         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65177         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65178         -1,
  65179         -1,
  65180     },
  65181 #endif /* chips */
  65182 
  65183 #if defined(BCM_88202_A0)
  65184     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88202_A0r */
  65185         soc_block_list[27],
  65186         soc_genreg,
  65187         1,
  65188         0,
  65189         0x60,
  65190         SOC_REG_FLAG_ABOVE_64_BITS |
  65191                           SOC_REG_FLAG_WO,
  65192         0,
  65193         1,
  65194         soc_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88202_A0r_fields,
  65195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65196         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65197         -1,
  65198         -1,
  65199     },
  65200 #endif /* chips */
  65201 
  65202 #if defined(BCM_88650_B0)
  65203     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88650_B0r */
  65204         soc_block_list[27],
  65205         soc_genreg,
  65206         1,
  65207         0,
  65208         0x60,
  65209         SOC_REG_FLAG_ABOVE_64_BITS |
  65210                           SOC_REG_FLAG_WO,
  65211         0,
  65212         1,
  65213         soc_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88650_B0r_fields,
  65214         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65215         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65216         -1,
  65217         -1,
  65218     },
  65219 #endif /* chips */
  65220 
  65221 #if defined(BCM_88660_A0)
  65222     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88660_A0r */
  65223         soc_block_list[27],
  65224         soc_genreg,
  65225         1,
  65226         0,
  65227         0x60,
  65228         SOC_REG_FLAG_ABOVE_64_BITS |
  65229                           SOC_REG_FLAG_WO,
  65230         0,
  65231         1,
  65232         soc_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88660_A0r_fields,
  65233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65234         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65235         -1,
  65236         -1,
  65237     },
  65238 #endif /* chips */
  65239 
  65240 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  65241     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88750_A0r */
  65242         soc_block_list[27],
  65243         soc_genreg,
  65244         1,
  65245         0,
  65246         0x30,
  65247         SOC_REG_FLAG_ABOVE_64_BITS |
  65248                           SOC_REG_FLAG_RO |
  65249                           SOC_REG_FLAG_WO,
  65250         0,
  65251         1,
  65252         soc_BRDC_FSRD_INDIRECT_COMMAND_RD_DATA_BCM88750_A0r_fields,
  65253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65254         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65255         -1,
  65256         -1,
  65257     },
  65258 #endif /* chips */
  65259 
  65260 #if defined(BCM_88675_A0)
  65261     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEMr */
  65262         soc_block_list[27],
  65263         soc_genreg,
  65264         1,
  65265         0,
  65266         0x41,
  65267         SOC_REG_FLAG_WO,
  65268         0,
  65269         1,
  65270         soc_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEMr_fields,
  65271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65272         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65273         -1,
  65274         -1,
  65275     },
  65276 #endif /* chips */
  65277 
  65278 #if defined(BCM_88375_A0)
  65279     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r */
  65280         soc_block_list[27],
  65281         soc_genreg,
  65282         1,
  65283         0,
  65284         0x41,
  65285         SOC_REG_FLAG_WO,
  65286         0,
  65287         1,
  65288         soc_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88375_A0r_fields,
  65289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65290         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65291         -1,
  65292         -1,
  65293     },
  65294 #endif /* chips */
  65295 
  65296 #if defined(BCM_88375_B0)
  65297     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r */
  65298         soc_block_list[27],
  65299         soc_genreg,
  65300         1,
  65301         0,
  65302         0x41,
  65303         SOC_REG_FLAG_WO,
  65304         0,
  65305         1,
  65306         soc_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88375_B0r_fields,
  65307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65308         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65309         -1,
  65310         -1,
  65311     },
  65312 #endif /* chips */
  65313 
  65314 #if defined(BCM_88675_B0)
  65315     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r */
  65316         soc_block_list[27],
  65317         soc_genreg,
  65318         1,
  65319         0,
  65320         0x41,
  65321         SOC_REG_FLAG_WO,
  65322         0,
  65323         1,
  65324         soc_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88675_B0r_fields,
  65325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65326         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65327         -1,
  65328         -1,
  65329     },
  65330 #endif /* chips */
  65331 
  65332 #if defined(BCM_88680_A0)
  65333     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r */
  65334         soc_block_list[27],
  65335         soc_genreg,
  65336         1,
  65337         0,
  65338         0x41,
  65339         SOC_REG_FLAG_WO,
  65340         0,
  65341         1,
  65342         soc_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88680_A0r_fields,
  65343         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65344         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65345         -1,
  65346         -1,
  65347     },
  65348 #endif /* chips */
  65349 
  65350 #if defined(BCM_88690_A0)
  65351     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88690_A0r */
  65352         soc_block_list[27],
  65353         soc_genreg,
  65354         1,
  65355         0,
  65356         0x41,
  65357         SOC_REG_FLAG_WO,
  65358         0,
  65359         1,
  65360         soc_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88690_A0r_fields,
  65361         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65362         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65363         -1,
  65364         -1,
  65365     },
  65366 #endif /* chips */
  65367 
  65368 #if defined(BCM_88790_A0)
  65369     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88790_A0r */
  65370         soc_block_list[27],
  65371         soc_genreg,
  65372         1,
  65373         0,
  65374         0x41,
  65375         SOC_REG_FLAG_WO,
  65376         0,
  65377         1,
  65378         soc_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88790_A0r_fields,
  65379         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65380         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65381         -1,
  65382         -1,
  65383     },
  65384 #endif /* chips */
  65385 
  65386 #if defined(BCM_88950_A0)
  65387     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM_BCM88950_A0r */
  65388         soc_block_list[27],
  65389         soc_genreg,
  65390         1,
  65391         0,
  65392         0x41,
  65393         SOC_REG_FLAG_WO,
  65394         0,
  65395         1,
  65396         soc_BRDC_DCL_INDIRECT_COMMAND_WIDE_MEMr_fields,
  65397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65398         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  65399         -1,
  65400         -1,
  65401     },
  65402 #endif /* chips */
  65403 
  65404 #if defined(BCM_88650_A0)
  65405     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATAr */
  65406         soc_block_list[27],
  65407         soc_genreg,
  65408         1,
  65409         0,
  65410         0x20,
  65411         SOC_REG_FLAG_ABOVE_64_BITS |
  65412                           SOC_REG_FLAG_WO,
  65413         0,
  65414         1,
  65415         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATAr_fields,
  65416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65417         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65418         -1,
  65419         -1,
  65420     },
  65421 #endif /* chips */
  65422 
  65423 #if defined(BCM_88202_A0)
  65424     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88202_A0r */
  65425         soc_block_list[27],
  65426         soc_genreg,
  65427         1,
  65428         0,
  65429         0x20,
  65430         SOC_REG_FLAG_ABOVE_64_BITS |
  65431                           SOC_REG_FLAG_WO,
  65432         0,
  65433         1,
  65434         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88202_A0r_fields,
  65435         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65436         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65437         -1,
  65438         -1,
  65439     },
  65440 #endif /* chips */
  65441 
  65442 #if defined(BCM_88375_A0)
  65443     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r */
  65444         soc_block_list[27],
  65445         soc_genreg,
  65446         1,
  65447         0,
  65448         0x20,
  65449         SOC_REG_FLAG_ABOVE_64_BITS |
  65450                           SOC_REG_FLAG_WO,
  65451         0,
  65452         1,
  65453         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88375_A0r_fields,
  65454         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65455         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65456         -1,
  65457         -1,
  65458     },
  65459 #endif /* chips */
  65460 
  65461 #if defined(BCM_88375_B0)
  65462     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r */
  65463         soc_block_list[27],
  65464         soc_genreg,
  65465         1,
  65466         0,
  65467         0x20,
  65468         SOC_REG_FLAG_ABOVE_64_BITS |
  65469                           SOC_REG_FLAG_WO,
  65470         0,
  65471         1,
  65472         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88375_B0r_fields,
  65473         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65474         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65475         -1,
  65476         -1,
  65477     },
  65478 #endif /* chips */
  65479 
  65480 #if defined(BCM_88650_B0)
  65481     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88650_B0r */
  65482         soc_block_list[27],
  65483         soc_genreg,
  65484         1,
  65485         0,
  65486         0x20,
  65487         SOC_REG_FLAG_ABOVE_64_BITS |
  65488                           SOC_REG_FLAG_WO,
  65489         0,
  65490         1,
  65491         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88650_B0r_fields,
  65492         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65493         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65494         -1,
  65495         -1,
  65496     },
  65497 #endif /* chips */
  65498 
  65499 #if defined(BCM_88660_A0)
  65500     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88660_A0r */
  65501         soc_block_list[27],
  65502         soc_genreg,
  65503         1,
  65504         0,
  65505         0x20,
  65506         SOC_REG_FLAG_ABOVE_64_BITS |
  65507                           SOC_REG_FLAG_WO,
  65508         0,
  65509         1,
  65510         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88660_A0r_fields,
  65511         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65512         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65513         -1,
  65514         -1,
  65515     },
  65516 #endif /* chips */
  65517 
  65518 #if defined(BCM_88675_A0)
  65519     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88675_A0r */
  65520         soc_block_list[27],
  65521         soc_genreg,
  65522         1,
  65523         0,
  65524         0x20,
  65525         SOC_REG_FLAG_ABOVE_64_BITS |
  65526                           SOC_REG_FLAG_WO,
  65527         0,
  65528         1,
  65529         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88675_A0r_fields,
  65530         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65531         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65532         -1,
  65533         -1,
  65534     },
  65535 #endif /* chips */
  65536 
  65537 #if defined(BCM_88675_B0)
  65538     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r */
  65539         soc_block_list[27],
  65540         soc_genreg,
  65541         1,
  65542         0,
  65543         0x20,
  65544         SOC_REG_FLAG_ABOVE_64_BITS |
  65545                           SOC_REG_FLAG_WO,
  65546         0,
  65547         1,
  65548         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88675_B0r_fields,
  65549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65550         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65551         -1,
  65552         -1,
  65553     },
  65554 #endif /* chips */
  65555 
  65556 #if defined(BCM_88680_A0)
  65557     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r */
  65558         soc_block_list[27],
  65559         soc_genreg,
  65560         1,
  65561         0,
  65562         0x20,
  65563         SOC_REG_FLAG_ABOVE_64_BITS |
  65564                           SOC_REG_FLAG_WO,
  65565         0,
  65566         1,
  65567         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88680_A0r_fields,
  65568         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65569         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65570         -1,
  65571         -1,
  65572     },
  65573 #endif /* chips */
  65574 
  65575 #if defined(BCM_88690_A0)
  65576     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r */
  65577         soc_block_list[27],
  65578         soc_genreg,
  65579         1,
  65580         0,
  65581         0x20,
  65582         SOC_REG_FLAG_ABOVE_64_BITS |
  65583                           SOC_REG_FLAG_WO,
  65584         0,
  65585         1,
  65586         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88690_A0r_fields,
  65587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65588         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65589         -1,
  65590         -1,
  65591     },
  65592 #endif /* chips */
  65593 
  65594 #if defined(BCM_88690_B0)
  65595     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
  65596         soc_block_list[27],
  65597         soc_genreg,
  65598         1,
  65599         0,
  65600         0x20,
  65601         SOC_REG_FLAG_ABOVE_64_BITS |
  65602                           SOC_REG_FLAG_WO,
  65603         0,
  65604         1,
  65605         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
  65606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65607         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65608         -1,
  65609         -1,
  65610     },
  65611 #endif /* chips */
  65612 
  65613 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  65614     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88750_A0r */
  65615         soc_block_list[27],
  65616         soc_genreg,
  65617         1,
  65618         0,
  65619         0x20,
  65620         SOC_REG_FLAG_ABOVE_64_BITS |
  65621                           SOC_REG_FLAG_WO,
  65622         0,
  65623         1,
  65624         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88750_A0r_fields,
  65625         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65626         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65627         -1,
  65628         -1,
  65629     },
  65630 #endif /* chips */
  65631 
  65632 #if defined(BCM_88790_A0)
  65633     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88790_A0r */
  65634         soc_block_list[27],
  65635         soc_genreg,
  65636         1,
  65637         0,
  65638         0x20,
  65639         SOC_REG_FLAG_ABOVE_64_BITS |
  65640                           SOC_REG_FLAG_WO,
  65641         0,
  65642         1,
  65643         soc_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88790_A0r_fields,
  65644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65646         -1,
  65647         -1,
  65648     },
  65649 #endif /* chips */
  65650 
  65651 #if defined(BCM_88950_A0)
  65652     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_COMMAND_WR_DATA_BCM88950_A0r */
  65653         soc_block_list[27],
  65654         soc_genreg,
  65655         1,
  65656         0,
  65657         0x20,
  65658         SOC_REG_FLAG_ABOVE_64_BITS |
  65659                           SOC_REG_FLAG_WO,
  65660         0,
  65661         1,
  65662         soc_BRDC_DCL_INDIRECT_COMMAND_WR_DATAr_fields,
  65663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  65665         -1,
  65666         -1,
  65667     },
  65668 #endif /* chips */
  65669 
  65670 #if defined(BCM_88675_A0)
  65671     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLEr */
  65672         soc_block_list[27],
  65673         soc_genreg,
  65674         1,
  65675         0,
  65676         0x83,
  65677         SOC_REG_FLAG_WO,
  65678         0,
  65679         4,
  65680         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLEr_fields,
  65681         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65682         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  65683         -1,
  65684         -1,
  65685     },
  65686 #endif /* chips */
  65687 
  65688 #if defined(BCM_88375_A0)
  65689     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88375_A0r */
  65690         soc_block_list[27],
  65691         soc_genreg,
  65692         1,
  65693         0,
  65694         0x83,
  65695         SOC_REG_FLAG_WO,
  65696         0,
  65697         4,
  65698         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88375_A0r_fields,
  65699         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65700         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  65701         -1,
  65702         -1,
  65703     },
  65704 #endif /* chips */
  65705 
  65706 #if defined(BCM_88375_B0)
  65707     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88375_B0r */
  65708         soc_block_list[27],
  65709         soc_genreg,
  65710         1,
  65711         0,
  65712         0x83,
  65713         SOC_REG_FLAG_WO,
  65714         0,
  65715         4,
  65716         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88375_B0r_fields,
  65717         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65718         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  65719         -1,
  65720         -1,
  65721     },
  65722 #endif /* chips */
  65723 
  65724 #if defined(BCM_88675_B0)
  65725     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88675_B0r */
  65726         soc_block_list[27],
  65727         soc_genreg,
  65728         1,
  65729         0,
  65730         0x83,
  65731         SOC_REG_FLAG_WO,
  65732         0,
  65733         4,
  65734         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88675_B0r_fields,
  65735         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65736         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  65737         -1,
  65738         -1,
  65739     },
  65740 #endif /* chips */
  65741 
  65742 #if defined(BCM_88680_A0)
  65743     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88680_A0r */
  65744         soc_block_list[27],
  65745         soc_genreg,
  65746         1,
  65747         0,
  65748         0x83,
  65749         SOC_REG_FLAG_WO,
  65750         0,
  65751         4,
  65752         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88680_A0r_fields,
  65753         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65754         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  65755         -1,
  65756         -1,
  65757     },
  65758 #endif /* chips */
  65759 
  65760 #if defined(BCM_88690_A0)
  65761     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88690_A0r */
  65762         soc_block_list[27],
  65763         soc_genreg,
  65764         1,
  65765         0,
  65766         0x83,
  65767         SOC_REG_FLAG_WO,
  65768         0,
  65769         4,
  65770         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88690_A0r_fields,
  65771         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65772         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  65773         -1,
  65774         -1,
  65775     },
  65776 #endif /* chips */
  65777 
  65778 #if defined(BCM_88690_B0)
  65779     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
  65780         soc_block_list[27],
  65781         soc_genreg,
  65782         1,
  65783         0,
  65784         0x83,
  65785         SOC_REG_FLAG_WO,
  65786         0,
  65787         4,
  65788         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
  65789         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65790         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  65791         -1,
  65792         -1,
  65793     },
  65794 #endif /* chips */
  65795 
  65796 #if defined(BCM_88790_A0)
  65797     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88790_A0r */
  65798         soc_block_list[27],
  65799         soc_genreg,
  65800         1,
  65801         0,
  65802         0x83,
  65803         SOC_REG_FLAG_WO,
  65804         0,
  65805         4,
  65806         soc_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88790_A0r_fields,
  65807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65808         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  65809         -1,
  65810         -1,
  65811     },
  65812 #endif /* chips */
  65813 
  65814 #if defined(BCM_88950_A0)
  65815     { /* SOC_REG_INT_BRDC_FSRD_INDIRECT_FORCE_BUBBLE_BCM88950_A0r */
  65816         soc_block_list[27],
  65817         soc_genreg,
  65818         1,
  65819         0,
  65820         0x83,
  65821         SOC_REG_FLAG_WO,
  65822         0,
  65823         4,
  65824         soc_BRDC_DCL_INDIRECT_FORCE_BUBBLEr_fields,
  65825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65826         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  65827         -1,
  65828         -1,
  65829     },
  65830 #endif /* chips */
  65831 
  65832 #if defined(BCM_88650_A0)
  65833     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTERr */
  65834         soc_block_list[27],
  65835         soc_genreg,
  65836         1,
  65837         0,
  65838         0x10,
  65839         SOC_REG_FLAG_WO,
  65840         0,
  65841         3,
  65842         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTERr_fields,
  65843         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65844         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65845         -1,
  65846         -1,
  65847     },
  65848 #endif /* chips */
  65849 
  65850 #if defined(BCM_88202_A0)
  65851     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88202_A0r */
  65852         soc_block_list[27],
  65853         soc_genreg,
  65854         1,
  65855         0,
  65856         0x10,
  65857         SOC_REG_FLAG_WO,
  65858         0,
  65859         3,
  65860         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88202_A0r_fields,
  65861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65862         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65863         -1,
  65864         -1,
  65865     },
  65866 #endif /* chips */
  65867 
  65868 #if defined(BCM_88375_A0)
  65869     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88375_A0r */
  65870         soc_block_list[27],
  65871         soc_genreg,
  65872         1,
  65873         0,
  65874         0x10,
  65875         SOC_REG_FLAG_WO,
  65876         0,
  65877         4,
  65878         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88375_A0r_fields,
  65879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65880         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  65881         -1,
  65882         -1,
  65883     },
  65884 #endif /* chips */
  65885 
  65886 #if defined(BCM_88375_B0)
  65887     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88375_B0r */
  65888         soc_block_list[27],
  65889         soc_genreg,
  65890         1,
  65891         0,
  65892         0x10,
  65893         SOC_REG_FLAG_WO,
  65894         0,
  65895         4,
  65896         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88375_B0r_fields,
  65897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65898         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  65899         -1,
  65900         -1,
  65901     },
  65902 #endif /* chips */
  65903 
  65904 #if defined(BCM_88650_B0)
  65905     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88650_B0r */
  65906         soc_block_list[27],
  65907         soc_genreg,
  65908         1,
  65909         0,
  65910         0x10,
  65911         SOC_REG_FLAG_WO,
  65912         0,
  65913         3,
  65914         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88650_B0r_fields,
  65915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65916         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65917         -1,
  65918         -1,
  65919     },
  65920 #endif /* chips */
  65921 
  65922 #if defined(BCM_88660_A0)
  65923     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88660_A0r */
  65924         soc_block_list[27],
  65925         soc_genreg,
  65926         1,
  65927         0,
  65928         0x10,
  65929         SOC_REG_FLAG_WO,
  65930         0,
  65931         3,
  65932         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88660_A0r_fields,
  65933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65934         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  65935         -1,
  65936         -1,
  65937     },
  65938 #endif /* chips */
  65939 
  65940 #if defined(BCM_88675_A0)
  65941     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88675_A0r */
  65942         soc_block_list[27],
  65943         soc_genreg,
  65944         1,
  65945         0,
  65946         0x10,
  65947         SOC_REG_FLAG_WO,
  65948         0,
  65949         4,
  65950         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88675_A0r_fields,
  65951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65952         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  65953         -1,
  65954         -1,
  65955     },
  65956 #endif /* chips */
  65957 
  65958 #if defined(BCM_88675_B0)
  65959     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88675_B0r */
  65960         soc_block_list[27],
  65961         soc_genreg,
  65962         1,
  65963         0,
  65964         0x10,
  65965         SOC_REG_FLAG_WO,
  65966         0,
  65967         4,
  65968         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88675_B0r_fields,
  65969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65970         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  65971         -1,
  65972         -1,
  65973     },
  65974 #endif /* chips */
  65975 
  65976 #if defined(BCM_88680_A0)
  65977     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88680_A0r */
  65978         soc_block_list[27],
  65979         soc_genreg,
  65980         1,
  65981         0,
  65982         0x10,
  65983         SOC_REG_FLAG_WO,
  65984         0,
  65985         4,
  65986         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88680_A0r_fields,
  65987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  65988         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  65989         -1,
  65990         -1,
  65991     },
  65992 #endif /* chips */
  65993 
  65994 #if defined(BCM_88690_A0)
  65995     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88690_A0r */
  65996         soc_block_list[27],
  65997         soc_genreg,
  65998         1,
  65999         0,
  66000         0x10,
  66001         SOC_REG_FLAG_WO,
  66002         0,
  66003         2,
  66004         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88690_A0r_fields,
  66005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66006         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66007         -1,
  66008         -1,
  66009     },
  66010 #endif /* chips */
  66011 
  66012 #if defined(BCM_88690_B0)
  66013     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  66014         soc_block_list[27],
  66015         soc_genreg,
  66016         1,
  66017         0,
  66018         0x10,
  66019         SOC_REG_FLAG_WO,
  66020         0,
  66021         2,
  66022         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  66023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66024         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66025         -1,
  66026         -1,
  66027     },
  66028 #endif /* chips */
  66029 
  66030 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  66031     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88750_A0r */
  66032         soc_block_list[27],
  66033         soc_genreg,
  66034         1,
  66035         0,
  66036         0x10,
  66037         SOC_REG_FLAG_WO,
  66038         0,
  66039         4,
  66040         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88750_A0r_fields,
  66041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66042         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66043         -1,
  66044         -1,
  66045     },
  66046 #endif /* chips */
  66047 
  66048 #if defined(BCM_88790_A0)
  66049     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88790_A0r */
  66050         soc_block_list[27],
  66051         soc_genreg,
  66052         1,
  66053         0,
  66054         0x10,
  66055         SOC_REG_FLAG_WO,
  66056         0,
  66057         2,
  66058         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88790_A0r_fields,
  66059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66060         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66061         -1,
  66062         -1,
  66063     },
  66064 #endif /* chips */
  66065 
  66066 #if defined(BCM_88950_A0)
  66067     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88950_A0r */
  66068         soc_block_list[27],
  66069         soc_genreg,
  66070         1,
  66071         0,
  66072         0x10,
  66073         SOC_REG_FLAG_WO,
  66074         0,
  66075         4,
  66076         soc_BRDC_FSRD_INTERRUPT_MASK_REGISTER_BCM88950_A0r_fields,
  66077         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66078         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66079         -1,
  66080         -1,
  66081     },
  66082 #endif /* chips */
  66083 
  66084 #if defined(BCM_88650_A0)
  66085     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTERr */
  66086         soc_block_list[27],
  66087         soc_genreg,
  66088         1,
  66089         0,
  66090         0,
  66091         SOC_REG_FLAG_WO |
  66092                           SOC_REG_FLAG_INTERRUPT,
  66093         0,
  66094         3,
  66095         soc_BRDC_FSRD_INTERRUPT_REGISTERr_fields,
  66096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66097         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66098         -1,
  66099         -1,
  66100     },
  66101 #endif /* chips */
  66102 
  66103 #if defined(BCM_88202_A0)
  66104     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88202_A0r */
  66105         soc_block_list[27],
  66106         soc_genreg,
  66107         1,
  66108         0,
  66109         0,
  66110         SOC_REG_FLAG_WO |
  66111                           SOC_REG_FLAG_INTERRUPT,
  66112         0,
  66113         3,
  66114         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88202_A0r_fields,
  66115         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66116         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66117         -1,
  66118         -1,
  66119     },
  66120 #endif /* chips */
  66121 
  66122 #if defined(BCM_88375_A0)
  66123     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88375_A0r */
  66124         soc_block_list[27],
  66125         soc_genreg,
  66126         1,
  66127         0,
  66128         0,
  66129         SOC_REG_FLAG_RO |
  66130                           SOC_REG_FLAG_WO |
  66131                           SOC_REG_FLAG_INTERRUPT,
  66132         0,
  66133         4,
  66134         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  66135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66136         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66137         -1,
  66138         -1,
  66139     },
  66140 #endif /* chips */
  66141 
  66142 #if defined(BCM_88375_B0)
  66143     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88375_B0r */
  66144         soc_block_list[27],
  66145         soc_genreg,
  66146         1,
  66147         0,
  66148         0,
  66149         SOC_REG_FLAG_RO |
  66150                           SOC_REG_FLAG_WO |
  66151                           SOC_REG_FLAG_INTERRUPT,
  66152         0,
  66153         4,
  66154         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  66155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66156         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66157         -1,
  66158         -1,
  66159     },
  66160 #endif /* chips */
  66161 
  66162 #if defined(BCM_88650_B0)
  66163     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88650_B0r */
  66164         soc_block_list[27],
  66165         soc_genreg,
  66166         1,
  66167         0,
  66168         0,
  66169         SOC_REG_FLAG_WO |
  66170                           SOC_REG_FLAG_INTERRUPT,
  66171         0,
  66172         3,
  66173         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88650_B0r_fields,
  66174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66175         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66176         -1,
  66177         -1,
  66178     },
  66179 #endif /* chips */
  66180 
  66181 #if defined(BCM_88660_A0)
  66182     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88660_A0r */
  66183         soc_block_list[27],
  66184         soc_genreg,
  66185         1,
  66186         0,
  66187         0,
  66188         SOC_REG_FLAG_WO |
  66189                           SOC_REG_FLAG_INTERRUPT,
  66190         0,
  66191         3,
  66192         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88660_A0r_fields,
  66193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66194         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66195         -1,
  66196         -1,
  66197     },
  66198 #endif /* chips */
  66199 
  66200 #if defined(BCM_88675_A0)
  66201     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88675_A0r */
  66202         soc_block_list[27],
  66203         soc_genreg,
  66204         1,
  66205         0,
  66206         0,
  66207         SOC_REG_FLAG_RO |
  66208                           SOC_REG_FLAG_WO |
  66209                           SOC_REG_FLAG_INTERRUPT,
  66210         0,
  66211         4,
  66212         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  66213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66214         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66215         -1,
  66216         -1,
  66217     },
  66218 #endif /* chips */
  66219 
  66220 #if defined(BCM_88675_B0)
  66221     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88675_B0r */
  66222         soc_block_list[27],
  66223         soc_genreg,
  66224         1,
  66225         0,
  66226         0,
  66227         SOC_REG_FLAG_RO |
  66228                           SOC_REG_FLAG_WO |
  66229                           SOC_REG_FLAG_INTERRUPT,
  66230         0,
  66231         4,
  66232         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  66233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66234         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66235         -1,
  66236         -1,
  66237     },
  66238 #endif /* chips */
  66239 
  66240 #if defined(BCM_88680_A0)
  66241     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88680_A0r */
  66242         soc_block_list[27],
  66243         soc_genreg,
  66244         1,
  66245         0,
  66246         0,
  66247         SOC_REG_FLAG_RO |
  66248                           SOC_REG_FLAG_WO |
  66249                           SOC_REG_FLAG_INTERRUPT,
  66250         0,
  66251         4,
  66252         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  66253         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66254         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66255         -1,
  66256         -1,
  66257     },
  66258 #endif /* chips */
  66259 
  66260 #if defined(BCM_88690_A0)
  66261     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88690_A0r */
  66262         soc_block_list[27],
  66263         soc_genreg,
  66264         1,
  66265         0,
  66266         0,
  66267         SOC_REG_FLAG_RO |
  66268                           SOC_REG_FLAG_WO |
  66269                           SOC_REG_FLAG_INTERRUPT |
  66270                           SOC_REG_FLAG_SIGNAL,
  66271         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  66272         2,
  66273         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  66274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66275         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66276         -1,
  66277         -1,
  66278     },
  66279 #endif /* chips */
  66280 
  66281 #if defined(BCM_88690_B0)
  66282     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88690_B0r */
  66283         soc_block_list[27],
  66284         soc_genreg,
  66285         1,
  66286         0,
  66287         0,
  66288         SOC_REG_FLAG_RO |
  66289                           SOC_REG_FLAG_WO |
  66290                           SOC_REG_FLAG_INTERRUPT |
  66291                           SOC_REG_FLAG_SIGNAL,
  66292         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  66293         2,
  66294         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  66295         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66296         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66297         -1,
  66298         -1,
  66299     },
  66300 #endif /* chips */
  66301 
  66302 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  66303     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88750_A0r */
  66304         soc_block_list[27],
  66305         soc_genreg,
  66306         1,
  66307         0,
  66308         0,
  66309         SOC_REG_FLAG_WO |
  66310                           SOC_REG_FLAG_INTERRUPT,
  66311         0,
  66312         4,
  66313         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88750_A0r_fields,
  66314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66315         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66316         -1,
  66317         -1,
  66318     },
  66319 #endif /* chips */
  66320 
  66321 #if defined(BCM_88790_A0)
  66322     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88790_A0r */
  66323         soc_block_list[27],
  66324         soc_genreg,
  66325         1,
  66326         0,
  66327         0,
  66328         SOC_REG_FLAG_RO |
  66329                           SOC_REG_FLAG_WO |
  66330                           SOC_REG_FLAG_INTERRUPT |
  66331                           SOC_REG_FLAG_SIGNAL,
  66332         0,
  66333         2,
  66334         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  66335         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66336         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66337         -1,
  66338         -1,
  66339     },
  66340 #endif /* chips */
  66341 
  66342 #if defined(BCM_88950_A0)
  66343     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_BCM88950_A0r */
  66344         soc_block_list[27],
  66345         soc_genreg,
  66346         1,
  66347         0,
  66348         0,
  66349         SOC_REG_FLAG_RO |
  66350                           SOC_REG_FLAG_WO |
  66351                           SOC_REG_FLAG_INTERRUPT,
  66352         0,
  66353         4,
  66354         soc_BRDC_FSRD_INTERRUPT_REGISTER_BCM88950_A0r_fields,
  66355         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66356         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  66357         -1,
  66358         -1,
  66359     },
  66360 #endif /* chips */
  66361 
  66362 #if defined(BCM_88650_A0)
  66363     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TESTr */
  66364         soc_block_list[27],
  66365         soc_genreg,
  66366         1,
  66367         0,
  66368         0x1a,
  66369         SOC_REG_FLAG_WO |
  66370                           SOC_REG_FLAG_INTERRUPT,
  66371         0,
  66372         1,
  66373         soc_BRDC_FSRD_INTERRUPT_REGISTER_TESTr_fields,
  66374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66375         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66376         -1,
  66377         -1,
  66378     },
  66379 #endif /* chips */
  66380 
  66381 #if defined(BCM_88202_A0)
  66382     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88202_A0r */
  66383         soc_block_list[27],
  66384         soc_genreg,
  66385         1,
  66386         0,
  66387         0x1a,
  66388         SOC_REG_FLAG_WO |
  66389                           SOC_REG_FLAG_INTERRUPT,
  66390         0,
  66391         1,
  66392         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88202_A0r_fields,
  66393         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66394         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66395         -1,
  66396         -1,
  66397     },
  66398 #endif /* chips */
  66399 
  66400 #if defined(BCM_88375_A0)
  66401     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  66402         soc_block_list[27],
  66403         soc_genreg,
  66404         1,
  66405         0,
  66406         0x18,
  66407         SOC_REG_FLAG_WO,
  66408         0,
  66409         1,
  66410         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  66411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66412         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66413         -1,
  66414         -1,
  66415     },
  66416 #endif /* chips */
  66417 
  66418 #if defined(BCM_88375_B0)
  66419     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  66420         soc_block_list[27],
  66421         soc_genreg,
  66422         1,
  66423         0,
  66424         0x18,
  66425         SOC_REG_FLAG_WO,
  66426         0,
  66427         1,
  66428         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  66429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66430         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66431         -1,
  66432         -1,
  66433     },
  66434 #endif /* chips */
  66435 
  66436 #if defined(BCM_88650_B0)
  66437     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88650_B0r */
  66438         soc_block_list[27],
  66439         soc_genreg,
  66440         1,
  66441         0,
  66442         0x1a,
  66443         SOC_REG_FLAG_WO |
  66444                           SOC_REG_FLAG_INTERRUPT,
  66445         0,
  66446         1,
  66447         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88650_B0r_fields,
  66448         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66449         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66450         -1,
  66451         -1,
  66452     },
  66453 #endif /* chips */
  66454 
  66455 #if defined(BCM_88660_A0)
  66456     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88660_A0r */
  66457         soc_block_list[27],
  66458         soc_genreg,
  66459         1,
  66460         0,
  66461         0x1a,
  66462         SOC_REG_FLAG_WO |
  66463                           SOC_REG_FLAG_INTERRUPT,
  66464         0,
  66465         1,
  66466         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88660_A0r_fields,
  66467         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66468         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  66469         -1,
  66470         -1,
  66471     },
  66472 #endif /* chips */
  66473 
  66474 #if defined(BCM_88675_A0)
  66475     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  66476         soc_block_list[27],
  66477         soc_genreg,
  66478         1,
  66479         0,
  66480         0x18,
  66481         SOC_REG_FLAG_WO,
  66482         0,
  66483         1,
  66484         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  66485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66487         -1,
  66488         -1,
  66489     },
  66490 #endif /* chips */
  66491 
  66492 #if defined(BCM_88675_B0)
  66493     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  66494         soc_block_list[27],
  66495         soc_genreg,
  66496         1,
  66497         0,
  66498         0x18,
  66499         SOC_REG_FLAG_WO,
  66500         0,
  66501         1,
  66502         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  66503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66504         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66505         -1,
  66506         -1,
  66507     },
  66508 #endif /* chips */
  66509 
  66510 #if defined(BCM_88680_A0)
  66511     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  66512         soc_block_list[27],
  66513         soc_genreg,
  66514         1,
  66515         0,
  66516         0x18,
  66517         SOC_REG_FLAG_WO,
  66518         0,
  66519         1,
  66520         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  66521         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66522         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66523         -1,
  66524         -1,
  66525     },
  66526 #endif /* chips */
  66527 
  66528 #if defined(BCM_88690_A0)
  66529     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  66530         soc_block_list[27],
  66531         soc_genreg,
  66532         1,
  66533         0,
  66534         0x18,
  66535         SOC_REG_FLAG_WO,
  66536         0,
  66537         1,
  66538         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  66539         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66540         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66541         -1,
  66542         -1,
  66543     },
  66544 #endif /* chips */
  66545 
  66546 #if defined(BCM_88690_B0)
  66547     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  66548         soc_block_list[27],
  66549         soc_genreg,
  66550         1,
  66551         0,
  66552         0x18,
  66553         SOC_REG_FLAG_WO,
  66554         0,
  66555         1,
  66556         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  66557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66558         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66559         -1,
  66560         -1,
  66561     },
  66562 #endif /* chips */
  66563 
  66564 #if defined(BCM_88790_A0)
  66565     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  66566         soc_block_list[27],
  66567         soc_genreg,
  66568         1,
  66569         0,
  66570         0x18,
  66571         SOC_REG_FLAG_WO,
  66572         0,
  66573         1,
  66574         soc_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88790_A0r_fields,
  66575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66576         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  66577         -1,
  66578         -1,
  66579     },
  66580 #endif /* chips */
  66581 
  66582 #if defined(BCM_88950_A0)
  66583     { /* SOC_REG_INT_BRDC_FSRD_INTERRUPT_REGISTER_TEST_BCM88950_A0r */
  66584         soc_block_list[27],
  66585         soc_genreg,
  66586         1,
  66587         0,
  66588         0x18,
  66589         SOC_REG_FLAG_WO,
  66590         0,
  66591         1,
  66592         soc_BRDC_CCS_INTERRUPT_REGISTER_TESTr_fields,
  66593         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66594         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66595         -1,
  66596         -1,
  66597     },
  66598 #endif /* chips */
  66599 
  66600 #if defined(BCM_88675_A0)
  66601     { /* SOC_REG_INT_BRDC_FSRD_OUTPUT_DROP_COUNTERr */
  66602         soc_block_list[27],
  66603         soc_genreg,
  66604         1,
  66605         0,
  66606         0x207,
  66607         SOC_REG_FLAG_RO |
  66608                           SOC_REG_FLAG_WO,
  66609         0,
  66610         2,
  66611         soc_BRDC_FSRD_OUTPUT_DROP_COUNTERr_fields,
  66612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66613         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66614         -1,
  66615         -1,
  66616     },
  66617 #endif /* chips */
  66618 
  66619 #if defined(BCM_88375_A0)
  66620     { /* SOC_REG_INT_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88375_A0r */
  66621         soc_block_list[27],
  66622         soc_genreg,
  66623         1,
  66624         0,
  66625         0x207,
  66626         SOC_REG_FLAG_RO |
  66627                           SOC_REG_FLAG_WO,
  66628         0,
  66629         2,
  66630         soc_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88375_A0r_fields,
  66631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66633         -1,
  66634         -1,
  66635     },
  66636 #endif /* chips */
  66637 
  66638 #if defined(BCM_88375_B0)
  66639     { /* SOC_REG_INT_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88375_B0r */
  66640         soc_block_list[27],
  66641         soc_genreg,
  66642         1,
  66643         0,
  66644         0x207,
  66645         SOC_REG_FLAG_RO |
  66646                           SOC_REG_FLAG_WO,
  66647         0,
  66648         2,
  66649         soc_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88375_B0r_fields,
  66650         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66651         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66652         -1,
  66653         -1,
  66654     },
  66655 #endif /* chips */
  66656 
  66657 #if defined(BCM_88675_B0)
  66658     { /* SOC_REG_INT_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88675_B0r */
  66659         soc_block_list[27],
  66660         soc_genreg,
  66661         1,
  66662         0,
  66663         0x207,
  66664         SOC_REG_FLAG_RO |
  66665                           SOC_REG_FLAG_WO,
  66666         0,
  66667         2,
  66668         soc_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88675_B0r_fields,
  66669         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66670         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66671         -1,
  66672         -1,
  66673     },
  66674 #endif /* chips */
  66675 
  66676 #if defined(BCM_88680_A0)
  66677     { /* SOC_REG_INT_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88680_A0r */
  66678         soc_block_list[27],
  66679         soc_genreg,
  66680         1,
  66681         0,
  66682         0x207,
  66683         SOC_REG_FLAG_RO |
  66684                           SOC_REG_FLAG_WO,
  66685         0,
  66686         2,
  66687         soc_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88680_A0r_fields,
  66688         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66690         -1,
  66691         -1,
  66692     },
  66693 #endif /* chips */
  66694 
  66695 #if defined(BCM_88950_A0)
  66696     { /* SOC_REG_INT_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88950_A0r */
  66697         soc_block_list[27],
  66698         soc_genreg,
  66699         1,
  66700         0,
  66701         0x207,
  66702         SOC_REG_FLAG_RO |
  66703                           SOC_REG_FLAG_WO,
  66704         0,
  66705         2,
  66706         soc_BRDC_FSRD_OUTPUT_DROP_COUNTER_BCM88950_A0r_fields,
  66707         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66708         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66709         -1,
  66710         -1,
  66711     },
  66712 #endif /* chips */
  66713 
  66714 #if defined(BCM_88790_A0)
  66715     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0r */
  66716         soc_block_list[27],
  66717         soc_genreg,
  66718         1,
  66719         0,
  66720         0xb0,
  66721         SOC_REG_FLAG_WO,
  66722         0,
  66723         1,
  66724         soc_BRDC_FSRD_PCMI_0r_fields,
  66725         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  66726         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66727         -1,
  66728         -1,
  66729     },
  66730 #endif /* chips */
  66731 
  66732 #if defined(BCM_88790_A0)
  66733     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1r */
  66734         soc_block_list[27],
  66735         soc_genreg,
  66736         1,
  66737         0,
  66738         0xb3,
  66739         SOC_REG_FLAG_WO,
  66740         0,
  66741         1,
  66742         soc_BRDC_FSRD_PCMI_1r_fields,
  66743         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  66744         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66745         -1,
  66746         -1,
  66747     },
  66748 #endif /* chips */
  66749 
  66750 #if defined(BCM_88790_A0)
  66751     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2r */
  66752         soc_block_list[27],
  66753         soc_genreg,
  66754         1,
  66755         0,
  66756         0xb6,
  66757         SOC_REG_FLAG_WO,
  66758         0,
  66759         1,
  66760         soc_BRDC_FSRD_PCMI_2r_fields,
  66761         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  66762         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66763         -1,
  66764         -1,
  66765     },
  66766 #endif /* chips */
  66767 
  66768 #if defined(BCM_88790_A0)
  66769     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3r */
  66770         soc_block_list[27],
  66771         soc_genreg,
  66772         1,
  66773         0,
  66774         0xb9,
  66775         SOC_REG_FLAG_WO,
  66776         0,
  66777         1,
  66778         soc_BRDC_FSRD_PCMI_3r_fields,
  66779         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  66780         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66781         -1,
  66782         -1,
  66783     },
  66784 #endif /* chips */
  66785 
  66786 #if defined(BCM_88690_B0)
  66787     { /* SOC_REG_INT_BRDC_FSRD_PCMI_4r */
  66788         soc_block_list[27],
  66789         soc_genreg,
  66790         1,
  66791         0,
  66792         0xbc,
  66793         SOC_REG_FLAG_WO,
  66794         0,
  66795         1,
  66796         soc_BRDC_FSRD_PCMI_4r_fields,
  66797         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  66798         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66799         -1,
  66800         -1,
  66801     },
  66802 #endif /* chips */
  66803 
  66804 #if defined(BCM_88690_A0)
  66805     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_BCM88690_A0r */
  66806         soc_block_list[27],
  66807         soc_genreg,
  66808         1,
  66809         0,
  66810         0xb0,
  66811         SOC_REG_FLAG_WO,
  66812         0,
  66813         1,
  66814         soc_BRDC_FSRD_PCMI_0_BCM88690_A0r_fields,
  66815         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  66816         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66817         -1,
  66818         -1,
  66819     },
  66820 #endif /* chips */
  66821 
  66822 #if defined(BCM_88690_B0)
  66823     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_BCM88690_B0r */
  66824         soc_block_list[27],
  66825         soc_genreg,
  66826         1,
  66827         0,
  66828         0xb0,
  66829         SOC_REG_FLAG_WO,
  66830         0,
  66831         1,
  66832         soc_BRDC_FSRD_PCMI_0_BCM88690_B0r_fields,
  66833         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  66834         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66835         -1,
  66836         -1,
  66837     },
  66838 #endif /* chips */
  66839 
  66840 #if defined(BCM_88790_A0)
  66841     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_Sr */
  66842         soc_block_list[27],
  66843         soc_genreg,
  66844         1,
  66845         0,
  66846         0xb1,
  66847         SOC_REG_FLAG_RO |
  66848                           SOC_REG_FLAG_WO,
  66849         0,
  66850         3,
  66851         soc_BRDC_FSRD_PCMI_0_Sr_fields,
  66852         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66853         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66854         -1,
  66855         -1,
  66856     },
  66857 #endif /* chips */
  66858 
  66859 #if defined(BCM_88690_A0)
  66860     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_S_BCM88690_A0r */
  66861         soc_block_list[27],
  66862         soc_genreg,
  66863         1,
  66864         0,
  66865         0xb1,
  66866         SOC_REG_FLAG_RO |
  66867                           SOC_REG_FLAG_WO,
  66868         0,
  66869         3,
  66870         soc_BRDC_FSRD_PCMI_0_S_BCM88690_A0r_fields,
  66871         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66872         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66873         -1,
  66874         -1,
  66875     },
  66876 #endif /* chips */
  66877 
  66878 #if defined(BCM_88690_B0)
  66879     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_S_BCM88690_B0r */
  66880         soc_block_list[27],
  66881         soc_genreg,
  66882         1,
  66883         0,
  66884         0xb1,
  66885         SOC_REG_FLAG_RO |
  66886                           SOC_REG_FLAG_WO,
  66887         0,
  66888         3,
  66889         soc_BRDC_FSRD_PCMI_0_S_BCM88690_B0r_fields,
  66890         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66891         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66892         -1,
  66893         -1,
  66894     },
  66895 #endif /* chips */
  66896 
  66897 #if defined(BCM_88790_A0)
  66898     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_Tr */
  66899         soc_block_list[27],
  66900         soc_genreg,
  66901         1,
  66902         0,
  66903         0xb2,
  66904         SOC_REG_FLAG_WO,
  66905         0,
  66906         2,
  66907         soc_BRDC_FSRD_PCMI_0_Tr_fields,
  66908         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66909         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66910         -1,
  66911         -1,
  66912     },
  66913 #endif /* chips */
  66914 
  66915 #if defined(BCM_88690_A0)
  66916     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_T_BCM88690_A0r */
  66917         soc_block_list[27],
  66918         soc_genreg,
  66919         1,
  66920         0,
  66921         0xb2,
  66922         SOC_REG_FLAG_WO,
  66923         0,
  66924         2,
  66925         soc_BRDC_FSRD_PCMI_0_T_BCM88690_A0r_fields,
  66926         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66927         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66928         -1,
  66929         -1,
  66930     },
  66931 #endif /* chips */
  66932 
  66933 #if defined(BCM_88690_B0)
  66934     { /* SOC_REG_INT_BRDC_FSRD_PCMI_0_T_BCM88690_B0r */
  66935         soc_block_list[27],
  66936         soc_genreg,
  66937         1,
  66938         0,
  66939         0xb2,
  66940         SOC_REG_FLAG_WO,
  66941         0,
  66942         2,
  66943         soc_BRDC_FSRD_PCMI_0_T_BCM88690_B0r_fields,
  66944         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  66945         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  66946         -1,
  66947         -1,
  66948     },
  66949 #endif /* chips */
  66950 
  66951 #if defined(BCM_88690_A0)
  66952     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_BCM88690_A0r */
  66953         soc_block_list[27],
  66954         soc_genreg,
  66955         1,
  66956         0,
  66957         0xb3,
  66958         SOC_REG_FLAG_WO,
  66959         0,
  66960         1,
  66961         soc_BRDC_FSRD_PCMI_1_BCM88690_A0r_fields,
  66962         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  66963         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66964         -1,
  66965         -1,
  66966     },
  66967 #endif /* chips */
  66968 
  66969 #if defined(BCM_88690_B0)
  66970     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_BCM88690_B0r */
  66971         soc_block_list[27],
  66972         soc_genreg,
  66973         1,
  66974         0,
  66975         0xb3,
  66976         SOC_REG_FLAG_WO,
  66977         0,
  66978         1,
  66979         soc_BRDC_FSRD_PCMI_1_BCM88690_B0r_fields,
  66980         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  66981         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  66982         -1,
  66983         -1,
  66984     },
  66985 #endif /* chips */
  66986 
  66987 #if defined(BCM_88790_A0)
  66988     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_Sr */
  66989         soc_block_list[27],
  66990         soc_genreg,
  66991         1,
  66992         0,
  66993         0xb4,
  66994         SOC_REG_FLAG_RO |
  66995                           SOC_REG_FLAG_WO,
  66996         0,
  66997         3,
  66998         soc_BRDC_FSRD_PCMI_1_Sr_fields,
  66999         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67000         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67001         -1,
  67002         -1,
  67003     },
  67004 #endif /* chips */
  67005 
  67006 #if defined(BCM_88690_A0)
  67007     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_S_BCM88690_A0r */
  67008         soc_block_list[27],
  67009         soc_genreg,
  67010         1,
  67011         0,
  67012         0xb4,
  67013         SOC_REG_FLAG_RO |
  67014                           SOC_REG_FLAG_WO,
  67015         0,
  67016         3,
  67017         soc_BRDC_FSRD_PCMI_1_S_BCM88690_A0r_fields,
  67018         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67019         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67020         -1,
  67021         -1,
  67022     },
  67023 #endif /* chips */
  67024 
  67025 #if defined(BCM_88690_B0)
  67026     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_S_BCM88690_B0r */
  67027         soc_block_list[27],
  67028         soc_genreg,
  67029         1,
  67030         0,
  67031         0xb4,
  67032         SOC_REG_FLAG_RO |
  67033                           SOC_REG_FLAG_WO,
  67034         0,
  67035         3,
  67036         soc_BRDC_FSRD_PCMI_1_S_BCM88690_B0r_fields,
  67037         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67038         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67039         -1,
  67040         -1,
  67041     },
  67042 #endif /* chips */
  67043 
  67044 #if defined(BCM_88790_A0)
  67045     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_Tr */
  67046         soc_block_list[27],
  67047         soc_genreg,
  67048         1,
  67049         0,
  67050         0xb5,
  67051         SOC_REG_FLAG_WO,
  67052         0,
  67053         2,
  67054         soc_BRDC_FSRD_PCMI_1_Tr_fields,
  67055         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67056         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67057         -1,
  67058         -1,
  67059     },
  67060 #endif /* chips */
  67061 
  67062 #if defined(BCM_88690_A0)
  67063     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_T_BCM88690_A0r */
  67064         soc_block_list[27],
  67065         soc_genreg,
  67066         1,
  67067         0,
  67068         0xb5,
  67069         SOC_REG_FLAG_WO,
  67070         0,
  67071         2,
  67072         soc_BRDC_FSRD_PCMI_1_T_BCM88690_A0r_fields,
  67073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67074         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67075         -1,
  67076         -1,
  67077     },
  67078 #endif /* chips */
  67079 
  67080 #if defined(BCM_88690_B0)
  67081     { /* SOC_REG_INT_BRDC_FSRD_PCMI_1_T_BCM88690_B0r */
  67082         soc_block_list[27],
  67083         soc_genreg,
  67084         1,
  67085         0,
  67086         0xb5,
  67087         SOC_REG_FLAG_WO,
  67088         0,
  67089         2,
  67090         soc_BRDC_FSRD_PCMI_1_T_BCM88690_B0r_fields,
  67091         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67092         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67093         -1,
  67094         -1,
  67095     },
  67096 #endif /* chips */
  67097 
  67098 #if defined(BCM_88690_A0)
  67099     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_BCM88690_A0r */
  67100         soc_block_list[27],
  67101         soc_genreg,
  67102         1,
  67103         0,
  67104         0xb6,
  67105         SOC_REG_FLAG_WO,
  67106         0,
  67107         1,
  67108         soc_BRDC_FSRD_PCMI_2_BCM88690_A0r_fields,
  67109         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  67110         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67111         -1,
  67112         -1,
  67113     },
  67114 #endif /* chips */
  67115 
  67116 #if defined(BCM_88690_B0)
  67117     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_BCM88690_B0r */
  67118         soc_block_list[27],
  67119         soc_genreg,
  67120         1,
  67121         0,
  67122         0xb6,
  67123         SOC_REG_FLAG_WO,
  67124         0,
  67125         1,
  67126         soc_BRDC_FSRD_PCMI_2_BCM88690_B0r_fields,
  67127         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  67128         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67129         -1,
  67130         -1,
  67131     },
  67132 #endif /* chips */
  67133 
  67134 #if defined(BCM_88790_A0)
  67135     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_Sr */
  67136         soc_block_list[27],
  67137         soc_genreg,
  67138         1,
  67139         0,
  67140         0xb7,
  67141         SOC_REG_FLAG_RO |
  67142                           SOC_REG_FLAG_WO,
  67143         0,
  67144         3,
  67145         soc_BRDC_FSRD_PCMI_2_Sr_fields,
  67146         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67147         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67148         -1,
  67149         -1,
  67150     },
  67151 #endif /* chips */
  67152 
  67153 #if defined(BCM_88690_A0)
  67154     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_S_BCM88690_A0r */
  67155         soc_block_list[27],
  67156         soc_genreg,
  67157         1,
  67158         0,
  67159         0xb7,
  67160         SOC_REG_FLAG_RO |
  67161                           SOC_REG_FLAG_WO,
  67162         0,
  67163         3,
  67164         soc_BRDC_FSRD_PCMI_2_S_BCM88690_A0r_fields,
  67165         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67166         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67167         -1,
  67168         -1,
  67169     },
  67170 #endif /* chips */
  67171 
  67172 #if defined(BCM_88690_B0)
  67173     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_S_BCM88690_B0r */
  67174         soc_block_list[27],
  67175         soc_genreg,
  67176         1,
  67177         0,
  67178         0xb7,
  67179         SOC_REG_FLAG_RO |
  67180                           SOC_REG_FLAG_WO,
  67181         0,
  67182         3,
  67183         soc_BRDC_FSRD_PCMI_2_S_BCM88690_B0r_fields,
  67184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67186         -1,
  67187         -1,
  67188     },
  67189 #endif /* chips */
  67190 
  67191 #if defined(BCM_88790_A0)
  67192     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_Tr */
  67193         soc_block_list[27],
  67194         soc_genreg,
  67195         1,
  67196         0,
  67197         0xb8,
  67198         SOC_REG_FLAG_WO,
  67199         0,
  67200         2,
  67201         soc_BRDC_FSRD_PCMI_2_Tr_fields,
  67202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67203         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67204         -1,
  67205         -1,
  67206     },
  67207 #endif /* chips */
  67208 
  67209 #if defined(BCM_88690_A0)
  67210     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_T_BCM88690_A0r */
  67211         soc_block_list[27],
  67212         soc_genreg,
  67213         1,
  67214         0,
  67215         0xb8,
  67216         SOC_REG_FLAG_WO,
  67217         0,
  67218         2,
  67219         soc_BRDC_FSRD_PCMI_2_T_BCM88690_A0r_fields,
  67220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67221         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67222         -1,
  67223         -1,
  67224     },
  67225 #endif /* chips */
  67226 
  67227 #if defined(BCM_88690_B0)
  67228     { /* SOC_REG_INT_BRDC_FSRD_PCMI_2_T_BCM88690_B0r */
  67229         soc_block_list[27],
  67230         soc_genreg,
  67231         1,
  67232         0,
  67233         0xb8,
  67234         SOC_REG_FLAG_WO,
  67235         0,
  67236         2,
  67237         soc_BRDC_FSRD_PCMI_2_T_BCM88690_B0r_fields,
  67238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67239         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67240         -1,
  67241         -1,
  67242     },
  67243 #endif /* chips */
  67244 
  67245 #if defined(BCM_88690_A0)
  67246     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_BCM88690_A0r */
  67247         soc_block_list[27],
  67248         soc_genreg,
  67249         1,
  67250         0,
  67251         0xb9,
  67252         SOC_REG_FLAG_WO,
  67253         0,
  67254         1,
  67255         soc_BRDC_FSRD_PCMI_3_BCM88690_A0r_fields,
  67256         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  67257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67258         -1,
  67259         -1,
  67260     },
  67261 #endif /* chips */
  67262 
  67263 #if defined(BCM_88690_B0)
  67264     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_BCM88690_B0r */
  67265         soc_block_list[27],
  67266         soc_genreg,
  67267         1,
  67268         0,
  67269         0xb9,
  67270         SOC_REG_FLAG_WO,
  67271         0,
  67272         1,
  67273         soc_BRDC_FSRD_PCMI_3_BCM88690_B0r_fields,
  67274         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  67275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67276         -1,
  67277         -1,
  67278     },
  67279 #endif /* chips */
  67280 
  67281 #if defined(BCM_88790_A0)
  67282     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_Sr */
  67283         soc_block_list[27],
  67284         soc_genreg,
  67285         1,
  67286         0,
  67287         0xba,
  67288         SOC_REG_FLAG_RO |
  67289                           SOC_REG_FLAG_WO,
  67290         0,
  67291         3,
  67292         soc_BRDC_FSRD_PCMI_3_Sr_fields,
  67293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67295         -1,
  67296         -1,
  67297     },
  67298 #endif /* chips */
  67299 
  67300 #if defined(BCM_88690_A0)
  67301     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_S_BCM88690_A0r */
  67302         soc_block_list[27],
  67303         soc_genreg,
  67304         1,
  67305         0,
  67306         0xba,
  67307         SOC_REG_FLAG_RO |
  67308                           SOC_REG_FLAG_WO,
  67309         0,
  67310         3,
  67311         soc_BRDC_FSRD_PCMI_3_S_BCM88690_A0r_fields,
  67312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67314         -1,
  67315         -1,
  67316     },
  67317 #endif /* chips */
  67318 
  67319 #if defined(BCM_88690_B0)
  67320     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_S_BCM88690_B0r */
  67321         soc_block_list[27],
  67322         soc_genreg,
  67323         1,
  67324         0,
  67325         0xba,
  67326         SOC_REG_FLAG_RO |
  67327                           SOC_REG_FLAG_WO,
  67328         0,
  67329         3,
  67330         soc_BRDC_FSRD_PCMI_3_S_BCM88690_B0r_fields,
  67331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67333         -1,
  67334         -1,
  67335     },
  67336 #endif /* chips */
  67337 
  67338 #if defined(BCM_88790_A0)
  67339     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_Tr */
  67340         soc_block_list[27],
  67341         soc_genreg,
  67342         1,
  67343         0,
  67344         0xbb,
  67345         SOC_REG_FLAG_WO,
  67346         0,
  67347         2,
  67348         soc_BRDC_FSRD_PCMI_3_Tr_fields,
  67349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67350         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67351         -1,
  67352         -1,
  67353     },
  67354 #endif /* chips */
  67355 
  67356 #if defined(BCM_88690_A0)
  67357     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_T_BCM88690_A0r */
  67358         soc_block_list[27],
  67359         soc_genreg,
  67360         1,
  67361         0,
  67362         0xbb,
  67363         SOC_REG_FLAG_WO,
  67364         0,
  67365         2,
  67366         soc_BRDC_FSRD_PCMI_3_T_BCM88690_A0r_fields,
  67367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67368         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67369         -1,
  67370         -1,
  67371     },
  67372 #endif /* chips */
  67373 
  67374 #if defined(BCM_88690_B0)
  67375     { /* SOC_REG_INT_BRDC_FSRD_PCMI_3_T_BCM88690_B0r */
  67376         soc_block_list[27],
  67377         soc_genreg,
  67378         1,
  67379         0,
  67380         0xbb,
  67381         SOC_REG_FLAG_WO,
  67382         0,
  67383         2,
  67384         soc_BRDC_FSRD_PCMI_3_T_BCM88690_B0r_fields,
  67385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67386         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67387         -1,
  67388         -1,
  67389     },
  67390 #endif /* chips */
  67391 
  67392 #if defined(BCM_88690_B0)
  67393     { /* SOC_REG_INT_BRDC_FSRD_PCMI_4_Sr */
  67394         soc_block_list[27],
  67395         soc_genreg,
  67396         1,
  67397         0,
  67398         0xbd,
  67399         SOC_REG_FLAG_RO |
  67400                           SOC_REG_FLAG_WO,
  67401         0,
  67402         3,
  67403         soc_BRDC_FSRD_PCMI_4_Sr_fields,
  67404         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  67406         -1,
  67407         -1,
  67408     },
  67409 #endif /* chips */
  67410 
  67411 #if defined(BCM_88690_B0)
  67412     { /* SOC_REG_INT_BRDC_FSRD_PCMI_4_Tr */
  67413         soc_block_list[27],
  67414         soc_genreg,
  67415         1,
  67416         0,
  67417         0xbe,
  67418         SOC_REG_FLAG_WO,
  67419         0,
  67420         2,
  67421         soc_BRDC_FSRD_PCMI_4_Tr_fields,
  67422         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67423         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  67424         -1,
  67425         -1,
  67426     },
  67427 #endif /* chips */
  67428 
  67429 #if defined(BCM_88650_A0)
  67430     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTERr */
  67431         soc_block_list[27],
  67432         soc_genreg,
  67433         3,
  67434         0,
  67435         0x11,
  67436         SOC_REG_FLAG_ARRAY |
  67437                           SOC_REG_FLAG_WO |
  67438                           SOC_REG_FLAG_REG_ARRAY |
  67439                           SOC_REG_FLAG_INTERRUPT,
  67440         0,
  67441         3,
  67442         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTERr_fields,
  67443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67444         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67445         -1,
  67446         -1,
  67447     },
  67448 #endif /* chips */
  67449 
  67450 #if defined(BCM_88202_A0)
  67451     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88202_A0r */
  67452         soc_block_list[27],
  67453         soc_genreg,
  67454         3,
  67455         0,
  67456         0x11,
  67457         SOC_REG_FLAG_ARRAY |
  67458                           SOC_REG_FLAG_WO |
  67459                           SOC_REG_FLAG_REG_ARRAY |
  67460                           SOC_REG_FLAG_INTERRUPT,
  67461         0,
  67462         4,
  67463         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88202_A0r_fields,
  67464         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67465         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67466         -1,
  67467         -1,
  67468     },
  67469 #endif /* chips */
  67470 
  67471 #if defined(BCM_88375_A0)
  67472     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88375_A0r */
  67473         soc_block_list[27],
  67474         soc_genreg,
  67475         3,
  67476         0,
  67477         0x110,
  67478         SOC_REG_FLAG_ARRAY |
  67479                           SOC_REG_FLAG_WO |
  67480                           SOC_REG_FLAG_REG_ARRAY,
  67481         0,
  67482         4,
  67483         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88375_A0r_fields,
  67484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67485         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67486         -1,
  67487         -1,
  67488     },
  67489 #endif /* chips */
  67490 
  67491 #if defined(BCM_88375_B0)
  67492     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88375_B0r */
  67493         soc_block_list[27],
  67494         soc_genreg,
  67495         3,
  67496         0,
  67497         0x110,
  67498         SOC_REG_FLAG_ARRAY |
  67499                           SOC_REG_FLAG_WO |
  67500                           SOC_REG_FLAG_REG_ARRAY,
  67501         0,
  67502         4,
  67503         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88375_B0r_fields,
  67504         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67505         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67506         -1,
  67507         -1,
  67508     },
  67509 #endif /* chips */
  67510 
  67511 #if defined(BCM_88650_B0)
  67512     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88650_B0r */
  67513         soc_block_list[27],
  67514         soc_genreg,
  67515         3,
  67516         0,
  67517         0x11,
  67518         SOC_REG_FLAG_ARRAY |
  67519                           SOC_REG_FLAG_WO |
  67520                           SOC_REG_FLAG_REG_ARRAY |
  67521                           SOC_REG_FLAG_INTERRUPT,
  67522         0,
  67523         3,
  67524         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88650_B0r_fields,
  67525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67526         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67527         -1,
  67528         -1,
  67529     },
  67530 #endif /* chips */
  67531 
  67532 #if defined(BCM_88660_A0)
  67533     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88660_A0r */
  67534         soc_block_list[27],
  67535         soc_genreg,
  67536         3,
  67537         0,
  67538         0x11,
  67539         SOC_REG_FLAG_ARRAY |
  67540                           SOC_REG_FLAG_WO |
  67541                           SOC_REG_FLAG_REG_ARRAY |
  67542                           SOC_REG_FLAG_INTERRUPT,
  67543         0,
  67544         3,
  67545         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88660_A0r_fields,
  67546         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67547         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67548         -1,
  67549         -1,
  67550     },
  67551 #endif /* chips */
  67552 
  67553 #if defined(BCM_88675_A0)
  67554     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88675_A0r */
  67555         soc_block_list[27],
  67556         soc_genreg,
  67557         3,
  67558         0,
  67559         0x110,
  67560         SOC_REG_FLAG_ARRAY |
  67561                           SOC_REG_FLAG_WO |
  67562                           SOC_REG_FLAG_REG_ARRAY,
  67563         0,
  67564         4,
  67565         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88675_A0r_fields,
  67566         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67567         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67568         -1,
  67569         -1,
  67570     },
  67571 #endif /* chips */
  67572 
  67573 #if defined(BCM_88675_B0)
  67574     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88675_B0r */
  67575         soc_block_list[27],
  67576         soc_genreg,
  67577         3,
  67578         0,
  67579         0x110,
  67580         SOC_REG_FLAG_ARRAY |
  67581                           SOC_REG_FLAG_WO |
  67582                           SOC_REG_FLAG_REG_ARRAY,
  67583         0,
  67584         4,
  67585         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88675_B0r_fields,
  67586         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67587         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67588         -1,
  67589         -1,
  67590     },
  67591 #endif /* chips */
  67592 
  67593 #if defined(BCM_88680_A0)
  67594     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88680_A0r */
  67595         soc_block_list[27],
  67596         soc_genreg,
  67597         3,
  67598         0,
  67599         0x110,
  67600         SOC_REG_FLAG_ARRAY |
  67601                           SOC_REG_FLAG_WO |
  67602                           SOC_REG_FLAG_REG_ARRAY,
  67603         0,
  67604         4,
  67605         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88680_A0r_fields,
  67606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67607         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67608         -1,
  67609         -1,
  67610     },
  67611 #endif /* chips */
  67612 
  67613 #if defined(BCM_88690_A0)
  67614     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88690_A0r */
  67615         soc_block_list[27],
  67616         soc_genreg,
  67617         1,
  67618         0,
  67619         0x101,
  67620         SOC_REG_FLAG_WO,
  67621         0,
  67622         5,
  67623         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88690_A0r_fields,
  67624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67625         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67626         -1,
  67627         -1,
  67628     },
  67629 #endif /* chips */
  67630 
  67631 #if defined(BCM_88690_B0)
  67632     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  67633         soc_block_list[27],
  67634         soc_genreg,
  67635         1,
  67636         0,
  67637         0x101,
  67638         SOC_REG_FLAG_WO,
  67639         0,
  67640         5,
  67641         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  67642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67643         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67644         -1,
  67645         -1,
  67646     },
  67647 #endif /* chips */
  67648 
  67649 #if defined(BCM_88750_A0)
  67650     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88750_A0r */
  67651         soc_block_list[27],
  67652         soc_genreg,
  67653         4,
  67654         0,
  67655         0x11,
  67656         SOC_REG_FLAG_ARRAY |
  67657                           SOC_REG_FLAG_WO |
  67658                           SOC_REG_FLAG_REG_ARRAY,
  67659         0,
  67660         3,
  67661         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88750_A0r_fields,
  67662         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67663         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67664         -1,
  67665         -1,
  67666     },
  67667 #endif /* chips */
  67668 
  67669 #if defined(BCM_88750_B0)
  67670     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88750_B0r */
  67671         soc_block_list[27],
  67672         soc_genreg,
  67673         4,
  67674         0,
  67675         0x11,
  67676         SOC_REG_FLAG_ARRAY |
  67677                           SOC_REG_FLAG_WO |
  67678                           SOC_REG_FLAG_REG_ARRAY,
  67679         0,
  67680         3,
  67681         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88750_B0r_fields,
  67682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67683         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67684         -1,
  67685         -1,
  67686     },
  67687 #endif /* chips */
  67688 
  67689 #if defined(BCM_88790_A0)
  67690     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88790_A0r */
  67691         soc_block_list[27],
  67692         soc_genreg,
  67693         1,
  67694         0,
  67695         0x101,
  67696         SOC_REG_FLAG_WO,
  67697         0,
  67698         5,
  67699         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88790_A0r_fields,
  67700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67701         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67702         -1,
  67703         -1,
  67704     },
  67705 #endif /* chips */
  67706 
  67707 #if defined(BCM_88950_A0)
  67708     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88950_A0r */
  67709         soc_block_list[27],
  67710         soc_genreg,
  67711         3,
  67712         0,
  67713         0x110,
  67714         SOC_REG_FLAG_ARRAY |
  67715                           SOC_REG_FLAG_WO |
  67716                           SOC_REG_FLAG_REG_ARRAY,
  67717         0,
  67718         4,
  67719         soc_BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER_BCM88950_A0r_fields,
  67720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67721         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67722         -1,
  67723         -1,
  67724     },
  67725 #endif /* chips */
  67726 
  67727 #if defined(BCM_88650_A0)
  67728     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTERr */
  67729         soc_block_list[27],
  67730         soc_genreg,
  67731         3,
  67732         0,
  67733         0x1,
  67734         SOC_REG_FLAG_ARRAY |
  67735                           SOC_REG_FLAG_WO |
  67736                           SOC_REG_FLAG_REG_ARRAY |
  67737                           SOC_REG_FLAG_INTERRUPT,
  67738         0,
  67739         3,
  67740         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTERr_fields,
  67741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67742         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67743         -1,
  67744         -1,
  67745     },
  67746 #endif /* chips */
  67747 
  67748 #if defined(BCM_88202_A0)
  67749     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88202_A0r */
  67750         soc_block_list[27],
  67751         soc_genreg,
  67752         3,
  67753         0,
  67754         0x1,
  67755         SOC_REG_FLAG_ARRAY |
  67756                           SOC_REG_FLAG_WO |
  67757                           SOC_REG_FLAG_REG_ARRAY |
  67758                           SOC_REG_FLAG_INTERRUPT,
  67759         0,
  67760         4,
  67761         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88202_A0r_fields,
  67762         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67763         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67764         -1,
  67765         -1,
  67766     },
  67767 #endif /* chips */
  67768 
  67769 #if defined(BCM_88375_A0)
  67770     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88375_A0r */
  67771         soc_block_list[27],
  67772         soc_genreg,
  67773         3,
  67774         0,
  67775         0x100,
  67776         SOC_REG_FLAG_ARRAY |
  67777                           SOC_REG_FLAG_WO |
  67778                           SOC_REG_FLAG_REG_ARRAY |
  67779                           SOC_REG_FLAG_INTERRUPT,
  67780         0,
  67781         4,
  67782         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88375_A0r_fields,
  67783         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67784         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67785         -1,
  67786         -1,
  67787     },
  67788 #endif /* chips */
  67789 
  67790 #if defined(BCM_88375_B0)
  67791     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88375_B0r */
  67792         soc_block_list[27],
  67793         soc_genreg,
  67794         3,
  67795         0,
  67796         0x100,
  67797         SOC_REG_FLAG_ARRAY |
  67798                           SOC_REG_FLAG_WO |
  67799                           SOC_REG_FLAG_REG_ARRAY |
  67800                           SOC_REG_FLAG_INTERRUPT,
  67801         0,
  67802         4,
  67803         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88375_B0r_fields,
  67804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67805         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67806         -1,
  67807         -1,
  67808     },
  67809 #endif /* chips */
  67810 
  67811 #if defined(BCM_88650_B0)
  67812     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88650_B0r */
  67813         soc_block_list[27],
  67814         soc_genreg,
  67815         3,
  67816         0,
  67817         0x1,
  67818         SOC_REG_FLAG_ARRAY |
  67819                           SOC_REG_FLAG_WO |
  67820                           SOC_REG_FLAG_REG_ARRAY |
  67821                           SOC_REG_FLAG_INTERRUPT,
  67822         0,
  67823         3,
  67824         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88650_B0r_fields,
  67825         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67826         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67827         -1,
  67828         -1,
  67829     },
  67830 #endif /* chips */
  67831 
  67832 #if defined(BCM_88660_A0)
  67833     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88660_A0r */
  67834         soc_block_list[27],
  67835         soc_genreg,
  67836         3,
  67837         0,
  67838         0x1,
  67839         SOC_REG_FLAG_ARRAY |
  67840                           SOC_REG_FLAG_WO |
  67841                           SOC_REG_FLAG_REG_ARRAY |
  67842                           SOC_REG_FLAG_INTERRUPT,
  67843         0,
  67844         3,
  67845         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88660_A0r_fields,
  67846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67847         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67848         -1,
  67849         -1,
  67850     },
  67851 #endif /* chips */
  67852 
  67853 #if defined(BCM_88675_A0)
  67854     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88675_A0r */
  67855         soc_block_list[27],
  67856         soc_genreg,
  67857         3,
  67858         0,
  67859         0x100,
  67860         SOC_REG_FLAG_ARRAY |
  67861                           SOC_REG_FLAG_WO |
  67862                           SOC_REG_FLAG_REG_ARRAY |
  67863                           SOC_REG_FLAG_INTERRUPT,
  67864         0,
  67865         4,
  67866         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88675_A0r_fields,
  67867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67868         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67869         -1,
  67870         -1,
  67871     },
  67872 #endif /* chips */
  67873 
  67874 #if defined(BCM_88675_B0)
  67875     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88675_B0r */
  67876         soc_block_list[27],
  67877         soc_genreg,
  67878         3,
  67879         0,
  67880         0x100,
  67881         SOC_REG_FLAG_ARRAY |
  67882                           SOC_REG_FLAG_WO |
  67883                           SOC_REG_FLAG_REG_ARRAY |
  67884                           SOC_REG_FLAG_INTERRUPT,
  67885         0,
  67886         4,
  67887         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88675_B0r_fields,
  67888         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67889         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67890         -1,
  67891         -1,
  67892     },
  67893 #endif /* chips */
  67894 
  67895 #if defined(BCM_88680_A0)
  67896     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88680_A0r */
  67897         soc_block_list[27],
  67898         soc_genreg,
  67899         3,
  67900         0,
  67901         0x100,
  67902         SOC_REG_FLAG_ARRAY |
  67903                           SOC_REG_FLAG_WO |
  67904                           SOC_REG_FLAG_REG_ARRAY |
  67905                           SOC_REG_FLAG_INTERRUPT,
  67906         0,
  67907         4,
  67908         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88680_A0r_fields,
  67909         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67910         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  67911         -1,
  67912         -1,
  67913     },
  67914 #endif /* chips */
  67915 
  67916 #if defined(BCM_88690_A0)
  67917     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88690_A0r */
  67918         soc_block_list[27],
  67919         soc_genreg,
  67920         1,
  67921         0,
  67922         0x100,
  67923         SOC_REG_FLAG_WO |
  67924                           SOC_REG_FLAG_INTERRUPT |
  67925                           SOC_REG_FLAG_SIGNAL,
  67926         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  67927         5,
  67928         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88690_A0r_fields,
  67929         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67930         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67931         -1,
  67932         -1,
  67933     },
  67934 #endif /* chips */
  67935 
  67936 #if defined(BCM_88690_B0)
  67937     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88690_B0r */
  67938         soc_block_list[27],
  67939         soc_genreg,
  67940         1,
  67941         0,
  67942         0x100,
  67943         SOC_REG_FLAG_WO |
  67944                           SOC_REG_FLAG_INTERRUPT |
  67945                           SOC_REG_FLAG_SIGNAL,
  67946         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  67947         5,
  67948         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  67949         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67950         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67951         -1,
  67952         -1,
  67953     },
  67954 #endif /* chips */
  67955 
  67956 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  67957     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88750_A0r */
  67958         soc_block_list[27],
  67959         soc_genreg,
  67960         4,
  67961         0,
  67962         0x1,
  67963         SOC_REG_FLAG_ARRAY |
  67964                           SOC_REG_FLAG_WO |
  67965                           SOC_REG_FLAG_REG_ARRAY |
  67966                           SOC_REG_FLAG_INTERRUPT,
  67967         0,
  67968         3,
  67969         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88750_A0r_fields,
  67970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67971         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  67972         -1,
  67973         -1,
  67974     },
  67975 #endif /* chips */
  67976 
  67977 #if defined(BCM_88790_A0)
  67978     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88790_A0r */
  67979         soc_block_list[27],
  67980         soc_genreg,
  67981         1,
  67982         0,
  67983         0x100,
  67984         SOC_REG_FLAG_WO |
  67985                           SOC_REG_FLAG_INTERRUPT |
  67986                           SOC_REG_FLAG_SIGNAL,
  67987         0,
  67988         5,
  67989         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88790_A0r_fields,
  67990         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  67991         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  67992         -1,
  67993         -1,
  67994     },
  67995 #endif /* chips */
  67996 
  67997 #if defined(BCM_88950_A0)
  67998     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88950_A0r */
  67999         soc_block_list[27],
  68000         soc_genreg,
  68001         3,
  68002         0,
  68003         0x100,
  68004         SOC_REG_FLAG_ARRAY |
  68005                           SOC_REG_FLAG_WO |
  68006                           SOC_REG_FLAG_REG_ARRAY |
  68007                           SOC_REG_FLAG_INTERRUPT,
  68008         0,
  68009         4,
  68010         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_BCM88950_A0r_fields,
  68011         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68012         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  68013         -1,
  68014         -1,
  68015     },
  68016 #endif /* chips */
  68017 
  68018 #if defined(BCM_88650_A0)
  68019     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TESTr */
  68020         soc_block_list[27],
  68021         soc_genreg,
  68022         3,
  68023         0,
  68024         0x1b,
  68025         SOC_REG_FLAG_ARRAY |
  68026                           SOC_REG_FLAG_WO |
  68027                           SOC_REG_FLAG_REG_ARRAY |
  68028                           SOC_REG_FLAG_INTERRUPT,
  68029         0,
  68030         1,
  68031         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TESTr_fields,
  68032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68033         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68034         -1,
  68035         -1,
  68036     },
  68037 #endif /* chips */
  68038 
  68039 #if defined(BCM_88202_A0)
  68040     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88202_A0r */
  68041         soc_block_list[27],
  68042         soc_genreg,
  68043         3,
  68044         0,
  68045         0x1b,
  68046         SOC_REG_FLAG_ARRAY |
  68047                           SOC_REG_FLAG_WO |
  68048                           SOC_REG_FLAG_REG_ARRAY |
  68049                           SOC_REG_FLAG_INTERRUPT,
  68050         0,
  68051         1,
  68052         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88202_A0r_fields,
  68053         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68054         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68055         -1,
  68056         -1,
  68057     },
  68058 #endif /* chips */
  68059 
  68060 #if defined(BCM_88375_A0)
  68061     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88375_A0r */
  68062         soc_block_list[27],
  68063         soc_genreg,
  68064         3,
  68065         0,
  68066         0x120,
  68067         SOC_REG_FLAG_ARRAY |
  68068                           SOC_REG_FLAG_WO |
  68069                           SOC_REG_FLAG_REG_ARRAY,
  68070         0,
  68071         1,
  68072         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88375_A0r_fields,
  68073         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68074         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68075         -1,
  68076         -1,
  68077     },
  68078 #endif /* chips */
  68079 
  68080 #if defined(BCM_88375_B0)
  68081     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88375_B0r */
  68082         soc_block_list[27],
  68083         soc_genreg,
  68084         3,
  68085         0,
  68086         0x120,
  68087         SOC_REG_FLAG_ARRAY |
  68088                           SOC_REG_FLAG_WO |
  68089                           SOC_REG_FLAG_REG_ARRAY,
  68090         0,
  68091         1,
  68092         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88375_B0r_fields,
  68093         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68094         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68095         -1,
  68096         -1,
  68097     },
  68098 #endif /* chips */
  68099 
  68100 #if defined(BCM_88650_B0)
  68101     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88650_B0r */
  68102         soc_block_list[27],
  68103         soc_genreg,
  68104         3,
  68105         0,
  68106         0x1b,
  68107         SOC_REG_FLAG_ARRAY |
  68108                           SOC_REG_FLAG_WO |
  68109                           SOC_REG_FLAG_REG_ARRAY |
  68110                           SOC_REG_FLAG_INTERRUPT,
  68111         0,
  68112         1,
  68113         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88650_B0r_fields,
  68114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68115         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68116         -1,
  68117         -1,
  68118     },
  68119 #endif /* chips */
  68120 
  68121 #if defined(BCM_88660_A0)
  68122     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88660_A0r */
  68123         soc_block_list[27],
  68124         soc_genreg,
  68125         3,
  68126         0,
  68127         0x1b,
  68128         SOC_REG_FLAG_ARRAY |
  68129                           SOC_REG_FLAG_WO |
  68130                           SOC_REG_FLAG_REG_ARRAY |
  68131                           SOC_REG_FLAG_INTERRUPT,
  68132         0,
  68133         1,
  68134         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88660_A0r_fields,
  68135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68136         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68137         -1,
  68138         -1,
  68139     },
  68140 #endif /* chips */
  68141 
  68142 #if defined(BCM_88675_A0)
  68143     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88675_A0r */
  68144         soc_block_list[27],
  68145         soc_genreg,
  68146         3,
  68147         0,
  68148         0x120,
  68149         SOC_REG_FLAG_ARRAY |
  68150                           SOC_REG_FLAG_WO |
  68151                           SOC_REG_FLAG_REG_ARRAY,
  68152         0,
  68153         1,
  68154         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88675_A0r_fields,
  68155         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68156         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68157         -1,
  68158         -1,
  68159     },
  68160 #endif /* chips */
  68161 
  68162 #if defined(BCM_88675_B0)
  68163     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88675_B0r */
  68164         soc_block_list[27],
  68165         soc_genreg,
  68166         3,
  68167         0,
  68168         0x120,
  68169         SOC_REG_FLAG_ARRAY |
  68170                           SOC_REG_FLAG_WO |
  68171                           SOC_REG_FLAG_REG_ARRAY,
  68172         0,
  68173         1,
  68174         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88675_B0r_fields,
  68175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68177         -1,
  68178         -1,
  68179     },
  68180 #endif /* chips */
  68181 
  68182 #if defined(BCM_88680_A0)
  68183     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88680_A0r */
  68184         soc_block_list[27],
  68185         soc_genreg,
  68186         3,
  68187         0,
  68188         0x120,
  68189         SOC_REG_FLAG_ARRAY |
  68190                           SOC_REG_FLAG_WO |
  68191                           SOC_REG_FLAG_REG_ARRAY,
  68192         0,
  68193         1,
  68194         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88680_A0r_fields,
  68195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68196         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68197         -1,
  68198         -1,
  68199     },
  68200 #endif /* chips */
  68201 
  68202 #if defined(BCM_88690_A0)
  68203     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88690_A0r */
  68204         soc_block_list[27],
  68205         soc_genreg,
  68206         1,
  68207         0,
  68208         0x102,
  68209         SOC_REG_FLAG_WO,
  68210         0,
  68211         1,
  68212         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88690_A0r_fields,
  68213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68214         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  68215         -1,
  68216         -1,
  68217     },
  68218 #endif /* chips */
  68219 
  68220 #if defined(BCM_88690_B0)
  68221     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  68222         soc_block_list[27],
  68223         soc_genreg,
  68224         1,
  68225         0,
  68226         0x102,
  68227         SOC_REG_FLAG_WO,
  68228         0,
  68229         1,
  68230         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  68231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68232         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  68233         -1,
  68234         -1,
  68235     },
  68236 #endif /* chips */
  68237 
  68238 #if defined(BCM_88790_A0)
  68239     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88790_A0r */
  68240         soc_block_list[27],
  68241         soc_genreg,
  68242         1,
  68243         0,
  68244         0x102,
  68245         SOC_REG_FLAG_WO,
  68246         0,
  68247         1,
  68248         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88790_A0r_fields,
  68249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68250         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  68251         -1,
  68252         -1,
  68253     },
  68254 #endif /* chips */
  68255 
  68256 #if defined(BCM_88950_A0)
  68257     { /* SOC_REG_INT_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88950_A0r */
  68258         soc_block_list[27],
  68259         soc_genreg,
  68260         3,
  68261         0,
  68262         0x120,
  68263         SOC_REG_FLAG_ARRAY |
  68264                           SOC_REG_FLAG_WO |
  68265                           SOC_REG_FLAG_REG_ARRAY,
  68266         0,
  68267         1,
  68268         soc_BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST_BCM88950_A0r_fields,
  68269         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68270         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68271         -1,
  68272         -1,
  68273     },
  68274 #endif /* chips */
  68275 
  68276 #if defined(BCM_88690_B0)
  68277     { /* SOC_REG_INT_BRDC_FSRD_REG_0041r */
  68278         soc_block_list[27],
  68279         soc_genreg,
  68280         1,
  68281         0,
  68282         0x41,
  68283         SOC_REG_FLAG_WO,
  68284         0,
  68285         1,
  68286         soc_BRDC_FSRD_REG_0041r_fields,
  68287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68288         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68289         -1,
  68290         -1,
  68291     },
  68292 #endif /* chips */
  68293 
  68294 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  68295     { /* SOC_REG_INT_BRDC_FSRD_REG_0050r */
  68296         soc_block_list[27],
  68297         soc_genreg,
  68298         1,
  68299         0,
  68300         0x50,
  68301         SOC_REG_FLAG_WO,
  68302         0,
  68303         1,
  68304         soc_ECI_REG_0050r_fields,
  68305         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68306         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68307         -1,
  68308         -1,
  68309     },
  68310 #endif /* chips */
  68311 
  68312 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  68313     { /* SOC_REG_INT_BRDC_FSRD_REG_0051r */
  68314         soc_block_list[27],
  68315         soc_genreg,
  68316         1,
  68317         0,
  68318         0x51,
  68319         SOC_REG_FLAG_WO,
  68320         0,
  68321         1,
  68322         soc_ECI_REG_0051r_fields,
  68323         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68324         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68325         -1,
  68326         -1,
  68327     },
  68328 #endif /* chips */
  68329 
  68330 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  68331     { /* SOC_REG_INT_BRDC_FSRD_REG_0052r */
  68332         soc_block_list[27],
  68333         soc_genreg,
  68334         1,
  68335         0,
  68336         0x52,
  68337         SOC_REG_FLAG_WO,
  68338         0,
  68339         1,
  68340         soc_ECI_REG_0052r_fields,
  68341         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68342         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68343         -1,
  68344         -1,
  68345     },
  68346 #endif /* chips */
  68347 
  68348 #if defined(BCM_88750_B0)
  68349     { /* SOC_REG_INT_BRDC_FSRD_REG_0053r */
  68350         soc_block_list[27],
  68351         soc_genreg,
  68352         1,
  68353         0,
  68354         0x53,
  68355         SOC_REG_FLAG_WO,
  68356         0,
  68357         1,
  68358         soc_ECI_REG_0053r_fields,
  68359         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68360         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68361         -1,
  68362         -1,
  68363     },
  68364 #endif /* chips */
  68365 
  68366 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  68367     { /* SOC_REG_INT_BRDC_FSRD_REG_0054r */
  68368         soc_block_list[27],
  68369         soc_genreg,
  68370         1,
  68371         0,
  68372         0x54,
  68373         SOC_REG_FLAG_WO,
  68374         0,
  68375         2,
  68376         soc_DRCBROADCAST_REG_0085_BCM83207_A0r_fields,
  68377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68378         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  68379         -1,
  68380         -1,
  68381     },
  68382 #endif /* chips */
  68383 
  68384 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  68385     { /* SOC_REG_INT_BRDC_FSRD_REG_0058r */
  68386         soc_block_list[27],
  68387         soc_genreg,
  68388         1,
  68389         0,
  68390         0x58,
  68391         SOC_REG_FLAG_WO,
  68392         0,
  68393         1,
  68394         soc_BRDC_FSRD_REG_0058r_fields,
  68395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68396         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68397         -1,
  68398         -1,
  68399     },
  68400 #endif /* chips */
  68401 
  68402 #if defined(BCM_88650_A0)
  68403     { /* SOC_REG_INT_BRDC_FSRD_REG_0084r */
  68404         soc_block_list[27],
  68405         soc_genreg,
  68406         1,
  68407         0,
  68408         0x84,
  68409         SOC_REG_FLAG_WO,
  68410         0,
  68411         2,
  68412         soc_BRDC_FSRD_REG_0084r_fields,
  68413         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68414         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  68415         -1,
  68416         -1,
  68417     },
  68418 #endif /* chips */
  68419 
  68420 #if defined(BCM_88650_A0)
  68421     { /* SOC_REG_INT_BRDC_FSRD_REG_0087r */
  68422         soc_block_list[27],
  68423         soc_genreg,
  68424         1,
  68425         0,
  68426         0x87,
  68427         SOC_REG_FLAG_WO,
  68428         0,
  68429         1,
  68430         soc_BRDC_FSRD_REG_0087r_fields,
  68431         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68432         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68433         -1,
  68434         -1,
  68435     },
  68436 #endif /* chips */
  68437 
  68438 #if defined(BCM_88650_A0)
  68439     { /* SOC_REG_INT_BRDC_FSRD_REG_0090r */
  68440         soc_block_list[27],
  68441         soc_genreg,
  68442         1,
  68443         0,
  68444         0x90,
  68445         SOC_REG_FLAG_WO,
  68446         0,
  68447         1,
  68448         soc_BRDC_FSRD_REG_0090r_fields,
  68449         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68450         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68451         -1,
  68452         -1,
  68453     },
  68454 #endif /* chips */
  68455 
  68456 #if defined(BCM_88650_A0)
  68457     { /* SOC_REG_INT_BRDC_FSRD_REG_0091r */
  68458         soc_block_list[27],
  68459         soc_genreg,
  68460         1,
  68461         0,
  68462         0x91,
  68463         SOC_REG_FLAG_WO,
  68464         0,
  68465         1,
  68466         soc_BRDC_FSRD_REG_0091r_fields,
  68467         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68468         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68469         -1,
  68470         -1,
  68471     },
  68472 #endif /* chips */
  68473 
  68474 #if defined(BCM_88650_A0)
  68475     { /* SOC_REG_INT_BRDC_FSRD_REG_0092r */
  68476         soc_block_list[27],
  68477         soc_genreg,
  68478         1,
  68479         0,
  68480         0x92,
  68481         SOC_REG_FLAG_WO,
  68482         0,
  68483         1,
  68484         soc_BRDC_FSRD_REG_0092r_fields,
  68485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68486         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68487         -1,
  68488         -1,
  68489     },
  68490 #endif /* chips */
  68491 
  68492 #if defined(BCM_88690_B0)
  68493     { /* SOC_REG_INT_BRDC_FSRD_REG_0094r */
  68494         soc_block_list[27],
  68495         soc_genreg,
  68496         1,
  68497         0,
  68498         0x94,
  68499         SOC_REG_FLAG_64_BITS |
  68500                           SOC_REG_FLAG_RO |
  68501                           SOC_REG_FLAG_WO,
  68502         SOC_REG_FLAG_COUNTER_FEILDS |
  68503                           SOC_REG_FLAG_INIT_ON_READ,
  68504         4,
  68505         soc_BRDC_FSRD_REG_0094r_fields,
  68506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68507         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  68508         -1,
  68509         -1,
  68510     },
  68511 #endif /* chips */
  68512 
  68513 #if defined(BCM_88650_A0)
  68514     { /* SOC_REG_INT_BRDC_FSRD_REG_0170r */
  68515         soc_block_list[27],
  68516         soc_genreg,
  68517         3,
  68518         0,
  68519         0x170,
  68520         SOC_REG_FLAG_ARRAY |
  68521                           SOC_REG_FLAG_WO |
  68522                           SOC_REG_FLAG_REG_ARRAY,
  68523         0,
  68524         1,
  68525         soc_BRDC_FSRD_REG_0170r_fields,
  68526         SOC_RESET_VAL_DEC(0x00408102, 0x00000000)
  68527         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  68528         -1,
  68529         -1,
  68530     },
  68531 #endif /* chips */
  68532 
  68533 #if defined(BCM_88202_A0)
  68534     { /* SOC_REG_INT_BRDC_FSRD_REG_0084_BCM88202_A0r */
  68535         soc_block_list[27],
  68536         soc_genreg,
  68537         1,
  68538         0,
  68539         0x84,
  68540         SOC_REG_FLAG_WO,
  68541         0,
  68542         2,
  68543         soc_BRDC_FSRD_REG_0084_BCM88202_A0r_fields,
  68544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68545         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  68546         -1,
  68547         -1,
  68548     },
  68549 #endif /* chips */
  68550 
  68551 #if defined(BCM_88650_B0)
  68552     { /* SOC_REG_INT_BRDC_FSRD_REG_0084_BCM88650_B0r */
  68553         soc_block_list[27],
  68554         soc_genreg,
  68555         1,
  68556         0,
  68557         0x84,
  68558         SOC_REG_FLAG_WO,
  68559         0,
  68560         2,
  68561         soc_BRDC_FSRD_REG_0084_BCM88650_B0r_fields,
  68562         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68563         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  68564         -1,
  68565         -1,
  68566     },
  68567 #endif /* chips */
  68568 
  68569 #if defined(BCM_88660_A0)
  68570     { /* SOC_REG_INT_BRDC_FSRD_REG_0084_BCM88660_A0r */
  68571         soc_block_list[27],
  68572         soc_genreg,
  68573         1,
  68574         0,
  68575         0x84,
  68576         SOC_REG_FLAG_WO,
  68577         0,
  68578         2,
  68579         soc_BRDC_FSRD_REG_0084_BCM88660_A0r_fields,
  68580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68581         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  68582         -1,
  68583         -1,
  68584     },
  68585 #endif /* chips */
  68586 
  68587 #if defined(BCM_88202_A0)
  68588     { /* SOC_REG_INT_BRDC_FSRD_REG_0087_BCM88202_A0r */
  68589         soc_block_list[27],
  68590         soc_genreg,
  68591         1,
  68592         0,
  68593         0x87,
  68594         SOC_REG_FLAG_WO,
  68595         0,
  68596         1,
  68597         soc_BRDC_FSRD_REG_0087_BCM88202_A0r_fields,
  68598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68599         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68600         -1,
  68601         -1,
  68602     },
  68603 #endif /* chips */
  68604 
  68605 #if defined(BCM_88650_B0)
  68606     { /* SOC_REG_INT_BRDC_FSRD_REG_0087_BCM88650_B0r */
  68607         soc_block_list[27],
  68608         soc_genreg,
  68609         1,
  68610         0,
  68611         0x87,
  68612         SOC_REG_FLAG_WO,
  68613         0,
  68614         1,
  68615         soc_BRDC_FSRD_REG_0087_BCM88650_B0r_fields,
  68616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68617         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68618         -1,
  68619         -1,
  68620     },
  68621 #endif /* chips */
  68622 
  68623 #if defined(BCM_88660_A0)
  68624     { /* SOC_REG_INT_BRDC_FSRD_REG_0087_BCM88660_A0r */
  68625         soc_block_list[27],
  68626         soc_genreg,
  68627         1,
  68628         0,
  68629         0x87,
  68630         SOC_REG_FLAG_WO,
  68631         0,
  68632         1,
  68633         soc_BRDC_FSRD_REG_0087_BCM88660_A0r_fields,
  68634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68635         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68636         -1,
  68637         -1,
  68638     },
  68639 #endif /* chips */
  68640 
  68641 #if defined(BCM_88202_A0)
  68642     { /* SOC_REG_INT_BRDC_FSRD_REG_0090_BCM88202_A0r */
  68643         soc_block_list[27],
  68644         soc_genreg,
  68645         1,
  68646         0,
  68647         0x90,
  68648         SOC_REG_FLAG_WO,
  68649         0,
  68650         1,
  68651         soc_BRDC_FSRD_REG_0090_BCM88202_A0r_fields,
  68652         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68654         -1,
  68655         -1,
  68656     },
  68657 #endif /* chips */
  68658 
  68659 #if defined(BCM_88650_B0)
  68660     { /* SOC_REG_INT_BRDC_FSRD_REG_0090_BCM88650_B0r */
  68661         soc_block_list[27],
  68662         soc_genreg,
  68663         1,
  68664         0,
  68665         0x90,
  68666         SOC_REG_FLAG_WO,
  68667         0,
  68668         1,
  68669         soc_BRDC_FSRD_REG_0090_BCM88650_B0r_fields,
  68670         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68671         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68672         -1,
  68673         -1,
  68674     },
  68675 #endif /* chips */
  68676 
  68677 #if defined(BCM_88660_A0)
  68678     { /* SOC_REG_INT_BRDC_FSRD_REG_0090_BCM88660_A0r */
  68679         soc_block_list[27],
  68680         soc_genreg,
  68681         1,
  68682         0,
  68683         0x90,
  68684         SOC_REG_FLAG_WO,
  68685         0,
  68686         1,
  68687         soc_BRDC_FSRD_REG_0090_BCM88660_A0r_fields,
  68688         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68689         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68690         -1,
  68691         -1,
  68692     },
  68693 #endif /* chips */
  68694 
  68695 #if defined(BCM_88202_A0)
  68696     { /* SOC_REG_INT_BRDC_FSRD_REG_0091_BCM88202_A0r */
  68697         soc_block_list[27],
  68698         soc_genreg,
  68699         1,
  68700         0,
  68701         0x91,
  68702         SOC_REG_FLAG_WO,
  68703         0,
  68704         1,
  68705         soc_BRDC_FSRD_REG_0091_BCM88202_A0r_fields,
  68706         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68707         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68708         -1,
  68709         -1,
  68710     },
  68711 #endif /* chips */
  68712 
  68713 #if defined(BCM_88650_B0)
  68714     { /* SOC_REG_INT_BRDC_FSRD_REG_0091_BCM88650_B0r */
  68715         soc_block_list[27],
  68716         soc_genreg,
  68717         1,
  68718         0,
  68719         0x91,
  68720         SOC_REG_FLAG_WO,
  68721         0,
  68722         1,
  68723         soc_BRDC_FSRD_REG_0091_BCM88650_B0r_fields,
  68724         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68725         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68726         -1,
  68727         -1,
  68728     },
  68729 #endif /* chips */
  68730 
  68731 #if defined(BCM_88660_A0)
  68732     { /* SOC_REG_INT_BRDC_FSRD_REG_0091_BCM88660_A0r */
  68733         soc_block_list[27],
  68734         soc_genreg,
  68735         1,
  68736         0,
  68737         0x91,
  68738         SOC_REG_FLAG_WO,
  68739         0,
  68740         1,
  68741         soc_BRDC_FSRD_REG_0091_BCM88660_A0r_fields,
  68742         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  68743         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68744         -1,
  68745         -1,
  68746     },
  68747 #endif /* chips */
  68748 
  68749 #if defined(BCM_88202_A0)
  68750     { /* SOC_REG_INT_BRDC_FSRD_REG_0092_BCM88202_A0r */
  68751         soc_block_list[27],
  68752         soc_genreg,
  68753         1,
  68754         0,
  68755         0x92,
  68756         SOC_REG_FLAG_WO,
  68757         0,
  68758         1,
  68759         soc_BRDC_FSRD_REG_0092_BCM88202_A0r_fields,
  68760         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68761         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68762         -1,
  68763         -1,
  68764     },
  68765 #endif /* chips */
  68766 
  68767 #if defined(BCM_88650_B0)
  68768     { /* SOC_REG_INT_BRDC_FSRD_REG_0092_BCM88650_B0r */
  68769         soc_block_list[27],
  68770         soc_genreg,
  68771         1,
  68772         0,
  68773         0x92,
  68774         SOC_REG_FLAG_WO,
  68775         0,
  68776         1,
  68777         soc_BRDC_FSRD_REG_0092_BCM88650_B0r_fields,
  68778         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68779         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68780         -1,
  68781         -1,
  68782     },
  68783 #endif /* chips */
  68784 
  68785 #if defined(BCM_88660_A0)
  68786     { /* SOC_REG_INT_BRDC_FSRD_REG_0092_BCM88660_A0r */
  68787         soc_block_list[27],
  68788         soc_genreg,
  68789         1,
  68790         0,
  68791         0x92,
  68792         SOC_REG_FLAG_WO,
  68793         0,
  68794         1,
  68795         soc_BRDC_FSRD_REG_0092_BCM88660_A0r_fields,
  68796         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68797         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68798         -1,
  68799         -1,
  68800     },
  68801 #endif /* chips */
  68802 
  68803 #if defined(BCM_88690_B0)
  68804     { /* SOC_REG_INT_BRDC_FSRD_REG_009Ar */
  68805         soc_block_list[27],
  68806         soc_genreg,
  68807         1,
  68808         0,
  68809         0x9a,
  68810         SOC_REG_FLAG_WO,
  68811         0,
  68812         1,
  68813         soc_BRDC_FSRD_REG_009Ar_fields,
  68814         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68815         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68816         -1,
  68817         -1,
  68818     },
  68819 #endif /* chips */
  68820 
  68821 #if defined(BCM_88690_B0)
  68822     { /* SOC_REG_INT_BRDC_FSRD_REG_009Cr */
  68823         soc_block_list[27],
  68824         soc_genreg,
  68825         1,
  68826         0,
  68827         0x9c,
  68828         SOC_REG_FLAG_WO,
  68829         0,
  68830         1,
  68831         soc_BRDC_FSRD_REG_009Cr_fields,
  68832         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68833         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68834         -1,
  68835         -1,
  68836     },
  68837 #endif /* chips */
  68838 
  68839 #if defined(BCM_88650_A0)
  68840     { /* SOC_REG_INT_BRDC_FSRD_REG_00B0r */
  68841         soc_block_list[27],
  68842         soc_genreg,
  68843         1,
  68844         0,
  68845         0xb0,
  68846         SOC_REG_FLAG_WO,
  68847         0,
  68848         1,
  68849         soc_BRDC_FSRD_REG_00B0r_fields,
  68850         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  68851         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68852         -1,
  68853         -1,
  68854     },
  68855 #endif /* chips */
  68856 
  68857 #if defined(BCM_88650_A0)
  68858     { /* SOC_REG_INT_BRDC_FSRD_REG_00B1r */
  68859         soc_block_list[27],
  68860         soc_genreg,
  68861         1,
  68862         0,
  68863         0xb1,
  68864         SOC_REG_FLAG_WO,
  68865         0,
  68866         3,
  68867         soc_BRDC_FSRD_REG_00B1r_fields,
  68868         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68869         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68870         -1,
  68871         -1,
  68872     },
  68873 #endif /* chips */
  68874 
  68875 #if defined(BCM_88650_A0)
  68876     { /* SOC_REG_INT_BRDC_FSRD_REG_00B2r */
  68877         soc_block_list[27],
  68878         soc_genreg,
  68879         1,
  68880         0,
  68881         0xb2,
  68882         SOC_REG_FLAG_WO,
  68883         0,
  68884         1,
  68885         soc_BRDC_FSRD_REG_00B2r_fields,
  68886         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68887         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  68888         -1,
  68889         -1,
  68890     },
  68891 #endif /* chips */
  68892 
  68893 #if defined(BCM_88650_A0)
  68894     { /* SOC_REG_INT_BRDC_FSRD_REG_00B3r */
  68895         soc_block_list[27],
  68896         soc_genreg,
  68897         1,
  68898         0,
  68899         0xb3,
  68900         SOC_REG_FLAG_WO,
  68901         0,
  68902         1,
  68903         soc_BRDC_FSRD_REG_00B3r_fields,
  68904         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68905         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68906         -1,
  68907         -1,
  68908     },
  68909 #endif /* chips */
  68910 
  68911 #if defined(BCM_88650_A0)
  68912     { /* SOC_REG_INT_BRDC_FSRD_REG_00B4r */
  68913         soc_block_list[27],
  68914         soc_genreg,
  68915         1,
  68916         0,
  68917         0xb4,
  68918         SOC_REG_FLAG_WO,
  68919         0,
  68920         1,
  68921         soc_BRDC_FSRD_REG_00B4r_fields,
  68922         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  68923         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68924         -1,
  68925         -1,
  68926     },
  68927 #endif /* chips */
  68928 
  68929 #if defined(BCM_88650_A0)
  68930     { /* SOC_REG_INT_BRDC_FSRD_REG_00B5r */
  68931         soc_block_list[27],
  68932         soc_genreg,
  68933         1,
  68934         0,
  68935         0xb5,
  68936         SOC_REG_FLAG_WO,
  68937         0,
  68938         3,
  68939         soc_BRDC_FSRD_REG_00B5r_fields,
  68940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68941         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68942         -1,
  68943         -1,
  68944     },
  68945 #endif /* chips */
  68946 
  68947 #if defined(BCM_88650_A0)
  68948     { /* SOC_REG_INT_BRDC_FSRD_REG_00B6r */
  68949         soc_block_list[27],
  68950         soc_genreg,
  68951         1,
  68952         0,
  68953         0xb6,
  68954         SOC_REG_FLAG_WO,
  68955         0,
  68956         1,
  68957         soc_BRDC_FSRD_REG_00B6r_fields,
  68958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68959         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  68960         -1,
  68961         -1,
  68962     },
  68963 #endif /* chips */
  68964 
  68965 #if defined(BCM_88650_A0)
  68966     { /* SOC_REG_INT_BRDC_FSRD_REG_00B7r */
  68967         soc_block_list[27],
  68968         soc_genreg,
  68969         1,
  68970         0,
  68971         0xb7,
  68972         SOC_REG_FLAG_WO,
  68973         0,
  68974         1,
  68975         soc_BRDC_FSRD_REG_00B7r_fields,
  68976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  68977         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  68978         -1,
  68979         -1,
  68980     },
  68981 #endif /* chips */
  68982 
  68983 #if defined(BCM_88202_A0)
  68984     { /* SOC_REG_INT_BRDC_FSRD_REG_00B0_BCM88202_A0r */
  68985         soc_block_list[27],
  68986         soc_genreg,
  68987         1,
  68988         0,
  68989         0xb0,
  68990         SOC_REG_FLAG_WO,
  68991         0,
  68992         1,
  68993         soc_BRDC_FSRD_REG_00B0_BCM88202_A0r_fields,
  68994         SOC_RESET_VAL_DEC(0x1ad27480, 0x00000000)
  68995         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  68996         -1,
  68997         -1,
  68998     },
  68999 #endif /* chips */
  69000 
  69001 #if defined(BCM_88650_B0)
  69002     { /* SOC_REG_INT_BRDC_FSRD_REG_00B0_BCM88650_B0r */
  69003         soc_block_list[27],
  69004         soc_genreg,
  69005         1,
  69006         0,
  69007         0xb0,
  69008         SOC_REG_FLAG_WO,
  69009         0,
  69010         1,
  69011         soc_BRDC_FSRD_REG_00B0_BCM88650_B0r_fields,
  69012         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  69013         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69014         -1,
  69015         -1,
  69016     },
  69017 #endif /* chips */
  69018 
  69019 #if defined(BCM_88660_A0)
  69020     { /* SOC_REG_INT_BRDC_FSRD_REG_00B0_BCM88660_A0r */
  69021         soc_block_list[27],
  69022         soc_genreg,
  69023         1,
  69024         0,
  69025         0xb0,
  69026         SOC_REG_FLAG_WO,
  69027         0,
  69028         1,
  69029         soc_BRDC_FSRD_REG_00B0_BCM88660_A0r_fields,
  69030         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  69031         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69032         -1,
  69033         -1,
  69034     },
  69035 #endif /* chips */
  69036 
  69037 #if defined(BCM_88202_A0)
  69038     { /* SOC_REG_INT_BRDC_FSRD_REG_00B1_BCM88202_A0r */
  69039         soc_block_list[27],
  69040         soc_genreg,
  69041         1,
  69042         0,
  69043         0xb1,
  69044         SOC_REG_FLAG_WO,
  69045         0,
  69046         3,
  69047         soc_BRDC_FSRD_REG_00B1_BCM88202_A0r_fields,
  69048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69049         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69050         -1,
  69051         -1,
  69052     },
  69053 #endif /* chips */
  69054 
  69055 #if defined(BCM_88650_B0)
  69056     { /* SOC_REG_INT_BRDC_FSRD_REG_00B1_BCM88650_B0r */
  69057         soc_block_list[27],
  69058         soc_genreg,
  69059         1,
  69060         0,
  69061         0xb1,
  69062         SOC_REG_FLAG_WO,
  69063         0,
  69064         3,
  69065         soc_BRDC_FSRD_REG_00B1_BCM88650_B0r_fields,
  69066         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69067         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69068         -1,
  69069         -1,
  69070     },
  69071 #endif /* chips */
  69072 
  69073 #if defined(BCM_88660_A0)
  69074     { /* SOC_REG_INT_BRDC_FSRD_REG_00B1_BCM88660_A0r */
  69075         soc_block_list[27],
  69076         soc_genreg,
  69077         1,
  69078         0,
  69079         0xb1,
  69080         SOC_REG_FLAG_WO,
  69081         0,
  69082         3,
  69083         soc_BRDC_FSRD_REG_00B1_BCM88660_A0r_fields,
  69084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69086         -1,
  69087         -1,
  69088     },
  69089 #endif /* chips */
  69090 
  69091 #if defined(BCM_88202_A0)
  69092     { /* SOC_REG_INT_BRDC_FSRD_REG_00B2_BCM88202_A0r */
  69093         soc_block_list[27],
  69094         soc_genreg,
  69095         1,
  69096         0,
  69097         0xb2,
  69098         SOC_REG_FLAG_WO,
  69099         0,
  69100         1,
  69101         soc_BRDC_FSRD_REG_00B2_BCM88202_A0r_fields,
  69102         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69103         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69104         -1,
  69105         -1,
  69106     },
  69107 #endif /* chips */
  69108 
  69109 #if defined(BCM_88650_B0)
  69110     { /* SOC_REG_INT_BRDC_FSRD_REG_00B2_BCM88650_B0r */
  69111         soc_block_list[27],
  69112         soc_genreg,
  69113         1,
  69114         0,
  69115         0xb2,
  69116         SOC_REG_FLAG_WO,
  69117         0,
  69118         1,
  69119         soc_BRDC_FSRD_REG_00B2_BCM88650_B0r_fields,
  69120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69121         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69122         -1,
  69123         -1,
  69124     },
  69125 #endif /* chips */
  69126 
  69127 #if defined(BCM_88660_A0)
  69128     { /* SOC_REG_INT_BRDC_FSRD_REG_00B2_BCM88660_A0r */
  69129         soc_block_list[27],
  69130         soc_genreg,
  69131         1,
  69132         0,
  69133         0xb2,
  69134         SOC_REG_FLAG_WO,
  69135         0,
  69136         1,
  69137         soc_BRDC_FSRD_REG_00B2_BCM88660_A0r_fields,
  69138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69139         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69140         -1,
  69141         -1,
  69142     },
  69143 #endif /* chips */
  69144 
  69145 #if defined(BCM_88202_A0)
  69146     { /* SOC_REG_INT_BRDC_FSRD_REG_00B3_BCM88202_A0r */
  69147         soc_block_list[27],
  69148         soc_genreg,
  69149         1,
  69150         0,
  69151         0xb3,
  69152         SOC_REG_FLAG_WO,
  69153         0,
  69154         1,
  69155         soc_BRDC_FSRD_REG_00B3_BCM88202_A0r_fields,
  69156         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69157         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69158         -1,
  69159         -1,
  69160     },
  69161 #endif /* chips */
  69162 
  69163 #if defined(BCM_88650_B0)
  69164     { /* SOC_REG_INT_BRDC_FSRD_REG_00B3_BCM88650_B0r */
  69165         soc_block_list[27],
  69166         soc_genreg,
  69167         1,
  69168         0,
  69169         0xb3,
  69170         SOC_REG_FLAG_WO,
  69171         0,
  69172         1,
  69173         soc_BRDC_FSRD_REG_00B3_BCM88650_B0r_fields,
  69174         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69175         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69176         -1,
  69177         -1,
  69178     },
  69179 #endif /* chips */
  69180 
  69181 #if defined(BCM_88660_A0)
  69182     { /* SOC_REG_INT_BRDC_FSRD_REG_00B3_BCM88660_A0r */
  69183         soc_block_list[27],
  69184         soc_genreg,
  69185         1,
  69186         0,
  69187         0xb3,
  69188         SOC_REG_FLAG_WO,
  69189         0,
  69190         1,
  69191         soc_BRDC_FSRD_REG_00B3_BCM88660_A0r_fields,
  69192         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69193         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69194         -1,
  69195         -1,
  69196     },
  69197 #endif /* chips */
  69198 
  69199 #if defined(BCM_88202_A0)
  69200     { /* SOC_REG_INT_BRDC_FSRD_REG_00B4_BCM88202_A0r */
  69201         soc_block_list[27],
  69202         soc_genreg,
  69203         1,
  69204         0,
  69205         0xb4,
  69206         SOC_REG_FLAG_WO,
  69207         0,
  69208         1,
  69209         soc_BRDC_FSRD_REG_00B4_BCM88202_A0r_fields,
  69210         SOC_RESET_VAL_DEC(0x1ad27480, 0x00000000)
  69211         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69212         -1,
  69213         -1,
  69214     },
  69215 #endif /* chips */
  69216 
  69217 #if defined(BCM_88650_B0)
  69218     { /* SOC_REG_INT_BRDC_FSRD_REG_00B4_BCM88650_B0r */
  69219         soc_block_list[27],
  69220         soc_genreg,
  69221         1,
  69222         0,
  69223         0xb4,
  69224         SOC_REG_FLAG_WO,
  69225         0,
  69226         1,
  69227         soc_BRDC_FSRD_REG_00B4_BCM88650_B0r_fields,
  69228         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  69229         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69230         -1,
  69231         -1,
  69232     },
  69233 #endif /* chips */
  69234 
  69235 #if defined(BCM_88660_A0)
  69236     { /* SOC_REG_INT_BRDC_FSRD_REG_00B4_BCM88660_A0r */
  69237         soc_block_list[27],
  69238         soc_genreg,
  69239         1,
  69240         0,
  69241         0xb4,
  69242         SOC_REG_FLAG_WO,
  69243         0,
  69244         1,
  69245         soc_BRDC_FSRD_REG_00B4_BCM88660_A0r_fields,
  69246         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  69247         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69248         -1,
  69249         -1,
  69250     },
  69251 #endif /* chips */
  69252 
  69253 #if defined(BCM_88202_A0)
  69254     { /* SOC_REG_INT_BRDC_FSRD_REG_00B5_BCM88202_A0r */
  69255         soc_block_list[27],
  69256         soc_genreg,
  69257         1,
  69258         0,
  69259         0xb5,
  69260         SOC_REG_FLAG_WO,
  69261         0,
  69262         3,
  69263         soc_BRDC_FSRD_REG_00B5_BCM88202_A0r_fields,
  69264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69265         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69266         -1,
  69267         -1,
  69268     },
  69269 #endif /* chips */
  69270 
  69271 #if defined(BCM_88650_B0)
  69272     { /* SOC_REG_INT_BRDC_FSRD_REG_00B5_BCM88650_B0r */
  69273         soc_block_list[27],
  69274         soc_genreg,
  69275         1,
  69276         0,
  69277         0xb5,
  69278         SOC_REG_FLAG_WO,
  69279         0,
  69280         3,
  69281         soc_BRDC_FSRD_REG_00B5_BCM88650_B0r_fields,
  69282         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69283         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69284         -1,
  69285         -1,
  69286     },
  69287 #endif /* chips */
  69288 
  69289 #if defined(BCM_88660_A0)
  69290     { /* SOC_REG_INT_BRDC_FSRD_REG_00B5_BCM88660_A0r */
  69291         soc_block_list[27],
  69292         soc_genreg,
  69293         1,
  69294         0,
  69295         0xb5,
  69296         SOC_REG_FLAG_WO,
  69297         0,
  69298         3,
  69299         soc_BRDC_FSRD_REG_00B5_BCM88660_A0r_fields,
  69300         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69301         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69302         -1,
  69303         -1,
  69304     },
  69305 #endif /* chips */
  69306 
  69307 #if defined(BCM_88202_A0)
  69308     { /* SOC_REG_INT_BRDC_FSRD_REG_00B6_BCM88202_A0r */
  69309         soc_block_list[27],
  69310         soc_genreg,
  69311         1,
  69312         0,
  69313         0xb6,
  69314         SOC_REG_FLAG_WO,
  69315         0,
  69316         1,
  69317         soc_BRDC_FSRD_REG_00B6_BCM88202_A0r_fields,
  69318         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69319         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69320         -1,
  69321         -1,
  69322     },
  69323 #endif /* chips */
  69324 
  69325 #if defined(BCM_88650_B0)
  69326     { /* SOC_REG_INT_BRDC_FSRD_REG_00B6_BCM88650_B0r */
  69327         soc_block_list[27],
  69328         soc_genreg,
  69329         1,
  69330         0,
  69331         0xb6,
  69332         SOC_REG_FLAG_WO,
  69333         0,
  69334         1,
  69335         soc_BRDC_FSRD_REG_00B6_BCM88650_B0r_fields,
  69336         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69337         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69338         -1,
  69339         -1,
  69340     },
  69341 #endif /* chips */
  69342 
  69343 #if defined(BCM_88660_A0)
  69344     { /* SOC_REG_INT_BRDC_FSRD_REG_00B6_BCM88660_A0r */
  69345         soc_block_list[27],
  69346         soc_genreg,
  69347         1,
  69348         0,
  69349         0xb6,
  69350         SOC_REG_FLAG_WO,
  69351         0,
  69352         1,
  69353         soc_BRDC_FSRD_REG_00B6_BCM88660_A0r_fields,
  69354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69355         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69356         -1,
  69357         -1,
  69358     },
  69359 #endif /* chips */
  69360 
  69361 #if defined(BCM_88202_A0)
  69362     { /* SOC_REG_INT_BRDC_FSRD_REG_00B7_BCM88202_A0r */
  69363         soc_block_list[27],
  69364         soc_genreg,
  69365         1,
  69366         0,
  69367         0xb7,
  69368         SOC_REG_FLAG_WO,
  69369         0,
  69370         1,
  69371         soc_BRDC_FSRD_REG_00B7_BCM88202_A0r_fields,
  69372         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69373         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69374         -1,
  69375         -1,
  69376     },
  69377 #endif /* chips */
  69378 
  69379 #if defined(BCM_88650_B0)
  69380     { /* SOC_REG_INT_BRDC_FSRD_REG_00B7_BCM88650_B0r */
  69381         soc_block_list[27],
  69382         soc_genreg,
  69383         1,
  69384         0,
  69385         0xb7,
  69386         SOC_REG_FLAG_WO,
  69387         0,
  69388         1,
  69389         soc_BRDC_FSRD_REG_00B7_BCM88650_B0r_fields,
  69390         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69391         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69392         -1,
  69393         -1,
  69394     },
  69395 #endif /* chips */
  69396 
  69397 #if defined(BCM_88660_A0)
  69398     { /* SOC_REG_INT_BRDC_FSRD_REG_00B7_BCM88660_A0r */
  69399         soc_block_list[27],
  69400         soc_genreg,
  69401         1,
  69402         0,
  69403         0xb7,
  69404         SOC_REG_FLAG_WO,
  69405         0,
  69406         1,
  69407         soc_BRDC_FSRD_REG_00B7_BCM88660_A0r_fields,
  69408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69409         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69410         -1,
  69411         -1,
  69412     },
  69413 #endif /* chips */
  69414 
  69415 #if defined(BCM_88690_B0)
  69416     { /* SOC_REG_INT_BRDC_FSRD_REG_00C2r */
  69417         soc_block_list[27],
  69418         soc_genreg,
  69419         1,
  69420         0,
  69421         0xc2,
  69422         SOC_REG_FLAG_WO,
  69423         0,
  69424         6,
  69425         soc_BRDC_FSRD_REG_00C2r_fields,
  69426         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  69427         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  69428         -1,
  69429         -1,
  69430     },
  69431 #endif /* chips */
  69432 
  69433 #if defined(BCM_88650_B0)
  69434     { /* SOC_REG_INT_BRDC_FSRD_REG_0170_BCM88650_B0r */
  69435         soc_block_list[27],
  69436         soc_genreg,
  69437         3,
  69438         0,
  69439         0x170,
  69440         SOC_REG_FLAG_ARRAY |
  69441                           SOC_REG_FLAG_WO |
  69442                           SOC_REG_FLAG_REG_ARRAY,
  69443         0,
  69444         1,
  69445         soc_BRDC_FSRD_REG_0170_BCM88650_B0r_fields,
  69446         SOC_RESET_VAL_DEC(0x00408102, 0x00000000)
  69447         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  69448         -1,
  69449         -1,
  69450     },
  69451 #endif /* chips */
  69452 
  69453 #if defined(BCM_88660_A0)
  69454     { /* SOC_REG_INT_BRDC_FSRD_REG_0170_BCM88660_A0r */
  69455         soc_block_list[27],
  69456         soc_genreg,
  69457         3,
  69458         0,
  69459         0x170,
  69460         SOC_REG_FLAG_ARRAY |
  69461                           SOC_REG_FLAG_WO |
  69462                           SOC_REG_FLAG_REG_ARRAY,
  69463         0,
  69464         1,
  69465         soc_BRDC_FSRD_REG_0170_BCM88660_A0r_fields,
  69466         SOC_RESET_VAL_DEC(0x00408102, 0x00000000)
  69467         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  69468         -1,
  69469         -1,
  69470     },
  69471 #endif /* chips */
  69472 
  69473 #if defined(BCM_88202_A0)
  69474     { /* SOC_REG_INT_BRDC_FSRD_REG_017Br */
  69475         soc_block_list[27],
  69476         soc_genreg,
  69477         3,
  69478         0,
  69479         0x17b,
  69480         SOC_REG_FLAG_ABOVE_64_BITS |
  69481                           SOC_REG_FLAG_ARRAY |
  69482                           SOC_REG_FLAG_WO |
  69483                           SOC_REG_FLAG_REG_ARRAY,
  69484         0,
  69485         1,
  69486         soc_BRDC_FSRD_REG_017Br_fields,
  69487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69488         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69489         -1,
  69490         -1,
  69491     },
  69492 #endif /* chips */
  69493 
  69494 #if defined(BCM_88375_A0)
  69495     { /* SOC_REG_INT_BRDC_FSRD_REG_017B_BCM88375_A0r */
  69496         soc_block_list[27],
  69497         soc_genreg,
  69498         3,
  69499         0,
  69500         0x17b,
  69501         SOC_REG_FLAG_ABOVE_64_BITS |
  69502                           SOC_REG_FLAG_ARRAY |
  69503                           SOC_REG_FLAG_WO |
  69504                           SOC_REG_FLAG_REG_ARRAY,
  69505         0,
  69506         1,
  69507         soc_BRDC_FSRD_REG_017B_BCM88375_A0r_fields,
  69508         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69509         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69510         -1,
  69511         -1,
  69512     },
  69513 #endif /* chips */
  69514 
  69515 #if defined(BCM_88375_B0)
  69516     { /* SOC_REG_INT_BRDC_FSRD_REG_017B_BCM88375_B0r */
  69517         soc_block_list[27],
  69518         soc_genreg,
  69519         3,
  69520         0,
  69521         0x17b,
  69522         SOC_REG_FLAG_ABOVE_64_BITS |
  69523                           SOC_REG_FLAG_ARRAY |
  69524                           SOC_REG_FLAG_WO |
  69525                           SOC_REG_FLAG_REG_ARRAY,
  69526         0,
  69527         1,
  69528         soc_BRDC_FSRD_REG_017B_BCM88375_B0r_fields,
  69529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69530         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69531         -1,
  69532         -1,
  69533     },
  69534 #endif /* chips */
  69535 
  69536 #if defined(BCM_88675_A0)
  69537     { /* SOC_REG_INT_BRDC_FSRD_REG_017B_BCM88675_A0r */
  69538         soc_block_list[27],
  69539         soc_genreg,
  69540         3,
  69541         0,
  69542         0x17b,
  69543         SOC_REG_FLAG_ABOVE_64_BITS |
  69544                           SOC_REG_FLAG_ARRAY |
  69545                           SOC_REG_FLAG_WO |
  69546                           SOC_REG_FLAG_REG_ARRAY,
  69547         0,
  69548         1,
  69549         soc_BRDC_FSRD_REG_017B_BCM88675_A0r_fields,
  69550         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69551         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69552         -1,
  69553         -1,
  69554     },
  69555 #endif /* chips */
  69556 
  69557 #if defined(BCM_88675_B0)
  69558     { /* SOC_REG_INT_BRDC_FSRD_REG_017B_BCM88675_B0r */
  69559         soc_block_list[27],
  69560         soc_genreg,
  69561         3,
  69562         0,
  69563         0x17b,
  69564         SOC_REG_FLAG_ABOVE_64_BITS |
  69565                           SOC_REG_FLAG_ARRAY |
  69566                           SOC_REG_FLAG_WO |
  69567                           SOC_REG_FLAG_REG_ARRAY,
  69568         0,
  69569         1,
  69570         soc_BRDC_FSRD_REG_017B_BCM88675_B0r_fields,
  69571         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69572         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69573         -1,
  69574         -1,
  69575     },
  69576 #endif /* chips */
  69577 
  69578 #if defined(BCM_88680_A0)
  69579     { /* SOC_REG_INT_BRDC_FSRD_REG_017B_BCM88680_A0r */
  69580         soc_block_list[27],
  69581         soc_genreg,
  69582         3,
  69583         0,
  69584         0x17b,
  69585         SOC_REG_FLAG_ABOVE_64_BITS |
  69586                           SOC_REG_FLAG_ARRAY |
  69587                           SOC_REG_FLAG_WO |
  69588                           SOC_REG_FLAG_REG_ARRAY,
  69589         0,
  69590         1,
  69591         soc_BRDC_FSRD_REG_017B_BCM88680_A0r_fields,
  69592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69593         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69594         -1,
  69595         -1,
  69596     },
  69597 #endif /* chips */
  69598 
  69599 #if defined(BCM_88950_A0)
  69600     { /* SOC_REG_INT_BRDC_FSRD_REG_017B_BCM88950_A0r */
  69601         soc_block_list[27],
  69602         soc_genreg,
  69603         3,
  69604         0,
  69605         0x17b,
  69606         SOC_REG_FLAG_ABOVE_64_BITS |
  69607                           SOC_REG_FLAG_ARRAY |
  69608                           SOC_REG_FLAG_WO |
  69609                           SOC_REG_FLAG_REG_ARRAY,
  69610         0,
  69611         1,
  69612         soc_BRDC_FSRD_REG_017B_BCM88950_A0r_fields,
  69613         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69614         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  69615         -1,
  69616         -1,
  69617     },
  69618 #endif /* chips */
  69619 
  69620 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69621     { /* SOC_REG_INT_BRDC_FSRD_REG_01E9r */
  69622         soc_block_list[27],
  69623         soc_genreg,
  69624         1,
  69625         0,
  69626         0x1e9,
  69627         SOC_REG_FLAG_WO,
  69628         0,
  69629         3,
  69630         soc_DRCBROADCAST_REG_00B1_BCM83207_A0r_fields,
  69631         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69632         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69633         -1,
  69634         -1,
  69635     },
  69636 #endif /* chips */
  69637 
  69638 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69639     { /* SOC_REG_INT_BRDC_FSRD_REG_01EAr */
  69640         soc_block_list[27],
  69641         soc_genreg,
  69642         1,
  69643         0,
  69644         0x1ea,
  69645         SOC_REG_FLAG_WO,
  69646         0,
  69647         1,
  69648         soc_DRCBROADCAST_REG_00B2_BCM83207_A0r_fields,
  69649         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69650         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69651         -1,
  69652         -1,
  69653     },
  69654 #endif /* chips */
  69655 
  69656 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69657     { /* SOC_REG_INT_BRDC_FSRD_REG_01EBr */
  69658         soc_block_list[27],
  69659         soc_genreg,
  69660         1,
  69661         0,
  69662         0x1eb,
  69663         SOC_REG_FLAG_WO,
  69664         0,
  69665         1,
  69666         soc_DRCBROADCAST_REG_00B3_BCM83207_A0r_fields,
  69667         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69668         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69669         -1,
  69670         -1,
  69671     },
  69672 #endif /* chips */
  69673 
  69674 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69675     { /* SOC_REG_INT_BRDC_FSRD_REG_01ECr */
  69676         soc_block_list[27],
  69677         soc_genreg,
  69678         1,
  69679         0,
  69680         0x1ec,
  69681         SOC_REG_FLAG_WO,
  69682         0,
  69683         1,
  69684         soc_DRCBROADCAST_REG_00B4_BCM83207_A0r_fields,
  69685         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  69686         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69687         -1,
  69688         -1,
  69689     },
  69690 #endif /* chips */
  69691 
  69692 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69693     { /* SOC_REG_INT_BRDC_FSRD_REG_01EDr */
  69694         soc_block_list[27],
  69695         soc_genreg,
  69696         1,
  69697         0,
  69698         0x1ed,
  69699         SOC_REG_FLAG_WO,
  69700         0,
  69701         3,
  69702         soc_DRCBROADCAST_REG_00B1_BCM83207_A0r_fields,
  69703         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69704         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69705         -1,
  69706         -1,
  69707     },
  69708 #endif /* chips */
  69709 
  69710 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69711     { /* SOC_REG_INT_BRDC_FSRD_REG_01EEr */
  69712         soc_block_list[27],
  69713         soc_genreg,
  69714         1,
  69715         0,
  69716         0x1ee,
  69717         SOC_REG_FLAG_WO,
  69718         0,
  69719         1,
  69720         soc_DRCBROADCAST_REG_00B2_BCM83207_A0r_fields,
  69721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69722         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69723         -1,
  69724         -1,
  69725     },
  69726 #endif /* chips */
  69727 
  69728 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69729     { /* SOC_REG_INT_BRDC_FSRD_REG_01EFr */
  69730         soc_block_list[27],
  69731         soc_genreg,
  69732         1,
  69733         0,
  69734         0x1ef,
  69735         SOC_REG_FLAG_WO,
  69736         0,
  69737         1,
  69738         soc_DRCBROADCAST_REG_00B3_BCM83207_A0r_fields,
  69739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69740         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69741         -1,
  69742         -1,
  69743     },
  69744 #endif /* chips */
  69745 
  69746 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69747     { /* SOC_REG_INT_BRDC_FSRD_REG_01F0r */
  69748         soc_block_list[27],
  69749         soc_genreg,
  69750         1,
  69751         0,
  69752         0x1f0,
  69753         SOC_REG_FLAG_WO,
  69754         0,
  69755         1,
  69756         soc_DRCBROADCAST_REG_00B4_BCM83207_A0r_fields,
  69757         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  69758         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69759         -1,
  69760         -1,
  69761     },
  69762 #endif /* chips */
  69763 
  69764 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69765     { /* SOC_REG_INT_BRDC_FSRD_REG_01F1r */
  69766         soc_block_list[27],
  69767         soc_genreg,
  69768         1,
  69769         0,
  69770         0x1f1,
  69771         SOC_REG_FLAG_WO,
  69772         0,
  69773         3,
  69774         soc_DRCBROADCAST_REG_00B1_BCM83207_A0r_fields,
  69775         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69776         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69777         -1,
  69778         -1,
  69779     },
  69780 #endif /* chips */
  69781 
  69782 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69783     { /* SOC_REG_INT_BRDC_FSRD_REG_01F2r */
  69784         soc_block_list[27],
  69785         soc_genreg,
  69786         1,
  69787         0,
  69788         0x1f2,
  69789         SOC_REG_FLAG_WO,
  69790         0,
  69791         1,
  69792         soc_DRCBROADCAST_REG_00B2_BCM83207_A0r_fields,
  69793         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69794         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  69795         -1,
  69796         -1,
  69797     },
  69798 #endif /* chips */
  69799 
  69800 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69801     { /* SOC_REG_INT_BRDC_FSRD_REG_01F3r */
  69802         soc_block_list[27],
  69803         soc_genreg,
  69804         1,
  69805         0,
  69806         0x1f3,
  69807         SOC_REG_FLAG_WO,
  69808         0,
  69809         1,
  69810         soc_DRCBROADCAST_REG_00B3_BCM83207_A0r_fields,
  69811         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69812         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  69813         -1,
  69814         -1,
  69815     },
  69816 #endif /* chips */
  69817 
  69818 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  69819     { /* SOC_REG_INT_BRDC_FSRD_REG_1E8r */
  69820         soc_block_list[27],
  69821         soc_genreg,
  69822         1,
  69823         0,
  69824         0x1e8,
  69825         SOC_REG_FLAG_WO,
  69826         0,
  69827         1,
  69828         soc_DRCBROADCAST_REG_00B4_BCM83207_A0r_fields,
  69829         SOC_RESET_VAL_DEC(0x1fca0555, 0x00000000)
  69830         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  69831         -1,
  69832         -1,
  69833     },
  69834 #endif /* chips */
  69835 
  69836 #if defined(BCM_88675_A0)
  69837     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDRr */
  69838         soc_block_list[27],
  69839         soc_genreg,
  69840         1,
  69841         0,
  69842         0x85,
  69843         SOC_REG_FLAG_WO,
  69844         0,
  69845         2,
  69846         soc_BRDC_FSRD_RESERVED_MIRROR_ADDRr_fields,
  69847         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69848         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69849         -1,
  69850         -1,
  69851     },
  69852 #endif /* chips */
  69853 
  69854 #if defined(BCM_88375_A0)
  69855     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88375_A0r */
  69856         soc_block_list[27],
  69857         soc_genreg,
  69858         1,
  69859         0,
  69860         0x85,
  69861         SOC_REG_FLAG_WO,
  69862         0,
  69863         2,
  69864         soc_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88375_A0r_fields,
  69865         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69866         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69867         -1,
  69868         -1,
  69869     },
  69870 #endif /* chips */
  69871 
  69872 #if defined(BCM_88375_B0)
  69873     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88375_B0r */
  69874         soc_block_list[27],
  69875         soc_genreg,
  69876         1,
  69877         0,
  69878         0x85,
  69879         SOC_REG_FLAG_WO,
  69880         0,
  69881         2,
  69882         soc_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88375_B0r_fields,
  69883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69884         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69885         -1,
  69886         -1,
  69887     },
  69888 #endif /* chips */
  69889 
  69890 #if defined(BCM_88675_B0)
  69891     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88675_B0r */
  69892         soc_block_list[27],
  69893         soc_genreg,
  69894         1,
  69895         0,
  69896         0x85,
  69897         SOC_REG_FLAG_WO,
  69898         0,
  69899         2,
  69900         soc_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88675_B0r_fields,
  69901         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69902         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69903         -1,
  69904         -1,
  69905     },
  69906 #endif /* chips */
  69907 
  69908 #if defined(BCM_88680_A0)
  69909     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88680_A0r */
  69910         soc_block_list[27],
  69911         soc_genreg,
  69912         1,
  69913         0,
  69914         0x85,
  69915         SOC_REG_FLAG_WO,
  69916         0,
  69917         2,
  69918         soc_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88680_A0r_fields,
  69919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69920         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69921         -1,
  69922         -1,
  69923     },
  69924 #endif /* chips */
  69925 
  69926 #if defined(BCM_88690_A0)
  69927     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88690_A0r */
  69928         soc_block_list[27],
  69929         soc_genreg,
  69930         1,
  69931         0,
  69932         0x85,
  69933         SOC_REG_FLAG_WO,
  69934         0,
  69935         2,
  69936         soc_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88690_A0r_fields,
  69937         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69938         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69939         -1,
  69940         -1,
  69941     },
  69942 #endif /* chips */
  69943 
  69944 #if defined(BCM_88690_B0)
  69945     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88690_B0r */
  69946         soc_block_list[27],
  69947         soc_genreg,
  69948         1,
  69949         0,
  69950         0x85,
  69951         SOC_REG_FLAG_WO,
  69952         0,
  69953         2,
  69954         soc_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
  69955         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69956         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69957         -1,
  69958         -1,
  69959     },
  69960 #endif /* chips */
  69961 
  69962 #if defined(BCM_88790_A0)
  69963     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88790_A0r */
  69964         soc_block_list[27],
  69965         soc_genreg,
  69966         1,
  69967         0,
  69968         0x85,
  69969         SOC_REG_FLAG_WO,
  69970         0,
  69971         2,
  69972         soc_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88790_A0r_fields,
  69973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69974         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69975         -1,
  69976         -1,
  69977     },
  69978 #endif /* chips */
  69979 
  69980 #if defined(BCM_88950_A0)
  69981     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MIRROR_ADDR_BCM88950_A0r */
  69982         soc_block_list[27],
  69983         soc_genreg,
  69984         1,
  69985         0,
  69986         0x85,
  69987         SOC_REG_FLAG_WO,
  69988         0,
  69989         2,
  69990         soc_BRDC_CCS_RESERVED_MIRROR_ADDRr_fields,
  69991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  69992         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  69993         -1,
  69994         -1,
  69995     },
  69996 #endif /* chips */
  69997 
  69998 #if defined(BCM_88675_A0)
  69999     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCDr */
  70000         soc_block_list[27],
  70001         soc_genreg,
  70002         1,
  70003         0,
  70004         0xae,
  70005         SOC_REG_FLAG_WO,
  70006         0,
  70007         6,
  70008         soc_BRDC_FSRD_RESERVED_MTCDr_fields,
  70009         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70010         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70011         -1,
  70012         -1,
  70013     },
  70014 #endif /* chips */
  70015 
  70016 #if defined(BCM_88375_A0)
  70017     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCD_BCM88375_A0r */
  70018         soc_block_list[27],
  70019         soc_genreg,
  70020         1,
  70021         0,
  70022         0xae,
  70023         SOC_REG_FLAG_WO,
  70024         0,
  70025         6,
  70026         soc_BRDC_FSRD_RESERVED_MTCD_BCM88375_A0r_fields,
  70027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70028         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70029         -1,
  70030         -1,
  70031     },
  70032 #endif /* chips */
  70033 
  70034 #if defined(BCM_88375_B0)
  70035     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCD_BCM88375_B0r */
  70036         soc_block_list[27],
  70037         soc_genreg,
  70038         1,
  70039         0,
  70040         0xae,
  70041         SOC_REG_FLAG_WO,
  70042         0,
  70043         6,
  70044         soc_BRDC_FSRD_RESERVED_MTCD_BCM88375_B0r_fields,
  70045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70046         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70047         -1,
  70048         -1,
  70049     },
  70050 #endif /* chips */
  70051 
  70052 #if defined(BCM_88675_B0)
  70053     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCD_BCM88675_B0r */
  70054         soc_block_list[27],
  70055         soc_genreg,
  70056         1,
  70057         0,
  70058         0xae,
  70059         SOC_REG_FLAG_WO,
  70060         0,
  70061         6,
  70062         soc_BRDC_FSRD_RESERVED_MTCD_BCM88675_B0r_fields,
  70063         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70064         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70065         -1,
  70066         -1,
  70067     },
  70068 #endif /* chips */
  70069 
  70070 #if defined(BCM_88680_A0)
  70071     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCD_BCM88680_A0r */
  70072         soc_block_list[27],
  70073         soc_genreg,
  70074         1,
  70075         0,
  70076         0xae,
  70077         SOC_REG_FLAG_WO,
  70078         0,
  70079         6,
  70080         soc_BRDC_FSRD_RESERVED_MTCD_BCM88680_A0r_fields,
  70081         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70082         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70083         -1,
  70084         -1,
  70085     },
  70086 #endif /* chips */
  70087 
  70088 #if defined(BCM_88690_A0)
  70089     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCD_BCM88690_A0r */
  70090         soc_block_list[27],
  70091         soc_genreg,
  70092         1,
  70093         0,
  70094         0xae,
  70095         SOC_REG_FLAG_WO,
  70096         0,
  70097         6,
  70098         soc_BRDC_FSRD_RESERVED_MTCD_BCM88690_A0r_fields,
  70099         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70100         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70101         -1,
  70102         -1,
  70103     },
  70104 #endif /* chips */
  70105 
  70106 #if defined(BCM_88690_B0)
  70107     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCD_BCM88690_B0r */
  70108         soc_block_list[27],
  70109         soc_genreg,
  70110         1,
  70111         0,
  70112         0xae,
  70113         SOC_REG_FLAG_WO,
  70114         0,
  70115         6,
  70116         soc_BRDC_FSRD_RESERVED_MTCD_BCM88690_B0r_fields,
  70117         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70118         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70119         -1,
  70120         -1,
  70121     },
  70122 #endif /* chips */
  70123 
  70124 #if defined(BCM_88790_A0)
  70125     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCD_BCM88790_A0r */
  70126         soc_block_list[27],
  70127         soc_genreg,
  70128         1,
  70129         0,
  70130         0xae,
  70131         SOC_REG_FLAG_WO,
  70132         0,
  70133         6,
  70134         soc_BRDC_FSRD_RESERVED_MTCD_BCM88790_A0r_fields,
  70135         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70136         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  70137         -1,
  70138         -1,
  70139     },
  70140 #endif /* chips */
  70141 
  70142 #if defined(BCM_88675_A0)
  70143     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCPr */
  70144         soc_block_list[27],
  70145         soc_genreg,
  70146         1,
  70147         0,
  70148         0xad,
  70149         SOC_REG_FLAG_64_BITS |
  70150                           SOC_REG_FLAG_WO,
  70151         0,
  70152         17,
  70153         soc_BRDC_FSRD_RESERVED_MTCPr_fields,
  70154         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70155         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70156         -1,
  70157         -1,
  70158     },
  70159 #endif /* chips */
  70160 
  70161 #if defined(BCM_88375_A0)
  70162     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88375_A0r */
  70163         soc_block_list[27],
  70164         soc_genreg,
  70165         1,
  70166         0,
  70167         0xad,
  70168         SOC_REG_FLAG_64_BITS |
  70169                           SOC_REG_FLAG_WO,
  70170         0,
  70171         17,
  70172         soc_BRDC_FSRD_RESERVED_MTCP_BCM88375_A0r_fields,
  70173         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70174         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70175         -1,
  70176         -1,
  70177     },
  70178 #endif /* chips */
  70179 
  70180 #if defined(BCM_88375_B0)
  70181     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88375_B0r */
  70182         soc_block_list[27],
  70183         soc_genreg,
  70184         1,
  70185         0,
  70186         0xad,
  70187         SOC_REG_FLAG_64_BITS |
  70188                           SOC_REG_FLAG_WO,
  70189         0,
  70190         17,
  70191         soc_BRDC_FSRD_RESERVED_MTCP_BCM88375_B0r_fields,
  70192         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70193         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70194         -1,
  70195         -1,
  70196     },
  70197 #endif /* chips */
  70198 
  70199 #if defined(BCM_88675_B0)
  70200     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88675_B0r */
  70201         soc_block_list[27],
  70202         soc_genreg,
  70203         1,
  70204         0,
  70205         0xad,
  70206         SOC_REG_FLAG_64_BITS |
  70207                           SOC_REG_FLAG_WO,
  70208         0,
  70209         17,
  70210         soc_BRDC_FSRD_RESERVED_MTCP_BCM88675_B0r_fields,
  70211         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70212         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70213         -1,
  70214         -1,
  70215     },
  70216 #endif /* chips */
  70217 
  70218 #if defined(BCM_88680_A0)
  70219     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88680_A0r */
  70220         soc_block_list[27],
  70221         soc_genreg,
  70222         1,
  70223         0,
  70224         0xad,
  70225         SOC_REG_FLAG_64_BITS |
  70226                           SOC_REG_FLAG_WO,
  70227         0,
  70228         17,
  70229         soc_BRDC_FSRD_RESERVED_MTCP_BCM88680_A0r_fields,
  70230         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70231         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70232         -1,
  70233         -1,
  70234     },
  70235 #endif /* chips */
  70236 
  70237 #if defined(BCM_88690_A0)
  70238     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88690_A0r */
  70239         soc_block_list[27],
  70240         soc_genreg,
  70241         1,
  70242         0,
  70243         0xad,
  70244         SOC_REG_FLAG_64_BITS |
  70245                           SOC_REG_FLAG_WO,
  70246         0,
  70247         17,
  70248         soc_BRDC_FSRD_RESERVED_MTCP_BCM88690_A0r_fields,
  70249         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70250         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70251         -1,
  70252         -1,
  70253     },
  70254 #endif /* chips */
  70255 
  70256 #if defined(BCM_88690_B0)
  70257     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88690_B0r */
  70258         soc_block_list[27],
  70259         soc_genreg,
  70260         1,
  70261         0,
  70262         0xad,
  70263         SOC_REG_FLAG_64_BITS |
  70264                           SOC_REG_FLAG_WO,
  70265         0,
  70266         17,
  70267         soc_BRDC_FSRD_RESERVED_MTCP_BCM88690_B0r_fields,
  70268         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70269         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70270         -1,
  70271         -1,
  70272     },
  70273 #endif /* chips */
  70274 
  70275 #if defined(BCM_88790_A0)
  70276     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88790_A0r */
  70277         soc_block_list[27],
  70278         soc_genreg,
  70279         1,
  70280         0,
  70281         0xad,
  70282         SOC_REG_FLAG_64_BITS |
  70283                           SOC_REG_FLAG_WO,
  70284         0,
  70285         17,
  70286         soc_BRDC_FSRD_RESERVED_MTCP_BCM88790_A0r_fields,
  70287         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  70288         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  70289         -1,
  70290         -1,
  70291     },
  70292 #endif /* chips */
  70293 
  70294 #if defined(BCM_88950_A0)
  70295     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_MTCP_BCM88950_A0r */
  70296         soc_block_list[27],
  70297         soc_genreg,
  70298         1,
  70299         0,
  70300         0xad,
  70301         SOC_REG_FLAG_64_BITS |
  70302                           SOC_REG_FLAG_WO,
  70303         0,
  70304         18,
  70305         soc_BRDC_CCS_RESERVED_MTCPr_fields,
  70306         SOC_RESET_VAL_DEC(0x80000000, 0x00000001)
  70307         SOC_RESET_MASK_DEC(0xffffffff, 0x07ffffff)
  70308         -1,
  70309         -1,
  70310     },
  70311 #endif /* chips */
  70312 
  70313 #if defined(BCM_88675_A0)
  70314     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0r */
  70315         soc_block_list[27],
  70316         soc_genreg,
  70317         1,
  70318         0,
  70319         0xb0,
  70320         SOC_REG_FLAG_WO,
  70321         0,
  70322         1,
  70323         soc_BRDC_FSRD_RESERVED_PCMI_0r_fields,
  70324         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70325         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70326         -1,
  70327         -1,
  70328     },
  70329 #endif /* chips */
  70330 
  70331 #if defined(BCM_88675_A0)
  70332     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1r */
  70333         soc_block_list[27],
  70334         soc_genreg,
  70335         1,
  70336         0,
  70337         0xb3,
  70338         SOC_REG_FLAG_WO,
  70339         0,
  70340         1,
  70341         soc_BRDC_FSRD_RESERVED_PCMI_1r_fields,
  70342         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70343         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70344         -1,
  70345         -1,
  70346     },
  70347 #endif /* chips */
  70348 
  70349 #if defined(BCM_88675_A0)
  70350     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2r */
  70351         soc_block_list[27],
  70352         soc_genreg,
  70353         1,
  70354         0,
  70355         0xb6,
  70356         SOC_REG_FLAG_WO,
  70357         0,
  70358         1,
  70359         soc_BRDC_FSRD_RESERVED_PCMI_2r_fields,
  70360         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70361         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70362         -1,
  70363         -1,
  70364     },
  70365 #endif /* chips */
  70366 
  70367 #if defined(BCM_88675_A0)
  70368     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4r */
  70369         soc_block_list[27],
  70370         soc_genreg,
  70371         1,
  70372         0,
  70373         0xbc,
  70374         SOC_REG_FLAG_WO,
  70375         0,
  70376         1,
  70377         soc_BRDC_FSRD_RESERVED_PCMI_4r_fields,
  70378         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70379         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70380         -1,
  70381         -1,
  70382     },
  70383 #endif /* chips */
  70384 
  70385 #if defined(BCM_88375_A0)
  70386     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_BCM88375_A0r */
  70387         soc_block_list[27],
  70388         soc_genreg,
  70389         1,
  70390         0,
  70391         0xb0,
  70392         SOC_REG_FLAG_WO,
  70393         0,
  70394         1,
  70395         soc_BRDC_FSRD_RESERVED_PCMI_0_BCM88375_A0r_fields,
  70396         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70397         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70398         -1,
  70399         -1,
  70400     },
  70401 #endif /* chips */
  70402 
  70403 #if defined(BCM_88375_B0)
  70404     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_BCM88375_B0r */
  70405         soc_block_list[27],
  70406         soc_genreg,
  70407         1,
  70408         0,
  70409         0xb0,
  70410         SOC_REG_FLAG_WO,
  70411         0,
  70412         1,
  70413         soc_BRDC_FSRD_RESERVED_PCMI_0_BCM88375_B0r_fields,
  70414         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70415         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70416         -1,
  70417         -1,
  70418     },
  70419 #endif /* chips */
  70420 
  70421 #if defined(BCM_88675_B0)
  70422     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_BCM88675_B0r */
  70423         soc_block_list[27],
  70424         soc_genreg,
  70425         1,
  70426         0,
  70427         0xb0,
  70428         SOC_REG_FLAG_WO,
  70429         0,
  70430         1,
  70431         soc_BRDC_FSRD_RESERVED_PCMI_0_BCM88675_B0r_fields,
  70432         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70433         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70434         -1,
  70435         -1,
  70436     },
  70437 #endif /* chips */
  70438 
  70439 #if defined(BCM_88680_A0)
  70440     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_BCM88680_A0r */
  70441         soc_block_list[27],
  70442         soc_genreg,
  70443         1,
  70444         0,
  70445         0xb0,
  70446         SOC_REG_FLAG_WO,
  70447         0,
  70448         1,
  70449         soc_BRDC_FSRD_RESERVED_PCMI_0_BCM88680_A0r_fields,
  70450         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70451         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70452         -1,
  70453         -1,
  70454     },
  70455 #endif /* chips */
  70456 
  70457 #if defined(BCM_88950_A0)
  70458     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_BCM88950_A0r */
  70459         soc_block_list[27],
  70460         soc_genreg,
  70461         1,
  70462         0,
  70463         0xb0,
  70464         SOC_REG_FLAG_WO,
  70465         0,
  70466         1,
  70467         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  70468         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70469         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70470         -1,
  70471         -1,
  70472     },
  70473 #endif /* chips */
  70474 
  70475 #if defined(BCM_88675_A0)
  70476     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_Sr */
  70477         soc_block_list[27],
  70478         soc_genreg,
  70479         1,
  70480         0,
  70481         0xb1,
  70482         SOC_REG_FLAG_RO |
  70483                           SOC_REG_FLAG_WO,
  70484         0,
  70485         3,
  70486         soc_BRDC_FSRD_RESERVED_PCMI_0_Sr_fields,
  70487         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70488         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70489         -1,
  70490         -1,
  70491     },
  70492 #endif /* chips */
  70493 
  70494 #if defined(BCM_88375_A0)
  70495     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88375_A0r */
  70496         soc_block_list[27],
  70497         soc_genreg,
  70498         1,
  70499         0,
  70500         0xb1,
  70501         SOC_REG_FLAG_RO |
  70502                           SOC_REG_FLAG_WO,
  70503         0,
  70504         3,
  70505         soc_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88375_A0r_fields,
  70506         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70507         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70508         -1,
  70509         -1,
  70510     },
  70511 #endif /* chips */
  70512 
  70513 #if defined(BCM_88375_B0)
  70514     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88375_B0r */
  70515         soc_block_list[27],
  70516         soc_genreg,
  70517         1,
  70518         0,
  70519         0xb1,
  70520         SOC_REG_FLAG_RO |
  70521                           SOC_REG_FLAG_WO,
  70522         0,
  70523         3,
  70524         soc_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88375_B0r_fields,
  70525         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70526         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70527         -1,
  70528         -1,
  70529     },
  70530 #endif /* chips */
  70531 
  70532 #if defined(BCM_88675_B0)
  70533     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88675_B0r */
  70534         soc_block_list[27],
  70535         soc_genreg,
  70536         1,
  70537         0,
  70538         0xb1,
  70539         SOC_REG_FLAG_RO |
  70540                           SOC_REG_FLAG_WO,
  70541         0,
  70542         3,
  70543         soc_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88675_B0r_fields,
  70544         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70545         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70546         -1,
  70547         -1,
  70548     },
  70549 #endif /* chips */
  70550 
  70551 #if defined(BCM_88680_A0)
  70552     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88680_A0r */
  70553         soc_block_list[27],
  70554         soc_genreg,
  70555         1,
  70556         0,
  70557         0xb1,
  70558         SOC_REG_FLAG_RO |
  70559                           SOC_REG_FLAG_WO,
  70560         0,
  70561         3,
  70562         soc_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88680_A0r_fields,
  70563         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70564         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70565         -1,
  70566         -1,
  70567     },
  70568 #endif /* chips */
  70569 
  70570 #if defined(BCM_88950_A0)
  70571     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_S_BCM88950_A0r */
  70572         soc_block_list[27],
  70573         soc_genreg,
  70574         1,
  70575         0,
  70576         0xb1,
  70577         SOC_REG_FLAG_RO |
  70578                           SOC_REG_FLAG_WO,
  70579         0,
  70580         3,
  70581         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  70582         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70583         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70584         -1,
  70585         -1,
  70586     },
  70587 #endif /* chips */
  70588 
  70589 #if defined(BCM_88675_A0)
  70590     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_Tr */
  70591         soc_block_list[27],
  70592         soc_genreg,
  70593         1,
  70594         0,
  70595         0xb2,
  70596         SOC_REG_FLAG_WO,
  70597         0,
  70598         2,
  70599         soc_BRDC_FSRD_RESERVED_PCMI_0_Tr_fields,
  70600         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70601         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70602         -1,
  70603         -1,
  70604     },
  70605 #endif /* chips */
  70606 
  70607 #if defined(BCM_88375_A0)
  70608     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88375_A0r */
  70609         soc_block_list[27],
  70610         soc_genreg,
  70611         1,
  70612         0,
  70613         0xb2,
  70614         SOC_REG_FLAG_WO,
  70615         0,
  70616         2,
  70617         soc_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88375_A0r_fields,
  70618         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70619         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70620         -1,
  70621         -1,
  70622     },
  70623 #endif /* chips */
  70624 
  70625 #if defined(BCM_88375_B0)
  70626     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88375_B0r */
  70627         soc_block_list[27],
  70628         soc_genreg,
  70629         1,
  70630         0,
  70631         0xb2,
  70632         SOC_REG_FLAG_WO,
  70633         0,
  70634         2,
  70635         soc_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88375_B0r_fields,
  70636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70637         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70638         -1,
  70639         -1,
  70640     },
  70641 #endif /* chips */
  70642 
  70643 #if defined(BCM_88675_B0)
  70644     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88675_B0r */
  70645         soc_block_list[27],
  70646         soc_genreg,
  70647         1,
  70648         0,
  70649         0xb2,
  70650         SOC_REG_FLAG_WO,
  70651         0,
  70652         2,
  70653         soc_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88675_B0r_fields,
  70654         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70655         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70656         -1,
  70657         -1,
  70658     },
  70659 #endif /* chips */
  70660 
  70661 #if defined(BCM_88680_A0)
  70662     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88680_A0r */
  70663         soc_block_list[27],
  70664         soc_genreg,
  70665         1,
  70666         0,
  70667         0xb2,
  70668         SOC_REG_FLAG_WO,
  70669         0,
  70670         2,
  70671         soc_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88680_A0r_fields,
  70672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70673         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70674         -1,
  70675         -1,
  70676     },
  70677 #endif /* chips */
  70678 
  70679 #if defined(BCM_88950_A0)
  70680     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_0_T_BCM88950_A0r */
  70681         soc_block_list[27],
  70682         soc_genreg,
  70683         1,
  70684         0,
  70685         0xb2,
  70686         SOC_REG_FLAG_WO,
  70687         0,
  70688         2,
  70689         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  70690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70691         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70692         -1,
  70693         -1,
  70694     },
  70695 #endif /* chips */
  70696 
  70697 #if defined(BCM_88375_A0)
  70698     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_BCM88375_A0r */
  70699         soc_block_list[27],
  70700         soc_genreg,
  70701         1,
  70702         0,
  70703         0xb3,
  70704         SOC_REG_FLAG_WO,
  70705         0,
  70706         1,
  70707         soc_BRDC_FSRD_RESERVED_PCMI_1_BCM88375_A0r_fields,
  70708         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70709         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70710         -1,
  70711         -1,
  70712     },
  70713 #endif /* chips */
  70714 
  70715 #if defined(BCM_88375_B0)
  70716     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_BCM88375_B0r */
  70717         soc_block_list[27],
  70718         soc_genreg,
  70719         1,
  70720         0,
  70721         0xb3,
  70722         SOC_REG_FLAG_WO,
  70723         0,
  70724         1,
  70725         soc_BRDC_FSRD_RESERVED_PCMI_1_BCM88375_B0r_fields,
  70726         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70727         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70728         -1,
  70729         -1,
  70730     },
  70731 #endif /* chips */
  70732 
  70733 #if defined(BCM_88675_B0)
  70734     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_BCM88675_B0r */
  70735         soc_block_list[27],
  70736         soc_genreg,
  70737         1,
  70738         0,
  70739         0xb3,
  70740         SOC_REG_FLAG_WO,
  70741         0,
  70742         1,
  70743         soc_BRDC_FSRD_RESERVED_PCMI_1_BCM88675_B0r_fields,
  70744         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70745         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70746         -1,
  70747         -1,
  70748     },
  70749 #endif /* chips */
  70750 
  70751 #if defined(BCM_88680_A0)
  70752     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_BCM88680_A0r */
  70753         soc_block_list[27],
  70754         soc_genreg,
  70755         1,
  70756         0,
  70757         0xb3,
  70758         SOC_REG_FLAG_WO,
  70759         0,
  70760         1,
  70761         soc_BRDC_FSRD_RESERVED_PCMI_1_BCM88680_A0r_fields,
  70762         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70763         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70764         -1,
  70765         -1,
  70766     },
  70767 #endif /* chips */
  70768 
  70769 #if defined(BCM_88950_A0)
  70770     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_BCM88950_A0r */
  70771         soc_block_list[27],
  70772         soc_genreg,
  70773         1,
  70774         0,
  70775         0xb3,
  70776         SOC_REG_FLAG_WO,
  70777         0,
  70778         1,
  70779         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  70780         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  70781         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70782         -1,
  70783         -1,
  70784     },
  70785 #endif /* chips */
  70786 
  70787 #if defined(BCM_88675_A0)
  70788     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_Sr */
  70789         soc_block_list[27],
  70790         soc_genreg,
  70791         1,
  70792         0,
  70793         0xb4,
  70794         SOC_REG_FLAG_RO |
  70795                           SOC_REG_FLAG_WO,
  70796         0,
  70797         3,
  70798         soc_BRDC_FSRD_RESERVED_PCMI_1_Sr_fields,
  70799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70800         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70801         -1,
  70802         -1,
  70803     },
  70804 #endif /* chips */
  70805 
  70806 #if defined(BCM_88375_A0)
  70807     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88375_A0r */
  70808         soc_block_list[27],
  70809         soc_genreg,
  70810         1,
  70811         0,
  70812         0xb4,
  70813         SOC_REG_FLAG_RO |
  70814                           SOC_REG_FLAG_WO,
  70815         0,
  70816         3,
  70817         soc_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88375_A0r_fields,
  70818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70819         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70820         -1,
  70821         -1,
  70822     },
  70823 #endif /* chips */
  70824 
  70825 #if defined(BCM_88375_B0)
  70826     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88375_B0r */
  70827         soc_block_list[27],
  70828         soc_genreg,
  70829         1,
  70830         0,
  70831         0xb4,
  70832         SOC_REG_FLAG_RO |
  70833                           SOC_REG_FLAG_WO,
  70834         0,
  70835         3,
  70836         soc_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88375_B0r_fields,
  70837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70838         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70839         -1,
  70840         -1,
  70841     },
  70842 #endif /* chips */
  70843 
  70844 #if defined(BCM_88675_B0)
  70845     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88675_B0r */
  70846         soc_block_list[27],
  70847         soc_genreg,
  70848         1,
  70849         0,
  70850         0xb4,
  70851         SOC_REG_FLAG_RO |
  70852                           SOC_REG_FLAG_WO,
  70853         0,
  70854         3,
  70855         soc_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88675_B0r_fields,
  70856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70857         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70858         -1,
  70859         -1,
  70860     },
  70861 #endif /* chips */
  70862 
  70863 #if defined(BCM_88680_A0)
  70864     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88680_A0r */
  70865         soc_block_list[27],
  70866         soc_genreg,
  70867         1,
  70868         0,
  70869         0xb4,
  70870         SOC_REG_FLAG_RO |
  70871                           SOC_REG_FLAG_WO,
  70872         0,
  70873         3,
  70874         soc_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88680_A0r_fields,
  70875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70876         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70877         -1,
  70878         -1,
  70879     },
  70880 #endif /* chips */
  70881 
  70882 #if defined(BCM_88950_A0)
  70883     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_S_BCM88950_A0r */
  70884         soc_block_list[27],
  70885         soc_genreg,
  70886         1,
  70887         0,
  70888         0xb4,
  70889         SOC_REG_FLAG_RO |
  70890                           SOC_REG_FLAG_WO,
  70891         0,
  70892         3,
  70893         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  70894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70895         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  70896         -1,
  70897         -1,
  70898     },
  70899 #endif /* chips */
  70900 
  70901 #if defined(BCM_88675_A0)
  70902     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_Tr */
  70903         soc_block_list[27],
  70904         soc_genreg,
  70905         1,
  70906         0,
  70907         0xb5,
  70908         SOC_REG_FLAG_WO,
  70909         0,
  70910         2,
  70911         soc_BRDC_FSRD_RESERVED_PCMI_1_Tr_fields,
  70912         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70913         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70914         -1,
  70915         -1,
  70916     },
  70917 #endif /* chips */
  70918 
  70919 #if defined(BCM_88375_A0)
  70920     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88375_A0r */
  70921         soc_block_list[27],
  70922         soc_genreg,
  70923         1,
  70924         0,
  70925         0xb5,
  70926         SOC_REG_FLAG_WO,
  70927         0,
  70928         2,
  70929         soc_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88375_A0r_fields,
  70930         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70931         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70932         -1,
  70933         -1,
  70934     },
  70935 #endif /* chips */
  70936 
  70937 #if defined(BCM_88375_B0)
  70938     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88375_B0r */
  70939         soc_block_list[27],
  70940         soc_genreg,
  70941         1,
  70942         0,
  70943         0xb5,
  70944         SOC_REG_FLAG_WO,
  70945         0,
  70946         2,
  70947         soc_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88375_B0r_fields,
  70948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70949         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70950         -1,
  70951         -1,
  70952     },
  70953 #endif /* chips */
  70954 
  70955 #if defined(BCM_88675_B0)
  70956     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88675_B0r */
  70957         soc_block_list[27],
  70958         soc_genreg,
  70959         1,
  70960         0,
  70961         0xb5,
  70962         SOC_REG_FLAG_WO,
  70963         0,
  70964         2,
  70965         soc_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88675_B0r_fields,
  70966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70967         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70968         -1,
  70969         -1,
  70970     },
  70971 #endif /* chips */
  70972 
  70973 #if defined(BCM_88680_A0)
  70974     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88680_A0r */
  70975         soc_block_list[27],
  70976         soc_genreg,
  70977         1,
  70978         0,
  70979         0xb5,
  70980         SOC_REG_FLAG_WO,
  70981         0,
  70982         2,
  70983         soc_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88680_A0r_fields,
  70984         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  70985         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  70986         -1,
  70987         -1,
  70988     },
  70989 #endif /* chips */
  70990 
  70991 #if defined(BCM_88950_A0)
  70992     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_1_T_BCM88950_A0r */
  70993         soc_block_list[27],
  70994         soc_genreg,
  70995         1,
  70996         0,
  70997         0xb5,
  70998         SOC_REG_FLAG_WO,
  70999         0,
  71000         2,
  71001         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  71002         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71003         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71004         -1,
  71005         -1,
  71006     },
  71007 #endif /* chips */
  71008 
  71009 #if defined(BCM_88375_A0)
  71010     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_BCM88375_A0r */
  71011         soc_block_list[27],
  71012         soc_genreg,
  71013         1,
  71014         0,
  71015         0xb6,
  71016         SOC_REG_FLAG_WO,
  71017         0,
  71018         1,
  71019         soc_BRDC_FSRD_RESERVED_PCMI_2_BCM88375_A0r_fields,
  71020         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71021         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71022         -1,
  71023         -1,
  71024     },
  71025 #endif /* chips */
  71026 
  71027 #if defined(BCM_88375_B0)
  71028     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_BCM88375_B0r */
  71029         soc_block_list[27],
  71030         soc_genreg,
  71031         1,
  71032         0,
  71033         0xb6,
  71034         SOC_REG_FLAG_WO,
  71035         0,
  71036         1,
  71037         soc_BRDC_FSRD_RESERVED_PCMI_2_BCM88375_B0r_fields,
  71038         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71039         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71040         -1,
  71041         -1,
  71042     },
  71043 #endif /* chips */
  71044 
  71045 #if defined(BCM_88675_B0)
  71046     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_BCM88675_B0r */
  71047         soc_block_list[27],
  71048         soc_genreg,
  71049         1,
  71050         0,
  71051         0xb6,
  71052         SOC_REG_FLAG_WO,
  71053         0,
  71054         1,
  71055         soc_BRDC_FSRD_RESERVED_PCMI_2_BCM88675_B0r_fields,
  71056         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71057         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71058         -1,
  71059         -1,
  71060     },
  71061 #endif /* chips */
  71062 
  71063 #if defined(BCM_88680_A0)
  71064     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_BCM88680_A0r */
  71065         soc_block_list[27],
  71066         soc_genreg,
  71067         1,
  71068         0,
  71069         0xb6,
  71070         SOC_REG_FLAG_WO,
  71071         0,
  71072         1,
  71073         soc_BRDC_FSRD_RESERVED_PCMI_2_BCM88680_A0r_fields,
  71074         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71075         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71076         -1,
  71077         -1,
  71078     },
  71079 #endif /* chips */
  71080 
  71081 #if defined(BCM_88950_A0)
  71082     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_BCM88950_A0r */
  71083         soc_block_list[27],
  71084         soc_genreg,
  71085         1,
  71086         0,
  71087         0xb6,
  71088         SOC_REG_FLAG_WO,
  71089         0,
  71090         1,
  71091         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  71092         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71093         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71094         -1,
  71095         -1,
  71096     },
  71097 #endif /* chips */
  71098 
  71099 #if defined(BCM_88675_A0)
  71100     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_Sr */
  71101         soc_block_list[27],
  71102         soc_genreg,
  71103         1,
  71104         0,
  71105         0xb7,
  71106         SOC_REG_FLAG_RO |
  71107                           SOC_REG_FLAG_WO,
  71108         0,
  71109         3,
  71110         soc_BRDC_FSRD_RESERVED_PCMI_2_Sr_fields,
  71111         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71112         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71113         -1,
  71114         -1,
  71115     },
  71116 #endif /* chips */
  71117 
  71118 #if defined(BCM_88375_A0)
  71119     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88375_A0r */
  71120         soc_block_list[27],
  71121         soc_genreg,
  71122         1,
  71123         0,
  71124         0xb7,
  71125         SOC_REG_FLAG_RO |
  71126                           SOC_REG_FLAG_WO,
  71127         0,
  71128         3,
  71129         soc_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88375_A0r_fields,
  71130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71132         -1,
  71133         -1,
  71134     },
  71135 #endif /* chips */
  71136 
  71137 #if defined(BCM_88375_B0)
  71138     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88375_B0r */
  71139         soc_block_list[27],
  71140         soc_genreg,
  71141         1,
  71142         0,
  71143         0xb7,
  71144         SOC_REG_FLAG_RO |
  71145                           SOC_REG_FLAG_WO,
  71146         0,
  71147         3,
  71148         soc_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88375_B0r_fields,
  71149         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71150         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71151         -1,
  71152         -1,
  71153     },
  71154 #endif /* chips */
  71155 
  71156 #if defined(BCM_88675_B0)
  71157     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88675_B0r */
  71158         soc_block_list[27],
  71159         soc_genreg,
  71160         1,
  71161         0,
  71162         0xb7,
  71163         SOC_REG_FLAG_RO |
  71164                           SOC_REG_FLAG_WO,
  71165         0,
  71166         3,
  71167         soc_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88675_B0r_fields,
  71168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71169         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71170         -1,
  71171         -1,
  71172     },
  71173 #endif /* chips */
  71174 
  71175 #if defined(BCM_88680_A0)
  71176     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88680_A0r */
  71177         soc_block_list[27],
  71178         soc_genreg,
  71179         1,
  71180         0,
  71181         0xb7,
  71182         SOC_REG_FLAG_RO |
  71183                           SOC_REG_FLAG_WO,
  71184         0,
  71185         3,
  71186         soc_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88680_A0r_fields,
  71187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71188         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71189         -1,
  71190         -1,
  71191     },
  71192 #endif /* chips */
  71193 
  71194 #if defined(BCM_88950_A0)
  71195     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_S_BCM88950_A0r */
  71196         soc_block_list[27],
  71197         soc_genreg,
  71198         1,
  71199         0,
  71200         0xb7,
  71201         SOC_REG_FLAG_RO |
  71202                           SOC_REG_FLAG_WO,
  71203         0,
  71204         3,
  71205         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  71206         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71207         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71208         -1,
  71209         -1,
  71210     },
  71211 #endif /* chips */
  71212 
  71213 #if defined(BCM_88675_A0)
  71214     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_Tr */
  71215         soc_block_list[27],
  71216         soc_genreg,
  71217         1,
  71218         0,
  71219         0xb8,
  71220         SOC_REG_FLAG_WO,
  71221         0,
  71222         2,
  71223         soc_BRDC_FSRD_RESERVED_PCMI_2_Tr_fields,
  71224         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71225         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71226         -1,
  71227         -1,
  71228     },
  71229 #endif /* chips */
  71230 
  71231 #if defined(BCM_88375_A0)
  71232     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88375_A0r */
  71233         soc_block_list[27],
  71234         soc_genreg,
  71235         1,
  71236         0,
  71237         0xb8,
  71238         SOC_REG_FLAG_WO,
  71239         0,
  71240         2,
  71241         soc_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88375_A0r_fields,
  71242         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71243         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71244         -1,
  71245         -1,
  71246     },
  71247 #endif /* chips */
  71248 
  71249 #if defined(BCM_88375_B0)
  71250     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88375_B0r */
  71251         soc_block_list[27],
  71252         soc_genreg,
  71253         1,
  71254         0,
  71255         0xb8,
  71256         SOC_REG_FLAG_WO,
  71257         0,
  71258         2,
  71259         soc_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88375_B0r_fields,
  71260         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71261         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71262         -1,
  71263         -1,
  71264     },
  71265 #endif /* chips */
  71266 
  71267 #if defined(BCM_88675_B0)
  71268     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88675_B0r */
  71269         soc_block_list[27],
  71270         soc_genreg,
  71271         1,
  71272         0,
  71273         0xb8,
  71274         SOC_REG_FLAG_WO,
  71275         0,
  71276         2,
  71277         soc_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88675_B0r_fields,
  71278         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71279         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71280         -1,
  71281         -1,
  71282     },
  71283 #endif /* chips */
  71284 
  71285 #if defined(BCM_88680_A0)
  71286     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88680_A0r */
  71287         soc_block_list[27],
  71288         soc_genreg,
  71289         1,
  71290         0,
  71291         0xb8,
  71292         SOC_REG_FLAG_WO,
  71293         0,
  71294         2,
  71295         soc_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88680_A0r_fields,
  71296         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71297         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71298         -1,
  71299         -1,
  71300     },
  71301 #endif /* chips */
  71302 
  71303 #if defined(BCM_88950_A0)
  71304     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_2_T_BCM88950_A0r */
  71305         soc_block_list[27],
  71306         soc_genreg,
  71307         1,
  71308         0,
  71309         0xb8,
  71310         SOC_REG_FLAG_WO,
  71311         0,
  71312         2,
  71313         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  71314         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71315         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71316         -1,
  71317         -1,
  71318     },
  71319 #endif /* chips */
  71320 
  71321 #if defined(BCM_88375_A0)
  71322     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_BCM88375_A0r */
  71323         soc_block_list[27],
  71324         soc_genreg,
  71325         1,
  71326         0,
  71327         0xbc,
  71328         SOC_REG_FLAG_WO,
  71329         0,
  71330         1,
  71331         soc_BRDC_FSRD_RESERVED_PCMI_4_BCM88375_A0r_fields,
  71332         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71333         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71334         -1,
  71335         -1,
  71336     },
  71337 #endif /* chips */
  71338 
  71339 #if defined(BCM_88375_B0)
  71340     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_BCM88375_B0r */
  71341         soc_block_list[27],
  71342         soc_genreg,
  71343         1,
  71344         0,
  71345         0xbc,
  71346         SOC_REG_FLAG_WO,
  71347         0,
  71348         1,
  71349         soc_BRDC_FSRD_RESERVED_PCMI_4_BCM88375_B0r_fields,
  71350         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71351         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71352         -1,
  71353         -1,
  71354     },
  71355 #endif /* chips */
  71356 
  71357 #if defined(BCM_88675_B0)
  71358     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_BCM88675_B0r */
  71359         soc_block_list[27],
  71360         soc_genreg,
  71361         1,
  71362         0,
  71363         0xbc,
  71364         SOC_REG_FLAG_WO,
  71365         0,
  71366         1,
  71367         soc_BRDC_FSRD_RESERVED_PCMI_4_BCM88675_B0r_fields,
  71368         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71369         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71370         -1,
  71371         -1,
  71372     },
  71373 #endif /* chips */
  71374 
  71375 #if defined(BCM_88680_A0)
  71376     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_BCM88680_A0r */
  71377         soc_block_list[27],
  71378         soc_genreg,
  71379         1,
  71380         0,
  71381         0xbc,
  71382         SOC_REG_FLAG_WO,
  71383         0,
  71384         1,
  71385         soc_BRDC_FSRD_RESERVED_PCMI_4_BCM88680_A0r_fields,
  71386         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71387         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71388         -1,
  71389         -1,
  71390     },
  71391 #endif /* chips */
  71392 
  71393 #if defined(BCM_88950_A0)
  71394     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_BCM88950_A0r */
  71395         soc_block_list[27],
  71396         soc_genreg,
  71397         1,
  71398         0,
  71399         0xbc,
  71400         SOC_REG_FLAG_WO,
  71401         0,
  71402         1,
  71403         soc_BRDC_DCH_RESERVED_PCMI_2r_fields,
  71404         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  71405         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71406         -1,
  71407         -1,
  71408     },
  71409 #endif /* chips */
  71410 
  71411 #if defined(BCM_88675_A0)
  71412     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_Sr */
  71413         soc_block_list[27],
  71414         soc_genreg,
  71415         1,
  71416         0,
  71417         0xbd,
  71418         SOC_REG_FLAG_RO |
  71419                           SOC_REG_FLAG_WO,
  71420         0,
  71421         3,
  71422         soc_BRDC_FSRD_RESERVED_PCMI_4_Sr_fields,
  71423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71424         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71425         -1,
  71426         -1,
  71427     },
  71428 #endif /* chips */
  71429 
  71430 #if defined(BCM_88375_A0)
  71431     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88375_A0r */
  71432         soc_block_list[27],
  71433         soc_genreg,
  71434         1,
  71435         0,
  71436         0xbd,
  71437         SOC_REG_FLAG_RO |
  71438                           SOC_REG_FLAG_WO,
  71439         0,
  71440         3,
  71441         soc_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88375_A0r_fields,
  71442         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71443         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71444         -1,
  71445         -1,
  71446     },
  71447 #endif /* chips */
  71448 
  71449 #if defined(BCM_88375_B0)
  71450     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88375_B0r */
  71451         soc_block_list[27],
  71452         soc_genreg,
  71453         1,
  71454         0,
  71455         0xbd,
  71456         SOC_REG_FLAG_RO |
  71457                           SOC_REG_FLAG_WO,
  71458         0,
  71459         3,
  71460         soc_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88375_B0r_fields,
  71461         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71462         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71463         -1,
  71464         -1,
  71465     },
  71466 #endif /* chips */
  71467 
  71468 #if defined(BCM_88675_B0)
  71469     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88675_B0r */
  71470         soc_block_list[27],
  71471         soc_genreg,
  71472         1,
  71473         0,
  71474         0xbd,
  71475         SOC_REG_FLAG_RO |
  71476                           SOC_REG_FLAG_WO,
  71477         0,
  71478         3,
  71479         soc_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88675_B0r_fields,
  71480         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71481         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71482         -1,
  71483         -1,
  71484     },
  71485 #endif /* chips */
  71486 
  71487 #if defined(BCM_88680_A0)
  71488     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88680_A0r */
  71489         soc_block_list[27],
  71490         soc_genreg,
  71491         1,
  71492         0,
  71493         0xbd,
  71494         SOC_REG_FLAG_RO |
  71495                           SOC_REG_FLAG_WO,
  71496         0,
  71497         3,
  71498         soc_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88680_A0r_fields,
  71499         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71500         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71501         -1,
  71502         -1,
  71503     },
  71504 #endif /* chips */
  71505 
  71506 #if defined(BCM_88950_A0)
  71507     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_S_BCM88950_A0r */
  71508         soc_block_list[27],
  71509         soc_genreg,
  71510         1,
  71511         0,
  71512         0xbd,
  71513         SOC_REG_FLAG_RO |
  71514                           SOC_REG_FLAG_WO,
  71515         0,
  71516         3,
  71517         soc_BRDC_DCH_RESERVED_PCMI_2_Sr_fields,
  71518         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71519         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71520         -1,
  71521         -1,
  71522     },
  71523 #endif /* chips */
  71524 
  71525 #if defined(BCM_88675_A0)
  71526     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_Tr */
  71527         soc_block_list[27],
  71528         soc_genreg,
  71529         1,
  71530         0,
  71531         0xbe,
  71532         SOC_REG_FLAG_WO,
  71533         0,
  71534         2,
  71535         soc_BRDC_FSRD_RESERVED_PCMI_4_Tr_fields,
  71536         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71537         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71538         -1,
  71539         -1,
  71540     },
  71541 #endif /* chips */
  71542 
  71543 #if defined(BCM_88375_A0)
  71544     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88375_A0r */
  71545         soc_block_list[27],
  71546         soc_genreg,
  71547         1,
  71548         0,
  71549         0xbe,
  71550         SOC_REG_FLAG_WO,
  71551         0,
  71552         2,
  71553         soc_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88375_A0r_fields,
  71554         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71555         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71556         -1,
  71557         -1,
  71558     },
  71559 #endif /* chips */
  71560 
  71561 #if defined(BCM_88375_B0)
  71562     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88375_B0r */
  71563         soc_block_list[27],
  71564         soc_genreg,
  71565         1,
  71566         0,
  71567         0xbe,
  71568         SOC_REG_FLAG_WO,
  71569         0,
  71570         2,
  71571         soc_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88375_B0r_fields,
  71572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71573         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71574         -1,
  71575         -1,
  71576     },
  71577 #endif /* chips */
  71578 
  71579 #if defined(BCM_88675_B0)
  71580     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88675_B0r */
  71581         soc_block_list[27],
  71582         soc_genreg,
  71583         1,
  71584         0,
  71585         0xbe,
  71586         SOC_REG_FLAG_WO,
  71587         0,
  71588         2,
  71589         soc_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88675_B0r_fields,
  71590         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71591         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71592         -1,
  71593         -1,
  71594     },
  71595 #endif /* chips */
  71596 
  71597 #if defined(BCM_88680_A0)
  71598     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88680_A0r */
  71599         soc_block_list[27],
  71600         soc_genreg,
  71601         1,
  71602         0,
  71603         0xbe,
  71604         SOC_REG_FLAG_WO,
  71605         0,
  71606         2,
  71607         soc_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88680_A0r_fields,
  71608         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71609         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71610         -1,
  71611         -1,
  71612     },
  71613 #endif /* chips */
  71614 
  71615 #if defined(BCM_88950_A0)
  71616     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_PCMI_4_T_BCM88950_A0r */
  71617         soc_block_list[27],
  71618         soc_genreg,
  71619         1,
  71620         0,
  71621         0xbe,
  71622         SOC_REG_FLAG_WO,
  71623         0,
  71624         2,
  71625         soc_BRDC_DCH_RESERVED_PCMI_2_Tr_fields,
  71626         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71627         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  71628         -1,
  71629         -1,
  71630     },
  71631 #endif /* chips */
  71632 
  71633 #if defined(BCM_88675_A0)
  71634     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0r */
  71635         soc_block_list[27],
  71636         soc_genreg,
  71637         1,
  71638         0,
  71639         0x90,
  71640         SOC_REG_FLAG_WO,
  71641         0,
  71642         1,
  71643         soc_BRDC_FSRD_RESERVED_SPARE_0r_fields,
  71644         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71645         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71646         -1,
  71647         -1,
  71648     },
  71649 #endif /* chips */
  71650 
  71651 #if defined(BCM_88675_A0)
  71652     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1r */
  71653         soc_block_list[27],
  71654         soc_genreg,
  71655         1,
  71656         0,
  71657         0x91,
  71658         SOC_REG_FLAG_WO,
  71659         0,
  71660         1,
  71661         soc_BRDC_FSRD_RESERVED_SPARE_1r_fields,
  71662         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71663         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71664         -1,
  71665         -1,
  71666     },
  71667 #endif /* chips */
  71668 
  71669 #if defined(BCM_88675_A0)
  71670     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2r */
  71671         soc_block_list[27],
  71672         soc_genreg,
  71673         1,
  71674         0,
  71675         0x92,
  71676         SOC_REG_FLAG_WO,
  71677         0,
  71678         1,
  71679         soc_BRDC_FSRD_RESERVED_SPARE_2r_fields,
  71680         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71681         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71682         -1,
  71683         -1,
  71684     },
  71685 #endif /* chips */
  71686 
  71687 #if defined(BCM_88675_A0)
  71688     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3r */
  71689         soc_block_list[27],
  71690         soc_genreg,
  71691         1,
  71692         0,
  71693         0x93,
  71694         SOC_REG_FLAG_WO,
  71695         0,
  71696         1,
  71697         soc_BRDC_FSRD_RESERVED_SPARE_3r_fields,
  71698         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  71699         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71700         -1,
  71701         -1,
  71702     },
  71703 #endif /* chips */
  71704 
  71705 #if defined(BCM_88375_A0)
  71706     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88375_A0r */
  71707         soc_block_list[27],
  71708         soc_genreg,
  71709         1,
  71710         0,
  71711         0x90,
  71712         SOC_REG_FLAG_WO,
  71713         0,
  71714         1,
  71715         soc_BRDC_FSRD_RESERVED_SPARE_0_BCM88375_A0r_fields,
  71716         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71717         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71718         -1,
  71719         -1,
  71720     },
  71721 #endif /* chips */
  71722 
  71723 #if defined(BCM_88375_B0)
  71724     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88375_B0r */
  71725         soc_block_list[27],
  71726         soc_genreg,
  71727         1,
  71728         0,
  71729         0x90,
  71730         SOC_REG_FLAG_WO,
  71731         0,
  71732         1,
  71733         soc_BRDC_FSRD_RESERVED_SPARE_0_BCM88375_B0r_fields,
  71734         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71735         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71736         -1,
  71737         -1,
  71738     },
  71739 #endif /* chips */
  71740 
  71741 #if defined(BCM_88675_B0)
  71742     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88675_B0r */
  71743         soc_block_list[27],
  71744         soc_genreg,
  71745         1,
  71746         0,
  71747         0x90,
  71748         SOC_REG_FLAG_WO,
  71749         0,
  71750         1,
  71751         soc_BRDC_FSRD_RESERVED_SPARE_0_BCM88675_B0r_fields,
  71752         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71753         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71754         -1,
  71755         -1,
  71756     },
  71757 #endif /* chips */
  71758 
  71759 #if defined(BCM_88680_A0)
  71760     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88680_A0r */
  71761         soc_block_list[27],
  71762         soc_genreg,
  71763         1,
  71764         0,
  71765         0x90,
  71766         SOC_REG_FLAG_WO,
  71767         0,
  71768         1,
  71769         soc_BRDC_FSRD_RESERVED_SPARE_0_BCM88680_A0r_fields,
  71770         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71771         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71772         -1,
  71773         -1,
  71774     },
  71775 #endif /* chips */
  71776 
  71777 #if defined(BCM_88690_A0)
  71778     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88690_A0r */
  71779         soc_block_list[27],
  71780         soc_genreg,
  71781         1,
  71782         0,
  71783         0x90,
  71784         SOC_REG_FLAG_WO,
  71785         0,
  71786         1,
  71787         soc_BRDC_FSRD_RESERVED_SPARE_0_BCM88690_A0r_fields,
  71788         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71789         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71790         -1,
  71791         -1,
  71792     },
  71793 #endif /* chips */
  71794 
  71795 #if defined(BCM_88690_B0)
  71796     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88690_B0r */
  71797         soc_block_list[27],
  71798         soc_genreg,
  71799         1,
  71800         0,
  71801         0x90,
  71802         SOC_REG_FLAG_WO,
  71803         0,
  71804         1,
  71805         soc_BRDC_FSRD_RESERVED_SPARE_0_BCM88690_B0r_fields,
  71806         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71807         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71808         -1,
  71809         -1,
  71810     },
  71811 #endif /* chips */
  71812 
  71813 #if defined(BCM_88790_A0)
  71814     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88790_A0r */
  71815         soc_block_list[27],
  71816         soc_genreg,
  71817         1,
  71818         0,
  71819         0x90,
  71820         SOC_REG_FLAG_WO,
  71821         0,
  71822         1,
  71823         soc_BRDC_FSRD_RESERVED_SPARE_0_BCM88790_A0r_fields,
  71824         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71825         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71826         -1,
  71827         -1,
  71828     },
  71829 #endif /* chips */
  71830 
  71831 #if defined(BCM_88950_A0)
  71832     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_0_BCM88950_A0r */
  71833         soc_block_list[27],
  71834         soc_genreg,
  71835         1,
  71836         0,
  71837         0x90,
  71838         SOC_REG_FLAG_WO,
  71839         0,
  71840         1,
  71841         soc_BRDC_CCS_RESERVED_SPARE_0r_fields,
  71842         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71843         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71844         -1,
  71845         -1,
  71846     },
  71847 #endif /* chips */
  71848 
  71849 #if defined(BCM_88375_A0)
  71850     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88375_A0r */
  71851         soc_block_list[27],
  71852         soc_genreg,
  71853         1,
  71854         0,
  71855         0x91,
  71856         SOC_REG_FLAG_WO,
  71857         0,
  71858         1,
  71859         soc_BRDC_FSRD_RESERVED_SPARE_1_BCM88375_A0r_fields,
  71860         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71861         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71862         -1,
  71863         -1,
  71864     },
  71865 #endif /* chips */
  71866 
  71867 #if defined(BCM_88375_B0)
  71868     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88375_B0r */
  71869         soc_block_list[27],
  71870         soc_genreg,
  71871         1,
  71872         0,
  71873         0x91,
  71874         SOC_REG_FLAG_WO,
  71875         0,
  71876         1,
  71877         soc_BRDC_FSRD_RESERVED_SPARE_1_BCM88375_B0r_fields,
  71878         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71879         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71880         -1,
  71881         -1,
  71882     },
  71883 #endif /* chips */
  71884 
  71885 #if defined(BCM_88675_B0)
  71886     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88675_B0r */
  71887         soc_block_list[27],
  71888         soc_genreg,
  71889         1,
  71890         0,
  71891         0x91,
  71892         SOC_REG_FLAG_WO,
  71893         0,
  71894         1,
  71895         soc_BRDC_FSRD_RESERVED_SPARE_1_BCM88675_B0r_fields,
  71896         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71897         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71898         -1,
  71899         -1,
  71900     },
  71901 #endif /* chips */
  71902 
  71903 #if defined(BCM_88680_A0)
  71904     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88680_A0r */
  71905         soc_block_list[27],
  71906         soc_genreg,
  71907         1,
  71908         0,
  71909         0x91,
  71910         SOC_REG_FLAG_WO,
  71911         0,
  71912         1,
  71913         soc_BRDC_FSRD_RESERVED_SPARE_1_BCM88680_A0r_fields,
  71914         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71915         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71916         -1,
  71917         -1,
  71918     },
  71919 #endif /* chips */
  71920 
  71921 #if defined(BCM_88690_A0)
  71922     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88690_A0r */
  71923         soc_block_list[27],
  71924         soc_genreg,
  71925         1,
  71926         0,
  71927         0x91,
  71928         SOC_REG_FLAG_WO,
  71929         0,
  71930         1,
  71931         soc_BRDC_FSRD_RESERVED_SPARE_1_BCM88690_A0r_fields,
  71932         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71933         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71934         -1,
  71935         -1,
  71936     },
  71937 #endif /* chips */
  71938 
  71939 #if defined(BCM_88690_B0)
  71940     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88690_B0r */
  71941         soc_block_list[27],
  71942         soc_genreg,
  71943         1,
  71944         0,
  71945         0x91,
  71946         SOC_REG_FLAG_WO,
  71947         0,
  71948         1,
  71949         soc_BRDC_FSRD_RESERVED_SPARE_1_BCM88690_B0r_fields,
  71950         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71951         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71952         -1,
  71953         -1,
  71954     },
  71955 #endif /* chips */
  71956 
  71957 #if defined(BCM_88790_A0)
  71958     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88790_A0r */
  71959         soc_block_list[27],
  71960         soc_genreg,
  71961         1,
  71962         0,
  71963         0x91,
  71964         SOC_REG_FLAG_WO,
  71965         0,
  71966         1,
  71967         soc_BRDC_FSRD_RESERVED_SPARE_1_BCM88790_A0r_fields,
  71968         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71969         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71970         -1,
  71971         -1,
  71972     },
  71973 #endif /* chips */
  71974 
  71975 #if defined(BCM_88950_A0)
  71976     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_1_BCM88950_A0r */
  71977         soc_block_list[27],
  71978         soc_genreg,
  71979         1,
  71980         0,
  71981         0x91,
  71982         SOC_REG_FLAG_WO,
  71983         0,
  71984         1,
  71985         soc_BRDC_CCS_RESERVED_SPARE_1r_fields,
  71986         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  71987         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  71988         -1,
  71989         -1,
  71990     },
  71991 #endif /* chips */
  71992 
  71993 #if defined(BCM_88375_A0)
  71994     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88375_A0r */
  71995         soc_block_list[27],
  71996         soc_genreg,
  71997         1,
  71998         0,
  71999         0x92,
  72000         SOC_REG_FLAG_WO,
  72001         0,
  72002         1,
  72003         soc_BRDC_FSRD_RESERVED_SPARE_2_BCM88375_A0r_fields,
  72004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72006         -1,
  72007         -1,
  72008     },
  72009 #endif /* chips */
  72010 
  72011 #if defined(BCM_88375_B0)
  72012     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88375_B0r */
  72013         soc_block_list[27],
  72014         soc_genreg,
  72015         1,
  72016         0,
  72017         0x92,
  72018         SOC_REG_FLAG_WO,
  72019         0,
  72020         1,
  72021         soc_BRDC_FSRD_RESERVED_SPARE_2_BCM88375_B0r_fields,
  72022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72023         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72024         -1,
  72025         -1,
  72026     },
  72027 #endif /* chips */
  72028 
  72029 #if defined(BCM_88675_B0)
  72030     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88675_B0r */
  72031         soc_block_list[27],
  72032         soc_genreg,
  72033         1,
  72034         0,
  72035         0x92,
  72036         SOC_REG_FLAG_WO,
  72037         0,
  72038         1,
  72039         soc_BRDC_FSRD_RESERVED_SPARE_2_BCM88675_B0r_fields,
  72040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72041         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72042         -1,
  72043         -1,
  72044     },
  72045 #endif /* chips */
  72046 
  72047 #if defined(BCM_88680_A0)
  72048     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88680_A0r */
  72049         soc_block_list[27],
  72050         soc_genreg,
  72051         1,
  72052         0,
  72053         0x92,
  72054         SOC_REG_FLAG_WO,
  72055         0,
  72056         1,
  72057         soc_BRDC_FSRD_RESERVED_SPARE_2_BCM88680_A0r_fields,
  72058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72059         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72060         -1,
  72061         -1,
  72062     },
  72063 #endif /* chips */
  72064 
  72065 #if defined(BCM_88690_A0)
  72066     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88690_A0r */
  72067         soc_block_list[27],
  72068         soc_genreg,
  72069         1,
  72070         0,
  72071         0x92,
  72072         SOC_REG_FLAG_WO,
  72073         0,
  72074         1,
  72075         soc_BRDC_FSRD_RESERVED_SPARE_2_BCM88690_A0r_fields,
  72076         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72077         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72078         -1,
  72079         -1,
  72080     },
  72081 #endif /* chips */
  72082 
  72083 #if defined(BCM_88690_B0)
  72084     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88690_B0r */
  72085         soc_block_list[27],
  72086         soc_genreg,
  72087         1,
  72088         0,
  72089         0x92,
  72090         SOC_REG_FLAG_WO,
  72091         0,
  72092         1,
  72093         soc_BRDC_FSRD_RESERVED_SPARE_2_BCM88690_B0r_fields,
  72094         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72095         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72096         -1,
  72097         -1,
  72098     },
  72099 #endif /* chips */
  72100 
  72101 #if defined(BCM_88790_A0)
  72102     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88790_A0r */
  72103         soc_block_list[27],
  72104         soc_genreg,
  72105         1,
  72106         0,
  72107         0x92,
  72108         SOC_REG_FLAG_WO,
  72109         0,
  72110         1,
  72111         soc_BRDC_FSRD_RESERVED_SPARE_2_BCM88790_A0r_fields,
  72112         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72113         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72114         -1,
  72115         -1,
  72116     },
  72117 #endif /* chips */
  72118 
  72119 #if defined(BCM_88950_A0)
  72120     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_2_BCM88950_A0r */
  72121         soc_block_list[27],
  72122         soc_genreg,
  72123         1,
  72124         0,
  72125         0x92,
  72126         SOC_REG_FLAG_WO,
  72127         0,
  72128         1,
  72129         soc_BRDC_CCS_RESERVED_SPARE_2r_fields,
  72130         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72131         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72132         -1,
  72133         -1,
  72134     },
  72135 #endif /* chips */
  72136 
  72137 #if defined(BCM_88375_A0)
  72138     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88375_A0r */
  72139         soc_block_list[27],
  72140         soc_genreg,
  72141         1,
  72142         0,
  72143         0x93,
  72144         SOC_REG_FLAG_WO,
  72145         0,
  72146         1,
  72147         soc_BRDC_FSRD_RESERVED_SPARE_3_BCM88375_A0r_fields,
  72148         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72149         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72150         -1,
  72151         -1,
  72152     },
  72153 #endif /* chips */
  72154 
  72155 #if defined(BCM_88375_B0)
  72156     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88375_B0r */
  72157         soc_block_list[27],
  72158         soc_genreg,
  72159         1,
  72160         0,
  72161         0x93,
  72162         SOC_REG_FLAG_WO,
  72163         0,
  72164         1,
  72165         soc_BRDC_FSRD_RESERVED_SPARE_3_BCM88375_B0r_fields,
  72166         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72167         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72168         -1,
  72169         -1,
  72170     },
  72171 #endif /* chips */
  72172 
  72173 #if defined(BCM_88675_B0)
  72174     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88675_B0r */
  72175         soc_block_list[27],
  72176         soc_genreg,
  72177         1,
  72178         0,
  72179         0x93,
  72180         SOC_REG_FLAG_WO,
  72181         0,
  72182         1,
  72183         soc_BRDC_FSRD_RESERVED_SPARE_3_BCM88675_B0r_fields,
  72184         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72185         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72186         -1,
  72187         -1,
  72188     },
  72189 #endif /* chips */
  72190 
  72191 #if defined(BCM_88680_A0)
  72192     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88680_A0r */
  72193         soc_block_list[27],
  72194         soc_genreg,
  72195         1,
  72196         0,
  72197         0x93,
  72198         SOC_REG_FLAG_WO,
  72199         0,
  72200         1,
  72201         soc_BRDC_FSRD_RESERVED_SPARE_3_BCM88680_A0r_fields,
  72202         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72203         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72204         -1,
  72205         -1,
  72206     },
  72207 #endif /* chips */
  72208 
  72209 #if defined(BCM_88690_A0)
  72210     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88690_A0r */
  72211         soc_block_list[27],
  72212         soc_genreg,
  72213         1,
  72214         0,
  72215         0x93,
  72216         SOC_REG_FLAG_WO,
  72217         0,
  72218         1,
  72219         soc_BRDC_FSRD_RESERVED_SPARE_3_BCM88690_A0r_fields,
  72220         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72221         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72222         -1,
  72223         -1,
  72224     },
  72225 #endif /* chips */
  72226 
  72227 #if defined(BCM_88690_B0)
  72228     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88690_B0r */
  72229         soc_block_list[27],
  72230         soc_genreg,
  72231         1,
  72232         0,
  72233         0x93,
  72234         SOC_REG_FLAG_WO,
  72235         0,
  72236         1,
  72237         soc_BRDC_FSRD_RESERVED_SPARE_3_BCM88690_B0r_fields,
  72238         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72239         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72240         -1,
  72241         -1,
  72242     },
  72243 #endif /* chips */
  72244 
  72245 #if defined(BCM_88790_A0)
  72246     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88790_A0r */
  72247         soc_block_list[27],
  72248         soc_genreg,
  72249         1,
  72250         0,
  72251         0x93,
  72252         SOC_REG_FLAG_WO,
  72253         0,
  72254         1,
  72255         soc_BRDC_FSRD_RESERVED_SPARE_3_BCM88790_A0r_fields,
  72256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72257         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72258         -1,
  72259         -1,
  72260     },
  72261 #endif /* chips */
  72262 
  72263 #if defined(BCM_88950_A0)
  72264     { /* SOC_REG_INT_BRDC_FSRD_RESERVED_SPARE_3_BCM88950_A0r */
  72265         soc_block_list[27],
  72266         soc_genreg,
  72267         1,
  72268         0,
  72269         0x93,
  72270         SOC_REG_FLAG_WO,
  72271         0,
  72272         1,
  72273         soc_BRDC_CCS_RESERVED_SPARE_3r_fields,
  72274         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72275         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  72276         -1,
  72277         -1,
  72278     },
  72279 #endif /* chips */
  72280 
  72281 #if defined(BCM_88675_A0)
  72282     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIGr */
  72283         soc_block_list[27],
  72284         soc_genreg,
  72285         1,
  72286         0,
  72287         0x202,
  72288         SOC_REG_FLAG_WO,
  72289         0,
  72290         8,
  72291         soc_BRDC_FSRD_RES_CAL_CONFIGr_fields,
  72292         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72293         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  72294         -1,
  72295         -1,
  72296     },
  72297 #endif /* chips */
  72298 
  72299 #if defined(BCM_88375_A0)
  72300     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88375_A0r */
  72301         soc_block_list[27],
  72302         soc_genreg,
  72303         1,
  72304         0,
  72305         0x202,
  72306         SOC_REG_FLAG_WO,
  72307         0,
  72308         8,
  72309         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88375_A0r_fields,
  72310         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72311         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  72312         -1,
  72313         -1,
  72314     },
  72315 #endif /* chips */
  72316 
  72317 #if defined(BCM_88375_B0)
  72318     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88375_B0r */
  72319         soc_block_list[27],
  72320         soc_genreg,
  72321         1,
  72322         0,
  72323         0x202,
  72324         SOC_REG_FLAG_WO,
  72325         0,
  72326         8,
  72327         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88375_B0r_fields,
  72328         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72329         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  72330         -1,
  72331         -1,
  72332     },
  72333 #endif /* chips */
  72334 
  72335 #if defined(BCM_88675_B0)
  72336     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88675_B0r */
  72337         soc_block_list[27],
  72338         soc_genreg,
  72339         1,
  72340         0,
  72341         0x202,
  72342         SOC_REG_FLAG_WO,
  72343         0,
  72344         8,
  72345         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88675_B0r_fields,
  72346         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72347         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  72348         -1,
  72349         -1,
  72350     },
  72351 #endif /* chips */
  72352 
  72353 #if defined(BCM_88680_A0)
  72354     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88680_A0r */
  72355         soc_block_list[27],
  72356         soc_genreg,
  72357         1,
  72358         0,
  72359         0x202,
  72360         SOC_REG_FLAG_WO,
  72361         0,
  72362         8,
  72363         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88680_A0r_fields,
  72364         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72365         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  72366         -1,
  72367         -1,
  72368     },
  72369 #endif /* chips */
  72370 
  72371 #if defined(BCM_88690_A0)
  72372     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88690_A0r */
  72373         soc_block_list[27],
  72374         soc_genreg,
  72375         1,
  72376         0,
  72377         0x10e,
  72378         SOC_REG_FLAG_64_BITS |
  72379                           SOC_REG_FLAG_WO,
  72380         0,
  72381         8,
  72382         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88690_A0r_fields,
  72383         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72384         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  72385         -1,
  72386         -1,
  72387     },
  72388 #endif /* chips */
  72389 
  72390 #if defined(BCM_88690_B0)
  72391     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88690_B0r */
  72392         soc_block_list[27],
  72393         soc_genreg,
  72394         1,
  72395         0,
  72396         0x10e,
  72397         SOC_REG_FLAG_64_BITS |
  72398                           SOC_REG_FLAG_WO,
  72399         0,
  72400         8,
  72401         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88690_B0r_fields,
  72402         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72403         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  72404         -1,
  72405         -1,
  72406     },
  72407 #endif /* chips */
  72408 
  72409 #if defined(BCM_88790_A0)
  72410     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88790_A0r */
  72411         soc_block_list[27],
  72412         soc_genreg,
  72413         1,
  72414         0,
  72415         0x10e,
  72416         SOC_REG_FLAG_64_BITS |
  72417                           SOC_REG_FLAG_WO,
  72418         0,
  72419         8,
  72420         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88790_A0r_fields,
  72421         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72422         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  72423         -1,
  72424         -1,
  72425     },
  72426 #endif /* chips */
  72427 
  72428 #if defined(BCM_88950_A0)
  72429     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CONFIG_BCM88950_A0r */
  72430         soc_block_list[27],
  72431         soc_genreg,
  72432         1,
  72433         0,
  72434         0x202,
  72435         SOC_REG_FLAG_WO,
  72436         0,
  72437         8,
  72438         soc_BRDC_FSRD_RES_CAL_CONFIG_BCM88950_A0r_fields,
  72439         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  72440         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  72441         -1,
  72442         -1,
  72443     },
  72444 #endif /* chips */
  72445 
  72446 #if defined(BCM_88202_A0)
  72447     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_CPU_OVERRIDE_REGISTERr */
  72448         soc_block_list[27],
  72449         soc_genreg,
  72450         1,
  72451         0,
  72452         0x282,
  72453         SOC_REG_FLAG_WO,
  72454         0,
  72455         6,
  72456         soc_BRDC_FSRD_RES_CAL_CPU_OVERRIDE_REGISTERr_fields,
  72457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72458         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  72459         -1,
  72460         -1,
  72461     },
  72462 #endif /* chips */
  72463 
  72464 #if defined(BCM_88202_A0)
  72465     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUSr */
  72466         soc_block_list[27],
  72467         soc_genreg,
  72468         1,
  72469         0,
  72470         0x283,
  72471         SOC_REG_FLAG_WO,
  72472         0,
  72473         3,
  72474         soc_BRDC_FSRD_RES_CAL_STATUSr_fields,
  72475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72476         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  72477         -1,
  72478         -1,
  72479     },
  72480 #endif /* chips */
  72481 
  72482 #if defined(BCM_88375_A0)
  72483     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88375_A0r */
  72484         soc_block_list[27],
  72485         soc_genreg,
  72486         1,
  72487         0,
  72488         0x203,
  72489         SOC_REG_FLAG_64_BITS |
  72490                           SOC_REG_FLAG_RO |
  72491                           SOC_REG_FLAG_WO,
  72492         0,
  72493         8,
  72494         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88375_A0r_fields,
  72495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72496         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  72497         -1,
  72498         -1,
  72499     },
  72500 #endif /* chips */
  72501 
  72502 #if defined(BCM_88375_B0)
  72503     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88375_B0r */
  72504         soc_block_list[27],
  72505         soc_genreg,
  72506         1,
  72507         0,
  72508         0x203,
  72509         SOC_REG_FLAG_64_BITS |
  72510                           SOC_REG_FLAG_RO |
  72511                           SOC_REG_FLAG_WO,
  72512         0,
  72513         8,
  72514         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88375_B0r_fields,
  72515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72516         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  72517         -1,
  72518         -1,
  72519     },
  72520 #endif /* chips */
  72521 
  72522 #if defined(BCM_88675_A0)
  72523     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88675_A0r */
  72524         soc_block_list[27],
  72525         soc_genreg,
  72526         1,
  72527         0,
  72528         0x203,
  72529         SOC_REG_FLAG_64_BITS |
  72530                           SOC_REG_FLAG_RO |
  72531                           SOC_REG_FLAG_WO,
  72532         0,
  72533         8,
  72534         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88675_A0r_fields,
  72535         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72536         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  72537         -1,
  72538         -1,
  72539     },
  72540 #endif /* chips */
  72541 
  72542 #if defined(BCM_88675_B0)
  72543     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88675_B0r */
  72544         soc_block_list[27],
  72545         soc_genreg,
  72546         1,
  72547         0,
  72548         0x203,
  72549         SOC_REG_FLAG_64_BITS |
  72550                           SOC_REG_FLAG_RO |
  72551                           SOC_REG_FLAG_WO,
  72552         0,
  72553         8,
  72554         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88675_B0r_fields,
  72555         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72556         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  72557         -1,
  72558         -1,
  72559     },
  72560 #endif /* chips */
  72561 
  72562 #if defined(BCM_88680_A0)
  72563     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88680_A0r */
  72564         soc_block_list[27],
  72565         soc_genreg,
  72566         1,
  72567         0,
  72568         0x203,
  72569         SOC_REG_FLAG_64_BITS |
  72570                           SOC_REG_FLAG_RO |
  72571                           SOC_REG_FLAG_WO,
  72572         0,
  72573         8,
  72574         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88680_A0r_fields,
  72575         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72576         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  72577         -1,
  72578         -1,
  72579     },
  72580 #endif /* chips */
  72581 
  72582 #if defined(BCM_88690_A0)
  72583     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88690_A0r */
  72584         soc_block_list[27],
  72585         soc_genreg,
  72586         1,
  72587         0,
  72588         0x110,
  72589         SOC_REG_FLAG_64_BITS |
  72590                           SOC_REG_FLAG_RO |
  72591                           SOC_REG_FLAG_WO,
  72592         0,
  72593         9,
  72594         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88690_A0r_fields,
  72595         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72596         SOC_RESET_MASK_DEC(0xffffffff, 0x0003ffff)
  72597         -1,
  72598         -1,
  72599     },
  72600 #endif /* chips */
  72601 
  72602 #if defined(BCM_88690_B0)
  72603     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88690_B0r */
  72604         soc_block_list[27],
  72605         soc_genreg,
  72606         1,
  72607         0,
  72608         0x110,
  72609         SOC_REG_FLAG_64_BITS |
  72610                           SOC_REG_FLAG_RO |
  72611                           SOC_REG_FLAG_WO,
  72612         0,
  72613         9,
  72614         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88690_B0r_fields,
  72615         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72616         SOC_RESET_MASK_DEC(0xffffffff, 0x0003ffff)
  72617         -1,
  72618         -1,
  72619     },
  72620 #endif /* chips */
  72621 
  72622 #if defined(BCM_88790_A0)
  72623     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88790_A0r */
  72624         soc_block_list[27],
  72625         soc_genreg,
  72626         1,
  72627         0,
  72628         0x110,
  72629         SOC_REG_FLAG_64_BITS |
  72630                           SOC_REG_FLAG_RO |
  72631                           SOC_REG_FLAG_WO,
  72632         0,
  72633         9,
  72634         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88790_A0r_fields,
  72635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72636         SOC_RESET_MASK_DEC(0xffffffff, 0x0003ffff)
  72637         -1,
  72638         -1,
  72639     },
  72640 #endif /* chips */
  72641 
  72642 #if defined(BCM_88950_A0)
  72643     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STATUS_BCM88950_A0r */
  72644         soc_block_list[27],
  72645         soc_genreg,
  72646         1,
  72647         0,
  72648         0x203,
  72649         SOC_REG_FLAG_64_BITS |
  72650                           SOC_REG_FLAG_RO |
  72651                           SOC_REG_FLAG_WO,
  72652         0,
  72653         8,
  72654         soc_BRDC_FSRD_RES_CAL_STATUS_BCM88950_A0r_fields,
  72655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  72656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  72657         -1,
  72658         -1,
  72659     },
  72660 #endif /* chips */
  72661 
  72662 #if defined(BCM_88675_A0)
  72663     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIGr */
  72664         soc_block_list[27],
  72665         soc_genreg,
  72666         1,
  72667         0,
  72668         0x205,
  72669         SOC_REG_FLAG_WO |
  72670                           SOC_REG_FLAG_SIGNAL,
  72671         0,
  72672         3,
  72673         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIGr_fields,
  72674         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72675         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72676         -1,
  72677         -1,
  72678     },
  72679 #endif /* chips */
  72680 
  72681 #if defined(BCM_88375_A0)
  72682     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88375_A0r */
  72683         soc_block_list[27],
  72684         soc_genreg,
  72685         1,
  72686         0,
  72687         0x205,
  72688         SOC_REG_FLAG_WO |
  72689                           SOC_REG_FLAG_SIGNAL,
  72690         0,
  72691         3,
  72692         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88375_A0r_fields,
  72693         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72694         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72695         -1,
  72696         -1,
  72697     },
  72698 #endif /* chips */
  72699 
  72700 #if defined(BCM_88375_B0)
  72701     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88375_B0r */
  72702         soc_block_list[27],
  72703         soc_genreg,
  72704         1,
  72705         0,
  72706         0x205,
  72707         SOC_REG_FLAG_WO |
  72708                           SOC_REG_FLAG_SIGNAL,
  72709         0,
  72710         3,
  72711         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88375_B0r_fields,
  72712         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72713         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72714         -1,
  72715         -1,
  72716     },
  72717 #endif /* chips */
  72718 
  72719 #if defined(BCM_88675_B0)
  72720     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88675_B0r */
  72721         soc_block_list[27],
  72722         soc_genreg,
  72723         1,
  72724         0,
  72725         0x205,
  72726         SOC_REG_FLAG_WO |
  72727                           SOC_REG_FLAG_SIGNAL,
  72728         0,
  72729         3,
  72730         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88675_B0r_fields,
  72731         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72732         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72733         -1,
  72734         -1,
  72735     },
  72736 #endif /* chips */
  72737 
  72738 #if defined(BCM_88680_A0)
  72739     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88680_A0r */
  72740         soc_block_list[27],
  72741         soc_genreg,
  72742         1,
  72743         0,
  72744         0x205,
  72745         SOC_REG_FLAG_WO |
  72746                           SOC_REG_FLAG_SIGNAL,
  72747         0,
  72748         3,
  72749         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88680_A0r_fields,
  72750         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72751         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72752         -1,
  72753         -1,
  72754     },
  72755 #endif /* chips */
  72756 
  72757 #if defined(BCM_88690_A0)
  72758     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88690_A0r */
  72759         soc_block_list[27],
  72760         soc_genreg,
  72761         1,
  72762         0,
  72763         0x112,
  72764         SOC_REG_FLAG_WO |
  72765                           SOC_REG_FLAG_SIGNAL,
  72766         0,
  72767         3,
  72768         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88690_A0r_fields,
  72769         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72770         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72771         -1,
  72772         -1,
  72773     },
  72774 #endif /* chips */
  72775 
  72776 #if defined(BCM_88690_B0)
  72777     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88690_B0r */
  72778         soc_block_list[27],
  72779         soc_genreg,
  72780         1,
  72781         0,
  72782         0x112,
  72783         SOC_REG_FLAG_WO |
  72784                           SOC_REG_FLAG_SIGNAL,
  72785         0,
  72786         3,
  72787         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88690_B0r_fields,
  72788         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72789         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72790         -1,
  72791         -1,
  72792     },
  72793 #endif /* chips */
  72794 
  72795 #if defined(BCM_88790_A0)
  72796     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88790_A0r */
  72797         soc_block_list[27],
  72798         soc_genreg,
  72799         1,
  72800         0,
  72801         0x112,
  72802         SOC_REG_FLAG_WO |
  72803                           SOC_REG_FLAG_SIGNAL,
  72804         0,
  72805         3,
  72806         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88790_A0r_fields,
  72807         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72808         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72809         -1,
  72810         -1,
  72811     },
  72812 #endif /* chips */
  72813 
  72814 #if defined(BCM_88950_A0)
  72815     { /* SOC_REG_INT_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88950_A0r */
  72816         soc_block_list[27],
  72817         soc_genreg,
  72818         1,
  72819         0,
  72820         0x205,
  72821         SOC_REG_FLAG_WO |
  72822                           SOC_REG_FLAG_SIGNAL,
  72823         0,
  72824         3,
  72825         soc_BRDC_FSRD_RES_CAL_STICKY_CONFIG_BCM88950_A0r_fields,
  72826         SOC_RESET_VAL_DEC(0x00000200, 0x00000000)
  72827         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  72828         -1,
  72829         -1,
  72830     },
  72831 #endif /* chips */
  72832 
  72833 #if defined(BCM_88650_A0)
  72834     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_IDr */
  72835         soc_block_list[27],
  72836         soc_genreg,
  72837         1,
  72838         0,
  72839         0x86,
  72840         SOC_REG_FLAG_WO,
  72841         0,
  72842         1,
  72843         soc_BRDC_FSRD_SBUS_BROADCAST_IDr_fields,
  72844         SOC_RESET_VAL_DEC(0x0000003e, 0x00000000)
  72845         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  72846         -1,
  72847         -1,
  72848     },
  72849 #endif /* chips */
  72850 
  72851 #if defined(BCM_88202_A0)
  72852     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88202_A0r */
  72853         soc_block_list[27],
  72854         soc_genreg,
  72855         1,
  72856         0,
  72857         0x86,
  72858         SOC_REG_FLAG_WO,
  72859         0,
  72860         1,
  72861         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88202_A0r_fields,
  72862         SOC_RESET_VAL_DEC(0x0000003e, 0x00000000)
  72863         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  72864         -1,
  72865         -1,
  72866     },
  72867 #endif /* chips */
  72868 
  72869 #if defined(BCM_88375_A0)
  72870     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88375_A0r */
  72871         soc_block_list[27],
  72872         soc_genreg,
  72873         1,
  72874         0,
  72875         0x86,
  72876         SOC_REG_FLAG_WO,
  72877         0,
  72878         1,
  72879         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88375_A0r_fields,
  72880         SOC_RESET_VAL_DEC(0x0000004c, 0x00000000)
  72881         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  72882         -1,
  72883         -1,
  72884     },
  72885 #endif /* chips */
  72886 
  72887 #if defined(BCM_88375_B0)
  72888     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88375_B0r */
  72889         soc_block_list[27],
  72890         soc_genreg,
  72891         1,
  72892         0,
  72893         0x86,
  72894         SOC_REG_FLAG_WO,
  72895         0,
  72896         1,
  72897         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88375_B0r_fields,
  72898         SOC_RESET_VAL_DEC(0x0000004c, 0x00000000)
  72899         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  72900         -1,
  72901         -1,
  72902     },
  72903 #endif /* chips */
  72904 
  72905 #if defined(BCM_88650_B0)
  72906     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88650_B0r */
  72907         soc_block_list[27],
  72908         soc_genreg,
  72909         1,
  72910         0,
  72911         0x86,
  72912         SOC_REG_FLAG_WO,
  72913         0,
  72914         1,
  72915         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88650_B0r_fields,
  72916         SOC_RESET_VAL_DEC(0x0000003e, 0x00000000)
  72917         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  72918         -1,
  72919         -1,
  72920     },
  72921 #endif /* chips */
  72922 
  72923 #if defined(BCM_88660_A0)
  72924     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88660_A0r */
  72925         soc_block_list[27],
  72926         soc_genreg,
  72927         1,
  72928         0,
  72929         0x86,
  72930         SOC_REG_FLAG_WO,
  72931         0,
  72932         1,
  72933         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88660_A0r_fields,
  72934         SOC_RESET_VAL_DEC(0x0000003e, 0x00000000)
  72935         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  72936         -1,
  72937         -1,
  72938     },
  72939 #endif /* chips */
  72940 
  72941 #if defined(BCM_88675_A0)
  72942     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88675_A0r */
  72943         soc_block_list[27],
  72944         soc_genreg,
  72945         1,
  72946         0,
  72947         0x86,
  72948         SOC_REG_FLAG_WO,
  72949         0,
  72950         1,
  72951         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88675_A0r_fields,
  72952         SOC_RESET_VAL_DEC(0x0000004c, 0x00000000)
  72953         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  72954         -1,
  72955         -1,
  72956     },
  72957 #endif /* chips */
  72958 
  72959 #if defined(BCM_88675_B0)
  72960     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88675_B0r */
  72961         soc_block_list[27],
  72962         soc_genreg,
  72963         1,
  72964         0,
  72965         0x86,
  72966         SOC_REG_FLAG_WO,
  72967         0,
  72968         1,
  72969         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88675_B0r_fields,
  72970         SOC_RESET_VAL_DEC(0x0000004c, 0x00000000)
  72971         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  72972         -1,
  72973         -1,
  72974     },
  72975 #endif /* chips */
  72976 
  72977 #if defined(BCM_88680_A0)
  72978     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88680_A0r */
  72979         soc_block_list[27],
  72980         soc_genreg,
  72981         1,
  72982         0,
  72983         0x86,
  72984         SOC_REG_FLAG_WO,
  72985         0,
  72986         1,
  72987         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88680_A0r_fields,
  72988         SOC_RESET_VAL_DEC(0x0000004c, 0x00000000)
  72989         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  72990         -1,
  72991         -1,
  72992     },
  72993 #endif /* chips */
  72994 
  72995 #if defined(BCM_88690_A0)
  72996     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88690_A0r */
  72997         soc_block_list[27],
  72998         soc_genreg,
  72999         1,
  73000         0,
  73001         0x86,
  73002         SOC_REG_FLAG_WO,
  73003         0,
  73004         1,
  73005         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88690_A0r_fields,
  73006         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  73007         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  73008         -1,
  73009         -1,
  73010     },
  73011 #endif /* chips */
  73012 
  73013 #if defined(BCM_88690_B0)
  73014     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88690_B0r */
  73015         soc_block_list[27],
  73016         soc_genreg,
  73017         1,
  73018         0,
  73019         0x86,
  73020         SOC_REG_FLAG_WO,
  73021         0,
  73022         1,
  73023         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
  73024         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  73025         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  73026         -1,
  73027         -1,
  73028     },
  73029 #endif /* chips */
  73030 
  73031 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  73032     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88750_A0r */
  73033         soc_block_list[27],
  73034         soc_genreg,
  73035         1,
  73036         0,
  73037         0x55,
  73038         SOC_REG_FLAG_WO,
  73039         0,
  73040         1,
  73041         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88750_A0r_fields,
  73042         SOC_RESET_VAL_DEC(0x0000003e, 0x00000000)
  73043         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  73044         -1,
  73045         -1,
  73046     },
  73047 #endif /* chips */
  73048 
  73049 #if defined(BCM_88790_A0)
  73050     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88790_A0r */
  73051         soc_block_list[27],
  73052         soc_genreg,
  73053         1,
  73054         0,
  73055         0x86,
  73056         SOC_REG_FLAG_WO,
  73057         0,
  73058         1,
  73059         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88790_A0r_fields,
  73060         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  73061         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  73062         -1,
  73063         -1,
  73064     },
  73065 #endif /* chips */
  73066 
  73067 #if defined(BCM_88950_A0)
  73068     { /* SOC_REG_INT_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88950_A0r */
  73069         soc_block_list[27],
  73070         soc_genreg,
  73071         1,
  73072         0,
  73073         0x86,
  73074         SOC_REG_FLAG_WO,
  73075         0,
  73076         1,
  73077         soc_BRDC_FSRD_SBUS_BROADCAST_ID_BCM88950_A0r_fields,
  73078         SOC_RESET_VAL_DEC(0x0000004c, 0x00000000)
  73079         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  73080         -1,
  73081         -1,
  73082     },
  73083 #endif /* chips */
  73084 
  73085 #if defined(BCM_88675_A0)
  73086     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAINr */
  73087         soc_block_list[27],
  73088         soc_genreg,
  73089         1,
  73090         0,
  73091         0x87,
  73092         SOC_REG_FLAG_WO,
  73093         0,
  73094         1,
  73095         soc_BRDC_FSRD_SBUS_LAST_IN_CHAINr_fields,
  73096         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73097         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73098         -1,
  73099         -1,
  73100     },
  73101 #endif /* chips */
  73102 
  73103 #if defined(BCM_88375_A0)
  73104     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88375_A0r */
  73105         soc_block_list[27],
  73106         soc_genreg,
  73107         1,
  73108         0,
  73109         0x87,
  73110         SOC_REG_FLAG_WO,
  73111         0,
  73112         1,
  73113         soc_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88375_A0r_fields,
  73114         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73115         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73116         -1,
  73117         -1,
  73118     },
  73119 #endif /* chips */
  73120 
  73121 #if defined(BCM_88375_B0)
  73122     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88375_B0r */
  73123         soc_block_list[27],
  73124         soc_genreg,
  73125         1,
  73126         0,
  73127         0x87,
  73128         SOC_REG_FLAG_WO,
  73129         0,
  73130         1,
  73131         soc_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88375_B0r_fields,
  73132         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73133         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73134         -1,
  73135         -1,
  73136     },
  73137 #endif /* chips */
  73138 
  73139 #if defined(BCM_88675_B0)
  73140     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88675_B0r */
  73141         soc_block_list[27],
  73142         soc_genreg,
  73143         1,
  73144         0,
  73145         0x87,
  73146         SOC_REG_FLAG_WO,
  73147         0,
  73148         1,
  73149         soc_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88675_B0r_fields,
  73150         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73151         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73152         -1,
  73153         -1,
  73154     },
  73155 #endif /* chips */
  73156 
  73157 #if defined(BCM_88680_A0)
  73158     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88680_A0r */
  73159         soc_block_list[27],
  73160         soc_genreg,
  73161         1,
  73162         0,
  73163         0x87,
  73164         SOC_REG_FLAG_WO,
  73165         0,
  73166         1,
  73167         soc_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88680_A0r_fields,
  73168         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73169         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73170         -1,
  73171         -1,
  73172     },
  73173 #endif /* chips */
  73174 
  73175 #if defined(BCM_88690_A0)
  73176     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88690_A0r */
  73177         soc_block_list[27],
  73178         soc_genreg,
  73179         1,
  73180         0,
  73181         0x87,
  73182         SOC_REG_FLAG_WO,
  73183         0,
  73184         1,
  73185         soc_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88690_A0r_fields,
  73186         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73187         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73188         -1,
  73189         -1,
  73190     },
  73191 #endif /* chips */
  73192 
  73193 #if defined(BCM_88690_B0)
  73194     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
  73195         soc_block_list[27],
  73196         soc_genreg,
  73197         1,
  73198         0,
  73199         0x87,
  73200         SOC_REG_FLAG_WO,
  73201         0,
  73202         1,
  73203         soc_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
  73204         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73205         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73206         -1,
  73207         -1,
  73208     },
  73209 #endif /* chips */
  73210 
  73211 #if defined(BCM_88790_A0)
  73212     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88790_A0r */
  73213         soc_block_list[27],
  73214         soc_genreg,
  73215         1,
  73216         0,
  73217         0x87,
  73218         SOC_REG_FLAG_WO,
  73219         0,
  73220         1,
  73221         soc_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88790_A0r_fields,
  73222         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73223         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73224         -1,
  73225         -1,
  73226     },
  73227 #endif /* chips */
  73228 
  73229 #if defined(BCM_88950_A0)
  73230     { /* SOC_REG_INT_BRDC_FSRD_SBUS_LAST_IN_CHAIN_BCM88950_A0r */
  73231         soc_block_list[27],
  73232         soc_genreg,
  73233         1,
  73234         0,
  73235         0x87,
  73236         SOC_REG_FLAG_WO,
  73237         0,
  73238         1,
  73239         soc_BRDC_CCS_SBUS_LAST_IN_CHAINr_fields,
  73240         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73241         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  73242         -1,
  73243         -1,
  73244     },
  73245 #endif /* chips */
  73246 
  73247 #if defined(BCM_88650_A0)
  73248     { /* SOC_REG_INT_BRDC_FSRD_SPARE_REGISTER_3r */
  73249         soc_block_list[27],
  73250         soc_genreg,
  73251         1,
  73252         0,
  73253         0x93,
  73254         SOC_REG_FLAG_WO,
  73255         0,
  73256         1,
  73257         soc_BRDC_FSRD_SPARE_REGISTER_3r_fields,
  73258         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73259         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73260         -1,
  73261         -1,
  73262     },
  73263 #endif /* chips */
  73264 
  73265 #if defined(BCM_88202_A0)
  73266     { /* SOC_REG_INT_BRDC_FSRD_SPARE_REGISTER_3_BCM88202_A0r */
  73267         soc_block_list[27],
  73268         soc_genreg,
  73269         1,
  73270         0,
  73271         0x93,
  73272         SOC_REG_FLAG_WO,
  73273         0,
  73274         1,
  73275         soc_BRDC_FSRD_SPARE_REGISTER_3_BCM88202_A0r_fields,
  73276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73277         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73278         -1,
  73279         -1,
  73280     },
  73281 #endif /* chips */
  73282 
  73283 #if defined(BCM_88650_B0)
  73284     { /* SOC_REG_INT_BRDC_FSRD_SPARE_REGISTER_3_BCM88650_B0r */
  73285         soc_block_list[27],
  73286         soc_genreg,
  73287         1,
  73288         0,
  73289         0x93,
  73290         SOC_REG_FLAG_WO,
  73291         0,
  73292         1,
  73293         soc_BRDC_FSRD_SPARE_REGISTER_3_BCM88650_B0r_fields,
  73294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73295         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73296         -1,
  73297         -1,
  73298     },
  73299 #endif /* chips */
  73300 
  73301 #if defined(BCM_88660_A0)
  73302     { /* SOC_REG_INT_BRDC_FSRD_SPARE_REGISTER_3_BCM88660_A0r */
  73303         soc_block_list[27],
  73304         soc_genreg,
  73305         1,
  73306         0,
  73307         0x93,
  73308         SOC_REG_FLAG_WO,
  73309         0,
  73310         1,
  73311         soc_BRDC_FSRD_SPARE_REGISTER_3_BCM88660_A0r_fields,
  73312         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73313         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73314         -1,
  73315         -1,
  73316     },
  73317 #endif /* chips */
  73318 
  73319 #if defined(BCM_88750_A0)
  73320     { /* SOC_REG_INT_BRDC_FSRD_SPARE_REGISTER_3_BCM88750_A0r */
  73321         soc_block_list[27],
  73322         soc_genreg,
  73323         1,
  73324         0,
  73325         0x53,
  73326         SOC_REG_FLAG_WO,
  73327         0,
  73328         1,
  73329         soc_BRDC_FSRD_SPARE_REGISTER_3_BCM88750_A0r_fields,
  73330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73331         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  73332         -1,
  73333         -1,
  73334     },
  73335 #endif /* chips */
  73336 
  73337 #if defined(BCM_88690_B0)
  73338     { /* SOC_REG_INT_BRDC_FSRD_SPECIAL_CLOCK_CONTROLSr */
  73339         soc_block_list[27],
  73340         soc_genreg,
  73341         1,
  73342         0,
  73343         0xc1,
  73344         SOC_REG_FLAG_WO,
  73345         0,
  73346         1,
  73347         soc_BRDC_FSRD_SPECIAL_CLOCK_CONTROLSr_fields,
  73348         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  73349         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
  73350         -1,
  73351         -1,
  73352     },
  73353 #endif /* chips */
  73354 
  73355 #if defined(BCM_88790_A0)
  73356     { /* SOC_REG_INT_BRDC_FSRD_SRD_CTRLr */
  73357         soc_block_list[27],
  73358         soc_genreg,
  73359         1,
  73360         0,
  73361         0x103,
  73362         SOC_REG_FLAG_ABOVE_64_BITS |
  73363                           SOC_REG_FLAG_WO,
  73364         0,
  73365         14,
  73366         soc_BRDC_FSRD_SRD_CTRLr_fields,
  73367         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73368         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  73369         -1,
  73370         -1,
  73371     },
  73372 #endif /* chips */
  73373 
  73374 #if defined(BCM_88690_A0)
  73375     { /* SOC_REG_INT_BRDC_FSRD_SRD_CTRL_BCM88690_A0r */
  73376         soc_block_list[27],
  73377         soc_genreg,
  73378         1,
  73379         0,
  73380         0x103,
  73381         SOC_REG_FLAG_ABOVE_64_BITS |
  73382                           SOC_REG_FLAG_WO,
  73383         0,
  73384         14,
  73385         soc_BRDC_FSRD_SRD_CTRL_BCM88690_A0r_fields,
  73386         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73387         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  73388         -1,
  73389         -1,
  73390     },
  73391 #endif /* chips */
  73392 
  73393 #if defined(BCM_88690_B0)
  73394     { /* SOC_REG_INT_BRDC_FSRD_SRD_CTRL_BCM88690_B0r */
  73395         soc_block_list[27],
  73396         soc_genreg,
  73397         1,
  73398         0,
  73399         0x103,
  73400         SOC_REG_FLAG_ABOVE_64_BITS |
  73401                           SOC_REG_FLAG_WO,
  73402         0,
  73403         14,
  73404         soc_BRDC_FSRD_SRD_CTRL_BCM88690_B0r_fields,
  73405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73406         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  73407         -1,
  73408         -1,
  73409     },
  73410 #endif /* chips */
  73411 
  73412 #if defined(BCM_88790_A0)
  73413     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_MODEr */
  73414         soc_block_list[27],
  73415         soc_genreg,
  73416         1,
  73417         0,
  73418         0x10a,
  73419         SOC_REG_FLAG_ABOVE_64_BITS |
  73420                           SOC_REG_FLAG_WO,
  73421         0,
  73422         16,
  73423         soc_BRDC_FSRD_SRD_LN_MODEr_fields,
  73424         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73425         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  73426         -1,
  73427         -1,
  73428     },
  73429 #endif /* chips */
  73430 
  73431 #if defined(BCM_88690_A0)
  73432     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_MODE_BCM88690_A0r */
  73433         soc_block_list[27],
  73434         soc_genreg,
  73435         1,
  73436         0,
  73437         0x10a,
  73438         SOC_REG_FLAG_ABOVE_64_BITS |
  73439                           SOC_REG_FLAG_WO,
  73440         0,
  73441         16,
  73442         soc_BRDC_FSRD_SRD_LN_MODE_BCM88690_A0r_fields,
  73443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73444         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  73445         -1,
  73446         -1,
  73447     },
  73448 #endif /* chips */
  73449 
  73450 #if defined(BCM_88690_B0)
  73451     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_MODE_BCM88690_B0r */
  73452         soc_block_list[27],
  73453         soc_genreg,
  73454         1,
  73455         0,
  73456         0x10a,
  73457         SOC_REG_FLAG_ABOVE_64_BITS |
  73458                           SOC_REG_FLAG_WO,
  73459         0,
  73460         16,
  73461         soc_BRDC_FSRD_SRD_LN_MODE_BCM88690_B0r_fields,
  73462         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73463         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  73464         -1,
  73465         -1,
  73466     },
  73467 #endif /* chips */
  73468 
  73469 #if defined(BCM_88790_A0)
  73470     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_OSRr */
  73471         soc_block_list[27],
  73472         soc_genreg,
  73473         1,
  73474         0,
  73475         0x108,
  73476         SOC_REG_FLAG_64_BITS |
  73477                           SOC_REG_FLAG_WO,
  73478         0,
  73479         16,
  73480         soc_BRDC_FSRD_SRD_LN_OSRr_fields,
  73481         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73482         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  73483         -1,
  73484         -1,
  73485     },
  73486 #endif /* chips */
  73487 
  73488 #if defined(BCM_88690_A0)
  73489     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_OSR_BCM88690_A0r */
  73490         soc_block_list[27],
  73491         soc_genreg,
  73492         1,
  73493         0,
  73494         0x108,
  73495         SOC_REG_FLAG_64_BITS |
  73496                           SOC_REG_FLAG_WO,
  73497         0,
  73498         16,
  73499         soc_BRDC_FSRD_SRD_LN_OSR_BCM88690_A0r_fields,
  73500         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73501         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  73502         -1,
  73503         -1,
  73504     },
  73505 #endif /* chips */
  73506 
  73507 #if defined(BCM_88690_B0)
  73508     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_OSR_BCM88690_B0r */
  73509         soc_block_list[27],
  73510         soc_genreg,
  73511         1,
  73512         0,
  73513         0x108,
  73514         SOC_REG_FLAG_64_BITS |
  73515                           SOC_REG_FLAG_WO,
  73516         0,
  73517         16,
  73518         soc_BRDC_FSRD_SRD_LN_OSR_BCM88690_B0r_fields,
  73519         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73520         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  73521         -1,
  73522         -1,
  73523     },
  73524 #endif /* chips */
  73525 
  73526 #if defined(BCM_88790_A0)
  73527     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_PAMr */
  73528         soc_block_list[27],
  73529         soc_genreg,
  73530         1,
  73531         0,
  73532         0x109,
  73533         SOC_REG_FLAG_64_BITS |
  73534                           SOC_REG_FLAG_WO,
  73535         0,
  73536         16,
  73537         soc_BRDC_FSRD_SRD_LN_PAMr_fields,
  73538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73539         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  73540         -1,
  73541         -1,
  73542     },
  73543 #endif /* chips */
  73544 
  73545 #if defined(BCM_88690_A0)
  73546     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_PAM_BCM88690_A0r */
  73547         soc_block_list[27],
  73548         soc_genreg,
  73549         1,
  73550         0,
  73551         0x109,
  73552         SOC_REG_FLAG_64_BITS |
  73553                           SOC_REG_FLAG_WO,
  73554         0,
  73555         16,
  73556         soc_BRDC_FSRD_SRD_LN_PAM_BCM88690_A0r_fields,
  73557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73558         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  73559         -1,
  73560         -1,
  73561     },
  73562 #endif /* chips */
  73563 
  73564 #if defined(BCM_88690_B0)
  73565     { /* SOC_REG_INT_BRDC_FSRD_SRD_LN_PAM_BCM88690_B0r */
  73566         soc_block_list[27],
  73567         soc_genreg,
  73568         1,
  73569         0,
  73570         0x109,
  73571         SOC_REG_FLAG_64_BITS |
  73572                           SOC_REG_FLAG_WO,
  73573         0,
  73574         16,
  73575         soc_BRDC_FSRD_SRD_LN_PAM_BCM88690_B0r_fields,
  73576         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73577         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  73578         -1,
  73579         -1,
  73580     },
  73581 #endif /* chips */
  73582 
  73583 #if defined(BCM_88790_A0)
  73584     { /* SOC_REG_INT_BRDC_FSRD_SRD_PLL_0_CTRLr */
  73585         soc_block_list[27],
  73586         soc_genreg,
  73587         1,
  73588         0,
  73589         0x106,
  73590         SOC_REG_FLAG_WO,
  73591         0,
  73592         8,
  73593         soc_BRDC_FSRD_SRD_PLL_0_CTRLr_fields,
  73594         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73595         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  73596         -1,
  73597         -1,
  73598     },
  73599 #endif /* chips */
  73600 
  73601 #if defined(BCM_88690_A0)
  73602     { /* SOC_REG_INT_BRDC_FSRD_SRD_PLL_0_CTRL_BCM88690_A0r */
  73603         soc_block_list[27],
  73604         soc_genreg,
  73605         1,
  73606         0,
  73607         0x106,
  73608         SOC_REG_FLAG_WO,
  73609         0,
  73610         8,
  73611         soc_BRDC_FSRD_SRD_PLL_0_CTRL_BCM88690_A0r_fields,
  73612         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73613         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  73614         -1,
  73615         -1,
  73616     },
  73617 #endif /* chips */
  73618 
  73619 #if defined(BCM_88690_B0)
  73620     { /* SOC_REG_INT_BRDC_FSRD_SRD_PLL_0_CTRL_BCM88690_B0r */
  73621         soc_block_list[27],
  73622         soc_genreg,
  73623         1,
  73624         0,
  73625         0x106,
  73626         SOC_REG_FLAG_WO,
  73627         0,
  73628         8,
  73629         soc_BRDC_FSRD_SRD_PLL_0_CTRL_BCM88690_B0r_fields,
  73630         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73631         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  73632         -1,
  73633         -1,
  73634     },
  73635 #endif /* chips */
  73636 
  73637 #if defined(BCM_88790_A0)
  73638     { /* SOC_REG_INT_BRDC_FSRD_SRD_PLL_1_CTRLr */
  73639         soc_block_list[27],
  73640         soc_genreg,
  73641         1,
  73642         0,
  73643         0x107,
  73644         SOC_REG_FLAG_WO,
  73645         0,
  73646         8,
  73647         soc_BRDC_FSRD_SRD_PLL_1_CTRLr_fields,
  73648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73649         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  73650         -1,
  73651         -1,
  73652     },
  73653 #endif /* chips */
  73654 
  73655 #if defined(BCM_88690_A0)
  73656     { /* SOC_REG_INT_BRDC_FSRD_SRD_PLL_1_CTRL_BCM88690_A0r */
  73657         soc_block_list[27],
  73658         soc_genreg,
  73659         1,
  73660         0,
  73661         0x107,
  73662         SOC_REG_FLAG_WO,
  73663         0,
  73664         8,
  73665         soc_BRDC_FSRD_SRD_PLL_1_CTRL_BCM88690_A0r_fields,
  73666         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73667         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  73668         -1,
  73669         -1,
  73670     },
  73671 #endif /* chips */
  73672 
  73673 #if defined(BCM_88690_B0)
  73674     { /* SOC_REG_INT_BRDC_FSRD_SRD_PLL_1_CTRL_BCM88690_B0r */
  73675         soc_block_list[27],
  73676         soc_genreg,
  73677         1,
  73678         0,
  73679         0x107,
  73680         SOC_REG_FLAG_WO,
  73681         0,
  73682         8,
  73683         soc_BRDC_FSRD_SRD_PLL_1_CTRL_BCM88690_B0r_fields,
  73684         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73685         SOC_RESET_MASK_DEC(0x007fffff, 0x00000000)
  73686         -1,
  73687         -1,
  73688     },
  73689 #endif /* chips */
  73690 
  73691 #if defined(BCM_88650_A0)
  73692     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRLr */
  73693         soc_block_list[27],
  73694         soc_genreg,
  73695         3,
  73696         0,
  73697         0x160,
  73698         SOC_REG_FLAG_ARRAY |
  73699                           SOC_REG_FLAG_WO |
  73700                           SOC_REG_FLAG_REG_ARRAY,
  73701         0,
  73702         12,
  73703         soc_BRDC_FSRD_SRD_QUAD_CTRLr_fields,
  73704         SOC_RESET_VAL_DEC(0x00047e03, 0x00000000)
  73705         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  73706         -1,
  73707         -1,
  73708     },
  73709 #endif /* chips */
  73710 
  73711 #if defined(BCM_88202_A0)
  73712     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88202_A0r */
  73713         soc_block_list[27],
  73714         soc_genreg,
  73715         3,
  73716         0,
  73717         0x160,
  73718         SOC_REG_FLAG_ARRAY |
  73719                           SOC_REG_FLAG_WO |
  73720                           SOC_REG_FLAG_REG_ARRAY,
  73721         0,
  73722         8,
  73723         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88202_A0r_fields,
  73724         SOC_RESET_VAL_DEC(0x000ff001, 0x00000000)
  73725         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  73726         -1,
  73727         -1,
  73728     },
  73729 #endif /* chips */
  73730 
  73731 #if defined(BCM_88375_A0)
  73732     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88375_A0r */
  73733         soc_block_list[27],
  73734         soc_genreg,
  73735         3,
  73736         0,
  73737         0x150,
  73738         SOC_REG_FLAG_ARRAY |
  73739                           SOC_REG_FLAG_WO |
  73740                           SOC_REG_FLAG_REG_ARRAY,
  73741         0,
  73742         11,
  73743         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88375_A0r_fields,
  73744         SOC_RESET_VAL_DEC(0x03fc0003, 0x00000000)
  73745         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  73746         -1,
  73747         -1,
  73748     },
  73749 #endif /* chips */
  73750 
  73751 #if defined(BCM_88375_B0)
  73752     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88375_B0r */
  73753         soc_block_list[27],
  73754         soc_genreg,
  73755         3,
  73756         0,
  73757         0x150,
  73758         SOC_REG_FLAG_ARRAY |
  73759                           SOC_REG_FLAG_WO |
  73760                           SOC_REG_FLAG_REG_ARRAY,
  73761         0,
  73762         11,
  73763         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88375_B0r_fields,
  73764         SOC_RESET_VAL_DEC(0x03fc0003, 0x00000000)
  73765         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  73766         -1,
  73767         -1,
  73768     },
  73769 #endif /* chips */
  73770 
  73771 #if defined(BCM_88650_B0)
  73772     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88650_B0r */
  73773         soc_block_list[27],
  73774         soc_genreg,
  73775         3,
  73776         0,
  73777         0x160,
  73778         SOC_REG_FLAG_ARRAY |
  73779                           SOC_REG_FLAG_WO |
  73780                           SOC_REG_FLAG_REG_ARRAY,
  73781         0,
  73782         12,
  73783         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88650_B0r_fields,
  73784         SOC_RESET_VAL_DEC(0x00047e03, 0x00000000)
  73785         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  73786         -1,
  73787         -1,
  73788     },
  73789 #endif /* chips */
  73790 
  73791 #if defined(BCM_88660_A0)
  73792     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88660_A0r */
  73793         soc_block_list[27],
  73794         soc_genreg,
  73795         3,
  73796         0,
  73797         0x160,
  73798         SOC_REG_FLAG_ARRAY |
  73799                           SOC_REG_FLAG_WO |
  73800                           SOC_REG_FLAG_REG_ARRAY,
  73801         0,
  73802         12,
  73803         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88660_A0r_fields,
  73804         SOC_RESET_VAL_DEC(0x00047e03, 0x00000000)
  73805         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  73806         -1,
  73807         -1,
  73808     },
  73809 #endif /* chips */
  73810 
  73811 #if defined(BCM_88675_A0)
  73812     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88675_A0r */
  73813         soc_block_list[27],
  73814         soc_genreg,
  73815         3,
  73816         0,
  73817         0x150,
  73818         SOC_REG_FLAG_ARRAY |
  73819                           SOC_REG_FLAG_WO |
  73820                           SOC_REG_FLAG_REG_ARRAY,
  73821         0,
  73822         11,
  73823         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88675_A0r_fields,
  73824         SOC_RESET_VAL_DEC(0x03fc0003, 0x00000000)
  73825         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  73826         -1,
  73827         -1,
  73828     },
  73829 #endif /* chips */
  73830 
  73831 #if defined(BCM_88675_B0)
  73832     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88675_B0r */
  73833         soc_block_list[27],
  73834         soc_genreg,
  73835         3,
  73836         0,
  73837         0x150,
  73838         SOC_REG_FLAG_ARRAY |
  73839                           SOC_REG_FLAG_WO |
  73840                           SOC_REG_FLAG_REG_ARRAY,
  73841         0,
  73842         11,
  73843         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88675_B0r_fields,
  73844         SOC_RESET_VAL_DEC(0x03fc0003, 0x00000000)
  73845         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  73846         -1,
  73847         -1,
  73848     },
  73849 #endif /* chips */
  73850 
  73851 #if defined(BCM_88680_A0)
  73852     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88680_A0r */
  73853         soc_block_list[27],
  73854         soc_genreg,
  73855         3,
  73856         0,
  73857         0x150,
  73858         SOC_REG_FLAG_ARRAY |
  73859                           SOC_REG_FLAG_WO |
  73860                           SOC_REG_FLAG_REG_ARRAY,
  73861         0,
  73862         11,
  73863         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88680_A0r_fields,
  73864         SOC_RESET_VAL_DEC(0x03fc0003, 0x00000000)
  73865         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  73866         -1,
  73867         -1,
  73868     },
  73869 #endif /* chips */
  73870 
  73871 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  73872     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88750_A0r */
  73873         soc_block_list[27],
  73874         soc_genreg,
  73875         4,
  73876         0,
  73877         0x60,
  73878         SOC_REG_FLAG_ARRAY |
  73879                           SOC_REG_FLAG_WO |
  73880                           SOC_REG_FLAG_REG_ARRAY |
  73881                           SOC_REG_FLAG_SIGNAL,
  73882         0,
  73883         12,
  73884         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88750_A0r_fields,
  73885         SOC_RESET_VAL_DEC(0x00047e03, 0x00000000)
  73886         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  73887         -1,
  73888         -1,
  73889     },
  73890 #endif /* chips */
  73891 
  73892 #if defined(BCM_88950_A0)
  73893     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_CTRL_BCM88950_A0r */
  73894         soc_block_list[27],
  73895         soc_genreg,
  73896         3,
  73897         0,
  73898         0x150,
  73899         SOC_REG_FLAG_ARRAY |
  73900                           SOC_REG_FLAG_WO |
  73901                           SOC_REG_FLAG_REG_ARRAY,
  73902         0,
  73903         11,
  73904         soc_BRDC_FSRD_SRD_QUAD_CTRL_BCM88950_A0r_fields,
  73905         SOC_RESET_VAL_DEC(0x03fc0003, 0x00000000)
  73906         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  73907         -1,
  73908         -1,
  73909     },
  73910 #endif /* chips */
  73911 
  73912 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  73913     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_FORCE_SPEED_STRAPSr */
  73914         soc_block_list[27],
  73915         soc_genreg,
  73916         4,
  73917         0,
  73918         0x70,
  73919         SOC_REG_FLAG_ARRAY |
  73920                           SOC_REG_FLAG_WO |
  73921                           SOC_REG_FLAG_REG_ARRAY,
  73922         0,
  73923         1,
  73924         soc_BRDC_FSRD_SRD_QUAD_LN_FORCE_SPEED_STRAPSr_fields,
  73925         SOC_RESET_VAL_DEC(0x00408102, 0x00000000)
  73926         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  73927         -1,
  73928         -1,
  73929     },
  73930 #endif /* chips */
  73931 
  73932 #if defined(BCM_88202_A0)
  73933     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_STRAPSr */
  73934         soc_block_list[27],
  73935         soc_genreg,
  73936         3,
  73937         0,
  73938         0x170,
  73939         SOC_REG_FLAG_ARRAY |
  73940                           SOC_REG_FLAG_WO |
  73941                           SOC_REG_FLAG_REG_ARRAY,
  73942         0,
  73943         4,
  73944         soc_BRDC_FSRD_SRD_QUAD_LN_STRAPSr_fields,
  73945         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73946         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73947         -1,
  73948         -1,
  73949     },
  73950 #endif /* chips */
  73951 
  73952 #if defined(BCM_88375_A0)
  73953     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88375_A0r */
  73954         soc_block_list[27],
  73955         soc_genreg,
  73956         3,
  73957         0,
  73958         0x170,
  73959         SOC_REG_FLAG_ARRAY |
  73960                           SOC_REG_FLAG_WO |
  73961                           SOC_REG_FLAG_REG_ARRAY,
  73962         0,
  73963         4,
  73964         soc_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88375_A0r_fields,
  73965         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73966         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73967         -1,
  73968         -1,
  73969     },
  73970 #endif /* chips */
  73971 
  73972 #if defined(BCM_88375_B0)
  73973     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88375_B0r */
  73974         soc_block_list[27],
  73975         soc_genreg,
  73976         3,
  73977         0,
  73978         0x170,
  73979         SOC_REG_FLAG_ARRAY |
  73980                           SOC_REG_FLAG_WO |
  73981                           SOC_REG_FLAG_REG_ARRAY,
  73982         0,
  73983         4,
  73984         soc_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88375_B0r_fields,
  73985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  73986         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  73987         -1,
  73988         -1,
  73989     },
  73990 #endif /* chips */
  73991 
  73992 #if defined(BCM_88675_A0)
  73993     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88675_A0r */
  73994         soc_block_list[27],
  73995         soc_genreg,
  73996         3,
  73997         0,
  73998         0x170,
  73999         SOC_REG_FLAG_ARRAY |
  74000                           SOC_REG_FLAG_WO |
  74001                           SOC_REG_FLAG_REG_ARRAY,
  74002         0,
  74003         4,
  74004         soc_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88675_A0r_fields,
  74005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74006         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74007         -1,
  74008         -1,
  74009     },
  74010 #endif /* chips */
  74011 
  74012 #if defined(BCM_88675_B0)
  74013     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88675_B0r */
  74014         soc_block_list[27],
  74015         soc_genreg,
  74016         3,
  74017         0,
  74018         0x170,
  74019         SOC_REG_FLAG_ARRAY |
  74020                           SOC_REG_FLAG_WO |
  74021                           SOC_REG_FLAG_REG_ARRAY,
  74022         0,
  74023         4,
  74024         soc_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88675_B0r_fields,
  74025         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74026         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74027         -1,
  74028         -1,
  74029     },
  74030 #endif /* chips */
  74031 
  74032 #if defined(BCM_88680_A0)
  74033     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88680_A0r */
  74034         soc_block_list[27],
  74035         soc_genreg,
  74036         3,
  74037         0,
  74038         0x170,
  74039         SOC_REG_FLAG_ARRAY |
  74040                           SOC_REG_FLAG_WO |
  74041                           SOC_REG_FLAG_REG_ARRAY,
  74042         0,
  74043         4,
  74044         soc_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88680_A0r_fields,
  74045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74046         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74047         -1,
  74048         -1,
  74049     },
  74050 #endif /* chips */
  74051 
  74052 #if defined(BCM_88950_A0)
  74053     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88950_A0r */
  74054         soc_block_list[27],
  74055         soc_genreg,
  74056         3,
  74057         0,
  74058         0x170,
  74059         SOC_REG_FLAG_ARRAY |
  74060                           SOC_REG_FLAG_WO |
  74061                           SOC_REG_FLAG_REG_ARRAY,
  74062         0,
  74063         4,
  74064         soc_BRDC_FSRD_SRD_QUAD_LN_STRAPS_BCM88950_A0r_fields,
  74065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74066         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74067         -1,
  74068         -1,
  74069     },
  74070 #endif /* chips */
  74071 
  74072 #if defined(BCM_88650_A0)
  74073     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUSr */
  74074         soc_block_list[27],
  74075         soc_genreg,
  74076         3,
  74077         0,
  74078         0x178,
  74079         SOC_REG_FLAG_ARRAY |
  74080                           SOC_REG_FLAG_WO |
  74081                           SOC_REG_FLAG_REG_ARRAY,
  74082         0,
  74083         4,
  74084         soc_BRDC_FSRD_SRD_QUAD_STATUSr_fields,
  74085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74086         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74087         -1,
  74088         -1,
  74089     },
  74090 #endif /* chips */
  74091 
  74092 #if defined(BCM_88202_A0)
  74093     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88202_A0r */
  74094         soc_block_list[27],
  74095         soc_genreg,
  74096         3,
  74097         0,
  74098         0x178,
  74099         SOC_REG_FLAG_ARRAY |
  74100                           SOC_REG_FLAG_WO |
  74101                           SOC_REG_FLAG_REG_ARRAY,
  74102         0,
  74103         4,
  74104         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88202_A0r_fields,
  74105         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74106         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74107         -1,
  74108         -1,
  74109     },
  74110 #endif /* chips */
  74111 
  74112 #if defined(BCM_88375_A0)
  74113     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88375_A0r */
  74114         soc_block_list[27],
  74115         soc_genreg,
  74116         3,
  74117         0,
  74118         0x178,
  74119         SOC_REG_FLAG_ARRAY |
  74120                           SOC_REG_FLAG_RO |
  74121                           SOC_REG_FLAG_WO |
  74122                           SOC_REG_FLAG_REG_ARRAY,
  74123         0,
  74124         4,
  74125         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88375_A0r_fields,
  74126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74127         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74128         -1,
  74129         -1,
  74130     },
  74131 #endif /* chips */
  74132 
  74133 #if defined(BCM_88375_B0)
  74134     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88375_B0r */
  74135         soc_block_list[27],
  74136         soc_genreg,
  74137         3,
  74138         0,
  74139         0x178,
  74140         SOC_REG_FLAG_ARRAY |
  74141                           SOC_REG_FLAG_RO |
  74142                           SOC_REG_FLAG_WO |
  74143                           SOC_REG_FLAG_REG_ARRAY,
  74144         0,
  74145         4,
  74146         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88375_B0r_fields,
  74147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74148         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74149         -1,
  74150         -1,
  74151     },
  74152 #endif /* chips */
  74153 
  74154 #if defined(BCM_88650_B0)
  74155     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88650_B0r */
  74156         soc_block_list[27],
  74157         soc_genreg,
  74158         3,
  74159         0,
  74160         0x178,
  74161         SOC_REG_FLAG_ARRAY |
  74162                           SOC_REG_FLAG_WO |
  74163                           SOC_REG_FLAG_REG_ARRAY,
  74164         0,
  74165         4,
  74166         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88650_B0r_fields,
  74167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74168         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74169         -1,
  74170         -1,
  74171     },
  74172 #endif /* chips */
  74173 
  74174 #if defined(BCM_88660_A0)
  74175     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88660_A0r */
  74176         soc_block_list[27],
  74177         soc_genreg,
  74178         3,
  74179         0,
  74180         0x178,
  74181         SOC_REG_FLAG_ARRAY |
  74182                           SOC_REG_FLAG_WO |
  74183                           SOC_REG_FLAG_REG_ARRAY,
  74184         0,
  74185         4,
  74186         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88660_A0r_fields,
  74187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74188         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74189         -1,
  74190         -1,
  74191     },
  74192 #endif /* chips */
  74193 
  74194 #if defined(BCM_88675_A0)
  74195     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88675_A0r */
  74196         soc_block_list[27],
  74197         soc_genreg,
  74198         3,
  74199         0,
  74200         0x178,
  74201         SOC_REG_FLAG_ARRAY |
  74202                           SOC_REG_FLAG_RO |
  74203                           SOC_REG_FLAG_WO |
  74204                           SOC_REG_FLAG_REG_ARRAY,
  74205         0,
  74206         4,
  74207         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88675_A0r_fields,
  74208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74209         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74210         -1,
  74211         -1,
  74212     },
  74213 #endif /* chips */
  74214 
  74215 #if defined(BCM_88675_B0)
  74216     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88675_B0r */
  74217         soc_block_list[27],
  74218         soc_genreg,
  74219         3,
  74220         0,
  74221         0x178,
  74222         SOC_REG_FLAG_ARRAY |
  74223                           SOC_REG_FLAG_RO |
  74224                           SOC_REG_FLAG_WO |
  74225                           SOC_REG_FLAG_REG_ARRAY,
  74226         0,
  74227         4,
  74228         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88675_B0r_fields,
  74229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74230         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74231         -1,
  74232         -1,
  74233     },
  74234 #endif /* chips */
  74235 
  74236 #if defined(BCM_88680_A0)
  74237     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88680_A0r */
  74238         soc_block_list[27],
  74239         soc_genreg,
  74240         3,
  74241         0,
  74242         0x178,
  74243         SOC_REG_FLAG_ARRAY |
  74244                           SOC_REG_FLAG_RO |
  74245                           SOC_REG_FLAG_WO |
  74246                           SOC_REG_FLAG_REG_ARRAY,
  74247         0,
  74248         4,
  74249         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88680_A0r_fields,
  74250         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74251         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74252         -1,
  74253         -1,
  74254     },
  74255 #endif /* chips */
  74256 
  74257 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  74258     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88750_A0r */
  74259         soc_block_list[27],
  74260         soc_genreg,
  74261         4,
  74262         0,
  74263         0x78,
  74264         SOC_REG_FLAG_ARRAY |
  74265                           SOC_REG_FLAG_RO |
  74266                           SOC_REG_FLAG_WO |
  74267                           SOC_REG_FLAG_REG_ARRAY,
  74268         0,
  74269         4,
  74270         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88750_A0r_fields,
  74271         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74272         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74273         -1,
  74274         -1,
  74275     },
  74276 #endif /* chips */
  74277 
  74278 #if defined(BCM_88950_A0)
  74279     { /* SOC_REG_INT_BRDC_FSRD_SRD_QUAD_STATUS_BCM88950_A0r */
  74280         soc_block_list[27],
  74281         soc_genreg,
  74282         3,
  74283         0,
  74284         0x178,
  74285         SOC_REG_FLAG_ARRAY |
  74286                           SOC_REG_FLAG_RO |
  74287                           SOC_REG_FLAG_WO |
  74288                           SOC_REG_FLAG_REG_ARRAY,
  74289         0,
  74290         4,
  74291         soc_BRDC_FSRD_SRD_QUAD_STATUS_BCM88950_A0r_fields,
  74292         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74293         SOC_RESET_MASK_DEC(0x00001fff, 0x00000000)
  74294         -1,
  74295         -1,
  74296     },
  74297 #endif /* chips */
  74298 
  74299 #if defined(BCM_88790_A0)
  74300     { /* SOC_REG_INT_BRDC_FSRD_SRD_STATUSr */
  74301         soc_block_list[27],
  74302         soc_genreg,
  74303         1,
  74304         0,
  74305         0x10b,
  74306         SOC_REG_FLAG_RO |
  74307                           SOC_REG_FLAG_WO,
  74308         0,
  74309         5,
  74310         soc_BRDC_FSRD_SRD_STATUSr_fields,
  74311         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74312         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  74313         -1,
  74314         -1,
  74315     },
  74316 #endif /* chips */
  74317 
  74318 #if defined(BCM_88690_A0)
  74319     { /* SOC_REG_INT_BRDC_FSRD_SRD_STATUS_BCM88690_A0r */
  74320         soc_block_list[27],
  74321         soc_genreg,
  74322         1,
  74323         0,
  74324         0x10b,
  74325         SOC_REG_FLAG_RO |
  74326                           SOC_REG_FLAG_WO,
  74327         0,
  74328         5,
  74329         soc_BRDC_FSRD_SRD_STATUS_BCM88690_A0r_fields,
  74330         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74331         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  74332         -1,
  74333         -1,
  74334     },
  74335 #endif /* chips */
  74336 
  74337 #if defined(BCM_88690_B0)
  74338     { /* SOC_REG_INT_BRDC_FSRD_SRD_STATUS_BCM88690_B0r */
  74339         soc_block_list[27],
  74340         soc_genreg,
  74341         1,
  74342         0,
  74343         0x10b,
  74344         SOC_REG_FLAG_RO |
  74345                           SOC_REG_FLAG_WO,
  74346         0,
  74347         5,
  74348         soc_BRDC_FSRD_SRD_STATUS_BCM88690_B0r_fields,
  74349         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74350         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  74351         -1,
  74352         -1,
  74353     },
  74354 #endif /* chips */
  74355 
  74356 #if defined(BCM_88675_A0)
  74357     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECTr */
  74358         soc_block_list[27],
  74359         soc_genreg,
  74360         1,
  74361         0,
  74362         0x206,
  74363         SOC_REG_FLAG_WO,
  74364         0,
  74365         4,
  74366         soc_BRDC_FSRD_SYNC_E_SELECTr_fields,
  74367         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74368         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74369         -1,
  74370         -1,
  74371     },
  74372 #endif /* chips */
  74373 
  74374 #if defined(BCM_88375_A0)
  74375     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88375_A0r */
  74376         soc_block_list[27],
  74377         soc_genreg,
  74378         1,
  74379         0,
  74380         0x206,
  74381         SOC_REG_FLAG_WO,
  74382         0,
  74383         4,
  74384         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88375_A0r_fields,
  74385         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74386         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74387         -1,
  74388         -1,
  74389     },
  74390 #endif /* chips */
  74391 
  74392 #if defined(BCM_88375_B0)
  74393     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88375_B0r */
  74394         soc_block_list[27],
  74395         soc_genreg,
  74396         1,
  74397         0,
  74398         0x206,
  74399         SOC_REG_FLAG_WO,
  74400         0,
  74401         4,
  74402         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88375_B0r_fields,
  74403         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74404         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74405         -1,
  74406         -1,
  74407     },
  74408 #endif /* chips */
  74409 
  74410 #if defined(BCM_88675_B0)
  74411     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88675_B0r */
  74412         soc_block_list[27],
  74413         soc_genreg,
  74414         1,
  74415         0,
  74416         0x206,
  74417         SOC_REG_FLAG_WO,
  74418         0,
  74419         4,
  74420         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88675_B0r_fields,
  74421         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74422         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74423         -1,
  74424         -1,
  74425     },
  74426 #endif /* chips */
  74427 
  74428 #if defined(BCM_88680_A0)
  74429     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88680_A0r */
  74430         soc_block_list[27],
  74431         soc_genreg,
  74432         1,
  74433         0,
  74434         0x206,
  74435         SOC_REG_FLAG_WO,
  74436         0,
  74437         4,
  74438         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88680_A0r_fields,
  74439         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74440         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74441         -1,
  74442         -1,
  74443     },
  74444 #endif /* chips */
  74445 
  74446 #if defined(BCM_88690_A0)
  74447     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88690_A0r */
  74448         soc_block_list[27],
  74449         soc_genreg,
  74450         1,
  74451         0,
  74452         0x113,
  74453         SOC_REG_FLAG_WO,
  74454         0,
  74455         4,
  74456         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88690_A0r_fields,
  74457         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74458         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74459         -1,
  74460         -1,
  74461     },
  74462 #endif /* chips */
  74463 
  74464 #if defined(BCM_88690_B0)
  74465     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88690_B0r */
  74466         soc_block_list[27],
  74467         soc_genreg,
  74468         1,
  74469         0,
  74470         0x113,
  74471         SOC_REG_FLAG_WO,
  74472         0,
  74473         4,
  74474         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88690_B0r_fields,
  74475         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74476         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74477         -1,
  74478         -1,
  74479     },
  74480 #endif /* chips */
  74481 
  74482 #if defined(BCM_88790_A0)
  74483     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88790_A0r */
  74484         soc_block_list[27],
  74485         soc_genreg,
  74486         1,
  74487         0,
  74488         0x113,
  74489         SOC_REG_FLAG_WO,
  74490         0,
  74491         4,
  74492         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88790_A0r_fields,
  74493         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74494         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74495         -1,
  74496         -1,
  74497     },
  74498 #endif /* chips */
  74499 
  74500 #if defined(BCM_88950_A0)
  74501     { /* SOC_REG_INT_BRDC_FSRD_SYNC_E_SELECT_BCM88950_A0r */
  74502         soc_block_list[27],
  74503         soc_genreg,
  74504         1,
  74505         0,
  74506         0x206,
  74507         SOC_REG_FLAG_WO,
  74508         0,
  74509         4,
  74510         soc_BRDC_FSRD_SYNC_E_SELECT_BCM88950_A0r_fields,
  74511         SOC_RESET_VAL_DEC(0x0000a510, 0x00000000)
  74512         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  74513         -1,
  74514         -1,
  74515     },
  74516 #endif /* chips */
  74517 
  74518 #if defined(BCM_88790_A0)
  74519     { /* SOC_REG_INT_BRDC_FSRD_TX_ILKN_CREDITr */
  74520         soc_block_list[27],
  74521         soc_genreg,
  74522         1,
  74523         0,
  74524         0x114,
  74525         SOC_REG_FLAG_WO,
  74526         0,
  74527         2,
  74528         soc_BRDC_FSRD_TX_ILKN_CREDITr_fields,
  74529         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74530         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  74531         -1,
  74532         -1,
  74533     },
  74534 #endif /* chips */
  74535 
  74536 #if defined(BCM_88690_A0)
  74537     { /* SOC_REG_INT_BRDC_FSRD_TX_ILKN_CREDIT_BCM88690_A0r */
  74538         soc_block_list[27],
  74539         soc_genreg,
  74540         1,
  74541         0,
  74542         0x114,
  74543         SOC_REG_FLAG_WO,
  74544         0,
  74545         2,
  74546         soc_BRDC_FSRD_TX_ILKN_CREDIT_BCM88690_A0r_fields,
  74547         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74548         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  74549         -1,
  74550         -1,
  74551     },
  74552 #endif /* chips */
  74553 
  74554 #if defined(BCM_88690_B0)
  74555     { /* SOC_REG_INT_BRDC_FSRD_TX_ILKN_CREDIT_BCM88690_B0r */
  74556         soc_block_list[27],
  74557         soc_genreg,
  74558         1,
  74559         0,
  74560         0x114,
  74561         SOC_REG_FLAG_WO,
  74562         0,
  74563         2,
  74564         soc_BRDC_FSRD_TX_ILKN_CREDIT_BCM88690_B0r_fields,
  74565         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74566         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  74567         -1,
  74568         -1,
  74569     },
  74570 #endif /* chips */
  74571 
  74572 #if defined(BCM_88650_A0)
  74573     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESSr */
  74574         soc_block_list[27],
  74575         soc_genreg,
  74576         1,
  74577         0,
  74578         0x180,
  74579         SOC_REG_FLAG_WO,
  74580         0,
  74581         6,
  74582         soc_BRDC_FSRD_WC_UC_MEM_ACCESSr_fields,
  74583         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  74584         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  74585         -1,
  74586         -1,
  74587     },
  74588 #endif /* chips */
  74589 
  74590 #if defined(BCM_88202_A0)
  74591     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88202_A0r */
  74592         soc_block_list[27],
  74593         soc_genreg,
  74594         1,
  74595         0,
  74596         0x280,
  74597         SOC_REG_FLAG_WO,
  74598         0,
  74599         6,
  74600         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88202_A0r_fields,
  74601         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  74602         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  74603         -1,
  74604         -1,
  74605     },
  74606 #endif /* chips */
  74607 
  74608 #if defined(BCM_88375_A0)
  74609     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88375_A0r */
  74610         soc_block_list[27],
  74611         soc_genreg,
  74612         1,
  74613         0,
  74614         0x200,
  74615         SOC_REG_FLAG_WO,
  74616         0,
  74617         2,
  74618         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88375_A0r_fields,
  74619         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  74620         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74621         -1,
  74622         -1,
  74623     },
  74624 #endif /* chips */
  74625 
  74626 #if defined(BCM_88375_B0)
  74627     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88375_B0r */
  74628         soc_block_list[27],
  74629         soc_genreg,
  74630         1,
  74631         0,
  74632         0x200,
  74633         SOC_REG_FLAG_WO,
  74634         0,
  74635         2,
  74636         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88375_B0r_fields,
  74637         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  74638         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74639         -1,
  74640         -1,
  74641     },
  74642 #endif /* chips */
  74643 
  74644 #if defined(BCM_88650_B0)
  74645     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88650_B0r */
  74646         soc_block_list[27],
  74647         soc_genreg,
  74648         1,
  74649         0,
  74650         0x180,
  74651         SOC_REG_FLAG_WO,
  74652         0,
  74653         6,
  74654         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88650_B0r_fields,
  74655         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  74656         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  74657         -1,
  74658         -1,
  74659     },
  74660 #endif /* chips */
  74661 
  74662 #if defined(BCM_88660_A0)
  74663     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88660_A0r */
  74664         soc_block_list[27],
  74665         soc_genreg,
  74666         1,
  74667         0,
  74668         0x180,
  74669         SOC_REG_FLAG_WO,
  74670         0,
  74671         6,
  74672         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88660_A0r_fields,
  74673         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  74674         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  74675         -1,
  74676         -1,
  74677     },
  74678 #endif /* chips */
  74679 
  74680 #if defined(BCM_88675_A0)
  74681     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88675_A0r */
  74682         soc_block_list[27],
  74683         soc_genreg,
  74684         1,
  74685         0,
  74686         0x200,
  74687         SOC_REG_FLAG_WO,
  74688         0,
  74689         2,
  74690         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88675_A0r_fields,
  74691         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  74692         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74693         -1,
  74694         -1,
  74695     },
  74696 #endif /* chips */
  74697 
  74698 #if defined(BCM_88675_B0)
  74699     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88675_B0r */
  74700         soc_block_list[27],
  74701         soc_genreg,
  74702         1,
  74703         0,
  74704         0x200,
  74705         SOC_REG_FLAG_WO,
  74706         0,
  74707         2,
  74708         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88675_B0r_fields,
  74709         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  74710         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74711         -1,
  74712         -1,
  74713     },
  74714 #endif /* chips */
  74715 
  74716 #if defined(BCM_88680_A0)
  74717     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88680_A0r */
  74718         soc_block_list[27],
  74719         soc_genreg,
  74720         1,
  74721         0,
  74722         0x200,
  74723         SOC_REG_FLAG_WO,
  74724         0,
  74725         2,
  74726         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88680_A0r_fields,
  74727         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  74728         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74729         -1,
  74730         -1,
  74731     },
  74732 #endif /* chips */
  74733 
  74734 #if defined(BCM_88690_A0)
  74735     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88690_A0r */
  74736         soc_block_list[27],
  74737         soc_genreg,
  74738         1,
  74739         0,
  74740         0x10c,
  74741         SOC_REG_FLAG_WO,
  74742         0,
  74743         1,
  74744         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88690_A0r_fields,
  74745         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  74746         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  74747         -1,
  74748         -1,
  74749     },
  74750 #endif /* chips */
  74751 
  74752 #if defined(BCM_88690_B0)
  74753     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88690_B0r */
  74754         soc_block_list[27],
  74755         soc_genreg,
  74756         1,
  74757         0,
  74758         0x10c,
  74759         SOC_REG_FLAG_WO,
  74760         0,
  74761         1,
  74762         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88690_B0r_fields,
  74763         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  74764         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  74765         -1,
  74766         -1,
  74767     },
  74768 #endif /* chips */
  74769 
  74770 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  74771     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88750_A0r */
  74772         soc_block_list[27],
  74773         soc_genreg,
  74774         1,
  74775         0,
  74776         0x80,
  74777         SOC_REG_FLAG_WO,
  74778         0,
  74779         6,
  74780         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88750_A0r_fields,
  74781         SOC_RESET_VAL_DEC(0x00000400, 0x00000000)
  74782         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  74783         -1,
  74784         -1,
  74785     },
  74786 #endif /* chips */
  74787 
  74788 #if defined(BCM_88790_A0)
  74789     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88790_A0r */
  74790         soc_block_list[27],
  74791         soc_genreg,
  74792         1,
  74793         0,
  74794         0x10c,
  74795         SOC_REG_FLAG_WO,
  74796         0,
  74797         1,
  74798         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88790_A0r_fields,
  74799         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  74800         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  74801         -1,
  74802         -1,
  74803     },
  74804 #endif /* chips */
  74805 
  74806 #if defined(BCM_88950_A0)
  74807     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88950_A0r */
  74808         soc_block_list[27],
  74809         soc_genreg,
  74810         1,
  74811         0,
  74812         0x200,
  74813         SOC_REG_FLAG_WO,
  74814         0,
  74815         2,
  74816         soc_BRDC_FSRD_WC_UC_MEM_ACCESS_BCM88950_A0r_fields,
  74817         SOC_RESET_VAL_DEC(0x00000004, 0x00000000)
  74818         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74819         -1,
  74820         -1,
  74821     },
  74822 #endif /* chips */
  74823 
  74824 #if defined(BCM_88650_A0)
  74825     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAPr */
  74826         soc_block_list[27],
  74827         soc_genreg,
  74828         1,
  74829         0,
  74830         0x181,
  74831         SOC_REG_FLAG_WO,
  74832         0,
  74833         1,
  74834         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAPr_fields,
  74835         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74836         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74837         -1,
  74838         -1,
  74839     },
  74840 #endif /* chips */
  74841 
  74842 #if defined(BCM_88202_A0)
  74843     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88202_A0r */
  74844         soc_block_list[27],
  74845         soc_genreg,
  74846         1,
  74847         0,
  74848         0x281,
  74849         SOC_REG_FLAG_WO,
  74850         0,
  74851         1,
  74852         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88202_A0r_fields,
  74853         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74854         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74855         -1,
  74856         -1,
  74857     },
  74858 #endif /* chips */
  74859 
  74860 #if defined(BCM_88375_A0)
  74861     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88375_A0r */
  74862         soc_block_list[27],
  74863         soc_genreg,
  74864         1,
  74865         0,
  74866         0x201,
  74867         SOC_REG_FLAG_WO,
  74868         0,
  74869         1,
  74870         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88375_A0r_fields,
  74871         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  74872         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74873         -1,
  74874         -1,
  74875     },
  74876 #endif /* chips */
  74877 
  74878 #if defined(BCM_88375_B0)
  74879     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88375_B0r */
  74880         soc_block_list[27],
  74881         soc_genreg,
  74882         1,
  74883         0,
  74884         0x201,
  74885         SOC_REG_FLAG_WO,
  74886         0,
  74887         1,
  74888         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88375_B0r_fields,
  74889         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  74890         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74891         -1,
  74892         -1,
  74893     },
  74894 #endif /* chips */
  74895 
  74896 #if defined(BCM_88650_B0)
  74897     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88650_B0r */
  74898         soc_block_list[27],
  74899         soc_genreg,
  74900         1,
  74901         0,
  74902         0x181,
  74903         SOC_REG_FLAG_WO,
  74904         0,
  74905         1,
  74906         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88650_B0r_fields,
  74907         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74908         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74909         -1,
  74910         -1,
  74911     },
  74912 #endif /* chips */
  74913 
  74914 #if defined(BCM_88660_A0)
  74915     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88660_A0r */
  74916         soc_block_list[27],
  74917         soc_genreg,
  74918         1,
  74919         0,
  74920         0x181,
  74921         SOC_REG_FLAG_WO,
  74922         0,
  74923         1,
  74924         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88660_A0r_fields,
  74925         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  74926         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74927         -1,
  74928         -1,
  74929     },
  74930 #endif /* chips */
  74931 
  74932 #if defined(BCM_88675_A0)
  74933     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88675_A0r */
  74934         soc_block_list[27],
  74935         soc_genreg,
  74936         1,
  74937         0,
  74938         0x201,
  74939         SOC_REG_FLAG_WO,
  74940         0,
  74941         1,
  74942         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88675_A0r_fields,
  74943         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  74944         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74945         -1,
  74946         -1,
  74947     },
  74948 #endif /* chips */
  74949 
  74950 #if defined(BCM_88675_B0)
  74951     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88675_B0r */
  74952         soc_block_list[27],
  74953         soc_genreg,
  74954         1,
  74955         0,
  74956         0x201,
  74957         SOC_REG_FLAG_WO,
  74958         0,
  74959         1,
  74960         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88675_B0r_fields,
  74961         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  74962         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74963         -1,
  74964         -1,
  74965     },
  74966 #endif /* chips */
  74967 
  74968 #if defined(BCM_88680_A0)
  74969     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88680_A0r */
  74970         soc_block_list[27],
  74971         soc_genreg,
  74972         1,
  74973         0,
  74974         0x201,
  74975         SOC_REG_FLAG_WO,
  74976         0,
  74977         1,
  74978         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88680_A0r_fields,
  74979         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  74980         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  74981         -1,
  74982         -1,
  74983     },
  74984 #endif /* chips */
  74985 
  74986 #if defined(BCM_88750_A0) || defined(BCM_88750_B0)
  74987     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88750_A0r */
  74988         soc_block_list[27],
  74989         soc_genreg,
  74990         1,
  74991         0,
  74992         0x81,
  74993         SOC_REG_FLAG_WO,
  74994         0,
  74995         1,
  74996         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88750_A0r_fields,
  74997         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  74998         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  74999         -1,
  75000         -1,
  75001     },
  75002 #endif /* chips */
  75003 
  75004 #if defined(BCM_88950_A0)
  75005     { /* SOC_REG_INT_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88950_A0r */
  75006         soc_block_list[27],
  75007         soc_genreg,
  75008         1,
  75009         0,
  75010         0x201,
  75011         SOC_REG_FLAG_WO,
  75012         0,
  75013         1,
  75014         soc_BRDC_FSRD_WC_UC_MEM_MASK_BITMAP_BCM88950_A0r_fields,
  75015         SOC_RESET_VAL_DEC(0x00000007, 0x00000000)
  75016         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75017         -1,
  75018         -1,
  75019     },
  75020 #endif /* chips */
  75021 
  75022 #if defined(BCM_88690_A0)
  75023     { /* SOC_REG_INT_BRDC_HBC_BIST_ADDR_CONFIGr */
  75024         soc_block_list[169],
  75025         soc_genreg,
  75026         1,
  75027         0,
  75028         0x1c2,
  75029         SOC_REG_FLAG_ABOVE_64_BITS,
  75030         0,
  75031         12,
  75032         soc_BRDC_HBC_BIST_ADDR_CONFIGr_fields,
  75033         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75034         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75035         -1,
  75036         -1,
  75037     },
  75038 #endif /* chips */
  75039 
  75040 #if defined(BCM_88690_B0)
  75041     { /* SOC_REG_INT_BRDC_HBC_BIST_ADDR_CONFIG_BCM88690_B0r */
  75042         soc_block_list[169],
  75043         soc_genreg,
  75044         1,
  75045         0,
  75046         0x1a1,
  75047         SOC_REG_FLAG_ABOVE_64_BITS |
  75048                           SOC_REG_FLAG_WO,
  75049         0,
  75050         12,
  75051         soc_BRDC_HBC_BIST_ADDR_CONFIG_BCM88690_B0r_fields,
  75052         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75053         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75054         -1,
  75055         -1,
  75056     },
  75057 #endif /* chips */
  75058 
  75059 #if defined(BCM_88690_A0)
  75060     { /* SOC_REG_INT_BRDC_HBC_BIST_BANK_REORDERr */
  75061         soc_block_list[169],
  75062         soc_genreg,
  75063         1,
  75064         0,
  75065         0x1c5,
  75066         0,
  75067         0,
  75068         5,
  75069         soc_BRDC_HBC_BIST_BANK_REORDERr_fields,
  75070         SOC_RESET_VAL_DEC(0x00000463, 0x00000000)
  75071         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75072         -1,
  75073         -1,
  75074     },
  75075 #endif /* chips */
  75076 
  75077 #if defined(BCM_88690_B0)
  75078     { /* SOC_REG_INT_BRDC_HBC_BIST_BANK_REORDER_BCM88690_B0r */
  75079         soc_block_list[169],
  75080         soc_genreg,
  75081         1,
  75082         0,
  75083         0x1a4,
  75084         SOC_REG_FLAG_WO,
  75085         0,
  75086         5,
  75087         soc_BRDC_HBC_BIST_BANK_REORDER_BCM88690_B0r_fields,
  75088         SOC_RESET_VAL_DEC(0x00000463, 0x00000000)
  75089         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  75090         -1,
  75091         -1,
  75092     },
  75093 #endif /* chips */
  75094 
  75095 #if defined(BCM_88690_A0)
  75096     { /* SOC_REG_INT_BRDC_HBC_BIST_COMMAND_CONFIGr */
  75097         soc_block_list[169],
  75098         soc_genreg,
  75099         1,
  75100         0,
  75101         0x1bf,
  75102         SOC_REG_FLAG_ABOVE_64_BITS,
  75103         0,
  75104         4,
  75105         soc_BRDC_HBC_BIST_COMMAND_CONFIGr_fields,
  75106         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75107         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75108         -1,
  75109         -1,
  75110     },
  75111 #endif /* chips */
  75112 
  75113 #if defined(BCM_88690_B0)
  75114     { /* SOC_REG_INT_BRDC_HBC_BIST_COMMAND_CONFIG_BCM88690_B0r */
  75115         soc_block_list[169],
  75116         soc_genreg,
  75117         1,
  75118         0,
  75119         0x19e,
  75120         SOC_REG_FLAG_ABOVE_64_BITS |
  75121                           SOC_REG_FLAG_WO,
  75122         0,
  75123         4,
  75124         soc_BRDC_HBC_BIST_COMMAND_CONFIG_BCM88690_B0r_fields,
  75125         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75126         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75127         -1,
  75128         -1,
  75129     },
  75130 #endif /* chips */
  75131 
  75132 #if defined(BCM_88690_A0)
  75133     { /* SOC_REG_INT_BRDC_HBC_BIST_CONTROLr */
  75134         soc_block_list[169],
  75135         soc_genreg,
  75136         1,
  75137         0,
  75138         0x1ba,
  75139         0,
  75140         0,
  75141         3,
  75142         soc_BRDC_HBC_BIST_CONTROLr_fields,
  75143         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75144         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75145         -1,
  75146         -1,
  75147     },
  75148 #endif /* chips */
  75149 
  75150 #if defined(BCM_88690_B0)
  75151     { /* SOC_REG_INT_BRDC_HBC_BIST_CONTROL_BCM88690_B0r */
  75152         soc_block_list[169],
  75153         soc_genreg,
  75154         1,
  75155         0,
  75156         0x199,
  75157         SOC_REG_FLAG_WO,
  75158         0,
  75159         3,
  75160         soc_BRDC_HBC_BIST_CONTROL_BCM88690_B0r_fields,
  75161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75162         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75163         -1,
  75164         -1,
  75165     },
  75166 #endif /* chips */
  75167 
  75168 #if defined(BCM_88690_A0)
  75169     { /* SOC_REG_INT_BRDC_HBC_BIST_DATA_CONFIGr */
  75170         soc_block_list[169],
  75171         soc_genreg,
  75172         1,
  75173         0,
  75174         0x1c6,
  75175         0,
  75176         0,
  75177         3,
  75178         soc_BRDC_HBC_BIST_DATA_CONFIGr_fields,
  75179         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75180         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  75181         -1,
  75182         -1,
  75183     },
  75184 #endif /* chips */
  75185 
  75186 #if defined(BCM_88690_B0)
  75187     { /* SOC_REG_INT_BRDC_HBC_BIST_DATA_CONFIG_BCM88690_B0r */
  75188         soc_block_list[169],
  75189         soc_genreg,
  75190         1,
  75191         0,
  75192         0x1a5,
  75193         SOC_REG_FLAG_WO,
  75194         0,
  75195         3,
  75196         soc_BRDC_HBC_BIST_DATA_CONFIG_BCM88690_B0r_fields,
  75197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75198         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  75199         -1,
  75200         -1,
  75201     },
  75202 #endif /* chips */
  75203 
  75204 #if defined(BCM_88690_A0)
  75205     { /* SOC_REG_INT_BRDC_HBC_BIST_DATA_MISR_MAPr */
  75206         soc_block_list[169],
  75207         soc_genreg,
  75208         1,
  75209         0,
  75210         0x21f,
  75211         SOC_REG_FLAG_ABOVE_64_BITS,
  75212         0,
  75213         20,
  75214         soc_BRDC_HBC_BIST_DATA_MISR_MAPr_fields,
  75215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75216         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75217         -1,
  75218         -1,
  75219     },
  75220 #endif /* chips */
  75221 
  75222 #if defined(BCM_88690_A0)
  75223     { /* SOC_REG_INT_BRDC_HBC_BIST_DATA_PRESETr */
  75224         soc_block_list[169],
  75225         soc_genreg,
  75226         16,
  75227         0,
  75228         0x20f,
  75229         SOC_REG_FLAG_ARRAY |
  75230                           SOC_REG_FLAG_REG_ARRAY,
  75231         0,
  75232         1,
  75233         soc_BRDC_HBC_BIST_DATA_PRESETr_fields,
  75234         SOC_RESET_VAL_DEC(0x000aaaaa, 0x00000000)
  75235         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  75236         -1,
  75237         -1,
  75238     },
  75239 #endif /* chips */
  75240 
  75241 #if defined(BCM_88690_B0)
  75242     { /* SOC_REG_INT_BRDC_HBC_BIST_DATA_PRESET_BCM88690_B0r */
  75243         soc_block_list[169],
  75244         soc_genreg,
  75245         16,
  75246         0,
  75247         0x1ee,
  75248         SOC_REG_FLAG_ARRAY |
  75249                           SOC_REG_FLAG_WO |
  75250                           SOC_REG_FLAG_REG_ARRAY,
  75251         0,
  75252         1,
  75253         soc_BRDC_HBC_BIST_DATA_PRESET_BCM88690_B0r_fields,
  75254         SOC_RESET_VAL_DEC(0x000aaaaa, 0x00000000)
  75255         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  75256         -1,
  75257         -1,
  75258     },
  75259 #endif /* chips */
  75260 
  75261 #if defined(BCM_88690_A0)
  75262     { /* SOC_REG_INT_BRDC_HBC_BIST_DWORD_MISR_STATEr */
  75263         soc_block_list[169],
  75264         soc_genreg,
  75265         1,
  75266         0,
  75267         0x22b,
  75268         SOC_REG_FLAG_ABOVE_64_BITS |
  75269                           SOC_REG_FLAG_RO,
  75270         0,
  75271         1,
  75272         soc_BRDC_HBC_BIST_DWORD_MISR_STATEr_fields,
  75273         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75274         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75275         -1,
  75276         -1,
  75277     },
  75278 #endif /* chips */
  75279 
  75280 #if defined(BCM_88690_B0)
  75281     { /* SOC_REG_INT_BRDC_HBC_BIST_DWORD_MISR_STATE_BCM88690_B0r */
  75282         soc_block_list[169],
  75283         soc_genreg,
  75284         1,
  75285         0,
  75286         0x206,
  75287         SOC_REG_FLAG_ABOVE_64_BITS |
  75288                           SOC_REG_FLAG_RO |
  75289                           SOC_REG_FLAG_WO,
  75290         0,
  75291         1,
  75292         soc_BRDC_HBC_BIST_DWORD_MISR_STATE_BCM88690_B0r_fields,
  75293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75294         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75295         -1,
  75296         -1,
  75297     },
  75298 #endif /* chips */
  75299 
  75300 #if defined(BCM_88690_A0)
  75301     { /* SOC_REG_INT_BRDC_HBC_BIST_ERR_COUNTERSr */
  75302         soc_block_list[169],
  75303         soc_genreg,
  75304         1,
  75305         0,
  75306         0x223,
  75307         SOC_REG_FLAG_ABOVE_64_BITS |
  75308                           SOC_REG_FLAG_RO,
  75309         SOC_REG_FLAG_COUNTER_FEILDS |
  75310                           SOC_REG_FLAG_INIT_ON_READ,
  75311         6,
  75312         soc_BRDC_HBC_BIST_ERR_COUNTERSr_fields,
  75313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75314         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75315         -1,
  75316         -1,
  75317     },
  75318 #endif /* chips */
  75319 
  75320 #if defined(BCM_88690_B0)
  75321     { /* SOC_REG_INT_BRDC_HBC_BIST_ERR_COUNTERS_BCM88690_B0r */
  75322         soc_block_list[169],
  75323         soc_genreg,
  75324         1,
  75325         0,
  75326         0x1fe,
  75327         SOC_REG_FLAG_ABOVE_64_BITS |
  75328                           SOC_REG_FLAG_RO |
  75329                           SOC_REG_FLAG_WO,
  75330         SOC_REG_FLAG_COUNTER_FEILDS |
  75331                           SOC_REG_FLAG_INIT_ON_READ,
  75332         6,
  75333         soc_BRDC_HBC_BIST_ERR_COUNTERS_BCM88690_B0r_fields,
  75334         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75335         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75336         -1,
  75337         -1,
  75338     },
  75339 #endif /* chips */
  75340 
  75341 #if defined(BCM_88690_A0)
  75342     { /* SOC_REG_INT_BRDC_HBC_BIST_PATTERNr */
  75343         soc_block_list[169],
  75344         soc_genreg,
  75345         8,
  75346         0,
  75347         0x1c7,
  75348         SOC_REG_FLAG_ABOVE_64_BITS |
  75349                           SOC_REG_FLAG_ARRAY |
  75350                           SOC_REG_FLAG_REG_ARRAY,
  75351         0,
  75352         2,
  75353         soc_BRDC_HBC_BIST_PATTERNr_fields,
  75354         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75355         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75356         -1,
  75357         -1,
  75358     },
  75359 #endif /* chips */
  75360 
  75361 #if defined(BCM_88690_B0)
  75362     { /* SOC_REG_INT_BRDC_HBC_BIST_PATTERN_BCM88690_B0r */
  75363         soc_block_list[169],
  75364         soc_genreg,
  75365         8,
  75366         0,
  75367         0x1a6,
  75368         SOC_REG_FLAG_ABOVE_64_BITS |
  75369                           SOC_REG_FLAG_ARRAY |
  75370                           SOC_REG_FLAG_WO |
  75371                           SOC_REG_FLAG_REG_ARRAY,
  75372         0,
  75373         2,
  75374         soc_BRDC_HBC_BIST_PATTERN_BCM88690_B0r_fields,
  75375         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75376         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75377         -1,
  75378         -1,
  75379     },
  75380 #endif /* chips */
  75381 
  75382 #if defined(BCM_88690_A0)
  75383     { /* SOC_REG_INT_BRDC_HBC_BIST_STATUSr */
  75384         soc_block_list[169],
  75385         soc_genreg,
  75386         1,
  75387         0,
  75388         0x1bb,
  75389         SOC_REG_FLAG_ABOVE_64_BITS |
  75390                           SOC_REG_FLAG_RO,
  75391         SOC_REG_FLAG_COUNTER_FEILDS |
  75392                           SOC_REG_FLAG_INIT_ON_READ,
  75393         5,
  75394         soc_BRDC_HBC_BIST_STATUSr_fields,
  75395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75397         -1,
  75398         -1,
  75399     },
  75400 #endif /* chips */
  75401 
  75402 #if defined(BCM_88690_B0)
  75403     { /* SOC_REG_INT_BRDC_HBC_BIST_STATUS_BCM88690_B0r */
  75404         soc_block_list[169],
  75405         soc_genreg,
  75406         1,
  75407         0,
  75408         0x19a,
  75409         SOC_REG_FLAG_ABOVE_64_BITS |
  75410                           SOC_REG_FLAG_RO |
  75411                           SOC_REG_FLAG_WO,
  75412         SOC_REG_FLAG_COUNTER_FEILDS |
  75413                           SOC_REG_FLAG_INIT_ON_READ,
  75414         5,
  75415         soc_BRDC_HBC_BIST_STATUS_BCM88690_B0r_fields,
  75416         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75417         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75418         -1,
  75419         -1,
  75420     },
  75421 #endif /* chips */
  75422 
  75423 #if defined(BCM_88690_A0)
  75424     { /* SOC_REG_INT_BRDC_HBC_BLOCKED_BY_COHERENCY_CNTr */
  75425         soc_block_list[169],
  75426         soc_genreg,
  75427         32,
  75428         0,
  75429         0x13a,
  75430         SOC_REG_FLAG_ARRAY |
  75431                           SOC_REG_FLAG_RO |
  75432                           SOC_REG_FLAG_REG_ARRAY,
  75433         SOC_REG_FLAG_COUNTER_FEILDS,
  75434         1,
  75435         soc_BRDC_HBC_BLOCKED_BY_COHERENCY_CNTr_fields,
  75436         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75437         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  75438         -1,
  75439         -1,
  75440     },
  75441 #endif /* chips */
  75442 
  75443 #if defined(BCM_88690_A0)
  75444     { /* SOC_REG_INT_BRDC_HBC_DATA_SOURCE_CONFIGr */
  75445         soc_block_list[169],
  75446         soc_genreg,
  75447         2,
  75448         0,
  75449         0x110,
  75450         SOC_REG_FLAG_ARRAY |
  75451                           SOC_REG_FLAG_REG_ARRAY,
  75452         0,
  75453         2,
  75454         soc_BRDC_HBC_DATA_SOURCE_CONFIGr_fields,
  75455         SOC_RESET_VAL_DEC(0x0003e9f4, 0x00000000)
  75456         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  75457         -1,
  75458         -1,
  75459     },
  75460 #endif /* chips */
  75461 
  75462 #if defined(BCM_88690_B0)
  75463     { /* SOC_REG_INT_BRDC_HBC_DATA_SOURCE_CONFIG_BCM88690_B0r */
  75464         soc_block_list[169],
  75465         soc_genreg,
  75466         2,
  75467         0,
  75468         0x10f,
  75469         SOC_REG_FLAG_ARRAY |
  75470                           SOC_REG_FLAG_WO |
  75471                           SOC_REG_FLAG_REG_ARRAY,
  75472         0,
  75473         2,
  75474         soc_BRDC_HBC_DATA_SOURCE_CONFIG_BCM88690_B0r_fields,
  75475         SOC_RESET_VAL_DEC(0x0003e9f4, 0x00000000)
  75476         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  75477         -1,
  75478         -1,
  75479     },
  75480 #endif /* chips */
  75481 
  75482 #if defined(BCM_88690_A0)
  75483     { /* SOC_REG_INT_BRDC_HBC_DRAM_CHANNEL_BLOCKED_CONFIGr */
  75484         soc_block_list[169],
  75485         soc_genreg,
  75486         1,
  75487         0,
  75488         0x176,
  75489         SOC_REG_FLAG_64_BITS,
  75490         0,
  75491         4,
  75492         soc_BRDC_HBC_DRAM_CHANNEL_BLOCKED_CONFIGr_fields,
  75493         SOC_RESET_VAL_DEC(0x3ec02711, 0x00006401)
  75494         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  75495         -1,
  75496         -1,
  75497     },
  75498 #endif /* chips */
  75499 
  75500 #if defined(BCM_88690_B0)
  75501     { /* SOC_REG_INT_BRDC_HBC_DRAM_CHANNEL_BLOCKED_CONFIG_BCM88690_B0r */
  75502         soc_block_list[169],
  75503         soc_genreg,
  75504         1,
  75505         0,
  75506         0x155,
  75507         SOC_REG_FLAG_64_BITS |
  75508                           SOC_REG_FLAG_WO,
  75509         0,
  75510         4,
  75511         soc_BRDC_HBC_DRAM_CHANNEL_BLOCKED_CONFIG_BCM88690_B0r_fields,
  75512         SOC_RESET_VAL_DEC(0x3ec02711, 0x00006401)
  75513         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  75514         -1,
  75515         -1,
  75516     },
  75517 #endif /* chips */
  75518 
  75519 #if defined(BCM_88690_A0)
  75520     { /* SOC_REG_INT_BRDC_HBC_DRAM_CHANNEL_BLOCKED_STATUSr */
  75521         soc_block_list[169],
  75522         soc_genreg,
  75523         1,
  75524         0,
  75525         0x178,
  75526         SOC_REG_FLAG_ABOVE_64_BITS |
  75527                           SOC_REG_FLAG_RO,
  75528         SOC_REG_FLAG_COUNTER_FEILDS |
  75529                           SOC_REG_FLAG_INIT_ON_READ,
  75530         3,
  75531         soc_BRDC_HBC_DRAM_CHANNEL_BLOCKED_STATUSr_fields,
  75532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75534         -1,
  75535         -1,
  75536     },
  75537 #endif /* chips */
  75538 
  75539 #if defined(BCM_88690_B0)
  75540     { /* SOC_REG_INT_BRDC_HBC_DRAM_CHANNEL_BLOCKED_STATUS_BCM88690_B0r */
  75541         soc_block_list[169],
  75542         soc_genreg,
  75543         1,
  75544         0,
  75545         0x157,
  75546         SOC_REG_FLAG_ABOVE_64_BITS |
  75547                           SOC_REG_FLAG_RO |
  75548                           SOC_REG_FLAG_WO,
  75549         SOC_REG_FLAG_COUNTER_FEILDS |
  75550                           SOC_REG_FLAG_INIT_ON_READ,
  75551         3,
  75552         soc_BRDC_HBC_DRAM_CHANNEL_BLOCKED_STATUS_BCM88690_B0r_fields,
  75553         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75554         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  75555         -1,
  75556         -1,
  75557     },
  75558 #endif /* chips */
  75559 
  75560 #if defined(BCM_88690_A0)
  75561     { /* SOC_REG_INT_BRDC_HBC_DSI_ASYNC_FIFO_CONFIGr */
  75562         soc_block_list[169],
  75563         soc_genreg,
  75564         2,
  75565         0,
  75566         0x112,
  75567         SOC_REG_FLAG_ARRAY |
  75568                           SOC_REG_FLAG_REG_ARRAY,
  75569         0,
  75570         16,
  75571         soc_BRDC_HBC_DSI_ASYNC_FIFO_CONFIGr_fields,
  75572         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75573         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  75574         -1,
  75575         -1,
  75576     },
  75577 #endif /* chips */
  75578 
  75579 #if defined(BCM_88690_B0)
  75580     { /* SOC_REG_INT_BRDC_HBC_DSI_ASYNC_FIFO_CONFIG_BCM88690_B0r */
  75581         soc_block_list[169],
  75582         soc_genreg,
  75583         2,
  75584         0,
  75585         0x111,
  75586         SOC_REG_FLAG_ARRAY |
  75587                           SOC_REG_FLAG_WO |
  75588                           SOC_REG_FLAG_REG_ARRAY,
  75589         0,
  75590         16,
  75591         soc_BRDC_HBC_DSI_ASYNC_FIFO_CONFIG_BCM88690_B0r_fields,
  75592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75593         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  75594         -1,
  75595         -1,
  75596     },
  75597 #endif /* chips */
  75598 
  75599 #if defined(BCM_88690_A0)
  75600     { /* SOC_REG_INT_BRDC_HBC_DSI_INTERRUPT_MASK_REGISTERr */
  75601         soc_block_list[169],
  75602         soc_genreg,
  75603         1,
  75604         0,
  75605         0x102,
  75606         SOC_REG_FLAG_64_BITS,
  75607         0,
  75608         36,
  75609         soc_BRDC_HBC_DSI_INTERRUPT_MASK_REGISTERr_fields,
  75610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75611         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  75612         -1,
  75613         -1,
  75614     },
  75615 #endif /* chips */
  75616 
  75617 #if defined(BCM_88690_B0)
  75618     { /* SOC_REG_INT_BRDC_HBC_DSI_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  75619         soc_block_list[169],
  75620         soc_genreg,
  75621         1,
  75622         0,
  75623         0x101,
  75624         SOC_REG_FLAG_WO,
  75625         0,
  75626         26,
  75627         soc_BRDC_HBC_DSI_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  75628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75629         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  75630         -1,
  75631         -1,
  75632     },
  75633 #endif /* chips */
  75634 
  75635 #if defined(BCM_88690_A0)
  75636     { /* SOC_REG_INT_BRDC_HBC_DSI_INTERRUPT_REGISTERr */
  75637         soc_block_list[169],
  75638         soc_genreg,
  75639         1,
  75640         0,
  75641         0x100,
  75642         SOC_REG_FLAG_64_BITS |
  75643                           SOC_REG_FLAG_INTERRUPT |
  75644                           SOC_REG_FLAG_SIGNAL,
  75645         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  75646         36,
  75647         soc_BRDC_HBC_DSI_INTERRUPT_REGISTERr_fields,
  75648         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75649         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  75650         -1,
  75651         -1,
  75652     },
  75653 #endif /* chips */
  75654 
  75655 #if defined(BCM_88690_B0)
  75656     { /* SOC_REG_INT_BRDC_HBC_DSI_INTERRUPT_REGISTER_BCM88690_B0r */
  75657         soc_block_list[169],
  75658         soc_genreg,
  75659         1,
  75660         0,
  75661         0x100,
  75662         SOC_REG_FLAG_WO |
  75663                           SOC_REG_FLAG_INTERRUPT |
  75664                           SOC_REG_FLAG_SIGNAL,
  75665         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  75666         26,
  75667         soc_BRDC_HBC_DSI_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  75668         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75669         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  75670         -1,
  75671         -1,
  75672     },
  75673 #endif /* chips */
  75674 
  75675 #if defined(BCM_88690_A0)
  75676     { /* SOC_REG_INT_BRDC_HBC_DSI_INTERRUPT_REGISTER_TESTr */
  75677         soc_block_list[169],
  75678         soc_genreg,
  75679         1,
  75680         0,
  75681         0x103,
  75682         SOC_REG_FLAG_64_BITS,
  75683         0,
  75684         1,
  75685         soc_BRDC_HBC_DSI_INTERRUPT_REGISTER_TESTr_fields,
  75686         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75687         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  75688         -1,
  75689         -1,
  75690     },
  75691 #endif /* chips */
  75692 
  75693 #if defined(BCM_88690_B0)
  75694     { /* SOC_REG_INT_BRDC_HBC_DSI_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  75695         soc_block_list[169],
  75696         soc_genreg,
  75697         1,
  75698         0,
  75699         0x102,
  75700         SOC_REG_FLAG_WO,
  75701         0,
  75702         1,
  75703         soc_BRDC_HBC_DSI_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  75704         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75705         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  75706         -1,
  75707         -1,
  75708     },
  75709 #endif /* chips */
  75710 
  75711 #if defined(BCM_88690_A0)
  75712     { /* SOC_REG_INT_BRDC_HBC_ECC_1B_ERR_CNTr */
  75713         soc_block_list[169],
  75714         soc_genreg,
  75715         1,
  75716         0,
  75717         0x94,
  75718         SOC_REG_FLAG_64_BITS |
  75719                           SOC_REG_FLAG_RO,
  75720         SOC_REG_FLAG_COUNTER_FEILDS |
  75721                           SOC_REG_FLAG_INIT_ON_READ,
  75722         4,
  75723         soc_BRDC_HBC_ECC_1B_ERR_CNTr_fields,
  75724         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75725         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  75726         -1,
  75727         -1,
  75728     },
  75729 #endif /* chips */
  75730 
  75731 #if defined(BCM_88690_B0)
  75732     { /* SOC_REG_INT_BRDC_HBC_ECC_1B_ERR_CNT_BCM88690_B0r */
  75733         soc_block_list[169],
  75734         soc_genreg,
  75735         1,
  75736         0,
  75737         0x94,
  75738         SOC_REG_FLAG_64_BITS |
  75739                           SOC_REG_FLAG_RO |
  75740                           SOC_REG_FLAG_WO,
  75741         SOC_REG_FLAG_COUNTER_FEILDS |
  75742                           SOC_REG_FLAG_INIT_ON_READ,
  75743         4,
  75744         soc_BRDC_HBC_ECC_1B_ERR_CNT_BCM88690_B0r_fields,
  75745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75746         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  75747         -1,
  75748         -1,
  75749     },
  75750 #endif /* chips */
  75751 
  75752 #if defined(BCM_88690_A0)
  75753     { /* SOC_REG_INT_BRDC_HBC_ECC_2B_ERR_CNTr */
  75754         soc_block_list[169],
  75755         soc_genreg,
  75756         1,
  75757         0,
  75758         0x96,
  75759         SOC_REG_FLAG_64_BITS |
  75760                           SOC_REG_FLAG_RO,
  75761         SOC_REG_FLAG_COUNTER_FEILDS |
  75762                           SOC_REG_FLAG_INIT_ON_READ,
  75763         4,
  75764         soc_BRDC_HBC_ECC_2B_ERR_CNTr_fields,
  75765         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75766         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  75767         -1,
  75768         -1,
  75769     },
  75770 #endif /* chips */
  75771 
  75772 #if defined(BCM_88690_B0)
  75773     { /* SOC_REG_INT_BRDC_HBC_ECC_2B_ERR_CNT_BCM88690_B0r */
  75774         soc_block_list[169],
  75775         soc_genreg,
  75776         1,
  75777         0,
  75778         0x96,
  75779         SOC_REG_FLAG_64_BITS |
  75780                           SOC_REG_FLAG_RO |
  75781                           SOC_REG_FLAG_WO,
  75782         SOC_REG_FLAG_COUNTER_FEILDS |
  75783                           SOC_REG_FLAG_INIT_ON_READ,
  75784         4,
  75785         soc_BRDC_HBC_ECC_2B_ERR_CNT_BCM88690_B0r_fields,
  75786         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75787         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  75788         -1,
  75789         -1,
  75790     },
  75791 #endif /* chips */
  75792 
  75793 #if defined(BCM_88690_A0)
  75794     { /* SOC_REG_INT_BRDC_HBC_ECC_ERR_1B_MONITOR_MEM_MASKr */
  75795         soc_block_list[169],
  75796         soc_genreg,
  75797         1,
  75798         0,
  75799         0x9a,
  75800         0,
  75801         0,
  75802         11,
  75803         soc_BRDC_HBC_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  75804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75805         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75806         -1,
  75807         -1,
  75808     },
  75809 #endif /* chips */
  75810 
  75811 #if defined(BCM_88690_B0)
  75812     { /* SOC_REG_INT_BRDC_HBC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r */
  75813         soc_block_list[169],
  75814         soc_genreg,
  75815         1,
  75816         0,
  75817         0x9a,
  75818         SOC_REG_FLAG_WO,
  75819         0,
  75820         11,
  75821         soc_BRDC_HBC_ECC_ERR_1B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  75822         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75823         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75824         -1,
  75825         -1,
  75826     },
  75827 #endif /* chips */
  75828 
  75829 #if defined(BCM_88690_A0)
  75830     { /* SOC_REG_INT_BRDC_HBC_ECC_ERR_2B_MONITOR_MEM_MASKr */
  75831         soc_block_list[169],
  75832         soc_genreg,
  75833         1,
  75834         0,
  75835         0x9c,
  75836         0,
  75837         0,
  75838         11,
  75839         soc_BRDC_HBC_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  75840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75841         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75842         -1,
  75843         -1,
  75844     },
  75845 #endif /* chips */
  75846 
  75847 #if defined(BCM_88690_B0)
  75848     { /* SOC_REG_INT_BRDC_HBC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r */
  75849         soc_block_list[169],
  75850         soc_genreg,
  75851         1,
  75852         0,
  75853         0x9c,
  75854         SOC_REG_FLAG_WO,
  75855         0,
  75856         11,
  75857         soc_BRDC_HBC_ECC_ERR_2B_MONITOR_MEM_MASK_BCM88690_B0r_fields,
  75858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75859         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  75860         -1,
  75861         -1,
  75862     },
  75863 #endif /* chips */
  75864 
  75865 #if defined(BCM_88690_A0)
  75866     { /* SOC_REG_INT_BRDC_HBC_ECC_INTERRUPT_REGISTERr */
  75867         soc_block_list[169],
  75868         soc_genreg,
  75869         1,
  75870         0,
  75871         0x7,
  75872         SOC_REG_FLAG_INTERRUPT |
  75873                           SOC_REG_FLAG_SIGNAL,
  75874         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  75875         3,
  75876         soc_BRDC_HBC_ECC_INTERRUPT_REGISTERr_fields,
  75877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75878         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75879         -1,
  75880         -1,
  75881     },
  75882 #endif /* chips */
  75883 
  75884 #if defined(BCM_88690_B0)
  75885     { /* SOC_REG_INT_BRDC_HBC_ECC_INTERRUPT_REGISTER_BCM88690_B0r */
  75886         soc_block_list[169],
  75887         soc_genreg,
  75888         1,
  75889         0,
  75890         0x7,
  75891         SOC_REG_FLAG_WO |
  75892                           SOC_REG_FLAG_INTERRUPT |
  75893                           SOC_REG_FLAG_SIGNAL,
  75894         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  75895         3,
  75896         soc_BRDC_HBC_ECC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  75897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75898         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75899         -1,
  75900         -1,
  75901     },
  75902 #endif /* chips */
  75903 
  75904 #if defined(BCM_88690_A0)
  75905     { /* SOC_REG_INT_BRDC_HBC_ECC_INTERRUPT_REGISTER_MASKr */
  75906         soc_block_list[169],
  75907         soc_genreg,
  75908         1,
  75909         0,
  75910         0x17,
  75911         0,
  75912         0,
  75913         3,
  75914         soc_BRDC_HBC_ECC_INTERRUPT_REGISTER_MASKr_fields,
  75915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75916         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75917         -1,
  75918         -1,
  75919     },
  75920 #endif /* chips */
  75921 
  75922 #if defined(BCM_88690_B0)
  75923     { /* SOC_REG_INT_BRDC_HBC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r */
  75924         soc_block_list[169],
  75925         soc_genreg,
  75926         1,
  75927         0,
  75928         0x17,
  75929         SOC_REG_FLAG_WO,
  75930         0,
  75931         3,
  75932         soc_BRDC_HBC_ECC_INTERRUPT_REGISTER_MASK_BCM88690_B0r_fields,
  75933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75934         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75935         -1,
  75936         -1,
  75937     },
  75938 #endif /* chips */
  75939 
  75940 #if defined(BCM_88690_A0)
  75941     { /* SOC_REG_INT_BRDC_HBC_ECC_INTERRUPT_REGISTER_TESTr */
  75942         soc_block_list[169],
  75943         soc_genreg,
  75944         1,
  75945         0,
  75946         0x1f,
  75947         0,
  75948         0,
  75949         1,
  75950         soc_BRDC_HBC_ECC_INTERRUPT_REGISTER_TESTr_fields,
  75951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75952         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75953         -1,
  75954         -1,
  75955     },
  75956 #endif /* chips */
  75957 
  75958 #if defined(BCM_88690_B0)
  75959     { /* SOC_REG_INT_BRDC_HBC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  75960         soc_block_list[169],
  75961         soc_genreg,
  75962         1,
  75963         0,
  75964         0x1f,
  75965         SOC_REG_FLAG_WO,
  75966         0,
  75967         1,
  75968         soc_BRDC_HBC_ECC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  75969         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75970         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  75971         -1,
  75972         -1,
  75973     },
  75974 #endif /* chips */
  75975 
  75976 #if defined(BCM_88690_A0)
  75977     { /* SOC_REG_INT_BRDC_HBC_ENABLE_DYNAMIC_MEMORY_ACCESSr */
  75978         soc_block_list[169],
  75979         soc_genreg,
  75980         1,
  75981         0,
  75982         0x84,
  75983         0,
  75984         0,
  75985         1,
  75986         soc_BRDC_HBC_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  75987         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  75988         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  75989         -1,
  75990         -1,
  75991     },
  75992 #endif /* chips */
  75993 
  75994 #if defined(BCM_88690_B0)
  75995     { /* SOC_REG_INT_BRDC_HBC_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r */
  75996         soc_block_list[169],
  75997         soc_genreg,
  75998         1,
  75999         0,
  76000         0x84,
  76001         SOC_REG_FLAG_WO,
  76002         0,
  76003         1,
  76004         soc_BRDC_HBC_ENABLE_DYNAMIC_MEMORY_ACCESS_BCM88690_B0r_fields,
  76005         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76006         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  76007         -1,
  76008         -1,
  76009     },
  76010 #endif /* chips */
  76011 
  76012 #if defined(BCM_88690_A0)
  76013     { /* SOC_REG_INT_BRDC_HBC_ERROR_INITIATION_DATAr */
  76014         soc_block_list[169],
  76015         soc_genreg,
  76016         1,
  76017         0,
  76018         0xa3,
  76019         0,
  76020         0,
  76021         1,
  76022         soc_BRDC_HBC_ERROR_INITIATION_DATAr_fields,
  76023         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76024         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  76025         -1,
  76026         -1,
  76027     },
  76028 #endif /* chips */
  76029 
  76030 #if defined(BCM_88690_A0)
  76031     { /* SOC_REG_INT_BRDC_HBC_GTIMER_CONFIGURATIONr */
  76032         soc_block_list[169],
  76033         soc_genreg,
  76034         1,
  76035         0,
  76036         0x89,
  76037         0,
  76038         0,
  76039         3,
  76040         soc_BRDC_HBC_GTIMER_CONFIGURATIONr_fields,
  76041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76042         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  76043         -1,
  76044         -1,
  76045     },
  76046 #endif /* chips */
  76047 
  76048 #if defined(BCM_88690_B0)
  76049     { /* SOC_REG_INT_BRDC_HBC_GTIMER_CONFIGURATION_BCM88690_B0r */
  76050         soc_block_list[169],
  76051         soc_genreg,
  76052         1,
  76053         0,
  76054         0x89,
  76055         SOC_REG_FLAG_WO,
  76056         0,
  76057         3,
  76058         soc_BRDC_HBC_GTIMER_CONFIGURATION_BCM88690_B0r_fields,
  76059         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76060         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  76061         -1,
  76062         -1,
  76063     },
  76064 #endif /* chips */
  76065 
  76066 #if defined(BCM_88690_A0)
  76067     { /* SOC_REG_INT_BRDC_HBC_GTIMER_CYCLEr */
  76068         soc_block_list[169],
  76069         soc_genreg,
  76070         1,
  76071         0,
  76072         0x88,
  76073         0,
  76074         0,
  76075         1,
  76076         soc_BRDC_HBC_GTIMER_CYCLEr_fields,
  76077         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  76078         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76079         -1,
  76080         -1,
  76081     },
  76082 #endif /* chips */
  76083 
  76084 #if defined(BCM_88690_B0)
  76085     { /* SOC_REG_INT_BRDC_HBC_GTIMER_CYCLE_BCM88690_B0r */
  76086         soc_block_list[169],
  76087         soc_genreg,
  76088         1,
  76089         0,
  76090         0x88,
  76091         SOC_REG_FLAG_WO,
  76092         0,
  76093         1,
  76094         soc_BRDC_HBC_GTIMER_CYCLE_BCM88690_B0r_fields,
  76095         SOC_RESET_VAL_DEC(0x3b9aca00, 0x00000000)
  76096         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76097         -1,
  76098         -1,
  76099     },
  76100 #endif /* chips */
  76101 
  76102 #if defined(BCM_88690_A0)
  76103     { /* SOC_REG_INT_BRDC_HBC_HBM_COLUMN_ACCESS_TIMINGSr */
  76104         soc_block_list[169],
  76105         soc_genreg,
  76106         1,
  76107         0,
  76108         0x161,
  76109         SOC_REG_FLAG_64_BITS,
  76110         0,
  76111         6,
  76112         soc_BRDC_HBC_HBM_COLUMN_ACCESS_TIMINGSr_fields,
  76113         SOC_RESET_VAL_DEC(0x83204084, 0x00000002)
  76114         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  76115         -1,
  76116         -1,
  76117     },
  76118 #endif /* chips */
  76119 
  76120 #if defined(BCM_88690_B0)
  76121     { /* SOC_REG_INT_BRDC_HBC_HBM_COLUMN_ACCESS_TIMINGS_BCM88690_B0r */
  76122         soc_block_list[169],
  76123         soc_genreg,
  76124         1,
  76125         0,
  76126         0x140,
  76127         SOC_REG_FLAG_64_BITS |
  76128                           SOC_REG_FLAG_WO,
  76129         0,
  76130         6,
  76131         soc_BRDC_HBC_HBM_COLUMN_ACCESS_TIMINGS_BCM88690_B0r_fields,
  76132         SOC_RESET_VAL_DEC(0x83204084, 0x00000002)
  76133         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  76134         -1,
  76135         -1,
  76136     },
  76137 #endif /* chips */
  76138 
  76139 #if defined(BCM_88690_A0)
  76140     { /* SOC_REG_INT_BRDC_HBC_HBM_COMMAND_COUNTERSr */
  76141         soc_block_list[169],
  76142         soc_genreg,
  76143         1,
  76144         0,
  76145         0x19c,
  76146         SOC_REG_FLAG_ABOVE_64_BITS |
  76147                           SOC_REG_FLAG_RO,
  76148         SOC_REG_FLAG_COUNTER_FEILDS,
  76149         7,
  76150         soc_BRDC_HBC_HBM_COMMAND_COUNTERSr_fields,
  76151         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76152         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76153         -1,
  76154         -1,
  76155     },
  76156 #endif /* chips */
  76157 
  76158 #if defined(BCM_88690_B0)
  76159     { /* SOC_REG_INT_BRDC_HBC_HBM_COMMAND_COUNTERS_BCM88690_B0r */
  76160         soc_block_list[169],
  76161         soc_genreg,
  76162         1,
  76163         0,
  76164         0x17b,
  76165         SOC_REG_FLAG_ABOVE_64_BITS |
  76166                           SOC_REG_FLAG_RO |
  76167                           SOC_REG_FLAG_WO,
  76168         SOC_REG_FLAG_COUNTER_FEILDS,
  76169         7,
  76170         soc_BRDC_HBC_HBM_COMMAND_COUNTERS_BCM88690_B0r_fields,
  76171         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76172         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76173         -1,
  76174         -1,
  76175     },
  76176 #endif /* chips */
  76177 
  76178 #if defined(BCM_88690_A0)
  76179     { /* SOC_REG_INT_BRDC_HBC_HBM_CONFIGr */
  76180         soc_block_list[169],
  76181         soc_genreg,
  76182         1,
  76183         0,
  76184         0x10a,
  76185         0,
  76186         0,
  76187         13,
  76188         soc_BRDC_HBC_HBM_CONFIGr_fields,
  76189         SOC_RESET_VAL_DEC(0x001301d4, 0x00000000)
  76190         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  76191         -1,
  76192         -1,
  76193     },
  76194 #endif /* chips */
  76195 
  76196 #if defined(BCM_88690_B0)
  76197     { /* SOC_REG_INT_BRDC_HBC_HBM_CONFIG_BCM88690_B0r */
  76198         soc_block_list[169],
  76199         soc_genreg,
  76200         1,
  76201         0,
  76202         0x109,
  76203         SOC_REG_FLAG_WO,
  76204         0,
  76205         13,
  76206         soc_BRDC_HBC_HBM_CONFIG_BCM88690_B0r_fields,
  76207         SOC_RESET_VAL_DEC(0x001301d4, 0x00000000)
  76208         SOC_RESET_MASK_DEC(0x001fffff, 0x00000000)
  76209         -1,
  76210         -1,
  76211     },
  76212 #endif /* chips */
  76213 
  76214 #if defined(BCM_88690_A0)
  76215     { /* SOC_REG_INT_BRDC_HBC_HBM_CPU_CONTROLr */
  76216         soc_block_list[169],
  76217         soc_genreg,
  76218         1,
  76219         0,
  76220         0x180,
  76221         SOC_REG_FLAG_64_BITS,
  76222         0,
  76223         21,
  76224         soc_BRDC_HBC_HBM_CPU_CONTROLr_fields,
  76225         SOC_RESET_VAL_DEC(0x0000000c, 0x0ff00c00)
  76226         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  76227         -1,
  76228         -1,
  76229     },
  76230 #endif /* chips */
  76231 
  76232 #if defined(BCM_88690_B0)
  76233     { /* SOC_REG_INT_BRDC_HBC_HBM_CPU_CONTROL_BCM88690_B0r */
  76234         soc_block_list[169],
  76235         soc_genreg,
  76236         1,
  76237         0,
  76238         0x15f,
  76239         SOC_REG_FLAG_64_BITS |
  76240                           SOC_REG_FLAG_WO,
  76241         0,
  76242         21,
  76243         soc_BRDC_HBC_HBM_CPU_CONTROL_BCM88690_B0r_fields,
  76244         SOC_RESET_VAL_DEC(0x0000000c, 0x0ff00c00)
  76245         SOC_RESET_MASK_DEC(0xffffffff, 0x7fffffff)
  76246         -1,
  76247         -1,
  76248     },
  76249 #endif /* chips */
  76250 
  76251 #if defined(BCM_88690_A0)
  76252     { /* SOC_REG_INT_BRDC_HBC_HBM_ECC_ERR_INFOr */
  76253         soc_block_list[169],
  76254         soc_genreg,
  76255         1,
  76256         0,
  76257         0x192,
  76258         SOC_REG_FLAG_ABOVE_64_BITS |
  76259                           SOC_REG_FLAG_RO,
  76260         0,
  76261         7,
  76262         soc_BRDC_HBC_HBM_ECC_ERR_INFOr_fields,
  76263         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76264         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76265         -1,
  76266         -1,
  76267     },
  76268 #endif /* chips */
  76269 
  76270 #if defined(BCM_88690_B0)
  76271     { /* SOC_REG_INT_BRDC_HBC_HBM_ECC_ERR_INFO_BCM88690_B0r */
  76272         soc_block_list[169],
  76273         soc_genreg,
  76274         1,
  76275         0,
  76276         0x171,
  76277         SOC_REG_FLAG_ABOVE_64_BITS |
  76278                           SOC_REG_FLAG_RO |
  76279                           SOC_REG_FLAG_WO,
  76280         0,
  76281         7,
  76282         soc_BRDC_HBC_HBM_ECC_ERR_INFO_BCM88690_B0r_fields,
  76283         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76284         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76285         -1,
  76286         -1,
  76287     },
  76288 #endif /* chips */
  76289 
  76290 #if defined(BCM_88690_A0)
  76291     { /* SOC_REG_INT_BRDC_HBC_HBM_ERR_COUNTERSr */
  76292         soc_block_list[169],
  76293         soc_genreg,
  76294         1,
  76295         0,
  76296         0x182,
  76297         SOC_REG_FLAG_ABOVE_64_BITS |
  76298                           SOC_REG_FLAG_RO,
  76299         SOC_REG_FLAG_COUNTER_FEILDS,
  76300         13,
  76301         soc_BRDC_HBC_HBM_ERR_COUNTERSr_fields,
  76302         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76303         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76304         -1,
  76305         -1,
  76306     },
  76307 #endif /* chips */
  76308 
  76309 #if defined(BCM_88690_B0)
  76310     { /* SOC_REG_INT_BRDC_HBC_HBM_ERR_COUNTERS_BCM88690_B0r */
  76311         soc_block_list[169],
  76312         soc_genreg,
  76313         1,
  76314         0,
  76315         0x161,
  76316         SOC_REG_FLAG_ABOVE_64_BITS |
  76317                           SOC_REG_FLAG_RO |
  76318                           SOC_REG_FLAG_WO,
  76319         SOC_REG_FLAG_COUNTER_FEILDS,
  76320         13,
  76321         soc_BRDC_HBC_HBM_ERR_COUNTERS_BCM88690_B0r_fields,
  76322         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76323         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76324         -1,
  76325         -1,
  76326     },
  76327 #endif /* chips */
  76328 
  76329 #if defined(BCM_88690_A0)
  76330     { /* SOC_REG_INT_BRDC_HBC_HBM_GENERAL_TIMINGSr */
  76331         soc_block_list[169],
  76332         soc_genreg,
  76333         1,
  76334         0,
  76335         0x164,
  76336         0,
  76337         0,
  76338         2,
  76339         soc_BRDC_HBC_HBM_GENERAL_TIMINGSr_fields,
  76340         SOC_RESET_VAL_DEC(0x000003c8, 0x00000000)
  76341         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  76342         -1,
  76343         -1,
  76344     },
  76345 #endif /* chips */
  76346 
  76347 #if defined(BCM_88690_B0)
  76348     { /* SOC_REG_INT_BRDC_HBC_HBM_GENERAL_TIMINGS_BCM88690_B0r */
  76349         soc_block_list[169],
  76350         soc_genreg,
  76351         1,
  76352         0,
  76353         0x143,
  76354         SOC_REG_FLAG_WO,
  76355         0,
  76356         2,
  76357         soc_BRDC_HBC_HBM_GENERAL_TIMINGS_BCM88690_B0r_fields,
  76358         SOC_RESET_VAL_DEC(0x000003c8, 0x00000000)
  76359         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  76360         -1,
  76361         -1,
  76362     },
  76363 #endif /* chips */
  76364 
  76365 #if defined(BCM_88690_A0)
  76366     { /* SOC_REG_INT_BRDC_HBC_HBM_MODE_REGISTERSr */
  76367         soc_block_list[169],
  76368         soc_genreg,
  76369         1,
  76370         0,
  76371         0x10b,
  76372         SOC_REG_FLAG_ABOVE_64_BITS,
  76373         0,
  76374         16,
  76375         soc_BRDC_HBC_HBM_MODE_REGISTERSr_fields,
  76376         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76377         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76378         -1,
  76379         -1,
  76380     },
  76381 #endif /* chips */
  76382 
  76383 #if defined(BCM_88690_B0)
  76384     { /* SOC_REG_INT_BRDC_HBC_HBM_MODE_REGISTERS_BCM88690_B0r */
  76385         soc_block_list[169],
  76386         soc_genreg,
  76387         1,
  76388         0,
  76389         0x10a,
  76390         SOC_REG_FLAG_ABOVE_64_BITS |
  76391                           SOC_REG_FLAG_WO,
  76392         0,
  76393         16,
  76394         soc_BRDC_HBC_HBM_MODE_REGISTERS_BCM88690_B0r_fields,
  76395         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76396         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76397         -1,
  76398         -1,
  76399     },
  76400 #endif /* chips */
  76401 
  76402 #if defined(BCM_88690_A0)
  76403     { /* SOC_REG_INT_BRDC_HBC_HBM_MODE_REGISTER_MANAGER_CONFIGr */
  76404         soc_block_list[169],
  76405         soc_genreg,
  76406         1,
  76407         0,
  76408         0x10f,
  76409         0,
  76410         0,
  76411         2,
  76412         soc_BRDC_HBC_HBM_MODE_REGISTER_MANAGER_CONFIGr_fields,
  76413         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  76414         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  76415         -1,
  76416         -1,
  76417     },
  76418 #endif /* chips */
  76419 
  76420 #if defined(BCM_88690_B0)
  76421     { /* SOC_REG_INT_BRDC_HBC_HBM_MODE_REGISTER_MANAGER_CONFIG_BCM88690_B0r */
  76422         soc_block_list[169],
  76423         soc_genreg,
  76424         1,
  76425         0,
  76426         0x10e,
  76427         SOC_REG_FLAG_WO,
  76428         0,
  76429         2,
  76430         soc_BRDC_HBC_HBM_MODE_REGISTER_MANAGER_CONFIG_BCM88690_B0r_fields,
  76431         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  76432         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  76433         -1,
  76434         -1,
  76435     },
  76436 #endif /* chips */
  76437 
  76438 #if defined(BCM_88690_A0)
  76439     { /* SOC_REG_INT_BRDC_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERRORr */
  76440         soc_block_list[169],
  76441         soc_genreg,
  76442         1,
  76443         0,
  76444         0x235,
  76445         SOC_REG_FLAG_RO,
  76446         SOC_REG_FLAG_INIT_ON_READ,
  76447         1,
  76448         soc_BRDC_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERRORr_fields,
  76449         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76450         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  76451         -1,
  76452         -1,
  76453     },
  76454 #endif /* chips */
  76455 
  76456 #if defined(BCM_88690_B0)
  76457     { /* SOC_REG_INT_BRDC_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERROR_BCM88690_B0r */
  76458         soc_block_list[169],
  76459         soc_genreg,
  76460         1,
  76461         0,
  76462         0x210,
  76463         SOC_REG_FLAG_RO |
  76464                           SOC_REG_FLAG_WO,
  76465         SOC_REG_FLAG_INIT_ON_READ,
  76466         1,
  76467         soc_BRDC_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERROR_BCM88690_B0r_fields,
  76468         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76469         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  76470         -1,
  76471         -1,
  76472     },
  76473 #endif /* chips */
  76474 
  76475 #if defined(BCM_88690_A0)
  76476     { /* SOC_REG_INT_BRDC_HBC_HBM_REFRESH_INTERVALSr */
  76477         soc_block_list[169],
  76478         soc_genreg,
  76479         8,
  76480         0,
  76481         0x165,
  76482         SOC_REG_FLAG_ARRAY |
  76483                           SOC_REG_FLAG_REG_ARRAY,
  76484         0,
  76485         2,
  76486         soc_BRDC_HBC_HBM_REFRESH_INTERVALSr_fields,
  76487         SOC_RESET_VAL_DEC(0x003d0f3c, 0x00000000)
  76488         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  76489         -1,
  76490         -1,
  76491     },
  76492 #endif /* chips */
  76493 
  76494 #if defined(BCM_88690_B0)
  76495     { /* SOC_REG_INT_BRDC_HBC_HBM_REFRESH_INTERVALS_BCM88690_B0r */
  76496         soc_block_list[169],
  76497         soc_genreg,
  76498         8,
  76499         0,
  76500         0x144,
  76501         SOC_REG_FLAG_ARRAY |
  76502                           SOC_REG_FLAG_WO |
  76503                           SOC_REG_FLAG_REG_ARRAY,
  76504         0,
  76505         2,
  76506         soc_BRDC_HBC_HBM_REFRESH_INTERVALS_BCM88690_B0r_fields,
  76507         SOC_RESET_VAL_DEC(0x003d0f3c, 0x00000000)
  76508         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  76509         -1,
  76510         -1,
  76511     },
  76512 #endif /* chips */
  76513 
  76514 #if defined(BCM_88690_A0)
  76515     { /* SOC_REG_INT_BRDC_HBC_HBM_REFRESH_TIMINGSr */
  76516         soc_block_list[169],
  76517         soc_genreg,
  76518         1,
  76519         0,
  76520         0x163,
  76521         0,
  76522         0,
  76523         3,
  76524         soc_BRDC_HBC_HBM_REFRESH_TIMINGSr_fields,
  76525         SOC_RESET_VAL_DEC(0x00a28104, 0x00000000)
  76526         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  76527         -1,
  76528         -1,
  76529     },
  76530 #endif /* chips */
  76531 
  76532 #if defined(BCM_88690_B0)
  76533     { /* SOC_REG_INT_BRDC_HBC_HBM_REFRESH_TIMINGS_BCM88690_B0r */
  76534         soc_block_list[169],
  76535         soc_genreg,
  76536         1,
  76537         0,
  76538         0x142,
  76539         SOC_REG_FLAG_WO,
  76540         0,
  76541         3,
  76542         soc_BRDC_HBC_HBM_REFRESH_TIMINGS_BCM88690_B0r_fields,
  76543         SOC_RESET_VAL_DEC(0x00a28104, 0x00000000)
  76544         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  76545         -1,
  76546         -1,
  76547     },
  76548 #endif /* chips */
  76549 
  76550 #if defined(BCM_88690_A0)
  76551     { /* SOC_REG_INT_BRDC_HBC_HBM_ROW_ACCESS_TIMINGSr */
  76552         soc_block_list[169],
  76553         soc_genreg,
  76554         1,
  76555         0,
  76556         0x15e,
  76557         SOC_REG_FLAG_ABOVE_64_BITS,
  76558         0,
  76559         11,
  76560         soc_BRDC_HBC_HBM_ROW_ACCESS_TIMINGSr_fields,
  76561         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76562         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76563         -1,
  76564         -1,
  76565     },
  76566 #endif /* chips */
  76567 
  76568 #if defined(BCM_88690_B0)
  76569     { /* SOC_REG_INT_BRDC_HBC_HBM_ROW_ACCESS_TIMINGS_BCM88690_B0r */
  76570         soc_block_list[169],
  76571         soc_genreg,
  76572         1,
  76573         0,
  76574         0x13d,
  76575         SOC_REG_FLAG_ABOVE_64_BITS |
  76576                           SOC_REG_FLAG_WO,
  76577         0,
  76578         11,
  76579         soc_BRDC_HBC_HBM_ROW_ACCESS_TIMINGS_BCM88690_B0r_fields,
  76580         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76581         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76582         -1,
  76583         -1,
  76584     },
  76585 #endif /* chips */
  76586 
  76587 #if defined(BCM_88690_A0)
  76588     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_COMMANDr */
  76589         soc_block_list[169],
  76590         soc_genreg,
  76591         1,
  76592         0,
  76593         0x80,
  76594         0,
  76595         0,
  76596         5,
  76597         soc_BRDC_HBC_INDIRECT_COMMANDr_fields,
  76598         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  76599         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76600         -1,
  76601         -1,
  76602     },
  76603 #endif /* chips */
  76604 
  76605 #if defined(BCM_88690_A0)
  76606     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_COMMAND_ADDRESSr */
  76607         soc_block_list[169],
  76608         soc_genreg,
  76609         1,
  76610         0,
  76611         0x81,
  76612         0,
  76613         0,
  76614         2,
  76615         soc_BRDC_HBC_INDIRECT_COMMAND_ADDRESSr_fields,
  76616         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76617         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76618         -1,
  76619         -1,
  76620     },
  76621 #endif /* chips */
  76622 
  76623 #if defined(BCM_88690_B0)
  76624     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r */
  76625         soc_block_list[169],
  76626         soc_genreg,
  76627         1,
  76628         0,
  76629         0x81,
  76630         SOC_REG_FLAG_WO,
  76631         0,
  76632         2,
  76633         soc_BRDC_HBC_INDIRECT_COMMAND_ADDRESS_BCM88690_B0r_fields,
  76634         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76635         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76636         -1,
  76637         -1,
  76638     },
  76639 #endif /* chips */
  76640 
  76641 #if defined(BCM_88690_B0)
  76642     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_COMMAND_BCM88690_B0r */
  76643         soc_block_list[169],
  76644         soc_genreg,
  76645         1,
  76646         0,
  76647         0x80,
  76648         SOC_REG_FLAG_WO,
  76649         0,
  76650         5,
  76651         soc_BRDC_HBC_INDIRECT_COMMAND_BCM88690_B0r_fields,
  76652         SOC_RESET_VAL_DEC(0x0e000000, 0x00000000)
  76653         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  76654         -1,
  76655         -1,
  76656     },
  76657 #endif /* chips */
  76658 
  76659 #if defined(BCM_88690_A0)
  76660     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_COMMAND_RD_DATAr */
  76661         soc_block_list[169],
  76662         soc_genreg,
  76663         1,
  76664         0,
  76665         0x60,
  76666         SOC_REG_FLAG_ABOVE_64_BITS |
  76667                           SOC_REG_FLAG_RO |
  76668                           SOC_REG_FLAG_SIGNAL,
  76669         0,
  76670         1,
  76671         soc_BRDC_HBC_INDIRECT_COMMAND_RD_DATAr_fields,
  76672         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76673         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76674         -1,
  76675         -1,
  76676     },
  76677 #endif /* chips */
  76678 
  76679 #if defined(BCM_88690_A0)
  76680     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_COMMAND_WR_DATAr */
  76681         soc_block_list[169],
  76682         soc_genreg,
  76683         1,
  76684         0,
  76685         0x20,
  76686         SOC_REG_FLAG_ABOVE_64_BITS,
  76687         0,
  76688         1,
  76689         soc_BRDC_HBC_INDIRECT_COMMAND_WR_DATAr_fields,
  76690         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76691         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76692         -1,
  76693         -1,
  76694     },
  76695 #endif /* chips */
  76696 
  76697 #if defined(BCM_88690_B0)
  76698     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r */
  76699         soc_block_list[169],
  76700         soc_genreg,
  76701         1,
  76702         0,
  76703         0x20,
  76704         SOC_REG_FLAG_ABOVE_64_BITS |
  76705                           SOC_REG_FLAG_WO,
  76706         0,
  76707         1,
  76708         soc_BRDC_HBC_INDIRECT_COMMAND_WR_DATA_BCM88690_B0r_fields,
  76709         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76710         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76711         -1,
  76712         -1,
  76713     },
  76714 #endif /* chips */
  76715 
  76716 #if defined(BCM_88690_A0)
  76717     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_FORCE_BUBBLEr */
  76718         soc_block_list[169],
  76719         soc_genreg,
  76720         1,
  76721         0,
  76722         0x83,
  76723         0,
  76724         0,
  76725         4,
  76726         soc_BRDC_HBC_INDIRECT_FORCE_BUBBLEr_fields,
  76727         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76728         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  76729         -1,
  76730         -1,
  76731     },
  76732 #endif /* chips */
  76733 
  76734 #if defined(BCM_88690_B0)
  76735     { /* SOC_REG_INT_BRDC_HBC_INDIRECT_FORCE_BUBBLE_BCM88690_B0r */
  76736         soc_block_list[169],
  76737         soc_genreg,
  76738         1,
  76739         0,
  76740         0x83,
  76741         SOC_REG_FLAG_WO,
  76742         0,
  76743         4,
  76744         soc_BRDC_HBC_INDIRECT_FORCE_BUBBLE_BCM88690_B0r_fields,
  76745         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76746         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  76747         -1,
  76748         -1,
  76749     },
  76750 #endif /* chips */
  76751 
  76752 #if defined(BCM_88690_A0)
  76753     { /* SOC_REG_INT_BRDC_HBC_INTERRUPT_MASK_REGISTERr */
  76754         soc_block_list[169],
  76755         soc_genreg,
  76756         1,
  76757         0,
  76758         0x10,
  76759         0,
  76760         0,
  76761         6,
  76762         soc_BRDC_HBC_INTERRUPT_MASK_REGISTERr_fields,
  76763         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76764         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  76765         -1,
  76766         -1,
  76767     },
  76768 #endif /* chips */
  76769 
  76770 #if defined(BCM_88690_B0)
  76771     { /* SOC_REG_INT_BRDC_HBC_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  76772         soc_block_list[169],
  76773         soc_genreg,
  76774         1,
  76775         0,
  76776         0x10,
  76777         SOC_REG_FLAG_WO,
  76778         0,
  76779         6,
  76780         soc_BRDC_HBC_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  76781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76782         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  76783         -1,
  76784         -1,
  76785     },
  76786 #endif /* chips */
  76787 
  76788 #if defined(BCM_88690_A0)
  76789     { /* SOC_REG_INT_BRDC_HBC_INTERRUPT_REGISTERr */
  76790         soc_block_list[169],
  76791         soc_genreg,
  76792         1,
  76793         0,
  76794         0,
  76795         SOC_REG_FLAG_INTERRUPT |
  76796                           SOC_REG_FLAG_SIGNAL,
  76797         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  76798         6,
  76799         soc_BRDC_HBC_INTERRUPT_REGISTERr_fields,
  76800         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76801         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  76802         -1,
  76803         -1,
  76804     },
  76805 #endif /* chips */
  76806 
  76807 #if defined(BCM_88690_B0)
  76808     { /* SOC_REG_INT_BRDC_HBC_INTERRUPT_REGISTER_BCM88690_B0r */
  76809         soc_block_list[169],
  76810         soc_genreg,
  76811         1,
  76812         0,
  76813         0,
  76814         SOC_REG_FLAG_WO |
  76815                           SOC_REG_FLAG_INTERRUPT |
  76816                           SOC_REG_FLAG_SIGNAL,
  76817         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  76818         6,
  76819         soc_BRDC_HBC_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  76820         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76821         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  76822         -1,
  76823         -1,
  76824     },
  76825 #endif /* chips */
  76826 
  76827 #if defined(BCM_88690_A0)
  76828     { /* SOC_REG_INT_BRDC_HBC_INTERRUPT_REGISTER_TESTr */
  76829         soc_block_list[169],
  76830         soc_genreg,
  76831         1,
  76832         0,
  76833         0x18,
  76834         0,
  76835         0,
  76836         1,
  76837         soc_BRDC_HBC_INTERRUPT_REGISTER_TESTr_fields,
  76838         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76839         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  76840         -1,
  76841         -1,
  76842     },
  76843 #endif /* chips */
  76844 
  76845 #if defined(BCM_88690_B0)
  76846     { /* SOC_REG_INT_BRDC_HBC_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  76847         soc_block_list[169],
  76848         soc_genreg,
  76849         1,
  76850         0,
  76851         0x18,
  76852         SOC_REG_FLAG_WO,
  76853         0,
  76854         1,
  76855         soc_BRDC_HBC_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  76856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76857         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  76858         -1,
  76859         -1,
  76860     },
  76861 #endif /* chips */
  76862 
  76863 #if defined(BCM_88690_A0)
  76864     { /* SOC_REG_INT_BRDC_HBC_LAST_RETURNED_DATAr */
  76865         soc_block_list[169],
  76866         soc_genreg,
  76867         4,
  76868         0,
  76869         0x1a5,
  76870         SOC_REG_FLAG_ABOVE_64_BITS |
  76871                           SOC_REG_FLAG_ARRAY |
  76872                           SOC_REG_FLAG_RO |
  76873                           SOC_REG_FLAG_REG_ARRAY,
  76874         0,
  76875         4,
  76876         soc_BRDC_HBC_LAST_RETURNED_DATAr_fields,
  76877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76878         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76879         -1,
  76880         -1,
  76881     },
  76882 #endif /* chips */
  76883 
  76884 #if defined(BCM_88690_B0)
  76885     { /* SOC_REG_INT_BRDC_HBC_LAST_RETURNED_DATA_BCM88690_B0r */
  76886         soc_block_list[169],
  76887         soc_genreg,
  76888         4,
  76889         0,
  76890         0x184,
  76891         SOC_REG_FLAG_ABOVE_64_BITS |
  76892                           SOC_REG_FLAG_ARRAY |
  76893                           SOC_REG_FLAG_RO |
  76894                           SOC_REG_FLAG_WO |
  76895                           SOC_REG_FLAG_REG_ARRAY,
  76896         0,
  76897         4,
  76898         soc_BRDC_HBC_LAST_RETURNED_DATA_BCM88690_B0r_fields,
  76899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76900         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  76901         -1,
  76902         -1,
  76903     },
  76904 #endif /* chips */
  76905 
  76906 #if defined(BCM_88690_A0)
  76907     { /* SOC_REG_INT_BRDC_HBC_PARITY_ERR_CNTr */
  76908         soc_block_list[169],
  76909         soc_genreg,
  76910         1,
  76911         0,
  76912         0x98,
  76913         SOC_REG_FLAG_64_BITS |
  76914                           SOC_REG_FLAG_RO,
  76915         SOC_REG_FLAG_COUNTER_FEILDS |
  76916                           SOC_REG_FLAG_INIT_ON_READ,
  76917         4,
  76918         soc_BRDC_HBC_PARITY_ERR_CNTr_fields,
  76919         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76920         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  76921         -1,
  76922         -1,
  76923     },
  76924 #endif /* chips */
  76925 
  76926 #if defined(BCM_88690_B0)
  76927     { /* SOC_REG_INT_BRDC_HBC_PARITY_ERR_CNT_BCM88690_B0r */
  76928         soc_block_list[169],
  76929         soc_genreg,
  76930         1,
  76931         0,
  76932         0x98,
  76933         SOC_REG_FLAG_64_BITS |
  76934                           SOC_REG_FLAG_RO |
  76935                           SOC_REG_FLAG_WO,
  76936         SOC_REG_FLAG_COUNTER_FEILDS |
  76937                           SOC_REG_FLAG_INIT_ON_READ,
  76938         4,
  76939         soc_BRDC_HBC_PARITY_ERR_CNT_BCM88690_B0r_fields,
  76940         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76941         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  76942         -1,
  76943         -1,
  76944     },
  76945 #endif /* chips */
  76946 
  76947 #if defined(BCM_88690_A0)
  76948     { /* SOC_REG_INT_BRDC_HBC_PAR_ERR_MEM_MASKr */
  76949         soc_block_list[169],
  76950         soc_genreg,
  76951         1,
  76952         0,
  76953         0xa0,
  76954         0,
  76955         0,
  76956         22,
  76957         soc_BRDC_HBC_PAR_ERR_MEM_MASKr_fields,
  76958         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76959         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  76960         -1,
  76961         -1,
  76962     },
  76963 #endif /* chips */
  76964 
  76965 #if defined(BCM_88690_B0)
  76966     { /* SOC_REG_INT_BRDC_HBC_PAR_ERR_MEM_MASK_BCM88690_B0r */
  76967         soc_block_list[169],
  76968         soc_genreg,
  76969         1,
  76970         0,
  76971         0xa0,
  76972         SOC_REG_FLAG_WO,
  76973         0,
  76974         20,
  76975         soc_BRDC_HBC_PAR_ERR_MEM_MASK_BCM88690_B0r_fields,
  76976         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  76977         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  76978         -1,
  76979         -1,
  76980     },
  76981 #endif /* chips */
  76982 
  76983 #if defined(BCM_88690_A0)
  76984     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_BANK_REMAPPINGr */
  76985         soc_block_list[169],
  76986         soc_genreg,
  76987         1,
  76988         0,
  76989         0x17e,
  76990         0,
  76991         0,
  76992         5,
  76993         soc_BRDC_HBC_PIPELINES_BANK_REMAPPINGr_fields,
  76994         SOC_RESET_VAL_DEC(0x00004688, 0x00000000)
  76995         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  76996         -1,
  76997         -1,
  76998     },
  76999 #endif /* chips */
  77000 
  77001 #if defined(BCM_88690_B0)
  77002     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_BANK_REMAPPING_BCM88690_B0r */
  77003         soc_block_list[169],
  77004         soc_genreg,
  77005         1,
  77006         0,
  77007         0x15d,
  77008         SOC_REG_FLAG_WO,
  77009         0,
  77010         5,
  77011         soc_BRDC_HBC_PIPELINES_BANK_REMAPPING_BCM88690_B0r_fields,
  77012         SOC_RESET_VAL_DEC(0x00004688, 0x00000000)
  77013         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  77014         -1,
  77015         -1,
  77016     },
  77017 #endif /* chips */
  77018 
  77019 #if defined(BCM_88690_A0)
  77020     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_COMMAND_PIN_MUXr */
  77021         soc_block_list[169],
  77022         soc_genreg,
  77023         1,
  77024         0,
  77025         0x17c,
  77026         SOC_REG_FLAG_64_BITS,
  77027         0,
  77028         14,
  77029         soc_BRDC_HBC_PIPELINES_COMMAND_PIN_MUXr_fields,
  77030         SOC_RESET_VAL_DEC(0x76543210, 0x00dcba98)
  77031         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  77032         -1,
  77033         -1,
  77034     },
  77035 #endif /* chips */
  77036 
  77037 #if defined(BCM_88690_B0)
  77038     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_COMMAND_PIN_MUX_BCM88690_B0r */
  77039         soc_block_list[169],
  77040         soc_genreg,
  77041         1,
  77042         0,
  77043         0x15b,
  77044         SOC_REG_FLAG_64_BITS |
  77045                           SOC_REG_FLAG_WO,
  77046         0,
  77047         14,
  77048         soc_BRDC_HBC_PIPELINES_COMMAND_PIN_MUX_BCM88690_B0r_fields,
  77049         SOC_RESET_VAL_DEC(0x76543210, 0x00dcba98)
  77050         SOC_RESET_MASK_DEC(0xffffffff, 0x00ffffff)
  77051         -1,
  77052         -1,
  77053     },
  77054 #endif /* chips */
  77055 
  77056 #if defined(BCM_88690_A0)
  77057     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_CONFIGr */
  77058         soc_block_list[169],
  77059         soc_genreg,
  77060         1,
  77061         0,
  77062         0x17b,
  77063         0,
  77064         0,
  77065         12,
  77066         soc_BRDC_HBC_PIPELINES_CONFIGr_fields,
  77067         SOC_RESET_VAL_DEC(0x000508cc, 0x00000000)
  77068         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  77069         -1,
  77070         -1,
  77071     },
  77072 #endif /* chips */
  77073 
  77074 #if defined(BCM_88690_B0)
  77075     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_CONFIG_BCM88690_B0r */
  77076         soc_block_list[169],
  77077         soc_genreg,
  77078         1,
  77079         0,
  77080         0x15a,
  77081         SOC_REG_FLAG_WO,
  77082         0,
  77083         12,
  77084         soc_BRDC_HBC_PIPELINES_CONFIG_BCM88690_B0r_fields,
  77085         SOC_RESET_VAL_DEC(0x000508cc, 0x00000000)
  77086         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  77087         -1,
  77088         -1,
  77089     },
  77090 #endif /* chips */
  77091 
  77092 #if defined(BCM_88690_A0)
  77093     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_DEBUGr */
  77094         soc_block_list[169],
  77095         soc_genreg,
  77096         1,
  77097         0,
  77098         0x1b9,
  77099         SOC_REG_FLAG_RO,
  77100         SOC_REG_FLAG_INIT_ON_READ,
  77101         8,
  77102         soc_BRDC_HBC_PIPELINES_DEBUGr_fields,
  77103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77104         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  77105         -1,
  77106         -1,
  77107     },
  77108 #endif /* chips */
  77109 
  77110 #if defined(BCM_88690_B0)
  77111     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_DEBUG_BCM88690_B0r */
  77112         soc_block_list[169],
  77113         soc_genreg,
  77114         1,
  77115         0,
  77116         0x198,
  77117         SOC_REG_FLAG_RO |
  77118                           SOC_REG_FLAG_WO,
  77119         SOC_REG_FLAG_INIT_ON_READ,
  77120         8,
  77121         soc_BRDC_HBC_PIPELINES_DEBUG_BCM88690_B0r_fields,
  77122         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77123         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  77124         -1,
  77125         -1,
  77126     },
  77127 #endif /* chips */
  77128 
  77129 #if defined(BCM_88690_A0)
  77130     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_INTERRUPT_MASK_REGISTERr */
  77131         soc_block_list[169],
  77132         soc_genreg,
  77133         1,
  77134         0,
  77135         0x108,
  77136         0,
  77137         0,
  77138         14,
  77139         soc_BRDC_HBC_PIPELINES_INTERRUPT_MASK_REGISTERr_fields,
  77140         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77141         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  77142         -1,
  77143         -1,
  77144     },
  77145 #endif /* chips */
  77146 
  77147 #if defined(BCM_88690_B0)
  77148     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  77149         soc_block_list[169],
  77150         soc_genreg,
  77151         1,
  77152         0,
  77153         0x107,
  77154         SOC_REG_FLAG_WO,
  77155         0,
  77156         14,
  77157         soc_BRDC_HBC_PIPELINES_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  77158         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77159         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  77160         -1,
  77161         -1,
  77162     },
  77163 #endif /* chips */
  77164 
  77165 #if defined(BCM_88690_A0)
  77166     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_INTERRUPT_REGISTERr */
  77167         soc_block_list[169],
  77168         soc_genreg,
  77169         1,
  77170         0,
  77171         0x107,
  77172         SOC_REG_FLAG_INTERRUPT |
  77173                           SOC_REG_FLAG_SIGNAL,
  77174         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  77175         14,
  77176         soc_BRDC_HBC_PIPELINES_INTERRUPT_REGISTERr_fields,
  77177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77178         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  77179         -1,
  77180         -1,
  77181     },
  77182 #endif /* chips */
  77183 
  77184 #if defined(BCM_88690_B0)
  77185     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_INTERRUPT_REGISTER_BCM88690_B0r */
  77186         soc_block_list[169],
  77187         soc_genreg,
  77188         1,
  77189         0,
  77190         0x106,
  77191         SOC_REG_FLAG_WO |
  77192                           SOC_REG_FLAG_INTERRUPT |
  77193                           SOC_REG_FLAG_SIGNAL,
  77194         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  77195         14,
  77196         soc_BRDC_HBC_PIPELINES_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  77197         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77198         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  77199         -1,
  77200         -1,
  77201     },
  77202 #endif /* chips */
  77203 
  77204 #if defined(BCM_88690_A0)
  77205     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_INTERRUPT_REGISTER_TESTr */
  77206         soc_block_list[169],
  77207         soc_genreg,
  77208         1,
  77209         0,
  77210         0x109,
  77211         0,
  77212         0,
  77213         1,
  77214         soc_BRDC_HBC_PIPELINES_INTERRUPT_REGISTER_TESTr_fields,
  77215         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77216         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  77217         -1,
  77218         -1,
  77219     },
  77220 #endif /* chips */
  77221 
  77222 #if defined(BCM_88690_B0)
  77223     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  77224         soc_block_list[169],
  77225         soc_genreg,
  77226         1,
  77227         0,
  77228         0x108,
  77229         SOC_REG_FLAG_WO,
  77230         0,
  77231         1,
  77232         soc_BRDC_HBC_PIPELINES_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  77233         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77234         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  77235         -1,
  77236         -1,
  77237     },
  77238 #endif /* chips */
  77239 
  77240 #if defined(BCM_88690_A0)
  77241     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_PHY_RCMDr */
  77242         soc_block_list[169],
  77243         soc_genreg,
  77244         1,
  77245         0,
  77246         0x17f,
  77247         0,
  77248         0,
  77249         4,
  77250         soc_BRDC_HBC_PIPELINES_PHY_RCMDr_fields,
  77251         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
  77252         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  77253         -1,
  77254         -1,
  77255     },
  77256 #endif /* chips */
  77257 
  77258 #if defined(BCM_88690_B0)
  77259     { /* SOC_REG_INT_BRDC_HBC_PIPELINES_PHY_RCMD_BCM88690_B0r */
  77260         soc_block_list[169],
  77261         soc_genreg,
  77262         1,
  77263         0,
  77264         0x15e,
  77265         SOC_REG_FLAG_WO,
  77266         0,
  77267         4,
  77268         soc_BRDC_HBC_PIPELINES_PHY_RCMD_BCM88690_B0r_fields,
  77269         SOC_RESET_VAL_DEC(0x000000e4, 0x00000000)
  77270         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  77271         -1,
  77272         -1,
  77273     },
  77274 #endif /* chips */
  77275 
  77276 #if defined(BCM_88690_A0)
  77277     { /* SOC_REG_INT_BRDC_HBC_RDR_DS_TRANS_CNTr */
  77278         soc_block_list[169],
  77279         soc_genreg,
  77280         2,
  77281         0,
  77282         0x15b,
  77283         SOC_REG_FLAG_ARRAY |
  77284                           SOC_REG_FLAG_RO |
  77285                           SOC_REG_FLAG_REG_ARRAY,
  77286         SOC_REG_FLAG_COUNTER_FEILDS,
  77287         1,
  77288         soc_BRDC_HBC_RDR_DS_TRANS_CNTr_fields,
  77289         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77290         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77291         -1,
  77292         -1,
  77293     },
  77294 #endif /* chips */
  77295 
  77296 #if defined(BCM_88690_B0)
  77297     { /* SOC_REG_INT_BRDC_HBC_RDR_DS_TRANS_CNT_BCM88690_B0r */
  77298         soc_block_list[169],
  77299         soc_genreg,
  77300         2,
  77301         0,
  77302         0x13a,
  77303         SOC_REG_FLAG_ARRAY |
  77304                           SOC_REG_FLAG_RO |
  77305                           SOC_REG_FLAG_WO |
  77306                           SOC_REG_FLAG_REG_ARRAY,
  77307         SOC_REG_FLAG_COUNTER_FEILDS,
  77308         1,
  77309         soc_BRDC_HBC_RDR_DS_TRANS_CNT_BCM88690_B0r_fields,
  77310         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77311         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77312         -1,
  77313         -1,
  77314     },
  77315 #endif /* chips */
  77316 
  77317 #if defined(BCM_88690_A0)
  77318     { /* SOC_REG_INT_BRDC_HBC_RDR_INTERRUPT_MASK_REGISTERr */
  77319         soc_block_list[169],
  77320         soc_genreg,
  77321         1,
  77322         0,
  77323         0x105,
  77324         0,
  77325         0,
  77326         2,
  77327         soc_BRDC_HBC_RDR_INTERRUPT_MASK_REGISTERr_fields,
  77328         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77329         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77330         -1,
  77331         -1,
  77332     },
  77333 #endif /* chips */
  77334 
  77335 #if defined(BCM_88690_B0)
  77336     { /* SOC_REG_INT_BRDC_HBC_RDR_INTERRUPT_MASK_REGISTER_BCM88690_B0r */
  77337         soc_block_list[169],
  77338         soc_genreg,
  77339         1,
  77340         0,
  77341         0x104,
  77342         SOC_REG_FLAG_WO,
  77343         0,
  77344         2,
  77345         soc_BRDC_HBC_RDR_INTERRUPT_MASK_REGISTER_BCM88690_B0r_fields,
  77346         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77347         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77348         -1,
  77349         -1,
  77350     },
  77351 #endif /* chips */
  77352 
  77353 #if defined(BCM_88690_A0)
  77354     { /* SOC_REG_INT_BRDC_HBC_RDR_INTERRUPT_REGISTERr */
  77355         soc_block_list[169],
  77356         soc_genreg,
  77357         1,
  77358         0,
  77359         0x104,
  77360         SOC_REG_FLAG_INTERRUPT |
  77361                           SOC_REG_FLAG_SIGNAL,
  77362         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  77363         2,
  77364         soc_BRDC_HBC_RDR_INTERRUPT_REGISTERr_fields,
  77365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77366         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77367         -1,
  77368         -1,
  77369     },
  77370 #endif /* chips */
  77371 
  77372 #if defined(BCM_88690_B0)
  77373     { /* SOC_REG_INT_BRDC_HBC_RDR_INTERRUPT_REGISTER_BCM88690_B0r */
  77374         soc_block_list[169],
  77375         soc_genreg,
  77376         1,
  77377         0,
  77378         0x103,
  77379         SOC_REG_FLAG_WO |
  77380                           SOC_REG_FLAG_INTERRUPT |
  77381                           SOC_REG_FLAG_SIGNAL,
  77382         SOC_REG_FLAG_CLEAR_BITS_ON_WRITE,
  77383         2,
  77384         soc_BRDC_HBC_RDR_INTERRUPT_REGISTER_BCM88690_B0r_fields,
  77385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77386         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77387         -1,
  77388         -1,
  77389     },
  77390 #endif /* chips */
  77391 
  77392 #if defined(BCM_88690_A0)
  77393     { /* SOC_REG_INT_BRDC_HBC_RDR_INTERRUPT_REGISTER_TESTr */
  77394         soc_block_list[169],
  77395         soc_genreg,
  77396         1,
  77397         0,
  77398         0x106,
  77399         0,
  77400         0,
  77401         1,
  77402         soc_BRDC_HBC_RDR_INTERRUPT_REGISTER_TESTr_fields,
  77403         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77404         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77405         -1,
  77406         -1,
  77407     },
  77408 #endif /* chips */
  77409 
  77410 #if defined(BCM_88690_B0)
  77411     { /* SOC_REG_INT_BRDC_HBC_RDR_INTERRUPT_REGISTER_TEST_BCM88690_B0r */
  77412         soc_block_list[169],
  77413         soc_genreg,
  77414         1,
  77415         0,
  77416         0x105,
  77417         SOC_REG_FLAG_WO,
  77418         0,
  77419         1,
  77420         soc_BRDC_HBC_RDR_INTERRUPT_REGISTER_TEST_BCM88690_B0r_fields,
  77421         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77422         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  77423         -1,
  77424         -1,
  77425     },
  77426 #endif /* chips */
  77427 
  77428 #if defined(BCM_88690_A0)
  77429     { /* SOC_REG_INT_BRDC_HBC_RDR_RD_INFO_WMKr */
  77430         soc_block_list[169],
  77431         soc_genreg,
  77432         1,
  77433         0,
  77434         0x15d,
  77435         SOC_REG_FLAG_RO,
  77436         SOC_REG_FLAG_INIT_ON_READ,
  77437         1,
  77438         soc_BRDC_HBC_RDR_RD_INFO_WMKr_fields,
  77439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77440         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  77441         -1,
  77442         -1,
  77443     },
  77444 #endif /* chips */
  77445 
  77446 #if defined(BCM_88690_B0)
  77447     { /* SOC_REG_INT_BRDC_HBC_RDR_RD_INFO_WMK_BCM88690_B0r */
  77448         soc_block_list[169],
  77449         soc_genreg,
  77450         1,
  77451         0,
  77452         0x13c,
  77453         SOC_REG_FLAG_RO |
  77454                           SOC_REG_FLAG_WO,
  77455         SOC_REG_FLAG_INIT_ON_READ,
  77456         1,
  77457         soc_BRDC_HBC_RDR_RD_INFO_WMK_BCM88690_B0r_fields,
  77458         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77459         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  77460         -1,
  77461         -1,
  77462     },
  77463 #endif /* chips */
  77464 
  77465 #if defined(BCM_88690_A0)
  77466     { /* SOC_REG_INT_BRDC_HBC_RDR_TOT_TRANS_CNTr */
  77467         soc_block_list[169],
  77468         soc_genreg,
  77469         1,
  77470         0,
  77471         0x15a,
  77472         SOC_REG_FLAG_RO,
  77473         SOC_REG_FLAG_COUNTER_FEILDS,
  77474         1,
  77475         soc_BRDC_HBC_RDR_TOT_TRANS_CNTr_fields,
  77476         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77477         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77478         -1,
  77479         -1,
  77480     },
  77481 #endif /* chips */
  77482 
  77483 #if defined(BCM_88690_B0)
  77484     { /* SOC_REG_INT_BRDC_HBC_RDR_TOT_TRANS_CNT_BCM88690_B0r */
  77485         soc_block_list[169],
  77486         soc_genreg,
  77487         1,
  77488         0,
  77489         0x139,
  77490         SOC_REG_FLAG_RO |
  77491                           SOC_REG_FLAG_WO,
  77492         SOC_REG_FLAG_COUNTER_FEILDS,
  77493         1,
  77494         soc_BRDC_HBC_RDR_TOT_TRANS_CNT_BCM88690_B0r_fields,
  77495         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77496         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77497         -1,
  77498         -1,
  77499     },
  77500 #endif /* chips */
  77501 
  77502 #if defined(BCM_88690_A0)
  77503     { /* SOC_REG_INT_BRDC_HBC_READ_DATA_REORDER_STATUSr */
  77504         soc_block_list[169],
  77505         soc_genreg,
  77506         2,
  77507         0,
  77508         0x114,
  77509         SOC_REG_FLAG_ABOVE_64_BITS |
  77510                           SOC_REG_FLAG_ARRAY |
  77511                           SOC_REG_FLAG_RO |
  77512                           SOC_REG_FLAG_REG_ARRAY,
  77513         0,
  77514         2,
  77515         soc_BRDC_HBC_READ_DATA_REORDER_STATUSr_fields,
  77516         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77517         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77518         -1,
  77519         -1,
  77520     },
  77521 #endif /* chips */
  77522 
  77523 #if defined(BCM_88690_B0)
  77524     { /* SOC_REG_INT_BRDC_HBC_READ_DATA_REORDER_STATUS_BCM88690_B0r */
  77525         soc_block_list[169],
  77526         soc_genreg,
  77527         2,
  77528         0,
  77529         0x113,
  77530         SOC_REG_FLAG_ABOVE_64_BITS |
  77531                           SOC_REG_FLAG_ARRAY |
  77532                           SOC_REG_FLAG_RO |
  77533                           SOC_REG_FLAG_WO |
  77534                           SOC_REG_FLAG_REG_ARRAY,
  77535         0,
  77536         2,
  77537         soc_BRDC_HBC_READ_DATA_REORDER_STATUS_BCM88690_B0r_fields,
  77538         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77539         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77540         -1,
  77541         -1,
  77542     },
  77543 #endif /* chips */
  77544 
  77545 #if defined(BCM_88690_A0)
  77546     { /* SOC_REG_INT_BRDC_HBC_REG_0041r */
  77547         soc_block_list[169],
  77548         soc_genreg,
  77549         1,
  77550         0,
  77551         0x41,
  77552         0,
  77553         0,
  77554         1,
  77555         soc_BRDC_HBC_REG_0041r_fields,
  77556         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77557         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  77558         -1,
  77559         -1,
  77560     },
  77561 #endif /* chips */
  77562 
  77563 #if defined(BCM_88690_B0)
  77564     { /* SOC_REG_INT_BRDC_HBC_REG_0041_BCM88690_B0r */
  77565         soc_block_list[169],
  77566         soc_genreg,
  77567         1,
  77568         0,
  77569         0x41,
  77570         SOC_REG_FLAG_WO,
  77571         0,
  77572         1,
  77573         soc_BRDC_HBC_REG_0041_BCM88690_B0r_fields,
  77574         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77575         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  77576         -1,
  77577         -1,
  77578     },
  77579 #endif /* chips */
  77580 
  77581 #if defined(BCM_88690_A0)
  77582     { /* SOC_REG_INT_BRDC_HBC_REG_00A4r */
  77583         soc_block_list[169],
  77584         soc_genreg,
  77585         1,
  77586         0,
  77587         0xa4,
  77588         0,
  77589         0,
  77590         11,
  77591         soc_BRDC_HBC_REG_00A4r_fields,
  77592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77593         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77594         -1,
  77595         -1,
  77596     },
  77597 #endif /* chips */
  77598 
  77599 #if defined(BCM_88690_A0)
  77600     { /* SOC_REG_INT_BRDC_HBC_REG_00A6r */
  77601         soc_block_list[169],
  77602         soc_genreg,
  77603         1,
  77604         0,
  77605         0xa6,
  77606         0,
  77607         0,
  77608         11,
  77609         soc_BRDC_HBC_REG_00A6r_fields,
  77610         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77611         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77612         -1,
  77613         -1,
  77614     },
  77615 #endif /* chips */
  77616 
  77617 #if defined(BCM_88690_A0)
  77618     { /* SOC_REG_INT_BRDC_HBC_REG_00AAr */
  77619         soc_block_list[169],
  77620         soc_genreg,
  77621         1,
  77622         0,
  77623         0xaa,
  77624         0,
  77625         0,
  77626         22,
  77627         soc_BRDC_HBC_REG_00AAr_fields,
  77628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77629         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  77630         -1,
  77631         -1,
  77632     },
  77633 #endif /* chips */
  77634 
  77635 #if defined(BCM_88690_A0)
  77636     { /* SOC_REG_INT_BRDC_HBC_REG_00C2r */
  77637         soc_block_list[169],
  77638         soc_genreg,
  77639         1,
  77640         0,
  77641         0xc2,
  77642         0,
  77643         0,
  77644         6,
  77645         soc_BRDC_HBC_REG_00C2r_fields,
  77646         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  77647         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  77648         -1,
  77649         -1,
  77650     },
  77651 #endif /* chips */
  77652 
  77653 #if defined(BCM_88690_B0)
  77654     { /* SOC_REG_INT_BRDC_HBC_REG_00C2_BCM88690_B0r */
  77655         soc_block_list[169],
  77656         soc_genreg,
  77657         1,
  77658         0,
  77659         0xc2,
  77660         SOC_REG_FLAG_WO,
  77661         0,
  77662         6,
  77663         soc_BRDC_HBC_REG_00C2_BCM88690_B0r_fields,
  77664         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  77665         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  77666         -1,
  77667         -1,
  77668     },
  77669 #endif /* chips */
  77670 
  77671 #if defined(BCM_88690_A0)
  77672     { /* SOC_REG_INT_BRDC_HBC_RESERVED_MIRROR_ADDRr */
  77673         soc_block_list[169],
  77674         soc_genreg,
  77675         1,
  77676         0,
  77677         0x85,
  77678         0,
  77679         0,
  77680         2,
  77681         soc_BRDC_HBC_RESERVED_MIRROR_ADDRr_fields,
  77682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77683         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  77684         -1,
  77685         -1,
  77686     },
  77687 #endif /* chips */
  77688 
  77689 #if defined(BCM_88690_B0)
  77690     { /* SOC_REG_INT_BRDC_HBC_RESERVED_MIRROR_ADDR_BCM88690_B0r */
  77691         soc_block_list[169],
  77692         soc_genreg,
  77693         1,
  77694         0,
  77695         0x85,
  77696         SOC_REG_FLAG_WO,
  77697         0,
  77698         2,
  77699         soc_BRDC_HBC_RESERVED_MIRROR_ADDR_BCM88690_B0r_fields,
  77700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77701         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  77702         -1,
  77703         -1,
  77704     },
  77705 #endif /* chips */
  77706 
  77707 #if defined(BCM_88690_A0)
  77708     { /* SOC_REG_INT_BRDC_HBC_RESERVED_MTCDr */
  77709         soc_block_list[169],
  77710         soc_genreg,
  77711         1,
  77712         0,
  77713         0xae,
  77714         0,
  77715         0,
  77716         6,
  77717         soc_BRDC_HBC_RESERVED_MTCDr_fields,
  77718         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77719         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  77720         -1,
  77721         -1,
  77722     },
  77723 #endif /* chips */
  77724 
  77725 #if defined(BCM_88690_B0)
  77726     { /* SOC_REG_INT_BRDC_HBC_RESERVED_MTCD_BCM88690_B0r */
  77727         soc_block_list[169],
  77728         soc_genreg,
  77729         1,
  77730         0,
  77731         0xae,
  77732         SOC_REG_FLAG_WO,
  77733         0,
  77734         6,
  77735         soc_BRDC_HBC_RESERVED_MTCD_BCM88690_B0r_fields,
  77736         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77737         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  77738         -1,
  77739         -1,
  77740     },
  77741 #endif /* chips */
  77742 
  77743 #if defined(BCM_88690_A0)
  77744     { /* SOC_REG_INT_BRDC_HBC_RESERVED_MTCPr */
  77745         soc_block_list[169],
  77746         soc_genreg,
  77747         1,
  77748         0,
  77749         0xad,
  77750         SOC_REG_FLAG_64_BITS,
  77751         0,
  77752         17,
  77753         soc_BRDC_HBC_RESERVED_MTCPr_fields,
  77754         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  77755         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  77756         -1,
  77757         -1,
  77758     },
  77759 #endif /* chips */
  77760 
  77761 #if defined(BCM_88690_B0)
  77762     { /* SOC_REG_INT_BRDC_HBC_RESERVED_MTCP_BCM88690_B0r */
  77763         soc_block_list[169],
  77764         soc_genreg,
  77765         1,
  77766         0,
  77767         0xad,
  77768         SOC_REG_FLAG_64_BITS |
  77769                           SOC_REG_FLAG_WO,
  77770         0,
  77771         17,
  77772         soc_BRDC_HBC_RESERVED_MTCP_BCM88690_B0r_fields,
  77773         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  77774         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  77775         -1,
  77776         -1,
  77777     },
  77778 #endif /* chips */
  77779 
  77780 #if defined(BCM_88690_A0)
  77781     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_0r */
  77782         soc_block_list[169],
  77783         soc_genreg,
  77784         1,
  77785         0,
  77786         0x90,
  77787         0,
  77788         0,
  77789         1,
  77790         soc_BRDC_HBC_RESERVED_SPARE_0r_fields,
  77791         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  77792         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77793         -1,
  77794         -1,
  77795     },
  77796 #endif /* chips */
  77797 
  77798 #if defined(BCM_88690_A0)
  77799     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_1r */
  77800         soc_block_list[169],
  77801         soc_genreg,
  77802         1,
  77803         0,
  77804         0x91,
  77805         0,
  77806         0,
  77807         1,
  77808         soc_BRDC_HBC_RESERVED_SPARE_1r_fields,
  77809         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  77810         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77811         -1,
  77812         -1,
  77813     },
  77814 #endif /* chips */
  77815 
  77816 #if defined(BCM_88690_A0)
  77817     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_2r */
  77818         soc_block_list[169],
  77819         soc_genreg,
  77820         1,
  77821         0,
  77822         0x92,
  77823         0,
  77824         0,
  77825         1,
  77826         soc_BRDC_HBC_RESERVED_SPARE_2r_fields,
  77827         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77828         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77829         -1,
  77830         -1,
  77831     },
  77832 #endif /* chips */
  77833 
  77834 #if defined(BCM_88690_A0)
  77835     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_3r */
  77836         soc_block_list[169],
  77837         soc_genreg,
  77838         1,
  77839         0,
  77840         0x93,
  77841         0,
  77842         0,
  77843         1,
  77844         soc_BRDC_HBC_RESERVED_SPARE_3r_fields,
  77845         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77846         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77847         -1,
  77848         -1,
  77849     },
  77850 #endif /* chips */
  77851 
  77852 #if defined(BCM_88690_B0)
  77853     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_0_BCM88690_B0r */
  77854         soc_block_list[169],
  77855         soc_genreg,
  77856         1,
  77857         0,
  77858         0x90,
  77859         SOC_REG_FLAG_WO,
  77860         0,
  77861         1,
  77862         soc_BRDC_HBC_RESERVED_SPARE_0_BCM88690_B0r_fields,
  77863         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  77864         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77865         -1,
  77866         -1,
  77867     },
  77868 #endif /* chips */
  77869 
  77870 #if defined(BCM_88690_B0)
  77871     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_1_BCM88690_B0r */
  77872         soc_block_list[169],
  77873         soc_genreg,
  77874         1,
  77875         0,
  77876         0x91,
  77877         SOC_REG_FLAG_WO,
  77878         0,
  77879         1,
  77880         soc_BRDC_HBC_RESERVED_SPARE_1_BCM88690_B0r_fields,
  77881         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  77882         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77883         -1,
  77884         -1,
  77885     },
  77886 #endif /* chips */
  77887 
  77888 #if defined(BCM_88690_B0)
  77889     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_2_BCM88690_B0r */
  77890         soc_block_list[169],
  77891         soc_genreg,
  77892         1,
  77893         0,
  77894         0x92,
  77895         SOC_REG_FLAG_WO,
  77896         0,
  77897         1,
  77898         soc_BRDC_HBC_RESERVED_SPARE_2_BCM88690_B0r_fields,
  77899         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77900         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77901         -1,
  77902         -1,
  77903     },
  77904 #endif /* chips */
  77905 
  77906 #if defined(BCM_88690_B0)
  77907     { /* SOC_REG_INT_BRDC_HBC_RESERVED_SPARE_3_BCM88690_B0r */
  77908         soc_block_list[169],
  77909         soc_genreg,
  77910         1,
  77911         0,
  77912         0x93,
  77913         SOC_REG_FLAG_WO,
  77914         0,
  77915         1,
  77916         soc_BRDC_HBC_RESERVED_SPARE_3_BCM88690_B0r_fields,
  77917         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77918         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  77919         -1,
  77920         -1,
  77921     },
  77922 #endif /* chips */
  77923 
  77924 #if defined(BCM_88690_A0)
  77925     { /* SOC_REG_INT_BRDC_HBC_RPBQ_CONFIGr */
  77926         soc_block_list[169],
  77927         soc_genreg,
  77928         1,
  77929         0,
  77930         0x131,
  77931         0,
  77932         0,
  77933         2,
  77934         soc_BRDC_HBC_RPBQ_CONFIGr_fields,
  77935         SOC_RESET_VAL_DEC(0x00000108, 0x00000000)
  77936         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  77937         -1,
  77938         -1,
  77939     },
  77940 #endif /* chips */
  77941 
  77942 #if defined(BCM_88690_B0)
  77943     { /* SOC_REG_INT_BRDC_HBC_RPBQ_CONFIG_BCM88690_B0r */
  77944         soc_block_list[169],
  77945         soc_genreg,
  77946         1,
  77947         0,
  77948         0x130,
  77949         SOC_REG_FLAG_WO,
  77950         0,
  77951         2,
  77952         soc_BRDC_HBC_RPBQ_CONFIG_BCM88690_B0r_fields,
  77953         SOC_RESET_VAL_DEC(0x00000108, 0x00000000)
  77954         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  77955         -1,
  77956         -1,
  77957     },
  77958 #endif /* chips */
  77959 
  77960 #if defined(BCM_88690_A0)
  77961     { /* SOC_REG_INT_BRDC_HBC_RPBQ_STATUSr */
  77962         soc_block_list[169],
  77963         soc_genreg,
  77964         1,
  77965         0,
  77966         0x132,
  77967         SOC_REG_FLAG_ABOVE_64_BITS |
  77968                           SOC_REG_FLAG_RO |
  77969                           SOC_REG_FLAG_SIGNAL,
  77970         0,
  77971         1,
  77972         soc_BRDC_HBC_RPBQ_STATUSr_fields,
  77973         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  77974         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  77975         -1,
  77976         -1,
  77977     },
  77978 #endif /* chips */
  77979 
  77980 #if defined(BCM_88690_A0)
  77981     { /* SOC_REG_INT_BRDC_HBC_SBUS_BROADCAST_IDr */
  77982         soc_block_list[169],
  77983         soc_genreg,
  77984         1,
  77985         0,
  77986         0x86,
  77987         0,
  77988         0,
  77989         1,
  77990         soc_BRDC_HBC_SBUS_BROADCAST_IDr_fields,
  77991         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  77992         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  77993         -1,
  77994         -1,
  77995     },
  77996 #endif /* chips */
  77997 
  77998 #if defined(BCM_88690_B0)
  77999     { /* SOC_REG_INT_BRDC_HBC_SBUS_BROADCAST_ID_BCM88690_B0r */
  78000         soc_block_list[169],
  78001         soc_genreg,
  78002         1,
  78003         0,
  78004         0x86,
  78005         SOC_REG_FLAG_WO,
  78006         0,
  78007         1,
  78008         soc_BRDC_HBC_SBUS_BROADCAST_ID_BCM88690_B0r_fields,
  78009         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  78010         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78011         -1,
  78012         -1,
  78013     },
  78014 #endif /* chips */
  78015 
  78016 #if defined(BCM_88690_A0)
  78017     { /* SOC_REG_INT_BRDC_HBC_SBUS_LAST_IN_CHAINr */
  78018         soc_block_list[169],
  78019         soc_genreg,
  78020         1,
  78021         0,
  78022         0x87,
  78023         0,
  78024         0,
  78025         1,
  78026         soc_BRDC_HBC_SBUS_LAST_IN_CHAINr_fields,
  78027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78028         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  78029         -1,
  78030         -1,
  78031     },
  78032 #endif /* chips */
  78033 
  78034 #if defined(BCM_88690_B0)
  78035     { /* SOC_REG_INT_BRDC_HBC_SBUS_LAST_IN_CHAIN_BCM88690_B0r */
  78036         soc_block_list[169],
  78037         soc_genreg,
  78038         1,
  78039         0,
  78040         0x87,
  78041         SOC_REG_FLAG_WO,
  78042         0,
  78043         1,
  78044         soc_BRDC_HBC_SBUS_LAST_IN_CHAIN_BCM88690_B0r_fields,
  78045         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78046         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  78047         -1,
  78048         -1,
  78049     },
  78050 #endif /* chips */
  78051 
  78052 #if defined(BCM_88690_B0)
  78053     { /* SOC_REG_INT_BRDC_HBC_SPECIAL_CLOCK_CONTROLSr */
  78054         soc_block_list[169],
  78055         soc_genreg,
  78056         1,
  78057         0,
  78058         0xc1,
  78059         SOC_REG_FLAG_WO,
  78060         0,
  78061         1,
  78062         soc_BRDC_HBC_SPECIAL_CLOCK_CONTROLSr_fields,
  78063         SOC_RESET_VAL_DEC(0x00000002, 0x00000000)
  78064         SOC_RESET_MASK_DEC(0x00000002, 0x00000000)
  78065         -1,
  78066         -1,
  78067     },
  78068 #endif /* chips */
  78069 
  78070 #if defined(BCM_88690_A0)
  78071     { /* SOC_REG_INT_BRDC_HBC_TSM_CONFIGr */
  78072         soc_block_list[169],
  78073         soc_genreg,
  78074         1,
  78075         0,
  78076         0x16d,
  78077         SOC_REG_FLAG_64_BITS,
  78078         0,
  78079         7,
  78080         soc_BRDC_HBC_TSM_CONFIGr_fields,
  78081         SOC_RESET_VAL_DEC(0xffffffff, 0x00008106)
  78082         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  78083         -1,
  78084         -1,
  78085     },
  78086 #endif /* chips */
  78087 
  78088 #if defined(BCM_88690_B0)
  78089     { /* SOC_REG_INT_BRDC_HBC_TSM_CONFIG_BCM88690_B0r */
  78090         soc_block_list[169],
  78091         soc_genreg,
  78092         1,
  78093         0,
  78094         0x14c,
  78095         SOC_REG_FLAG_64_BITS |
  78096                           SOC_REG_FLAG_WO,
  78097         0,
  78098         7,
  78099         soc_BRDC_HBC_TSM_CONFIG_BCM88690_B0r_fields,
  78100         SOC_RESET_VAL_DEC(0xffffffff, 0x00008106)
  78101         SOC_RESET_MASK_DEC(0xffffffff, 0x1fffffff)
  78102         -1,
  78103         -1,
  78104     },
  78105 #endif /* chips */
  78106 
  78107 #if defined(BCM_88690_A0)
  78108     { /* SOC_REG_INT_BRDC_HBC_TSM_DEBUGr */
  78109         soc_block_list[169],
  78110         soc_genreg,
  78111         1,
  78112         0,
  78113         0x172,
  78114         SOC_REG_FLAG_ABOVE_64_BITS |
  78115                           SOC_REG_FLAG_RO,
  78116         SOC_REG_FLAG_COUNTER_FEILDS |
  78117                           SOC_REG_FLAG_INIT_ON_READ,
  78118         4,
  78119         soc_BRDC_HBC_TSM_DEBUGr_fields,
  78120         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78121         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78122         -1,
  78123         -1,
  78124     },
  78125 #endif /* chips */
  78126 
  78127 #if defined(BCM_88690_B0)
  78128     { /* SOC_REG_INT_BRDC_HBC_TSM_DEBUG_BCM88690_B0r */
  78129         soc_block_list[169],
  78130         soc_genreg,
  78131         1,
  78132         0,
  78133         0x151,
  78134         SOC_REG_FLAG_ABOVE_64_BITS |
  78135                           SOC_REG_FLAG_RO |
  78136                           SOC_REG_FLAG_WO,
  78137         SOC_REG_FLAG_COUNTER_FEILDS |
  78138                           SOC_REG_FLAG_INIT_ON_READ,
  78139         4,
  78140         soc_BRDC_HBC_TSM_DEBUG_BCM88690_B0r_fields,
  78141         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78142         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78143         -1,
  78144         -1,
  78145     },
  78146 #endif /* chips */
  78147 
  78148 #if defined(BCM_88690_A0)
  78149     { /* SOC_REG_INT_BRDC_HBC_TSM_READ_WRITE_SWITCH_CONFIGr */
  78150         soc_block_list[169],
  78151         soc_genreg,
  78152         1,
  78153         0,
  78154         0x16f,
  78155         SOC_REG_FLAG_ABOVE_64_BITS,
  78156         0,
  78157         11,
  78158         soc_BRDC_HBC_TSM_READ_WRITE_SWITCH_CONFIGr_fields,
  78159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78161         -1,
  78162         -1,
  78163     },
  78164 #endif /* chips */
  78165 
  78166 #if defined(BCM_88690_B0)
  78167     { /* SOC_REG_INT_BRDC_HBC_TSM_READ_WRITE_SWITCH_CONFIG_BCM88690_B0r */
  78168         soc_block_list[169],
  78169         soc_genreg,
  78170         1,
  78171         0,
  78172         0x14e,
  78173         SOC_REG_FLAG_ABOVE_64_BITS |
  78174                           SOC_REG_FLAG_WO,
  78175         0,
  78176         11,
  78177         soc_BRDC_HBC_TSM_READ_WRITE_SWITCH_CONFIG_BCM88690_B0r_fields,
  78178         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78179         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78180         -1,
  78181         -1,
  78182     },
  78183 #endif /* chips */
  78184 
  78185 #if defined(BCM_88690_A0)
  78186     { /* SOC_REG_INT_BRDC_HBC_WDB_STATUSr */
  78187         soc_block_list[169],
  78188         soc_genreg,
  78189         1,
  78190         0,
  78191         0x126,
  78192         SOC_REG_FLAG_64_BITS |
  78193                           SOC_REG_FLAG_RO,
  78194         SOC_REG_FLAG_COUNTER_FEILDS |
  78195                           SOC_REG_FLAG_INIT_ON_READ,
  78196         3,
  78197         soc_BRDC_HBC_WDB_STATUSr_fields,
  78198         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78199         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  78200         -1,
  78201         -1,
  78202     },
  78203 #endif /* chips */
  78204 
  78205 #if defined(BCM_88690_B0)
  78206     { /* SOC_REG_INT_BRDC_HBC_WDB_STATUS_BCM88690_B0r */
  78207         soc_block_list[169],
  78208         soc_genreg,
  78209         1,
  78210         0,
  78211         0x125,
  78212         SOC_REG_FLAG_64_BITS |
  78213                           SOC_REG_FLAG_RO |
  78214                           SOC_REG_FLAG_WO,
  78215         SOC_REG_FLAG_COUNTER_FEILDS |
  78216                           SOC_REG_FLAG_INIT_ON_READ,
  78217         3,
  78218         soc_BRDC_HBC_WDB_STATUS_BCM88690_B0r_fields,
  78219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78220         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  78221         -1,
  78222         -1,
  78223     },
  78224 #endif /* chips */
  78225 
  78226 #if defined(BCM_88690_A0)
  78227     { /* SOC_REG_INT_BRDC_HBC_WPBQ_CONFIGr */
  78228         soc_block_list[169],
  78229         soc_genreg,
  78230         1,
  78231         0,
  78232         0x128,
  78233         0,
  78234         0,
  78235         1,
  78236         soc_BRDC_HBC_WPBQ_CONFIGr_fields,
  78237         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  78238         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  78239         -1,
  78240         -1,
  78241     },
  78242 #endif /* chips */
  78243 
  78244 #if defined(BCM_88690_B0)
  78245     { /* SOC_REG_INT_BRDC_HBC_WPBQ_CONFIG_BCM88690_B0r */
  78246         soc_block_list[169],
  78247         soc_genreg,
  78248         1,
  78249         0,
  78250         0x127,
  78251         SOC_REG_FLAG_WO,
  78252         0,
  78253         1,
  78254         soc_BRDC_HBC_WPBQ_CONFIG_BCM88690_B0r_fields,
  78255         SOC_RESET_VAL_DEC(0x00000008, 0x00000000)
  78256         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  78257         -1,
  78258         -1,
  78259     },
  78260 #endif /* chips */
  78261 
  78262 #if defined(BCM_88690_A0)
  78263     { /* SOC_REG_INT_BRDC_HBC_WPBQ_STATUSr */
  78264         soc_block_list[169],
  78265         soc_genreg,
  78266         1,
  78267         0,
  78268         0x129,
  78269         SOC_REG_FLAG_ABOVE_64_BITS |
  78270                           SOC_REG_FLAG_RO |
  78271                           SOC_REG_FLAG_SIGNAL,
  78272         0,
  78273         1,
  78274         soc_BRDC_HBC_WPBQ_STATUSr_fields,
  78275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78277         -1,
  78278         -1,
  78279     },
  78280 #endif /* chips */
  78281 
  78282 #if defined(BCM_88790_A0)
  78283     { /* SOC_REG_INT_BRDC_LCM_ADMIT_DENY_DFL_FULL_CNTr */
  78284         soc_block_list[109],
  78285         soc_genreg,
  78286         1,
  78287         0,
  78288         0x384,
  78289         SOC_REG_FLAG_RO,
  78290         SOC_REG_FLAG_COUNTER_FEILDS,
  78291         1,
  78292         soc_BRDC_LCM_ADMIT_DENY_DFL_FULL_CNTr_fields,
  78293         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78294         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  78295         -1,
  78296         -1,
  78297     },
  78298 #endif /* chips */
  78299 
  78300 #if defined(BCM_88790_A0)
  78301     { /* SOC_REG_INT_BRDC_LCM_ADMIT_DROP_CNTr */
  78302         soc_block_list[109],
  78303         soc_genreg,
  78304         2,
  78305         0,
  78306         0x28b,
  78307         SOC_REG_FLAG_ARRAY |
  78308                           SOC_REG_FLAG_RO |
  78309                           SOC_REG_FLAG_REG_ARRAY,
  78310         SOC_REG_FLAG_COUNTER_FEILDS,
  78311         2,
  78312         soc_BRDC_LCM_ADMIT_DROP_CNTr_fields,
  78313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78314         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  78315         -1,
  78316         -1,
  78317     },
  78318 #endif /* chips */
  78319 
  78320 #if defined(BCM_88790_A0)
  78321     { /* SOC_REG_INT_BRDC_LCM_ADMIT_DROP_CPU_CNTr */
  78322         soc_block_list[109],
  78323         soc_genreg,
  78324         1,
  78325         0,
  78326         0x28d,
  78327         SOC_REG_FLAG_RO,
  78328         SOC_REG_FLAG_COUNTER_FEILDS,
  78329         2,
  78330         soc_BRDC_LCM_ADMIT_DROP_CPU_CNTr_fields,
  78331         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78332         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  78333         -1,
  78334         -1,
  78335     },
  78336 #endif /* chips */
  78337 
  78338 #if defined(BCM_88790_A0)
  78339     { /* SOC_REG_INT_BRDC_LCM_ADMIT_DROP_REASONS_DCHr */
  78340         soc_block_list[109],
  78341         soc_genreg,
  78342         8,
  78343         0,
  78344         0x296,
  78345         SOC_REG_FLAG_ARRAY |
  78346                           SOC_REG_FLAG_RO |
  78347                           SOC_REG_FLAG_REG_ARRAY,
  78348         0,
  78349         1,
  78350         soc_BRDC_LCM_ADMIT_DROP_REASONS_DCHr_fields,
  78351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78352         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  78353         -1,
  78354         -1,
  78355     },
  78356 #endif /* chips */
  78357 
  78358 #if defined(BCM_88790_A0)
  78359     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_0r */
  78360         soc_block_list[109],
  78361         soc_genreg,
  78362         1,
  78363         0,
  78364         0x104,
  78365         0,
  78366         0,
  78367         1,
  78368         soc_BRDC_LCM_AUTO_DOC_NAME_0r_fields,
  78369         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  78370         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  78371         -1,
  78372         -1,
  78373     },
  78374 #endif /* chips */
  78375 
  78376 #if defined(BCM_88790_A0)
  78377     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_1r */
  78378         soc_block_list[109],
  78379         soc_genreg,
  78380         24,
  78381         0,
  78382         0x29e,
  78383         SOC_REG_FLAG_ARRAY |
  78384                           SOC_REG_FLAG_RO |
  78385                           SOC_REG_FLAG_REG_ARRAY,
  78386         0,
  78387         1,
  78388         soc_BRDC_LCM_AUTO_DOC_NAME_1r_fields,
  78389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78390         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  78391         -1,
  78392         -1,
  78393     },
  78394 #endif /* chips */
  78395 
  78396 #if defined(BCM_88790_A0)
  78397     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_2r */
  78398         soc_block_list[109],
  78399         soc_genreg,
  78400         1,
  78401         0,
  78402         0x2b6,
  78403         SOC_REG_FLAG_RO,
  78404         0,
  78405         10,
  78406         soc_BRDC_LCM_AUTO_DOC_NAME_2r_fields,
  78407         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78408         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  78409         -1,
  78410         -1,
  78411     },
  78412 #endif /* chips */
  78413 
  78414 #if defined(BCM_88790_A0)
  78415     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_3r */
  78416         soc_block_list[109],
  78417         soc_genreg,
  78418         1,
  78419         0,
  78420         0x2b7,
  78421         SOC_REG_FLAG_RO,
  78422         0,
  78423         3,
  78424         soc_BRDC_LCM_AUTO_DOC_NAME_3r_fields,
  78425         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78426         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  78427         -1,
  78428         -1,
  78429     },
  78430 #endif /* chips */
  78431 
  78432 #if defined(BCM_88790_A0)
  78433     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_4r */
  78434         soc_block_list[109],
  78435         soc_genreg,
  78436         24,
  78437         0,
  78438         0x2b8,
  78439         SOC_REG_FLAG_ARRAY |
  78440                           SOC_REG_FLAG_RO |
  78441                           SOC_REG_FLAG_REG_ARRAY,
  78442         0,
  78443         3,
  78444         soc_BRDC_LCM_AUTO_DOC_NAME_4r_fields,
  78445         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78446         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  78447         -1,
  78448         -1,
  78449     },
  78450 #endif /* chips */
  78451 
  78452 #if defined(BCM_88790_A0)
  78453     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_5r */
  78454         soc_block_list[109],
  78455         soc_genreg,
  78456         24,
  78457         0,
  78458         0x2d0,
  78459         SOC_REG_FLAG_ARRAY |
  78460                           SOC_REG_FLAG_RO |
  78461                           SOC_REG_FLAG_REG_ARRAY,
  78462         0,
  78463         1,
  78464         soc_BRDC_LCM_AUTO_DOC_NAME_5r_fields,
  78465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78466         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  78467         -1,
  78468         -1,
  78469     },
  78470 #endif /* chips */
  78471 
  78472 #if defined(BCM_88790_A0)
  78473     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_6r */
  78474         soc_block_list[109],
  78475         soc_genreg,
  78476         24,
  78477         0,
  78478         0x2e8,
  78479         SOC_REG_FLAG_ARRAY |
  78480                           SOC_REG_FLAG_RO |
  78481                           SOC_REG_FLAG_REG_ARRAY,
  78482         0,
  78483         1,
  78484         soc_BRDC_LCM_AUTO_DOC_NAME_6r_fields,
  78485         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78486         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  78487         -1,
  78488         -1,
  78489     },
  78490 #endif /* chips */
  78491 
  78492 #if defined(BCM_88790_A0)
  78493     { /* SOC_REG_INT_BRDC_LCM_AUTO_DOC_NAME_7r */
  78494         soc_block_list[109],
  78495         soc_genreg,
  78496         1,
  78497         0,
  78498         0x300,
  78499         SOC_REG_FLAG_RO,
  78500         0,
  78501         2,
  78502         soc_BRDC_LCM_AUTO_DOC_NAME_7r_fields,
  78503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78504         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  78505         -1,
  78506         -1,
  78507     },
  78508 #endif /* chips */
  78509 
  78510 #if defined(BCM_88790_A0)
  78511     { /* SOC_REG_INT_BRDC_LCM_DCML_SEPARATION_REGISTERr */
  78512         soc_block_list[109],
  78513         soc_genreg,
  78514         1,
  78515         0,
  78516         0x307,
  78517         0,
  78518         0,
  78519         6,
  78520         soc_BRDC_LCM_DCML_SEPARATION_REGISTERr_fields,
  78521         SOC_RESET_VAL_DEC(0x00000188, 0x00000000)
  78522         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  78523         -1,
  78524         -1,
  78525     },
  78526 #endif /* chips */
  78527 
  78528 #if defined(BCM_88790_A0)
  78529     { /* SOC_REG_INT_BRDC_LCM_DFL_BANKS_MC_DROP_THr */
  78530         soc_block_list[109],
  78531         soc_genreg,
  78532         1,
  78533         0,
  78534         0x208,
  78535         SOC_REG_FLAG_64_BITS,
  78536         0,
  78537         4,
  78538         soc_BRDC_LCM_DFL_BANKS_MC_DROP_THr_fields,
  78539         SOC_RESET_VAL_DEC(0xc2384708, 0x00000e11)
  78540         SOC_RESET_MASK_DEC(0xffffffff, 0x00000fff)
  78541         -1,
  78542         -1,
  78543     },
  78544 #endif /* chips */
  78545 
  78546 #if defined(BCM_88790_A0)
  78547     { /* SOC_REG_INT_BRDC_LCM_DFL_BANKS_THr */
  78548         soc_block_list[109],
  78549         soc_genreg,
  78550         1,
  78551         0,
  78552         0x207,
  78553         0,
  78554         0,
  78555         1,
  78556         soc_BRDC_LCM_DFL_BANKS_THr_fields,
  78557         SOC_RESET_VAL_DEC(0x00000708, 0x00000000)
  78558         SOC_RESET_MASK_DEC(0x000007ff, 0x00000000)
  78559         -1,
  78560         -1,
  78561     },
  78562 #endif /* chips */
  78563 
  78564 #if defined(BCM_88790_A0)
  78565     { /* SOC_REG_INT_BRDC_LCM_DFL_FC_TH_METHOD_1r */
  78566         soc_block_list[109],
  78567         soc_genreg,
  78568         1,
  78569         0,
  78570         0x203,
  78571         SOC_REG_FLAG_64_BITS,
  78572         0,
  78573         3,
  78574         soc_BRDC_LCM_DFL_FC_TH_METHOD_1r_fields,
  78575         SOC_RESET_VAL_DEC(0x8ca08ca0, 0x00008ca0)
  78576         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  78577         -1,
  78578         -1,
  78579     },
  78580 #endif /* chips */
  78581 
  78582 #if defined(BCM_88790_A0)
  78583     { /* SOC_REG_INT_BRDC_LCM_DFL_FC_TH_METHOD_2r */
  78584         soc_block_list[109],
  78585         soc_genreg,
  78586         1,
  78587         0,
  78588         0x205,
  78589         SOC_REG_FLAG_64_BITS,
  78590         0,
  78591         3,
  78592         soc_BRDC_LCM_DFL_FC_TH_METHOD_2r_fields,
  78593         SOC_RESET_VAL_DEC(0xf00d2f00, 0x0d2f00d2)
  78594         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  78595         -1,
  78596         -1,
  78597     },
  78598 #endif /* chips */
  78599 
  78600 #if defined(BCM_88790_A0)
  78601     { /* SOC_REG_INT_BRDC_LCM_DFL_GCI_COPIES_THRESHOLDSr */
  78602         soc_block_list[109],
  78603         soc_genreg,
  78604         1,
  78605         0,
  78606         0x1f2,
  78607         SOC_REG_FLAG_ABOVE_64_BITS,
  78608         0,
  78609         9,
  78610         soc_BRDC_LCM_DFL_GCI_COPIES_THRESHOLDSr_fields,
  78611         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78612         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78613         -1,
  78614         -1,
  78615     },
  78616 #endif /* chips */
  78617 
  78618 #if defined(BCM_88790_A0)
  78619     { /* SOC_REG_INT_BRDC_LCM_DFL_GCI_TH_METHOD_1r */
  78620         soc_block_list[109],
  78621         soc_genreg,
  78622         1,
  78623         0,
  78624         0x1e7,
  78625         SOC_REG_FLAG_ABOVE_64_BITS,
  78626         0,
  78627         9,
  78628         soc_BRDC_LCM_DFL_GCI_TH_METHOD_1r_fields,
  78629         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78630         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78631         -1,
  78632         -1,
  78633     },
  78634 #endif /* chips */
  78635 
  78636 #if defined(BCM_88790_A0)
  78637     { /* SOC_REG_INT_BRDC_LCM_DFL_GCI_TH_METHOD_2r */
  78638         soc_block_list[109],
  78639         soc_genreg,
  78640         1,
  78641         0,
  78642         0x1ec,
  78643         SOC_REG_FLAG_ABOVE_64_BITS,
  78644         0,
  78645         9,
  78646         soc_BRDC_LCM_DFL_GCI_TH_METHOD_2r_fields,
  78647         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78648         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78649         -1,
  78650         -1,
  78651     },
  78652 #endif /* chips */
  78653 
  78654 #if defined(BCM_88790_A0)
  78655     { /* SOC_REG_INT_BRDC_LCM_DFL_MC_COPIES_ADMIT_THRESHOLDSr */
  78656         soc_block_list[109],
  78657         soc_genreg,
  78658         1,
  78659         0,
  78660         0x1e4,
  78661         SOC_REG_FLAG_ABOVE_64_BITS,
  78662         0,
  78663         4,
  78664         soc_BRDC_LCM_DFL_MC_COPIES_ADMIT_THRESHOLDSr_fields,
  78665         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78666         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78667         -1,
  78668         -1,
  78669     },
  78670 #endif /* chips */
  78671 
  78672 #if defined(BCM_88790_A0)
  78673     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_1r */
  78674         soc_block_list[109],
  78675         soc_genreg,
  78676         1,
  78677         0,
  78678         0x1db,
  78679         SOC_REG_FLAG_ABOVE_64_BITS,
  78680         0,
  78681         8,
  78682         soc_BRDC_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_1r_fields,
  78683         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78684         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78685         -1,
  78686         -1,
  78687     },
  78688 #endif /* chips */
  78689 
  78690 #if defined(BCM_88790_A0)
  78691     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_2r */
  78692         soc_block_list[109],
  78693         soc_genreg,
  78694         1,
  78695         0,
  78696         0x1df,
  78697         SOC_REG_FLAG_ABOVE_64_BITS,
  78698         0,
  78699         8,
  78700         soc_BRDC_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_2r_fields,
  78701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78702         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78703         -1,
  78704         -1,
  78705     },
  78706 #endif /* chips */
  78707 
  78708 #if defined(BCM_88790_A0)
  78709     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_COPIES_FRAG_CNT_INFO_Pr */
  78710         soc_block_list[109],
  78711         soc_genreg,
  78712         3,
  78713         0,
  78714         0x23e,
  78715         SOC_REG_FLAG_ARRAY |
  78716                           SOC_REG_FLAG_RO |
  78717                           SOC_REG_FLAG_REG_ARRAY,
  78718         0,
  78719         1,
  78720         soc_BRDC_LCM_DFL_PIPE_COPIES_FRAG_CNT_INFO_Pr_fields,
  78721         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78722         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  78723         -1,
  78724         -1,
  78725     },
  78726 #endif /* chips */
  78727 
  78728 #if defined(BCM_88790_A0)
  78729     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_MC_FRAG_CNT_INFO_Pr */
  78730         soc_block_list[109],
  78731         soc_genreg,
  78732         3,
  78733         0,
  78734         0x241,
  78735         SOC_REG_FLAG_ARRAY |
  78736                           SOC_REG_FLAG_RO |
  78737                           SOC_REG_FLAG_REG_ARRAY,
  78738         0,
  78739         1,
  78740         soc_BRDC_LCM_DFL_PIPE_MC_FRAG_CNT_INFO_Pr_fields,
  78741         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78742         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78743         -1,
  78744         -1,
  78745     },
  78746 #endif /* chips */
  78747 
  78748 #if defined(BCM_88790_A0)
  78749     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_DIFF_Pr */
  78750         soc_block_list[109],
  78751         soc_genreg,
  78752         3,
  78753         0,
  78754         0x23b,
  78755         SOC_REG_FLAG_ARRAY |
  78756                           SOC_REG_FLAG_RO |
  78757                           SOC_REG_FLAG_REG_ARRAY,
  78758         0,
  78759         1,
  78760         soc_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_DIFF_Pr_fields,
  78761         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78762         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  78763         -1,
  78764         -1,
  78765     },
  78766 #endif /* chips */
  78767 
  78768 #if defined(BCM_88790_A0)
  78769     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_1_Pr */
  78770         soc_block_list[109],
  78771         soc_genreg,
  78772         3,
  78773         0,
  78774         0x232,
  78775         SOC_REG_FLAG_ARRAY |
  78776                           SOC_REG_FLAG_RO |
  78777                           SOC_REG_FLAG_REG_ARRAY,
  78778         0,
  78779         1,
  78780         soc_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_1_Pr_fields,
  78781         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78782         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78783         -1,
  78784         -1,
  78785     },
  78786 #endif /* chips */
  78787 
  78788 #if defined(BCM_88790_A0)
  78789     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_2_Pr */
  78790         soc_block_list[109],
  78791         soc_genreg,
  78792         3,
  78793         0,
  78794         0x238,
  78795         SOC_REG_FLAG_ARRAY |
  78796                           SOC_REG_FLAG_RO |
  78797                           SOC_REG_FLAG_REG_ARRAY,
  78798         0,
  78799         1,
  78800         soc_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_2_Pr_fields,
  78801         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78802         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  78803         -1,
  78804         -1,
  78805     },
  78806 #endif /* chips */
  78807 
  78808 #if defined(BCM_88790_A0)
  78809     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_REFr */
  78810         soc_block_list[109],
  78811         soc_genreg,
  78812         1,
  78813         0,
  78814         0x105,
  78815         0,
  78816         0,
  78817         3,
  78818         soc_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_REFr_fields,
  78819         SOC_RESET_VAL_DEC(0x0000003f, 0x00000000)
  78820         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  78821         -1,
  78822         -1,
  78823     },
  78824 #endif /* chips */
  78825 
  78826 #if defined(BCM_88790_A0)
  78827     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_1_Pr */
  78828         soc_block_list[109],
  78829         soc_genreg,
  78830         3,
  78831         0,
  78832         0x22f,
  78833         SOC_REG_FLAG_ARRAY |
  78834                           SOC_REG_FLAG_RO |
  78835                           SOC_REG_FLAG_REG_ARRAY,
  78836         0,
  78837         1,
  78838         soc_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_1_Pr_fields,
  78839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78840         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  78841         -1,
  78842         -1,
  78843     },
  78844 #endif /* chips */
  78845 
  78846 #if defined(BCM_88790_A0)
  78847     { /* SOC_REG_INT_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_2_Pr */
  78848         soc_block_list[109],
  78849         soc_genreg,
  78850         3,
  78851         0,
  78852         0x235,
  78853         SOC_REG_FLAG_ARRAY |
  78854                           SOC_REG_FLAG_RO |
  78855                           SOC_REG_FLAG_REG_ARRAY,
  78856         0,
  78857         1,
  78858         soc_BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_2_Pr_fields,
  78859         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78860         SOC_RESET_MASK_DEC(0x000fffff, 0x00000000)
  78861         -1,
  78862         -1,
  78863     },
  78864 #endif /* chips */
  78865 
  78866 #if defined(BCM_88790_A0)
  78867     { /* SOC_REG_INT_BRDC_LCM_DFL_RCI_TH_METHOD_1r */
  78868         soc_block_list[109],
  78869         soc_genreg,
  78870         1,
  78871         0,
  78872         0x1f8,
  78873         SOC_REG_FLAG_ABOVE_64_BITS,
  78874         0,
  78875         9,
  78876         soc_BRDC_LCM_DFL_RCI_TH_METHOD_1r_fields,
  78877         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78878         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78879         -1,
  78880         -1,
  78881     },
  78882 #endif /* chips */
  78883 
  78884 #if defined(BCM_88790_A0)
  78885     { /* SOC_REG_INT_BRDC_LCM_DFL_RCI_TH_METHOD_2r */
  78886         soc_block_list[109],
  78887         soc_genreg,
  78888         1,
  78889         0,
  78890         0x1fd,
  78891         SOC_REG_FLAG_ABOVE_64_BITS,
  78892         0,
  78893         9,
  78894         soc_BRDC_LCM_DFL_RCI_TH_METHOD_2r_fields,
  78895         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78896         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78897         -1,
  78898         -1,
  78899     },
  78900 #endif /* chips */
  78901 
  78902 #if defined(BCM_88790_A0)
  78903     { /* SOC_REG_INT_BRDC_LCM_DISABLE_MACr */
  78904         soc_block_list[109],
  78905         soc_genreg,
  78906         1,
  78907         0,
  78908         0x356,
  78909         0,
  78910         0,
  78911         1,
  78912         soc_BRDC_LCM_DISABLE_MACr_fields,
  78913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78914         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  78915         -1,
  78916         -1,
  78917     },
  78918 #endif /* chips */
  78919 
  78920 #if defined(BCM_88790_A0)
  78921     { /* SOC_REG_INT_BRDC_LCM_DTL_ADMIT_LR_TH_PROFILEr */
  78922         soc_block_list[109],
  78923         soc_genreg,
  78924         2,
  78925         0,
  78926         0x178,
  78927         SOC_REG_FLAG_ABOVE_64_BITS |
  78928                           SOC_REG_FLAG_ARRAY |
  78929                           SOC_REG_FLAG_REG_ARRAY,
  78930         0,
  78931         16,
  78932         soc_BRDC_LCM_DTL_ADMIT_LR_TH_PROFILEr_fields,
  78933         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78934         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78935         -1,
  78936         -1,
  78937     },
  78938 #endif /* chips */
  78939 
  78940 #if defined(BCM_88790_A0)
  78941     { /* SOC_REG_INT_BRDC_LCM_DTL_ADMIT_NLR_TH_PROFILEr */
  78942         soc_block_list[109],
  78943         soc_genreg,
  78944         2,
  78945         0,
  78946         0x16a,
  78947         SOC_REG_FLAG_ABOVE_64_BITS |
  78948                           SOC_REG_FLAG_ARRAY |
  78949                           SOC_REG_FLAG_REG_ARRAY,
  78950         0,
  78951         16,
  78952         soc_BRDC_LCM_DTL_ADMIT_NLR_TH_PROFILEr_fields,
  78953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78954         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  78955         -1,
  78956         -1,
  78957     },
  78958 #endif /* chips */
  78959 
  78960 #if defined(BCM_88790_A0)
  78961     { /* SOC_REG_INT_BRDC_LCM_DTL_CPU_CELL_CNTr */
  78962         soc_block_list[109],
  78963         soc_genreg,
  78964         1,
  78965         0,
  78966         0x37b,
  78967         SOC_REG_FLAG_RO,
  78968         SOC_REG_FLAG_COUNTER_FEILDS,
  78969         1,
  78970         soc_BRDC_LCM_DTL_CPU_CELL_CNTr_fields,
  78971         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  78972         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  78973         -1,
  78974         -1,
  78975     },
  78976 #endif /* chips */
  78977 
  78978 #if defined(BCM_88790_A0)
  78979     { /* SOC_REG_INT_BRDC_LCM_DTL_CPU_TAGS_THr */
  78980         soc_block_list[109],
  78981         soc_genreg,
  78982         1,
  78983         0,
  78984         0x20e,
  78985         0,
  78986         0,
  78987         1,
  78988         soc_BRDC_LCM_DTL_CPU_TAGS_THr_fields,
  78989         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  78990         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  78991         -1,
  78992         -1,
  78993     },
  78994 #endif /* chips */
  78995 
  78996 #if defined(BCM_88790_A0)
  78997     { /* SOC_REG_INT_BRDC_LCM_DTL_CPU_TAG_FIFO_STATUSr */
  78998         soc_block_list[109],
  78999         soc_genreg,
  79000         1,
  79001         0,
  79002         0x28a,
  79003         SOC_REG_FLAG_RO,
  79004         0,
  79005         2,
  79006         soc_BRDC_LCM_DTL_CPU_TAG_FIFO_STATUSr_fields,
  79007         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79008         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  79009         -1,
  79010         -1,
  79011     },
  79012 #endif /* chips */
  79013 
  79014 #if defined(BCM_88790_A0)
  79015     { /* SOC_REG_INT_BRDC_LCM_DTL_DROPPED_IP_PR_P_0_CNTr */
  79016         soc_block_list[109],
  79017         soc_genreg,
  79018         4,
  79019         0,
  79020         0x35a,
  79021         SOC_REG_FLAG_ARRAY |
  79022                           SOC_REG_FLAG_RO |
  79023                           SOC_REG_FLAG_REG_ARRAY,
  79024         SOC_REG_FLAG_COUNTER_FEILDS,
  79025         1,
  79026         soc_BRDC_LCM_DTL_DROPPED_IP_PR_P_0_CNTr_fields,
  79027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79028         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79029         -1,
  79030         -1,
  79031     },
  79032 #endif /* chips */
  79033 
  79034 #if defined(BCM_88790_A0)
  79035     { /* SOC_REG_INT_BRDC_LCM_DTL_DROPPED_IP_PR_P_1_CNTr */
  79036         soc_block_list[109],
  79037         soc_genreg,
  79038         4,
  79039         0,
  79040         0x35e,
  79041         SOC_REG_FLAG_ARRAY |
  79042                           SOC_REG_FLAG_RO |
  79043                           SOC_REG_FLAG_REG_ARRAY,
  79044         SOC_REG_FLAG_COUNTER_FEILDS,
  79045         1,
  79046         soc_BRDC_LCM_DTL_DROPPED_IP_PR_P_1_CNTr_fields,
  79047         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79048         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79049         -1,
  79050         -1,
  79051     },
  79052 #endif /* chips */
  79053 
  79054 #if defined(BCM_88790_A0)
  79055     { /* SOC_REG_INT_BRDC_LCM_DTL_DROPPED_IP_PR_P_2_CNTr */
  79056         soc_block_list[109],
  79057         soc_genreg,
  79058         4,
  79059         0,
  79060         0x362,
  79061         SOC_REG_FLAG_ARRAY |
  79062                           SOC_REG_FLAG_RO |
  79063                           SOC_REG_FLAG_REG_ARRAY,
  79064         SOC_REG_FLAG_COUNTER_FEILDS,
  79065         1,
  79066         soc_BRDC_LCM_DTL_DROPPED_IP_PR_P_2_CNTr_fields,
  79067         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79068         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79069         -1,
  79070         -1,
  79071     },
  79072 #endif /* chips */
  79073 
  79074 #if defined(BCM_88790_A0)
  79075     { /* SOC_REG_INT_BRDC_LCM_DTL_DROPPED_SRC_P_CNTr */
  79076         soc_block_list[109],
  79077         soc_genreg,
  79078         3,
  79079         0,
  79080         0x366,
  79081         SOC_REG_FLAG_ARRAY |
  79082                           SOC_REG_FLAG_RO |
  79083                           SOC_REG_FLAG_REG_ARRAY,
  79084         SOC_REG_FLAG_COUNTER_FEILDS,
  79085         1,
  79086         soc_BRDC_LCM_DTL_DROPPED_SRC_P_CNTr_fields,
  79087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79088         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79089         -1,
  79090         -1,
  79091     },
  79092 #endif /* chips */
  79093 
  79094 #if defined(BCM_88790_A0)
  79095     { /* SOC_REG_INT_BRDC_LCM_DTL_FC_TH_LR_PROFILEr */
  79096         soc_block_list[109],
  79097         soc_genreg,
  79098         2,
  79099         0,
  79100         0x1d4,
  79101         SOC_REG_FLAG_ABOVE_64_BITS |
  79102                           SOC_REG_FLAG_ARRAY |
  79103                           SOC_REG_FLAG_REG_ARRAY,
  79104         0,
  79105         6,
  79106         soc_BRDC_LCM_DTL_FC_TH_LR_PROFILEr_fields,
  79107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79108         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79109         -1,
  79110         -1,
  79111     },
  79112 #endif /* chips */
  79113 
  79114 #if defined(BCM_88790_A0)
  79115     { /* SOC_REG_INT_BRDC_LCM_DTL_FC_TH_NLR_PROFILEr */
  79116         soc_block_list[109],
  79117         soc_genreg,
  79118         2,
  79119         0,
  79120         0x1ce,
  79121         SOC_REG_FLAG_ABOVE_64_BITS |
  79122                           SOC_REG_FLAG_ARRAY |
  79123                           SOC_REG_FLAG_REG_ARRAY,
  79124         0,
  79125         6,
  79126         soc_BRDC_LCM_DTL_FC_TH_NLR_PROFILEr_fields,
  79127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79128         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79129         -1,
  79130         -1,
  79131     },
  79132 #endif /* chips */
  79133 
  79134 #if defined(BCM_88790_A0)
  79135     { /* SOC_REG_INT_BRDC_LCM_DTL_FIFOS_DEPTH_TYPEr */
  79136         soc_block_list[109],
  79137         soc_genreg,
  79138         2,
  79139         0,
  79140         0x216,
  79141         SOC_REG_FLAG_64_BITS |
  79142                           SOC_REG_FLAG_ARRAY |
  79143                           SOC_REG_FLAG_REG_ARRAY,
  79144         0,
  79145         3,
  79146         soc_BRDC_LCM_DTL_FIFOS_DEPTH_TYPEr_fields,
  79147         SOC_RESET_VAL_DEC(0x54554554, 0x00000005)
  79148         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  79149         -1,
  79150         -1,
  79151     },
  79152 #endif /* chips */
  79153 
  79154 #if defined(BCM_88790_A0)
  79155     { /* SOC_REG_INT_BRDC_LCM_DTL_FRAG_MAX_LEVEL_LR_Pr */
  79156         soc_block_list[109],
  79157         soc_genreg,
  79158         3,
  79159         0,
  79160         0x286,
  79161         SOC_REG_FLAG_ARRAY |
  79162                           SOC_REG_FLAG_RO |
  79163                           SOC_REG_FLAG_REG_ARRAY,
  79164         0,
  79165         2,
  79166         soc_BRDC_LCM_DTL_FRAG_MAX_LEVEL_LR_Pr_fields,
  79167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79168         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  79169         -1,
  79170         -1,
  79171     },
  79172 #endif /* chips */
  79173 
  79174 #if defined(BCM_88790_A0)
  79175     { /* SOC_REG_INT_BRDC_LCM_DTL_FRAG_MAX_LEVEL_NLR_Pr */
  79176         soc_block_list[109],
  79177         soc_genreg,
  79178         3,
  79179         0,
  79180         0x283,
  79181         SOC_REG_FLAG_ARRAY |
  79182                           SOC_REG_FLAG_RO |
  79183                           SOC_REG_FLAG_REG_ARRAY,
  79184         0,
  79185         2,
  79186         soc_BRDC_LCM_DTL_FRAG_MAX_LEVEL_NLR_Pr_fields,
  79187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79188         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  79189         -1,
  79190         -1,
  79191     },
  79192 #endif /* chips */
  79193 
  79194 #if defined(BCM_88790_A0)
  79195     { /* SOC_REG_INT_BRDC_LCM_DTL_GCI_TH_P_0_LR_PROFILEr */
  79196         soc_block_list[109],
  79197         soc_genreg,
  79198         2,
  79199         0,
  79200         0x198,
  79201         SOC_REG_FLAG_ABOVE_64_BITS |
  79202                           SOC_REG_FLAG_ARRAY |
  79203                           SOC_REG_FLAG_REG_ARRAY,
  79204         0,
  79205         6,
  79206         soc_BRDC_LCM_DTL_GCI_TH_P_0_LR_PROFILEr_fields,
  79207         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79208         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79209         -1,
  79210         -1,
  79211     },
  79212 #endif /* chips */
  79213 
  79214 #if defined(BCM_88790_A0)
  79215     { /* SOC_REG_INT_BRDC_LCM_DTL_GCI_TH_P_0_NLR_PROFILEr */
  79216         soc_block_list[109],
  79217         soc_genreg,
  79218         2,
  79219         0,
  79220         0x186,
  79221         SOC_REG_FLAG_ABOVE_64_BITS |
  79222                           SOC_REG_FLAG_ARRAY |
  79223                           SOC_REG_FLAG_REG_ARRAY,
  79224         0,
  79225         6,
  79226         soc_BRDC_LCM_DTL_GCI_TH_P_0_NLR_PROFILEr_fields,
  79227         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79228         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79229         -1,
  79230         -1,
  79231     },
  79232 #endif /* chips */
  79233 
  79234 #if defined(BCM_88790_A0)
  79235     { /* SOC_REG_INT_BRDC_LCM_DTL_GCI_TH_P_1_LR_PROFILEr */
  79236         soc_block_list[109],
  79237         soc_genreg,
  79238         2,
  79239         0,
  79240         0x19e,
  79241         SOC_REG_FLAG_ABOVE_64_BITS |
  79242                           SOC_REG_FLAG_ARRAY |
  79243                           SOC_REG_FLAG_REG_ARRAY,
  79244         0,
  79245         6,
  79246         soc_BRDC_LCM_DTL_GCI_TH_P_1_LR_PROFILEr_fields,
  79247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79248         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79249         -1,
  79250         -1,
  79251     },
  79252 #endif /* chips */
  79253 
  79254 #if defined(BCM_88790_A0)
  79255     { /* SOC_REG_INT_BRDC_LCM_DTL_GCI_TH_P_1_NLR_PROFILEr */
  79256         soc_block_list[109],
  79257         soc_genreg,
  79258         2,
  79259         0,
  79260         0x18c,
  79261         SOC_REG_FLAG_ABOVE_64_BITS |
  79262                           SOC_REG_FLAG_ARRAY |
  79263                           SOC_REG_FLAG_REG_ARRAY,
  79264         0,
  79265         6,
  79266         soc_BRDC_LCM_DTL_GCI_TH_P_1_NLR_PROFILEr_fields,
  79267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79268         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79269         -1,
  79270         -1,
  79271     },
  79272 #endif /* chips */
  79273 
  79274 #if defined(BCM_88790_A0)
  79275     { /* SOC_REG_INT_BRDC_LCM_DTL_GCI_TH_P_2_LR_PROFILEr */
  79276         soc_block_list[109],
  79277         soc_genreg,
  79278         2,
  79279         0,
  79280         0x1a4,
  79281         SOC_REG_FLAG_ABOVE_64_BITS |
  79282                           SOC_REG_FLAG_ARRAY |
  79283                           SOC_REG_FLAG_REG_ARRAY,
  79284         0,
  79285         6,
  79286         soc_BRDC_LCM_DTL_GCI_TH_P_2_LR_PROFILEr_fields,
  79287         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79288         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79289         -1,
  79290         -1,
  79291     },
  79292 #endif /* chips */
  79293 
  79294 #if defined(BCM_88790_A0)
  79295     { /* SOC_REG_INT_BRDC_LCM_DTL_GCI_TH_P_2_NLR_PROFILEr */
  79296         soc_block_list[109],
  79297         soc_genreg,
  79298         2,
  79299         0,
  79300         0x192,
  79301         SOC_REG_FLAG_ABOVE_64_BITS |
  79302                           SOC_REG_FLAG_ARRAY |
  79303                           SOC_REG_FLAG_REG_ARRAY,
  79304         0,
  79305         6,
  79306         soc_BRDC_LCM_DTL_GCI_TH_P_2_NLR_PROFILEr_fields,
  79307         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79308         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79309         -1,
  79310         -1,
  79311     },
  79312 #endif /* chips */
  79313 
  79314 #if defined(BCM_88790_A0)
  79315     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_CPU_CELL_CNTr */
  79316         soc_block_list[109],
  79317         soc_genreg,
  79318         1,
  79319         0,
  79320         0x37c,
  79321         SOC_REG_FLAG_RO,
  79322         SOC_REG_FLAG_COUNTER_FEILDS,
  79323         1,
  79324         soc_BRDC_LCM_DTL_LCLRT_CPU_CELL_CNTr_fields,
  79325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79326         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79327         -1,
  79328         -1,
  79329     },
  79330 #endif /* chips */
  79331 
  79332 #if defined(BCM_88790_A0)
  79333     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_0_CNTr */
  79334         soc_block_list[109],
  79335         soc_genreg,
  79336         4,
  79337         0,
  79338         0x36c,
  79339         SOC_REG_FLAG_ARRAY |
  79340                           SOC_REG_FLAG_RO |
  79341                           SOC_REG_FLAG_REG_ARRAY,
  79342         SOC_REG_FLAG_COUNTER_FEILDS,
  79343         1,
  79344         soc_BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_0_CNTr_fields,
  79345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79346         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79347         -1,
  79348         -1,
  79349     },
  79350 #endif /* chips */
  79351 
  79352 #if defined(BCM_88790_A0)
  79353     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_1_CNTr */
  79354         soc_block_list[109],
  79355         soc_genreg,
  79356         4,
  79357         0,
  79358         0x370,
  79359         SOC_REG_FLAG_ARRAY |
  79360                           SOC_REG_FLAG_RO |
  79361                           SOC_REG_FLAG_REG_ARRAY,
  79362         SOC_REG_FLAG_COUNTER_FEILDS,
  79363         1,
  79364         soc_BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_1_CNTr_fields,
  79365         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79366         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79367         -1,
  79368         -1,
  79369     },
  79370 #endif /* chips */
  79371 
  79372 #if defined(BCM_88790_A0)
  79373     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_2_CNTr */
  79374         soc_block_list[109],
  79375         soc_genreg,
  79376         4,
  79377         0,
  79378         0x374,
  79379         SOC_REG_FLAG_ARRAY |
  79380                           SOC_REG_FLAG_RO |
  79381                           SOC_REG_FLAG_REG_ARRAY,
  79382         SOC_REG_FLAG_COUNTER_FEILDS,
  79383         1,
  79384         soc_BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_2_CNTr_fields,
  79385         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79386         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79387         -1,
  79388         -1,
  79389     },
  79390 #endif /* chips */
  79391 
  79392 #if defined(BCM_88790_A0)
  79393     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_DROPPED_SRC_P_CNTr */
  79394         soc_block_list[109],
  79395         soc_genreg,
  79396         3,
  79397         0,
  79398         0x378,
  79399         SOC_REG_FLAG_ARRAY |
  79400                           SOC_REG_FLAG_RO |
  79401                           SOC_REG_FLAG_REG_ARRAY,
  79402         SOC_REG_FLAG_COUNTER_FEILDS,
  79403         1,
  79404         soc_BRDC_LCM_DTL_LCLRT_DROPPED_SRC_P_CNTr_fields,
  79405         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79406         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79407         -1,
  79408         -1,
  79409     },
  79410 #endif /* chips */
  79411 
  79412 #if defined(BCM_88790_A0)
  79413     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_LINK_TYPEr */
  79414         soc_block_list[109],
  79415         soc_genreg,
  79416         1,
  79417         0,
  79418         0x21a,
  79419         0,
  79420         0,
  79421         1,
  79422         soc_BRDC_LCM_DTL_LCLRT_LINK_TYPEr_fields,
  79423         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79424         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  79425         -1,
  79426         -1,
  79427     },
  79428 #endif /* chips */
  79429 
  79430 #if defined(BCM_88790_A0)
  79431     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_TOTAL_IN_CELL_P_CNTr */
  79432         soc_block_list[109],
  79433         soc_genreg,
  79434         3,
  79435         0,
  79436         0x369,
  79437         SOC_REG_FLAG_ARRAY |
  79438                           SOC_REG_FLAG_RO |
  79439                           SOC_REG_FLAG_REG_ARRAY,
  79440         SOC_REG_FLAG_COUNTER_FEILDS,
  79441         1,
  79442         soc_BRDC_LCM_DTL_LCLRT_TOTAL_IN_CELL_P_CNTr_fields,
  79443         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79444         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79445         -1,
  79446         -1,
  79447     },
  79448 #endif /* chips */
  79449 
  79450 #if defined(BCM_88790_A0)
  79451     { /* SOC_REG_INT_BRDC_LCM_DTL_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr */
  79452         soc_block_list[109],
  79453         soc_genreg,
  79454         1,
  79455         0,
  79456         0x22e,
  79457         0,
  79458         0,
  79459         2,
  79460         soc_BRDC_LCM_DTL_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  79461         SOC_RESET_VAL_DEC(0x04001000, 0x00000000)
  79462         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  79463         -1,
  79464         -1,
  79465     },
  79466 #endif /* chips */
  79467 
  79468 #if defined(BCM_88790_A0)
  79469     { /* SOC_REG_INT_BRDC_LCM_DTL_LINK_TYPEr */
  79470         soc_block_list[109],
  79471         soc_genreg,
  79472         1,
  79473         0,
  79474         0x215,
  79475         0,
  79476         0,
  79477         1,
  79478         soc_BRDC_LCM_DTL_LINK_TYPEr_fields,
  79479         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79480         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  79481         -1,
  79482         -1,
  79483     },
  79484 #endif /* chips */
  79485 
  79486 #if defined(BCM_88790_A0)
  79487     { /* SOC_REG_INT_BRDC_LCM_DTL_PIPES_WEIGHTS_REGISTERr */
  79488         soc_block_list[109],
  79489         soc_genreg,
  79490         1,
  79491         0,
  79492         0x34d,
  79493         0,
  79494         0,
  79495         7,
  79496         soc_BRDC_LCM_DTL_PIPES_WEIGHTS_REGISTERr_fields,
  79497         SOC_RESET_VAL_DEC(0x18010101, 0x00000000)
  79498         SOC_RESET_MASK_DEC(0x3f7f7f7f, 0x00000000)
  79499         -1,
  79500         -1,
  79501     },
  79502 #endif /* chips */
  79503 
  79504 #if defined(BCM_88790_A0)
  79505     { /* SOC_REG_INT_BRDC_LCM_DTL_RCI_TH_P_0_LR_PROFILEr */
  79506         soc_block_list[109],
  79507         soc_genreg,
  79508         2,
  79509         0,
  79510         0x1bc,
  79511         SOC_REG_FLAG_ABOVE_64_BITS |
  79512                           SOC_REG_FLAG_ARRAY |
  79513                           SOC_REG_FLAG_REG_ARRAY,
  79514         0,
  79515         6,
  79516         soc_BRDC_LCM_DTL_RCI_TH_P_0_LR_PROFILEr_fields,
  79517         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79518         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79519         -1,
  79520         -1,
  79521     },
  79522 #endif /* chips */
  79523 
  79524 #if defined(BCM_88790_A0)
  79525     { /* SOC_REG_INT_BRDC_LCM_DTL_RCI_TH_P_0_NLR_PROFILEr */
  79526         soc_block_list[109],
  79527         soc_genreg,
  79528         2,
  79529         0,
  79530         0x1aa,
  79531         SOC_REG_FLAG_ABOVE_64_BITS |
  79532                           SOC_REG_FLAG_ARRAY |
  79533                           SOC_REG_FLAG_REG_ARRAY,
  79534         0,
  79535         6,
  79536         soc_BRDC_LCM_DTL_RCI_TH_P_0_NLR_PROFILEr_fields,
  79537         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79538         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79539         -1,
  79540         -1,
  79541     },
  79542 #endif /* chips */
  79543 
  79544 #if defined(BCM_88790_A0)
  79545     { /* SOC_REG_INT_BRDC_LCM_DTL_RCI_TH_P_1_LR_PROFILEr */
  79546         soc_block_list[109],
  79547         soc_genreg,
  79548         2,
  79549         0,
  79550         0x1c2,
  79551         SOC_REG_FLAG_ABOVE_64_BITS |
  79552                           SOC_REG_FLAG_ARRAY |
  79553                           SOC_REG_FLAG_REG_ARRAY,
  79554         0,
  79555         6,
  79556         soc_BRDC_LCM_DTL_RCI_TH_P_1_LR_PROFILEr_fields,
  79557         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79558         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79559         -1,
  79560         -1,
  79561     },
  79562 #endif /* chips */
  79563 
  79564 #if defined(BCM_88790_A0)
  79565     { /* SOC_REG_INT_BRDC_LCM_DTL_RCI_TH_P_1_NLR_PROFILEr */
  79566         soc_block_list[109],
  79567         soc_genreg,
  79568         2,
  79569         0,
  79570         0x1b0,
  79571         SOC_REG_FLAG_ABOVE_64_BITS |
  79572                           SOC_REG_FLAG_ARRAY |
  79573                           SOC_REG_FLAG_REG_ARRAY,
  79574         0,
  79575         6,
  79576         soc_BRDC_LCM_DTL_RCI_TH_P_1_NLR_PROFILEr_fields,
  79577         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79578         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79579         -1,
  79580         -1,
  79581     },
  79582 #endif /* chips */
  79583 
  79584 #if defined(BCM_88790_A0)
  79585     { /* SOC_REG_INT_BRDC_LCM_DTL_RCI_TH_P_2_LR_PROFILEr */
  79586         soc_block_list[109],
  79587         soc_genreg,
  79588         2,
  79589         0,
  79590         0x1c8,
  79591         SOC_REG_FLAG_ABOVE_64_BITS |
  79592                           SOC_REG_FLAG_ARRAY |
  79593                           SOC_REG_FLAG_REG_ARRAY,
  79594         0,
  79595         6,
  79596         soc_BRDC_LCM_DTL_RCI_TH_P_2_LR_PROFILEr_fields,
  79597         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79598         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79599         -1,
  79600         -1,
  79601     },
  79602 #endif /* chips */
  79603 
  79604 #if defined(BCM_88790_A0)
  79605     { /* SOC_REG_INT_BRDC_LCM_DTL_RCI_TH_P_2_NLR_PROFILEr */
  79606         soc_block_list[109],
  79607         soc_genreg,
  79608         2,
  79609         0,
  79610         0x1b6,
  79611         SOC_REG_FLAG_ABOVE_64_BITS |
  79612                           SOC_REG_FLAG_ARRAY |
  79613                           SOC_REG_FLAG_REG_ARRAY,
  79614         0,
  79615         6,
  79616         soc_BRDC_LCM_DTL_RCI_TH_P_2_NLR_PROFILEr_fields,
  79617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79618         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79619         -1,
  79620         -1,
  79621     },
  79622 #endif /* chips */
  79623 
  79624 #if defined(BCM_88790_A0)
  79625     { /* SOC_REG_INT_BRDC_LCM_DTL_TH_PROFILES_MAPPINGr */
  79626         soc_block_list[109],
  79627         soc_genreg,
  79628         1,
  79629         0,
  79630         0x1da,
  79631         0,
  79632         0,
  79633         1,
  79634         soc_BRDC_LCM_DTL_TH_PROFILES_MAPPINGr_fields,
  79635         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79636         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  79637         -1,
  79638         -1,
  79639     },
  79640 #endif /* chips */
  79641 
  79642 #if defined(BCM_88790_A0)
  79643     { /* SOC_REG_INT_BRDC_LCM_DTL_TOTAL_IN_CELL_P_CNTr */
  79644         soc_block_list[109],
  79645         soc_genreg,
  79646         3,
  79647         0,
  79648         0x357,
  79649         SOC_REG_FLAG_ARRAY |
  79650                           SOC_REG_FLAG_RO |
  79651                           SOC_REG_FLAG_REG_ARRAY,
  79652         SOC_REG_FLAG_COUNTER_FEILDS,
  79653         1,
  79654         soc_BRDC_LCM_DTL_TOTAL_IN_CELL_P_CNTr_fields,
  79655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79656         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79657         -1,
  79658         -1,
  79659     },
  79660 #endif /* chips */
  79661 
  79662 #if defined(BCM_88790_A0)
  79663     { /* SOC_REG_INT_BRDC_LCM_DTL_WFQ_DYN_WEIGHT_THD_REGISTERr */
  79664         soc_block_list[109],
  79665         soc_genreg,
  79666         1,
  79667         0,
  79668         0x22d,
  79669         0,
  79670         0,
  79671         2,
  79672         soc_BRDC_LCM_DTL_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  79673         SOC_RESET_VAL_DEC(0x04001000, 0x00000000)
  79674         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  79675         -1,
  79676         -1,
  79677     },
  79678 #endif /* chips */
  79679 
  79680 #if defined(BCM_88790_A0)
  79681     { /* SOC_REG_INT_BRDC_LCM_DTMLOP_PIPES_WEIGHTS_COUNTER_PNr */
  79682         soc_block_list[109],
  79683         soc_genreg,
  79684         3,
  79685         0,
  79686         0x350,
  79687         SOC_REG_FLAG_ARRAY |
  79688                           SOC_REG_FLAG_RO |
  79689                           SOC_REG_FLAG_REG_ARRAY,
  79690         0,
  79691         1,
  79692         soc_BRDC_LCM_DTMLOP_PIPES_WEIGHTS_COUNTER_PNr_fields,
  79693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79694         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  79695         -1,
  79696         -1,
  79697     },
  79698 #endif /* chips */
  79699 
  79700 #if defined(BCM_88790_A0)
  79701     { /* SOC_REG_INT_BRDC_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_2r */
  79702         soc_block_list[109],
  79703         soc_genreg,
  79704         1,
  79705         0,
  79706         0x34e,
  79707         0,
  79708         0,
  79709         1,
  79710         soc_BRDC_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_2r_fields,
  79711         SOC_RESET_VAL_DEC(0x03ffffff, 0x00000000)
  79712         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  79713         -1,
  79714         -1,
  79715     },
  79716 #endif /* chips */
  79717 
  79718 #if defined(BCM_88790_A0)
  79719     { /* SOC_REG_INT_BRDC_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_3r */
  79720         soc_block_list[109],
  79721         soc_genreg,
  79722         1,
  79723         0,
  79724         0x34f,
  79725         0,
  79726         0,
  79727         1,
  79728         soc_BRDC_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_3r_fields,
  79729         SOC_RESET_VAL_DEC(0x007fffff, 0x00000000)
  79730         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  79731         -1,
  79732         -1,
  79733     },
  79734 #endif /* chips */
  79735 
  79736 #if defined(BCM_88790_A0)
  79737     { /* SOC_REG_INT_BRDC_LCM_DTML_ENABLERSr */
  79738         soc_block_list[109],
  79739         soc_genreg,
  79740         1,
  79741         0,
  79742         0x306,
  79743         0,
  79744         0,
  79745         8,
  79746         soc_BRDC_LCM_DTML_ENABLERSr_fields,
  79747         SOC_RESET_VAL_DEC(0x00100004, 0x00000000)
  79748         SOC_RESET_MASK_DEC(0x01f7fff7, 0x00000000)
  79749         -1,
  79750         -1,
  79751     },
  79752 #endif /* chips */
  79753 
  79754 #if defined(BCM_88790_A0)
  79755     { /* SOC_REG_INT_BRDC_LCM_DTM_ADMIT_CYCLE_TH_PROFILEr */
  79756         soc_block_list[109],
  79757         soc_genreg,
  79758         2,
  79759         0,
  79760         0x138,
  79761         SOC_REG_FLAG_64_BITS |
  79762                           SOC_REG_FLAG_ARRAY |
  79763                           SOC_REG_FLAG_REG_ARRAY,
  79764         0,
  79765         4,
  79766         soc_BRDC_LCM_DTM_ADMIT_CYCLE_TH_PROFILEr_fields,
  79767         SOC_RESET_VAL_DEC(0x24004800, 0x09001200)
  79768         SOC_RESET_MASK_DEC(0xffffffff, 0x0fffffff)
  79769         -1,
  79770         -1,
  79771     },
  79772 #endif /* chips */
  79773 
  79774 #if defined(BCM_88790_A0)
  79775     { /* SOC_REG_INT_BRDC_LCM_DTM_ADMIT_JOB_FIFO_CYCLE_THr */
  79776         soc_block_list[109],
  79777         soc_genreg,
  79778         1,
  79779         0,
  79780         0x164,
  79781         SOC_REG_FLAG_ABOVE_64_BITS,
  79782         0,
  79783         4,
  79784         soc_BRDC_LCM_DTM_ADMIT_JOB_FIFO_CYCLE_THr_fields,
  79785         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79786         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79787         -1,
  79788         -1,
  79789     },
  79790 #endif /* chips */
  79791 
  79792 #if defined(BCM_88790_A0)
  79793     { /* SOC_REG_INT_BRDC_LCM_DTM_ADMIT_TH_PROFILEr */
  79794         soc_block_list[109],
  79795         soc_genreg,
  79796         2,
  79797         0,
  79798         0x12a,
  79799         SOC_REG_FLAG_ABOVE_64_BITS |
  79800                           SOC_REG_FLAG_ARRAY |
  79801                           SOC_REG_FLAG_REG_ARRAY,
  79802         0,
  79803         16,
  79804         soc_BRDC_LCM_DTM_ADMIT_TH_PROFILEr_fields,
  79805         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79806         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79807         -1,
  79808         -1,
  79809     },
  79810 #endif /* chips */
  79811 
  79812 #if defined(BCM_88790_A0)
  79813     { /* SOC_REG_INT_BRDC_LCM_DTM_CNT_INFO_1r */
  79814         soc_block_list[109],
  79815         soc_genreg,
  79816         1,
  79817         0,
  79818         0x275,
  79819         SOC_REG_FLAG_64_BITS |
  79820                           SOC_REG_FLAG_RO,
  79821         0,
  79822         2,
  79823         soc_BRDC_LCM_DTM_CNT_INFO_1r_fields,
  79824         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79825         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  79826         -1,
  79827         -1,
  79828     },
  79829 #endif /* chips */
  79830 
  79831 #if defined(BCM_88790_A0)
  79832     { /* SOC_REG_INT_BRDC_LCM_DTM_CNT_INFO_2r */
  79833         soc_block_list[109],
  79834         soc_genreg,
  79835         1,
  79836         0,
  79837         0x277,
  79838         SOC_REG_FLAG_RO,
  79839         0,
  79840         2,
  79841         soc_BRDC_LCM_DTM_CNT_INFO_2r_fields,
  79842         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79843         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  79844         -1,
  79845         -1,
  79846     },
  79847 #endif /* chips */
  79848 
  79849 #if defined(BCM_88790_A0)
  79850     { /* SOC_REG_INT_BRDC_LCM_DTM_CNT_INFO_3r */
  79851         soc_block_list[109],
  79852         soc_genreg,
  79853         1,
  79854         0,
  79855         0x278,
  79856         SOC_REG_FLAG_64_BITS |
  79857                           SOC_REG_FLAG_RO,
  79858         0,
  79859         2,
  79860         soc_BRDC_LCM_DTM_CNT_INFO_3r_fields,
  79861         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79862         SOC_RESET_MASK_DEC(0xffffffff, 0x0000000f)
  79863         -1,
  79864         -1,
  79865     },
  79866 #endif /* chips */
  79867 
  79868 #if defined(BCM_88790_A0)
  79869     { /* SOC_REG_INT_BRDC_LCM_DTM_CNT_INFO_SELECTr */
  79870         soc_block_list[109],
  79871         soc_genreg,
  79872         1,
  79873         0,
  79874         0x274,
  79875         0,
  79876         0,
  79877         3,
  79878         soc_BRDC_LCM_DTM_CNT_INFO_SELECTr_fields,
  79879         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79880         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  79881         -1,
  79882         -1,
  79883     },
  79884 #endif /* chips */
  79885 
  79886 #if defined(BCM_88790_A0)
  79887     { /* SOC_REG_INT_BRDC_LCM_DTM_COPIES_RTP_FC_THRESHOLDSr */
  79888         soc_block_list[109],
  79889         soc_genreg,
  79890         1,
  79891         0,
  79892         0x167,
  79893         SOC_REG_FLAG_ABOVE_64_BITS,
  79894         0,
  79895         4,
  79896         soc_BRDC_LCM_DTM_COPIES_RTP_FC_THRESHOLDSr_fields,
  79897         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79898         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79899         -1,
  79900         -1,
  79901     },
  79902 #endif /* chips */
  79903 
  79904 #if defined(BCM_88790_A0)
  79905     { /* SOC_REG_INT_BRDC_LCM_DTM_CPU_TAGS_STATUSr */
  79906         soc_block_list[109],
  79907         soc_genreg,
  79908         1,
  79909         0,
  79910         0x289,
  79911         SOC_REG_FLAG_RO,
  79912         0,
  79913         1,
  79914         soc_BRDC_LCM_DTM_CPU_TAGS_STATUSr_fields,
  79915         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79916         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79917         -1,
  79918         -1,
  79919     },
  79920 #endif /* chips */
  79921 
  79922 #if defined(BCM_88790_A0)
  79923     { /* SOC_REG_INT_BRDC_LCM_DTM_CPU_TAGS_THr */
  79924         soc_block_list[109],
  79925         soc_genreg,
  79926         1,
  79927         0,
  79928         0x20d,
  79929         0,
  79930         0,
  79931         1,
  79932         soc_BRDC_LCM_DTM_CPU_TAGS_THr_fields,
  79933         SOC_RESET_VAL_DEC(0x00000078, 0x00000000)
  79934         SOC_RESET_MASK_DEC(0x000003ff, 0x00000000)
  79935         -1,
  79936         -1,
  79937     },
  79938 #endif /* chips */
  79939 
  79940 #if defined(BCM_88790_A0)
  79941     { /* SOC_REG_INT_BRDC_LCM_DTM_DTL_FLOW_CONTROL_CNT_Pr */
  79942         soc_block_list[109],
  79943         soc_genreg,
  79944         3,
  79945         0,
  79946         0x33f,
  79947         SOC_REG_FLAG_ARRAY |
  79948                           SOC_REG_FLAG_RO |
  79949                           SOC_REG_FLAG_REG_ARRAY,
  79950         SOC_REG_FLAG_COUNTER_FEILDS,
  79951         1,
  79952         soc_BRDC_LCM_DTM_DTL_FLOW_CONTROL_CNT_Pr_fields,
  79953         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79954         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  79955         -1,
  79956         -1,
  79957     },
  79958 #endif /* chips */
  79959 
  79960 #if defined(BCM_88790_A0)
  79961     { /* SOC_REG_INT_BRDC_LCM_DTM_DYN_PIPES_WEIGHTS_REGISTERr */
  79962         soc_block_list[109],
  79963         soc_genreg,
  79964         1,
  79965         0,
  79966         0x314,
  79967         0,
  79968         0,
  79969         4,
  79970         soc_BRDC_LCM_DTM_DYN_PIPES_WEIGHTS_REGISTERr_fields,
  79971         SOC_RESET_VAL_DEC(0x01010101, 0x00000000)
  79972         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  79973         -1,
  79974         -1,
  79975     },
  79976 #endif /* chips */
  79977 
  79978 #if defined(BCM_88790_A0)
  79979     { /* SOC_REG_INT_BRDC_LCM_DTM_FC_TH_PROFILEr */
  79980         soc_block_list[109],
  79981         soc_genreg,
  79982         2,
  79983         0,
  79984         0x15c,
  79985         SOC_REG_FLAG_ABOVE_64_BITS |
  79986                           SOC_REG_FLAG_ARRAY |
  79987                           SOC_REG_FLAG_REG_ARRAY,
  79988         0,
  79989         9,
  79990         soc_BRDC_LCM_DTM_FC_TH_PROFILEr_fields,
  79991         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  79992         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  79993         -1,
  79994         -1,
  79995     },
  79996 #endif /* chips */
  79997 
  79998 #if defined(BCM_88790_A0)
  79999     { /* SOC_REG_INT_BRDC_LCM_DTM_FIFOS_DEPTH_TYPEr */
  80000         soc_block_list[109],
  80001         soc_genreg,
  80002         2,
  80003         0,
  80004         0x213,
  80005         SOC_REG_FLAG_ARRAY |
  80006                           SOC_REG_FLAG_REG_ARRAY,
  80007         0,
  80008         2,
  80009         soc_BRDC_LCM_DTM_FIFOS_DEPTH_TYPEr_fields,
  80010         SOC_RESET_VAL_DEC(0x06000600, 0x00000000)
  80011         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00000000)
  80012         -1,
  80013         -1,
  80014     },
  80015 #endif /* chips */
  80016 
  80017 #if defined(BCM_88790_A0)
  80018     { /* SOC_REG_INT_BRDC_LCM_DTM_FIFO_TYPE_BMPr */
  80019         soc_block_list[109],
  80020         soc_genreg,
  80021         1,
  80022         0,
  80023         0x212,
  80024         0,
  80025         0,
  80026         1,
  80027         soc_BRDC_LCM_DTM_FIFO_TYPE_BMPr_fields,
  80028         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80029         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  80030         -1,
  80031         -1,
  80032     },
  80033 #endif /* chips */
  80034 
  80035 #if defined(BCM_88790_A0)
  80036     { /* SOC_REG_INT_BRDC_LCM_DTM_FRAG_CNT_INFO_P_0_DCHr */
  80037         soc_block_list[109],
  80038         soc_genreg,
  80039         8,
  80040         0,
  80041         0x24c,
  80042         SOC_REG_FLAG_ARRAY |
  80043                           SOC_REG_FLAG_RO |
  80044                           SOC_REG_FLAG_REG_ARRAY,
  80045         0,
  80046         2,
  80047         soc_BRDC_LCM_DTM_FRAG_CNT_INFO_P_0_DCHr_fields,
  80048         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80049         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  80050         -1,
  80051         -1,
  80052     },
  80053 #endif /* chips */
  80054 
  80055 #if defined(BCM_88790_A0)
  80056     { /* SOC_REG_INT_BRDC_LCM_DTM_FRAG_CNT_INFO_P_1_DCHr */
  80057         soc_block_list[109],
  80058         soc_genreg,
  80059         8,
  80060         0,
  80061         0x25c,
  80062         SOC_REG_FLAG_ARRAY |
  80063                           SOC_REG_FLAG_RO |
  80064                           SOC_REG_FLAG_REG_ARRAY,
  80065         0,
  80066         2,
  80067         soc_BRDC_LCM_DTM_FRAG_CNT_INFO_P_1_DCHr_fields,
  80068         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80069         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  80070         -1,
  80071         -1,
  80072     },
  80073 #endif /* chips */
  80074 
  80075 #if defined(BCM_88790_A0)
  80076     { /* SOC_REG_INT_BRDC_LCM_DTM_FRAG_CNT_INFO_P_2_DCHr */
  80077         soc_block_list[109],
  80078         soc_genreg,
  80079         8,
  80080         0,
  80081         0x26c,
  80082         SOC_REG_FLAG_ARRAY |
  80083                           SOC_REG_FLAG_RO |
  80084                           SOC_REG_FLAG_REG_ARRAY,
  80085         0,
  80086         2,
  80087         soc_BRDC_LCM_DTM_FRAG_CNT_INFO_P_2_DCHr_fields,
  80088         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80089         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  80090         -1,
  80091         -1,
  80092     },
  80093 #endif /* chips */
  80094 
  80095 #if defined(BCM_88790_A0)
  80096     { /* SOC_REG_INT_BRDC_LCM_DTM_GCI_TH_PROFILEr */
  80097         soc_block_list[109],
  80098         soc_genreg,
  80099         2,
  80100         0,
  80101         0x13c,
  80102         SOC_REG_FLAG_ABOVE_64_BITS |
  80103                           SOC_REG_FLAG_ARRAY |
  80104                           SOC_REG_FLAG_REG_ARRAY,
  80105         0,
  80106         18,
  80107         soc_BRDC_LCM_DTM_GCI_TH_PROFILEr_fields,
  80108         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80109         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80110         -1,
  80111         -1,
  80112     },
  80113 #endif /* chips */
  80114 
  80115 #if defined(BCM_88790_A0)
  80116     { /* SOC_REG_INT_BRDC_LCM_DTM_LATENCY_CFGr */
  80117         soc_block_list[109],
  80118         soc_genreg,
  80119         3,
  80120         0,
  80121         0x308,
  80122         SOC_REG_FLAG_ARRAY |
  80123                           SOC_REG_FLAG_REG_ARRAY,
  80124         0,
  80125         1,
  80126         soc_BRDC_LCM_DTM_LATENCY_CFGr_fields,
  80127         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80128         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  80129         -1,
  80130         -1,
  80131     },
  80132 #endif /* chips */
  80133 
  80134 #if defined(BCM_88790_A0)
  80135     { /* SOC_REG_INT_BRDC_LCM_DTM_LCLRT_DTL_FLOW_CONTROL_CNT_Pr */
  80136         soc_block_list[109],
  80137         soc_genreg,
  80138         3,
  80139         0,
  80140         0x342,
  80141         SOC_REG_FLAG_ARRAY |
  80142                           SOC_REG_FLAG_RO |
  80143                           SOC_REG_FLAG_REG_ARRAY,
  80144         SOC_REG_FLAG_COUNTER_FEILDS,
  80145         1,
  80146         soc_BRDC_LCM_DTM_LCLRT_DTL_FLOW_CONTROL_CNT_Pr_fields,
  80147         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80148         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80149         -1,
  80150         -1,
  80151     },
  80152 #endif /* chips */
  80153 
  80154 #if defined(BCM_88790_A0)
  80155     { /* SOC_REG_INT_BRDC_LCM_DTM_LCLRT_PIPES_WEIGHTS_COUNTER_PNr */
  80156         soc_block_list[109],
  80157         soc_genreg,
  80158         3,
  80159         0,
  80160         0x311,
  80161         SOC_REG_FLAG_ARRAY |
  80162                           SOC_REG_FLAG_RO |
  80163                           SOC_REG_FLAG_REG_ARRAY,
  80164         0,
  80165         1,
  80166         soc_BRDC_LCM_DTM_LCLRT_PIPES_WEIGHTS_COUNTER_PNr_fields,
  80167         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80168         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  80169         -1,
  80170         -1,
  80171     },
  80172 #endif /* chips */
  80173 
  80174 #if defined(BCM_88790_A0)
  80175     { /* SOC_REG_INT_BRDC_LCM_DTM_LCLRT_TOTAL_OUT_CELL_CNT_Pr */
  80176         soc_block_list[109],
  80177         soc_genreg,
  80178         3,
  80179         0,
  80180         0x330,
  80181         SOC_REG_FLAG_ARRAY |
  80182                           SOC_REG_FLAG_RO |
  80183                           SOC_REG_FLAG_REG_ARRAY,
  80184         SOC_REG_FLAG_COUNTER_FEILDS,
  80185         1,
  80186         soc_BRDC_LCM_DTM_LCLRT_TOTAL_OUT_CELL_CNT_Pr_fields,
  80187         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80188         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80189         -1,
  80190         -1,
  80191     },
  80192 #endif /* chips */
  80193 
  80194 #if defined(BCM_88790_A0)
  80195     { /* SOC_REG_INT_BRDC_LCM_DTM_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr */
  80196         soc_block_list[109],
  80197         soc_genreg,
  80198         1,
  80199         0,
  80200         0x22c,
  80201         0,
  80202         0,
  80203         2,
  80204         soc_BRDC_LCM_DTM_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  80205         SOC_RESET_VAL_DEC(0x04801200, 0x00000000)
  80206         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  80207         -1,
  80208         -1,
  80209     },
  80210 #endif /* chips */
  80211 
  80212 #if defined(BCM_88790_A0)
  80213     { /* SOC_REG_INT_BRDC_LCM_DTM_MASK_FC_AGING_PERIODr */
  80214         soc_block_list[109],
  80215         soc_genreg,
  80216         1,
  80217         0,
  80218         0x345,
  80219         0,
  80220         0,
  80221         1,
  80222         soc_BRDC_LCM_DTM_MASK_FC_AGING_PERIODr_fields,
  80223         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80224         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80225         -1,
  80226         -1,
  80227     },
  80228 #endif /* chips */
  80229 
  80230 #if defined(BCM_88790_A0)
  80231     { /* SOC_REG_INT_BRDC_LCM_DTM_PIPES_WEIGHTS_COUNTER_PNr */
  80232         soc_block_list[109],
  80233         soc_genreg,
  80234         3,
  80235         0,
  80236         0x30e,
  80237         SOC_REG_FLAG_ARRAY |
  80238                           SOC_REG_FLAG_RO |
  80239                           SOC_REG_FLAG_REG_ARRAY,
  80240         0,
  80241         1,
  80242         soc_BRDC_LCM_DTM_PIPES_WEIGHTS_COUNTER_PNr_fields,
  80243         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80244         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  80245         -1,
  80246         -1,
  80247     },
  80248 #endif /* chips */
  80249 
  80250 #if defined(BCM_88790_A0)
  80251     { /* SOC_REG_INT_BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTERr */
  80252         soc_block_list[109],
  80253         soc_genreg,
  80254         1,
  80255         0,
  80256         0x30b,
  80257         0,
  80258         0,
  80259         8,
  80260         soc_BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTERr_fields,
  80261         SOC_RESET_VAL_DEC(0x18010101, 0x00000000)
  80262         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  80263         -1,
  80264         -1,
  80265     },
  80266 #endif /* chips */
  80267 
  80268 #if defined(BCM_88790_A0)
  80269     { /* SOC_REG_INT_BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTER_2r */
  80270         soc_block_list[109],
  80271         soc_genreg,
  80272         1,
  80273         0,
  80274         0x30c,
  80275         0,
  80276         0,
  80277         1,
  80278         soc_BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTER_2r_fields,
  80279         SOC_RESET_VAL_DEC(0x003fffff, 0x00000000)
  80280         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  80281         -1,
  80282         -1,
  80283     },
  80284 #endif /* chips */
  80285 
  80286 #if defined(BCM_88790_A0)
  80287     { /* SOC_REG_INT_BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTER_3r */
  80288         soc_block_list[109],
  80289         soc_genreg,
  80290         1,
  80291         0,
  80292         0x30d,
  80293         0,
  80294         0,
  80295         1,
  80296         soc_BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTER_3r_fields,
  80297         SOC_RESET_VAL_DEC(0x0007ffff, 0x00000000)
  80298         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  80299         -1,
  80300         -1,
  80301     },
  80302 #endif /* chips */
  80303 
  80304 #if defined(BCM_88790_A0)
  80305     { /* SOC_REG_INT_BRDC_LCM_DTM_RCI_TH_PROFILEr */
  80306         soc_block_list[109],
  80307         soc_genreg,
  80308         2,
  80309         0,
  80310         0x14c,
  80311         SOC_REG_FLAG_ABOVE_64_BITS |
  80312                           SOC_REG_FLAG_ARRAY |
  80313                           SOC_REG_FLAG_REG_ARRAY,
  80314         0,
  80315         18,
  80316         soc_BRDC_LCM_DTM_RCI_TH_PROFILEr_fields,
  80317         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80318         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  80319         -1,
  80320         -1,
  80321     },
  80322 #endif /* chips */
  80323 
  80324 #if defined(BCM_88790_A0)
  80325     { /* SOC_REG_INT_BRDC_LCM_DTM_TAG_CNT_INFO_P_0_DCHr */
  80326         soc_block_list[109],
  80327         soc_genreg,
  80328         8,
  80329         0,
  80330         0x244,
  80331         SOC_REG_FLAG_ARRAY |
  80332                           SOC_REG_FLAG_RO |
  80333                           SOC_REG_FLAG_REG_ARRAY,
  80334         0,
  80335         2,
  80336         soc_BRDC_LCM_DTM_TAG_CNT_INFO_P_0_DCHr_fields,
  80337         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80338         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  80339         -1,
  80340         -1,
  80341     },
  80342 #endif /* chips */
  80343 
  80344 #if defined(BCM_88790_A0)
  80345     { /* SOC_REG_INT_BRDC_LCM_DTM_TAG_CNT_INFO_P_1_DCHr */
  80346         soc_block_list[109],
  80347         soc_genreg,
  80348         8,
  80349         0,
  80350         0x254,
  80351         SOC_REG_FLAG_ARRAY |
  80352                           SOC_REG_FLAG_RO |
  80353                           SOC_REG_FLAG_REG_ARRAY,
  80354         0,
  80355         2,
  80356         soc_BRDC_LCM_DTM_TAG_CNT_INFO_P_1_DCHr_fields,
  80357         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80358         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  80359         -1,
  80360         -1,
  80361     },
  80362 #endif /* chips */
  80363 
  80364 #if defined(BCM_88790_A0)
  80365     { /* SOC_REG_INT_BRDC_LCM_DTM_TAG_CNT_INFO_P_2_DCHr */
  80366         soc_block_list[109],
  80367         soc_genreg,
  80368         8,
  80369         0,
  80370         0x264,
  80371         SOC_REG_FLAG_ARRAY |
  80372                           SOC_REG_FLAG_RO |
  80373                           SOC_REG_FLAG_REG_ARRAY,
  80374         0,
  80375         2,
  80376         soc_BRDC_LCM_DTM_TAG_CNT_INFO_P_2_DCHr_fields,
  80377         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80378         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  80379         -1,
  80380         -1,
  80381     },
  80382 #endif /* chips */
  80383 
  80384 #if defined(BCM_88790_A0)
  80385     { /* SOC_REG_INT_BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_0r */
  80386         soc_block_list[109],
  80387         soc_genreg,
  80388         8,
  80389         0,
  80390         0x315,
  80391         SOC_REG_FLAG_ARRAY |
  80392                           SOC_REG_FLAG_RO |
  80393                           SOC_REG_FLAG_REG_ARRAY,
  80394         SOC_REG_FLAG_COUNTER_FEILDS,
  80395         1,
  80396         soc_BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_0r_fields,
  80397         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80398         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80399         -1,
  80400         -1,
  80401     },
  80402 #endif /* chips */
  80403 
  80404 #if defined(BCM_88790_A0)
  80405     { /* SOC_REG_INT_BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_1r */
  80406         soc_block_list[109],
  80407         soc_genreg,
  80408         8,
  80409         0,
  80410         0x31d,
  80411         SOC_REG_FLAG_ARRAY |
  80412                           SOC_REG_FLAG_RO |
  80413                           SOC_REG_FLAG_REG_ARRAY,
  80414         SOC_REG_FLAG_COUNTER_FEILDS,
  80415         1,
  80416         soc_BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_1r_fields,
  80417         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80418         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80419         -1,
  80420         -1,
  80421     },
  80422 #endif /* chips */
  80423 
  80424 #if defined(BCM_88790_A0)
  80425     { /* SOC_REG_INT_BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_2r */
  80426         soc_block_list[109],
  80427         soc_genreg,
  80428         8,
  80429         0,
  80430         0x325,
  80431         SOC_REG_FLAG_ARRAY |
  80432                           SOC_REG_FLAG_RO |
  80433                           SOC_REG_FLAG_REG_ARRAY,
  80434         SOC_REG_FLAG_COUNTER_FEILDS,
  80435         1,
  80436         soc_BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_2r_fields,
  80437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80438         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80439         -1,
  80440         -1,
  80441     },
  80442 #endif /* chips */
  80443 
  80444 #if defined(BCM_88790_A0)
  80445     { /* SOC_REG_INT_BRDC_LCM_DTM_TOTAL_OUT_CELL_CNT_Pr */
  80446         soc_block_list[109],
  80447         soc_genreg,
  80448         3,
  80449         0,
  80450         0x32d,
  80451         SOC_REG_FLAG_ARRAY |
  80452                           SOC_REG_FLAG_RO |
  80453                           SOC_REG_FLAG_REG_ARRAY,
  80454         SOC_REG_FLAG_COUNTER_FEILDS,
  80455         1,
  80456         soc_BRDC_LCM_DTM_TOTAL_OUT_CELL_CNT_Pr_fields,
  80457         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80458         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80459         -1,
  80460         -1,
  80461     },
  80462 #endif /* chips */
  80463 
  80464 #if defined(BCM_88790_A0)
  80465     { /* SOC_REG_INT_BRDC_LCM_DTM_WFQ_DYN_WEIGHT_THD_REGISTERr */
  80466         soc_block_list[109],
  80467         soc_genreg,
  80468         1,
  80469         0,
  80470         0x22b,
  80471         0,
  80472         0,
  80473         2,
  80474         soc_BRDC_LCM_DTM_WFQ_DYN_WEIGHT_THD_REGISTERr_fields,
  80475         SOC_RESET_VAL_DEC(0x04801200, 0x00000000)
  80476         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  80477         -1,
  80478         -1,
  80479     },
  80480 #endif /* chips */
  80481 
  80482 #if defined(BCM_88790_A0)
  80483     { /* SOC_REG_INT_BRDC_LCM_DYN_PIPES_WEIGHTS_REGISTERr */
  80484         soc_block_list[109],
  80485         soc_genreg,
  80486         1,
  80487         0,
  80488         0x353,
  80489         0,
  80490         0,
  80491         4,
  80492         soc_BRDC_LCM_DYN_PIPES_WEIGHTS_REGISTERr_fields,
  80493         SOC_RESET_VAL_DEC(0x01010101, 0x00000000)
  80494         SOC_RESET_MASK_DEC(0x7f7f7f7f, 0x00000000)
  80495         -1,
  80496         -1,
  80497     },
  80498 #endif /* chips */
  80499 
  80500 #if defined(BCM_88790_A0)
  80501     { /* SOC_REG_INT_BRDC_LCM_ECC_1B_ERR_CNTr */
  80502         soc_block_list[109],
  80503         soc_genreg,
  80504         1,
  80505         0,
  80506         0x94,
  80507         SOC_REG_FLAG_64_BITS |
  80508                           SOC_REG_FLAG_RO,
  80509         SOC_REG_FLAG_COUNTER_FEILDS,
  80510         4,
  80511         soc_BRDC_LCM_ECC_1B_ERR_CNTr_fields,
  80512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80513         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  80514         -1,
  80515         -1,
  80516     },
  80517 #endif /* chips */
  80518 
  80519 #if defined(BCM_88790_A0)
  80520     { /* SOC_REG_INT_BRDC_LCM_ECC_2B_ERR_CNTr */
  80521         soc_block_list[109],
  80522         soc_genreg,
  80523         1,
  80524         0,
  80525         0x96,
  80526         SOC_REG_FLAG_64_BITS |
  80527                           SOC_REG_FLAG_RO,
  80528         SOC_REG_FLAG_COUNTER_FEILDS,
  80529         4,
  80530         soc_BRDC_LCM_ECC_2B_ERR_CNTr_fields,
  80531         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80532         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  80533         -1,
  80534         -1,
  80535     },
  80536 #endif /* chips */
  80537 
  80538 #if defined(BCM_88790_A0)
  80539     { /* SOC_REG_INT_BRDC_LCM_ECC_ERR_1B_INITIATEr */
  80540         soc_block_list[109],
  80541         soc_genreg,
  80542         1,
  80543         0,
  80544         0xa4,
  80545         0,
  80546         0,
  80547         5,
  80548         soc_BRDC_LCM_ECC_ERR_1B_INITIATEr_fields,
  80549         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80550         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  80551         -1,
  80552         -1,
  80553     },
  80554 #endif /* chips */
  80555 
  80556 #if defined(BCM_88790_A0)
  80557     { /* SOC_REG_INT_BRDC_LCM_ECC_ERR_1B_MONITOR_MEM_MASKr */
  80558         soc_block_list[109],
  80559         soc_genreg,
  80560         1,
  80561         0,
  80562         0x9a,
  80563         0,
  80564         0,
  80565         5,
  80566         soc_BRDC_LCM_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  80567         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80568         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  80569         -1,
  80570         -1,
  80571     },
  80572 #endif /* chips */
  80573 
  80574 #if defined(BCM_88790_A0)
  80575     { /* SOC_REG_INT_BRDC_LCM_ECC_ERR_2B_INITIATEr */
  80576         soc_block_list[109],
  80577         soc_genreg,
  80578         1,
  80579         0,
  80580         0xa6,
  80581         0,
  80582         0,
  80583         5,
  80584         soc_BRDC_LCM_ECC_ERR_2B_INITIATEr_fields,
  80585         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80586         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  80587         -1,
  80588         -1,
  80589     },
  80590 #endif /* chips */
  80591 
  80592 #if defined(BCM_88790_A0)
  80593     { /* SOC_REG_INT_BRDC_LCM_ECC_ERR_2B_MONITOR_MEM_MASKr */
  80594         soc_block_list[109],
  80595         soc_genreg,
  80596         1,
  80597         0,
  80598         0x9c,
  80599         0,
  80600         0,
  80601         5,
  80602         soc_BRDC_LCM_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  80603         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80604         SOC_RESET_MASK_DEC(0x00382080, 0x00000000)
  80605         -1,
  80606         -1,
  80607     },
  80608 #endif /* chips */
  80609 
  80610 #if defined(BCM_88790_A0)
  80611     { /* SOC_REG_INT_BRDC_LCM_ECC_INTERRUPT_REGISTERr */
  80612         soc_block_list[109],
  80613         soc_genreg,
  80614         1,
  80615         0,
  80616         0x7,
  80617         SOC_REG_FLAG_INTERRUPT |
  80618                           SOC_REG_FLAG_SIGNAL,
  80619         0,
  80620         3,
  80621         soc_BRDC_LCM_ECC_INTERRUPT_REGISTERr_fields,
  80622         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80623         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  80624         -1,
  80625         -1,
  80626     },
  80627 #endif /* chips */
  80628 
  80629 #if defined(BCM_88790_A0)
  80630     { /* SOC_REG_INT_BRDC_LCM_ECC_INTERRUPT_REGISTER_MASKr */
  80631         soc_block_list[109],
  80632         soc_genreg,
  80633         1,
  80634         0,
  80635         0x17,
  80636         0,
  80637         0,
  80638         3,
  80639         soc_BRDC_LCM_ECC_INTERRUPT_REGISTER_MASKr_fields,
  80640         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80641         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  80642         -1,
  80643         -1,
  80644     },
  80645 #endif /* chips */
  80646 
  80647 #if defined(BCM_88790_A0)
  80648     { /* SOC_REG_INT_BRDC_LCM_ECC_INTERRUPT_REGISTER_TESTr */
  80649         soc_block_list[109],
  80650         soc_genreg,
  80651         1,
  80652         0,
  80653         0x1f,
  80654         0,
  80655         0,
  80656         1,
  80657         soc_BRDC_LCM_ECC_INTERRUPT_REGISTER_TESTr_fields,
  80658         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80659         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  80660         -1,
  80661         -1,
  80662     },
  80663 #endif /* chips */
  80664 
  80665 #if defined(BCM_88790_A0)
  80666     { /* SOC_REG_INT_BRDC_LCM_ERROR_INITIATION_DATAr */
  80667         soc_block_list[109],
  80668         soc_genreg,
  80669         1,
  80670         0,
  80671         0xa3,
  80672         0,
  80673         0,
  80674         1,
  80675         soc_BRDC_LCM_ERROR_INITIATION_DATAr_fields,
  80676         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80677         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  80678         -1,
  80679         -1,
  80680     },
  80681 #endif /* chips */
  80682 
  80683 #if defined(BCM_88790_A0)
  80684     { /* SOC_REG_INT_BRDC_LCM_FAP_GLOBAL_GENERAL_CFG_1r */
  80685         soc_block_list[109],
  80686         soc_genreg,
  80687         1,
  80688         0,
  80689         0xc3,
  80690         0,
  80691         0,
  80692         2,
  80693         soc_BRDC_LCM_FAP_GLOBAL_GENERAL_CFG_1r_fields,
  80694         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  80695         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  80696         -1,
  80697         -1,
  80698     },
  80699 #endif /* chips */
  80700 
  80701 #if defined(BCM_88790_A0)
  80702     { /* SOC_REG_INT_BRDC_LCM_FE_GLOBAL_DCH_CAPTURE_CELLS_DCMLr */
  80703         soc_block_list[109],
  80704         soc_genreg,
  80705         1,
  80706         0,
  80707         0xf5,
  80708         0,
  80709         0,
  80710         8,
  80711         soc_BRDC_LCM_FE_GLOBAL_DCH_CAPTURE_CELLS_DCMLr_fields,
  80712         SOC_RESET_VAL_DEC(0x00fac688, 0x00000000)
  80713         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  80714         -1,
  80715         -1,
  80716     },
  80717 #endif /* chips */
  80718 
  80719 #if defined(BCM_88790_A0)
  80720     { /* SOC_REG_INT_BRDC_LCM_FE_GLOBAL_GENERAL_CFG_1r */
  80721         soc_block_list[109],
  80722         soc_genreg,
  80723         1,
  80724         0,
  80725         0xf4,
  80726         0,
  80727         0,
  80728         4,
  80729         soc_BRDC_LCM_FE_GLOBAL_GENERAL_CFG_1r_fields,
  80730         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  80731         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  80732         -1,
  80733         -1,
  80734     },
  80735 #endif /* chips */
  80736 
  80737 #if defined(BCM_88790_A0)
  80738     { /* SOC_REG_INT_BRDC_LCM_GLOBAL_MEM_OPTIONSr */
  80739         soc_block_list[109],
  80740         soc_genreg,
  80741         1,
  80742         0,
  80743         0xc2,
  80744         0,
  80745         0,
  80746         6,
  80747         soc_BRDC_LCM_GLOBAL_MEM_OPTIONSr_fields,
  80748         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  80749         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  80750         -1,
  80751         -1,
  80752     },
  80753 #endif /* chips */
  80754 
  80755 #if defined(BCM_88790_A0)
  80756     { /* SOC_REG_INT_BRDC_LCM_GTIMER_CONFIGURATIONr */
  80757         soc_block_list[109],
  80758         soc_genreg,
  80759         1,
  80760         0,
  80761         0x89,
  80762         0,
  80763         0,
  80764         3,
  80765         soc_BRDC_LCM_GTIMER_CONFIGURATIONr_fields,
  80766         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80767         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  80768         -1,
  80769         -1,
  80770     },
  80771 #endif /* chips */
  80772 
  80773 #if defined(BCM_88790_A0)
  80774     { /* SOC_REG_INT_BRDC_LCM_GTIMER_CYCLEr */
  80775         soc_block_list[109],
  80776         soc_genreg,
  80777         1,
  80778         0,
  80779         0x88,
  80780         0,
  80781         0,
  80782         1,
  80783         soc_BRDC_LCM_GTIMER_CYCLEr_fields,
  80784         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  80785         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  80786         -1,
  80787         -1,
  80788     },
  80789 #endif /* chips */
  80790 
  80791 #if defined(BCM_88790_A0)
  80792     { /* SOC_REG_INT_BRDC_LCM_INTERRUPT_MASK_REGISTERr */
  80793         soc_block_list[109],
  80794         soc_genreg,
  80795         1,
  80796         0,
  80797         0x10,
  80798         0,
  80799         0,
  80800         5,
  80801         soc_BRDC_LCM_INTERRUPT_MASK_REGISTERr_fields,
  80802         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80803         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  80804         -1,
  80805         -1,
  80806     },
  80807 #endif /* chips */
  80808 
  80809 #if defined(BCM_88790_A0)
  80810     { /* SOC_REG_INT_BRDC_LCM_INTERRUPT_REGISTERr */
  80811         soc_block_list[109],
  80812         soc_genreg,
  80813         1,
  80814         0,
  80815         0,
  80816         SOC_REG_FLAG_INTERRUPT |
  80817                           SOC_REG_FLAG_SIGNAL,
  80818         0,
  80819         5,
  80820         soc_BRDC_LCM_INTERRUPT_REGISTERr_fields,
  80821         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80822         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  80823         -1,
  80824         -1,
  80825     },
  80826 #endif /* chips */
  80827 
  80828 #if defined(BCM_88790_A0)
  80829     { /* SOC_REG_INT_BRDC_LCM_INTERRUPT_REGISTER_TESTr */
  80830         soc_block_list[109],
  80831         soc_genreg,
  80832         1,
  80833         0,
  80834         0x18,
  80835         0,
  80836         0,
  80837         1,
  80838         soc_BRDC_LCM_INTERRUPT_REGISTER_TESTr_fields,
  80839         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80840         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  80841         -1,
  80842         -1,
  80843     },
  80844 #endif /* chips */
  80845 
  80846 #if defined(BCM_88790_A0)
  80847     { /* SOC_REG_INT_BRDC_LCM_LCLRT_FIFOS_DEPTH_TYPEr */
  80848         soc_block_list[109],
  80849         soc_genreg,
  80850         2,
  80851         0,
  80852         0x21b,
  80853         SOC_REG_FLAG_64_BITS |
  80854                           SOC_REG_FLAG_ARRAY |
  80855                           SOC_REG_FLAG_REG_ARRAY,
  80856         0,
  80857         3,
  80858         soc_BRDC_LCM_LCLRT_FIFOS_DEPTH_TYPEr_fields,
  80859         SOC_RESET_VAL_DEC(0xa82a82a8, 0x00000002)
  80860         SOC_RESET_MASK_DEC(0xff7ff7ff, 0x00000007)
  80861         -1,
  80862         -1,
  80863     },
  80864 #endif /* chips */
  80865 
  80866 #if defined(BCM_88790_A0)
  80867     { /* SOC_REG_INT_BRDC_LCM_LCM_ADMIT_ENABLERSr */
  80868         soc_block_list[109],
  80869         soc_genreg,
  80870         1,
  80871         0,
  80872         0x106,
  80873         0,
  80874         0,
  80875         4,
  80876         soc_BRDC_LCM_LCM_ADMIT_ENABLERSr_fields,
  80877         SOC_RESET_VAL_DEC(0x0000000f, 0x00000000)
  80878         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  80879         -1,
  80880         -1,
  80881     },
  80882 #endif /* chips */
  80883 
  80884 #if defined(BCM_88790_A0)
  80885     { /* SOC_REG_INT_BRDC_LCM_LCM_FC_ENABLERSr */
  80886         soc_block_list[109],
  80887         soc_genreg,
  80888         1,
  80889         0,
  80890         0x10a,
  80891         0,
  80892         0,
  80893         6,
  80894         soc_BRDC_LCM_LCM_FC_ENABLERSr_fields,
  80895         SOC_RESET_VAL_DEC(0x00003ff7, 0x00000000)
  80896         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  80897         -1,
  80898         -1,
  80899     },
  80900 #endif /* chips */
  80901 
  80902 #if defined(BCM_88790_A0)
  80903     { /* SOC_REG_INT_BRDC_LCM_LCM_GCI_ENABLERSr */
  80904         soc_block_list[109],
  80905         soc_genreg,
  80906         1,
  80907         0,
  80908         0x107,
  80909         0,
  80910         0,
  80911         3,
  80912         soc_BRDC_LCM_LCM_GCI_ENABLERSr_fields,
  80913         SOC_RESET_VAL_DEC(0x07ffffff, 0x00000000)
  80914         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  80915         -1,
  80916         -1,
  80917     },
  80918 #endif /* chips */
  80919 
  80920 #if defined(BCM_88790_A0)
  80921     { /* SOC_REG_INT_BRDC_LCM_LCM_INTERRUPT_REGISTERr */
  80922         soc_block_list[109],
  80923         soc_genreg,
  80924         1,
  80925         0,
  80926         0x100,
  80927         SOC_REG_FLAG_INTERRUPT |
  80928                           SOC_REG_FLAG_SIGNAL,
  80929         0,
  80930         5,
  80931         soc_BRDC_LCM_LCM_INTERRUPT_REGISTERr_fields,
  80932         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80933         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  80934         -1,
  80935         -1,
  80936     },
  80937 #endif /* chips */
  80938 
  80939 #if defined(BCM_88790_A0)
  80940     { /* SOC_REG_INT_BRDC_LCM_LCM_INTERRUPT_REGISTER_MASKr */
  80941         soc_block_list[109],
  80942         soc_genreg,
  80943         1,
  80944         0,
  80945         0x101,
  80946         0,
  80947         0,
  80948         5,
  80949         soc_BRDC_LCM_LCM_INTERRUPT_REGISTER_MASKr_fields,
  80950         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80951         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  80952         -1,
  80953         -1,
  80954     },
  80955 #endif /* chips */
  80956 
  80957 #if defined(BCM_88790_A0)
  80958     { /* SOC_REG_INT_BRDC_LCM_LCM_INTERRUPT_REGISTER_TESTr */
  80959         soc_block_list[109],
  80960         soc_genreg,
  80961         1,
  80962         0,
  80963         0x102,
  80964         0,
  80965         0,
  80966         1,
  80967         soc_BRDC_LCM_LCM_INTERRUPT_REGISTER_TESTr_fields,
  80968         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  80969         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  80970         -1,
  80971         -1,
  80972     },
  80973 #endif /* chips */
  80974 
  80975 #if defined(BCM_88790_A0)
  80976     { /* SOC_REG_INT_BRDC_LCM_LCM_RCI_ENABLERSr */
  80977         soc_block_list[109],
  80978         soc_genreg,
  80979         1,
  80980         0,
  80981         0x108,
  80982         SOC_REG_FLAG_64_BITS,
  80983         0,
  80984         4,
  80985         soc_BRDC_LCM_LCM_RCI_ENABLERSr_fields,
  80986         SOC_RESET_VAL_DEC(0xffffffff, 0x003fffff)
  80987         SOC_RESET_MASK_DEC(0xffffffff, 0x003fffff)
  80988         -1,
  80989         -1,
  80990     },
  80991 #endif /* chips */
  80992 
  80993 #if defined(BCM_88790_A0)
  80994     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_0r */
  80995         soc_block_list[109],
  80996         soc_genreg,
  80997         1,
  80998         0,
  80999         0x301,
  81000         SOC_REG_FLAG_64_BITS,
  81001         0,
  81002         2,
  81003         soc_BRDC_LCM_LCM_REGISTER_0r_fields,
  81004         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81005         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  81006         -1,
  81007         -1,
  81008     },
  81009 #endif /* chips */
  81010 
  81011 #if defined(BCM_88790_A0)
  81012     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_1r */
  81013         soc_block_list[109],
  81014         soc_genreg,
  81015         1,
  81016         0,
  81017         0x303,
  81018         0,
  81019         0,
  81020         3,
  81021         soc_BRDC_LCM_LCM_REGISTER_1r_fields,
  81022         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81023         SOC_RESET_MASK_DEC(0x07ffffff, 0x00000000)
  81024         -1,
  81025         -1,
  81026     },
  81027 #endif /* chips */
  81028 
  81029 #if defined(BCM_88790_A0)
  81030     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_2r */
  81031         soc_block_list[109],
  81032         soc_genreg,
  81033         1,
  81034         0,
  81035         0x304,
  81036         0,
  81037         0,
  81038         5,
  81039         soc_BRDC_LCM_LCM_REGISTER_2r_fields,
  81040         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81041         SOC_RESET_MASK_DEC(0x3fffffff, 0x00000000)
  81042         -1,
  81043         -1,
  81044     },
  81045 #endif /* chips */
  81046 
  81047 #if defined(BCM_88790_A0)
  81048     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_3r */
  81049         soc_block_list[109],
  81050         soc_genreg,
  81051         1,
  81052         0,
  81053         0x305,
  81054         0,
  81055         0,
  81056         7,
  81057         soc_BRDC_LCM_LCM_REGISTER_3r_fields,
  81058         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81059         SOC_RESET_MASK_DEC(0x003fffff, 0x00000000)
  81060         -1,
  81061         -1,
  81062     },
  81063 #endif /* chips */
  81064 
  81065 #if defined(BCM_88790_A0)
  81066     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_5r */
  81067         soc_block_list[109],
  81068         soc_genreg,
  81069         2,
  81070         0,
  81071         0x21f,
  81072         SOC_REG_FLAG_64_BITS |
  81073                           SOC_REG_FLAG_ARRAY |
  81074                           SOC_REG_FLAG_REG_ARRAY,
  81075         0,
  81076         3,
  81077         soc_BRDC_LCM_LCM_REGISTER_5r_fields,
  81078         SOC_RESET_VAL_DEC(0x06000600, 0x00000600)
  81079         SOC_RESET_MASK_DEC(0x1fff1fff, 0x00001fff)
  81080         -1,
  81081         -1,
  81082     },
  81083 #endif /* chips */
  81084 
  81085 #if defined(BCM_88790_A0)
  81086     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_6r */
  81087         soc_block_list[109],
  81088         soc_genreg,
  81089         2,
  81090         0,
  81091         0x223,
  81092         SOC_REG_FLAG_64_BITS |
  81093                           SOC_REG_FLAG_ARRAY |
  81094                           SOC_REG_FLAG_REG_ARRAY,
  81095         0,
  81096         3,
  81097         soc_BRDC_LCM_LCM_REGISTER_6r_fields,
  81098         SOC_RESET_VAL_DEC(0x50aa8554, 0x00000015)
  81099         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  81100         -1,
  81101         -1,
  81102     },
  81103 #endif /* chips */
  81104 
  81105 #if defined(BCM_88790_A0)
  81106     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_7r */
  81107         soc_block_list[109],
  81108         soc_genreg,
  81109         2,
  81110         0,
  81111         0x227,
  81112         SOC_REG_FLAG_64_BITS |
  81113                           SOC_REG_FLAG_ARRAY |
  81114                           SOC_REG_FLAG_REG_ARRAY,
  81115         0,
  81116         3,
  81117         soc_BRDC_LCM_LCM_REGISTER_7r_fields,
  81118         SOC_RESET_VAL_DEC(0xa05502a8, 0x0000000a)
  81119         SOC_RESET_MASK_DEC(0xffffffff, 0x0000007f)
  81120         -1,
  81121         -1,
  81122     },
  81123 #endif /* chips */
  81124 
  81125 #if defined(BCM_88790_A0)
  81126     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_8r */
  81127         soc_block_list[109],
  81128         soc_genreg,
  81129         8,
  81130         0,
  81131         0x28e,
  81132         SOC_REG_FLAG_ARRAY |
  81133                           SOC_REG_FLAG_RO |
  81134                           SOC_REG_FLAG_REG_ARRAY,
  81135         0,
  81136         1,
  81137         soc_BRDC_LCM_LCM_REGISTER_8r_fields,
  81138         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81139         SOC_RESET_MASK_DEC(0x01ffffff, 0x00000000)
  81140         -1,
  81141         -1,
  81142     },
  81143 #endif /* chips */
  81144 
  81145 #if defined(BCM_88790_A0)
  81146     { /* SOC_REG_INT_BRDC_LCM_LCM_REGISTER_9r */
  81147         soc_block_list[109],
  81148         soc_genreg,
  81149         3,
  81150         0,
  81151         0x333,
  81152         SOC_REG_FLAG_ABOVE_64_BITS |
  81153                           SOC_REG_FLAG_ARRAY |
  81154                           SOC_REG_FLAG_RO |
  81155                           SOC_REG_FLAG_REG_ARRAY,
  81156         0,
  81157         8,
  81158         soc_BRDC_LCM_LCM_REGISTER_9r_fields,
  81159         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81160         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81161         -1,
  81162         -1,
  81163     },
  81164 #endif /* chips */
  81165 
  81166 #if defined(BCM_88790_A0)
  81167     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_1r */
  81168         soc_block_list[109],
  81169         soc_genreg,
  81170         1,
  81171         0,
  81172         0x27b,
  81173         SOC_REG_FLAG_RO,
  81174         0,
  81175         2,
  81176         soc_BRDC_LCM_LINK_CNT_INFO_1r_fields,
  81177         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81178         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  81179         -1,
  81180         -1,
  81181     },
  81182 #endif /* chips */
  81183 
  81184 #if defined(BCM_88790_A0)
  81185     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_2r */
  81186         soc_block_list[109],
  81187         soc_genreg,
  81188         1,
  81189         0,
  81190         0x27c,
  81191         SOC_REG_FLAG_RO,
  81192         0,
  81193         2,
  81194         soc_BRDC_LCM_LINK_CNT_INFO_2r_fields,
  81195         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81196         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  81197         -1,
  81198         -1,
  81199     },
  81200 #endif /* chips */
  81201 
  81202 #if defined(BCM_88790_A0)
  81203     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_3r */
  81204         soc_block_list[109],
  81205         soc_genreg,
  81206         1,
  81207         0,
  81208         0x27d,
  81209         SOC_REG_FLAG_RO,
  81210         0,
  81211         2,
  81212         soc_BRDC_LCM_LINK_CNT_INFO_3r_fields,
  81213         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81214         SOC_RESET_MASK_DEC(0x03ffffff, 0x00000000)
  81215         -1,
  81216         -1,
  81217     },
  81218 #endif /* chips */
  81219 
  81220 #if defined(BCM_88790_A0)
  81221     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_4r */
  81222         soc_block_list[109],
  81223         soc_genreg,
  81224         1,
  81225         0,
  81226         0x27e,
  81227         SOC_REG_FLAG_RO,
  81228         0,
  81229         2,
  81230         soc_BRDC_LCM_LINK_CNT_INFO_4r_fields,
  81231         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81232         SOC_RESET_MASK_DEC(0x0fffffff, 0x00000000)
  81233         -1,
  81234         -1,
  81235     },
  81236 #endif /* chips */
  81237 
  81238 #if defined(BCM_88790_A0)
  81239     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_5r */
  81240         soc_block_list[109],
  81241         soc_genreg,
  81242         1,
  81243         0,
  81244         0x27f,
  81245         SOC_REG_FLAG_RO,
  81246         0,
  81247         2,
  81248         soc_BRDC_LCM_LINK_CNT_INFO_5r_fields,
  81249         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81250         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81251         -1,
  81252         -1,
  81253     },
  81254 #endif /* chips */
  81255 
  81256 #if defined(BCM_88790_A0)
  81257     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_6r */
  81258         soc_block_list[109],
  81259         soc_genreg,
  81260         1,
  81261         0,
  81262         0x280,
  81263         SOC_REG_FLAG_RO,
  81264         0,
  81265         2,
  81266         soc_BRDC_LCM_LINK_CNT_INFO_6r_fields,
  81267         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81268         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81269         -1,
  81270         -1,
  81271     },
  81272 #endif /* chips */
  81273 
  81274 #if defined(BCM_88790_A0)
  81275     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_7r */
  81276         soc_block_list[109],
  81277         soc_genreg,
  81278         1,
  81279         0,
  81280         0x281,
  81281         SOC_REG_FLAG_64_BITS |
  81282                           SOC_REG_FLAG_RO,
  81283         0,
  81284         2,
  81285         soc_BRDC_LCM_LINK_CNT_INFO_7r_fields,
  81286         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81287         SOC_RESET_MASK_DEC(0xffffffff, 0x000000ff)
  81288         -1,
  81289         -1,
  81290     },
  81291 #endif /* chips */
  81292 
  81293 #if defined(BCM_88790_A0)
  81294     { /* SOC_REG_INT_BRDC_LCM_LINK_CNT_INFO_SELECTr */
  81295         soc_block_list[109],
  81296         soc_genreg,
  81297         1,
  81298         0,
  81299         0x27a,
  81300         0,
  81301         0,
  81302         2,
  81303         soc_BRDC_LCM_LINK_CNT_INFO_SELECTr_fields,
  81304         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81305         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  81306         -1,
  81307         -1,
  81308     },
  81309 #endif /* chips */
  81310 
  81311 #if defined(BCM_88790_A0)
  81312     { /* SOC_REG_INT_BRDC_LCM_LINK_FC_TH_PROFILEr */
  81313         soc_block_list[109],
  81314         soc_genreg,
  81315         2,
  81316         0,
  81317         0x111,
  81318         SOC_REG_FLAG_64_BITS |
  81319                           SOC_REG_FLAG_ARRAY |
  81320                           SOC_REG_FLAG_REG_ARRAY,
  81321         0,
  81322         3,
  81323         soc_BRDC_LCM_LINK_FC_TH_PROFILEr_fields,
  81324         SOC_RESET_VAL_DEC(0x8ca08ca0, 0x00008ca0)
  81325         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  81326         -1,
  81327         -1,
  81328     },
  81329 #endif /* chips */
  81330 
  81331 #if defined(BCM_88790_A0)
  81332     { /* SOC_REG_INT_BRDC_LCM_LINK_LEVEL_FLOW_CONTROL_Pr */
  81333         soc_block_list[109],
  81334         soc_genreg,
  81335         3,
  81336         0,
  81337         0x37d,
  81338         SOC_REG_FLAG_ARRAY |
  81339                           SOC_REG_FLAG_RO |
  81340                           SOC_REG_FLAG_REG_ARRAY |
  81341                           SOC_REG_FLAG_SIGNAL,
  81342         0,
  81343         1,
  81344         soc_BRDC_LCM_LINK_LEVEL_FLOW_CONTROL_Pr_fields,
  81345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81346         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  81347         -1,
  81348         -1,
  81349     },
  81350 #endif /* chips */
  81351 
  81352 #if defined(BCM_88790_A0)
  81353     { /* SOC_REG_INT_BRDC_LCM_LINK_LOAD_COUNT_CFGr */
  81354         soc_block_list[109],
  81355         soc_genreg,
  81356         1,
  81357         0,
  81358         0x20f,
  81359         0,
  81360         0,
  81361         1,
  81362         soc_BRDC_LCM_LINK_LOAD_COUNT_CFGr_fields,
  81363         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  81364         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  81365         -1,
  81366         -1,
  81367     },
  81368 #endif /* chips */
  81369 
  81370 #if defined(BCM_88790_A0)
  81371     { /* SOC_REG_INT_BRDC_LCM_LINK_LOAD_HYST_THr */
  81372         soc_block_list[109],
  81373         soc_genreg,
  81374         1,
  81375         0,
  81376         0x211,
  81377         0,
  81378         0,
  81379         2,
  81380         soc_BRDC_LCM_LINK_LOAD_HYST_THr_fields,
  81381         SOC_RESET_VAL_DEC(0xffff0000, 0x00000000)
  81382         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81383         -1,
  81384         -1,
  81385     },
  81386 #endif /* chips */
  81387 
  81388 #if defined(BCM_88790_A0)
  81389     { /* SOC_REG_INT_BRDC_LCM_LINK_LOAD_HYST_TYPEr */
  81390         soc_block_list[109],
  81391         soc_genreg,
  81392         1,
  81393         0,
  81394         0x210,
  81395         0,
  81396         0,
  81397         1,
  81398         soc_BRDC_LCM_LINK_LOAD_HYST_TYPEr_fields,
  81399         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81400         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81401         -1,
  81402         -1,
  81403     },
  81404 #endif /* chips */
  81405 
  81406 #if defined(BCM_88790_A0)
  81407     { /* SOC_REG_INT_BRDC_LCM_LINK_RCI_GRNT_TH_PROFILEr */
  81408         soc_block_list[109],
  81409         soc_genreg,
  81410         2,
  81411         0,
  81412         0x115,
  81413         SOC_REG_FLAG_ABOVE_64_BITS |
  81414                           SOC_REG_FLAG_ARRAY |
  81415                           SOC_REG_FLAG_REG_ARRAY,
  81416         0,
  81417         9,
  81418         soc_BRDC_LCM_LINK_RCI_GRNT_TH_PROFILEr_fields,
  81419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81421         -1,
  81422         -1,
  81423     },
  81424 #endif /* chips */
  81425 
  81426 #if defined(BCM_88790_A0)
  81427     { /* SOC_REG_INT_BRDC_LCM_LINK_RCI_TOTAL_TH_PROFILEr */
  81428         soc_block_list[109],
  81429         soc_genreg,
  81430         2,
  81431         0,
  81432         0x11f,
  81433         SOC_REG_FLAG_ABOVE_64_BITS |
  81434                           SOC_REG_FLAG_ARRAY |
  81435                           SOC_REG_FLAG_REG_ARRAY,
  81436         0,
  81437         9,
  81438         soc_BRDC_LCM_LINK_RCI_TOTAL_TH_PROFILEr_fields,
  81439         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81440         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81441         -1,
  81442         -1,
  81443     },
  81444 #endif /* chips */
  81445 
  81446 #if defined(BCM_88790_A0)
  81447     { /* SOC_REG_INT_BRDC_LCM_LINK_TH_PROFILEr */
  81448         soc_block_list[109],
  81449         soc_genreg,
  81450         2,
  81451         0,
  81452         0x10b,
  81453         SOC_REG_FLAG_ABOVE_64_BITS |
  81454                           SOC_REG_FLAG_ARRAY |
  81455                           SOC_REG_FLAG_REG_ARRAY,
  81456         0,
  81457         6,
  81458         soc_BRDC_LCM_LINK_TH_PROFILEr_fields,
  81459         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81460         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81461         -1,
  81462         -1,
  81463     },
  81464 #endif /* chips */
  81465 
  81466 #if defined(BCM_88790_A0)
  81467     { /* SOC_REG_INT_BRDC_LCM_LINK_TH_PROFILES_MAPPINGr */
  81468         soc_block_list[109],
  81469         soc_genreg,
  81470         1,
  81471         0,
  81472         0x129,
  81473         0,
  81474         0,
  81475         1,
  81476         soc_BRDC_LCM_LINK_TH_PROFILES_MAPPINGr_fields,
  81477         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81478         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  81479         -1,
  81480         -1,
  81481     },
  81482 #endif /* chips */
  81483 
  81484 #if defined(BCM_88790_A0)
  81485     { /* SOC_REG_INT_BRDC_LCM_LLFC_RATE_CNT_Pr */
  81486         soc_block_list[109],
  81487         soc_genreg,
  81488         3,
  81489         0,
  81490         0x380,
  81491         SOC_REG_FLAG_ARRAY |
  81492                           SOC_REG_FLAG_RO |
  81493                           SOC_REG_FLAG_REG_ARRAY,
  81494         SOC_REG_FLAG_COUNTER_FEILDS,
  81495         1,
  81496         soc_BRDC_LCM_LLFC_RATE_CNT_Pr_fields,
  81497         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81498         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81499         -1,
  81500         -1,
  81501     },
  81502 #endif /* chips */
  81503 
  81504 #if defined(BCM_88790_A0)
  81505     { /* SOC_REG_INT_BRDC_LCM_PIPES_MAPPING_ENr */
  81506         soc_block_list[109],
  81507         soc_genreg,
  81508         1,
  81509         0,
  81510         0x346,
  81511         0,
  81512         0,
  81513         1,
  81514         soc_BRDC_LCM_PIPES_MAPPING_ENr_fields,
  81515         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81516         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  81517         -1,
  81518         -1,
  81519     },
  81520 #endif /* chips */
  81521 
  81522 #if defined(BCM_88790_A0)
  81523     { /* SOC_REG_INT_BRDC_LCM_PIPES_SEPARATION_REGISTERr */
  81524         soc_block_list[109],
  81525         soc_genreg,
  81526         1,
  81527         0,
  81528         0x103,
  81529         0,
  81530         0,
  81531         8,
  81532         soc_BRDC_LCM_PIPES_SEPARATION_REGISTERr_fields,
  81533         SOC_RESET_VAL_DEC(0x00008095, 0x00000000)
  81534         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  81535         -1,
  81536         -1,
  81537     },
  81538 #endif /* chips */
  81539 
  81540 #if defined(BCM_88790_A0)
  81541     { /* SOC_REG_INT_BRDC_LCM_RCI_TABLE_PIPEr */
  81542         soc_block_list[109],
  81543         soc_genreg,
  81544         3,
  81545         0,
  81546         0x20a,
  81547         SOC_REG_FLAG_ARRAY |
  81548                           SOC_REG_FLAG_REG_ARRAY,
  81549         0,
  81550         1,
  81551         soc_BRDC_LCM_RCI_TABLE_PIPEr_fields,
  81552         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81553         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81554         -1,
  81555         -1,
  81556     },
  81557 #endif /* chips */
  81558 
  81559 #if defined(BCM_88790_A0)
  81560     { /* SOC_REG_INT_BRDC_LCM_READ_MECH_DEBUG_1r */
  81561         soc_block_list[109],
  81562         soc_genreg,
  81563         1,
  81564         0,
  81565         0x383,
  81566         0,
  81567         0,
  81568         1,
  81569         soc_BRDC_LCM_READ_MECH_DEBUG_1r_fields,
  81570         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  81571         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81572         -1,
  81573         -1,
  81574     },
  81575 #endif /* chips */
  81576 
  81577 #if defined(BCM_88790_A0)
  81578     { /* SOC_REG_INT_BRDC_LCM_REMOTE_PRI_PIPE_IDXr */
  81579         soc_block_list[109],
  81580         soc_genreg,
  81581         1,
  81582         0,
  81583         0x347,
  81584         SOC_REG_FLAG_64_BITS,
  81585         0,
  81586         1,
  81587         soc_BRDC_LCM_REMOTE_PRI_PIPE_IDXr_fields,
  81588         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81589         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  81590         -1,
  81591         -1,
  81592     },
  81593 #endif /* chips */
  81594 
  81595 #if defined(BCM_88790_A0)
  81596     { /* SOC_REG_INT_BRDC_LCM_REMOTE_SEC_PIPE_IDXr */
  81597         soc_block_list[109],
  81598         soc_genreg,
  81599         1,
  81600         0,
  81601         0x349,
  81602         SOC_REG_FLAG_64_BITS,
  81603         0,
  81604         1,
  81605         soc_BRDC_LCM_REMOTE_SEC_PIPE_IDXr_fields,
  81606         SOC_RESET_VAL_DEC(0x55555555, 0x00005555)
  81607         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  81608         -1,
  81609         -1,
  81610     },
  81611 #endif /* chips */
  81612 
  81613 #if defined(BCM_88790_A0)
  81614     { /* SOC_REG_INT_BRDC_LCM_RESERVED_MIRROR_ADDRr */
  81615         soc_block_list[109],
  81616         soc_genreg,
  81617         1,
  81618         0,
  81619         0x85,
  81620         0,
  81621         0,
  81622         2,
  81623         soc_BRDC_LCM_RESERVED_MIRROR_ADDRr_fields,
  81624         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81625         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  81626         -1,
  81627         -1,
  81628     },
  81629 #endif /* chips */
  81630 
  81631 #if defined(BCM_88790_A0)
  81632     { /* SOC_REG_INT_BRDC_LCM_RESERVED_MTCDr */
  81633         soc_block_list[109],
  81634         soc_genreg,
  81635         1,
  81636         0,
  81637         0xae,
  81638         0,
  81639         0,
  81640         6,
  81641         soc_BRDC_LCM_RESERVED_MTCDr_fields,
  81642         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81643         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  81644         -1,
  81645         -1,
  81646     },
  81647 #endif /* chips */
  81648 
  81649 #if defined(BCM_88790_A0)
  81650     { /* SOC_REG_INT_BRDC_LCM_RESERVED_MTCPr */
  81651         soc_block_list[109],
  81652         soc_genreg,
  81653         1,
  81654         0,
  81655         0xad,
  81656         SOC_REG_FLAG_64_BITS,
  81657         0,
  81658         17,
  81659         soc_BRDC_LCM_RESERVED_MTCPr_fields,
  81660         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  81661         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  81662         -1,
  81663         -1,
  81664     },
  81665 #endif /* chips */
  81666 
  81667 #if defined(BCM_88790_A0)
  81668     { /* SOC_REG_INT_BRDC_LCM_RESERVED_SPARE_0r */
  81669         soc_block_list[109],
  81670         soc_genreg,
  81671         1,
  81672         0,
  81673         0x90,
  81674         0,
  81675         0,
  81676         1,
  81677         soc_BRDC_LCM_RESERVED_SPARE_0r_fields,
  81678         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  81679         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81680         -1,
  81681         -1,
  81682     },
  81683 #endif /* chips */
  81684 
  81685 #if defined(BCM_88790_A0)
  81686     { /* SOC_REG_INT_BRDC_LCM_RESERVED_SPARE_1r */
  81687         soc_block_list[109],
  81688         soc_genreg,
  81689         1,
  81690         0,
  81691         0x91,
  81692         0,
  81693         0,
  81694         1,
  81695         soc_BRDC_LCM_RESERVED_SPARE_1r_fields,
  81696         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  81697         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81698         -1,
  81699         -1,
  81700     },
  81701 #endif /* chips */
  81702 
  81703 #if defined(BCM_88790_A0)
  81704     { /* SOC_REG_INT_BRDC_LCM_RESERVED_SPARE_2r */
  81705         soc_block_list[109],
  81706         soc_genreg,
  81707         1,
  81708         0,
  81709         0x92,
  81710         0,
  81711         0,
  81712         1,
  81713         soc_BRDC_LCM_RESERVED_SPARE_2r_fields,
  81714         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81715         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81716         -1,
  81717         -1,
  81718     },
  81719 #endif /* chips */
  81720 
  81721 #if defined(BCM_88790_A0)
  81722     { /* SOC_REG_INT_BRDC_LCM_RESERVED_SPARE_3r */
  81723         soc_block_list[109],
  81724         soc_genreg,
  81725         1,
  81726         0,
  81727         0x93,
  81728         0,
  81729         0,
  81730         1,
  81731         soc_BRDC_LCM_RESERVED_SPARE_3r_fields,
  81732         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81733         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  81734         -1,
  81735         -1,
  81736     },
  81737 #endif /* chips */
  81738 
  81739 #if defined(BCM_88790_A0)
  81740     { /* SOC_REG_INT_BRDC_LCM_SBUS_BROADCAST_IDr */
  81741         soc_block_list[109],
  81742         soc_genreg,
  81743         1,
  81744         0,
  81745         0x86,
  81746         0,
  81747         0,
  81748         1,
  81749         soc_BRDC_LCM_SBUS_BROADCAST_IDr_fields,
  81750         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  81751         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  81752         -1,
  81753         -1,
  81754     },
  81755 #endif /* chips */
  81756 
  81757 #if defined(BCM_88790_A0)
  81758     { /* SOC_REG_INT_BRDC_LCM_SBUS_LAST_IN_CHAINr */
  81759         soc_block_list[109],
  81760         soc_genreg,
  81761         1,
  81762         0,
  81763         0x87,
  81764         0,
  81765         0,
  81766         1,
  81767         soc_BRDC_LCM_SBUS_LAST_IN_CHAINr_fields,
  81768         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81769         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81770         -1,
  81771         -1,
  81772     },
  81773 #endif /* chips */
  81774 
  81775 #if defined(BCM_88790_A0)
  81776     { /* SOC_REG_INT_BRDC_LCM_THREE_PIPES_BMPr */
  81777         soc_block_list[109],
  81778         soc_genreg,
  81779         1,
  81780         0,
  81781         0x34c,
  81782         0,
  81783         0,
  81784         1,
  81785         soc_BRDC_LCM_THREE_PIPES_BMPr_fields,
  81786         SOC_RESET_VAL_DEC(0x00ffffff, 0x00000000)
  81787         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  81788         -1,
  81789         -1,
  81790     },
  81791 #endif /* chips */
  81792 
  81793 #if defined(BCM_88790_A0)
  81794     { /* SOC_REG_INT_BRDC_LCM_TWO_PIPES_BMPr */
  81795         soc_block_list[109],
  81796         soc_genreg,
  81797         1,
  81798         0,
  81799         0x34b,
  81800         0,
  81801         0,
  81802         1,
  81803         soc_BRDC_LCM_TWO_PIPES_BMPr_fields,
  81804         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81805         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  81806         -1,
  81807         -1,
  81808     },
  81809 #endif /* chips */
  81810 
  81811 #if defined(BCM_88790_A0)
  81812     { /* SOC_REG_INT_BRDC_LCM_TX_CPU_CELL_OUTPUT_LINKr */
  81813         soc_block_list[109],
  81814         soc_genreg,
  81815         1,
  81816         0,
  81817         0x355,
  81818         0,
  81819         0,
  81820         2,
  81821         soc_BRDC_LCM_TX_CPU_CELL_OUTPUT_LINKr_fields,
  81822         SOC_RESET_VAL_DEC(0x00007f00, 0x00000000)
  81823         SOC_RESET_MASK_DEC(0x0000ff1f, 0x00000000)
  81824         -1,
  81825         -1,
  81826     },
  81827 #endif /* chips */
  81828 
  81829 #if defined(BCM_88790_A0)
  81830     { /* SOC_REG_INT_BRDC_LCM_TX_CPU_CELL_TRGr */
  81831         soc_block_list[109],
  81832         soc_genreg,
  81833         1,
  81834         0,
  81835         0x354,
  81836         SOC_REG_FLAG_SIGNAL,
  81837         0,
  81838         1,
  81839         soc_BRDC_LCM_TX_CPU_CELL_TRGr_fields,
  81840         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81841         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81842         -1,
  81843         -1,
  81844     },
  81845 #endif /* chips */
  81846 
  81847 #if defined(BCM_88790_A0)
  81848     { /* SOC_REG_INT_BRDC_QRH_ALLOWED_LINKS_PIPE_0_REGISTERr */
  81849         soc_block_list[111],
  81850         soc_genreg,
  81851         1,
  81852         0,
  81853         0x109,
  81854         SOC_REG_FLAG_ABOVE_64_BITS,
  81855         0,
  81856         1,
  81857         soc_BRDC_QRH_ALLOWED_LINKS_PIPE_0_REGISTERr_fields,
  81858         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81859         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81860         -1,
  81861         -1,
  81862     },
  81863 #endif /* chips */
  81864 
  81865 #if defined(BCM_88790_A0)
  81866     { /* SOC_REG_INT_BRDC_QRH_ALLOWED_LINKS_PIPE_1_REGISTERr */
  81867         soc_block_list[111],
  81868         soc_genreg,
  81869         1,
  81870         0,
  81871         0x10f,
  81872         SOC_REG_FLAG_ABOVE_64_BITS,
  81873         0,
  81874         1,
  81875         soc_BRDC_QRH_ALLOWED_LINKS_PIPE_1_REGISTERr_fields,
  81876         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81877         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81878         -1,
  81879         -1,
  81880     },
  81881 #endif /* chips */
  81882 
  81883 #if defined(BCM_88790_A0)
  81884     { /* SOC_REG_INT_BRDC_QRH_ALLOWED_LINKS_PIPE_2_REGISTERr */
  81885         soc_block_list[111],
  81886         soc_genreg,
  81887         1,
  81888         0,
  81889         0x115,
  81890         SOC_REG_FLAG_ABOVE_64_BITS,
  81891         0,
  81892         1,
  81893         soc_BRDC_QRH_ALLOWED_LINKS_PIPE_2_REGISTERr_fields,
  81894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81896         -1,
  81897         -1,
  81898     },
  81899 #endif /* chips */
  81900 
  81901 #if defined(BCM_88790_A0)
  81902     { /* SOC_REG_INT_BRDC_QRH_ALL_MUL_DROP_THr */
  81903         soc_block_list[111],
  81904         soc_genreg,
  81905         1,
  81906         0,
  81907         0x125,
  81908         SOC_REG_FLAG_64_BITS,
  81909         0,
  81910         3,
  81911         soc_BRDC_QRH_ALL_MUL_DROP_THr_fields,
  81912         SOC_RESET_VAL_DEC(0x08000200, 0x00000000)
  81913         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  81914         -1,
  81915         -1,
  81916     },
  81917 #endif /* chips */
  81918 
  81919 #if defined(BCM_88790_A0)
  81920     { /* SOC_REG_INT_BRDC_QRH_AUTO_DOC_NAME_0r */
  81921         soc_block_list[111],
  81922         soc_genreg,
  81923         1,
  81924         0,
  81925         0x107,
  81926         0,
  81927         0,
  81928         1,
  81929         soc_BRDC_QRH_AUTO_DOC_NAME_0r_fields,
  81930         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  81931         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  81932         -1,
  81933         -1,
  81934     },
  81935 #endif /* chips */
  81936 
  81937 #if defined(BCM_88790_A0)
  81938     { /* SOC_REG_INT_BRDC_QRH_AUTO_DOC_NAME_1r */
  81939         soc_block_list[111],
  81940         soc_genreg,
  81941         1,
  81942         0,
  81943         0x13e,
  81944         SOC_REG_FLAG_ABOVE_64_BITS,
  81945         0,
  81946         1,
  81947         soc_BRDC_QRH_AUTO_DOC_NAME_1r_fields,
  81948         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81949         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  81950         -1,
  81951         -1,
  81952     },
  81953 #endif /* chips */
  81954 
  81955 #if defined(BCM_88790_A0)
  81956     { /* SOC_REG_INT_BRDC_QRH_CRH_INTERRUPT_MASK_REGISTERr */
  81957         soc_block_list[111],
  81958         soc_genreg,
  81959         1,
  81960         0,
  81961         0x104,
  81962         0,
  81963         0,
  81964         3,
  81965         soc_BRDC_QRH_CRH_INTERRUPT_MASK_REGISTERr_fields,
  81966         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81967         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  81968         -1,
  81969         -1,
  81970     },
  81971 #endif /* chips */
  81972 
  81973 #if defined(BCM_88790_A0)
  81974     { /* SOC_REG_INT_BRDC_QRH_CRH_INTERRUPT_REGISTERr */
  81975         soc_block_list[111],
  81976         soc_genreg,
  81977         1,
  81978         0,
  81979         0x103,
  81980         SOC_REG_FLAG_INTERRUPT |
  81981                           SOC_REG_FLAG_SIGNAL,
  81982         0,
  81983         3,
  81984         soc_BRDC_QRH_CRH_INTERRUPT_REGISTERr_fields,
  81985         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  81986         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  81987         -1,
  81988         -1,
  81989     },
  81990 #endif /* chips */
  81991 
  81992 #if defined(BCM_88790_A0)
  81993     { /* SOC_REG_INT_BRDC_QRH_CRH_INTERRUPT_REGISTER_TESTr */
  81994         soc_block_list[111],
  81995         soc_genreg,
  81996         1,
  81997         0,
  81998         0x105,
  81999         0,
  82000         0,
  82001         1,
  82002         soc_BRDC_QRH_CRH_INTERRUPT_REGISTER_TESTr_fields,
  82003         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82004         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82005         -1,
  82006         -1,
  82007     },
  82008 #endif /* chips */
  82009 
  82010 #if defined(BCM_88790_A0)
  82011     { /* SOC_REG_INT_BRDC_QRH_DRH_DROPPED_LOW_MULr */
  82012         soc_block_list[111],
  82013         soc_genreg,
  82014         1,
  82015         0,
  82016         0x127,
  82017         SOC_REG_FLAG_RO,
  82018         SOC_REG_FLAG_COUNTER_FEILDS,
  82019         2,
  82020         soc_BRDC_QRH_DRH_DROPPED_LOW_MULr_fields,
  82021         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82022         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82023         -1,
  82024         -1,
  82025     },
  82026 #endif /* chips */
  82027 
  82028 #if defined(BCM_88790_A0)
  82029     { /* SOC_REG_INT_BRDC_QRH_DRH_FLOW_CONTROL_CNT_Pr */
  82030         soc_block_list[111],
  82031         soc_genreg,
  82032         3,
  82033         0,
  82034         0x12c,
  82035         SOC_REG_FLAG_ARRAY |
  82036                           SOC_REG_FLAG_RO |
  82037                           SOC_REG_FLAG_REG_ARRAY,
  82038         SOC_REG_FLAG_COUNTER_FEILDS,
  82039         1,
  82040         soc_BRDC_QRH_DRH_FLOW_CONTROL_CNT_Pr_fields,
  82041         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82042         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82043         -1,
  82044         -1,
  82045     },
  82046 #endif /* chips */
  82047 
  82048 #if defined(BCM_88790_A0)
  82049     { /* SOC_REG_INT_BRDC_QRH_DRH_INPUT_QUERY_CNT_Pr */
  82050         soc_block_list[111],
  82051         soc_genreg,
  82052         3,
  82053         0,
  82054         0x129,
  82055         SOC_REG_FLAG_ARRAY |
  82056                           SOC_REG_FLAG_RO |
  82057                           SOC_REG_FLAG_REG_ARRAY,
  82058         SOC_REG_FLAG_COUNTER_FEILDS,
  82059         1,
  82060         soc_BRDC_QRH_DRH_INPUT_QUERY_CNT_Pr_fields,
  82061         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82062         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82063         -1,
  82064         -1,
  82065     },
  82066 #endif /* chips */
  82067 
  82068 #if defined(BCM_88790_A0)
  82069     { /* SOC_REG_INT_BRDC_QRH_DRH_INTERRUPT_MASK_REGISTERr */
  82070         soc_block_list[111],
  82071         soc_genreg,
  82072         1,
  82073         0,
  82074         0x101,
  82075         0,
  82076         0,
  82077         6,
  82078         soc_BRDC_QRH_DRH_INTERRUPT_MASK_REGISTERr_fields,
  82079         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82080         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82081         -1,
  82082         -1,
  82083     },
  82084 #endif /* chips */
  82085 
  82086 #if defined(BCM_88790_A0)
  82087     { /* SOC_REG_INT_BRDC_QRH_DRH_INTERRUPT_REGISTERr */
  82088         soc_block_list[111],
  82089         soc_genreg,
  82090         1,
  82091         0,
  82092         0x100,
  82093         SOC_REG_FLAG_INTERRUPT |
  82094                           SOC_REG_FLAG_SIGNAL,
  82095         0,
  82096         6,
  82097         soc_BRDC_QRH_DRH_INTERRUPT_REGISTERr_fields,
  82098         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82099         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82100         -1,
  82101         -1,
  82102     },
  82103 #endif /* chips */
  82104 
  82105 #if defined(BCM_88790_A0)
  82106     { /* SOC_REG_INT_BRDC_QRH_DRH_INTERRUPT_REGISTER_TESTr */
  82107         soc_block_list[111],
  82108         soc_genreg,
  82109         1,
  82110         0,
  82111         0x102,
  82112         0,
  82113         0,
  82114         1,
  82115         soc_BRDC_QRH_DRH_INTERRUPT_REGISTER_TESTr_fields,
  82116         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82117         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82118         -1,
  82119         -1,
  82120     },
  82121 #endif /* chips */
  82122 
  82123 #if defined(BCM_88790_A0)
  82124     { /* SOC_REG_INT_BRDC_QRH_DRH_LOAD_BALANCING_GENERAL_CONFIGr */
  82125         soc_block_list[111],
  82126         soc_genreg,
  82127         1,
  82128         0,
  82129         0x135,
  82130         SOC_REG_FLAG_64_BITS,
  82131         0,
  82132         6,
  82133         soc_BRDC_QRH_DRH_LOAD_BALANCING_GENERAL_CONFIGr_fields,
  82134         SOC_RESET_VAL_DEC(0x00000030, 0x0000ffff)
  82135         SOC_RESET_MASK_DEC(0x0000007f, 0xffffffff)
  82136         -1,
  82137         -1,
  82138     },
  82139 #endif /* chips */
  82140 
  82141 #if defined(BCM_88790_A0)
  82142     { /* SOC_REG_INT_BRDC_QRH_DRH_LOAD_BALANCING_LEVEL_CONFIGr */
  82143         soc_block_list[111],
  82144         soc_genreg,
  82145         1,
  82146         0,
  82147         0x132,
  82148         SOC_REG_FLAG_64_BITS,
  82149         0,
  82150         4,
  82151         soc_BRDC_QRH_DRH_LOAD_BALANCING_LEVEL_CONFIGr_fields,
  82152         SOC_RESET_VAL_DEC(0x11008ff0, 0x00000000)
  82153         SOC_RESET_MASK_DEC(0xffffffff, 0x00000001)
  82154         -1,
  82155         -1,
  82156     },
  82157 #endif /* chips */
  82158 
  82159 #if defined(BCM_88790_A0)
  82160     { /* SOC_REG_INT_BRDC_QRH_DRH_LOAD_BALANCING_LEVEL_OPTIMIZATIONr */
  82161         soc_block_list[111],
  82162         soc_genreg,
  82163         1,
  82164         0,
  82165         0x134,
  82166         0,
  82167         0,
  82168         3,
  82169         soc_BRDC_QRH_DRH_LOAD_BALANCING_LEVEL_OPTIMIZATIONr_fields,
  82170         SOC_RESET_VAL_DEC(0xffff0080, 0x00000000)
  82171         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82172         -1,
  82173         -1,
  82174     },
  82175 #endif /* chips */
  82176 
  82177 #if defined(BCM_88790_A0)
  82178     { /* SOC_REG_INT_BRDC_QRH_DRH_MCSFF_HIT_COUNTERr */
  82179         soc_block_list[111],
  82180         soc_genreg,
  82181         1,
  82182         0,
  82183         0x128,
  82184         SOC_REG_FLAG_RO,
  82185         SOC_REG_FLAG_COUNTER_FEILDS,
  82186         2,
  82187         soc_BRDC_QRH_DRH_MCSFF_HIT_COUNTERr_fields,
  82188         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82189         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  82190         -1,
  82191         -1,
  82192     },
  82193 #endif /* chips */
  82194 
  82195 #if defined(BCM_88790_A0)
  82196     { /* SOC_REG_INT_BRDC_QRH_DRH_OUTPUT_REPLY_CNT_Pr */
  82197         soc_block_list[111],
  82198         soc_genreg,
  82199         3,
  82200         0,
  82201         0x12f,
  82202         SOC_REG_FLAG_ARRAY |
  82203                           SOC_REG_FLAG_RO |
  82204                           SOC_REG_FLAG_REG_ARRAY,
  82205         SOC_REG_FLAG_COUNTER_FEILDS,
  82206         1,
  82207         soc_BRDC_QRH_DRH_OUTPUT_REPLY_CNT_Pr_fields,
  82208         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82209         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82210         -1,
  82211         -1,
  82212     },
  82213 #endif /* chips */
  82214 
  82215 #if defined(BCM_88790_A0)
  82216     { /* SOC_REG_INT_BRDC_QRH_DRH_REP_FIFO_STAT_Pr */
  82217         soc_block_list[111],
  82218         soc_genreg,
  82219         3,
  82220         0,
  82221         0x151,
  82222         SOC_REG_FLAG_ARRAY |
  82223                           SOC_REG_FLAG_RO |
  82224                           SOC_REG_FLAG_REG_ARRAY,
  82225         0,
  82226         1,
  82227         soc_BRDC_QRH_DRH_REP_FIFO_STAT_Pr_fields,
  82228         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82229         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  82230         -1,
  82231         -1,
  82232     },
  82233 #endif /* chips */
  82234 
  82235 #if defined(BCM_88790_A0)
  82236     { /* SOC_REG_INT_BRDC_QRH_DRH_UNREACHABLEMULTICASTINFOr */
  82237         soc_block_list[111],
  82238         soc_genreg,
  82239         1,
  82240         0,
  82241         0x121,
  82242         SOC_REG_FLAG_RO,
  82243         0,
  82244         2,
  82245         soc_BRDC_QRH_DRH_UNREACHABLEMULTICASTINFOr_fields,
  82246         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82247         SOC_RESET_MASK_DEC(0x7ffff7ff, 0x00000000)
  82248         -1,
  82249         -1,
  82250     },
  82251 #endif /* chips */
  82252 
  82253 #if defined(BCM_88790_A0)
  82254     { /* SOC_REG_INT_BRDC_QRH_DRH_WFQ_CONFIGURATIONSr */
  82255         soc_block_list[111],
  82256         soc_genreg,
  82257         1,
  82258         0,
  82259         0x141,
  82260         SOC_REG_FLAG_ABOVE_64_BITS,
  82261         0,
  82262         10,
  82263         soc_BRDC_QRH_DRH_WFQ_CONFIGURATIONSr_fields,
  82264         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82265         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  82266         -1,
  82267         -1,
  82268     },
  82269 #endif /* chips */
  82270 
  82271 #if defined(BCM_88790_A0)
  82272     { /* SOC_REG_INT_BRDC_QRH_DYN_PIPES_WEIGHTS_REGISTERr */
  82273         soc_block_list[111],
  82274         soc_genreg,
  82275         1,
  82276         0,
  82277         0x146,
  82278         0,
  82279         0,
  82280         5,
  82281         soc_BRDC_QRH_DYN_PIPES_WEIGHTS_REGISTERr_fields,
  82282         SOC_RESET_VAL_DEC(0x81010101, 0x00000000)
  82283         SOC_RESET_MASK_DEC(0xff7f7f7f, 0x00000000)
  82284         -1,
  82285         -1,
  82286     },
  82287 #endif /* chips */
  82288 
  82289 #if defined(BCM_88790_A0)
  82290     { /* SOC_REG_INT_BRDC_QRH_ECC_1B_ERR_CNTr */
  82291         soc_block_list[111],
  82292         soc_genreg,
  82293         1,
  82294         0,
  82295         0x94,
  82296         SOC_REG_FLAG_64_BITS |
  82297                           SOC_REG_FLAG_RO,
  82298         SOC_REG_FLAG_COUNTER_FEILDS,
  82299         4,
  82300         soc_BRDC_QRH_ECC_1B_ERR_CNTr_fields,
  82301         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82302         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  82303         -1,
  82304         -1,
  82305     },
  82306 #endif /* chips */
  82307 
  82308 #if defined(BCM_88790_A0)
  82309     { /* SOC_REG_INT_BRDC_QRH_ECC_2B_ERR_CNTr */
  82310         soc_block_list[111],
  82311         soc_genreg,
  82312         1,
  82313         0,
  82314         0x96,
  82315         SOC_REG_FLAG_64_BITS |
  82316                           SOC_REG_FLAG_RO,
  82317         SOC_REG_FLAG_COUNTER_FEILDS,
  82318         4,
  82319         soc_BRDC_QRH_ECC_2B_ERR_CNTr_fields,
  82320         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82321         SOC_RESET_MASK_DEC(0xffffffff, 0x0000ffff)
  82322         -1,
  82323         -1,
  82324     },
  82325 #endif /* chips */
  82326 
  82327 #if defined(BCM_88790_A0)
  82328     { /* SOC_REG_INT_BRDC_QRH_ECC_ERR_1B_INITIATEr */
  82329         soc_block_list[111],
  82330         soc_genreg,
  82331         1,
  82332         0,
  82333         0xa4,
  82334         0,
  82335         0,
  82336         30,
  82337         soc_BRDC_QRH_ECC_ERR_1B_INITIATEr_fields,
  82338         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82339         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
  82340         -1,
  82341         -1,
  82342     },
  82343 #endif /* chips */
  82344 
  82345 #if defined(BCM_88790_A0)
  82346     { /* SOC_REG_INT_BRDC_QRH_ECC_ERR_1B_MONITOR_MEM_MASKr */
  82347         soc_block_list[111],
  82348         soc_genreg,
  82349         1,
  82350         0,
  82351         0x9a,
  82352         0,
  82353         0,
  82354         30,
  82355         soc_BRDC_QRH_ECC_ERR_1B_MONITOR_MEM_MASKr_fields,
  82356         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82357         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
  82358         -1,
  82359         -1,
  82360     },
  82361 #endif /* chips */
  82362 
  82363 #if defined(BCM_88790_A0)
  82364     { /* SOC_REG_INT_BRDC_QRH_ECC_ERR_2B_INITIATEr */
  82365         soc_block_list[111],
  82366         soc_genreg,
  82367         1,
  82368         0,
  82369         0xa6,
  82370         0,
  82371         0,
  82372         30,
  82373         soc_BRDC_QRH_ECC_ERR_2B_INITIATEr_fields,
  82374         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82375         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
  82376         -1,
  82377         -1,
  82378     },
  82379 #endif /* chips */
  82380 
  82381 #if defined(BCM_88790_A0)
  82382     { /* SOC_REG_INT_BRDC_QRH_ECC_ERR_2B_MONITOR_MEM_MASKr */
  82383         soc_block_list[111],
  82384         soc_genreg,
  82385         1,
  82386         0,
  82387         0x9c,
  82388         0,
  82389         0,
  82390         30,
  82391         soc_BRDC_QRH_ECC_ERR_2B_MONITOR_MEM_MASKr_fields,
  82392         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82393         SOC_RESET_MASK_DEC(0xfffff3ff, 0x00000000)
  82394         -1,
  82395         -1,
  82396     },
  82397 #endif /* chips */
  82398 
  82399 #if defined(BCM_88790_A0)
  82400     { /* SOC_REG_INT_BRDC_QRH_ECC_INTERRUPT_REGISTERr */
  82401         soc_block_list[111],
  82402         soc_genreg,
  82403         1,
  82404         0,
  82405         0x7,
  82406         SOC_REG_FLAG_INTERRUPT |
  82407                           SOC_REG_FLAG_SIGNAL,
  82408         0,
  82409         3,
  82410         soc_BRDC_QRH_ECC_INTERRUPT_REGISTERr_fields,
  82411         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82412         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82413         -1,
  82414         -1,
  82415     },
  82416 #endif /* chips */
  82417 
  82418 #if defined(BCM_88790_A0)
  82419     { /* SOC_REG_INT_BRDC_QRH_ECC_INTERRUPT_REGISTER_MASKr */
  82420         soc_block_list[111],
  82421         soc_genreg,
  82422         1,
  82423         0,
  82424         0x17,
  82425         0,
  82426         0,
  82427         3,
  82428         soc_BRDC_QRH_ECC_INTERRUPT_REGISTER_MASKr_fields,
  82429         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82430         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82431         -1,
  82432         -1,
  82433     },
  82434 #endif /* chips */
  82435 
  82436 #if defined(BCM_88790_A0)
  82437     { /* SOC_REG_INT_BRDC_QRH_ECC_INTERRUPT_REGISTER_TESTr */
  82438         soc_block_list[111],
  82439         soc_genreg,
  82440         1,
  82441         0,
  82442         0x1f,
  82443         0,
  82444         0,
  82445         1,
  82446         soc_BRDC_QRH_ECC_INTERRUPT_REGISTER_TESTr_fields,
  82447         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82448         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82449         -1,
  82450         -1,
  82451     },
  82452 #endif /* chips */
  82453 
  82454 #if defined(BCM_88790_A0)
  82455     { /* SOC_REG_INT_BRDC_QRH_ENABLE_DYNAMIC_MEMORY_ACCESSr */
  82456         soc_block_list[111],
  82457         soc_genreg,
  82458         1,
  82459         0,
  82460         0x84,
  82461         0,
  82462         0,
  82463         1,
  82464         soc_BRDC_QRH_ENABLE_DYNAMIC_MEMORY_ACCESSr_fields,
  82465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82466         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82467         -1,
  82468         -1,
  82469     },
  82470 #endif /* chips */
  82471 
  82472 #if defined(BCM_88790_A0)
  82473     { /* SOC_REG_INT_BRDC_QRH_ERROR_INITIATION_DATAr */
  82474         soc_block_list[111],
  82475         soc_genreg,
  82476         1,
  82477         0,
  82478         0xa3,
  82479         0,
  82480         0,
  82481         1,
  82482         soc_BRDC_QRH_ERROR_INITIATION_DATAr_fields,
  82483         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82484         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82485         -1,
  82486         -1,
  82487     },
  82488 #endif /* chips */
  82489 
  82490 #if defined(BCM_88790_A0)
  82491     { /* SOC_REG_INT_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_1r */
  82492         soc_block_list[111],
  82493         soc_genreg,
  82494         1,
  82495         0,
  82496         0xf6,
  82497         0,
  82498         0,
  82499         4,
  82500         soc_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_1r_fields,
  82501         SOC_RESET_VAL_DEC(0x007f97f8, 0x00000000)
  82502         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  82503         -1,
  82504         -1,
  82505     },
  82506 #endif /* chips */
  82507 
  82508 #if defined(BCM_88790_A0)
  82509     { /* SOC_REG_INT_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_2r */
  82510         soc_block_list[111],
  82511         soc_genreg,
  82512         1,
  82513         0,
  82514         0xf7,
  82515         0,
  82516         0,
  82517         4,
  82518         soc_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_2r_fields,
  82519         SOC_RESET_VAL_DEC(0x007fb7fa, 0x00000000)
  82520         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  82521         -1,
  82522         -1,
  82523     },
  82524 #endif /* chips */
  82525 
  82526 #if defined(BCM_88790_A0)
  82527     { /* SOC_REG_INT_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_3r */
  82528         soc_block_list[111],
  82529         soc_genreg,
  82530         1,
  82531         0,
  82532         0xf8,
  82533         0,
  82534         0,
  82535         4,
  82536         soc_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_3r_fields,
  82537         SOC_RESET_VAL_DEC(0x007fd7fc, 0x00000000)
  82538         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  82539         -1,
  82540         -1,
  82541     },
  82542 #endif /* chips */
  82543 
  82544 #if defined(BCM_88790_A0)
  82545     { /* SOC_REG_INT_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_4r */
  82546         soc_block_list[111],
  82547         soc_genreg,
  82548         1,
  82549         0,
  82550         0xf9,
  82551         0,
  82552         0,
  82553         4,
  82554         soc_BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_4r_fields,
  82555         SOC_RESET_VAL_DEC(0x007ff7fe, 0x00000000)
  82556         SOC_RESET_MASK_DEC(0x00ffffff, 0x00000000)
  82557         -1,
  82558         -1,
  82559     },
  82560 #endif /* chips */
  82561 
  82562 #if defined(BCM_88790_A0)
  82563     { /* SOC_REG_INT_BRDC_QRH_FE_GLOBAL_GENERAL_CFG_1r */
  82564         soc_block_list[111],
  82565         soc_genreg,
  82566         1,
  82567         0,
  82568         0xf4,
  82569         0,
  82570         0,
  82571         4,
  82572         soc_BRDC_QRH_FE_GLOBAL_GENERAL_CFG_1r_fields,
  82573         SOC_RESET_VAL_DEC(0x0000000c, 0x00000000)
  82574         SOC_RESET_MASK_DEC(0x0000000f, 0x00000000)
  82575         -1,
  82576         -1,
  82577     },
  82578 #endif /* chips */
  82579 
  82580 #if defined(BCM_88790_A0)
  82581     { /* SOC_REG_INT_BRDC_QRH_FE_GROUP_DEST_IDr */
  82582         soc_block_list[111],
  82583         soc_genreg,
  82584         8,
  82585         0,
  82586         0x147,
  82587         SOC_REG_FLAG_ARRAY |
  82588                           SOC_REG_FLAG_REG_ARRAY,
  82589         0,
  82590         2,
  82591         soc_BRDC_QRH_FE_GROUP_DEST_IDr_fields,
  82592         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82593         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  82594         -1,
  82595         -1,
  82596     },
  82597 #endif /* chips */
  82598 
  82599 #if defined(BCM_88790_A0)
  82600     { /* SOC_REG_INT_BRDC_QRH_GLOBAL_MEM_OPTIONSr */
  82601         soc_block_list[111],
  82602         soc_genreg,
  82603         1,
  82604         0,
  82605         0xc2,
  82606         0,
  82607         0,
  82608         6,
  82609         soc_BRDC_QRH_GLOBAL_MEM_OPTIONSr_fields,
  82610         SOC_RESET_VAL_DEC(0x00000030, 0x00000000)
  82611         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  82612         -1,
  82613         -1,
  82614     },
  82615 #endif /* chips */
  82616 
  82617 #if defined(BCM_88790_A0)
  82618     { /* SOC_REG_INT_BRDC_QRH_GTIMER_CONFIGURATIONr */
  82619         soc_block_list[111],
  82620         soc_genreg,
  82621         1,
  82622         0,
  82623         0x89,
  82624         0,
  82625         0,
  82626         3,
  82627         soc_BRDC_QRH_GTIMER_CONFIGURATIONr_fields,
  82628         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82629         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82630         -1,
  82631         -1,
  82632     },
  82633 #endif /* chips */
  82634 
  82635 #if defined(BCM_88790_A0)
  82636     { /* SOC_REG_INT_BRDC_QRH_GTIMER_CYCLEr */
  82637         soc_block_list[111],
  82638         soc_genreg,
  82639         1,
  82640         0,
  82641         0x88,
  82642         0,
  82643         0,
  82644         1,
  82645         soc_BRDC_QRH_GTIMER_CYCLEr_fields,
  82646         SOC_RESET_VAL_DEC(0x2aea5400, 0x00000000)
  82647         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82648         -1,
  82649         -1,
  82650     },
  82651 #endif /* chips */
  82652 
  82653 #if defined(BCM_88790_A0)
  82654     { /* SOC_REG_INT_BRDC_QRH_INDIRECT_COMMANDr */
  82655         soc_block_list[111],
  82656         soc_genreg,
  82657         1,
  82658         0,
  82659         0x80,
  82660         0,
  82661         0,
  82662         5,
  82663         soc_BRDC_QRH_INDIRECT_COMMANDr_fields,
  82664         SOC_RESET_VAL_DEC(0x00100000, 0x00000000)
  82665         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82666         -1,
  82667         -1,
  82668     },
  82669 #endif /* chips */
  82670 
  82671 #if defined(BCM_88790_A0)
  82672     { /* SOC_REG_INT_BRDC_QRH_INDIRECT_COMMAND_ADDRESSr */
  82673         soc_block_list[111],
  82674         soc_genreg,
  82675         1,
  82676         0,
  82677         0x81,
  82678         0,
  82679         0,
  82680         2,
  82681         soc_BRDC_QRH_INDIRECT_COMMAND_ADDRESSr_fields,
  82682         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82684         -1,
  82685         -1,
  82686     },
  82687 #endif /* chips */
  82688 
  82689 #if defined(BCM_88790_A0)
  82690     { /* SOC_REG_INT_BRDC_QRH_INDIRECT_COMMAND_DATA_INCREMENTr */
  82691         soc_block_list[111],
  82692         soc_genreg,
  82693         1,
  82694         0,
  82695         0x82,
  82696         SOC_REG_FLAG_64_BITS,
  82697         0,
  82698         1,
  82699         soc_BRDC_QRH_INDIRECT_COMMAND_DATA_INCREMENTr_fields,
  82700         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82701         SOC_RESET_MASK_DEC(0xffffffff, 0xffffffff)
  82702         -1,
  82703         -1,
  82704     },
  82705 #endif /* chips */
  82706 
  82707 #if defined(BCM_88790_A0)
  82708     { /* SOC_REG_INT_BRDC_QRH_INDIRECT_COMMAND_RD_DATAr */
  82709         soc_block_list[111],
  82710         soc_genreg,
  82711         1,
  82712         0,
  82713         0x60,
  82714         SOC_REG_FLAG_ABOVE_64_BITS |
  82715                           SOC_REG_FLAG_RO |
  82716                           SOC_REG_FLAG_SIGNAL,
  82717         0,
  82718         1,
  82719         soc_BRDC_QRH_INDIRECT_COMMAND_RD_DATAr_fields,
  82720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82721         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  82722         -1,
  82723         -1,
  82724     },
  82725 #endif /* chips */
  82726 
  82727 #if defined(BCM_88790_A0)
  82728     { /* SOC_REG_INT_BRDC_QRH_INDIRECT_COMMAND_WIDE_MEMr */
  82729         soc_block_list[111],
  82730         soc_genreg,
  82731         1,
  82732         0,
  82733         0x41,
  82734         0,
  82735         0,
  82736         1,
  82737         soc_BRDC_QRH_INDIRECT_COMMAND_WIDE_MEMr_fields,
  82738         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82739         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  82740         -1,
  82741         -1,
  82742     },
  82743 #endif /* chips */
  82744 
  82745 #if defined(BCM_88790_A0)
  82746     { /* SOC_REG_INT_BRDC_QRH_INDIRECT_COMMAND_WR_DATAr */
  82747         soc_block_list[111],
  82748         soc_genreg,
  82749         1,
  82750         0,
  82751         0x20,
  82752         SOC_REG_FLAG_ABOVE_64_BITS,
  82753         0,
  82754         1,
  82755         soc_BRDC_QRH_INDIRECT_COMMAND_WR_DATAr_fields,
  82756         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82757         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  82758         -1,
  82759         -1,
  82760     },
  82761 #endif /* chips */
  82762 
  82763 #if defined(BCM_88790_A0)
  82764     { /* SOC_REG_INT_BRDC_QRH_INDIRECT_FORCE_BUBBLEr */
  82765         soc_block_list[111],
  82766         soc_genreg,
  82767         1,
  82768         0,
  82769         0x83,
  82770         0,
  82771         0,
  82772         4,
  82773         soc_BRDC_QRH_INDIRECT_FORCE_BUBBLEr_fields,
  82774         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82775         SOC_RESET_MASK_DEC(0x0007ffff, 0x00000000)
  82776         -1,
  82777         -1,
  82778     },
  82779 #endif /* chips */
  82780 
  82781 #if defined(BCM_88790_A0)
  82782     { /* SOC_REG_INT_BRDC_QRH_INTERRUPT_MASK_REGISTERr */
  82783         soc_block_list[111],
  82784         soc_genreg,
  82785         1,
  82786         0,
  82787         0x10,
  82788         0,
  82789         0,
  82790         3,
  82791         soc_BRDC_QRH_INTERRUPT_MASK_REGISTERr_fields,
  82792         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82793         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82794         -1,
  82795         -1,
  82796     },
  82797 #endif /* chips */
  82798 
  82799 #if defined(BCM_88790_A0)
  82800     { /* SOC_REG_INT_BRDC_QRH_INTERRUPT_REGISTERr */
  82801         soc_block_list[111],
  82802         soc_genreg,
  82803         1,
  82804         0,
  82805         0,
  82806         SOC_REG_FLAG_RO |
  82807                           SOC_REG_FLAG_INTERRUPT |
  82808                           SOC_REG_FLAG_SIGNAL,
  82809         0,
  82810         3,
  82811         soc_BRDC_QRH_INTERRUPT_REGISTERr_fields,
  82812         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82813         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82814         -1,
  82815         -1,
  82816     },
  82817 #endif /* chips */
  82818 
  82819 #if defined(BCM_88790_A0)
  82820     { /* SOC_REG_INT_BRDC_QRH_INTERRUPT_REGISTER_TESTr */
  82821         soc_block_list[111],
  82822         soc_genreg,
  82823         1,
  82824         0,
  82825         0x18,
  82826         0,
  82827         0,
  82828         1,
  82829         soc_BRDC_QRH_INTERRUPT_REGISTER_TESTr_fields,
  82830         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82831         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82832         -1,
  82833         -1,
  82834     },
  82835 #endif /* chips */
  82836 
  82837 #if defined(BCM_88790_A0)
  82838     { /* SOC_REG_INT_BRDC_QRH_LCM_FC_CONFIGr */
  82839         soc_block_list[111],
  82840         soc_genreg,
  82841         1,
  82842         0,
  82843         0x14f,
  82844         0,
  82845         0,
  82846         1,
  82847         soc_BRDC_QRH_LCM_FC_CONFIGr_fields,
  82848         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82849         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  82850         -1,
  82851         -1,
  82852     },
  82853 #endif /* chips */
  82854 
  82855 #if defined(BCM_88790_A0)
  82856     { /* SOC_REG_INT_BRDC_QRH_LOAD_BALANCE_MAX_DEBUG_LINK_Pr */
  82857         soc_block_list[111],
  82858         soc_genreg,
  82859         3,
  82860         0,
  82861         0x157,
  82862         SOC_REG_FLAG_ARRAY |
  82863                           SOC_REG_FLAG_REG_ARRAY,
  82864         0,
  82865         2,
  82866         soc_BRDC_QRH_LOAD_BALANCE_MAX_DEBUG_LINK_Pr_fields,
  82867         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82868         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  82869         -1,
  82870         -1,
  82871     },
  82872 #endif /* chips */
  82873 
  82874 #if defined(BCM_88790_A0)
  82875     { /* SOC_REG_INT_BRDC_QRH_LOAD_BALANCE_MAX_LEVEL_Pr */
  82876         soc_block_list[111],
  82877         soc_genreg,
  82878         3,
  82879         0,
  82880         0x154,
  82881         SOC_REG_FLAG_ARRAY |
  82882                           SOC_REG_FLAG_RO |
  82883                           SOC_REG_FLAG_REG_ARRAY,
  82884         0,
  82885         2,
  82886         soc_BRDC_QRH_LOAD_BALANCE_MAX_LEVEL_Pr_fields,
  82887         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82888         SOC_RESET_MASK_DEC(0x0001ffff, 0x00000000)
  82889         -1,
  82890         -1,
  82891     },
  82892 #endif /* chips */
  82893 
  82894 #if defined(BCM_88790_A0)
  82895     { /* SOC_REG_INT_BRDC_QRH_LOCAL_ROUTE_CONFIGURATIONSr */
  82896         soc_block_list[111],
  82897         soc_genreg,
  82898         1,
  82899         0,
  82900         0x13d,
  82901         0,
  82902         0,
  82903         5,
  82904         soc_BRDC_QRH_LOCAL_ROUTE_CONFIGURATIONSr_fields,
  82905         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82906         SOC_RESET_MASK_DEC(0x000003f6, 0x00000000)
  82907         -1,
  82908         -1,
  82909     },
  82910 #endif /* chips */
  82911 
  82912 #if defined(BCM_88790_A0)
  82913     { /* SOC_REG_INT_BRDC_QRH_LOW_PR_MULTHr */
  82914         soc_block_list[111],
  82915         soc_genreg,
  82916         1,
  82917         0,
  82918         0x123,
  82919         SOC_REG_FLAG_64_BITS,
  82920         0,
  82921         3,
  82922         soc_BRDC_QRH_LOW_PR_MULTHr_fields,
  82923         SOC_RESET_VAL_DEC(0x08000200, 0x00000000)
  82924         SOC_RESET_MASK_DEC(0xffffffff, 0x000003ff)
  82925         -1,
  82926         -1,
  82927     },
  82928 #endif /* chips */
  82929 
  82930 #if defined(BCM_88790_A0)
  82931     { /* SOC_REG_INT_BRDC_QRH_LOW_PR_MUL_CTRLr */
  82932         soc_block_list[111],
  82933         soc_genreg,
  82934         1,
  82935         0,
  82936         0x122,
  82937         0,
  82938         0,
  82939         7,
  82940         soc_BRDC_QRH_LOW_PR_MUL_CTRLr_fields,
  82941         SOC_RESET_VAL_DEC(0x00000500, 0x00000000)
  82942         SOC_RESET_MASK_DEC(0x0ffffff7, 0x00000000)
  82943         -1,
  82944         -1,
  82945     },
  82946 #endif /* chips */
  82947 
  82948 #if defined(BCM_88790_A0)
  82949     { /* SOC_REG_INT_BRDC_QRH_MASK_FC_AGING_PERIODr */
  82950         soc_block_list[111],
  82951         soc_genreg,
  82952         1,
  82953         0,
  82954         0x150,
  82955         0,
  82956         0,
  82957         1,
  82958         soc_BRDC_QRH_MASK_FC_AGING_PERIODr_fields,
  82959         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82960         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  82961         -1,
  82962         -1,
  82963     },
  82964 #endif /* chips */
  82965 
  82966 #if defined(BCM_88790_A0)
  82967     { /* SOC_REG_INT_BRDC_QRH_MULICAST_ALLOWED_LINKS_REGISTERr */
  82968         soc_block_list[111],
  82969         soc_genreg,
  82970         1,
  82971         0,
  82972         0x11b,
  82973         SOC_REG_FLAG_ABOVE_64_BITS,
  82974         0,
  82975         1,
  82976         soc_BRDC_QRH_MULICAST_ALLOWED_LINKS_REGISTERr_fields,
  82977         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  82978         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  82979         -1,
  82980         -1,
  82981     },
  82982 #endif /* chips */
  82983 
  82984 #if defined(BCM_88790_A0)
  82985     { /* SOC_REG_INT_BRDC_QRH_MULTICAST_MODE_SELECTIONr */
  82986         soc_block_list[111],
  82987         soc_genreg,
  82988         1,
  82989         0,
  82990         0x108,
  82991         0,
  82992         0,
  82993         4,
  82994         soc_BRDC_QRH_MULTICAST_MODE_SELECTIONr_fields,
  82995         SOC_RESET_VAL_DEC(0x00000101, 0x00000000)
  82996         SOC_RESET_MASK_DEC(0x001fff01, 0x00000000)
  82997         -1,
  82998         -1,
  82999     },
  83000 #endif /* chips */
  83001 
  83002 #if defined(BCM_88790_A0)
  83003     { /* SOC_REG_INT_BRDC_QRH_PIPES_WEIGHTS_COUNTER_0r */
  83004         soc_block_list[111],
  83005         soc_genreg,
  83006         1,
  83007         0,
  83008         0x143,
  83009         SOC_REG_FLAG_RO,
  83010         0,
  83011         1,
  83012         soc_BRDC_QRH_PIPES_WEIGHTS_COUNTER_0r_fields,
  83013         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83014         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  83015         -1,
  83016         -1,
  83017     },
  83018 #endif /* chips */
  83019 
  83020 #if defined(BCM_88790_A0)
  83021     { /* SOC_REG_INT_BRDC_QRH_PIPES_WEIGHTS_COUNTER_1r */
  83022         soc_block_list[111],
  83023         soc_genreg,
  83024         1,
  83025         0,
  83026         0x144,
  83027         SOC_REG_FLAG_RO,
  83028         0,
  83029         1,
  83030         soc_BRDC_QRH_PIPES_WEIGHTS_COUNTER_1r_fields,
  83031         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83032         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  83033         -1,
  83034         -1,
  83035     },
  83036 #endif /* chips */
  83037 
  83038 #if defined(BCM_88790_A0)
  83039     { /* SOC_REG_INT_BRDC_QRH_PIPES_WEIGHTS_COUNTER_2r */
  83040         soc_block_list[111],
  83041         soc_genreg,
  83042         1,
  83043         0,
  83044         0x145,
  83045         SOC_REG_FLAG_RO,
  83046         0,
  83047         1,
  83048         soc_BRDC_QRH_PIPES_WEIGHTS_COUNTER_2r_fields,
  83049         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83050         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  83051         -1,
  83052         -1,
  83053     },
  83054 #endif /* chips */
  83055 
  83056 #if defined(BCM_88790_A0)
  83057     { /* SOC_REG_INT_BRDC_QRH_REACHABILITY_MESSAGE_GENERATOR_CONFIGURATIONr */
  83058         soc_block_list[111],
  83059         soc_genreg,
  83060         1,
  83061         0,
  83062         0x106,
  83063         0,
  83064         0,
  83065         2,
  83066         soc_BRDC_QRH_REACHABILITY_MESSAGE_GENERATOR_CONFIGURATIONr_fields,
  83067         SOC_RESET_VAL_DEC(0x000007ff, 0x00000000)
  83068         SOC_RESET_MASK_DEC(0x00000fff, 0x00000000)
  83069         -1,
  83070         -1,
  83071     },
  83072 #endif /* chips */
  83073 
  83074 #if defined(BCM_88790_A0)
  83075     { /* SOC_REG_INT_BRDC_QRH_RESERVED_MIRROR_ADDRr */
  83076         soc_block_list[111],
  83077         soc_genreg,
  83078         1,
  83079         0,
  83080         0x85,
  83081         0,
  83082         0,
  83083         2,
  83084         soc_BRDC_QRH_RESERVED_MIRROR_ADDRr_fields,
  83085         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83086         SOC_RESET_MASK_DEC(0x8000ffff, 0x00000000)
  83087         -1,
  83088         -1,
  83089     },
  83090 #endif /* chips */
  83091 
  83092 #if defined(BCM_88790_A0)
  83093     { /* SOC_REG_INT_BRDC_QRH_RESERVED_MTCDr */
  83094         soc_block_list[111],
  83095         soc_genreg,
  83096         1,
  83097         0,
  83098         0xae,
  83099         0,
  83100         0,
  83101         6,
  83102         soc_BRDC_QRH_RESERVED_MTCDr_fields,
  83103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83104         SOC_RESET_MASK_DEC(0x0000003f, 0x00000000)
  83105         -1,
  83106         -1,
  83107     },
  83108 #endif /* chips */
  83109 
  83110 #if defined(BCM_88790_A0)
  83111     { /* SOC_REG_INT_BRDC_QRH_RESERVED_MTCPr */
  83112         soc_block_list[111],
  83113         soc_genreg,
  83114         1,
  83115         0,
  83116         0xad,
  83117         SOC_REG_FLAG_64_BITS,
  83118         0,
  83119         17,
  83120         soc_BRDC_QRH_RESERVED_MTCPr_fields,
  83121         SOC_RESET_VAL_DEC(0x00000000, 0x03000006)
  83122         SOC_RESET_MASK_DEC(0xfff9ffff, 0x07ffffef)
  83123         -1,
  83124         -1,
  83125     },
  83126 #endif /* chips */
  83127 
  83128 #if defined(BCM_88790_A0)
  83129     { /* SOC_REG_INT_BRDC_QRH_RESERVED_SPARE_0r */
  83130         soc_block_list[111],
  83131         soc_genreg,
  83132         1,
  83133         0,
  83134         0x90,
  83135         0,
  83136         0,
  83137         1,
  83138         soc_BRDC_QRH_RESERVED_SPARE_0r_fields,
  83139         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  83140         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83141         -1,
  83142         -1,
  83143     },
  83144 #endif /* chips */
  83145 
  83146 #if defined(BCM_88790_A0)
  83147     { /* SOC_REG_INT_BRDC_QRH_RESERVED_SPARE_1r */
  83148         soc_block_list[111],
  83149         soc_genreg,
  83150         1,
  83151         0,
  83152         0x91,
  83153         0,
  83154         0,
  83155         1,
  83156         soc_BRDC_QRH_RESERVED_SPARE_1r_fields,
  83157         SOC_RESET_VAL_DEC(0xffffffff, 0x00000000)
  83158         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83159         -1,
  83160         -1,
  83161     },
  83162 #endif /* chips */
  83163 
  83164 #if defined(BCM_88790_A0)
  83165     { /* SOC_REG_INT_BRDC_QRH_RESERVED_SPARE_2r */
  83166         soc_block_list[111],
  83167         soc_genreg,
  83168         1,
  83169         0,
  83170         0x92,
  83171         0,
  83172         0,
  83173         1,
  83174         soc_BRDC_QRH_RESERVED_SPARE_2r_fields,
  83175         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83176         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83177         -1,
  83178         -1,
  83179     },
  83180 #endif /* chips */
  83181 
  83182 #if defined(BCM_88790_A0)
  83183     { /* SOC_REG_INT_BRDC_QRH_RESERVED_SPARE_3r */
  83184         soc_block_list[111],
  83185         soc_genreg,
  83186         1,
  83187         0,
  83188         0x93,
  83189         0,
  83190         0,
  83191         1,
  83192         soc_BRDC_QRH_RESERVED_SPARE_3r_fields,
  83193         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83194         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83195         -1,
  83196         -1,
  83197     },
  83198 #endif /* chips */
  83199 
  83200 #if defined(BCM_88790_A0)
  83201     { /* SOC_REG_INT_BRDC_QRH_SBUS_BROADCAST_IDr */
  83202         soc_block_list[111],
  83203         soc_genreg,
  83204         1,
  83205         0,
  83206         0x86,
  83207         0,
  83208         0,
  83209         1,
  83210         soc_BRDC_QRH_SBUS_BROADCAST_IDr_fields,
  83211         SOC_RESET_VAL_DEC(0x0000007f, 0x00000000)
  83212         SOC_RESET_MASK_DEC(0x0000007f, 0x00000000)
  83213         -1,
  83214         -1,
  83215     },
  83216 #endif /* chips */
  83217 
  83218 #if defined(BCM_88790_A0)
  83219     { /* SOC_REG_INT_BRDC_QRH_SBUS_LAST_IN_CHAINr */
  83220         soc_block_list[111],
  83221         soc_genreg,
  83222         1,
  83223         0,
  83224         0x87,
  83225         0,
  83226         0,
  83227         1,
  83228         soc_BRDC_QRH_SBUS_LAST_IN_CHAINr_fields,
  83229         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83230         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83231         -1,
  83232         -1,
  83233     },
  83234 #endif /* chips */
  83235 
  83236 #if defined(BCM_88790_A0)
  83237     { /* SOC_REG_INT_BRDC_QRH_SIMPLE_RR_LINKS_CONFIGr */
  83238         soc_block_list[111],
  83239         soc_genreg,
  83240         1,
  83241         0,
  83242         0x137,
  83243         SOC_REG_FLAG_ABOVE_64_BITS,
  83244         0,
  83245         1,
  83246         soc_BRDC_QRH_SIMPLE_RR_LINKS_CONFIGr_fields,
  83247         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83248         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83249         -1,
  83250         -1,
  83251     },
  83252 #endif /* chips */
  83253 
  83254 #if defined(BCM_56370_A0)
  83255     { /* SOC_REG_INT_BROADSCAN_LOGICAL_TABLE_SELECT_CONFIGr */
  83256         soc_block_list[5],
  83257         soc_genreg,
  83258         1,
  83259         0,
  83260         0x6a002100,
  83261         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83262         0,
  83263         1,
  83264         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIGr_fields,
  83265         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83266         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  83267         -1,
  83268         -1,
  83269         0,
  83270     },
  83271 #endif /* chips */
  83272 
  83273 #if defined(BCM_56370_A0)
  83274     { /* SOC_REG_INT_BROADSCAN_LOGICAL_TABLE_SELECT_CONFIG_PIPE0r */
  83275         soc_block_list[5],
  83276         soc_genreg,
  83277         1,
  83278         0,
  83279         0x6a002100,
  83280         0,
  83281         0,
  83282         1,
  83283         soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIGr_fields,
  83284         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83285         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  83286         -1,
  83287         -1,
  83288         0,
  83289     },
  83290 #endif /* chips */
  83291 
  83292 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83293     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
  83294     defined(BCM_56800_A0)
  83295     { /* SOC_REG_INT_BSAFE_GLB_CMD_CTRLr */
  83296         soc_block_list[7],
  83297         soc_genreg,
  83298         1,
  83299         0,
  83300         0x80214,
  83301         0,
  83302         0,
  83303         13,
  83304         soc_BSAFE_GLB_CMD_CTRLr_fields,
  83305         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83306         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83307         -1,
  83308         -1,
  83309     },
  83310 #endif /* chips */
  83311 
  83312 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83313     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
  83314     defined(BCM_56800_A0)
  83315     { /* SOC_REG_INT_BSAFE_GLB_CMD_DATA_INr */
  83316         soc_block_list[7],
  83317         soc_genreg,
  83318         1,
  83319         0,
  83320         0x80218,
  83321         0,
  83322         0,
  83323         1,
  83324         soc_BSAFE_GLB_CMD_DATA_INr_fields,
  83325         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83326         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83327         -1,
  83328         -1,
  83329     },
  83330 #endif /* chips */
  83331 
  83332 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83333     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
  83334     defined(BCM_56800_A0)
  83335     { /* SOC_REG_INT_BSAFE_GLB_CMD_DATA_OUTr */
  83336         soc_block_list[7],
  83337         soc_genreg,
  83338         1,
  83339         0,
  83340         0x8021c,
  83341         SOC_REG_FLAG_RO,
  83342         0,
  83343         1,
  83344         soc_BSAFE_GLB_CMD_DATA_OUTr_fields,
  83345         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83346         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83347         -1,
  83348         -1,
  83349     },
  83350 #endif /* chips */
  83351 
  83352 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83353     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  83354     { /* SOC_REG_INT_BSAFE_GLB_DEV_STATUSr */
  83355         soc_block_list[7],
  83356         soc_genreg,
  83357         1,
  83358         0,
  83359         0x80210,
  83360         SOC_REG_FLAG_RO,
  83361         0,
  83362         7,
  83363         soc_BSAFE_GLB_DEV_STATUSr_fields,
  83364         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83365         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83366         -1,
  83367         -1,
  83368     },
  83369 #endif /* chips */
  83370 
  83371 #if defined(BCM_56800_A0)
  83372     { /* SOC_REG_INT_BSAFE_GLB_DEV_STATUS_BCM56800_A0r */
  83373         soc_block_list[7],
  83374         soc_genreg,
  83375         1,
  83376         0,
  83377         0x80210,
  83378         SOC_REG_FLAG_RO,
  83379         0,
  83380         8,
  83381         soc_BSAFE_GLB_DEV_STATUS_BCM56800_A0r_fields,
  83382         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83383         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83384         -1,
  83385         -1,
  83386     },
  83387 #endif /* chips */
  83388 
  83389 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83390     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  83391     { /* SOC_REG_INT_BSAFE_GLB_INT_CTRLr */
  83392         soc_block_list[7],
  83393         soc_genreg,
  83394         1,
  83395         0,
  83396         0x80220,
  83397         0,
  83398         0,
  83399         8,
  83400         soc_BSAFE_GLB_INT_CTRLr_fields,
  83401         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83402         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83403         -1,
  83404         -1,
  83405     },
  83406 #endif /* chips */
  83407 
  83408 #if defined(BCM_56800_A0)
  83409     { /* SOC_REG_INT_BSAFE_GLB_INT_CTRL_BCM56800_A0r */
  83410         soc_block_list[7],
  83411         soc_genreg,
  83412         1,
  83413         0,
  83414         0x80220,
  83415         0,
  83416         0,
  83417         8,
  83418         soc_BSAFE_GLB_INT_CTRL_BCM56800_A0r_fields,
  83419         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83420         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83421         -1,
  83422         -1,
  83423     },
  83424 #endif /* chips */
  83425 
  83426 #if defined(BCM_56800_A0)
  83427     { /* SOC_REG_INT_BSAFE_GLB_MEM_PARAMr */
  83428         soc_block_list[7],
  83429         soc_genreg,
  83430         1,
  83431         0,
  83432         0x80224,
  83433         0,
  83434         0,
  83435         5,
  83436         soc_BSAFE_GLB_MEM_PARAMr_fields,
  83437         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83438         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83439         -1,
  83440         -1,
  83441     },
  83442 #endif /* chips */
  83443 
  83444 #if defined(BCM_56800_A0)
  83445     { /* SOC_REG_INT_BSAFE_GLB_MEM_TST_CTLr */
  83446         soc_block_list[7],
  83447         soc_genreg,
  83448         1,
  83449         0,
  83450         0x80228,
  83451         0,
  83452         0,
  83453         2,
  83454         soc_BSAFE_GLB_MEM_TST_CTLr_fields,
  83455         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83456         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83457         -1,
  83458         -1,
  83459     },
  83460 #endif /* chips */
  83461 
  83462 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83463     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
  83464     defined(BCM_56800_A0)
  83465     { /* SOC_REG_INT_BSAFE_GLB_PRESCALEr */
  83466         soc_block_list[7],
  83467         soc_genreg,
  83468         1,
  83469         0,
  83470         0x80204,
  83471         SOC_REG_FLAG_RO,
  83472         0,
  83473         2,
  83474         soc_BSAFE_GLB_PRESCALEr_fields,
  83475         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83476         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83477         -1,
  83478         -1,
  83479     },
  83480 #endif /* chips */
  83481 
  83482 #if defined(BCM_56504_A0) || defined(BCM_56504_B0) || \
  83483     defined(BCM_56514_A0) || defined(BCM_56800_A0)
  83484     { /* SOC_REG_INT_BSAFE_GLB_PROD_CFGr */
  83485         soc_block_list[7],
  83486         soc_genreg,
  83487         1,
  83488         0,
  83489         0x8020c,
  83490         SOC_REG_FLAG_RO,
  83491         0,
  83492         1,
  83493         soc_BSAFE_GLB_PROD_CFGr_fields,
  83494         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83495         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83496         -1,
  83497         -1,
  83498     },
  83499 #endif /* chips */
  83500 
  83501 #if defined(BCM_56314_A0)
  83502     { /* SOC_REG_INT_BSAFE_GLB_PROD_CFG_BCM56314_A0r */
  83503         soc_block_list[7],
  83504         soc_genreg,
  83505         1,
  83506         0,
  83507         0x8020c,
  83508         SOC_REG_FLAG_RO,
  83509         0,
  83510         6,
  83511         soc_BSAFE_GLB_PROD_CFG_BCM56314_A0r_fields,
  83512         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83513         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83514         -1,
  83515         -1,
  83516     },
  83517 #endif /* chips */
  83518 
  83519 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83520     defined(BCM_56504_B0) || defined(BCM_56514_A0) || \
  83521     defined(BCM_56800_A0)
  83522     { /* SOC_REG_INT_BSAFE_GLB_TIMERr */
  83523         soc_block_list[7],
  83524         soc_genreg,
  83525         1,
  83526         0,
  83527         0x80200,
  83528         SOC_REG_FLAG_RO,
  83529         0,
  83530         1,
  83531         soc_BSAFE_GLB_TIMERr_fields,
  83532         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83533         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83534         -1,
  83535         -1,
  83536     },
  83537 #endif /* chips */
  83538 
  83539 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \
  83540     defined(BCM_56504_B0) || defined(BCM_56514_A0)
  83541     { /* SOC_REG_INT_BSAFE_GLB_UHSM_CFGr */
  83542         soc_block_list[7],
  83543         soc_genreg,
  83544         1,
  83545         0,
  83546         0x80208,
  83547         SOC_REG_FLAG_RO,
  83548         0,
  83549         1,
  83550         soc_BSAFE_GLB_UHSM_CFGr_fields,
  83551         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83552         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83553         -1,
  83554         -1,
  83555     },
  83556 #endif /* chips */
  83557 
  83558 #if defined(BCM_56800_A0)
  83559     { /* SOC_REG_INT_BSAFE_GLB_UHSM_CFG_BCM56800_A0r */
  83560         soc_block_list[7],
  83561         soc_genreg,
  83562         1,
  83563         0,
  83564         0x80208,
  83565         SOC_REG_FLAG_RO,
  83566         0,
  83567         2,
  83568         soc_BSAFE_GLB_UHSM_CFG_BCM56800_A0r_fields,
  83569         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83570         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83571         -1,
  83572         -1,
  83573     },
  83574 #endif /* chips */
  83575 
  83576 #if defined(BCM_56370_A0)
  83577     { /* SOC_REG_INT_BSC_AG_DEBUG_REGISTERr */
  83578         soc_block_list[5],
  83579         soc_genreg,
  83580         1,
  83581         0,
  83582         0x8a030600,
  83583         0,
  83584         0,
  83585         4,
  83586         soc_BSC_AG_DEBUG_REGISTERr_fields,
  83587         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83588         SOC_RESET_MASK_DEC(0x1fffffff, 0x00000000)
  83589         -1,
  83590         -1,
  83591         3,
  83592     },
  83593 #endif /* chips */
  83594 
  83595 #if defined(BCM_56370_A0)
  83596     { /* SOC_REG_INT_BSC_AG_GROUP_FLUSH_CONFIG_64r */
  83597         soc_block_list[5],
  83598         soc_genreg,
  83599         1,
  83600         0,
  83601         0x8a030200,
  83602         SOC_REG_FLAG_64_BITS,
  83603         0,
  83604         9,
  83605         soc_BSC_AG_GROUP_FLUSH_CONFIG_64r_fields,
  83606         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83607         SOC_RESET_MASK_DEC(0xffffffff, 0x00001fff)
  83608         -1,
  83609         -1,
  83610         3,
  83611     },
  83612 #endif /* chips */
  83613 
  83614 #if defined(BCM_56370_A0)
  83615     { /* SOC_REG_INT_BSC_AG_PERIODIC_EXPORTr */
  83616         soc_block_list[5],
  83617         soc_genreg,
  83618         1,
  83619         0,
  83620         0x8a030700,
  83621         SOC_REG_FLAG_64_BITS,
  83622         0,
  83623         3,
  83624         soc_BSC_AG_PERIODIC_EXPORTr_fields,
  83625         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  83626         SOC_RESET_MASK_DEC(0xffffffff, 0x000001ff)
  83627         -1,
  83628         -1,
  83629         3,
  83630     },
  83631 #endif /* chips */
  83632 
  83633 #if defined(BCM_56370_A0)
  83634     { /* SOC_REG_INT_BSC_AG_RAM_CONTROLr */
  83635         soc_block_list[5],
  83636         soc_genreg,
  83637         1,
  83638         0,
  83639         0x8a030000,
  83640         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83641         0,
  83642         1,
  83643         soc_BSC_AG_RAM_CONTROLr_fields,
  83644         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83645         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83646         -1,
  83647         -1,
  83648         0,
  83649     },
  83650 #endif /* chips */
  83651 
  83652 #if defined(BCM_56370_A0)
  83653     { /* SOC_REG_INT_BSC_AG_RAM_CONTROL_PIPE0r */
  83654         soc_block_list[5],
  83655         soc_genreg,
  83656         1,
  83657         0,
  83658         0x8a030000,
  83659         0,
  83660         0,
  83661         1,
  83662         soc_BSC_AG_RAM_CONTROLr_fields,
  83663         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83664         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83665         -1,
  83666         -1,
  83667         0,
  83668     },
  83669 #endif /* chips */
  83670 
  83671 #if defined(BCM_56370_A0)
  83672     { /* SOC_REG_INT_BSC_AG_SCAN_ADDR_RANGE_CONTROLr */
  83673         soc_block_list[5],
  83674         soc_genreg,
  83675         1,
  83676         0,
  83677         0x8a030500,
  83678         0,
  83679         0,
  83680         2,
  83681         soc_BSC_AG_SCAN_ADDR_RANGE_CONTROLr_fields,
  83682         SOC_RESET_VAL_DEC(0x8fff0000, 0x00000000)
  83683         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  83684         -1,
  83685         -1,
  83686         3,
  83687     },
  83688 #endif /* chips */
  83689 
  83690 #if defined(BCM_56370_A0)
  83691     { /* SOC_REG_INT_BSC_AG_SCAN_CONTROLr */
  83692         soc_block_list[5],
  83693         soc_genreg,
  83694         1,
  83695         0,
  83696         0x8a030400,
  83697         0,
  83698         0,
  83699         1,
  83700         soc_BSC_AG_SCAN_CONTROLr_fields,
  83701         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83702         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83703         -1,
  83704         -1,
  83705         3,
  83706     },
  83707 #endif /* chips */
  83708 
  83709 #if defined(BCM_56370_A0)
  83710     { /* SOC_REG_INT_BSC_AG_SCAN_PERIOD_SELECTr */
  83711         soc_block_list[5],
  83712         soc_genreg,
  83713         1,
  83714         0,
  83715         0x8a030300,
  83716         0,
  83717         0,
  83718         1,
  83719         soc_BSC_AG_SCAN_PERIOD_SELECTr_fields,
  83720         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83721         SOC_RESET_MASK_DEC(0x00000003, 0x00000000)
  83722         -1,
  83723         -1,
  83724         3,
  83725     },
  83726 #endif /* chips */
  83727 
  83728 #if defined(BCM_56370_A0)
  83729     { /* SOC_REG_INT_BSC_AG_SER_CONTROLr */
  83730         soc_block_list[5],
  83731         soc_genreg,
  83732         1,
  83733         0,
  83734         0x8a030100,
  83735         (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83736         0,
  83737         2,
  83738         soc_BSC_AG_SER_CONTROLr_fields,
  83739         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83740         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83741         -1,
  83742         -1,
  83743         0,
  83744     },
  83745 #endif /* chips */
  83746 
  83747 #if defined(BCM_56370_A0)
  83748     { /* SOC_REG_INT_BSC_DG_RAM_CONTROL_0r */
  83749         soc_block_list[5],
  83750         soc_genreg,
  83751         1,
  83752         0,
  83753         0x8a022000,
  83754         SOC_REG_FLAG_64_BITS |
  83755                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83756         0,
  83757         12,
  83758         soc_BSC_DG_RAM_CONTROL_0r_fields,
  83759         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83760         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83761         -1,
  83762         -1,
  83763         0,
  83764     },
  83765 #endif /* chips */
  83766 
  83767 #if defined(BCM_56370_A0)
  83768     { /* SOC_REG_INT_BSC_DG_RAM_CONTROL_1r */
  83769         soc_block_list[5],
  83770         soc_genreg,
  83771         1,
  83772         0,
  83773         0x8a022100,
  83774         SOC_REG_FLAG_64_BITS |
  83775                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83776         0,
  83777         12,
  83778         soc_BSC_DG_RAM_CONTROL_1r_fields,
  83779         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83780         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83781         -1,
  83782         -1,
  83783         0,
  83784     },
  83785 #endif /* chips */
  83786 
  83787 #if defined(BCM_56370_A0)
  83788     { /* SOC_REG_INT_BSC_DG_RAM_CONTROL_2r */
  83789         soc_block_list[5],
  83790         soc_genreg,
  83791         1,
  83792         0,
  83793         0x8a022200,
  83794         SOC_REG_FLAG_64_BITS |
  83795                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  83796         0,
  83797         7,
  83798         soc_BSC_DG_RAM_CONTROL_2r_fields,
  83799         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83800         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83801         -1,
  83802         -1,
  83803         0,
  83804     },
  83805 #endif /* chips */
  83806 
  83807 #if defined(BCM_56370_A0)
  83808     { /* SOC_REG_INT_BSC_DG_RAM_CONTROL_0_PIPE0r */
  83809         soc_block_list[5],
  83810         soc_genreg,
  83811         1,
  83812         0,
  83813         0x8a022000,
  83814         SOC_REG_FLAG_64_BITS,
  83815         0,
  83816         12,
  83817         soc_BSC_DG_RAM_CONTROL_0r_fields,
  83818         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83819         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83820         -1,
  83821         -1,
  83822         0,
  83823     },
  83824 #endif /* chips */
  83825 
  83826 #if defined(BCM_56370_A0)
  83827     { /* SOC_REG_INT_BSC_DG_RAM_CONTROL_1_PIPE0r */
  83828         soc_block_list[5],
  83829         soc_genreg,
  83830         1,
  83831         0,
  83832         0x8a022100,
  83833         SOC_REG_FLAG_64_BITS,
  83834         0,
  83835         12,
  83836         soc_BSC_DG_RAM_CONTROL_1r_fields,
  83837         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83838         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83839         -1,
  83840         -1,
  83841         0,
  83842     },
  83843 #endif /* chips */
  83844 
  83845 #if defined(BCM_56370_A0)
  83846     { /* SOC_REG_INT_BSC_DG_RAM_CONTROL_2_PIPE0r */
  83847         soc_block_list[5],
  83848         soc_genreg,
  83849         1,
  83850         0,
  83851         0x8a022200,
  83852         SOC_REG_FLAG_64_BITS,
  83853         0,
  83854         7,
  83855         soc_BSC_DG_RAM_CONTROL_2r_fields,
  83856         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83857         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83858         -1,
  83859         -1,
  83860         0,
  83861     },
  83862 #endif /* chips */
  83863 
  83864 #if defined(BCM_56370_A0)
  83865     { /* SOC_REG_INT_BSC_DG_SER_CONTROLr */
  83866         soc_block_list[5],
  83867         soc_genreg,
  83868         1,
  83869         0,
  83870         0x8a022300,
  83871         SOC_REG_FLAG_64_BITS,
  83872         0,
  83873         62,
  83874         soc_BSC_DG_SER_CONTROLr_fields,
  83875         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83876         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83877         -1,
  83878         -1,
  83879         0,
  83880     },
  83881 #endif /* chips */
  83882 
  83883 #if defined(BCM_56370_A0)
  83884     { /* SOC_REG_INT_BSC_DT_PDE_RAM_CONTROLr */
  83885         soc_block_list[5],
  83886         soc_genreg,
  83887         1,
  83888         0,
  83889         0x8a018100,
  83890         0,
  83891         0,
  83892         3,
  83893         soc_BSC_DT_PDE_RAM_CONTROLr_fields,
  83894         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83895         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83896         -1,
  83897         -1,
  83898         3,
  83899     },
  83900 #endif /* chips */
  83901 
  83902 #if defined(BCM_56370_A0)
  83903     { /* SOC_REG_INT_BSC_DT_RAM_CONTROLr */
  83904         soc_block_list[5],
  83905         soc_genreg,
  83906         1,
  83907         0,
  83908         0x8a018200,
  83909         0,
  83910         0,
  83911         2,
  83912         soc_BSC_DT_RAM_CONTROLr_fields,
  83913         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83914         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83915         -1,
  83916         -1,
  83917         3,
  83918     },
  83919 #endif /* chips */
  83920 
  83921 #if defined(BCM_56370_A0)
  83922     { /* SOC_REG_INT_BSC_DT_RANDOM_SEED_CONFIGr */
  83923         soc_block_list[5],
  83924         soc_genreg,
  83925         1,
  83926         0,
  83927         0x8a018000,
  83928         0,
  83929         0,
  83930         1,
  83931         soc_HG_TRUNK_RAND_LB_SEEDr_fields,
  83932         SOC_RESET_VAL_DEC(0x00000001, 0x00000000)
  83933         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  83934         -1,
  83935         -1,
  83936         3,
  83937     },
  83938 #endif /* chips */
  83939 
  83940 #if defined(BCM_56370_A0)
  83941     { /* SOC_REG_INT_BSC_DT_SER_CONTROLr */
  83942         soc_block_list[5],
  83943         soc_genreg,
  83944         1,
  83945         0,
  83946         0x8a018300,
  83947         0,
  83948         0,
  83949         5,
  83950         soc_BSC_DT_SER_CONTROLr_fields,
  83951         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83952         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  83953         -1,
  83954         -1,
  83955         3,
  83956     },
  83957 #endif /* chips */
  83958 
  83959 #if defined(BCM_56370_A0)
  83960     { /* SOC_REG_INT_BSC_EX_BROADSCAN_GLOBAL_SER_DROP_ENABLEr */
  83961         soc_block_list[5],
  83962         soc_genreg,
  83963         1,
  83964         0,
  83965         0x8a050000,
  83966         0,
  83967         0,
  83968         1,
  83969         soc_BSC_EX_BROADSCAN_GLOBAL_SER_DROP_ENABLEr_fields,
  83970         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83971         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83972         -1,
  83973         -1,
  83974         0,
  83975     },
  83976 #endif /* chips */
  83977 
  83978 #if defined(BCM_56370_A0)
  83979     { /* SOC_REG_INT_BSC_EX_BROADSCAN_IPFIX_CREDIT_RESETr */
  83980         soc_block_list[5],
  83981         soc_genreg,
  83982         1,
  83983         0,
  83984         0x8a050100,
  83985         0,
  83986         0,
  83987         1,
  83988         soc_BSC_EX_BROADSCAN_IPFIX_CREDIT_RESETr_fields,
  83989         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  83990         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  83991         -1,
  83992         -1,
  83993         0,
  83994     },
  83995 #endif /* chips */
  83996 
  83997 #if defined(BCM_56370_A0)
  83998     { /* SOC_REG_INT_BSC_EX_EXPORT_CONTROLr */
  83999         soc_block_list[5],
  84000         soc_genreg,
  84001         1,
  84002         0,
  84003         0x8a050500,
  84004         0,
  84005         0,
  84006         3,
  84007         soc_BSC_EX_EXPORT_CONTROLr_fields,
  84008         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84009         SOC_RESET_MASK_DEC(0x0000001f, 0x00000000)
  84010         -1,
  84011         -1,
  84012         3,
  84013     },
  84014 #endif /* chips */
  84015 
  84016 #if defined(BCM_56370_A0)
  84017     { /* SOC_REG_INT_BSC_EX_EXPORT_RAM_CONTROLr */
  84018         soc_block_list[5],
  84019         soc_genreg,
  84020         1,
  84021         0,
  84022         0x8a050300,
  84023         0,
  84024         0,
  84025         1,
  84026         soc_BSC_EX_EXPORT_RAM_CONTROLr_fields,
  84027         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84028         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84029         -1,
  84030         -1,
  84031         0,
  84032     },
  84033 #endif /* chips */
  84034 
  84035 #if defined(BCM_56370_A0)
  84036     { /* SOC_REG_INT_BSC_EX_EXPORT_SET_LENGTHr */
  84037         soc_block_list[5],
  84038         soc_genreg,
  84039         1,
  84040         0,
  84041         0x8a050400,
  84042         0,
  84043         0,
  84044         1,
  84045         soc_BSC_EX_EXPORT_SET_LENGTHr_fields,
  84046         SOC_RESET_VAL_DEC(0x00000080, 0x00000000)
  84047         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  84048         -1,
  84049         -1,
  84050         3,
  84051     },
  84052 #endif /* chips */
  84053 
  84054 #if defined(BCM_56370_A0)
  84055     { /* SOC_REG_INT_BSC_EX_GLOBAL_EVENT_VECTOR_CONTROL_ON_SERr */
  84056         soc_block_list[5],
  84057         soc_genreg,
  84058         1,
  84059         0,
  84060         0x8a050200,
  84061         0,
  84062         0,
  84063         1,
  84064         soc_BSC_EX_GLOBAL_EVENT_VECTOR_CONTROL_ON_SERr_fields,
  84065         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84066         SOC_RESET_MASK_DEC(0x00000001, 0x00000000)
  84067         -1,
  84068         -1,
  84069         0,
  84070     },
  84071 #endif /* chips */
  84072 
  84073 #if defined(BCM_56370_A0)
  84074     { /* SOC_REG_INT_BSC_EX_SEQ_NUMr */
  84075         soc_block_list[5],
  84076         soc_genreg,
  84077         8,
  84078         0,
  84079         0x8a050800,
  84080         SOC_REG_FLAG_ARRAY,
  84081         0,
  84082         1,
  84083         soc_BSC_EX_SEQ_NUMr_fields,
  84084         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84085         SOC_RESET_MASK_DEC(0xffffffff, 0x00000000)
  84086         -1,
  84087         -1,
  84088         3,
  84089     },
  84090 #endif /* chips */
  84091 
  84092 #if defined(BCM_56370_A0)
  84093     { /* SOC_REG_INT_BSC_EX_SER_CONTROLr */
  84094         soc_block_list[5],
  84095         soc_genreg,
  84096         1,
  84097         0,
  84098         0x8a050700,
  84099         0,
  84100         0,
  84101         3,
  84102         soc_BSC_EX_SER_CONTROLr_fields,
  84103         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84104         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84105         -1,
  84106         -1,
  84107         3,
  84108     },
  84109 #endif /* chips */
  84110 
  84111 #if defined(BCM_56370_A0)
  84112     { /* SOC_REG_INT_BSC_KG_RAM_CONTROLr */
  84113         soc_block_list[5],
  84114         soc_genreg,
  84115         1,
  84116         0,
  84117         0x8a020000,
  84118         SOC_REG_FLAG_64_BITS |
  84119                           (9 << SOC_REG_FLAG_ACC_TYPE_SHIFT),
  84120         0,
  84121         8,
  84122         soc_BSC_KG_RAM_CONTROLr_fields,
  84123         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84124         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84125         -1,
  84126         -1,
  84127         0,
  84128     },
  84129 #endif /* chips */
  84130 
  84131 #if defined(BCM_56370_A0)
  84132     { /* SOC_REG_INT_BSC_KG_RAM_CONTROL_PIPE0r */
  84133         soc_block_list[5],
  84134         soc_genreg,
  84135         1,
  84136         0,
  84137         0x8a020000,
  84138         SOC_REG_FLAG_64_BITS,
  84139         0,
  84140         8,
  84141         soc_BSC_KG_RAM_CONTROLr_fields,
  84142         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84143         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84144         -1,
  84145         -1,
  84146         0,
  84147     },
  84148 #endif /* chips */
  84149 
  84150 #if defined(BCM_56370_A0)
  84151     { /* SOC_REG_INT_BSC_KG_SER_CONTROLr */
  84152         soc_block_list[5],
  84153         soc_genreg,
  84154         1,
  84155         0,
  84156         0x8a020100,
  84157         0,
  84158         0,
  84159         16,
  84160         soc_BSC_KG_SER_CONTROLr_fields,
  84161         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84162         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84163         -1,
  84164         -1,
  84165         0,
  84166     },
  84167 #endif /* chips */
  84168 
  84169 #if defined(BCM_56370_A0)
  84170     { /* SOC_REG_INT_BSC_KT_KEY_SER_CONTROLr */
  84171         soc_block_list[5],
  84172         soc_genreg,
  84173         1,
  84174         0,
  84175         0x8a010200,
  84176         0,
  84177         0,
  84178         3,
  84179         soc_BSC_KT_KEY_SER_CONTROLr_fields,
  84180         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84181         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84182         -1,
  84183         -1,
  84184         0,
  84185     },
  84186 #endif /* chips */
  84187 
  84188 #if defined(BCM_56370_A0)
  84189     { /* SOC_REG_INT_BSC_KT_KEY_TABLE_RAM_CONTROL_0r */
  84190         soc_block_list[5],
  84191         soc_genreg,
  84192         1,
  84193         0,
  84194         0x8a010000,
  84195         0,
  84196         0,
  84197         2,
  84198         soc_BSC_KT_KEY_TABLE_RAM_CONTROL_0r_fields,
  84199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84200         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84201         -1,
  84202         -1,
  84203         3,
  84204     },
  84205 #endif /* chips */
  84206 
  84207 #if defined(BCM_56370_A0)
  84208     { /* SOC_REG_INT_BSC_KT_KEY_TABLE_RAM_CONTROL_1r */
  84209         soc_block_list[5],
  84210         soc_genreg,
  84211         1,
  84212         0,
  84213         0x8a010100,
  84214         SOC_REG_FLAG_64_BITS,
  84215         0,
  84216         4,
  84217         soc_BSC_KT_KEY_TABLE_RAM_CONTROL_1r_fields,
  84218         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84219         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84220         -1,
  84221         -1,
  84222         3,
  84223     },
  84224 #endif /* chips */
  84225 
  84226 #if defined(BCM_56370_A0)
  84227     { /* SOC_REG_INT_BSK_ALU_DATA_LTS_C_KEY_GEN_CAM_BIST_CONFIG_64r */
  84228         soc_block_list[5],
  84229         soc_genreg,
  84230         1,
  84231         0,
  84232         0x8a009f00,
  84233         SOC_REG_FLAG_64_BITS,
  84234         0,
  84235         6,
  84236         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84237         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84238         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84239         -1,
  84240         -1,
  84241         0,
  84242     },
  84243 #endif /* chips */
  84244 
  84245 #if defined(BCM_56370_A0)
  84246     { /* SOC_REG_INT_BSK_ALU_DATA_LTS_C_KEY_GEN_CAM_BIST_STATUSr */
  84247         soc_block_list[5],
  84248         soc_genreg,
  84249         1,
  84250         0,
  84251         0x8a009e00,
  84252         SOC_REG_FLAG_RO,
  84253         0,
  84254         1,
  84255         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84256         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84257         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84258         -1,
  84259         -1,
  84260         0,
  84261     },
  84262 #endif /* chips */
  84263 
  84264 #if defined(BCM_56370_A0)
  84265     { /* SOC_REG_INT_BSK_ALU_DATA_LTS_C_KEY_GEN_SER_CONTROLr */
  84266         soc_block_list[5],
  84267         soc_genreg,
  84268         1,
  84269         0,
  84270         0x8a009d00,
  84271         0,
  84272         0,
  84273         13,
  84274         soc_EGR_ADAPT_1_KEY_GEN_SER_CONTROLr_fields,
  84275         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84276         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84277         -1,
  84278         -1,
  84279         0,
  84280     },
  84281 #endif /* chips */
  84282 
  84283 #if defined(BCM_56370_A0)
  84284     { /* SOC_REG_INT_BSK_ALU_DATA_LTS_C_KEY_GEN_TM_CONTROL_64r */
  84285         soc_block_list[5],
  84286         soc_genreg,
  84287         1,
  84288         0,
  84289         0x8a009c00,
  84290         SOC_REG_FLAG_64_BITS,
  84291         0,
  84292         4,
  84293         soc_BSK_ALU_DATA_LTS_C_KEY_GEN_TM_CONTROL_64r_fields,
  84294         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84295         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84296         -1,
  84297         -1,
  84298         0,
  84299     },
  84300 #endif /* chips */
  84301 
  84302 #if defined(BCM_56370_A0)
  84303     { /* SOC_REG_INT_BSK_FTFP_CAM_BIST_CONFIG_64r */
  84304         soc_block_list[5],
  84305         soc_genreg,
  84306         1,
  84307         0,
  84308         0x8a008100,
  84309         SOC_REG_FLAG_64_BITS,
  84310         0,
  84311         6,
  84312         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84313         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84314         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84315         -1,
  84316         -1,
  84317         3,
  84318     },
  84319 #endif /* chips */
  84320 
  84321 #if defined(BCM_56370_A0)
  84322     { /* SOC_REG_INT_BSK_FTFP_CAM_BIST_STATUSr */
  84323         soc_block_list[5],
  84324         soc_genreg,
  84325         1,
  84326         0,
  84327         0x8a008000,
  84328         SOC_REG_FLAG_RO,
  84329         0,
  84330         1,
  84331         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84332         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84333         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84334         -1,
  84335         -1,
  84336         3,
  84337     },
  84338 #endif /* chips */
  84339 
  84340 #if defined(BCM_56370_A0)
  84341     { /* SOC_REG_INT_BSK_FTFP_CAM_CONTROLr */
  84342         soc_block_list[5],
  84343         soc_genreg,
  84344         1,
  84345         0,
  84346         0x8a008200,
  84347         0,
  84348         0,
  84349         7,
  84350         soc_BSK_FTFP_CAM_CONTROLr_fields,
  84351         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84352         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84353         -1,
  84354         -1,
  84355         3,
  84356     },
  84357 #endif /* chips */
  84358 
  84359 #if defined(BCM_56370_A0)
  84360     { /* SOC_REG_INT_BSK_FTFP_LTS_A_KEY_GEN_CAM_BIST_CONFIG_64r */
  84361         soc_block_list[5],
  84362         soc_genreg,
  84363         1,
  84364         0,
  84365         0x8a008700,
  84366         SOC_REG_FLAG_64_BITS,
  84367         0,
  84368         6,
  84369         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84370         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84371         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84372         -1,
  84373         -1,
  84374         0,
  84375     },
  84376 #endif /* chips */
  84377 
  84378 #if defined(BCM_56370_A0)
  84379     { /* SOC_REG_INT_BSK_FTFP_LTS_A_KEY_GEN_CAM_BIST_STATUSr */
  84380         soc_block_list[5],
  84381         soc_genreg,
  84382         1,
  84383         0,
  84384         0x8a008600,
  84385         SOC_REG_FLAG_RO,
  84386         0,
  84387         1,
  84388         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84389         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84390         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84391         -1,
  84392         -1,
  84393         0,
  84394     },
  84395 #endif /* chips */
  84396 
  84397 #if defined(BCM_56370_A0)
  84398     { /* SOC_REG_INT_BSK_FTFP_LTS_A_KEY_GEN_SER_CONTROLr */
  84399         soc_block_list[5],
  84400         soc_genreg,
  84401         1,
  84402         0,
  84403         0x8a008500,
  84404         0,
  84405         0,
  84406         13,
  84407         soc_EGR_ADAPT_1_KEY_GEN_SER_CONTROLr_fields,
  84408         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84409         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84410         -1,
  84411         -1,
  84412         0,
  84413     },
  84414 #endif /* chips */
  84415 
  84416 #if defined(BCM_56370_A0)
  84417     { /* SOC_REG_INT_BSK_FTFP_LTS_A_KEY_GEN_TM_CONTROL_64r */
  84418         soc_block_list[5],
  84419         soc_genreg,
  84420         1,
  84421         0,
  84422         0x8a008400,
  84423         SOC_REG_FLAG_64_BITS,
  84424         0,
  84425         5,
  84426         soc_EGR_ADAPT_1_KEY_GEN_TM_CONTROL_64r_fields,
  84427         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84428         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84429         -1,
  84430         -1,
  84431         0,
  84432     },
  84433 #endif /* chips */
  84434 
  84435 #if defined(BCM_56370_A0)
  84436     { /* SOC_REG_INT_BSK_FTFP_LTS_B_KEY_GEN_CAM_BIST_CONFIG_64r */
  84437         soc_block_list[5],
  84438         soc_genreg,
  84439         1,
  84440         0,
  84441         0x8a008b00,
  84442         SOC_REG_FLAG_64_BITS,
  84443         0,
  84444         6,
  84445         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84446         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84447         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84448         -1,
  84449         -1,
  84450         0,
  84451     },
  84452 #endif /* chips */
  84453 
  84454 #if defined(BCM_56370_A0)
  84455     { /* SOC_REG_INT_BSK_FTFP_LTS_B_KEY_GEN_CAM_BIST_STATUSr */
  84456         soc_block_list[5],
  84457         soc_genreg,
  84458         1,
  84459         0,
  84460         0x8a008a00,
  84461         SOC_REG_FLAG_RO,
  84462         0,
  84463         1,
  84464         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84465         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84466         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84467         -1,
  84468         -1,
  84469         0,
  84470     },
  84471 #endif /* chips */
  84472 
  84473 #if defined(BCM_56370_A0)
  84474     { /* SOC_REG_INT_BSK_FTFP_LTS_B_KEY_GEN_SER_CONTROLr */
  84475         soc_block_list[5],
  84476         soc_genreg,
  84477         1,
  84478         0,
  84479         0x8a008900,
  84480         0,
  84481         0,
  84482         13,
  84483         soc_EGR_ADAPT_1_KEY_GEN_SER_CONTROLr_fields,
  84484         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84485         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84486         -1,
  84487         -1,
  84488         0,
  84489     },
  84490 #endif /* chips */
  84491 
  84492 #if defined(BCM_56370_A0)
  84493     { /* SOC_REG_INT_BSK_FTFP_LTS_B_KEY_GEN_TM_CONTROL_64r */
  84494         soc_block_list[5],
  84495         soc_genreg,
  84496         1,
  84497         0,
  84498         0x8a008800,
  84499         SOC_REG_FLAG_64_BITS,
  84500         0,
  84501         4,
  84502         soc_BSK_ALU_DATA_LTS_C_KEY_GEN_TM_CONTROL_64r_fields,
  84503         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84504         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84505         -1,
  84506         -1,
  84507         0,
  84508     },
  84509 #endif /* chips */
  84510 
  84511 #if defined(BCM_56370_A0)
  84512     { /* SOC_REG_INT_BSK_FTFP_RAM_CONTROLr */
  84513         soc_block_list[5],
  84514         soc_genreg,
  84515         1,
  84516         0,
  84517         0x8a008300,
  84518         0,
  84519         0,
  84520         3,
  84521         soc_BSK_FTFP_RAM_CONTROLr_fields,
  84522         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84523         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84524         -1,
  84525         -1,
  84526         3,
  84527     },
  84528 #endif /* chips */
  84529 
  84530 #if defined(BCM_56370_A0)
  84531     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_A_KEY_GEN_CAM_BIST_CONFIG_64r */
  84532         soc_block_list[5],
  84533         soc_genreg,
  84534         1,
  84535         0,
  84536         0x8a009700,
  84537         SOC_REG_FLAG_64_BITS,
  84538         0,
  84539         6,
  84540         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84541         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84542         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84543         -1,
  84544         -1,
  84545         0,
  84546     },
  84547 #endif /* chips */
  84548 
  84549 #if defined(BCM_56370_A0)
  84550     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_A_KEY_GEN_CAM_BIST_STATUSr */
  84551         soc_block_list[5],
  84552         soc_genreg,
  84553         1,
  84554         0,
  84555         0x8a009600,
  84556         SOC_REG_FLAG_RO,
  84557         0,
  84558         1,
  84559         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84560         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84561         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84562         -1,
  84563         -1,
  84564         0,
  84565     },
  84566 #endif /* chips */
  84567 
  84568 #if defined(BCM_56370_A0)
  84569     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_A_KEY_GEN_SER_CONTROLr */
  84570         soc_block_list[5],
  84571         soc_genreg,
  84572         1,
  84573         0,
  84574         0x8a009500,
  84575         0,
  84576         0,
  84577         13,
  84578         soc_EGR_ADAPT_1_KEY_GEN_SER_CONTROLr_fields,
  84579         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84580         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84581         -1,
  84582         -1,
  84583         0,
  84584     },
  84585 #endif /* chips */
  84586 
  84587 #if defined(BCM_56370_A0)
  84588     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_A_KEY_GEN_TM_CONTROL_64r */
  84589         soc_block_list[5],
  84590         soc_genreg,
  84591         1,
  84592         0,
  84593         0x8a009400,
  84594         SOC_REG_FLAG_64_BITS,
  84595         0,
  84596         5,
  84597         soc_EGR_ADAPT_1_KEY_GEN_TM_CONTROL_64r_fields,
  84598         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84599         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84600         -1,
  84601         -1,
  84602         0,
  84603     },
  84604 #endif /* chips */
  84605 
  84606 #if defined(BCM_56370_A0)
  84607     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_B_KEY_GEN_CAM_BIST_CONFIG_64r */
  84608         soc_block_list[5],
  84609         soc_genreg,
  84610         1,
  84611         0,
  84612         0x8a009b00,
  84613         SOC_REG_FLAG_64_BITS,
  84614         0,
  84615         6,
  84616         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84617         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84618         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84619         -1,
  84620         -1,
  84621         0,
  84622     },
  84623 #endif /* chips */
  84624 
  84625 #if defined(BCM_56370_A0)
  84626     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_B_KEY_GEN_CAM_BIST_STATUSr */
  84627         soc_block_list[5],
  84628         soc_genreg,
  84629         1,
  84630         0,
  84631         0x8a009a00,
  84632         SOC_REG_FLAG_RO,
  84633         0,
  84634         1,
  84635         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84636         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84637         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84638         -1,
  84639         -1,
  84640         0,
  84641     },
  84642 #endif /* chips */
  84643 
  84644 #if defined(BCM_56370_A0)
  84645     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_B_KEY_GEN_SER_CONTROLr */
  84646         soc_block_list[5],
  84647         soc_genreg,
  84648         1,
  84649         0,
  84650         0x8a009900,
  84651         0,
  84652         0,
  84653         13,
  84654         soc_EGR_ADAPT_1_KEY_GEN_SER_CONTROLr_fields,
  84655         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84656         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84657         -1,
  84658         -1,
  84659         0,
  84660     },
  84661 #endif /* chips */
  84662 
  84663 #if defined(BCM_56370_A0)
  84664     { /* SOC_REG_INT_BSK_SESSION_DATA_LTS_B_KEY_GEN_TM_CONTROL_64r */
  84665         soc_block_list[5],
  84666         soc_genreg,
  84667         1,
  84668         0,
  84669         0x8a009800,
  84670         SOC_REG_FLAG_64_BITS,
  84671         0,
  84672         4,
  84673         soc_BSK_ALU_DATA_LTS_C_KEY_GEN_TM_CONTROL_64r_fields,
  84674         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84675         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84676         -1,
  84677         -1,
  84678         0,
  84679     },
  84680 #endif /* chips */
  84681 
  84682 #if defined(BCM_56370_A0)
  84683     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_A_KEY_GEN_CAM_BIST_CONFIG_64r */
  84684         soc_block_list[5],
  84685         soc_genreg,
  84686         1,
  84687         0,
  84688         0x8a008f00,
  84689         SOC_REG_FLAG_64_BITS,
  84690         0,
  84691         6,
  84692         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84693         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84694         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84695         -1,
  84696         -1,
  84697         0,
  84698     },
  84699 #endif /* chips */
  84700 
  84701 #if defined(BCM_56370_A0)
  84702     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_A_KEY_GEN_CAM_BIST_STATUSr */
  84703         soc_block_list[5],
  84704         soc_genreg,
  84705         1,
  84706         0,
  84707         0x8a008e00,
  84708         SOC_REG_FLAG_RO,
  84709         0,
  84710         1,
  84711         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84712         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84713         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84714         -1,
  84715         -1,
  84716         0,
  84717     },
  84718 #endif /* chips */
  84719 
  84720 #if defined(BCM_56370_A0)
  84721     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_A_KEY_GEN_SER_CONTROLr */
  84722         soc_block_list[5],
  84723         soc_genreg,
  84724         1,
  84725         0,
  84726         0x8a008d00,
  84727         0,
  84728         0,
  84729         13,
  84730         soc_EGR_ADAPT_1_KEY_GEN_SER_CONTROLr_fields,
  84731         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84732         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84733         -1,
  84734         -1,
  84735         0,
  84736     },
  84737 #endif /* chips */
  84738 
  84739 #if defined(BCM_56370_A0)
  84740     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_A_KEY_GEN_TM_CONTROL_64r */
  84741         soc_block_list[5],
  84742         soc_genreg,
  84743         1,
  84744         0,
  84745         0x8a008c00,
  84746         SOC_REG_FLAG_64_BITS,
  84747         0,
  84748         5,
  84749         soc_EGR_ADAPT_1_KEY_GEN_TM_CONTROL_64r_fields,
  84750         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84751         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84752         -1,
  84753         -1,
  84754         0,
  84755     },
  84756 #endif /* chips */
  84757 
  84758 #if defined(BCM_56370_A0)
  84759     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_B_KEY_GEN_CAM_BIST_CONFIG_64r */
  84760         soc_block_list[5],
  84761         soc_genreg,
  84762         1,
  84763         0,
  84764         0x8a009300,
  84765         SOC_REG_FLAG_64_BITS,
  84766         0,
  84767         6,
  84768         soc_CPU_COS_CAM_BIST_CONFIG_64_BCM56870_A0r_fields,
  84769         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84770         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84771         -1,
  84772         -1,
  84773         0,
  84774     },
  84775 #endif /* chips */
  84776 
  84777 #if defined(BCM_56370_A0)
  84778     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_B_KEY_GEN_CAM_BIST_STATUSr */
  84779         soc_block_list[5],
  84780         soc_genreg,
  84781         1,
  84782         0,
  84783         0x8a009200,
  84784         SOC_REG_FLAG_RO,
  84785         0,
  84786         1,
  84787         soc_EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUSr_fields,
  84788         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84789         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84790         -1,
  84791         -1,
  84792         0,
  84793     },
  84794 #endif /* chips */
  84795 
  84796 #if defined(BCM_56370_A0)
  84797     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_B_KEY_GEN_SER_CONTROLr */
  84798         soc_block_list[5],
  84799         soc_genreg,
  84800         1,
  84801         0,
  84802         0x8a009100,
  84803         0,
  84804         0,
  84805         13,
  84806         soc_EGR_ADAPT_1_KEY_GEN_SER_CONTROLr_fields,
  84807         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84808         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84809         -1,
  84810         -1,
  84811         0,
  84812     },
  84813 #endif /* chips */
  84814 
  84815 #if defined(BCM_56370_A0)
  84816     { /* SOC_REG_INT_BSK_SESSION_KEY_LTS_B_KEY_GEN_TM_CONTROL_64r */
  84817         soc_block_list[5],
  84818         soc_genreg,
  84819         1,
  84820         0,
  84821         0x8a009000,
  84822         SOC_REG_FLAG_64_BITS,
  84823         0,
  84824         4,
  84825         soc_BSK_ALU_DATA_LTS_C_KEY_GEN_TM_CONTROL_64r_fields,
  84826         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84827         SOC_RESET_MASK_DEC(0x00000000, 0x00000000)
  84828         -1,
  84829         -1,
  84830         0,
  84831     },
  84832 #endif /* chips */
  84833 
  84834 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  84835     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  84836     { /* SOC_REG_INT_BST_HW_SNAPSHOT_ENr */
  84837         soc_block_list[4],
  84838         soc_genreg,
  84839         1,
  84840         0,
  84841         0x32000900,
  84842         0,
  84843         0,
  84844         3,
  84845         soc_BST_HW_SNAPSHOT_ENr_fields,
  84846         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84847         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  84848         -1,
  84849         -1,
  84850     },
  84851 #endif /* chips */
  84852 
  84853 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84854     { /* SOC_REG_INT_BST_SNAPSHOT_ACTION_ENr */
  84855         soc_block_list[4],
  84856         soc_genreg,
  84857         1,
  84858         0,
  84859         0x32000800,
  84860         0,
  84861         0,
  84862         3,
  84863         soc_BST_SNAPSHOT_ACTION_ENr_fields,
  84864         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84865         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  84866         -1,
  84867         -1,
  84868     },
  84869 #endif /* chips */
  84870 
  84871 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  84872     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  84873     { /* SOC_REG_INT_BST_SNAPSHOT_ACTION_EN_BCM56560_A0r */
  84874         soc_block_list[4],
  84875         soc_genreg,
  84876         1,
  84877         0,
  84878         0x32000800,
  84879         0,
  84880         0,
  84881         3,
  84882         soc_BST_SNAPSHOT_ACTION_EN_BCM56560_A0r_fields,
  84883         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84884         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  84885         -1,
  84886         -1,
  84887     },
  84888 #endif /* chips */
  84889 
  84890 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \
  84891     defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84892     { /* SOC_REG_INT_BST_TRACKING_CONFIGr */
  84893         soc_block_list[4],
  84894         soc_genreg,
  84895         1,
  84896         0,
  84897         0x32000900,
  84898         0,
  84899         0,
  84900         3,
  84901         soc_BST_TRACKING_CONFIGr_fields,
  84902         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84903         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  84904         -1,
  84905         -1,
  84906     },
  84907 #endif /* chips */
  84908 
  84909 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  84910     { /* SOC_REG_INT_BST_TRACKING_ENABLEr */
  84911         soc_block_list[4],
  84912         soc_genreg,
  84913         1,
  84914         0,
  84915         0x32000800,
  84916         0,
  84917         0,
  84918         3,
  84919         soc_BST_TRACKING_ENABLEr_fields,
  84920         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84921         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  84922         -1,
  84923         -1,
  84924     },
  84925 #endif /* chips */
  84926 
  84927 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  84928     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  84929     { /* SOC_REG_INT_BST_TRACKING_ENABLE_BCM56560_A0r */
  84930         soc_block_list[4],
  84931         soc_genreg,
  84932         1,
  84933         0,
  84934         0x32000700,
  84935         0,
  84936         0,
  84937         3,
  84938         soc_BST_TRACKING_ENABLE_BCM56560_A0r_fields,
  84939         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84940         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  84941         -1,
  84942         -1,
  84943     },
  84944 #endif /* chips */
  84945 
  84946 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  84947     { /* SOC_REG_INT_BST_TRACKING_ENABLE_BCM56850_A0r */
  84948         soc_block_list[4],
  84949         soc_genreg,
  84950         1,
  84951         0,
  84952         0x32000700,
  84953         0,
  84954         0,
  84955         3,
  84956         soc_BST_TRACKING_ENABLEr_fields,
  84957         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84958         SOC_RESET_MASK_DEC(0x00000007, 0x00000000)
  84959         -1,
  84960         -1,
  84961     },
  84962 #endif /* chips */
  84963 
  84964 #if defined(BCM_88732_A0)
  84965     { /* SOC_REG_INT_BUCKET_ECCr */
  84966         soc_block_list[4],
  84967         soc_portreg,
  84968         8,
  84969         0,
  84970         0xa000038,
  84971         SOC_REG_FLAG_ARRAY,
  84972         0,
  84973         1,
  84974         soc_BUCKET_ECCr_fields,
  84975         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84976         SOC_RESET_MASK_DEC(0x000000ff, 0x00000000)
  84977         -1,
  84978         50,
  84979     },
  84980 #endif /* chips */
  84981 
  84982 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  84983     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  84984     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  84985     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SPr */
  84986         soc_block_list[4],
  84987         soc_genreg,
  84988         4,
  84989         0,
  84990         0x208010a,
  84991         SOC_REG_FLAG_ARRAY,
  84992         0,
  84993         1,
  84994         soc_BUFFER_CELL_LIMIT_SPr_fields,
  84995         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  84996         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  84997         -1,
  84998         -1,
  84999     },
  85000 #endif /* chips */
  85001 
  85002 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  85003     defined(BCM_56270_A0)
  85004     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_BCM56260_A0r */
  85005         soc_block_list[4],
  85006         soc_genreg,
  85007         4,
  85008         0,
  85009         0xa010a00,
  85010         SOC_REG_FLAG_ARRAY,
  85011         0,
  85012         1,
  85013         soc_BUFFER_CELL_LIMIT_SP_BCM56260_A0r_fields,
  85014         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85015         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  85016         -1,
  85017         -1,
  85018     },
  85019 #endif /* chips */
  85020 
  85021 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  85022     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_BCM56440_A0r */
  85023         soc_block_list[4],
  85024         soc_genreg,
  85025         4,
  85026         0,
  85027         0x208010a,
  85028         SOC_REG_FLAG_ARRAY,
  85029         0,
  85030         1,
  85031         soc_BUFFER_CELL_LIMIT_SP_BCM56440_A0r_fields,
  85032         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85033         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  85034         -1,
  85035         -1,
  85036     },
  85037 #endif /* chips */
  85038 
  85039 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  85040     defined(BCM_56450_B1)
  85041     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_BCM56450_A0r */
  85042         soc_block_list[4],
  85043         soc_genreg,
  85044         4,
  85045         0,
  85046         0xa010a00,
  85047         SOC_REG_FLAG_ARRAY,
  85048         0,
  85049         1,
  85050         soc_BUFFER_CELL_LIMIT_SP_BCM56450_A0r_fields,
  85051         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85052         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  85053         -1,
  85054         -1,
  85055     },
  85056 #endif /* chips */
  85057 
  85058 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  85059     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_BCM56640_A0r */
  85060         soc_block_list[4],
  85061         soc_genreg,
  85062         4,
  85063         0,
  85064         0xa010a00,
  85065         SOC_REG_FLAG_ARRAY,
  85066         0,
  85067         1,
  85068         soc_BUFFER_CELL_LIMIT_SP_BCM56640_A0r_fields,
  85069         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85070         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  85071         -1,
  85072         -1,
  85073     },
  85074 #endif /* chips */
  85075 
  85076 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  85077     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_BCM56840_A0r */
  85078         soc_block_list[4],
  85079         soc_genreg,
  85080         4,
  85081         0,
  85082         0x208010a,
  85083         SOC_REG_FLAG_ARRAY,
  85084         0,
  85085         1,
  85086         soc_BUFFER_CELL_LIMIT_SP_BCM56840_A0r_fields,
  85087         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85088         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  85089         -1,
  85090         -1,
  85091     },
  85092 #endif /* chips */
  85093 
  85094 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  85095     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  85096     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  85097     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_SHAREDr */
  85098         soc_block_list[4],
  85099         soc_genreg,
  85100         1,
  85101         0,
  85102         0x208010e,
  85103         0,
  85104         0,
  85105         1,
  85106         soc_BUFFER_CELL_LIMIT_SPr_fields,
  85107         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85108         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  85109         -1,
  85110         -1,
  85111     },
  85112 #endif /* chips */
  85113 
  85114 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \
  85115     defined(BCM_56270_A0)
  85116     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_SHARED_BCM56260_A0r */
  85117         soc_block_list[4],
  85118         soc_genreg,
  85119         1,
  85120         0,
  85121         0xa010e00,
  85122         0,
  85123         0,
  85124         1,
  85125         soc_BUFFER_CELL_LIMIT_SP_BCM56260_A0r_fields,
  85126         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85127         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  85128         -1,
  85129         -1,
  85130     },
  85131 #endif /* chips */
  85132 
  85133 #if defined(BCM_56440_A0) || defined(BCM_56440_B0)
  85134     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_SHARED_BCM56440_A0r */
  85135         soc_block_list[4],
  85136         soc_genreg,
  85137         1,
  85138         0,
  85139         0x208010e,
  85140         0,
  85141         0,
  85142         1,
  85143         soc_BUFFER_CELL_LIMIT_SP_BCM56440_A0r_fields,
  85144         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85145         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  85146         -1,
  85147         -1,
  85148     },
  85149 #endif /* chips */
  85150 
  85151 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \
  85152     defined(BCM_56450_B1)
  85153     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_SHARED_BCM56450_A0r */
  85154         soc_block_list[4],
  85155         soc_genreg,
  85156         1,
  85157         0,
  85158         0xa010e00,
  85159         0,
  85160         0,
  85161         1,
  85162         soc_BUFFER_CELL_LIMIT_SP_BCM56450_A0r_fields,
  85163         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85164         SOC_RESET_MASK_DEC(0x0003ffff, 0x00000000)
  85165         -1,
  85166         -1,
  85167     },
  85168 #endif /* chips */
  85169 
  85170 #if defined(BCM_56340_A0) || defined(BCM_56640_A0)
  85171     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_SHARED_BCM56640_A0r */
  85172         soc_block_list[4],
  85173         soc_genreg,
  85174         1,
  85175         0,
  85176         0xa010e00,
  85177         0,
  85178         0,
  85179         1,
  85180         soc_BUFFER_CELL_LIMIT_SP_BCM56640_A0r_fields,
  85181         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85182         SOC_RESET_MASK_DEC(0x00007fff, 0x00000000)
  85183         -1,
  85184         -1,
  85185     },
  85186 #endif /* chips */
  85187 
  85188 #if defined(BCM_56840_A0) || defined(BCM_56840_B0)
  85189     { /* SOC_REG_INT_BUFFER_CELL_LIMIT_SP_SHARED_BCM56840_A0r */
  85190         soc_block_list[4],
  85191         soc_genreg,
  85192         1,
  85193         0,
  85194         0x208010e,
  85195         0,
  85196         0,
  85197         1,
  85198         soc_BUFFER_CELL_LIMIT_SP_BCM56840_A0r_fields,
  85199         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85200         SOC_RESET_MASK_DEC(0x0000ffff, 0x00000000)
  85201         -1,
  85202         -1,
  85203     },
  85204 #endif /* chips */
  85205 
  85206 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  85207     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  85208     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  85209     { /* SOC_REG_INT_BUFFER_PACKET_LIMIT_SPr */
  85210         soc_block_list[4],
  85211         soc_genreg,
  85212         4,
  85213         0,
  85214         0x208010f,
  85215         SOC_REG_FLAG_ARRAY,
  85216         0,
  85217         1,
  85218         soc_BUFFER_PACKET_LIMIT_SPr_fields,
  85219         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85220         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  85221         -1,
  85222         -1,
  85223     },
  85224 #endif /* chips */
  85225 
  85226 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \
  85227     defined(BCM_56634_A0) || defined(BCM_56634_B0) || \
  85228     defined(BCM_56685_A0) || defined(BCM_56685_B0)
  85229     { /* SOC_REG_INT_BUFFER_PACKET_LIMIT_SP_SHAREDr */
  85230         soc_block_list[4],
  85231         soc_genreg,
  85232         1,
  85233         0,
  85234         0x2080113,
  85235         0,
  85236         0,
  85237         1,
  85238         soc_BUFFER_PACKET_LIMIT_SPr_fields,
  85239         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85240         SOC_RESET_MASK_DEC(0x00003fff, 0x00000000)
  85241         -1,
  85242         -1,
  85243     },
  85244 #endif /* chips */
  85245 
  85246 #if defined(BCM_56850_A0) || defined(BCM_56860_A0)
  85247     { /* SOC_REG_INT_BUF_CFGr */
  85248         soc_block_list[4],
  85249         soc_genreg,
  85250         16,
  85251         0,
  85252         0x56002000,
  85253         SOC_REG_FLAG_ARRAY,
  85254         0,
  85255         2,
  85256         soc_BUF_CFGr_fields,
  85257         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85258         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  85259         -1,
  85260         -1,
  85261     },
  85262 #endif /* chips */
  85263 
  85264 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \
  85265     defined(BCM_56670_A0) || defined(BCM_56670_B0)
  85266     { /* SOC_REG_INT_BUF_CFG_BCM56560_A0r */
  85267         soc_block_list[4],
  85268         soc_genreg,
  85269         16,
  85270         0,
  85271         0x56002000,
  85272         SOC_REG_FLAG_ARRAY,
  85273         0,
  85274         2,
  85275         soc_BUF_CFG_BCM56560_A0r_fields,
  85276         SOC_RESET_VAL_DEC(0x00000000, 0x00000000)
  85277         SOC_RESET_MASK_DEC(0x000001ff, 0x00000000)
  85278         -1,
  85279         -1,
  85280     },
  85281 #endif /* chips */
  85282