allregs_alias.i (3604142B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allregs_alias.i 12 * Purpose: Register aliases. 13 */ 14 15 /* A9JTAG_M0_IDM_IDM_INTERRUPT_STATUS */ "", 16 /* A9JTAG_M0_IDM_IDM_RESET_STATUS */ "", 17 /* A9JTAG_M0_IDM_IO_CONTROL_DIRECT */ "", 18 /* A9JTAG_M0_IDM_IO_STATUS */ "", 19 /* A9JTAG_M0_IDM_RESET_CONTROL */ "", 20 /* A9JTAG_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 21 /* A9JTAG_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 22 /* A9JTAG_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 23 /* A9JTAG_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 24 /* A9JTAG_S0_IDM_IDM_ERROR_LOG_ID */ "", 25 /* A9JTAG_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 26 /* A9JTAG_S0_IDM_IDM_INTERRUPT_STATUS */ "", 27 /* A9JTAG_S0_IDM_IDM_RESET_READ_ID */ "", 28 /* A9JTAG_S0_IDM_IDM_RESET_STATUS */ "", 29 /* A9JTAG_S0_IDM_IDM_RESET_WRITE_ID */ "", 30 /* A9JTAG_S0_IDM_RESET_CONTROL */ "", 31 /* ACPAL_ACPAL_CONTROL_REG */ "", 32 /* ACPAL_ACPAL_ERR_RESP_ADDRESS */ "", 33 /* ACPAL_ACPAL_ERR_RESP_AWID */ "", 34 /* ACPAL_ACPAL_ERR_RESP_INTR_MASK */ "", 35 /* ACPAL_ACPAL_ERR_RESP_INTR_STATUS */ "", 36 /* ACPAL_ACPAL_ERR_RESP_OTHER_ATTR */ "", 37 /* ACPAL_ACPAL_SYNC_REG */ "", 38 /* ACTION_CONTROL_TM */ "ESM_ACL_TABLE_CONTROL_TM", 39 /* ADAPT_RAM_CONTROL */ "", 40 /* ADAPT_RAM_CONTROL_PIPE0 */ "", 41 /* ADAPT_RAM_CONTROL_PIPE1 */ "", 42 /* ADAPT_RAM_CONTROL_PIPE2 */ "", 43 /* ADAPT_RAM_CONTROL_PIPE3 */ "", 44 /* ADAPT_RAM_CONTROL_PIPE4 */ "", 45 /* ADAPT_RAM_CONTROL_PIPE5 */ "", 46 /* ADAPT_RAM_CONTROL_PIPE6 */ "", 47 /* ADAPT_RAM_CONTROL_PIPE7 */ "", 48 /* ADAPT_SER_CONTROL */ "", 49 /* AGINGCTRMEMDEBUG */ "", 50 /* AGINGEXPMEMDEBUG */ "", 51 /* AGINGMSKTBLMEMDEBUG */ "", 52 /* AGINGMSKTBLMEMDEBUG_XPE0 */ "", 53 /* AGING_CTR_ECC_CONTROL_EXT */ "", 54 /* AGING_CTR_ECC_CONTROL_INT */ "", 55 /* AGING_DFT_CNT_EXT */ "", 56 /* AGING_DFT_CNT_INT */ "", 57 /* AGING_ERROR_EXT */ "", 58 /* AGING_ERROR_INT */ "", 59 /* AGING_ERROR_MASK_EXT */ "", 60 /* AGING_ERROR_MASK_INT */ "", 61 /* AGING_EXP_ECC_CONTROL_EXT */ "", 62 /* AGING_EXP_ECC_CONTROL_INT */ "", 63 /* AGING_LMT_ECC_CONTROL_EXT */ "", 64 /* AGING_LMT_ECC_CONTROL_INT */ "", 65 /* ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROL */ "", 66 /* ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS */ "", 67 /* ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTR */ "", 68 /* ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_NACK */ "", 69 /* AMAC_IDM0_IDM_INTERRUPT_STATUS */ "", 70 /* AMAC_IDM0_IDM_RESET_CONTROL */ "", 71 /* AMAC_IDM0_IDM_RESET_STATUS */ "", 72 /* AMAC_IDM0_IO_CONTROL_DIRECT */ "", 73 /* AMAC_IDM0_IO_STATUS */ "", 74 /* AMAC_IDM1_IDM_INTERRUPT_STATUS */ "", 75 /* AMAC_IDM1_IDM_RESET_CONTROL */ "", 76 /* AMAC_IDM1_IDM_RESET_STATUS */ "", 77 /* AMAC_IDM1_IO_CONTROL_DIRECT */ "", 78 /* AMAC_IDM1_IO_STATUS */ "", 79 /* AM_TOP_ECC_1B_ERR_CNT */ "", 80 /* AM_TOP_ECC_2B_ERR_CNT */ "", 81 /* AM_TOP_ECC_ERR_1B_INITIATE */ "", 82 /* AM_TOP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 83 /* AM_TOP_ECC_ERR_2B_INITIATE */ "", 84 /* AM_TOP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 85 /* AM_TOP_ECC_INTERRUPT_REGISTER */ "", 86 /* AM_TOP_ECC_INTERRUPT_REGISTER_MASK */ "", 87 /* AM_TOP_ECC_INTERRUPT_REGISTER_TEST */ "", 88 /* AM_TOP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 89 /* AM_TOP_ERROR_INITIATION_DATA */ "", 90 /* AM_TOP_GLOBAL_MEM_OPTIONS */ "", 91 /* AM_TOP_GTIMER_CONFIGURATION */ "", 92 /* AM_TOP_INDIRECT_COMMAND */ "", 93 /* AM_TOP_INDIRECT_COMMAND_ADDRESS */ "", 94 /* AM_TOP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 95 /* AM_TOP_INDIRECT_COMMAND_RD_DATA */ "", 96 /* AM_TOP_INDIRECT_COMMAND_WIDE_MEM */ "", 97 /* AM_TOP_INDIRECT_COMMAND_WR_DATA */ "", 98 /* AM_TOP_INDIRECT_FORCE_BUBBLE */ "", 99 /* AM_TOP_INDIRECT_WR_MASK */ "", 100 /* AM_TOP_INTERRUPT_MASK_REGISTER */ "", 101 /* AM_TOP_INTERRUPT_REGISTER */ "", 102 /* AM_TOP_INTERRUPT_REGISTER_TEST */ "", 103 /* AM_TOP_RESERVED_MIRROR_ADDR */ "", 104 /* AM_TOP_RESERVED_MTCD */ "", 105 /* AM_TOP_RESERVED_MTCP */ "", 106 /* AM_TOP_RESERVED_SPARE_0 */ "", 107 /* AM_TOP_RESERVED_SPARE_1 */ "", 108 /* AM_TOP_RESERVED_SPARE_2 */ "", 109 /* AM_TOP_RESERVED_SPARE_3 */ "", 110 /* AM_TOP_SBUS_BROADCAST_ID */ "", 111 /* AM_TOP_SBUS_LAST_IN_CHAIN */ "", 112 /* ANY_RMEP_TLV_INTERFACE_DOWN_STATUS */ "", 113 /* ANY_RMEP_TLV_INTERFACE_UP_STATUS */ "", 114 /* ANY_RMEP_TLV_PORT_DOWN_STATUS */ "", 115 /* ANY_RMEP_TLV_PORT_UP_STATUS */ "", 116 /* AN_X1_CONTROL_BAM_SPEED_PRI_0 */ "", 117 /* AN_X1_CONTROL_BAM_SPEED_PRI_1 */ "", 118 /* AN_X1_CONTROL_BAM_SPEED_PRI_2 */ "", 119 /* AN_X1_CONTROL_BAM_SPEED_PRI_3 */ "", 120 /* AN_X1_CONTROL_BAM_SPEED_PRI_4 */ "", 121 /* AN_X1_CONTROL_IEEE_SPEED_PRI_1 */ "", 122 /* AN_X1_CONTROL_OUI_LOWER */ "", 123 /* AN_X1_CONTROL_OUI_UPPER */ "", 124 /* AN_X1_SW_MGMT_GLB_INT */ "", 125 /* AN_X1_SW_MGMT_GLB_MASK */ "", 126 /* AN_X1_TIMERS_CL73_BREAK_LINK */ "", 127 /* AN_X1_TIMERS_CL73_DME_LOCK */ "", 128 /* AN_X1_TIMERS_CL73_ERROR */ "", 129 /* AN_X1_TIMERS_DME_PAGE_TIMER_TYPE */ "", 130 /* AN_X1_TIMERS_IGNORE_LINK_TIMER */ "", 131 /* AN_X1_TIMERS_IGNORE_LINK_TIMER_PAM4 */ "", 132 /* AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72 */ "", 133 /* AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_CL72_PAM4 */ "", 134 /* AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72 */ "", 135 /* AN_X1_TIMERS_LINK_FAIL_INHIBIT_TIMER_NOT_CL72_PAM4 */ "", 136 /* AN_X1_TIMERS_PD_SD_TIMER */ "", 137 /* AN_X4_ABILITIES_CL73_CFG */ "", 138 /* AN_X4_ABILITIES_CL73_CONTROLS */ "", 139 /* AN_X4_ABILITIES_LD_BAM_ABILITIES */ "", 140 /* AN_X4_ABILITIES_LD_BASE_ABILITIES_0 */ "", 141 /* AN_X4_ABILITIES_LD_BASE_ABILITIES_1 */ "", 142 /* AN_X4_ABILITIES_LD_BASE_ABILITIES_2 */ "", 143 /* AN_X4_ABILITIES_LD_BASE_ABILITIES_3 */ "", 144 /* AN_X4_ABILITIES_LD_BASE_ABILITIES_4 */ "", 145 /* AN_X4_ABILITIES_LD_BASE_ABILITIES_5 */ "", 146 /* AN_X4_ABILITIES_LD_FEC_BASEPAGE_ABILITIES */ "", 147 /* AN_X4_ABILITIES_LD_UP1_ABILITIES_0 */ "", 148 /* AN_X4_ABILITIES_LD_UP1_ABILITIES_1 */ "", 149 /* AN_X4_ABILITIES_SW_AN_BASE_PAGE_0 */ "", 150 /* AN_X4_ABILITIES_SW_AN_BASE_PAGE_1 */ "", 151 /* AN_X4_ABILITIES_SW_AN_BASE_PAGE_2 */ "", 152 /* AN_X4_STATUS_LP_BASE1 */ "", 153 /* AN_X4_STATUS_LP_BASE2 */ "", 154 /* AN_X4_STATUS_LP_BASE3 */ "", 155 /* AN_X4_STATUS_LP_MP5_LOWER */ "", 156 /* AN_X4_STATUS_LP_MP5_MIDDLE */ "", 157 /* AN_X4_STATUS_LP_MP5_UPPER */ "", 158 /* AN_X4_STATUS_LP_OUI_UP1 */ "", 159 /* AN_X4_STATUS_LP_OUI_UP2 */ "", 160 /* AN_X4_STATUS_LP_OUI_UP3 */ "", 161 /* AN_X4_STATUS_LP_OUI_UP4 */ "", 162 /* AN_X4_STATUS_LP_OUI_UP5 */ "", 163 /* AN_X4_STATUS_LP_UP_LOWER */ "", 164 /* AN_X4_STATUS_LP_UP_MIDDLE */ "", 165 /* AN_X4_STATUS_LP_UP_UPPER */ "", 166 /* AN_X4_STATUS_PSEQ_RF */ "", 167 /* AN_X4_STATUS_PSEQ_STATUS */ "", 168 /* AN_X4_STATUS_PXNG_STATUS */ "", 169 /* AN_X4_STATUS_RES_ERR */ "", 170 /* AN_X4_STATUS_R_CL73_STATUS */ "", 171 /* AN_X4_STATUS_UNEXP_PAGE */ "", 172 /* AN_X4_SW_MGMT_AN_ABILITY_RESOLUTION_STATUS */ "", 173 /* AN_X4_SW_MGMT_AN_MISC_STATUS */ "", 174 /* AN_X4_SW_MGMT_INT */ "", 175 /* AN_X4_SW_MGMT_INT_EN */ "", 176 /* AN_X4_SW_MGMT_LD_CONTROL */ "", 177 /* AN_X4_SW_MGMT_LD_PAGE_0 */ "", 178 /* AN_X4_SW_MGMT_LD_PAGE_1 */ "", 179 /* AN_X4_SW_MGMT_LD_PAGE_2 */ "", 180 /* AN_X4_SW_MGMT_LP_PAGE_0 */ "", 181 /* AN_X4_SW_MGMT_LP_PAGE_1 */ "", 182 /* AN_X4_SW_MGMT_LP_PAGE_2 */ "", 183 /* AN_X4_SW_MGMT_SW_CONTROL_STATUS */ "", 184 /* AN_X4_SW_MGMT_TLA_SEQUENCER_STATUS */ "", 185 /* AN_X4_SW_MGMT_WAIT_ACK_COMPLETE */ "", 186 /* AOPSTH */ "", 187 /* APBR_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 188 /* APBR_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 189 /* APBR_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 190 /* APBR_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 191 /* APBR_S0_IDM_IDM_ERROR_LOG_ID */ "", 192 /* APBR_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 193 /* APBR_S0_IDM_IDM_INTERRUPT_STATUS */ "", 194 /* APBR_S0_IDM_IDM_RESET_CONTROL */ "", 195 /* APBR_S0_IDM_IDM_RESET_READ_ID */ "", 196 /* APBR_S0_IDM_IDM_RESET_STATUS */ "", 197 /* APBR_S0_IDM_IDM_RESET_WRITE_ID */ "", 198 /* APBS_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 199 /* APBS_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 200 /* APBS_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 201 /* APBS_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 202 /* APBS_S0_IDM_IDM_ERROR_LOG_ID */ "", 203 /* APBS_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 204 /* APBS_S0_IDM_IDM_INTERRUPT_STATUS */ "", 205 /* APBS_S0_IDM_IDM_RESET_CONTROL */ "", 206 /* APBS_S0_IDM_IDM_RESET_READ_ID */ "", 207 /* APBS_S0_IDM_IDM_RESET_STATUS */ "", 208 /* APBS_S0_IDM_IDM_RESET_WRITE_ID */ "", 209 /* APBV_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 210 /* APBV_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 211 /* APBV_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 212 /* APBV_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 213 /* APBV_S0_IDM_IDM_ERROR_LOG_ID */ "", 214 /* APBV_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 215 /* APBV_S0_IDM_IDM_INTERRUPT_STATUS */ "", 216 /* APBV_S0_IDM_IDM_RESET_CONTROL */ "", 217 /* APBV_S0_IDM_IDM_RESET_READ_ID */ "", 218 /* APBV_S0_IDM_IDM_RESET_STATUS */ "", 219 /* APBV_S0_IDM_IDM_RESET_WRITE_ID */ "", 220 /* APBW_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 221 /* APBW_IDM_IDM_ERROR_LOG_COMPLETE */ "", 222 /* APBW_IDM_IDM_ERROR_LOG_CONTROL */ "", 223 /* APBW_IDM_IDM_ERROR_LOG_FLAGS */ "", 224 /* APBW_IDM_IDM_ERROR_LOG_ID */ "", 225 /* APBW_IDM_IDM_ERROR_LOG_STATUS */ "", 226 /* APBW_IDM_IDM_INTERRUPT_STATUS */ "", 227 /* APBW_IDM_IDM_IO_CONTROL_DIRECT */ "", 228 /* APBW_IDM_IDM_IO_STATUS */ "", 229 /* APBW_IDM_IDM_RESET_CONTROL */ "", 230 /* APBW_IDM_IDM_RESET_READ_ID */ "", 231 /* APBW_IDM_IDM_RESET_STATUS */ "", 232 /* APBW_IDM_IDM_RESET_WRITE_ID */ "", 233 /* APBX_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 234 /* APBX_IDM_IDM_ERROR_LOG_COMPLETE */ "", 235 /* APBX_IDM_IDM_ERROR_LOG_CONTROL */ "", 236 /* APBX_IDM_IDM_ERROR_LOG_FLAGS */ "", 237 /* APBX_IDM_IDM_ERROR_LOG_ID */ "", 238 /* APBX_IDM_IDM_ERROR_LOG_STATUS */ "", 239 /* APBX_IDM_IDM_INTERRUPT_STATUS */ "", 240 /* APBX_IDM_IDM_IO_CONTROL_DIRECT */ "", 241 /* APBX_IDM_IDM_RESET_CONTROL */ "", 242 /* APBX_IDM_IDM_RESET_READ_ID */ "", 243 /* APBX_IDM_IDM_RESET_STATUS */ "", 244 /* APBX_IDM_IDM_RESET_WRITE_ID */ "", 245 /* APBY_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 246 /* APBY_IDM_IDM_ERROR_LOG_COMPLETE */ "", 247 /* APBY_IDM_IDM_ERROR_LOG_CONTROL */ "", 248 /* APBY_IDM_IDM_ERROR_LOG_FLAGS */ "", 249 /* APBY_IDM_IDM_ERROR_LOG_ID */ "", 250 /* APBY_IDM_IDM_ERROR_LOG_STATUS */ "", 251 /* APBY_IDM_IDM_INTERRUPT_STATUS */ "", 252 /* APBY_IDM_IDM_IO_CONTROL_DIRECT */ "", 253 /* APBY_IDM_IDM_RESET_CONTROL */ "", 254 /* APBY_IDM_IDM_RESET_READ_ID */ "", 255 /* APBY_IDM_IDM_RESET_STATUS */ "", 256 /* APBY_IDM_IDM_RESET_WRITE_ID */ "", 257 /* APBY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 258 /* APBY_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 259 /* APBY_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 260 /* APBY_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 261 /* APBY_S0_IDM_IDM_ERROR_LOG_ID */ "", 262 /* APBY_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 263 /* APBY_S0_IDM_IDM_INTERRUPT_STATUS */ "", 264 /* APBY_S0_IDM_IDM_IO_CONTROL_DIRECT */ "", 265 /* APBY_S0_IDM_IDM_IO_STATUS */ "", 266 /* APBY_S0_IDM_IDM_RESET_CONTROL */ "", 267 /* APBY_S0_IDM_IDM_RESET_READ_ID */ "", 268 /* APBY_S0_IDM_IDM_RESET_STATUS */ "", 269 /* APBY_S0_IDM_IDM_RESET_WRITE_ID */ "", 270 /* APBZ_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 271 /* APBZ_IDM_IDM_ERROR_LOG_COMPLETE */ "", 272 /* APBZ_IDM_IDM_ERROR_LOG_CONTROL */ "", 273 /* APBZ_IDM_IDM_ERROR_LOG_FLAGS */ "", 274 /* APBZ_IDM_IDM_ERROR_LOG_ID */ "", 275 /* APBZ_IDM_IDM_ERROR_LOG_STATUS */ "", 276 /* APBZ_IDM_IDM_INTERRUPT_STATUS */ "", 277 /* APBZ_IDM_IDM_IO_CONTROL_DIRECT */ "", 278 /* APBZ_IDM_IDM_RESET_CONTROL */ "", 279 /* APBZ_IDM_IDM_RESET_READ_ID */ "", 280 /* APBZ_IDM_IDM_RESET_STATUS */ "", 281 /* APBZ_IDM_IDM_RESET_WRITE_ID */ "", 282 /* APBZ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 283 /* APBZ_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 284 /* APBZ_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 285 /* APBZ_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 286 /* APBZ_S0_IDM_IDM_ERROR_LOG_ID */ "", 287 /* APBZ_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 288 /* APBZ_S0_IDM_IDM_INTERRUPT_STATUS */ "", 289 /* APBZ_S0_IDM_IDM_IO_CONTROL_DIRECT */ "", 290 /* APBZ_S0_IDM_IDM_IO_STATUS */ "", 291 /* APBZ_S0_IDM_IDM_RESET_CONTROL */ "", 292 /* APBZ_S0_IDM_IDM_RESET_READ_ID */ "", 293 /* APBZ_S0_IDM_IDM_RESET_STATUS */ "", 294 /* APBZ_S0_IDM_IDM_RESET_WRITE_ID */ "", 295 /* APM0_BUFFER_FLUSH_CONTROL */ "", 296 /* APM0_DATA_SWAP_CONTROL */ "", 297 /* APM0_DEBUG_DMA_HOSTRD_STATE_MACHINE */ "", 298 /* APM0_DEBUG_DMA_HOSTWR_STATE_MACHINE */ "", 299 /* APM0_DEBUG_RXQ_STATE_MACHINE */ "", 300 /* APM0_DEBUG_TXQ_CH0_STATE_MACHINE */ "", 301 /* APM0_DEBUG_TXQ_CH1_STATE_MACHINE */ "", 302 /* APM0_DEBUG_TXQ_CH2_STATE_MACHINE */ "", 303 /* APM0_DEBUG_TXQ_CH3_STATE_MACHINE */ "", 304 /* APM0_DEVCONTROL */ "", 305 /* APM0_DEVSTATUS */ "", 306 /* APM0_ERROR_STATUS */ "", 307 /* APM0_FLOWCNTL_TH */ "", 308 /* APM0_GPTIMER */ "", 309 /* APM0_INTMASK */ "", 310 /* APM0_INTRCVLAZY */ "", 311 /* APM0_INTSTATUS */ "", 312 /* APM0_M0_IDM_IDM_INTERRUPT_STATUS */ "", 313 /* APM0_M0_IDM_IDM_IO_CONTROL_DIRECT */ "", 314 /* APM0_M0_IDM_IDM_IO_STATUS */ "", 315 /* APM0_M0_IDM_IDM_RESET_CONTROL */ "", 316 /* APM0_M0_IDM_IDM_RESET_STATUS */ "", 317 /* APM0_MEMORYECCSTATUS */ "", 318 /* APM0_MEMORY_ECC_CONTROL */ "", 319 /* APM0_MEMORY_ECC_STATUS_1 */ "", 320 /* APM0_RCVADDR_HIGH */ "", 321 /* APM0_RCVADDR_LOW */ "", 322 /* APM0_RCVCONTROL */ "", 323 /* APM0_RCVPTR */ "", 324 /* APM0_RCVSTATUS0 */ "", 325 /* APM0_RCVSTATUS1 */ "", 326 /* APM0_RXPRSR_VLAN */ "", 327 /* APM0_RXQCONTROL */ "", 328 /* APM0_RX_PACKET_DMA_READ_ARB_CTRL */ "", 329 /* APM0_RX_PACKET_DMA_WRITE_ARB_CTRL */ "", 330 /* APM0_RX_PACKET_DMA_WRITE_AXI_MAP_CTRL */ "", 331 /* APM0_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES */ "", 332 /* APM0_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT */ "", 333 /* APM0_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT */ "", 334 /* APM0_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL */ "", 335 /* APM0_STATISTICS_COUNTER_CTRL */ "", 336 /* APM0_STATISTICS_RXQ_COMPLETE_PKT_DROP_COUNTER */ "", 337 /* APM0_STATISTICS_RXQ_PARTIAL_PKT_DROP_COUNTER */ "", 338 /* APM0_STATISTICS_RXQ_TRANSFERRED_PKT_COUNTER */ "", 339 /* APM0_STATISTICS_RXQ_TRUNCATED_PKT_COUNTER */ "", 340 /* APM0_STATISTICS_TXQ_CH0_ERROR_PKT_COUNTER */ "", 341 /* APM0_STATISTICS_TXQ_CH0_GOOD_PKT_COUNTER */ "", 342 /* APM0_STATISTICS_TXQ_CH0_PKT_DROP_COUNTER */ "", 343 /* APM0_STATISTICS_TXQ_CH1_ERROR_PKT_COUNTER */ "", 344 /* APM0_STATISTICS_TXQ_CH1_GOOD_PKT_COUNTER */ "", 345 /* APM0_STATISTICS_TXQ_CH1_PKT_DROP_COUNTER */ "", 346 /* APM0_STATISTICS_TXQ_CH2_ERROR_PKT_COUNTER */ "", 347 /* APM0_STATISTICS_TXQ_CH2_GOOD_PKT_COUNTER */ "", 348 /* APM0_STATISTICS_TXQ_CH2_PKT_DROP_COUNTER */ "", 349 /* APM0_STATISTICS_TXQ_CH3_ERROR_PKT_COUNTER */ "", 350 /* APM0_STATISTICS_TXQ_CH3_GOOD_PKT_COUNTER */ "", 351 /* APM0_STATISTICS_TXQ_CH3_PKT_DROP_COUNTER */ "", 352 /* APM0_STATUS_RXQ_BUF_DEPTH */ "", 353 /* APM0_STATUS_TXQ_SHARED_BUF_DEPTH_CH0 */ "", 354 /* APM0_STATUS_TXQ_SHARED_BUF_DEPTH_CH1 */ "", 355 /* APM0_STATUS_TXQ_SHARED_BUF_DEPTH_CH2 */ "", 356 /* APM0_STATUS_TXQ_SHARED_BUF_DEPTH_CH3 */ "", 357 /* APM0_TXARB_WRR_TH */ "", 358 /* APM0_TXQRXQMEMORYCONTROL */ "", 359 /* APM0_TXQ_COMMON_CONTROL */ "", 360 /* APM0_TXQ_DATA_TRANSMIT_REQ_CONTROL0 */ "", 361 /* APM0_TXQ_DATA_TRANSMIT_REQ_CONTROL1 */ "", 362 /* APM0_TX_PACKET_DMA_READ_ARB_CTRL */ "", 363 /* APM0_XMTADDR_HIGH_0 */ "", 364 /* APM0_XMTADDR_HIGH_1 */ "", 365 /* APM0_XMTADDR_HIGH_2 */ "", 366 /* APM0_XMTADDR_HIGH_3 */ "", 367 /* APM0_XMTADDR_LOW_0 */ "", 368 /* APM0_XMTADDR_LOW_1 */ "", 369 /* APM0_XMTADDR_LOW_2 */ "", 370 /* APM0_XMTADDR_LOW_3 */ "", 371 /* APM0_XMTCONTROL_0 */ "", 372 /* APM0_XMTCONTROL_1 */ "", 373 /* APM0_XMTCONTROL_2 */ "", 374 /* APM0_XMTCONTROL_3 */ "", 375 /* APM0_XMTPTR_0 */ "", 376 /* APM0_XMTPTR_1 */ "", 377 /* APM0_XMTPTR_2 */ "", 378 /* APM0_XMTPTR_3 */ "", 379 /* APM0_XMTSTATUS0_0 */ "", 380 /* APM0_XMTSTATUS0_1 */ "", 381 /* APM0_XMTSTATUS0_2 */ "", 382 /* APM0_XMTSTATUS0_3 */ "", 383 /* APM0_XMTSTATUS1_0 */ "", 384 /* APM0_XMTSTATUS1_1 */ "", 385 /* APM0_XMTSTATUS1_2 */ "", 386 /* APM0_XMTSTATUS1_3 */ "", 387 /* APM1_BUFFER_FLUSH_CONTROL */ "", 388 /* APM1_DATA_SWAP_CONTROL */ "", 389 /* APM1_DEBUG_DMA_HOSTRD_STATE_MACHINE */ "", 390 /* APM1_DEBUG_DMA_HOSTWR_STATE_MACHINE */ "", 391 /* APM1_DEBUG_RXQ_STATE_MACHINE */ "", 392 /* APM1_DEBUG_TXQ_CH0_STATE_MACHINE */ "", 393 /* APM1_DEBUG_TXQ_CH1_STATE_MACHINE */ "", 394 /* APM1_DEBUG_TXQ_CH2_STATE_MACHINE */ "", 395 /* APM1_DEBUG_TXQ_CH3_STATE_MACHINE */ "", 396 /* APM1_DEVCONTROL */ "", 397 /* APM1_DEVSTATUS */ "", 398 /* APM1_ERROR_STATUS */ "", 399 /* APM1_FLOWCNTL_TH */ "", 400 /* APM1_GPTIMER */ "", 401 /* APM1_INTMASK */ "", 402 /* APM1_INTRCVLAZY */ "", 403 /* APM1_INTSTATUS */ "", 404 /* APM1_M0_IDM_IDM_INTERRUPT_STATUS */ "", 405 /* APM1_M0_IDM_IDM_IO_CONTROL_DIRECT */ "", 406 /* APM1_M0_IDM_IDM_IO_STATUS */ "", 407 /* APM1_M0_IDM_IDM_RESET_CONTROL */ "", 408 /* APM1_M0_IDM_IDM_RESET_STATUS */ "", 409 /* APM1_MEMORYECCSTATUS */ "", 410 /* APM1_MEMORY_ECC_CONTROL */ "", 411 /* APM1_MEMORY_ECC_STATUS_1 */ "", 412 /* APM1_RCVADDR_HIGH */ "", 413 /* APM1_RCVADDR_LOW */ "", 414 /* APM1_RCVCONTROL */ "", 415 /* APM1_RCVPTR */ "", 416 /* APM1_RCVSTATUS0 */ "", 417 /* APM1_RCVSTATUS1 */ "", 418 /* APM1_RXPRSR_VLAN */ "", 419 /* APM1_RXQCONTROL */ "", 420 /* APM1_RX_PACKET_DMA_READ_ARB_CTRL */ "", 421 /* APM1_RX_PACKET_DMA_WRITE_ARB_CTRL */ "", 422 /* APM1_RX_PACKET_DMA_WRITE_AXI_MAP_CTRL */ "", 423 /* APM1_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES */ "", 424 /* APM1_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT */ "", 425 /* APM1_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT */ "", 426 /* APM1_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL */ "", 427 /* APM1_STATISTICS_COUNTER_CTRL */ "", 428 /* APM1_STATISTICS_RXQ_COMPLETE_PKT_DROP_COUNTER */ "", 429 /* APM1_STATISTICS_RXQ_PARTIAL_PKT_DROP_COUNTER */ "", 430 /* APM1_STATISTICS_RXQ_TRANSFERRED_PKT_COUNTER */ "", 431 /* APM1_STATISTICS_RXQ_TRUNCATED_PKT_COUNTER */ "", 432 /* APM1_STATISTICS_TXQ_CH0_ERROR_PKT_COUNTER */ "", 433 /* APM1_STATISTICS_TXQ_CH0_GOOD_PKT_COUNTER */ "", 434 /* APM1_STATISTICS_TXQ_CH0_PKT_DROP_COUNTER */ "", 435 /* APM1_STATISTICS_TXQ_CH1_ERROR_PKT_COUNTER */ "", 436 /* APM1_STATISTICS_TXQ_CH1_GOOD_PKT_COUNTER */ "", 437 /* APM1_STATISTICS_TXQ_CH1_PKT_DROP_COUNTER */ "", 438 /* APM1_STATISTICS_TXQ_CH2_ERROR_PKT_COUNTER */ "", 439 /* APM1_STATISTICS_TXQ_CH2_GOOD_PKT_COUNTER */ "", 440 /* APM1_STATISTICS_TXQ_CH2_PKT_DROP_COUNTER */ "", 441 /* APM1_STATISTICS_TXQ_CH3_ERROR_PKT_COUNTER */ "", 442 /* APM1_STATISTICS_TXQ_CH3_GOOD_PKT_COUNTER */ "", 443 /* APM1_STATISTICS_TXQ_CH3_PKT_DROP_COUNTER */ "", 444 /* APM1_STATUS_RXQ_BUF_DEPTH */ "", 445 /* APM1_STATUS_TXQ_SHARED_BUF_DEPTH_CH0 */ "", 446 /* APM1_STATUS_TXQ_SHARED_BUF_DEPTH_CH1 */ "", 447 /* APM1_STATUS_TXQ_SHARED_BUF_DEPTH_CH2 */ "", 448 /* APM1_STATUS_TXQ_SHARED_BUF_DEPTH_CH3 */ "", 449 /* APM1_TXARB_WRR_TH */ "", 450 /* APM1_TXQRXQMEMORYCONTROL */ "", 451 /* APM1_TXQ_COMMON_CONTROL */ "", 452 /* APM1_TXQ_DATA_TRANSMIT_REQ_CONTROL0 */ "", 453 /* APM1_TXQ_DATA_TRANSMIT_REQ_CONTROL1 */ "", 454 /* APM1_TX_PACKET_DMA_READ_ARB_CTRL */ "", 455 /* APM1_XMTADDR_HIGH_0 */ "", 456 /* APM1_XMTADDR_HIGH_1 */ "", 457 /* APM1_XMTADDR_HIGH_2 */ "", 458 /* APM1_XMTADDR_HIGH_3 */ "", 459 /* APM1_XMTADDR_LOW_0 */ "", 460 /* APM1_XMTADDR_LOW_1 */ "", 461 /* APM1_XMTADDR_LOW_2 */ "", 462 /* APM1_XMTADDR_LOW_3 */ "", 463 /* APM1_XMTCONTROL_0 */ "", 464 /* APM1_XMTCONTROL_1 */ "", 465 /* APM1_XMTCONTROL_2 */ "", 466 /* APM1_XMTCONTROL_3 */ "", 467 /* APM1_XMTPTR_0 */ "", 468 /* APM1_XMTPTR_1 */ "", 469 /* APM1_XMTPTR_2 */ "", 470 /* APM1_XMTPTR_3 */ "", 471 /* APM1_XMTSTATUS0_0 */ "", 472 /* APM1_XMTSTATUS0_1 */ "", 473 /* APM1_XMTSTATUS0_2 */ "", 474 /* APM1_XMTSTATUS0_3 */ "", 475 /* APM1_XMTSTATUS1_0 */ "", 476 /* APM1_XMTSTATUS1_1 */ "", 477 /* APM1_XMTSTATUS1_2 */ "", 478 /* APM1_XMTSTATUS1_3 */ "", 479 /* ARB_EOP_DEBUG */ "", 480 /* ARB_MOP_DEBUG */ "", 481 /* ARB_RAM_1_DBGCTRL */ "ARB_RAM_1_CONTROL", 482 /* ARB_RAM_DBGCTRL */ "ARB_RAM_CONTROL", 483 /* ARB_RAM_DBGCTRL_1 */ "ARB_RAM_CONTROL_1", 484 /* ARB_SER_CONTROL */ "", 485 /* ARMCSSYS_M0_IDM_IDM_INTERRUPT_STATUS */ "", 486 /* ARMCSSYS_M0_IDM_IDM_RESET_STATUS */ "", 487 /* ARMCSSYS_M0_IDM_IO_CONTROL_DIRECT */ "", 488 /* ARMCSSYS_M0_IDM_IO_STATUS */ "", 489 /* ARMCSSYS_M0_IDM_RESET_CONTROL */ "", 490 /* ARP_RARP_ENABLE */ "", 491 /* ASFCONFIG */ "", 492 /* ASFPKTCOUNT */ "", 493 /* ASFPORTSPEED */ "", 494 /* ASF_CREDIT_THRESH_HI */ "", 495 /* ASF_CREDIT_THRESH_LO */ "", 496 /* ASF_ENABLE_0_64Q */ "", 497 /* ASF_ENABLE_1_64Q */ "", 498 /* ASF_ENABLE_8Q */ "", 499 /* ASF_EPORT_CFG */ "", 500 /* ASF_IPORT_CFG */ "", 501 /* ASF_PKT_SIZE */ "", 502 /* ASF_PORT_CFG */ "", 503 /* ASF_PORT_SPEED */ "", 504 /* ASF_PORT_SPEED_MATCH_BMP0 */ "", 505 /* ASF_PORT_SPEED_MATCH_BMP1 */ "", 506 /* ASF_PORT_SPEED_MATCH_BMP2 */ "", 507 /* ATSB1_TCID_0 */ "", 508 /* ATSB1_TCID_1 */ "", 509 /* ATSB1_TCID_2 */ "", 510 /* ATSB1_TCID_3 */ "", 511 /* ATSB1_TCID_4 */ "", 512 /* ATSB1_TCID_5 */ "", 513 /* ATSB1_TCID_6 */ "", 514 /* ATSB1_TCID_7 */ "", 515 /* ATSB1_TCID_8 */ "", 516 /* ATSB1_TCID_9 */ "", 517 /* ATSB1_TCID_10 */ "", 518 /* ATSB1_TCID_11 */ "", 519 /* ATSB1_TCID_12 */ "", 520 /* ATSB1_TCID_13 */ "", 521 /* ATSB1_TCID_14 */ "", 522 /* ATSB1_TCID_15 */ "", 523 /* ATSB2_TCID_0 */ "", 524 /* ATSB2_TCID_1 */ "", 525 /* ATSB2_TCID_2 */ "", 526 /* ATSB2_TCID_3 */ "", 527 /* ATSB2_TCID_4 */ "", 528 /* ATSB2_TCID_5 */ "", 529 /* ATSB2_TCID_6 */ "", 530 /* ATSB2_TCID_7 */ "", 531 /* ATSB2_TCID_8 */ "", 532 /* ATSB2_TCID_9 */ "", 533 /* ATSB2_TCID_10 */ "", 534 /* ATSB2_TCID_11 */ "", 535 /* ATSB2_TCID_12 */ "", 536 /* ATSB2_TCID_13 */ "", 537 /* ATSB2_TCID_14 */ "", 538 /* ATSB2_TCID_15 */ "", 539 /* ATSC_TCID_0 */ "", 540 /* ATSC_TCID_1 */ "", 541 /* ATSC_TCID_2 */ "", 542 /* ATSC_TCID_3 */ "", 543 /* ATSC_TCID_4 */ "", 544 /* ATSC_TCID_5 */ "", 545 /* ATSC_TCID_6 */ "", 546 /* ATSC_TCID_7 */ "", 547 /* ATSC_TCID_8 */ "", 548 /* ATSC_TCID_9 */ "", 549 /* ATSC_TCID_10 */ "", 550 /* ATSC_TCID_11 */ "", 551 /* ATSC_TCID_12 */ "", 552 /* ATSC_TCID_13 */ "", 553 /* ATSC_TCID_14 */ "", 554 /* ATSC_TCID_15 */ "", 555 /* ATSUM1_TCID_0 */ "", 556 /* ATSUM1_TCID_1 */ "", 557 /* ATSUM1_TCID_2 */ "", 558 /* ATSUM1_TCID_3 */ "", 559 /* ATSUM1_TCID_4 */ "", 560 /* ATSUM1_TCID_5 */ "", 561 /* ATSUM1_TCID_6 */ "", 562 /* ATSUM1_TCID_7 */ "", 563 /* ATSUM1_TCID_8 */ "", 564 /* ATSUM1_TCID_9 */ "", 565 /* ATSUM1_TCID_10 */ "", 566 /* ATSUM1_TCID_11 */ "", 567 /* ATSUM1_TCID_12 */ "", 568 /* ATSUM1_TCID_13 */ "", 569 /* ATSUM1_TCID_14 */ "", 570 /* ATSUM1_TCID_15 */ "", 571 /* ATSUM2_TCID_0 */ "", 572 /* ATSUM2_TCID_1 */ "", 573 /* ATSUM2_TCID_2 */ "", 574 /* ATSUM2_TCID_3 */ "", 575 /* ATSUM2_TCID_4 */ "", 576 /* ATSUM2_TCID_5 */ "", 577 /* ATSUM2_TCID_6 */ "", 578 /* ATSUM2_TCID_7 */ "", 579 /* ATSUM2_TCID_8 */ "", 580 /* ATSUM2_TCID_9 */ "", 581 /* ATSUM2_TCID_10 */ "", 582 /* ATSUM2_TCID_11 */ "", 583 /* ATSUM2_TCID_12 */ "", 584 /* ATSUM2_TCID_13 */ "", 585 /* ATSUM2_TCID_14 */ "", 586 /* ATSUM2_TCID_15 */ "", 587 /* AUTOVOIP_OUI_1 */ "", 588 /* AUTOVOIP_OUI_2 */ "", 589 /* AUTOVOIP_OUI_3 */ "", 590 /* AUTOVOIP_OUI_4 */ "", 591 /* AUTOVOIP_OUI_5 */ "", 592 /* AUTOVOIP_OUI_6 */ "", 593 /* AUX_ARB_CONTROL */ "", 594 /* AUX_ARB_CONTROL_2 */ "", 595 /* AUX_ARB_CONTROL_2_64 */ "", 596 /* AUX_ARB_CONTROL_PIPE0 */ "", 597 /* AUX_ARB_CONTROL_PIPE1 */ "", 598 /* AUX_ARB_CONTROL_PIPE2 */ "", 599 /* AUX_ARB_CONTROL_PIPE3 */ "", 600 /* AUX_ARB_CONTROL_PIPE4 */ "", 601 /* AUX_ARB_CONTROL_PIPE5 */ "", 602 /* AUX_ARB_CONTROL_PIPE6 */ "", 603 /* AUX_ARB_CONTROL_PIPE7 */ "", 604 /* AUX_L2_BULK_CONTROL */ "", 605 /* AVS_CTRL */ "", 606 /* AVS_CTRL_0 */ "", 607 /* AVS_REG_HW_MNTR_AC_DCN_CEN_ROSC_0 */ "", 608 /* AVS_REG_HW_MNTR_AC_PATGEN_HI_LO_DUR */ "", 609 /* AVS_REG_HW_MNTR_ADC_SETTLING_TIME */ "", 610 /* AVS_REG_HW_MNTR_AVS_INTERRUPT_FLAGS */ "", 611 /* AVS_REG_HW_MNTR_AVS_INTERRUPT_FLAGS_CLEAR */ "", 612 /* AVS_REG_HW_MNTR_AVS_REGISTERS_LOCKS */ "", 613 /* AVS_REG_HW_MNTR_AVS_SPARE_0 */ "", 614 /* AVS_REG_HW_MNTR_AVS_SPARE_1 */ "", 615 /* AVS_REG_HW_MNTR_ENABLE_DEFAULT_CEN_ROSC_0 */ "", 616 /* AVS_REG_HW_MNTR_ENABLE_DEFAULT_CEN_ROSC_1 */ "", 617 /* AVS_REG_HW_MNTR_ENABLE_DEFAULT_PVT_MNTR */ "", 618 /* AVS_REG_HW_MNTR_IDLE_STATE_0_CEN_ROSC_0 */ "", 619 /* AVS_REG_HW_MNTR_IDLE_STATE_0_CEN_ROSC_1 */ "", 620 /* AVS_REG_HW_MNTR_INTERRUPT_POW_WDOG_EN */ "", 621 /* AVS_REG_HW_MNTR_INTERRUPT_POW_WDOG_EN_1 */ "", 622 /* AVS_REG_HW_MNTR_INTERRUPT_POW_WDOG_EN_2 */ "", 623 /* AVS_REG_HW_MNTR_INTERRUPT_SW_MEASUREMENT_DONE_EN */ "", 624 /* AVS_REG_HW_MNTR_LAST_MEASURED_SENSOR */ "", 625 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_CEN_ROSC_0 */ "", 626 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_CEN_ROSC_1 */ "", 627 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_POW_WDOG */ "", 628 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_PVT_MNTR */ "", 629 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_RMT_ROSC_0 */ "", 630 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_RMT_ROSC_1 */ "", 631 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_RMT_ROSC_2 */ "", 632 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_RMT_ROSC_3 */ "", 633 /* AVS_REG_HW_MNTR_MEASUREMENTS_INIT_RMT_ROSC_4 */ "", 634 /* AVS_REG_HW_MNTR_REMOTE_SENSOR_TYPE */ "", 635 /* AVS_REG_HW_MNTR_REMOTE_SENSOR_TYPE_1 */ "", 636 /* AVS_REG_HW_MNTR_REMOTE_SENSOR_TYPE_2 */ "", 637 /* AVS_REG_HW_MNTR_ROSC_COUNTING_MODE */ "", 638 /* AVS_REG_HW_MNTR_ROSC_MEASUREMENT_TIME_CONTROL */ "", 639 /* AVS_REG_HW_MNTR_SEQUENCER_INIT */ "", 640 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_CEN_ROSC_0 */ "", 641 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_CEN_ROSC_1 */ "", 642 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_PVT_MNTR */ "", 643 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_RMT_ROSC_0 */ "", 644 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_RMT_ROSC_1 */ "", 645 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_RMT_ROSC_2 */ "", 646 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_RMT_ROSC_3 */ "", 647 /* AVS_REG_HW_MNTR_SEQUENCER_MASK_RMT_ROSC_4 */ "", 648 /* AVS_REG_HW_MNTR_SW_CONTROLS */ "", 649 /* AVS_REG_HW_MNTR_SW_MEASUREMENT_UNIT_BUSY */ "", 650 /* AVS_REG_HW_MNTR_TEMPERATURE_RESET_ENABLE */ "", 651 /* AVS_REG_HW_MNTR_TEMPERATURE_THRESHOLD */ "", 652 /* AVS_REG_MISC_CONTROL_0 */ "", 653 /* AVS_REG_MISC_CONTROL_1 */ "", 654 /* AVS_REG_MISC_CONTROL_2 */ "", 655 /* AVS_REG_MISC_CONTROL_3 */ "", 656 /* AVS_REG_MISC_STATUS_0 */ "", 657 /* AVS_REG_MISC_STATUS_1 */ "", 658 /* AVS_REG_PMB_REGISTERS_CLEAR_PMB_ERROR_STATUS */ "", 659 /* AVS_REG_PMB_REGISTERS_PMB_ERROR_STATUS */ "", 660 /* AVS_REG_PMB_REGISTERS_PMB_TIMEOUT */ "", 661 /* AVS_REG_PMB_SLAVE_AVS_PWD_ACC_CONTROL */ "", 662 /* AVS_REG_PMB_SLAVE_AVS_PWD_CONTROL */ "", 663 /* AVS_REG_PMB_SLAVE_AVS_ROSC_CONTROL */ "", 664 /* AVS_REG_PMB_SLAVE_AVS_ROSC_COUNT */ "", 665 /* AVS_REG_PMB_SLAVE_AVS_ROSC_H_THRESHOLD */ "", 666 /* AVS_REG_PMB_SLAVE_AVS_ROSC_ILVT16_THRESHOLD */ "", 667 /* AVS_REG_PMB_SLAVE_AVS_ROSC_LVT16_LVT20_CONTROL */ "", 668 /* AVS_REG_PMB_SLAVE_AVS_ROSC_LVT16_LVT20_COUNT */ "", 669 /* AVS_REG_PMB_SLAVE_AVS_ROSC_LVT16_THRESHOLD */ "", 670 /* AVS_REG_PMB_SLAVE_AVS_ROSC_LVT20_THRESHOLD */ "", 671 /* AVS_REG_PMB_SLAVE_AVS_ROSC_MISC_CONTROL */ "", 672 /* AVS_REG_PMB_SLAVE_AVS_ROSC_SVT20_ILVT16_CONTROL */ "", 673 /* AVS_REG_PMB_SLAVE_AVS_ROSC_SVT20_ILVT16_COUNT */ "", 674 /* AVS_REG_PMB_SLAVE_AVS_ROSC_SVT20_THRESHOLD */ "", 675 /* AVS_REG_PMB_SLAVE_AVS_ROSC_S_THRESHOLD */ "", 676 /* AVS_REG_PMB_SLAVE_AVS_ROSC_ULVT16_THRESHOLD */ "", 677 /* AVS_REG_PMB_SLAVE_AVS_ROSC_ULVT16_ULVT20_CONTROL */ "", 678 /* AVS_REG_PMB_SLAVE_AVS_ROSC_ULVT16_ULVT20_COUNT */ "", 679 /* AVS_REG_PMB_SLAVE_AVS_ROSC_ULVT20_THRESHOLD */ "", 680 /* AVS_REG_PMB_SLAVE_BPCM_CAPABILITY */ "", 681 /* AVS_REG_PMB_SLAVE_BPCM_CONTROL */ "", 682 /* AVS_REG_PMB_SLAVE_BPCM_ID */ "", 683 /* AVS_REG_PMB_SLAVE_BPCM_STATUS */ "", 684 /* AVS_REG_PMB_SLAVE_DEVICE_PWRDWN_CONTROL_0 */ "", 685 /* AVS_REG_PMB_SLAVE_DEVICE_PWRDWN_CONTROL_1 */ "", 686 /* AVS_REG_PMB_SLAVE_DEVICE_PWRDWN_CONTROL_2 */ "", 687 /* AVS_REG_PMB_SLAVE_DEVICE_PWRDWN_CONTROL_3 */ "", 688 /* AVS_REG_PVT_MNTR_CONFIG_AVS_TOP_ANALOG_SRAM_INDICATOR */ "", 689 /* AVS_REG_PVT_MNTR_CONFIG_DAC_CODE */ "", 690 /* AVS_REG_PVT_MNTR_CONFIG_DAC_CODE_PROGRAMMING_ENABLE */ "", 691 /* AVS_REG_PVT_MNTR_CONFIG_MAX_DAC_CODE */ "", 692 /* AVS_REG_PVT_MNTR_CONFIG_MIN_DAC_CODE */ "", 693 /* AVS_REG_PVT_MNTR_CONFIG_PVT_MNTR_CTRL */ "", 694 /* AVS_REG_PVT_MNTR_CONFIG_PVT_MNTR_SW_RESETB */ "", 695 /* AVS_REG_PVT_MNTR_CONFIG_PVT_MNTR_TP_MODE_ENABLE */ "", 696 /* AVS_REG_ROSC_THRESHOLD_1_CEN_ROSC_THRESHOLD1_EN_0 */ "", 697 /* AVS_REG_ROSC_THRESHOLD_1_CEN_ROSC_THRESHOLD1_EN_1 */ "", 698 /* AVS_REG_ROSC_THRESHOLD_1_INTERRUPT_STATUS_THRESHOLD1_FAULTY_SENSOR */ "", 699 /* AVS_REG_ROSC_THRESHOLD_1_RMT_ROSC_THRESHOLD1_EN_0 */ "", 700 /* AVS_REG_ROSC_THRESHOLD_1_RMT_ROSC_THRESHOLD1_EN_1 */ "", 701 /* AVS_REG_ROSC_THRESHOLD_1_RMT_ROSC_THRESHOLD1_EN_2 */ "", 702 /* AVS_REG_ROSC_THRESHOLD_1_RMT_ROSC_THRESHOLD1_EN_3 */ "", 703 /* AVS_REG_ROSC_THRESHOLD_1_RMT_ROSC_THRESHOLD1_EN_4 */ "", 704 /* AVS_REG_ROSC_THRESHOLD_1_THRESHOLD1_CEN_ROSC */ "", 705 /* AVS_REG_ROSC_THRESHOLD_1_THRESHOLD1_DIRECTION */ "", 706 /* AVS_REG_ROSC_THRESHOLD_1_THRESHOLD1_RMT_ROSC_G8H */ "", 707 /* AVS_REG_ROSC_THRESHOLD_1_THRESHOLD1_RMT_ROSC_G8S */ "", 708 /* AVS_REG_ROSC_THRESHOLD_1_THRESHOLD1_RMT_ROSC_GH */ "", 709 /* AVS_REG_ROSC_THRESHOLD_1_THRESHOLD1_RMT_ROSC_GS */ "", 710 /* AVS_REG_ROSC_THRESHOLD_2_CEN_ROSC_THRESHOLD2_EN_0 */ "", 711 /* AVS_REG_ROSC_THRESHOLD_2_CEN_ROSC_THRESHOLD2_EN_1 */ "", 712 /* AVS_REG_ROSC_THRESHOLD_2_INTERRUPT_STATUS_THRESHOLD2_FAULTY_SENSOR */ "", 713 /* AVS_REG_ROSC_THRESHOLD_2_RMT_ROSC_THRESHOLD2_EN_0 */ "", 714 /* AVS_REG_ROSC_THRESHOLD_2_RMT_ROSC_THRESHOLD2_EN_1 */ "", 715 /* AVS_REG_ROSC_THRESHOLD_2_RMT_ROSC_THRESHOLD2_EN_2 */ "", 716 /* AVS_REG_ROSC_THRESHOLD_2_RMT_ROSC_THRESHOLD2_EN_3 */ "", 717 /* AVS_REG_ROSC_THRESHOLD_2_RMT_ROSC_THRESHOLD2_EN_4 */ "", 718 /* AVS_REG_ROSC_THRESHOLD_2_THRESHOLD2_CEN_ROSC */ "", 719 /* AVS_REG_ROSC_THRESHOLD_2_THRESHOLD2_DIRECTION */ "", 720 /* AVS_REG_ROSC_THRESHOLD_2_THRESHOLD2_RMT_ROSC_G8H */ "", 721 /* AVS_REG_ROSC_THRESHOLD_2_THRESHOLD2_RMT_ROSC_G8S */ "", 722 /* AVS_REG_ROSC_THRESHOLD_2_THRESHOLD2_RMT_ROSC_GH */ "", 723 /* AVS_REG_ROSC_THRESHOLD_2_THRESHOLD2_RMT_ROSC_GS */ "", 724 /* AVS_REG_RO_REGISTERS_0_CEN_ROSC_ALL_IDL_HI_LOW_ROSCS */ "", 725 /* AVS_REG_RO_REGISTERS_0_CEN_ROSC_STATUS */ "", 726 /* AVS_REG_RO_REGISTERS_0_PVT_0P85V_0_MNTR_STATUS */ "", 727 /* AVS_REG_RO_REGISTERS_0_PVT_0P85V_1_MNTR_STATUS */ "", 728 /* AVS_REG_RO_REGISTERS_0_PVT_1P8V_MNTR_STATUS */ "", 729 /* AVS_REG_RO_REGISTERS_0_PVT_1V_0_MNTR_STATUS */ "", 730 /* AVS_REG_RO_REGISTERS_0_PVT_1V_1_MNTR_STATUS */ "", 731 /* AVS_REG_RO_REGISTERS_0_PVT_3P3V_MNTR_STATUS */ "", 732 /* AVS_REG_RO_REGISTERS_0_PVT_TEMPERATURE_MNTR_STATUS */ "", 733 /* AVS_REG_RO_REGISTERS_0_PVT_TESTMODE_MNTR_STATUS */ "", 734 /* AVS_REG_RO_REGISTERS_1_INTERRUPT_STATUS_FAULTY_POW_WDOG */ "", 735 /* AVS_REG_RO_REGISTERS_1_INTERRUPT_STATUS_FAULTY_POW_WDOG_1 */ "", 736 /* AVS_REG_RO_REGISTERS_1_INTERRUPT_STATUS_FAULTY_POW_WDOG_2 */ "", 737 /* AVS_REG_RO_REGISTERS_1_POW_WDOG_FAILURE_STATUS */ "", 738 /* AVS_REG_RO_REGISTERS_1_RMT_ROSC_STATUS */ "", 739 /* AVS_REG_TEMPERATURE_MONITOR_ENABLE_OVER_TEMPERATURE_RESET */ "", 740 /* AVS_REG_TEMPERATURE_MONITOR_ENABLE_TEMPERATURE_INTERRUPT_SOURCES */ "", 741 /* AVS_REG_TEMPERATURE_MONITOR_SPARE_0 */ "", 742 /* AVS_REG_TEMPERATURE_MONITOR_TEMPERATURE_INTERRUPT_IDLE_TIME */ "", 743 /* AVS_REG_TEMPERATURE_MONITOR_TEMPERATURE_INTERRUPT_TEMPERATURE */ "", 744 /* AVS_REG_TEMPERATURE_MONITOR_TEMPERATURE_INTERRUPT_THRESHOLDS */ "", 745 /* AVS_REG_TEMPERATURE_MONITOR_TEMPERATURE_MEASUREMENT_STATUS */ "", 746 /* AVS_REG_TEMPERATURE_MONITOR_TEMPERATURE_RESET_THRESHOLD */ "", 747 /* AVS_REG_TEMPERATURE_MONITOR_TP_TMON_TEST_ENABLE */ "", 748 /* AVS_REG_TOP_CTRL_AVS_CONVERGENCE_STATUS */ "", 749 /* AVS_REG_TOP_CTRL_AVS_STATUS_IN */ "", 750 /* AVS_REG_TOP_CTRL_AVS_STATUS_OUT */ "", 751 /* AVS_REG_TOP_CTRL_MEMORY_ASSIST */ "", 752 /* AVS_REG_TOP_CTRL_MEMORY_ASSIST_STATUS */ "", 753 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_AFEC0 */ "", 754 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_AFEC1 */ "", 755 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_AFEC2 */ "", 756 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_AFEC3 */ "", 757 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_BSP */ "", 758 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_DIAG_DEC */ "", 759 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_HIF */ "", 760 /* AVS_REG_TOP_CTRL_MEMORY_STANDBY_LEAP */ "", 761 /* AVS_REG_TOP_CTRL_OTP_AVS_INFO */ "", 762 /* AVS_REG_TOP_CTRL_OTP_STATUS */ "", 763 /* AVS_REG_TOP_CTRL_PVT_MNTR1_DAC_CODE */ "", 764 /* AVS_REG_TOP_CTRL_PVT_MNTR2_DAC_CODE */ "", 765 /* AVS_REG_TOP_CTRL_PVT_MNTR3_DAC_CODE */ "", 766 /* AVS_REG_TOP_CTRL_PVT_MNTR4_DAC_CODE */ "", 767 /* AVS_REG_TOP_CTRL_PVT_MNTR5_DAC_CODE */ "", 768 /* AVS_REG_TOP_CTRL_REVID */ "", 769 /* AVS_REG_TOP_CTRL_RMON_HZ */ "", 770 /* AVS_REG_TOP_CTRL_RMON_RAWR_EXT */ "", 771 /* AVS_REG_TOP_CTRL_RMON_RAWR_INT_HZ */ "", 772 /* AVS_REG_TOP_CTRL_RMON_RAWR_INT_VT */ "", 773 /* AVS_REG_TOP_CTRL_RMON_VT */ "", 774 /* AVS_REG_TOP_CTRL_S2_STANDBY_STATUS */ "", 775 /* AVS_REG_TOP_CTRL_SPARE_HIGH */ "", 776 /* AVS_REG_TOP_CTRL_SPARE_LOW */ "", 777 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_AFEC0 */ "", 778 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_AFEC1 */ "", 779 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_AFEC2 */ "", 780 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_AFEC3 */ "", 781 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_AIO */ "", 782 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_BVN */ "", 783 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_BVND */ "", 784 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_DIAG_DEC */ "", 785 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_FSK */ "", 786 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_GFX */ "", 787 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_HVD */ "", 788 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_LEAP */ "", 789 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_M2MC1 */ "", 790 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_MOCAMAC */ "", 791 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_MOCAPHY */ "", 792 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_RAAGA0 */ "", 793 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_SDS0 */ "", 794 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_SDS1 */ "", 795 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_SDS2 */ "", 796 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_SDS3 */ "", 797 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_SID */ "", 798 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_V3D */ "", 799 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_IN_VEC */ "", 800 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_AFEC0 */ "", 801 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_AFEC1 */ "", 802 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_AFEC2 */ "", 803 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_AFEC3 */ "", 804 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_AIO */ "", 805 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_BVN */ "", 806 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_BVND */ "", 807 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_DIAG_DEC */ "", 808 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_FSK */ "", 809 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_GFX */ "", 810 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_HVD */ "", 811 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_LEAP */ "", 812 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_M2MC1 */ "", 813 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_MOCAMAC */ "", 814 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_MOCAPHY */ "", 815 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_RAAGA0 */ "", 816 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_SDS0 */ "", 817 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_SDS1 */ "", 818 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_SDS2 */ "", 819 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_SDS3 */ "", 820 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_SID */ "", 821 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_V3D */ "", 822 /* AVS_REG_TOP_CTRL_SRAM_POWER_GATE_OUT_VEC */ "", 823 /* AVS_REG_TOP_CTRL_START_AVS_CPU */ "", 824 /* AVS_REG_TOP_CTRL_VOLTAGE_REGULATOR_PWRDN */ "", 825 /* AVS_REG_TOP_CTRL_VOLTAGE_REGULATOR_STATUS */ "", 826 /* AVS_REG_TOP_CTRL_VTRAP_STATUS */ "", 827 /* AVS_REG_TOP_CTRL_VTRAP_STATUS_CLEAR */ "", 828 /* AXIIC_A9JTAG_M0_FN_MOD */ "", 829 /* AXIIC_A9JTAG_M0_READ_QOS */ "", 830 /* AXIIC_A9JTAG_M0_WRITE_QOS */ "", 831 /* AXIIC_A9JTAG_S0_FN_MOD_BM_ISS */ "", 832 /* AXIIC_A9JTAG_S0_SECURITY */ "", 833 /* AXIIC_AMAC_FA_M0_AR_B */ "", 834 /* AXIIC_AMAC_FA_M0_AR_P */ "", 835 /* AXIIC_AMAC_FA_M0_AR_R */ "", 836 /* AXIIC_AMAC_FA_M0_AW_B */ "", 837 /* AXIIC_AMAC_FA_M0_AW_P */ "", 838 /* AXIIC_AMAC_FA_M0_AW_R */ "", 839 /* AXIIC_AMAC_FA_M0_FN_MOD */ "", 840 /* AXIIC_AMAC_FA_M0_KI */ "", 841 /* AXIIC_AMAC_FA_M0_MAX_COMB_OT */ "", 842 /* AXIIC_AMAC_FA_M0_MAX_OT */ "", 843 /* AXIIC_AMAC_FA_M0_QOS_CNTL */ "", 844 /* AXIIC_AMAC_FA_M0_QOS_RANGE */ "", 845 /* AXIIC_AMAC_FA_M0_READ_QOS */ "", 846 /* AXIIC_AMAC_FA_M0_TGT_LATENCY */ "", 847 /* AXIIC_AMAC_FA_M0_WRITE_QOS */ "", 848 /* AXIIC_AMAC_FA_M1_AR_B */ "", 849 /* AXIIC_AMAC_FA_M1_AR_P */ "", 850 /* AXIIC_AMAC_FA_M1_AR_R */ "", 851 /* AXIIC_AMAC_FA_M1_AW_B */ "", 852 /* AXIIC_AMAC_FA_M1_AW_P */ "", 853 /* AXIIC_AMAC_FA_M1_AW_R */ "", 854 /* AXIIC_AMAC_FA_M1_FN_MOD */ "", 855 /* AXIIC_AMAC_FA_M1_KI */ "", 856 /* AXIIC_AMAC_FA_M1_MAX_COMB_OT */ "", 857 /* AXIIC_AMAC_FA_M1_MAX_OT */ "", 858 /* AXIIC_AMAC_FA_M1_QOS_CNTL */ "", 859 /* AXIIC_AMAC_FA_M1_QOS_RANGE */ "", 860 /* AXIIC_AMAC_FA_M1_READ_QOS */ "", 861 /* AXIIC_AMAC_FA_M1_TGT_LATENCY */ "", 862 /* AXIIC_AMAC_FA_M1_WRITE_QOS */ "", 863 /* AXIIC_AMAC_M0_AR_B */ "", 864 /* AXIIC_AMAC_M0_AR_P */ "", 865 /* AXIIC_AMAC_M0_AR_R */ "", 866 /* AXIIC_AMAC_M0_AW_B */ "", 867 /* AXIIC_AMAC_M0_AW_P */ "", 868 /* AXIIC_AMAC_M0_AW_R */ "", 869 /* AXIIC_AMAC_M0_FN_MOD */ "", 870 /* AXIIC_AMAC_M0_KI */ "", 871 /* AXIIC_AMAC_M0_MAX_COMB_OT */ "", 872 /* AXIIC_AMAC_M0_MAX_OT */ "", 873 /* AXIIC_AMAC_M0_QOS_CNTL */ "", 874 /* AXIIC_AMAC_M0_QOS_RANGE */ "", 875 /* AXIIC_AMAC_M0_READ_QOS */ "", 876 /* AXIIC_AMAC_M0_TGT_LATENCY */ "", 877 /* AXIIC_AMAC_M0_WRITE_QOS */ "", 878 /* AXIIC_AMAC_M1_AR_B */ "", 879 /* AXIIC_AMAC_M1_AR_P */ "", 880 /* AXIIC_AMAC_M1_AR_R */ "", 881 /* AXIIC_AMAC_M1_AW_B */ "", 882 /* AXIIC_AMAC_M1_AW_P */ "", 883 /* AXIIC_AMAC_M1_AW_R */ "", 884 /* AXIIC_AMAC_M1_FN_MOD */ "", 885 /* AXIIC_AMAC_M1_KI */ "", 886 /* AXIIC_AMAC_M1_MAX_COMB_OT */ "", 887 /* AXIIC_AMAC_M1_MAX_OT */ "", 888 /* AXIIC_AMAC_M1_QOS_CNTL */ "", 889 /* AXIIC_AMAC_M1_QOS_RANGE */ "", 890 /* AXIIC_AMAC_M1_READ_QOS */ "", 891 /* AXIIC_AMAC_M1_TGT_LATENCY */ "", 892 /* AXIIC_AMAC_M1_WRITE_QOS */ "", 893 /* AXIIC_APBR_S0_SECURITY */ "", 894 /* AXIIC_APBS_S0_SECURITY */ "", 895 /* AXIIC_APBV_S0_SECURITY */ "", 896 /* AXIIC_APBW_S0_SECURITY */ "", 897 /* AXIIC_APBX_S0_SECURITY */ "", 898 /* AXIIC_APBY_S0_SECURITY */ "", 899 /* AXIIC_APBZ_S0_SECURITY */ "", 900 /* AXIIC_APB_W1_SECURITY */ "", 901 /* AXIIC_APB_W2_SECURITY */ "", 902 /* AXIIC_APB_W3_SECURITY */ "", 903 /* AXIIC_APB_W4_SECURITY */ "", 904 /* AXIIC_CMCID_M0_AR_B */ "", 905 /* AXIIC_CMCID_M0_AR_P */ "", 906 /* AXIIC_CMCID_M0_AR_R */ "", 907 /* AXIIC_CMCID_M0_AW_B */ "", 908 /* AXIIC_CMCID_M0_AW_P */ "", 909 /* AXIIC_CMCID_M0_AW_R */ "", 910 /* AXIIC_CMCID_M0_FN_MOD */ "", 911 /* AXIIC_CMCID_M0_KI */ "", 912 /* AXIIC_CMCID_M0_MAX_COMB_OT */ "", 913 /* AXIIC_CMCID_M0_MAX_OT */ "", 914 /* AXIIC_CMCID_M0_QOS_CNTL */ "", 915 /* AXIIC_CMCID_M0_QOS_RANGE */ "", 916 /* AXIIC_CMCID_M0_READ_QOS */ "", 917 /* AXIIC_CMCID_M0_TGT_LATENCY */ "", 918 /* AXIIC_CMCID_M0_WRITE_QOS */ "", 919 /* AXIIC_CMICD_M0_AR_B */ "", 920 /* AXIIC_CMICD_M0_AR_P */ "", 921 /* AXIIC_CMICD_M0_AR_R */ "", 922 /* AXIIC_CMICD_M0_AW_B */ "", 923 /* AXIIC_CMICD_M0_AW_P */ "", 924 /* AXIIC_CMICD_M0_AW_R */ "", 925 /* AXIIC_CMICD_M0_FN_MOD */ "", 926 /* AXIIC_CMICD_M0_KI */ "", 927 /* AXIIC_CMICD_M0_MAX_COMB_OT */ "", 928 /* AXIIC_CMICD_M0_MAX_OT */ "", 929 /* AXIIC_CMICD_M0_QOS_CNTL */ "", 930 /* AXIIC_CMICD_M0_QOS_RANGE */ "", 931 /* AXIIC_CMICD_M0_READ_QOS */ "", 932 /* AXIIC_CMICD_M0_TGT_LATENCY */ "", 933 /* AXIIC_CMICD_M0_WRITE_QOS */ "", 934 /* AXIIC_CMICD_S0_FN_MOD_BM_ISS */ "", 935 /* AXIIC_CMICD_S0_SECURITY */ "", 936 /* AXIIC_COMPONENT_ID0 */ "", 937 /* AXIIC_COMPONENT_ID1 */ "", 938 /* AXIIC_COMPONENT_ID2 */ "", 939 /* AXIIC_COMPONENT_ID3 */ "", 940 /* AXIIC_CR5JTAG_M0_READ_QOS */ "", 941 /* AXIIC_CR5JTAG_M0_WRITE_QOS */ "", 942 /* AXIIC_CRYPTO_S0_FN_MOD_BM_ISS */ "", 943 /* AXIIC_CRYPTO_S0_SECURITY */ "", 944 /* AXIIC_DDR_S1_FN_MOD_BM_ISS */ "", 945 /* AXIIC_DDR_S2_FN_MOD_BM_ISS */ "", 946 /* AXIIC_DMA_M0_AR_B */ "", 947 /* AXIIC_DMA_M0_AR_P */ "", 948 /* AXIIC_DMA_M0_AR_R */ "", 949 /* AXIIC_DMA_M0_AW_B */ "", 950 /* AXIIC_DMA_M0_AW_P */ "", 951 /* AXIIC_DMA_M0_AW_R */ "", 952 /* AXIIC_DMA_M0_FN_MOD */ "", 953 /* AXIIC_DMA_M0_KI */ "", 954 /* AXIIC_DMA_M0_MAX_COMB_OT */ "", 955 /* AXIIC_DMA_M0_MAX_OT */ "", 956 /* AXIIC_DMA_M0_QOS_CNTL */ "", 957 /* AXIIC_DMA_M0_QOS_RANGE */ "", 958 /* AXIIC_DMA_M0_READ_QOS */ "", 959 /* AXIIC_DMA_M0_TGT_LATENCY */ "", 960 /* AXIIC_DMA_M0_WRITE_QOS */ "", 961 /* AXIIC_DMU_M0_FN_MOD */ "", 962 /* AXIIC_DMU_M0_READ_QOS */ "", 963 /* AXIIC_DMU_M0_WRITE_QOS */ "", 964 /* AXIIC_DMU_S0_SECURITY */ "", 965 /* AXIIC_DS_0_IDM_ERROR_LOG_ADDR_LSB */ "", 966 /* AXIIC_DS_0_IDM_ERROR_LOG_COMPLETE */ "", 967 /* AXIIC_DS_0_IDM_ERROR_LOG_CONTROL */ "", 968 /* AXIIC_DS_0_IDM_ERROR_LOG_FLAGS */ "", 969 /* AXIIC_DS_0_IDM_ERROR_LOG_ID */ "", 970 /* AXIIC_DS_0_IDM_ERROR_LOG_STATUS */ "", 971 /* AXIIC_DS_0_IDM_INTERRUPT_STATUS */ "", 972 /* AXIIC_DS_0_IDM_RESET_READ_ID */ "", 973 /* AXIIC_DS_0_IDM_RESET_STATUS */ "", 974 /* AXIIC_DS_0_IDM_RESET_WRITE_ID */ "", 975 /* AXIIC_DS_1_IDM_ERROR_LOG_ADDR_LSB */ "", 976 /* AXIIC_DS_1_IDM_ERROR_LOG_COMPLETE */ "", 977 /* AXIIC_DS_1_IDM_ERROR_LOG_CONTROL */ "", 978 /* AXIIC_DS_1_IDM_ERROR_LOG_FLAGS */ "", 979 /* AXIIC_DS_1_IDM_ERROR_LOG_ID */ "", 980 /* AXIIC_DS_1_IDM_ERROR_LOG_STATUS */ "", 981 /* AXIIC_DS_1_IDM_INTERRUPT_STATUS */ "", 982 /* AXIIC_DS_1_IDM_RESET_READ_ID */ "", 983 /* AXIIC_DS_1_IDM_RESET_STATUS */ "", 984 /* AXIIC_DS_1_IDM_RESET_WRITE_ID */ "", 985 /* AXIIC_DS_2_IDM_ERROR_LOG_ADDR_LSB */ "", 986 /* AXIIC_DS_2_IDM_ERROR_LOG_COMPLETE */ "", 987 /* AXIIC_DS_2_IDM_ERROR_LOG_CONTROL */ "", 988 /* AXIIC_DS_2_IDM_ERROR_LOG_FLAGS */ "", 989 /* AXIIC_DS_2_IDM_ERROR_LOG_ID */ "", 990 /* AXIIC_DS_2_IDM_ERROR_LOG_STATUS */ "", 991 /* AXIIC_DS_2_IDM_INTERRUPT_STATUS */ "", 992 /* AXIIC_DS_2_IDM_RESET_READ_ID */ "", 993 /* AXIIC_DS_2_IDM_RESET_STATUS */ "", 994 /* AXIIC_DS_2_IDM_RESET_WRITE_ID */ "", 995 /* AXIIC_DS_3_IDM_ERROR_LOG_ADDR_LSB */ "", 996 /* AXIIC_DS_3_IDM_ERROR_LOG_COMPLETE */ "", 997 /* AXIIC_DS_3_IDM_ERROR_LOG_CONTROL */ "", 998 /* AXIIC_DS_3_IDM_ERROR_LOG_FLAGS */ "", 999 /* AXIIC_DS_3_IDM_ERROR_LOG_ID */ "", 1000 /* AXIIC_DS_3_IDM_ERROR_LOG_STATUS */ "", 1001 /* AXIIC_DS_3_IDM_INTERRUPT_STATUS */ "", 1002 /* AXIIC_DS_3_IDM_RESET_READ_ID */ "", 1003 /* AXIIC_DS_3_IDM_RESET_STATUS */ "", 1004 /* AXIIC_DS_3_IDM_RESET_WRITE_ID */ "", 1005 /* AXIIC_DS_4_IDM_ERROR_LOG_ADDR_LSB */ "", 1006 /* AXIIC_DS_4_IDM_ERROR_LOG_COMPLETE */ "", 1007 /* AXIIC_DS_4_IDM_ERROR_LOG_CONTROL */ "", 1008 /* AXIIC_DS_4_IDM_ERROR_LOG_FLAGS */ "", 1009 /* AXIIC_DS_4_IDM_ERROR_LOG_ID */ "", 1010 /* AXIIC_DS_4_IDM_ERROR_LOG_STATUS */ "", 1011 /* AXIIC_DS_4_IDM_INTERRUPT_STATUS */ "", 1012 /* AXIIC_DS_4_IDM_RESET_READ_ID */ "", 1013 /* AXIIC_DS_4_IDM_RESET_STATUS */ "", 1014 /* AXIIC_DS_4_IDM_RESET_WRITE_ID */ "", 1015 /* AXIIC_EXT_M0_AR_B */ "", 1016 /* AXIIC_EXT_M0_AR_P */ "", 1017 /* AXIIC_EXT_M0_AR_R */ "", 1018 /* AXIIC_EXT_M0_AW_B */ "", 1019 /* AXIIC_EXT_M0_AW_P */ "", 1020 /* AXIIC_EXT_M0_AW_R */ "", 1021 /* AXIIC_EXT_M0_FN_MOD */ "", 1022 /* AXIIC_EXT_M0_KI */ "", 1023 /* AXIIC_EXT_M0_MAX_COMB_OT */ "", 1024 /* AXIIC_EXT_M0_MAX_OT */ "", 1025 /* AXIIC_EXT_M0_QOS_CNTL */ "", 1026 /* AXIIC_EXT_M0_QOS_RANGE */ "", 1027 /* AXIIC_EXT_M0_READ_QOS */ "", 1028 /* AXIIC_EXT_M0_TGT_LATENCY */ "", 1029 /* AXIIC_EXT_M0_WRITE_QOS */ "", 1030 /* AXIIC_EXT_M1_AR_B */ "", 1031 /* AXIIC_EXT_M1_AR_P */ "", 1032 /* AXIIC_EXT_M1_AR_R */ "", 1033 /* AXIIC_EXT_M1_AW_B */ "", 1034 /* AXIIC_EXT_M1_AW_P */ "", 1035 /* AXIIC_EXT_M1_AW_R */ "", 1036 /* AXIIC_EXT_M1_FN_MOD */ "", 1037 /* AXIIC_EXT_M1_KI */ "", 1038 /* AXIIC_EXT_M1_MAX_COMB_OT */ "", 1039 /* AXIIC_EXT_M1_MAX_OT */ "", 1040 /* AXIIC_EXT_M1_QOS_CNTL */ "", 1041 /* AXIIC_EXT_M1_QOS_RANGE */ "", 1042 /* AXIIC_EXT_M1_READ_QOS */ "", 1043 /* AXIIC_EXT_M1_TGT_LATENCY */ "", 1044 /* AXIIC_EXT_M1_WRITE_QOS */ "", 1045 /* AXIIC_EXT_S0_FN_MOD_BM_ISS */ "", 1046 /* AXIIC_EXT_S0_SECURITY */ "", 1047 /* AXIIC_EXT_S1_SECURITY */ "", 1048 /* AXIIC_I2S_M0_FN_MOD */ "", 1049 /* AXIIC_I2S_M0_READ_QOS */ "", 1050 /* AXIIC_I2S_M0_WRITE_QOS */ "", 1051 /* AXIIC_IHOST_ACP_FN_MOD_BM_ISS */ "", 1052 /* AXIIC_IHOST_ACP_SECURITY */ "", 1053 /* AXIIC_IHOST_M0_AR_B */ "", 1054 /* AXIIC_IHOST_M0_AR_P */ "", 1055 /* AXIIC_IHOST_M0_AR_R */ "", 1056 /* AXIIC_IHOST_M0_AW_B */ "", 1057 /* AXIIC_IHOST_M0_AW_P */ "", 1058 /* AXIIC_IHOST_M0_AW_R */ "", 1059 /* AXIIC_IHOST_M0_FN_MOD */ "", 1060 /* AXIIC_IHOST_M0_KI */ "", 1061 /* AXIIC_IHOST_M0_MAX_COMB_OT */ "", 1062 /* AXIIC_IHOST_M0_MAX_OT */ "", 1063 /* AXIIC_IHOST_M0_QOS_CNTL */ "", 1064 /* AXIIC_IHOST_M0_QOS_RANGE */ "", 1065 /* AXIIC_IHOST_M0_READ_QOS */ "", 1066 /* AXIIC_IHOST_M0_TGT_LATENCY */ "", 1067 /* AXIIC_IHOST_M0_WRITE_QOS */ "", 1068 /* AXIIC_IHOST_M1_AR_B */ "", 1069 /* AXIIC_IHOST_M1_AR_P */ "", 1070 /* AXIIC_IHOST_M1_AR_R */ "", 1071 /* AXIIC_IHOST_M1_AW_B */ "", 1072 /* AXIIC_IHOST_M1_AW_P */ "", 1073 /* AXIIC_IHOST_M1_AW_R */ "", 1074 /* AXIIC_IHOST_M1_FN_MOD */ "", 1075 /* AXIIC_IHOST_M1_KI */ "", 1076 /* AXIIC_IHOST_M1_MAX_COMB_OT */ "", 1077 /* AXIIC_IHOST_M1_MAX_OT */ "", 1078 /* AXIIC_IHOST_M1_QOS_CNTL */ "", 1079 /* AXIIC_IHOST_M1_QOS_RANGE */ "", 1080 /* AXIIC_IHOST_M1_READ_QOS */ "", 1081 /* AXIIC_IHOST_M1_TGT_LATENCY */ "", 1082 /* AXIIC_IHOST_M1_WRITE_QOS */ "", 1083 /* AXIIC_IHOST_S0_FN_MOD */ "", 1084 /* AXIIC_IHOST_S0_FN_MOD_BM_ISS */ "", 1085 /* AXIIC_IHOST_S0_SECURITY */ "", 1086 /* AXIIC_JTAG_M0_FN_MOD */ "", 1087 /* AXIIC_JTAG_M0_READ_QOS */ "", 1088 /* AXIIC_JTAG_M0_WRITE_QOS */ "", 1089 /* AXIIC_MHOST0_M0_AR_B */ "", 1090 /* AXIIC_MHOST0_M0_AR_P */ "", 1091 /* AXIIC_MHOST0_M0_AR_R */ "", 1092 /* AXIIC_MHOST0_M0_AW_B */ "", 1093 /* AXIIC_MHOST0_M0_AW_P */ "", 1094 /* AXIIC_MHOST0_M0_AW_R */ "", 1095 /* AXIIC_MHOST0_M0_FN_MOD */ "", 1096 /* AXIIC_MHOST0_M0_KI */ "", 1097 /* AXIIC_MHOST0_M0_MAX_COMB_OT */ "", 1098 /* AXIIC_MHOST0_M0_MAX_OT */ "", 1099 /* AXIIC_MHOST0_M0_QOS_CNTL */ "", 1100 /* AXIIC_MHOST0_M0_QOS_RANGE */ "", 1101 /* AXIIC_MHOST0_M0_READ_QOS */ "", 1102 /* AXIIC_MHOST0_M0_TGT_LATENCY */ "", 1103 /* AXIIC_MHOST0_M0_WRITE_QOS */ "", 1104 /* AXIIC_MHOST0_S0_FN_MOD_BM_ISS */ "", 1105 /* AXIIC_MHOST0_S0_SECURITY */ "", 1106 /* AXIIC_MHOST1_M0_AR_B */ "", 1107 /* AXIIC_MHOST1_M0_AR_P */ "", 1108 /* AXIIC_MHOST1_M0_AR_R */ "", 1109 /* AXIIC_MHOST1_M0_AW_B */ "", 1110 /* AXIIC_MHOST1_M0_AW_P */ "", 1111 /* AXIIC_MHOST1_M0_AW_R */ "", 1112 /* AXIIC_MHOST1_M0_FN_MOD */ "", 1113 /* AXIIC_MHOST1_M0_KI */ "", 1114 /* AXIIC_MHOST1_M0_MAX_COMB_OT */ "", 1115 /* AXIIC_MHOST1_M0_MAX_OT */ "", 1116 /* AXIIC_MHOST1_M0_QOS_CNTL */ "", 1117 /* AXIIC_MHOST1_M0_QOS_RANGE */ "", 1118 /* AXIIC_MHOST1_M0_READ_QOS */ "", 1119 /* AXIIC_MHOST1_M0_TGT_LATENCY */ "", 1120 /* AXIIC_MHOST1_M0_WRITE_QOS */ "", 1121 /* AXIIC_MHOST1_S0_FN_MOD_BM_ISS */ "", 1122 /* AXIIC_MHOST1_S0_SECURITY */ "", 1123 /* AXIIC_NAND_S0_FN_MOD_BM_ISS */ "", 1124 /* AXIIC_NAND_S0_SECURITY */ "", 1125 /* AXIIC_PCIE0_M0_AR_B */ "", 1126 /* AXIIC_PCIE0_M0_AR_P */ "", 1127 /* AXIIC_PCIE0_M0_AR_R */ "", 1128 /* AXIIC_PCIE0_M0_AW_B */ "", 1129 /* AXIIC_PCIE0_M0_AW_P */ "", 1130 /* AXIIC_PCIE0_M0_AW_R */ "", 1131 /* AXIIC_PCIE0_M0_FN_MOD */ "", 1132 /* AXIIC_PCIE0_M0_KI */ "", 1133 /* AXIIC_PCIE0_M0_MAX_COMB_OT */ "", 1134 /* AXIIC_PCIE0_M0_MAX_OT */ "", 1135 /* AXIIC_PCIE0_M0_QOS_CNTL */ "", 1136 /* AXIIC_PCIE0_M0_QOS_RANGE */ "", 1137 /* AXIIC_PCIE0_M0_READ_QOS */ "", 1138 /* AXIIC_PCIE0_M0_TGT_LATENCY */ "", 1139 /* AXIIC_PCIE0_M0_WRITE_QOS */ "", 1140 /* AXIIC_PCIE0_S0_FN_MOD_BM_ISS */ "", 1141 /* AXIIC_PCIE0_S0_SECURITY */ "", 1142 /* AXIIC_PCIE1_M0_AR_B */ "", 1143 /* AXIIC_PCIE1_M0_AR_P */ "", 1144 /* AXIIC_PCIE1_M0_AR_R */ "", 1145 /* AXIIC_PCIE1_M0_AW_B */ "", 1146 /* AXIIC_PCIE1_M0_AW_P */ "", 1147 /* AXIIC_PCIE1_M0_AW_R */ "", 1148 /* AXIIC_PCIE1_M0_FN_MOD */ "", 1149 /* AXIIC_PCIE1_M0_KI */ "", 1150 /* AXIIC_PCIE1_M0_MAX_COMB_OT */ "", 1151 /* AXIIC_PCIE1_M0_MAX_OT */ "", 1152 /* AXIIC_PCIE1_M0_QOS_CNTL */ "", 1153 /* AXIIC_PCIE1_M0_QOS_RANGE */ "", 1154 /* AXIIC_PCIE1_M0_READ_QOS */ "", 1155 /* AXIIC_PCIE1_M0_TGT_LATENCY */ "", 1156 /* AXIIC_PCIE1_M0_WRITE_QOS */ "", 1157 /* AXIIC_PCIE1_S0_FN_MOD_BM_ISS */ "", 1158 /* AXIIC_PCIE1_S0_SECURITY */ "", 1159 /* AXIIC_PCIE2_M0_AR_B */ "", 1160 /* AXIIC_PCIE2_M0_AR_P */ "", 1161 /* AXIIC_PCIE2_M0_AR_R */ "", 1162 /* AXIIC_PCIE2_M0_AW_B */ "", 1163 /* AXIIC_PCIE2_M0_AW_P */ "", 1164 /* AXIIC_PCIE2_M0_AW_R */ "", 1165 /* AXIIC_PCIE2_M0_FN_MOD */ "", 1166 /* AXIIC_PCIE2_M0_KI */ "", 1167 /* AXIIC_PCIE2_M0_MAX_COMB_OT */ "", 1168 /* AXIIC_PCIE2_M0_MAX_OT */ "", 1169 /* AXIIC_PCIE2_M0_QOS_CNTL */ "", 1170 /* AXIIC_PCIE2_M0_QOS_RANGE */ "", 1171 /* AXIIC_PCIE2_M0_READ_QOS */ "", 1172 /* AXIIC_PCIE2_M0_TGT_LATENCY */ "", 1173 /* AXIIC_PCIE2_M0_WRITE_QOS */ "", 1174 /* AXIIC_PCIE2_S0_FN_MOD_BM_ISS */ "", 1175 /* AXIIC_PCIE2_S0_SECURITY */ "", 1176 /* AXIIC_PERIPHERAL_ID0 */ "", 1177 /* AXIIC_PERIPHERAL_ID1 */ "", 1178 /* AXIIC_PERIPHERAL_ID2 */ "", 1179 /* AXIIC_PERIPHERAL_ID3 */ "", 1180 /* AXIIC_PERIPHERAL_ID4 */ "", 1181 /* AXIIC_PERIPHERAL_ID5 */ "", 1182 /* AXIIC_PERIPHERAL_ID6 */ "", 1183 /* AXIIC_PERIPHERAL_ID7 */ "", 1184 /* AXIIC_PNOR_S0_FN_MOD_BM_ISS */ "", 1185 /* AXIIC_PNOR_S0_SECURITY */ "", 1186 /* AXIIC_QSPI_S0_FN_MOD_BM_ISS */ "", 1187 /* AXIIC_QSPI_S0_SECURITY */ "", 1188 /* AXIIC_REMAP */ "", 1189 /* AXIIC_ROM_S0_FN_MOD_BM_ISS */ "", 1190 /* AXIIC_ROM_S0_SECURITY */ "", 1191 /* AXIIC_RTS_M0_AR_B */ "", 1192 /* AXIIC_RTS_M0_AR_P */ "", 1193 /* AXIIC_RTS_M0_AR_R */ "", 1194 /* AXIIC_RTS_M0_AW_B */ "", 1195 /* AXIIC_RTS_M0_AW_P */ "", 1196 /* AXIIC_RTS_M0_AW_R */ "", 1197 /* AXIIC_RTS_M0_FN_MOD */ "", 1198 /* AXIIC_RTS_M0_KI */ "", 1199 /* AXIIC_RTS_M0_MAX_COMB_OT */ "", 1200 /* AXIIC_RTS_M0_MAX_OT */ "", 1201 /* AXIIC_RTS_M0_QOS_CNTL */ "", 1202 /* AXIIC_RTS_M0_QOS_RANGE */ "", 1203 /* AXIIC_RTS_M0_READ_QOS */ "", 1204 /* AXIIC_RTS_M0_TGT_LATENCY */ "", 1205 /* AXIIC_RTS_M0_WRITE_QOS */ "", 1206 /* AXIIC_RTS_S0_FN_MOD_BM_ISS */ "", 1207 /* AXIIC_SATA_M0_AR_B */ "", 1208 /* AXIIC_SATA_M0_AR_P */ "", 1209 /* AXIIC_SATA_M0_AR_R */ "", 1210 /* AXIIC_SATA_M0_AW_B */ "", 1211 /* AXIIC_SATA_M0_AW_P */ "", 1212 /* AXIIC_SATA_M0_AW_R */ "", 1213 /* AXIIC_SATA_M0_FN_MOD */ "", 1214 /* AXIIC_SATA_M0_KI */ "", 1215 /* AXIIC_SATA_M0_MAX_COMB_OT */ "", 1216 /* AXIIC_SATA_M0_MAX_OT */ "", 1217 /* AXIIC_SATA_M0_QOS_CNTL */ "", 1218 /* AXIIC_SATA_M0_QOS_RANGE */ "", 1219 /* AXIIC_SATA_M0_READ_QOS */ "", 1220 /* AXIIC_SATA_M0_TGT_LATENCY */ "", 1221 /* AXIIC_SATA_M0_WRITE_QOS */ "", 1222 /* AXIIC_SDIO_M0_AR_B */ "", 1223 /* AXIIC_SDIO_M0_AR_P */ "", 1224 /* AXIIC_SDIO_M0_AR_R */ "", 1225 /* AXIIC_SDIO_M0_AW_B */ "", 1226 /* AXIIC_SDIO_M0_AW_P */ "", 1227 /* AXIIC_SDIO_M0_AW_R */ "", 1228 /* AXIIC_SDIO_M0_FN_MOD */ "", 1229 /* AXIIC_SDIO_M0_KI */ "", 1230 /* AXIIC_SDIO_M0_MAX_COMB_OT */ "", 1231 /* AXIIC_SDIO_M0_MAX_OT */ "", 1232 /* AXIIC_SDIO_M0_QOS_CNTL */ "", 1233 /* AXIIC_SDIO_M0_QOS_RANGE */ "", 1234 /* AXIIC_SDIO_M0_READ_QOS */ "", 1235 /* AXIIC_SDIO_M0_TGT_LATENCY */ "", 1236 /* AXIIC_SDIO_M0_WRITE_QOS */ "", 1237 /* AXIIC_SDIO_M1_AR_B */ "", 1238 /* AXIIC_SDIO_M1_AR_P */ "", 1239 /* AXIIC_SDIO_M1_AR_R */ "", 1240 /* AXIIC_SDIO_M1_AW_B */ "", 1241 /* AXIIC_SDIO_M1_AW_P */ "", 1242 /* AXIIC_SDIO_M1_AW_R */ "", 1243 /* AXIIC_SDIO_M1_FN_MOD */ "", 1244 /* AXIIC_SDIO_M1_KI */ "", 1245 /* AXIIC_SDIO_M1_MAX_COMB_OT */ "", 1246 /* AXIIC_SDIO_M1_MAX_OT */ "", 1247 /* AXIIC_SDIO_M1_QOS_CNTL */ "", 1248 /* AXIIC_SDIO_M1_QOS_RANGE */ "", 1249 /* AXIIC_SDIO_M1_READ_QOS */ "", 1250 /* AXIIC_SDIO_M1_TGT_LATENCY */ "", 1251 /* AXIIC_SDIO_M1_WRITE_QOS */ "", 1252 /* AXIIC_SMAU_S0_FN_MOD_BM_ISS */ "", 1253 /* AXIIC_SRAM_S0_FN_MOD */ "", 1254 /* AXIIC_SRAM_S0_FN_MOD_BM_ISS */ "", 1255 /* AXIIC_USB2D_M0_AR_B */ "", 1256 /* AXIIC_USB2D_M0_AR_P */ "", 1257 /* AXIIC_USB2D_M0_AR_R */ "", 1258 /* AXIIC_USB2D_M0_AW_B */ "", 1259 /* AXIIC_USB2D_M0_AW_P */ "", 1260 /* AXIIC_USB2D_M0_AW_R */ "", 1261 /* AXIIC_USB2D_M0_FN_MOD */ "", 1262 /* AXIIC_USB2D_M0_KI */ "", 1263 /* AXIIC_USB2D_M0_MAX_COMB_OT */ "", 1264 /* AXIIC_USB2D_M0_MAX_OT */ "", 1265 /* AXIIC_USB2D_M0_QOS_CNTL */ "", 1266 /* AXIIC_USB2D_M0_QOS_RANGE */ "", 1267 /* AXIIC_USB2D_M0_READ_QOS */ "", 1268 /* AXIIC_USB2D_M0_TGT_LATENCY */ "", 1269 /* AXIIC_USB2D_M0_WRITE_QOS */ "", 1270 /* AXIIC_USB2H_M0_AR_B */ "", 1271 /* AXIIC_USB2H_M0_AR_P */ "", 1272 /* AXIIC_USB2H_M0_AR_R */ "", 1273 /* AXIIC_USB2H_M0_AW_B */ "", 1274 /* AXIIC_USB2H_M0_AW_P */ "", 1275 /* AXIIC_USB2H_M0_AW_R */ "", 1276 /* AXIIC_USB2H_M0_FN_MOD */ "", 1277 /* AXIIC_USB2H_M0_KI */ "", 1278 /* AXIIC_USB2H_M0_MAX_COMB_OT */ "", 1279 /* AXIIC_USB2H_M0_MAX_OT */ "", 1280 /* AXIIC_USB2H_M0_QOS_CNTL */ "", 1281 /* AXIIC_USB2H_M0_QOS_RANGE */ "", 1282 /* AXIIC_USB2H_M0_READ_QOS */ "", 1283 /* AXIIC_USB2H_M0_TGT_LATENCY */ "", 1284 /* AXIIC_USB2H_M0_WRITE_QOS */ "", 1285 /* AXIIC_USB3H_M0_AR_B */ "", 1286 /* AXIIC_USB3H_M0_AR_P */ "", 1287 /* AXIIC_USB3H_M0_AR_R */ "", 1288 /* AXIIC_USB3H_M0_AW_B */ "", 1289 /* AXIIC_USB3H_M0_AW_P */ "", 1290 /* AXIIC_USB3H_M0_AW_R */ "", 1291 /* AXIIC_USB3H_M0_FN_MOD */ "", 1292 /* AXIIC_USB3H_M0_KI */ "", 1293 /* AXIIC_USB3H_M0_MAX_COMB_OT */ "", 1294 /* AXIIC_USB3H_M0_MAX_OT */ "", 1295 /* AXIIC_USB3H_M0_QOS_CNTL */ "", 1296 /* AXIIC_USB3H_M0_QOS_RANGE */ "", 1297 /* AXIIC_USB3H_M0_READ_QOS */ "", 1298 /* AXIIC_USB3H_M0_TGT_LATENCY */ "", 1299 /* AXIIC_USB3H_M0_WRITE_QOS */ "", 1300 /* AXI_PCIE_M0_IDM_IDM_INTERRUPT_STATUS */ "", 1301 /* AXI_PCIE_M0_IDM_IDM_RESET_STATUS */ "", 1302 /* AXI_PCIE_M0_IDM_IO_CONTROL_DIRECT */ "", 1303 /* AXI_PCIE_M0_IDM_IO_STATUS */ "", 1304 /* AXI_PCIE_M0_IDM_M_IDM_RESET_CONTROL */ "", 1305 /* AXI_PCIE_M1_IDM_IDM_INTERRUPT_STATUS */ "", 1306 /* AXI_PCIE_M1_IDM_IDM_RESET_STATUS */ "", 1307 /* AXI_PCIE_M1_IDM_IO_CONTROL_DIRECT */ "", 1308 /* AXI_PCIE_M1_IDM_IO_STATUS */ "", 1309 /* AXI_PCIE_M1_IDM_M_IDM_RESET_CONTROL */ "", 1310 /* AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 1311 /* AXI_PCIE_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 1312 /* AXI_PCIE_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 1313 /* AXI_PCIE_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 1314 /* AXI_PCIE_S0_IDM_IDM_ERROR_LOG_ID */ "", 1315 /* AXI_PCIE_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 1316 /* AXI_PCIE_S0_IDM_IDM_INTERRUPT_STATUS */ "", 1317 /* AXI_PCIE_S0_IDM_IDM_RESET_READ_ID */ "", 1318 /* AXI_PCIE_S0_IDM_IDM_RESET_STATUS */ "", 1319 /* AXI_PCIE_S0_IDM_IDM_RESET_WRITE_ID */ "", 1320 /* AXI_PCIE_S0_IDM_S_IDM_RESET_CONTROL */ "", 1321 /* AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 1322 /* AXI_PCIE_S1_IDM_IDM_ERROR_LOG_COMPLETE */ "", 1323 /* AXI_PCIE_S1_IDM_IDM_ERROR_LOG_CONTROL */ "", 1324 /* AXI_PCIE_S1_IDM_IDM_ERROR_LOG_FLAGS */ "", 1325 /* AXI_PCIE_S1_IDM_IDM_ERROR_LOG_ID */ "", 1326 /* AXI_PCIE_S1_IDM_IDM_ERROR_LOG_STATUS */ "", 1327 /* AXI_PCIE_S1_IDM_IDM_INTERRUPT_STATUS */ "", 1328 /* AXI_PCIE_S1_IDM_IDM_RESET_READ_ID */ "", 1329 /* AXI_PCIE_S1_IDM_IDM_RESET_STATUS */ "", 1330 /* AXI_PCIE_S1_IDM_IDM_RESET_WRITE_ID */ "", 1331 /* AXI_PCIE_S1_IDM_S_IDM_RESET_CONTROL */ "", 1332 /* AXI_SRAM_MEMC_CONFIG */ "", 1333 /* AXP_CH_DEBUG_PKT_DROP */ "", 1334 /* AXP_CH_INBUF_ECC_CONTROL */ "", 1335 /* AXP_CH_INBUF_ECC_STATUS_INTR */ "", 1336 /* AXP_CH_INT_MASK */ "", 1337 /* AXP_CH_INT_STATUS */ "", 1338 /* AXP_CH_IP_CREDIT_COUNT */ "", 1339 /* AXP_CH_LCL_INT_MASK */ "", 1340 /* AXP_CH_LCL_INT_STATUS */ "", 1341 /* AXP_CH_MAX_MMU_REQ */ "", 1342 /* AXP_CH_MEM_CONTROL */ "", 1343 /* AXP_CH_MMU_REQ_COUNT */ "", 1344 /* AXP_CH_MMU_REQ_EN */ "", 1345 /* AXP_CH_NLFIB_CREDIT_COUNT */ "", 1346 /* AXP_CH_NLFIB_PTR */ "", 1347 /* AXP_CH_NLFOB_CREDIT_COUNT */ "", 1348 /* AXP_CH_NLFOB_CTRL */ "", 1349 /* AXP_CH_NLF_CLK_DISABLE */ "", 1350 /* AXP_CH_NLF_FLUSH */ "", 1351 /* AXP_CH_NLF_PORT_MAPPING */ "", 1352 /* AXP_CH_OUTPUT_ARB_CONTROL */ "", 1353 /* AXP_CH_OUTPUT_ARB_STRICTP */ "", 1354 /* AXP_CH_OUTPUT_ARB_WERR */ "", 1355 /* AXP_SM_BULK_CLEAR_CONTROL0 */ "", 1356 /* AXP_SM_BULK_CLEAR_CONTROL1 */ "", 1357 /* AXP_SM_BULK_CLEAR_STATUS */ "", 1358 /* AXP_SM_BYTES_MATCHED_COUNTER */ "", 1359 /* AXP_SM_CHAR_REMAP_ECC_INTR_ENABLE_CONTROL */ "", 1360 /* AXP_SM_CHAR_REMAP_ECC_INTR_STATUS */ "", 1361 /* AXP_SM_DEBUG_BESTMATCH_STATUS */ "", 1362 /* AXP_SM_DEBUG_FLAGDATA_STATUS */ "", 1363 /* AXP_SM_DEBUG_FLOWDATA_STATUS0 */ "", 1364 /* AXP_SM_DEBUG_FLOWDATA_STATUS1 */ "", 1365 /* AXP_SM_DEBUG_HEADERDATA_STATUS0 */ "", 1366 /* AXP_SM_DEBUG_HEADERDATA_STATUS1 */ "", 1367 /* AXP_SM_DEBUG_MATCHBUF_STATUS */ "", 1368 /* AXP_SM_DEBUG_MATCHDATA_STATUS */ "", 1369 /* AXP_SM_DEBUG_MATCH_PROC_CONTROL */ "", 1370 /* AXP_SM_DEBUG_METADATA_STATUS0 */ "", 1371 /* AXP_SM_DEBUG_METADATA_STATUS1 */ "", 1372 /* AXP_SM_DEBUG_METADATA_STATUS2 */ "", 1373 /* AXP_SM_DEBUG_METADATA_STATUS3 */ "", 1374 /* AXP_SM_DEBUG_PACKET_BUFFER_CONTROL */ "", 1375 /* AXP_SM_DEBUG_PACKET_BUFFER_STATUS */ "", 1376 /* AXP_SM_DEBUG_REGEX_CONTROL */ "", 1377 /* AXP_SM_DEBUG_REGEX_PAUSE_CONTROL0 */ "", 1378 /* AXP_SM_DEBUG_REGEX_PAUSE_CONTROL1 */ "", 1379 /* AXP_SM_DEBUG_REGEX_PAUSE_STATUS */ "", 1380 /* AXP_SM_ECC_ERROR_COUNTER */ "", 1381 /* AXP_SM_FLOW_DONE_PACKET_DROP_COUNTER */ "", 1382 /* AXP_SM_FLOW_PACKET_NUM_ERROR_COUNTER */ "", 1383 /* AXP_SM_FLOW_TABLE_ECC_INTR_ENABLE_CONTROL */ "", 1384 /* AXP_SM_FLOW_TABLE_ECC_INTR_STATUS */ "", 1385 /* AXP_SM_FLOW_TIMESTAMP_ERROR_COUNTER */ "", 1386 /* AXP_SM_FLOW_TRACKER_ERROR_COUNTER */ "", 1387 /* AXP_SM_FRAGMENTS_RECEIVED_COUNTER */ "", 1388 /* AXP_SM_IN_PACKET_ERROR_COUNTER */ "", 1389 /* AXP_SM_L4_CHECKSUM_ERROR_COUNTER */ "", 1390 /* AXP_SM_MATCHED_FLOWS_COUNTER */ "", 1391 /* AXP_SM_MATCH_COUNTER_ECC_INTR_ENABLE_CONTROL */ "", 1392 /* AXP_SM_MATCH_COUNTER_ECC_INTR_STATUS */ "", 1393 /* AXP_SM_MATCH_TABLE_ECC_INTR_ENABLE_CONTROL */ "", 1394 /* AXP_SM_MATCH_TABLE_ECC_INTR_STATUS */ "", 1395 /* AXP_SM_MEMORY_BULK_RESET */ "", 1396 /* AXP_SM_MEM_ECC_GEN_CONTROL */ "", 1397 /* AXP_SM_MEM_PDA_CONTROL */ "", 1398 /* AXP_SM_MEM_TM_CONTROL */ "", 1399 /* AXP_SM_PACKETS_DROPPED_COUNTER */ "", 1400 /* AXP_SM_PACKETS_RECEIVED_COUNTER */ "", 1401 /* AXP_SM_PACKETS_SENT_COUNTER */ "", 1402 /* AXP_SM_PACKET_BUFFER_ECC_INTR_ENABLE_CONTROL */ "", 1403 /* AXP_SM_PACKET_BUFFER_ECC_INTR_STATUS */ "", 1404 /* AXP_SM_PACKET_LENGTH_ERROR_COUNTER */ "", 1405 /* AXP_SM_REGEX_CONTROL0 */ "", 1406 /* AXP_SM_REGEX_CONTROL1 */ "", 1407 /* AXP_SM_REGEX_CONTROL2 */ "", 1408 /* AXP_SM_REGEX_CONTROL3 */ "", 1409 /* AXP_SM_REGEX_CONTROL4 */ "", 1410 /* AXP_SM_REGEX_STATE_INTR_ENABLE_CONTROL */ "", 1411 /* AXP_SM_REGEX_STATE_INTR_STATUS0 */ "", 1412 /* AXP_SM_REGEX_STATE_INTR_STATUS1 */ "", 1413 /* AXP_SM_REGEX_STATUS0 */ "", 1414 /* AXP_SM_REGEX_STATUS1 */ "", 1415 /* AXP_SM_REGEX_STATUS2 */ "", 1416 /* AXP_SM_REPORT_PACKET_CONTROL0 */ "", 1417 /* AXP_SM_REPORT_PACKET_CONTROL1 */ "", 1418 /* AXP_SM_REPORT_PACKET_CONTROL2 */ "", 1419 /* AXP_SM_REPORT_PACKET_CONTROL3 */ "", 1420 /* AXP_SM_SIGNATURE_MATCH_ACTIVE_STATUS0 */ "", 1421 /* AXP_SM_SIGNATURE_MATCH_ACTIVE_STATUS1 */ "", 1422 /* AXP_SM_SIGNATURE_MATCH_CONTROL */ "", 1423 /* AXP_SM_SIGNATURE_MATCH_INTR_ENABLE_CONTROL */ "", 1424 /* AXP_SM_SIGNATURE_MATCH_INTR_STATUS */ "", 1425 /* AXP_SM_STATE_TABLE_ECC_INTR_ENABLE_CONTROL */ "", 1426 /* AXP_SM_STATE_TABLE_ECC_INTR_STATUS */ "", 1427 /* AXP_SM_TOTAL_CROSS_SIG_FLAGS_COUNTER */ "", 1428 /* AXP_SM_TOTAL_MATCH_COUNTER */ "", 1429 /* AXP_SM_UNMATCHED_FLOWS_COUNTER */ "", 1430 /* AXP_WRX_CREDIT_CNT */ "", 1431 /* AXP_WRX_DEBUG1 */ "", 1432 /* AXP_WRX_ERR_PKT_DROP_STAT_CNT */ "", 1433 /* AXP_WRX_ERR_STAT_CNT */ "", 1434 /* AXP_WRX_INTR_ENABLE */ "", 1435 /* AXP_WRX_INTR_STATUS */ "", 1436 /* AXP_WRX_MASTER_CTRL */ "", 1437 /* AXP_WRX_MEMORY_BULK_RESET */ "", 1438 /* AXP_WRX_MEMORY_TM */ "", 1439 /* AXP_WRX_PARITY_CONTROL */ "", 1440 /* AXP_WRX_PKT_IN_STAT_CNT */ "", 1441 /* AXP_WRX_PKT_OUT_STAT_CNT */ "", 1442 /* AXP_WRX_REASSEEMBLY_MAX_LAPSE_TIME */ "", 1443 /* AXP_WRX_REASSEMBLED_PKT_STAT_CNT */ "", 1444 /* AXP_WRX_SVP_HASH_CTRL */ "", 1445 /* AXP_WRX_SVP_PARITY_STATUS_INTR */ "", 1446 /* AXP_WRX_SVP_PARITY_STATUS_NACK */ "", 1447 /* AXP_WRX_WCD_HASH_CTRL */ "", 1448 /* AXP_WRX_WCD_PARITY_STATUS_INTR */ "", 1449 /* AXP_WRX_WCD_PARITY_STATUS_NACK */ "", 1450 /* AXP_WTX_COPY_TO_CPU_COUNT */ "", 1451 /* AXP_WTX_DSCP_MAP_PAR_STATUS_INTR */ "", 1452 /* AXP_WTX_DSCP_MAP_PAR_STATUS_NACK */ "", 1453 /* AXP_WTX_DVP_PROFILE_ECC_STATUS_INTR */ "", 1454 /* AXP_WTX_DVP_PROFILE_ECC_STATUS_NACK */ "", 1455 /* AXP_WTX_ENCAP_CONFIG */ "", 1456 /* AXP_WTX_ERR_CHK_EN */ "", 1457 /* AXP_WTX_FRAG_COUNT */ "", 1458 /* AXP_WTX_FRAG_ID_PAR_STATUS_INTR */ "", 1459 /* AXP_WTX_FRAG_ID_PAR_STATUS_NACK */ "", 1460 /* AXP_WTX_ICREDIT_CTL */ "", 1461 /* AXP_WTX_INBUF_CREDIT_COUNT */ "", 1462 /* AXP_WTX_INT_MASK */ "", 1463 /* AXP_WTX_INT_STATUS */ "", 1464 /* AXP_WTX_LKUP_DROP_COUNT */ "", 1465 /* AXP_WTX_MEMORY_BULK_RESET */ "", 1466 /* AXP_WTX_MEM_CONTROL_0 */ "", 1467 /* AXP_WTX_MEM_CONTROL_1 */ "", 1468 /* AXP_WTX_MEM_PDA_CONTROL */ "", 1469 /* AXP_WTX_MTU_DROP_COUNT */ "", 1470 /* AXP_WTX_OUTBUF_CREDIT_COUNT */ "", 1471 /* AXP_WTX_OUTBUF_FLOW_CTL */ "", 1472 /* AXP_WTX_PRI_MAP_PAR_STATUS_INTR */ "", 1473 /* AXP_WTX_PRI_MAP_PAR_STATUS_NACK */ "", 1474 /* AXP_WTX_SOFT_RESET */ "", 1475 /* AXP_WTX_TRUNK_BLOCK_MASK_PAR_STATUS_INTR */ "", 1476 /* AXP_WTX_TRUNK_BLOCK_MASK_PAR_STATUS_NACK */ "", 1477 /* AXP_WTX_TRUNK_DROP_COUNT */ "", 1478 /* AXP_WTX_TRUNK_GROUP_BITMAP_PAR_STATUS_INTR */ "", 1479 /* AXP_WTX_TRUNK_GROUP_BITMAP_PAR_STATUS_NACK */ "", 1480 /* AXP_WTX_TUNNEL_ECC_STATUS_INTR */ "", 1481 /* AXP_WTX_TUNNEL_ECC_STATUS_NACK */ "", 1482 /* AXP_WTX_TUNNEL_ID_MASK */ "", 1483 /* AXP_WTX_TUNNEL_TPID */ "", 1484 /* BASE_TIME_FRAC */ "", 1485 /* BASE_TIME_SEC */ "", 1486 /* BCAST_BLOCK_MASK */ "", 1487 /* BCAST_BLOCK_MASK_64 */ "BCAST_BLOCK_MASK", 1488 /* BCAST_BLOCK_MASK_HI */ "", 1489 /* BCAST_BLOCK_MASK_HI_64 */ "BCAST_BLOCK_MASK_HI_64", 1490 /* BCAST_BLOCK_MASK_LO_64 */ "BCAST_BLOCK_MASK_LO_64", 1491 /* BCAST_BLOCK_MASK_PARITY_CONTROL */ "", 1492 /* BCAST_BLOCK_MASK_PARITY_STATUS_INTR */ "", 1493 /* BCAST_BLOCK_MASK_PARITY_STATUS_NACK */ "", 1494 /* BCAST_STORM_CONTROL */ "", 1495 /* BDM_BDB_CONFIG */ "", 1496 /* BDM_BDB_STATUS */ "", 1497 /* BDM_BD_DATA_DEBUG */ "", 1498 /* BDM_ECC_1B_ERR_CNT */ "", 1499 /* BDM_ECC_2B_ERR_CNT */ "", 1500 /* BDM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 1501 /* BDM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 1502 /* BDM_ECC_INTERRUPT_REGISTER */ "", 1503 /* BDM_ECC_INTERRUPT_REGISTER_MASK */ "", 1504 /* BDM_ECC_INTERRUPT_REGISTER_TEST */ "", 1505 /* BDM_ERROR_INITIATION_DATA */ "", 1506 /* BDM_FPC_CONFIG */ "", 1507 /* BDM_FPC_CONTROL */ "", 1508 /* BDM_FPC_DELETE */ "", 1509 /* BDM_FPC_MODULE_STATUS */ "", 1510 /* BDM_FPC_STATUS */ "", 1511 /* BDM_GTIMER_CONFIGURATION */ "", 1512 /* BDM_GTIMER_CYCLE */ "", 1513 /* BDM_INTERRUPT_MASK_REGISTER */ "", 1514 /* BDM_INTERRUPT_REGISTER */ "", 1515 /* BDM_INTERRUPT_REGISTER_TEST */ "", 1516 /* BDM_PCMI_0 */ "", 1517 /* BDM_PCMI_1 */ "", 1518 /* BDM_PCMI_2 */ "", 1519 /* BDM_PCMI_3 */ "", 1520 /* BDM_PCMI_4 */ "", 1521 /* BDM_PCMI_0_S */ "", 1522 /* BDM_PCMI_0_T */ "", 1523 /* BDM_PCMI_1_S */ "", 1524 /* BDM_PCMI_1_T */ "", 1525 /* BDM_PCMI_2_S */ "", 1526 /* BDM_PCMI_2_T */ "", 1527 /* BDM_PCMI_3_S */ "", 1528 /* BDM_PCMI_3_T */ "", 1529 /* BDM_PCMI_4_S */ "", 1530 /* BDM_PCMI_4_T */ "", 1531 /* BDM_REG_00A4 */ "", 1532 /* BDM_REG_00A6 */ "", 1533 /* BDM_REG_00C2 */ "", 1534 /* BDM_RESERVED_MIRROR_ADDR */ "", 1535 /* BDM_RESERVED_MTCD */ "", 1536 /* BDM_RESERVED_MTCP */ "", 1537 /* BDM_RESERVED_SPARE_0 */ "", 1538 /* BDM_RESERVED_SPARE_1 */ "", 1539 /* BDM_RESERVED_SPARE_2 */ "", 1540 /* BDM_RESERVED_SPARE_3 */ "", 1541 /* BDM_SBUS_BROADCAST_ID */ "", 1542 /* BDM_SBUS_LAST_IN_CHAIN */ "", 1543 /* BDM_SPECIAL_CLOCK_CONTROLS */ "", 1544 /* BFD_RX_ACH_TYPE_CONTROL0 */ "", 1545 /* BFD_RX_ACH_TYPE_CONTROL1 */ "", 1546 /* BFD_RX_ACH_TYPE_MPLSTP */ "", 1547 /* BFD_RX_ACH_TYPE_MPLSTP1 */ "", 1548 /* BFD_RX_ACH_TYPE_MPLSTP1_32 */ "BFD_RX_ACH_TYPE_MPLSTP1", 1549 /* BFD_RX_ACH_TYPE_MPLSTP_1 */ "", 1550 /* BFD_RX_UDP_CONTROL */ "", 1551 /* BFD_RX_UDP_CONTROL_1 */ "", 1552 /* BFD_RX_UDP_CONTROL_64 */ "BFD_RX_UDP_CONTROL", 1553 /* BFD_RX_UDP_CONTROL_1_64 */ "BFD_RX_UDP_CONTROL_1", 1554 /* BFD_VERSION_CONTROL */ "", 1555 /* BHH_RX_ACH_TYPE */ "", 1556 /* BISR_DEBUG_DATA */ "", 1557 /* BISR_LOAD_DONE_STATUS */ "", 1558 /* BISR_LOAD_STATUS */ "", 1559 /* BISTCONFIG */ "", 1560 /* BISTCONFIG2 */ "", 1561 /* BISTCONFIGURATIONS */ "", 1562 /* BISTENDADDRESS */ "", 1563 /* BISTERROROCCURRED */ "", 1564 /* BISTFULLMASKERRORCOUNTER */ "", 1565 /* BISTFULLMASKWORD0 */ "", 1566 /* BISTFULLMASKWORD1 */ "", 1567 /* BISTFULLMASKWORD2 */ "", 1568 /* BISTFULLMASKWORD3 */ "", 1569 /* BISTFULLMASKWORD4 */ "", 1570 /* BISTFULLMASKWORD5 */ "", 1571 /* BISTFULLMASKWORD6 */ "", 1572 /* BISTFULLMASKWORD7 */ "", 1573 /* BISTGENERALCONFIGURATIONS */ "", 1574 /* BISTGLOBALERRORCOUNTER */ "", 1575 /* BISTLASTADDRERR */ "", 1576 /* BISTLASTDATAERRWORD0 */ "", 1577 /* BISTLASTDATAERRWORD1 */ "", 1578 /* BISTLASTDATAERRWORD2 */ "", 1579 /* BISTLASTDATAERRWORD3 */ "", 1580 /* BISTLASTDATAERRWORD4 */ "", 1581 /* BISTLASTDATAERRWORD5 */ "", 1582 /* BISTLASTDATAERRWORD6 */ "", 1583 /* BISTLASTDATAERRWORD7 */ "", 1584 /* BISTNUMBEROFACTIONS */ "", 1585 /* BISTPATTERNWORD0 */ "", 1586 /* BISTPATTERNWORD1 */ "", 1587 /* BISTPATTERNWORD2 */ "", 1588 /* BISTPATTERNWORD3 */ "", 1589 /* BISTPATTERNWORD4 */ "", 1590 /* BISTPATTERNWORD5 */ "", 1591 /* BISTPATTERNWORD6 */ "", 1592 /* BISTPATTERNWORD7 */ "", 1593 /* BISTSINGLEBITMASK */ "", 1594 /* BISTSINGLEBITMASKERRORCOUNTER */ "", 1595 /* BISTSTARTADDRESS */ "", 1596 /* BISTSTATUSES */ "", 1597 /* BKPMETERINGBUCKET */ "", 1598 /* BKPMETERINGCONFIG */ "", 1599 /* BKPMETERINGCONFIG1 */ "", 1600 /* BKPMETERINGCONFIG_64 */ "BKPMETERINGCONFIG", 1601 /* BKPMETERINGCONFIG_EXT */ "", 1602 /* BKPMETERINGDISCSTATUS */ "", 1603 /* BKPMETERINGDISCSTATUS0 */ "BKPMETERINGDISCSTATUS0", 1604 /* BKPMETERINGDISCSTATUS1 */ "BKPMETERINGDISCSTATUS1", 1605 /* BKPMETERINGDISCSTATUS0_64 */ "BKPMETERINGDISCSTATUS0", 1606 /* BKPMETERINGDISCSTATUS1_64 */ "BKPMETERINGDISCSTATUS1", 1607 /* BKPMETERINGDISCSTATUS_0 */ "", 1608 /* BKPMETERINGDISCSTATUS_1 */ "", 1609 /* BKPMETERINGDISCSTATUS_2 */ "", 1610 /* BKPMETERINGDISCSTATUS_64 */ "BKPMETERINGDISCSTATUS", 1611 /* BKPMETERINGSTATUS */ "", 1612 /* BKPMETERINGSTATUS_0 */ "", 1613 /* BKPMETERINGSTATUS_1 */ "", 1614 /* BKPMETERINGSTATUS_2 */ "", 1615 /* BKPMETERINGWARNSTATUS */ "", 1616 /* BKPMETERINGWARNSTATUS0 */ "BKPMETERINGWARNSTATUS0", 1617 /* BKPMETERINGWARNSTATUS1 */ "BKPMETERINGWARNSTATUS1", 1618 /* BKPMETERINGWARNSTATUS0_64 */ "BKPMETERINGWARNSTATUS0", 1619 /* BKPMETERINGWARNSTATUS1_64 */ "BKPMETERINGWARNSTATUS1", 1620 /* BKPMETERINGWARNSTATUS_64 */ "BKPMETERINGWARNSTATUS", 1621 /* BKP_CONFIG */ "", 1622 /* BKP_DISC_BMAP */ "", 1623 /* BKP_DISC_BMAP_HI */ "", 1624 /* BKP_DISC_PRIORITY */ "", 1625 /* BKP_STATUS */ "", 1626 /* BLH_ECC_1B_ERR_CNT */ "", 1627 /* BLH_ECC_2B_ERR_CNT */ "", 1628 /* BLH_ECC_ERR_1B_INITIATE */ "", 1629 /* BLH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 1630 /* BLH_ECC_ERR_2B_INITIATE */ "", 1631 /* BLH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 1632 /* BLH_ECC_INTERRUPT_REGISTER */ "", 1633 /* BLH_ECC_INTERRUPT_REGISTER_MASK */ "", 1634 /* BLH_ECC_INTERRUPT_REGISTER_TEST */ "", 1635 /* BLH_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 1636 /* BLH_ERROR_INITIATION_DATA */ "", 1637 /* BLH_FSRDCONFIG_ALL_LANES_0 */ "", 1638 /* BLH_F_0_LN_0_MODE_0 */ "", 1639 /* BLH_F_0_LN_1_MODE_0 */ "", 1640 /* BLH_F_0_LN_2_MODE_0 */ "", 1641 /* BLH_F_0_LN_3_MODE_0 */ "", 1642 /* BLH_F_0_LN_4_MODE_0 */ "", 1643 /* BLH_F_0_LN_5_MODE_0 */ "", 1644 /* BLH_F_0_LN_6_MODE_0 */ "", 1645 /* BLH_F_0_LN_7_MODE_0 */ "", 1646 /* BLH_GLOBAL_MEM_OPTIONS */ "", 1647 /* BLH_GTIMER_CONFIGURATION */ "", 1648 /* BLH_INDIRECT_COMMAND */ "", 1649 /* BLH_INDIRECT_COMMAND_ADDRESS */ "", 1650 /* BLH_INDIRECT_COMMAND_DATA_INCREMENT */ "", 1651 /* BLH_INDIRECT_COMMAND_RD_DATA */ "", 1652 /* BLH_INDIRECT_COMMAND_WIDE_MEM */ "", 1653 /* BLH_INDIRECT_COMMAND_WR_DATA */ "", 1654 /* BLH_INDIRECT_FORCE_BUBBLE */ "", 1655 /* BLH_INDIRECT_WR_MASK */ "", 1656 /* BLH_INTERRUPT_MASK_REGISTER */ "", 1657 /* BLH_INTERRUPT_REGISTER */ "", 1658 /* BLH_INTERRUPT_REGISTER_TEST */ "", 1659 /* BLH_LANES_RX_RESET_0 */ "", 1660 /* BLH_LANES_TX_RESET_0 */ "", 1661 /* BLH_MASK_SIGNAL_DETRECT_0 */ "", 1662 /* BLH_PARITY_ERR_CNT */ "", 1663 /* BLH_PAR_ERR_INITIATE */ "", 1664 /* BLH_PAR_ERR_MEM_MASK */ "", 1665 /* BLH_PCMI_0 */ "", 1666 /* BLH_PCMI_1 */ "", 1667 /* BLH_PCMI_2 */ "", 1668 /* BLH_PCMI_3 */ "", 1669 /* BLH_PCMI_4 */ "", 1670 /* BLH_PCMI_0_S */ "", 1671 /* BLH_PCMI_0_T */ "", 1672 /* BLH_PCMI_1_S */ "", 1673 /* BLH_PCMI_1_T */ "", 1674 /* BLH_PCMI_2_S */ "", 1675 /* BLH_PCMI_2_T */ "", 1676 /* BLH_PCMI_3_S */ "", 1677 /* BLH_PCMI_3_T */ "", 1678 /* BLH_PCMI_4_S */ "", 1679 /* BLH_PCMI_4_T */ "", 1680 /* BLH_PLL_CORE_MODE_0 */ "", 1681 /* BLH_PLL_REF_CFG_0 */ "", 1682 /* BLH_REG_0901 */ "", 1683 /* BLH_RESCAL_CFG_0 */ "", 1684 /* BLH_RESERVED_MIRROR_ADDR */ "", 1685 /* BLH_RESERVED_MTCD */ "", 1686 /* BLH_RESERVED_MTCP */ "", 1687 /* BLH_RESERVED_SPARE_0 */ "", 1688 /* BLH_RESERVED_SPARE_1 */ "", 1689 /* BLH_RESERVED_SPARE_2 */ "", 1690 /* BLH_RESERVED_SPARE_3 */ "", 1691 /* BLH_RX_OVER_SAMPLING_MODE_0 */ "", 1692 /* BLH_RX_PAM_4_MODE_0 */ "", 1693 /* BLH_SBUS_BROADCAST_ID */ "", 1694 /* BLH_SBUS_LAST_IN_CHAIN */ "", 1695 /* BLH_SRD_STATUS_0 */ "", 1696 /* BLH_SRD_STATUS_CHANGED_0 */ "", 1697 /* BLH_SRD_STATUS_CHANGED_0_MASK */ "", 1698 /* BLH_SRD_STATUS_CHANGED_0_TEST */ "", 1699 /* BLH_TX_DRV_HV_DIS_0 */ "", 1700 /* BLH_TX_OVER_SAMPLING_MODE_0 */ "", 1701 /* BLH_TX_PAM_4_MODE_0 */ "", 1702 /* BLH_WC_UC_MEM_ACCESS */ "", 1703 /* BMAC_PFC_COS0_XOFF_CNT */ "", 1704 /* BMAC_PFC_COS10_XOFF_CNT */ "", 1705 /* BMAC_PFC_COS11_XOFF_CNT */ "", 1706 /* BMAC_PFC_COS12_XOFF_CNT */ "", 1707 /* BMAC_PFC_COS13_XOFF_CNT */ "", 1708 /* BMAC_PFC_COS14_XOFF_CNT */ "", 1709 /* BMAC_PFC_COS15_XOFF_CNT */ "", 1710 /* BMAC_PFC_COS1_XOFF_CNT */ "", 1711 /* BMAC_PFC_COS2_XOFF_CNT */ "", 1712 /* BMAC_PFC_COS3_XOFF_CNT */ "", 1713 /* BMAC_PFC_COS4_XOFF_CNT */ "", 1714 /* BMAC_PFC_COS5_XOFF_CNT */ "", 1715 /* BMAC_PFC_COS6_XOFF_CNT */ "", 1716 /* BMAC_PFC_COS7_XOFF_CNT */ "", 1717 /* BMAC_PFC_COS8_XOFF_CNT */ "", 1718 /* BMAC_PFC_COS9_XOFF_CNT */ "", 1719 /* BMAC_PFC_CTRL */ "", 1720 /* BMAC_PFC_DA_HI */ "", 1721 /* BMAC_PFC_DA_LO */ "", 1722 /* BMAC_PFC_OPCODE */ "", 1723 /* BMAC_PFC_TYPE */ "", 1724 /* BOOT_NIC_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 1725 /* BOOT_NIC_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 1726 /* BOOT_NIC_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 1727 /* BOOT_NIC_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 1728 /* BOOT_NIC_S0_IDM_IDM_ERROR_LOG_ID */ "", 1729 /* BOOT_NIC_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 1730 /* BOOT_NIC_S0_IDM_IDM_INTERRUPT_STATUS */ "", 1731 /* BOOT_NIC_S0_IDM_IDM_RESET_CONTROL */ "", 1732 /* BOOT_NIC_S0_IDM_IDM_RESET_READ_ID */ "", 1733 /* BOOT_NIC_S0_IDM_IDM_RESET_STATUS */ "", 1734 /* BOOT_NIC_S0_IDM_IDM_RESET_WRITE_ID */ "", 1735 /* BRCM_RESERVED_CPM_0 */ "", 1736 /* BRCM_RESERVED_CPM_1 */ "", 1737 /* BRCM_RESERVED_CPM_2 */ "", 1738 /* BRCM_RESERVED_CPM_3 */ "", 1739 /* BRCM_RESERVED_CPM_4 */ "", 1740 /* BRCM_RESERVED_CPM_5 */ "", 1741 /* BRCM_RESERVED_CPM_6 */ "", 1742 /* BRCM_RESERVED_CPM_7 */ "", 1743 /* BRCM_RESERVED_CPM_8 */ "", 1744 /* BRCM_RESERVED_CPM_9 */ "", 1745 /* BRCM_RESERVED_CPM_12 */ "", 1746 /* BRCM_RESERVED_CPM_13 */ "", 1747 /* BRCM_RESERVED_CPM_14 */ "", 1748 /* BRCM_RESERVED_CPM_15 */ "", 1749 /* BRCM_RESERVED_CPM_16 */ "", 1750 /* BRCM_RESERVED_CPM_300 */ "", 1751 /* BRCM_RESERVED_CPM_302 */ "", 1752 /* BRCM_RESERVED_CPM_303 */ "", 1753 /* BRCM_RESERVED_CPM_304 */ "", 1754 /* BRCM_RESERVED_CPM_305 */ "", 1755 /* BRCM_RESERVED_CPM_307 */ "", 1756 /* BRCM_RESERVED_CPM_308 */ "", 1757 /* BRCM_RESERVED_CPM_309 */ "", 1758 /* BRCM_RESERVED_CPM_310 */ "", 1759 /* BRCM_RESERVED_CPM_311 */ "", 1760 /* BRCM_RESERVED_CPM_312 */ "", 1761 /* BRCM_RESERVED_CPM_313 */ "", 1762 /* BRCM_RESERVED_CPM_314 */ "", 1763 /* BRCM_RESERVED_CPM_315 */ "", 1764 /* BRCM_RESERVED_CPM_316 */ "", 1765 /* BRCM_RESERVED_CPM_317 */ "", 1766 /* BRCM_RESERVED_CPM_318 */ "", 1767 /* BRCM_RESERVED_CPM_319 */ "", 1768 /* BRCM_RESERVED_CPM_320 */ "", 1769 /* BRCM_RESERVED_CPM_321 */ "", 1770 /* BRCM_RESERVED_CPM_322 */ "", 1771 /* BRCM_RESERVED_CPM_323 */ "", 1772 /* BRCM_RESERVED_CPM_324 */ "", 1773 /* BRCM_RESERVED_CPM_325 */ "", 1774 /* BRCM_RESERVED_CPM_326 */ "", 1775 /* BRCM_RESERVED_CPM_327 */ "", 1776 /* BRCM_RESERVED_EP_1 */ "", 1777 /* BRCM_RESERVED_IPROC_4 */ "", 1778 /* BRCM_RESERVED_IPROC_5 */ "", 1779 /* BRCM_RESERVED_IPROC_6 */ "", 1780 /* BRCM_RESERVED_IPROC_7 */ "", 1781 /* BRCM_RESERVED_IPROC_8 */ "", 1782 /* BRCM_RESERVED_IPROC_9 */ "", 1783 /* BRCM_RESERVED_IPROC_10 */ "", 1784 /* BRCM_RESERVED_IPROC_11 */ "", 1785 /* BRCM_RESERVED_IPROC_12 */ "", 1786 /* BRCM_RESERVED_IPROC_13 */ "", 1787 /* BRCM_RESERVED_IPROC_14 */ "", 1788 /* BRCM_RESERVED_IPROC_15 */ "", 1789 /* BRCM_RESERVED_IPROC_16 */ "", 1790 /* BRCM_RESERVED_IPROC_17 */ "", 1791 /* BRCM_RESERVED_IPROC_18 */ "", 1792 /* BRCM_RESERVED_IPROC_19 */ "", 1793 /* BRCM_RESERVED_IPROC_20 */ "", 1794 /* BRCM_RESERVED_IPROC_21 */ "", 1795 /* BRCM_RESERVED_IPROC_22 */ "", 1796 /* BRCM_RESERVED_IPROC_23 */ "", 1797 /* BRCM_RESERVED_IPROC_24 */ "", 1798 /* BRCM_RESERVED_IPROC_25 */ "", 1799 /* BRCM_RESERVED_IPROC_26 */ "", 1800 /* BRCM_RESERVED_IPROC_27 */ "", 1801 /* BRCM_RESERVED_IPROC_28 */ "", 1802 /* BRCM_RESERVED_IPROC_29 */ "", 1803 /* BRCM_RESERVED_IPROC_30 */ "", 1804 /* BRCM_RESERVED_IPROC_31 */ "", 1805 /* BRCM_RESERVED_IPROC_32 */ "", 1806 /* BRCM_RESERVED_IPROC_33 */ "", 1807 /* BRCM_RESERVED_IPROC_34 */ "", 1808 /* BRCM_RESERVED_IPROC_35 */ "", 1809 /* BRCM_RESERVED_IPROC_36 */ "", 1810 /* BRCM_RESERVED_IPROC_37 */ "", 1811 /* BRCM_RESERVED_IPROC_38 */ "", 1812 /* BRCM_RESERVED_IPROC_39 */ "", 1813 /* BRCM_RESERVED_IP_1 */ "", 1814 /* BRCM_RESERVED_TOP_3 */ "", 1815 /* BRCM_RESERVED_TOP_4 */ "", 1816 /* BRCM_RESERVED_TOP_5 */ "", 1817 /* BRCM_RESERVED_TOP_6 */ "", 1818 /* BRCM_RESERVED_TOP_7 */ "", 1819 /* BRCM_RESERVED_TOP_8 */ "", 1820 /* BRCM_RESERVED_TOP_9 */ "", 1821 /* BRCM_RESERVED_TOP_10 */ "", 1822 /* BRCM_RESERVED_TOP_11 */ "", 1823 /* BRCM_RESERVED_TOP_12 */ "", 1824 /* BRCM_RESERVED_TOP_13 */ "", 1825 /* BRCM_RESERVED_TOP_14 */ "", 1826 /* BRDC_CCH_ARAD_BMP */ "", 1827 /* BRDC_CCH_AUTO_DOC_NAME_6 */ "", 1828 /* BRDC_CCH_AUTO_DOC_NAME_7 */ "", 1829 /* BRDC_CCH_AUTO_DOC_NAME_12 */ "", 1830 /* BRDC_CCH_AUTO_DOC_NAME_13 */ "", 1831 /* BRDC_CCH_AUTO_DOC_NAME_14 */ "", 1832 /* BRDC_CCH_AUTO_DOC_NAME_15 */ "", 1833 /* BRDC_CCH_AUTO_DOC_NAME_16 */ "", 1834 /* BRDC_CCH_AUTO_DOC_NAME_17 */ "", 1835 /* BRDC_CCH_AUTO_DOC_NAME_18 */ "", 1836 /* BRDC_CCH_AUTO_DOC_NAME_19 */ "", 1837 /* BRDC_CCH_AUTO_DOC_NAME_20 */ "", 1838 /* BRDC_CCH_AUTO_DOC_NAME_21 */ "", 1839 /* BRDC_CCH_CAPTURED_CELL */ "", 1840 /* BRDC_CCH_CAPTURED_CELL_VALID */ "", 1841 /* BRDC_CCH_CAPTURE_FIFO_DISCARD_CNT */ "", 1842 /* BRDC_CCH_CAPTURE_FILTER_CELL_0 */ "", 1843 /* BRDC_CCH_CAPTURE_FILTER_CELL_1 */ "", 1844 /* BRDC_CCH_CAPTURE_FILTER_MASK_0 */ "", 1845 /* BRDC_CCH_CAPTURE_FILTER_MASK_1 */ "", 1846 /* BRDC_CCH_CAPTURE_HIT_CNT */ "", 1847 /* BRDC_CCH_CAPTURE_HIT_MASK_0_CNT */ "", 1848 /* BRDC_CCH_CAPTURE_HIT_MASK_1_CNT */ "", 1849 /* BRDC_CCH_CCH_CONFIGURATIONS */ "", 1850 /* BRDC_CCH_CCP_0_DSCRD_CNT */ "", 1851 /* BRDC_CCH_CCP_0_ILLEGAL_CELLS_DATA */ "", 1852 /* BRDC_CCH_CCP_0_PROGRAMMABLE_CELLS_COUNTER */ "", 1853 /* BRDC_CCH_CCP_1_DSCRD_CNT */ "", 1854 /* BRDC_CCH_CCP_1_ILLEGAL_CELLS_DATA */ "", 1855 /* BRDC_CCH_CCP_1_PROGRAMMABLE_CELLS_COUNTER */ "", 1856 /* BRDC_CCH_CCP_FIFOS_WATER_MARK */ "", 1857 /* BRDC_CCH_CONNECTIVITY_LINKS_EVENTS */ "", 1858 /* BRDC_CCH_CONNECTIVITY_LINK_0 */ "", 1859 /* BRDC_CCH_CONNECTIVITY_LINK_1 */ "", 1860 /* BRDC_CCH_CONNECTIVITY_LINK_2 */ "", 1861 /* BRDC_CCH_CONNECTIVITY_LINK_3 */ "", 1862 /* BRDC_CCH_CONNECTIVITY_LINK_4 */ "", 1863 /* BRDC_CCH_CONNECTIVITY_LINK_5 */ "", 1864 /* BRDC_CCH_CONNECTIVITY_LINK_6 */ "", 1865 /* BRDC_CCH_CONNECTIVITY_LINK_7 */ "", 1866 /* BRDC_CCH_CONNECTIVITY_LINK_8 */ "", 1867 /* BRDC_CCH_CONNECTIVITY_LINK_9 */ "", 1868 /* BRDC_CCH_CONNECTIVITY_LINK_10 */ "", 1869 /* BRDC_CCH_CONNECTIVITY_LINK_11 */ "", 1870 /* BRDC_CCH_CONNECTIVITY_LINK_12 */ "", 1871 /* BRDC_CCH_CONNECTIVITY_LINK_13 */ "", 1872 /* BRDC_CCH_CONNECTIVITY_LINK_14 */ "", 1873 /* BRDC_CCH_CONNECTIVITY_LINK_15 */ "", 1874 /* BRDC_CCH_CONNECTIVITY_LINK_16 */ "", 1875 /* BRDC_CCH_CONNECTIVITY_LINK_17 */ "", 1876 /* BRDC_CCH_CONNECTIVITY_LINK_18 */ "", 1877 /* BRDC_CCH_CONNECTIVITY_LINK_19 */ "", 1878 /* BRDC_CCH_CONNECTIVITY_LINK_20 */ "", 1879 /* BRDC_CCH_CONNECTIVITY_LINK_21 */ "", 1880 /* BRDC_CCH_CONNECTIVITY_LINK_22 */ "", 1881 /* BRDC_CCH_CONNECTIVITY_LINK_23 */ "", 1882 /* BRDC_CCH_CREDIT_CELLS_CNT */ "", 1883 /* BRDC_CCH_CRP_FIFO_WATER_MARK */ "", 1884 /* BRDC_CCH_CRP_UNREACHABLE_CELL_DATA */ "", 1885 /* BRDC_CCH_DEBUG_CONFIGURATIONS */ "", 1886 /* BRDC_CCH_ECC_1B_ERR_CNT */ "", 1887 /* BRDC_CCH_ECC_2B_ERR_CNT */ "", 1888 /* BRDC_CCH_ECC_ERR_1B_INITIATE */ "", 1889 /* BRDC_CCH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 1890 /* BRDC_CCH_ECC_ERR_2B_INITIATE */ "", 1891 /* BRDC_CCH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 1892 /* BRDC_CCH_ECC_INTERRUPT_REGISTER */ "", 1893 /* BRDC_CCH_ECC_INTERRUPT_REGISTER_MASK */ "", 1894 /* BRDC_CCH_ECC_INTERRUPT_REGISTER_TEST */ "", 1895 /* BRDC_CCH_ERROR_INITIATION_DATA */ "", 1896 /* BRDC_CCH_FE_GLOBAL_GENERAL_CFG_1 */ "", 1897 /* BRDC_CCH_FILTERED_CELLS_CONFIGURATIONS */ "", 1898 /* BRDC_CCH_FLOW_STATUS_CELLS_CNT */ "", 1899 /* BRDC_CCH_GLOBAL_MEM_OPTIONS */ "", 1900 /* BRDC_CCH_GTIMER_CONFIGURATION */ "", 1901 /* BRDC_CCH_GTIMER_CYCLE */ "", 1902 /* BRDC_CCH_INTERRUPT_MASK_REGISTER */ "", 1903 /* BRDC_CCH_INTERRUPT_REGISTER */ "", 1904 /* BRDC_CCH_INTERRUPT_REGISTER_TEST */ "", 1905 /* BRDC_CCH_PAR_ERR_INITIATE */ "", 1906 /* BRDC_CCH_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTER */ "", 1907 /* BRDC_CCH_REACHABILITY_CELLS_CNT */ "", 1908 /* BRDC_CCH_RESERVED_MIRROR_ADDR */ "", 1909 /* BRDC_CCH_RESERVED_MTCD */ "", 1910 /* BRDC_CCH_RESERVED_MTCP */ "", 1911 /* BRDC_CCH_RESERVED_SPARE_0 */ "", 1912 /* BRDC_CCH_RESERVED_SPARE_1 */ "", 1913 /* BRDC_CCH_RESERVED_SPARE_2 */ "", 1914 /* BRDC_CCH_RESERVED_SPARE_3 */ "", 1915 /* BRDC_CCH_SBUS_BROADCAST_ID */ "", 1916 /* BRDC_CCH_SBUS_LAST_IN_CHAIN */ "", 1917 /* BRDC_CCH_SELF_ROUTED_CELLS_CNT */ "", 1918 /* BRDC_CCH_TOTAL_CELLS_CNT */ "", 1919 /* BRDC_CCH_UNREACHABLE_DESTINATION_CELLS_CNT */ "", 1920 /* BRDC_CCS_ARAD_BMP */ "", 1921 /* BRDC_CCS_CAPTURED_CELL */ "", 1922 /* BRDC_CCS_CAPTURED_CELL_VALID */ "", 1923 /* BRDC_CCS_CAPTURE_FIFO_DISCARD_CNT */ "", 1924 /* BRDC_CCS_CAPTURE_FILTER_CELL_0 */ "", 1925 /* BRDC_CCS_CAPTURE_FILTER_CELL_1 */ "", 1926 /* BRDC_CCS_CAPTURE_FILTER_MASK_0 */ "", 1927 /* BRDC_CCS_CAPTURE_FILTER_MASK_1 */ "", 1928 /* BRDC_CCS_CAPTURE_HIT_CNT */ "", 1929 /* BRDC_CCS_CCS_CONFIGURATIONS */ "", 1930 /* BRDC_CCS_CDMA_LP_CELLS_DISCARD_CNT */ "", 1931 /* BRDC_CCS_CDMB_LP_CELLS_DISCARD_CNT */ "", 1932 /* BRDC_CCS_CDMC_LP_CELLS_DISCARD_CNT */ "", 1933 /* BRDC_CCS_CDMD_LP_CELLS_DISCARD_CNT */ "", 1934 /* BRDC_CCS_CDM_OVERFLOW_FIFO_NUMBER */ "", 1935 /* BRDC_CCS_CPU_SOURCE_CELL_DATA */ "", 1936 /* BRDC_CCS_CPU_SOURCE_CELL_TRIGGER */ "", 1937 /* BRDC_CCS_CREDIT_CELLS_CNT */ "", 1938 /* BRDC_CCS_CRP_FIFO_WATER_MARK */ "", 1939 /* BRDC_CCS_CRP_PARITY_ERR_CNT */ "", 1940 /* BRDC_CCS_CRP_UNREACHABLE_CELL_DATA */ "", 1941 /* BRDC_CCS_CTP_INTERNAL_REACHABILITY_CELLS_CNT */ "", 1942 /* BRDC_CCS_DEBUG_CONFIGURATIONS */ "", 1943 /* BRDC_CCS_ECC_1B_ERR_CNT */ "", 1944 /* BRDC_CCS_ECC_2B_ERR_CNT */ "", 1945 /* BRDC_CCS_ECC_ERR_1B_INITIATE */ "", 1946 /* BRDC_CCS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 1947 /* BRDC_CCS_ECC_ERR_2B_INITIATE */ "", 1948 /* BRDC_CCS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 1949 /* BRDC_CCS_ECC_INTERRUPT_REGISTER */ "", 1950 /* BRDC_CCS_ECC_INTERRUPT_REGISTER_MASK */ "", 1951 /* BRDC_CCS_ECC_INTERRUPT_REGISTER_TEST */ "", 1952 /* BRDC_CCS_ERROR_INITIATION_DATA */ "", 1953 /* BRDC_CCS_FE_13_LINKS_CREDIT_CELLS_CNT */ "", 1954 /* BRDC_CCS_FE_13_LINKS_FLOW_STATUS_CELLS_CNT */ "", 1955 /* BRDC_CCS_FE_13_LINKS_REACHABILITY_CELLS_CNT */ "", 1956 /* BRDC_CCS_FE_13_LINKS_SELF_ROUTED_CELLS_CNT */ "", 1957 /* BRDC_CCS_FE_13_LINKS_TOTAL_CELLS_CNT */ "", 1958 /* BRDC_CCS_FILTERED_CELLS_CONFIGURATIONS */ "", 1959 /* BRDC_CCS_FLOW_STATUS_CELLS_CNT */ "", 1960 /* BRDC_CCS_GLOBAL_GENERAL_CFG_2 */ "", 1961 /* BRDC_CCS_GLOBAL_GENERAL_FE_CFG_1 */ "", 1962 /* BRDC_CCS_GLOBAL_MEM_OPTIONS */ "", 1963 /* BRDC_CCS_GTIMER_CONFIGURATION */ "", 1964 /* BRDC_CCS_GTIMER_TRIGGER */ "", 1965 /* BRDC_CCS_INTERRUPT_MASK_REGISTER */ "", 1966 /* BRDC_CCS_INTERRUPT_REGISTER */ "", 1967 /* BRDC_CCS_INTERRUPT_REGISTER_TEST */ "", 1968 /* BRDC_CCS_MID_FIFOS_LP_WATER_MARK */ "", 1969 /* BRDC_CCS_PAR_ERR_INITIATE */ "", 1970 /* BRDC_CCS_PROGRAMMABLE_MID_FIFOS_WATER_MARK */ "", 1971 /* BRDC_CCS_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARK */ "", 1972 /* BRDC_CCS_REACHABILITY_CELLS_CNT */ "", 1973 /* BRDC_CCS_REG_0102 */ "", 1974 /* BRDC_CCS_REG_0112 */ "", 1975 /* BRDC_CCS_REG_0113 */ "", 1976 /* BRDC_CCS_REG_0114 */ "", 1977 /* BRDC_CCS_REG_0120 */ "", 1978 /* BRDC_CCS_REG_0128 */ "", 1979 /* BRDC_CCS_REG_0140 */ "", 1980 /* BRDC_CCS_REG_0144 */ "", 1981 /* BRDC_CCS_REG_0149 */ "", 1982 /* BRDC_CCS_REG_011A */ "", 1983 /* BRDC_CCS_REG_011B */ "", 1984 /* BRDC_CCS_REG_011C */ "", 1985 /* BRDC_CCS_REG_014A */ "", 1986 /* BRDC_CCS_REG_014B */ "", 1987 /* BRDC_CCS_RESERVED_MIRROR_ADDR */ "", 1988 /* BRDC_CCS_RESERVED_MTCP */ "", 1989 /* BRDC_CCS_RESERVED_SPARE_0 */ "", 1990 /* BRDC_CCS_RESERVED_SPARE_1 */ "", 1991 /* BRDC_CCS_RESERVED_SPARE_2 */ "", 1992 /* BRDC_CCS_RESERVED_SPARE_3 */ "", 1993 /* BRDC_CCS_SBUS_BROADCAST_ID */ "", 1994 /* BRDC_CCS_SBUS_LAST_IN_CHAIN */ "", 1995 /* BRDC_CCS_SELF_ROUTED_CELLS_CNT */ "", 1996 /* BRDC_CCS_TOTAL_CELLS_CNT */ "", 1997 /* BRDC_CCS_UNREACHABLE_DESTINATION_CELLS_CNT */ "", 1998 /* BRDC_DCH_AUTO_DOC_NAME_0 */ "", 1999 /* BRDC_DCH_AUTO_DOC_NAME_13 */ "", 2000 /* BRDC_DCH_AUTO_DOC_NAME_15 */ "", 2001 /* BRDC_DCH_AUTO_DOC_NAME_16 */ "", 2002 /* BRDC_DCH_AUTO_DOC_NAME_17 */ "", 2003 /* BRDC_DCH_AUTO_DOC_NAME_29 */ "", 2004 /* BRDC_DCH_AUTO_DOC_NAME_31 */ "", 2005 /* BRDC_DCH_AUTO_DOC_NAME_33 */ "", 2006 /* BRDC_DCH_AUTO_DOC_NAME_35 */ "", 2007 /* BRDC_DCH_AUTO_DOC_NAME_36 */ "", 2008 /* BRDC_DCH_AUTO_DOC_NAME_37 */ "", 2009 /* BRDC_DCH_AUTO_DOC_NAME_38 */ "", 2010 /* BRDC_DCH_AUTO_DOC_NAME_39 */ "", 2011 /* BRDC_DCH_AUTO_DOC_NAME_40 */ "", 2012 /* BRDC_DCH_AUTO_DOC_NAME_41 */ "", 2013 /* BRDC_DCH_AUTO_DOC_NAME_42 */ "", 2014 /* BRDC_DCH_AUTO_DOC_NAME_43 */ "", 2015 /* BRDC_DCH_AUTO_DOC_NAME_44 */ "", 2016 /* BRDC_DCH_AUTO_DOC_NAME_45 */ "", 2017 /* BRDC_DCH_AUTO_DOC_NAME_46 */ "", 2018 /* BRDC_DCH_AUTO_DOC_NAME_47 */ "", 2019 /* BRDC_DCH_AUTO_DOC_NAME_48 */ "", 2020 /* BRDC_DCH_CAPTURED_CELL_A */ "", 2021 /* BRDC_DCH_CAPTURED_CELL_B */ "", 2022 /* BRDC_DCH_CAPTURED_CELL_C */ "", 2023 /* BRDC_DCH_CAPTURED_CELL_D */ "", 2024 /* BRDC_DCH_CAPTURED_CELL_DATA_0 */ "", 2025 /* BRDC_DCH_CAPTURED_CELL_DATA_1 */ "", 2026 /* BRDC_DCH_CAPTURED_CELL_DATA_2 */ "", 2027 /* BRDC_DCH_CELL_TYPE_ERR_SRC */ "", 2028 /* BRDC_DCH_DCH_ENABLERS_REGISTER_1 */ "", 2029 /* BRDC_DCH_DCH_ENABLERS_REGISTER_2 */ "", 2030 /* BRDC_DCH_DCH_ENABLERS_REGISTER_2_P */ "", 2031 /* BRDC_DCH_DCH_ENABLERS_REGISTER_3_P */ "", 2032 /* BRDC_DCH_DCH_ERROR_INITIATION_DATA */ "", 2033 /* BRDC_DCH_DCH_TOTAL_CELL_CNT_P_0 */ "", 2034 /* BRDC_DCH_DCH_TOTAL_CELL_CNT_P_1 */ "", 2035 /* BRDC_DCH_DCH_TOTAL_CELL_CNT_P_2 */ "", 2036 /* BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_0 */ "", 2037 /* BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_1 */ "", 2038 /* BRDC_DCH_DCH_TOTAL_OUT_CELL_CNT_P_2 */ "", 2039 /* BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_0 */ "", 2040 /* BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_1 */ "", 2041 /* BRDC_DCH_DCM_FLOW_CNTROL_0_CNT_P_2 */ "", 2042 /* BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_0 */ "", 2043 /* BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_1 */ "", 2044 /* BRDC_DCH_DCM_FLOW_CNTROL_1_CNT_P_2 */ "", 2045 /* BRDC_DCH_DROP_FILTER_CNT */ "", 2046 /* BRDC_DCH_DROP_LOW_PRIORITY_CNT_P */ "", 2047 /* BRDC_DCH_DYN_PIPES_WEIGHTS_REGISTER */ "", 2048 /* BRDC_DCH_DYN_WFQ_WEIGHT_THD_REGISTE */ "", 2049 /* BRDC_DCH_ECC_1B_ERR_CNT */ "", 2050 /* BRDC_DCH_ECC_2B_ERR_CNT */ "", 2051 /* BRDC_DCH_ECC_ERR_1B_INITIATE */ "", 2052 /* BRDC_DCH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 2053 /* BRDC_DCH_ECC_ERR_2B_INITIATE */ "", 2054 /* BRDC_DCH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 2055 /* BRDC_DCH_ECC_INTERRUPT_REGISTER */ "", 2056 /* BRDC_DCH_ECC_INTERRUPT_REGISTER_MASK */ "", 2057 /* BRDC_DCH_ECC_INTERRUPT_REGISTER_TEST */ "", 2058 /* BRDC_DCH_ERROR_FILTER */ "", 2059 /* BRDC_DCH_ERROR_FILTER_2 */ "", 2060 /* BRDC_DCH_ERROR_FILTER_CNT */ "", 2061 /* BRDC_DCH_ERROR_FILTER_EN */ "", 2062 /* BRDC_DCH_ERROR_FILTER_MASK */ "", 2063 /* BRDC_DCH_ERROR_FILTER_MASK_2 */ "", 2064 /* BRDC_DCH_ERROR_INITIATION_DATA */ "", 2065 /* BRDC_DCH_FAP_GLOBAL_GENERAL_CFG_1 */ "", 2066 /* BRDC_DCH_FE_GLOBAL_GENERAL_CFG_1 */ "", 2067 /* BRDC_DCH_FIFOS_DEPTH_TYPE */ "", 2068 /* BRDC_DCH_FIFO_DISCARD_CNT_P */ "", 2069 /* BRDC_DCH_FIFO_DISCARD_COUNTER_P */ "", 2070 /* BRDC_DCH_FILTER_MATCH_INPUT_LINK */ "", 2071 /* BRDC_DCH_GEN_ERR_MEM */ "", 2072 /* BRDC_DCH_GLOBAL_FE_DEST_IDS_1 */ "", 2073 /* BRDC_DCH_GLOBAL_FE_DEST_IDS_2 */ "", 2074 /* BRDC_DCH_GLOBAL_GENERAL_CFG_1 */ "", 2075 /* BRDC_DCH_GLOBAL_GENERAL_FE_CFG_1 */ "", 2076 /* BRDC_DCH_GLOBAL_MEM_OPTIONS */ "", 2077 /* BRDC_DCH_GTIMER_CONFIGURATION */ "", 2078 /* BRDC_DCH_GTIMER_CYCLE */ "", 2079 /* BRDC_DCH_GTIMER_TRIGGER */ "", 2080 /* BRDC_DCH_IFM_MAX_OCCUP_P_0 */ "", 2081 /* BRDC_DCH_IFM_MAX_OCCUP_P_1 */ "", 2082 /* BRDC_DCH_IFM_MAX_OCCUP_P_2 */ "", 2083 /* BRDC_DCH_INTERRUPT_MASK_REGISTER */ "", 2084 /* BRDC_DCH_INTERRUPT_REGISTER */ "", 2085 /* BRDC_DCH_INTERRUPT_REGISTER_TEST */ "", 2086 /* BRDC_DCH_LINK_CELL_PACKING_EN */ "", 2087 /* BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_BMP */ "", 2088 /* BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_0 */ "", 2089 /* BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_1 */ "", 2090 /* BRDC_DCH_LINK_LEVEL_FLOW_CONTROL_P_2 */ "", 2091 /* BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_0 */ "", 2092 /* BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_1 */ "", 2093 /* BRDC_DCH_LINK_UP_STATUS_FROM_DCHP_2 */ "", 2094 /* BRDC_DCH_LOCAL_GCI_RCI_TYPE_0_P */ "", 2095 /* BRDC_DCH_LOCAL_GCI_RCI_TYPE_1_P */ "", 2096 /* BRDC_DCH_LOCAL_GCI_TYPE_0_P */ "", 2097 /* BRDC_DCH_LOCAL_GCI_TYPE_1_P */ "", 2098 /* BRDC_DCH_LOW_PR_MUL_0 */ "", 2099 /* BRDC_DCH_LOW_PR_MUL_1 */ "", 2100 /* BRDC_DCH_LP_PIPE_SHAPER_REGISTER */ "", 2101 /* BRDC_DCH_MATCH_FILT */ "", 2102 /* BRDC_DCH_MATCH_FILT_MASK */ "", 2103 /* BRDC_DCH_MC_EST_NOF_REP */ "", 2104 /* BRDC_DCH_MID_PR_MUL_0 */ "", 2105 /* BRDC_DCH_MID_PR_MUL_1 */ "", 2106 /* BRDC_DCH_PCMI_0 */ "", 2107 /* BRDC_DCH_PCMI_1 */ "", 2108 /* BRDC_DCH_PCMI_2 */ "", 2109 /* BRDC_DCH_PCMI_3 */ "", 2110 /* BRDC_DCH_PCMI_0_S */ "", 2111 /* BRDC_DCH_PCMI_0_T */ "", 2112 /* BRDC_DCH_PCMI_1_S */ "", 2113 /* BRDC_DCH_PCMI_1_T */ "", 2114 /* BRDC_DCH_PCMI_2_S */ "", 2115 /* BRDC_DCH_PCMI_2_T */ "", 2116 /* BRDC_DCH_PCMI_3_S */ "", 2117 /* BRDC_DCH_PCMI_3_T */ "", 2118 /* BRDC_DCH_PIPES_MAPPING_EN */ "", 2119 /* BRDC_DCH_PIPES_MAP_EN */ "", 2120 /* BRDC_DCH_PIPES_SEPARATION_REGISTER */ "", 2121 /* BRDC_DCH_PIPES_WEIGHTS_COUNTER_PN */ "", 2122 /* BRDC_DCH_PIPES_WEIGHTS_REGISTER */ "", 2123 /* BRDC_DCH_PIPES_WEIGHTS_REGISTER_2 */ "", 2124 /* BRDC_DCH_PIPES_WEIGHTS_REGISTER_3 */ "", 2125 /* BRDC_DCH_PRG_CELL_CNT_0 */ "", 2126 /* BRDC_DCH_PRG_CELL_CNT_1 */ "", 2127 /* BRDC_DCH_PRG_CELL_CNT_2 */ "", 2128 /* BRDC_DCH_PRIORITY_TRANSLATION */ "", 2129 /* BRDC_DCH_PROGRAMMABLE_CELLS_COUNTER_1 */ "", 2130 /* BRDC_DCH_PROGRAMMABLE_CELLS_COUNTER_2 */ "", 2131 /* BRDC_DCH_RATE_LIMITER */ "", 2132 /* BRDC_DCH_REG_0103 */ "", 2133 /* BRDC_DCH_REG_0107 */ "", 2134 /* BRDC_DCH_REG_0108 */ "", 2135 /* BRDC_DCH_REG_0114 */ "", 2136 /* BRDC_DCH_REG_0116 */ "", 2137 /* BRDC_DCH_REG_0196 */ "", 2138 /* BRDC_DCH_REG_0210 */ "", 2139 /* BRDC_DCH_REG_0212 */ "", 2140 /* BRDC_DCH_REG_0214 */ "", 2141 /* BRDC_DCH_REG_019C */ "", 2142 /* BRDC_DCH_REG_01A2 */ "", 2143 /* BRDC_DCH_REG_01A8 */ "", 2144 /* BRDC_DCH_REG_01BE */ "", 2145 /* BRDC_DCH_REG_01BF */ "", 2146 /* BRDC_DCH_REG_01C0 */ "", 2147 /* BRDC_DCH_REG_01DE */ "", 2148 /* BRDC_DCH_REG_01EA */ "", 2149 /* BRDC_DCH_REG_01ED */ "", 2150 /* BRDC_DCH_REG_01F3 */ "", 2151 /* BRDC_DCH_REG_01F9 */ "", 2152 /* BRDC_DCH_REG_01FF */ "", 2153 /* BRDC_DCH_REMOTE_PRI_PIPE_IDX */ "", 2154 /* BRDC_DCH_REMOTE_SEC_PIPE_IDX */ "", 2155 /* BRDC_DCH_RESERVED_MIRROR_ADDR */ "", 2156 /* BRDC_DCH_RESERVED_MTCD */ "", 2157 /* BRDC_DCH_RESERVED_MTCP */ "", 2158 /* BRDC_DCH_RESERVED_PCMI_2 */ "", 2159 /* BRDC_DCH_RESERVED_PCMI_4 */ "", 2160 /* BRDC_DCH_RESERVED_PCMI_2_S */ "", 2161 /* BRDC_DCH_RESERVED_PCMI_2_T */ "", 2162 /* BRDC_DCH_RESERVED_PCMI_4_S */ "", 2163 /* BRDC_DCH_RESERVED_PCMI_4_T */ "", 2164 /* BRDC_DCH_RESERVED_SPARE_0 */ "", 2165 /* BRDC_DCH_RESERVED_SPARE_1 */ "", 2166 /* BRDC_DCH_RESERVED_SPARE_2 */ "", 2167 /* BRDC_DCH_RESERVED_SPARE_3 */ "", 2168 /* BRDC_DCH_SBUS_BROADCAST_ID */ "", 2169 /* BRDC_DCH_SBUS_LAST_IN_CHAIN */ "", 2170 /* BRDC_DCH_TDM_PRIORITY */ "", 2171 /* BRDC_DCH_THREE_PIPES_BMP */ "", 2172 /* BRDC_DCH_TWO_PIPES_BMP */ "", 2173 /* BRDC_DCH_TX_CPU_CELL_CNT */ "", 2174 /* BRDC_DCH_TX_CPU_CELL_DATA */ "", 2175 /* BRDC_DCH_TX_CPU_CELL_HEADER */ "", 2176 /* BRDC_DCH_TX_CPU_CELL_INFO */ "", 2177 /* BRDC_DCH_TX_CPU_CELL_TRG */ "", 2178 /* BRDC_DCH_TYPE_ERR_DROP_CNT */ "", 2179 /* BRDC_DCH_UNREACH_DEST */ "", 2180 /* BRDC_DCH_UNREACH_DEST_CNT */ "", 2181 /* BRDC_DCH_UN_EXP_DISC_CNT_3 */ "", 2182 /* BRDC_DCH_UN_EXP_DISC_CNT_2_PN */ "", 2183 /* BRDC_DCH_UN_EXP_DISC_CNT_2_P_N */ "", 2184 /* BRDC_DCH_UN_EXP_DISC_CNT_3_PN */ "", 2185 /* BRDC_DCH_UN_EXP_DISC_CNT_3_P_N */ "", 2186 /* BRDC_DCH_UN_EXP_DISC_CNT_PN */ "", 2187 /* BRDC_DCH_UN_EXP_DISC_CNT_P_N */ "", 2188 /* BRDC_DCH_UN_REACH_DEST */ "", 2189 /* BRDC_DCH_USE_MC_CELL_PRIO_BMP */ "", 2190 /* BRDC_DCH_WFQ_DYN_WEIGHT_THD_REGISTE */ "", 2191 /* BRDC_DCL_ALM_FULL_P */ "", 2192 /* BRDC_DCL_CCP_0_DSCRD_CNT */ "", 2193 /* BRDC_DCL_CCP_0_ILLEGAL_CELLS_DATA */ "", 2194 /* BRDC_DCL_CCP_0_PROGRAMMABLE_CELLS_COUNTER */ "", 2195 /* BRDC_DCL_CCP_1_DSCRD_CNT */ "", 2196 /* BRDC_DCL_CCP_1_ILLEGAL_CELLS_DATA */ "", 2197 /* BRDC_DCL_CCP_1_PROGRAMMABLE_CELLS_COUNTER */ "", 2198 /* BRDC_DCL_CCP_CONFIGURATIONS */ "", 2199 /* BRDC_DCL_CCP_FIFOS_WATER_MARK */ "", 2200 /* BRDC_DCL_CONNECTIVITY_LINKS_EVENTS */ "", 2201 /* BRDC_DCL_CONNECTIVITY_LINK_0 */ "", 2202 /* BRDC_DCL_CONNECTIVITY_LINK_1 */ "", 2203 /* BRDC_DCL_CONNECTIVITY_LINK_2 */ "", 2204 /* BRDC_DCL_CONNECTIVITY_LINK_3 */ "", 2205 /* BRDC_DCL_CONNECTIVITY_LINK_4 */ "", 2206 /* BRDC_DCL_CONNECTIVITY_LINK_5 */ "", 2207 /* BRDC_DCL_CONNECTIVITY_LINK_6 */ "", 2208 /* BRDC_DCL_CONNECTIVITY_LINK_7 */ "", 2209 /* BRDC_DCL_CONNECTIVITY_LINK_8 */ "", 2210 /* BRDC_DCL_CONNECTIVITY_LINK_9 */ "", 2211 /* BRDC_DCL_CONNECTIVITY_LINK_10 */ "", 2212 /* BRDC_DCL_CONNECTIVITY_LINK_11 */ "", 2213 /* BRDC_DCL_CONNECTIVITY_LINK_12 */ "", 2214 /* BRDC_DCL_CONNECTIVITY_LINK_13 */ "", 2215 /* BRDC_DCL_CONNECTIVITY_LINK_14 */ "", 2216 /* BRDC_DCL_CONNECTIVITY_LINK_15 */ "", 2217 /* BRDC_DCL_CONNECTIVITY_LINK_16 */ "", 2218 /* BRDC_DCL_CONNECTIVITY_LINK_17 */ "", 2219 /* BRDC_DCL_CONNECTIVITY_LINK_18 */ "", 2220 /* BRDC_DCL_CONNECTIVITY_LINK_19 */ "", 2221 /* BRDC_DCL_CONNECTIVITY_LINK_20 */ "", 2222 /* BRDC_DCL_CONNECTIVITY_LINK_21 */ "", 2223 /* BRDC_DCL_CONNECTIVITY_LINK_22 */ "", 2224 /* BRDC_DCL_CONNECTIVITY_LINK_23 */ "", 2225 /* BRDC_DCL_CONNECTIVITY_LINK_24 */ "", 2226 /* BRDC_DCL_CONNECTIVITY_LINK_25 */ "", 2227 /* BRDC_DCL_CONNECTIVITY_LINK_26 */ "", 2228 /* BRDC_DCL_CONNECTIVITY_LINK_27 */ "", 2229 /* BRDC_DCL_CONNECTIVITY_LINK_28 */ "", 2230 /* BRDC_DCL_CONNECTIVITY_LINK_29 */ "", 2231 /* BRDC_DCL_CONNECTIVITY_LINK_30 */ "", 2232 /* BRDC_DCL_CONNECTIVITY_LINK_31 */ "", 2233 /* BRDC_DCL_CONNECTIVITY_LINK_32 */ "", 2234 /* BRDC_DCL_CONNECTIVITY_LINK_33 */ "", 2235 /* BRDC_DCL_CONNECTIVITY_LINK_34 */ "", 2236 /* BRDC_DCL_CONNECTIVITY_LINK_35 */ "", 2237 /* BRDC_DCL_CPU_CELL_CNT */ "", 2238 /* BRDC_DCL_CPU_DATA_CELL_0 */ "", 2239 /* BRDC_DCL_CPU_DATA_CELL_1 */ "", 2240 /* BRDC_DCL_CPU_DATA_CELL_2 */ "", 2241 /* BRDC_DCL_CPU_DATA_CELL_3 */ "", 2242 /* BRDC_DCL_CPU_DATA_CELL_4 */ "", 2243 /* BRDC_DCL_DATA_CRC_ERR_CNT */ "", 2244 /* BRDC_DCL_DCL_ENABLERS_REGISTER */ "", 2245 /* BRDC_DCL_DCL_LLFC_TH */ "", 2246 /* BRDC_DCL_DCMB_ALM_FULL_P */ "", 2247 /* BRDC_DCL_DCMB_DCL_LLFC_TH */ "", 2248 /* BRDC_DCL_DCMB_DROPPED_IP_PR_P_0_CNT */ "", 2249 /* BRDC_DCL_DCMB_DROPPED_IP_PR_P_1_CNT */ "", 2250 /* BRDC_DCL_DCMB_DROPPED_IP_PR_P_2_CNT */ "", 2251 /* BRDC_DCL_DCMB_DROPPED_SRC_P_CNT */ "", 2252 /* BRDC_DCL_DCMB_FIFO_DEPTH_TYPE */ "", 2253 /* BRDC_DCL_DCMB_LINK_WEIGHT_CONFIG_THRESHOLDS */ "", 2254 /* BRDC_DCL_DCMB_MAX_OCCUPANCY_FIFO_P */ "", 2255 /* BRDC_DCL_DCMB_TOTAL_IN_CELL_P_CNT */ "", 2256 /* BRDC_DCL_DCMB_TOTAL_OUT_CELL_P_CNT */ "", 2257 /* BRDC_DCL_DCMB_TOTAL_OUT_WORD_P_CNT */ "", 2258 /* BRDC_DCL_DCMB_TYPE_0_DRP_PRI_P */ "", 2259 /* BRDC_DCL_DCMB_TYPE_0_GCI_TH_P */ "", 2260 /* BRDC_DCL_DCMB_TYPE_0_RCI_TH_P */ "", 2261 /* BRDC_DCL_DCMB_TYPE_1_DRP_PRI_P */ "", 2262 /* BRDC_DCL_DCMB_TYPE_1_GCI_TH_P */ "", 2263 /* BRDC_DCL_DCMB_TYPE_1_RCI_TH_P */ "", 2264 /* BRDC_DCL_DCMB_UNPACKED_CELL_P_CNT */ "", 2265 /* BRDC_DCL_DLOP_RR_ENABLERS */ "", 2266 /* BRDC_DCL_DROPPED_IP_PR_P_0_CNT */ "", 2267 /* BRDC_DCL_DROPPED_IP_PR_P_1_CNT */ "", 2268 /* BRDC_DCL_DROPPED_IP_PR_P_2_CNT */ "", 2269 /* BRDC_DCL_DROPPED_SRC_P_CNT */ "", 2270 /* BRDC_DCL_DROP_CPU_CELL_CNT */ "", 2271 /* BRDC_DCL_ECC_1B_ERR_CNT */ "", 2272 /* BRDC_DCL_ECC_2B_ERR_CNT */ "", 2273 /* BRDC_DCL_ECC_ERR_1B_INITIATE */ "", 2274 /* BRDC_DCL_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 2275 /* BRDC_DCL_ECC_ERR_2B_INITIATE */ "", 2276 /* BRDC_DCL_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 2277 /* BRDC_DCL_ECC_INTERRUPT_REGISTER */ "", 2278 /* BRDC_DCL_ECC_INTERRUPT_REGISTER_MASK */ "", 2279 /* BRDC_DCL_ECC_INTERRUPT_REGISTER_TEST */ "", 2280 /* BRDC_DCL_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 2281 /* BRDC_DCL_ERROR_INITIATION_DATA */ "", 2282 /* BRDC_DCL_FIFO_DEPTH_TYPE */ "", 2283 /* BRDC_DCL_GLOBAL_GENERAL_FE_CFG_1 */ "", 2284 /* BRDC_DCL_GLOBAL_MEM_OPTIONS */ "", 2285 /* BRDC_DCL_GTIMER_CONFIGURATION */ "", 2286 /* BRDC_DCL_GTIMER_TRIGGER */ "", 2287 /* BRDC_DCL_INDIRECT_COMMAND */ "", 2288 /* BRDC_DCL_INDIRECT_COMMAND_ADDRESS */ "", 2289 /* BRDC_DCL_INDIRECT_COMMAND_DATA_INCREMENT */ "", 2290 /* BRDC_DCL_INDIRECT_COMMAND_WIDE_MEM */ "", 2291 /* BRDC_DCL_INDIRECT_COMMAND_WR_DATA */ "", 2292 /* BRDC_DCL_INDIRECT_FORCE_BUBBLE */ "", 2293 /* BRDC_DCL_INTERRUPT_MASK_REGISTER */ "", 2294 /* BRDC_DCL_INTERRUPT_REGISTER */ "", 2295 /* BRDC_DCL_INTERRUPT_REGISTER_TEST */ "", 2296 /* BRDC_DCL_LINKS_WEIGHT_CONFIG */ "", 2297 /* BRDC_DCL_LINKS_WEIGHT_CONFIG_P_0_GT_P_1 */ "", 2298 /* BRDC_DCL_LINKS_WEIGHT_CONFIG_P_1_GT_P_0 */ "", 2299 /* BRDC_DCL_LINK_CELL_PACKING_EN */ "", 2300 /* BRDC_DCL_LINK_EN_SIMPLE_UNPACK */ "", 2301 /* BRDC_DCL_LINK_LEVEL_FLOW_CONTROL_P */ "", 2302 /* BRDC_DCL_LINK_TYPE */ "", 2303 /* BRDC_DCL_LINK_WEIGHT_CONFIG_THRESHOLDS */ "", 2304 /* BRDC_DCL_LLFC_RATE_CNT_P */ "", 2305 /* BRDC_DCL_MAX_OCCUPANCY_FIFO_P */ "", 2306 /* BRDC_DCL_PCP_ERR_INFORMATION */ "", 2307 /* BRDC_DCL_PCP_VALIDITY_CHECK_ENABLERS */ "", 2308 /* BRDC_DCL_PIPES_MAP_EN */ "", 2309 /* BRDC_DCL_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTER */ "", 2310 /* BRDC_DCL_REG_0100 */ "", 2311 /* BRDC_DCL_REG_0105 */ "", 2312 /* BRDC_DCL_REG_0108 */ "", 2313 /* BRDC_DCL_REG_0118 */ "", 2314 /* BRDC_DCL_REG_0120 */ "", 2315 /* BRDC_DCL_REG_0240 */ "", 2316 /* BRDC_DCL_REG_011A */ "", 2317 /* BRDC_DCL_REG_011D */ "", 2318 /* BRDC_DCL_REG_023E */ "", 2319 /* BRDC_DCL_REMOTE_PRI_PIPE_IDX */ "", 2320 /* BRDC_DCL_REMOTE_SEC_PIPE_IDX */ "", 2321 /* BRDC_DCL_RESERVED_MIRROR_ADDR */ "", 2322 /* BRDC_DCL_RESERVED_MTCP */ "", 2323 /* BRDC_DCL_RESERVED_PCMI_0 */ "", 2324 /* BRDC_DCL_RESERVED_PCMI_1 */ "", 2325 /* BRDC_DCL_RESERVED_PCMI_0_S */ "", 2326 /* BRDC_DCL_RESERVED_PCMI_0_T */ "", 2327 /* BRDC_DCL_RESERVED_PCMI_1_S */ "", 2328 /* BRDC_DCL_RESERVED_PCMI_1_T */ "", 2329 /* BRDC_DCL_RESERVED_SPARE_0 */ "", 2330 /* BRDC_DCL_RESERVED_SPARE_1 */ "", 2331 /* BRDC_DCL_RESERVED_SPARE_2 */ "", 2332 /* BRDC_DCL_RESERVED_SPARE_3 */ "", 2333 /* BRDC_DCL_SBUS_BROADCAST_ID */ "", 2334 /* BRDC_DCL_SBUS_LAST_IN_CHAIN */ "", 2335 /* BRDC_DCL_SHAPER_AND_WFQ_CFG */ "", 2336 /* BRDC_DCL_TAG_PAR_ERR_CNT_P */ "", 2337 /* BRDC_DCL_THREE_PIPES_BMP */ "", 2338 /* BRDC_DCL_TOTAL_IN_CELL_P_CNT */ "", 2339 /* BRDC_DCL_TOTAL_OUT_CELL_P_CNT */ "", 2340 /* BRDC_DCL_TOTAL_OUT_WORD_P_CNT */ "", 2341 /* BRDC_DCL_TRANSMIT_CELL_OUTPUT_LINK_NUMBER */ "", 2342 /* BRDC_DCL_TRANSMIT_DATA_CELL_TRIGGER */ "", 2343 /* BRDC_DCL_TWO_PIPES_BMP */ "", 2344 /* BRDC_DCL_TYPE_0_DRP_PRI_P */ "", 2345 /* BRDC_DCL_TYPE_0_GCI_TH_P */ "", 2346 /* BRDC_DCL_TYPE_0_RCI_TH_P */ "", 2347 /* BRDC_DCL_TYPE_1_DRP_PRI_P */ "", 2348 /* BRDC_DCL_TYPE_1_GCI_TH_P */ "", 2349 /* BRDC_DCL_TYPE_1_RCI_TH_P */ "", 2350 /* BRDC_DCL_UNPACKED_CELL_P_CNT */ "", 2351 /* BRDC_DCML_AUTO_DOC_NAME_1 */ "", 2352 /* BRDC_DCML_AUTO_DOC_NAME_34 */ "", 2353 /* BRDC_DCML_AUTO_DOC_NAME_37 */ "", 2354 /* BRDC_DCML_AUTO_DOC_NAME_38 */ "", 2355 /* BRDC_DCML_AUTO_DOC_NAME_47 */ "", 2356 /* BRDC_DCML_AUTO_DOC_NAME_48 */ "", 2357 /* BRDC_DCML_AUTO_DOC_NAME_49 */ "", 2358 /* BRDC_DCML_CCML_CONFIGURATIONS */ "", 2359 /* BRDC_DCML_CDMA_LP_CELLS_DISCARD_CNT */ "", 2360 /* BRDC_DCML_CDMB_LP_CELLS_DISCARD_CNT */ "", 2361 /* BRDC_DCML_CDMC_LP_CELLS_DISCARD_CNT */ "", 2362 /* BRDC_DCML_CDMD_LP_CELLS_DISCARD_CNT */ "", 2363 /* BRDC_DCML_CDME_LP_CELLS_DISCARD_CNT */ "", 2364 /* BRDC_DCML_CDMF_LP_CELLS_DISCARD_CNT */ "", 2365 /* BRDC_DCML_CDMG_LP_CELLS_DISCARD_CNT */ "", 2366 /* BRDC_DCML_CDMH_LP_CELLS_DISCARD_CNT */ "", 2367 /* BRDC_DCML_CDM_OVERFLOW_FIFO_NUMBER */ "", 2368 /* BRDC_DCML_CPU_FORCE_MAC_LINK_IREADY */ "", 2369 /* BRDC_DCML_CPU_SOURCE_CELL_DATA */ "", 2370 /* BRDC_DCML_CPU_SOURCE_CELL_TRIGGER */ "", 2371 /* BRDC_DCML_CTP_CREDIT_CELLS_CNT */ "", 2372 /* BRDC_DCML_CTP_FS_CELLS_CNT */ "", 2373 /* BRDC_DCML_CTP_INTERNAL_REACHABILITY_CELLS_CNT */ "", 2374 /* BRDC_DCML_DCML_ENABLERS */ "", 2375 /* BRDC_DCML_DCML_SEPARATION_REGISTER */ "", 2376 /* BRDC_DCML_DFL_ECC_ERR_CFG */ "", 2377 /* BRDC_DCML_ECC_1B_ERR_CNT */ "", 2378 /* BRDC_DCML_ECC_2B_ERR_CNT */ "", 2379 /* BRDC_DCML_ECC_ERR_1B_INITIATE */ "", 2380 /* BRDC_DCML_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 2381 /* BRDC_DCML_ECC_ERR_2B_INITIATE */ "", 2382 /* BRDC_DCML_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 2383 /* BRDC_DCML_ECC_INTERRUPT_REGISTER */ "", 2384 /* BRDC_DCML_ECC_INTERRUPT_REGISTER_MASK */ "", 2385 /* BRDC_DCML_ECC_INTERRUPT_REGISTER_TEST */ "", 2386 /* BRDC_DCML_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 2387 /* BRDC_DCML_ERROR_INITIATION_DATA */ "", 2388 /* BRDC_DCML_FAP_GLOBAL_GENERAL_CFG_1 */ "", 2389 /* BRDC_DCML_FBC_BANK_STAT */ "", 2390 /* BRDC_DCML_FBC_BANK_STAT_DIFF */ "", 2391 /* BRDC_DCML_FE_GLOBAL_GENERAL_CFG_1 */ "", 2392 /* BRDC_DCML_FE_GLOBAL_GENERAL_CFG_2 */ "", 2393 /* BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER */ "", 2394 /* BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_MASK */ "", 2395 /* BRDC_DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_TEST */ "", 2396 /* BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER */ "", 2397 /* BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_MASK */ "", 2398 /* BRDC_DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_TEST */ "", 2399 /* BRDC_DCML_GLOBAL_MEM_OPTIONS */ "", 2400 /* BRDC_DCML_GTIMER_CONFIGURATION */ "", 2401 /* BRDC_DCML_GTIMER_CYCLE */ "", 2402 /* BRDC_DCML_INDIRECT_COMMAND */ "", 2403 /* BRDC_DCML_INDIRECT_COMMAND_ADDRESS */ "", 2404 /* BRDC_DCML_INDIRECT_COMMAND_DATA_INCREMENT */ "", 2405 /* BRDC_DCML_INDIRECT_COMMAND_RD_DATA */ "", 2406 /* BRDC_DCML_INDIRECT_COMMAND_WIDE_MEM */ "", 2407 /* BRDC_DCML_INDIRECT_COMMAND_WR_DATA */ "", 2408 /* BRDC_DCML_INDIRECT_FORCE_BUBBLE */ "", 2409 /* BRDC_DCML_INTERRUPT_MASK_REGISTER */ "", 2410 /* BRDC_DCML_INTERRUPT_REGISTER */ "", 2411 /* BRDC_DCML_INTERRUPT_REGISTER_TEST */ "", 2412 /* BRDC_DCML_MID_FIFOS_LP_WATER_MARK */ "", 2413 /* BRDC_DCML_MID_FIFOS_SATTUS_CDMA */ "", 2414 /* BRDC_DCML_MID_FIFOS_SATTUS_CDMAD */ "", 2415 /* BRDC_DCML_MID_FIFOS_SATTUS_CDMAH */ "", 2416 /* BRDC_DCML_MID_FIFOS_SATTUS_CDMB */ "", 2417 /* BRDC_DCML_MID_FIFOS_SATTUS_CDMC */ "", 2418 /* BRDC_DCML_MID_FIFOS_SATTUS_CDME */ "", 2419 /* BRDC_DCML_MID_FIFOS_SATTUS_CDMF */ "", 2420 /* BRDC_DCML_MID_FIFOS_SATTUS_CDMG */ "", 2421 /* BRDC_DCML_PCMI_0 */ "", 2422 /* BRDC_DCML_PCMI_1 */ "", 2423 /* BRDC_DCML_PCMI_2 */ "", 2424 /* BRDC_DCML_PCMI_3 */ "", 2425 /* BRDC_DCML_PCMI_0_S */ "", 2426 /* BRDC_DCML_PCMI_0_T */ "", 2427 /* BRDC_DCML_PCMI_1_S */ "", 2428 /* BRDC_DCML_PCMI_1_T */ "", 2429 /* BRDC_DCML_PCMI_2_S */ "", 2430 /* BRDC_DCML_PCMI_2_T */ "", 2431 /* BRDC_DCML_PCMI_3_S */ "", 2432 /* BRDC_DCML_PCMI_3_T */ "", 2433 /* BRDC_DCML_PIPES_MAPPING_EN */ "", 2434 /* BRDC_DCML_PROGRAMMABLE_MID_FIFOS_WATER_MARK */ "", 2435 /* BRDC_DCML_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARK */ "", 2436 /* BRDC_DCML_REMOTE_PRI_PIPE_IDX */ "", 2437 /* BRDC_DCML_REMOTE_SEC_PIPE_IDX */ "", 2438 /* BRDC_DCML_RESERVED_MIRROR_ADDR */ "", 2439 /* BRDC_DCML_RESERVED_MTCD */ "", 2440 /* BRDC_DCML_RESERVED_MTCP */ "", 2441 /* BRDC_DCML_RESERVED_SPARE_0 */ "", 2442 /* BRDC_DCML_RESERVED_SPARE_1 */ "", 2443 /* BRDC_DCML_RESERVED_SPARE_2 */ "", 2444 /* BRDC_DCML_RESERVED_SPARE_3 */ "", 2445 /* BRDC_DCML_SBUS_BROADCAST_ID */ "", 2446 /* BRDC_DCML_SBUS_LAST_IN_CHAIN */ "", 2447 /* BRDC_DCML_THREE_PIPES_BMP */ "", 2448 /* BRDC_DCML_TOTAL_OUT_CELL_P_CNT */ "", 2449 /* BRDC_DCML_TOTAL_OUT_CPU_CAPTURE_CELL_CNT */ "", 2450 /* BRDC_DCML_TOTAL_OUT_CPU_TRANSMIT_CELL_CNT */ "", 2451 /* BRDC_DCML_TOTAL_OUT_INBAND_CELL_CNT */ "", 2452 /* BRDC_DCML_TOTAL_OUT_WORD_P_CNT */ "", 2453 /* BRDC_DCML_TWO_PIPES_BMP */ "", 2454 /* BRDC_DCML_TX_CPU_CELL_DATA_0 */ "", 2455 /* BRDC_DCML_TX_CPU_CELL_DATA_1 */ "", 2456 /* BRDC_DCML_TX_CPU_CELL_HEADER */ "", 2457 /* BRDC_DCM_DCL_FLOW_CONTROL_CNT_P */ "", 2458 /* BRDC_DCM_DCM_ENABLERS_REGISTER */ "", 2459 /* BRDC_DCM_DCM_MAX_OCUP_P */ "", 2460 /* BRDC_DCM_DROP_IP_PRI_P_0_CNT */ "", 2461 /* BRDC_DCM_DROP_IP_PRI_P_1_CNT */ "", 2462 /* BRDC_DCM_DROP_IP_PRI_P_2_CNT */ "", 2463 /* BRDC_DCM_DROP_TOTAL_P_CNT */ "", 2464 /* BRDC_DCM_DYN_PIPES_WEIGHTS_REGISTER */ "", 2465 /* BRDC_DCM_DYN_WFQ_WEIGHT_THD_REGISTER */ "", 2466 /* BRDC_DCM_ECC_1B_ERR_CNT */ "", 2467 /* BRDC_DCM_ECC_2B_ERR_CNT */ "", 2468 /* BRDC_DCM_ECC_ERR_1B_INITIATE */ "", 2469 /* BRDC_DCM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 2470 /* BRDC_DCM_ECC_ERR_2B_INITIATE */ "", 2471 /* BRDC_DCM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 2472 /* BRDC_DCM_ECC_INTERRUPT_REGISTER */ "", 2473 /* BRDC_DCM_ECC_INTERRUPT_REGISTER_MASK */ "", 2474 /* BRDC_DCM_ECC_INTERRUPT_REGISTER_TEST */ "", 2475 /* BRDC_DCM_ERROR_INITIATION_DATA */ "", 2476 /* BRDC_DCM_FIFOS_DEPTH_TYPE */ "", 2477 /* BRDC_DCM_FIFOS_THRESHOLDS_P_TYPE_0 */ "", 2478 /* BRDC_DCM_FIFOS_THRESHOLDS_P_TYPE_1 */ "", 2479 /* BRDC_DCM_FIFO_TYPE */ "", 2480 /* BRDC_DCM_GCI_TH_P_TYPE_0 */ "", 2481 /* BRDC_DCM_GCI_TH_P_TYPE_1 */ "", 2482 /* BRDC_DCM_GLOBAL_DCH_CAPTURE_CELLS_DCL */ "", 2483 /* BRDC_DCM_GLOBAL_GENERAL_CFG_1 */ "", 2484 /* BRDC_DCM_GLOBAL_GENERAL_FE_CFG_1 */ "", 2485 /* BRDC_DCM_GLOBAL_MEM_OPTIONS */ "", 2486 /* BRDC_DCM_GTIMER_CONFIGURATION */ "", 2487 /* BRDC_DCM_GTIMER_TRIGGER */ "", 2488 /* BRDC_DCM_INTERRUPT_MASK_REGISTER */ "", 2489 /* BRDC_DCM_INTERRUPT_REGISTER */ "", 2490 /* BRDC_DCM_INTERRUPT_REGISTER_TEST */ "", 2491 /* BRDC_DCM_MC_LOW_PRIO_REP_THD_P_TYPE_0 */ "", 2492 /* BRDC_DCM_MC_LOW_PRIO_REP_THD_P_TYPE_1 */ "", 2493 /* BRDC_DCM_MC_LP_CELL_DRP_CNT_P */ "", 2494 /* BRDC_DCM_PIPES_WEIGHTS_REGISTER */ "", 2495 /* BRDC_DCM_PIPE_0_PRIORITY_DROP_THRESHOLD_TYPE */ "", 2496 /* BRDC_DCM_PIPE_1_PRIORITY_DROP_THRESHOLD_TYPE */ "", 2497 /* BRDC_DCM_PIPE_2_PRIORITY_DROP_THRESHOLD_TYPE */ "", 2498 /* BRDC_DCM_RCI_TH_P_TYPE_0 */ "", 2499 /* BRDC_DCM_RCI_TH_P_TYPE_1 */ "", 2500 /* BRDC_DCM_REG_0100 */ "", 2501 /* BRDC_DCM_REG_0103 */ "", 2502 /* BRDC_DCM_RESERVED_MIRROR_ADDR */ "", 2503 /* BRDC_DCM_RESERVED_MTCP */ "", 2504 /* BRDC_DCM_RESERVED_PCMI_0 */ "", 2505 /* BRDC_DCM_RESERVED_PCMI_1 */ "", 2506 /* BRDC_DCM_RESERVED_PCMI_2 */ "", 2507 /* BRDC_DCM_RESERVED_PCMI_4 */ "", 2508 /* BRDC_DCM_RESERVED_PCMI_0_S */ "", 2509 /* BRDC_DCM_RESERVED_PCMI_0_T */ "", 2510 /* BRDC_DCM_RESERVED_PCMI_1_S */ "", 2511 /* BRDC_DCM_RESERVED_PCMI_1_T */ "", 2512 /* BRDC_DCM_RESERVED_PCMI_2_S */ "", 2513 /* BRDC_DCM_RESERVED_PCMI_2_T */ "", 2514 /* BRDC_DCM_RESERVED_PCMI_4_S */ "", 2515 /* BRDC_DCM_RESERVED_PCMI_4_T */ "", 2516 /* BRDC_DCM_RESERVED_SPARE_0 */ "", 2517 /* BRDC_DCM_RESERVED_SPARE_1 */ "", 2518 /* BRDC_DCM_RESERVED_SPARE_2 */ "", 2519 /* BRDC_DCM_RESERVED_SPARE_3 */ "", 2520 /* BRDC_DCM_SBUS_BROADCAST_ID */ "", 2521 /* BRDC_DCM_SBUS_LAST_IN_CHAIN */ "", 2522 /* BRDC_DCM_TOTAL_IN_CELL_CNT_PAB */ "", 2523 /* BRDC_DCM_TOTAL_IN_CELL_CNT_PCD */ "", 2524 /* BRDC_FMACH_ASYNC_FIFO_ACCESS_READ_DATA */ "", 2525 /* BRDC_FMACH_ASYNC_FIFO_ACCESS_TRIGGER */ "", 2526 /* BRDC_FMACH_ASYNC_FIFO_CONFIGURATION */ "", 2527 /* BRDC_FMACH_BEC_CONFIGURATION */ "", 2528 /* BRDC_FMACH_BEC_STATUS */ "", 2529 /* BRDC_FMACH_BER_GEN_BITMAP */ "", 2530 /* BRDC_FMACH_BER_GEN_PERIOD */ "", 2531 /* BRDC_FMACH_CNTRL_INTRLVD_MODE_REG */ "", 2532 /* BRDC_FMACH_CONTROL_CELL_BURST_REGISTER */ "", 2533 /* BRDC_FMACH_ECC_1B_ERR_ADDR */ "", 2534 /* BRDC_FMACH_ECC_1B_ERR_CNT */ "", 2535 /* BRDC_FMACH_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 2536 /* BRDC_FMACH_ECC_2B_ERR_ADDR */ "", 2537 /* BRDC_FMACH_ECC_2B_ERR_CNT */ "", 2538 /* BRDC_FMACH_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 2539 /* BRDC_FMACH_EDS_CONFIGURATION */ "", 2540 /* BRDC_FMACH_EDS_STATUS */ "", 2541 /* BRDC_FMACH_ERROR_INITIATION */ "", 2542 /* BRDC_FMACH_ERROR_INITIATION_DATA */ "", 2543 /* BRDC_FMACH_FBIST_CONFIGURATION_A */ "", 2544 /* BRDC_FMACH_FBIST_CONFIGURATION_B */ "", 2545 /* BRDC_FMACH_FBIST_STATUS */ "", 2546 /* BRDC_FMACH_FMAL_COMMA_BURST_CONFIGURATION */ "", 2547 /* BRDC_FMACH_FMAL_GENERAL_CONFIGURATION */ "", 2548 /* BRDC_FMACH_FMAL_STATISTICS_COUNT_CONTROL */ "", 2549 /* BRDC_FMACH_FMAL_STATISTICS_GTIMER */ "", 2550 /* BRDC_FMACH_FMAL_STATISTICS_OUTPUT */ "", 2551 /* BRDC_FMACH_FMAL_STATISTICS_OUTPUT_CONTROL */ "", 2552 /* BRDC_FMACH_FPS_CONFIGURATION_BER */ "", 2553 /* BRDC_FMACH_FPS_CONFIGURATION_RX_SYNC */ "", 2554 /* BRDC_FMACH_FPS_RX_FEC_CONFIGURATION */ "", 2555 /* BRDC_FMACH_FPS_RX_STATUS */ "", 2556 /* BRDC_FMACH_FPS_TX_CONFIGURATION */ "", 2557 /* BRDC_FMACH_GENERAL_CONFIGURATION_REGISTER */ "", 2558 /* BRDC_FMACH_GLOBAL_TEST_RX_IDL_PTRN */ "", 2559 /* BRDC_FMACH_GLOBAL_TEST_TX_IDL_PTRN */ "", 2560 /* BRDC_FMACH_GLOBAL_TEST_TX_PR_SEED_A */ "", 2561 /* BRDC_FMACH_GLOBAL_TEST_TX_PR_SEED_B */ "", 2562 /* BRDC_FMACH_GTIMER_CONFIGURATION */ "", 2563 /* BRDC_FMACH_GTIMER_TRIGGER */ "", 2564 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER */ "", 2565 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_1 */ "", 2566 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_2 */ "", 2567 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_3 */ "", 2568 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_4 */ "", 2569 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_5 */ "", 2570 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_6 */ "", 2571 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_7 */ "", 2572 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_8 */ "", 2573 /* BRDC_FMACH_INTERRUPT_MASK_REGISTER_9 */ "", 2574 /* BRDC_FMACH_INTERRUPT_REGISTER */ "", 2575 /* BRDC_FMACH_INTERRUPT_REGISTER_1 */ "", 2576 /* BRDC_FMACH_INTERRUPT_REGISTER_2 */ "", 2577 /* BRDC_FMACH_INTERRUPT_REGISTER_3 */ "", 2578 /* BRDC_FMACH_INTERRUPT_REGISTER_4 */ "", 2579 /* BRDC_FMACH_INTERRUPT_REGISTER_5 */ "", 2580 /* BRDC_FMACH_INTERRUPT_REGISTER_6 */ "", 2581 /* BRDC_FMACH_INTERRUPT_REGISTER_7 */ "", 2582 /* BRDC_FMACH_INTERRUPT_REGISTER_8 */ "", 2583 /* BRDC_FMACH_INTERRUPT_REGISTER_9 */ "", 2584 /* BRDC_FMACH_KPCS_CONFIGURATION */ "", 2585 /* BRDC_FMACH_KPCS_RX_STATUS */ "", 2586 /* BRDC_FMACH_KPCS_TEST_RX_CONFIGURATION */ "", 2587 /* BRDC_FMACH_KPCS_TEST_RX_STATUS */ "", 2588 /* BRDC_FMACH_KPCS_TEST_TX_CONFIGURATION */ "", 2589 /* BRDC_FMACH_LEAKY_BUCKET */ "", 2590 /* BRDC_FMACH_LEAKY_BUCKET_CONTROL_REGISTER */ "", 2591 /* BRDC_FMACH_LFEC_CONFIGURATION */ "", 2592 /* BRDC_FMACH_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER */ "", 2593 /* BRDC_FMACH_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER */ "", 2594 /* BRDC_FMACH_LOOPBACK_ENABLE_REGISTER */ "", 2595 /* BRDC_FMACH_RECEIVE_RESET_REGISTER */ "", 2596 /* BRDC_FMACH_REG_0050 */ "", 2597 /* BRDC_FMACH_REG_0051 */ "", 2598 /* BRDC_FMACH_REG_0052 */ "", 2599 /* BRDC_FMACH_REG_0054 */ "", 2600 /* BRDC_FMACH_REG_0065 */ "", 2601 /* BRDC_FMACH_REG_0066 */ "", 2602 /* BRDC_FMACH_REG_0096 */ "", 2603 /* BRDC_FMACH_REG_0098 */ "", 2604 /* BRDC_FMACH_REG_0099 */ "", 2605 /* BRDC_FMACH_REG_0140 */ "", 2606 /* BRDC_FMACH_REG_005A */ "", 2607 /* BRDC_FMACH_REG_005B */ "", 2608 /* BRDC_FMACH_REG_01A8 */ "", 2609 /* BRDC_FMACH_REG_01AC */ "", 2610 /* BRDC_FMACH_REG_01E9 */ "", 2611 /* BRDC_FMACH_REG_01EA */ "", 2612 /* BRDC_FMACH_REG_01EB */ "", 2613 /* BRDC_FMACH_REG_01EC */ "", 2614 /* BRDC_FMACH_REG_01ED */ "", 2615 /* BRDC_FMACH_REG_01EE */ "", 2616 /* BRDC_FMACH_REG_01EF */ "", 2617 /* BRDC_FMACH_REG_01FA */ "", 2618 /* BRDC_FMACH_REG_1E8 */ "", 2619 /* BRDC_FMACH_SBUS_BROADCAST_ID */ "", 2620 /* BRDC_FMACH_SBUS_LAST_IN_CHAIN */ "", 2621 /* BRDC_FMACH_SPARE_REGISTER_3 */ "", 2622 /* BRDC_FMACH_TEST_CONFIGURATION */ "", 2623 /* BRDC_FMACH_TEST_STATUS */ "", 2624 /* BRDC_FMACH_TX_CELL_LIMIT */ "", 2625 /* BRDC_FMACL_ASYNC_FIFO_ACCESS_READ_DATA */ "", 2626 /* BRDC_FMACL_ASYNC_FIFO_ACCESS_TRIGGER */ "", 2627 /* BRDC_FMACL_ASYNC_FIFO_CONFIGURATION */ "", 2628 /* BRDC_FMACL_BEC_CONFIGURATION */ "", 2629 /* BRDC_FMACL_BEC_STATUS */ "", 2630 /* BRDC_FMACL_BER_GEN_BITMAP */ "", 2631 /* BRDC_FMACL_BER_GEN_PERIOD */ "", 2632 /* BRDC_FMACL_CNTRL_INTRLVD_MODE_REG */ "", 2633 /* BRDC_FMACL_CONTROL_CELL_BURST_REGISTER */ "", 2634 /* BRDC_FMACL_ECC_1B_ERR_ADDR */ "", 2635 /* BRDC_FMACL_ECC_1B_ERR_CNT */ "", 2636 /* BRDC_FMACL_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 2637 /* BRDC_FMACL_ECC_2B_ERR_ADDR */ "", 2638 /* BRDC_FMACL_ECC_2B_ERR_CNT */ "", 2639 /* BRDC_FMACL_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 2640 /* BRDC_FMACL_EDS_CONFIGURATION */ "", 2641 /* BRDC_FMACL_EDS_STATUS */ "", 2642 /* BRDC_FMACL_ERROR_INITIATION */ "", 2643 /* BRDC_FMACL_ERROR_INITIATION_DATA */ "", 2644 /* BRDC_FMACL_FBIST_CONFIGURATION_A */ "", 2645 /* BRDC_FMACL_FBIST_CONFIGURATION_B */ "", 2646 /* BRDC_FMACL_FBIST_STATUS */ "", 2647 /* BRDC_FMACL_FMAL_COMMA_BURST_CONFIGURATION */ "", 2648 /* BRDC_FMACL_FMAL_GENERAL_CONFIGURATION */ "", 2649 /* BRDC_FMACL_FMAL_STATISTICS_COUNT_CONTROL */ "", 2650 /* BRDC_FMACL_FMAL_STATISTICS_GTIMER */ "", 2651 /* BRDC_FMACL_FMAL_STATISTICS_OUTPUT */ "", 2652 /* BRDC_FMACL_FMAL_STATISTICS_OUTPUT_CONTROL */ "", 2653 /* BRDC_FMACL_FPS_CONFIGURATION_BER */ "", 2654 /* BRDC_FMACL_FPS_CONFIGURATION_RX_SYNC */ "", 2655 /* BRDC_FMACL_FPS_RX_FEC_CONFIGURATION */ "", 2656 /* BRDC_FMACL_FPS_RX_STATUS */ "", 2657 /* BRDC_FMACL_FPS_TX_CONFIGURATION */ "", 2658 /* BRDC_FMACL_GENERAL_CONFIGURATION_REGISTER */ "", 2659 /* BRDC_FMACL_GLOBAL_TEST_RX_IDL_PTRN */ "", 2660 /* BRDC_FMACL_GLOBAL_TEST_TX_IDL_PTRN */ "", 2661 /* BRDC_FMACL_GLOBAL_TEST_TX_PR_SEED_A */ "", 2662 /* BRDC_FMACL_GLOBAL_TEST_TX_PR_SEED_B */ "", 2663 /* BRDC_FMACL_GTIMER_CONFIGURATION */ "", 2664 /* BRDC_FMACL_GTIMER_TRIGGER */ "", 2665 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER */ "", 2666 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_1 */ "", 2667 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_2 */ "", 2668 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_3 */ "", 2669 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_4 */ "", 2670 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_5 */ "", 2671 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_6 */ "", 2672 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_7 */ "", 2673 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_8 */ "", 2674 /* BRDC_FMACL_INTERRUPT_MASK_REGISTER_9 */ "", 2675 /* BRDC_FMACL_INTERRUPT_REGISTER */ "", 2676 /* BRDC_FMACL_INTERRUPT_REGISTER_1 */ "", 2677 /* BRDC_FMACL_INTERRUPT_REGISTER_2 */ "", 2678 /* BRDC_FMACL_INTERRUPT_REGISTER_3 */ "", 2679 /* BRDC_FMACL_INTERRUPT_REGISTER_4 */ "", 2680 /* BRDC_FMACL_INTERRUPT_REGISTER_5 */ "", 2681 /* BRDC_FMACL_INTERRUPT_REGISTER_6 */ "", 2682 /* BRDC_FMACL_INTERRUPT_REGISTER_7 */ "", 2683 /* BRDC_FMACL_INTERRUPT_REGISTER_8 */ "", 2684 /* BRDC_FMACL_INTERRUPT_REGISTER_9 */ "", 2685 /* BRDC_FMACL_KPCS_CONFIGURATION */ "", 2686 /* BRDC_FMACL_KPCS_RX_STATUS */ "", 2687 /* BRDC_FMACL_KPCS_TEST_RX_CONFIGURATION */ "", 2688 /* BRDC_FMACL_KPCS_TEST_RX_STATUS */ "", 2689 /* BRDC_FMACL_KPCS_TEST_TX_CONFIGURATION */ "", 2690 /* BRDC_FMACL_LEAKY_BUCKET */ "", 2691 /* BRDC_FMACL_LEAKY_BUCKET_CONTROL_REGISTER */ "", 2692 /* BRDC_FMACL_LFEC_CONFIGURATION */ "", 2693 /* BRDC_FMACL_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER */ "", 2694 /* BRDC_FMACL_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER */ "", 2695 /* BRDC_FMACL_LOOPBACK_ENABLE_REGISTER */ "", 2696 /* BRDC_FMACL_RECEIVE_RESET_REGISTER */ "", 2697 /* BRDC_FMACL_REG_0050 */ "", 2698 /* BRDC_FMACL_REG_0051 */ "", 2699 /* BRDC_FMACL_REG_0052 */ "", 2700 /* BRDC_FMACL_REG_0054 */ "", 2701 /* BRDC_FMACL_REG_0065 */ "", 2702 /* BRDC_FMACL_REG_0066 */ "", 2703 /* BRDC_FMACL_REG_0096 */ "", 2704 /* BRDC_FMACL_REG_0098 */ "", 2705 /* BRDC_FMACL_REG_0099 */ "", 2706 /* BRDC_FMACL_REG_0140 */ "", 2707 /* BRDC_FMACL_REG_005A */ "", 2708 /* BRDC_FMACL_REG_005B */ "", 2709 /* BRDC_FMACL_REG_01A8 */ "", 2710 /* BRDC_FMACL_REG_01AC */ "", 2711 /* BRDC_FMACL_REG_01E9 */ "", 2712 /* BRDC_FMACL_REG_01EA */ "", 2713 /* BRDC_FMACL_REG_01EB */ "", 2714 /* BRDC_FMACL_REG_01EC */ "", 2715 /* BRDC_FMACL_REG_01ED */ "", 2716 /* BRDC_FMACL_REG_01EE */ "", 2717 /* BRDC_FMACL_REG_01EF */ "", 2718 /* BRDC_FMACL_REG_01FA */ "", 2719 /* BRDC_FMACL_REG_1E8 */ "", 2720 /* BRDC_FMACL_SBUS_BROADCAST_ID */ "", 2721 /* BRDC_FMACL_SBUS_LAST_IN_CHAIN */ "", 2722 /* BRDC_FMACL_SPARE_REGISTER_3 */ "", 2723 /* BRDC_FMACL_TEST_CONFIGURATION */ "", 2724 /* BRDC_FMACL_TEST_STATUS */ "", 2725 /* BRDC_FMACL_TX_CELL_LIMIT */ "", 2726 /* BRDC_FMAC_AC_ASYNC_FIFO_CONFIGURATION */ "", 2727 /* BRDC_FMAC_AC_BER_GEN_BITMAP */ "", 2728 /* BRDC_FMAC_AC_BER_GEN_PERIOD */ "", 2729 /* BRDC_FMAC_AC_FBIST_CONFIGURATION_A */ "", 2730 /* BRDC_FMAC_AC_FBIST_CONFIGURATION_B */ "", 2731 /* BRDC_FMAC_AC_FBIST_STATUS */ "", 2732 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_1 */ "", 2733 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_2 */ "", 2734 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_3 */ "", 2735 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_4 */ "", 2736 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_5 */ "", 2737 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_6 */ "", 2738 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_7 */ "", 2739 /* BRDC_FMAC_AC_FMAC_INTERRUPT_MASK_REGISTER_8 */ "", 2740 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1 */ "", 2741 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2 */ "", 2742 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3 */ "", 2743 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4 */ "", 2744 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5 */ "", 2745 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6 */ "", 2746 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7 */ "", 2747 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8 */ "", 2748 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_1_TEST */ "", 2749 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_2_TEST */ "", 2750 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_3_TEST */ "", 2751 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_4_TEST */ "", 2752 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_5_TEST */ "", 2753 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_6_TEST */ "", 2754 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_7_TEST */ "", 2755 /* BRDC_FMAC_AC_FMAC_INTERRUPT_REGISTER_8_TEST */ "", 2756 /* BRDC_FMAC_AC_FMAL_GENERAL_CONFIGURATION */ "", 2757 /* BRDC_FMAC_AC_FMAL_RX_GENERAL_CONFIGURATION */ "", 2758 /* BRDC_FMAC_AC_FMAL_STATISTICS_COUNT_CONTROL */ "", 2759 /* BRDC_FMAC_AC_FMAL_STATISTICS_GTIMER */ "", 2760 /* BRDC_FMAC_AC_FMAL_STATISTICS_OUTPUT_CONTROL */ "", 2761 /* BRDC_FMAC_AC_FMAL_TX_COMMA_BURST_CONFIGURATION */ "", 2762 /* BRDC_FMAC_AC_FMAL_TX_CONTROL_BURST_CONFIGURATION */ "", 2763 /* BRDC_FMAC_AC_FMAL_TX_GENERAL_CONFIGURATION */ "", 2764 /* BRDC_FMAC_AC_FPS_CONFIGURATION_BER */ "", 2765 /* BRDC_FMAC_AC_FPS_CONFIGURATION_RX_SYNC */ "", 2766 /* BRDC_FMAC_AC_FPS_RX_FEC_CONFIGURATION */ "", 2767 /* BRDC_FMAC_AC_FPS_RX_STATUS */ "", 2768 /* BRDC_FMAC_AC_FPS_TX_CONFIGURATION */ "", 2769 /* BRDC_FMAC_AC_GENERAL_CONFIGURATION_REGISTER */ "", 2770 /* BRDC_FMAC_AC_GLOBAL_GENERAL_CFG_1 */ "", 2771 /* BRDC_FMAC_AC_GLOBAL_GENERAL_FE_CFG_1 */ "", 2772 /* BRDC_FMAC_AC_GLOBAL_MEM_OPTIONS */ "", 2773 /* BRDC_FMAC_AC_GLOBAL_TEST_RX_IDL_PTRN */ "", 2774 /* BRDC_FMAC_AC_GLOBAL_TEST_TX_IDL_PTRN */ "", 2775 /* BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_A */ "", 2776 /* BRDC_FMAC_AC_GLOBAL_TEST_TX_PR_SEED_B */ "", 2777 /* BRDC_FMAC_AC_GRACEFULL_POWER_ON_OFF */ "", 2778 /* BRDC_FMAC_AC_GTIMER_CONFIGURATION */ "", 2779 /* BRDC_FMAC_AC_GTIMER_TRIGGER */ "", 2780 /* BRDC_FMAC_AC_INTERRUPT_MASK_REGISTER */ "", 2781 /* BRDC_FMAC_AC_INTERRUPT_REGISTER */ "", 2782 /* BRDC_FMAC_AC_INTERRUPT_REGISTER_TEST */ "", 2783 /* BRDC_FMAC_AC_KPCS_CONFIGURATION */ "", 2784 /* BRDC_FMAC_AC_KPCS_RX_STATUS */ "", 2785 /* BRDC_FMAC_AC_KPCS_TEST_RX_CONFIGURATION */ "", 2786 /* BRDC_FMAC_AC_KPCS_TEST_RX_STATUS */ "", 2787 /* BRDC_FMAC_AC_KPCS_TEST_TX_CONFIGURATION */ "", 2788 /* BRDC_FMAC_AC_LEAKY_BUCKET */ "", 2789 /* BRDC_FMAC_AC_LEAKY_BUCKET_CONTROL_REGISTER */ "", 2790 /* BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER */ "", 2791 /* BRDC_FMAC_AC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER */ "", 2792 /* BRDC_FMAC_AC_LINK_TOPO_MODE_REG_0 */ "", 2793 /* BRDC_FMAC_AC_LINK_TOPO_MODE_REG_2 */ "", 2794 /* BRDC_FMAC_AC_LOOPBACK_ENABLE_REGISTER */ "", 2795 /* BRDC_FMAC_AC_RECEIVE_RESET_REGISTER */ "", 2796 /* BRDC_FMAC_AC_REG_0102 */ "", 2797 /* BRDC_FMAC_AC_REG_0116 */ "", 2798 /* BRDC_FMAC_AC_REG_0118 */ "", 2799 /* BRDC_FMAC_AC_REG_0119 */ "", 2800 /* BRDC_FMAC_AC_REG_0139 */ "", 2801 /* BRDC_FMAC_AC_RESERVED_MIRROR_ADDR */ "", 2802 /* BRDC_FMAC_AC_RESERVED_MTCP */ "", 2803 /* BRDC_FMAC_AC_RESERVED_SPARE_0 */ "", 2804 /* BRDC_FMAC_AC_RESERVED_SPARE_1 */ "", 2805 /* BRDC_FMAC_AC_RESERVED_SPARE_2 */ "", 2806 /* BRDC_FMAC_AC_RESERVED_SPARE_3 */ "", 2807 /* BRDC_FMAC_AC_RSF_CONFIGURATION */ "", 2808 /* BRDC_FMAC_AC_RSF_STATUS */ "", 2809 /* BRDC_FMAC_AC_SBUS_BROADCAST_ID */ "", 2810 /* BRDC_FMAC_AC_SBUS_LAST_IN_CHAIN */ "", 2811 /* BRDC_FMAC_AC_TX_CELL_LIMIT */ "", 2812 /* BRDC_FMAC_ASYNC_FIFO_CONFIGURATION */ "", 2813 /* BRDC_FMAC_AUTO_DOC_NAME_12 */ "", 2814 /* BRDC_FMAC_AUTO_DOC_NAME_36 */ "", 2815 /* BRDC_FMAC_AUTO_DOC_NAME_37 */ "", 2816 /* BRDC_FMAC_AUTO_DOC_NAME_38 */ "", 2817 /* BRDC_FMAC_AUTO_DOC_NAME_39 */ "", 2818 /* BRDC_FMAC_AUTO_DOC_NAME_40 */ "", 2819 /* BRDC_FMAC_AUTO_DOC_NAME_41 */ "", 2820 /* BRDC_FMAC_AUTO_DOC_NAME_42 */ "", 2821 /* BRDC_FMAC_AUTO_DOC_NAME_43 */ "", 2822 /* BRDC_FMAC_BD_ASYNC_FIFO_CONFIGURATION */ "", 2823 /* BRDC_FMAC_BD_BER_GEN_BITMAP */ "", 2824 /* BRDC_FMAC_BD_BER_GEN_PERIOD */ "", 2825 /* BRDC_FMAC_BD_FBIST_CONFIGURATION_A */ "", 2826 /* BRDC_FMAC_BD_FBIST_CONFIGURATION_B */ "", 2827 /* BRDC_FMAC_BD_FBIST_STATUS */ "", 2828 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_1 */ "", 2829 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_2 */ "", 2830 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_3 */ "", 2831 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_4 */ "", 2832 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_5 */ "", 2833 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_6 */ "", 2834 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_7 */ "", 2835 /* BRDC_FMAC_BD_FMAC_INTERRUPT_MASK_REGISTER_8 */ "", 2836 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_1 */ "", 2837 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_2 */ "", 2838 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_3 */ "", 2839 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_4 */ "", 2840 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_5 */ "", 2841 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_6 */ "", 2842 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_7 */ "", 2843 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_8 */ "", 2844 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_1_TEST */ "", 2845 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_2_TEST */ "", 2846 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_3_TEST */ "", 2847 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_4_TEST */ "", 2848 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_5_TEST */ "", 2849 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_6_TEST */ "", 2850 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_7_TEST */ "", 2851 /* BRDC_FMAC_BD_FMAC_INTERRUPT_REGISTER_8_TEST */ "", 2852 /* BRDC_FMAC_BD_FMAL_GENERAL_CONFIGURATION */ "", 2853 /* BRDC_FMAC_BD_FMAL_RX_GENERAL_CONFIGURATION */ "", 2854 /* BRDC_FMAC_BD_FMAL_STATISTICS_COUNT_CONTROL */ "", 2855 /* BRDC_FMAC_BD_FMAL_STATISTICS_GTIMER */ "", 2856 /* BRDC_FMAC_BD_FMAL_STATISTICS_OUTPUT_CONTROL */ "", 2857 /* BRDC_FMAC_BD_FMAL_TX_COMMA_BURST_CONFIGURATION */ "", 2858 /* BRDC_FMAC_BD_FMAL_TX_CONTROL_BURST_CONFIGURATION */ "", 2859 /* BRDC_FMAC_BD_FMAL_TX_GENERAL_CONFIGURATION */ "", 2860 /* BRDC_FMAC_BD_FPS_CONFIGURATION_BER */ "", 2861 /* BRDC_FMAC_BD_FPS_CONFIGURATION_RX_SYNC */ "", 2862 /* BRDC_FMAC_BD_FPS_RX_FEC_CONFIGURATION */ "", 2863 /* BRDC_FMAC_BD_FPS_RX_STATUS */ "", 2864 /* BRDC_FMAC_BD_FPS_TX_CONFIGURATION */ "", 2865 /* BRDC_FMAC_BD_GENERAL_CONFIGURATION_REGISTER */ "", 2866 /* BRDC_FMAC_BD_GLOBAL_GENERAL_CFG_1 */ "", 2867 /* BRDC_FMAC_BD_GLOBAL_GENERAL_FE_CFG_1 */ "", 2868 /* BRDC_FMAC_BD_GLOBAL_MEM_OPTIONS */ "", 2869 /* BRDC_FMAC_BD_GLOBAL_TEST_RX_IDL_PTRN */ "", 2870 /* BRDC_FMAC_BD_GLOBAL_TEST_TX_IDL_PTRN */ "", 2871 /* BRDC_FMAC_BD_GLOBAL_TEST_TX_PR_SEED_A */ "", 2872 /* BRDC_FMAC_BD_GLOBAL_TEST_TX_PR_SEED_B */ "", 2873 /* BRDC_FMAC_BD_GRACEFULL_POWER_ON_OFF */ "", 2874 /* BRDC_FMAC_BD_GTIMER_CONFIGURATION */ "", 2875 /* BRDC_FMAC_BD_GTIMER_TRIGGER */ "", 2876 /* BRDC_FMAC_BD_INTERRUPT_MASK_REGISTER */ "", 2877 /* BRDC_FMAC_BD_INTERRUPT_REGISTER */ "", 2878 /* BRDC_FMAC_BD_INTERRUPT_REGISTER_TEST */ "", 2879 /* BRDC_FMAC_BD_KPCS_CONFIGURATION */ "", 2880 /* BRDC_FMAC_BD_KPCS_RX_STATUS */ "", 2881 /* BRDC_FMAC_BD_KPCS_TEST_RX_CONFIGURATION */ "", 2882 /* BRDC_FMAC_BD_KPCS_TEST_RX_STATUS */ "", 2883 /* BRDC_FMAC_BD_KPCS_TEST_TX_CONFIGURATION */ "", 2884 /* BRDC_FMAC_BD_LEAKY_BUCKET */ "", 2885 /* BRDC_FMAC_BD_LEAKY_BUCKET_CONTROL_REGISTER */ "", 2886 /* BRDC_FMAC_BD_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER */ "", 2887 /* BRDC_FMAC_BD_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER */ "", 2888 /* BRDC_FMAC_BD_LINK_TOPO_MODE_REG_0 */ "", 2889 /* BRDC_FMAC_BD_LINK_TOPO_MODE_REG_2 */ "", 2890 /* BRDC_FMAC_BD_LOOPBACK_ENABLE_REGISTER */ "", 2891 /* BRDC_FMAC_BD_RECEIVE_RESET_REGISTER */ "", 2892 /* BRDC_FMAC_BD_REG_0102 */ "", 2893 /* BRDC_FMAC_BD_REG_0116 */ "", 2894 /* BRDC_FMAC_BD_REG_0118 */ "", 2895 /* BRDC_FMAC_BD_REG_0119 */ "", 2896 /* BRDC_FMAC_BD_REG_0139 */ "", 2897 /* BRDC_FMAC_BD_RESERVED_MIRROR_ADDR */ "", 2898 /* BRDC_FMAC_BD_RESERVED_MTCP */ "", 2899 /* BRDC_FMAC_BD_RESERVED_SPARE_0 */ "", 2900 /* BRDC_FMAC_BD_RESERVED_SPARE_1 */ "", 2901 /* BRDC_FMAC_BD_RESERVED_SPARE_2 */ "", 2902 /* BRDC_FMAC_BD_RESERVED_SPARE_3 */ "", 2903 /* BRDC_FMAC_BD_RSF_CONFIGURATION */ "", 2904 /* BRDC_FMAC_BD_RSF_STATUS */ "", 2905 /* BRDC_FMAC_BD_SBUS_BROADCAST_ID */ "", 2906 /* BRDC_FMAC_BD_SBUS_LAST_IN_CHAIN */ "", 2907 /* BRDC_FMAC_BD_TX_CELL_LIMIT */ "", 2908 /* BRDC_FMAC_BEC_CONFIGURATION */ "", 2909 /* BRDC_FMAC_BEC_STATUS */ "", 2910 /* BRDC_FMAC_BER_GEN_BITMAP */ "", 2911 /* BRDC_FMAC_BER_GEN_PERIOD */ "", 2912 /* BRDC_FMAC_CNTRL_INTRLVD_MODE_REG */ "", 2913 /* BRDC_FMAC_CONTROL_CELL_BURST_REGISTER */ "", 2914 /* BRDC_FMAC_DATA_FIFO_WMK */ "", 2915 /* BRDC_FMAC_ECC_1B_ERR_ADDR */ "", 2916 /* BRDC_FMAC_ECC_1B_ERR_CNT */ "", 2917 /* BRDC_FMAC_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 2918 /* BRDC_FMAC_ECC_2B_ERR_ADDR */ "", 2919 /* BRDC_FMAC_ECC_2B_ERR_CNT */ "", 2920 /* BRDC_FMAC_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 2921 /* BRDC_FMAC_ECC_ERR_1B_INITIATE */ "", 2922 /* BRDC_FMAC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 2923 /* BRDC_FMAC_ECC_ERR_2B_INITIATE */ "", 2924 /* BRDC_FMAC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 2925 /* BRDC_FMAC_ECC_INTERRUPT_REGISTER */ "", 2926 /* BRDC_FMAC_ECC_INTERRUPT_REGISTER_MASK */ "", 2927 /* BRDC_FMAC_ECC_INTERRUPT_REGISTER_TEST */ "", 2928 /* BRDC_FMAC_EDS_CONFIGURATION */ "", 2929 /* BRDC_FMAC_EDS_STATUS */ "", 2930 /* BRDC_FMAC_ERROR_INITIATION */ "", 2931 /* BRDC_FMAC_ERROR_INITIATION_DATA */ "", 2932 /* BRDC_FMAC_FABRIC_SYSTEM_CONFIG_0 */ "", 2933 /* BRDC_FMAC_FABRIC_SYSTEM_CONFIG_1 */ "", 2934 /* BRDC_FMAC_FAP_GLOBAL_GENERAL_CFG_1 */ "", 2935 /* BRDC_FMAC_FBIST_CONFIGURATION_A */ "", 2936 /* BRDC_FMAC_FBIST_CONFIGURATION_B */ "", 2937 /* BRDC_FMAC_FBIST_STATUS */ "", 2938 /* BRDC_FMAC_FE_GLOBAL_GENERAL_CFG_1 */ "", 2939 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_1 */ "", 2940 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_2 */ "", 2941 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_3 */ "", 2942 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_4 */ "", 2943 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_5 */ "", 2944 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_6 */ "", 2945 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_7 */ "", 2946 /* BRDC_FMAC_FMAC_INTERRUPT_MASK_REGISTER_8 */ "", 2947 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1 */ "", 2948 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2 */ "", 2949 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3 */ "", 2950 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4 */ "", 2951 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5 */ "", 2952 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6 */ "", 2953 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7 */ "", 2954 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8 */ "", 2955 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_1_TEST */ "", 2956 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_2_TEST */ "", 2957 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_3_TEST */ "", 2958 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_4_TEST */ "", 2959 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_5_TEST */ "", 2960 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_6_TEST */ "", 2961 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_7_TEST */ "", 2962 /* BRDC_FMAC_FMAC_INTERRUPT_REGISTER_8_TEST */ "", 2963 /* BRDC_FMAC_FMAL_COMMA_BURST_CONFIGURATION */ "", 2964 /* BRDC_FMAC_FMAL_GENERAL_CONFIGURATION */ "", 2965 /* BRDC_FMAC_FMAL_RCI_GCI_WMK */ "", 2966 /* BRDC_FMAC_FMAL_RX_GENERAL_CONFIGURATION */ "", 2967 /* BRDC_FMAC_FMAL_STATISTICS_COUNT_CONTROL */ "", 2968 /* BRDC_FMAC_FMAL_STATISTICS_GTIMER */ "", 2969 /* BRDC_FMAC_FMAL_STATISTICS_OUTPUT */ "", 2970 /* BRDC_FMAC_FMAL_STATISTICS_OUTPUT_CONTROL */ "", 2971 /* BRDC_FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION */ "", 2972 /* BRDC_FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION */ "", 2973 /* BRDC_FMAC_FMAL_TX_DC_AUTO_ADJUST */ "", 2974 /* BRDC_FMAC_FMAL_TX_GENERAL_CONFIGURATION */ "", 2975 /* BRDC_FMAC_FMAL_TX_SIMPLE_UNPACKING_CNT */ "", 2976 /* BRDC_FMAC_FPS_CONFIGURATION_BER */ "", 2977 /* BRDC_FMAC_FPS_CONFIGURATION_RX_SYNC */ "", 2978 /* BRDC_FMAC_FPS_RX_FEC_CONFIGURATION */ "", 2979 /* BRDC_FMAC_FPS_RX_STATUS */ "", 2980 /* BRDC_FMAC_FPS_TX_CONFIGURATION */ "", 2981 /* BRDC_FMAC_GENERAL_CONFIGURATION_REGISTER */ "", 2982 /* BRDC_FMAC_GLOBAL_GENERAL_CFG_1 */ "", 2983 /* BRDC_FMAC_GLOBAL_GENERAL_FE_CFG_1 */ "", 2984 /* BRDC_FMAC_GLOBAL_MEM_OPTIONS */ "", 2985 /* BRDC_FMAC_GLOBAL_TEST_RX_IDL_PTRN */ "", 2986 /* BRDC_FMAC_GLOBAL_TEST_TX_IDL_PTRN */ "", 2987 /* BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_A */ "", 2988 /* BRDC_FMAC_GLOBAL_TEST_TX_PR_SEED_B */ "", 2989 /* BRDC_FMAC_GRACEFULL_POWER_ON_OFF */ "", 2990 /* BRDC_FMAC_GTIMER_CONFIGURATION */ "", 2991 /* BRDC_FMAC_GTIMER_CYCLE */ "", 2992 /* BRDC_FMAC_GTIMER_TRIGGER */ "", 2993 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER */ "", 2994 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_1 */ "", 2995 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_2 */ "", 2996 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_3 */ "", 2997 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_4 */ "", 2998 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_5 */ "", 2999 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_6 */ "", 3000 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_7 */ "", 3001 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_8 */ "", 3002 /* BRDC_FMAC_INTERRUPT_MASK_REGISTER_9 */ "", 3003 /* BRDC_FMAC_INTERRUPT_REGISTER */ "", 3004 /* BRDC_FMAC_INTERRUPT_REGISTER_1 */ "", 3005 /* BRDC_FMAC_INTERRUPT_REGISTER_2 */ "", 3006 /* BRDC_FMAC_INTERRUPT_REGISTER_3 */ "", 3007 /* BRDC_FMAC_INTERRUPT_REGISTER_4 */ "", 3008 /* BRDC_FMAC_INTERRUPT_REGISTER_5 */ "", 3009 /* BRDC_FMAC_INTERRUPT_REGISTER_6 */ "", 3010 /* BRDC_FMAC_INTERRUPT_REGISTER_7 */ "", 3011 /* BRDC_FMAC_INTERRUPT_REGISTER_8 */ "", 3012 /* BRDC_FMAC_INTERRUPT_REGISTER_9 */ "", 3013 /* BRDC_FMAC_INTERRUPT_REGISTER_1_TEST */ "", 3014 /* BRDC_FMAC_INTERRUPT_REGISTER_2_TEST */ "", 3015 /* BRDC_FMAC_INTERRUPT_REGISTER_3_TEST */ "", 3016 /* BRDC_FMAC_INTERRUPT_REGISTER_4_TEST */ "", 3017 /* BRDC_FMAC_INTERRUPT_REGISTER_5_TEST */ "", 3018 /* BRDC_FMAC_INTERRUPT_REGISTER_6_TEST */ "", 3019 /* BRDC_FMAC_INTERRUPT_REGISTER_7_TEST */ "", 3020 /* BRDC_FMAC_INTERRUPT_REGISTER_8_TEST */ "", 3021 /* BRDC_FMAC_INTERRUPT_REGISTER_9_TEST */ "", 3022 /* BRDC_FMAC_INTERRUPT_REGISTER_TEST */ "", 3023 /* BRDC_FMAC_KPCS_CONFIGURATION */ "", 3024 /* BRDC_FMAC_KPCS_RX_STATUS */ "", 3025 /* BRDC_FMAC_KPCS_TEST_RX_CONFIGURATION */ "", 3026 /* BRDC_FMAC_KPCS_TEST_RX_STATUS */ "", 3027 /* BRDC_FMAC_KPCS_TEST_TX_CONFIGURATION */ "", 3028 /* BRDC_FMAC_LEAKY_BUCKET */ "", 3029 /* BRDC_FMAC_LEAKY_BUCKET_CONTROL_REGISTER */ "", 3030 /* BRDC_FMAC_LFEC_CONFIGURATION */ "", 3031 /* BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER */ "", 3032 /* BRDC_FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER */ "", 3033 /* BRDC_FMAC_LINK_TOPO_MODE_REG_0 */ "", 3034 /* BRDC_FMAC_LINK_TOPO_MODE_REG_2 */ "", 3035 /* BRDC_FMAC_LOOPBACK_ENABLE_REGISTER */ "", 3036 /* BRDC_FMAC_MACT_PM_CREDIT_FILTER */ "", 3037 /* BRDC_FMAC_PARITY_ERR_CNT */ "", 3038 /* BRDC_FMAC_PAR_ERR_INITIATE */ "", 3039 /* BRDC_FMAC_PAR_ERR_MEM_MASK */ "", 3040 /* BRDC_FMAC_RECEIVE_RESET_REGISTER */ "", 3041 /* BRDC_FMAC_REG_0050 */ "", 3042 /* BRDC_FMAC_REG_0051 */ "", 3043 /* BRDC_FMAC_REG_0052 */ "", 3044 /* BRDC_FMAC_REG_0053 */ "", 3045 /* BRDC_FMAC_REG_0054 */ "", 3046 /* BRDC_FMAC_REG_0058 */ "", 3047 /* BRDC_FMAC_REG_0068 */ "", 3048 /* BRDC_FMAC_REG_0096 */ "", 3049 /* BRDC_FMAC_REG_0098 */ "", 3050 /* BRDC_FMAC_REG_0099 */ "", 3051 /* BRDC_FMAC_REG_0102 */ "", 3052 /* BRDC_FMAC_REG_0114 */ "", 3053 /* BRDC_FMAC_REG_0116 */ "", 3054 /* BRDC_FMAC_REG_0118 */ "", 3055 /* BRDC_FMAC_REG_0119 */ "", 3056 /* BRDC_FMAC_REG_0121 */ "", 3057 /* BRDC_FMAC_REG_0122 */ "", 3058 /* BRDC_FMAC_REG_0123 */ "", 3059 /* BRDC_FMAC_REG_0139 */ "", 3060 /* BRDC_FMAC_REG_0140 */ "", 3061 /* BRDC_FMAC_REG_005A */ "", 3062 /* BRDC_FMAC_REG_005B */ "", 3063 /* BRDC_FMAC_REG_005C */ "", 3064 /* BRDC_FMAC_REG_00A0 */ "", 3065 /* BRDC_FMAC_REG_00C2 */ "", 3066 /* BRDC_FMAC_REG_00C3 */ "", 3067 /* BRDC_FMAC_REG_00F4 */ "", 3068 /* BRDC_FMAC_REG_011A */ "", 3069 /* BRDC_FMAC_REG_011C */ "", 3070 /* BRDC_FMAC_REG_011D */ "", 3071 /* BRDC_FMAC_REG_012A */ "", 3072 /* BRDC_FMAC_REG_012C */ "", 3073 /* BRDC_FMAC_REG_012D */ "", 3074 /* BRDC_FMAC_REG_01A8 */ "", 3075 /* BRDC_FMAC_REG_01AC */ "", 3076 /* BRDC_FMAC_REG_01FA */ "", 3077 /* BRDC_FMAC_RESERVED_MIRROR_ADDR */ "", 3078 /* BRDC_FMAC_RESERVED_MTCD */ "", 3079 /* BRDC_FMAC_RESERVED_MTCP */ "", 3080 /* BRDC_FMAC_RESERVED_SPARE_0 */ "", 3081 /* BRDC_FMAC_RESERVED_SPARE_1 */ "", 3082 /* BRDC_FMAC_RESERVED_SPARE_2 */ "", 3083 /* BRDC_FMAC_RESERVED_SPARE_3 */ "", 3084 /* BRDC_FMAC_RETIMER */ "", 3085 /* BRDC_FMAC_RSF_CONFIGURATION */ "", 3086 /* BRDC_FMAC_RSF_STATUS */ "", 3087 /* BRDC_FMAC_RX_LANE_SWAP_0 */ "", 3088 /* BRDC_FMAC_RX_LANE_SWAP_1 */ "", 3089 /* BRDC_FMAC_RX_LANE_SWAP_2 */ "", 3090 /* BRDC_FMAC_RX_LANE_SWAP_3 */ "", 3091 /* BRDC_FMAC_RX_RRR_CRL_OVF_DROP_CNT */ "", 3092 /* BRDC_FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT */ "", 3093 /* BRDC_FMAC_SBUS_BROADCAST_ID */ "", 3094 /* BRDC_FMAC_SBUS_LAST_IN_CHAIN */ "", 3095 /* BRDC_FMAC_SPARE_REGISTER_2 */ "", 3096 /* BRDC_FMAC_SPECIAL_CLOCK_CONTROLS */ "", 3097 /* BRDC_FMAC_TEST_CONFIGURATION */ "", 3098 /* BRDC_FMAC_TEST_STATUS */ "", 3099 /* BRDC_FMAC_TX_CELL_LIMIT */ "", 3100 /* BRDC_FMAC_TX_LANE_SWAP_0 */ "", 3101 /* BRDC_FMAC_TX_LANE_SWAP_1 */ "", 3102 /* BRDC_FMAC_TX_LANE_SWAP_2 */ "", 3103 /* BRDC_FMAC_TX_LANE_SWAP_3 */ "", 3104 /* BRDC_FSRD_AUTO_DOC_NAME_2 */ "", 3105 /* BRDC_FSRD_ECC_1B_ERR_CNT */ "", 3106 /* BRDC_FSRD_ECC_2B_ERR_CNT */ "", 3107 /* BRDC_FSRD_ECC_ERR_1B_INITIATE */ "", 3108 /* BRDC_FSRD_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 3109 /* BRDC_FSRD_ECC_ERR_2B_INITIATE */ "", 3110 /* BRDC_FSRD_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 3111 /* BRDC_FSRD_ECC_INTERRUPT_REGISTER */ "", 3112 /* BRDC_FSRD_ECC_INTERRUPT_REGISTER_MASK */ "", 3113 /* BRDC_FSRD_ECC_INTERRUPT_REGISTER_TEST */ "", 3114 /* BRDC_FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 3115 /* BRDC_FSRD_ERROR_INITIATION_DATA */ "", 3116 /* BRDC_FSRD_FSRD_REGISTER_0 */ "", 3117 /* BRDC_FSRD_GENERAL_CONFIGURTION */ "", 3118 /* BRDC_FSRD_GLOBAL_MEM_OPTIONS */ "", 3119 /* BRDC_FSRD_GTIMER_CONFIGURATION */ "", 3120 /* BRDC_FSRD_GTIMER_CYCLE */ "", 3121 /* BRDC_FSRD_GTIMER_TRIGGER */ "", 3122 /* BRDC_FSRD_INDIRECT_COMMAND */ "", 3123 /* BRDC_FSRD_INDIRECT_COMMAND_ADDRESS */ "", 3124 /* BRDC_FSRD_INDIRECT_COMMAND_DATA_INCREMENT */ "", 3125 /* BRDC_FSRD_INDIRECT_COMMAND_RD_DATA */ "", 3126 /* BRDC_FSRD_INDIRECT_COMMAND_WIDE_MEM */ "", 3127 /* BRDC_FSRD_INDIRECT_COMMAND_WR_DATA */ "", 3128 /* BRDC_FSRD_INDIRECT_FORCE_BUBBLE */ "", 3129 /* BRDC_FSRD_INTERRUPT_MASK_REGISTER */ "", 3130 /* BRDC_FSRD_INTERRUPT_REGISTER */ "", 3131 /* BRDC_FSRD_INTERRUPT_REGISTER_TEST */ "", 3132 /* BRDC_FSRD_OUTPUT_DROP_COUNTER */ "", 3133 /* BRDC_FSRD_PCMI_0 */ "", 3134 /* BRDC_FSRD_PCMI_1 */ "", 3135 /* BRDC_FSRD_PCMI_2 */ "", 3136 /* BRDC_FSRD_PCMI_3 */ "", 3137 /* BRDC_FSRD_PCMI_4 */ "", 3138 /* BRDC_FSRD_PCMI_0_S */ "", 3139 /* BRDC_FSRD_PCMI_0_T */ "", 3140 /* BRDC_FSRD_PCMI_1_S */ "", 3141 /* BRDC_FSRD_PCMI_1_T */ "", 3142 /* BRDC_FSRD_PCMI_2_S */ "", 3143 /* BRDC_FSRD_PCMI_2_T */ "", 3144 /* BRDC_FSRD_PCMI_3_S */ "", 3145 /* BRDC_FSRD_PCMI_3_T */ "", 3146 /* BRDC_FSRD_PCMI_4_S */ "", 3147 /* BRDC_FSRD_PCMI_4_T */ "", 3148 /* BRDC_FSRD_QUAD_INTERRUPT_MASK_REGISTER */ "", 3149 /* BRDC_FSRD_QUAD_INTERRUPT_REGISTER */ "", 3150 /* BRDC_FSRD_QUAD_INTERRUPT_REGISTER_TEST */ "", 3151 /* BRDC_FSRD_REG_0041 */ "", 3152 /* BRDC_FSRD_REG_0050 */ "", 3153 /* BRDC_FSRD_REG_0051 */ "", 3154 /* BRDC_FSRD_REG_0052 */ "", 3155 /* BRDC_FSRD_REG_0053 */ "", 3156 /* BRDC_FSRD_REG_0054 */ "", 3157 /* BRDC_FSRD_REG_0058 */ "", 3158 /* BRDC_FSRD_REG_0084 */ "", 3159 /* BRDC_FSRD_REG_0087 */ "", 3160 /* BRDC_FSRD_REG_0090 */ "", 3161 /* BRDC_FSRD_REG_0091 */ "", 3162 /* BRDC_FSRD_REG_0092 */ "", 3163 /* BRDC_FSRD_REG_0094 */ "", 3164 /* BRDC_FSRD_REG_0170 */ "", 3165 /* BRDC_FSRD_REG_009A */ "", 3166 /* BRDC_FSRD_REG_009C */ "", 3167 /* BRDC_FSRD_REG_00B0 */ "", 3168 /* BRDC_FSRD_REG_00B1 */ "", 3169 /* BRDC_FSRD_REG_00B2 */ "", 3170 /* BRDC_FSRD_REG_00B3 */ "", 3171 /* BRDC_FSRD_REG_00B4 */ "", 3172 /* BRDC_FSRD_REG_00B5 */ "", 3173 /* BRDC_FSRD_REG_00B6 */ "", 3174 /* BRDC_FSRD_REG_00B7 */ "", 3175 /* BRDC_FSRD_REG_00C2 */ "", 3176 /* BRDC_FSRD_REG_017B */ "", 3177 /* BRDC_FSRD_REG_01E9 */ "", 3178 /* BRDC_FSRD_REG_01EA */ "", 3179 /* BRDC_FSRD_REG_01EB */ "", 3180 /* BRDC_FSRD_REG_01EC */ "", 3181 /* BRDC_FSRD_REG_01ED */ "", 3182 /* BRDC_FSRD_REG_01EE */ "", 3183 /* BRDC_FSRD_REG_01EF */ "", 3184 /* BRDC_FSRD_REG_01F0 */ "", 3185 /* BRDC_FSRD_REG_01F1 */ "", 3186 /* BRDC_FSRD_REG_01F2 */ "", 3187 /* BRDC_FSRD_REG_01F3 */ "", 3188 /* BRDC_FSRD_REG_1E8 */ "", 3189 /* BRDC_FSRD_RESERVED_MIRROR_ADDR */ "", 3190 /* BRDC_FSRD_RESERVED_MTCD */ "", 3191 /* BRDC_FSRD_RESERVED_MTCP */ "", 3192 /* BRDC_FSRD_RESERVED_PCMI_0 */ "", 3193 /* BRDC_FSRD_RESERVED_PCMI_1 */ "", 3194 /* BRDC_FSRD_RESERVED_PCMI_2 */ "", 3195 /* BRDC_FSRD_RESERVED_PCMI_4 */ "", 3196 /* BRDC_FSRD_RESERVED_PCMI_0_S */ "", 3197 /* BRDC_FSRD_RESERVED_PCMI_0_T */ "", 3198 /* BRDC_FSRD_RESERVED_PCMI_1_S */ "", 3199 /* BRDC_FSRD_RESERVED_PCMI_1_T */ "", 3200 /* BRDC_FSRD_RESERVED_PCMI_2_S */ "", 3201 /* BRDC_FSRD_RESERVED_PCMI_2_T */ "", 3202 /* BRDC_FSRD_RESERVED_PCMI_4_S */ "", 3203 /* BRDC_FSRD_RESERVED_PCMI_4_T */ "", 3204 /* BRDC_FSRD_RESERVED_SPARE_0 */ "", 3205 /* BRDC_FSRD_RESERVED_SPARE_1 */ "", 3206 /* BRDC_FSRD_RESERVED_SPARE_2 */ "", 3207 /* BRDC_FSRD_RESERVED_SPARE_3 */ "", 3208 /* BRDC_FSRD_RES_CAL_CONFIG */ "", 3209 /* BRDC_FSRD_RES_CAL_CPU_OVERRIDE_REGISTER */ "", 3210 /* BRDC_FSRD_RES_CAL_STATUS */ "", 3211 /* BRDC_FSRD_RES_CAL_STICKY_CONFIG */ "", 3212 /* BRDC_FSRD_SBUS_BROADCAST_ID */ "", 3213 /* BRDC_FSRD_SBUS_LAST_IN_CHAIN */ "", 3214 /* BRDC_FSRD_SPARE_REGISTER_3 */ "", 3215 /* BRDC_FSRD_SPECIAL_CLOCK_CONTROLS */ "", 3216 /* BRDC_FSRD_SRD_CTRL */ "", 3217 /* BRDC_FSRD_SRD_LN_MODE */ "", 3218 /* BRDC_FSRD_SRD_LN_OSR */ "", 3219 /* BRDC_FSRD_SRD_LN_PAM */ "", 3220 /* BRDC_FSRD_SRD_PLL_0_CTRL */ "", 3221 /* BRDC_FSRD_SRD_PLL_1_CTRL */ "", 3222 /* BRDC_FSRD_SRD_QUAD_CTRL */ "", 3223 /* BRDC_FSRD_SRD_QUAD_LN_FORCE_SPEED_STRAPS */ "", 3224 /* BRDC_FSRD_SRD_QUAD_LN_STRAPS */ "", 3225 /* BRDC_FSRD_SRD_QUAD_STATUS */ "", 3226 /* BRDC_FSRD_SRD_STATUS */ "", 3227 /* BRDC_FSRD_SYNC_E_SELECT */ "", 3228 /* BRDC_FSRD_TX_ILKN_CREDIT */ "", 3229 /* BRDC_FSRD_WC_UC_MEM_ACCESS */ "", 3230 /* BRDC_FSRD_WC_UC_MEM_MASK_BITMAP */ "", 3231 /* BRDC_HBC_BIST_ADDR_CONFIG */ "", 3232 /* BRDC_HBC_BIST_BANK_REORDER */ "", 3233 /* BRDC_HBC_BIST_COMMAND_CONFIG */ "", 3234 /* BRDC_HBC_BIST_CONTROL */ "", 3235 /* BRDC_HBC_BIST_DATA_CONFIG */ "", 3236 /* BRDC_HBC_BIST_DATA_MISR_MAP */ "", 3237 /* BRDC_HBC_BIST_DATA_PRESET */ "", 3238 /* BRDC_HBC_BIST_DWORD_MISR_STATE */ "", 3239 /* BRDC_HBC_BIST_ERR_COUNTERS */ "", 3240 /* BRDC_HBC_BIST_PATTERN */ "", 3241 /* BRDC_HBC_BIST_STATUS */ "", 3242 /* BRDC_HBC_BLOCKED_BY_COHERENCY_CNT */ "", 3243 /* BRDC_HBC_DATA_SOURCE_CONFIG */ "", 3244 /* BRDC_HBC_DRAM_CHANNEL_BLOCKED_CONFIG */ "", 3245 /* BRDC_HBC_DRAM_CHANNEL_BLOCKED_STATUS */ "", 3246 /* BRDC_HBC_DSI_ASYNC_FIFO_CONFIG */ "", 3247 /* BRDC_HBC_DSI_INTERRUPT_MASK_REGISTER */ "", 3248 /* BRDC_HBC_DSI_INTERRUPT_REGISTER */ "", 3249 /* BRDC_HBC_DSI_INTERRUPT_REGISTER_TEST */ "", 3250 /* BRDC_HBC_ECC_1B_ERR_CNT */ "", 3251 /* BRDC_HBC_ECC_2B_ERR_CNT */ "", 3252 /* BRDC_HBC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 3253 /* BRDC_HBC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 3254 /* BRDC_HBC_ECC_INTERRUPT_REGISTER */ "", 3255 /* BRDC_HBC_ECC_INTERRUPT_REGISTER_MASK */ "", 3256 /* BRDC_HBC_ECC_INTERRUPT_REGISTER_TEST */ "", 3257 /* BRDC_HBC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 3258 /* BRDC_HBC_ERROR_INITIATION_DATA */ "", 3259 /* BRDC_HBC_GTIMER_CONFIGURATION */ "", 3260 /* BRDC_HBC_GTIMER_CYCLE */ "", 3261 /* BRDC_HBC_HBM_COLUMN_ACCESS_TIMINGS */ "", 3262 /* BRDC_HBC_HBM_COMMAND_COUNTERS */ "", 3263 /* BRDC_HBC_HBM_CONFIG */ "", 3264 /* BRDC_HBC_HBM_CPU_CONTROL */ "", 3265 /* BRDC_HBC_HBM_ECC_ERR_INFO */ "", 3266 /* BRDC_HBC_HBM_ERR_COUNTERS */ "", 3267 /* BRDC_HBC_HBM_GENERAL_TIMINGS */ "", 3268 /* BRDC_HBC_HBM_MODE_REGISTERS */ "", 3269 /* BRDC_HBC_HBM_MODE_REGISTER_MANAGER_CONFIG */ "", 3270 /* BRDC_HBC_HBM_PHY_CH_REGISTER_ACCESS_ERROR */ "", 3271 /* BRDC_HBC_HBM_REFRESH_INTERVALS */ "", 3272 /* BRDC_HBC_HBM_REFRESH_TIMINGS */ "", 3273 /* BRDC_HBC_HBM_ROW_ACCESS_TIMINGS */ "", 3274 /* BRDC_HBC_INDIRECT_COMMAND */ "", 3275 /* BRDC_HBC_INDIRECT_COMMAND_ADDRESS */ "", 3276 /* BRDC_HBC_INDIRECT_COMMAND_RD_DATA */ "", 3277 /* BRDC_HBC_INDIRECT_COMMAND_WR_DATA */ "", 3278 /* BRDC_HBC_INDIRECT_FORCE_BUBBLE */ "", 3279 /* BRDC_HBC_INTERRUPT_MASK_REGISTER */ "", 3280 /* BRDC_HBC_INTERRUPT_REGISTER */ "", 3281 /* BRDC_HBC_INTERRUPT_REGISTER_TEST */ "", 3282 /* BRDC_HBC_LAST_RETURNED_DATA */ "", 3283 /* BRDC_HBC_PARITY_ERR_CNT */ "", 3284 /* BRDC_HBC_PAR_ERR_MEM_MASK */ "", 3285 /* BRDC_HBC_PIPELINES_BANK_REMAPPING */ "", 3286 /* BRDC_HBC_PIPELINES_COMMAND_PIN_MUX */ "", 3287 /* BRDC_HBC_PIPELINES_CONFIG */ "", 3288 /* BRDC_HBC_PIPELINES_DEBUG */ "", 3289 /* BRDC_HBC_PIPELINES_INTERRUPT_MASK_REGISTER */ "", 3290 /* BRDC_HBC_PIPELINES_INTERRUPT_REGISTER */ "", 3291 /* BRDC_HBC_PIPELINES_INTERRUPT_REGISTER_TEST */ "", 3292 /* BRDC_HBC_PIPELINES_PHY_RCMD */ "", 3293 /* BRDC_HBC_RDR_DS_TRANS_CNT */ "", 3294 /* BRDC_HBC_RDR_INTERRUPT_MASK_REGISTER */ "", 3295 /* BRDC_HBC_RDR_INTERRUPT_REGISTER */ "", 3296 /* BRDC_HBC_RDR_INTERRUPT_REGISTER_TEST */ "", 3297 /* BRDC_HBC_RDR_RD_INFO_WMK */ "", 3298 /* BRDC_HBC_RDR_TOT_TRANS_CNT */ "", 3299 /* BRDC_HBC_READ_DATA_REORDER_STATUS */ "", 3300 /* BRDC_HBC_REG_0041 */ "", 3301 /* BRDC_HBC_REG_00A4 */ "", 3302 /* BRDC_HBC_REG_00A6 */ "", 3303 /* BRDC_HBC_REG_00AA */ "", 3304 /* BRDC_HBC_REG_00C2 */ "", 3305 /* BRDC_HBC_RESERVED_MIRROR_ADDR */ "", 3306 /* BRDC_HBC_RESERVED_MTCD */ "", 3307 /* BRDC_HBC_RESERVED_MTCP */ "", 3308 /* BRDC_HBC_RESERVED_SPARE_0 */ "", 3309 /* BRDC_HBC_RESERVED_SPARE_1 */ "", 3310 /* BRDC_HBC_RESERVED_SPARE_2 */ "", 3311 /* BRDC_HBC_RESERVED_SPARE_3 */ "", 3312 /* BRDC_HBC_RPBQ_CONFIG */ "", 3313 /* BRDC_HBC_RPBQ_STATUS */ "", 3314 /* BRDC_HBC_SBUS_BROADCAST_ID */ "", 3315 /* BRDC_HBC_SBUS_LAST_IN_CHAIN */ "", 3316 /* BRDC_HBC_SPECIAL_CLOCK_CONTROLS */ "", 3317 /* BRDC_HBC_TSM_CONFIG */ "", 3318 /* BRDC_HBC_TSM_DEBUG */ "", 3319 /* BRDC_HBC_TSM_READ_WRITE_SWITCH_CONFIG */ "", 3320 /* BRDC_HBC_WDB_STATUS */ "", 3321 /* BRDC_HBC_WPBQ_CONFIG */ "", 3322 /* BRDC_HBC_WPBQ_STATUS */ "", 3323 /* BRDC_LCM_ADMIT_DENY_DFL_FULL_CNT */ "", 3324 /* BRDC_LCM_ADMIT_DROP_CNT */ "", 3325 /* BRDC_LCM_ADMIT_DROP_CPU_CNT */ "", 3326 /* BRDC_LCM_ADMIT_DROP_REASONS_DCH */ "", 3327 /* BRDC_LCM_AUTO_DOC_NAME_0 */ "", 3328 /* BRDC_LCM_AUTO_DOC_NAME_1 */ "", 3329 /* BRDC_LCM_AUTO_DOC_NAME_2 */ "", 3330 /* BRDC_LCM_AUTO_DOC_NAME_3 */ "", 3331 /* BRDC_LCM_AUTO_DOC_NAME_4 */ "", 3332 /* BRDC_LCM_AUTO_DOC_NAME_5 */ "", 3333 /* BRDC_LCM_AUTO_DOC_NAME_6 */ "", 3334 /* BRDC_LCM_AUTO_DOC_NAME_7 */ "", 3335 /* BRDC_LCM_DCML_SEPARATION_REGISTER */ "", 3336 /* BRDC_LCM_DFL_BANKS_MC_DROP_TH */ "", 3337 /* BRDC_LCM_DFL_BANKS_TH */ "", 3338 /* BRDC_LCM_DFL_FC_TH_METHOD_1 */ "", 3339 /* BRDC_LCM_DFL_FC_TH_METHOD_2 */ "", 3340 /* BRDC_LCM_DFL_GCI_COPIES_THRESHOLDS */ "", 3341 /* BRDC_LCM_DFL_GCI_TH_METHOD_1 */ "", 3342 /* BRDC_LCM_DFL_GCI_TH_METHOD_2 */ "", 3343 /* BRDC_LCM_DFL_MC_COPIES_ADMIT_THRESHOLDS */ "", 3344 /* BRDC_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_1 */ "", 3345 /* BRDC_LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_2 */ "", 3346 /* BRDC_LCM_DFL_PIPE_COPIES_FRAG_CNT_INFO_P */ "", 3347 /* BRDC_LCM_DFL_PIPE_MC_FRAG_CNT_INFO_P */ "", 3348 /* BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_DIFF_P */ "", 3349 /* BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_1_P */ "", 3350 /* BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_2_P */ "", 3351 /* BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_REF */ "", 3352 /* BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_1_P */ "", 3353 /* BRDC_LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_2_P */ "", 3354 /* BRDC_LCM_DFL_RCI_TH_METHOD_1 */ "", 3355 /* BRDC_LCM_DFL_RCI_TH_METHOD_2 */ "", 3356 /* BRDC_LCM_DISABLE_MAC */ "", 3357 /* BRDC_LCM_DTL_ADMIT_LR_TH_PROFILE */ "", 3358 /* BRDC_LCM_DTL_ADMIT_NLR_TH_PROFILE */ "", 3359 /* BRDC_LCM_DTL_CPU_CELL_CNT */ "", 3360 /* BRDC_LCM_DTL_CPU_TAGS_TH */ "", 3361 /* BRDC_LCM_DTL_CPU_TAG_FIFO_STATUS */ "", 3362 /* BRDC_LCM_DTL_DROPPED_IP_PR_P_0_CNT */ "", 3363 /* BRDC_LCM_DTL_DROPPED_IP_PR_P_1_CNT */ "", 3364 /* BRDC_LCM_DTL_DROPPED_IP_PR_P_2_CNT */ "", 3365 /* BRDC_LCM_DTL_DROPPED_SRC_P_CNT */ "", 3366 /* BRDC_LCM_DTL_FC_TH_LR_PROFILE */ "", 3367 /* BRDC_LCM_DTL_FC_TH_NLR_PROFILE */ "", 3368 /* BRDC_LCM_DTL_FIFOS_DEPTH_TYPE */ "", 3369 /* BRDC_LCM_DTL_FRAG_MAX_LEVEL_LR_P */ "", 3370 /* BRDC_LCM_DTL_FRAG_MAX_LEVEL_NLR_P */ "", 3371 /* BRDC_LCM_DTL_GCI_TH_P_0_LR_PROFILE */ "", 3372 /* BRDC_LCM_DTL_GCI_TH_P_0_NLR_PROFILE */ "", 3373 /* BRDC_LCM_DTL_GCI_TH_P_1_LR_PROFILE */ "", 3374 /* BRDC_LCM_DTL_GCI_TH_P_1_NLR_PROFILE */ "", 3375 /* BRDC_LCM_DTL_GCI_TH_P_2_LR_PROFILE */ "", 3376 /* BRDC_LCM_DTL_GCI_TH_P_2_NLR_PROFILE */ "", 3377 /* BRDC_LCM_DTL_LCLRT_CPU_CELL_CNT */ "", 3378 /* BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_0_CNT */ "", 3379 /* BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_1_CNT */ "", 3380 /* BRDC_LCM_DTL_LCLRT_DROPPED_IP_PR_P_2_CNT */ "", 3381 /* BRDC_LCM_DTL_LCLRT_DROPPED_SRC_P_CNT */ "", 3382 /* BRDC_LCM_DTL_LCLRT_LINK_TYPE */ "", 3383 /* BRDC_LCM_DTL_LCLRT_TOTAL_IN_CELL_P_CNT */ "", 3384 /* BRDC_LCM_DTL_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 3385 /* BRDC_LCM_DTL_LINK_TYPE */ "", 3386 /* BRDC_LCM_DTL_PIPES_WEIGHTS_REGISTER */ "", 3387 /* BRDC_LCM_DTL_RCI_TH_P_0_LR_PROFILE */ "", 3388 /* BRDC_LCM_DTL_RCI_TH_P_0_NLR_PROFILE */ "", 3389 /* BRDC_LCM_DTL_RCI_TH_P_1_LR_PROFILE */ "", 3390 /* BRDC_LCM_DTL_RCI_TH_P_1_NLR_PROFILE */ "", 3391 /* BRDC_LCM_DTL_RCI_TH_P_2_LR_PROFILE */ "", 3392 /* BRDC_LCM_DTL_RCI_TH_P_2_NLR_PROFILE */ "", 3393 /* BRDC_LCM_DTL_TH_PROFILES_MAPPING */ "", 3394 /* BRDC_LCM_DTL_TOTAL_IN_CELL_P_CNT */ "", 3395 /* BRDC_LCM_DTL_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 3396 /* BRDC_LCM_DTMLOP_PIPES_WEIGHTS_COUNTER_PN */ "", 3397 /* BRDC_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_2 */ "", 3398 /* BRDC_LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_3 */ "", 3399 /* BRDC_LCM_DTML_ENABLERS */ "", 3400 /* BRDC_LCM_DTM_ADMIT_CYCLE_TH_PROFILE */ "", 3401 /* BRDC_LCM_DTM_ADMIT_JOB_FIFO_CYCLE_TH */ "", 3402 /* BRDC_LCM_DTM_ADMIT_TH_PROFILE */ "", 3403 /* BRDC_LCM_DTM_CNT_INFO_1 */ "", 3404 /* BRDC_LCM_DTM_CNT_INFO_2 */ "", 3405 /* BRDC_LCM_DTM_CNT_INFO_3 */ "", 3406 /* BRDC_LCM_DTM_CNT_INFO_SELECT */ "", 3407 /* BRDC_LCM_DTM_COPIES_RTP_FC_THRESHOLDS */ "", 3408 /* BRDC_LCM_DTM_CPU_TAGS_STATUS */ "", 3409 /* BRDC_LCM_DTM_CPU_TAGS_TH */ "", 3410 /* BRDC_LCM_DTM_DTL_FLOW_CONTROL_CNT_P */ "", 3411 /* BRDC_LCM_DTM_DYN_PIPES_WEIGHTS_REGISTER */ "", 3412 /* BRDC_LCM_DTM_FC_TH_PROFILE */ "", 3413 /* BRDC_LCM_DTM_FIFOS_DEPTH_TYPE */ "", 3414 /* BRDC_LCM_DTM_FIFO_TYPE_BMP */ "", 3415 /* BRDC_LCM_DTM_FRAG_CNT_INFO_P_0_DCH */ "", 3416 /* BRDC_LCM_DTM_FRAG_CNT_INFO_P_1_DCH */ "", 3417 /* BRDC_LCM_DTM_FRAG_CNT_INFO_P_2_DCH */ "", 3418 /* BRDC_LCM_DTM_GCI_TH_PROFILE */ "", 3419 /* BRDC_LCM_DTM_LATENCY_CFG */ "", 3420 /* BRDC_LCM_DTM_LCLRT_DTL_FLOW_CONTROL_CNT_P */ "", 3421 /* BRDC_LCM_DTM_LCLRT_PIPES_WEIGHTS_COUNTER_PN */ "", 3422 /* BRDC_LCM_DTM_LCLRT_TOTAL_OUT_CELL_CNT_P */ "", 3423 /* BRDC_LCM_DTM_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 3424 /* BRDC_LCM_DTM_MASK_FC_AGING_PERIOD */ "", 3425 /* BRDC_LCM_DTM_PIPES_WEIGHTS_COUNTER_PN */ "", 3426 /* BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTER */ "", 3427 /* BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTER_2 */ "", 3428 /* BRDC_LCM_DTM_PIPES_WEIGHTS_REGISTER_3 */ "", 3429 /* BRDC_LCM_DTM_RCI_TH_PROFILE */ "", 3430 /* BRDC_LCM_DTM_TAG_CNT_INFO_P_0_DCH */ "", 3431 /* BRDC_LCM_DTM_TAG_CNT_INFO_P_1_DCH */ "", 3432 /* BRDC_LCM_DTM_TAG_CNT_INFO_P_2_DCH */ "", 3433 /* BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_0 */ "", 3434 /* BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_1 */ "", 3435 /* BRDC_LCM_DTM_TOTAL_CELL_CNT_DCH_P_2 */ "", 3436 /* BRDC_LCM_DTM_TOTAL_OUT_CELL_CNT_P */ "", 3437 /* BRDC_LCM_DTM_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 3438 /* BRDC_LCM_DYN_PIPES_WEIGHTS_REGISTER */ "", 3439 /* BRDC_LCM_ECC_1B_ERR_CNT */ "", 3440 /* BRDC_LCM_ECC_2B_ERR_CNT */ "", 3441 /* BRDC_LCM_ECC_ERR_1B_INITIATE */ "", 3442 /* BRDC_LCM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 3443 /* BRDC_LCM_ECC_ERR_2B_INITIATE */ "", 3444 /* BRDC_LCM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 3445 /* BRDC_LCM_ECC_INTERRUPT_REGISTER */ "", 3446 /* BRDC_LCM_ECC_INTERRUPT_REGISTER_MASK */ "", 3447 /* BRDC_LCM_ECC_INTERRUPT_REGISTER_TEST */ "", 3448 /* BRDC_LCM_ERROR_INITIATION_DATA */ "", 3449 /* BRDC_LCM_FAP_GLOBAL_GENERAL_CFG_1 */ "", 3450 /* BRDC_LCM_FE_GLOBAL_DCH_CAPTURE_CELLS_DCML */ "", 3451 /* BRDC_LCM_FE_GLOBAL_GENERAL_CFG_1 */ "", 3452 /* BRDC_LCM_GLOBAL_MEM_OPTIONS */ "", 3453 /* BRDC_LCM_GTIMER_CONFIGURATION */ "", 3454 /* BRDC_LCM_GTIMER_CYCLE */ "", 3455 /* BRDC_LCM_INTERRUPT_MASK_REGISTER */ "", 3456 /* BRDC_LCM_INTERRUPT_REGISTER */ "", 3457 /* BRDC_LCM_INTERRUPT_REGISTER_TEST */ "", 3458 /* BRDC_LCM_LCLRT_FIFOS_DEPTH_TYPE */ "", 3459 /* BRDC_LCM_LCM_ADMIT_ENABLERS */ "", 3460 /* BRDC_LCM_LCM_FC_ENABLERS */ "", 3461 /* BRDC_LCM_LCM_GCI_ENABLERS */ "", 3462 /* BRDC_LCM_LCM_INTERRUPT_REGISTER */ "", 3463 /* BRDC_LCM_LCM_INTERRUPT_REGISTER_MASK */ "", 3464 /* BRDC_LCM_LCM_INTERRUPT_REGISTER_TEST */ "", 3465 /* BRDC_LCM_LCM_RCI_ENABLERS */ "", 3466 /* BRDC_LCM_LCM_REGISTER_0 */ "", 3467 /* BRDC_LCM_LCM_REGISTER_1 */ "", 3468 /* BRDC_LCM_LCM_REGISTER_2 */ "", 3469 /* BRDC_LCM_LCM_REGISTER_3 */ "", 3470 /* BRDC_LCM_LCM_REGISTER_5 */ "", 3471 /* BRDC_LCM_LCM_REGISTER_6 */ "", 3472 /* BRDC_LCM_LCM_REGISTER_7 */ "", 3473 /* BRDC_LCM_LCM_REGISTER_8 */ "", 3474 /* BRDC_LCM_LCM_REGISTER_9 */ "", 3475 /* BRDC_LCM_LINK_CNT_INFO_1 */ "", 3476 /* BRDC_LCM_LINK_CNT_INFO_2 */ "", 3477 /* BRDC_LCM_LINK_CNT_INFO_3 */ "", 3478 /* BRDC_LCM_LINK_CNT_INFO_4 */ "", 3479 /* BRDC_LCM_LINK_CNT_INFO_5 */ "", 3480 /* BRDC_LCM_LINK_CNT_INFO_6 */ "", 3481 /* BRDC_LCM_LINK_CNT_INFO_7 */ "", 3482 /* BRDC_LCM_LINK_CNT_INFO_SELECT */ "", 3483 /* BRDC_LCM_LINK_FC_TH_PROFILE */ "", 3484 /* BRDC_LCM_LINK_LEVEL_FLOW_CONTROL_P */ "", 3485 /* BRDC_LCM_LINK_LOAD_COUNT_CFG */ "", 3486 /* BRDC_LCM_LINK_LOAD_HYST_TH */ "", 3487 /* BRDC_LCM_LINK_LOAD_HYST_TYPE */ "", 3488 /* BRDC_LCM_LINK_RCI_GRNT_TH_PROFILE */ "", 3489 /* BRDC_LCM_LINK_RCI_TOTAL_TH_PROFILE */ "", 3490 /* BRDC_LCM_LINK_TH_PROFILE */ "", 3491 /* BRDC_LCM_LINK_TH_PROFILES_MAPPING */ "", 3492 /* BRDC_LCM_LLFC_RATE_CNT_P */ "", 3493 /* BRDC_LCM_PIPES_MAPPING_EN */ "", 3494 /* BRDC_LCM_PIPES_SEPARATION_REGISTER */ "", 3495 /* BRDC_LCM_RCI_TABLE_PIPE */ "", 3496 /* BRDC_LCM_READ_MECH_DEBUG_1 */ "", 3497 /* BRDC_LCM_REMOTE_PRI_PIPE_IDX */ "", 3498 /* BRDC_LCM_REMOTE_SEC_PIPE_IDX */ "", 3499 /* BRDC_LCM_RESERVED_MIRROR_ADDR */ "", 3500 /* BRDC_LCM_RESERVED_MTCD */ "", 3501 /* BRDC_LCM_RESERVED_MTCP */ "", 3502 /* BRDC_LCM_RESERVED_SPARE_0 */ "", 3503 /* BRDC_LCM_RESERVED_SPARE_1 */ "", 3504 /* BRDC_LCM_RESERVED_SPARE_2 */ "", 3505 /* BRDC_LCM_RESERVED_SPARE_3 */ "", 3506 /* BRDC_LCM_SBUS_BROADCAST_ID */ "", 3507 /* BRDC_LCM_SBUS_LAST_IN_CHAIN */ "", 3508 /* BRDC_LCM_THREE_PIPES_BMP */ "", 3509 /* BRDC_LCM_TWO_PIPES_BMP */ "", 3510 /* BRDC_LCM_TX_CPU_CELL_OUTPUT_LINK */ "", 3511 /* BRDC_LCM_TX_CPU_CELL_TRG */ "", 3512 /* BRDC_QRH_ALLOWED_LINKS_PIPE_0_REGISTER */ "", 3513 /* BRDC_QRH_ALLOWED_LINKS_PIPE_1_REGISTER */ "", 3514 /* BRDC_QRH_ALLOWED_LINKS_PIPE_2_REGISTER */ "", 3515 /* BRDC_QRH_ALL_MUL_DROP_TH */ "", 3516 /* BRDC_QRH_AUTO_DOC_NAME_0 */ "", 3517 /* BRDC_QRH_AUTO_DOC_NAME_1 */ "", 3518 /* BRDC_QRH_CRH_INTERRUPT_MASK_REGISTER */ "", 3519 /* BRDC_QRH_CRH_INTERRUPT_REGISTER */ "", 3520 /* BRDC_QRH_CRH_INTERRUPT_REGISTER_TEST */ "", 3521 /* BRDC_QRH_DRH_DROPPED_LOW_MUL */ "", 3522 /* BRDC_QRH_DRH_FLOW_CONTROL_CNT_P */ "", 3523 /* BRDC_QRH_DRH_INPUT_QUERY_CNT_P */ "", 3524 /* BRDC_QRH_DRH_INTERRUPT_MASK_REGISTER */ "", 3525 /* BRDC_QRH_DRH_INTERRUPT_REGISTER */ "", 3526 /* BRDC_QRH_DRH_INTERRUPT_REGISTER_TEST */ "", 3527 /* BRDC_QRH_DRH_LOAD_BALANCING_GENERAL_CONFIG */ "", 3528 /* BRDC_QRH_DRH_LOAD_BALANCING_LEVEL_CONFIG */ "", 3529 /* BRDC_QRH_DRH_LOAD_BALANCING_LEVEL_OPTIMIZATION */ "", 3530 /* BRDC_QRH_DRH_MCSFF_HIT_COUNTER */ "", 3531 /* BRDC_QRH_DRH_OUTPUT_REPLY_CNT_P */ "", 3532 /* BRDC_QRH_DRH_REP_FIFO_STAT_P */ "", 3533 /* BRDC_QRH_DRH_UNREACHABLEMULTICASTINFO */ "", 3534 /* BRDC_QRH_DRH_WFQ_CONFIGURATIONS */ "", 3535 /* BRDC_QRH_DYN_PIPES_WEIGHTS_REGISTER */ "", 3536 /* BRDC_QRH_ECC_1B_ERR_CNT */ "", 3537 /* BRDC_QRH_ECC_2B_ERR_CNT */ "", 3538 /* BRDC_QRH_ECC_ERR_1B_INITIATE */ "", 3539 /* BRDC_QRH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 3540 /* BRDC_QRH_ECC_ERR_2B_INITIATE */ "", 3541 /* BRDC_QRH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 3542 /* BRDC_QRH_ECC_INTERRUPT_REGISTER */ "", 3543 /* BRDC_QRH_ECC_INTERRUPT_REGISTER_MASK */ "", 3544 /* BRDC_QRH_ECC_INTERRUPT_REGISTER_TEST */ "", 3545 /* BRDC_QRH_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 3546 /* BRDC_QRH_ERROR_INITIATION_DATA */ "", 3547 /* BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_1 */ "", 3548 /* BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_2 */ "", 3549 /* BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_3 */ "", 3550 /* BRDC_QRH_FE_GLOBAL_FE_DEST_IDS_4 */ "", 3551 /* BRDC_QRH_FE_GLOBAL_GENERAL_CFG_1 */ "", 3552 /* BRDC_QRH_FE_GROUP_DEST_ID */ "", 3553 /* BRDC_QRH_GLOBAL_MEM_OPTIONS */ "", 3554 /* BRDC_QRH_GTIMER_CONFIGURATION */ "", 3555 /* BRDC_QRH_GTIMER_CYCLE */ "", 3556 /* BRDC_QRH_INDIRECT_COMMAND */ "", 3557 /* BRDC_QRH_INDIRECT_COMMAND_ADDRESS */ "", 3558 /* BRDC_QRH_INDIRECT_COMMAND_DATA_INCREMENT */ "", 3559 /* BRDC_QRH_INDIRECT_COMMAND_RD_DATA */ "", 3560 /* BRDC_QRH_INDIRECT_COMMAND_WIDE_MEM */ "", 3561 /* BRDC_QRH_INDIRECT_COMMAND_WR_DATA */ "", 3562 /* BRDC_QRH_INDIRECT_FORCE_BUBBLE */ "", 3563 /* BRDC_QRH_INTERRUPT_MASK_REGISTER */ "", 3564 /* BRDC_QRH_INTERRUPT_REGISTER */ "", 3565 /* BRDC_QRH_INTERRUPT_REGISTER_TEST */ "", 3566 /* BRDC_QRH_LCM_FC_CONFIG */ "", 3567 /* BRDC_QRH_LOAD_BALANCE_MAX_DEBUG_LINK_P */ "", 3568 /* BRDC_QRH_LOAD_BALANCE_MAX_LEVEL_P */ "", 3569 /* BRDC_QRH_LOCAL_ROUTE_CONFIGURATIONS */ "", 3570 /* BRDC_QRH_LOW_PR_MULTH */ "", 3571 /* BRDC_QRH_LOW_PR_MUL_CTRL */ "", 3572 /* BRDC_QRH_MASK_FC_AGING_PERIOD */ "", 3573 /* BRDC_QRH_MULICAST_ALLOWED_LINKS_REGISTER */ "", 3574 /* BRDC_QRH_MULTICAST_MODE_SELECTION */ "", 3575 /* BRDC_QRH_PIPES_WEIGHTS_COUNTER_0 */ "", 3576 /* BRDC_QRH_PIPES_WEIGHTS_COUNTER_1 */ "", 3577 /* BRDC_QRH_PIPES_WEIGHTS_COUNTER_2 */ "", 3578 /* BRDC_QRH_REACHABILITY_MESSAGE_GENERATOR_CONFIGURATION */ "", 3579 /* BRDC_QRH_RESERVED_MIRROR_ADDR */ "", 3580 /* BRDC_QRH_RESERVED_MTCD */ "", 3581 /* BRDC_QRH_RESERVED_MTCP */ "", 3582 /* BRDC_QRH_RESERVED_SPARE_0 */ "", 3583 /* BRDC_QRH_RESERVED_SPARE_1 */ "", 3584 /* BRDC_QRH_RESERVED_SPARE_2 */ "", 3585 /* BRDC_QRH_RESERVED_SPARE_3 */ "", 3586 /* BRDC_QRH_SBUS_BROADCAST_ID */ "", 3587 /* BRDC_QRH_SBUS_LAST_IN_CHAIN */ "", 3588 /* BRDC_QRH_SIMPLE_RR_LINKS_CONFIG */ "", 3589 /* BROADSCAN_LOGICAL_TABLE_SELECT_CONFIG */ "", 3590 /* BROADSCAN_LOGICAL_TABLE_SELECT_CONFIG_PIPE0 */ "", 3591 /* BSAFE_GLB_CMD_CTRL */ "", 3592 /* BSAFE_GLB_CMD_DATA_IN */ "", 3593 /* BSAFE_GLB_CMD_DATA_OUT */ "", 3594 /* BSAFE_GLB_DEV_STATUS */ "", 3595 /* BSAFE_GLB_INT_CTRL */ "", 3596 /* BSAFE_GLB_MEM_PARAM */ "", 3597 /* BSAFE_GLB_MEM_TST_CTL */ "", 3598 /* BSAFE_GLB_PRESCALE */ "", 3599 /* BSAFE_GLB_PROD_CFG */ "", 3600 /* BSAFE_GLB_TIMER */ "", 3601 /* BSAFE_GLB_UHSM_CFG */ "", 3602 /* BSC_AG_DEBUG_REGISTER */ "", 3603 /* BSC_AG_GROUP_FLUSH_CONFIG_64 */ "", 3604 /* BSC_AG_PERIODIC_EXPORT */ "", 3605 /* BSC_AG_RAM_CONTROL */ "", 3606 /* BSC_AG_RAM_CONTROL_PIPE0 */ "", 3607 /* BSC_AG_SCAN_ADDR_RANGE_CONTROL */ "", 3608 /* BSC_AG_SCAN_CONTROL */ "", 3609 /* BSC_AG_SCAN_PERIOD_SELECT */ "", 3610 /* BSC_AG_SER_CONTROL */ "", 3611 /* BSC_DG_RAM_CONTROL_0 */ "", 3612 /* BSC_DG_RAM_CONTROL_1 */ "", 3613 /* BSC_DG_RAM_CONTROL_2 */ "", 3614 /* BSC_DG_RAM_CONTROL_0_PIPE0 */ "", 3615 /* BSC_DG_RAM_CONTROL_1_PIPE0 */ "", 3616 /* BSC_DG_RAM_CONTROL_2_PIPE0 */ "", 3617 /* BSC_DG_SER_CONTROL */ "", 3618 /* BSC_DT_PDE_RAM_CONTROL */ "", 3619 /* BSC_DT_RAM_CONTROL */ "", 3620 /* BSC_DT_RANDOM_SEED_CONFIG */ "", 3621 /* BSC_DT_SER_CONTROL */ "", 3622 /* BSC_EX_BROADSCAN_GLOBAL_SER_DROP_ENABLE */ "", 3623 /* BSC_EX_BROADSCAN_IPFIX_CREDIT_RESET */ "", 3624 /* BSC_EX_EXPORT_CONTROL */ "", 3625 /* BSC_EX_EXPORT_RAM_CONTROL */ "", 3626 /* BSC_EX_EXPORT_SET_LENGTH */ "", 3627 /* BSC_EX_GLOBAL_EVENT_VECTOR_CONTROL_ON_SER */ "", 3628 /* BSC_EX_SEQ_NUM */ "", 3629 /* BSC_EX_SER_CONTROL */ "", 3630 /* BSC_KG_RAM_CONTROL */ "", 3631 /* BSC_KG_RAM_CONTROL_PIPE0 */ "", 3632 /* BSC_KG_SER_CONTROL */ "", 3633 /* BSC_KT_KEY_SER_CONTROL */ "", 3634 /* BSC_KT_KEY_TABLE_RAM_CONTROL_0 */ "", 3635 /* BSC_KT_KEY_TABLE_RAM_CONTROL_1 */ "", 3636 /* BSK_ALU_DATA_LTS_C_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 3637 /* BSK_ALU_DATA_LTS_C_KEY_GEN_CAM_BIST_STATUS */ "", 3638 /* BSK_ALU_DATA_LTS_C_KEY_GEN_SER_CONTROL */ "", 3639 /* BSK_ALU_DATA_LTS_C_KEY_GEN_TM_CONTROL_64 */ "", 3640 /* BSK_FTFP_CAM_BIST_CONFIG_64 */ "", 3641 /* BSK_FTFP_CAM_BIST_STATUS */ "", 3642 /* BSK_FTFP_CAM_CONTROL */ "", 3643 /* BSK_FTFP_LTS_A_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 3644 /* BSK_FTFP_LTS_A_KEY_GEN_CAM_BIST_STATUS */ "", 3645 /* BSK_FTFP_LTS_A_KEY_GEN_SER_CONTROL */ "", 3646 /* BSK_FTFP_LTS_A_KEY_GEN_TM_CONTROL_64 */ "", 3647 /* BSK_FTFP_LTS_B_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 3648 /* BSK_FTFP_LTS_B_KEY_GEN_CAM_BIST_STATUS */ "", 3649 /* BSK_FTFP_LTS_B_KEY_GEN_SER_CONTROL */ "", 3650 /* BSK_FTFP_LTS_B_KEY_GEN_TM_CONTROL_64 */ "", 3651 /* BSK_FTFP_RAM_CONTROL */ "", 3652 /* BSK_SESSION_DATA_LTS_A_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 3653 /* BSK_SESSION_DATA_LTS_A_KEY_GEN_CAM_BIST_STATUS */ "", 3654 /* BSK_SESSION_DATA_LTS_A_KEY_GEN_SER_CONTROL */ "", 3655 /* BSK_SESSION_DATA_LTS_A_KEY_GEN_TM_CONTROL_64 */ "", 3656 /* BSK_SESSION_DATA_LTS_B_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 3657 /* BSK_SESSION_DATA_LTS_B_KEY_GEN_CAM_BIST_STATUS */ "", 3658 /* BSK_SESSION_DATA_LTS_B_KEY_GEN_SER_CONTROL */ "", 3659 /* BSK_SESSION_DATA_LTS_B_KEY_GEN_TM_CONTROL_64 */ "", 3660 /* BSK_SESSION_KEY_LTS_A_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 3661 /* BSK_SESSION_KEY_LTS_A_KEY_GEN_CAM_BIST_STATUS */ "", 3662 /* BSK_SESSION_KEY_LTS_A_KEY_GEN_SER_CONTROL */ "", 3663 /* BSK_SESSION_KEY_LTS_A_KEY_GEN_TM_CONTROL_64 */ "", 3664 /* BSK_SESSION_KEY_LTS_B_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 3665 /* BSK_SESSION_KEY_LTS_B_KEY_GEN_CAM_BIST_STATUS */ "", 3666 /* BSK_SESSION_KEY_LTS_B_KEY_GEN_SER_CONTROL */ "", 3667 /* BSK_SESSION_KEY_LTS_B_KEY_GEN_TM_CONTROL_64 */ "", 3668 /* BST_HW_SNAPSHOT_EN */ "", 3669 /* BST_SNAPSHOT_ACTION_EN */ "", 3670 /* BST_TRACKING_CONFIG */ "BST_HW_SNAPSHOT_ENABLE", 3671 /* BST_TRACKING_ENABLE */ "", 3672 /* BUCKET_ECC */ "", 3673 /* BUFFER_CELL_LIMIT_SP */ "", 3674 /* BUFFER_CELL_LIMIT_SP_SHARED */ "", 3675 /* BUFFER_PACKET_LIMIT_SP */ "", 3676 /* BUFFER_PACKET_LIMIT_SP_SHARED */ "", 3677 /* BUF_CFG */ "", 3678 /* CAPWAP_ENABLE */ "", 3679 /* CAPWAP_PAYLOAD_PARSING_CONTROL */ "", 3680 /* CASCHNG1_CID_0 */ "", 3681 /* CASCHNG1_CID_1 */ "", 3682 /* CASCHNG1_CID_2 */ "", 3683 /* CASCHNG1_CID_3 */ "", 3684 /* CASCHNG1_CID_4 */ "", 3685 /* CASCHNG1_CID_5 */ "", 3686 /* CASCHNG1_CID_6 */ "", 3687 /* CASCHNG1_CID_7 */ "", 3688 /* CASCHNG1_CID_8 */ "", 3689 /* CASCHNG1_CID_9 */ "", 3690 /* CASCHNG1_CID_10 */ "", 3691 /* CASCHNG1_CID_11 */ "", 3692 /* CASCHNG1_CID_12 */ "", 3693 /* CASCHNG1_CID_13 */ "", 3694 /* CASCHNG1_CID_14 */ "", 3695 /* CASCHNG1_CID_15 */ "", 3696 /* CASCHNG2_CID_0 */ "", 3697 /* CASCHNG2_CID_1 */ "", 3698 /* CASCHNG2_CID_2 */ "", 3699 /* CASCHNG2_CID_3 */ "", 3700 /* CASCHNG2_CID_4 */ "", 3701 /* CASCHNG2_CID_5 */ "", 3702 /* CASCHNG2_CID_6 */ "", 3703 /* CASCHNG2_CID_7 */ "", 3704 /* CASCHNG2_CID_8 */ "", 3705 /* CASCHNG2_CID_9 */ "", 3706 /* CASCHNG2_CID_10 */ "", 3707 /* CASCHNG2_CID_11 */ "", 3708 /* CASCHNG2_CID_12 */ "", 3709 /* CASCHNG2_CID_13 */ "", 3710 /* CASCHNG2_CID_14 */ "", 3711 /* CASCHNG2_CID_15 */ "", 3712 /* CASIDLE */ "", 3713 /* CASMODRPC_CHID_0 */ "", 3714 /* CASMODRPC_CHID_1 */ "", 3715 /* CASMODRPC_CHID_2 */ "", 3716 /* CASMODRPC_CHID_3 */ "", 3717 /* CASMODRPC_CHID_4 */ "", 3718 /* CASMODRPC_CHID_5 */ "", 3719 /* CASMODRPC_CHID_6 */ "", 3720 /* CASMODRPC_CHID_7 */ "", 3721 /* CASMODRPC_CHID_8 */ "", 3722 /* CASMODRPC_CHID_9 */ "", 3723 /* CASMODRPC_CHID_10 */ "", 3724 /* CASMODRPC_CHID_11 */ "", 3725 /* CASMODRPC_CHID_12 */ "", 3726 /* CASMODRPC_CHID_13 */ "", 3727 /* CASMODRPC_CHID_14 */ "", 3728 /* CASMODRPC_CHID_15 */ "", 3729 /* CASMODRPC_CHID_16 */ "", 3730 /* CASMODRPC_CHID_17 */ "", 3731 /* CASMODRPC_CHID_18 */ "", 3732 /* CASMODRPC_CHID_19 */ "", 3733 /* CASMODRPC_CHID_20 */ "", 3734 /* CASMODRPC_CHID_21 */ "", 3735 /* CASMODRPC_CHID_22 */ "", 3736 /* CASMODRPC_CHID_23 */ "", 3737 /* CASMODRPC_CHID_24 */ "", 3738 /* CASMODRPC_CHID_25 */ "", 3739 /* CASMODRPC_CHID_26 */ "", 3740 /* CASMODRPC_CHID_27 */ "", 3741 /* CASMODRPC_CHID_28 */ "", 3742 /* CASMODRPC_CHID_29 */ "", 3743 /* CASMODRPC_CHID_30 */ "", 3744 /* CASMODRPC_CHID_31 */ "", 3745 /* CASMODRPC_CHID_32 */ "", 3746 /* CASMODRPC_CHID_33 */ "", 3747 /* CASMODRPC_CHID_34 */ "", 3748 /* CASMODRPC_CHID_35 */ "", 3749 /* CASMODRPC_CHID_36 */ "", 3750 /* CASMODRPC_CHID_37 */ "", 3751 /* CASMODRPC_CHID_38 */ "", 3752 /* CASMODRPC_CHID_39 */ "", 3753 /* CASMODRPC_CHID_40 */ "", 3754 /* CASMODRPC_CHID_41 */ "", 3755 /* CASMODRPC_CHID_42 */ "", 3756 /* CASMODRPC_CHID_43 */ "", 3757 /* CASMODRPC_CHID_44 */ "", 3758 /* CASMODRPC_CHID_45 */ "", 3759 /* CASMODRPC_CHID_46 */ "", 3760 /* CASMODRPC_CHID_47 */ "", 3761 /* CASMODRPC_CHID_48 */ "", 3762 /* CASMODRPC_CHID_49 */ "", 3763 /* CASMODRPC_CHID_50 */ "", 3764 /* CASMODRPC_CHID_51 */ "", 3765 /* CASMODRPC_CHID_52 */ "", 3766 /* CASMODRPC_CHID_53 */ "", 3767 /* CASMODRPC_CHID_54 */ "", 3768 /* CASMODRPC_CHID_55 */ "", 3769 /* CASMODRPC_CHID_56 */ "", 3770 /* CASMODRPC_CHID_57 */ "", 3771 /* CASMODRPC_CHID_58 */ "", 3772 /* CASMODRPC_CHID_59 */ "", 3773 /* CASMODRPC_CHID_60 */ "", 3774 /* CASMODRPC_CHID_61 */ "", 3775 /* CASMODRPC_CHID_62 */ "", 3776 /* CASMODRPC_CHID_63 */ "", 3777 /* CASOTPC_CHID_0 */ "", 3778 /* CASOTPC_CHID_1 */ "", 3779 /* CASOTPC_CHID_2 */ "", 3780 /* CASOTPC_CHID_3 */ "", 3781 /* CASOTPC_CHID_4 */ "", 3782 /* CASOTPC_CHID_5 */ "", 3783 /* CASOTPC_CHID_6 */ "", 3784 /* CASOTPC_CHID_7 */ "", 3785 /* CASOTPC_CHID_8 */ "", 3786 /* CASOTPC_CHID_9 */ "", 3787 /* CASOTPC_CHID_10 */ "", 3788 /* CASOTPC_CHID_11 */ "", 3789 /* CASOTPC_CHID_12 */ "", 3790 /* CASOTPC_CHID_13 */ "", 3791 /* CASOTPC_CHID_14 */ "", 3792 /* CASOTPC_CHID_15 */ "", 3793 /* CASOTPC_CHID_16 */ "", 3794 /* CASOTPC_CHID_17 */ "", 3795 /* CASOTPC_CHID_18 */ "", 3796 /* CASOTPC_CHID_19 */ "", 3797 /* CASOTPC_CHID_20 */ "", 3798 /* CASOTPC_CHID_21 */ "", 3799 /* CASOTPC_CHID_22 */ "", 3800 /* CASOTPC_CHID_23 */ "", 3801 /* CASOTPC_CHID_24 */ "", 3802 /* CASOTPC_CHID_25 */ "", 3803 /* CASOTPC_CHID_26 */ "", 3804 /* CASOTPC_CHID_27 */ "", 3805 /* CASOTPC_CHID_28 */ "", 3806 /* CASOTPC_CHID_29 */ "", 3807 /* CASOTPC_CHID_30 */ "", 3808 /* CASOTPC_CHID_31 */ "", 3809 /* CASOTPC_CHID_32 */ "", 3810 /* CASOTPC_CHID_33 */ "", 3811 /* CASOTPC_CHID_34 */ "", 3812 /* CASOTPC_CHID_35 */ "", 3813 /* CASOTPC_CHID_36 */ "", 3814 /* CASOTPC_CHID_37 */ "", 3815 /* CASOTPC_CHID_38 */ "", 3816 /* CASOTPC_CHID_39 */ "", 3817 /* CASOTPC_CHID_40 */ "", 3818 /* CASOTPC_CHID_41 */ "", 3819 /* CASOTPC_CHID_42 */ "", 3820 /* CASOTPC_CHID_43 */ "", 3821 /* CASOTPC_CHID_44 */ "", 3822 /* CASOTPC_CHID_45 */ "", 3823 /* CASOTPC_CHID_46 */ "", 3824 /* CASOTPC_CHID_47 */ "", 3825 /* CASOTPC_CHID_48 */ "", 3826 /* CASOTPC_CHID_49 */ "", 3827 /* CASOTPC_CHID_50 */ "", 3828 /* CASOTPC_CHID_51 */ "", 3829 /* CASOTPC_CHID_52 */ "", 3830 /* CASOTPC_CHID_53 */ "", 3831 /* CASOTPC_CHID_54 */ "", 3832 /* CASOTPC_CHID_55 */ "", 3833 /* CASOTPC_CHID_56 */ "", 3834 /* CASOTPC_CHID_57 */ "", 3835 /* CASOTPC_CHID_58 */ "", 3836 /* CASOTPC_CHID_59 */ "", 3837 /* CASOTPC_CHID_60 */ "", 3838 /* CASOTPC_CHID_61 */ "", 3839 /* CASOTPC_CHID_62 */ "", 3840 /* CASOTPC_CHID_63 */ "", 3841 /* CASREPL1_CID_0 */ "", 3842 /* CASREPL1_CID_1 */ "", 3843 /* CASREPL1_CID_2 */ "", 3844 /* CASREPL1_CID_3 */ "", 3845 /* CASREPL1_CID_4 */ "", 3846 /* CASREPL1_CID_5 */ "", 3847 /* CASREPL1_CID_6 */ "", 3848 /* CASREPL1_CID_7 */ "", 3849 /* CASREPL1_CID_8 */ "", 3850 /* CASREPL1_CID_9 */ "", 3851 /* CASREPL1_CID_10 */ "", 3852 /* CASREPL1_CID_11 */ "", 3853 /* CASREPL1_CID_12 */ "", 3854 /* CASREPL1_CID_13 */ "", 3855 /* CASREPL1_CID_14 */ "", 3856 /* CASREPL1_CID_15 */ "", 3857 /* CASREPL2_CID_0 */ "", 3858 /* CASREPL2_CID_1 */ "", 3859 /* CASREPL2_CID_2 */ "", 3860 /* CASREPL2_CID_3 */ "", 3861 /* CASREPL2_CID_4 */ "", 3862 /* CASREPL2_CID_5 */ "", 3863 /* CASREPL2_CID_6 */ "", 3864 /* CASREPL2_CID_7 */ "", 3865 /* CASREPL2_CID_8 */ "", 3866 /* CASREPL2_CID_9 */ "", 3867 /* CASREPL2_CID_10 */ "", 3868 /* CASREPL2_CID_11 */ "", 3869 /* CASREPL2_CID_12 */ "", 3870 /* CASREPL2_CID_13 */ "", 3871 /* CASREPL2_CID_14 */ "", 3872 /* CASREPL2_CID_15 */ "", 3873 /* CASSTAT_CHID_0 */ "", 3874 /* CASSTAT_CHID_1 */ "", 3875 /* CASSTAT_CHID_2 */ "", 3876 /* CASSTAT_CHID_3 */ "", 3877 /* CASSTAT_CHID_4 */ "", 3878 /* CASSTAT_CHID_5 */ "", 3879 /* CASSTAT_CHID_6 */ "", 3880 /* CASSTAT_CHID_7 */ "", 3881 /* CASSTAT_CHID_8 */ "", 3882 /* CASSTAT_CHID_9 */ "", 3883 /* CASSTAT_CHID_10 */ "", 3884 /* CASSTAT_CHID_11 */ "", 3885 /* CASSTAT_CHID_12 */ "", 3886 /* CASSTAT_CHID_13 */ "", 3887 /* CASSTAT_CHID_14 */ "", 3888 /* CASSTAT_CHID_15 */ "", 3889 /* CASSTAT_CHID_16 */ "", 3890 /* CASSTAT_CHID_17 */ "", 3891 /* CASSTAT_CHID_18 */ "", 3892 /* CASSTAT_CHID_19 */ "", 3893 /* CASSTAT_CHID_20 */ "", 3894 /* CASSTAT_CHID_21 */ "", 3895 /* CASSTAT_CHID_22 */ "", 3896 /* CASSTAT_CHID_23 */ "", 3897 /* CASSTAT_CHID_24 */ "", 3898 /* CASSTAT_CHID_25 */ "", 3899 /* CASSTAT_CHID_26 */ "", 3900 /* CASSTAT_CHID_27 */ "", 3901 /* CASSTAT_CHID_28 */ "", 3902 /* CASSTAT_CHID_29 */ "", 3903 /* CASSTAT_CHID_30 */ "", 3904 /* CASSTAT_CHID_31 */ "", 3905 /* CASSTAT_CHID_32 */ "", 3906 /* CASSTAT_CHID_33 */ "", 3907 /* CASSTAT_CHID_34 */ "", 3908 /* CASSTAT_CHID_35 */ "", 3909 /* CASSTAT_CHID_36 */ "", 3910 /* CASSTAT_CHID_37 */ "", 3911 /* CASSTAT_CHID_38 */ "", 3912 /* CASSTAT_CHID_39 */ "", 3913 /* CASSTAT_CHID_40 */ "", 3914 /* CASSTAT_CHID_41 */ "", 3915 /* CASSTAT_CHID_42 */ "", 3916 /* CASSTAT_CHID_43 */ "", 3917 /* CASSTAT_CHID_44 */ "", 3918 /* CASSTAT_CHID_45 */ "", 3919 /* CASSTAT_CHID_46 */ "", 3920 /* CASSTAT_CHID_47 */ "", 3921 /* CASSTAT_CHID_48 */ "", 3922 /* CASSTAT_CHID_49 */ "", 3923 /* CASSTAT_CHID_50 */ "", 3924 /* CASSTAT_CHID_51 */ "", 3925 /* CASSTAT_CHID_52 */ "", 3926 /* CASSTAT_CHID_53 */ "", 3927 /* CASSTAT_CHID_54 */ "", 3928 /* CASSTAT_CHID_55 */ "", 3929 /* CASSTAT_CHID_56 */ "", 3930 /* CASSTAT_CHID_57 */ "", 3931 /* CASSTAT_CHID_58 */ "", 3932 /* CASSTAT_CHID_59 */ "", 3933 /* CASSTAT_CHID_60 */ "", 3934 /* CASSTAT_CHID_61 */ "", 3935 /* CASSTAT_CHID_62 */ "", 3936 /* CASSTAT_CHID_63 */ "", 3937 /* CBL_ATTRIBUTE */ "", 3938 /* CBPCELLCRCERRPTR */ "", 3939 /* CBPCELLERRPTR */ "", 3940 /* CBPCELLHDRMEMDEBUG */ "", 3941 /* CBPCELLHDRPARITYERRPTR */ "", 3942 /* CBPCELLLINKMEMDEBUG */ "", 3943 /* CBPCELLLINKPARITYERRPTR */ "", 3944 /* CBPDATAMEM0DEBUG */ "", 3945 /* CBPDATAMEM10DEBUG */ "", 3946 /* CBPDATAMEM11DEBUG */ "", 3947 /* CBPDATAMEM12DEBUG */ "", 3948 /* CBPDATAMEM13DEBUG */ "", 3949 /* CBPDATAMEM14DEBUG */ "", 3950 /* CBPDATAMEM15DEBUG */ "", 3951 /* CBPDATAMEM1DEBUG */ "", 3952 /* CBPDATAMEM2DEBUG */ "", 3953 /* CBPDATAMEM3DEBUG */ "", 3954 /* CBPDATAMEM4DEBUG */ "", 3955 /* CBPDATAMEM5DEBUG */ "", 3956 /* CBPDATAMEM6DEBUG */ "", 3957 /* CBPDATAMEM7DEBUG */ "", 3958 /* CBPDATAMEM8DEBUG */ "", 3959 /* CBPDATAMEM9DEBUG */ "", 3960 /* CBPDATAMEMDEBUG */ "", 3961 /* CBPMEMDEBUG */ "", 3962 /* CBPMEMDEBUG1 */ "", 3963 /* CBPMEMDEBUG2 */ "", 3964 /* CBPPKTHDR0LMEMDEBUG */ "", 3965 /* CBPPKTHDR0MEMDEBUG */ "", 3966 /* CBPPKTHDR0UMEMDEBUG */ "", 3967 /* CBPPKTHDR1MEMDEBUG */ "", 3968 /* CBPPKTHDR2MEMDEBUG */ "", 3969 /* CBPPKTHDRCPUMEMDEBUG */ "", 3970 /* CBPPKTHDRMEM0DEBUG */ "", 3971 /* CBPPKTHDRMEM1DEBUG */ "", 3972 /* CBPPKTHDRMEM2DEBUG */ "", 3973 /* CBPPKTHDRMEMEXTDEBUG */ "", 3974 /* CBPPKTHDRPARITYERRPTR */ "", 3975 /* CBPPKTHDR_ERRPTR0 */ "", 3976 /* CBPPKTHDR_ERRPTR1 */ "", 3977 /* CBPPKTHDR_ERRPTR2 */ "", 3978 /* CBPPKTHDR_ERRPTR3 */ "", 3979 /* CBPPKTHDR_ERR_CLR */ "", 3980 /* CBPPKTHDR_ERR_VLD */ "", 3981 /* CBPPOWERDOWN00 */ "", 3982 /* CBPPOWERDOWN01 */ "", 3983 /* CBPPOWERDOWN02 */ "", 3984 /* CBPPOWERDOWN10 */ "", 3985 /* CBPPOWERDOWN11 */ "", 3986 /* CBPPOWERDOWN12 */ "", 3987 /* CBPPOWERDOWN20 */ "", 3988 /* CBPPOWERDOWN21 */ "", 3989 /* CBPPOWERDOWN22 */ "", 3990 /* CBPPOWERDOWN30 */ "", 3991 /* CBPPOWERDOWN31 */ "", 3992 /* CBPPOWERDOWN32 */ "", 3993 /* CCH_ARAD_BMP */ "", 3994 /* CCH_AUTO_DOC_NAME_6 */ "", 3995 /* CCH_AUTO_DOC_NAME_7 */ "", 3996 /* CCH_AUTO_DOC_NAME_12 */ "", 3997 /* CCH_AUTO_DOC_NAME_13 */ "", 3998 /* CCH_AUTO_DOC_NAME_14 */ "", 3999 /* CCH_AUTO_DOC_NAME_15 */ "", 4000 /* CCH_AUTO_DOC_NAME_16 */ "", 4001 /* CCH_AUTO_DOC_NAME_17 */ "", 4002 /* CCH_AUTO_DOC_NAME_18 */ "", 4003 /* CCH_AUTO_DOC_NAME_19 */ "", 4004 /* CCH_AUTO_DOC_NAME_20 */ "", 4005 /* CCH_AUTO_DOC_NAME_21 */ "", 4006 /* CCH_CAPTURED_CELL */ "", 4007 /* CCH_CAPTURED_CELL_VALID */ "", 4008 /* CCH_CAPTURE_FIFO_DISCARD_CNT */ "", 4009 /* CCH_CAPTURE_FILTER_CELL_0 */ "", 4010 /* CCH_CAPTURE_FILTER_CELL_1 */ "", 4011 /* CCH_CAPTURE_FILTER_MASK_0 */ "", 4012 /* CCH_CAPTURE_FILTER_MASK_1 */ "", 4013 /* CCH_CAPTURE_HIT_CNT */ "", 4014 /* CCH_CAPTURE_HIT_MASK_0_CNT */ "", 4015 /* CCH_CAPTURE_HIT_MASK_1_CNT */ "", 4016 /* CCH_CCH_CONFIGURATIONS */ "", 4017 /* CCH_CCP_0_DSCRD_CNT */ "", 4018 /* CCH_CCP_0_ILLEGAL_CELLS_DATA */ "", 4019 /* CCH_CCP_0_PROGRAMMABLE_CELLS_COUNTER */ "", 4020 /* CCH_CCP_1_DSCRD_CNT */ "", 4021 /* CCH_CCP_1_ILLEGAL_CELLS_DATA */ "", 4022 /* CCH_CCP_1_PROGRAMMABLE_CELLS_COUNTER */ "", 4023 /* CCH_CCP_FIFOS_WATER_MARK */ "", 4024 /* CCH_CONNECTIVITY_LINKS_EVENTS */ "", 4025 /* CCH_CONNECTIVITY_LINK_0 */ "", 4026 /* CCH_CONNECTIVITY_LINK_1 */ "", 4027 /* CCH_CONNECTIVITY_LINK_2 */ "", 4028 /* CCH_CONNECTIVITY_LINK_3 */ "", 4029 /* CCH_CONNECTIVITY_LINK_4 */ "", 4030 /* CCH_CONNECTIVITY_LINK_5 */ "", 4031 /* CCH_CONNECTIVITY_LINK_6 */ "", 4032 /* CCH_CONNECTIVITY_LINK_7 */ "", 4033 /* CCH_CONNECTIVITY_LINK_8 */ "", 4034 /* CCH_CONNECTIVITY_LINK_9 */ "", 4035 /* CCH_CONNECTIVITY_LINK_10 */ "", 4036 /* CCH_CONNECTIVITY_LINK_11 */ "", 4037 /* CCH_CONNECTIVITY_LINK_12 */ "", 4038 /* CCH_CONNECTIVITY_LINK_13 */ "", 4039 /* CCH_CONNECTIVITY_LINK_14 */ "", 4040 /* CCH_CONNECTIVITY_LINK_15 */ "", 4041 /* CCH_CONNECTIVITY_LINK_16 */ "", 4042 /* CCH_CONNECTIVITY_LINK_17 */ "", 4043 /* CCH_CONNECTIVITY_LINK_18 */ "", 4044 /* CCH_CONNECTIVITY_LINK_19 */ "", 4045 /* CCH_CONNECTIVITY_LINK_20 */ "", 4046 /* CCH_CONNECTIVITY_LINK_21 */ "", 4047 /* CCH_CONNECTIVITY_LINK_22 */ "", 4048 /* CCH_CONNECTIVITY_LINK_23 */ "", 4049 /* CCH_CREDIT_CELLS_CNT */ "", 4050 /* CCH_CRP_FIFO_WATER_MARK */ "", 4051 /* CCH_CRP_UNREACHABLE_CELL_DATA */ "", 4052 /* CCH_DEBUG_CONFIGURATIONS */ "", 4053 /* CCH_ECC_1B_ERR_CNT */ "", 4054 /* CCH_ECC_2B_ERR_CNT */ "", 4055 /* CCH_ECC_ERR_1B_INITIATE */ "", 4056 /* CCH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 4057 /* CCH_ECC_ERR_2B_INITIATE */ "", 4058 /* CCH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 4059 /* CCH_ECC_INTERRUPT_REGISTER */ "", 4060 /* CCH_ECC_INTERRUPT_REGISTER_MASK */ "", 4061 /* CCH_ECC_INTERRUPT_REGISTER_TEST */ "", 4062 /* CCH_ERROR_INITIATION_DATA */ "", 4063 /* CCH_FE_GLOBAL_GENERAL_CFG_1 */ "", 4064 /* CCH_FILTERED_CELLS_CONFIGURATIONS */ "", 4065 /* CCH_FLOW_STATUS_CELLS_CNT */ "", 4066 /* CCH_GLOBAL_MEM_OPTIONS */ "", 4067 /* CCH_GTIMER_CONFIGURATION */ "", 4068 /* CCH_GTIMER_CYCLE */ "", 4069 /* CCH_INTERRUPT_MASK_REGISTER */ "", 4070 /* CCH_INTERRUPT_REGISTER */ "", 4071 /* CCH_INTERRUPT_REGISTER_TEST */ "", 4072 /* CCH_PAR_ERR_INITIATE */ "", 4073 /* CCH_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTER */ "", 4074 /* CCH_REACHABILITY_CELLS_CNT */ "", 4075 /* CCH_RESERVED_MIRROR_ADDR */ "", 4076 /* CCH_RESERVED_MTCD */ "", 4077 /* CCH_RESERVED_MTCP */ "", 4078 /* CCH_RESERVED_SPARE_0 */ "", 4079 /* CCH_RESERVED_SPARE_1 */ "", 4080 /* CCH_RESERVED_SPARE_2 */ "", 4081 /* CCH_RESERVED_SPARE_3 */ "", 4082 /* CCH_SBUS_BROADCAST_ID */ "", 4083 /* CCH_SBUS_LAST_IN_CHAIN */ "", 4084 /* CCH_SELF_ROUTED_CELLS_CNT */ "", 4085 /* CCH_TOTAL_CELLS_CNT */ "", 4086 /* CCH_UNREACHABLE_DESTINATION_CELLS_CNT */ "", 4087 /* CCM_COPYTO_CPU_CONTROL */ "", 4088 /* CCM_INTERRUPT_CONTROL */ "", 4089 /* CCM_READ_CONTROL */ "", 4090 /* CCPE_MEMDEBUG */ "", 4091 /* CCPFIFO_STS */ "", 4092 /* CCPI_MEMDEBUG */ "", 4093 /* CCPMEMDEBUG */ "", 4094 /* CCPPARITYERRORPTR */ "", 4095 /* CCP_COMMON_DEBUG0 */ "", 4096 /* CCP_ERROR */ "", 4097 /* CCP_ERROR_MASK */ "", 4098 /* CCP_EXT_DEBUG0 */ "", 4099 /* CCP_FIFO_MEMDEBUG */ "", 4100 /* CCP_INT_DEBUG0 */ "", 4101 /* CCP_STS */ "", 4102 /* CCS_ARAD_BMP */ "", 4103 /* CCS_CAPTURED_CELL */ "", 4104 /* CCS_CAPTURED_CELL_VALID */ "", 4105 /* CCS_CAPTURE_FIFO_DISCARD_CNT */ "", 4106 /* CCS_CAPTURE_FILTER_CELL_0 */ "", 4107 /* CCS_CAPTURE_FILTER_CELL_1 */ "", 4108 /* CCS_CAPTURE_FILTER_MASK_0 */ "", 4109 /* CCS_CAPTURE_FILTER_MASK_1 */ "", 4110 /* CCS_CAPTURE_HIT_CNT */ "", 4111 /* CCS_CCS_CONFIGURATIONS */ "", 4112 /* CCS_CDMA_LP_CELLS_DISCARD_CNT */ "", 4113 /* CCS_CDMB_LP_CELLS_DISCARD_CNT */ "", 4114 /* CCS_CDMC_LP_CELLS_DISCARD_CNT */ "", 4115 /* CCS_CDMD_LP_CELLS_DISCARD_CNT */ "", 4116 /* CCS_CDM_OVERFLOW_FIFO_NUMBER */ "", 4117 /* CCS_CPU_SOURCE_CELL_DATA */ "", 4118 /* CCS_CPU_SOURCE_CELL_TRIGGER */ "", 4119 /* CCS_CPU_SRC_CELL_DATA */ "", 4120 /* CCS_CREDIT_CELLS_CNT */ "", 4121 /* CCS_CRP_FIFO_WATER_MARK */ "", 4122 /* CCS_CRP_PARITY_ERR_CNT */ "", 4123 /* CCS_CRP_UNREACHABLE_CELL_DATA */ "", 4124 /* CCS_CTP_INTERNAL_REACHABILITY_CELLS_CNT */ "", 4125 /* CCS_DEBUG_CONFIGURATIONS */ "", 4126 /* CCS_ECC_1B_ERR_CNT */ "", 4127 /* CCS_ECC_2B_ERR_CNT */ "", 4128 /* CCS_ECC_ERR_1B_INITIATE */ "", 4129 /* CCS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 4130 /* CCS_ECC_ERR_2B_INITIATE */ "", 4131 /* CCS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 4132 /* CCS_ECC_ERR_MONITOR_MEM_MASK */ "", 4133 /* CCS_ECC_INTERRUPT_REGISTER */ "", 4134 /* CCS_ECC_INTERRUPT_REGISTER_MASK */ "", 4135 /* CCS_ECC_INTERRUPT_REGISTER_TEST */ "", 4136 /* CCS_ERROR_INITIATION_DATA */ "", 4137 /* CCS_FE_13_LINKS_CREDIT_CELLS_CNT */ "", 4138 /* CCS_FE_13_LINKS_FLOW_STATUS_CELLS_CNT */ "", 4139 /* CCS_FE_13_LINKS_REACHABILITY_CELLS_CNT */ "", 4140 /* CCS_FE_13_LINKS_SELF_ROUTED_CELLS_CNT */ "", 4141 /* CCS_FE_13_LINKS_TOTAL_CELLS_CNT */ "", 4142 /* CCS_FILTERED_CELLS_CONFIGURATIONS */ "", 4143 /* CCS_FLOW_STATUS_CELLS_CNT */ "", 4144 /* CCS_GLOBAL_GENERAL_CFG_2 */ "", 4145 /* CCS_GLOBAL_GENERAL_FE_CFG_1 */ "", 4146 /* CCS_GLOBAL_MEM_OPTIONS */ "", 4147 /* CCS_GTIMER_CONFIGURATION */ "", 4148 /* CCS_GTIMER_TRIGGER */ "", 4149 /* CCS_INITIATE_CELL_PARITY_ERROR */ "", 4150 /* CCS_INITIATE_ECC_ERROR */ "", 4151 /* CCS_INTERRUPT_MASK_REGISTER */ "", 4152 /* CCS_INTERRUPT_REGISTER */ "", 4153 /* CCS_INTERRUPT_REGISTER_TEST */ "", 4154 /* CCS_MID_FIFOS_LP_WATER_MARK */ "", 4155 /* CCS_PAR_ERR_INITIATE */ "", 4156 /* CCS_PROGRAMMABLE_MID_FIFOS_WATER_MARK */ "", 4157 /* CCS_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARK */ "", 4158 /* CCS_REACHABILITY_CELLS_CNT */ "", 4159 /* CCS_REG_0050 */ "", 4160 /* CCS_REG_0051 */ "", 4161 /* CCS_REG_0052 */ "", 4162 /* CCS_REG_0054 */ "", 4163 /* CCS_REG_0055 */ "", 4164 /* CCS_REG_0058 */ "", 4165 /* CCS_REG_0062 */ "", 4166 /* CCS_REG_0066 */ "", 4167 /* CCS_REG_0080 */ "", 4168 /* CCS_REG_0086 */ "", 4169 /* CCS_REG_0102 */ "", 4170 /* CCS_REG_0112 */ "", 4171 /* CCS_REG_0113 */ "", 4172 /* CCS_REG_0114 */ "", 4173 /* CCS_REG_0118 */ "", 4174 /* CCS_REG_0120 */ "", 4175 /* CCS_REG_0124 */ "", 4176 /* CCS_REG_0125 */ "", 4177 /* CCS_REG_0126 */ "", 4178 /* CCS_REG_0128 */ "", 4179 /* CCS_REG_0140 */ "", 4180 /* CCS_REG_0144 */ "", 4181 /* CCS_REG_0149 */ "", 4182 /* CCS_REG_005A */ "", 4183 /* CCS_REG_005B */ "", 4184 /* CCS_REG_007A */ "", 4185 /* CCS_REG_007B */ "", 4186 /* CCS_REG_007C */ "", 4187 /* CCS_REG_011A */ "", 4188 /* CCS_REG_011B */ "", 4189 /* CCS_REG_011C */ "", 4190 /* CCS_REG_014A */ "", 4191 /* CCS_REG_014B */ "", 4192 /* CCS_REG_01F5 */ "", 4193 /* CCS_REG_01F6 */ "", 4194 /* CCS_REG_01F7 */ "", 4195 /* CCS_REG_01F8 */ "", 4196 /* CCS_REG_01FA */ "", 4197 /* CCS_REG_01FB */ "", 4198 /* CCS_REG_01FC */ "", 4199 /* CCS_REG_01FD */ "", 4200 /* CCS_REG_01FE */ "", 4201 /* CCS_RESERVED_MIRROR_ADDR */ "", 4202 /* CCS_RESERVED_MTCP */ "", 4203 /* CCS_RESERVED_SPARE_0 */ "", 4204 /* CCS_RESERVED_SPARE_1 */ "", 4205 /* CCS_RESERVED_SPARE_2 */ "", 4206 /* CCS_RESERVED_SPARE_3 */ "", 4207 /* CCS_SBUS_BROADCAST_ID */ "", 4208 /* CCS_SBUS_LAST_IN_CHAIN */ "", 4209 /* CCS_SELF_ROUTED_CELLS_CNT */ "", 4210 /* CCS_SOURCE_ROUTED_CELLS_CNT */ "", 4211 /* CCS_SPARE_REGISTER_3 */ "", 4212 /* CCS_TOTAL_CELLS_CNT */ "", 4213 /* CCS_UNREACHABLE_DESTINATION_CELLS_CNT */ "", 4214 /* CCS_VSC_256_LINK_BITMAP_REGISTER */ "", 4215 /* CDMAC_CTRL */ "", 4216 /* CDMAC_ECC_CTRL */ "", 4217 /* CDMAC_ECC_STATUS */ "", 4218 /* CDMAC_FIFO_STATUS */ "", 4219 /* CDMAC_INTR_ENABLE */ "", 4220 /* CDMAC_INTR_STATUS */ "", 4221 /* CDMAC_LAG_FAILOVER_STATUS */ "", 4222 /* CDMAC_LINK_INTR_CTRL */ "", 4223 /* CDMAC_LINK_INTR_STATUS */ "", 4224 /* CDMAC_MEM_CTRL */ "", 4225 /* CDMAC_MIB_COUNTER_CTRL */ "", 4226 /* CDMAC_MIB_COUNTER_MODE */ "", 4227 /* CDMAC_MIB_COUNTER_PROG_RANGE_CNTR0 */ "", 4228 /* CDMAC_MIB_COUNTER_PROG_RANGE_CNTR1 */ "", 4229 /* CDMAC_MIB_COUNTER_PROG_RANGE_CNTR2 */ "", 4230 /* CDMAC_MIB_COUNTER_PROG_RANGE_CNTR3 */ "", 4231 /* CDMAC_MODE */ "", 4232 /* CDMAC_PAUSE_CTRL */ "", 4233 /* CDMAC_PFC_CTRL */ "", 4234 /* CDMAC_PFC_DA */ "", 4235 /* CDMAC_PFC_OPCODE */ "", 4236 /* CDMAC_PFC_TYPE */ "", 4237 /* CDMAC_RSV_MASK */ "", 4238 /* CDMAC_RX_CTRL */ "", 4239 /* CDMAC_RX_LSS_CTRL */ "", 4240 /* CDMAC_RX_LSS_STATUS */ "", 4241 /* CDMAC_RX_MAC_SA */ "", 4242 /* CDMAC_RX_MAX_SIZE */ "", 4243 /* CDMAC_RX_VLAN_TAG */ "", 4244 /* CDMAC_SPARE */ "", 4245 /* CDMAC_TXFIFO_CELL_CNT */ "", 4246 /* CDMAC_TXFIFO_CELL_REQ_CNT */ "", 4247 /* CDMAC_TX_CTRL */ "", 4248 /* CDMAC_TX_MAC_SA */ "", 4249 /* CDMAC_VERSION_ID */ "", 4250 /* CDPORT_FAULT_LINK_STATUS */ "", 4251 /* CDPORT_FLOW_CONTROL_CONFIG */ "", 4252 /* CDPORT_GENERAL_SPARE0_REG */ "", 4253 /* CDPORT_GENERAL_SPARE1_REG */ "", 4254 /* CDPORT_GENERAL_SPARE2_REG */ "", 4255 /* CDPORT_GENERAL_SPARE3_REG */ "", 4256 /* CDPORT_INTR_ENABLE */ "", 4257 /* CDPORT_INTR_STATUS */ "", 4258 /* CDPORT_LAG_FAILOVER_CONFIG */ "", 4259 /* CDPORT_LED_CONTROL */ "", 4260 /* CDPORT_LINKSTATUS_DOWN */ "", 4261 /* CDPORT_MAC_CONTROL */ "", 4262 /* CDPORT_MODE_REG */ "", 4263 /* CDPORT_PM_VERSION_ID */ "", 4264 /* CDPORT_SBUS_CONTROL */ "", 4265 /* CDPORT_SPARE0_REG */ "", 4266 /* CDPORT_SPARE1_REG */ "", 4267 /* CDPORT_SPARE2_REG */ "", 4268 /* CDPORT_SPARE3_REG */ "", 4269 /* CDPORT_SW_FLOW_CONTROL */ "", 4270 /* CDPORT_TSC_INTR_STATUS */ "", 4271 /* CDPORT_TSC_MEM_CTRL */ "", 4272 /* CDPORT_TSC_PLL_LOCK_STATUS */ "", 4273 /* CDPORT_XGXS0_CTRL_REG */ "", 4274 /* CDPORT_XGXS0_LN0_STATUS_REG */ "", 4275 /* CDPORT_XGXS0_LN1_STATUS_REG */ "", 4276 /* CDPORT_XGXS0_LN2_STATUS_REG */ "", 4277 /* CDPORT_XGXS0_LN3_STATUS_REG */ "", 4278 /* CDPORT_XGXS0_LN4_STATUS_REG */ "", 4279 /* CDPORT_XGXS0_LN5_STATUS_REG */ "", 4280 /* CDPORT_XGXS0_LN6_STATUS_REG */ "", 4281 /* CDPORT_XGXS0_LN7_STATUS_REG */ "", 4282 /* CDUM_ALIGNER_DEBUG_DATA_WAIT_AT_GS */ "", 4283 /* CDUM_ALIGNER_DEBUG_FIFO_WR_STATUS_MAX_OCCUPANCY */ "", 4284 /* CDUM_ALIGNER_DEBUG_REG */ "", 4285 /* CDUM_ALIGNER_MEMS_RESET */ "", 4286 /* CDUM_AUTO_DOC_NAME_1 */ "", 4287 /* CDUM_AUTO_DOC_NAME_2 */ "", 4288 /* CDUM_BIST_ERROR_GENERATOR */ "", 4289 /* CDUM_BIST_EVENTS_GENERATOR */ "", 4290 /* CDUM_BIST_EVENTS_STATUS */ "", 4291 /* CDUM_CONTROL_FRAME_CONFIG */ "", 4292 /* CDUM_ECC_1B_ERR_CNT */ "", 4293 /* CDUM_ECC_2B_ERR_CNT */ "", 4294 /* CDUM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 4295 /* CDUM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 4296 /* CDUM_ECC_INTERRUPT_REGISTER */ "", 4297 /* CDUM_ECC_INTERRUPT_REGISTER_MASK */ "", 4298 /* CDUM_ECC_INTERRUPT_REGISTER_TEST */ "", 4299 /* CDUM_EGQ_CRDT_CONFIG */ "", 4300 /* CDUM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 4301 /* CDUM_ERROR_INITIATION_DATA */ "", 4302 /* CDUM_ETH_TX_GEN_LLFC_CNT */ "", 4303 /* CDUM_ETH_TX_LLFC_STOP_TX_CNT */ "", 4304 /* CDUM_FC_BIST */ "", 4305 /* CDUM_FC_CHOOSE_PORT_FOR_ETH_TX */ "", 4306 /* CDUM_FC_CHOOSE_PORT_FOR_PFC */ "", 4307 /* CDUM_FC_GEN_SAFC_REFRESH_TIMER */ "", 4308 /* CDUM_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT */ "", 4309 /* CDUM_FC_LLFC_STOP_TX_FORCE */ "", 4310 /* CDUM_FC_LLFC_STOP_TX_FROM_CFC_MASK */ "", 4311 /* CDUM_FC_MASK_FC_WHEN_LINK_FAIL */ "", 4312 /* CDUM_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC */ "", 4313 /* CDUM_FC_MASK_PFC_PRIO_OF_RMC */ "", 4314 /* CDUM_FC_PFC_CFG */ "", 4315 /* CDUM_FC_PFC_DEBUG_INDICATIONS */ "", 4316 /* CDUM_FC_PFC_RX_BITMAP_MAP_FORCE_EN */ "", 4317 /* CDUM_FC_PFC_RX_BITMAP_TYPE_A */ "", 4318 /* CDUM_FC_PFC_RX_BITMAP_TYPE_B */ "", 4319 /* CDUM_FC_PFC_RX_BITMAP_TYPE_PER_PORT */ "", 4320 /* CDUM_FC_PFC_TX_BITMAP_TYPE_A */ "", 4321 /* CDUM_FC_PFC_TX_BITMAP_TYPE_B */ "", 4322 /* CDUM_FC_PFC_TX_BITMAP_TYPE_C */ "", 4323 /* CDUM_FC_PFC_TX_BITMAP_TYPE_D */ "", 4324 /* CDUM_FC_PFC_TX_BITMAP_TYPE_PER_PORT */ "", 4325 /* CDUM_FC_RESET */ "", 4326 /* CDUM_FC_RX_GEN_LLFC_FROM_QMLF */ "", 4327 /* CDUM_FC_RX_GEN_PFC_FROM_QMLF_PORT */ "", 4328 /* CDUM_FC_TX_GEN_LLFC_FORCE */ "", 4329 /* CDUM_FC_TX_GEN_LLFC_FROM_CFC */ "", 4330 /* CDUM_FC_TX_GEN_LLFC_FROM_CFC_MASK */ "", 4331 /* CDUM_FC_TX_GEN_LLFC_FROM_CFC_OCB_MASK */ "", 4332 /* CDUM_FC_TX_GEN_LLFC_FROM_CFC_PD_MASK */ "", 4333 /* CDUM_FC_TX_GEN_LLFC_TO_PM */ "", 4334 /* CDUM_FC_TX_GEN_PFC_FORCE */ "", 4335 /* CDUM_FC_TX_GEN_PFC_FORCE_MASK */ "", 4336 /* CDUM_FC_TX_LLFC_STOP_TX_FROM_CFC */ "", 4337 /* CDUM_FC_TX_LLFC_STOP_TX_TO_PM */ "", 4338 /* CDUM_FC_TX_LOW_PASS_FILTER */ "", 4339 /* CDUM_FIFO_WRITE_POINTER_QMLF_SELECT */ "", 4340 /* CDUM_FIFO_WRITE_POINTER_RESULT */ "", 4341 /* CDUM_FLUSH_SOP_WITH_ERR_CONFIG */ "", 4342 /* CDUM_GTIMER_CONFIGURATION */ "", 4343 /* CDUM_GTIMER_CYCLE */ "", 4344 /* CDUM_INDIRECT_COMMAND */ "", 4345 /* CDUM_INDIRECT_COMMAND_ADDRESS */ "", 4346 /* CDUM_INDIRECT_COMMAND_RD_DATA */ "", 4347 /* CDUM_INDIRECT_COMMAND_WR_DATA */ "", 4348 /* CDUM_INDIRECT_FORCE_BUBBLE */ "", 4349 /* CDUM_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION */ "", 4350 /* CDUM_INSTRUMENTATION_DEBUG_WRAP_AROUND */ "", 4351 /* CDUM_INSTRUMENTATION_ECI_SIGNALS_COUNTER */ "", 4352 /* CDUM_INSTRUMENTATION_INTERVALS_COUNTER */ "", 4353 /* CDUM_INSTRUMENTATION_LAST_INTERVAL_WRITTEN */ "", 4354 /* CDUM_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED */ "", 4355 /* CDUM_INSTRUMENTATION_OVERRIDE_MODE */ "", 4356 /* CDUM_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT */ "", 4357 /* CDUM_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT */ "", 4358 /* CDUM_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT */ "", 4359 /* CDUM_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT */ "", 4360 /* CDUM_INSTRUMENTATION_PFC_DEBUG_AND_BREAKING_MECHANISM */ "", 4361 /* CDUM_INSTRUMENTATION_RESET_LOW */ "", 4362 /* CDUM_INSTRUMENTATION_RSTN_PFC_CNTS */ "", 4363 /* CDUM_INSTRUMENTATION_RSTN_TRAFFIC_CNTS */ "", 4364 /* CDUM_INSTRUMENTATION_TIME_FACTOR_FOR_PFC_CNTS */ "", 4365 /* CDUM_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT */ "", 4366 /* CDUM_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT */ "", 4367 /* CDUM_INTERRUPT_MASK_REGISTER */ "", 4368 /* CDUM_INTERRUPT_REGISTER */ "", 4369 /* CDUM_INTERRUPT_REGISTER_TEST */ "", 4370 /* CDUM_LAST_RECEIVED_FROM_EGQ_CONTROLS */ "", 4371 /* CDUM_LAST_RECEIVED_FROM_EGQ_DATA */ "", 4372 /* CDUM_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP */ "", 4373 /* CDUM_LAST_RECEIVED_FROM_PARSER_PER_PORT */ "", 4374 /* CDUM_LAST_RECEIVED_FROM_PM_CONTROLS */ "", 4375 /* CDUM_LAST_RECEIVED_FROM_PM_DATA */ "", 4376 /* CDUM_LAST_RECEIVED_FROM_PM_DATA_ON_SOP */ "", 4377 /* CDUM_LAST_SENT_TO_IRE_CONTROLS */ "", 4378 /* CDUM_LAST_SENT_TO_IRE_DATA */ "", 4379 /* CDUM_LAST_SENT_TO_IRE_DATA_ON_SOP */ "", 4380 /* CDUM_LAST_SENT_TO_PM_CONTROLS */ "", 4381 /* CDUM_LAST_SENT_TO_PM_DATA */ "", 4382 /* CDUM_LAST_SENT_TO_PM_DATA_ON_SOP */ "", 4383 /* CDUM_LINK_ACTIVE */ "", 4384 /* CDUM_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER */ "", 4385 /* CDUM_LINK_STATUS_CHANGE_INTERRUPT_REGISTER */ "", 4386 /* CDUM_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST */ "", 4387 /* CDUM_MAC_0_RESET */ "", 4388 /* CDUM_MAC_1_RESET */ "", 4389 /* CDUM_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER */ "", 4390 /* CDUM_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER */ "", 4391 /* CDUM_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST */ "", 4392 /* CDUM_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION */ "", 4393 /* CDUM_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION */ "", 4394 /* CDUM_NIF_PM_EXTERNAL_LPI_INDICATION */ "", 4395 /* CDUM_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION */ "", 4396 /* CDUM_NIF_PM_EXTRA_SAMPLES */ "", 4397 /* CDUM_NIF_PM_ILKN_RX_RSTN */ "", 4398 /* CDUM_NIF_PM_ILKN_TX_RSTN */ "", 4399 /* CDUM_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS */ "", 4400 /* CDUM_NIF_PM_U_RESOLVED_SPEED */ "", 4401 /* CDUM_NIF_TSC_LANE_STATUS */ "", 4402 /* CDUM_PARITY_ERR_CNT */ "", 4403 /* CDUM_PARSER_HARD_CONTROL */ "", 4404 /* CDUM_PARSER_HARD_CONTROL_PLANE */ "", 4405 /* CDUM_PARSER_HARD_ETHER_TYPE */ "", 4406 /* CDUM_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 4407 /* CDUM_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 4408 /* CDUM_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 4409 /* CDUM_PARSER_HARD_PORT_ETH_TPID */ "", 4410 /* CDUM_PARSER_HARD_PORT_PROPERTIES */ "", 4411 /* CDUM_PARSER_HARD_PORT_TYPE */ "", 4412 /* CDUM_PARSER_HARD_SPECIAL_LABEL */ "", 4413 /* CDUM_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 4414 /* CDUM_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES */ "", 4415 /* CDUM_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 4416 /* CDUM_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION */ "", 4417 /* CDUM_PARSER_SOFT_TCAM_0_TO_7 */ "", 4418 /* CDUM_PARSER_SOFT_TCAM_16_TO_23 */ "", 4419 /* CDUM_PARSER_SOFT_TCAM_24_TO_31 */ "", 4420 /* CDUM_PARSER_SOFT_TCAM_8_TO_15 */ "", 4421 /* CDUM_PAR_ERR_MEM_MASK */ "", 4422 /* CDUM_PCMI_0 */ "", 4423 /* CDUM_PCMI_1 */ "", 4424 /* CDUM_PCMI_2 */ "", 4425 /* CDUM_PCMI_3 */ "", 4426 /* CDUM_PCMI_4 */ "", 4427 /* CDUM_PCMI_0_S */ "", 4428 /* CDUM_PCMI_0_T */ "", 4429 /* CDUM_PCMI_1_S */ "", 4430 /* CDUM_PCMI_1_T */ "", 4431 /* CDUM_PCMI_2_S */ "", 4432 /* CDUM_PCMI_2_T */ "", 4433 /* CDUM_PCMI_3_S */ "", 4434 /* CDUM_PCMI_3_T */ "", 4435 /* CDUM_PCMI_4_S */ "", 4436 /* CDUM_PCMI_4_T */ "", 4437 /* CDUM_PM_BYPASS_CONFIG */ "", 4438 /* CDUM_PM_MEM_TEST_CTL_MANUALLY_ADDED */ "", 4439 /* CDUM_PM_TX_PLL_LOCK_STATUS */ "", 4440 /* CDUM_PORTS_CONFIG */ "", 4441 /* CDUM_PORTS_INDICATIONS */ "", 4442 /* CDUM_PRD_BYPASS */ "", 4443 /* CDUM_PRD_CONFIG */ "", 4444 /* CDUM_PRD_EN */ "", 4445 /* CDUM_PRD_ERR_PKT_DROP_CNT_PORT */ "", 4446 /* CDUM_PRD_OVERRIDES */ "", 4447 /* CDUM_PRD_PKT_DROP_CNT_PORT */ "", 4448 /* CDUM_REG_0041 */ "", 4449 /* CDUM_REG_00A4 */ "", 4450 /* CDUM_REG_00A6 */ "", 4451 /* CDUM_REG_00AA */ "", 4452 /* CDUM_REG_00C2 */ "", 4453 /* CDUM_REG_00C4 */ "", 4454 /* CDUM_RESERVED_MIRROR_ADDR */ "", 4455 /* CDUM_RESERVED_MTCD */ "", 4456 /* CDUM_RESERVED_MTCP */ "", 4457 /* CDUM_RESERVED_SPARE_0 */ "", 4458 /* CDUM_RESERVED_SPARE_1 */ "", 4459 /* CDUM_RESERVED_SPARE_2 */ "", 4460 /* CDUM_RESERVED_SPARE_3 */ "", 4461 /* CDUM_RUNT_PKT_CONFIG */ "", 4462 /* CDUM_RX_FIFOS_SRSTN */ "", 4463 /* CDUM_RX_FIFOS_VECTOR_PER_PORT */ "", 4464 /* CDUM_RX_FIFO_RANGE_RMC_0 */ "", 4465 /* CDUM_RX_FIFO_RANGE_RMC_1 */ "", 4466 /* CDUM_RX_FIFO_RANGE_RMC_2 */ "", 4467 /* CDUM_RX_FIFO_RANGE_RMC_3 */ "", 4468 /* CDUM_RX_FIFO_RANGE_RMC_4 */ "", 4469 /* CDUM_RX_FIFO_RANGE_RMC_5 */ "", 4470 /* CDUM_RX_FIFO_RANGE_RMC_6 */ "", 4471 /* CDUM_RX_FIFO_RANGE_RMC_7 */ "", 4472 /* CDUM_RX_FIFO_RANGE_RMC_8 */ "", 4473 /* CDUM_RX_FIFO_RANGE_RMC_9 */ "", 4474 /* CDUM_RX_FIFO_RANGE_RMC_10 */ "", 4475 /* CDUM_RX_FIFO_RANGE_RMC_11 */ "", 4476 /* CDUM_RX_FIFO_RANGE_RMC_12 */ "", 4477 /* CDUM_RX_FIFO_RANGE_RMC_13 */ "", 4478 /* CDUM_RX_FIFO_RANGE_RMC_14 */ "", 4479 /* CDUM_RX_FIFO_RANGE_RMC_15 */ "", 4480 /* CDUM_RX_MISS_EOP_ERR_COUNTER */ "", 4481 /* CDUM_RX_MISS_SOP_ERR_COUNTER */ "", 4482 /* CDUM_RX_MLF_CONFIG */ "", 4483 /* CDUM_RX_MLF_CTRL_PKT_DROP */ "", 4484 /* CDUM_RX_MLF_DROP_ALL_DATA */ "", 4485 /* CDUM_RX_MLF_LEVEL */ "", 4486 /* CDUM_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC */ "", 4487 /* CDUM_RX_MLF_MAX_OCCUPANCY */ "", 4488 /* CDUM_RX_MLF_OVERFLOW */ "", 4489 /* CDUM_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC */ "", 4490 /* CDUM_RX_MLF_UNDERFLOW */ "", 4491 /* CDUM_RX_NUM_TOTAL_DROPPED_EOPS */ "", 4492 /* CDUM_RX_PKT_CTRL_DROP_COUNTER */ "", 4493 /* CDUM_RX_PKT_CTRL_NON_DROP_COUNTER */ "", 4494 /* CDUM_RX_PKT_DROP_COUNTER */ "", 4495 /* CDUM_RX_PKT_OVF_DROP_COUNTER */ "", 4496 /* CDUM_RX_PKT_PRD_DROP_COUNTER */ "", 4497 /* CDUM_RX_PORT_0_MAP_TO_RMC */ "", 4498 /* CDUM_RX_PORT_1_MAP_TO_RMC */ "", 4499 /* CDUM_RX_PORT_2_MAP_TO_RMC */ "", 4500 /* CDUM_RX_PORT_3_MAP_TO_RMC */ "", 4501 /* CDUM_RX_PORT_4_MAP_TO_RMC */ "", 4502 /* CDUM_RX_PORT_5_MAP_TO_RMC */ "", 4503 /* CDUM_RX_PORT_6_MAP_TO_RMC */ "", 4504 /* CDUM_RX_PORT_7_MAP_TO_RMC */ "", 4505 /* CDUM_RX_PORT_MAP_IS_INVALID */ "", 4506 /* CDUM_RX_PORT_MAP_IS_INVALID_PARAM */ "", 4507 /* CDUM_RX_PORT_OVF */ "", 4508 /* CDUM_RX_RMC_0_MAP */ "", 4509 /* CDUM_RX_RMC_0_PRD_THRESHOLDS_CONFIG */ "", 4510 /* CDUM_RX_RMC_10_MAP */ "", 4511 /* CDUM_RX_RMC_10_PRD_THRESHOLDS_CONFIG */ "", 4512 /* CDUM_RX_RMC_11_MAP */ "", 4513 /* CDUM_RX_RMC_11_PRD_THRESHOLDS_CONFIG */ "", 4514 /* CDUM_RX_RMC_12_MAP */ "", 4515 /* CDUM_RX_RMC_12_PRD_THRESHOLDS_CONFIG */ "", 4516 /* CDUM_RX_RMC_13_MAP */ "", 4517 /* CDUM_RX_RMC_13_PRD_THRESHOLDS_CONFIG */ "", 4518 /* CDUM_RX_RMC_14_MAP */ "", 4519 /* CDUM_RX_RMC_14_PRD_THRESHOLDS_CONFIG */ "", 4520 /* CDUM_RX_RMC_15_MAP */ "", 4521 /* CDUM_RX_RMC_15_PRD_THRESHOLDS_CONFIG */ "", 4522 /* CDUM_RX_RMC_1_MAP */ "", 4523 /* CDUM_RX_RMC_1_PRD_THRESHOLDS_CONFIG */ "", 4524 /* CDUM_RX_RMC_2_MAP */ "", 4525 /* CDUM_RX_RMC_2_PRD_THRESHOLDS_CONFIG */ "", 4526 /* CDUM_RX_RMC_3_MAP */ "", 4527 /* CDUM_RX_RMC_3_PRD_THRESHOLDS_CONFIG */ "", 4528 /* CDUM_RX_RMC_4_MAP */ "", 4529 /* CDUM_RX_RMC_4_PRD_THRESHOLDS_CONFIG */ "", 4530 /* CDUM_RX_RMC_5_MAP */ "", 4531 /* CDUM_RX_RMC_5_PRD_THRESHOLDS_CONFIG */ "", 4532 /* CDUM_RX_RMC_6_MAP */ "", 4533 /* CDUM_RX_RMC_6_PRD_THRESHOLDS_CONFIG */ "", 4534 /* CDUM_RX_RMC_7_MAP */ "", 4535 /* CDUM_RX_RMC_7_PRD_THRESHOLDS_CONFIG */ "", 4536 /* CDUM_RX_RMC_8_MAP */ "", 4537 /* CDUM_RX_RMC_8_PRD_THRESHOLDS_CONFIG */ "", 4538 /* CDUM_RX_RMC_9_MAP */ "", 4539 /* CDUM_RX_RMC_9_PRD_THRESHOLDS_CONFIG */ "", 4540 /* CDUM_RX_RMC_MAP_TO_PORT_IS_INVALID */ "", 4541 /* CDUM_RX_RUNT_PKT_COUNTER */ "", 4542 /* CDUM_RX_SMALL_PKT_ERR_DROP_COUNTER */ "", 4543 /* CDUM_RX_TDM_BYTE_COUNTER */ "", 4544 /* CDUM_RX_TDM_PKT_COUNTER */ "", 4545 /* CDUM_RX_THRESHOLD_AFTER_OVERFLOW_RMC */ "", 4546 /* CDUM_RX_TOTAL_BYTE_COUNTER */ "", 4547 /* CDUM_RX_TOTAL_BYTE_WITH_ERR_COUNTER */ "", 4548 /* CDUM_RX_TOTAL_PKT_COUNTER */ "", 4549 /* CDUM_RX_TOTAL_PKT_WITH_ERR_COUNTER */ "", 4550 /* CDUM_SBUS_BROADCAST_ID */ "", 4551 /* CDUM_SBUS_LAST_IN_CHAIN */ "", 4552 /* CDUM_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT */ "", 4553 /* CDUM_SYNC_ETH_CFG */ "", 4554 /* CDUM_SYNC_ETH_DEBUG */ "", 4555 /* CDUM_TX_EGRESS_CREDITS_DEBUG_PM */ "", 4556 /* CDUM_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE */ "", 4557 /* CDUM_TX_FIFO_FLUSH_AND_STOP_TOOL */ "", 4558 /* CDUM_TX_MLF_CONFIG */ "", 4559 /* CDUM_TX_MLF_ERR_ON_MOP_FROM_EGQ */ "", 4560 /* CDUM_TX_MLF_FIFO_FLUSH */ "", 4561 /* CDUM_TX_MLF_LEVEL_PM */ "", 4562 /* CDUM_TX_MLF_MAX_OCCUPANCY */ "", 4563 /* CDUM_TX_MLF_NUM_CREDITS_FROM_PM */ "", 4564 /* CDUM_TX_MLF_OVERFLOW_PM */ "", 4565 /* CDUM_TX_NO_DATA_IN_BUFFER */ "", 4566 /* CDUM_TX_PORTS_CONFIG */ "", 4567 /* CDUM_TX_PORTS_SRSTN */ "", 4568 /* CDUM_TX_PORT_OVF */ "", 4569 /* CDUM_TX_QMLF_CONFIG */ "", 4570 /* CDUM_TX_TMC_RATE_LIMITER_LEVEL */ "", 4571 /* CDUM_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY */ "", 4572 /* CDUM_TX_TOTAL_BYTE_COUNTER */ "", 4573 /* CDUM_TX_TOTAL_BYTE_WITH_ERR_COUNTER */ "", 4574 /* CDUM_TX_TOTAL_ERR_ON_SOP_BYTE_COUNTER */ "", 4575 /* CDUM_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER */ "", 4576 /* CDUM_TX_TOTAL_PKT_COUNTER */ "", 4577 /* CDUM_TX_TOTAL_PKT_WITH_ERR_COUNTER */ "", 4578 /* CDUM_TX_WRONG_PORT_FROM_EGQ_QMLF */ "", 4579 /* CDU_ALIGNER_DEBUG_DATA_WAIT_AT_GS */ "", 4580 /* CDU_ALIGNER_DEBUG_FIFO_WR_STATUS_MAX_OCCUPANCY */ "", 4581 /* CDU_ALIGNER_DEBUG_REG */ "", 4582 /* CDU_ALIGNER_MEMS_RESET */ "", 4583 /* CDU_AUTO_DOC_NAME_1 */ "", 4584 /* CDU_AUTO_DOC_NAME_2 */ "", 4585 /* CDU_BIST_ERROR_GENERATOR */ "", 4586 /* CDU_BIST_EVENTS_GENERATOR */ "", 4587 /* CDU_BIST_EVENTS_STATUS */ "", 4588 /* CDU_CONTROL_FRAME_CONFIG */ "", 4589 /* CDU_ECC_1B_ERR_CNT */ "", 4590 /* CDU_ECC_2B_ERR_CNT */ "", 4591 /* CDU_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 4592 /* CDU_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 4593 /* CDU_ECC_INTERRUPT_REGISTER */ "", 4594 /* CDU_ECC_INTERRUPT_REGISTER_MASK */ "", 4595 /* CDU_ECC_INTERRUPT_REGISTER_TEST */ "", 4596 /* CDU_EGQ_CRDT_CONFIG */ "", 4597 /* CDU_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 4598 /* CDU_ERROR_INITIATION_DATA */ "", 4599 /* CDU_ETH_TX_GEN_LLFC_CNT */ "", 4600 /* CDU_ETH_TX_LLFC_STOP_TX_CNT */ "", 4601 /* CDU_FC_BIST */ "", 4602 /* CDU_FC_CHOOSE_PORT_FOR_ETH_TX */ "", 4603 /* CDU_FC_CHOOSE_PORT_FOR_PFC */ "", 4604 /* CDU_FC_GEN_SAFC_REFRESH_TIMER */ "", 4605 /* CDU_FC_LLFC_RX_FIFOS_VECTOR_MASK_PER_PORT */ "", 4606 /* CDU_FC_LLFC_STOP_TX_FORCE */ "", 4607 /* CDU_FC_LLFC_STOP_TX_FROM_CFC_MASK */ "", 4608 /* CDU_FC_MASK_FC_WHEN_LINK_FAIL */ "", 4609 /* CDU_FC_MASK_PFC_FROM_LLFC_PRIO_OF_RMC */ "", 4610 /* CDU_FC_MASK_PFC_PRIO_OF_RMC */ "", 4611 /* CDU_FC_PFC_CFG */ "", 4612 /* CDU_FC_PFC_DEBUG_INDICATIONS */ "", 4613 /* CDU_FC_PFC_RX_BITMAP_MAP_FORCE_EN */ "", 4614 /* CDU_FC_PFC_RX_BITMAP_TYPE_A */ "", 4615 /* CDU_FC_PFC_RX_BITMAP_TYPE_B */ "", 4616 /* CDU_FC_PFC_RX_BITMAP_TYPE_PER_PORT */ "", 4617 /* CDU_FC_PFC_TX_BITMAP_TYPE_A */ "", 4618 /* CDU_FC_PFC_TX_BITMAP_TYPE_B */ "", 4619 /* CDU_FC_PFC_TX_BITMAP_TYPE_C */ "", 4620 /* CDU_FC_PFC_TX_BITMAP_TYPE_D */ "", 4621 /* CDU_FC_PFC_TX_BITMAP_TYPE_PER_PORT */ "", 4622 /* CDU_FC_RESET */ "", 4623 /* CDU_FC_RX_GEN_LLFC_FROM_QMLF */ "", 4624 /* CDU_FC_RX_GEN_PFC_FROM_QMLF_PORT */ "", 4625 /* CDU_FC_TX_GEN_LLFC_FORCE */ "", 4626 /* CDU_FC_TX_GEN_LLFC_FROM_CFC */ "", 4627 /* CDU_FC_TX_GEN_LLFC_FROM_CFC_MASK */ "", 4628 /* CDU_FC_TX_GEN_LLFC_FROM_CFC_OCB_MASK */ "", 4629 /* CDU_FC_TX_GEN_LLFC_FROM_CFC_PD_MASK */ "", 4630 /* CDU_FC_TX_GEN_LLFC_TO_PM */ "", 4631 /* CDU_FC_TX_GEN_PFC_FORCE */ "", 4632 /* CDU_FC_TX_GEN_PFC_FORCE_MASK */ "", 4633 /* CDU_FC_TX_LLFC_STOP_TX_FROM_CFC */ "", 4634 /* CDU_FC_TX_LLFC_STOP_TX_TO_PM */ "", 4635 /* CDU_FC_TX_LOW_PASS_FILTER */ "", 4636 /* CDU_FIFO_WRITE_POINTER_QMLF_SELECT */ "", 4637 /* CDU_FIFO_WRITE_POINTER_RESULT */ "", 4638 /* CDU_FLUSH_SOP_WITH_ERR_CONFIG */ "", 4639 /* CDU_GTIMER_CONFIGURATION */ "", 4640 /* CDU_GTIMER_CYCLE */ "", 4641 /* CDU_INDIRECT_COMMAND */ "", 4642 /* CDU_INDIRECT_COMMAND_ADDRESS */ "", 4643 /* CDU_INDIRECT_COMMAND_RD_DATA */ "", 4644 /* CDU_INDIRECT_COMMAND_WR_DATA */ "", 4645 /* CDU_INDIRECT_FORCE_BUBBLE */ "", 4646 /* CDU_INSTRUMENTATION_DEBUG_MODE_DISABLE_INSTRUMENTATION */ "", 4647 /* CDU_INSTRUMENTATION_DEBUG_WRAP_AROUND */ "", 4648 /* CDU_INSTRUMENTATION_ECI_SIGNALS_COUNTER */ "", 4649 /* CDU_INSTRUMENTATION_INTERVALS_COUNTER */ "", 4650 /* CDU_INSTRUMENTATION_LAST_INTERVAL_WRITTEN */ "", 4651 /* CDU_INSTRUMENTATION_NUMBER_OF_INTERVALS_USED */ "", 4652 /* CDU_INSTRUMENTATION_OVERRIDE_MODE */ "", 4653 /* CDU_INSTRUMENTATION_PFC_0_TO_1_DATA_CURRENT_INTERVAL_PORT */ "", 4654 /* CDU_INSTRUMENTATION_PFC_2_TO_3_DATA_CURRENT_INTERVAL_PORT */ "", 4655 /* CDU_INSTRUMENTATION_PFC_4_TO_5_DATA_CURRENT_INTERVAL_PORT */ "", 4656 /* CDU_INSTRUMENTATION_PFC_6_TO_7_DATA_CURRENT_INTERVAL_PORT */ "", 4657 /* CDU_INSTRUMENTATION_PFC_DEBUG_AND_BREAKING_MECHANISM */ "", 4658 /* CDU_INSTRUMENTATION_RESET_LOW */ "", 4659 /* CDU_INSTRUMENTATION_RSTN_PFC_CNTS */ "", 4660 /* CDU_INSTRUMENTATION_RSTN_TRAFFIC_CNTS */ "", 4661 /* CDU_INSTRUMENTATION_TIME_FACTOR_FOR_PFC_CNTS */ "", 4662 /* CDU_INSTRUMENTATION_TRAFFIC_DATA_CURRENT_INTERVAL_PORT */ "", 4663 /* CDU_INSTRUMENTATION_TRAFFIC_DROPPED_DATA_CURRENT_INTERVAL_PORT */ "", 4664 /* CDU_INTERRUPT_MASK_REGISTER */ "", 4665 /* CDU_INTERRUPT_REGISTER */ "", 4666 /* CDU_INTERRUPT_REGISTER_TEST */ "", 4667 /* CDU_LAST_RECEIVED_FROM_EGQ_CONTROLS */ "", 4668 /* CDU_LAST_RECEIVED_FROM_EGQ_DATA */ "", 4669 /* CDU_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP */ "", 4670 /* CDU_LAST_RECEIVED_FROM_PARSER_PER_PORT */ "", 4671 /* CDU_LAST_RECEIVED_FROM_PM_CONTROLS */ "", 4672 /* CDU_LAST_RECEIVED_FROM_PM_DATA */ "", 4673 /* CDU_LAST_RECEIVED_FROM_PM_DATA_ON_SOP */ "", 4674 /* CDU_LAST_SENT_TO_IRE_CONTROLS */ "", 4675 /* CDU_LAST_SENT_TO_IRE_DATA */ "", 4676 /* CDU_LAST_SENT_TO_IRE_DATA_ON_SOP */ "", 4677 /* CDU_LAST_SENT_TO_PM_CONTROLS */ "", 4678 /* CDU_LAST_SENT_TO_PM_DATA */ "", 4679 /* CDU_LAST_SENT_TO_PM_DATA_ON_SOP */ "", 4680 /* CDU_LINK_ACTIVE */ "", 4681 /* CDU_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER */ "", 4682 /* CDU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER */ "", 4683 /* CDU_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST */ "", 4684 /* CDU_MAC_0_RESET */ "", 4685 /* CDU_MAC_1_RESET */ "", 4686 /* CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER */ "", 4687 /* CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER */ "", 4688 /* CDU_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST */ "", 4689 /* CDU_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION */ "", 4690 /* CDU_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION */ "", 4691 /* CDU_NIF_PM_EXTERNAL_LPI_INDICATION */ "", 4692 /* CDU_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION */ "", 4693 /* CDU_NIF_PM_EXTRA_SAMPLES */ "", 4694 /* CDU_NIF_PM_ILKN_RX_RSTN */ "", 4695 /* CDU_NIF_PM_ILKN_TX_RSTN */ "", 4696 /* CDU_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS */ "", 4697 /* CDU_NIF_PM_U_RESOLVED_SPEED */ "", 4698 /* CDU_NIF_TSC_LANE_STATUS */ "", 4699 /* CDU_PARITY_ERR_CNT */ "", 4700 /* CDU_PARSER_HARD_CONTROL */ "", 4701 /* CDU_PARSER_HARD_CONTROL_PLANE */ "", 4702 /* CDU_PARSER_HARD_ETHER_TYPE */ "", 4703 /* CDU_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 4704 /* CDU_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 4705 /* CDU_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 4706 /* CDU_PARSER_HARD_PORT_ETH_TPID */ "", 4707 /* CDU_PARSER_HARD_PORT_PROPERTIES */ "", 4708 /* CDU_PARSER_HARD_PORT_TYPE */ "", 4709 /* CDU_PARSER_HARD_SPECIAL_LABEL */ "", 4710 /* CDU_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 4711 /* CDU_PARSER_SOFT_AFTER_ETH_PROTOCOL_HEADER_SIZE_IN_BYTES */ "", 4712 /* CDU_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 4713 /* CDU_PARSER_SOFT_PROTOCOL_KEY_CONSTRUCTION */ "", 4714 /* CDU_PARSER_SOFT_TCAM_0_TO_7 */ "", 4715 /* CDU_PARSER_SOFT_TCAM_16_TO_23 */ "", 4716 /* CDU_PARSER_SOFT_TCAM_24_TO_31 */ "", 4717 /* CDU_PARSER_SOFT_TCAM_8_TO_15 */ "", 4718 /* CDU_PAR_ERR_MEM_MASK */ "", 4719 /* CDU_PCMI_0 */ "", 4720 /* CDU_PCMI_1 */ "", 4721 /* CDU_PCMI_2 */ "", 4722 /* CDU_PCMI_3 */ "", 4723 /* CDU_PCMI_4 */ "", 4724 /* CDU_PCMI_0_S */ "", 4725 /* CDU_PCMI_0_T */ "", 4726 /* CDU_PCMI_1_S */ "", 4727 /* CDU_PCMI_1_T */ "", 4728 /* CDU_PCMI_2_S */ "", 4729 /* CDU_PCMI_2_T */ "", 4730 /* CDU_PCMI_3_S */ "", 4731 /* CDU_PCMI_3_T */ "", 4732 /* CDU_PCMI_4_S */ "", 4733 /* CDU_PCMI_4_T */ "", 4734 /* CDU_PM_BYPASS_CONFIG */ "", 4735 /* CDU_PM_MEM_TEST_CTL_MANUALLY_ADDED */ "", 4736 /* CDU_PM_TX_PLL_LOCK_STATUS */ "", 4737 /* CDU_PORTS_CONFIG */ "", 4738 /* CDU_PORTS_INDICATIONS */ "", 4739 /* CDU_PRD_BYPASS */ "", 4740 /* CDU_PRD_CONFIG */ "", 4741 /* CDU_PRD_EN */ "", 4742 /* CDU_PRD_ERR_PKT_DROP_CNT_PORT */ "", 4743 /* CDU_PRD_OVERRIDES */ "", 4744 /* CDU_PRD_PKT_DROP_CNT_PORT */ "", 4745 /* CDU_REG_0041 */ "", 4746 /* CDU_REG_00A4 */ "", 4747 /* CDU_REG_00A6 */ "", 4748 /* CDU_REG_00AA */ "", 4749 /* CDU_REG_00C2 */ "", 4750 /* CDU_REG_00C4 */ "", 4751 /* CDU_RESERVED_MIRROR_ADDR */ "", 4752 /* CDU_RESERVED_MTCD */ "", 4753 /* CDU_RESERVED_MTCP */ "", 4754 /* CDU_RESERVED_SPARE_0 */ "", 4755 /* CDU_RESERVED_SPARE_1 */ "", 4756 /* CDU_RESERVED_SPARE_2 */ "", 4757 /* CDU_RESERVED_SPARE_3 */ "", 4758 /* CDU_RUNT_PKT_CONFIG */ "", 4759 /* CDU_RX_FIFOS_SRSTN */ "", 4760 /* CDU_RX_FIFOS_VECTOR_PER_PORT */ "", 4761 /* CDU_RX_FIFO_RANGE_RMC_0 */ "", 4762 /* CDU_RX_FIFO_RANGE_RMC_1 */ "", 4763 /* CDU_RX_FIFO_RANGE_RMC_2 */ "", 4764 /* CDU_RX_FIFO_RANGE_RMC_3 */ "", 4765 /* CDU_RX_FIFO_RANGE_RMC_4 */ "", 4766 /* CDU_RX_FIFO_RANGE_RMC_5 */ "", 4767 /* CDU_RX_FIFO_RANGE_RMC_6 */ "", 4768 /* CDU_RX_FIFO_RANGE_RMC_7 */ "", 4769 /* CDU_RX_FIFO_RANGE_RMC_8 */ "", 4770 /* CDU_RX_FIFO_RANGE_RMC_9 */ "", 4771 /* CDU_RX_FIFO_RANGE_RMC_10 */ "", 4772 /* CDU_RX_FIFO_RANGE_RMC_11 */ "", 4773 /* CDU_RX_FIFO_RANGE_RMC_12 */ "", 4774 /* CDU_RX_FIFO_RANGE_RMC_13 */ "", 4775 /* CDU_RX_FIFO_RANGE_RMC_14 */ "", 4776 /* CDU_RX_FIFO_RANGE_RMC_15 */ "", 4777 /* CDU_RX_MISS_EOP_ERR_COUNTER */ "", 4778 /* CDU_RX_MISS_SOP_ERR_COUNTER */ "", 4779 /* CDU_RX_MLF_CONFIG */ "", 4780 /* CDU_RX_MLF_CTRL_PKT_DROP */ "", 4781 /* CDU_RX_MLF_DROP_ALL_DATA */ "", 4782 /* CDU_RX_MLF_LEVEL */ "", 4783 /* CDU_RX_MLF_LLFC_THRESHOLDS_CONFIG_RMC */ "", 4784 /* CDU_RX_MLF_MAX_OCCUPANCY */ "", 4785 /* CDU_RX_MLF_OVERFLOW */ "", 4786 /* CDU_RX_MLF_PFC_THRESHOLDS_CONFIG_RMC */ "", 4787 /* CDU_RX_MLF_UNDERFLOW */ "", 4788 /* CDU_RX_NUM_TOTAL_DROPPED_EOPS */ "", 4789 /* CDU_RX_PKT_CTRL_DROP_COUNTER */ "", 4790 /* CDU_RX_PKT_CTRL_NON_DROP_COUNTER */ "", 4791 /* CDU_RX_PKT_DROP_COUNTER */ "", 4792 /* CDU_RX_PKT_OVF_DROP_COUNTER */ "", 4793 /* CDU_RX_PKT_PRD_DROP_COUNTER */ "", 4794 /* CDU_RX_PORT_0_MAP_TO_RMC */ "", 4795 /* CDU_RX_PORT_1_MAP_TO_RMC */ "", 4796 /* CDU_RX_PORT_2_MAP_TO_RMC */ "", 4797 /* CDU_RX_PORT_3_MAP_TO_RMC */ "", 4798 /* CDU_RX_PORT_4_MAP_TO_RMC */ "", 4799 /* CDU_RX_PORT_5_MAP_TO_RMC */ "", 4800 /* CDU_RX_PORT_6_MAP_TO_RMC */ "", 4801 /* CDU_RX_PORT_7_MAP_TO_RMC */ "", 4802 /* CDU_RX_PORT_MAP_IS_INVALID */ "", 4803 /* CDU_RX_PORT_MAP_IS_INVALID_PARAM */ "", 4804 /* CDU_RX_PORT_OVF */ "", 4805 /* CDU_RX_RMC_0_MAP */ "", 4806 /* CDU_RX_RMC_0_PRD_THRESHOLDS_CONFIG */ "", 4807 /* CDU_RX_RMC_10_MAP */ "", 4808 /* CDU_RX_RMC_10_PRD_THRESHOLDS_CONFIG */ "", 4809 /* CDU_RX_RMC_11_MAP */ "", 4810 /* CDU_RX_RMC_11_PRD_THRESHOLDS_CONFIG */ "", 4811 /* CDU_RX_RMC_12_MAP */ "", 4812 /* CDU_RX_RMC_12_PRD_THRESHOLDS_CONFIG */ "", 4813 /* CDU_RX_RMC_13_MAP */ "", 4814 /* CDU_RX_RMC_13_PRD_THRESHOLDS_CONFIG */ "", 4815 /* CDU_RX_RMC_14_MAP */ "", 4816 /* CDU_RX_RMC_14_PRD_THRESHOLDS_CONFIG */ "", 4817 /* CDU_RX_RMC_15_MAP */ "", 4818 /* CDU_RX_RMC_15_PRD_THRESHOLDS_CONFIG */ "", 4819 /* CDU_RX_RMC_1_MAP */ "", 4820 /* CDU_RX_RMC_1_PRD_THRESHOLDS_CONFIG */ "", 4821 /* CDU_RX_RMC_2_MAP */ "", 4822 /* CDU_RX_RMC_2_PRD_THRESHOLDS_CONFIG */ "", 4823 /* CDU_RX_RMC_3_MAP */ "", 4824 /* CDU_RX_RMC_3_PRD_THRESHOLDS_CONFIG */ "", 4825 /* CDU_RX_RMC_4_MAP */ "", 4826 /* CDU_RX_RMC_4_PRD_THRESHOLDS_CONFIG */ "", 4827 /* CDU_RX_RMC_5_MAP */ "", 4828 /* CDU_RX_RMC_5_PRD_THRESHOLDS_CONFIG */ "", 4829 /* CDU_RX_RMC_6_MAP */ "", 4830 /* CDU_RX_RMC_6_PRD_THRESHOLDS_CONFIG */ "", 4831 /* CDU_RX_RMC_7_MAP */ "", 4832 /* CDU_RX_RMC_7_PRD_THRESHOLDS_CONFIG */ "", 4833 /* CDU_RX_RMC_8_MAP */ "", 4834 /* CDU_RX_RMC_8_PRD_THRESHOLDS_CONFIG */ "", 4835 /* CDU_RX_RMC_9_MAP */ "", 4836 /* CDU_RX_RMC_9_PRD_THRESHOLDS_CONFIG */ "", 4837 /* CDU_RX_RMC_MAP_TO_PORT_IS_INVALID */ "", 4838 /* CDU_RX_RUNT_PKT_COUNTER */ "", 4839 /* CDU_RX_SMALL_PKT_ERR_DROP_COUNTER */ "", 4840 /* CDU_RX_TDM_BYTE_COUNTER */ "", 4841 /* CDU_RX_TDM_PKT_COUNTER */ "", 4842 /* CDU_RX_THRESHOLD_AFTER_OVERFLOW_RMC */ "", 4843 /* CDU_RX_TOTAL_BYTE_COUNTER */ "", 4844 /* CDU_RX_TOTAL_BYTE_WITH_ERR_COUNTER */ "", 4845 /* CDU_RX_TOTAL_PKT_COUNTER */ "", 4846 /* CDU_RX_TOTAL_PKT_WITH_ERR_COUNTER */ "", 4847 /* CDU_SBUS_BROADCAST_ID */ "", 4848 /* CDU_SBUS_LAST_IN_CHAIN */ "", 4849 /* CDU_SCH_RD_EN_WITHOUT_RD_EN_PER_RMC_CNT */ "", 4850 /* CDU_SYNC_ETH_CFG */ "", 4851 /* CDU_SYNC_ETH_DEBUG */ "", 4852 /* CDU_TX_EGRESS_CREDITS_DEBUG_PM */ "", 4853 /* CDU_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE */ "", 4854 /* CDU_TX_FIFO_FLUSH_AND_STOP_TOOL */ "", 4855 /* CDU_TX_MLF_CONFIG */ "", 4856 /* CDU_TX_MLF_ERR_ON_MOP_FROM_EGQ */ "", 4857 /* CDU_TX_MLF_FIFO_FLUSH */ "", 4858 /* CDU_TX_MLF_LEVEL_PM */ "", 4859 /* CDU_TX_MLF_MAX_OCCUPANCY */ "", 4860 /* CDU_TX_MLF_NUM_CREDITS_FROM_PM */ "", 4861 /* CDU_TX_MLF_OVERFLOW_PM */ "", 4862 /* CDU_TX_NO_DATA_IN_BUFFER */ "", 4863 /* CDU_TX_PORTS_CONFIG */ "", 4864 /* CDU_TX_PORTS_SRSTN */ "", 4865 /* CDU_TX_PORT_OVF */ "", 4866 /* CDU_TX_QMLF_CONFIG */ "", 4867 /* CDU_TX_TMC_RATE_LIMITER_LEVEL */ "", 4868 /* CDU_TX_TMC_RATE_LIMITER_LEVEL_MAX_OCCUPANCY */ "", 4869 /* CDU_TX_TOTAL_BYTE_COUNTER */ "", 4870 /* CDU_TX_TOTAL_BYTE_WITH_ERR_COUNTER */ "", 4871 /* CDU_TX_TOTAL_ERR_ON_SOP_BYTE_COUNTER */ "", 4872 /* CDU_TX_TOTAL_ERR_ON_SOP_PKT_COUNTER */ "", 4873 /* CDU_TX_TOTAL_PKT_COUNTER */ "", 4874 /* CDU_TX_TOTAL_PKT_WITH_ERR_COUNTER */ "", 4875 /* CDU_TX_WRONG_PORT_FROM_EGQ_QMLF */ "", 4876 /* CELLCHKMEMDEBUG */ "", 4877 /* CELLCHK_POWERDOWN_S0 */ "", 4878 /* CELLCHK_POWERDOWN_S1 */ "", 4879 /* CELLCHK_POWERDOWN_S2 */ "", 4880 /* CELLLINKEMEMDEBUG */ "", 4881 /* CELLLINKEMEMDEBUG0 */ "", 4882 /* CELLLINKEMEMDEBUG1 */ "", 4883 /* CELLLINKIMEMDEBUG */ "", 4884 /* CELLLINKMEMDEBUG */ "", 4885 /* CELL_ASM_0_CONTROL */ "", 4886 /* CELL_ASM_CUT_THRU_THRESHOLD */ "", 4887 /* CELL_ASM_CUT_THRU_THRESHOLD0 */ "", 4888 /* CELL_BUFFER0_ECC_STATUS */ "", 4889 /* CELL_BUFFER1_ECC_STATUS */ "", 4890 /* CELL_BUFFER2_ECC_STATUS */ "", 4891 /* CELL_BUFFER3_ECC_STATUS */ "", 4892 /* CELL_BUFFER_PTR_STATUS */ "", 4893 /* CELL_LINK_MEM_DEBUG_TM */ "", 4894 /* CELL_QUEUE_ECC_STATUS_INTR */ "", 4895 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE0 */ "", 4896 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE1 */ "", 4897 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE2 */ "", 4898 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE3 */ "", 4899 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE4 */ "", 4900 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE5 */ "", 4901 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE6 */ "", 4902 /* CELL_QUEUE_ECC_STATUS_INTR_PIPE7 */ "", 4903 /* CELL_RESET_LIMIT_OFFSET_SP */ "", 4904 /* CELL_SPAP_RED_OFFSET_SP */ "", 4905 /* CELL_SPAP_YELLOW_OFFSET_SP */ "", 4906 /* CENTRAL_CTR_EVICTION_CONTROL */ "", 4907 /* CENTRAL_CTR_EVICTION_COUNTER_FLAG */ "", 4908 /* CENTRAL_CTR_EVICTION_FIFO_PARITY_CONTROL */ "", 4909 /* CENTRAL_CTR_EVICTION_FIFO_PARITY_ERROR */ "", 4910 /* CENTRAL_CTR_EVICTION_FIFO_RAM_CONTROL */ "", 4911 /* CENTRAL_CTR_EVICTION_FIFO_STATUS */ "", 4912 /* CENTRAL_CTR_EVICTION_INTR_ENABLE */ "", 4913 /* CENTRAL_CTR_EVICTION_INTR_STATUS */ "", 4914 /* CFAPBANK0STATUS */ "", 4915 /* CFAPBANK10STATUS */ "", 4916 /* CFAPBANK11STATUS */ "", 4917 /* CFAPBANK12STATUS */ "", 4918 /* CFAPBANK13STATUS */ "", 4919 /* CFAPBANK14STATUS */ "", 4920 /* CFAPBANK15STATUS */ "", 4921 /* CFAPBANK1STATUS */ "", 4922 /* CFAPBANK2STATUS */ "", 4923 /* CFAPBANK3STATUS */ "", 4924 /* CFAPBANK4STATUS */ "", 4925 /* CFAPBANK5STATUS */ "", 4926 /* CFAPBANK6STATUS */ "", 4927 /* CFAPBANK7STATUS */ "", 4928 /* CFAPBANK8STATUS */ "", 4929 /* CFAPBANK9STATUS */ "", 4930 /* CFAPBANKFULL */ "", 4931 /* CFAPBANKPARITYERROR */ "", 4932 /* CFAPBANKSTATUS */ "", 4933 /* CFAPBANK_STKPTR */ "", 4934 /* CFAPBANK_THD */ "", 4935 /* CFAPBSTSTAT */ "CFAP_BST_STAT", 4936 /* CFAPBSTTHRS */ "CFAP_BST_THRESHOLD", 4937 /* CFAPCONFIG */ "", 4938 /* CFAPDEBUGSCR0 */ "", 4939 /* CFAPDEBUGSCR1 */ "", 4940 /* CFAPDEBUGSCR2 */ "", 4941 /* CFAPECONFIG */ "", 4942 /* CFAPEFULLRESETPOINT */ "", 4943 /* CFAPEFULLSETPOINT */ "", 4944 /* CFAPEINIT */ "", 4945 /* CFAPELOWWATERMARK */ "", 4946 /* CFAPEMEMDEBUG_BITMAP */ "", 4947 /* CFAPEMEMDEBUG_STACK */ "", 4948 /* CFAPEOTPCONFIG */ "", 4949 /* CFAPEREADPOINTER */ "", 4950 /* CFAPESTACKSTATUS */ "", 4951 /* CFAPE_BITMAP_ECC_STATUS */ "", 4952 /* CFAPE_ECC_DEBUG */ "", 4953 /* CFAPE_ECC_ERROR */ "", 4954 /* CFAPE_ERROR_MASK */ "", 4955 /* CFAPE_POOL_CONG_DETECT_THRESH_0 */ "", 4956 /* CFAPE_POOL_CONG_DETECT_THRESH_1 */ "", 4957 /* CFAPE_POOL_CONG_DETECT_THRESH_2 */ "", 4958 /* CFAPE_STACK_ECC_STATUS */ "", 4959 /* CFAPFULLRESETPOINT */ "", 4960 /* CFAPFULLSETPOINT */ "", 4961 /* CFAPFULLTHRESHOLD */ "", 4962 /* CFAPFULLTHRESHOLD0 */ "", 4963 /* CFAPFULLTHRESHOLD1 */ "", 4964 /* CFAPFULLTHRESHOLDRESET */ "", 4965 /* CFAPFULLTHRESHOLDSET */ "", 4966 /* CFAPI0MEMDEBUG_BITMAP */ "", 4967 /* CFAPI0MEMDEBUG_STACK */ "", 4968 /* CFAPI0READPOINTER */ "", 4969 /* CFAPI0STACKSTATUS */ "", 4970 /* CFAPI0_BITMAP_ECC_STATUS */ "", 4971 /* CFAPI0_ECC_DEBUG */ "", 4972 /* CFAPI0_ECC_ERROR */ "", 4973 /* CFAPI0_ERROR_MASK */ "", 4974 /* CFAPI0_STACK_ECC_STATUS */ "", 4975 /* CFAPI1MEMDEBUG_BITMAP */ "", 4976 /* CFAPI1MEMDEBUG_STACK */ "", 4977 /* CFAPI1READPOINTER */ "", 4978 /* CFAPI1STACKSTATUS */ "", 4979 /* CFAPI1_BITMAP_ECC_STATUS */ "", 4980 /* CFAPI1_ECC_DEBUG */ "", 4981 /* CFAPI1_ECC_ERROR */ "", 4982 /* CFAPI1_ERROR_MASK */ "", 4983 /* CFAPI1_STACK_ECC_STATUS */ "", 4984 /* CFAPICONFIG */ "", 4985 /* CFAPIFULLRESETPOINT */ "", 4986 /* CFAPIFULLSETPOINT */ "", 4987 /* CFAPIINIT */ "", 4988 /* CFAPILOWWATERMARK */ "", 4989 /* CFAPIMEMDEBUG_BITMAP */ "", 4990 /* CFAPIMEMDEBUG_STACK */ "", 4991 /* CFAPINIT */ "", 4992 /* CFAPIOTPCONFIG */ "", 4993 /* CFAPIREADPOINTER */ "", 4994 /* CFAPISTACKSTATUS */ "", 4995 /* CFAPI_BITMAP_ECC_STATUS */ "", 4996 /* CFAPI_ECC_DEBUG */ "", 4997 /* CFAPI_ECC_ERROR */ "", 4998 /* CFAPI_ERROR_MASK */ "", 4999 /* CFAPI_STACK_ECC_STATUS */ "", 5000 /* CFAPLOWWATERMARK */ "", 5001 /* CFAPMEMDEBUG */ "", 5002 /* CFAPOTPCONFIG */ "", 5003 /* CFAPPARITYERRORPTR */ "", 5004 /* CFAPREADPOINTER */ "", 5005 /* CFAP_ARBITER_CONTROL */ "", 5006 /* CFAP_ARBITER_MASK */ "", 5007 /* CFAP_ARBITER_RANDOM_SEED */ "", 5008 /* CFAP_ARBITER_RANKER */ "", 5009 /* CFAP_ARBITER_RANKER0 */ "", 5010 /* CFAP_ARBITER_RANKER1 */ "", 5011 /* CFAP_ARBITER_RANKER2 */ "", 5012 /* CFAP_ARBITER_RANKER3 */ "", 5013 /* CFAP_ARBITER_RANKER4 */ "", 5014 /* CFAP_ARBITER_RANKER5 */ "", 5015 /* CFAP_ARBITER_RANKER6 */ "", 5016 /* CFAP_ARBITER_RANKER7 */ "", 5017 /* CFAP_ARBITER_RANKER8 */ "", 5018 /* CFAP_ARBITER_RANKER9 */ "", 5019 /* CFAP_ARBITER_RANKER10 */ "", 5020 /* CFAP_ARBITER_RANKER11 */ "", 5021 /* CFAP_ARBITER_RANKER12 */ "", 5022 /* CFAP_ARBITER_RANKER13 */ "", 5023 /* CFAP_ARBITER_RANKER14 */ "", 5024 /* CFAP_ARBITER_RANKER15 */ "", 5025 /* CFAP_ARBITER_RANKER16 */ "", 5026 /* CFAP_ARBITER_RANKER17 */ "", 5027 /* CFAP_ARBITER_RANKER18 */ "", 5028 /* CFAP_BANK_PTR_MASK */ "", 5029 /* CFAP_BST_STAT */ "CFAP_BST_STAT", 5030 /* CFAP_BST_THRS */ "CFAP_BST_THRESHOLD", 5031 /* CFAP_BUFFER_POOL_CONG_STATE */ "", 5032 /* CFAP_DEBUG_CFG0 */ "", 5033 /* CFAP_DEBUG_CFG1 */ "", 5034 /* CFAP_DROP_CNT */ "", 5035 /* CFAP_DROP_PKT_CNT */ "", 5036 /* CFAP_ECC_1B_COUNTER */ "", 5037 /* CFAP_ECC_2B_COUNTER */ "", 5038 /* CFAP_EN_COR_ERR_RPT */ "", 5039 /* CFAP_ERROR */ "", 5040 /* CFAP_ERROR_MASK */ "", 5041 /* CFAP_FULL_BP_STATUS */ "", 5042 /* CFAP_POOL_CONG_DETECT_THRESH_0 */ "", 5043 /* CFAP_POOL_CONG_DETECT_THRESH_1 */ "", 5044 /* CFAP_POOL_CONG_DETECT_THRESH_2 */ "", 5045 /* CFAP_STACK_WATERMARK */ "", 5046 /* CFC_CAT_2_TC_MAP_HCFC_ENA */ "", 5047 /* CFC_CAT_2_TC_MAP_NIF_ENA */ "", 5048 /* CFC_CFC_ENABLERS */ "", 5049 /* CFC_CFC_REGISTER_1 */ "", 5050 /* CFC_CGM_GLBL_FC_STATUS */ "", 5051 /* CFC_CGM_VSQ_FC_STATUS_SEL */ "", 5052 /* CFC_CGM_VSQ_GRPS_ABCD_FC_STATUS */ "", 5053 /* CFC_CGM_VSQ_LLFC_STATUS */ "", 5054 /* CFC_CGM_VSQ_PFC_STATUS */ "", 5055 /* CFC_CLR_CMIC_FC */ "", 5056 /* CFC_CLR_CMIC_TX_FC */ "", 5057 /* CFC_CLR_EGQ_PFC */ "", 5058 /* CFC_CLR_NIF_FAST_LLFC */ "", 5059 /* CFC_CLR_NIF_LNK_FC */ "", 5060 /* CFC_CLR_NIF_PFC */ "", 5061 /* CFC_CLR_SCH_FC */ "", 5062 /* CFC_CLR_SCH_IF_FC */ "", 5063 /* CFC_CLR_SCH_PFC */ "", 5064 /* CFC_CMIC_RX_FC_CFG */ "", 5065 /* CFC_CMIC_RX_FC_MAP */ "", 5066 /* CFC_CMIC_RX_FC_MASK */ "", 5067 /* CFC_CMIC_RX_FC_STATUS */ "", 5068 /* CFC_CMIC_TX_FC */ "", 5069 /* CFC_CMIC_TX_FC_STATUS */ "", 5070 /* CFC_ECC_1B_ERR_CNT */ "", 5071 /* CFC_ECC_2B_ERR_CNT */ "", 5072 /* CFC_ECC_ERR_1B_INITIATE */ "", 5073 /* CFC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 5074 /* CFC_ECC_ERR_2B_INITIATE */ "", 5075 /* CFC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 5076 /* CFC_ECC_INTERRUPT_REGISTER */ "", 5077 /* CFC_ECC_INTERRUPT_REGISTER_MASK */ "", 5078 /* CFC_ECC_INTERRUPT_REGISTER_TEST */ "", 5079 /* CFC_EGQ_CNM_LLFC_STATUS */ "", 5080 /* CFC_EGQ_CNM_PFC_STATUS */ "", 5081 /* CFC_EGQ_FC_STATUS */ "", 5082 /* CFC_EGQ_IF_FC_STATUS */ "", 5083 /* CFC_EGQ_PFC_STATUS */ "", 5084 /* CFC_EGQ_SEL */ "", 5085 /* CFC_EGQ_STATUS_SEL */ "", 5086 /* CFC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 5087 /* CFC_ERROR_INITIATION_DATA */ "", 5088 /* CFC_FRC_CMIC_FC */ "", 5089 /* CFC_FRC_CMIC_TX_FC */ "", 5090 /* CFC_FRC_EGQ_PFC */ "", 5091 /* CFC_FRC_NIF_FAST_LLFC */ "", 5092 /* CFC_FRC_NIF_LNK_FC */ "", 5093 /* CFC_FRC_NIF_PFC */ "", 5094 /* CFC_FRC_NIF_SHR */ "", 5095 /* CFC_FRC_SCH_FC */ "", 5096 /* CFC_FRC_SCH_IF_FC */ "", 5097 /* CFC_FRC_SCH_PFC */ "", 5098 /* CFC_GLB_RSC_CGM_MASK */ "", 5099 /* CFC_GLB_RSC_DRAM_CGM_TO_NIF_LLFC_HP_MAP */ "", 5100 /* CFC_GLB_RSC_HDRM_CGM_TO_NIF_LLFC_HP_MAP */ "", 5101 /* CFC_GLB_RSC_IQM_MASK */ "", 5102 /* CFC_GLB_RSC_MIX_CGM_TO_NIF_LLFC_HP_MAP */ "", 5103 /* CFC_GLB_RSC_MIX_POOL_0_IQM_0_TO_NIF_LLFC_HP_MAP */ "", 5104 /* CFC_GLB_RSC_MIX_POOL_0_IQM_1_TO_NIF_LLFC_HP_MAP */ "", 5105 /* CFC_GLB_RSC_MIX_POOL_1_IQM_0_TO_NIF_LLFC_HP_MAP */ "", 5106 /* CFC_GLB_RSC_MIX_POOL_1_IQM_1_TO_NIF_LLFC_HP_MAP */ "", 5107 /* CFC_GLB_RSC_OCB_POOL_0_IQM_0_TO_NIF_LLFC_HP_MAP */ "", 5108 /* CFC_GLB_RSC_OCB_POOL_0_IQM_1_TO_NIF_LLFC_HP_MAP */ "", 5109 /* CFC_GLB_RSC_OCB_POOL_1_IQM_0_TO_NIF_LLFC_HP_MAP */ "", 5110 /* CFC_GLB_RSC_OCB_POOL_1_IQM_1_TO_NIF_LLFC_HP_MAP */ "", 5111 /* CFC_GLB_RSC_POOL_0_CGM_TO_NIF_LLFC_HP_MAP */ "", 5112 /* CFC_GLB_RSC_POOL_1_CGM_TO_NIF_LLFC_HP_MAP */ "", 5113 /* CFC_GLB_RSC_SRAM_CGM_TO_NIF_LLFC_HP_MAP */ "", 5114 /* CFC_GLB_RSC_TO_HCFC_HP_MAP */ "", 5115 /* CFC_GLB_RSC_TO_HCFC_LP_MAP */ "", 5116 /* CFC_GLB_RSC_TO_RCL_PFC_HP_MAP */ "", 5117 /* CFC_GLB_RSC_TO_RCL_PFC_LP_MAP */ "", 5118 /* CFC_GLOBAL_MEM_OPTIONS */ "", 5119 /* CFC_GTIMER_CONFIGURATION */ "", 5120 /* CFC_GTIMER_CYCLE */ "", 5121 /* CFC_GTIMER_TRIGGER */ "", 5122 /* CFC_HCFC_OOB_0_CHANNEL_BASE_CFG */ "", 5123 /* CFC_HCFC_OOB_0_MESSAGE_CFG */ "", 5124 /* CFC_HCFC_OOB_1_CHANNEL_BASE_CFG */ "", 5125 /* CFC_HCFC_OOB_1_MESSAGE_CFG */ "", 5126 /* CFC_HCFC_OOB_CHANNEL_BASE_CFG */ "", 5127 /* CFC_HCFC_OOB_MESSAGE_CFG */ "", 5128 /* CFC_HCFC_OOB_RX_0_CRC_ERR_CTR */ "", 5129 /* CFC_HCFC_OOB_RX_0_WD_PERIOD_CFG */ "", 5130 /* CFC_HCFC_OOB_RX_1_CRC_ERR_CTR */ "", 5131 /* CFC_HCFC_OOB_RX_1_WD_PERIOD_CFG */ "", 5132 /* CFC_HCFC_OOB_RX_CRC_ERR_CTR */ "", 5133 /* CFC_HCFC_OOB_RX_ERR_CFG */ "", 5134 /* CFC_HCFC_OOB_RX_HEADER_CHECK_DISABLE */ "", 5135 /* CFC_HCFC_OOB_RX_WD_EN_CFG */ "", 5136 /* CFC_HCFC_OOB_RX_WD_ERR_STATUS */ "", 5137 /* CFC_HCFC_OOB_RX_WD_PERIOD_CFG */ "", 5138 /* CFC_HCFC_OOB_TX_0_GENERAL_CFG */ "", 5139 /* CFC_HCFC_OOB_TX_1_GENERAL_CFG */ "", 5140 /* CFC_HCFC_OOB_TX_GENERAL_CFG */ "", 5141 /* CFC_IHB_0_PP_INBAND */ "", 5142 /* CFC_IHB_1_PP_INBAND */ "", 5143 /* CFC_ILKN_0_MUB_TX_CAL */ "", 5144 /* CFC_ILKN_0_OOB_RX_CRC_ERR_CNT */ "", 5145 /* CFC_ILKN_0_OOB_RX_LANES_STATUS */ "", 5146 /* CFC_ILKN_1_MUB_TX_CAL */ "", 5147 /* CFC_ILKN_1_OOB_RX_CRC_ERR_CNT */ "", 5148 /* CFC_ILKN_1_OOB_RX_LANES_STATUS */ "", 5149 /* CFC_ILKN_2_MUB_TX_CAL */ "", 5150 /* CFC_ILKN_3_MUB_TX_CAL */ "", 5151 /* CFC_ILKN_4_MUB_TX_CAL */ "", 5152 /* CFC_ILKN_5_MUB_TX_CAL */ "", 5153 /* CFC_ILKN_INB_RX_0_FC_STATUS */ "", 5154 /* CFC_ILKN_INB_RX_1_FC_STATUS */ "", 5155 /* CFC_ILKN_INB_RX_2_FC_STATUS */ "", 5156 /* CFC_ILKN_INB_RX_3_FC_STATUS */ "", 5157 /* CFC_ILKN_INB_RX_4_FC_STATUS */ "", 5158 /* CFC_ILKN_INB_RX_5_FC_STATUS */ "", 5159 /* CFC_ILKN_MUB_ENABLE */ "", 5160 /* CFC_ILKN_MUB_RX_IF_ENA */ "", 5161 /* CFC_ILKN_OOB_CONFIG */ "", 5162 /* CFC_ILKN_OOB_INDICATIONS */ "", 5163 /* CFC_ILKN_OOB_POLARITY_CFG */ "", 5164 /* CFC_ILKN_OOB_RSTN */ "", 5165 /* CFC_ILKN_OOB_RX_0_FC_STATUS */ "", 5166 /* CFC_ILKN_OOB_RX_1_FC_STATUS */ "", 5167 /* CFC_ILKN_OOB_RX_FC_STATUS */ "", 5168 /* CFC_ILKN_OOB_RX_RT_CAL_CFG */ "", 5169 /* CFC_ILKN_OOB_TX_FRC */ "", 5170 /* CFC_ILKN_OOB_TX_MASK_CFG */ "", 5171 /* CFC_ILKN_OOB_TX_RT_CAL_CFG */ "", 5172 /* CFC_ILKN_PP_RX_4_FC_STATUS */ "", 5173 /* CFC_ILKN_RETRANSMIT_REQ_TIMERS */ "", 5174 /* CFC_ILKN_RETRANSMIT_REQ_TIMERS_EXT */ "", 5175 /* CFC_ILKN_RX_0_FC_STATUS */ "", 5176 /* CFC_ILKN_RX_1_FC_STATUS */ "", 5177 /* CFC_ILKN_RX_CONFIGURATION */ "", 5178 /* CFC_ILKN_TX_CONFIGURATION */ "", 5179 /* CFC_INDIRECT_COMMAND */ "", 5180 /* CFC_INDIRECT_COMMAND_ADDRESS */ "", 5181 /* CFC_INDIRECT_COMMAND_DATA_INCREMENT */ "", 5182 /* CFC_INDIRECT_COMMAND_RD_DATA */ "", 5183 /* CFC_INDIRECT_COMMAND_WIDE_MEM */ "", 5184 /* CFC_INDIRECT_COMMAND_WR_DATA */ "", 5185 /* CFC_INDIRECT_FORCE_BUBBLE */ "", 5186 /* CFC_INDIRECT_WR_MASK */ "", 5187 /* CFC_INITIATE_PAR_ERR */ "", 5188 /* CFC_INTERRUPT_MASK_REGISTER */ "", 5189 /* CFC_INTERRUPT_REGISTER */ "", 5190 /* CFC_INTERRUPT_REGISTER_TEST */ "", 5191 /* CFC_IQM_GLBL_FC_STATUS */ "", 5192 /* CFC_IQM_SEL */ "", 5193 /* CFC_IQM_VSQ_FC_STATUS_SEL */ "", 5194 /* CFC_IQM_VSQ_GRPS_ABCD_FC_STATUS */ "", 5195 /* CFC_IQM_VSQ_LLFC_STATUS */ "", 5196 /* CFC_IQM_VSQ_PFC_STATUS */ "", 5197 /* CFC_LP_GLB_RSC_TO_NIF_PFC_MAP */ "", 5198 /* CFC_NIF_AF_FC_STATUS */ "", 5199 /* CFC_NIF_FCV_STATUS */ "", 5200 /* CFC_NIF_FCV_STATUS_SEL */ "", 5201 /* CFC_NIF_MUB_STATUS */ "", 5202 /* CFC_NIF_PFC_STATUS */ "", 5203 /* CFC_NIF_PFC_STATUS_SEL */ "", 5204 /* CFC_NIF_RT_STATUS */ "", 5205 /* CFC_OOB_PAD_CONFIGURATION */ "", 5206 /* CFC_OOB_RX_ERR */ "", 5207 /* CFC_PARITY_ERR_CNT */ "", 5208 /* CFC_PARITY_ERR_MONITOR_MEM_MASK */ "", 5209 /* CFC_PAR_ERR_INITIATE */ "", 5210 /* CFC_PAR_ERR_MEM_MASK */ "", 5211 /* CFC_PCMI_0 */ "", 5212 /* CFC_PCMI_1 */ "", 5213 /* CFC_PCMI_2 */ "", 5214 /* CFC_PCMI_3 */ "", 5215 /* CFC_PCMI_4 */ "", 5216 /* CFC_PCMI_0_S */ "", 5217 /* CFC_PCMI_0_T */ "", 5218 /* CFC_PCMI_1_S */ "", 5219 /* CFC_PCMI_1_T */ "", 5220 /* CFC_PCMI_2_S */ "", 5221 /* CFC_PCMI_2_T */ "", 5222 /* CFC_PCMI_3_S */ "", 5223 /* CFC_PCMI_3_T */ "", 5224 /* CFC_PCMI_4_S */ "", 5225 /* CFC_PCMI_4_T */ "", 5226 /* CFC_PFC_GENERIC_BITMAP */ "", 5227 /* CFC_PFC_GENERIC_BITMAP_0 */ "", 5228 /* CFC_PFC_GENERIC_BITMAP_1 */ "", 5229 /* CFC_PFC_GENERIC_BITMAP_2 */ "", 5230 /* CFC_PFC_GENERIC_BITMAP_3 */ "", 5231 /* CFC_PFC_GENERIC_BITMAP_4 */ "", 5232 /* CFC_PFC_GENERIC_BITMAP_5 */ "", 5233 /* CFC_PFC_GENERIC_BITMAP_6 */ "", 5234 /* CFC_PFC_GENERIC_BITMAP_7 */ "", 5235 /* CFC_PFC_GENERIC_BITMAP_8 */ "", 5236 /* CFC_PFC_GENERIC_BITMAP_9 */ "", 5237 /* CFC_PFC_GENERIC_BITMAP_10 */ "", 5238 /* CFC_PFC_GENERIC_BITMAP_11 */ "", 5239 /* CFC_PFC_GENERIC_BITMAP_12 */ "", 5240 /* CFC_PFC_GENERIC_BITMAP_13 */ "", 5241 /* CFC_PFC_GENERIC_BITMAP_14 */ "", 5242 /* CFC_PFC_GENERIC_BITMAP_15 */ "", 5243 /* CFC_PFC_GENERIC_BITMAP_16 */ "", 5244 /* CFC_PFC_GENERIC_BITMAP_17 */ "", 5245 /* CFC_PFC_GENERIC_BITMAP_18 */ "", 5246 /* CFC_PFC_GENERIC_BITMAP_19 */ "", 5247 /* CFC_PFC_GENERIC_BITMAP_20 */ "", 5248 /* CFC_PFC_GENERIC_BITMAP_21 */ "", 5249 /* CFC_PFC_GENERIC_BITMAP_22 */ "", 5250 /* CFC_PFC_GENERIC_BITMAP_23 */ "", 5251 /* CFC_PFC_GENERIC_BITMAP_24 */ "", 5252 /* CFC_PFC_GENERIC_BITMAP_25 */ "", 5253 /* CFC_PFC_GENERIC_BITMAP_26 */ "", 5254 /* CFC_PFC_GENERIC_BITMAP_27 */ "", 5255 /* CFC_PFC_GENERIC_BITMAP_28 */ "", 5256 /* CFC_PFC_GENERIC_BITMAP_29 */ "", 5257 /* CFC_PFC_GENERIC_BITMAP_30 */ "", 5258 /* CFC_PFC_GENERIC_BITMAP_31 */ "", 5259 /* CFC_PFC_GENERIC_BITMAP_32 */ "", 5260 /* CFC_PFC_GENERIC_BITMAP_33 */ "", 5261 /* CFC_PFC_GENERIC_BITMAP_34 */ "", 5262 /* CFC_PFC_GENERIC_BITMAP_35 */ "", 5263 /* CFC_PFC_GENERIC_BITMAP_36 */ "", 5264 /* CFC_PFC_GENERIC_BITMAP_37 */ "", 5265 /* CFC_PFC_GENERIC_BITMAP_38 */ "", 5266 /* CFC_PFC_GENERIC_BITMAP_39 */ "", 5267 /* CFC_PFC_STATUS */ "", 5268 /* CFC_PFC_STATUS_SEL */ "", 5269 /* CFC_PP_INBAND */ "", 5270 /* CFC_PP_RX_4_FC_STATUS */ "", 5271 /* CFC_QPAIR_LAG_MAP */ "", 5272 /* CFC_REG_0041 */ "", 5273 /* CFC_REG_0085 */ "", 5274 /* CFC_REG_0086 */ "", 5275 /* CFC_REG_0087 */ "", 5276 /* CFC_REG_0090 */ "", 5277 /* CFC_REG_0091 */ "", 5278 /* CFC_REG_0092 */ "", 5279 /* CFC_REG_0093 */ "", 5280 /* CFC_REG_0284 */ "", 5281 /* CFC_REG_00A4 */ "", 5282 /* CFC_REG_00A6 */ "", 5283 /* CFC_REG_00AE */ "", 5284 /* CFC_REG_00C2 */ "", 5285 /* CFC_REG_00CF */ "", 5286 /* CFC_RESERVED_MIRROR_ADDR */ "", 5287 /* CFC_RESERVED_MTCD */ "", 5288 /* CFC_RESERVED_MTCP */ "", 5289 /* CFC_RESERVED_PCMI_0 */ "", 5290 /* CFC_RESERVED_PCMI_1 */ "", 5291 /* CFC_RESERVED_PCMI_2 */ "", 5292 /* CFC_RESERVED_PCMI_3 */ "", 5293 /* CFC_RESERVED_PCMI_4 */ "", 5294 /* CFC_RESERVED_PCMI_0_S */ "", 5295 /* CFC_RESERVED_PCMI_0_T */ "", 5296 /* CFC_RESERVED_PCMI_1_S */ "", 5297 /* CFC_RESERVED_PCMI_1_T */ "", 5298 /* CFC_RESERVED_PCMI_2_S */ "", 5299 /* CFC_RESERVED_PCMI_2_T */ "", 5300 /* CFC_RESERVED_PCMI_3_S */ "", 5301 /* CFC_RESERVED_PCMI_3_T */ "", 5302 /* CFC_RESERVED_PCMI_4_S */ "", 5303 /* CFC_RESERVED_PCMI_4_T */ "", 5304 /* CFC_RESERVED_SPARE_0 */ "", 5305 /* CFC_RESERVED_SPARE_1 */ "", 5306 /* CFC_RESERVED_SPARE_2 */ "", 5307 /* CFC_RESERVED_SPARE_3 */ "", 5308 /* CFC_RING_OSCILATOR */ "", 5309 /* CFC_SBUS_BROADCAST_ID */ "", 5310 /* CFC_SBUS_LAST_IN_CHAIN */ "", 5311 /* CFC_SCH_OOB_RX_CFG */ "", 5312 /* CFC_SELECT_OUTPUT_OF_SYNCHRONOUS_ETHERNET_PADS */ "", 5313 /* CFC_SPI_OOB_CONFIGURATION */ "", 5314 /* CFC_SPI_OOB_RX_0_ERROR_COUNTER */ "", 5315 /* CFC_SPI_OOB_RX_0_GEN_PFC_STATUS */ "", 5316 /* CFC_SPI_OOB_RX_0_LLFC_STATUS */ "", 5317 /* CFC_SPI_OOB_RX_0_PFC_STATUS */ "", 5318 /* CFC_SPI_OOB_RX_1_ERROR_COUNTER */ "", 5319 /* CFC_SPI_OOB_RX_1_GEN_PFC_STATUS */ "", 5320 /* CFC_SPI_OOB_RX_1_LLFC_STATUS */ "", 5321 /* CFC_SPI_OOB_RX_1_PFC_STATUS */ "", 5322 /* CFC_SPI_OOB_RX_CONFIGURATION_0 */ "", 5323 /* CFC_SPI_OOB_RX_CONFIGURATION_1 */ "", 5324 /* CFC_SPI_OOB_RX_ERROR_COUNTER */ "", 5325 /* CFC_SPI_OOB_RX_ERR_CFG */ "", 5326 /* CFC_SPI_OOB_RX_GEN_PFC_STATUS */ "", 5327 /* CFC_SPI_OOB_RX_LLFC_STATUS */ "", 5328 /* CFC_SPI_OOB_RX_PFC_SEL */ "", 5329 /* CFC_SPI_OOB_RX_PFC_STATUS */ "", 5330 /* CFC_SPI_OOB_RX_WD_EN_CFG */ "", 5331 /* CFC_SPI_OOB_RX_WD_PERIOD_CFG */ "", 5332 /* CFC_SPI_OOB_TX_CONFIGURATION */ "", 5333 /* CFC_SWAP_NIF_FCV_POLARITY */ "", 5334 /* CFC_SYNCE_MASTER_PLL_CONFIG */ "", 5335 /* CFC_SYNCE_MASTER_PLL_STATUS */ "", 5336 /* CFC_SYNCE_SLAVE_PLL_CONFIG */ "", 5337 /* CFC_SYNCE_SLAVE_PLL_STATUS */ "", 5338 /* CFG_RAM_CONTROL */ "", 5339 /* CFG_RAM_CONTROL_1 */ "", 5340 /* CFG_RAM_CONTROL_2 */ "", 5341 /* CFG_RAM_CONTROL_1_PIPE0 */ "", 5342 /* CFG_RAM_CONTROL_1_PIPE1 */ "", 5343 /* CFG_RAM_CONTROL_1_PIPE2 */ "", 5344 /* CFG_RAM_CONTROL_1_PIPE3 */ "", 5345 /* CFG_RAM_CONTROL_2_PIPE0 */ "", 5346 /* CFG_RAM_CONTROL_2_PIPE1 */ "", 5347 /* CFG_RAM_CONTROL_2_PIPE2 */ "", 5348 /* CFG_RAM_CONTROL_2_PIPE3 */ "", 5349 /* CFG_RAM_DBGCTRL */ "CFG_RAM_CONTROL", 5350 /* CFG_RAM_DBGCTRL_1 */ "CFG_RAM_CONTROL_1", 5351 /* CFG_SER_CONTROL */ "", 5352 /* CGM_AUTO_DOC_NAME_22 */ "", 5353 /* CGM_AUTO_DOC_NAME_27 */ "", 5354 /* CGM_AUTO_DOC_NAME_31 */ "", 5355 /* CGM_AUTO_DOC_NAME_35 */ "", 5356 /* CGM_AUTO_DOC_NAME_42 */ "", 5357 /* CGM_AUTO_DOC_NAME_44 */ "", 5358 /* CGM_AUTO_DOC_NAME_47 */ "", 5359 /* CGM_AUTO_DOC_NAME_49 */ "", 5360 /* CGM_AUTO_DOC_NAME_51 */ "", 5361 /* CGM_AUTO_DOC_NAME_53 */ "", 5362 /* CGM_AUTO_DOC_NAME_55 */ "", 5363 /* CGM_AUTO_DOC_NAME_58 */ "", 5364 /* CGM_AUTO_DOC_NAME_60 */ "", 5365 /* CGM_AUTO_DOC_NAME_63 */ "", 5366 /* CGM_AUTO_DOC_NAME_65 */ "", 5367 /* CGM_AUTO_DOC_NAME_68 */ "", 5368 /* CGM_AUTO_DOC_NAME_70 */ "", 5369 /* CGM_AUTO_DOC_NAME_73 */ "", 5370 /* CGM_CGM_DB_TH_SP_OR_SHARED */ "", 5371 /* CGM_CGM_DISABLE_DISCARDS_TO_PQP */ "", 5372 /* CGM_CGM_DISABLE_DISCARDS_TO_RQP */ "", 5373 /* CGM_CGM_DP_ELIGIBLE_TO_USE_RESOURCES */ "", 5374 /* CGM_CGM_DROP_CTR_PKT_OR_DB */ "", 5375 /* CGM_CGM_DYN_TH_DEBUG */ "", 5376 /* CGM_CGM_GENERAL_DB_TH */ "", 5377 /* CGM_CGM_GENERAL_FC_TH */ "", 5378 /* CGM_CGM_GENERAL_PD_TH */ "", 5379 /* CGM_CGM_INIT */ "", 5380 /* CGM_CGM_MAP_IF_2_TH */ "", 5381 /* CGM_CGM_MAP_TC_TO_SP */ "", 5382 /* CGM_CGM_MAX_VALUES_DISABLE_UPDATE */ "", 5383 /* CGM_CGM_MC_DB_DROPPED_CNT_VALUE */ "", 5384 /* CGM_CGM_MC_DB_SP_TC_TH */ "", 5385 /* CGM_CGM_MC_DB_TC_FC_TH */ "", 5386 /* CGM_CGM_MC_INTERFACE_MAP_TH */ "", 5387 /* CGM_CGM_MC_INTERFACE_PD_TH */ "", 5388 /* CGM_CGM_MC_PD_PER_PORT_DYN_TH_DEBUG */ "", 5389 /* CGM_CGM_MC_PD_SP_TC_TH */ "", 5390 /* CGM_CGM_MC_PD_TC_FC_TH */ "", 5391 /* CGM_CGM_MC_REP_DB_DROPPED_CNT_VALUE */ "", 5392 /* CGM_CGM_MC_REP_PD_DROPPED_CNT_VALUE */ "", 5393 /* CGM_CGM_MC_RSVD_DB_SP_TH */ "", 5394 /* CGM_CGM_MC_RSVD_MAX_VAL */ "", 5395 /* CGM_CGM_PD_TH_SP_OR_SHARED */ "", 5396 /* CGM_CGM_QUEUE_IS_DISABLED */ "", 5397 /* CGM_CGM_REP_AROUND_INTERRUPT_REGISTER */ "", 5398 /* CGM_CGM_REP_AROUND_INTERRUPT_REGISTER_MASK */ "", 5399 /* CGM_CGM_REP_AROUND_INT_REG_TEST */ "", 5400 /* CGM_CGM_UC_DB_DROPPED_BY_PQP_CNT_VALUE */ "", 5401 /* CGM_CGM_UC_DB_DROPPED_BY_RQP_CNT_VALUE */ "", 5402 /* CGM_CGM_UC_PD_DROPPED_CNT_VALUE */ "", 5403 /* CGM_CGM_UC_PD_INTERFACE_FC_ALPHA */ "", 5404 /* CGM_CGM_UC_PD_INTERFACE_FC_MAX_TH */ "", 5405 /* CGM_CGM_UC_PD_INTERFACE_FC_MIN_TH */ "", 5406 /* CGM_CGM_UC_PD_INTERFACE_FC_TH */ "", 5407 /* CGM_CGM_UC_SIZE_256_INTERFACE_FC_ALPHA */ "", 5408 /* CGM_CGM_UC_SIZE_256_INTERFACE_FC_MAX_TH */ "", 5409 /* CGM_CGM_UC_SIZE_256_INTERFACE_FC_MIN_TH */ "", 5410 /* CGM_CGM_UC_SIZE_256_INTERFACE_FC_TH */ "", 5411 /* CGM_CONGESTION_INTERRUPT_ENABLERS */ "", 5412 /* CGM_CONGESTION_INTERRUPT_REGISTER */ "", 5413 /* CGM_CONGESTION_INTERRUPT_REGISTER_MASK */ "", 5414 /* CGM_CONGESTION_INTERRUPT_REGISTER_TEST */ "", 5415 /* CGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_ALPHA */ "", 5416 /* CGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_MAXIMUM_THRESHOLDS */ "", 5417 /* CGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_MINIMUM_THRESHOLDS */ "", 5418 /* CGM_CONGESTION_MANAGEMENT_GLOBAL_DB_THRESHOLDS */ "", 5419 /* CGM_CONGESTION_MANAGEMENT_GLOBAL_FLOW_CONTROL_THRESHOLDS */ "", 5420 /* CGM_CONGESTION_MANAGEMENT_GLOBAL_PD_THRESHOLDS */ "", 5421 /* CGM_CONGESTION_MANAGEMENT_MULTICAST_FLOW_CONTROL_PER_TC_THREHOSLDS */ "", 5422 /* CGM_CONGESTION_MANAGEMENT_MULTICAST_RESERVED_RESOURCES */ "", 5423 /* CGM_CONGESTION_MANAGEMENT_MULTICAST_RESERVED_RESOURCES_PER_CLASS */ "", 5424 /* CGM_CONGESTION_MANAGEMENT_PD_SERVICE_POOL_THRESHOLDS */ "", 5425 /* CGM_CONGESTION_TRACKING_MULTICAST_DBSP_0_MAX_VALUE */ "", 5426 /* CGM_CONGESTION_TRACKING_MULTICAST_DBSP_1_MAX_VALUE */ "", 5427 /* CGM_CONGESTION_TRACKING_MULTICAST_DB_MAX_VALUE */ "", 5428 /* CGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE */ "", 5429 /* CGM_CONGESTION_TRACKING_MULTICAST_PDSP_0_MAX_VALUE */ "", 5430 /* CGM_CONGESTION_TRACKING_MULTICAST_PDSP_1_MAX_VALUE */ "", 5431 /* CGM_CONGESTION_TRACKING_MULTICAST_PD_MAX_VALUE */ "", 5432 /* CGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE */ "", 5433 /* CGM_CONGESTION_TRACKING_TOTAL_DB_MAX_VALUE */ "", 5434 /* CGM_CONGESTION_TRACKING_TOTAL_PD_MAX_VALUE */ "", 5435 /* CGM_CONGESTION_TRACKING_UNICAST_DB_MAX_VALUE */ "", 5436 /* CGM_CONGESTION_TRACKING_UNICAST_PD_MAX_VALUE */ "", 5437 /* CGM_CRPS_ILM_BUBBLE_REQ_CTR */ "", 5438 /* CGM_CRPS_IRPP_CTR_BUBBLE_REQ_CTR */ "", 5439 /* CGM_CRPS_PP_1_PQP_DROP_REASONS_MASK */ "", 5440 /* CGM_CRPS_PP_2_PQP_DROP_REASONS_MASK */ "", 5441 /* CGM_CRPS_TM_CTR_BUBBLE_REQ_CTR */ "", 5442 /* CGM_CRPS_TM_PQP_DROP_REASONS_MASK */ "", 5443 /* CGM_DEST_REQUESTS_CTR */ "", 5444 /* CGM_DP_LEVEL_RJCT_PKT_CTR */ "", 5445 /* CGM_DRAM_BDBS_FREE_MIN_STATUS */ "", 5446 /* CGM_DRAM_BDBS_FREE_STATUS */ "", 5447 /* CGM_DRAM_BDBS_RJCT_PKT_CTR */ "", 5448 /* CGM_DRAM_BOUND_RECOVERY_MAX_STATUS */ "", 5449 /* CGM_DRAM_BOUND_RECOVERY_STATUS */ "", 5450 /* CGM_DRAM_BOUND_STATE_LFSR_MASKS */ "", 5451 /* CGM_DRAM_BOUND_STATE_TH */ "", 5452 /* CGM_DRAM_QM_RPRT_RX_FIFO_STATUS */ "", 5453 /* CGM_DRAM_RPRT_STOP_TH */ "", 5454 /* CGM_DROP_REASON_RJCT_MASK */ "", 5455 /* CGM_DUMMY_REG */ "", 5456 /* CGM_ECC_1B_ERR_CNT */ "", 5457 /* CGM_ECC_2B_ERR_CNT */ "", 5458 /* CGM_ECC_ERR_1B_INITIATE */ "", 5459 /* CGM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 5460 /* CGM_ECC_ERR_2B_INITIATE */ "", 5461 /* CGM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 5462 /* CGM_ECC_INTERRUPT_REGISTER */ "", 5463 /* CGM_ECC_INTERRUPT_REGISTER_MASK */ "", 5464 /* CGM_ECC_INTERRUPT_REGISTER_TEST */ "", 5465 /* CGM_ENABLERS */ "", 5466 /* CGM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 5467 /* CGM_ERROR_INITIATION_DATA */ "", 5468 /* CGM_EXTERNAL_ERR_PKT_CTR */ "", 5469 /* CGM_EXT_STAT_BILL_SETTINGS */ "", 5470 /* CGM_EXT_STAT_BILL_STAMP */ "", 5471 /* CGM_EXT_STAT_QNUM_RANGE_FILTER */ "", 5472 /* CGM_EXT_STAT_SCRB_SETTINGS */ "", 5473 /* CGM_EXT_STAT_SETTINGS */ "", 5474 /* CGM_FABRIC_MC_BASE_QUEUE */ "", 5475 /* CGM_FIFO_SIZES */ "", 5476 /* CGM_FLOW_AGR_SETTINGS */ "", 5477 /* CGM_FLOW_BASE_QUEUE */ "", 5478 /* CGM_FR_GLBL_RSRC_RJCT_STATUS */ "", 5479 /* CGM_FR_RSRC_DP_RJCT_STATUS */ "", 5480 /* CGM_GLBL_RJCT_PRMS */ "", 5481 /* CGM_GLOBAL_FC_STATUS */ "", 5482 /* CGM_GLOBAL_MEM_OPTIONS */ "", 5483 /* CGM_GTIMER_CONFIGURATION */ "", 5484 /* CGM_GTIMER_CYCLE */ "", 5485 /* CGM_GTIMER_TRIGGER */ "", 5486 /* CGM_HDR_APPEND_PTR_MC_OW */ "", 5487 /* CGM_IEP_SETTINGS */ "", 5488 /* CGM_INDIRECT_COMMAND */ "", 5489 /* CGM_INDIRECT_COMMAND_ADDRESS */ "", 5490 /* CGM_INDIRECT_COMMAND_DATA_INCREMENT */ "", 5491 /* CGM_INDIRECT_COMMAND_RD_DATA */ "", 5492 /* CGM_INDIRECT_COMMAND_WIDE_MEM */ "", 5493 /* CGM_INDIRECT_COMMAND_WR_DATA */ "", 5494 /* CGM_INDIRECT_FORCE_BUBBLE */ "", 5495 /* CGM_INDIRECT_WR_MASK */ "", 5496 /* CGM_INIT */ "", 5497 /* CGM_INSTRUMENTATION_SETTINGS */ "", 5498 /* CGM_INSTRUMENTATION_STATUS */ "", 5499 /* CGM_INTERRUPT_MASK_REGISTER */ "", 5500 /* CGM_INTERRUPT_REGISTER */ "", 5501 /* CGM_INTERRUPT_REGISTER_TEST */ "", 5502 /* CGM_INT_IRPP_STAT_SETTINGS */ "", 5503 /* CGM_INT_TM_STAT_SETTINGS */ "", 5504 /* CGM_INVALID_CUD */ "", 5505 /* CGM_INVALID_DESTINATION_QUEUE */ "", 5506 /* CGM_IPT_SRAM_TO_DRAM_CMD_NRDY_CTR */ "", 5507 /* CGM_IPT_TX_CMD_NRDY_CTR */ "", 5508 /* CGM_IRPP_CTR_PTR_A_PKT_CTR */ "", 5509 /* CGM_IRPP_CTR_PTR_A_PKT_FILTERED_CTR */ "", 5510 /* CGM_IRPP_CTR_PTR_B_PKT_CTR */ "", 5511 /* CGM_IRPP_CTR_PTR_B_PKT_FILTERED_CTR */ "", 5512 /* CGM_IRPP_CTR_PTR_SETTINGS */ "", 5513 /* CGM_LAST_DRAM_ENQ_CMD */ "", 5514 /* CGM_LAST_REAS_RPRT */ "", 5515 /* CGM_LAST_SRAM_ENQ_CMD */ "", 5516 /* CGM_LM_CTR_CMD_FILTER */ "", 5517 /* CGM_LOW_PRIORITY_CONGESTION_INTERRUPT_ENABLERS */ "", 5518 /* CGM_LOW_PRIORITY_INTERRUPT_REGISTER */ "", 5519 /* CGM_LOW_PRIORITY_INTERRUPT_REGISTER_MASK */ "", 5520 /* CGM_LOW_PRIORITY_INTERRUPT_REGISTER_TEST */ "", 5521 /* CGM_MAX_PB_VSQ_QSIZE_TRACK_SETTINGS */ "", 5522 /* CGM_MAX_PB_VSQ_SRAM_BUFFERS_QSIZE_TRACK */ "", 5523 /* CGM_MAX_PB_VSQ_SRAM_PDS_QSIZE_TRACK */ "", 5524 /* CGM_MAX_PB_VSQ_WORDS_QSIZE_TRACK */ "", 5525 /* CGM_MAX_QB_VSQ_QSIZE_TRACK_SETTINGS */ "", 5526 /* CGM_MAX_QB_VSQ_SRAM_BUFFERS_QSIZE_TRACK */ "", 5527 /* CGM_MAX_QB_VSQ_SRAM_PDS_QSIZE_TRACK */ "", 5528 /* CGM_MAX_QB_VSQ_WORDS_QSIZE_TRACK */ "", 5529 /* CGM_MAX_VOQ_QSIZE_TRACK_SETTINGS */ "", 5530 /* CGM_MAX_VOQ_SRAM_BUFFERS_QSIZE_TRACK */ "", 5531 /* CGM_MAX_VOQ_SRAM_PDS_QSIZE_TRACK */ "", 5532 /* CGM_MAX_VOQ_SRAM_WORDS_QSIZE_TRACK */ "", 5533 /* CGM_MAX_VOQ_WORDS_QSIZE_TRACK */ "", 5534 /* CGM_MAX_VSQA_SRAM_BUFFERS_QSIZE_TRACK */ "", 5535 /* CGM_MAX_VSQA_SRAM_PDS_QSIZE_TRACK */ "", 5536 /* CGM_MAX_VSQA_WORDS_QSIZE_TRACK */ "", 5537 /* CGM_MAX_VSQB_SRAM_BUFFERS_QSIZE_TRACK */ "", 5538 /* CGM_MAX_VSQB_SRAM_PDS_QSIZE_TRACK */ "", 5539 /* CGM_MAX_VSQB_WORDS_QSIZE_TRACK */ "", 5540 /* CGM_MAX_VSQC_SRAM_BUFFERS_QSIZE_TRACK */ "", 5541 /* CGM_MAX_VSQC_SRAM_PDS_QSIZE_TRACK */ "", 5542 /* CGM_MAX_VSQC_WORDS_QSIZE_TRACK */ "", 5543 /* CGM_MAX_VSQD_SRAM_BUFFERS_QSIZE_TRACK */ "", 5544 /* CGM_MAX_VSQD_SRAM_PDS_QSIZE_TRACK */ "", 5545 /* CGM_MAX_VSQD_WORDS_QSIZE_TRACK */ "", 5546 /* CGM_MAX_VSQE_SRAM_BUFFERS_QSIZE_TRACK */ "", 5547 /* CGM_MAX_VSQE_SRAM_PDS_QSIZE_TRACK */ "", 5548 /* CGM_MAX_VSQE_WORDS_QSIZE_TRACK */ "", 5549 /* CGM_MAX_VSQF_SRAM_BUFFERS_QSIZE_TRACK */ "", 5550 /* CGM_MAX_VSQF_SRAM_PDS_QSIZE_TRACK */ "", 5551 /* CGM_MAX_VSQF_WORDS_QSIZE_TRACK */ "", 5552 /* CGM_MCH_FWD_RX_REP_CTR */ "", 5553 /* CGM_MCH_MIRROR_PKT_DROP_CTR */ "", 5554 /* CGM_MCH_SNIF_0_PKT_DROP_CTR */ "", 5555 /* CGM_MCH_SNIF_0_RX_REP_CTR */ "", 5556 /* CGM_MCH_SNIF_1_PKT_DROP_CTR */ "", 5557 /* CGM_MCH_SNIF_1_RX_REP_CTR */ "", 5558 /* CGM_MCH_SNIF_2_PKT_DROP_CTR */ "", 5559 /* CGM_MCH_SNIF_2_RX_REP_CTR */ "", 5560 /* CGM_MCH_SNOOP_PKT_DROP_CTR */ "", 5561 /* CGM_MCL_FWD_RX_REP_CTR */ "", 5562 /* CGM_MCL_MIRROR_PKT_DROP_CTR */ "", 5563 /* CGM_MCL_SNIF_0_PKT_DROP_CTR */ "", 5564 /* CGM_MCL_SNIF_0_RX_REP_CTR */ "", 5565 /* CGM_MCL_SNIF_1_PKT_DROP_CTR */ "", 5566 /* CGM_MCL_SNIF_1_RX_REP_CTR */ "", 5567 /* CGM_MCL_SNIF_2_PKT_DROP_CTR */ "", 5568 /* CGM_MCL_SNIF_2_RX_REP_CTR */ "", 5569 /* CGM_MCL_SNOOP_PKT_DROP_CTR */ "", 5570 /* CGM_MC_DB_CNT */ "", 5571 /* CGM_MC_DB_CNT_MAX_VALUE */ "", 5572 /* CGM_MC_DB_SP_0_CNT */ "", 5573 /* CGM_MC_DB_SP_0_CNT_MAX_VALUE */ "", 5574 /* CGM_MC_DB_SP_1_CNT */ "", 5575 /* CGM_MC_DB_SP_1_CNT_MAX_VALUE */ "", 5576 /* CGM_MC_DB_SP_TC_CNT */ "", 5577 /* CGM_MC_DB_SP_TC_CNT_MAX_VALUE */ "", 5578 /* CGM_MC_FIFO_FULL_PKT_CTR */ "", 5579 /* CGM_MC_PD_CNT */ "", 5580 /* CGM_MC_PD_CNT_MAX_VALUE */ "", 5581 /* CGM_MC_PD_IF_CNT */ "", 5582 /* CGM_MC_PD_IF_CNT_MAX_VALUE */ "", 5583 /* CGM_MC_PD_SP_0_CNT */ "", 5584 /* CGM_MC_PD_SP_0_CNT_MAX_VALUE */ "", 5585 /* CGM_MC_PD_SP_1_CNT */ "", 5586 /* CGM_MC_PD_SP_1_CNT_MAX_VALUE */ "", 5587 /* CGM_MC_PD_SP_TC_CNT */ "", 5588 /* CGM_MC_PD_SP_TC_CNT_MAX_VALUE */ "", 5589 /* CGM_MC_REP_ERR_PKT_CTR */ "", 5590 /* CGM_MC_RSVD_DB_SP_0_CNT */ "", 5591 /* CGM_MC_RSVD_DB_SP_1_CNT */ "", 5592 /* CGM_MC_RSVD_PD_SP_0_CNT */ "", 5593 /* CGM_MC_RSVD_PD_SP_1_CNT */ "", 5594 /* CGM_MC_SIZE_256_IF_CNT */ "", 5595 /* CGM_MC_SIZE_256_IF_CNT_MAX_VALUE */ "", 5596 /* CGM_MC_TC_PRIORITY_MAP */ "", 5597 /* CGM_MICRO_BURST_SETTINGS */ "", 5598 /* CGM_MICRO_BURST_STATUS */ "", 5599 /* CGM_MIRROR_RJCT_ACTION */ "", 5600 /* CGM_MIRROR_RJCT_REASON_MASK */ "", 5601 /* CGM_MIRROR_RJCT_SETTINGS */ "", 5602 /* CGM_MRPS_METER_CMD_NRDY_CTR */ "", 5603 /* CGM_MULTICAST_DATA_BUFFERS_COUNTER */ "", 5604 /* CGM_MULTICAST_DATA_BUFFERS_DROP_COUNTER */ "", 5605 /* CGM_MULTICAST_REPLICATIONS_PACKET_DESCRIPTORS_COUNTER */ "", 5606 /* CGM_MULTICAST_REPLICATIONS_PACKET_DESCRIPTORS_DROP_COUNTER */ "", 5607 /* CGM_MULTICAST_REPLICATIONS_QUEUE_LENGTH_DROP_COUNTER */ "", 5608 /* CGM_PB_VSQ_FC_STATUS */ "", 5609 /* CGM_PB_VSQ_GLOBAL_FC_STATUS */ "", 5610 /* CGM_PB_VSQ_LLFC_CONGESTION_FIFO_DATA */ "", 5611 /* CGM_PB_VSQ_PG_CONGESTION_FIFO_DATA */ "", 5612 /* CGM_PB_VSQ_RJCT_SETTINGS */ "", 5613 /* CGM_PB_VSQ_SHRD_FR_RJCT_STATUS */ "", 5614 /* CGM_PB_VSQ_SHRD_OC_RJCT_STATUS */ "", 5615 /* CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_MAX_OC */ "", 5616 /* CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_OC */ "", 5617 /* CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_0_MAX_OC */ "", 5618 /* CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_0_OC */ "", 5619 /* CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_1_MAX_OC */ "", 5620 /* CGM_PB_VSQ_SRAM_BUFFERS_GRNTD_POOL_1_OC */ "", 5621 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_0_FR */ "", 5622 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_0_MAX_OC */ "", 5623 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_0_OC */ "", 5624 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_1_FR */ "", 5625 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_1_MAX_OC */ "", 5626 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_EXT_POOL_1_OC */ "", 5627 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_FR */ "", 5628 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_MAX_OC */ "", 5629 /* CGM_PB_VSQ_SRAM_BUFFERS_HDRM_OC */ "", 5630 /* CGM_PB_VSQ_SRAM_BUFFERS_OC_TH */ "", 5631 /* CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_0_FR */ "", 5632 /* CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_0_MAX_OC */ "", 5633 /* CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_0_OC */ "", 5634 /* CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_1_FR */ "", 5635 /* CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_1_MAX_OC */ "", 5636 /* CGM_PB_VSQ_SRAM_BUFFERS_SHRD_POOL_1_OC */ "", 5637 /* CGM_PB_VSQ_SRAM_PDS_GRNTD_MAX_OC */ "", 5638 /* CGM_PB_VSQ_SRAM_PDS_GRNTD_OC */ "", 5639 /* CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_0_MAX_OC */ "", 5640 /* CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_0_OC */ "", 5641 /* CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_1_MAX_OC */ "", 5642 /* CGM_PB_VSQ_SRAM_PDS_GRNTD_POOL_1_OC */ "", 5643 /* CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_0_FR */ "", 5644 /* CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_0_MAX_OC */ "", 5645 /* CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_0_OC */ "", 5646 /* CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_1_FR */ "", 5647 /* CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_1_MAX_OC */ "", 5648 /* CGM_PB_VSQ_SRAM_PDS_HDRM_EXT_POOL_1_OC */ "", 5649 /* CGM_PB_VSQ_SRAM_PDS_HDRM_FR */ "", 5650 /* CGM_PB_VSQ_SRAM_PDS_HDRM_MAX_OC */ "", 5651 /* CGM_PB_VSQ_SRAM_PDS_HDRM_OC */ "", 5652 /* CGM_PB_VSQ_SRAM_PDS_OC_TH */ "", 5653 /* CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_0_FR */ "", 5654 /* CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_0_MAX_OC */ "", 5655 /* CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_0_OC */ "", 5656 /* CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_1_FR */ "", 5657 /* CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_1_MAX_OC */ "", 5658 /* CGM_PB_VSQ_SRAM_PDS_SHRD_POOL_1_OC */ "", 5659 /* CGM_PB_VSQ_WORDS_GRNTD_MAX_OC */ "", 5660 /* CGM_PB_VSQ_WORDS_GRNTD_OC */ "", 5661 /* CGM_PB_VSQ_WORDS_GRNTD_POOL_0_MAX_OC */ "", 5662 /* CGM_PB_VSQ_WORDS_GRNTD_POOL_0_OC */ "", 5663 /* CGM_PB_VSQ_WORDS_GRNTD_POOL_1_MAX_OC */ "", 5664 /* CGM_PB_VSQ_WORDS_GRNTD_POOL_1_OC */ "", 5665 /* CGM_PB_VSQ_WORDS_HDRM_FR */ "", 5666 /* CGM_PB_VSQ_WORDS_HDRM_MAX_OC */ "", 5667 /* CGM_PB_VSQ_WORDS_HDRM_OC */ "", 5668 /* CGM_PB_VSQ_WORDS_OC_TH */ "", 5669 /* CGM_PB_VSQ_WORDS_SHRD_POOL_0_FR */ "", 5670 /* CGM_PB_VSQ_WORDS_SHRD_POOL_0_MAX_OC */ "", 5671 /* CGM_PB_VSQ_WORDS_SHRD_POOL_0_OC */ "", 5672 /* CGM_PB_VSQ_WORDS_SHRD_POOL_1_FR */ "", 5673 /* CGM_PB_VSQ_WORDS_SHRD_POOL_1_MAX_OC */ "", 5674 /* CGM_PB_VSQ_WORDS_SHRD_POOL_1_OC */ "", 5675 /* CGM_PCMI_0 */ "", 5676 /* CGM_PCMI_1 */ "", 5677 /* CGM_PCMI_2 */ "", 5678 /* CGM_PCMI_3 */ "", 5679 /* CGM_PCMI_4 */ "", 5680 /* CGM_PCMI_0_S */ "", 5681 /* CGM_PCMI_0_T */ "", 5682 /* CGM_PCMI_1_S */ "", 5683 /* CGM_PCMI_1_T */ "", 5684 /* CGM_PCMI_2_S */ "", 5685 /* CGM_PCMI_2_T */ "", 5686 /* CGM_PCMI_3_S */ "", 5687 /* CGM_PCMI_3_T */ "", 5688 /* CGM_PCMI_4_S */ "", 5689 /* CGM_PCMI_4_T */ "", 5690 /* CGM_PKT_SIZE_ERR_PKT_CTR */ "", 5691 /* CGM_PQP_DISCARD_REASONS */ "", 5692 /* CGM_PRG_CTR_SETTINGS */ "", 5693 /* CGM_PRG_RJCT_PKT_CTR_0 */ "", 5694 /* CGM_PRG_RJCT_PKT_CTR_1 */ "", 5695 /* CGM_PRG_RJCT_PKT_CTR_2 */ "", 5696 /* CGM_PRG_RJCT_PKT_CTR_3 */ "", 5697 /* CGM_PRG_RJCT_PKT_CTR_4 */ "", 5698 /* CGM_PRG_RJCT_PKT_CTR_5 */ "", 5699 /* CGM_PRG_RJCT_PKT_CTR_6 */ "", 5700 /* CGM_PRG_RJCT_PKT_CTR_7 */ "", 5701 /* CGM_PRG_RJCT_PKT_CTR_0_MASK */ "", 5702 /* CGM_PRG_RJCT_PKT_CTR_1_MASK */ "", 5703 /* CGM_PRG_RJCT_PKT_CTR_2_MASK */ "", 5704 /* CGM_PRG_RJCT_PKT_CTR_3_MASK */ "", 5705 /* CGM_PRG_RJCT_PKT_CTR_4_MASK */ "", 5706 /* CGM_PRG_RJCT_PKT_CTR_5_MASK */ "", 5707 /* CGM_PRG_RJCT_PKT_CTR_6_MASK */ "", 5708 /* CGM_PRG_RJCT_PKT_CTR_7_MASK */ "", 5709 /* CGM_QB_VSQ_FC_STATUS */ "", 5710 /* CGM_QDC_ERR_INTERRUPT_REGISTER */ "", 5711 /* CGM_QDC_ERR_INTERRUPT_REGISTER_MASK */ "", 5712 /* CGM_QDC_ERR_INTERRUPT_REGISTER_TEST */ "", 5713 /* CGM_QNUM_NOT_VALID_PKT_CTR */ "", 5714 /* CGM_QNUM_RES_ERR_PKT_CTR */ "", 5715 /* CGM_REAS_RPRT_CTR */ "", 5716 /* CGM_RECOVERY_CACHE_SETTINGS */ "", 5717 /* CGM_REG_0041 */ "", 5718 /* CGM_REG_0202 */ "", 5719 /* CGM_REG_0275 */ "", 5720 /* CGM_REG_0305 */ "", 5721 /* CGM_REG_0335 */ "", 5722 /* CGM_REG_0365 */ "", 5723 /* CGM_REG_0395 */ "", 5724 /* CGM_REG_0400 */ "", 5725 /* CGM_REG_0402 */ "", 5726 /* CGM_REG_0500 */ "", 5727 /* CGM_REG_0501 */ "", 5728 /* CGM_REG_0504 */ "", 5729 /* CGM_REG_0505 */ "", 5730 /* CGM_REG_0507 */ "", 5731 /* CGM_REG_0508 */ "", 5732 /* CGM_REG_0510 */ "", 5733 /* CGM_REG_0511 */ "", 5734 /* CGM_REG_0512 */ "", 5735 /* CGM_REG_0514 */ "", 5736 /* CGM_REG_0516 */ "", 5737 /* CGM_REG_0517 */ "", 5738 /* CGM_REG_0519 */ "", 5739 /* CGM_REG_00C2 */ "", 5740 /* CGM_REG_00C5 */ "", 5741 /* CGM_REG_00C7 */ "", 5742 /* CGM_REG_025C */ "", 5743 /* CGM_REG_025D */ "", 5744 /* CGM_REG_027E */ "", 5745 /* CGM_REG_028D */ "", 5746 /* CGM_REG_02A5 */ "", 5747 /* CGM_REG_02BD */ "", 5748 /* CGM_REG_02D5 */ "", 5749 /* CGM_REG_02ED */ "", 5750 /* CGM_REG_031D */ "", 5751 /* CGM_REG_034D */ "", 5752 /* CGM_REG_037D */ "", 5753 /* CGM_REG_03AD */ "", 5754 /* CGM_REG_03C5 */ "", 5755 /* CGM_REG_03DD */ "", 5756 /* CGM_REG_03E6 */ "", 5757 /* CGM_REG_03E8 */ "", 5758 /* CGM_REG_03E9 */ "", 5759 /* CGM_REG_03EC */ "", 5760 /* CGM_REG_03ED */ "", 5761 /* CGM_REG_03EE */ "", 5762 /* CGM_REG_03F2 */ "", 5763 /* CGM_REG_03F3 */ "", 5764 /* CGM_REG_03F6 */ "", 5765 /* CGM_REG_03F8 */ "", 5766 /* CGM_REG_03FA */ "", 5767 /* CGM_REG_03FB */ "", 5768 /* CGM_REG_03FE */ "", 5769 /* CGM_REG_04F2 */ "", 5770 /* CGM_REG_04F3 */ "", 5771 /* CGM_REG_04F4 */ "", 5772 /* CGM_REG_04F5 */ "", 5773 /* CGM_REG_04F6 */ "", 5774 /* CGM_REG_04F7 */ "", 5775 /* CGM_REG_04F9 */ "", 5776 /* CGM_REG_04FC */ "", 5777 /* CGM_REG_04FD */ "", 5778 /* CGM_REG_04FF */ "", 5779 /* CGM_REG_050B */ "", 5780 /* CGM_REG_050C */ "", 5781 /* CGM_REG_050D */ "", 5782 /* CGM_REG_050F */ "", 5783 /* CGM_REJECT_STATUS_BITMAP */ "", 5784 /* CGM_REP_CMD_FIFO_RJCT_STATUS */ "", 5785 /* CGM_RESERVED_MIRROR_ADDR */ "", 5786 /* CGM_RESERVED_MTCD */ "", 5787 /* CGM_RESERVED_MTCP */ "", 5788 /* CGM_RESERVED_PCMI_0 */ "", 5789 /* CGM_RESERVED_PCMI_1 */ "", 5790 /* CGM_RESERVED_PCMI_2 */ "", 5791 /* CGM_RESERVED_PCMI_3 */ "", 5792 /* CGM_RESERVED_PCMI_4 */ "", 5793 /* CGM_RESERVED_PCMI_0_S */ "", 5794 /* CGM_RESERVED_PCMI_0_T */ "", 5795 /* CGM_RESERVED_PCMI_1_S */ "", 5796 /* CGM_RESERVED_PCMI_1_T */ "", 5797 /* CGM_RESERVED_PCMI_2_S */ "", 5798 /* CGM_RESERVED_PCMI_2_T */ "", 5799 /* CGM_RESERVED_PCMI_3_S */ "", 5800 /* CGM_RESERVED_PCMI_3_T */ "", 5801 /* CGM_RESERVED_PCMI_4_S */ "", 5802 /* CGM_RESERVED_PCMI_4_T */ "", 5803 /* CGM_RESERVED_SPARE_0 */ "", 5804 /* CGM_RESERVED_SPARE_1 */ "", 5805 /* CGM_RESERVED_SPARE_2 */ "", 5806 /* CGM_RESERVED_SPARE_3 */ "", 5807 /* CGM_RQP_DISCARD_REASONS */ "", 5808 /* CGM_SBUS_BROADCAST_ID */ "", 5809 /* CGM_SBUS_LAST_IN_CHAIN */ "", 5810 /* CGM_SERVICE_POOL_0_MULTICAST_DATA_BUFFERS_COUNTER */ "", 5811 /* CGM_SERVICE_POOL_0_MULTICAST_PACKET_DESCRIPTORS_COUNTER */ "", 5812 /* CGM_SERVICE_POOL_0_RESERVED_DATA_BUFFERS */ "", 5813 /* CGM_SERVICE_POOL_0_RESERVED_PACKET_DESCRIPTORS */ "", 5814 /* CGM_SERVICE_POOL_1_MULTICAST_DATA_BUFFERS_COUNTER */ "", 5815 /* CGM_SERVICE_POOL_1_MULTICAST_PACKET_DESCRIPTORS_COUNTER */ "", 5816 /* CGM_SERVICE_POOL_1_RESERVED_DATA_BUFFERS */ "", 5817 /* CGM_SERVICE_POOL_1_RESERVED_PACKET_DESCRIPTORS */ "", 5818 /* CGM_SPB_PKT_RLS_NRDY_CTR */ "", 5819 /* CGM_SPECIAL_CLOCK_CONTROLS */ "", 5820 /* CGM_SQM_ENQ_CMD_NRDY_CTR */ "", 5821 /* CGM_SRAM_BUFFERS_FREE_MIN_STATUS */ "", 5822 /* CGM_SRAM_BUFFERS_FREE_STATUS */ "", 5823 /* CGM_SRAM_BUFFERS_RJCT_PKT_CTR */ "", 5824 /* CGM_SRAM_BUFFER_RLS_RPRT_BYTE_CTR */ "", 5825 /* CGM_SRAM_BUFFER_RLS_RPRT_PKT_CTR */ "", 5826 /* CGM_SRAM_BUFF_RLS_RPRT_CTR */ "", 5827 /* CGM_SRAM_HDRM_RSRC_FLOW_CONTROL_THS */ "", 5828 /* CGM_SRAM_PDBS_FREE_MIN_STATUS */ "", 5829 /* CGM_SRAM_PDBS_FREE_STATUS */ "", 5830 /* CGM_SRAM_PDBS_RJCT_PKT_CTR */ "", 5831 /* CGM_SRAM_RSRC_ERR_PKT_CTR */ "", 5832 /* CGM_STATISTICS_TRACKING_CONTROL */ "", 5833 /* CGM_STAT_DEQ_BILL_BUBBLE_REQ_CTR */ "", 5834 /* CGM_STAT_DEQ_QSIZE_BUBBLE_REQ_CTR */ "", 5835 /* CGM_STAT_ENQ_BILL_BUBBLE_REQ_CTR */ "", 5836 /* CGM_STAT_ENQ_QSIZE_BUBBLE_REQ_CTR */ "", 5837 /* CGM_ST_EGR_BILL_DEQ_RPRT_DROP_CTR */ "", 5838 /* CGM_ST_ING_BILL_DEQ_RPRT_DROP_CTR */ "", 5839 /* CGM_ST_ING_BILL_ENQ_RPRT_DROP_CTR */ "", 5840 /* CGM_ST_ING_BILL_SETTINGS */ "", 5841 /* CGM_ST_PORT_FC_SETTINGS */ "", 5842 /* CGM_ST_PORT_SETTINGS */ "", 5843 /* CGM_ST_QNUM_RANGE_FILTER */ "", 5844 /* CGM_ST_QSIZE_DEQ_RPRT_DROP_CTR */ "", 5845 /* CGM_ST_QSIZE_ENQ_RPRT_DROP_CTR */ "", 5846 /* CGM_ST_QSIZE_RPRT_PRD */ "", 5847 /* CGM_ST_QSIZE_RPRT_QSIZE_SEL */ "", 5848 /* CGM_ST_QSIZE_SCRB_RPRT_DROP_CTR */ "", 5849 /* CGM_ST_QSIZE_SCRB_SETTINGS */ "", 5850 /* CGM_ST_RPRT_RX_FIFO_ERR_INTERRUPT_REGISTER */ "", 5851 /* CGM_ST_RPRT_RX_FIFO_ERR_INTERRUPT_REGISTER_MASK */ "", 5852 /* CGM_ST_RPRT_RX_FIFO_ERR_INTERRUPT_REGISTER_TEST */ "", 5853 /* CGM_SYSTEM_RED_QSIZE_FR_RSRC_TH */ "", 5854 /* CGM_SYSTEM_RED_QSIZE_FR_SHRD_RSRC_TH */ "", 5855 /* CGM_SYSTEM_RED_QSIZE_MAX_STATUS */ "", 5856 /* CGM_SYSTEM_RED_QSIZE_STATUS */ "", 5857 /* CGM_SYSTEM_RED_RANGE_FR_RSRC_TH */ "", 5858 /* CGM_SYSTEM_RED_RANGE_FR_SHRD_RSRC_TH */ "", 5859 /* CGM_SYS_RED_SETTINGS */ "", 5860 /* CGM_TAR_FIFO_REJECT_STATUS */ "", 5861 /* CGM_TAR_FIFO_RJCT_PKT_CTR */ "", 5862 /* CGM_TAR_MCH_REP_FIFO_MAX_STATUS */ "", 5863 /* CGM_TAR_MCH_REP_FIFO_STATUS */ "", 5864 /* CGM_TAR_MCL_REP_FIFO_MAX_STATUS */ "", 5865 /* CGM_TAR_MCL_REP_FIFO_STATUS */ "", 5866 /* CGM_TAR_STATIC_CONFIGURATION */ "", 5867 /* CGM_TAR_UC_REP_FIFO_MAX_STATUS */ "", 5868 /* CGM_TAR_UC_REP_FIFO_STATUS */ "", 5869 /* CGM_TM_CTR_PTR_A_PKT_CTR */ "", 5870 /* CGM_TM_CTR_PTR_A_PKT_FILTERED_CTR */ "", 5871 /* CGM_TM_CTR_PTR_B_PKT_CTR */ "", 5872 /* CGM_TM_CTR_PTR_B_PKT_FILTERED_CTR */ "", 5873 /* CGM_TM_CTR_PTR_SETTINGS */ "", 5874 /* CGM_TOTAL_DATA_BUFFERS_COUNTER */ "", 5875 /* CGM_TOTAL_DB_CNT */ "", 5876 /* CGM_TOTAL_DB_CNT_MAX_VALUE */ "", 5877 /* CGM_TOTAL_DRAM_RSRC_FLOW_CONTROL_THS */ "", 5878 /* CGM_TOTAL_PACKET_DESCRIPTORS_COUNTER */ "", 5879 /* CGM_TOTAL_PB_VSQ_OC_ERR_INTERRUPT_REGISTER */ "", 5880 /* CGM_TOTAL_PB_VSQ_OC_ERR_INTERRUPT_REGISTER_MASK */ "", 5881 /* CGM_TOTAL_PB_VSQ_OC_ERR_INTERRUPT_REGISTER_TEST */ "", 5882 /* CGM_TOTAL_PD_CNT */ "", 5883 /* CGM_TOTAL_PD_CNT_MAX_VALUE */ "", 5884 /* CGM_TOTAL_SRAM_RSRC_FLOW_CONTROL_THS */ "", 5885 /* CGM_TOTAL_VOQ_OC_ERR_INTERRUPT_REGISTER */ "", 5886 /* CGM_TOTAL_VOQ_OC_ERR_INTERRUPT_REGISTER_MASK */ "", 5887 /* CGM_TOTAL_VOQ_OC_ERR_INTERRUPT_REGISTER_TEST */ "", 5888 /* CGM_UC_DB_CNT */ "", 5889 /* CGM_UC_DB_CNT_MAX_VALUE */ "", 5890 /* CGM_UC_FWD_RX_REP_CTR */ "", 5891 /* CGM_UC_MIRROR_PKT_DROP_CTR */ "", 5892 /* CGM_UC_PD_CNT */ "", 5893 /* CGM_UC_PD_CNT_MAX_VALUE */ "", 5894 /* CGM_UC_PD_IF_CNT */ "", 5895 /* CGM_UC_PD_IF_CNT_MAX_VALUE */ "", 5896 /* CGM_UC_SIZE_256_IF_CNT */ "", 5897 /* CGM_UC_SIZE_256_IF_CNT_MAX_VALUE */ "", 5898 /* CGM_UC_SNIF_0_PKT_DROP_CTR */ "", 5899 /* CGM_UC_SNIF_0_RX_REP_CTR */ "", 5900 /* CGM_UC_SNIF_1_PKT_DROP_CTR */ "", 5901 /* CGM_UC_SNIF_1_RX_REP_CTR */ "", 5902 /* CGM_UC_SNIF_2_PKT_DROP_CTR */ "", 5903 /* CGM_UC_SNIF_2_RX_REP_CTR */ "", 5904 /* CGM_UC_SNOOP_PKT_DROP_CTR */ "", 5905 /* CGM_UNICAST_DATA_BUFFERS_COUNTER */ "", 5906 /* CGM_UNICAST_DATA_BUFFERS_DROP_BY_PQP_COUNTER */ "", 5907 /* CGM_UNICAST_DATA_BUFFERS_DROP_BY_RQP_COUNTER */ "", 5908 /* CGM_UNICAST_PACKET_DESCRIPTORS_COUNTER */ "", 5909 /* CGM_UNICAST_PACKET_DESCRIPTORS_DROP_COUNTER */ "", 5910 /* CGM_VISIBILITY_RJCT_PKT_CTR */ "", 5911 /* CGM_VISIBILITY_SETTINGS */ "", 5912 /* CGM_VISIBILITY_SRAM_ENQ_DATA_0 */ "", 5913 /* CGM_VISIBILITY_SRAM_ENQ_DATA_1 */ "", 5914 /* CGM_VISIBILITY_SRAM_ENQ_DATA_2 */ "", 5915 /* CGM_VISIBILITY_TAR_DATA_0 */ "", 5916 /* CGM_VISIBILITY_TAR_DATA_1 */ "", 5917 /* CGM_VISIBILITY_TAR_DATA_2 */ "", 5918 /* CGM_VOQ_CONGESTION_FIFO_DATA */ "", 5919 /* CGM_VOQ_CTR_ERR_INTERRUPT_REGISTER */ "", 5920 /* CGM_VOQ_CTR_ERR_INTERRUPT_REGISTER_MASK */ "", 5921 /* CGM_VOQ_CTR_ERR_INTERRUPT_REGISTER_TEST */ "", 5922 /* CGM_VOQ_DRAM_BLOCK_BMP_MASK */ "", 5923 /* CGM_VOQ_DRAM_BLOCK_DP_TH */ "", 5924 /* CGM_VOQ_DRAM_BLOCK_RJCT_THRESHOLDS */ "", 5925 /* CGM_VOQ_DRAM_DEL_BUNDLE_BYTE_CTR */ "", 5926 /* CGM_VOQ_DRAM_DEL_BUNDLE_CTR */ "", 5927 /* CGM_VOQ_DRAM_DEL_BYTE_CTR */ "", 5928 /* CGM_VOQ_DRAM_DEL_PKT_CTR */ "", 5929 /* CGM_VOQ_DRAM_DEQ_BUNDLE_BYTE_CTR */ "", 5930 /* CGM_VOQ_DRAM_DEQ_BUNDLE_CTR */ "", 5931 /* CGM_VOQ_DRAM_DEQ_BYTE_CTR */ "", 5932 /* CGM_VOQ_DRAM_DEQ_PKT_CTR */ "", 5933 /* CGM_VOQ_DRAM_DEQ_RPRT_BYTE_CTR */ "", 5934 /* CGM_VOQ_DRAM_DEQ_RPRT_CTR */ "", 5935 /* CGM_VOQ_DRAM_DEQ_TO_FABRIC_BUNDLE_CTR */ "", 5936 /* CGM_VOQ_DRAM_DEQ_TO_FABRIC_BYTE_CTR */ "", 5937 /* CGM_VOQ_DRAM_ENQ_BUNDLE_BYTE_CTR */ "", 5938 /* CGM_VOQ_DRAM_ENQ_BUNDLE_CTR */ "", 5939 /* CGM_VOQ_DRAM_ENQ_RPRT_BYTE_CTR */ "", 5940 /* CGM_VOQ_DRAM_ENQ_RPRT_CTR */ "", 5941 /* CGM_VOQ_LATENCY_RJCT_SETTINGS */ "", 5942 /* CGM_VOQ_OCCUPANCY_ERR_QNUM */ "", 5943 /* CGM_VOQ_OCCUPANCY_ERR_STATUS */ "", 5944 /* CGM_VOQ_RJCT_SETTINGS */ "", 5945 /* CGM_VOQ_SHRD_OC_RJCT_STATUS */ "", 5946 /* CGM_VOQ_SHRD_OC_TH */ "", 5947 /* CGM_VOQ_SRAM_BUFFERS_GRNTD_MAX_OC */ "", 5948 /* CGM_VOQ_SRAM_BUFFERS_GRNTD_OC */ "", 5949 /* CGM_VOQ_SRAM_BUFFERS_SHRD_FR */ "", 5950 /* CGM_VOQ_SRAM_BUFFERS_SHRD_MAX_OC */ "", 5951 /* CGM_VOQ_SRAM_BUFFERS_SHRD_OC */ "", 5952 /* CGM_VOQ_SRAM_DEL_BYTE_CTR */ "", 5953 /* CGM_VOQ_SRAM_DEL_PKT_CTR */ "", 5954 /* CGM_VOQ_SRAM_DEQ_BYTE_CTR */ "", 5955 /* CGM_VOQ_SRAM_DEQ_PKT_CTR */ "", 5956 /* CGM_VOQ_SRAM_DEQ_RPRT_BYTE_CTR */ "", 5957 /* CGM_VOQ_SRAM_DEQ_RPRT_CTR */ "", 5958 /* CGM_VOQ_SRAM_DEQ_TO_DRAM_BYTE_CTR */ "", 5959 /* CGM_VOQ_SRAM_DEQ_TO_DRAM_PKT_CTR */ "", 5960 /* CGM_VOQ_SRAM_DEQ_TO_FABRIC_BYTE_CTR */ "", 5961 /* CGM_VOQ_SRAM_DEQ_TO_FABRIC_PKT_CTR */ "", 5962 /* CGM_VOQ_SRAM_ENQ_BYTE_CTR */ "", 5963 /* CGM_VOQ_SRAM_ENQ_PKT_CTR */ "", 5964 /* CGM_VOQ_SRAM_ENQ_RJCT_BYTE_CTR */ "", 5965 /* CGM_VOQ_SRAM_ENQ_RJCT_PKT_CTR */ "", 5966 /* CGM_VOQ_SRAM_ENQ_RPRT_BYTE_CTR */ "", 5967 /* CGM_VOQ_SRAM_ENQ_RPRT_CTR */ "", 5968 /* CGM_VOQ_SRAM_LCD_BYTE_CTR */ "", 5969 /* CGM_VOQ_SRAM_LCD_PKT_CTR */ "", 5970 /* CGM_VOQ_SRAM_PDS_GRNTD_MAX_OC */ "", 5971 /* CGM_VOQ_SRAM_PDS_GRNTD_OC */ "", 5972 /* CGM_VOQ_SRAM_PDS_SHRD_FR */ "", 5973 /* CGM_VOQ_SRAM_PDS_SHRD_MAX_OC */ "", 5974 /* CGM_VOQ_SRAM_PDS_SHRD_OC */ "", 5975 /* CGM_VOQ_SRAM_WORDS_GRNTD_MAX_OC */ "", 5976 /* CGM_VOQ_SRAM_WORDS_GRNTD_OC */ "", 5977 /* CGM_VOQ_SRAM_WORDS_SHRD_FR */ "", 5978 /* CGM_VOQ_SRAM_WORDS_SHRD_MAX_OC */ "", 5979 /* CGM_VOQ_SRAM_WORDS_SHRD_OC */ "", 5980 /* CGM_VOQ_WORDS_GRNTD_MAX_OC */ "", 5981 /* CGM_VOQ_WORDS_GRNTD_OC */ "", 5982 /* CGM_VOQ_WORDS_SHRD_FR */ "", 5983 /* CGM_VOQ_WORDS_SHRD_MAX_OC */ "", 5984 /* CGM_VOQ_WORDS_SHRD_OC */ "", 5985 /* CGM_VSQA_FC_STATUS_MASK */ "", 5986 /* CGM_VSQA_OCCUPANCY_ERR_STATUS */ "", 5987 /* CGM_VSQB_FC_STATUS_MASK */ "", 5988 /* CGM_VSQB_OCCUPANCY_ERR_STATUS */ "", 5989 /* CGM_VSQC_FC_STATUS_MASK */ "", 5990 /* CGM_VSQC_OCCUPANCY_ERR_STATUS */ "", 5991 /* CGM_VSQD_FC_STATUS_MASK */ "", 5992 /* CGM_VSQD_OCCUPANCY_ERR_STATUS */ "", 5993 /* CGM_VSQE_FC_STATUS_MASK */ "", 5994 /* CGM_VSQE_OCCUPANCY_ERR_STATUS */ "", 5995 /* CGM_VSQF_FC_STATUS_MASK */ "", 5996 /* CGM_VSQF_OCCUPANCY_ERR_STATUS */ "", 5997 /* CGM_VSQ_CATEGORY_RANGES */ "", 5998 /* CGM_VSQ_CTR_ERR_INTERRUPT_REGISTER */ "", 5999 /* CGM_VSQ_CTR_ERR_INTERRUPT_REGISTER_MASK */ "", 6000 /* CGM_VSQ_CTR_ERR_INTERRUPT_REGISTER_TEST */ "", 6001 /* CGM_VSQ_DRAM_DEL_BYTE_CTR */ "", 6002 /* CGM_VSQ_DRAM_DEL_PKT_CTR */ "", 6003 /* CGM_VSQ_DRAM_DEQ_BYTE_CTR */ "", 6004 /* CGM_VSQ_DRAM_DEQ_PKT_CTR */ "", 6005 /* CGM_VSQ_FC_STATUS */ "", 6006 /* CGM_VSQ_OCCUPANCY_ERR_QNUM */ "", 6007 /* CGM_VSQ_SETTINGS */ "", 6008 /* CGM_VSQ_SRAM_DEL_BYTE_CTR */ "", 6009 /* CGM_VSQ_SRAM_DEL_PKT_CTR */ "", 6010 /* CGM_VSQ_SRAM_DEQ_BYTE_CTR */ "", 6011 /* CGM_VSQ_SRAM_DEQ_PKT_CTR */ "", 6012 /* CGM_VSQ_SRAM_DEQ_TO_DRAM_BYTE_CTR */ "", 6013 /* CGM_VSQ_SRAM_DEQ_TO_DRAM_PKT_CTR */ "", 6014 /* CGM_VSQ_SRAM_DEQ_TO_FABRIC_BYTE_CTR */ "", 6015 /* CGM_VSQ_SRAM_DEQ_TO_FABRIC_PKT_CTR */ "", 6016 /* CGM_VSQ_SRAM_ENQ_BYTE_CTR */ "", 6017 /* CGM_VSQ_SRAM_ENQ_PKT_CTR */ "", 6018 /* CGM_VSQ_SRAM_ENQ_RJCT_BYTE_CTR */ "", 6019 /* CGM_VSQ_SRAM_ENQ_RJCT_PKT_CTR */ "", 6020 /* CGM_XOR_MEM_INIT_DONE */ "", 6021 /* CHFC2PFC_STATE */ "", 6022 /* CHFC_TC2PRI_TBL_ECC_CONFIG */ "", 6023 /* CHFC_TC2PRI_TBL_ECC_ERR1 */ "", 6024 /* CHFC_TC2PRI_TBL_ECC_ERR2 */ "", 6025 /* CHFC_TC2PRI_TBL_ECC_ERR1_CNT */ "", 6026 /* CHIPCOMMONA_CAPABILITIESEXTENSION */ "", 6027 /* CHIPCOMMONA_CHIPCTRL */ "", 6028 /* CHIPCOMMONA_CHIPID */ "", 6029 /* CHIPCOMMONA_CHIPSTATUS */ "", 6030 /* CHIPCOMMONA_CLKDIV */ "", 6031 /* CHIPCOMMONA_CLKDIV2 */ "", 6032 /* CHIPCOMMONA_CLOCKCTLSTATUS */ "", 6033 /* CHIPCOMMONA_CORECAPABILITIES */ "", 6034 /* CHIPCOMMONA_CORECTRL */ "", 6035 /* CHIPCOMMONA_EROM_PTR_OFFSET */ "", 6036 /* CHIPCOMMONA_GPIODEBUGSEL */ "", 6037 /* CHIPCOMMONA_GPIOEVENT */ "", 6038 /* CHIPCOMMONA_GPIOEVENTINTMASK */ "", 6039 /* CHIPCOMMONA_GPIOEVENTINTPOLARITY */ "", 6040 /* CHIPCOMMONA_GPIOINPUT */ "", 6041 /* CHIPCOMMONA_GPIOINTMASK */ "", 6042 /* CHIPCOMMONA_GPIOINTPOLARITY */ "", 6043 /* CHIPCOMMONA_GPIOOUT */ "", 6044 /* CHIPCOMMONA_GPIOOUTEN */ "", 6045 /* CHIPCOMMONA_GPIOTIMEROUTMASK */ "", 6046 /* CHIPCOMMONA_GPIOTIMERVAL */ "", 6047 /* CHIPCOMMONA_GSIOADDRESS */ "", 6048 /* CHIPCOMMONA_GSIOCTRL */ "", 6049 /* CHIPCOMMONA_GSIODATA */ "", 6050 /* CHIPCOMMONA_INTMASK */ "", 6051 /* CHIPCOMMONA_INTSTATUS */ "", 6052 /* CHIPCOMMONA_JTAGMASTERCMD */ "", 6053 /* CHIPCOMMONA_JTAGMASTERCTRL */ "", 6054 /* CHIPCOMMONA_JTAGMASTERDATA */ "", 6055 /* CHIPCOMMONA_JTAGMASTERINSTR */ "", 6056 /* CHIPCOMMONA_OTPCTRL */ "", 6057 /* CHIPCOMMONA_OTPCTRL1 */ "", 6058 /* CHIPCOMMONA_OTPLAYOUT */ "", 6059 /* CHIPCOMMONA_OTPPROG */ "", 6060 /* CHIPCOMMONA_OTPSTATUS */ "", 6061 /* CHIPCOMMONA_UART0_DLH_IER */ "", 6062 /* CHIPCOMMONA_UART0_IIR_FCR */ "", 6063 /* CHIPCOMMONA_UART0_LCR */ "", 6064 /* CHIPCOMMONA_UART0_LSR */ "", 6065 /* CHIPCOMMONA_UART0_MCR */ "", 6066 /* CHIPCOMMONA_UART0_MSR */ "", 6067 /* CHIPCOMMONA_UART0_RBR_THR_DLL */ "", 6068 /* CHIPCOMMONA_UART0_SCR */ "", 6069 /* CHIPCOMMONA_UART1_DLH_IER */ "", 6070 /* CHIPCOMMONA_UART1_IIR_FCR */ "", 6071 /* CHIPCOMMONA_UART1_LCR */ "", 6072 /* CHIPCOMMONA_UART1_LSR */ "", 6073 /* CHIPCOMMONA_UART1_MCR */ "", 6074 /* CHIPCOMMONA_UART1_MSR */ "", 6075 /* CHIPCOMMONA_UART1_RBR_THR_DLL */ "", 6076 /* CHIPCOMMONA_UART1_SCR */ "", 6077 /* CHIPCOMMONA_WATCHDOGCOUNTER */ "", 6078 /* CHIPCOMMONB_GP_AUX_SEL */ "", 6079 /* CHIPCOMMONB_GP_DATA_IN */ "", 6080 /* CHIPCOMMONB_GP_DATA_OUT */ "", 6081 /* CHIPCOMMONB_GP_INIT_VAL */ "", 6082 /* CHIPCOMMONB_GP_INT_CLR */ "", 6083 /* CHIPCOMMONB_GP_INT_DE */ "", 6084 /* CHIPCOMMONB_GP_INT_EDGE */ "", 6085 /* CHIPCOMMONB_GP_INT_MSK */ "", 6086 /* CHIPCOMMONB_GP_INT_MSTAT */ "", 6087 /* CHIPCOMMONB_GP_INT_STAT */ "", 6088 /* CHIPCOMMONB_GP_INT_TYPE */ "", 6089 /* CHIPCOMMONB_GP_OUT_EN */ "", 6090 /* CHIPCOMMONB_GP_PAD_RES */ "", 6091 /* CHIPCOMMONB_GP_PRB_ENABLE */ "", 6092 /* CHIPCOMMONB_GP_PRB_OE */ "", 6093 /* CHIPCOMMONB_GP_RES_EN */ "", 6094 /* CHIPCOMMONB_GP_TEST_ENABLE */ "", 6095 /* CHIPCOMMONB_GP_TEST_INPUT */ "", 6096 /* CHIPCOMMONB_GP_TEST_OUTPUT */ "", 6097 /* CHIPCOMMONB_MII_MANAGEMENT_COMMAND_DATA */ "", 6098 /* CHIPCOMMONB_MII_MANAGEMENT_CONTROL */ "", 6099 /* CHIPCOMMONB_PKA_CONTROL_STATUS */ "", 6100 /* CHIPCOMMONB_PKA_DATA_INPUT */ "", 6101 /* CHIPCOMMONB_PKA_DATA_OUTPUT */ "", 6102 /* CHIPCOMMONB_PKA_SCA_LFSR_SEED */ "", 6103 /* CHIPCOMMONB_PWMCTL */ "", 6104 /* CHIPCOMMONB_PWM_DUTYHI_COUNT0 */ "", 6105 /* CHIPCOMMONB_PWM_DUTYHI_COUNT1 */ "", 6106 /* CHIPCOMMONB_PWM_DUTYHI_COUNT2 */ "", 6107 /* CHIPCOMMONB_PWM_DUTYHI_COUNT3 */ "", 6108 /* CHIPCOMMONB_PWM_PERIOD_COUNT0 */ "", 6109 /* CHIPCOMMONB_PWM_PERIOD_COUNT1 */ "", 6110 /* CHIPCOMMONB_PWM_PERIOD_COUNT2 */ "", 6111 /* CHIPCOMMONB_PWM_PERIOD_COUNT3 */ "", 6112 /* CHIPCOMMONB_PWM_PRESCALE */ "", 6113 /* CHIPCOMMONB_RNG_CTRL */ "", 6114 /* CHIPCOMMONB_RNG_DATA */ "", 6115 /* CHIPCOMMONB_RNG_FF_THRES */ "", 6116 /* CHIPCOMMONB_RNG_INT_MASK */ "", 6117 /* CHIPCOMMONB_RNG_STATUS */ "", 6118 /* CHIPCOMMONB_SMBUS1_SMBUS_ADDRESS */ "", 6119 /* CHIPCOMMONB_SMBUS1_SMBUS_BIT_BANG_CONTROL */ "", 6120 /* CHIPCOMMONB_SMBUS1_SMBUS_CONFIG */ "", 6121 /* CHIPCOMMONB_SMBUS1_SMBUS_EVENT_ENABLE */ "", 6122 /* CHIPCOMMONB_SMBUS1_SMBUS_EVENT_STATUS */ "", 6123 /* CHIPCOMMONB_SMBUS1_SMBUS_MASTER_COMMAND */ "", 6124 /* CHIPCOMMONB_SMBUS1_SMBUS_MASTER_DATA_READ */ "", 6125 /* CHIPCOMMONB_SMBUS1_SMBUS_MASTER_DATA_WRITE */ "", 6126 /* CHIPCOMMONB_SMBUS1_SMBUS_MASTER_FIFO_CONTROL */ "", 6127 /* CHIPCOMMONB_SMBUS1_SMBUS_SLAVE_COMMAND */ "", 6128 /* CHIPCOMMONB_SMBUS1_SMBUS_SLAVE_DATA_READ */ "", 6129 /* CHIPCOMMONB_SMBUS1_SMBUS_SLAVE_DATA_WRITE */ "", 6130 /* CHIPCOMMONB_SMBUS1_SMBUS_SLAVE_FIFO_CONTROL */ "", 6131 /* CHIPCOMMONB_SMBUS1_SMBUS_TIMING_CONFIG */ "", 6132 /* CHIPCOMMONB_SMBUS_ADDRESS */ "", 6133 /* CHIPCOMMONB_SMBUS_BIT_BANG_CONTROL */ "", 6134 /* CHIPCOMMONB_SMBUS_CONFIG */ "", 6135 /* CHIPCOMMONB_SMBUS_EVENT_ENABLE */ "", 6136 /* CHIPCOMMONB_SMBUS_EVENT_STATUS */ "", 6137 /* CHIPCOMMONB_SMBUS_MASTER_COMMAND */ "", 6138 /* CHIPCOMMONB_SMBUS_MASTER_DATA_READ */ "", 6139 /* CHIPCOMMONB_SMBUS_MASTER_DATA_WRITE */ "", 6140 /* CHIPCOMMONB_SMBUS_MASTER_FIFO_CONTROL */ "", 6141 /* CHIPCOMMONB_SMBUS_SLAVE_COMMAND */ "", 6142 /* CHIPCOMMONB_SMBUS_SLAVE_DATA_READ */ "", 6143 /* CHIPCOMMONB_SMBUS_SLAVE_DATA_WRITE */ "", 6144 /* CHIPCOMMONB_SMBUS_SLAVE_FIFO_CONTROL */ "", 6145 /* CHIPCOMMONB_SMBUS_TIMING_CONFIG */ "", 6146 /* CHIPCOMMONB_TIM0_TIM_TIMER1BGLOAD */ "", 6147 /* CHIPCOMMONB_TIM0_TIM_TIMER1CONTROL */ "", 6148 /* CHIPCOMMONB_TIM0_TIM_TIMER1INTCLR */ "", 6149 /* CHIPCOMMONB_TIM0_TIM_TIMER1LOAD */ "", 6150 /* CHIPCOMMONB_TIM0_TIM_TIMER1MIS */ "", 6151 /* CHIPCOMMONB_TIM0_TIM_TIMER1RIS */ "", 6152 /* CHIPCOMMONB_TIM0_TIM_TIMER1VALUE */ "", 6153 /* CHIPCOMMONB_TIM0_TIM_TIMER2BGLOAD */ "", 6154 /* CHIPCOMMONB_TIM0_TIM_TIMER2CONTROL */ "", 6155 /* CHIPCOMMONB_TIM0_TIM_TIMER2INTCLR */ "", 6156 /* CHIPCOMMONB_TIM0_TIM_TIMER2LOAD */ "", 6157 /* CHIPCOMMONB_TIM0_TIM_TIMER2MIS */ "", 6158 /* CHIPCOMMONB_TIM0_TIM_TIMER2RIS */ "", 6159 /* CHIPCOMMONB_TIM0_TIM_TIMER2VALUE */ "", 6160 /* CHIPCOMMONB_TIM0_TIM_TIMERITCR */ "", 6161 /* CHIPCOMMONB_TIM0_TIM_TIMERITOP */ "", 6162 /* CHIPCOMMONB_TIM0_TIM_TIMERPCELLID0 */ "", 6163 /* CHIPCOMMONB_TIM0_TIM_TIMERPCELLID1 */ "", 6164 /* CHIPCOMMONB_TIM0_TIM_TIMERPCELLID2 */ "", 6165 /* CHIPCOMMONB_TIM0_TIM_TIMERPCELLID3 */ "", 6166 /* CHIPCOMMONB_TIM0_TIM_TIMERPERIPHID0 */ "", 6167 /* CHIPCOMMONB_TIM0_TIM_TIMERPERIPHID1 */ "", 6168 /* CHIPCOMMONB_TIM0_TIM_TIMERPERIPHID2 */ "", 6169 /* CHIPCOMMONB_TIM0_TIM_TIMERPERIPHID3 */ "", 6170 /* CHIPCOMMONB_TIM1_TIM_TIMER1BGLOAD */ "", 6171 /* CHIPCOMMONB_TIM1_TIM_TIMER1CONTROL */ "", 6172 /* CHIPCOMMONB_TIM1_TIM_TIMER1INTCLR */ "", 6173 /* CHIPCOMMONB_TIM1_TIM_TIMER1LOAD */ "", 6174 /* CHIPCOMMONB_TIM1_TIM_TIMER1MIS */ "", 6175 /* CHIPCOMMONB_TIM1_TIM_TIMER1RIS */ "", 6176 /* CHIPCOMMONB_TIM1_TIM_TIMER1VALUE */ "", 6177 /* CHIPCOMMONB_TIM1_TIM_TIMER2BGLOAD */ "", 6178 /* CHIPCOMMONB_TIM1_TIM_TIMER2CONTROL */ "", 6179 /* CHIPCOMMONB_TIM1_TIM_TIMER2INTCLR */ "", 6180 /* CHIPCOMMONB_TIM1_TIM_TIMER2LOAD */ "", 6181 /* CHIPCOMMONB_TIM1_TIM_TIMER2MIS */ "", 6182 /* CHIPCOMMONB_TIM1_TIM_TIMER2RIS */ "", 6183 /* CHIPCOMMONB_TIM1_TIM_TIMER2VALUE */ "", 6184 /* CHIPCOMMONB_TIM1_TIM_TIMERITCR */ "", 6185 /* CHIPCOMMONB_TIM1_TIM_TIMERITOP */ "", 6186 /* CHIPCOMMONB_TIM1_TIM_TIMERPCELLID0 */ "", 6187 /* CHIPCOMMONB_TIM1_TIM_TIMERPCELLID1 */ "", 6188 /* CHIPCOMMONB_TIM1_TIM_TIMERPCELLID2 */ "", 6189 /* CHIPCOMMONB_TIM1_TIM_TIMERPCELLID3 */ "", 6190 /* CHIPCOMMONB_TIM1_TIM_TIMERPERIPHID0 */ "", 6191 /* CHIPCOMMONB_TIM1_TIM_TIMERPERIPHID1 */ "", 6192 /* CHIPCOMMONB_TIM1_TIM_TIMERPERIPHID2 */ "", 6193 /* CHIPCOMMONB_TIM1_TIM_TIMERPERIPHID3 */ "", 6194 /* CHIPCOMMONB_UART0_CPR */ "", 6195 /* CHIPCOMMONB_UART0_CTR */ "", 6196 /* CHIPCOMMONB_UART0_DLH_IER */ "", 6197 /* CHIPCOMMONB_UART0_DMASA */ "", 6198 /* CHIPCOMMONB_UART0_FAR */ "", 6199 /* CHIPCOMMONB_UART0_HTX */ "", 6200 /* CHIPCOMMONB_UART0_IIR_FCR */ "", 6201 /* CHIPCOMMONB_UART0_LCR */ "", 6202 /* CHIPCOMMONB_UART0_LPDLH */ "", 6203 /* CHIPCOMMONB_UART0_LPDLL */ "", 6204 /* CHIPCOMMONB_UART0_LSR */ "", 6205 /* CHIPCOMMONB_UART0_MCR */ "", 6206 /* CHIPCOMMONB_UART0_MSR */ "", 6207 /* CHIPCOMMONB_UART0_RBR_THR_DLL */ "", 6208 /* CHIPCOMMONB_UART0_RFL */ "", 6209 /* CHIPCOMMONB_UART0_RFW */ "", 6210 /* CHIPCOMMONB_UART0_SBCR */ "", 6211 /* CHIPCOMMONB_UART0_SCR */ "", 6212 /* CHIPCOMMONB_UART0_SDMAM */ "", 6213 /* CHIPCOMMONB_UART0_SFE */ "", 6214 /* CHIPCOMMONB_UART0_SRBR_STHR */ "", 6215 /* CHIPCOMMONB_UART0_SRR */ "", 6216 /* CHIPCOMMONB_UART0_SRT */ "", 6217 /* CHIPCOMMONB_UART0_SRTS */ "", 6218 /* CHIPCOMMONB_UART0_STET */ "", 6219 /* CHIPCOMMONB_UART0_TFL */ "", 6220 /* CHIPCOMMONB_UART0_TFR */ "", 6221 /* CHIPCOMMONB_UART0_UCV */ "", 6222 /* CHIPCOMMONB_UART0_USR */ "", 6223 /* CHIPCOMMONB_WDT_WDOGCONTROL */ "", 6224 /* CHIPCOMMONB_WDT_WDOGINTCLR */ "", 6225 /* CHIPCOMMONB_WDT_WDOGITCR */ "", 6226 /* CHIPCOMMONB_WDT_WDOGITOP */ "", 6227 /* CHIPCOMMONB_WDT_WDOGLOAD */ "", 6228 /* CHIPCOMMONB_WDT_WDOGLOCK */ "", 6229 /* CHIPCOMMONB_WDT_WDOGMIS */ "", 6230 /* CHIPCOMMONB_WDT_WDOGPCELLID0 */ "", 6231 /* CHIPCOMMONB_WDT_WDOGPCELLID1 */ "", 6232 /* CHIPCOMMONB_WDT_WDOGPCELLID2 */ "", 6233 /* CHIPCOMMONB_WDT_WDOGPCELLID3 */ "", 6234 /* CHIPCOMMONB_WDT_WDOGPERIPHID0 */ "", 6235 /* CHIPCOMMONB_WDT_WDOGPERIPHID1 */ "", 6236 /* CHIPCOMMONB_WDT_WDOGPERIPHID2 */ "", 6237 /* CHIPCOMMONB_WDT_WDOGPERIPHID3 */ "", 6238 /* CHIPCOMMONB_WDT_WDOGRIS */ "", 6239 /* CHIPCOMMONB_WDT_WDOGVALUE */ "", 6240 /* CHIPCOMMONG_GP_AUX_SEL */ "", 6241 /* CHIPCOMMONG_GP_DATA_IN */ "", 6242 /* CHIPCOMMONG_GP_DATA_OUT */ "", 6243 /* CHIPCOMMONG_GP_INIT_VAL */ "", 6244 /* CHIPCOMMONG_GP_INT_CLR */ "", 6245 /* CHIPCOMMONG_GP_INT_DE */ "", 6246 /* CHIPCOMMONG_GP_INT_EDGE */ "", 6247 /* CHIPCOMMONG_GP_INT_MSK */ "", 6248 /* CHIPCOMMONG_GP_INT_MSTAT */ "", 6249 /* CHIPCOMMONG_GP_INT_STAT */ "", 6250 /* CHIPCOMMONG_GP_INT_TYPE */ "", 6251 /* CHIPCOMMONG_GP_OUT_EN */ "", 6252 /* CHIPCOMMONG_GP_PAD_RES */ "", 6253 /* CHIPCOMMONG_GP_PRB_ENABLE */ "", 6254 /* CHIPCOMMONG_GP_PRB_OE */ "", 6255 /* CHIPCOMMONG_GP_RES_EN */ "", 6256 /* CHIPCOMMONG_GP_TEST_ENABLE */ "", 6257 /* CHIPCOMMONG_GP_TEST_INPUT */ "", 6258 /* CHIPCOMMONG_GP_TEST_OUTPUT */ "", 6259 /* CHIPCOMMONG_MII_MANAGEMENT_COMMAND_DATA */ "", 6260 /* CHIPCOMMONG_MII_MANAGEMENT_CONTROL */ "", 6261 /* CHIPCOMMONG_PWMCTL */ "", 6262 /* CHIPCOMMONG_PWM_DUTYHI_COUNT0 */ "", 6263 /* CHIPCOMMONG_PWM_DUTYHI_COUNT1 */ "", 6264 /* CHIPCOMMONG_PWM_DUTYHI_COUNT2 */ "", 6265 /* CHIPCOMMONG_PWM_DUTYHI_COUNT3 */ "", 6266 /* CHIPCOMMONG_PWM_PERIOD_COUNT0 */ "", 6267 /* CHIPCOMMONG_PWM_PERIOD_COUNT1 */ "", 6268 /* CHIPCOMMONG_PWM_PERIOD_COUNT2 */ "", 6269 /* CHIPCOMMONG_PWM_PERIOD_COUNT3 */ "", 6270 /* CHIPCOMMONG_PWM_PRESCALE */ "", 6271 /* CHIPCOMMONG_SMBUS0_SMBUS_ADDRESS */ "", 6272 /* CHIPCOMMONG_SMBUS0_SMBUS_BIT_BANG_CONTROL */ "", 6273 /* CHIPCOMMONG_SMBUS0_SMBUS_CONFIG */ "", 6274 /* CHIPCOMMONG_SMBUS0_SMBUS_EVENT_ENABLE */ "", 6275 /* CHIPCOMMONG_SMBUS0_SMBUS_EVENT_STATUS */ "", 6276 /* CHIPCOMMONG_SMBUS0_SMBUS_MASTER_COMMAND */ "", 6277 /* CHIPCOMMONG_SMBUS0_SMBUS_MASTER_DATA_READ */ "", 6278 /* CHIPCOMMONG_SMBUS0_SMBUS_MASTER_DATA_WRITE */ "", 6279 /* CHIPCOMMONG_SMBUS0_SMBUS_MASTER_FIFO_CONTROL */ "", 6280 /* CHIPCOMMONG_SMBUS0_SMBUS_SLAVE_COMMAND */ "", 6281 /* CHIPCOMMONG_SMBUS0_SMBUS_SLAVE_DATA_READ */ "", 6282 /* CHIPCOMMONG_SMBUS0_SMBUS_SLAVE_DATA_WRITE */ "", 6283 /* CHIPCOMMONG_SMBUS0_SMBUS_SLAVE_FIFO_CONTROL */ "", 6284 /* CHIPCOMMONG_SMBUS0_SMBUS_TIMING_CONFIG */ "", 6285 /* CHIPCOMMONG_SMBUS0_SMBUS_TIMING_CONFIG_2 */ "", 6286 /* CHIPCOMMONG_SMBUS1_SMBUS_ADDRESS */ "", 6287 /* CHIPCOMMONG_SMBUS1_SMBUS_BIT_BANG_CONTROL */ "", 6288 /* CHIPCOMMONG_SMBUS1_SMBUS_CONFIG */ "", 6289 /* CHIPCOMMONG_SMBUS1_SMBUS_EVENT_ENABLE */ "", 6290 /* CHIPCOMMONG_SMBUS1_SMBUS_EVENT_STATUS */ "", 6291 /* CHIPCOMMONG_SMBUS1_SMBUS_MASTER_COMMAND */ "", 6292 /* CHIPCOMMONG_SMBUS1_SMBUS_MASTER_DATA_READ */ "", 6293 /* CHIPCOMMONG_SMBUS1_SMBUS_MASTER_DATA_WRITE */ "", 6294 /* CHIPCOMMONG_SMBUS1_SMBUS_MASTER_FIFO_CONTROL */ "", 6295 /* CHIPCOMMONG_SMBUS1_SMBUS_SLAVE_COMMAND */ "", 6296 /* CHIPCOMMONG_SMBUS1_SMBUS_SLAVE_DATA_READ */ "", 6297 /* CHIPCOMMONG_SMBUS1_SMBUS_SLAVE_DATA_WRITE */ "", 6298 /* CHIPCOMMONG_SMBUS1_SMBUS_SLAVE_FIFO_CONTROL */ "", 6299 /* CHIPCOMMONG_SMBUS1_SMBUS_TIMING_CONFIG */ "", 6300 /* CHIPCOMMONG_SMBUS1_SMBUS_TIMING_CONFIG_2 */ "", 6301 /* CHIPCOMMONG_SMBUS2_SMBUS_ADDRESS */ "", 6302 /* CHIPCOMMONG_SMBUS2_SMBUS_BIT_BANG_CONTROL */ "", 6303 /* CHIPCOMMONG_SMBUS2_SMBUS_CONFIG */ "", 6304 /* CHIPCOMMONG_SMBUS2_SMBUS_EVENT_ENABLE */ "", 6305 /* CHIPCOMMONG_SMBUS2_SMBUS_EVENT_STATUS */ "", 6306 /* CHIPCOMMONG_SMBUS2_SMBUS_MASTER_COMMAND */ "", 6307 /* CHIPCOMMONG_SMBUS2_SMBUS_MASTER_DATA_READ */ "", 6308 /* CHIPCOMMONG_SMBUS2_SMBUS_MASTER_DATA_WRITE */ "", 6309 /* CHIPCOMMONG_SMBUS2_SMBUS_MASTER_FIFO_CONTROL */ "", 6310 /* CHIPCOMMONG_SMBUS2_SMBUS_SLAVE_COMMAND */ "", 6311 /* CHIPCOMMONG_SMBUS2_SMBUS_SLAVE_DATA_READ */ "", 6312 /* CHIPCOMMONG_SMBUS2_SMBUS_SLAVE_DATA_WRITE */ "", 6313 /* CHIPCOMMONG_SMBUS2_SMBUS_SLAVE_FIFO_CONTROL */ "", 6314 /* CHIPCOMMONG_SMBUS2_SMBUS_TIMING_CONFIG */ "", 6315 /* CHIPCOMMONG_SMBUS2_SMBUS_TIMING_CONFIG_2 */ "", 6316 /* CHIPCOMMONG_SMBUS3_SMBUS_ADDRESS */ "", 6317 /* CHIPCOMMONG_SMBUS3_SMBUS_BIT_BANG_CONTROL */ "", 6318 /* CHIPCOMMONG_SMBUS3_SMBUS_CONFIG */ "", 6319 /* CHIPCOMMONG_SMBUS3_SMBUS_EVENT_ENABLE */ "", 6320 /* CHIPCOMMONG_SMBUS3_SMBUS_EVENT_STATUS */ "", 6321 /* CHIPCOMMONG_SMBUS3_SMBUS_MASTER_COMMAND */ "", 6322 /* CHIPCOMMONG_SMBUS3_SMBUS_MASTER_DATA_READ */ "", 6323 /* CHIPCOMMONG_SMBUS3_SMBUS_MASTER_DATA_WRITE */ "", 6324 /* CHIPCOMMONG_SMBUS3_SMBUS_MASTER_FIFO_CONTROL */ "", 6325 /* CHIPCOMMONG_SMBUS3_SMBUS_SLAVE_COMMAND */ "", 6326 /* CHIPCOMMONG_SMBUS3_SMBUS_SLAVE_DATA_READ */ "", 6327 /* CHIPCOMMONG_SMBUS3_SMBUS_SLAVE_DATA_WRITE */ "", 6328 /* CHIPCOMMONG_SMBUS3_SMBUS_SLAVE_FIFO_CONTROL */ "", 6329 /* CHIPCOMMONG_SMBUS3_SMBUS_TIMING_CONFIG */ "", 6330 /* CHIPCOMMONG_SMBUS3_SMBUS_TIMING_CONFIG_2 */ "", 6331 /* CHIPCOMMONG_SMBUS4_SMBUS_ADDRESS */ "", 6332 /* CHIPCOMMONG_SMBUS4_SMBUS_BIT_BANG_CONTROL */ "", 6333 /* CHIPCOMMONG_SMBUS4_SMBUS_CONFIG */ "", 6334 /* CHIPCOMMONG_SMBUS4_SMBUS_EVENT_ENABLE */ "", 6335 /* CHIPCOMMONG_SMBUS4_SMBUS_EVENT_STATUS */ "", 6336 /* CHIPCOMMONG_SMBUS4_SMBUS_MASTER_COMMAND */ "", 6337 /* CHIPCOMMONG_SMBUS4_SMBUS_MASTER_DATA_READ */ "", 6338 /* CHIPCOMMONG_SMBUS4_SMBUS_MASTER_DATA_WRITE */ "", 6339 /* CHIPCOMMONG_SMBUS4_SMBUS_MASTER_FIFO_CONTROL */ "", 6340 /* CHIPCOMMONG_SMBUS4_SMBUS_SLAVE_COMMAND */ "", 6341 /* CHIPCOMMONG_SMBUS4_SMBUS_SLAVE_DATA_READ */ "", 6342 /* CHIPCOMMONG_SMBUS4_SMBUS_SLAVE_DATA_WRITE */ "", 6343 /* CHIPCOMMONG_SMBUS4_SMBUS_SLAVE_FIFO_CONTROL */ "", 6344 /* CHIPCOMMONG_SMBUS4_SMBUS_TIMING_CONFIG */ "", 6345 /* CHIPCOMMONG_SMBUS4_SMBUS_TIMING_CONFIG_2 */ "", 6346 /* CHIPCOMMONG_SMBUS5_SMBUS_ADDRESS */ "", 6347 /* CHIPCOMMONG_SMBUS5_SMBUS_BIT_BANG_CONTROL */ "", 6348 /* CHIPCOMMONG_SMBUS5_SMBUS_CONFIG */ "", 6349 /* CHIPCOMMONG_SMBUS5_SMBUS_EVENT_ENABLE */ "", 6350 /* CHIPCOMMONG_SMBUS5_SMBUS_EVENT_STATUS */ "", 6351 /* CHIPCOMMONG_SMBUS5_SMBUS_MASTER_COMMAND */ "", 6352 /* CHIPCOMMONG_SMBUS5_SMBUS_MASTER_DATA_READ */ "", 6353 /* CHIPCOMMONG_SMBUS5_SMBUS_MASTER_DATA_WRITE */ "", 6354 /* CHIPCOMMONG_SMBUS5_SMBUS_MASTER_FIFO_CONTROL */ "", 6355 /* CHIPCOMMONG_SMBUS5_SMBUS_SLAVE_COMMAND */ "", 6356 /* CHIPCOMMONG_SMBUS5_SMBUS_SLAVE_DATA_READ */ "", 6357 /* CHIPCOMMONG_SMBUS5_SMBUS_SLAVE_DATA_WRITE */ "", 6358 /* CHIPCOMMONG_SMBUS5_SMBUS_SLAVE_FIFO_CONTROL */ "", 6359 /* CHIPCOMMONG_SMBUS5_SMBUS_TIMING_CONFIG */ "", 6360 /* CHIPCOMMONG_SMBUS5_SMBUS_TIMING_CONFIG_2 */ "", 6361 /* CHIPCOMMONG_SMBUS6_SMBUS_ADDRESS */ "", 6362 /* CHIPCOMMONG_SMBUS6_SMBUS_BIT_BANG_CONTROL */ "", 6363 /* CHIPCOMMONG_SMBUS6_SMBUS_CONFIG */ "", 6364 /* CHIPCOMMONG_SMBUS6_SMBUS_EVENT_ENABLE */ "", 6365 /* CHIPCOMMONG_SMBUS6_SMBUS_EVENT_STATUS */ "", 6366 /* CHIPCOMMONG_SMBUS6_SMBUS_MASTER_COMMAND */ "", 6367 /* CHIPCOMMONG_SMBUS6_SMBUS_MASTER_DATA_READ */ "", 6368 /* CHIPCOMMONG_SMBUS6_SMBUS_MASTER_DATA_WRITE */ "", 6369 /* CHIPCOMMONG_SMBUS6_SMBUS_MASTER_FIFO_CONTROL */ "", 6370 /* CHIPCOMMONG_SMBUS6_SMBUS_SLAVE_COMMAND */ "", 6371 /* CHIPCOMMONG_SMBUS6_SMBUS_SLAVE_DATA_READ */ "", 6372 /* CHIPCOMMONG_SMBUS6_SMBUS_SLAVE_DATA_WRITE */ "", 6373 /* CHIPCOMMONG_SMBUS6_SMBUS_SLAVE_FIFO_CONTROL */ "", 6374 /* CHIPCOMMONG_SMBUS6_SMBUS_TIMING_CONFIG */ "", 6375 /* CHIPCOMMONG_SMBUS6_SMBUS_TIMING_CONFIG_2 */ "", 6376 /* CHIPCOMMONG_SPI0_SSPCPSR */ "", 6377 /* CHIPCOMMONG_SPI0_SSPCR0 */ "", 6378 /* CHIPCOMMONG_SPI0_SSPCR1 */ "", 6379 /* CHIPCOMMONG_SPI0_SSPDMACR */ "", 6380 /* CHIPCOMMONG_SPI0_SSPDR */ "", 6381 /* CHIPCOMMONG_SPI0_SSPICR */ "", 6382 /* CHIPCOMMONG_SPI0_SSPIMSC */ "", 6383 /* CHIPCOMMONG_SPI0_SSPITIP */ "", 6384 /* CHIPCOMMONG_SPI0_SSPITOP */ "", 6385 /* CHIPCOMMONG_SPI0_SSPMIS */ "", 6386 /* CHIPCOMMONG_SPI0_SSPPCELLID0 */ "", 6387 /* CHIPCOMMONG_SPI0_SSPPCELLID1 */ "", 6388 /* CHIPCOMMONG_SPI0_SSPPCELLID2 */ "", 6389 /* CHIPCOMMONG_SPI0_SSPPCELLID3 */ "", 6390 /* CHIPCOMMONG_SPI0_SSPPERIPHID0 */ "", 6391 /* CHIPCOMMONG_SPI0_SSPPERIPHID1 */ "", 6392 /* CHIPCOMMONG_SPI0_SSPPERIPHID2 */ "", 6393 /* CHIPCOMMONG_SPI0_SSPPERIPHID3 */ "", 6394 /* CHIPCOMMONG_SPI0_SSPRIS */ "", 6395 /* CHIPCOMMONG_SPI0_SSPSR */ "", 6396 /* CHIPCOMMONG_SPI0_SSPTCR */ "", 6397 /* CHIPCOMMONG_SPI0_SSPTDR */ "", 6398 /* CHIPCOMMONG_SPI1_SSPCPSR */ "", 6399 /* CHIPCOMMONG_SPI1_SSPCR0 */ "", 6400 /* CHIPCOMMONG_SPI1_SSPCR1 */ "", 6401 /* CHIPCOMMONG_SPI1_SSPDMACR */ "", 6402 /* CHIPCOMMONG_SPI1_SSPDR */ "", 6403 /* CHIPCOMMONG_SPI1_SSPICR */ "", 6404 /* CHIPCOMMONG_SPI1_SSPIMSC */ "", 6405 /* CHIPCOMMONG_SPI1_SSPITIP */ "", 6406 /* CHIPCOMMONG_SPI1_SSPITOP */ "", 6407 /* CHIPCOMMONG_SPI1_SSPMIS */ "", 6408 /* CHIPCOMMONG_SPI1_SSPPCELLID0 */ "", 6409 /* CHIPCOMMONG_SPI1_SSPPCELLID1 */ "", 6410 /* CHIPCOMMONG_SPI1_SSPPCELLID2 */ "", 6411 /* CHIPCOMMONG_SPI1_SSPPCELLID3 */ "", 6412 /* CHIPCOMMONG_SPI1_SSPPERIPHID0 */ "", 6413 /* CHIPCOMMONG_SPI1_SSPPERIPHID1 */ "", 6414 /* CHIPCOMMONG_SPI1_SSPPERIPHID2 */ "", 6415 /* CHIPCOMMONG_SPI1_SSPPERIPHID3 */ "", 6416 /* CHIPCOMMONG_SPI1_SSPRIS */ "", 6417 /* CHIPCOMMONG_SPI1_SSPSR */ "", 6418 /* CHIPCOMMONG_SPI1_SSPTCR */ "", 6419 /* CHIPCOMMONG_SPI1_SSPTDR */ "", 6420 /* CHIPCOMMONG_SPI2_SSPCPSR */ "", 6421 /* CHIPCOMMONG_SPI2_SSPCR0 */ "", 6422 /* CHIPCOMMONG_SPI2_SSPCR1 */ "", 6423 /* CHIPCOMMONG_SPI2_SSPDMACR */ "", 6424 /* CHIPCOMMONG_SPI2_SSPDR */ "", 6425 /* CHIPCOMMONG_SPI2_SSPICR */ "", 6426 /* CHIPCOMMONG_SPI2_SSPIMSC */ "", 6427 /* CHIPCOMMONG_SPI2_SSPITIP */ "", 6428 /* CHIPCOMMONG_SPI2_SSPITOP */ "", 6429 /* CHIPCOMMONG_SPI2_SSPMIS */ "", 6430 /* CHIPCOMMONG_SPI2_SSPPCELLID0 */ "", 6431 /* CHIPCOMMONG_SPI2_SSPPCELLID1 */ "", 6432 /* CHIPCOMMONG_SPI2_SSPPCELLID2 */ "", 6433 /* CHIPCOMMONG_SPI2_SSPPCELLID3 */ "", 6434 /* CHIPCOMMONG_SPI2_SSPPERIPHID0 */ "", 6435 /* CHIPCOMMONG_SPI2_SSPPERIPHID1 */ "", 6436 /* CHIPCOMMONG_SPI2_SSPPERIPHID2 */ "", 6437 /* CHIPCOMMONG_SPI2_SSPPERIPHID3 */ "", 6438 /* CHIPCOMMONG_SPI2_SSPRIS */ "", 6439 /* CHIPCOMMONG_SPI2_SSPSR */ "", 6440 /* CHIPCOMMONG_SPI2_SSPTCR */ "", 6441 /* CHIPCOMMONG_SPI2_SSPTDR */ "", 6442 /* CHIPCOMMONG_SPI3_SSPCPSR */ "", 6443 /* CHIPCOMMONG_SPI3_SSPCR0 */ "", 6444 /* CHIPCOMMONG_SPI3_SSPCR1 */ "", 6445 /* CHIPCOMMONG_SPI3_SSPDMACR */ "", 6446 /* CHIPCOMMONG_SPI3_SSPDR */ "", 6447 /* CHIPCOMMONG_SPI3_SSPICR */ "", 6448 /* CHIPCOMMONG_SPI3_SSPIMSC */ "", 6449 /* CHIPCOMMONG_SPI3_SSPITIP */ "", 6450 /* CHIPCOMMONG_SPI3_SSPITOP */ "", 6451 /* CHIPCOMMONG_SPI3_SSPMIS */ "", 6452 /* CHIPCOMMONG_SPI3_SSPPCELLID0 */ "", 6453 /* CHIPCOMMONG_SPI3_SSPPCELLID1 */ "", 6454 /* CHIPCOMMONG_SPI3_SSPPCELLID2 */ "", 6455 /* CHIPCOMMONG_SPI3_SSPPCELLID3 */ "", 6456 /* CHIPCOMMONG_SPI3_SSPPERIPHID0 */ "", 6457 /* CHIPCOMMONG_SPI3_SSPPERIPHID1 */ "", 6458 /* CHIPCOMMONG_SPI3_SSPPERIPHID2 */ "", 6459 /* CHIPCOMMONG_SPI3_SSPPERIPHID3 */ "", 6460 /* CHIPCOMMONG_SPI3_SSPRIS */ "", 6461 /* CHIPCOMMONG_SPI3_SSPSR */ "", 6462 /* CHIPCOMMONG_SPI3_SSPTCR */ "", 6463 /* CHIPCOMMONG_SPI3_SSPTDR */ "", 6464 /* CHIPCOMMONG_SPI4_SSPCPSR */ "", 6465 /* CHIPCOMMONG_SPI4_SSPCR0 */ "", 6466 /* CHIPCOMMONG_SPI4_SSPCR1 */ "", 6467 /* CHIPCOMMONG_SPI4_SSPDMACR */ "", 6468 /* CHIPCOMMONG_SPI4_SSPDR */ "", 6469 /* CHIPCOMMONG_SPI4_SSPICR */ "", 6470 /* CHIPCOMMONG_SPI4_SSPIMSC */ "", 6471 /* CHIPCOMMONG_SPI4_SSPITIP */ "", 6472 /* CHIPCOMMONG_SPI4_SSPITOP */ "", 6473 /* CHIPCOMMONG_SPI4_SSPMIS */ "", 6474 /* CHIPCOMMONG_SPI4_SSPPCELLID0 */ "", 6475 /* CHIPCOMMONG_SPI4_SSPPCELLID1 */ "", 6476 /* CHIPCOMMONG_SPI4_SSPPCELLID2 */ "", 6477 /* CHIPCOMMONG_SPI4_SSPPCELLID3 */ "", 6478 /* CHIPCOMMONG_SPI4_SSPPERIPHID0 */ "", 6479 /* CHIPCOMMONG_SPI4_SSPPERIPHID1 */ "", 6480 /* CHIPCOMMONG_SPI4_SSPPERIPHID2 */ "", 6481 /* CHIPCOMMONG_SPI4_SSPPERIPHID3 */ "", 6482 /* CHIPCOMMONG_SPI4_SSPRIS */ "", 6483 /* CHIPCOMMONG_SPI4_SSPSR */ "", 6484 /* CHIPCOMMONG_SPI4_SSPTCR */ "", 6485 /* CHIPCOMMONG_SPI4_SSPTDR */ "", 6486 /* CHIPCOMMONG_SPI5_SSPCPSR */ "", 6487 /* CHIPCOMMONG_SPI5_SSPCR0 */ "", 6488 /* CHIPCOMMONG_SPI5_SSPCR1 */ "", 6489 /* CHIPCOMMONG_SPI5_SSPDMACR */ "", 6490 /* CHIPCOMMONG_SPI5_SSPDR */ "", 6491 /* CHIPCOMMONG_SPI5_SSPICR */ "", 6492 /* CHIPCOMMONG_SPI5_SSPIMSC */ "", 6493 /* CHIPCOMMONG_SPI5_SSPITIP */ "", 6494 /* CHIPCOMMONG_SPI5_SSPITOP */ "", 6495 /* CHIPCOMMONG_SPI5_SSPMIS */ "", 6496 /* CHIPCOMMONG_SPI5_SSPPCELLID0 */ "", 6497 /* CHIPCOMMONG_SPI5_SSPPCELLID1 */ "", 6498 /* CHIPCOMMONG_SPI5_SSPPCELLID2 */ "", 6499 /* CHIPCOMMONG_SPI5_SSPPCELLID3 */ "", 6500 /* CHIPCOMMONG_SPI5_SSPPERIPHID0 */ "", 6501 /* CHIPCOMMONG_SPI5_SSPPERIPHID1 */ "", 6502 /* CHIPCOMMONG_SPI5_SSPPERIPHID2 */ "", 6503 /* CHIPCOMMONG_SPI5_SSPPERIPHID3 */ "", 6504 /* CHIPCOMMONG_SPI5_SSPRIS */ "", 6505 /* CHIPCOMMONG_SPI5_SSPSR */ "", 6506 /* CHIPCOMMONG_SPI5_SSPTCR */ "", 6507 /* CHIPCOMMONG_SPI5_SSPTDR */ "", 6508 /* CHIPCOMMONG_SRAB_CMDSTAT */ "", 6509 /* CHIPCOMMONG_SRAB_RDH */ "", 6510 /* CHIPCOMMONG_SRAB_RDL */ "", 6511 /* CHIPCOMMONG_SRAB_SW_IF */ "", 6512 /* CHIPCOMMONG_SRAB_SW_INTR_CLR */ "", 6513 /* CHIPCOMMONG_SRAB_SW_INTR_ENABLE */ "", 6514 /* CHIPCOMMONG_SRAB_SW_MASKED_INTR_STATUS */ "", 6515 /* CHIPCOMMONG_SRAB_SW_RAW_INTR_STATUS */ "", 6516 /* CHIPCOMMONG_SRAB_WDH */ "", 6517 /* CHIPCOMMONG_SRAB_WDL */ "", 6518 /* CHIPCOMMONG_TIM0_TIM_TIMER1BGLOAD */ "", 6519 /* CHIPCOMMONG_TIM0_TIM_TIMER1CONTROL */ "", 6520 /* CHIPCOMMONG_TIM0_TIM_TIMER1INTCLR */ "", 6521 /* CHIPCOMMONG_TIM0_TIM_TIMER1LOAD */ "", 6522 /* CHIPCOMMONG_TIM0_TIM_TIMER1MIS */ "", 6523 /* CHIPCOMMONG_TIM0_TIM_TIMER1RIS */ "", 6524 /* CHIPCOMMONG_TIM0_TIM_TIMER1VALUE */ "", 6525 /* CHIPCOMMONG_TIM0_TIM_TIMER2BGLOAD */ "", 6526 /* CHIPCOMMONG_TIM0_TIM_TIMER2CONTROL */ "", 6527 /* CHIPCOMMONG_TIM0_TIM_TIMER2INTCLR */ "", 6528 /* CHIPCOMMONG_TIM0_TIM_TIMER2LOAD */ "", 6529 /* CHIPCOMMONG_TIM0_TIM_TIMER2MIS */ "", 6530 /* CHIPCOMMONG_TIM0_TIM_TIMER2RIS */ "", 6531 /* CHIPCOMMONG_TIM0_TIM_TIMER2VALUE */ "", 6532 /* CHIPCOMMONG_TIM0_TIM_TIMERITCR */ "", 6533 /* CHIPCOMMONG_TIM0_TIM_TIMERITOP */ "", 6534 /* CHIPCOMMONG_TIM0_TIM_TIMERPCELLID0 */ "", 6535 /* CHIPCOMMONG_TIM0_TIM_TIMERPCELLID1 */ "", 6536 /* CHIPCOMMONG_TIM0_TIM_TIMERPCELLID2 */ "", 6537 /* CHIPCOMMONG_TIM0_TIM_TIMERPCELLID3 */ "", 6538 /* CHIPCOMMONG_TIM0_TIM_TIMERPERIPHID0 */ "", 6539 /* CHIPCOMMONG_TIM0_TIM_TIMERPERIPHID1 */ "", 6540 /* CHIPCOMMONG_TIM0_TIM_TIMERPERIPHID2 */ "", 6541 /* CHIPCOMMONG_TIM0_TIM_TIMERPERIPHID3 */ "", 6542 /* CHIPCOMMONG_TIM1_TIM_TIMER1BGLOAD */ "", 6543 /* CHIPCOMMONG_TIM1_TIM_TIMER1CONTROL */ "", 6544 /* CHIPCOMMONG_TIM1_TIM_TIMER1INTCLR */ "", 6545 /* CHIPCOMMONG_TIM1_TIM_TIMER1LOAD */ "", 6546 /* CHIPCOMMONG_TIM1_TIM_TIMER1MIS */ "", 6547 /* CHIPCOMMONG_TIM1_TIM_TIMER1RIS */ "", 6548 /* CHIPCOMMONG_TIM1_TIM_TIMER1VALUE */ "", 6549 /* CHIPCOMMONG_TIM1_TIM_TIMER2BGLOAD */ "", 6550 /* CHIPCOMMONG_TIM1_TIM_TIMER2CONTROL */ "", 6551 /* CHIPCOMMONG_TIM1_TIM_TIMER2INTCLR */ "", 6552 /* CHIPCOMMONG_TIM1_TIM_TIMER2LOAD */ "", 6553 /* CHIPCOMMONG_TIM1_TIM_TIMER2MIS */ "", 6554 /* CHIPCOMMONG_TIM1_TIM_TIMER2RIS */ "", 6555 /* CHIPCOMMONG_TIM1_TIM_TIMER2VALUE */ "", 6556 /* CHIPCOMMONG_TIM1_TIM_TIMERITCR */ "", 6557 /* CHIPCOMMONG_TIM1_TIM_TIMERITOP */ "", 6558 /* CHIPCOMMONG_TIM1_TIM_TIMERPCELLID0 */ "", 6559 /* CHIPCOMMONG_TIM1_TIM_TIMERPCELLID1 */ "", 6560 /* CHIPCOMMONG_TIM1_TIM_TIMERPCELLID2 */ "", 6561 /* CHIPCOMMONG_TIM1_TIM_TIMERPCELLID3 */ "", 6562 /* CHIPCOMMONG_TIM1_TIM_TIMERPERIPHID0 */ "", 6563 /* CHIPCOMMONG_TIM1_TIM_TIMERPERIPHID1 */ "", 6564 /* CHIPCOMMONG_TIM1_TIM_TIMERPERIPHID2 */ "", 6565 /* CHIPCOMMONG_TIM1_TIM_TIMERPERIPHID3 */ "", 6566 /* CHIPCOMMONG_TIM2_TIM_TIMER1BGLOAD */ "", 6567 /* CHIPCOMMONG_TIM2_TIM_TIMER1CONTROL */ "", 6568 /* CHIPCOMMONG_TIM2_TIM_TIMER1INTCLR */ "", 6569 /* CHIPCOMMONG_TIM2_TIM_TIMER1LOAD */ "", 6570 /* CHIPCOMMONG_TIM2_TIM_TIMER1MIS */ "", 6571 /* CHIPCOMMONG_TIM2_TIM_TIMER1RIS */ "", 6572 /* CHIPCOMMONG_TIM2_TIM_TIMER1VALUE */ "", 6573 /* CHIPCOMMONG_TIM2_TIM_TIMER2BGLOAD */ "", 6574 /* CHIPCOMMONG_TIM2_TIM_TIMER2CONTROL */ "", 6575 /* CHIPCOMMONG_TIM2_TIM_TIMER2INTCLR */ "", 6576 /* CHIPCOMMONG_TIM2_TIM_TIMER2LOAD */ "", 6577 /* CHIPCOMMONG_TIM2_TIM_TIMER2MIS */ "", 6578 /* CHIPCOMMONG_TIM2_TIM_TIMER2RIS */ "", 6579 /* CHIPCOMMONG_TIM2_TIM_TIMER2VALUE */ "", 6580 /* CHIPCOMMONG_TIM2_TIM_TIMERITCR */ "", 6581 /* CHIPCOMMONG_TIM2_TIM_TIMERITOP */ "", 6582 /* CHIPCOMMONG_TIM2_TIM_TIMERPCELLID0 */ "", 6583 /* CHIPCOMMONG_TIM2_TIM_TIMERPCELLID1 */ "", 6584 /* CHIPCOMMONG_TIM2_TIM_TIMERPCELLID2 */ "", 6585 /* CHIPCOMMONG_TIM2_TIM_TIMERPCELLID3 */ "", 6586 /* CHIPCOMMONG_TIM2_TIM_TIMERPERIPHID0 */ "", 6587 /* CHIPCOMMONG_TIM2_TIM_TIMERPERIPHID1 */ "", 6588 /* CHIPCOMMONG_TIM2_TIM_TIMERPERIPHID2 */ "", 6589 /* CHIPCOMMONG_TIM2_TIM_TIMERPERIPHID3 */ "", 6590 /* CHIPCOMMONG_TIM3_TIM_TIMER1BGLOAD */ "", 6591 /* CHIPCOMMONG_TIM3_TIM_TIMER1CONTROL */ "", 6592 /* CHIPCOMMONG_TIM3_TIM_TIMER1INTCLR */ "", 6593 /* CHIPCOMMONG_TIM3_TIM_TIMER1LOAD */ "", 6594 /* CHIPCOMMONG_TIM3_TIM_TIMER1MIS */ "", 6595 /* CHIPCOMMONG_TIM3_TIM_TIMER1RIS */ "", 6596 /* CHIPCOMMONG_TIM3_TIM_TIMER1VALUE */ "", 6597 /* CHIPCOMMONG_TIM3_TIM_TIMER2BGLOAD */ "", 6598 /* CHIPCOMMONG_TIM3_TIM_TIMER2CONTROL */ "", 6599 /* CHIPCOMMONG_TIM3_TIM_TIMER2INTCLR */ "", 6600 /* CHIPCOMMONG_TIM3_TIM_TIMER2LOAD */ "", 6601 /* CHIPCOMMONG_TIM3_TIM_TIMER2MIS */ "", 6602 /* CHIPCOMMONG_TIM3_TIM_TIMER2RIS */ "", 6603 /* CHIPCOMMONG_TIM3_TIM_TIMER2VALUE */ "", 6604 /* CHIPCOMMONG_TIM3_TIM_TIMERITCR */ "", 6605 /* CHIPCOMMONG_TIM3_TIM_TIMERITOP */ "", 6606 /* CHIPCOMMONG_TIM3_TIM_TIMERPCELLID0 */ "", 6607 /* CHIPCOMMONG_TIM3_TIM_TIMERPCELLID1 */ "", 6608 /* CHIPCOMMONG_TIM3_TIM_TIMERPCELLID2 */ "", 6609 /* CHIPCOMMONG_TIM3_TIM_TIMERPCELLID3 */ "", 6610 /* CHIPCOMMONG_TIM3_TIM_TIMERPERIPHID0 */ "", 6611 /* CHIPCOMMONG_TIM3_TIM_TIMERPERIPHID1 */ "", 6612 /* CHIPCOMMONG_TIM3_TIM_TIMERPERIPHID2 */ "", 6613 /* CHIPCOMMONG_TIM3_TIM_TIMERPERIPHID3 */ "", 6614 /* CHIPCOMMONG_UART0_UART_CPR */ "", 6615 /* CHIPCOMMONG_UART0_UART_CTR */ "", 6616 /* CHIPCOMMONG_UART0_UART_DLH_IER */ "", 6617 /* CHIPCOMMONG_UART0_UART_DMASA */ "", 6618 /* CHIPCOMMONG_UART0_UART_FAR */ "", 6619 /* CHIPCOMMONG_UART0_UART_HTX */ "", 6620 /* CHIPCOMMONG_UART0_UART_IIR_FCR */ "", 6621 /* CHIPCOMMONG_UART0_UART_LCR */ "", 6622 /* CHIPCOMMONG_UART0_UART_LSR */ "", 6623 /* CHIPCOMMONG_UART0_UART_MCR */ "", 6624 /* CHIPCOMMONG_UART0_UART_MSR */ "", 6625 /* CHIPCOMMONG_UART0_UART_RBR_THR_DLL */ "", 6626 /* CHIPCOMMONG_UART0_UART_RFL */ "", 6627 /* CHIPCOMMONG_UART0_UART_RFW */ "", 6628 /* CHIPCOMMONG_UART0_UART_SBCR */ "", 6629 /* CHIPCOMMONG_UART0_UART_SCR */ "", 6630 /* CHIPCOMMONG_UART0_UART_SDMAM */ "", 6631 /* CHIPCOMMONG_UART0_UART_SFE */ "", 6632 /* CHIPCOMMONG_UART0_UART_SRBR_STHR */ "", 6633 /* CHIPCOMMONG_UART0_UART_SRR */ "", 6634 /* CHIPCOMMONG_UART0_UART_SRT */ "", 6635 /* CHIPCOMMONG_UART0_UART_SRTS */ "", 6636 /* CHIPCOMMONG_UART0_UART_STET */ "", 6637 /* CHIPCOMMONG_UART0_UART_TFL */ "", 6638 /* CHIPCOMMONG_UART0_UART_TFR */ "", 6639 /* CHIPCOMMONG_UART0_UART_UCV */ "", 6640 /* CHIPCOMMONG_UART0_UART_USR */ "", 6641 /* CHIPCOMMONG_UART1_UART_CPR */ "", 6642 /* CHIPCOMMONG_UART1_UART_CTR */ "", 6643 /* CHIPCOMMONG_UART1_UART_DLH_IER */ "", 6644 /* CHIPCOMMONG_UART1_UART_DMASA */ "", 6645 /* CHIPCOMMONG_UART1_UART_FAR */ "", 6646 /* CHIPCOMMONG_UART1_UART_HTX */ "", 6647 /* CHIPCOMMONG_UART1_UART_IIR_FCR */ "", 6648 /* CHIPCOMMONG_UART1_UART_LCR */ "", 6649 /* CHIPCOMMONG_UART1_UART_LSR */ "", 6650 /* CHIPCOMMONG_UART1_UART_MCR */ "", 6651 /* CHIPCOMMONG_UART1_UART_MSR */ "", 6652 /* CHIPCOMMONG_UART1_UART_RBR_THR_DLL */ "", 6653 /* CHIPCOMMONG_UART1_UART_RFL */ "", 6654 /* CHIPCOMMONG_UART1_UART_RFW */ "", 6655 /* CHIPCOMMONG_UART1_UART_SBCR */ "", 6656 /* CHIPCOMMONG_UART1_UART_SCR */ "", 6657 /* CHIPCOMMONG_UART1_UART_SDMAM */ "", 6658 /* CHIPCOMMONG_UART1_UART_SFE */ "", 6659 /* CHIPCOMMONG_UART1_UART_SRBR_STHR */ "", 6660 /* CHIPCOMMONG_UART1_UART_SRR */ "", 6661 /* CHIPCOMMONG_UART1_UART_SRT */ "", 6662 /* CHIPCOMMONG_UART1_UART_SRTS */ "", 6663 /* CHIPCOMMONG_UART1_UART_STET */ "", 6664 /* CHIPCOMMONG_UART1_UART_TFL */ "", 6665 /* CHIPCOMMONG_UART1_UART_TFR */ "", 6666 /* CHIPCOMMONG_UART1_UART_UCV */ "", 6667 /* CHIPCOMMONG_UART1_UART_USR */ "", 6668 /* CHIPCOMMONG_UART2_UART_CPR */ "", 6669 /* CHIPCOMMONG_UART2_UART_CTR */ "", 6670 /* CHIPCOMMONG_UART2_UART_DLH_IER */ "", 6671 /* CHIPCOMMONG_UART2_UART_DMASA */ "", 6672 /* CHIPCOMMONG_UART2_UART_FAR */ "", 6673 /* CHIPCOMMONG_UART2_UART_HTX */ "", 6674 /* CHIPCOMMONG_UART2_UART_IIR_FCR */ "", 6675 /* CHIPCOMMONG_UART2_UART_LCR */ "", 6676 /* CHIPCOMMONG_UART2_UART_LSR */ "", 6677 /* CHIPCOMMONG_UART2_UART_MCR */ "", 6678 /* CHIPCOMMONG_UART2_UART_MSR */ "", 6679 /* CHIPCOMMONG_UART2_UART_RBR_THR_DLL */ "", 6680 /* CHIPCOMMONG_UART2_UART_RFL */ "", 6681 /* CHIPCOMMONG_UART2_UART_RFW */ "", 6682 /* CHIPCOMMONG_UART2_UART_SBCR */ "", 6683 /* CHIPCOMMONG_UART2_UART_SCR */ "", 6684 /* CHIPCOMMONG_UART2_UART_SDMAM */ "", 6685 /* CHIPCOMMONG_UART2_UART_SFE */ "", 6686 /* CHIPCOMMONG_UART2_UART_SRBR_STHR */ "", 6687 /* CHIPCOMMONG_UART2_UART_SRR */ "", 6688 /* CHIPCOMMONG_UART2_UART_SRT */ "", 6689 /* CHIPCOMMONG_UART2_UART_SRTS */ "", 6690 /* CHIPCOMMONG_UART2_UART_STET */ "", 6691 /* CHIPCOMMONG_UART2_UART_TFL */ "", 6692 /* CHIPCOMMONG_UART2_UART_TFR */ "", 6693 /* CHIPCOMMONG_UART2_UART_UCV */ "", 6694 /* CHIPCOMMONG_UART2_UART_USR */ "", 6695 /* CHIPCOMMONG_UART3_UART_CPR */ "", 6696 /* CHIPCOMMONG_UART3_UART_CTR */ "", 6697 /* CHIPCOMMONG_UART3_UART_DLH_IER */ "", 6698 /* CHIPCOMMONG_UART3_UART_DMASA */ "", 6699 /* CHIPCOMMONG_UART3_UART_FAR */ "", 6700 /* CHIPCOMMONG_UART3_UART_HTX */ "", 6701 /* CHIPCOMMONG_UART3_UART_IIR_FCR */ "", 6702 /* CHIPCOMMONG_UART3_UART_LCR */ "", 6703 /* CHIPCOMMONG_UART3_UART_LSR */ "", 6704 /* CHIPCOMMONG_UART3_UART_MCR */ "", 6705 /* CHIPCOMMONG_UART3_UART_MSR */ "", 6706 /* CHIPCOMMONG_UART3_UART_RBR_THR_DLL */ "", 6707 /* CHIPCOMMONG_UART3_UART_RFL */ "", 6708 /* CHIPCOMMONG_UART3_UART_RFW */ "", 6709 /* CHIPCOMMONG_UART3_UART_SBCR */ "", 6710 /* CHIPCOMMONG_UART3_UART_SCR */ "", 6711 /* CHIPCOMMONG_UART3_UART_SDMAM */ "", 6712 /* CHIPCOMMONG_UART3_UART_SFE */ "", 6713 /* CHIPCOMMONG_UART3_UART_SRBR_STHR */ "", 6714 /* CHIPCOMMONG_UART3_UART_SRR */ "", 6715 /* CHIPCOMMONG_UART3_UART_SRT */ "", 6716 /* CHIPCOMMONG_UART3_UART_SRTS */ "", 6717 /* CHIPCOMMONG_UART3_UART_STET */ "", 6718 /* CHIPCOMMONG_UART3_UART_TFL */ "", 6719 /* CHIPCOMMONG_UART3_UART_TFR */ "", 6720 /* CHIPCOMMONG_UART3_UART_UCV */ "", 6721 /* CHIPCOMMONG_UART3_UART_USR */ "", 6722 /* CHIPCOMMONG_UART4_UART_CPR */ "", 6723 /* CHIPCOMMONG_UART4_UART_CTR */ "", 6724 /* CHIPCOMMONG_UART4_UART_DLH_IER */ "", 6725 /* CHIPCOMMONG_UART4_UART_DMASA */ "", 6726 /* CHIPCOMMONG_UART4_UART_FAR */ "", 6727 /* CHIPCOMMONG_UART4_UART_HTX */ "", 6728 /* CHIPCOMMONG_UART4_UART_IIR_FCR */ "", 6729 /* CHIPCOMMONG_UART4_UART_LCR */ "", 6730 /* CHIPCOMMONG_UART4_UART_LSR */ "", 6731 /* CHIPCOMMONG_UART4_UART_MCR */ "", 6732 /* CHIPCOMMONG_UART4_UART_MSR */ "", 6733 /* CHIPCOMMONG_UART4_UART_RBR_THR_DLL */ "", 6734 /* CHIPCOMMONG_UART4_UART_RFL */ "", 6735 /* CHIPCOMMONG_UART4_UART_RFW */ "", 6736 /* CHIPCOMMONG_UART4_UART_SBCR */ "", 6737 /* CHIPCOMMONG_UART4_UART_SCR */ "", 6738 /* CHIPCOMMONG_UART4_UART_SDMAM */ "", 6739 /* CHIPCOMMONG_UART4_UART_SFE */ "", 6740 /* CHIPCOMMONG_UART4_UART_SRBR_STHR */ "", 6741 /* CHIPCOMMONG_UART4_UART_SRR */ "", 6742 /* CHIPCOMMONG_UART4_UART_SRT */ "", 6743 /* CHIPCOMMONG_UART4_UART_SRTS */ "", 6744 /* CHIPCOMMONG_UART4_UART_STET */ "", 6745 /* CHIPCOMMONG_UART4_UART_TFL */ "", 6746 /* CHIPCOMMONG_UART4_UART_TFR */ "", 6747 /* CHIPCOMMONG_UART4_UART_UCV */ "", 6748 /* CHIPCOMMONG_UART4_UART_USR */ "", 6749 /* CHIPCOMMONG_WDT0_WDT_WDOGCONTROL */ "", 6750 /* CHIPCOMMONG_WDT0_WDT_WDOGINTCLR */ "", 6751 /* CHIPCOMMONG_WDT0_WDT_WDOGITCR */ "", 6752 /* CHIPCOMMONG_WDT0_WDT_WDOGITOP */ "", 6753 /* CHIPCOMMONG_WDT0_WDT_WDOGLOAD */ "", 6754 /* CHIPCOMMONG_WDT0_WDT_WDOGLOCK */ "", 6755 /* CHIPCOMMONG_WDT0_WDT_WDOGMIS */ "", 6756 /* CHIPCOMMONG_WDT0_WDT_WDOGPCELLID0 */ "", 6757 /* CHIPCOMMONG_WDT0_WDT_WDOGPCELLID1 */ "", 6758 /* CHIPCOMMONG_WDT0_WDT_WDOGPCELLID2 */ "", 6759 /* CHIPCOMMONG_WDT0_WDT_WDOGPCELLID3 */ "", 6760 /* CHIPCOMMONG_WDT0_WDT_WDOGPERIPHID0 */ "", 6761 /* CHIPCOMMONG_WDT0_WDT_WDOGPERIPHID1 */ "", 6762 /* CHIPCOMMONG_WDT0_WDT_WDOGPERIPHID2 */ "", 6763 /* CHIPCOMMONG_WDT0_WDT_WDOGPERIPHID3 */ "", 6764 /* CHIPCOMMONG_WDT0_WDT_WDOGRIS */ "", 6765 /* CHIPCOMMONG_WDT0_WDT_WDOGVALUE */ "", 6766 /* CHIPCOMMONG_WDT1_WDT_WDOGCONTROL */ "", 6767 /* CHIPCOMMONG_WDT1_WDT_WDOGINTCLR */ "", 6768 /* CHIPCOMMONG_WDT1_WDT_WDOGITCR */ "", 6769 /* CHIPCOMMONG_WDT1_WDT_WDOGITOP */ "", 6770 /* CHIPCOMMONG_WDT1_WDT_WDOGLOAD */ "", 6771 /* CHIPCOMMONG_WDT1_WDT_WDOGLOCK */ "", 6772 /* CHIPCOMMONG_WDT1_WDT_WDOGMIS */ "", 6773 /* CHIPCOMMONG_WDT1_WDT_WDOGPCELLID0 */ "", 6774 /* CHIPCOMMONG_WDT1_WDT_WDOGPCELLID1 */ "", 6775 /* CHIPCOMMONG_WDT1_WDT_WDOGPCELLID2 */ "", 6776 /* CHIPCOMMONG_WDT1_WDT_WDOGPCELLID3 */ "", 6777 /* CHIPCOMMONG_WDT1_WDT_WDOGPERIPHID0 */ "", 6778 /* CHIPCOMMONG_WDT1_WDT_WDOGPERIPHID1 */ "", 6779 /* CHIPCOMMONG_WDT1_WDT_WDOGPERIPHID2 */ "", 6780 /* CHIPCOMMONG_WDT1_WDT_WDOGPERIPHID3 */ "", 6781 /* CHIPCOMMONG_WDT1_WDT_WDOGRIS */ "", 6782 /* CHIPCOMMONG_WDT1_WDT_WDOGVALUE */ "", 6783 /* CHIPCOMMONG_WDT_WDOGCONTROL */ "", 6784 /* CHIPCOMMONG_WDT_WDOGINTCLR */ "", 6785 /* CHIPCOMMONG_WDT_WDOGITCR */ "", 6786 /* CHIPCOMMONG_WDT_WDOGITOP */ "", 6787 /* CHIPCOMMONG_WDT_WDOGLOAD */ "", 6788 /* CHIPCOMMONG_WDT_WDOGLOCK */ "", 6789 /* CHIPCOMMONG_WDT_WDOGMIS */ "", 6790 /* CHIPCOMMONG_WDT_WDOGPCELLID0 */ "", 6791 /* CHIPCOMMONG_WDT_WDOGPCELLID1 */ "", 6792 /* CHIPCOMMONG_WDT_WDOGPCELLID2 */ "", 6793 /* CHIPCOMMONG_WDT_WDOGPCELLID3 */ "", 6794 /* CHIPCOMMONG_WDT_WDOGPERIPHID0 */ "", 6795 /* CHIPCOMMONG_WDT_WDOGPERIPHID1 */ "", 6796 /* CHIPCOMMONG_WDT_WDOGPERIPHID2 */ "", 6797 /* CHIPCOMMONG_WDT_WDOGPERIPHID3 */ "", 6798 /* CHIPCOMMONG_WDT_WDOGRIS */ "", 6799 /* CHIPCOMMONG_WDT_WDOGVALUE */ "", 6800 /* CHIPCOMMONS_GP_AUX_SEL */ "", 6801 /* CHIPCOMMONS_GP_DATA_IN */ "", 6802 /* CHIPCOMMONS_GP_DATA_OUT */ "", 6803 /* CHIPCOMMONS_GP_INIT_VAL */ "", 6804 /* CHIPCOMMONS_GP_INT_CLR */ "", 6805 /* CHIPCOMMONS_GP_INT_DE */ "", 6806 /* CHIPCOMMONS_GP_INT_EDGE */ "", 6807 /* CHIPCOMMONS_GP_INT_MSK */ "", 6808 /* CHIPCOMMONS_GP_INT_MSTAT */ "", 6809 /* CHIPCOMMONS_GP_INT_STAT */ "", 6810 /* CHIPCOMMONS_GP_INT_TYPE */ "", 6811 /* CHIPCOMMONS_GP_OUT_EN */ "", 6812 /* CHIPCOMMONS_GP_PAD_RES */ "", 6813 /* CHIPCOMMONS_GP_PRB_ENABLE */ "", 6814 /* CHIPCOMMONS_GP_PRB_OE */ "", 6815 /* CHIPCOMMONS_GP_RES_EN */ "", 6816 /* CHIPCOMMONS_GP_TEST_ENABLE */ "", 6817 /* CHIPCOMMONS_GP_TEST_INPUT */ "", 6818 /* CHIPCOMMONS_GP_TEST_OUTPUT */ "", 6819 /* CHIPCOMMONS_PKA_CONTROL_STATUS */ "", 6820 /* CHIPCOMMONS_PKA_DATA_INPUT */ "", 6821 /* CHIPCOMMONS_PKA_DATA_OUTPUT */ "", 6822 /* CHIPCOMMONS_PKA_SCA_LFSR_SEED */ "", 6823 /* CHIPCOMMONS_RBG_SOFT_RESET */ "", 6824 /* CHIPCOMMONS_RNG_CTRL */ "", 6825 /* CHIPCOMMONS_RNG_FIFO_COUNT */ "", 6826 /* CHIPCOMMONS_RNG_FIFO_DATA */ "", 6827 /* CHIPCOMMONS_RNG_INT_ENABLE */ "", 6828 /* CHIPCOMMONS_RNG_INT_STATUS */ "", 6829 /* CHIPCOMMONS_RNG_REV_ID */ "", 6830 /* CHIPCOMMONS_RNG_SOFT_RESET */ "", 6831 /* CHIPCOMMONS_RNG_TOTAL_BIT_COUNT */ "", 6832 /* CHIPCOMMONS_TYPE_TOTAL_BIT_COUNT_THRESHOLD */ "", 6833 /* CHIPCOMMONS_WDT_WDOGCONTROL */ "", 6834 /* CHIPCOMMONS_WDT_WDOGINTCLR */ "", 6835 /* CHIPCOMMONS_WDT_WDOGITCR */ "", 6836 /* CHIPCOMMONS_WDT_WDOGITOP */ "", 6837 /* CHIPCOMMONS_WDT_WDOGLOAD */ "", 6838 /* CHIPCOMMONS_WDT_WDOGLOCK */ "", 6839 /* CHIPCOMMONS_WDT_WDOGMIS */ "", 6840 /* CHIPCOMMONS_WDT_WDOGPCELLID0 */ "", 6841 /* CHIPCOMMONS_WDT_WDOGPCELLID1 */ "", 6842 /* CHIPCOMMONS_WDT_WDOGPCELLID2 */ "", 6843 /* CHIPCOMMONS_WDT_WDOGPCELLID3 */ "", 6844 /* CHIPCOMMONS_WDT_WDOGPERIPHID0 */ "", 6845 /* CHIPCOMMONS_WDT_WDOGPERIPHID1 */ "", 6846 /* CHIPCOMMONS_WDT_WDOGPERIPHID2 */ "", 6847 /* CHIPCOMMONS_WDT_WDOGPERIPHID3 */ "", 6848 /* CHIPCOMMONS_WDT_WDOGRIS */ "", 6849 /* CHIPCOMMONS_WDT_WDOGVALUE */ "", 6850 /* CHIP_CONFIG */ "", 6851 /* CHIP_CONFIG_ECC_STATUS */ "", 6852 /* CHIP_INDACC_CTLSTS */ "", 6853 /* CHIP_INDACC_RDATA */ "", 6854 /* CHIP_INDACC_WDATA */ "", 6855 /* CHIP_SBUS_CFG */ "", 6856 /* CHIP_SWRST */ "", 6857 /* CHIP_TEST */ "", 6858 /* CHIP_UMACSPEED */ "", 6859 /* CHLBSEL */ "", 6860 /* CH_BASE_EXPECTED */ "", 6861 /* CI0_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUG */ "", 6862 /* CI0_TO_EMC_WTAG_RETURN_COUNT_DEBUG */ "", 6863 /* CI1_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUG */ "", 6864 /* CI1_TO_EMC_WTAG_RETURN_COUNT_DEBUG */ "", 6865 /* CI2_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUG */ "", 6866 /* CI2_TO_EMC_WTAG_RETURN_COUNT_DEBUG */ "", 6867 /* CI3_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUG */ "", 6868 /* CI3_TO_EMC_WTAG_RETURN_COUNT_DEBUG */ "", 6869 /* CI4_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUG */ "", 6870 /* CI4_TO_EMC_WTAG_RETURN_COUNT_DEBUG */ "", 6871 /* CI5_TO_EMC_CELL_DATA_RETURN_COUNT_DEBUG */ "", 6872 /* CI5_TO_EMC_WTAG_RETURN_COUNT_DEBUG */ "", 6873 /* CI_CONFIG0 */ "", 6874 /* CI_CONFIG1 */ "", 6875 /* CI_CONFIG2 */ "", 6876 /* CI_CONFIG3 */ "", 6877 /* CI_CONFIG4 */ "", 6878 /* CI_CONFIG6 */ "", 6879 /* CI_CONFIG7 */ "", 6880 /* CI_DDR_AUTOINIT */ "", 6881 /* CI_DDR_BURST */ "", 6882 /* CI_DDR_ITER */ "", 6883 /* CI_DDR_MR0 */ "", 6884 /* CI_DDR_MR1 */ "", 6885 /* CI_DDR_MR2 */ "", 6886 /* CI_DDR_MR3 */ "", 6887 /* CI_DDR_PHY_REG_CTRL */ "", 6888 /* CI_DDR_PHY_REG_DATA */ "", 6889 /* CI_DDR_START */ "", 6890 /* CI_DDR_STEP */ "", 6891 /* CI_DDR_TEST */ "", 6892 /* CI_DDR_TEST_ALT_DATA0 */ "", 6893 /* CI_DDR_TEST_ALT_DATA1 */ "", 6894 /* CI_DDR_TEST_ALT_DATA2 */ "", 6895 /* CI_DDR_TEST_ALT_DATA3 */ "", 6896 /* CI_DDR_TEST_ALT_DATA4 */ "", 6897 /* CI_DDR_TEST_ALT_DATA5 */ "", 6898 /* CI_DDR_TEST_ALT_DATA6 */ "", 6899 /* CI_DDR_TEST_ALT_DATA7 */ "", 6900 /* CI_DDR_TEST_DATA0 */ "", 6901 /* CI_DDR_TEST_DATA1 */ "", 6902 /* CI_DDR_TEST_DATA2 */ "", 6903 /* CI_DDR_TEST_DATA3 */ "", 6904 /* CI_DDR_TEST_DATA4 */ "", 6905 /* CI_DDR_TEST_DATA5 */ "", 6906 /* CI_DDR_TEST_DATA6 */ "", 6907 /* CI_DDR_TEST_DATA7 */ "", 6908 /* CI_DDR_TEST_FAILED_DATA0 */ "", 6909 /* CI_DDR_TEST_FAILED_DATA1 */ "", 6910 /* CI_DDR_TEST_FAILED_DATA2 */ "", 6911 /* CI_DDR_TEST_FAILED_DATA3 */ "", 6912 /* CI_DDR_TEST_FAILED_DATA4 */ "", 6913 /* CI_DDR_TEST_FAILED_DATA5 */ "", 6914 /* CI_DDR_TEST_FAILED_DATA6 */ "", 6915 /* CI_DDR_TEST_FAILED_DATA7 */ "", 6916 /* CI_DEBUG */ "", 6917 /* CI_DEBUG_RD_LINES */ "", 6918 /* CI_DEBUG_WR_LINES */ "", 6919 /* CI_ECC_DEBUG */ "", 6920 /* CI_ECC_STATUS */ "", 6921 /* CI_ERROR */ "", 6922 /* CI_ERROR_MASK */ "", 6923 /* CI_FAILED_ADDR */ "", 6924 /* CI_MEM_ACC_CTRL */ "", 6925 /* CI_MEM_ACC_DATA0 */ "", 6926 /* CI_MEM_ACC_DATA1 */ "", 6927 /* CI_MEM_ACC_DATA2 */ "", 6928 /* CI_MEM_ACC_DATA3 */ "", 6929 /* CI_MEM_ACC_DATA4 */ "", 6930 /* CI_MEM_ACC_DATA5 */ "", 6931 /* CI_MEM_ACC_DATA6 */ "", 6932 /* CI_MEM_ACC_DATA7 */ "", 6933 /* CI_MEM_DEBUG0 */ "", 6934 /* CI_MEM_DEBUG1 */ "", 6935 /* CI_MRS_CMD */ "", 6936 /* CI_PHY_CONTROL */ "", 6937 /* CI_PHY_ERROR */ "", 6938 /* CI_PHY_STRAPS0 */ "", 6939 /* CI_PHY_STRAPS1 */ "", 6940 /* CI_PHY_STRAPS0_RET */ "", 6941 /* CI_PHY_STRAPS1_RET */ "", 6942 /* CI_PRBS_TEST_CTL */ "", 6943 /* CI_PRBS_TEST_ERROR01 */ "", 6944 /* CI_PRBS_TEST_ERROR23 */ "", 6945 /* CI_PRBS_TEST_FORCE_ERROR01 */ "", 6946 /* CI_PRBS_TEST_FORCE_ERROR23 */ "", 6947 /* CI_PRBS_TEST_MASK01 */ "", 6948 /* CI_PRBS_TEST_MASK23 */ "", 6949 /* CI_PRBS_TEST_SEED01 */ "", 6950 /* CI_PRBS_TEST_SEED23 */ "", 6951 /* CI_RESET */ "", 6952 /* CL22_B0_PHYID2 */ "", 6953 /* CL22_B0_PHYID3 */ "", 6954 /* CL82_AM_REGS_LANES_1_0_AM_BYTE2 */ "", 6955 /* CL82_AM_REGS_LANE_0_AM_BYTE10 */ "", 6956 /* CL82_AM_REGS_LANE_1_AM_BYTE10 */ "", 6957 /* CL82_BER_HO */ "", 6958 /* CL82_BER_LO */ "", 6959 /* CL82_ERRORED_BLOCKS_HO */ "", 6960 /* CL82_RX_LATCHED_STATUS */ "", 6961 /* CL82_RX_LIVE_STATUS */ "", 6962 /* CL82_SHARED_CL82_AM_TIMER */ "", 6963 /* CLCHPMC1_CHID_0 */ "", 6964 /* CLCHPMC1_CHID_1 */ "", 6965 /* CLCHPMC1_CHID_2 */ "", 6966 /* CLCHPMC1_CHID_3 */ "", 6967 /* CLCHPMC1_CHID_4 */ "", 6968 /* CLCHPMC1_CHID_5 */ "", 6969 /* CLCHPMC1_CHID_6 */ "", 6970 /* CLCHPMC1_CHID_7 */ "", 6971 /* CLCHPMC1_CHID_8 */ "", 6972 /* CLCHPMC1_CHID_9 */ "", 6973 /* CLCHPMC1_CHID_10 */ "", 6974 /* CLCHPMC1_CHID_11 */ "", 6975 /* CLCHPMC1_CHID_12 */ "", 6976 /* CLCHPMC1_CHID_13 */ "", 6977 /* CLCHPMC1_CHID_14 */ "", 6978 /* CLCHPMC1_CHID_15 */ "", 6979 /* CLCHPMC1_CHID_16 */ "", 6980 /* CLCHPMC1_CHID_17 */ "", 6981 /* CLCHPMC1_CHID_18 */ "", 6982 /* CLCHPMC1_CHID_19 */ "", 6983 /* CLCHPMC1_CHID_20 */ "", 6984 /* CLCHPMC1_CHID_21 */ "", 6985 /* CLCHPMC1_CHID_22 */ "", 6986 /* CLCHPMC1_CHID_23 */ "", 6987 /* CLCHPMC1_CHID_24 */ "", 6988 /* CLCHPMC1_CHID_25 */ "", 6989 /* CLCHPMC1_CHID_26 */ "", 6990 /* CLCHPMC1_CHID_27 */ "", 6991 /* CLCHPMC1_CHID_28 */ "", 6992 /* CLCHPMC1_CHID_29 */ "", 6993 /* CLCHPMC1_CHID_30 */ "", 6994 /* CLCHPMC1_CHID_31 */ "", 6995 /* CLCHPMC1_CHID_32 */ "", 6996 /* CLCHPMC1_CHID_33 */ "", 6997 /* CLCHPMC1_CHID_34 */ "", 6998 /* CLCHPMC1_CHID_35 */ "", 6999 /* CLCHPMC1_CHID_36 */ "", 7000 /* CLCHPMC1_CHID_37 */ "", 7001 /* CLCHPMC1_CHID_38 */ "", 7002 /* CLCHPMC1_CHID_39 */ "", 7003 /* CLCHPMC1_CHID_40 */ "", 7004 /* CLCHPMC1_CHID_41 */ "", 7005 /* CLCHPMC1_CHID_42 */ "", 7006 /* CLCHPMC1_CHID_43 */ "", 7007 /* CLCHPMC1_CHID_44 */ "", 7008 /* CLCHPMC1_CHID_45 */ "", 7009 /* CLCHPMC1_CHID_46 */ "", 7010 /* CLCHPMC1_CHID_47 */ "", 7011 /* CLCHPMC1_CHID_48 */ "", 7012 /* CLCHPMC1_CHID_49 */ "", 7013 /* CLCHPMC1_CHID_50 */ "", 7014 /* CLCHPMC1_CHID_51 */ "", 7015 /* CLCHPMC1_CHID_52 */ "", 7016 /* CLCHPMC1_CHID_53 */ "", 7017 /* CLCHPMC1_CHID_54 */ "", 7018 /* CLCHPMC1_CHID_55 */ "", 7019 /* CLCHPMC1_CHID_56 */ "", 7020 /* CLCHPMC1_CHID_57 */ "", 7021 /* CLCHPMC1_CHID_58 */ "", 7022 /* CLCHPMC1_CHID_59 */ "", 7023 /* CLCHPMC1_CHID_60 */ "", 7024 /* CLCHPMC1_CHID_61 */ "", 7025 /* CLCHPMC1_CHID_62 */ "", 7026 /* CLCHPMC1_CHID_63 */ "", 7027 /* CLCHPMC2_CHID_0 */ "", 7028 /* CLCHPMC2_CHID_1 */ "", 7029 /* CLCHPMC2_CHID_2 */ "", 7030 /* CLCHPMC2_CHID_3 */ "", 7031 /* CLCHPMC2_CHID_4 */ "", 7032 /* CLCHPMC2_CHID_5 */ "", 7033 /* CLCHPMC2_CHID_6 */ "", 7034 /* CLCHPMC2_CHID_7 */ "", 7035 /* CLCHPMC2_CHID_8 */ "", 7036 /* CLCHPMC2_CHID_9 */ "", 7037 /* CLCHPMC2_CHID_10 */ "", 7038 /* CLCHPMC2_CHID_11 */ "", 7039 /* CLCHPMC2_CHID_12 */ "", 7040 /* CLCHPMC2_CHID_13 */ "", 7041 /* CLCHPMC2_CHID_14 */ "", 7042 /* CLCHPMC2_CHID_15 */ "", 7043 /* CLCHPMC2_CHID_16 */ "", 7044 /* CLCHPMC2_CHID_17 */ "", 7045 /* CLCHPMC2_CHID_18 */ "", 7046 /* CLCHPMC2_CHID_19 */ "", 7047 /* CLCHPMC2_CHID_20 */ "", 7048 /* CLCHPMC2_CHID_21 */ "", 7049 /* CLCHPMC2_CHID_22 */ "", 7050 /* CLCHPMC2_CHID_23 */ "", 7051 /* CLCHPMC2_CHID_24 */ "", 7052 /* CLCHPMC2_CHID_25 */ "", 7053 /* CLCHPMC2_CHID_26 */ "", 7054 /* CLCHPMC2_CHID_27 */ "", 7055 /* CLCHPMC2_CHID_28 */ "", 7056 /* CLCHPMC2_CHID_29 */ "", 7057 /* CLCHPMC2_CHID_30 */ "", 7058 /* CLCHPMC2_CHID_31 */ "", 7059 /* CLCHPMC2_CHID_32 */ "", 7060 /* CLCHPMC2_CHID_33 */ "", 7061 /* CLCHPMC2_CHID_34 */ "", 7062 /* CLCHPMC2_CHID_35 */ "", 7063 /* CLCHPMC2_CHID_36 */ "", 7064 /* CLCHPMC2_CHID_37 */ "", 7065 /* CLCHPMC2_CHID_38 */ "", 7066 /* CLCHPMC2_CHID_39 */ "", 7067 /* CLCHPMC2_CHID_40 */ "", 7068 /* CLCHPMC2_CHID_41 */ "", 7069 /* CLCHPMC2_CHID_42 */ "", 7070 /* CLCHPMC2_CHID_43 */ "", 7071 /* CLCHPMC2_CHID_44 */ "", 7072 /* CLCHPMC2_CHID_45 */ "", 7073 /* CLCHPMC2_CHID_46 */ "", 7074 /* CLCHPMC2_CHID_47 */ "", 7075 /* CLCHPMC2_CHID_48 */ "", 7076 /* CLCHPMC2_CHID_49 */ "", 7077 /* CLCHPMC2_CHID_50 */ "", 7078 /* CLCHPMC2_CHID_51 */ "", 7079 /* CLCHPMC2_CHID_52 */ "", 7080 /* CLCHPMC2_CHID_53 */ "", 7081 /* CLCHPMC2_CHID_54 */ "", 7082 /* CLCHPMC2_CHID_55 */ "", 7083 /* CLCHPMC2_CHID_56 */ "", 7084 /* CLCHPMC2_CHID_57 */ "", 7085 /* CLCHPMC2_CHID_58 */ "", 7086 /* CLCHPMC2_CHID_59 */ "", 7087 /* CLCHPMC2_CHID_60 */ "", 7088 /* CLCHPMC2_CHID_61 */ "", 7089 /* CLCHPMC2_CHID_62 */ "", 7090 /* CLCHPMC2_CHID_63 */ "", 7091 /* CLCHPMC3_CHID_0 */ "", 7092 /* CLCHPMC3_CHID_1 */ "", 7093 /* CLCHPMC3_CHID_2 */ "", 7094 /* CLCHPMC3_CHID_3 */ "", 7095 /* CLCHPMC3_CHID_4 */ "", 7096 /* CLCHPMC3_CHID_5 */ "", 7097 /* CLCHPMC3_CHID_6 */ "", 7098 /* CLCHPMC3_CHID_7 */ "", 7099 /* CLCHPMC3_CHID_8 */ "", 7100 /* CLCHPMC3_CHID_9 */ "", 7101 /* CLCHPMC3_CHID_10 */ "", 7102 /* CLCHPMC3_CHID_11 */ "", 7103 /* CLCHPMC3_CHID_12 */ "", 7104 /* CLCHPMC3_CHID_13 */ "", 7105 /* CLCHPMC3_CHID_14 */ "", 7106 /* CLCHPMC3_CHID_15 */ "", 7107 /* CLCHPMC3_CHID_16 */ "", 7108 /* CLCHPMC3_CHID_17 */ "", 7109 /* CLCHPMC3_CHID_18 */ "", 7110 /* CLCHPMC3_CHID_19 */ "", 7111 /* CLCHPMC3_CHID_20 */ "", 7112 /* CLCHPMC3_CHID_21 */ "", 7113 /* CLCHPMC3_CHID_22 */ "", 7114 /* CLCHPMC3_CHID_23 */ "", 7115 /* CLCHPMC3_CHID_24 */ "", 7116 /* CLCHPMC3_CHID_25 */ "", 7117 /* CLCHPMC3_CHID_26 */ "", 7118 /* CLCHPMC3_CHID_27 */ "", 7119 /* CLCHPMC3_CHID_28 */ "", 7120 /* CLCHPMC3_CHID_29 */ "", 7121 /* CLCHPMC3_CHID_30 */ "", 7122 /* CLCHPMC3_CHID_31 */ "", 7123 /* CLCHPMC3_CHID_32 */ "", 7124 /* CLCHPMC3_CHID_33 */ "", 7125 /* CLCHPMC3_CHID_34 */ "", 7126 /* CLCHPMC3_CHID_35 */ "", 7127 /* CLCHPMC3_CHID_36 */ "", 7128 /* CLCHPMC3_CHID_37 */ "", 7129 /* CLCHPMC3_CHID_38 */ "", 7130 /* CLCHPMC3_CHID_39 */ "", 7131 /* CLCHPMC3_CHID_40 */ "", 7132 /* CLCHPMC3_CHID_41 */ "", 7133 /* CLCHPMC3_CHID_42 */ "", 7134 /* CLCHPMC3_CHID_43 */ "", 7135 /* CLCHPMC3_CHID_44 */ "", 7136 /* CLCHPMC3_CHID_45 */ "", 7137 /* CLCHPMC3_CHID_46 */ "", 7138 /* CLCHPMC3_CHID_47 */ "", 7139 /* CLCHPMC3_CHID_48 */ "", 7140 /* CLCHPMC3_CHID_49 */ "", 7141 /* CLCHPMC3_CHID_50 */ "", 7142 /* CLCHPMC3_CHID_51 */ "", 7143 /* CLCHPMC3_CHID_52 */ "", 7144 /* CLCHPMC3_CHID_53 */ "", 7145 /* CLCHPMC3_CHID_54 */ "", 7146 /* CLCHPMC3_CHID_55 */ "", 7147 /* CLCHPMC3_CHID_56 */ "", 7148 /* CLCHPMC3_CHID_57 */ "", 7149 /* CLCHPMC3_CHID_58 */ "", 7150 /* CLCHPMC3_CHID_59 */ "", 7151 /* CLCHPMC3_CHID_60 */ "", 7152 /* CLCHPMC3_CHID_61 */ "", 7153 /* CLCHPMC3_CHID_62 */ "", 7154 /* CLCHPMC3_CHID_63 */ "", 7155 /* CLCHPMC4_CHID_0 */ "", 7156 /* CLCHPMC4_CHID_1 */ "", 7157 /* CLCHPMC4_CHID_2 */ "", 7158 /* CLCHPMC4_CHID_3 */ "", 7159 /* CLCHPMC4_CHID_4 */ "", 7160 /* CLCHPMC4_CHID_5 */ "", 7161 /* CLCHPMC4_CHID_6 */ "", 7162 /* CLCHPMC4_CHID_7 */ "", 7163 /* CLCHPMC4_CHID_8 */ "", 7164 /* CLCHPMC4_CHID_9 */ "", 7165 /* CLCHPMC4_CHID_10 */ "", 7166 /* CLCHPMC4_CHID_11 */ "", 7167 /* CLCHPMC4_CHID_12 */ "", 7168 /* CLCHPMC4_CHID_13 */ "", 7169 /* CLCHPMC4_CHID_14 */ "", 7170 /* CLCHPMC4_CHID_15 */ "", 7171 /* CLCHPMC4_CHID_16 */ "", 7172 /* CLCHPMC4_CHID_17 */ "", 7173 /* CLCHPMC4_CHID_18 */ "", 7174 /* CLCHPMC4_CHID_19 */ "", 7175 /* CLCHPMC4_CHID_20 */ "", 7176 /* CLCHPMC4_CHID_21 */ "", 7177 /* CLCHPMC4_CHID_22 */ "", 7178 /* CLCHPMC4_CHID_23 */ "", 7179 /* CLCHPMC4_CHID_24 */ "", 7180 /* CLCHPMC4_CHID_25 */ "", 7181 /* CLCHPMC4_CHID_26 */ "", 7182 /* CLCHPMC4_CHID_27 */ "", 7183 /* CLCHPMC4_CHID_28 */ "", 7184 /* CLCHPMC4_CHID_29 */ "", 7185 /* CLCHPMC4_CHID_30 */ "", 7186 /* CLCHPMC4_CHID_31 */ "", 7187 /* CLCHPMC4_CHID_32 */ "", 7188 /* CLCHPMC4_CHID_33 */ "", 7189 /* CLCHPMC4_CHID_34 */ "", 7190 /* CLCHPMC4_CHID_35 */ "", 7191 /* CLCHPMC4_CHID_36 */ "", 7192 /* CLCHPMC4_CHID_37 */ "", 7193 /* CLCHPMC4_CHID_38 */ "", 7194 /* CLCHPMC4_CHID_39 */ "", 7195 /* CLCHPMC4_CHID_40 */ "", 7196 /* CLCHPMC4_CHID_41 */ "", 7197 /* CLCHPMC4_CHID_42 */ "", 7198 /* CLCHPMC4_CHID_43 */ "", 7199 /* CLCHPMC4_CHID_44 */ "", 7200 /* CLCHPMC4_CHID_45 */ "", 7201 /* CLCHPMC4_CHID_46 */ "", 7202 /* CLCHPMC4_CHID_47 */ "", 7203 /* CLCHPMC4_CHID_48 */ "", 7204 /* CLCHPMC4_CHID_49 */ "", 7205 /* CLCHPMC4_CHID_50 */ "", 7206 /* CLCHPMC4_CHID_51 */ "", 7207 /* CLCHPMC4_CHID_52 */ "", 7208 /* CLCHPMC4_CHID_53 */ "", 7209 /* CLCHPMC4_CHID_54 */ "", 7210 /* CLCHPMC4_CHID_55 */ "", 7211 /* CLCHPMC4_CHID_56 */ "", 7212 /* CLCHPMC4_CHID_57 */ "", 7213 /* CLCHPMC4_CHID_58 */ "", 7214 /* CLCHPMC4_CHID_59 */ "", 7215 /* CLCHPMC4_CHID_60 */ "", 7216 /* CLCHPMC4_CHID_61 */ "", 7217 /* CLCHPMC4_CHID_62 */ "", 7218 /* CLCHPMC4_CHID_63 */ "", 7219 /* CLDROPC */ "", 7220 /* CLG2MAC_CLEAR_ECC_STATUS */ "", 7221 /* CLG2MAC_CLEAR_FIFO_STATUS */ "", 7222 /* CLG2MAC_CLEAR_RX_LSS_STATUS */ "", 7223 /* CLG2MAC_CTRL */ "", 7224 /* CLG2MAC_E2ECC_DATA_HDR_0 */ "", 7225 /* CLG2MAC_E2ECC_DATA_HDR_1 */ "", 7226 /* CLG2MAC_E2ECC_MODULE_HDR_0 */ "", 7227 /* CLG2MAC_E2ECC_MODULE_HDR_1 */ "", 7228 /* CLG2MAC_E2EFC_DATA_HDR_0 */ "", 7229 /* CLG2MAC_E2EFC_DATA_HDR_1 */ "", 7230 /* CLG2MAC_E2EFC_MODULE_HDR_0 */ "", 7231 /* CLG2MAC_E2EFC_MODULE_HDR_1 */ "", 7232 /* CLG2MAC_E2E_CTRL */ "", 7233 /* CLG2MAC_ECC_CTRL */ "", 7234 /* CLG2MAC_ECC_FORCE_DOUBLE_BIT_ERR */ "", 7235 /* CLG2MAC_ECC_FORCE_SINGLE_BIT_ERR */ "", 7236 /* CLG2MAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 7237 /* CLG2MAC_EEE_CTRL */ "", 7238 /* CLG2MAC_EEE_TIMERS */ "", 7239 /* CLG2MAC_FIFO_STATUS */ "", 7240 /* CLG2MAC_GMII_EEE_CTRL */ "", 7241 /* CLG2MAC_HIGIG_HDR_0 */ "", 7242 /* CLG2MAC_HIGIG_HDR_1 */ "", 7243 /* CLG2MAC_INTR_ENABLE */ "", 7244 /* CLG2MAC_INTR_STATUS */ "", 7245 /* CLG2MAC_LAG_FAILOVER_STATUS */ "", 7246 /* CLG2MAC_LLFC_CTRL */ "", 7247 /* CLG2MAC_MEM_CTRL */ "", 7248 /* CLG2MAC_MODE */ "", 7249 /* CLG2MAC_PAUSE_CTRL */ "", 7250 /* CLG2MAC_PFC_CTRL */ "", 7251 /* CLG2MAC_PFC_DA */ "", 7252 /* CLG2MAC_PFC_OPCODE */ "", 7253 /* CLG2MAC_PFC_TYPE */ "", 7254 /* CLG2MAC_RX_CDC_ECC_STATUS */ "", 7255 /* CLG2MAC_RX_CTRL */ "", 7256 /* CLG2MAC_RX_LLFC_MSG_FIELDS */ "", 7257 /* CLG2MAC_RX_LSS_CTRL */ "", 7258 /* CLG2MAC_RX_LSS_STATUS */ "", 7259 /* CLG2MAC_RX_MAC_SA */ "", 7260 /* CLG2MAC_RX_MAX_SIZE */ "", 7261 /* CLG2MAC_RX_TS_MEM_ECC_STATUS */ "", 7262 /* CLG2MAC_RX_VLAN_TAG */ "", 7263 /* CLG2MAC_SPARE0 */ "", 7264 /* CLG2MAC_SPARE1 */ "", 7265 /* CLG2MAC_TIMESTAMP_ADJUST */ "", 7266 /* CLG2MAC_TIMESTAMP_BYTE_ADJUST */ "", 7267 /* CLG2MAC_TXFIFO_CELL_CNT */ "", 7268 /* CLG2MAC_TXFIFO_CELL_REQ_CNT */ "", 7269 /* CLG2MAC_TX_CDC_ECC_STATUS */ "", 7270 /* CLG2MAC_TX_CRC_CORRUPT_CTRL */ "", 7271 /* CLG2MAC_TX_CTRL */ "", 7272 /* CLG2MAC_TX_LLFC_MSG_FIELDS */ "", 7273 /* CLG2MAC_TX_MAC_SA */ "", 7274 /* CLG2MAC_TX_TIMESTAMP_FIFO_DATA */ "", 7275 /* CLG2MAC_TX_TIMESTAMP_FIFO_STATUS */ "", 7276 /* CLG2MAC_VERSION_ID */ "", 7277 /* CLGPMC1 */ "", 7278 /* CLGPMC2 */ "", 7279 /* CLGPMC3 */ "", 7280 /* CLGPMC4 */ "", 7281 /* CLGPMC5 */ "", 7282 /* CLGPMC6 */ "", 7283 /* CLGPMC7 */ "", 7284 /* CLGPMC8 */ "", 7285 /* CLINK_ERROR */ "", 7286 /* CLINK_ERROR_MASK */ "", 7287 /* CLKACT */ "", 7288 /* CLMAC_CLEAR_ECC_STATUS */ "", 7289 /* CLMAC_CLEAR_FIFO_STATUS */ "", 7290 /* CLMAC_CLEAR_RX_LSS_STATUS */ "", 7291 /* CLMAC_CTRL */ "", 7292 /* CLMAC_E2ECC_DATA_HDR_0 */ "", 7293 /* CLMAC_E2ECC_DATA_HDR_1 */ "", 7294 /* CLMAC_E2ECC_MODULE_HDR_0 */ "", 7295 /* CLMAC_E2ECC_MODULE_HDR_1 */ "", 7296 /* CLMAC_E2EFC_DATA_HDR_0 */ "", 7297 /* CLMAC_E2EFC_DATA_HDR_1 */ "", 7298 /* CLMAC_E2EFC_MODULE_HDR_0 */ "", 7299 /* CLMAC_E2EFC_MODULE_HDR_1 */ "", 7300 /* CLMAC_E2E_CTRL */ "", 7301 /* CLMAC_ECC_CTRL */ "", 7302 /* CLMAC_ECC_FORCE_DOUBLE_BIT_ERR */ "", 7303 /* CLMAC_ECC_FORCE_SINGLE_BIT_ERR */ "", 7304 /* CLMAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 7305 /* CLMAC_EEE_CTRL */ "", 7306 /* CLMAC_EEE_TIMERS */ "", 7307 /* CLMAC_FIFO_STATUS */ "", 7308 /* CLMAC_GMII_EEE_CTRL */ "", 7309 /* CLMAC_HIGIG_HDR_0 */ "", 7310 /* CLMAC_HIGIG_HDR_1 */ "", 7311 /* CLMAC_INTR_ENABLE */ "", 7312 /* CLMAC_INTR_STATUS */ "", 7313 /* CLMAC_LAG_FAILOVER_STATUS */ "", 7314 /* CLMAC_LLFC_CTRL */ "", 7315 /* CLMAC_MEM_CTRL */ "", 7316 /* CLMAC_MERGE_CLEAR_STATUS */ "", 7317 /* CLMAC_MERGE_CONFIG */ "", 7318 /* CLMAC_MERGE_CTRL_SECRET_CONFIG */ "", 7319 /* CLMAC_MERGE_FRG_CNT_CONFIG */ "", 7320 /* CLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG */ "", 7321 /* CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0 */ "", 7322 /* CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1 */ "", 7323 /* CLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2 */ "", 7324 /* CLMAC_MERGE_RX_TIMEOUT_CONFIG */ "", 7325 /* CLMAC_MERGE_SMD_CONFIG_0 */ "", 7326 /* CLMAC_MERGE_SMD_CONFIG_1 */ "", 7327 /* CLMAC_MERGE_STATUS */ "", 7328 /* CLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG */ "", 7329 /* CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0 */ "", 7330 /* CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1 */ "", 7331 /* CLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2 */ "", 7332 /* CLMAC_MERGE_VERIFY_STATE */ "", 7333 /* CLMAC_MODE */ "", 7334 /* CLMAC_PAUSE_CTRL */ "", 7335 /* CLMAC_PFC_CTRL */ "", 7336 /* CLMAC_PFC_DA */ "", 7337 /* CLMAC_PFC_OPCODE */ "", 7338 /* CLMAC_PFC_TYPE */ "", 7339 /* CLMAC_RX_CDC_ECC_STATUS */ "", 7340 /* CLMAC_RX_CTRL */ "", 7341 /* CLMAC_RX_LLFC_MSG_FIELDS */ "", 7342 /* CLMAC_RX_LSS_CTRL */ "", 7343 /* CLMAC_RX_LSS_STATUS */ "", 7344 /* CLMAC_RX_MAC_SA */ "", 7345 /* CLMAC_RX_MAX_SIZE */ "", 7346 /* CLMAC_RX_TS_MEM_ECC_STATUS */ "", 7347 /* CLMAC_RX_VLAN_TAG */ "", 7348 /* CLMAC_SPARE0 */ "", 7349 /* CLMAC_SPARE1 */ "", 7350 /* CLMAC_TIMESTAMP_ADJUST */ "", 7351 /* CLMAC_TIMESTAMP_BYTE_ADJUST */ "", 7352 /* CLMAC_TXFIFO_CELL_CNT */ "", 7353 /* CLMAC_TXFIFO_CELL_REQ_CNT */ "", 7354 /* CLMAC_TX_CDC_ECC_STATUS */ "", 7355 /* CLMAC_TX_CRC_CORRUPT_CTRL */ "", 7356 /* CLMAC_TX_CTRL */ "", 7357 /* CLMAC_TX_EP_CREDITS_CONFIG */ "", 7358 /* CLMAC_TX_LLFC_MSG_FIELDS */ "", 7359 /* CLMAC_TX_MAC_SA */ "", 7360 /* CLMAC_TX_TIMESTAMP_FIFO_DATA */ "", 7361 /* CLMAC_TX_TIMESTAMP_FIFO_STATUS */ "", 7362 /* CLMAC_VERSION_ID */ "", 7363 /* CLMIB_R64 */ "CLMIB_GRx64", 7364 /* CLMIB_R127 */ "CLMIB_GRx127", 7365 /* CLMIB_R255 */ "CLMIB_GRx255", 7366 /* CLMIB_R511 */ "CLMIB_GRx511", 7367 /* CLMIB_R1023 */ "CLMIB_GRx1023", 7368 /* CLMIB_R1518 */ "CLMIB_GRx1518", 7369 /* CLMIB_R2047 */ "CLMIB_GRx2047", 7370 /* CLMIB_R4095 */ "CLMIB_GRx4095", 7371 /* CLMIB_R9216 */ "CLMIB_GRx9216", 7372 /* CLMIB_R16383 */ "CLMIB_GRx16383", 7373 /* CLMIB_RALN */ "CLMIB_GRxALN", 7374 /* CLMIB_RBCA */ "CLMIB_GRxBCA", 7375 /* CLMIB_RBYT */ "CLMIB_GRxByt", 7376 /* CLMIB_RDVLN */ "CLMIB_GRxDVLN", 7377 /* CLMIB_RERPKT */ "CLMIB_GRxFrErr", 7378 /* CLMIB_RFCR */ "CLMIB_GRxFCR", 7379 /* CLMIB_RFCS */ "CLMIB_GRxFCS", 7380 /* CLMIB_RFLR */ "CLMIB_GRxFLR", 7381 /* CLMIB_RFRG */ "CLMIB_GRxFRG", 7382 /* CLMIB_RJBR */ "CLMIB_GRxJBR", 7383 /* CLMIB_RMCA */ "CLMIB_GRxMCA", 7384 /* CLMIB_RMCRC */ "CLMIB_GRxMCRC", 7385 /* CLMIB_RMGV */ "CLMIB_GRx1522", 7386 /* CLMIB_RMTUE */ "CLMIB_GRxMTUE", 7387 /* CLMIB_ROVR */ "CLMIB_GRxOVR", 7388 /* CLMIB_RPFC0 */ "CLMIB_GRxPFCP0", 7389 /* CLMIB_RPFC1 */ "CLMIB_GRxPFCP1", 7390 /* CLMIB_RPFC2 */ "CLMIB_GRxPFCP2", 7391 /* CLMIB_RPFC3 */ "CLMIB_GRxPFCP3", 7392 /* CLMIB_RPFC4 */ "CLMIB_GRxPFCP4", 7393 /* CLMIB_RPFC5 */ "CLMIB_GRxPFCP5", 7394 /* CLMIB_RPFC6 */ "CLMIB_GRxPFCP6", 7395 /* CLMIB_RPFC7 */ "CLMIB_GRxPFCP7", 7396 /* CLMIB_RPFCOFF0 */ "CLMIB_GRxPFCOFF0", 7397 /* CLMIB_RPFCOFF1 */ "CLMIB_GRxPFCOFF1", 7398 /* CLMIB_RPFCOFF2 */ "CLMIB_GRxPFCOFF2", 7399 /* CLMIB_RPFCOFF3 */ "CLMIB_GRxPFCOFF3", 7400 /* CLMIB_RPFCOFF4 */ "CLMIB_GRxPFCOFF4", 7401 /* CLMIB_RPFCOFF5 */ "CLMIB_GRxPFCOFF5", 7402 /* CLMIB_RPFCOFF6 */ "CLMIB_GRxPFCOFF6", 7403 /* CLMIB_RPFCOFF7 */ "CLMIB_GRxPFCOFF7", 7404 /* CLMIB_RPKT */ "CLMIB_GRxPkt", 7405 /* CLMIB_RPOK */ "CLMIB_GRxPOK", 7406 /* CLMIB_RPRM */ "CLMIB_GRxPRM", 7407 /* CLMIB_RPROG0 */ "CLMIB_GRxProg0", 7408 /* CLMIB_RPROG1 */ "CLMIB_GRxProg1", 7409 /* CLMIB_RPROG2 */ "CLMIB_GRxProg2", 7410 /* CLMIB_RPROG3 */ "CLMIB_GRxProg3", 7411 /* CLMIB_RRBYT */ "CLMIB_GRxRByt", 7412 /* CLMIB_RRPKT */ "CLMIB_GRxRPkt", 7413 /* CLMIB_RSCHCRC */ "CLMIB_GRxSCHCRC", 7414 /* CLMIB_RTRFU */ "CLMIB_GRxTRFU", 7415 /* CLMIB_RUCA */ "CLMIB_GRxUCA", 7416 /* CLMIB_RUND */ "CLMIB_GRxUND", 7417 /* CLMIB_RVLN */ "CLMIB_GRxVLN", 7418 /* CLMIB_RXCF */ "CLMIB_GRxCF", 7419 /* CLMIB_RXPF */ "CLMIB_GRxPF", 7420 /* CLMIB_RXPP */ "CLMIB_GRxPP", 7421 /* CLMIB_RXUDA */ "CLMIB_GRxUDA", 7422 /* CLMIB_RXUO */ "CLMIB_GRxUO", 7423 /* CLMIB_RXWSA */ "CLMIB_GRxWSA", 7424 /* CLMIB_RX_EEE_LPI_DURATION_COUNTER */ "CLMIB_RX_EEE_LPI_DURATION_COUNTER", 7425 /* CLMIB_RX_EEE_LPI_EVENT_COUNTER */ "CLMIB_RX_EEE_LPI_EVENT_COUNTER", 7426 /* CLMIB_RX_HCFC_COUNTER */ "CLMIB_RX_HCFC_COUNTER", 7427 /* CLMIB_RX_HCFC_CRC_COUNTER */ "CLMIB_RX_HCFC_CRC_COUNTER", 7428 /* CLMIB_RX_LLFC_CRC_COUNTER */ "CLMIB_RX_LLFC_CRC_COUNTER", 7429 /* CLMIB_RX_LLFC_LOG_COUNTER */ "CLMIB_RX_LLFC_LOG_COUNTER", 7430 /* CLMIB_RX_LLFC_PHY_COUNTER */ "CLMIB_RX_LLFC_PHY_COUNTER", 7431 /* CLMIB_T64 */ "CLMIB_GTx64", 7432 /* CLMIB_T127 */ "CLMIB_GTx127", 7433 /* CLMIB_T255 */ "CLMIB_GTx255", 7434 /* CLMIB_T511 */ "CLMIB_GTx511", 7435 /* CLMIB_T1023 */ "CLMIB_GTx1023", 7436 /* CLMIB_T1518 */ "CLMIB_GTx1518", 7437 /* CLMIB_T2047 */ "CLMIB_GTx2047", 7438 /* CLMIB_T4095 */ "CLMIB_GTx4095", 7439 /* CLMIB_T9216 */ "CLMIB_GTx9216", 7440 /* CLMIB_T16383 */ "CLMIB_GTx16383", 7441 /* CLMIB_TBCA */ "CLMIB_GTxBCA", 7442 /* CLMIB_TBYT */ "CLMIB_GTxBYT", 7443 /* CLMIB_TDFR */ "CLMIB_GTxDFR", 7444 /* CLMIB_TDVLN */ "CLMIB_GTxDVLN", 7445 /* CLMIB_TEDF */ "CLMIB_GTxEDF", 7446 /* CLMIB_TERR */ "CLMIB_GTxErr", 7447 /* CLMIB_TFCS */ "CLMIB_GTxFCS", 7448 /* CLMIB_TFRG */ "CLMIB_GTxFRG", 7449 /* CLMIB_TJBR */ "CLMIB_GTxJBR", 7450 /* CLMIB_TLCL */ "CLMIB_GTxLCL", 7451 /* CLMIB_TMCA */ "CLMIB_GTxMCA", 7452 /* CLMIB_TMCL */ "CLMIB_GTxMCL", 7453 /* CLMIB_TMGV */ "CLMIB_GTx1522", 7454 /* CLMIB_TNCL */ "CLMIB_GTxNCL", 7455 /* CLMIB_TOVR */ "CLMIB_GTxOVR", 7456 /* CLMIB_TPFC0 */ "CLMIB_GTxPFCP0", 7457 /* CLMIB_TPFC1 */ "CLMIB_GTxPFCP1", 7458 /* CLMIB_TPFC2 */ "CLMIB_GTxPFCP2", 7459 /* CLMIB_TPFC3 */ "CLMIB_GTxPFCP3", 7460 /* CLMIB_TPFC4 */ "CLMIB_GTxPFCP4", 7461 /* CLMIB_TPFC5 */ "CLMIB_GTxPFCP5", 7462 /* CLMIB_TPFC6 */ "CLMIB_GTxPFCP6", 7463 /* CLMIB_TPFC7 */ "CLMIB_GTxPFCP7", 7464 /* CLMIB_TPFCOFF0 */ "CLMIB_GTxPFCOFF0", 7465 /* CLMIB_TPFCOFF1 */ "CLMIB_GTxPFCOFF1", 7466 /* CLMIB_TPFCOFF2 */ "CLMIB_GTxPFCOFF2", 7467 /* CLMIB_TPFCOFF3 */ "CLMIB_GTxPFCOFF3", 7468 /* CLMIB_TPFCOFF4 */ "CLMIB_GTxPFCOFF4", 7469 /* CLMIB_TPFCOFF5 */ "CLMIB_GTxPFCOFF5", 7470 /* CLMIB_TPFCOFF6 */ "CLMIB_GTxPFCOFF6", 7471 /* CLMIB_TPFCOFF7 */ "CLMIB_GTxPFCOFF7", 7472 /* CLMIB_TPKT */ "CLMIB_GTxPkt", 7473 /* CLMIB_TPOK */ "CLMIB_GTxPOK", 7474 /* CLMIB_TRPKT */ "CLMIB_GTxRPKT", 7475 /* CLMIB_TSCL */ "CLMIB_GTxSCL", 7476 /* CLMIB_TSPARE0 */ "CLMIB_GTxSPARE0", 7477 /* CLMIB_TSPARE1 */ "CLMIB_GTxSPARE1", 7478 /* CLMIB_TSPARE2 */ "CLMIB_GTxSPARE2", 7479 /* CLMIB_TSPARE3 */ "CLMIB_GTxSPARE3", 7480 /* CLMIB_TUCA */ "CLMIB_GTxUCA", 7481 /* CLMIB_TUFL */ "CLMIB_GTxUFL", 7482 /* CLMIB_TVLN */ "CLMIB_GTxVLN", 7483 /* CLMIB_TXCF */ "CLMIB_GTxCF", 7484 /* CLMIB_TXCL */ "CLMIB_GTxXCL", 7485 /* CLMIB_TXPF */ "CLMIB_GTxPF", 7486 /* CLMIB_TXPP */ "CLMIB_GTxPP", 7487 /* CLMIB_TX_EEE_LPI_DURATION_COUNTER */ "CLMIB_TX_EEE_LPI_DURATION_COUNTER", 7488 /* CLMIB_TX_EEE_LPI_EVENT_COUNTER */ "CLMIB_TX_EEE_LPI_EVENT_COUNTER", 7489 /* CLMIB_TX_HCFC_COUNTER */ "CLMIB_TX_HCFC_COUNTER", 7490 /* CLMIB_TX_LLFC_LOG_COUNTER */ "CLMIB_TX_LLFC_LOG_COUNTER", 7491 /* CLMIB_XTHOL */ "CLMIB_XTHOL", 7492 /* CLPORT_CNTMAXSIZE */ "", 7493 /* CLPORT_CONFIG */ "", 7494 /* CLPORT_ECC_CONTROL */ "", 7495 /* CLPORT_EEE_CLOCK_GATE */ "", 7496 /* CLPORT_EEE_CORE0_CLOCK_GATE_COUNTER */ "", 7497 /* CLPORT_EEE_COUNTER_MODE */ "", 7498 /* CLPORT_EEE_DURATION_TIMER_PULSE */ "", 7499 /* CLPORT_ENABLE_REG */ "", 7500 /* CLPORT_FAULT_LINK_STATUS */ "", 7501 /* CLPORT_FLOW_CONTROL_CONFIG */ "", 7502 /* CLPORT_FORCE_DOUBLE_BIT_ERROR */ "", 7503 /* CLPORT_FORCE_SINGLE_BIT_ERROR */ "", 7504 /* CLPORT_GENERAL_SPARE1_REG */ "", 7505 /* CLPORT_GENERAL_SPARE2_REG */ "", 7506 /* CLPORT_GENERAL_SPARE3_REG */ "", 7507 /* CLPORT_GENERAL_SPARE6_REG */ "", 7508 /* CLPORT_GENERAL_SPARE7_REG */ "", 7509 /* CLPORT_INTR_ENABLE */ "", 7510 /* CLPORT_INTR_STATUS */ "", 7511 /* CLPORT_LAG_FAILOVER_CONFIG */ "", 7512 /* CLPORT_LED_CHAIN_CONFIG */ "", 7513 /* CLPORT_LINKSTATUS_DOWN */ "", 7514 /* CLPORT_LINKSTATUS_DOWN_CLEAR */ "", 7515 /* CLPORT_MAC_CONTROL */ "", 7516 /* CLPORT_MAC_RSV_MASK */ "", 7517 /* CLPORT_MIB_MIN_FRAG_SIZE */ "", 7518 /* CLPORT_MIB_PROG_RANGE_CNTR0_CONFIG */ "", 7519 /* CLPORT_MIB_PROG_RANGE_CNTR1_CONFIG */ "", 7520 /* CLPORT_MIB_PROG_RANGE_CNTR2_CONFIG */ "", 7521 /* CLPORT_MIB_PROG_RANGE_CNTR3_CONFIG */ "", 7522 /* CLPORT_MIB_RESET */ "", 7523 /* CLPORT_MIB_RSC0_ECC_STATUS */ "", 7524 /* CLPORT_MIB_RSC1_ECC_STATUS */ "", 7525 /* CLPORT_MIB_RSC_RAM_CONTROL */ "", 7526 /* CLPORT_MIB_TSC0_ECC_STATUS */ "", 7527 /* CLPORT_MIB_TSC1_ECC_STATUS */ "", 7528 /* CLPORT_MIB_TSC_RAM_CONTROL */ "", 7529 /* CLPORT_MODE_REG */ "", 7530 /* CLPORT_PMD_PLL0_CTRL_CONFIG */ "", 7531 /* CLPORT_PMD_PLL1_CTRL_CONFIG */ "", 7532 /* CLPORT_PMD_PLL_CTRL_CONFIG */ "", 7533 /* CLPORT_PM_VERSION_ID */ "", 7534 /* CLPORT_PORT_SPARE0 */ "", 7535 /* CLPORT_PORT_SPARE1 */ "", 7536 /* CLPORT_PORT_SPARE2 */ "", 7537 /* CLPORT_PORT_SPARE3 */ "", 7538 /* CLPORT_POWER_SAVE */ "", 7539 /* CLPORT_SBUS_CONTROL */ "", 7540 /* CLPORT_SGNDET_EARLYCRS */ "", 7541 /* CLPORT_SOFT_RESET */ "", 7542 /* CLPORT_SPARE0_REG */ "", 7543 /* CLPORT_SW_FLOW_CONTROL */ "", 7544 /* CLPORT_TSC_PLL_LOCK_STATUS */ "", 7545 /* CLPORT_TS_TIMER_31_0_REG */ "", 7546 /* CLPORT_TS_TIMER_47_32_REG */ "", 7547 /* CLPORT_TXPI_CSR_CTRL1 */ "", 7548 /* CLPORT_TXPI_CSR_OVER_EN */ "", 7549 /* CLPORT_TXPI_CSR_OVER_VAL_0_HIGH */ "", 7550 /* CLPORT_TXPI_CSR_OVER_VAL_0_LOW */ "", 7551 /* CLPORT_TXPI_CSR_OVER_VAL_1_HIGH */ "", 7552 /* CLPORT_TXPI_CSR_OVER_VAL_1_LOW */ "", 7553 /* CLPORT_TXPI_CSR_OVER_VAL_2_HIGH */ "", 7554 /* CLPORT_TXPI_CSR_OVER_VAL_2_LOW */ "", 7555 /* CLPORT_TXPI_CSR_OVER_VAL_3_HIGH */ "", 7556 /* CLPORT_TXPI_CSR_OVER_VAL_3_LOW */ "", 7557 /* CLPORT_TXPI_DATA_OUT_STS_0_HIGH */ "", 7558 /* CLPORT_TXPI_DATA_OUT_STS_0_LOW */ "", 7559 /* CLPORT_TXPI_DATA_OUT_STS_1_HIGH */ "", 7560 /* CLPORT_TXPI_DATA_OUT_STS_1_LOW */ "", 7561 /* CLPORT_TXPI_DATA_OUT_STS_2_HIGH */ "", 7562 /* CLPORT_TXPI_DATA_OUT_STS_2_LOW */ "", 7563 /* CLPORT_TXPI_DATA_OUT_STS_3_HIGH */ "", 7564 /* CLPORT_TXPI_DATA_OUT_STS_3_LOW */ "", 7565 /* CLPORT_TXPI_LANE_SELECTION */ "", 7566 /* CLPORT_WC_UCMEM_CTRL */ "", 7567 /* CLPORT_XGXS0_CTRL_REG */ "", 7568 /* CLPORT_XGXS0_LN0_STATUS0_REG */ "", 7569 /* CLPORT_XGXS0_LN1_STATUS0_REG */ "", 7570 /* CLPORT_XGXS0_LN2_STATUS0_REG */ "", 7571 /* CLPORT_XGXS0_LN3_STATUS0_REG */ "", 7572 /* CLPORT_XGXS_COUNTER_MODE */ "", 7573 /* CLP_CMAC_CLEAR_ECC_STATUS */ "", 7574 /* CLP_CMAC_CLEAR_FIFO_STATUS */ "", 7575 /* CLP_CMAC_CLEAR_RX_LSS_STATUS */ "", 7576 /* CLP_CMAC_CTRL */ "", 7577 /* CLP_CMAC_ECC_CTRL */ "", 7578 /* CLP_CMAC_ECC_STATUS */ "", 7579 /* CLP_CMAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 7580 /* CLP_CMAC_EEE_CTRL */ "", 7581 /* CLP_CMAC_EEE_TIMERS */ "", 7582 /* CLP_CMAC_FIFO_STATUS */ "", 7583 /* CLP_CMAC_LLFC_CTRL */ "", 7584 /* CLP_CMAC_MODE */ "", 7585 /* CLP_CMAC_PAUSE_CTRL */ "", 7586 /* CLP_CMAC_PFC_CTRL */ "", 7587 /* CLP_CMAC_PFC_DA */ "", 7588 /* CLP_CMAC_PFC_OPCODE */ "", 7589 /* CLP_CMAC_PFC_TYPE */ "", 7590 /* CLP_CMAC_RX_CTRL */ "", 7591 /* CLP_CMAC_RX_LLFC_MSG_FIELDS */ "", 7592 /* CLP_CMAC_RX_LSS_CTRL */ "", 7593 /* CLP_CMAC_RX_LSS_STATUS */ "", 7594 /* CLP_CMAC_RX_MAC_SA */ "", 7595 /* CLP_CMAC_RX_MAX_SIZE */ "", 7596 /* CLP_CMAC_RX_VLAN_TAG */ "", 7597 /* CLP_CMAC_TIMESTAMP_ADJUST */ "", 7598 /* CLP_CMAC_TX_CTRL */ "", 7599 /* CLP_CMAC_TX_FIFO_CREDITS */ "", 7600 /* CLP_CMAC_TX_LLFC_MSG_FIELDS */ "", 7601 /* CLP_CMAC_TX_MAC_SA */ "", 7602 /* CLP_CMAC_TX_TIMESTAMP_FIFO_DATA */ "", 7603 /* CLP_CMAC_TX_TIMESTAMP_FIFO_STATUS */ "", 7604 /* CLP_CMAC_VERSION_ID */ "", 7605 /* CLP_PORT_CMAC_MODE */ "", 7606 /* CLP_REG_040200 */ "", 7607 /* CLP_REG_040300 */ "", 7608 /* CLP_REG_041500 */ "", 7609 /* CLP_REG_060200 */ "", 7610 /* CLP_REG_060300 */ "", 7611 /* CLP_REG_061500 */ "", 7612 /* CLP_REG_062000 */ "", 7613 /* CLP_REG_062200 */ "", 7614 /* CLP_REG_062500 */ "", 7615 /* CLP_REG_2022300 */ "", 7616 /* CLP_REG_041F00 */ "", 7617 /* CLP_REG_061E00 */ "", 7618 /* CLP_REG_061F00 */ "", 7619 /* CLP_XMAC_CLEAR_FIFO_STATUS */ "", 7620 /* CLP_XMAC_CLEAR_RX_LSS_STATUS */ "", 7621 /* CLP_XMAC_CTRL */ "", 7622 /* CLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 7623 /* CLP_XMAC_EEE_CTRL */ "", 7624 /* CLP_XMAC_EEE_TIMERS */ "", 7625 /* CLP_XMAC_FIFO_STATUS */ "", 7626 /* CLP_XMAC_GMII_EEE_CTRL */ "", 7627 /* CLP_XMAC_LH_HDR_3 */ "", 7628 /* CLP_XMAC_LLFC_CTRL */ "", 7629 /* CLP_XMAC_MODE */ "", 7630 /* CLP_XMAC_OSTS_TIMESTAMP_ADJUST */ "", 7631 /* CLP_XMAC_PAUSE_CTRL */ "", 7632 /* CLP_XMAC_PFC_CTRL */ "", 7633 /* CLP_XMAC_PFC_DA */ "", 7634 /* CLP_XMAC_PFC_OPCODE */ "", 7635 /* CLP_XMAC_PFC_TYPE */ "", 7636 /* CLP_XMAC_RX_CTRL */ "", 7637 /* CLP_XMAC_RX_LLFC_MSG_FIELDS */ "", 7638 /* CLP_XMAC_RX_LSS_CTRL */ "", 7639 /* CLP_XMAC_RX_LSS_STATUS */ "", 7640 /* CLP_XMAC_RX_MAC_SA */ "", 7641 /* CLP_XMAC_RX_MAX_SIZE */ "", 7642 /* CLP_XMAC_RX_VLAN_TAG */ "", 7643 /* CLP_XMAC_TX_CTRL */ "", 7644 /* CLP_XMAC_TX_FIFO_CREDITS */ "", 7645 /* CLP_XMAC_TX_LLFC_MSG_FIELDS */ "", 7646 /* CLP_XMAC_TX_MAC_SA */ "", 7647 /* CLP_XMAC_TX_TIMESTAMP_FIFO_DATA */ "", 7648 /* CLP_XMAC_TX_TIMESTAMP_FIFO_STATUS */ "", 7649 /* CLP_XMAC_VERSION_ID */ "", 7650 /* CMAC_CLEAR_ECC_STATUS */ "", 7651 /* CMAC_CLEAR_FIFO_STATUS */ "", 7652 /* CMAC_CLEAR_RX_LSS_STATUS */ "", 7653 /* CMAC_CTRL */ "", 7654 /* CMAC_ECC_CTRL */ "", 7655 /* CMAC_ECC_STATUS */ "", 7656 /* CMAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 7657 /* CMAC_EEE_CTRL */ "", 7658 /* CMAC_EEE_TIMERS */ "", 7659 /* CMAC_FIFO_STATUS */ "", 7660 /* CMAC_HCFC_CTRL */ "", 7661 /* CMAC_LAG_FAILOVER_STATUS */ "", 7662 /* CMAC_LLFC_CTRL */ "", 7663 /* CMAC_MACSEC_CTRL */ "", 7664 /* CMAC_MODE */ "", 7665 /* CMAC_PAUSE_CTRL */ "", 7666 /* CMAC_PFC_CTRL */ "", 7667 /* CMAC_PFC_DA */ "", 7668 /* CMAC_PFC_OPCODE */ "", 7669 /* CMAC_PFC_TYPE */ "", 7670 /* CMAC_RX_CTRL */ "", 7671 /* CMAC_RX_LLFC_MSG_FIELDS */ "", 7672 /* CMAC_RX_LSS_CTRL */ "", 7673 /* CMAC_RX_LSS_STATUS */ "", 7674 /* CMAC_RX_MAC_SA */ "", 7675 /* CMAC_RX_MAX_SIZE */ "", 7676 /* CMAC_RX_VLAN_TAG */ "", 7677 /* CMAC_SPARE0 */ "", 7678 /* CMAC_SPARE1 */ "", 7679 /* CMAC_TIMESTAMP_ADJUST */ "", 7680 /* CMAC_TX_CTRL */ "", 7681 /* CMAC_TX_FIFO_CREDITS */ "", 7682 /* CMAC_TX_LLFC_MSG_FIELDS */ "", 7683 /* CMAC_TX_MAC_SA */ "", 7684 /* CMAC_TX_MEMORY_TM_CTRL */ "", 7685 /* CMAC_TX_TIMESTAMP_FIFO_DATA */ "", 7686 /* CMAC_TX_TIMESTAMP_FIFO_STATUS */ "", 7687 /* CMAC_VERSION_ID */ "", 7688 /* CMICD_M0_IDM_IDM_INTERRUPT_STATUS */ "", 7689 /* CMICD_M0_IDM_IDM_RESET_CONTROL */ "", 7690 /* CMICD_M0_IDM_IDM_RESET_STATUS */ "", 7691 /* CMICD_M0_IDM_IO_CONTROL_DIRECT */ "", 7692 /* CMICD_M0_IDM_IO_STATUS */ "", 7693 /* CMICD_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 7694 /* CMICD_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 7695 /* CMICD_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 7696 /* CMICD_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 7697 /* CMICD_S0_IDM_IDM_ERROR_LOG_ID */ "", 7698 /* CMICD_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 7699 /* CMICD_S0_IDM_IDM_INTERRUPT_STATUS */ "", 7700 /* CMICD_S0_IDM_IDM_IO_CONTROL_DIRECT */ "", 7701 /* CMICD_S0_IDM_IDM_IO_STATUS */ "", 7702 /* CMICD_S0_IDM_IDM_RESET_CONTROL */ "", 7703 /* CMICD_S0_IDM_IDM_RESET_READ_ID */ "", 7704 /* CMICD_S0_IDM_IDM_RESET_STATUS */ "", 7705 /* CMICD_S0_IDM_IDM_RESET_WRITE_ID */ "", 7706 /* CMICMINTIMER */ "", 7707 /* CMICM_BSPI_B0_CNTRL */ "", 7708 /* CMICM_BSPI_B0_STATUS */ "", 7709 /* CMICM_BSPI_B1_CNTRL */ "", 7710 /* CMICM_BSPI_B1_STATUS */ "", 7711 /* CMICM_BSPI_BUSY_STATUS */ "", 7712 /* CMICM_BSPI_INTR_STATUS */ "", 7713 /* CMICM_BSPI_MAST_N_BOOT */ "", 7714 /* CMICM_COMMON_CONFIG */ "", 7715 /* CMICM_D0_CACHE_I_D_BANK_MEM_CONTROL */ "", 7716 /* CMICM_D0_CACHE_I_D_DIRTY_MEM_CONTROL */ "", 7717 /* CMICM_D0_CACHE_I_D_TAG_MEM_CONTROL */ "", 7718 /* CMICM_D0_ETB_MEM_CONTROL */ "", 7719 /* CMICM_D0_SRAM_MEM_CONTROL */ "", 7720 /* CMICM_D0_TCM_MEM_CONTROL */ "", 7721 /* CMICM_REVID */ "", 7722 /* CMICTXCOSMASK */ "", 7723 /* CMICX_M0_IDM_IDM_INTERRUPT_STATUS */ "", 7724 /* CMICX_M0_IDM_IDM_RESET_CONTROL */ "", 7725 /* CMICX_M0_IDM_IDM_RESET_STATUS */ "", 7726 /* CMICX_M0_IDM_IO_CONTROL_DIRECT */ "", 7727 /* CMICX_M0_IDM_IO_STATUS */ "", 7728 /* CMICX_M1_IDM_IDM_INTERRUPT_STATUS */ "", 7729 /* CMICX_M1_IDM_IDM_RESET_CONTROL */ "", 7730 /* CMICX_M1_IDM_IDM_RESET_STATUS */ "", 7731 /* CMICX_M1_IDM_IO_CONTROL_DIRECT */ "", 7732 /* CMICX_M1_IDM_IO_STATUS */ "", 7733 /* CMICX_M2_IDM_IDM_INTERRUPT_STATUS */ "", 7734 /* CMICX_M2_IDM_IDM_RESET_CONTROL */ "", 7735 /* CMICX_M2_IDM_IDM_RESET_STATUS */ "", 7736 /* CMICX_M2_IDM_IO_CONTROL_DIRECT */ "", 7737 /* CMICX_M2_IDM_IO_STATUS */ "", 7738 /* CMICX_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 7739 /* CMICX_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 7740 /* CMICX_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 7741 /* CMICX_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 7742 /* CMICX_S0_IDM_IDM_ERROR_LOG_ID */ "", 7743 /* CMICX_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 7744 /* CMICX_S0_IDM_IDM_INTERRUPT_STATUS */ "", 7745 /* CMICX_S0_IDM_IDM_IO_CONTROL_DIRECT */ "", 7746 /* CMICX_S0_IDM_IDM_IO_STATUS */ "", 7747 /* CMICX_S0_IDM_IDM_RESET_CONTROL */ "", 7748 /* CMICX_S0_IDM_IDM_RESET_READ_ID */ "", 7749 /* CMICX_S0_IDM_IDM_RESET_STATUS */ "", 7750 /* CMICX_S0_IDM_IDM_RESET_WRITE_ID */ "", 7751 /* CMIC_1000_BASE_X_MODE */ "", 7752 /* CMIC_BROADSYNC_REF_CLK_GEN_CTRL */ "", 7753 /* CMIC_BS0_CLK_CTRL */ "", 7754 /* CMIC_BS0_CONFIG */ "", 7755 /* CMIC_BS0_HEARTBEAT_CTRL */ "", 7756 /* CMIC_BS0_HEARTBEAT_DOWN_DURATION */ "", 7757 /* CMIC_BS0_HEARTBEAT_UP_DURATION */ "", 7758 /* CMIC_BS0_INITIAL_CRC */ "", 7759 /* CMIC_BS0_INPUT_TIME_0 */ "", 7760 /* CMIC_BS0_INPUT_TIME_1 */ "", 7761 /* CMIC_BS0_INPUT_TIME_2 */ "", 7762 /* CMIC_BS0_OUTPUT_TIME_0 */ "", 7763 /* CMIC_BS0_OUTPUT_TIME_1 */ "", 7764 /* CMIC_BS0_OUTPUT_TIME_2 */ "", 7765 /* CMIC_BS1_CLK_CTRL */ "", 7766 /* CMIC_BS1_CONFIG */ "", 7767 /* CMIC_BS1_HEARTBEAT_CTRL */ "", 7768 /* CMIC_BS1_HEARTBEAT_DOWN_DURATION */ "", 7769 /* CMIC_BS1_HEARTBEAT_UP_DURATION */ "", 7770 /* CMIC_BS1_INITIAL_CRC */ "", 7771 /* CMIC_BS1_INPUT_TIME_0 */ "", 7772 /* CMIC_BS1_INPUT_TIME_1 */ "", 7773 /* CMIC_BS1_INPUT_TIME_2 */ "", 7774 /* CMIC_BS1_OUTPUT_TIME_0 */ "", 7775 /* CMIC_BS1_OUTPUT_TIME_1 */ "", 7776 /* CMIC_BS1_OUTPUT_TIME_2 */ "", 7777 /* CMIC_BS_CAPTURE_CTRL */ "", 7778 /* CMIC_BS_CAPTURE_FREE_RUN_TIME_0 */ "", 7779 /* CMIC_BS_CAPTURE_FREE_RUN_TIME_1 */ "", 7780 /* CMIC_BS_CAPTURE_STATUS */ "", 7781 /* CMIC_BS_CAPTURE_SYNC_TIME_0 */ "", 7782 /* CMIC_BS_CAPTURE_SYNC_TIME_1 */ "", 7783 /* CMIC_BS_CAPTURE_SYNT_TIME_0 */ "", 7784 /* CMIC_BS_CAPTURE_SYNT_TIME_1 */ "", 7785 /* CMIC_BS_CLK_CTRL */ "", 7786 /* CMIC_BS_CLK_CTRL_0 */ "", 7787 /* CMIC_BS_CLK_CTRL_1 */ "", 7788 /* CMIC_BS_CLK_TOGGLE_TIME_0 */ "", 7789 /* CMIC_BS_CLK_TOGGLE_TIME_1 */ "", 7790 /* CMIC_BS_CLK_TOGGLE_TIME_2 */ "", 7791 /* CMIC_BS_CONFIG */ "", 7792 /* CMIC_BS_DRIFT_RATE */ "", 7793 /* CMIC_BS_HEARTBEAT_CTRL */ "", 7794 /* CMIC_BS_HEARTBEAT_DOWN_DURATION */ "", 7795 /* CMIC_BS_HEARTBEAT_UP_DURATION */ "", 7796 /* CMIC_BS_INITIAL_CRC */ "", 7797 /* CMIC_BS_INPUT_TIME_0 */ "", 7798 /* CMIC_BS_INPUT_TIME_1 */ "", 7799 /* CMIC_BS_INPUT_TIME_2 */ "", 7800 /* CMIC_BS_OFFSET_ADJUST_0 */ "", 7801 /* CMIC_BS_OFFSET_ADJUST_1 */ "", 7802 /* CMIC_BS_OUTPUT_TIME_0 */ "", 7803 /* CMIC_BS_OUTPUT_TIME_1 */ "", 7804 /* CMIC_BS_OUTPUT_TIME_2 */ "", 7805 /* CMIC_BS_REF_CLK_GEN_CTRL */ "", 7806 /* CMIC_CHIP_MODE_CONTROL */ "", 7807 /* CMIC_CHIP_PARITY_INTR_ENABLE */ "", 7808 /* CMIC_CHIP_PARITY_INTR_STATUS */ "", 7809 /* CMIC_CMC0_2BIT_ECC_ERROR_STATUS */ "", 7810 /* CMIC_CMC0_2BIT_ECC_ERROR_STATUS_MASK */ "", 7811 /* CMIC_CMC0_AXIIC_DMA_ECC_INTR */ "", 7812 /* CMIC_CMC0_AXIIC_DMA_ECC_INTR_CLR */ "", 7813 /* CMIC_CMC0_AXIIC_DMA_ECC_INTR_ENABLE */ "", 7814 /* CMIC_CMC0_AXIIC_TM_CONTROL_0 */ "", 7815 /* CMIC_CMC0_AXIIC_TM_CONTROL_1 */ "", 7816 /* CMIC_CMC0_AXIIC_TM_CONTROL_2 */ "", 7817 /* CMIC_CMC0_CCMDMA_CH0_CFG */ "", 7818 /* CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_HI */ "", 7819 /* CMIC_CMC0_CCMDMA_CH0_CUR_HOST0_ADDR_LO */ "", 7820 /* CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_HI */ "", 7821 /* CMIC_CMC0_CCMDMA_CH0_CUR_HOST1_ADDR_LO */ "", 7822 /* CMIC_CMC0_CCMDMA_CH0_ECC_CONTROL */ "", 7823 /* CMIC_CMC0_CCMDMA_CH0_ECC_STATUS */ "", 7824 /* CMIC_CMC0_CCMDMA_CH0_ECC_STATUS_CLR */ "", 7825 /* CMIC_CMC0_CCMDMA_CH0_ENTRY_COUNT */ "", 7826 /* CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI */ "", 7827 /* CMIC_CMC0_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO */ "", 7828 /* CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI */ "", 7829 /* CMIC_CMC0_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO */ "", 7830 /* CMIC_CMC0_CCMDMA_CH0_STAT */ "", 7831 /* CMIC_CMC0_CCMDMA_CH0_TM_CONTROL */ "", 7832 /* CMIC_CMC0_CCMDMA_CH1_CFG */ "", 7833 /* CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_HI */ "", 7834 /* CMIC_CMC0_CCMDMA_CH1_CUR_HOST0_ADDR_LO */ "", 7835 /* CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_HI */ "", 7836 /* CMIC_CMC0_CCMDMA_CH1_CUR_HOST1_ADDR_LO */ "", 7837 /* CMIC_CMC0_CCMDMA_CH1_ECC_CONTROL */ "", 7838 /* CMIC_CMC0_CCMDMA_CH1_ECC_STATUS */ "", 7839 /* CMIC_CMC0_CCMDMA_CH1_ECC_STATUS_CLR */ "", 7840 /* CMIC_CMC0_CCMDMA_CH1_ENTRY_COUNT */ "", 7841 /* CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI */ "", 7842 /* CMIC_CMC0_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO */ "", 7843 /* CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI */ "", 7844 /* CMIC_CMC0_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO */ "", 7845 /* CMIC_CMC0_CCMDMA_CH1_STAT */ "", 7846 /* CMIC_CMC0_CCMDMA_CH1_TM_CONTROL */ "", 7847 /* CMIC_CMC0_CCMDMA_TM_CONTROL_0 */ "", 7848 /* CMIC_CMC0_CCMDMA_TM_CONTROL_1 */ "", 7849 /* CMIC_CMC0_CCM_DMA_CFG */ "", 7850 /* CMIC_CMC0_CCM_DMA_CUR_HOST0_ADDR */ "", 7851 /* CMIC_CMC0_CCM_DMA_CUR_HOST1_ADDR */ "", 7852 /* CMIC_CMC0_CCM_DMA_ECCERR_ADDR */ "", 7853 /* CMIC_CMC0_CCM_DMA_ECCERR_CONTROL */ "", 7854 /* CMIC_CMC0_CCM_DMA_ENTRY_COUNT */ "", 7855 /* CMIC_CMC0_CCM_DMA_HOST0_MEM_START_ADDR */ "", 7856 /* CMIC_CMC0_CCM_DMA_HOST1_MEM_START_ADDR */ "", 7857 /* CMIC_CMC0_CCM_DMA_STAT */ "", 7858 /* CMIC_CMC0_CCM_DMA_STATUS_CLR */ "", 7859 /* CMIC_CMC0_CH0_COS_CTRL_RX_0 */ "", 7860 /* CMIC_CMC0_CH0_COS_CTRL_RX_1 */ "", 7861 /* CMIC_CMC0_CH0_DMA_CTRL */ "", 7862 /* CMIC_CMC0_CH0_DMA_CURR_DESC */ "", 7863 /* CMIC_CMC0_CH0_RXBUF_THRESHOLD_CONFIG */ "", 7864 /* CMIC_CMC0_CH1_COS_CTRL_RX_0 */ "", 7865 /* CMIC_CMC0_CH1_COS_CTRL_RX_1 */ "", 7866 /* CMIC_CMC0_CH1_DMA_CTRL */ "", 7867 /* CMIC_CMC0_CH1_DMA_CURR_DESC */ "", 7868 /* CMIC_CMC0_CH1_RXBUF_THRESHOLD_CONFIG */ "", 7869 /* CMIC_CMC0_CH2_COS_CTRL_RX_0 */ "", 7870 /* CMIC_CMC0_CH2_COS_CTRL_RX_1 */ "", 7871 /* CMIC_CMC0_CH2_DMA_CTRL */ "", 7872 /* CMIC_CMC0_CH2_DMA_CURR_DESC */ "", 7873 /* CMIC_CMC0_CH2_RXBUF_THRESHOLD_CONFIG */ "", 7874 /* CMIC_CMC0_CH3_COS_CTRL_RX_0 */ "", 7875 /* CMIC_CMC0_CH3_COS_CTRL_RX_1 */ "", 7876 /* CMIC_CMC0_CH3_DMA_CTRL */ "", 7877 /* CMIC_CMC0_CH3_DMA_CURR_DESC */ "", 7878 /* CMIC_CMC0_CH3_RXBUF_THRESHOLD_CONFIG */ "", 7879 /* CMIC_CMC0_CONFIG */ "", 7880 /* CMIC_CMC0_DMA_CH0_DESC_HALT_ADDR */ "", 7881 /* CMIC_CMC0_DMA_CH0_INTR_COAL */ "", 7882 /* CMIC_CMC0_DMA_CH1_DESC_HALT_ADDR */ "", 7883 /* CMIC_CMC0_DMA_CH1_INTR_COAL */ "", 7884 /* CMIC_CMC0_DMA_CH2_DESC_HALT_ADDR */ "", 7885 /* CMIC_CMC0_DMA_CH2_INTR_COAL */ "", 7886 /* CMIC_CMC0_DMA_CH3_DESC_HALT_ADDR */ "", 7887 /* CMIC_CMC0_DMA_CH3_INTR_COAL */ "", 7888 /* CMIC_CMC0_DMA_DESC0 */ "", 7889 /* CMIC_CMC0_DMA_DESC1 */ "", 7890 /* CMIC_CMC0_DMA_DESC2 */ "", 7891 /* CMIC_CMC0_DMA_DESC3 */ "", 7892 /* CMIC_CMC0_DMA_STAT */ "", 7893 /* CMIC_CMC0_DMA_STAT_CLR */ "", 7894 /* CMIC_CMC0_DMA_STAT_HI */ "", 7895 /* CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_0 */ "", 7896 /* CMIC_CMC0_FIFORDDMA_CH0_TM_CONTROL_1 */ "", 7897 /* CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_0 */ "", 7898 /* CMIC_CMC0_FIFORDDMA_CH1_TM_CONTROL_1 */ "", 7899 /* CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_0 */ "", 7900 /* CMIC_CMC0_FIFORDDMA_CH2_TM_CONTROL_1 */ "", 7901 /* CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_0 */ "", 7902 /* CMIC_CMC0_FIFORDDMA_CH3_TM_CONTROL_1 */ "", 7903 /* CMIC_CMC0_FIFO_CH0_RD_DMA_CFG */ "", 7904 /* CMIC_CMC0_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 7905 /* CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_ADDRESS */ "", 7906 /* CMIC_CMC0_FIFO_CH0_RD_DMA_ECCERR_CONTROL */ "", 7907 /* CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR */ "", 7908 /* CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS */ "", 7909 /* CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD */ "", 7910 /* CMIC_CMC0_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR */ "", 7911 /* CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 7912 /* CMIC_CMC0_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 7913 /* CMIC_CMC0_FIFO_CH0_RD_DMA_OPCODE */ "", 7914 /* CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG */ "", 7915 /* CMIC_CMC0_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS */ "", 7916 /* CMIC_CMC0_FIFO_CH0_RD_DMA_STAT */ "", 7917 /* CMIC_CMC0_FIFO_CH0_RD_DMA_STAT_CLR */ "", 7918 /* CMIC_CMC0_FIFO_CH1_RD_DMA_CFG */ "", 7919 /* CMIC_CMC0_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 7920 /* CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_ADDRESS */ "", 7921 /* CMIC_CMC0_FIFO_CH1_RD_DMA_ECCERR_CONTROL */ "", 7922 /* CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR */ "", 7923 /* CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS */ "", 7924 /* CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD */ "", 7925 /* CMIC_CMC0_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR */ "", 7926 /* CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 7927 /* CMIC_CMC0_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 7928 /* CMIC_CMC0_FIFO_CH1_RD_DMA_OPCODE */ "", 7929 /* CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG */ "", 7930 /* CMIC_CMC0_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS */ "", 7931 /* CMIC_CMC0_FIFO_CH1_RD_DMA_STAT */ "", 7932 /* CMIC_CMC0_FIFO_CH1_RD_DMA_STAT_CLR */ "", 7933 /* CMIC_CMC0_FIFO_CH2_RD_DMA_CFG */ "", 7934 /* CMIC_CMC0_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 7935 /* CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_ADDRESS */ "", 7936 /* CMIC_CMC0_FIFO_CH2_RD_DMA_ECCERR_CONTROL */ "", 7937 /* CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR */ "", 7938 /* CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS */ "", 7939 /* CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD */ "", 7940 /* CMIC_CMC0_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR */ "", 7941 /* CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 7942 /* CMIC_CMC0_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 7943 /* CMIC_CMC0_FIFO_CH2_RD_DMA_OPCODE */ "", 7944 /* CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG */ "", 7945 /* CMIC_CMC0_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS */ "", 7946 /* CMIC_CMC0_FIFO_CH2_RD_DMA_STAT */ "", 7947 /* CMIC_CMC0_FIFO_CH2_RD_DMA_STAT_CLR */ "", 7948 /* CMIC_CMC0_FIFO_CH3_RD_DMA_CFG */ "", 7949 /* CMIC_CMC0_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 7950 /* CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_ADDRESS */ "", 7951 /* CMIC_CMC0_FIFO_CH3_RD_DMA_ECCERR_CONTROL */ "", 7952 /* CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR */ "", 7953 /* CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS */ "", 7954 /* CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD */ "", 7955 /* CMIC_CMC0_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR */ "", 7956 /* CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 7957 /* CMIC_CMC0_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 7958 /* CMIC_CMC0_FIFO_CH3_RD_DMA_OPCODE */ "", 7959 /* CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG */ "", 7960 /* CMIC_CMC0_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS */ "", 7961 /* CMIC_CMC0_FIFO_CH3_RD_DMA_STAT */ "", 7962 /* CMIC_CMC0_FIFO_CH3_RD_DMA_STAT_CLR */ "", 7963 /* CMIC_CMC0_FIFO_RD_DMA_DEBUG */ "", 7964 /* CMIC_CMC0_FSCHAN_ADDRESS */ "", 7965 /* CMIC_CMC0_FSCHAN_DATA32 */ "", 7966 /* CMIC_CMC0_FSCHAN_DATA64_HI */ "", 7967 /* CMIC_CMC0_FSCHAN_DATA64_LO */ "", 7968 /* CMIC_CMC0_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE */ "", 7969 /* CMIC_CMC0_FSCHAN_OPCODE */ "", 7970 /* CMIC_CMC0_FSCHAN_STATUS */ "", 7971 /* CMIC_CMC0_HOSTMEM_ADDR_REMAP_0 */ "", 7972 /* CMIC_CMC0_HOSTMEM_ADDR_REMAP_1 */ "", 7973 /* CMIC_CMC0_HOSTMEM_ADDR_REMAP_2 */ "", 7974 /* CMIC_CMC0_HOSTMEM_ADDR_REMAP_3 */ "", 7975 /* CMIC_CMC0_IRQ_STAT0 */ "", 7976 /* CMIC_CMC0_IRQ_STAT1 */ "", 7977 /* CMIC_CMC0_IRQ_STAT2 */ "", 7978 /* CMIC_CMC0_IRQ_STAT3 */ "", 7979 /* CMIC_CMC0_IRQ_STAT4 */ "", 7980 /* CMIC_CMC0_IRQ_STAT5 */ "", 7981 /* CMIC_CMC0_IRQ_STAT6 */ "", 7982 /* CMIC_CMC0_MIIM_ADDRESS */ "", 7983 /* CMIC_CMC0_MIIM_CTRL */ "", 7984 /* CMIC_CMC0_MIIM_PARAM */ "", 7985 /* CMIC_CMC0_MIIM_READ_DATA */ "", 7986 /* CMIC_CMC0_MIIM_STAT */ "", 7987 /* CMIC_CMC0_PCIE_IRQ_MASK0 */ "", 7988 /* CMIC_CMC0_PCIE_IRQ_MASK1 */ "", 7989 /* CMIC_CMC0_PCIE_IRQ_MASK2 */ "", 7990 /* CMIC_CMC0_PCIE_IRQ_MASK3 */ "", 7991 /* CMIC_CMC0_PCIE_IRQ_MASK4 */ "", 7992 /* CMIC_CMC0_PCIE_IRQ_MASK5 */ "", 7993 /* CMIC_CMC0_PCIE_IRQ_MASK6 */ "", 7994 /* CMIC_CMC0_PCIE_MISCEL */ "", 7995 /* CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_0 */ "", 7996 /* CMIC_CMC0_PKTDMA_CH0_COS_CTRL_RX_1 */ "", 7997 /* CMIC_CMC0_PKTDMA_CH0_CTRL */ "", 7998 /* CMIC_CMC0_PKTDMA_CH0_CURR_DESC_HI */ "", 7999 /* CMIC_CMC0_PKTDMA_CH0_CURR_DESC_LO */ "", 8000 /* CMIC_CMC0_PKTDMA_CH0_DEBUG_CONTROL */ "", 8001 /* CMIC_CMC0_PKTDMA_CH0_DEBUG_SM_STATUS */ "", 8002 /* CMIC_CMC0_PKTDMA_CH0_DEBUG_STATUS */ "", 8003 /* CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_HI */ "", 8004 /* CMIC_CMC0_PKTDMA_CH0_DESC_ADDR_LO */ "", 8005 /* CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_REQ */ "", 8006 /* CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_RX */ "", 8007 /* CMIC_CMC0_PKTDMA_CH0_DESC_COUNT_STATUS_WR */ "", 8008 /* CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_HI */ "", 8009 /* CMIC_CMC0_PKTDMA_CH0_DESC_HALT_ADDR_LO */ "", 8010 /* CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_CONTROL */ "", 8011 /* CMIC_CMC0_PKTDMA_CH0_DESC_MEM_ECC_STATUS */ "", 8012 /* CMIC_CMC0_PKTDMA_CH0_DESC_MEM_TM_CONTROL */ "", 8013 /* CMIC_CMC0_PKTDMA_CH0_INTR_COAL */ "", 8014 /* CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT */ "", 8015 /* CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP */ "", 8016 /* CMIC_CMC0_PKTDMA_CH0_PKT_COUNT_TXPKT */ "", 8017 /* CMIC_CMC0_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG */ "", 8018 /* CMIC_CMC0_PKTDMA_CH0_STAT */ "", 8019 /* CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_0 */ "", 8020 /* CMIC_CMC0_PKTDMA_CH1_COS_CTRL_RX_1 */ "", 8021 /* CMIC_CMC0_PKTDMA_CH1_CTRL */ "", 8022 /* CMIC_CMC0_PKTDMA_CH1_CURR_DESC_HI */ "", 8023 /* CMIC_CMC0_PKTDMA_CH1_CURR_DESC_LO */ "", 8024 /* CMIC_CMC0_PKTDMA_CH1_DEBUG_CONTROL */ "", 8025 /* CMIC_CMC0_PKTDMA_CH1_DEBUG_SM_STATUS */ "", 8026 /* CMIC_CMC0_PKTDMA_CH1_DEBUG_STATUS */ "", 8027 /* CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_HI */ "", 8028 /* CMIC_CMC0_PKTDMA_CH1_DESC_ADDR_LO */ "", 8029 /* CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_REQ */ "", 8030 /* CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_RX */ "", 8031 /* CMIC_CMC0_PKTDMA_CH1_DESC_COUNT_STATUS_WR */ "", 8032 /* CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_HI */ "", 8033 /* CMIC_CMC0_PKTDMA_CH1_DESC_HALT_ADDR_LO */ "", 8034 /* CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_CONTROL */ "", 8035 /* CMIC_CMC0_PKTDMA_CH1_DESC_MEM_ECC_STATUS */ "", 8036 /* CMIC_CMC0_PKTDMA_CH1_DESC_MEM_TM_CONTROL */ "", 8037 /* CMIC_CMC0_PKTDMA_CH1_INTR_COAL */ "", 8038 /* CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT */ "", 8039 /* CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP */ "", 8040 /* CMIC_CMC0_PKTDMA_CH1_PKT_COUNT_TXPKT */ "", 8041 /* CMIC_CMC0_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG */ "", 8042 /* CMIC_CMC0_PKTDMA_CH1_STAT */ "", 8043 /* CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_0 */ "", 8044 /* CMIC_CMC0_PKTDMA_CH2_COS_CTRL_RX_1 */ "", 8045 /* CMIC_CMC0_PKTDMA_CH2_CTRL */ "", 8046 /* CMIC_CMC0_PKTDMA_CH2_CURR_DESC_HI */ "", 8047 /* CMIC_CMC0_PKTDMA_CH2_CURR_DESC_LO */ "", 8048 /* CMIC_CMC0_PKTDMA_CH2_DEBUG_CONTROL */ "", 8049 /* CMIC_CMC0_PKTDMA_CH2_DEBUG_SM_STATUS */ "", 8050 /* CMIC_CMC0_PKTDMA_CH2_DEBUG_STATUS */ "", 8051 /* CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_HI */ "", 8052 /* CMIC_CMC0_PKTDMA_CH2_DESC_ADDR_LO */ "", 8053 /* CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_REQ */ "", 8054 /* CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_RX */ "", 8055 /* CMIC_CMC0_PKTDMA_CH2_DESC_COUNT_STATUS_WR */ "", 8056 /* CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_HI */ "", 8057 /* CMIC_CMC0_PKTDMA_CH2_DESC_HALT_ADDR_LO */ "", 8058 /* CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_CONTROL */ "", 8059 /* CMIC_CMC0_PKTDMA_CH2_DESC_MEM_ECC_STATUS */ "", 8060 /* CMIC_CMC0_PKTDMA_CH2_DESC_MEM_TM_CONTROL */ "", 8061 /* CMIC_CMC0_PKTDMA_CH2_INTR_COAL */ "", 8062 /* CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT */ "", 8063 /* CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP */ "", 8064 /* CMIC_CMC0_PKTDMA_CH2_PKT_COUNT_TXPKT */ "", 8065 /* CMIC_CMC0_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG */ "", 8066 /* CMIC_CMC0_PKTDMA_CH2_STAT */ "", 8067 /* CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_0 */ "", 8068 /* CMIC_CMC0_PKTDMA_CH3_COS_CTRL_RX_1 */ "", 8069 /* CMIC_CMC0_PKTDMA_CH3_CTRL */ "", 8070 /* CMIC_CMC0_PKTDMA_CH3_CURR_DESC_HI */ "", 8071 /* CMIC_CMC0_PKTDMA_CH3_CURR_DESC_LO */ "", 8072 /* CMIC_CMC0_PKTDMA_CH3_DEBUG_CONTROL */ "", 8073 /* CMIC_CMC0_PKTDMA_CH3_DEBUG_SM_STATUS */ "", 8074 /* CMIC_CMC0_PKTDMA_CH3_DEBUG_STATUS */ "", 8075 /* CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_HI */ "", 8076 /* CMIC_CMC0_PKTDMA_CH3_DESC_ADDR_LO */ "", 8077 /* CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_REQ */ "", 8078 /* CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_RX */ "", 8079 /* CMIC_CMC0_PKTDMA_CH3_DESC_COUNT_STATUS_WR */ "", 8080 /* CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_HI */ "", 8081 /* CMIC_CMC0_PKTDMA_CH3_DESC_HALT_ADDR_LO */ "", 8082 /* CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_CONTROL */ "", 8083 /* CMIC_CMC0_PKTDMA_CH3_DESC_MEM_ECC_STATUS */ "", 8084 /* CMIC_CMC0_PKTDMA_CH3_DESC_MEM_TM_CONTROL */ "", 8085 /* CMIC_CMC0_PKTDMA_CH3_INTR_COAL */ "", 8086 /* CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT */ "", 8087 /* CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP */ "", 8088 /* CMIC_CMC0_PKTDMA_CH3_PKT_COUNT_TXPKT */ "", 8089 /* CMIC_CMC0_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG */ "", 8090 /* CMIC_CMC0_PKTDMA_CH3_STAT */ "", 8091 /* CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_0 */ "", 8092 /* CMIC_CMC0_PKTDMA_CH4_COS_CTRL_RX_1 */ "", 8093 /* CMIC_CMC0_PKTDMA_CH4_CTRL */ "", 8094 /* CMIC_CMC0_PKTDMA_CH4_CURR_DESC_HI */ "", 8095 /* CMIC_CMC0_PKTDMA_CH4_CURR_DESC_LO */ "", 8096 /* CMIC_CMC0_PKTDMA_CH4_DEBUG_CONTROL */ "", 8097 /* CMIC_CMC0_PKTDMA_CH4_DEBUG_SM_STATUS */ "", 8098 /* CMIC_CMC0_PKTDMA_CH4_DEBUG_STATUS */ "", 8099 /* CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_HI */ "", 8100 /* CMIC_CMC0_PKTDMA_CH4_DESC_ADDR_LO */ "", 8101 /* CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_REQ */ "", 8102 /* CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_RX */ "", 8103 /* CMIC_CMC0_PKTDMA_CH4_DESC_COUNT_STATUS_WR */ "", 8104 /* CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_HI */ "", 8105 /* CMIC_CMC0_PKTDMA_CH4_DESC_HALT_ADDR_LO */ "", 8106 /* CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_CONTROL */ "", 8107 /* CMIC_CMC0_PKTDMA_CH4_DESC_MEM_ECC_STATUS */ "", 8108 /* CMIC_CMC0_PKTDMA_CH4_DESC_MEM_TM_CONTROL */ "", 8109 /* CMIC_CMC0_PKTDMA_CH4_INTR_COAL */ "", 8110 /* CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT */ "", 8111 /* CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP */ "", 8112 /* CMIC_CMC0_PKTDMA_CH4_PKT_COUNT_TXPKT */ "", 8113 /* CMIC_CMC0_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG */ "", 8114 /* CMIC_CMC0_PKTDMA_CH4_STAT */ "", 8115 /* CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_0 */ "", 8116 /* CMIC_CMC0_PKTDMA_CH5_COS_CTRL_RX_1 */ "", 8117 /* CMIC_CMC0_PKTDMA_CH5_CTRL */ "", 8118 /* CMIC_CMC0_PKTDMA_CH5_CURR_DESC_HI */ "", 8119 /* CMIC_CMC0_PKTDMA_CH5_CURR_DESC_LO */ "", 8120 /* CMIC_CMC0_PKTDMA_CH5_DEBUG_CONTROL */ "", 8121 /* CMIC_CMC0_PKTDMA_CH5_DEBUG_SM_STATUS */ "", 8122 /* CMIC_CMC0_PKTDMA_CH5_DEBUG_STATUS */ "", 8123 /* CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_HI */ "", 8124 /* CMIC_CMC0_PKTDMA_CH5_DESC_ADDR_LO */ "", 8125 /* CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_REQ */ "", 8126 /* CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_RX */ "", 8127 /* CMIC_CMC0_PKTDMA_CH5_DESC_COUNT_STATUS_WR */ "", 8128 /* CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_HI */ "", 8129 /* CMIC_CMC0_PKTDMA_CH5_DESC_HALT_ADDR_LO */ "", 8130 /* CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_CONTROL */ "", 8131 /* CMIC_CMC0_PKTDMA_CH5_DESC_MEM_ECC_STATUS */ "", 8132 /* CMIC_CMC0_PKTDMA_CH5_DESC_MEM_TM_CONTROL */ "", 8133 /* CMIC_CMC0_PKTDMA_CH5_INTR_COAL */ "", 8134 /* CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT */ "", 8135 /* CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP */ "", 8136 /* CMIC_CMC0_PKTDMA_CH5_PKT_COUNT_TXPKT */ "", 8137 /* CMIC_CMC0_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG */ "", 8138 /* CMIC_CMC0_PKTDMA_CH5_STAT */ "", 8139 /* CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_0 */ "", 8140 /* CMIC_CMC0_PKTDMA_CH6_COS_CTRL_RX_1 */ "", 8141 /* CMIC_CMC0_PKTDMA_CH6_CTRL */ "", 8142 /* CMIC_CMC0_PKTDMA_CH6_CURR_DESC_HI */ "", 8143 /* CMIC_CMC0_PKTDMA_CH6_CURR_DESC_LO */ "", 8144 /* CMIC_CMC0_PKTDMA_CH6_DEBUG_CONTROL */ "", 8145 /* CMIC_CMC0_PKTDMA_CH6_DEBUG_SM_STATUS */ "", 8146 /* CMIC_CMC0_PKTDMA_CH6_DEBUG_STATUS */ "", 8147 /* CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_HI */ "", 8148 /* CMIC_CMC0_PKTDMA_CH6_DESC_ADDR_LO */ "", 8149 /* CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_REQ */ "", 8150 /* CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_RX */ "", 8151 /* CMIC_CMC0_PKTDMA_CH6_DESC_COUNT_STATUS_WR */ "", 8152 /* CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_HI */ "", 8153 /* CMIC_CMC0_PKTDMA_CH6_DESC_HALT_ADDR_LO */ "", 8154 /* CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_CONTROL */ "", 8155 /* CMIC_CMC0_PKTDMA_CH6_DESC_MEM_ECC_STATUS */ "", 8156 /* CMIC_CMC0_PKTDMA_CH6_DESC_MEM_TM_CONTROL */ "", 8157 /* CMIC_CMC0_PKTDMA_CH6_INTR_COAL */ "", 8158 /* CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT */ "", 8159 /* CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP */ "", 8160 /* CMIC_CMC0_PKTDMA_CH6_PKT_COUNT_TXPKT */ "", 8161 /* CMIC_CMC0_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG */ "", 8162 /* CMIC_CMC0_PKTDMA_CH6_STAT */ "", 8163 /* CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_0 */ "", 8164 /* CMIC_CMC0_PKTDMA_CH7_COS_CTRL_RX_1 */ "", 8165 /* CMIC_CMC0_PKTDMA_CH7_CTRL */ "", 8166 /* CMIC_CMC0_PKTDMA_CH7_CURR_DESC_HI */ "", 8167 /* CMIC_CMC0_PKTDMA_CH7_CURR_DESC_LO */ "", 8168 /* CMIC_CMC0_PKTDMA_CH7_DEBUG_CONTROL */ "", 8169 /* CMIC_CMC0_PKTDMA_CH7_DEBUG_SM_STATUS */ "", 8170 /* CMIC_CMC0_PKTDMA_CH7_DEBUG_STATUS */ "", 8171 /* CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_HI */ "", 8172 /* CMIC_CMC0_PKTDMA_CH7_DESC_ADDR_LO */ "", 8173 /* CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_REQ */ "", 8174 /* CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_RX */ "", 8175 /* CMIC_CMC0_PKTDMA_CH7_DESC_COUNT_STATUS_WR */ "", 8176 /* CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_HI */ "", 8177 /* CMIC_CMC0_PKTDMA_CH7_DESC_HALT_ADDR_LO */ "", 8178 /* CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_CONTROL */ "", 8179 /* CMIC_CMC0_PKTDMA_CH7_DESC_MEM_ECC_STATUS */ "", 8180 /* CMIC_CMC0_PKTDMA_CH7_DESC_MEM_TM_CONTROL */ "", 8181 /* CMIC_CMC0_PKTDMA_CH7_INTR_COAL */ "", 8182 /* CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT */ "", 8183 /* CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP */ "", 8184 /* CMIC_CMC0_PKTDMA_CH7_PKT_COUNT_TXPKT */ "", 8185 /* CMIC_CMC0_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG */ "", 8186 /* CMIC_CMC0_PKTDMA_CH7_STAT */ "", 8187 /* CMIC_CMC0_PKT_COUNT_CH0_RXPKT */ "", 8188 /* CMIC_CMC0_PKT_COUNT_CH0_TXPKT */ "", 8189 /* CMIC_CMC0_PKT_COUNT_CH1_RXPKT */ "", 8190 /* CMIC_CMC0_PKT_COUNT_CH1_TXPKT */ "", 8191 /* CMIC_CMC0_PKT_COUNT_CH2_RXPKT */ "", 8192 /* CMIC_CMC0_PKT_COUNT_CH2_TXPKT */ "", 8193 /* CMIC_CMC0_PKT_COUNT_CH3_RXPKT */ "", 8194 /* CMIC_CMC0_PKT_COUNT_CH3_TXPKT */ "", 8195 /* CMIC_CMC0_PKT_COUNT_RXPKT */ "", 8196 /* CMIC_CMC0_PKT_COUNT_TXPKT */ "", 8197 /* CMIC_CMC0_PROGRAMMABLE_COS_MASK0 */ "", 8198 /* CMIC_CMC0_PROGRAMMABLE_COS_MASK1 */ "", 8199 /* CMIC_CMC0_RCPU_IRQ_MASK0 */ "", 8200 /* CMIC_CMC0_RXBUF_THRESHOLD_CONFIG */ "", 8201 /* CMIC_CMC0_SBUSDMA_CH0_CONTROL */ "", 8202 /* CMIC_CMC0_SBUSDMA_CH0_COUNT */ "", 8203 /* CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS */ "", 8204 /* CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI */ "", 8205 /* CMIC_CMC0_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO */ "", 8206 /* CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS */ "", 8207 /* CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI */ "", 8208 /* CMIC_CMC0_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO */ "", 8209 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT */ "", 8210 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 8211 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 8212 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 8213 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE */ "", 8214 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST */ "", 8215 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 8216 /* CMIC_CMC0_SBUSDMA_CH0_CUR_SBUS_ADDRESS */ "", 8217 /* CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS */ "", 8218 /* CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_HI */ "", 8219 /* CMIC_CMC0_SBUSDMA_CH0_DESC_START_ADDRESS_LO */ "", 8220 /* CMIC_CMC0_SBUSDMA_CH0_ECC_CONTROL */ "", 8221 /* CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS */ "", 8222 /* CMIC_CMC0_SBUSDMA_CH0_ECC_STATUS_CLR */ "", 8223 /* CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS */ "", 8224 /* CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI */ "", 8225 /* CMIC_CMC0_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO */ "", 8226 /* CMIC_CMC0_SBUSDMA_CH0_ITER_COUNT */ "", 8227 /* CMIC_CMC0_SBUSDMA_CH0_OPCODE */ "", 8228 /* CMIC_CMC0_SBUSDMA_CH0_REQUEST */ "", 8229 /* CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG */ "", 8230 /* CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR */ "", 8231 /* CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS */ "", 8232 /* CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI */ "", 8233 /* CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO */ "", 8234 /* CMIC_CMC0_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL */ "", 8235 /* CMIC_CMC0_SBUSDMA_CH0_SBUS_START_ADDRESS */ "", 8236 /* CMIC_CMC0_SBUSDMA_CH0_STATUS */ "", 8237 /* CMIC_CMC0_SBUSDMA_CH0_TIMER */ "", 8238 /* CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL */ "", 8239 /* CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_0 */ "", 8240 /* CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_1 */ "", 8241 /* CMIC_CMC0_SBUSDMA_CH0_TM_CONTROL_2 */ "", 8242 /* CMIC_CMC0_SBUSDMA_CH1_CONTROL */ "", 8243 /* CMIC_CMC0_SBUSDMA_CH1_COUNT */ "", 8244 /* CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS */ "", 8245 /* CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI */ "", 8246 /* CMIC_CMC0_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO */ "", 8247 /* CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS */ "", 8248 /* CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI */ "", 8249 /* CMIC_CMC0_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO */ "", 8250 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT */ "", 8251 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 8252 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 8253 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 8254 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE */ "", 8255 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST */ "", 8256 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 8257 /* CMIC_CMC0_SBUSDMA_CH1_CUR_SBUS_ADDRESS */ "", 8258 /* CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS */ "", 8259 /* CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_HI */ "", 8260 /* CMIC_CMC0_SBUSDMA_CH1_DESC_START_ADDRESS_LO */ "", 8261 /* CMIC_CMC0_SBUSDMA_CH1_ECC_CONTROL */ "", 8262 /* CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS */ "", 8263 /* CMIC_CMC0_SBUSDMA_CH1_ECC_STATUS_CLR */ "", 8264 /* CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS */ "", 8265 /* CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI */ "", 8266 /* CMIC_CMC0_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO */ "", 8267 /* CMIC_CMC0_SBUSDMA_CH1_ITER_COUNT */ "", 8268 /* CMIC_CMC0_SBUSDMA_CH1_OPCODE */ "", 8269 /* CMIC_CMC0_SBUSDMA_CH1_REQUEST */ "", 8270 /* CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG */ "", 8271 /* CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR */ "", 8272 /* CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS */ "", 8273 /* CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI */ "", 8274 /* CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO */ "", 8275 /* CMIC_CMC0_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL */ "", 8276 /* CMIC_CMC0_SBUSDMA_CH1_SBUS_START_ADDRESS */ "", 8277 /* CMIC_CMC0_SBUSDMA_CH1_STATUS */ "", 8278 /* CMIC_CMC0_SBUSDMA_CH1_TIMER */ "", 8279 /* CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL */ "", 8280 /* CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_0 */ "", 8281 /* CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_1 */ "", 8282 /* CMIC_CMC0_SBUSDMA_CH1_TM_CONTROL_2 */ "", 8283 /* CMIC_CMC0_SBUSDMA_CH2_CONTROL */ "", 8284 /* CMIC_CMC0_SBUSDMA_CH2_COUNT */ "", 8285 /* CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS */ "", 8286 /* CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI */ "", 8287 /* CMIC_CMC0_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO */ "", 8288 /* CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS */ "", 8289 /* CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI */ "", 8290 /* CMIC_CMC0_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO */ "", 8291 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT */ "", 8292 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 8293 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 8294 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 8295 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE */ "", 8296 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST */ "", 8297 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 8298 /* CMIC_CMC0_SBUSDMA_CH2_CUR_SBUS_ADDRESS */ "", 8299 /* CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS */ "", 8300 /* CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_HI */ "", 8301 /* CMIC_CMC0_SBUSDMA_CH2_DESC_START_ADDRESS_LO */ "", 8302 /* CMIC_CMC0_SBUSDMA_CH2_ECC_CONTROL */ "", 8303 /* CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS */ "", 8304 /* CMIC_CMC0_SBUSDMA_CH2_ECC_STATUS_CLR */ "", 8305 /* CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS */ "", 8306 /* CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI */ "", 8307 /* CMIC_CMC0_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO */ "", 8308 /* CMIC_CMC0_SBUSDMA_CH2_ITER_COUNT */ "", 8309 /* CMIC_CMC0_SBUSDMA_CH2_OPCODE */ "", 8310 /* CMIC_CMC0_SBUSDMA_CH2_REQUEST */ "", 8311 /* CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG */ "", 8312 /* CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR */ "", 8313 /* CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS */ "", 8314 /* CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI */ "", 8315 /* CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO */ "", 8316 /* CMIC_CMC0_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL */ "", 8317 /* CMIC_CMC0_SBUSDMA_CH2_SBUS_START_ADDRESS */ "", 8318 /* CMIC_CMC0_SBUSDMA_CH2_STATUS */ "", 8319 /* CMIC_CMC0_SBUSDMA_CH2_TIMER */ "", 8320 /* CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL */ "", 8321 /* CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_0 */ "", 8322 /* CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_1 */ "", 8323 /* CMIC_CMC0_SBUSDMA_CH2_TM_CONTROL_2 */ "", 8324 /* CMIC_CMC0_SBUSDMA_CH3_CONTROL */ "", 8325 /* CMIC_CMC0_SBUSDMA_CH3_COUNT */ "", 8326 /* CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI */ "", 8327 /* CMIC_CMC0_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO */ "", 8328 /* CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI */ "", 8329 /* CMIC_CMC0_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO */ "", 8330 /* CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT */ "", 8331 /* CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 8332 /* CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 8333 /* CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE */ "", 8334 /* CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST */ "", 8335 /* CMIC_CMC0_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 8336 /* CMIC_CMC0_SBUSDMA_CH3_CUR_SBUS_ADDRESS */ "", 8337 /* CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_HI */ "", 8338 /* CMIC_CMC0_SBUSDMA_CH3_DESC_START_ADDRESS_LO */ "", 8339 /* CMIC_CMC0_SBUSDMA_CH3_ECC_CONTROL */ "", 8340 /* CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS */ "", 8341 /* CMIC_CMC0_SBUSDMA_CH3_ECC_STATUS_CLR */ "", 8342 /* CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI */ "", 8343 /* CMIC_CMC0_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO */ "", 8344 /* CMIC_CMC0_SBUSDMA_CH3_ITER_COUNT */ "", 8345 /* CMIC_CMC0_SBUSDMA_CH3_OPCODE */ "", 8346 /* CMIC_CMC0_SBUSDMA_CH3_REQUEST */ "", 8347 /* CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG */ "", 8348 /* CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR */ "", 8349 /* CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI */ "", 8350 /* CMIC_CMC0_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO */ "", 8351 /* CMIC_CMC0_SBUSDMA_CH3_SBUS_START_ADDRESS */ "", 8352 /* CMIC_CMC0_SBUSDMA_CH3_STATUS */ "", 8353 /* CMIC_CMC0_SBUSDMA_CH3_TIMER */ "", 8354 /* CMIC_CMC0_SBUSDMA_CH3_TM_CONTROL */ "", 8355 /* CMIC_CMC0_SCHAN_ACK_DATA_BEAT_COUNT */ "", 8356 /* CMIC_CMC0_SCHAN_CTRL */ "", 8357 /* CMIC_CMC0_SCHAN_ERR */ "", 8358 /* CMIC_CMC0_SCHAN_MESSAGE */ "", 8359 /* CMIC_CMC0_SCHAN_MESSAGE0 */ "", 8360 /* CMIC_CMC0_SCHAN_MESSAGE1 */ "", 8361 /* CMIC_CMC0_SCHAN_MESSAGE2 */ "", 8362 /* CMIC_CMC0_SCHAN_MESSAGE3 */ "", 8363 /* CMIC_CMC0_SCHAN_MESSAGE4 */ "", 8364 /* CMIC_CMC0_SCHAN_MESSAGE5 */ "", 8365 /* CMIC_CMC0_SCHAN_MESSAGE6 */ "", 8366 /* CMIC_CMC0_SCHAN_MESSAGE7 */ "", 8367 /* CMIC_CMC0_SCHAN_MESSAGE8 */ "", 8368 /* CMIC_CMC0_SCHAN_MESSAGE9 */ "", 8369 /* CMIC_CMC0_SCHAN_MESSAGE10 */ "", 8370 /* CMIC_CMC0_SCHAN_MESSAGE11 */ "", 8371 /* CMIC_CMC0_SCHAN_MESSAGE12 */ "", 8372 /* CMIC_CMC0_SCHAN_MESSAGE13 */ "", 8373 /* CMIC_CMC0_SCHAN_MESSAGE14 */ "", 8374 /* CMIC_CMC0_SCHAN_MESSAGE15 */ "", 8375 /* CMIC_CMC0_SCHAN_MESSAGE16 */ "", 8376 /* CMIC_CMC0_SCHAN_MESSAGE17 */ "", 8377 /* CMIC_CMC0_SCHAN_MESSAGE18 */ "", 8378 /* CMIC_CMC0_SCHAN_MESSAGE19 */ "", 8379 /* CMIC_CMC0_SCHAN_MESSAGE20 */ "", 8380 /* CMIC_CMC0_SCHAN_MESSAGE21 */ "", 8381 /* CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS */ "", 8382 /* CMIC_CMC0_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE */ "", 8383 /* CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS */ "", 8384 /* CMIC_CMC0_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE */ "", 8385 /* CMIC_CMC0_SHARED_AXI_AR_COUNT_SPLIT_TX */ "", 8386 /* CMIC_CMC0_SHARED_AXI_AR_COUNT_TX */ "", 8387 /* CMIC_CMC0_SHARED_AXI_PER_ID_STAT */ "", 8388 /* CMIC_CMC0_SHARED_AXI_STAT */ "", 8389 /* CMIC_CMC0_SHARED_CCMDMA_READ_ARB_CTRL */ "", 8390 /* CMIC_CMC0_SHARED_CCMDMA_READ_AXI_MAP_CTRL */ "", 8391 /* CMIC_CMC0_SHARED_CCMDMA_WRITE_ARB_CTRL */ "", 8392 /* CMIC_CMC0_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL */ "", 8393 /* CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_CONTROL */ "", 8394 /* CMIC_CMC0_SHARED_COMPLETION_BUF_ECC_STATUS */ "", 8395 /* CMIC_CMC0_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES */ "", 8396 /* CMIC_CMC0_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES */ "", 8397 /* CMIC_CMC0_SHARED_COMPLETION_BUF_TM_CONTROL */ "", 8398 /* CMIC_CMC0_SHARED_CONFIG */ "", 8399 /* CMIC_CMC0_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT */ "", 8400 /* CMIC_CMC0_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT */ "", 8401 /* CMIC_CMC0_SHARED_IRQ_STAT0 */ "", 8402 /* CMIC_CMC0_SHARED_IRQ_STAT1 */ "", 8403 /* CMIC_CMC0_SHARED_IRQ_STAT_CLR0 */ "", 8404 /* CMIC_CMC0_SHARED_PACKET_DMA_READ_ARB_CTRL */ "", 8405 /* CMIC_CMC0_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL */ "", 8406 /* CMIC_CMC0_SHARED_PACKET_DMA_WRITE_ARB_CTRL */ "", 8407 /* CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0 */ "", 8408 /* CMIC_CMC0_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1 */ "", 8409 /* CMIC_CMC0_SHARED_PKT_COUNT_RXPKT */ "", 8410 /* CMIC_CMC0_SHARED_PKT_COUNT_RXPKT_ERR */ "", 8411 /* CMIC_CMC0_SHARED_PKT_COUNT_TXPKT */ "", 8412 /* CMIC_CMC0_SHARED_PKT_COUNT_TXPKT_ERR */ "", 8413 /* CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK0 */ "", 8414 /* CMIC_CMC0_SHARED_PROGRAMMABLE_COS_MASK1 */ "", 8415 /* CMIC_CMC0_SHARED_RXBUF_BLOCK_DATABUF_ALLOC */ "", 8416 /* CMIC_CMC0_SHARED_RXBUF_CONFIG */ "", 8417 /* CMIC_CMC0_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 8418 /* CMIC_CMC0_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 8419 /* CMIC_CMC0_SHARED_RXBUF_ECC_CONTROL */ "", 8420 /* CMIC_CMC0_SHARED_RXBUF_ECC_STATUS */ "", 8421 /* CMIC_CMC0_SHARED_RXBUF_ECC_STATUS_CLR */ "", 8422 /* CMIC_CMC0_SHARED_RXBUF_THRESHOLD_CONFIG */ "", 8423 /* CMIC_CMC0_SHARED_RXBUF_TM_CONTROL */ "", 8424 /* CMIC_CMC0_SHARED_SBUS_DMA_READ_ARB_CTRL */ "", 8425 /* CMIC_CMC0_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL */ "", 8426 /* CMIC_CMC0_SHARED_SBUS_DMA_WRITE_ARB_CTRL */ "", 8427 /* CMIC_CMC0_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL */ "", 8428 /* CMIC_CMC0_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 8429 /* CMIC_CMC0_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 8430 /* CMIC_CMC0_SHARED_TXBUF_DEBUG */ "", 8431 /* CMIC_CMC0_SHARED_TXBUF_ECC_CONTROL */ "", 8432 /* CMIC_CMC0_SHARED_TXBUF_ECC_STATUS */ "", 8433 /* CMIC_CMC0_SHARED_TXBUF_ECC_STATUS_CLR */ "", 8434 /* CMIC_CMC0_SHARED_TXBUF_MAX_BUF_LIMITS */ "", 8435 /* CMIC_CMC0_SHARED_TXBUF_MIN_BUF_LIMITS */ "", 8436 /* CMIC_CMC0_SHARED_TXBUF_RD_THRESHOLD_CONFIG */ "", 8437 /* CMIC_CMC0_SHARED_TXBUF_RD_WRR_ARB_CTRL */ "", 8438 /* CMIC_CMC0_SHARED_TXBUF_SLICE0_PKT_CNT */ "", 8439 /* CMIC_CMC0_SHARED_TXBUF_SLICE1_PKT_CNT */ "", 8440 /* CMIC_CMC0_SHARED_TXBUF_SLICE2_PKT_CNT */ "", 8441 /* CMIC_CMC0_SHARED_TXBUF_SLICE3_PKT_CNT */ "", 8442 /* CMIC_CMC0_SHARED_TXBUF_TM_CONTROL */ "", 8443 /* CMIC_CMC0_SLAM_DMA_CFG */ "", 8444 /* CMIC_CMC0_SLAM_DMA_CUR_ENTRY_SBUS_ADDR */ "", 8445 /* CMIC_CMC0_SLAM_DMA_ENTRY_COUNT */ "", 8446 /* CMIC_CMC0_SLAM_DMA_PCIMEM_START_ADDR */ "", 8447 /* CMIC_CMC0_SLAM_DMA_SBUS_CMD_CONFIG */ "", 8448 /* CMIC_CMC0_SLAM_DMA_SBUS_START_ADDR */ "", 8449 /* CMIC_CMC0_SLAM_DMA_STAT */ "", 8450 /* CMIC_CMC0_STAT */ "", 8451 /* CMIC_CMC0_STAT_DMA_ADDR */ "", 8452 /* CMIC_CMC0_STAT_DMA_CFG */ "", 8453 /* CMIC_CMC0_STAT_DMA_CURRENT */ "", 8454 /* CMIC_CMC0_STAT_DMA_PORTS_0 */ "", 8455 /* CMIC_CMC0_STAT_DMA_PORTS_1 */ "", 8456 /* CMIC_CMC0_STAT_DMA_PORTS_2 */ "", 8457 /* CMIC_CMC0_STAT_DMA_SBUS_START_ADDRESS */ "", 8458 /* CMIC_CMC0_STAT_DMA_STAT */ "", 8459 /* CMIC_CMC0_SW_INTR_CONFIG */ "", 8460 /* CMIC_CMC0_TABLE_DMA_CFG */ "", 8461 /* CMIC_CMC0_TABLE_DMA_CUR_ENTRY_SBUS_ADDR */ "", 8462 /* CMIC_CMC0_TABLE_DMA_ENTRY_COUNT */ "", 8463 /* CMIC_CMC0_TABLE_DMA_PCIMEM_START_ADDR */ "", 8464 /* CMIC_CMC0_TABLE_DMA_SBUS_CMD_CONFIG */ "", 8465 /* CMIC_CMC0_TABLE_DMA_SBUS_START_ADDR */ "", 8466 /* CMIC_CMC0_TABLE_DMA_STAT */ "", 8467 /* CMIC_CMC0_TM_CONTROL_0 */ "", 8468 /* CMIC_CMC0_TM_CONTROL_1 */ "", 8469 /* CMIC_CMC0_UC0_IRQ_MASK0 */ "", 8470 /* CMIC_CMC0_UC0_IRQ_MASK1 */ "", 8471 /* CMIC_CMC0_UC0_IRQ_MASK2 */ "", 8472 /* CMIC_CMC0_UC0_IRQ_MASK3 */ "", 8473 /* CMIC_CMC0_UC0_IRQ_MASK4 */ "", 8474 /* CMIC_CMC0_UC0_IRQ_MASK5 */ "", 8475 /* CMIC_CMC0_UC0_IRQ_MASK6 */ "", 8476 /* CMIC_CMC0_UC1_IRQ_MASK0 */ "", 8477 /* CMIC_CMC0_UC1_IRQ_MASK1 */ "", 8478 /* CMIC_CMC0_UC1_IRQ_MASK2 */ "", 8479 /* CMIC_CMC0_UC1_IRQ_MASK3 */ "", 8480 /* CMIC_CMC0_UC1_IRQ_MASK4 */ "", 8481 /* CMIC_CMC0_UC1_IRQ_MASK5 */ "", 8482 /* CMIC_CMC0_UC1_IRQ_MASK6 */ "", 8483 /* CMIC_CMC1_2BIT_ECC_ERROR_STATUS */ "", 8484 /* CMIC_CMC1_2BIT_ECC_ERROR_STATUS_MASK */ "", 8485 /* CMIC_CMC1_AXIIC_DMA_ECC_INTR */ "", 8486 /* CMIC_CMC1_AXIIC_DMA_ECC_INTR_CLR */ "", 8487 /* CMIC_CMC1_AXIIC_DMA_ECC_INTR_ENABLE */ "", 8488 /* CMIC_CMC1_AXIIC_TM_CONTROL_0 */ "", 8489 /* CMIC_CMC1_AXIIC_TM_CONTROL_1 */ "", 8490 /* CMIC_CMC1_AXIIC_TM_CONTROL_2 */ "", 8491 /* CMIC_CMC1_CCMDMA_CH0_CFG */ "", 8492 /* CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_HI */ "", 8493 /* CMIC_CMC1_CCMDMA_CH0_CUR_HOST0_ADDR_LO */ "", 8494 /* CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_HI */ "", 8495 /* CMIC_CMC1_CCMDMA_CH0_CUR_HOST1_ADDR_LO */ "", 8496 /* CMIC_CMC1_CCMDMA_CH0_ECC_CONTROL */ "", 8497 /* CMIC_CMC1_CCMDMA_CH0_ECC_STATUS */ "", 8498 /* CMIC_CMC1_CCMDMA_CH0_ECC_STATUS_CLR */ "", 8499 /* CMIC_CMC1_CCMDMA_CH0_ENTRY_COUNT */ "", 8500 /* CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_HI */ "", 8501 /* CMIC_CMC1_CCMDMA_CH0_HOST0_MEM_START_ADDR_LO */ "", 8502 /* CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_HI */ "", 8503 /* CMIC_CMC1_CCMDMA_CH0_HOST1_MEM_START_ADDR_LO */ "", 8504 /* CMIC_CMC1_CCMDMA_CH0_STAT */ "", 8505 /* CMIC_CMC1_CCMDMA_CH0_TM_CONTROL */ "", 8506 /* CMIC_CMC1_CCMDMA_CH1_CFG */ "", 8507 /* CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_HI */ "", 8508 /* CMIC_CMC1_CCMDMA_CH1_CUR_HOST0_ADDR_LO */ "", 8509 /* CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_HI */ "", 8510 /* CMIC_CMC1_CCMDMA_CH1_CUR_HOST1_ADDR_LO */ "", 8511 /* CMIC_CMC1_CCMDMA_CH1_ECC_CONTROL */ "", 8512 /* CMIC_CMC1_CCMDMA_CH1_ECC_STATUS */ "", 8513 /* CMIC_CMC1_CCMDMA_CH1_ECC_STATUS_CLR */ "", 8514 /* CMIC_CMC1_CCMDMA_CH1_ENTRY_COUNT */ "", 8515 /* CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_HI */ "", 8516 /* CMIC_CMC1_CCMDMA_CH1_HOST0_MEM_START_ADDR_LO */ "", 8517 /* CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_HI */ "", 8518 /* CMIC_CMC1_CCMDMA_CH1_HOST1_MEM_START_ADDR_LO */ "", 8519 /* CMIC_CMC1_CCMDMA_CH1_STAT */ "", 8520 /* CMIC_CMC1_CCMDMA_CH1_TM_CONTROL */ "", 8521 /* CMIC_CMC1_CCMDMA_TM_CONTROL_0 */ "", 8522 /* CMIC_CMC1_CCMDMA_TM_CONTROL_1 */ "", 8523 /* CMIC_CMC1_CCM_DMA_CFG */ "", 8524 /* CMIC_CMC1_CCM_DMA_CUR_HOST0_ADDR */ "", 8525 /* CMIC_CMC1_CCM_DMA_CUR_HOST1_ADDR */ "", 8526 /* CMIC_CMC1_CCM_DMA_ECCERR_ADDR */ "", 8527 /* CMIC_CMC1_CCM_DMA_ECCERR_CONTROL */ "", 8528 /* CMIC_CMC1_CCM_DMA_ENTRY_COUNT */ "", 8529 /* CMIC_CMC1_CCM_DMA_HOST0_MEM_START_ADDR */ "", 8530 /* CMIC_CMC1_CCM_DMA_HOST1_MEM_START_ADDR */ "", 8531 /* CMIC_CMC1_CCM_DMA_STAT */ "", 8532 /* CMIC_CMC1_CCM_DMA_STATUS_CLR */ "", 8533 /* CMIC_CMC1_CH0_COS_CTRL_RX_0 */ "", 8534 /* CMIC_CMC1_CH0_COS_CTRL_RX_1 */ "", 8535 /* CMIC_CMC1_CH0_DMA_CTRL */ "", 8536 /* CMIC_CMC1_CH0_DMA_CURR_DESC */ "", 8537 /* CMIC_CMC1_CH0_RXBUF_THRESHOLD_CONFIG */ "", 8538 /* CMIC_CMC1_CH1_COS_CTRL_RX_0 */ "", 8539 /* CMIC_CMC1_CH1_COS_CTRL_RX_1 */ "", 8540 /* CMIC_CMC1_CH1_DMA_CTRL */ "", 8541 /* CMIC_CMC1_CH1_DMA_CURR_DESC */ "", 8542 /* CMIC_CMC1_CH1_RXBUF_THRESHOLD_CONFIG */ "", 8543 /* CMIC_CMC1_CH2_COS_CTRL_RX_0 */ "", 8544 /* CMIC_CMC1_CH2_COS_CTRL_RX_1 */ "", 8545 /* CMIC_CMC1_CH2_DMA_CTRL */ "", 8546 /* CMIC_CMC1_CH2_DMA_CURR_DESC */ "", 8547 /* CMIC_CMC1_CH2_RXBUF_THRESHOLD_CONFIG */ "", 8548 /* CMIC_CMC1_CH3_COS_CTRL_RX_0 */ "", 8549 /* CMIC_CMC1_CH3_COS_CTRL_RX_1 */ "", 8550 /* CMIC_CMC1_CH3_DMA_CTRL */ "", 8551 /* CMIC_CMC1_CH3_DMA_CURR_DESC */ "", 8552 /* CMIC_CMC1_CH3_RXBUF_THRESHOLD_CONFIG */ "", 8553 /* CMIC_CMC1_CONFIG */ "", 8554 /* CMIC_CMC1_DMA_CH0_DESC_HALT_ADDR */ "", 8555 /* CMIC_CMC1_DMA_CH0_INTR_COAL */ "", 8556 /* CMIC_CMC1_DMA_CH1_DESC_HALT_ADDR */ "", 8557 /* CMIC_CMC1_DMA_CH1_INTR_COAL */ "", 8558 /* CMIC_CMC1_DMA_CH2_DESC_HALT_ADDR */ "", 8559 /* CMIC_CMC1_DMA_CH2_INTR_COAL */ "", 8560 /* CMIC_CMC1_DMA_CH3_DESC_HALT_ADDR */ "", 8561 /* CMIC_CMC1_DMA_CH3_INTR_COAL */ "", 8562 /* CMIC_CMC1_DMA_DESC0 */ "", 8563 /* CMIC_CMC1_DMA_DESC1 */ "", 8564 /* CMIC_CMC1_DMA_DESC2 */ "", 8565 /* CMIC_CMC1_DMA_DESC3 */ "", 8566 /* CMIC_CMC1_DMA_STAT */ "", 8567 /* CMIC_CMC1_DMA_STAT_CLR */ "", 8568 /* CMIC_CMC1_DMA_STAT_HI */ "", 8569 /* CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_0 */ "", 8570 /* CMIC_CMC1_FIFORDDMA_CH0_TM_CONTROL_1 */ "", 8571 /* CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_0 */ "", 8572 /* CMIC_CMC1_FIFORDDMA_CH1_TM_CONTROL_1 */ "", 8573 /* CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_0 */ "", 8574 /* CMIC_CMC1_FIFORDDMA_CH2_TM_CONTROL_1 */ "", 8575 /* CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_0 */ "", 8576 /* CMIC_CMC1_FIFORDDMA_CH3_TM_CONTROL_1 */ "", 8577 /* CMIC_CMC1_FIFO_CH0_RD_DMA_CFG */ "", 8578 /* CMIC_CMC1_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 8579 /* CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_ADDRESS */ "", 8580 /* CMIC_CMC1_FIFO_CH0_RD_DMA_ECCERR_CONTROL */ "", 8581 /* CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR */ "", 8582 /* CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS */ "", 8583 /* CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD */ "", 8584 /* CMIC_CMC1_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR */ "", 8585 /* CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 8586 /* CMIC_CMC1_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 8587 /* CMIC_CMC1_FIFO_CH0_RD_DMA_OPCODE */ "", 8588 /* CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG */ "", 8589 /* CMIC_CMC1_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS */ "", 8590 /* CMIC_CMC1_FIFO_CH0_RD_DMA_STAT */ "", 8591 /* CMIC_CMC1_FIFO_CH0_RD_DMA_STAT_CLR */ "", 8592 /* CMIC_CMC1_FIFO_CH1_RD_DMA_CFG */ "", 8593 /* CMIC_CMC1_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 8594 /* CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_ADDRESS */ "", 8595 /* CMIC_CMC1_FIFO_CH1_RD_DMA_ECCERR_CONTROL */ "", 8596 /* CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR */ "", 8597 /* CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS */ "", 8598 /* CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD */ "", 8599 /* CMIC_CMC1_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR */ "", 8600 /* CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 8601 /* CMIC_CMC1_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 8602 /* CMIC_CMC1_FIFO_CH1_RD_DMA_OPCODE */ "", 8603 /* CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG */ "", 8604 /* CMIC_CMC1_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS */ "", 8605 /* CMIC_CMC1_FIFO_CH1_RD_DMA_STAT */ "", 8606 /* CMIC_CMC1_FIFO_CH1_RD_DMA_STAT_CLR */ "", 8607 /* CMIC_CMC1_FIFO_CH2_RD_DMA_CFG */ "", 8608 /* CMIC_CMC1_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 8609 /* CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_ADDRESS */ "", 8610 /* CMIC_CMC1_FIFO_CH2_RD_DMA_ECCERR_CONTROL */ "", 8611 /* CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR */ "", 8612 /* CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS */ "", 8613 /* CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD */ "", 8614 /* CMIC_CMC1_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR */ "", 8615 /* CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 8616 /* CMIC_CMC1_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 8617 /* CMIC_CMC1_FIFO_CH2_RD_DMA_OPCODE */ "", 8618 /* CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG */ "", 8619 /* CMIC_CMC1_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS */ "", 8620 /* CMIC_CMC1_FIFO_CH2_RD_DMA_STAT */ "", 8621 /* CMIC_CMC1_FIFO_CH2_RD_DMA_STAT_CLR */ "", 8622 /* CMIC_CMC1_FIFO_CH3_RD_DMA_CFG */ "", 8623 /* CMIC_CMC1_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 8624 /* CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_ADDRESS */ "", 8625 /* CMIC_CMC1_FIFO_CH3_RD_DMA_ECCERR_CONTROL */ "", 8626 /* CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR */ "", 8627 /* CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS */ "", 8628 /* CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD */ "", 8629 /* CMIC_CMC1_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR */ "", 8630 /* CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 8631 /* CMIC_CMC1_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 8632 /* CMIC_CMC1_FIFO_CH3_RD_DMA_OPCODE */ "", 8633 /* CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG */ "", 8634 /* CMIC_CMC1_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS */ "", 8635 /* CMIC_CMC1_FIFO_CH3_RD_DMA_STAT */ "", 8636 /* CMIC_CMC1_FIFO_CH3_RD_DMA_STAT_CLR */ "", 8637 /* CMIC_CMC1_FIFO_RD_DMA_DEBUG */ "", 8638 /* CMIC_CMC1_FSCHAN_ADDRESS */ "", 8639 /* CMIC_CMC1_FSCHAN_DATA32 */ "", 8640 /* CMIC_CMC1_FSCHAN_DATA64_HI */ "", 8641 /* CMIC_CMC1_FSCHAN_DATA64_LO */ "", 8642 /* CMIC_CMC1_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE */ "", 8643 /* CMIC_CMC1_FSCHAN_OPCODE */ "", 8644 /* CMIC_CMC1_FSCHAN_STATUS */ "", 8645 /* CMIC_CMC1_HOSTMEM_ADDR_REMAP_0 */ "", 8646 /* CMIC_CMC1_HOSTMEM_ADDR_REMAP_1 */ "", 8647 /* CMIC_CMC1_HOSTMEM_ADDR_REMAP_2 */ "", 8648 /* CMIC_CMC1_HOSTMEM_ADDR_REMAP_3 */ "", 8649 /* CMIC_CMC1_IRQ_STAT0 */ "", 8650 /* CMIC_CMC1_IRQ_STAT1 */ "", 8651 /* CMIC_CMC1_IRQ_STAT2 */ "", 8652 /* CMIC_CMC1_IRQ_STAT3 */ "", 8653 /* CMIC_CMC1_IRQ_STAT4 */ "", 8654 /* CMIC_CMC1_IRQ_STAT5 */ "", 8655 /* CMIC_CMC1_IRQ_STAT6 */ "", 8656 /* CMIC_CMC1_MIIM_ADDRESS */ "", 8657 /* CMIC_CMC1_MIIM_CTRL */ "", 8658 /* CMIC_CMC1_MIIM_PARAM */ "", 8659 /* CMIC_CMC1_MIIM_READ_DATA */ "", 8660 /* CMIC_CMC1_MIIM_STAT */ "", 8661 /* CMIC_CMC1_PCIE_IRQ_MASK0 */ "", 8662 /* CMIC_CMC1_PCIE_IRQ_MASK1 */ "", 8663 /* CMIC_CMC1_PCIE_IRQ_MASK2 */ "", 8664 /* CMIC_CMC1_PCIE_IRQ_MASK3 */ "", 8665 /* CMIC_CMC1_PCIE_IRQ_MASK4 */ "", 8666 /* CMIC_CMC1_PCIE_IRQ_MASK5 */ "", 8667 /* CMIC_CMC1_PCIE_IRQ_MASK6 */ "", 8668 /* CMIC_CMC1_PCIE_MISCEL */ "", 8669 /* CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_0 */ "", 8670 /* CMIC_CMC1_PKTDMA_CH0_COS_CTRL_RX_1 */ "", 8671 /* CMIC_CMC1_PKTDMA_CH0_CTRL */ "", 8672 /* CMIC_CMC1_PKTDMA_CH0_CURR_DESC_HI */ "", 8673 /* CMIC_CMC1_PKTDMA_CH0_CURR_DESC_LO */ "", 8674 /* CMIC_CMC1_PKTDMA_CH0_DEBUG_CONTROL */ "", 8675 /* CMIC_CMC1_PKTDMA_CH0_DEBUG_SM_STATUS */ "", 8676 /* CMIC_CMC1_PKTDMA_CH0_DEBUG_STATUS */ "", 8677 /* CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_HI */ "", 8678 /* CMIC_CMC1_PKTDMA_CH0_DESC_ADDR_LO */ "", 8679 /* CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_REQ */ "", 8680 /* CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_RX */ "", 8681 /* CMIC_CMC1_PKTDMA_CH0_DESC_COUNT_STATUS_WR */ "", 8682 /* CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_HI */ "", 8683 /* CMIC_CMC1_PKTDMA_CH0_DESC_HALT_ADDR_LO */ "", 8684 /* CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_CONTROL */ "", 8685 /* CMIC_CMC1_PKTDMA_CH0_DESC_MEM_ECC_STATUS */ "", 8686 /* CMIC_CMC1_PKTDMA_CH0_DESC_MEM_TM_CONTROL */ "", 8687 /* CMIC_CMC1_PKTDMA_CH0_INTR_COAL */ "", 8688 /* CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT */ "", 8689 /* CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_RXPKT_DROP */ "", 8690 /* CMIC_CMC1_PKTDMA_CH0_PKT_COUNT_TXPKT */ "", 8691 /* CMIC_CMC1_PKTDMA_CH0_RXBUF_THRESHOLD_CONFIG */ "", 8692 /* CMIC_CMC1_PKTDMA_CH0_STAT */ "", 8693 /* CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_0 */ "", 8694 /* CMIC_CMC1_PKTDMA_CH1_COS_CTRL_RX_1 */ "", 8695 /* CMIC_CMC1_PKTDMA_CH1_CTRL */ "", 8696 /* CMIC_CMC1_PKTDMA_CH1_CURR_DESC_HI */ "", 8697 /* CMIC_CMC1_PKTDMA_CH1_CURR_DESC_LO */ "", 8698 /* CMIC_CMC1_PKTDMA_CH1_DEBUG_CONTROL */ "", 8699 /* CMIC_CMC1_PKTDMA_CH1_DEBUG_SM_STATUS */ "", 8700 /* CMIC_CMC1_PKTDMA_CH1_DEBUG_STATUS */ "", 8701 /* CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_HI */ "", 8702 /* CMIC_CMC1_PKTDMA_CH1_DESC_ADDR_LO */ "", 8703 /* CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_REQ */ "", 8704 /* CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_RX */ "", 8705 /* CMIC_CMC1_PKTDMA_CH1_DESC_COUNT_STATUS_WR */ "", 8706 /* CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_HI */ "", 8707 /* CMIC_CMC1_PKTDMA_CH1_DESC_HALT_ADDR_LO */ "", 8708 /* CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_CONTROL */ "", 8709 /* CMIC_CMC1_PKTDMA_CH1_DESC_MEM_ECC_STATUS */ "", 8710 /* CMIC_CMC1_PKTDMA_CH1_DESC_MEM_TM_CONTROL */ "", 8711 /* CMIC_CMC1_PKTDMA_CH1_INTR_COAL */ "", 8712 /* CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT */ "", 8713 /* CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_RXPKT_DROP */ "", 8714 /* CMIC_CMC1_PKTDMA_CH1_PKT_COUNT_TXPKT */ "", 8715 /* CMIC_CMC1_PKTDMA_CH1_RXBUF_THRESHOLD_CONFIG */ "", 8716 /* CMIC_CMC1_PKTDMA_CH1_STAT */ "", 8717 /* CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_0 */ "", 8718 /* CMIC_CMC1_PKTDMA_CH2_COS_CTRL_RX_1 */ "", 8719 /* CMIC_CMC1_PKTDMA_CH2_CTRL */ "", 8720 /* CMIC_CMC1_PKTDMA_CH2_CURR_DESC_HI */ "", 8721 /* CMIC_CMC1_PKTDMA_CH2_CURR_DESC_LO */ "", 8722 /* CMIC_CMC1_PKTDMA_CH2_DEBUG_CONTROL */ "", 8723 /* CMIC_CMC1_PKTDMA_CH2_DEBUG_SM_STATUS */ "", 8724 /* CMIC_CMC1_PKTDMA_CH2_DEBUG_STATUS */ "", 8725 /* CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_HI */ "", 8726 /* CMIC_CMC1_PKTDMA_CH2_DESC_ADDR_LO */ "", 8727 /* CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_REQ */ "", 8728 /* CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_RX */ "", 8729 /* CMIC_CMC1_PKTDMA_CH2_DESC_COUNT_STATUS_WR */ "", 8730 /* CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_HI */ "", 8731 /* CMIC_CMC1_PKTDMA_CH2_DESC_HALT_ADDR_LO */ "", 8732 /* CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_CONTROL */ "", 8733 /* CMIC_CMC1_PKTDMA_CH2_DESC_MEM_ECC_STATUS */ "", 8734 /* CMIC_CMC1_PKTDMA_CH2_DESC_MEM_TM_CONTROL */ "", 8735 /* CMIC_CMC1_PKTDMA_CH2_INTR_COAL */ "", 8736 /* CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT */ "", 8737 /* CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_RXPKT_DROP */ "", 8738 /* CMIC_CMC1_PKTDMA_CH2_PKT_COUNT_TXPKT */ "", 8739 /* CMIC_CMC1_PKTDMA_CH2_RXBUF_THRESHOLD_CONFIG */ "", 8740 /* CMIC_CMC1_PKTDMA_CH2_STAT */ "", 8741 /* CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_0 */ "", 8742 /* CMIC_CMC1_PKTDMA_CH3_COS_CTRL_RX_1 */ "", 8743 /* CMIC_CMC1_PKTDMA_CH3_CTRL */ "", 8744 /* CMIC_CMC1_PKTDMA_CH3_CURR_DESC_HI */ "", 8745 /* CMIC_CMC1_PKTDMA_CH3_CURR_DESC_LO */ "", 8746 /* CMIC_CMC1_PKTDMA_CH3_DEBUG_CONTROL */ "", 8747 /* CMIC_CMC1_PKTDMA_CH3_DEBUG_SM_STATUS */ "", 8748 /* CMIC_CMC1_PKTDMA_CH3_DEBUG_STATUS */ "", 8749 /* CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_HI */ "", 8750 /* CMIC_CMC1_PKTDMA_CH3_DESC_ADDR_LO */ "", 8751 /* CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_REQ */ "", 8752 /* CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_RX */ "", 8753 /* CMIC_CMC1_PKTDMA_CH3_DESC_COUNT_STATUS_WR */ "", 8754 /* CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_HI */ "", 8755 /* CMIC_CMC1_PKTDMA_CH3_DESC_HALT_ADDR_LO */ "", 8756 /* CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_CONTROL */ "", 8757 /* CMIC_CMC1_PKTDMA_CH3_DESC_MEM_ECC_STATUS */ "", 8758 /* CMIC_CMC1_PKTDMA_CH3_DESC_MEM_TM_CONTROL */ "", 8759 /* CMIC_CMC1_PKTDMA_CH3_INTR_COAL */ "", 8760 /* CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT */ "", 8761 /* CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_RXPKT_DROP */ "", 8762 /* CMIC_CMC1_PKTDMA_CH3_PKT_COUNT_TXPKT */ "", 8763 /* CMIC_CMC1_PKTDMA_CH3_RXBUF_THRESHOLD_CONFIG */ "", 8764 /* CMIC_CMC1_PKTDMA_CH3_STAT */ "", 8765 /* CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_0 */ "", 8766 /* CMIC_CMC1_PKTDMA_CH4_COS_CTRL_RX_1 */ "", 8767 /* CMIC_CMC1_PKTDMA_CH4_CTRL */ "", 8768 /* CMIC_CMC1_PKTDMA_CH4_CURR_DESC_HI */ "", 8769 /* CMIC_CMC1_PKTDMA_CH4_CURR_DESC_LO */ "", 8770 /* CMIC_CMC1_PKTDMA_CH4_DEBUG_CONTROL */ "", 8771 /* CMIC_CMC1_PKTDMA_CH4_DEBUG_SM_STATUS */ "", 8772 /* CMIC_CMC1_PKTDMA_CH4_DEBUG_STATUS */ "", 8773 /* CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_HI */ "", 8774 /* CMIC_CMC1_PKTDMA_CH4_DESC_ADDR_LO */ "", 8775 /* CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_REQ */ "", 8776 /* CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_RX */ "", 8777 /* CMIC_CMC1_PKTDMA_CH4_DESC_COUNT_STATUS_WR */ "", 8778 /* CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_HI */ "", 8779 /* CMIC_CMC1_PKTDMA_CH4_DESC_HALT_ADDR_LO */ "", 8780 /* CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_CONTROL */ "", 8781 /* CMIC_CMC1_PKTDMA_CH4_DESC_MEM_ECC_STATUS */ "", 8782 /* CMIC_CMC1_PKTDMA_CH4_DESC_MEM_TM_CONTROL */ "", 8783 /* CMIC_CMC1_PKTDMA_CH4_INTR_COAL */ "", 8784 /* CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT */ "", 8785 /* CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_RXPKT_DROP */ "", 8786 /* CMIC_CMC1_PKTDMA_CH4_PKT_COUNT_TXPKT */ "", 8787 /* CMIC_CMC1_PKTDMA_CH4_RXBUF_THRESHOLD_CONFIG */ "", 8788 /* CMIC_CMC1_PKTDMA_CH4_STAT */ "", 8789 /* CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_0 */ "", 8790 /* CMIC_CMC1_PKTDMA_CH5_COS_CTRL_RX_1 */ "", 8791 /* CMIC_CMC1_PKTDMA_CH5_CTRL */ "", 8792 /* CMIC_CMC1_PKTDMA_CH5_CURR_DESC_HI */ "", 8793 /* CMIC_CMC1_PKTDMA_CH5_CURR_DESC_LO */ "", 8794 /* CMIC_CMC1_PKTDMA_CH5_DEBUG_CONTROL */ "", 8795 /* CMIC_CMC1_PKTDMA_CH5_DEBUG_SM_STATUS */ "", 8796 /* CMIC_CMC1_PKTDMA_CH5_DEBUG_STATUS */ "", 8797 /* CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_HI */ "", 8798 /* CMIC_CMC1_PKTDMA_CH5_DESC_ADDR_LO */ "", 8799 /* CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_REQ */ "", 8800 /* CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_RX */ "", 8801 /* CMIC_CMC1_PKTDMA_CH5_DESC_COUNT_STATUS_WR */ "", 8802 /* CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_HI */ "", 8803 /* CMIC_CMC1_PKTDMA_CH5_DESC_HALT_ADDR_LO */ "", 8804 /* CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_CONTROL */ "", 8805 /* CMIC_CMC1_PKTDMA_CH5_DESC_MEM_ECC_STATUS */ "", 8806 /* CMIC_CMC1_PKTDMA_CH5_DESC_MEM_TM_CONTROL */ "", 8807 /* CMIC_CMC1_PKTDMA_CH5_INTR_COAL */ "", 8808 /* CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT */ "", 8809 /* CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_RXPKT_DROP */ "", 8810 /* CMIC_CMC1_PKTDMA_CH5_PKT_COUNT_TXPKT */ "", 8811 /* CMIC_CMC1_PKTDMA_CH5_RXBUF_THRESHOLD_CONFIG */ "", 8812 /* CMIC_CMC1_PKTDMA_CH5_STAT */ "", 8813 /* CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_0 */ "", 8814 /* CMIC_CMC1_PKTDMA_CH6_COS_CTRL_RX_1 */ "", 8815 /* CMIC_CMC1_PKTDMA_CH6_CTRL */ "", 8816 /* CMIC_CMC1_PKTDMA_CH6_CURR_DESC_HI */ "", 8817 /* CMIC_CMC1_PKTDMA_CH6_CURR_DESC_LO */ "", 8818 /* CMIC_CMC1_PKTDMA_CH6_DEBUG_CONTROL */ "", 8819 /* CMIC_CMC1_PKTDMA_CH6_DEBUG_SM_STATUS */ "", 8820 /* CMIC_CMC1_PKTDMA_CH6_DEBUG_STATUS */ "", 8821 /* CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_HI */ "", 8822 /* CMIC_CMC1_PKTDMA_CH6_DESC_ADDR_LO */ "", 8823 /* CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_REQ */ "", 8824 /* CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_RX */ "", 8825 /* CMIC_CMC1_PKTDMA_CH6_DESC_COUNT_STATUS_WR */ "", 8826 /* CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_HI */ "", 8827 /* CMIC_CMC1_PKTDMA_CH6_DESC_HALT_ADDR_LO */ "", 8828 /* CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_CONTROL */ "", 8829 /* CMIC_CMC1_PKTDMA_CH6_DESC_MEM_ECC_STATUS */ "", 8830 /* CMIC_CMC1_PKTDMA_CH6_DESC_MEM_TM_CONTROL */ "", 8831 /* CMIC_CMC1_PKTDMA_CH6_INTR_COAL */ "", 8832 /* CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT */ "", 8833 /* CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_RXPKT_DROP */ "", 8834 /* CMIC_CMC1_PKTDMA_CH6_PKT_COUNT_TXPKT */ "", 8835 /* CMIC_CMC1_PKTDMA_CH6_RXBUF_THRESHOLD_CONFIG */ "", 8836 /* CMIC_CMC1_PKTDMA_CH6_STAT */ "", 8837 /* CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_0 */ "", 8838 /* CMIC_CMC1_PKTDMA_CH7_COS_CTRL_RX_1 */ "", 8839 /* CMIC_CMC1_PKTDMA_CH7_CTRL */ "", 8840 /* CMIC_CMC1_PKTDMA_CH7_CURR_DESC_HI */ "", 8841 /* CMIC_CMC1_PKTDMA_CH7_CURR_DESC_LO */ "", 8842 /* CMIC_CMC1_PKTDMA_CH7_DEBUG_CONTROL */ "", 8843 /* CMIC_CMC1_PKTDMA_CH7_DEBUG_SM_STATUS */ "", 8844 /* CMIC_CMC1_PKTDMA_CH7_DEBUG_STATUS */ "", 8845 /* CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_HI */ "", 8846 /* CMIC_CMC1_PKTDMA_CH7_DESC_ADDR_LO */ "", 8847 /* CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_REQ */ "", 8848 /* CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_RX */ "", 8849 /* CMIC_CMC1_PKTDMA_CH7_DESC_COUNT_STATUS_WR */ "", 8850 /* CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_HI */ "", 8851 /* CMIC_CMC1_PKTDMA_CH7_DESC_HALT_ADDR_LO */ "", 8852 /* CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_CONTROL */ "", 8853 /* CMIC_CMC1_PKTDMA_CH7_DESC_MEM_ECC_STATUS */ "", 8854 /* CMIC_CMC1_PKTDMA_CH7_DESC_MEM_TM_CONTROL */ "", 8855 /* CMIC_CMC1_PKTDMA_CH7_INTR_COAL */ "", 8856 /* CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT */ "", 8857 /* CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_RXPKT_DROP */ "", 8858 /* CMIC_CMC1_PKTDMA_CH7_PKT_COUNT_TXPKT */ "", 8859 /* CMIC_CMC1_PKTDMA_CH7_RXBUF_THRESHOLD_CONFIG */ "", 8860 /* CMIC_CMC1_PKTDMA_CH7_STAT */ "", 8861 /* CMIC_CMC1_PKT_COUNT_CH0_RXPKT */ "", 8862 /* CMIC_CMC1_PKT_COUNT_CH0_TXPKT */ "", 8863 /* CMIC_CMC1_PKT_COUNT_CH1_RXPKT */ "", 8864 /* CMIC_CMC1_PKT_COUNT_CH1_TXPKT */ "", 8865 /* CMIC_CMC1_PKT_COUNT_CH2_RXPKT */ "", 8866 /* CMIC_CMC1_PKT_COUNT_CH2_TXPKT */ "", 8867 /* CMIC_CMC1_PKT_COUNT_CH3_RXPKT */ "", 8868 /* CMIC_CMC1_PKT_COUNT_CH3_TXPKT */ "", 8869 /* CMIC_CMC1_PKT_COUNT_RXPKT */ "", 8870 /* CMIC_CMC1_PKT_COUNT_TXPKT */ "", 8871 /* CMIC_CMC1_PROGRAMMABLE_COS_MASK0 */ "", 8872 /* CMIC_CMC1_PROGRAMMABLE_COS_MASK1 */ "", 8873 /* CMIC_CMC1_RCPU_IRQ_MASK0 */ "", 8874 /* CMIC_CMC1_RXBUF_THRESHOLD_CONFIG */ "", 8875 /* CMIC_CMC1_SBUSDMA_CH0_CONTROL */ "", 8876 /* CMIC_CMC1_SBUSDMA_CH0_COUNT */ "", 8877 /* CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS */ "", 8878 /* CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_HI */ "", 8879 /* CMIC_CMC1_SBUSDMA_CH0_CUR_DESC_ADDRESS_LO */ "", 8880 /* CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS */ "", 8881 /* CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_HI */ "", 8882 /* CMIC_CMC1_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS_LO */ "", 8883 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT */ "", 8884 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 8885 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 8886 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 8887 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE */ "", 8888 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST */ "", 8889 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 8890 /* CMIC_CMC1_SBUSDMA_CH0_CUR_SBUS_ADDRESS */ "", 8891 /* CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS */ "", 8892 /* CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_HI */ "", 8893 /* CMIC_CMC1_SBUSDMA_CH0_DESC_START_ADDRESS_LO */ "", 8894 /* CMIC_CMC1_SBUSDMA_CH0_ECC_CONTROL */ "", 8895 /* CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS */ "", 8896 /* CMIC_CMC1_SBUSDMA_CH0_ECC_STATUS_CLR */ "", 8897 /* CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS */ "", 8898 /* CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_HI */ "", 8899 /* CMIC_CMC1_SBUSDMA_CH0_HOSTMEM_START_ADDRESS_LO */ "", 8900 /* CMIC_CMC1_SBUSDMA_CH0_ITER_COUNT */ "", 8901 /* CMIC_CMC1_SBUSDMA_CH0_OPCODE */ "", 8902 /* CMIC_CMC1_SBUSDMA_CH0_REQUEST */ "", 8903 /* CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG */ "", 8904 /* CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR */ "", 8905 /* CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS */ "", 8906 /* CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_HI */ "", 8907 /* CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS_LO */ "", 8908 /* CMIC_CMC1_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL */ "", 8909 /* CMIC_CMC1_SBUSDMA_CH0_SBUS_START_ADDRESS */ "", 8910 /* CMIC_CMC1_SBUSDMA_CH0_STATUS */ "", 8911 /* CMIC_CMC1_SBUSDMA_CH0_TIMER */ "", 8912 /* CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL */ "", 8913 /* CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_0 */ "", 8914 /* CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_1 */ "", 8915 /* CMIC_CMC1_SBUSDMA_CH0_TM_CONTROL_2 */ "", 8916 /* CMIC_CMC1_SBUSDMA_CH1_CONTROL */ "", 8917 /* CMIC_CMC1_SBUSDMA_CH1_COUNT */ "", 8918 /* CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS */ "", 8919 /* CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_HI */ "", 8920 /* CMIC_CMC1_SBUSDMA_CH1_CUR_DESC_ADDRESS_LO */ "", 8921 /* CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS */ "", 8922 /* CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_HI */ "", 8923 /* CMIC_CMC1_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS_LO */ "", 8924 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT */ "", 8925 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 8926 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 8927 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 8928 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE */ "", 8929 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST */ "", 8930 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 8931 /* CMIC_CMC1_SBUSDMA_CH1_CUR_SBUS_ADDRESS */ "", 8932 /* CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS */ "", 8933 /* CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_HI */ "", 8934 /* CMIC_CMC1_SBUSDMA_CH1_DESC_START_ADDRESS_LO */ "", 8935 /* CMIC_CMC1_SBUSDMA_CH1_ECC_CONTROL */ "", 8936 /* CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS */ "", 8937 /* CMIC_CMC1_SBUSDMA_CH1_ECC_STATUS_CLR */ "", 8938 /* CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS */ "", 8939 /* CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_HI */ "", 8940 /* CMIC_CMC1_SBUSDMA_CH1_HOSTMEM_START_ADDRESS_LO */ "", 8941 /* CMIC_CMC1_SBUSDMA_CH1_ITER_COUNT */ "", 8942 /* CMIC_CMC1_SBUSDMA_CH1_OPCODE */ "", 8943 /* CMIC_CMC1_SBUSDMA_CH1_REQUEST */ "", 8944 /* CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG */ "", 8945 /* CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR */ "", 8946 /* CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS */ "", 8947 /* CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_HI */ "", 8948 /* CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS_LO */ "", 8949 /* CMIC_CMC1_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL */ "", 8950 /* CMIC_CMC1_SBUSDMA_CH1_SBUS_START_ADDRESS */ "", 8951 /* CMIC_CMC1_SBUSDMA_CH1_STATUS */ "", 8952 /* CMIC_CMC1_SBUSDMA_CH1_TIMER */ "", 8953 /* CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL */ "", 8954 /* CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_0 */ "", 8955 /* CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_1 */ "", 8956 /* CMIC_CMC1_SBUSDMA_CH1_TM_CONTROL_2 */ "", 8957 /* CMIC_CMC1_SBUSDMA_CH2_CONTROL */ "", 8958 /* CMIC_CMC1_SBUSDMA_CH2_COUNT */ "", 8959 /* CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS */ "", 8960 /* CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_HI */ "", 8961 /* CMIC_CMC1_SBUSDMA_CH2_CUR_DESC_ADDRESS_LO */ "", 8962 /* CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS */ "", 8963 /* CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_HI */ "", 8964 /* CMIC_CMC1_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS_LO */ "", 8965 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT */ "", 8966 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 8967 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 8968 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 8969 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE */ "", 8970 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST */ "", 8971 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 8972 /* CMIC_CMC1_SBUSDMA_CH2_CUR_SBUS_ADDRESS */ "", 8973 /* CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS */ "", 8974 /* CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_HI */ "", 8975 /* CMIC_CMC1_SBUSDMA_CH2_DESC_START_ADDRESS_LO */ "", 8976 /* CMIC_CMC1_SBUSDMA_CH2_ECC_CONTROL */ "", 8977 /* CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS */ "", 8978 /* CMIC_CMC1_SBUSDMA_CH2_ECC_STATUS_CLR */ "", 8979 /* CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS */ "", 8980 /* CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_HI */ "", 8981 /* CMIC_CMC1_SBUSDMA_CH2_HOSTMEM_START_ADDRESS_LO */ "", 8982 /* CMIC_CMC1_SBUSDMA_CH2_ITER_COUNT */ "", 8983 /* CMIC_CMC1_SBUSDMA_CH2_OPCODE */ "", 8984 /* CMIC_CMC1_SBUSDMA_CH2_REQUEST */ "", 8985 /* CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG */ "", 8986 /* CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR */ "", 8987 /* CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS */ "", 8988 /* CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_HI */ "", 8989 /* CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS_LO */ "", 8990 /* CMIC_CMC1_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL */ "", 8991 /* CMIC_CMC1_SBUSDMA_CH2_SBUS_START_ADDRESS */ "", 8992 /* CMIC_CMC1_SBUSDMA_CH2_STATUS */ "", 8993 /* CMIC_CMC1_SBUSDMA_CH2_TIMER */ "", 8994 /* CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL */ "", 8995 /* CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_0 */ "", 8996 /* CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_1 */ "", 8997 /* CMIC_CMC1_SBUSDMA_CH2_TM_CONTROL_2 */ "", 8998 /* CMIC_CMC1_SBUSDMA_CH3_CONTROL */ "", 8999 /* CMIC_CMC1_SBUSDMA_CH3_COUNT */ "", 9000 /* CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_HI */ "", 9001 /* CMIC_CMC1_SBUSDMA_CH3_CUR_DESC_ADDRESS_LO */ "", 9002 /* CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_HI */ "", 9003 /* CMIC_CMC1_SBUSDMA_CH3_CUR_HOSTMEM_ADDRESS_LO */ "", 9004 /* CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_COUNT */ "", 9005 /* CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_HI */ "", 9006 /* CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS_LO */ "", 9007 /* CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_OPCODE */ "", 9008 /* CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_REQUEST */ "", 9009 /* CMIC_CMC1_SBUSDMA_CH3_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 9010 /* CMIC_CMC1_SBUSDMA_CH3_CUR_SBUS_ADDRESS */ "", 9011 /* CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_HI */ "", 9012 /* CMIC_CMC1_SBUSDMA_CH3_DESC_START_ADDRESS_LO */ "", 9013 /* CMIC_CMC1_SBUSDMA_CH3_ECC_CONTROL */ "", 9014 /* CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS */ "", 9015 /* CMIC_CMC1_SBUSDMA_CH3_ECC_STATUS_CLR */ "", 9016 /* CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_HI */ "", 9017 /* CMIC_CMC1_SBUSDMA_CH3_HOSTMEM_START_ADDRESS_LO */ "", 9018 /* CMIC_CMC1_SBUSDMA_CH3_ITER_COUNT */ "", 9019 /* CMIC_CMC1_SBUSDMA_CH3_OPCODE */ "", 9020 /* CMIC_CMC1_SBUSDMA_CH3_REQUEST */ "", 9021 /* CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG */ "", 9022 /* CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_DEBUG_CLR */ "", 9023 /* CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_HI */ "", 9024 /* CMIC_CMC1_SBUSDMA_CH3_SBUSDMA_ECCERR_ADDRESS_LO */ "", 9025 /* CMIC_CMC1_SBUSDMA_CH3_SBUS_START_ADDRESS */ "", 9026 /* CMIC_CMC1_SBUSDMA_CH3_STATUS */ "", 9027 /* CMIC_CMC1_SBUSDMA_CH3_TIMER */ "", 9028 /* CMIC_CMC1_SBUSDMA_CH3_TM_CONTROL */ "", 9029 /* CMIC_CMC1_SCHAN_ACK_DATA_BEAT_COUNT */ "", 9030 /* CMIC_CMC1_SCHAN_CTRL */ "", 9031 /* CMIC_CMC1_SCHAN_ERR */ "", 9032 /* CMIC_CMC1_SCHAN_MESSAGE */ "", 9033 /* CMIC_CMC1_SCHAN_MESSAGE0 */ "", 9034 /* CMIC_CMC1_SCHAN_MESSAGE1 */ "", 9035 /* CMIC_CMC1_SCHAN_MESSAGE2 */ "", 9036 /* CMIC_CMC1_SCHAN_MESSAGE3 */ "", 9037 /* CMIC_CMC1_SCHAN_MESSAGE4 */ "", 9038 /* CMIC_CMC1_SCHAN_MESSAGE5 */ "", 9039 /* CMIC_CMC1_SCHAN_MESSAGE6 */ "", 9040 /* CMIC_CMC1_SCHAN_MESSAGE7 */ "", 9041 /* CMIC_CMC1_SCHAN_MESSAGE8 */ "", 9042 /* CMIC_CMC1_SCHAN_MESSAGE9 */ "", 9043 /* CMIC_CMC1_SCHAN_MESSAGE10 */ "", 9044 /* CMIC_CMC1_SCHAN_MESSAGE11 */ "", 9045 /* CMIC_CMC1_SCHAN_MESSAGE12 */ "", 9046 /* CMIC_CMC1_SCHAN_MESSAGE13 */ "", 9047 /* CMIC_CMC1_SCHAN_MESSAGE14 */ "", 9048 /* CMIC_CMC1_SCHAN_MESSAGE15 */ "", 9049 /* CMIC_CMC1_SCHAN_MESSAGE16 */ "", 9050 /* CMIC_CMC1_SCHAN_MESSAGE17 */ "", 9051 /* CMIC_CMC1_SCHAN_MESSAGE18 */ "", 9052 /* CMIC_CMC1_SCHAN_MESSAGE19 */ "", 9053 /* CMIC_CMC1_SCHAN_MESSAGE20 */ "", 9054 /* CMIC_CMC1_SCHAN_MESSAGE21 */ "", 9055 /* CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS */ "", 9056 /* CMIC_CMC1_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE */ "", 9057 /* CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS */ "", 9058 /* CMIC_CMC1_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE */ "", 9059 /* CMIC_CMC1_SHARED_AXI_AR_COUNT_SPLIT_TX */ "", 9060 /* CMIC_CMC1_SHARED_AXI_AR_COUNT_TX */ "", 9061 /* CMIC_CMC1_SHARED_AXI_PER_ID_STAT */ "", 9062 /* CMIC_CMC1_SHARED_AXI_STAT */ "", 9063 /* CMIC_CMC1_SHARED_CCMDMA_READ_ARB_CTRL */ "", 9064 /* CMIC_CMC1_SHARED_CCMDMA_READ_AXI_MAP_CTRL */ "", 9065 /* CMIC_CMC1_SHARED_CCMDMA_WRITE_ARB_CTRL */ "", 9066 /* CMIC_CMC1_SHARED_CCMDMA_WRITE_AXI_MAP_CTRL */ "", 9067 /* CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_CONTROL */ "", 9068 /* CMIC_CMC1_SHARED_COMPLETION_BUF_ECC_STATUS */ "", 9069 /* CMIC_CMC1_SHARED_COMPLETION_BUF_MAX_FLIST_ENTRIES */ "", 9070 /* CMIC_CMC1_SHARED_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES */ "", 9071 /* CMIC_CMC1_SHARED_COMPLETION_BUF_TM_CONTROL */ "", 9072 /* CMIC_CMC1_SHARED_CONFIG */ "", 9073 /* CMIC_CMC1_SHARED_DMA_MASTER_READ_PER_ID_OUTSTD_TRANS_LIMIT */ "", 9074 /* CMIC_CMC1_SHARED_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT */ "", 9075 /* CMIC_CMC1_SHARED_IRQ_STAT0 */ "", 9076 /* CMIC_CMC1_SHARED_IRQ_STAT1 */ "", 9077 /* CMIC_CMC1_SHARED_IRQ_STAT_CLR0 */ "", 9078 /* CMIC_CMC1_SHARED_PACKET_DMA_READ_ARB_CTRL */ "", 9079 /* CMIC_CMC1_SHARED_PACKET_DMA_READ_AXI_MAP_CTRL */ "", 9080 /* CMIC_CMC1_SHARED_PACKET_DMA_WRITE_ARB_CTRL */ "", 9081 /* CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL0 */ "", 9082 /* CMIC_CMC1_SHARED_PACKET_DMA_WRITE_AXI_MAP_CTRL1 */ "", 9083 /* CMIC_CMC1_SHARED_PKT_COUNT_RXPKT */ "", 9084 /* CMIC_CMC1_SHARED_PKT_COUNT_RXPKT_ERR */ "", 9085 /* CMIC_CMC1_SHARED_PKT_COUNT_TXPKT */ "", 9086 /* CMIC_CMC1_SHARED_PKT_COUNT_TXPKT_ERR */ "", 9087 /* CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK0 */ "", 9088 /* CMIC_CMC1_SHARED_PROGRAMMABLE_COS_MASK1 */ "", 9089 /* CMIC_CMC1_SHARED_RXBUF_BLOCK_DATABUF_ALLOC */ "", 9090 /* CMIC_CMC1_SHARED_RXBUF_CONFIG */ "", 9091 /* CMIC_CMC1_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 9092 /* CMIC_CMC1_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 9093 /* CMIC_CMC1_SHARED_RXBUF_ECC_CONTROL */ "", 9094 /* CMIC_CMC1_SHARED_RXBUF_ECC_STATUS */ "", 9095 /* CMIC_CMC1_SHARED_RXBUF_ECC_STATUS_CLR */ "", 9096 /* CMIC_CMC1_SHARED_RXBUF_THRESHOLD_CONFIG */ "", 9097 /* CMIC_CMC1_SHARED_RXBUF_TM_CONTROL */ "", 9098 /* CMIC_CMC1_SHARED_SBUS_DMA_READ_ARB_CTRL */ "", 9099 /* CMIC_CMC1_SHARED_SBUS_DMA_READ_AXI_MAP_CTRL */ "", 9100 /* CMIC_CMC1_SHARED_SBUS_DMA_WRITE_ARB_CTRL */ "", 9101 /* CMIC_CMC1_SHARED_SBUS_DMA_WRITE_AXI_MAP_CTRL */ "", 9102 /* CMIC_CMC1_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 9103 /* CMIC_CMC1_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 9104 /* CMIC_CMC1_SHARED_TXBUF_DEBUG */ "", 9105 /* CMIC_CMC1_SHARED_TXBUF_ECC_CONTROL */ "", 9106 /* CMIC_CMC1_SHARED_TXBUF_ECC_STATUS */ "", 9107 /* CMIC_CMC1_SHARED_TXBUF_ECC_STATUS_CLR */ "", 9108 /* CMIC_CMC1_SHARED_TXBUF_MAX_BUF_LIMITS */ "", 9109 /* CMIC_CMC1_SHARED_TXBUF_MIN_BUF_LIMITS */ "", 9110 /* CMIC_CMC1_SHARED_TXBUF_RD_THRESHOLD_CONFIG */ "", 9111 /* CMIC_CMC1_SHARED_TXBUF_RD_WRR_ARB_CTRL */ "", 9112 /* CMIC_CMC1_SHARED_TXBUF_SLICE0_PKT_CNT */ "", 9113 /* CMIC_CMC1_SHARED_TXBUF_SLICE1_PKT_CNT */ "", 9114 /* CMIC_CMC1_SHARED_TXBUF_SLICE2_PKT_CNT */ "", 9115 /* CMIC_CMC1_SHARED_TXBUF_SLICE3_PKT_CNT */ "", 9116 /* CMIC_CMC1_SHARED_TXBUF_TM_CONTROL */ "", 9117 /* CMIC_CMC1_SLAM_DMA_CFG */ "", 9118 /* CMIC_CMC1_SLAM_DMA_CUR_ENTRY_SBUS_ADDR */ "", 9119 /* CMIC_CMC1_SLAM_DMA_ENTRY_COUNT */ "", 9120 /* CMIC_CMC1_SLAM_DMA_PCIMEM_START_ADDR */ "", 9121 /* CMIC_CMC1_SLAM_DMA_SBUS_CMD_CONFIG */ "", 9122 /* CMIC_CMC1_SLAM_DMA_SBUS_START_ADDR */ "", 9123 /* CMIC_CMC1_SLAM_DMA_STAT */ "", 9124 /* CMIC_CMC1_STAT */ "", 9125 /* CMIC_CMC1_STAT_DMA_ADDR */ "", 9126 /* CMIC_CMC1_STAT_DMA_CFG */ "", 9127 /* CMIC_CMC1_STAT_DMA_CURRENT */ "", 9128 /* CMIC_CMC1_STAT_DMA_PORTS_0 */ "", 9129 /* CMIC_CMC1_STAT_DMA_PORTS_1 */ "", 9130 /* CMIC_CMC1_STAT_DMA_PORTS_2 */ "", 9131 /* CMIC_CMC1_STAT_DMA_SBUS_START_ADDRESS */ "", 9132 /* CMIC_CMC1_STAT_DMA_STAT */ "", 9133 /* CMIC_CMC1_SW_INTR_CONFIG */ "", 9134 /* CMIC_CMC1_TABLE_DMA_CFG */ "", 9135 /* CMIC_CMC1_TABLE_DMA_CUR_ENTRY_SBUS_ADDR */ "", 9136 /* CMIC_CMC1_TABLE_DMA_ENTRY_COUNT */ "", 9137 /* CMIC_CMC1_TABLE_DMA_PCIMEM_START_ADDR */ "", 9138 /* CMIC_CMC1_TABLE_DMA_SBUS_CMD_CONFIG */ "", 9139 /* CMIC_CMC1_TABLE_DMA_SBUS_START_ADDR */ "", 9140 /* CMIC_CMC1_TABLE_DMA_STAT */ "", 9141 /* CMIC_CMC1_TM_CONTROL_0 */ "", 9142 /* CMIC_CMC1_TM_CONTROL_1 */ "", 9143 /* CMIC_CMC1_UC0_IRQ_MASK0 */ "", 9144 /* CMIC_CMC1_UC0_IRQ_MASK1 */ "", 9145 /* CMIC_CMC1_UC0_IRQ_MASK2 */ "", 9146 /* CMIC_CMC1_UC0_IRQ_MASK3 */ "", 9147 /* CMIC_CMC1_UC0_IRQ_MASK4 */ "", 9148 /* CMIC_CMC1_UC0_IRQ_MASK5 */ "", 9149 /* CMIC_CMC1_UC0_IRQ_MASK6 */ "", 9150 /* CMIC_CMC1_UC1_IRQ_MASK0 */ "", 9151 /* CMIC_CMC1_UC1_IRQ_MASK1 */ "", 9152 /* CMIC_CMC1_UC1_IRQ_MASK2 */ "", 9153 /* CMIC_CMC1_UC1_IRQ_MASK3 */ "", 9154 /* CMIC_CMC1_UC1_IRQ_MASK4 */ "", 9155 /* CMIC_CMC1_UC1_IRQ_MASK5 */ "", 9156 /* CMIC_CMC1_UC1_IRQ_MASK6 */ "", 9157 /* CMIC_CMC2_2BIT_ECC_ERROR_STATUS */ "", 9158 /* CMIC_CMC2_2BIT_ECC_ERROR_STATUS_MASK */ "", 9159 /* CMIC_CMC2_AXIIC_DMA_ECC_INTR */ "", 9160 /* CMIC_CMC2_AXIIC_DMA_ECC_INTR_CLR */ "", 9161 /* CMIC_CMC2_AXIIC_DMA_ECC_INTR_ENABLE */ "", 9162 /* CMIC_CMC2_AXIIC_TM_CONTROL_0 */ "", 9163 /* CMIC_CMC2_AXIIC_TM_CONTROL_1 */ "", 9164 /* CMIC_CMC2_AXIIC_TM_CONTROL_2 */ "", 9165 /* CMIC_CMC2_CCMDMA_TM_CONTROL_0 */ "", 9166 /* CMIC_CMC2_CCMDMA_TM_CONTROL_1 */ "", 9167 /* CMIC_CMC2_CCM_DMA_CFG */ "", 9168 /* CMIC_CMC2_CCM_DMA_CUR_HOST0_ADDR */ "", 9169 /* CMIC_CMC2_CCM_DMA_CUR_HOST1_ADDR */ "", 9170 /* CMIC_CMC2_CCM_DMA_ECCERR_ADDR */ "", 9171 /* CMIC_CMC2_CCM_DMA_ECCERR_CONTROL */ "", 9172 /* CMIC_CMC2_CCM_DMA_ENTRY_COUNT */ "", 9173 /* CMIC_CMC2_CCM_DMA_HOST0_MEM_START_ADDR */ "", 9174 /* CMIC_CMC2_CCM_DMA_HOST1_MEM_START_ADDR */ "", 9175 /* CMIC_CMC2_CCM_DMA_STAT */ "", 9176 /* CMIC_CMC2_CCM_DMA_STATUS_CLR */ "", 9177 /* CMIC_CMC2_CH0_COS_CTRL_RX_0 */ "", 9178 /* CMIC_CMC2_CH0_COS_CTRL_RX_1 */ "", 9179 /* CMIC_CMC2_CH0_DMA_CTRL */ "", 9180 /* CMIC_CMC2_CH0_DMA_CURR_DESC */ "", 9181 /* CMIC_CMC2_CH0_RXBUF_THRESHOLD_CONFIG */ "", 9182 /* CMIC_CMC2_CH1_COS_CTRL_RX_0 */ "", 9183 /* CMIC_CMC2_CH1_COS_CTRL_RX_1 */ "", 9184 /* CMIC_CMC2_CH1_DMA_CTRL */ "", 9185 /* CMIC_CMC2_CH1_DMA_CURR_DESC */ "", 9186 /* CMIC_CMC2_CH1_RXBUF_THRESHOLD_CONFIG */ "", 9187 /* CMIC_CMC2_CH2_COS_CTRL_RX_0 */ "", 9188 /* CMIC_CMC2_CH2_COS_CTRL_RX_1 */ "", 9189 /* CMIC_CMC2_CH2_DMA_CTRL */ "", 9190 /* CMIC_CMC2_CH2_DMA_CURR_DESC */ "", 9191 /* CMIC_CMC2_CH2_RXBUF_THRESHOLD_CONFIG */ "", 9192 /* CMIC_CMC2_CH3_COS_CTRL_RX_0 */ "", 9193 /* CMIC_CMC2_CH3_COS_CTRL_RX_1 */ "", 9194 /* CMIC_CMC2_CH3_DMA_CTRL */ "", 9195 /* CMIC_CMC2_CH3_DMA_CURR_DESC */ "", 9196 /* CMIC_CMC2_CH3_RXBUF_THRESHOLD_CONFIG */ "", 9197 /* CMIC_CMC2_CONFIG */ "", 9198 /* CMIC_CMC2_DMA_CH0_DESC_HALT_ADDR */ "", 9199 /* CMIC_CMC2_DMA_CH0_INTR_COAL */ "", 9200 /* CMIC_CMC2_DMA_CH1_DESC_HALT_ADDR */ "", 9201 /* CMIC_CMC2_DMA_CH1_INTR_COAL */ "", 9202 /* CMIC_CMC2_DMA_CH2_DESC_HALT_ADDR */ "", 9203 /* CMIC_CMC2_DMA_CH2_INTR_COAL */ "", 9204 /* CMIC_CMC2_DMA_CH3_DESC_HALT_ADDR */ "", 9205 /* CMIC_CMC2_DMA_CH3_INTR_COAL */ "", 9206 /* CMIC_CMC2_DMA_DESC0 */ "", 9207 /* CMIC_CMC2_DMA_DESC1 */ "", 9208 /* CMIC_CMC2_DMA_DESC2 */ "", 9209 /* CMIC_CMC2_DMA_DESC3 */ "", 9210 /* CMIC_CMC2_DMA_STAT */ "", 9211 /* CMIC_CMC2_DMA_STAT_CLR */ "", 9212 /* CMIC_CMC2_DMA_STAT_HI */ "", 9213 /* CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_0 */ "", 9214 /* CMIC_CMC2_FIFORDDMA_CH0_TM_CONTROL_1 */ "", 9215 /* CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_0 */ "", 9216 /* CMIC_CMC2_FIFORDDMA_CH1_TM_CONTROL_1 */ "", 9217 /* CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_0 */ "", 9218 /* CMIC_CMC2_FIFORDDMA_CH2_TM_CONTROL_1 */ "", 9219 /* CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_0 */ "", 9220 /* CMIC_CMC2_FIFORDDMA_CH3_TM_CONTROL_1 */ "", 9221 /* CMIC_CMC2_FIFO_CH0_RD_DMA_CFG */ "", 9222 /* CMIC_CMC2_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 9223 /* CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_ADDRESS */ "", 9224 /* CMIC_CMC2_FIFO_CH0_RD_DMA_ECCERR_CONTROL */ "", 9225 /* CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR */ "", 9226 /* CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS */ "", 9227 /* CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD */ "", 9228 /* CMIC_CMC2_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR */ "", 9229 /* CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9230 /* CMIC_CMC2_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9231 /* CMIC_CMC2_FIFO_CH0_RD_DMA_OPCODE */ "", 9232 /* CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_CMD_CONFIG */ "", 9233 /* CMIC_CMC2_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS */ "", 9234 /* CMIC_CMC2_FIFO_CH0_RD_DMA_STAT */ "", 9235 /* CMIC_CMC2_FIFO_CH0_RD_DMA_STAT_CLR */ "", 9236 /* CMIC_CMC2_FIFO_CH1_RD_DMA_CFG */ "", 9237 /* CMIC_CMC2_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 9238 /* CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_ADDRESS */ "", 9239 /* CMIC_CMC2_FIFO_CH1_RD_DMA_ECCERR_CONTROL */ "", 9240 /* CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR */ "", 9241 /* CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS */ "", 9242 /* CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD */ "", 9243 /* CMIC_CMC2_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR */ "", 9244 /* CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9245 /* CMIC_CMC2_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9246 /* CMIC_CMC2_FIFO_CH1_RD_DMA_OPCODE */ "", 9247 /* CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_CMD_CONFIG */ "", 9248 /* CMIC_CMC2_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS */ "", 9249 /* CMIC_CMC2_FIFO_CH1_RD_DMA_STAT */ "", 9250 /* CMIC_CMC2_FIFO_CH1_RD_DMA_STAT_CLR */ "", 9251 /* CMIC_CMC2_FIFO_CH2_RD_DMA_CFG */ "", 9252 /* CMIC_CMC2_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 9253 /* CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_ADDRESS */ "", 9254 /* CMIC_CMC2_FIFO_CH2_RD_DMA_ECCERR_CONTROL */ "", 9255 /* CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR */ "", 9256 /* CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS */ "", 9257 /* CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD */ "", 9258 /* CMIC_CMC2_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR */ "", 9259 /* CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9260 /* CMIC_CMC2_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9261 /* CMIC_CMC2_FIFO_CH2_RD_DMA_OPCODE */ "", 9262 /* CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_CMD_CONFIG */ "", 9263 /* CMIC_CMC2_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS */ "", 9264 /* CMIC_CMC2_FIFO_CH2_RD_DMA_STAT */ "", 9265 /* CMIC_CMC2_FIFO_CH2_RD_DMA_STAT_CLR */ "", 9266 /* CMIC_CMC2_FIFO_CH3_RD_DMA_CFG */ "", 9267 /* CMIC_CMC2_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR */ "", 9268 /* CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_ADDRESS */ "", 9269 /* CMIC_CMC2_FIFO_CH3_RD_DMA_ECCERR_CONTROL */ "", 9270 /* CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR */ "", 9271 /* CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS */ "", 9272 /* CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD */ "", 9273 /* CMIC_CMC2_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR */ "", 9274 /* CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9275 /* CMIC_CMC2_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9276 /* CMIC_CMC2_FIFO_CH3_RD_DMA_OPCODE */ "", 9277 /* CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_CMD_CONFIG */ "", 9278 /* CMIC_CMC2_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS */ "", 9279 /* CMIC_CMC2_FIFO_CH3_RD_DMA_STAT */ "", 9280 /* CMIC_CMC2_FIFO_CH3_RD_DMA_STAT_CLR */ "", 9281 /* CMIC_CMC2_FIFO_RD_DMA_DEBUG */ "", 9282 /* CMIC_CMC2_FSCHAN_ADDRESS */ "", 9283 /* CMIC_CMC2_FSCHAN_DATA32 */ "", 9284 /* CMIC_CMC2_FSCHAN_DATA64_HI */ "", 9285 /* CMIC_CMC2_FSCHAN_DATA64_LO */ "", 9286 /* CMIC_CMC2_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE */ "", 9287 /* CMIC_CMC2_FSCHAN_OPCODE */ "", 9288 /* CMIC_CMC2_FSCHAN_STATUS */ "", 9289 /* CMIC_CMC2_HOSTMEM_ADDR_REMAP_0 */ "", 9290 /* CMIC_CMC2_HOSTMEM_ADDR_REMAP_1 */ "", 9291 /* CMIC_CMC2_HOSTMEM_ADDR_REMAP_2 */ "", 9292 /* CMIC_CMC2_HOSTMEM_ADDR_REMAP_3 */ "", 9293 /* CMIC_CMC2_IRQ_STAT0 */ "", 9294 /* CMIC_CMC2_IRQ_STAT1 */ "", 9295 /* CMIC_CMC2_IRQ_STAT2 */ "", 9296 /* CMIC_CMC2_IRQ_STAT3 */ "", 9297 /* CMIC_CMC2_IRQ_STAT4 */ "", 9298 /* CMIC_CMC2_IRQ_STAT5 */ "", 9299 /* CMIC_CMC2_IRQ_STAT6 */ "", 9300 /* CMIC_CMC2_MIIM_ADDRESS */ "", 9301 /* CMIC_CMC2_MIIM_CTRL */ "", 9302 /* CMIC_CMC2_MIIM_PARAM */ "", 9303 /* CMIC_CMC2_MIIM_READ_DATA */ "", 9304 /* CMIC_CMC2_MIIM_STAT */ "", 9305 /* CMIC_CMC2_PCIE_IRQ_MASK0 */ "", 9306 /* CMIC_CMC2_PCIE_IRQ_MASK1 */ "", 9307 /* CMIC_CMC2_PCIE_IRQ_MASK2 */ "", 9308 /* CMIC_CMC2_PCIE_IRQ_MASK3 */ "", 9309 /* CMIC_CMC2_PCIE_IRQ_MASK4 */ "", 9310 /* CMIC_CMC2_PCIE_IRQ_MASK5 */ "", 9311 /* CMIC_CMC2_PCIE_IRQ_MASK6 */ "", 9312 /* CMIC_CMC2_PCIE_MISCEL */ "", 9313 /* CMIC_CMC2_PKT_COUNT_CH0_RXPKT */ "", 9314 /* CMIC_CMC2_PKT_COUNT_CH0_TXPKT */ "", 9315 /* CMIC_CMC2_PKT_COUNT_CH1_RXPKT */ "", 9316 /* CMIC_CMC2_PKT_COUNT_CH1_TXPKT */ "", 9317 /* CMIC_CMC2_PKT_COUNT_CH2_RXPKT */ "", 9318 /* CMIC_CMC2_PKT_COUNT_CH2_TXPKT */ "", 9319 /* CMIC_CMC2_PKT_COUNT_CH3_RXPKT */ "", 9320 /* CMIC_CMC2_PKT_COUNT_CH3_TXPKT */ "", 9321 /* CMIC_CMC2_PKT_COUNT_RXPKT */ "", 9322 /* CMIC_CMC2_PKT_COUNT_TXPKT */ "", 9323 /* CMIC_CMC2_PROGRAMMABLE_COS_MASK0 */ "", 9324 /* CMIC_CMC2_PROGRAMMABLE_COS_MASK1 */ "", 9325 /* CMIC_CMC2_RCPU_IRQ_MASK0 */ "", 9326 /* CMIC_CMC2_RXBUF_THRESHOLD_CONFIG */ "", 9327 /* CMIC_CMC2_SBUSDMA_CH0_CONTROL */ "", 9328 /* CMIC_CMC2_SBUSDMA_CH0_COUNT */ "", 9329 /* CMIC_CMC2_SBUSDMA_CH0_CUR_DESC_ADDRESS */ "", 9330 /* CMIC_CMC2_SBUSDMA_CH0_CUR_HOSTMEM_ADDRESS */ "", 9331 /* CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_COUNT */ "", 9332 /* CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 9333 /* CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_OPCODE */ "", 9334 /* CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_REQUEST */ "", 9335 /* CMIC_CMC2_SBUSDMA_CH0_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 9336 /* CMIC_CMC2_SBUSDMA_CH0_CUR_SBUS_ADDRESS */ "", 9337 /* CMIC_CMC2_SBUSDMA_CH0_DESC_START_ADDRESS */ "", 9338 /* CMIC_CMC2_SBUSDMA_CH0_HOSTMEM_START_ADDRESS */ "", 9339 /* CMIC_CMC2_SBUSDMA_CH0_ITER_COUNT */ "", 9340 /* CMIC_CMC2_SBUSDMA_CH0_OPCODE */ "", 9341 /* CMIC_CMC2_SBUSDMA_CH0_REQUEST */ "", 9342 /* CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUG */ "", 9343 /* CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_DEBUG_CLR */ "", 9344 /* CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_ADDRESS */ "", 9345 /* CMIC_CMC2_SBUSDMA_CH0_SBUSDMA_ECCERR_CONTROL */ "", 9346 /* CMIC_CMC2_SBUSDMA_CH0_SBUS_START_ADDRESS */ "", 9347 /* CMIC_CMC2_SBUSDMA_CH0_STATUS */ "", 9348 /* CMIC_CMC2_SBUSDMA_CH0_TIMER */ "", 9349 /* CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_0 */ "", 9350 /* CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_1 */ "", 9351 /* CMIC_CMC2_SBUSDMA_CH0_TM_CONTROL_2 */ "", 9352 /* CMIC_CMC2_SBUSDMA_CH1_CONTROL */ "", 9353 /* CMIC_CMC2_SBUSDMA_CH1_COUNT */ "", 9354 /* CMIC_CMC2_SBUSDMA_CH1_CUR_DESC_ADDRESS */ "", 9355 /* CMIC_CMC2_SBUSDMA_CH1_CUR_HOSTMEM_ADDRESS */ "", 9356 /* CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_COUNT */ "", 9357 /* CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 9358 /* CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_OPCODE */ "", 9359 /* CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_REQUEST */ "", 9360 /* CMIC_CMC2_SBUSDMA_CH1_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 9361 /* CMIC_CMC2_SBUSDMA_CH1_CUR_SBUS_ADDRESS */ "", 9362 /* CMIC_CMC2_SBUSDMA_CH1_DESC_START_ADDRESS */ "", 9363 /* CMIC_CMC2_SBUSDMA_CH1_HOSTMEM_START_ADDRESS */ "", 9364 /* CMIC_CMC2_SBUSDMA_CH1_ITER_COUNT */ "", 9365 /* CMIC_CMC2_SBUSDMA_CH1_OPCODE */ "", 9366 /* CMIC_CMC2_SBUSDMA_CH1_REQUEST */ "", 9367 /* CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUG */ "", 9368 /* CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_DEBUG_CLR */ "", 9369 /* CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_ADDRESS */ "", 9370 /* CMIC_CMC2_SBUSDMA_CH1_SBUSDMA_ECCERR_CONTROL */ "", 9371 /* CMIC_CMC2_SBUSDMA_CH1_SBUS_START_ADDRESS */ "", 9372 /* CMIC_CMC2_SBUSDMA_CH1_STATUS */ "", 9373 /* CMIC_CMC2_SBUSDMA_CH1_TIMER */ "", 9374 /* CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_0 */ "", 9375 /* CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_1 */ "", 9376 /* CMIC_CMC2_SBUSDMA_CH1_TM_CONTROL_2 */ "", 9377 /* CMIC_CMC2_SBUSDMA_CH2_CONTROL */ "", 9378 /* CMIC_CMC2_SBUSDMA_CH2_COUNT */ "", 9379 /* CMIC_CMC2_SBUSDMA_CH2_CUR_DESC_ADDRESS */ "", 9380 /* CMIC_CMC2_SBUSDMA_CH2_CUR_HOSTMEM_ADDRESS */ "", 9381 /* CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_COUNT */ "", 9382 /* CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_HOSTMEM_START_ADDRESS */ "", 9383 /* CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_OPCODE */ "", 9384 /* CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_REQUEST */ "", 9385 /* CMIC_CMC2_SBUSDMA_CH2_CUR_SBUSDMA_CONFIG_SBUS_START_ADDRESS */ "", 9386 /* CMIC_CMC2_SBUSDMA_CH2_CUR_SBUS_ADDRESS */ "", 9387 /* CMIC_CMC2_SBUSDMA_CH2_DESC_START_ADDRESS */ "", 9388 /* CMIC_CMC2_SBUSDMA_CH2_HOSTMEM_START_ADDRESS */ "", 9389 /* CMIC_CMC2_SBUSDMA_CH2_ITER_COUNT */ "", 9390 /* CMIC_CMC2_SBUSDMA_CH2_OPCODE */ "", 9391 /* CMIC_CMC2_SBUSDMA_CH2_REQUEST */ "", 9392 /* CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUG */ "", 9393 /* CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_DEBUG_CLR */ "", 9394 /* CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_ADDRESS */ "", 9395 /* CMIC_CMC2_SBUSDMA_CH2_SBUSDMA_ECCERR_CONTROL */ "", 9396 /* CMIC_CMC2_SBUSDMA_CH2_SBUS_START_ADDRESS */ "", 9397 /* CMIC_CMC2_SBUSDMA_CH2_STATUS */ "", 9398 /* CMIC_CMC2_SBUSDMA_CH2_TIMER */ "", 9399 /* CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_0 */ "", 9400 /* CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_1 */ "", 9401 /* CMIC_CMC2_SBUSDMA_CH2_TM_CONTROL_2 */ "", 9402 /* CMIC_CMC2_SCHAN_ACK_DATA_BEAT_COUNT */ "", 9403 /* CMIC_CMC2_SCHAN_CTRL */ "", 9404 /* CMIC_CMC2_SCHAN_ERR */ "", 9405 /* CMIC_CMC2_SCHAN_MESSAGE */ "", 9406 /* CMIC_CMC2_SCHAN_MESSAGE0 */ "", 9407 /* CMIC_CMC2_SCHAN_MESSAGE1 */ "", 9408 /* CMIC_CMC2_SCHAN_MESSAGE2 */ "", 9409 /* CMIC_CMC2_SCHAN_MESSAGE3 */ "", 9410 /* CMIC_CMC2_SCHAN_MESSAGE4 */ "", 9411 /* CMIC_CMC2_SCHAN_MESSAGE5 */ "", 9412 /* CMIC_CMC2_SCHAN_MESSAGE6 */ "", 9413 /* CMIC_CMC2_SCHAN_MESSAGE7 */ "", 9414 /* CMIC_CMC2_SCHAN_MESSAGE8 */ "", 9415 /* CMIC_CMC2_SCHAN_MESSAGE9 */ "", 9416 /* CMIC_CMC2_SCHAN_MESSAGE10 */ "", 9417 /* CMIC_CMC2_SCHAN_MESSAGE11 */ "", 9418 /* CMIC_CMC2_SCHAN_MESSAGE12 */ "", 9419 /* CMIC_CMC2_SCHAN_MESSAGE13 */ "", 9420 /* CMIC_CMC2_SCHAN_MESSAGE14 */ "", 9421 /* CMIC_CMC2_SCHAN_MESSAGE15 */ "", 9422 /* CMIC_CMC2_SCHAN_MESSAGE16 */ "", 9423 /* CMIC_CMC2_SCHAN_MESSAGE17 */ "", 9424 /* CMIC_CMC2_SCHAN_MESSAGE18 */ "", 9425 /* CMIC_CMC2_SCHAN_MESSAGE19 */ "", 9426 /* CMIC_CMC2_SCHAN_MESSAGE20 */ "", 9427 /* CMIC_CMC2_SCHAN_MESSAGE21 */ "", 9428 /* CMIC_CMC2_SLAM_DMA_CFG */ "", 9429 /* CMIC_CMC2_SLAM_DMA_CUR_ENTRY_SBUS_ADDR */ "", 9430 /* CMIC_CMC2_SLAM_DMA_ENTRY_COUNT */ "", 9431 /* CMIC_CMC2_SLAM_DMA_PCIMEM_START_ADDR */ "", 9432 /* CMIC_CMC2_SLAM_DMA_SBUS_CMD_CONFIG */ "", 9433 /* CMIC_CMC2_SLAM_DMA_SBUS_START_ADDR */ "", 9434 /* CMIC_CMC2_SLAM_DMA_STAT */ "", 9435 /* CMIC_CMC2_STAT */ "", 9436 /* CMIC_CMC2_STAT_DMA_ADDR */ "", 9437 /* CMIC_CMC2_STAT_DMA_CFG */ "", 9438 /* CMIC_CMC2_STAT_DMA_CURRENT */ "", 9439 /* CMIC_CMC2_STAT_DMA_PORTS_0 */ "", 9440 /* CMIC_CMC2_STAT_DMA_PORTS_1 */ "", 9441 /* CMIC_CMC2_STAT_DMA_PORTS_2 */ "", 9442 /* CMIC_CMC2_STAT_DMA_SBUS_START_ADDRESS */ "", 9443 /* CMIC_CMC2_STAT_DMA_STAT */ "", 9444 /* CMIC_CMC2_SW_INTR_CONFIG */ "", 9445 /* CMIC_CMC2_TABLE_DMA_CFG */ "", 9446 /* CMIC_CMC2_TABLE_DMA_CUR_ENTRY_SBUS_ADDR */ "", 9447 /* CMIC_CMC2_TABLE_DMA_ENTRY_COUNT */ "", 9448 /* CMIC_CMC2_TABLE_DMA_PCIMEM_START_ADDR */ "", 9449 /* CMIC_CMC2_TABLE_DMA_SBUS_CMD_CONFIG */ "", 9450 /* CMIC_CMC2_TABLE_DMA_SBUS_START_ADDR */ "", 9451 /* CMIC_CMC2_TABLE_DMA_STAT */ "", 9452 /* CMIC_CMC2_TM_CONTROL_0 */ "", 9453 /* CMIC_CMC2_TM_CONTROL_1 */ "", 9454 /* CMIC_CMC2_UC0_IRQ_MASK0 */ "", 9455 /* CMIC_CMC2_UC0_IRQ_MASK1 */ "", 9456 /* CMIC_CMC2_UC0_IRQ_MASK2 */ "", 9457 /* CMIC_CMC2_UC0_IRQ_MASK3 */ "", 9458 /* CMIC_CMC2_UC0_IRQ_MASK4 */ "", 9459 /* CMIC_CMC2_UC0_IRQ_MASK5 */ "", 9460 /* CMIC_CMC2_UC0_IRQ_MASK6 */ "", 9461 /* CMIC_CMC2_UC1_IRQ_MASK0 */ "", 9462 /* CMIC_CMC2_UC1_IRQ_MASK1 */ "", 9463 /* CMIC_CMC2_UC1_IRQ_MASK2 */ "", 9464 /* CMIC_CMC2_UC1_IRQ_MASK3 */ "", 9465 /* CMIC_CMC2_UC1_IRQ_MASK4 */ "", 9466 /* CMIC_CMC2_UC1_IRQ_MASK5 */ "", 9467 /* CMIC_CMC2_UC1_IRQ_MASK6 */ "", 9468 /* CMIC_CMICE_BISR_REG_RD_DATA */ "", 9469 /* CMIC_COMMON_BSPI_BIGENDIAN */ "", 9470 /* CMIC_COMMON_I2C_PIO_ENDIANESS */ "", 9471 /* CMIC_COMMON_MIIM_ADDRESS */ "", 9472 /* CMIC_COMMON_MIIM_CTRL */ "", 9473 /* CMIC_COMMON_MIIM_PARAM */ "", 9474 /* CMIC_COMMON_MIIM_READ_DATA */ "", 9475 /* CMIC_COMMON_MIIM_STAT */ "", 9476 /* CMIC_COMMON_PCIE_PIO_ENDIANESS */ "", 9477 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG */ "", 9478 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CFG_1 */ "", 9479 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9480 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9481 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_HI */ "", 9482 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECCERR_ADDRESS_LO */ "", 9483 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_CONTROL */ "", 9484 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS */ "", 9485 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_ECC_STATUS_CLR */ "", 9486 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9487 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9488 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD */ "", 9489 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9490 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9491 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_OPCODE */ "", 9492 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS */ "", 9493 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT */ "", 9494 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_STAT_CLR */ "", 9495 /* CMIC_COMMON_POOL_FIFO_CH0_RD_DMA_TM_CONTROL */ "", 9496 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG */ "", 9497 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CFG_1 */ "", 9498 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9499 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9500 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_HI */ "", 9501 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECCERR_ADDRESS_LO */ "", 9502 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_CONTROL */ "", 9503 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS */ "", 9504 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_ECC_STATUS_CLR */ "", 9505 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9506 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9507 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_HOSTMEM_THRESHOLD */ "", 9508 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9509 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9510 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_OPCODE */ "", 9511 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_SBUS_START_ADDRESS */ "", 9512 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT */ "", 9513 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_STAT_CLR */ "", 9514 /* CMIC_COMMON_POOL_FIFO_CH10_RD_DMA_TM_CONTROL */ "", 9515 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG */ "", 9516 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CFG_1 */ "", 9517 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9518 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9519 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_HI */ "", 9520 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECCERR_ADDRESS_LO */ "", 9521 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_CONTROL */ "", 9522 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS */ "", 9523 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_ECC_STATUS_CLR */ "", 9524 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9525 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9526 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_HOSTMEM_THRESHOLD */ "", 9527 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9528 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9529 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_OPCODE */ "", 9530 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_SBUS_START_ADDRESS */ "", 9531 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT */ "", 9532 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_STAT_CLR */ "", 9533 /* CMIC_COMMON_POOL_FIFO_CH11_RD_DMA_TM_CONTROL */ "", 9534 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG */ "", 9535 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CFG_1 */ "", 9536 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9537 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9538 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_HI */ "", 9539 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECCERR_ADDRESS_LO */ "", 9540 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_CONTROL */ "", 9541 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS */ "", 9542 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_ECC_STATUS_CLR */ "", 9543 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9544 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9545 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD */ "", 9546 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9547 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9548 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_OPCODE */ "", 9549 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS */ "", 9550 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT */ "", 9551 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_STAT_CLR */ "", 9552 /* CMIC_COMMON_POOL_FIFO_CH1_RD_DMA_TM_CONTROL */ "", 9553 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG */ "", 9554 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CFG_1 */ "", 9555 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9556 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9557 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_HI */ "", 9558 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECCERR_ADDRESS_LO */ "", 9559 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_CONTROL */ "", 9560 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS */ "", 9561 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_ECC_STATUS_CLR */ "", 9562 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9563 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9564 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD */ "", 9565 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9566 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9567 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_OPCODE */ "", 9568 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS */ "", 9569 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT */ "", 9570 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_STAT_CLR */ "", 9571 /* CMIC_COMMON_POOL_FIFO_CH2_RD_DMA_TM_CONTROL */ "", 9572 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG */ "", 9573 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CFG_1 */ "", 9574 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9575 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9576 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_HI */ "", 9577 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECCERR_ADDRESS_LO */ "", 9578 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_CONTROL */ "", 9579 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS */ "", 9580 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_ECC_STATUS_CLR */ "", 9581 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9582 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9583 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD */ "", 9584 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9585 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9586 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_OPCODE */ "", 9587 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS */ "", 9588 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT */ "", 9589 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_STAT_CLR */ "", 9590 /* CMIC_COMMON_POOL_FIFO_CH3_RD_DMA_TM_CONTROL */ "", 9591 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG */ "", 9592 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CFG_1 */ "", 9593 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9594 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9595 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_HI */ "", 9596 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECCERR_ADDRESS_LO */ "", 9597 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_CONTROL */ "", 9598 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS */ "", 9599 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_ECC_STATUS_CLR */ "", 9600 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9601 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9602 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_HOSTMEM_THRESHOLD */ "", 9603 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9604 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9605 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_OPCODE */ "", 9606 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_SBUS_START_ADDRESS */ "", 9607 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT */ "", 9608 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_STAT_CLR */ "", 9609 /* CMIC_COMMON_POOL_FIFO_CH4_RD_DMA_TM_CONTROL */ "", 9610 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG */ "", 9611 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CFG_1 */ "", 9612 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9613 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9614 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_HI */ "", 9615 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECCERR_ADDRESS_LO */ "", 9616 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_CONTROL */ "", 9617 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS */ "", 9618 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_ECC_STATUS_CLR */ "", 9619 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9620 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9621 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_HOSTMEM_THRESHOLD */ "", 9622 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9623 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9624 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_OPCODE */ "", 9625 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_SBUS_START_ADDRESS */ "", 9626 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT */ "", 9627 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_STAT_CLR */ "", 9628 /* CMIC_COMMON_POOL_FIFO_CH5_RD_DMA_TM_CONTROL */ "", 9629 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG */ "", 9630 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CFG_1 */ "", 9631 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9632 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9633 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_HI */ "", 9634 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECCERR_ADDRESS_LO */ "", 9635 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_CONTROL */ "", 9636 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS */ "", 9637 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_ECC_STATUS_CLR */ "", 9638 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9639 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9640 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_HOSTMEM_THRESHOLD */ "", 9641 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9642 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9643 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_OPCODE */ "", 9644 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_SBUS_START_ADDRESS */ "", 9645 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT */ "", 9646 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_STAT_CLR */ "", 9647 /* CMIC_COMMON_POOL_FIFO_CH6_RD_DMA_TM_CONTROL */ "", 9648 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG */ "", 9649 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CFG_1 */ "", 9650 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9651 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9652 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_HI */ "", 9653 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECCERR_ADDRESS_LO */ "", 9654 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_CONTROL */ "", 9655 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS */ "", 9656 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_ECC_STATUS_CLR */ "", 9657 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9658 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9659 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_HOSTMEM_THRESHOLD */ "", 9660 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9661 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9662 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_OPCODE */ "", 9663 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_SBUS_START_ADDRESS */ "", 9664 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT */ "", 9665 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_STAT_CLR */ "", 9666 /* CMIC_COMMON_POOL_FIFO_CH7_RD_DMA_TM_CONTROL */ "", 9667 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG */ "", 9668 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CFG_1 */ "", 9669 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9670 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9671 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_HI */ "", 9672 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECCERR_ADDRESS_LO */ "", 9673 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_CONTROL */ "", 9674 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS */ "", 9675 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_ECC_STATUS_CLR */ "", 9676 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9677 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9678 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_HOSTMEM_THRESHOLD */ "", 9679 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9680 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9681 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_OPCODE */ "", 9682 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_SBUS_START_ADDRESS */ "", 9683 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT */ "", 9684 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_STAT_CLR */ "", 9685 /* CMIC_COMMON_POOL_FIFO_CH8_RD_DMA_TM_CONTROL */ "", 9686 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG */ "", 9687 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CFG_1 */ "", 9688 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_HI */ "", 9689 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_CUR_HOSTMEM_WRITE_PTR_LO */ "", 9690 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_HI */ "", 9691 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECCERR_ADDRESS_LO */ "", 9692 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_CONTROL */ "", 9693 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS */ "", 9694 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_ECC_STATUS_CLR */ "", 9695 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_HI */ "", 9696 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_START_ADDRESS_LO */ "", 9697 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_HOSTMEM_THRESHOLD */ "", 9698 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_READ_FRM_HOSTMEM */ "", 9699 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_NUM_OF_ENTRIES_VALID_IN_HOSTMEM */ "", 9700 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_OPCODE */ "", 9701 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_SBUS_START_ADDRESS */ "", 9702 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT */ "", 9703 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_STAT_CLR */ "", 9704 /* CMIC_COMMON_POOL_FIFO_CH9_RD_DMA_TM_CONTROL */ "", 9705 /* CMIC_COMMON_POOL_SCHAN_CH0_ACK_DATA_BEAT_COUNT */ "", 9706 /* CMIC_COMMON_POOL_SCHAN_CH0_CTRL */ "", 9707 /* CMIC_COMMON_POOL_SCHAN_CH0_ERR */ "", 9708 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE */ "", 9709 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE0 */ "", 9710 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE1 */ "", 9711 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE2 */ "", 9712 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE3 */ "", 9713 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE4 */ "", 9714 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE5 */ "", 9715 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE6 */ "", 9716 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE7 */ "", 9717 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE8 */ "", 9718 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE9 */ "", 9719 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE10 */ "", 9720 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE11 */ "", 9721 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE12 */ "", 9722 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE13 */ "", 9723 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE14 */ "", 9724 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE15 */ "", 9725 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE16 */ "", 9726 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE17 */ "", 9727 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE18 */ "", 9728 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE19 */ "", 9729 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE20 */ "", 9730 /* CMIC_COMMON_POOL_SCHAN_CH0_MESSAGE21 */ "", 9731 /* CMIC_COMMON_POOL_SCHAN_CH1_ACK_DATA_BEAT_COUNT */ "", 9732 /* CMIC_COMMON_POOL_SCHAN_CH1_CTRL */ "", 9733 /* CMIC_COMMON_POOL_SCHAN_CH1_ERR */ "", 9734 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE */ "", 9735 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE0 */ "", 9736 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE1 */ "", 9737 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE2 */ "", 9738 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE3 */ "", 9739 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE4 */ "", 9740 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE5 */ "", 9741 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE6 */ "", 9742 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE7 */ "", 9743 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE8 */ "", 9744 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE9 */ "", 9745 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE10 */ "", 9746 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE11 */ "", 9747 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE12 */ "", 9748 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE13 */ "", 9749 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE14 */ "", 9750 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE15 */ "", 9751 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE16 */ "", 9752 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE17 */ "", 9753 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE18 */ "", 9754 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE19 */ "", 9755 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE20 */ "", 9756 /* CMIC_COMMON_POOL_SCHAN_CH1_MESSAGE21 */ "", 9757 /* CMIC_COMMON_POOL_SCHAN_CH2_ACK_DATA_BEAT_COUNT */ "", 9758 /* CMIC_COMMON_POOL_SCHAN_CH2_CTRL */ "", 9759 /* CMIC_COMMON_POOL_SCHAN_CH2_ERR */ "", 9760 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE */ "", 9761 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE0 */ "", 9762 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE1 */ "", 9763 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE2 */ "", 9764 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE3 */ "", 9765 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE4 */ "", 9766 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE5 */ "", 9767 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE6 */ "", 9768 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE7 */ "", 9769 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE8 */ "", 9770 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE9 */ "", 9771 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE10 */ "", 9772 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE11 */ "", 9773 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE12 */ "", 9774 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE13 */ "", 9775 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE14 */ "", 9776 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE15 */ "", 9777 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE16 */ "", 9778 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE17 */ "", 9779 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE18 */ "", 9780 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE19 */ "", 9781 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE20 */ "", 9782 /* CMIC_COMMON_POOL_SCHAN_CH2_MESSAGE21 */ "", 9783 /* CMIC_COMMON_POOL_SCHAN_CH3_ACK_DATA_BEAT_COUNT */ "", 9784 /* CMIC_COMMON_POOL_SCHAN_CH3_CTRL */ "", 9785 /* CMIC_COMMON_POOL_SCHAN_CH3_ERR */ "", 9786 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE */ "", 9787 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE0 */ "", 9788 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE1 */ "", 9789 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE2 */ "", 9790 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE3 */ "", 9791 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE4 */ "", 9792 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE5 */ "", 9793 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE6 */ "", 9794 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE7 */ "", 9795 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE8 */ "", 9796 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE9 */ "", 9797 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE10 */ "", 9798 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE11 */ "", 9799 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE12 */ "", 9800 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE13 */ "", 9801 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE14 */ "", 9802 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE15 */ "", 9803 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE16 */ "", 9804 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE17 */ "", 9805 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE18 */ "", 9806 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE19 */ "", 9807 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE20 */ "", 9808 /* CMIC_COMMON_POOL_SCHAN_CH3_MESSAGE21 */ "", 9809 /* CMIC_COMMON_POOL_SCHAN_CH4_ACK_DATA_BEAT_COUNT */ "", 9810 /* CMIC_COMMON_POOL_SCHAN_CH4_CTRL */ "", 9811 /* CMIC_COMMON_POOL_SCHAN_CH4_ERR */ "", 9812 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE */ "", 9813 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE0 */ "", 9814 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE1 */ "", 9815 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE2 */ "", 9816 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE3 */ "", 9817 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE4 */ "", 9818 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE5 */ "", 9819 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE6 */ "", 9820 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE7 */ "", 9821 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE8 */ "", 9822 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE9 */ "", 9823 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE10 */ "", 9824 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE11 */ "", 9825 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE12 */ "", 9826 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE13 */ "", 9827 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE14 */ "", 9828 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE15 */ "", 9829 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE16 */ "", 9830 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE17 */ "", 9831 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE18 */ "", 9832 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE19 */ "", 9833 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE20 */ "", 9834 /* CMIC_COMMON_POOL_SCHAN_CH4_MESSAGE21 */ "", 9835 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY */ "", 9836 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY0 */ "", 9837 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY1 */ "", 9838 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY2 */ "", 9839 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY3 */ "", 9840 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY4 */ "", 9841 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY5 */ "", 9842 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY6 */ "", 9843 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY7 */ "", 9844 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY8 */ "", 9845 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY9 */ "", 9846 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY10 */ "", 9847 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY11 */ "", 9848 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY12 */ "", 9849 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY13 */ "", 9850 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY14 */ "", 9851 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY15 */ "", 9852 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY16 */ "", 9853 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY17 */ "", 9854 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY18 */ "", 9855 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY19 */ "", 9856 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY20 */ "", 9857 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY21 */ "", 9858 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY22 */ "", 9859 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY23 */ "", 9860 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY24 */ "", 9861 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY25 */ "", 9862 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY26 */ "", 9863 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY27 */ "", 9864 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY28 */ "", 9865 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY29 */ "", 9866 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY30 */ "", 9867 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY31 */ "", 9868 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY32 */ "", 9869 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY33 */ "", 9870 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY34 */ "", 9871 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY35 */ "", 9872 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY36 */ "", 9873 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY37 */ "", 9874 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY38 */ "", 9875 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY39 */ "", 9876 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY40 */ "", 9877 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY41 */ "", 9878 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY42 */ "", 9879 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY43 */ "", 9880 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY44 */ "", 9881 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY45 */ "", 9882 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY46 */ "", 9883 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY47 */ "", 9884 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY48 */ "", 9885 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY49 */ "", 9886 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY50 */ "", 9887 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY51 */ "", 9888 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY52 */ "", 9889 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY53 */ "", 9890 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY54 */ "", 9891 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY55 */ "", 9892 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY56 */ "", 9893 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY57 */ "", 9894 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY58 */ "", 9895 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY59 */ "", 9896 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY60 */ "", 9897 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY61 */ "", 9898 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY62 */ "", 9899 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY63 */ "", 9900 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY64 */ "", 9901 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY65 */ "", 9902 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY66 */ "", 9903 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY67 */ "", 9904 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY68 */ "", 9905 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY69 */ "", 9906 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY70 */ "", 9907 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY71 */ "", 9908 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY72 */ "", 9909 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY73 */ "", 9910 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY74 */ "", 9911 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY75 */ "", 9912 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY76 */ "", 9913 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY77 */ "", 9914 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY78 */ "", 9915 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY79 */ "", 9916 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY80 */ "", 9917 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY81 */ "", 9918 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY82 */ "", 9919 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY83 */ "", 9920 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY84 */ "", 9921 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY85 */ "", 9922 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY86 */ "", 9923 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY87 */ "", 9924 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY88 */ "", 9925 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY89 */ "", 9926 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY90 */ "", 9927 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY91 */ "", 9928 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY92 */ "", 9929 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY93 */ "", 9930 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY94 */ "", 9931 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY95 */ "", 9932 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY96 */ "", 9933 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY97 */ "", 9934 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY98 */ "", 9935 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY99 */ "", 9936 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY100 */ "", 9937 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY101 */ "", 9938 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY102 */ "", 9939 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY103 */ "", 9940 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY104 */ "", 9941 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY105 */ "", 9942 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY106 */ "", 9943 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY107 */ "", 9944 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY108 */ "", 9945 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY109 */ "", 9946 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY110 */ "", 9947 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY111 */ "", 9948 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY112 */ "", 9949 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY113 */ "", 9950 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY114 */ "", 9951 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY115 */ "", 9952 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY116 */ "", 9953 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY117 */ "", 9954 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY118 */ "", 9955 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY119 */ "", 9956 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY120 */ "", 9957 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY121 */ "", 9958 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY122 */ "", 9959 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY123 */ "", 9960 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY124 */ "", 9961 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY125 */ "", 9962 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY126 */ "", 9963 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY127 */ "", 9964 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY128 */ "", 9965 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY129 */ "", 9966 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY130 */ "", 9967 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY131 */ "", 9968 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY132 */ 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CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY344 */ "", 10181 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY345 */ "", 10182 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY346 */ "", 10183 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY347 */ "", 10184 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY348 */ "", 10185 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY349 */ "", 10186 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY350 */ "", 10187 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_COMMAND_MEMORY351 */ "", 10188 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_CTRL */ "", 10189 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_LOWER */ "", 10190 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_RESP_HOSTMEM_START_ADDR_UPPER */ "", 10191 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_STATUS */ "", 10192 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_LOWER */ "", 10193 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH0_SUMMARY_HOSTMEM_START_ADDR_UPPER */ "", 10194 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY */ "", 10195 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY0 */ "", 10196 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY1 */ "", 10197 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY2 */ "", 10198 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY3 */ "", 10199 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY4 */ "", 10200 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY5 */ "", 10201 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY6 */ "", 10202 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY7 */ "", 10203 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY8 */ "", 10204 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY9 */ "", 10205 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY10 */ "", 10206 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY11 */ "", 10207 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY12 */ "", 10208 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY13 */ "", 10209 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY14 */ "", 10210 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY15 */ "", 10211 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY16 */ "", 10212 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY17 */ "", 10213 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY18 */ "", 10214 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY19 */ "", 10215 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY20 */ "", 10216 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY21 */ "", 10217 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY22 */ "", 10218 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY23 */ "", 10219 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY24 */ "", 10220 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY25 */ "", 10221 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY26 */ "", 10222 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY27 */ "", 10223 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY28 */ "", 10224 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY29 */ "", 10225 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY30 */ "", 10226 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY31 */ "", 10227 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY32 */ "", 10228 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY33 */ "", 10229 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY34 */ "", 10230 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY35 */ "", 10231 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY36 */ "", 10232 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY37 */ "", 10233 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY38 */ "", 10234 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY39 */ "", 10235 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY40 */ "", 10236 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY41 */ "", 10237 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY42 */ "", 10238 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY43 */ "", 10239 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY44 */ "", 10240 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY45 */ "", 10241 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY46 */ "", 10242 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY47 */ "", 10243 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY48 */ "", 10244 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY49 */ "", 10245 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY50 */ "", 10246 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY51 */ "", 10247 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY52 */ "", 10248 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY53 */ "", 10249 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY54 */ "", 10250 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY55 */ "", 10251 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY56 */ "", 10252 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY57 */ "", 10253 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY58 */ "", 10254 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY59 */ "", 10255 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY60 */ "", 10256 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY61 */ "", 10257 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY62 */ "", 10258 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY63 */ "", 10259 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY64 */ "", 10260 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY65 */ "", 10261 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY66 */ "", 10262 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY67 */ "", 10263 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY68 */ "", 10264 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY69 */ "", 10265 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY70 */ "", 10266 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY71 */ "", 10267 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY72 */ "", 10268 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY73 */ "", 10269 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY74 */ "", 10270 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY75 */ "", 10271 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY76 */ "", 10272 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY77 */ "", 10273 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY78 */ "", 10274 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY79 */ "", 10275 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY80 */ "", 10276 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY81 */ "", 10277 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY82 */ "", 10278 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY83 */ "", 10279 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY84 */ "", 10280 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY85 */ "", 10281 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY86 */ "", 10282 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY87 */ "", 10283 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY88 */ "", 10284 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY89 */ "", 10285 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY90 */ "", 10286 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY91 */ "", 10287 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY92 */ "", 10288 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY93 */ "", 10289 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY94 */ "", 10290 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY95 */ "", 10291 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY96 */ "", 10292 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY97 */ "", 10293 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY98 */ "", 10294 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY99 */ "", 10295 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY100 */ "", 10296 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY101 */ "", 10297 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY102 */ "", 10298 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY103 */ "", 10299 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY104 */ "", 10300 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY105 */ "", 10301 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY106 */ "", 10302 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY107 */ "", 10303 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY108 */ "", 10304 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY109 */ "", 10305 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY110 */ "", 10306 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY111 */ "", 10307 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY112 */ "", 10308 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY113 */ "", 10309 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY114 */ "", 10310 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY115 */ "", 10311 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY116 */ "", 10312 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY117 */ "", 10313 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY118 */ "", 10314 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY119 */ "", 10315 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY120 */ "", 10316 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY121 */ "", 10317 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY122 */ "", 10318 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY123 */ "", 10319 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY124 */ "", 10320 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY125 */ "", 10321 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY126 */ "", 10322 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY127 */ "", 10323 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY128 */ "", 10324 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY129 */ "", 10325 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY130 */ "", 10326 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY131 */ "", 10327 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY132 */ "", 10328 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY133 */ "", 10329 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY134 */ "", 10330 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY135 */ "", 10331 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY136 */ "", 10332 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY137 */ "", 10333 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY138 */ "", 10334 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY139 */ "", 10335 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY140 */ "", 10336 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY141 */ "", 10337 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY142 */ "", 10338 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY143 */ "", 10339 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY144 */ "", 10340 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY145 */ "", 10341 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY146 */ "", 10342 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY147 */ "", 10343 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY148 */ "", 10344 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY149 */ "", 10345 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY150 */ "", 10346 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY151 */ "", 10347 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY152 */ "", 10348 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY153 */ "", 10349 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY154 */ "", 10350 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY155 */ "", 10351 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY156 */ "", 10352 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY157 */ "", 10353 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY158 */ "", 10354 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY159 */ "", 10355 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY160 */ "", 10356 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY161 */ "", 10357 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY162 */ "", 10358 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY163 */ "", 10359 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY164 */ "", 10360 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY165 */ "", 10361 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY166 */ "", 10362 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY167 */ "", 10363 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY168 */ "", 10364 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY169 */ "", 10365 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY170 */ "", 10366 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY171 */ "", 10367 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY172 */ "", 10368 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY173 */ "", 10369 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY174 */ "", 10370 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY175 */ "", 10371 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY176 */ "", 10372 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY177 */ "", 10373 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY178 */ "", 10374 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY179 */ "", 10375 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY180 */ "", 10376 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY181 */ "", 10377 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY182 */ "", 10378 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY183 */ "", 10379 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY184 */ "", 10380 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY185 */ "", 10381 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY186 */ "", 10382 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY187 */ "", 10383 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY188 */ "", 10384 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY189 */ "", 10385 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY190 */ "", 10386 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY191 */ "", 10387 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY192 */ "", 10388 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY193 */ "", 10389 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY194 */ "", 10390 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY195 */ "", 10391 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY196 */ "", 10392 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY197 */ "", 10393 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY198 */ "", 10394 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY199 */ "", 10395 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY200 */ "", 10396 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY201 */ "", 10397 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY202 */ "", 10398 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY203 */ "", 10399 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY204 */ "", 10400 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY205 */ "", 10401 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY206 */ "", 10402 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY207 */ "", 10403 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY208 */ "", 10404 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY209 */ "", 10405 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY210 */ "", 10406 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY211 */ "", 10407 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY212 */ "", 10408 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY213 */ "", 10409 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY214 */ "", 10410 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY215 */ "", 10411 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY216 */ "", 10412 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY217 */ "", 10413 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY218 */ "", 10414 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY219 */ "", 10415 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY220 */ "", 10416 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY221 */ "", 10417 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY222 */ "", 10418 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY223 */ "", 10419 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY224 */ "", 10420 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY225 */ "", 10421 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY226 */ "", 10422 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY227 */ "", 10423 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY228 */ "", 10424 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY229 */ "", 10425 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY230 */ "", 10426 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY231 */ "", 10427 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY232 */ "", 10428 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY233 */ "", 10429 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY234 */ "", 10430 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY235 */ "", 10431 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY236 */ "", 10432 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY237 */ "", 10433 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY238 */ "", 10434 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY239 */ "", 10435 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY240 */ "", 10436 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY241 */ "", 10437 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY242 */ "", 10438 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY243 */ "", 10439 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY244 */ "", 10440 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY245 */ "", 10441 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY246 */ "", 10442 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY247 */ "", 10443 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY248 */ "", 10444 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY249 */ "", 10445 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY250 */ "", 10446 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY251 */ "", 10447 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY252 */ "", 10448 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY253 */ "", 10449 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY254 */ "", 10450 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY255 */ "", 10451 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY256 */ "", 10452 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY257 */ "", 10453 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY258 */ "", 10454 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY259 */ "", 10455 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY260 */ "", 10456 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY261 */ "", 10457 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY262 */ "", 10458 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY263 */ "", 10459 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY264 */ "", 10460 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY265 */ "", 10461 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY266 */ "", 10462 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY267 */ "", 10463 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY268 */ "", 10464 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY269 */ "", 10465 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY270 */ "", 10466 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY271 */ "", 10467 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY272 */ "", 10468 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY273 */ "", 10469 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY274 */ "", 10470 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY275 */ "", 10471 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY276 */ "", 10472 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY277 */ "", 10473 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY278 */ "", 10474 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY279 */ "", 10475 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY280 */ "", 10476 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY281 */ "", 10477 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY282 */ "", 10478 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY283 */ "", 10479 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY284 */ "", 10480 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY285 */ "", 10481 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY286 */ "", 10482 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY287 */ "", 10483 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY288 */ "", 10484 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY289 */ "", 10485 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY290 */ "", 10486 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY291 */ "", 10487 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY292 */ "", 10488 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY293 */ "", 10489 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY294 */ "", 10490 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY295 */ "", 10491 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY296 */ "", 10492 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY297 */ "", 10493 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY298 */ "", 10494 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY299 */ "", 10495 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY300 */ "", 10496 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY301 */ "", 10497 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY302 */ "", 10498 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY303 */ "", 10499 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY304 */ "", 10500 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY305 */ "", 10501 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY306 */ "", 10502 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY307 */ "", 10503 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY308 */ "", 10504 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY309 */ "", 10505 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY310 */ "", 10506 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY311 */ "", 10507 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY312 */ "", 10508 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY313 */ "", 10509 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY314 */ "", 10510 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY315 */ "", 10511 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY316 */ "", 10512 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY317 */ "", 10513 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY318 */ "", 10514 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY319 */ "", 10515 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY320 */ "", 10516 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY321 */ "", 10517 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY322 */ "", 10518 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY323 */ "", 10519 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY324 */ "", 10520 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY325 */ "", 10521 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY326 */ "", 10522 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY327 */ "", 10523 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY328 */ "", 10524 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY329 */ "", 10525 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY330 */ "", 10526 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY331 */ "", 10527 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY332 */ "", 10528 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY333 */ "", 10529 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY334 */ "", 10530 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY335 */ "", 10531 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY336 */ "", 10532 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY337 */ "", 10533 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY338 */ "", 10534 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY339 */ "", 10535 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY340 */ "", 10536 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY341 */ "", 10537 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY342 */ "", 10538 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY343 */ "", 10539 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY344 */ "", 10540 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY345 */ "", 10541 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY346 */ "", 10542 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY347 */ "", 10543 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY348 */ "", 10544 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY349 */ "", 10545 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY350 */ "", 10546 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_COMMAND_MEMORY351 */ "", 10547 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_CTRL */ "", 10548 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_LOWER */ "", 10549 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_RESP_HOSTMEM_START_ADDR_UPPER */ "", 10550 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_STATUS */ "", 10551 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_LOWER */ "", 10552 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_CH1_SUMMARY_HOSTMEM_START_ADDR_UPPER */ "", 10553 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_CTRL */ "", 10554 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_ECC_STATUS */ "", 10555 /* CMIC_COMMON_POOL_SCHAN_FIFO_0_TM_CTRL */ "", 10556 /* CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS */ "", 10557 /* CMIC_COMMON_POOL_SHARED_1BIT_ECC_ERROR_STATUS_ENABLE */ "", 10558 /* CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS */ "", 10559 /* CMIC_COMMON_POOL_SHARED_2BIT_ECC_ERROR_STATUS_ENABLE */ "", 10560 /* CMIC_COMMON_POOL_SHARED_CONFIG */ "", 10561 /* CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_ARB_CTRL */ "", 10562 /* CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL */ "", 10563 /* CMIC_COMMON_POOL_SHARED_FIFO_DMA_WRITE_AXI_MAP_CTRL_1 */ "", 10564 /* CMIC_COMMON_POOL_SHARED_IRQ_STAT0 */ "", 10565 /* CMIC_COMMON_POOL_SHARED_SCHAN_FIFO_WRITE_ARB_CTRL */ "", 10566 /* CMIC_COMMON_RPE_PIO_ENDIANESS */ "", 10567 /* CMIC_COMMON_SCHAN_ACK_DATA_BEAT_COUNT */ "", 10568 /* CMIC_COMMON_SCHAN_CTRL */ "", 10569 /* CMIC_COMMON_SCHAN_ERR */ "", 10570 /* CMIC_COMMON_SCHAN_MESSAGE */ "", 10571 /* CMIC_COMMON_SCHAN_MESSAGE0 */ "", 10572 /* CMIC_COMMON_SCHAN_MESSAGE1 */ "", 10573 /* CMIC_COMMON_SCHAN_MESSAGE2 */ "", 10574 /* CMIC_COMMON_SCHAN_MESSAGE3 */ "", 10575 /* CMIC_COMMON_SCHAN_MESSAGE4 */ "", 10576 /* CMIC_COMMON_SCHAN_MESSAGE5 */ "", 10577 /* CMIC_COMMON_SCHAN_MESSAGE6 */ "", 10578 /* CMIC_COMMON_SCHAN_MESSAGE7 */ "", 10579 /* CMIC_COMMON_SCHAN_MESSAGE8 */ "", 10580 /* CMIC_COMMON_SCHAN_MESSAGE9 */ "", 10581 /* CMIC_COMMON_SCHAN_MESSAGE10 */ "", 10582 /* CMIC_COMMON_SCHAN_MESSAGE11 */ "", 10583 /* CMIC_COMMON_SCHAN_MESSAGE12 */ "", 10584 /* CMIC_COMMON_SCHAN_MESSAGE13 */ "", 10585 /* CMIC_COMMON_SCHAN_MESSAGE14 */ "", 10586 /* CMIC_COMMON_SCHAN_MESSAGE15 */ "", 10587 /* CMIC_COMMON_SCHAN_MESSAGE16 */ "", 10588 /* CMIC_COMMON_SCHAN_MESSAGE17 */ "", 10589 /* CMIC_COMMON_SCHAN_MESSAGE18 */ "", 10590 /* CMIC_COMMON_SCHAN_MESSAGE19 */ "", 10591 /* CMIC_COMMON_SCHAN_MESSAGE20 */ "", 10592 /* CMIC_COMMON_SCHAN_MESSAGE21 */ "", 10593 /* CMIC_COMMON_SPI_PIO_ENDIANESS */ "", 10594 /* CMIC_COMMON_STRAP_STATUS_0 */ "", 10595 /* CMIC_COMMON_STRAP_STATUS_1 */ "", 10596 /* CMIC_COMMON_UC0_PIO_ENDIANESS */ "", 10597 /* CMIC_COMMON_UC1_PIO_ENDIANESS */ "", 10598 /* CMIC_CONFIG */ "", 10599 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0 */ "", 10600 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1 */ "", 10601 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2 */ "", 10602 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3 */ "", 10603 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4 */ "", 10604 /* CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0 */ "", 10605 /* CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1 */ "", 10606 /* CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2 */ "", 10607 /* CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_3 */ "", 10608 /* CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_0 */ "", 10609 /* CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_1 */ "", 10610 /* CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_2 */ "", 10611 /* CMIC_CORE_PLL2_CTRL_STATUS_REGISTER_3 */ "", 10612 /* CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_0 */ "", 10613 /* CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_1 */ "", 10614 /* CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2 */ "", 10615 /* CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3 */ "", 10616 /* CMIC_COS_CTRL_RX */ "", 10617 /* CMIC_COS_CTRL_RX_0 */ "", 10618 /* CMIC_COS_CTRL_RX_1 */ "", 10619 /* CMIC_COS_CTRL_RX_2 */ "", 10620 /* CMIC_COS_CTRL_RX_3 */ "", 10621 /* CMIC_COS_CTRL_RX_4 */ "", 10622 /* CMIC_COS_CTRL_RX_5 */ "", 10623 /* CMIC_COS_CTRL_RX_6 */ "", 10624 /* CMIC_COS_CTRL_RX_7 */ "", 10625 /* CMIC_COS_CTRL_RX_HI */ "", 10626 /* CMIC_CPS_RESET */ "", 10627 /* CMIC_DEV_REV_ID */ "", 10628 /* CMIC_DMA_CTRL */ "", 10629 /* CMIC_DMA_DESC0 */ "", 10630 /* CMIC_DMA_DESC1 */ "", 10631 /* CMIC_DMA_DESC2 */ "", 10632 /* CMIC_DMA_DESC3 */ "", 10633 /* CMIC_DMA_IC_AR_ARB_MI0 */ "", 10634 /* CMIC_DMA_IC_AR_ARB_MI1 */ "", 10635 /* CMIC_DMA_IC_AW_ARB_MI0 */ "", 10636 /* CMIC_DMA_IC_AW_ARB_MI1 */ "", 10637 /* CMIC_DMA_IC_CFG_REG_0 */ "", 10638 /* CMIC_DMA_IC_CFG_REG_1 */ "", 10639 /* CMIC_DMA_IC_CFG_REG_2 */ "", 10640 /* CMIC_DMA_IC_ID_REG_0 */ "", 10641 /* CMIC_DMA_IC_ID_REG_1 */ "", 10642 /* CMIC_DMA_IC_ID_REG_2 */ "", 10643 /* CMIC_DMA_IC_ID_REG_3 */ "", 10644 /* CMIC_DMA_IC_PER_REG_0 */ "", 10645 /* CMIC_DMA_IC_PER_REG_1 */ "", 10646 /* CMIC_DMA_IC_PER_REG_2 */ "", 10647 /* CMIC_DMA_IC_PER_REG_3 */ "", 10648 /* CMIC_DMA_STAT */ "", 10649 /* CMIC_EB3_VLI_CONFIG_REGISTER */ "", 10650 /* CMIC_ENDIANESS_SEL */ "", 10651 /* CMIC_FIFO_CH0_RD_DMA_CFG */ "", 10652 /* CMIC_FIFO_CH0_RD_DMA_HOSTMEM_READ_PTR */ "", 10653 /* CMIC_FIFO_CH0_RD_DMA_HOSTMEM_START_ADDRESS */ "", 10654 /* CMIC_FIFO_CH0_RD_DMA_HOSTMEM_THRESHOLD */ "", 10655 /* CMIC_FIFO_CH0_RD_DMA_HOSTMEM_WRITE_PTR */ "", 10656 /* CMIC_FIFO_CH0_RD_DMA_SBUS_START_ADDRESS */ "", 10657 /* CMIC_FIFO_CH1_RD_DMA_CFG */ "", 10658 /* CMIC_FIFO_CH1_RD_DMA_HOSTMEM_READ_PTR */ "", 10659 /* CMIC_FIFO_CH1_RD_DMA_HOSTMEM_START_ADDRESS */ "", 10660 /* CMIC_FIFO_CH1_RD_DMA_HOSTMEM_THRESHOLD */ "", 10661 /* CMIC_FIFO_CH1_RD_DMA_HOSTMEM_WRITE_PTR */ "", 10662 /* CMIC_FIFO_CH1_RD_DMA_SBUS_START_ADDRESS */ "", 10663 /* CMIC_FIFO_CH2_RD_DMA_CFG */ "", 10664 /* CMIC_FIFO_CH2_RD_DMA_HOSTMEM_READ_PTR */ "", 10665 /* CMIC_FIFO_CH2_RD_DMA_HOSTMEM_START_ADDRESS */ "", 10666 /* CMIC_FIFO_CH2_RD_DMA_HOSTMEM_THRESHOLD */ "", 10667 /* CMIC_FIFO_CH2_RD_DMA_HOSTMEM_WRITE_PTR */ "", 10668 /* CMIC_FIFO_CH2_RD_DMA_SBUS_START_ADDRESS */ "", 10669 /* CMIC_FIFO_CH3_RD_DMA_CFG */ "", 10670 /* CMIC_FIFO_CH3_RD_DMA_HOSTMEM_READ_PTR */ "", 10671 /* CMIC_FIFO_CH3_RD_DMA_HOSTMEM_START_ADDRESS */ "", 10672 /* CMIC_FIFO_CH3_RD_DMA_HOSTMEM_THRESHOLD */ "", 10673 /* CMIC_FIFO_CH3_RD_DMA_HOSTMEM_WRITE_PTR */ "", 10674 /* CMIC_FIFO_CH3_RD_DMA_SBUS_START_ADDRESS */ "", 10675 /* CMIC_FIFO_DMA_SB_ARB_CTRL */ "", 10676 /* CMIC_FIFO_RD_DMA_DEBUG */ "", 10677 /* CMIC_FINE_GRAIN_COUNTERS_CTRL */ "", 10678 /* CMIC_FINE_GRAIN_COUNTERS_NS_VALUE */ "", 10679 /* CMIC_FINE_GRAIN_COUNTERS_SECOND_VALUE */ "", 10680 /* CMIC_FSCHAN_ADDRESS */ "", 10681 /* CMIC_FSCHAN_DATA32 */ "", 10682 /* CMIC_FSCHAN_DATA64_HI */ "", 10683 /* CMIC_FSCHAN_DATA64_LO */ "", 10684 /* CMIC_FSCHAN_ENABLE_PROGRAMMABLE_OPCODE */ "", 10685 /* CMIC_FSCHAN_OPCODE */ "", 10686 /* CMIC_FSCHAN_STATUS */ "", 10687 /* CMIC_FSRF_STBY_CONTROL */ "", 10688 /* CMIC_GFPORT_CLOCK_CONFIG */ "", 10689 /* CMIC_GP_AUX_SEL */ "", 10690 /* CMIC_GP_DATA_IN */ "", 10691 /* CMIC_GP_DATA_OUT */ "", 10692 /* CMIC_GP_INIT_VAL */ "", 10693 /* CMIC_GP_INT_CLR */ "", 10694 /* CMIC_GP_INT_DE */ "", 10695 /* CMIC_GP_INT_EDGE */ "", 10696 /* CMIC_GP_INT_MSK */ "", 10697 /* CMIC_GP_INT_MSTAT */ "", 10698 /* CMIC_GP_INT_STAT */ "", 10699 /* CMIC_GP_INT_TYPE */ "", 10700 /* CMIC_GP_OUT_EN */ "", 10701 /* CMIC_GP_PAD_RES */ "", 10702 /* CMIC_GP_PRB_ENABLE */ "", 10703 /* CMIC_GP_PRB_OE */ "", 10704 /* CMIC_GP_RES_EN */ "", 10705 /* CMIC_GP_TEST_ENABLE */ "", 10706 /* CMIC_GP_TEST_INPUT */ "", 10707 /* CMIC_GP_TEST_OUTPUT */ "", 10708 /* CMIC_I2CM_SMBUS_ADDRESS */ "", 10709 /* CMIC_I2CM_SMBUS_BIT_BANG_CONTROL */ "", 10710 /* CMIC_I2CM_SMBUS_CONFIG */ "", 10711 /* CMIC_I2CM_SMBUS_EVENT_ENABLE */ "", 10712 /* CMIC_I2CM_SMBUS_EVENT_STATUS */ "", 10713 /* CMIC_I2CM_SMBUS_MASTER_COMMAND */ "", 10714 /* CMIC_I2CM_SMBUS_MASTER_DATA_READ */ "", 10715 /* CMIC_I2CM_SMBUS_MASTER_DATA_WRITE */ "", 10716 /* CMIC_I2CM_SMBUS_MASTER_FIFO_CONTROL */ "", 10717 /* CMIC_I2CM_SMBUS_SLAVE_COMMAND */ "", 10718 /* CMIC_I2CM_SMBUS_SLAVE_DATA_READ */ "", 10719 /* CMIC_I2CM_SMBUS_SLAVE_DATA_WRITE */ "", 10720 /* CMIC_I2CM_SMBUS_SLAVE_FIFO_CONTROL */ "", 10721 /* CMIC_I2CM_SMBUS_TIMING_CONFIG */ "", 10722 /* CMIC_I2C_CTRL */ "", 10723 /* CMIC_I2C_DATA */ "", 10724 /* CMIC_I2C_RESET */ "", 10725 /* CMIC_I2C_SLAVE_ADDR */ "", 10726 /* CMIC_I2C_SLAVE_XADDR */ "", 10727 /* CMIC_I2C_STAT */ "", 10728 /* CMIC_INTR_PKT_PACING_DELAY */ "", 10729 /* CMIC_INTR_WAIT_CYCLES */ "", 10730 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE0 */ "", 10731 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE1 */ "", 10732 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE2 */ "", 10733 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE3 */ "", 10734 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE4 */ "", 10735 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE5 */ "", 10736 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE6 */ "", 10737 /* CMIC_IPROC_TO_RCPU_IRQ_ENABLE7 */ "", 10738 /* CMIC_IPROC_TO_RCPU_IRQ_STAT0 */ "", 10739 /* CMIC_IPROC_TO_RCPU_IRQ_STAT1 */ "", 10740 /* CMIC_IPROC_TO_RCPU_IRQ_STAT2 */ "", 10741 /* CMIC_IPROC_TO_RCPU_IRQ_STAT3 */ "", 10742 /* CMIC_IPROC_TO_RCPU_IRQ_STAT4 */ "", 10743 /* CMIC_IPROC_TO_RCPU_IRQ_STAT5 */ "", 10744 /* CMIC_IPROC_TO_RCPU_IRQ_STAT6 */ "", 10745 /* CMIC_IPROC_TO_RCPU_IRQ_STAT7 */ "", 10746 /* CMIC_IRQ_CLR_3 */ "", 10747 /* CMIC_IRQ_MASK */ "", 10748 /* CMIC_IRQ_MASK_1 */ "", 10749 /* CMIC_IRQ_MASK_2 */ "", 10750 /* CMIC_IRQ_MASK_3 */ "", 10751 /* CMIC_IRQ_STAT */ "", 10752 /* CMIC_IRQ_STAT_1 */ "", 10753 /* CMIC_IRQ_STAT_2 */ "", 10754 /* CMIC_IRQ_STAT_3 */ "", 10755 /* CMIC_LEDCLK_PARAMS */ "", 10756 /* CMIC_LEDUP0_CLK_DIV */ "", 10757 /* CMIC_LEDUP0_CLK_PARAMS */ "", 10758 /* CMIC_LEDUP0_CTRL */ "", 10759 /* CMIC_LEDUP0_DATA_RAM */ "", 10760 /* CMIC_LEDUP0_DATA_RAM0 */ "", 10761 /* CMIC_LEDUP0_DATA_RAM1 */ "", 10762 /* CMIC_LEDUP0_DATA_RAM2 */ "", 10763 /* CMIC_LEDUP0_DATA_RAM3 */ "", 10764 /* CMIC_LEDUP0_DATA_RAM4 */ "", 10765 /* CMIC_LEDUP0_DATA_RAM5 */ "", 10766 /* CMIC_LEDUP0_DATA_RAM6 */ "", 10767 /* CMIC_LEDUP0_DATA_RAM7 */ "", 10768 /* CMIC_LEDUP0_DATA_RAM8 */ "", 10769 /* CMIC_LEDUP0_DATA_RAM9 */ "", 10770 /* CMIC_LEDUP0_DATA_RAM10 */ "", 10771 /* CMIC_LEDUP0_DATA_RAM11 */ "", 10772 /* CMIC_LEDUP0_DATA_RAM12 */ "", 10773 /* CMIC_LEDUP0_DATA_RAM13 */ "", 10774 /* CMIC_LEDUP0_DATA_RAM14 */ "", 10775 /* CMIC_LEDUP0_DATA_RAM15 */ "", 10776 /* CMIC_LEDUP0_DATA_RAM16 */ "", 10777 /* CMIC_LEDUP0_DATA_RAM17 */ "", 10778 /* CMIC_LEDUP0_DATA_RAM18 */ "", 10779 /* CMIC_LEDUP0_DATA_RAM19 */ "", 10780 /* CMIC_LEDUP0_DATA_RAM20 */ "", 10781 /* CMIC_LEDUP0_DATA_RAM21 */ "", 10782 /* CMIC_LEDUP0_DATA_RAM22 */ "", 10783 /* CMIC_LEDUP0_DATA_RAM23 */ "", 10784 /* CMIC_LEDUP0_DATA_RAM24 */ "", 10785 /* CMIC_LEDUP0_DATA_RAM25 */ "", 10786 /* CMIC_LEDUP0_DATA_RAM26 */ "", 10787 /* CMIC_LEDUP0_DATA_RAM27 */ "", 10788 /* CMIC_LEDUP0_DATA_RAM28 */ "", 10789 /* CMIC_LEDUP0_DATA_RAM29 */ "", 10790 /* CMIC_LEDUP0_DATA_RAM30 */ "", 10791 /* CMIC_LEDUP0_DATA_RAM31 */ "", 10792 /* CMIC_LEDUP0_DATA_RAM32 */ "", 10793 /* CMIC_LEDUP0_DATA_RAM33 */ "", 10794 /* CMIC_LEDUP0_DATA_RAM34 */ "", 10795 /* CMIC_LEDUP0_DATA_RAM35 */ "", 10796 /* CMIC_LEDUP0_DATA_RAM36 */ "", 10797 /* CMIC_LEDUP0_DATA_RAM37 */ "", 10798 /* CMIC_LEDUP0_DATA_RAM38 */ "", 10799 /* CMIC_LEDUP0_DATA_RAM39 */ "", 10800 /* CMIC_LEDUP0_DATA_RAM40 */ "", 10801 /* CMIC_LEDUP0_DATA_RAM41 */ "", 10802 /* CMIC_LEDUP0_DATA_RAM42 */ "", 10803 /* CMIC_LEDUP0_DATA_RAM43 */ "", 10804 /* CMIC_LEDUP0_DATA_RAM44 */ "", 10805 /* CMIC_LEDUP0_DATA_RAM45 */ "", 10806 /* CMIC_LEDUP0_DATA_RAM46 */ "", 10807 /* CMIC_LEDUP0_DATA_RAM47 */ "", 10808 /* CMIC_LEDUP0_DATA_RAM48 */ "", 10809 /* CMIC_LEDUP0_DATA_RAM49 */ "", 10810 /* CMIC_LEDUP0_DATA_RAM50 */ "", 10811 /* CMIC_LEDUP0_DATA_RAM51 */ "", 10812 /* CMIC_LEDUP0_DATA_RAM52 */ "", 10813 /* CMIC_LEDUP0_DATA_RAM53 */ "", 10814 /* CMIC_LEDUP0_DATA_RAM54 */ "", 10815 /* CMIC_LEDUP0_DATA_RAM55 */ "", 10816 /* CMIC_LEDUP0_DATA_RAM56 */ "", 10817 /* CMIC_LEDUP0_DATA_RAM57 */ "", 10818 /* CMIC_LEDUP0_DATA_RAM58 */ "", 10819 /* CMIC_LEDUP0_DATA_RAM59 */ "", 10820 /* CMIC_LEDUP0_DATA_RAM60 */ "", 10821 /* CMIC_LEDUP0_DATA_RAM61 */ "", 10822 /* CMIC_LEDUP0_DATA_RAM62 */ "", 10823 /* CMIC_LEDUP0_DATA_RAM63 */ "", 10824 /* CMIC_LEDUP0_DATA_RAM64 */ "", 10825 /* CMIC_LEDUP0_DATA_RAM65 */ "", 10826 /* CMIC_LEDUP0_DATA_RAM66 */ "", 10827 /* CMIC_LEDUP0_DATA_RAM67 */ "", 10828 /* CMIC_LEDUP0_DATA_RAM68 */ "", 10829 /* CMIC_LEDUP0_DATA_RAM69 */ "", 10830 /* CMIC_LEDUP0_DATA_RAM70 */ "", 10831 /* CMIC_LEDUP0_DATA_RAM71 */ "", 10832 /* CMIC_LEDUP0_DATA_RAM72 */ "", 10833 /* CMIC_LEDUP0_DATA_RAM73 */ "", 10834 /* CMIC_LEDUP0_DATA_RAM74 */ "", 10835 /* CMIC_LEDUP0_DATA_RAM75 */ "", 10836 /* CMIC_LEDUP0_DATA_RAM76 */ "", 10837 /* CMIC_LEDUP0_DATA_RAM77 */ "", 10838 /* CMIC_LEDUP0_DATA_RAM78 */ "", 10839 /* CMIC_LEDUP0_DATA_RAM79 */ "", 10840 /* CMIC_LEDUP0_DATA_RAM80 */ "", 10841 /* CMIC_LEDUP0_DATA_RAM81 */ "", 10842 /* CMIC_LEDUP0_DATA_RAM82 */ "", 10843 /* CMIC_LEDUP0_DATA_RAM83 */ "", 10844 /* CMIC_LEDUP0_DATA_RAM84 */ "", 10845 /* CMIC_LEDUP0_DATA_RAM85 */ "", 10846 /* CMIC_LEDUP0_DATA_RAM86 */ "", 10847 /* CMIC_LEDUP0_DATA_RAM87 */ "", 10848 /* CMIC_LEDUP0_DATA_RAM88 */ "", 10849 /* CMIC_LEDUP0_DATA_RAM89 */ "", 10850 /* CMIC_LEDUP0_DATA_RAM90 */ "", 10851 /* CMIC_LEDUP0_DATA_RAM91 */ "", 10852 /* CMIC_LEDUP0_DATA_RAM92 */ "", 10853 /* CMIC_LEDUP0_DATA_RAM93 */ "", 10854 /* CMIC_LEDUP0_DATA_RAM94 */ "", 10855 /* CMIC_LEDUP0_DATA_RAM95 */ "", 10856 /* CMIC_LEDUP0_DATA_RAM96 */ "", 10857 /* CMIC_LEDUP0_DATA_RAM97 */ "", 10858 /* CMIC_LEDUP0_DATA_RAM98 */ "", 10859 /* CMIC_LEDUP0_DATA_RAM99 */ "", 10860 /* CMIC_LEDUP0_DATA_RAM100 */ "", 10861 /* CMIC_LEDUP0_DATA_RAM101 */ "", 10862 /* CMIC_LEDUP0_DATA_RAM102 */ "", 10863 /* CMIC_LEDUP0_DATA_RAM103 */ "", 10864 /* CMIC_LEDUP0_DATA_RAM104 */ "", 10865 /* CMIC_LEDUP0_DATA_RAM105 */ "", 10866 /* CMIC_LEDUP0_DATA_RAM106 */ "", 10867 /* CMIC_LEDUP0_DATA_RAM107 */ "", 10868 /* CMIC_LEDUP0_DATA_RAM108 */ "", 10869 /* CMIC_LEDUP0_DATA_RAM109 */ "", 10870 /* CMIC_LEDUP0_DATA_RAM110 */ "", 10871 /* CMIC_LEDUP0_DATA_RAM111 */ "", 10872 /* CMIC_LEDUP0_DATA_RAM112 */ "", 10873 /* CMIC_LEDUP0_DATA_RAM113 */ "", 10874 /* CMIC_LEDUP0_DATA_RAM114 */ "", 10875 /* CMIC_LEDUP0_DATA_RAM115 */ "", 10876 /* CMIC_LEDUP0_DATA_RAM116 */ "", 10877 /* CMIC_LEDUP0_DATA_RAM117 */ "", 10878 /* CMIC_LEDUP0_DATA_RAM118 */ "", 10879 /* CMIC_LEDUP0_DATA_RAM119 */ "", 10880 /* CMIC_LEDUP0_DATA_RAM120 */ "", 10881 /* CMIC_LEDUP0_DATA_RAM121 */ "", 10882 /* CMIC_LEDUP0_DATA_RAM122 */ "", 10883 /* CMIC_LEDUP0_DATA_RAM123 */ "", 10884 /* CMIC_LEDUP0_DATA_RAM124 */ "", 10885 /* CMIC_LEDUP0_DATA_RAM125 */ "", 10886 /* CMIC_LEDUP0_DATA_RAM126 */ "", 10887 /* CMIC_LEDUP0_DATA_RAM127 */ "", 10888 /* CMIC_LEDUP0_DATA_RAM128 */ "", 10889 /* CMIC_LEDUP0_DATA_RAM129 */ "", 10890 /* CMIC_LEDUP0_DATA_RAM130 */ "", 10891 /* CMIC_LEDUP0_DATA_RAM131 */ "", 10892 /* CMIC_LEDUP0_DATA_RAM132 */ "", 10893 /* CMIC_LEDUP0_DATA_RAM133 */ "", 10894 /* CMIC_LEDUP0_DATA_RAM134 */ "", 10895 /* CMIC_LEDUP0_DATA_RAM135 */ "", 10896 /* CMIC_LEDUP0_DATA_RAM136 */ "", 10897 /* CMIC_LEDUP0_DATA_RAM137 */ "", 10898 /* CMIC_LEDUP0_DATA_RAM138 */ "", 10899 /* CMIC_LEDUP0_DATA_RAM139 */ "", 10900 /* CMIC_LEDUP0_DATA_RAM140 */ "", 10901 /* CMIC_LEDUP0_DATA_RAM141 */ "", 10902 /* CMIC_LEDUP0_DATA_RAM142 */ "", 10903 /* CMIC_LEDUP0_DATA_RAM143 */ "", 10904 /* CMIC_LEDUP0_DATA_RAM144 */ "", 10905 /* CMIC_LEDUP0_DATA_RAM145 */ "", 10906 /* CMIC_LEDUP0_DATA_RAM146 */ "", 10907 /* CMIC_LEDUP0_DATA_RAM147 */ "", 10908 /* CMIC_LEDUP0_DATA_RAM148 */ "", 10909 /* CMIC_LEDUP0_DATA_RAM149 */ "", 10910 /* CMIC_LEDUP0_DATA_RAM150 */ "", 10911 /* CMIC_LEDUP0_DATA_RAM151 */ "", 10912 /* CMIC_LEDUP0_DATA_RAM152 */ "", 10913 /* CMIC_LEDUP0_DATA_RAM153 */ "", 10914 /* CMIC_LEDUP0_DATA_RAM154 */ "", 10915 /* CMIC_LEDUP0_DATA_RAM155 */ "", 10916 /* CMIC_LEDUP0_DATA_RAM156 */ "", 10917 /* CMIC_LEDUP0_DATA_RAM157 */ "", 10918 /* CMIC_LEDUP0_DATA_RAM158 */ "", 10919 /* CMIC_LEDUP0_DATA_RAM159 */ "", 10920 /* CMIC_LEDUP0_DATA_RAM160 */ "", 10921 /* CMIC_LEDUP0_DATA_RAM161 */ "", 10922 /* CMIC_LEDUP0_DATA_RAM162 */ "", 10923 /* CMIC_LEDUP0_DATA_RAM163 */ "", 10924 /* CMIC_LEDUP0_DATA_RAM164 */ "", 10925 /* CMIC_LEDUP0_DATA_RAM165 */ "", 10926 /* CMIC_LEDUP0_DATA_RAM166 */ "", 10927 /* CMIC_LEDUP0_DATA_RAM167 */ "", 10928 /* CMIC_LEDUP0_DATA_RAM168 */ "", 10929 /* CMIC_LEDUP0_DATA_RAM169 */ "", 10930 /* CMIC_LEDUP0_DATA_RAM170 */ "", 10931 /* CMIC_LEDUP0_DATA_RAM171 */ "", 10932 /* CMIC_LEDUP0_DATA_RAM172 */ "", 10933 /* CMIC_LEDUP0_DATA_RAM173 */ "", 10934 /* CMIC_LEDUP0_DATA_RAM174 */ "", 10935 /* CMIC_LEDUP0_DATA_RAM175 */ "", 10936 /* CMIC_LEDUP0_DATA_RAM176 */ "", 10937 /* CMIC_LEDUP0_DATA_RAM177 */ "", 10938 /* CMIC_LEDUP0_DATA_RAM178 */ "", 10939 /* CMIC_LEDUP0_DATA_RAM179 */ "", 10940 /* CMIC_LEDUP0_DATA_RAM180 */ "", 10941 /* CMIC_LEDUP0_DATA_RAM181 */ "", 10942 /* CMIC_LEDUP0_DATA_RAM182 */ "", 10943 /* CMIC_LEDUP0_DATA_RAM183 */ "", 10944 /* CMIC_LEDUP0_DATA_RAM184 */ "", 10945 /* CMIC_LEDUP0_DATA_RAM185 */ "", 10946 /* CMIC_LEDUP0_DATA_RAM186 */ "", 10947 /* CMIC_LEDUP0_DATA_RAM187 */ "", 10948 /* CMIC_LEDUP0_DATA_RAM188 */ "", 10949 /* CMIC_LEDUP0_DATA_RAM189 */ "", 10950 /* CMIC_LEDUP0_DATA_RAM190 */ "", 10951 /* CMIC_LEDUP0_DATA_RAM191 */ "", 10952 /* CMIC_LEDUP0_DATA_RAM192 */ "", 10953 /* CMIC_LEDUP0_DATA_RAM193 */ "", 10954 /* CMIC_LEDUP0_DATA_RAM194 */ "", 10955 /* CMIC_LEDUP0_DATA_RAM195 */ "", 10956 /* CMIC_LEDUP0_DATA_RAM196 */ "", 10957 /* CMIC_LEDUP0_DATA_RAM197 */ "", 10958 /* CMIC_LEDUP0_DATA_RAM198 */ "", 10959 /* CMIC_LEDUP0_DATA_RAM199 */ "", 10960 /* CMIC_LEDUP0_DATA_RAM200 */ "", 10961 /* CMIC_LEDUP0_DATA_RAM201 */ "", 10962 /* CMIC_LEDUP0_DATA_RAM202 */ "", 10963 /* CMIC_LEDUP0_DATA_RAM203 */ "", 10964 /* CMIC_LEDUP0_DATA_RAM204 */ "", 10965 /* CMIC_LEDUP0_DATA_RAM205 */ "", 10966 /* CMIC_LEDUP0_DATA_RAM206 */ "", 10967 /* CMIC_LEDUP0_DATA_RAM207 */ "", 10968 /* CMIC_LEDUP0_DATA_RAM208 */ "", 10969 /* CMIC_LEDUP0_DATA_RAM209 */ "", 10970 /* CMIC_LEDUP0_DATA_RAM210 */ "", 10971 /* CMIC_LEDUP0_DATA_RAM211 */ "", 10972 /* CMIC_LEDUP0_DATA_RAM212 */ "", 10973 /* CMIC_LEDUP0_DATA_RAM213 */ "", 10974 /* CMIC_LEDUP0_DATA_RAM214 */ "", 10975 /* CMIC_LEDUP0_DATA_RAM215 */ "", 10976 /* CMIC_LEDUP0_DATA_RAM216 */ "", 10977 /* CMIC_LEDUP0_DATA_RAM217 */ "", 10978 /* CMIC_LEDUP0_DATA_RAM218 */ "", 10979 /* CMIC_LEDUP0_DATA_RAM219 */ "", 10980 /* CMIC_LEDUP0_DATA_RAM220 */ "", 10981 /* CMIC_LEDUP0_DATA_RAM221 */ "", 10982 /* CMIC_LEDUP0_DATA_RAM222 */ "", 10983 /* CMIC_LEDUP0_DATA_RAM223 */ "", 10984 /* CMIC_LEDUP0_DATA_RAM224 */ "", 10985 /* CMIC_LEDUP0_DATA_RAM225 */ "", 10986 /* CMIC_LEDUP0_DATA_RAM226 */ "", 10987 /* CMIC_LEDUP0_DATA_RAM227 */ "", 10988 /* CMIC_LEDUP0_DATA_RAM228 */ "", 10989 /* CMIC_LEDUP0_DATA_RAM229 */ "", 10990 /* CMIC_LEDUP0_DATA_RAM230 */ "", 10991 /* CMIC_LEDUP0_DATA_RAM231 */ "", 10992 /* CMIC_LEDUP0_DATA_RAM232 */ "", 10993 /* CMIC_LEDUP0_DATA_RAM233 */ "", 10994 /* CMIC_LEDUP0_DATA_RAM234 */ "", 10995 /* CMIC_LEDUP0_DATA_RAM235 */ "", 10996 /* CMIC_LEDUP0_DATA_RAM236 */ "", 10997 /* CMIC_LEDUP0_DATA_RAM237 */ "", 10998 /* CMIC_LEDUP0_DATA_RAM238 */ "", 10999 /* CMIC_LEDUP0_DATA_RAM239 */ "", 11000 /* CMIC_LEDUP0_DATA_RAM240 */ "", 11001 /* CMIC_LEDUP0_DATA_RAM241 */ "", 11002 /* CMIC_LEDUP0_DATA_RAM242 */ "", 11003 /* CMIC_LEDUP0_DATA_RAM243 */ "", 11004 /* CMIC_LEDUP0_DATA_RAM244 */ "", 11005 /* CMIC_LEDUP0_DATA_RAM245 */ "", 11006 /* CMIC_LEDUP0_DATA_RAM246 */ "", 11007 /* CMIC_LEDUP0_DATA_RAM247 */ "", 11008 /* CMIC_LEDUP0_DATA_RAM248 */ "", 11009 /* CMIC_LEDUP0_DATA_RAM249 */ "", 11010 /* CMIC_LEDUP0_DATA_RAM250 */ "", 11011 /* CMIC_LEDUP0_DATA_RAM251 */ "", 11012 /* CMIC_LEDUP0_DATA_RAM252 */ "", 11013 /* CMIC_LEDUP0_DATA_RAM253 */ "", 11014 /* CMIC_LEDUP0_DATA_RAM254 */ "", 11015 /* CMIC_LEDUP0_DATA_RAM255 */ "", 11016 /* CMIC_LEDUP0_ECC_CONFIG */ "", 11017 /* CMIC_LEDUP0_ECC_INTR */ "", 11018 /* CMIC_LEDUP0_ECC_INTR_CLR */ "", 11019 /* CMIC_LEDUP0_ECC_INTR_ENABLE */ "", 11020 /* CMIC_LEDUP0_ECC_STATUS */ "", 11021 /* CMIC_LEDUP0_PORT_ORDER_REMAP_0_3 */ "", 11022 /* CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 */ "", 11023 /* CMIC_LEDUP0_PORT_ORDER_REMAP_16_19 */ "", 11024 /* CMIC_LEDUP0_PORT_ORDER_REMAP_20_23 */ "", 11025 /* CMIC_LEDUP0_PORT_ORDER_REMAP_24_27 */ "", 11026 /* CMIC_LEDUP0_PORT_ORDER_REMAP_28_31 */ "", 11027 /* CMIC_LEDUP0_PORT_ORDER_REMAP_32_35 */ "", 11028 /* CMIC_LEDUP0_PORT_ORDER_REMAP_36_39 */ "", 11029 /* CMIC_LEDUP0_PORT_ORDER_REMAP_40_43 */ "", 11030 /* CMIC_LEDUP0_PORT_ORDER_REMAP_44_47 */ "", 11031 /* CMIC_LEDUP0_PORT_ORDER_REMAP_48_51 */ "", 11032 /* CMIC_LEDUP0_PORT_ORDER_REMAP_4_7 */ "", 11033 /* CMIC_LEDUP0_PORT_ORDER_REMAP_52_55 */ "", 11034 /* CMIC_LEDUP0_PORT_ORDER_REMAP_56_59 */ "", 11035 /* CMIC_LEDUP0_PORT_ORDER_REMAP_60_63 */ "", 11036 /* CMIC_LEDUP0_PORT_ORDER_REMAP_8_11 */ "", 11037 /* CMIC_LEDUP0_PROGRAM_RAM */ "", 11038 /* CMIC_LEDUP0_PROGRAM_RAM0 */ "", 11039 /* CMIC_LEDUP0_PROGRAM_RAM1 */ "", 11040 /* CMIC_LEDUP0_PROGRAM_RAM2 */ "", 11041 /* CMIC_LEDUP0_PROGRAM_RAM3 */ "", 11042 /* CMIC_LEDUP0_PROGRAM_RAM4 */ "", 11043 /* CMIC_LEDUP0_PROGRAM_RAM5 */ "", 11044 /* CMIC_LEDUP0_PROGRAM_RAM6 */ "", 11045 /* CMIC_LEDUP0_PROGRAM_RAM7 */ "", 11046 /* CMIC_LEDUP0_PROGRAM_RAM8 */ "", 11047 /* CMIC_LEDUP0_PROGRAM_RAM9 */ "", 11048 /* CMIC_LEDUP0_PROGRAM_RAM10 */ "", 11049 /* CMIC_LEDUP0_PROGRAM_RAM11 */ "", 11050 /* CMIC_LEDUP0_PROGRAM_RAM12 */ "", 11051 /* CMIC_LEDUP0_PROGRAM_RAM13 */ "", 11052 /* CMIC_LEDUP0_PROGRAM_RAM14 */ "", 11053 /* CMIC_LEDUP0_PROGRAM_RAM15 */ "", 11054 /* CMIC_LEDUP0_PROGRAM_RAM16 */ "", 11055 /* CMIC_LEDUP0_PROGRAM_RAM17 */ "", 11056 /* CMIC_LEDUP0_PROGRAM_RAM18 */ "", 11057 /* CMIC_LEDUP0_PROGRAM_RAM19 */ "", 11058 /* CMIC_LEDUP0_PROGRAM_RAM20 */ "", 11059 /* CMIC_LEDUP0_PROGRAM_RAM21 */ "", 11060 /* CMIC_LEDUP0_PROGRAM_RAM22 */ "", 11061 /* CMIC_LEDUP0_PROGRAM_RAM23 */ "", 11062 /* CMIC_LEDUP0_PROGRAM_RAM24 */ "", 11063 /* CMIC_LEDUP0_PROGRAM_RAM25 */ "", 11064 /* CMIC_LEDUP0_PROGRAM_RAM26 */ "", 11065 /* CMIC_LEDUP0_PROGRAM_RAM27 */ "", 11066 /* CMIC_LEDUP0_PROGRAM_RAM28 */ "", 11067 /* CMIC_LEDUP0_PROGRAM_RAM29 */ "", 11068 /* CMIC_LEDUP0_PROGRAM_RAM30 */ "", 11069 /* CMIC_LEDUP0_PROGRAM_RAM31 */ "", 11070 /* CMIC_LEDUP0_PROGRAM_RAM32 */ "", 11071 /* CMIC_LEDUP0_PROGRAM_RAM33 */ "", 11072 /* CMIC_LEDUP0_PROGRAM_RAM34 */ "", 11073 /* CMIC_LEDUP0_PROGRAM_RAM35 */ "", 11074 /* CMIC_LEDUP0_PROGRAM_RAM36 */ "", 11075 /* CMIC_LEDUP0_PROGRAM_RAM37 */ "", 11076 /* CMIC_LEDUP0_PROGRAM_RAM38 */ "", 11077 /* CMIC_LEDUP0_PROGRAM_RAM39 */ "", 11078 /* CMIC_LEDUP0_PROGRAM_RAM40 */ "", 11079 /* CMIC_LEDUP0_PROGRAM_RAM41 */ "", 11080 /* CMIC_LEDUP0_PROGRAM_RAM42 */ "", 11081 /* CMIC_LEDUP0_PROGRAM_RAM43 */ "", 11082 /* CMIC_LEDUP0_PROGRAM_RAM44 */ "", 11083 /* CMIC_LEDUP0_PROGRAM_RAM45 */ "", 11084 /* CMIC_LEDUP0_PROGRAM_RAM46 */ "", 11085 /* CMIC_LEDUP0_PROGRAM_RAM47 */ "", 11086 /* CMIC_LEDUP0_PROGRAM_RAM48 */ "", 11087 /* CMIC_LEDUP0_PROGRAM_RAM49 */ "", 11088 /* CMIC_LEDUP0_PROGRAM_RAM50 */ "", 11089 /* CMIC_LEDUP0_PROGRAM_RAM51 */ "", 11090 /* CMIC_LEDUP0_PROGRAM_RAM52 */ "", 11091 /* CMIC_LEDUP0_PROGRAM_RAM53 */ "", 11092 /* CMIC_LEDUP0_PROGRAM_RAM54 */ "", 11093 /* CMIC_LEDUP0_PROGRAM_RAM55 */ "", 11094 /* CMIC_LEDUP0_PROGRAM_RAM56 */ "", 11095 /* CMIC_LEDUP0_PROGRAM_RAM57 */ "", 11096 /* CMIC_LEDUP0_PROGRAM_RAM58 */ "", 11097 /* CMIC_LEDUP0_PROGRAM_RAM59 */ "", 11098 /* CMIC_LEDUP0_PROGRAM_RAM60 */ "", 11099 /* CMIC_LEDUP0_PROGRAM_RAM61 */ "", 11100 /* CMIC_LEDUP0_PROGRAM_RAM62 */ "", 11101 /* CMIC_LEDUP0_PROGRAM_RAM63 */ "", 11102 /* CMIC_LEDUP0_PROGRAM_RAM64 */ "", 11103 /* CMIC_LEDUP0_PROGRAM_RAM65 */ "", 11104 /* CMIC_LEDUP0_PROGRAM_RAM66 */ "", 11105 /* CMIC_LEDUP0_PROGRAM_RAM67 */ "", 11106 /* CMIC_LEDUP0_PROGRAM_RAM68 */ "", 11107 /* CMIC_LEDUP0_PROGRAM_RAM69 */ "", 11108 /* CMIC_LEDUP0_PROGRAM_RAM70 */ "", 11109 /* CMIC_LEDUP0_PROGRAM_RAM71 */ "", 11110 /* CMIC_LEDUP0_PROGRAM_RAM72 */ "", 11111 /* CMIC_LEDUP0_PROGRAM_RAM73 */ "", 11112 /* CMIC_LEDUP0_PROGRAM_RAM74 */ "", 11113 /* CMIC_LEDUP0_PROGRAM_RAM75 */ "", 11114 /* CMIC_LEDUP0_PROGRAM_RAM76 */ "", 11115 /* CMIC_LEDUP0_PROGRAM_RAM77 */ "", 11116 /* CMIC_LEDUP0_PROGRAM_RAM78 */ "", 11117 /* CMIC_LEDUP0_PROGRAM_RAM79 */ "", 11118 /* CMIC_LEDUP0_PROGRAM_RAM80 */ "", 11119 /* CMIC_LEDUP0_PROGRAM_RAM81 */ "", 11120 /* CMIC_LEDUP0_PROGRAM_RAM82 */ "", 11121 /* CMIC_LEDUP0_PROGRAM_RAM83 */ "", 11122 /* CMIC_LEDUP0_PROGRAM_RAM84 */ "", 11123 /* CMIC_LEDUP0_PROGRAM_RAM85 */ "", 11124 /* CMIC_LEDUP0_PROGRAM_RAM86 */ "", 11125 /* CMIC_LEDUP0_PROGRAM_RAM87 */ "", 11126 /* CMIC_LEDUP0_PROGRAM_RAM88 */ "", 11127 /* CMIC_LEDUP0_PROGRAM_RAM89 */ "", 11128 /* CMIC_LEDUP0_PROGRAM_RAM90 */ "", 11129 /* CMIC_LEDUP0_PROGRAM_RAM91 */ "", 11130 /* CMIC_LEDUP0_PROGRAM_RAM92 */ "", 11131 /* CMIC_LEDUP0_PROGRAM_RAM93 */ "", 11132 /* CMIC_LEDUP0_PROGRAM_RAM94 */ "", 11133 /* CMIC_LEDUP0_PROGRAM_RAM95 */ "", 11134 /* CMIC_LEDUP0_PROGRAM_RAM96 */ "", 11135 /* CMIC_LEDUP0_PROGRAM_RAM97 */ "", 11136 /* CMIC_LEDUP0_PROGRAM_RAM98 */ "", 11137 /* CMIC_LEDUP0_PROGRAM_RAM99 */ "", 11138 /* CMIC_LEDUP0_PROGRAM_RAM100 */ "", 11139 /* CMIC_LEDUP0_PROGRAM_RAM101 */ "", 11140 /* CMIC_LEDUP0_PROGRAM_RAM102 */ "", 11141 /* CMIC_LEDUP0_PROGRAM_RAM103 */ "", 11142 /* CMIC_LEDUP0_PROGRAM_RAM104 */ "", 11143 /* CMIC_LEDUP0_PROGRAM_RAM105 */ "", 11144 /* CMIC_LEDUP0_PROGRAM_RAM106 */ "", 11145 /* CMIC_LEDUP0_PROGRAM_RAM107 */ "", 11146 /* CMIC_LEDUP0_PROGRAM_RAM108 */ "", 11147 /* CMIC_LEDUP0_PROGRAM_RAM109 */ "", 11148 /* CMIC_LEDUP0_PROGRAM_RAM110 */ "", 11149 /* CMIC_LEDUP0_PROGRAM_RAM111 */ "", 11150 /* CMIC_LEDUP0_PROGRAM_RAM112 */ "", 11151 /* CMIC_LEDUP0_PROGRAM_RAM113 */ "", 11152 /* CMIC_LEDUP0_PROGRAM_RAM114 */ "", 11153 /* CMIC_LEDUP0_PROGRAM_RAM115 */ "", 11154 /* CMIC_LEDUP0_PROGRAM_RAM116 */ "", 11155 /* CMIC_LEDUP0_PROGRAM_RAM117 */ "", 11156 /* CMIC_LEDUP0_PROGRAM_RAM118 */ "", 11157 /* CMIC_LEDUP0_PROGRAM_RAM119 */ "", 11158 /* CMIC_LEDUP0_PROGRAM_RAM120 */ "", 11159 /* CMIC_LEDUP0_PROGRAM_RAM121 */ "", 11160 /* CMIC_LEDUP0_PROGRAM_RAM122 */ "", 11161 /* CMIC_LEDUP0_PROGRAM_RAM123 */ "", 11162 /* CMIC_LEDUP0_PROGRAM_RAM124 */ "", 11163 /* CMIC_LEDUP0_PROGRAM_RAM125 */ "", 11164 /* CMIC_LEDUP0_PROGRAM_RAM126 */ "", 11165 /* CMIC_LEDUP0_PROGRAM_RAM127 */ "", 11166 /* CMIC_LEDUP0_PROGRAM_RAM128 */ "", 11167 /* CMIC_LEDUP0_PROGRAM_RAM129 */ "", 11168 /* CMIC_LEDUP0_PROGRAM_RAM130 */ "", 11169 /* CMIC_LEDUP0_PROGRAM_RAM131 */ "", 11170 /* CMIC_LEDUP0_PROGRAM_RAM132 */ "", 11171 /* CMIC_LEDUP0_PROGRAM_RAM133 */ "", 11172 /* CMIC_LEDUP0_PROGRAM_RAM134 */ "", 11173 /* CMIC_LEDUP0_PROGRAM_RAM135 */ "", 11174 /* CMIC_LEDUP0_PROGRAM_RAM136 */ "", 11175 /* CMIC_LEDUP0_PROGRAM_RAM137 */ "", 11176 /* CMIC_LEDUP0_PROGRAM_RAM138 */ "", 11177 /* CMIC_LEDUP0_PROGRAM_RAM139 */ "", 11178 /* CMIC_LEDUP0_PROGRAM_RAM140 */ "", 11179 /* CMIC_LEDUP0_PROGRAM_RAM141 */ "", 11180 /* CMIC_LEDUP0_PROGRAM_RAM142 */ "", 11181 /* CMIC_LEDUP0_PROGRAM_RAM143 */ "", 11182 /* CMIC_LEDUP0_PROGRAM_RAM144 */ "", 11183 /* CMIC_LEDUP0_PROGRAM_RAM145 */ "", 11184 /* CMIC_LEDUP0_PROGRAM_RAM146 */ "", 11185 /* CMIC_LEDUP0_PROGRAM_RAM147 */ "", 11186 /* CMIC_LEDUP0_PROGRAM_RAM148 */ "", 11187 /* CMIC_LEDUP0_PROGRAM_RAM149 */ "", 11188 /* CMIC_LEDUP0_PROGRAM_RAM150 */ "", 11189 /* CMIC_LEDUP0_PROGRAM_RAM151 */ "", 11190 /* CMIC_LEDUP0_PROGRAM_RAM152 */ "", 11191 /* CMIC_LEDUP0_PROGRAM_RAM153 */ "", 11192 /* CMIC_LEDUP0_PROGRAM_RAM154 */ "", 11193 /* CMIC_LEDUP0_PROGRAM_RAM155 */ "", 11194 /* CMIC_LEDUP0_PROGRAM_RAM156 */ "", 11195 /* CMIC_LEDUP0_PROGRAM_RAM157 */ "", 11196 /* CMIC_LEDUP0_PROGRAM_RAM158 */ "", 11197 /* CMIC_LEDUP0_PROGRAM_RAM159 */ "", 11198 /* CMIC_LEDUP0_PROGRAM_RAM160 */ "", 11199 /* CMIC_LEDUP0_PROGRAM_RAM161 */ "", 11200 /* CMIC_LEDUP0_PROGRAM_RAM162 */ "", 11201 /* CMIC_LEDUP0_PROGRAM_RAM163 */ "", 11202 /* CMIC_LEDUP0_PROGRAM_RAM164 */ "", 11203 /* CMIC_LEDUP0_PROGRAM_RAM165 */ "", 11204 /* CMIC_LEDUP0_PROGRAM_RAM166 */ "", 11205 /* CMIC_LEDUP0_PROGRAM_RAM167 */ "", 11206 /* CMIC_LEDUP0_PROGRAM_RAM168 */ "", 11207 /* CMIC_LEDUP0_PROGRAM_RAM169 */ "", 11208 /* CMIC_LEDUP0_PROGRAM_RAM170 */ "", 11209 /* CMIC_LEDUP0_PROGRAM_RAM171 */ "", 11210 /* CMIC_LEDUP0_PROGRAM_RAM172 */ "", 11211 /* CMIC_LEDUP0_PROGRAM_RAM173 */ "", 11212 /* CMIC_LEDUP0_PROGRAM_RAM174 */ "", 11213 /* CMIC_LEDUP0_PROGRAM_RAM175 */ "", 11214 /* CMIC_LEDUP0_PROGRAM_RAM176 */ "", 11215 /* CMIC_LEDUP0_PROGRAM_RAM177 */ "", 11216 /* CMIC_LEDUP0_PROGRAM_RAM178 */ "", 11217 /* CMIC_LEDUP0_PROGRAM_RAM179 */ "", 11218 /* CMIC_LEDUP0_PROGRAM_RAM180 */ "", 11219 /* CMIC_LEDUP0_PROGRAM_RAM181 */ "", 11220 /* CMIC_LEDUP0_PROGRAM_RAM182 */ "", 11221 /* CMIC_LEDUP0_PROGRAM_RAM183 */ "", 11222 /* CMIC_LEDUP0_PROGRAM_RAM184 */ "", 11223 /* CMIC_LEDUP0_PROGRAM_RAM185 */ "", 11224 /* CMIC_LEDUP0_PROGRAM_RAM186 */ "", 11225 /* CMIC_LEDUP0_PROGRAM_RAM187 */ "", 11226 /* CMIC_LEDUP0_PROGRAM_RAM188 */ "", 11227 /* CMIC_LEDUP0_PROGRAM_RAM189 */ "", 11228 /* CMIC_LEDUP0_PROGRAM_RAM190 */ "", 11229 /* CMIC_LEDUP0_PROGRAM_RAM191 */ "", 11230 /* CMIC_LEDUP0_PROGRAM_RAM192 */ "", 11231 /* CMIC_LEDUP0_PROGRAM_RAM193 */ "", 11232 /* CMIC_LEDUP0_PROGRAM_RAM194 */ "", 11233 /* CMIC_LEDUP0_PROGRAM_RAM195 */ "", 11234 /* CMIC_LEDUP0_PROGRAM_RAM196 */ "", 11235 /* CMIC_LEDUP0_PROGRAM_RAM197 */ "", 11236 /* CMIC_LEDUP0_PROGRAM_RAM198 */ "", 11237 /* CMIC_LEDUP0_PROGRAM_RAM199 */ "", 11238 /* CMIC_LEDUP0_PROGRAM_RAM200 */ "", 11239 /* CMIC_LEDUP0_PROGRAM_RAM201 */ "", 11240 /* CMIC_LEDUP0_PROGRAM_RAM202 */ "", 11241 /* CMIC_LEDUP0_PROGRAM_RAM203 */ "", 11242 /* CMIC_LEDUP0_PROGRAM_RAM204 */ "", 11243 /* CMIC_LEDUP0_PROGRAM_RAM205 */ "", 11244 /* CMIC_LEDUP0_PROGRAM_RAM206 */ "", 11245 /* CMIC_LEDUP0_PROGRAM_RAM207 */ "", 11246 /* CMIC_LEDUP0_PROGRAM_RAM208 */ "", 11247 /* CMIC_LEDUP0_PROGRAM_RAM209 */ "", 11248 /* CMIC_LEDUP0_PROGRAM_RAM210 */ "", 11249 /* CMIC_LEDUP0_PROGRAM_RAM211 */ "", 11250 /* CMIC_LEDUP0_PROGRAM_RAM212 */ "", 11251 /* CMIC_LEDUP0_PROGRAM_RAM213 */ "", 11252 /* CMIC_LEDUP0_PROGRAM_RAM214 */ "", 11253 /* CMIC_LEDUP0_PROGRAM_RAM215 */ "", 11254 /* CMIC_LEDUP0_PROGRAM_RAM216 */ "", 11255 /* CMIC_LEDUP0_PROGRAM_RAM217 */ "", 11256 /* CMIC_LEDUP0_PROGRAM_RAM218 */ "", 11257 /* CMIC_LEDUP0_PROGRAM_RAM219 */ "", 11258 /* CMIC_LEDUP0_PROGRAM_RAM220 */ "", 11259 /* CMIC_LEDUP0_PROGRAM_RAM221 */ "", 11260 /* CMIC_LEDUP0_PROGRAM_RAM222 */ "", 11261 /* CMIC_LEDUP0_PROGRAM_RAM223 */ "", 11262 /* CMIC_LEDUP0_PROGRAM_RAM224 */ "", 11263 /* CMIC_LEDUP0_PROGRAM_RAM225 */ "", 11264 /* CMIC_LEDUP0_PROGRAM_RAM226 */ "", 11265 /* CMIC_LEDUP0_PROGRAM_RAM227 */ "", 11266 /* CMIC_LEDUP0_PROGRAM_RAM228 */ "", 11267 /* CMIC_LEDUP0_PROGRAM_RAM229 */ "", 11268 /* CMIC_LEDUP0_PROGRAM_RAM230 */ "", 11269 /* CMIC_LEDUP0_PROGRAM_RAM231 */ "", 11270 /* CMIC_LEDUP0_PROGRAM_RAM232 */ "", 11271 /* CMIC_LEDUP0_PROGRAM_RAM233 */ "", 11272 /* CMIC_LEDUP0_PROGRAM_RAM234 */ "", 11273 /* CMIC_LEDUP0_PROGRAM_RAM235 */ "", 11274 /* CMIC_LEDUP0_PROGRAM_RAM236 */ "", 11275 /* CMIC_LEDUP0_PROGRAM_RAM237 */ "", 11276 /* CMIC_LEDUP0_PROGRAM_RAM238 */ "", 11277 /* CMIC_LEDUP0_PROGRAM_RAM239 */ "", 11278 /* CMIC_LEDUP0_PROGRAM_RAM240 */ "", 11279 /* CMIC_LEDUP0_PROGRAM_RAM241 */ "", 11280 /* CMIC_LEDUP0_PROGRAM_RAM242 */ "", 11281 /* CMIC_LEDUP0_PROGRAM_RAM243 */ "", 11282 /* CMIC_LEDUP0_PROGRAM_RAM244 */ "", 11283 /* CMIC_LEDUP0_PROGRAM_RAM245 */ "", 11284 /* CMIC_LEDUP0_PROGRAM_RAM246 */ "", 11285 /* CMIC_LEDUP0_PROGRAM_RAM247 */ "", 11286 /* CMIC_LEDUP0_PROGRAM_RAM248 */ "", 11287 /* CMIC_LEDUP0_PROGRAM_RAM249 */ "", 11288 /* CMIC_LEDUP0_PROGRAM_RAM250 */ "", 11289 /* CMIC_LEDUP0_PROGRAM_RAM251 */ "", 11290 /* CMIC_LEDUP0_PROGRAM_RAM252 */ "", 11291 /* CMIC_LEDUP0_PROGRAM_RAM253 */ "", 11292 /* CMIC_LEDUP0_PROGRAM_RAM254 */ "", 11293 /* CMIC_LEDUP0_PROGRAM_RAM255 */ "", 11294 /* CMIC_LEDUP0_SCANCHAIN_ASSEMBLY_ST_ADDR */ "", 11295 /* CMIC_LEDUP0_SCANOUT_COUNT_UPPER */ "", 11296 /* CMIC_LEDUP0_STATUS */ "", 11297 /* CMIC_LEDUP0_TM_CONTROL */ "", 11298 /* CMIC_LEDUP1_CLK_DIV */ "", 11299 /* CMIC_LEDUP1_CLK_PARAMS */ "", 11300 /* CMIC_LEDUP1_CTRL */ "", 11301 /* CMIC_LEDUP1_DATA_RAM */ "", 11302 /* CMIC_LEDUP1_DATA_RAM0 */ "", 11303 /* CMIC_LEDUP1_DATA_RAM1 */ "", 11304 /* CMIC_LEDUP1_DATA_RAM2 */ "", 11305 /* CMIC_LEDUP1_DATA_RAM3 */ "", 11306 /* CMIC_LEDUP1_DATA_RAM4 */ "", 11307 /* CMIC_LEDUP1_DATA_RAM5 */ "", 11308 /* CMIC_LEDUP1_DATA_RAM6 */ "", 11309 /* CMIC_LEDUP1_DATA_RAM7 */ "", 11310 /* CMIC_LEDUP1_DATA_RAM8 */ "", 11311 /* CMIC_LEDUP1_DATA_RAM9 */ "", 11312 /* CMIC_LEDUP1_DATA_RAM10 */ "", 11313 /* CMIC_LEDUP1_DATA_RAM11 */ "", 11314 /* CMIC_LEDUP1_DATA_RAM12 */ "", 11315 /* CMIC_LEDUP1_DATA_RAM13 */ "", 11316 /* CMIC_LEDUP1_DATA_RAM14 */ "", 11317 /* CMIC_LEDUP1_DATA_RAM15 */ "", 11318 /* CMIC_LEDUP1_DATA_RAM16 */ "", 11319 /* CMIC_LEDUP1_DATA_RAM17 */ "", 11320 /* CMIC_LEDUP1_DATA_RAM18 */ "", 11321 /* CMIC_LEDUP1_DATA_RAM19 */ "", 11322 /* CMIC_LEDUP1_DATA_RAM20 */ "", 11323 /* CMIC_LEDUP1_DATA_RAM21 */ "", 11324 /* CMIC_LEDUP1_DATA_RAM22 */ "", 11325 /* CMIC_LEDUP1_DATA_RAM23 */ "", 11326 /* CMIC_LEDUP1_DATA_RAM24 */ "", 11327 /* CMIC_LEDUP1_DATA_RAM25 */ "", 11328 /* CMIC_LEDUP1_DATA_RAM26 */ "", 11329 /* CMIC_LEDUP1_DATA_RAM27 */ "", 11330 /* CMIC_LEDUP1_DATA_RAM28 */ "", 11331 /* CMIC_LEDUP1_DATA_RAM29 */ "", 11332 /* CMIC_LEDUP1_DATA_RAM30 */ "", 11333 /* CMIC_LEDUP1_DATA_RAM31 */ "", 11334 /* CMIC_LEDUP1_DATA_RAM32 */ "", 11335 /* CMIC_LEDUP1_DATA_RAM33 */ "", 11336 /* CMIC_LEDUP1_DATA_RAM34 */ "", 11337 /* CMIC_LEDUP1_DATA_RAM35 */ "", 11338 /* CMIC_LEDUP1_DATA_RAM36 */ "", 11339 /* CMIC_LEDUP1_DATA_RAM37 */ "", 11340 /* CMIC_LEDUP1_DATA_RAM38 */ "", 11341 /* CMIC_LEDUP1_DATA_RAM39 */ "", 11342 /* CMIC_LEDUP1_DATA_RAM40 */ "", 11343 /* CMIC_LEDUP1_DATA_RAM41 */ "", 11344 /* CMIC_LEDUP1_DATA_RAM42 */ "", 11345 /* CMIC_LEDUP1_DATA_RAM43 */ "", 11346 /* CMIC_LEDUP1_DATA_RAM44 */ "", 11347 /* CMIC_LEDUP1_DATA_RAM45 */ "", 11348 /* CMIC_LEDUP1_DATA_RAM46 */ "", 11349 /* CMIC_LEDUP1_DATA_RAM47 */ "", 11350 /* CMIC_LEDUP1_DATA_RAM48 */ "", 11351 /* CMIC_LEDUP1_DATA_RAM49 */ "", 11352 /* CMIC_LEDUP1_DATA_RAM50 */ "", 11353 /* CMIC_LEDUP1_DATA_RAM51 */ "", 11354 /* CMIC_LEDUP1_DATA_RAM52 */ "", 11355 /* CMIC_LEDUP1_DATA_RAM53 */ "", 11356 /* CMIC_LEDUP1_DATA_RAM54 */ "", 11357 /* CMIC_LEDUP1_DATA_RAM55 */ "", 11358 /* CMIC_LEDUP1_DATA_RAM56 */ "", 11359 /* CMIC_LEDUP1_DATA_RAM57 */ "", 11360 /* CMIC_LEDUP1_DATA_RAM58 */ "", 11361 /* CMIC_LEDUP1_DATA_RAM59 */ "", 11362 /* CMIC_LEDUP1_DATA_RAM60 */ "", 11363 /* CMIC_LEDUP1_DATA_RAM61 */ "", 11364 /* CMIC_LEDUP1_DATA_RAM62 */ "", 11365 /* CMIC_LEDUP1_DATA_RAM63 */ "", 11366 /* CMIC_LEDUP1_DATA_RAM64 */ "", 11367 /* CMIC_LEDUP1_DATA_RAM65 */ "", 11368 /* CMIC_LEDUP1_DATA_RAM66 */ "", 11369 /* CMIC_LEDUP1_DATA_RAM67 */ "", 11370 /* CMIC_LEDUP1_DATA_RAM68 */ "", 11371 /* CMIC_LEDUP1_DATA_RAM69 */ "", 11372 /* CMIC_LEDUP1_DATA_RAM70 */ "", 11373 /* CMIC_LEDUP1_DATA_RAM71 */ "", 11374 /* CMIC_LEDUP1_DATA_RAM72 */ "", 11375 /* CMIC_LEDUP1_DATA_RAM73 */ "", 11376 /* CMIC_LEDUP1_DATA_RAM74 */ "", 11377 /* CMIC_LEDUP1_DATA_RAM75 */ "", 11378 /* CMIC_LEDUP1_DATA_RAM76 */ "", 11379 /* CMIC_LEDUP1_DATA_RAM77 */ "", 11380 /* CMIC_LEDUP1_DATA_RAM78 */ "", 11381 /* CMIC_LEDUP1_DATA_RAM79 */ "", 11382 /* CMIC_LEDUP1_DATA_RAM80 */ "", 11383 /* CMIC_LEDUP1_DATA_RAM81 */ "", 11384 /* CMIC_LEDUP1_DATA_RAM82 */ "", 11385 /* CMIC_LEDUP1_DATA_RAM83 */ "", 11386 /* CMIC_LEDUP1_DATA_RAM84 */ "", 11387 /* CMIC_LEDUP1_DATA_RAM85 */ "", 11388 /* CMIC_LEDUP1_DATA_RAM86 */ "", 11389 /* CMIC_LEDUP1_DATA_RAM87 */ "", 11390 /* CMIC_LEDUP1_DATA_RAM88 */ "", 11391 /* CMIC_LEDUP1_DATA_RAM89 */ "", 11392 /* CMIC_LEDUP1_DATA_RAM90 */ "", 11393 /* CMIC_LEDUP1_DATA_RAM91 */ "", 11394 /* CMIC_LEDUP1_DATA_RAM92 */ "", 11395 /* CMIC_LEDUP1_DATA_RAM93 */ "", 11396 /* CMIC_LEDUP1_DATA_RAM94 */ "", 11397 /* CMIC_LEDUP1_DATA_RAM95 */ "", 11398 /* CMIC_LEDUP1_DATA_RAM96 */ "", 11399 /* CMIC_LEDUP1_DATA_RAM97 */ "", 11400 /* CMIC_LEDUP1_DATA_RAM98 */ "", 11401 /* CMIC_LEDUP1_DATA_RAM99 */ "", 11402 /* CMIC_LEDUP1_DATA_RAM100 */ "", 11403 /* CMIC_LEDUP1_DATA_RAM101 */ "", 11404 /* CMIC_LEDUP1_DATA_RAM102 */ "", 11405 /* CMIC_LEDUP1_DATA_RAM103 */ "", 11406 /* CMIC_LEDUP1_DATA_RAM104 */ "", 11407 /* CMIC_LEDUP1_DATA_RAM105 */ "", 11408 /* CMIC_LEDUP1_DATA_RAM106 */ "", 11409 /* CMIC_LEDUP1_DATA_RAM107 */ "", 11410 /* CMIC_LEDUP1_DATA_RAM108 */ "", 11411 /* CMIC_LEDUP1_DATA_RAM109 */ "", 11412 /* CMIC_LEDUP1_DATA_RAM110 */ "", 11413 /* CMIC_LEDUP1_DATA_RAM111 */ "", 11414 /* CMIC_LEDUP1_DATA_RAM112 */ "", 11415 /* CMIC_LEDUP1_DATA_RAM113 */ "", 11416 /* CMIC_LEDUP1_DATA_RAM114 */ "", 11417 /* CMIC_LEDUP1_DATA_RAM115 */ "", 11418 /* CMIC_LEDUP1_DATA_RAM116 */ "", 11419 /* CMIC_LEDUP1_DATA_RAM117 */ "", 11420 /* CMIC_LEDUP1_DATA_RAM118 */ "", 11421 /* CMIC_LEDUP1_DATA_RAM119 */ "", 11422 /* CMIC_LEDUP1_DATA_RAM120 */ "", 11423 /* CMIC_LEDUP1_DATA_RAM121 */ "", 11424 /* CMIC_LEDUP1_DATA_RAM122 */ "", 11425 /* CMIC_LEDUP1_DATA_RAM123 */ "", 11426 /* CMIC_LEDUP1_DATA_RAM124 */ "", 11427 /* CMIC_LEDUP1_DATA_RAM125 */ "", 11428 /* CMIC_LEDUP1_DATA_RAM126 */ "", 11429 /* CMIC_LEDUP1_DATA_RAM127 */ "", 11430 /* CMIC_LEDUP1_DATA_RAM128 */ "", 11431 /* CMIC_LEDUP1_DATA_RAM129 */ "", 11432 /* CMIC_LEDUP1_DATA_RAM130 */ "", 11433 /* CMIC_LEDUP1_DATA_RAM131 */ "", 11434 /* CMIC_LEDUP1_DATA_RAM132 */ "", 11435 /* CMIC_LEDUP1_DATA_RAM133 */ "", 11436 /* CMIC_LEDUP1_DATA_RAM134 */ "", 11437 /* CMIC_LEDUP1_DATA_RAM135 */ "", 11438 /* CMIC_LEDUP1_DATA_RAM136 */ "", 11439 /* CMIC_LEDUP1_DATA_RAM137 */ "", 11440 /* CMIC_LEDUP1_DATA_RAM138 */ "", 11441 /* CMIC_LEDUP1_DATA_RAM139 */ "", 11442 /* CMIC_LEDUP1_DATA_RAM140 */ "", 11443 /* CMIC_LEDUP1_DATA_RAM141 */ "", 11444 /* CMIC_LEDUP1_DATA_RAM142 */ "", 11445 /* CMIC_LEDUP1_DATA_RAM143 */ "", 11446 /* CMIC_LEDUP1_DATA_RAM144 */ "", 11447 /* CMIC_LEDUP1_DATA_RAM145 */ "", 11448 /* CMIC_LEDUP1_DATA_RAM146 */ "", 11449 /* CMIC_LEDUP1_DATA_RAM147 */ "", 11450 /* CMIC_LEDUP1_DATA_RAM148 */ "", 11451 /* CMIC_LEDUP1_DATA_RAM149 */ "", 11452 /* CMIC_LEDUP1_DATA_RAM150 */ "", 11453 /* CMIC_LEDUP1_DATA_RAM151 */ "", 11454 /* CMIC_LEDUP1_DATA_RAM152 */ "", 11455 /* CMIC_LEDUP1_DATA_RAM153 */ "", 11456 /* CMIC_LEDUP1_DATA_RAM154 */ "", 11457 /* CMIC_LEDUP1_DATA_RAM155 */ "", 11458 /* CMIC_LEDUP1_DATA_RAM156 */ "", 11459 /* CMIC_LEDUP1_DATA_RAM157 */ "", 11460 /* CMIC_LEDUP1_DATA_RAM158 */ "", 11461 /* CMIC_LEDUP1_DATA_RAM159 */ "", 11462 /* CMIC_LEDUP1_DATA_RAM160 */ "", 11463 /* CMIC_LEDUP1_DATA_RAM161 */ "", 11464 /* CMIC_LEDUP1_DATA_RAM162 */ "", 11465 /* CMIC_LEDUP1_DATA_RAM163 */ "", 11466 /* CMIC_LEDUP1_DATA_RAM164 */ "", 11467 /* CMIC_LEDUP1_DATA_RAM165 */ "", 11468 /* CMIC_LEDUP1_DATA_RAM166 */ "", 11469 /* CMIC_LEDUP1_DATA_RAM167 */ "", 11470 /* CMIC_LEDUP1_DATA_RAM168 */ "", 11471 /* CMIC_LEDUP1_DATA_RAM169 */ "", 11472 /* CMIC_LEDUP1_DATA_RAM170 */ "", 11473 /* CMIC_LEDUP1_DATA_RAM171 */ "", 11474 /* CMIC_LEDUP1_DATA_RAM172 */ "", 11475 /* CMIC_LEDUP1_DATA_RAM173 */ "", 11476 /* CMIC_LEDUP1_DATA_RAM174 */ "", 11477 /* CMIC_LEDUP1_DATA_RAM175 */ "", 11478 /* CMIC_LEDUP1_DATA_RAM176 */ "", 11479 /* CMIC_LEDUP1_DATA_RAM177 */ "", 11480 /* CMIC_LEDUP1_DATA_RAM178 */ "", 11481 /* CMIC_LEDUP1_DATA_RAM179 */ "", 11482 /* CMIC_LEDUP1_DATA_RAM180 */ "", 11483 /* CMIC_LEDUP1_DATA_RAM181 */ "", 11484 /* CMIC_LEDUP1_DATA_RAM182 */ "", 11485 /* CMIC_LEDUP1_DATA_RAM183 */ "", 11486 /* CMIC_LEDUP1_DATA_RAM184 */ "", 11487 /* CMIC_LEDUP1_DATA_RAM185 */ "", 11488 /* CMIC_LEDUP1_DATA_RAM186 */ "", 11489 /* CMIC_LEDUP1_DATA_RAM187 */ "", 11490 /* CMIC_LEDUP1_DATA_RAM188 */ "", 11491 /* CMIC_LEDUP1_DATA_RAM189 */ "", 11492 /* CMIC_LEDUP1_DATA_RAM190 */ "", 11493 /* CMIC_LEDUP1_DATA_RAM191 */ "", 11494 /* CMIC_LEDUP1_DATA_RAM192 */ "", 11495 /* CMIC_LEDUP1_DATA_RAM193 */ "", 11496 /* CMIC_LEDUP1_DATA_RAM194 */ "", 11497 /* CMIC_LEDUP1_DATA_RAM195 */ "", 11498 /* CMIC_LEDUP1_DATA_RAM196 */ "", 11499 /* CMIC_LEDUP1_DATA_RAM197 */ "", 11500 /* CMIC_LEDUP1_DATA_RAM198 */ "", 11501 /* CMIC_LEDUP1_DATA_RAM199 */ "", 11502 /* CMIC_LEDUP1_DATA_RAM200 */ "", 11503 /* CMIC_LEDUP1_DATA_RAM201 */ "", 11504 /* CMIC_LEDUP1_DATA_RAM202 */ "", 11505 /* CMIC_LEDUP1_DATA_RAM203 */ "", 11506 /* CMIC_LEDUP1_DATA_RAM204 */ "", 11507 /* CMIC_LEDUP1_DATA_RAM205 */ "", 11508 /* CMIC_LEDUP1_DATA_RAM206 */ "", 11509 /* CMIC_LEDUP1_DATA_RAM207 */ "", 11510 /* CMIC_LEDUP1_DATA_RAM208 */ "", 11511 /* CMIC_LEDUP1_DATA_RAM209 */ "", 11512 /* CMIC_LEDUP1_DATA_RAM210 */ "", 11513 /* CMIC_LEDUP1_DATA_RAM211 */ "", 11514 /* CMIC_LEDUP1_DATA_RAM212 */ "", 11515 /* CMIC_LEDUP1_DATA_RAM213 */ "", 11516 /* CMIC_LEDUP1_DATA_RAM214 */ "", 11517 /* CMIC_LEDUP1_DATA_RAM215 */ "", 11518 /* CMIC_LEDUP1_DATA_RAM216 */ "", 11519 /* CMIC_LEDUP1_DATA_RAM217 */ "", 11520 /* CMIC_LEDUP1_DATA_RAM218 */ "", 11521 /* CMIC_LEDUP1_DATA_RAM219 */ "", 11522 /* CMIC_LEDUP1_DATA_RAM220 */ "", 11523 /* CMIC_LEDUP1_DATA_RAM221 */ "", 11524 /* CMIC_LEDUP1_DATA_RAM222 */ "", 11525 /* CMIC_LEDUP1_DATA_RAM223 */ "", 11526 /* CMIC_LEDUP1_DATA_RAM224 */ "", 11527 /* CMIC_LEDUP1_DATA_RAM225 */ "", 11528 /* CMIC_LEDUP1_DATA_RAM226 */ "", 11529 /* CMIC_LEDUP1_DATA_RAM227 */ "", 11530 /* CMIC_LEDUP1_DATA_RAM228 */ "", 11531 /* CMIC_LEDUP1_DATA_RAM229 */ "", 11532 /* CMIC_LEDUP1_DATA_RAM230 */ "", 11533 /* CMIC_LEDUP1_DATA_RAM231 */ "", 11534 /* CMIC_LEDUP1_DATA_RAM232 */ "", 11535 /* CMIC_LEDUP1_DATA_RAM233 */ "", 11536 /* CMIC_LEDUP1_DATA_RAM234 */ "", 11537 /* CMIC_LEDUP1_DATA_RAM235 */ "", 11538 /* CMIC_LEDUP1_DATA_RAM236 */ "", 11539 /* CMIC_LEDUP1_DATA_RAM237 */ "", 11540 /* CMIC_LEDUP1_DATA_RAM238 */ "", 11541 /* CMIC_LEDUP1_DATA_RAM239 */ "", 11542 /* CMIC_LEDUP1_DATA_RAM240 */ "", 11543 /* CMIC_LEDUP1_DATA_RAM241 */ "", 11544 /* CMIC_LEDUP1_DATA_RAM242 */ "", 11545 /* CMIC_LEDUP1_DATA_RAM243 */ "", 11546 /* CMIC_LEDUP1_DATA_RAM244 */ "", 11547 /* CMIC_LEDUP1_DATA_RAM245 */ "", 11548 /* CMIC_LEDUP1_DATA_RAM246 */ "", 11549 /* CMIC_LEDUP1_DATA_RAM247 */ "", 11550 /* CMIC_LEDUP1_DATA_RAM248 */ "", 11551 /* CMIC_LEDUP1_DATA_RAM249 */ "", 11552 /* CMIC_LEDUP1_DATA_RAM250 */ "", 11553 /* CMIC_LEDUP1_DATA_RAM251 */ "", 11554 /* CMIC_LEDUP1_DATA_RAM252 */ "", 11555 /* CMIC_LEDUP1_DATA_RAM253 */ "", 11556 /* CMIC_LEDUP1_DATA_RAM254 */ "", 11557 /* CMIC_LEDUP1_DATA_RAM255 */ "", 11558 /* CMIC_LEDUP1_ECC_CONFIG */ "", 11559 /* CMIC_LEDUP1_ECC_INTR */ "", 11560 /* CMIC_LEDUP1_ECC_INTR_CLR */ "", 11561 /* CMIC_LEDUP1_ECC_INTR_ENABLE */ "", 11562 /* CMIC_LEDUP1_ECC_STATUS */ "", 11563 /* CMIC_LEDUP1_PORT_ORDER_REMAP_0_3 */ "", 11564 /* CMIC_LEDUP1_PORT_ORDER_REMAP_12_15 */ "", 11565 /* CMIC_LEDUP1_PORT_ORDER_REMAP_16_19 */ "", 11566 /* CMIC_LEDUP1_PORT_ORDER_REMAP_20_23 */ "", 11567 /* CMIC_LEDUP1_PORT_ORDER_REMAP_24_27 */ "", 11568 /* CMIC_LEDUP1_PORT_ORDER_REMAP_28_31 */ "", 11569 /* CMIC_LEDUP1_PORT_ORDER_REMAP_32_35 */ "", 11570 /* CMIC_LEDUP1_PORT_ORDER_REMAP_36_39 */ "", 11571 /* CMIC_LEDUP1_PORT_ORDER_REMAP_40_43 */ "", 11572 /* CMIC_LEDUP1_PORT_ORDER_REMAP_44_47 */ "", 11573 /* CMIC_LEDUP1_PORT_ORDER_REMAP_48_51 */ "", 11574 /* CMIC_LEDUP1_PORT_ORDER_REMAP_4_7 */ "", 11575 /* CMIC_LEDUP1_PORT_ORDER_REMAP_52_55 */ "", 11576 /* CMIC_LEDUP1_PORT_ORDER_REMAP_56_59 */ "", 11577 /* CMIC_LEDUP1_PORT_ORDER_REMAP_60_63 */ "", 11578 /* CMIC_LEDUP1_PORT_ORDER_REMAP_8_11 */ "", 11579 /* CMIC_LEDUP1_PROGRAM_RAM */ "", 11580 /* CMIC_LEDUP1_PROGRAM_RAM0 */ "", 11581 /* CMIC_LEDUP1_PROGRAM_RAM1 */ "", 11582 /* CMIC_LEDUP1_PROGRAM_RAM2 */ "", 11583 /* CMIC_LEDUP1_PROGRAM_RAM3 */ "", 11584 /* CMIC_LEDUP1_PROGRAM_RAM4 */ "", 11585 /* CMIC_LEDUP1_PROGRAM_RAM5 */ "", 11586 /* CMIC_LEDUP1_PROGRAM_RAM6 */ "", 11587 /* CMIC_LEDUP1_PROGRAM_RAM7 */ "", 11588 /* CMIC_LEDUP1_PROGRAM_RAM8 */ "", 11589 /* CMIC_LEDUP1_PROGRAM_RAM9 */ "", 11590 /* CMIC_LEDUP1_PROGRAM_RAM10 */ "", 11591 /* CMIC_LEDUP1_PROGRAM_RAM11 */ "", 11592 /* CMIC_LEDUP1_PROGRAM_RAM12 */ "", 11593 /* CMIC_LEDUP1_PROGRAM_RAM13 */ "", 11594 /* CMIC_LEDUP1_PROGRAM_RAM14 */ "", 11595 /* CMIC_LEDUP1_PROGRAM_RAM15 */ "", 11596 /* CMIC_LEDUP1_PROGRAM_RAM16 */ "", 11597 /* CMIC_LEDUP1_PROGRAM_RAM17 */ "", 11598 /* CMIC_LEDUP1_PROGRAM_RAM18 */ "", 11599 /* CMIC_LEDUP1_PROGRAM_RAM19 */ "", 11600 /* CMIC_LEDUP1_PROGRAM_RAM20 */ "", 11601 /* CMIC_LEDUP1_PROGRAM_RAM21 */ "", 11602 /* CMIC_LEDUP1_PROGRAM_RAM22 */ "", 11603 /* CMIC_LEDUP1_PROGRAM_RAM23 */ "", 11604 /* CMIC_LEDUP1_PROGRAM_RAM24 */ "", 11605 /* CMIC_LEDUP1_PROGRAM_RAM25 */ "", 11606 /* CMIC_LEDUP1_PROGRAM_RAM26 */ "", 11607 /* CMIC_LEDUP1_PROGRAM_RAM27 */ "", 11608 /* CMIC_LEDUP1_PROGRAM_RAM28 */ "", 11609 /* CMIC_LEDUP1_PROGRAM_RAM29 */ "", 11610 /* CMIC_LEDUP1_PROGRAM_RAM30 */ "", 11611 /* CMIC_LEDUP1_PROGRAM_RAM31 */ "", 11612 /* CMIC_LEDUP1_PROGRAM_RAM32 */ "", 11613 /* CMIC_LEDUP1_PROGRAM_RAM33 */ "", 11614 /* CMIC_LEDUP1_PROGRAM_RAM34 */ "", 11615 /* CMIC_LEDUP1_PROGRAM_RAM35 */ "", 11616 /* CMIC_LEDUP1_PROGRAM_RAM36 */ "", 11617 /* CMIC_LEDUP1_PROGRAM_RAM37 */ "", 11618 /* CMIC_LEDUP1_PROGRAM_RAM38 */ "", 11619 /* CMIC_LEDUP1_PROGRAM_RAM39 */ "", 11620 /* CMIC_LEDUP1_PROGRAM_RAM40 */ "", 11621 /* CMIC_LEDUP1_PROGRAM_RAM41 */ "", 11622 /* CMIC_LEDUP1_PROGRAM_RAM42 */ "", 11623 /* CMIC_LEDUP1_PROGRAM_RAM43 */ "", 11624 /* CMIC_LEDUP1_PROGRAM_RAM44 */ "", 11625 /* CMIC_LEDUP1_PROGRAM_RAM45 */ "", 11626 /* CMIC_LEDUP1_PROGRAM_RAM46 */ "", 11627 /* CMIC_LEDUP1_PROGRAM_RAM47 */ "", 11628 /* CMIC_LEDUP1_PROGRAM_RAM48 */ "", 11629 /* CMIC_LEDUP1_PROGRAM_RAM49 */ "", 11630 /* CMIC_LEDUP1_PROGRAM_RAM50 */ "", 11631 /* CMIC_LEDUP1_PROGRAM_RAM51 */ "", 11632 /* CMIC_LEDUP1_PROGRAM_RAM52 */ "", 11633 /* CMIC_LEDUP1_PROGRAM_RAM53 */ "", 11634 /* CMIC_LEDUP1_PROGRAM_RAM54 */ "", 11635 /* CMIC_LEDUP1_PROGRAM_RAM55 */ "", 11636 /* CMIC_LEDUP1_PROGRAM_RAM56 */ "", 11637 /* CMIC_LEDUP1_PROGRAM_RAM57 */ "", 11638 /* CMIC_LEDUP1_PROGRAM_RAM58 */ "", 11639 /* CMIC_LEDUP1_PROGRAM_RAM59 */ "", 11640 /* CMIC_LEDUP1_PROGRAM_RAM60 */ "", 11641 /* CMIC_LEDUP1_PROGRAM_RAM61 */ "", 11642 /* CMIC_LEDUP1_PROGRAM_RAM62 */ "", 11643 /* CMIC_LEDUP1_PROGRAM_RAM63 */ "", 11644 /* CMIC_LEDUP1_PROGRAM_RAM64 */ "", 11645 /* CMIC_LEDUP1_PROGRAM_RAM65 */ "", 11646 /* CMIC_LEDUP1_PROGRAM_RAM66 */ "", 11647 /* CMIC_LEDUP1_PROGRAM_RAM67 */ "", 11648 /* CMIC_LEDUP1_PROGRAM_RAM68 */ "", 11649 /* CMIC_LEDUP1_PROGRAM_RAM69 */ "", 11650 /* CMIC_LEDUP1_PROGRAM_RAM70 */ "", 11651 /* CMIC_LEDUP1_PROGRAM_RAM71 */ "", 11652 /* CMIC_LEDUP1_PROGRAM_RAM72 */ "", 11653 /* CMIC_LEDUP1_PROGRAM_RAM73 */ "", 11654 /* CMIC_LEDUP1_PROGRAM_RAM74 */ "", 11655 /* CMIC_LEDUP1_PROGRAM_RAM75 */ "", 11656 /* CMIC_LEDUP1_PROGRAM_RAM76 */ "", 11657 /* CMIC_LEDUP1_PROGRAM_RAM77 */ "", 11658 /* CMIC_LEDUP1_PROGRAM_RAM78 */ "", 11659 /* CMIC_LEDUP1_PROGRAM_RAM79 */ "", 11660 /* CMIC_LEDUP1_PROGRAM_RAM80 */ "", 11661 /* CMIC_LEDUP1_PROGRAM_RAM81 */ "", 11662 /* CMIC_LEDUP1_PROGRAM_RAM82 */ "", 11663 /* CMIC_LEDUP1_PROGRAM_RAM83 */ "", 11664 /* CMIC_LEDUP1_PROGRAM_RAM84 */ "", 11665 /* CMIC_LEDUP1_PROGRAM_RAM85 */ "", 11666 /* CMIC_LEDUP1_PROGRAM_RAM86 */ "", 11667 /* CMIC_LEDUP1_PROGRAM_RAM87 */ "", 11668 /* CMIC_LEDUP1_PROGRAM_RAM88 */ "", 11669 /* CMIC_LEDUP1_PROGRAM_RAM89 */ "", 11670 /* CMIC_LEDUP1_PROGRAM_RAM90 */ "", 11671 /* CMIC_LEDUP1_PROGRAM_RAM91 */ "", 11672 /* CMIC_LEDUP1_PROGRAM_RAM92 */ "", 11673 /* CMIC_LEDUP1_PROGRAM_RAM93 */ "", 11674 /* CMIC_LEDUP1_PROGRAM_RAM94 */ "", 11675 /* CMIC_LEDUP1_PROGRAM_RAM95 */ "", 11676 /* CMIC_LEDUP1_PROGRAM_RAM96 */ "", 11677 /* CMIC_LEDUP1_PROGRAM_RAM97 */ "", 11678 /* CMIC_LEDUP1_PROGRAM_RAM98 */ "", 11679 /* CMIC_LEDUP1_PROGRAM_RAM99 */ "", 11680 /* CMIC_LEDUP1_PROGRAM_RAM100 */ "", 11681 /* CMIC_LEDUP1_PROGRAM_RAM101 */ "", 11682 /* CMIC_LEDUP1_PROGRAM_RAM102 */ "", 11683 /* CMIC_LEDUP1_PROGRAM_RAM103 */ "", 11684 /* CMIC_LEDUP1_PROGRAM_RAM104 */ "", 11685 /* CMIC_LEDUP1_PROGRAM_RAM105 */ "", 11686 /* CMIC_LEDUP1_PROGRAM_RAM106 */ "", 11687 /* CMIC_LEDUP1_PROGRAM_RAM107 */ "", 11688 /* CMIC_LEDUP1_PROGRAM_RAM108 */ "", 11689 /* CMIC_LEDUP1_PROGRAM_RAM109 */ "", 11690 /* CMIC_LEDUP1_PROGRAM_RAM110 */ "", 11691 /* CMIC_LEDUP1_PROGRAM_RAM111 */ "", 11692 /* CMIC_LEDUP1_PROGRAM_RAM112 */ "", 11693 /* CMIC_LEDUP1_PROGRAM_RAM113 */ "", 11694 /* CMIC_LEDUP1_PROGRAM_RAM114 */ "", 11695 /* CMIC_LEDUP1_PROGRAM_RAM115 */ "", 11696 /* CMIC_LEDUP1_PROGRAM_RAM116 */ "", 11697 /* CMIC_LEDUP1_PROGRAM_RAM117 */ "", 11698 /* CMIC_LEDUP1_PROGRAM_RAM118 */ "", 11699 /* CMIC_LEDUP1_PROGRAM_RAM119 */ "", 11700 /* CMIC_LEDUP1_PROGRAM_RAM120 */ "", 11701 /* CMIC_LEDUP1_PROGRAM_RAM121 */ "", 11702 /* CMIC_LEDUP1_PROGRAM_RAM122 */ "", 11703 /* CMIC_LEDUP1_PROGRAM_RAM123 */ "", 11704 /* CMIC_LEDUP1_PROGRAM_RAM124 */ "", 11705 /* CMIC_LEDUP1_PROGRAM_RAM125 */ "", 11706 /* CMIC_LEDUP1_PROGRAM_RAM126 */ "", 11707 /* CMIC_LEDUP1_PROGRAM_RAM127 */ "", 11708 /* CMIC_LEDUP1_PROGRAM_RAM128 */ "", 11709 /* CMIC_LEDUP1_PROGRAM_RAM129 */ "", 11710 /* CMIC_LEDUP1_PROGRAM_RAM130 */ "", 11711 /* CMIC_LEDUP1_PROGRAM_RAM131 */ "", 11712 /* CMIC_LEDUP1_PROGRAM_RAM132 */ "", 11713 /* CMIC_LEDUP1_PROGRAM_RAM133 */ "", 11714 /* CMIC_LEDUP1_PROGRAM_RAM134 */ "", 11715 /* CMIC_LEDUP1_PROGRAM_RAM135 */ "", 11716 /* CMIC_LEDUP1_PROGRAM_RAM136 */ "", 11717 /* CMIC_LEDUP1_PROGRAM_RAM137 */ "", 11718 /* CMIC_LEDUP1_PROGRAM_RAM138 */ "", 11719 /* CMIC_LEDUP1_PROGRAM_RAM139 */ "", 11720 /* CMIC_LEDUP1_PROGRAM_RAM140 */ "", 11721 /* CMIC_LEDUP1_PROGRAM_RAM141 */ "", 11722 /* CMIC_LEDUP1_PROGRAM_RAM142 */ "", 11723 /* CMIC_LEDUP1_PROGRAM_RAM143 */ "", 11724 /* CMIC_LEDUP1_PROGRAM_RAM144 */ "", 11725 /* CMIC_LEDUP1_PROGRAM_RAM145 */ "", 11726 /* CMIC_LEDUP1_PROGRAM_RAM146 */ "", 11727 /* CMIC_LEDUP1_PROGRAM_RAM147 */ "", 11728 /* CMIC_LEDUP1_PROGRAM_RAM148 */ "", 11729 /* CMIC_LEDUP1_PROGRAM_RAM149 */ "", 11730 /* CMIC_LEDUP1_PROGRAM_RAM150 */ "", 11731 /* CMIC_LEDUP1_PROGRAM_RAM151 */ "", 11732 /* CMIC_LEDUP1_PROGRAM_RAM152 */ "", 11733 /* CMIC_LEDUP1_PROGRAM_RAM153 */ "", 11734 /* CMIC_LEDUP1_PROGRAM_RAM154 */ "", 11735 /* CMIC_LEDUP1_PROGRAM_RAM155 */ "", 11736 /* CMIC_LEDUP1_PROGRAM_RAM156 */ "", 11737 /* CMIC_LEDUP1_PROGRAM_RAM157 */ "", 11738 /* CMIC_LEDUP1_PROGRAM_RAM158 */ "", 11739 /* CMIC_LEDUP1_PROGRAM_RAM159 */ "", 11740 /* CMIC_LEDUP1_PROGRAM_RAM160 */ "", 11741 /* CMIC_LEDUP1_PROGRAM_RAM161 */ "", 11742 /* CMIC_LEDUP1_PROGRAM_RAM162 */ "", 11743 /* CMIC_LEDUP1_PROGRAM_RAM163 */ "", 11744 /* CMIC_LEDUP1_PROGRAM_RAM164 */ "", 11745 /* CMIC_LEDUP1_PROGRAM_RAM165 */ "", 11746 /* CMIC_LEDUP1_PROGRAM_RAM166 */ "", 11747 /* CMIC_LEDUP1_PROGRAM_RAM167 */ "", 11748 /* CMIC_LEDUP1_PROGRAM_RAM168 */ "", 11749 /* CMIC_LEDUP1_PROGRAM_RAM169 */ "", 11750 /* CMIC_LEDUP1_PROGRAM_RAM170 */ "", 11751 /* CMIC_LEDUP1_PROGRAM_RAM171 */ "", 11752 /* CMIC_LEDUP1_PROGRAM_RAM172 */ "", 11753 /* CMIC_LEDUP1_PROGRAM_RAM173 */ "", 11754 /* CMIC_LEDUP1_PROGRAM_RAM174 */ "", 11755 /* CMIC_LEDUP1_PROGRAM_RAM175 */ "", 11756 /* CMIC_LEDUP1_PROGRAM_RAM176 */ "", 11757 /* CMIC_LEDUP1_PROGRAM_RAM177 */ "", 11758 /* CMIC_LEDUP1_PROGRAM_RAM178 */ "", 11759 /* CMIC_LEDUP1_PROGRAM_RAM179 */ "", 11760 /* CMIC_LEDUP1_PROGRAM_RAM180 */ "", 11761 /* CMIC_LEDUP1_PROGRAM_RAM181 */ "", 11762 /* CMIC_LEDUP1_PROGRAM_RAM182 */ "", 11763 /* CMIC_LEDUP1_PROGRAM_RAM183 */ "", 11764 /* CMIC_LEDUP1_PROGRAM_RAM184 */ "", 11765 /* CMIC_LEDUP1_PROGRAM_RAM185 */ "", 11766 /* CMIC_LEDUP1_PROGRAM_RAM186 */ "", 11767 /* CMIC_LEDUP1_PROGRAM_RAM187 */ "", 11768 /* CMIC_LEDUP1_PROGRAM_RAM188 */ "", 11769 /* CMIC_LEDUP1_PROGRAM_RAM189 */ "", 11770 /* CMIC_LEDUP1_PROGRAM_RAM190 */ "", 11771 /* CMIC_LEDUP1_PROGRAM_RAM191 */ "", 11772 /* CMIC_LEDUP1_PROGRAM_RAM192 */ "", 11773 /* CMIC_LEDUP1_PROGRAM_RAM193 */ "", 11774 /* CMIC_LEDUP1_PROGRAM_RAM194 */ "", 11775 /* CMIC_LEDUP1_PROGRAM_RAM195 */ "", 11776 /* CMIC_LEDUP1_PROGRAM_RAM196 */ "", 11777 /* CMIC_LEDUP1_PROGRAM_RAM197 */ "", 11778 /* CMIC_LEDUP1_PROGRAM_RAM198 */ "", 11779 /* CMIC_LEDUP1_PROGRAM_RAM199 */ "", 11780 /* CMIC_LEDUP1_PROGRAM_RAM200 */ "", 11781 /* CMIC_LEDUP1_PROGRAM_RAM201 */ "", 11782 /* CMIC_LEDUP1_PROGRAM_RAM202 */ "", 11783 /* CMIC_LEDUP1_PROGRAM_RAM203 */ "", 11784 /* CMIC_LEDUP1_PROGRAM_RAM204 */ "", 11785 /* CMIC_LEDUP1_PROGRAM_RAM205 */ "", 11786 /* CMIC_LEDUP1_PROGRAM_RAM206 */ "", 11787 /* CMIC_LEDUP1_PROGRAM_RAM207 */ "", 11788 /* CMIC_LEDUP1_PROGRAM_RAM208 */ "", 11789 /* CMIC_LEDUP1_PROGRAM_RAM209 */ "", 11790 /* CMIC_LEDUP1_PROGRAM_RAM210 */ "", 11791 /* CMIC_LEDUP1_PROGRAM_RAM211 */ "", 11792 /* CMIC_LEDUP1_PROGRAM_RAM212 */ "", 11793 /* CMIC_LEDUP1_PROGRAM_RAM213 */ "", 11794 /* CMIC_LEDUP1_PROGRAM_RAM214 */ "", 11795 /* CMIC_LEDUP1_PROGRAM_RAM215 */ "", 11796 /* CMIC_LEDUP1_PROGRAM_RAM216 */ "", 11797 /* CMIC_LEDUP1_PROGRAM_RAM217 */ "", 11798 /* CMIC_LEDUP1_PROGRAM_RAM218 */ "", 11799 /* CMIC_LEDUP1_PROGRAM_RAM219 */ "", 11800 /* CMIC_LEDUP1_PROGRAM_RAM220 */ "", 11801 /* CMIC_LEDUP1_PROGRAM_RAM221 */ "", 11802 /* CMIC_LEDUP1_PROGRAM_RAM222 */ "", 11803 /* CMIC_LEDUP1_PROGRAM_RAM223 */ "", 11804 /* CMIC_LEDUP1_PROGRAM_RAM224 */ "", 11805 /* CMIC_LEDUP1_PROGRAM_RAM225 */ "", 11806 /* CMIC_LEDUP1_PROGRAM_RAM226 */ "", 11807 /* CMIC_LEDUP1_PROGRAM_RAM227 */ "", 11808 /* CMIC_LEDUP1_PROGRAM_RAM228 */ "", 11809 /* CMIC_LEDUP1_PROGRAM_RAM229 */ "", 11810 /* CMIC_LEDUP1_PROGRAM_RAM230 */ "", 11811 /* CMIC_LEDUP1_PROGRAM_RAM231 */ "", 11812 /* CMIC_LEDUP1_PROGRAM_RAM232 */ "", 11813 /* CMIC_LEDUP1_PROGRAM_RAM233 */ "", 11814 /* CMIC_LEDUP1_PROGRAM_RAM234 */ "", 11815 /* CMIC_LEDUP1_PROGRAM_RAM235 */ "", 11816 /* CMIC_LEDUP1_PROGRAM_RAM236 */ "", 11817 /* CMIC_LEDUP1_PROGRAM_RAM237 */ "", 11818 /* CMIC_LEDUP1_PROGRAM_RAM238 */ "", 11819 /* CMIC_LEDUP1_PROGRAM_RAM239 */ "", 11820 /* CMIC_LEDUP1_PROGRAM_RAM240 */ "", 11821 /* CMIC_LEDUP1_PROGRAM_RAM241 */ "", 11822 /* CMIC_LEDUP1_PROGRAM_RAM242 */ "", 11823 /* CMIC_LEDUP1_PROGRAM_RAM243 */ "", 11824 /* CMIC_LEDUP1_PROGRAM_RAM244 */ "", 11825 /* CMIC_LEDUP1_PROGRAM_RAM245 */ "", 11826 /* CMIC_LEDUP1_PROGRAM_RAM246 */ "", 11827 /* CMIC_LEDUP1_PROGRAM_RAM247 */ "", 11828 /* CMIC_LEDUP1_PROGRAM_RAM248 */ "", 11829 /* CMIC_LEDUP1_PROGRAM_RAM249 */ "", 11830 /* CMIC_LEDUP1_PROGRAM_RAM250 */ "", 11831 /* CMIC_LEDUP1_PROGRAM_RAM251 */ "", 11832 /* CMIC_LEDUP1_PROGRAM_RAM252 */ "", 11833 /* CMIC_LEDUP1_PROGRAM_RAM253 */ "", 11834 /* CMIC_LEDUP1_PROGRAM_RAM254 */ "", 11835 /* CMIC_LEDUP1_PROGRAM_RAM255 */ "", 11836 /* CMIC_LEDUP1_SCANCHAIN_ASSEMBLY_ST_ADDR */ "", 11837 /* CMIC_LEDUP1_SCANOUT_COUNT_UPPER */ "", 11838 /* CMIC_LEDUP1_STATUS */ "", 11839 /* CMIC_LEDUP1_TM_CONTROL */ "", 11840 /* CMIC_LEDUP2_CLK_DIV */ "", 11841 /* CMIC_LEDUP2_CLK_PARAMS */ "", 11842 /* CMIC_LEDUP2_CTRL */ "", 11843 /* CMIC_LEDUP2_DATA_RAM */ "", 11844 /* CMIC_LEDUP2_DATA_RAM0 */ "", 11845 /* CMIC_LEDUP2_DATA_RAM1 */ "", 11846 /* CMIC_LEDUP2_DATA_RAM2 */ "", 11847 /* CMIC_LEDUP2_DATA_RAM3 */ "", 11848 /* CMIC_LEDUP2_DATA_RAM4 */ "", 11849 /* CMIC_LEDUP2_DATA_RAM5 */ "", 11850 /* CMIC_LEDUP2_DATA_RAM6 */ "", 11851 /* CMIC_LEDUP2_DATA_RAM7 */ "", 11852 /* CMIC_LEDUP2_DATA_RAM8 */ "", 11853 /* CMIC_LEDUP2_DATA_RAM9 */ "", 11854 /* CMIC_LEDUP2_DATA_RAM10 */ "", 11855 /* CMIC_LEDUP2_DATA_RAM11 */ "", 11856 /* CMIC_LEDUP2_DATA_RAM12 */ "", 11857 /* CMIC_LEDUP2_DATA_RAM13 */ "", 11858 /* CMIC_LEDUP2_DATA_RAM14 */ "", 11859 /* CMIC_LEDUP2_DATA_RAM15 */ "", 11860 /* CMIC_LEDUP2_DATA_RAM16 */ "", 11861 /* CMIC_LEDUP2_DATA_RAM17 */ "", 11862 /* CMIC_LEDUP2_DATA_RAM18 */ "", 11863 /* CMIC_LEDUP2_DATA_RAM19 */ "", 11864 /* CMIC_LEDUP2_DATA_RAM20 */ "", 11865 /* CMIC_LEDUP2_DATA_RAM21 */ "", 11866 /* CMIC_LEDUP2_DATA_RAM22 */ "", 11867 /* CMIC_LEDUP2_DATA_RAM23 */ "", 11868 /* CMIC_LEDUP2_DATA_RAM24 */ "", 11869 /* CMIC_LEDUP2_DATA_RAM25 */ "", 11870 /* CMIC_LEDUP2_DATA_RAM26 */ "", 11871 /* CMIC_LEDUP2_DATA_RAM27 */ "", 11872 /* CMIC_LEDUP2_DATA_RAM28 */ "", 11873 /* CMIC_LEDUP2_DATA_RAM29 */ "", 11874 /* CMIC_LEDUP2_DATA_RAM30 */ "", 11875 /* CMIC_LEDUP2_DATA_RAM31 */ "", 11876 /* CMIC_LEDUP2_DATA_RAM32 */ "", 11877 /* CMIC_LEDUP2_DATA_RAM33 */ "", 11878 /* CMIC_LEDUP2_DATA_RAM34 */ "", 11879 /* CMIC_LEDUP2_DATA_RAM35 */ "", 11880 /* CMIC_LEDUP2_DATA_RAM36 */ "", 11881 /* CMIC_LEDUP2_DATA_RAM37 */ "", 11882 /* CMIC_LEDUP2_DATA_RAM38 */ "", 11883 /* CMIC_LEDUP2_DATA_RAM39 */ "", 11884 /* CMIC_LEDUP2_DATA_RAM40 */ "", 11885 /* CMIC_LEDUP2_DATA_RAM41 */ "", 11886 /* CMIC_LEDUP2_DATA_RAM42 */ "", 11887 /* CMIC_LEDUP2_DATA_RAM43 */ "", 11888 /* CMIC_LEDUP2_DATA_RAM44 */ "", 11889 /* CMIC_LEDUP2_DATA_RAM45 */ "", 11890 /* CMIC_LEDUP2_DATA_RAM46 */ "", 11891 /* CMIC_LEDUP2_DATA_RAM47 */ "", 11892 /* CMIC_LEDUP2_DATA_RAM48 */ "", 11893 /* CMIC_LEDUP2_DATA_RAM49 */ "", 11894 /* CMIC_LEDUP2_DATA_RAM50 */ "", 11895 /* CMIC_LEDUP2_DATA_RAM51 */ "", 11896 /* CMIC_LEDUP2_DATA_RAM52 */ "", 11897 /* CMIC_LEDUP2_DATA_RAM53 */ "", 11898 /* CMIC_LEDUP2_DATA_RAM54 */ "", 11899 /* CMIC_LEDUP2_DATA_RAM55 */ "", 11900 /* CMIC_LEDUP2_DATA_RAM56 */ "", 11901 /* CMIC_LEDUP2_DATA_RAM57 */ "", 11902 /* CMIC_LEDUP2_DATA_RAM58 */ "", 11903 /* CMIC_LEDUP2_DATA_RAM59 */ "", 11904 /* CMIC_LEDUP2_DATA_RAM60 */ "", 11905 /* CMIC_LEDUP2_DATA_RAM61 */ "", 11906 /* CMIC_LEDUP2_DATA_RAM62 */ "", 11907 /* CMIC_LEDUP2_DATA_RAM63 */ "", 11908 /* CMIC_LEDUP2_DATA_RAM64 */ "", 11909 /* CMIC_LEDUP2_DATA_RAM65 */ "", 11910 /* CMIC_LEDUP2_DATA_RAM66 */ "", 11911 /* CMIC_LEDUP2_DATA_RAM67 */ "", 11912 /* CMIC_LEDUP2_DATA_RAM68 */ "", 11913 /* CMIC_LEDUP2_DATA_RAM69 */ "", 11914 /* CMIC_LEDUP2_DATA_RAM70 */ "", 11915 /* CMIC_LEDUP2_DATA_RAM71 */ "", 11916 /* CMIC_LEDUP2_DATA_RAM72 */ "", 11917 /* CMIC_LEDUP2_DATA_RAM73 */ "", 11918 /* CMIC_LEDUP2_DATA_RAM74 */ "", 11919 /* CMIC_LEDUP2_DATA_RAM75 */ "", 11920 /* CMIC_LEDUP2_DATA_RAM76 */ "", 11921 /* CMIC_LEDUP2_DATA_RAM77 */ "", 11922 /* CMIC_LEDUP2_DATA_RAM78 */ "", 11923 /* CMIC_LEDUP2_DATA_RAM79 */ "", 11924 /* CMIC_LEDUP2_DATA_RAM80 */ "", 11925 /* CMIC_LEDUP2_DATA_RAM81 */ "", 11926 /* CMIC_LEDUP2_DATA_RAM82 */ "", 11927 /* CMIC_LEDUP2_DATA_RAM83 */ "", 11928 /* CMIC_LEDUP2_DATA_RAM84 */ "", 11929 /* CMIC_LEDUP2_DATA_RAM85 */ "", 11930 /* CMIC_LEDUP2_DATA_RAM86 */ "", 11931 /* CMIC_LEDUP2_DATA_RAM87 */ "", 11932 /* CMIC_LEDUP2_DATA_RAM88 */ "", 11933 /* CMIC_LEDUP2_DATA_RAM89 */ "", 11934 /* CMIC_LEDUP2_DATA_RAM90 */ "", 11935 /* CMIC_LEDUP2_DATA_RAM91 */ "", 11936 /* CMIC_LEDUP2_DATA_RAM92 */ "", 11937 /* CMIC_LEDUP2_DATA_RAM93 */ "", 11938 /* CMIC_LEDUP2_DATA_RAM94 */ "", 11939 /* CMIC_LEDUP2_DATA_RAM95 */ "", 11940 /* CMIC_LEDUP2_DATA_RAM96 */ "", 11941 /* CMIC_LEDUP2_DATA_RAM97 */ "", 11942 /* CMIC_LEDUP2_DATA_RAM98 */ "", 11943 /* CMIC_LEDUP2_DATA_RAM99 */ "", 11944 /* CMIC_LEDUP2_DATA_RAM100 */ "", 11945 /* CMIC_LEDUP2_DATA_RAM101 */ "", 11946 /* CMIC_LEDUP2_DATA_RAM102 */ "", 11947 /* CMIC_LEDUP2_DATA_RAM103 */ "", 11948 /* CMIC_LEDUP2_DATA_RAM104 */ "", 11949 /* CMIC_LEDUP2_DATA_RAM105 */ "", 11950 /* CMIC_LEDUP2_DATA_RAM106 */ "", 11951 /* CMIC_LEDUP2_DATA_RAM107 */ "", 11952 /* CMIC_LEDUP2_DATA_RAM108 */ "", 11953 /* CMIC_LEDUP2_DATA_RAM109 */ "", 11954 /* CMIC_LEDUP2_DATA_RAM110 */ "", 11955 /* CMIC_LEDUP2_DATA_RAM111 */ "", 11956 /* CMIC_LEDUP2_DATA_RAM112 */ "", 11957 /* CMIC_LEDUP2_DATA_RAM113 */ "", 11958 /* CMIC_LEDUP2_DATA_RAM114 */ "", 11959 /* CMIC_LEDUP2_DATA_RAM115 */ "", 11960 /* CMIC_LEDUP2_DATA_RAM116 */ "", 11961 /* CMIC_LEDUP2_DATA_RAM117 */ "", 11962 /* CMIC_LEDUP2_DATA_RAM118 */ "", 11963 /* CMIC_LEDUP2_DATA_RAM119 */ "", 11964 /* CMIC_LEDUP2_DATA_RAM120 */ "", 11965 /* CMIC_LEDUP2_DATA_RAM121 */ "", 11966 /* CMIC_LEDUP2_DATA_RAM122 */ "", 11967 /* CMIC_LEDUP2_DATA_RAM123 */ "", 11968 /* CMIC_LEDUP2_DATA_RAM124 */ "", 11969 /* CMIC_LEDUP2_DATA_RAM125 */ "", 11970 /* CMIC_LEDUP2_DATA_RAM126 */ "", 11971 /* CMIC_LEDUP2_DATA_RAM127 */ "", 11972 /* CMIC_LEDUP2_DATA_RAM128 */ "", 11973 /* CMIC_LEDUP2_DATA_RAM129 */ "", 11974 /* CMIC_LEDUP2_DATA_RAM130 */ "", 11975 /* CMIC_LEDUP2_DATA_RAM131 */ "", 11976 /* CMIC_LEDUP2_DATA_RAM132 */ "", 11977 /* CMIC_LEDUP2_DATA_RAM133 */ "", 11978 /* CMIC_LEDUP2_DATA_RAM134 */ "", 11979 /* CMIC_LEDUP2_DATA_RAM135 */ "", 11980 /* CMIC_LEDUP2_DATA_RAM136 */ "", 11981 /* CMIC_LEDUP2_DATA_RAM137 */ "", 11982 /* CMIC_LEDUP2_DATA_RAM138 */ "", 11983 /* CMIC_LEDUP2_DATA_RAM139 */ "", 11984 /* CMIC_LEDUP2_DATA_RAM140 */ "", 11985 /* CMIC_LEDUP2_DATA_RAM141 */ "", 11986 /* CMIC_LEDUP2_DATA_RAM142 */ "", 11987 /* CMIC_LEDUP2_DATA_RAM143 */ "", 11988 /* CMIC_LEDUP2_DATA_RAM144 */ "", 11989 /* CMIC_LEDUP2_DATA_RAM145 */ "", 11990 /* CMIC_LEDUP2_DATA_RAM146 */ "", 11991 /* CMIC_LEDUP2_DATA_RAM147 */ "", 11992 /* CMIC_LEDUP2_DATA_RAM148 */ "", 11993 /* CMIC_LEDUP2_DATA_RAM149 */ "", 11994 /* CMIC_LEDUP2_DATA_RAM150 */ "", 11995 /* CMIC_LEDUP2_DATA_RAM151 */ "", 11996 /* CMIC_LEDUP2_DATA_RAM152 */ "", 11997 /* CMIC_LEDUP2_DATA_RAM153 */ "", 11998 /* CMIC_LEDUP2_DATA_RAM154 */ "", 11999 /* CMIC_LEDUP2_DATA_RAM155 */ "", 12000 /* CMIC_LEDUP2_DATA_RAM156 */ "", 12001 /* CMIC_LEDUP2_DATA_RAM157 */ "", 12002 /* CMIC_LEDUP2_DATA_RAM158 */ "", 12003 /* CMIC_LEDUP2_DATA_RAM159 */ "", 12004 /* CMIC_LEDUP2_DATA_RAM160 */ "", 12005 /* CMIC_LEDUP2_DATA_RAM161 */ "", 12006 /* CMIC_LEDUP2_DATA_RAM162 */ "", 12007 /* CMIC_LEDUP2_DATA_RAM163 */ "", 12008 /* CMIC_LEDUP2_DATA_RAM164 */ "", 12009 /* CMIC_LEDUP2_DATA_RAM165 */ "", 12010 /* CMIC_LEDUP2_DATA_RAM166 */ "", 12011 /* CMIC_LEDUP2_DATA_RAM167 */ "", 12012 /* CMIC_LEDUP2_DATA_RAM168 */ "", 12013 /* CMIC_LEDUP2_DATA_RAM169 */ "", 12014 /* CMIC_LEDUP2_DATA_RAM170 */ "", 12015 /* CMIC_LEDUP2_DATA_RAM171 */ "", 12016 /* CMIC_LEDUP2_DATA_RAM172 */ "", 12017 /* CMIC_LEDUP2_DATA_RAM173 */ "", 12018 /* CMIC_LEDUP2_DATA_RAM174 */ "", 12019 /* CMIC_LEDUP2_DATA_RAM175 */ "", 12020 /* CMIC_LEDUP2_DATA_RAM176 */ "", 12021 /* CMIC_LEDUP2_DATA_RAM177 */ "", 12022 /* CMIC_LEDUP2_DATA_RAM178 */ "", 12023 /* CMIC_LEDUP2_DATA_RAM179 */ "", 12024 /* CMIC_LEDUP2_DATA_RAM180 */ "", 12025 /* CMIC_LEDUP2_DATA_RAM181 */ "", 12026 /* CMIC_LEDUP2_DATA_RAM182 */ "", 12027 /* CMIC_LEDUP2_DATA_RAM183 */ "", 12028 /* CMIC_LEDUP2_DATA_RAM184 */ "", 12029 /* CMIC_LEDUP2_DATA_RAM185 */ "", 12030 /* CMIC_LEDUP2_DATA_RAM186 */ "", 12031 /* CMIC_LEDUP2_DATA_RAM187 */ "", 12032 /* CMIC_LEDUP2_DATA_RAM188 */ "", 12033 /* CMIC_LEDUP2_DATA_RAM189 */ "", 12034 /* CMIC_LEDUP2_DATA_RAM190 */ "", 12035 /* CMIC_LEDUP2_DATA_RAM191 */ "", 12036 /* CMIC_LEDUP2_DATA_RAM192 */ "", 12037 /* CMIC_LEDUP2_DATA_RAM193 */ "", 12038 /* CMIC_LEDUP2_DATA_RAM194 */ "", 12039 /* CMIC_LEDUP2_DATA_RAM195 */ "", 12040 /* CMIC_LEDUP2_DATA_RAM196 */ "", 12041 /* CMIC_LEDUP2_DATA_RAM197 */ "", 12042 /* CMIC_LEDUP2_DATA_RAM198 */ "", 12043 /* CMIC_LEDUP2_DATA_RAM199 */ "", 12044 /* CMIC_LEDUP2_DATA_RAM200 */ "", 12045 /* CMIC_LEDUP2_DATA_RAM201 */ "", 12046 /* CMIC_LEDUP2_DATA_RAM202 */ "", 12047 /* CMIC_LEDUP2_DATA_RAM203 */ "", 12048 /* CMIC_LEDUP2_DATA_RAM204 */ "", 12049 /* CMIC_LEDUP2_DATA_RAM205 */ "", 12050 /* CMIC_LEDUP2_DATA_RAM206 */ "", 12051 /* CMIC_LEDUP2_DATA_RAM207 */ "", 12052 /* CMIC_LEDUP2_DATA_RAM208 */ "", 12053 /* CMIC_LEDUP2_DATA_RAM209 */ "", 12054 /* CMIC_LEDUP2_DATA_RAM210 */ "", 12055 /* CMIC_LEDUP2_DATA_RAM211 */ "", 12056 /* CMIC_LEDUP2_DATA_RAM212 */ "", 12057 /* CMIC_LEDUP2_DATA_RAM213 */ "", 12058 /* CMIC_LEDUP2_DATA_RAM214 */ "", 12059 /* CMIC_LEDUP2_DATA_RAM215 */ "", 12060 /* CMIC_LEDUP2_DATA_RAM216 */ "", 12061 /* CMIC_LEDUP2_DATA_RAM217 */ "", 12062 /* CMIC_LEDUP2_DATA_RAM218 */ "", 12063 /* CMIC_LEDUP2_DATA_RAM219 */ "", 12064 /* CMIC_LEDUP2_DATA_RAM220 */ "", 12065 /* CMIC_LEDUP2_DATA_RAM221 */ "", 12066 /* CMIC_LEDUP2_DATA_RAM222 */ "", 12067 /* CMIC_LEDUP2_DATA_RAM223 */ "", 12068 /* CMIC_LEDUP2_DATA_RAM224 */ "", 12069 /* CMIC_LEDUP2_DATA_RAM225 */ "", 12070 /* CMIC_LEDUP2_DATA_RAM226 */ "", 12071 /* CMIC_LEDUP2_DATA_RAM227 */ "", 12072 /* CMIC_LEDUP2_DATA_RAM228 */ "", 12073 /* CMIC_LEDUP2_DATA_RAM229 */ "", 12074 /* CMIC_LEDUP2_DATA_RAM230 */ "", 12075 /* CMIC_LEDUP2_DATA_RAM231 */ "", 12076 /* CMIC_LEDUP2_DATA_RAM232 */ "", 12077 /* CMIC_LEDUP2_DATA_RAM233 */ "", 12078 /* CMIC_LEDUP2_DATA_RAM234 */ "", 12079 /* CMIC_LEDUP2_DATA_RAM235 */ "", 12080 /* CMIC_LEDUP2_DATA_RAM236 */ "", 12081 /* CMIC_LEDUP2_DATA_RAM237 */ "", 12082 /* CMIC_LEDUP2_DATA_RAM238 */ "", 12083 /* CMIC_LEDUP2_DATA_RAM239 */ "", 12084 /* CMIC_LEDUP2_DATA_RAM240 */ "", 12085 /* CMIC_LEDUP2_DATA_RAM241 */ "", 12086 /* CMIC_LEDUP2_DATA_RAM242 */ "", 12087 /* CMIC_LEDUP2_DATA_RAM243 */ "", 12088 /* CMIC_LEDUP2_DATA_RAM244 */ "", 12089 /* CMIC_LEDUP2_DATA_RAM245 */ "", 12090 /* CMIC_LEDUP2_DATA_RAM246 */ "", 12091 /* CMIC_LEDUP2_DATA_RAM247 */ "", 12092 /* CMIC_LEDUP2_DATA_RAM248 */ "", 12093 /* CMIC_LEDUP2_DATA_RAM249 */ "", 12094 /* CMIC_LEDUP2_DATA_RAM250 */ "", 12095 /* CMIC_LEDUP2_DATA_RAM251 */ "", 12096 /* CMIC_LEDUP2_DATA_RAM252 */ "", 12097 /* CMIC_LEDUP2_DATA_RAM253 */ "", 12098 /* CMIC_LEDUP2_DATA_RAM254 */ "", 12099 /* CMIC_LEDUP2_DATA_RAM255 */ "", 12100 /* CMIC_LEDUP2_ECC_CONFIG */ "", 12101 /* CMIC_LEDUP2_ECC_INTR */ "", 12102 /* CMIC_LEDUP2_ECC_INTR_CLR */ "", 12103 /* CMIC_LEDUP2_ECC_INTR_ENABLE */ "", 12104 /* CMIC_LEDUP2_ECC_STATUS */ "", 12105 /* CMIC_LEDUP2_PORT_ORDER_REMAP_0_3 */ "", 12106 /* CMIC_LEDUP2_PORT_ORDER_REMAP_12_15 */ "", 12107 /* CMIC_LEDUP2_PORT_ORDER_REMAP_16_19 */ "", 12108 /* CMIC_LEDUP2_PORT_ORDER_REMAP_20_23 */ "", 12109 /* CMIC_LEDUP2_PORT_ORDER_REMAP_24_27 */ "", 12110 /* CMIC_LEDUP2_PORT_ORDER_REMAP_28_31 */ "", 12111 /* CMIC_LEDUP2_PORT_ORDER_REMAP_32_35 */ "", 12112 /* CMIC_LEDUP2_PORT_ORDER_REMAP_36_39 */ "", 12113 /* CMIC_LEDUP2_PORT_ORDER_REMAP_40_43 */ "", 12114 /* CMIC_LEDUP2_PORT_ORDER_REMAP_44_47 */ "", 12115 /* CMIC_LEDUP2_PORT_ORDER_REMAP_48_51 */ "", 12116 /* CMIC_LEDUP2_PORT_ORDER_REMAP_4_7 */ "", 12117 /* CMIC_LEDUP2_PORT_ORDER_REMAP_52_55 */ "", 12118 /* CMIC_LEDUP2_PORT_ORDER_REMAP_56_59 */ "", 12119 /* CMIC_LEDUP2_PORT_ORDER_REMAP_60_63 */ "", 12120 /* CMIC_LEDUP2_PORT_ORDER_REMAP_8_11 */ "", 12121 /* CMIC_LEDUP2_PROGRAM_RAM */ "", 12122 /* CMIC_LEDUP2_PROGRAM_RAM0 */ "", 12123 /* CMIC_LEDUP2_PROGRAM_RAM1 */ "", 12124 /* CMIC_LEDUP2_PROGRAM_RAM2 */ "", 12125 /* CMIC_LEDUP2_PROGRAM_RAM3 */ "", 12126 /* CMIC_LEDUP2_PROGRAM_RAM4 */ "", 12127 /* CMIC_LEDUP2_PROGRAM_RAM5 */ "", 12128 /* CMIC_LEDUP2_PROGRAM_RAM6 */ "", 12129 /* CMIC_LEDUP2_PROGRAM_RAM7 */ "", 12130 /* CMIC_LEDUP2_PROGRAM_RAM8 */ "", 12131 /* CMIC_LEDUP2_PROGRAM_RAM9 */ "", 12132 /* CMIC_LEDUP2_PROGRAM_RAM10 */ "", 12133 /* CMIC_LEDUP2_PROGRAM_RAM11 */ "", 12134 /* CMIC_LEDUP2_PROGRAM_RAM12 */ "", 12135 /* CMIC_LEDUP2_PROGRAM_RAM13 */ "", 12136 /* CMIC_LEDUP2_PROGRAM_RAM14 */ "", 12137 /* CMIC_LEDUP2_PROGRAM_RAM15 */ "", 12138 /* CMIC_LEDUP2_PROGRAM_RAM16 */ "", 12139 /* CMIC_LEDUP2_PROGRAM_RAM17 */ "", 12140 /* CMIC_LEDUP2_PROGRAM_RAM18 */ "", 12141 /* CMIC_LEDUP2_PROGRAM_RAM19 */ "", 12142 /* CMIC_LEDUP2_PROGRAM_RAM20 */ "", 12143 /* CMIC_LEDUP2_PROGRAM_RAM21 */ "", 12144 /* CMIC_LEDUP2_PROGRAM_RAM22 */ "", 12145 /* CMIC_LEDUP2_PROGRAM_RAM23 */ "", 12146 /* CMIC_LEDUP2_PROGRAM_RAM24 */ "", 12147 /* CMIC_LEDUP2_PROGRAM_RAM25 */ "", 12148 /* CMIC_LEDUP2_PROGRAM_RAM26 */ "", 12149 /* CMIC_LEDUP2_PROGRAM_RAM27 */ "", 12150 /* CMIC_LEDUP2_PROGRAM_RAM28 */ "", 12151 /* CMIC_LEDUP2_PROGRAM_RAM29 */ "", 12152 /* CMIC_LEDUP2_PROGRAM_RAM30 */ "", 12153 /* CMIC_LEDUP2_PROGRAM_RAM31 */ "", 12154 /* CMIC_LEDUP2_PROGRAM_RAM32 */ "", 12155 /* CMIC_LEDUP2_PROGRAM_RAM33 */ "", 12156 /* CMIC_LEDUP2_PROGRAM_RAM34 */ "", 12157 /* CMIC_LEDUP2_PROGRAM_RAM35 */ "", 12158 /* CMIC_LEDUP2_PROGRAM_RAM36 */ "", 12159 /* CMIC_LEDUP2_PROGRAM_RAM37 */ "", 12160 /* CMIC_LEDUP2_PROGRAM_RAM38 */ "", 12161 /* CMIC_LEDUP2_PROGRAM_RAM39 */ "", 12162 /* CMIC_LEDUP2_PROGRAM_RAM40 */ "", 12163 /* CMIC_LEDUP2_PROGRAM_RAM41 */ "", 12164 /* CMIC_LEDUP2_PROGRAM_RAM42 */ "", 12165 /* CMIC_LEDUP2_PROGRAM_RAM43 */ "", 12166 /* CMIC_LEDUP2_PROGRAM_RAM44 */ "", 12167 /* CMIC_LEDUP2_PROGRAM_RAM45 */ "", 12168 /* CMIC_LEDUP2_PROGRAM_RAM46 */ "", 12169 /* CMIC_LEDUP2_PROGRAM_RAM47 */ "", 12170 /* CMIC_LEDUP2_PROGRAM_RAM48 */ "", 12171 /* CMIC_LEDUP2_PROGRAM_RAM49 */ "", 12172 /* CMIC_LEDUP2_PROGRAM_RAM50 */ "", 12173 /* CMIC_LEDUP2_PROGRAM_RAM51 */ "", 12174 /* CMIC_LEDUP2_PROGRAM_RAM52 */ "", 12175 /* CMIC_LEDUP2_PROGRAM_RAM53 */ "", 12176 /* CMIC_LEDUP2_PROGRAM_RAM54 */ "", 12177 /* CMIC_LEDUP2_PROGRAM_RAM55 */ "", 12178 /* CMIC_LEDUP2_PROGRAM_RAM56 */ "", 12179 /* CMIC_LEDUP2_PROGRAM_RAM57 */ "", 12180 /* CMIC_LEDUP2_PROGRAM_RAM58 */ "", 12181 /* CMIC_LEDUP2_PROGRAM_RAM59 */ "", 12182 /* CMIC_LEDUP2_PROGRAM_RAM60 */ "", 12183 /* CMIC_LEDUP2_PROGRAM_RAM61 */ "", 12184 /* CMIC_LEDUP2_PROGRAM_RAM62 */ "", 12185 /* CMIC_LEDUP2_PROGRAM_RAM63 */ "", 12186 /* CMIC_LEDUP2_PROGRAM_RAM64 */ "", 12187 /* CMIC_LEDUP2_PROGRAM_RAM65 */ "", 12188 /* CMIC_LEDUP2_PROGRAM_RAM66 */ "", 12189 /* CMIC_LEDUP2_PROGRAM_RAM67 */ "", 12190 /* CMIC_LEDUP2_PROGRAM_RAM68 */ "", 12191 /* CMIC_LEDUP2_PROGRAM_RAM69 */ "", 12192 /* CMIC_LEDUP2_PROGRAM_RAM70 */ "", 12193 /* CMIC_LEDUP2_PROGRAM_RAM71 */ "", 12194 /* CMIC_LEDUP2_PROGRAM_RAM72 */ "", 12195 /* CMIC_LEDUP2_PROGRAM_RAM73 */ "", 12196 /* CMIC_LEDUP2_PROGRAM_RAM74 */ "", 12197 /* CMIC_LEDUP2_PROGRAM_RAM75 */ "", 12198 /* CMIC_LEDUP2_PROGRAM_RAM76 */ "", 12199 /* CMIC_LEDUP2_PROGRAM_RAM77 */ "", 12200 /* CMIC_LEDUP2_PROGRAM_RAM78 */ "", 12201 /* CMIC_LEDUP2_PROGRAM_RAM79 */ "", 12202 /* CMIC_LEDUP2_PROGRAM_RAM80 */ "", 12203 /* CMIC_LEDUP2_PROGRAM_RAM81 */ "", 12204 /* CMIC_LEDUP2_PROGRAM_RAM82 */ "", 12205 /* CMIC_LEDUP2_PROGRAM_RAM83 */ "", 12206 /* CMIC_LEDUP2_PROGRAM_RAM84 */ "", 12207 /* CMIC_LEDUP2_PROGRAM_RAM85 */ "", 12208 /* CMIC_LEDUP2_PROGRAM_RAM86 */ "", 12209 /* CMIC_LEDUP2_PROGRAM_RAM87 */ "", 12210 /* CMIC_LEDUP2_PROGRAM_RAM88 */ "", 12211 /* CMIC_LEDUP2_PROGRAM_RAM89 */ "", 12212 /* CMIC_LEDUP2_PROGRAM_RAM90 */ "", 12213 /* CMIC_LEDUP2_PROGRAM_RAM91 */ "", 12214 /* CMIC_LEDUP2_PROGRAM_RAM92 */ "", 12215 /* CMIC_LEDUP2_PROGRAM_RAM93 */ "", 12216 /* CMIC_LEDUP2_PROGRAM_RAM94 */ "", 12217 /* CMIC_LEDUP2_PROGRAM_RAM95 */ "", 12218 /* CMIC_LEDUP2_PROGRAM_RAM96 */ "", 12219 /* CMIC_LEDUP2_PROGRAM_RAM97 */ "", 12220 /* CMIC_LEDUP2_PROGRAM_RAM98 */ "", 12221 /* CMIC_LEDUP2_PROGRAM_RAM99 */ "", 12222 /* CMIC_LEDUP2_PROGRAM_RAM100 */ "", 12223 /* CMIC_LEDUP2_PROGRAM_RAM101 */ "", 12224 /* CMIC_LEDUP2_PROGRAM_RAM102 */ "", 12225 /* CMIC_LEDUP2_PROGRAM_RAM103 */ "", 12226 /* CMIC_LEDUP2_PROGRAM_RAM104 */ "", 12227 /* CMIC_LEDUP2_PROGRAM_RAM105 */ "", 12228 /* CMIC_LEDUP2_PROGRAM_RAM106 */ "", 12229 /* CMIC_LEDUP2_PROGRAM_RAM107 */ "", 12230 /* CMIC_LEDUP2_PROGRAM_RAM108 */ "", 12231 /* CMIC_LEDUP2_PROGRAM_RAM109 */ "", 12232 /* CMIC_LEDUP2_PROGRAM_RAM110 */ "", 12233 /* CMIC_LEDUP2_PROGRAM_RAM111 */ "", 12234 /* CMIC_LEDUP2_PROGRAM_RAM112 */ "", 12235 /* CMIC_LEDUP2_PROGRAM_RAM113 */ "", 12236 /* CMIC_LEDUP2_PROGRAM_RAM114 */ "", 12237 /* CMIC_LEDUP2_PROGRAM_RAM115 */ "", 12238 /* CMIC_LEDUP2_PROGRAM_RAM116 */ "", 12239 /* CMIC_LEDUP2_PROGRAM_RAM117 */ "", 12240 /* CMIC_LEDUP2_PROGRAM_RAM118 */ "", 12241 /* CMIC_LEDUP2_PROGRAM_RAM119 */ "", 12242 /* CMIC_LEDUP2_PROGRAM_RAM120 */ "", 12243 /* CMIC_LEDUP2_PROGRAM_RAM121 */ "", 12244 /* CMIC_LEDUP2_PROGRAM_RAM122 */ "", 12245 /* CMIC_LEDUP2_PROGRAM_RAM123 */ "", 12246 /* CMIC_LEDUP2_PROGRAM_RAM124 */ "", 12247 /* CMIC_LEDUP2_PROGRAM_RAM125 */ "", 12248 /* CMIC_LEDUP2_PROGRAM_RAM126 */ "", 12249 /* CMIC_LEDUP2_PROGRAM_RAM127 */ "", 12250 /* CMIC_LEDUP2_PROGRAM_RAM128 */ "", 12251 /* CMIC_LEDUP2_PROGRAM_RAM129 */ "", 12252 /* CMIC_LEDUP2_PROGRAM_RAM130 */ "", 12253 /* CMIC_LEDUP2_PROGRAM_RAM131 */ "", 12254 /* CMIC_LEDUP2_PROGRAM_RAM132 */ "", 12255 /* CMIC_LEDUP2_PROGRAM_RAM133 */ "", 12256 /* CMIC_LEDUP2_PROGRAM_RAM134 */ "", 12257 /* CMIC_LEDUP2_PROGRAM_RAM135 */ "", 12258 /* CMIC_LEDUP2_PROGRAM_RAM136 */ "", 12259 /* CMIC_LEDUP2_PROGRAM_RAM137 */ "", 12260 /* CMIC_LEDUP2_PROGRAM_RAM138 */ "", 12261 /* CMIC_LEDUP2_PROGRAM_RAM139 */ "", 12262 /* CMIC_LEDUP2_PROGRAM_RAM140 */ "", 12263 /* CMIC_LEDUP2_PROGRAM_RAM141 */ "", 12264 /* CMIC_LEDUP2_PROGRAM_RAM142 */ "", 12265 /* CMIC_LEDUP2_PROGRAM_RAM143 */ "", 12266 /* CMIC_LEDUP2_PROGRAM_RAM144 */ "", 12267 /* CMIC_LEDUP2_PROGRAM_RAM145 */ "", 12268 /* CMIC_LEDUP2_PROGRAM_RAM146 */ "", 12269 /* CMIC_LEDUP2_PROGRAM_RAM147 */ "", 12270 /* CMIC_LEDUP2_PROGRAM_RAM148 */ "", 12271 /* CMIC_LEDUP2_PROGRAM_RAM149 */ "", 12272 /* CMIC_LEDUP2_PROGRAM_RAM150 */ "", 12273 /* CMIC_LEDUP2_PROGRAM_RAM151 */ "", 12274 /* CMIC_LEDUP2_PROGRAM_RAM152 */ "", 12275 /* CMIC_LEDUP2_PROGRAM_RAM153 */ "", 12276 /* CMIC_LEDUP2_PROGRAM_RAM154 */ "", 12277 /* CMIC_LEDUP2_PROGRAM_RAM155 */ "", 12278 /* CMIC_LEDUP2_PROGRAM_RAM156 */ "", 12279 /* CMIC_LEDUP2_PROGRAM_RAM157 */ "", 12280 /* CMIC_LEDUP2_PROGRAM_RAM158 */ "", 12281 /* CMIC_LEDUP2_PROGRAM_RAM159 */ "", 12282 /* CMIC_LEDUP2_PROGRAM_RAM160 */ "", 12283 /* CMIC_LEDUP2_PROGRAM_RAM161 */ "", 12284 /* CMIC_LEDUP2_PROGRAM_RAM162 */ "", 12285 /* CMIC_LEDUP2_PROGRAM_RAM163 */ "", 12286 /* CMIC_LEDUP2_PROGRAM_RAM164 */ "", 12287 /* CMIC_LEDUP2_PROGRAM_RAM165 */ "", 12288 /* CMIC_LEDUP2_PROGRAM_RAM166 */ "", 12289 /* CMIC_LEDUP2_PROGRAM_RAM167 */ "", 12290 /* CMIC_LEDUP2_PROGRAM_RAM168 */ "", 12291 /* CMIC_LEDUP2_PROGRAM_RAM169 */ "", 12292 /* CMIC_LEDUP2_PROGRAM_RAM170 */ "", 12293 /* CMIC_LEDUP2_PROGRAM_RAM171 */ "", 12294 /* CMIC_LEDUP2_PROGRAM_RAM172 */ "", 12295 /* CMIC_LEDUP2_PROGRAM_RAM173 */ "", 12296 /* CMIC_LEDUP2_PROGRAM_RAM174 */ "", 12297 /* CMIC_LEDUP2_PROGRAM_RAM175 */ "", 12298 /* CMIC_LEDUP2_PROGRAM_RAM176 */ "", 12299 /* CMIC_LEDUP2_PROGRAM_RAM177 */ "", 12300 /* CMIC_LEDUP2_PROGRAM_RAM178 */ "", 12301 /* CMIC_LEDUP2_PROGRAM_RAM179 */ "", 12302 /* CMIC_LEDUP2_PROGRAM_RAM180 */ "", 12303 /* CMIC_LEDUP2_PROGRAM_RAM181 */ "", 12304 /* CMIC_LEDUP2_PROGRAM_RAM182 */ "", 12305 /* CMIC_LEDUP2_PROGRAM_RAM183 */ "", 12306 /* CMIC_LEDUP2_PROGRAM_RAM184 */ "", 12307 /* CMIC_LEDUP2_PROGRAM_RAM185 */ "", 12308 /* CMIC_LEDUP2_PROGRAM_RAM186 */ "", 12309 /* CMIC_LEDUP2_PROGRAM_RAM187 */ "", 12310 /* CMIC_LEDUP2_PROGRAM_RAM188 */ "", 12311 /* CMIC_LEDUP2_PROGRAM_RAM189 */ "", 12312 /* CMIC_LEDUP2_PROGRAM_RAM190 */ "", 12313 /* CMIC_LEDUP2_PROGRAM_RAM191 */ "", 12314 /* CMIC_LEDUP2_PROGRAM_RAM192 */ "", 12315 /* CMIC_LEDUP2_PROGRAM_RAM193 */ "", 12316 /* CMIC_LEDUP2_PROGRAM_RAM194 */ "", 12317 /* CMIC_LEDUP2_PROGRAM_RAM195 */ "", 12318 /* CMIC_LEDUP2_PROGRAM_RAM196 */ "", 12319 /* CMIC_LEDUP2_PROGRAM_RAM197 */ "", 12320 /* CMIC_LEDUP2_PROGRAM_RAM198 */ "", 12321 /* CMIC_LEDUP2_PROGRAM_RAM199 */ "", 12322 /* CMIC_LEDUP2_PROGRAM_RAM200 */ "", 12323 /* CMIC_LEDUP2_PROGRAM_RAM201 */ "", 12324 /* CMIC_LEDUP2_PROGRAM_RAM202 */ "", 12325 /* CMIC_LEDUP2_PROGRAM_RAM203 */ "", 12326 /* CMIC_LEDUP2_PROGRAM_RAM204 */ "", 12327 /* CMIC_LEDUP2_PROGRAM_RAM205 */ "", 12328 /* CMIC_LEDUP2_PROGRAM_RAM206 */ "", 12329 /* CMIC_LEDUP2_PROGRAM_RAM207 */ "", 12330 /* CMIC_LEDUP2_PROGRAM_RAM208 */ "", 12331 /* CMIC_LEDUP2_PROGRAM_RAM209 */ "", 12332 /* CMIC_LEDUP2_PROGRAM_RAM210 */ "", 12333 /* CMIC_LEDUP2_PROGRAM_RAM211 */ "", 12334 /* CMIC_LEDUP2_PROGRAM_RAM212 */ "", 12335 /* CMIC_LEDUP2_PROGRAM_RAM213 */ "", 12336 /* CMIC_LEDUP2_PROGRAM_RAM214 */ "", 12337 /* CMIC_LEDUP2_PROGRAM_RAM215 */ "", 12338 /* CMIC_LEDUP2_PROGRAM_RAM216 */ "", 12339 /* CMIC_LEDUP2_PROGRAM_RAM217 */ "", 12340 /* CMIC_LEDUP2_PROGRAM_RAM218 */ "", 12341 /* CMIC_LEDUP2_PROGRAM_RAM219 */ "", 12342 /* CMIC_LEDUP2_PROGRAM_RAM220 */ "", 12343 /* CMIC_LEDUP2_PROGRAM_RAM221 */ "", 12344 /* CMIC_LEDUP2_PROGRAM_RAM222 */ "", 12345 /* CMIC_LEDUP2_PROGRAM_RAM223 */ "", 12346 /* CMIC_LEDUP2_PROGRAM_RAM224 */ "", 12347 /* CMIC_LEDUP2_PROGRAM_RAM225 */ "", 12348 /* CMIC_LEDUP2_PROGRAM_RAM226 */ "", 12349 /* CMIC_LEDUP2_PROGRAM_RAM227 */ "", 12350 /* CMIC_LEDUP2_PROGRAM_RAM228 */ "", 12351 /* CMIC_LEDUP2_PROGRAM_RAM229 */ "", 12352 /* CMIC_LEDUP2_PROGRAM_RAM230 */ "", 12353 /* CMIC_LEDUP2_PROGRAM_RAM231 */ "", 12354 /* CMIC_LEDUP2_PROGRAM_RAM232 */ "", 12355 /* CMIC_LEDUP2_PROGRAM_RAM233 */ "", 12356 /* CMIC_LEDUP2_PROGRAM_RAM234 */ "", 12357 /* CMIC_LEDUP2_PROGRAM_RAM235 */ "", 12358 /* CMIC_LEDUP2_PROGRAM_RAM236 */ "", 12359 /* CMIC_LEDUP2_PROGRAM_RAM237 */ "", 12360 /* CMIC_LEDUP2_PROGRAM_RAM238 */ "", 12361 /* CMIC_LEDUP2_PROGRAM_RAM239 */ "", 12362 /* CMIC_LEDUP2_PROGRAM_RAM240 */ "", 12363 /* CMIC_LEDUP2_PROGRAM_RAM241 */ "", 12364 /* CMIC_LEDUP2_PROGRAM_RAM242 */ "", 12365 /* CMIC_LEDUP2_PROGRAM_RAM243 */ "", 12366 /* CMIC_LEDUP2_PROGRAM_RAM244 */ "", 12367 /* CMIC_LEDUP2_PROGRAM_RAM245 */ "", 12368 /* CMIC_LEDUP2_PROGRAM_RAM246 */ "", 12369 /* CMIC_LEDUP2_PROGRAM_RAM247 */ "", 12370 /* CMIC_LEDUP2_PROGRAM_RAM248 */ "", 12371 /* CMIC_LEDUP2_PROGRAM_RAM249 */ "", 12372 /* CMIC_LEDUP2_PROGRAM_RAM250 */ "", 12373 /* CMIC_LEDUP2_PROGRAM_RAM251 */ "", 12374 /* CMIC_LEDUP2_PROGRAM_RAM252 */ "", 12375 /* CMIC_LEDUP2_PROGRAM_RAM253 */ "", 12376 /* CMIC_LEDUP2_PROGRAM_RAM254 */ "", 12377 /* CMIC_LEDUP2_PROGRAM_RAM255 */ "", 12378 /* CMIC_LEDUP2_SCANCHAIN_ASSEMBLY_ST_ADDR */ "", 12379 /* CMIC_LEDUP2_SCANOUT_COUNT_UPPER */ "", 12380 /* CMIC_LEDUP2_STATUS */ "", 12381 /* CMIC_LEDUP2_TM_CONTROL */ "", 12382 /* CMIC_LEDUP3_CLK_DIV */ "", 12383 /* CMIC_LEDUP3_CLK_PARAMS */ "", 12384 /* CMIC_LEDUP3_CTRL */ "", 12385 /* CMIC_LEDUP3_DATA_RAM */ "", 12386 /* CMIC_LEDUP3_ECC_CONFIG */ "", 12387 /* CMIC_LEDUP3_ECC_INTR */ "", 12388 /* CMIC_LEDUP3_ECC_INTR_CLR */ "", 12389 /* CMIC_LEDUP3_ECC_INTR_ENABLE */ "", 12390 /* CMIC_LEDUP3_ECC_STATUS */ "", 12391 /* CMIC_LEDUP3_PORT_ORDER_REMAP_0_3 */ "", 12392 /* CMIC_LEDUP3_PORT_ORDER_REMAP_12_15 */ "", 12393 /* CMIC_LEDUP3_PORT_ORDER_REMAP_16_19 */ "", 12394 /* CMIC_LEDUP3_PORT_ORDER_REMAP_20_23 */ "", 12395 /* CMIC_LEDUP3_PORT_ORDER_REMAP_24_27 */ "", 12396 /* CMIC_LEDUP3_PORT_ORDER_REMAP_28_31 */ "", 12397 /* CMIC_LEDUP3_PORT_ORDER_REMAP_32_35 */ "", 12398 /* CMIC_LEDUP3_PORT_ORDER_REMAP_36_39 */ "", 12399 /* CMIC_LEDUP3_PORT_ORDER_REMAP_40_43 */ "", 12400 /* CMIC_LEDUP3_PORT_ORDER_REMAP_44_47 */ "", 12401 /* CMIC_LEDUP3_PORT_ORDER_REMAP_48_51 */ "", 12402 /* CMIC_LEDUP3_PORT_ORDER_REMAP_4_7 */ "", 12403 /* CMIC_LEDUP3_PORT_ORDER_REMAP_52_55 */ "", 12404 /* CMIC_LEDUP3_PORT_ORDER_REMAP_56_59 */ "", 12405 /* CMIC_LEDUP3_PORT_ORDER_REMAP_60_63 */ "", 12406 /* CMIC_LEDUP3_PORT_ORDER_REMAP_8_11 */ "", 12407 /* CMIC_LEDUP3_PROGRAM_RAM */ "", 12408 /* CMIC_LEDUP3_SCANCHAIN_ASSEMBLY_ST_ADDR */ "", 12409 /* CMIC_LEDUP3_SCANOUT_COUNT_UPPER */ "", 12410 /* CMIC_LEDUP3_STATUS */ "", 12411 /* CMIC_LEDUP3_TM_CONTROL */ "", 12412 /* CMIC_LEDUP4_CLK_DIV */ "", 12413 /* CMIC_LEDUP4_CLK_PARAMS */ "", 12414 /* CMIC_LEDUP4_CTRL */ "", 12415 /* CMIC_LEDUP4_DATA_RAM */ "", 12416 /* CMIC_LEDUP4_ECC_CONFIG */ "", 12417 /* CMIC_LEDUP4_ECC_INTR */ "", 12418 /* CMIC_LEDUP4_ECC_INTR_CLR */ "", 12419 /* CMIC_LEDUP4_ECC_INTR_ENABLE */ "", 12420 /* CMIC_LEDUP4_ECC_STATUS */ "", 12421 /* CMIC_LEDUP4_PORT_ORDER_REMAP_0_3 */ "", 12422 /* CMIC_LEDUP4_PORT_ORDER_REMAP_12_15 */ "", 12423 /* CMIC_LEDUP4_PORT_ORDER_REMAP_16_19 */ "", 12424 /* CMIC_LEDUP4_PORT_ORDER_REMAP_20_23 */ "", 12425 /* CMIC_LEDUP4_PORT_ORDER_REMAP_24_27 */ "", 12426 /* CMIC_LEDUP4_PORT_ORDER_REMAP_28_31 */ "", 12427 /* CMIC_LEDUP4_PORT_ORDER_REMAP_32_35 */ "", 12428 /* CMIC_LEDUP4_PORT_ORDER_REMAP_36_39 */ "", 12429 /* CMIC_LEDUP4_PORT_ORDER_REMAP_40_43 */ "", 12430 /* CMIC_LEDUP4_PORT_ORDER_REMAP_44_47 */ "", 12431 /* CMIC_LEDUP4_PORT_ORDER_REMAP_48_51 */ "", 12432 /* CMIC_LEDUP4_PORT_ORDER_REMAP_4_7 */ "", 12433 /* CMIC_LEDUP4_PORT_ORDER_REMAP_52_55 */ "", 12434 /* CMIC_LEDUP4_PORT_ORDER_REMAP_56_59 */ "", 12435 /* CMIC_LEDUP4_PORT_ORDER_REMAP_60_63 */ "", 12436 /* CMIC_LEDUP4_PORT_ORDER_REMAP_8_11 */ "", 12437 /* CMIC_LEDUP4_PROGRAM_RAM */ "", 12438 /* CMIC_LEDUP4_SCANCHAIN_ASSEMBLY_ST_ADDR */ "", 12439 /* CMIC_LEDUP4_SCANOUT_COUNT_UPPER */ "", 12440 /* CMIC_LEDUP4_STATUS */ "", 12441 /* CMIC_LEDUP4_TM_CONTROL */ "", 12442 /* CMIC_LEDUP_CTRL */ "", 12443 /* CMIC_LEDUP_DATA_RAM */ "", 12444 /* CMIC_LEDUP_PROGRAM_RAM */ "", 12445 /* CMIC_LEDUP_STATUS */ "", 12446 /* CMIC_LED_PORT_ORDER_REMAP_0_4 */ "", 12447 /* CMIC_LED_PORT_ORDER_REMAP_10_14 */ "", 12448 /* CMIC_LED_PORT_ORDER_REMAP_15_19 */ "", 12449 /* CMIC_LED_PORT_ORDER_REMAP_20_24 */ "", 12450 /* CMIC_LED_PORT_ORDER_REMAP_25_29 */ "", 12451 /* CMIC_LED_PORT_ORDER_REMAP_30_34 */ "", 12452 /* CMIC_LED_PORT_ORDER_REMAP_35_39 */ "", 12453 /* CMIC_LED_PORT_ORDER_REMAP_40_44 */ "", 12454 /* CMIC_LED_PORT_ORDER_REMAP_45_49 */ "", 12455 /* CMIC_LED_PORT_ORDER_REMAP_50_54 */ "", 12456 /* CMIC_LED_PORT_ORDER_REMAP_5_9 */ "", 12457 /* CMIC_LINK_STAT */ "", 12458 /* CMIC_LINK_STATUS_CHANGE_STICKY */ "", 12459 /* CMIC_LINK_STAT_HI */ "", 12460 /* CMIC_LINK_STAT_HI_2 */ "", 12461 /* CMIC_LINK_STAT_HI_3 */ "", 12462 /* CMIC_MCS_IC_AR_ARB_MI0 */ "", 12463 /* CMIC_MCS_IC_AR_ARB_MI1 */ "", 12464 /* CMIC_MCS_IC_AR_ARB_MI2 */ "", 12465 /* CMIC_MCS_IC_AR_ARB_MI3 */ "", 12466 /* CMIC_MCS_IC_AR_ARB_MI4 */ "", 12467 /* CMIC_MCS_IC_AR_ARB_MI5 */ "", 12468 /* CMIC_MCS_IC_AR_ARB_MI6 */ "", 12469 /* CMIC_MCS_IC_AR_ARB_MI7 */ "", 12470 /* CMIC_MCS_IC_AR_ARB_MI8 */ "", 12471 /* CMIC_MCS_IC_AR_ARB_MI9 */ "", 12472 /* CMIC_MCS_IC_AR_ARB_MI10 */ "", 12473 /* CMIC_MCS_IC_AR_ARB_MI11 */ "", 12474 /* CMIC_MCS_IC_AR_ARB_MI12 */ "", 12475 /* CMIC_MCS_IC_AR_ARB_MI13 */ "", 12476 /* CMIC_MCS_IC_AW_ARB_MI0 */ "", 12477 /* CMIC_MCS_IC_AW_ARB_MI1 */ "", 12478 /* CMIC_MCS_IC_AW_ARB_MI2 */ "", 12479 /* CMIC_MCS_IC_AW_ARB_MI3 */ "", 12480 /* CMIC_MCS_IC_AW_ARB_MI4 */ "", 12481 /* CMIC_MCS_IC_AW_ARB_MI5 */ "", 12482 /* CMIC_MCS_IC_AW_ARB_MI6 */ "", 12483 /* CMIC_MCS_IC_AW_ARB_MI7 */ "", 12484 /* CMIC_MCS_IC_AW_ARB_MI8 */ "", 12485 /* CMIC_MCS_IC_AW_ARB_MI9 */ "", 12486 /* CMIC_MCS_IC_AW_ARB_MI10 */ "", 12487 /* CMIC_MCS_IC_AW_ARB_MI11 */ "", 12488 /* CMIC_MCS_IC_AW_ARB_MI12 */ "", 12489 /* CMIC_MCS_IC_AW_ARB_MI13 */ "", 12490 /* CMIC_MCS_IC_CFG_REG_0 */ "", 12491 /* CMIC_MCS_IC_CFG_REG_1 */ "", 12492 /* CMIC_MCS_IC_CFG_REG_2 */ "", 12493 /* CMIC_MCS_IC_ID_REG_0 */ "", 12494 /* CMIC_MCS_IC_ID_REG_1 */ "", 12495 /* CMIC_MCS_IC_ID_REG_2 */ "", 12496 /* CMIC_MCS_IC_ID_REG_3 */ "", 12497 /* CMIC_MCS_IC_PER_REG_0 */ "", 12498 /* CMIC_MCS_IC_PER_REG_1 */ "", 12499 /* CMIC_MCS_IC_PER_REG_2 */ "", 12500 /* CMIC_MCS_IC_PER_REG_3 */ "", 12501 /* CMIC_MIIM_ADDRESS */ "", 12502 /* CMIC_MIIM_AUTO_SCAN_ADDRESS */ "", 12503 /* CMIC_MIIM_BUS_MAP_19_10 */ "", 12504 /* CMIC_MIIM_BUS_MAP_29_20 */ "", 12505 /* CMIC_MIIM_BUS_MAP_39_30 */ "", 12506 /* CMIC_MIIM_BUS_MAP_49_40 */ "", 12507 /* CMIC_MIIM_BUS_MAP_59_50 */ "", 12508 /* CMIC_MIIM_BUS_MAP_69_60 */ "", 12509 /* CMIC_MIIM_BUS_MAP_79_70 */ "", 12510 /* CMIC_MIIM_BUS_MAP_9_0 */ "", 12511 /* CMIC_MIIM_BUS_SEL_MAP_103_96 */ "", 12512 /* CMIC_MIIM_BUS_SEL_MAP_109_100 */ "", 12513 /* CMIC_MIIM_BUS_SEL_MAP_111_104 */ "", 12514 /* CMIC_MIIM_BUS_SEL_MAP_119_110 */ "", 12515 /* CMIC_MIIM_BUS_SEL_MAP_119_112 */ "", 12516 /* CMIC_MIIM_BUS_SEL_MAP_127_120 */ "", 12517 /* CMIC_MIIM_BUS_SEL_MAP_129_120 */ "", 12518 /* CMIC_MIIM_BUS_SEL_MAP_135_128 */ "", 12519 /* CMIC_MIIM_BUS_SEL_MAP_139_130 */ "", 12520 /* CMIC_MIIM_BUS_SEL_MAP_143_136 */ "", 12521 /* CMIC_MIIM_BUS_SEL_MAP_149_140 */ "", 12522 /* CMIC_MIIM_BUS_SEL_MAP_151_144 */ "", 12523 /* CMIC_MIIM_BUS_SEL_MAP_159_150 */ "", 12524 /* CMIC_MIIM_BUS_SEL_MAP_159_152 */ "", 12525 /* CMIC_MIIM_BUS_SEL_MAP_15_8 */ "", 12526 /* CMIC_MIIM_BUS_SEL_MAP_167_160 */ "", 12527 /* CMIC_MIIM_BUS_SEL_MAP_169_160 */ "", 12528 /* CMIC_MIIM_BUS_SEL_MAP_175_168 */ "", 12529 /* CMIC_MIIM_BUS_SEL_MAP_179_170 */ "", 12530 /* CMIC_MIIM_BUS_SEL_MAP_183_176 */ "", 12531 /* CMIC_MIIM_BUS_SEL_MAP_189_180 */ "", 12532 /* CMIC_MIIM_BUS_SEL_MAP_191_184 */ "", 12533 /* CMIC_MIIM_BUS_SEL_MAP_191_190 */ "", 12534 /* CMIC_MIIM_BUS_SEL_MAP_199_192 */ "", 12535 /* CMIC_MIIM_BUS_SEL_MAP_19_10 */ "", 12536 /* CMIC_MIIM_BUS_SEL_MAP_207_200 */ "", 12537 /* CMIC_MIIM_BUS_SEL_MAP_215_208 */ "", 12538 /* CMIC_MIIM_BUS_SEL_MAP_223_216 */ "", 12539 /* CMIC_MIIM_BUS_SEL_MAP_231_224 */ "", 12540 /* CMIC_MIIM_BUS_SEL_MAP_239_232 */ "", 12541 /* CMIC_MIIM_BUS_SEL_MAP_23_16 */ "", 12542 /* CMIC_MIIM_BUS_SEL_MAP_247_240 */ "", 12543 /* CMIC_MIIM_BUS_SEL_MAP_255_248 */ "", 12544 /* CMIC_MIIM_BUS_SEL_MAP_263_256 */ "", 12545 /* CMIC_MIIM_BUS_SEL_MAP_271_264 */ "", 12546 /* CMIC_MIIM_BUS_SEL_MAP_279_272 */ "", 12547 /* CMIC_MIIM_BUS_SEL_MAP_287_280 */ "", 12548 /* CMIC_MIIM_BUS_SEL_MAP_295_288 */ "", 12549 /* CMIC_MIIM_BUS_SEL_MAP_29_20 */ "", 12550 /* CMIC_MIIM_BUS_SEL_MAP_303_296 */ "", 12551 /* CMIC_MIIM_BUS_SEL_MAP_311_304 */ "", 12552 /* CMIC_MIIM_BUS_SEL_MAP_319_312 */ "", 12553 /* CMIC_MIIM_BUS_SEL_MAP_31_24 */ "", 12554 /* CMIC_MIIM_BUS_SEL_MAP_39_30 */ "", 12555 /* CMIC_MIIM_BUS_SEL_MAP_39_32 */ "", 12556 /* CMIC_MIIM_BUS_SEL_MAP_47_40 */ "", 12557 /* CMIC_MIIM_BUS_SEL_MAP_49_40 */ "", 12558 /* CMIC_MIIM_BUS_SEL_MAP_55_48 */ "", 12559 /* CMIC_MIIM_BUS_SEL_MAP_59_50 */ "", 12560 /* CMIC_MIIM_BUS_SEL_MAP_63_56 */ "", 12561 /* CMIC_MIIM_BUS_SEL_MAP_69_60 */ "", 12562 /* CMIC_MIIM_BUS_SEL_MAP_71_64 */ "", 12563 /* CMIC_MIIM_BUS_SEL_MAP_79_70 */ "", 12564 /* CMIC_MIIM_BUS_SEL_MAP_79_72 */ "", 12565 /* CMIC_MIIM_BUS_SEL_MAP_7_0 */ "", 12566 /* CMIC_MIIM_BUS_SEL_MAP_87_80 */ "", 12567 /* CMIC_MIIM_BUS_SEL_MAP_89_80 */ "", 12568 /* CMIC_MIIM_BUS_SEL_MAP_95_88 */ "", 12569 /* CMIC_MIIM_BUS_SEL_MAP_95_90 */ "", 12570 /* CMIC_MIIM_BUS_SEL_MAP_99_90 */ "", 12571 /* CMIC_MIIM_BUS_SEL_MAP_9_0 */ "", 12572 /* CMIC_MIIM_CLR_SCAN_STATUS */ "", 12573 /* CMIC_MIIM_CONFIG */ "", 12574 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_103_100 */ "", 12575 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_107_104 */ "", 12576 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_111_108 */ "", 12577 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_115_112 */ "", 12578 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_119_116 */ "", 12579 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_11_8 */ "", 12580 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_123_120 */ "", 12581 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_127_124 */ "", 12582 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_131_128 */ "", 12583 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_135_132 */ "", 12584 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_139_136 */ "", 12585 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_143_140 */ "", 12586 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_147_144 */ "", 12587 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_151_148 */ "", 12588 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_155_152 */ "", 12589 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_159_156 */ "", 12590 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_15_12 */ "", 12591 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_163_160 */ "", 12592 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_167_164 */ "", 12593 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_171_168 */ "", 12594 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_175_172 */ "", 12595 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_179_176 */ "", 12596 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_183_180 */ "", 12597 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_187_184 */ "", 12598 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_191_188 */ "", 12599 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_195_192 */ "", 12600 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_199_196 */ "", 12601 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_19_16 */ "", 12602 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_203_200 */ "", 12603 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_207_204 */ "", 12604 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_211_208 */ "", 12605 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_215_212 */ "", 12606 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_219_216 */ "", 12607 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_223_220 */ "", 12608 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_227_224 */ "", 12609 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_231_228 */ "", 12610 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_235_232 */ "", 12611 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_239_236 */ "", 12612 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_23_20 */ "", 12613 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_243_240 */ "", 12614 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_247_244 */ "", 12615 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_251_248 */ "", 12616 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_255_252 */ "", 12617 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_259_256 */ "", 12618 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_263_260 */ "", 12619 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_267_264 */ "", 12620 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_271_268 */ "", 12621 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_275_272 */ "", 12622 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_279_276 */ "", 12623 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_27_24 */ "", 12624 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_283_280 */ "", 12625 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_287_284 */ "", 12626 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_291_288 */ "", 12627 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_295_292 */ "", 12628 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_299_296 */ "", 12629 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_303_300 */ "", 12630 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_307_304 */ "", 12631 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_311_308 */ "", 12632 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_315_312 */ "", 12633 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_319_316 */ "", 12634 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_31_28 */ "", 12635 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_35_32 */ "", 12636 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_39_36 */ "", 12637 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_3_0 */ "", 12638 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_43_40 */ "", 12639 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_47_44 */ "", 12640 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_51_48 */ "", 12641 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_55_52 */ "", 12642 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_59_56 */ "", 12643 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_63_60 */ "", 12644 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_67_64 */ "", 12645 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_71_68 */ "", 12646 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_75_72 */ "", 12647 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_79_76 */ "", 12648 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_7_4 */ "", 12649 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_83_80 */ "", 12650 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_87_84 */ "", 12651 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_91_88 */ "", 12652 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_95_92 */ "", 12653 /* CMIC_MIIM_EXT_PHY_ADDR_MAP_99_96 */ "", 12654 /* CMIC_MIIM_INT_SEL_MAP */ "", 12655 /* CMIC_MIIM_INT_SEL_MAP_0 */ "", 12656 /* CMIC_MIIM_INT_SEL_MAP_1 */ "", 12657 /* CMIC_MIIM_INT_SEL_MAP_2 */ "", 12658 /* CMIC_MIIM_INT_SEL_MAP_3 */ "", 12659 /* CMIC_MIIM_INT_SEL_MAP_4 */ "", 12660 /* CMIC_MIIM_INT_SEL_MAP_5 */ "", 12661 /* CMIC_MIIM_INT_SEL_MAP_6 */ "", 12662 /* CMIC_MIIM_INT_SEL_MAP_7 */ "", 12663 /* CMIC_MIIM_INT_SEL_MAP_8 */ "", 12664 /* CMIC_MIIM_INT_SEL_MAP_9 */ "", 12665 /* CMIC_MIIM_INT_SEL_MAP_HI */ "", 12666 /* CMIC_MIIM_INT_SEL_MAP_HI_2 */ "", 12667 /* CMIC_MIIM_INT_SEL_MAP_HI_3 */ "", 12668 /* CMIC_MIIM_LINK_STATUS_0 */ "", 12669 /* CMIC_MIIM_LINK_STATUS_1 */ "", 12670 /* CMIC_MIIM_LINK_STATUS_2 */ "", 12671 /* CMIC_MIIM_LINK_STATUS_3 */ "", 12672 /* CMIC_MIIM_LINK_STATUS_4 */ "", 12673 /* CMIC_MIIM_LINK_STATUS_5 */ "", 12674 /* CMIC_MIIM_LINK_STATUS_6 */ "", 12675 /* CMIC_MIIM_LINK_STATUS_7 */ "", 12676 /* CMIC_MIIM_LINK_STATUS_8 */ "", 12677 /* CMIC_MIIM_LINK_STATUS_9 */ "", 12678 /* CMIC_MIIM_PARAM */ "", 12679 /* CMIC_MIIM_PAUSE_MIIM_ADDRESS */ "", 12680 /* CMIC_MIIM_PAUSE_SCAN_PORTS_0 */ "", 12681 /* CMIC_MIIM_PAUSE_SCAN_PORTS_1 */ "", 12682 /* CMIC_MIIM_PAUSE_SCAN_PORTS_2 */ "", 12683 /* CMIC_MIIM_PAUSE_SCAN_PORTS_3 */ "", 12684 /* CMIC_MIIM_PAUSE_SCAN_PORTS_4 */ "", 12685 /* CMIC_MIIM_PAUSE_SCAN_PORTS_5 */ "", 12686 /* CMIC_MIIM_PAUSE_SCAN_PORTS_6 */ "", 12687 /* CMIC_MIIM_PAUSE_SCAN_PORTS_7 */ "", 12688 /* CMIC_MIIM_PAUSE_SCAN_PORTS_8 */ "", 12689 /* CMIC_MIIM_PAUSE_SCAN_PORTS_9 */ "", 12690 /* CMIC_MIIM_PORT_TYPE_MAP */ "", 12691 /* CMIC_MIIM_PORT_TYPE_MAP_BUS2 */ "", 12692 /* CMIC_MIIM_PORT_TYPE_MAP_BUS2_HI */ "", 12693 /* CMIC_MIIM_PORT_TYPE_MAP_HI */ "", 12694 /* CMIC_MIIM_PROTOCOL_MAP */ "", 12695 /* CMIC_MIIM_PROTOCOL_MAP_0 */ "", 12696 /* CMIC_MIIM_PROTOCOL_MAP_1 */ "", 12697 /* CMIC_MIIM_PROTOCOL_MAP_2 */ "", 12698 /* CMIC_MIIM_PROTOCOL_MAP_3 */ "", 12699 /* CMIC_MIIM_PROTOCOL_MAP_4 */ "", 12700 /* CMIC_MIIM_PROTOCOL_MAP_5 */ "", 12701 /* CMIC_MIIM_PROTOCOL_MAP_6 */ "", 12702 /* CMIC_MIIM_PROTOCOL_MAP_7 */ "", 12703 /* CMIC_MIIM_PROTOCOL_MAP_8 */ "", 12704 /* CMIC_MIIM_PROTOCOL_MAP_9 */ "", 12705 /* CMIC_MIIM_PROTOCOL_MAP_HI */ "", 12706 /* CMIC_MIIM_PROTOCOL_MAP_HI_2 */ "", 12707 /* CMIC_MIIM_READ_DATA */ "", 12708 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_0 */ "", 12709 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_1 */ "", 12710 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_2 */ "", 12711 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_3 */ "", 12712 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_4 */ "", 12713 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_5 */ "", 12714 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_6 */ "", 12715 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_7 */ "", 12716 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_8 */ "", 12717 /* CMIC_MIIM_RX_PAUSE_CAPABILITY_9 */ "", 12718 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_0 */ "", 12719 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_1 */ "", 12720 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_2 */ "", 12721 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_3 */ "", 12722 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_4 */ "", 12723 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_5 */ "", 12724 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_6 */ "", 12725 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_7 */ "", 12726 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_8 */ "", 12727 /* CMIC_MIIM_RX_PAUSE_OVERRIDE_CONTROL_9 */ "", 12728 /* CMIC_MIIM_RX_PAUSE_STATUS_0 */ "", 12729 /* CMIC_MIIM_RX_PAUSE_STATUS_1 */ "", 12730 /* CMIC_MIIM_RX_PAUSE_STATUS_2 */ "", 12731 /* CMIC_MIIM_RX_PAUSE_STATUS_3 */ "", 12732 /* CMIC_MIIM_RX_PAUSE_STATUS_4 */ "", 12733 /* CMIC_MIIM_RX_PAUSE_STATUS_5 */ "", 12734 /* CMIC_MIIM_RX_PAUSE_STATUS_6 */ "", 12735 /* CMIC_MIIM_RX_PAUSE_STATUS_7 */ "", 12736 /* CMIC_MIIM_RX_PAUSE_STATUS_8 */ "", 12737 /* CMIC_MIIM_RX_PAUSE_STATUS_9 */ "", 12738 /* CMIC_MIIM_SCAN_CTRL */ "", 12739 /* CMIC_MIIM_SCAN_PORTS_0 */ "", 12740 /* CMIC_MIIM_SCAN_PORTS_1 */ "", 12741 /* CMIC_MIIM_SCAN_PORTS_2 */ "", 12742 /* CMIC_MIIM_SCAN_PORTS_3 */ "", 12743 /* CMIC_MIIM_SCAN_PORTS_4 */ "", 12744 /* CMIC_MIIM_SCAN_PORTS_5 */ "", 12745 /* CMIC_MIIM_SCAN_PORTS_6 */ "", 12746 /* CMIC_MIIM_SCAN_PORTS_7 */ "", 12747 /* CMIC_MIIM_SCAN_PORTS_8 */ "", 12748 /* CMIC_MIIM_SCAN_PORTS_9 */ "", 12749 /* CMIC_MIIM_SCAN_STATUS */ "", 12750 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_0 */ "", 12751 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_1 */ "", 12752 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_2 */ "", 12753 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_3 */ "", 12754 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_4 */ "", 12755 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_5 */ "", 12756 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_6 */ "", 12757 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_7 */ "", 12758 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_8 */ "", 12759 /* CMIC_MIIM_TX_PAUSE_CAPABILITY_9 */ "", 12760 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_0 */ "", 12761 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_1 */ "", 12762 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_2 */ "", 12763 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_3 */ "", 12764 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_4 */ "", 12765 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_5 */ "", 12766 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_6 */ "", 12767 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_7 */ "", 12768 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_8 */ "", 12769 /* CMIC_MIIM_TX_PAUSE_OVERRIDE_CONTROL_9 */ "", 12770 /* CMIC_MIIM_TX_PAUSE_STATUS_0 */ "", 12771 /* CMIC_MIIM_TX_PAUSE_STATUS_1 */ "", 12772 /* CMIC_MIIM_TX_PAUSE_STATUS_2 */ "", 12773 /* CMIC_MIIM_TX_PAUSE_STATUS_3 */ "", 12774 /* CMIC_MIIM_TX_PAUSE_STATUS_4 */ "", 12775 /* CMIC_MIIM_TX_PAUSE_STATUS_5 */ "", 12776 /* CMIC_MIIM_TX_PAUSE_STATUS_6 */ "", 12777 /* CMIC_MIIM_TX_PAUSE_STATUS_7 */ "", 12778 /* CMIC_MIIM_TX_PAUSE_STATUS_8 */ "", 12779 /* CMIC_MIIM_TX_PAUSE_STATUS_9 */ "", 12780 /* CMIC_MISC_CONTROL */ "", 12781 /* CMIC_MISC_STATUS */ "", 12782 /* CMIC_MMU_COSLC_COUNT_ADDR */ "", 12783 /* CMIC_MMU_COSLC_COUNT_DATA */ "", 12784 /* CMIC_OVERRIDE_STRAP */ "", 12785 /* CMIC_PAUSE_MIIM_ADDRESS */ "", 12786 /* CMIC_PAUSE_SCAN_PORTS */ "", 12787 /* CMIC_PCIE_CFG_ADDRESS */ "", 12788 /* CMIC_PCIE_CFG_READ_DATA */ "", 12789 /* CMIC_PCIE_CFG_WRITE_DATA */ "", 12790 /* CMIC_PCIE_CONFIG */ "", 12791 /* CMIC_PCIE_ERROR_STATUS */ "", 12792 /* CMIC_PCIE_ERROR_STATUS_CLR */ "", 12793 /* CMIC_PCIE_MISCEL */ "", 12794 /* CMIC_PCIE_USERIF_PURGE_CONTROL */ "", 12795 /* CMIC_PCIE_USERIF_PURGE_STATUS */ "", 12796 /* CMIC_PCIE_USERIF_STATUS */ "", 12797 /* CMIC_PCIE_USERIF_STATUS_CLR */ "", 12798 /* CMIC_PCIE_USERIF_STATUS_MASK */ "", 12799 /* CMIC_PCIE_USERIF_TIMEOUT */ "", 12800 /* CMIC_PEAK_THERMAL_MON_RESULT */ "", 12801 /* CMIC_PIO_IC_AR_ARB_MI0 */ "", 12802 /* CMIC_PIO_IC_AR_ARB_MI1 */ "", 12803 /* CMIC_PIO_IC_AR_ARB_MI2 */ "", 12804 /* CMIC_PIO_IC_AR_ARB_MI3 */ "", 12805 /* CMIC_PIO_IC_AR_ARB_MI4 */ "", 12806 /* CMIC_PIO_IC_AR_ARB_MI5 */ "", 12807 /* CMIC_PIO_IC_AR_ARB_MI6 */ "", 12808 /* CMIC_PIO_IC_AR_ARB_MI7 */ "", 12809 /* CMIC_PIO_IC_AW_ARB_MI0 */ "", 12810 /* CMIC_PIO_IC_AW_ARB_MI1 */ "", 12811 /* CMIC_PIO_IC_AW_ARB_MI2 */ "", 12812 /* CMIC_PIO_IC_AW_ARB_MI3 */ "", 12813 /* CMIC_PIO_IC_AW_ARB_MI4 */ "", 12814 /* CMIC_PIO_IC_AW_ARB_MI5 */ "", 12815 /* CMIC_PIO_IC_AW_ARB_MI6 */ "", 12816 /* CMIC_PIO_IC_AW_ARB_MI7 */ "", 12817 /* CMIC_PIO_IC_CFG_REG_0 */ "", 12818 /* CMIC_PIO_IC_CFG_REG_1 */ "", 12819 /* CMIC_PIO_IC_CFG_REG_2 */ "", 12820 /* CMIC_PIO_IC_ID_REG_0 */ "", 12821 /* CMIC_PIO_IC_ID_REG_1 */ "", 12822 /* CMIC_PIO_IC_ID_REG_2 */ "", 12823 /* CMIC_PIO_IC_ID_REG_3 */ "", 12824 /* CMIC_PIO_IC_PER_REG_0 */ "", 12825 /* CMIC_PIO_IC_PER_REG_1 */ "", 12826 /* CMIC_PIO_IC_PER_REG_2 */ "", 12827 /* CMIC_PIO_IC_PER_REG_3 */ "", 12828 /* CMIC_PIO_MCS_ACCESS_PAGE */ "", 12829 /* CMIC_PIO_WAIT_CYCLES */ "", 12830 /* CMIC_PKT_COS */ "", 12831 /* CMIC_PKT_COS_0 */ "", 12832 /* CMIC_PKT_COS_1 */ "", 12833 /* CMIC_PKT_COS_HI */ "", 12834 /* CMIC_PKT_COS_QUEUES_HI */ "", 12835 /* CMIC_PKT_COS_QUEUES_LO */ "", 12836 /* CMIC_PKT_COUNT_FROMCPU */ "", 12837 /* CMIC_PKT_COUNT_FROMCPU_MH */ "", 12838 /* CMIC_PKT_COUNT_INTR */ "", 12839 /* CMIC_PKT_COUNT_PIO */ "", 12840 /* CMIC_PKT_COUNT_PIO_REPLY */ "", 12841 /* CMIC_PKT_COUNT_SCHAN */ "", 12842 /* CMIC_PKT_COUNT_SCHAN_REP */ "", 12843 /* CMIC_PKT_COUNT_TOCPUD */ "", 12844 /* CMIC_PKT_COUNT_TOCPUDM */ "", 12845 /* CMIC_PKT_COUNT_TOCPUE */ "", 12846 /* CMIC_PKT_COUNT_TOCPUEM */ "", 12847 /* CMIC_PKT_COUNT_TOCPUN */ "", 12848 /* CMIC_PKT_CTRL */ "", 12849 /* CMIC_PKT_ETHER_SIG */ "", 12850 /* CMIC_PKT_LMAC0_HI */ "", 12851 /* CMIC_PKT_LMAC0_LO */ "", 12852 /* CMIC_PKT_LMAC1_HI */ "", 12853 /* CMIC_PKT_LMAC1_LO */ "", 12854 /* CMIC_PKT_PORTS */ "", 12855 /* CMIC_PKT_PORTS_0 */ "", 12856 /* CMIC_PKT_PORTS_1 */ "", 12857 /* CMIC_PKT_PORTS_2 */ "", 12858 /* CMIC_PKT_PORTS_3 */ "", 12859 /* CMIC_PKT_PORTS_4 */ "", 12860 /* CMIC_PKT_PORTS_5 */ "", 12861 /* CMIC_PKT_PORTS_6 */ "", 12862 /* CMIC_PKT_PORTS_7 */ "", 12863 /* CMIC_PKT_PORTS_HI */ "", 12864 /* CMIC_PKT_PORTS_HI_2 */ "", 12865 /* CMIC_PKT_PRI_MAP_TABLE */ "", 12866 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_0 */ "", 12867 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_1 */ "", 12868 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_2 */ "", 12869 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_3 */ "", 12870 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_4 */ "", 12871 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_5 */ "", 12872 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_6 */ "", 12873 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_7 */ "", 12874 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_8 */ "", 12875 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_9 */ "", 12876 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_10 */ "", 12877 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_11 */ "", 12878 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_12 */ "", 12879 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_13 */ "", 12880 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_14 */ "", 12881 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_15 */ "", 12882 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_16 */ "", 12883 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_17 */ "", 12884 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_18 */ "", 12885 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_19 */ "", 12886 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_20 */ "", 12887 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_21 */ "", 12888 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_22 */ "", 12889 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_23 */ "", 12890 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_24 */ "", 12891 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_25 */ "", 12892 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_26 */ "", 12893 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_27 */ "", 12894 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_28 */ "", 12895 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_29 */ "", 12896 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_30 */ "", 12897 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_31 */ "", 12898 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_32 */ "", 12899 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_33 */ "", 12900 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_34 */ "", 12901 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_35 */ "", 12902 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_36 */ "", 12903 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_37 */ "", 12904 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_38 */ "", 12905 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_39 */ "", 12906 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_40 */ "", 12907 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_41 */ "", 12908 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_42 */ "", 12909 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_43 */ "", 12910 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_44 */ "", 12911 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_45 */ "", 12912 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_46 */ "", 12913 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_47 */ "", 12914 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_48 */ "", 12915 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_49 */ "", 12916 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_50 */ "", 12917 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_51 */ "", 12918 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_52 */ "", 12919 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_53 */ "", 12920 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_54 */ "", 12921 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_55 */ "", 12922 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_56 */ "", 12923 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_57 */ "", 12924 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_58 */ "", 12925 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_59 */ "", 12926 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_60 */ "", 12927 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_61 */ "", 12928 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_62 */ "", 12929 /* CMIC_PKT_PRI_MAP_TABLE_ENTRY_63 */ "", 12930 /* CMIC_PKT_REASON */ "", 12931 /* CMIC_PKT_REASON_0_TYPE */ "", 12932 /* CMIC_PKT_REASON_0_TYPE0 */ "", 12933 /* CMIC_PKT_REASON_0_TYPE1 */ "", 12934 /* CMIC_PKT_REASON_0_TYPE2 */ "", 12935 /* CMIC_PKT_REASON_0_TYPE3 */ "", 12936 /* CMIC_PKT_REASON_0_TYPE4 */ "", 12937 /* CMIC_PKT_REASON_0_TYPE5 */ "", 12938 /* CMIC_PKT_REASON_0_TYPE6 */ "", 12939 /* CMIC_PKT_REASON_0_TYPE7 */ "", 12940 /* CMIC_PKT_REASON_0_TYPE8 */ "", 12941 /* CMIC_PKT_REASON_0_TYPE9 */ "", 12942 /* CMIC_PKT_REASON_0_TYPE10 */ "", 12943 /* CMIC_PKT_REASON_0_TYPE11 */ "", 12944 /* CMIC_PKT_REASON_0_TYPE12 */ "", 12945 /* CMIC_PKT_REASON_0_TYPE13 */ "", 12946 /* CMIC_PKT_REASON_0_TYPE14 */ "", 12947 /* CMIC_PKT_REASON_0_TYPE15 */ "", 12948 /* CMIC_PKT_REASON_1_TYPE */ "", 12949 /* CMIC_PKT_REASON_1_TYPE0 */ "", 12950 /* CMIC_PKT_REASON_1_TYPE1 */ "", 12951 /* CMIC_PKT_REASON_1_TYPE2 */ "", 12952 /* CMIC_PKT_REASON_1_TYPE3 */ "", 12953 /* CMIC_PKT_REASON_1_TYPE4 */ "", 12954 /* CMIC_PKT_REASON_1_TYPE5 */ "", 12955 /* CMIC_PKT_REASON_1_TYPE6 */ "", 12956 /* CMIC_PKT_REASON_1_TYPE7 */ "", 12957 /* CMIC_PKT_REASON_1_TYPE8 */ "", 12958 /* CMIC_PKT_REASON_1_TYPE9 */ "", 12959 /* CMIC_PKT_REASON_1_TYPE10 */ "", 12960 /* CMIC_PKT_REASON_1_TYPE11 */ "", 12961 /* CMIC_PKT_REASON_1_TYPE12 */ "", 12962 /* CMIC_PKT_REASON_1_TYPE13 */ "", 12963 /* CMIC_PKT_REASON_1_TYPE14 */ "", 12964 /* CMIC_PKT_REASON_1_TYPE15 */ "", 12965 /* CMIC_PKT_REASON_2_TYPE */ "", 12966 /* CMIC_PKT_REASON_2_TYPE0 */ "", 12967 /* CMIC_PKT_REASON_2_TYPE1 */ "", 12968 /* CMIC_PKT_REASON_2_TYPE2 */ "", 12969 /* CMIC_PKT_REASON_2_TYPE3 */ "", 12970 /* CMIC_PKT_REASON_2_TYPE4 */ "", 12971 /* CMIC_PKT_REASON_2_TYPE5 */ "", 12972 /* CMIC_PKT_REASON_2_TYPE6 */ "", 12973 /* CMIC_PKT_REASON_2_TYPE7 */ "", 12974 /* CMIC_PKT_REASON_2_TYPE8 */ "", 12975 /* CMIC_PKT_REASON_2_TYPE9 */ "", 12976 /* CMIC_PKT_REASON_2_TYPE10 */ "", 12977 /* CMIC_PKT_REASON_2_TYPE11 */ "", 12978 /* CMIC_PKT_REASON_2_TYPE12 */ "", 12979 /* CMIC_PKT_REASON_2_TYPE13 */ "", 12980 /* CMIC_PKT_REASON_2_TYPE14 */ "", 12981 /* CMIC_PKT_REASON_2_TYPE15 */ "", 12982 /* CMIC_PKT_REASON_DIRECT */ "", 12983 /* CMIC_PKT_REASON_DIRECT_0_TYPE */ "", 12984 /* CMIC_PKT_REASON_DIRECT_0_TYPE0 */ "", 12985 /* CMIC_PKT_REASON_DIRECT_0_TYPE1 */ "", 12986 /* CMIC_PKT_REASON_DIRECT_0_TYPE2 */ "", 12987 /* CMIC_PKT_REASON_DIRECT_0_TYPE3 */ "", 12988 /* CMIC_PKT_REASON_DIRECT_0_TYPE4 */ "", 12989 /* CMIC_PKT_REASON_DIRECT_0_TYPE5 */ "", 12990 /* CMIC_PKT_REASON_DIRECT_0_TYPE6 */ "", 12991 /* CMIC_PKT_REASON_DIRECT_0_TYPE7 */ "", 12992 /* CMIC_PKT_REASON_DIRECT_0_TYPE8 */ "", 12993 /* CMIC_PKT_REASON_DIRECT_0_TYPE9 */ "", 12994 /* CMIC_PKT_REASON_DIRECT_0_TYPE10 */ "", 12995 /* CMIC_PKT_REASON_DIRECT_0_TYPE11 */ "", 12996 /* CMIC_PKT_REASON_DIRECT_0_TYPE12 */ "", 12997 /* CMIC_PKT_REASON_DIRECT_0_TYPE13 */ "", 12998 /* CMIC_PKT_REASON_DIRECT_0_TYPE14 */ "", 12999 /* CMIC_PKT_REASON_DIRECT_0_TYPE15 */ "", 13000 /* CMIC_PKT_REASON_DIRECT_1_TYPE */ "", 13001 /* CMIC_PKT_REASON_DIRECT_1_TYPE0 */ "", 13002 /* CMIC_PKT_REASON_DIRECT_1_TYPE1 */ "", 13003 /* CMIC_PKT_REASON_DIRECT_1_TYPE2 */ "", 13004 /* CMIC_PKT_REASON_DIRECT_1_TYPE3 */ "", 13005 /* CMIC_PKT_REASON_DIRECT_1_TYPE4 */ "", 13006 /* CMIC_PKT_REASON_DIRECT_1_TYPE5 */ "", 13007 /* CMIC_PKT_REASON_DIRECT_1_TYPE6 */ "", 13008 /* CMIC_PKT_REASON_DIRECT_1_TYPE7 */ "", 13009 /* CMIC_PKT_REASON_DIRECT_1_TYPE8 */ "", 13010 /* CMIC_PKT_REASON_DIRECT_1_TYPE9 */ "", 13011 /* CMIC_PKT_REASON_DIRECT_1_TYPE10 */ "", 13012 /* CMIC_PKT_REASON_DIRECT_1_TYPE11 */ "", 13013 /* CMIC_PKT_REASON_DIRECT_1_TYPE12 */ "", 13014 /* CMIC_PKT_REASON_DIRECT_1_TYPE13 */ "", 13015 /* CMIC_PKT_REASON_DIRECT_1_TYPE14 */ "", 13016 /* CMIC_PKT_REASON_DIRECT_1_TYPE15 */ "", 13017 /* CMIC_PKT_REASON_DIRECT_2_TYPE */ "", 13018 /* CMIC_PKT_REASON_DIRECT_2_TYPE0 */ "", 13019 /* CMIC_PKT_REASON_DIRECT_2_TYPE1 */ "", 13020 /* CMIC_PKT_REASON_DIRECT_2_TYPE2 */ "", 13021 /* CMIC_PKT_REASON_DIRECT_2_TYPE3 */ "", 13022 /* CMIC_PKT_REASON_DIRECT_2_TYPE4 */ "", 13023 /* CMIC_PKT_REASON_DIRECT_2_TYPE5 */ "", 13024 /* CMIC_PKT_REASON_DIRECT_2_TYPE6 */ "", 13025 /* CMIC_PKT_REASON_DIRECT_2_TYPE7 */ "", 13026 /* CMIC_PKT_REASON_DIRECT_2_TYPE8 */ "", 13027 /* CMIC_PKT_REASON_DIRECT_2_TYPE9 */ "", 13028 /* CMIC_PKT_REASON_DIRECT_2_TYPE10 */ "", 13029 /* CMIC_PKT_REASON_DIRECT_2_TYPE11 */ "", 13030 /* CMIC_PKT_REASON_DIRECT_2_TYPE12 */ "", 13031 /* CMIC_PKT_REASON_DIRECT_2_TYPE13 */ "", 13032 /* CMIC_PKT_REASON_DIRECT_2_TYPE14 */ "", 13033 /* CMIC_PKT_REASON_DIRECT_2_TYPE15 */ "", 13034 /* CMIC_PKT_REASON_DIRECT_HI */ "", 13035 /* CMIC_PKT_REASON_HI */ "", 13036 /* CMIC_PKT_REASON_MINI */ "", 13037 /* CMIC_PKT_REASON_MINI_0_TYPE */ "", 13038 /* CMIC_PKT_REASON_MINI_0_TYPE0 */ "", 13039 /* CMIC_PKT_REASON_MINI_0_TYPE1 */ "", 13040 /* CMIC_PKT_REASON_MINI_0_TYPE2 */ "", 13041 /* CMIC_PKT_REASON_MINI_0_TYPE3 */ "", 13042 /* CMIC_PKT_REASON_MINI_0_TYPE4 */ "", 13043 /* CMIC_PKT_REASON_MINI_0_TYPE5 */ "", 13044 /* CMIC_PKT_REASON_MINI_0_TYPE6 */ "", 13045 /* CMIC_PKT_REASON_MINI_0_TYPE7 */ "", 13046 /* CMIC_PKT_REASON_MINI_0_TYPE8 */ "", 13047 /* CMIC_PKT_REASON_MINI_0_TYPE9 */ "", 13048 /* CMIC_PKT_REASON_MINI_0_TYPE10 */ "", 13049 /* CMIC_PKT_REASON_MINI_0_TYPE11 */ "", 13050 /* CMIC_PKT_REASON_MINI_0_TYPE12 */ "", 13051 /* CMIC_PKT_REASON_MINI_0_TYPE13 */ "", 13052 /* CMIC_PKT_REASON_MINI_0_TYPE14 */ "", 13053 /* CMIC_PKT_REASON_MINI_0_TYPE15 */ "", 13054 /* CMIC_PKT_REASON_MINI_1_TYPE */ "", 13055 /* CMIC_PKT_REASON_MINI_1_TYPE0 */ "", 13056 /* CMIC_PKT_REASON_MINI_1_TYPE1 */ "", 13057 /* CMIC_PKT_REASON_MINI_1_TYPE2 */ "", 13058 /* CMIC_PKT_REASON_MINI_1_TYPE3 */ "", 13059 /* CMIC_PKT_REASON_MINI_1_TYPE4 */ "", 13060 /* CMIC_PKT_REASON_MINI_1_TYPE5 */ "", 13061 /* CMIC_PKT_REASON_MINI_1_TYPE6 */ "", 13062 /* CMIC_PKT_REASON_MINI_1_TYPE7 */ "", 13063 /* CMIC_PKT_REASON_MINI_1_TYPE8 */ "", 13064 /* CMIC_PKT_REASON_MINI_1_TYPE9 */ "", 13065 /* CMIC_PKT_REASON_MINI_1_TYPE10 */ "", 13066 /* CMIC_PKT_REASON_MINI_1_TYPE11 */ "", 13067 /* CMIC_PKT_REASON_MINI_1_TYPE12 */ "", 13068 /* CMIC_PKT_REASON_MINI_1_TYPE13 */ "", 13069 /* CMIC_PKT_REASON_MINI_1_TYPE14 */ "", 13070 /* CMIC_PKT_REASON_MINI_1_TYPE15 */ "", 13071 /* CMIC_PKT_REASON_MINI_2_TYPE */ "", 13072 /* CMIC_PKT_REASON_MINI_2_TYPE0 */ "", 13073 /* CMIC_PKT_REASON_MINI_2_TYPE1 */ "", 13074 /* CMIC_PKT_REASON_MINI_2_TYPE2 */ "", 13075 /* CMIC_PKT_REASON_MINI_2_TYPE3 */ "", 13076 /* CMIC_PKT_REASON_MINI_2_TYPE4 */ "", 13077 /* CMIC_PKT_REASON_MINI_2_TYPE5 */ "", 13078 /* CMIC_PKT_REASON_MINI_2_TYPE6 */ "", 13079 /* CMIC_PKT_REASON_MINI_2_TYPE7 */ "", 13080 /* CMIC_PKT_REASON_MINI_2_TYPE8 */ "", 13081 /* CMIC_PKT_REASON_MINI_2_TYPE9 */ "", 13082 /* CMIC_PKT_REASON_MINI_2_TYPE10 */ "", 13083 /* CMIC_PKT_REASON_MINI_2_TYPE11 */ "", 13084 /* CMIC_PKT_REASON_MINI_2_TYPE12 */ "", 13085 /* CMIC_PKT_REASON_MINI_2_TYPE13 */ "", 13086 /* CMIC_PKT_REASON_MINI_2_TYPE14 */ "", 13087 /* CMIC_PKT_REASON_MINI_2_TYPE15 */ "", 13088 /* CMIC_PKT_REASON_MINI_HI */ "", 13089 /* CMIC_PKT_RMAC */ "", 13090 /* CMIC_PKT_RMAC_HI */ "", 13091 /* CMIC_PKT_RMH0 */ "", 13092 /* CMIC_PKT_RMH1 */ "", 13093 /* CMIC_PKT_RMH2 */ "", 13094 /* CMIC_PKT_RMH3 */ "", 13095 /* CMIC_PKT_VLAN */ "", 13096 /* CMIC_QGPHY_QSGMII_CONTROL */ "", 13097 /* CMIC_RATE_ADJUST */ "CMIC_RATE_ADJUST_EXT_MDIO", 13098 /* CMIC_RATE_ADJUST_EXT_MDIO */ "", 13099 /* CMIC_RATE_ADJUST_I2C */ "", 13100 /* CMIC_RATE_ADJUST_INT_MDIO */ "", 13101 /* CMIC_RATE_ADJUST_STDMA */ "", 13102 /* CMIC_REG_00040004 */ "", 13103 /* CMIC_REG_00040040 */ "", 13104 /* CMIC_REG_0004003C */ "", 13105 /* CMIC_RPE0_MAX_CELL_LIMIT */ "", 13106 /* CMIC_RPE1_MAX_CELL_LIMIT */ "", 13107 /* CMIC_RPE_1BIT_ECC_ERROR_STATUS */ "", 13108 /* CMIC_RPE_1BIT_ECC_ERROR_STATUS_ENABLE */ "", 13109 /* CMIC_RPE_2BIT_ECC_ERROR_STATUS */ "", 13110 /* CMIC_RPE_2BIT_ECC_ERROR_STATUS_ENABLE */ "", 13111 /* CMIC_RPE_AXI_AR_COUNT_SPLIT_TX */ "", 13112 /* CMIC_RPE_AXI_AR_COUNT_TX */ "", 13113 /* CMIC_RPE_AXI_STAT */ "", 13114 /* CMIC_RPE_COMPLETION_BUF_ECC_CONTROL */ "", 13115 /* CMIC_RPE_COMPLETION_BUF_ECC_STATUS */ "", 13116 /* CMIC_RPE_COMPLETION_BUF_MAX_FLIST_ENTRIES */ "", 13117 /* CMIC_RPE_COMPLETION_BUF_STATUS_NUM_FREE_ENTRIES */ "", 13118 /* CMIC_RPE_COMPLETION_BUF_TM_CONTROL */ "", 13119 /* CMIC_RPE_DEBUG */ "", 13120 /* CMIC_RPE_DMA_MASTER_TOTAL_OUTSTD_TRANS_LIMIT */ "", 13121 /* CMIC_RPE_INTR_PKT_PACING_DELAY */ "", 13122 /* CMIC_RPE_IRQ_STAT */ "", 13123 /* CMIC_RPE_IRQ_STAT0 */ "", 13124 /* CMIC_RPE_IRQ_STAT1 */ "", 13125 /* CMIC_RPE_IRQ_STAT2 */ "", 13126 /* CMIC_RPE_IRQ_STAT3 */ "", 13127 /* CMIC_RPE_IRQ_STAT4 */ "", 13128 /* CMIC_RPE_IRQ_STAT5 */ "", 13129 /* CMIC_RPE_IRQ_STAT6 */ "", 13130 /* CMIC_RPE_IRQ_STAT_CLR */ "", 13131 /* CMIC_RPE_MAX_CELL_LIMIT */ "", 13132 /* CMIC_RPE_MIIM_ADDRESS */ "", 13133 /* CMIC_RPE_MIIM_CTRL */ "", 13134 /* CMIC_RPE_MIIM_PARAM */ "", 13135 /* CMIC_RPE_MIIM_READ_DATA */ "", 13136 /* CMIC_RPE_MIIM_STAT */ "", 13137 /* CMIC_RPE_PCIE_IRQ_MASK0 */ "", 13138 /* CMIC_RPE_PIO_MEMDMA_COS_0 */ "", 13139 /* CMIC_RPE_PIO_MEMDMA_COS_1 */ "", 13140 /* CMIC_RPE_PIO_MEMDMA_MEM_ECC_CONTROL */ "", 13141 /* CMIC_RPE_PIO_MEMDMA_MEM_ECC_STATUS */ "", 13142 /* CMIC_RPE_PIO_MEMDMA_MEM_TM_CONTROL */ "", 13143 /* CMIC_RPE_PIO_MEMDMA_RXBUF_THRESHOLD_CONFIG */ "", 13144 /* CMIC_RPE_PKTDMA_COS_0 */ "", 13145 /* CMIC_RPE_PKTDMA_COS_1 */ "", 13146 /* CMIC_RPE_PKTDMA_RXBUF_THRESHOLD_CONFIG */ "", 13147 /* CMIC_RPE_PKT_COS_QUEUES_HI */ "", 13148 /* CMIC_RPE_PKT_COS_QUEUES_LO */ "", 13149 /* CMIC_RPE_PKT_COUNT_FROMCPU */ "", 13150 /* CMIC_RPE_PKT_COUNT_FROMCPU_MH */ "", 13151 /* CMIC_RPE_PKT_COUNT_INTR */ "", 13152 /* CMIC_RPE_PKT_COUNT_MEMDMA */ "", 13153 /* CMIC_RPE_PKT_COUNT_MEMDMA_REPLY */ "", 13154 /* CMIC_RPE_PKT_COUNT_PIO */ "", 13155 /* CMIC_RPE_PKT_COUNT_PIO_MEMDMA_DROP */ "", 13156 /* CMIC_RPE_PKT_COUNT_PIO_REPLY */ "", 13157 /* CMIC_RPE_PKT_COUNT_RXPKT */ "", 13158 /* CMIC_RPE_PKT_COUNT_RXPKT_ERR */ "", 13159 /* CMIC_RPE_PKT_COUNT_SBUSDMA */ "", 13160 /* CMIC_RPE_PKT_COUNT_SBUSDMA_REPLY */ "", 13161 /* CMIC_RPE_PKT_COUNT_SCHAN */ "", 13162 /* CMIC_RPE_PKT_COUNT_SCHAN_REP */ "", 13163 /* CMIC_RPE_PKT_COUNT_SCHAN_SBUSDMA_DROP */ "", 13164 /* CMIC_RPE_PKT_COUNT_TOCPUD */ "", 13165 /* CMIC_RPE_PKT_COUNT_TOCPUDM */ "", 13166 /* CMIC_RPE_PKT_COUNT_TOCPUE */ "", 13167 /* CMIC_RPE_PKT_COUNT_TOCPUEM */ "", 13168 /* CMIC_RPE_PKT_COUNT_TXPKT */ "", 13169 /* CMIC_RPE_PKT_COUNT_TXPKT_ERR */ "", 13170 /* CMIC_RPE_PKT_CTRL */ "", 13171 /* CMIC_RPE_PKT_ETHER_SIG */ "", 13172 /* CMIC_RPE_PKT_LMAC0_HI */ "", 13173 /* CMIC_RPE_PKT_LMAC0_LO */ "", 13174 /* CMIC_RPE_PKT_LMAC1_HI */ "", 13175 /* CMIC_RPE_PKT_LMAC1_LO */ "", 13176 /* CMIC_RPE_PKT_PORTS_0 */ "", 13177 /* CMIC_RPE_PKT_PORTS_1 */ "", 13178 /* CMIC_RPE_PKT_PORTS_2 */ "", 13179 /* CMIC_RPE_PKT_PORTS_3 */ "", 13180 /* CMIC_RPE_PKT_PORTS_4 */ "", 13181 /* CMIC_RPE_PKT_PORTS_5 */ "", 13182 /* CMIC_RPE_PKT_PORTS_6 */ "", 13183 /* CMIC_RPE_PKT_PORTS_7 */ "", 13184 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_0 */ "", 13185 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_1 */ "", 13186 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_2 */ "", 13187 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_3 */ "", 13188 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_4 */ "", 13189 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_5 */ "", 13190 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_6 */ "", 13191 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_7 */ "", 13192 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_8 */ "", 13193 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_9 */ "", 13194 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_10 */ "", 13195 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_11 */ "", 13196 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_12 */ "", 13197 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_13 */ "", 13198 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_14 */ "", 13199 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_15 */ "", 13200 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_16 */ "", 13201 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_17 */ "", 13202 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_18 */ "", 13203 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_19 */ "", 13204 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_20 */ "", 13205 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_21 */ "", 13206 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_22 */ "", 13207 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_23 */ "", 13208 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_24 */ "", 13209 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_25 */ "", 13210 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_26 */ "", 13211 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_27 */ "", 13212 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_28 */ "", 13213 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_29 */ "", 13214 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_30 */ "", 13215 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_31 */ "", 13216 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_32 */ "", 13217 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_33 */ "", 13218 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_34 */ "", 13219 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_35 */ "", 13220 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_36 */ "", 13221 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_37 */ "", 13222 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_38 */ "", 13223 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_39 */ "", 13224 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_40 */ "", 13225 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_41 */ "", 13226 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_42 */ "", 13227 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_43 */ "", 13228 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_44 */ "", 13229 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_45 */ "", 13230 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_46 */ "", 13231 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_47 */ "", 13232 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_48 */ "", 13233 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_49 */ "", 13234 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_50 */ "", 13235 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_51 */ "", 13236 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_52 */ "", 13237 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_53 */ "", 13238 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_54 */ "", 13239 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_55 */ "", 13240 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_56 */ "", 13241 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_57 */ "", 13242 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_58 */ "", 13243 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_59 */ "", 13244 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_60 */ "", 13245 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_61 */ "", 13246 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_62 */ "", 13247 /* CMIC_RPE_PKT_PRI_MAP_TABLE_ENTRY_63 */ "", 13248 /* CMIC_RPE_PKT_REASON_0_TYPE */ "", 13249 /* CMIC_RPE_PKT_REASON_0_TYPE0 */ "", 13250 /* CMIC_RPE_PKT_REASON_0_TYPE1 */ "", 13251 /* CMIC_RPE_PKT_REASON_0_TYPE2 */ "", 13252 /* CMIC_RPE_PKT_REASON_0_TYPE3 */ "", 13253 /* CMIC_RPE_PKT_REASON_0_TYPE4 */ "", 13254 /* CMIC_RPE_PKT_REASON_0_TYPE5 */ "", 13255 /* CMIC_RPE_PKT_REASON_0_TYPE6 */ "", 13256 /* CMIC_RPE_PKT_REASON_0_TYPE7 */ "", 13257 /* CMIC_RPE_PKT_REASON_0_TYPE8 */ "", 13258 /* CMIC_RPE_PKT_REASON_0_TYPE9 */ "", 13259 /* CMIC_RPE_PKT_REASON_0_TYPE10 */ "", 13260 /* CMIC_RPE_PKT_REASON_0_TYPE11 */ "", 13261 /* CMIC_RPE_PKT_REASON_0_TYPE12 */ "", 13262 /* CMIC_RPE_PKT_REASON_0_TYPE13 */ "", 13263 /* CMIC_RPE_PKT_REASON_0_TYPE14 */ "", 13264 /* CMIC_RPE_PKT_REASON_0_TYPE15 */ "", 13265 /* CMIC_RPE_PKT_REASON_1_TYPE */ "", 13266 /* CMIC_RPE_PKT_REASON_1_TYPE0 */ "", 13267 /* CMIC_RPE_PKT_REASON_1_TYPE1 */ "", 13268 /* CMIC_RPE_PKT_REASON_1_TYPE2 */ "", 13269 /* CMIC_RPE_PKT_REASON_1_TYPE3 */ "", 13270 /* CMIC_RPE_PKT_REASON_1_TYPE4 */ "", 13271 /* CMIC_RPE_PKT_REASON_1_TYPE5 */ "", 13272 /* CMIC_RPE_PKT_REASON_1_TYPE6 */ "", 13273 /* CMIC_RPE_PKT_REASON_1_TYPE7 */ "", 13274 /* CMIC_RPE_PKT_REASON_1_TYPE8 */ "", 13275 /* CMIC_RPE_PKT_REASON_1_TYPE9 */ "", 13276 /* CMIC_RPE_PKT_REASON_1_TYPE10 */ "", 13277 /* CMIC_RPE_PKT_REASON_1_TYPE11 */ "", 13278 /* CMIC_RPE_PKT_REASON_1_TYPE12 */ "", 13279 /* CMIC_RPE_PKT_REASON_1_TYPE13 */ "", 13280 /* CMIC_RPE_PKT_REASON_1_TYPE14 */ "", 13281 /* CMIC_RPE_PKT_REASON_1_TYPE15 */ "", 13282 /* CMIC_RPE_PKT_REASON_2_TYPE */ "", 13283 /* CMIC_RPE_PKT_REASON_2_TYPE0 */ "", 13284 /* CMIC_RPE_PKT_REASON_2_TYPE1 */ "", 13285 /* CMIC_RPE_PKT_REASON_2_TYPE2 */ "", 13286 /* CMIC_RPE_PKT_REASON_2_TYPE3 */ "", 13287 /* CMIC_RPE_PKT_REASON_2_TYPE4 */ "", 13288 /* CMIC_RPE_PKT_REASON_2_TYPE5 */ "", 13289 /* CMIC_RPE_PKT_REASON_2_TYPE6 */ "", 13290 /* CMIC_RPE_PKT_REASON_2_TYPE7 */ "", 13291 /* CMIC_RPE_PKT_REASON_2_TYPE8 */ "", 13292 /* CMIC_RPE_PKT_REASON_2_TYPE9 */ "", 13293 /* CMIC_RPE_PKT_REASON_2_TYPE10 */ "", 13294 /* CMIC_RPE_PKT_REASON_2_TYPE11 */ "", 13295 /* CMIC_RPE_PKT_REASON_2_TYPE12 */ "", 13296 /* CMIC_RPE_PKT_REASON_2_TYPE13 */ "", 13297 /* CMIC_RPE_PKT_REASON_2_TYPE14 */ "", 13298 /* CMIC_RPE_PKT_REASON_2_TYPE15 */ "", 13299 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE */ "", 13300 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE0 */ "", 13301 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE1 */ "", 13302 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE2 */ "", 13303 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE3 */ "", 13304 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE4 */ "", 13305 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE5 */ "", 13306 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE6 */ "", 13307 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE7 */ "", 13308 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE8 */ "", 13309 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE9 */ "", 13310 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE10 */ "", 13311 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE11 */ "", 13312 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE12 */ "", 13313 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE13 */ "", 13314 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE14 */ "", 13315 /* CMIC_RPE_PKT_REASON_DIRECT_0_TYPE15 */ "", 13316 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE */ "", 13317 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE0 */ "", 13318 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE1 */ "", 13319 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE2 */ "", 13320 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE3 */ "", 13321 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE4 */ "", 13322 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE5 */ "", 13323 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE6 */ "", 13324 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE7 */ "", 13325 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE8 */ "", 13326 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE9 */ "", 13327 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE10 */ "", 13328 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE11 */ "", 13329 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE12 */ "", 13330 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE13 */ "", 13331 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE14 */ "", 13332 /* CMIC_RPE_PKT_REASON_DIRECT_1_TYPE15 */ "", 13333 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE */ "", 13334 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE0 */ "", 13335 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE1 */ "", 13336 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE2 */ "", 13337 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE3 */ "", 13338 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE4 */ "", 13339 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE5 */ "", 13340 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE6 */ "", 13341 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE7 */ "", 13342 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE8 */ "", 13343 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE9 */ "", 13344 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE10 */ "", 13345 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE11 */ "", 13346 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE12 */ "", 13347 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE13 */ "", 13348 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE14 */ "", 13349 /* CMIC_RPE_PKT_REASON_DIRECT_2_TYPE15 */ "", 13350 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE */ "", 13351 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE0 */ "", 13352 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE1 */ "", 13353 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE2 */ "", 13354 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE3 */ "", 13355 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE4 */ "", 13356 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE5 */ "", 13357 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE6 */ "", 13358 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE7 */ "", 13359 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE8 */ "", 13360 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE9 */ "", 13361 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE10 */ "", 13362 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE11 */ "", 13363 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE12 */ "", 13364 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE13 */ "", 13365 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE14 */ "", 13366 /* CMIC_RPE_PKT_REASON_MINI_0_TYPE15 */ "", 13367 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE */ "", 13368 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE0 */ "", 13369 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE1 */ "", 13370 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE2 */ "", 13371 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE3 */ "", 13372 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE4 */ "", 13373 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE5 */ "", 13374 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE6 */ "", 13375 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE7 */ "", 13376 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE8 */ "", 13377 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE9 */ "", 13378 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE10 */ "", 13379 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE11 */ "", 13380 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE12 */ "", 13381 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE13 */ "", 13382 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE14 */ "", 13383 /* CMIC_RPE_PKT_REASON_MINI_1_TYPE15 */ "", 13384 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE */ "", 13385 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE0 */ "", 13386 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE1 */ "", 13387 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE2 */ "", 13388 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE3 */ "", 13389 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE4 */ "", 13390 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE5 */ "", 13391 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE6 */ "", 13392 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE7 */ "", 13393 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE8 */ "", 13394 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE9 */ "", 13395 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE10 */ "", 13396 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE11 */ "", 13397 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE12 */ "", 13398 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE13 */ "", 13399 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE14 */ "", 13400 /* CMIC_RPE_PKT_REASON_MINI_2_TYPE15 */ "", 13401 /* CMIC_RPE_PKT_RMAC */ "", 13402 /* CMIC_RPE_PKT_RMAC_HI */ "", 13403 /* CMIC_RPE_PKT_RMH0 */ "", 13404 /* CMIC_RPE_PKT_RMH1 */ "", 13405 /* CMIC_RPE_PKT_RMH2 */ "", 13406 /* CMIC_RPE_PKT_RMH3 */ "", 13407 /* CMIC_RPE_PKT_VLAN */ "", 13408 /* CMIC_RPE_RCPU_IRQ_MASK0 */ "", 13409 /* CMIC_RPE_RCPU_IRQ_MASK1 */ "", 13410 /* CMIC_RPE_RCPU_IRQ_MASK2 */ "", 13411 /* CMIC_RPE_RCPU_IRQ_MASK3 */ "", 13412 /* CMIC_RPE_RCPU_IRQ_MASK4 */ "", 13413 /* CMIC_RPE_RCPU_IRQ_MASK5 */ "", 13414 /* CMIC_RPE_RCPU_IRQ_MASK6 */ "", 13415 /* CMIC_RPE_SCHAN_SBUSDMA_COS_0 */ "", 13416 /* CMIC_RPE_SCHAN_SBUSDMA_COS_1 */ "", 13417 /* CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_CONTROL */ "", 13418 /* CMIC_RPE_SCHAN_SBUSDMA_MEM_ECC_STATUS */ "", 13419 /* CMIC_RPE_SCHAN_SBUSDMA_MEM_TM_CONTROL */ "", 13420 /* CMIC_RPE_SCHAN_SBUSDMA_RXBUF_THRESHOLD_CONFIG */ "", 13421 /* CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK0 */ "", 13422 /* CMIC_RPE_SHARED_PROGRAMMABLE_COS_MASK1 */ "", 13423 /* CMIC_RPE_SHARED_RXBUF_BLOCK_DATABUF_ALLOC */ "", 13424 /* CMIC_RPE_SHARED_RXBUF_CONFIG */ "", 13425 /* CMIC_RPE_SHARED_RXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 13426 /* CMIC_RPE_SHARED_RXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 13427 /* CMIC_RPE_SHARED_RXBUF_ECC_CONTROL */ "", 13428 /* CMIC_RPE_SHARED_RXBUF_ECC_STATUS */ "", 13429 /* CMIC_RPE_SHARED_RXBUF_ECC_STATUS_CLR */ "", 13430 /* CMIC_RPE_SHARED_RXBUF_THRESHOLD_CONFIG */ "", 13431 /* CMIC_RPE_SHARED_RXBUF_TM_CONTROL */ "", 13432 /* CMIC_RPE_SHARED_TXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 13433 /* CMIC_RPE_SHARED_TXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 13434 /* CMIC_RPE_SHARED_TXBUF_DEBUG */ "", 13435 /* CMIC_RPE_SHARED_TXBUF_ECC_CONTROL */ "", 13436 /* CMIC_RPE_SHARED_TXBUF_ECC_STATUS */ "", 13437 /* CMIC_RPE_SHARED_TXBUF_ECC_STATUS_CLR */ "", 13438 /* CMIC_RPE_SHARED_TXBUF_MAX_BUF_LIMITS */ "", 13439 /* CMIC_RPE_SHARED_TXBUF_MIN_BUF_LIMITS */ "", 13440 /* CMIC_RPE_SHARED_TXBUF_RD_THRESHOLD_CONFIG */ "", 13441 /* CMIC_RPE_SHARED_TXBUF_RD_WRR_ARB_CTRL */ "", 13442 /* CMIC_RPE_SHARED_TXBUF_SLICE0_PKT_CNT */ "", 13443 /* CMIC_RPE_SHARED_TXBUF_SLICE1_PKT_CNT */ "", 13444 /* CMIC_RPE_SHARED_TXBUF_SLICE2_PKT_CNT */ "", 13445 /* CMIC_RPE_SHARED_TXBUF_SLICE3_PKT_CNT */ "", 13446 /* CMIC_RPE_SHARED_TXBUF_TM_CONTROL */ "", 13447 /* CMIC_RPE_STAT */ "", 13448 /* CMIC_RPE_STAT_CLR */ "", 13449 /* CMIC_RPE_SW_INTR_CONFIG */ "", 13450 /* CMIC_RPE_UC0_IRQ_MASK0 */ "", 13451 /* CMIC_RPE_UC1_IRQ_MASK0 */ "", 13452 /* CMIC_RXBUF_BLOCK_DATABUF_ALLOC */ "", 13453 /* CMIC_RXBUF_BLOCK_STATUSBUF_ALLOC */ "", 13454 /* CMIC_RXBUF_CONFIG */ "", 13455 /* CMIC_RXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 13456 /* CMIC_RXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 13457 /* CMIC_RXBUF_DATABUF_TM_0 */ "", 13458 /* CMIC_RXBUF_DATABUF_TM_1 */ "", 13459 /* CMIC_RXBUF_DATABUF_TM_2 */ "", 13460 /* CMIC_RXBUF_ECCERR_CONTROL */ "", 13461 /* CMIC_RXBUF_EPINTF_BUF_DEPTH */ "", 13462 /* CMIC_RXBUF_EPINTF_MAX_INTERFACE_CREDITS */ "", 13463 /* CMIC_RXBUF_EPINTF_RELEASE_ALL_CREDITS */ "", 13464 /* CMIC_RXBUF_MEM_CONTROL_0 */ "", 13465 /* CMIC_RXBUF_STATBUF_TM_0 */ "", 13466 /* CMIC_RXBUF_STATBUF_TM_1 */ "", 13467 /* CMIC_RXBUF_STATUSBUF_MAX_FLIST_ENTRIES */ "", 13468 /* CMIC_RXBUF_STATUSBUF_NUM_FREE_ENTRIES */ "", 13469 /* CMIC_RX_PAUSE_CAPABILITY */ "", 13470 /* CMIC_RX_PAUSE_OVERRIDE_CONTROL */ "", 13471 /* CMIC_RX_PAUSE_STAT */ "", 13472 /* CMIC_SBUS_RING_MAP */ "", 13473 /* CMIC_SBUS_RING_MAP_0 */ "", 13474 /* CMIC_SBUS_RING_MAP_1 */ "", 13475 /* CMIC_SBUS_RING_MAP_2 */ "", 13476 /* CMIC_SBUS_RING_MAP_3 */ "", 13477 /* CMIC_SBUS_RING_MAP_4 */ "", 13478 /* CMIC_SBUS_RING_MAP_5 */ "", 13479 /* CMIC_SBUS_RING_MAP_6 */ "", 13480 /* CMIC_SBUS_RING_MAP_7 */ "", 13481 /* CMIC_SBUS_RING_MAP_0_7 */ "", 13482 /* CMIC_SBUS_RING_MAP_104_111 */ "", 13483 /* CMIC_SBUS_RING_MAP_112_119 */ "", 13484 /* CMIC_SBUS_RING_MAP_120_127 */ "", 13485 /* CMIC_SBUS_RING_MAP_16_23 */ "", 13486 /* CMIC_SBUS_RING_MAP_24_31 */ "", 13487 /* CMIC_SBUS_RING_MAP_32_39 */ "", 13488 /* CMIC_SBUS_RING_MAP_40_47 */ "", 13489 /* CMIC_SBUS_RING_MAP_48_55 */ "", 13490 /* CMIC_SBUS_RING_MAP_56_63 */ "", 13491 /* CMIC_SBUS_RING_MAP_64_71 */ "", 13492 /* CMIC_SBUS_RING_MAP_72_79 */ "", 13493 /* CMIC_SBUS_RING_MAP_80_87 */ "", 13494 /* CMIC_SBUS_RING_MAP_88_95 */ "", 13495 /* CMIC_SBUS_RING_MAP_8_15 */ "", 13496 /* CMIC_SBUS_RING_MAP_96_103 */ "", 13497 /* CMIC_SBUS_TIMEOUT */ "", 13498 /* CMIC_SCAN_PORTS */ "", 13499 /* CMIC_SCAN_PORTS_HI */ "", 13500 /* CMIC_SCAN_PORTS_HI_2 */ "", 13501 /* CMIC_SCAN_PORTS_HI_3 */ "", 13502 /* CMIC_SCHAN_CTRL */ "", 13503 /* CMIC_SCHAN_ERR */ "", 13504 /* CMIC_SCHAN_MESSAGE */ "", 13505 /* CMIC_SCHAN_MESSAGE_EXT */ "", 13506 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE */ "", 13507 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE0 */ "", 13508 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE1 */ "", 13509 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE2 */ "", 13510 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE3 */ "", 13511 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE4 */ "", 13512 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE5 */ "", 13513 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE6 */ "", 13514 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE7 */ "", 13515 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE8 */ "", 13516 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE9 */ "", 13517 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE10 */ "", 13518 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE11 */ "", 13519 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE12 */ "", 13520 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE13 */ "", 13521 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE14 */ "", 13522 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE15 */ "", 13523 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE16 */ "", 13524 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE17 */ "", 13525 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE18 */ "", 13526 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE19 */ "", 13527 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE20 */ "", 13528 /* CMIC_SCHAN_RCPU_RPIO_MESSAGE21 */ "", 13529 /* CMIC_SEMAPHORE_1 */ "", 13530 /* CMIC_SEMAPHORE_2 */ "", 13531 /* CMIC_SEMAPHORE_3 */ "", 13532 /* CMIC_SEMAPHORE_4 */ "", 13533 /* CMIC_SEMAPHORE_5 */ "", 13534 /* CMIC_SEMAPHORE_6 */ "", 13535 /* CMIC_SEMAPHORE_7 */ "", 13536 /* CMIC_SEMAPHORE_8 */ "", 13537 /* CMIC_SEMAPHORE_9 */ "", 13538 /* CMIC_SEMAPHORE_10 */ "", 13539 /* CMIC_SEMAPHORE_11 */ "", 13540 /* CMIC_SEMAPHORE_12 */ "", 13541 /* CMIC_SEMAPHORE_13 */ "", 13542 /* CMIC_SEMAPHORE_14 */ "", 13543 /* CMIC_SEMAPHORE_15 */ "", 13544 /* CMIC_SEMAPHORE_16 */ "", 13545 /* CMIC_SEMAPHORE_17 */ "", 13546 /* CMIC_SEMAPHORE_18 */ "", 13547 /* CMIC_SEMAPHORE_19 */ "", 13548 /* CMIC_SEMAPHORE_20 */ "", 13549 /* CMIC_SEMAPHORE_21 */ "", 13550 /* CMIC_SEMAPHORE_22 */ "", 13551 /* CMIC_SEMAPHORE_23 */ "", 13552 /* CMIC_SEMAPHORE_24 */ "", 13553 /* CMIC_SEMAPHORE_25 */ "", 13554 /* CMIC_SEMAPHORE_26 */ "", 13555 /* CMIC_SEMAPHORE_27 */ "", 13556 /* CMIC_SEMAPHORE_28 */ "", 13557 /* CMIC_SEMAPHORE_29 */ "", 13558 /* CMIC_SEMAPHORE_30 */ "", 13559 /* CMIC_SEMAPHORE_31 */ "", 13560 /* CMIC_SEMAPHORE_32 */ "", 13561 /* CMIC_SEMAPHORE_10_SHADOW */ "", 13562 /* CMIC_SEMAPHORE_11_SHADOW */ "", 13563 /* CMIC_SEMAPHORE_12_SHADOW */ "", 13564 /* CMIC_SEMAPHORE_13_SHADOW */ "", 13565 /* CMIC_SEMAPHORE_14_SHADOW */ "", 13566 /* CMIC_SEMAPHORE_15_SHADOW */ "", 13567 /* CMIC_SEMAPHORE_16_SHADOW */ "", 13568 /* CMIC_SEMAPHORE_17_SHADOW */ "", 13569 /* CMIC_SEMAPHORE_18_SHADOW */ "", 13570 /* CMIC_SEMAPHORE_19_SHADOW */ "", 13571 /* CMIC_SEMAPHORE_1_SHADOW */ "", 13572 /* CMIC_SEMAPHORE_20_SHADOW */ "", 13573 /* CMIC_SEMAPHORE_21_SHADOW */ "", 13574 /* CMIC_SEMAPHORE_22_SHADOW */ "", 13575 /* CMIC_SEMAPHORE_23_SHADOW */ "", 13576 /* CMIC_SEMAPHORE_24_SHADOW */ "", 13577 /* CMIC_SEMAPHORE_25_SHADOW */ "", 13578 /* CMIC_SEMAPHORE_26_SHADOW */ "", 13579 /* CMIC_SEMAPHORE_27_SHADOW */ "", 13580 /* CMIC_SEMAPHORE_28_SHADOW */ "", 13581 /* CMIC_SEMAPHORE_29_SHADOW */ "", 13582 /* CMIC_SEMAPHORE_2_SHADOW */ "", 13583 /* CMIC_SEMAPHORE_30_SHADOW */ "", 13584 /* CMIC_SEMAPHORE_31_SHADOW */ "", 13585 /* CMIC_SEMAPHORE_32_SHADOW */ "", 13586 /* CMIC_SEMAPHORE_3_SHADOW */ "", 13587 /* CMIC_SEMAPHORE_4_SHADOW */ "", 13588 /* CMIC_SEMAPHORE_5_SHADOW */ "", 13589 /* CMIC_SEMAPHORE_6_SHADOW */ "", 13590 /* CMIC_SEMAPHORE_7_SHADOW */ "", 13591 /* CMIC_SEMAPHORE_8_SHADOW */ "", 13592 /* CMIC_SEMAPHORE_9_SHADOW */ "", 13593 /* CMIC_SER0_END_ADDR_0 */ "", 13594 /* CMIC_SER0_END_ADDR_1 */ "", 13595 /* CMIC_SER0_END_ADDR_2 */ "", 13596 /* CMIC_SER0_END_ADDR_3 */ "", 13597 /* CMIC_SER0_END_ADDR_4 */ "", 13598 /* CMIC_SER0_END_ADDR_5 */ "", 13599 /* CMIC_SER0_END_ADDR_6 */ "", 13600 /* CMIC_SER0_END_ADDR_7 */ "", 13601 /* CMIC_SER0_END_ADDR_8 */ "", 13602 /* CMIC_SER0_END_ADDR_9 */ "", 13603 /* CMIC_SER0_END_ADDR_10 */ "", 13604 /* CMIC_SER0_END_ADDR_11 */ "", 13605 /* CMIC_SER0_END_ADDR_12 */ "", 13606 /* CMIC_SER0_END_ADDR_13 */ "", 13607 /* CMIC_SER0_END_ADDR_14 */ "", 13608 /* CMIC_SER0_END_ADDR_15 */ "", 13609 /* CMIC_SER0_END_ADDR_16 */ "", 13610 /* CMIC_SER0_END_ADDR_17 */ "", 13611 /* CMIC_SER0_END_ADDR_18 */ "", 13612 /* CMIC_SER0_END_ADDR_19 */ "", 13613 /* CMIC_SER0_END_ADDR_20 */ "", 13614 /* CMIC_SER0_END_ADDR_21 */ "", 13615 /* CMIC_SER0_END_ADDR_22 */ "", 13616 /* CMIC_SER0_END_ADDR_23 */ "", 13617 /* CMIC_SER0_END_ADDR_24 */ "", 13618 /* CMIC_SER0_END_ADDR_25 */ "", 13619 /* CMIC_SER0_END_ADDR_26 */ "", 13620 /* CMIC_SER0_END_ADDR_27 */ "", 13621 /* CMIC_SER0_END_ADDR_28 */ "", 13622 /* CMIC_SER0_END_ADDR_29 */ "", 13623 /* CMIC_SER0_END_ADDR_30 */ "", 13624 /* CMIC_SER0_END_ADDR_31 */ "", 13625 /* CMIC_SER0_FAIL_CNT */ "", 13626 /* CMIC_SER0_FAIL_ENTRY */ "", 13627 /* CMIC_SER0_INTERLEAVE_PARITY */ "", 13628 /* CMIC_SER0_MEM_ADDR */ "", 13629 /* CMIC_SER0_MEM_ADDR_0 */ "", 13630 /* CMIC_SER0_MEM_ADDR_1 */ "", 13631 /* CMIC_SER0_MEM_ADDR_2 */ "", 13632 /* CMIC_SER0_MEM_ADDR_3 */ "", 13633 /* CMIC_SER0_MEM_ADDR_4 */ "", 13634 /* CMIC_SER0_MEM_ADDR_5 */ "", 13635 /* CMIC_SER0_MEM_ADDR_6 */ "", 13636 /* CMIC_SER0_MEM_ADDR_7 */ "", 13637 /* CMIC_SER0_MEM_ADDR_8 */ "", 13638 /* CMIC_SER0_MEM_ADDR_9 */ "", 13639 /* CMIC_SER0_MEM_ADDR_10 */ "", 13640 /* CMIC_SER0_MEM_ADDR_11 */ "", 13641 /* CMIC_SER0_MEM_ADDR_12 */ "", 13642 /* CMIC_SER0_MEM_ADDR_13 */ "", 13643 /* CMIC_SER0_MEM_ADDR_14 */ "", 13644 /* CMIC_SER0_MEM_ADDR_15 */ "", 13645 /* CMIC_SER0_MEM_ADDR_16 */ "", 13646 /* CMIC_SER0_MEM_ADDR_17 */ "", 13647 /* CMIC_SER0_MEM_ADDR_18 */ "", 13648 /* CMIC_SER0_MEM_ADDR_19 */ "", 13649 /* CMIC_SER0_MEM_ADDR_20 */ "", 13650 /* CMIC_SER0_MEM_ADDR_21 */ "", 13651 /* CMIC_SER0_MEM_ADDR_22 */ "", 13652 /* CMIC_SER0_MEM_ADDR_23 */ "", 13653 /* CMIC_SER0_MEM_ADDR_24 */ "", 13654 /* CMIC_SER0_MEM_ADDR_25 */ "", 13655 /* CMIC_SER0_MEM_ADDR_26 */ "", 13656 /* CMIC_SER0_MEM_ADDR_27 */ "", 13657 /* CMIC_SER0_MEM_ADDR_28 */ "", 13658 /* CMIC_SER0_MEM_ADDR_29 */ "", 13659 /* CMIC_SER0_MEM_ADDR_30 */ "", 13660 /* CMIC_SER0_MEM_ADDR_31 */ "", 13661 /* CMIC_SER0_MEM_DATA */ "", 13662 /* CMIC_SER0_PARITY_MODE_SEL_15_0 */ "", 13663 /* CMIC_SER0_PARITY_MODE_SEL_31_16 */ "", 13664 /* CMIC_SER0_POWER_DOWN_MEM_LOWER */ "", 13665 /* CMIC_SER0_POWER_DOWN_MEM_UPPER */ "", 13666 /* CMIC_SER0_PROTECT_ADDR_RANGE_VALID */ "", 13667 /* CMIC_SER0_RANGE0_DATAENTRY_LEN */ "", 13668 /* CMIC_SER0_RANGE10_DATAENTRY_LEN */ "", 13669 /* CMIC_SER0_RANGE11_DATAENTRY_LEN */ "", 13670 /* CMIC_SER0_RANGE12_DATAENTRY_LEN */ "", 13671 /* CMIC_SER0_RANGE13_DATAENTRY_LEN */ "", 13672 /* CMIC_SER0_RANGE14_DATAENTRY_LEN */ "", 13673 /* CMIC_SER0_RANGE15_DATAENTRY_LEN */ "", 13674 /* CMIC_SER0_RANGE16_DATAENTRY_LEN */ "", 13675 /* CMIC_SER0_RANGE17_DATAENTRY_LEN */ "", 13676 /* CMIC_SER0_RANGE18_DATAENTRY_LEN */ "", 13677 /* CMIC_SER0_RANGE19_DATAENTRY_LEN */ "", 13678 /* CMIC_SER0_RANGE1_DATAENTRY_LEN */ "", 13679 /* CMIC_SER0_RANGE20_DATAENTRY_LEN */ "", 13680 /* CMIC_SER0_RANGE21_DATAENTRY_LEN */ "", 13681 /* CMIC_SER0_RANGE22_DATAENTRY_LEN */ "", 13682 /* CMIC_SER0_RANGE23_DATAENTRY_LEN */ "", 13683 /* CMIC_SER0_RANGE24_DATAENTRY_LEN */ "", 13684 /* CMIC_SER0_RANGE25_DATAENTRY_LEN */ "", 13685 /* CMIC_SER0_RANGE26_DATAENTRY_LEN */ "", 13686 /* CMIC_SER0_RANGE27_DATAENTRY_LEN */ "", 13687 /* CMIC_SER0_RANGE28_DATAENTRY_LEN */ "", 13688 /* CMIC_SER0_RANGE29_DATAENTRY_LEN */ "", 13689 /* CMIC_SER0_RANGE2_DATAENTRY_LEN */ "", 13690 /* CMIC_SER0_RANGE30_DATAENTRY_LEN */ "", 13691 /* CMIC_SER0_RANGE31_DATAENTRY_LEN */ "", 13692 /* CMIC_SER0_RANGE3_DATAENTRY_LEN */ "", 13693 /* CMIC_SER0_RANGE4_DATAENTRY_LEN */ "", 13694 /* CMIC_SER0_RANGE5_DATAENTRY_LEN */ "", 13695 /* CMIC_SER0_RANGE6_DATAENTRY_LEN */ "", 13696 /* CMIC_SER0_RANGE7_DATAENTRY_LEN */ "", 13697 /* CMIC_SER0_RANGE8_DATAENTRY_LEN */ "", 13698 /* CMIC_SER0_RANGE9_DATAENTRY_LEN */ "", 13699 /* CMIC_SER0_START_ADDR_0 */ "", 13700 /* CMIC_SER0_START_ADDR_1 */ "", 13701 /* CMIC_SER0_START_ADDR_2 */ "", 13702 /* CMIC_SER0_START_ADDR_3 */ "", 13703 /* CMIC_SER0_START_ADDR_4 */ "", 13704 /* CMIC_SER0_START_ADDR_5 */ "", 13705 /* CMIC_SER0_START_ADDR_6 */ "", 13706 /* CMIC_SER0_START_ADDR_7 */ "", 13707 /* CMIC_SER0_START_ADDR_8 */ "", 13708 /* CMIC_SER0_START_ADDR_9 */ "", 13709 /* CMIC_SER0_START_ADDR_10 */ "", 13710 /* CMIC_SER0_START_ADDR_11 */ "", 13711 /* CMIC_SER0_START_ADDR_12 */ "", 13712 /* CMIC_SER0_START_ADDR_13 */ "", 13713 /* CMIC_SER0_START_ADDR_14 */ "", 13714 /* CMIC_SER0_START_ADDR_15 */ "", 13715 /* CMIC_SER0_START_ADDR_16 */ "", 13716 /* CMIC_SER0_START_ADDR_17 */ "", 13717 /* CMIC_SER0_START_ADDR_18 */ "", 13718 /* CMIC_SER0_START_ADDR_19 */ "", 13719 /* CMIC_SER0_START_ADDR_20 */ "", 13720 /* CMIC_SER0_START_ADDR_21 */ "", 13721 /* CMIC_SER0_START_ADDR_22 */ "", 13722 /* CMIC_SER0_START_ADDR_23 */ "", 13723 /* CMIC_SER0_START_ADDR_24 */ "", 13724 /* CMIC_SER0_START_ADDR_25 */ "", 13725 /* CMIC_SER0_START_ADDR_26 */ "", 13726 /* CMIC_SER0_START_ADDR_27 */ "", 13727 /* CMIC_SER0_START_ADDR_28 */ "", 13728 /* CMIC_SER0_START_ADDR_29 */ "", 13729 /* CMIC_SER0_START_ADDR_30 */ "", 13730 /* CMIC_SER0_START_ADDR_31 */ "", 13731 /* CMIC_SER1_END_ADDR_0 */ "", 13732 /* CMIC_SER1_END_ADDR_1 */ "", 13733 /* CMIC_SER1_END_ADDR_2 */ "", 13734 /* CMIC_SER1_END_ADDR_3 */ "", 13735 /* CMIC_SER1_END_ADDR_4 */ "", 13736 /* CMIC_SER1_END_ADDR_5 */ "", 13737 /* CMIC_SER1_END_ADDR_6 */ "", 13738 /* CMIC_SER1_END_ADDR_7 */ "", 13739 /* CMIC_SER1_END_ADDR_8 */ "", 13740 /* CMIC_SER1_END_ADDR_9 */ "", 13741 /* CMIC_SER1_END_ADDR_10 */ "", 13742 /* CMIC_SER1_END_ADDR_11 */ "", 13743 /* CMIC_SER1_END_ADDR_12 */ "", 13744 /* CMIC_SER1_END_ADDR_13 */ "", 13745 /* CMIC_SER1_END_ADDR_14 */ "", 13746 /* CMIC_SER1_END_ADDR_15 */ "", 13747 /* CMIC_SER1_END_ADDR_16 */ "", 13748 /* CMIC_SER1_END_ADDR_17 */ "", 13749 /* CMIC_SER1_END_ADDR_18 */ "", 13750 /* CMIC_SER1_END_ADDR_19 */ "", 13751 /* CMIC_SER1_END_ADDR_20 */ "", 13752 /* CMIC_SER1_END_ADDR_21 */ "", 13753 /* CMIC_SER1_END_ADDR_22 */ "", 13754 /* CMIC_SER1_END_ADDR_23 */ "", 13755 /* CMIC_SER1_END_ADDR_24 */ "", 13756 /* CMIC_SER1_END_ADDR_25 */ "", 13757 /* CMIC_SER1_END_ADDR_26 */ "", 13758 /* CMIC_SER1_END_ADDR_27 */ "", 13759 /* CMIC_SER1_END_ADDR_28 */ "", 13760 /* CMIC_SER1_END_ADDR_29 */ "", 13761 /* CMIC_SER1_END_ADDR_30 */ "", 13762 /* CMIC_SER1_END_ADDR_31 */ "", 13763 /* CMIC_SER1_FAIL_CNT */ "", 13764 /* CMIC_SER1_FAIL_ENTRY */ "", 13765 /* CMIC_SER1_INTERLEAVE_PARITY */ "", 13766 /* CMIC_SER1_MEM_ADDR */ "", 13767 /* CMIC_SER1_MEM_ADDR_0 */ "", 13768 /* CMIC_SER1_MEM_ADDR_1 */ "", 13769 /* CMIC_SER1_MEM_ADDR_2 */ "", 13770 /* CMIC_SER1_MEM_ADDR_3 */ "", 13771 /* CMIC_SER1_MEM_ADDR_4 */ "", 13772 /* CMIC_SER1_MEM_ADDR_5 */ "", 13773 /* CMIC_SER1_MEM_ADDR_6 */ "", 13774 /* CMIC_SER1_MEM_ADDR_7 */ "", 13775 /* CMIC_SER1_MEM_ADDR_8 */ "", 13776 /* CMIC_SER1_MEM_ADDR_9 */ "", 13777 /* CMIC_SER1_MEM_ADDR_10 */ "", 13778 /* CMIC_SER1_MEM_ADDR_11 */ "", 13779 /* CMIC_SER1_MEM_ADDR_12 */ "", 13780 /* CMIC_SER1_MEM_ADDR_13 */ "", 13781 /* CMIC_SER1_MEM_ADDR_14 */ "", 13782 /* CMIC_SER1_MEM_ADDR_15 */ "", 13783 /* CMIC_SER1_MEM_ADDR_16 */ "", 13784 /* CMIC_SER1_MEM_ADDR_17 */ "", 13785 /* CMIC_SER1_MEM_ADDR_18 */ "", 13786 /* CMIC_SER1_MEM_ADDR_19 */ "", 13787 /* CMIC_SER1_MEM_ADDR_20 */ "", 13788 /* CMIC_SER1_MEM_ADDR_21 */ "", 13789 /* CMIC_SER1_MEM_ADDR_22 */ "", 13790 /* CMIC_SER1_MEM_ADDR_23 */ "", 13791 /* CMIC_SER1_MEM_ADDR_24 */ "", 13792 /* CMIC_SER1_MEM_ADDR_25 */ "", 13793 /* CMIC_SER1_MEM_ADDR_26 */ "", 13794 /* CMIC_SER1_MEM_ADDR_27 */ "", 13795 /* CMIC_SER1_MEM_ADDR_28 */ "", 13796 /* CMIC_SER1_MEM_ADDR_29 */ "", 13797 /* CMIC_SER1_MEM_ADDR_30 */ "", 13798 /* CMIC_SER1_MEM_ADDR_31 */ "", 13799 /* CMIC_SER1_MEM_DATA */ "", 13800 /* CMIC_SER1_PARITY_MODE_SEL_15_0 */ "", 13801 /* CMIC_SER1_PARITY_MODE_SEL_31_16 */ "", 13802 /* CMIC_SER1_POWER_DOWN_MEM_LOWER */ "", 13803 /* CMIC_SER1_POWER_DOWN_MEM_UPPER */ "", 13804 /* CMIC_SER1_PROTECT_ADDR_RANGE_VALID */ "", 13805 /* CMIC_SER1_RANGE0_DATAENTRY_LEN */ "", 13806 /* CMIC_SER1_RANGE10_DATAENTRY_LEN */ "", 13807 /* CMIC_SER1_RANGE11_DATAENTRY_LEN */ "", 13808 /* CMIC_SER1_RANGE12_DATAENTRY_LEN */ "", 13809 /* CMIC_SER1_RANGE13_DATAENTRY_LEN */ "", 13810 /* CMIC_SER1_RANGE14_DATAENTRY_LEN */ "", 13811 /* CMIC_SER1_RANGE15_DATAENTRY_LEN */ "", 13812 /* CMIC_SER1_RANGE16_DATAENTRY_LEN */ "", 13813 /* CMIC_SER1_RANGE17_DATAENTRY_LEN */ "", 13814 /* CMIC_SER1_RANGE18_DATAENTRY_LEN */ "", 13815 /* CMIC_SER1_RANGE19_DATAENTRY_LEN */ "", 13816 /* CMIC_SER1_RANGE1_DATAENTRY_LEN */ "", 13817 /* CMIC_SER1_RANGE20_DATAENTRY_LEN */ "", 13818 /* CMIC_SER1_RANGE21_DATAENTRY_LEN */ "", 13819 /* CMIC_SER1_RANGE22_DATAENTRY_LEN */ "", 13820 /* CMIC_SER1_RANGE23_DATAENTRY_LEN */ "", 13821 /* CMIC_SER1_RANGE24_DATAENTRY_LEN */ "", 13822 /* CMIC_SER1_RANGE25_DATAENTRY_LEN */ "", 13823 /* CMIC_SER1_RANGE26_DATAENTRY_LEN */ "", 13824 /* CMIC_SER1_RANGE27_DATAENTRY_LEN */ "", 13825 /* CMIC_SER1_RANGE28_DATAENTRY_LEN */ "", 13826 /* CMIC_SER1_RANGE29_DATAENTRY_LEN */ "", 13827 /* CMIC_SER1_RANGE2_DATAENTRY_LEN */ "", 13828 /* CMIC_SER1_RANGE30_DATAENTRY_LEN */ "", 13829 /* CMIC_SER1_RANGE31_DATAENTRY_LEN */ "", 13830 /* CMIC_SER1_RANGE3_DATAENTRY_LEN */ "", 13831 /* CMIC_SER1_RANGE4_DATAENTRY_LEN */ "", 13832 /* CMIC_SER1_RANGE5_DATAENTRY_LEN */ "", 13833 /* CMIC_SER1_RANGE6_DATAENTRY_LEN */ "", 13834 /* CMIC_SER1_RANGE7_DATAENTRY_LEN */ "", 13835 /* CMIC_SER1_RANGE8_DATAENTRY_LEN */ "", 13836 /* CMIC_SER1_RANGE9_DATAENTRY_LEN */ "", 13837 /* CMIC_SER1_START_ADDR_0 */ "", 13838 /* CMIC_SER1_START_ADDR_1 */ "", 13839 /* CMIC_SER1_START_ADDR_2 */ "", 13840 /* CMIC_SER1_START_ADDR_3 */ "", 13841 /* CMIC_SER1_START_ADDR_4 */ "", 13842 /* CMIC_SER1_START_ADDR_5 */ "", 13843 /* CMIC_SER1_START_ADDR_6 */ "", 13844 /* CMIC_SER1_START_ADDR_7 */ "", 13845 /* CMIC_SER1_START_ADDR_8 */ "", 13846 /* CMIC_SER1_START_ADDR_9 */ "", 13847 /* CMIC_SER1_START_ADDR_10 */ "", 13848 /* CMIC_SER1_START_ADDR_11 */ "", 13849 /* CMIC_SER1_START_ADDR_12 */ "", 13850 /* CMIC_SER1_START_ADDR_13 */ "", 13851 /* CMIC_SER1_START_ADDR_14 */ "", 13852 /* CMIC_SER1_START_ADDR_15 */ "", 13853 /* CMIC_SER1_START_ADDR_16 */ "", 13854 /* CMIC_SER1_START_ADDR_17 */ "", 13855 /* CMIC_SER1_START_ADDR_18 */ "", 13856 /* CMIC_SER1_START_ADDR_19 */ "", 13857 /* CMIC_SER1_START_ADDR_20 */ "", 13858 /* CMIC_SER1_START_ADDR_21 */ "", 13859 /* CMIC_SER1_START_ADDR_22 */ "", 13860 /* CMIC_SER1_START_ADDR_23 */ "", 13861 /* CMIC_SER1_START_ADDR_24 */ "", 13862 /* CMIC_SER1_START_ADDR_25 */ "", 13863 /* CMIC_SER1_START_ADDR_26 */ "", 13864 /* CMIC_SER1_START_ADDR_27 */ "", 13865 /* CMIC_SER1_START_ADDR_28 */ "", 13866 /* CMIC_SER1_START_ADDR_29 */ "", 13867 /* CMIC_SER1_START_ADDR_30 */ "", 13868 /* CMIC_SER1_START_ADDR_31 */ "", 13869 /* CMIC_SER_END_ADDR_0 */ "", 13870 /* CMIC_SER_END_ADDR_1 */ "", 13871 /* CMIC_SER_END_ADDR_2 */ "", 13872 /* CMIC_SER_END_ADDR_3 */ "", 13873 /* CMIC_SER_END_ADDR_4 */ "", 13874 /* CMIC_SER_END_ADDR_5 */ "", 13875 /* CMIC_SER_END_ADDR_6 */ "", 13876 /* CMIC_SER_END_ADDR_7 */ "", 13877 /* CMIC_SER_END_ADDR_8 */ "", 13878 /* CMIC_SER_END_ADDR_9 */ "", 13879 /* CMIC_SER_END_ADDR_10 */ "", 13880 /* CMIC_SER_END_ADDR_11 */ "", 13881 /* CMIC_SER_END_ADDR_12 */ "", 13882 /* CMIC_SER_END_ADDR_13 */ "", 13883 /* CMIC_SER_END_ADDR_14 */ "", 13884 /* CMIC_SER_END_ADDR_15 */ "", 13885 /* CMIC_SER_END_ADDR_16 */ "", 13886 /* CMIC_SER_END_ADDR_17 */ "", 13887 /* CMIC_SER_END_ADDR_18 */ "", 13888 /* CMIC_SER_END_ADDR_19 */ "", 13889 /* CMIC_SER_END_ADDR_20 */ "", 13890 /* CMIC_SER_END_ADDR_21 */ "", 13891 /* CMIC_SER_END_ADDR_22 */ "", 13892 /* CMIC_SER_END_ADDR_23 */ "", 13893 /* CMIC_SER_END_ADDR_24 */ "", 13894 /* CMIC_SER_END_ADDR_25 */ "", 13895 /* CMIC_SER_END_ADDR_26 */ "", 13896 /* CMIC_SER_END_ADDR_27 */ "", 13897 /* CMIC_SER_END_ADDR_28 */ "", 13898 /* CMIC_SER_END_ADDR_29 */ "", 13899 /* CMIC_SER_END_ADDR_30 */ "", 13900 /* CMIC_SER_END_ADDR_31 */ "", 13901 /* CMIC_SER_FAIL_CNT */ "", 13902 /* CMIC_SER_FAIL_ENTRY */ "", 13903 /* CMIC_SER_INTERLEAVE_PARITY */ "", 13904 /* CMIC_SER_MEM_ADDR */ "", 13905 /* CMIC_SER_MEM_ADDR_0 */ "", 13906 /* CMIC_SER_MEM_ADDR_1 */ "", 13907 /* CMIC_SER_MEM_ADDR_2 */ "", 13908 /* CMIC_SER_MEM_ADDR_3 */ "", 13909 /* CMIC_SER_MEM_ADDR_4 */ "", 13910 /* CMIC_SER_MEM_ADDR_5 */ "", 13911 /* CMIC_SER_MEM_ADDR_6 */ "", 13912 /* CMIC_SER_MEM_ADDR_7 */ "", 13913 /* CMIC_SER_MEM_ADDR_8 */ "", 13914 /* CMIC_SER_MEM_ADDR_9 */ "", 13915 /* CMIC_SER_MEM_ADDR_10 */ "", 13916 /* CMIC_SER_MEM_ADDR_11 */ "", 13917 /* CMIC_SER_MEM_ADDR_12 */ "", 13918 /* CMIC_SER_MEM_ADDR_13 */ "", 13919 /* CMIC_SER_MEM_ADDR_14 */ "", 13920 /* CMIC_SER_MEM_ADDR_15 */ "", 13921 /* CMIC_SER_MEM_ADDR_16 */ "", 13922 /* CMIC_SER_MEM_ADDR_17 */ "", 13923 /* CMIC_SER_MEM_ADDR_18 */ "", 13924 /* CMIC_SER_MEM_ADDR_19 */ "", 13925 /* CMIC_SER_MEM_ADDR_20 */ "", 13926 /* CMIC_SER_MEM_ADDR_21 */ "", 13927 /* CMIC_SER_MEM_ADDR_22 */ "", 13928 /* CMIC_SER_MEM_ADDR_23 */ "", 13929 /* CMIC_SER_MEM_ADDR_24 */ "", 13930 /* CMIC_SER_MEM_ADDR_25 */ "", 13931 /* CMIC_SER_MEM_ADDR_26 */ "", 13932 /* CMIC_SER_MEM_ADDR_27 */ "", 13933 /* CMIC_SER_MEM_ADDR_28 */ "", 13934 /* CMIC_SER_MEM_ADDR_29 */ "", 13935 /* CMIC_SER_MEM_ADDR_30 */ "", 13936 /* CMIC_SER_MEM_ADDR_31 */ "", 13937 /* CMIC_SER_MEM_DATA */ "", 13938 /* CMIC_SER_PARITY_MODE_SEL */ "", 13939 /* CMIC_SER_PARITY_MODE_SEL_15_0 */ "", 13940 /* CMIC_SER_PARITY_MODE_SEL_31_16 */ "", 13941 /* CMIC_SER_POWER_DOWN_MEM_LOWER */ "", 13942 /* CMIC_SER_POWER_DOWN_MEM_UPPER */ "", 13943 /* CMIC_SER_PROTECT_ADDR_RANGE_VALID */ "", 13944 /* CMIC_SER_RANGE0_DATAENTRY_LEN */ "", 13945 /* CMIC_SER_RANGE10_DATAENTRY_LEN */ "", 13946 /* CMIC_SER_RANGE11_DATAENTRY_LEN */ "", 13947 /* CMIC_SER_RANGE12_DATAENTRY_LEN */ "", 13948 /* CMIC_SER_RANGE13_DATAENTRY_LEN */ "", 13949 /* CMIC_SER_RANGE14_DATAENTRY_LEN */ "", 13950 /* CMIC_SER_RANGE15_DATAENTRY_LEN */ "", 13951 /* CMIC_SER_RANGE16_DATAENTRY_LEN */ "", 13952 /* CMIC_SER_RANGE17_DATAENTRY_LEN */ "", 13953 /* CMIC_SER_RANGE18_DATAENTRY_LEN */ "", 13954 /* CMIC_SER_RANGE19_DATAENTRY_LEN */ "", 13955 /* CMIC_SER_RANGE1_DATAENTRY_LEN */ "", 13956 /* CMIC_SER_RANGE20_DATAENTRY_LEN */ "", 13957 /* CMIC_SER_RANGE21_DATAENTRY_LEN */ "", 13958 /* CMIC_SER_RANGE22_DATAENTRY_LEN */ "", 13959 /* CMIC_SER_RANGE23_DATAENTRY_LEN */ "", 13960 /* CMIC_SER_RANGE24_DATAENTRY_LEN */ "", 13961 /* CMIC_SER_RANGE25_DATAENTRY_LEN */ "", 13962 /* CMIC_SER_RANGE26_DATAENTRY_LEN */ "", 13963 /* CMIC_SER_RANGE27_DATAENTRY_LEN */ "", 13964 /* CMIC_SER_RANGE28_DATAENTRY_LEN */ "", 13965 /* CMIC_SER_RANGE29_DATAENTRY_LEN */ "", 13966 /* CMIC_SER_RANGE2_DATAENTRY_LEN */ "", 13967 /* CMIC_SER_RANGE30_DATAENTRY_LEN */ "", 13968 /* CMIC_SER_RANGE31_DATAENTRY_LEN */ "", 13969 /* CMIC_SER_RANGE3_DATAENTRY_LEN */ "", 13970 /* CMIC_SER_RANGE4_DATAENTRY_LEN */ "", 13971 /* CMIC_SER_RANGE5_DATAENTRY_LEN */ "", 13972 /* CMIC_SER_RANGE6_DATAENTRY_LEN */ "", 13973 /* CMIC_SER_RANGE7_DATAENTRY_LEN */ "", 13974 /* CMIC_SER_RANGE8_DATAENTRY_LEN */ "", 13975 /* CMIC_SER_RANGE9_DATAENTRY_LEN */ "", 13976 /* CMIC_SER_START_ADDR_0 */ "", 13977 /* CMIC_SER_START_ADDR_1 */ "", 13978 /* CMIC_SER_START_ADDR_2 */ "", 13979 /* CMIC_SER_START_ADDR_3 */ "", 13980 /* CMIC_SER_START_ADDR_4 */ "", 13981 /* CMIC_SER_START_ADDR_5 */ "", 13982 /* CMIC_SER_START_ADDR_6 */ "", 13983 /* CMIC_SER_START_ADDR_7 */ "", 13984 /* CMIC_SER_START_ADDR_8 */ "", 13985 /* CMIC_SER_START_ADDR_9 */ "", 13986 /* CMIC_SER_START_ADDR_10 */ "", 13987 /* CMIC_SER_START_ADDR_11 */ "", 13988 /* CMIC_SER_START_ADDR_12 */ "", 13989 /* CMIC_SER_START_ADDR_13 */ "", 13990 /* CMIC_SER_START_ADDR_14 */ "", 13991 /* CMIC_SER_START_ADDR_15 */ "", 13992 /* CMIC_SER_START_ADDR_16 */ "", 13993 /* CMIC_SER_START_ADDR_17 */ "", 13994 /* CMIC_SER_START_ADDR_18 */ "", 13995 /* CMIC_SER_START_ADDR_19 */ "", 13996 /* CMIC_SER_START_ADDR_20 */ "", 13997 /* CMIC_SER_START_ADDR_21 */ "", 13998 /* CMIC_SER_START_ADDR_22 */ "", 13999 /* CMIC_SER_START_ADDR_23 */ "", 14000 /* CMIC_SER_START_ADDR_24 */ "", 14001 /* CMIC_SER_START_ADDR_25 */ "", 14002 /* CMIC_SER_START_ADDR_26 */ "", 14003 /* CMIC_SER_START_ADDR_27 */ "", 14004 /* CMIC_SER_START_ADDR_28 */ "", 14005 /* CMIC_SER_START_ADDR_29 */ "", 14006 /* CMIC_SER_START_ADDR_30 */ "", 14007 /* CMIC_SER_START_ADDR_31 */ "", 14008 /* CMIC_SLAM_DMA_CFG */ "", 14009 /* CMIC_SLAM_DMA_CUR_ENTRY_SBUS_ADDR */ "", 14010 /* CMIC_SLAM_DMA_ENTRY_COUNT */ "", 14011 /* CMIC_SLAM_DMA_PCIMEM_START_ADDR */ "", 14012 /* CMIC_SLAM_DMA_SBUS_START_ADDR */ "", 14013 /* CMIC_SOFT_RESET_REG */ "", 14014 /* CMIC_SOFT_RESET_REG_2 */ "", 14015 /* CMIC_SRAM_TM0_CONTROL */ "", 14016 /* CMIC_SRAM_TM1_CONTROL */ "", 14017 /* CMIC_SRAM_TM2_CONTROL */ "", 14018 /* CMIC_SRAM_TM3_CONTROL */ "", 14019 /* CMIC_SRAM_TM_CONTROL */ "", 14020 /* CMIC_SRAM_TM_CONTROL_2 */ "", 14021 /* CMIC_STAT_DMA_ADDR */ "", 14022 /* CMIC_STAT_DMA_BLKNUM_MAP_95 */ "", 14023 /* CMIC_STAT_DMA_BLKNUM_MAP_14_10 */ "", 14024 /* CMIC_STAT_DMA_BLKNUM_MAP_15_8 */ "", 14025 /* CMIC_STAT_DMA_BLKNUM_MAP_19_15 */ "", 14026 /* CMIC_STAT_DMA_BLKNUM_MAP_23_16 */ "", 14027 /* CMIC_STAT_DMA_BLKNUM_MAP_24_20 */ "", 14028 /* CMIC_STAT_DMA_BLKNUM_MAP_29_25 */ "", 14029 /* CMIC_STAT_DMA_BLKNUM_MAP_31_24 */ "", 14030 /* CMIC_STAT_DMA_BLKNUM_MAP_34_30 */ "", 14031 /* CMIC_STAT_DMA_BLKNUM_MAP_39_32 */ "", 14032 /* CMIC_STAT_DMA_BLKNUM_MAP_39_35 */ "", 14033 /* CMIC_STAT_DMA_BLKNUM_MAP_44_40 */ "", 14034 /* CMIC_STAT_DMA_BLKNUM_MAP_47_40 */ "", 14035 /* CMIC_STAT_DMA_BLKNUM_MAP_49_45 */ "", 14036 /* CMIC_STAT_DMA_BLKNUM_MAP_4_0 */ "", 14037 /* CMIC_STAT_DMA_BLKNUM_MAP_54_50 */ "", 14038 /* CMIC_STAT_DMA_BLKNUM_MAP_55_48 */ "", 14039 /* CMIC_STAT_DMA_BLKNUM_MAP_59_55 */ "", 14040 /* CMIC_STAT_DMA_BLKNUM_MAP_63_56 */ "", 14041 /* CMIC_STAT_DMA_BLKNUM_MAP_63_60 */ "", 14042 /* CMIC_STAT_DMA_BLKNUM_MAP_64_60 */ "", 14043 /* CMIC_STAT_DMA_BLKNUM_MAP_69_65 */ "", 14044 /* CMIC_STAT_DMA_BLKNUM_MAP_74_70 */ "", 14045 /* CMIC_STAT_DMA_BLKNUM_MAP_79_75 */ "", 14046 /* CMIC_STAT_DMA_BLKNUM_MAP_7_0 */ "", 14047 /* CMIC_STAT_DMA_BLKNUM_MAP_84_80 */ "", 14048 /* CMIC_STAT_DMA_BLKNUM_MAP_89_85 */ "", 14049 /* CMIC_STAT_DMA_BLKNUM_MAP_94_90 */ "", 14050 /* CMIC_STAT_DMA_BLKNUM_MAP_9_5 */ "", 14051 /* CMIC_STAT_DMA_CURRENT */ "", 14052 /* CMIC_STAT_DMA_EGR_STATS_CFG */ "", 14053 /* CMIC_STAT_DMA_ING_STATS_CFG */ "", 14054 /* CMIC_STAT_DMA_MAC_STATS_CFG */ "", 14055 /* CMIC_STAT_DMA_PORTNUM_MAP_11_6 */ "", 14056 /* CMIC_STAT_DMA_PORTNUM_MAP_11_8 */ "", 14057 /* CMIC_STAT_DMA_PORTNUM_MAP_15_8 */ "", 14058 /* CMIC_STAT_DMA_PORTNUM_MAP_15_12 */ "", 14059 /* CMIC_STAT_DMA_PORTNUM_MAP_17_12 */ "", 14060 /* CMIC_STAT_DMA_PORTNUM_MAP_19_16 */ "", 14061 /* CMIC_STAT_DMA_PORTNUM_MAP_23_16 */ "", 14062 /* CMIC_STAT_DMA_PORTNUM_MAP_23_18 */ "", 14063 /* CMIC_STAT_DMA_PORTNUM_MAP_23_20 */ "", 14064 /* CMIC_STAT_DMA_PORTNUM_MAP_27_24 */ "", 14065 /* CMIC_STAT_DMA_PORTNUM_MAP_31_24 */ "", 14066 /* CMIC_STAT_DMA_PORTNUM_MAP_31_28 */ "", 14067 /* CMIC_STAT_DMA_PORTNUM_MAP_35_32 */ "", 14068 /* CMIC_STAT_DMA_PORTNUM_MAP_39_36 */ "", 14069 /* CMIC_STAT_DMA_PORTNUM_MAP_3_0 */ "", 14070 /* CMIC_STAT_DMA_PORTNUM_MAP_43_40 */ "", 14071 /* CMIC_STAT_DMA_PORTNUM_MAP_47_44 */ "", 14072 /* CMIC_STAT_DMA_PORTNUM_MAP_51_48 */ "", 14073 /* CMIC_STAT_DMA_PORTNUM_MAP_55_52 */ "", 14074 /* CMIC_STAT_DMA_PORTNUM_MAP_59_56 */ "", 14075 /* CMIC_STAT_DMA_PORTNUM_MAP_5_0 */ "", 14076 /* CMIC_STAT_DMA_PORTNUM_MAP_63_60 */ "", 14077 /* CMIC_STAT_DMA_PORTNUM_MAP_67_64 */ "", 14078 /* CMIC_STAT_DMA_PORTNUM_MAP_71_68 */ "", 14079 /* CMIC_STAT_DMA_PORTNUM_MAP_75_72 */ "", 14080 /* CMIC_STAT_DMA_PORTNUM_MAP_79_76 */ "", 14081 /* CMIC_STAT_DMA_PORTNUM_MAP_7_0 */ "", 14082 /* CMIC_STAT_DMA_PORTNUM_MAP_7_4 */ "", 14083 /* CMIC_STAT_DMA_PORTNUM_MAP_83_80 */ "", 14084 /* CMIC_STAT_DMA_PORTNUM_MAP_87_84 */ "", 14085 /* CMIC_STAT_DMA_PORTNUM_MAP_91_88 */ "", 14086 /* CMIC_STAT_DMA_PORTNUM_MAP_95_92 */ "", 14087 /* CMIC_STAT_DMA_PORTS */ "", 14088 /* CMIC_STAT_DMA_PORTS_HI */ "", 14089 /* CMIC_STAT_DMA_PORTS_HI_2 */ "", 14090 /* CMIC_STAT_DMA_PORT_TYPE_MAP */ "", 14091 /* CMIC_STAT_DMA_PORT_TYPE_MAP_0 */ "", 14092 /* CMIC_STAT_DMA_PORT_TYPE_MAP_1 */ "", 14093 /* CMIC_STAT_DMA_PORT_TYPE_MAP_2 */ "", 14094 /* CMIC_STAT_DMA_PORT_TYPE_MAP_HI */ "", 14095 /* CMIC_STAT_DMA_PORT_TYPE_MAP_HI_2 */ "", 14096 /* CMIC_STAT_DMA_SBUS_START_ADDRESS */ "", 14097 /* CMIC_STAT_DMA_SETUP */ "", 14098 /* CMIC_STRAP_OPTIONS */ "", 14099 /* CMIC_SWITCH_FEATURE_ENABLE */ "", 14100 /* CMIC_SWITCH_FEATURE_ENABLE_1 */ "", 14101 /* CMIC_SWITCH_FEATURE_ENABLE_2 */ "", 14102 /* CMIC_SW_PIO_ACK_DATA_BEAT_COUNT */ "", 14103 /* CMIC_SW_RST */ "", 14104 /* CMIC_TABLE_DMA_CFG */ "", 14105 /* CMIC_TABLE_DMA_CUR_ENTRY_SBUS_ADDR */ "", 14106 /* CMIC_TABLE_DMA_ENTRY_COUNT */ "", 14107 /* CMIC_TABLE_DMA_PCIMEM_START_ADDR */ "", 14108 /* CMIC_TABLE_DMA_SBUS_START_ADDR */ "", 14109 /* CMIC_TAP_CONTROL */ "", 14110 /* CMIC_THERMAL_MON_CALIBRATION */ "", 14111 /* CMIC_THERMAL_MON_CTRL */ "", 14112 /* CMIC_THERMAL_MON_RESULT */ "", 14113 /* CMIC_THERMAL_MON_RESULT_0 */ "", 14114 /* CMIC_THERMAL_MON_RESULT_1 */ "", 14115 /* CMIC_THERMAL_MON_RESULT_2 */ "", 14116 /* CMIC_THERMAL_MON_RESULT_3 */ "", 14117 /* CMIC_THERMAL_MON_RESULT_4 */ "", 14118 /* CMIC_THERMAL_MON_RESULT_5 */ "", 14119 /* CMIC_THERMAL_MON_RESULT_6 */ "", 14120 /* CMIC_THERMAL_MON_RESULT_7 */ "", 14121 /* CMIC_TIM0_TIMER1BGLOAD */ "", 14122 /* CMIC_TIM0_TIMER1CONTROL */ "", 14123 /* CMIC_TIM0_TIMER1INTCLR */ "", 14124 /* CMIC_TIM0_TIMER1LOAD */ "", 14125 /* CMIC_TIM0_TIMER1MIS */ "", 14126 /* CMIC_TIM0_TIMER1RIS */ "", 14127 /* CMIC_TIM0_TIMER1VALUE */ "", 14128 /* CMIC_TIM0_TIMER2BGLOAD */ "", 14129 /* CMIC_TIM0_TIMER2CONTROL */ "", 14130 /* CMIC_TIM0_TIMER2INTCLR */ "", 14131 /* CMIC_TIM0_TIMER2LOAD */ "", 14132 /* CMIC_TIM0_TIMER2MIS */ "", 14133 /* CMIC_TIM0_TIMER2RIS */ "", 14134 /* CMIC_TIM0_TIMER2VALUE */ "", 14135 /* CMIC_TIM0_TIMERITCR */ "", 14136 /* CMIC_TIM0_TIMERITOP */ "", 14137 /* CMIC_TIM0_TIMERPCELLID0 */ "", 14138 /* CMIC_TIM0_TIMERPCELLID1 */ "", 14139 /* CMIC_TIM0_TIMERPCELLID2 */ "", 14140 /* CMIC_TIM0_TIMERPCELLID3 */ "", 14141 /* CMIC_TIM0_TIMERPERIPHID0 */ "", 14142 /* CMIC_TIM0_TIMERPERIPHID1 */ "", 14143 /* CMIC_TIM0_TIMERPERIPHID2 */ "", 14144 /* CMIC_TIM0_TIMERPERIPHID3 */ "", 14145 /* CMIC_TIM1_TIMER1BGLOAD */ "", 14146 /* CMIC_TIM1_TIMER1CONTROL */ "", 14147 /* CMIC_TIM1_TIMER1INTCLR */ "", 14148 /* CMIC_TIM1_TIMER1LOAD */ "", 14149 /* CMIC_TIM1_TIMER1MIS */ "", 14150 /* CMIC_TIM1_TIMER1RIS */ "", 14151 /* CMIC_TIM1_TIMER1VALUE */ "", 14152 /* CMIC_TIM1_TIMER2BGLOAD */ "", 14153 /* CMIC_TIM1_TIMER2CONTROL */ "", 14154 /* CMIC_TIM1_TIMER2INTCLR */ "", 14155 /* CMIC_TIM1_TIMER2LOAD */ "", 14156 /* CMIC_TIM1_TIMER2MIS */ "", 14157 /* CMIC_TIM1_TIMER2RIS */ "", 14158 /* CMIC_TIM1_TIMER2VALUE */ "", 14159 /* CMIC_TIM1_TIMERITCR */ "", 14160 /* CMIC_TIM1_TIMERITOP */ "", 14161 /* CMIC_TIM1_TIMERPCELLID0 */ "", 14162 /* CMIC_TIM1_TIMERPCELLID1 */ "", 14163 /* CMIC_TIM1_TIMERPCELLID2 */ "", 14164 /* CMIC_TIM1_TIMERPCELLID3 */ "", 14165 /* CMIC_TIM1_TIMERPERIPHID0 */ "", 14166 /* CMIC_TIM1_TIMERPERIPHID1 */ "", 14167 /* CMIC_TIM1_TIMERPERIPHID2 */ "", 14168 /* CMIC_TIM1_TIMERPERIPHID3 */ "", 14169 /* CMIC_TIMESYNC_BROADSYNC0_CLK_COUNT_CTRL */ "", 14170 /* CMIC_TIMESYNC_BROADSYNC1_CLK_COUNT_CTRL */ "", 14171 /* CMIC_TIMESYNC_CAPTURE_STATUS_1 */ "", 14172 /* CMIC_TIMESYNC_CAPTURE_STATUS_CLR_1 */ "", 14173 /* CMIC_TIMESYNC_CONTROL */ "", 14174 /* CMIC_TIMESYNC_COUNTER_CONFIG_SELECT */ "", 14175 /* CMIC_TIMESYNC_DEBUG_CTRL */ "", 14176 /* CMIC_TIMESYNC_FIFO_ECC_CONFIG */ "", 14177 /* CMIC_TIMESYNC_FIFO_ECC_STATUS */ "", 14178 /* CMIC_TIMESYNC_FIFO_STATUS */ "", 14179 /* CMIC_TIMESYNC_GPIO_0_CTRL */ "", 14180 /* CMIC_TIMESYNC_GPIO_0_DOWN_EVENT_CTRL */ "", 14181 /* CMIC_TIMESYNC_GPIO_0_INPUT_DIVISOR */ "", 14182 /* CMIC_TIMESYNC_GPIO_0_OUTPUT_ENABLE */ "", 14183 /* CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_LOWER */ "", 14184 /* CMIC_TIMESYNC_GPIO_0_PHASE_ADJUST_UPPER */ "", 14185 /* CMIC_TIMESYNC_GPIO_0_UP_EVENT_CTRL */ "", 14186 /* CMIC_TIMESYNC_GPIO_1_CTRL */ "", 14187 /* CMIC_TIMESYNC_GPIO_1_DOWN_EVENT_CTRL */ "", 14188 /* CMIC_TIMESYNC_GPIO_1_INPUT_DIVISOR */ "", 14189 /* CMIC_TIMESYNC_GPIO_1_OUTPUT_ENABLE */ "", 14190 /* CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_LOWER */ "", 14191 /* CMIC_TIMESYNC_GPIO_1_PHASE_ADJUST_UPPER */ "", 14192 /* CMIC_TIMESYNC_GPIO_1_UP_EVENT_CTRL */ "", 14193 /* CMIC_TIMESYNC_GPIO_2_CTRL */ "", 14194 /* CMIC_TIMESYNC_GPIO_2_DOWN_EVENT_CTRL */ "", 14195 /* CMIC_TIMESYNC_GPIO_2_INPUT_DIVISOR */ "", 14196 /* CMIC_TIMESYNC_GPIO_2_OUTPUT_ENABLE */ "", 14197 /* CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_LOWER */ "", 14198 /* CMIC_TIMESYNC_GPIO_2_PHASE_ADJUST_UPPER */ "", 14199 /* CMIC_TIMESYNC_GPIO_2_UP_EVENT_CTRL */ "", 14200 /* CMIC_TIMESYNC_GPIO_3_CTRL */ "", 14201 /* CMIC_TIMESYNC_GPIO_3_DOWN_EVENT_CTRL */ "", 14202 /* CMIC_TIMESYNC_GPIO_3_INPUT_DIVISOR */ "", 14203 /* CMIC_TIMESYNC_GPIO_3_OUTPUT_ENABLE */ "", 14204 /* CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_LOWER */ "", 14205 /* CMIC_TIMESYNC_GPIO_3_PHASE_ADJUST_UPPER */ "", 14206 /* CMIC_TIMESYNC_GPIO_3_UP_EVENT_CTRL */ "", 14207 /* CMIC_TIMESYNC_GPIO_4_CTRL */ "", 14208 /* CMIC_TIMESYNC_GPIO_4_DOWN_EVENT_CTRL */ "", 14209 /* CMIC_TIMESYNC_GPIO_4_INPUT_DIVISOR */ "", 14210 /* CMIC_TIMESYNC_GPIO_4_OUTPUT_ENABLE */ "", 14211 /* CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_LOWER */ "", 14212 /* CMIC_TIMESYNC_GPIO_4_PHASE_ADJUST_UPPER */ "", 14213 /* CMIC_TIMESYNC_GPIO_4_UP_EVENT_CTRL */ "", 14214 /* CMIC_TIMESYNC_GPIO_5_CTRL */ "", 14215 /* CMIC_TIMESYNC_GPIO_5_DOWN_EVENT_CTRL */ "", 14216 /* CMIC_TIMESYNC_GPIO_5_INPUT_DIVISOR */ "", 14217 /* CMIC_TIMESYNC_GPIO_5_OUTPUT_ENABLE */ "", 14218 /* CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_LOWER */ "", 14219 /* CMIC_TIMESYNC_GPIO_5_PHASE_ADJUST_UPPER */ "", 14220 /* CMIC_TIMESYNC_GPIO_5_UP_EVENT_CTRL */ "", 14221 /* CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_LOWER */ "", 14222 /* CMIC_TIMESYNC_INPUT_TIME_FIFO_TS_UPPER */ "", 14223 /* CMIC_TIMESYNC_INTERRUPT_CLR */ "", 14224 /* CMIC_TIMESYNC_INTERRUPT_ENABLE */ "", 14225 /* CMIC_TIMESYNC_INTERRUPT_STATUS */ "", 14226 /* CMIC_TIMESYNC_SYNCE_CLK1_COUNT_CTRL */ "", 14227 /* CMIC_TIMESYNC_SYNCE_CLK2_COUNT_CTRL */ "", 14228 /* CMIC_TIMESYNC_SYNCE_CLK3_COUNT_CTRL */ "", 14229 /* CMIC_TIMESYNC_SYNCE_CLK4_COUNT_CTRL */ "", 14230 /* CMIC_TIMESYNC_SYNCE_CLK5_COUNT_CTRL */ "", 14231 /* CMIC_TIMESYNC_TIMER */ "", 14232 /* CMIC_TIMESYNC_TIME_CAPTURE_CONTROL */ "", 14233 /* CMIC_TIMESYNC_TIME_CAPTURE_MODE */ "", 14234 /* CMIC_TIMESYNC_TM */ "", 14235 /* CMIC_TIMESYNC_TS0_COUNTER_ENABLE */ "", 14236 /* CMIC_TIMESYNC_TS0_FREQ_CTRL_FRAC */ "", 14237 /* CMIC_TIMESYNC_TS0_FREQ_CTRL_LOWER */ "", 14238 /* CMIC_TIMESYNC_TS0_FREQ_CTRL_UPPER */ "", 14239 /* CMIC_TIMESYNC_TS1_COUNTER_ENABLE */ "", 14240 /* CMIC_TIMESYNC_TS1_FREQ_CTRL_FRAC */ "", 14241 /* CMIC_TIMESYNC_TS1_FREQ_CTRL_LOWER */ "", 14242 /* CMIC_TIMESYNC_TS1_FREQ_CTRL_UPPER */ "", 14243 /* CMIC_TOP_CONFIG */ "", 14244 /* CMIC_TOP_EPINTF_BUF_DEPTH */ "", 14245 /* CMIC_TOP_EPINTF_MAX_INTERFACE_CREDITS */ "", 14246 /* CMIC_TOP_EPINTF_RELEASE_ALL_CREDITS */ "", 14247 /* CMIC_TOP_EP_TO_CPU_HEADER_SIZE */ "", 14248 /* CMIC_TOP_IPINTF_BUF_DEPTH */ "", 14249 /* CMIC_TOP_IPINTF_INTERFACE_CREDITS */ "", 14250 /* CMIC_TOP_IPINTF_WRR_ARB_CTRL */ "", 14251 /* CMIC_TOP_PKT_COUNT_RXPKT */ "", 14252 /* CMIC_TOP_PKT_COUNT_RXPKT_DROP */ "", 14253 /* CMIC_TOP_PKT_COUNT_RXPKT_ERR */ "", 14254 /* CMIC_TOP_PKT_COUNT_TXPKT */ "", 14255 /* CMIC_TOP_PKT_COUNT_TXPKT_ERR */ "", 14256 /* CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA */ "", 14257 /* CMIC_TOP_SBUS_RING_ARB_CTRL_FIFODMA_1 */ "", 14258 /* CMIC_TOP_SBUS_RING_ARB_CTRL_RPE_SCHAN */ "", 14259 /* CMIC_TOP_SBUS_RING_ARB_CTRL_SBUSDMA */ "", 14260 /* CMIC_TOP_SBUS_RING_ARB_CTRL_SCHAN */ "", 14261 /* CMIC_TOP_SBUS_RING_MAP_0_7 */ "", 14262 /* CMIC_TOP_SBUS_RING_MAP_104_111 */ "", 14263 /* CMIC_TOP_SBUS_RING_MAP_112_119 */ "", 14264 /* CMIC_TOP_SBUS_RING_MAP_120_127 */ "", 14265 /* CMIC_TOP_SBUS_RING_MAP_16_23 */ "", 14266 /* CMIC_TOP_SBUS_RING_MAP_24_31 */ "", 14267 /* CMIC_TOP_SBUS_RING_MAP_32_39 */ "", 14268 /* CMIC_TOP_SBUS_RING_MAP_40_47 */ "", 14269 /* CMIC_TOP_SBUS_RING_MAP_48_55 */ "", 14270 /* CMIC_TOP_SBUS_RING_MAP_56_63 */ "", 14271 /* CMIC_TOP_SBUS_RING_MAP_64_71 */ "", 14272 /* CMIC_TOP_SBUS_RING_MAP_72_79 */ "", 14273 /* CMIC_TOP_SBUS_RING_MAP_80_87 */ "", 14274 /* CMIC_TOP_SBUS_RING_MAP_88_95 */ "", 14275 /* CMIC_TOP_SBUS_RING_MAP_8_15 */ "", 14276 /* CMIC_TOP_SBUS_RING_MAP_96_103 */ "", 14277 /* CMIC_TOP_SBUS_TIMEOUT */ "", 14278 /* CMIC_TOP_STATISTICS_COUNTER_CONTROL */ "", 14279 /* CMIC_TOP_STATISTICS_COUNTER_STATUS */ "", 14280 /* CMIC_TOP_STATISTICS_EP_BYTE_COUNT_HI */ "", 14281 /* CMIC_TOP_STATISTICS_EP_BYTE_COUNT_LO */ "", 14282 /* CMIC_TOP_STATISTICS_EP_PKT_COUNT */ "", 14283 /* CMIC_TOP_STATISTICS_IP_BYTE_COUNT_HI */ "", 14284 /* CMIC_TOP_STATISTICS_IP_BYTE_COUNT_LO */ "", 14285 /* CMIC_TOP_STATISTICS_IP_PKT_COUNT */ "", 14286 /* CMIC_TOP_TO_MMU_COS_MASK_LSB_BITS */ "", 14287 /* CMIC_TOP_TO_MMU_COS_MASK_MSB_BITS */ "", 14288 /* CMIC_TO_CORE_PLL_CONTROL_1 */ "", 14289 /* CMIC_TO_CORE_PLL_CONTROL_2 */ "", 14290 /* CMIC_TO_CORE_PLL_X2_1_CONTROL_1 */ "", 14291 /* CMIC_TO_CORE_PLL_X2_1_CONTROL_2 */ "", 14292 /* CMIC_TO_CORE_PLL_X2_2_CONTROL_1 */ "", 14293 /* CMIC_TO_CORE_PLL_X2_2_CONTROL_2 */ "", 14294 /* CMIC_TO_CORE_PLL_X2_3_CONTROL_1 */ "", 14295 /* CMIC_TO_CORE_PLL_X2_3_CONTROL_2 */ "", 14296 /* CMIC_TS_CAPTURE_STATUS */ "", 14297 /* CMIC_TS_CAPTURE_STATUS_CLR */ "", 14298 /* CMIC_TS_FIFO_STATUS */ "", 14299 /* CMIC_TS_FREQ_CTRL_LOWER */ "", 14300 /* CMIC_TS_FREQ_CTRL_UPPER */ "", 14301 /* CMIC_TS_GPIO_1_CTRL */ "", 14302 /* CMIC_TS_GPIO_1_DOWN_EVENT_CTRL */ "", 14303 /* CMIC_TS_GPIO_1_OUTPUT_ENABLE */ "", 14304 /* CMIC_TS_GPIO_1_PHASE_ADJUST */ "", 14305 /* CMIC_TS_GPIO_1_UP_EVENT_CTRL */ "", 14306 /* CMIC_TS_GPIO_2_CTRL */ "", 14307 /* CMIC_TS_GPIO_2_DOWN_EVENT_CTRL */ "", 14308 /* CMIC_TS_GPIO_2_OUTPUT_ENABLE */ "", 14309 /* CMIC_TS_GPIO_2_PHASE_ADJUST */ "", 14310 /* CMIC_TS_GPIO_2_UP_EVENT_CTRL */ "", 14311 /* CMIC_TS_GPIO_3_CTRL */ "", 14312 /* CMIC_TS_GPIO_3_DOWN_EVENT_CTRL */ "", 14313 /* CMIC_TS_GPIO_3_OUTPUT_ENABLE */ "", 14314 /* CMIC_TS_GPIO_3_PHASE_ADJUST */ "", 14315 /* CMIC_TS_GPIO_3_UP_EVENT_CTRL */ "", 14316 /* CMIC_TS_GPIO_4_CTRL */ "", 14317 /* CMIC_TS_GPIO_4_DOWN_EVENT_CTRL */ "", 14318 /* CMIC_TS_GPIO_4_OUTPUT_ENABLE */ "", 14319 /* CMIC_TS_GPIO_4_PHASE_ADJUST */ "", 14320 /* CMIC_TS_GPIO_4_UP_EVENT_CTRL */ "", 14321 /* CMIC_TS_GPIO_5_CTRL */ "", 14322 /* CMIC_TS_GPIO_5_DOWN_EVENT_CTRL */ "", 14323 /* CMIC_TS_GPIO_5_OUTPUT_ENABLE */ "", 14324 /* CMIC_TS_GPIO_5_PHASE_ADJUST */ "", 14325 /* CMIC_TS_GPIO_5_UP_EVENT_CTRL */ "", 14326 /* CMIC_TS_GPIO_6_CTRL */ "", 14327 /* CMIC_TS_GPIO_6_DOWN_EVENT_CTRL */ "", 14328 /* CMIC_TS_GPIO_6_OUTPUT_ENABLE */ "", 14329 /* CMIC_TS_GPIO_6_PHASE_ADJUST */ "", 14330 /* CMIC_TS_GPIO_6_UP_EVENT_CTRL */ "", 14331 /* CMIC_TS_INPUT_TIME_FIFO_ID */ "", 14332 /* CMIC_TS_INPUT_TIME_FIFO_TS */ "", 14333 /* CMIC_TS_L1_CLK_RECOVERED_CLK_BKUP_COUNT_CTRL */ "", 14334 /* CMIC_TS_L1_CLK_RECOVERED_CLK_COUNT_CTRL */ "", 14335 /* CMIC_TS_LCPLL_CLK_COUNT_CTRL */ "", 14336 /* CMIC_TS_TIME_CAPTURE_CTRL */ "", 14337 /* CMIC_TXBUF_CMC0_PKT_CNT */ "", 14338 /* CMIC_TXBUF_CMC1_PKT_CNT */ "", 14339 /* CMIC_TXBUF_CMC2_PKT_CNT */ "", 14340 /* CMIC_TXBUF_CONFIG */ "", 14341 /* CMIC_TXBUF_DATABUF_MAX_FLIST_ENTRIES */ "", 14342 /* CMIC_TXBUF_DATABUF_NUM_FREE_ENTRIES */ "", 14343 /* CMIC_TXBUF_DATABUF_TM_0 */ "", 14344 /* CMIC_TXBUF_DATABUF_TM_1 */ "", 14345 /* CMIC_TXBUF_DEBUG */ "", 14346 /* CMIC_TXBUF_ECCERR_CONTROL */ "", 14347 /* CMIC_TXBUF_IPINTF_BUF_DEPTH */ "", 14348 /* CMIC_TXBUF_IPINTF_INTERFACE_CREDITS */ "", 14349 /* CMIC_TXBUF_MAX_BUF_LIMITS */ "", 14350 /* CMIC_TXBUF_MHDRBUF_TM_0 */ "", 14351 /* CMIC_TXBUF_MIN_BUF_LIMITS */ "", 14352 /* CMIC_TXBUF_RPE_PKT_CNT */ "", 14353 /* CMIC_TXBUF_STAT */ "", 14354 /* CMIC_TXBUF_STAT_CLR */ "", 14355 /* CMIC_TXBUF_TM_CONTROL */ "", 14356 /* CMIC_TXBUF_TM_CONTROL_1 */ "", 14357 /* CMIC_TX_PAUSE_CAPABILITY */ "", 14358 /* CMIC_TX_PAUSE_OVERRIDE_CONTROL */ "", 14359 /* CMIC_TX_PAUSE_STAT */ "", 14360 /* CMIC_UART0_CPR */ "", 14361 /* CMIC_UART0_CTR */ "", 14362 /* CMIC_UART0_DLH_IER */ "", 14363 /* CMIC_UART0_DMASA */ "", 14364 /* CMIC_UART0_FAR */ "", 14365 /* CMIC_UART0_HTX */ "", 14366 /* CMIC_UART0_IIR_FCR */ "", 14367 /* CMIC_UART0_LCR */ "", 14368 /* CMIC_UART0_LPDLH */ "", 14369 /* CMIC_UART0_LPDLL */ "", 14370 /* CMIC_UART0_LSR */ "", 14371 /* CMIC_UART0_MCR */ "", 14372 /* CMIC_UART0_MSR */ "", 14373 /* CMIC_UART0_RBR_THR_DLL */ "", 14374 /* CMIC_UART0_RFL */ "", 14375 /* CMIC_UART0_RFW */ "", 14376 /* CMIC_UART0_SBCR */ "", 14377 /* CMIC_UART0_SCR */ "", 14378 /* CMIC_UART0_SDMAM */ "", 14379 /* CMIC_UART0_SFE */ "", 14380 /* CMIC_UART0_SRBR_STHR */ "", 14381 /* CMIC_UART0_SRR */ "", 14382 /* CMIC_UART0_SRT */ "", 14383 /* CMIC_UART0_SRTS */ "", 14384 /* CMIC_UART0_STET */ "", 14385 /* CMIC_UART0_TFL */ "", 14386 /* CMIC_UART0_TFR */ "", 14387 /* CMIC_UART0_UCV */ "", 14388 /* CMIC_UART0_USR */ "", 14389 /* CMIC_UART1_CPR */ "", 14390 /* CMIC_UART1_CTR */ "", 14391 /* CMIC_UART1_DLH_IER */ "", 14392 /* CMIC_UART1_DMASA */ "", 14393 /* CMIC_UART1_FAR */ "", 14394 /* CMIC_UART1_HTX */ "", 14395 /* CMIC_UART1_IIR_FCR */ "", 14396 /* CMIC_UART1_LCR */ "", 14397 /* CMIC_UART1_LPDLH */ "", 14398 /* CMIC_UART1_LPDLL */ "", 14399 /* CMIC_UART1_LSR */ "", 14400 /* CMIC_UART1_MCR */ "", 14401 /* CMIC_UART1_MSR */ "", 14402 /* CMIC_UART1_RBR_THR_DLL */ "", 14403 /* CMIC_UART1_RFL */ "", 14404 /* CMIC_UART1_RFW */ "", 14405 /* CMIC_UART1_SBCR */ "", 14406 /* CMIC_UART1_SCR */ "", 14407 /* CMIC_UART1_SDMAM */ "", 14408 /* CMIC_UART1_SFE */ "", 14409 /* CMIC_UART1_SRBR_STHR */ "", 14410 /* CMIC_UART1_SRR */ "", 14411 /* CMIC_UART1_SRT */ "", 14412 /* CMIC_UART1_SRTS */ "", 14413 /* CMIC_UART1_STET */ "", 14414 /* CMIC_UART1_TFL */ "", 14415 /* CMIC_UART1_TFR */ "", 14416 /* CMIC_UART1_UCV */ "", 14417 /* CMIC_UART1_USR */ "", 14418 /* CMIC_UC0_CONFIG */ "", 14419 /* CMIC_UC1_CONFIG */ "", 14420 /* CMIC_V3_MIIM_BUS_SEL_MAP_127_120 */ "CMIC_MIIM_BUS_SEL_MAP_127_120", 14421 /* CMIC_XGXS0_PLL_CONTROL_1 */ "", 14422 /* CMIC_XGXS0_PLL_CONTROL_2 */ "", 14423 /* CMIC_XGXS0_PLL_CONTROL_3 */ "", 14424 /* CMIC_XGXS0_PLL_CONTROL_4 */ "", 14425 /* CMIC_XGXS0_PLL_STATUS */ "", 14426 /* CMIC_XGXS1_PLL_CONTROL_1 */ "", 14427 /* CMIC_XGXS1_PLL_CONTROL_2 */ "", 14428 /* CMIC_XGXS1_PLL_CONTROL_3 */ "", 14429 /* CMIC_XGXS1_PLL_CONTROL_4 */ "", 14430 /* CMIC_XGXS1_PLL_STATUS */ "", 14431 /* CMIC_XGXS2_PLL_CONTROL_1 */ "", 14432 /* CMIC_XGXS2_PLL_CONTROL_2 */ "", 14433 /* CMIC_XGXS2_PLL_CONTROL_3 */ "", 14434 /* CMIC_XGXS2_PLL_CONTROL_4 */ "", 14435 /* CMIC_XGXS2_PLL_STATUS */ "", 14436 /* CMIC_XGXS3_PLL_CONTROL_1 */ "", 14437 /* CMIC_XGXS3_PLL_CONTROL_2 */ "", 14438 /* CMIC_XGXS3_PLL_CONTROL_3 */ "", 14439 /* CMIC_XGXS3_PLL_CONTROL_4 */ "", 14440 /* CMIC_XGXS3_PLL_STATUS */ "", 14441 /* CMIC_XGXS_MDIO_CONFIG_0 */ "", 14442 /* CMIC_XGXS_MDIO_CONFIG_1 */ "", 14443 /* CMIC_XGXS_MDIO_CONFIG_2 */ "", 14444 /* CMIC_XGXS_MDIO_CONFIG_3 */ "", 14445 /* CMIC_XGXS_MDIO_CONFIG_4 */ "", 14446 /* CMIC_XGXS_MDIO_CONFIG_5 */ "", 14447 /* CMIC_XGXS_MDIO_CONFIG_6 */ "", 14448 /* CMIC_XGXS_MDIO_CONFIG_7 */ "", 14449 /* CMIC_XGXS_MDIO_CONFIG_8 */ "", 14450 /* CMIC_XGXS_MDIO_CONFIG_9 */ "", 14451 /* CMIC_XGXS_MDIO_CONFIG_10 */ "", 14452 /* CMIC_XGXS_MDIO_CONFIG_11 */ "", 14453 /* CMIC_XGXS_MDIO_CONFIG_12 */ "", 14454 /* CMIC_XGXS_MDIO_CONFIG_13 */ "", 14455 /* CMIC_XGXS_MDIO_CONFIG_14 */ "", 14456 /* CMIC_XGXS_MDIO_CONFIG_15 */ "", 14457 /* CMIC_XGXS_MDIO_CONFIG_16 */ "", 14458 /* CMIC_XGXS_MDIO_CONFIG_17 */ "", 14459 /* CMIC_XGXS_MDIO_CONFIG_18 */ "", 14460 /* CMIC_XGXS_MDIO_CONFIG_19 */ "", 14461 /* CMIC_XGXS_MDIO_CONFIG_20 */ "", 14462 /* CMIC_XGXS_MDIO_CONFIG_21 */ "", 14463 /* CMIC_XGXS_MDIO_CONFIG_22 */ "", 14464 /* CMIC_XGXS_MDIO_CONFIG_23 */ "", 14465 /* CMIC_XGXS_MDIO_CONFIG_24 */ "", 14466 /* CMIC_XGXS_PLL_CONTROL_1 */ "", 14467 /* CMIC_XGXS_PLL_CONTROL_2 */ "", 14468 /* CMIC_XGXS_PLL_CONTROL_3 */ "", 14469 /* CMIC_XGXS_PLL_CONTROL_4 */ "", 14470 /* CMIC_XGXS_PLL_STATUS */ "", 14471 /* CNG0COSDROPRATE */ "", 14472 /* CNG1COSDROPRATE */ "", 14473 /* CNGCOSCELLLIMIT0 */ "", 14474 /* CNGCOSCELLLIMIT1 */ "", 14475 /* CNGCOSPKTLIMIT0 */ "", 14476 /* CNGCOSPKTLIMIT1 */ "", 14477 /* CNGCOSPKTLIMIT0_QGROUP */ "", 14478 /* CNGCOSPKTLIMIT0_QLAYER */ "", 14479 /* CNGCOSPKTLIMIT1_QGROUP */ "", 14480 /* CNGCOSPKTLIMIT1_QLAYER */ "", 14481 /* CNGDROPCOUNT0 */ "", 14482 /* CNGDROPCOUNT1 */ "", 14483 /* CNGDYNCELLLIMIT0 */ "", 14484 /* CNGDYNCELLLIMIT1 */ "", 14485 /* CNGPORTPKTLIMIT0 */ "", 14486 /* CNGPORTPKTLIMIT1 */ "", 14487 /* CNGTOTALDYNCELLLIMIT0 */ "", 14488 /* CNGTOTALDYNCELLLIMIT1 */ "", 14489 /* CNG_MAP */ "", 14490 /* CNM_VERSION_CONTROL */ "", 14491 /* CNTX_AGING_LIMIT */ "", 14492 /* CNTX_LRU_EN */ "", 14493 /* COEFC_MSG0 */ "", 14494 /* COEFC_MSG1 */ "", 14495 /* COE_FLOW_CONTROL_CONFIG */ "", 14496 /* COE_VLAN_PAUSE_ID */ "", 14497 /* COE_VLAN_PAUSE_MACDA_LS */ "", 14498 /* COE_VLAN_PAUSE_MACDA_MS */ "", 14499 /* COE_VLAN_PAUSE_RX_DA_LS */ "", 14500 /* COE_VLAN_PAUSE_RX_DA_MS */ "", 14501 /* COE_VLAN_PAUSE_RX_ETHER_TYPE */ "", 14502 /* COE_VLAN_PAUSE_RX_OPCODE */ "", 14503 /* COLOR_AWARE */ "", 14504 /* COLOR_DROP_EN */ "", 14505 /* COLOR_DROP_EN_QGROUP */ "", 14506 /* COLOR_DROP_EN_QLAYER */ "", 14507 /* COMMAND_CONFIG */ "", 14508 /* CONFIG_ECC */ "", 14509 /* CONGESTION_STATE_BYTES */ "", 14510 /* COREID */ "", 14511 /* CORRECTED_ECC_ERROR */ "", 14512 /* CORRECTED_ECC_ERROR_MASK */ "", 14513 /* COSDP_REMAP_CONTROL */ "", 14514 /* COSLCCOUNT */ "", 14515 /* COSLCCOUNT_QGROUP */ "", 14516 /* COSMASK */ "", 14517 /* COSMASK_CPU */ "", 14518 /* COSMASK_CPU1 */ "", 14519 /* COSPKTCOUNT */ "", 14520 /* COSPKTCOUNT_QGROUP */ "", 14521 /* COSWEIGHTS */ "", 14522 /* COS_MAP_SEL */ "", 14523 /* COS_MODE */ "", 14524 /* COS_MODE_64 */ "COS_MODE", 14525 /* COS_MODE_64_SPLIT0 */ "", 14526 /* COS_MODE_64_SPLIT1 */ "", 14527 /* COS_MODE_SPLIT0 */ "COS_MODE_64_SPLIT0", 14528 /* COS_MODE_SPLIT1 */ "COS_MODE_64_SPLIT1", 14529 /* COS_MODE_X */ "", 14530 /* COS_MODE_X_64 */ "COS_MODE_X", 14531 /* COS_MODE_X_64_0 */ "COS_MODE_X_64_0", 14532 /* COS_MODE_X_64_1 */ "COS_MODE_X_64_1", 14533 /* COS_MODE_Y */ "", 14534 /* COS_MODE_Y_64 */ "COS_MODE_Y", 14535 /* COS_QUEUE */ "", 14536 /* COS_SEL */ "", 14537 /* COS_SEL_2 */ "", 14538 /* CPATHBISRDBGRDDATA */ "", 14539 /* CPB_PARITY_CONTROL */ "", 14540 /* CPB_PARITY_STATUS_INTR */ "", 14541 /* CPMPORT_CTRL_CONFIG */ "", 14542 /* CPMPORT_PLL0_CTRL_CONFIG */ "", 14543 /* CPMPORT_PLL1_CTRL_CONFIG */ "", 14544 /* CPMPORT_PMD_CTRL */ "", 14545 /* CPMPORT_PMD_PORT_STATUS */ "", 14546 /* CPMPORT_PMD_STATUS */ "", 14547 /* CPMPORT_SBUS_CONFIG */ "", 14548 /* CPMPORT_TOP_LANE_CTRL */ "", 14549 /* CPMPORT_TOP_RX_PHY_LANE_CTRL_0 */ "", 14550 /* CPMPORT_TOP_RX_PHY_LANE_CTRL_1 */ "", 14551 /* CPMPORT_TOP_RX_PHY_LANE_CTRL_2 */ "", 14552 /* CPMPORT_TOP_RX_PHY_LANE_CTRL_3 */ "", 14553 /* CPMPORT_TOP_TX_PHY_LANE_CTRL_0 */ "", 14554 /* CPMPORT_TOP_TX_PHY_LANE_CTRL_1 */ "", 14555 /* CPMPORT_TOP_TX_PHY_LANE_CTRL_2 */ "", 14556 /* CPMPORT_TOP_TX_PHY_LANE_CTRL_3 */ "", 14557 /* CPORT_CDC_RXFIFO_CELL_CNT */ "", 14558 /* CPORT_CDC_RXFIFO_ECC_STATUS */ "", 14559 /* CPORT_CDC_RXFIFO_OVRFLW */ "", 14560 /* CPORT_CDC_TXFIFO_CELL_CNT */ "", 14561 /* CPORT_CDC_TXFIFO_CELL_REQ_CNT */ "", 14562 /* CPORT_CDC_TXFIFO_ECC_STATUS */ "", 14563 /* CPORT_CDC_TXFIFO_OVRFLW */ "", 14564 /* CPORT_CONFIG */ "", 14565 /* CPORT_ECC_CONTROL */ "", 14566 /* CPORT_EEE_CLOCK_GATE */ "", 14567 /* CPORT_EEE_CORE0_CLOCK_GATE_COUNTER */ "", 14568 /* CPORT_EEE_COUNTER_MODE */ "", 14569 /* CPORT_EEE_DURATION_TIMER_PULSE */ "", 14570 /* CPORT_ENABLE_REG */ "", 14571 /* CPORT_FAULT_LINK_STATUS */ "", 14572 /* CPORT_FORCE_DOUBLE_BIT_ERROR */ "", 14573 /* CPORT_FORCE_SINGLE_BIT_ERROR */ "", 14574 /* CPORT_INTR_ENABLE */ "", 14575 /* CPORT_INTR_STATUS */ "", 14576 /* CPORT_LAG_FAILOVER_CONFIG */ "", 14577 /* CPORT_LED_CHAIN_CONFIG */ "", 14578 /* CPORT_LINKSTATUS_DOWN */ "", 14579 /* CPORT_LINKSTATUS_DOWN_CLEAR */ "", 14580 /* CPORT_MAC_CONTROL */ "", 14581 /* CPORT_MAC_MODE */ "", 14582 /* CPORT_MODE_REG */ "", 14583 /* CPORT_POWER_SAVE */ "", 14584 /* CPORT_SGNDET_EARLYCRS */ "", 14585 /* CPORT_SOFT_RESET */ "", 14586 /* CPORT_SPARE0_REG */ "", 14587 /* CPORT_SW_FLOW_CONTROL */ "", 14588 /* CPORT_TXFIFO0_ECC_STATUS */ "", 14589 /* CPORT_TXFIFO_CELL_CNT */ "", 14590 /* CPORT_TXFIFO_CELL_REQ_CNT */ "", 14591 /* CPORT_TXFIFO_OVRFLW */ "", 14592 /* CPORT_TXFIFO_PKT_DROP_CTL */ "", 14593 /* CPORT_XGXS0_LN0_STATUS0_REG */ "", 14594 /* CPORT_XHOL_D0 */ "", 14595 /* CPORT_XHOL_D1 */ "", 14596 /* CPORT_XHOL_D2 */ "", 14597 /* CPORT_XHOL_D3 */ "", 14598 /* CPORT_XHOL_MH0 */ "", 14599 /* CPORT_XHOL_MH1 */ "", 14600 /* CPORT_XHOL_MH2 */ "", 14601 /* CPORT_XHOL_MH3 */ "", 14602 /* CPORT_XHOL_RX_MH_DATA0 */ "", 14603 /* CPORT_XHOL_RX_MH_DATA1 */ "", 14604 /* CPORT_XHOL_RX_MH_DATA2 */ "", 14605 /* CPORT_XHOL_RX_MH_DATA3 */ "", 14606 /* CPORT_XHOL_RX_MH_MASK0 */ "", 14607 /* CPORT_XHOL_RX_MH_MASK1 */ "", 14608 /* CPORT_XHOL_RX_MH_MASK2 */ "", 14609 /* CPORT_XHOL_RX_MH_MASK3 */ "", 14610 /* CPORT_XHOL_RX_PKT_DATA0 */ "", 14611 /* CPORT_XHOL_RX_PKT_DATA1 */ "", 14612 /* CPORT_XHOL_RX_PKT_DATA2 */ "", 14613 /* CPORT_XHOL_RX_PKT_DATA3 */ "", 14614 /* CPORT_XHOL_RX_PKT_MASK0 */ "", 14615 /* CPORT_XHOL_RX_PKT_MASK1 */ "", 14616 /* CPORT_XHOL_RX_PKT_MASK2 */ "", 14617 /* CPORT_XHOL_RX_PKT_MASK3 */ "", 14618 /* CPORT_XMODID_DUAL_EN */ "", 14619 /* CPORT_XPAUSE_D0 */ "", 14620 /* CPORT_XPAUSE_D1 */ "", 14621 /* CPORT_XPAUSE_D2 */ "", 14622 /* CPORT_XPAUSE_D3 */ "", 14623 /* CPORT_XPAUSE_MH0 */ "", 14624 /* CPORT_XPAUSE_MH1 */ "", 14625 /* CPORT_XPAUSE_MH2 */ "", 14626 /* CPORT_XPAUSE_MH3 */ "", 14627 /* CPORT_XPAUSE_RX_DA_LS */ "", 14628 /* CPORT_XPAUSE_RX_DA_MS */ "", 14629 /* CPORT_XPAUSE_RX_LENGTH_TYPE */ "", 14630 /* CPORT_XPAUSE_RX_OPCODE */ "", 14631 /* CPORT_XPAUSE_TX_PKT_XOFF_VAL */ "", 14632 /* CPORT_XPAUSE_WATCHDOG_INIT_VAL */ "", 14633 /* CPORT_XPAUSE_WATCHDOG_THRESH */ "", 14634 /* CPORT_XTPSE */ "", 14635 /* CPQLINKMEMDEBUG */ "", 14636 /* CPQ_COS_EMPTY_REG */ "", 14637 /* CPRI_CIP_CLK_CTRL */ "", 14638 /* CPRI_CLK_CTRL */ "", 14639 /* CPRI_DECAP_AGNOSTIC_MODE_CTRL */ "", 14640 /* CPRI_DECAP_AGNOSTIC_MODE_INTR_ENABLE */ "", 14641 /* CPRI_DECAP_AGNOSTIC_MODE_INTR_STATUS */ "", 14642 /* CPRI_DECAP_CLS_QUEUE_ECC_INTR_STATUS */ "", 14643 /* CPRI_DECAP_CLS_QUEUE_INTR_ENABLE_CONTROL */ "", 14644 /* CPRI_DECAP_COMP_NEG_SAT_CTRL */ "", 14645 /* CPRI_DECAP_COMP_TAB_I_0_ECC_INTR_STATUS */ "", 14646 /* CPRI_DECAP_COMP_TAB_I_0_INTR_ENABLE_CONTROL */ "", 14647 /* CPRI_DECAP_COMP_TAB_I_1_ECC_INTR_STATUS */ "", 14648 /* CPRI_DECAP_COMP_TAB_I_1_INTR_ENABLE_CONTROL */ "", 14649 /* CPRI_DECAP_COMP_TAB_Q_0_ECC_INTR_STATUS */ "", 14650 /* CPRI_DECAP_COMP_TAB_Q_0_INTR_ENABLE_CONTROL */ "", 14651 /* CPRI_DECAP_COMP_TAB_Q_1_ECC_INTR_STATUS */ "", 14652 /* CPRI_DECAP_COMP_TAB_Q_1_INTR_ENABLE_CONTROL */ "", 14653 /* CPRI_DECAP_CORRUPT_ECC_CTRL */ "", 14654 /* CPRI_DECAP_CTRL */ "", 14655 /* CPRI_DECAP_DATA_MEM_ECC_INTR_STATUS */ "", 14656 /* CPRI_DECAP_DATA_MEM_INTR_ENABLE_CONTROL */ "", 14657 /* CPRI_DECAP_DATA_QUEUE_BUFFSIZE_INTR_ENABLE */ "", 14658 /* CPRI_DECAP_DATA_QUEUE_BUFFSIZE_INTR_STATUS */ "", 14659 /* CPRI_DECAP_DATA_QUEUE_OVERFLOW_INTR_ENABLE */ "", 14660 /* CPRI_DECAP_DATA_QUEUE_OVERFLOW_INTR_STATUS */ "", 14661 /* CPRI_DECAP_DATA_QUEUE_UNDERFLOW_INTR_ENABLE */ "", 14662 /* CPRI_DECAP_DATA_QUEUE_UNDERFLOW_INTR_STATUS */ "", 14663 /* CPRI_DECAP_DCOMP_NEG_SAT_CTRL */ "", 14664 /* CPRI_DECAP_DISABLE_ECC_CTRL */ "", 14665 /* CPRI_DECAP_DROP_CNT */ "", 14666 /* CPRI_DECAP_DVT_CTRL */ "", 14667 /* CPRI_DECAP_EP_DROP_CNT */ "", 14668 /* CPRI_DECAP_EXD_HDR_CTRL */ "", 14669 /* CPRI_DECAP_FLOWID_QUEUE_ECC_INTR_STATUS */ "", 14670 /* CPRI_DECAP_FLOWID_QUEUE_INTR_ENABLE_CONTROL */ "", 14671 /* CPRI_DECAP_HDR_FLD_MAPPING */ "", 14672 /* CPRI_DECAP_HDR_FLD_MASKING */ "", 14673 /* CPRI_DECAP_LATCH_1BIT_ERR_ADDR_CTRL */ "", 14674 /* CPRI_DECAP_LEN_FLD_ADJ */ "", 14675 /* CPRI_DECAP_MEMBUF_0_ECC_INTR_STATUS */ "", 14676 /* CPRI_DECAP_MEMBUF_0_INTR_ENABLE_CONTROL */ "", 14677 /* CPRI_DECAP_MEMBUF_1_ECC_INTR_STATUS */ "", 14678 /* CPRI_DECAP_MEMBUF_1_INTR_ENABLE_CONTROL */ "", 14679 /* CPRI_DECAP_ORDERING_INFO_ECC_INTR_STATUS */ "", 14680 /* CPRI_DECAP_ORDERING_INFO_INTR_ENABLE_CONTROL */ "", 14681 /* CPRI_DECAP_PKT_CNT_ECC_INTR_STATUS */ "", 14682 /* CPRI_DECAP_PKT_CNT_INTR_ENABLE_CONTROL */ "", 14683 /* CPRI_DECAP_PRES_TIME_CTRL */ "", 14684 /* CPRI_DECAP_Q_CFG_ECC_INTR_STATUS */ "", 14685 /* CPRI_DECAP_Q_CFG_INTR_ENABLE_CONTROL */ "", 14686 /* CPRI_DECAP_SEQ_OFF_ECC_INTR_STATUS */ "", 14687 /* CPRI_DECAP_SEQ_OFF_INTR_ENABLE_CONTROL */ "", 14688 /* CPRI_DECAP_STATE_STATUS */ "", 14689 /* CPRI_ENCAP_CORRUPT_ECC_CTRL */ "", 14690 /* CPRI_ENCAP_CRC_CTRL */ "", 14691 /* CPRI_ENCAP_CTRL_QUEUE_INTR_ENABLE */ "", 14692 /* CPRI_ENCAP_CTRL_QUEUE_INTR_STATUS */ "", 14693 /* CPRI_ENCAP_DATA_MEM_ECC_INTR_STATUS */ "", 14694 /* CPRI_ENCAP_DATA_MEM_INTR_ENABLE_CONTROL */ "", 14695 /* CPRI_ENCAP_DATA_QUEUE_INTR_ENABLE */ "", 14696 /* CPRI_ENCAP_DATA_QUEUE_INTR_STATUS */ "", 14697 /* CPRI_ENCAP_DISABLE_ECC_CTRL */ "", 14698 /* CPRI_ENCAP_ETH_HDR_ECC_INTR_STATUS */ "", 14699 /* CPRI_ENCAP_ETH_HDR_INTR_ENABLE_CONTROL */ "", 14700 /* CPRI_ENCAP_EXD_HDR_CTRL */ "", 14701 /* CPRI_ENCAP_GSM_TS_ERR_QUEUE_INTR_ENABLE */ "", 14702 /* CPRI_ENCAP_GSM_TS_ERR_QUEUE_INTR_STATUS */ "", 14703 /* CPRI_ENCAP_HDR_FLD_MAPPING */ "", 14704 /* CPRI_ENCAP_LATCH_1BIT_ERR_ADDR_CTRL */ "", 14705 /* CPRI_ENCAP_LEN_FLD_ADJ */ "", 14706 /* CPRI_ENCAP_MISC_FIFO_INTR_STATUS */ "", 14707 /* CPRI_ENCAP_MISC_FIFO_QUEUE_INTR_ENABLE */ "", 14708 /* CPRI_ENCAP_ORDERING_INFO_ECC_INTR_STATUS */ "", 14709 /* CPRI_ENCAP_ORDERING_INFO_INTR_ENABLE_CONTROL */ "", 14710 /* CPRI_ENCAP_PKT_CNT_ECC_INTR_STATUS */ "", 14711 /* CPRI_ENCAP_PKT_CNT_INTR_ENABLE_CONTROL */ "", 14712 /* CPRI_ENCAP_Q_CFG_ECC_INTR_STATUS */ "", 14713 /* CPRI_ENCAP_Q_CFG_INTR_ENABLE_CONTROL */ "", 14714 /* CPRI_ENCAP_RSVD_CONTROL */ "", 14715 /* CPRI_ENCAP_RXFRM_0_ECC_INTR_STATUS */ "", 14716 /* CPRI_ENCAP_RXFRM_0_INTR_ENABLE_CONTROL */ "", 14717 /* CPRI_ENCAP_RXFRM_1_ECC_INTR_STATUS */ "", 14718 /* CPRI_ENCAP_RXFRM_1_INTR_ENABLE_CONTROL */ "", 14719 /* CPRI_ENCAP_SEQ_NUM_CTL_ECC_INTR_STATUS */ "", 14720 /* CPRI_ENCAP_SEQ_NUM_CTL_INTR_ENABLE_CONTROL */ "", 14721 /* CPRI_ENCAP_SEQ_NUM_DATA_ECC_INTR_STATUS */ "", 14722 /* CPRI_ENCAP_SEQ_NUM_DATA_INTR_ENABLE_CONTROL */ "", 14723 /* CPRI_ENCAP_STATE_STATUS */ "", 14724 /* CPRI_ENCAP_TDM_CTRL */ "", 14725 /* CPRI_ENCAP_VLAN_CTRL */ "", 14726 /* CPRI_ENCAP_VLAN_QINQ_CTRL */ "", 14727 /* CPRI_ENCAP_WQ_0_ECC_INTR_STATUS */ "", 14728 /* CPRI_ENCAP_WQ_0_INTR_ENABLE_CONTROL */ "", 14729 /* CPRI_ENCAP_WQ_1_ECC_INTR_STATUS */ "", 14730 /* CPRI_ENCAP_WQ_1_INTR_ENABLE_CONTROL */ "", 14731 /* CPRI_ENCAP_WQ_2_ECC_INTR_STATUS */ "", 14732 /* CPRI_ENCAP_WQ_2_INTR_ENABLE_CONTROL */ "", 14733 /* CPRI_ENCAP_WQ_3_ECC_INTR_STATUS */ "", 14734 /* CPRI_ENCAP_WQ_3_INTR_ENABLE_CONTROL */ "", 14735 /* CPRI_ENCAP_WQ_CTRL */ "", 14736 /* CPRI_ENCAP_WQ_FIFO_CNT_STS */ "", 14737 /* CPRI_FAST_CLK_CTRL */ "", 14738 /* CPRI_FAST_ETH_CNTR_STATUS */ "", 14739 /* CPRI_FAST_ETH_ERR_CNTR_STATUS */ "", 14740 /* CPRI_HDLC_CNTR_STATUS */ "", 14741 /* CPRI_HDLC_ERR_CNTR_STATUS */ "", 14742 /* CPRI_ING_PRES_TM_CTRL */ "", 14743 /* CPRI_ING_PRES_TM_OFFSET */ "", 14744 /* CPRI_ING_PRES_TM_STATUS */ "", 14745 /* CPRI_ING_TS_APPROX_INC */ "", 14746 /* CPRI_INTR_ENABLE */ "", 14747 /* CPRI_INTR_STATUS */ "", 14748 /* CPRI_MEM_TEST_MODE_CTRL */ "", 14749 /* CPRI_PMD_RX_CTRL */ "", 14750 /* CPRI_PMD_RX_RST_CTRL */ "", 14751 /* CPRI_PMD_TX_CTRL */ "", 14752 /* CPRI_PMD_TX_RST_CTRL */ "", 14753 /* CPRI_RF_TS_CTRL */ "", 14754 /* CPRI_RST_CTRL */ "", 14755 /* CPRI_RXFRM_BFRM_CTRL */ "", 14756 /* CPRI_RXFRM_BFRM_MAP_TAB0_INTR_ENABLE_CONTROL */ "", 14757 /* CPRI_RXFRM_BFRM_MAP_TAB0_INTR_STATUS */ "", 14758 /* CPRI_RXFRM_BFRM_MAP_TAB1_INTR_ENABLE_CONTROL */ "", 14759 /* CPRI_RXFRM_BFRM_MAP_TAB1_INTR_STATUS */ "", 14760 /* CPRI_RXFRM_CFLW_BUF_TAB_INTR_ENABLE_CONTROL */ "", 14761 /* CPRI_RXFRM_CFLW_BUF_TAB_INTR_STATUS */ "", 14762 /* CPRI_RXFRM_CFLW_PGC_TAB_INTR_ENABLE_CONTROL */ "", 14763 /* CPRI_RXFRM_CFLW_PGC_TAB_INTR_STATUS */ "", 14764 /* CPRI_RXFRM_CPRSR_CTRL */ "", 14765 /* CPRI_RXFRM_CPRSR_INTR_ENABLE_CONTROL */ "", 14766 /* CPRI_RXFRM_CPRSR_MAP_TAB_INTR_ENABLE_CONTROL */ "", 14767 /* CPRI_RXFRM_CPRSR_MAP_TAB_INTR_STATUS */ "", 14768 /* CPRI_RXFRM_CPRSR_STATE_MEM_INTR_ENABLE_CONTROL */ "", 14769 /* CPRI_RXFRM_CPRSR_STATE_MEM_INTR_STATUS */ "", 14770 /* CPRI_RXFRM_CPRSR_STATUS */ "", 14771 /* CPRI_RXFRM_ENABLE_AXC_SC */ "", 14772 /* CPRI_RXFRM_IQ_PK_BUFF_AXC_PLD_MEM_INTR_ENABLE_CONTROL */ "", 14773 /* CPRI_RXFRM_IQ_PK_BUFF_AXC_PLD_MEM_INTR_STATUS */ "", 14774 /* CPRI_RXFRM_IQ_PK_BUFF_AXC_STATE_MEM_INTR_ENABLE_CONTROL */ "", 14775 /* CPRI_RXFRM_IQ_PK_BUFF_AXC_STATE_MEM_INTR_STATUS */ "", 14776 /* CPRI_RXFRM_IQ_PK_BUFF_MEM_INTR_ENABLE_CONTROL */ "", 14777 /* CPRI_RXFRM_IQ_PK_BUFF_MEM_INTR_STATUS */ "", 14778 /* CPRI_RXFRM_RXPCS_CORRUPT_ECC_CTRL */ "", 14779 /* CPRI_RXFRM_RXPCS_DISABLE_ECC_CTRL */ "", 14780 /* CPRI_RXFRM_RXPCS_LATCH_1BIT_ERR_ADDR_CTRL */ "", 14781 /* CPRI_RXFRM_SC */ "", 14782 /* CPRI_RXFRM_STATUS */ "", 14783 /* CPRI_RXFRM_VSD_CTRL */ "", 14784 /* CPRI_RXFRM_VSD_MASK0_COPY0_CTRL */ "", 14785 /* CPRI_RXFRM_VSD_MASK0_COPY1_CTRL */ "", 14786 /* CPRI_RXFRM_VSD_MASK1_COPY0_CTRL */ "", 14787 /* CPRI_RXFRM_VSD_MASK1_COPY1_CTRL */ "", 14788 /* CPRI_RXFRM_VSD_RSRV_MASK0_CTRL */ "", 14789 /* CPRI_RXFRM_VSD_RSRV_MASK1_CTRL */ "", 14790 /* CPRI_RXPCS_0_CNTR_STATUS */ "", 14791 /* CPRI_RXPCS_1_CNTR_STATUS */ "", 14792 /* CPRI_RXPCS_2_CNTR_STATUS */ "", 14793 /* CPRI_RXPCS_CL91_TS_CTRL */ "", 14794 /* CPRI_RXPCS_CTRL */ "", 14795 /* CPRI_RXPCS_EXTRACT_INTR_ENABLE_CONTROL */ "", 14796 /* CPRI_RXPCS_EXTRACT_INTR_STATUS */ "", 14797 /* CPRI_RXPCS_FEC_0_CTRL */ "", 14798 /* CPRI_RXPCS_FEC_0_STATUS */ "", 14799 /* CPRI_RXPCS_FEC_1_CTRL */ "", 14800 /* CPRI_RXPCS_FEC_1_STATUS */ "", 14801 /* CPRI_RXPCS_FEC_2_CTRL */ "", 14802 /* CPRI_RXPCS_FEC_2_STATUS */ "", 14803 /* CPRI_RXPCS_FEC_3_CTRL */ "", 14804 /* CPRI_RXPCS_FEC_3_STATUS */ "", 14805 /* CPRI_RXPCS_FEC_4_CTRL */ "", 14806 /* CPRI_RXPCS_FEC_4_STATUS */ "", 14807 /* CPRI_RXPCS_FEC_5_STATUS */ "", 14808 /* CPRI_RXPCS_FEC_6_STATUS */ "", 14809 /* CPRI_RXPCS_FEC_7_STATUS */ "", 14810 /* CPRI_RXPCS_FEC_8_STATUS */ "", 14811 /* CPRI_RXPCS_FEC_CL91_CTRL */ "", 14812 /* CPRI_RXPCS_FEC_DECODER_RAM1_INTR_ENABLE_CONTROL */ "", 14813 /* CPRI_RXPCS_FEC_DECODER_RAM1_INTR_STATUS */ "", 14814 /* CPRI_RXPCS_FEC_DECODER_RAM2_INTR_ENABLE_CONTROL */ "", 14815 /* CPRI_RXPCS_FEC_DECODER_RAM2_INTR_STATUS */ "", 14816 /* CPRI_RXPCS_FEC_INTR_ENABLE_CONTROL */ "", 14817 /* CPRI_RXPCS_FEC_INTR_STATUS */ "", 14818 /* CPRI_RXPCS_FSM_LATCHED_STATUS */ "", 14819 /* CPRI_RXPCS_FSM_LIVE_STATUS */ "", 14820 /* CPRI_RXPCS_INTR_ENABLE */ "", 14821 /* CPRI_RXPCS_INTR_STATUS */ "", 14822 /* CPRI_RXPCS_SC */ "", 14823 /* CPRI_RXPCS_STATUS */ "", 14824 /* CPRI_RX_1588_CAP_INTR_ENABLE_CONTROL */ "", 14825 /* CPRI_RX_1588_CAP_INTR_STATUS */ "", 14826 /* CPRI_RX_1588_CTRL */ "", 14827 /* CPRI_RX_1588_FIFO_INTR_ENABLE_CONTROL */ "", 14828 /* CPRI_RX_1588_FIFO_INTR_STATUS */ "", 14829 /* CPRI_RX_CTRL */ "", 14830 /* CPRI_RX_FAST_ETH_CTRL */ "", 14831 /* CPRI_RX_FAST_ETH_FSM_STATUS */ "", 14832 /* CPRI_RX_FUNC_INTR_ENABLE */ "", 14833 /* CPRI_RX_FUNC_INTR_STATUS */ "", 14834 /* CPRI_RX_GCW_0_STATUS */ "", 14835 /* CPRI_RX_GCW_1_STATUS */ "", 14836 /* CPRI_RX_GCW_2_STATUS */ "", 14837 /* CPRI_RX_GCW_3_STATUS */ "", 14838 /* CPRI_RX_GCW_ERR_CNTR_STATUS */ "", 14839 /* CPRI_RX_GCW_INTR_ENABLE_CONTROL */ "", 14840 /* CPRI_RX_GCW_INTR_STATUS */ "", 14841 /* CPRI_RX_HDLC_CTRL */ "", 14842 /* CPRI_RX_HDLC_FSM_STATUS */ "", 14843 /* CPRI_RX_INTR_ENABLE */ "", 14844 /* CPRI_RX_INTR_STATUS */ "", 14845 /* CPRI_RX_OP_ERR_INTR_ENABLE */ "", 14846 /* CPRI_RX_OP_ERR_INTR_STATUS */ "", 14847 /* CPRI_RX_STATS_CNTR_0_STATUS */ "", 14848 /* CPRI_RX_STATS_CNTR_1_STATUS */ "", 14849 /* CPRI_RX_STATS_CNTR_2_STATUS */ "", 14850 /* CPRI_RX_STATS_CNTR_3_STATUS */ "", 14851 /* CPRI_RX_STATS_CNTR_4_STATUS */ "", 14852 /* CPRI_RX_STATS_CNTR_5_STATUS */ "", 14853 /* CPRI_RX_STATS_CNTR_6_STATUS */ "", 14854 /* CPRI_RX_TS_ADJ_CTRL */ "", 14855 /* CPRI_TXFRM_BFA_CTRL */ "", 14856 /* CPRI_TXFRM_BFA_MAP_TAB0_INTR_ENABLE_CONTROL */ "", 14857 /* CPRI_TXFRM_BFA_MAP_TAB0_INTR_STATUS */ "", 14858 /* CPRI_TXFRM_BFA_MAP_TAB1_INTR_ENABLE_CONTROL */ "", 14859 /* CPRI_TXFRM_BFA_MAP_TAB1_INTR_STATUS */ "", 14860 /* CPRI_TXFRM_CA_MAP_TAB_INTR_ENABLE_CONTROL */ "", 14861 /* CPRI_TXFRM_CA_MAP_TAB_INTR_STATUS */ "", 14862 /* CPRI_TXFRM_CA_PAY_TAB_INTR_ENABLE_CONTROL */ "", 14863 /* CPRI_TXFRM_CA_PAY_TAB_INTR_STATUS */ "", 14864 /* CPRI_TXFRM_CA_STATE_TAB_INTR_ENABLE_CONTROL */ "", 14865 /* CPRI_TXFRM_CA_STATE_TAB_INTR_STATUS */ "", 14866 /* CPRI_TXFRM_CWA_FLOW_BUFFER0_INTR_ENABLE_CONTROL */ "", 14867 /* CPRI_TXFRM_CWA_FLOW_BUFFER0_INTR_STATUS */ "", 14868 /* CPRI_TXFRM_CWA_FLOW_BUFFER1_INTR_ENABLE_CONTROL */ "", 14869 /* CPRI_TXFRM_CWA_FLOW_BUFFER1_INTR_STATUS */ "", 14870 /* CPRI_TXFRM_CWA_FLOW_CONFIG_INTR_ENABLE_CONTROL */ "", 14871 /* CPRI_TXFRM_CWA_FLOW_CONFIG_INTR_STATUS */ "", 14872 /* CPRI_TXFRM_CWA_GCW */ "", 14873 /* CPRI_TXFRM_CWA_GCW_INTR_ENABLE_CONTROL */ "", 14874 /* CPRI_TXFRM_CWA_GCW_INTR_STATUS */ "", 14875 /* CPRI_TXFRM_CWA_GENERAL */ "", 14876 /* CPRI_TXFRM_CWA_L1 */ "", 14877 /* CPRI_TXFRM_CWA_VSD_CTRL_CFG */ "", 14878 /* CPRI_TXFRM_CWA_VSD_CTRL_CTRL */ "", 14879 /* CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL0 */ "", 14880 /* CPRI_TXFRM_CWA_VSD_CTRL_MASK0_CTRL1 */ "", 14881 /* CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL0 */ "", 14882 /* CPRI_TXFRM_CWA_VSD_CTRL_MASK1_CTRL1 */ "", 14883 /* CPRI_TXFRM_CWA_VSD_CTRL_PACKET_SIZE_ERR_STATUS */ "", 14884 /* CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK0_CTRL2 */ "", 14885 /* CPRI_TXFRM_CWA_VSD_CTRL_RSRV_MASK1_CTRL2 */ "", 14886 /* CPRI_TXFRM_CWA_VSD_RAW_CTRL */ "", 14887 /* CPRI_TXFRM_CWA_VSD_RAW_PACKET_SIZE_ERR_STATUS */ "", 14888 /* CPRI_TXFRM_DEBUG_CTRL */ "", 14889 /* CPRI_TXFRM_GENERAL_CTRL */ "", 14890 /* CPRI_TXFRM_INTR_ENABLE_CONTROL */ "", 14891 /* CPRI_TXFRM_INTR_STATUS */ "", 14892 /* CPRI_TXFRM_IQU_BUFFER_INTR_ENABLE_CONTROL */ "", 14893 /* CPRI_TXFRM_IQU_BUFFER_INTR_STATUS */ "", 14894 /* CPRI_TXFRM_IQU_STATE_INTR_ENABLE_CONTROL */ "", 14895 /* CPRI_TXFRM_IQU_STATE_INTR_STATUS */ "", 14896 /* CPRI_TXFRM_STATUS */ "", 14897 /* CPRI_TXFRM_STOP_STATE */ "", 14898 /* CPRI_TXFRM_TGEN_CFG1 */ "", 14899 /* CPRI_TXFRM_TGEN_CFG2 */ "", 14900 /* CPRI_TXFRM_TGEN_CFG3 */ "", 14901 /* CPRI_TXFRM_TGEN_CFG4 */ "", 14902 /* CPRI_TXFRM_TGEN_STATUS */ "", 14903 /* CPRI_TXFRM_TXPCS_CORRUPT_ECC_CTRL */ "", 14904 /* CPRI_TXFRM_TXPCS_DISABLE_ECC_CTRL */ "", 14905 /* CPRI_TXFRM_TXPCS_LATCH_1BIT_ERR_ADDR_CTRL */ "", 14906 /* CPRI_TXPCS_CL91_TS_CTRL */ "", 14907 /* CPRI_TXPCS_CTRL */ "", 14908 /* CPRI_TXPCS_FEC_CL91_CTRL */ "", 14909 /* CPRI_TXPCS_INTR_ENABLE_CONTROL */ "", 14910 /* CPRI_TXPCS_INTR_STATUS */ "", 14911 /* CPRI_TXPCS_STATUS */ "", 14912 /* CPRI_TXPCS_STOP_STATE */ "", 14913 /* CPRI_TXPCS_TX_FIFO_INTR_ENABLE_CONTROL */ "", 14914 /* CPRI_TXPCS_TX_FIFO_INTR_STATUS */ "", 14915 /* CPRI_TXPI_CSR_OVER_EN */ "", 14916 /* CPRI_TXPI_CSR_OVER_VAL */ "", 14917 /* CPRI_TXPI_DATA_OUT_STS */ "", 14918 /* CPRI_TX_1588_CAP_INTR_ENABLE_CONTROL */ "", 14919 /* CPRI_TX_1588_CAP_INTR_STATUS */ "", 14920 /* CPRI_TX_1588_CTRL */ "", 14921 /* CPRI_TX_1588_FIFO_INTR_ENABLE_CONTROL */ "", 14922 /* CPRI_TX_1588_FIFO_INTR_STATUS */ "", 14923 /* CPRI_TX_CTRL */ "", 14924 /* CPRI_TX_FAST_ETH_CTRL */ "", 14925 /* CPRI_TX_FUNC_INTR_ENABLE */ "", 14926 /* CPRI_TX_FUNC_INTR_STATUS */ "", 14927 /* CPRI_TX_HDLC_CTRL */ "", 14928 /* CPRI_TX_INTR_ENABLE */ "", 14929 /* CPRI_TX_INTR_STATUS */ "", 14930 /* CPRI_TX_MEM_TEST_MODE_CTRL */ "", 14931 /* CPRI_TX_OP_ERR_INTR_ENABLE */ "", 14932 /* CPRI_TX_OP_ERR_INTR_STATUS */ "", 14933 /* CPRI_TX_TS_ADJ_CTRL */ "", 14934 /* CPRI_VSDRAW_ERR_CNTR_STATUS */ "", 14935 /* CPRI_VSD_CTRL_ERR_CNTR_STATUS */ "", 14936 /* CPUMAXBUCKET */ "", 14937 /* CPUMAXBUCKETCONFIG_64 */ "CPUMAXBUCKETCONFIG", 14938 /* CPUPKTECC */ "", 14939 /* CPUPKTMAXBUCKET */ "", 14940 /* CPUPKTMAXBUCKETCONFIG */ "", 14941 /* CPUPKTPORTMAXBUCKET */ "", 14942 /* CPUPKTPORTMAXBUCKETCONFIG */ "", 14943 /* CPUPORTMAXBUCKET */ "", 14944 /* CPUPORTMAXBUCKETCONFIG_64 */ "CPUPORTMAXBUCKETCONFIG", 14945 /* CPUSLOTMINTIMER */ "", 14946 /* CPU_BW */ "", 14947 /* CPU_CONTROL_0 */ "", 14948 /* CPU_CONTROL_1 */ "", 14949 /* CPU_CONTROL_2 */ "", 14950 /* CPU_CONTROL_3 */ "", 14951 /* CPU_CONTROL_4 */ "", 14952 /* CPU_CONTROL_M */ "", 14953 /* CPU_COS14_MASK */ "", 14954 /* CPU_COS15_MASK */ "", 14955 /* CPU_COS1_MASK */ "", 14956 /* CPU_COS2_MASK */ "", 14957 /* CPU_COS3_MASK */ "", 14958 /* CPU_COS4_MASK */ "", 14959 /* CPU_COS5_MASK */ "", 14960 /* CPU_COS6_MASK */ "", 14961 /* CPU_COS7_MASK */ "", 14962 /* CPU_COS_CAM_BIST_CONFIG */ "", 14963 /* CPU_COS_CAM_BIST_CONFIG_64 */ "", 14964 /* CPU_COS_CAM_BIST_CONFIG_64_PIPE0 */ "", 14965 /* CPU_COS_CAM_BIST_CONFIG_64_PIPE1 */ "", 14966 /* CPU_COS_CAM_BIST_CONFIG_64_PIPE2 */ "", 14967 /* CPU_COS_CAM_BIST_CONFIG_64_PIPE3 */ "", 14968 /* CPU_COS_CAM_BIST_CONFIG_PIPE0 */ "", 14969 /* CPU_COS_CAM_BIST_CONFIG_PIPE1 */ "", 14970 /* CPU_COS_CAM_BIST_CONFIG_PIPE2 */ "", 14971 /* CPU_COS_CAM_BIST_CONFIG_PIPE3 */ "", 14972 /* CPU_COS_CAM_BIST_DBG_DATA */ "", 14973 /* CPU_COS_CAM_BIST_DBG_DATA_PIPE0 */ "", 14974 /* CPU_COS_CAM_BIST_DBG_DATA_PIPE1 */ "", 14975 /* CPU_COS_CAM_BIST_DBG_DATA_PIPE2 */ "", 14976 /* CPU_COS_CAM_BIST_DBG_DATA_PIPE3 */ "", 14977 /* CPU_COS_CAM_BIST_STATUS */ "", 14978 /* CPU_COS_CAM_BIST_STATUS_PIPE0 */ "", 14979 /* CPU_COS_CAM_BIST_STATUS_PIPE1 */ "", 14980 /* CPU_COS_CAM_BIST_STATUS_PIPE2 */ "", 14981 /* CPU_COS_CAM_BIST_STATUS_PIPE3 */ "", 14982 /* CPU_COS_CAM_DBGCTRL */ "CPU_COS_CAM_CONTROL", 14983 /* CPU_COS_CAM_DBGCTRL_PIPE0 */ "CPU_COS_CAM_CONTROL_PIPE0", 14984 /* CPU_COS_CAM_DBGCTRL_PIPE1 */ "CPU_COS_CAM_CONTROL_PIPE1", 14985 /* CPU_COS_CAM_DBGCTRL_PIPE2 */ "CPU_COS_CAM_CONTROL_PIPE2", 14986 /* CPU_COS_CAM_DBGCTRL_PIPE3 */ "CPU_COS_CAM_CONTROL_PIPE3", 14987 /* CPU_COS_CAM_SERCTRL */ "CPU_COS_CAM_SER_CONTROL", 14988 /* CPU_COS_MAP_CAM_BIST_CONFIG_64 */ "", 14989 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE0 */ "", 14990 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE1 */ "", 14991 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE2 */ "", 14992 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE3 */ "", 14993 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE4 */ "", 14994 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE5 */ "", 14995 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE6 */ "", 14996 /* CPU_COS_MAP_CAM_BIST_CONFIG_64_PIPE7 */ "", 14997 /* CPU_COS_MAP_CAM_BIST_STATUS */ "", 14998 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE0 */ "", 14999 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE1 */ "", 15000 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE2 */ "", 15001 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE3 */ "", 15002 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE4 */ "", 15003 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE5 */ "", 15004 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE6 */ "", 15005 /* CPU_COS_MAP_CAM_BIST_STATUS_PIPE7 */ "", 15006 /* CPU_COS_MAP_CAM_CONTROL */ "", 15007 /* CPU_COS_MAP_CAM_CONTROL_PIPE0 */ "", 15008 /* CPU_COS_MAP_CAM_CONTROL_PIPE1 */ "", 15009 /* CPU_COS_MAP_CAM_CONTROL_PIPE2 */ "", 15010 /* CPU_COS_MAP_CAM_CONTROL_PIPE3 */ "", 15011 /* CPU_COS_MAP_CAM_CONTROL_PIPE4 */ "", 15012 /* CPU_COS_MAP_CAM_CONTROL_PIPE5 */ "", 15013 /* CPU_COS_MAP_CAM_CONTROL_PIPE6 */ "", 15014 /* CPU_COS_MAP_CAM_CONTROL_PIPE7 */ "", 15015 /* CPU_COS_SEL */ "", 15016 /* CPU_COS_SEL_2 */ "", 15017 /* CPU_HI_RQE_Q_NUM */ "", 15018 /* CPU_LB_OPP_CFG */ "", 15019 /* CPU_LO_RQE_Q_NUM */ "", 15020 /* CPU_MASQUERADE_COUNTER_DEST_TYPE */ "", 15021 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE0 */ "", 15022 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE1 */ "", 15023 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE2 */ "", 15024 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE3 */ "", 15025 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE4 */ "", 15026 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE5 */ "", 15027 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE6 */ "", 15028 /* CPU_MASQUERADE_COUNTER_DEST_TYPE_PIPE7 */ "", 15029 /* CPU_PKT_PROFILE_1 */ "", 15030 /* CPU_PKT_PROFILE_2 */ "", 15031 /* CPU_PKT_PROFILE_3 */ "", 15032 /* CPU_PRIORITY_SEL */ "", 15033 /* CPU_PRIORITY_SEL_2 */ "", 15034 /* CPU_QL_CONTROL */ "", 15035 /* CPU_SLOT_COUNT */ "", 15036 /* CPU_TS_PARITY_CONTROL */ "", 15037 /* CPU_TS_PARITY_STATUS_INTR */ "", 15038 /* CPU_TS_PARITY_STATUS_NACK */ "", 15039 /* CRC_APPEND_ENABLE */ "", 15040 /* CRPS_ACCESS_COLLISION_INTERRUPT_REGISTER */ "", 15041 /* CRPS_ACCESS_COLLISION_INTERRUPT_REGISTER_MASK */ "", 15042 /* CRPS_ACCESS_COLLISION_INTERRUPT_REGISTER_TEST */ "", 15043 /* CRPS_CGM_OFFSET_BMAP_A */ "", 15044 /* CRPS_CGM_OFFSET_BMAP_B */ "", 15045 /* CRPS_CGM_POINTER_MASK_A */ "", 15046 /* CRPS_CGM_POINTER_MASK_B */ "", 15047 /* CRPS_CNTCMD_PKTSIZE_COMPENSATION_SETTING */ "", 15048 /* CRPS_CNT_PROCESSOR_READ */ "", 15049 /* CRPS_CNT_PROCESSOR_READ_16 */ "", 15050 /* CRPS_CNT_PROCESSOR_READ_17 */ "", 15051 /* CRPS_CRPS_0_TO_3_PRE_RD_FIFO_STS_1 */ "", 15052 /* CRPS_CRPS_12_TO_16_PRE_RD_FIFO_STS_1 */ "", 15053 /* CRPS_CRPS_12_TO_17_PRE_RD_FIFO_STS_1 */ "", 15054 /* CRPS_CRPS_4_TO_7_PRE_RD_FIFO_STS_1 */ "", 15055 /* CRPS_CRPS_8_TO_11_PRE_RD_FIFO_STS_1 */ "", 15056 /* CRPS_CRPS_CACHE_RD_RESULTS */ "", 15057 /* CRPS_CRPS_CACHE_RD_RESULTS_0_TO_3 */ "", 15058 /* CRPS_CRPS_CACHE_RD_RESULTS_12_TO_16 */ "", 15059 /* CRPS_CRPS_CACHE_RD_RESULTS_12_TO_17 */ "", 15060 /* CRPS_CRPS_CACHE_RD_RESULTS_4_TO_7 */ "", 15061 /* CRPS_CRPS_CACHE_RD_RESULTS_8_TO_11 */ "", 15062 /* CRPS_CRPS_CGM_A_LAST_CMD_RCVD */ "", 15063 /* CRPS_CRPS_CGM_B_LAST_CMD_RCVD */ "", 15064 /* CRPS_CRPS_CNT_OVRF_STS */ "", 15065 /* CRPS_CRPS_CNT_SRC_CFG */ "", 15066 /* CRPS_CRPS_CNT_SRC_GROUP_SIZES */ "", 15067 /* CRPS_CRPS_CNT_SRC_MODE */ "", 15068 /* CRPS_CRPS_COUNTER_STS_1 */ "", 15069 /* CRPS_CRPS_DEBUG_LAST_COMMAND */ "", 15070 /* CRPS_CRPS_DIRECT_RD_RESULT */ "", 15071 /* CRPS_CRPS_DIRECT_RD_RESULT_16 */ "", 15072 /* CRPS_CRPS_DIRECT_RD_RESULT_17 */ "", 15073 /* CRPS_CRPS_DMA_ACCESS */ "", 15074 /* CRPS_CRPS_DMA_ALMOST_FULL_INT_THRESHOLD */ "", 15075 /* CRPS_CRPS_DMA_FIFO_STATUS */ "", 15076 /* CRPS_CRPS_DO_NOT_COUNT_FILTER */ "", 15077 /* CRPS_CRPS_ECC_ERR_DATA_RST_CFG */ "", 15078 /* CRPS_CRPS_EGQ_A_LAST_CMD_RCVD */ "", 15079 /* CRPS_CRPS_EGQ_B_LAST_CMD_RCVD */ "", 15080 /* CRPS_CRPS_EGQ_TM_LAST_CMD_RCVD */ "", 15081 /* CRPS_CRPS_ENGINES_DMA_SELECT */ "", 15082 /* CRPS_CRPS_ENGINE_CFG */ "", 15083 /* CRPS_CRPS_ENGINE_ERROR */ "", 15084 /* CRPS_CRPS_ENGINE_INIT_DONE */ "", 15085 /* CRPS_CRPS_ENGINE_INIT_REQUEST */ "", 15086 /* CRPS_CRPS_ENGINE_MMUX_EN */ "", 15087 /* CRPS_CRPS_ENGINE_SCAN_ENABLE */ "", 15088 /* CRPS_CRPS_ENGINE_WRITE_TOD_ENABLE */ "", 15089 /* CRPS_CRPS_EPNI_A_LAST_CMD_RCVD */ "", 15090 /* CRPS_CRPS_EPNI_B_LAST_CMD_RCVD */ "", 15091 /* CRPS_CRPS_GENERAL_CFG */ "", 15092 /* CRPS_CRPS_IDP_D_LAST_CMD_RCVD */ "", 15093 /* CRPS_CRPS_IDP_S_LAST_CMD_RCVD */ "", 15094 /* CRPS_CRPS_IF_ADAPTER_CFG */ "", 15095 /* CRPS_CRPS_IF_ADAPTER_CGM_IRPP_0_CFG */ "", 15096 /* CRPS_CRPS_IF_ADAPTER_CGM_IRPP_1_CFG */ "", 15097 /* CRPS_CRPS_IF_ADAPTER_CGM_IRPP_2_CFG */ "", 15098 /* CRPS_CRPS_IF_ADAPTER_ETPP_CTR_CFG */ "", 15099 /* CRPS_CRPS_IHB_A_LAST_CMD_RCVD */ "", 15100 /* CRPS_CRPS_IHB_B_LAST_CMD_RCVD */ "", 15101 /* CRPS_CRPS_INIT_ON */ "", 15102 /* CRPS_CRPS_IRPP_A_LAST_CMD_RCVD */ "", 15103 /* CRPS_CRPS_IRPP_B_LAST_CMD_RCVD */ "", 15104 /* CRPS_CRPS_LAST_CMD_RCVD */ "", 15105 /* CRPS_CRPS_LM_DUMMY_REPLY */ "", 15106 /* CRPS_CRPS_MAX_REFRESH_CFG */ "", 15107 /* CRPS_CRPS_MAX_REFRESH_CFG_16 */ "", 15108 /* CRPS_CRPS_MAX_REFRESH_CFG_17 */ "", 15109 /* CRPS_CRPS_MODULESRC_CFG */ "", 15110 /* CRPS_CRPS_ONE_ENTRY_MODE_CNT_CMD */ "", 15111 /* CRPS_CRPS_OVTH_MEM_STS_SEL */ "", 15112 /* CRPS_CRPS_PIPE_COUNTERS */ "", 15113 /* CRPS_CRPS_PIPE_COUNTERS_2 */ "", 15114 /* CRPS_CRPS_PREFETCH_TIMERS_CFG */ "", 15115 /* CRPS_CRPS_PREFETCH_TIMER_PERIOD_CFG */ "", 15116 /* CRPS_CRPS_PRE_RD_FIFO_STS_1 */ "", 15117 /* CRPS_CRPS_SEQUENTIAL_TMR_CFG */ "", 15118 /* CRPS_CRPS_SEQUENTIAL_TMR_CFG_16 */ "", 15119 /* CRPS_CRPS_SEQUENTIAL_TMR_CFG_17 */ "", 15120 /* CRPS_CRPS_SRC_MASK */ "", 15121 /* CRPS_CRPS_THRESHOLDS_CFG */ "", 15122 /* CRPS_DMA_0_FULLNESS_INTERRUPT_REGISTER */ "", 15123 /* CRPS_DMA_0_FULLNESS_INTERRUPT_REGISTER_MASK */ "", 15124 /* CRPS_DMA_0_FULLNESS_INTERRUPT_REGISTER_TEST */ "", 15125 /* CRPS_DMA_1_FULLNESS_INTERRUPT_REGISTER */ "", 15126 /* CRPS_DMA_1_FULLNESS_INTERRUPT_REGISTER_MASK */ "", 15127 /* CRPS_DMA_1_FULLNESS_INTERRUPT_REGISTER_TEST */ "", 15128 /* CRPS_ECC_1B_ERR_CNT */ "", 15129 /* CRPS_ECC_2B_ERR_CNT */ "", 15130 /* CRPS_ECC_ERR_1B_INITIATE */ "", 15131 /* CRPS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 15132 /* CRPS_ECC_ERR_2B_INITIATE */ "", 15133 /* CRPS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 15134 /* CRPS_ECC_INTERRUPT_REGISTER */ "", 15135 /* CRPS_ECC_INTERRUPT_REGISTER_MASK */ "", 15136 /* CRPS_ECC_INTERRUPT_REGISTER_TEST */ "", 15137 /* CRPS_EGQ_0_OFFSET_BMAP_A */ "", 15138 /* CRPS_EGQ_0_OFFSET_BMAP_B */ "", 15139 /* CRPS_EGQ_0_POINTER_MASK_A */ "", 15140 /* CRPS_EGQ_0_POINTER_MASK_B */ "", 15141 /* CRPS_EGQ_0_TM_OFFSET_BMAP */ "", 15142 /* CRPS_EGQ_0_TM_POINTER_MASK */ "", 15143 /* CRPS_EGQ_1_OFFSET_BMAP_A */ "", 15144 /* CRPS_EGQ_1_OFFSET_BMAP_B */ "", 15145 /* CRPS_EGQ_1_POINTER_MASK_A */ "", 15146 /* CRPS_EGQ_1_POINTER_MASK_B */ "", 15147 /* CRPS_EGQ_1_TM_OFFSET_BMAP */ "", 15148 /* CRPS_EGQ_1_TM_POINTER_MASK */ "", 15149 /* CRPS_EGQ_OFFSET_BMAP_A */ "", 15150 /* CRPS_EGQ_OFFSET_BMAP_B */ "", 15151 /* CRPS_EGQ_POINTER_MASK_A */ "", 15152 /* CRPS_EGQ_POINTER_MASK_B */ "", 15153 /* CRPS_EGQ_TM_OFFSET_BMAP */ "", 15154 /* CRPS_EGQ_TM_POINTER_MASK */ "", 15155 /* CRPS_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 15156 /* CRPS_ENGINE_INTERRUPT_MASK_REGISTER */ "", 15157 /* CRPS_ENGINE_INTERRUPT_REGISTER */ "", 15158 /* CRPS_ENGINE_INTERRUPT_REGISTER_TEST */ "", 15159 /* CRPS_EPNI_0_OFFSET_BMAP_A */ "", 15160 /* CRPS_EPNI_0_OFFSET_BMAP_B */ "", 15161 /* CRPS_EPNI_0_POINTER_MASK_A */ "", 15162 /* CRPS_EPNI_0_POINTER_MASK_B */ "", 15163 /* CRPS_EPNI_1_OFFSET_BMAP_A */ "", 15164 /* CRPS_EPNI_1_OFFSET_BMAP_B */ "", 15165 /* CRPS_EPNI_1_POINTER_MASK_A */ "", 15166 /* CRPS_EPNI_1_POINTER_MASK_B */ "", 15167 /* CRPS_EPNI_OFFSET_BMAP_A */ "", 15168 /* CRPS_EPNI_OFFSET_BMAP_B */ "", 15169 /* CRPS_EPNI_POINTER_MASK_A */ "", 15170 /* CRPS_EPNI_POINTER_MASK_B */ "", 15171 /* CRPS_ERROR_COUNTER_OVF_ERROR_INTERRUPT_REGISTER */ "", 15172 /* CRPS_ERROR_COUNTER_OVF_ERROR_INTERRUPT_REGISTER_MASK */ "", 15173 /* CRPS_ERROR_COUNTER_OVF_ERROR_INTERRUPT_REGISTER_TEST */ "", 15174 /* CRPS_ERROR_INITIATION_DATA */ "", 15175 /* CRPS_GLOBAL_MEM_OPTIONS */ "", 15176 /* CRPS_GTIMER_CONFIGURATION */ "", 15177 /* CRPS_GTIMER_CYCLE */ "", 15178 /* CRPS_GTIMER_TRIGGER */ "", 15179 /* CRPS_IDPD_POINTER_MASK */ "", 15180 /* CRPS_IDPS_POINTER_MASK */ "", 15181 /* CRPS_IHBA_POINTER_MASK */ "", 15182 /* CRPS_IHBB_POINTER_MASK */ "", 15183 /* CRPS_IHB_0_POINTER_MASK */ "", 15184 /* CRPS_IHB_1_POINTER_MASK */ "", 15185 /* CRPS_INDIRECT_COMMAND */ "", 15186 /* CRPS_INDIRECT_COMMAND_ADDRESS */ "", 15187 /* CRPS_INDIRECT_COMMAND_DATA_INCREMENT */ "", 15188 /* CRPS_INDIRECT_COMMAND_RD_DATA */ "", 15189 /* CRPS_INDIRECT_COMMAND_WIDE_MEM */ "", 15190 /* CRPS_INDIRECT_COMMAND_WR_DATA */ "", 15191 /* CRPS_INDIRECT_FORCE_BUBBLE */ "", 15192 /* CRPS_INDIRECT_WR_MASK */ "", 15193 /* CRPS_INTERRUPT_MASK_REGISTER */ "", 15194 /* CRPS_INTERRUPT_REGISTER */ "", 15195 /* CRPS_INTERRUPT_REGISTER_TEST */ "", 15196 /* CRPS_IPT_0_POINTER_MASK */ "", 15197 /* CRPS_IPT_1_POINTER_MASK */ "", 15198 /* CRPS_IQM_0_OFFSET_BMAP_A */ "", 15199 /* CRPS_IQM_0_OFFSET_BMAP_B */ "", 15200 /* CRPS_IQM_0_POINTER_MASK_A */ "", 15201 /* CRPS_IQM_0_POINTER_MASK_B */ "", 15202 /* CRPS_IQM_1_OFFSET_BMAP_A */ "", 15203 /* CRPS_IQM_1_OFFSET_BMAP_B */ "", 15204 /* CRPS_IQM_1_POINTER_MASK_A */ "", 15205 /* CRPS_IQM_1_POINTER_MASK_B */ "", 15206 /* CRPS_IRPP_0_OFFSET_BMAP_A */ "", 15207 /* CRPS_IRPP_0_OFFSET_BMAP_B */ "", 15208 /* CRPS_IRPP_0_POINTER_MASK_A */ "", 15209 /* CRPS_IRPP_0_POINTER_MASK_B */ "", 15210 /* CRPS_IRPP_1_OFFSET_BMAP_A */ "", 15211 /* CRPS_IRPP_1_OFFSET_BMAP_B */ "", 15212 /* CRPS_IRPP_1_POINTER_MASK_A */ "", 15213 /* CRPS_IRPP_1_POINTER_MASK_B */ "", 15214 /* CRPS_IRPP_OFFSET_BMAP_A */ "", 15215 /* CRPS_IRPP_OFFSET_BMAP_B */ "", 15216 /* CRPS_IRPP_POINTER_MASK_A */ "", 15217 /* CRPS_IRPP_POINTER_MASK_B */ "", 15218 /* CRPS_LM_COLLISION_ERROR_INTERRUPT_REGISTER */ "", 15219 /* CRPS_LM_COLLISION_ERROR_INTERRUPT_REGISTER_MASK */ "", 15220 /* CRPS_LM_COLLISION_ERROR_INTERRUPT_REGISTER_TEST */ "", 15221 /* CRPS_PARITY_ERR_CNT */ "", 15222 /* CRPS_PAR_ERR_INITIATE */ "", 15223 /* CRPS_PAR_ERR_INTERRUPT_MASK_REGISTER */ "", 15224 /* CRPS_PAR_ERR_INTERRUPT_REGISTER */ "", 15225 /* CRPS_PAR_ERR_INTERRUPT_REGISTER_TEST */ "", 15226 /* CRPS_PAR_ERR_MEM_MASK */ "", 15227 /* CRPS_REG_0041 */ "", 15228 /* CRPS_REG_0085 */ "", 15229 /* CRPS_REG_0086 */ "", 15230 /* CRPS_REG_0087 */ "", 15231 /* CRPS_REG_0090 */ "", 15232 /* CRPS_REG_0091 */ "", 15233 /* CRPS_REG_0092 */ "", 15234 /* CRPS_REG_0093 */ "", 15235 /* CRPS_REG_00A4 */ "", 15236 /* CRPS_REG_00A6 */ "", 15237 /* CRPS_REG_00AE */ "", 15238 /* CRPS_REG_00AF */ "", 15239 /* CRPS_REG_00C2 */ "", 15240 /* CRPS_REG_00CE */ "", 15241 /* CRPS_RESERVED_MIRROR_ADDR */ "", 15242 /* CRPS_RESERVED_MTCD */ "", 15243 /* CRPS_RESERVED_MTCP */ "", 15244 /* CRPS_RESERVED_PCMI_0 */ "", 15245 /* CRPS_RESERVED_PCMI_1 */ "", 15246 /* CRPS_RESERVED_PCMI_2 */ "", 15247 /* CRPS_RESERVED_PCMI_3 */ "", 15248 /* CRPS_RESERVED_PCMI_4 */ "", 15249 /* CRPS_RESERVED_PCMI_0_S */ "", 15250 /* CRPS_RESERVED_PCMI_0_T */ "", 15251 /* CRPS_RESERVED_PCMI_1_S */ "", 15252 /* CRPS_RESERVED_PCMI_1_T */ "", 15253 /* CRPS_RESERVED_PCMI_2_S */ "", 15254 /* CRPS_RESERVED_PCMI_2_T */ "", 15255 /* CRPS_RESERVED_PCMI_3_S */ "", 15256 /* CRPS_RESERVED_PCMI_3_T */ "", 15257 /* CRPS_RESERVED_PCMI_4_S */ "", 15258 /* CRPS_RESERVED_PCMI_4_T */ "", 15259 /* CRPS_RESERVED_SPARE_0 */ "", 15260 /* CRPS_RESERVED_SPARE_1 */ "", 15261 /* CRPS_RESERVED_SPARE_2 */ "", 15262 /* CRPS_RESERVED_SPARE_3 */ "", 15263 /* CRPS_SBUS_BROADCAST_ID */ "", 15264 /* CRPS_SBUS_LAST_IN_CHAIN */ "", 15265 /* CRPS_SRC_CMD_CNT */ "", 15266 /* CRPS_SRC_CMD_WAS_FILTERED_INTERRUPT_REGISTER */ "", 15267 /* CRPS_SRC_CMD_WAS_FILTERED_INTERRUPT_REGISTER_MASK */ "", 15268 /* CRPS_SRC_CMD_WAS_FILTERED_INTERRUPT_REGISTER_TEST */ "", 15269 /* CRPS_SRC_INVLID_ACCESS_INTERRUPT_REGISTER */ "", 15270 /* CRPS_SRC_INVLID_ACCESS_INTERRUPT_REGISTER_MASK */ "", 15271 /* CRPS_SRC_INVLID_ACCESS_INTERRUPT_REGISTER_TEST */ "", 15272 /* CRPS_TWO_ENGINE_MODE */ "", 15273 /* CRU_CONTROL */ "", 15274 /* CRU_CPU0_POWERDOWN */ "", 15275 /* CRU_CPU0_POWERUP */ "", 15276 /* CRU_DDRPHY_PWR_CTRL */ "", 15277 /* CRU_DEBUG */ "", 15278 /* CRU_IHOST_PWRDWN_EN */ "", 15279 /* CRU_IHOST_PWRDWN_STATUS */ "", 15280 /* CRU_POWERSEQ_TIMER1 */ "", 15281 /* CRU_POWERSEQ_TIMER2 */ "", 15282 /* CRU_STATUS */ "", 15283 /* CRU_TIMER */ "", 15284 /* CRYPTO_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 15285 /* CRYPTO_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 15286 /* CRYPTO_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 15287 /* CRYPTO_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 15288 /* CRYPTO_S0_IDM_IDM_ERROR_LOG_ID */ "", 15289 /* CRYPTO_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 15290 /* CRYPTO_S0_IDM_IDM_INTERRUPT_STATUS */ "", 15291 /* CRYPTO_S0_IDM_IDM_RESET_CONTROL */ "", 15292 /* CRYPTO_S0_IDM_IDM_RESET_READ_ID */ "", 15293 /* CRYPTO_S0_IDM_IDM_RESET_STATUS */ "", 15294 /* CRYPTO_S0_IDM_IDM_RESET_WRITE_ID */ "", 15295 /* CSRCSEL_CHID_0 */ "", 15296 /* CSRCSEL_CHID_1 */ "", 15297 /* CSRCSEL_CHID_2 */ "", 15298 /* CSRCSEL_CHID_3 */ "", 15299 /* CSRCSEL_CHID_4 */ "", 15300 /* CSRCSEL_CHID_5 */ "", 15301 /* CSRCSEL_CHID_6 */ "", 15302 /* CSRCSEL_CHID_7 */ "", 15303 /* CSRCSEL_CHID_8 */ "", 15304 /* CSRCSEL_CHID_9 */ "", 15305 /* CSRCSEL_CHID_10 */ "", 15306 /* CSRCSEL_CHID_11 */ "", 15307 /* CSRCSEL_CHID_12 */ "", 15308 /* CSRCSEL_CHID_13 */ "", 15309 /* CSRCSEL_CHID_14 */ "", 15310 /* CSRCSEL_CHID_15 */ "", 15311 /* CSRCSEL_CHID_16 */ "", 15312 /* CSRCSEL_CHID_17 */ "", 15313 /* CSRCSEL_CHID_18 */ "", 15314 /* CSRCSEL_CHID_19 */ "", 15315 /* CSRCSEL_CHID_20 */ "", 15316 /* CSRCSEL_CHID_21 */ "", 15317 /* CSRCSEL_CHID_22 */ "", 15318 /* CSRCSEL_CHID_23 */ "", 15319 /* CSRCSEL_CHID_24 */ "", 15320 /* CSRCSEL_CHID_25 */ "", 15321 /* CSRCSEL_CHID_26 */ "", 15322 /* CSRCSEL_CHID_27 */ "", 15323 /* CSRCSEL_CHID_28 */ "", 15324 /* CSRCSEL_CHID_29 */ "", 15325 /* CSRCSEL_CHID_30 */ "", 15326 /* CSRCSEL_CHID_31 */ "", 15327 /* CSRCSEL_CHID_32 */ "", 15328 /* CSRCSEL_CHID_33 */ "", 15329 /* CSRCSEL_CHID_34 */ "", 15330 /* CSRCSEL_CHID_35 */ "", 15331 /* CSRCSEL_CHID_36 */ "", 15332 /* CSRCSEL_CHID_37 */ "", 15333 /* CSRCSEL_CHID_38 */ "", 15334 /* CSRCSEL_CHID_39 */ "", 15335 /* CSRCSEL_CHID_40 */ "", 15336 /* CSRCSEL_CHID_41 */ "", 15337 /* CSRCSEL_CHID_42 */ "", 15338 /* CSRCSEL_CHID_43 */ "", 15339 /* CSRCSEL_CHID_44 */ "", 15340 /* CSRCSEL_CHID_45 */ "", 15341 /* CSRCSEL_CHID_46 */ "", 15342 /* CSRCSEL_CHID_47 */ "", 15343 /* CSRCSEL_CHID_48 */ "", 15344 /* CSRCSEL_CHID_49 */ "", 15345 /* CSRCSEL_CHID_50 */ "", 15346 /* CSRCSEL_CHID_51 */ "", 15347 /* CSRCSEL_CHID_52 */ "", 15348 /* CSRCSEL_CHID_53 */ "", 15349 /* CSRCSEL_CHID_54 */ "", 15350 /* CSRCSEL_CHID_55 */ "", 15351 /* CSRCSEL_CHID_56 */ "", 15352 /* CSRCSEL_CHID_57 */ "", 15353 /* CSRCSEL_CHID_58 */ "", 15354 /* CSRCSEL_CHID_59 */ "", 15355 /* CSRCSEL_CHID_60 */ "", 15356 /* CSRCSEL_CHID_61 */ "", 15357 /* CSRCSEL_CHID_62 */ "", 15358 /* CSRCSEL_CHID_63 */ "", 15359 /* CTRL_DA1 */ "", 15360 /* CTRL_DA2 */ "", 15361 /* CTRL_DA3 */ "", 15362 /* CTRL_DA4 */ "", 15363 /* CTRL_DA5 */ "", 15364 /* CTRL_DA6 */ "", 15365 /* CTRL_ETHERTYPE1 */ "", 15366 /* CTRL_ETHERTYPE2 */ "", 15367 /* CTR_DEQ_DEBUG */ "", 15368 /* CTR_DEQ_DTYPE_TBL0 */ "", 15369 /* CTR_DEQ_DTYPE_TBL1 */ "", 15370 /* CTR_DEQ_DTYPE_TBL2 */ "", 15371 /* CTR_DEQ_S1_STATS_EN */ "", 15372 /* CTR_DEQ_STATS_CFG */ "", 15373 /* CTR_DEQ_STATUS_ECC_STATUS */ "", 15374 /* CTR_ECC_DEBUG */ "", 15375 /* CTR_ENQ_DEBUG */ "", 15376 /* CTR_ENQ_STATS_CFG */ "", 15377 /* CTR_ERROR */ "", 15378 /* CTR_ERROR_MASK */ "", 15379 /* CTR_FLEX_CNT_ECC_STATUS */ "", 15380 /* CTR_MEM_CFG */ "", 15381 /* CTR_MEM_DEBUG */ "", 15382 /* CTR_MEM_TM */ "", 15383 /* CTR_Q_STATS_MAP */ "", 15384 /* CTR_RQE_FIFO_ECC_STATUS */ "", 15385 /* CTR_SEGMENT_START */ "", 15386 /* CTR_SYS_CONTROL */ "", 15387 /* CT_FIFO_DBG */ "", 15388 /* CT_PURGE_CNT */ "", 15389 /* CT_PURGE_CNT_XPE0 */ "", 15390 /* CT_PURGE_CNT_XPE1 */ "", 15391 /* CT_PURGE_CNT_XPE2 */ "", 15392 /* CT_PURGE_CNT_XPE3 */ "", 15393 /* CUSTOM_HEADER_MASK */ "", 15394 /* CUSTOM_PACKET_HEADER_OVERRIDE */ "", 15395 /* CUT_THROUGH_PRIORITY */ "", 15396 /* CWINTEQ */ "", 15397 /* CWINTMSK */ "", 15398 /* CWINTQST */ "", 15399 /* CWINTS_CHID_0 */ "", 15400 /* CWINTS_CHID_1 */ "", 15401 /* CWINTS_CHID_2 */ "", 15402 /* CWINTS_CHID_3 */ "", 15403 /* CWINTS_CHID_4 */ "", 15404 /* CWINTS_CHID_5 */ "", 15405 /* CWINTS_CHID_6 */ "", 15406 /* CWINTS_CHID_7 */ "", 15407 /* CWINTS_CHID_8 */ "", 15408 /* CWINTS_CHID_9 */ "", 15409 /* CWINTS_CHID_10 */ "", 15410 /* CWINTS_CHID_11 */ "", 15411 /* CWINTS_CHID_12 */ "", 15412 /* CWINTS_CHID_13 */ "", 15413 /* CWINTS_CHID_14 */ "", 15414 /* CWINTS_CHID_15 */ "", 15415 /* CWINTS_CHID_16 */ "", 15416 /* CWINTS_CHID_17 */ "", 15417 /* CWINTS_CHID_18 */ "", 15418 /* CWINTS_CHID_19 */ "", 15419 /* CWINTS_CHID_20 */ "", 15420 /* CWINTS_CHID_21 */ "", 15421 /* CWINTS_CHID_22 */ "", 15422 /* CWINTS_CHID_23 */ "", 15423 /* CWINTS_CHID_24 */ "", 15424 /* CWINTS_CHID_25 */ "", 15425 /* CWINTS_CHID_26 */ "", 15426 /* CWINTS_CHID_27 */ "", 15427 /* CWINTS_CHID_28 */ "", 15428 /* CWINTS_CHID_29 */ "", 15429 /* CWINTS_CHID_30 */ "", 15430 /* CWINTS_CHID_31 */ "", 15431 /* CWINTS_CHID_32 */ "", 15432 /* CWINTS_CHID_33 */ "", 15433 /* CWINTS_CHID_34 */ "", 15434 /* CWINTS_CHID_35 */ "", 15435 /* CWINTS_CHID_36 */ "", 15436 /* CWINTS_CHID_37 */ "", 15437 /* CWINTS_CHID_38 */ "", 15438 /* CWINTS_CHID_39 */ "", 15439 /* CWINTS_CHID_40 */ "", 15440 /* CWINTS_CHID_41 */ "", 15441 /* CWINTS_CHID_42 */ "", 15442 /* CWINTS_CHID_43 */ "", 15443 /* CWINTS_CHID_44 */ "", 15444 /* CWINTS_CHID_45 */ "", 15445 /* CWINTS_CHID_46 */ "", 15446 /* CWINTS_CHID_47 */ "", 15447 /* CWINTS_CHID_48 */ "", 15448 /* CWINTS_CHID_49 */ "", 15449 /* CWINTS_CHID_50 */ "", 15450 /* CWINTS_CHID_51 */ "", 15451 /* CWINTS_CHID_52 */ "", 15452 /* CWINTS_CHID_53 */ "", 15453 /* CWINTS_CHID_54 */ "", 15454 /* CWINTS_CHID_55 */ "", 15455 /* CWINTS_CHID_56 */ "", 15456 /* CWINTS_CHID_57 */ "", 15457 /* CWINTS_CHID_58 */ "", 15458 /* CWINTS_CHID_59 */ "", 15459 /* CWINTS_CHID_60 */ "", 15460 /* CWINTS_CHID_61 */ "", 15461 /* CWINTS_CHID_62 */ "", 15462 /* CWINTS_CHID_63 */ "", 15463 /* CW_PD_CELL_CTRL */ "", 15464 /* CW_PD_CELL_GO */ "", 15465 /* CW_PE_CELL_CTRL */ "", 15466 /* CW_PE_CELL_GO */ "", 15467 /* CW_PKT_CELL_DATA0 */ "", 15468 /* CW_PKT_CELL_DATA1 */ "", 15469 /* CW_PKT_CELL_DATA2 */ "", 15470 /* CW_PKT_CELL_DATA3 */ "", 15471 /* CW_PKT_CELL_DATA4 */ "", 15472 /* CW_PKT_CELL_DATA5 */ "", 15473 /* CW_PKT_CELL_DATA6 */ "", 15474 /* CW_PKT_CELL_DATA7 */ "", 15475 /* CW_PKT_CELL_DATA8 */ "", 15476 /* CW_PKT_CELL_DATA9 */ "", 15477 /* CW_PKT_CELL_DATA10 */ "", 15478 /* CW_PKT_CELL_DATA11 */ "", 15479 /* CW_PKT_CELL_DATA12 */ "", 15480 /* CW_PKT_CELL_DATA13 */ "", 15481 /* CW_PKT_CELL_DATA14 */ "", 15482 /* CW_PKT_CELL_DATA15 */ "", 15483 /* CW_PKT_CELL_DATA16 */ "", 15484 /* CW_PKT_CELL_DATA17 */ "", 15485 /* CW_PKT_CELL_DATA18 */ "", 15486 /* CW_PKT_CELL_DATA19 */ "", 15487 /* CW_PKT_CELL_DATA20 */ "", 15488 /* CW_PKT_CELL_DATA21 */ "", 15489 /* CW_PKT_CELL_DATA22 */ "", 15490 /* CW_PKT_CELL_DATA23 */ "", 15491 /* CW_PKT_CELL_DATA24 */ "", 15492 /* CW_PKT_CELL_DATA25 */ "", 15493 /* CW_PKT_CELL_DATA26 */ "", 15494 /* CW_PKT_CELL_DATA27 */ "", 15495 /* CW_PKT_CELL_DATA28 */ "", 15496 /* CW_PKT_CELL_DATA29 */ "", 15497 /* CW_PKT_CELL_DATA30 */ "", 15498 /* CW_PKT_CELL_DATA31 */ "", 15499 /* CXXPORT_INTR_ENABLE */ "", 15500 /* CXXPORT_INTR_STATUS */ "", 15501 /* CXXPORT_LED_CHAIN_CONFIG */ "", 15502 /* CXXPORT_MODE_REG */ "", 15503 /* CXXPORT_POWER_SAVE */ "", 15504 /* CXXPORT_SBUS_CONTROL */ "", 15505 /* CXXPORT_SOFT_RESET */ "", 15506 /* CXXPORT_SPARE_REG */ "", 15507 /* CXXPORT_WC_UCMEM_CTRL0 */ "", 15508 /* CXXPORT_WC_UCMEM_CTRL1 */ "", 15509 /* CXXPORT_WC_UCMEM_CTRL2 */ "", 15510 /* CXXPORT_XGXS0_CTRL0_REG */ "", 15511 /* CXXPORT_XGXS0_CTRL1_REG */ "", 15512 /* CXXPORT_XGXS0_CTRL2_REG */ "", 15513 /* CXX_CXXPORT_INTR_ENABLE */ "", 15514 /* CXX_CXXPORT_INTR_STATUS */ "", 15515 /* CXX_CXXPORT_LED_CHAIN_CONFIG */ "", 15516 /* CXX_CXXPORT_MODE_REG */ "", 15517 /* CXX_CXXPORT_POWER_SAVE */ "", 15518 /* CXX_CXXPORT_SBUS_CONTROL */ "", 15519 /* CXX_CXXPORT_SOFT_RESET */ "", 15520 /* CXX_CXXPORT_SPARE_REG */ "", 15521 /* CXX_CXXPORT_WC_UCMEM_CTRL_0 */ "", 15522 /* CXX_CXXPORT_WC_UCMEM_CTRL_1 */ "", 15523 /* CXX_CXXPORT_WC_UCMEM_CTRL_2 */ "", 15524 /* CXX_CXXPORT_XGXS_0_CTRL_0_REG */ "", 15525 /* CXX_CXXPORT_XGXS_0_CTRL_1_REG */ "", 15526 /* CXX_CXXPORT_XGXS_0_CTRL_2_REG */ "", 15527 /* CYCLE_TIME */ "", 15528 /* CYCLE_TIME_EXTENSION */ "", 15529 /* DCH_AUTO_DOC_NAME_0 */ "", 15530 /* DCH_AUTO_DOC_NAME_13 */ "", 15531 /* DCH_AUTO_DOC_NAME_15 */ "", 15532 /* DCH_AUTO_DOC_NAME_16 */ "", 15533 /* DCH_AUTO_DOC_NAME_17 */ "", 15534 /* DCH_AUTO_DOC_NAME_29 */ "", 15535 /* DCH_AUTO_DOC_NAME_31 */ "", 15536 /* DCH_AUTO_DOC_NAME_33 */ "", 15537 /* DCH_AUTO_DOC_NAME_35 */ "", 15538 /* DCH_AUTO_DOC_NAME_36 */ "", 15539 /* DCH_AUTO_DOC_NAME_37 */ "", 15540 /* DCH_AUTO_DOC_NAME_38 */ "", 15541 /* DCH_AUTO_DOC_NAME_39 */ "", 15542 /* DCH_AUTO_DOC_NAME_40 */ "", 15543 /* DCH_AUTO_DOC_NAME_41 */ "", 15544 /* DCH_AUTO_DOC_NAME_42 */ "", 15545 /* DCH_AUTO_DOC_NAME_43 */ "", 15546 /* DCH_AUTO_DOC_NAME_44 */ "", 15547 /* DCH_AUTO_DOC_NAME_45 */ "", 15548 /* DCH_AUTO_DOC_NAME_46 */ "", 15549 /* DCH_AUTO_DOC_NAME_47 */ "", 15550 /* DCH_AUTO_DOC_NAME_48 */ "", 15551 /* DCH_AUTO_DOC_NAME_49 */ "", 15552 /* DCH_CAPTURED_CELL_A */ "", 15553 /* DCH_CAPTURED_CELL_B */ "", 15554 /* DCH_CAPTURED_CELL_C */ "", 15555 /* DCH_CAPTURED_CELL_D */ "", 15556 /* DCH_CAPTURED_CELL_DATA_0 */ "", 15557 /* DCH_CAPTURED_CELL_DATA_1 */ "", 15558 /* DCH_CAPTURED_CELL_DATA_2 */ "", 15559 /* DCH_CELL_TYPE_ERR_SRC */ "", 15560 /* DCH_CPU_DATA_CELL_AP */ "", 15561 /* DCH_CPU_DATA_CELL_AS */ "", 15562 /* DCH_CPU_DATA_CELL_BP */ "", 15563 /* DCH_CPU_DATA_CELL_BS */ "", 15564 /* DCH_DCH_DROPPED_LOW_MUL_CNT_P */ "", 15565 /* DCH_DCH_DROPPED_LOW_MUL_CNT_S */ "", 15566 /* DCH_DCH_ENABLERS_REGISTER_1 */ "", 15567 /* DCH_DCH_ENABLERS_REGISTER_2 */ "", 15568 /* DCH_DCH_ENABLERS_REGISTER_2_P */ "", 15569 /* DCH_DCH_ENABLERS_REGISTER_3_P */ "", 15570 /* DCH_DCH_ERROR_INITIATION_DATA */ "", 15571 /* DCH_DCH_LOCAL_GCI_TYPE_0_TH_P */ "", 15572 /* DCH_DCH_LOCAL_GCI_TYPE_0_TH_S */ "", 15573 /* DCH_DCH_LOCAL_GCI_TYPE_1_TH_P */ "", 15574 /* DCH_DCH_LOCAL_GCI_TYPE_1_TH_S */ "", 15575 /* DCH_DCH_OVERFLOWS_AND_FIFOS_STATUSES_P */ "", 15576 /* DCH_DCH_OVERFLOWS_AND_FIFOS_STATUSES_S */ "", 15577 /* DCH_DCH_REORD_DISCARD_COUNTER_P */ "", 15578 /* DCH_DCH_REORD_DISCARD_COUNTER_S */ "", 15579 /* DCH_DCH_TOTAL_CELL_CNT_P */ "", 15580 /* DCH_DCH_TOTAL_CELL_CNT_P_0 */ "", 15581 /* DCH_DCH_TOTAL_CELL_CNT_P_1 */ "", 15582 /* DCH_DCH_TOTAL_CELL_CNT_P_2 */ "", 15583 /* DCH_DCH_TOTAL_CELL_CNT_S */ "", 15584 /* DCH_DCH_TOTAL_OUT_CELL_CNT_P */ "", 15585 /* DCH_DCH_TOTAL_OUT_CELL_CNT_P_0 */ "", 15586 /* DCH_DCH_TOTAL_OUT_CELL_CNT_P_1 */ "", 15587 /* DCH_DCH_TOTAL_OUT_CELL_CNT_P_2 */ "", 15588 /* DCH_DCH_TOTAL_OUT_CELL_CNT_S */ "", 15589 /* DCH_DCMM_FLOW_CNTROL_CNT */ "", 15590 /* DCH_DCMU_FLOW_CNTROL_CNT */ "", 15591 /* DCH_DCM_FLOW_CNTROL_0_CNT_P_0 */ "", 15592 /* DCH_DCM_FLOW_CNTROL_0_CNT_P_1 */ "", 15593 /* DCH_DCM_FLOW_CNTROL_0_CNT_P_2 */ "", 15594 /* DCH_DCM_FLOW_CNTROL_1_CNT_P_0 */ "", 15595 /* DCH_DCM_FLOW_CNTROL_1_CNT_P_1 */ "", 15596 /* DCH_DCM_FLOW_CNTROL_1_CNT_P_2 */ "", 15597 /* DCH_DROP_FILTER_CNT */ "", 15598 /* DCH_DROP_LOW_PRIORITY_CNT_P */ "", 15599 /* DCH_DROP_LOW_PRI_CNT_P */ "", 15600 /* DCH_DROP_LOW_PRI_CNT_S */ "", 15601 /* DCH_DYN_PIPES_WEIGHTS_REGISTER */ "", 15602 /* DCH_DYN_WFQ_WEIGHT_THD_REGISTE */ "", 15603 /* DCH_ECC_1B_ERR_ADDR */ "", 15604 /* DCH_ECC_1B_ERR_CNT */ "", 15605 /* DCH_ECC_2B_ERR_ADDR */ "", 15606 /* DCH_ECC_2B_ERR_CNT */ "", 15607 /* DCH_ECC_ERR_1B_INITIATE */ "", 15608 /* DCH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 15609 /* DCH_ECC_ERR_2B_INITIATE */ "", 15610 /* DCH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 15611 /* DCH_ECC_ERR_MONITOR_MEM_MASK */ "", 15612 /* DCH_ECC_INTERRUPT_REGISTER */ "", 15613 /* DCH_ECC_INTERRUPT_REGISTER_MASK */ "", 15614 /* DCH_ECC_INTERRUPT_REGISTER_TEST */ "", 15615 /* DCH_ERROR_FILTER */ "", 15616 /* DCH_ERROR_FILTER_2 */ "", 15617 /* DCH_ERROR_FILTER_CNT */ "", 15618 /* DCH_ERROR_FILTER_CNT_P */ "", 15619 /* DCH_ERROR_FILTER_CNT_S */ "", 15620 /* DCH_ERROR_FILTER_EN */ "", 15621 /* DCH_ERROR_FILTER_MASK */ "", 15622 /* DCH_ERROR_FILTER_MASK_2 */ "", 15623 /* DCH_ERROR_FILTER_MASK_EN */ "", 15624 /* DCH_ERROR_INITIATION_DATA */ "", 15625 /* DCH_FAP_GLOBAL_GENERAL_CFG_1 */ "", 15626 /* DCH_FE_1600_B_0_ENABLERS */ "", 15627 /* DCH_FE_GLOBAL_GENERAL_CFG_1 */ "", 15628 /* DCH_FIFOS_DEPTH_TYPE */ "", 15629 /* DCH_FIFO_DISCARD_CNT_P */ "", 15630 /* DCH_FIFO_DISCARD_COUNTER_P */ "", 15631 /* DCH_FIFO_DISCARD_COUNTER_S */ "", 15632 /* DCH_FILTER_MATCH_INPUT_LINK */ "", 15633 /* DCH_GEN_ERR_MEM */ "", 15634 /* DCH_GLOBAL_FE_DEST_IDS_1 */ "", 15635 /* DCH_GLOBAL_FE_DEST_IDS_2 */ "", 15636 /* DCH_GLOBAL_GENERAL_CFG_1 */ "", 15637 /* DCH_GLOBAL_GENERAL_FE_CFG_1 */ "", 15638 /* DCH_GLOBAL_MEM_OPTIONS */ "", 15639 /* DCH_GTIMER_CONFIGURATION */ "", 15640 /* DCH_GTIMER_CYCLE */ "", 15641 /* DCH_GTIMER_TRIGGER */ "", 15642 /* DCH_IFM_MAX_OCCUP_P_0 */ "", 15643 /* DCH_IFM_MAX_OCCUP_P_1 */ "", 15644 /* DCH_IFM_MAX_OCCUP_P_2 */ "", 15645 /* DCH_INTERRUPT_MASK_REGISTER */ "", 15646 /* DCH_INTERRUPT_MASK_REGISTER_1 */ "", 15647 /* DCH_INTERRUPT_MASK_REGISTER_2 */ "", 15648 /* DCH_INTERRUPT_REGISTER */ "", 15649 /* DCH_INTERRUPT_REGISTER_1 */ "", 15650 /* DCH_INTERRUPT_REGISTER_2 */ "", 15651 /* DCH_INTERRUPT_REGISTER_TEST */ "", 15652 /* DCH_LINK_CELL_PACKING_EN */ "", 15653 /* DCH_LINK_LEVEL_FLOW_CONTROL_BMP */ "", 15654 /* DCH_LINK_LEVEL_FLOW_CONTROL_BMP_P */ "", 15655 /* DCH_LINK_LEVEL_FLOW_CONTROL_BMP_S */ "", 15656 /* DCH_LINK_LEVEL_FLOW_CONTROL_P */ "", 15657 /* DCH_LINK_LEVEL_FLOW_CONTROL_P_0 */ "", 15658 /* DCH_LINK_LEVEL_FLOW_CONTROL_P_1 */ "", 15659 /* DCH_LINK_LEVEL_FLOW_CONTROL_P_2 */ "", 15660 /* DCH_LINK_LEVEL_FLOW_CONTROL_S */ "", 15661 /* DCH_LINK_UP_STATUS_FROM_DCHP */ "", 15662 /* DCH_LINK_UP_STATUS_FROM_DCHP_0 */ "", 15663 /* DCH_LINK_UP_STATUS_FROM_DCHP_1 */ "", 15664 /* DCH_LINK_UP_STATUS_FROM_DCHP_2 */ "", 15665 /* DCH_LINK_UP_STATUS_FROM_DCHS */ "", 15666 /* DCH_LOCAL_GCI_RCI_TYPE_0_P */ "", 15667 /* DCH_LOCAL_GCI_RCI_TYPE_1_P */ "", 15668 /* DCH_LOCAL_GCI_TYPE_0_P */ "", 15669 /* DCH_LOCAL_GCI_TYPE_1_P */ "", 15670 /* DCH_LOW_PR_MUL_0 */ "", 15671 /* DCH_LOW_PR_MUL_1 */ "", 15672 /* DCH_LP_PIPE_SHAPER_REGISTER */ "", 15673 /* DCH_MATCH_FILT */ "", 15674 /* DCH_MATCH_FILT_MASK */ "", 15675 /* DCH_MC_EST_NOF_REP */ "", 15676 /* DCH_MID_PR_MUL_0 */ "", 15677 /* DCH_MID_PR_MUL_1 */ "", 15678 /* DCH_PARITY_ERR_ADDR */ "", 15679 /* DCH_PARITY_ERR_CNT */ "", 15680 /* DCH_PCMI_0 */ "", 15681 /* DCH_PCMI_1 */ "", 15682 /* DCH_PCMI_2 */ "", 15683 /* DCH_PCMI_3 */ "", 15684 /* DCH_PCMI_0_S */ "", 15685 /* DCH_PCMI_0_T */ "", 15686 /* DCH_PCMI_1_S */ "", 15687 /* DCH_PCMI_1_T */ "", 15688 /* DCH_PCMI_2_S */ "", 15689 /* DCH_PCMI_2_T */ "", 15690 /* DCH_PCMI_3_S */ "", 15691 /* DCH_PCMI_3_T */ "", 15692 /* DCH_PETRA_BMP */ "", 15693 /* DCH_PETRA_PIPE_BMP */ "", 15694 /* DCH_PIPES_MAPPING_EN */ "", 15695 /* DCH_PIPES_MAP_EN */ "", 15696 /* DCH_PIPES_SEPARATION_REGISTER */ "", 15697 /* DCH_PIPES_WEIGHTS_COUNTER_PN */ "", 15698 /* DCH_PIPES_WEIGHTS_REGISTER */ "", 15699 /* DCH_PIPES_WEIGHTS_REGISTER_2 */ "", 15700 /* DCH_PIPES_WEIGHTS_REGISTER_3 */ "", 15701 /* DCH_PRG_CELL_CNT_0 */ "", 15702 /* DCH_PRG_CELL_CNT_1 */ "", 15703 /* DCH_PRG_CELL_CNT_2 */ "", 15704 /* DCH_PRIORITY_TRANSLATION */ "", 15705 /* DCH_PROGRAMMABLE_CELLS_COUNTER_1 */ "", 15706 /* DCH_PROGRAMMABLE_CELLS_COUNTER_2 */ "", 15707 /* DCH_PROGRAMMABLE_CELLS_COUNTER_P */ "", 15708 /* DCH_PROGRAMMABLE_CELLS_COUNTER_S */ "", 15709 /* DCH_PROGRAMMABLE_DATA_CELL_COUNTER_0 */ "", 15710 /* DCH_PROGRAMMABLE_DATA_CELL_COUNTER_1 */ "", 15711 /* DCH_PROGRAMMABLE_DATA_CELL_COUNTER_2 */ "", 15712 /* DCH_PROGRAMMABLE_DATA_CELL_COUNTER_MASK_0 */ "", 15713 /* DCH_PROGRAMMABLE_DATA_CELL_COUNTER_MASK_1 */ "", 15714 /* DCH_PROGRAMMABLE_DATA_CELL_COUNTER_MASK_2 */ "", 15715 /* DCH_RATE_LIMITER */ "", 15716 /* DCH_REG_0050 */ "", 15717 /* DCH_REG_0051 */ "", 15718 /* DCH_REG_0052 */ "", 15719 /* DCH_REG_0054 */ "", 15720 /* DCH_REG_0055 */ "", 15721 /* DCH_REG_0058 */ "", 15722 /* DCH_REG_0060 */ "", 15723 /* DCH_REG_0061 */ "", 15724 /* DCH_REG_0062 */ "", 15725 /* DCH_REG_0063 */ "", 15726 /* DCH_REG_0064 */ "", 15727 /* DCH_REG_0075 */ "", 15728 /* DCH_REG_0077 */ "", 15729 /* DCH_REG_0091 */ "", 15730 /* DCH_REG_0094 */ "", 15731 /* DCH_REG_0103 */ "", 15732 /* DCH_REG_0107 */ "", 15733 /* DCH_REG_0108 */ "", 15734 /* DCH_REG_0109 */ "", 15735 /* DCH_REG_0110 */ "", 15736 /* DCH_REG_0111 */ "", 15737 /* DCH_REG_0112 */ "", 15738 /* DCH_REG_0113 */ "", 15739 /* DCH_REG_0114 */ "", 15740 /* DCH_REG_0115 */ "", 15741 /* DCH_REG_0116 */ "", 15742 /* DCH_REG_0117 */ "", 15743 /* DCH_REG_0196 */ "", 15744 /* DCH_REG_0210 */ "", 15745 /* DCH_REG_0212 */ "", 15746 /* DCH_REG_0214 */ "", 15747 /* DCH_REG_005A */ "", 15748 /* DCH_REG_005B */ "", 15749 /* DCH_REG_005C */ "", 15750 /* DCH_REG_005D */ "", 15751 /* DCH_REG_00ED */ "", 15752 /* DCH_REG_00EE */ "", 15753 /* DCH_REG_00EF */ "", 15754 /* DCH_REG_00F0 */ "", 15755 /* DCH_REG_00F1 */ "", 15756 /* DCH_REG_00F3 */ "", 15757 /* DCH_REG_00F5 */ "", 15758 /* DCH_REG_010A */ "", 15759 /* DCH_REG_010D */ "", 15760 /* DCH_REG_010E */ "", 15761 /* DCH_REG_019C */ "", 15762 /* DCH_REG_01A2 */ "", 15763 /* DCH_REG_01A8 */ "", 15764 /* DCH_REG_01BE */ "", 15765 /* DCH_REG_01BF */ "", 15766 /* DCH_REG_01C0 */ "", 15767 /* DCH_REG_01DE */ "", 15768 /* DCH_REG_01EA */ "", 15769 /* DCH_REG_01ED */ "", 15770 /* DCH_REG_01F3 */ "", 15771 /* DCH_REG_01F9 */ "", 15772 /* DCH_REG_01FF */ "", 15773 /* DCH_REMOTE_PRI_PIPE_IDX */ "", 15774 /* DCH_REMOTE_SEC_PIPE_IDX */ "", 15775 /* DCH_RESERVED_MIRROR_ADDR */ "", 15776 /* DCH_RESERVED_MTCD */ "", 15777 /* DCH_RESERVED_MTCP */ "", 15778 /* DCH_RESERVED_PCMI_2 */ "", 15779 /* DCH_RESERVED_PCMI_4 */ "", 15780 /* DCH_RESERVED_PCMI_2_S */ "", 15781 /* DCH_RESERVED_PCMI_2_T */ "", 15782 /* DCH_RESERVED_PCMI_4_S */ "", 15783 /* DCH_RESERVED_PCMI_4_T */ "", 15784 /* DCH_RESERVED_SPARE_0 */ "", 15785 /* DCH_RESERVED_SPARE_1 */ "", 15786 /* DCH_RESERVED_SPARE_2 */ "", 15787 /* DCH_RESERVED_SPARE_3 */ "", 15788 /* DCH_SBUS_BROADCAST_ID */ "", 15789 /* DCH_SBUS_LAST_IN_CHAIN */ "", 15790 /* DCH_SPARE_REGISTER_3 */ "", 15791 /* DCH_STAT_ROUT_TBL_0 */ "", 15792 /* DCH_STAT_ROUT_TBL_1 */ "", 15793 /* DCH_STAT_ROUT_TBL_2 */ "", 15794 /* DCH_STAT_ROUT_TBL_3 */ "", 15795 /* DCH_STAT_ROUT_TBL_4 */ "", 15796 /* DCH_STAT_ROUT_TBL_5 */ "", 15797 /* DCH_STAT_ROUT_TBL_6 */ "", 15798 /* DCH_STAT_ROUT_TBL_7 */ "", 15799 /* DCH_TDM_PRIORITY */ "", 15800 /* DCH_THREE_PIPES_BMP */ "", 15801 /* DCH_TWO_PIPES_BMP */ "", 15802 /* DCH_TX_CPU_CELL_CNT */ "", 15803 /* DCH_TX_CPU_CELL_DATA */ "", 15804 /* DCH_TX_CPU_CELL_HEADER */ "", 15805 /* DCH_TX_CPU_CELL_INFO */ "", 15806 /* DCH_TX_CPU_CELL_TRG */ "", 15807 /* DCH_TYPE_ERR_DROP_CNT */ "", 15808 /* DCH_UNREACH_DEST */ "", 15809 /* DCH_UNREACH_DEST_CNT */ "", 15810 /* DCH_UN_EXP_DISC_CNT_3 */ "", 15811 /* DCH_UN_EXP_DISC_CNT_2_PN */ "", 15812 /* DCH_UN_EXP_DISC_CNT_2_P_N */ "", 15813 /* DCH_UN_EXP_DISC_CNT_3_PN */ "", 15814 /* DCH_UN_EXP_DISC_CNT_3_P_N */ "", 15815 /* DCH_UN_EXP_DISC_CNT_PN */ "", 15816 /* DCH_UN_EXP_DISC_CNT_P_N */ "", 15817 /* DCH_UN_REACH_DEST */ "", 15818 /* DCH_UN_REACH_DEST_0_P */ "", 15819 /* DCH_UN_REACH_DEST_0_S */ "", 15820 /* DCH_USE_MC_CELL_PRIO_BMP */ "", 15821 /* DCH_WFQ_DYN_WEIGHT_THD_REGISTE */ "", 15822 /* DCL_ALM_FULL_P */ "", 15823 /* DCL_CCP_0_DSCRD_CNT */ "", 15824 /* DCL_CCP_0_ILLEGAL_CELLS_DATA */ "", 15825 /* DCL_CCP_0_PROGRAMMABLE_CELLS_COUNTER */ "", 15826 /* DCL_CCP_1_DSCRD_CNT */ "", 15827 /* DCL_CCP_1_ILLEGAL_CELLS_DATA */ "", 15828 /* DCL_CCP_1_PROGRAMMABLE_CELLS_COUNTER */ "", 15829 /* DCL_CCP_CONFIGURATIONS */ "", 15830 /* DCL_CCP_FIFOS_WATER_MARK */ "", 15831 /* DCL_CONNECTIVITY_LINKS_EVENTS */ "", 15832 /* DCL_CONNECTIVITY_LINK_0 */ "", 15833 /* DCL_CONNECTIVITY_LINK_1 */ "", 15834 /* DCL_CONNECTIVITY_LINK_2 */ "", 15835 /* DCL_CONNECTIVITY_LINK_3 */ "", 15836 /* DCL_CONNECTIVITY_LINK_4 */ "", 15837 /* DCL_CONNECTIVITY_LINK_5 */ "", 15838 /* DCL_CONNECTIVITY_LINK_6 */ "", 15839 /* DCL_CONNECTIVITY_LINK_7 */ "", 15840 /* DCL_CONNECTIVITY_LINK_8 */ "", 15841 /* DCL_CONNECTIVITY_LINK_9 */ "", 15842 /* DCL_CONNECTIVITY_LINK_10 */ "", 15843 /* DCL_CONNECTIVITY_LINK_11 */ "", 15844 /* DCL_CONNECTIVITY_LINK_12 */ "", 15845 /* DCL_CONNECTIVITY_LINK_13 */ "", 15846 /* DCL_CONNECTIVITY_LINK_14 */ "", 15847 /* DCL_CONNECTIVITY_LINK_15 */ "", 15848 /* DCL_CONNECTIVITY_LINK_16 */ "", 15849 /* DCL_CONNECTIVITY_LINK_17 */ "", 15850 /* DCL_CONNECTIVITY_LINK_18 */ "", 15851 /* DCL_CONNECTIVITY_LINK_19 */ "", 15852 /* DCL_CONNECTIVITY_LINK_20 */ "", 15853 /* DCL_CONNECTIVITY_LINK_21 */ "", 15854 /* DCL_CONNECTIVITY_LINK_22 */ "", 15855 /* DCL_CONNECTIVITY_LINK_23 */ "", 15856 /* DCL_CONNECTIVITY_LINK_24 */ "", 15857 /* DCL_CONNECTIVITY_LINK_25 */ "", 15858 /* DCL_CONNECTIVITY_LINK_26 */ "", 15859 /* DCL_CONNECTIVITY_LINK_27 */ "", 15860 /* DCL_CONNECTIVITY_LINK_28 */ "", 15861 /* DCL_CONNECTIVITY_LINK_29 */ "", 15862 /* DCL_CONNECTIVITY_LINK_30 */ "", 15863 /* DCL_CONNECTIVITY_LINK_31 */ "", 15864 /* DCL_CONNECTIVITY_LINK_32 */ "", 15865 /* DCL_CONNECTIVITY_LINK_33 */ "", 15866 /* DCL_CONNECTIVITY_LINK_34 */ "", 15867 /* DCL_CONNECTIVITY_LINK_35 */ "", 15868 /* DCL_CPU_CELL_CNT */ "", 15869 /* DCL_CPU_CELL_FIFO_STATUS */ "", 15870 /* DCL_CPU_DATA_CELL_0 */ "", 15871 /* DCL_CPU_DATA_CELL_1 */ "", 15872 /* DCL_CPU_DATA_CELL_2 */ "", 15873 /* DCL_CPU_DATA_CELL_3 */ "", 15874 /* DCL_CPU_DATA_CELL_4 */ "", 15875 /* DCL_DATA_CRC_ERR_CNT */ "", 15876 /* DCL_DCL_DROPPED_P_0_CNT_P */ "", 15877 /* DCL_DCL_DROPPED_P_0_CNT_S */ "", 15878 /* DCL_DCL_DROPPED_P_1_CNT_P */ "", 15879 /* DCL_DCL_DROPPED_P_1_CNT_S */ "", 15880 /* DCL_DCL_DROPPED_P_2_CNT_P */ "", 15881 /* DCL_DCL_DROPPED_P_2_CNT_S */ "", 15882 /* DCL_DCL_DROPPED_P_3_CNT_P */ "", 15883 /* DCL_DCL_DROPPED_P_3_CNT_S */ "", 15884 /* DCL_DCL_ENABLERS_REGISTER */ "", 15885 /* DCL_DCL_LLFC_TH */ "", 15886 /* DCL_DCL_TOTAL_IN_CELL_CNT_P */ "", 15887 /* DCL_DCL_TOTAL_IN_CELL_CNT_S */ "", 15888 /* DCL_DCL_TOTAL_IN_WORD_CNT_P */ "", 15889 /* DCL_DCL_TOTAL_IN_WORD_CNT_S */ "", 15890 /* DCL_DCL_TOTAL_OUT_CELL_CNT_P */ "", 15891 /* DCL_DCL_TOTAL_OUT_CELL_CNT_S */ "", 15892 /* DCL_DCL_TOTAL_OUT_WORD_CNT_P */ "", 15893 /* DCL_DCL_TOTAL_OUT_WORD_CNT_S */ "", 15894 /* DCL_DCMB_ALM_FULL_P */ "", 15895 /* DCL_DCMB_DCL_LLFC_TH */ "", 15896 /* DCL_DCMB_DROPPED_IP_PR_P_0_CNT */ "", 15897 /* DCL_DCMB_DROPPED_IP_PR_P_1_CNT */ "", 15898 /* DCL_DCMB_DROPPED_IP_PR_P_2_CNT */ "", 15899 /* DCL_DCMB_DROPPED_SRC_P_CNT */ "", 15900 /* DCL_DCMB_FIFO_DEPTH_TYPE */ "", 15901 /* DCL_DCMB_LINK_WEIGHT_CONFIG_THRESHOLDS */ "", 15902 /* DCL_DCMB_MAX_OCCUPANCY_FIFO_P */ "", 15903 /* DCL_DCMB_TOTAL_IN_CELL_P_CNT */ "", 15904 /* DCL_DCMB_TOTAL_OUT_CELL_P_CNT */ "", 15905 /* DCL_DCMB_TOTAL_OUT_WORD_P_CNT */ "", 15906 /* DCL_DCMB_TYPE_0_DRP_PRI_P */ "", 15907 /* DCL_DCMB_TYPE_0_GCI_TH_P */ "", 15908 /* DCL_DCMB_TYPE_0_RCI_TH_P */ "", 15909 /* DCL_DCMB_TYPE_1_DRP_PRI_P */ "", 15910 /* DCL_DCMB_TYPE_1_GCI_TH_P */ "", 15911 /* DCL_DCMB_TYPE_1_RCI_TH_P */ "", 15912 /* DCL_DCMB_UNPACKED_CELL_P_CNT */ "", 15913 /* DCL_DLOP_RR_ENABLERS */ "", 15914 /* DCL_DROPPED_IP_PR_P_0_CNT */ "", 15915 /* DCL_DROPPED_IP_PR_P_1_CNT */ "", 15916 /* DCL_DROPPED_IP_PR_P_2_CNT */ "", 15917 /* DCL_DROPPED_SRC_P_CNT */ "", 15918 /* DCL_DROP_CPU_CELL_CNT */ "", 15919 /* DCL_ECC_1B_ERR_ADDR */ "", 15920 /* DCL_ECC_1B_ERR_CNT */ "", 15921 /* DCL_ECC_2B_ERR_ADDR */ "", 15922 /* DCL_ECC_2B_ERR_CNT */ "", 15923 /* DCL_ECC_ERR_1B_INITIATE */ "", 15924 /* DCL_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 15925 /* DCL_ECC_ERR_2B_INITIATE */ "", 15926 /* DCL_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 15927 /* DCL_ECC_ERR_MONITOR_MEM_MASK */ "", 15928 /* DCL_ECC_INTERRUPT_REGISTER */ "", 15929 /* DCL_ECC_INTERRUPT_REGISTER_MASK */ "", 15930 /* DCL_ECC_INTERRUPT_REGISTER_TEST */ "", 15931 /* DCL_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 15932 /* DCL_ERROR_INITIATION_DATA */ "", 15933 /* DCL_FIFO_DEPTH_TYPE */ "", 15934 /* DCL_GEN_ERR_MEM */ "", 15935 /* DCL_GLOBAL_GENERAL_FE_CFG_1 */ "", 15936 /* DCL_GLOBAL_MEM_OPTIONS */ "", 15937 /* DCL_GTIMER_CONFIGURATION */ "", 15938 /* DCL_GTIMER_TRIGGER */ "", 15939 /* DCL_INDIRECT_COMMAND */ "", 15940 /* DCL_INDIRECT_COMMAND_ADDRESS */ "", 15941 /* DCL_INDIRECT_COMMAND_DATA_INCREMENT */ "", 15942 /* DCL_INDIRECT_COMMAND_RD_DATA */ "", 15943 /* DCL_INDIRECT_COMMAND_WIDE_MEM */ "", 15944 /* DCL_INDIRECT_COMMAND_WR_DATA */ "", 15945 /* DCL_INDIRECT_FORCE_BUBBLE */ "", 15946 /* DCL_INTERRUPT_MASK_REGISTER */ "", 15947 /* DCL_INTERRUPT_REGISTER */ "", 15948 /* DCL_INTERRUPT_REGISTER_TEST */ "", 15949 /* DCL_LINKS_WEIGHT_CONFIG */ "", 15950 /* DCL_LINKS_WEIGHT_CONFIG_0 */ "", 15951 /* DCL_LINKS_WEIGHT_CONFIG_1 */ "", 15952 /* DCL_LINKS_WEIGHT_CONFIG_2 */ "", 15953 /* DCL_LINKS_WEIGHT_CONFIG_3 */ "", 15954 /* DCL_LINKS_WEIGHT_CONFIG_4 */ "", 15955 /* DCL_LINKS_WEIGHT_CONFIG_5 */ "", 15956 /* DCL_LINKS_WEIGHT_CONFIG_6 */ "", 15957 /* DCL_LINKS_WEIGHT_CONFIG_7 */ "", 15958 /* DCL_LINKS_WEIGHT_CONFIG_8 */ "", 15959 /* DCL_LINKS_WEIGHT_CONFIG_9 */ "", 15960 /* DCL_LINKS_WEIGHT_CONFIG_10 */ "", 15961 /* DCL_LINKS_WEIGHT_CONFIG_11 */ "", 15962 /* DCL_LINKS_WEIGHT_CONFIG_12 */ "", 15963 /* DCL_LINKS_WEIGHT_CONFIG_13 */ "", 15964 /* DCL_LINKS_WEIGHT_CONFIG_14 */ "", 15965 /* DCL_LINKS_WEIGHT_CONFIG_15 */ "", 15966 /* DCL_LINKS_WEIGHT_CONFIG_P_0_GT_P_1 */ "", 15967 /* DCL_LINKS_WEIGHT_CONFIG_P_1_GT_P_0 */ "", 15968 /* DCL_LINK_CELL_PACKING_EN */ "", 15969 /* DCL_LINK_EN_SIMPLE_UNPACK */ "", 15970 /* DCL_LINK_LEVEL_FLOW_CONTROL_P */ "", 15971 /* DCL_LINK_LEVEL_FLOW_CONTROL_S */ "", 15972 /* DCL_LINK_TYPE */ "", 15973 /* DCL_LINK_TYPE_BMP_P */ "", 15974 /* DCL_LINK_TYPE_BMP_S */ "", 15975 /* DCL_LINK_WEIGHT_CONFIG_THRESHOLDS */ "", 15976 /* DCL_LLFC_RATE_CNT_P */ "", 15977 /* DCL_LLFC_RATE_CNT_S */ "", 15978 /* DCL_MAX_OCCUPANCY_FIFO_P */ "", 15979 /* DCL_MAX_OCUPANCY_FIFO_P */ "", 15980 /* DCL_MAX_OCUPANCY_FIFO_S */ "", 15981 /* DCL_MUL_SHAPER_RATE */ "", 15982 /* DCL_PARITY_ERR_ADDR */ "", 15983 /* DCL_PARITY_ERR_CNT */ "", 15984 /* DCL_PCP_ERR_INFORMATION */ "", 15985 /* DCL_PCP_VALIDITY_CHECK_ENABLERS */ "", 15986 /* DCL_PETRA_BMP */ "", 15987 /* DCL_PETRA_PIPE_BMP */ "", 15988 /* DCL_PIPES_MAP_EN */ "", 15989 /* DCL_PROGRAMMABLE_LINK_AND_TYPE_FOR_CELLS_COUNTER */ "", 15990 /* DCL_REG_0050 */ "", 15991 /* DCL_REG_0051 */ "", 15992 /* DCL_REG_0052 */ "", 15993 /* DCL_REG_0054 */ "", 15994 /* DCL_REG_0055 */ "", 15995 /* DCL_REG_0058 */ "", 15996 /* DCL_REG_0100 */ "", 15997 /* DCL_REG_0101 */ "", 15998 /* DCL_REG_0103 */ "", 15999 /* DCL_REG_0105 */ "", 16000 /* DCL_REG_0108 */ "", 16001 /* DCL_REG_0118 */ "", 16002 /* DCL_REG_0120 */ "", 16003 /* DCL_REG_0121 */ "", 16004 /* DCL_REG_0125 */ "", 16005 /* DCL_REG_0240 */ "", 16006 /* DCL_REG_005A */ "", 16007 /* DCL_REG_005B */ "", 16008 /* DCL_REG_005C */ "", 16009 /* DCL_REG_00A2 */ "", 16010 /* DCL_REG_00A3 */ "", 16011 /* DCL_REG_00A6 */ "", 16012 /* DCL_REG_00A9 */ "", 16013 /* DCL_REG_00AA */ "", 16014 /* DCL_REG_00AE */ "", 16015 /* DCL_REG_011A */ "", 16016 /* DCL_REG_011D */ "", 16017 /* DCL_REG_023E */ "", 16018 /* DCL_REMOTE_PRI_PIPE_IDX */ "", 16019 /* DCL_REMOTE_SEC_PIPE_IDX */ "", 16020 /* DCL_RESERVED_MIRROR_ADDR */ "", 16021 /* DCL_RESERVED_MTCP */ "", 16022 /* DCL_RESERVED_PCMI_0 */ "", 16023 /* DCL_RESERVED_PCMI_1 */ "", 16024 /* DCL_RESERVED_PCMI_0_S */ "", 16025 /* DCL_RESERVED_PCMI_0_T */ "", 16026 /* DCL_RESERVED_PCMI_1_S */ "", 16027 /* DCL_RESERVED_PCMI_1_T */ "", 16028 /* DCL_RESERVED_SPARE_0 */ "", 16029 /* DCL_RESERVED_SPARE_1 */ "", 16030 /* DCL_RESERVED_SPARE_2 */ "", 16031 /* DCL_RESERVED_SPARE_3 */ "", 16032 /* DCL_SBUS_BROADCAST_ID */ "", 16033 /* DCL_SBUS_LAST_IN_CHAIN */ "", 16034 /* DCL_SHAPER_AND_WFQ_CFG */ "", 16035 /* DCL_SPARE_REGISTER_3 */ "", 16036 /* DCL_TAG_PAR_ERR_CNT */ "", 16037 /* DCL_TAG_PAR_ERR_CNT_P */ "", 16038 /* DCL_THREE_PIPES_BMP */ "", 16039 /* DCL_TOTAL_IN_CELL_P_CNT */ "", 16040 /* DCL_TOTAL_OUT_CELL_P_CNT */ "", 16041 /* DCL_TOTAL_OUT_WORD_P_CNT */ "", 16042 /* DCL_TRANSMIT_CELL_OUTPUT_LINK_NUMBER */ "", 16043 /* DCL_TRANSMIT_DATA_CELL_TRIGGER */ "", 16044 /* DCL_TWO_PIPES_BMP */ "", 16045 /* DCL_TYPE_01_RCI_TH_P */ "", 16046 /* DCL_TYPE_01_RCI_TH_S */ "", 16047 /* DCL_TYPE_0_ALM_FULL_P */ "", 16048 /* DCL_TYPE_0_ALM_FULL_S */ "", 16049 /* DCL_TYPE_0_DRP_PP */ "", 16050 /* DCL_TYPE_0_DRP_PRI_P */ "", 16051 /* DCL_TYPE_0_DRP_PS */ "", 16052 /* DCL_TYPE_0_GCI_TH_P */ "", 16053 /* DCL_TYPE_0_GCI_TH_S */ "", 16054 /* DCL_TYPE_0_RCI_TH_P */ "", 16055 /* DCL_TYPE_1_ALM_FULL_P */ "", 16056 /* DCL_TYPE_1_ALM_FULL_S */ "", 16057 /* DCL_TYPE_1_DRP_PP */ "", 16058 /* DCL_TYPE_1_DRP_PRI_P */ "", 16059 /* DCL_TYPE_1_DRP_PS */ "", 16060 /* DCL_TYPE_1_GCI_TH_P */ "", 16061 /* DCL_TYPE_1_GCI_TH_S */ "", 16062 /* DCL_TYPE_1_RCI_TH_P */ "", 16063 /* DCL_UNPACKED_CELL_P_CNT */ "", 16064 /* DCMA_DCLM_FLOW_CNTROL_CNT */ "", 16065 /* DCMA_DCLU_FLOW_CNTROL_CNT */ "", 16066 /* DCMA_DCMMA_DCM_MAX_OCUPP_SECONDARY */ "", 16067 /* DCMA_DCMMA_DROPPED_IP_0 */ "", 16068 /* DCMA_DCMMA_DROPPED_IP_1 */ "", 16069 /* DCMA_DCMMA_DROPPED_IP_2 */ "", 16070 /* DCMA_DCMMA_DROPPED_IP_3 */ "", 16071 /* DCMA_DCMMA_DROPPED_TOTAL_CNT */ "", 16072 /* DCMA_DCMMA_GCI_TH */ "", 16073 /* DCMA_DCMMA_PRIORITY_DROP_THRESHOLD */ "", 16074 /* DCMA_DCMMA_TOTAL_IN_CELL_CNT_0 */ "", 16075 /* DCMA_DCMMA_TOTAL_IN_CELL_CNT_1 */ "", 16076 /* DCMA_DCMM_ALM_FULL_0 */ "", 16077 /* DCMA_DCMUA_DCM_MAX_OCUPP_PRIMERY */ "", 16078 /* DCMA_DCMUA_DROPPED_IP_0 */ "", 16079 /* DCMA_DCMUA_DROPPED_IP_1 */ "", 16080 /* DCMA_DCMUA_DROPPED_IP_2 */ "", 16081 /* DCMA_DCMUA_DROPPED_IP_3 */ "", 16082 /* DCMA_DCMUA_DROPPED_TOTAL_CNT */ "", 16083 /* DCMA_DCMUA_GCI_TH */ "", 16084 /* DCMA_DCMUA_PRIORITY_DROP_THRESHOLD */ "", 16085 /* DCMA_DCMUA_TOTAL_IN_CELL_CNT_0 */ "", 16086 /* DCMA_DCMUA_TOTAL_IN_CELL_CNT_1 */ "", 16087 /* DCMA_DCMU_ALM_FULL_0 */ "", 16088 /* DCMA_DCM_ENABLERS_REGISTER */ "", 16089 /* DCMA_ECC_1B_ERR_ADDR */ "", 16090 /* DCMA_ECC_1B_ERR_CNT */ "", 16091 /* DCMA_ECC_2B_ERR_ADDR */ "", 16092 /* DCMA_ECC_2B_ERR_CNT */ "", 16093 /* DCMA_ECC_ERR_MONITOR_MEM_MASK_A */ "", 16094 /* DCMA_ERROR_INITIATION_DATA */ "", 16095 /* DCMA_GEN_ERR_MEM_A */ "", 16096 /* DCMA_GTIMER_CONFIGURATION */ "", 16097 /* DCMA_GTIMER_TRIGGER */ "", 16098 /* DCMA_INTERRUPT_MASK_REGISTER */ "", 16099 /* DCMA_INTERRUPT_REGISTER */ "", 16100 /* DCMA_PARITY_ERR_ADDR */ "", 16101 /* DCMA_PARITY_ERR_CNT */ "", 16102 /* DCMA_REG_0050 */ "", 16103 /* DCMA_REG_0051 */ "", 16104 /* DCMA_REG_0052 */ "", 16105 /* DCMA_REG_0054 */ "", 16106 /* DCMA_REG_0055 */ "", 16107 /* DCMA_REG_0058 */ "", 16108 /* DCMA_REG_0084 */ "", 16109 /* DCMA_REG_0085 */ "", 16110 /* DCMA_REG_0086 */ "", 16111 /* DCMA_REG_0087 */ "", 16112 /* DCMA_REG_005A */ "", 16113 /* DCMA_REG_005B */ "", 16114 /* DCMA_REG_005D */ "", 16115 /* DCMA_SPARE_REGISTER_3 */ "", 16116 /* DCMB_DCLM_FLOW_CNTROL_CNT */ "", 16117 /* DCMB_DCLU_FLOW_CNTROL_CNT */ "", 16118 /* DCMB_DCMMBLM_FULL_0 */ "", 16119 /* DCMB_DCMMB_DCM_MAX_OCUPP_SECONDARY */ "", 16120 /* DCMB_DCMMB_DROPPED_IP_0 */ "", 16121 /* DCMB_DCMMB_DROPPED_IP_1 */ "", 16122 /* DCMB_DCMMB_DROPPED_IP_2 */ "", 16123 /* DCMB_DCMMB_DROPPED_IP_3 */ "", 16124 /* DCMB_DCMMB_DROPPED_TOTAL_CNT */ "", 16125 /* DCMB_DCMMB_GCI_TH */ "", 16126 /* DCMB_DCMMB_PRIORITY_DROP_THRESHOLD */ "", 16127 /* DCMB_DCMMB_TOTAL_IN_CELL_CNT_0 */ "", 16128 /* DCMB_DCMMB_TOTAL_IN_CELL_CNT_1 */ "", 16129 /* DCMB_DCMUBLM_FULL_0 */ "", 16130 /* DCMB_DCMUB_DCM_MAX_OCUPP_PRIMERY */ "", 16131 /* DCMB_DCMUB_DROPPED_IP_0 */ "", 16132 /* DCMB_DCMUB_DROPPED_IP_1 */ "", 16133 /* DCMB_DCMUB_DROPPED_IP_2 */ "", 16134 /* DCMB_DCMUB_DROPPED_IP_3 */ "", 16135 /* DCMB_DCMUB_DROPPED_TOTAL_CNT */ "", 16136 /* DCMB_DCMUB_GCI_TH */ "", 16137 /* DCMB_DCMUB_PRIORITY_DROP_THRESHOLD */ "", 16138 /* DCMB_DCMUB_TOTAL_IN_CELL_CNT_0 */ "", 16139 /* DCMB_DCMUB_TOTAL_IN_CELL_CNT_1 */ "", 16140 /* DCMB_DCM_ENABLERS_REGISTER */ "", 16141 /* DCMB_ECC_1B_ERR_ADDR */ "", 16142 /* DCMB_ECC_1B_ERR_CNT */ "", 16143 /* DCMB_ECC_2B_ERR_ADDR */ "", 16144 /* DCMB_ECC_2B_ERR_CNT */ "", 16145 /* DCMB_ECC_ERR_MONITOR_MEM_MASK_A */ "", 16146 /* DCMB_ERROR_INITIATION_DATA */ "", 16147 /* DCMB_GEN_ERR_MEM_A */ "", 16148 /* DCMB_GTIMER_CONFIGURATION */ "", 16149 /* DCMB_GTIMER_TRIGGER */ "", 16150 /* DCMB_INTERRUPT_MASK_REGISTER */ "", 16151 /* DCMB_INTERRUPT_REGISTER */ "", 16152 /* DCMB_PARITY_ERR_ADDR */ "", 16153 /* DCMB_PARITY_ERR_CNT */ "", 16154 /* DCMB_REG_0050 */ "", 16155 /* DCMB_REG_0051 */ "", 16156 /* DCMB_REG_0052 */ "", 16157 /* DCMB_REG_0054 */ "", 16158 /* DCMB_REG_0055 */ "", 16159 /* DCMB_REG_0058 */ "", 16160 /* DCMB_REG_0084 */ "", 16161 /* DCMB_REG_0085 */ "", 16162 /* DCMB_REG_0086 */ "", 16163 /* DCMB_REG_0087 */ "", 16164 /* DCMB_REG_005A */ "", 16165 /* DCMB_REG_005B */ "", 16166 /* DCMB_REG_005D */ "", 16167 /* DCMB_SPARE_REGISTER_3 */ "", 16168 /* DCMC_CIG_ENABLERS_REGISTER */ "", 16169 /* DCMC_CIG_FORCE_CTRL */ "", 16170 /* DCMC_CIG_LINK_FORCE_EN */ "", 16171 /* DCMC_DCM_ENABLERS_REGISTER */ "", 16172 /* DCMC_FIFO_COUNTER_CTRL */ "", 16173 /* DCMC_GLOBAL_GENERAL_FE_CFG_1 */ "", 16174 /* DCMC_GTIMER_CONFIGURATION */ "", 16175 /* DCMC_GTIMER_TRIGGER */ "", 16176 /* DCMC_INTERRUPT_MASK_REGISTER */ "", 16177 /* DCMC_INTERRUPT_REGISTER */ "", 16178 /* DCMC_INTERRUPT_REGISTER_TEST */ "", 16179 /* DCMC_LINK_BUNDLE_0_TH_0 */ "", 16180 /* DCMC_LINK_BUNDLE_0_TH_1 */ "", 16181 /* DCMC_LINK_BUNDLE_0_TH_2 */ "", 16182 /* DCMC_LINK_BUNDLE_1_TH_0 */ "", 16183 /* DCMC_LINK_BUNDLE_1_TH_1 */ "", 16184 /* DCMC_LINK_BUNDLE_1_TH_2 */ "", 16185 /* DCMC_LINK_BUNDLE_2_TH_0 */ "", 16186 /* DCMC_LINK_BUNDLE_2_TH_1 */ "", 16187 /* DCMC_LINK_BUNDLE_2_TH_2 */ "", 16188 /* DCMC_LINK_BUNDLE_3_TH_0 */ "", 16189 /* DCMC_LINK_BUNDLE_3_TH_1 */ "", 16190 /* DCMC_LINK_BUNDLE_3_TH_2 */ "", 16191 /* DCMC_LINK_BUNDLE_BMP_0 */ "", 16192 /* DCMC_LINK_BUNDLE_BMP_1 */ "", 16193 /* DCMC_LINK_BUNDLE_BMP_2 */ "", 16194 /* DCMC_LINK_BUNDLE_BMP_3 */ "", 16195 /* DCMC_LINK_LOAD_COUNT_MODE_PASS_WMARK_P_0 */ "", 16196 /* DCMC_LINK_LOAD_COUNT_MODE_PASS_WMARK_P_1 */ "", 16197 /* DCMC_LINK_LOAD_COUNT_MODE_PASS_WMARK_P_2 */ "", 16198 /* DCMC_LINK_LOAD_COUNT_MODE_PIPE_0 */ "", 16199 /* DCMC_LINK_LOAD_COUNT_MODE_PIPE_1 */ "", 16200 /* DCMC_LINK_LOAD_COUNT_MODE_PIPE_2 */ "", 16201 /* DCMC_LINK_LOAD_TH */ "", 16202 /* DCMC_LINK_LOAD_TH_PASS_P */ "", 16203 /* DCMC_LINK_LOAD_TH_PASS_S */ "", 16204 /* DCMC_LINK_LOAD_TH_PASS_WMARK_P */ "", 16205 /* DCMC_LINK_LOAD_TH_PASS_WMARK_S */ "", 16206 /* DCMC_MAX_FABRIC_GCI_WMARK */ "", 16207 /* DCMC_MAX_FABRIC_RCI_WMARK */ "", 16208 /* DCMC_RCI_CNT_MAX_SIZE */ "", 16209 /* DCMC_REG_0000 */ "", 16210 /* DCMC_REG_0010 */ "", 16211 /* DCMC_REG_0050 */ "", 16212 /* DCMC_REG_0051 */ "", 16213 /* DCMC_REG_0052 */ "", 16214 /* DCMC_REG_0054 */ "", 16215 /* DCMC_REG_0055 */ "", 16216 /* DCMC_REG_005A */ "", 16217 /* DCMC_REG_005B */ "", 16218 /* DCMC_REG_00AF */ "", 16219 /* DCMC_REG_00B0 */ "", 16220 /* DCMC_REG_00B1 */ "", 16221 /* DCMC_REG_00B2 */ "", 16222 /* DCMC_REG_00B3 */ "", 16223 /* DCMC_REG_00B4 */ "", 16224 /* DCMC_REG_00B5 */ "", 16225 /* DCMC_REG_00B6 */ "", 16226 /* DCMC_REG_00B7 */ "", 16227 /* DCMC_REG_00B8 */ "", 16228 /* DCMC_REG_00B9 */ "", 16229 /* DCMC_REG_00BA */ "", 16230 /* DCMC_REPEATER_ROUTING_TABLE_0 */ "", 16231 /* DCMC_REPEATER_ROUTING_TABLE_1 */ "", 16232 /* DCMC_REPEATER_ROUTING_TABLE_2 */ "", 16233 /* DCMC_REPEATER_ROUTING_TABLE_3 */ "", 16234 /* DCMC_REPEATER_ROUTING_TABLE_4 */ "", 16235 /* DCMC_REPEATER_ROUTING_TABLE_5 */ "", 16236 /* DCMC_REPEATER_ROUTING_TABLE_6 */ "", 16237 /* DCMC_REPEATER_ROUTING_TABLE_7 */ "", 16238 /* DCMC_REPEATER_ROUTING_TABLE_8 */ "", 16239 /* DCMC_REPEATER_ROUTING_TABLE_9 */ "", 16240 /* DCMC_REPEATER_ROUTING_TABLE_10 */ "", 16241 /* DCMC_REPEATER_ROUTING_TABLE_11 */ "", 16242 /* DCMC_REPEATER_ROUTING_TABLE_12 */ "", 16243 /* DCMC_REPEATER_ROUTING_TABLE_13 */ "", 16244 /* DCMC_REPEATER_ROUTING_TABLE_14 */ "", 16245 /* DCMC_REPEATER_ROUTING_TABLE_15 */ "", 16246 /* DCMC_REPEATER_ROUTING_TABLE_16 */ "", 16247 /* DCMC_REPEATER_ROUTING_TABLE_17 */ "", 16248 /* DCMC_REPEATER_ROUTING_TABLE_18 */ "", 16249 /* DCMC_REPEATER_ROUTING_TABLE_19 */ "", 16250 /* DCMC_REPEATER_ROUTING_TABLE_20 */ "", 16251 /* DCMC_REPEATER_ROUTING_TABLE_21 */ "", 16252 /* DCMC_REPEATER_ROUTING_TABLE_22 */ "", 16253 /* DCMC_REPEATER_ROUTING_TABLE_23 */ "", 16254 /* DCMC_REPEATER_ROUTING_TABLE_24 */ "", 16255 /* DCMC_REPEATER_ROUTING_TABLE_25 */ "", 16256 /* DCMC_REPEATER_ROUTING_TABLE_26 */ "", 16257 /* DCMC_REPEATER_ROUTING_TABLE_27 */ "", 16258 /* DCMC_REPEATER_ROUTING_TABLE_28 */ "", 16259 /* DCMC_REPEATER_ROUTING_TABLE_29 */ "", 16260 /* DCMC_REPEATER_ROUTING_TABLE_30 */ "", 16261 /* DCMC_REPEATER_ROUTING_TABLE_31 */ "", 16262 /* DCMC_REPEATER_ROUTING_TABLE_32 */ "", 16263 /* DCMC_REPEATER_ROUTING_TABLE_33 */ "", 16264 /* DCMC_REPEATER_ROUTING_TABLE_34 */ "", 16265 /* DCMC_REPEATER_ROUTING_TABLE_35 */ "", 16266 /* DCMC_RESERVED_MIRROR_ADDR */ "", 16267 /* DCMC_RESERVED_SPARE_0 */ "", 16268 /* DCMC_RESERVED_SPARE_1 */ "", 16269 /* DCMC_RESERVED_SPARE_2 */ "", 16270 /* DCMC_RESERVED_SPARE_3 */ "", 16271 /* DCMC_SBUS_BROADCAST_ID */ "", 16272 /* DCMC_SBUS_LAST_IN_CHAIN */ "", 16273 /* DCMC_SPARE_REGISTER_3 */ "", 16274 /* DCML_AUTO_DOC_NAME_1 */ "", 16275 /* DCML_AUTO_DOC_NAME_34 */ "", 16276 /* DCML_AUTO_DOC_NAME_37 */ "", 16277 /* DCML_AUTO_DOC_NAME_38 */ "", 16278 /* DCML_AUTO_DOC_NAME_47 */ "", 16279 /* DCML_AUTO_DOC_NAME_48 */ "", 16280 /* DCML_AUTO_DOC_NAME_49 */ "", 16281 /* DCML_CCML_CONFIGURATIONS */ "", 16282 /* DCML_CDMA_LP_CELLS_DISCARD_CNT */ "", 16283 /* DCML_CDMB_LP_CELLS_DISCARD_CNT */ "", 16284 /* DCML_CDMC_LP_CELLS_DISCARD_CNT */ "", 16285 /* DCML_CDMD_LP_CELLS_DISCARD_CNT */ "", 16286 /* DCML_CDME_LP_CELLS_DISCARD_CNT */ "", 16287 /* DCML_CDMF_LP_CELLS_DISCARD_CNT */ "", 16288 /* DCML_CDMG_LP_CELLS_DISCARD_CNT */ "", 16289 /* DCML_CDMH_LP_CELLS_DISCARD_CNT */ "", 16290 /* DCML_CDM_OVERFLOW_FIFO_NUMBER */ "", 16291 /* DCML_CPU_FORCE_MAC_LINK_IREADY */ "", 16292 /* DCML_CPU_SOURCE_CELL_DATA */ "", 16293 /* DCML_CPU_SOURCE_CELL_TRIGGER */ "", 16294 /* DCML_CTP_CREDIT_CELLS_CNT */ "", 16295 /* DCML_CTP_FS_CELLS_CNT */ "", 16296 /* DCML_CTP_INTERNAL_REACHABILITY_CELLS_CNT */ "", 16297 /* DCML_DCML_ENABLERS */ "", 16298 /* DCML_DCML_SEPARATION_REGISTER */ "", 16299 /* DCML_DFL_ECC_ERR_CFG */ "", 16300 /* DCML_ECC_1B_ERR_CNT */ "", 16301 /* DCML_ECC_2B_ERR_CNT */ "", 16302 /* DCML_ECC_ERR_1B_INITIATE */ "", 16303 /* DCML_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 16304 /* DCML_ECC_ERR_2B_INITIATE */ "", 16305 /* DCML_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 16306 /* DCML_ECC_INTERRUPT_REGISTER */ "", 16307 /* DCML_ECC_INTERRUPT_REGISTER_MASK */ "", 16308 /* DCML_ECC_INTERRUPT_REGISTER_TEST */ "", 16309 /* DCML_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 16310 /* DCML_ERROR_INITIATION_DATA */ "", 16311 /* DCML_FAP_GLOBAL_GENERAL_CFG_1 */ "", 16312 /* DCML_FBC_BANK_STAT */ "", 16313 /* DCML_FBC_BANK_STAT_DIFF */ "", 16314 /* DCML_FE_GLOBAL_GENERAL_CFG_1 */ "", 16315 /* DCML_FE_GLOBAL_GENERAL_CFG_2 */ "", 16316 /* DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER */ "", 16317 /* DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_MASK */ "", 16318 /* DCML_FPC_ALLOC_ERROR_INTERRUPT_REGISTER_TEST */ "", 16319 /* DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER */ "", 16320 /* DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_MASK */ "", 16321 /* DCML_FPC_FREE_ERROR_INTERRUPT_REGISTER_TEST */ "", 16322 /* DCML_GLOBAL_MEM_OPTIONS */ "", 16323 /* DCML_GTIMER_CONFIGURATION */ "", 16324 /* DCML_GTIMER_CYCLE */ "", 16325 /* DCML_INDIRECT_COMMAND */ "", 16326 /* DCML_INDIRECT_COMMAND_ADDRESS */ "", 16327 /* DCML_INDIRECT_COMMAND_DATA_INCREMENT */ "", 16328 /* DCML_INDIRECT_COMMAND_RD_DATA */ "", 16329 /* DCML_INDIRECT_COMMAND_WIDE_MEM */ "", 16330 /* DCML_INDIRECT_COMMAND_WR_DATA */ "", 16331 /* DCML_INDIRECT_FORCE_BUBBLE */ "", 16332 /* DCML_INTERRUPT_MASK_REGISTER */ "", 16333 /* DCML_INTERRUPT_REGISTER */ "", 16334 /* DCML_INTERRUPT_REGISTER_TEST */ "", 16335 /* DCML_MID_FIFOS_LP_WATER_MARK */ "", 16336 /* DCML_MID_FIFOS_SATTUS_CDMA */ "", 16337 /* DCML_MID_FIFOS_SATTUS_CDMAD */ "", 16338 /* DCML_MID_FIFOS_SATTUS_CDMAH */ "", 16339 /* DCML_MID_FIFOS_SATTUS_CDMB */ "", 16340 /* DCML_MID_FIFOS_SATTUS_CDMC */ "", 16341 /* DCML_MID_FIFOS_SATTUS_CDME */ "", 16342 /* DCML_MID_FIFOS_SATTUS_CDMF */ "", 16343 /* DCML_MID_FIFOS_SATTUS_CDMG */ "", 16344 /* DCML_PCMI_0 */ "", 16345 /* DCML_PCMI_1 */ "", 16346 /* DCML_PCMI_2 */ "", 16347 /* DCML_PCMI_3 */ "", 16348 /* DCML_PCMI_0_S */ "", 16349 /* DCML_PCMI_0_T */ "", 16350 /* DCML_PCMI_1_S */ "", 16351 /* DCML_PCMI_1_T */ "", 16352 /* DCML_PCMI_2_S */ "", 16353 /* DCML_PCMI_2_T */ "", 16354 /* DCML_PCMI_3_S */ "", 16355 /* DCML_PCMI_3_T */ "", 16356 /* DCML_PIPES_MAPPING_EN */ "", 16357 /* DCML_PROGRAMMABLE_MID_FIFOS_WATER_MARK */ "", 16358 /* DCML_PROGRAMMABLE_MID_FIFO_NUMBER_FOR_WATER_MARK */ "", 16359 /* DCML_REMOTE_PRI_PIPE_IDX */ "", 16360 /* DCML_REMOTE_SEC_PIPE_IDX */ "", 16361 /* DCML_RESERVED_MIRROR_ADDR */ "", 16362 /* DCML_RESERVED_MTCD */ "", 16363 /* DCML_RESERVED_MTCP */ "", 16364 /* DCML_RESERVED_SPARE_0 */ "", 16365 /* DCML_RESERVED_SPARE_1 */ "", 16366 /* DCML_RESERVED_SPARE_2 */ "", 16367 /* DCML_RESERVED_SPARE_3 */ "", 16368 /* DCML_SBUS_BROADCAST_ID */ "", 16369 /* DCML_SBUS_LAST_IN_CHAIN */ "", 16370 /* DCML_THREE_PIPES_BMP */ "", 16371 /* DCML_TOTAL_OUT_CELL_P_CNT */ "", 16372 /* DCML_TOTAL_OUT_CPU_CAPTURE_CELL_CNT */ "", 16373 /* DCML_TOTAL_OUT_CPU_TRANSMIT_CELL_CNT */ "", 16374 /* DCML_TOTAL_OUT_INBAND_CELL_CNT */ "", 16375 /* DCML_TOTAL_OUT_WORD_P_CNT */ "", 16376 /* DCML_TWO_PIPES_BMP */ "", 16377 /* DCML_TX_CPU_CELL_DATA_0 */ "", 16378 /* DCML_TX_CPU_CELL_DATA_1 */ "", 16379 /* DCML_TX_CPU_CELL_HEADER */ "", 16380 /* DCM_DCL_FLOW_CONTROL_CNT_P */ "", 16381 /* DCM_DCM_ENABLERS_REGISTER */ "", 16382 /* DCM_DCM_MAX_OCUP_P */ "", 16383 /* DCM_DROP_IP_PRI_P_0_CNT */ "", 16384 /* DCM_DROP_IP_PRI_P_1_CNT */ "", 16385 /* DCM_DROP_IP_PRI_P_2_CNT */ "", 16386 /* DCM_DROP_TOTAL_P_CNT */ "", 16387 /* DCM_DYN_PIPES_WEIGHTS_REGISTER */ "", 16388 /* DCM_DYN_WFQ_WEIGHT_THD_REGISTER */ "", 16389 /* DCM_ECC_1B_ERR_CNT */ "", 16390 /* DCM_ECC_2B_ERR_CNT */ "", 16391 /* DCM_ECC_ERR_1B_INITIATE */ "", 16392 /* DCM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 16393 /* DCM_ECC_ERR_2B_INITIATE */ "", 16394 /* DCM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 16395 /* DCM_ECC_INTERRUPT_REGISTER */ "", 16396 /* DCM_ECC_INTERRUPT_REGISTER_MASK */ "", 16397 /* DCM_ECC_INTERRUPT_REGISTER_TEST */ "", 16398 /* DCM_ERROR_INITIATION_DATA */ "", 16399 /* DCM_FIFOS_DEPTH_TYPE */ "", 16400 /* DCM_FIFOS_THRESHOLDS_P_TYPE_0 */ "", 16401 /* DCM_FIFOS_THRESHOLDS_P_TYPE_1 */ "", 16402 /* DCM_FIFO_TYPE */ "", 16403 /* DCM_GCI_TH_P_TYPE_0 */ "", 16404 /* DCM_GCI_TH_P_TYPE_1 */ "", 16405 /* DCM_GLOBAL_DCH_CAPTURE_CELLS_DCL */ "", 16406 /* DCM_GLOBAL_GENERAL_CFG_1 */ "", 16407 /* DCM_GLOBAL_GENERAL_FE_CFG_1 */ "", 16408 /* DCM_GLOBAL_MEM_OPTIONS */ "", 16409 /* DCM_GTIMER_CONFIGURATION */ "", 16410 /* DCM_GTIMER_TRIGGER */ "", 16411 /* DCM_INTERRUPT_MASK_REGISTER */ "", 16412 /* DCM_INTERRUPT_REGISTER */ "", 16413 /* DCM_INTERRUPT_REGISTER_TEST */ "", 16414 /* DCM_MC_LOW_PRIO_REP_THD_P_TYPE_0 */ "", 16415 /* DCM_MC_LOW_PRIO_REP_THD_P_TYPE_1 */ "", 16416 /* DCM_MC_LP_CELL_DRP_CNT_P */ "", 16417 /* DCM_PIPES_WEIGHTS_REGISTER */ "", 16418 /* DCM_PIPE_0_PRIORITY_DROP_THRESHOLD_TYPE */ "", 16419 /* DCM_PIPE_1_PRIORITY_DROP_THRESHOLD_TYPE */ "", 16420 /* DCM_PIPE_2_PRIORITY_DROP_THRESHOLD_TYPE */ "", 16421 /* DCM_RCI_TH_P_TYPE_0 */ "", 16422 /* DCM_RCI_TH_P_TYPE_1 */ "", 16423 /* DCM_REG_0100 */ "", 16424 /* DCM_REG_0103 */ "", 16425 /* DCM_RESERVED_MIRROR_ADDR */ "", 16426 /* DCM_RESERVED_MTCP */ "", 16427 /* DCM_RESERVED_PCMI_0 */ "", 16428 /* DCM_RESERVED_PCMI_1 */ "", 16429 /* DCM_RESERVED_PCMI_2 */ "", 16430 /* DCM_RESERVED_PCMI_4 */ "", 16431 /* DCM_RESERVED_PCMI_0_S */ "", 16432 /* DCM_RESERVED_PCMI_0_T */ "", 16433 /* DCM_RESERVED_PCMI_1_S */ "", 16434 /* DCM_RESERVED_PCMI_1_T */ "", 16435 /* DCM_RESERVED_PCMI_2_S */ "", 16436 /* DCM_RESERVED_PCMI_2_T */ "", 16437 /* DCM_RESERVED_PCMI_4_S */ "", 16438 /* DCM_RESERVED_PCMI_4_T */ "", 16439 /* DCM_RESERVED_SPARE_0 */ "", 16440 /* DCM_RESERVED_SPARE_1 */ "", 16441 /* DCM_RESERVED_SPARE_2 */ "", 16442 /* DCM_RESERVED_SPARE_3 */ "", 16443 /* DCM_SBUS_BROADCAST_ID */ "", 16444 /* DCM_SBUS_LAST_IN_CHAIN */ "", 16445 /* DCM_TOTAL_IN_CELL_CNT_PAB */ "", 16446 /* DCM_TOTAL_IN_CELL_CNT_PCD */ "", 16447 /* DCRCSS */ "", 16448 /* DDHA_ECC_1B_ERR_CNT */ "", 16449 /* DDHA_ECC_2B_ERR_CNT */ "", 16450 /* DDHA_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 16451 /* DDHA_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 16452 /* DDHA_ECC_INTERRUPT_REGISTER */ "", 16453 /* DDHA_ECC_INTERRUPT_REGISTER_MASK */ "", 16454 /* DDHA_ECC_INTERRUPT_REGISTER_TEST */ "", 16455 /* DDHA_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 16456 /* DDHA_ERROR_INITIATION_DATA */ "", 16457 /* DDHA_GTIMER_CONFIGURATION */ "", 16458 /* DDHA_GTIMER_CYCLE */ "", 16459 /* DDHA_INDIRECT_COMMAND */ "", 16460 /* DDHA_INDIRECT_COMMAND_ADDRESS */ "", 16461 /* DDHA_INDIRECT_COMMAND_RD_DATA */ "", 16462 /* DDHA_INDIRECT_COMMAND_WR_DATA */ "", 16463 /* DDHA_INDIRECT_FORCE_BUBBLE */ "", 16464 /* DDHA_INDIRECT_WR_MASK */ "", 16465 /* DDHA_INTERRUPT_MASK_REGISTER */ "", 16466 /* DDHA_INTERRUPT_REGISTER */ "", 16467 /* DDHA_INTERRUPT_REGISTER_TEST */ "", 16468 /* DDHA_PCMI_0 */ "", 16469 /* DDHA_PCMI_1 */ "", 16470 /* DDHA_PCMI_2 */ "", 16471 /* DDHA_PCMI_3 */ "", 16472 /* DDHA_PCMI_4 */ "", 16473 /* DDHA_PCMI_0_S */ "", 16474 /* DDHA_PCMI_0_T */ "", 16475 /* DDHA_PCMI_1_S */ "", 16476 /* DDHA_PCMI_1_T */ "", 16477 /* DDHA_PCMI_2_S */ "", 16478 /* DDHA_PCMI_2_T */ "", 16479 /* DDHA_PCMI_3_S */ "", 16480 /* DDHA_PCMI_3_T */ "", 16481 /* DDHA_PCMI_4_S */ "", 16482 /* DDHA_PCMI_4_T */ "", 16483 /* DDHA_REG_0041 */ "", 16484 /* DDHA_REG_0098 */ "", 16485 /* DDHA_REG_0100 */ "", 16486 /* DDHA_REG_0101 */ "", 16487 /* DDHA_REG_0102 */ "", 16488 /* DDHA_REG_0103 */ "", 16489 /* DDHA_REG_0105 */ "", 16490 /* DDHA_REG_0106 */ "", 16491 /* DDHA_REG_0107 */ "", 16492 /* DDHA_REG_0108 */ "", 16493 /* DDHA_REG_0134 */ "", 16494 /* DDHA_REG_0154 */ "", 16495 /* DDHA_REG_0155 */ "", 16496 /* DDHA_REG_0156 */ "", 16497 /* DDHA_REG_0166 */ "", 16498 /* DDHA_REG_0176 */ "", 16499 /* DDHA_REG_0200 */ "", 16500 /* DDHA_REG_0201 */ "", 16501 /* DDHA_REG_0202 */ "", 16502 /* DDHA_REG_0203 */ "", 16503 /* DDHA_REG_0205 */ "", 16504 /* DDHA_REG_0206 */ "", 16505 /* DDHA_REG_0207 */ "", 16506 /* DDHA_REG_0208 */ "", 16507 /* DDHA_REG_0234 */ "", 16508 /* DDHA_REG_0254 */ "", 16509 /* DDHA_REG_0255 */ "", 16510 /* DDHA_REG_0256 */ "", 16511 /* DDHA_REG_0266 */ "", 16512 /* DDHA_REG_0276 */ "", 16513 /* DDHA_REG_00A0 */ "", 16514 /* DDHA_REG_00A4 */ "", 16515 /* DDHA_REG_00A6 */ "", 16516 /* DDHA_REG_00AA */ "", 16517 /* DDHA_REG_00C2 */ "", 16518 /* DDHA_REG_010C */ "", 16519 /* DDHA_REG_012C */ "", 16520 /* DDHA_REG_015E */ "", 16521 /* DDHA_REG_016E */ "", 16522 /* DDHA_REG_017E */ "", 16523 /* DDHA_REG_020C */ "", 16524 /* DDHA_REG_022C */ "", 16525 /* DDHA_REG_025E */ "", 16526 /* DDHA_REG_026E */ "", 16527 /* DDHA_REG_027E */ "", 16528 /* DDHA_RESERVED_MIRROR_ADDR */ "", 16529 /* DDHA_RESERVED_MTCD */ "", 16530 /* DDHA_RESERVED_MTCP */ "", 16531 /* DDHA_RESERVED_SPARE_0 */ "", 16532 /* DDHA_RESERVED_SPARE_1 */ "", 16533 /* DDHA_RESERVED_SPARE_2 */ "", 16534 /* DDHA_RESERVED_SPARE_3 */ "", 16535 /* DDHA_SBUS_BROADCAST_ID */ "", 16536 /* DDHA_SBUS_LAST_IN_CHAIN */ "", 16537 /* DDHB_ECC_1B_ERR_CNT */ "", 16538 /* DDHB_ECC_2B_ERR_CNT */ "", 16539 /* DDHB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 16540 /* DDHB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 16541 /* DDHB_ECC_INTERRUPT_REGISTER */ "", 16542 /* DDHB_ECC_INTERRUPT_REGISTER_MASK */ "", 16543 /* DDHB_ECC_INTERRUPT_REGISTER_TEST */ "", 16544 /* DDHB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 16545 /* DDHB_ERROR_INITIATION_DATA */ "", 16546 /* DDHB_GTIMER_CONFIGURATION */ "", 16547 /* DDHB_GTIMER_CYCLE */ "", 16548 /* DDHB_INDIRECT_COMMAND */ "", 16549 /* DDHB_INDIRECT_COMMAND_ADDRESS */ "", 16550 /* DDHB_INDIRECT_COMMAND_RD_DATA */ "", 16551 /* DDHB_INDIRECT_COMMAND_WR_DATA */ "", 16552 /* DDHB_INDIRECT_FORCE_BUBBLE */ "", 16553 /* DDHB_INDIRECT_WR_MASK */ "", 16554 /* DDHB_INTERRUPT_MASK_REGISTER */ "", 16555 /* DDHB_INTERRUPT_REGISTER */ "", 16556 /* DDHB_INTERRUPT_REGISTER_TEST */ "", 16557 /* DDHB_PCMI_0 */ "", 16558 /* DDHB_PCMI_1 */ "", 16559 /* DDHB_PCMI_2 */ "", 16560 /* DDHB_PCMI_3 */ "", 16561 /* DDHB_PCMI_4 */ "", 16562 /* DDHB_PCMI_0_S */ "", 16563 /* DDHB_PCMI_0_T */ "", 16564 /* DDHB_PCMI_1_S */ "", 16565 /* DDHB_PCMI_1_T */ "", 16566 /* DDHB_PCMI_2_S */ "", 16567 /* DDHB_PCMI_2_T */ "", 16568 /* DDHB_PCMI_3_S */ "", 16569 /* DDHB_PCMI_3_T */ "", 16570 /* DDHB_PCMI_4_S */ "", 16571 /* DDHB_PCMI_4_T */ "", 16572 /* DDHB_REG_0041 */ "", 16573 /* DDHB_REG_0098 */ "", 16574 /* DDHB_REG_0100 */ "", 16575 /* DDHB_REG_0101 */ "", 16576 /* DDHB_REG_0102 */ "", 16577 /* DDHB_REG_0103 */ "", 16578 /* DDHB_REG_0105 */ "", 16579 /* DDHB_REG_0106 */ "", 16580 /* DDHB_REG_0107 */ "", 16581 /* DDHB_REG_0108 */ "", 16582 /* DDHB_REG_0133 */ "", 16583 /* DDHB_REG_0153 */ "", 16584 /* DDHB_REG_0154 */ "", 16585 /* DDHB_REG_0155 */ "", 16586 /* DDHB_REG_0165 */ "", 16587 /* DDHB_REG_0175 */ "", 16588 /* DDHB_REG_0200 */ "", 16589 /* DDHB_REG_0201 */ "", 16590 /* DDHB_REG_0202 */ "", 16591 /* DDHB_REG_0203 */ "", 16592 /* DDHB_REG_0205 */ "", 16593 /* DDHB_REG_0206 */ "", 16594 /* DDHB_REG_0207 */ "", 16595 /* DDHB_REG_0208 */ "", 16596 /* DDHB_REG_0234 */ "", 16597 /* DDHB_REG_0254 */ "", 16598 /* DDHB_REG_0255 */ "", 16599 /* DDHB_REG_0256 */ "", 16600 /* DDHB_REG_0266 */ "", 16601 /* DDHB_REG_0276 */ "", 16602 /* DDHB_REG_00A0 */ "", 16603 /* DDHB_REG_00A4 */ "", 16604 /* DDHB_REG_00A6 */ "", 16605 /* DDHB_REG_00AA */ "", 16606 /* DDHB_REG_00C2 */ "", 16607 /* DDHB_REG_010B */ "", 16608 /* DDHB_REG_012B */ "", 16609 /* DDHB_REG_015D */ "", 16610 /* DDHB_REG_016D */ "", 16611 /* DDHB_REG_017D */ "", 16612 /* DDHB_REG_020C */ "", 16613 /* DDHB_REG_022C */ "", 16614 /* DDHB_REG_025E */ "", 16615 /* DDHB_REG_026E */ "", 16616 /* DDHB_REG_027E */ "", 16617 /* DDHB_RESERVED_MIRROR_ADDR */ "", 16618 /* DDHB_RESERVED_MTCD */ "", 16619 /* DDHB_RESERVED_MTCP */ "", 16620 /* DDHB_RESERVED_SPARE_0 */ "", 16621 /* DDHB_RESERVED_SPARE_1 */ "", 16622 /* DDHB_RESERVED_SPARE_2 */ "", 16623 /* DDHB_RESERVED_SPARE_3 */ "", 16624 /* DDHB_SBUS_BROADCAST_ID */ "", 16625 /* DDHB_SBUS_LAST_IN_CHAIN */ "", 16626 /* DDP_AUTO_DOC_NAME_5 */ "", 16627 /* DDP_BIG_LAT_CNI_CNTR */ "", 16628 /* DDP_BIG_LAT_PKTS_CNTR */ "", 16629 /* DDP_BUFF_CRC_ERR_CNT */ "", 16630 /* DDP_BUNDLE_COUNTERS */ "", 16631 /* DDP_C0_PORT_AC_CMD */ "", 16632 /* DDP_C0_PORT_AC_DATA */ "", 16633 /* DDP_C0_PORT_A_RADDR */ "", 16634 /* DDP_C0_PORT_BD_CMD */ "", 16635 /* DDP_C0_PORT_BD_DATA */ "", 16636 /* DDP_C0_PORT_B_RADDR */ "", 16637 /* DDP_C0_PORT_C_WADDR */ "", 16638 /* DDP_C0_PORT_D_WADDR */ "", 16639 /* DDP_C1_PORT_AC_CMD */ "", 16640 /* DDP_C1_PORT_AC_DATA */ "", 16641 /* DDP_C1_PORT_A_RADDR */ "", 16642 /* DDP_C1_PORT_BD_CMD */ "", 16643 /* DDP_C1_PORT_BD_DATA */ "", 16644 /* DDP_C1_PORT_B_RADDR */ "", 16645 /* DDP_C1_PORT_C_WADDR */ "", 16646 /* DDP_C1_PORT_D_WADDR */ "", 16647 /* DDP_C2_PORT_AC_CMD */ "", 16648 /* DDP_C2_PORT_AC_DATA */ "", 16649 /* DDP_C2_PORT_A_RADDR */ "", 16650 /* DDP_C2_PORT_BD_CMD */ "", 16651 /* DDP_C2_PORT_BD_DATA */ "", 16652 /* DDP_C2_PORT_B_RADDR */ "", 16653 /* DDP_C2_PORT_C_WADDR */ "", 16654 /* DDP_C2_PORT_D_WADDR */ "", 16655 /* DDP_C3_PORT_AC_CMD */ "", 16656 /* DDP_C3_PORT_AC_DATA */ "", 16657 /* DDP_C3_PORT_A_RADDR */ "", 16658 /* DDP_C3_PORT_BD_CMD */ "", 16659 /* DDP_C3_PORT_BD_DATA */ "", 16660 /* DDP_C3_PORT_B_RADDR */ "", 16661 /* DDP_C3_PORT_C_WADDR */ "", 16662 /* DDP_C3_PORT_D_WADDR */ "", 16663 /* DDP_CPU_DELETE_BDB_CONTROL */ "", 16664 /* DDP_CPU_DELETE_BUFF_CONTROL */ "", 16665 /* DDP_CPU_DEL_BDB_CNT */ "", 16666 /* DDP_CPU_DEL_BUFF_CNT */ "", 16667 /* DDP_CPU_RELEASE_BDB_CONTROL */ "", 16668 /* DDP_CPU_RELEASE_BUFF_CONTROL */ "", 16669 /* DDP_CPU_REL_BDB_CNT */ "", 16670 /* DDP_CPU_REL_BUFF_CNT */ "", 16671 /* DDP_CPYDAT_CRC_ERR_DEL_BDB_CNT */ "", 16672 /* DDP_CPYDAT_ECC_ERR_DEL_BDB_CNT */ "", 16673 /* DDP_CPYDAT_PKTSIZE_ERR_DEL_BDB_CNT */ "", 16674 /* DDP_CRC_ERR_BDB_CAM_FULL_CNT */ "", 16675 /* DDP_CRC_ERR_BDB_FIFO_FULL_CNT */ "", 16676 /* DDP_CRC_ERR_BUFF_FIFO_FULL_CNT */ "", 16677 /* DDP_CRC_ERR_DEL_BDB_CNT */ "", 16678 /* DDP_CRC_ERR_DEL_BUFF_CNT */ "", 16679 /* DDP_CRC_STORM_CONFIGURATION_REGISTER */ "", 16680 /* DDP_CRC_STORM_DEBUG */ "", 16681 /* DDP_CRC_STORM_MANUAL_RESET */ "", 16682 /* DDP_DDP_GENERAL_CONFIGURATION */ "", 16683 /* DDP_DDP_INIT_STATUS */ "", 16684 /* DDP_DDP_STOP_DEQUEUE */ "", 16685 /* DDP_DEBUG_STATUS */ "", 16686 /* DDP_DELETED_LAT_PKTS_CNT */ "", 16687 /* DDP_DELETE_BDB_CONFIGS */ "", 16688 /* DDP_DELETE_BDB_FIFO_HEAD */ "", 16689 /* DDP_DELETE_BDB_FIFO_STATUS */ "", 16690 /* DDP_DELETE_BUFF_CONFIGS */ "", 16691 /* DDP_DELETE_BUFF_FIFO_HEAD */ "", 16692 /* DDP_DELETE_BUFF_FIFO_STATUS */ "", 16693 /* DDP_ECC_1B_ERR_CNT */ "", 16694 /* DDP_ECC_2B_ERR_CNT */ "", 16695 /* DDP_ECC_ERR_1B_INITIATE */ "", 16696 /* DDP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 16697 /* DDP_ECC_ERR_2B_INITIATE */ "", 16698 /* DDP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 16699 /* DDP_ECC_INTERRUPT_REGISTER */ "", 16700 /* DDP_ECC_INTERRUPT_REGISTER_MASK */ "", 16701 /* DDP_ECC_INTERRUPT_REGISTER_TEST */ "", 16702 /* DDP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 16703 /* DDP_ERROR_INITIATION_DATA */ "", 16704 /* DDP_ERR_INITIATE */ "", 16705 /* DDP_EXT_MEM_ERR_INTERRUPT_REGISTER */ "", 16706 /* DDP_EXT_MEM_ERR_INTERRUPT_REGISTER_MASK */ "", 16707 /* DDP_EXT_MEM_ERR_INTERRUPT_REGISTER_TEST */ "", 16708 /* DDP_FBC_CACHE_STATUS */ "", 16709 /* DDP_FBC_CONFIGURATION */ "", 16710 /* DDP_FBC_CONTROL */ "", 16711 /* DDP_FBC_DEBUG */ "", 16712 /* DDP_FBC_FORCE */ "", 16713 /* DDP_FBC_READ_POINTER_ARRAY */ "", 16714 /* DDP_FBC_STATUS */ "", 16715 /* DDP_FBC_WRITE_POINTER_ARRAY */ "", 16716 /* DDP_GLOBAL_GENERAL_CFG_3 */ "", 16717 /* DDP_GLOBAL_MEM_OPTIONS */ "", 16718 /* DDP_GLOBAL_SYS_HEADER_CFG */ "", 16719 /* DDP_GTIMER_CONFIGURATION */ "", 16720 /* DDP_GTIMER_CYCLE */ "", 16721 /* DDP_INDIRECT_COMMAND */ "", 16722 /* DDP_INDIRECT_COMMAND_ADDRESS */ "", 16723 /* DDP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 16724 /* DDP_INDIRECT_COMMAND_RD_DATA */ "", 16725 /* DDP_INDIRECT_COMMAND_WIDE_MEM */ "", 16726 /* DDP_INDIRECT_COMMAND_WR_DATA */ "", 16727 /* DDP_INDIRECT_FORCE_BUBBLE */ "", 16728 /* DDP_INTERRUPT_MASK_REGISTER */ "", 16729 /* DDP_INTERRUPT_REGISTER */ "", 16730 /* DDP_INTERRUPT_REGISTER_TEST */ "", 16731 /* DDP_ITE_CONFIGURATIONS */ "", 16732 /* DDP_ITE_DEBUG */ "", 16733 /* DDP_ITE_DEBUG_FROM_ITPP */ "", 16734 /* DDP_ITE_DEBUG_TO_ITPP */ "", 16735 /* DDP_ITE_FIX_CONFIG */ "", 16736 /* DDP_ITE_INTERRUPT_REGISTER */ "", 16737 /* DDP_ITE_INTERRUPT_REGISTER_MASK */ "", 16738 /* DDP_ITE_INTERRUPT_REGISTER_TEST */ "", 16739 /* DDP_LAST_DDP_2_MMU_FBC_RD */ "", 16740 /* DDP_LAST_DDP_2_MMU_FBC_WR */ "", 16741 /* DDP_MAXIMUM_AND_MINIMUM_PACKET_SIZE */ "", 16742 /* DDP_MAX_LATENCY_LAT_PKT */ "", 16743 /* DDP_MLM_COUNTERS */ "", 16744 /* DDP_MMU_COUNTERS */ "", 16745 /* DDP_MODULE_CONTROL */ "", 16746 /* DDP_NOT_OUT_READY_COUNTERS */ "", 16747 /* DDP_NO_READ_WHEN_READY_COUNTERS */ "", 16748 /* DDP_PACKET_ERROR_COUNTERS */ "", 16749 /* DDP_PACKET_LATENCY_FORMAT */ "", 16750 /* DDP_PACKET_LATENCY_MEASUREMENT */ "", 16751 /* DDP_PCMI_0 */ "", 16752 /* DDP_PCMI_1 */ "", 16753 /* DDP_PCMI_2 */ "", 16754 /* DDP_PCMI_3 */ "", 16755 /* DDP_PCMI_4 */ "", 16756 /* DDP_PCMI_0_S */ "", 16757 /* DDP_PCMI_0_T */ "", 16758 /* DDP_PCMI_1_S */ "", 16759 /* DDP_PCMI_1_T */ "", 16760 /* DDP_PCMI_2_S */ "", 16761 /* DDP_PCMI_2_T */ "", 16762 /* DDP_PCMI_3_S */ "", 16763 /* DDP_PCMI_3_T */ "", 16764 /* DDP_PCMI_4_S */ "", 16765 /* DDP_PCMI_4_T */ "", 16766 /* DDP_PKT_LST_RD_DBUFF */ "", 16767 /* DDP_PROGRAM_GO */ "", 16768 /* DDP_REG_00A4 */ "", 16769 /* DDP_REG_00A6 */ "", 16770 /* DDP_REG_00C2 */ "", 16771 /* DDP_REG_00C3 */ "", 16772 /* DDP_REG_00C4 */ "", 16773 /* DDP_REG_00C5 */ "", 16774 /* DDP_REG_00C6 */ "", 16775 /* DDP_REG_00C7 */ "", 16776 /* DDP_RESERVED_MIRROR_ADDR */ "", 16777 /* DDP_RESERVED_MTCD */ "", 16778 /* DDP_RESERVED_MTCP */ "", 16779 /* DDP_RESERVED_SPARE_0 */ "", 16780 /* DDP_RESERVED_SPARE_1 */ "", 16781 /* DDP_RESERVED_SPARE_2 */ "", 16782 /* DDP_RESERVED_SPARE_3 */ "", 16783 /* DDP_SBUS_BROADCAST_ID */ "", 16784 /* DDP_SBUS_LAST_IN_CHAIN */ "", 16785 /* DDP_SPECIAL_CLOCK_CONTROLS */ "", 16786 /* DDP_TDU_CORRECTED_ERR_DEL_BDB_CNT */ "", 16787 /* DDP_TDU_ERR_DEL_BDB_CNT */ "", 16788 /* DDP_TDU_WORDS_ERR_CNT */ "", 16789 /* DDP_TXI_NOT_READY_COUNTERS */ "", 16790 /* DDR3_PLL_CTRL_REGISTER_0 */ "", 16791 /* DDR3_PLL_CTRL_REGISTER_1 */ "", 16792 /* DDR3_PLL_CTRL_REGISTER_2 */ "", 16793 /* DDR3_PLL_CTRL_REGISTER_3 */ "", 16794 /* DDR3_PLL_CTRL_REGISTER_4 */ "", 16795 /* DDR3_PLL_STATUS */ "", 16796 /* DDR4_PHY_AQ_IO_CONFIG */ "", 16797 /* DDR4_PHY_AQ_LDO_CONFIG */ "", 16798 /* DDR4_PHY_AQ_L_MACRO_RESERVED_REG */ "", 16799 /* DDR4_PHY_AQ_L_MAX_VDL_ADDR */ "", 16800 /* DDR4_PHY_AQ_L_MAX_VDL_CTRL */ "", 16801 /* DDR4_PHY_AQ_L_STATUS_MACRO_RESERVED */ "", 16802 /* DDR4_PHY_AQ_U_MACRO_RESERVED_REG */ "", 16803 /* DDR4_PHY_AQ_U_MAX_VDL_ADDR */ "", 16804 /* DDR4_PHY_AQ_U_MAX_VDL_CTRL */ "", 16805 /* DDR4_PHY_AQ_U_STATUS_MACRO_RESERVED */ "", 16806 /* DDR4_PHY_COMMON_CK_CONFIG */ "", 16807 /* DDR4_PHY_COMMON_IO_CONFIG */ "", 16808 /* DDR4_PHY_COMMON_LDO_CONFIG */ "", 16809 /* DDR4_PHY_COMMON_MACRO_RESERVED_REG */ "", 16810 /* DDR4_PHY_COMMON_MAX_VDL_CK */ "", 16811 /* DDR4_PHY_COMMON_RESCAL_INIT_CONFIG */ "", 16812 /* DDR4_PHY_COMMON_RESCAL_OPERATION_CONFIG */ "", 16813 /* DDR4_PHY_COMMON_STATUS_MACRO_RESERVED */ "", 16814 /* DDR4_PHY_COMMON_STATUS_RESCAL */ "", 16815 /* DDR4_PHY_CONTROL_REGS_ACTIVE_INTERFACES_CONFIG */ "", 16816 /* DDR4_PHY_CONTROL_REGS_DDR4_DRAM_PARAMETER_CONFIG */ "", 16817 /* DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_INITIALIZER */ "", 16818 /* DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_LSB */ "", 16819 /* DDR4_PHY_CONTROL_REGS_DDR4_REN_FIFO_CENTRAL_MODIFIER_MSB */ "", 16820 /* DDR4_PHY_CONTROL_REGS_FREQ_CNTR_CONFIG */ "", 16821 /* DDR4_PHY_CONTROL_REGS_INPUT_SHIFT_CTRL */ "", 16822 /* DDR4_PHY_CONTROL_REGS_READ_CLOCK_CONFIG */ "", 16823 /* DDR4_PHY_CONTROL_REGS_READ_FIFO_CTRL */ "", 16824 /* DDR4_PHY_CONTROL_REGS_RESERVED_REG */ "", 16825 /* DDR4_PHY_CONTROL_REGS_RESET_CTRL */ "", 16826 /* DDR4_PHY_CONTROL_REGS_REVISION */ "", 16827 /* DDR4_PHY_CONTROL_REGS_SHARED_VREF_DAC_CONFIG */ "", 16828 /* DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_DCOUNT */ "", 16829 /* DDR4_PHY_CONTROL_REGS_STATUS_FREQ_CNTR_UCOUNT */ "", 16830 /* DDR4_PHY_CONTROL_REGS_STATUS_MACRO_RESERVED */ "", 16831 /* DDR4_PHY_CONTROL_REGS_SUPPLEMENT_VREF_DAC_CONFIG */ "", 16832 /* DDR4_PHY_CONTROL_REGS_WRITE_FIFO_CTRL */ "", 16833 /* DDR4_PHY_DQ_BYTE0_CDR_N_VDL_CONFIG */ "", 16834 /* DDR4_PHY_DQ_BYTE0_CDR_OPERATION_CONFIG */ "", 16835 /* DDR4_PHY_DQ_BYTE0_CDR_P_VDL_CONFIG */ "", 16836 /* DDR4_PHY_DQ_BYTE0_CDR_TIMING_CONFIG */ "", 16837 /* DDR4_PHY_DQ_BYTE0_CDR_TRACK_CONFIG */ "", 16838 /* DDR4_PHY_DQ_BYTE0_CDR_UPDATE_CONFIG */ "", 16839 /* DDR4_PHY_DQ_BYTE0_CDR_VDL_CAP_CONFIG */ "", 16840 /* DDR4_PHY_DQ_BYTE0_DATA_IO_CONFIG */ "", 16841 /* DDR4_PHY_DQ_BYTE0_DDR4_OE_CONFIG */ "", 16842 /* DDR4_PHY_DQ_BYTE0_DDR4_READ_MAX_VDL_FSM */ "", 16843 /* DDR4_PHY_DQ_BYTE0_DDR4_REN_FIFO_CONFIG */ "", 16844 /* DDR4_PHY_DQ_BYTE0_DDR4_REN_GEN_ERR_CTRL */ "", 16845 /* DDR4_PHY_DQ_BYTE0_DDR4_REN_STRETCH_CONFIG */ "", 16846 /* DDR4_PHY_DQ_BYTE0_DQS_IO_CONFIG */ "", 16847 /* DDR4_PHY_DQ_BYTE0_GDDR5_READ_ALIGNMENT_CTRL */ "", 16848 /* DDR4_PHY_DQ_BYTE0_GDDR5_READ_FSM_CTRL */ "", 16849 /* DDR4_PHY_DQ_BYTE0_LDO_R_CONFIG */ "", 16850 /* DDR4_PHY_DQ_BYTE0_LDO_W_CONFIG */ "", 16851 /* DDR4_PHY_DQ_BYTE0_MACRO_RESERVED_REG */ "", 16852 /* DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDN */ "", 16853 /* DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSDP */ "", 16854 /* DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEN */ "", 16855 /* DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQSEP */ "", 16856 /* DDR4_PHY_DQ_BYTE0_READ_MAX_VDL_DQS_MASTER_CTRL */ "", 16857 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT0 */ "", 16858 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT1 */ "", 16859 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT2 */ "", 16860 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT3 */ "", 16861 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT4 */ "", 16862 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT5 */ "", 16863 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT6 */ "", 16864 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_BIT7 */ "", 16865 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_DBI */ "", 16866 /* DDR4_PHY_DQ_BYTE0_READ_MIN_VDL_EDC */ "", 16867 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_DN_VDL_STAT */ "", 16868 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_DP_VDL_STAT */ "", 16869 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_EN_VDL_STAT */ "", 16870 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_EP_VDL_STAT */ "", 16871 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_N_VDL */ "", 16872 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_OPERATION */ "", 16873 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_P_VDL */ "", 16874 /* DDR4_PHY_DQ_BYTE0_STATUS_CDR_TIMING */ "", 16875 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_CTR */ "", 16876 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_FIFO_PTR */ "", 16877 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH */ "", 16878 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR1 */ "", 16879 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR2 */ "", 16880 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_ERR3 */ "", 16881 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RCMD_MACH_RCMD_ID */ "", 16882 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_RDATA_FIFO */ "", 16883 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_FIFO */ "", 16884 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR1 */ "", 16885 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_ERR2 */ "", 16886 /* DDR4_PHY_DQ_BYTE0_STATUS_DDR4_REN_GEN_RCMD_ID */ "", 16887 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR */ "", 16888 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB */ "", 16889 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB */ "", 16890 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES */ "", 16891 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS */ "", 16892 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB */ "", 16893 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB */ "", 16894 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES */ "", 16895 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS */ "", 16896 /* DDR4_PHY_DQ_BYTE0_STATUS_GDDR5_FIFO_POINTERS */ "", 16897 /* DDR4_PHY_DQ_BYTE0_STATUS_MACRO_RESERVED */ "", 16898 /* DDR4_PHY_DQ_BYTE0_STATUS_WRITE_LEVELING */ "", 16899 /* DDR4_PHY_DQ_BYTE0_VREF_DAC_CONFIG */ "", 16900 /* DDR4_PHY_DQ_BYTE0_WRITE_LEVELING_CONFIG */ "", 16901 /* DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA */ "", 16902 /* DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DATA_SHADOW */ "", 16903 /* DDR4_PHY_DQ_BYTE0_WRITE_MAX_VDL_DQS */ "", 16904 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT0 */ "", 16905 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT1 */ "", 16906 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT2 */ "", 16907 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT3 */ "", 16908 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT4 */ "", 16909 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT5 */ "", 16910 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT6 */ "", 16911 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_BIT7 */ "", 16912 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_DBI */ "", 16913 /* DDR4_PHY_DQ_BYTE0_WRITE_MIN_VDL_EDC */ "", 16914 /* DDR4_PHY_DQ_BYTE1_CDR_N_VDL_CONFIG */ "", 16915 /* DDR4_PHY_DQ_BYTE1_CDR_OPERATION_CONFIG */ "", 16916 /* DDR4_PHY_DQ_BYTE1_CDR_P_VDL_CONFIG */ "", 16917 /* DDR4_PHY_DQ_BYTE1_CDR_TIMING_CONFIG */ "", 16918 /* DDR4_PHY_DQ_BYTE1_CDR_TRACK_CONFIG */ "", 16919 /* DDR4_PHY_DQ_BYTE1_CDR_UPDATE_CONFIG */ "", 16920 /* DDR4_PHY_DQ_BYTE1_CDR_VDL_CAP_CONFIG */ "", 16921 /* DDR4_PHY_DQ_BYTE1_DATA_IO_CONFIG */ "", 16922 /* DDR4_PHY_DQ_BYTE1_DDR4_OE_CONFIG */ "", 16923 /* DDR4_PHY_DQ_BYTE1_DDR4_READ_MAX_VDL_FSM */ "", 16924 /* DDR4_PHY_DQ_BYTE1_DDR4_REN_FIFO_CONFIG */ "", 16925 /* DDR4_PHY_DQ_BYTE1_DDR4_REN_GEN_ERR_CTRL */ "", 16926 /* DDR4_PHY_DQ_BYTE1_DDR4_REN_STRETCH_CONFIG */ "", 16927 /* DDR4_PHY_DQ_BYTE1_DQS_IO_CONFIG */ "", 16928 /* DDR4_PHY_DQ_BYTE1_GDDR5_READ_ALIGNMENT_CTRL */ "", 16929 /* DDR4_PHY_DQ_BYTE1_GDDR5_READ_FSM_CTRL */ "", 16930 /* DDR4_PHY_DQ_BYTE1_LDO_R_CONFIG */ "", 16931 /* DDR4_PHY_DQ_BYTE1_LDO_W_CONFIG */ "", 16932 /* DDR4_PHY_DQ_BYTE1_MACRO_RESERVED_REG */ "", 16933 /* DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDN */ "", 16934 /* DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSDP */ "", 16935 /* DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEN */ "", 16936 /* DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQSEP */ "", 16937 /* DDR4_PHY_DQ_BYTE1_READ_MAX_VDL_DQS_MASTER_CTRL */ "", 16938 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT0 */ "", 16939 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT1 */ "", 16940 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT2 */ "", 16941 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT3 */ "", 16942 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT4 */ "", 16943 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT5 */ "", 16944 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT6 */ "", 16945 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_BIT7 */ "", 16946 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_DBI */ "", 16947 /* DDR4_PHY_DQ_BYTE1_READ_MIN_VDL_EDC */ "", 16948 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_DN_VDL_STAT */ "", 16949 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_DP_VDL_STAT */ "", 16950 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_EN_VDL_STAT */ "", 16951 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_EP_VDL_STAT */ "", 16952 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_N_VDL */ "", 16953 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_OPERATION */ "", 16954 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_P_VDL */ "", 16955 /* DDR4_PHY_DQ_BYTE1_STATUS_CDR_TIMING */ "", 16956 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_CTR */ "", 16957 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_FIFO_PTR */ "", 16958 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH */ "", 16959 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR1 */ "", 16960 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR2 */ "", 16961 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_ERR3 */ "", 16962 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RCMD_MACH_RCMD_ID */ "", 16963 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_RDATA_FIFO */ "", 16964 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_FIFO */ "", 16965 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR1 */ "", 16966 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_ERR2 */ "", 16967 /* DDR4_PHY_DQ_BYTE1_STATUS_DDR4_REN_GEN_RCMD_ID */ "", 16968 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR */ "", 16969 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB */ "", 16970 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB */ "", 16971 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES */ "", 16972 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS */ "", 16973 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB */ "", 16974 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB */ "", 16975 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES */ "", 16976 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS */ "", 16977 /* DDR4_PHY_DQ_BYTE1_STATUS_GDDR5_FIFO_POINTERS */ "", 16978 /* DDR4_PHY_DQ_BYTE1_STATUS_MACRO_RESERVED */ "", 16979 /* DDR4_PHY_DQ_BYTE1_STATUS_WRITE_LEVELING */ "", 16980 /* DDR4_PHY_DQ_BYTE1_VREF_DAC_CONFIG */ "", 16981 /* DDR4_PHY_DQ_BYTE1_WRITE_LEVELING_CONFIG */ "", 16982 /* DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA */ "", 16983 /* DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DATA_SHADOW */ "", 16984 /* DDR4_PHY_DQ_BYTE1_WRITE_MAX_VDL_DQS */ "", 16985 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT0 */ "", 16986 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT1 */ "", 16987 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT2 */ "", 16988 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT3 */ "", 16989 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT4 */ "", 16990 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT5 */ "", 16991 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT6 */ "", 16992 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_BIT7 */ "", 16993 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_DBI */ "", 16994 /* DDR4_PHY_DQ_BYTE1_WRITE_MIN_VDL_EDC */ "", 16995 /* DDR4_PHY_DQ_BYTE2_CDR_N_VDL_CONFIG */ "", 16996 /* DDR4_PHY_DQ_BYTE2_CDR_OPERATION_CONFIG */ "", 16997 /* DDR4_PHY_DQ_BYTE2_CDR_P_VDL_CONFIG */ "", 16998 /* DDR4_PHY_DQ_BYTE2_CDR_TIMING_CONFIG */ "", 16999 /* DDR4_PHY_DQ_BYTE2_CDR_TRACK_CONFIG */ "", 17000 /* DDR4_PHY_DQ_BYTE2_CDR_UPDATE_CONFIG */ "", 17001 /* DDR4_PHY_DQ_BYTE2_CDR_VDL_CAP_CONFIG */ "", 17002 /* DDR4_PHY_DQ_BYTE2_DATA_IO_CONFIG */ "", 17003 /* DDR4_PHY_DQ_BYTE2_DDR4_OE_CONFIG */ "", 17004 /* DDR4_PHY_DQ_BYTE2_DDR4_READ_MAX_VDL_FSM */ "", 17005 /* DDR4_PHY_DQ_BYTE2_DDR4_REN_FIFO_CONFIG */ "", 17006 /* DDR4_PHY_DQ_BYTE2_DDR4_REN_GEN_ERR_CTRL */ "", 17007 /* DDR4_PHY_DQ_BYTE2_DDR4_REN_STRETCH_CONFIG */ "", 17008 /* DDR4_PHY_DQ_BYTE2_DQS_IO_CONFIG */ "", 17009 /* DDR4_PHY_DQ_BYTE2_GDDR5_READ_ALIGNMENT_CTRL */ "", 17010 /* DDR4_PHY_DQ_BYTE2_GDDR5_READ_FSM_CTRL */ "", 17011 /* DDR4_PHY_DQ_BYTE2_LDO_R_CONFIG */ "", 17012 /* DDR4_PHY_DQ_BYTE2_LDO_W_CONFIG */ "", 17013 /* DDR4_PHY_DQ_BYTE2_MACRO_RESERVED_REG */ "", 17014 /* DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDN */ "", 17015 /* DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSDP */ "", 17016 /* DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEN */ "", 17017 /* DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQSEP */ "", 17018 /* DDR4_PHY_DQ_BYTE2_READ_MAX_VDL_DQS_MASTER_CTRL */ "", 17019 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT0 */ "", 17020 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT1 */ "", 17021 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT2 */ "", 17022 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT3 */ "", 17023 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT4 */ "", 17024 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT5 */ "", 17025 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT6 */ "", 17026 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_BIT7 */ "", 17027 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_DBI */ "", 17028 /* DDR4_PHY_DQ_BYTE2_READ_MIN_VDL_EDC */ "", 17029 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_DN_VDL_STAT */ "", 17030 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_DP_VDL_STAT */ "", 17031 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_EN_VDL_STAT */ "", 17032 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_EP_VDL_STAT */ "", 17033 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_N_VDL */ "", 17034 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_OPERATION */ "", 17035 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_P_VDL */ "", 17036 /* DDR4_PHY_DQ_BYTE2_STATUS_CDR_TIMING */ "", 17037 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_CTR */ "", 17038 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_FIFO_PTR */ "", 17039 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH */ "", 17040 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR1 */ "", 17041 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR2 */ "", 17042 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_ERR3 */ "", 17043 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RCMD_MACH_RCMD_ID */ "", 17044 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_RDATA_FIFO */ "", 17045 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_FIFO */ "", 17046 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR1 */ "", 17047 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_ERR2 */ "", 17048 /* DDR4_PHY_DQ_BYTE2_STATUS_DDR4_REN_GEN_RCMD_ID */ "", 17049 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR */ "", 17050 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB */ "", 17051 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB */ "", 17052 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES */ "", 17053 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS */ "", 17054 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB */ "", 17055 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB */ "", 17056 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES */ "", 17057 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS */ "", 17058 /* DDR4_PHY_DQ_BYTE2_STATUS_GDDR5_FIFO_POINTERS */ "", 17059 /* DDR4_PHY_DQ_BYTE2_STATUS_MACRO_RESERVED */ "", 17060 /* DDR4_PHY_DQ_BYTE2_STATUS_WRITE_LEVELING */ "", 17061 /* DDR4_PHY_DQ_BYTE2_VREF_DAC_CONFIG */ "", 17062 /* DDR4_PHY_DQ_BYTE2_WRITE_LEVELING_CONFIG */ "", 17063 /* DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA */ "", 17064 /* DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DATA_SHADOW */ "", 17065 /* DDR4_PHY_DQ_BYTE2_WRITE_MAX_VDL_DQS */ "", 17066 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT0 */ "", 17067 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT1 */ "", 17068 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT2 */ "", 17069 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT3 */ "", 17070 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT4 */ "", 17071 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT5 */ "", 17072 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT6 */ "", 17073 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_BIT7 */ "", 17074 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_DBI */ "", 17075 /* DDR4_PHY_DQ_BYTE2_WRITE_MIN_VDL_EDC */ "", 17076 /* DDR4_PHY_DQ_BYTE3_CDR_N_VDL_CONFIG */ "", 17077 /* DDR4_PHY_DQ_BYTE3_CDR_OPERATION_CONFIG */ "", 17078 /* DDR4_PHY_DQ_BYTE3_CDR_P_VDL_CONFIG */ "", 17079 /* DDR4_PHY_DQ_BYTE3_CDR_TIMING_CONFIG */ "", 17080 /* DDR4_PHY_DQ_BYTE3_CDR_TRACK_CONFIG */ "", 17081 /* DDR4_PHY_DQ_BYTE3_CDR_UPDATE_CONFIG */ "", 17082 /* DDR4_PHY_DQ_BYTE3_CDR_VDL_CAP_CONFIG */ "", 17083 /* DDR4_PHY_DQ_BYTE3_DATA_IO_CONFIG */ "", 17084 /* DDR4_PHY_DQ_BYTE3_DDR4_OE_CONFIG */ "", 17085 /* DDR4_PHY_DQ_BYTE3_DDR4_READ_MAX_VDL_FSM */ "", 17086 /* DDR4_PHY_DQ_BYTE3_DDR4_REN_FIFO_CONFIG */ "", 17087 /* DDR4_PHY_DQ_BYTE3_DDR4_REN_GEN_ERR_CTRL */ "", 17088 /* DDR4_PHY_DQ_BYTE3_DDR4_REN_STRETCH_CONFIG */ "", 17089 /* DDR4_PHY_DQ_BYTE3_DQS_IO_CONFIG */ "", 17090 /* DDR4_PHY_DQ_BYTE3_GDDR5_READ_ALIGNMENT_CTRL */ "", 17091 /* DDR4_PHY_DQ_BYTE3_GDDR5_READ_FSM_CTRL */ "", 17092 /* DDR4_PHY_DQ_BYTE3_LDO_R_CONFIG */ "", 17093 /* DDR4_PHY_DQ_BYTE3_LDO_W_CONFIG */ "", 17094 /* DDR4_PHY_DQ_BYTE3_MACRO_RESERVED_REG */ "", 17095 /* DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDN */ "", 17096 /* DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSDP */ "", 17097 /* DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEN */ "", 17098 /* DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQSEP */ "", 17099 /* DDR4_PHY_DQ_BYTE3_READ_MAX_VDL_DQS_MASTER_CTRL */ "", 17100 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT0 */ "", 17101 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT1 */ "", 17102 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT2 */ "", 17103 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT3 */ "", 17104 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT4 */ "", 17105 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT5 */ "", 17106 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT6 */ "", 17107 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_BIT7 */ "", 17108 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_DBI */ "", 17109 /* DDR4_PHY_DQ_BYTE3_READ_MIN_VDL_EDC */ "", 17110 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_DN_VDL_STAT */ "", 17111 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_DP_VDL_STAT */ "", 17112 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_EN_VDL_STAT */ "", 17113 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_EP_VDL_STAT */ "", 17114 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_N_VDL */ "", 17115 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_OPERATION */ "", 17116 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_P_VDL */ "", 17117 /* DDR4_PHY_DQ_BYTE3_STATUS_CDR_TIMING */ "", 17118 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_CTR */ "", 17119 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_FIFO_PTR */ "", 17120 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH */ "", 17121 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR1 */ "", 17122 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR2 */ "", 17123 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_ERR3 */ "", 17124 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RCMD_MACH_RCMD_ID */ "", 17125 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_RDATA_FIFO */ "", 17126 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_FIFO */ "", 17127 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR1 */ "", 17128 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_ERR2 */ "", 17129 /* DDR4_PHY_DQ_BYTE3_STATUS_DDR4_REN_GEN_RCMD_ID */ "", 17130 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR */ "", 17131 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB */ "", 17132 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB */ "", 17133 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES */ "", 17134 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS */ "", 17135 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB */ "", 17136 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB */ "", 17137 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES */ "", 17138 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS */ "", 17139 /* DDR4_PHY_DQ_BYTE3_STATUS_GDDR5_FIFO_POINTERS */ "", 17140 /* DDR4_PHY_DQ_BYTE3_STATUS_MACRO_RESERVED */ "", 17141 /* DDR4_PHY_DQ_BYTE3_STATUS_WRITE_LEVELING */ "", 17142 /* DDR4_PHY_DQ_BYTE3_VREF_DAC_CONFIG */ "", 17143 /* DDR4_PHY_DQ_BYTE3_WRITE_LEVELING_CONFIG */ "", 17144 /* DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA */ "", 17145 /* DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DATA_SHADOW */ "", 17146 /* DDR4_PHY_DQ_BYTE3_WRITE_MAX_VDL_DQS */ "", 17147 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT0 */ "", 17148 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT1 */ "", 17149 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT2 */ "", 17150 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT3 */ "", 17151 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT4 */ "", 17152 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT5 */ "", 17153 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT6 */ "", 17154 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_BIT7 */ "", 17155 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_DBI */ "", 17156 /* DDR4_PHY_DQ_BYTE3_WRITE_MIN_VDL_EDC */ "", 17157 /* DDR4_PHY_DQ_BYTE4_CDR_N_VDL_CONFIG */ "", 17158 /* DDR4_PHY_DQ_BYTE4_CDR_OPERATION_CONFIG */ "", 17159 /* DDR4_PHY_DQ_BYTE4_CDR_P_VDL_CONFIG */ "", 17160 /* DDR4_PHY_DQ_BYTE4_CDR_TIMING_CONFIG */ "", 17161 /* DDR4_PHY_DQ_BYTE4_CDR_TRACK_CONFIG */ "", 17162 /* DDR4_PHY_DQ_BYTE4_CDR_UPDATE_CONFIG */ "", 17163 /* DDR4_PHY_DQ_BYTE4_CDR_VDL_CAP_CONFIG */ "", 17164 /* DDR4_PHY_DQ_BYTE4_DATA_IO_CONFIG */ "", 17165 /* DDR4_PHY_DQ_BYTE4_DDR4_OE_CONFIG */ "", 17166 /* DDR4_PHY_DQ_BYTE4_DDR4_READ_MAX_VDL_FSM */ "", 17167 /* DDR4_PHY_DQ_BYTE4_DDR4_REN_FIFO_CONFIG */ "", 17168 /* DDR4_PHY_DQ_BYTE4_DDR4_REN_GEN_ERR_CTRL */ "", 17169 /* DDR4_PHY_DQ_BYTE4_DDR4_REN_STRETCH_CONFIG */ "", 17170 /* DDR4_PHY_DQ_BYTE4_DQS_IO_CONFIG */ "", 17171 /* DDR4_PHY_DQ_BYTE4_GDDR5_READ_ALIGNMENT_CTRL */ "", 17172 /* DDR4_PHY_DQ_BYTE4_GDDR5_READ_FSM_CTRL */ "", 17173 /* DDR4_PHY_DQ_BYTE4_LDO_R_CONFIG */ "", 17174 /* DDR4_PHY_DQ_BYTE4_LDO_W_CONFIG */ "", 17175 /* DDR4_PHY_DQ_BYTE4_MACRO_RESERVED_REG */ "", 17176 /* DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDN */ "", 17177 /* DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSDP */ "", 17178 /* DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEN */ "", 17179 /* DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQSEP */ "", 17180 /* DDR4_PHY_DQ_BYTE4_READ_MAX_VDL_DQS_MASTER_CTRL */ "", 17181 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT0 */ "", 17182 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT1 */ "", 17183 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT2 */ "", 17184 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT3 */ "", 17185 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT4 */ "", 17186 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT5 */ "", 17187 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT6 */ "", 17188 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_BIT7 */ "", 17189 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_DBI */ "", 17190 /* DDR4_PHY_DQ_BYTE4_READ_MIN_VDL_EDC */ "", 17191 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_DN_VDL_STAT */ "", 17192 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_DP_VDL_STAT */ "", 17193 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_EN_VDL_STAT */ "", 17194 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_EP_VDL_STAT */ "", 17195 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_N_VDL */ "", 17196 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_OPERATION */ "", 17197 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_P_VDL */ "", 17198 /* DDR4_PHY_DQ_BYTE4_STATUS_CDR_TIMING */ "", 17199 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_CTR */ "", 17200 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_FIFO_PTR */ "", 17201 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH */ "", 17202 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR1 */ "", 17203 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR2 */ "", 17204 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_ERR3 */ "", 17205 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RCMD_MACH_RCMD_ID */ "", 17206 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_RDATA_FIFO */ "", 17207 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_FIFO */ "", 17208 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR1 */ "", 17209 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_ERR2 */ "", 17210 /* DDR4_PHY_DQ_BYTE4_STATUS_DDR4_REN_GEN_RCMD_ID */ "", 17211 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR */ "", 17212 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_LSB */ "", 17213 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_RCMDS_MSB */ "", 17214 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_STATES */ "", 17215 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_ERROR_VALIDS */ "", 17216 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_LSB */ "", 17217 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_RCMDS_MSB */ "", 17218 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_STATES */ "", 17219 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_DATA_VALID_GEN_LAST_VALIDS */ "", 17220 /* DDR4_PHY_DQ_BYTE4_STATUS_GDDR5_FIFO_POINTERS */ "", 17221 /* DDR4_PHY_DQ_BYTE4_STATUS_MACRO_RESERVED */ "", 17222 /* DDR4_PHY_DQ_BYTE4_STATUS_WRITE_LEVELING */ "", 17223 /* DDR4_PHY_DQ_BYTE4_VREF_DAC_CONFIG */ "", 17224 /* DDR4_PHY_DQ_BYTE4_WRITE_LEVELING_CONFIG */ "", 17225 /* DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA */ "", 17226 /* DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DATA_SHADOW */ "", 17227 /* DDR4_PHY_DQ_BYTE4_WRITE_MAX_VDL_DQS */ "", 17228 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT0 */ "", 17229 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT1 */ "", 17230 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT2 */ "", 17231 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT3 */ "", 17232 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT4 */ "", 17233 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT5 */ "", 17234 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT6 */ "", 17235 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_BIT7 */ "", 17236 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_DBI */ "", 17237 /* DDR4_PHY_DQ_BYTE4_WRITE_MIN_VDL_EDC */ "", 17238 /* DDR4_PHY_SUPPLEMENT_IO_CONFIG */ "", 17239 /* DDR4_PHY_SUPPLEMENT_MACRO_RESERVED_REG */ "", 17240 /* DDR4_PHY_SUPPLEMENT_STATUS_MACRO_RESERVED */ "", 17241 /* DDR_APB_CLK_ROUTE */ "", 17242 /* DDR_APB_COMMON_CTRL */ "", 17243 /* DDR_APB_DBG_1 */ "", 17244 /* DDR_APB_DBG_2 */ "", 17245 /* DDR_APB_DBG_3 */ "", 17246 /* DDR_APB_FRAC_N_MODE_LOCK_DET */ "", 17247 /* DDR_APB_LP_FREQ_1 */ "", 17248 /* DDR_APB_LP_FREQ_2 */ "", 17249 /* DDR_APB_LP_VCO_CTRL_1 */ "", 17250 /* DDR_APB_LP_VCO_CTRL_2 */ "", 17251 /* DDR_APB_LP_VCO_CTRL_3 */ "", 17252 /* DDR_APB_POST_DIV_CTRL */ "", 17253 /* DDR_APB_PWR_RST */ "", 17254 /* DDR_APB_RESET_OVERRIDE */ "", 17255 /* DDR_APB_SCAN_ATE_CTRL */ "", 17256 /* DDR_APB_SSC_1 */ "", 17257 /* DDR_APB_SSC_2 */ "", 17258 /* DDR_BISTCONFIG */ "", 17259 /* DDR_BISTCONFIG2 */ "", 17260 /* DDR_BISTCONFIGURATIONS */ "", 17261 /* DDR_BISTCONFIGURATIONS_0 */ "", 17262 /* DDR_BISTCONFIGURATIONS_1 */ "", 17263 /* DDR_BISTDBIERROCCURED */ "", 17264 /* DDR_BISTEDCERROCCURED */ "", 17265 /* DDR_BISTENDADDRESS */ "", 17266 /* DDR_BISTERROROCCURRED */ "", 17267 /* DDR_BISTFIFOSTATUSES */ "", 17268 /* DDR_BISTFULLMASKERRORCOUNTER */ "", 17269 /* DDR_BISTFULLMASKWORD0 */ "", 17270 /* DDR_BISTFULLMASKWORD1 */ "", 17271 /* DDR_BISTFULLMASKWORD2 */ "", 17272 /* DDR_BISTFULLMASKWORD3 */ "", 17273 /* DDR_BISTFULLMASKWORD4 */ "", 17274 /* DDR_BISTFULLMASKWORD5 */ "", 17275 /* DDR_BISTFULLMASKWORD6 */ "", 17276 /* DDR_BISTFULLMASKWORD7 */ "", 17277 /* DDR_BISTGENERALCONFIGURATIONS */ "", 17278 /* DDR_BISTGLOBALERRORCOUNTER */ "", 17279 /* DDR_BISTLASTADDRERR */ "", 17280 /* DDR_BISTLASTDATAERRLSB31_TO_0 */ "", 17281 /* DDR_BISTLASTDATAERRLSB_127_TO_96 */ "", 17282 /* DDR_BISTLASTDATAERRLSB_63_TO_32 */ "", 17283 /* DDR_BISTLASTDATAERRLSB_95_TO_64 */ "", 17284 /* DDR_BISTLASTDATAERRMSB31_TO_0 */ "", 17285 /* DDR_BISTLASTDATAERRMSB_127_TO_96 */ "", 17286 /* DDR_BISTLASTDATAERRMSB_63_TO_32 */ "", 17287 /* DDR_BISTLASTDATAERRMSB_95_TO_64 */ "", 17288 /* DDR_BISTLASTDATAERRWORD0 */ "", 17289 /* DDR_BISTLASTDATAERRWORD1 */ "", 17290 /* DDR_BISTLASTDATAERRWORD2 */ "", 17291 /* DDR_BISTLASTDATAERRWORD3 */ "", 17292 /* DDR_BISTLASTDATAERRWORD4 */ "", 17293 /* DDR_BISTLASTDATAERRWORD5 */ "", 17294 /* DDR_BISTLASTDATAERRWORD6 */ "", 17295 /* DDR_BISTLASTDATAERRWORD7 */ "", 17296 /* DDR_BISTLASTREADDATALSB31_TO_0 */ "", 17297 /* DDR_BISTLASTREADDATALSB_127_TO_96 */ "", 17298 /* DDR_BISTLASTREADDATALSB_63_TO_32 */ "", 17299 /* DDR_BISTLASTREADDATALSB_95_TO_64 */ "", 17300 /* DDR_BISTLASTREADDATAMSB31_TO_0 */ "", 17301 /* DDR_BISTLASTREADDATAMSB_127_TO_96 */ "", 17302 /* DDR_BISTLASTREADDATAMSB_63_TO_32 */ "", 17303 /* DDR_BISTLASTREADDATAMSB_95_TO_64 */ "", 17304 /* DDR_BISTMPRSTAGGERPATTERNS */ "", 17305 /* DDR_BISTMPRSTAGGERWEIGHTS */ "", 17306 /* DDR_BISTNUMBEROFACTIONS */ "", 17307 /* DDR_BISTPATTERNREPETITION_0 */ "", 17308 /* DDR_BISTPATTERNREPETITION_1 */ "", 17309 /* DDR_BISTPATTERNWORD0 */ "", 17310 /* DDR_BISTPATTERNWORD1 */ "", 17311 /* DDR_BISTPATTERNWORD2 */ "", 17312 /* DDR_BISTPATTERNWORD3 */ "", 17313 /* DDR_BISTPATTERNWORD4 */ "", 17314 /* DDR_BISTPATTERNWORD5 */ "", 17315 /* DDR_BISTPATTERNWORD6 */ "", 17316 /* DDR_BISTPATTERNWORD7 */ "", 17317 /* DDR_BISTPRBSADDRSEED */ "", 17318 /* DDR_BISTPRBSDATASEEDLSB31_TO_0 */ "", 17319 /* DDR_BISTPRBSDATASEEDLSB_127_TO_96 */ "", 17320 /* DDR_BISTPRBSDATASEEDLSB_63_TO_32 */ "", 17321 /* DDR_BISTPRBSDATASEEDLSB_95_TO_64 */ "", 17322 /* DDR_BISTPRBSDATASEEDMSB31_TO_0 */ "", 17323 /* DDR_BISTPRBSDATASEEDMSB_127_TO_96 */ "", 17324 /* DDR_BISTPRBSDATASEEDMSB_63_TO_32 */ "", 17325 /* DDR_BISTPRBSDATASEEDMSB_95_TO_64 */ "", 17326 /* DDR_BISTREPEATPATTERN1LSB31_TO_0 */ "", 17327 /* DDR_BISTREPEATPATTERN1LSB_127_TO_96 */ "", 17328 /* DDR_BISTREPEATPATTERN1LSB_63_TO_32 */ "", 17329 /* DDR_BISTREPEATPATTERN1LSB_95_TO_64 */ "", 17330 /* DDR_BISTREPEATPATTERN1MSB31_TO_0 */ "", 17331 /* DDR_BISTREPEATPATTERN1MSB_127_TO_96 */ "", 17332 /* DDR_BISTREPEATPATTERN1MSB_63_TO_32 */ "", 17333 /* DDR_BISTREPEATPATTERN1MSB_95_TO_64 */ "", 17334 /* DDR_BISTREPEATPATTERN2LSB31_TO_0 */ "", 17335 /* DDR_BISTREPEATPATTERN2LSB_127_TO_96 */ "", 17336 /* DDR_BISTREPEATPATTERN2LSB_63_TO_32 */ "", 17337 /* DDR_BISTREPEATPATTERN2LSB_95_TO_64 */ "", 17338 /* DDR_BISTREPEATPATTERN2MSB31_TO_0 */ "", 17339 /* DDR_BISTREPEATPATTERN2MSB_127_TO_96 */ "", 17340 /* DDR_BISTREPEATPATTERN2MSB_63_TO_32 */ "", 17341 /* DDR_BISTREPEATPATTERN2MSB_95_TO_64 */ "", 17342 /* DDR_BISTREPEATPATTERN3LSB31_TO_0 */ "", 17343 /* DDR_BISTREPEATPATTERN3LSB_127_TO_96 */ "", 17344 /* DDR_BISTREPEATPATTERN3LSB_63_TO_32 */ "", 17345 /* DDR_BISTREPEATPATTERN3LSB_95_TO_64 */ "", 17346 /* DDR_BISTREPEATPATTERN3MSB31_TO_0 */ "", 17347 /* DDR_BISTREPEATPATTERN3MSB_127_TO_96 */ "", 17348 /* DDR_BISTREPEATPATTERN3MSB_63_TO_32 */ "", 17349 /* DDR_BISTREPEATPATTERN3MSB_95_TO_64 */ "", 17350 /* DDR_BISTREPEATPATTERN4LSB31_TO_0 */ "", 17351 /* DDR_BISTREPEATPATTERN4LSB_127_TO_96 */ "", 17352 /* DDR_BISTREPEATPATTERN4LSB_63_TO_32 */ "", 17353 /* DDR_BISTREPEATPATTERN4LSB_95_TO_64 */ "", 17354 /* DDR_BISTREPEATPATTERN4MSB31_TO_0 */ "", 17355 /* DDR_BISTREPEATPATTERN4MSB_127_TO_96 */ "", 17356 /* DDR_BISTREPEATPATTERN4MSB_63_TO_32 */ "", 17357 /* DDR_BISTREPEATPATTERN4MSB_95_TO_64 */ "", 17358 /* DDR_BISTREPEATPATTERN5LSB31_TO_0 */ "", 17359 /* DDR_BISTREPEATPATTERN5LSB_127_TO_96 */ "", 17360 /* DDR_BISTREPEATPATTERN5LSB_63_TO_32 */ "", 17361 /* DDR_BISTREPEATPATTERN5LSB_95_TO_64 */ "", 17362 /* DDR_BISTREPEATPATTERN5MSB31_TO_0 */ "", 17363 /* DDR_BISTREPEATPATTERN5MSB_127_TO_96 */ "", 17364 /* DDR_BISTREPEATPATTERN5MSB_63_TO_32 */ "", 17365 /* DDR_BISTREPEATPATTERN5MSB_95_TO_64 */ "", 17366 /* DDR_BISTREPEATPATTERN6LSB31_TO_0 */ "", 17367 /* DDR_BISTREPEATPATTERN6LSB_127_TO_96 */ "", 17368 /* DDR_BISTREPEATPATTERN6LSB_63_TO_32 */ "", 17369 /* DDR_BISTREPEATPATTERN6LSB_95_TO_64 */ "", 17370 /* DDR_BISTREPEATPATTERN6MSB31_TO_0 */ "", 17371 /* DDR_BISTREPEATPATTERN6MSB_127_TO_96 */ "", 17372 /* DDR_BISTREPEATPATTERN6MSB_63_TO_32 */ "", 17373 /* DDR_BISTREPEATPATTERN6MSB_95_TO_64 */ "", 17374 /* DDR_BISTREPEATPATTERN7LSB31_TO_0 */ "", 17375 /* DDR_BISTREPEATPATTERN7LSB_127_TO_96 */ "", 17376 /* DDR_BISTREPEATPATTERN7LSB_63_TO_32 */ "", 17377 /* DDR_BISTREPEATPATTERN7LSB_95_TO_64 */ "", 17378 /* DDR_BISTREPEATPATTERN7MSB31_TO_0 */ "", 17379 /* DDR_BISTREPEATPATTERN7MSB_127_TO_96 */ "", 17380 /* DDR_BISTREPEATPATTERN7MSB_63_TO_32 */ "", 17381 /* DDR_BISTREPEATPATTERN7MSB_95_TO_64 */ "", 17382 /* DDR_BISTSINGLEBITMASK */ "", 17383 /* DDR_BISTSINGLEBITMASKERRORCOUNTER */ "", 17384 /* DDR_BISTSTARTADDRESS */ "", 17385 /* DDR_BISTSTATUSES */ "", 17386 /* DDR_CNTBISTDBIERRGLOBAL */ "", 17387 /* DDR_CNTBISTEDCERRGLOBAL */ "", 17388 /* DDR_DENALI_CTL_00 */ "", 17389 /* DDR_DENALI_CTL_01 */ "", 17390 /* DDR_DENALI_CTL_02 */ "", 17391 /* DDR_DENALI_CTL_03 */ "", 17392 /* DDR_DENALI_CTL_04 */ "", 17393 /* DDR_DENALI_CTL_05 */ "", 17394 /* DDR_DENALI_CTL_06 */ "", 17395 /* DDR_DENALI_CTL_07 */ "", 17396 /* DDR_DENALI_CTL_08 */ "", 17397 /* DDR_DENALI_CTL_09 */ "", 17398 /* DDR_DENALI_CTL_10 */ "", 17399 /* DDR_DENALI_CTL_11 */ "", 17400 /* DDR_DENALI_CTL_12 */ "", 17401 /* DDR_DENALI_CTL_13 */ "", 17402 /* DDR_DENALI_CTL_14 */ "", 17403 /* DDR_DENALI_CTL_15 */ "", 17404 /* DDR_DENALI_CTL_16 */ "", 17405 /* DDR_DENALI_CTL_17 */ "", 17406 /* DDR_DENALI_CTL_18 */ "", 17407 /* DDR_DENALI_CTL_19 */ "", 17408 /* DDR_DENALI_CTL_20 */ "", 17409 /* DDR_DENALI_CTL_21 */ "", 17410 /* DDR_DENALI_CTL_22 */ "", 17411 /* DDR_DENALI_CTL_23 */ "", 17412 /* DDR_DENALI_CTL_24 */ "", 17413 /* DDR_DENALI_CTL_25 */ "", 17414 /* DDR_DENALI_CTL_26 */ "", 17415 /* DDR_DENALI_CTL_27 */ "", 17416 /* DDR_DENALI_CTL_28 */ "", 17417 /* DDR_DENALI_CTL_29 */ "", 17418 /* DDR_DENALI_CTL_30 */ "", 17419 /* DDR_DENALI_CTL_31 */ "", 17420 /* DDR_DENALI_CTL_32 */ "", 17421 /* DDR_DENALI_CTL_33 */ "", 17422 /* DDR_DENALI_CTL_34 */ "", 17423 /* DDR_DENALI_CTL_35 */ "", 17424 /* DDR_DENALI_CTL_36 */ "", 17425 /* DDR_DENALI_CTL_37 */ "", 17426 /* DDR_DENALI_CTL_38 */ "", 17427 /* DDR_DENALI_CTL_39 */ "", 17428 /* DDR_DENALI_CTL_40 */ "", 17429 /* DDR_DENALI_CTL_41 */ "", 17430 /* DDR_DENALI_CTL_42 */ "", 17431 /* DDR_DENALI_CTL_43 */ "", 17432 /* DDR_DENALI_CTL_44 */ "", 17433 /* DDR_DENALI_CTL_45 */ "", 17434 /* DDR_DENALI_CTL_46 */ "", 17435 /* DDR_DENALI_CTL_47 */ "", 17436 /* DDR_DENALI_CTL_48 */ "", 17437 /* DDR_DENALI_CTL_49 */ "", 17438 /* DDR_DENALI_CTL_50 */ "", 17439 /* DDR_DENALI_CTL_51 */ "", 17440 /* DDR_DENALI_CTL_52 */ "", 17441 /* DDR_DENALI_CTL_53 */ "", 17442 /* DDR_DENALI_CTL_54 */ "", 17443 /* DDR_DENALI_CTL_55 */ "", 17444 /* DDR_DENALI_CTL_56 */ "", 17445 /* DDR_DENALI_CTL_57 */ "", 17446 /* DDR_DENALI_CTL_58 */ "", 17447 /* DDR_DENALI_CTL_59 */ "", 17448 /* DDR_DENALI_CTL_60 */ "", 17449 /* DDR_DENALI_CTL_61 */ "", 17450 /* DDR_DENALI_CTL_62 */ "", 17451 /* DDR_DENALI_CTL_63 */ "", 17452 /* DDR_DENALI_CTL_64 */ "", 17453 /* DDR_DENALI_CTL_65 */ "", 17454 /* DDR_DENALI_CTL_66 */ "", 17455 /* DDR_DENALI_CTL_67 */ "", 17456 /* DDR_DENALI_CTL_68 */ "", 17457 /* DDR_DENALI_CTL_69 */ "", 17458 /* DDR_DENALI_CTL_70 */ "", 17459 /* DDR_DENALI_CTL_71 */ "", 17460 /* DDR_DENALI_CTL_72 */ "", 17461 /* DDR_DENALI_CTL_73 */ "", 17462 /* DDR_DENALI_CTL_74 */ "", 17463 /* DDR_DENALI_CTL_75 */ "", 17464 /* DDR_DENALI_CTL_76 */ "", 17465 /* DDR_DENALI_CTL_77 */ "", 17466 /* DDR_DENALI_CTL_78 */ "", 17467 /* DDR_DENALI_CTL_79 */ "", 17468 /* DDR_DENALI_CTL_80 */ "", 17469 /* DDR_DENALI_CTL_81 */ "", 17470 /* DDR_DENALI_CTL_82 */ "", 17471 /* DDR_DENALI_CTL_83 */ "", 17472 /* DDR_DENALI_CTL_84 */ "", 17473 /* DDR_DENALI_CTL_85 */ "", 17474 /* DDR_DENALI_CTL_86 */ "", 17475 /* DDR_DENALI_CTL_87 */ "", 17476 /* DDR_DENALI_CTL_88 */ "", 17477 /* DDR_DENALI_CTL_89 */ "", 17478 /* DDR_DENALI_CTL_90 */ "", 17479 /* DDR_DENALI_CTL_91 */ "", 17480 /* DDR_DENALI_CTL_92 */ "", 17481 /* DDR_DENALI_CTL_93 */ "", 17482 /* DDR_DENALI_CTL_94 */ "", 17483 /* DDR_DENALI_CTL_95 */ "", 17484 /* DDR_DENALI_CTL_96 */ "", 17485 /* DDR_DENALI_CTL_97 */ "", 17486 /* DDR_DENALI_CTL_98 */ "", 17487 /* DDR_DENALI_CTL_99 */ "", 17488 /* DDR_DENALI_CTL_100 */ "", 17489 /* DDR_DENALI_CTL_101 */ "", 17490 /* DDR_DENALI_CTL_102 */ "", 17491 /* DDR_DENALI_CTL_103 */ "", 17492 /* DDR_DENALI_CTL_104 */ "", 17493 /* DDR_DENALI_CTL_105 */ "", 17494 /* DDR_DENALI_CTL_106 */ "", 17495 /* DDR_DENALI_CTL_107 */ "", 17496 /* DDR_DENALI_CTL_108 */ "", 17497 /* DDR_DENALI_CTL_109 */ "", 17498 /* DDR_DENALI_CTL_110 */ "", 17499 /* DDR_DENALI_CTL_111 */ "", 17500 /* DDR_DENALI_CTL_112 */ "", 17501 /* DDR_DENALI_CTL_113 */ "", 17502 /* DDR_DENALI_CTL_114 */ "", 17503 /* DDR_DENALI_CTL_115 */ "", 17504 /* DDR_DENALI_CTL_116 */ "", 17505 /* DDR_DENALI_CTL_117 */ "", 17506 /* DDR_DENALI_CTL_118 */ "", 17507 /* DDR_DENALI_CTL_119 */ "", 17508 /* DDR_DENALI_CTL_120 */ "", 17509 /* DDR_DENALI_CTL_121 */ "", 17510 /* DDR_DENALI_CTL_122 */ "", 17511 /* DDR_DENALI_CTL_123 */ "", 17512 /* DDR_DENALI_CTL_124 */ "", 17513 /* DDR_DENALI_CTL_125 */ "", 17514 /* DDR_DENALI_CTL_126 */ "", 17515 /* DDR_DENALI_CTL_127 */ "", 17516 /* DDR_DENALI_CTL_128 */ "", 17517 /* DDR_DENALI_CTL_129 */ "", 17518 /* DDR_DENALI_CTL_130 */ "", 17519 /* DDR_DENALI_CTL_131 */ "", 17520 /* DDR_DENALI_CTL_132 */ "", 17521 /* DDR_DENALI_CTL_133 */ "", 17522 /* DDR_DENALI_CTL_134 */ "", 17523 /* DDR_DENALI_CTL_135 */ "", 17524 /* DDR_DENALI_CTL_136 */ "", 17525 /* DDR_DENALI_CTL_137 */ "", 17526 /* DDR_DENALI_CTL_138 */ "", 17527 /* DDR_DENALI_CTL_139 */ "", 17528 /* DDR_DENALI_CTL_140 */ "", 17529 /* DDR_DENALI_CTL_141 */ "", 17530 /* DDR_DENALI_CTL_142 */ "", 17531 /* DDR_DENALI_CTL_143 */ "", 17532 /* DDR_DENALI_CTL_144 */ "", 17533 /* DDR_DENALI_CTL_145 */ "", 17534 /* DDR_DENALI_CTL_146 */ "", 17535 /* DDR_DENALI_CTL_147 */ "", 17536 /* DDR_DENALI_CTL_148 */ "", 17537 /* DDR_DENALI_CTL_149 */ "", 17538 /* DDR_DENALI_CTL_150 */ "", 17539 /* DDR_DENALI_CTL_151 */ "", 17540 /* DDR_DENALI_CTL_152 */ "", 17541 /* DDR_DENALI_CTL_153 */ "", 17542 /* DDR_DENALI_CTL_154 */ "", 17543 /* DDR_DENALI_CTL_155 */ "", 17544 /* DDR_DENALI_CTL_156 */ "", 17545 /* DDR_DENALI_CTL_157 */ "", 17546 /* DDR_DENALI_CTL_158 */ "", 17547 /* DDR_DENALI_CTL_159 */ "", 17548 /* DDR_DENALI_CTL_160 */ "", 17549 /* DDR_DENALI_CTL_161 */ "", 17550 /* DDR_DENALI_CTL_162 */ "", 17551 /* DDR_DENALI_CTL_163 */ "", 17552 /* DDR_DENALI_CTL_164 */ "", 17553 /* DDR_DENALI_CTL_165 */ "", 17554 /* DDR_DENALI_CTL_166 */ "", 17555 /* DDR_DENALI_CTL_167 */ "", 17556 /* DDR_DENALI_CTL_168 */ "", 17557 /* DDR_DENALI_CTL_169 */ "", 17558 /* DDR_DENALI_CTL_170 */ "", 17559 /* DDR_DENALI_CTL_171 */ "", 17560 /* DDR_DENALI_CTL_172 */ "", 17561 /* DDR_DENALI_CTL_173 */ "", 17562 /* DDR_DENALI_CTL_174 */ "", 17563 /* DDR_DENALI_CTL_175 */ "", 17564 /* DDR_DENALI_CTL_176 */ "", 17565 /* DDR_DENALI_CTL_177 */ "", 17566 /* DDR_DENALI_CTL_178 */ "", 17567 /* DDR_DENALI_CTL_179 */ "", 17568 /* DDR_DENALI_CTL_180 */ "", 17569 /* DDR_DENALI_CTL_181 */ "", 17570 /* DDR_DENALI_CTL_182 */ "", 17571 /* DDR_DENALI_CTL_183 */ "", 17572 /* DDR_DENALI_CTL_184 */ "", 17573 /* DDR_DENALI_CTL_185 */ "", 17574 /* DDR_DENALI_CTL_186 */ "", 17575 /* DDR_DENALI_CTL_187 */ "", 17576 /* DDR_DENALI_CTL_188 */ "", 17577 /* DDR_DENALI_CTL_189 */ "", 17578 /* DDR_DENALI_CTL_190 */ "", 17579 /* DDR_DENALI_CTL_191 */ "", 17580 /* DDR_DENALI_CTL_192 */ "", 17581 /* DDR_DENALI_CTL_193 */ "", 17582 /* DDR_DENALI_CTL_194 */ "", 17583 /* DDR_DENALI_CTL_195 */ "", 17584 /* DDR_DENALI_CTL_196 */ "", 17585 /* DDR_DENALI_CTL_197 */ "", 17586 /* DDR_DENALI_CTL_198 */ "", 17587 /* DDR_DENALI_CTL_199 */ "", 17588 /* DDR_DENALI_CTL_200 */ "", 17589 /* DDR_DENALI_CTL_201 */ "", 17590 /* DDR_DENALI_CTL_202 */ "", 17591 /* DDR_DENALI_CTL_203 */ "", 17592 /* DDR_DENALI_CTL_204 */ "", 17593 /* DDR_DENALI_CTL_205 */ "", 17594 /* DDR_DENALI_CTL_206 */ "", 17595 /* DDR_DENALI_CTL_207 */ "", 17596 /* DDR_DENALI_CTL_208 */ "", 17597 /* DDR_DENALI_CTL_209 */ "", 17598 /* DDR_DENALI_CTL_210 */ "", 17599 /* DDR_DENALI_CTL_211 */ "", 17600 /* DDR_DENALI_CTL_212 */ "", 17601 /* DDR_DENALI_CTL_213 */ "", 17602 /* DDR_DENALI_CTL_214 */ "", 17603 /* DDR_DENALI_CTL_215 */ "", 17604 /* DDR_DENALI_CTL_216 */ "", 17605 /* DDR_DENALI_CTL_217 */ "", 17606 /* DDR_DENALI_CTL_218 */ "", 17607 /* DDR_DENALI_CTL_219 */ "", 17608 /* DDR_DENALI_CTL_220 */ "", 17609 /* DDR_DENALI_CTL_221 */ "", 17610 /* DDR_DENALI_CTL_222 */ "", 17611 /* DDR_DENALI_CTL_223 */ "", 17612 /* DDR_DENALI_CTL_224 */ "", 17613 /* DDR_DENALI_CTL_225 */ "", 17614 /* DDR_DENALI_CTL_226 */ "", 17615 /* DDR_DENALI_CTL_227 */ "", 17616 /* DDR_DENALI_CTL_228 */ "", 17617 /* DDR_DENALI_CTL_229 */ "", 17618 /* DDR_DENALI_CTL_230 */ "", 17619 /* DDR_DENALI_CTL_231 */ "", 17620 /* DDR_DENALI_CTL_232 */ "", 17621 /* DDR_DENALI_CTL_233 */ "", 17622 /* DDR_DENALI_CTL_234 */ "", 17623 /* DDR_DENALI_CTL_235 */ "", 17624 /* DDR_DENALI_CTL_236 */ "", 17625 /* DDR_DENALI_CTL_237 */ "", 17626 /* DDR_DENALI_CTL_238 */ "", 17627 /* DDR_DENALI_CTL_239 */ "", 17628 /* DDR_DENALI_CTL_240 */ "", 17629 /* DDR_DENALI_CTL_241 */ "", 17630 /* DDR_DENALI_CTL_242 */ "", 17631 /* DDR_DENALI_CTL_243 */ "", 17632 /* DDR_DENALI_CTL_245 */ "", 17633 /* DDR_DENALI_CTL_246 */ "", 17634 /* DDR_DENALI_CTL_247 */ "", 17635 /* DDR_DENALI_CTL_248 */ "", 17636 /* DDR_DENALI_CTL_249 */ "", 17637 /* DDR_DENALI_CTL_250 */ "", 17638 /* DDR_DENALI_CTL_251 */ "", 17639 /* DDR_DENALI_CTL_252 */ "", 17640 /* DDR_DENALI_CTL_253 */ "", 17641 /* DDR_DENALI_CTL_254 */ "", 17642 /* DDR_DENALI_CTL_255 */ "", 17643 /* DDR_DENALI_CTL_256 */ "", 17644 /* DDR_DENALI_CTL_257 */ "", 17645 /* DDR_DENALI_CTL_258 */ "", 17646 /* DDR_DENALI_CTL_259 */ "", 17647 /* DDR_DENALI_CTL_260 */ "", 17648 /* DDR_DENALI_CTL_261 */ "", 17649 /* DDR_DENALI_CTL_262 */ "", 17650 /* DDR_DENALI_CTL_263 */ "", 17651 /* DDR_DENALI_CTL_264 */ "", 17652 /* DDR_DENALI_CTL_265 */ "", 17653 /* DDR_DENALI_CTL_266 */ "", 17654 /* DDR_DENALI_CTL_267 */ "", 17655 /* DDR_DENALI_CTL_268 */ "", 17656 /* DDR_DENALI_CTL_269 */ "", 17657 /* DDR_DENALI_CTL_270 */ "", 17658 /* DDR_DENALI_CTL_271 */ "", 17659 /* DDR_DENALI_CTL_272 */ "", 17660 /* DDR_DENALI_CTL_273 */ "", 17661 /* DDR_DENALI_CTL_274 */ "", 17662 /* DDR_DENALI_CTL_275 */ "", 17663 /* DDR_DENALI_CTL_276 */ "", 17664 /* DDR_DENALI_CTL_277 */ "", 17665 /* DDR_DENALI_CTL_278 */ "", 17666 /* DDR_DENALI_CTL_279 */ "", 17667 /* DDR_DENALI_CTL_280 */ "", 17668 /* DDR_DENALI_CTL_281 */ "", 17669 /* DDR_DENALI_CTL_282 */ "", 17670 /* DDR_DENALI_CTL_283 */ "", 17671 /* DDR_DENALI_CTL_284 */ "", 17672 /* DDR_DENALI_CTL_285 */ "", 17673 /* DDR_DENALI_CTL_286 */ "", 17674 /* DDR_DENALI_CTL_287 */ "", 17675 /* DDR_DENALI_CTL_288 */ "", 17676 /* DDR_DENALI_CTL_289 */ "", 17677 /* DDR_DENALI_CTL_290 */ "", 17678 /* DDR_DENALI_CTL_291 */ "", 17679 /* DDR_DENALI_CTL_292 */ "", 17680 /* DDR_DENALI_CTL_293 */ "", 17681 /* DDR_DENALI_CTL_294 */ "", 17682 /* DDR_DENALI_CTL_295 */ "", 17683 /* DDR_DENALI_CTL_296 */ "", 17684 /* DDR_DENALI_CTL_297 */ "", 17685 /* DDR_DENALI_CTL_298 */ "", 17686 /* DDR_DENALI_CTL_299 */ "", 17687 /* DDR_DENALI_CTL_300 */ "", 17688 /* DDR_DENALI_CTL_301 */ "", 17689 /* DDR_DENALI_CTL_302 */ "", 17690 /* DDR_DENALI_CTL_303 */ "", 17691 /* DDR_DENALI_CTL_304 */ "", 17692 /* DDR_DRAMSPECIALFEATURES */ "", 17693 /* DDR_GDDR5BISTFINISHPRD */ "", 17694 /* DDR_INTIALCALIBUSEMPR */ "", 17695 /* DDR_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL */ "", 17696 /* DDR_PHY_BYTE_LANE_0_BL_SPARE_REG */ "", 17697 /* DDR_PHY_BYTE_LANE_0_CLOCK_ENABLE */ "", 17698 /* DDR_PHY_BYTE_LANE_0_CLOCK_IDLE */ "", 17699 /* DDR_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL */ "", 17700 /* DDR_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL */ "", 17701 /* DDR_PHY_BYTE_LANE_0_DQS_RX_TRIM */ "", 17702 /* DDR_PHY_BYTE_LANE_0_DQ_RX_TRIM */ "", 17703 /* DDR_PHY_BYTE_LANE_0_DRIVE_PAD_CTL */ "", 17704 /* DDR_PHY_BYTE_LANE_0_EDC_CRC_CONTROL */ "", 17705 /* DDR_PHY_BYTE_LANE_0_EDC_CRC_COUNT */ "", 17706 /* DDR_PHY_BYTE_LANE_0_EDC_CRC_STATUS */ "", 17707 /* DDR_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR */ "", 17708 /* DDR_PHY_BYTE_LANE_0_EDC_DPD_CONTROL */ "", 17709 /* DDR_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL */ "", 17710 /* DDR_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS */ "", 17711 /* DDR_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR */ "", 17712 /* DDR_PHY_BYTE_LANE_0_EDC_DPD_STATUS */ "", 17713 /* DDR_PHY_BYTE_LANE_0_EDC_DRIVE_PAD_CTL */ "", 17714 /* DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL */ "", 17715 /* DDR_PHY_BYTE_LANE_0_LDO_CONFIG */ "", 17716 /* DDR_PHY_BYTE_LANE_0_MISC_RX_TRIM */ "", 17717 /* DDR_PHY_BYTE_LANE_0_ODT_CONTROL */ "", 17718 /* DDR_PHY_BYTE_LANE_0_RD_EN_DLY_CYC */ "", 17719 /* DDR_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL */ "", 17720 /* DDR_PHY_BYTE_LANE_0_READ_CONTROL */ "", 17721 /* DDR_PHY_BYTE_LANE_0_READ_FIFO_ADDR */ "", 17722 /* DDR_PHY_BYTE_LANE_0_READ_FIFO_CLEAR */ "", 17723 /* DDR_PHY_BYTE_LANE_0_READ_FIFO_DATA */ "", 17724 /* DDR_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI */ "", 17725 /* DDR_PHY_BYTE_LANE_0_READ_FIFO_STATUS */ "", 17726 /* DDR_PHY_BYTE_LANE_0_STATIC_PAD_CTL */ "", 17727 /* DDR_PHY_BYTE_LANE_0_VDL_CLK_CONTROL */ "", 17728 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN */ "", 17729 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP */ "", 17730 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N */ "", 17731 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P */ "", 17732 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N */ "", 17733 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P */ "", 17734 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N */ "", 17735 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P */ "", 17736 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N */ "", 17737 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P */ "", 17738 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N */ "", 17739 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P */ "", 17740 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N */ "", 17741 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P */ "", 17742 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N */ "", 17743 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P */ "", 17744 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N */ "", 17745 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P */ "", 17746 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN */ "", 17747 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP */ "", 17748 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN */ "", 17749 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP */ "", 17750 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CRC */ "", 17751 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0 */ "", 17752 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1 */ "", 17753 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_ALERT */ "", 17754 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM */ "", 17755 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0 */ "", 17756 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1 */ "", 17757 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2 */ "", 17758 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3 */ "", 17759 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4 */ "", 17760 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5 */ "", 17761 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6 */ "", 17762 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7 */ "", 17763 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS */ "", 17764 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N */ "", 17765 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P */ "", 17766 /* DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC */ "", 17767 /* DDR_PHY_BYTE_LANE_0_VDL_LDE_CONTROL */ "", 17768 /* DDR_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC */ "", 17769 /* DDR_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE */ "", 17770 /* DDR_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL */ "", 17771 /* DDR_PHY_BYTE_LANE_1_BL_SPARE_REG */ "", 17772 /* DDR_PHY_BYTE_LANE_1_CLOCK_ENABLE */ "", 17773 /* DDR_PHY_BYTE_LANE_1_CLOCK_IDLE */ "", 17774 /* DDR_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL */ "", 17775 /* DDR_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL */ "", 17776 /* DDR_PHY_BYTE_LANE_1_DQS_RX_TRIM */ "", 17777 /* DDR_PHY_BYTE_LANE_1_DQ_RX_TRIM */ "", 17778 /* DDR_PHY_BYTE_LANE_1_DRIVE_PAD_CTL */ "", 17779 /* DDR_PHY_BYTE_LANE_1_EDC_CRC_CONTROL */ "", 17780 /* DDR_PHY_BYTE_LANE_1_EDC_CRC_COUNT */ "", 17781 /* DDR_PHY_BYTE_LANE_1_EDC_CRC_STATUS */ "", 17782 /* DDR_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR */ "", 17783 /* DDR_PHY_BYTE_LANE_1_EDC_DPD_CONTROL */ "", 17784 /* DDR_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL */ "", 17785 /* DDR_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS */ "", 17786 /* DDR_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR */ "", 17787 /* DDR_PHY_BYTE_LANE_1_EDC_DPD_STATUS */ "", 17788 /* DDR_PHY_BYTE_LANE_1_EDC_DRIVE_PAD_CTL */ "", 17789 /* DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL */ "", 17790 /* DDR_PHY_BYTE_LANE_1_LDO_CONFIG */ "", 17791 /* DDR_PHY_BYTE_LANE_1_MISC_RX_TRIM */ "", 17792 /* DDR_PHY_BYTE_LANE_1_ODT_CONTROL */ "", 17793 /* DDR_PHY_BYTE_LANE_1_RD_EN_DLY_CYC */ "", 17794 /* DDR_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL */ "", 17795 /* DDR_PHY_BYTE_LANE_1_READ_CONTROL */ "", 17796 /* DDR_PHY_BYTE_LANE_1_READ_FIFO_ADDR */ "", 17797 /* DDR_PHY_BYTE_LANE_1_READ_FIFO_CLEAR */ "", 17798 /* DDR_PHY_BYTE_LANE_1_READ_FIFO_DATA */ "", 17799 /* DDR_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI */ "", 17800 /* DDR_PHY_BYTE_LANE_1_READ_FIFO_STATUS */ "", 17801 /* DDR_PHY_BYTE_LANE_1_STATIC_PAD_CTL */ "", 17802 /* DDR_PHY_BYTE_LANE_1_VDL_CLK_CONTROL */ "", 17803 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN */ "", 17804 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP */ "", 17805 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N */ "", 17806 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P */ "", 17807 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N */ "", 17808 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P */ "", 17809 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N */ "", 17810 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P */ "", 17811 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N */ "", 17812 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P */ "", 17813 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N */ "", 17814 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P */ "", 17815 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N */ "", 17816 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P */ "", 17817 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N */ "", 17818 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P */ "", 17819 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N */ "", 17820 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P */ "", 17821 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN */ "", 17822 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP */ "", 17823 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN */ "", 17824 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP */ "", 17825 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CRC */ "", 17826 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0 */ "", 17827 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1 */ "", 17828 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_ALERT */ "", 17829 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM */ "", 17830 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0 */ "", 17831 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1 */ "", 17832 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2 */ "", 17833 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3 */ "", 17834 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4 */ "", 17835 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5 */ "", 17836 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6 */ "", 17837 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7 */ "", 17838 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS */ "", 17839 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N */ "", 17840 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P */ "", 17841 /* DDR_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC */ "", 17842 /* DDR_PHY_BYTE_LANE_1_VDL_LDE_CONTROL */ "", 17843 /* DDR_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC */ "", 17844 /* DDR_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE */ "", 17845 /* DDR_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL */ "", 17846 /* DDR_PHY_BYTE_LANE_2_BL_SPARE_REG */ "", 17847 /* DDR_PHY_BYTE_LANE_2_CLOCK_ENABLE */ "", 17848 /* DDR_PHY_BYTE_LANE_2_CLOCK_IDLE */ "", 17849 /* DDR_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL */ "", 17850 /* DDR_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL */ "", 17851 /* DDR_PHY_BYTE_LANE_2_DQS_RX_TRIM */ "", 17852 /* DDR_PHY_BYTE_LANE_2_DQ_RX_TRIM */ "", 17853 /* DDR_PHY_BYTE_LANE_2_DRIVE_PAD_CTL */ "", 17854 /* DDR_PHY_BYTE_LANE_2_EDC_CRC_CONTROL */ "", 17855 /* DDR_PHY_BYTE_LANE_2_EDC_CRC_COUNT */ "", 17856 /* DDR_PHY_BYTE_LANE_2_EDC_CRC_STATUS */ "", 17857 /* DDR_PHY_BYTE_LANE_2_EDC_CRC_STATUS_CLEAR */ "", 17858 /* DDR_PHY_BYTE_LANE_2_EDC_DPD_CONTROL */ "", 17859 /* DDR_PHY_BYTE_LANE_2_EDC_DPD_OUT_CONTROL */ "", 17860 /* DDR_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS */ "", 17861 /* DDR_PHY_BYTE_LANE_2_EDC_DPD_OUT_STATUS_CLEAR */ "", 17862 /* DDR_PHY_BYTE_LANE_2_EDC_DPD_STATUS */ "", 17863 /* DDR_PHY_BYTE_LANE_2_EDC_DRIVE_PAD_CTL */ "", 17864 /* DDR_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL */ "", 17865 /* DDR_PHY_BYTE_LANE_2_LDO_CONFIG */ "", 17866 /* DDR_PHY_BYTE_LANE_2_MISC_RX_TRIM */ "", 17867 /* DDR_PHY_BYTE_LANE_2_ODT_CONTROL */ "", 17868 /* DDR_PHY_BYTE_LANE_2_RD_EN_DLY_CYC */ "", 17869 /* DDR_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL */ "", 17870 /* DDR_PHY_BYTE_LANE_2_READ_CONTROL */ "", 17871 /* DDR_PHY_BYTE_LANE_2_READ_FIFO_ADDR */ "", 17872 /* DDR_PHY_BYTE_LANE_2_READ_FIFO_CLEAR */ "", 17873 /* DDR_PHY_BYTE_LANE_2_READ_FIFO_DATA */ "", 17874 /* DDR_PHY_BYTE_LANE_2_READ_FIFO_DM_DBI */ "", 17875 /* DDR_PHY_BYTE_LANE_2_READ_FIFO_STATUS */ "", 17876 /* DDR_PHY_BYTE_LANE_2_STATIC_PAD_CTL */ "", 17877 /* DDR_PHY_BYTE_LANE_2_VDL_CLK_CONTROL */ "", 17878 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN */ "", 17879 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP */ "", 17880 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N */ "", 17881 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P */ "", 17882 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N */ "", 17883 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P */ "", 17884 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N */ "", 17885 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P */ "", 17886 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N */ "", 17887 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P */ "", 17888 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N */ "", 17889 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P */ "", 17890 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N */ "", 17891 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P */ "", 17892 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N */ "", 17893 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P */ "", 17894 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N */ "", 17895 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P */ "", 17896 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN */ "", 17897 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP */ "", 17898 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN */ "", 17899 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP */ "", 17900 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CRC */ "", 17901 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0 */ "", 17902 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1 */ "", 17903 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_ALERT */ "", 17904 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM */ "", 17905 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0 */ "", 17906 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1 */ "", 17907 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2 */ "", 17908 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3 */ "", 17909 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4 */ "", 17910 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5 */ "", 17911 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6 */ "", 17912 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7 */ "", 17913 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS */ "", 17914 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N */ "", 17915 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P */ "", 17916 /* DDR_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC */ "", 17917 /* DDR_PHY_BYTE_LANE_2_VDL_LDE_CONTROL */ "", 17918 /* DDR_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC */ "", 17919 /* DDR_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE */ "", 17920 /* DDR_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL */ "", 17921 /* DDR_PHY_BYTE_LANE_3_BL_SPARE_REG */ "", 17922 /* DDR_PHY_BYTE_LANE_3_CLOCK_ENABLE */ "", 17923 /* DDR_PHY_BYTE_LANE_3_CLOCK_IDLE */ "", 17924 /* DDR_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL */ "", 17925 /* DDR_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL */ "", 17926 /* DDR_PHY_BYTE_LANE_3_DQS_RX_TRIM */ "", 17927 /* DDR_PHY_BYTE_LANE_3_DQ_RX_TRIM */ "", 17928 /* DDR_PHY_BYTE_LANE_3_DRIVE_PAD_CTL */ "", 17929 /* DDR_PHY_BYTE_LANE_3_EDC_CRC_CONTROL */ "", 17930 /* DDR_PHY_BYTE_LANE_3_EDC_CRC_COUNT */ "", 17931 /* DDR_PHY_BYTE_LANE_3_EDC_CRC_STATUS */ "", 17932 /* DDR_PHY_BYTE_LANE_3_EDC_CRC_STATUS_CLEAR */ "", 17933 /* DDR_PHY_BYTE_LANE_3_EDC_DPD_CONTROL */ "", 17934 /* DDR_PHY_BYTE_LANE_3_EDC_DPD_OUT_CONTROL */ "", 17935 /* DDR_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS */ "", 17936 /* DDR_PHY_BYTE_LANE_3_EDC_DPD_OUT_STATUS_CLEAR */ "", 17937 /* DDR_PHY_BYTE_LANE_3_EDC_DPD_STATUS */ "", 17938 /* DDR_PHY_BYTE_LANE_3_EDC_DRIVE_PAD_CTL */ "", 17939 /* DDR_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL */ "", 17940 /* DDR_PHY_BYTE_LANE_3_LDO_CONFIG */ "", 17941 /* DDR_PHY_BYTE_LANE_3_MISC_RX_TRIM */ "", 17942 /* DDR_PHY_BYTE_LANE_3_ODT_CONTROL */ "", 17943 /* DDR_PHY_BYTE_LANE_3_RD_EN_DLY_CYC */ "", 17944 /* DDR_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL */ "", 17945 /* DDR_PHY_BYTE_LANE_3_READ_CONTROL */ "", 17946 /* DDR_PHY_BYTE_LANE_3_READ_FIFO_ADDR */ "", 17947 /* DDR_PHY_BYTE_LANE_3_READ_FIFO_CLEAR */ "", 17948 /* DDR_PHY_BYTE_LANE_3_READ_FIFO_DATA */ "", 17949 /* DDR_PHY_BYTE_LANE_3_READ_FIFO_DM_DBI */ "", 17950 /* DDR_PHY_BYTE_LANE_3_READ_FIFO_STATUS */ "", 17951 /* DDR_PHY_BYTE_LANE_3_STATIC_PAD_CTL */ "", 17952 /* DDR_PHY_BYTE_LANE_3_VDL_CLK_CONTROL */ "", 17953 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN */ "", 17954 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP */ "", 17955 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N */ "", 17956 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P */ "", 17957 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N */ "", 17958 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P */ "", 17959 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N */ "", 17960 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P */ "", 17961 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N */ "", 17962 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P */ "", 17963 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N */ "", 17964 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P */ "", 17965 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N */ "", 17966 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P */ "", 17967 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N */ "", 17968 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P */ "", 17969 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N */ "", 17970 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P */ "", 17971 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN */ "", 17972 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP */ "", 17973 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN */ "", 17974 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP */ "", 17975 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CRC */ "", 17976 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0 */ "", 17977 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1 */ "", 17978 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_ALERT */ "", 17979 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM */ "", 17980 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0 */ "", 17981 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1 */ "", 17982 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2 */ "", 17983 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3 */ "", 17984 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4 */ "", 17985 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5 */ "", 17986 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6 */ "", 17987 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7 */ "", 17988 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS */ "", 17989 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N */ "", 17990 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P */ "", 17991 /* DDR_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC */ "", 17992 /* DDR_PHY_BYTE_LANE_3_VDL_LDE_CONTROL */ "", 17993 /* DDR_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC */ "", 17994 /* DDR_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE */ "", 17995 /* DDR_PHY_CONTROL_REGS_ABI_PAR_CNTRL */ "", 17996 /* DDR_PHY_CONTROL_REGS_AC_SPARE_REG */ "", 17997 /* DDR_PHY_CONTROL_REGS_ALERT_CLEAR */ "", 17998 /* DDR_PHY_CONTROL_REGS_ALERT_DFI */ "", 17999 /* DDR_PHY_CONTROL_REGS_ALERT_STATUS */ "", 18000 /* DDR_PHY_CONTROL_REGS_AUX_CONTROL */ "", 18001 /* DDR_PHY_CONTROL_REGS_BYTE_LANE_ALIGN_MASKS */ "", 18002 /* DDR_PHY_CONTROL_REGS_CA_PARITY */ "", 18003 /* DDR_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL */ "", 18004 /* DDR_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0 */ "", 18005 /* DDR_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS1 */ "", 18006 /* DDR_PHY_CONTROL_REGS_CK_DRIVE_PAD_CTL */ "", 18007 /* DDR_PHY_CONTROL_REGS_CLK_PM_CTRL */ "", 18008 /* DDR_PHY_CONTROL_REGS_CLOCK_IDLE */ "", 18009 /* DDR_PHY_CONTROL_REGS_CMD_CYC_DLY */ "", 18010 /* DDR_PHY_CONTROL_REGS_COMMAND_AUX_REG1 */ "", 18011 /* DDR_PHY_CONTROL_REGS_COMMAND_AUX_REG2 */ "", 18012 /* DDR_PHY_CONTROL_REGS_COMMAND_AUX_REG3 */ "", 18013 /* DDR_PHY_CONTROL_REGS_COMMAND_AUX_REG4 */ "", 18014 /* DDR_PHY_CONTROL_REGS_COMMAND_REG */ "", 18015 /* DDR_PHY_CONTROL_REGS_COMMAND_REG1 */ "", 18016 /* DDR_PHY_CONTROL_REGS_COMMAND_REG2 */ "", 18017 /* DDR_PHY_CONTROL_REGS_COMMAND_REG3 */ "", 18018 /* DDR_PHY_CONTROL_REGS_COMMAND_REG4 */ "", 18019 /* DDR_PHY_CONTROL_REGS_COMMAND_REG_TIMER */ "", 18020 /* DDR_PHY_CONTROL_REGS_COMR_CAL */ "", 18021 /* DDR_PHY_CONTROL_REGS_DATAPATH_LOOPBACK */ "", 18022 /* DDR_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE */ "", 18023 /* DDR_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL */ "", 18024 /* DDR_PHY_CONTROL_REGS_DFI_CNTRL */ "", 18025 /* DDR_PHY_CONTROL_REGS_DRAM_CONFIG */ "", 18026 /* DDR_PHY_CONTROL_REGS_DRAM_TIMING1 */ "", 18027 /* DDR_PHY_CONTROL_REGS_DRAM_TIMING2 */ "", 18028 /* DDR_PHY_CONTROL_REGS_DRAM_TIMING3 */ "", 18029 /* DDR_PHY_CONTROL_REGS_DRAM_TIMING4 */ "", 18030 /* DDR_PHY_CONTROL_REGS_DRIVE_PAD_CTL */ "", 18031 /* DDR_PHY_CONTROL_REGS_DRIVE_PAD_CTL_2T */ "", 18032 /* DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL */ "", 18033 /* DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 */ "", 18034 /* DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 */ "", 18035 /* DDR_PHY_CONTROL_REGS_LDO_COMP_CONTROL */ "", 18036 /* DDR_PHY_CONTROL_REGS_MODE_REG0 */ "", 18037 /* DDR_PHY_CONTROL_REGS_MODE_REG1 */ "", 18038 /* DDR_PHY_CONTROL_REGS_MODE_REG2 */ "", 18039 /* DDR_PHY_CONTROL_REGS_MODE_REG3 */ "", 18040 /* DDR_PHY_CONTROL_REGS_MODE_REG4 */ "", 18041 /* DDR_PHY_CONTROL_REGS_MODE_REG5 */ "", 18042 /* DDR_PHY_CONTROL_REGS_MODE_REG6 */ "", 18043 /* DDR_PHY_CONTROL_REGS_MODE_REG7 */ "", 18044 /* DDR_PHY_CONTROL_REGS_MODE_REG8 */ "", 18045 /* DDR_PHY_CONTROL_REGS_MODE_REG15 */ "", 18046 /* DDR_PHY_CONTROL_REGS_MODE_REG63 */ "", 18047 /* DDR_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS */ "", 18048 /* DDR_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS */ "", 18049 /* DDR_PHY_CONTROL_REGS_PHYBIST_BL2_STATUS */ "", 18050 /* DDR_PHY_CONTROL_REGS_PHYBIST_BL3_STATUS */ "", 18051 /* DDR_PHY_CONTROL_REGS_PHYBIST_BL4_STATUS */ "", 18052 /* DDR_PHY_CONTROL_REGS_PHYBIST_CA_MASK */ "", 18053 /* DDR_PHY_CONTROL_REGS_PHYBIST_CNTRL */ "", 18054 /* DDR_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS */ "", 18055 /* DDR_PHY_CONTROL_REGS_PHYBIST_DQ_MASK1 */ "", 18056 /* DDR_PHY_CONTROL_REGS_PHYBIST_DQ_MASK2 */ "", 18057 /* DDR_PHY_CONTROL_REGS_PHYBIST_DQ_STATUS */ "", 18058 /* DDR_PHY_CONTROL_REGS_PHYBIST_MISC_STATUS */ "", 18059 /* DDR_PHY_CONTROL_REGS_PHYBIST_SEED */ "", 18060 /* DDR_PHY_CONTROL_REGS_PHYBIST_STATUS */ "", 18061 /* DDR_PHY_CONTROL_REGS_PLL_CONFIG */ "", 18062 /* DDR_PHY_CONTROL_REGS_PLL_CONTROL */ "", 18063 /* DDR_PHY_CONTROL_REGS_PLL_CONTROL1 */ "", 18064 /* DDR_PHY_CONTROL_REGS_PLL_CONTROL2 */ "", 18065 /* DDR_PHY_CONTROL_REGS_PLL_CONTROL3 */ "", 18066 /* DDR_PHY_CONTROL_REGS_PLL_DIVIDERS */ "", 18067 /* DDR_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER */ "", 18068 /* DDR_PHY_CONTROL_REGS_PLL_SS_CONTROL */ "", 18069 /* DDR_PHY_CONTROL_REGS_PLL_SS_LIMIT */ "", 18070 /* DDR_PHY_CONTROL_REGS_PLL_STATUS */ "", 18071 /* DDR_PHY_CONTROL_REGS_READ_ENABLE_CONTROL */ "", 18072 /* DDR_PHY_CONTROL_REGS_READ_ENABLE_STATUS */ "", 18073 /* DDR_PHY_CONTROL_REGS_REFRESH */ "", 18074 /* DDR_PHY_CONTROL_REGS_REVISION */ "", 18075 /* DDR_PHY_CONTROL_REGS_RO_PROC_MON_CTL */ "", 18076 /* DDR_PHY_CONTROL_REGS_RO_PROC_MON_STATUS */ "", 18077 /* DDR_PHY_CONTROL_REGS_RX_TRIM */ "", 18078 /* DDR_PHY_CONTROL_REGS_STANDBY_CONTROL */ "", 18079 /* DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL */ "", 18080 /* DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_2T */ "", 18081 /* DDR_PHY_CONTROL_REGS_STRAP_CONTROL */ "", 18082 /* DDR_PHY_CONTROL_REGS_STRAP_CONTROL2 */ "", 18083 /* DDR_PHY_CONTROL_REGS_STRAP_STATUS */ "", 18084 /* DDR_PHY_CONTROL_REGS_STRAP_STATUS2 */ "", 18085 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1 */ "", 18086 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2 */ "", 18087 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL */ "", 18088 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL */ "", 18089 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK */ "", 18090 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS */ "", 18091 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK */ "", 18092 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS */ "", 18093 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL */ "", 18094 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS */ "", 18095 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED */ "", 18096 /* DDR_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS */ "", 18097 /* DDR_PHY_CONTROL_REGS_UPDATE_VDL */ "", 18098 /* DDR_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1 */ "", 18099 /* DDR_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2 */ "", 18100 /* DDR_PHY_CONTROL_REGS_VDL_CALIBRATE */ "", 18101 /* DDR_PHY_CONTROL_REGS_VDL_CALIB_STATUS */ "", 18102 /* DDR_PHY_CONTROL_REGS_VDL_CALIB_STATUS1 */ "", 18103 /* DDR_PHY_CONTROL_REGS_VDL_CALIB_STATUS2 */ "", 18104 /* DDR_PHY_CONTROL_REGS_VDL_CALIB_STATUS_ECC */ "", 18105 /* DDR_PHY_CONTROL_REGS_VDL_CLK_CONTROL */ "", 18106 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD00 */ "", 18107 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD01 */ "", 18108 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD02 */ "", 18109 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD03 */ "", 18110 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD04 */ "", 18111 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD05 */ "", 18112 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD06 */ "", 18113 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD07 */ "", 18114 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD08 */ "", 18115 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD09 */ "", 18116 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD10 */ "", 18117 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD11 */ "", 18118 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD12 */ "", 18119 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD13 */ "", 18120 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD14 */ "", 18121 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AD15 */ "", 18122 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AUX0 */ "", 18123 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AUX1 */ "", 18124 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_AUX2 */ "", 18125 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_BA0 */ "", 18126 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_BA1 */ "", 18127 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_BA2 */ "", 18128 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N */ "", 18129 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_CKE */ "", 18130 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_CS0 */ "", 18131 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_CS1 */ "", 18132 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK */ "", 18133 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N */ "", 18134 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P */ "", 18135 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_ODT */ "", 18136 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_PAR */ "", 18137 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N */ "", 18138 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_RST_N */ "", 18139 /* DDR_PHY_CONTROL_REGS_VDL_CONTROL_WE_N */ "", 18140 /* DDR_PHY_CONTROL_REGS_VDL_DQ_CALIB_STATUS */ "", 18141 /* DDR_PHY_CONTROL_REGS_VDL_LDE_CONTROL */ "", 18142 /* DDR_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL */ "", 18143 /* DDR_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL */ "", 18144 /* DDR_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS */ "", 18145 /* DDR_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR */ "", 18146 /* DDR_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE */ "", 18147 /* DDR_PHY_CONTROL_REGS_VDL_MONITOR_REF */ "", 18148 /* DDR_PHY_CONTROL_REGS_VDL_MONITOR_STATUS */ "", 18149 /* DDR_PHY_CONTROL_REGS_VDL_OVRIDE_BIT_CTL */ "", 18150 /* DDR_PHY_CONTROL_REGS_VDL_OVRIDE_BYTE_CTL */ "", 18151 /* DDR_PHY_CONTROL_REGS_VDL_RD_DATA_DLY_STATUS */ "", 18152 /* DDR_PHY_CONTROL_REGS_VDL_RD_EN_CALIB_STATUS */ "", 18153 /* DDR_PHY_CONTROL_REGS_VDL_WR_CHAN_CALIB_STATUS */ "", 18154 /* DDR_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS */ "", 18155 /* DDR_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL */ "", 18156 /* DDR_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE */ "", 18157 /* DDR_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS */ "", 18158 /* DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL */ "", 18159 /* DDR_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL */ "", 18160 /* DDR_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS */ "", 18161 /* DDR_PHY_CONTROL_REGS_WRITE_ODT_CNTRL */ "", 18162 /* DDR_PHY_CONTROL_REGS_ZQ_CAL */ "", 18163 /* DDR_PHY_CONTROL_REGS_ZQ_CAL2 */ "", 18164 /* DDR_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL */ "", 18165 /* DDR_PHY_ECC_LANE_BL_SPARE_REG */ "", 18166 /* DDR_PHY_ECC_LANE_CLOCK_ENABLE */ "", 18167 /* DDR_PHY_ECC_LANE_CLOCK_IDLE */ "", 18168 /* DDR_PHY_ECC_LANE_CLOCK_PAD_DISABLE */ "", 18169 /* DDR_PHY_ECC_LANE_DQSN_DRIVE_PAD_CTL */ "", 18170 /* DDR_PHY_ECC_LANE_DQSP_DRIVE_PAD_CTL */ "", 18171 /* DDR_PHY_ECC_LANE_DQS_RX_TRIM */ "", 18172 /* DDR_PHY_ECC_LANE_DQ_RX_TRIM */ "", 18173 /* DDR_PHY_ECC_LANE_DRIVE_PAD_CTL */ "", 18174 /* DDR_PHY_ECC_LANE_DYN_VDL_OVRIDE_BYTE_BIT_R_N */ "", 18175 /* DDR_PHY_ECC_LANE_DYN_VDL_OVRIDE_BYTE_BIT_R_P */ "", 18176 /* DDR_PHY_ECC_LANE_DYN_VDL_OVRIDE_BYTE_BIT_W */ "", 18177 /* DDR_PHY_ECC_LANE_DYN_VDL_OVRIDE_BYTE_R_N */ "", 18178 /* DDR_PHY_ECC_LANE_DYN_VDL_OVRIDE_BYTE_R_P */ "", 18179 /* DDR_PHY_ECC_LANE_DYN_VDL_OVRIDE_BYTE_W */ "", 18180 /* DDR_PHY_ECC_LANE_EDC_CRC_CONTROL */ "", 18181 /* DDR_PHY_ECC_LANE_EDC_CRC_COUNT */ "", 18182 /* DDR_PHY_ECC_LANE_EDC_CRC_STATUS */ "", 18183 /* DDR_PHY_ECC_LANE_EDC_CRC_STATUS_CLEAR */ "", 18184 /* DDR_PHY_ECC_LANE_EDC_DPD_CONTROL */ "", 18185 /* DDR_PHY_ECC_LANE_EDC_DPD_OUT_CONTROL */ "", 18186 /* DDR_PHY_ECC_LANE_EDC_DPD_OUT_STATUS */ "", 18187 /* DDR_PHY_ECC_LANE_EDC_DPD_OUT_STATUS_CLEAR */ "", 18188 /* DDR_PHY_ECC_LANE_EDC_DPD_STATUS */ "", 18189 /* DDR_PHY_ECC_LANE_EDC_DRIVE_PAD_CTL */ "", 18190 /* DDR_PHY_ECC_LANE_IDLE_PAD_CONTROL */ "", 18191 /* DDR_PHY_ECC_LANE_LDO_CONFIG */ "", 18192 /* DDR_PHY_ECC_LANE_MISC_RX_TRIM */ "", 18193 /* DDR_PHY_ECC_LANE_ODT_CONTROL */ "", 18194 /* DDR_PHY_ECC_LANE_PHYBIST_VDL_ADJ */ "", 18195 /* DDR_PHY_ECC_LANE_RD_EN_DLY_CYC */ "", 18196 /* DDR_PHY_ECC_LANE_RD_EN_DRIVE_PAD_CTL */ "", 18197 /* DDR_PHY_ECC_LANE_READ_CONTROL */ "", 18198 /* DDR_PHY_ECC_LANE_READ_DATA_DLY */ "", 18199 /* DDR_PHY_ECC_LANE_READ_FIFO_ADDR */ "", 18200 /* DDR_PHY_ECC_LANE_READ_FIFO_CLEAR */ "", 18201 /* DDR_PHY_ECC_LANE_READ_FIFO_DATA */ "", 18202 /* DDR_PHY_ECC_LANE_READ_FIFO_DATA_0 */ "", 18203 /* DDR_PHY_ECC_LANE_READ_FIFO_DATA_1 */ "", 18204 /* DDR_PHY_ECC_LANE_READ_FIFO_DATA_2 */ "", 18205 /* DDR_PHY_ECC_LANE_READ_FIFO_DATA_3 */ "", 18206 /* DDR_PHY_ECC_LANE_READ_FIFO_DM_DBI */ "", 18207 /* DDR_PHY_ECC_LANE_READ_FIFO_STATUS */ "", 18208 /* DDR_PHY_ECC_LANE_STATIC_PAD_CTL */ "", 18209 /* DDR_PHY_ECC_LANE_VDL_CLK_CONTROL */ "", 18210 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DMN */ "", 18211 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DMP */ "", 18212 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ0N */ "", 18213 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ0P */ "", 18214 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ1N */ "", 18215 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ1P */ "", 18216 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ2N */ "", 18217 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ2P */ "", 18218 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ3N */ "", 18219 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ3P */ "", 18220 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ4N */ "", 18221 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ4P */ "", 18222 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ5N */ "", 18223 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ5P */ "", 18224 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ6N */ "", 18225 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ6P */ "", 18226 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ7N */ "", 18227 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQ7P */ "", 18228 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQSN */ "", 18229 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_DQSP */ "", 18230 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_EDCN */ "", 18231 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_EDCP */ "", 18232 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_EN_CRC */ "", 18233 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_EN_CS0 */ "", 18234 /* DDR_PHY_ECC_LANE_VDL_CONTROL_RD_EN_CS1 */ "", 18235 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DM */ "", 18236 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ0 */ "", 18237 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ1 */ "", 18238 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ2 */ "", 18239 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ3 */ "", 18240 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ4 */ "", 18241 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ5 */ "", 18242 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ6 */ "", 18243 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQ7 */ "", 18244 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_DQS */ "", 18245 /* DDR_PHY_ECC_LANE_VDL_CONTROL_WR_EDC */ "", 18246 /* DDR_PHY_ECC_LANE_VDL_LDE_CONTROL */ "", 18247 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_N */ "", 18248 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_P */ "", 18249 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_W */ "", 18250 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_N */ "", 18251 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_P */ "", 18252 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_W */ "", 18253 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_N */ "", 18254 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_P */ "", 18255 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_W */ "", 18256 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_N */ "", 18257 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_P */ "", 18258 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_W */ "", 18259 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN */ "", 18260 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_DM_W */ "", 18261 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN */ "", 18262 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_N */ "", 18263 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_P */ "", 18264 /* DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_W */ "", 18265 /* DDR_PHY_ECC_LANE_WR_CHAN_DLY_CYC */ "", 18266 /* DDR_PHY_ECC_LANE_WR_PREAMBLE_MODE */ "", 18267 /* DDR_PHY_WORD_LANE_0_CLOCK_PAD_DISABLE */ "", 18268 /* DDR_PHY_WORD_LANE_0_DRIVE_PAD_CTL */ "", 18269 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N */ "", 18270 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P */ "", 18271 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_BIT_W */ "", 18272 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_N */ "", 18273 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_R_P */ "", 18274 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE0_W */ "", 18275 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N */ "", 18276 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P */ "", 18277 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_BIT_W */ "", 18278 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_N */ "", 18279 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_R_P */ "", 18280 /* DDR_PHY_WORD_LANE_0_DYN_VDL_OVRIDE_BYTE1_W */ "", 18281 /* DDR_PHY_WORD_LANE_0_IDLE_PAD_CONTROL */ "", 18282 /* DDR_PHY_WORD_LANE_0_PHYBIST_VDL_ADJ */ "", 18283 /* DDR_PHY_WORD_LANE_0_READ_CONTROL */ "", 18284 /* DDR_PHY_WORD_LANE_0_READ_DATA_DLY */ "", 18285 /* DDR_PHY_WORD_LANE_0_READ_FIFO_CLEAR */ "", 18286 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_0 */ "", 18287 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_1 */ "", 18288 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_2 */ "", 18289 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL0_3 */ "", 18290 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_0 */ "", 18291 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_1 */ "", 18292 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_2 */ "", 18293 /* DDR_PHY_WORD_LANE_0_READ_FIFO_DATA_BL1_3 */ "", 18294 /* DDR_PHY_WORD_LANE_0_READ_FIFO_STATUS */ "", 18295 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N */ "", 18296 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P */ "", 18297 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W */ "", 18298 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N */ "", 18299 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P */ "", 18300 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W */ "", 18301 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N */ "", 18302 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P */ "", 18303 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W */ "", 18304 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N */ "", 18305 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P */ "", 18306 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W */ "", 18307 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_N */ "", 18308 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_R_P */ "", 18309 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT4_W */ "", 18310 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_N */ "", 18311 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_R_P */ "", 18312 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT5_W */ "", 18313 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_N */ "", 18314 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_R_P */ "", 18315 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT6_W */ "", 18316 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_N */ "", 18317 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_R_P */ "", 18318 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT7_W */ "", 18319 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN */ "", 18320 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W */ "", 18321 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N */ "", 18322 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P */ "", 18323 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W */ "", 18324 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_N */ "", 18325 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_R_P */ "", 18326 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT0_W */ "", 18327 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_N */ "", 18328 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_R_P */ "", 18329 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT1_W */ "", 18330 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_N */ "", 18331 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_R_P */ "", 18332 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT2_W */ "", 18333 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_N */ "", 18334 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_R_P */ "", 18335 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT3_W */ "", 18336 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_N */ "", 18337 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_R_P */ "", 18338 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT4_W */ "", 18339 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_N */ "", 18340 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_R_P */ "", 18341 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT5_W */ "", 18342 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_N */ "", 18343 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_R_P */ "", 18344 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT6_W */ "", 18345 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_N */ "", 18346 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_R_P */ "", 18347 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT7_W */ "", 18348 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_BIT_RD_EN */ "", 18349 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_DM_W */ "", 18350 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_N */ "", 18351 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_R_P */ "", 18352 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE1_W */ "", 18353 /* DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN */ "", 18354 /* DDR_PHY_WORD_LANE_0_WR_PREAMBLE_MODE */ "", 18355 /* DDR_PHY_WORD_LANE_1_CLOCK_PAD_DISABLE */ "", 18356 /* DDR_PHY_WORD_LANE_1_DRIVE_PAD_CTL */ "", 18357 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N */ "", 18358 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P */ "", 18359 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_BIT_W */ "", 18360 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_N */ "", 18361 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_R_P */ "", 18362 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE0_W */ "", 18363 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N */ "", 18364 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P */ "", 18365 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_BIT_W */ "", 18366 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_N */ "", 18367 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_R_P */ "", 18368 /* DDR_PHY_WORD_LANE_1_DYN_VDL_OVRIDE_BYTE1_W */ "", 18369 /* DDR_PHY_WORD_LANE_1_IDLE_PAD_CONTROL */ "", 18370 /* DDR_PHY_WORD_LANE_1_PHYBIST_VDL_ADJ */ "", 18371 /* DDR_PHY_WORD_LANE_1_READ_CONTROL */ "", 18372 /* DDR_PHY_WORD_LANE_1_READ_DATA_DLY */ "", 18373 /* DDR_PHY_WORD_LANE_1_READ_FIFO_CLEAR */ "", 18374 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_0 */ "", 18375 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_1 */ "", 18376 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_2 */ "", 18377 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL0_3 */ "", 18378 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_0 */ "", 18379 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_1 */ "", 18380 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_2 */ "", 18381 /* DDR_PHY_WORD_LANE_1_READ_FIFO_DATA_BL1_3 */ "", 18382 /* DDR_PHY_WORD_LANE_1_READ_FIFO_STATUS */ "", 18383 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_N */ "", 18384 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_R_P */ "", 18385 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT0_W */ "", 18386 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_N */ "", 18387 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_R_P */ "", 18388 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT1_W */ "", 18389 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_N */ "", 18390 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_R_P */ "", 18391 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT2_W */ "", 18392 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_N */ "", 18393 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_R_P */ "", 18394 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT3_W */ "", 18395 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_N */ "", 18396 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_R_P */ "", 18397 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT4_W */ "", 18398 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_N */ "", 18399 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_R_P */ "", 18400 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT5_W */ "", 18401 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_N */ "", 18402 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_R_P */ "", 18403 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT6_W */ "", 18404 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_N */ "", 18405 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_R_P */ "", 18406 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT7_W */ "", 18407 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_BIT_RD_EN */ "", 18408 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_DM_W */ "", 18409 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_N */ "", 18410 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_R_P */ "", 18411 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE0_W */ "", 18412 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_N */ "", 18413 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_R_P */ "", 18414 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT0_W */ "", 18415 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_N */ "", 18416 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_R_P */ "", 18417 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT1_W */ "", 18418 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_N */ "", 18419 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_R_P */ "", 18420 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT2_W */ "", 18421 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_N */ "", 18422 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_R_P */ "", 18423 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT3_W */ "", 18424 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_N */ "", 18425 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_R_P */ "", 18426 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT4_W */ "", 18427 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_N */ "", 18428 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_R_P */ "", 18429 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT5_W */ "", 18430 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_N */ "", 18431 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_R_P */ "", 18432 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT6_W */ "", 18433 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_N */ "", 18434 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_R_P */ "", 18435 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT7_W */ "", 18436 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_BIT_RD_EN */ "", 18437 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_DM_W */ "", 18438 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_N */ "", 18439 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_R_P */ "", 18440 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE1_W */ "", 18441 /* DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN */ "", 18442 /* DDR_PHY_WORD_LANE_1_WR_PREAMBLE_MODE */ "", 18443 /* DDR_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 18444 /* DDR_S0_IDM_ERROR_LOG_COMPLETE */ "", 18445 /* DDR_S0_IDM_ERROR_LOG_CONTROL */ "", 18446 /* DDR_S0_IDM_ERROR_LOG_FLAGS */ "", 18447 /* DDR_S0_IDM_ERROR_LOG_ID */ "", 18448 /* DDR_S0_IDM_ERROR_LOG_STATUS */ "", 18449 /* DDR_S0_IDM_INTERRUPT_STATUS */ "", 18450 /* DDR_S0_IDM_IO_CONTROL_DIRECT */ "", 18451 /* DDR_S0_IDM_IO_STATUS */ "", 18452 /* DDR_S0_IDM_RESET_CONTROL */ "", 18453 /* DDR_S0_IDM_RESET_READ_ID */ "", 18454 /* DDR_S0_IDM_RESET_STATUS */ "", 18455 /* DDR_S0_IDM_RESET_WRITE_ID */ "", 18456 /* DDR_S1_IDM_ERROR_LOG_ADDR_LSB */ "", 18457 /* DDR_S1_IDM_ERROR_LOG_COMPLETE */ "", 18458 /* DDR_S1_IDM_ERROR_LOG_CONTROL */ "", 18459 /* DDR_S1_IDM_ERROR_LOG_FLAGS */ "", 18460 /* DDR_S1_IDM_ERROR_LOG_ID */ "", 18461 /* DDR_S1_IDM_ERROR_LOG_STATUS */ "", 18462 /* DDR_S1_IDM_INTERRUPT_STATUS */ "", 18463 /* DDR_S1_IDM_IO_CONTROL_DIRECT */ "", 18464 /* DDR_S1_IDM_IO_STATUS */ "", 18465 /* DDR_S1_IDM_RESET_CONTROL */ "", 18466 /* DDR_S1_IDM_RESET_READ_ID */ "", 18467 /* DDR_S1_IDM_RESET_STATUS */ "", 18468 /* DDR_S1_IDM_RESET_WRITE_ID */ "", 18469 /* DDR_S2_IDM_ERROR_LOG_ADDR_LSB */ "", 18470 /* DDR_S2_IDM_ERROR_LOG_COMPLETE */ "", 18471 /* DDR_S2_IDM_ERROR_LOG_CONTROL */ "", 18472 /* DDR_S2_IDM_ERROR_LOG_FLAGS */ "", 18473 /* DDR_S2_IDM_ERROR_LOG_ID */ "", 18474 /* DDR_S2_IDM_ERROR_LOG_STATUS */ "", 18475 /* DDR_S2_IDM_INTERRUPT_STATUS */ "", 18476 /* DDR_S2_IDM_IO_CONTROL_DIRECT */ "", 18477 /* DDR_S2_IDM_IO_STATUS */ "", 18478 /* DDR_S2_IDM_RESET_CONTROL */ "", 18479 /* DDR_S2_IDM_RESET_READ_ID */ "", 18480 /* DDR_S2_IDM_RESET_STATUS */ "", 18481 /* DDR_S2_IDM_RESET_WRITE_ID */ "", 18482 /* DEBOUNCED_LINK_STATUS */ "", 18483 /* DEBOUNCED_LINK_STATUS_CHANGE */ "", 18484 /* DEBOUNCED_LINK_STATUS_CHANGE_MASK */ "", 18485 /* DEBOUNCED_LINK_STATUS_STICKY */ "", 18486 /* DEBUG0 */ "", 18487 /* DEBUG1 */ "", 18488 /* DEBUG10 */ "", 18489 /* DEBUG20 */ "", 18490 /* DEBUG0_EXT */ "", 18491 /* DEBUG0_INT */ "", 18492 /* DEBUG1_EXT */ "", 18493 /* DEBUG1_INT */ "", 18494 /* DEBUG2_EXT */ "", 18495 /* DEBUG2_INT */ "", 18496 /* DEBUGRAM_ECC_STATUS */ "", 18497 /* DEBUG_CAPTURE_ECC_STATUS */ "", 18498 /* DEBUG_COLOR_STATUS */ "", 18499 /* DEBUG_COMP_CLKEN_RST_CONTROL */ "", 18500 /* DEBUG_ENQ_DROP_COS */ "", 18501 /* DEBUG_ENQ_DROP_PG */ "", 18502 /* DEBUG_ENQ_DROP_SOURCE */ "", 18503 /* DEBUG_HOL_STATUS */ "", 18504 /* DEBUG_MEM_DCM_CONTROL */ "", 18505 /* DEBUG_NIC_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 18506 /* DEBUG_NIC_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 18507 /* DEBUG_NIC_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 18508 /* DEBUG_NIC_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 18509 /* DEBUG_NIC_S0_IDM_IDM_ERROR_LOG_ID */ "", 18510 /* DEBUG_NIC_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 18511 /* DEBUG_NIC_S0_IDM_IDM_INTERRUPT_STATUS */ "", 18512 /* DEBUG_NIC_S0_IDM_IDM_IO_CONTROL_DIRECT */ "", 18513 /* DEBUG_NIC_S0_IDM_IDM_IO_STATUS */ "", 18514 /* DEBUG_NIC_S0_IDM_IDM_RESET_CONTROL */ "", 18515 /* DEBUG_NIC_S0_IDM_IDM_RESET_READ_ID */ "", 18516 /* DEBUG_NIC_S0_IDM_IDM_RESET_STATUS */ "", 18517 /* DEBUG_NIC_S0_IDM_IDM_RESET_WRITE_ID */ "", 18518 /* DEBUG_PG_COUNT_STATUS0 */ "", 18519 /* DEBUG_PG_COUNT_STATUS1 */ "", 18520 /* DEBUG_PORT_COUNT_STATUS0 */ "", 18521 /* DEBUG_PORT_COUNT_STATUS1 */ "", 18522 /* DEBUG_PORT_SELECT */ "", 18523 /* DEBUG_PORT_SHARED_STATUS */ "", 18524 /* DEBUG_QUEUE_MIN_STATUS */ "", 18525 /* DEBUG_QUEUE_SHARED_STATUS */ "", 18526 /* DEBUG_THDI_ERROR */ "", 18527 /* DEBUG_THDI_ERROR_MASK */ "", 18528 /* DEBUG_THDO_ERROR */ "", 18529 /* DEBUG_THDO_ERROR_MASK */ "", 18530 /* DEBUG_TOQ_QEN_ACCOUNT_0 */ "", 18531 /* DEBUG_TOQ_QEN_ACCOUNT_1 */ "", 18532 /* DEBUG_TOQ_QUEUE_STATE */ "", 18533 /* DEFAULT_SVP_ENABLE */ "", 18534 /* DEQ_AGED_PKT_CNT */ "", 18535 /* DEQ_AGINGMASK */ "", 18536 /* DEQ_AGINGMASK_64 */ "DEQ_AGINGMASK", 18537 /* DEQ_AGINGMASK_CPU_PORT */ "", 18538 /* DEQ_AGINGMASK_CPU_PORT_0 */ "", 18539 /* DEQ_AGINGMASK_CPU_PORT_1 */ "", 18540 /* DEQ_AGINGMASK_RDE */ "", 18541 /* DEQ_AGINGMASK_UCQ_0 */ "", 18542 /* DEQ_AGINGMASK_UCQ_1 */ "", 18543 /* DEQ_AGINGMASK_UCQ_2 */ "", 18544 /* DEQ_AGINGMASK_UCQ_3 */ "", 18545 /* DEQ_AGINGMASK_UCQ_4 */ "", 18546 /* DEQ_AGINGMASK_UCQ_5 */ "", 18547 /* DEQ_AGINGMASK_UCQ_6 */ "", 18548 /* DEQ_AGINGMASK_UCQ_7 */ "", 18549 /* DEQ_AGINGMASK_UCQ_8 */ "", 18550 /* DEQ_AGINGMASK_UCQ_9 */ "", 18551 /* DEQ_AGINGMASK_UCQ_10 */ "", 18552 /* DEQ_AGINGMASK_UCQ_11 */ "", 18553 /* DEQ_AGINGMASK_UCQ_12 */ "", 18554 /* DEQ_AGINGMASK_UCQ_13 */ "", 18555 /* DEQ_AGINGMASK_UCQ_14 */ "", 18556 /* DEQ_AGINGMASK_UCQ_15 */ "", 18557 /* DEQ_AGING_MASK_LOOKUP_TABLE_MEMORY_DEBUG */ "", 18558 /* DEQ_AGING_MASK_MEMORY_ECC_STATUS_DEBUG */ "", 18559 /* DEQ_BYPASSMMU */ "", 18560 /* DEQ_CBPERRPTR */ "", 18561 /* DEQ_CCBE_CONTROL_DATA_REPLICATION_ERROR_CODE_DEBUG */ "", 18562 /* DEQ_CCBE_TRACE_IF_CAPT_0 */ "", 18563 /* DEQ_CCBE_TRACE_IF_CAPT_1 */ "", 18564 /* DEQ_CCBE_TRACE_IF_CONTROL */ "", 18565 /* DEQ_CCBE_TRACE_IF_COUNTER */ "", 18566 /* DEQ_CCBE_TRACE_IF_MASK_FIELD_0 */ "", 18567 /* DEQ_CCBE_TRACE_IF_MASK_FIELD_1 */ "", 18568 /* DEQ_CCBE_TRACE_IF_VALUE_FIELD_0 */ "", 18569 /* DEQ_CCBE_TRACE_IF_VALUE_FIELD_1 */ "", 18570 /* DEQ_CCPE_FIFO_CFG */ "", 18571 /* DEQ_CELL_CLASSIFICATION_EXT_ERROR_CODE_DEBUG */ "", 18572 /* DEQ_CELL_CLASSIFICATION_INT_ERROR_CODE_DEBUG */ "", 18573 /* DEQ_CELL_RECONSTRUCTION_32B_RESIDUAL_BUFFER_ECC_STATUS_DEBUG */ "", 18574 /* DEQ_CELL_RECONSTRUCTION_32B_RESIDUAL_BUFFER_MEMORY_DEBUG */ "", 18575 /* DEQ_CELL_REP_BUFFER_WATERMARK_DEBUG */ "", 18576 /* DEQ_CFG */ "", 18577 /* DEQ_CT_PURGE_CNT_X */ "", 18578 /* DEQ_CT_PURGE_CNT_Y */ "", 18579 /* DEQ_DEBUG0 */ "", 18580 /* DEQ_DEBUG1 */ "", 18581 /* DEQ_ECC_DEBUG */ "", 18582 /* DEQ_ECC_DEBUG_0 */ "", 18583 /* DEQ_ECC_VERIFICATION_ECC_STATUS_DEBUG */ "", 18584 /* DEQ_EFIFO_AGING_WRED_MEMORY_DEBUG */ "", 18585 /* DEQ_EFIFO_CCBE_CONTROL_DATA_MEMORY_DEBUG */ "", 18586 /* DEQ_EFIFO_CCBE_DATA_ECC_MEMORY_0_DEBUG */ "", 18587 /* DEQ_EFIFO_CCBE_DATA_ECC_MEMORY_1_DEBUG */ "", 18588 /* DEQ_EFIFO_CCBE_DATA_ECC_MEMORY_2_DEBUG */ "", 18589 /* DEQ_EFIFO_CCBE_DATA_ECC_MEMORY_3_DEBUG */ "", 18590 /* DEQ_EFIFO_CCBE_DATA_ECC_MEMORY_4_DEBUG */ "", 18591 /* DEQ_EFIFO_CCBE_DATA_ECC_MEMORY_5_DEBUG */ "", 18592 /* DEQ_EFIFO_CCBE_DATA_ECC_MEMORY_DEBUG */ "", 18593 /* DEQ_EFIFO_CFG */ "", 18594 /* DEQ_EFIFO_CFG_COMPLETE */ "", 18595 /* DEQ_EFIFO_EMPTY_FULL_STATUS_DEBUG */ "", 18596 /* DEQ_EFIFO_STATUS_DEBUG */ "", 18597 /* DEQ_EFIFO_WATERMARK_DEBUG */ "", 18598 /* DEQ_EGRESS_FIFO_AGING_WRED_MEMORY_ECC_STATUS_DEBUG */ "", 18599 /* DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_ECC_STATUS_DEBUG */ "", 18600 /* DEQ_EGRESS_FIFO_OVERFLOW_ERROR_PORT_DEBUG */ "", 18601 /* DEQ_EGRESS_FIFO_UNDERRUN_ERROR_PORT_DEBUG */ "", 18602 /* DEQ_EP_REDIRECT_BUFFER_0_ECC_STATUS_DEBUG */ "", 18603 /* DEQ_EP_REDIRECT_BUFFER_1_ECC_STATUS_DEBUG */ "", 18604 /* DEQ_EP_REDIRECT_BUFFER_2_ECC_STATUS_DEBUG */ "", 18605 /* DEQ_EP_REDIRECT_BUFFER_ECC_STATUS_DEBUG */ "", 18606 /* DEQ_EP_REDIRECT_BUFFER_MEMORY_0_DEBUG */ "", 18607 /* DEQ_EP_REDIRECT_BUFFER_MEMORY_1_DEBUG */ "", 18608 /* DEQ_EP_REDIRECT_BUFFER_MEMORY_2_DEBUG */ "", 18609 /* DEQ_ERROR */ "", 18610 /* DEQ_ERROR_0 */ "", 18611 /* DEQ_ERROR_1 */ "", 18612 /* DEQ_ERROR_2 */ "", 18613 /* DEQ_ERROR_3 */ "", 18614 /* DEQ_ERROR_4 */ "", 18615 /* DEQ_ERROR_MASK_0 */ "", 18616 /* DEQ_ERROR_MASK_1 */ "", 18617 /* DEQ_ERROR_MASK_2 */ "", 18618 /* DEQ_ERROR_MASK_3 */ "", 18619 /* DEQ_ERROR_MASK_4 */ "", 18620 /* DEQ_GLOBAL_1B_ECC_ERROR_COUNT_DEBUG */ "", 18621 /* DEQ_GLOBAL_2B_ECC_ERROR_COUNT_DEBUG */ "", 18622 /* DEQ_GLOBAL_CELL_COUNT_DEBUG */ "", 18623 /* DEQ_GLOBAL_PKT_AGED_COUNT_DEBUG */ "", 18624 /* DEQ_GLOBAL_PKT_AGED_MARKED_COUNT_DEBUG */ "", 18625 /* DEQ_GLOBAL_PKT_COUNT_DEBUG */ "", 18626 /* DEQ_GLOBAL_PKT_MARKED_COUNT_DEBUG */ "", 18627 /* DEQ_GLOBAL_RD_REQ_RSP_COUNT_DEBUG */ "", 18628 /* DEQ_IPMC_ERASE_CNT_X */ "", 18629 /* DEQ_IPMC_ERASE_CNT_Y */ "", 18630 /* DEQ_LENGTHERRPTR */ "", 18631 /* DEQ_MARKED_PKT_CNT */ "", 18632 /* DEQ_MEMDEBUG */ "", 18633 /* DEQ_MEMDEBUG0 */ "", 18634 /* DEQ_MEMDEBUG1 */ "", 18635 /* DEQ_MEMDEBUG2 */ "", 18636 /* DEQ_MEMDEBUG3 */ "", 18637 /* DEQ_MISCELLANEOUS_CFG_DEBUG */ "", 18638 /* DEQ_MPBERRPTR */ "", 18639 /* DEQ_OPQ_CELL_INFO_ECC_STATUS_DEBUG */ "", 18640 /* DEQ_PKTHDR0ERRPTR */ "", 18641 /* DEQ_PKTHDR2ERRPTR */ "", 18642 /* DEQ_PKTHDRCPUERRPTR */ "", 18643 /* DEQ_PKTHDRERRPTR */ "", 18644 /* DEQ_PRE_EGRESS_FIFO_ECC_VERIFICATION_EXT_ECC_STATUS_DEBUG */ "", 18645 /* DEQ_PRE_EGRESS_FIFO_ECC_VERIFICATION_INT_ECC_STATUS_DEBUG */ "", 18646 /* DEQ_PST_EGRESS_FIFO_ECC_VERIFICATION_EXT_ECC_STATUS_DEBUG */ "", 18647 /* DEQ_PST_EGRESS_FIFO_ECC_VERIFICATION_INT_ECC_STATUS_DEBUG */ "", 18648 /* DEQ_PURGE_PKT_CNT */ "", 18649 /* DEQ_QCN_LB_COS */ "", 18650 /* DEQ_RDEDESCPERRPTR */ "", 18651 /* DEQ_RDEHDRERRPTR */ "", 18652 /* DEQ_RDE_TRACE_IF_CAPT_0 */ "", 18653 /* DEQ_RDE_TRACE_IF_CAPT_1 */ "", 18654 /* DEQ_RDE_TRACE_IF_CONTROL */ "", 18655 /* DEQ_RDE_TRACE_IF_COUNTER */ "", 18656 /* DEQ_RDE_TRACE_IF_MASK_FIELD_0 */ "", 18657 /* DEQ_RDE_TRACE_IF_MASK_FIELD_1 */ "", 18658 /* DEQ_RDE_TRACE_IF_VALUE_FIELD_0 */ "", 18659 /* DEQ_RDE_TRACE_IF_VALUE_FIELD_1 */ "", 18660 /* DEQ_RD_CTRL_CELL_REP_INFO_BUFFER_MEMORY_DEBUG */ "", 18661 /* DEQ_RD_CTRL_EXT_CELL_REP_INFO_BUFFER_CFG */ "", 18662 /* DEQ_RD_CTRL_RD_REQ_LATENCY_WATERMARK_DEBUG */ "", 18663 /* DEQ_REPLISTERRPTR */ "", 18664 /* DEQ_SMERRPTR */ "", 18665 /* DEQ_SOP_CNT_X */ "", 18666 /* DEQ_SOP_CNT_Y */ "", 18667 /* DEQ_SPARE */ "", 18668 /* DEQ_TOQ_CELL_REP_INFO_BUFFER_ECC_STATUS_DEBUG */ "", 18669 /* DEQ_TOQ_CREDIT_INITIALIZATION_COMPLETE */ "", 18670 /* DEQ_TRACE_IF_CAPT_0 */ "", 18671 /* DEQ_TRACE_IF_CAPT_1 */ "", 18672 /* DEQ_TRACE_IF_CONTROL */ "", 18673 /* DEQ_TRACE_IF_COUNTER */ "", 18674 /* DEQ_TRACE_IF_MASK_FIELD_0 */ "", 18675 /* DEQ_TRACE_IF_MASK_FIELD_1 */ "", 18676 /* DEQ_TRACE_IF_VALUE_FIELD_0 */ "", 18677 /* DEQ_TRACE_IF_VALUE_FIELD_1 */ "", 18678 /* DEST_PORT_CFG_0 */ "", 18679 /* DEST_PORT_CFG_1 */ "", 18680 /* DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROL */ "", 18681 /* DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_STATUS_INTR */ "", 18682 /* DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_STATUS_NACK */ "", 18683 /* DHC_ECC_1B_ERR_CNT */ "", 18684 /* DHC_ECC_2B_ERR_CNT */ "", 18685 /* DHC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 18686 /* DHC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 18687 /* DHC_ECC_INTERRUPT_REGISTER */ "", 18688 /* DHC_ECC_INTERRUPT_REGISTER_MASK */ "", 18689 /* DHC_ECC_INTERRUPT_REGISTER_TEST */ "", 18690 /* DHC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 18691 /* DHC_ERROR_INITIATION_DATA */ "", 18692 /* DHC_GTIMER_CONFIGURATION */ "", 18693 /* DHC_GTIMER_CYCLE */ "", 18694 /* DHC_INDIRECT_COMMAND */ "", 18695 /* DHC_INDIRECT_COMMAND_ADDRESS */ "", 18696 /* DHC_INDIRECT_COMMAND_RD_DATA */ "", 18697 /* DHC_INDIRECT_COMMAND_WR_DATA */ "", 18698 /* DHC_INDIRECT_FORCE_BUBBLE */ "", 18699 /* DHC_INDIRECT_WR_MASK */ "", 18700 /* DHC_INTERRUPT_MASK_REGISTER */ "", 18701 /* DHC_INTERRUPT_REGISTER */ "", 18702 /* DHC_INTERRUPT_REGISTER_TEST */ "", 18703 /* DHC_PCMI_0 */ "", 18704 /* DHC_PCMI_1 */ "", 18705 /* DHC_PCMI_2 */ "", 18706 /* DHC_PCMI_3 */ "", 18707 /* DHC_PCMI_4 */ "", 18708 /* DHC_PCMI_0_S */ "", 18709 /* DHC_PCMI_0_T */ "", 18710 /* DHC_PCMI_1_S */ "", 18711 /* DHC_PCMI_1_T */ "", 18712 /* DHC_PCMI_2_S */ "", 18713 /* DHC_PCMI_2_T */ "", 18714 /* DHC_PCMI_3_S */ "", 18715 /* DHC_PCMI_3_T */ "", 18716 /* DHC_PCMI_4_S */ "", 18717 /* DHC_PCMI_4_T */ "", 18718 /* DHC_REG_0041 */ "", 18719 /* DHC_REG_0098 */ "", 18720 /* DHC_REG_0100 */ "", 18721 /* DHC_REG_0101 */ "", 18722 /* DHC_REG_0102 */ "", 18723 /* DHC_REG_0103 */ "", 18724 /* DHC_REG_0105 */ "", 18725 /* DHC_REG_0106 */ "", 18726 /* DHC_REG_0107 */ "", 18727 /* DHC_REG_0108 */ "", 18728 /* DHC_REG_0134 */ "", 18729 /* DHC_REG_0154 */ "", 18730 /* DHC_REG_0155 */ "", 18731 /* DHC_REG_0156 */ "", 18732 /* DHC_REG_0166 */ "", 18733 /* DHC_REG_0176 */ "", 18734 /* DHC_REG_00A0 */ "", 18735 /* DHC_REG_00A4 */ "", 18736 /* DHC_REG_00A6 */ "", 18737 /* DHC_REG_00AA */ "", 18738 /* DHC_REG_00C2 */ "", 18739 /* DHC_REG_010C */ "", 18740 /* DHC_REG_012C */ "", 18741 /* DHC_REG_015E */ "", 18742 /* DHC_REG_016E */ "", 18743 /* DHC_REG_017E */ "", 18744 /* DHC_RESERVED_MIRROR_ADDR */ "", 18745 /* DHC_RESERVED_MTCD */ "", 18746 /* DHC_RESERVED_MTCP */ "", 18747 /* DHC_RESERVED_SPARE_0 */ "", 18748 /* DHC_RESERVED_SPARE_1 */ "", 18749 /* DHC_RESERVED_SPARE_2 */ "", 18750 /* DHC_RESERVED_SPARE_3 */ "", 18751 /* DHC_SBUS_BROADCAST_ID */ "", 18752 /* DHC_SBUS_LAST_IN_CHAIN */ "", 18753 /* DIAG_LOOPBACK_CNT0 */ "", 18754 /* DIAG_LOOPBACK_CNT1 */ "", 18755 /* DLB_ECMP_CLEAR_METRIC_STATE_64 */ "", 18756 /* DLB_ECMP_CURRENT_TIME */ "", 18757 /* DLB_ECMP_CURRENT_TIME_PIPE0 */ "", 18758 /* DLB_ECMP_CURRENT_TIME_PIPE1 */ "", 18759 /* DLB_ECMP_CURRENT_TIME_PIPE2 */ "", 18760 /* DLB_ECMP_CURRENT_TIME_PIPE3 */ "", 18761 /* DLB_ECMP_CURRENT_TIME_PIPE4 */ "", 18762 /* DLB_ECMP_CURRENT_TIME_PIPE5 */ "", 18763 /* DLB_ECMP_CURRENT_TIME_PIPE6 */ "", 18764 /* DLB_ECMP_CURRENT_TIME_PIPE7 */ "", 18765 /* DLB_ECMP_EOP_BUFFER */ "", 18766 /* DLB_ECMP_ETHERTYPE_ELIGIBILITY_CONTROL */ "", 18767 /* DLB_ECMP_FLOWSET_PDA_CONTROL */ "", 18768 /* DLB_ECMP_HW_RESET_CONTROL */ "", 18769 /* DLB_ECMP_INTR_ENABLE */ "", 18770 /* DLB_ECMP_INTR_STATUS */ "", 18771 /* DLB_ECMP_MEMBER_HW_STATE_64 */ "", 18772 /* DLB_ECMP_MONITOR_CONTROL */ "", 18773 /* DLB_ECMP_MONITOR_CONTROL_PIPE0 */ "", 18774 /* DLB_ECMP_MONITOR_CONTROL_PIPE1 */ "", 18775 /* DLB_ECMP_MONITOR_CONTROL_PIPE2 */ "", 18776 /* DLB_ECMP_MONITOR_CONTROL_PIPE3 */ "", 18777 /* DLB_ECMP_MONITOR_CONTROL_PIPE4 */ "", 18778 /* DLB_ECMP_MONITOR_CONTROL_PIPE5 */ "", 18779 /* DLB_ECMP_MONITOR_CONTROL_PIPE6 */ "", 18780 /* DLB_ECMP_MONITOR_CONTROL_PIPE7 */ "", 18781 /* DLB_ECMP_MONITOR_IFP_CONTROL */ "", 18782 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE0 */ "", 18783 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE1 */ "", 18784 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE2 */ "", 18785 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE3 */ "", 18786 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE4 */ "", 18787 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE5 */ "", 18788 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE6 */ "", 18789 /* DLB_ECMP_MONITOR_IFP_CONTROL_PIPE7 */ "", 18790 /* DLB_ECMP_MONITOR_MIRROR_CONFIG */ "", 18791 /* DLB_ECMP_PLA_QUALITY_MEASURE_CONTROL */ "", 18792 /* DLB_ECMP_PORT_XPE_A_B_SELECTOR */ "", 18793 /* DLB_ECMP_PORT_XPE_A_B_SELECTOR_PIPE0 */ "", 18794 /* DLB_ECMP_PORT_XPE_A_B_SELECTOR_PIPE1 */ "", 18795 /* DLB_ECMP_PORT_XPE_A_B_SELECTOR_PIPE2 */ "", 18796 /* DLB_ECMP_PORT_XPE_A_B_SELECTOR_PIPE3 */ "", 18797 /* DLB_ECMP_QUALITY_MEASURE_CONTROL */ "", 18798 /* DLB_ECMP_QUALITY_MEASURE_CONTROL_PIPE0 */ "", 18799 /* DLB_ECMP_QUALITY_MEASURE_CONTROL_PIPE1 */ "", 18800 /* DLB_ECMP_QUALITY_MEASURE_CONTROL_PIPE2 */ "", 18801 /* DLB_ECMP_QUALITY_MEASURE_CONTROL_PIPE3 */ "", 18802 /* DLB_ECMP_RAM_CONTROL */ "", 18803 /* DLB_ECMP_RAM_CONTROL_0 */ "", 18804 /* DLB_ECMP_RAM_CONTROL_1 */ "", 18805 /* DLB_ECMP_RAM_CONTROL_2 */ "", 18806 /* DLB_ECMP_RAM_CONTROL_3 */ "", 18807 /* DLB_ECMP_RAM_CONTROL_0_PIPE0 */ "", 18808 /* DLB_ECMP_RAM_CONTROL_0_PIPE1 */ "", 18809 /* DLB_ECMP_RAM_CONTROL_0_PIPE2 */ "", 18810 /* DLB_ECMP_RAM_CONTROL_0_PIPE3 */ "", 18811 /* DLB_ECMP_RAM_CONTROL_0_PIPE4 */ "", 18812 /* DLB_ECMP_RAM_CONTROL_0_PIPE5 */ "", 18813 /* DLB_ECMP_RAM_CONTROL_0_PIPE6 */ "", 18814 /* DLB_ECMP_RAM_CONTROL_0_PIPE7 */ "", 18815 /* DLB_ECMP_RAM_CONTROL_1_PIPE0 */ "", 18816 /* DLB_ECMP_RAM_CONTROL_1_PIPE1 */ "", 18817 /* DLB_ECMP_RAM_CONTROL_1_PIPE2 */ "", 18818 /* DLB_ECMP_RAM_CONTROL_1_PIPE3 */ "", 18819 /* DLB_ECMP_RAM_CONTROL_2_PIPE0 */ "", 18820 /* DLB_ECMP_RAM_CONTROL_2_PIPE1 */ "", 18821 /* DLB_ECMP_RAM_CONTROL_2_PIPE2 */ "", 18822 /* DLB_ECMP_RAM_CONTROL_2_PIPE3 */ "", 18823 /* DLB_ECMP_RAM_CONTROL_3_PIPE0 */ "", 18824 /* DLB_ECMP_RAM_CONTROL_3_PIPE1 */ "", 18825 /* DLB_ECMP_RAM_CONTROL_3_PIPE2 */ "", 18826 /* DLB_ECMP_RAM_CONTROL_3_PIPE3 */ "", 18827 /* DLB_ECMP_RANDOM_SELECTION_CONTROL */ "", 18828 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE0 */ "", 18829 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE1 */ "", 18830 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE2 */ "", 18831 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE3 */ "", 18832 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE4 */ "", 18833 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE5 */ "", 18834 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE6 */ "", 18835 /* DLB_ECMP_RANDOM_SELECTION_CONTROL_PIPE7 */ "", 18836 /* DLB_ECMP_REFRESH_DISABLE */ "", 18837 /* DLB_ECMP_REFRESH_INDEX */ "", 18838 /* DLB_ECMP_REFRESH_INDEX_PIPE0 */ "", 18839 /* DLB_ECMP_REFRESH_INDEX_PIPE1 */ "", 18840 /* DLB_ECMP_REFRESH_INDEX_PIPE2 */ "", 18841 /* DLB_ECMP_REFRESH_INDEX_PIPE3 */ "", 18842 /* DLB_ECMP_REFRESH_INDEX_PIPE4 */ "", 18843 /* DLB_ECMP_REFRESH_INDEX_PIPE5 */ "", 18844 /* DLB_ECMP_REFRESH_INDEX_PIPE6 */ "", 18845 /* DLB_ECMP_REFRESH_INDEX_PIPE7 */ "", 18846 /* DLB_ECMP_SER_CONTROL */ "", 18847 /* DLB_ECMP_SER_CONTROL_2 */ "", 18848 /* DLB_ECMP_SER_FIFO_CTRL */ "", 18849 /* DLB_ECMP_SER_FIFO_STATUS */ "", 18850 /* DLB_HGT_CURRENT_TIME */ "", 18851 /* DLB_HGT_FINAL_PORT_QUALITY_MEASURE */ "", 18852 /* DLB_HGT_FLOWSET_PDA_CONTROL */ "", 18853 /* DLB_HGT_FLOWSET_PORT_PARITY_CONTROL */ "", 18854 /* DLB_HGT_FLOWSET_PORT_PARITY_STATUS_INTR */ "", 18855 /* DLB_HGT_FLOWSET_PORT_PARITY_STATUS_NACK */ "", 18856 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_CONTROL */ "", 18857 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTR */ "", 18858 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_NACK */ "", 18859 /* DLB_HGT_FLOWSET_TIMESTAMP_PARITY_CONTROL */ "", 18860 /* DLB_HGT_FLOWSET_TIMESTAMP_PARITY_STATUS_INTR */ "", 18861 /* DLB_HGT_FLOWSET_TIMESTAMP_PARITY_STATUS_NACK */ "", 18862 /* DLB_HGT_LAG_CURRENT_TIME */ "", 18863 /* DLB_HGT_LAG_CURRENT_TIME_PIPE0 */ "", 18864 /* DLB_HGT_LAG_CURRENT_TIME_PIPE1 */ "", 18865 /* DLB_HGT_LAG_CURRENT_TIME_PIPE2 */ "", 18866 /* DLB_HGT_LAG_CURRENT_TIME_PIPE3 */ "", 18867 /* DLB_HGT_LAG_ETHERTYPE_ELIGIBILITY_CONTROL */ "", 18868 /* DLB_HGT_LAG_ETHERTYPE_ELIGIBILITY_CONTROL_PIPE0 */ "", 18869 /* DLB_HGT_LAG_ETHERTYPE_ELIGIBILITY_CONTROL_PIPE1 */ "", 18870 /* DLB_HGT_LAG_PORT_XPE_A_B_SELECTOR */ "", 18871 /* DLB_HGT_LAG_PORT_XPE_A_B_SELECTOR_PIPE0 */ "", 18872 /* DLB_HGT_LAG_PORT_XPE_A_B_SELECTOR_PIPE1 */ "", 18873 /* DLB_HGT_LAG_PORT_XPE_A_B_SELECTOR_PIPE2 */ "", 18874 /* DLB_HGT_LAG_PORT_XPE_A_B_SELECTOR_PIPE3 */ "", 18875 /* DLB_HGT_LAG_QUALITY_MEASURE_CONTROL */ "", 18876 /* DLB_HGT_LAG_QUALITY_MEASURE_CONTROL_PIPE0 */ "", 18877 /* DLB_HGT_LAG_QUALITY_MEASURE_CONTROL_PIPE1 */ "", 18878 /* DLB_HGT_LAG_QUALITY_MEASURE_CONTROL_PIPE2 */ "", 18879 /* DLB_HGT_LAG_QUALITY_MEASURE_CONTROL_PIPE3 */ "", 18880 /* DLB_HGT_LAG_RAM_CONTROL_0 */ "", 18881 /* DLB_HGT_LAG_RAM_CONTROL_1 */ "", 18882 /* DLB_HGT_LAG_RAM_CONTROL_2 */ "", 18883 /* DLB_HGT_LAG_RAM_CONTROL_0_PIPE0 */ "", 18884 /* DLB_HGT_LAG_RAM_CONTROL_0_PIPE1 */ "", 18885 /* DLB_HGT_LAG_RAM_CONTROL_0_PIPE2 */ "", 18886 /* DLB_HGT_LAG_RAM_CONTROL_0_PIPE3 */ "", 18887 /* DLB_HGT_LAG_RAM_CONTROL_1_PIPE0 */ "", 18888 /* DLB_HGT_LAG_RAM_CONTROL_1_PIPE1 */ "", 18889 /* DLB_HGT_LAG_RAM_CONTROL_1_PIPE2 */ "", 18890 /* DLB_HGT_LAG_RAM_CONTROL_1_PIPE3 */ "", 18891 /* DLB_HGT_LAG_RAM_CONTROL_2_PIPE0 */ "", 18892 /* DLB_HGT_LAG_RAM_CONTROL_2_PIPE1 */ "", 18893 /* DLB_HGT_LAG_RAM_CONTROL_2_PIPE2 */ "", 18894 /* DLB_HGT_LAG_RAM_CONTROL_2_PIPE3 */ "", 18895 /* DLB_HGT_LAG_RANDOM_SELECTION_CONTROL */ "", 18896 /* DLB_HGT_LAG_RANDOM_SELECTION_CONTROL_PIPE0 */ "", 18897 /* DLB_HGT_LAG_RANDOM_SELECTION_CONTROL_PIPE1 */ "", 18898 /* DLB_HGT_LAG_RANDOM_SELECTION_CONTROL_PIPE2 */ "", 18899 /* DLB_HGT_LAG_RANDOM_SELECTION_CONTROL_PIPE3 */ "", 18900 /* DLB_HGT_LAG_REFRESH_DISABLE */ "", 18901 /* DLB_HGT_LAG_REFRESH_INDEX */ "", 18902 /* DLB_HGT_LAG_REFRESH_INDEX_PIPE0 */ "", 18903 /* DLB_HGT_LAG_REFRESH_INDEX_PIPE1 */ "", 18904 /* DLB_HGT_LAG_REFRESH_INDEX_PIPE2 */ "", 18905 /* DLB_HGT_LAG_REFRESH_INDEX_PIPE3 */ "", 18906 /* DLB_HGT_LAG_SELECTION */ "", 18907 /* DLB_HGT_LAG_SER_CONTROL */ "", 18908 /* DLB_HGT_MEMBER_HW_STATE */ "", 18909 /* DLB_HGT_PORT_AVG_QUALITY_MEASURE */ "", 18910 /* DLB_HGT_PORT_INST_QUALITY_MEASURE */ "", 18911 /* DLB_HGT_PORT_QUALITY_MEASURE_UPDATE_CONTROL */ "", 18912 /* DLB_HGT_QUALITY_MEASURE_CONTROL */ "", 18913 /* DLB_HGT_QUANTIZED_AVG_QUALITY_MEASURE */ "", 18914 /* DLB_HGT_QUANTIZE_CONTROL */ "", 18915 /* DLB_HGT_RANDOM_SELECTION_CONTROL */ "", 18916 /* DLB_HGT_RANDOM_SELECTION_CONTROL_X */ "", 18917 /* DLB_HGT_RANDOM_SELECTION_CONTROL_Y */ "", 18918 /* DLB_HGT_REFRESH_INDEX */ "", 18919 /* DLB_HGT_REFRESH_INDEX_X */ "", 18920 /* DLB_HGT_REFRESH_INDEX_Y */ "", 18921 /* DLB_HGT_SER_CONTROL */ "", 18922 /* DLB_ID_0_TO_63_ENABLE */ "", 18923 /* DLB_ID_64_TO_127_ENABLE */ "", 18924 /* DLB_IETR_CLK_CTRL */ "", 18925 /* DLB_IETR_CLK_CTRL_PIPE0 */ "", 18926 /* DLB_IETR_CLK_CTRL_PIPE1 */ "", 18927 /* DLB_IETR_CLK_CTRL_PIPE2 */ "", 18928 /* DLB_IETR_CLK_CTRL_PIPE3 */ "", 18929 /* DLB_IETR_CLK_CTRL_PIPE4 */ "", 18930 /* DLB_IETR_CLK_CTRL_PIPE5 */ "", 18931 /* DLB_IETR_CLK_CTRL_PIPE6 */ "", 18932 /* DLB_IETR_CLK_CTRL_PIPE7 */ "", 18933 /* DLB_LAG_CLEAR_METRIC_STATE_64 */ "", 18934 /* DLB_LAG_CURRENT_TIME */ "", 18935 /* DLB_LAG_EOP_BUFFER */ "", 18936 /* DLB_LAG_FLOWSET_PDA_CONTROL */ "", 18937 /* DLB_LAG_MEMBER_HW_STATE_64 */ "", 18938 /* DLB_LAG_PLA_QUALITY_MEASURE_CONTROL */ "", 18939 /* DLB_LAG_QUALITY_MEASURE_CONTROL */ "", 18940 /* DLB_LAG_RAM_CONTROL */ "", 18941 /* DLB_LAG_RANDOM_SELECTION_CONTROL */ "", 18942 /* DLB_LAG_REFRESH_INDEX */ "", 18943 /* DLB_LAG_SER_CONTROL */ "", 18944 /* DLFBC_STORM_CONTROL */ "", 18945 /* DMAC_M0_IDM_IDM_INTERRUPT_STATUS */ "", 18946 /* DMAC_M0_IDM_IDM_RESET_STATUS */ "", 18947 /* DMAC_M0_IDM_IO_CONTROL_DIRECT */ "", 18948 /* DMAC_M0_IDM_IO_STATUS */ "", 18949 /* DMAC_M0_IDM_RESET_CONTROL */ "", 18950 /* DMAC_PL330_CC_0 */ "", 18951 /* DMAC_PL330_CC_1 */ "", 18952 /* DMAC_PL330_CC_2 */ "", 18953 /* DMAC_PL330_CC_3 */ "", 18954 /* DMAC_PL330_CC_4 */ "", 18955 /* DMAC_PL330_CC_5 */ "", 18956 /* DMAC_PL330_CC_6 */ "", 18957 /* DMAC_PL330_CC_7 */ "", 18958 /* DMAC_PL330_CPC0 */ "", 18959 /* DMAC_PL330_CPC1 */ "", 18960 /* DMAC_PL330_CPC2 */ "", 18961 /* DMAC_PL330_CPC3 */ "", 18962 /* DMAC_PL330_CPC4 */ "", 18963 /* DMAC_PL330_CPC5 */ "", 18964 /* DMAC_PL330_CPC6 */ "", 18965 /* DMAC_PL330_CPC7 */ "", 18966 /* DMAC_PL330_CR0 */ "", 18967 /* DMAC_PL330_CR1 */ "", 18968 /* DMAC_PL330_CR2 */ "", 18969 /* DMAC_PL330_CR3 */ "", 18970 /* DMAC_PL330_CR4 */ "", 18971 /* DMAC_PL330_CRDN */ "", 18972 /* DMAC_PL330_CS0 */ "", 18973 /* DMAC_PL330_CS1 */ "", 18974 /* DMAC_PL330_CS2 */ "", 18975 /* DMAC_PL330_CS3 */ "", 18976 /* DMAC_PL330_CS4 */ "", 18977 /* DMAC_PL330_CS5 */ "", 18978 /* DMAC_PL330_CS6 */ "", 18979 /* DMAC_PL330_CS7 */ "", 18980 /* DMAC_PL330_DA_0 */ "", 18981 /* DMAC_PL330_DA_1 */ "", 18982 /* DMAC_PL330_DA_2 */ "", 18983 /* DMAC_PL330_DA_3 */ "", 18984 /* DMAC_PL330_DA_4 */ "", 18985 /* DMAC_PL330_DA_5 */ "", 18986 /* DMAC_PL330_DA_6 */ "", 18987 /* DMAC_PL330_DA_7 */ "", 18988 /* DMAC_PL330_DBGCMD */ "", 18989 /* DMAC_PL330_DBGINST0 */ "", 18990 /* DMAC_PL330_DBGINST1 */ "", 18991 /* DMAC_PL330_DBGSTATUS */ "", 18992 /* DMAC_PL330_DPC */ "", 18993 /* DMAC_PL330_DS */ "", 18994 /* DMAC_PL330_FSC */ "", 18995 /* DMAC_PL330_FSM */ "", 18996 /* DMAC_PL330_FTC0 */ "", 18997 /* DMAC_PL330_FTC1 */ "", 18998 /* DMAC_PL330_FTC2 */ "", 18999 /* DMAC_PL330_FTC3 */ "", 19000 /* DMAC_PL330_FTC4 */ "", 19001 /* DMAC_PL330_FTC5 */ "", 19002 /* DMAC_PL330_FTC6 */ "", 19003 /* DMAC_PL330_FTC7 */ "", 19004 /* DMAC_PL330_FTM */ "", 19005 /* DMAC_PL330_INTCLR */ "", 19006 /* DMAC_PL330_INTEN */ "", 19007 /* DMAC_PL330_INTSTATUS */ "", 19008 /* DMAC_PL330_INT_EVENT_RIS */ "", 19009 /* DMAC_PL330_LC0_0 */ "", 19010 /* DMAC_PL330_LC0_1 */ "", 19011 /* DMAC_PL330_LC0_2 */ "", 19012 /* DMAC_PL330_LC0_3 */ "", 19013 /* DMAC_PL330_LC0_4 */ "", 19014 /* DMAC_PL330_LC0_5 */ "", 19015 /* DMAC_PL330_LC0_6 */ "", 19016 /* DMAC_PL330_LC0_7 */ "", 19017 /* DMAC_PL330_LC1_0 */ "", 19018 /* DMAC_PL330_LC1_1 */ "", 19019 /* DMAC_PL330_LC1_2 */ "", 19020 /* DMAC_PL330_LC1_3 */ "", 19021 /* DMAC_PL330_LC1_4 */ "", 19022 /* DMAC_PL330_LC1_5 */ "", 19023 /* DMAC_PL330_LC1_6 */ "", 19024 /* DMAC_PL330_LC1_7 */ "", 19025 /* DMAC_PL330_SA_0 */ "", 19026 /* DMAC_PL330_SA_1 */ "", 19027 /* DMAC_PL330_SA_2 */ "", 19028 /* DMAC_PL330_SA_3 */ "", 19029 /* DMAC_PL330_SA_4 */ "", 19030 /* DMAC_PL330_SA_5 */ "", 19031 /* DMAC_PL330_SA_6 */ "", 19032 /* DMAC_PL330_SA_7 */ "", 19033 /* DMAC_PL330_WD */ "", 19034 /* DMA_MCS_BUF_MEM_CONTROL */ "", 19035 /* DMA_PCIE_BUF_MEM_CONTROL */ "", 19036 /* DMU_CRU_IHOST_PWR_CONTROL */ "", 19037 /* DMU_CRU_IHOST_PWR_CONTROL_STATUS */ "", 19038 /* DMU_CRU_IPROC_DEBUG_SEL */ "", 19039 /* DMU_CRU_IPROC_DEBUG_STATUS */ "", 19040 /* DMU_CRU_RESET */ "", 19041 /* DMU_M0_IDM_IDM_INTERRUPT_STATUS */ "", 19042 /* DMU_M0_IDM_IDM_IO_CONTROL_DIRECT */ "", 19043 /* DMU_M0_IDM_IDM_IO_STATUS */ "", 19044 /* DMU_M0_IDM_IDM_RESET_CONTROL */ "", 19045 /* DMU_M0_IDM_IDM_RESET_STATUS */ "", 19046 /* DMU_PCU_CHIP_PLL_LOCK_CONTROL */ "", 19047 /* DMU_PCU_CHIP_PLL_LOCK_STATUS */ "", 19048 /* DMU_PCU_CRU_RESET_REASON */ "", 19049 /* DMU_PCU_DEBUG_BUS */ "", 19050 /* DMU_PCU_DEBUG_BUS_SEL */ "", 19051 /* DMU_PCU_IPROC_CONTROL */ "", 19052 /* DMU_PCU_IPROC_RESET_REASON */ "", 19053 /* DMU_PCU_IPROC_STATUS */ "", 19054 /* DMU_PCU_IPROC_STRAPS_CAPTURED */ "", 19055 /* DMU_PCU_IPROC_STRAPS_SW_OVERRIDE */ "", 19056 /* DMU_PCU_OTP_CONFIG */ "", 19057 /* DMU_PCU_OTP_CONFIG_0 */ "", 19058 /* DMU_PCU_OTP_CONFIG_1 */ "", 19059 /* DMU_PCU_OTP_CONFIG_2 */ "", 19060 /* DMU_PCU_OTP_CONFIG_3 */ "", 19061 /* DMU_PCU_OTP_CONFIG_4 */ "", 19062 /* DMU_PCU_OTP_CONFIG_5 */ "", 19063 /* DMU_PCU_OTP_CONFIG_6 */ "", 19064 /* DMU_PCU_OTP_CONFIG_7 */ "", 19065 /* DMU_PCU_OTP_CONFIG_8 */ "", 19066 /* DMU_PCU_OTP_CONFIG_9 */ "", 19067 /* DMU_PCU_OTP_CONFIG_10 */ "", 19068 /* DMU_PCU_OTP_CONFIG_11 */ "", 19069 /* DMU_PCU_OTP_CONFIG_12 */ "", 19070 /* DMU_PCU_OTP_CONFIG_13 */ "", 19071 /* DMU_PCU_OTP_CONFIG_14 */ "", 19072 /* DMU_PCU_OTP_CONFIG_15 */ "", 19073 /* DMU_PCU_OTP_CONFIG_16 */ "", 19074 /* DMU_PCU_OTP_CONFIG_17 */ "", 19075 /* DMU_PCU_OTP_CONFIG_18 */ "", 19076 /* DMU_PCU_OTP_CONFIG_19 */ "", 19077 /* DMU_PCU_OTP_CONFIG_20 */ "", 19078 /* DMU_PCU_OTP_CONFIG_21 */ "", 19079 /* DMU_PCU_OTP_CONFIG_22 */ "", 19080 /* DMU_PCU_OTP_CONFIG_23 */ "", 19081 /* DMU_PCU_OTP_CONFIG_24 */ "", 19082 /* DMU_PCU_OTP_CONFIG_25 */ "", 19083 /* DMU_PCU_OTP_CONFIG_26 */ "", 19084 /* DMU_PCU_OTP_CONFIG_27 */ "", 19085 /* DMU_PCU_OTP_CONFIG_28 */ "", 19086 /* DMU_PCU_OTP_CONFIG_29 */ "", 19087 /* DMU_PCU_OTP_CONFIG_30 */ "", 19088 /* DMU_PCU_OTP_CONFIG_31 */ "", 19089 /* DMU_PCU_OTP_SW_OVERRIDE */ "", 19090 /* DMU_PCU_OTP_SW_OVERRIDE_0 */ "", 19091 /* DMU_PCU_OTP_SW_OVERRIDE_1 */ "", 19092 /* DMU_PCU_OTP_SW_OVERRIDE_2 */ "", 19093 /* DMU_PCU_OTP_SW_OVERRIDE_3 */ "", 19094 /* DMU_PCU_OTP_SW_OVERRIDE_4 */ "", 19095 /* DMU_PCU_OTP_SW_OVERRIDE_5 */ "", 19096 /* DMU_PCU_OTP_SW_OVERRIDE_6 */ "", 19097 /* DMU_PCU_OTP_SW_OVERRIDE_7 */ "", 19098 /* DMU_PCU_OTP_SW_OVERRIDE_8 */ "", 19099 /* DMU_PCU_OTP_SW_OVERRIDE_9 */ "", 19100 /* DMU_PCU_OTP_SW_OVERRIDE_10 */ "", 19101 /* DMU_PCU_OTP_SW_OVERRIDE_11 */ "", 19102 /* DMU_PCU_OTP_SW_OVERRIDE_12 */ "", 19103 /* DMU_PCU_OTP_SW_OVERRIDE_13 */ "", 19104 /* DMU_PCU_OTP_SW_OVERRIDE_14 */ "", 19105 /* DMU_PCU_OTP_SW_OVERRIDE_15 */ "", 19106 /* DMU_PCU_OTP_SW_OVERRIDE_16 */ "", 19107 /* DMU_PCU_OTP_SW_OVERRIDE_17 */ "", 19108 /* DMU_PCU_OTP_SW_OVERRIDE_18 */ "", 19109 /* DMU_PCU_OTP_SW_OVERRIDE_19 */ "", 19110 /* DMU_PCU_OTP_SW_OVERRIDE_20 */ "", 19111 /* DMU_PCU_OTP_SW_OVERRIDE_21 */ "", 19112 /* DMU_PCU_OTP_SW_OVERRIDE_22 */ "", 19113 /* DMU_PCU_OTP_SW_OVERRIDE_23 */ "", 19114 /* DMU_PCU_OTP_SW_OVERRIDE_24 */ "", 19115 /* DMU_PCU_OTP_SW_OVERRIDE_25 */ "", 19116 /* DMU_PCU_OTP_SW_OVERRIDE_26 */ "", 19117 /* DMU_PCU_OTP_SW_OVERRIDE_27 */ "", 19118 /* DMU_PCU_OTP_SW_OVERRIDE_28 */ "", 19119 /* DMU_PCU_OTP_SW_OVERRIDE_29 */ "", 19120 /* DMU_PCU_OTP_SW_OVERRIDE_30 */ "", 19121 /* DMU_PCU_OTP_SW_OVERRIDE_31 */ "", 19122 /* DMU_PCU_OTP_SW_OVERRIDE_EN */ "", 19123 /* DMU_PCU_PCIE_SLAVE_RESET_MODE */ "", 19124 /* DMU_PCU_POR_CONTROL */ "", 19125 /* DMU_PCU_SOFT_RESET */ "", 19126 /* DMU_PCU_SWITCH_RESET_REASON */ "", 19127 /* DMU_PCU_WATCHDOG_RESET_MODE */ "", 19128 /* DMU_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 19129 /* DMU_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 19130 /* DMU_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 19131 /* DMU_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 19132 /* DMU_S0_IDM_IDM_ERROR_LOG_ID */ "", 19133 /* DMU_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 19134 /* DMU_S0_IDM_IDM_INTERRUPT_STATUS */ "", 19135 /* DMU_S0_IDM_IDM_RESET_CONTROL */ "", 19136 /* DMU_S0_IDM_IDM_RESET_READ_ID */ "", 19137 /* DMU_S0_IDM_IDM_RESET_STATUS */ "", 19138 /* DMU_S0_IDM_IDM_RESET_WRITE_ID */ "", 19139 /* DMVOQ_WRED_CONFIG */ "", 19140 /* DNAT_DISCARDS */ "", 19141 /* DNAT_DISCARDS_64 */ "DNAT_DISCARDS", 19142 /* DNAT_DISCARDS_64_PIPE0 */ "DNAT_DISCARDS_PIPE0", 19143 /* DNAT_DISCARDS_64_PIPE1 */ "DNAT_DISCARDS_PIPE1", 19144 /* DNAT_DISCARDS_64_PIPE2 */ "DNAT_DISCARDS_PIPE2", 19145 /* DNAT_DISCARDS_64_PIPE3 */ "DNAT_DISCARDS_PIPE3", 19146 /* DNAT_DISCARDS_PIPE0 */ "", 19147 /* DNAT_DISCARDS_PIPE1 */ "", 19148 /* DNAT_DISCARDS_PIPE2 */ "", 19149 /* DNAT_DISCARDS_PIPE3 */ "", 19150 /* DNAT_TRANSLATIONS */ "", 19151 /* DNAT_TRANSLATIONS_64 */ "DNAT_TRANSLATIONS", 19152 /* DNAT_TRANSLATIONS_64_PIPE0 */ "DNAT_TRANSLATIONS_PIPE0", 19153 /* DNAT_TRANSLATIONS_64_PIPE1 */ "DNAT_TRANSLATIONS_PIPE1", 19154 /* DNAT_TRANSLATIONS_64_PIPE2 */ "DNAT_TRANSLATIONS_PIPE2", 19155 /* DNAT_TRANSLATIONS_64_PIPE3 */ "DNAT_TRANSLATIONS_PIPE3", 19156 /* DNAT_TRANSLATIONS_PIPE0 */ "", 19157 /* DNAT_TRANSLATIONS_PIPE1 */ "", 19158 /* DNAT_TRANSLATIONS_PIPE2 */ "", 19159 /* DNAT_TRANSLATIONS_PIPE3 */ "", 19160 /* DOS_CONTROL */ "", 19161 /* DOS_CONTROL_2 */ "", 19162 /* DOS_CONTROL_3 */ "", 19163 /* DPATHBISRDBGRDDATA */ "", 19164 /* DQM_AUTO_DOC_NAME_4 */ "", 19165 /* DQM_AUTO_DOC_NAME_10 */ "", 19166 /* DQM_AUTO_DOC_NAME_12 */ "", 19167 /* DQM_AUTO_DOC_NAME_16 */ "", 19168 /* DQM_AUTO_DOC_NAME_18 */ "", 19169 /* DQM_AUTO_DOC_NAME_20 */ "", 19170 /* DQM_AUTO_DOC_NAME_23 */ "", 19171 /* DQM_AUTO_DOC_NAME_26 */ "", 19172 /* DQM_AUTO_DOC_NAME_29 */ "", 19173 /* DQM_AUTO_DOC_NAME_31 */ "", 19174 /* DQM_AUTO_DOC_NAME_33 */ "", 19175 /* DQM_BDBLL_SIZE */ "", 19176 /* DQM_BDB_ALLOCATE_NRDY_CTR */ "", 19177 /* DQM_BDM_RD_ACCESS_DROP_CTR */ "", 19178 /* DQM_BDM_RD_ACCESS_VALID_CTR */ "", 19179 /* DQM_BDM_WR_ACCESS_VALID_CTR */ "", 19180 /* DQM_BD_RD_REQ_NRDY_CTR */ "", 19181 /* DQM_BD_WR_REQ_NRDY_CTR */ "", 19182 /* DQM_BUNDLE_DEQ_CTR */ "", 19183 /* DQM_BUNDLE_ENQ_CTR */ "", 19184 /* DQM_DEQ_RPRT_CTR */ "", 19185 /* DQM_DQM_ENABLERS */ "", 19186 /* DQM_DQM_INIT */ "", 19187 /* DQM_ECC_1B_ERR_CNT */ "", 19188 /* DQM_ECC_2B_ERR_CNT */ "", 19189 /* DQM_ECC_ERR_1B_INITIATE */ "", 19190 /* DQM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 19191 /* DQM_ECC_ERR_2B_INITIATE */ "", 19192 /* DQM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 19193 /* DQM_ECC_INTERRUPT_REGISTER */ "", 19194 /* DQM_ECC_INTERRUPT_REGISTER_MASK */ "", 19195 /* DQM_ECC_INTERRUPT_REGISTER_TEST */ "", 19196 /* DQM_EDRA_RPRT_FIFO_IRDY_TH */ "", 19197 /* DQM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 19198 /* DQM_ENQ_RPRT_CTR */ "", 19199 /* DQM_ERROR_INITIATION_DATA */ "", 19200 /* DQM_FREE_BDBLL_MIN_SIZE */ "", 19201 /* DQM_FREE_BDBLL_SIZE */ "", 19202 /* DQM_FR_BDB_CACHE_SETTINGS */ "", 19203 /* DQM_GLOBAL_MEM_OPTIONS */ "", 19204 /* DQM_GTIMER_CONFIGURATION */ "", 19205 /* DQM_GTIMER_CYCLE */ "", 19206 /* DQM_INDIRECT_COMMAND */ "", 19207 /* DQM_INDIRECT_COMMAND_ADDRESS */ "", 19208 /* DQM_INDIRECT_COMMAND_DATA_INCREMENT */ "", 19209 /* DQM_INDIRECT_COMMAND_RD_DATA */ "", 19210 /* DQM_INDIRECT_COMMAND_WIDE_MEM */ "", 19211 /* DQM_INDIRECT_COMMAND_WR_DATA */ "", 19212 /* DQM_INDIRECT_FORCE_BUBBLE */ "", 19213 /* DQM_INTERNAL_FIFO_THS */ "", 19214 /* DQM_INTERRUPT_MASK_REGISTER */ "", 19215 /* DQM_INTERRUPT_REGISTER */ "", 19216 /* DQM_INTERRUPT_REGISTER_TEST */ "", 19217 /* DQM_IQM_BUNDLE_TX_NRDY_CTR */ "", 19218 /* DQM_LAST_DEQ_CMD */ "", 19219 /* DQM_LAST_ENQ_CMD */ "", 19220 /* DQM_QDC_ERR_INTERRUPT_REGISTER */ "", 19221 /* DQM_QDC_ERR_INTERRUPT_REGISTER_MASK */ "", 19222 /* DQM_QDC_ERR_INTERRUPT_REGISTER_TEST */ "", 19223 /* DQM_REG_0041 */ "", 19224 /* DQM_REG_0112 */ "", 19225 /* DQM_REG_0113 */ "", 19226 /* DQM_REG_0115 */ "", 19227 /* DQM_REG_0116 */ "", 19228 /* DQM_REG_0117 */ "", 19229 /* DQM_REG_0119 */ "", 19230 /* DQM_REG_00A4 */ "", 19231 /* DQM_REG_00A6 */ "", 19232 /* DQM_REG_00C2 */ "", 19233 /* DQM_REG_00C5 */ "", 19234 /* DQM_REG_00C7 */ "", 19235 /* DQM_REG_011C */ "", 19236 /* DQM_REG_011E */ "", 19237 /* DQM_REG_011F */ "", 19238 /* DQM_RESERVED_MIRROR_ADDR */ "", 19239 /* DQM_RESERVED_MTCD */ "", 19240 /* DQM_RESERVED_MTCP */ "", 19241 /* DQM_RESERVED_PCMI_0 */ "", 19242 /* DQM_RESERVED_PCMI_1 */ "", 19243 /* DQM_RESERVED_PCMI_2 */ "", 19244 /* DQM_RESERVED_PCMI_3 */ "", 19245 /* DQM_RESERVED_PCMI_4 */ "", 19246 /* DQM_RESERVED_PCMI_0_S */ "", 19247 /* DQM_RESERVED_PCMI_0_T */ "", 19248 /* DQM_RESERVED_PCMI_1_S */ "", 19249 /* DQM_RESERVED_PCMI_1_T */ "", 19250 /* DQM_RESERVED_PCMI_2_S */ "", 19251 /* DQM_RESERVED_PCMI_2_T */ "", 19252 /* DQM_RESERVED_PCMI_3_S */ "", 19253 /* DQM_RESERVED_PCMI_3_T */ "", 19254 /* DQM_RESERVED_PCMI_4_S */ "", 19255 /* DQM_RESERVED_PCMI_4_T */ "", 19256 /* DQM_RESERVED_SPARE_0 */ "", 19257 /* DQM_RESERVED_SPARE_1 */ "", 19258 /* DQM_RESERVED_SPARE_2 */ "", 19259 /* DQM_RESERVED_SPARE_3 */ "", 19260 /* DQM_SBUS_BROADCAST_ID */ "", 19261 /* DQM_SBUS_LAST_IN_CHAIN */ "", 19262 /* DQM_SQM_ENABLERS */ "", 19263 /* DQM_TX_BUNDLE_FIFO_MAX_STATUS */ "", 19264 /* DQM_TX_FIFO_ERR_INTERRUPT_REGISTER */ "", 19265 /* DQM_TX_FIFO_ERR_INTERRUPT_REGISTER_MASK */ "", 19266 /* DQM_TX_FIFO_ERR_INTERRUPT_REGISTER_TEST */ "", 19267 /* DQM_TX_FIFO_MAX_STATUS */ "", 19268 /* DQS_MEMDEBUG */ "", 19269 /* DRCA_AC_OPERATING_CONDITIONS_1 */ "", 19270 /* DRCA_AC_OPERATING_CONDITIONS_2 */ "", 19271 /* DRCA_AC_OPERATING_CONDITIONS_3 */ "", 19272 /* DRCA_AC_OPERATING_CONDITIONS_4 */ "", 19273 /* DRCA_AC_OPERATING_CONDITIONS_5 */ "", 19274 /* DRCA_ADDR_BANK_MAP */ "", 19275 /* DRCA_ADDR_WITH_RD_CRC */ "", 19276 /* DRCA_ADDR_WITH_WR_CRC */ "", 19277 /* DRCA_ALIGN_ERR_INDICATION */ "", 19278 /* DRCA_ASYNC_FIFO_CFG */ "", 19279 /* DRCA_AUXS_MUX */ "", 19280 /* DRCA_BIST_CONFIGURATIONS */ "", 19281 /* DRCA_BIST_DBI_ERR_OCCURED */ "", 19282 /* DRCA_BIST_EDC_ERR_OCCURED */ "", 19283 /* DRCA_BIST_END_ADDRESS */ "", 19284 /* DRCA_BIST_ERROR_OCCURRED */ "", 19285 /* DRCA_BIST_FULL_MASK_ERROR_COUNTER */ "", 19286 /* DRCA_BIST_FULL_MASK_WORD_0 */ "", 19287 /* DRCA_BIST_FULL_MASK_WORD_1 */ "", 19288 /* DRCA_BIST_FULL_MASK_WORD_2 */ "", 19289 /* DRCA_BIST_FULL_MASK_WORD_3 */ "", 19290 /* DRCA_BIST_FULL_MASK_WORD_4 */ "", 19291 /* DRCA_BIST_FULL_MASK_WORD_5 */ "", 19292 /* DRCA_BIST_FULL_MASK_WORD_6 */ "", 19293 /* DRCA_BIST_FULL_MASK_WORD_7 */ "", 19294 /* DRCA_BIST_GLOBAL_ERROR_COUNTER */ "", 19295 /* DRCA_BIST_LAST_ADDR_ERR */ "", 19296 /* DRCA_BIST_LAST_DATA_ERR */ "", 19297 /* DRCA_BIST_LAST_DATA_ERR_LSB */ "", 19298 /* DRCA_BIST_LAST_DATA_ERR_MSB */ "", 19299 /* DRCA_BIST_LAST_READ_DATA_LSB */ "", 19300 /* DRCA_BIST_LAST_READ_DATA_MSB */ "", 19301 /* DRCA_BIST_MPR_STAGGER_PATTERNS */ "", 19302 /* DRCA_BIST_MPR_STAGGER_WEIGHTS */ "", 19303 /* DRCA_BIST_NUMBER_OF_ACTIONS */ "", 19304 /* DRCA_BIST_PATTERN_REPETITION */ "", 19305 /* DRCA_BIST_PATTERN_WORD_0 */ "", 19306 /* DRCA_BIST_PATTERN_WORD_1 */ "", 19307 /* DRCA_BIST_PATTERN_WORD_2 */ "", 19308 /* DRCA_BIST_PATTERN_WORD_3 */ "", 19309 /* DRCA_BIST_PATTERN_WORD_4 */ "", 19310 /* DRCA_BIST_PATTERN_WORD_5 */ "", 19311 /* DRCA_BIST_PATTERN_WORD_6 */ "", 19312 /* DRCA_BIST_PATTERN_WORD_7 */ "", 19313 /* DRCA_BIST_PRBS_ADDR_SEED */ "", 19314 /* DRCA_BIST_PRBS_DATA_SEED_LSB */ "", 19315 /* DRCA_BIST_PRBS_DATA_SEED_MSB */ "", 19316 /* DRCA_BIST_RATE_LIMITER */ "", 19317 /* DRCA_BIST_REPEAT_PATTERN_1_LSB */ "", 19318 /* DRCA_BIST_REPEAT_PATTERN_1_MSB */ "", 19319 /* DRCA_BIST_REPEAT_PATTERN_2_LSB */ "", 19320 /* DRCA_BIST_REPEAT_PATTERN_2_MSB */ "", 19321 /* DRCA_BIST_REPEAT_PATTERN_3_LSB */ "", 19322 /* DRCA_BIST_REPEAT_PATTERN_3_MSB */ "", 19323 /* DRCA_BIST_REPEAT_PATTERN_4_LSB */ "", 19324 /* DRCA_BIST_REPEAT_PATTERN_4_MSB */ "", 19325 /* DRCA_BIST_REPEAT_PATTERN_5_LSB */ "", 19326 /* DRCA_BIST_REPEAT_PATTERN_5_MSB */ "", 19327 /* DRCA_BIST_REPEAT_PATTERN_6_LSB */ "", 19328 /* DRCA_BIST_REPEAT_PATTERN_6_MSB */ "", 19329 /* DRCA_BIST_REPEAT_PATTERN_7_LSB */ "", 19330 /* DRCA_BIST_REPEAT_PATTERN_7_MSB */ "", 19331 /* DRCA_BIST_SINGLE_BIT_MASK */ "", 19332 /* DRCA_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 19333 /* DRCA_BIST_START_ADDRESS */ "", 19334 /* DRCA_BIST_STATUSES */ "", 19335 /* DRCA_CALIBRATION_SEQUENCE_ADDRESS */ "", 19336 /* DRCA_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 19337 /* DRCA_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 19338 /* DRCA_CALIB_BIST_ERROR_OCCURRED */ "", 19339 /* DRCA_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 19340 /* DRCA_CLAM_SHELL */ "", 19341 /* DRCA_CNT_BIST_DBI_ERR_GLOBAL */ "", 19342 /* DRCA_CNT_BIST_EDC_ERR_GLOBAL */ "", 19343 /* DRCA_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 19344 /* DRCA_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 19345 /* DRCA_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 19346 /* DRCA_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 19347 /* DRCA_CPU_COMMANDS */ "", 19348 /* DRCA_DATA_LOCK */ "", 19349 /* DRCA_DATA_LOCK_TIMEOUT_PRD */ "", 19350 /* DRCA_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 19351 /* DRCA_DDR_CONTROLLER_TRIGGERS */ "", 19352 /* DRCA_DDR_EXTENDED_MODE_REGISTER_1 */ "", 19353 /* DRCA_DDR_EXTENDED_MODE_REGISTER_2 */ "", 19354 /* DRCA_DDR_EXTENDED_MODE_REGISTER_3 */ "", 19355 /* DRCA_DDR_MODE_REGISTER_1 */ "", 19356 /* DRCA_DDR_MODE_REGISTER_2 */ "", 19357 /* DRCA_DDR_PHY_PLL_CTRL */ "", 19358 /* DRCA_DDR_PHY_PLL_DEBUG_PROGRAM */ "", 19359 /* DRCA_DDR_PHY_PLL_FREQ_CTRL */ "", 19360 /* DRCA_DDR_PHY_PLL_LOCK_DETECT_CTRL */ "", 19361 /* DRCA_DDR_PHY_PLL_RC */ "", 19362 /* DRCA_DDR_PHY_PLL_RESET */ "", 19363 /* DRCA_DDR_PHY_PLL_STATUS */ "", 19364 /* DRCA_DDR_PHY_PLL_VCO_CTRL */ "", 19365 /* DRCA_DDR_PHY_UPDATE_ENABLE */ "", 19366 /* DRCA_DPI_POWER */ "", 19367 /* DRCA_DPI_STATUS */ "", 19368 /* DRCA_DPI_STAT_CNTRL */ "", 19369 /* DRCA_DPRC_ENABLERS */ "", 19370 /* DRCA_DQ_BYTE_0_MAP */ "", 19371 /* DRCA_DQ_BYTE_1_MAP */ "", 19372 /* DRCA_DQ_BYTE_2_MAP */ "", 19373 /* DRCA_DQ_BYTE_3_MAP */ "", 19374 /* DRCA_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 19375 /* DRCA_DRAM_ERROR_DETECT */ "", 19376 /* DRCA_DRAM_ERROR_INNITATE */ "", 19377 /* DRCA_DRAM_ERROR_RECOVERY */ "", 19378 /* DRCA_DRAM_INIT_FINISHED */ "", 19379 /* DRCA_DRAM_MR_0 */ "", 19380 /* DRCA_DRAM_MR_1 */ "", 19381 /* DRCA_DRAM_MR_2 */ "", 19382 /* DRCA_DRAM_MR_3 */ "", 19383 /* DRCA_DRAM_MR_4 */ "", 19384 /* DRCA_DRAM_MR_5 */ "", 19385 /* DRCA_DRAM_MR_6 */ "", 19386 /* DRCA_DRAM_MR_7 */ "", 19387 /* DRCA_DRAM_MR_8 */ "", 19388 /* DRCA_DRAM_MR_9 */ "", 19389 /* DRCA_DRAM_MR_10 */ "", 19390 /* DRCA_DRAM_MR_11 */ "", 19391 /* DRCA_DRAM_MR_12 */ "", 19392 /* DRCA_DRAM_MR_13 */ "", 19393 /* DRCA_DRAM_MR_14 */ "", 19394 /* DRCA_DRAM_MR_15 */ "", 19395 /* DRCA_DRAM_SET */ "", 19396 /* DRCA_DRAM_SPECIAL_FEATURES */ "", 19397 /* DRCA_DRAM_TIME_PARAMS */ "", 19398 /* DRCA_DWF_WATERMARK */ "", 19399 /* DRCA_ECC_1B_ERR_CNT */ "", 19400 /* DRCA_ECC_2B_ERR_CNT */ "", 19401 /* DRCA_ECC_ERR_1B_INITIATE */ "", 19402 /* DRCA_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 19403 /* DRCA_ECC_ERR_2B_INITIATE */ "", 19404 /* DRCA_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 19405 /* DRCA_ECC_INTERRUPT_REGISTER */ "", 19406 /* DRCA_ECC_INTERRUPT_REGISTER_MASK */ "", 19407 /* DRCA_ECC_INTERRUPT_REGISTER_TEST */ "", 19408 /* DRCA_ERROR_INITIATION_DATA */ "", 19409 /* DRCA_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 19410 /* DRCA_EXTENDED_MODE_WR_2_REGISTER */ "", 19411 /* DRCA_EXT_PHY_CTRL_STATUS */ "", 19412 /* DRCA_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 19413 /* DRCA_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 19414 /* DRCA_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 19415 /* DRCA_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 19416 /* DRCA_GDDR_5_BIST_CONFIGURATIONS */ "", 19417 /* DRCA_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 19418 /* DRCA_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 19419 /* DRCA_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 19420 /* DRCA_GDDR_5_BIST_FINISH_PRD */ "", 19421 /* DRCA_GDDR_5_BIST_PRBS_ADT_SEED */ "", 19422 /* DRCA_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 19423 /* DRCA_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 19424 /* DRCA_GDDR_5_BIST_PRBS_DBI_SEED */ "", 19425 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 19426 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 19427 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 19428 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 19429 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 19430 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 19431 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 19432 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 19433 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_0_BL_16 */ "", 19434 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_1_BL_16 */ "", 19435 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_2_BL_16 */ "", 19436 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_3_BL_16 */ "", 19437 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_4_BL_16 */ "", 19438 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_5_BL_16 */ "", 19439 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_6_BL_16 */ "", 19440 /* DRCA_GDDR_5_BIST_RD_FIFO_PATTERN_7_BL_16 */ "", 19441 /* DRCA_GDDR_5_BIST_STATUSES */ "", 19442 /* DRCA_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 19443 /* DRCA_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 19444 /* DRCA_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 19445 /* DRCA_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 19446 /* DRCA_GDDR_5_SPECIAL_CMD_TIMING */ "", 19447 /* DRCA_GDDR_BIST_LAST_READ_DATA_LSB */ "", 19448 /* DRCA_GDDR_BIST_LAST_READ_DATA_MSB */ "", 19449 /* DRCA_GENERAL_CONFIGURATIONS */ "", 19450 /* DRCA_GLOBALF */ "", 19451 /* DRCA_GLOBAL_MEM_OPTIONS */ "", 19452 /* DRCA_GLUE_LOGIC_REGISTER */ "", 19453 /* DRCA_GTIMER_CONFIGURATION */ "", 19454 /* DRCA_GTIMER_TRIGGER */ "", 19455 /* DRCA_INITIALIZATION_CONTROLL */ "", 19456 /* DRCA_INIT_SEQUENCE_REGISTER */ "", 19457 /* DRCA_INTERRUPT_MASK_REGISTER */ "", 19458 /* DRCA_INTERRUPT_REGISTER */ "", 19459 /* DRCA_INTERRUPT_REGISTER_TEST */ "", 19460 /* DRCA_INTIAL_CALIB_USE_MPR */ "", 19461 /* DRCA_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 19462 /* DRCA_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 19463 /* DRCA_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 19464 /* DRCA_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 19465 /* DRCA_LOOPBACK_CONFIG */ "", 19466 /* DRCA_LOOPBACK_CONTROL */ "", 19467 /* DRCA_LOOPBACK_DBI_ERROR_OCCURRED */ "", 19468 /* DRCA_LOOPBACK_DBI_FULL_ERR_CNT */ "", 19469 /* DRCA_LOOPBACK_DBI_MASK_WORD */ "", 19470 /* DRCA_LOOPBACK_DBI_PATTERN_WORD */ "", 19471 /* DRCA_LOOPBACK_ERROR_OCCURRED */ "", 19472 /* DRCA_LOOPBACK_FULL_ERR_CNT */ "", 19473 /* DRCA_LOOPBACK_MASK_WORD */ "", 19474 /* DRCA_LOOPBACK_PATTERN_WORD */ "", 19475 /* DRCA_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 19476 /* DRCA_LOOPBACK_PRBS_DATA_SEED */ "", 19477 /* DRCA_LOOPBACK_PRBS_DBI_SEED */ "", 19478 /* DRCA_ODT_CONFIGURATION_REGISTER */ "", 19479 /* DRCA_PARITY_ERR_CNT */ "", 19480 /* DRCA_PAR_ERR_INITIATE */ "", 19481 /* DRCA_PAR_ERR_MEM_MASK */ "", 19482 /* DRCA_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 19483 /* DRCA_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 19484 /* DRCA_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 19485 /* DRCA_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 19486 /* DRCA_PHY_CALIBRATION */ "", 19487 /* DRCA_PHY_CALIBRATION_CFG */ "", 19488 /* DRCA_PHY_CALIBRATION_CTRL */ "", 19489 /* DRCA_PHY_CALIBRATION_RES_FIFO_CFG */ "", 19490 /* DRCA_PHY_CALIBRATION_RES_FIFO_CFG_0 */ "", 19491 /* DRCA_PHY_CALIBRATION_RES_FIFO_CFG_1 */ "", 19492 /* DRCA_PHY_CALIBRATION_RES_FIFO_CFG_2 */ "", 19493 /* DRCA_PHY_CALIBRATION_RES_FIFO_CFG_3 */ "", 19494 /* DRCA_PHY_CALIB_FINISHED */ "", 19495 /* DRCA_PPR_ACTIVE */ "", 19496 /* DRCA_PPR_CFG */ "", 19497 /* DRCA_PWD_CLOCK_CONTROL */ "", 19498 /* DRCA_RBUS_ADDR */ "", 19499 /* DRCA_RBUS_RDATA */ "", 19500 /* DRCA_RBUS_RD_RESULT */ "", 19501 /* DRCA_RBUS_WDATA */ "", 19502 /* DRCA_REGISTER_ACCESS_RD_DATA_VALID */ "", 19503 /* DRCA_REGISTER_CONTROL */ "", 19504 /* DRCA_REGISTER_CONTROL_RDATA */ "", 19505 /* DRCA_REGISTER_CONTROL_WDATA */ "", 19506 /* DRCA_REG_0085 */ "", 19507 /* DRCA_REG_0087 */ "", 19508 /* DRCA_REG_90 */ "", 19509 /* DRCA_REG_0091 */ "", 19510 /* DRCA_REG_0092 */ "", 19511 /* DRCA_REG_0093 */ "", 19512 /* DRCA_REG_0209 */ "", 19513 /* DRCA_REG_0210 */ "", 19514 /* DRCA_REG_0211 */ "", 19515 /* DRCA_REG_0212 */ "", 19516 /* DRCA_REG_0242 */ "", 19517 /* DRCA_REG_0243 */ "", 19518 /* DRCA_REG_00AF */ "", 19519 /* DRCA_REG_00B0 */ "", 19520 /* DRCA_REG_00B1 */ "", 19521 /* DRCA_REG_00B2 */ "", 19522 /* DRCA_REG_00B3 */ "", 19523 /* DRCA_REG_00B4 */ "", 19524 /* DRCA_REG_00B5 */ "", 19525 /* DRCA_REG_00B6 */ "", 19526 /* DRCA_REG_00B7 */ "", 19527 /* DRCA_REG_00B8 */ "", 19528 /* DRCA_REG_00B9 */ "", 19529 /* DRCA_REG_00BA */ "", 19530 /* DRCA_REG_00BB */ "", 19531 /* DRCA_REG_00BC */ "", 19532 /* DRCA_REG_00BD */ "", 19533 /* DRCA_REG_00BE */ "", 19534 /* DRCA_REG_00BF */ "", 19535 /* DRCA_REG_00C0 */ "", 19536 /* DRCA_REG_00C1 */ "", 19537 /* DRCA_REG_00C2 */ "", 19538 /* DRCA_REG_00C3 */ "", 19539 /* DRCA_REG_020A */ "", 19540 /* DRCA_REG_020B */ "", 19541 /* DRCA_REG_020C */ "", 19542 /* DRCA_REG_020D */ "", 19543 /* DRCA_REG_020E */ "", 19544 /* DRCA_REG_020F */ "", 19545 /* DRCA_REG_021C */ "", 19546 /* DRCA_REG_0B0 */ "", 19547 /* DRCA_RESERVED_MIRROR_ADDR */ "", 19548 /* DRCA_RESERVED_MTCD */ "", 19549 /* DRCA_RESERVED_MTCP */ "", 19550 /* DRCA_RESERVED_SPARE_0 */ "", 19551 /* DRCA_RESERVED_SPARE_1 */ "", 19552 /* DRCA_RESERVED_SPARE_2 */ "", 19553 /* DRCA_RESERVED_SPARE_3 */ "", 19554 /* DRCA_RETRANSMIT_STATUS */ "", 19555 /* DRCA_RXI_WATERMARK */ "", 19556 /* DRCA_SBUS_BROADCAST_ID */ "", 19557 /* DRCA_SBUS_LAST_IN_CHAIN */ "", 19558 /* DRCA_SHADOW_DRAM_MR_0 */ "", 19559 /* DRCA_SHADOW_DRAM_MR_1 */ "", 19560 /* DRCA_SHADOW_DRAM_MR_2 */ "", 19561 /* DRCA_SHADOW_DRAM_MR_3 */ "", 19562 /* DRCA_SHADOW_DRAM_MR_4 */ "", 19563 /* DRCA_SHADOW_DRAM_MR_5 */ "", 19564 /* DRCA_SHADOW_DRAM_MR_6 */ "", 19565 /* DRCA_SHADOW_DRAM_MR_7 */ "", 19566 /* DRCA_SHADOW_DRAM_MR_8 */ "", 19567 /* DRCA_SHADOW_DRAM_MR_9 */ "", 19568 /* DRCA_SHADOW_DRAM_MR_10 */ "", 19569 /* DRCA_SHADOW_DRAM_MR_11 */ "", 19570 /* DRCA_SHADOW_DRAM_MR_12 */ "", 19571 /* DRCA_SHADOW_DRAM_MR_13 */ "", 19572 /* DRCA_SHADOW_DRAM_MR_14 */ "", 19573 /* DRCA_SHADOW_DRAM_MR_15 */ "", 19574 /* DRCA_SPARE_REGISTER */ "", 19575 /* DRCA_SPARE_REGISTER_3 */ "", 19576 /* DRCA_TRAIN_INIT_TRIGERS */ "", 19577 /* DRCA_VDL_CNTRL */ "", 19578 /* DRCA_WRITE_READ_RATES */ "", 19579 /* DRCA_WR_CRC_WATERMARK */ "", 19580 /* DRCBROADCAST_AC_OPERATING_CONDITIONS_1 */ "", 19581 /* DRCBROADCAST_AC_OPERATING_CONDITIONS_2 */ "", 19582 /* DRCBROADCAST_AC_OPERATING_CONDITIONS_3 */ "", 19583 /* DRCBROADCAST_AC_OPERATING_CONDITIONS_4 */ "", 19584 /* DRCBROADCAST_AC_OPERATING_CONDITIONS_5 */ "", 19585 /* DRCBROADCAST_ADDR_BANK_MAP */ "", 19586 /* DRCBROADCAST_ADDR_WITH_RD_CRC */ "", 19587 /* DRCBROADCAST_ADDR_WITH_WR_CRC */ "", 19588 /* DRCBROADCAST_ALIGN_ERR_INDICATION */ "", 19589 /* DRCBROADCAST_AUXS_MUX */ "", 19590 /* DRCBROADCAST_BIST_CONFIGURATIONS */ "", 19591 /* DRCBROADCAST_BIST_DBI_ERR_OCCURED */ "", 19592 /* DRCBROADCAST_BIST_EDC_ERR_OCCURED */ "", 19593 /* DRCBROADCAST_BIST_END_ADDRESS */ "", 19594 /* DRCBROADCAST_BIST_ERROR_OCCURRED */ "", 19595 /* DRCBROADCAST_BIST_FULL_MASK_ERROR_COUNTER */ "", 19596 /* DRCBROADCAST_BIST_FULL_MASK_WORD_0 */ "", 19597 /* DRCBROADCAST_BIST_FULL_MASK_WORD_1 */ "", 19598 /* DRCBROADCAST_BIST_FULL_MASK_WORD_2 */ "", 19599 /* DRCBROADCAST_BIST_FULL_MASK_WORD_3 */ "", 19600 /* DRCBROADCAST_BIST_FULL_MASK_WORD_4 */ "", 19601 /* DRCBROADCAST_BIST_FULL_MASK_WORD_5 */ "", 19602 /* DRCBROADCAST_BIST_FULL_MASK_WORD_6 */ "", 19603 /* DRCBROADCAST_BIST_FULL_MASK_WORD_7 */ "", 19604 /* DRCBROADCAST_BIST_GLOBAL_ERROR_COUNTER */ "", 19605 /* DRCBROADCAST_BIST_LAST_ADDR_ERR */ "", 19606 /* DRCBROADCAST_BIST_LAST_DATA_ERR */ "", 19607 /* DRCBROADCAST_BIST_LAST_DATA_ERR_LSB */ "", 19608 /* DRCBROADCAST_BIST_LAST_DATA_ERR_MSB */ "", 19609 /* DRCBROADCAST_BIST_LAST_READ_DATA_LSB */ "", 19610 /* DRCBROADCAST_BIST_LAST_READ_DATA_MSB */ "", 19611 /* DRCBROADCAST_BIST_MPR_STAGGER_PATTERNS */ "", 19612 /* DRCBROADCAST_BIST_MPR_STAGGER_WEIGHTS */ "", 19613 /* DRCBROADCAST_BIST_NUMBER_OF_ACTIONS */ "", 19614 /* DRCBROADCAST_BIST_PATTERN_REPETITION */ "", 19615 /* DRCBROADCAST_BIST_PATTERN_WORD_0 */ "", 19616 /* DRCBROADCAST_BIST_PATTERN_WORD_1 */ "", 19617 /* DRCBROADCAST_BIST_PATTERN_WORD_2 */ "", 19618 /* DRCBROADCAST_BIST_PATTERN_WORD_3 */ "", 19619 /* DRCBROADCAST_BIST_PATTERN_WORD_4 */ "", 19620 /* DRCBROADCAST_BIST_PATTERN_WORD_5 */ "", 19621 /* DRCBROADCAST_BIST_PATTERN_WORD_6 */ "", 19622 /* DRCBROADCAST_BIST_PATTERN_WORD_7 */ "", 19623 /* DRCBROADCAST_BIST_PRBS_ADDR_SEED */ "", 19624 /* DRCBROADCAST_BIST_PRBS_DATA_SEED_LSB */ "", 19625 /* DRCBROADCAST_BIST_PRBS_DATA_SEED_MSB */ "", 19626 /* DRCBROADCAST_BIST_RATE_LIMITER */ "", 19627 /* DRCBROADCAST_BIST_REPEAT_PATTERN_1_LSB */ "", 19628 /* DRCBROADCAST_BIST_REPEAT_PATTERN_1_MSB */ "", 19629 /* DRCBROADCAST_BIST_REPEAT_PATTERN_2_LSB */ "", 19630 /* DRCBROADCAST_BIST_REPEAT_PATTERN_2_MSB */ "", 19631 /* DRCBROADCAST_BIST_REPEAT_PATTERN_3_LSB */ "", 19632 /* DRCBROADCAST_BIST_REPEAT_PATTERN_3_MSB */ "", 19633 /* DRCBROADCAST_BIST_REPEAT_PATTERN_4_LSB */ "", 19634 /* DRCBROADCAST_BIST_REPEAT_PATTERN_4_MSB */ "", 19635 /* DRCBROADCAST_BIST_REPEAT_PATTERN_5_LSB */ "", 19636 /* DRCBROADCAST_BIST_REPEAT_PATTERN_5_MSB */ "", 19637 /* DRCBROADCAST_BIST_REPEAT_PATTERN_6_LSB */ "", 19638 /* DRCBROADCAST_BIST_REPEAT_PATTERN_6_MSB */ "", 19639 /* DRCBROADCAST_BIST_REPEAT_PATTERN_7_LSB */ "", 19640 /* DRCBROADCAST_BIST_REPEAT_PATTERN_7_MSB */ "", 19641 /* DRCBROADCAST_BIST_SINGLE_BIT_MASK */ "", 19642 /* DRCBROADCAST_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 19643 /* DRCBROADCAST_BIST_START_ADDRESS */ "", 19644 /* DRCBROADCAST_BIST_STATUSES */ "", 19645 /* DRCBROADCAST_CALIBRATION_SEQUENCE_ADDRESS */ "", 19646 /* DRCBROADCAST_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 19647 /* DRCBROADCAST_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 19648 /* DRCBROADCAST_CALIB_BIST_ERROR_OCCURRED */ "", 19649 /* DRCBROADCAST_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 19650 /* DRCBROADCAST_CLAM_SHELL */ "", 19651 /* DRCBROADCAST_CNT_BIST_DBI_ERR_GLOBAL */ "", 19652 /* DRCBROADCAST_CNT_BIST_EDC_ERR_GLOBAL */ "", 19653 /* DRCBROADCAST_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 19654 /* DRCBROADCAST_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 19655 /* DRCBROADCAST_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 19656 /* DRCBROADCAST_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 19657 /* DRCBROADCAST_CPU_COMMANDS */ "", 19658 /* DRCBROADCAST_DATA_LOCK */ "", 19659 /* DRCBROADCAST_DATA_LOCK_TIMEOUT_PRD */ "", 19660 /* DRCBROADCAST_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 19661 /* DRCBROADCAST_DDR_CONTROLLER_TRIGGERS */ "", 19662 /* DRCBROADCAST_DDR_EXTENDED_MODE_REGISTER_1 */ "", 19663 /* DRCBROADCAST_DDR_EXTENDED_MODE_REGISTER_2 */ "", 19664 /* DRCBROADCAST_DDR_EXTENDED_MODE_REGISTER_3 */ "", 19665 /* DRCBROADCAST_DDR_MODE_REGISTER_1 */ "", 19666 /* DRCBROADCAST_DDR_MODE_REGISTER_2 */ "", 19667 /* DRCBROADCAST_DDR_PHY_PLL_CTRL */ "", 19668 /* DRCBROADCAST_DDR_PHY_PLL_FREQ_CTRL */ "", 19669 /* DRCBROADCAST_DDR_PHY_PLL_RC */ "", 19670 /* DRCBROADCAST_DDR_PHY_PLL_RESET */ "", 19671 /* DRCBROADCAST_DDR_PHY_PLL_STATUS */ "", 19672 /* DRCBROADCAST_DDR_PHY_UPDATE_ENABLE */ "", 19673 /* DRCBROADCAST_DPI_POWER */ "", 19674 /* DRCBROADCAST_DPI_STATUS */ "", 19675 /* DRCBROADCAST_DPI_STAT_CNTRL */ "", 19676 /* DRCBROADCAST_DPRC_ENABLERS */ "", 19677 /* DRCBROADCAST_DQ_BYTE_0_MAP */ "", 19678 /* DRCBROADCAST_DQ_BYTE_1_MAP */ "", 19679 /* DRCBROADCAST_DQ_BYTE_2_MAP */ "", 19680 /* DRCBROADCAST_DQ_BYTE_3_MAP */ "", 19681 /* DRCBROADCAST_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 19682 /* DRCBROADCAST_DRAM_ERROR_DETECT */ "", 19683 /* DRCBROADCAST_DRAM_ERROR_INNITATE */ "", 19684 /* DRCBROADCAST_DRAM_ERROR_RECOVERY */ "", 19685 /* DRCBROADCAST_DRAM_INIT_FINISHED */ "", 19686 /* DRCBROADCAST_DRAM_MR_0 */ "", 19687 /* DRCBROADCAST_DRAM_MR_1 */ "", 19688 /* DRCBROADCAST_DRAM_MR_2 */ "", 19689 /* DRCBROADCAST_DRAM_MR_3 */ "", 19690 /* DRCBROADCAST_DRAM_MR_4 */ "", 19691 /* DRCBROADCAST_DRAM_MR_5 */ "", 19692 /* DRCBROADCAST_DRAM_MR_6 */ "", 19693 /* DRCBROADCAST_DRAM_MR_7 */ "", 19694 /* DRCBROADCAST_DRAM_MR_8 */ "", 19695 /* DRCBROADCAST_DRAM_MR_12 */ "", 19696 /* DRCBROADCAST_DRAM_MR_14 */ "", 19697 /* DRCBROADCAST_DRAM_MR_15 */ "", 19698 /* DRCBROADCAST_DRAM_SET */ "", 19699 /* DRCBROADCAST_DRAM_SPECIAL_FEATURES */ "", 19700 /* DRCBROADCAST_DRAM_TIME_PARAMS */ "", 19701 /* DRCBROADCAST_DWF_WATERMARK */ "", 19702 /* DRCBROADCAST_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 19703 /* DRCBROADCAST_EXTENDED_MODE_WR_2_REGISTER */ "", 19704 /* DRCBROADCAST_EXT_PHY_CTRL_STATUS */ "", 19705 /* DRCBROADCAST_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 19706 /* DRCBROADCAST_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 19707 /* DRCBROADCAST_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 19708 /* DRCBROADCAST_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 19709 /* DRCBROADCAST_GDDR_5_BIST_CONFIGURATIONS */ "", 19710 /* DRCBROADCAST_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 19711 /* DRCBROADCAST_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 19712 /* DRCBROADCAST_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 19713 /* DRCBROADCAST_GDDR_5_BIST_FINISH_PRD */ "", 19714 /* DRCBROADCAST_GDDR_5_BIST_PRBS_ADT_SEED */ "", 19715 /* DRCBROADCAST_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 19716 /* DRCBROADCAST_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 19717 /* DRCBROADCAST_GDDR_5_BIST_PRBS_DBI_SEED */ "", 19718 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 19719 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 19720 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 19721 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 19722 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 19723 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 19724 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 19725 /* DRCBROADCAST_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 19726 /* DRCBROADCAST_GDDR_5_BIST_STATUSES */ "", 19727 /* DRCBROADCAST_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 19728 /* DRCBROADCAST_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 19729 /* DRCBROADCAST_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 19730 /* DRCBROADCAST_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 19731 /* DRCBROADCAST_GDDR_5_SPECIAL_CMD_TIMING */ "", 19732 /* DRCBROADCAST_GDDR_BIST_LAST_READ_DATA_LSB */ "", 19733 /* DRCBROADCAST_GDDR_BIST_LAST_READ_DATA_MSB */ "", 19734 /* DRCBROADCAST_GENERAL_CONFIGURATIONS */ "", 19735 /* DRCBROADCAST_GLOBALF */ "", 19736 /* DRCBROADCAST_GLOBAL_MEM_OPTIONS */ "", 19737 /* DRCBROADCAST_GLUE_LOGIC_REGISTER */ "", 19738 /* DRCBROADCAST_GTIMER_CONFIGURATION */ "", 19739 /* DRCBROADCAST_GTIMER_TRIGGER */ "", 19740 /* DRCBROADCAST_INITIALIZATION_CONTROLL */ "", 19741 /* DRCBROADCAST_INIT_SEQUENCE_REGISTER */ "", 19742 /* DRCBROADCAST_INTERRUPT_MASK_REGISTER */ "", 19743 /* DRCBROADCAST_INTERRUPT_REGISTER */ "", 19744 /* DRCBROADCAST_INTERRUPT_REGISTER_TEST */ "", 19745 /* DRCBROADCAST_INTIAL_CALIB_USE_MPR */ "", 19746 /* DRCBROADCAST_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 19747 /* DRCBROADCAST_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 19748 /* DRCBROADCAST_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 19749 /* DRCBROADCAST_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 19750 /* DRCBROADCAST_LOOPBACK_CONFIG */ "", 19751 /* DRCBROADCAST_LOOPBACK_CONTROL */ "", 19752 /* DRCBROADCAST_LOOPBACK_DBI_ERROR_OCCURRED */ "", 19753 /* DRCBROADCAST_LOOPBACK_DBI_FULL_ERR_CNT */ "", 19754 /* DRCBROADCAST_LOOPBACK_DBI_MASK_WORD */ "", 19755 /* DRCBROADCAST_LOOPBACK_DBI_PATTERN_WORD */ "", 19756 /* DRCBROADCAST_LOOPBACK_ERROR_OCCURRED */ "", 19757 /* DRCBROADCAST_LOOPBACK_FULL_ERR_CNT */ "", 19758 /* DRCBROADCAST_LOOPBACK_MASK_WORD */ "", 19759 /* DRCBROADCAST_LOOPBACK_PATTERN_WORD */ "", 19760 /* DRCBROADCAST_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 19761 /* DRCBROADCAST_LOOPBACK_PRBS_DATA_SEED */ "", 19762 /* DRCBROADCAST_LOOPBACK_PRBS_DBI_SEED */ "", 19763 /* DRCBROADCAST_ODT_CONFIGURATION_REGISTER */ "", 19764 /* DRCBROADCAST_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 19765 /* DRCBROADCAST_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 19766 /* DRCBROADCAST_PHY_CALIBRATION */ "", 19767 /* DRCBROADCAST_PHY_CALIBRATION_CFG */ "", 19768 /* DRCBROADCAST_PHY_CALIBRATION_CTRL */ "", 19769 /* DRCBROADCAST_PHY_CALIBRATION_RES_FIFO_CFG */ "", 19770 /* DRCBROADCAST_PHY_CALIB_FINISHED */ "", 19771 /* DRCBROADCAST_PPR_ACTIVE */ "", 19772 /* DRCBROADCAST_PPR_CFG */ "", 19773 /* DRCBROADCAST_PWD_CLOCK_CONTROL */ "", 19774 /* DRCBROADCAST_RBUS_ADDR */ "", 19775 /* DRCBROADCAST_RBUS_RDATA */ "", 19776 /* DRCBROADCAST_RBUS_RD_RESULT */ "", 19777 /* DRCBROADCAST_RBUS_WDATA */ "", 19778 /* DRCBROADCAST_REGISTER_ACCESS_RD_DATA_VALID */ "", 19779 /* DRCBROADCAST_REGISTER_CONTROL */ "", 19780 /* DRCBROADCAST_REGISTER_CONTROL_RDATA */ "", 19781 /* DRCBROADCAST_REGISTER_CONTROL_WDATA */ "", 19782 /* DRCBROADCAST_REG_0085 */ "", 19783 /* DRCBROADCAST_REG_0087 */ "", 19784 /* DRCBROADCAST_REG_90 */ "", 19785 /* DRCBROADCAST_REG_0091 */ "", 19786 /* DRCBROADCAST_REG_0092 */ "", 19787 /* DRCBROADCAST_REG_0093 */ "", 19788 /* DRCBROADCAST_REG_0209 */ "", 19789 /* DRCBROADCAST_REG_0210 */ "", 19790 /* DRCBROADCAST_REG_0211 */ "", 19791 /* DRCBROADCAST_REG_0212 */ "", 19792 /* DRCBROADCAST_REG_0242 */ "", 19793 /* DRCBROADCAST_REG_0243 */ "", 19794 /* DRCBROADCAST_REG_00AF */ "", 19795 /* DRCBROADCAST_REG_00B0 */ "", 19796 /* DRCBROADCAST_REG_00B1 */ "", 19797 /* DRCBROADCAST_REG_00B2 */ "", 19798 /* DRCBROADCAST_REG_00B3 */ "", 19799 /* DRCBROADCAST_REG_00B4 */ "", 19800 /* DRCBROADCAST_REG_00B5 */ "", 19801 /* DRCBROADCAST_REG_00B6 */ "", 19802 /* DRCBROADCAST_REG_00B7 */ "", 19803 /* DRCBROADCAST_REG_00B8 */ "", 19804 /* DRCBROADCAST_REG_00B9 */ "", 19805 /* DRCBROADCAST_REG_00BA */ "", 19806 /* DRCBROADCAST_REG_00BB */ "", 19807 /* DRCBROADCAST_REG_00BC */ "", 19808 /* DRCBROADCAST_REG_00BD */ "", 19809 /* DRCBROADCAST_REG_00BE */ "", 19810 /* DRCBROADCAST_REG_00BF */ "", 19811 /* DRCBROADCAST_REG_00C0 */ "", 19812 /* DRCBROADCAST_REG_00C1 */ "", 19813 /* DRCBROADCAST_REG_00C2 */ "", 19814 /* DRCBROADCAST_REG_00C3 */ "", 19815 /* DRCBROADCAST_REG_020A */ "", 19816 /* DRCBROADCAST_REG_020B */ "", 19817 /* DRCBROADCAST_REG_020C */ "", 19818 /* DRCBROADCAST_REG_020D */ "", 19819 /* DRCBROADCAST_REG_020E */ "", 19820 /* DRCBROADCAST_REG_020F */ "", 19821 /* DRCBROADCAST_REG_021C */ "", 19822 /* DRCBROADCAST_REG_0B0 */ "", 19823 /* DRCBROADCAST_RESERVED_MIRROR_ADDR */ "", 19824 /* DRCBROADCAST_RESERVED_MTCD */ "", 19825 /* DRCBROADCAST_RESERVED_MTCP */ "", 19826 /* DRCBROADCAST_RESERVED_SPARE_0 */ "", 19827 /* DRCBROADCAST_RESERVED_SPARE_1 */ "", 19828 /* DRCBROADCAST_RESERVED_SPARE_2 */ "", 19829 /* DRCBROADCAST_RESERVED_SPARE_3 */ "", 19830 /* DRCBROADCAST_RETRANSMIT_STATUS */ "", 19831 /* DRCBROADCAST_RXI_WATERMARK */ "", 19832 /* DRCBROADCAST_SBUS_BROADCAST_ID */ "", 19833 /* DRCBROADCAST_SBUS_LAST_IN_CHAIN */ "", 19834 /* DRCBROADCAST_SHADOW_DRAM_MR_0 */ "", 19835 /* DRCBROADCAST_SHADOW_DRAM_MR_1 */ "", 19836 /* DRCBROADCAST_SHADOW_DRAM_MR_2 */ "", 19837 /* DRCBROADCAST_SHADOW_DRAM_MR_3 */ "", 19838 /* DRCBROADCAST_SHADOW_DRAM_MR_4 */ "", 19839 /* DRCBROADCAST_SHADOW_DRAM_MR_5 */ "", 19840 /* DRCBROADCAST_SHADOW_DRAM_MR_6 */ "", 19841 /* DRCBROADCAST_SHADOW_DRAM_MR_7 */ "", 19842 /* DRCBROADCAST_SHADOW_DRAM_MR_8 */ "", 19843 /* DRCBROADCAST_SHADOW_DRAM_MR_12 */ "", 19844 /* DRCBROADCAST_SHADOW_DRAM_MR_14 */ "", 19845 /* DRCBROADCAST_SHADOW_DRAM_MR_15 */ "", 19846 /* DRCBROADCAST_SPARE_REGISTER */ "", 19847 /* DRCBROADCAST_SPARE_REGISTER_3 */ "", 19848 /* DRCBROADCAST_TRAIN_INIT_TRIGERS */ "", 19849 /* DRCBROADCAST_VDL_CNTRL */ "", 19850 /* DRCBROADCAST_WRITE_READ_RATES */ "", 19851 /* DRCBROADCAST_WR_CRC_WATERMARK */ "", 19852 /* DRCB_AC_OPERATING_CONDITIONS_1 */ "", 19853 /* DRCB_AC_OPERATING_CONDITIONS_2 */ "", 19854 /* DRCB_AC_OPERATING_CONDITIONS_3 */ "", 19855 /* DRCB_AC_OPERATING_CONDITIONS_4 */ "", 19856 /* DRCB_AC_OPERATING_CONDITIONS_5 */ "", 19857 /* DRCB_ADDR_BANK_MAP */ "", 19858 /* DRCB_ADDR_WITH_RD_CRC */ "", 19859 /* DRCB_ADDR_WITH_WR_CRC */ "", 19860 /* DRCB_ALIGN_ERR_INDICATION */ "", 19861 /* DRCB_ASYNC_FIFO_CFG */ "", 19862 /* DRCB_AUXS_MUX */ "", 19863 /* DRCB_BIST_CONFIGURATIONS */ "", 19864 /* DRCB_BIST_DBI_ERR_OCCURED */ "", 19865 /* DRCB_BIST_EDC_ERR_OCCURED */ "", 19866 /* DRCB_BIST_END_ADDRESS */ "", 19867 /* DRCB_BIST_ERROR_OCCURRED */ "", 19868 /* DRCB_BIST_FULL_MASK_ERROR_COUNTER */ "", 19869 /* DRCB_BIST_FULL_MASK_WORD_0 */ "", 19870 /* DRCB_BIST_FULL_MASK_WORD_1 */ "", 19871 /* DRCB_BIST_FULL_MASK_WORD_2 */ "", 19872 /* DRCB_BIST_FULL_MASK_WORD_3 */ "", 19873 /* DRCB_BIST_FULL_MASK_WORD_4 */ "", 19874 /* DRCB_BIST_FULL_MASK_WORD_5 */ "", 19875 /* DRCB_BIST_FULL_MASK_WORD_6 */ "", 19876 /* DRCB_BIST_FULL_MASK_WORD_7 */ "", 19877 /* DRCB_BIST_GLOBAL_ERROR_COUNTER */ "", 19878 /* DRCB_BIST_LAST_ADDR_ERR */ "", 19879 /* DRCB_BIST_LAST_DATA_ERR */ "", 19880 /* DRCB_BIST_LAST_DATA_ERR_LSB */ "", 19881 /* DRCB_BIST_LAST_DATA_ERR_MSB */ "", 19882 /* DRCB_BIST_LAST_READ_DATA_LSB */ "", 19883 /* DRCB_BIST_LAST_READ_DATA_MSB */ "", 19884 /* DRCB_BIST_MPR_STAGGER_PATTERNS */ "", 19885 /* DRCB_BIST_MPR_STAGGER_WEIGHTS */ "", 19886 /* DRCB_BIST_NUMBER_OF_ACTIONS */ "", 19887 /* DRCB_BIST_PATTERN_REPETITION */ "", 19888 /* DRCB_BIST_PATTERN_WORD_0 */ "", 19889 /* DRCB_BIST_PATTERN_WORD_1 */ "", 19890 /* DRCB_BIST_PATTERN_WORD_2 */ "", 19891 /* DRCB_BIST_PATTERN_WORD_3 */ "", 19892 /* DRCB_BIST_PATTERN_WORD_4 */ "", 19893 /* DRCB_BIST_PATTERN_WORD_5 */ "", 19894 /* DRCB_BIST_PATTERN_WORD_6 */ "", 19895 /* DRCB_BIST_PATTERN_WORD_7 */ "", 19896 /* DRCB_BIST_PRBS_ADDR_SEED */ "", 19897 /* DRCB_BIST_PRBS_DATA_SEED_LSB */ "", 19898 /* DRCB_BIST_PRBS_DATA_SEED_MSB */ "", 19899 /* DRCB_BIST_RATE_LIMITER */ "", 19900 /* DRCB_BIST_REPEAT_PATTERN_1_LSB */ "", 19901 /* DRCB_BIST_REPEAT_PATTERN_1_MSB */ "", 19902 /* DRCB_BIST_REPEAT_PATTERN_2_LSB */ "", 19903 /* DRCB_BIST_REPEAT_PATTERN_2_MSB */ "", 19904 /* DRCB_BIST_REPEAT_PATTERN_3_LSB */ "", 19905 /* DRCB_BIST_REPEAT_PATTERN_3_MSB */ "", 19906 /* DRCB_BIST_REPEAT_PATTERN_4_LSB */ "", 19907 /* DRCB_BIST_REPEAT_PATTERN_4_MSB */ "", 19908 /* DRCB_BIST_REPEAT_PATTERN_5_LSB */ "", 19909 /* DRCB_BIST_REPEAT_PATTERN_5_MSB */ "", 19910 /* DRCB_BIST_REPEAT_PATTERN_6_LSB */ "", 19911 /* DRCB_BIST_REPEAT_PATTERN_6_MSB */ "", 19912 /* DRCB_BIST_REPEAT_PATTERN_7_LSB */ "", 19913 /* DRCB_BIST_REPEAT_PATTERN_7_MSB */ "", 19914 /* DRCB_BIST_SINGLE_BIT_MASK */ "", 19915 /* DRCB_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 19916 /* DRCB_BIST_START_ADDRESS */ "", 19917 /* DRCB_BIST_STATUSES */ "", 19918 /* DRCB_CALIBRATION_SEQUENCE_ADDRESS */ "", 19919 /* DRCB_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 19920 /* DRCB_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 19921 /* DRCB_CALIB_BIST_ERROR_OCCURRED */ "", 19922 /* DRCB_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 19923 /* DRCB_CLAM_SHELL */ "", 19924 /* DRCB_CNT_BIST_DBI_ERR_GLOBAL */ "", 19925 /* DRCB_CNT_BIST_EDC_ERR_GLOBAL */ "", 19926 /* DRCB_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 19927 /* DRCB_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 19928 /* DRCB_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 19929 /* DRCB_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 19930 /* DRCB_CPU_COMMANDS */ "", 19931 /* DRCB_DATA_LOCK */ "", 19932 /* DRCB_DATA_LOCK_TIMEOUT_PRD */ "", 19933 /* DRCB_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 19934 /* DRCB_DDR_CONTROLLER_TRIGGERS */ "", 19935 /* DRCB_DDR_EXTENDED_MODE_REGISTER_1 */ "", 19936 /* DRCB_DDR_EXTENDED_MODE_REGISTER_2 */ "", 19937 /* DRCB_DDR_EXTENDED_MODE_REGISTER_3 */ "", 19938 /* DRCB_DDR_MODE_REGISTER_1 */ "", 19939 /* DRCB_DDR_MODE_REGISTER_2 */ "", 19940 /* DRCB_DDR_PHY_PLL_CTRL */ "", 19941 /* DRCB_DDR_PHY_PLL_FREQ_CTRL */ "", 19942 /* DRCB_DDR_PHY_PLL_RC */ "", 19943 /* DRCB_DDR_PHY_PLL_RESET */ "", 19944 /* DRCB_DDR_PHY_PLL_STATUS */ "", 19945 /* DRCB_DDR_PHY_UPDATE_ENABLE */ "", 19946 /* DRCB_DPI_POWER */ "", 19947 /* DRCB_DPI_STATUS */ "", 19948 /* DRCB_DPI_STAT_CNTRL */ "", 19949 /* DRCB_DPRC_ENABLERS */ "", 19950 /* DRCB_DQ_BYTE_0_MAP */ "", 19951 /* DRCB_DQ_BYTE_1_MAP */ "", 19952 /* DRCB_DQ_BYTE_2_MAP */ "", 19953 /* DRCB_DQ_BYTE_3_MAP */ "", 19954 /* DRCB_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 19955 /* DRCB_DRAM_ERROR_DETECT */ "", 19956 /* DRCB_DRAM_ERROR_INNITATE */ "", 19957 /* DRCB_DRAM_ERROR_RECOVERY */ "", 19958 /* DRCB_DRAM_INIT_FINISHED */ "", 19959 /* DRCB_DRAM_MR_0 */ "", 19960 /* DRCB_DRAM_MR_1 */ "", 19961 /* DRCB_DRAM_MR_2 */ "", 19962 /* DRCB_DRAM_MR_3 */ "", 19963 /* DRCB_DRAM_MR_4 */ "", 19964 /* DRCB_DRAM_MR_5 */ "", 19965 /* DRCB_DRAM_MR_6 */ "", 19966 /* DRCB_DRAM_MR_7 */ "", 19967 /* DRCB_DRAM_MR_8 */ "", 19968 /* DRCB_DRAM_MR_12 */ "", 19969 /* DRCB_DRAM_MR_14 */ "", 19970 /* DRCB_DRAM_MR_15 */ "", 19971 /* DRCB_DRAM_SET */ "", 19972 /* DRCB_DRAM_SPECIAL_FEATURES */ "", 19973 /* DRCB_DRAM_TIME_PARAMS */ "", 19974 /* DRCB_DWF_WATERMARK */ "", 19975 /* DRCB_ECC_1B_ERR_CNT */ "", 19976 /* DRCB_ECC_2B_ERR_CNT */ "", 19977 /* DRCB_ECC_ERR_1B_INITIATE */ "", 19978 /* DRCB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 19979 /* DRCB_ECC_ERR_2B_INITIATE */ "", 19980 /* DRCB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 19981 /* DRCB_ECC_INTERRUPT_REGISTER */ "", 19982 /* DRCB_ECC_INTERRUPT_REGISTER_MASK */ "", 19983 /* DRCB_ECC_INTERRUPT_REGISTER_TEST */ "", 19984 /* DRCB_ERROR_INITIATION_DATA */ "", 19985 /* DRCB_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 19986 /* DRCB_EXTENDED_MODE_WR_2_REGISTER */ "", 19987 /* DRCB_EXT_PHY_CTRL_STATUS */ "", 19988 /* DRCB_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 19989 /* DRCB_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 19990 /* DRCB_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 19991 /* DRCB_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 19992 /* DRCB_GDDR_5_BIST_CONFIGURATIONS */ "", 19993 /* DRCB_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 19994 /* DRCB_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 19995 /* DRCB_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 19996 /* DRCB_GDDR_5_BIST_FINISH_PRD */ "", 19997 /* DRCB_GDDR_5_BIST_PRBS_ADT_SEED */ "", 19998 /* DRCB_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 19999 /* DRCB_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 20000 /* DRCB_GDDR_5_BIST_PRBS_DBI_SEED */ "", 20001 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 20002 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 20003 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 20004 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 20005 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 20006 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 20007 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 20008 /* DRCB_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 20009 /* DRCB_GDDR_5_BIST_STATUSES */ "", 20010 /* DRCB_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 20011 /* DRCB_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 20012 /* DRCB_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 20013 /* DRCB_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 20014 /* DRCB_GDDR_5_SPECIAL_CMD_TIMING */ "", 20015 /* DRCB_GDDR_BIST_LAST_READ_DATA_LSB */ "", 20016 /* DRCB_GDDR_BIST_LAST_READ_DATA_MSB */ "", 20017 /* DRCB_GENERAL_CONFIGURATIONS */ "", 20018 /* DRCB_GLOBALF */ "", 20019 /* DRCB_GLOBAL_MEM_OPTIONS */ "", 20020 /* DRCB_GLUE_LOGIC_REGISTER */ "", 20021 /* DRCB_GTIMER_CONFIGURATION */ "", 20022 /* DRCB_GTIMER_TRIGGER */ "", 20023 /* DRCB_INITIALIZATION_CONTROLL */ "", 20024 /* DRCB_INIT_SEQUENCE_REGISTER */ "", 20025 /* DRCB_INTERRUPT_MASK_REGISTER */ "", 20026 /* DRCB_INTERRUPT_REGISTER */ "", 20027 /* DRCB_INTERRUPT_REGISTER_TEST */ "", 20028 /* DRCB_INTIAL_CALIB_USE_MPR */ "", 20029 /* DRCB_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 20030 /* DRCB_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 20031 /* DRCB_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 20032 /* DRCB_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 20033 /* DRCB_LOOPBACK_CONFIG */ "", 20034 /* DRCB_LOOPBACK_CONTROL */ "", 20035 /* DRCB_LOOPBACK_DBI_ERROR_OCCURRED */ "", 20036 /* DRCB_LOOPBACK_DBI_FULL_ERR_CNT */ "", 20037 /* DRCB_LOOPBACK_DBI_MASK_WORD */ "", 20038 /* DRCB_LOOPBACK_DBI_PATTERN_WORD */ "", 20039 /* DRCB_LOOPBACK_ERROR_OCCURRED */ "", 20040 /* DRCB_LOOPBACK_FULL_ERR_CNT */ "", 20041 /* DRCB_LOOPBACK_MASK_WORD */ "", 20042 /* DRCB_LOOPBACK_PATTERN_WORD */ "", 20043 /* DRCB_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 20044 /* DRCB_LOOPBACK_PRBS_DATA_SEED */ "", 20045 /* DRCB_LOOPBACK_PRBS_DBI_SEED */ "", 20046 /* DRCB_ODT_CONFIGURATION_REGISTER */ "", 20047 /* DRCB_PARITY_ERR_CNT */ "", 20048 /* DRCB_PAR_ERR_INITIATE */ "", 20049 /* DRCB_PAR_ERR_MEM_MASK */ "", 20050 /* DRCB_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 20051 /* DRCB_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 20052 /* DRCB_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 20053 /* DRCB_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 20054 /* DRCB_PHY_CALIBRATION */ "", 20055 /* DRCB_PHY_CALIBRATION_CFG */ "", 20056 /* DRCB_PHY_CALIBRATION_CTRL */ "", 20057 /* DRCB_PHY_CALIBRATION_RES_FIFO_CFG */ "", 20058 /* DRCB_PHY_CALIB_FINISHED */ "", 20059 /* DRCB_PPR_ACTIVE */ "", 20060 /* DRCB_PPR_CFG */ "", 20061 /* DRCB_PWD_CLOCK_CONTROL */ "", 20062 /* DRCB_RBUS_ADDR */ "", 20063 /* DRCB_RBUS_RDATA */ "", 20064 /* DRCB_RBUS_RD_RESULT */ "", 20065 /* DRCB_RBUS_WDATA */ "", 20066 /* DRCB_REGISTER_ACCESS_RD_DATA_VALID */ "", 20067 /* DRCB_REGISTER_CONTROL */ "", 20068 /* DRCB_REGISTER_CONTROL_RDATA */ "", 20069 /* DRCB_REGISTER_CONTROL_WDATA */ "", 20070 /* DRCB_REG_0085 */ "", 20071 /* DRCB_REG_0087 */ "", 20072 /* DRCB_REG_90 */ "", 20073 /* DRCB_REG_0091 */ "", 20074 /* DRCB_REG_0092 */ "", 20075 /* DRCB_REG_0093 */ "", 20076 /* DRCB_REG_0209 */ "", 20077 /* DRCB_REG_0210 */ "", 20078 /* DRCB_REG_0211 */ "", 20079 /* DRCB_REG_0212 */ "", 20080 /* DRCB_REG_0242 */ "", 20081 /* DRCB_REG_0243 */ "", 20082 /* DRCB_REG_00AF */ "", 20083 /* DRCB_REG_00B0 */ "", 20084 /* DRCB_REG_00B1 */ "", 20085 /* DRCB_REG_00B2 */ "", 20086 /* DRCB_REG_00B3 */ "", 20087 /* DRCB_REG_00B4 */ "", 20088 /* DRCB_REG_00B5 */ "", 20089 /* DRCB_REG_00B6 */ "", 20090 /* DRCB_REG_00B7 */ "", 20091 /* DRCB_REG_00B8 */ "", 20092 /* DRCB_REG_00B9 */ "", 20093 /* DRCB_REG_00BA */ "", 20094 /* DRCB_REG_00BB */ "", 20095 /* DRCB_REG_00BC */ "", 20096 /* DRCB_REG_00BD */ "", 20097 /* DRCB_REG_00BE */ "", 20098 /* DRCB_REG_00BF */ "", 20099 /* DRCB_REG_00C0 */ "", 20100 /* DRCB_REG_00C1 */ "", 20101 /* DRCB_REG_00C2 */ "", 20102 /* DRCB_REG_00C3 */ "", 20103 /* DRCB_REG_020A */ "", 20104 /* DRCB_REG_020B */ "", 20105 /* DRCB_REG_020C */ "", 20106 /* DRCB_REG_020D */ "", 20107 /* DRCB_REG_020E */ "", 20108 /* DRCB_REG_020F */ "", 20109 /* DRCB_REG_021C */ "", 20110 /* DRCB_REG_0B0 */ "", 20111 /* DRCB_RESERVED_MIRROR_ADDR */ "", 20112 /* DRCB_RESERVED_MTCD */ "", 20113 /* DRCB_RESERVED_MTCP */ "", 20114 /* DRCB_RESERVED_SPARE_0 */ "", 20115 /* DRCB_RESERVED_SPARE_1 */ "", 20116 /* DRCB_RESERVED_SPARE_2 */ "", 20117 /* DRCB_RESERVED_SPARE_3 */ "", 20118 /* DRCB_RETRANSMIT_STATUS */ "", 20119 /* DRCB_RXI_WATERMARK */ "", 20120 /* DRCB_SBUS_BROADCAST_ID */ "", 20121 /* DRCB_SBUS_LAST_IN_CHAIN */ "", 20122 /* DRCB_SHADOW_DRAM_MR_0 */ "", 20123 /* DRCB_SHADOW_DRAM_MR_1 */ "", 20124 /* DRCB_SHADOW_DRAM_MR_2 */ "", 20125 /* DRCB_SHADOW_DRAM_MR_3 */ "", 20126 /* DRCB_SHADOW_DRAM_MR_4 */ "", 20127 /* DRCB_SHADOW_DRAM_MR_5 */ "", 20128 /* DRCB_SHADOW_DRAM_MR_6 */ "", 20129 /* DRCB_SHADOW_DRAM_MR_7 */ "", 20130 /* DRCB_SHADOW_DRAM_MR_8 */ "", 20131 /* DRCB_SHADOW_DRAM_MR_12 */ "", 20132 /* DRCB_SHADOW_DRAM_MR_14 */ "", 20133 /* DRCB_SHADOW_DRAM_MR_15 */ "", 20134 /* DRCB_SPARE_REGISTER */ "", 20135 /* DRCB_SPARE_REGISTER_3 */ "", 20136 /* DRCB_TRAIN_INIT_TRIGERS */ "", 20137 /* DRCB_VDL_CNTRL */ "", 20138 /* DRCB_WRITE_READ_RATES */ "", 20139 /* DRCB_WR_CRC_WATERMARK */ "", 20140 /* DRCC_AC_OPERATING_CONDITIONS_1 */ "", 20141 /* DRCC_AC_OPERATING_CONDITIONS_2 */ "", 20142 /* DRCC_AC_OPERATING_CONDITIONS_3 */ "", 20143 /* DRCC_AC_OPERATING_CONDITIONS_4 */ "", 20144 /* DRCC_AC_OPERATING_CONDITIONS_5 */ "", 20145 /* DRCC_ADDR_BANK_MAP */ "", 20146 /* DRCC_ADDR_WITH_RD_CRC */ "", 20147 /* DRCC_ADDR_WITH_WR_CRC */ "", 20148 /* DRCC_ALIGN_ERR_INDICATION */ "", 20149 /* DRCC_ASYNC_FIFO_CFG */ "", 20150 /* DRCC_AUXS_MUX */ "", 20151 /* DRCC_BIST_CONFIGURATIONS */ "", 20152 /* DRCC_BIST_DBI_ERR_OCCURED */ "", 20153 /* DRCC_BIST_EDC_ERR_OCCURED */ "", 20154 /* DRCC_BIST_END_ADDRESS */ "", 20155 /* DRCC_BIST_ERROR_OCCURRED */ "", 20156 /* DRCC_BIST_FULL_MASK_ERROR_COUNTER */ "", 20157 /* DRCC_BIST_FULL_MASK_WORD_0 */ "", 20158 /* DRCC_BIST_FULL_MASK_WORD_1 */ "", 20159 /* DRCC_BIST_FULL_MASK_WORD_2 */ "", 20160 /* DRCC_BIST_FULL_MASK_WORD_3 */ "", 20161 /* DRCC_BIST_FULL_MASK_WORD_4 */ "", 20162 /* DRCC_BIST_FULL_MASK_WORD_5 */ "", 20163 /* DRCC_BIST_FULL_MASK_WORD_6 */ "", 20164 /* DRCC_BIST_FULL_MASK_WORD_7 */ "", 20165 /* DRCC_BIST_GLOBAL_ERROR_COUNTER */ "", 20166 /* DRCC_BIST_LAST_ADDR_ERR */ "", 20167 /* DRCC_BIST_LAST_DATA_ERR */ "", 20168 /* DRCC_BIST_LAST_DATA_ERR_LSB */ "", 20169 /* DRCC_BIST_LAST_DATA_ERR_MSB */ "", 20170 /* DRCC_BIST_LAST_READ_DATA_LSB */ "", 20171 /* DRCC_BIST_LAST_READ_DATA_MSB */ "", 20172 /* DRCC_BIST_MPR_STAGGER_PATTERNS */ "", 20173 /* DRCC_BIST_MPR_STAGGER_WEIGHTS */ "", 20174 /* DRCC_BIST_NUMBER_OF_ACTIONS */ "", 20175 /* DRCC_BIST_PATTERN_REPETITION */ "", 20176 /* DRCC_BIST_PATTERN_WORD_0 */ "", 20177 /* DRCC_BIST_PATTERN_WORD_1 */ "", 20178 /* DRCC_BIST_PATTERN_WORD_2 */ "", 20179 /* DRCC_BIST_PATTERN_WORD_3 */ "", 20180 /* DRCC_BIST_PATTERN_WORD_4 */ "", 20181 /* DRCC_BIST_PATTERN_WORD_5 */ "", 20182 /* DRCC_BIST_PATTERN_WORD_6 */ "", 20183 /* DRCC_BIST_PATTERN_WORD_7 */ "", 20184 /* DRCC_BIST_PRBS_ADDR_SEED */ "", 20185 /* DRCC_BIST_PRBS_DATA_SEED_LSB */ "", 20186 /* DRCC_BIST_PRBS_DATA_SEED_MSB */ "", 20187 /* DRCC_BIST_RATE_LIMITER */ "", 20188 /* DRCC_BIST_REPEAT_PATTERN_1_LSB */ "", 20189 /* DRCC_BIST_REPEAT_PATTERN_1_MSB */ "", 20190 /* DRCC_BIST_REPEAT_PATTERN_2_LSB */ "", 20191 /* DRCC_BIST_REPEAT_PATTERN_2_MSB */ "", 20192 /* DRCC_BIST_REPEAT_PATTERN_3_LSB */ "", 20193 /* DRCC_BIST_REPEAT_PATTERN_3_MSB */ "", 20194 /* DRCC_BIST_REPEAT_PATTERN_4_LSB */ "", 20195 /* DRCC_BIST_REPEAT_PATTERN_4_MSB */ "", 20196 /* DRCC_BIST_REPEAT_PATTERN_5_LSB */ "", 20197 /* DRCC_BIST_REPEAT_PATTERN_5_MSB */ "", 20198 /* DRCC_BIST_REPEAT_PATTERN_6_LSB */ "", 20199 /* DRCC_BIST_REPEAT_PATTERN_6_MSB */ "", 20200 /* DRCC_BIST_REPEAT_PATTERN_7_LSB */ "", 20201 /* DRCC_BIST_REPEAT_PATTERN_7_MSB */ "", 20202 /* DRCC_BIST_SINGLE_BIT_MASK */ "", 20203 /* DRCC_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 20204 /* DRCC_BIST_START_ADDRESS */ "", 20205 /* DRCC_BIST_STATUSES */ "", 20206 /* DRCC_CALIBRATION_SEQUENCE_ADDRESS */ "", 20207 /* DRCC_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 20208 /* DRCC_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 20209 /* DRCC_CALIB_BIST_ERROR_OCCURRED */ "", 20210 /* DRCC_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 20211 /* DRCC_CLAM_SHELL */ "", 20212 /* DRCC_CNT_BIST_DBI_ERR_GLOBAL */ "", 20213 /* DRCC_CNT_BIST_EDC_ERR_GLOBAL */ "", 20214 /* DRCC_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 20215 /* DRCC_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 20216 /* DRCC_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 20217 /* DRCC_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 20218 /* DRCC_CPU_COMMANDS */ "", 20219 /* DRCC_DATA_LOCK */ "", 20220 /* DRCC_DATA_LOCK_TIMEOUT_PRD */ "", 20221 /* DRCC_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 20222 /* DRCC_DDR_CONTROLLER_TRIGGERS */ "", 20223 /* DRCC_DDR_EXTENDED_MODE_REGISTER_1 */ "", 20224 /* DRCC_DDR_EXTENDED_MODE_REGISTER_2 */ "", 20225 /* DRCC_DDR_EXTENDED_MODE_REGISTER_3 */ "", 20226 /* DRCC_DDR_MODE_REGISTER_1 */ "", 20227 /* DRCC_DDR_MODE_REGISTER_2 */ "", 20228 /* DRCC_DDR_PHY_PLL_CTRL */ "", 20229 /* DRCC_DDR_PHY_PLL_FREQ_CTRL */ "", 20230 /* DRCC_DDR_PHY_PLL_RC */ "", 20231 /* DRCC_DDR_PHY_PLL_RESET */ "", 20232 /* DRCC_DDR_PHY_PLL_STATUS */ "", 20233 /* DRCC_DDR_PHY_UPDATE_ENABLE */ "", 20234 /* DRCC_DPI_POWER */ "", 20235 /* DRCC_DPI_STATUS */ "", 20236 /* DRCC_DPI_STAT_CNTRL */ "", 20237 /* DRCC_DPRC_ENABLERS */ "", 20238 /* DRCC_DQ_BYTE_0_MAP */ "", 20239 /* DRCC_DQ_BYTE_1_MAP */ "", 20240 /* DRCC_DQ_BYTE_2_MAP */ "", 20241 /* DRCC_DQ_BYTE_3_MAP */ "", 20242 /* DRCC_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 20243 /* DRCC_DRAM_ERROR_DETECT */ "", 20244 /* DRCC_DRAM_ERROR_INNITATE */ "", 20245 /* DRCC_DRAM_ERROR_RECOVERY */ "", 20246 /* DRCC_DRAM_INIT_FINISHED */ "", 20247 /* DRCC_DRAM_MR_0 */ "", 20248 /* DRCC_DRAM_MR_1 */ "", 20249 /* DRCC_DRAM_MR_2 */ "", 20250 /* DRCC_DRAM_MR_3 */ "", 20251 /* DRCC_DRAM_MR_4 */ "", 20252 /* DRCC_DRAM_MR_5 */ "", 20253 /* DRCC_DRAM_MR_6 */ "", 20254 /* DRCC_DRAM_MR_7 */ "", 20255 /* DRCC_DRAM_MR_8 */ "", 20256 /* DRCC_DRAM_MR_12 */ "", 20257 /* DRCC_DRAM_MR_14 */ "", 20258 /* DRCC_DRAM_MR_15 */ "", 20259 /* DRCC_DRAM_SET */ "", 20260 /* DRCC_DRAM_SPECIAL_FEATURES */ "", 20261 /* DRCC_DRAM_TIME_PARAMS */ "", 20262 /* DRCC_DWF_WATERMARK */ "", 20263 /* DRCC_ECC_1B_ERR_CNT */ "", 20264 /* DRCC_ECC_2B_ERR_CNT */ "", 20265 /* DRCC_ECC_ERR_1B_INITIATE */ "", 20266 /* DRCC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 20267 /* DRCC_ECC_ERR_2B_INITIATE */ "", 20268 /* DRCC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 20269 /* DRCC_ECC_INTERRUPT_REGISTER */ "", 20270 /* DRCC_ECC_INTERRUPT_REGISTER_MASK */ "", 20271 /* DRCC_ECC_INTERRUPT_REGISTER_TEST */ "", 20272 /* DRCC_ERROR_INITIATION_DATA */ "", 20273 /* DRCC_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 20274 /* DRCC_EXTENDED_MODE_WR_2_REGISTER */ "", 20275 /* DRCC_EXT_PHY_CTRL_STATUS */ "", 20276 /* DRCC_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 20277 /* DRCC_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 20278 /* DRCC_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 20279 /* DRCC_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 20280 /* DRCC_GDDR_5_BIST_CONFIGURATIONS */ "", 20281 /* DRCC_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 20282 /* DRCC_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 20283 /* DRCC_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 20284 /* DRCC_GDDR_5_BIST_FINISH_PRD */ "", 20285 /* DRCC_GDDR_5_BIST_PRBS_ADT_SEED */ "", 20286 /* DRCC_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 20287 /* DRCC_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 20288 /* DRCC_GDDR_5_BIST_PRBS_DBI_SEED */ "", 20289 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 20290 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 20291 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 20292 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 20293 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 20294 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 20295 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 20296 /* DRCC_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 20297 /* DRCC_GDDR_5_BIST_STATUSES */ "", 20298 /* DRCC_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 20299 /* DRCC_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 20300 /* DRCC_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 20301 /* DRCC_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 20302 /* DRCC_GDDR_5_SPECIAL_CMD_TIMING */ "", 20303 /* DRCC_GDDR_BIST_LAST_READ_DATA_LSB */ "", 20304 /* DRCC_GDDR_BIST_LAST_READ_DATA_MSB */ "", 20305 /* DRCC_GENERAL_CONFIGURATIONS */ "", 20306 /* DRCC_GLOBALF */ "", 20307 /* DRCC_GLOBAL_MEM_OPTIONS */ "", 20308 /* DRCC_GLUE_LOGIC_REGISTER */ "", 20309 /* DRCC_GTIMER_CONFIGURATION */ "", 20310 /* DRCC_GTIMER_TRIGGER */ "", 20311 /* DRCC_INITIALIZATION_CONTROLL */ "", 20312 /* DRCC_INIT_SEQUENCE_REGISTER */ "", 20313 /* DRCC_INTERRUPT_MASK_REGISTER */ "", 20314 /* DRCC_INTERRUPT_REGISTER */ "", 20315 /* DRCC_INTERRUPT_REGISTER_TEST */ "", 20316 /* DRCC_INTIAL_CALIB_USE_MPR */ "", 20317 /* DRCC_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 20318 /* DRCC_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 20319 /* DRCC_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 20320 /* DRCC_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 20321 /* DRCC_LOOPBACK_CONFIG */ "", 20322 /* DRCC_LOOPBACK_CONTROL */ "", 20323 /* DRCC_LOOPBACK_DBI_ERROR_OCCURRED */ "", 20324 /* DRCC_LOOPBACK_DBI_FULL_ERR_CNT */ "", 20325 /* DRCC_LOOPBACK_DBI_MASK_WORD */ "", 20326 /* DRCC_LOOPBACK_DBI_PATTERN_WORD */ "", 20327 /* DRCC_LOOPBACK_ERROR_OCCURRED */ "", 20328 /* DRCC_LOOPBACK_FULL_ERR_CNT */ "", 20329 /* DRCC_LOOPBACK_MASK_WORD */ "", 20330 /* DRCC_LOOPBACK_PATTERN_WORD */ "", 20331 /* DRCC_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 20332 /* DRCC_LOOPBACK_PRBS_DATA_SEED */ "", 20333 /* DRCC_LOOPBACK_PRBS_DBI_SEED */ "", 20334 /* DRCC_ODT_CONFIGURATION_REGISTER */ "", 20335 /* DRCC_PARITY_ERR_CNT */ "", 20336 /* DRCC_PAR_ERR_INITIATE */ "", 20337 /* DRCC_PAR_ERR_MEM_MASK */ "", 20338 /* DRCC_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 20339 /* DRCC_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 20340 /* DRCC_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 20341 /* DRCC_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 20342 /* DRCC_PHY_CALIBRATION */ "", 20343 /* DRCC_PHY_CALIBRATION_CFG */ "", 20344 /* DRCC_PHY_CALIBRATION_CTRL */ "", 20345 /* DRCC_PHY_CALIBRATION_RES_FIFO_CFG */ "", 20346 /* DRCC_PHY_CALIB_FINISHED */ "", 20347 /* DRCC_PPR_ACTIVE */ "", 20348 /* DRCC_PPR_CFG */ "", 20349 /* DRCC_PWD_CLOCK_CONTROL */ "", 20350 /* DRCC_RBUS_ADDR */ "", 20351 /* DRCC_RBUS_RDATA */ "", 20352 /* DRCC_RBUS_RD_RESULT */ "", 20353 /* DRCC_RBUS_WDATA */ "", 20354 /* DRCC_REGISTER_ACCESS_RD_DATA_VALID */ "", 20355 /* DRCC_REGISTER_CONTROL */ "", 20356 /* DRCC_REGISTER_CONTROL_RDATA */ "", 20357 /* DRCC_REGISTER_CONTROL_WDATA */ "", 20358 /* DRCC_REG_0085 */ "", 20359 /* DRCC_REG_0087 */ "", 20360 /* DRCC_REG_90 */ "", 20361 /* DRCC_REG_0091 */ "", 20362 /* DRCC_REG_0092 */ "", 20363 /* DRCC_REG_0093 */ "", 20364 /* DRCC_REG_0209 */ "", 20365 /* DRCC_REG_0210 */ "", 20366 /* DRCC_REG_0211 */ "", 20367 /* DRCC_REG_0212 */ "", 20368 /* DRCC_REG_0242 */ "", 20369 /* DRCC_REG_0243 */ "", 20370 /* DRCC_REG_00AF */ "", 20371 /* DRCC_REG_00B0 */ "", 20372 /* DRCC_REG_00B1 */ "", 20373 /* DRCC_REG_00B2 */ "", 20374 /* DRCC_REG_00B3 */ "", 20375 /* DRCC_REG_00B4 */ "", 20376 /* DRCC_REG_00B5 */ "", 20377 /* DRCC_REG_00B6 */ "", 20378 /* DRCC_REG_00B7 */ "", 20379 /* DRCC_REG_00B8 */ "", 20380 /* DRCC_REG_00B9 */ "", 20381 /* DRCC_REG_00BA */ "", 20382 /* DRCC_REG_00BB */ "", 20383 /* DRCC_REG_00BC */ "", 20384 /* DRCC_REG_00BD */ "", 20385 /* DRCC_REG_00BE */ "", 20386 /* DRCC_REG_00BF */ "", 20387 /* DRCC_REG_00C0 */ "", 20388 /* DRCC_REG_00C1 */ "", 20389 /* DRCC_REG_00C2 */ "", 20390 /* DRCC_REG_00C3 */ "", 20391 /* DRCC_REG_020A */ "", 20392 /* DRCC_REG_020B */ "", 20393 /* DRCC_REG_020C */ "", 20394 /* DRCC_REG_020D */ "", 20395 /* DRCC_REG_020E */ "", 20396 /* DRCC_REG_020F */ "", 20397 /* DRCC_REG_021C */ "", 20398 /* DRCC_REG_0B0 */ "", 20399 /* DRCC_RESERVED_MIRROR_ADDR */ "", 20400 /* DRCC_RESERVED_MTCD */ "", 20401 /* DRCC_RESERVED_MTCP */ "", 20402 /* DRCC_RESERVED_SPARE_0 */ "", 20403 /* DRCC_RESERVED_SPARE_1 */ "", 20404 /* DRCC_RESERVED_SPARE_2 */ "", 20405 /* DRCC_RESERVED_SPARE_3 */ "", 20406 /* DRCC_RETRANSMIT_STATUS */ "", 20407 /* DRCC_RXI_WATERMARK */ "", 20408 /* DRCC_SBUS_BROADCAST_ID */ "", 20409 /* DRCC_SBUS_LAST_IN_CHAIN */ "", 20410 /* DRCC_SHADOW_DRAM_MR_0 */ "", 20411 /* DRCC_SHADOW_DRAM_MR_1 */ "", 20412 /* DRCC_SHADOW_DRAM_MR_2 */ "", 20413 /* DRCC_SHADOW_DRAM_MR_3 */ "", 20414 /* DRCC_SHADOW_DRAM_MR_4 */ "", 20415 /* DRCC_SHADOW_DRAM_MR_5 */ "", 20416 /* DRCC_SHADOW_DRAM_MR_6 */ "", 20417 /* DRCC_SHADOW_DRAM_MR_7 */ "", 20418 /* DRCC_SHADOW_DRAM_MR_8 */ "", 20419 /* DRCC_SHADOW_DRAM_MR_12 */ "", 20420 /* DRCC_SHADOW_DRAM_MR_14 */ "", 20421 /* DRCC_SHADOW_DRAM_MR_15 */ "", 20422 /* DRCC_SPARE_REGISTER */ "", 20423 /* DRCC_SPARE_REGISTER_3 */ "", 20424 /* DRCC_TRAIN_INIT_TRIGERS */ "", 20425 /* DRCC_VDL_CNTRL */ "", 20426 /* DRCC_WRITE_READ_RATES */ "", 20427 /* DRCC_WR_CRC_WATERMARK */ "", 20428 /* DRCD_AC_OPERATING_CONDITIONS_1 */ "", 20429 /* DRCD_AC_OPERATING_CONDITIONS_2 */ "", 20430 /* DRCD_AC_OPERATING_CONDITIONS_3 */ "", 20431 /* DRCD_AC_OPERATING_CONDITIONS_4 */ "", 20432 /* DRCD_AC_OPERATING_CONDITIONS_5 */ "", 20433 /* DRCD_ADDR_BANK_MAP */ "", 20434 /* DRCD_ADDR_WITH_RD_CRC */ "", 20435 /* DRCD_ADDR_WITH_WR_CRC */ "", 20436 /* DRCD_ALIGN_ERR_INDICATION */ "", 20437 /* DRCD_AUXS_MUX */ "", 20438 /* DRCD_BIST_CONFIGURATIONS */ "", 20439 /* DRCD_BIST_DBI_ERR_OCCURED */ "", 20440 /* DRCD_BIST_EDC_ERR_OCCURED */ "", 20441 /* DRCD_BIST_END_ADDRESS */ "", 20442 /* DRCD_BIST_ERROR_OCCURRED */ "", 20443 /* DRCD_BIST_FULL_MASK_ERROR_COUNTER */ "", 20444 /* DRCD_BIST_FULL_MASK_WORD_0 */ "", 20445 /* DRCD_BIST_FULL_MASK_WORD_1 */ "", 20446 /* DRCD_BIST_FULL_MASK_WORD_2 */ "", 20447 /* DRCD_BIST_FULL_MASK_WORD_3 */ "", 20448 /* DRCD_BIST_FULL_MASK_WORD_4 */ "", 20449 /* DRCD_BIST_FULL_MASK_WORD_5 */ "", 20450 /* DRCD_BIST_FULL_MASK_WORD_6 */ "", 20451 /* DRCD_BIST_FULL_MASK_WORD_7 */ "", 20452 /* DRCD_BIST_GLOBAL_ERROR_COUNTER */ "", 20453 /* DRCD_BIST_LAST_ADDR_ERR */ "", 20454 /* DRCD_BIST_LAST_DATA_ERR */ "", 20455 /* DRCD_BIST_LAST_DATA_ERR_LSB */ "", 20456 /* DRCD_BIST_LAST_DATA_ERR_MSB */ "", 20457 /* DRCD_BIST_LAST_READ_DATA_LSB */ "", 20458 /* DRCD_BIST_LAST_READ_DATA_MSB */ "", 20459 /* DRCD_BIST_MPR_STAGGER_PATTERNS */ "", 20460 /* DRCD_BIST_MPR_STAGGER_WEIGHTS */ "", 20461 /* DRCD_BIST_NUMBER_OF_ACTIONS */ "", 20462 /* DRCD_BIST_PATTERN_REPETITION */ "", 20463 /* DRCD_BIST_PATTERN_WORD_0 */ "", 20464 /* DRCD_BIST_PATTERN_WORD_1 */ "", 20465 /* DRCD_BIST_PATTERN_WORD_2 */ "", 20466 /* DRCD_BIST_PATTERN_WORD_3 */ "", 20467 /* DRCD_BIST_PATTERN_WORD_4 */ "", 20468 /* DRCD_BIST_PATTERN_WORD_5 */ "", 20469 /* DRCD_BIST_PATTERN_WORD_6 */ "", 20470 /* DRCD_BIST_PATTERN_WORD_7 */ "", 20471 /* DRCD_BIST_PRBS_ADDR_SEED */ "", 20472 /* DRCD_BIST_PRBS_DATA_SEED_LSB */ "", 20473 /* DRCD_BIST_PRBS_DATA_SEED_MSB */ "", 20474 /* DRCD_BIST_RATE_LIMITER */ "", 20475 /* DRCD_BIST_REPEAT_PATTERN_1_LSB */ "", 20476 /* DRCD_BIST_REPEAT_PATTERN_1_MSB */ "", 20477 /* DRCD_BIST_REPEAT_PATTERN_2_LSB */ "", 20478 /* DRCD_BIST_REPEAT_PATTERN_2_MSB */ "", 20479 /* DRCD_BIST_REPEAT_PATTERN_3_LSB */ "", 20480 /* DRCD_BIST_REPEAT_PATTERN_3_MSB */ "", 20481 /* DRCD_BIST_REPEAT_PATTERN_4_LSB */ "", 20482 /* DRCD_BIST_REPEAT_PATTERN_4_MSB */ "", 20483 /* DRCD_BIST_REPEAT_PATTERN_5_LSB */ "", 20484 /* DRCD_BIST_REPEAT_PATTERN_5_MSB */ "", 20485 /* DRCD_BIST_REPEAT_PATTERN_6_LSB */ "", 20486 /* DRCD_BIST_REPEAT_PATTERN_6_MSB */ "", 20487 /* DRCD_BIST_REPEAT_PATTERN_7_LSB */ "", 20488 /* DRCD_BIST_REPEAT_PATTERN_7_MSB */ "", 20489 /* DRCD_BIST_SINGLE_BIT_MASK */ "", 20490 /* DRCD_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 20491 /* DRCD_BIST_START_ADDRESS */ "", 20492 /* DRCD_BIST_STATUSES */ "", 20493 /* DRCD_CALIBRATION_SEQUENCE_ADDRESS */ "", 20494 /* DRCD_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 20495 /* DRCD_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 20496 /* DRCD_CALIB_BIST_ERROR_OCCURRED */ "", 20497 /* DRCD_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 20498 /* DRCD_CLAM_SHELL */ "", 20499 /* DRCD_CNT_BIST_DBI_ERR_GLOBAL */ "", 20500 /* DRCD_CNT_BIST_EDC_ERR_GLOBAL */ "", 20501 /* DRCD_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 20502 /* DRCD_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 20503 /* DRCD_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 20504 /* DRCD_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 20505 /* DRCD_CPU_COMMANDS */ "", 20506 /* DRCD_DATA_LOCK */ "", 20507 /* DRCD_DATA_LOCK_TIMEOUT_PRD */ "", 20508 /* DRCD_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 20509 /* DRCD_DDR_CONTROLLER_TRIGGERS */ "", 20510 /* DRCD_DDR_EXTENDED_MODE_REGISTER_1 */ "", 20511 /* DRCD_DDR_EXTENDED_MODE_REGISTER_2 */ "", 20512 /* DRCD_DDR_EXTENDED_MODE_REGISTER_3 */ "", 20513 /* DRCD_DDR_MODE_REGISTER_1 */ "", 20514 /* DRCD_DDR_MODE_REGISTER_2 */ "", 20515 /* DRCD_DDR_PHY_PLL_CTRL */ "", 20516 /* DRCD_DDR_PHY_PLL_FREQ_CTRL */ "", 20517 /* DRCD_DDR_PHY_PLL_RC */ "", 20518 /* DRCD_DDR_PHY_PLL_RESET */ "", 20519 /* DRCD_DDR_PHY_PLL_STATUS */ "", 20520 /* DRCD_DDR_PHY_UPDATE_ENABLE */ "", 20521 /* DRCD_DPI_POWER */ "", 20522 /* DRCD_DPI_STATUS */ "", 20523 /* DRCD_DPI_STAT_CNTRL */ "", 20524 /* DRCD_DPRC_ENABLERS */ "", 20525 /* DRCD_DQ_BYTE_0_MAP */ "", 20526 /* DRCD_DQ_BYTE_1_MAP */ "", 20527 /* DRCD_DQ_BYTE_2_MAP */ "", 20528 /* DRCD_DQ_BYTE_3_MAP */ "", 20529 /* DRCD_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 20530 /* DRCD_DRAM_ERROR_DETECT */ "", 20531 /* DRCD_DRAM_ERROR_INNITATE */ "", 20532 /* DRCD_DRAM_ERROR_RECOVERY */ "", 20533 /* DRCD_DRAM_INIT_FINISHED */ "", 20534 /* DRCD_DRAM_MR_0 */ "", 20535 /* DRCD_DRAM_MR_1 */ "", 20536 /* DRCD_DRAM_MR_2 */ "", 20537 /* DRCD_DRAM_MR_3 */ "", 20538 /* DRCD_DRAM_MR_4 */ "", 20539 /* DRCD_DRAM_MR_5 */ "", 20540 /* DRCD_DRAM_MR_6 */ "", 20541 /* DRCD_DRAM_MR_7 */ "", 20542 /* DRCD_DRAM_MR_8 */ "", 20543 /* DRCD_DRAM_MR_12 */ "", 20544 /* DRCD_DRAM_MR_14 */ "", 20545 /* DRCD_DRAM_MR_15 */ "", 20546 /* DRCD_DRAM_SET */ "", 20547 /* DRCD_DRAM_SPECIAL_FEATURES */ "", 20548 /* DRCD_DRAM_TIME_PARAMS */ "", 20549 /* DRCD_DWF_WATERMARK */ "", 20550 /* DRCD_ECC_1B_ERR_CNT */ "", 20551 /* DRCD_ECC_2B_ERR_CNT */ "", 20552 /* DRCD_ECC_ERR_1B_INITIATE */ "", 20553 /* DRCD_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 20554 /* DRCD_ECC_ERR_2B_INITIATE */ "", 20555 /* DRCD_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 20556 /* DRCD_ECC_INTERRUPT_REGISTER */ "", 20557 /* DRCD_ECC_INTERRUPT_REGISTER_MASK */ "", 20558 /* DRCD_ECC_INTERRUPT_REGISTER_TEST */ "", 20559 /* DRCD_ERROR_INITIATION_DATA */ "", 20560 /* DRCD_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 20561 /* DRCD_EXTENDED_MODE_WR_2_REGISTER */ "", 20562 /* DRCD_EXT_PHY_CTRL_STATUS */ "", 20563 /* DRCD_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 20564 /* DRCD_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 20565 /* DRCD_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 20566 /* DRCD_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 20567 /* DRCD_GDDR_5_BIST_CONFIGURATIONS */ "", 20568 /* DRCD_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 20569 /* DRCD_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 20570 /* DRCD_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 20571 /* DRCD_GDDR_5_BIST_FINISH_PRD */ "", 20572 /* DRCD_GDDR_5_BIST_PRBS_ADT_SEED */ "", 20573 /* DRCD_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 20574 /* DRCD_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 20575 /* DRCD_GDDR_5_BIST_PRBS_DBI_SEED */ "", 20576 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 20577 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 20578 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 20579 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 20580 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 20581 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 20582 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 20583 /* DRCD_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 20584 /* DRCD_GDDR_5_BIST_STATUSES */ "", 20585 /* DRCD_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 20586 /* DRCD_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 20587 /* DRCD_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 20588 /* DRCD_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 20589 /* DRCD_GDDR_5_SPECIAL_CMD_TIMING */ "", 20590 /* DRCD_GDDR_BIST_LAST_READ_DATA_LSB */ "", 20591 /* DRCD_GDDR_BIST_LAST_READ_DATA_MSB */ "", 20592 /* DRCD_GENERAL_CONFIGURATIONS */ "", 20593 /* DRCD_GLOBALF */ "", 20594 /* DRCD_GLOBAL_MEM_OPTIONS */ "", 20595 /* DRCD_GLUE_LOGIC_REGISTER */ "", 20596 /* DRCD_GTIMER_CONFIGURATION */ "", 20597 /* DRCD_GTIMER_TRIGGER */ "", 20598 /* DRCD_INITIALIZATION_CONTROLL */ "", 20599 /* DRCD_INIT_SEQUENCE_REGISTER */ "", 20600 /* DRCD_INTERRUPT_MASK_REGISTER */ "", 20601 /* DRCD_INTERRUPT_REGISTER */ "", 20602 /* DRCD_INTERRUPT_REGISTER_TEST */ "", 20603 /* DRCD_INTIAL_CALIB_USE_MPR */ "", 20604 /* DRCD_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 20605 /* DRCD_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 20606 /* DRCD_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 20607 /* DRCD_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 20608 /* DRCD_LOOPBACK_CONFIG */ "", 20609 /* DRCD_LOOPBACK_CONTROL */ "", 20610 /* DRCD_LOOPBACK_DBI_ERROR_OCCURRED */ "", 20611 /* DRCD_LOOPBACK_DBI_FULL_ERR_CNT */ "", 20612 /* DRCD_LOOPBACK_DBI_MASK_WORD */ "", 20613 /* DRCD_LOOPBACK_DBI_PATTERN_WORD */ "", 20614 /* DRCD_LOOPBACK_ERROR_OCCURRED */ "", 20615 /* DRCD_LOOPBACK_FULL_ERR_CNT */ "", 20616 /* DRCD_LOOPBACK_MASK_WORD */ "", 20617 /* DRCD_LOOPBACK_PATTERN_WORD */ "", 20618 /* DRCD_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 20619 /* DRCD_LOOPBACK_PRBS_DATA_SEED */ "", 20620 /* DRCD_LOOPBACK_PRBS_DBI_SEED */ "", 20621 /* DRCD_ODT_CONFIGURATION_REGISTER */ "", 20622 /* DRCD_PARITY_ERR_CNT */ "", 20623 /* DRCD_PAR_ERR_INITIATE */ "", 20624 /* DRCD_PAR_ERR_MEM_MASK */ "", 20625 /* DRCD_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 20626 /* DRCD_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 20627 /* DRCD_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 20628 /* DRCD_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 20629 /* DRCD_PHY_CALIBRATION */ "", 20630 /* DRCD_PHY_CALIBRATION_CFG */ "", 20631 /* DRCD_PHY_CALIBRATION_CTRL */ "", 20632 /* DRCD_PHY_CALIBRATION_RES_FIFO_CFG */ "", 20633 /* DRCD_PHY_CALIB_FINISHED */ "", 20634 /* DRCD_PPR_ACTIVE */ "", 20635 /* DRCD_PPR_CFG */ "", 20636 /* DRCD_PWD_CLOCK_CONTROL */ "", 20637 /* DRCD_RBUS_ADDR */ "", 20638 /* DRCD_RBUS_RDATA */ "", 20639 /* DRCD_RBUS_RD_RESULT */ "", 20640 /* DRCD_RBUS_WDATA */ "", 20641 /* DRCD_REGISTER_ACCESS_RD_DATA_VALID */ "", 20642 /* DRCD_REGISTER_CONTROL */ "", 20643 /* DRCD_REGISTER_CONTROL_RDATA */ "", 20644 /* DRCD_REGISTER_CONTROL_WDATA */ "", 20645 /* DRCD_REG_0085 */ "", 20646 /* DRCD_REG_0087 */ "", 20647 /* DRCD_REG_90 */ "", 20648 /* DRCD_REG_0091 */ "", 20649 /* DRCD_REG_0092 */ "", 20650 /* DRCD_REG_0093 */ "", 20651 /* DRCD_REG_0209 */ "", 20652 /* DRCD_REG_0210 */ "", 20653 /* DRCD_REG_0211 */ "", 20654 /* DRCD_REG_0212 */ "", 20655 /* DRCD_REG_0242 */ "", 20656 /* DRCD_REG_0243 */ "", 20657 /* DRCD_REG_00AF */ "", 20658 /* DRCD_REG_00B0 */ "", 20659 /* DRCD_REG_00B1 */ "", 20660 /* DRCD_REG_00B2 */ "", 20661 /* DRCD_REG_00B3 */ "", 20662 /* DRCD_REG_00B4 */ "", 20663 /* DRCD_REG_00B5 */ "", 20664 /* DRCD_REG_00B6 */ "", 20665 /* DRCD_REG_00B7 */ "", 20666 /* DRCD_REG_00B8 */ "", 20667 /* DRCD_REG_00B9 */ "", 20668 /* DRCD_REG_00BA */ "", 20669 /* DRCD_REG_00BB */ "", 20670 /* DRCD_REG_00BC */ "", 20671 /* DRCD_REG_00BD */ "", 20672 /* DRCD_REG_00BE */ "", 20673 /* DRCD_REG_00BF */ "", 20674 /* DRCD_REG_00C0 */ "", 20675 /* DRCD_REG_00C1 */ "", 20676 /* DRCD_REG_00C2 */ "", 20677 /* DRCD_REG_00C3 */ "", 20678 /* DRCD_REG_020A */ "", 20679 /* DRCD_REG_020B */ "", 20680 /* DRCD_REG_020C */ "", 20681 /* DRCD_REG_020D */ "", 20682 /* DRCD_REG_020E */ "", 20683 /* DRCD_REG_020F */ "", 20684 /* DRCD_REG_021C */ "", 20685 /* DRCD_REG_0B0 */ "", 20686 /* DRCD_RESERVED_MIRROR_ADDR */ "", 20687 /* DRCD_RESERVED_MTCD */ "", 20688 /* DRCD_RESERVED_MTCP */ "", 20689 /* DRCD_RESERVED_SPARE_0 */ "", 20690 /* DRCD_RESERVED_SPARE_1 */ "", 20691 /* DRCD_RESERVED_SPARE_2 */ "", 20692 /* DRCD_RESERVED_SPARE_3 */ "", 20693 /* DRCD_RETRANSMIT_STATUS */ "", 20694 /* DRCD_RXI_WATERMARK */ "", 20695 /* DRCD_SBUS_BROADCAST_ID */ "", 20696 /* DRCD_SBUS_LAST_IN_CHAIN */ "", 20697 /* DRCD_SHADOW_DRAM_MR_0 */ "", 20698 /* DRCD_SHADOW_DRAM_MR_1 */ "", 20699 /* DRCD_SHADOW_DRAM_MR_2 */ "", 20700 /* DRCD_SHADOW_DRAM_MR_3 */ "", 20701 /* DRCD_SHADOW_DRAM_MR_4 */ "", 20702 /* DRCD_SHADOW_DRAM_MR_5 */ "", 20703 /* DRCD_SHADOW_DRAM_MR_6 */ "", 20704 /* DRCD_SHADOW_DRAM_MR_7 */ "", 20705 /* DRCD_SHADOW_DRAM_MR_8 */ "", 20706 /* DRCD_SHADOW_DRAM_MR_12 */ "", 20707 /* DRCD_SHADOW_DRAM_MR_14 */ "", 20708 /* DRCD_SHADOW_DRAM_MR_15 */ "", 20709 /* DRCD_SPARE_REGISTER */ "", 20710 /* DRCD_SPARE_REGISTER_3 */ "", 20711 /* DRCD_TRAIN_INIT_TRIGERS */ "", 20712 /* DRCD_VDL_CNTRL */ "", 20713 /* DRCD_WRITE_READ_RATES */ "", 20714 /* DRCD_WR_CRC_WATERMARK */ "", 20715 /* DRCE_AC_OPERATING_CONDITIONS_1 */ "", 20716 /* DRCE_AC_OPERATING_CONDITIONS_2 */ "", 20717 /* DRCE_AC_OPERATING_CONDITIONS_3 */ "", 20718 /* DRCE_AC_OPERATING_CONDITIONS_4 */ "", 20719 /* DRCE_AC_OPERATING_CONDITIONS_5 */ "", 20720 /* DRCE_ADDR_BANK_MAP */ "", 20721 /* DRCE_ADDR_WITH_RD_CRC */ "", 20722 /* DRCE_ADDR_WITH_WR_CRC */ "", 20723 /* DRCE_ALIGN_ERR_INDICATION */ "", 20724 /* DRCE_AUXS_MUX */ "", 20725 /* DRCE_BIST_CONFIGURATIONS */ "", 20726 /* DRCE_BIST_DBI_ERR_OCCURED */ "", 20727 /* DRCE_BIST_EDC_ERR_OCCURED */ "", 20728 /* DRCE_BIST_END_ADDRESS */ "", 20729 /* DRCE_BIST_ERROR_OCCURRED */ "", 20730 /* DRCE_BIST_FULL_MASK_ERROR_COUNTER */ "", 20731 /* DRCE_BIST_FULL_MASK_WORD_0 */ "", 20732 /* DRCE_BIST_FULL_MASK_WORD_1 */ "", 20733 /* DRCE_BIST_FULL_MASK_WORD_2 */ "", 20734 /* DRCE_BIST_FULL_MASK_WORD_3 */ "", 20735 /* DRCE_BIST_FULL_MASK_WORD_4 */ "", 20736 /* DRCE_BIST_FULL_MASK_WORD_5 */ "", 20737 /* DRCE_BIST_FULL_MASK_WORD_6 */ "", 20738 /* DRCE_BIST_FULL_MASK_WORD_7 */ "", 20739 /* DRCE_BIST_GLOBAL_ERROR_COUNTER */ "", 20740 /* DRCE_BIST_LAST_ADDR_ERR */ "", 20741 /* DRCE_BIST_LAST_DATA_ERR */ "", 20742 /* DRCE_BIST_LAST_DATA_ERR_LSB */ "", 20743 /* DRCE_BIST_LAST_DATA_ERR_MSB */ "", 20744 /* DRCE_BIST_LAST_READ_DATA_LSB */ "", 20745 /* DRCE_BIST_LAST_READ_DATA_MSB */ "", 20746 /* DRCE_BIST_MPR_STAGGER_PATTERNS */ "", 20747 /* DRCE_BIST_MPR_STAGGER_WEIGHTS */ "", 20748 /* DRCE_BIST_NUMBER_OF_ACTIONS */ "", 20749 /* DRCE_BIST_PATTERN_REPETITION */ "", 20750 /* DRCE_BIST_PATTERN_WORD_0 */ "", 20751 /* DRCE_BIST_PATTERN_WORD_1 */ "", 20752 /* DRCE_BIST_PATTERN_WORD_2 */ "", 20753 /* DRCE_BIST_PATTERN_WORD_3 */ "", 20754 /* DRCE_BIST_PATTERN_WORD_4 */ "", 20755 /* DRCE_BIST_PATTERN_WORD_5 */ "", 20756 /* DRCE_BIST_PATTERN_WORD_6 */ "", 20757 /* DRCE_BIST_PATTERN_WORD_7 */ "", 20758 /* DRCE_BIST_PRBS_ADDR_SEED */ "", 20759 /* DRCE_BIST_PRBS_DATA_SEED_LSB */ "", 20760 /* DRCE_BIST_PRBS_DATA_SEED_MSB */ "", 20761 /* DRCE_BIST_RATE_LIMITER */ "", 20762 /* DRCE_BIST_REPEAT_PATTERN_1_LSB */ "", 20763 /* DRCE_BIST_REPEAT_PATTERN_1_MSB */ "", 20764 /* DRCE_BIST_REPEAT_PATTERN_2_LSB */ "", 20765 /* DRCE_BIST_REPEAT_PATTERN_2_MSB */ "", 20766 /* DRCE_BIST_REPEAT_PATTERN_3_LSB */ "", 20767 /* DRCE_BIST_REPEAT_PATTERN_3_MSB */ "", 20768 /* DRCE_BIST_REPEAT_PATTERN_4_LSB */ "", 20769 /* DRCE_BIST_REPEAT_PATTERN_4_MSB */ "", 20770 /* DRCE_BIST_REPEAT_PATTERN_5_LSB */ "", 20771 /* DRCE_BIST_REPEAT_PATTERN_5_MSB */ "", 20772 /* DRCE_BIST_REPEAT_PATTERN_6_LSB */ "", 20773 /* DRCE_BIST_REPEAT_PATTERN_6_MSB */ "", 20774 /* DRCE_BIST_REPEAT_PATTERN_7_LSB */ "", 20775 /* DRCE_BIST_REPEAT_PATTERN_7_MSB */ "", 20776 /* DRCE_BIST_SINGLE_BIT_MASK */ "", 20777 /* DRCE_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 20778 /* DRCE_BIST_START_ADDRESS */ "", 20779 /* DRCE_BIST_STATUSES */ "", 20780 /* DRCE_CALIBRATION_SEQUENCE_ADDRESS */ "", 20781 /* DRCE_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 20782 /* DRCE_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 20783 /* DRCE_CALIB_BIST_ERROR_OCCURRED */ "", 20784 /* DRCE_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 20785 /* DRCE_CLAM_SHELL */ "", 20786 /* DRCE_CNT_BIST_DBI_ERR_GLOBAL */ "", 20787 /* DRCE_CNT_BIST_EDC_ERR_GLOBAL */ "", 20788 /* DRCE_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 20789 /* DRCE_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 20790 /* DRCE_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 20791 /* DRCE_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 20792 /* DRCE_CPU_COMMANDS */ "", 20793 /* DRCE_DATA_LOCK */ "", 20794 /* DRCE_DATA_LOCK_TIMEOUT_PRD */ "", 20795 /* DRCE_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 20796 /* DRCE_DDR_CONTROLLER_TRIGGERS */ "", 20797 /* DRCE_DDR_EXTENDED_MODE_REGISTER_1 */ "", 20798 /* DRCE_DDR_EXTENDED_MODE_REGISTER_2 */ "", 20799 /* DRCE_DDR_EXTENDED_MODE_REGISTER_3 */ "", 20800 /* DRCE_DDR_MODE_REGISTER_1 */ "", 20801 /* DRCE_DDR_MODE_REGISTER_2 */ "", 20802 /* DRCE_DDR_PHY_PLL_CTRL */ "", 20803 /* DRCE_DDR_PHY_PLL_FREQ_CTRL */ "", 20804 /* DRCE_DDR_PHY_PLL_RC */ "", 20805 /* DRCE_DDR_PHY_PLL_RESET */ "", 20806 /* DRCE_DDR_PHY_PLL_STATUS */ "", 20807 /* DRCE_DDR_PHY_UPDATE_ENABLE */ "", 20808 /* DRCE_DPI_POWER */ "", 20809 /* DRCE_DPI_STATUS */ "", 20810 /* DRCE_DPI_STAT_CNTRL */ "", 20811 /* DRCE_DPRC_ENABLERS */ "", 20812 /* DRCE_DQ_BYTE_0_MAP */ "", 20813 /* DRCE_DQ_BYTE_1_MAP */ "", 20814 /* DRCE_DQ_BYTE_2_MAP */ "", 20815 /* DRCE_DQ_BYTE_3_MAP */ "", 20816 /* DRCE_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 20817 /* DRCE_DRAM_ERROR_DETECT */ "", 20818 /* DRCE_DRAM_ERROR_INNITATE */ "", 20819 /* DRCE_DRAM_ERROR_RECOVERY */ "", 20820 /* DRCE_DRAM_INIT_FINISHED */ "", 20821 /* DRCE_DRAM_MR_0 */ "", 20822 /* DRCE_DRAM_MR_1 */ "", 20823 /* DRCE_DRAM_MR_2 */ "", 20824 /* DRCE_DRAM_MR_3 */ "", 20825 /* DRCE_DRAM_MR_4 */ "", 20826 /* DRCE_DRAM_MR_5 */ "", 20827 /* DRCE_DRAM_MR_6 */ "", 20828 /* DRCE_DRAM_MR_7 */ "", 20829 /* DRCE_DRAM_MR_8 */ "", 20830 /* DRCE_DRAM_MR_12 */ "", 20831 /* DRCE_DRAM_MR_14 */ "", 20832 /* DRCE_DRAM_MR_15 */ "", 20833 /* DRCE_DRAM_SET */ "", 20834 /* DRCE_DRAM_SPECIAL_FEATURES */ "", 20835 /* DRCE_DRAM_TIME_PARAMS */ "", 20836 /* DRCE_DWF_WATERMARK */ "", 20837 /* DRCE_ECC_1B_ERR_CNT */ "", 20838 /* DRCE_ECC_2B_ERR_CNT */ "", 20839 /* DRCE_ECC_ERR_1B_INITIATE */ "", 20840 /* DRCE_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 20841 /* DRCE_ECC_ERR_2B_INITIATE */ "", 20842 /* DRCE_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 20843 /* DRCE_ECC_INTERRUPT_REGISTER */ "", 20844 /* DRCE_ECC_INTERRUPT_REGISTER_MASK */ "", 20845 /* DRCE_ECC_INTERRUPT_REGISTER_TEST */ "", 20846 /* DRCE_ERROR_INITIATION_DATA */ "", 20847 /* DRCE_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 20848 /* DRCE_EXTENDED_MODE_WR_2_REGISTER */ "", 20849 /* DRCE_EXT_PHY_CTRL_STATUS */ "", 20850 /* DRCE_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 20851 /* DRCE_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 20852 /* DRCE_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 20853 /* DRCE_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 20854 /* DRCE_GDDR_5_BIST_CONFIGURATIONS */ "", 20855 /* DRCE_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 20856 /* DRCE_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 20857 /* DRCE_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 20858 /* DRCE_GDDR_5_BIST_FINISH_PRD */ "", 20859 /* DRCE_GDDR_5_BIST_PRBS_ADT_SEED */ "", 20860 /* DRCE_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 20861 /* DRCE_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 20862 /* DRCE_GDDR_5_BIST_PRBS_DBI_SEED */ "", 20863 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 20864 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 20865 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 20866 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 20867 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 20868 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 20869 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 20870 /* DRCE_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 20871 /* DRCE_GDDR_5_BIST_STATUSES */ "", 20872 /* DRCE_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 20873 /* DRCE_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 20874 /* DRCE_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 20875 /* DRCE_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 20876 /* DRCE_GDDR_5_SPECIAL_CMD_TIMING */ "", 20877 /* DRCE_GDDR_BIST_LAST_READ_DATA_LSB */ "", 20878 /* DRCE_GDDR_BIST_LAST_READ_DATA_MSB */ "", 20879 /* DRCE_GENERAL_CONFIGURATIONS */ "", 20880 /* DRCE_GLOBAL_MEM_OPTIONS */ "", 20881 /* DRCE_GLUE_LOGIC_REGISTER */ "", 20882 /* DRCE_GTIMER_CONFIGURATION */ "", 20883 /* DRCE_GTIMER_TRIGGER */ "", 20884 /* DRCE_INITIALIZATION_CONTROLL */ "", 20885 /* DRCE_INIT_SEQUENCE_REGISTER */ "", 20886 /* DRCE_INTERRUPT_MASK_REGISTER */ "", 20887 /* DRCE_INTERRUPT_REGISTER */ "", 20888 /* DRCE_INTERRUPT_REGISTER_TEST */ "", 20889 /* DRCE_INTIAL_CALIB_USE_MPR */ "", 20890 /* DRCE_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 20891 /* DRCE_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 20892 /* DRCE_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 20893 /* DRCE_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 20894 /* DRCE_LOOPBACK_CONFIG */ "", 20895 /* DRCE_LOOPBACK_CONTROL */ "", 20896 /* DRCE_LOOPBACK_DBI_ERROR_OCCURRED */ "", 20897 /* DRCE_LOOPBACK_DBI_FULL_ERR_CNT */ "", 20898 /* DRCE_LOOPBACK_DBI_MASK_WORD */ "", 20899 /* DRCE_LOOPBACK_DBI_PATTERN_WORD */ "", 20900 /* DRCE_LOOPBACK_ERROR_OCCURRED */ "", 20901 /* DRCE_LOOPBACK_FULL_ERR_CNT */ "", 20902 /* DRCE_LOOPBACK_MASK_WORD */ "", 20903 /* DRCE_LOOPBACK_PATTERN_WORD */ "", 20904 /* DRCE_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 20905 /* DRCE_LOOPBACK_PRBS_DATA_SEED */ "", 20906 /* DRCE_LOOPBACK_PRBS_DBI_SEED */ "", 20907 /* DRCE_ODT_CONFIGURATION_REGISTER */ "", 20908 /* DRCE_PARITY_ERR_CNT */ "", 20909 /* DRCE_PAR_ERR_INITIATE */ "", 20910 /* DRCE_PAR_ERR_MEM_MASK */ "", 20911 /* DRCE_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 20912 /* DRCE_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 20913 /* DRCE_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 20914 /* DRCE_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 20915 /* DRCE_PHY_CALIBRATION */ "", 20916 /* DRCE_PHY_CALIBRATION_CFG */ "", 20917 /* DRCE_PHY_CALIBRATION_CTRL */ "", 20918 /* DRCE_PHY_CALIBRATION_RES_FIFO_CFG */ "", 20919 /* DRCE_PHY_CALIB_FINISHED */ "", 20920 /* DRCE_PPR_ACTIVE */ "", 20921 /* DRCE_PPR_CFG */ "", 20922 /* DRCE_PWD_CLOCK_CONTROL */ "", 20923 /* DRCE_RBUS_ADDR */ "", 20924 /* DRCE_RBUS_RDATA */ "", 20925 /* DRCE_RBUS_RD_RESULT */ "", 20926 /* DRCE_RBUS_WDATA */ "", 20927 /* DRCE_REGISTER_ACCESS_RD_DATA_VALID */ "", 20928 /* DRCE_REGISTER_CONTROL */ "", 20929 /* DRCE_REGISTER_CONTROL_RDATA */ "", 20930 /* DRCE_REGISTER_CONTROL_WDATA */ "", 20931 /* DRCE_REG_0085 */ "", 20932 /* DRCE_REG_0087 */ "", 20933 /* DRCE_REG_90 */ "", 20934 /* DRCE_REG_0091 */ "", 20935 /* DRCE_REG_0092 */ "", 20936 /* DRCE_REG_0093 */ "", 20937 /* DRCE_REG_0209 */ "", 20938 /* DRCE_REG_0210 */ "", 20939 /* DRCE_REG_0211 */ "", 20940 /* DRCE_REG_0212 */ "", 20941 /* DRCE_REG_0242 */ "", 20942 /* DRCE_REG_0243 */ "", 20943 /* DRCE_REG_00B0 */ "", 20944 /* DRCE_REG_00B1 */ "", 20945 /* DRCE_REG_00B2 */ "", 20946 /* DRCE_REG_00B3 */ "", 20947 /* DRCE_REG_00B4 */ "", 20948 /* DRCE_REG_00B5 */ "", 20949 /* DRCE_REG_00B6 */ "", 20950 /* DRCE_REG_00B7 */ "", 20951 /* DRCE_REG_00B8 */ "", 20952 /* DRCE_REG_00B9 */ "", 20953 /* DRCE_REG_00BA */ "", 20954 /* DRCE_REG_00BB */ "", 20955 /* DRCE_REG_00BC */ "", 20956 /* DRCE_REG_00BD */ "", 20957 /* DRCE_REG_00BE */ "", 20958 /* DRCE_REG_00BF */ "", 20959 /* DRCE_REG_00C0 */ "", 20960 /* DRCE_REG_00C1 */ "", 20961 /* DRCE_REG_00C2 */ "", 20962 /* DRCE_REG_00C3 */ "", 20963 /* DRCE_REG_020A */ "", 20964 /* DRCE_REG_020B */ "", 20965 /* DRCE_REG_020C */ "", 20966 /* DRCE_REG_020D */ "", 20967 /* DRCE_REG_020E */ "", 20968 /* DRCE_REG_020F */ "", 20969 /* DRCE_REG_021C */ "", 20970 /* DRCE_REG_0B0 */ "", 20971 /* DRCE_RESERVED_MIRROR_ADDR */ "", 20972 /* DRCE_RESERVED_MTCD */ "", 20973 /* DRCE_RESERVED_MTCP */ "", 20974 /* DRCE_RESERVED_SPARE_0 */ "", 20975 /* DRCE_RESERVED_SPARE_1 */ "", 20976 /* DRCE_RESERVED_SPARE_2 */ "", 20977 /* DRCE_RESERVED_SPARE_3 */ "", 20978 /* DRCE_RETRANSMIT_STATUS */ "", 20979 /* DRCE_RXI_WATERMARK */ "", 20980 /* DRCE_SBUS_BROADCAST_ID */ "", 20981 /* DRCE_SBUS_LAST_IN_CHAIN */ "", 20982 /* DRCE_SHADOW_DRAM_MR_0 */ "", 20983 /* DRCE_SHADOW_DRAM_MR_1 */ "", 20984 /* DRCE_SHADOW_DRAM_MR_2 */ "", 20985 /* DRCE_SHADOW_DRAM_MR_3 */ "", 20986 /* DRCE_SHADOW_DRAM_MR_4 */ "", 20987 /* DRCE_SHADOW_DRAM_MR_5 */ "", 20988 /* DRCE_SHADOW_DRAM_MR_6 */ "", 20989 /* DRCE_SHADOW_DRAM_MR_7 */ "", 20990 /* DRCE_SHADOW_DRAM_MR_8 */ "", 20991 /* DRCE_SHADOW_DRAM_MR_12 */ "", 20992 /* DRCE_SHADOW_DRAM_MR_14 */ "", 20993 /* DRCE_SHADOW_DRAM_MR_15 */ "", 20994 /* DRCE_SPARE_REGISTER */ "", 20995 /* DRCE_SPARE_REGISTER_3 */ "", 20996 /* DRCE_TRAIN_INIT_TRIGERS */ "", 20997 /* DRCE_VDL_CNTRL */ "", 20998 /* DRCE_WRITE_READ_RATES */ "", 20999 /* DRCE_WR_CRC_WATERMARK */ "", 21000 /* DRCF_AC_OPERATING_CONDITIONS_1 */ "", 21001 /* DRCF_AC_OPERATING_CONDITIONS_2 */ "", 21002 /* DRCF_AC_OPERATING_CONDITIONS_3 */ "", 21003 /* DRCF_AC_OPERATING_CONDITIONS_4 */ "", 21004 /* DRCF_AC_OPERATING_CONDITIONS_5 */ "", 21005 /* DRCF_ADDR_BANK_MAP */ "", 21006 /* DRCF_ADDR_WITH_RD_CRC */ "", 21007 /* DRCF_ADDR_WITH_WR_CRC */ "", 21008 /* DRCF_ALIGN_ERR_INDICATION */ "", 21009 /* DRCF_AUXS_MUX */ "", 21010 /* DRCF_BIST_CONFIGURATIONS */ "", 21011 /* DRCF_BIST_DBI_ERR_OCCURED */ "", 21012 /* DRCF_BIST_EDC_ERR_OCCURED */ "", 21013 /* DRCF_BIST_END_ADDRESS */ "", 21014 /* DRCF_BIST_ERROR_OCCURRED */ "", 21015 /* DRCF_BIST_FULL_MASK_ERROR_COUNTER */ "", 21016 /* DRCF_BIST_FULL_MASK_WORD_0 */ "", 21017 /* DRCF_BIST_FULL_MASK_WORD_1 */ "", 21018 /* DRCF_BIST_FULL_MASK_WORD_2 */ "", 21019 /* DRCF_BIST_FULL_MASK_WORD_3 */ "", 21020 /* DRCF_BIST_FULL_MASK_WORD_4 */ "", 21021 /* DRCF_BIST_FULL_MASK_WORD_5 */ "", 21022 /* DRCF_BIST_FULL_MASK_WORD_6 */ "", 21023 /* DRCF_BIST_FULL_MASK_WORD_7 */ "", 21024 /* DRCF_BIST_GLOBAL_ERROR_COUNTER */ "", 21025 /* DRCF_BIST_LAST_ADDR_ERR */ "", 21026 /* DRCF_BIST_LAST_DATA_ERR */ "", 21027 /* DRCF_BIST_LAST_DATA_ERR_LSB */ "", 21028 /* DRCF_BIST_LAST_DATA_ERR_MSB */ "", 21029 /* DRCF_BIST_LAST_READ_DATA_LSB */ "", 21030 /* DRCF_BIST_LAST_READ_DATA_MSB */ "", 21031 /* DRCF_BIST_MPR_STAGGER_PATTERNS */ "", 21032 /* DRCF_BIST_MPR_STAGGER_WEIGHTS */ "", 21033 /* DRCF_BIST_NUMBER_OF_ACTIONS */ "", 21034 /* DRCF_BIST_PATTERN_REPETITION */ "", 21035 /* DRCF_BIST_PATTERN_WORD_0 */ "", 21036 /* DRCF_BIST_PATTERN_WORD_1 */ "", 21037 /* DRCF_BIST_PATTERN_WORD_2 */ "", 21038 /* DRCF_BIST_PATTERN_WORD_3 */ "", 21039 /* DRCF_BIST_PATTERN_WORD_4 */ "", 21040 /* DRCF_BIST_PATTERN_WORD_5 */ "", 21041 /* DRCF_BIST_PATTERN_WORD_6 */ "", 21042 /* DRCF_BIST_PATTERN_WORD_7 */ "", 21043 /* DRCF_BIST_PRBS_ADDR_SEED */ "", 21044 /* DRCF_BIST_PRBS_DATA_SEED_LSB */ "", 21045 /* DRCF_BIST_PRBS_DATA_SEED_MSB */ "", 21046 /* DRCF_BIST_RATE_LIMITER */ "", 21047 /* DRCF_BIST_REPEAT_PATTERN_1_LSB */ "", 21048 /* DRCF_BIST_REPEAT_PATTERN_1_MSB */ "", 21049 /* DRCF_BIST_REPEAT_PATTERN_2_LSB */ "", 21050 /* DRCF_BIST_REPEAT_PATTERN_2_MSB */ "", 21051 /* DRCF_BIST_REPEAT_PATTERN_3_LSB */ "", 21052 /* DRCF_BIST_REPEAT_PATTERN_3_MSB */ "", 21053 /* DRCF_BIST_REPEAT_PATTERN_4_LSB */ "", 21054 /* DRCF_BIST_REPEAT_PATTERN_4_MSB */ "", 21055 /* DRCF_BIST_REPEAT_PATTERN_5_LSB */ "", 21056 /* DRCF_BIST_REPEAT_PATTERN_5_MSB */ "", 21057 /* DRCF_BIST_REPEAT_PATTERN_6_LSB */ "", 21058 /* DRCF_BIST_REPEAT_PATTERN_6_MSB */ "", 21059 /* DRCF_BIST_REPEAT_PATTERN_7_LSB */ "", 21060 /* DRCF_BIST_REPEAT_PATTERN_7_MSB */ "", 21061 /* DRCF_BIST_SINGLE_BIT_MASK */ "", 21062 /* DRCF_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 21063 /* DRCF_BIST_START_ADDRESS */ "", 21064 /* DRCF_BIST_STATUSES */ "", 21065 /* DRCF_CALIBRATION_SEQUENCE_ADDRESS */ "", 21066 /* DRCF_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 21067 /* DRCF_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 21068 /* DRCF_CALIB_BIST_ERROR_OCCURRED */ "", 21069 /* DRCF_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 21070 /* DRCF_CLAM_SHELL */ "", 21071 /* DRCF_CNT_BIST_DBI_ERR_GLOBAL */ "", 21072 /* DRCF_CNT_BIST_EDC_ERR_GLOBAL */ "", 21073 /* DRCF_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 21074 /* DRCF_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 21075 /* DRCF_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 21076 /* DRCF_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 21077 /* DRCF_CPU_COMMANDS */ "", 21078 /* DRCF_DATA_LOCK */ "", 21079 /* DRCF_DATA_LOCK_TIMEOUT_PRD */ "", 21080 /* DRCF_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 21081 /* DRCF_DDR_CONTROLLER_TRIGGERS */ "", 21082 /* DRCF_DDR_EXTENDED_MODE_REGISTER_1 */ "", 21083 /* DRCF_DDR_EXTENDED_MODE_REGISTER_2 */ "", 21084 /* DRCF_DDR_EXTENDED_MODE_REGISTER_3 */ "", 21085 /* DRCF_DDR_MODE_REGISTER_1 */ "", 21086 /* DRCF_DDR_MODE_REGISTER_2 */ "", 21087 /* DRCF_DDR_PHY_PLL_CTRL */ "", 21088 /* DRCF_DDR_PHY_PLL_FREQ_CTRL */ "", 21089 /* DRCF_DDR_PHY_PLL_RC */ "", 21090 /* DRCF_DDR_PHY_PLL_RESET */ "", 21091 /* DRCF_DDR_PHY_PLL_STATUS */ "", 21092 /* DRCF_DDR_PHY_UPDATE_ENABLE */ "", 21093 /* DRCF_DPI_POWER */ "", 21094 /* DRCF_DPI_STATUS */ "", 21095 /* DRCF_DPI_STAT_CNTRL */ "", 21096 /* DRCF_DPRC_ENABLERS */ "", 21097 /* DRCF_DQ_BYTE_0_MAP */ "", 21098 /* DRCF_DQ_BYTE_1_MAP */ "", 21099 /* DRCF_DQ_BYTE_2_MAP */ "", 21100 /* DRCF_DQ_BYTE_3_MAP */ "", 21101 /* DRCF_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 21102 /* DRCF_DRAM_ERROR_DETECT */ "", 21103 /* DRCF_DRAM_ERROR_INNITATE */ "", 21104 /* DRCF_DRAM_ERROR_RECOVERY */ "", 21105 /* DRCF_DRAM_INIT_FINISHED */ "", 21106 /* DRCF_DRAM_MR_0 */ "", 21107 /* DRCF_DRAM_MR_1 */ "", 21108 /* DRCF_DRAM_MR_2 */ "", 21109 /* DRCF_DRAM_MR_3 */ "", 21110 /* DRCF_DRAM_MR_4 */ "", 21111 /* DRCF_DRAM_MR_5 */ "", 21112 /* DRCF_DRAM_MR_6 */ "", 21113 /* DRCF_DRAM_MR_7 */ "", 21114 /* DRCF_DRAM_MR_8 */ "", 21115 /* DRCF_DRAM_MR_12 */ "", 21116 /* DRCF_DRAM_MR_14 */ "", 21117 /* DRCF_DRAM_MR_15 */ "", 21118 /* DRCF_DRAM_SET */ "", 21119 /* DRCF_DRAM_SPECIAL_FEATURES */ "", 21120 /* DRCF_DRAM_TIME_PARAMS */ "", 21121 /* DRCF_DWF_WATERMARK */ "", 21122 /* DRCF_ECC_1B_ERR_CNT */ "", 21123 /* DRCF_ECC_2B_ERR_CNT */ "", 21124 /* DRCF_ECC_ERR_1B_INITIATE */ "", 21125 /* DRCF_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 21126 /* DRCF_ECC_ERR_2B_INITIATE */ "", 21127 /* DRCF_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 21128 /* DRCF_ECC_INTERRUPT_REGISTER */ "", 21129 /* DRCF_ECC_INTERRUPT_REGISTER_MASK */ "", 21130 /* DRCF_ECC_INTERRUPT_REGISTER_TEST */ "", 21131 /* DRCF_ERROR_INITIATION_DATA */ "", 21132 /* DRCF_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 21133 /* DRCF_EXTENDED_MODE_WR_2_REGISTER */ "", 21134 /* DRCF_EXT_PHY_CTRL_STATUS */ "", 21135 /* DRCF_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 21136 /* DRCF_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 21137 /* DRCF_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 21138 /* DRCF_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 21139 /* DRCF_GDDR_5_BIST_CONFIGURATIONS */ "", 21140 /* DRCF_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 21141 /* DRCF_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 21142 /* DRCF_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 21143 /* DRCF_GDDR_5_BIST_FINISH_PRD */ "", 21144 /* DRCF_GDDR_5_BIST_PRBS_ADT_SEED */ "", 21145 /* DRCF_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 21146 /* DRCF_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 21147 /* DRCF_GDDR_5_BIST_PRBS_DBI_SEED */ "", 21148 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 21149 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 21150 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 21151 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 21152 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 21153 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 21154 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 21155 /* DRCF_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 21156 /* DRCF_GDDR_5_BIST_STATUSES */ "", 21157 /* DRCF_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 21158 /* DRCF_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 21159 /* DRCF_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 21160 /* DRCF_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 21161 /* DRCF_GDDR_5_SPECIAL_CMD_TIMING */ "", 21162 /* DRCF_GDDR_BIST_LAST_READ_DATA_LSB */ "", 21163 /* DRCF_GDDR_BIST_LAST_READ_DATA_MSB */ "", 21164 /* DRCF_GENERAL_CONFIGURATIONS */ "", 21165 /* DRCF_GLOBAL_MEM_OPTIONS */ "", 21166 /* DRCF_GLUE_LOGIC_REGISTER */ "", 21167 /* DRCF_GTIMER_CONFIGURATION */ "", 21168 /* DRCF_GTIMER_TRIGGER */ "", 21169 /* DRCF_INITIALIZATION_CONTROLL */ "", 21170 /* DRCF_INIT_SEQUENCE_REGISTER */ "", 21171 /* DRCF_INTERRUPT_MASK_REGISTER */ "", 21172 /* DRCF_INTERRUPT_REGISTER */ "", 21173 /* DRCF_INTERRUPT_REGISTER_TEST */ "", 21174 /* DRCF_INTIAL_CALIB_USE_MPR */ "", 21175 /* DRCF_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 21176 /* DRCF_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 21177 /* DRCF_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 21178 /* DRCF_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 21179 /* DRCF_LOOPBACK_CONFIG */ "", 21180 /* DRCF_LOOPBACK_CONTROL */ "", 21181 /* DRCF_LOOPBACK_DBI_ERROR_OCCURRED */ "", 21182 /* DRCF_LOOPBACK_DBI_FULL_ERR_CNT */ "", 21183 /* DRCF_LOOPBACK_DBI_MASK_WORD */ "", 21184 /* DRCF_LOOPBACK_DBI_PATTERN_WORD */ "", 21185 /* DRCF_LOOPBACK_ERROR_OCCURRED */ "", 21186 /* DRCF_LOOPBACK_FULL_ERR_CNT */ "", 21187 /* DRCF_LOOPBACK_MASK_WORD */ "", 21188 /* DRCF_LOOPBACK_PATTERN_WORD */ "", 21189 /* DRCF_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 21190 /* DRCF_LOOPBACK_PRBS_DATA_SEED */ "", 21191 /* DRCF_LOOPBACK_PRBS_DBI_SEED */ "", 21192 /* DRCF_ODT_CONFIGURATION_REGISTER */ "", 21193 /* DRCF_PARITY_ERR_CNT */ "", 21194 /* DRCF_PAR_ERR_INITIATE */ "", 21195 /* DRCF_PAR_ERR_MEM_MASK */ "", 21196 /* DRCF_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 21197 /* DRCF_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 21198 /* DRCF_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 21199 /* DRCF_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 21200 /* DRCF_PHY_CALIBRATION */ "", 21201 /* DRCF_PHY_CALIBRATION_CFG */ "", 21202 /* DRCF_PHY_CALIBRATION_CTRL */ "", 21203 /* DRCF_PHY_CALIBRATION_RES_FIFO_CFG */ "", 21204 /* DRCF_PHY_CALIB_FINISHED */ "", 21205 /* DRCF_PPR_ACTIVE */ "", 21206 /* DRCF_PPR_CFG */ "", 21207 /* DRCF_PWD_CLOCK_CONTROL */ "", 21208 /* DRCF_RBUS_ADDR */ "", 21209 /* DRCF_RBUS_RDATA */ "", 21210 /* DRCF_RBUS_RD_RESULT */ "", 21211 /* DRCF_RBUS_WDATA */ "", 21212 /* DRCF_REGISTER_ACCESS_RD_DATA_VALID */ "", 21213 /* DRCF_REGISTER_CONTROL */ "", 21214 /* DRCF_REGISTER_CONTROL_RDATA */ "", 21215 /* DRCF_REGISTER_CONTROL_WDATA */ "", 21216 /* DRCF_REG_0085 */ "", 21217 /* DRCF_REG_0087 */ "", 21218 /* DRCF_REG_90 */ "", 21219 /* DRCF_REG_0091 */ "", 21220 /* DRCF_REG_0092 */ "", 21221 /* DRCF_REG_0209 */ "", 21222 /* DRCF_REG_0210 */ "", 21223 /* DRCF_REG_0211 */ "", 21224 /* DRCF_REG_0212 */ "", 21225 /* DRCF_REG_0242 */ "", 21226 /* DRCF_REG_0243 */ "", 21227 /* DRCF_REG_00B0 */ "", 21228 /* DRCF_REG_00B1 */ "", 21229 /* DRCF_REG_00B2 */ "", 21230 /* DRCF_REG_00B3 */ "", 21231 /* DRCF_REG_00B4 */ "", 21232 /* DRCF_REG_00B5 */ "", 21233 /* DRCF_REG_00B6 */ "", 21234 /* DRCF_REG_00B7 */ "", 21235 /* DRCF_REG_020A */ "", 21236 /* DRCF_REG_020B */ "", 21237 /* DRCF_REG_020C */ "", 21238 /* DRCF_REG_020D */ "", 21239 /* DRCF_REG_020E */ "", 21240 /* DRCF_REG_020F */ "", 21241 /* DRCF_REG_021C */ "", 21242 /* DRCF_RESERVED_MIRROR_ADDR */ "", 21243 /* DRCF_RESERVED_MTCD */ "", 21244 /* DRCF_RESERVED_MTCP */ "", 21245 /* DRCF_RESERVED_SPARE_0 */ "", 21246 /* DRCF_RESERVED_SPARE_1 */ "", 21247 /* DRCF_RESERVED_SPARE_2 */ "", 21248 /* DRCF_RESERVED_SPARE_3 */ "", 21249 /* DRCF_RETRANSMIT_STATUS */ "", 21250 /* DRCF_RXI_WATERMARK */ "", 21251 /* DRCF_SBUS_BROADCAST_ID */ "", 21252 /* DRCF_SBUS_LAST_IN_CHAIN */ "", 21253 /* DRCF_SHADOW_DRAM_MR_0 */ "", 21254 /* DRCF_SHADOW_DRAM_MR_1 */ "", 21255 /* DRCF_SHADOW_DRAM_MR_2 */ "", 21256 /* DRCF_SHADOW_DRAM_MR_3 */ "", 21257 /* DRCF_SHADOW_DRAM_MR_4 */ "", 21258 /* DRCF_SHADOW_DRAM_MR_5 */ "", 21259 /* DRCF_SHADOW_DRAM_MR_6 */ "", 21260 /* DRCF_SHADOW_DRAM_MR_7 */ "", 21261 /* DRCF_SHADOW_DRAM_MR_8 */ "", 21262 /* DRCF_SHADOW_DRAM_MR_12 */ "", 21263 /* DRCF_SHADOW_DRAM_MR_14 */ "", 21264 /* DRCF_SHADOW_DRAM_MR_15 */ "", 21265 /* DRCF_SPARE_REGISTER */ "", 21266 /* DRCF_SPARE_REGISTER_3 */ "", 21267 /* DRCF_TRAIN_INIT_TRIGERS */ "", 21268 /* DRCF_VDL_CNTRL */ "", 21269 /* DRCF_WRITE_READ_RATES */ "", 21270 /* DRCF_WR_CRC_WATERMARK */ "", 21271 /* DRCG_AC_OPERATING_CONDITIONS_1 */ "", 21272 /* DRCG_AC_OPERATING_CONDITIONS_2 */ "", 21273 /* DRCG_AC_OPERATING_CONDITIONS_3 */ "", 21274 /* DRCG_AC_OPERATING_CONDITIONS_4 */ "", 21275 /* DRCG_AC_OPERATING_CONDITIONS_5 */ "", 21276 /* DRCG_ADDR_BANK_MAP */ "", 21277 /* DRCG_ADDR_WITH_RD_CRC */ "", 21278 /* DRCG_ADDR_WITH_WR_CRC */ "", 21279 /* DRCG_ALIGN_ERR_INDICATION */ "", 21280 /* DRCG_AUXS_MUX */ "", 21281 /* DRCG_BIST_CONFIGURATIONS */ "", 21282 /* DRCG_BIST_DBI_ERR_OCCURED */ "", 21283 /* DRCG_BIST_EDC_ERR_OCCURED */ "", 21284 /* DRCG_BIST_END_ADDRESS */ "", 21285 /* DRCG_BIST_ERROR_OCCURRED */ "", 21286 /* DRCG_BIST_FULL_MASK_ERROR_COUNTER */ "", 21287 /* DRCG_BIST_FULL_MASK_WORD_0 */ "", 21288 /* DRCG_BIST_FULL_MASK_WORD_1 */ "", 21289 /* DRCG_BIST_FULL_MASK_WORD_2 */ "", 21290 /* DRCG_BIST_FULL_MASK_WORD_3 */ "", 21291 /* DRCG_BIST_FULL_MASK_WORD_4 */ "", 21292 /* DRCG_BIST_FULL_MASK_WORD_5 */ "", 21293 /* DRCG_BIST_FULL_MASK_WORD_6 */ "", 21294 /* DRCG_BIST_FULL_MASK_WORD_7 */ "", 21295 /* DRCG_BIST_GLOBAL_ERROR_COUNTER */ "", 21296 /* DRCG_BIST_LAST_ADDR_ERR */ "", 21297 /* DRCG_BIST_LAST_DATA_ERR */ "", 21298 /* DRCG_BIST_LAST_DATA_ERR_LSB */ "", 21299 /* DRCG_BIST_LAST_DATA_ERR_MSB */ "", 21300 /* DRCG_BIST_LAST_READ_DATA_LSB */ "", 21301 /* DRCG_BIST_LAST_READ_DATA_MSB */ "", 21302 /* DRCG_BIST_MPR_STAGGER_PATTERNS */ "", 21303 /* DRCG_BIST_MPR_STAGGER_WEIGHTS */ "", 21304 /* DRCG_BIST_NUMBER_OF_ACTIONS */ "", 21305 /* DRCG_BIST_PATTERN_REPETITION */ "", 21306 /* DRCG_BIST_PATTERN_WORD_0 */ "", 21307 /* DRCG_BIST_PATTERN_WORD_1 */ "", 21308 /* DRCG_BIST_PATTERN_WORD_2 */ "", 21309 /* DRCG_BIST_PATTERN_WORD_3 */ "", 21310 /* DRCG_BIST_PATTERN_WORD_4 */ "", 21311 /* DRCG_BIST_PATTERN_WORD_5 */ "", 21312 /* DRCG_BIST_PATTERN_WORD_6 */ "", 21313 /* DRCG_BIST_PATTERN_WORD_7 */ "", 21314 /* DRCG_BIST_PRBS_ADDR_SEED */ "", 21315 /* DRCG_BIST_PRBS_DATA_SEED_LSB */ "", 21316 /* DRCG_BIST_PRBS_DATA_SEED_MSB */ "", 21317 /* DRCG_BIST_RATE_LIMITER */ "", 21318 /* DRCG_BIST_REPEAT_PATTERN_1_LSB */ "", 21319 /* DRCG_BIST_REPEAT_PATTERN_1_MSB */ "", 21320 /* DRCG_BIST_REPEAT_PATTERN_2_LSB */ "", 21321 /* DRCG_BIST_REPEAT_PATTERN_2_MSB */ "", 21322 /* DRCG_BIST_REPEAT_PATTERN_3_LSB */ "", 21323 /* DRCG_BIST_REPEAT_PATTERN_3_MSB */ "", 21324 /* DRCG_BIST_REPEAT_PATTERN_4_LSB */ "", 21325 /* DRCG_BIST_REPEAT_PATTERN_4_MSB */ "", 21326 /* DRCG_BIST_REPEAT_PATTERN_5_LSB */ "", 21327 /* DRCG_BIST_REPEAT_PATTERN_5_MSB */ "", 21328 /* DRCG_BIST_REPEAT_PATTERN_6_LSB */ "", 21329 /* DRCG_BIST_REPEAT_PATTERN_6_MSB */ "", 21330 /* DRCG_BIST_REPEAT_PATTERN_7_LSB */ "", 21331 /* DRCG_BIST_REPEAT_PATTERN_7_MSB */ "", 21332 /* DRCG_BIST_SINGLE_BIT_MASK */ "", 21333 /* DRCG_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 21334 /* DRCG_BIST_START_ADDRESS */ "", 21335 /* DRCG_BIST_STATUSES */ "", 21336 /* DRCG_CALIBRATION_SEQUENCE_ADDRESS */ "", 21337 /* DRCG_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 21338 /* DRCG_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 21339 /* DRCG_CALIB_BIST_ERROR_OCCURRED */ "", 21340 /* DRCG_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 21341 /* DRCG_CLAM_SHELL */ "", 21342 /* DRCG_CNT_BIST_DBI_ERR_GLOBAL */ "", 21343 /* DRCG_CNT_BIST_EDC_ERR_GLOBAL */ "", 21344 /* DRCG_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 21345 /* DRCG_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 21346 /* DRCG_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 21347 /* DRCG_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 21348 /* DRCG_CPU_COMMANDS */ "", 21349 /* DRCG_DATA_LOCK */ "", 21350 /* DRCG_DATA_LOCK_TIMEOUT_PRD */ "", 21351 /* DRCG_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 21352 /* DRCG_DDR_CONTROLLER_TRIGGERS */ "", 21353 /* DRCG_DDR_EXTENDED_MODE_REGISTER_1 */ "", 21354 /* DRCG_DDR_EXTENDED_MODE_REGISTER_2 */ "", 21355 /* DRCG_DDR_EXTENDED_MODE_REGISTER_3 */ "", 21356 /* DRCG_DDR_MODE_REGISTER_1 */ "", 21357 /* DRCG_DDR_MODE_REGISTER_2 */ "", 21358 /* DRCG_DDR_PHY_PLL_CTRL */ "", 21359 /* DRCG_DDR_PHY_PLL_FREQ_CTRL */ "", 21360 /* DRCG_DDR_PHY_PLL_RC */ "", 21361 /* DRCG_DDR_PHY_PLL_RESET */ "", 21362 /* DRCG_DDR_PHY_PLL_STATUS */ "", 21363 /* DRCG_DDR_PHY_UPDATE_ENABLE */ "", 21364 /* DRCG_DPI_POWER */ "", 21365 /* DRCG_DPI_STATUS */ "", 21366 /* DRCG_DPI_STAT_CNTRL */ "", 21367 /* DRCG_DPRC_ENABLERS */ "", 21368 /* DRCG_DQ_BYTE_0_MAP */ "", 21369 /* DRCG_DQ_BYTE_1_MAP */ "", 21370 /* DRCG_DQ_BYTE_2_MAP */ "", 21371 /* DRCG_DQ_BYTE_3_MAP */ "", 21372 /* DRCG_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 21373 /* DRCG_DRAM_ERROR_DETECT */ "", 21374 /* DRCG_DRAM_ERROR_INNITATE */ "", 21375 /* DRCG_DRAM_ERROR_RECOVERY */ "", 21376 /* DRCG_DRAM_INIT_FINISHED */ "", 21377 /* DRCG_DRAM_MR_0 */ "", 21378 /* DRCG_DRAM_MR_1 */ "", 21379 /* DRCG_DRAM_MR_2 */ "", 21380 /* DRCG_DRAM_MR_3 */ "", 21381 /* DRCG_DRAM_MR_4 */ "", 21382 /* DRCG_DRAM_MR_5 */ "", 21383 /* DRCG_DRAM_MR_6 */ "", 21384 /* DRCG_DRAM_MR_7 */ "", 21385 /* DRCG_DRAM_MR_8 */ "", 21386 /* DRCG_DRAM_MR_12 */ "", 21387 /* DRCG_DRAM_MR_14 */ "", 21388 /* DRCG_DRAM_MR_15 */ "", 21389 /* DRCG_DRAM_SET */ "", 21390 /* DRCG_DRAM_SPECIAL_FEATURES */ "", 21391 /* DRCG_DRAM_TIME_PARAMS */ "", 21392 /* DRCG_DWF_WATERMARK */ "", 21393 /* DRCG_ECC_1B_ERR_CNT */ "", 21394 /* DRCG_ECC_2B_ERR_CNT */ "", 21395 /* DRCG_ECC_ERR_1B_INITIATE */ "", 21396 /* DRCG_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 21397 /* DRCG_ECC_ERR_2B_INITIATE */ "", 21398 /* DRCG_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 21399 /* DRCG_ECC_INTERRUPT_REGISTER */ "", 21400 /* DRCG_ECC_INTERRUPT_REGISTER_MASK */ "", 21401 /* DRCG_ECC_INTERRUPT_REGISTER_TEST */ "", 21402 /* DRCG_ERROR_INITIATION_DATA */ "", 21403 /* DRCG_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 21404 /* DRCG_EXTENDED_MODE_WR_2_REGISTER */ "", 21405 /* DRCG_EXT_PHY_CTRL_STATUS */ "", 21406 /* DRCG_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 21407 /* DRCG_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 21408 /* DRCG_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 21409 /* DRCG_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 21410 /* DRCG_GDDR_5_BIST_CONFIGURATIONS */ "", 21411 /* DRCG_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 21412 /* DRCG_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 21413 /* DRCG_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 21414 /* DRCG_GDDR_5_BIST_FINISH_PRD */ "", 21415 /* DRCG_GDDR_5_BIST_PRBS_ADT_SEED */ "", 21416 /* DRCG_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 21417 /* DRCG_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 21418 /* DRCG_GDDR_5_BIST_PRBS_DBI_SEED */ "", 21419 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 21420 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 21421 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 21422 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 21423 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 21424 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 21425 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 21426 /* DRCG_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 21427 /* DRCG_GDDR_5_BIST_STATUSES */ "", 21428 /* DRCG_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 21429 /* DRCG_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 21430 /* DRCG_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 21431 /* DRCG_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 21432 /* DRCG_GDDR_5_SPECIAL_CMD_TIMING */ "", 21433 /* DRCG_GDDR_BIST_LAST_READ_DATA_LSB */ "", 21434 /* DRCG_GDDR_BIST_LAST_READ_DATA_MSB */ "", 21435 /* DRCG_GENERAL_CONFIGURATIONS */ "", 21436 /* DRCG_GLOBAL_MEM_OPTIONS */ "", 21437 /* DRCG_GLUE_LOGIC_REGISTER */ "", 21438 /* DRCG_GTIMER_CONFIGURATION */ "", 21439 /* DRCG_GTIMER_TRIGGER */ "", 21440 /* DRCG_INITIALIZATION_CONTROLL */ "", 21441 /* DRCG_INIT_SEQUENCE_REGISTER */ "", 21442 /* DRCG_INTERRUPT_MASK_REGISTER */ "", 21443 /* DRCG_INTERRUPT_REGISTER */ "", 21444 /* DRCG_INTERRUPT_REGISTER_TEST */ "", 21445 /* DRCG_INTIAL_CALIB_USE_MPR */ "", 21446 /* DRCG_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 21447 /* DRCG_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 21448 /* DRCG_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 21449 /* DRCG_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 21450 /* DRCG_LOOPBACK_CONFIG */ "", 21451 /* DRCG_LOOPBACK_CONTROL */ "", 21452 /* DRCG_LOOPBACK_DBI_ERROR_OCCURRED */ "", 21453 /* DRCG_LOOPBACK_DBI_FULL_ERR_CNT */ "", 21454 /* DRCG_LOOPBACK_DBI_MASK_WORD */ "", 21455 /* DRCG_LOOPBACK_DBI_PATTERN_WORD */ "", 21456 /* DRCG_LOOPBACK_ERROR_OCCURRED */ "", 21457 /* DRCG_LOOPBACK_FULL_ERR_CNT */ "", 21458 /* DRCG_LOOPBACK_MASK_WORD */ "", 21459 /* DRCG_LOOPBACK_PATTERN_WORD */ "", 21460 /* DRCG_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 21461 /* DRCG_LOOPBACK_PRBS_DATA_SEED */ "", 21462 /* DRCG_LOOPBACK_PRBS_DBI_SEED */ "", 21463 /* DRCG_ODT_CONFIGURATION_REGISTER */ "", 21464 /* DRCG_PARITY_ERR_CNT */ "", 21465 /* DRCG_PAR_ERR_INITIATE */ "", 21466 /* DRCG_PAR_ERR_MEM_MASK */ "", 21467 /* DRCG_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 21468 /* DRCG_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 21469 /* DRCG_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 21470 /* DRCG_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 21471 /* DRCG_PHY_CALIBRATION */ "", 21472 /* DRCG_PHY_CALIBRATION_CFG */ "", 21473 /* DRCG_PHY_CALIBRATION_CTRL */ "", 21474 /* DRCG_PHY_CALIBRATION_RES_FIFO_CFG */ "", 21475 /* DRCG_PHY_CALIB_FINISHED */ "", 21476 /* DRCG_PPR_ACTIVE */ "", 21477 /* DRCG_PPR_CFG */ "", 21478 /* DRCG_PWD_CLOCK_CONTROL */ "", 21479 /* DRCG_RBUS_ADDR */ "", 21480 /* DRCG_RBUS_RDATA */ "", 21481 /* DRCG_RBUS_RD_RESULT */ "", 21482 /* DRCG_RBUS_WDATA */ "", 21483 /* DRCG_REGISTER_ACCESS_RD_DATA_VALID */ "", 21484 /* DRCG_REGISTER_CONTROL */ "", 21485 /* DRCG_REGISTER_CONTROL_RDATA */ "", 21486 /* DRCG_REGISTER_CONTROL_WDATA */ "", 21487 /* DRCG_REG_0085 */ "", 21488 /* DRCG_REG_0087 */ "", 21489 /* DRCG_REG_90 */ "", 21490 /* DRCG_REG_0091 */ "", 21491 /* DRCG_REG_0092 */ "", 21492 /* DRCG_REG_0209 */ "", 21493 /* DRCG_REG_0210 */ "", 21494 /* DRCG_REG_0211 */ "", 21495 /* DRCG_REG_0212 */ "", 21496 /* DRCG_REG_0242 */ "", 21497 /* DRCG_REG_0243 */ "", 21498 /* DRCG_REG_00B0 */ "", 21499 /* DRCG_REG_00B1 */ "", 21500 /* DRCG_REG_00B2 */ "", 21501 /* DRCG_REG_00B3 */ "", 21502 /* DRCG_REG_00B4 */ "", 21503 /* DRCG_REG_00B5 */ "", 21504 /* DRCG_REG_00B6 */ "", 21505 /* DRCG_REG_00B7 */ "", 21506 /* DRCG_REG_020A */ "", 21507 /* DRCG_REG_020B */ "", 21508 /* DRCG_REG_020C */ "", 21509 /* DRCG_REG_020D */ "", 21510 /* DRCG_REG_020E */ "", 21511 /* DRCG_REG_020F */ "", 21512 /* DRCG_REG_021C */ "", 21513 /* DRCG_RESERVED_MIRROR_ADDR */ "", 21514 /* DRCG_RESERVED_MTCD */ "", 21515 /* DRCG_RESERVED_MTCP */ "", 21516 /* DRCG_RESERVED_SPARE_0 */ "", 21517 /* DRCG_RESERVED_SPARE_1 */ "", 21518 /* DRCG_RESERVED_SPARE_2 */ "", 21519 /* DRCG_RESERVED_SPARE_3 */ "", 21520 /* DRCG_RETRANSMIT_STATUS */ "", 21521 /* DRCG_RXI_WATERMARK */ "", 21522 /* DRCG_SBUS_BROADCAST_ID */ "", 21523 /* DRCG_SBUS_LAST_IN_CHAIN */ "", 21524 /* DRCG_SHADOW_DRAM_MR_0 */ "", 21525 /* DRCG_SHADOW_DRAM_MR_1 */ "", 21526 /* DRCG_SHADOW_DRAM_MR_2 */ "", 21527 /* DRCG_SHADOW_DRAM_MR_3 */ "", 21528 /* DRCG_SHADOW_DRAM_MR_4 */ "", 21529 /* DRCG_SHADOW_DRAM_MR_5 */ "", 21530 /* DRCG_SHADOW_DRAM_MR_6 */ "", 21531 /* DRCG_SHADOW_DRAM_MR_7 */ "", 21532 /* DRCG_SHADOW_DRAM_MR_8 */ "", 21533 /* DRCG_SHADOW_DRAM_MR_12 */ "", 21534 /* DRCG_SHADOW_DRAM_MR_14 */ "", 21535 /* DRCG_SHADOW_DRAM_MR_15 */ "", 21536 /* DRCG_SPARE_REGISTER */ "", 21537 /* DRCG_SPARE_REGISTER_3 */ "", 21538 /* DRCG_TRAIN_INIT_TRIGERS */ "", 21539 /* DRCG_VDL_CNTRL */ "", 21540 /* DRCG_WRITE_READ_RATES */ "", 21541 /* DRCG_WR_CRC_WATERMARK */ "", 21542 /* DRCH_AC_OPERATING_CONDITIONS_1 */ "", 21543 /* DRCH_AC_OPERATING_CONDITIONS_2 */ "", 21544 /* DRCH_AC_OPERATING_CONDITIONS_3 */ "", 21545 /* DRCH_AC_OPERATING_CONDITIONS_4 */ "", 21546 /* DRCH_AC_OPERATING_CONDITIONS_5 */ "", 21547 /* DRCH_ADDR_BANK_MAP */ "", 21548 /* DRCH_ADDR_WITH_RD_CRC */ "", 21549 /* DRCH_ADDR_WITH_WR_CRC */ "", 21550 /* DRCH_ALIGN_ERR_INDICATION */ "", 21551 /* DRCH_AUXS_MUX */ "", 21552 /* DRCH_BIST_CONFIGURATIONS */ "", 21553 /* DRCH_BIST_DBI_ERR_OCCURED */ "", 21554 /* DRCH_BIST_EDC_ERR_OCCURED */ "", 21555 /* DRCH_BIST_END_ADDRESS */ "", 21556 /* DRCH_BIST_ERROR_OCCURRED */ "", 21557 /* DRCH_BIST_FULL_MASK_ERROR_COUNTER */ "", 21558 /* DRCH_BIST_FULL_MASK_WORD_0 */ "", 21559 /* DRCH_BIST_FULL_MASK_WORD_1 */ "", 21560 /* DRCH_BIST_FULL_MASK_WORD_2 */ "", 21561 /* DRCH_BIST_FULL_MASK_WORD_3 */ "", 21562 /* DRCH_BIST_FULL_MASK_WORD_4 */ "", 21563 /* DRCH_BIST_FULL_MASK_WORD_5 */ "", 21564 /* DRCH_BIST_FULL_MASK_WORD_6 */ "", 21565 /* DRCH_BIST_FULL_MASK_WORD_7 */ "", 21566 /* DRCH_BIST_GLOBAL_ERROR_COUNTER */ "", 21567 /* DRCH_BIST_LAST_ADDR_ERR */ "", 21568 /* DRCH_BIST_LAST_DATA_ERR */ "", 21569 /* DRCH_BIST_LAST_DATA_ERR_LSB */ "", 21570 /* DRCH_BIST_LAST_DATA_ERR_MSB */ "", 21571 /* DRCH_BIST_LAST_READ_DATA_LSB */ "", 21572 /* DRCH_BIST_LAST_READ_DATA_MSB */ "", 21573 /* DRCH_BIST_MPR_STAGGER_PATTERNS */ "", 21574 /* DRCH_BIST_MPR_STAGGER_WEIGHTS */ "", 21575 /* DRCH_BIST_NUMBER_OF_ACTIONS */ "", 21576 /* DRCH_BIST_PATTERN_REPETITION */ "", 21577 /* DRCH_BIST_PATTERN_WORD_0 */ "", 21578 /* DRCH_BIST_PATTERN_WORD_1 */ "", 21579 /* DRCH_BIST_PATTERN_WORD_2 */ "", 21580 /* DRCH_BIST_PATTERN_WORD_3 */ "", 21581 /* DRCH_BIST_PATTERN_WORD_4 */ "", 21582 /* DRCH_BIST_PATTERN_WORD_5 */ "", 21583 /* DRCH_BIST_PATTERN_WORD_6 */ "", 21584 /* DRCH_BIST_PATTERN_WORD_7 */ "", 21585 /* DRCH_BIST_PRBS_ADDR_SEED */ "", 21586 /* DRCH_BIST_PRBS_DATA_SEED_LSB */ "", 21587 /* DRCH_BIST_PRBS_DATA_SEED_MSB */ "", 21588 /* DRCH_BIST_RATE_LIMITER */ "", 21589 /* DRCH_BIST_REPEAT_PATTERN_1_LSB */ "", 21590 /* DRCH_BIST_REPEAT_PATTERN_1_MSB */ "", 21591 /* DRCH_BIST_REPEAT_PATTERN_2_LSB */ "", 21592 /* DRCH_BIST_REPEAT_PATTERN_2_MSB */ "", 21593 /* DRCH_BIST_REPEAT_PATTERN_3_LSB */ "", 21594 /* DRCH_BIST_REPEAT_PATTERN_3_MSB */ "", 21595 /* DRCH_BIST_REPEAT_PATTERN_4_LSB */ "", 21596 /* DRCH_BIST_REPEAT_PATTERN_4_MSB */ "", 21597 /* DRCH_BIST_REPEAT_PATTERN_5_LSB */ "", 21598 /* DRCH_BIST_REPEAT_PATTERN_5_MSB */ "", 21599 /* DRCH_BIST_REPEAT_PATTERN_6_LSB */ "", 21600 /* DRCH_BIST_REPEAT_PATTERN_6_MSB */ "", 21601 /* DRCH_BIST_REPEAT_PATTERN_7_LSB */ "", 21602 /* DRCH_BIST_REPEAT_PATTERN_7_MSB */ "", 21603 /* DRCH_BIST_SINGLE_BIT_MASK */ "", 21604 /* DRCH_BIST_SINGLE_BIT_MASK_ERROR_COUNTER */ "", 21605 /* DRCH_BIST_START_ADDRESS */ "", 21606 /* DRCH_BIST_STATUSES */ "", 21607 /* DRCH_CALIBRATION_SEQUENCE_ADDRESS */ "", 21608 /* DRCH_CALIB_BIST_DBI_ERROR_OCCURRED */ "", 21609 /* DRCH_CALIB_BIST_DBI_FULL_MASK_ERROR_COUNTER */ "", 21610 /* DRCH_CALIB_BIST_ERROR_OCCURRED */ "", 21611 /* DRCH_CALIB_BIST_FULL_MASK_ERROR_COUNTER */ "", 21612 /* DRCH_CLAM_SHELL */ "", 21613 /* DRCH_CNT_BIST_DBI_ERR_GLOBAL */ "", 21614 /* DRCH_CNT_BIST_EDC_ERR_GLOBAL */ "", 21615 /* DRCH_CNT_GDDR_5_BIST_ADT_ERR_GLOBAL */ "", 21616 /* DRCH_CNT_GDDR_5_BIST_DATA_ERR_GLOBAL */ "", 21617 /* DRCH_CNT_GDDR_5_BIST_DBI_ERR_GLOBAL */ "", 21618 /* DRCH_CNT_GDDR_5_BIST_EDC_ERR_GLOBAL */ "", 21619 /* DRCH_CPU_COMMANDS */ "", 21620 /* DRCH_DATA_LOCK */ "", 21621 /* DRCH_DATA_LOCK_TIMEOUT_PRD */ "", 21622 /* DRCH_DDR_2_EXTENDED_MODE_WR_3_REGISTER */ "", 21623 /* DRCH_DDR_CONTROLLER_TRIGGERS */ "", 21624 /* DRCH_DDR_EXTENDED_MODE_REGISTER_1 */ "", 21625 /* DRCH_DDR_EXTENDED_MODE_REGISTER_2 */ "", 21626 /* DRCH_DDR_EXTENDED_MODE_REGISTER_3 */ "", 21627 /* DRCH_DDR_MODE_REGISTER_1 */ "", 21628 /* DRCH_DDR_MODE_REGISTER_2 */ "", 21629 /* DRCH_DDR_PHY_PLL_CTRL */ "", 21630 /* DRCH_DDR_PHY_PLL_FREQ_CTRL */ "", 21631 /* DRCH_DDR_PHY_PLL_RC */ "", 21632 /* DRCH_DDR_PHY_PLL_RESET */ "", 21633 /* DRCH_DDR_PHY_PLL_STATUS */ "", 21634 /* DRCH_DDR_PHY_UPDATE_ENABLE */ "", 21635 /* DRCH_DPI_POWER */ "", 21636 /* DRCH_DPI_STATUS */ "", 21637 /* DRCH_DPI_STAT_CNTRL */ "", 21638 /* DRCH_DPRC_ENABLERS */ "", 21639 /* DRCH_DQ_BYTE_0_MAP */ "", 21640 /* DRCH_DQ_BYTE_1_MAP */ "", 21641 /* DRCH_DQ_BYTE_2_MAP */ "", 21642 /* DRCH_DQ_BYTE_3_MAP */ "", 21643 /* DRCH_DRAM_COMPLIANCE_CONFIGURATION_REGISTER */ "", 21644 /* DRCH_DRAM_ERROR_DETECT */ "", 21645 /* DRCH_DRAM_ERROR_INNITATE */ "", 21646 /* DRCH_DRAM_ERROR_RECOVERY */ "", 21647 /* DRCH_DRAM_INIT_FINISHED */ "", 21648 /* DRCH_DRAM_MR_0 */ "", 21649 /* DRCH_DRAM_MR_1 */ "", 21650 /* DRCH_DRAM_MR_2 */ "", 21651 /* DRCH_DRAM_MR_3 */ "", 21652 /* DRCH_DRAM_MR_4 */ "", 21653 /* DRCH_DRAM_MR_5 */ "", 21654 /* DRCH_DRAM_MR_6 */ "", 21655 /* DRCH_DRAM_MR_7 */ "", 21656 /* DRCH_DRAM_MR_8 */ "", 21657 /* DRCH_DRAM_MR_12 */ "", 21658 /* DRCH_DRAM_MR_14 */ "", 21659 /* DRCH_DRAM_MR_15 */ "", 21660 /* DRCH_DRAM_SET */ "", 21661 /* DRCH_DRAM_SPECIAL_FEATURES */ "", 21662 /* DRCH_DRAM_TIME_PARAMS */ "", 21663 /* DRCH_DWF_WATERMARK */ "", 21664 /* DRCH_ECC_1B_ERR_CNT */ "", 21665 /* DRCH_ECC_2B_ERR_CNT */ "", 21666 /* DRCH_ECC_ERR_1B_INITIATE */ "", 21667 /* DRCH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 21668 /* DRCH_ECC_ERR_2B_INITIATE */ "", 21669 /* DRCH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 21670 /* DRCH_ECC_INTERRUPT_REGISTER */ "", 21671 /* DRCH_ECC_INTERRUPT_REGISTER_MASK */ "", 21672 /* DRCH_ECC_INTERRUPT_REGISTER_TEST */ "", 21673 /* DRCH_ERROR_INITIATION_DATA */ "", 21674 /* DRCH_EVENT_TRIGGER_ON_PARITY_PAD_CONFIG */ "", 21675 /* DRCH_EXTENDED_MODE_WR_2_REGISTER */ "", 21676 /* DRCH_EXT_PHY_CTRL_STATUS */ "", 21677 /* DRCH_GDDR_5_BIST_ADT_ADDR_DQ_MAP */ "", 21678 /* DRCH_GDDR_5_BIST_ADT_ERR_OCCURED */ "", 21679 /* DRCH_GDDR_5_BIST_ADT_PATTERNS_0 */ "", 21680 /* DRCH_GDDR_5_BIST_ADT_PATTERNS_1 */ "", 21681 /* DRCH_GDDR_5_BIST_CONFIGURATIONS */ "", 21682 /* DRCH_GDDR_5_BIST_DATA_ERR_OCCURED */ "", 21683 /* DRCH_GDDR_5_BIST_DBI_ERR_OCCURED */ "", 21684 /* DRCH_GDDR_5_BIST_EDC_ERR_OCCURED */ "", 21685 /* DRCH_GDDR_5_BIST_FINISH_PRD */ "", 21686 /* DRCH_GDDR_5_BIST_PRBS_ADT_SEED */ "", 21687 /* DRCH_GDDR_5_BIST_PRBS_DATA_SEED_LSB */ "", 21688 /* DRCH_GDDR_5_BIST_PRBS_DATA_SEED_MSB */ "", 21689 /* DRCH_GDDR_5_BIST_PRBS_DBI_SEED */ "", 21690 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_0 */ "", 21691 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_1 */ "", 21692 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_2 */ "", 21693 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_3 */ "", 21694 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_4 */ "", 21695 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_5 */ "", 21696 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_6 */ "", 21697 /* DRCH_GDDR_5_BIST_RD_FIFO_PATTERN_7 */ "", 21698 /* DRCH_GDDR_5_BIST_STATUSES */ "", 21699 /* DRCH_GDDR_5_BIST_TOTAL_NUMBER_OF_COMMANDS */ "", 21700 /* DRCH_GDDR_5_BIST_WR_RD_DBI_PATTERN */ "", 21701 /* DRCH_GDDR_5_BIST_WR_RD_PATTERN_LSB */ "", 21702 /* DRCH_GDDR_5_BIST_WR_RD_PATTERN_MSB */ "", 21703 /* DRCH_GDDR_5_SPECIAL_CMD_TIMING */ "", 21704 /* DRCH_GDDR_BIST_LAST_READ_DATA_LSB */ "", 21705 /* DRCH_GDDR_BIST_LAST_READ_DATA_MSB */ "", 21706 /* DRCH_GENERAL_CONFIGURATIONS */ "", 21707 /* DRCH_GLOBAL_MEM_OPTIONS */ "", 21708 /* DRCH_GLUE_LOGIC_REGISTER */ "", 21709 /* DRCH_GTIMER_CONFIGURATION */ "", 21710 /* DRCH_GTIMER_TRIGGER */ "", 21711 /* DRCH_INITIALIZATION_CONTROLL */ "", 21712 /* DRCH_INIT_SEQUENCE_REGISTER */ "", 21713 /* DRCH_INTERRUPT_MASK_REGISTER */ "", 21714 /* DRCH_INTERRUPT_REGISTER */ "", 21715 /* DRCH_INTERRUPT_REGISTER_TEST */ "", 21716 /* DRCH_INTIAL_CALIB_USE_MPR */ "", 21717 /* DRCH_LOOPBACK_ADDR_CTRL_ERROR_OCCURRED */ "", 21718 /* DRCH_LOOPBACK_ADDR_CTRL_FULL_ERR_CNT */ "", 21719 /* DRCH_LOOPBACK_ADDR_CTRL_MASK_WORD */ "", 21720 /* DRCH_LOOPBACK_ADDR_CTRL_PATTERN_WORD */ "", 21721 /* DRCH_LOOPBACK_CONFIG */ "", 21722 /* DRCH_LOOPBACK_CONTROL */ "", 21723 /* DRCH_LOOPBACK_DBI_ERROR_OCCURRED */ "", 21724 /* DRCH_LOOPBACK_DBI_FULL_ERR_CNT */ "", 21725 /* DRCH_LOOPBACK_DBI_MASK_WORD */ "", 21726 /* DRCH_LOOPBACK_DBI_PATTERN_WORD */ "", 21727 /* DRCH_LOOPBACK_ERROR_OCCURRED */ "", 21728 /* DRCH_LOOPBACK_FULL_ERR_CNT */ "", 21729 /* DRCH_LOOPBACK_MASK_WORD */ "", 21730 /* DRCH_LOOPBACK_PATTERN_WORD */ "", 21731 /* DRCH_LOOPBACK_PRBS_ADDR_CTRL_SEED */ "", 21732 /* DRCH_LOOPBACK_PRBS_DATA_SEED */ "", 21733 /* DRCH_LOOPBACK_PRBS_DBI_SEED */ "", 21734 /* DRCH_ODT_CONFIGURATION_REGISTER */ "", 21735 /* DRCH_PARITY_ERR_CNT */ "", 21736 /* DRCH_PAR_ERR_INITIATE */ "", 21737 /* DRCH_PAR_ERR_MEM_MASK */ "", 21738 /* DRCH_PERIODIC_DRAM_TEMP_SENS_CFG */ "", 21739 /* DRCH_PERIODIC_DRAM_TEMP_SENS_STATUS */ "", 21740 /* DRCH_PERIODIC_PHY_CDR_MONITOR_CFG */ "", 21741 /* DRCH_PERIODIC_PHY_CDR_MONITOR_STATUS */ "", 21742 /* DRCH_PHY_CALIBRATION */ "", 21743 /* DRCH_PHY_CALIBRATION_CFG */ "", 21744 /* DRCH_PHY_CALIBRATION_CTRL */ "", 21745 /* DRCH_PHY_CALIBRATION_RES_FIFO_CFG */ "", 21746 /* DRCH_PHY_CALIB_FINISHED */ "", 21747 /* DRCH_PPR_ACTIVE */ "", 21748 /* DRCH_PPR_CFG */ "", 21749 /* DRCH_PWD_CLOCK_CONTROL */ "", 21750 /* DRCH_RBUS_ADDR */ "", 21751 /* DRCH_RBUS_RDATA */ "", 21752 /* DRCH_RBUS_RD_RESULT */ "", 21753 /* DRCH_RBUS_WDATA */ "", 21754 /* DRCH_REGISTER_ACCESS_RD_DATA_VALID */ "", 21755 /* DRCH_REGISTER_CONTROL */ "", 21756 /* DRCH_REGISTER_CONTROL_RDATA */ "", 21757 /* DRCH_REGISTER_CONTROL_WDATA */ "", 21758 /* DRCH_REG_0085 */ "", 21759 /* DRCH_REG_0087 */ "", 21760 /* DRCH_REG_90 */ "", 21761 /* DRCH_REG_0091 */ "", 21762 /* DRCH_REG_0092 */ "", 21763 /* DRCH_REG_0209 */ "", 21764 /* DRCH_REG_0210 */ "", 21765 /* DRCH_REG_0211 */ "", 21766 /* DRCH_REG_0212 */ "", 21767 /* DRCH_REG_0242 */ "", 21768 /* DRCH_REG_0243 */ "", 21769 /* DRCH_REG_00B0 */ "", 21770 /* DRCH_REG_00B1 */ "", 21771 /* DRCH_REG_00B2 */ "", 21772 /* DRCH_REG_00B3 */ "", 21773 /* DRCH_REG_00B4 */ "", 21774 /* DRCH_REG_00B5 */ "", 21775 /* DRCH_REG_00B6 */ "", 21776 /* DRCH_REG_00B7 */ "", 21777 /* DRCH_REG_020A */ "", 21778 /* DRCH_REG_020B */ "", 21779 /* DRCH_REG_020C */ "", 21780 /* DRCH_REG_020D */ "", 21781 /* DRCH_REG_020E */ "", 21782 /* DRCH_REG_020F */ "", 21783 /* DRCH_REG_021C */ "", 21784 /* DRCH_RESERVED_MIRROR_ADDR */ "", 21785 /* DRCH_RESERVED_MTCD */ "", 21786 /* DRCH_RESERVED_MTCP */ "", 21787 /* DRCH_RESERVED_SPARE_0 */ "", 21788 /* DRCH_RESERVED_SPARE_1 */ "", 21789 /* DRCH_RESERVED_SPARE_2 */ "", 21790 /* DRCH_RESERVED_SPARE_3 */ "", 21791 /* DRCH_RETRANSMIT_STATUS */ "", 21792 /* DRCH_RXI_WATERMARK */ "", 21793 /* DRCH_SBUS_BROADCAST_ID */ "", 21794 /* DRCH_SBUS_LAST_IN_CHAIN */ "", 21795 /* DRCH_SHADOW_DRAM_MR_0 */ "", 21796 /* DRCH_SHADOW_DRAM_MR_1 */ "", 21797 /* DRCH_SHADOW_DRAM_MR_2 */ "", 21798 /* DRCH_SHADOW_DRAM_MR_3 */ "", 21799 /* DRCH_SHADOW_DRAM_MR_4 */ "", 21800 /* DRCH_SHADOW_DRAM_MR_5 */ "", 21801 /* DRCH_SHADOW_DRAM_MR_6 */ "", 21802 /* DRCH_SHADOW_DRAM_MR_7 */ "", 21803 /* DRCH_SHADOW_DRAM_MR_8 */ "", 21804 /* DRCH_SHADOW_DRAM_MR_12 */ "", 21805 /* DRCH_SHADOW_DRAM_MR_14 */ "", 21806 /* DRCH_SHADOW_DRAM_MR_15 */ "", 21807 /* DRCH_SPARE_REGISTER */ "", 21808 /* DRCH_SPARE_REGISTER_3 */ "", 21809 /* DRCH_TRAIN_INIT_TRIGERS */ "", 21810 /* DRCH_VDL_CNTRL */ "", 21811 /* DRCH_WRITE_READ_RATES */ "", 21812 /* DRCH_WR_CRC_WATERMARK */ "", 21813 /* DROP_AGG */ "", 21814 /* DROP_BYTE_CNT */ "", 21815 /* DROP_BYTE_CNT_ING */ "", 21816 /* DROP_BYTE_CNT_ING_64 */ "DROP_BYTE_CNT_ING", 21817 /* DROP_CBP */ "", 21818 /* DROP_CBP_64 */ "DROP_CBP", 21819 /* DROP_CNT_EN */ "", 21820 /* DROP_CONTROL_0 */ "", 21821 /* DROP_CONTROL_1 */ "", 21822 /* DROP_ICV_FAILED_PKTS */ "", 21823 /* DROP_MACSEC_ERROR_PKTS */ "", 21824 /* DROP_PKT_CNT */ "", 21825 /* DROP_PKT_CNT_ING */ "", 21826 /* DROP_PKT_CNT_OVQ */ "", 21827 /* DROP_PKT_CNT_RED */ "", 21828 /* DROP_PKT_CNT_RQE_BYTE_64 */ "", 21829 /* DROP_PKT_CNT_RQE_PKT */ "", 21830 /* DROP_PKT_CNT_RQE_PKT_64 */ "DROP_PKT_CNT_RQE_PKT", 21831 /* DROP_PKT_CNT_RQE_RED */ "", 21832 /* DROP_PKT_CNT_RQE_RED_64 */ "DROP_PKT_CNT_RQE_RED", 21833 /* DROP_PKT_CNT_RQE_YEL */ "", 21834 /* DROP_PKT_CNT_RQE_YEL_64 */ "DROP_PKT_CNT_RQE_YEL", 21835 /* DROP_PKT_CNT_YEL */ "", 21836 /* DROP_UNCONTROLLED_PORT_ONLY_PKTS */ "", 21837 /* DSCP_CONTROL */ "", 21838 /* DSCP_DBGCTRL */ "DSCP_CONTROL", 21839 /* DSCP_TABLE_PARITY_CONTROL */ "", 21840 /* DSCP_TABLE_PARITY_STATUS */ "", 21841 /* DSCP_TABLE_PARITY_STATUS_INTR */ "", 21842 /* DSCP_TABLE_PARITY_STATUS_NACK */ "", 21843 /* DST_COMPRESSION_CAM_BIST_CONFIG */ "", 21844 /* DST_COMPRESSION_CAM_BIST_CONFIG_2 */ "", 21845 /* DST_COMPRESSION_CAM_BIST_CONFIG_64 */ "", 21846 /* DST_COMPRESSION_CAM_BIST_CONFIG_2_PIPE0 */ "", 21847 /* DST_COMPRESSION_CAM_BIST_CONFIG_2_PIPE1 */ "", 21848 /* DST_COMPRESSION_CAM_BIST_CONFIG_2_PIPE2 */ "", 21849 /* DST_COMPRESSION_CAM_BIST_CONFIG_2_PIPE3 */ "", 21850 /* DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE0 */ "", 21851 /* DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE1 */ "", 21852 /* DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE2 */ "", 21853 /* DST_COMPRESSION_CAM_BIST_CONFIG_64_PIPE3 */ "", 21854 /* DST_COMPRESSION_CAM_BIST_CONFIG_PIPE0 */ "", 21855 /* DST_COMPRESSION_CAM_BIST_CONFIG_PIPE1 */ "", 21856 /* DST_COMPRESSION_CAM_BIST_CONFIG_PIPE2 */ "", 21857 /* DST_COMPRESSION_CAM_BIST_CONFIG_PIPE3 */ "", 21858 /* DST_COMPRESSION_CAM_BIST_DBG_DATA */ "", 21859 /* DST_COMPRESSION_CAM_BIST_DBG_DATA_PIPE0 */ "", 21860 /* DST_COMPRESSION_CAM_BIST_DBG_DATA_PIPE1 */ "", 21861 /* DST_COMPRESSION_CAM_BIST_DBG_DATA_PIPE2 */ "", 21862 /* DST_COMPRESSION_CAM_BIST_DBG_DATA_PIPE3 */ "", 21863 /* DST_COMPRESSION_CAM_BIST_STATUS */ "", 21864 /* DST_COMPRESSION_CAM_BIST_STATUS_PIPE0 */ "", 21865 /* DST_COMPRESSION_CAM_BIST_STATUS_PIPE1 */ "", 21866 /* DST_COMPRESSION_CAM_BIST_STATUS_PIPE2 */ "", 21867 /* DST_COMPRESSION_CAM_BIST_STATUS_PIPE3 */ "", 21868 /* DST_COMPRESSION_CAM_DBGCTRL */ "DST_COMPRESSION_CAM_CONTROL", 21869 /* DST_COMPRESSION_CAM_DBGCTRL_PIPE0 */ "DST_COMPRESSION_CAM_CONTROL_PIPE0", 21870 /* DST_COMPRESSION_CAM_DBGCTRL_PIPE1 */ "DST_COMPRESSION_CAM_CONTROL_PIPE1", 21871 /* DST_COMPRESSION_CAM_DBGCTRL_PIPE2 */ "DST_COMPRESSION_CAM_CONTROL_PIPE2", 21872 /* DST_COMPRESSION_CAM_DBGCTRL_PIPE3 */ "DST_COMPRESSION_CAM_CONTROL_PIPE3", 21873 /* DST_COMPRESSION_RAM_DBGCTRL */ "DST_COMPRESSION_RAM_CONTROL", 21874 /* DST_COMPRESSION_RAM_DBGCTRL_PIPE0 */ "DST_COMPRESSION_RAM_CONTROL_PIPE0", 21875 /* DST_COMPRESSION_RAM_DBGCTRL_PIPE1 */ "DST_COMPRESSION_RAM_CONTROL_PIPE1", 21876 /* DST_COMPRESSION_RAM_DBGCTRL_PIPE2 */ "DST_COMPRESSION_RAM_CONTROL_PIPE2", 21877 /* DST_COMPRESSION_RAM_DBGCTRL_PIPE3 */ "DST_COMPRESSION_RAM_CONTROL_PIPE3", 21878 /* DYNAMIC_PORT_RECFG_VECTOR_CFG */ "", 21879 /* DYNAMIC_PORT_RECFG_VECTOR_CFG_29_00 */ "", 21880 /* DYNAMIC_PORT_RECFG_VECTOR_CFG_31_00 */ "", 21881 /* DYNAMIC_PORT_RECFG_VECTOR_CFG_41_32 */ "", 21882 /* DYNCELLCOUNT */ "", 21883 /* DYNCELLLIMIT */ "", 21884 /* DYNPKTCNTPORT */ "", 21885 /* DYNRESETLIMPORT */ "", 21886 /* DYNXQCNTPORT */ "", 21887 /* E2ECC_COS_CELL_STATE */ "", 21888 /* E2ECC_COS_CELL_STATE_0 */ "", 21889 /* E2ECC_COS_CELL_STATE_1 */ "", 21890 /* E2ECC_COS_CELL_STATE_2 */ "", 21891 /* E2ECC_COS_PKT_STATE */ "", 21892 /* E2ECC_COS_PKT_STATE_0 */ "", 21893 /* E2ECC_COS_PKT_STATE_1 */ "", 21894 /* E2ECC_COS_PKT_STATE_2 */ "", 21895 /* E2ECC_COS_STATE */ "", 21896 /* E2ECC_COS_STATE_0 */ "", 21897 /* E2ECC_COS_STATE_1 */ "", 21898 /* E2ECC_COS_STATE_2 */ "", 21899 /* E2ECC_HOL_EN */ "", 21900 /* E2ECC_HOL_PBM */ "", 21901 /* E2ECC_MAX_TX_TIMER */ "", 21902 /* E2ECC_MIN_TX_TIMER */ "", 21903 /* E2ECC_MODE */ "", 21904 /* E2ECC_PORT_CELL_STATE */ "", 21905 /* E2ECC_PORT_CELL_STATE_0 */ "", 21906 /* E2ECC_PORT_CELL_STATE_1 */ "", 21907 /* E2ECC_PORT_CELL_STATE_2 */ "", 21908 /* E2ECC_PORT_CONFIG */ "", 21909 /* E2ECC_PORT_MAPPING */ "", 21910 /* E2ECC_PORT_MAPPING_CONFIG */ "", 21911 /* E2ECC_PORT_PKT_STATE */ "", 21912 /* E2ECC_PORT_PKT_STATE_0 */ "", 21913 /* E2ECC_PORT_PKT_STATE_1 */ "", 21914 /* E2ECC_PORT_PKT_STATE_2 */ "", 21915 /* E2ECC_TX_ENABLE_BMP */ "", 21916 /* E2ECC_TX_MODE */ "", 21917 /* E2ECC_TX_PORTS_NUM */ "", 21918 /* E2ECONFIG */ "", 21919 /* E2EFCEMA_CNT_DISC_LIMIT */ "", 21920 /* E2EFCEMA_CNT_RESET_LIMIT */ "", 21921 /* E2EFCEMA_CNT_SET_LIMIT */ "", 21922 /* E2EFCEMA_CNT_VAL */ "", 21923 /* E2EFCEMA_TX_RMT_DISC0 */ "", 21924 /* E2EFCEMA_TX_RMT_DISC1 */ "", 21925 /* E2EFCEMA_TX_RMT_IBP0 */ "", 21926 /* E2EFCEMA_TX_RMT_IBP1 */ "", 21927 /* E2EFCEXT_CNT_DISC_LIMIT */ "", 21928 /* E2EFCEXT_CNT_RESET_LIMIT */ "", 21929 /* E2EFCEXT_CNT_SET_LIMIT */ "", 21930 /* E2EFCEXT_CNT_VAL */ "", 21931 /* E2EFCEXT_TX_RMT_DISC0 */ "", 21932 /* E2EFCEXT_TX_RMT_DISC1 */ "", 21933 /* E2EFCEXT_TX_RMT_IBP0 */ "", 21934 /* E2EFCEXT_TX_RMT_IBP1 */ "", 21935 /* E2EFCINT_CNT_DISC_LIMIT */ "", 21936 /* E2EFCINT_CNT_RESET_LIMIT */ "", 21937 /* E2EFCINT_CNT_SET_LIMIT */ "", 21938 /* E2EFCINT_CNT_VAL */ "", 21939 /* E2EFCINT_TX_RMT_DISC0 */ "", 21940 /* E2EFCINT_TX_RMT_DISC1 */ "", 21941 /* E2EFCINT_TX_RMT_IBP0 */ "", 21942 /* E2EFCINT_TX_RMT_IBP1 */ "", 21943 /* E2EFCQEN_CNT_DISC_LIMIT */ "", 21944 /* E2EFCQEN_CNT_RESET_LIMIT */ "", 21945 /* E2EFCQEN_CNT_SET_LIMIT */ "", 21946 /* E2EFCQEN_CNT_VAL */ "", 21947 /* E2EFCQEN_TX_RMT_DISC0 */ "", 21948 /* E2EFCQEN_TX_RMT_DISC1 */ "", 21949 /* E2EFCQEN_TX_RMT_IBP0 */ "", 21950 /* E2EFCQEN_TX_RMT_IBP1 */ "", 21951 /* E2EFCRQE_CNT_DISC_LIMIT */ "", 21952 /* E2EFCRQE_CNT_RESET_LIMIT */ "", 21953 /* E2EFCRQE_CNT_SET_LIMIT */ "", 21954 /* E2EFCRQE_CNT_VAL */ "", 21955 /* E2EFCRQE_TX_RMT_DISC0 */ "", 21956 /* E2EFCRQE_TX_RMT_DISC1 */ "", 21957 /* E2EFCRQE_TX_RMT_IBP0 */ "", 21958 /* E2EFCRQE_TX_RMT_IBP1 */ "", 21959 /* E2EFC_CNT_ATTR */ "", 21960 /* E2EFC_CNT_DISC_LIMIT */ "", 21961 /* E2EFC_CNT_RESET_LIMIT */ "", 21962 /* E2EFC_CNT_SET_LIMIT */ "", 21963 /* E2EFC_CNT_VAL */ "", 21964 /* E2EFC_CONFIG */ "", 21965 /* E2EFC_HG_MAX_TX_TIMER */ "", 21966 /* E2EFC_HG_MIN_TX_TIMER */ "", 21967 /* E2EFC_HIGIG_PORTS */ "", 21968 /* E2EFC_IBP_EN */ "", 21969 /* E2EFC_IBP_HG_RMOD */ "", 21970 /* E2EFC_MAX_TX_TIMER */ "", 21971 /* E2EFC_MEM_TM */ "", 21972 /* E2EFC_MIN_TX_TIMER */ "", 21973 /* E2EFC_PARITYERRORPTR */ "", 21974 /* E2EFC_PORT_MAPPING */ "", 21975 /* E2EFC_PORT_MAPPING_CONFIG */ "", 21976 /* E2EFC_RMOD_CFG */ "", 21977 /* E2EFC_RX_CNT */ "", 21978 /* E2EFC_RX_RMODID */ "", 21979 /* E2EFC_RX_RMODID_0 */ "", 21980 /* E2EFC_RX_RMODID_1 */ "", 21981 /* E2EFC_RX_RMODID_64 */ "E2EFC_RX_RMODID", 21982 /* E2EFC_RX_RMT_IBP0 */ "", 21983 /* E2EFC_RX_RMT_IBP1 */ "", 21984 /* E2EFC_RX_RMT_TIMEOUT */ "", 21985 /* E2EFC_TX_CNT */ "", 21986 /* E2EFC_TX_RMODID */ "", 21987 /* E2EFC_TX_RMODID_0 */ "", 21988 /* E2EFC_TX_RMODID_1 */ "", 21989 /* E2EFC_TX_RMODID_64 */ "E2EFC_TX_RMODID", 21990 /* E2EFC_TX_RMT_DISC0 */ "", 21991 /* E2EFC_TX_RMT_DISC1 */ "", 21992 /* E2EFC_TX_RMT_IBP0 */ "", 21993 /* E2EFC_TX_RMT_IBP1 */ "", 21994 /* E2EIBPBKPSTATUS */ "", 21995 /* E2EIBPCELLCOUNT */ "", 21996 /* E2EIBPCELLSETLIMIT */ "", 21997 /* E2EIBPDISCARDSETLIMIT */ "", 21998 /* E2EIBPDISCSTATUS */ "", 21999 /* E2EIBPPKTCOUNT */ "", 22000 /* E2EIBPPKTSETLIMIT */ "", 22001 /* E2E_CONTROL_FIELD */ "", 22002 /* E2E_DROP_COUNT */ "", 22003 /* E2E_DROP_COUNT_X */ "", 22004 /* E2E_DROP_COUNT_Y */ "", 22005 /* E2E_HOL_EN */ "", 22006 /* E2E_HOL_PBM */ "", 22007 /* E2E_HOL_RX_DA_LS */ "", 22008 /* E2E_HOL_RX_DA_MS */ "", 22009 /* E2E_HOL_RX_LENGTH_TYPE */ "", 22010 /* E2E_HOL_RX_OPCODE */ "", 22011 /* E2E_HOL_STATUS0_ECC_STATUS */ "", 22012 /* E2E_HOL_STATUS1_ECC_STATUS */ "", 22013 /* E2E_HOL_STATUS2_ECC_STATUS */ "", 22014 /* E2E_HOL_STATUS3_ECC_STATUS */ "", 22015 /* E2E_HOL_STATUS_1_PARITY_CONTROL */ "", 22016 /* E2E_HOL_STATUS_1_PARITY_STATUS_INTR */ "", 22017 /* E2E_HOL_STATUS_1_PARITY_STATUS_NACK */ "", 22018 /* E2E_HOL_STATUS_PARITY_CONTROL */ "", 22019 /* E2E_HOL_STATUS_PARITY_STATUS_INTR */ "", 22020 /* E2E_HOL_STATUS_PARITY_STATUS_NACK */ "", 22021 /* E2E_HOL_XBM */ "", 22022 /* E2E_IBP_RX_DA_LS */ "", 22023 /* E2E_IBP_RX_DA_MS */ "", 22024 /* E2E_IBP_RX_LENGTH_TYPE */ "", 22025 /* E2E_IBP_RX_OPCODE */ "", 22026 /* E2E_MAX_TX_TIMER */ "", 22027 /* E2E_MIN_TX_TIMER */ "", 22028 /* E2E_YELLOW_OFFSET_TABLE */ "", 22029 /* EARLY_DYNCELLLIMIT */ "", 22030 /* EARLY_HOLCOSCELLMAXLIMIT */ "", 22031 /* EARLY_PIPEMEM0_DEBUG */ "", 22032 /* EARLY_PIPEMEM0_DEBUG_XPE0 */ "", 22033 /* EARLY_PIPEMEM1_DEBUG */ "", 22034 /* EARLY_PIPEMEM1_DEBUG_XPE0 */ "", 22035 /* EARLY_PIPEMEM2_DEBUG */ "", 22036 /* EARLY_PIPEMEM2_DEBUG_XPE0 */ "", 22037 /* EARLY_PIPEMEM3_DEBUG */ "", 22038 /* EARLY_PIPEMEM3_DEBUG_XPE0 */ "", 22039 /* EARLY_PIPEMEMHI_DEBUG */ "", 22040 /* EARLY_PIPEMEMLO_DEBUG */ "", 22041 /* EAVBUCKETCONFIG_EXT */ "", 22042 /* EAVBUCKETCONFIG_EXT_QGROUP */ "", 22043 /* EAVBUCKETCONFIG_EXT_QLAYER */ "", 22044 /* EAV_ENABLE_BMAP */ "", 22045 /* EAV_MAXBUCKET_64 */ "EAV_MAXBUCKET", 22046 /* EAV_MAXBUCKET_24Q */ "", 22047 /* EAV_MINBUCKET_64 */ "EAV_MINBUCKET", 22048 /* EAV_MINBUCKET_24Q */ "", 22049 /* EBTOQ_DEBUG */ "", 22050 /* EBTOQ_ENQ_DEQ_EOP_PREFETCH_COLLISION_DEBUG */ "", 22051 /* EBTOQ_STATUS */ "", 22052 /* ECCP_1B_ERR_INT_CTR */ "", 22053 /* ECCP_1B_ERR_INT_STAT */ "", 22054 /* ECC_ADDR0 */ "", 22055 /* ECC_ADDR1 */ "", 22056 /* ECC_ADDR2 */ "", 22057 /* ECC_ADDR3 */ "", 22058 /* ECC_ADDR4 */ "", 22059 /* ECC_ADDR5 */ "", 22060 /* ECC_ADDR6 */ "", 22061 /* ECC_ADDR7 */ "", 22062 /* ECC_ADDR8 */ "", 22063 /* ECC_ADDR9 */ "", 22064 /* ECC_ADDR10 */ "", 22065 /* ECC_ADDR11 */ "", 22066 /* ECC_ADDR12 */ "", 22067 /* ECC_ADDR13 */ "", 22068 /* ECC_ADDR14 */ "", 22069 /* ECC_ADDR15 */ "", 22070 /* ECC_ADDR16 */ "", 22071 /* ECC_ADDR17 */ "", 22072 /* ECC_ADDR18 */ "", 22073 /* ECC_ADDR19 */ "", 22074 /* ECC_ADDR20 */ "", 22075 /* ECC_ADDR21 */ "", 22076 /* ECC_ADDR22 */ "", 22077 /* ECC_ADDR23 */ "", 22078 /* ECC_ADDR24 */ "", 22079 /* ECC_ADDR25 */ "", 22080 /* ECC_ADDR26 */ "", 22081 /* ECC_ADDR27 */ "", 22082 /* ECC_ADDR28 */ "", 22083 /* ECC_ADDR29 */ "", 22084 /* ECC_ADDR30 */ "", 22085 /* ECC_ADDR31 */ "", 22086 /* ECC_ADDR32 */ "", 22087 /* ECC_ADDR33 */ "", 22088 /* ECC_ADDR34 */ "", 22089 /* ECC_ADDR35 */ "", 22090 /* ECC_ADDR36 */ "", 22091 /* ECC_CONFIG0 */ "", 22092 /* ECC_CONFIG1 */ "", 22093 /* ECC_CONFIG2 */ "", 22094 /* ECC_CONFIG3 */ "", 22095 /* ECC_CONFIG4 */ "", 22096 /* ECC_CONFIG5 */ "", 22097 /* ECC_CONFIG6 */ "", 22098 /* ECC_CONFIG7 */ "", 22099 /* ECC_CONFIG8 */ "", 22100 /* ECC_CONFIG9 */ "", 22101 /* ECC_CONFIG10 */ "", 22102 /* ECC_CONFIG11 */ "", 22103 /* ECC_CONFIG12 */ "", 22104 /* ECC_CONFIG13 */ "", 22105 /* ECC_CONFIG14 */ "", 22106 /* ECC_CONFIG15 */ "", 22107 /* ECC_CONFIG16 */ "", 22108 /* ECC_CONFIG17 */ "", 22109 /* ECC_CONFIG18 */ "", 22110 /* ECC_CONFIG19 */ "", 22111 /* ECC_CONFIG20 */ "", 22112 /* ECC_CONFIG21 */ "", 22113 /* ECC_CONFIG22 */ "", 22114 /* ECC_CONFIG23 */ "", 22115 /* ECC_CONFIG24 */ "", 22116 /* ECC_CONFIG25 */ "", 22117 /* ECC_CONFIG26 */ "", 22118 /* ECC_CONFIG27 */ "", 22119 /* ECC_CONFIG28 */ "", 22120 /* ECC_CONFIG29 */ "", 22121 /* ECC_CONFIG30 */ "", 22122 /* ECC_CONFIG31 */ "", 22123 /* ECC_CONFIG32 */ "", 22124 /* ECC_CONFIG33 */ "", 22125 /* ECC_CONFIG34 */ "", 22126 /* ECC_CONFIG35 */ "", 22127 /* ECC_CONFIG36 */ "", 22128 /* ECC_CTLSTS_ECNTR */ "", 22129 /* ECC_CTLSTS_EMIB1 */ "", 22130 /* ECC_CTLSTS_EMIB2 */ "", 22131 /* ECC_CTLSTS_EPKTRAM */ "", 22132 /* ECC_CTLSTS_ESATBL0 */ "", 22133 /* ECC_CTLSTS_ESATBL1 */ "", 22134 /* ECC_CTLSTS_ESATBL2 */ "", 22135 /* ECC_CTLSTS_ESATBL3 */ "", 22136 /* ECC_CTLSTS_ESCTBL */ "", 22137 /* ECC_CTLSTS_ICNTR */ "", 22138 /* ECC_CTLSTS_IMGMTPKT */ "", 22139 /* ECC_CTLSTS_IMIB1 */ "", 22140 /* ECC_CTLSTS_IMIB2 */ "", 22141 /* ECC_CTLSTS_IMIB3 */ "", 22142 /* ECC_CTLSTS_IMIB1B */ "", 22143 /* ECC_CTLSTS_IPKTRAM */ "", 22144 /* ECC_CTLSTS_ISATBL */ "", 22145 /* ECC_CTLSTS_ISCTBL */ "", 22146 /* ECC_CTLSTS_ISPLUTBL */ "", 22147 /* ECC_CTLSTS_ISPPLTBL */ "", 22148 /* ECC_CTLSTS_OMGMTPKT */ "", 22149 /* ECC_CTLSTS_SCTCAMHIT */ "", 22150 /* ECC_CTLSTS_SPTCAMHIT */ "", 22151 /* ECC_DATA1 */ "", 22152 /* ECC_DATA12 */ "", 22153 /* ECC_DATA13 */ "", 22154 /* ECC_DATA14 */ "", 22155 /* ECC_DATA20 */ "", 22156 /* ECC_DATA24 */ "", 22157 /* ECC_DATA27 */ "", 22158 /* ECC_DATA28 */ "", 22159 /* ECC_DATA29 */ "", 22160 /* ECC_DATA30 */ "", 22161 /* ECC_DATA31 */ "", 22162 /* ECC_DATA33 */ "", 22163 /* ECC_ERROR0 */ "", 22164 /* ECC_ERROR1 */ "", 22165 /* ECC_ERROR2 */ "", 22166 /* ECC_ERROR3 */ "", 22167 /* ECC_ERROR4 */ "", 22168 /* ECC_ERROR0_MASK */ "", 22169 /* ECC_ERROR1_MASK */ "", 22170 /* ECC_ERROR2_MASK */ "", 22171 /* ECC_ERROR3_MASK */ "", 22172 /* ECC_ERROR4_MASK */ "", 22173 /* ECC_ERROR_SINGLE_BIT_ERROR_CNT */ "", 22174 /* ECC_ERR_PTR_CTR_EXT */ "", 22175 /* ECC_ERR_PTR_CTR_INT */ "", 22176 /* ECC_ERR_PTR_EXP_EXT */ "", 22177 /* ECC_ERR_PTR_EXP_INT */ "", 22178 /* ECC_ERR_PTR_LMT_EXT */ "", 22179 /* ECC_ERR_PTR_LMT_INT */ "", 22180 /* ECC_SINGLE_BIT_ERRORS */ "", 22181 /* ECGM_CGM_DB_TH_SP_OR_SHARED */ "", 22182 /* ECGM_CGM_DEBUG_COUNTERS */ "", 22183 /* ECGM_CGM_DISABLE_DISCARDS_TO_PQP */ "", 22184 /* ECGM_CGM_DISABLE_DISCARDS_TO_RQP */ "", 22185 /* ECGM_CGM_DP_ELIGIBLE_TO_USE_RESOURCES */ "", 22186 /* ECGM_CGM_DROP_CTR_PKT_OR_DB */ "", 22187 /* ECGM_CGM_DYN_TH_DEBUG */ "", 22188 /* ECGM_CGM_INIT_DONE */ "", 22189 /* ECGM_CGM_MAP_IF_2_TH */ "", 22190 /* ECGM_CGM_MAP_REPLICATION_FIFO_TO_TC */ "", 22191 /* ECGM_CGM_MAP_TC_TO_SP */ "", 22192 /* ECGM_CGM_MC_INTERFACE_MAP_TH */ "", 22193 /* ECGM_CGM_MC_INTERFACE_PD_TH */ "", 22194 /* ECGM_CGM_MC_PD_PER_PORT_DYN_TH_DEBUG */ "", 22195 /* ECGM_CGM_MC_PD_TC_FC_TH */ "", 22196 /* ECGM_CGM_PD_TH_SP_OR_SHARED */ "", 22197 /* ECGM_CGM_QUEUE_IS_DISABLED */ "", 22198 /* ECGM_CGM_QUEUE_PAIR_DISABLED */ "", 22199 /* ECGM_CGM_REP_AROUND_INTERRUPT_REGISTER */ "", 22200 /* ECGM_CGM_REP_AROUND_INTERRUPT_REGISTER_MASK */ "", 22201 /* ECGM_CGM_REP_AROUND_INTERRUPT_REGISTER_TEST */ "", 22202 /* ECGM_CGM_REP_AROUND_INT_REG_TEST */ "", 22203 /* ECGM_CGM_UC_PD_INTERFACE_FC_ALPHA */ "", 22204 /* ECGM_CGM_UC_PD_INTERFACE_FC_MAX_TH */ "", 22205 /* ECGM_CGM_UC_PD_INTERFACE_FC_MIN_TH */ "", 22206 /* ECGM_CGM_UC_SIZE_256_INTERFACE_FC_ALPHA */ "", 22207 /* ECGM_CGM_UC_SIZE_256_INTERFACE_FC_MAX_TH */ "", 22208 /* ECGM_CGM_UC_SIZE_256_INTERFACE_FC_MIN_TH */ "", 22209 /* ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_ALPHA */ "", 22210 /* ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_ALPHA_0 */ "", 22211 /* ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_ALPHA_1 */ "", 22212 /* ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_MAXIMUM_THRESHOLDS */ "", 22213 /* ECGM_CONGESTION_MANAGEMENT_DB_SERVICE_POOL_MINIMUM_THRESHOLDS */ "", 22214 /* ECGM_CONGESTION_MANAGEMENT_GLOBAL_DB_THRESHOLDS */ "", 22215 /* ECGM_CONGESTION_MANAGEMENT_GLOBAL_FLOW_CONTROL_THRESHOLDS */ "", 22216 /* ECGM_CONGESTION_MANAGEMENT_GLOBAL_PD_THRESHOLDS */ "", 22217 /* ECGM_CONGESTION_MANAGEMENT_MULTICAST_FLOW_CONTROL_PER_TC_THREHOSLDS */ "", 22218 /* ECGM_CONGESTION_MANAGEMENT_MULTICAST_RESERVED_RESOURCES */ "", 22219 /* ECGM_CONGESTION_MANAGEMENT_MULTICAST_RESERVED_RESOURCES_PER_CLASS */ "", 22220 /* ECGM_CONGESTION_MANAGEMENT_PD_SERVICE_POOL_THRESHOLDS */ "", 22221 /* ECGM_CONGESTION_TRACKING_MULTICAST_DBSP_0_MAX_VALUE */ "", 22222 /* ECGM_CONGESTION_TRACKING_MULTICAST_DBSP_1_MAX_VALUE */ "", 22223 /* ECGM_CONGESTION_TRACKING_MULTICAST_DB_MAX_VALUE */ "", 22224 /* ECGM_CONGESTION_TRACKING_MULTICAST_D_BPER_SP_TC_MAX_VALUE */ "", 22225 /* ECGM_CONGESTION_TRACKING_MULTICAST_PDSP_0_MAX_VALUE */ "", 22226 /* ECGM_CONGESTION_TRACKING_MULTICAST_PDSP_1_MAX_VALUE */ "", 22227 /* ECGM_CONGESTION_TRACKING_MULTICAST_PD_MAX_VALUE */ "", 22228 /* ECGM_CONGESTION_TRACKING_MULTICAST_P_DPER_SP_TC_MAX_VALUE */ "", 22229 /* ECGM_CONGESTION_TRACKING_TOTAL_DB_MAX_VALUE */ "", 22230 /* ECGM_CONGESTION_TRACKING_TOTAL_PD_MAX_VALUE */ "", 22231 /* ECGM_CONGESTION_TRACKING_UNICAST_DB_MAX_VALUE */ "", 22232 /* ECGM_CONGESTION_TRACKING_UNICAST_PD_MAX_VALUE */ "", 22233 /* ECGM_CRPS_PP_1_PQP_DROP_REASONS_MASK */ "", 22234 /* ECGM_CRPS_PP_2_PQP_DROP_REASONS_MASK */ "", 22235 /* ECGM_CRPS_TM_PQP_DROP_REASONS_MASK */ "", 22236 /* ECGM_DUMMY_REG */ "", 22237 /* ECGM_ECC_1B_ERR_CNT */ "", 22238 /* ECGM_ECC_2B_ERR_CNT */ "", 22239 /* ECGM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 22240 /* ECGM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 22241 /* ECGM_ECC_INTERRUPT_REGISTER */ "", 22242 /* ECGM_ECC_INTERRUPT_REGISTER_MASK */ "", 22243 /* ECGM_ECC_INTERRUPT_REGISTER_TEST */ "", 22244 /* ECGM_EGQ_2_SCH_GLOBAL_FC */ "", 22245 /* ECGM_EGQ_2_SCH_INTERFACE_FC */ "", 22246 /* ECGM_EGQ_2_SCH_PORT_FC */ "", 22247 /* ECGM_EGQ_2_SCH_PORT_FC_CFG */ "", 22248 /* ECGM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 22249 /* ECGM_ERROR_INITIATION_DATA */ "", 22250 /* ECGM_GTIMER_CONFIGURATION */ "", 22251 /* ECGM_GTIMER_CYCLE */ "", 22252 /* ECGM_INDIRECT_COMMAND */ "", 22253 /* ECGM_INDIRECT_COMMAND_ADDRESS */ "", 22254 /* ECGM_INDIRECT_COMMAND_RD_DATA */ "", 22255 /* ECGM_INDIRECT_COMMAND_WR_DATA */ "", 22256 /* ECGM_INDIRECT_FORCE_BUBBLE */ "", 22257 /* ECGM_INTERRUPT_MASK_REGISTER */ "", 22258 /* ECGM_INTERRUPT_REGISTER */ "", 22259 /* ECGM_INTERRUPT_REGISTER_TEST */ "", 22260 /* ECGM_MC_DB_SP_TC_CNT */ "", 22261 /* ECGM_MC_PD_SP_TC_CNT */ "", 22262 /* ECGM_MULTICAST_DATA_BUFFERS_COUNTER */ "", 22263 /* ECGM_MULTICAST_DATA_BUFFERS_DROP_COUNTER */ "", 22264 /* ECGM_MULTICAST_REPLICATIONS_PACKET_DESCRIPTORS_COUNTER */ "", 22265 /* ECGM_MULTICAST_REPLICATIONS_PACKET_DESCRIPTORS_DROP_COUNTER */ "", 22266 /* ECGM_MULTICAST_REPLICATIONS_QUEUE_LENGTH_DROP_COUNTER */ "", 22267 /* ECGM_PQP_DISCARD_REASONS */ "", 22268 /* ECGM_REG_0041 */ "", 22269 /* ECGM_REG_00A4 */ "", 22270 /* ECGM_REG_00A6 */ "", 22271 /* ECGM_REG_00C2 */ "", 22272 /* ECGM_REG_00C5 */ "", 22273 /* ECGM_RESERVED_MIRROR_ADDR */ "", 22274 /* ECGM_RESERVED_MTCD */ "", 22275 /* ECGM_RESERVED_MTCP */ "", 22276 /* ECGM_RESERVED_SPARE_0 */ "", 22277 /* ECGM_RESERVED_SPARE_1 */ "", 22278 /* ECGM_RESERVED_SPARE_2 */ "", 22279 /* ECGM_RESERVED_SPARE_3 */ "", 22280 /* ECGM_RQP_DISCARD_REASONS */ "", 22281 /* ECGM_SBUS_BROADCAST_ID */ "", 22282 /* ECGM_SBUS_LAST_IN_CHAIN */ "", 22283 /* ECGM_SERVICE_POOL_0_MULTICAST_DATA_BUFFERS_COUNTER */ "", 22284 /* ECGM_SERVICE_POOL_0_MULTICAST_PACKET_DESCRIPTORS_COUNTER */ "", 22285 /* ECGM_SERVICE_POOL_0_RESERVED_DATA_BUFFERS */ "", 22286 /* ECGM_SERVICE_POOL_0_RESERVED_PACKET_DESCRIPTORS */ "", 22287 /* ECGM_SERVICE_POOL_1_MULTICAST_DATA_BUFFERS_COUNTER */ "", 22288 /* ECGM_SERVICE_POOL_1_MULTICAST_PACKET_DESCRIPTORS_COUNTER */ "", 22289 /* ECGM_SERVICE_POOL_1_RESERVED_DATA_BUFFERS */ "", 22290 /* ECGM_SERVICE_POOL_1_RESERVED_PACKET_DESCRIPTORS */ "", 22291 /* ECGM_SPECIAL_CLOCK_CONTROLS */ "", 22292 /* ECGM_STATISTICS_TRACKING_CONTROL */ "", 22293 /* ECGM_TOTAL_DATA_BUFFERS_COUNTER */ "", 22294 /* ECGM_TOTAL_PACKET_DESCRIPTORS_COUNTER */ "", 22295 /* ECGM_UNICAST_DATA_BUFFERS_COUNTER */ "", 22296 /* ECGM_UNICAST_DATA_BUFFERS_DROP_BY_PQP_COUNTER */ "", 22297 /* ECGM_UNICAST_DATA_BUFFERS_DROP_BY_RQP_COUNTER */ "", 22298 /* ECGM_UNICAST_PACKET_DESCRIPTORS_COUNTER */ "", 22299 /* ECGM_UNICAST_PACKET_DESCRIPTORS_DROP_COUNTER */ "", 22300 /* ECHCTL_CHID_0 */ "", 22301 /* ECHCTL_CHID_1 */ "", 22302 /* ECHCTL_CHID_2 */ "", 22303 /* ECHCTL_CHID_3 */ "", 22304 /* ECHCTL_CHID_4 */ "", 22305 /* ECHCTL_CHID_5 */ "", 22306 /* ECHCTL_CHID_6 */ "", 22307 /* ECHCTL_CHID_7 */ "", 22308 /* ECHCTL_CHID_8 */ "", 22309 /* ECHCTL_CHID_9 */ "", 22310 /* ECHCTL_CHID_10 */ "", 22311 /* ECHCTL_CHID_11 */ "", 22312 /* ECHCTL_CHID_12 */ "", 22313 /* ECHCTL_CHID_13 */ "", 22314 /* ECHCTL_CHID_14 */ "", 22315 /* ECHCTL_CHID_15 */ "", 22316 /* ECHCTL_CHID_16 */ "", 22317 /* ECHCTL_CHID_17 */ "", 22318 /* ECHCTL_CHID_18 */ "", 22319 /* ECHCTL_CHID_19 */ "", 22320 /* ECHCTL_CHID_20 */ "", 22321 /* ECHCTL_CHID_21 */ "", 22322 /* ECHCTL_CHID_22 */ "", 22323 /* ECHCTL_CHID_23 */ "", 22324 /* ECHCTL_CHID_24 */ "", 22325 /* ECHCTL_CHID_25 */ "", 22326 /* ECHCTL_CHID_26 */ "", 22327 /* ECHCTL_CHID_27 */ "", 22328 /* ECHCTL_CHID_28 */ "", 22329 /* ECHCTL_CHID_29 */ "", 22330 /* ECHCTL_CHID_30 */ "", 22331 /* ECHCTL_CHID_31 */ "", 22332 /* ECHCTL_CHID_32 */ "", 22333 /* ECHCTL_CHID_33 */ "", 22334 /* ECHCTL_CHID_34 */ "", 22335 /* ECHCTL_CHID_35 */ "", 22336 /* ECHCTL_CHID_36 */ "", 22337 /* ECHCTL_CHID_37 */ "", 22338 /* ECHCTL_CHID_38 */ "", 22339 /* ECHCTL_CHID_39 */ "", 22340 /* ECHCTL_CHID_40 */ "", 22341 /* ECHCTL_CHID_41 */ "", 22342 /* ECHCTL_CHID_42 */ "", 22343 /* ECHCTL_CHID_43 */ "", 22344 /* ECHCTL_CHID_44 */ "", 22345 /* ECHCTL_CHID_45 */ "", 22346 /* ECHCTL_CHID_46 */ "", 22347 /* ECHCTL_CHID_47 */ "", 22348 /* ECHCTL_CHID_48 */ "", 22349 /* ECHCTL_CHID_49 */ "", 22350 /* ECHCTL_CHID_50 */ "", 22351 /* ECHCTL_CHID_51 */ "", 22352 /* ECHCTL_CHID_52 */ "", 22353 /* ECHCTL_CHID_53 */ "", 22354 /* ECHCTL_CHID_54 */ "", 22355 /* ECHCTL_CHID_55 */ "", 22356 /* ECHCTL_CHID_56 */ "", 22357 /* ECHCTL_CHID_57 */ "", 22358 /* ECHCTL_CHID_58 */ "", 22359 /* ECHCTL_CHID_59 */ "", 22360 /* ECHCTL_CHID_60 */ "", 22361 /* ECHCTL_CHID_61 */ "", 22362 /* ECHCTL_CHID_62 */ "", 22363 /* ECHCTL_CHID_63 */ "", 22364 /* ECI_AUTO_DOC_NAME_2 */ "", 22365 /* ECI_AUTO_DOC_NAME_3 */ "", 22366 /* ECI_AUTO_DOC_NAME_4 */ "", 22367 /* ECI_AUTO_DOC_NAME_5 */ "", 22368 /* ECI_AUTO_DOC_NAME_6 */ "", 22369 /* ECI_AUTO_DOC_NAME_7 */ "", 22370 /* ECI_AUTO_DOC_NAME_8 */ "", 22371 /* ECI_AUTO_DOC_NAME_9 */ "", 22372 /* ECI_AUTO_DOC_NAME_10 */ "", 22373 /* ECI_AUTO_DOC_NAME_11 */ "", 22374 /* ECI_AUTO_DOC_NAME_12 */ "", 22375 /* ECI_AUTO_DOC_NAME_13 */ "", 22376 /* ECI_AUTO_DOC_NAME_14 */ "", 22377 /* ECI_AUTO_DOC_NAME_15 */ "", 22378 /* ECI_AUTO_DOC_NAME_16 */ "", 22379 /* ECI_AUTO_DOC_NAME_17 */ "", 22380 /* ECI_AUTO_DOC_NAME_19 */ "", 22381 /* ECI_AUTO_DOC_NAME_20 */ "", 22382 /* ECI_AUTO_DOC_NAME_21 */ "", 22383 /* ECI_AUTO_DOC_NAME_29 */ "", 22384 /* ECI_AUTO_DOC_NAME_30 */ "", 22385 /* ECI_AUTO_DOC_NAME_31 */ "", 22386 /* ECI_AUTO_DOC_NAME_32 */ "", 22387 /* ECI_AUTO_DOC_NAME_33 */ "", 22388 /* ECI_AUTO_DOC_NAME_34 */ "", 22389 /* ECI_AUTO_DOC_NAME_35 */ "", 22390 /* ECI_AUTO_DOC_NAME_36 */ "", 22391 /* ECI_AUTO_DOC_NAME_37 */ "", 22392 /* ECI_AUTO_DOC_NAME_38 */ "", 22393 /* ECI_AUTO_DOC_NAME_39 */ "", 22394 /* ECI_AUTO_DOC_NAME_40 */ "", 22395 /* ECI_AUTO_DOC_NAME_41 */ "", 22396 /* ECI_AUTO_DOC_NAME_43 */ "", 22397 /* ECI_AUTO_DOC_NAME_44 */ "", 22398 /* ECI_AUTO_DOC_NAME_45 */ "", 22399 /* ECI_AUTO_DOC_NAME_46 */ "", 22400 /* ECI_AUTO_DOC_NAME_47 */ "", 22401 /* ECI_AVS */ "", 22402 /* ECI_AVS_STATUS */ "", 22403 /* ECI_AVS_TOP_CTRL */ "", 22404 /* ECI_BIST_ENABLES */ "", 22405 /* ECI_BLH_INIT */ "", 22406 /* ECI_BLOCKS_INTERRUPT */ "", 22407 /* ECI_BLOCKS_POWER_DOWN */ "", 22408 /* ECI_BLOCKS_SBUS_RESET */ "", 22409 /* ECI_BLOCKS_SB_RST */ "", 22410 /* ECI_BLOCKS_SOFT_INIT */ "", 22411 /* ECI_BLOCKS_SOFT_RESET */ "", 22412 /* ECI_BLOCK_RESET_1 */ "", 22413 /* ECI_BOND_STATUS */ "", 22414 /* ECI_BROAD_VIEW_CTRL */ "", 22415 /* ECI_BS_0_PLL_CONFIG */ "", 22416 /* ECI_BS_0_PLL_STATUS */ "", 22417 /* ECI_BS_1_PLL_CONFIG */ "", 22418 /* ECI_BS_1_PLL_STATUS */ "", 22419 /* ECI_BS_PLL_CONFIG */ "", 22420 /* ECI_BS_PLL_CONFIGURATIONS */ "", 22421 /* ECI_BS_PLL_STATUS */ "", 22422 /* ECI_CDU_INSTRUMENTATION_CTRL */ "", 22423 /* ECI_CGM_INST_CTRL */ "", 22424 /* ECI_CMICM_STRAP_CONFIG */ "", 22425 /* ECI_CMIC_STRAP_CONFIG */ "", 22426 /* ECI_CMIC_TS_CLK */ "", 22427 /* ECI_CM_PLL_CONFIG */ "", 22428 /* ECI_CORE_FREQUENCY_VALUE */ "", 22429 /* ECI_CORE_PLL_STATUS */ "", 22430 /* ECI_COUNT_CTRL */ "", 22431 /* ECI_COUNT_MAX */ "", 22432 /* ECI_COUNT_STATUS */ "", 22433 /* ECI_CPU_CHANNEL_CONFIGURATION */ "", 22434 /* ECI_CPU_CHANNEL_PIPE_MAP */ "", 22435 /* ECI_CRPS_INSTRUMENTATION_CTRL */ "", 22436 /* ECI_CRPS_SELECT_TIME_OF_DAY_SOURCE */ "", 22437 /* ECI_DBG_LAST_EVENT_NUM */ "", 22438 /* ECI_DDR_0_PLL_CONFIG */ "", 22439 /* ECI_DDR_0_PLL_STATUS */ "", 22440 /* ECI_DDR_1_PLL_CONFIG */ "", 22441 /* ECI_DDR_1_PLL_STATUS */ "", 22442 /* ECI_DDR_2_PLL_CONFIG */ "", 22443 /* ECI_DDR_2_PLL_STATUS */ "", 22444 /* ECI_DDR_3_PLL_CONFIG */ "", 22445 /* ECI_DDR_3_PLL_STATUS */ "", 22446 /* ECI_DPRC_PLL_LOCK */ "", 22447 /* ECI_DRC_0_MDATA */ "", 22448 /* ECI_DRC_1_MDATA */ "", 22449 /* ECI_DRC_2_MDATA */ "", 22450 /* ECI_DRC_3_MDATA */ "", 22451 /* ECI_DRC_4_MDATA */ "", 22452 /* ECI_DRC_BIST */ "", 22453 /* ECI_DRC_BIST_ENABLES */ "", 22454 /* ECI_DRC_RESET */ "", 22455 /* ECI_DRC_SB_RST */ "", 22456 /* ECI_DRC_SOFT_INIT */ "", 22457 /* ECI_ECC_1B_ERR_CNT */ "", 22458 /* ECI_ECC_2B_ERR_CNT */ "", 22459 /* ECI_ECC_ERR_1B_INITIATE */ "", 22460 /* ECI_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 22461 /* ECI_ECC_ERR_2B_INITIATE */ "", 22462 /* ECI_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 22463 /* ECI_ECC_ERR_MONITOR_MEM_MASK */ "", 22464 /* ECI_ECC_INTERRUPT_REGISTER */ "", 22465 /* ECI_ECC_INTERRUPT_REGISTER_MASK */ "", 22466 /* ECI_ECC_INTERRUPT_REGISTER_TEST */ "", 22467 /* ECI_ECIC_BLOCKS_RESET */ "", 22468 /* ECI_ECIC_MDIO_CONFIG */ "", 22469 /* ECI_ECIC_MISC_RESET */ "", 22470 /* ECI_ECI_FIFO_CONFIG */ "", 22471 /* ECI_ECI_INTERNAL_INTERRUPT_MASK_REGISTER */ "", 22472 /* ECI_ECI_INTERNAL_INTERRUPT_REGISTER */ "", 22473 /* ECI_ECI_INTERRUPTS */ "", 22474 /* ECI_ECI_INTERRUPTS_MASK */ "", 22475 /* ECI_ECI_PIR_DEBUG_REGISTER */ "", 22476 /* ECI_ECI_REGISTER_0 */ "", 22477 /* ECI_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 22478 /* ECI_EPNI_0_PKT_WRITTEN */ "", 22479 /* ECI_EPNI_1_PKT_WRITTEN */ "", 22480 /* ECI_ERROR_INITIATION_DATA */ "", 22481 /* ECI_FAB_0_PLL_CONFIG */ "", 22482 /* ECI_FAB_0_PLL_CONFIGURATIONS */ "", 22483 /* ECI_FAB_0_PLL_STATUS */ "", 22484 /* ECI_FAB_1_PLL_CONFIG */ "", 22485 /* ECI_FAB_1_PLL_CONFIGURATIONS */ "", 22486 /* ECI_FAB_1_PLL_STATUS */ "", 22487 /* ECI_FAP_GLOBAL_GENERAL_CFG_1 */ "", 22488 /* ECI_FAP_GLOBAL_GENERAL_CFG_2 */ "", 22489 /* ECI_FAP_GLOBAL_GENERAL_CFG_3 */ "", 22490 /* ECI_FAP_GLOBAL_GENERAL_IDB */ "", 22491 /* ECI_FAP_GLOBAL_PP_1 */ "", 22492 /* ECI_FAP_GLOBAL_PP_2 */ "", 22493 /* ECI_FAP_GLOBAL_PP_3 */ "", 22494 /* ECI_FAP_GLOBAL_PP_4 */ "", 22495 /* ECI_FAP_GLOBAL_PP_5 */ "", 22496 /* ECI_FAP_GLOBAL_PP_6 */ "", 22497 /* ECI_FAP_GLOBAL_PP_7 */ "", 22498 /* ECI_FAP_GLOBAL_PP_8 */ "", 22499 /* ECI_FAP_GLOBAL_PP_9 */ "", 22500 /* ECI_FAP_GLOBAL_PP_10 */ "", 22501 /* ECI_FAP_GLOBAL_PP_11 */ "", 22502 /* ECI_FAP_GLOBAL_PP_12 */ "", 22503 /* ECI_FAP_GLOBAL_SYS_HEADER_CFG */ "", 22504 /* ECI_FE_1600_SOFT_INIT */ "", 22505 /* ECI_FE_1600_SOFT_RESET */ "", 22506 /* ECI_FE_GLOBAL_DCH_CAPTURE_CELLS_DCML */ "", 22507 /* ECI_FE_GLOBAL_FE_DEST_IDS_1 */ "", 22508 /* ECI_FE_GLOBAL_FE_DEST_IDS_2 */ "", 22509 /* ECI_FE_GLOBAL_FE_DEST_IDS_3 */ "", 22510 /* ECI_FE_GLOBAL_FE_DEST_IDS_4 */ "", 22511 /* ECI_FE_GLOBAL_GENERAL_CFG_1 */ "", 22512 /* ECI_FE_GLOBAL_GENERAL_CFG_2 */ "", 22513 /* ECI_FGL_EGRESS_CONFIG */ "", 22514 /* ECI_FGL_EGRESS_COUNTERS */ "", 22515 /* ECI_FGL_EGR_2_ING_LOOPBACK_CONTROL */ "", 22516 /* ECI_FGL_EGR_MC_CONTROL */ "", 22517 /* ECI_FGL_INGRESS_CONFIG */ "", 22518 /* ECI_FGL_INGRESS_COUNTERS */ "", 22519 /* ECI_FGL_INGRESS_TDM_CONTEXT_DROP */ "", 22520 /* ECI_FGL_LOOPBACK_CONTROL */ "", 22521 /* ECI_FIFO_DMA_SEL */ "", 22522 /* ECI_FMAC_GRACEFULL_POWER_UP_AND_DOWN */ "", 22523 /* ECI_FMAC_GRACEFUL_POWER_UP_AND_DOWN */ "", 22524 /* ECI_FR_CLK_DIV_CONTROL */ "", 22525 /* ECI_GENERAL_CONFIGURATION_1 */ "", 22526 /* ECI_GENERAL_CONFIGURATION_2 */ "", 22527 /* ECI_GLOBALA */ "", 22528 /* ECI_GLOBALB */ "", 22529 /* ECI_GLOBALC */ "", 22530 /* ECI_GLOBALD */ "", 22531 /* ECI_GLOBALE */ "", 22532 /* ECI_GLOBALF */ "", 22533 /* ECI_GLOBAL_0 */ "", 22534 /* ECI_GLOBAL_1 */ "", 22535 /* ECI_GLOBAL_2 */ "", 22536 /* ECI_GLOBAL_3 */ "", 22537 /* ECI_GLOBAL_4 */ "", 22538 /* ECI_GLOBAL_5 */ "", 22539 /* ECI_GLOBAL_6 */ "", 22540 /* ECI_GLOBAL_7 */ "", 22541 /* ECI_GLOBAL_8 */ "", 22542 /* ECI_GLOBAL_9 */ "", 22543 /* ECI_GLOBAL_10 */ "", 22544 /* ECI_GLOBAL_12 */ "", 22545 /* ECI_GLOBAL_13 */ "", 22546 /* ECI_GLOBAL_14 */ "", 22547 /* ECI_GLOBAL_15 */ "", 22548 /* ECI_GLOBAL_16 */ "", 22549 /* ECI_GLOBAL_17 */ "", 22550 /* ECI_GLOBAL_18 */ "", 22551 /* ECI_GLOBAL_19 */ "", 22552 /* ECI_GLOBAL_1_A */ "", 22553 /* ECI_GLOBAL_1_B */ "", 22554 /* ECI_GLOBAL_ADDR_TRANS_CFG */ "", 22555 /* ECI_GLOBAL_DCH_CAPTURE_CELLS_DCL */ "", 22556 /* ECI_GLOBAL_DQCQ_MAP_CFG_1 */ "", 22557 /* ECI_GLOBAL_DQCQ_MAP_CFG_2 */ "", 22558 /* ECI_GLOBAL_DRAM_NUMBER_SWAPPING */ "", 22559 /* ECI_GLOBAL_FE_DEST_IDS_1 */ "", 22560 /* ECI_GLOBAL_FE_DEST_IDS_2 */ "", 22561 /* ECI_GLOBAL_FMC_0 */ "", 22562 /* ECI_GLOBAL_FMC_1 */ "", 22563 /* ECI_GLOBAL_FULL_MC_DB_RANGE_0 */ "", 22564 /* ECI_GLOBAL_FULL_MC_DB_RANGE_1 */ "", 22565 /* ECI_GLOBAL_GENERAL_CFG_1 */ "", 22566 /* ECI_GLOBAL_GENERAL_CFG_2 */ "", 22567 /* ECI_GLOBAL_GENERAL_CFG_3 */ "", 22568 /* ECI_GLOBAL_GENERAL_CFG_4 */ "", 22569 /* ECI_GLOBAL_GENERAL_FE_CFG_1 */ "", 22570 /* ECI_GLOBAL_INGRESS_MULTICAST_INDICATION */ "", 22571 /* ECI_GLOBAL_ISP_0 */ "", 22572 /* ECI_GLOBAL_ISP_1 */ "", 22573 /* ECI_GLOBAL_MEM_OPTIONS */ "", 22574 /* ECI_GLOBAL_MINI_MC_DB_RANGE_0 */ "", 22575 /* ECI_GLOBAL_MINI_MC_DB_RANGE_1 */ "", 22576 /* ECI_GLOBAL_OCB_BANK_RANGE */ "", 22577 /* ECI_GLOBAL_OCB_BUF_RANGE_0 */ "", 22578 /* ECI_GLOBAL_OCB_BUF_RANGE_1 */ "", 22579 /* ECI_GLOBAL_ONE_PLUS_ONE_PORT_PROTECTION */ "", 22580 /* ECI_GLOBAL_PP_1 */ "", 22581 /* ECI_GLOBAL_PP_2 */ "", 22582 /* ECI_GLOBAL_PP_3 */ "", 22583 /* ECI_GLOBAL_PP_4 */ "", 22584 /* ECI_GLOBAL_PP_5 */ "", 22585 /* ECI_GLOBAL_PP_6 */ "", 22586 /* ECI_GLOBAL_PP_7 */ "", 22587 /* ECI_GLOBAL_PP_8 */ "", 22588 /* ECI_GLOBAL_SYS_HEADER_CFG */ "", 22589 /* ECI_GPIO_TS_SEL */ "", 22590 /* ECI_GP_CONTROL_0 */ "", 22591 /* ECI_GP_CONTROL_1 */ "", 22592 /* ECI_GP_CONTROL_2 */ "", 22593 /* ECI_GP_CONTROL_3 */ "", 22594 /* ECI_GP_CONTROL_4 */ "", 22595 /* ECI_GP_CONTROL_5 */ "", 22596 /* ECI_GP_CONTROL_6 */ "", 22597 /* ECI_GP_CONTROL_7 */ "", 22598 /* ECI_GP_CONTROL_8 */ "", 22599 /* ECI_GP_CONTROL_9 */ "", 22600 /* ECI_GP_CONTROL_10 */ "", 22601 /* ECI_GP_CONTROL_11 */ "", 22602 /* ECI_GP_COUNTER_0 */ "", 22603 /* ECI_GP_COUNTER_1 */ "", 22604 /* ECI_GP_COUNTER_2 */ "", 22605 /* ECI_GP_COUNTER_3 */ "", 22606 /* ECI_GP_STATUS_0 */ "", 22607 /* ECI_GP_STATUS_1 */ "", 22608 /* ECI_GP_STATUS_2 */ "", 22609 /* ECI_GP_STATUS_3 */ "", 22610 /* ECI_GP_STATUS_4 */ "", 22611 /* ECI_GP_STATUS_5 */ "", 22612 /* ECI_GP_STATUS_6 */ "", 22613 /* ECI_GP_STATUS_7 */ "", 22614 /* ECI_GTIMER_CONFIGURATION */ "", 22615 /* ECI_GTIMER_CYCLE */ "", 22616 /* ECI_GTIMER_TRIGGER */ "", 22617 /* ECI_INDIRECT_COMMAND */ "", 22618 /* ECI_INDIRECT_COMMAND_ADDRESS */ "", 22619 /* ECI_INDIRECT_COMMAND_DATA_INCREMENT */ "", 22620 /* ECI_INDIRECT_COMMAND_RD_DATA */ "", 22621 /* ECI_INDIRECT_COMMAND_WIDE_MEM */ "", 22622 /* ECI_INDIRECT_COMMAND_WR_DATA */ "", 22623 /* ECI_INDIRECT_FORCE_BUBBLE */ "", 22624 /* ECI_INTERRUPT_FORCE_ECI_REGISTER */ "", 22625 /* ECI_INTERRUPT_FORCE_REGISTER */ "", 22626 /* ECI_INTERRUPT_MASK_REGISTER */ "", 22627 /* ECI_INTERRUPT_REGISTER */ "", 22628 /* ECI_INTERRUPT_REGISTER_TEST */ "", 22629 /* ECI_IPROC_STRAP_CONFIG */ "", 22630 /* ECI_MAC_INTERRUPT_MASK_REGISTER */ "", 22631 /* ECI_MAC_INTERRUPT_REGISTER */ "", 22632 /* ECI_MASTER_SYNCE_PLL_STATUS */ "", 22633 /* ECI_MBIST_TEST_PORTS */ "", 22634 /* ECI_MDIO_CNTL_1 */ "", 22635 /* ECI_MDIO_CNTL_4 */ "", 22636 /* ECI_MDIO_CNTL_5 */ "", 22637 /* ECI_MDIO_CNTL_6 */ "", 22638 /* ECI_MDIO_CNTL_7 */ "", 22639 /* ECI_MDIO_CNTL_8 */ "", 22640 /* ECI_MDIO_CNTL_9 */ "", 22641 /* ECI_MDIO_CNTL_10 */ "", 22642 /* ECI_MDIO_CNTL_11 */ "", 22643 /* ECI_MDIO_CNTL_12 */ "", 22644 /* ECI_MDIO_CNTL_15 */ "", 22645 /* ECI_MDIO_CNTL_16 */ "", 22646 /* ECI_MDIO_CNTL_17 */ "", 22647 /* ECI_MDIO_CNTL_18 */ "", 22648 /* ECI_MDIO_ST_CONFIG */ "", 22649 /* ECI_MEMORY_START_ADDRESS */ "", 22650 /* ECI_MET_MON */ "", 22651 /* ECI_MIRROR_DATA_REGISTER */ "", 22652 /* ECI_MISC_PLL_0_CONFIG */ "", 22653 /* ECI_MISC_PLL_0_STATUS */ "", 22654 /* ECI_MISC_PLL_1_CONFIG */ "", 22655 /* ECI_MISC_PLL_1_STATUS */ "", 22656 /* ECI_MISC_PLL_2_CONFIG */ "", 22657 /* ECI_MISC_PLL_2_STATUS */ "", 22658 /* ECI_MISC_PLL_3_CONFIG */ "", 22659 /* ECI_MISC_PLL_3_STATUS */ "", 22660 /* ECI_MISC_PLL_4_CONFIG */ "", 22661 /* ECI_MISC_PLL_4_STATUS */ "", 22662 /* ECI_MISC_PLL_5_CONFIG */ "", 22663 /* ECI_MISC_PLL_5_STATUS */ "", 22664 /* ECI_MISC_PLL_6_CONFIG */ "", 22665 /* ECI_MISC_PLL_6_STATUS */ "", 22666 /* ECI_MISC_PLL_7_CONFIG */ "", 22667 /* ECI_MISC_PLL_7_STATUS */ "", 22668 /* ECI_MISC_PLL_8_CONFIG */ "", 22669 /* ECI_MISC_PLL_8_STATUS */ "", 22670 /* ECI_MISC_PLL_9_CONFIG */ "", 22671 /* ECI_MISC_PLL_9_STATUS */ "", 22672 /* ECI_MMU_0_PRBS_STATUS */ "", 22673 /* ECI_MMU_0_READ_DATA_LSB */ "", 22674 /* ECI_MMU_0_READ_DATA_MSB */ "", 22675 /* ECI_MMU_0_READ_DATA_VALID */ "", 22676 /* ECI_MMU_1_PRBS_STATUS */ "", 22677 /* ECI_MMU_1_READ_DATA_LSB */ "", 22678 /* ECI_MMU_1_READ_DATA_MSB */ "", 22679 /* ECI_MMU_1_READ_DATA_VALID */ "", 22680 /* ECI_MMU_2_PRBS_STATUS */ "", 22681 /* ECI_MMU_2_READ_DATA_LSB */ "", 22682 /* ECI_MMU_2_READ_DATA_MSB */ "", 22683 /* ECI_MMU_2_READ_DATA_VALID */ "", 22684 /* ECI_MMU_3_PRBS_STATUS */ "", 22685 /* ECI_MMU_3_READ_DATA_LSB */ "", 22686 /* ECI_MMU_3_READ_DATA_MSB */ "", 22687 /* ECI_MMU_3_READ_DATA_VALID */ "", 22688 /* ECI_MMU_4_PRBS_STATUS */ "", 22689 /* ECI_MMU_4_READ_DATA_LSB */ "", 22690 /* ECI_MMU_4_READ_DATA_MSB */ "", 22691 /* ECI_MMU_4_READ_DATA_VALID */ "", 22692 /* ECI_MMU_COMMAND */ "", 22693 /* ECI_MMU_COMMAND_DATA_LSB */ "", 22694 /* ECI_MMU_COMMAND_DATA_MSB */ "", 22695 /* ECI_MMU_PRBS_CTRL */ "", 22696 /* ECI_MMU_PRBS_END_ADDRESS */ "", 22697 /* ECI_MMU_PRBS_START_ADDRESS */ "", 22698 /* ECI_NIF_0_PLL_CONFIGURATIONS */ "", 22699 /* ECI_NIF_0_PLL_STATUS */ "", 22700 /* ECI_NIF_1_PLL_CONFIGURATIONS */ "", 22701 /* ECI_NIF_1_PLL_STATUS */ "", 22702 /* ECI_NIF_PMH_PLL_CONFIG */ "", 22703 /* ECI_NIF_PML_0_PLL_CONFIG */ "", 22704 /* ECI_NIF_PML_1_PLL_CONFIG */ "", 22705 /* ECI_NIF_PML_PLL_CONFIG */ "", 22706 /* ECI_NIF_PMX_PLL_CONFIG */ "", 22707 /* ECI_NUM_OF_MEM_WR_DONE */ "", 22708 /* ECI_OGER_1000 */ "", 22709 /* ECI_OGER_1001 */ "", 22710 /* ECI_OGER_1002 */ "", 22711 /* ECI_OGER_1003 */ "", 22712 /* ECI_OGER_1004 */ "", 22713 /* ECI_OGER_1005 */ "", 22714 /* ECI_OGER_1006 */ "", 22715 /* ECI_OGER_1007 */ "", 22716 /* ECI_OGER_1008 */ "", 22717 /* ECI_OGER_1009 */ "", 22718 /* ECI_OGER_1010 */ "", 22719 /* ECI_OGER_1011 */ "", 22720 /* ECI_OGER_1012 */ "", 22721 /* ECI_OGER_1013 */ "", 22722 /* ECI_OGER_1014 */ "", 22723 /* ECI_OGER_1015 */ "", 22724 /* ECI_OGER_1016 */ "", 22725 /* ECI_OGER_1017 */ "", 22726 /* ECI_OGER_1018 */ "", 22727 /* ECI_OGER_1019 */ "", 22728 /* ECI_OGER_1020 */ "", 22729 /* ECI_OGER_1021 */ "", 22730 /* ECI_OGER_1022 */ "", 22731 /* ECI_OGER_1023 */ "", 22732 /* ECI_OGER_1024 */ "", 22733 /* ECI_OGER_1025 */ "", 22734 /* ECI_OGER_1026 */ "", 22735 /* ECI_OGER_1027 */ "", 22736 /* ECI_OGER_1028 */ "", 22737 /* ECI_OGER_1029 */ "", 22738 /* ECI_OGER_1030 */ "", 22739 /* ECI_OGER_1031 */ "", 22740 /* ECI_OGER_1032 */ "", 22741 /* ECI_OGER_1033 */ "", 22742 /* ECI_OGER_1034 */ "", 22743 /* ECI_OGER_1035 */ "", 22744 /* ECI_OGER_1036 */ "", 22745 /* ECI_OGER_1037 */ "", 22746 /* ECI_OGER_1038 */ "", 22747 /* ECI_OGER_1039 */ "", 22748 /* ECI_OGER_1040 */ "", 22749 /* ECI_OGER_1041 */ "", 22750 /* ECI_OGER_1042 */ "", 22751 /* ECI_OGER_1043 */ "", 22752 /* ECI_OGER_1044 */ "", 22753 /* ECI_OGER_1046 */ "", 22754 /* ECI_OGER_1048 */ "", 22755 /* ECI_OGER_1049 */ "", 22756 /* ECI_OGER_1050 */ "", 22757 /* ECI_PACKET_SENT */ "", 22758 /* ECI_PAD_CONFIGURATION_REGISTER */ "", 22759 /* ECI_PARITY_ERR_ADDR */ "", 22760 /* ECI_PARITY_ERR_CNT */ "", 22761 /* ECI_PAR_ERR_INITIATE */ "", 22762 /* ECI_PCMI_0 */ "", 22763 /* ECI_PCMI_1 */ "", 22764 /* ECI_PCMI_2 */ "", 22765 /* ECI_PCMI_3 */ "", 22766 /* ECI_PCMI_4 */ "", 22767 /* ECI_PCMI_0_S */ "", 22768 /* ECI_PCMI_0_T */ "", 22769 /* ECI_PCMI_1_S */ "", 22770 /* ECI_PCMI_1_T */ "", 22771 /* ECI_PCMI_2_S */ "", 22772 /* ECI_PCMI_2_T */ "", 22773 /* ECI_PCMI_3_S */ "", 22774 /* ECI_PCMI_3_T */ "", 22775 /* ECI_PCMI_4_S */ "", 22776 /* ECI_PCMI_4_T */ "", 22777 /* ECI_PIR_CONFIGURATIONS */ "", 22778 /* ECI_PMH_PLL_STATUS */ "", 22779 /* ECI_PML_0_PLL_STATUS */ "", 22780 /* ECI_PML_1_PLL_STATUS */ "", 22781 /* ECI_PML_PLL_STATUS */ "", 22782 /* ECI_PMX_PLL_STATUS */ "", 22783 /* ECI_POWERUP_CONFIG */ "", 22784 /* ECI_POWER_UP_CONFIGURATION */ "", 22785 /* ECI_POWER_UP_MACHINE */ "", 22786 /* ECI_POWER_UP_MACHINE_GENERAL */ "", 22787 /* ECI_PP_FUNC_TEST_PORTS */ "", 22788 /* ECI_PP_INFO */ "", 22789 /* ECI_PRM_PLL_CONTROL_STATUS */ "", 22790 /* ECI_PVT_MON_A_CONTROL_REG */ "", 22791 /* ECI_PVT_MON_A_THERMAL_DATA */ "", 22792 /* ECI_PVT_MON_B_CONTROL_REG */ "", 22793 /* ECI_PVT_MON_B_THERMAL_DATA */ "", 22794 /* ECI_PVT_MON_CONTROL_REG */ "", 22795 /* ECI_PVT_MON_CTRL */ "", 22796 /* ECI_PVT_MON_C_CONTROL_REG */ "", 22797 /* ECI_PVT_MON_C_THERMAL_DATA */ "", 22798 /* ECI_PVT_MON_D_CONTROL_REG */ "", 22799 /* ECI_PVT_MON_D_THERMAL_DATA */ "", 22800 /* ECI_PVT_MON_RESULTS */ "", 22801 /* ECI_PVT_MON_THERMAL_DATA */ "", 22802 /* ECI_PVT_MON_TRACKER_CONTROL */ "", 22803 /* ECI_P_PLL_0_STATUS */ "", 22804 /* ECI_READ_MIRROR_MEMORY */ "", 22805 /* ECI_RECORDING_PARAM */ "", 22806 /* ECI_REG_0001 */ "", 22807 /* ECI_REG_0007 */ "", 22808 /* ECI_REG_0008 */ "", 22809 /* ECI_REG_0011 */ "", 22810 /* ECI_REG_0017 */ "", 22811 /* ECI_REG_0018 */ "", 22812 /* ECI_REG_0020 */ "", 22813 /* ECI_REG_0040 */ "", 22814 /* ECI_REG_0041 */ "", 22815 /* ECI_REG_0050 */ "", 22816 /* ECI_REG_0051 */ "", 22817 /* ECI_REG_0052 */ "", 22818 /* ECI_REG_0053 */ "", 22819 /* ECI_REG_0054 */ "", 22820 /* ECI_REG_0058 */ "", 22821 /* ECI_REG_0060 */ "", 22822 /* ECI_REG_0070 */ "", 22823 /* ECI_REG_0071 */ "", 22824 /* ECI_REG_0072 */ "", 22825 /* ECI_REG_0075 */ "", 22826 /* ECI_REG_0076 */ "", 22827 /* ECI_REG_0078 */ "", 22828 /* ECI_REG_0080 */ "", 22829 /* ECI_REG_0081 */ "", 22830 /* ECI_REG_0082 */ "", 22831 /* ECI_REG_0084 */ "", 22832 /* ECI_REG_0085 */ "", 22833 /* ECI_REG_0086 */ "", 22834 /* ECI_REG_0087 */ "", 22835 /* ECI_REG_0090 */ "", 22836 /* ECI_REG_0091 */ "", 22837 /* ECI_REG_0092 */ "", 22838 /* ECI_REG_0093 */ "", 22839 /* ECI_REG_0098 */ "", 22840 /* ECI_REG_0100 */ "", 22841 /* ECI_REG_0101 */ "", 22842 /* ECI_REG_0102 */ "", 22843 /* ECI_REG_0103 */ "", 22844 /* ECI_REG_0104 */ "", 22845 /* ECI_REG_0105 */ "", 22846 /* ECI_REG_0106 */ "", 22847 /* ECI_REG_0107 */ "", 22848 /* ECI_REG_0108 */ "", 22849 /* ECI_REG_0109 */ "", 22850 /* ECI_REG_0110 */ "", 22851 /* ECI_REG_0120 */ "", 22852 /* ECI_REG_0121 */ "", 22853 /* ECI_REG_0122 */ "", 22854 /* ECI_REG_0123 */ "", 22855 /* ECI_REG_0124 */ "", 22856 /* ECI_REG_0125 */ "", 22857 /* ECI_REG_0130 */ "", 22858 /* ECI_REG_0131 */ "", 22859 /* ECI_REG_0140 */ "", 22860 /* ECI_REG_0166 */ "", 22861 /* ECI_REG_0172 */ "", 22862 /* ECI_REG_0200 */ "", 22863 /* ECI_REG_0201 */ "", 22864 /* ECI_REG_0202 */ "", 22865 /* ECI_REG_0203 */ "", 22866 /* ECI_REG_0204 */ "", 22867 /* ECI_REG_0205 */ "", 22868 /* ECI_REG_0206 */ "", 22869 /* ECI_REG_0207 */ "", 22870 /* ECI_REG_0208 */ "", 22871 /* ECI_REG_0209 */ "", 22872 /* ECI_REG_0210 */ "", 22873 /* ECI_REG_0211 */ "", 22874 /* ECI_REG_0212 */ "", 22875 /* ECI_REG_0213 */ "", 22876 /* ECI_REG_0220 */ "", 22877 /* ECI_REG_0231 */ "", 22878 /* ECI_REG_0232 */ "", 22879 /* ECI_REG_0240 */ "", 22880 /* ECI_REG_0241 */ "", 22881 /* ECI_REG_0242 */ "", 22882 /* ECI_REG_0243 */ "", 22883 /* ECI_REG_0244 */ "", 22884 /* ECI_REG_0246 */ "", 22885 /* ECI_REG_0250 */ "", 22886 /* ECI_REG_0251 */ "", 22887 /* ECI_REG_0252 */ "", 22888 /* ECI_REG_0262 */ "", 22889 /* ECI_REG_0270 */ "", 22890 /* ECI_REG_0271 */ "", 22891 /* ECI_REG_0272 */ "", 22892 /* ECI_REG_0280 */ "", 22893 /* ECI_REG_0290 */ "", 22894 /* ECI_REG_0292 */ "", 22895 /* ECI_REG_000A */ "", 22896 /* ECI_REG_001F */ "", 22897 /* ECI_REG_007C */ "", 22898 /* ECI_REG_00A0 */ "", 22899 /* ECI_REG_00A3 */ "", 22900 /* ECI_REG_00A4 */ "", 22901 /* ECI_REG_00A6 */ "", 22902 /* ECI_REG_00AA */ "", 22903 /* ECI_REG_00AE */ "", 22904 /* ECI_REG_00AF */ "", 22905 /* ECI_REG_00B0 */ "", 22906 /* ECI_REG_00B1 */ "", 22907 /* ECI_REG_00B2 */ "", 22908 /* ECI_REG_00B3 */ "", 22909 /* ECI_REG_00B4 */ "", 22910 /* ECI_REG_00B5 */ "", 22911 /* ECI_REG_00B6 */ "", 22912 /* ECI_REG_00B7 */ "", 22913 /* ECI_REG_00B8 */ "", 22914 /* ECI_REG_00B9 */ "", 22915 /* ECI_REG_00BA */ "", 22916 /* ECI_REG_00BB */ "", 22917 /* ECI_REG_00BC */ "", 22918 /* ECI_REG_00BD */ "", 22919 /* ECI_REG_00BE */ "", 22920 /* ECI_REG_00BF */ "", 22921 /* ECI_REG_00D1 */ "", 22922 /* ECI_REG_00F0 */ "", 22923 /* ECI_REG_00F1 */ "", 22924 /* ECI_REG_00F2 */ "", 22925 /* ECI_REG_00F3 */ "", 22926 /* ECI_REG_00F4 */ "", 22927 /* ECI_REG_00F5 */ "", 22928 /* ECI_REG_00F6 */ "", 22929 /* ECI_REG_00F7 */ "", 22930 /* ECI_REG_00F8 */ "", 22931 /* ECI_REG_00F9 */ "", 22932 /* ECI_REG_00FA */ "", 22933 /* ECI_REG_00FB */ "", 22934 /* ECI_REG_00FC */ "", 22935 /* ECI_REG_00FD */ "", 22936 /* ECI_REG_00FE */ "", 22937 /* ECI_REG_00FF */ "", 22938 /* ECI_REG_010A */ "", 22939 /* ECI_REG_010B */ "", 22940 /* ECI_REG_010C */ "", 22941 /* ECI_REG_010D */ "", 22942 /* ECI_REG_010E */ "", 22943 /* ECI_REG_010F */ "", 22944 /* ECI_REG_012B */ "", 22945 /* ECI_REG_016C */ "", 22946 /* ECI_REG_017A */ "", 22947 /* ECI_REG_01AE */ "", 22948 /* ECI_REG_01B4 */ "", 22949 /* ECI_REG_01BA */ "", 22950 /* ECI_REG_01BB */ "", 22951 /* ECI_REG_01BD */ "", 22952 /* ECI_REG_01CE */ "", 22953 /* ECI_REG_01DC */ "", 22954 /* ECI_REG_01DE */ "", 22955 /* ECI_REG_01DF */ "", 22956 /* ECI_REG_01E0 */ "", 22957 /* ECI_REG_01E1 */ "", 22958 /* ECI_REG_01E2 */ "", 22959 /* ECI_REG_01E4 */ "", 22960 /* ECI_REG_01E9 */ "", 22961 /* ECI_REG_01EF */ "", 22962 /* ECI_REG_01F0 */ "", 22963 /* ECI_REG_01F1 */ "", 22964 /* ECI_REG_020A */ "", 22965 /* ECI_REG_020B */ "", 22966 /* ECI_REG_020C */ "", 22967 /* ECI_REG_020D */ "", 22968 /* ECI_REG_020E */ "", 22969 /* ECI_REG_020F */ "", 22970 /* ECI_REG_022F */ "", 22971 /* ECI_REG_023A */ "", 22972 /* ECI_REG_023D */ "", 22973 /* ECI_REG_024B */ "", 22974 /* ECI_REG_028D */ "", 22975 /* ECI_REG_028E */ "", 22976 /* ECI_REG_028F */ "", 22977 /* ECI_RESCAL_CONTROL */ "", 22978 /* ECI_RESCAL_CTRL */ "", 22979 /* ECI_RESCAL_STATUS */ "", 22980 /* ECI_RESERVED_2 */ "", 22981 /* ECI_RESERVED_3 */ "", 22982 /* ECI_RESERVED_4 */ "", 22983 /* ECI_RESERVED_5 */ "", 22984 /* ECI_RESERVED_6 */ "", 22985 /* ECI_RESERVED_7 */ "", 22986 /* ECI_RESERVED_8 */ "", 22987 /* ECI_RESERVED_9 */ "", 22988 /* ECI_RESERVED_10 */ "", 22989 /* ECI_RESERVED_11 */ "", 22990 /* ECI_RESERVED_12 */ "", 22991 /* ECI_RESERVED_13 */ "", 22992 /* ECI_RESERVED_14 */ "", 22993 /* ECI_RESERVED_15 */ "", 22994 /* ECI_RESERVED_16 */ "", 22995 /* ECI_RESERVED_17 */ "", 22996 /* ECI_RESERVED_19 */ "", 22997 /* ECI_RESERVED_20 */ "", 22998 /* ECI_RESERVED_21 */ "", 22999 /* ECI_RESERVED_22 */ "", 23000 /* ECI_RESERVED_29 */ "", 23001 /* ECI_RESERVED_30 */ "", 23002 /* ECI_RESERVED_31 */ "", 23003 /* ECI_RESERVED_32 */ "", 23004 /* ECI_RESERVED_33 */ "", 23005 /* ECI_RESERVED_34 */ "", 23006 /* ECI_RESERVED_35 */ "", 23007 /* ECI_RESERVED_36 */ "", 23008 /* ECI_RESERVED_37 */ "", 23009 /* ECI_RESERVED_38 */ "", 23010 /* ECI_RESERVED_39 */ "", 23011 /* ECI_RESERVED_40 */ "", 23012 /* ECI_RESERVED_43 */ "", 23013 /* ECI_RESERVED_44 */ "", 23014 /* ECI_RESERVED_45 */ "", 23015 /* ECI_RESERVED_46 */ "", 23016 /* ECI_RESERVED_47 */ "", 23017 /* ECI_RESERVED_49 */ "", 23018 /* ECI_RESERVED_50 */ "", 23019 /* ECI_RESERVED_51 */ "", 23020 /* ECI_RESERVED_52 */ "", 23021 /* ECI_RESERVED_MIRROR_ADDR */ "", 23022 /* ECI_RESERVED_MTCD */ "", 23023 /* ECI_RESERVED_MTCP */ "", 23024 /* ECI_RESERVED_PCMI_0 */ "", 23025 /* ECI_RESERVED_PCMI_1 */ "", 23026 /* ECI_RESERVED_PCMI_2 */ "", 23027 /* ECI_RESERVED_PCMI_3 */ "", 23028 /* ECI_RESERVED_PCMI_4 */ "", 23029 /* ECI_RESERVED_PCMI_0_S */ "", 23030 /* ECI_RESERVED_PCMI_0_T */ "", 23031 /* ECI_RESERVED_PCMI_1_S */ "", 23032 /* ECI_RESERVED_PCMI_1_T */ "", 23033 /* ECI_RESERVED_PCMI_2_S */ "", 23034 /* ECI_RESERVED_PCMI_2_T */ "", 23035 /* ECI_RESERVED_PCMI_3_S */ "", 23036 /* ECI_RESERVED_PCMI_3_T */ "", 23037 /* ECI_RESERVED_PCMI_4_S */ "", 23038 /* ECI_RESERVED_PCMI_4_T */ "", 23039 /* ECI_RESERVED_SPARE_0 */ "", 23040 /* ECI_RESERVED_SPARE_1 */ "", 23041 /* ECI_RESERVED_SPARE_2 */ "", 23042 /* ECI_RESERVED_SPARE_3 */ "", 23043 /* ECI_RES_CAL_CONFIG */ "", 23044 /* ECI_RES_CAL_CONFIG_01 */ "", 23045 /* ECI_RES_CAL_CONFIG_23 */ "", 23046 /* ECI_RES_CAL_CPU_OVERRIDE_REGISTER */ "", 23047 /* ECI_RES_CAL_STATUS */ "", 23048 /* ECI_RES_CAL_STICKY_CONFIG */ "", 23049 /* ECI_RES_CAL_STICKY_INIT_REGISTER */ "", 23050 /* ECI_ROV_STATUS */ "", 23051 /* ECI_SAM_CONFIGURATIONS */ "", 23052 /* ECI_SAM_DBG_TRANSACTION */ "", 23053 /* ECI_SAM_ERROR */ "", 23054 /* ECI_SAM_RD_DATA */ "", 23055 /* ECI_SBUS_BROADCAST_ID */ "", 23056 /* ECI_SBUS_LAST_IN_CHAIN */ "", 23057 /* ECI_SB_RSTN_AND_POWER_DOWN */ "", 23058 /* ECI_SCRATCH_PAD_0 */ "", 23059 /* ECI_SCRATCH_PAD_1 */ "", 23060 /* ECI_SCRATCH_PAD_2 */ "", 23061 /* ECI_SCRATCH_PAD_3 */ "", 23062 /* ECI_SELECT_OUTPUT_OF_SYNCHRONOUS_ETHERNET_PADS */ "", 23063 /* ECI_SINAI_INTERRUPTS */ "", 23064 /* ECI_SINAI_INTERRUPTS_MASK */ "", 23065 /* ECI_SINAI_INTERRUPTS_TEST */ "", 23066 /* ECI_SLAVE_SYNCE_PLL_STATUS */ "", 23067 /* ECI_SPARE_REGISTER */ "", 23068 /* ECI_SPARE_REGISTER_1 */ "", 23069 /* ECI_SPARE_REGISTER_2 */ "", 23070 /* ECI_SPLL_0_CONFIG_0 */ "", 23071 /* ECI_SPLL_0_CONFIG_1 */ "", 23072 /* ECI_SPLL_0_CONFIG_2 */ "", 23073 /* ECI_SPLL_0_CONFIG_3 */ "", 23074 /* ECI_SPLL_0_CONFIG_4 */ "", 23075 /* ECI_SRAM_0_TEST_STATUS_A */ "", 23076 /* ECI_SRAM_0_TEST_STATUS_B */ "", 23077 /* ECI_SRAM_0_TEST_STATUS_C */ "", 23078 /* ECI_SRAM_1_TEST_STATUS_A */ "", 23079 /* ECI_SRAM_1_TEST_STATUS_B */ "", 23080 /* ECI_SRAM_1_TEST_STATUS_C */ "", 23081 /* ECI_SRAM_2_TEST_STATUS_A */ "", 23082 /* ECI_SRAM_2_TEST_STATUS_B */ "", 23083 /* ECI_SRAM_2_TEST_STATUS_C */ "", 23084 /* ECI_SRAM_CONTROLLER */ "", 23085 /* ECI_SRAM_CONTROLLER_PRBS_MODE */ "", 23086 /* ECI_SRD_0_PLL_CONFIG */ "", 23087 /* ECI_SRD_0_PLL_STATUS */ "", 23088 /* ECI_SRD_1_PLL_CONFIG */ "", 23089 /* ECI_SRD_1_PLL_STATUS */ "", 23090 /* ECI_SW_VERSION */ "", 23091 /* ECI_SYNCE_MASTER_PLL_CONFIG */ "", 23092 /* ECI_SYNCE_SLAVE_PLL_CONFIG */ "", 23093 /* ECI_SYNC_E_RSTN */ "", 23094 /* ECI_TAP_CONTROL */ "", 23095 /* ECI_TAP_CPU_INTERFACE_COMMAND */ "", 23096 /* ECI_TAP_CPU_INTERFACE_DATA_IN */ "", 23097 /* ECI_TAP_CPU_INTERFACE_DATA_OUT */ "", 23098 /* ECI_TELECOM_PLL_CONFIGURATIONS */ "", 23099 /* ECI_TEST_REGISTER */ "", 23100 /* ECI_TIME_RATIO */ "", 23101 /* ECI_TIME_TO_WAIT_BEFORE_TRG_VAL */ "", 23102 /* ECI_TIME_TO_WAIT_TO_START_RECORD */ "", 23103 /* ECI_TOD_COMMAND */ "", 23104 /* ECI_TOD_COMMAND_RD_DATA */ "", 23105 /* ECI_TOD_COMMAND_WR_DATA */ "", 23106 /* ECI_TOD_GENERAL_CONFIGURATION */ "", 23107 /* ECI_TRIGGER_LOGIC_MDATA_MASK_0 */ "", 23108 /* ECI_TRIGGER_LOGIC_MDATA_MASK_1 */ "", 23109 /* ECI_TRIGGER_LOGIC_MDATA_MASK_2 */ "", 23110 /* ECI_TRIGGER_LOGIC_MDATA_MASK_3 */ "", 23111 /* ECI_TRIGGER_LOGIC_MDATA_MASK_4 */ "", 23112 /* ECI_TRIGGER_LOGIC_MDATA_VALUE_0 */ "", 23113 /* ECI_TRIGGER_LOGIC_MDATA_VALUE_1 */ "", 23114 /* ECI_TRIGGER_LOGIC_MDATA_VALUE_2 */ "", 23115 /* ECI_TRIGGER_LOGIC_MDATA_VALUE_3 */ "", 23116 /* ECI_TRIGGER_LOGIC_MDATA_VALUE_4 */ "", 23117 /* ECI_TS_PLL_CONFIG */ "", 23118 /* ECI_TS_PLL_CONFIGURATIONS */ "", 23119 /* ECI_TS_PLL_STATUS */ "", 23120 /* ECI_UC_PLL_CONFIG */ "", 23121 /* ECI_UC_PLL_STATUS */ "", 23122 /* ECI_UPI_CONTROL */ "", 23123 /* ECI_UPI_RES_ICID */ "", 23124 /* ECI_UPI_RES_PCM */ "", 23125 /* ECI_UPI_RES_RO */ "", 23126 /* ECI_VERSION_REGISTER */ "", 23127 /* ECI_VSN_CONFIG */ "", 23128 /* ECI_VSN_STATUS */ "", 23129 /* ECI_VTMON_CONFIG_1 */ "", 23130 /* ECI_VTMON_DATA */ "", 23131 /* ECI_VTMON_DATA_MAX */ "", 23132 /* ECI_WCMEM_ADDR */ "", 23133 /* ECI_XP_FUNC_TEST_PORTS */ "", 23134 /* ECMAP0_CID_0 */ "", 23135 /* ECMAP0_CID_1 */ "", 23136 /* ECMAP0_CID_2 */ "", 23137 /* ECMAP0_CID_3 */ "", 23138 /* ECMAP0_CID_4 */ "", 23139 /* ECMAP0_CID_5 */ "", 23140 /* ECMAP0_CID_6 */ "", 23141 /* ECMAP0_CID_7 */ "", 23142 /* ECMAP0_CID_8 */ "", 23143 /* ECMAP0_CID_9 */ "", 23144 /* ECMAP0_CID_10 */ "", 23145 /* ECMAP0_CID_11 */ "", 23146 /* ECMAP0_CID_12 */ "", 23147 /* ECMAP0_CID_13 */ "", 23148 /* ECMAP0_CID_14 */ "", 23149 /* ECMAP0_CID_15 */ "", 23150 /* ECMAP10_CID_0 */ "", 23151 /* ECMAP10_CID_1 */ "", 23152 /* ECMAP10_CID_2 */ "", 23153 /* ECMAP10_CID_3 */ "", 23154 /* ECMAP10_CID_4 */ "", 23155 /* ECMAP10_CID_5 */ "", 23156 /* ECMAP10_CID_6 */ "", 23157 /* ECMAP10_CID_7 */ "", 23158 /* ECMAP10_CID_8 */ "", 23159 /* ECMAP10_CID_9 */ "", 23160 /* ECMAP10_CID_10 */ "", 23161 /* ECMAP10_CID_11 */ "", 23162 /* ECMAP10_CID_12 */ "", 23163 /* ECMAP10_CID_13 */ "", 23164 /* ECMAP10_CID_14 */ "", 23165 /* ECMAP10_CID_15 */ "", 23166 /* ECMAP11_CID_0 */ "", 23167 /* ECMAP11_CID_1 */ "", 23168 /* ECMAP11_CID_2 */ "", 23169 /* ECMAP11_CID_3 */ "", 23170 /* ECMAP11_CID_4 */ "", 23171 /* ECMAP11_CID_5 */ "", 23172 /* ECMAP11_CID_6 */ "", 23173 /* ECMAP11_CID_7 */ "", 23174 /* ECMAP11_CID_8 */ "", 23175 /* ECMAP11_CID_9 */ "", 23176 /* ECMAP11_CID_10 */ "", 23177 /* ECMAP11_CID_11 */ "", 23178 /* ECMAP11_CID_12 */ "", 23179 /* ECMAP11_CID_13 */ "", 23180 /* ECMAP11_CID_14 */ "", 23181 /* ECMAP11_CID_15 */ "", 23182 /* ECMAP12_CID_0 */ "", 23183 /* ECMAP12_CID_1 */ "", 23184 /* ECMAP12_CID_2 */ "", 23185 /* ECMAP12_CID_3 */ "", 23186 /* ECMAP12_CID_4 */ "", 23187 /* ECMAP12_CID_5 */ "", 23188 /* ECMAP12_CID_6 */ "", 23189 /* ECMAP12_CID_7 */ "", 23190 /* ECMAP12_CID_8 */ "", 23191 /* ECMAP12_CID_9 */ "", 23192 /* ECMAP12_CID_10 */ "", 23193 /* ECMAP12_CID_11 */ "", 23194 /* ECMAP12_CID_12 */ "", 23195 /* ECMAP12_CID_13 */ "", 23196 /* ECMAP12_CID_14 */ "", 23197 /* ECMAP12_CID_15 */ "", 23198 /* ECMAP13_CID_0 */ "", 23199 /* ECMAP13_CID_1 */ "", 23200 /* ECMAP13_CID_2 */ "", 23201 /* ECMAP13_CID_3 */ "", 23202 /* ECMAP13_CID_4 */ "", 23203 /* ECMAP13_CID_5 */ "", 23204 /* ECMAP13_CID_6 */ "", 23205 /* ECMAP13_CID_7 */ "", 23206 /* ECMAP13_CID_8 */ "", 23207 /* ECMAP13_CID_9 */ "", 23208 /* ECMAP13_CID_10 */ "", 23209 /* ECMAP13_CID_11 */ "", 23210 /* ECMAP13_CID_12 */ "", 23211 /* ECMAP13_CID_13 */ "", 23212 /* ECMAP13_CID_14 */ "", 23213 /* ECMAP13_CID_15 */ "", 23214 /* ECMAP14_CID_0 */ "", 23215 /* ECMAP14_CID_1 */ "", 23216 /* ECMAP14_CID_2 */ "", 23217 /* ECMAP14_CID_3 */ "", 23218 /* ECMAP14_CID_4 */ "", 23219 /* ECMAP14_CID_5 */ "", 23220 /* ECMAP14_CID_6 */ "", 23221 /* ECMAP14_CID_7 */ "", 23222 /* ECMAP14_CID_8 */ "", 23223 /* ECMAP14_CID_9 */ "", 23224 /* ECMAP14_CID_10 */ "", 23225 /* ECMAP14_CID_11 */ "", 23226 /* ECMAP14_CID_12 */ "", 23227 /* ECMAP14_CID_13 */ "", 23228 /* ECMAP14_CID_14 */ "", 23229 /* ECMAP14_CID_15 */ "", 23230 /* ECMAP15_CID_0 */ "", 23231 /* ECMAP15_CID_1 */ "", 23232 /* ECMAP15_CID_2 */ "", 23233 /* ECMAP15_CID_3 */ "", 23234 /* ECMAP15_CID_4 */ "", 23235 /* ECMAP15_CID_5 */ "", 23236 /* ECMAP15_CID_6 */ "", 23237 /* ECMAP15_CID_7 */ "", 23238 /* ECMAP15_CID_8 */ "", 23239 /* ECMAP15_CID_9 */ "", 23240 /* ECMAP15_CID_10 */ "", 23241 /* ECMAP15_CID_11 */ "", 23242 /* ECMAP15_CID_12 */ "", 23243 /* ECMAP15_CID_13 */ "", 23244 /* ECMAP15_CID_14 */ "", 23245 /* ECMAP15_CID_15 */ "", 23246 /* ECMAP16_CID_0 */ "", 23247 /* ECMAP16_CID_1 */ "", 23248 /* ECMAP16_CID_2 */ "", 23249 /* ECMAP16_CID_3 */ "", 23250 /* ECMAP16_CID_4 */ "", 23251 /* ECMAP16_CID_5 */ "", 23252 /* ECMAP16_CID_6 */ "", 23253 /* ECMAP16_CID_7 */ "", 23254 /* ECMAP16_CID_8 */ "", 23255 /* ECMAP16_CID_9 */ "", 23256 /* ECMAP16_CID_10 */ "", 23257 /* ECMAP16_CID_11 */ "", 23258 /* ECMAP16_CID_12 */ "", 23259 /* ECMAP16_CID_13 */ "", 23260 /* ECMAP16_CID_14 */ "", 23261 /* ECMAP16_CID_15 */ "", 23262 /* ECMAP17_CID_0 */ "", 23263 /* ECMAP17_CID_1 */ "", 23264 /* ECMAP17_CID_2 */ "", 23265 /* ECMAP17_CID_3 */ "", 23266 /* ECMAP17_CID_4 */ "", 23267 /* ECMAP17_CID_5 */ "", 23268 /* ECMAP17_CID_6 */ "", 23269 /* ECMAP17_CID_7 */ "", 23270 /* ECMAP17_CID_8 */ "", 23271 /* ECMAP17_CID_9 */ "", 23272 /* ECMAP17_CID_10 */ "", 23273 /* ECMAP17_CID_11 */ "", 23274 /* ECMAP17_CID_12 */ "", 23275 /* ECMAP17_CID_13 */ "", 23276 /* ECMAP17_CID_14 */ "", 23277 /* ECMAP17_CID_15 */ "", 23278 /* ECMAP18_CID_0 */ "", 23279 /* ECMAP18_CID_1 */ "", 23280 /* ECMAP18_CID_2 */ "", 23281 /* ECMAP18_CID_3 */ "", 23282 /* ECMAP18_CID_4 */ "", 23283 /* ECMAP18_CID_5 */ "", 23284 /* ECMAP18_CID_6 */ "", 23285 /* ECMAP18_CID_7 */ "", 23286 /* ECMAP18_CID_8 */ "", 23287 /* ECMAP18_CID_9 */ "", 23288 /* ECMAP18_CID_10 */ "", 23289 /* ECMAP18_CID_11 */ "", 23290 /* ECMAP18_CID_12 */ "", 23291 /* ECMAP18_CID_13 */ "", 23292 /* ECMAP18_CID_14 */ "", 23293 /* ECMAP18_CID_15 */ "", 23294 /* ECMAP19_CID_0 */ "", 23295 /* ECMAP19_CID_1 */ "", 23296 /* ECMAP19_CID_2 */ "", 23297 /* ECMAP19_CID_3 */ "", 23298 /* ECMAP19_CID_4 */ "", 23299 /* ECMAP19_CID_5 */ "", 23300 /* ECMAP19_CID_6 */ "", 23301 /* ECMAP19_CID_7 */ "", 23302 /* ECMAP19_CID_8 */ "", 23303 /* ECMAP19_CID_9 */ "", 23304 /* ECMAP19_CID_10 */ "", 23305 /* ECMAP19_CID_11 */ "", 23306 /* ECMAP19_CID_12 */ "", 23307 /* ECMAP19_CID_13 */ "", 23308 /* ECMAP19_CID_14 */ "", 23309 /* ECMAP19_CID_15 */ "", 23310 /* ECMAP1_CID_0 */ "", 23311 /* ECMAP1_CID_1 */ "", 23312 /* ECMAP1_CID_2 */ "", 23313 /* ECMAP1_CID_3 */ "", 23314 /* ECMAP1_CID_4 */ "", 23315 /* ECMAP1_CID_5 */ "", 23316 /* ECMAP1_CID_6 */ "", 23317 /* ECMAP1_CID_7 */ "", 23318 /* ECMAP1_CID_8 */ "", 23319 /* ECMAP1_CID_9 */ "", 23320 /* ECMAP1_CID_10 */ "", 23321 /* ECMAP1_CID_11 */ "", 23322 /* ECMAP1_CID_12 */ "", 23323 /* ECMAP1_CID_13 */ "", 23324 /* ECMAP1_CID_14 */ "", 23325 /* ECMAP1_CID_15 */ "", 23326 /* ECMAP20_CID_0 */ "", 23327 /* ECMAP20_CID_1 */ "", 23328 /* ECMAP20_CID_2 */ "", 23329 /* ECMAP20_CID_3 */ "", 23330 /* ECMAP20_CID_4 */ "", 23331 /* ECMAP20_CID_5 */ "", 23332 /* ECMAP20_CID_6 */ "", 23333 /* ECMAP20_CID_7 */ "", 23334 /* ECMAP20_CID_8 */ "", 23335 /* ECMAP20_CID_9 */ "", 23336 /* ECMAP20_CID_10 */ "", 23337 /* ECMAP20_CID_11 */ "", 23338 /* ECMAP20_CID_12 */ "", 23339 /* ECMAP20_CID_13 */ "", 23340 /* ECMAP20_CID_14 */ "", 23341 /* ECMAP20_CID_15 */ "", 23342 /* ECMAP21_CID_0 */ "", 23343 /* ECMAP21_CID_1 */ "", 23344 /* ECMAP21_CID_2 */ "", 23345 /* ECMAP21_CID_3 */ "", 23346 /* ECMAP21_CID_4 */ "", 23347 /* ECMAP21_CID_5 */ "", 23348 /* ECMAP21_CID_6 */ "", 23349 /* ECMAP21_CID_7 */ "", 23350 /* ECMAP21_CID_8 */ "", 23351 /* ECMAP21_CID_9 */ "", 23352 /* ECMAP21_CID_10 */ "", 23353 /* ECMAP21_CID_11 */ "", 23354 /* ECMAP21_CID_12 */ "", 23355 /* ECMAP21_CID_13 */ "", 23356 /* ECMAP21_CID_14 */ "", 23357 /* ECMAP21_CID_15 */ "", 23358 /* ECMAP22_CID_0 */ "", 23359 /* ECMAP22_CID_1 */ "", 23360 /* ECMAP22_CID_2 */ "", 23361 /* ECMAP22_CID_3 */ "", 23362 /* ECMAP22_CID_4 */ "", 23363 /* ECMAP22_CID_5 */ "", 23364 /* ECMAP22_CID_6 */ "", 23365 /* ECMAP22_CID_7 */ "", 23366 /* ECMAP22_CID_8 */ "", 23367 /* ECMAP22_CID_9 */ "", 23368 /* ECMAP22_CID_10 */ "", 23369 /* ECMAP22_CID_11 */ "", 23370 /* ECMAP22_CID_12 */ "", 23371 /* ECMAP22_CID_13 */ "", 23372 /* ECMAP22_CID_14 */ "", 23373 /* ECMAP22_CID_15 */ "", 23374 /* ECMAP23_CID_0 */ "", 23375 /* ECMAP23_CID_1 */ "", 23376 /* ECMAP23_CID_2 */ "", 23377 /* ECMAP23_CID_3 */ "", 23378 /* ECMAP23_CID_4 */ "", 23379 /* ECMAP23_CID_5 */ "", 23380 /* ECMAP23_CID_6 */ "", 23381 /* ECMAP23_CID_7 */ "", 23382 /* ECMAP23_CID_8 */ "", 23383 /* ECMAP23_CID_9 */ "", 23384 /* ECMAP23_CID_10 */ "", 23385 /* ECMAP23_CID_11 */ "", 23386 /* ECMAP23_CID_12 */ "", 23387 /* ECMAP23_CID_13 */ "", 23388 /* ECMAP23_CID_14 */ "", 23389 /* ECMAP23_CID_15 */ "", 23390 /* ECMAP24_CID_0 */ "", 23391 /* ECMAP24_CID_1 */ "", 23392 /* ECMAP24_CID_2 */ "", 23393 /* ECMAP24_CID_3 */ "", 23394 /* ECMAP24_CID_4 */ "", 23395 /* ECMAP24_CID_5 */ "", 23396 /* ECMAP24_CID_6 */ "", 23397 /* ECMAP24_CID_7 */ "", 23398 /* ECMAP24_CID_8 */ "", 23399 /* ECMAP24_CID_9 */ "", 23400 /* ECMAP24_CID_10 */ "", 23401 /* ECMAP24_CID_11 */ "", 23402 /* ECMAP24_CID_12 */ "", 23403 /* ECMAP24_CID_13 */ "", 23404 /* ECMAP24_CID_14 */ "", 23405 /* ECMAP24_CID_15 */ "", 23406 /* ECMAP25_CID_0 */ "", 23407 /* ECMAP25_CID_1 */ "", 23408 /* ECMAP25_CID_2 */ "", 23409 /* ECMAP25_CID_3 */ "", 23410 /* ECMAP25_CID_4 */ "", 23411 /* ECMAP25_CID_5 */ "", 23412 /* ECMAP25_CID_6 */ "", 23413 /* ECMAP25_CID_7 */ "", 23414 /* ECMAP25_CID_8 */ "", 23415 /* ECMAP25_CID_9 */ "", 23416 /* ECMAP25_CID_10 */ "", 23417 /* ECMAP25_CID_11 */ "", 23418 /* ECMAP25_CID_12 */ "", 23419 /* ECMAP25_CID_13 */ "", 23420 /* ECMAP25_CID_14 */ "", 23421 /* ECMAP25_CID_15 */ "", 23422 /* ECMAP26_CID_0 */ "", 23423 /* ECMAP26_CID_1 */ "", 23424 /* ECMAP26_CID_2 */ "", 23425 /* ECMAP26_CID_3 */ "", 23426 /* ECMAP26_CID_4 */ "", 23427 /* ECMAP26_CID_5 */ "", 23428 /* ECMAP26_CID_6 */ "", 23429 /* ECMAP26_CID_7 */ "", 23430 /* ECMAP26_CID_8 */ "", 23431 /* ECMAP26_CID_9 */ "", 23432 /* ECMAP26_CID_10 */ "", 23433 /* ECMAP26_CID_11 */ "", 23434 /* ECMAP26_CID_12 */ "", 23435 /* ECMAP26_CID_13 */ "", 23436 /* ECMAP26_CID_14 */ "", 23437 /* ECMAP26_CID_15 */ "", 23438 /* ECMAP27_CID_0 */ "", 23439 /* ECMAP27_CID_1 */ "", 23440 /* ECMAP27_CID_2 */ "", 23441 /* ECMAP27_CID_3 */ "", 23442 /* ECMAP27_CID_4 */ "", 23443 /* ECMAP27_CID_5 */ "", 23444 /* ECMAP27_CID_6 */ "", 23445 /* ECMAP27_CID_7 */ "", 23446 /* ECMAP27_CID_8 */ "", 23447 /* ECMAP27_CID_9 */ "", 23448 /* ECMAP27_CID_10 */ "", 23449 /* ECMAP27_CID_11 */ "", 23450 /* ECMAP27_CID_12 */ "", 23451 /* ECMAP27_CID_13 */ "", 23452 /* ECMAP27_CID_14 */ "", 23453 /* ECMAP27_CID_15 */ "", 23454 /* ECMAP28_CID_0 */ "", 23455 /* ECMAP28_CID_1 */ "", 23456 /* ECMAP28_CID_2 */ "", 23457 /* ECMAP28_CID_3 */ "", 23458 /* ECMAP28_CID_4 */ "", 23459 /* ECMAP28_CID_5 */ "", 23460 /* ECMAP28_CID_6 */ "", 23461 /* ECMAP28_CID_7 */ "", 23462 /* ECMAP28_CID_8 */ "", 23463 /* ECMAP28_CID_9 */ "", 23464 /* ECMAP28_CID_10 */ "", 23465 /* ECMAP28_CID_11 */ "", 23466 /* ECMAP28_CID_12 */ "", 23467 /* ECMAP28_CID_13 */ "", 23468 /* ECMAP28_CID_14 */ "", 23469 /* ECMAP28_CID_15 */ "", 23470 /* ECMAP29_CID_0 */ "", 23471 /* ECMAP29_CID_1 */ "", 23472 /* ECMAP29_CID_2 */ "", 23473 /* ECMAP29_CID_3 */ "", 23474 /* ECMAP29_CID_4 */ "", 23475 /* ECMAP29_CID_5 */ "", 23476 /* ECMAP29_CID_6 */ "", 23477 /* ECMAP29_CID_7 */ "", 23478 /* ECMAP29_CID_8 */ "", 23479 /* ECMAP29_CID_9 */ "", 23480 /* ECMAP29_CID_10 */ "", 23481 /* ECMAP29_CID_11 */ "", 23482 /* ECMAP29_CID_12 */ "", 23483 /* ECMAP29_CID_13 */ "", 23484 /* ECMAP29_CID_14 */ "", 23485 /* ECMAP29_CID_15 */ "", 23486 /* ECMAP2_CID_0 */ "", 23487 /* ECMAP2_CID_1 */ "", 23488 /* ECMAP2_CID_2 */ "", 23489 /* ECMAP2_CID_3 */ "", 23490 /* ECMAP2_CID_4 */ "", 23491 /* ECMAP2_CID_5 */ "", 23492 /* ECMAP2_CID_6 */ "", 23493 /* ECMAP2_CID_7 */ "", 23494 /* ECMAP2_CID_8 */ "", 23495 /* ECMAP2_CID_9 */ "", 23496 /* ECMAP2_CID_10 */ "", 23497 /* ECMAP2_CID_11 */ "", 23498 /* ECMAP2_CID_12 */ "", 23499 /* ECMAP2_CID_13 */ "", 23500 /* ECMAP2_CID_14 */ "", 23501 /* ECMAP2_CID_15 */ "", 23502 /* ECMAP30_CID_0 */ "", 23503 /* ECMAP30_CID_1 */ "", 23504 /* ECMAP30_CID_2 */ "", 23505 /* ECMAP30_CID_3 */ "", 23506 /* ECMAP30_CID_4 */ "", 23507 /* ECMAP30_CID_5 */ "", 23508 /* ECMAP30_CID_6 */ "", 23509 /* ECMAP30_CID_7 */ "", 23510 /* ECMAP30_CID_8 */ "", 23511 /* ECMAP30_CID_9 */ "", 23512 /* ECMAP30_CID_10 */ "", 23513 /* ECMAP30_CID_11 */ "", 23514 /* ECMAP30_CID_12 */ "", 23515 /* ECMAP30_CID_13 */ "", 23516 /* ECMAP30_CID_14 */ "", 23517 /* ECMAP30_CID_15 */ "", 23518 /* ECMAP31_CID_0 */ "", 23519 /* ECMAP31_CID_1 */ "", 23520 /* ECMAP31_CID_2 */ "", 23521 /* ECMAP31_CID_3 */ "", 23522 /* ECMAP31_CID_4 */ "", 23523 /* ECMAP31_CID_5 */ "", 23524 /* ECMAP31_CID_6 */ "", 23525 /* ECMAP31_CID_7 */ "", 23526 /* ECMAP31_CID_8 */ "", 23527 /* ECMAP31_CID_9 */ "", 23528 /* ECMAP31_CID_10 */ "", 23529 /* ECMAP31_CID_11 */ "", 23530 /* ECMAP31_CID_12 */ "", 23531 /* ECMAP31_CID_13 */ "", 23532 /* ECMAP31_CID_14 */ "", 23533 /* ECMAP31_CID_15 */ "", 23534 /* ECMAP3_CID_0 */ "", 23535 /* ECMAP3_CID_1 */ "", 23536 /* ECMAP3_CID_2 */ "", 23537 /* ECMAP3_CID_3 */ "", 23538 /* ECMAP3_CID_4 */ "", 23539 /* ECMAP3_CID_5 */ "", 23540 /* ECMAP3_CID_6 */ "", 23541 /* ECMAP3_CID_7 */ "", 23542 /* ECMAP3_CID_8 */ "", 23543 /* ECMAP3_CID_9 */ "", 23544 /* ECMAP3_CID_10 */ "", 23545 /* ECMAP3_CID_11 */ "", 23546 /* ECMAP3_CID_12 */ "", 23547 /* ECMAP3_CID_13 */ "", 23548 /* ECMAP3_CID_14 */ "", 23549 /* ECMAP3_CID_15 */ "", 23550 /* ECMAP4_CID_0 */ "", 23551 /* ECMAP4_CID_1 */ "", 23552 /* ECMAP4_CID_2 */ "", 23553 /* ECMAP4_CID_3 */ "", 23554 /* ECMAP4_CID_4 */ "", 23555 /* ECMAP4_CID_5 */ "", 23556 /* ECMAP4_CID_6 */ "", 23557 /* ECMAP4_CID_7 */ "", 23558 /* ECMAP4_CID_8 */ "", 23559 /* ECMAP4_CID_9 */ "", 23560 /* ECMAP4_CID_10 */ "", 23561 /* ECMAP4_CID_11 */ "", 23562 /* ECMAP4_CID_12 */ "", 23563 /* ECMAP4_CID_13 */ "", 23564 /* ECMAP4_CID_14 */ "", 23565 /* ECMAP4_CID_15 */ "", 23566 /* ECMAP5_CID_0 */ "", 23567 /* ECMAP5_CID_1 */ "", 23568 /* ECMAP5_CID_2 */ "", 23569 /* ECMAP5_CID_3 */ "", 23570 /* ECMAP5_CID_4 */ "", 23571 /* ECMAP5_CID_5 */ "", 23572 /* ECMAP5_CID_6 */ "", 23573 /* ECMAP5_CID_7 */ "", 23574 /* ECMAP5_CID_8 */ "", 23575 /* ECMAP5_CID_9 */ "", 23576 /* ECMAP5_CID_10 */ "", 23577 /* ECMAP5_CID_11 */ "", 23578 /* ECMAP5_CID_12 */ "", 23579 /* ECMAP5_CID_13 */ "", 23580 /* ECMAP5_CID_14 */ "", 23581 /* ECMAP5_CID_15 */ "", 23582 /* ECMAP6_CID_0 */ "", 23583 /* ECMAP6_CID_1 */ "", 23584 /* ECMAP6_CID_2 */ "", 23585 /* ECMAP6_CID_3 */ "", 23586 /* ECMAP6_CID_4 */ "", 23587 /* ECMAP6_CID_5 */ "", 23588 /* ECMAP6_CID_6 */ "", 23589 /* ECMAP6_CID_7 */ "", 23590 /* ECMAP6_CID_8 */ "", 23591 /* ECMAP6_CID_9 */ "", 23592 /* ECMAP6_CID_10 */ "", 23593 /* ECMAP6_CID_11 */ "", 23594 /* ECMAP6_CID_12 */ "", 23595 /* ECMAP6_CID_13 */ "", 23596 /* ECMAP6_CID_14 */ "", 23597 /* ECMAP6_CID_15 */ "", 23598 /* ECMAP7_CID_0 */ "", 23599 /* ECMAP7_CID_1 */ "", 23600 /* ECMAP7_CID_2 */ "", 23601 /* ECMAP7_CID_3 */ "", 23602 /* ECMAP7_CID_4 */ "", 23603 /* ECMAP7_CID_5 */ "", 23604 /* ECMAP7_CID_6 */ "", 23605 /* ECMAP7_CID_7 */ "", 23606 /* ECMAP7_CID_8 */ "", 23607 /* ECMAP7_CID_9 */ "", 23608 /* ECMAP7_CID_10 */ "", 23609 /* ECMAP7_CID_11 */ "", 23610 /* ECMAP7_CID_12 */ "", 23611 /* ECMAP7_CID_13 */ "", 23612 /* ECMAP7_CID_14 */ "", 23613 /* ECMAP7_CID_15 */ "", 23614 /* ECMAP8_CID_0 */ "", 23615 /* ECMAP8_CID_1 */ "", 23616 /* ECMAP8_CID_2 */ "", 23617 /* ECMAP8_CID_3 */ "", 23618 /* ECMAP8_CID_4 */ "", 23619 /* ECMAP8_CID_5 */ "", 23620 /* ECMAP8_CID_6 */ "", 23621 /* ECMAP8_CID_7 */ "", 23622 /* ECMAP8_CID_8 */ "", 23623 /* ECMAP8_CID_9 */ "", 23624 /* ECMAP8_CID_10 */ "", 23625 /* ECMAP8_CID_11 */ "", 23626 /* ECMAP8_CID_12 */ "", 23627 /* ECMAP8_CID_13 */ "", 23628 /* ECMAP8_CID_14 */ "", 23629 /* ECMAP8_CID_15 */ "", 23630 /* ECMAP9_CID_0 */ "", 23631 /* ECMAP9_CID_1 */ "", 23632 /* ECMAP9_CID_2 */ "", 23633 /* ECMAP9_CID_3 */ "", 23634 /* ECMAP9_CID_4 */ "", 23635 /* ECMAP9_CID_5 */ "", 23636 /* ECMAP9_CID_6 */ "", 23637 /* ECMAP9_CID_7 */ "", 23638 /* ECMAP9_CID_8 */ "", 23639 /* ECMAP9_CID_9 */ "", 23640 /* ECMAP9_CID_10 */ "", 23641 /* ECMAP9_CID_11 */ "", 23642 /* ECMAP9_CID_12 */ "", 23643 /* ECMAP9_CID_13 */ "", 23644 /* ECMAP9_CID_14 */ "", 23645 /* ECMAP9_CID_15 */ "", 23646 /* ECMP_CONFIG */ "", 23647 /* ECMP_CONFIG_2 */ "", 23648 /* ECMP_GROUP_DLB_ID_OFFSET */ "", 23649 /* ECMP_RANDOM_LB_CONFIG */ "", 23650 /* ECMP_RANDOM_LB_CONFIG_PIPE0 */ "", 23651 /* ECMP_RANDOM_LB_CONFIG_PIPE1 */ "", 23652 /* ECMP_RANDOM_LB_CONFIG_PIPE2 */ "", 23653 /* ECMP_RANDOM_LB_CONFIG_PIPE3 */ "", 23654 /* ECMP_RANDOM_LB_CONFIG_PIPE4 */ "", 23655 /* ECMP_RANDOM_LB_CONFIG_PIPE5 */ "", 23656 /* ECMP_RANDOM_LB_CONFIG_PIPE6 */ "", 23657 /* ECMP_RANDOM_LB_CONFIG_PIPE7 */ "", 23658 /* ECN_CONFIG */ "", 23659 /* ECN_CONTROL */ "", 23660 /* ECRC */ "", 23661 /* ECRC_LIMIT */ "", 23662 /* EDATABUF_DBG_MMU_INTF_RESET */ "", 23663 /* EDATABUF_DBG_PORT_INTF_RESET */ "", 23664 /* EDATABUF_DBG_SFT_RESET */ "", 23665 /* EDATABUF_MIN_STARTCNT */ "", 23666 /* EDATABUF_PARITY_CONTROL */ "", 23667 /* EDATABUF_RAM_CONTROL */ "", 23668 /* EDATABUF_RAM_CONTROL2 */ "", 23669 /* EDATABUF_RAM_CONTROL3 */ "", 23670 /* EDATABUF_RAM_CONTROL4 */ "", 23671 /* EDATABUF_RAM_CONTROL5 */ "", 23672 /* EDATABUF_RAM_CONTROL6 */ "", 23673 /* EDATABUF_RAM_CONTROL7 */ "", 23674 /* EDATABUF_RAM_CONTROL8 */ "", 23675 /* EDATABUF_RAM_CONTROL9 */ "", 23676 /* EDATABUF_RAM_CONTROL10 */ "", 23677 /* EDATABUF_RAM_CONTROL11 */ "", 23678 /* EDATABUF_RAM_DBGCTRL */ "EDATABUF_RAM_CONTROL", 23679 /* EDATABUF_XQP_FLEXPORT_CONFIG */ "", 23680 /* EDB_1DBG_A */ "EGR_FORCE_SAF_CONFIG", 23681 /* EDB_1DBG_A_PIPE0 */ "EGR_FORCE_SAF_CONFIG_PIPE0", 23682 /* EDB_1DBG_A_PIPE1 */ "EGR_FORCE_SAF_CONFIG_PIPE1", 23683 /* EDB_1DBG_A_PIPE2 */ "EGR_FORCE_SAF_CONFIG_PIPE2", 23684 /* EDB_1DBG_A_PIPE3 */ "EGR_FORCE_SAF_CONFIG_PIPE3", 23685 /* EDB_1DBG_C */ "EGR_FORCE_SAF_DEBUG", 23686 /* EDB_1DBG_C_PIPE0 */ "EGR_FORCE_SAF_DEBUG_PIPE0", 23687 /* EDB_1DBG_C_PIPE1 */ "EGR_FORCE_SAF_DEBUG_PIPE1", 23688 /* EDB_BANK_ELIG_BITMAP */ "", 23689 /* EDB_BUF_CFG_OVERRIDE */ "", 23690 /* EDB_BUF_CFG_OVERRIDE_PIPE0 */ "", 23691 /* EDB_BUF_CFG_OVERRIDE_PIPE1 */ "", 23692 /* EDB_BUF_CFG_OVERRIDE_PIPE2 */ "", 23693 /* EDB_BUF_CFG_OVERRIDE_PIPE3 */ "", 23694 /* EDB_BUF_CFG_OVERRIDE_PIPE4 */ "", 23695 /* EDB_BUF_CFG_OVERRIDE_PIPE5 */ "", 23696 /* EDB_BUF_CFG_OVERRIDE_PIPE6 */ "", 23697 /* EDB_BUF_CFG_OVERRIDE_PIPE7 */ "", 23698 /* EDB_CFG_BUILD_EES_FIFOS_FIXED_LATENCY_SETTING */ "", 23699 /* EDB_CFG_CUD_MAPPING_ENABLE */ "", 23700 /* EDB_CFG_EEDB_ARP_POINTER_MSB */ "", 23701 /* EDB_CFG_OUTRIF_MAX */ "", 23702 /* EDB_CONTROL_BUFFER_ECC_EN */ "", 23703 /* EDB_CONTROL_BUFFER_EN_COR_ERR_RPT */ "", 23704 /* EDB_DATA_BUFFER_ECC_EN */ "", 23705 /* EDB_DATA_BUFFER_EN_COR_ERR_RPT */ "", 23706 /* EDB_DBG_A */ "EDB_SPECIAL_DROP_CTRL", 23707 /* EDB_DBG_A_PIPE0 */ "EDB_SPECIAL_DROP_CTRL_PIPE0", 23708 /* EDB_DBG_A_PIPE1 */ "EDB_SPECIAL_DROP_CTRL_PIPE1", 23709 /* EDB_DBG_A_PIPE2 */ "EDB_SPECIAL_DROP_CTRL_PIPE2", 23710 /* EDB_DBG_A_PIPE3 */ "EDB_SPECIAL_DROP_CTRL_PIPE3", 23711 /* EDB_DBG_A_PIPE4 */ "EDB_SPECIAL_DROP_CTRL_PIPE4", 23712 /* EDB_DBG_A_PIPE5 */ "EDB_SPECIAL_DROP_CTRL_PIPE5", 23713 /* EDB_DBG_A_PIPE6 */ "EDB_SPECIAL_DROP_CTRL_PIPE6", 23714 /* EDB_DBG_A_PIPE7 */ "EDB_SPECIAL_DROP_CTRL_PIPE7", 23715 /* EDB_DBG_B */ "EDB_SPECIAL_DROP_CTRL_2", 23716 /* EDB_DBG_B_PIPE0 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE0", 23717 /* EDB_DBG_B_PIPE1 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE1", 23718 /* EDB_DBG_B_PIPE2 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE2", 23719 /* EDB_DBG_B_PIPE3 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE3", 23720 /* EDB_DBG_B_PIPE4 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE4", 23721 /* EDB_DBG_B_PIPE5 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE5", 23722 /* EDB_DBG_B_PIPE6 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE6", 23723 /* EDB_DBG_B_PIPE7 */ "EDB_SPECIAL_DROP_CTRL_2_PIPE7", 23724 /* EDB_DBG_C */ "EDB_FLEXPORT_EXTRA_HOLDING", 23725 /* EDB_DBG_C_PIPE0 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE0", 23726 /* EDB_DBG_C_PIPE1 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE1", 23727 /* EDB_DBG_C_PIPE2 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE2", 23728 /* EDB_DBG_C_PIPE3 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE3", 23729 /* EDB_DBG_C_PIPE4 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE4", 23730 /* EDB_DBG_C_PIPE5 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE5", 23731 /* EDB_DBG_C_PIPE6 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE6", 23732 /* EDB_DBG_C_PIPE7 */ "EDB_FLEXPORT_EXTRA_HOLDING_PIPE7", 23733 /* EDB_ECC_1B_ERR_CNT */ "", 23734 /* EDB_ECC_2B_ERR_CNT */ "", 23735 /* EDB_ECC_ERR_1B_INITIATE */ "", 23736 /* EDB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 23737 /* EDB_ECC_ERR_2B_INITIATE */ "", 23738 /* EDB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 23739 /* EDB_ECC_INTERRUPT_REGISTER */ "", 23740 /* EDB_ECC_INTERRUPT_REGISTER_MASK */ "", 23741 /* EDB_ECC_INTERRUPT_REGISTER_TEST */ "", 23742 /* EDB_EEDB_0_POINTER_CONFLICT_INT_REG */ "", 23743 /* EDB_EEDB_0_POINTER_CONFLICT_INT_REG_MASK */ "", 23744 /* EDB_EEDB_0_POINTER_CONFLICT_INT_REG_TEST */ "", 23745 /* EDB_EEDB_1_POINTER_CONFLICT_INT_REG */ "", 23746 /* EDB_EEDB_1_POINTER_CONFLICT_INT_REG_MASK */ "", 23747 /* EDB_EEDB_1_POINTER_CONFLICT_INT_REG_TEST */ "", 23748 /* EDB_EEDB_CHICKEN_BITS */ "", 23749 /* EDB_EEDB_OUTLIF_ACCESS */ "", 23750 /* EDB_EEDB_OUTLIF_BASE */ "", 23751 /* EDB_EEDB_POINTER_CONFLICT_INT_REG */ "", 23752 /* EDB_EEDB_POINTER_CONFLICT_INT_REG_MASK */ "", 23753 /* EDB_EEDB_POINTER_CONFLICT_INT_REG_TEST */ "", 23754 /* EDB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 23755 /* EDB_ERROR_INITIATION_DATA */ "", 23756 /* EDB_ESEM_0_CAM_ENTRIES_COUNTER */ "", 23757 /* EDB_ESEM_0_DEFRAG_CONFIGURATION_REGISTER */ "", 23758 /* EDB_ESEM_0_DIAGNOSTICS */ "", 23759 /* EDB_ESEM_0_DIAGNOSTICS_ACCESSED_MODE */ "", 23760 /* EDB_ESEM_0_DIAGNOSTICS_INDEX */ "", 23761 /* EDB_ESEM_0_DIAGNOSTICS_KEY */ "", 23762 /* EDB_ESEM_0_DIAGNOSTICS_LOOKUP_RESULT */ "", 23763 /* EDB_ESEM_0_DIAGNOSTICS_READ_RESULT */ "", 23764 /* EDB_ESEM_0_ENTRIES_COUNTER */ "", 23765 /* EDB_ESEM_0_ERROR_CAM_TABLE_FULL_COUNTER */ "", 23766 /* EDB_ESEM_0_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 23767 /* EDB_ESEM_0_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 23768 /* EDB_ESEM_0_ERROR_TABLE_COHERENCY_COUNTER */ "", 23769 /* EDB_ESEM_0_GENERAL_EM_CONFIGURATION_REGISTER */ "", 23770 /* EDB_ESEM_0_INTERRUPT_MASK_REGISTER_ONE */ "", 23771 /* EDB_ESEM_0_INTERRUPT_REGISTER_ONE */ "", 23772 /* EDB_ESEM_0_INTERRUPT_REGISTER_ONE_TEST */ "", 23773 /* EDB_ESEM_0_KEY_TABLE_ENTRY_LIMIT */ "", 23774 /* EDB_ESEM_0_KILL_RESET_SEQUENCE */ "", 23775 /* EDB_ESEM_0_LAST_LOOKUP */ "", 23776 /* EDB_ESEM_0_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 23777 /* EDB_ESEM_0_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 23778 /* EDB_ESEM_0_MANAGEMENT_UNIT_FAILURE */ "", 23779 /* EDB_ESEM_0_REQUESTS_COUNTER */ "", 23780 /* EDB_ESEM_0_RESET_STATUS_REGISTER */ "", 23781 /* EDB_ESEM_0_WARNING_INSERTED_EXISTING_COUNTER */ "", 23782 /* EDB_ESEM_1_CAM_ENTRIES_COUNTER */ "", 23783 /* EDB_ESEM_1_DEFRAG_CONFIGURATION_REGISTER */ "", 23784 /* EDB_ESEM_1_DIAGNOSTICS */ "", 23785 /* EDB_ESEM_1_DIAGNOSTICS_ACCESSED_MODE */ "", 23786 /* EDB_ESEM_1_DIAGNOSTICS_INDEX */ "", 23787 /* EDB_ESEM_1_DIAGNOSTICS_KEY */ "", 23788 /* EDB_ESEM_1_DIAGNOSTICS_LOOKUP_RESULT */ "", 23789 /* EDB_ESEM_1_DIAGNOSTICS_READ_RESULT */ "", 23790 /* EDB_ESEM_1_ENTRIES_COUNTER */ "", 23791 /* EDB_ESEM_1_ERROR_CAM_TABLE_FULL_COUNTER */ "", 23792 /* EDB_ESEM_1_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 23793 /* EDB_ESEM_1_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 23794 /* EDB_ESEM_1_ERROR_TABLE_COHERENCY_COUNTER */ "", 23795 /* EDB_ESEM_1_GENERAL_EM_CONFIGURATION_REGISTER */ "", 23796 /* EDB_ESEM_1_INTERRUPT_MASK_REGISTER_ONE */ "", 23797 /* EDB_ESEM_1_INTERRUPT_REGISTER_ONE */ "", 23798 /* EDB_ESEM_1_INTERRUPT_REGISTER_ONE_TEST */ "", 23799 /* EDB_ESEM_1_KEY_TABLE_ENTRY_LIMIT */ "", 23800 /* EDB_ESEM_1_KILL_RESET_SEQUENCE */ "", 23801 /* EDB_ESEM_1_LAST_LOOKUP */ "", 23802 /* EDB_ESEM_1_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 23803 /* EDB_ESEM_1_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 23804 /* EDB_ESEM_1_MANAGEMENT_UNIT_FAILURE */ "", 23805 /* EDB_ESEM_1_REQUESTS_COUNTER */ "", 23806 /* EDB_ESEM_1_RESET_STATUS_REGISTER */ "", 23807 /* EDB_ESEM_1_WARNING_INSERTED_EXISTING_COUNTER */ "", 23808 /* EDB_ESEM_CAM_ENTRIES_COUNTER */ "", 23809 /* EDB_ESEM_DEFRAG_CONFIGURATION_REGISTER */ "", 23810 /* EDB_ESEM_DIAGNOSTICS */ "", 23811 /* EDB_ESEM_DIAGNOSTICS_ACCESSED_MODE */ "", 23812 /* EDB_ESEM_DIAGNOSTICS_INDEX */ "", 23813 /* EDB_ESEM_DIAGNOSTICS_KEY */ "", 23814 /* EDB_ESEM_DIAGNOSTICS_LOOKUP_RESULT */ "", 23815 /* EDB_ESEM_DIAGNOSTICS_READ_RESULT */ "", 23816 /* EDB_ESEM_ENTRIES_COUNTER */ "", 23817 /* EDB_ESEM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 23818 /* EDB_ESEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 23819 /* EDB_ESEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 23820 /* EDB_ESEM_ERROR_TABLE_COHERENCY_COUNTER */ "", 23821 /* EDB_ESEM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 23822 /* EDB_ESEM_INTERRUPT_MASK_REGISTER_ONE */ "", 23823 /* EDB_ESEM_INTERRUPT_REGISTER_ONE */ "", 23824 /* EDB_ESEM_INTERRUPT_REGISTER_ONE_TEST */ "", 23825 /* EDB_ESEM_KEY_TABLE_ENTRY_LIMIT */ "", 23826 /* EDB_ESEM_KILL_RESET_SEQUENCE */ "", 23827 /* EDB_ESEM_LAST_LOOKUP */ "", 23828 /* EDB_ESEM_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 23829 /* EDB_ESEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 23830 /* EDB_ESEM_MANAGEMENT_UNIT_FAILURE */ "", 23831 /* EDB_ESEM_MNGMNT_SER_INDICATION */ "", 23832 /* EDB_ESEM_REQUESTS_COUNTER */ "", 23833 /* EDB_ESEM_RESET_STATUS_REGISTER */ "", 23834 /* EDB_ESEM_SER_DISABLES_MNGMNT */ "", 23835 /* EDB_ESEM_WARNING_INSERTED_EXISTING_COUNTER */ "", 23836 /* EDB_FBC_FREE_CNT */ "", 23837 /* EDB_FBM_REG */ "", 23838 /* EDB_FQP_RD_0_REQ_CNT */ "", 23839 /* EDB_FQP_RD_1_REQ_CNT */ "", 23840 /* EDB_GLEM_CAM_ENTRIES_COUNTER */ "", 23841 /* EDB_GLEM_DEFRAG_CONFIGURATION_REGISTER */ "", 23842 /* EDB_GLEM_DIAGNOSTICS */ "", 23843 /* EDB_GLEM_DIAGNOSTICS_ACCESSED_MODE */ "", 23844 /* EDB_GLEM_DIAGNOSTICS_INDEX */ "", 23845 /* EDB_GLEM_DIAGNOSTICS_KEY */ "", 23846 /* EDB_GLEM_DIAGNOSTICS_LOOKUP_RESULT */ "", 23847 /* EDB_GLEM_DIAGNOSTICS_READ_RESULT */ "", 23848 /* EDB_GLEM_ENTRIES_COUNTER */ "", 23849 /* EDB_GLEM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 23850 /* EDB_GLEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 23851 /* EDB_GLEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 23852 /* EDB_GLEM_ERROR_TABLE_COHERENCY_COUNTER */ "", 23853 /* EDB_GLEM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 23854 /* EDB_GLEM_INTERRUPT_MASK_REGISTER_ONE */ "", 23855 /* EDB_GLEM_INTERRUPT_REGISTER_ONE */ "", 23856 /* EDB_GLEM_INTERRUPT_REGISTER_ONE_TEST */ "", 23857 /* EDB_GLEM_KEY_TABLE_ENTRY_LIMIT */ "", 23858 /* EDB_GLEM_KILL_RESET_SEQUENCE */ "", 23859 /* EDB_GLEM_LAST_LOOKUP */ "", 23860 /* EDB_GLEM_LAST_LOOKUP_MASTER */ "", 23861 /* EDB_GLEM_LAST_LOOKUP_SLAVE */ "", 23862 /* EDB_GLEM_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 23863 /* EDB_GLEM_LOOKUP_ARBITER_LOOKUP_COUNTER_MASTER */ "", 23864 /* EDB_GLEM_LOOKUP_ARBITER_LOOKUP_COUNTER_SLAVE */ "", 23865 /* EDB_GLEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 23866 /* EDB_GLEM_MANAGEMENT_UNIT_FAILURE */ "", 23867 /* EDB_GLEM_MNGMNT_SER_INDICATION */ "", 23868 /* EDB_GLEM_REQUESTS_COUNTER */ "", 23869 /* EDB_GLEM_RESET_STATUS_REGISTER */ "", 23870 /* EDB_GLEM_SER_DISABLES_MNGMNT */ "", 23871 /* EDB_GLEM_WARNING_INSERTED_EXISTING_COUNTER */ "", 23872 /* EDB_GLOBAL_GENERAL_CFG_2 */ "", 23873 /* EDB_GLOBAL_MEM_OPTIONS */ "", 23874 /* EDB_GTIMER_CONFIGURATION */ "", 23875 /* EDB_GTIMER_CYCLE */ "", 23876 /* EDB_GTIMER_TRIGGER */ "", 23877 /* EDB_INDIRECT_COMMAND */ "", 23878 /* EDB_INDIRECT_COMMAND_ADDRESS */ "", 23879 /* EDB_INDIRECT_COMMAND_DATA_INCREMENT */ "", 23880 /* EDB_INDIRECT_COMMAND_RD_DATA */ "", 23881 /* EDB_INDIRECT_COMMAND_WIDE_MEM */ "", 23882 /* EDB_INDIRECT_COMMAND_WR_DATA */ "", 23883 /* EDB_INDIRECT_FORCE_BUBBLE */ "", 23884 /* EDB_INDIRECT_WR_MASK */ "", 23885 /* EDB_INTERRUPT_MASK_REGISTER */ "", 23886 /* EDB_INTERRUPT_REGISTER */ "", 23887 /* EDB_INTERRUPT_REGISTER_TEST */ "", 23888 /* EDB_INTR_ENABLE */ "", 23889 /* EDB_INTR_STATUS */ "", 23890 /* EDB_INTR_STATUS_PIPE0 */ "", 23891 /* EDB_INTR_STATUS_PIPE1 */ "", 23892 /* EDB_INTR_STATUS_PIPE2 */ "", 23893 /* EDB_INTR_STATUS_PIPE3 */ "", 23894 /* EDB_INTR_STATUS_PIPE4 */ "", 23895 /* EDB_INTR_STATUS_PIPE5 */ "", 23896 /* EDB_INTR_STATUS_PIPE6 */ "", 23897 /* EDB_INTR_STATUS_PIPE7 */ "", 23898 /* EDB_MISC_CTRL */ "", 23899 /* EDB_MISC_CTRL_PIPE0 */ "", 23900 /* EDB_MISC_CTRL_PIPE1 */ "", 23901 /* EDB_MISC_CTRL_PIPE2 */ "", 23902 /* EDB_MISC_CTRL_PIPE3 */ "", 23903 /* EDB_MISC_CTRL_PIPE4 */ "", 23904 /* EDB_MISC_CTRL_PIPE5 */ "", 23905 /* EDB_MISC_CTRL_PIPE6 */ "", 23906 /* EDB_MISC_CTRL_PIPE7 */ "", 23907 /* EDB_PARITY_ERR_CNT */ "", 23908 /* EDB_PAR_ERR_INITIATE */ "", 23909 /* EDB_PAR_ERR_MEM_MASK */ "", 23910 /* EDB_PCMI_0 */ "", 23911 /* EDB_PCMI_1 */ "", 23912 /* EDB_PCMI_2 */ "", 23913 /* EDB_PCMI_3 */ "", 23914 /* EDB_PCMI_4 */ "", 23915 /* EDB_PCMI_0_S */ "", 23916 /* EDB_PCMI_0_T */ "", 23917 /* EDB_PCMI_1_S */ "", 23918 /* EDB_PCMI_1_T */ "", 23919 /* EDB_PCMI_2_S */ "", 23920 /* EDB_PCMI_2_T */ "", 23921 /* EDB_PCMI_3_S */ "", 23922 /* EDB_PCMI_3_T */ "", 23923 /* EDB_PCMI_4_S */ "", 23924 /* EDB_PCMI_4_T */ "", 23925 /* EDB_PM0_BUF_START_END_ADDR_0_1 */ "", 23926 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE0 */ "", 23927 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE1 */ "", 23928 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE2 */ "", 23929 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE3 */ "", 23930 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE4 */ "", 23931 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE5 */ "", 23932 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE6 */ "", 23933 /* EDB_PM0_BUF_START_END_ADDR_0_1_PIPE7 */ "", 23934 /* EDB_PM0_BUF_START_END_ADDR_2_3 */ "", 23935 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE0 */ "", 23936 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE1 */ "", 23937 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE2 */ "", 23938 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE3 */ "", 23939 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE4 */ "", 23940 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE5 */ "", 23941 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE6 */ "", 23942 /* EDB_PM0_BUF_START_END_ADDR_2_3_PIPE7 */ "", 23943 /* EDB_PM0_BUF_START_END_ADDR_4_5 */ "", 23944 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE0 */ "", 23945 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE1 */ "", 23946 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE2 */ "", 23947 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE3 */ "", 23948 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE4 */ "", 23949 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE5 */ "", 23950 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE6 */ "", 23951 /* EDB_PM0_BUF_START_END_ADDR_4_5_PIPE7 */ "", 23952 /* EDB_PM0_BUF_START_END_ADDR_6_7 */ "", 23953 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE0 */ "", 23954 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE1 */ "", 23955 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE2 */ "", 23956 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE3 */ "", 23957 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE4 */ "", 23958 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE5 */ "", 23959 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE6 */ "", 23960 /* EDB_PM0_BUF_START_END_ADDR_6_7_PIPE7 */ "", 23961 /* EDB_PM1_BUF_START_END_ADDR_0_1 */ "", 23962 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE0 */ "", 23963 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE1 */ "", 23964 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE2 */ "", 23965 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE3 */ "", 23966 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE4 */ "", 23967 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE5 */ "", 23968 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE6 */ "", 23969 /* EDB_PM1_BUF_START_END_ADDR_0_1_PIPE7 */ "", 23970 /* EDB_PM1_BUF_START_END_ADDR_2_3 */ "", 23971 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE0 */ "", 23972 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE1 */ "", 23973 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE2 */ "", 23974 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE3 */ "", 23975 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE4 */ "", 23976 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE5 */ "", 23977 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE6 */ "", 23978 /* EDB_PM1_BUF_START_END_ADDR_2_3_PIPE7 */ "", 23979 /* EDB_PM1_BUF_START_END_ADDR_4_5 */ "", 23980 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE0 */ "", 23981 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE1 */ "", 23982 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE2 */ "", 23983 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE3 */ "", 23984 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE4 */ "", 23985 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE5 */ "", 23986 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE6 */ "", 23987 /* EDB_PM1_BUF_START_END_ADDR_4_5_PIPE7 */ "", 23988 /* EDB_PM1_BUF_START_END_ADDR_6_7 */ "", 23989 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE0 */ "", 23990 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE1 */ "", 23991 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE2 */ "", 23992 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE3 */ "", 23993 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE4 */ "", 23994 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE5 */ "", 23995 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE6 */ "", 23996 /* EDB_PM1_BUF_START_END_ADDR_6_7_PIPE7 */ "", 23997 /* EDB_PM2_BUF_START_END_ADDR_0_1 */ "", 23998 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE0 */ "", 23999 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE1 */ "", 24000 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE2 */ "", 24001 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE3 */ "", 24002 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE4 */ "", 24003 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE5 */ "", 24004 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE6 */ "", 24005 /* EDB_PM2_BUF_START_END_ADDR_0_1_PIPE7 */ "", 24006 /* EDB_PM2_BUF_START_END_ADDR_2_3 */ "", 24007 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE0 */ "", 24008 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE1 */ "", 24009 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE2 */ "", 24010 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE3 */ "", 24011 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE4 */ "", 24012 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE5 */ "", 24013 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE6 */ "", 24014 /* EDB_PM2_BUF_START_END_ADDR_2_3_PIPE7 */ "", 24015 /* EDB_PM2_BUF_START_END_ADDR_4_5 */ "", 24016 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE0 */ "", 24017 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE1 */ "", 24018 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE2 */ "", 24019 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE3 */ "", 24020 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE4 */ "", 24021 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE5 */ "", 24022 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE6 */ "", 24023 /* EDB_PM2_BUF_START_END_ADDR_4_5_PIPE7 */ "", 24024 /* EDB_PM2_BUF_START_END_ADDR_6_7 */ "", 24025 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE0 */ "", 24026 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE1 */ "", 24027 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE2 */ "", 24028 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE3 */ "", 24029 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE4 */ "", 24030 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE5 */ "", 24031 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE6 */ "", 24032 /* EDB_PM2_BUF_START_END_ADDR_6_7_PIPE7 */ "", 24033 /* EDB_PM3_BUF_START_END_ADDR_0_1 */ "", 24034 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE0 */ "", 24035 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE1 */ "", 24036 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE2 */ "", 24037 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE3 */ "", 24038 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE4 */ "", 24039 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE5 */ "", 24040 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE6 */ "", 24041 /* EDB_PM3_BUF_START_END_ADDR_0_1_PIPE7 */ "", 24042 /* EDB_PM3_BUF_START_END_ADDR_2_3 */ "", 24043 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE0 */ "", 24044 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE1 */ "", 24045 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE2 */ "", 24046 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE3 */ "", 24047 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE4 */ "", 24048 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE5 */ "", 24049 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE6 */ "", 24050 /* EDB_PM3_BUF_START_END_ADDR_2_3_PIPE7 */ "", 24051 /* EDB_PM3_BUF_START_END_ADDR_4_5 */ "", 24052 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE0 */ "", 24053 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE1 */ "", 24054 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE2 */ "", 24055 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE3 */ "", 24056 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE4 */ "", 24057 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE5 */ "", 24058 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE6 */ "", 24059 /* EDB_PM3_BUF_START_END_ADDR_4_5_PIPE7 */ "", 24060 /* EDB_PM3_BUF_START_END_ADDR_6_7 */ "", 24061 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE0 */ "", 24062 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE1 */ "", 24063 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE2 */ "", 24064 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE3 */ "", 24065 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE4 */ "", 24066 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE5 */ "", 24067 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE6 */ "", 24068 /* EDB_PM3_BUF_START_END_ADDR_6_7_PIPE7 */ "", 24069 /* EDB_PORT_MODE_OVERRIDE */ "", 24070 /* EDB_PORT_MODE_OVERRIDE_PIPE0 */ "", 24071 /* EDB_PORT_MODE_OVERRIDE_PIPE1 */ "", 24072 /* EDB_PORT_MODE_OVERRIDE_PIPE2 */ "", 24073 /* EDB_PORT_MODE_OVERRIDE_PIPE3 */ "", 24074 /* EDB_PORT_MODE_OVERRIDE_PIPE4 */ "", 24075 /* EDB_PORT_MODE_OVERRIDE_PIPE5 */ "", 24076 /* EDB_PORT_MODE_OVERRIDE_PIPE6 */ "", 24077 /* EDB_PORT_MODE_OVERRIDE_PIPE7 */ "", 24078 /* EDB_RAM_TM_CONTROL_0 */ "", 24079 /* EDB_RAM_TM_CONTROL_1 */ "", 24080 /* EDB_RAM_TM_CONTROL_0_PIPE0 */ "", 24081 /* EDB_RAM_TM_CONTROL_0_PIPE1 */ "", 24082 /* EDB_RAM_TM_CONTROL_0_PIPE2 */ "", 24083 /* EDB_RAM_TM_CONTROL_0_PIPE3 */ "", 24084 /* EDB_RAM_TM_CONTROL_0_PIPE4 */ "", 24085 /* EDB_RAM_TM_CONTROL_0_PIPE5 */ "", 24086 /* EDB_RAM_TM_CONTROL_0_PIPE6 */ "", 24087 /* EDB_RAM_TM_CONTROL_0_PIPE7 */ "", 24088 /* EDB_RAM_TM_CONTROL_1_PIPE0 */ "", 24089 /* EDB_RAM_TM_CONTROL_1_PIPE1 */ "", 24090 /* EDB_RAM_TM_CONTROL_1_PIPE2 */ "", 24091 /* EDB_RAM_TM_CONTROL_1_PIPE3 */ "", 24092 /* EDB_RAM_TM_CONTROL_1_PIPE4 */ "", 24093 /* EDB_RAM_TM_CONTROL_1_PIPE5 */ "", 24094 /* EDB_RAM_TM_CONTROL_1_PIPE6 */ "", 24095 /* EDB_RAM_TM_CONTROL_1_PIPE7 */ "", 24096 /* EDB_REG_0041 */ "", 24097 /* EDB_REG_00A4 */ "", 24098 /* EDB_REG_00A6 */ "", 24099 /* EDB_REG_00C2 */ "", 24100 /* EDB_RESERVED_MIRROR_ADDR */ "", 24101 /* EDB_RESERVED_MTCD */ "", 24102 /* EDB_RESERVED_MTCP */ "", 24103 /* EDB_RESERVED_PCMI_0 */ "", 24104 /* EDB_RESERVED_PCMI_1 */ "", 24105 /* EDB_RESERVED_PCMI_2 */ "", 24106 /* EDB_RESERVED_PCMI_3 */ "", 24107 /* EDB_RESERVED_PCMI_4 */ "", 24108 /* EDB_RESERVED_PCMI_0_S */ "", 24109 /* EDB_RESERVED_PCMI_0_T */ "", 24110 /* EDB_RESERVED_PCMI_1_S */ "", 24111 /* EDB_RESERVED_PCMI_1_T */ "", 24112 /* EDB_RESERVED_PCMI_2_S */ "", 24113 /* EDB_RESERVED_PCMI_2_T */ "", 24114 /* EDB_RESERVED_PCMI_3_S */ "", 24115 /* EDB_RESERVED_PCMI_3_T */ "", 24116 /* EDB_RESERVED_PCMI_4_S */ "", 24117 /* EDB_RESERVED_PCMI_4_T */ "", 24118 /* EDB_RESERVED_SPARE_0 */ "", 24119 /* EDB_RESERVED_SPARE_1 */ "", 24120 /* EDB_RESERVED_SPARE_2 */ "", 24121 /* EDB_RESERVED_SPARE_3 */ "", 24122 /* EDB_RQP_WR_0_REQ_CNT */ "", 24123 /* EDB_RQP_WR_0_RES_CNT */ "", 24124 /* EDB_RQP_WR_0_RES_ERR_CNT */ "", 24125 /* EDB_RQP_WR_1_REQ_CNT */ "", 24126 /* EDB_RQP_WR_1_RES_CNT */ "", 24127 /* EDB_RQP_WR_1_RES_ERR_CNT */ "", 24128 /* EDB_SBUS_BROADCAST_ID */ "", 24129 /* EDB_SBUS_LAST_IN_CHAIN */ "", 24130 /* EDB_SER_FIFO_CTRL */ "", 24131 /* EDB_SER_FIFO_CTRL_PIPE0 */ "", 24132 /* EDB_SER_FIFO_CTRL_PIPE1 */ "", 24133 /* EDB_SER_FIFO_CTRL_PIPE2 */ "", 24134 /* EDB_SER_FIFO_CTRL_PIPE3 */ "", 24135 /* EDB_SER_FIFO_CTRL_PIPE4 */ "", 24136 /* EDB_SER_FIFO_CTRL_PIPE5 */ "", 24137 /* EDB_SER_FIFO_CTRL_PIPE6 */ "", 24138 /* EDB_SER_FIFO_CTRL_PIPE7 */ "", 24139 /* EDB_SER_FIFO_STATUS */ "", 24140 /* EDB_SER_FIFO_STATUS_PIPE0 */ "", 24141 /* EDB_SER_FIFO_STATUS_PIPE1 */ "", 24142 /* EDB_SER_FIFO_STATUS_PIPE2 */ "", 24143 /* EDB_SER_FIFO_STATUS_PIPE3 */ "", 24144 /* EDB_SER_FIFO_STATUS_PIPE4 */ "", 24145 /* EDB_SER_FIFO_STATUS_PIPE5 */ "", 24146 /* EDB_SER_FIFO_STATUS_PIPE6 */ "", 24147 /* EDB_SER_FIFO_STATUS_PIPE7 */ "", 24148 /* EDB_SPECIAL_CLOCK_CONTROLS */ "", 24149 /* EDB_SPECIAL_DROP_DEBUG */ "", 24150 /* EDB_SPECIAL_DROP_DEBUG_PIPE0 */ "", 24151 /* EDB_SPECIAL_DROP_DEBUG_PIPE1 */ "", 24152 /* EDB_SPECIAL_DROP_DEBUG_PIPE2 */ "", 24153 /* EDB_SPECIAL_DROP_DEBUG_PIPE3 */ "", 24154 /* EDB_SPECIAL_DROP_DEBUG_PIPE4 */ "", 24155 /* EDB_SPECIAL_DROP_DEBUG_PIPE5 */ "", 24156 /* EDB_SPECIAL_DROP_DEBUG_PIPE6 */ "", 24157 /* EDB_SPECIAL_DROP_DEBUG_PIPE7 */ "", 24158 /* EDB_WBS_CONFIG */ "", 24159 /* EDB_XOR_INIT_DONE */ "", 24160 /* EEE_BB_ENABLE */ "", 24161 /* EEE_BB_ENABLE_0 */ "", 24162 /* EEE_BB_ENABLE_1 */ "", 24163 /* EEE_BB_ENABLE_2 */ "", 24164 /* EEE_BB_TX_N */ "", 24165 /* EEE_BB_TX_N_0 */ "", 24166 /* EEE_BB_TX_N_1 */ "", 24167 /* EEE_BB_TX_N_2 */ "", 24168 /* EEE_DELAY_ENTRY_TIMER */ "", 24169 /* EEE_GLOBAL_BUF_THRESH */ "", 24170 /* EEE_LIMIT_STATE */ "", 24171 /* EEE_LIMIT_STATE_0 */ "", 24172 /* EEE_LIMIT_STATE_1 */ "", 24173 /* EEE_LIMIT_STATE_2 */ "", 24174 /* EEE_LPI_STATE */ "", 24175 /* EEE_LPI_STATE_0 */ "", 24176 /* EEE_LPI_STATE_1 */ "", 24177 /* EEE_LPI_STATE_2 */ "", 24178 /* EEE_MAX_PKT_LAT_0 */ "", 24179 /* EEE_MAX_PKT_LAT_1 */ "", 24180 /* EEE_MAX_PKT_LAT_2 */ "", 24181 /* EEE_MAX_PKT_LAT_3 */ "", 24182 /* EEE_PKT_TIMER_0 */ "", 24183 /* EEE_PKT_TIMER_1 */ "", 24184 /* EEE_PKT_TIMER_2 */ "", 24185 /* EEE_PKT_TIMER_3 */ "", 24186 /* EEE_PKT_TIMER_4 */ "", 24187 /* EEE_PKT_TIMER_5 */ "", 24188 /* EEE_PKT_TIMER_6 */ "", 24189 /* EEE_PKT_TIMER_7 */ "", 24190 /* EEE_PROFILE_SEL */ "", 24191 /* EEE_PROFILE_SEL_0 */ "", 24192 /* EEE_PROFILE_SEL_1 */ "", 24193 /* EEE_PROFILE_SEL_2 */ "", 24194 /* EEE_PROFILE_SEL_3 */ "", 24195 /* EEE_PROFILE_SEL_4 */ "", 24196 /* EEE_PROFILE_SEL_5 */ "", 24197 /* EEE_PROFILE_SEL_6 */ "", 24198 /* EEE_PROFILE_SEL_7 */ "", 24199 /* EEE_PROFILE_SEL_QLAYER */ "", 24200 /* EEE_QUEUE_THRESH_0 */ "", 24201 /* EEE_QUEUE_THRESH_1 */ "", 24202 /* EEE_QUEUE_THRESH_2 */ "", 24203 /* EEE_QUEUE_THRESH_3 */ "", 24204 /* EEE_WAKE_TIMER */ "", 24205 /* EFPMOD_MCPE_CONTROL */ "", 24206 /* EFPMOD_RAM_CONTROL_0 */ "", 24207 /* EFP_BUS_PARITY_CONTROL */ "", 24208 /* EFP_BUS_PARITY_ERROR */ "", 24209 /* EFP_CAM_BIST_CONFIG */ "", 24210 /* EFP_CAM_BIST_CONFIG_PIPE0 */ "", 24211 /* EFP_CAM_BIST_CONFIG_PIPE1 */ "", 24212 /* EFP_CAM_BIST_CONFIG_PIPE2 */ "", 24213 /* EFP_CAM_BIST_CONFIG_PIPE3 */ "", 24214 /* EFP_CAM_BIST_CONTROL */ "", 24215 /* EFP_CAM_BIST_DBG_DATA */ "", 24216 /* EFP_CAM_BIST_DBG_DATA_PIPE0 */ "", 24217 /* EFP_CAM_BIST_DBG_DATA_PIPE1 */ "", 24218 /* EFP_CAM_BIST_DBG_DATA_PIPE2 */ "", 24219 /* EFP_CAM_BIST_DBG_DATA_PIPE3 */ "", 24220 /* EFP_CAM_BIST_DEBUG_DATA_VALID */ "", 24221 /* EFP_CAM_BIST_DEBUG_SEND */ "", 24222 /* EFP_CAM_BIST_ENABLE */ "", 24223 /* EFP_CAM_BIST_S10_STATUS */ "", 24224 /* EFP_CAM_BIST_S12_STATUS */ "", 24225 /* EFP_CAM_BIST_S14_STATUS */ "", 24226 /* EFP_CAM_BIST_S15_STATUS */ "", 24227 /* EFP_CAM_BIST_S2_STATUS */ "", 24228 /* EFP_CAM_BIST_S3_STATUS */ "", 24229 /* EFP_CAM_BIST_S5_STATUS */ "", 24230 /* EFP_CAM_BIST_S6_STATUS */ "", 24231 /* EFP_CAM_BIST_S8_STATUS */ "", 24232 /* EFP_CAM_BIST_STATUS */ "", 24233 /* EFP_CAM_BIST_STATUS_PIPE0 */ "", 24234 /* EFP_CAM_BIST_STATUS_PIPE1 */ "", 24235 /* EFP_CAM_BIST_STATUS_PIPE2 */ "", 24236 /* EFP_CAM_BIST_STATUS_PIPE3 */ "", 24237 /* EFP_CAM_CONTROL_3_THRU_0 */ "", 24238 /* EFP_CAM_DEBUG_DATA_0 */ "", 24239 /* EFP_CAM_DEBUG_DATA_1 */ "", 24240 /* EFP_CAM_DEBUG_DATA_2 */ "", 24241 /* EFP_CAM_DEBUG_DATA_3 */ "", 24242 /* EFP_CAM_DEBUG_DATA_4 */ "", 24243 /* EFP_CAM_DEBUG_DATA_5 */ "", 24244 /* EFP_CAM_DEBUG_GLOBAL_MASK */ "", 24245 /* EFP_CAM_DEBUG_SEND */ "", 24246 /* EFP_CLASSID_B_SELECTOR_KEY_TYPE */ "", 24247 /* EFP_CLASSID_B_SELECTOR_KEY_TYPE_PIPE0 */ "", 24248 /* EFP_CLASSID_B_SELECTOR_KEY_TYPE_PIPE1 */ "", 24249 /* EFP_CLASSID_SELECTOR */ "", 24250 /* EFP_CLASSID_SELECTOR_A */ "", 24251 /* EFP_CLASSID_SELECTOR_A_PIPE0 */ "", 24252 /* EFP_CLASSID_SELECTOR_A_PIPE1 */ "", 24253 /* EFP_CLASSID_SELECTOR_PIPE0 */ "", 24254 /* EFP_CLASSID_SELECTOR_PIPE1 */ "", 24255 /* EFP_CLASSID_SELECTOR_PIPE2 */ "", 24256 /* EFP_CLASSID_SELECTOR_PIPE3 */ "", 24257 /* EFP_CLASSID_SELECTOR_PIPE4 */ "", 24258 /* EFP_CLASSID_SELECTOR_PIPE5 */ "", 24259 /* EFP_CLASSID_SELECTOR_PIPE6 */ "", 24260 /* EFP_CLASSID_SELECTOR_PIPE7 */ "", 24261 /* EFP_COUNTER_TABLE_PARITY_STATUS */ "", 24262 /* EFP_DEST_PORT_SELECTOR */ "", 24263 /* EFP_DEST_PORT_SELECTOR_PIPE0 */ "", 24264 /* EFP_DEST_PORT_SELECTOR_PIPE1 */ "", 24265 /* EFP_KEY4_DVP_SELECTOR */ "", 24266 /* EFP_KEY4_DVP_SELECTOR_PIPE0 */ "", 24267 /* EFP_KEY4_DVP_SELECTOR_PIPE1 */ "", 24268 /* EFP_KEY4_DVP_SELECTOR_PIPE2 */ "", 24269 /* EFP_KEY4_DVP_SELECTOR_PIPE3 */ "", 24270 /* EFP_KEY4_L3_CLASSID_SELECTOR */ "", 24271 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE0 */ "", 24272 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE1 */ "", 24273 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE2 */ "", 24274 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE3 */ "", 24275 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE4 */ "", 24276 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE5 */ "", 24277 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE6 */ "", 24278 /* EFP_KEY4_L3_CLASSID_SELECTOR_PIPE7 */ "", 24279 /* EFP_KEY4_MDL_SELECTOR */ "", 24280 /* EFP_KEY4_MDL_SELECTOR_PIPE0 */ "", 24281 /* EFP_KEY4_MDL_SELECTOR_PIPE1 */ "", 24282 /* EFP_KEY4_MDL_SELECTOR_PIPE2 */ "", 24283 /* EFP_KEY4_MDL_SELECTOR_PIPE3 */ "", 24284 /* EFP_KEY4_MDL_SELECTOR_PIPE4 */ "", 24285 /* EFP_KEY4_MDL_SELECTOR_PIPE5 */ "", 24286 /* EFP_KEY4_MDL_SELECTOR_PIPE6 */ "", 24287 /* EFP_KEY4_MDL_SELECTOR_PIPE7 */ "", 24288 /* EFP_KEY8_DVP_SELECTOR */ "", 24289 /* EFP_KEY8_DVP_SELECTOR_PIPE0 */ "", 24290 /* EFP_KEY8_DVP_SELECTOR_PIPE1 */ "", 24291 /* EFP_KEY8_DVP_SELECTOR_PIPE2 */ "", 24292 /* EFP_KEY8_DVP_SELECTOR_PIPE3 */ "", 24293 /* EFP_KEY8_L3_CLASSID_SELECTOR */ "", 24294 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE0 */ "", 24295 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE1 */ "", 24296 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE2 */ "", 24297 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE3 */ "", 24298 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE4 */ "", 24299 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE5 */ "", 24300 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE6 */ "", 24301 /* EFP_KEY8_L3_CLASSID_SELECTOR_PIPE7 */ "", 24302 /* EFP_METER_CONTROL */ "", 24303 /* EFP_METER_CONTROL_2 */ "", 24304 /* EFP_METER_CONTROL_PIPE0 */ "", 24305 /* EFP_METER_CONTROL_PIPE1 */ "", 24306 /* EFP_METER_CONTROL_PIPE2 */ "", 24307 /* EFP_METER_CONTROL_PIPE3 */ "", 24308 /* EFP_METER_PARITY_CONTROL */ "", 24309 /* EFP_METER_PARITY_STATUS_INTR */ "", 24310 /* EFP_METER_PARITY_STATUS_NACK */ "", 24311 /* EFP_METER_TABLE_PARITY_CONTROL */ "", 24312 /* EFP_METER_TABLE_PARITY_STATUS */ "", 24313 /* EFP_METER_TM_CONTROL */ "", 24314 /* EFP_PARITY_CONTROL */ "", 24315 /* EFP_POLICY_PARITY_CONTROL */ "", 24316 /* EFP_POLICY_PARITY_STATUS_INTR */ "", 24317 /* EFP_POLICY_PARITY_STATUS_NACK */ "", 24318 /* EFP_POLICY_PDA */ "", 24319 /* EFP_POLICY_TABLE_PARITY_CONTROL */ "", 24320 /* EFP_POLICY_TABLE_PARITY_STATUS */ "", 24321 /* EFP_RAM_CONTROL */ "", 24322 /* EFP_RAM_CONTROL_0 */ "", 24323 /* EFP_RAM_CONTROL_1 */ "", 24324 /* EFP_RAM_CONTROL_2 */ "", 24325 /* EFP_RAM_CONTROL_3 */ "", 24326 /* EFP_RAM_CONTROL_4 */ "", 24327 /* EFP_RAM_CONTROL_5 */ "", 24328 /* EFP_RAM_CONTROL_6 */ "", 24329 /* EFP_RAM_CONTROL_7 */ "", 24330 /* EFP_RAM_CONTROL_1_64 */ "EFP_RAM_CONTROL_1", 24331 /* EFP_RAM_CONTROL_1_64_PIPE0 */ "EFP_RAM_CONTROL_1_PIPE0", 24332 /* EFP_RAM_CONTROL_1_64_PIPE1 */ "EFP_RAM_CONTROL_1_PIPE1", 24333 /* EFP_RAM_CONTROL_1_64_PIPE2 */ "EFP_RAM_CONTROL_1_PIPE2", 24334 /* EFP_RAM_CONTROL_1_64_PIPE3 */ "EFP_RAM_CONTROL_1_PIPE3", 24335 /* EFP_RAM_CONTROL_1_64_PIPE4 */ "EFP_RAM_CONTROL_1_PIPE4", 24336 /* EFP_RAM_CONTROL_1_64_PIPE5 */ "EFP_RAM_CONTROL_1_PIPE5", 24337 /* EFP_RAM_CONTROL_1_64_PIPE6 */ "EFP_RAM_CONTROL_1_PIPE6", 24338 /* EFP_RAM_CONTROL_1_64_PIPE7 */ "EFP_RAM_CONTROL_1_PIPE7", 24339 /* EFP_RAM_CONTROL_1_PIPE0 */ "", 24340 /* EFP_RAM_CONTROL_1_PIPE1 */ "", 24341 /* EFP_RAM_CONTROL_2_64 */ "EFP_RAM_CONTROL_2", 24342 /* EFP_RAM_CONTROL_2_64_PIPE0 */ "EFP_RAM_CONTROL_2_PIPE0", 24343 /* EFP_RAM_CONTROL_2_64_PIPE1 */ "EFP_RAM_CONTROL_2_PIPE1", 24344 /* EFP_RAM_CONTROL_2_64_PIPE2 */ "EFP_RAM_CONTROL_2_PIPE2", 24345 /* EFP_RAM_CONTROL_2_64_PIPE3 */ "EFP_RAM_CONTROL_2_PIPE3", 24346 /* EFP_RAM_CONTROL_2_64_PIPE4 */ "EFP_RAM_CONTROL_2_PIPE4", 24347 /* EFP_RAM_CONTROL_2_64_PIPE5 */ "EFP_RAM_CONTROL_2_PIPE5", 24348 /* EFP_RAM_CONTROL_2_64_PIPE6 */ "EFP_RAM_CONTROL_2_PIPE6", 24349 /* EFP_RAM_CONTROL_2_64_PIPE7 */ "EFP_RAM_CONTROL_2_PIPE7", 24350 /* EFP_RAM_CONTROL_2_PIPE0 */ "", 24351 /* EFP_RAM_CONTROL_2_PIPE1 */ "", 24352 /* EFP_RAM_CONTROL_3_PIPE0 */ "", 24353 /* EFP_RAM_CONTROL_3_PIPE1 */ "", 24354 /* EFP_RAM_CONTROL_3_PIPE2 */ "", 24355 /* EFP_RAM_CONTROL_3_PIPE3 */ "", 24356 /* EFP_RAM_CONTROL_3_PIPE4 */ "", 24357 /* EFP_RAM_CONTROL_3_PIPE5 */ "", 24358 /* EFP_RAM_CONTROL_3_PIPE6 */ "", 24359 /* EFP_RAM_CONTROL_3_PIPE7 */ "", 24360 /* EFP_RAM_CONTROL_4_PIPE0 */ "", 24361 /* EFP_RAM_CONTROL_4_PIPE1 */ "", 24362 /* EFP_RAM_CONTROL_4_PIPE2 */ "", 24363 /* EFP_RAM_CONTROL_4_PIPE3 */ "", 24364 /* EFP_RAM_CONTROL_4_PIPE4 */ "", 24365 /* EFP_RAM_CONTROL_4_PIPE5 */ "", 24366 /* EFP_RAM_CONTROL_4_PIPE6 */ "", 24367 /* EFP_RAM_CONTROL_4_PIPE7 */ "", 24368 /* EFP_RAM_CONTROL_5_PIPE0 */ "", 24369 /* EFP_RAM_CONTROL_5_PIPE1 */ "", 24370 /* EFP_RAM_CONTROL_5_PIPE2 */ "", 24371 /* EFP_RAM_CONTROL_5_PIPE3 */ "", 24372 /* EFP_RAM_CONTROL_5_PIPE4 */ "", 24373 /* EFP_RAM_CONTROL_5_PIPE5 */ "", 24374 /* EFP_RAM_CONTROL_5_PIPE6 */ "", 24375 /* EFP_RAM_CONTROL_5_PIPE7 */ "", 24376 /* EFP_RAM_CONTROL_PIPE0 */ "", 24377 /* EFP_RAM_CONTROL_PIPE1 */ "", 24378 /* EFP_RAM_CONTROL_PIPE2 */ "", 24379 /* EFP_RAM_CONTROL_PIPE3 */ "", 24380 /* EFP_RAM_CONTROL_PIPE4 */ "", 24381 /* EFP_RAM_CONTROL_PIPE5 */ "", 24382 /* EFP_RAM_CONTROL_PIPE6 */ "", 24383 /* EFP_RAM_CONTROL_PIPE7 */ "", 24384 /* EFP_SLICE0_RAM_CONTROL */ "", 24385 /* EFP_SLICE1_RAM_CONTROL */ "", 24386 /* EFP_SLICE2_RAM_CONTROL */ "", 24387 /* EFP_SLICE3_RAM_CONTROL */ "", 24388 /* EFP_SLICE_0_CAM_BIST_CONFIG_64 */ "", 24389 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE0 */ "", 24390 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE1 */ "", 24391 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE2 */ "", 24392 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE3 */ "", 24393 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE4 */ "", 24394 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE5 */ "", 24395 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE6 */ "", 24396 /* EFP_SLICE_0_CAM_BIST_CONFIG_64_PIPE7 */ "", 24397 /* EFP_SLICE_0_CAM_BIST_STATUS */ "", 24398 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE0 */ "", 24399 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE1 */ "", 24400 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE2 */ "", 24401 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE3 */ "", 24402 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE4 */ "", 24403 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE5 */ "", 24404 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE6 */ "", 24405 /* EFP_SLICE_0_CAM_BIST_STATUS_PIPE7 */ "", 24406 /* EFP_SLICE_1_CAM_BIST_CONFIG_64 */ "", 24407 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE0 */ "", 24408 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE1 */ "", 24409 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE2 */ "", 24410 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE3 */ "", 24411 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE4 */ "", 24412 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE5 */ "", 24413 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE6 */ "", 24414 /* EFP_SLICE_1_CAM_BIST_CONFIG_64_PIPE7 */ "", 24415 /* EFP_SLICE_1_CAM_BIST_STATUS */ "", 24416 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE0 */ "", 24417 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE1 */ "", 24418 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE2 */ "", 24419 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE3 */ "", 24420 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE4 */ "", 24421 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE5 */ "", 24422 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE6 */ "", 24423 /* EFP_SLICE_1_CAM_BIST_STATUS_PIPE7 */ "", 24424 /* EFP_SLICE_2_CAM_BIST_CONFIG_64 */ "", 24425 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE0 */ "", 24426 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE1 */ "", 24427 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE2 */ "", 24428 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE3 */ "", 24429 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE4 */ "", 24430 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE5 */ "", 24431 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE6 */ "", 24432 /* EFP_SLICE_2_CAM_BIST_CONFIG_64_PIPE7 */ "", 24433 /* EFP_SLICE_2_CAM_BIST_STATUS */ "", 24434 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE0 */ "", 24435 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE1 */ "", 24436 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE2 */ "", 24437 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE3 */ "", 24438 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE4 */ "", 24439 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE5 */ "", 24440 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE6 */ "", 24441 /* EFP_SLICE_2_CAM_BIST_STATUS_PIPE7 */ "", 24442 /* EFP_SLICE_3_CAM_BIST_CONFIG_64 */ "", 24443 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE0 */ "", 24444 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE1 */ "", 24445 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE2 */ "", 24446 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE3 */ "", 24447 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE4 */ "", 24448 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE5 */ "", 24449 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE6 */ "", 24450 /* EFP_SLICE_3_CAM_BIST_CONFIG_64_PIPE7 */ "", 24451 /* EFP_SLICE_3_CAM_BIST_STATUS */ "", 24452 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE0 */ "", 24453 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE1 */ "", 24454 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE2 */ "", 24455 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE3 */ "", 24456 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE4 */ "", 24457 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE5 */ "", 24458 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE6 */ "", 24459 /* EFP_SLICE_3_CAM_BIST_STATUS_PIPE7 */ "", 24460 /* EFP_SLICE_CONTROL */ "", 24461 /* EFP_SLICE_CONTROL_PIPE0 */ "", 24462 /* EFP_SLICE_CONTROL_PIPE1 */ "", 24463 /* EFP_SLICE_CONTROL_PIPE2 */ "", 24464 /* EFP_SLICE_CONTROL_PIPE3 */ "", 24465 /* EFP_SLICE_CONTROL_PIPE4 */ "", 24466 /* EFP_SLICE_CONTROL_PIPE5 */ "", 24467 /* EFP_SLICE_CONTROL_PIPE6 */ "", 24468 /* EFP_SLICE_CONTROL_PIPE7 */ "", 24469 /* EFP_SLICE_MAP */ "", 24470 /* EFP_SLICE_MAP_PIPE0 */ "", 24471 /* EFP_SLICE_MAP_PIPE1 */ "", 24472 /* EFP_SLICE_MAP_PIPE2 */ "", 24473 /* EFP_SLICE_MAP_PIPE3 */ "", 24474 /* EFP_SLICE_MAP_PIPE4 */ "", 24475 /* EFP_SLICE_MAP_PIPE5 */ "", 24476 /* EFP_SLICE_MAP_PIPE6 */ "", 24477 /* EFP_SLICE_MAP_PIPE7 */ "", 24478 /* EFP_TCAM_BLKSEL */ "", 24479 /* EFP_TCAM_CONTROL */ "", 24480 /* EFP_TSN_CONTROL */ "", 24481 /* EGQ_ACCEPTABLE_FRAME_TYPE_TABLE */ "", 24482 /* EGQ_ACTION_PROFILE_1 */ "", 24483 /* EGQ_ACTION_PROFILE_2 */ "", 24484 /* EGQ_ACTION_PROFILE_3 */ "", 24485 /* EGQ_ACTION_PROFILE_4 */ "", 24486 /* EGQ_ACTION_PROFILE_5 */ "", 24487 /* EGQ_ALMOST_EMPTY_THRESHOLD_VALUE */ "", 24488 /* EGQ_AUXILIARY_DATA_TABLE */ "", 24489 /* EGQ_BOUNCE_BACK */ "", 24490 /* EGQ_CELL_DECODER_DEBUG_COUNTERS */ "", 24491 /* EGQ_CFC_FLOW_CONTROL */ "", 24492 /* EGQ_CFG_ADDITIONAL_TPID_VALUES */ "", 24493 /* EGQ_CFG_ALWAYS_CHECK_IPVX_COMPATIBLE_MC */ "", 24494 /* EGQ_CFG_BUG_FIX_CHICKEN_BITS_REG_1 */ "", 24495 /* EGQ_CFG_BUG_FIX_CHICKEN_BITS_REG_2 */ "", 24496 /* EGQ_CFG_ERPP_SER_TRAP */ "", 24497 /* EGQ_CFG_FWD_CODE_BUG_FIX_DISABLED */ "", 24498 /* EGQ_CFG_ING_MC_FIX */ "", 24499 /* EGQ_CFG_PETRAB_OUT_LIF_SRC */ "", 24500 /* EGQ_CFG_RIF_IN_STACK */ "", 24501 /* EGQ_CFG_SCHEDULER_PKT_SZ_COMP_ENABLE */ "", 24502 /* EGQ_CHANNELIZED_INTERFACE_MAX_BURST */ "", 24503 /* EGQ_CHANNELIZED_INTERFACE_RATE */ "", 24504 /* EGQ_CHECK_BW_TO_IFC */ "", 24505 /* EGQ_CHECK_BW_TO_OFP */ "", 24506 /* EGQ_CNM_COUNTER_CFG */ "", 24507 /* EGQ_CNM_CPID_TO_FC_TYPE_0 */ "", 24508 /* EGQ_CNM_CPID_TO_FC_TYPE_1 */ "", 24509 /* EGQ_CNM_CPID_TO_FC_TYPE_2 */ "", 24510 /* EGQ_CNM_GENERAL_CONFIG */ "", 24511 /* EGQ_CNM_PACKETS_CNT */ "", 24512 /* EGQ_CNM_TIMER_GRANULARITY_REG */ "", 24513 /* EGQ_CONTEXT_FIFO_THRESHOLD_VALUES */ "", 24514 /* EGQ_COPY_LAST_FSR_VSC_128_HDR */ "", 24515 /* EGQ_COPY_LAST_LSR_SOP_HEADER */ "", 24516 /* EGQ_COPY_LAST_PRP_SOP_HEADER */ "", 24517 /* EGQ_COPY_LAST_PRP_SOP_HEADER_ADD_INFORMATION */ "", 24518 /* EGQ_COUNTER_PROCESSOR_POINTER_MASKING */ "", 24519 /* EGQ_COUNTER_PROFILE_OFFSET */ "", 24520 /* EGQ_CPU_LAST_HEADER */ "", 24521 /* EGQ_CPU_PACKET_CONTROL */ "", 24522 /* EGQ_CPU_PACKET_COUNTER */ "", 24523 /* EGQ_CPU_PACKET_WORDS */ "", 24524 /* EGQ_CRC_DEBUG_COUNTERS */ "", 24525 /* EGQ_CSR_INTERFACE_SOP_COUNTER */ "", 24526 /* EGQ_CUP_DEBUG_COUNTERS */ "", 24527 /* EGQ_DBF_ECC_1B_ERR_ADDR */ "", 24528 /* EGQ_DBF_ECC_1B_ERR_CNT */ "", 24529 /* EGQ_DBF_ECC_2B_ERR_ADDR */ "", 24530 /* EGQ_DBF_ECC_2B_ERR_CNT */ "", 24531 /* EGQ_DBG_CDC_ERR_MASK_DIS_CNT */ "", 24532 /* EGQ_DBG_COMMAND */ "", 24533 /* EGQ_DBG_CUP_ERR_MASK_DIS_CNT */ "", 24534 /* EGQ_DBG_DATA */ "", 24535 /* EGQ_DBG_PRP_SOP_DISCARD_MASK_DIS_CNT */ "", 24536 /* EGQ_DBG_RQP_TXQ_COUNTERS_ENABLE */ "", 24537 /* EGQ_DBG_SOURCE_MASK_DIS_CNT */ "", 24538 /* EGQ_DELETE_FIFO_CONFIGURATION */ "", 24539 /* EGQ_DELETE_FIFO_STATUS */ "", 24540 /* EGQ_DISABLE_EGRESS_OFP */ "", 24541 /* EGQ_DISCARDED_SOP_COUNTER_SEL */ "", 24542 /* EGQ_ECC_1B_ERR_CNT */ "", 24543 /* EGQ_ECC_2B_ERR_CNT */ "", 24544 /* EGQ_ECC_ERR_1B_INITIATE */ "", 24545 /* EGQ_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 24546 /* EGQ_ECC_ERR_2B_INITIATE */ "", 24547 /* EGQ_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 24548 /* EGQ_ECC_INTERRUPT_REGISTER */ "", 24549 /* EGQ_ECC_INTERRUPT_REGISTER_MASK */ "", 24550 /* EGQ_ECC_INTERRUPT_REGISTER_TEST */ "", 24551 /* EGQ_EGQ_BLOCK_INIT_STATUS */ "", 24552 /* EGQ_EGRESS_INTERFACE_FAST_PORT_CONFIGURATION */ "", 24553 /* EGQ_EGRESS_PORT_PRIORITY_CONFIGURATION */ "", 24554 /* EGQ_EGRESS_QUEUES_EMPTY */ "", 24555 /* EGQ_EGRESS_REPLICATION_GENERAL_CONFIG */ "", 24556 /* EGQ_EGRESS_REPLICATION_MCID_MASK */ "", 24557 /* EGQ_EGRESS_SHAPERS_CREDIT_MEMORY_INIT_STATUS */ "", 24558 /* EGQ_EGRESS_SHAPER_CALENDARS_ARBITRATION_CYCLE_LENGTH */ "", 24559 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_0 */ "", 24560 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_1 */ "", 24561 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_2 */ "", 24562 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_3 */ "", 24563 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_4 */ "", 24564 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_5 */ "", 24565 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_6 */ "", 24566 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_7 */ "", 24567 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_8 */ "", 24568 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_CHAN_INTERFACE_9 */ "", 24569 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_NON_CHAN_INTERFACES */ "", 24570 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_QPAIR */ "", 24571 /* EGQ_EGRESS_SHAPER_CONFIGURATION_A_FOR_TCG */ "", 24572 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_0 */ "", 24573 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_1 */ "", 24574 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_2 */ "", 24575 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_3 */ "", 24576 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_4 */ "", 24577 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_5 */ "", 24578 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_6 */ "", 24579 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_7 */ "", 24580 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_8 */ "", 24581 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_CHAN_INTERFACE_9 */ "", 24582 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_NON_CHAN_INTERFACES */ "", 24583 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_QPAIR */ "", 24584 /* EGQ_EGRESS_SHAPER_CONFIGURATION_B_FOR_TCG */ "", 24585 /* EGQ_EGRESS_SHAPER_ENABLE_SETTINGS */ "", 24586 /* EGQ_EHP_BUBBLE_CONFIGURATION */ "", 24587 /* EGQ_EHP_BUBBLE_TRIGGER */ "", 24588 /* EGQ_EHP_DISCARD_PACKET_COUNTER */ "", 24589 /* EGQ_EHP_MULTICAST_HIGH_DISCARDS_COUNTER */ "", 24590 /* EGQ_EHP_MULTICAST_HIGH_PACKET_COUNTER */ "", 24591 /* EGQ_EHP_MULTICAST_LOW_DISCARDS_COUNTER */ "", 24592 /* EGQ_EHP_MULTICAST_LOW_PACKET_COUNTER */ "", 24593 /* EGQ_EHP_UNICAST_PACKET_COUNTER */ "", 24594 /* EGQ_EMPTY_MCID_COUNTER */ "", 24595 /* EGQ_EMPTY_PORT_MAX_CREDIT_VALUE */ "", 24596 /* EGQ_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 24597 /* EGQ_ENABLE_IP_ACL_ON_BRIDGE */ "", 24598 /* EGQ_ENABLE_MPLS_SAME_INTERFACE_FILTER */ "", 24599 /* EGQ_ERPP_DISCARDS_INTERRUPT_REGISTER_MASK */ "", 24600 /* EGQ_ERPP_DISCARDS_INTERRUPT_REGISTER_MASK_2 */ "", 24601 /* EGQ_ERPP_DISCARD_INTERRUPT_REGISTER */ "", 24602 /* EGQ_ERPP_DISCARD_INTERRUPT_REGISTER_2 */ "", 24603 /* EGQ_ERPP_DISCARD_INT_REG */ "", 24604 /* EGQ_ERPP_DISCARD_INT_REG_2 */ "", 24605 /* EGQ_ERPP_DISCARD_INT_REG_2_TEST */ "", 24606 /* EGQ_ERPP_DISCARD_INT_REG_MASK */ "", 24607 /* EGQ_ERPP_DISCARD_INT_REG_MASK_2 */ "", 24608 /* EGQ_ERPP_DISCARD_INT_REG_TEST */ "", 24609 /* EGQ_ERPP_LAG_PRUNING_DISCARDS_COUNTER */ "", 24610 /* EGQ_ERPP_PMF_DISCARDS_COUNTER */ "", 24611 /* EGQ_ERPP_VLAN_MEMBERSHIP_DISCARDS_COUNTER */ "", 24612 /* EGQ_ERROR_INITIATION_DATA */ "", 24613 /* EGQ_ETHERNET_TYPES */ "", 24614 /* EGQ_FABRIC_MULTICAST_ROUTE_INTERFACE_SOP_COUNTER */ "", 24615 /* EGQ_FABRIC_UNICAST_ROUTE_INTERFACE_SOP_COUNTER */ "", 24616 /* EGQ_FABRIC_VSC_128_SOP_COUNTER */ "", 24617 /* EGQ_FALL_BACK_TO_BRIDGE_VLAN_COMMANDS */ "", 24618 /* EGQ_FDR_PRIMARY_LAST_HEADER */ "", 24619 /* EGQ_FDR_PRIMARY_PACKET_COUNTER */ "", 24620 /* EGQ_FDR_SECONDARY_LAST_HEADER */ "", 24621 /* EGQ_FDR_SECONDARY_PACKET_COUNTER */ "", 24622 /* EGQ_FILETER_DEBUG_COUNTERS */ "", 24623 /* EGQ_FORCE_OR_IGNORE_FC */ "", 24624 /* EGQ_FQP_2_PQP_RDY */ "", 24625 /* EGQ_FQP_BUBBLE_CONFIGURATION */ "", 24626 /* EGQ_FQP_BUBBLE_TRIGGER */ "", 24627 /* EGQ_FQP_CELL_COUNTER */ "", 24628 /* EGQ_FQP_CONFIGURATION */ "", 24629 /* EGQ_FQP_DEBUG_HALT_CONFIGURATION */ "", 24630 /* EGQ_FQP_PACKET_COUNTER */ "", 24631 /* EGQ_FQP_SCHEDULER_CONFIGURATION */ "", 24632 /* EGQ_FQP_SCHEDULER_FIX_DIS */ "", 24633 /* EGQ_FRAGMENTATION_QUEUES_EMPTY_INDICATION */ "", 24634 /* EGQ_FRAGMENTATION_QUEUES_READY_WORDS_THRESHOLD */ "", 24635 /* EGQ_GENERAL_RQP_CONFIG */ "", 24636 /* EGQ_GENERAL_RQP_DEBUG_CONFIG */ "", 24637 /* EGQ_GLOBAL_CONFIG */ "", 24638 /* EGQ_GLOBAL_GENERAL_CFG_1 */ "", 24639 /* EGQ_GLOBAL_GENERAL_CFG_2 */ "", 24640 /* EGQ_GLOBAL_GENERAL_CFG_3 */ "", 24641 /* EGQ_GLOBAL_MEM_OPTIONS */ "", 24642 /* EGQ_GLOBAL_ONE_PLUS_ONE_PORT_PROTECTION */ "", 24643 /* EGQ_GLOBAL_PP_2 */ "", 24644 /* EGQ_GLOBAL_PP_3 */ "", 24645 /* EGQ_GLOBAL_PP_4 */ "", 24646 /* EGQ_GLOBAL_PP_5 */ "", 24647 /* EGQ_GLOBAL_PP_7 */ "", 24648 /* EGQ_GLOBAL_PP_8 */ "", 24649 /* EGQ_GLOBAL_SYS_HEADER_CFG */ "", 24650 /* EGQ_GTIMER_CONFIG */ "", 24651 /* EGQ_GTIMER_CONFIGURATION */ "", 24652 /* EGQ_GTIMER_CONFIG_CONT */ "", 24653 /* EGQ_GTIMER_TRIGGER */ "", 24654 /* EGQ_HIGHER_REQ_EN_PER_MAL */ "", 24655 /* EGQ_IFC_CANCEL_EN */ "", 24656 /* EGQ_IFC_DELAY_CONFIGURATION */ "", 24657 /* EGQ_IFC_IS_CHANNELIZED */ "", 24658 /* EGQ_IFC_IS_LBG */ "", 24659 /* EGQ_IFC_IS_WORK_CONSERVING */ "", 24660 /* EGQ_IFC_OK_DEQ */ "", 24661 /* EGQ_INDIRECT_COMMAND */ "", 24662 /* EGQ_INDIRECT_COMMAND_ADDRESS */ "", 24663 /* EGQ_INDIRECT_COMMAND_DATA_INCREMENT */ "", 24664 /* EGQ_INDIRECT_COMMAND_RD_DATA */ "", 24665 /* EGQ_INDIRECT_COMMAND_WIDE_MEM */ "", 24666 /* EGQ_INDIRECT_COMMAND_WR_DATA */ "", 24667 /* EGQ_INDIRECT_FORCE_BUBBLE */ "", 24668 /* EGQ_INDIRECT_WR_MASK */ "", 24669 /* EGQ_INIT_FQP_TXI_CMICM */ "", 24670 /* EGQ_INIT_FQP_TXI_IPSEC */ "", 24671 /* EGQ_INIT_FQP_TXI_NIF */ "", 24672 /* EGQ_INIT_FQP_TXI_OAM */ "", 24673 /* EGQ_INIT_FQP_TXI_OLP */ "", 24674 /* EGQ_INIT_FQP_TXI_RCY */ "", 24675 /* EGQ_INIT_FQP_TXI_SAT */ "", 24676 /* EGQ_INTERRUPT_MASK_REGISTER */ "", 24677 /* EGQ_INTERRUPT_REGISTER */ "", 24678 /* EGQ_INTERRUPT_REGISTER_TEST */ "", 24679 /* EGQ_INVALID_OTM */ "", 24680 /* EGQ_INVALID_OUTLIF */ "", 24681 /* EGQ_IN_LIF_DP_PROFILE_MAP */ "", 24682 /* EGQ_IPT_LAST_HEADER */ "", 24683 /* EGQ_IPT_PACKET_COUNTER */ "", 24684 /* EGQ_KEYA_DATA_BASE_PROFILE */ "", 24685 /* EGQ_KEYB_DATA_BASE_PROFILE */ "", 24686 /* EGQ_LAG_FILTER_ENABLE */ "", 24687 /* EGQ_LAST_CDC_HEADER */ "", 24688 /* EGQ_LAST_FSR_MC_VSC_256_HDR */ "", 24689 /* EGQ_LAST_FSR_UC_VSC_256_HDR */ "", 24690 /* EGQ_LAST_PRP_SOP_HEADER */ "", 24691 /* EGQ_LAST_PRP_TDM_HEADER */ "", 24692 /* EGQ_LAST_REASSEMBLY_ERROR_MCID */ "", 24693 /* EGQ_LBG_CONFIG */ "", 24694 /* EGQ_LBG_CREDIT_INIT */ "", 24695 /* EGQ_LBG_CREDIT_SIZE */ "", 24696 /* EGQ_LOCAL_ROUTE_INTERFACE_SOP_COUNTER */ "", 24697 /* EGQ_MAPPING_INTERFACES_TO_CHAN_ARBITER */ "", 24698 /* EGQ_MAP_FLEXIBLE_UDH_TYPE_TO_SIZE */ "", 24699 /* EGQ_MAXIMUM_AND_MINIMUM_PACKET_SIZE */ "", 24700 /* EGQ_MC_CONTEXT_FIFO_STATUS */ "", 24701 /* EGQ_MC_PRIORITY_LOOKUP_TABLE */ "", 24702 /* EGQ_MTU */ "", 24703 /* EGQ_MTU_CHECK_ENABLE */ "", 24704 /* EGQ_MULTICAST_EGRESS_PACKET_HEADER_COMPENSATION_FOR_TYPE_A */ "", 24705 /* EGQ_MULTICAST_EGRESS_PACKET_HEADER_COMPENSATION_FOR_TYPE_B */ "", 24706 /* EGQ_MULTICAST_FIFOS_CONFIGURATION */ "", 24707 /* EGQ_MULTICAST_OFFSET_ADDRESS */ "", 24708 /* EGQ_NETWORK_HEADERS_VALUE_1_OFFSET */ "", 24709 /* EGQ_NETWORK_HEADERS_VALUE_2_OFFSET */ "", 24710 /* EGQ_NIF_CANCEL_EN_REGISTER_1 */ "", 24711 /* EGQ_NIF_CANCEL_EN_REGISTER_2 */ "", 24712 /* EGQ_NIF_CANCEL_EN_REGISTER_3 */ "", 24713 /* EGQ_NIF_CANCEL_EN_REGISTER_4 */ "", 24714 /* EGQ_NIF_FLOW_CONTROL */ "", 24715 /* EGQ_NRDY_TH_0_2 */ "", 24716 /* EGQ_NRDY_TH_3_5 */ "", 24717 /* EGQ_NRDY_TH_6_7 */ "", 24718 /* EGQ_NRDY_TH_6_8 */ "", 24719 /* EGQ_NRDY_TH_9_11 */ "", 24720 /* EGQ_NRDY_TH_SEL */ "", 24721 /* EGQ_ONE_PLUS_ONE_PROTECT_EN */ "", 24722 /* EGQ_OPP_LEARNING_DISABLE */ "", 24723 /* EGQ_OTM_LEARNING_DISABLE */ "", 24724 /* EGQ_OTM_PORT_SPR_DIS */ "", 24725 /* EGQ_OUTLIF_MSB_MAPPED */ "", 24726 /* EGQ_OUTLIF_MSB_MAPPED_SHIFT */ "", 24727 /* EGQ_OUTRIF_MAX_VALUE */ "", 24728 /* EGQ_PACKET_RATE_SHAPER_EN */ "", 24729 /* EGQ_PACKET_REASSEMBLY_INTERRUPT_REGISTER */ "", 24730 /* EGQ_PACKET_REASSEMBLY_INTERRUPT_REGISTER_MASK */ "", 24731 /* EGQ_PARITY_ERR_CNT */ "", 24732 /* EGQ_PARSER_LAST_NWK_RECORD */ "", 24733 /* EGQ_PARSER_LAST_SYS_RECORD */ "", 24734 /* EGQ_PAR_ERR_INITIATE */ "", 24735 /* EGQ_PAR_ERR_MEM_MASK */ "", 24736 /* EGQ_PCMI_0 */ "", 24737 /* EGQ_PCMI_1 */ "", 24738 /* EGQ_PCMI_2 */ "", 24739 /* EGQ_PCMI_3 */ "", 24740 /* EGQ_PCMI_4 */ "", 24741 /* EGQ_PCMI_0_S */ "", 24742 /* EGQ_PCMI_0_T */ "", 24743 /* EGQ_PCMI_1_S */ "", 24744 /* EGQ_PCMI_1_T */ "", 24745 /* EGQ_PCMI_2_S */ "", 24746 /* EGQ_PCMI_2_T */ "", 24747 /* EGQ_PCMI_3_S */ "", 24748 /* EGQ_PCMI_3_T */ "", 24749 /* EGQ_PCMI_4_S */ "", 24750 /* EGQ_PCMI_4_T */ "", 24751 /* EGQ_PER_PACKET_HDR_COMP */ "", 24752 /* EGQ_PER_QUEUE_HEADER_COMPENSATION */ "", 24753 /* EGQ_PETRAB_EEI_CFG */ "", 24754 /* EGQ_PETRAB_EEI_MPLS_MAP */ "", 24755 /* EGQ_PETRAB_FHEI_SIZE_MAP */ "", 24756 /* EGQ_PETRAB_LEARN_ASD_TYPE_MAP */ "", 24757 /* EGQ_PKT_REAS_INT_REG */ "", 24758 /* EGQ_PKT_REAS_INT_REG_MASK */ "", 24759 /* EGQ_PKT_REAS_INT_REG_TEST */ "", 24760 /* EGQ_PORT_ALMOST_EMPTY_FORCE */ "", 24761 /* EGQ_PORT_ALMOST_EMPTY_SCHEDULER_DELAY */ "", 24762 /* EGQ_PP_CONFIG */ "", 24763 /* EGQ_PQP_2_FQP_OFP_STOP */ "", 24764 /* EGQ_PQP_AND_FQP_CALENDER_SETTING */ "", 24765 /* EGQ_PQP_CRPS_CONF */ "", 24766 /* EGQ_PQP_DISCARD_MULTICAST_PACKET_COUNTER */ "", 24767 /* EGQ_PQP_DISCARD_UNICAST_PACKET_COUNTER */ "", 24768 /* EGQ_PQP_MULTICAST_BYTES_COUNTER */ "", 24769 /* EGQ_PQP_MULTICAST_PACKET_COUNTER */ "", 24770 /* EGQ_PQP_SPECIAL_FLOW_CONTROL */ "", 24771 /* EGQ_PQP_UNICAST_BYTES_COUNTER */ "", 24772 /* EGQ_PQP_UNICAST_PACKET_COUNTER */ "", 24773 /* EGQ_PRIVATE_VLAN_FILTER */ "", 24774 /* EGQ_PRP_DEBUG_COUNTERS */ "", 24775 /* EGQ_PRP_SOP_CNT */ "", 24776 /* EGQ_PS_MODE */ "", 24777 /* EGQ_QPAIR_SPR_DIS */ "", 24778 /* EGQ_QP_MAX_CREDIT_VALUE */ "", 24779 /* EGQ_RCM_DEBUG */ "", 24780 /* EGQ_RCM_STATIC_CONFIG */ "", 24781 /* EGQ_REASSEMBLY_SCHEDULER_CONFIGURATION */ "", 24782 /* EGQ_REG_0085 */ "", 24783 /* EGQ_REG_0090 */ "", 24784 /* EGQ_REG_0091 */ "", 24785 /* EGQ_REG_0092 */ "", 24786 /* EGQ_REG_0093 */ "", 24787 /* EGQ_REG_0100 */ "", 24788 /* EGQ_REG_0101 */ "", 24789 /* EGQ_REG_0102 */ "", 24790 /* EGQ_REG_0103 */ "", 24791 /* EGQ_REG_0104 */ "", 24792 /* EGQ_REG_0105 */ "", 24793 /* EGQ_REG_0106 */ "", 24794 /* EGQ_REG_0107 */ "", 24795 /* EGQ_REG_0108 */ "", 24796 /* EGQ_REG_0128 */ "", 24797 /* EGQ_REG_0176 */ "", 24798 /* EGQ_REG_0177 */ "", 24799 /* EGQ_REG_0178 */ "", 24800 /* EGQ_REG_0179 */ "", 24801 /* EGQ_REG_0180 */ "", 24802 /* EGQ_REG_0182 */ "", 24803 /* EGQ_REG_0188 */ "", 24804 /* EGQ_REG_0194 */ "", 24805 /* EGQ_REG_0195 */ "", 24806 /* EGQ_REG_0196 */ "", 24807 /* EGQ_REG_0197 */ "", 24808 /* EGQ_REG_0198 */ "", 24809 /* EGQ_REG_0203 */ "", 24810 /* EGQ_REG_0231 */ "", 24811 /* EGQ_REG_0254 */ "", 24812 /* EGQ_REG_0291 */ "", 24813 /* EGQ_REG_0293 */ "", 24814 /* EGQ_REG_0296 */ "", 24815 /* EGQ_REG_0298 */ "", 24816 /* EGQ_REG_0386 */ "", 24817 /* EGQ_REG_0387 */ "", 24818 /* EGQ_REG_001C */ "", 24819 /* EGQ_REG_00AE */ "", 24820 /* EGQ_REG_00AF */ "", 24821 /* EGQ_REG_00B0 */ "", 24822 /* EGQ_REG_00B1 */ "", 24823 /* EGQ_REG_00B2 */ "", 24824 /* EGQ_REG_00B3 */ "", 24825 /* EGQ_REG_00BC */ "", 24826 /* EGQ_REG_00BD */ "", 24827 /* EGQ_REG_00BE */ "", 24828 /* EGQ_REG_00BF */ "", 24829 /* EGQ_REG_00C1 */ "", 24830 /* EGQ_REG_00CF */ "", 24831 /* EGQ_REG_00D0 */ "", 24832 /* EGQ_REG_00D2 */ "", 24833 /* EGQ_REG_00D3 */ "", 24834 /* EGQ_REG_00D4 */ "", 24835 /* EGQ_REG_00D5 */ "", 24836 /* EGQ_REG_00DA */ "", 24837 /* EGQ_REG_00DF */ "", 24838 /* EGQ_REG_00F6 */ "", 24839 /* EGQ_REG_00F7 */ "", 24840 /* EGQ_REG_00F8 */ "", 24841 /* EGQ_REG_00F9 */ "", 24842 /* EGQ_REG_00FA */ "", 24843 /* EGQ_REG_00FB */ "", 24844 /* EGQ_REG_00FC */ "", 24845 /* EGQ_REG_00FD */ "", 24846 /* EGQ_REG_00FE */ "", 24847 /* EGQ_REG_00FF */ "", 24848 /* EGQ_REG_010A */ "", 24849 /* EGQ_REG_010C */ "", 24850 /* EGQ_REG_010E */ "", 24851 /* EGQ_REG_015B */ "", 24852 /* EGQ_REG_017A */ "", 24853 /* EGQ_REG_01A3 */ "", 24854 /* EGQ_REG_01A9 */ "", 24855 /* EGQ_REG_01B4 */ "", 24856 /* EGQ_REG_01B6 */ "", 24857 /* EGQ_REG_01B7 */ "", 24858 /* EGQ_REG_01B9 */ "", 24859 /* EGQ_REG_01BB */ "", 24860 /* EGQ_REG_01C3 */ "", 24861 /* EGQ_REG_01C4 */ "", 24862 /* EGQ_REG_01C6 */ "", 24863 /* EGQ_REG_01CC */ "", 24864 /* EGQ_REG_01D2 */ "", 24865 /* EGQ_REG_01D4 */ "", 24866 /* EGQ_REG_01DF */ "", 24867 /* EGQ_REG_01E0 */ "", 24868 /* EGQ_REG_01E1 */ "", 24869 /* EGQ_REG_01E6 */ "", 24870 /* EGQ_REG_01E7 */ "", 24871 /* EGQ_REG_01EF */ "", 24872 /* EGQ_REG_023F */ "", 24873 /* EGQ_REG_037D */ "", 24874 /* EGQ_REG_037E */ "", 24875 /* EGQ_REG_037F */ "", 24876 /* EGQ_RESERVED_MIRROR_ADDR */ "", 24877 /* EGQ_RESERVED_MTCD */ "", 24878 /* EGQ_RESERVED_MTCP */ "", 24879 /* EGQ_RESERVED_PCMI_0 */ "", 24880 /* EGQ_RESERVED_PCMI_1 */ "", 24881 /* EGQ_RESERVED_PCMI_2 */ "", 24882 /* EGQ_RESERVED_PCMI_3 */ "", 24883 /* EGQ_RESERVED_PCMI_4 */ "", 24884 /* EGQ_RESERVED_PCMI_0_S */ "", 24885 /* EGQ_RESERVED_PCMI_0_T */ "", 24886 /* EGQ_RESERVED_PCMI_1_S */ "", 24887 /* EGQ_RESERVED_PCMI_1_T */ "", 24888 /* EGQ_RESERVED_PCMI_2_S */ "", 24889 /* EGQ_RESERVED_PCMI_2_T */ "", 24890 /* EGQ_RESERVED_PCMI_3_S */ "", 24891 /* EGQ_RESERVED_PCMI_3_T */ "", 24892 /* EGQ_RESERVED_PCMI_4_S */ "", 24893 /* EGQ_RESERVED_PCMI_4_T */ "", 24894 /* EGQ_RESERVED_SPARE_0 */ "", 24895 /* EGQ_RESERVED_SPARE_1 */ "", 24896 /* EGQ_RESERVED_SPARE_2 */ "", 24897 /* EGQ_RESERVED_SPARE_3 */ "", 24898 /* EGQ_RQP_DEBUG_COUNTERS */ "", 24899 /* EGQ_RQP_DISCARD_MULTICAST_PACKET_COUNTER */ "", 24900 /* EGQ_RQP_DISCARD_PACKET_COUNTER */ "", 24901 /* EGQ_RQP_DISCARD_SOP_COUNTER */ "", 24902 /* EGQ_RQP_PACKET_COUNTER */ "", 24903 /* EGQ_SAME_INTERFACE_FILTER */ "", 24904 /* EGQ_SBUS_BROADCAST_ID */ "", 24905 /* EGQ_SBUS_LAST_IN_CHAIN */ "", 24906 /* EGQ_SHAPER_MAP_CH_ARB_TO_IFC */ "", 24907 /* EGQ_SOP_IFC_DELAY_CONFIGURATION */ "", 24908 /* EGQ_SPLIT_HORIZON_FILTER */ "", 24909 /* EGQ_SYSTEM_HEADERS_FORMAT_CODE */ "", 24910 /* EGQ_SYSTEM_HEADERS_VALUE_1_OFFSET */ "", 24911 /* EGQ_SYSTEM_HEADERS_VALUE_2_OFFSET */ "", 24912 /* EGQ_TCG_SPR_DIS */ "", 24913 /* EGQ_TDM_GENERAL_CONFIGURATION */ "", 24914 /* EGQ_TDM_MAP_QUEUE_TO_TDM */ "", 24915 /* EGQ_TOTAL_EGQ_BW_MAX_BURST */ "", 24916 /* EGQ_TPID_PROFILES */ "", 24917 /* EGQ_TRILL_CONFIG */ "", 24918 /* EGQ_TTL_SCOPE */ "", 24919 /* EGQ_UNICAST_EGRESS_PACKET_HEADER_COMPENSATION_FOR_TYPE_A */ "", 24920 /* EGQ_UNICAST_EGRESS_PACKET_HEADER_COMPENSATION_FOR_TYPE_B */ "", 24921 /* EGQ_WDRR_PACKET_SIZE */ "", 24922 /* EGQ_WFQ_PACKET_SIZE */ "", 24923 /* EGQ_WFQ_TCG_DIS */ "", 24924 /* EGRDROPPKTCOUNT */ "", 24925 /* EGRDROPPKTCOUNT_COS */ "", 24926 /* EGRESSCELLREQUESTCOUNT */ "", 24927 /* EGRESSCELLREQUESTCOUNT_PREEMPT */ "", 24928 /* EGRESS_PACKET_BUFFER_CONTROL_INFO */ "", 24929 /* EGRMETERINGBUCKET */ "", 24930 /* EGRMETERINGCONFIG */ "", 24931 /* EGRMETERINGCONFIG1 */ "", 24932 /* EGRMETERINGCONFIG_64 */ "EGRMETERINGCONFIG", 24933 /* EGRSHAPEPARITYERRORPTR */ "", 24934 /* EGRTXPKTCTR */ "", 24935 /* EGRTXPKTCTR0 */ "", 24936 /* EGRTXPKTCTR1 */ "", 24937 /* EGRTXPKTCTR2 */ "", 24938 /* EGRTXPKTCTR3 */ "", 24939 /* EGRTXPKTCTR4 */ "", 24940 /* EGRTXPKTCTR5 */ "", 24941 /* EGRTXPKTCTR6 */ "", 24942 /* EGRTXPKTCTR7 */ "", 24943 /* EGRTXPKTCTRCONFIG */ "", 24944 /* EGRTXPKTCTRCONFIG0 */ "", 24945 /* EGRTXPKTCTRCONFIG1 */ "", 24946 /* EGRTXPKTCTRCONFIG2 */ "", 24947 /* EGRTXPKTCTRCONFIG3 */ "", 24948 /* EGRTXPKTCTRCONFIG4 */ "", 24949 /* EGRTXPKTCTRCONFIG5 */ "", 24950 /* EGRTXPKTCTRCONFIG6 */ "", 24951 /* EGRTXPKTCTRCONFIG7 */ "", 24952 /* EGR_1588OMPLS */ "", 24953 /* EGR_1588_CLOCK_ADDRESS */ "", 24954 /* EGR_1588_EGRESS_CTRL */ "", 24955 /* EGR_1588_INGRESS_CTRL */ "", 24956 /* EGR_1588_INGRESS_CTRL_2 */ "", 24957 /* EGR_1588_LINK_DELAY */ "", 24958 /* EGR_1588_LINK_DELAY_64 */ "", 24959 /* EGR_1588_LINK_DELAY_64_PARITY_CONTROL */ "", 24960 /* EGR_1588_LINK_DELAY_64_PARITY_STATUS_INTR */ "", 24961 /* EGR_1588_LINK_DELAY_64_PARITY_STATUS_NACK */ "", 24962 /* EGR_1588_PARSING_CONTROL */ "", 24963 /* EGR_1588_SA_PARITY_CONTROL */ "", 24964 /* EGR_1588_SA_PARITY_STATUS_INTR */ "", 24965 /* EGR_1588_SA_PARITY_STATUS_NACK */ "", 24966 /* EGR_1588_TIMER_DEBUG */ "", 24967 /* EGR_1588_TIMER_VALUE */ "", 24968 /* EGR_ACCU_8BEATS */ "", 24969 /* EGR_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 24970 /* EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUS */ "", 24971 /* EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 24972 /* EGR_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 24973 /* EGR_ADAPT_1_KEY_GEN_SER_CONTROL */ "", 24974 /* EGR_ADAPT_1_KEY_GEN_TM_CONTROL_64 */ "", 24975 /* EGR_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 24976 /* EGR_ADAPT_2_KEY_GEN_CAM_BIST_STATUS */ "", 24977 /* EGR_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 24978 /* EGR_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 24979 /* EGR_ADAPT_2_KEY_GEN_SER_CONTROL */ "", 24980 /* EGR_ADAPT_2_KEY_GEN_TM_CONTROL_64 */ "", 24981 /* EGR_ARB_MISC_CONTROL */ "", 24982 /* EGR_ARB_MISC_CONTROL_CORE */ "", 24983 /* EGR_ARB_SER_SCAN_CONFIG */ "", 24984 /* EGR_ARB_SER_SCAN_CONFIG_PIPE0 */ "", 24985 /* EGR_ARB_SER_SCAN_CONFIG_PIPE1 */ "", 24986 /* EGR_ARB_SER_SCAN_CONFIG_PIPE2 */ "", 24987 /* EGR_ARB_SER_SCAN_CONFIG_PIPE3 */ "", 24988 /* EGR_ARB_SER_SCAN_CONFIG_PIPE4 */ "", 24989 /* EGR_ARB_SER_SCAN_CONFIG_PIPE5 */ "", 24990 /* EGR_ARB_SER_SCAN_CONFIG_PIPE6 */ "", 24991 /* EGR_ARB_SER_SCAN_CONFIG_PIPE7 */ "", 24992 /* EGR_ARB_SER_SCAN_STATUS */ "", 24993 /* EGR_ARB_SER_SCAN_STATUS_PIPE0 */ "", 24994 /* EGR_ARB_SER_SCAN_STATUS_PIPE1 */ "", 24995 /* EGR_ARB_SER_SCAN_STATUS_PIPE2 */ "", 24996 /* EGR_ARB_SER_SCAN_STATUS_PIPE3 */ "", 24997 /* EGR_ARB_SER_SCAN_STATUS_PIPE4 */ "", 24998 /* EGR_ARB_SER_SCAN_STATUS_PIPE5 */ "", 24999 /* EGR_ARB_SER_SCAN_STATUS_PIPE6 */ "", 25000 /* EGR_ARB_SER_SCAN_STATUS_PIPE7 */ "", 25001 /* EGR_ARB_TIMEOUT_CONTROL */ "", 25002 /* EGR_ARB_TIMEOUT_CONTROL_CORE */ "", 25003 /* EGR_BUS_PARITY_ERR_COUNTER */ "", 25004 /* EGR_BYPASS_CTRL */ "", 25005 /* EGR_CAPWAP_FRAG_CONTROL */ "", 25006 /* EGR_CLPORT_BUFFER_SFT_RESET */ "", 25007 /* EGR_CL_PARITY_STATUS */ "", 25008 /* EGR_CM_BUFFER_STATUS_INTR */ "", 25009 /* EGR_CM_DBITS_PARITY_STATUS */ "", 25010 /* EGR_CM_DBUF_PARITY_CONTROL */ "", 25011 /* EGR_CM_DBUF_PARITY_STATUS */ "", 25012 /* EGR_CM_PARITY_STATUS */ "", 25013 /* EGR_CONFIG */ "", 25014 /* EGR_CONFIG_1 */ "", 25015 /* EGR_CONFIG_2 */ "", 25016 /* EGR_CONFIG_1_64 */ "EGR_CONFIG_1", 25017 /* EGR_COUNTER_CONTROL */ "", 25018 /* EGR_CPU_CONTROL */ "", 25019 /* EGR_CPU_CONTROL_1_64 */ "", 25020 /* EGR_CPU_CONTROL_2_64 */ "", 25021 /* EGR_CPU_COS_CONTROL_2 */ "", 25022 /* EGR_CPU_COS_CONTROL_1_64 */ "EGR_CPU_COS_CONTROL_1", 25023 /* EGR_DATABUF_CM_RAM_CTRL */ "", 25024 /* EGR_DATABUF_FC0_RAM_CTRL */ "", 25025 /* EGR_DATABUF_FC1_RAM_CTRL */ "", 25026 /* EGR_DATABUF_ISO_CONTROL_1 */ "", 25027 /* EGR_DATABUF_ISO_CONTROL_1_PIPE0 */ "", 25028 /* EGR_DATABUF_ISO_CONTROL_1_PIPE1 */ "", 25029 /* EGR_DATABUF_ISO_CONTROL_1_PIPE2 */ "", 25030 /* EGR_DATABUF_ISO_CONTROL_1_PIPE3 */ "", 25031 /* EGR_DATABUF_LP_RAM_CTRL */ "", 25032 /* EGR_DATABUF_LVM_CONTROL_1 */ "", 25033 /* EGR_DATABUF_LVM_CONTROL_1_PIPE0 */ "", 25034 /* EGR_DATABUF_LVM_CONTROL_1_PIPE1 */ "", 25035 /* EGR_DATABUF_LVM_CONTROL_1_PIPE2 */ "", 25036 /* EGR_DATABUF_LVM_CONTROL_1_PIPE3 */ "", 25037 /* EGR_DATABUF_RAM_CONTROL_0 */ "", 25038 /* EGR_DATABUF_RAM_CONTROL_1 */ "", 25039 /* EGR_DATABUF_RAM_CONTROL_2 */ "", 25040 /* EGR_DATABUF_RAM_CONTROL_3 */ "", 25041 /* EGR_DATABUF_RAM_CONTROL_4 */ "", 25042 /* EGR_DATABUF_RAM_CONTROL_5 */ "", 25043 /* EGR_DATABUF_RAM_CONTROL_6 */ "", 25044 /* EGR_DATABUF_RAM_CONTROL_1_PIPE0 */ "", 25045 /* EGR_DATABUF_RAM_CONTROL_1_PIPE1 */ "", 25046 /* EGR_DATABUF_RAM_CONTROL_1_PIPE2 */ "", 25047 /* EGR_DATABUF_RAM_CONTROL_1_PIPE3 */ "", 25048 /* EGR_DATABUF_RAM_CONTROL_2_PIPE0 */ "", 25049 /* EGR_DATABUF_RAM_CONTROL_2_PIPE1 */ "", 25050 /* EGR_DATABUF_RAM_CONTROL_2_PIPE2 */ "", 25051 /* EGR_DATABUF_RAM_CONTROL_2_PIPE3 */ "", 25052 /* EGR_DATABUF_RAM_CONTROL_3_PIPE0 */ "", 25053 /* EGR_DATABUF_RAM_CONTROL_3_PIPE1 */ "", 25054 /* EGR_DATABUF_RAM_CONTROL_3_PIPE2 */ "", 25055 /* EGR_DATABUF_RAM_CONTROL_3_PIPE3 */ "", 25056 /* EGR_DATABUF_RAM_CONTROL_4_PIPE0 */ "", 25057 /* EGR_DATABUF_RAM_CONTROL_4_PIPE1 */ "", 25058 /* EGR_DATABUF_RAM_CONTROL_4_PIPE2 */ "", 25059 /* EGR_DATABUF_RAM_CONTROL_4_PIPE3 */ "", 25060 /* EGR_DATABUF_RAM_CONTROL_5_PIPE0 */ "", 25061 /* EGR_DATABUF_RAM_CONTROL_5_PIPE1 */ "", 25062 /* EGR_DATABUF_RAM_CONTROL_5_PIPE2 */ "", 25063 /* EGR_DATABUF_RAM_CONTROL_5_PIPE3 */ "", 25064 /* EGR_DATABUF_RAM_CONTROL_6_PIPE0 */ "", 25065 /* EGR_DATABUF_RAM_CONTROL_6_PIPE1 */ "", 25066 /* EGR_DATABUF_RAM_CONTROL_DCM */ "", 25067 /* EGR_DATABUF_RAM_CONTROL_MISC */ "", 25068 /* EGR_DATABUF_RAM_CONTROL_PM */ "", 25069 /* EGR_DATABUF_RAM_CONTROL_STBY */ "", 25070 /* EGR_DATABUF_RDT_CONTROL_1 */ "", 25071 /* EGR_DATABUF_RDT_CONTROL_1_PIPE0 */ "", 25072 /* EGR_DATABUF_RDT_CONTROL_1_PIPE1 */ "", 25073 /* EGR_DATABUF_RDT_CONTROL_1_PIPE2 */ "", 25074 /* EGR_DATABUF_RDT_CONTROL_1_PIPE3 */ "", 25075 /* EGR_DATABUF_RESI_RAM_CTRL */ "", 25076 /* EGR_DATABUF_WBT_CONTROL_1 */ "", 25077 /* EGR_DATABUF_WBT_CONTROL_1_PIPE0 */ "", 25078 /* EGR_DATABUF_WBT_CONTROL_1_PIPE1 */ "", 25079 /* EGR_DATABUF_WBT_CONTROL_1_PIPE2 */ "", 25080 /* EGR_DATABUF_WBT_CONTROL_1_PIPE3 */ "", 25081 /* EGR_DATABUF_XQ1_RAM_CTRL */ "", 25082 /* EGR_DATABUF_XQ2_RAM_CTRL */ "", 25083 /* EGR_DATABUF_XQ3_RAM_CTRL */ "", 25084 /* EGR_DATABUF_XQ4_RAM_CTRL */ "", 25085 /* EGR_DATABUF_XQ5_RAM_CTRL */ "", 25086 /* EGR_DATABUF_XQ6_RAM_CTRL */ "", 25087 /* EGR_DATABUF_XQ7_RAM_CTRL */ "", 25088 /* EGR_DATABUF_XQ8_RAM_CTRL */ "", 25089 /* EGR_DATABUF_XQ9_RAM_CTRL */ "", 25090 /* EGR_DATAPATH_STATUS_INTR_0 */ "", 25091 /* EGR_DATAPATH_STATUS_INTR_1 */ "", 25092 /* EGR_DBG */ "", 25093 /* EGR_DBG_2 */ "", 25094 /* EGR_DEVICE_TO_PHYSICAL_PORT_NUMBER_MAPPING */ "", 25095 /* EGR_DOP_CTRL_0_64 */ "", 25096 /* EGR_DOP_CTRL_0_64_PIPE0 */ "", 25097 /* EGR_DOP_CTRL_0_64_PIPE1 */ "", 25098 /* EGR_DOP_CTRL_1_64 */ "", 25099 /* EGR_DOP_CTRL_1_64_PIPE0 */ "", 25100 /* EGR_DOP_CTRL_1_64_PIPE1 */ "", 25101 /* EGR_DOP_CTRL_2_64 */ "", 25102 /* EGR_DOP_CTRL_2_64_PIPE0 */ "", 25103 /* EGR_DOP_CTRL_2_64_PIPE1 */ "", 25104 /* EGR_DOP_STATUS_0 */ "", 25105 /* EGR_DOP_STATUS_0_PIPE0 */ "", 25106 /* EGR_DOP_STATUS_0_PIPE1 */ "", 25107 /* EGR_DOP_STATUS_1_64 */ "", 25108 /* EGR_DOP_STATUS_1_64_PIPE0 */ "", 25109 /* EGR_DOP_STATUS_1_64_PIPE1 */ "", 25110 /* EGR_DROP_VECTOR */ "", 25111 /* EGR_DROP_VECTOR_MASK */ "", 25112 /* EGR_DROP_VECTOR_PIPE0 */ "", 25113 /* EGR_DROP_VECTOR_PIPE1 */ "", 25114 /* EGR_DROP_VECTOR_PIPE2 */ "", 25115 /* EGR_DROP_VECTOR_PIPE3 */ "", 25116 /* EGR_DROP_VECTOR_PIPE4 */ "", 25117 /* EGR_DROP_VECTOR_PIPE5 */ "", 25118 /* EGR_DROP_VECTOR_PIPE6 */ "", 25119 /* EGR_DROP_VECTOR_PIPE7 */ "", 25120 /* EGR_DROP_VECTOR_X */ "", 25121 /* EGR_DROP_VECTOR_Y */ "", 25122 /* EGR_DSCP_TABLE_PARITY_STATUS_INTR */ "", 25123 /* EGR_DSCP_TABLE_PARITY_STATUS_NACK */ "", 25124 /* EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTR */ "", 25125 /* EGR_DVP_ATTRIBUTE_PARITY_STATUS_NACK */ "", 25126 /* EGR_DVP_ATTRIBUTE_PDA_CTRL */ "", 25127 /* EGR_EARB_CBE_ECC_STATUS */ "", 25128 /* EGR_EARB_ECC_DEBUG */ "", 25129 /* EGR_EARB_ECC_ERROR */ "", 25130 /* EGR_EARB_EVENT_FIFO_STATUS */ "", 25131 /* EGR_EARB_NULL_SLOT_CONTROL */ "", 25132 /* EGR_EARB_PBE_ECC_STATUS */ "", 25133 /* EGR_EARB_RAM_CONTROL */ "", 25134 /* EGR_EARB_RAM_CONTROL_PIPE0 */ "", 25135 /* EGR_EARB_RAM_CONTROL_PIPE1 */ "", 25136 /* EGR_EARB_RAM_CONTROL_PIPE2 */ "", 25137 /* EGR_EARB_RAM_CONTROL_PIPE3 */ "", 25138 /* EGR_EARB_RAM_CONTROL_PIPE4 */ "", 25139 /* EGR_EARB_RAM_CONTROL_PIPE5 */ "", 25140 /* EGR_EARB_RAM_CONTROL_PIPE6 */ "", 25141 /* EGR_EARB_RAM_CONTROL_PIPE7 */ "", 25142 /* EGR_EARB_SER_CONTROL */ "", 25143 /* EGR_EAV_CLASS */ "", 25144 /* EGR_ECC_CONTROL */ "", 25145 /* EGR_ECC_STATUS */ "", 25146 /* EGR_ECN_CONTROL */ "", 25147 /* EGR_ECN_COUNTER */ "", 25148 /* EGR_ECN_COUNTER_64 */ "EGR_ECN_COUNTER", 25149 /* EGR_ECN_COUNTER_PARITY_STATUS */ "", 25150 /* EGR_EDATABUF_ECC_CONTROL */ "", 25151 /* EGR_EDATABUF_EN_COR_ERR_RPT */ "", 25152 /* EGR_EDATABUF_EN_COR_ERR_RPT_1 */ "", 25153 /* EGR_EDATABUF_GP_RAM_CONTROL */ "", 25154 /* EGR_EDATABUF_PARITY_CONTROL */ "", 25155 /* EGR_EDATABUF_PARITY_CONTROL_64 */ "", 25156 /* EGR_EDATABUF_PDA_CONTROL */ "", 25157 /* EGR_EDATABUF_PDA_CONTROL_1 */ "", 25158 /* EGR_EDATABUF_PDA_CONTROL_PIPE0 */ "", 25159 /* EGR_EDATABUF_PDA_CONTROL_PIPE1 */ "", 25160 /* EGR_EDATABUF_PDA_CONTROL_PIPE2 */ "", 25161 /* EGR_EDATABUF_PDA_CONTROL_PIPE3 */ "", 25162 /* EGR_EDATABUF_RAM_CONTROL0_64 */ "", 25163 /* EGR_EDATABUF_RAM_CONTROL1_64 */ "", 25164 /* EGR_EDATABUF_RAM_CONTROL2_64 */ "", 25165 /* EGR_EDATABUF_RAM_CONTROL_1 */ "", 25166 /* EGR_EDATABUF_RAM_CONTROL_2 */ "", 25167 /* EGR_EDATABUF_STBY_CONTROL */ "", 25168 /* EGR_EDATABUF_XP_RAM_CONTROL_64 */ "", 25169 /* EGR_EDBIL_PKT_BYTES */ "", 25170 /* EGR_EDBIL_STATUS */ "", 25171 /* EGR_EDB_BUS_PARITY_DEBUG */ "", 25172 /* EGR_EDB_CM_ECC_STATUS */ "", 25173 /* EGR_EDB_CTRL_ECC_EN */ "", 25174 /* EGR_EDB_CTRL_PARITY_EN */ "", 25175 /* EGR_EDB_CTRL_PDA_EN */ "", 25176 /* EGR_EDB_DEBUG_SFT_RESET */ "", 25177 /* EGR_EDB_ECC_DEBUG */ "", 25178 /* EGR_EDB_ECC_ERROR */ "", 25179 /* EGR_EDB_EN_COR_ERR_RPT_PKT_LEN */ "", 25180 /* EGR_EDB_EN_COR_ERR_RPT_PREEMPT_LOOKUP */ "", 25181 /* EGR_EDB_EN_COR_ERR_RPT_PREEMPT_XFR_COUNT */ "", 25182 /* EGR_EDB_HW_CONTROL */ "", 25183 /* EGR_EDB_IX0A_ECC_STATUS */ "", 25184 /* EGR_EDB_IX0B_ECC_STATUS */ "", 25185 /* EGR_EDB_IX1A_ECC_STATUS */ "", 25186 /* EGR_EDB_IX1B_ECC_STATUS */ "", 25187 /* EGR_EDB_MIN_STARTCNT */ "", 25188 /* EGR_EDB_MISC_CTRL */ "", 25189 /* EGR_EDB_MISC_CTRL_PIPE0 */ "", 25190 /* EGR_EDB_MISC_CTRL_PIPE1 */ "", 25191 /* EGR_EDB_MISC_CTRL_PIPE2 */ "", 25192 /* EGR_EDB_MISC_CTRL_PIPE3 */ "", 25193 /* EGR_EDB_MS0_ECC_STATUS */ "", 25194 /* EGR_EDB_MS1_ECC_STATUS */ "", 25195 /* EGR_EDB_PARITY_ERROR */ "", 25196 /* EGR_EDB_PKT_LEN_PARITY_EN */ "", 25197 /* EGR_EDB_PREEMPT_LOOKUP_PARITY_EN */ "", 25198 /* EGR_EDB_PREEMPT_XFR_COUNT_PARITY_EN */ "", 25199 /* EGR_EFPMOD_CLK_GATING_CONTROL */ "", 25200 /* EGR_EFPMOD_PARITY_CONTROL */ "", 25201 /* EGR_EFPMOD_RAM_CONTROL */ "", 25202 /* EGR_EFPMOD_RAM_CONTROL_PIPE0 */ "", 25203 /* EGR_EFPMOD_RAM_CONTROL_PIPE1 */ "", 25204 /* EGR_EFPMOD_RAM_CONTROL_PIPE2 */ "", 25205 /* EGR_EFPMOD_RAM_CONTROL_PIPE3 */ "", 25206 /* EGR_EFPMOD_SER_CONTROL */ "", 25207 /* EGR_EFPPARS_CLK_GATING_CONTROL */ "", 25208 /* EGR_EFPPARS_OPAQUE_TAG_CONFIG_0 */ "", 25209 /* EGR_EFPPARS_OPAQUE_TAG_CONFIG_1 */ "", 25210 /* EGR_EFPPARS_PARITY_CONTROL */ "", 25211 /* EGR_EFPPARS_RAM_CONTROL */ "", 25212 /* EGR_EFPPARS_RAM_CONTROL_PIPE0 */ "", 25213 /* EGR_EFPPARS_RAM_CONTROL_PIPE1 */ "", 25214 /* EGR_EFPPARS_RAM_CONTROL_PIPE2 */ "", 25215 /* EGR_EFPPARS_RAM_CONTROL_PIPE3 */ "", 25216 /* EGR_EFPPARS_RAM_CONTROL_PIPE4 */ "", 25217 /* EGR_EFPPARS_RAM_CONTROL_PIPE5 */ "", 25218 /* EGR_EFPPARS_RAM_CONTROL_PIPE6 */ "", 25219 /* EGR_EFPPARS_RAM_CONTROL_PIPE7 */ "", 25220 /* EGR_EFPPARS_SER_CONTROL */ "", 25221 /* EGR_EFPPARS_TABLE_CONTROL */ "", 25222 /* EGR_EFP_CLK_GATING_CONTROL */ "", 25223 /* EGR_EFP_CNTR_UPDATE_CONTROL */ "", 25224 /* EGR_EFP_CNTR_UPDATE_CONTROL_PIPE0 */ "", 25225 /* EGR_EFP_CNTR_UPDATE_CONTROL_PIPE1 */ "", 25226 /* EGR_EFP_CNTR_UPDATE_CONTROL_PIPE2 */ "", 25227 /* EGR_EFP_CNTR_UPDATE_CONTROL_PIPE3 */ "", 25228 /* EGR_EFP_COUNTER_TABLE_PARITY_STATUS_INTR */ "", 25229 /* EGR_EFP_COUNTER_TABLE_PARITY_STATUS_NACK */ "", 25230 /* EGR_EFP_EN_COR_ERR_RPT */ "", 25231 /* EGR_EFP_EVICTION_CONTROL */ "", 25232 /* EGR_EFP_EVICTION_CONTROL_PIPE0 */ "", 25233 /* EGR_EFP_EVICTION_CONTROL_PIPE1 */ "", 25234 /* EGR_EFP_EVICTION_CONTROL_PIPE2 */ "", 25235 /* EGR_EFP_EVICTION_CONTROL_PIPE3 */ "", 25236 /* EGR_EFP_EVICTION_CONTROL_PIPE4 */ "", 25237 /* EGR_EFP_EVICTION_CONTROL_PIPE5 */ "", 25238 /* EGR_EFP_EVICTION_CONTROL_PIPE6 */ "", 25239 /* EGR_EFP_EVICTION_CONTROL_PIPE7 */ "", 25240 /* EGR_EFP_EVICTION_FAIL */ "", 25241 /* EGR_EFP_EVICTION_FAIL_PIPE0 */ "", 25242 /* EGR_EFP_EVICTION_FAIL_PIPE1 */ "", 25243 /* EGR_EFP_EVICTION_FAIL_PIPE2 */ "", 25244 /* EGR_EFP_EVICTION_FAIL_PIPE3 */ "", 25245 /* EGR_EFP_EVICTION_FAIL_PIPE4 */ "", 25246 /* EGR_EFP_EVICTION_FAIL_PIPE5 */ "", 25247 /* EGR_EFP_EVICTION_FAIL_PIPE6 */ "", 25248 /* EGR_EFP_EVICTION_FAIL_PIPE7 */ "", 25249 /* EGR_EFP_EVICTION_SEED */ "", 25250 /* EGR_EFP_EVICTION_SEED_PIPE0 */ "", 25251 /* EGR_EFP_EVICTION_SEED_PIPE1 */ "", 25252 /* EGR_EFP_EVICTION_SEED_PIPE2 */ "", 25253 /* EGR_EFP_EVICTION_SEED_PIPE3 */ "", 25254 /* EGR_EFP_EVICTION_SEED_PIPE4 */ "", 25255 /* EGR_EFP_EVICTION_SEED_PIPE5 */ "", 25256 /* EGR_EFP_EVICTION_SEED_PIPE6 */ "", 25257 /* EGR_EFP_EVICTION_SEED_PIPE7 */ "", 25258 /* EGR_EFP_EVICTION_THRESHOLD */ "", 25259 /* EGR_EFP_EVICTION_THRESHOLD_PIPE0 */ "", 25260 /* EGR_EFP_EVICTION_THRESHOLD_PIPE1 */ "", 25261 /* EGR_EFP_EVICTION_THRESHOLD_PIPE2 */ "", 25262 /* EGR_EFP_EVICTION_THRESHOLD_PIPE3 */ "", 25263 /* EGR_EHCPM_BUS_PARITY_DEBUG */ "", 25264 /* EGR_EHCPM_CLK_GATING_CONTROL */ "", 25265 /* EGR_EHCPM_ECC_DEBUG */ "", 25266 /* EGR_EHCPM_ECC_ERROR */ "", 25267 /* EGR_EHCPM_ECC_PARITY_CONTROL */ "", 25268 /* EGR_EHCPM_EINITBUF_RAM_ECC_STATUS */ "", 25269 /* EGR_EHCPM_EN_COR_ERR_RPT */ "", 25270 /* EGR_EHCPM_PARITY_CONTROL */ "", 25271 /* EGR_EHCPM_PARITY_ERROR */ "", 25272 /* EGR_EHCPM_RAM_CONTROL */ "", 25273 /* EGR_EHCPM_RAM_CONTROL_1 */ "", 25274 /* EGR_EHCPM_RAM_CONTROL_PIPE0 */ "", 25275 /* EGR_EHCPM_RAM_CONTROL_PIPE1 */ "", 25276 /* EGR_EHCPM_RAM_CONTROL_PIPE2 */ "", 25277 /* EGR_EHCPM_RAM_CONTROL_PIPE3 */ "", 25278 /* EGR_EHCPM_RAM_CONTROL_STBY */ "", 25279 /* EGR_EHCPM_SCI_TABLE_ECC_STATUS */ "", 25280 /* EGR_EHCPM_SER_CONTROL */ "", 25281 /* EGR_EHG_ETHERTYPE */ "", 25282 /* EGR_EHG_HEADER_CONTROL */ "", 25283 /* EGR_EHG_QOS_MAPPING_ECC_STATUS_INTR */ "", 25284 /* EGR_EHG_QOS_MAPPING_ECC_STATUS_NACK */ "", 25285 /* EGR_EIPT_CLK_GATING_CONTROL */ "", 25286 /* EGR_EIPT_ECC_CONTROL */ "", 25287 /* EGR_EIPT_RAM_CONTROL */ "", 25288 /* EGR_EL3_CLK_GATING_CONTROL */ "", 25289 /* EGR_EL3_ECC_PARITY_CONTROL */ "", 25290 /* EGR_EL3_EN_COR_ERR_RPT */ "", 25291 /* EGR_EL3_PARITY_CONTROL */ "", 25292 /* EGR_EL3_PM_CONTROL */ "", 25293 /* EGR_EL3_PM_CONTROL_PIPE0 */ "", 25294 /* EGR_EL3_PM_CONTROL_PIPE1 */ "", 25295 /* EGR_EL3_PM_CONTROL_PIPE2 */ "", 25296 /* EGR_EL3_PM_CONTROL_PIPE3 */ "", 25297 /* EGR_EL3_RAM_CONTROL */ "", 25298 /* EGR_EL3_RAM_CONTROL_2 */ "", 25299 /* EGR_EL3_RAM_CONTROL_3 */ "", 25300 /* EGR_EL3_RAM_CONTROL_4 */ "", 25301 /* EGR_EL3_RAM_CONTROL_5 */ "", 25302 /* EGR_EL3_RAM_CONTROL_6 */ "", 25303 /* EGR_EL3_RAM_CONTROL_7 */ "", 25304 /* EGR_EL3_RAM_CONTROL_8 */ "", 25305 /* EGR_EL3_RAM_CONTROL_9 */ "", 25306 /* EGR_EL3_RAM_CONTROL_10 */ "", 25307 /* EGR_EL3_RAM_CONTROL_11 */ "", 25308 /* EGR_EL3_RAM_CONTROL_64 */ "EGR_EL3_RAM_CONTROL", 25309 /* EGR_EL3_RAM_CONTROL_2_64 */ "EGR_EL3_RAM_CONTROL_2", 25310 /* EGR_EL3_RAM_CONTROL_2_64_PIPE0 */ "EGR_EL3_RAM_CONTROL_2_PIPE0", 25311 /* EGR_EL3_RAM_CONTROL_2_64_PIPE1 */ "EGR_EL3_RAM_CONTROL_2_PIPE1", 25312 /* EGR_EL3_RAM_CONTROL_2_64_PIPE2 */ "EGR_EL3_RAM_CONTROL_2_PIPE2", 25313 /* EGR_EL3_RAM_CONTROL_2_64_PIPE3 */ "EGR_EL3_RAM_CONTROL_2_PIPE3", 25314 /* EGR_EL3_RAM_CONTROL_2_PIPE0 */ "", 25315 /* EGR_EL3_RAM_CONTROL_2_PIPE1 */ "", 25316 /* EGR_EL3_RAM_CONTROL_2_PIPE2 */ "", 25317 /* EGR_EL3_RAM_CONTROL_2_PIPE3 */ "", 25318 /* EGR_EL3_RAM_CONTROL_3_64 */ "EGR_EL3_RAM_CONTROL_3", 25319 /* EGR_EL3_RAM_CONTROL_3_64_PIPE0 */ "EGR_EL3_RAM_CONTROL_3_PIPE0", 25320 /* EGR_EL3_RAM_CONTROL_3_64_PIPE1 */ "EGR_EL3_RAM_CONTROL_3_PIPE1", 25321 /* EGR_EL3_RAM_CONTROL_3_PIPE0 */ "", 25322 /* EGR_EL3_RAM_CONTROL_3_PIPE1 */ "", 25323 /* EGR_EL3_RAM_CONTROL_3_PIPE2 */ "", 25324 /* EGR_EL3_RAM_CONTROL_3_PIPE3 */ "", 25325 /* EGR_EL3_RAM_CONTROL_4_PIPE0 */ "", 25326 /* EGR_EL3_RAM_CONTROL_4_PIPE1 */ "", 25327 /* EGR_EL3_RAM_CONTROL_4_PIPE2 */ "", 25328 /* EGR_EL3_RAM_CONTROL_4_PIPE3 */ "", 25329 /* EGR_EL3_RAM_CONTROL_5_PIPE0 */ "", 25330 /* EGR_EL3_RAM_CONTROL_5_PIPE1 */ "", 25331 /* EGR_EL3_RAM_CONTROL_5_PIPE2 */ "", 25332 /* EGR_EL3_RAM_CONTROL_5_PIPE3 */ "", 25333 /* EGR_EL3_RAM_CONTROL_64_PIPE0 */ "EGR_EL3_RAM_CONTROL_PIPE0", 25334 /* EGR_EL3_RAM_CONTROL_64_PIPE1 */ "EGR_EL3_RAM_CONTROL_PIPE1", 25335 /* EGR_EL3_RAM_CONTROL_64_PIPE2 */ "EGR_EL3_RAM_CONTROL_PIPE2", 25336 /* EGR_EL3_RAM_CONTROL_64_PIPE3 */ "EGR_EL3_RAM_CONTROL_PIPE3", 25337 /* EGR_EL3_RAM_CONTROL_6_PIPE0 */ "", 25338 /* EGR_EL3_RAM_CONTROL_6_PIPE1 */ "", 25339 /* EGR_EL3_RAM_CONTROL_6_PIPE2 */ "", 25340 /* EGR_EL3_RAM_CONTROL_6_PIPE3 */ "", 25341 /* EGR_EL3_RAM_CONTROL_MISC */ "", 25342 /* EGR_EL3_RAM_CONTROL_PIPE0 */ "", 25343 /* EGR_EL3_RAM_CONTROL_PIPE1 */ "", 25344 /* EGR_EL3_RAM_CONTROL_PIPE2 */ "", 25345 /* EGR_EL3_RAM_CONTROL_PIPE3 */ "", 25346 /* EGR_EL3_SER_CONTROL */ "", 25347 /* EGR_EL3_STBY_CONTROL */ "", 25348 /* EGR_EL3_TCAM_SER_CONTROL */ "", 25349 /* EGR_EMOP_BUFFER_ECC_STATUS_INTR */ "", 25350 /* EGR_ENABLE */ "", 25351 /* EGR_ENABLE_SELECT */ "", 25352 /* EGR_EOAM_ECC_PARITY_CONTROL */ "", 25353 /* EGR_EOAM_RAM_CONTROL */ "", 25354 /* EGR_EOAM_RAM_CONTROL_1 */ "", 25355 /* EGR_EOAM_RAM_CONTROL_DCM */ "", 25356 /* EGR_EOAM_RAM_CONTROL_PM */ "", 25357 /* EGR_EPARS_BUS_PARITY_DEBUG */ "", 25358 /* EGR_EPARS_EN_COR_ERR_RPT */ "", 25359 /* EGR_EPARS_OPAQUE_TAG_CONFIG_0 */ "", 25360 /* EGR_EPARS_OPAQUE_TAG_CONFIG_1 */ "", 25361 /* EGR_EPARS_PARITY_ERROR */ "", 25362 /* EGR_EPARS_RAM_CONTROL */ "", 25363 /* EGR_EPARS_RAM_CONTROL_PIPE0 */ "", 25364 /* EGR_EPARS_RAM_CONTROL_PIPE1 */ "", 25365 /* EGR_EPARS_RAM_CONTROL_PIPE2 */ "", 25366 /* EGR_EPARS_RAM_CONTROL_PIPE3 */ "", 25367 /* EGR_EPARS_RAM_CONTROL_PIPE4 */ "", 25368 /* EGR_EPARS_RAM_CONTROL_PIPE5 */ "", 25369 /* EGR_EPARS_RAM_CONTROL_PIPE6 */ "", 25370 /* EGR_EPARS_RAM_CONTROL_PIPE7 */ "", 25371 /* EGR_EPARS_RAM_MSP_ECC_CTRL */ "", 25372 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE0 */ "", 25373 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE1 */ "", 25374 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE2 */ "", 25375 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE3 */ "", 25376 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE4 */ "", 25377 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE5 */ "", 25378 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE6 */ "", 25379 /* EGR_EPARS_RAM_MSP_ECC_CTRL_PIPE7 */ "", 25380 /* EGR_EPARS_SER_CONTROL */ "", 25381 /* EGR_EPARS_XOR_CONTROL */ "", 25382 /* EGR_EPARS_XOR_CONTROL_PIPE0 */ "", 25383 /* EGR_EPARS_XOR_CONTROL_PIPE1 */ "", 25384 /* EGR_EPARS_XOR_CONTROL_PIPE2 */ "", 25385 /* EGR_EPARS_XOR_CONTROL_PIPE3 */ "", 25386 /* EGR_EPARS_XOR_CONTROL_PIPE4 */ "", 25387 /* EGR_EPARS_XOR_CONTROL_PIPE5 */ "", 25388 /* EGR_EPARS_XOR_CONTROL_PIPE6 */ "", 25389 /* EGR_EPARS_XOR_CONTROL_PIPE7 */ "", 25390 /* EGR_EPFS_ECC_PARITY_CONTROL */ "", 25391 /* EGR_EPFS_EN_COR_ERR_RPT */ "", 25392 /* EGR_EPFS_RAM_CONTROL_4 */ "", 25393 /* EGR_EPFS_RAM_CONTROL_5 */ "", 25394 /* EGR_EPFS_RAM_CONTROL_64 */ "EGR_EPFS_RAM_CONTROL", 25395 /* EGR_EPFS_RAM_CONTROL_2_64 */ "EGR_EPFS_RAM_CONTROL_2", 25396 /* EGR_EPFS_RAM_CONTROL_2_64_PIPE0 */ "EGR_EPFS_RAM_CONTROL_2_PIPE0", 25397 /* EGR_EPFS_RAM_CONTROL_3_64 */ "EGR_EPFS_RAM_CONTROL_3", 25398 /* EGR_EPFS_RAM_CONTROL_3_64_PIPE0 */ "EGR_EPFS_RAM_CONTROL_3_PIPE0", 25399 /* EGR_EPFS_RAM_CONTROL_4_PIPE0 */ "", 25400 /* EGR_EPFS_RAM_CONTROL_5_PIPE0 */ "", 25401 /* EGR_EPFS_RAM_CONTROL_64_PIPE0 */ "EGR_EPFS_RAM_CONTROL_PIPE0", 25402 /* EGR_EPFS_TCAM_SER_CONTROL */ "", 25403 /* EGR_EPMOD_BUS_PARITY_DEBUG */ "", 25404 /* EGR_EPMOD_CLK_GATING_CONTROL */ "", 25405 /* EGR_EPMOD_ECC_CONTROL */ "", 25406 /* EGR_EPMOD_PARITY_CONTROL */ "", 25407 /* EGR_EPMOD_PARITY_ERROR */ "", 25408 /* EGR_EPMOD_PLB_PARITY_STATUS_INTR */ "", 25409 /* EGR_EPMOD_RAM_CONTROL */ "", 25410 /* EGR_EPMOD_RAM_CONTROL_0 */ "", 25411 /* EGR_EPMOD_RAM_CONTROL_1 */ "", 25412 /* EGR_EPMOD_RAM_CONTROL_2 */ "", 25413 /* EGR_EPMOD_RAM_CONTROL_0_64 */ "", 25414 /* EGR_EPMOD_RAM_CONTROL_PIPE0 */ "", 25415 /* EGR_EPMOD_RAM_CONTROL_PIPE1 */ "", 25416 /* EGR_EPMOD_RAM_CONTROL_PIPE2 */ "", 25417 /* EGR_EPMOD_RAM_CONTROL_PIPE3 */ "", 25418 /* EGR_EPMOD_RAM_CONTROL_PIPE4 */ "", 25419 /* EGR_EPMOD_RAM_CONTROL_PIPE5 */ "", 25420 /* EGR_EPMOD_RAM_CONTROL_PIPE6 */ "", 25421 /* EGR_EPMOD_RAM_CONTROL_PIPE7 */ "", 25422 /* EGR_EPMOD_SER_CONTROL */ "", 25423 /* EGR_EPOST_RAM_CONTROL */ "", 25424 /* EGR_EPOST_RAM_CONTROL_PIPE0 */ "", 25425 /* EGR_EPOST_RAM_CONTROL_PIPE1 */ "", 25426 /* EGR_EPOST_RAM_CONTROL_PIPE2 */ "", 25427 /* EGR_EPOST_RAM_CONTROL_PIPE3 */ "", 25428 /* EGR_EPOST_RAM_CONTROL_PIPE4 */ "", 25429 /* EGR_EPOST_RAM_CONTROL_PIPE5 */ "", 25430 /* EGR_EPOST_RAM_CONTROL_PIPE6 */ "", 25431 /* EGR_EPOST_RAM_CONTROL_PIPE7 */ "", 25432 /* EGR_ESW_CLK_GATING_CONTROL */ "", 25433 /* EGR_ESW_EN_COR_ERR_RPT */ "", 25434 /* EGR_ESW_RAM_CONTROL */ "", 25435 /* EGR_ESW_RAM_CONTROL_PIPE0 */ "", 25436 /* EGR_ESW_RAM_CONTROL_PIPE1 */ "", 25437 /* EGR_ESW_RAM_CONTROL_PIPE2 */ "", 25438 /* EGR_ESW_RAM_CONTROL_PIPE3 */ "", 25439 /* EGR_ESW_RAM_CONTROL_PIPE4 */ "", 25440 /* EGR_ESW_RAM_CONTROL_PIPE5 */ "", 25441 /* EGR_ESW_RAM_CONTROL_PIPE6 */ "", 25442 /* EGR_ESW_RAM_CONTROL_PIPE7 */ "", 25443 /* EGR_ESW_SER_CONTROL */ "", 25444 /* EGR_ETAG_MULTICAST_RANGE */ "", 25445 /* EGR_ETAG_PCP_DE_MAPPING_PARITY_CONTROL */ "", 25446 /* EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUS */ "", 25447 /* EGR_EVENT_DEBUG */ "", 25448 /* EGR_EVLAN_BUS_PARITY_DEBUG */ "", 25449 /* EGR_EVLAN_CLK_GATING_CONTROL */ "", 25450 /* EGR_EVLAN_ECC_DEBUG */ "", 25451 /* EGR_EVLAN_ECC_ERROR */ "", 25452 /* EGR_EVLAN_EN_COR_ERR_RPT */ "", 25453 /* EGR_EVLAN_PARITY_ERROR */ "", 25454 /* EGR_EVLAN_SER_CONTROL */ "", 25455 /* EGR_EVLAN_VLAN_ECC_STATUS */ "", 25456 /* EGR_EVLAN_VLAN_STG_ECC_STATUS */ "", 25457 /* EGR_EVXLT_BUS_PARITY_DEBUG */ "", 25458 /* EGR_EVXLT_DSCP_ECC_STATUS */ "", 25459 /* EGR_EVXLT_ECC_DEBUG */ "", 25460 /* EGR_EVXLT_ECC_ERROR */ "", 25461 /* EGR_EVXLT_PARITY_ERROR */ "", 25462 /* EGR_EVXLT_PRI_CNG_MAP_ECC_STATUS */ "", 25463 /* EGR_EVXLT_VLAN_XLATE_L_ECC_STATUS */ "", 25464 /* EGR_EVXLT_VLAN_XLATE_U_ECC_STATUS */ "", 25465 /* EGR_FCOE_DELIMITER_ERROR_FRAMES */ "", 25466 /* EGR_FCOE_DELIMITER_ERROR_FRAMES_64 */ "EGR_FCOE_DELIMITER_ERROR_FRAMES", 25467 /* EGR_FCOE_DELIMITER_ERROR_FRAMES_64_PIPE0 */ "EGR_FCOE_DELIMITER_ERROR_FRAMES_PIPE0", 25468 /* EGR_FCOE_DELIMITER_ERROR_FRAMES_64_PIPE1 */ "EGR_FCOE_DELIMITER_ERROR_FRAMES_PIPE1", 25469 /* EGR_FCOE_DELIMITER_ERROR_FRAMES_X */ "", 25470 /* EGR_FCOE_DELIMITER_ERROR_FRAMES_Y */ "", 25471 /* EGR_FCOE_EOF */ "", 25472 /* EGR_FCOE_ETHERTYPE */ "", 25473 /* EGR_FCOE_INVALID_CRC_FRAMES */ "", 25474 /* EGR_FCOE_INVALID_CRC_FRAMES_64 */ "EGR_FCOE_INVALID_CRC_FRAMES", 25475 /* EGR_FCOE_INVALID_CRC_FRAMES_64_PIPE0 */ "EGR_FCOE_INVALID_CRC_FRAMES_PIPE0", 25476 /* EGR_FCOE_INVALID_CRC_FRAMES_64_PIPE1 */ "EGR_FCOE_INVALID_CRC_FRAMES_PIPE1", 25477 /* EGR_FCOE_INVALID_CRC_FRAMES_X */ "", 25478 /* EGR_FCOE_INVALID_CRC_FRAMES_Y */ "", 25479 /* EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_CONFIG_64 */ "", 25480 /* EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_STATUS */ "", 25481 /* EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_STATUS_PIPE0 */ "", 25482 /* EGR_FIELD_EXTRACTION_PROFILE_1_CAM_BIST_STATUS_PIPE1 */ "", 25483 /* EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_CONFIG_64 */ "", 25484 /* EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_STATUS */ "", 25485 /* EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_STATUS_PIPE0 */ "", 25486 /* EGR_FIELD_EXTRACTION_PROFILE_2_CAM_BIST_STATUS_PIPE1 */ "", 25487 /* EGR_FLEXIBLE_IPV6_EXT_HDR */ "", 25488 /* EGR_FLEXPORT_EXTRA_HOLDING */ "", 25489 /* EGR_FLEXPORT_EXTRA_HOLDING_PIPE0 */ "", 25490 /* EGR_FLEXPORT_EXTRA_HOLDING_PIPE1 */ "", 25491 /* EGR_FLEXPORT_EXTRA_HOLDING_PIPE2 */ "", 25492 /* EGR_FLEXPORT_EXTRA_HOLDING_PIPE3 */ "", 25493 /* EGR_FLEX_CONFIG */ "", 25494 /* EGR_FLEX_CONTAINER_UPDATE_OPERAND_REG */ "", 25495 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_0 */ "", 25496 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_1 */ "", 25497 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_2 */ "", 25498 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_3 */ "", 25499 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_4 */ "", 25500 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_5 */ "", 25501 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_6 */ "", 25502 /* EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_7 */ "", 25503 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_0 */ "", 25504 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_1 */ "", 25505 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_2 */ "", 25506 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_3 */ "", 25507 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_4 */ "", 25508 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_5 */ "", 25509 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_6 */ "", 25510 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_7 */ "", 25511 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_0 */ "", 25512 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_1 */ "", 25513 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_2 */ "", 25514 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_3 */ "", 25515 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_4 */ "", 25516 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_5 */ "", 25517 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_6 */ "", 25518 /* EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_7 */ "", 25519 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_0 */ "", 25520 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_1 */ "", 25521 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_2 */ "", 25522 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_3 */ "", 25523 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_4 */ "", 25524 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_5 */ "", 25525 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_6 */ "", 25526 /* EGR_FLEX_CTR_COUNTER_UPDATE_CONTROL_7 */ "", 25527 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0 */ "", 25528 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1 */ "", 25529 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2 */ "", 25530 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3 */ "", 25531 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE0 */ "", 25532 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE1 */ "", 25533 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE2 */ "", 25534 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE3 */ "", 25535 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE4 */ "", 25536 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE5 */ "", 25537 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE6 */ "", 25538 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE7 */ "", 25539 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE0 */ "", 25540 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE1 */ "", 25541 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE2 */ "", 25542 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE3 */ "", 25543 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE4 */ "", 25544 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE5 */ "", 25545 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE6 */ "", 25546 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE7 */ "", 25547 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE0 */ "", 25548 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE1 */ "", 25549 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE2 */ "", 25550 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE3 */ "", 25551 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE4 */ "", 25552 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE5 */ "", 25553 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE6 */ "", 25554 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE7 */ "", 25555 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE0 */ "", 25556 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE1 */ "", 25557 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE2 */ "", 25558 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE3 */ "", 25559 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE4 */ "", 25560 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE5 */ "", 25561 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE6 */ "", 25562 /* EGR_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE7 */ "", 25563 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0 */ "", 25564 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1 */ "", 25565 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2 */ "", 25566 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3 */ "", 25567 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE0 */ "", 25568 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE1 */ "", 25569 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE2 */ "", 25570 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE3 */ "", 25571 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE4 */ "", 25572 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE5 */ "", 25573 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE6 */ "", 25574 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE7 */ "", 25575 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE0 */ "", 25576 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE1 */ "", 25577 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE2 */ "", 25578 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE3 */ "", 25579 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE4 */ "", 25580 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE5 */ "", 25581 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE6 */ "", 25582 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE7 */ "", 25583 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE0 */ "", 25584 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE1 */ "", 25585 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE2 */ "", 25586 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE3 */ "", 25587 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE4 */ "", 25588 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE5 */ "", 25589 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE6 */ "", 25590 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE7 */ "", 25591 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE0 */ "", 25592 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE1 */ "", 25593 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE2 */ "", 25594 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE3 */ "", 25595 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE4 */ "", 25596 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE5 */ "", 25597 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE6 */ "", 25598 /* EGR_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE7 */ "", 25599 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0 */ "", 25600 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1 */ "", 25601 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2 */ "", 25602 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3 */ "", 25603 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE0 */ "", 25604 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE1 */ "", 25605 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE2 */ "", 25606 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE3 */ "", 25607 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE4 */ "", 25608 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE5 */ "", 25609 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE6 */ "", 25610 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE7 */ "", 25611 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE0 */ "", 25612 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE1 */ "", 25613 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE2 */ "", 25614 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE3 */ "", 25615 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE4 */ "", 25616 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE5 */ "", 25617 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE6 */ "", 25618 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE7 */ "", 25619 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE0 */ "", 25620 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE1 */ "", 25621 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE2 */ "", 25622 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE3 */ "", 25623 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE4 */ "", 25624 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE5 */ "", 25625 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE6 */ "", 25626 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE7 */ "", 25627 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE0 */ "", 25628 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE1 */ "", 25629 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE2 */ "", 25630 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE3 */ "", 25631 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE4 */ "", 25632 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE5 */ "", 25633 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE6 */ "", 25634 /* EGR_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE7 */ "", 25635 /* EGR_FLEX_CTR_EVICTION_THRESHOLD_POOL_0 */ "", 25636 /* EGR_FLEX_CTR_EVICTION_THRESHOLD_POOL_1 */ "", 25637 /* EGR_FLEX_CTR_EVICTION_THRESHOLD_POOL_2 */ "", 25638 /* EGR_FLEX_CTR_EVICTION_THRESHOLD_POOL_3 */ "", 25639 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_0 */ "", 25640 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_1 */ "", 25641 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_2 */ "", 25642 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_3 */ "", 25643 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_4 */ "", 25644 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_5 */ "", 25645 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_6 */ "", 25646 /* EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_7 */ "", 25647 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_0 */ "", 25648 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_1 */ "", 25649 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_2 */ "", 25650 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_3 */ "", 25651 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_4 */ "", 25652 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_5 */ "", 25653 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_6 */ "", 25654 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_7 */ "", 25655 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_0 */ "", 25656 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_1 */ "", 25657 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_2 */ "", 25658 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_3 */ "", 25659 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_4 */ "", 25660 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_5 */ "", 25661 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_6 */ "", 25662 /* EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_7 */ "", 25663 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_0 */ "", 25664 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_1 */ "", 25665 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_2 */ "", 25666 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_3 */ "", 25667 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_4 */ "", 25668 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_5 */ "", 25669 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_6 */ "", 25670 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_7 */ "", 25671 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_8 */ "", 25672 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_9 */ "", 25673 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_10 */ "", 25674 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_11 */ "", 25675 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_12 */ "", 25676 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_13 */ "", 25677 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_14 */ "", 25678 /* EGR_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_15 */ "", 25679 /* EGR_FLEX_EDITOR_ERROR_VECTOR_MASK */ "", 25680 /* EGR_FLEX_EDITOR_ERROR_VECTOR_MASK_PIPE0 */ "", 25681 /* EGR_FORCE_SAF_CONFIG */ "", 25682 /* EGR_FP_COUNTER_PARITY_CONTROL */ "", 25683 /* EGR_FP_COUNTER_PARITY_STATUS */ "", 25684 /* EGR_FP_COUNTER_TABLE_DEBUG */ "", 25685 /* EGR_FP_COUNTER_TABLE_STATUS_INTR */ "", 25686 /* EGR_FP_COUNTER_TABLE_STATUS_NACK */ "", 25687 /* EGR_FRAGMENT_ID_ECC_STATUS_INTR */ "", 25688 /* EGR_FRAGMENT_ID_ECC_STATUS_NACK */ "", 25689 /* EGR_FRAGMENT_ID_PARITY_CONTROL */ "", 25690 /* EGR_FRAGMENT_ID_PARITY_STATUS */ "", 25691 /* EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTR */ "", 25692 /* EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_NACK */ "", 25693 /* EGR_FRAG_HEADER_ECC_STATUS_INTR */ "", 25694 /* EGR_FRAG_PACKET_ECC_STATUS_INTR */ "", 25695 /* EGR_FUSE_REGS_ADDR */ "", 25696 /* EGR_FUSE_REGS_DATA */ "", 25697 /* EGR_FWD_DOMAIN_MATCH */ "", 25698 /* EGR_GBP_CONTROL */ "", 25699 /* EGR_GBP_ETHERTYPE */ "", 25700 /* EGR_GE0_PARITY_STATUS */ "", 25701 /* EGR_GE1_PARITY_STATUS */ "", 25702 /* EGR_GE2_PARITY_STATUS */ "", 25703 /* EGR_GE3_PARITY_STATUS */ "", 25704 /* EGR_GE4_PARITY_STATUS */ "", 25705 /* EGR_GE5_PARITY_STATUS */ "", 25706 /* EGR_GE6_PARITY_STATUS */ "", 25707 /* EGR_GENEVE_CONTROL */ "", 25708 /* EGR_GP0_BUFFER_STATUS_INTR */ "", 25709 /* EGR_GP0_DBITS_PARITY_STATUS */ "", 25710 /* EGR_GP0_DBUF_PARITY_CONTROL */ "", 25711 /* EGR_GP0_DBUF_PARITY_STATUS */ "", 25712 /* EGR_GP0_PARITY_STATUS */ "", 25713 /* EGR_GP1_BUFFER_STATUS_INTR */ "", 25714 /* EGR_GP1_DBITS_PARITY_STATUS */ "", 25715 /* EGR_GP1_DBUF_PARITY_CONTROL */ "", 25716 /* EGR_GP1_DBUF_PARITY_STATUS */ "", 25717 /* EGR_GP1_PARITY_STATUS */ "", 25718 /* EGR_GP2_BUFFER_STATUS_INTR */ "", 25719 /* EGR_GP2_DBITS_PARITY_STATUS */ "", 25720 /* EGR_GP2_DBUF_PARITY_CONTROL */ "", 25721 /* EGR_GP2_DBUF_PARITY_STATUS */ "", 25722 /* EGR_GP2_PARITY_STATUS */ "", 25723 /* EGR_GP3_PARITY_STATUS */ "", 25724 /* EGR_GP4_PARITY_STATUS */ "", 25725 /* EGR_GPE_CONTROL */ "", 25726 /* EGR_GPP_ATTRIBUTES_MODBASE_PARITY_CONTROL */ "", 25727 /* EGR_GPP_ATTRIBUTES_MODBASE_PARITY_STATUS */ "", 25728 /* EGR_GPP_ATTRIBUTES_MODBASE_PARITY_STATUS_INTR */ "", 25729 /* EGR_GPP_ATTRIBUTES_MODBASE_PARITY_STATUS_NACK */ "", 25730 /* EGR_GPP_ATTRIBUTES_PARITY_CONTROL */ "", 25731 /* EGR_GPP_ATTRIBUTES_PARITY_STATUS */ "", 25732 /* EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTR */ "", 25733 /* EGR_GPP_ATTRIBUTES_PARITY_STATUS_NACK */ "", 25734 /* EGR_GP_DBITS_PARITY_STATUS */ "", 25735 /* EGR_GP_RESI_DBITS_PARITY_STATUS */ "", 25736 /* EGR_GSBU_CONFIG */ "", 25737 /* EGR_HBFC_CNM_ETHERTYPE */ "", 25738 /* EGR_HBFC_CNTAG_ETHERTYPE */ "", 25739 /* EGR_HBFC_CNTAG_ETHERTYPE_2 */ "", 25740 /* EGR_HCPM_RAM_CONTROL */ "", 25741 /* EGR_HEADER_ENCAP_DATA_PARITY_CONTROL */ "", 25742 /* EGR_HEADER_ENCAP_DATA_PARITY_STATUS */ "", 25743 /* EGR_HG_EH_CONTROL_64 */ "", 25744 /* EGR_HG_HDR_PROT_STATUS_TX_CONTROL */ "", 25745 /* EGR_HG_MIRROR_EDIT_CTRL_ID */ "", 25746 /* EGR_HG_PPD0_RX_VC_LABEL_OVERLAY_CONTROL */ "", 25747 /* EGR_HG_PPD0_TX_VC_LABEL_OVERLAY_CONTROL */ "", 25748 /* EGR_HISTO_DST_PORT_MAP */ "", 25749 /* EGR_HISTO_MON_0_CONFIG */ "", 25750 /* EGR_HISTO_MON_0_FLEX_BANK_SEL_0 */ "", 25751 /* EGR_HISTO_MON_0_FLEX_BANK_SEL_1 */ "", 25752 /* EGR_HISTO_MON_0_FLEX_COUNTER_WRAP_COUNTER */ "", 25753 /* EGR_HISTO_MON_0_HISTOGRAM_SET */ "", 25754 /* EGR_HISTO_MON_0_LAST_COUNTER_INDEX */ "", 25755 /* EGR_HISTO_MON_1_CONFIG */ "", 25756 /* EGR_HISTO_MON_1_FLEX_BANK_SEL_0 */ "", 25757 /* EGR_HISTO_MON_1_FLEX_BANK_SEL_1 */ "", 25758 /* EGR_HISTO_MON_1_FLEX_COUNTER_WRAP_COUNTER */ "", 25759 /* EGR_HISTO_MON_1_HISTOGRAM_SET */ "", 25760 /* EGR_HISTO_MON_1_LAST_COUNTER_INDEX */ "", 25761 /* EGR_HISTO_MON_2_CONFIG */ "", 25762 /* EGR_HISTO_MON_2_FLEX_BANK_SEL_0 */ "", 25763 /* EGR_HISTO_MON_2_FLEX_BANK_SEL_1 */ "", 25764 /* EGR_HISTO_MON_2_FLEX_COUNTER_WRAP_COUNTER */ "", 25765 /* EGR_HISTO_MON_2_HISTOGRAM_SET */ "", 25766 /* EGR_HISTO_MON_2_LAST_COUNTER_INDEX */ "", 25767 /* EGR_HISTO_MON_3_CONFIG */ "", 25768 /* EGR_HISTO_MON_3_FLEX_BANK_SEL_0 */ "", 25769 /* EGR_HISTO_MON_3_FLEX_BANK_SEL_1 */ "", 25770 /* EGR_HISTO_MON_3_FLEX_COUNTER_WRAP_COUNTER */ "", 25771 /* EGR_HISTO_MON_3_HISTOGRAM_SET */ "", 25772 /* EGR_HISTO_MON_3_LAST_COUNTER_INDEX */ "", 25773 /* EGR_HISTO_SRC_PORT_MAP */ "", 25774 /* EGR_HW_CONTROL */ "", 25775 /* EGR_HW_RESET_CONTROL_0 */ "", 25776 /* EGR_HW_RESET_CONTROL_1 */ "", 25777 /* EGR_HW_RESET_CONTROL_0_CORE */ "", 25778 /* EGR_HW_RESET_CONTROL_1_CORE */ "", 25779 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE0 */ "", 25780 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE1 */ "", 25781 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE2 */ "", 25782 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE3 */ "", 25783 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE4 */ "", 25784 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE5 */ "", 25785 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE6 */ "", 25786 /* EGR_HW_RESET_CONTROL_1_CORE_PIPE7 */ "", 25787 /* EGR_HW_RESET_CONTROL_1_PIPE0 */ "", 25788 /* EGR_HW_RESET_CONTROL_1_PIPE1 */ "", 25789 /* EGR_HW_RESET_CONTROL_1_PIPE2 */ "", 25790 /* EGR_HW_RESET_CONTROL_1_PIPE3 */ "", 25791 /* EGR_HW_RESET_CONTROL_1_PIPE4 */ "", 25792 /* EGR_HW_RESET_CONTROL_1_PIPE5 */ "", 25793 /* EGR_HW_RESET_CONTROL_1_PIPE6 */ "", 25794 /* EGR_HW_RESET_CONTROL_1_PIPE7 */ "", 25795 /* EGR_HW_RESET_CONTROL_1_X */ "", 25796 /* EGR_HW_RESET_CONTROL_1_Y */ "", 25797 /* EGR_INGRESS_PORT_TPID_SELECT */ "", 25798 /* EGR_INITBUF_ECC_CONTROL */ "", 25799 /* EGR_INITBUF_ECC_STATUS_DBE */ "", 25800 /* EGR_INITBUF_ECC_STATUS_INTR */ "", 25801 /* EGR_INITBUF_ECC_STATUS_SBE */ "", 25802 /* EGR_INNER_TPID */ "", 25803 /* EGR_INNER_TPID_0 */ "", 25804 /* EGR_INNER_TPID_1 */ "", 25805 /* EGR_INNER_TPID_2 */ "", 25806 /* EGR_INNER_TPID_3 */ "", 25807 /* EGR_INTR0 */ "", 25808 /* EGR_INTR1 */ "", 25809 /* EGR_INTR0_ENABLE */ "", 25810 /* EGR_INTR0_MASK */ "", 25811 /* EGR_INTR0_STATUS */ "", 25812 /* EGR_INTR1_ENABLE */ "", 25813 /* EGR_INTR1_MASK */ "", 25814 /* EGR_INTR1_STATUS */ "", 25815 /* EGR_INTR2_ENABLE */ "", 25816 /* EGR_INTR2_STATUS */ "", 25817 /* EGR_INTR_ENABLE */ "", 25818 /* EGR_INTR_ENABLE_2 */ "", 25819 /* EGR_INTR_ENABLE_64 */ "", 25820 /* EGR_INTR_ENABLE_PIPE0 */ "", 25821 /* EGR_INTR_STATUS */ "", 25822 /* EGR_INTR_STATUS_2 */ "", 25823 /* EGR_INTR_STATUS_64 */ "", 25824 /* EGR_INTR_STATUS_2_PIPE0 */ "", 25825 /* EGR_INTR_STATUS_2_PIPE1 */ "", 25826 /* EGR_INTR_STATUS_2_PIPE2 */ "", 25827 /* EGR_INTR_STATUS_2_PIPE3 */ "", 25828 /* EGR_INTR_STATUS_2_PIPE4 */ "", 25829 /* EGR_INTR_STATUS_2_PIPE5 */ "", 25830 /* EGR_INTR_STATUS_2_PIPE6 */ "", 25831 /* EGR_INTR_STATUS_2_PIPE7 */ "", 25832 /* EGR_INTR_STATUS_PIPE0 */ "", 25833 /* EGR_INTR_STATUS_PIPE1 */ "", 25834 /* EGR_INTR_STATUS_PIPE2 */ "", 25835 /* EGR_INTR_STATUS_PIPE3 */ "", 25836 /* EGR_INTR_STATUS_PIPE4 */ "", 25837 /* EGR_INTR_STATUS_PIPE5 */ "", 25838 /* EGR_INTR_STATUS_PIPE6 */ "", 25839 /* EGR_INTR_STATUS_PIPE7 */ "", 25840 /* EGR_INT_EGRESS_TIME_DELTA */ "", 25841 /* EGR_INT_LOOPBACK_MAX_FR */ "", 25842 /* EGR_INT_PORT_META_DATA */ "", 25843 /* EGR_INT_SWITCH_ID */ "", 25844 /* EGR_IN_BAND_CRC_CONTROL */ "", 25845 /* EGR_IN_BAND_CRC_COUNTER */ "", 25846 /* EGR_IPFIX_AGE_CONTROL */ "", 25847 /* EGR_IPFIX_CONFIG */ "", 25848 /* EGR_IPFIX_CURRENT_TIME */ "", 25849 /* EGR_IPFIX_DBG_CONTROL */ "", 25850 /* EGR_IPFIX_EOP_BUF_PARITY_CONTROL */ "", 25851 /* EGR_IPFIX_EOP_BUF_PARITY_STATUS_INTR */ "", 25852 /* EGR_IPFIX_EOP_BUF_PARITY_STATUS_NACK */ "", 25853 /* EGR_IPFIX_EXPORT_FIFO_COUNTER */ "", 25854 /* EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROL */ "", 25855 /* EGR_IPFIX_EXPORT_FIFO_PARITY_STATUS */ "", 25856 /* EGR_IPFIX_EXPORT_FIFO_PARITY_STATUS_NACK */ "", 25857 /* EGR_IPFIX_EXPORT_FIFO_READ_PTR */ "", 25858 /* EGR_IPFIX_EXPORT_FIFO_WRITE_PTR */ "", 25859 /* EGR_IPFIX_HASH_CONTROL */ "", 25860 /* EGR_IPFIX_MAXIMUM_IDLE_AGE_SET */ "", 25861 /* EGR_IPFIX_MAXIMUM_LIVE_TIME_SET */ "", 25862 /* EGR_IPFIX_MINIMUM_LIVE_TIME_SET */ "", 25863 /* EGR_IPFIX_MIRROR_CONTROL_64 */ "", 25864 /* EGR_IPFIX_MISSED_BUCKET_FULL_COUNT */ "", 25865 /* EGR_IPFIX_MISSED_EXPORT_FULL_COUNT */ "", 25866 /* EGR_IPFIX_MISSED_PORT_LIMIT_COUNT */ "", 25867 /* EGR_IPFIX_PDA_CONTROL */ "", 25868 /* EGR_IPFIX_PORT_CONFIG */ "", 25869 /* EGR_IPFIX_PORT_LIMIT_STATUS */ "", 25870 /* EGR_IPFIX_PORT_RECORD_COUNT */ "", 25871 /* EGR_IPFIX_PORT_RECORD_LIMIT_SET */ "", 25872 /* EGR_IPFIX_PORT_SAMPLING_COUNTER */ "", 25873 /* EGR_IPFIX_RAM_CONTROL */ "", 25874 /* EGR_IPFIX_SAMPLING_LIMIT_SET */ "", 25875 /* EGR_IPFIX_SER_CONTROL */ "", 25876 /* EGR_IPFIX_SESSION_PARITY_CONTROL */ "", 25877 /* EGR_IPFIX_SESSION_PARITY_STATUS */ "", 25878 /* EGR_IPFIX_SESSION_PARITY_STATUS_INTR_0 */ "", 25879 /* EGR_IPFIX_SESSION_PARITY_STATUS_INTR_1 */ "", 25880 /* EGR_IPFIX_SESSION_PARITY_STATUS_NACK_0 */ "", 25881 /* EGR_IPFIX_SESSION_PARITY_STATUS_NACK_1 */ "", 25882 /* EGR_IPMC_CFG2 */ "", 25883 /* EGR_IPMC_CFG2_PARITY_STATUS_INTR */ "", 25884 /* EGR_IPMC_CFG2_PARITY_STATUS_NACK */ "", 25885 /* EGR_IPMC_PARITY_STATUS_INTR */ "", 25886 /* EGR_IPMC_PARITY_STATUS_NACK */ "", 25887 /* EGR_IP_TUNNEL_PARITY_CONTROL */ "", 25888 /* EGR_IP_TUNNEL_PARITY_STATUS */ "", 25889 /* EGR_IP_TUNNEL_PARITY_STATUS_INTR */ "", 25890 /* EGR_IP_TUNNEL_PARITY_STATUS_NACK */ "", 25891 /* EGR_L1_CLK_RECOVERY_CTRL */ "", 25892 /* EGR_L2GRE_CONTROL */ "", 25893 /* EGR_L2_MTU */ "", 25894 /* EGR_L3_INTF_BANK_SEL */ "", 25895 /* EGR_L3_INTF_PARITY_CONTROL */ "", 25896 /* EGR_L3_INTF_PARITY_STATUS */ "", 25897 /* EGR_L3_INTF_PARITY_STATUS_INTR */ "", 25898 /* EGR_L3_INTF_PARITY_STATUS_NACK */ "", 25899 /* EGR_L3_NEXT_HOP_BANK_SEL */ "", 25900 /* EGR_L3_NEXT_HOP_PARITY_CONTROL */ "", 25901 /* EGR_L3_NEXT_HOP_PARITY_STATUS */ "", 25902 /* EGR_L3_NEXT_HOP_PARITY_STATUS_INTR */ "", 25903 /* EGR_L3_NEXT_HOP_PARITY_STATUS_NACK */ "", 25904 /* EGR_L3_NEXT_HOP_PDA_CTRL0 */ "", 25905 /* EGR_L3_NEXT_HOP_PDA_CTRL1 */ "", 25906 /* EGR_L3_NEXT_HOP_PDA_CTRL2 */ "", 25907 /* EGR_L3_NEXT_HOP_PDA_CTRL3 */ "", 25908 /* EGR_L3_TUNNEL_PFM_VID */ "", 25909 /* EGR_LATENCY_MODE */ "", 25910 /* EGR_LBP_BUFFER_STATUS_INTR */ "", 25911 /* EGR_LBR_OPCODE */ "", 25912 /* EGR_LLTAG_TPID */ "", 25913 /* EGR_LLTAG_TPID_2 */ "", 25914 /* EGR_LMFC_EOP_BUFFER_0_PARITY_CONTROL */ "", 25915 /* EGR_LMFC_EOP_BUFFER_1_PARITY_CONTROL */ "", 25916 /* EGR_LMFC_EOP_BUFFER_2_PARITY_CONTROL */ "", 25917 /* EGR_LM_RAM_CONTROL_1 */ "", 25918 /* EGR_LM_RAM_CONTROL_0_64 */ "", 25919 /* EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPING */ "", 25920 /* EGR_LOOPBACK_PORT_TPID */ "", 25921 /* EGR_LPORT_PROFILE_SELECT */ "", 25922 /* EGR_LP_BUFFER_STATUS_INTR */ "", 25923 /* EGR_LP_DBUF_PARITY_CONTROL */ "", 25924 /* EGR_LP_DBUF_PARITY_STATUS */ "", 25925 /* EGR_MAC_DA_PROFILE_PARITY_STATUS_INTR */ "", 25926 /* EGR_MAC_DA_PROFILE_PARITY_STATUS_NACK */ "", 25927 /* EGR_MAP_MH_PARITY_STATUS_INTR */ "", 25928 /* EGR_MAP_MH_PARITY_STATUS_NACK */ "", 25929 /* EGR_MAP_MH_PRI0 */ "", 25930 /* EGR_MAP_MH_PRI1 */ "", 25931 /* EGR_MASK_ECC_CONTROL */ "", 25932 /* EGR_MASK_ECC_STATUS */ "", 25933 /* EGR_MASK_MODBASE_PARITY_CONTROL */ "EGR_MASK_MODBASE_PARITY_CONTROL", 25934 /* EGR_MASK_MODBASE_PARITY_STATUS */ "", 25935 /* EGR_MASK_MODBASE_PARITY_STATUS_INTR */ "EGR_MASK_MODBASE_PARITY_STATUS_INTR", 25936 /* EGR_MASK_MODBASE_PARITY_STATUS_NACK */ "EGR_MASK_MODBASE_PARITY_STATUS_NACK", 25937 /* EGR_MASK_PARITY_CONTROL */ "", 25938 /* EGR_MASK_PARITY_STATUS */ "", 25939 /* EGR_MASK_PARITY_STATUS_INTR */ "", 25940 /* EGR_MASK_PARITY_STATUS_NACK */ "", 25941 /* EGR_MA_INDEX_ECC_CONTROL */ "", 25942 /* EGR_MA_INDEX_PARITY_STATUS_INTR */ "", 25943 /* EGR_MA_INDEX_PARITY_STATUS_NACK */ "", 25944 /* EGR_MCPE_CONTROL */ "", 25945 /* EGR_MC_CONTROL_1 */ "", 25946 /* EGR_MC_CONTROL_2 */ "", 25947 /* EGR_MEM_ECC_ERR_COUNTER */ "", 25948 /* EGR_MFRAME_COUNTER_PARITY_STATUS */ "", 25949 /* EGR_MIML_ETHERTYPE */ "", 25950 /* EGR_MIM_ETHERTYPE */ "", 25951 /* EGR_MIRROR_ENCAP_DATA_1_PARITY_STATUS */ "", 25952 /* EGR_MIRROR_ENCAP_PSAMP */ "", 25953 /* EGR_MIRROR_PSAMP_FORMAT_2_MONITOR */ "", 25954 /* EGR_MIRROR_SELECT */ "", 25955 /* EGR_MIRROR_ZERO_PAYLOAD_OFFSET_CFG_0 */ "", 25956 /* EGR_MIRROR_ZERO_PAYLOAD_OFFSET_CFG_1 */ "", 25957 /* EGR_MIRROR_ZERO_PAYLOAD_OFFSET_CFG_2 */ "", 25958 /* EGR_MIRROR_ZERO_PAYLOAD_OFFSET_CFG_3 */ "", 25959 /* EGR_MIRROR_ZERO_PAYLOAD_PARSE_CFG_0 */ "", 25960 /* EGR_MIRROR_ZERO_PAYLOAD_PARSE_CFG_1 */ "", 25961 /* EGR_MIRROR_ZERO_PAYLOAD_PARSE_CFG_2 */ "", 25962 /* EGR_MISC_INTR_STATUS */ "", 25963 /* EGR_MISC_XMIT_START_COUNT */ "", 25964 /* EGR_MISC_XMIT_START_COUNT_PIPE0 */ "", 25965 /* EGR_MISC_XMIT_START_COUNT_PIPE1 */ "", 25966 /* EGR_MISC_XMIT_START_COUNT_PIPE2 */ "", 25967 /* EGR_MISC_XMIT_START_COUNT_PIPE3 */ "", 25968 /* EGR_MMU_CELL_CREDIT */ "", 25969 /* EGR_MMU_REQUESTS */ "", 25970 /* EGR_MODMAP_CTRL */ "", 25971 /* EGR_MOD_MAP_PARITY_CONTROL */ "", 25972 /* EGR_MOD_MAP_PARITY_STATUS */ "", 25973 /* EGR_MOD_MAP_PARITY_STATUS_INTR */ "", 25974 /* EGR_MOD_MAP_PARITY_STATUS_NACK */ "", 25975 /* EGR_MPB_ECC_STATUS_INTR */ "", 25976 /* EGR_MPLS_ENTROPY_LABEL_CONTROL */ "", 25977 /* EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_INTR */ "", 25978 /* EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_NACK */ "", 25979 /* EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_INTR */ "", 25980 /* EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_NACK */ "", 25981 /* EGR_MPLS_PRI_MAPPING_PARITY_STATUS_INTR */ "", 25982 /* EGR_MPLS_PRI_MAPPING_PARITY_STATUS_NACK */ "", 25983 /* EGR_MPLS_SPECIAL_LABEL_CONTROL */ "", 25984 /* EGR_MPLS_VC_AND_SWAP_LABEL_PARITY_CONTROL */ "", 25985 /* EGR_MPLS_VC_AND_SWAP_LABEL_PARITY_STATUS */ "", 25986 /* EGR_MPLS_VC_AND_SWAP_LABEL_PARITY_STATUS_INTR */ "", 25987 /* EGR_MPLS_VC_AND_SWAP_LABEL_PARITY_STATUS_NACK */ "", 25988 /* EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_STATUS_INTR */ "", 25989 /* EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_STATUS_NACK */ "", 25990 /* EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PDA_CTRL */ "", 25991 /* EGR_MP_GROUP_ECC_CONTROL */ "", 25992 /* EGR_MP_GROUP_HASH_CONTROL */ "", 25993 /* EGR_MP_GROUP_PARITY_STATUS_INTR_0 */ "", 25994 /* EGR_MP_GROUP_PARITY_STATUS_INTR_1 */ "", 25995 /* EGR_MP_GROUP_PARITY_STATUS_NACK_0 */ "", 25996 /* EGR_MP_GROUP_PARITY_STATUS_NACK_1 */ "", 25997 /* EGR_MTU */ "", 25998 /* EGR_MTU_CHECK_PARITY_CONTROL */ "", 25999 /* EGR_MTU_CHECK_PARITY_STATUS */ "", 26000 /* EGR_MTU_SIZE */ "", 26001 /* EGR_MULTICAST_MAC_ADDR_MASK */ "", 26002 /* EGR_MY_MODID_SET_64 */ "", 26003 /* EGR_NEXT_HOP_PARITY_CONTROL */ "", 26004 /* EGR_NEXT_HOP_PARITY_STATUS */ "", 26005 /* EGR_NIV_CONFIG */ "", 26006 /* EGR_NIV_ETHERTYPE */ "", 26007 /* EGR_NIV_ETHERTYPE_2 */ "", 26008 /* EGR_OAMP_CONTROL */ "", 26009 /* EGR_OAM_CONTROL */ "", 26010 /* EGR_OAM_COPYTO_CPU_CONTROL */ "", 26011 /* EGR_OAM_C_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_C_INTERFACE_DROP_CONTROL", 26012 /* EGR_OAM_DVP_INTERFACE_DROP_CONTROL_64 */ "", 26013 /* EGR_OAM_ERROR_CONTROL */ "", 26014 /* EGR_OAM_FLEXIBLE_DOMAIN_CONTROL_PARITY_CONTROL */ "", 26015 /* EGR_OAM_INTF_PROC_SELECT_CONTROL_64 */ "EGR_OAM_INTF_PROC_SELECT_CONTROL", 26016 /* EGR_OAM_KEY_SELECT_CONTROL_64 */ "EGR_OAM_KEY_SELECT_CONTROL", 26017 /* EGR_OAM_LM_CNG_CONTROL */ "EGR_OAM_LM_CNG_CONTROL", 26018 /* EGR_OAM_LM_COUNTERS_0_ECC_CONTROL */ "", 26019 /* EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTR */ "", 26020 /* EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_NACK */ "", 26021 /* EGR_OAM_LM_COUNTERS_1_ECC_CONTROL */ "", 26022 /* EGR_OAM_LM_COUNTERS_1_PARITY_STATUS_INTR */ "", 26023 /* EGR_OAM_LM_COUNTERS_1_PARITY_STATUS_NACK */ "", 26024 /* EGR_OAM_LM_COUNTERS_2_ECC_CONTROL */ "", 26025 /* EGR_OAM_LPR_TM_CONTROL_0_64 */ "EGR_OAM_LPR_TM_CONTROL_0", 26026 /* EGR_OAM_LSP_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_LSP_INTERFACE_DROP_CONTROL", 26027 /* EGR_OAM_OPCODE_CONTROL_PROFILE_PARITY_CONTROL */ "", 26028 /* EGR_OAM_OPCODE_GROUP_PARITY_CONTROL */ "", 26029 /* EGR_OAM_PORT_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_PORT_INTERFACE_DROP_CONTROL", 26030 /* EGR_OAM_PW_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_PW_INTERFACE_DROP_CONTROL", 26031 /* EGR_OAM_RX_MODE_FOR_CPU */ "", 26032 /* EGR_OAM_SAT_MISC_ETHERTYPE_0 */ "", 26033 /* EGR_OAM_SAT_MISC_ETHERTYPE_1 */ "", 26034 /* EGR_OAM_SAT_MISC_ETHERTYPE_2 */ "", 26035 /* EGR_OAM_SAT_MISC_ETHERTYPE_3 */ "", 26036 /* EGR_OAM_SAT_MISC_MAC_SA */ "", 26037 /* EGR_OAM_SECTION_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_SECTION_INTERFACE_DROP_CONTROL", 26038 /* EGR_OAM_S_C_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_S_C_INTERFACE_DROP_CONTROL", 26039 /* EGR_OAM_S_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_S_INTERFACE_DROP_CONTROL", 26040 /* EGR_OAM_S_INTERFACE_PASSIVE_PROCESSING_CONTROL */ "EGR_OAM_S_INTERFACE_PASSIVE_PROCESSING_CONTROL", 26041 /* EGR_OAM_VP_INTERFACE_DROP_CONTROL_64 */ "EGR_OAM_VP_INTERFACE_DROP_CONTROL", 26042 /* EGR_OLP_SGPP_CONFIG */ "", 26043 /* EGR_OLP_VLAN */ "", 26044 /* EGR_OLP_VLAN_1 */ "", 26045 /* EGR_OUTER_TPID */ "", 26046 /* EGR_OUTER_TPID_0 */ "", 26047 /* EGR_OUTER_TPID_1 */ "", 26048 /* EGR_OUTER_TPID_2 */ "", 26049 /* EGR_OUTER_TPID_3 */ "", 26050 /* EGR_PARSER_INNER_TPID */ "", 26051 /* EGR_PARSER_INNER_TPID_0 */ "", 26052 /* EGR_PARSER_INNER_TPID_1 */ "", 26053 /* EGR_PARSER_INNER_TPID_2 */ "", 26054 /* EGR_PARSER_INNER_TPID_3 */ "", 26055 /* EGR_PARSER_OUTER_TPID */ "", 26056 /* EGR_PARSER_OUTER_TPID_0 */ "", 26057 /* EGR_PARSER_OUTER_TPID_1 */ "", 26058 /* EGR_PARSER_OUTER_TPID_2 */ "", 26059 /* EGR_PARSER_OUTER_TPID_3 */ "", 26060 /* EGR_PCP_DE_MAPPING_PARITY_STATUS_INTR */ "", 26061 /* EGR_PCP_DE_MAPPING_PARITY_STATUS_NACK */ "", 26062 /* EGR_PERQ_CNTR_UPDATE_CONTROL */ "", 26063 /* EGR_PERQ_CNTR_UPDATE_CONTROL_PIPE0 */ "", 26064 /* EGR_PERQ_CNTR_UPDATE_CONTROL_PIPE1 */ "", 26065 /* EGR_PERQ_CNTR_UPDATE_CONTROL_PIPE2 */ "", 26066 /* EGR_PERQ_CNTR_UPDATE_CONTROL_PIPE3 */ "", 26067 /* EGR_PERQ_COUNTER_PARITY_CONTROL */ "", 26068 /* EGR_PERQ_COUNTER_PARITY_STATUS */ "", 26069 /* EGR_PERQ_EVICTION_CONTROL */ "", 26070 /* EGR_PERQ_EVICTION_CONTROL_PIPE0 */ "", 26071 /* EGR_PERQ_EVICTION_CONTROL_PIPE1 */ "", 26072 /* EGR_PERQ_EVICTION_CONTROL_PIPE2 */ "", 26073 /* EGR_PERQ_EVICTION_CONTROL_PIPE3 */ "", 26074 /* EGR_PERQ_EVICTION_CONTROL_PIPE4 */ "", 26075 /* EGR_PERQ_EVICTION_CONTROL_PIPE5 */ "", 26076 /* EGR_PERQ_EVICTION_CONTROL_PIPE6 */ "", 26077 /* EGR_PERQ_EVICTION_CONTROL_PIPE7 */ "", 26078 /* EGR_PERQ_EVICTION_FAIL */ "", 26079 /* EGR_PERQ_EVICTION_FAIL_PIPE0 */ "", 26080 /* EGR_PERQ_EVICTION_FAIL_PIPE1 */ "", 26081 /* EGR_PERQ_EVICTION_FAIL_PIPE2 */ "", 26082 /* EGR_PERQ_EVICTION_FAIL_PIPE3 */ "", 26083 /* EGR_PERQ_EVICTION_FAIL_PIPE4 */ "", 26084 /* EGR_PERQ_EVICTION_FAIL_PIPE5 */ "", 26085 /* EGR_PERQ_EVICTION_FAIL_PIPE6 */ "", 26086 /* EGR_PERQ_EVICTION_FAIL_PIPE7 */ "", 26087 /* EGR_PERQ_EVICTION_SEED */ "", 26088 /* EGR_PERQ_EVICTION_SEED_PIPE0 */ "", 26089 /* EGR_PERQ_EVICTION_SEED_PIPE1 */ "", 26090 /* EGR_PERQ_EVICTION_SEED_PIPE2 */ "", 26091 /* EGR_PERQ_EVICTION_SEED_PIPE3 */ "", 26092 /* EGR_PERQ_EVICTION_SEED_PIPE4 */ "", 26093 /* EGR_PERQ_EVICTION_SEED_PIPE5 */ "", 26094 /* EGR_PERQ_EVICTION_SEED_PIPE6 */ "", 26095 /* EGR_PERQ_EVICTION_SEED_PIPE7 */ "", 26096 /* EGR_PERQ_EVICTION_THRESHOLD */ "", 26097 /* EGR_PERQ_EVICTION_THRESHOLD_PIPE0 */ "", 26098 /* EGR_PERQ_EVICTION_THRESHOLD_PIPE1 */ "", 26099 /* EGR_PERQ_EVICTION_THRESHOLD_PIPE2 */ "", 26100 /* EGR_PERQ_EVICTION_THRESHOLD_PIPE3 */ "", 26101 /* EGR_PERQ_XMT_COUNTERS */ "", 26102 /* EGR_PERQ_XMT_COUNTERS_BASE_ADDR_PARITY_STATUS_INTR */ "", 26103 /* EGR_PERQ_XMT_COUNTERS_BASE_ADDR_PARITY_STATUS_NACK */ "", 26104 /* EGR_PERQ_XMT_COUNTERS_PARITY_STATUS */ "", 26105 /* EGR_PERQ_XMT_COUNTERS_PARITY_STATUS_INTR */ "", 26106 /* EGR_PERQ_XMT_COUNTERS_PARITY_STATUS_NACK */ "", 26107 /* EGR_PERQ_XMT_COUNTERS_STATUS_INTR */ "", 26108 /* EGR_PERQ_XMT_COUNTERS_STATUS_NACK */ "", 26109 /* EGR_PERQ_XMT_COUNTER_ECC_STATUS */ "", 26110 /* EGR_PER_Q_ECN_MARKED_PARITY_CONTROL */ "", 26111 /* EGR_PER_Q_ECN_MARKED_PARITY_STATUS */ "", 26112 /* EGR_PE_ETHERTYPE */ "", 26113 /* EGR_PE_ETHERTYPE_2 */ "", 26114 /* EGR_PKT_FLOW_SELECT_CAM_BIST_CONFIG_64 */ "", 26115 /* EGR_PKT_FLOW_SELECT_CAM_BIST_STATUS */ "", 26116 /* EGR_PKT_FLOW_SELECT_CAM_BIST_STATUS_PIPE0 */ "", 26117 /* EGR_PKT_FLOW_SELECT_CAM_BIST_STATUS_PIPE1 */ "", 26118 /* EGR_PKT_MODS_CONTROL */ "", 26119 /* EGR_PKT_MODS_CONTROL_2 */ "", 26120 /* EGR_PORT */ "", 26121 /* EGR_PORT_1 */ "", 26122 /* EGR_PORT_64 */ "EGR_PORT", 26123 /* EGR_PORT_BUFFER_CLK_SHUTDOWN */ "", 26124 /* EGR_PORT_BUFFER_CLK_SHUTDOWN_PIPE0 */ "", 26125 /* EGR_PORT_BUFFER_CLK_SHUTDOWN_PIPE1 */ "", 26126 /* EGR_PORT_BUFFER_CLK_SHUTDOWN_PIPE2 */ "", 26127 /* EGR_PORT_BUFFER_CLK_SHUTDOWN_PIPE3 */ "", 26128 /* EGR_PORT_BUFFER_SFT_RESET */ "", 26129 /* EGR_PORT_BUFFER_SFT_RESET_0 */ "", 26130 /* EGR_PORT_BUFFER_SFT_RESET_0_PIPE0 */ "", 26131 /* EGR_PORT_BUFFER_SFT_RESET_0_PIPE1 */ "", 26132 /* EGR_PORT_BUFFER_SFT_RESET_0_PIPE2 */ "", 26133 /* EGR_PORT_BUFFER_SFT_RESET_0_PIPE3 */ "", 26134 /* EGR_PORT_L3UC_MODS */ "", 26135 /* EGR_PORT_MIN_PKT_SIZE */ "", 26136 /* EGR_PORT_MODE */ "", 26137 /* EGR_PORT_PARITY_STATUS_INTR */ "", 26138 /* EGR_PORT_PARITY_STATUS_NACK */ "", 26139 /* EGR_PORT_PKT_CTRL */ "", 26140 /* EGR_PORT_REQUESTS */ "", 26141 /* EGR_PORT_TO_NHI_MAPPING */ "", 26142 /* EGR_PRI_CNG_MAP_PARITY_STATUS_INTR */ "", 26143 /* EGR_PRI_CNG_MAP_PARITY_STATUS_NACK */ "", 26144 /* EGR_PVLAN_EPORT_CONTROL */ "", 26145 /* EGR_PW_INIT_COUNTERS_PARITY_CONTROL */ "", 26146 /* EGR_PW_INIT_COUNTERS_PARITY_STATUS */ "", 26147 /* EGR_PW_INIT_COUNTERS_PARITY_STATUS_INTR */ "", 26148 /* EGR_PW_INIT_COUNTERS_PARITY_STATUS_NACK */ "", 26149 /* EGR_QCN_CNM_CONTROL_1 */ "", 26150 /* EGR_QCN_CNM_CONTROL_2 */ "", 26151 /* EGR_QCN_CNM_ETHERTYPE */ "", 26152 /* EGR_QCN_CNM_LBMH_CONTROL */ "", 26153 /* EGR_QCN_CNTAG_ETHERTYPE */ "", 26154 /* EGR_QCN_CNTAG_ETHERTYPE_2 */ "", 26155 /* EGR_QOS_CTRL_CAM_BIST_CONFIG_64 */ "", 26156 /* EGR_QOS_CTRL_CAM_BIST_STATUS */ "", 26157 /* EGR_QOS_CTRL_CAM_BIST_STATUS_PIPE0 */ "", 26158 /* EGR_QOS_CTRL_CAM_BIST_STATUS_PIPE1 */ "", 26159 /* EGR_QUEUE_TO_PP_PORT_MAP_PARITY_STATUS_INTR */ "", 26160 /* EGR_QUEUE_TO_PP_PORT_MAP_PARITY_STATUS_NACK */ "", 26161 /* EGR_Q_BEGIN */ "", 26162 /* EGR_Q_CORE_BEGIN */ "", 26163 /* EGR_Q_END */ "", 26164 /* EGR_Q_END_PIPE0 */ "", 26165 /* EGR_Q_END_PIPE1 */ "", 26166 /* EGR_Q_END_PIPE2 */ "", 26167 /* EGR_Q_END_PIPE3 */ "", 26168 /* EGR_Q_END_PIPE4 */ "", 26169 /* EGR_Q_END_PIPE5 */ "", 26170 /* EGR_Q_END_PIPE6 */ "", 26171 /* EGR_Q_END_PIPE7 */ "", 26172 /* EGR_RDB_DROP_VECTOR_MASK */ "", 26173 /* EGR_REPLACEMENT_TTL */ "", 26174 /* EGR_RESI0_PARITY_STATUS */ "", 26175 /* EGR_RESI23_PARITY_STATUS */ "", 26176 /* EGR_RESI_BUFFER_STATUS_INTR */ "", 26177 /* EGR_RESI_DBITS_PARITY_STATUS */ "", 26178 /* EGR_RESI_PARITY_STATUS */ "", 26179 /* EGR_ROE_ETHERTYPE */ "", 26180 /* EGR_RSPAN_VLAN_TAG */ "", 26181 /* EGR_SAT_SAMP_DATA_PARITY_CONTROL */ "", 26182 /* EGR_SAT_SAMP_TCAM_BIST_CONFIG */ "", 26183 /* EGR_SAT_SAMP_TCAM_BIST_DBG_DATA */ "", 26184 /* EGR_SAT_SAMP_TCAM_BIST_STATUS */ "", 26185 /* EGR_SAT_SAMP_TCAM_DBGCTRL */ "EGR_SAT_SAMP_TCAM_CONTROL", 26186 /* EGR_SAT_SAMP_TM_CONTROL */ "", 26187 /* EGR_SBS_CONTROL */ "", 26188 /* EGR_SD_TAG_CONTROL */ "", 26189 /* EGR_SECTAG_ETHERTYPE */ "", 26190 /* EGR_SEQUENCE_NUMBER_CTRL */ "", 26191 /* EGR_SERVICE_COUNTER_TABLE_PARITY_STATUS_INTR */ "", 26192 /* EGR_SERVICE_COUNTER_TABLE_PARITY_STATUS_NACK */ "", 26193 /* EGR_SERVICE_COUNTER_TABLE_STATUS_INTR */ "", 26194 /* EGR_SERVICE_COUNTER_TABLE_STATUS_NACK */ "", 26195 /* EGR_SERVICE_PRI_MAP_0_PARITY_CONTROL */ "", 26196 /* EGR_SERVICE_PRI_MAP_1_PARITY_CONTROL */ "", 26197 /* EGR_SERVICE_PRI_MAP_2_PARITY_CONTROL */ "", 26198 /* EGR_SER_FIFO_CTRL */ "", 26199 /* EGR_SER_FIFO_CTRL_2 */ "", 26200 /* EGR_SER_FIFO_CTRL_2_PIPE0 */ "", 26201 /* EGR_SER_FIFO_CTRL_2_PIPE1 */ "", 26202 /* EGR_SER_FIFO_CTRL_2_PIPE2 */ "", 26203 /* EGR_SER_FIFO_CTRL_2_PIPE3 */ "", 26204 /* EGR_SER_FIFO_CTRL_2_PIPE4 */ "", 26205 /* EGR_SER_FIFO_CTRL_2_PIPE5 */ "", 26206 /* EGR_SER_FIFO_CTRL_2_PIPE6 */ "", 26207 /* EGR_SER_FIFO_CTRL_2_PIPE7 */ "", 26208 /* EGR_SER_FIFO_CTRL_PIPE0 */ "", 26209 /* EGR_SER_FIFO_CTRL_PIPE1 */ "", 26210 /* EGR_SER_FIFO_CTRL_PIPE2 */ "", 26211 /* EGR_SER_FIFO_CTRL_PIPE3 */ "", 26212 /* EGR_SER_FIFO_CTRL_PIPE4 */ "", 26213 /* EGR_SER_FIFO_CTRL_PIPE5 */ "", 26214 /* EGR_SER_FIFO_CTRL_PIPE6 */ "", 26215 /* EGR_SER_FIFO_CTRL_PIPE7 */ "", 26216 /* EGR_SER_FIFO_STATUS */ "", 26217 /* EGR_SER_FIFO_STATUS_2 */ "", 26218 /* EGR_SER_FIFO_STATUS_2_PIPE0 */ "", 26219 /* EGR_SER_FIFO_STATUS_2_PIPE1 */ "", 26220 /* EGR_SER_FIFO_STATUS_2_PIPE2 */ "", 26221 /* EGR_SER_FIFO_STATUS_2_PIPE3 */ "", 26222 /* EGR_SER_FIFO_STATUS_2_PIPE4 */ "", 26223 /* EGR_SER_FIFO_STATUS_2_PIPE5 */ "", 26224 /* EGR_SER_FIFO_STATUS_2_PIPE6 */ "", 26225 /* EGR_SER_FIFO_STATUS_2_PIPE7 */ "", 26226 /* EGR_SER_FIFO_STATUS_PIPE0 */ "", 26227 /* EGR_SER_FIFO_STATUS_PIPE1 */ "", 26228 /* EGR_SER_FIFO_STATUS_PIPE2 */ "", 26229 /* EGR_SER_FIFO_STATUS_PIPE3 */ "", 26230 /* EGR_SER_FIFO_STATUS_PIPE4 */ "", 26231 /* EGR_SER_FIFO_STATUS_PIPE5 */ "", 26232 /* EGR_SER_FIFO_STATUS_PIPE6 */ "", 26233 /* EGR_SER_FIFO_STATUS_PIPE7 */ "", 26234 /* EGR_SET_DOT1P_PRESERVE */ "", 26235 /* EGR_SET_DSCP_PRESERVE */ "", 26236 /* EGR_SFLOW_CPU_COS_CONFIG */ "", 26237 /* EGR_SF_SRC_MODID_CHECK */ "", 26238 /* EGR_SF_SRC_MODID_CHECK_PARITY_STATUS_INTR */ "", 26239 /* EGR_SF_SRC_MODID_CHECK_PARITY_STATUS_NACK */ "", 26240 /* EGR_SHAPING_CONTROL */ "", 26241 /* EGR_SOURCE_PORT_IDENTITY_MASK */ "", 26242 /* EGR_SPECIAL_DROP_CTRL */ "", 26243 /* EGR_SPECIAL_DROP_CTRL_2 */ "", 26244 /* EGR_SPECIAL_DROP_CTRL_2_PIPE0 */ "", 26245 /* EGR_SPECIAL_DROP_CTRL_2_PIPE1 */ "", 26246 /* EGR_SPECIAL_DROP_CTRL_2_PIPE2 */ "", 26247 /* EGR_SPECIAL_DROP_CTRL_2_PIPE3 */ "", 26248 /* EGR_SPECIAL_DROP_CTRL_PIPE0 */ "", 26249 /* EGR_SPECIAL_DROP_CTRL_PIPE1 */ "", 26250 /* EGR_SPECIAL_DROP_CTRL_PIPE2 */ "", 26251 /* EGR_SPECIAL_DROP_CTRL_PIPE3 */ "", 26252 /* EGR_SPECIAL_DROP_DEBUG */ "", 26253 /* EGR_SPECIAL_DROP_DEBUG_PIPE0 */ "", 26254 /* EGR_SPECIAL_DROP_DEBUG_PIPE1 */ "", 26255 /* EGR_SRC_PORT */ "", 26256 /* EGR_SR_FLOW_COUNT_POOL0_PARITY_STATUS */ "", 26257 /* EGR_SR_FLOW_COUNT_POOL1_PARITY_STATUS */ "", 26258 /* EGR_START_XMIT_AFTER_MOP_ARRIVAL */ "", 26259 /* EGR_STATS_COUNTER_ECC_STATUS */ "", 26260 /* EGR_STATS_COUNTER_TABLE_PARITY_STATUS */ "", 26261 /* EGR_STATS_COUNTER_TABLE_PARITY_STATUS_INTR */ "", 26262 /* EGR_STATS_COUNTER_TABLE_PARITY_STATUS_NACK */ "", 26263 /* EGR_STATS_COUNTER_TABLE_STATUS_INTR */ "", 26264 /* EGR_STATS_COUNTER_TABLE_STATUS_NACK */ "", 26265 /* EGR_STU_CHECK_PARITY_CONTROL */ "", 26266 /* EGR_STU_CHECK_PARITY_STATUS */ "", 26267 /* EGR_SUBPORT_TAG_TPID */ "", 26268 /* EGR_SYS_RSVD_OBJECTS */ "", 26269 /* EGR_SYS_RSVD_VID */ "", 26270 /* EGR_TDM_ERR */ "", 26271 /* EGR_TDM_ERR_0 */ "", 26272 /* EGR_TDM_ERR_1 */ "", 26273 /* EGR_TDM_ERR_PIPE0 */ "", 26274 /* EGR_TDM_ERR_PIPE1 */ "", 26275 /* EGR_TDM_ERR_PIPE2 */ "", 26276 /* EGR_TDM_ERR_PIPE3 */ "", 26277 /* EGR_TRILL_HEADER_ATTRIBUTES */ "", 26278 /* EGR_TRILL_TX_ACCESS_PORT_TRILL_PKTS_DISCARDED */ "", 26279 /* EGR_TRILL_TX_ACCESS_PORT_TRILL_PKTS_DISCARDED_64 */ "EGR_TRILL_TX_ACCESS_PORT_TRILL_PKTS_DISCARDED", 26280 /* EGR_TRILL_TX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED */ "", 26281 /* EGR_TRILL_TX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_64 */ "EGR_TRILL_TX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED", 26282 /* EGR_TRILL_TX_PKTS */ "", 26283 /* EGR_TRILL_TX_PKTS_64 */ "EGR_TRILL_TX_PKTS", 26284 /* EGR_TS_CONTROL */ "", 26285 /* EGR_TS_CONTROL_2 */ "", 26286 /* EGR_TS_ING_PORT_MAP */ "", 26287 /* EGR_TUNNEL_CONTROL */ "", 26288 /* EGR_TUNNEL_ID_MASK */ "", 26289 /* EGR_TUNNEL_PIMDR1_CFG0 */ "", 26290 /* EGR_TUNNEL_PIMDR1_CFG1 */ "", 26291 /* EGR_TUNNEL_PIMDR2_CFG0 */ "", 26292 /* EGR_TUNNEL_PIMDR2_CFG1 */ "", 26293 /* EGR_VFI_ACTION_MASK_PROFILE */ "", 26294 /* EGR_VFI_PARITY_STATUS_INTR */ "", 26295 /* EGR_VFI_PARITY_STATUS_NACK */ "", 26296 /* EGR_VINTF_COUNTER_TABLE_PARITY_STATUS_INTR */ "", 26297 /* EGR_VINTF_COUNTER_TABLE_PARITY_STATUS_NACK */ "", 26298 /* EGR_VINTF_COUNTER_TABLE_STATUS_INTR */ "", 26299 /* EGR_VINTF_COUNTER_TABLE_STATUS_NACK */ "", 26300 /* EGR_VLAN_ACTION_MASK_PROFILE */ "", 26301 /* EGR_VLAN_CONTROL_1 */ "", 26302 /* EGR_VLAN_CONTROL_2 */ "", 26303 /* EGR_VLAN_CONTROL_3 */ "", 26304 /* EGR_VLAN_CONTROL_1_PARITY_STATUS_INTR */ "", 26305 /* EGR_VLAN_CONTROL_1_PARITY_STATUS_NACK */ "", 26306 /* EGR_VLAN_COUNTER_TABLE_PARITY_STATUS */ "", 26307 /* EGR_VLAN_ECC_PARITY_CONTROL */ "", 26308 /* EGR_VLAN_LOGICAL_TO_PHYSICAL_MAPPING */ "", 26309 /* EGR_VLAN_PARITY_CONTROL */ "", 26310 /* EGR_VLAN_PARITY_STATUS */ "", 26311 /* EGR_VLAN_PARITY_STATUS_INTR */ "", 26312 /* EGR_VLAN_PARITY_STATUS_NACK */ "", 26313 /* EGR_VLAN_PDA_CTRL */ "", 26314 /* EGR_VLAN_RAM_CONTROL_0 */ "", 26315 /* EGR_VLAN_RAM_CONTROL_1 */ "", 26316 /* EGR_VLAN_RAM_CONTROL_2 */ "", 26317 /* EGR_VLAN_RAM_CONTROL_3 */ "", 26318 /* EGR_VLAN_RAM_CONTROL_4 */ "", 26319 /* EGR_VLAN_RAM_CONTROL_5 */ "", 26320 /* EGR_VLAN_RAM_CONTROL_6 */ "", 26321 /* EGR_VLAN_RAM_CONTROL_7 */ "", 26322 /* EGR_VLAN_RAM_CONTROL_8 */ "", 26323 /* EGR_VLAN_RAM_CONTROL_9 */ "", 26324 /* EGR_VLAN_RAM_CONTROL_1_64 */ "EGR_VLAN_RAM_CONTROL_1", 26325 /* EGR_VLAN_RAM_CONTROL_1_64_PIPE0 */ "EGR_VLAN_RAM_CONTROL_1_PIPE0", 26326 /* EGR_VLAN_RAM_CONTROL_1_64_PIPE1 */ "EGR_VLAN_RAM_CONTROL_1_PIPE1", 26327 /* EGR_VLAN_RAM_CONTROL_1_64_PIPE2 */ "EGR_VLAN_RAM_CONTROL_1_PIPE2", 26328 /* EGR_VLAN_RAM_CONTROL_1_64_PIPE3 */ "EGR_VLAN_RAM_CONTROL_1_PIPE3", 26329 /* EGR_VLAN_RAM_CONTROL_1_PIPE0 */ "", 26330 /* EGR_VLAN_RAM_CONTROL_1_PIPE1 */ "", 26331 /* EGR_VLAN_RAM_CONTROL_1_PIPE2 */ "", 26332 /* EGR_VLAN_RAM_CONTROL_1_PIPE3 */ "", 26333 /* EGR_VLAN_RAM_CONTROL_2_64 */ "EGR_VLAN_RAM_CONTROL_2", 26334 /* EGR_VLAN_RAM_CONTROL_2_64_PIPE0 */ "EGR_VLAN_RAM_CONTROL_2_PIPE0", 26335 /* EGR_VLAN_RAM_CONTROL_2_64_PIPE1 */ "EGR_VLAN_RAM_CONTROL_2_PIPE1", 26336 /* EGR_VLAN_RAM_CONTROL_2_64_PIPE2 */ "EGR_VLAN_RAM_CONTROL_2_PIPE2", 26337 /* EGR_VLAN_RAM_CONTROL_2_64_PIPE3 */ "EGR_VLAN_RAM_CONTROL_2_PIPE3", 26338 /* EGR_VLAN_RAM_CONTROL_2_PIPE0 */ "", 26339 /* EGR_VLAN_RAM_CONTROL_2_PIPE1 */ "", 26340 /* EGR_VLAN_RAM_CONTROL_2_PIPE2 */ "", 26341 /* EGR_VLAN_RAM_CONTROL_2_PIPE3 */ "", 26342 /* EGR_VLAN_RAM_CONTROL_3_64 */ "EGR_VLAN_RAM_CONTROL_3", 26343 /* EGR_VLAN_RAM_CONTROL_3_64_PIPE0 */ "EGR_VLAN_RAM_CONTROL_3_PIPE0", 26344 /* EGR_VLAN_RAM_CONTROL_3_64_PIPE1 */ "EGR_VLAN_RAM_CONTROL_3_PIPE1", 26345 /* EGR_VLAN_RAM_CONTROL_3_64_PIPE2 */ "EGR_VLAN_RAM_CONTROL_3_PIPE2", 26346 /* EGR_VLAN_RAM_CONTROL_3_64_PIPE3 */ "EGR_VLAN_RAM_CONTROL_3_PIPE3", 26347 /* EGR_VLAN_RAM_CONTROL_4_64 */ "EGR_VLAN_RAM_CONTROL_4", 26348 /* EGR_VLAN_RAM_CONTROL_4_64_PIPE0 */ "EGR_VLAN_RAM_CONTROL_4_PIPE0", 26349 /* EGR_VLAN_RAM_CONTROL_4_64_PIPE1 */ "EGR_VLAN_RAM_CONTROL_4_PIPE1", 26350 /* EGR_VLAN_RAM_CONTROL_4_64_PIPE2 */ "EGR_VLAN_RAM_CONTROL_4_PIPE2", 26351 /* EGR_VLAN_RAM_CONTROL_4_64_PIPE3 */ "EGR_VLAN_RAM_CONTROL_4_PIPE3", 26352 /* EGR_VLAN_RAM_CONTROL_4_PIPE0 */ "", 26353 /* EGR_VLAN_RAM_CONTROL_4_PIPE1 */ "", 26354 /* EGR_VLAN_RAM_CONTROL_4_PIPE2 */ "", 26355 /* EGR_VLAN_RAM_CONTROL_4_PIPE3 */ "", 26356 /* EGR_VLAN_RAM_CONTROL_5_PIPE0 */ "", 26357 /* EGR_VLAN_RAM_CONTROL_5_PIPE1 */ "", 26358 /* EGR_VLAN_RAM_CONTROL_5_PIPE2 */ "", 26359 /* EGR_VLAN_RAM_CONTROL_5_PIPE3 */ "", 26360 /* EGR_VLAN_RAM_CONTROL_6_PIPE0 */ "", 26361 /* EGR_VLAN_RAM_CONTROL_6_PIPE1 */ "", 26362 /* EGR_VLAN_RAM_CONTROL_6_PIPE2 */ "", 26363 /* EGR_VLAN_RAM_CONTROL_6_PIPE3 */ "", 26364 /* EGR_VLAN_RAM_CONTROL_7_PIPE0 */ "", 26365 /* EGR_VLAN_RAM_CONTROL_7_PIPE1 */ "", 26366 /* EGR_VLAN_RAM_CONTROL_7_PIPE2 */ "", 26367 /* EGR_VLAN_RAM_CONTROL_7_PIPE3 */ "", 26368 /* EGR_VLAN_RAM_CONTROL_8_PIPE0 */ "", 26369 /* EGR_VLAN_RAM_CONTROL_8_PIPE1 */ "", 26370 /* EGR_VLAN_RAM_CONTROL_8_PIPE2 */ "", 26371 /* EGR_VLAN_RAM_CONTROL_8_PIPE3 */ "", 26372 /* EGR_VLAN_RAM_CONTROL_DCM */ "", 26373 /* EGR_VLAN_RAM_CONTROL_PDAH */ "", 26374 /* EGR_VLAN_RAM_CONTROL_PDAH_PIPE0 */ "", 26375 /* EGR_VLAN_RAM_CONTROL_PDAH_PIPE1 */ "", 26376 /* EGR_VLAN_RAM_CONTROL_PDAH_PIPE2 */ "", 26377 /* EGR_VLAN_RAM_CONTROL_PDAH_PIPE3 */ "", 26378 /* EGR_VLAN_RAM_CONTROL_PM */ "", 26379 /* EGR_VLAN_RAM_CONTROL_PM_PIPE0 */ "", 26380 /* EGR_VLAN_RAM_CONTROL_PM_PIPE1 */ "", 26381 /* EGR_VLAN_RAM_CONTROL_PM_PIPE2 */ "", 26382 /* EGR_VLAN_RAM_CONTROL_PM_PIPE3 */ "", 26383 /* EGR_VLAN_RAM_CONTROL_STBY */ "", 26384 /* EGR_VLAN_RAM_MSP_ECC_CTRL */ "", 26385 /* EGR_VLAN_RAM_MSP_ECC_CTRL_PIPE0 */ "", 26386 /* EGR_VLAN_RAM_MSP_ECC_CTRL_PIPE1 */ "", 26387 /* EGR_VLAN_RAM_MSP_ECC_CTRL_PIPE2 */ "", 26388 /* EGR_VLAN_RAM_MSP_ECC_CTRL_PIPE3 */ "", 26389 /* EGR_VLAN_SER_CONTROL */ "", 26390 /* EGR_VLAN_STG_ADDR_MASK */ "", 26391 /* EGR_VLAN_STG_PARITY_CONTROL */ "", 26392 /* EGR_VLAN_STG_PARITY_STATUS */ "", 26393 /* EGR_VLAN_STG_PARITY_STATUS_INTR */ "", 26394 /* EGR_VLAN_STG_PARITY_STATUS_NACK */ "", 26395 /* EGR_VLAN_TABLE_PARITY_CONTROL */ "", 26396 /* EGR_VLAN_TABLE_PARITY_STATUS */ "", 26397 /* EGR_VLAN_TAG_ACTION_FOR_BYPASS */ "", 26398 /* EGR_VLAN_TCAM_SER_CONTROL */ "", 26399 /* EGR_VLAN_XLATE_CONTROL */ "", 26400 /* EGR_VLAN_XLATE_HASH_CONTROL */ "", 26401 /* EGR_VLAN_XLATE_PARITY_CONTROL */ "", 26402 /* EGR_VLAN_XLATE_PARITY_STATUS */ "", 26403 /* EGR_VLAN_XLATE_PARITY_STATUS_0 */ "", 26404 /* EGR_VLAN_XLATE_PARITY_STATUS_1 */ "", 26405 /* EGR_VLAN_XLATE_PARITY_STATUS_INTR_0 */ "", 26406 /* EGR_VLAN_XLATE_PARITY_STATUS_INTR_1 */ "", 26407 /* EGR_VLAN_XLATE_PARITY_STATUS_NACK_0 */ "", 26408 /* EGR_VLAN_XLATE_PARITY_STATUS_NACK_1 */ "", 26409 /* EGR_VP_GROUP_CHECK_ENABLE */ "", 26410 /* EGR_VP_VLAN_MEMBERSHIP_HASH_CONTROL */ "", 26411 /* EGR_VXLAN_CONTROL */ "", 26412 /* EGR_VXLAN_HEADER_PARITY_CONTROL */ "", 26413 /* EGR_VXLAN_HEADER_PARITY_STATUS */ "", 26414 /* EGR_VXLT_CAM_BIST_CONFIG */ "", 26415 /* EGR_VXLT_CAM_BIST_CONTROL */ "", 26416 /* EGR_VXLT_CAM_BIST_DBG_DATA */ "", 26417 /* EGR_VXLT_CAM_BIST_S10_STATUS */ "", 26418 /* EGR_VXLT_CAM_BIST_S2_STATUS */ "", 26419 /* EGR_VXLT_CAM_BIST_S3_STATUS */ "", 26420 /* EGR_VXLT_CAM_BIST_S5_STATUS */ "", 26421 /* EGR_VXLT_CAM_BIST_S6_STATUS */ "", 26422 /* EGR_VXLT_CAM_BIST_S8_STATUS */ "", 26423 /* EGR_VXLT_CAM_BIST_STATUS */ "", 26424 /* EGR_VXLT_CAM_CONTROL */ "", 26425 /* EGR_WESP_PROTO_CONTROL */ "", 26426 /* EGR_WLAN_DVP_PARITY_STATUS_INTR */ "", 26427 /* EGR_WLAN_DVP_PARITY_STATUS_NACK */ "", 26428 /* EGR_XL0_PARITY_STATUS */ "", 26429 /* EGR_XL10_PARITY_STATUS */ "", 26430 /* EGR_XL11_PARITY_STATUS */ "", 26431 /* EGR_XL12_PARITY_STATUS */ "", 26432 /* EGR_XL13_PARITY_STATUS */ "", 26433 /* EGR_XL1_PARITY_STATUS */ "", 26434 /* EGR_XL2_PARITY_STATUS */ "", 26435 /* EGR_XL3_PARITY_STATUS */ "", 26436 /* EGR_XL4_PARITY_STATUS */ "", 26437 /* EGR_XL5_PARITY_STATUS */ "", 26438 /* EGR_XL6_PARITY_STATUS */ "", 26439 /* EGR_XL7_PARITY_STATUS */ "", 26440 /* EGR_XL8_PARITY_STATUS */ "", 26441 /* EGR_XL9_PARITY_STATUS */ "", 26442 /* EGR_XLP0_BUFFER_STATUS_INTR */ "", 26443 /* EGR_XLP1_BUFFER_STATUS_INTR */ "", 26444 /* EGR_XLP2_BUFFER_STATUS_INTR */ "", 26445 /* EGR_XLP3_BUFFER_STATUS_INTR */ "", 26446 /* EGR_XLP4_BUFFER_STATUS_INTR */ "", 26447 /* EGR_XLP5_BUFFER_STATUS_INTR */ "", 26448 /* EGR_XLP6_BUFFER_STATUS_INTR */ "", 26449 /* EGR_XLP7_BUFFER_STATUS_INTR */ "", 26450 /* EGR_XLP8_BUFFER_STATUS_INTR */ "", 26451 /* EGR_XLPORT_BUFFER_SFT_RESET_0 */ "", 26452 /* EGR_XLPORT_BUFFER_SFT_RESET_1 */ "", 26453 /* EGR_XLPORT_BUFFER_SFT_RESET_0_X */ "", 26454 /* EGR_XLPORT_BUFFER_SFT_RESET_0_Y */ "", 26455 /* EGR_XLPORT_BUFFER_SFT_RESET_1_X */ "", 26456 /* EGR_XLPORT_BUFFER_SFT_RESET_1_Y */ "", 26457 /* EGR_XP0_DBITS_PARITY_STATUS */ "", 26458 /* EGR_XP0_PARITY_STATUS */ "", 26459 /* EGR_XP10_DBITS_PARITY_STATUS */ "", 26460 /* EGR_XP11_DBITS_PARITY_STATUS */ "", 26461 /* EGR_XP12_DBITS_PARITY_STATUS */ "", 26462 /* EGR_XP13_DBITS_PARITY_STATUS */ "", 26463 /* EGR_XP14_DBITS_PARITY_STATUS */ "", 26464 /* EGR_XP15_DBITS_PARITY_STATUS */ "", 26465 /* EGR_XP16_DBITS_PARITY_STATUS */ "", 26466 /* EGR_XP17_DBITS_PARITY_STATUS */ "", 26467 /* EGR_XP18_DBITS_PARITY_STATUS */ "", 26468 /* EGR_XP19_DBITS_PARITY_STATUS */ "", 26469 /* EGR_XP1_DBITS_PARITY_STATUS */ "", 26470 /* EGR_XP1_PARITY_STATUS */ "", 26471 /* EGR_XP2_DBITS_PARITY_STATUS */ "", 26472 /* EGR_XP2_PARITY_STATUS */ "", 26473 /* EGR_XP3_DBITS_PARITY_STATUS */ "", 26474 /* EGR_XP3_PARITY_STATUS */ "", 26475 /* EGR_XP4_DBITS_PARITY_STATUS */ "", 26476 /* EGR_XP5_DBITS_PARITY_STATUS */ "", 26477 /* EGR_XP6_DBITS_PARITY_STATUS */ "", 26478 /* EGR_XP7_DBITS_PARITY_STATUS */ "", 26479 /* EGR_XP8_DBITS_PARITY_STATUS */ "", 26480 /* EGR_XP9_DBITS_PARITY_STATUS */ "", 26481 /* EGR_XQ0_BUFFER_STATUS_INTR */ "", 26482 /* EGR_XQ0_DBUF_PARITY_CONTROL */ "", 26483 /* EGR_XQ0_DBUF_PARITY_STATUS */ "", 26484 /* EGR_XQ0_PFC_CONTROL */ "", 26485 /* EGR_XQ1_BUFFER_STATUS_INTR */ "", 26486 /* EGR_XQ1_DBUF_PARITY_CONTROL */ "", 26487 /* EGR_XQ1_DBUF_PARITY_STATUS */ "", 26488 /* EGR_XQ1_PFC_CONTROL */ "", 26489 /* EGR_XQ2_BUFFER_STATUS_INTR */ "", 26490 /* EGR_XQ2_DBUF_PARITY_CONTROL */ "", 26491 /* EGR_XQ2_DBUF_PARITY_STATUS */ "", 26492 /* EGR_XQ2_PFC_CONTROL */ "", 26493 /* EGR_XQ3_BUFFER_STATUS_INTR */ "", 26494 /* EGR_XQ3_DBUF_PARITY_CONTROL */ "", 26495 /* EGR_XQ3_DBUF_PARITY_STATUS */ "", 26496 /* EGR_XQ3_PFC_CONTROL */ "", 26497 /* EGR_XQ4_BUFFER_STATUS_INTR */ "", 26498 /* EGR_XQ4_PFC_CONTROL */ "", 26499 /* EGR_XQ5_BUFFER_STATUS_INTR */ "", 26500 /* EGR_XQ5_PFC_CONTROL */ "", 26501 /* EGR_XQ6_BUFFER_STATUS_INTR */ "", 26502 /* EGR_XQ6_PFC_CONTROL */ "", 26503 /* EGR_XQ7_BUFFER_STATUS_INTR */ "", 26504 /* EGR_XQ7_PFC_CONTROL */ "", 26505 /* EGR_XQ8_PFC_CONTROL */ "", 26506 /* EGR_XQ9_PFC_CONTROL */ "", 26507 /* EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_CONFIG_64 */ "", 26508 /* EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_STATUS */ "", 26509 /* EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0 */ "", 26510 /* EGR_ZONE_0_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1 */ "", 26511 /* EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_CONFIG_64 */ "", 26512 /* EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_STATUS */ "", 26513 /* EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0 */ "", 26514 /* EGR_ZONE_1_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1 */ "", 26515 /* EGR_ZONE_1_L2_TAG_ACTIONS_MAP_CNTAG */ "", 26516 /* EGR_ZONE_1_L2_TAG_ACTIONS_MAP_ETAG */ "", 26517 /* EGR_ZONE_1_L2_TAG_ACTIONS_MAP_IVLAN */ "", 26518 /* EGR_ZONE_1_L2_TAG_ACTIONS_MAP_OVLAN */ "", 26519 /* EGR_ZONE_1_L2_TAG_ACTIONS_MAP_SUBPORT_TAG */ "", 26520 /* EGR_ZONE_1_L2_TAG_ACTIONS_MAP_VNTAG */ "", 26521 /* EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_CONFIG_64 */ "", 26522 /* EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_STATUS */ "", 26523 /* EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0 */ "", 26524 /* EGR_ZONE_2_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1 */ "", 26525 /* EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_CONFIG_64 */ "", 26526 /* EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_STATUS */ "", 26527 /* EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0 */ "", 26528 /* EGR_ZONE_3_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1 */ "", 26529 /* EGR_ZONE_3_L2_TAG_ACTIONS_MAP_CNTAG */ "", 26530 /* EGR_ZONE_3_L2_TAG_ACTIONS_MAP_ETAG */ "", 26531 /* EGR_ZONE_3_L2_TAG_ACTIONS_MAP_IVLAN */ "", 26532 /* EGR_ZONE_3_L2_TAG_ACTIONS_MAP_OVLAN */ "", 26533 /* EGR_ZONE_3_L2_TAG_ACTIONS_MAP_SUBPORT_TAG */ "", 26534 /* EGR_ZONE_3_L2_TAG_ACTIONS_MAP_VNTAG */ "", 26535 /* EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_CONFIG_64 */ "", 26536 /* EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_STATUS */ "", 26537 /* EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE0 */ "", 26538 /* EGR_ZONE_4_EDITOR_CONTROL_CAM_BIST_STATUS_PIPE1 */ "", 26539 /* EGR_ZONE_MATCH_ID_CONFIG */ "", 26540 /* EHCPM_RAM_DBGCTRL */ "EHCPM_RAM_CONTROL", 26541 /* EHG_RX_CONTROL */ "", 26542 /* EHG_RX_PKT_DROP */ "", 26543 /* EHG_TPID */ "", 26544 /* EHG_TX_CONTROL */ "", 26545 /* EHG_TX_IPV4ID */ "", 26546 /* EINITBUF_DEBUG_CONTROL */ "", 26547 /* EL3_RAM_CONTROL */ "", 26548 /* EL3_RAM_CONTROL_64 */ "", 26549 /* EL3_RAM_DBGCTRL */ "EL3_RAM_CONTROL", 26550 /* EL3_TM_REG_1 */ "", 26551 /* EMC_BUFFER_EMPTY_FULL_STATUS_DEBUG */ "", 26552 /* EMC_CFG */ "", 26553 /* EMC_CI_FULL_STATUS_DEBUG */ "", 26554 /* EMC_CSDB_0_BUFFER_PAR_STATUS_DEBUG */ "", 26555 /* EMC_CSDB_1_BUFFER_PAR_STATUS_DEBUG */ "", 26556 /* EMC_CSDB_2_BUFFER_PAR_STATUS_DEBUG */ "", 26557 /* EMC_CSDB_3_BUFFER_PAR_STATUS_DEBUG */ "", 26558 /* EMC_CSDB_4_BUFFER_PAR_STATUS_DEBUG */ "", 26559 /* EMC_CSDB_5_BUFFER_PAR_STATUS_DEBUG */ "", 26560 /* EMC_CSDB_MEM_DEBUG */ "", 26561 /* EMC_ECC_DEBUG */ "", 26562 /* EMC_ECC_DEBUG_0 */ "", 26563 /* EMC_ECC_DEBUG_1 */ "", 26564 /* EMC_ERRB_0_BUFFER_ECC_STATUS_DEBUG */ "", 26565 /* EMC_ERRB_0_BUFFER_FILL_LEVEL_DEBUG */ "", 26566 /* EMC_ERRB_0_BUFFER_WATERMARK_DEBUG */ "", 26567 /* EMC_ERRB_0_MEM_DEBUG */ "", 26568 /* EMC_ERRB_1_BUFFER_ECC_STATUS_DEBUG */ "", 26569 /* EMC_ERRB_1_BUFFER_FILL_LEVEL_DEBUG */ "", 26570 /* EMC_ERRB_1_BUFFER_WATERMARK_DEBUG */ "", 26571 /* EMC_ERRB_1_MEM_DEBUG */ "", 26572 /* EMC_ERRB_BUFFER_ECC_STATUS_DEBUG */ "", 26573 /* EMC_ERRB_BUFFER_FILL_LEVEL_DEBUG */ "", 26574 /* EMC_ERRB_BUFFER_WATERMARK_DEBUG */ "", 26575 /* EMC_ERRB_FIFO_NFULL_THRESHOLD */ "", 26576 /* EMC_ERRB_MEM_DEBUG */ "", 26577 /* EMC_ERROR */ "", 26578 /* EMC_ERROR_0 */ "", 26579 /* EMC_ERROR_1 */ "", 26580 /* EMC_ERROR_2 */ "", 26581 /* EMC_ERROR_3 */ "", 26582 /* EMC_ERROR_MASK_0 */ "", 26583 /* EMC_ERROR_MASK_1 */ "", 26584 /* EMC_ERROR_MASK_2 */ "", 26585 /* EMC_ERROR_MASK_3 */ "", 26586 /* EMC_EWRB_0_BUFFER_0_ECC_STATUS_DEBUG */ "", 26587 /* EMC_EWRB_0_BUFFER_1_ECC_STATUS_DEBUG */ "", 26588 /* EMC_EWRB_0_BUFFER_FILL_LEVEL_DEBUG */ "", 26589 /* EMC_EWRB_0_BUFFER_WATERMARK_DEBUG */ "", 26590 /* EMC_EWRB_0_MEM_DEBUG */ "", 26591 /* EMC_EWRB_1_BUFFER_0_ECC_STATUS_DEBUG */ "", 26592 /* EMC_EWRB_1_BUFFER_1_ECC_STATUS_DEBUG */ "", 26593 /* EMC_EWRB_1_BUFFER_FILL_LEVEL_DEBUG */ "", 26594 /* EMC_EWRB_1_BUFFER_WATERMARK_DEBUG */ "", 26595 /* EMC_EWRB_1_MEM_DEBUG */ "", 26596 /* EMC_EWRB_BUFFER_0_ECC_STATUS_DEBUG */ "", 26597 /* EMC_EWRB_BUFFER_1_ECC_STATUS_DEBUG */ "", 26598 /* EMC_EWRB_BUFFER_FILL_LEVEL_DEBUG */ "", 26599 /* EMC_EWRB_BUFFER_WATERMARK_DEBUG */ "", 26600 /* EMC_EWRB_FIFO_NFULL_THRESHOLD */ "", 26601 /* EMC_EWRB_MEM_DEBUG */ "", 26602 /* EMC_FIXED_PATTERN_DEBUG */ "", 26603 /* EMC_FREE_POOL_SIZES */ "", 26604 /* EMC_GLOBAL_1B_ECC_ERROR_COUNT_DEBUG */ "", 26605 /* EMC_GLOBAL_2B_ECC_ERROR_COUNT_DEBUG */ "", 26606 /* EMC_IRRB_BUFFER_ECC_STATUS_DEBUG */ "", 26607 /* EMC_IRRB_BUFFER_FILL_LEVEL_DEBUG */ "", 26608 /* EMC_IRRB_BUFFER_WATERMARK_DEBUG */ "", 26609 /* EMC_IRRB_MEM_DEBUG */ "", 26610 /* EMC_IRRB_THRESHOLDS */ "", 26611 /* EMC_IWRB_BUFFER_ECC_STATUS_DEBUG */ "", 26612 /* EMC_IWRB_BUFFER_FILL_LEVEL_DEBUG */ "", 26613 /* EMC_IWRB_BUFFER_WATERMARK_DEBUG */ "", 26614 /* EMC_IWRB_MEM_DEBUG */ "", 26615 /* EMC_IWRB_SIZE */ "", 26616 /* EMC_RFCQ_BUFFER_ECC_STATUS_DEBUG */ "", 26617 /* EMC_RFCQ_BUFFER_FILL_LEVEL_DEBUG */ "", 26618 /* EMC_RFCQ_BUFFER_WATERMARK_DEBUG */ "", 26619 /* EMC_RFCQ_MEM_DEBUG */ "", 26620 /* EMC_RSFP_BUFFER_ECC_STATUS_DEBUG */ "", 26621 /* EMC_RSFP_BUFFER_FILL_LEVEL_DEBUG */ "", 26622 /* EMC_RSFP_MEM_DEBUG */ "", 26623 /* EMC_SWAT_BUFFER_ECC_STATUS_DEBUG */ "", 26624 /* EMC_SWAT_MEM_DEBUG */ "", 26625 /* EMC_TO_CI0_RD_REQ_COUNT_DEBUG */ "", 26626 /* EMC_TO_CI0_WR_REQ_COUNT_DEBUG */ "", 26627 /* EMC_TO_CI1_RD_REQ_COUNT_DEBUG */ "", 26628 /* EMC_TO_CI1_WR_REQ_COUNT_DEBUG */ "", 26629 /* EMC_TO_CI2_RD_REQ_COUNT_DEBUG */ "", 26630 /* EMC_TO_CI2_WR_REQ_COUNT_DEBUG */ "", 26631 /* EMC_TO_CI3_RD_REQ_COUNT_DEBUG */ "", 26632 /* EMC_TO_CI3_WR_REQ_COUNT_DEBUG */ "", 26633 /* EMC_TO_CI4_RD_REQ_COUNT_DEBUG */ "", 26634 /* EMC_TO_CI4_WR_REQ_COUNT_DEBUG */ "", 26635 /* EMC_TO_CI5_RD_REQ_COUNT_DEBUG */ "", 26636 /* EMC_TO_CI5_WR_REQ_COUNT_DEBUG */ "", 26637 /* EMC_TO_ITE_WR_REQ_PKT_COMPLETE_COUNT_DEBUG */ "", 26638 /* EMC_WCMT_BUFFER_ECC_STATUS_DEBUG */ "", 26639 /* EMC_WCMT_MEM_DEBUG */ "", 26640 /* EMC_WLCT0_LOWER_A_BUFFER_ECC_STATUS_DEBUG */ "", 26641 /* EMC_WLCT0_LOWER_B_BUFFER_ECC_STATUS_DEBUG */ "", 26642 /* EMC_WLCT0_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUG */ "", 26643 /* EMC_WLCT0_UPPER_A_BUFFER_ECC_STATUS_DEBUG */ "", 26644 /* EMC_WLCT0_UPPER_B_BUFFER_ECC_STATUS_DEBUG */ "", 26645 /* EMC_WLCT1_LOWER_A_BUFFER_ECC_STATUS_DEBUG */ "", 26646 /* EMC_WLCT1_LOWER_B_BUFFER_ECC_STATUS_DEBUG */ "", 26647 /* EMC_WLCT1_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUG */ "", 26648 /* EMC_WLCT1_UPPER_A_BUFFER_ECC_STATUS_DEBUG */ "", 26649 /* EMC_WLCT1_UPPER_B_BUFFER_ECC_STATUS_DEBUG */ "", 26650 /* EMC_WLCT2_LOWER_A_BUFFER_ECC_STATUS_DEBUG */ "", 26651 /* EMC_WLCT2_LOWER_B_BUFFER_ECC_STATUS_DEBUG */ "", 26652 /* EMC_WLCT2_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUG */ "", 26653 /* EMC_WLCT2_UPPER_A_BUFFER_ECC_STATUS_DEBUG */ "", 26654 /* EMC_WLCT2_UPPER_B_BUFFER_ECC_STATUS_DEBUG */ "", 26655 /* EMC_WLCT_BUFFER_ECC_STATUS_DEBUG */ "", 26656 /* EMC_WLCT_MEM_DEBUG */ "", 26657 /* EMC_WLCT_MERGED_RETURN_WTAG_FIFO_ECC_STATUS_DEBUG */ "", 26658 /* EMC_WLCT_MERGED_RETURN_WTAG_FIFO_FILL_LEVEL_DEBUG */ "", 26659 /* EMC_WLCT_MERGED_RETURN_WTAG_FIFO_MEM_DEBUG */ "", 26660 /* EMC_WLCT_MERGED_RETURN_WTAG_FIFO_NFULL_THRESHOLD */ "", 26661 /* EMC_WLCT_MERGED_RETURN_WTAG_FIFO_WATERMARK_DEBUG */ "", 26662 /* EMC_WTFP_BUFFER_ECC_STATUS_DEBUG */ "", 26663 /* EMC_WTFP_BUFFER_FILL_LEVEL_DEBUG */ "", 26664 /* EMC_WTFP_MEM_DEBUG */ "", 26665 /* EMC_WTOQ_BUFFER_ECC_STATUS_DEBUG */ "", 26666 /* EMC_WTOQ_BUFFER_FILL_LEVEL_DEBUG */ "", 26667 /* EMC_WTOQ_MEM_DEBUG */ "", 26668 /* EMIRROR_CONTROL */ "", 26669 /* EMIRROR_CONTROL1 */ "", 26670 /* EMIRROR_CONTROL1_64 */ "EMIRROR_CONTROL1", 26671 /* EMIRROR_CONTROL1_HI */ "EMIRROR_CONTROL1_HI", 26672 /* EMIRROR_CONTROL1_LO */ "EMIRROR_CONTROL1_LO", 26673 /* EMIRROR_CONTROL1_PARITY_CONTROL */ "", 26674 /* EMIRROR_CONTROL1_PARITY_STATUS_INTR */ "", 26675 /* EMIRROR_CONTROL1_PARITY_STATUS_NACK */ "", 26676 /* EMIRROR_CONTROL2_64 */ "EMIRROR_CONTROL2", 26677 /* EMIRROR_CONTROL2_PARITY_CONTROL */ "", 26678 /* EMIRROR_CONTROL2_PARITY_STATUS_INTR */ "", 26679 /* EMIRROR_CONTROL2_PARITY_STATUS_NACK */ "", 26680 /* EMIRROR_CONTROL3_64 */ "EMIRROR_CONTROL3", 26681 /* EMIRROR_CONTROL3_PARITY_CONTROL */ "", 26682 /* EMIRROR_CONTROL3_PARITY_STATUS_INTR */ "", 26683 /* EMIRROR_CONTROL3_PARITY_STATUS_NACK */ "", 26684 /* EMIRROR_CONTROL_64 */ "EMIRROR_CONTROL", 26685 /* EMIRROR_CONTROL_HI */ "", 26686 /* EMIRROR_CONTROL_HI_64 */ "EMIRROR_CONTROL_HI_64", 26687 /* EMIRROR_CONTROL_LO_64 */ "EMIRROR_CONTROL_LO_64", 26688 /* EMIRROR_CONTROL_PARITY_CONTROL */ "", 26689 /* EMIRROR_CONTROL_PARITY_STATUS_INTR */ "", 26690 /* EMIRROR_CONTROL_PARITY_STATUS_NACK */ "", 26691 /* EMMU_FUSE_DEBUG0 */ "", 26692 /* EMMU_FUSE_DEBUG1 */ "", 26693 /* EMMU_FUSE_DEBUG2 */ "", 26694 /* ENDPOINT_QUEUE_MAP_HASH_CONTROL */ "", 26695 /* ENHANCED_HASHING_CONTROL */ "", 26696 /* ENHANCED_HASHING_CONTROL_2 */ "", 26697 /* ENQS_ASF_ERROR */ "", 26698 /* ENQS_ASF_ERROR_0 */ "", 26699 /* ENQS_ASF_ERROR_1 */ "", 26700 /* ENQS_CONFIG */ "", 26701 /* ENQ_ASF_ERROR */ "", 26702 /* ENQ_ASF_HS_OVERSUB_EN */ "", 26703 /* ENQ_ASF_LRCT_OVERSUB_EN */ "", 26704 /* ENQ_ASF_MASK */ "", 26705 /* ENQ_ASF_SUPPRESS_ES_OVERSUB_HS_PICK */ "", 26706 /* ENQ_CCBI_ERROR */ "", 26707 /* ENQ_CCBI_ERROR_MASK */ "", 26708 /* ENQ_CONFIG */ "", 26709 /* ENQ_CTRL_PKT_MODE */ "", 26710 /* ENQ_IPMCGRP_TBL_PARITYERRORPTR */ "", 26711 /* ENQ_IPMCGRP_TBL_PARITYERROR_STATUS */ "", 26712 /* ENQ_IP_PKT_MON */ "", 26713 /* ENQ_PRI_TO_RQE_CPU_HI_QUEUE_MAPPING */ "", 26714 /* ENQ_PRI_TO_RQE_CPU_LO_QUEUE_MAPPING */ "", 26715 /* ENQ_PRI_TO_RQE_MIRROR_QUEUE_MAPPING */ "", 26716 /* EOP_BUFFER_MTU_ECC_STATUS_INTR */ "", 26717 /* EOP_BUFFER_MTU_ECC_STATUS_INTR_PIPE0 */ "", 26718 /* EOP_BUFFER_MTU_ECC_STATUS_INTR_PIPE1 */ "", 26719 /* EOP_BUFFER_MTU_ECC_STATUS_INTR_PIPE2 */ "", 26720 /* EOP_BUFFER_MTU_ECC_STATUS_INTR_PIPE3 */ "", 26721 /* EPC_LINK_BMAP */ "", 26722 /* EPC_LINK_BMAP_64 */ "EPC_LINK_BMAP", 26723 /* EPC_LINK_BMAP_HI */ "", 26724 /* EPC_LINK_BMAP_HI_64 */ "EPC_LINK_BMAP_HI_64", 26725 /* EPC_LINK_BMAP_LO_64 */ "EPC_LINK_BMAP_LO_64", 26726 /* EPNI_ACCEPTABLE_FRAME_TYPE */ "", 26727 /* EPNI_ALIGNER_CONFIGURATION */ "", 26728 /* EPNI_ALIGNER_ERROR_STATUS */ "", 26729 /* EPNI_AUXILIARY_DATA_TABLE */ "", 26730 /* EPNI_BSA */ "", 26731 /* EPNI_CFG_48_BITS_1588_TS_ENABLE */ "", 26732 /* EPNI_CFG_ACC_FRAME_TYPE_TRAP */ "", 26733 /* EPNI_CFG_AC_OUTLIF_PROFILE_MEMBERSHIP_CHECK */ "", 26734 /* EPNI_CFG_ADDITIONAL_TPID_VALUES */ "", 26735 /* EPNI_CFG_ALWAYS_CHECK_IPVX_COMPATIBLE_MC */ "", 26736 /* EPNI_CFG_BUG_FIX_CHICKEN_BITS_REG_1 */ "", 26737 /* EPNI_CFG_BUG_FIX_CHICKEN_BITS_REG_2 */ "", 26738 /* EPNI_CFG_DC_OVERLAY */ "", 26739 /* EPNI_CFG_EEDB_ARP_POINTER_MSB */ "", 26740 /* EPNI_CFG_EEI_MAPPING_IS_REQUIRED */ "", 26741 /* EPNI_CFG_EES_ACTION_TRAP */ "", 26742 /* EPNI_CFG_EGRESS_MEMBERSHIP_FILTER */ "", 26743 /* EPNI_CFG_EGRESS_OAM_INJECTION_MAP */ "", 26744 /* EPNI_CFG_ENABLE_DSCP_MARKING */ "", 26745 /* EPNI_CFG_ENABLE_ETAG */ "", 26746 /* EPNI_CFG_ENABLE_FILTERING_PER_FWD_CODE */ "", 26747 /* EPNI_CFG_ENTRY_TYPE_L_2_LIF */ "", 26748 /* EPNI_CFG_ETPP_LATENCY_TRAP */ "", 26749 /* EPNI_CFG_ETPP_SER_TRAP */ "", 26750 /* EPNI_CFG_EVE_ETAG_FORMAT */ "", 26751 /* EPNI_CFG_FWD_CODE_BUG_FIX_DISABLED */ "", 26752 /* EPNI_CFG_GLEM_LKUP_CONFIG */ "", 26753 /* EPNI_CFG_GLEM_TRAP */ "", 26754 /* EPNI_CFG_GRE_ETHERTYPE_ETHERNET */ "", 26755 /* EPNI_CFG_GRE_ETHERTYPE_IP */ "", 26756 /* EPNI_CFG_ING_MC_FIX */ "", 26757 /* EPNI_CFG_IN_LIF_PROFILE_MAP */ "", 26758 /* EPNI_CFG_KEEP_ING_ECID */ "", 26759 /* EPNI_CFG_LATENCY_ACCURACY */ "", 26760 /* EPNI_CFG_LATENCY_COUNTER_PORT_OFFSET */ "", 26761 /* EPNI_CFG_LATENCY_PER_PORT_ENABLE */ "", 26762 /* EPNI_CFG_LINK_FIFOS_FIXED_LATENCY_SETTING */ "", 26763 /* EPNI_CFG_MAP_ENC_MODE_TO_PROTOCOL */ "", 26764 /* EPNI_CFG_MAP_ENC_MODE_TO_SIZE */ "", 26765 /* EPNI_CFG_MAP_ENC_MODE_TO_TEMPLATE */ "", 26766 /* EPNI_CFG_MAP_OUTLIF_PROFILE_TO_DOMAIN */ "", 26767 /* EPNI_CFG_MAP_OUTLIF_PROFILE_TO_ENC_MODE */ "", 26768 /* EPNI_CFG_MAP_OUTLIF_PROFILE_TO_L_2_CP_PROFILE */ "", 26769 /* EPNI_CFG_MAP_OUTLIF_PROFILE_TO_NATIVE_DEFAULT_AC */ "", 26770 /* EPNI_CFG_MAP_OUTLIF_PROFILE_TO_NATIVE_L_2_CP_PROFILE */ "", 26771 /* EPNI_CFG_MAP_OUTLIF_PROFILE_TO_ORIENTATION */ "", 26772 /* EPNI_CFG_MARKING_DP_MAP */ "", 26773 /* EPNI_CFG_MPLS_NULL_VALUES */ "", 26774 /* EPNI_CFG_MTU_TRAP */ "", 26775 /* EPNI_CFG_NATIVE_DEFAULT_AC_POINTERS */ "", 26776 /* EPNI_CFG_NATIVE_ESEM_KEY_SELECT */ "", 26777 /* EPNI_CFG_NATIVE_ETHERNET_COMPENSATION */ "", 26778 /* EPNI_CFG_NATIVE_EVE_ENABLE */ "", 26779 /* EPNI_CFG_NEW_IP_TUNNEL_ENC_MODE_ENABLED */ "", 26780 /* EPNI_CFG_OUTER_TAG */ "", 26781 /* EPNI_CFG_OUTLIF_MAPPING_IS_REQUIRED */ "", 26782 /* EPNI_CFG_OUTLIF_PROFILE_ALLOW_QOS_INHERITANCE */ "", 26783 /* EPNI_CFG_OUTLIF_PROFILE_ALLOW_TTL_INHERITANCE */ "", 26784 /* EPNI_CFG_OUTLIF_PROFILE_L_2_LIF */ "", 26785 /* EPNI_CFG_OUT_PP_PORT_DEFAULT_MEMBERSHIP */ "", 26786 /* EPNI_CFG_PETRAB_OUT_LIF_SRC */ "", 26787 /* EPNI_CFG_PORT_ENABLE_DSCP_MARKING */ "", 26788 /* EPNI_CFG_PP_LIF_COUNTER_MODE */ "", 26789 /* EPNI_CFG_PROTECTION_PATH_TRAP */ "", 26790 /* EPNI_CFG_PROTECTION_PTR_MODE */ "", 26791 /* EPNI_CFG_PRP_FIFOS_FIXED_LATENCY_SETTING */ "", 26792 /* EPNI_CFG_RIF_COUNTER_FWD_CODE_OFFSET */ "", 26793 /* EPNI_CFG_RIF_COUNTER_PORT_OFFSET */ "", 26794 /* EPNI_CFG_RIF_IN_STACK */ "", 26795 /* EPNI_CFG_ROUTING_PER_HEADER_CODE_ENABLE */ "", 26796 /* EPNI_CFG_SCHEDULER_PKT_SZ_COMP_ENABLE */ "", 26797 /* EPNI_CFG_SPLIT_HORIZON_FILTER */ "", 26798 /* EPNI_CFG_SPLIT_HORIZON_TRAP */ "", 26799 /* EPNI_CFG_STP_STATE_TRAP */ "", 26800 /* EPNI_CFG_TRILL_NICKNAME_BRIDGING */ "", 26801 /* EPNI_CFG_TRILL_NICKNAME_ROUTING */ "", 26802 /* EPNI_CFG_TX_TAG_USED_AS_RIF_REMARK */ "", 26803 /* EPNI_CFG_VSI_COUNTER_PORT_OFFSET */ "", 26804 /* EPNI_CFG_VSI_MEMBERSHIP_FILTER */ "", 26805 /* EPNI_CFG_VXLAN_UDP_FIELDS */ "", 26806 /* EPNI_CHECK_BW_TO_PACKET_DESCRIPTOR */ "", 26807 /* EPNI_CHICKEN_BIT_VECTOR */ "", 26808 /* EPNI_CMICM_CREDITS_ON_INIT */ "", 26809 /* EPNI_CONFIGURES_EGRESS_INTERFACES */ "", 26810 /* EPNI_COUNTERS_BASE */ "", 26811 /* EPNI_COUNTER_0_BASE */ "", 26812 /* EPNI_COUNTER_1_BASE */ "", 26813 /* EPNI_COUNTER_OUT_LIF_RANGE_0 */ "", 26814 /* EPNI_COUNTER_OUT_LIF_RANGE_1 */ "", 26815 /* EPNI_COUNTER_PORT_TM */ "", 26816 /* EPNI_COUNTER_RESOLUTION_FIX_ENABLED */ "", 26817 /* EPNI_DBG_COMMAND */ "", 26818 /* EPNI_DBG_DATA */ "", 26819 /* EPNI_DEFAULT_AC_ENTRY */ "", 26820 /* EPNI_DISABLE_EGRESS_INTERFACES */ "", 26821 /* EPNI_DP_MAP_FIX_ENABLED */ "", 26822 /* EPNI_DROPPED_PKT_CONFIGURATION */ "", 26823 /* EPNI_ECC_1B_ERR_CNT */ "", 26824 /* EPNI_ECC_2B_ERR_CNT */ "", 26825 /* EPNI_ECC_ERR_1B_INITIATE */ "", 26826 /* EPNI_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 26827 /* EPNI_ECC_ERR_2B_INITIATE */ "", 26828 /* EPNI_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 26829 /* EPNI_ECC_INTERRUPT_REGISTER */ "", 26830 /* EPNI_ECC_INTERRUPT_REGISTER_MASK */ "", 26831 /* EPNI_ECC_INTERRUPT_REGISTER_TEST */ "", 26832 /* EPNI_ECN_IP_MAP */ "", 26833 /* EPNI_ECN_MPLS_MAP */ "", 26834 /* EPNI_ECN_REMARK */ "", 26835 /* EPNI_EEDB_NATIVE_OUTLIF_BASE */ "", 26836 /* EPNI_EEDB_OUTLIF_ACCESS */ "", 26837 /* EPNI_EEDB_OUTLIF_BASE */ "", 26838 /* EPNI_EGQ_IFC_DELAY_CHECK */ "", 26839 /* EPNI_EGRESS_INTERFACE_NO_FRAGMENTATION_MODE_CONFIGURATION */ "", 26840 /* EPNI_EGRESS_MEMBERSHIP_MODE */ "", 26841 /* EPNI_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 26842 /* EPNI_ENTROPY_LABEL_MSBS */ "", 26843 /* EPNI_EPE_BYTES_COUNTER */ "", 26844 /* EPNI_EPE_DISCARDED_PACKETS_COUNTER */ "", 26845 /* EPNI_EPE_MIRRORED_PACKETS_COUNTER */ "", 26846 /* EPNI_EPE_PACKET_COUNTER */ "", 26847 /* EPNI_EPNI_CNT_CFG */ "", 26848 /* EPNI_EPNI_DISC_CNT */ "", 26849 /* EPNI_EPNI_FIFO_WATERMARKS */ "", 26850 /* EPNI_EPNI_FRWD_DISC_CNT */ "", 26851 /* EPNI_EPNI_IFC_CNT */ "", 26852 /* EPNI_EPNI_INIT_STATUS */ "", 26853 /* EPNI_EPNI_MIRR_CNT */ "", 26854 /* EPNI_EPNI_Q_CNT */ "", 26855 /* EPNI_ERROR_INITIATION_DATA */ "", 26856 /* EPNI_ESEM_CAM_ENTRIES_COUNTER */ "", 26857 /* EPNI_ESEM_DIAGNOSTICS */ "", 26858 /* EPNI_ESEM_DIAGNOSTICS_ACCESSED_MODE */ "", 26859 /* EPNI_ESEM_DIAGNOSTICS_INDEX */ "", 26860 /* EPNI_ESEM_DIAGNOSTICS_KEY */ "", 26861 /* EPNI_ESEM_DIAGNOSTICS_LOOKUP_RESULT */ "", 26862 /* EPNI_ESEM_DIAGNOSTICS_READ_RESULT */ "", 26863 /* EPNI_ESEM_ENTRIES_COUNTER */ "", 26864 /* EPNI_ESEM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 26865 /* EPNI_ESEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 26866 /* EPNI_ESEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 26867 /* EPNI_ESEM_ERROR_TABLE_COHERENCY_COUNTER */ "", 26868 /* EPNI_ESEM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 26869 /* EPNI_ESEM_INTERRUPT_MASK_REGISTER_ONE */ "", 26870 /* EPNI_ESEM_INTERRUPT_REGISTER_ONE */ "", 26871 /* EPNI_ESEM_INTERRUPT_REGISTER_ONE_TEST */ "", 26872 /* EPNI_ESEM_KEY_TABLE_ENTRY_LIMIT */ "", 26873 /* EPNI_ESEM_LAST_LOOKUP */ "", 26874 /* EPNI_ESEM_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 26875 /* EPNI_ESEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 26876 /* EPNI_ESEM_MANAGEMENT_UNIT_FAILURE */ "", 26877 /* EPNI_ESEM_REQUESTS_COUNTER */ "", 26878 /* EPNI_ESEM_RESET_STATUS_REGISTER */ "", 26879 /* EPNI_ESEM_WARNING_INSERTED_EXISTING_COUNTER */ "", 26880 /* EPNI_ETHERNET_HEADER_EDITING_SIZE */ "", 26881 /* EPNI_ETHERNET_IP */ "", 26882 /* EPNI_ETHERNET_TYPES */ "", 26883 /* EPNI_ETHERTYPE_CUSTOM */ "", 26884 /* EPNI_ETHERTYPE_DEFAULT */ "", 26885 /* EPNI_ETPP_LAST_INTERRUPT_TM_CMD */ "", 26886 /* EPNI_ETPP_LAST_TM_CMD */ "", 26887 /* EPNI_ETPP_PIPE_LENGTH */ "", 26888 /* EPNI_FALL_BACK_TO_BRIDGE_VLAN_COMMANDS */ "", 26889 /* EPNI_FALL_TO_BRIDGE_FWD_CODE_FIX_ENABLED */ "", 26890 /* EPNI_FHEI_MPLS_COMMAND */ "", 26891 /* EPNI_GLOBAL_CONFIG */ "", 26892 /* EPNI_GLOBAL_GENERAL_CFG_1 */ "", 26893 /* EPNI_GLOBAL_GENERAL_CFG_2 */ "", 26894 /* EPNI_GLOBAL_GENERAL_CFG_3 */ "", 26895 /* EPNI_GLOBAL_MEM_OPTIONS */ "", 26896 /* EPNI_GLOBAL_PP_2 */ "", 26897 /* EPNI_GLOBAL_PP_3 */ "", 26898 /* EPNI_GLOBAL_PP_4 */ "", 26899 /* EPNI_GLOBAL_PP_5 */ "", 26900 /* EPNI_GLOBAL_PP_6 */ "", 26901 /* EPNI_GLOBAL_PP_7 */ "", 26902 /* EPNI_GLOBAL_PP_8 */ "", 26903 /* EPNI_GLOBAL_SYS_HEADER_CFG */ "", 26904 /* EPNI_GTIMER_CONFIG */ "", 26905 /* EPNI_GTIMER_CONFIGURATION */ "", 26906 /* EPNI_GTIMER_CONFIG_CONT */ "", 26907 /* EPNI_GTIMER_CYCLE */ "", 26908 /* EPNI_GTIMER_TRIGGER */ "", 26909 /* EPNI_HEADER_EDITING_SIZE */ "", 26910 /* EPNI_IEEE_1588 */ "", 26911 /* EPNI_IEEE_1588_TS_MSB_COUNTER */ "", 26912 /* EPNI_IFC_IS_LBG */ "", 26913 /* EPNI_INDIRECT_COMMAND */ "", 26914 /* EPNI_INDIRECT_COMMAND_ADDRESS */ "", 26915 /* EPNI_INDIRECT_COMMAND_DATA_INCREMENT */ "", 26916 /* EPNI_INDIRECT_COMMAND_RD_DATA */ "", 26917 /* EPNI_INDIRECT_COMMAND_WIDE_MEM */ "", 26918 /* EPNI_INDIRECT_COMMAND_WR_DATA */ "", 26919 /* EPNI_INDIRECT_FORCE_BUBBLE */ "", 26920 /* EPNI_INDIRECT_WR_MASK */ "", 26921 /* EPNI_INIT_TXI_CONFIG */ "", 26922 /* EPNI_INTERRUPT_MASK_REGISTER */ "", 26923 /* EPNI_INTERRUPT_REGISTER */ "", 26924 /* EPNI_INTERRUPT_REGISTER_TEST */ "", 26925 /* EPNI_INVALID_OUTLIF */ "", 26926 /* EPNI_IN_LIF_DP_PROFILE_MAP */ "", 26927 /* EPNI_IPV4_EXP_TO_TOS_MAP */ "", 26928 /* EPNI_IPV4_SIP */ "", 26929 /* EPNI_IPV4_SIP_ROUTING */ "", 26930 /* EPNI_IPV4_SIZE_WITH_ETH_IP_KEY */ "", 26931 /* EPNI_IPV4_SIZE_WITH_GRE_4_KEY */ "", 26932 /* EPNI_IPV4_SIZE_WITH_GRE_8_KEY */ "", 26933 /* EPNI_IPV4_TOS */ "", 26934 /* EPNI_IPV4_TOS_MODEL */ "", 26935 /* EPNI_IPV4_TOS_TO_FLAGS */ "", 26936 /* EPNI_IPV4_TTL */ "", 26937 /* EPNI_IPV4_TTL_MODEL */ "", 26938 /* EPNI_IPV4_TUNNEL_REMARK */ "", 26939 /* EPNI_IPV4_UNKNOWN_HEADER_CODE_CFG */ "", 26940 /* EPNI_IPV6_EXP_TO_TC_MAP */ "", 26941 /* EPNI_IP_PROTOCOL_CUSTOM */ "", 26942 /* EPNI_IP_PROTOCOL_GRE */ "", 26943 /* EPNI_ITAG_TC_DP_MAP */ "", 26944 /* EPNI_LBG_BYTES_COUNTER_MODEM */ "", 26945 /* EPNI_LBG_BYTES_COUNTER_MODEM_HP */ "", 26946 /* EPNI_LBG_BYTES_COUNTER_MODEM_LP */ "", 26947 /* EPNI_LBG_FIFOS_EMPTY */ "", 26948 /* EPNI_LBG_FIFO_CONFIGURATION_WRITE */ "", 26949 /* EPNI_LBG_GENERAL_CONFIGURATION */ "", 26950 /* EPNI_LBG_HEADER_CONFIGURATION */ "", 26951 /* EPNI_LBG_PACKET_COUNTER_MODEM */ "", 26952 /* EPNI_LBG_PACKET_COUNTER_MODEM_HP */ "", 26953 /* EPNI_LBG_PACKET_COUNTER_MODEM_LP */ "", 26954 /* EPNI_LBG_TC_DP_MAPPING */ "", 26955 /* EPNI_LBG_TC_DP_MAPPING_PRIORITY */ "", 26956 /* EPNI_LBG_TX_BC_PKT_COUNTER */ "", 26957 /* EPNI_LBG_TX_BC_PKT_COUNTER_0 */ "", 26958 /* EPNI_LBG_TX_BC_PKT_COUNTER_2 */ "", 26959 /* EPNI_LBG_TX_BC_PKT_COUNTER_4 */ "", 26960 /* EPNI_LBG_TX_BC_PKT_COUNTER_6 */ "", 26961 /* EPNI_LBG_TX_BC_PKT_COUNTER_8 */ "", 26962 /* EPNI_LBG_TX_BC_PKT_COUNTER_10 */ "", 26963 /* EPNI_LBG_TX_BYTES_COUNTER */ "", 26964 /* EPNI_LBG_TX_BYTES_COUNTER_0 */ "", 26965 /* EPNI_LBG_TX_BYTES_COUNTER_2 */ "", 26966 /* EPNI_LBG_TX_BYTES_COUNTER_4 */ "", 26967 /* EPNI_LBG_TX_BYTES_COUNTER_6 */ "", 26968 /* EPNI_LBG_TX_BYTES_COUNTER_8 */ "", 26969 /* EPNI_LBG_TX_BYTES_COUNTER_10 */ "", 26970 /* EPNI_LBG_TX_ERROR_PKTS_COUNTER */ "", 26971 /* EPNI_LBG_TX_MC_PKT_COUNTER */ "", 26972 /* EPNI_LBG_TX_MC_PKT_COUNTER_0 */ "", 26973 /* EPNI_LBG_TX_MC_PKT_COUNTER_2 */ "", 26974 /* EPNI_LBG_TX_MC_PKT_COUNTER_4 */ "", 26975 /* EPNI_LBG_TX_MC_PKT_COUNTER_6 */ "", 26976 /* EPNI_LBG_TX_MC_PKT_COUNTER_8 */ "", 26977 /* EPNI_LBG_TX_MC_PKT_COUNTER_10 */ "", 26978 /* EPNI_LBG_TX_PKT_1024_COUNTER */ "", 26979 /* EPNI_LBG_TX_PKT_1024_COUNTER_0 */ "", 26980 /* EPNI_LBG_TX_PKT_1024_COUNTER_2 */ "", 26981 /* EPNI_LBG_TX_PKT_1024_COUNTER_4 */ "", 26982 /* EPNI_LBG_TX_PKT_1024_COUNTER_6 */ "", 26983 /* EPNI_LBG_TX_PKT_1024_COUNTER_8 */ "", 26984 /* EPNI_LBG_TX_PKT_1024_COUNTER_10 */ "", 26985 /* EPNI_LBG_TX_PKT_128_COUNTER */ "", 26986 /* EPNI_LBG_TX_PKT_128_COUNTER_0 */ "", 26987 /* EPNI_LBG_TX_PKT_128_COUNTER_2 */ "", 26988 /* EPNI_LBG_TX_PKT_128_COUNTER_4 */ "", 26989 /* EPNI_LBG_TX_PKT_128_COUNTER_6 */ "", 26990 /* EPNI_LBG_TX_PKT_128_COUNTER_8 */ "", 26991 /* EPNI_LBG_TX_PKT_128_COUNTER_10 */ "", 26992 /* EPNI_LBG_TX_PKT_1519_COUNTER */ "", 26993 /* EPNI_LBG_TX_PKT_1519_COUNTER_0 */ "", 26994 /* EPNI_LBG_TX_PKT_1519_COUNTER_2 */ "", 26995 /* EPNI_LBG_TX_PKT_1519_COUNTER_4 */ "", 26996 /* EPNI_LBG_TX_PKT_1519_COUNTER_6 */ "", 26997 /* EPNI_LBG_TX_PKT_1519_COUNTER_8 */ "", 26998 /* EPNI_LBG_TX_PKT_1519_COUNTER_10 */ "", 26999 /* EPNI_LBG_TX_PKT_256_COUNTER */ "", 27000 /* EPNI_LBG_TX_PKT_256_COUNTER_0 */ "", 27001 /* EPNI_LBG_TX_PKT_256_COUNTER_2 */ "", 27002 /* EPNI_LBG_TX_PKT_256_COUNTER_4 */ "", 27003 /* EPNI_LBG_TX_PKT_256_COUNTER_6 */ "", 27004 /* EPNI_LBG_TX_PKT_256_COUNTER_8 */ "", 27005 /* EPNI_LBG_TX_PKT_256_COUNTER_10 */ "", 27006 /* EPNI_LBG_TX_PKT_512_COUNTER */ "", 27007 /* EPNI_LBG_TX_PKT_512_COUNTER_0 */ "", 27008 /* EPNI_LBG_TX_PKT_512_COUNTER_2 */ "", 27009 /* EPNI_LBG_TX_PKT_512_COUNTER_4 */ "", 27010 /* EPNI_LBG_TX_PKT_512_COUNTER_6 */ "", 27011 /* EPNI_LBG_TX_PKT_512_COUNTER_8 */ "", 27012 /* EPNI_LBG_TX_PKT_512_COUNTER_10 */ "", 27013 /* EPNI_LBG_TX_PKT_64_COUNTER */ "", 27014 /* EPNI_LBG_TX_PKT_64_COUNTER_0 */ "", 27015 /* EPNI_LBG_TX_PKT_64_COUNTER_2 */ "", 27016 /* EPNI_LBG_TX_PKT_64_COUNTER_4 */ "", 27017 /* EPNI_LBG_TX_PKT_64_COUNTER_6 */ "", 27018 /* EPNI_LBG_TX_PKT_64_COUNTER_8 */ "", 27019 /* EPNI_LBG_TX_PKT_64_COUNTER_10 */ "", 27020 /* EPNI_LBG_TX_PKT_65_COUNTER */ "", 27021 /* EPNI_LBG_TX_PKT_65_COUNTER_0 */ "", 27022 /* EPNI_LBG_TX_PKT_65_COUNTER_2 */ "", 27023 /* EPNI_LBG_TX_PKT_65_COUNTER_4 */ "", 27024 /* EPNI_LBG_TX_PKT_65_COUNTER_6 */ "", 27025 /* EPNI_LBG_TX_PKT_65_COUNTER_8 */ "", 27026 /* EPNI_LBG_TX_PKT_65_COUNTER_10 */ "", 27027 /* EPNI_LBG_TX_PKT_COUNTER */ "", 27028 /* EPNI_LBG_TX_PKT_COUNTER_0 */ "", 27029 /* EPNI_LBG_TX_PKT_COUNTER_2 */ "", 27030 /* EPNI_LBG_TX_PKT_COUNTER_4 */ "", 27031 /* EPNI_LBG_TX_PKT_COUNTER_6 */ "", 27032 /* EPNI_LBG_TX_PKT_COUNTER_8 */ "", 27033 /* EPNI_LBG_TX_PKT_COUNTER_10 */ "", 27034 /* EPNI_LBG_TX_UC_PKT_COUNTER */ "", 27035 /* EPNI_LBG_TX_UC_PKT_COUNTER_0 */ "", 27036 /* EPNI_LBG_TX_UC_PKT_COUNTER_2 */ "", 27037 /* EPNI_LBG_TX_UC_PKT_COUNTER_4 */ "", 27038 /* EPNI_LBG_TX_UC_PKT_COUNTER_6 */ "", 27039 /* EPNI_LBG_TX_UC_PKT_COUNTER_8 */ "", 27040 /* EPNI_LBG_TX_UC_PKT_COUNTER_10 */ "", 27041 /* EPNI_LIF_MTU */ "", 27042 /* EPNI_LIF_MTU_PROFILE_MAPPING */ "", 27043 /* EPNI_LINK_FILTER_ENABLE */ "", 27044 /* EPNI_MAC_IN_MAC_ROO_FIX_ENABLED */ "", 27045 /* EPNI_MAPPING_RECYCLE_TRAFFICTO_INGRESS_PIPE */ "", 27046 /* EPNI_MAP_FLEXIBLE_UDH_TYPE_TO_SIZE */ "", 27047 /* EPNI_MASK_CHECK_BW_TO_PACKET_DESCRIPTOR */ "", 27048 /* EPNI_MEF_L_2_CP_TRANSPARANT_BITMAP */ "", 27049 /* EPNI_MIRROED_TRAFFIC_SHAPER_CONFIGURATION */ "", 27050 /* EPNI_MIRRORED_PACKETS_COUNTER_CONFIGURATION */ "", 27051 /* EPNI_MIRROR_CHANNEL */ "", 27052 /* EPNI_MIRROR_VID_REG */ "", 27053 /* EPNI_MIRR_AND_TRAP_FIFO_CONFIGURATION */ "", 27054 /* EPNI_MIRR_FIFO_CONFIGURATION */ "", 27055 /* EPNI_MPLS_BOS_PER_HEADER_CODE */ "", 27056 /* EPNI_MPLS_CONTROL_WORD */ "", 27057 /* EPNI_MPLS_OUTLIF_PROFILE_PUSH_TO_SWAP_ENABLED */ "", 27058 /* EPNI_MTU */ "", 27059 /* EPNI_MY_MAC */ "", 27060 /* EPNI_NATIVE_PCP_DEI_PROFILE */ "", 27061 /* EPNI_NETWORK_HEADERS_VALUE_1_OFFSET */ "", 27062 /* EPNI_NETWORK_HEADERS_VALUE_2_OFFSET */ "", 27063 /* EPNI_NEW_LLNK_PCP_DEI_PROFILE */ "", 27064 /* EPNI_OAM_INVALID_LIF */ "", 27065 /* EPNI_OAM_PROCESS_MAP */ "", 27066 /* EPNI_OUTLIF_MSB_MAPPED */ "", 27067 /* EPNI_OUTLIF_MSB_MAPPED_SHIFT */ "", 27068 /* EPNI_OUTRIF_MAX_VALUE */ "", 27069 /* EPNI_PACKET_HAS_OUTER_VID */ "", 27070 /* EPNI_PACKET_IS_TAGGED_AFTER_EVE_1 */ "", 27071 /* EPNI_PACKET_IS_TAGGED_AFTER_EVE_2 */ "", 27072 /* EPNI_PACKET_IS_TAGGED_AFTER_EVE_3 */ "", 27073 /* EPNI_PACKET_IS_TAGGED_AFTER_EVE_4 */ "", 27074 /* EPNI_PACKET_LATENCY_MEASUREMENT_CFG */ "", 27075 /* EPNI_PARITY_ERR_CNT */ "", 27076 /* EPNI_PAR_ERR_INITIATE */ "", 27077 /* EPNI_PAR_ERR_MEM_MASK */ "", 27078 /* EPNI_PCMI_0 */ "", 27079 /* EPNI_PCMI_1 */ "", 27080 /* EPNI_PCMI_2 */ "", 27081 /* EPNI_PCMI_3 */ "", 27082 /* EPNI_PCMI_4 */ "", 27083 /* EPNI_PCMI_0_S */ "", 27084 /* EPNI_PCMI_0_T */ "", 27085 /* EPNI_PCMI_1_S */ "", 27086 /* EPNI_PCMI_1_T */ "", 27087 /* EPNI_PCMI_2_S */ "", 27088 /* EPNI_PCMI_2_T */ "", 27089 /* EPNI_PCMI_3_S */ "", 27090 /* EPNI_PCMI_3_T */ "", 27091 /* EPNI_PCMI_4_S */ "", 27092 /* EPNI_PCMI_4_T */ "", 27093 /* EPNI_PCP_DEI_PROFILE */ "", 27094 /* EPNI_PER_LBG_MODEM_SEQ_MAX_VALUE */ "", 27095 /* EPNI_PER_LBG_SEQ_MAX_VALUE */ "", 27096 /* EPNI_PETRAB_EEI */ "", 27097 /* EPNI_PETRAB_EEI_MPLS_MAP */ "", 27098 /* EPNI_PETRAB_FHEI_SIZE_MAP */ "", 27099 /* EPNI_PETRAB_LEARN_ASD_TYPE_MAP */ "", 27100 /* EPNI_PMC_PARITY_EN */ "", 27101 /* EPNI_PP_CONFIG */ "", 27102 /* EPNI_PP_INT_REG */ "", 27103 /* EPNI_PP_INT_REG_MASK */ "", 27104 /* EPNI_PP_INT_REG_TEST */ "", 27105 /* EPNI_PRGE_MIRROR_TRAP_EN */ "", 27106 /* EPNI_RECYCLE_ARBITER_CONFIGURATION */ "", 27107 /* EPNI_RECYLED_TRAFFIC_SHAPER_CONFIGURATION */ "", 27108 /* EPNI_REG_0041 */ "", 27109 /* EPNI_REG_0085 */ "", 27110 /* EPNI_REG_0090 */ "", 27111 /* EPNI_REG_0091 */ "", 27112 /* EPNI_REG_0092 */ "", 27113 /* EPNI_REG_0093 */ "", 27114 /* EPNI_REG_0098 */ "", 27115 /* EPNI_REG_0103 */ "", 27116 /* EPNI_REG_0117 */ "", 27117 /* EPNI_REG_0129 */ "", 27118 /* EPNI_REG_0201 */ "", 27119 /* EPNI_REG_0203 */ "", 27120 /* EPNI_REG_0205 */ "", 27121 /* EPNI_REG_0207 */ "", 27122 /* EPNI_REG_0215 */ "", 27123 /* EPNI_REG_0217 */ "", 27124 /* EPNI_REG_0219 */ "", 27125 /* EPNI_REG_0220 */ "", 27126 /* EPNI_REG_0231 */ "", 27127 /* EPNI_REG_0233 */ "", 27128 /* EPNI_REG_0235 */ "", 27129 /* EPNI_REG_0237 */ "", 27130 /* EPNI_REG_0239 */ "", 27131 /* EPNI_REG_0247 */ "", 27132 /* EPNI_REG_0249 */ "", 27133 /* EPNI_REG_0251 */ "", 27134 /* EPNI_REG_0261 */ "", 27135 /* EPNI_REG_0263 */ "", 27136 /* EPNI_REG_0265 */ "", 27137 /* EPNI_REG_0267 */ "", 27138 /* EPNI_REG_0269 */ "", 27139 /* EPNI_REG_0277 */ "", 27140 /* EPNI_REG_0279 */ "", 27141 /* EPNI_REG_0281 */ "", 27142 /* EPNI_REG_0291 */ "", 27143 /* EPNI_REG_0293 */ "", 27144 /* EPNI_REG_0295 */ "", 27145 /* EPNI_REG_0297 */ "", 27146 /* EPNI_REG_0299 */ "", 27147 /* EPNI_REG_0303 */ "", 27148 /* EPNI_REG_0500 */ "", 27149 /* EPNI_REG_0600 */ "", 27150 /* EPNI_REG_0700 */ "", 27151 /* EPNI_REG_0701 */ "", 27152 /* EPNI_REG_0702 */ "", 27153 /* EPNI_REG_00A0 */ "", 27154 /* EPNI_REG_00A4 */ "", 27155 /* EPNI_REG_00A6 */ "", 27156 /* EPNI_REG_00AA */ "", 27157 /* EPNI_REG_00AE */ "", 27158 /* EPNI_REG_00AF */ "", 27159 /* EPNI_REG_00C1 */ "", 27160 /* EPNI_REG_00C2 */ "", 27161 /* EPNI_REG_00C5 */ "", 27162 /* EPNI_REG_00CF */ "", 27163 /* EPNI_REG_00D0 */ "", 27164 /* EPNI_REG_00D2 */ "", 27165 /* EPNI_REG_00D3 */ "", 27166 /* EPNI_REG_00D4 */ "", 27167 /* EPNI_REG_00D5 */ "", 27168 /* EPNI_REG_00D6 */ "", 27169 /* EPNI_REG_00DA */ "", 27170 /* EPNI_REG_00DC */ "", 27171 /* EPNI_REG_011B */ "", 27172 /* EPNI_REG_012A */ "", 27173 /* EPNI_REG_012D */ "", 27174 /* EPNI_REG_012E */ "", 27175 /* EPNI_REG_018C */ "", 27176 /* EPNI_REG_01A1 */ "", 27177 /* EPNI_REG_01AC */ "", 27178 /* EPNI_REG_01AF */ "", 27179 /* EPNI_REG_01CD */ "", 27180 /* EPNI_REG_01CF */ "", 27181 /* EPNI_REG_01D1 */ "", 27182 /* EPNI_REG_01D3 */ "", 27183 /* EPNI_REG_01D5 */ "", 27184 /* EPNI_REG_01D7 */ "", 27185 /* EPNI_REG_01E5 */ "", 27186 /* EPNI_REG_01E7 */ "", 27187 /* EPNI_REG_01E9 */ "", 27188 /* EPNI_REG_01EB */ "", 27189 /* EPNI_REG_01ED */ "", 27190 /* EPNI_REG_01EF */ "", 27191 /* EPNI_REG_01FD */ "", 27192 /* EPNI_REG_01FF */ "", 27193 /* EPNI_REG_021B */ "", 27194 /* EPNI_REG_021D */ "", 27195 /* EPNI_REG_021F */ "", 27196 /* EPNI_REG_022F */ "", 27197 /* EPNI_REG_024B */ "", 27198 /* EPNI_REG_024D */ "", 27199 /* EPNI_REG_024F */ "", 27200 /* EPNI_REG_025F */ "", 27201 /* EPNI_REG_027B */ "", 27202 /* EPNI_REG_027D */ "", 27203 /* EPNI_REG_027F */ "", 27204 /* EPNI_REG_028F */ "", 27205 /* EPNI_REG_02A7 */ "", 27206 /* EPNI_REG_02A9 */ "", 27207 /* EPNI_REG_02AB */ "", 27208 /* EPNI_REG_02AD */ "", 27209 /* EPNI_REG_02AF */ "", 27210 /* EPNI_REG_02B1 */ "", 27211 /* EPNI_REG_02BF */ "", 27212 /* EPNI_REG_02C1 */ "", 27213 /* EPNI_REG_02C3 */ "", 27214 /* EPNI_REG_02C5 */ "", 27215 /* EPNI_REG_02C7 */ "", 27216 /* EPNI_REG_02C9 */ "", 27217 /* EPNI_REG_02D7 */ "", 27218 /* EPNI_REG_02D9 */ "", 27219 /* EPNI_REG_02DB */ "", 27220 /* EPNI_REG_02DD */ "", 27221 /* EPNI_REG_02DF */ "", 27222 /* EPNI_REG_02E1 */ "", 27223 /* EPNI_REG_02E2 */ "", 27224 /* EPNI_REMARK_PROFILE_CONFIGURATION */ "", 27225 /* EPNI_RESERVED_MIRROR_ADDR */ "", 27226 /* EPNI_RESERVED_MTCD */ "", 27227 /* EPNI_RESERVED_MTCP */ "", 27228 /* EPNI_RESERVED_PCMI_0 */ "", 27229 /* EPNI_RESERVED_PCMI_1 */ "", 27230 /* EPNI_RESERVED_PCMI_2 */ "", 27231 /* EPNI_RESERVED_PCMI_3 */ "", 27232 /* EPNI_RESERVED_PCMI_4 */ "", 27233 /* EPNI_RESERVED_PCMI_0_S */ "", 27234 /* EPNI_RESERVED_PCMI_0_T */ "", 27235 /* EPNI_RESERVED_PCMI_1_S */ "", 27236 /* EPNI_RESERVED_PCMI_1_T */ "", 27237 /* EPNI_RESERVED_PCMI_2_S */ "", 27238 /* EPNI_RESERVED_PCMI_2_T */ "", 27239 /* EPNI_RESERVED_PCMI_3_S */ "", 27240 /* EPNI_RESERVED_PCMI_3_T */ "", 27241 /* EPNI_RESERVED_PCMI_4_S */ "", 27242 /* EPNI_RESERVED_PCMI_4_T */ "", 27243 /* EPNI_RESERVED_SPARE_0 */ "", 27244 /* EPNI_RESERVED_SPARE_1 */ "", 27245 /* EPNI_RESERVED_SPARE_2 */ "", 27246 /* EPNI_RESERVED_SPARE_3 */ "", 27247 /* EPNI_ROO_NEW_LINK_OUTER_VID_ENABLED */ "", 27248 /* EPNI_SBUS_BROADCAST_ID */ "", 27249 /* EPNI_SBUS_LAST_IN_CHAIN */ "", 27250 /* EPNI_SET_SEQUENCE_NUMBER */ "", 27251 /* EPNI_SPECIAL_IFS_TXI_IRDY_UNSET */ "", 27252 /* EPNI_STATISTICS_REPORTING_CONFIGURATION */ "", 27253 /* EPNI_SYSTEM_HEADERS_FORMAT_CODE */ "", 27254 /* EPNI_SYSTEM_HEADERS_VALUE_1_OFFSET */ "", 27255 /* EPNI_SYSTEM_HEADERS_VALUE_2_OFFSET */ "", 27256 /* EPNI_TC_DP_MAP_PORT_FIX_ENABLED */ "", 27257 /* EPNI_TDM_EN_CRC_PER_PORT */ "", 27258 /* EPNI_TDM_EPE_CONFIGURATION */ "", 27259 /* EPNI_TERMINATE_HEADER */ "", 27260 /* EPNI_TPID_PROFILES */ "", 27261 /* EPNI_TRAP_TRAFFIC_SHAPER_CONFIGURATION */ "", 27262 /* EPNI_TRILL_CONFIG */ "", 27263 /* EPNI_TTL_DECREMENT_ENABLE */ "", 27264 /* EPNI_USE_PROTECTION_AS_DATA_PER_BANK */ "", 27265 /* EPOST_HW_STATUS */ "", 27266 /* EPOST_HW_STATUS_PIPE0 */ "", 27267 /* EPOST_HW_STATUS_PIPE1 */ "", 27268 /* EPOST_HW_STATUS_PIPE2 */ "", 27269 /* EPOST_HW_STATUS_PIPE3 */ "", 27270 /* EPOST_HW_STATUS_PIPE4 */ "", 27271 /* EPOST_HW_STATUS_PIPE5 */ "", 27272 /* EPOST_HW_STATUS_PIPE6 */ "", 27273 /* EPOST_HW_STATUS_PIPE7 */ "", 27274 /* EPOST_SER_CONTROL */ "", 27275 /* EPOST_SLOT_PIPELINE_CONFIG */ "", 27276 /* EPRE_DISABLE_INTERFACES */ "", 27277 /* EPRE_ECC_1B_ERR_CNT */ "", 27278 /* EPRE_ECC_2B_ERR_CNT */ "", 27279 /* EPRE_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 27280 /* EPRE_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 27281 /* EPRE_ECC_INTERRUPT_REGISTER */ "", 27282 /* EPRE_ECC_INTERRUPT_REGISTER_MASK */ "", 27283 /* EPRE_ECC_INTERRUPT_REGISTER_TEST */ "", 27284 /* EPRE_EPRE_FIFO_WATERMARKS */ "", 27285 /* EPRE_ERROR_INITIATION_DATA */ "", 27286 /* EPRE_GTIMER_CONFIGURATION */ "", 27287 /* EPRE_GTIMER_CYCLE */ "", 27288 /* EPRE_HP_MIRR_TRAFFIC_SHAPER_CONFIGURATION */ "", 27289 /* EPRE_IFC_TXI_IRDY_UNSET */ "", 27290 /* EPRE_INTERRUPT_MASK_REGISTER */ "", 27291 /* EPRE_INTERRUPT_REGISTER */ "", 27292 /* EPRE_INTERRUPT_REGISTER_TEST */ "", 27293 /* EPRE_IRE_RECYCLE_ARBITER_CONFIGURATION */ "", 27294 /* EPRE_MIRR_FIFO_CONFIGURATION */ "", 27295 /* EPRE_PCMI_0 */ "", 27296 /* EPRE_PCMI_1 */ "", 27297 /* EPRE_PCMI_2 */ "", 27298 /* EPRE_PCMI_3 */ "", 27299 /* EPRE_PCMI_4 */ "", 27300 /* EPRE_PCMI_0_S */ "", 27301 /* EPRE_PCMI_0_T */ "", 27302 /* EPRE_PCMI_1_S */ "", 27303 /* EPRE_PCMI_1_T */ "", 27304 /* EPRE_PCMI_2_S */ "", 27305 /* EPRE_PCMI_2_T */ "", 27306 /* EPRE_PCMI_3_S */ "", 27307 /* EPRE_PCMI_3_T */ "", 27308 /* EPRE_PCMI_4_S */ "", 27309 /* EPRE_PCMI_4_T */ "", 27310 /* EPRE_RECYLED_TRAFFIC_SHAPER_CONFIGURATION */ "", 27311 /* EPRE_REG_0098 */ "", 27312 /* EPRE_REG_00A0 */ "", 27313 /* EPRE_REG_00A4 */ "", 27314 /* EPRE_REG_00A6 */ "", 27315 /* EPRE_REG_00AA */ "", 27316 /* EPRE_REG_00C2 */ "", 27317 /* EPRE_REG_00C5 */ "", 27318 /* EPRE_RESERVED_MIRROR_ADDR */ "", 27319 /* EPRE_RESERVED_MTCD */ "", 27320 /* EPRE_RESERVED_MTCP */ "", 27321 /* EPRE_RESERVED_SPARE_0 */ "", 27322 /* EPRE_RESERVED_SPARE_1 */ "", 27323 /* EPRE_RESERVED_SPARE_2 */ "", 27324 /* EPRE_RESERVED_SPARE_3 */ "", 27325 /* EPRE_SBUS_BROADCAST_ID */ "", 27326 /* EPRE_SBUS_LAST_IN_CHAIN */ "", 27327 /* EPS_ACC_MAX_CREDIT */ "", 27328 /* EPS_ECC_1B_ERR_CNT */ "", 27329 /* EPS_ECC_2B_ERR_CNT */ "", 27330 /* EPS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 27331 /* EPS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 27332 /* EPS_ECC_INTERRUPT_REGISTER */ "", 27333 /* EPS_ECC_INTERRUPT_REGISTER_MASK */ "", 27334 /* EPS_ECC_INTERRUPT_REGISTER_TEST */ "", 27335 /* EPS_EGRESS_CALENDAR_SHAPER_SETTINGS */ "", 27336 /* EPS_EGRESS_SHAPER_ENABLE_SETTINGS */ "", 27337 /* EPS_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 27338 /* EPS_EPS_CANCEL_CNT */ "", 27339 /* EPS_EPS_CANCEL_STATUS */ "", 27340 /* EPS_EPS_GENERAL_CFG */ "", 27341 /* EPS_EPS_PRIO_PROG_MIS_MATCH_CNT */ "", 27342 /* EPS_EPS_SPR_INIT_STAT */ "", 27343 /* EPS_EPS_WFQ_CNT_NEG_STAT */ "", 27344 /* EPS_ERROR_INITIATION_DATA */ "", 27345 /* EPS_GTIMER_CONFIGURATION */ "", 27346 /* EPS_GTIMER_CYCLE */ "", 27347 /* EPS_HEADER_CMPNS_EN */ "", 27348 /* EPS_IFC_OK_DEQ */ "", 27349 /* EPS_INDIRECT_COMMAND */ "", 27350 /* EPS_INDIRECT_COMMAND_ADDRESS */ "", 27351 /* EPS_INDIRECT_COMMAND_RD_DATA */ "", 27352 /* EPS_INDIRECT_COMMAND_WR_DATA */ "", 27353 /* EPS_INDIRECT_FORCE_BUBBLE */ "", 27354 /* EPS_INTERRUPT_MASK_REGISTER */ "", 27355 /* EPS_INTERRUPT_REGISTER */ "", 27356 /* EPS_INTERRUPT_REGISTER_TEST */ "", 27357 /* EPS_PORT_MAX_CREDIT_VALUE */ "", 27358 /* EPS_PORT_SCH_WFQ_PACKET_SIZE */ "", 27359 /* EPS_PQP_CALENDAR_SETTING */ "", 27360 /* EPS_PS_MODE */ "", 27361 /* EPS_QP_MAX_CREDIT_VALUE */ "", 27362 /* EPS_REG_0041 */ "", 27363 /* EPS_REG_0098 */ "", 27364 /* EPS_REG_00A0 */ "", 27365 /* EPS_REG_00A4 */ "", 27366 /* EPS_REG_00A6 */ "", 27367 /* EPS_REG_00AA */ "", 27368 /* EPS_REG_00C2 */ "", 27369 /* EPS_RESERVED_MIRROR_ADDR */ "", 27370 /* EPS_RESERVED_MTCD */ "", 27371 /* EPS_RESERVED_MTCP */ "", 27372 /* EPS_RESERVED_SPARE_0 */ "", 27373 /* EPS_RESERVED_SPARE_1 */ "", 27374 /* EPS_RESERVED_SPARE_2 */ "", 27375 /* EPS_RESERVED_SPARE_3 */ "", 27376 /* EPS_SBUS_BROADCAST_ID */ "", 27377 /* EPS_SBUS_LAST_IN_CHAIN */ "", 27378 /* EPS_SPECIAL_CLOCK_CONTROLS */ "", 27379 /* EPS_TCG_MAX_CREDIT_VALUE */ "", 27380 /* EPS_UC_MC_WFQ_PACKET_SIZE */ "", 27381 /* EP_BISR */ "", 27382 /* EP_DATAPATH_INTR_ENABLE */ "", 27383 /* EP_EDB_MISC_CONTROL */ "", 27384 /* EP_INTR0_ENABLE */ "", 27385 /* EP_INTR0_STATUS */ "", 27386 /* EP_INTR1_ENABLE */ "", 27387 /* EP_INTR1_STATUS */ "", 27388 /* EP_INTR_ENABLE */ "", 27389 /* EP_INTR_STATUS */ "", 27390 /* EP_NUM_NORM_CELLS_RECVD */ "", 27391 /* EP_NUM_NORM_PKTS_DROPPED */ "", 27392 /* EP_NUM_NORM_PKTS_RECVD */ "", 27393 /* EP_NUM_UNMOD_CELLS_RECVD */ "", 27394 /* EP_NUM_UNMOD_PKTS_DROPPED */ "", 27395 /* EP_NUM_UNMOD_PKTS_RECVD */ "", 27396 /* EP_PARITY_INTR_STATUS */ "", 27397 /* EP_PARSER0_HFE_SER_CONTROL */ "", 27398 /* EP_PARSER0_HFE_STAGE_TM_CONTROL_0 */ "", 27399 /* EP_PARSER0_HFE_STAGE_TM_CONTROL_0_PIPE0 */ "", 27400 /* EP_PARSER0_HFE_STAGE_TM_CONTROL_0_PIPE1 */ "", 27401 /* EP_PARSER1_HFE_SER_CONTROL */ "", 27402 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_0 */ "", 27403 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_1 */ "", 27404 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_2 */ "", 27405 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_3 */ "", 27406 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_0_PIPE0 */ "", 27407 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_0_PIPE1 */ "", 27408 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_1_PIPE0 */ "", 27409 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_1_PIPE1 */ "", 27410 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_2_PIPE0 */ "", 27411 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_2_PIPE1 */ "", 27412 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_3_PIPE0 */ "", 27413 /* EP_PARSER1_HFE_STAGE_TM_CONTROL_3_PIPE1 */ "", 27414 /* EP_REDIR_CONTROL */ "", 27415 /* ERBFIFO_STATUS */ "", 27416 /* ERB_CTL */ "", 27417 /* ERB_INTR_CLEAR */ "", 27418 /* ERB_INTR_ENABLE */ "", 27419 /* ERB_INTR_STATUS */ "", 27420 /* ERB_IPCF_PTR_MISMATCH_INFO */ "", 27421 /* ERPP_ACTION_DISABLE */ "", 27422 /* ERPP_ACTION_PROFILE_1 */ "", 27423 /* ERPP_ACTION_PROFILE_2 */ "", 27424 /* ERPP_CFG_ETHERNET_FWD_CONTEXT */ "", 27425 /* ERPP_CFG_EXCLUDE_SOURCE_MAPPED */ "", 27426 /* ERPP_CFG_FHEI_MODEL */ "", 27427 /* ERPP_CFG_FILTER_FORWARDING_STRENGTH_1 */ "", 27428 /* ERPP_CFG_FILTER_FORWARDING_STRENGTH_2 */ "", 27429 /* ERPP_CFG_FILTER_FORWARDING_STRENGTH_3 */ "", 27430 /* ERPP_CFG_FILTER_SNOOP_STRENGTH_1 */ "", 27431 /* ERPP_CFG_FILTER_SNOOP_STRENGTH_2 */ "", 27432 /* ERPP_CFG_FILTER_SNOOP_STRENGTH_3 */ "", 27433 /* ERPP_CFG_GLEM_VALID_AND_NOT_FOUND */ "", 27434 /* ERPP_CFG_IPV4_MC_FWD_CONTEXT */ "", 27435 /* ERPP_CFG_IPV4_UC_FWD_CONTEXT */ "", 27436 /* ERPP_CFG_IPV6_MC_FWD_CONTEXT */ "", 27437 /* ERPP_CFG_IPV6_UC_FWD_CONTEXT */ "", 27438 /* ERPP_CFG_LEARN_EN_PER_FWD_CONTEXT */ "", 27439 /* ERPP_CFG_LOCAL_OUTLIF_WIDTH */ "", 27440 /* ERPP_CFG_MAP_FORWARD_STRENGTH_TO_STRENGTH */ "", 27441 /* ERPP_CFG_OPP_LEARNING_DISABLE */ "", 27442 /* ERPP_CFG_OTM_LEARNING_DISABLE */ "", 27443 /* ERPP_CFG_OUTLIF_PROFILE_WIDTH */ "", 27444 /* ERPP_CFG_OUTRIF_MAX_VALUE */ "", 27445 /* ERPP_CFG_PROTOCOL_IS_TCP */ "", 27446 /* ERPP_CFG_PROTOCOL_IS_UDP */ "", 27447 /* ERPP_CFG_RIF_IN_STACK */ "", 27448 /* ERPP_CFG_SPLIT_HORIZON_FILTER */ "", 27449 /* ERPP_CFG_TDM_MAP_QUEUE_TO_TDM */ "", 27450 /* ERPP_COLLECTOR_VIS_EN */ "", 27451 /* ERPP_COUNTER */ "", 27452 /* ERPP_DBG_LAST_FES */ "", 27453 /* ERPP_DBG_LAST_FES_NUM */ "", 27454 /* ERPP_DEVICE_CFG_BTR */ "", 27455 /* ERPP_DEVICE_CFG_JR_COMPATIBILITY_APP_DB_INDEX */ "", 27456 /* ERPP_DEVICE_CFG_PARSER_ENABLERS */ "", 27457 /* ERPP_DEVICE_CFG_POP_SIZE_IN_BYTES */ "", 27458 /* ERPP_DEVICE_CFG_REMARK_PROFILE */ "", 27459 /* ERPP_ECC_1B_ERR_CNT */ "", 27460 /* ERPP_ECC_2B_ERR_CNT */ "", 27461 /* ERPP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 27462 /* ERPP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 27463 /* ERPP_ECC_INTERRUPT_REGISTER */ "", 27464 /* ERPP_ECC_INTERRUPT_REGISTER_MASK */ "", 27465 /* ERPP_ECC_INTERRUPT_REGISTER_TEST */ "", 27466 /* ERPP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 27467 /* ERPP_EPMFCS_TCAM_ECC_FIX_EN */ "", 27468 /* ERPP_EPMFCS_TCAM_PROTECTION_ERROR */ "", 27469 /* ERPP_EPMFCS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 27470 /* ERPP_EPMFCS_TCAM_RESET_BLOCK */ "", 27471 /* ERPP_ERPP_DISCARDS_INTERRUPT_REGISTER_MASK */ "", 27472 /* ERPP_ERPP_DISCARDS_INTERRUPT_REGISTER_MASK_2 */ "", 27473 /* ERPP_ERPP_DISCARD_INTERRUPT_REGISTER */ "", 27474 /* ERPP_ERPP_DISCARD_INTERRUPT_REGISTER_2 */ "", 27475 /* ERPP_ERPP_DISCARD_INT_REG_2_TEST */ "", 27476 /* ERPP_ERPP_DISCARD_INT_REG_TEST */ "", 27477 /* ERPP_ERROR_INITIATION_DATA */ "", 27478 /* ERPP_FHEI_MPLS_COMMAND */ "", 27479 /* ERPP_FIFO_ALMOST_FULL_THRESHOLD */ "", 27480 /* ERPP_FWD_CONTEXT_IS_PP */ "", 27481 /* ERPP_FWD_LAYER_ADDITIONAL_INFO_TO_IP_MC_ELIGIBLE_MAPPING */ "", 27482 /* ERPP_GLOBAL_CONFIG */ "", 27483 /* ERPP_GTIMER_CONFIGURATION */ "", 27484 /* ERPP_GTIMER_CYCLE */ "", 27485 /* ERPP_INDIRECT_COMMAND */ "", 27486 /* ERPP_INDIRECT_COMMAND_ADDRESS */ "", 27487 /* ERPP_INDIRECT_COMMAND_RD_DATA */ "", 27488 /* ERPP_INDIRECT_COMMAND_WIDE_MEM */ "", 27489 /* ERPP_INDIRECT_COMMAND_WR_DATA */ "", 27490 /* ERPP_INDIRECT_FORCE_BUBBLE */ "", 27491 /* ERPP_INDIRECT_WR_MASK */ "", 27492 /* ERPP_INGRESS_TRAPPED_BY_FHEI */ "", 27493 /* ERPP_INTERRUPT_MASK_REGISTER */ "", 27494 /* ERPP_INTERRUPT_REGISTER */ "", 27495 /* ERPP_INTERRUPT_REGISTER_TEST */ "", 27496 /* ERPP_INVALID_OTM */ "", 27497 /* ERPP_JERICHO_COMPATIBLE_REGISTERS */ "", 27498 /* ERPP_LAG_FILTER_ENABLE */ "", 27499 /* ERPP_LEARN_CMD_DESTINATION_OFFSET */ "", 27500 /* ERPP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_ENTRY_FORMAT_INDEX */ "", 27501 /* ERPP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUE */ "", 27502 /* ERPP_LEARN_CMD_EEI_OFFSET */ "", 27503 /* ERPP_LEARN_CMD_FEC_OFFSET */ "", 27504 /* ERPP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_ENTRY_FORMAT_INDEX */ "", 27505 /* ERPP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUE */ "", 27506 /* ERPP_LEARN_CMD_OUT_LIF_OFFSET */ "", 27507 /* ERPP_NUM_ENTRIES_NETWORK_HEADERS_FIFO */ "", 27508 /* ERPP_NUM_ENTRIES_PMF_INITIAL_ACTIONS_FIFO */ "", 27509 /* ERPP_NUM_ENTRIES_PRP_SAVE_NETWORK_HEADER_FIFO */ "", 27510 /* ERPP_NUM_ENTRIES_PRP_WAIT_FOR_GLEM_FIFO */ "", 27511 /* ERPP_NUM_ENTRIES_PRP_WAIT_FOR_NETWORK_HEADER_FIFO */ "", 27512 /* ERPP_NUM_ENTRIES_SYSTEM_HEADERS_CONTAINER_FIFO */ "", 27513 /* ERPP_NUM_ENTRIES_TM_DATA_BYPASS_FIFO */ "", 27514 /* ERPP_NUM_ENTRIES_TM_FIELDS_FIFO */ "", 27515 /* ERPP_PARITY_ERR_CNT */ "", 27516 /* ERPP_PARSER_FIFO_ALMOST_FULL_THRESHOLD */ "", 27517 /* ERPP_PAR_ERR_MEM_MASK */ "", 27518 /* ERPP_PCMI_0 */ "", 27519 /* ERPP_PCMI_1 */ "", 27520 /* ERPP_PCMI_2 */ "", 27521 /* ERPP_PCMI_3 */ "", 27522 /* ERPP_PCMI_4 */ "", 27523 /* ERPP_PCMI_0_S */ "", 27524 /* ERPP_PCMI_0_T */ "", 27525 /* ERPP_PCMI_1_S */ "", 27526 /* ERPP_PCMI_1_T */ "", 27527 /* ERPP_PCMI_2_S */ "", 27528 /* ERPP_PCMI_2_T */ "", 27529 /* ERPP_PCMI_3_S */ "", 27530 /* ERPP_PCMI_3_T */ "", 27531 /* ERPP_PCMI_4_S */ "", 27532 /* ERPP_PCMI_4_T */ "", 27533 /* ERPP_PMF_DEFAULT_ACTIONS */ "", 27534 /* ERPP_PMF_PRTOCOL_IS_L_4 */ "", 27535 /* ERPP_PORT_VISIBILITY_EN */ "", 27536 /* ERPP_PORT_VISIBILITY_FORCE */ "", 27537 /* ERPP_PPH_BASE_FIELDS_CG_2 */ "", 27538 /* ERPP_PP_CONFIG */ "", 27539 /* ERPP_REG_0400 */ "", 27540 /* ERPP_REG_0405 */ "", 27541 /* ERPP_REG_0413 */ "", 27542 /* ERPP_REG_0553 */ "", 27543 /* ERPP_REG_0602 */ "", 27544 /* ERPP_REG_1004 */ "", 27545 /* ERPP_REG_1007 */ "", 27546 /* ERPP_REG_1009 */ "", 27547 /* ERPP_REG_00A4 */ "", 27548 /* ERPP_REG_00A6 */ "", 27549 /* ERPP_REG_00AA */ "", 27550 /* ERPP_REG_00C2 */ "", 27551 /* ERPP_REG_00C5 */ "", 27552 /* ERPP_REG_00C6 */ "", 27553 /* ERPP_REG_00E8 */ "", 27554 /* ERPP_REG_00E9 */ "", 27555 /* ERPP_REG_00EB */ "", 27556 /* ERPP_REG_00ED */ "", 27557 /* ERPP_REG_00EE */ "", 27558 /* ERPP_REG_00F0 */ "", 27559 /* ERPP_REG_00F1 */ "", 27560 /* ERPP_REG_00F2 */ "", 27561 /* ERPP_REG_040D */ "", 27562 /* ERPP_REG_040E */ "", 27563 /* ERPP_REG_040F */ "", 27564 /* ERPP_REG_F000 */ "", 27565 /* ERPP_RESERVED_MIRROR_ADDR */ "", 27566 /* ERPP_RESERVED_MTCD */ "", 27567 /* ERPP_RESERVED_MTCP */ "", 27568 /* ERPP_RESERVED_SPARE_0 */ "", 27569 /* ERPP_RESERVED_SPARE_1 */ "", 27570 /* ERPP_RESERVED_SPARE_2 */ "", 27571 /* ERPP_RESERVED_SPARE_3 */ "", 27572 /* ERPP_SBUS_BROADCAST_ID */ "", 27573 /* ERPP_SBUS_LAST_IN_CHAIN */ "", 27574 /* ERPP_SER_ACTION_RESOLUTION */ "", 27575 /* ERPP_STAT_VISIBILITY */ "", 27576 /* ERPP_SYSTEM_HEADERS_CG_1 */ "", 27577 /* ERPP_TDM_GENERAL_CONFIGURATION */ "", 27578 /* ERPP_TM_SPARE_BITS */ "", 27579 /* ERPP_TTL_SCOPE */ "", 27580 /* ERPP_UTILITY_REGS */ "", 27581 /* ERROR_CCM_DEFECT_STATUS */ "", 27582 /* ERR_PKT_CNT */ "", 27583 /* ES01C_ERB_CTL */ "", 27584 /* ES01C_EXTFP_POLICY_DED_INFO */ "", 27585 /* ES01C_EXTFP_POLICY_SEC_INFO */ "", 27586 /* ES01C_FP0RSPFIFO_RS_CTL */ "", 27587 /* ES01C_FP0RSPFIFO_RS_STATUS */ "", 27588 /* ES01C_FP1RSPFIFO_RS_CTL */ "", 27589 /* ES01C_FP1RSPFIFO_RS_STATUS */ "", 27590 /* ES01C_FPCREQFIFO_WS_STATUS */ "", 27591 /* ES01C_INTR_CLEAR */ "", 27592 /* ES01C_INTR_ENABLE */ "", 27593 /* ES01C_INTR_STATUS */ "", 27594 /* ES01C_L2L3RSPFIFO_RS_CTL */ "", 27595 /* ES01C_L2L3RSPFIFO_RS_STATUS */ "", 27596 /* ES01_ADFPCNTR_DED_INFO */ "", 27597 /* ES01_ADFPCNTR_SEC_INFO */ "", 27598 /* ES01_ADL2DST_DED_INFO */ "", 27599 /* ES01_ADL2DST_SEC_INFO */ "", 27600 /* ES01_ADL2SRC_DED_INFO */ "", 27601 /* ES01_ADL2SRC_SEC_INFO */ "", 27602 /* ES01_ADL3DST_DED_INFO */ "", 27603 /* ES01_ADL3DST_SEC_INFO */ "", 27604 /* ES01_ADL3SRC_DED_INFO */ "", 27605 /* ES01_ADL3SRC_SEC_INFO */ "", 27606 /* ES01_ADREQ0FIFO_RS_CTL */ "", 27607 /* ES01_ADREQ0FIFO_RS_STATUS */ "", 27608 /* ES01_ADREQ1FIFO_RS_CTL */ "", 27609 /* ES01_ADREQ1FIFO_RS_STATUS */ "", 27610 /* ES01_BYT_CNT_WRAP_INFO */ "", 27611 /* ES01_INTR_CLEAR */ "", 27612 /* ES01_INTR_ENABLE */ "", 27613 /* ES01_INTR_STATUS */ "", 27614 /* ES01_MISC_CTL */ "", 27615 /* ES01_MISC_STATUS */ "", 27616 /* ES01_PKT_CNT_WRAP_INFO */ "", 27617 /* ES0_DDR36_CONFIG_REG1_IS */ "", 27618 /* ES0_DDR36_CONFIG_REG2_IS */ "", 27619 /* ES0_DDR36_CONFIG_REG3_IS */ "", 27620 /* ES0_DDR36_STATUS_REG1_IS */ "", 27621 /* ES0_DDR36_STATUS_REG2_IS */ "", 27622 /* ES0_DTU_ATE_STS0 */ "", 27623 /* ES0_DTU_ATE_STS1 */ "", 27624 /* ES0_DTU_ATE_STS2 */ "", 27625 /* ES0_DTU_ATE_STS3 */ "", 27626 /* ES0_DTU_ATE_STS4 */ "", 27627 /* ES0_DTU_ATE_TMODE */ "", 27628 /* ES0_DTU_LTE_ADR0 */ "", 27629 /* ES0_DTU_LTE_ADR1 */ "", 27630 /* ES0_DTU_LTE_D0F_0 */ "", 27631 /* ES0_DTU_LTE_D0F_1 */ "", 27632 /* ES0_DTU_LTE_D0R_0 */ "", 27633 /* ES0_DTU_LTE_D0R_1 */ "", 27634 /* ES0_DTU_LTE_D1F_0 */ "", 27635 /* ES0_DTU_LTE_D1F_1 */ "", 27636 /* ES0_DTU_LTE_D1R_0 */ "", 27637 /* ES0_DTU_LTE_D1R_1 */ "", 27638 /* ES0_DTU_LTE_STS_DONE */ "", 27639 /* ES0_DTU_LTE_STS_ERR_ADR */ "", 27640 /* ES0_DTU_LTE_STS_ERR_DF_0 */ "", 27641 /* ES0_DTU_LTE_STS_ERR_DF_1 */ "", 27642 /* ES0_DTU_LTE_STS_ERR_DR_0 */ "", 27643 /* ES0_DTU_LTE_STS_ERR_DR_1 */ "", 27644 /* ES0_DTU_LTE_TMODE0 */ "", 27645 /* ES0_DTU_LTE_TMODE1 */ "", 27646 /* ES0_DTU_MODE */ "", 27647 /* ES0_MCU_EN */ "", 27648 /* ES0_MCU_STATUS */ "", 27649 /* ES0_SRAM_CTL */ "", 27650 /* ES1_DDR36_CONFIG_REG1_IS */ "", 27651 /* ES1_DDR36_CONFIG_REG2_IS */ "", 27652 /* ES1_DDR36_CONFIG_REG3_IS */ "", 27653 /* ES1_DDR36_STATUS_REG1_IS */ "", 27654 /* ES1_DDR36_STATUS_REG2_IS */ "", 27655 /* ES1_DTU_ATE_STS0 */ "", 27656 /* ES1_DTU_ATE_STS1 */ "", 27657 /* ES1_DTU_ATE_STS2 */ "", 27658 /* ES1_DTU_ATE_STS3 */ "", 27659 /* ES1_DTU_ATE_STS4 */ "", 27660 /* ES1_DTU_ATE_TMODE */ "", 27661 /* ES1_DTU_LTE_ADR0 */ "", 27662 /* ES1_DTU_LTE_ADR1 */ "", 27663 /* ES1_DTU_LTE_D0F_0 */ "", 27664 /* ES1_DTU_LTE_D0F_1 */ "", 27665 /* ES1_DTU_LTE_D0R_0 */ "", 27666 /* ES1_DTU_LTE_D0R_1 */ "", 27667 /* ES1_DTU_LTE_D1F_0 */ "", 27668 /* ES1_DTU_LTE_D1F_1 */ "", 27669 /* ES1_DTU_LTE_D1R_0 */ "", 27670 /* ES1_DTU_LTE_D1R_1 */ "", 27671 /* ES1_DTU_LTE_STS_DONE */ "", 27672 /* ES1_DTU_LTE_STS_ERR_ADR */ "", 27673 /* ES1_DTU_LTE_STS_ERR_DF_0 */ "", 27674 /* ES1_DTU_LTE_STS_ERR_DF_1 */ "", 27675 /* ES1_DTU_LTE_STS_ERR_DR_0 */ "", 27676 /* ES1_DTU_LTE_STS_ERR_DR_1 */ "", 27677 /* ES1_DTU_LTE_TMODE0 */ "", 27678 /* ES1_DTU_LTE_TMODE1 */ "", 27679 /* ES1_DTU_MODE */ "", 27680 /* ES1_MCU_EN */ "", 27681 /* ES1_MCU_STATUS */ "", 27682 /* ES1_SRAM_CTL */ "", 27683 /* ESA0 */ "", 27684 /* ESA1 */ "", 27685 /* ESA2 */ "", 27686 /* ESCONFIG */ "", 27687 /* ESEC_AES_CNTRL */ "", 27688 /* ESEC_AES_STATUS */ "", 27689 /* ESEC_CONFIG */ "", 27690 /* ESEC_CTRL */ "", 27691 /* ESEC_DEBUGFF_ECC_STATUS */ "", 27692 /* ESEC_DEBUG_1 */ "", 27693 /* ESEC_DEBUG_CTRL */ "", 27694 /* ESEC_DEBUG_GLOBAL_1 */ "", 27695 /* ESEC_DEBUG_GLOBAL_2 */ "", 27696 /* ESEC_ECC_DEBUG */ "", 27697 /* ESEC_ECC_ERROR */ "", 27698 /* ESEC_ECC_ERROR_MASK */ "", 27699 /* ESEC_EGRESS_MTU0_1 */ "", 27700 /* ESEC_EGRESS_MTU2_3 */ "", 27701 /* ESEC_EGRESS_MTU_FOR_MGMT_PKT */ "", 27702 /* ESEC_FIPS_CONTROL */ "", 27703 /* ESEC_FIPS_DATA_REG0 */ "", 27704 /* ESEC_FIPS_DATA_REG1 */ "", 27705 /* ESEC_FIPS_DATA_REG2 */ "", 27706 /* ESEC_FIPS_DATA_REG3 */ "", 27707 /* ESEC_FIPS_ENC_DATA_REG0 */ "", 27708 /* ESEC_FIPS_ENC_DATA_REG1 */ "", 27709 /* ESEC_FIPS_ENC_DATA_REG2 */ "", 27710 /* ESEC_FIPS_ENC_DATA_REG3 */ "", 27711 /* ESEC_FIPS_INDIRECT_ACCESS */ "", 27712 /* ESEC_FIPS_INDIRECT_ADDR */ "", 27713 /* ESEC_FIPS_INDIRECT_RD_DATA */ "", 27714 /* ESEC_FIPS_INDIRECT_WR_DATA */ "", 27715 /* ESEC_FIPS_IV_REG0 */ "", 27716 /* ESEC_FIPS_IV_REG1 */ "", 27717 /* ESEC_FIPS_IV_REG2 */ "", 27718 /* ESEC_FIPS_KEY_REG0 */ "", 27719 /* ESEC_FIPS_KEY_REG1 */ "", 27720 /* ESEC_FIPS_KEY_REG2 */ "", 27721 /* ESEC_FIPS_KEY_REG3 */ "", 27722 /* ESEC_FIPS_KEY_REG4 */ "", 27723 /* ESEC_FIPS_KEY_REG5 */ "", 27724 /* ESEC_FIPS_KEY_REG6 */ "", 27725 /* ESEC_FIPS_KEY_REG7 */ "", 27726 /* ESEC_FIPS_STATUS */ "", 27727 /* ESEC_GLOBAL_CTRL */ "", 27728 /* ESEC_GLOBAL_PRE_SCALE */ "", 27729 /* ESEC_GLOBAL_TICK_TIME */ "", 27730 /* ESEC_GLOBAL_TIMER */ "", 27731 /* ESEC_HEADER_CAPTURE_CTRL */ "", 27732 /* ESEC_LKUPFF_ECC_STATUS */ "", 27733 /* ESEC_MASTER_CTRL */ "", 27734 /* ESEC_MIB1_ECC_STATUS */ "", 27735 /* ESEC_MIB2_ECC_STATUS */ "", 27736 /* ESEC_MIB3_ECC_STATUS */ "", 27737 /* ESEC_MIB4_ECC_STATUS */ "", 27738 /* ESEC_MIB5_ECC_STATUS */ "", 27739 /* ESEC_OLP_RX_ETYPE */ "", 27740 /* ESEC_OLP_RX_MAC_DA0 */ "", 27741 /* ESEC_OLP_RX_MAC_DA1 */ "", 27742 /* ESEC_OLP_RX_MAC_SA0 */ "", 27743 /* ESEC_OLP_RX_MAC_SA1 */ "", 27744 /* ESEC_OLP_RX_VLAN */ "", 27745 /* ESEC_OVR_IV_REG0 */ "", 27746 /* ESEC_OVR_IV_REG1 */ "", 27747 /* ESEC_OVR_IV_REG2 */ "", 27748 /* ESEC_OVR_KEY_REG0 */ "", 27749 /* ESEC_OVR_KEY_REG1 */ "", 27750 /* ESEC_OVR_KEY_REG2 */ "", 27751 /* ESEC_OVR_KEY_REG3 */ "", 27752 /* ESEC_OVR_KEY_REG4 */ "", 27753 /* ESEC_OVR_KEY_REG5 */ "", 27754 /* ESEC_OVR_KEY_REG6 */ "", 27755 /* ESEC_OVR_KEY_REG7 */ "", 27756 /* ESEC_PDCFF_ECC_STATUS */ "", 27757 /* ESEC_PN_THD */ "", 27758 /* ESEC_SADB_ECC_STATUS */ "", 27759 /* ESEC_SAKEY_ECC_STATUS */ "", 27760 /* ESEC_SA_EXPIRY_INT */ "", 27761 /* ESEC_SA_EXPIRY_INT_MASK */ "", 27762 /* ESEC_SA_TABLE_DEBUG */ "", 27763 /* ESEC_SCDB_ECC_STATUS */ "", 27764 /* ESEC_SOFT_SA_EXPIRY_INT */ "", 27765 /* ESEC_SOFT_SA_EXPIRY_INT_MASK */ "", 27766 /* ESEC_XLCFF_ECC_STATUS */ "", 27767 /* ESEC_XMIT_CREDIT_EMPTY_INT */ "", 27768 /* ESEC_XMIT_CREDIT_EMPTY_INT_MASK */ "", 27769 /* ESEC_XPN_THD0 */ "", 27770 /* ESEC_XPN_THD1 */ "", 27771 /* ESMIF_ADM_CTRL_STATUS */ "", 27772 /* ESMIF_CNP_SEARCH_REQ_COUNT */ "", 27773 /* ESMIF_CUR_PENDING_COST0 */ "", 27774 /* ESMIF_CUR_PENDING_COST1 */ "", 27775 /* ESMIF_CUR_PENDING_COST2 */ "", 27776 /* ESMIF_DROP_COUNT */ "", 27777 /* ESMIF_INIT_CONFIG */ "", 27778 /* ESMIF_MAX_PENDING_COST0 */ "", 27779 /* ESMIF_MAX_PENDING_COST1 */ "", 27780 /* ESMIF_MAX_PENDING_COST2 */ "", 27781 /* ESMIF_MULTI_ECC_PARITY_ERROR_LOG */ "", 27782 /* ESM_ADM_CTRL_FIFO_STATUS */ "", 27783 /* ESM_ADM_THR_DROP_ALL_COST0 */ "", 27784 /* ESM_ADM_THR_DROP_ALL_COST1 */ "", 27785 /* ESM_ADM_THR_DROP_ALL_COST2 */ "", 27786 /* ESM_ADM_THR_DROP_ALL_RESET_COST0 */ "", 27787 /* ESM_ADM_THR_DROP_ALL_RESET_COST1 */ "", 27788 /* ESM_ADM_THR_DROP_ALL_RESET_COST2 */ "", 27789 /* ESM_ADM_THR_DROP_OPT_COST0 */ "", 27790 /* ESM_ADM_THR_DROP_OPT_COST1 */ "", 27791 /* ESM_ADM_THR_DROP_OPT_COST2 */ "", 27792 /* ESM_ADM_THR_DROP_OPT_RESET_COST0 */ "", 27793 /* ESM_ADM_THR_DROP_OPT_RESET_COST1 */ "", 27794 /* ESM_ADM_THR_DROP_OPT_RESET_COST2 */ "", 27795 /* ESM_AGE_CNT */ "", 27796 /* ESM_AXP_THR_XOFF_COST0 */ "", 27797 /* ESM_AXP_THR_XOFF_COST1 */ "", 27798 /* ESM_AXP_THR_XOFF_COST2 */ "", 27799 /* ESM_AXP_THR_XOFF_RESET_COST0 */ "", 27800 /* ESM_AXP_THR_XOFF_RESET_COST1 */ "", 27801 /* ESM_AXP_THR_XOFF_RESET_COST2 */ "", 27802 /* ESM_CONTAINER_SELECT */ "", 27803 /* ESM_CTL */ "", 27804 /* ESM_ERR_CTL */ "", 27805 /* ESM_ET_HWTL_CONTROL */ "", 27806 /* ESM_ET_HWTL_EVENT_ERR_INFO */ "", 27807 /* ESM_ET_HWTL_MM_INFO */ "", 27808 /* ESM_ET_HWTL_STATUS_0 */ "", 27809 /* ESM_ET_HWTL_STATUS_1 */ "", 27810 /* ESM_ET_RSP_CBA_MM_INFO */ "", 27811 /* ESM_ET_RSP_FIFO_STATUS */ "", 27812 /* ESM_EVENT_ERR_STATUS_INTR */ "", 27813 /* ESM_EVENT_ERR_STATUS_INTR_ENABLE */ "", 27814 /* ESM_EXT_HITBIT_CONTROL */ "", 27815 /* ESM_FIFO_MAX_COUNTS */ "", 27816 /* ESM_KEYGEN_CTL */ "", 27817 /* ESM_L2_AGE_CTL */ "", 27818 /* ESM_L2_AGE_STATUS */ "", 27819 /* ESM_MAX_LATENCY_RECORDED */ "", 27820 /* ESM_MEMORY_DBGCTRL_0 */ "ESM_MEMORY_CONTROL_0", 27821 /* ESM_MEMORY_DBGCTRL_1 */ "ESM_MEMORY_CONTROL_1", 27822 /* ESM_MEMORY_DBGCTRL_2 */ "ESM_MEMORY_CONTROL_2", 27823 /* ESM_MEMORY_DBGCTRL_3 */ "ESM_MEMORY_CONTROL_3", 27824 /* ESM_MEMORY_DBGCTRL_4 */ "ESM_MEMORY_CONTROL_4", 27825 /* ESM_MISC_CONTROL */ "", 27826 /* ESM_MISC_STATUS */ "", 27827 /* ESM_MODE_PER_PORT */ "", 27828 /* ESM_OPT_REQ_INTERVAL */ "", 27829 /* ESM_PER_PORT_AGE_CONTROL */ "", 27830 /* ESM_PER_PORT_REPL_CONTROL */ "", 27831 /* ESM_PKT_TYPE_ID_CAM_BIST_CONFIG */ "", 27832 /* ESM_PKT_TYPE_ID_CAM_BIST_DBGCTRL */ "ESM_PKT_TYPE_ID_CAM_BIST_CONTROL", 27833 /* ESM_PKT_TYPE_ID_CAM_BIST_DBG_DATA */ "", 27834 /* ESM_PKT_TYPE_ID_CAM_BIST_STATUS */ "", 27835 /* ESM_PKT_TYPE_ID_CAM_DBGCTRL */ "ESM_PKT_TYPE_ID_CAM_CONTROL", 27836 /* ESM_PPA_STATUS */ "", 27837 /* ESM_REQUEST_LANE_MAP */ "", 27838 /* ESM_REUSE_COUNTER_0 */ "", 27839 /* ESM_REUSE_COUNTER_1 */ "", 27840 /* ESM_REUSE_COUNTER_2 */ "", 27841 /* ESM_REUSE_COUNTER_3 */ "", 27842 /* ESM_SEARCH_PROFILE_BASE */ "", 27843 /* ESTDMCONFIG */ "", 27844 /* ES_BYPASSMMU */ "", 27845 /* ES_CPU_SCHEDULER */ "", 27846 /* ES_ERROR */ "", 27847 /* ES_ERROR_INFO */ "", 27848 /* ES_ERROR_MASK */ "", 27849 /* ES_LLS_DYNAMIC_UPDATE_INT */ "", 27850 /* ES_LLS_DYNAMIC_UPDATE_INT_MASK */ "", 27851 /* ES_LLS_SOFT_RESET */ "", 27852 /* ES_LL_FC_CONFIG */ "", 27853 /* ES_PIPE0_ASF_CREDIT_THRESH_HI */ "", 27854 /* ES_PIPE0_ASF_CREDIT_THRESH_LO */ "", 27855 /* ES_PIPE0_GRP_WT_SELECT */ "", 27856 /* ES_PIPE0_LLS_CONFIG0 */ "", 27857 /* ES_PIPE0_LLS_CONFIG_SP_MIN_PRIORITY */ "", 27858 /* ES_PIPE0_LLS_DEBUG_ENQ_BLOCK_ON_L0 */ "", 27859 /* ES_PIPE0_LLS_DEBUG_ENQ_BLOCK_ON_L1 */ "", 27860 /* ES_PIPE0_LLS_DEBUG_ENQ_BLOCK_ON_L2 */ "", 27861 /* ES_PIPE0_LLS_DEBUG_ENQ_BLOCK_ON_PORT */ "", 27862 /* ES_PIPE0_LLS_DEBUG_FORCE_CPU_COSMASK0 */ "", 27863 /* ES_PIPE0_LLS_DEBUG_FORCE_CPU_COSMASK1 */ "", 27864 /* ES_PIPE0_LLS_DEBUG_INJECT_ACTIVATION */ "", 27865 /* ES_PIPE0_LLS_DEBUG_P_WERR_MAX_SC_RESET */ "", 27866 /* ES_PIPE0_LLS_DEBUG_SPECIAL */ "", 27867 /* ES_PIPE0_LLS_EN_COR_ERR_RPT_1 */ "", 27868 /* ES_PIPE0_LLS_EN_COR_ERR_RPT_2 */ "", 27869 /* ES_PIPE0_LLS_ERROR_VIOLATE_1IN11_TDM */ "", 27870 /* ES_PIPE0_LLS_FC_CONFIG */ "", 27871 /* ES_PIPE0_LLS_FIXED_DEQ_LEN */ "", 27872 /* ES_PIPE0_LLS_MEM_L0_TM_0 */ "", 27873 /* ES_PIPE0_LLS_MEM_L0_TM_1 */ "", 27874 /* ES_PIPE0_LLS_MEM_L0_TM_2 */ "", 27875 /* ES_PIPE0_LLS_MEM_L0_TM_3 */ "", 27876 /* ES_PIPE0_LLS_MEM_L0_TM_4 */ "", 27877 /* ES_PIPE0_LLS_MEM_L0_TM_5 */ "", 27878 /* ES_PIPE0_LLS_MEM_L0_TM_6 */ "", 27879 /* ES_PIPE0_LLS_MEM_L0_TM_7 */ "", 27880 /* ES_PIPE0_LLS_MEM_L0_TM_8 */ "", 27881 /* ES_PIPE0_LLS_MEM_L0_TM_9 */ "", 27882 /* ES_PIPE0_LLS_MEM_L1_TM_0 */ "", 27883 /* ES_PIPE0_LLS_MEM_L1_TM_1 */ "", 27884 /* ES_PIPE0_LLS_MEM_L1_TM_2 */ "", 27885 /* ES_PIPE0_LLS_MEM_L1_TM_3 */ "", 27886 /* ES_PIPE0_LLS_MEM_L1_TM_4 */ "", 27887 /* ES_PIPE0_LLS_MEM_L1_TM_5 */ "", 27888 /* ES_PIPE0_LLS_MEM_L1_TM_6 */ "", 27889 /* ES_PIPE0_LLS_MEM_L1_TM_7 */ "", 27890 /* ES_PIPE0_LLS_MEM_L1_TM_8 */ "", 27891 /* ES_PIPE0_LLS_MEM_L1_TM_9 */ "", 27892 /* ES_PIPE0_LLS_MEM_L2_TM_0 */ "", 27893 /* ES_PIPE0_LLS_MEM_L2_TM_2 */ "", 27894 /* ES_PIPE0_LLS_MEM_L2_TM_3 */ "", 27895 /* ES_PIPE0_LLS_MEM_L2_TM_4 */ "", 27896 /* ES_PIPE0_LLS_MEM_L2_TM_5 */ "", 27897 /* ES_PIPE0_LLS_MEM_L2_TM_6 */ "", 27898 /* ES_PIPE0_LLS_MEM_LVM */ "", 27899 /* ES_PIPE0_LLS_MEM_PORT_TM_0 */ "", 27900 /* ES_PIPE0_LLS_MEM_PORT_TM_1 */ "", 27901 /* ES_PIPE0_LLS_MEM_PORT_TM_2 */ "", 27902 /* ES_PIPE0_LLS_MEM_PORT_TM_3 */ "", 27903 /* ES_PIPE0_LLS_MEM_PORT_TM_4 */ "", 27904 /* ES_PIPE0_LLS_PKT_ACC_CONFIG1 */ "", 27905 /* ES_PIPE0_LLS_PKT_ACC_CONFIG2 */ "", 27906 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_0A */ "", 27907 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_0B */ "", 27908 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_0C */ "", 27909 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_1A */ "", 27910 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_1B */ "", 27911 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_1C */ "", 27912 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_2A */ "", 27913 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_2B */ "", 27914 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_2C */ "", 27915 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_3A */ "", 27916 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_3B */ "", 27917 /* ES_PIPE0_LLS_SP_WERR_DYN_CHANGE_3C */ "", 27918 /* ES_PIPE0_MIN_SPACING */ "", 27919 /* ES_PIPE0_MMU_1DBG_A_HI */ "ES_PIPE0_FORCE_SAF_HI", 27920 /* ES_PIPE0_MMU_1DBG_A_LO */ "ES_PIPE0_FORCE_SAF_LO", 27921 /* ES_PIPE0_MMU_1DBG_A_MID */ "ES_PIPE0_FORCE_SAF_MID", 27922 /* ES_PIPE0_MMU_1DBG_C */ "ES_PIPE0_DIP_ACTIVATION0", 27923 /* ES_PIPE0_MMU_2DBG_C_0 */ "ES_PIPE0_DIP_DEACTIVATION", 27924 /* ES_PIPE0_MMU_2DBG_C_1 */ "ES_PIPE0_DIP_INSERTION0", 27925 /* ES_PIPE0_MMU_3DBG_C */ "ES_PIPE0_DIP_INSERTION1", 27926 /* ES_PIPE0_MMU_DI_THR */ "ES_PIPE0_DIP_ACTIVATION1", 27927 /* ES_PIPE0_MMU_PORT_CREDIT */ "", 27928 /* ES_PIPE0_MMU_PORT_CREDIT_EXPRESS */ "ES_PIPE0_MMU_PORT_CREDIT", 27929 /* ES_PIPE0_MMU_PORT_CREDIT_PREEMPT */ "", 27930 /* ES_PIPE0_MMU_PORT_CURRENT_CREDIT */ "", 27931 /* ES_PIPE0_MMU_PORT_CURRENT_CREDIT_EXPRESS */ "ES_PIPE0_MMU_PORT_CURRENT_CREDIT", 27932 /* ES_PIPE0_MMU_PORT_CURRENT_CREDIT_PREEMPT */ "", 27933 /* ES_PIPE0_OVR_SUB_GRP0_TBL */ "", 27934 /* ES_PIPE0_OVR_SUB_GRP0_WT */ "", 27935 /* ES_PIPE0_OVR_SUB_GRP1_TBL */ "", 27936 /* ES_PIPE0_OVR_SUB_GRP1_WT */ "", 27937 /* ES_PIPE0_OVR_SUB_GRP2_TBL */ "", 27938 /* ES_PIPE0_OVR_SUB_GRP2_WT */ "", 27939 /* ES_PIPE0_OVR_SUB_GRP3_TBL */ "", 27940 /* ES_PIPE0_OVR_SUB_GRP3_WT */ "", 27941 /* ES_PIPE0_OVR_SUB_GRP4_TBL */ "", 27942 /* ES_PIPE0_OVR_SUB_GRP5_TBL */ "", 27943 /* ES_PIPE0_OVR_SUB_GRP6_TBL */ "", 27944 /* ES_PIPE0_OVR_SUB_GRP7_TBL */ "", 27945 /* ES_PIPE0_OVR_SUB_GRP_CFG */ "", 27946 /* ES_PIPE0_OVR_SUB_GRP_WT0 */ "", 27947 /* ES_PIPE0_OVR_SUB_GRP_WT1 */ "", 27948 /* ES_PIPE0_OVR_SUB_GRP_WT2 */ "", 27949 /* ES_PIPE0_OVR_SUB_GRP_WT3 */ "", 27950 /* ES_PIPE0_OVR_SUB_GRP_WT4 */ "", 27951 /* ES_PIPE0_OVR_SUB_GRP_WT5 */ "", 27952 /* ES_PIPE0_OVR_SUB_GRP_WT6 */ "", 27953 /* ES_PIPE0_OVR_SUB_GRP_WT7 */ "", 27954 /* ES_PIPE0_TDM_CONFIG */ "", 27955 /* ES_PIPE0_TDM_PORT_CREDIT_MODE_0_31 */ "", 27956 /* ES_PIPE0_TDM_PORT_CREDIT_MODE_32_63 */ "", 27957 /* ES_PIPE0_TDM_TBL_DEBUG */ "", 27958 /* ES_PIPE1_ASF_CREDIT_THRESH_HI */ "", 27959 /* ES_PIPE1_ASF_CREDIT_THRESH_LO */ "", 27960 /* ES_PIPE1_GRP_WT_SELECT */ "", 27961 /* ES_PIPE1_LLS_CONFIG0 */ "", 27962 /* ES_PIPE1_LLS_CONFIG_SP_MIN_PRIORITY */ "", 27963 /* ES_PIPE1_LLS_DEBUG_ENQ_BLOCK_ON_L0 */ "", 27964 /* ES_PIPE1_LLS_DEBUG_ENQ_BLOCK_ON_L1 */ "", 27965 /* ES_PIPE1_LLS_DEBUG_ENQ_BLOCK_ON_L2 */ "", 27966 /* ES_PIPE1_LLS_DEBUG_ENQ_BLOCK_ON_PORT */ "", 27967 /* ES_PIPE1_LLS_DEBUG_INJECT_ACTIVATION */ "", 27968 /* ES_PIPE1_LLS_DEBUG_P_WERR_MAX_SC_RESET */ "", 27969 /* ES_PIPE1_LLS_DEBUG_SPECIAL */ "", 27970 /* ES_PIPE1_LLS_EN_COR_ERR_RPT_1 */ "", 27971 /* ES_PIPE1_LLS_EN_COR_ERR_RPT_2 */ "", 27972 /* ES_PIPE1_LLS_ERROR_VIOLATE_1IN11_TDM */ "", 27973 /* ES_PIPE1_LLS_FC_CONFIG */ "", 27974 /* ES_PIPE1_LLS_FIXED_DEQ_LEN */ "", 27975 /* ES_PIPE1_LLS_MEM_L0_TM_0 */ "", 27976 /* ES_PIPE1_LLS_MEM_L0_TM_1 */ "", 27977 /* ES_PIPE1_LLS_MEM_L0_TM_2 */ "", 27978 /* ES_PIPE1_LLS_MEM_L0_TM_3 */ "", 27979 /* ES_PIPE1_LLS_MEM_L0_TM_4 */ "", 27980 /* ES_PIPE1_LLS_MEM_L0_TM_5 */ "", 27981 /* ES_PIPE1_LLS_MEM_L0_TM_6 */ "", 27982 /* ES_PIPE1_LLS_MEM_L0_TM_7 */ "", 27983 /* ES_PIPE1_LLS_MEM_L0_TM_8 */ "", 27984 /* ES_PIPE1_LLS_MEM_L0_TM_9 */ "", 27985 /* ES_PIPE1_LLS_MEM_L1_TM_0 */ "", 27986 /* ES_PIPE1_LLS_MEM_L1_TM_1 */ "", 27987 /* ES_PIPE1_LLS_MEM_L1_TM_2 */ "", 27988 /* ES_PIPE1_LLS_MEM_L1_TM_3 */ "", 27989 /* ES_PIPE1_LLS_MEM_L1_TM_4 */ "", 27990 /* ES_PIPE1_LLS_MEM_L1_TM_5 */ "", 27991 /* ES_PIPE1_LLS_MEM_L1_TM_6 */ "", 27992 /* ES_PIPE1_LLS_MEM_L1_TM_7 */ "", 27993 /* ES_PIPE1_LLS_MEM_L1_TM_8 */ "", 27994 /* ES_PIPE1_LLS_MEM_L1_TM_9 */ "", 27995 /* ES_PIPE1_LLS_MEM_L2_TM_0 */ "", 27996 /* ES_PIPE1_LLS_MEM_L2_TM_2 */ "", 27997 /* ES_PIPE1_LLS_MEM_L2_TM_3 */ "", 27998 /* ES_PIPE1_LLS_MEM_L2_TM_4 */ "", 27999 /* ES_PIPE1_LLS_MEM_L2_TM_5 */ "", 28000 /* ES_PIPE1_LLS_MEM_L2_TM_6 */ "", 28001 /* ES_PIPE1_LLS_MEM_LVM */ "", 28002 /* ES_PIPE1_LLS_MEM_PORT_TM_0 */ "", 28003 /* ES_PIPE1_LLS_MEM_PORT_TM_1 */ "", 28004 /* ES_PIPE1_LLS_MEM_PORT_TM_2 */ "", 28005 /* ES_PIPE1_LLS_MEM_PORT_TM_3 */ "", 28006 /* ES_PIPE1_LLS_MEM_PORT_TM_4 */ "", 28007 /* ES_PIPE1_LLS_PKT_ACC_CONFIG1 */ "", 28008 /* ES_PIPE1_LLS_PKT_ACC_CONFIG2 */ "", 28009 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_0A */ "", 28010 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_0B */ "", 28011 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_0C */ "", 28012 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_1A */ "", 28013 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_1B */ "", 28014 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_1C */ "", 28015 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_2A */ "", 28016 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_2B */ "", 28017 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_2C */ "", 28018 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_3A */ "", 28019 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_3B */ "", 28020 /* ES_PIPE1_LLS_SP_WERR_DYN_CHANGE_3C */ "", 28021 /* ES_PIPE1_MIN_SPACING */ "", 28022 /* ES_PIPE1_MMU_1DBG_A_HI */ "ES_PIPE1_FORCE_SAF_HI", 28023 /* ES_PIPE1_MMU_1DBG_A_LO */ "ES_PIPE1_FORCE_SAF_LO", 28024 /* ES_PIPE1_MMU_1DBG_C */ "ES_PIPE1_DIP_ACTIVATION0", 28025 /* ES_PIPE1_MMU_2DBG_C_0 */ "ES_PIPE1_DIP_DEACTIVATION", 28026 /* ES_PIPE1_MMU_2DBG_C_1 */ "ES_PIPE1_DIP_INSERTION0", 28027 /* ES_PIPE1_MMU_3DBG_C */ "ES_PIPE1_DIP_INSERTION1", 28028 /* ES_PIPE1_MMU_DI_THR */ "ES_PIPE1_DIP_ACTIVATION1", 28029 /* ES_PIPE1_MMU_PORT_CREDIT */ "", 28030 /* ES_PIPE1_MMU_PORT_CURRENT_CREDIT */ "", 28031 /* ES_PIPE1_OVR_SUB_GRP0_TBL */ "", 28032 /* ES_PIPE1_OVR_SUB_GRP0_WT */ "", 28033 /* ES_PIPE1_OVR_SUB_GRP1_TBL */ "", 28034 /* ES_PIPE1_OVR_SUB_GRP1_WT */ "", 28035 /* ES_PIPE1_OVR_SUB_GRP2_TBL */ "", 28036 /* ES_PIPE1_OVR_SUB_GRP2_WT */ "", 28037 /* ES_PIPE1_OVR_SUB_GRP3_TBL */ "", 28038 /* ES_PIPE1_OVR_SUB_GRP3_WT */ "", 28039 /* ES_PIPE1_OVR_SUB_GRP4_TBL */ "", 28040 /* ES_PIPE1_OVR_SUB_GRP5_TBL */ "", 28041 /* ES_PIPE1_OVR_SUB_GRP6_TBL */ "", 28042 /* ES_PIPE1_OVR_SUB_GRP7_TBL */ "", 28043 /* ES_PIPE1_OVR_SUB_GRP_CFG */ "", 28044 /* ES_PIPE1_OVR_SUB_GRP_WT0 */ "", 28045 /* ES_PIPE1_OVR_SUB_GRP_WT1 */ "", 28046 /* ES_PIPE1_OVR_SUB_GRP_WT2 */ "", 28047 /* ES_PIPE1_OVR_SUB_GRP_WT3 */ "", 28048 /* ES_PIPE1_TDM_CONFIG */ "", 28049 /* ES_PIPE1_TDM_TBL_DEBUG */ "", 28050 /* ES_PORTGRP_WDRR_WEIGHTS */ "", 28051 /* ES_PURGEQ_PORT_ENABLE */ "ES_PURGEQ_PORT_MASK", 28052 /* ES_QUEUE_TO_PRIO */ "", 28053 /* ES_QUEUE_TO_PRIO_P54 */ "", 28054 /* ES_S2_MEMORY_CREDIT_TM_0 */ "", 28055 /* ES_S2_MEMORY_CREDIT_TM_1 */ "", 28056 /* ES_S2_MEMORY_PARITY_STATUS_0 */ "", 28057 /* ES_S2_MEMORY_PARITY_STATUS_1 */ "", 28058 /* ES_S2_MEMORY_TM_0 */ "", 28059 /* ES_S2_MEMORY_TM_1 */ "", 28060 /* ES_S3_MEMORY_CREDIT_TM_0 */ "", 28061 /* ES_S3_MEMORY_CREDIT_TM_1 */ "", 28062 /* ES_S3_MEMORY_PARITY_STATUS_0 */ "", 28063 /* ES_S3_MEMORY_PARITY_STATUS_1 */ "", 28064 /* ES_S3_MEMORY_TM_0 */ "", 28065 /* ES_S3_MEMORY_TM_1 */ "", 28066 /* ES_TDM_CAL_CFG */ "", 28067 /* ES_TDM_CONFIG */ "", 28068 /* ES_TDM_EN */ "", 28069 /* ETAG_MULTICAST_RANGE */ "", 28070 /* ETB_AUTHENTICATION_STATUS */ "", 28071 /* ETB_CLAIM_TAG_CLEAR */ "", 28072 /* ETB_CLAIM_TAG_SET */ "", 28073 /* ETB_COMPONENT_ID_0 */ "", 28074 /* ETB_COMPONENT_ID_1 */ "", 28075 /* ETB_COMPONENT_ID_2 */ "", 28076 /* ETB_COMPONENT_ID_3 */ "", 28077 /* ETB_CTL */ "", 28078 /* ETB_DEVICE_ID */ "", 28079 /* ETB_DEVICE_TYPE_ID */ "", 28080 /* ETB_FFCR */ "", 28081 /* ETB_FFSR */ "", 28082 /* ETB_IITRFLIN */ "", 28083 /* ETB_IITRFLINACK */ "", 28084 /* ETB_INTEG_MODE_CTRL */ "", 28085 /* ETB_ITATBCTR0 */ "", 28086 /* ETB_ITATBCTR1 */ "", 28087 /* ETB_ITATBCTR2 */ "", 28088 /* ETB_ITATBDATA0 */ "", 28089 /* ETB_ITMISCOP0 */ "", 28090 /* ETB_LOCK_ACCESS */ "", 28091 /* ETB_LOCK_STATUS */ "", 28092 /* ETB_PERIPHERAL_ID_0 */ "", 28093 /* ETB_PERIPHERAL_ID_1 */ "", 28094 /* ETB_PERIPHERAL_ID_2 */ "", 28095 /* ETB_PERIPHERAL_ID_3 */ "", 28096 /* ETB_PERIPHERAL_ID_4 */ "", 28097 /* ETB_PERIPHERAL_ID_5 */ "", 28098 /* ETB_PERIPHERAL_ID_6 */ "", 28099 /* ETB_PERIPHERAL_ID_7 */ "", 28100 /* ETB_RDP */ "", 28101 /* ETB_RRD */ "", 28102 /* ETB_RRP */ "", 28103 /* ETB_RWD */ "", 28104 /* ETB_RWP */ "", 28105 /* ETB_STS */ "", 28106 /* ETC_CTL */ "", 28107 /* ETHERTYPE_MAP */ "", 28108 /* ETHERTYPE_MAP_PIPE0 */ "", 28109 /* ETHERTYPE_MAP_PIPE1 */ "", 28110 /* ETHERTYPE_MAP_PIPE2 */ "", 28111 /* ETHERTYPE_MAP_PIPE3 */ "", 28112 /* ETHERTYPE_MAP_PIPE4 */ "", 28113 /* ETHERTYPE_MAP_PIPE5 */ "", 28114 /* ETHERTYPE_MAP_PIPE6 */ "", 28115 /* ETHERTYPE_MAP_PIPE7 */ "", 28116 /* ETM_ADDR_CMP_ACCESS_TYPE_1 */ "", 28117 /* ETM_ADDR_CMP_ACCESS_TYPE_2 */ "", 28118 /* ETM_ADDR_CMP_ACCESS_TYPE_3 */ "", 28119 /* ETM_ADDR_CMP_ACCESS_TYPE_4 */ "", 28120 /* ETM_ADDR_CMP_ACCESS_TYPE_5 */ "", 28121 /* ETM_ADDR_CMP_ACCESS_TYPE_6 */ "", 28122 /* ETM_ADDR_CMP_ACCESS_TYPE_7 */ "", 28123 /* ETM_ADDR_CMP_ACCESS_TYPE_8 */ "", 28124 /* ETM_ADDR_CMP_VALUE_1 */ "", 28125 /* ETM_ADDR_CMP_VALUE_2 */ "", 28126 /* ETM_ADDR_CMP_VALUE_3 */ "", 28127 /* ETM_ADDR_CMP_VALUE_4 */ "", 28128 /* ETM_ADDR_CMP_VALUE_5 */ "", 28129 /* ETM_ADDR_CMP_VALUE_6 */ "", 28130 /* ETM_ADDR_CMP_VALUE_7 */ "", 28131 /* ETM_ADDR_CMP_VALUE_8 */ "", 28132 /* ETM_ASIC_CONTROL */ "", 28133 /* ETM_AUTHENTICATION_STATUS */ "", 28134 /* ETM_CFG_CODE */ "", 28135 /* ETM_CFG_CODE_EXT */ "", 28136 /* ETM_CLAIM_TAG_CLEAR */ "", 28137 /* ETM_CLAIM_TAG_SET */ "", 28138 /* ETM_COMPONENT_ID_0 */ "", 28139 /* ETM_COMPONENT_ID_1 */ "", 28140 /* ETM_COMPONENT_ID_2 */ "", 28141 /* ETM_COMPONENT_ID_3 */ "", 28142 /* ETM_CONTEXT_ID_CMP_MASK */ "", 28143 /* ETM_CONTEXT_ID_CMP_VALUE */ "", 28144 /* ETM_CORESIGHT_TRACE_ID */ "", 28145 /* ETM_COUNTER_ENABLE_EVENT_1 */ "", 28146 /* ETM_COUNTER_ENABLE_EVENT_2 */ "", 28147 /* ETM_COUNTER_RELOAD_EVENT_1 */ "", 28148 /* ETM_COUNTER_RELOAD_EVENT_2 */ "", 28149 /* ETM_COUNTER_RELOAD_VALUE_1 */ "", 28150 /* ETM_COUNTER_RELOAD_VALUE_2 */ "", 28151 /* ETM_COUNTER_VALUE_1 */ "", 28152 /* ETM_COUNTER_VALUE_2 */ "", 28153 /* ETM_CURRENT_SEQ_STATE */ "", 28154 /* ETM_DATA_CMP_MASK_1 */ "", 28155 /* ETM_DATA_CMP_MASK_3 */ "", 28156 /* ETM_DATA_CMP_VALUE_1 */ "", 28157 /* ETM_DATA_CMP_VALUE_3 */ "", 28158 /* ETM_DEVICE_CONFIG */ "", 28159 /* ETM_DEVICE_TYPE */ "", 28160 /* ETM_ETM_CONTROL */ "", 28161 /* ETM_ETM_ID */ "", 28162 /* ETM_ETM_STATUS */ "", 28163 /* ETM_EXTENDED_EXT_INPUT_SELECTOR */ "", 28164 /* ETM_EXT_OUTPUT_EVENT_1 */ "", 28165 /* ETM_EXT_OUTPUT_EVENT_2 */ "", 28166 /* ETM_FIFOFULL_LEVEL */ "", 28167 /* ETM_INTEGRATION_MODE_CONTROL */ "", 28168 /* ETM_ITATBCTR0 */ "", 28169 /* ETM_ITATBCTR1 */ "", 28170 /* ETM_ITATBCTR2 */ "", 28171 /* ETM_ITATBDATA0 */ "", 28172 /* ETM_ITETMIF */ "", 28173 /* ETM_ITMISCIN */ "", 28174 /* ETM_ITMISCOUT */ "", 28175 /* ETM_ITTRIGGERACK */ "", 28176 /* ETM_ITTRIGGERREQ */ "", 28177 /* ETM_LOCK_ACCESS */ "", 28178 /* ETM_LOCK_STATUS */ "", 28179 /* ETM_PERIPHERAL_ID_0 */ "", 28180 /* ETM_PERIPHERAL_ID_1 */ "", 28181 /* ETM_PERIPHERAL_ID_2 */ "", 28182 /* ETM_PERIPHERAL_ID_3 */ "", 28183 /* ETM_PERIPHERAL_ID_4 */ "", 28184 /* ETM_PERIPHERAL_ID_5 */ "", 28185 /* ETM_PERIPHERAL_ID_6 */ "", 28186 /* ETM_PERIPHERAL_ID_7 */ "", 28187 /* ETM_POWER_DOWN_STATUS */ "", 28188 /* ETM_SEQ_STATE_TRN_EVENT_1 */ "", 28189 /* ETM_SEQ_STATE_TRN_EVENT_2 */ "", 28190 /* ETM_SEQ_STATE_TRN_EVENT_3 */ "", 28191 /* ETM_SEQ_STATE_TRN_EVENT_4 */ "", 28192 /* ETM_SEQ_STATE_TRN_EVENT_5 */ "", 28193 /* ETM_SEQ_STATE_TRN_EVENT_6 */ "", 28194 /* ETM_SYNC_FREQ */ "", 28195 /* ETM_SYSTEM_CFG */ "", 28196 /* ETM_TRIGGER_EVENT */ "", 28197 /* ETM_TR_EN_CTRL_1 */ "", 28198 /* ETM_TR_EN_CTRL_2 */ "", 28199 /* ETM_TR_EN_EVENT */ "", 28200 /* ETM_TR_EN_START_STOP_RESOURCE_CTRL */ "", 28201 /* ETM_VIEW_DATA_CONTROL_1 */ "", 28202 /* ETM_VIEW_DATA_EVENT */ "", 28203 /* ETPPA_BYPASS_FIFO_ALMOST_FULL_THRESHOLD */ "", 28204 /* ETPPA_BYPASS_STAMP_FTMH_ENABLE */ "", 28205 /* ETPPA_CFG_ACCEPTABLE_FRAME_TYPE_PER_FWD_CODE */ "", 28206 /* ETPPA_CFG_EEDB_ENABLED */ "", 28207 /* ETPPA_CFG_EEI_ISID_TYPE */ "", 28208 /* ETPPA_CFG_FHEI_MODEL */ "", 28209 /* ETPPA_CFG_FHEI_MPLS_POP_TYPE */ "", 28210 /* ETPPA_CFG_FHEI_MPLS_SWAP_REMARK_MAP */ "", 28211 /* ETPPA_CFG_FHEI_MPLS_SWAP_TYPE */ "", 28212 /* ETPPA_CFG_FHEI_QOS_MODEL_MAP */ "", 28213 /* ETPPA_CFG_FHEI_TTL_MODEL_MAP */ "", 28214 /* ETPPA_CFG_FORWARDING_ACTION_STRENGTH_1 */ "", 28215 /* ETPPA_CFG_FWD_CODE_TO_ACTION_PROFILE */ "", 28216 /* ETPPA_CFG_INGRESS_NWK_QOS_TYPE */ "", 28217 /* ETPPA_CFG_INLIF_SELECTED */ "", 28218 /* ETPPA_CFG_LAYER_PROTOCOL_IPV4 */ "", 28219 /* ETPPA_CFG_LAYER_PROTOCOL_IPV6 */ "", 28220 /* ETPPA_CFG_LAYER_PROTOCOL_MPLS */ "", 28221 /* ETPPA_CFG_MAP_FORWARD_STRENGTH_TO_STRENGTH */ "", 28222 /* ETPPA_CFG_MAP_FWD_LAYER_PROTOCOL */ "", 28223 /* ETPPA_CFG_MAP_FWD_LAYER_TYPE */ "", 28224 /* ETPPA_CFG_MAP_SNIFF_TO_MIRROR_ACTION */ "", 28225 /* ETPPA_CFG_MAP_SNIFF_TO_SNOOP_ACTION */ "", 28226 /* ETPPA_CFG_MAP_SNIFF_TO_SNOOP_STRENGTH */ "", 28227 /* ETPPA_CFG_OUTLIF_SELECTED */ "", 28228 /* ETPPA_CFG_REMARK_PROTOCOL_PROFILE */ "", 28229 /* ETPPA_CFG_RIF_IN_STACK */ "", 28230 /* ETPPA_CFG_RIF_MAX_VALUE */ "", 28231 /* ETPPA_CFG_SNOOP_ACTION_STRENGTH_1 */ "", 28232 /* ETPPA_CFG_TC_2_NWK_QOS_MAPPING */ "", 28233 /* ETPPA_CFG_TRAP_ACTION_PROFILE_1 */ "", 28234 /* ETPPA_COLLECTOR_VIS_EN */ "", 28235 /* ETPPA_COS_PROFILE_TABLE */ "", 28236 /* ETPPA_DEVICE_CFG_PARSER_ENABLERS */ "", 28237 /* ETPPA_DEVICE_CFG_POP_SIZE_IN_BYTES */ "", 28238 /* ETPPA_DEVICE_CFG_REMARK_PROFILE */ "", 28239 /* ETPPA_ECC_1B_ERR_CNT */ "", 28240 /* ETPPA_ECC_2B_ERR_CNT */ "", 28241 /* ETPPA_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 28242 /* ETPPA_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 28243 /* ETPPA_ECC_INTERRUPT_REGISTER */ "", 28244 /* ETPPA_ECC_INTERRUPT_REGISTER_MASK */ "", 28245 /* ETPPA_ECC_INTERRUPT_REGISTER_TEST */ "", 28246 /* ETPPA_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 28247 /* ETPPA_ERROR_INITIATION_DATA */ "", 28248 /* ETPPA_ETHERNET_FWD_CODE */ "", 28249 /* ETPPA_ETPPA_INT_REG */ "", 28250 /* ETPPA_ETPPA_INT_REG_MASK */ "", 28251 /* ETPPA_ETPPA_INT_REG_TEST */ "", 28252 /* ETPPA_ETPP_LATENCY_SETTINGS */ "", 28253 /* ETPPA_ETPP_PRP_INT_REG */ "", 28254 /* ETPPA_ETPP_PRP_INT_REG_MASK */ "", 28255 /* ETPPA_ETPP_PRP_INT_REG_TEST */ "", 28256 /* ETPPA_FHEI_MPLS_COMMAND */ "", 28257 /* ETPPA_FIFO_ALMOST_FULL_THRESHOLD */ "", 28258 /* ETPPA_FWD_LAYER_ADDITIONAL_INFO_TO_IP_MC_ELIGIBLE_MAPPING */ "", 28259 /* ETPPA_GTIMER_CONFIGURATION */ "", 28260 /* ETPPA_GTIMER_CYCLE */ "", 28261 /* ETPPA_INDIRECT_COMMAND */ "", 28262 /* ETPPA_INDIRECT_COMMAND_ADDRESS */ "", 28263 /* ETPPA_INDIRECT_COMMAND_RD_DATA */ "", 28264 /* ETPPA_INDIRECT_COMMAND_WIDE_MEM */ "", 28265 /* ETPPA_INDIRECT_COMMAND_WR_DATA */ "", 28266 /* ETPPA_INDIRECT_FORCE_BUBBLE */ "", 28267 /* ETPPA_INGRESS_TRAPPED_BY_FHEI */ "", 28268 /* ETPPA_INITIAL_NWK_QOS_SELECT */ "", 28269 /* ETPPA_INITIAL_NWK_QOS_SELECT_PLUS_1 */ "", 28270 /* ETPPA_INTERRUPT_MASK_REGISTER */ "", 28271 /* ETPPA_INTERRUPT_REGISTER */ "", 28272 /* ETPPA_INTERRUPT_REGISTER_TEST */ "", 28273 /* ETPPA_JERICHO_COMPATIBLE_REGISTERS */ "", 28274 /* ETPPA_NUM_ENTRIES_BYPASS_FIFO */ "", 28275 /* ETPPA_NUM_ENTRIES_NETWORK_HEADERS_FIFO */ "", 28276 /* ETPPA_NUM_ENTRIES_PRP_NETWORK_HEADER_FIFO */ "", 28277 /* ETPPA_NUM_ENTRIES_PRP_SYSTEM_HEADER_FIFO */ "", 28278 /* ETPPA_NUM_ENTRIES_SYSTEM_HEADERS_CONTAINER_FIFO */ "", 28279 /* ETPPA_NUM_ENTRIES_TM_FIELDS_FIFO */ "", 28280 /* ETPPA_OUTRIF_MAX_VALUE */ "", 28281 /* ETPPA_PARITY_ERR_CNT */ "", 28282 /* ETPPA_PARSER_FIFO_ALMOST_FULL_THRESHOLD */ "", 28283 /* ETPPA_PAR_ERR_MEM_MASK */ "", 28284 /* ETPPA_PCMI_0 */ "", 28285 /* ETPPA_PCMI_1 */ "", 28286 /* ETPPA_PCMI_2 */ "", 28287 /* ETPPA_PCMI_3 */ "", 28288 /* ETPPA_PCMI_4 */ "", 28289 /* ETPPA_PCMI_0_S */ "", 28290 /* ETPPA_PCMI_0_T */ "", 28291 /* ETPPA_PCMI_1_S */ "", 28292 /* ETPPA_PCMI_1_T */ "", 28293 /* ETPPA_PCMI_2_S */ "", 28294 /* ETPPA_PCMI_2_T */ "", 28295 /* ETPPA_PCMI_3_S */ "", 28296 /* ETPPA_PCMI_3_T */ "", 28297 /* ETPPA_PCMI_4_S */ "", 28298 /* ETPPA_PCMI_4_T */ "", 28299 /* ETPPA_PMF_ACR_ACTION_DISABLE */ "", 28300 /* ETPPA_PORT_VISIBILITY_EN */ "", 28301 /* ETPPA_PORT_VISIBILITY_FORCE */ "", 28302 /* ETPPA_PPH_BASE_FIELDS_CG_2 */ "", 28303 /* ETPPA_PRP_CONTEXT_ENABLERS */ "", 28304 /* ETPPA_REG_0340 */ "", 28305 /* ETPPA_REG_0341 */ "", 28306 /* ETPPA_REG_0400 */ "", 28307 /* ETPPA_REG_0405 */ "", 28308 /* ETPPA_REG_0450 */ "", 28309 /* ETPPA_REG_0451 */ "", 28310 /* ETPPA_REG_0455 */ "", 28311 /* ETPPA_REG_1050 */ "", 28312 /* ETPPA_REG_1051 */ "", 28313 /* ETPPA_REG_00A4 */ "", 28314 /* ETPPA_REG_00A6 */ "", 28315 /* ETPPA_REG_00AA */ "", 28316 /* ETPPA_REG_00C2 */ "", 28317 /* ETPPA_REG_00C5 */ "", 28318 /* ETPPA_REG_00C6 */ "", 28319 /* ETPPA_REG_00E8 */ "", 28320 /* ETPPA_REG_00E9 */ "", 28321 /* ETPPA_REG_00EB */ "", 28322 /* ETPPA_REG_00EE */ "", 28323 /* ETPPA_REG_00F0 */ "", 28324 /* ETPPA_REG_00F1 */ "", 28325 /* ETPPA_REG_00F2 */ "", 28326 /* ETPPA_REG_040D */ "", 28327 /* ETPPA_REG_F000 */ "", 28328 /* ETPPA_RESERVED_MIRROR_ADDR */ "", 28329 /* ETPPA_RESERVED_MTCD */ "", 28330 /* ETPPA_RESERVED_MTCP */ "", 28331 /* ETPPA_RESERVED_SPARE_0 */ "", 28332 /* ETPPA_RESERVED_SPARE_1 */ "", 28333 /* ETPPA_RESERVED_SPARE_2 */ "", 28334 /* ETPPA_RESERVED_SPARE_3 */ "", 28335 /* ETPPA_SBUS_BROADCAST_ID */ "", 28336 /* ETPPA_SBUS_LAST_IN_CHAIN */ "", 28337 /* ETPPA_STAT_VISIBILITY */ "", 28338 /* ETPPA_SYSTEM_HEADERS_CG_1 */ "", 28339 /* ETPPA_TDM_GENERAL_CONFIGURATION */ "", 28340 /* ETPPA_UTILITY_REGS */ "", 28341 /* ETPPA_XOR_INIT_DONE */ "", 28342 /* ETPPB_BTC_DEFAULT_VALUES */ "", 28343 /* ETPPB_BTC_INT_REG */ "", 28344 /* ETPPB_BTC_INT_REG_MASK */ "", 28345 /* ETPPB_BTC_INT_REG_TEST */ "", 28346 /* ETPPB_CFG_CW_PREVENT_MAP */ "", 28347 /* ETPPB_CFG_EXTERNAL_STATISTICS_IDENTIFIER */ "", 28348 /* ETPPB_CFG_EXTERNAL_STATISTICS_OPCODE_SIZE */ "", 28349 /* ETPPB_CFG_FHEI_TYPE_CPU_TRAP */ "", 28350 /* ETPPB_CFG_FORWARD_CODE_IPV4_OR_IPV6 */ "", 28351 /* ETPPB_CFG_IEEE_1588_MAC_ENABLE */ "", 28352 /* ETPPB_CFG_IEEE_1588_RECORD_TS */ "", 28353 /* ETPPB_CFG_IEEE_1588_TS_OFFSET_FIX */ "", 28354 /* ETPPB_CFG_IEEE_1588_TX_STAMP_CF */ "", 28355 /* ETPPB_CFG_IEEE_OSTS_PER_PORT_EN */ "", 28356 /* ETPPB_CFG_MAP_REMARK_PROFILE_QOS_DP */ "", 28357 /* ETPPB_CFG_MAP_REMARK_PROFILE_QOS_VAR */ "", 28358 /* ETPPB_CFG_MEMBERSHIP_PER_FWD_CODE */ "", 28359 /* ETPPB_CFG_MEMBERSHIP_PER_PORT_EN */ "", 28360 /* ETPPB_CFG_MEMBERSHIP_TRAP_PARAMS */ "", 28361 /* ETPPB_CFG_MIRROR_ACTION_NULL_PROFILE */ "", 28362 /* ETPPB_CFG_MPLS_CONTROL_WORD */ "", 28363 /* ETPPB_CFG_OAM_TYPE */ "", 28364 /* ETPPB_CFG_OVERRIDE_PIPE_QOS_VALUES */ "", 28365 /* ETPPB_CFG_PIPE_MAPPED_TTL_VARIABLE_MAP */ "", 28366 /* ETPPB_CFG_STAT_METADATA_CURRENT_PROTOCOL_TYPE */ "", 28367 /* ETPPB_CFG_STP_STATE_PER_FWD_CODE */ "", 28368 /* ETPPB_CFG_STP_TRAP_PARAMS */ "", 28369 /* ETPPB_CFG_TRAP_BYTES_TO_ADD */ "", 28370 /* ETPPB_CFG_TRAP_DP_EXTERNAL_SHIFT */ "", 28371 /* ETPPB_CFG_TRAP_DP_INTERNAL_SHIFT */ "", 28372 /* ETPPB_CFG_TRAP_DROP_EXTERNAL_SHIFT */ "", 28373 /* ETPPB_CFG_TRAP_DROP_INTERNAL_SHIFT */ "", 28374 /* ETPPB_CFG_TRAP_ECN_EXTERNAL_SHIFT */ "", 28375 /* ETPPB_CFG_TRAP_ECN_INTERNAL_SHIFT */ "", 28376 /* ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_METADATA_SHIFT */ "", 28377 /* ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_0_SHIFT */ "", 28378 /* ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_1_SHIFT */ "", 28379 /* ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_2_SHIFT */ "", 28380 /* ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OBJ_3_SHIFT */ "", 28381 /* ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_OPCODE_SHIFT */ "", 28382 /* ETPPB_CFG_TRAP_EXTERNAL_STATISTICS_PACKET_SIZE_SHIFT */ "", 28383 /* ETPPB_CFG_TRAP_MC_EXTERNAL_SHIFT */ "", 28384 /* ETPPB_CFG_TRAP_MC_INTERNAL_SHIFT */ "", 28385 /* ETPPB_CFG_TRAP_OBJ_0_SHIFT */ "", 28386 /* ETPPB_CFG_TRAP_OBJ_1_SHIFT */ "", 28387 /* ETPPB_CFG_TRAP_OBJ_2_SHIFT */ "", 28388 /* ETPPB_CFG_TRAP_OBJ_3_SHIFT */ "", 28389 /* ETPPB_CFG_TRAP_OBJ_4_SHIFT */ "", 28390 /* ETPPB_CFG_TRAP_OBJ_5_SHIFT */ "", 28391 /* ETPPB_CFG_TRAP_OBJ_6_SHIFT */ "", 28392 /* ETPPB_CFG_TRAP_OBJ_7_SHIFT */ "", 28393 /* ETPPB_CFG_TRAP_OBJ_8_SHIFT */ "", 28394 /* ETPPB_CFG_TRAP_OBJ_9_SHIFT */ "", 28395 /* ETPPB_CFG_TRAP_PORT_EXTERNAL_SHIFT */ "", 28396 /* ETPPB_CFG_TRAP_PORT_INTERNAL_SHIFT */ "", 28397 /* ETPPB_CFG_TRAP_TC_EXTERNAL_SHIFT */ "", 28398 /* ETPPB_CFG_TRAP_TC_INTERNAL_SHIFT */ "", 28399 /* ETPPB_CFG_TS_UDP_ENCAP */ "", 28400 /* ETPPB_CFG_TTL_MODEL_PIPE_MAP */ "", 28401 /* ETPPB_CFG_VID */ "", 28402 /* ETPPB_DEVICE_CFG_PORT_MTU_EN */ "", 28403 /* ETPPB_DEVICE_CFG_TRAP_FUNCTIONS_ENABLE */ "", 28404 /* ETPPB_ECC_1B_ERR_CNT */ "", 28405 /* ETPPB_ECC_2B_ERR_CNT */ "", 28406 /* ETPPB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 28407 /* ETPPB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 28408 /* ETPPB_ECC_INTERRUPT_REGISTER */ "", 28409 /* ETPPB_ECC_INTERRUPT_REGISTER_MASK */ "", 28410 /* ETPPB_ECC_INTERRUPT_REGISTER_TEST */ "", 28411 /* ETPPB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 28412 /* ETPPB_ENC_1_CONTEXT_STATUS */ "", 28413 /* ETPPB_ENC_2_CONTEXT_STATUS */ "", 28414 /* ETPPB_ENC_3_CONTEXT_STATUS */ "", 28415 /* ETPPB_ENC_4_CONTEXT_STATUS */ "", 28416 /* ETPPB_ENC_5_CONTEXT_STATUS */ "", 28417 /* ETPPB_ENC_DEVICE_CONFIGS */ "", 28418 /* ETPPB_ERROR_INITIATION_DATA */ "", 28419 /* ETPPB_ETPPB_INT_REG */ "", 28420 /* ETPPB_ETPPB_INT_REG_MASK */ "", 28421 /* ETPPB_ETPPB_INT_REG_TEST */ "", 28422 /* ETPPB_FIFO_ALMOST_FULL_THRESHOLD */ "", 28423 /* ETPPB_FWD_CONTEXT_STATUS */ "", 28424 /* ETPPB_GTIMER_CONFIGURATION */ "", 28425 /* ETPPB_GTIMER_CYCLE */ "", 28426 /* ETPPB_INDIRECT_COMMAND */ "", 28427 /* ETPPB_INDIRECT_COMMAND_ADDRESS */ "", 28428 /* ETPPB_INDIRECT_COMMAND_RD_DATA */ "", 28429 /* ETPPB_INDIRECT_COMMAND_WIDE_MEM */ "", 28430 /* ETPPB_INDIRECT_COMMAND_WR_DATA */ "", 28431 /* ETPPB_INDIRECT_FORCE_BUBBLE */ "", 28432 /* ETPPB_INTERRUPT_MASK_REGISTER */ "", 28433 /* ETPPB_INTERRUPT_REGISTER */ "", 28434 /* ETPPB_INTERRUPT_REGISTER_TEST */ "", 28435 /* ETPPB_MAP_STS_TO_INTERFACE */ "", 28436 /* ETPPB_MAP_STS_TO_TYPE */ "", 28437 /* ETPPB_MIRROR_ACTION_TABLE */ "", 28438 /* ETPPB_NETWORK_OFFSET */ "", 28439 /* ETPPB_NUM_ENTRIES_ENCAPSULATION_2_DATA_FIFO */ "", 28440 /* ETPPB_NUM_ENTRIES_ENCAPSULATION_3_DATA_FIFO */ "", 28441 /* ETPPB_NUM_ENTRIES_ENCAPSULATION_4_DATA_FIFO */ "", 28442 /* ETPPB_NUM_ENTRIES_ENCAPSULATION_5_DATA_FIFO */ "", 28443 /* ETPPB_NUM_ENTRIES_TRAP_BYPASS_FIFO */ "", 28444 /* ETPPB_NUM_ENTRIES_TRAP_ORIGINAL_FTMH_FIFO */ "", 28445 /* ETPPB_PARITY_ERR_CNT */ "", 28446 /* ETPPB_PAR_ERR_MEM_MASK */ "", 28447 /* ETPPB_PCMI_0 */ "", 28448 /* ETPPB_PCMI_1 */ "", 28449 /* ETPPB_PCMI_2 */ "", 28450 /* ETPPB_PCMI_3 */ "", 28451 /* ETPPB_PCMI_4 */ "", 28452 /* ETPPB_PCMI_0_S */ "", 28453 /* ETPPB_PCMI_0_T */ "", 28454 /* ETPPB_PCMI_1_S */ "", 28455 /* ETPPB_PCMI_1_T */ "", 28456 /* ETPPB_PCMI_2_S */ "", 28457 /* ETPPB_PCMI_2_T */ "", 28458 /* ETPPB_PCMI_3_S */ "", 28459 /* ETPPB_PCMI_3_T */ "", 28460 /* ETPPB_PCMI_4_S */ "", 28461 /* ETPPB_PCMI_4_T */ "", 28462 /* ETPPB_QOS_MODEL_MAPPING_TABLE */ "", 28463 /* ETPPB_RCY_CMD_MAP */ "", 28464 /* ETPPB_REG_0103 */ "", 28465 /* ETPPB_REG_0300 */ "", 28466 /* ETPPB_REG_0301 */ "", 28467 /* ETPPB_REG_0315 */ "", 28468 /* ETPPB_REG_0320 */ "", 28469 /* ETPPB_REG_0321 */ "", 28470 /* ETPPB_REG_0335 */ "", 28471 /* ETPPB_REG_0340 */ "", 28472 /* ETPPB_REG_0341 */ "", 28473 /* ETPPB_REG_0355 */ "", 28474 /* ETPPB_REG_0360 */ "", 28475 /* ETPPB_REG_0361 */ "", 28476 /* ETPPB_REG_0520 */ "", 28477 /* ETPPB_REG_0521 */ "", 28478 /* ETPPB_REG_0535 */ "", 28479 /* ETPPB_REG_00A4 */ "", 28480 /* ETPPB_REG_00A6 */ "", 28481 /* ETPPB_REG_00AA */ "", 28482 /* ETPPB_REG_00C2 */ "", 28483 /* ETPPB_REG_00C5 */ "", 28484 /* ETPPB_REG_00C6 */ "", 28485 /* ETPPB_REG_00E8 */ "", 28486 /* ETPPB_REG_00E9 */ "", 28487 /* ETPPB_REG_00EB */ "", 28488 /* ETPPB_REG_00EE */ "", 28489 /* ETPPB_REG_00F0 */ "", 28490 /* ETPPB_REG_00F1 */ "", 28491 /* ETPPB_REG_00F2 */ "", 28492 /* ETPPB_REG_F000 */ "", 28493 /* ETPPB_RESERVED_MIRROR_ADDR */ "", 28494 /* ETPPB_RESERVED_MTCD */ "", 28495 /* ETPPB_RESERVED_MTCP */ "", 28496 /* ETPPB_RESERVED_SPARE_0 */ "", 28497 /* ETPPB_RESERVED_SPARE_1 */ "", 28498 /* ETPPB_RESERVED_SPARE_2 */ "", 28499 /* ETPPB_RESERVED_SPARE_3 */ "", 28500 /* ETPPB_SBUS_BROADCAST_ID */ "", 28501 /* ETPPB_SBUS_LAST_IN_CHAIN */ "", 28502 /* ETPPB_SNOOP_ACTION_TABLE */ "", 28503 /* ETPPB_SPECIAL_CLOCK_CONTROLS */ "", 28504 /* ETPPB_TERM_CONTEXT_STATUS */ "", 28505 /* ETPPB_TRAP_ADDITIONAL_DATA_STATUS */ "", 28506 /* ETPPB_TRAP_CONTEXT_STATUS */ "", 28507 /* ETPPC_CFG_CW_PREVENT_MAP */ "", 28508 /* ETPPC_CFG_DEFAULT_INVALID_ETPS */ "", 28509 /* ETPPC_CFG_DONT_COUNT */ "", 28510 /* ETPPC_CFG_DONT_METER */ "", 28511 /* ETPPC_CFG_DP_METER_CMD */ "", 28512 /* ETPPC_CFG_EES_TYPE_VALID_FOR_VSD */ "", 28513 /* ETPPC_CFG_ENTRY_IS_EM_BUSTER */ "", 28514 /* ETPPC_CFG_ESEM_1_SHIFT_VAL */ "", 28515 /* ETPPC_CFG_ESEM_2_SHIFT_VAL */ "", 28516 /* ETPPC_CFG_ESEM_3_SHIFT_VAL */ "", 28517 /* ETPPC_CFG_FINAL_DP_TRAP */ "", 28518 /* ETPPC_CFG_FLOW_ID_EXIST */ "", 28519 /* ETPPC_CFG_FORWARD_CODE_IPV4_OR_IPV6 */ "", 28520 /* ETPPC_CFG_FWD_EGRESS_DO_NOT_TTL_DECREMENT */ "", 28521 /* ETPPC_CFG_IEEE_1588_RX_STAMP */ "", 28522 /* ETPPC_CFG_INVALID_OAM_LIF */ "", 28523 /* ETPPC_CFG_IS_TTL_MODEL_INHERIT_PHP */ "", 28524 /* ETPPC_CFG_KEEP_ING_ECID */ "", 28525 /* ETPPC_CFG_LATENCY_TRAP_PARAMS */ "", 28526 /* ETPPC_CFG_LAYER_PROTOCOL_IPV4 */ "", 28527 /* ETPPC_CFG_LAYER_PROTOCOL_IPV6 */ "", 28528 /* ETPPC_CFG_LAYER_PROTOCOL_MPLS */ "", 28529 /* ETPPC_CFG_LAYER_PROTOCOL_OAM */ "", 28530 /* ETPPC_CFG_MAP_FIRST_NIBBLE */ "", 28531 /* ETPPC_CFG_MAP_FWD_LAYER_PROTOCOL */ "", 28532 /* ETPPC_CFG_MAP_FWD_PLUS_1_EXPLICIT_REMARK_PROFILE */ "", 28533 /* ETPPC_CFG_MAP_FWD_PLUS_1_PROTOCOL */ "", 28534 /* ETPPC_CFG_MAP_FWD_PLUS_1_REMARK_PROFILE */ "", 28535 /* ETPPC_CFG_MAP_OUTLIF_PROFILE_TO_L_2_CP_PROFILE */ "", 28536 /* ETPPC_CFG_MAP_REMARK_PROFILE_QOS_DP */ "", 28537 /* ETPPC_CFG_MAP_REMARK_PROFILE_QOS_VAR */ "", 28538 /* ETPPC_CFG_MAP_STACK_ACTION_PROFILE_IDX */ "", 28539 /* ETPPC_CFG_METERING_TRAP_PARAMS */ "", 28540 /* ETPPC_CFG_METER_OFFSET_MAP */ "", 28541 /* ETPPC_CFG_MPLS_CONTROL_WORD */ "", 28542 /* ETPPC_CFG_OAM_PORT_PROFILE */ "", 28543 /* ETPPC_CFG_OAM_TRAP_LIF_PROFILE_MAP */ "", 28544 /* ETPPC_CFG_OVERRIDE_PIPE_QOS_VALUES */ "", 28545 /* ETPPC_CFG_PEM_ESEM_DEFAULT_RESULT_PROFILE */ "", 28546 /* ETPPC_CFG_PHANTOM_QUEUES_ENABLE */ "", 28547 /* ETPPC_CFG_PIPE_MAPPED_TTL_VARIABLE_MAP */ "", 28548 /* ETPPC_CFG_PRIORITY_MAP_OAM_LIF_PROFILE */ "", 28549 /* ETPPC_CFG_PROTECTION_DB_TRAP_PARAMS */ "", 28550 /* ETPPC_CFG_QOS_MODEL_IS_PIPE */ "", 28551 /* ETPPC_CFG_REMARK_PROTOCOL_PROFILE */ "", 28552 /* ETPPC_CFG_SPLIT_HORIZON_FILTER */ "", 28553 /* ETPPC_CFG_SPLIT_HORIZON_PER_FWD_CODE */ "", 28554 /* ETPPC_CFG_SPLIT_HORIZON_PER_OUTLIF_PROFILE */ "", 28555 /* ETPPC_CFG_SPLIT_HORIZON_PER_OUT_PP_PORT */ "", 28556 /* ETPPC_CFG_SPLIT_HORIZON_TRAP_PARAMS */ "", 28557 /* ETPPC_CFG_STACK_MIRROR_ACTION_PROFILE */ "", 28558 /* ETPPC_CFG_STACK_TRAP_1_TRAP_PARAMS */ "", 28559 /* ETPPC_CFG_STACK_TRAP_2_TRAP_PARAMS */ "", 28560 /* ETPPC_CFG_STAT_METADATA_CURRENT_PROTOCOL_TYPE */ "", 28561 /* ETPPC_CFG_STAT_OBJ_CMD_TO_IS_METER */ "", 28562 /* ETPPC_CFG_STAT_OBJ_CMD_TO_METER_IF */ "", 28563 /* ETPPC_CFG_STAT_OBJ_CMD_TO_METER_QOS_PROFILE */ "", 28564 /* ETPPC_CFG_SWITCH_ID */ "", 28565 /* ETPPC_CFG_TAIL_EDITING_BITMAP */ "", 28566 /* ETPPC_CFG_TAIL_EDITING_SIZE */ "", 28567 /* ETPPC_CFG_TERMINATION_FWD_CODE_EN */ "", 28568 /* ETPPC_CFG_TTL_MODEL_PIPE_MAP */ "", 28569 /* ETPPC_DEVICE_CFG_TS_UDP_ENCAP */ "", 28570 /* ETPPC_ECC_1B_ERR_CNT */ "", 28571 /* ETPPC_ECC_2B_ERR_CNT */ "", 28572 /* ETPPC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 28573 /* ETPPC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 28574 /* ETPPC_ECC_INTERRUPT_REGISTER */ "", 28575 /* ETPPC_ECC_INTERRUPT_REGISTER_MASK */ "", 28576 /* ETPPC_ECC_INTERRUPT_REGISTER_TEST */ "", 28577 /* ETPPC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 28578 /* ETPPC_ENC_DEVICE_CONFIGS */ "", 28579 /* ETPPC_ERROR_INITIATION_DATA */ "", 28580 /* ETPPC_ETHERNET_FWD_CODE */ "", 28581 /* ETPPC_ETPPC_INT_REG */ "", 28582 /* ETPPC_ETPPC_INT_REG_MASK */ "", 28583 /* ETPPC_ETPPC_INT_REG_TEST */ "", 28584 /* ETPPC_ETPPC_SAMPLE_VALIDS */ "", 28585 /* ETPPC_ETPP_TERM_INT_REG */ "", 28586 /* ETPPC_ETPP_TERM_INT_REG_MASK */ "", 28587 /* ETPPC_ETPP_TERM_INT_REG_TEST */ "", 28588 /* ETPPC_ETPS_ENTRY_IS_AC */ "", 28589 /* ETPPC_GTIMER_CONFIGURATION */ "", 28590 /* ETPPC_GTIMER_CYCLE */ "", 28591 /* ETPPC_INDIRECT_COMMAND */ "", 28592 /* ETPPC_INDIRECT_COMMAND_ADDRESS */ "", 28593 /* ETPPC_INDIRECT_COMMAND_RD_DATA */ "", 28594 /* ETPPC_INDIRECT_COMMAND_WIDE_MEM */ "", 28595 /* ETPPC_INDIRECT_COMMAND_WR_DATA */ "", 28596 /* ETPPC_INDIRECT_FORCE_BUBBLE */ "", 28597 /* ETPPC_INTERRUPT_MASK_REGISTER */ "", 28598 /* ETPPC_INTERRUPT_REGISTER */ "", 28599 /* ETPPC_INTERRUPT_REGISTER_TEST */ "", 28600 /* ETPPC_IPV4_MC_FWD_CODE */ "", 28601 /* ETPPC_IPV4_UC_FWD_CODE */ "", 28602 /* ETPPC_IPV6_MC_FWD_CODE */ "", 28603 /* ETPPC_IPV6_UC_FWD_CODE */ "", 28604 /* ETPPC_JERICHO_COMPATIBLE_REGISTERS */ "", 28605 /* ETPPC_MAP_STRENGTH_TO_OAM_INJECTION */ "", 28606 /* ETPPC_MEF_L_2_CP_TRANSPARANT_BITMAP */ "", 28607 /* ETPPC_MPLS_FWD_CODE */ "", 28608 /* ETPPC_NUM_ENTRIES_BIER_BIT_MASK_FIFO */ "", 28609 /* ETPPC_NUM_ENTRIES_ENCAPSULATION_1_DATA_FIFO */ "", 28610 /* ETPPC_NUM_ENTRIES_ESEM_RESULT_FIFO */ "", 28611 /* ETPPC_NUM_ENTRIES_EXEM_RESULT_FIFO */ "", 28612 /* ETPPC_NUM_ENTRIES_FWD_BYPASS_FIFO */ "", 28613 /* ETPPC_NUM_ENTRIES_OEM_RESULT_FIFO */ "", 28614 /* ETPPC_NUM_ENTRIES_TERM_PIPE_FIFO_1 */ "", 28615 /* ETPPC_NUM_ENTRIES_TERM_PIPE_FIFO_2 */ "", 28616 /* ETPPC_NUM_ENTRIES_VSD_RESULT_FIFO */ "", 28617 /* ETPPC_OAM_COUNTER_IN_RANGE_CFG_0 */ "", 28618 /* ETPPC_OAM_COUNTER_IN_RANGE_CFG_1 */ "", 28619 /* ETPPC_OAM_COUNTER_IN_RANGE_CFG_2 */ "", 28620 /* ETPPC_OAM_COUNTER_NOT_IN_RANGE_CFG_0 */ "", 28621 /* ETPPC_OAM_COUNTER_NOT_IN_RANGE_CFG_1 */ "", 28622 /* ETPPC_OAM_COUNTER_NOT_IN_RANGE_CFG_2 */ "", 28623 /* ETPPC_OAM_COUNTER_RANGE */ "", 28624 /* ETPPC_OAM_DEFAULT_ACC_MEP_PROFILES */ "", 28625 /* ETPPC_OAM_DEFAULT_COUNTERS */ "", 28626 /* ETPPC_OAM_DEFAULT_INTERFACE */ "", 28627 /* ETPPC_OAM_DEFAULT_MP_TYPE_VECTOR */ "", 28628 /* ETPPC_OAM_LIF_DB_ACCESS_PROFILE_EN_0 */ "", 28629 /* ETPPC_OAM_LIF_DB_ACCESS_PROFILE_EN_1 */ "", 28630 /* ETPPC_OAM_LIF_DB_ACCESS_PROFILE_EN_2 */ "", 28631 /* ETPPC_OAM_LM_COUNTER_READ_IDX_SEL_MEM */ "", 28632 /* ETPPC_OAM_PACKET_INJECTED_BITMAP */ "", 28633 /* ETPPC_OAM_PRIORITY_MAP */ "", 28634 /* ETPPC_OAM_PROCESS_MAP */ "", 28635 /* ETPPC_OAM_VMV_SHIFT_VALUE_MAP */ "", 28636 /* ETPPC_OUTLIF_ORIENTATION_MAPPING */ "", 28637 /* ETPPC_PARITY_ERR_CNT */ "", 28638 /* ETPPC_PAR_ERR_MEM_MASK */ "", 28639 /* ETPPC_PCMI_0 */ "", 28640 /* ETPPC_PCMI_1 */ "", 28641 /* ETPPC_PCMI_2 */ "", 28642 /* ETPPC_PCMI_3 */ "", 28643 /* ETPPC_PCMI_4 */ "", 28644 /* ETPPC_PCMI_0_S */ "", 28645 /* ETPPC_PCMI_0_T */ "", 28646 /* ETPPC_PCMI_1_S */ "", 28647 /* ETPPC_PCMI_1_T */ "", 28648 /* ETPPC_PCMI_2_S */ "", 28649 /* ETPPC_PCMI_2_T */ "", 28650 /* ETPPC_PCMI_3_S */ "", 28651 /* ETPPC_PCMI_3_T */ "", 28652 /* ETPPC_PCMI_4_S */ "", 28653 /* ETPPC_PCMI_4_T */ "", 28654 /* ETPPC_PHP_MAP_FWD_CODE */ "", 28655 /* ETPPC_QOS_MODEL_MAPPING_TABLE */ "", 28656 /* ETPPC_REG_0300 */ "", 28657 /* ETPPC_REG_0301 */ "", 28658 /* ETPPC_REG_0315 */ "", 28659 /* ETPPC_REG_0320 */ "", 28660 /* ETPPC_REG_0321 */ "", 28661 /* ETPPC_REG_0330 */ "", 28662 /* ETPPC_REG_0331 */ "", 28663 /* ETPPC_REG_0335 */ "", 28664 /* ETPPC_REG_0345 */ "", 28665 /* ETPPC_REG_00A4 */ "", 28666 /* ETPPC_REG_00A6 */ "", 28667 /* ETPPC_REG_00AA */ "", 28668 /* ETPPC_REG_00C2 */ "", 28669 /* ETPPC_REG_00C5 */ "", 28670 /* ETPPC_REG_00C6 */ "", 28671 /* ETPPC_REG_00E8 */ "", 28672 /* ETPPC_REG_00E9 */ "", 28673 /* ETPPC_REG_00EB */ "", 28674 /* ETPPC_REG_00EE */ "", 28675 /* ETPPC_REG_00F0 */ "", 28676 /* ETPPC_REG_00F1 */ "", 28677 /* ETPPC_REG_00F2 */ "", 28678 /* ETPPC_REG_F000 */ "", 28679 /* ETPPC_RESERVED_MIRROR_ADDR */ "", 28680 /* ETPPC_RESERVED_MTCD */ "", 28681 /* ETPPC_RESERVED_MTCP */ "", 28682 /* ETPPC_RESERVED_SPARE_0 */ "", 28683 /* ETPPC_RESERVED_SPARE_1 */ "", 28684 /* ETPPC_RESERVED_SPARE_2 */ "", 28685 /* ETPPC_RESERVED_SPARE_3 */ "", 28686 /* ETPPC_SBUS_BROADCAST_ID */ "", 28687 /* ETPPC_SBUS_LAST_IN_CHAIN */ "", 28688 /* ETPPC_SPECIAL_CLOCK_CONTROLS */ "", 28689 /* ETPPC_STATISTICS_FWD_CODE_TO_PROTOCOL_TYPE */ "", 28690 /* ETPPC_XOR_INIT_DONE */ "", 28691 /* ETRAP_COLOR_EN_INT_PRI */ "", 28692 /* ETRAP_COLOR_EN_PKT_TYPE */ "", 28693 /* ETRAP_DEBUG_CTRL */ "", 28694 /* ETRAP_DEBUG_CTRL_PIPE0 */ "", 28695 /* ETRAP_DEBUG_CTRL_PIPE1 */ "", 28696 /* ETRAP_DEBUG_CTRL_PIPE2 */ "", 28697 /* ETRAP_DEBUG_CTRL_PIPE3 */ "", 28698 /* ETRAP_DEBUG_CTRL_PIPE4 */ "", 28699 /* ETRAP_DEBUG_CTRL_PIPE5 */ "", 28700 /* ETRAP_DEBUG_CTRL_PIPE6 */ "", 28701 /* ETRAP_DEBUG_CTRL_PIPE7 */ "", 28702 /* ETRAP_EN_COR_ERR_RPT */ "", 28703 /* ETRAP_FILT_CFG */ "", 28704 /* ETRAP_FILT_EXCEED_CTR */ "", 28705 /* ETRAP_FILT_EXCEED_CTR_PIPE0 */ "", 28706 /* ETRAP_FILT_EXCEED_CTR_PIPE1 */ "", 28707 /* ETRAP_FILT_EXCEED_CTR_PIPE2 */ "", 28708 /* ETRAP_FILT_EXCEED_CTR_PIPE3 */ "", 28709 /* ETRAP_FILT_EXCEED_CTR_PIPE4 */ "", 28710 /* ETRAP_FILT_EXCEED_CTR_PIPE5 */ "", 28711 /* ETRAP_FILT_EXCEED_CTR_PIPE6 */ "", 28712 /* ETRAP_FILT_EXCEED_CTR_PIPE7 */ "", 28713 /* ETRAP_FILT_THRESH */ "", 28714 /* ETRAP_FLOW_CFG */ "", 28715 /* ETRAP_FLOW_DETECT_CTR */ "", 28716 /* ETRAP_FLOW_DETECT_CTR_PIPE0 */ "", 28717 /* ETRAP_FLOW_DETECT_CTR_PIPE1 */ "", 28718 /* ETRAP_FLOW_DETECT_CTR_PIPE2 */ "", 28719 /* ETRAP_FLOW_DETECT_CTR_PIPE3 */ "", 28720 /* ETRAP_FLOW_DETECT_CTR_PIPE4 */ "", 28721 /* ETRAP_FLOW_DETECT_CTR_PIPE5 */ "", 28722 /* ETRAP_FLOW_DETECT_CTR_PIPE6 */ "", 28723 /* ETRAP_FLOW_DETECT_CTR_PIPE7 */ "", 28724 /* ETRAP_FLOW_ELEPH_THRESHOLD */ "", 28725 /* ETRAP_FLOW_ELEPH_THR_RED */ "", 28726 /* ETRAP_FLOW_ELEPH_THR_YEL */ "", 28727 /* ETRAP_FLOW_INS_FAIL_CTR */ "", 28728 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE0 */ "", 28729 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE1 */ "", 28730 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE2 */ "", 28731 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE3 */ "", 28732 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE4 */ "", 28733 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE5 */ "", 28734 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE6 */ "", 28735 /* ETRAP_FLOW_INS_FAIL_CTR_PIPE7 */ "", 28736 /* ETRAP_FLOW_INS_SUCCESS_CTR */ "", 28737 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE0 */ "", 28738 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE1 */ "", 28739 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE2 */ "", 28740 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE3 */ "", 28741 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE4 */ "", 28742 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE5 */ "", 28743 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE6 */ "", 28744 /* ETRAP_FLOW_INS_SUCCESS_CTR_PIPE7 */ "", 28745 /* ETRAP_FLOW_RESET_THRESHOLD */ "", 28746 /* ETRAP_LKUP_EN_INT_PRI */ "", 28747 /* ETRAP_LKUP_EN_PKT_TYPE */ "", 28748 /* ETRAP_MONITOR_CONFIG */ "", 28749 /* ETRAP_MONITOR_MIRROR_CONFIG */ "", 28750 /* ETRAP_MSEC */ "", 28751 /* ETRAP_MSEC_PIPE0 */ "", 28752 /* ETRAP_MSEC_PIPE1 */ "", 28753 /* ETRAP_MSEC_PIPE2 */ "", 28754 /* ETRAP_MSEC_PIPE3 */ "", 28755 /* ETRAP_MSEC_PIPE4 */ "", 28756 /* ETRAP_MSEC_PIPE5 */ "", 28757 /* ETRAP_MSEC_PIPE6 */ "", 28758 /* ETRAP_MSEC_PIPE7 */ "", 28759 /* ETRAP_PROC_EN */ "", 28760 /* ETRAP_PROC_EN_2 */ "", 28761 /* ETRAP_QUEUE_EN_INT_PRI */ "", 28762 /* ETRAP_QUEUE_EN_PKT_TYPE */ "", 28763 /* ETRAP_SAMPLE_ADDR */ "", 28764 /* ETRAP_SAMPLE_ADDR_PIPE0 */ "", 28765 /* ETRAP_SAMPLE_ADDR_PIPE1 */ "", 28766 /* ETRAP_SAMPLE_ADDR_PIPE2 */ "", 28767 /* ETRAP_SAMPLE_ADDR_PIPE3 */ "", 28768 /* ETRAP_SAMPLE_ADDR_PIPE4 */ "", 28769 /* ETRAP_SAMPLE_ADDR_PIPE5 */ "", 28770 /* ETRAP_SAMPLE_ADDR_PIPE6 */ "", 28771 /* ETRAP_SAMPLE_ADDR_PIPE7 */ "", 28772 /* ETRAP_SER_CONTROL */ "", 28773 /* ETRAP_TIMEBASE */ "", 28774 /* ETRAP_USEC */ "", 28775 /* ETRAP_USEC_PIPE0 */ "", 28776 /* ETRAP_USEC_PIPE1 */ "", 28777 /* ETRAP_USEC_PIPE2 */ "", 28778 /* ETRAP_USEC_PIPE3 */ "", 28779 /* ETRAP_USEC_PIPE4 */ "", 28780 /* ETRAP_USEC_PIPE5 */ "", 28781 /* ETRAP_USEC_PIPE6 */ "", 28782 /* ETRAP_USEC_PIPE7 */ "", 28783 /* ETU_ATE_CONFIG_REG2_IS */ "", 28784 /* ETU_BIST_CTL */ "", 28785 /* ETU_BIST_PATTERN0 */ "", 28786 /* ETU_BIST_PATTERN1 */ "", 28787 /* ETU_BIST_STS */ "", 28788 /* ETU_BKGND_PROC_ERR_INFO */ "", 28789 /* ETU_BKGND_PROC_SEC_INFO */ "", 28790 /* ETU_CONFIG0 */ "", 28791 /* ETU_CONFIG1 */ "", 28792 /* ETU_CONFIG2 */ "", 28793 /* ETU_CONFIG3 */ "", 28794 /* ETU_CONFIG4 */ "", 28795 /* ETU_CP_CMD_ERR_STATE */ "", 28796 /* ETU_CP_TIMEOUT_LATENCY */ "", 28797 /* ETU_DBG_IPIPE_ERR_RSP_COUNT */ "", 28798 /* ETU_DBG_IPIPE_REQ_RSP_COUNT */ "", 28799 /* ETU_DBG_PD_TM */ "", 28800 /* ETU_DBG_SM */ "", 28801 /* ETU_DDR72_CONFIG_REG1_IS */ "", 28802 /* ETU_DDR72_CONFIG_REG2_IS */ "", 28803 /* ETU_DDR72_CONFIG_REG3_IS */ "", 28804 /* ETU_DDR72_STATUS_REG1_IS */ "", 28805 /* ETU_DDR72_STATUS_REG2_IS */ "", 28806 /* ETU_DDR72_STATUS_REG3_IS */ "", 28807 /* ETU_DFT_CTL */ "", 28808 /* ETU_DFT_CTL2 */ "", 28809 /* ETU_DTU_ATE_CAPT_DAT */ "", 28810 /* ETU_DTU_ATE_CONFIG_REG1_IS */ "", 28811 /* ETU_DTU_ATE_EXP_DAT */ "", 28812 /* ETU_DTU_ATE_STS1 */ "", 28813 /* ETU_ET_INST_REQ */ "", 28814 /* ETU_ET_INST_STATUS */ "", 28815 /* ETU_EXT_L2_BULK_INFO */ "", 28816 /* ETU_EXT_L2_CMD_ERR_INFO1 */ "", 28817 /* ETU_EXT_L2_CMD_ERR_INFO2 */ "", 28818 /* ETU_GLOBAL_INTR_CLEAR */ "", 28819 /* ETU_GLOBAL_INTR_ENABLE */ "", 28820 /* ETU_GLOBAL_INTR_STS */ "", 28821 /* ETU_INST_OPC */ "", 28822 /* ETU_INTR_CLEAR */ "", 28823 /* ETU_INTR_ENABLE */ "", 28824 /* ETU_INTR_STATUS */ "", 28825 /* ETU_INT_MEM_RST */ "", 28826 /* ETU_L2MODFIFO_STATUS */ "", 28827 /* ETU_L2SEARCH72_INST */ "", 28828 /* ETU_LTE_BIST_CTL */ "", 28829 /* ETU_LTE_BIST_REF_SEARCH0 */ "", 28830 /* ETU_LTE_BIST_REF_SEARCH1 */ "", 28831 /* ETU_LTE_BIST_STATUS */ "", 28832 /* ETU_LUREQFIFO_RS_CTL */ "", 28833 /* ETU_LUREQFIFO_RS_STATUS */ "", 28834 /* ETU_PP_XLAT0_PERR_INFO */ "", 28835 /* ETU_PP_XLAT1_PERR_INFO */ "", 28836 /* ETU_RDDATA72_INST */ "", 28837 /* ETU_RDMASK72_INST */ "", 28838 /* ETU_RRFE_WAIT_FULL_INFO */ "", 28839 /* ETU_RRFE_WAIT_PENDING0_INFO */ "", 28840 /* ETU_RRFE_WAIT_TIMER */ "", 28841 /* ETU_RSLT_DAT0 */ "", 28842 /* ETU_RSLT_DAT1 */ "", 28843 /* ETU_RSLT_DAT2 */ "", 28844 /* ETU_RX_CW_ERR_CHANOUT */ "", 28845 /* ETU_RX_CW_ERR_DW0_HI */ "", 28846 /* ETU_RX_CW_ERR_DW0_LO */ "", 28847 /* ETU_RX_CW_ERR_DW1_HI */ "", 28848 /* ETU_RX_CW_ERR_DW1_LO */ "", 28849 /* ETU_RX_CW_ERR_INFO1 */ "", 28850 /* ETU_RX_CW_ERR_INFO2 */ "", 28851 /* ETU_RX_ERS0_CHANOUT */ "", 28852 /* ETU_RX_ERS0_DW0_HI */ "", 28853 /* ETU_RX_ERS0_DW0_LO */ "", 28854 /* ETU_RX_ERS0_DW1_HI */ "", 28855 /* ETU_RX_ERS0_DW1_LO */ "", 28856 /* ETU_RX_ERS0_INFO2 */ "", 28857 /* ETU_RX_RSP_FIFO_CTL */ "", 28858 /* ETU_RX_RSP_FIFO_EV_DBE_STS */ "", 28859 /* ETU_RX_RSP_FIFO_EV_SBE_STS */ "", 28860 /* ETU_RX_RSP_FIFO_INTR_CLR */ "", 28861 /* ETU_RX_RSP_FIFO_INTR_ENABLE */ "", 28862 /* ETU_RX_RSP_FIFO_INTR_STS */ "", 28863 /* ETU_RX_RSP_FIFO_OD_DBE_STS */ "", 28864 /* ETU_RX_RSP_FIFO_OD_SBE_STS */ "", 28865 /* ETU_RX_RSP_FIFO_STS */ "", 28866 /* ETU_S0_RBUS_PERR_INFO */ "", 28867 /* ETU_S1_RBUS_PERR_INFO */ "", 28868 /* ETU_SBUS_CMD_ERR_INFO1 */ "", 28869 /* ETU_SBUS_CMD_ERR_INFO2 */ "", 28870 /* ETU_SBUS_CMD_SEC_INFO */ "", 28871 /* ETU_SEARCH0_RESULT */ "", 28872 /* ETU_SEARCH1_RESULT */ "", 28873 /* ETU_TX_CP_MAX_LATENCY */ "", 28874 /* ETU_TX_EXT_L2_MAX_LATENCY */ "", 28875 /* ETU_TX_PIPE_CTL_FIFO_CTL */ "", 28876 /* ETU_TX_PIPE_CTL_FIFO_DBE_STS */ "", 28877 /* ETU_TX_PIPE_CTL_FIFO_INTR_CLR */ "", 28878 /* ETU_TX_PIPE_CTL_FIFO_INTR_ENABLE */ "", 28879 /* ETU_TX_PIPE_CTL_FIFO_INTR_STS */ "", 28880 /* ETU_TX_PIPE_CTL_FIFO_SBE_STS */ "", 28881 /* ETU_TX_PIPE_CTL_FIFO_STS */ "", 28882 /* ETU_TX_RAW_REQ_CONTROL_WORD */ "", 28883 /* ETU_TX_REQ_FIFO_CTL */ "", 28884 /* ETU_TX_REQ_FIFO_EV_DBE_STS */ "", 28885 /* ETU_TX_REQ_FIFO_EV_SBE_STS */ "", 28886 /* ETU_TX_REQ_FIFO_INTR_CLR */ "", 28887 /* ETU_TX_REQ_FIFO_INTR_ENABLE */ "", 28888 /* ETU_TX_REQ_FIFO_INTR_STS */ "", 28889 /* ETU_TX_REQ_FIFO_OD_DBE_STS */ "", 28890 /* ETU_TX_REQ_FIFO_OD_SBE_STS */ "", 28891 /* ETU_TX_REQ_FIFO_STS */ "", 28892 /* ETU_WRDM72_INST */ "", 28893 /* ETU_WR_DB_V0_DATA0 */ "", 28894 /* ETU_WR_DB_V0_DATA1 */ "", 28895 /* ETU_WR_DB_V0_DATA2 */ "", 28896 /* ETU_WR_DB_V0_MASK0 */ "", 28897 /* ETU_WR_DB_V0_MASK1 */ "", 28898 /* ETU_WR_DB_V0_MASK2 */ "", 28899 /* EVENT_FIFO_ECC_STATUS_INTR */ "", 28900 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE0 */ "", 28901 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE1 */ "", 28902 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE2 */ "", 28903 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE3 */ "", 28904 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE4 */ "", 28905 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE5 */ "", 28906 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE6 */ "", 28907 /* EVENT_FIFO_ECC_STATUS_INTR_PIPE7 */ "", 28908 /* EVLAN_RAM_DBGCTRL */ "EVLAN_RAM_CONTROL", 28909 /* EVLAN_TM_REG_1 */ "", 28910 /* EVLAN_WW_REG_1 */ "", 28911 /* EVNT_ECC_1B_ERR_CNT */ "", 28912 /* EVNT_ECC_2B_ERR_CNT */ "", 28913 /* EVNT_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 28914 /* EVNT_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 28915 /* EVNT_ECC_INTERRUPT_REGISTER */ "", 28916 /* EVNT_ECC_INTERRUPT_REGISTER_MASK */ "", 28917 /* EVNT_ECC_INTERRUPT_REGISTER_TEST */ "", 28918 /* EVNT_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 28919 /* EVNT_ERROR_INITIATION_DATA */ "", 28920 /* EVNT_EVENTOR_INTERRUPT_MASK_REGISTER */ "", 28921 /* EVNT_EVENTOR_INTERRUPT_REGISTER */ "", 28922 /* EVNT_EVENTOR_INTERRUPT_REGISTER_TEST */ "", 28923 /* EVNT_EVENTOR_INT_BIT_TRIGGER */ "", 28924 /* EVNT_EVPCK_HEADER_STACK */ "", 28925 /* EVNT_EVPCK_HEADER_STACK_SIZE */ "", 28926 /* EVNT_EVPCK_HEADER_TIMESTAMP_SEL */ "", 28927 /* EVNT_EXT_BLOCKS_SELECTOR_CFG */ "", 28928 /* EVNT_GTIMER_CONFIGURATION */ "", 28929 /* EVNT_GTIMER_CYCLE */ "", 28930 /* EVNT_INDIRECT_COMMAND */ "", 28931 /* EVNT_INDIRECT_COMMAND_ADDRESS */ "", 28932 /* EVNT_INDIRECT_COMMAND_RD_DATA */ "", 28933 /* EVNT_INDIRECT_COMMAND_WR_DATA */ "", 28934 /* EVNT_INDIRECT_FORCE_BUBBLE */ "", 28935 /* EVNT_INTERNAL_HOST_EVENT_TRIGGER */ "", 28936 /* EVNT_INTERNAL_TOD_EVENT_VALUE */ "", 28937 /* EVNT_INTERRUPT_MASK_REGISTER */ "", 28938 /* EVNT_INTERRUPT_REGISTER */ "", 28939 /* EVNT_INTERRUPT_REGISTER_TEST */ "", 28940 /* EVNT_MACT_EVENTOR_DMA_SEL */ "", 28941 /* EVNT_MAIN_MEM_BANK_TYPE */ "", 28942 /* EVNT_MAIN_MEM_RX_PTRS */ "", 28943 /* EVNT_MAIN_MEM_TX_PTRS */ "", 28944 /* EVNT_PIPE_SELECTOR */ "", 28945 /* EVNT_REG_0041 */ "", 28946 /* EVNT_REG_0098 */ "", 28947 /* EVNT_REG_00A0 */ "", 28948 /* EVNT_REG_00A4 */ "", 28949 /* EVNT_REG_00A6 */ "", 28950 /* EVNT_REG_00AA */ "", 28951 /* EVNT_REG_00C2 */ "", 28952 /* EVNT_REG_00C5 */ "", 28953 /* EVNT_RESERVED_MIRROR_ADDR */ "", 28954 /* EVNT_RESERVED_MTCD */ "", 28955 /* EVNT_RESERVED_MTCP */ "", 28956 /* EVNT_RESERVED_SPARE_0 */ "", 28957 /* EVNT_RESERVED_SPARE_1 */ "", 28958 /* EVNT_RESERVED_SPARE_2 */ "", 28959 /* EVNT_RESERVED_SPARE_3 */ "", 28960 /* EVNT_RX_CMIC_FLEX_CMD */ "", 28961 /* EVNT_RX_EVPCK_HEADER_STACK_SIZE */ "", 28962 /* EVNT_RX_HANDLER_CMIC_STMS_STATE */ "", 28963 /* EVNT_RX_MAIN_BUFFER_TH */ "", 28964 /* EVNT_RX_MAIN_BUFFER_TIMEOUT */ "", 28965 /* EVNT_RX_SEQ_CHECK */ "", 28966 /* EVNT_RX_TO_TX_BUFFER */ "", 28967 /* EVNT_SBUS_BROADCAST_ID */ "", 28968 /* EVNT_SBUS_LAST_IN_CHAIN */ "", 28969 /* EVNT_SHARED_CMIC_ENG_POOL */ "", 28970 /* EVNT_SPECIAL_CLOCK_CONTROLS */ "", 28971 /* EVNT_TRANSMIT_ERR_HEADER_STACK */ "", 28972 /* EVNT_TRANSMIT_ERR_HEADER_STACK_SIZE */ "", 28973 /* EVNT_TRANSMIT_HEADER_STACK */ "", 28974 /* EVNT_TRANSMIT_HEADER_STACK_SIZE */ "", 28975 /* EVNT_TX_1588_TOD_SAMP */ "", 28976 /* EVNT_TX_1588_TOD_SAMP_SRC_SEL */ "", 28977 /* EVNT_TX_CMIC_FLEX_CMD */ "", 28978 /* EVNT_TX_CONTEXT_IS_FIFO_DMA */ "", 28979 /* EVNT_TX_ENG_CLEAR_BUFFER_MEM_ERR */ "", 28980 /* EVNT_TX_ENG_CONTEXT_PRIORITY_RR_VEC */ "", 28981 /* EVNT_TX_ENG_CONTEXT_QUEUE_MAX_SIZE */ "", 28982 /* EVNT_TX_ENG_CONTEXT_QUEUE_TIMEOUT_VALUE */ "", 28983 /* EVNT_TX_ENG_CONTEXT_QUEUE_TYPE */ "", 28984 /* EVNT_TX_ENG_DUMMY_PATTERN */ "", 28985 /* EVNT_TX_ENG_ERR_CONFIG */ "", 28986 /* EVNT_TX_ENG_EVENTS_CNT */ "", 28987 /* EVNT_TX_ENG_EVPCK_PADDING_ENABLE */ "", 28988 /* EVNT_TX_HANDLER_ACCEPT_UNDONE_NEW_EVENT_REQS */ "", 28989 /* EVNT_TX_HANDLER_CLEAR_CMIC_DONE_STM_ERR */ "", 28990 /* EVNT_TX_HANDLER_CMIC_STMS_STATE */ "", 28991 /* EVNT_TX_HANDLER_CUR_BUFFER_CMIC_ENGINE */ "", 28992 /* EVNT_TX_HANDLER_EXT_PRIORITY_RR_VEC */ "", 28993 /* EVNT_TX_HANDLER_ONETIME_EVENT_EN */ "", 28994 /* EVNT_TX_HANDLER_REQ_EN */ "", 28995 /* EVNT_TX_MAIN_BUFFER_TH */ "", 28996 /* EVNT_TX_MAIN_BUFFER_TIMEOUT */ "", 28997 /* EVXLT2_GBP_SID_DID_LOOKUP_MISS_POLICY */ "", 28998 /* EVXLT_RAM_CONTROL_1 */ "", 28999 /* EVXLT_RAM_CONTROL_2 */ "", 29000 /* EVXLT_RAM_CONTROL_1_64 */ "", 29001 /* EVXLT_RAM_CONTROL_2_64 */ "", 29002 /* EVXLT_RAM_CONTROL_3_64 */ "", 29003 /* EVXLT_RAM_DBGCTRL */ "EVXLT_RAM_CONTROL", 29004 /* EVXLT_TM_REG_1 */ "", 29005 /* EVXLT_WW_REG_1 */ "", 29006 /* EXACT_MATCH_AUX_TAG_FIELD_BUS_CONTAINER_SEL */ "", 29007 /* EXACT_MATCH_AUX_TAG_FIELD_BUS_CONTAINER_SEL_PIPE0 */ "", 29008 /* EXACT_MATCH_AUX_TAG_FIELD_BUS_CONTAINER_SEL_PIPE1 */ "", 29009 /* EXACT_MATCH_ING_ZONE_MATCH_ID_CONFIG */ "", 29010 /* EXACT_MATCH_ING_ZONE_MATCH_ID_CONFIG_PIPE0 */ "", 29011 /* EXACT_MATCH_ING_ZONE_MATCH_ID_CONFIG_PIPE1 */ "", 29012 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG */ "", 29013 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2 */ "", 29014 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64 */ "", 29015 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE0 */ "", 29016 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE1 */ "", 29017 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE2 */ "", 29018 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE3 */ "", 29019 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0 */ "", 29020 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1 */ "", 29021 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2 */ "", 29022 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3 */ "", 29023 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE4 */ "", 29024 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE5 */ "", 29025 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE6 */ "", 29026 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE7 */ "", 29027 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE0 */ "", 29028 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE1 */ "", 29029 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE2 */ "", 29030 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE3 */ "", 29031 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE4 */ "", 29032 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE5 */ "", 29033 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE6 */ "", 29034 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE7 */ "", 29035 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA */ "", 29036 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE0 */ "", 29037 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE1 */ "", 29038 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE2 */ "", 29039 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE3 */ "", 29040 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE4 */ "", 29041 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE5 */ "", 29042 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE6 */ "", 29043 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE7 */ "", 29044 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS */ "", 29045 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0 */ "", 29046 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1 */ "", 29047 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2 */ "", 29048 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3 */ "", 29049 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE4 */ "", 29050 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE5 */ "", 29051 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE6 */ "", 29052 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE7 */ "", 29053 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL", 29054 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE0 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE0", 29055 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE1 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE1", 29056 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE2 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE2", 29057 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE3 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE3", 29058 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE4 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE4", 29059 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE5 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE5", 29060 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE6 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE6", 29061 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE7 */ "EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE7", 29062 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG */ "", 29063 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE0 */ "", 29064 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE1 */ "", 29065 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE2 */ "", 29066 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE3 */ "", 29067 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE4 */ "", 29068 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE5 */ "", 29069 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE6 */ "", 29070 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_CONFIG_PIPE7 */ "", 29071 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM */ "", 29072 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE0 */ "", 29073 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE1 */ "", 29074 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE2 */ "", 29075 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE3 */ "", 29076 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE4 */ "", 29077 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE5 */ "", 29078 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE6 */ "", 29079 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TM_PIPE7 */ "", 29080 /* EXACT_MATCH_QOS_CONTROL */ "", 29081 /* EXACT_MATCH_QOS_CONTROL_PIPE0 */ "", 29082 /* EXACT_MATCH_QOS_CONTROL_PIPE1 */ "", 29083 /* EXACT_MATCH_QOS_CONTROL_PIPE2 */ "", 29084 /* EXACT_MATCH_QOS_CONTROL_PIPE3 */ "", 29085 /* EXP_FRAGMENT_CNT */ "", 29086 /* EXT1_RESET_ON_EMPTY_MAX_PORT1 */ "", 29087 /* EXT1_RESET_ON_EMPTY_MAX_PORT2 */ "", 29088 /* EXT1_RESET_ON_EMPTY_MAX_PORT3 */ "", 29089 /* EXT1_RESET_ON_EMPTY_MAX_PORT4 */ "", 29090 /* EXT1_RESET_ON_EMPTY_MAX_PORT34 */ "", 29091 /* EXT1_RESET_ON_EMPTY_MAX_PORT35 */ "", 29092 /* EXT1_RESET_ON_EMPTY_MAX_PORT36 */ "", 29093 /* EXT1_RESET_ON_EMPTY_MAX_PORT37 */ "", 29094 /* EXT1_SHAPING_CONTROL_PORT1 */ "", 29095 /* EXT1_SHAPING_CONTROL_PORT2 */ "", 29096 /* EXT1_SHAPING_CONTROL_PORT3 */ "", 29097 /* EXT1_SHAPING_CONTROL_PORT4 */ "", 29098 /* EXT1_SHAPING_CONTROL_PORT34 */ "", 29099 /* EXT1_SHAPING_CONTROL_PORT35 */ "", 29100 /* EXT1_SHAPING_CONTROL_PORT36 */ "", 29101 /* EXT1_SHAPING_CONTROL_PORT37 */ "", 29102 /* EXTADDR */ "", 29103 /* EXT_BUFFER_POOL_CONG_STATE */ "", 29104 /* EXT_IFP_ACT_PARITY_CONTROL */ "", 29105 /* EXT_IFP_ACT_PARITY_STATUS_INTR */ "", 29106 /* EXT_IFP_ACT_PARITY_STATUS_NACK */ "", 29107 /* EXT_M0_IDM_IDM_INTERRUPT_STATUS */ "", 29108 /* EXT_M0_IDM_IDM_RESET_CONTROL */ "", 29109 /* EXT_M0_IDM_IDM_RESET_STATUS */ "", 29110 /* EXT_M1_IDM_IDM_INTERRUPT_STATUS */ "", 29111 /* EXT_M1_IDM_IDM_RESET_CONTROL */ "", 29112 /* EXT_M1_IDM_IDM_RESET_STATUS */ "", 29113 /* EXT_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 29114 /* EXT_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 29115 /* EXT_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 29116 /* EXT_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 29117 /* EXT_S0_IDM_IDM_ERROR_LOG_ID */ "", 29118 /* EXT_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 29119 /* EXT_S0_IDM_IDM_INTERRUPT_STATUS */ "", 29120 /* EXT_S0_IDM_IDM_RESET_CONTROL */ "", 29121 /* EXT_S0_IDM_IDM_RESET_READ_ID */ "", 29122 /* EXT_S0_IDM_IDM_RESET_STATUS */ "", 29123 /* EXT_S0_IDM_IDM_RESET_WRITE_ID */ "", 29124 /* EXT_S1_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 29125 /* EXT_S1_IDM_IDM_ERROR_LOG_COMPLETE */ "", 29126 /* EXT_S1_IDM_IDM_ERROR_LOG_CONTROL */ "", 29127 /* EXT_S1_IDM_IDM_ERROR_LOG_FLAGS */ "", 29128 /* EXT_S1_IDM_IDM_ERROR_LOG_ID */ "", 29129 /* EXT_S1_IDM_IDM_ERROR_LOG_STATUS */ "", 29130 /* EXT_S1_IDM_IDM_INTERRUPT_STATUS */ "", 29131 /* EXT_S1_IDM_IDM_RESET_CONTROL */ "", 29132 /* EXT_S1_IDM_IDM_RESET_READ_ID */ "", 29133 /* EXT_S1_IDM_IDM_RESET_STATUS */ "", 29134 /* EXT_S1_IDM_IDM_RESET_WRITE_ID */ "", 29135 /* EXT_TCAM_ATTR */ "", 29136 /* FAST_TX_FLUSH */ "", 29137 /* FCOE_ING_CONTROL */ "", 29138 /* FCR_AUTO_DOC_NAME_5 */ "", 29139 /* FCR_AUTO_DOC_NAME_8 */ "", 29140 /* FCR_AUTO_DOC_NAME_11 */ "", 29141 /* FCR_AUTO_DOC_NAME_16 */ "", 29142 /* FCR_AUTO_DOC_NAME_21 */ "", 29143 /* FCR_AUTO_DOC_NAME_25 */ "", 29144 /* FCR_AUTO_DOC_NAME_31 */ "", 29145 /* FCR_AUTO_DOC_NAME_32 */ "", 29146 /* FCR_AUTO_DOC_NAME_34 */ "", 29147 /* FCR_CELL_DROP_COUNTER_0 */ "", 29148 /* FCR_CELL_DROP_COUNTER_1 */ "", 29149 /* FCR_CONNECTIVITY_MAP_CHANGE_EVENT_REGISTERS */ "", 29150 /* FCR_CONNECTIVITY_MAP_REGISTERS */ "", 29151 /* FCR_CONTROL_CELL_FIFO_BUFFER */ "", 29152 /* FCR_CREDIT_CELLS_COUNTER */ "", 29153 /* FCR_CRMA_WATERMARKS */ "", 29154 /* FCR_CRMB_WATERMARKS */ "", 29155 /* FCR_CRM_WATERMARKS */ "", 29156 /* FCR_ECC_1B_ERR_CNT */ "", 29157 /* FCR_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 29158 /* FCR_ECC_2B_ERR_CNT */ "", 29159 /* FCR_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 29160 /* FCR_ECC_ERR_1B_INITIATE */ "", 29161 /* FCR_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 29162 /* FCR_ECC_ERR_2B_INITIATE */ "", 29163 /* FCR_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 29164 /* FCR_ECC_INTERRUPT_REGISTER */ "", 29165 /* FCR_ECC_INTERRUPT_REGISTER_MASK */ "", 29166 /* FCR_ECC_INTERRUPT_REGISTER_TEST */ "", 29167 /* FCR_EFMS_CONFIGURATION */ "", 29168 /* FCR_EFMS_COUNTERS */ "", 29169 /* FCR_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 29170 /* FCR_ERROR_INITIATION_DATA */ "", 29171 /* FCR_FCR_ENABLERS_AND_FILTER_MATCH_INPUT_LINK */ "", 29172 /* FCR_FCR_ENABLE_LAG_CORE_DEST_FLIP_PER_PORT */ "", 29173 /* FCR_FCR_ENABLE_LAG_PORT_DEST_MODIFY_PER_PORT */ "", 29174 /* FCR_FCR_PRE_CONFIGURED_DUMMY_PORT */ "", 29175 /* FCR_FLOW_STATUS_CELLS_COUNTER */ "", 29176 /* FCR_GLOBAL_GENERAL_CFG_2 */ "", 29177 /* FCR_GLOBAL_MEM_OPTIONS */ "", 29178 /* FCR_GTIMER_CONFIGURATION */ "", 29179 /* FCR_GTIMER_CYCLE */ "", 29180 /* FCR_GTIMER_TRIGGER */ "", 29181 /* FCR_INDIRECT_COMMAND */ "", 29182 /* FCR_INDIRECT_COMMAND_ADDRESS */ "", 29183 /* FCR_INDIRECT_COMMAND_DATA_INCREMENT */ "", 29184 /* FCR_INDIRECT_COMMAND_RD_DATA */ "", 29185 /* FCR_INDIRECT_COMMAND_WIDE_MEM */ "", 29186 /* FCR_INDIRECT_COMMAND_WR_DATA */ "", 29187 /* FCR_INDIRECT_FORCE_BUBBLE */ "", 29188 /* FCR_INITIATE_ECC_1B_ERRORS */ "", 29189 /* FCR_INITIATE_ECC_2B_ERRORS */ "", 29190 /* FCR_INTERRUPT_MASK_REGISTER */ "", 29191 /* FCR_INTERRUPT_REGISTER */ "", 29192 /* FCR_INTERRUPT_REGISTER_TEST */ "", 29193 /* FCR_PARITY_ERR_CNT */ "", 29194 /* FCR_PAR_ERR_INITIATE */ "", 29195 /* FCR_PAR_ERR_MEM_MASK */ "", 29196 /* FCR_PROGRAMMABLE_CELLS_COUNTER */ "", 29197 /* FCR_PROGRAMMABLE_CONTROL_CELL_COUNTER */ "", 29198 /* FCR_PROGRAMMABLE_CONTROL_CELL_COUNTER_MASK_0 */ "", 29199 /* FCR_REACHABILITY_CELLS_COUNTER */ "", 29200 /* FCR_REG_0041 */ "", 29201 /* FCR_REG_0085 */ "", 29202 /* FCR_REG_0090 */ "", 29203 /* FCR_REG_0091 */ "", 29204 /* FCR_REG_0092 */ "", 29205 /* FCR_REG_0093 */ "", 29206 /* FCR_REG_0098 */ "", 29207 /* FCR_REG_0167 */ "", 29208 /* FCR_REG_0197 */ "", 29209 /* FCR_REG_0240 */ "", 29210 /* FCR_REG_00A0 */ "", 29211 /* FCR_REG_00A4 */ "", 29212 /* FCR_REG_00A6 */ "", 29213 /* FCR_REG_00AA */ "", 29214 /* FCR_REG_00AE */ "", 29215 /* FCR_REG_00AF */ "", 29216 /* FCR_REG_00C2 */ "", 29217 /* FCR_REG_00C4 */ "", 29218 /* FCR_REG_00CE */ "", 29219 /* FCR_REG_00CF */ "", 29220 /* FCR_REG_01B0 */ "", 29221 /* FCR_REG_01B1 */ "", 29222 /* FCR_REG_01B2 */ "", 29223 /* FCR_REG_01B7 */ "", 29224 /* FCR_REG_01B8 */ "", 29225 /* FCR_REG_01C0 */ "", 29226 /* FCR_RESERVED_MIRROR_ADDR */ "", 29227 /* FCR_RESERVED_MTCD */ "", 29228 /* FCR_RESERVED_MTCP */ "", 29229 /* FCR_RESERVED_SPARE_0 */ "", 29230 /* FCR_RESERVED_SPARE_1 */ "", 29231 /* FCR_RESERVED_SPARE_2 */ "", 29232 /* FCR_RESERVED_SPARE_3 */ "", 29233 /* FCR_SBUS_BROADCAST_ID */ "", 29234 /* FCR_SBUS_LAST_IN_CHAIN */ "", 29235 /* FCR_SPECIAL_CLOCK_CONTROLS */ "", 29236 /* FCR_TOTAL_CELLS_COUNTER */ "", 29237 /* FCT_AUTO_DOC_NAME_1 */ "", 29238 /* FCT_AUTO_DOC_NAME_2 */ "", 29239 /* FCT_AUTO_DOC_NAME_6 */ "", 29240 /* FCT_AUTO_DOC_NAME_7 */ "", 29241 /* FCT_AUTO_DOC_NAME_8 */ "", 29242 /* FCT_AUTO_DOC_NAME_9 */ "", 29243 /* FCT_AUTO_DOC_NAME_10 */ "", 29244 /* FCT_AUTO_DOC_NAME_11 */ "", 29245 /* FCT_CPU_TRANSMIT_CELL */ "", 29246 /* FCT_CPU_TRANSMIT_CELLS_TRIGGER */ "", 29247 /* FCT_CPU_TRANSMIT_CELL_LINK_NUMBER */ "", 29248 /* FCT_ECC_1B_ERR_CNT */ "", 29249 /* FCT_ECC_2B_ERR_CNT */ "", 29250 /* FCT_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 29251 /* FCT_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 29252 /* FCT_ECC_INTERRUPT_REGISTER */ "", 29253 /* FCT_ECC_INTERRUPT_REGISTER_MASK */ "", 29254 /* FCT_ECC_INTERRUPT_REGISTER_TEST */ "", 29255 /* FCT_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 29256 /* FCT_ERROR_INITIATION_DATA */ "", 29257 /* FCT_FCT_ENABLER_REGISTER */ "", 29258 /* FCT_GLOBAL_GENERAL_CFG_1 */ "", 29259 /* FCT_GLOBAL_GENERAL_CFG_2 */ "", 29260 /* FCT_GLOBAL_MEM_OPTIONS */ "", 29261 /* FCT_GTIMER_CONFIGURATION */ "", 29262 /* FCT_GTIMER_CYCLE */ "", 29263 /* FCT_GTIMER_TRIGGER */ "", 29264 /* FCT_INDIRECT_COMMAND */ "", 29265 /* FCT_INDIRECT_COMMAND_ADDRESS */ "", 29266 /* FCT_INDIRECT_COMMAND_RD_DATA */ "", 29267 /* FCT_INDIRECT_COMMAND_WR_DATA */ "", 29268 /* FCT_INDIRECT_FORCE_BUBBLE */ "", 29269 /* FCT_INTERRUPT_MASK_REGISTER */ "", 29270 /* FCT_INTERRUPT_REGISTER */ "", 29271 /* FCT_INTERRUPT_REGISTER_TEST */ "", 29272 /* FCT_LOCAL_ROUTE_CELLS_COUNTER */ "", 29273 /* FCT_MESH_MODE_DEVICE_IDS */ "", 29274 /* FCT_MIN_NUM_OF_LINKS_DROPS */ "", 29275 /* FCT_REG_0041 */ "", 29276 /* FCT_REG_0085 */ "", 29277 /* FCT_REG_0086 */ "", 29278 /* FCT_REG_0090 */ "", 29279 /* FCT_REG_0091 */ "", 29280 /* FCT_REG_0092 */ "", 29281 /* FCT_REG_0093 */ "", 29282 /* FCT_REG_0098 */ "", 29283 /* FCT_REG_0101 */ "", 29284 /* FCT_REG_0107 */ "", 29285 /* FCT_REG_0108 */ "", 29286 /* FCT_REG_0109 */ "", 29287 /* FCT_REG_0123 */ "", 29288 /* FCT_REG_0124 */ "", 29289 /* FCT_REG_00A0 */ "", 29290 /* FCT_REG_00A4 */ "", 29291 /* FCT_REG_00A6 */ "", 29292 /* FCT_REG_00AA */ "", 29293 /* FCT_REG_00B8 */ "", 29294 /* FCT_REG_00B9 */ "", 29295 /* FCT_REG_00BA */ "", 29296 /* FCT_REG_00BB */ "", 29297 /* FCT_REG_00C0 */ "", 29298 /* FCT_REG_00C1 */ "", 29299 /* FCT_REG_00C2 */ "", 29300 /* FCT_REG_00C3 */ "", 29301 /* FCT_REG_00C4 */ "", 29302 /* FCT_REG_00CE */ "", 29303 /* FCT_REG_010A */ "", 29304 /* FCT_REG_010B */ "", 29305 /* FCT_REG_010C */ "", 29306 /* FCT_REG_010D */ "", 29307 /* FCT_REG_010F */ "", 29308 /* FCT_RESERVED_MIRROR_ADDR */ "", 29309 /* FCT_RESERVED_MTCD */ "", 29310 /* FCT_RESERVED_MTCP */ "", 29311 /* FCT_RESERVED_SPARE_0 */ "", 29312 /* FCT_RESERVED_SPARE_1 */ "", 29313 /* FCT_RESERVED_SPARE_2 */ "", 29314 /* FCT_RESERVED_SPARE_3 */ "", 29315 /* FCT_SBUS_BROADCAST_ID */ "", 29316 /* FCT_SBUS_LAST_IN_CHAIN */ "", 29317 /* FCT_SPECIAL_CLOCK_CONTROLS */ "", 29318 /* FCT_TRANSMITTED_CONTROL_CELLS_COUNTER */ "", 29319 /* FCT_TRANSMITTED_CR_CELLS_COUNTER */ "", 29320 /* FCT_TRANSMITTED_FS_CELLS_COUNTER */ "", 29321 /* FCT_TRANSMITTED_RTP_CELLS_COUNTER */ "", 29322 /* FCT_UNREACHABLE_DESTINATION */ "", 29323 /* FC_DST_PORT_MAPPING_TABLE_0 */ "", 29324 /* FC_DST_PORT_MAPPING_TABLE_1 */ "", 29325 /* FC_DST_PORT_MAPPING_TABLE_2 */ "", 29326 /* FC_MAP_DEBUG_TM */ "", 29327 /* FC_MAP_TBL2_ECC_ERR1 */ "", 29328 /* FC_MAP_TBL2_ECC_ERR2 */ "", 29329 /* FC_STTB_BITWR_ENABLE */ "", 29330 /* FDA_AUTO_DOC_NAME_2 */ "", 29331 /* FDA_AUTO_DOC_NAME_4 */ "", 29332 /* FDA_AUTO_DOC_NAME_6 */ "", 29333 /* FDA_AUTO_DOC_NAME_7 */ "", 29334 /* FDA_AUTO_DOC_NAME_8 */ "", 29335 /* FDA_AUTO_DOC_NAME_9 */ "", 29336 /* FDA_AUTO_DOC_NAME_15 */ "", 29337 /* FDA_AUTO_DOC_NAME_16 */ "", 29338 /* FDA_AUTO_DOC_NAME_17 */ "", 29339 /* FDA_AUTO_DOC_NAME_18 */ "", 29340 /* FDA_AUTO_DOC_NAME_19 */ "", 29341 /* FDA_AUTO_DOC_NAME_20 */ "", 29342 /* FDA_AUTO_DOC_NAME_21 */ "", 29343 /* FDA_AUTO_DOC_NAME_22 */ "", 29344 /* FDA_AUTO_DOC_NAME_23 */ "", 29345 /* FDA_AUTO_DOC_NAME_24 */ "", 29346 /* FDA_AUTO_DOC_NAME_25 */ "", 29347 /* FDA_AUTO_DOC_NAME_27 */ "", 29348 /* FDA_AUTO_DOC_NAME_31 */ "", 29349 /* FDA_ECC_1B_ERR_CNT */ "", 29350 /* FDA_ECC_2B_ERR_CNT */ "", 29351 /* FDA_ECC_ERR_1B_INITIATE */ "", 29352 /* FDA_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 29353 /* FDA_ECC_ERR_2B_INITIATE */ "", 29354 /* FDA_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 29355 /* FDA_ECC_INTERRUPT_REGISTER */ "", 29356 /* FDA_ECC_INTERRUPT_REGISTER_MASK */ "", 29357 /* FDA_ECC_INTERRUPT_REGISTER_TEST */ "", 29358 /* FDA_EGQ_CELLS_IN_CNT_IPT */ "", 29359 /* FDA_EGQ_CELLS_IN_CNT_IPT_0 */ "", 29360 /* FDA_EGQ_CELLS_IN_CNT_IPT_1 */ "", 29361 /* FDA_EGQ_CELLS_IN_CNT_MESHMC */ "", 29362 /* FDA_EGQ_CELLS_IN_CNT_MESHMC_0 */ "", 29363 /* FDA_EGQ_CELLS_IN_CNT_MESHMC_1 */ "", 29364 /* FDA_EGQ_CELLS_IN_CNT_TDM */ "", 29365 /* FDA_EGQ_CELLS_OUT_CNT_FAB_FIFO_0 */ "", 29366 /* FDA_EGQ_CELLS_OUT_CNT_FAB_FIFO_1 */ "", 29367 /* FDA_EGQ_CELLS_OUT_CNT_FAB_FIFO_2 */ "", 29368 /* FDA_EGQ_CELLS_OUT_CNT_FAB_PIPE_0 */ "", 29369 /* FDA_EGQ_CELLS_OUT_CNT_FAB_PIPE_1 */ "", 29370 /* FDA_EGQ_CELLS_OUT_CNT_FAB_PIPE_2 */ "", 29371 /* FDA_EGQ_CELLS_OUT_CNT_IPT */ "", 29372 /* FDA_EGQ_CELLS_OUT_CNT_IPT_0 */ "", 29373 /* FDA_EGQ_CELLS_OUT_CNT_IPT_1 */ "", 29374 /* FDA_EGQ_CELLS_OUT_CNT_MESHMC */ "", 29375 /* FDA_EGQ_CELLS_OUT_CNT_MESHMC_0 */ "", 29376 /* FDA_EGQ_CELLS_OUT_CNT_MESHMC_1 */ "", 29377 /* FDA_EGQ_CELLS_OUT_CNT_TDM */ "", 29378 /* FDA_EGQ_FABFIF_0_PRIO_0_DROP_CNT */ "", 29379 /* FDA_EGQ_FABFIF_0_PRIO_1_DROP_CNT */ "", 29380 /* FDA_EGQ_FABFIF_0_PRIO_2_DROP_CNT */ "", 29381 /* FDA_EGQ_FABFIF_1_PRIO_0_DROP_CNT */ "", 29382 /* FDA_EGQ_FABFIF_1_PRIO_1_DROP_CNT */ "", 29383 /* FDA_EGQ_FABFIF_1_PRIO_2_DROP_CNT */ "", 29384 /* FDA_EGQ_FABFIF_2_PRIO_0_DROP_CNT */ "", 29385 /* FDA_EGQ_FABFIF_2_PRIO_1_DROP_CNT */ "", 29386 /* FDA_EGQ_FABFIF_2_PRIO_2_DROP_CNT */ "", 29387 /* FDA_EGQ_FAB_0_OVF_DROP_CNT */ "", 29388 /* FDA_EGQ_FAB_1_OVF_DROP_CNT */ "", 29389 /* FDA_EGQ_FAB_2_OVF_DROP_CNT */ "", 29390 /* FDA_EGQ_FAB_DROP_CNT */ "", 29391 /* FDA_EGQ_FAB_FIFOS_WM */ "", 29392 /* FDA_EGQ_IPT_DROP_CNT */ "", 29393 /* FDA_EGQ_IPT_FIFOS_WM */ "", 29394 /* FDA_EGQ_MESHMC_0_OVF_DROP_COUNT */ "", 29395 /* FDA_EGQ_MESHMC_0_PRIO_0_DROP_CNT */ "", 29396 /* FDA_EGQ_MESHMC_0_PRIO_1_DROP_CNT */ "", 29397 /* FDA_EGQ_MESHMC_0_PRIO_2_DROP_CNT */ "", 29398 /* FDA_EGQ_MESHMC_0_PRIO_3_DROP_CNT */ "", 29399 /* FDA_EGQ_MESHMC_1_OVF_DROP_COUNT */ "", 29400 /* FDA_EGQ_MESHMC_1_PRIO_0_DROP_CNT */ "", 29401 /* FDA_EGQ_MESHMC_1_PRIO_1_DROP_CNT */ "", 29402 /* FDA_EGQ_MESHMC_1_PRIO_2_DROP_CNT */ "", 29403 /* FDA_EGQ_MESHMC_1_PRIO_3_DROP_CNT */ "", 29404 /* FDA_EGQ_MESHMC_DROP_CNT */ "", 29405 /* FDA_EGQ_MESHMC_FIFOS_WM */ "", 29406 /* FDA_EGQ_MESHMC_FIFO_WM */ "", 29407 /* FDA_EGQ_MESHMC_OVF_DROP_COUNT */ "", 29408 /* FDA_EGQ_MESHMC_PRIO_0_DROP_CNT */ "", 29409 /* FDA_EGQ_MESHMC_PRIO_1_DROP_CNT */ "", 29410 /* FDA_EGQ_MESHMC_PRIO_2_DROP_CNT */ "", 29411 /* FDA_EGQ_RR_THRESHOLD */ "", 29412 /* FDA_EGQ_TDM_DROP_CNT */ "", 29413 /* FDA_EGQ_TDM_FIFO_WM */ "", 29414 /* FDA_EGQ_TDM_OVF_DROP_COUNT */ "", 29415 /* FDA_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 29416 /* FDA_ERROR_INITIATION_DATA */ "", 29417 /* FDA_FABRIC_18_18 */ "", 29418 /* FDA_FABRIC_24_24 */ "", 29419 /* FDA_FAB_18_SCH_CELLS_IN_CNT_P_1 */ "", 29420 /* FDA_FAB_18_SCH_CELLS_IN_CNT_P_2 */ "", 29421 /* FDA_FAB_18_SCH_CELLS_IN_CNT_P_3 */ "", 29422 /* FDA_FAB_18_SCH_WFQ_CFG */ "", 29423 /* FDA_FAB_24_SCH_CELLS_IN_CNT_P_1 */ "", 29424 /* FDA_FAB_24_SCH_CELLS_IN_CNT_P_2 */ "", 29425 /* FDA_FAB_24_SCH_CELLS_IN_CNT_P_3 */ "", 29426 /* FDA_FAB_24_SCH_PIPE_STRICT_PRIO */ "", 29427 /* FDA_FAB_24_SCH_WFQ_CFG */ "", 29428 /* FDA_FAB_36_SCH_CELLS_IN_CNT_P_1 */ "", 29429 /* FDA_FAB_36_SCH_CELLS_IN_CNT_P_2 */ "", 29430 /* FDA_FAB_36_SCH_CELLS_IN_CNT_P_3 */ "", 29431 /* FDA_FAB_36_SCH_WFQ_CFG */ "", 29432 /* FDA_FAB_48_SCH_CELLS_IN_CNT_P_1 */ "", 29433 /* FDA_FAB_48_SCH_CELLS_IN_CNT_P_2 */ "", 29434 /* FDA_FAB_48_SCH_CELLS_IN_CNT_P_3 */ "", 29435 /* FDA_FAB_48_SCH_PIPE_STRICT_PRIO */ "", 29436 /* FDA_FAB_48_SCH_WFQ_CFG */ "", 29437 /* FDA_FAB_MCT_DROP_CNT */ "", 29438 /* FDA_FAB_PIPE_STRICT_PRIO */ "", 29439 /* FDA_FDA_EGQ_FABFIF_0_PRIO_DROP_THR */ "", 29440 /* FDA_FDA_EGQ_FABFIF_1_PRIO_DROP_THR */ "", 29441 /* FDA_FDA_EGQ_FABFIF_2_PRIO_DROP_THR */ "", 29442 /* FDA_FDA_EGQ_FABRIC_FIFO_PARTITIONING */ "", 29443 /* FDA_FDA_EGQ_FABRIC_RCI */ "", 29444 /* FDA_FDA_EGQ_FAB_ECC_INFO */ "", 29445 /* FDA_FDA_EGQ_IPT_ALM_FULL_TH */ "", 29446 /* FDA_FDA_EGQ_MESHMC_0_PRIO_DROP_THR */ "", 29447 /* FDA_FDA_EGQ_MESHMC_1_PRIO_DROP_THR */ "", 29448 /* FDA_FDA_EGQ_MESHMC_PRIO_DROP_THR */ "", 29449 /* FDA_FDA_EGQ_PIPE_TO_FIFO_MAPPING */ "", 29450 /* FDA_FDA_EGQ_WFQ */ "", 29451 /* FDA_FDA_EGQ_WFQ_ALMOST_FULL_WEIGHTS */ "", 29452 /* FDA_FDA_ENABLERS */ "", 29453 /* FDA_FDA_IPT_RCI */ "", 29454 /* FDA_FDA_IPT_TOTAL_RCI */ "", 29455 /* FDA_FDA_MESHMC_FC_EN */ "", 29456 /* FDA_FDA_REGISTER_0 */ "", 29457 /* FDA_FDA_TDM_FC_EN */ "", 29458 /* FDA_FDA_TDM_FC_THR */ "", 29459 /* FDA_GCI_CONFIGS */ "", 29460 /* FDA_GLOBAL_GENERAL_CFG_1 */ "", 29461 /* FDA_GLOBAL_GENERAL_CFG_2 */ "", 29462 /* FDA_GLOBAL_MEM_OPTIONS */ "", 29463 /* FDA_GTIMER_CONFIGURATION */ "", 29464 /* FDA_GTIMER_CYCLE */ "", 29465 /* FDA_GTIMER_TRIGGER */ "", 29466 /* FDA_INDIRECT_COMMAND */ "", 29467 /* FDA_INDIRECT_COMMAND_ADDRESS */ "", 29468 /* FDA_INDIRECT_COMMAND_DATA_INCREMENT */ "", 29469 /* FDA_INDIRECT_COMMAND_RD_DATA */ "", 29470 /* FDA_INDIRECT_COMMAND_WIDE_MEM */ "", 29471 /* FDA_INDIRECT_COMMAND_WR_DATA */ "", 29472 /* FDA_INDIRECT_FORCE_BUBBLE */ "", 29473 /* FDA_INTERRUPT_MASK_REGISTER */ "", 29474 /* FDA_INTERRUPT_REGISTER */ "", 29475 /* FDA_INTERRUPT_REGISTER_TEST */ "", 29476 /* FDA_PARITY_ERR_CNT */ "", 29477 /* FDA_PAR_ERR_INITIATE */ "", 29478 /* FDA_PAR_ERR_MEM_MASK */ "", 29479 /* FDA_P_1_MTM_INITIATE_ECC_1B_ERRORS */ "", 29480 /* FDA_P_1_MTM_INITIATE_ECC_2B_ERRORS */ "", 29481 /* FDA_P_1_PSM_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 29482 /* FDA_P_1_PSM_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 29483 /* FDA_P_2_MTM_INITIATE_ECC_1B_ERRORS */ "", 29484 /* FDA_P_2_MTM_INITIATE_ECC_2B_ERRORS */ "", 29485 /* FDA_P_2_PSM_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 29486 /* FDA_P_2_PSM_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 29487 /* FDA_P_3_MTM_INITIATE_ECC_1B_ERRORS */ "", 29488 /* FDA_P_3_MTM_INITIATE_ECC_2B_ERRORS */ "", 29489 /* FDA_P_3_PSM_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 29490 /* FDA_P_3_PSM_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 29491 /* FDA_RCI_CONFIGS */ "", 29492 /* FDA_RCI_CORE_MAPPING */ "", 29493 /* FDA_RCI_DEVICE_MAPPING */ "", 29494 /* FDA_RCI_SCORES_INFO */ "", 29495 /* FDA_REG_0101 */ "", 29496 /* FDA_REG_0102 */ "", 29497 /* FDA_REG_0103 */ "", 29498 /* FDA_REG_0104 */ "", 29499 /* FDA_REG_0107 */ "", 29500 /* FDA_REG_0108 */ "", 29501 /* FDA_REG_0109 */ "", 29502 /* FDA_REG_0110 */ "", 29503 /* FDA_REG_0111 */ "", 29504 /* FDA_REG_0112 */ "", 29505 /* FDA_REG_0113 */ "", 29506 /* FDA_REG_0118 */ "", 29507 /* FDA_REG_0122 */ "", 29508 /* FDA_REG_0124 */ "", 29509 /* FDA_REG_0126 */ "", 29510 /* FDA_REG_0128 */ "", 29511 /* FDA_REG_0150 */ "", 29512 /* FDA_REG_0151 */ "", 29513 /* FDA_REG_0152 */ "", 29514 /* FDA_REG_0153 */ "", 29515 /* FDA_REG_0155 */ "", 29516 /* FDA_REG_0158 */ "", 29517 /* FDA_REG_00A */ "", 29518 /* FDA_REG_00A4 */ "", 29519 /* FDA_REG_00A6 */ "", 29520 /* FDA_REG_00B */ "", 29521 /* FDA_REG_00C */ "", 29522 /* FDA_REG_00C2 */ "", 29523 /* FDA_REG_010A */ "", 29524 /* FDA_REG_010B */ "", 29525 /* FDA_REG_010C */ "", 29526 /* FDA_REG_010D */ "", 29527 /* FDA_REG_010E */ "", 29528 /* FDA_REG_010F */ "", 29529 /* FDA_REG_012A */ "", 29530 /* FDA_REG_016C */ "", 29531 /* FDA_RESERVED_MIRROR_ADDR */ "", 29532 /* FDA_RESERVED_MTCD */ "", 29533 /* FDA_RESERVED_MTCP */ "", 29534 /* FDA_RESERVED_PCMI_0 */ "", 29535 /* FDA_RESERVED_PCMI_1 */ "", 29536 /* FDA_RESERVED_PCMI_2 */ "", 29537 /* FDA_RESERVED_PCMI_3 */ "", 29538 /* FDA_RESERVED_PCMI_4 */ "", 29539 /* FDA_RESERVED_PCMI_0_S */ "", 29540 /* FDA_RESERVED_PCMI_0_T */ "", 29541 /* FDA_RESERVED_PCMI_1_S */ "", 29542 /* FDA_RESERVED_PCMI_1_T */ "", 29543 /* FDA_RESERVED_PCMI_2_S */ "", 29544 /* FDA_RESERVED_PCMI_2_T */ "", 29545 /* FDA_RESERVED_PCMI_3_S */ "", 29546 /* FDA_RESERVED_PCMI_3_T */ "", 29547 /* FDA_RESERVED_PCMI_4_S */ "", 29548 /* FDA_RESERVED_PCMI_4_T */ "", 29549 /* FDA_RESERVED_SPARE_0 */ "", 29550 /* FDA_RESERVED_SPARE_1 */ "", 29551 /* FDA_RESERVED_SPARE_2 */ "", 29552 /* FDA_RESERVED_SPARE_3 */ "", 29553 /* FDA_SBUS_BROADCAST_ID */ "", 29554 /* FDA_SBUS_LAST_IN_CHAIN */ "", 29555 /* FDA_SINGLE_FAP_MODE_EGQ_SEL */ "", 29556 /* FDA_SOFT_RESET_DROP_EN */ "", 29557 /* FDA_SPECIAL_CLOCK_CONTROLS */ "", 29558 /* FDR_AUTO_DOC_NAME_1 */ "", 29559 /* FDR_AUTO_DOC_NAME_13 */ "", 29560 /* FDR_AUTO_DOC_NAME_14 */ "", 29561 /* FDR_AUTO_DOC_NAME_15 */ "", 29562 /* FDR_AUTO_DOC_NAME_16 */ "", 29563 /* FDR_AUTO_DOC_NAME_23 */ "", 29564 /* FDR_AUTO_DOC_NAME_24 */ "", 29565 /* FDR_AUTO_DOC_NAME_25 */ "", 29566 /* FDR_AUTO_DOC_NAME_26 */ "", 29567 /* FDR_AUTO_DOC_NAME_27 */ "", 29568 /* FDR_AUTO_DOC_NAME_28 */ "", 29569 /* FDR_AUTO_DOC_NAME_29 */ "", 29570 /* FDR_AUTO_DOC_NAME_30 */ "", 29571 /* FDR_AUTO_DOC_NAME_31 */ "", 29572 /* FDR_AUTO_DOC_NAME_32 */ "", 29573 /* FDR_AUTO_DOC_NAME_33 */ "", 29574 /* FDR_AUTO_DOC_NAME_34 */ "", 29575 /* FDR_AUTO_DOC_NAME_35 */ "", 29576 /* FDR_AUTO_DOC_NAME_36 */ "", 29577 /* FDR_AUTO_DOC_NAME_37 */ "", 29578 /* FDR_AUTO_DOC_NAME_38 */ "", 29579 /* FDR_AUTO_DOC_NAME_39 */ "", 29580 /* FDR_AUTO_DOC_NAME_40 */ "", 29581 /* FDR_AUTO_DOC_NAME_41 */ "", 29582 /* FDR_AUTO_DOC_NAME_42 */ "", 29583 /* FDR_AUTO_DOC_NAME_43 */ "", 29584 /* FDR_AUTO_DOC_NAME_44 */ "", 29585 /* FDR_AUTO_DOC_NAME_45 */ "", 29586 /* FDR_AUTO_DOC_NAME_46 */ "", 29587 /* FDR_AUTO_DOC_NAME_47 */ "", 29588 /* FDR_AUTO_DOC_NAME_48 */ "", 29589 /* FDR_AUTO_DOC_NAME_49 */ "", 29590 /* FDR_AUTO_DOC_NAME_50 */ "", 29591 /* FDR_CELL_IN_CNT_PRIMARY */ "", 29592 /* FDR_CELL_IN_CNT_SECONDARY */ "", 29593 /* FDR_CELL_IN_CNT_TOTAL */ "", 29594 /* FDR_CELL_OUT_CNT_PRIMARY */ "", 29595 /* FDR_CELL_OUT_CNT_SECONDARY */ "", 29596 /* FDR_CPU_DATA_CELL_A_PRIMARY */ "", 29597 /* FDR_CPU_DATA_CELL_B_PRIMARY */ "", 29598 /* FDR_CPU_DATA_CELL_C_PRIMARY */ "", 29599 /* FDR_CPU_DATA_CELL_D_PRIMARY */ "", 29600 /* FDR_CPU_DATA_CELL_MAC */ "", 29601 /* FDR_ECC_1B_ERR_CNT */ "", 29602 /* FDR_ECC_1B_ERR_CNT_PRIMARY */ "", 29603 /* FDR_ECC_1B_ERR_CNT_SECONDARY */ "", 29604 /* FDR_ECC_1B_ERR_MONITOR_MEM_MASK_PRIMARY */ "", 29605 /* FDR_ECC_1B_ERR_MONITOR_MEM_MASK_SECONDARY */ "", 29606 /* FDR_ECC_2B_ERR_CNT */ "", 29607 /* FDR_ECC_2B_ERR_CNT_PRIMARY */ "", 29608 /* FDR_ECC_2B_ERR_CNT_SECONDARY */ "", 29609 /* FDR_ECC_2B_ERR_MONITOR_MEM_MASK_PRIMARY */ "", 29610 /* FDR_ECC_2B_ERR_MONITOR_MEM_MASK_SECONDARY */ "", 29611 /* FDR_ECC_ERR_1B_INITIATE */ "", 29612 /* FDR_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 29613 /* FDR_ECC_ERR_2B_INITIATE */ "", 29614 /* FDR_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 29615 /* FDR_ECC_INTERRUPT_REGISTER */ "", 29616 /* FDR_ECC_INTERRUPT_REGISTER_MASK */ "", 29617 /* FDR_ECC_INTERRUPT_REGISTER_TEST */ "", 29618 /* FDR_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 29619 /* FDR_ERROR_FILTER */ "", 29620 /* FDR_ERROR_FILTER_2 */ "", 29621 /* FDR_ERROR_FILTER_CNT_PRIMARY */ "", 29622 /* FDR_ERROR_FILTER_CNT_SECONDARY */ "", 29623 /* FDR_ERROR_FILTER_MASK */ "", 29624 /* FDR_ERROR_FILTER_MASK_2 */ "", 29625 /* FDR_ERROR_FILTER_MASK_EN */ "", 29626 /* FDR_ERROR_INITIATION_DATA */ "", 29627 /* FDR_FABRIC_18_18 */ "", 29628 /* FDR_FABRIC_24_24 */ "", 29629 /* FDR_FABRIC_SEPARATE_MODE */ "", 29630 /* FDR_FDR_DISCARD_COUNTER_A_PRIMARY */ "", 29631 /* FDR_FDR_DISCARD_COUNTER_A_SECONDARY */ "", 29632 /* FDR_FDR_DISCARD_COUNTER_B_PRIMARY */ "", 29633 /* FDR_FDR_DISCARD_COUNTER_B_SECONDARY */ "", 29634 /* FDR_FDR_ENABLERS_REGISTER_1 */ "", 29635 /* FDR_FDR_ENABLERS_REGISTER_2 */ "", 29636 /* FDR_FDR_ENABLERS_REGISTER_3 */ "", 29637 /* FDR_FDR_FIFO_DISCARD_COUNTER_A_PRIMARY */ "", 29638 /* FDR_FDR_FIFO_DISCARD_COUNTER_A_SECONDARY */ "", 29639 /* FDR_FDR_FIFO_DISCARD_COUNTER_B_PRIMARY */ "", 29640 /* FDR_FDR_FIFO_DISCARD_COUNTER_B_SECONDARY */ "", 29641 /* FDR_FDR_INTERRUPT_MASK_REGISTER_1 */ "", 29642 /* FDR_FDR_INTERRUPT_MASK_REGISTER_2 */ "", 29643 /* FDR_FDR_INTERRUPT_MASK_REGISTER_3 */ "", 29644 /* FDR_FDR_INTERRUPT_MASK_REGISTER_4 */ "", 29645 /* FDR_FDR_INTERRUPT_MASK_REGISTER_GENERAL */ "", 29646 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_0 */ "", 29647 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_1 */ "", 29648 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_2 */ "", 29649 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_3 */ "", 29650 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_4 */ "", 29651 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_5 */ "", 29652 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_6 */ "", 29653 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_1_MAC_7 */ "", 29654 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_0 */ "", 29655 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_1 */ "", 29656 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_2 */ "", 29657 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_3 */ "", 29658 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_4 */ "", 29659 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_5 */ "", 29660 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_6 */ "", 29661 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_2_MAC_7 */ "", 29662 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_0 */ "", 29663 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_1 */ "", 29664 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_2 */ "", 29665 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_3 */ "", 29666 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_4 */ "", 29667 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_5 */ "", 29668 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_6 */ "", 29669 /* FDR_FDR_INTERRUPT_MASK_REGISTER_P_3_MAC_7 */ "", 29670 /* FDR_FDR_INTERRUPT_REGISTER_1 */ "", 29671 /* FDR_FDR_INTERRUPT_REGISTER_2 */ "", 29672 /* FDR_FDR_INTERRUPT_REGISTER_3 */ "", 29673 /* FDR_FDR_INTERRUPT_REGISTER_4 */ "", 29674 /* FDR_FDR_INTERRUPT_REGISTER_1_TEST */ "", 29675 /* FDR_FDR_INTERRUPT_REGISTER_2_TEST */ "", 29676 /* FDR_FDR_INTERRUPT_REGISTER_3_TEST */ "", 29677 /* FDR_FDR_INTERRUPT_REGISTER_4_TEST */ "", 29678 /* FDR_FDR_INTERRUPT_REGISTER_GENERAL */ "", 29679 /* FDR_FDR_INTERRUPT_REGISTER_GENERAL_TEST */ "", 29680 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_0 */ "", 29681 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_1 */ "", 29682 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_2 */ "", 29683 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_3 */ "", 29684 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_4 */ "", 29685 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_5 */ "", 29686 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_6 */ "", 29687 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_7 */ "", 29688 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_0_TEST */ "", 29689 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_1_TEST */ "", 29690 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_2_TEST */ "", 29691 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_3_TEST */ "", 29692 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_4_TEST */ "", 29693 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_5_TEST */ "", 29694 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_6_TEST */ "", 29695 /* FDR_FDR_INTERRUPT_REGISTER_P_1_MAC_7_TEST */ "", 29696 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_0 */ "", 29697 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_1 */ "", 29698 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_2 */ "", 29699 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_3 */ "", 29700 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_4 */ "", 29701 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_5 */ "", 29702 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_6 */ "", 29703 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_7 */ "", 29704 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_0_TEST */ "", 29705 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_1_TEST */ "", 29706 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_2_TEST */ "", 29707 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_3_TEST */ "", 29708 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_4_TEST */ "", 29709 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_5_TEST */ "", 29710 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_6_TEST */ "", 29711 /* FDR_FDR_INTERRUPT_REGISTER_P_2_MAC_7_TEST */ "", 29712 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_0 */ "", 29713 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_1 */ "", 29714 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_2 */ "", 29715 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_3 */ "", 29716 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_4 */ "", 29717 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_5 */ "", 29718 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_6 */ "", 29719 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_7 */ "", 29720 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_0_TEST */ "", 29721 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_1_TEST */ "", 29722 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_2_TEST */ "", 29723 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_3_TEST */ "", 29724 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_4_TEST */ "", 29725 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_5_TEST */ "", 29726 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_6_TEST */ "", 29727 /* FDR_FDR_INTERRUPT_REGISTER_P_3_MAC_7_TEST */ "", 29728 /* FDR_FDR_IN_FC_AGING_PERIOD */ "", 29729 /* FDR_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDRA_PRIMARY */ "", 29730 /* FDR_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDRA_SECONDARY */ "", 29731 /* FDR_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDR_B_PRIMARY */ "", 29732 /* FDR_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDR_B_SECONDARY */ "", 29733 /* FDR_FDR_REGISTER_0 */ "", 29734 /* FDR_FDR_REGISTER_1 */ "", 29735 /* FDR_FDR_SCH_RCI_SCORE_WM */ "", 29736 /* FDR_FILTER_MATCH_ENABLERS */ "", 29737 /* FDR_FILTER_MATCH_INPUT_LINK */ "", 29738 /* FDR_FILTER_MATCH_LINK_EN */ "", 29739 /* FDR_GLOBAL_GENERAL_CFG_1 */ "", 29740 /* FDR_GLOBAL_GENERAL_CFG_2 */ "", 29741 /* FDR_GLOBAL_MEM_OPTIONS */ "", 29742 /* FDR_GTIMER_CONFIGURATION */ "", 29743 /* FDR_GTIMER_CYCLE */ "", 29744 /* FDR_GTIMER_TRIGGER */ "", 29745 /* FDR_INBAND_HEADER */ "", 29746 /* FDR_INBAND_HEADER_FDR_IN */ "", 29747 /* FDR_INBAND_HEADER_VALID */ "", 29748 /* FDR_INBAND_HEADER_VALID_FDR_IN */ "", 29749 /* FDR_INBAND_PAYLOAD_LSB */ "", 29750 /* FDR_INBAND_PAYLOAD_LSB_FDR_IN */ "", 29751 /* FDR_INBAND_PAYLOAD_MSB */ "", 29752 /* FDR_INBAND_PAYLOAD_MSB_FDR_IN */ "", 29753 /* FDR_INDIRECT_COMMAND */ "", 29754 /* FDR_INDIRECT_COMMAND_ADDRESS */ "", 29755 /* FDR_INDIRECT_COMMAND_RD_DATA */ "", 29756 /* FDR_INDIRECT_COMMAND_WR_DATA */ "", 29757 /* FDR_INDIRECT_FORCE_BUBBLE */ "", 29758 /* FDR_INITIATE_ECC_1B_ERRORS_PRIMARY */ "", 29759 /* FDR_INITIATE_ECC_1B_ERRORS_SECONDARY */ "", 29760 /* FDR_INITIATE_ECC_2B_ERRORS_PRIMARY */ "", 29761 /* FDR_INITIATE_ECC_2B_ERRORS_SECONDARY */ "", 29762 /* FDR_INTERRUPT_MASK_REGISTER */ "", 29763 /* FDR_INTERRUPT_MASK_REGISTER_1 */ "", 29764 /* FDR_INTERRUPT_MASK_REGISTER_2 */ "", 29765 /* FDR_INTERRUPT_MASK_REGISTER_3 */ "", 29766 /* FDR_INTERRUPT_REGISTER */ "", 29767 /* FDR_INTERRUPT_REGISTER_1 */ "", 29768 /* FDR_INTERRUPT_REGISTER_2 */ "", 29769 /* FDR_INTERRUPT_REGISTER_3 */ "", 29770 /* FDR_INTERRUPT_REGISTER_1_TEST */ "", 29771 /* FDR_INTERRUPT_REGISTER_2_TEST */ "", 29772 /* FDR_INTERRUPT_REGISTER_3_TEST */ "", 29773 /* FDR_INTERRUPT_REGISTER_TEST */ "", 29774 /* FDR_LINK_FIFO_CONFIG */ "", 29775 /* FDR_LINK_FIFO_PIPE_PARTITION */ "", 29776 /* FDR_LINK_FIFO_STATUS_PRIMARY */ "", 29777 /* FDR_LINK_FIFO_STATUS_SECONDARY */ "", 29778 /* FDR_LINK_FIFO_TYPE_BMP */ "", 29779 /* FDR_LINK_LEVEL_FLOW_CONTROL */ "", 29780 /* FDR_LINK_UP_STATUS_CHANGED_FROM_FDRA_PRIMARY */ "", 29781 /* FDR_LINK_UP_STATUS_CHANGED_FROM_FDRA_SECONDARY */ "", 29782 /* FDR_LINK_UP_STATUS_CHANGED_FROM_FDRB_PRIMARY */ "", 29783 /* FDR_LINK_UP_STATUS_CHANGED_FROM_FDRB_SECONDARY */ "", 29784 /* FDR_LINK_UP_STATUS_CHANGED_FROM_MACN_P_1 */ "", 29785 /* FDR_LINK_UP_STATUS_CHANGED_FROM_MACN_P_2 */ "", 29786 /* FDR_LINK_UP_STATUS_CHANGED_FROM_MACN_P_3 */ "", 29787 /* FDR_LINK_UP_STATUS_FROM_FDRA_PRIMARY */ "", 29788 /* FDR_LINK_UP_STATUS_FROM_FDRA_P_2 */ "", 29789 /* FDR_LINK_UP_STATUS_FROM_FDRA_P_3 */ "", 29790 /* FDR_LINK_UP_STATUS_FROM_FDRA_SECONDARY */ "", 29791 /* FDR_LINK_UP_STATUS_FROM_FDRB_PRIMARY */ "", 29792 /* FDR_LINK_UP_STATUS_FROM_FDRB_P_2 */ "", 29793 /* FDR_LINK_UP_STATUS_FROM_FDRB_P_3 */ "", 29794 /* FDR_LINK_UP_STATUS_FROM_FDRB_SECONDARY */ "", 29795 /* FDR_LINK_UP_STATUS_FROM_MACN_P_1 */ "", 29796 /* FDR_LINK_UP_STATUS_FROM_MACN_P_2 */ "", 29797 /* FDR_LINK_UP_STATUS_FROM_MACN_P_3 */ "", 29798 /* FDR_LOCAL_FIFO_RCI_LEVEL */ "", 29799 /* FDR_OFM_CLASS_DROP_TH */ "", 29800 /* FDR_OFM_CORE_FIFO_CONFIG */ "", 29801 /* FDR_OFM_FIFO_OVFLW_DROP_CNT_P */ "", 29802 /* FDR_OFM_FIFO_PIPE_PARTITION */ "", 29803 /* FDR_OFM_FIFO_TRAFFIC_CLASS_DROP_CNT_P */ "", 29804 /* FDR_PARITY_ERR_CNT */ "", 29805 /* FDR_PAR_ERR_INITIATE */ "", 29806 /* FDR_PAR_ERR_MEM_MASK */ "", 29807 /* FDR_PCMI_0 */ "", 29808 /* FDR_PCMI_1 */ "", 29809 /* FDR_PCMI_2 */ "", 29810 /* FDR_PCMI_3 */ "", 29811 /* FDR_PCMI_4 */ "", 29812 /* FDR_PCMI_0_S */ "", 29813 /* FDR_PCMI_0_T */ "", 29814 /* FDR_PCMI_1_S */ "", 29815 /* FDR_PCMI_1_T */ "", 29816 /* FDR_PCMI_2_S */ "", 29817 /* FDR_PCMI_2_T */ "", 29818 /* FDR_PCMI_3_S */ "", 29819 /* FDR_PCMI_3_T */ "", 29820 /* FDR_PCMI_4_S */ "", 29821 /* FDR_PCMI_4_T */ "", 29822 /* FDR_PROGRAMMABLE_CELLS_COUNTER_PRIMARY */ "", 29823 /* FDR_PROGRAMMABLE_CELLS_COUNTER_SECONDARY */ "", 29824 /* FDR_PROGRAMMABLE_DATA_CELL_COUNTER_0 */ "", 29825 /* FDR_PROGRAMMABLE_DATA_CELL_COUNTER_1 */ "", 29826 /* FDR_PROGRAMMABLE_DATA_CELL_COUNTER_MASK_0 */ "", 29827 /* FDR_PROGRAMMABLE_DATA_CELL_COUNTER_MASK_1 */ "", 29828 /* FDR_P_1_CELL_IN_CNT */ "", 29829 /* FDR_P_1_CPU_DATA_CELL_A */ "", 29830 /* FDR_P_1_CPU_DATA_CELL_B */ "", 29831 /* FDR_P_1_CPU_DATA_CELL_C */ "", 29832 /* FDR_P_1_CPU_DATA_CELL_D */ "", 29833 /* FDR_P_1_ECC_1B_ERR_CNT */ "", 29834 /* FDR_P_1_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 29835 /* FDR_P_1_ECC_2B_ERR_CNT */ "", 29836 /* FDR_P_1_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 29837 /* FDR_P_1_ERROR_FILTER_CNT */ "", 29838 /* FDR_P_1_FDR_DISCARD_COUNTER_A */ "", 29839 /* FDR_P_1_FDR_DISCARD_COUNTER_B */ "", 29840 /* FDR_P_1_FDR_DISCARD_COUNTER_MACN */ "", 29841 /* FDR_P_1_FDR_FIFOS_STATUSES_MAC */ "", 29842 /* FDR_P_1_FDR_FIFO_DISCARD_COUNTER_A */ "", 29843 /* FDR_P_1_FDR_FIFO_DISCARD_COUNTER_B */ "", 29844 /* FDR_P_1_FDR_FIFO_DISCARD_COUNTER_MACN */ "", 29845 /* FDR_P_1_FDR_OUT_SRC_FIFO_INFO_1 */ "", 29846 /* FDR_P_1_FDR_OUT_SRC_FIFO_INFO_2 */ "", 29847 /* FDR_P_1_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDRA */ "", 29848 /* FDR_P_1_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDR_B */ "", 29849 /* FDR_P_1_INITIATE_ECC_1B_ERRORS */ "", 29850 /* FDR_P_1_INITIATE_ECC_1B_ERRORS_A */ "", 29851 /* FDR_P_1_INITIATE_ECC_2B_ERRORS */ "", 29852 /* FDR_P_1_INITIATE_ECC_2B_ERRORS_A */ "", 29853 /* FDR_P_1_LINK_FIFO_STATUS */ "", 29854 /* FDR_P_1_PROGRAMMABLE_CELLS_COUNTER */ "", 29855 /* FDR_P_2_CELL_IN_CNT */ "", 29856 /* FDR_P_2_ECC_1B_ERR_CNT */ "", 29857 /* FDR_P_2_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 29858 /* FDR_P_2_ECC_2B_ERR_CNT */ "", 29859 /* FDR_P_2_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 29860 /* FDR_P_2_ERROR_FILTER_CNT */ "", 29861 /* FDR_P_2_FDR_DISCARD_COUNTER_A */ "", 29862 /* FDR_P_2_FDR_DISCARD_COUNTER_B */ "", 29863 /* FDR_P_2_FDR_DISCARD_COUNTER_MACN */ "", 29864 /* FDR_P_2_FDR_FIFOS_STATUSES_MAC */ "", 29865 /* FDR_P_2_FDR_FIFO_DISCARD_COUNTER_A */ "", 29866 /* FDR_P_2_FDR_FIFO_DISCARD_COUNTER_B */ "", 29867 /* FDR_P_2_FDR_FIFO_DISCARD_COUNTER_MACN */ "", 29868 /* FDR_P_2_FDR_OUT_SRC_FIFO_INFO_1 */ "", 29869 /* FDR_P_2_FDR_OUT_SRC_FIFO_INFO_2 */ "", 29870 /* FDR_P_2_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDRA */ "", 29871 /* FDR_P_2_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDR_B */ "", 29872 /* FDR_P_2_INITIATE_ECC_1B_ERRORS */ "", 29873 /* FDR_P_2_INITIATE_ECC_2B_ERRORS */ "", 29874 /* FDR_P_2_LINK_FIFO_STATUS */ "", 29875 /* FDR_P_2_LINK_UP_STATUS_CHANGED_FROM_FDRA */ "", 29876 /* FDR_P_2_LINK_UP_STATUS_CHANGED_FROM_FDRB */ "", 29877 /* FDR_P_2_PROGRAMMABLE_CELLS_COUNTER */ "", 29878 /* FDR_P_3_CELL_IN_CNT */ "", 29879 /* FDR_P_3_ECC_1B_ERR_CNT */ "", 29880 /* FDR_P_3_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 29881 /* FDR_P_3_ECC_2B_ERR_CNT */ "", 29882 /* FDR_P_3_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 29883 /* FDR_P_3_ERROR_FILTER_CNT */ "", 29884 /* FDR_P_3_FDR_DISCARD_COUNTER_A */ "", 29885 /* FDR_P_3_FDR_DISCARD_COUNTER_B */ "", 29886 /* FDR_P_3_FDR_DISCARD_COUNTER_MACN */ "", 29887 /* FDR_P_3_FDR_FIFOS_STATUSES_MAC */ "", 29888 /* FDR_P_3_FDR_FIFO_DISCARD_COUNTER_A */ "", 29889 /* FDR_P_3_FDR_FIFO_DISCARD_COUNTER_B */ "", 29890 /* FDR_P_3_FDR_FIFO_DISCARD_COUNTER_MACN */ "", 29891 /* FDR_P_3_FDR_OUT_SRC_FIFO_INFO_1 */ "", 29892 /* FDR_P_3_FDR_OUT_SRC_FIFO_INFO_2 */ "", 29893 /* FDR_P_3_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDRA */ "", 29894 /* FDR_P_3_FDR_OVERFLOWS_AND_FIFOS_STATUSES_FDR_B */ "", 29895 /* FDR_P_3_INITIATE_ECC_1B_ERRORS */ "", 29896 /* FDR_P_3_INITIATE_ECC_2B_ERRORS */ "", 29897 /* FDR_P_3_LINK_FIFO_STATUS */ "", 29898 /* FDR_P_3_LINK_UP_STATUS_CHANGED_FROM_FDRA */ "", 29899 /* FDR_P_3_LINK_UP_STATUS_CHANGED_FROM_FDRB */ "", 29900 /* FDR_P_3_PROGRAMMABLE_CELLS_COUNTER */ "", 29901 /* FDR_P_CELL_IN_CNT */ "", 29902 /* FDR_P_DROP_FILTER_CNT */ "", 29903 /* FDR_P_DROP_FILTER_EN */ "", 29904 /* FDR_P_ERROR_FILTER_CNT */ "", 29905 /* FDR_P_FDR_IN_OUTGOING_CELL_CNT */ "", 29906 /* FDR_P_FDR_OUT_OUTGOING_TAG_CNT */ "", 29907 /* FDR_P_PROGRAMMABLE_CELLS_COUNTER */ "", 29908 /* FDR_RCI_FDR_IN_TH_TYPE */ "", 29909 /* FDR_RCI_FDR_OUT_TH */ "", 29910 /* FDR_RCI_FDR_OUT_TOTAL_TH */ "", 29911 /* FDR_REG_0041 */ "", 29912 /* FDR_REG_0085 */ "", 29913 /* FDR_REG_0086 */ "", 29914 /* FDR_REG_0090 */ "", 29915 /* FDR_REG_0091 */ "", 29916 /* FDR_REG_0092 */ "", 29917 /* FDR_REG_0093 */ "", 29918 /* FDR_REG_0111 */ "", 29919 /* FDR_REG_0112 */ "", 29920 /* FDR_REG_0146 */ "", 29921 /* FDR_REG_0159 */ "", 29922 /* FDR_REG_0163 */ "", 29923 /* FDR_REG_0164 */ "", 29924 /* FDR_REG_0179 */ "", 29925 /* FDR_REG_0191 */ "", 29926 /* FDR_REG_0212 */ "", 29927 /* FDR_REG_0214 */ "", 29928 /* FDR_REG_0216 */ "", 29929 /* FDR_REG_0218 */ "", 29930 /* FDR_REG_0221 */ "", 29931 /* FDR_REG_0223 */ "", 29932 /* FDR_REG_0224 */ "", 29933 /* FDR_REG_0226 */ "", 29934 /* FDR_REG_0228 */ "", 29935 /* FDR_REG_0232 */ "", 29936 /* FDR_REG_0234 */ "", 29937 /* FDR_REG_0236 */ "", 29938 /* FDR_REG_0238 */ "", 29939 /* FDR_REG_0239 */ "", 29940 /* FDR_REG_0241 */ "", 29941 /* FDR_REG_0242 */ "", 29942 /* FDR_REG_0243 */ "", 29943 /* FDR_REG_0244 */ "", 29944 /* FDR_REG_0245 */ "", 29945 /* FDR_REG_0246 */ "", 29946 /* FDR_REG_0247 */ "", 29947 /* FDR_REG_0248 */ "", 29948 /* FDR_REG_0250 */ "", 29949 /* FDR_REG_0252 */ "", 29950 /* FDR_REG_0256 */ "", 29951 /* FDR_REG_0257 */ "", 29952 /* FDR_REG_0258 */ "", 29953 /* FDR_REG_0262 */ "", 29954 /* FDR_REG_0264 */ "", 29955 /* FDR_REG_0268 */ "", 29956 /* FDR_REG_0269 */ "", 29957 /* FDR_REG_0270 */ "", 29958 /* FDR_REG_0271 */ "", 29959 /* FDR_REG_0272 */ "", 29960 /* FDR_REG_0274 */ "", 29961 /* FDR_REG_0275 */ "", 29962 /* FDR_REG_0276 */ "", 29963 /* FDR_REG_0277 */ "", 29964 /* FDR_REG_0278 */ "", 29965 /* FDR_REG_0279 */ "", 29966 /* FDR_REG_0280 */ "", 29967 /* FDR_REG_0282 */ "", 29968 /* FDR_REG_0283 */ "", 29969 /* FDR_REG_0284 */ "", 29970 /* FDR_REG_0286 */ "", 29971 /* FDR_REG_0287 */ "", 29972 /* FDR_REG_0288 */ "", 29973 /* FDR_REG_0290 */ "", 29974 /* FDR_REG_0323 */ "", 29975 /* FDR_REG_0324 */ "", 29976 /* FDR_REG_0325 */ "", 29977 /* FDR_REG_0326 */ "", 29978 /* FDR_REG_0327 */ "", 29979 /* FDR_REG_0328 */ "", 29980 /* FDR_REG_00A4 */ "", 29981 /* FDR_REG_00A6 */ "", 29982 /* FDR_REG_00AE */ "", 29983 /* FDR_REG_00AF */ "", 29984 /* FDR_REG_00C2 */ "", 29985 /* FDR_REG_00C3 */ "", 29986 /* FDR_REG_00C4 */ "", 29987 /* FDR_REG_00CE */ "", 29988 /* FDR_REG_00CF */ "", 29989 /* FDR_REG_00D0 */ "", 29990 /* FDR_REG_0100_1 */ "", 29991 /* FDR_REG_0100_2 */ "", 29992 /* FDR_REG_0100_3 */ "", 29993 /* FDR_REG_010C_1 */ "", 29994 /* FDR_REG_010C_2 */ "", 29995 /* FDR_REG_010C_3 */ "", 29996 /* FDR_REG_010D */ "", 29997 /* FDR_REG_0111_1 */ "", 29998 /* FDR_REG_0111_2 */ "", 29999 /* FDR_REG_0111_3 */ "", 30000 /* FDR_REG_011A */ "", 30001 /* FDR_REG_011D_1 */ "", 30002 /* FDR_REG_011D_2 */ "", 30003 /* FDR_REG_011D_3 */ "", 30004 /* FDR_REG_011E */ "", 30005 /* FDR_REG_012A_1 */ "", 30006 /* FDR_REG_012A_2 */ "", 30007 /* FDR_REG_012A_3 */ "", 30008 /* FDR_REG_016A */ "", 30009 /* FDR_REG_016B */ "", 30010 /* FDR_REG_016C */ "", 30011 /* FDR_REG_017E */ "", 30012 /* FDR_REG_017F */ "", 30013 /* FDR_REG_018C */ "", 30014 /* FDR_REG_019F */ "", 30015 /* FDR_REG_01A4 */ "", 30016 /* FDR_REG_01AA */ "", 30017 /* FDR_REG_01AC */ "", 30018 /* FDR_REG_01AE */ "", 30019 /* FDR_REG_01B2 */ "", 30020 /* FDR_REG_01B7 */ "", 30021 /* FDR_REG_01C4 */ "", 30022 /* FDR_REG_01C5 */ "", 30023 /* FDR_REG_01C7 */ "", 30024 /* FDR_REG_01CA */ "", 30025 /* FDR_REG_01CD */ "", 30026 /* FDR_REG_01D0 */ "", 30027 /* FDR_REG_01D3 */ "", 30028 /* FDR_REG_01D6 */ "", 30029 /* FDR_REG_01D7 */ "", 30030 /* FDR_REG_01D8 */ "", 30031 /* FDR_REG_01DA */ "", 30032 /* FDR_REG_01DB */ "", 30033 /* FDR_REG_01DC */ "", 30034 /* FDR_REG_01DD */ "", 30035 /* FDR_REG_01DE */ "", 30036 /* FDR_REG_01DF */ "", 30037 /* FDR_REG_01E0 */ "", 30038 /* FDR_REG_01EB */ "", 30039 /* FDR_REG_01EC */ "", 30040 /* FDR_REG_01F0 */ "", 30041 /* FDR_REG_01FE */ "", 30042 /* FDR_REG_021A */ "", 30043 /* FDR_REG_021C */ "", 30044 /* FDR_REG_021D */ "", 30045 /* FDR_REG_021F */ "", 30046 /* FDR_REG_022A */ "", 30047 /* FDR_REG_022C */ "", 30048 /* FDR_REG_022E */ "", 30049 /* FDR_REG_023A */ "", 30050 /* FDR_REG_023B */ "", 30051 /* FDR_REG_023C */ "", 30052 /* FDR_REG_023D */ "", 30053 /* FDR_REG_023E */ "", 30054 /* FDR_REG_023F */ "", 30055 /* FDR_REG_024A */ "", 30056 /* FDR_REG_025C */ "", 30057 /* FDR_REG_025E */ "", 30058 /* FDR_REG_026A */ "", 30059 /* FDR_REG_026C */ "", 30060 /* FDR_REG_026D */ "", 30061 /* FDR_REG_026E */ "", 30062 /* FDR_REG_027A */ "", 30063 /* FDR_REG_027B */ "", 30064 /* FDR_REG_027C */ "", 30065 /* FDR_REG_027D */ "", 30066 /* FDR_REG_027E */ "", 30067 /* FDR_REG_027F */ "", 30068 /* FDR_REG_028A */ "", 30069 /* FDR_REG_028B */ "", 30070 /* FDR_REG_028C */ "", 30071 /* FDR_REG_029E */ "", 30072 /* FDR_RESERVED_MIRROR_ADDR */ "", 30073 /* FDR_RESERVED_MTCD */ "", 30074 /* FDR_RESERVED_MTCP */ "", 30075 /* FDR_RESERVED_PCMI_0 */ "", 30076 /* FDR_RESERVED_PCMI_1 */ "", 30077 /* FDR_RESERVED_PCMI_2 */ "", 30078 /* FDR_RESERVED_PCMI_3 */ "", 30079 /* FDR_RESERVED_PCMI_4 */ "", 30080 /* FDR_RESERVED_PCMI_0_S */ "", 30081 /* FDR_RESERVED_PCMI_0_T */ "", 30082 /* FDR_RESERVED_PCMI_1_S */ "", 30083 /* FDR_RESERVED_PCMI_1_T */ "", 30084 /* FDR_RESERVED_PCMI_2_S */ "", 30085 /* FDR_RESERVED_PCMI_2_T */ "", 30086 /* FDR_RESERVED_PCMI_3_S */ "", 30087 /* FDR_RESERVED_PCMI_3_T */ "", 30088 /* FDR_RESERVED_PCMI_4_S */ "", 30089 /* FDR_RESERVED_PCMI_4_T */ "", 30090 /* FDR_RESERVED_SPARE_0 */ "", 30091 /* FDR_RESERVED_SPARE_1 */ "", 30092 /* FDR_RESERVED_SPARE_2 */ "", 30093 /* FDR_RESERVED_SPARE_3 */ "", 30094 /* FDR_SBUS_BROADCAST_ID */ "", 30095 /* FDR_SBUS_LAST_IN_CHAIN */ "", 30096 /* FDR_SPECIAL_CLOCK_CONTROLS */ "", 30097 /* FDR_SYNC_E_SELECT */ "", 30098 /* FDR_WFQ_CONFIG */ "", 30099 /* FDTL_AUTO_DOC_NAME_1 */ "", 30100 /* FDTL_AUTO_DOC_NAME_2 */ "", 30101 /* FDTL_AUTO_DOC_NAME_3 */ "", 30102 /* FDTL_ECC_1B_ERR_CNT */ "", 30103 /* FDTL_ECC_2B_ERR_CNT */ "", 30104 /* FDTL_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 30105 /* FDTL_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 30106 /* FDTL_ECC_INTERRUPT_REGISTER */ "", 30107 /* FDTL_ECC_INTERRUPT_REGISTER_MASK */ "", 30108 /* FDTL_ECC_INTERRUPT_REGISTER_TEST */ "", 30109 /* FDTL_ERROR_INITIATION_DATA */ "", 30110 /* FDTL_FDTL_REGISTER_1 */ "", 30111 /* FDTL_GTIMER_CONFIGURATION */ "", 30112 /* FDTL_GTIMER_CYCLE */ "", 30113 /* FDTL_INTERRUPT_MASK_REGISTER */ "", 30114 /* FDTL_INTERRUPT_REGISTER */ "", 30115 /* FDTL_INTERRUPT_REGISTER_TEST */ "", 30116 /* FDTL_LINK_RESET */ "", 30117 /* FDTL_PARALLEL_DATA_PATH */ "", 30118 /* FDTL_PCMI_0 */ "", 30119 /* FDTL_PCMI_1 */ "", 30120 /* FDTL_PCMI_2 */ "", 30121 /* FDTL_PCMI_3 */ "", 30122 /* FDTL_PCMI_4 */ "", 30123 /* FDTL_PCMI_0_S */ "", 30124 /* FDTL_PCMI_0_T */ "", 30125 /* FDTL_PCMI_1_S */ "", 30126 /* FDTL_PCMI_1_T */ "", 30127 /* FDTL_PCMI_2_S */ "", 30128 /* FDTL_PCMI_2_T */ "", 30129 /* FDTL_PCMI_3_S */ "", 30130 /* FDTL_PCMI_3_T */ "", 30131 /* FDTL_PCMI_4_S */ "", 30132 /* FDTL_PCMI_4_T */ "", 30133 /* FDTL_REG_0098 */ "", 30134 /* FDTL_REG_00A0 */ "", 30135 /* FDTL_REG_00A4 */ "", 30136 /* FDTL_REG_00A6 */ "", 30137 /* FDTL_REG_00AA */ "", 30138 /* FDTL_REG_00C2 */ "", 30139 /* FDTL_REG_00C3 */ "", 30140 /* FDTL_REG_00C4 */ "", 30141 /* FDTL_RESERVED_MIRROR_ADDR */ "", 30142 /* FDTL_RESERVED_MTCD */ "", 30143 /* FDTL_RESERVED_MTCP */ "", 30144 /* FDTL_RESERVED_SPARE_0 */ "", 30145 /* FDTL_RESERVED_SPARE_1 */ "", 30146 /* FDTL_RESERVED_SPARE_2 */ "", 30147 /* FDTL_RESERVED_SPARE_3 */ "", 30148 /* FDTL_SBUS_BROADCAST_ID */ "", 30149 /* FDTL_SBUS_LAST_IN_CHAIN */ "", 30150 /* FDTL_SPECIAL_CLOCK_CONTROLS */ "", 30151 /* FDT_AUTO_DOC_NAME_9 */ "", 30152 /* FDT_AUTO_DOC_NAME_10 */ "", 30153 /* FDT_AUTO_DOC_NAME_11 */ "", 30154 /* FDT_AUTO_DOC_NAME_12 */ "", 30155 /* FDT_AUTO_DOC_NAME_21 */ "", 30156 /* FDT_AUTO_DOC_NAME_22 */ "", 30157 /* FDT_AUTO_DOC_NAME_28 */ "", 30158 /* FDT_AUTO_DOC_NAME_29 */ "", 30159 /* FDT_BUNDLE_GROUPS */ "", 30160 /* FDT_BUNDLE_GROUPS_CNT */ "", 30161 /* FDT_CONTEXT_CELL_COUNTER */ "", 30162 /* FDT_CORE_MESHMC_CELL_CNT */ "", 30163 /* FDT_CPU_CELL_CNT */ "", 30164 /* FDT_CPU_DATA_CELL_0 */ "", 30165 /* FDT_CPU_DATA_CELL_1 */ "", 30166 /* FDT_CPU_DATA_CELL_2 */ "", 30167 /* FDT_CPU_DATA_CELL_3 */ "", 30168 /* FDT_CRC_DROPPED_CELL_CNT */ "", 30169 /* FDT_CRC_DROPPED_PCK_CNT */ "", 30170 /* FDT_DTQ_BADDR_0 */ "", 30171 /* FDT_DTQ_BADDR_1 */ "", 30172 /* FDT_DTQ_BADDR_2 */ "", 30173 /* FDT_DTQ_BADDR_3 */ "", 30174 /* FDT_DTQ_BADDR_4 */ "", 30175 /* FDT_DTQ_BADDR_5 */ "", 30176 /* FDT_DTQ_CELL_CNT */ "", 30177 /* FDT_DTQ_EADDR_5 */ "", 30178 /* FDT_DTQ_EN */ "", 30179 /* FDT_DTQ_WMK */ "", 30180 /* FDT_ECC_1B_ERR_CNT */ "", 30181 /* FDT_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 30182 /* FDT_ECC_2B_ERR_CNT */ "", 30183 /* FDT_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 30184 /* FDT_ECC_ERR_1B_INITIATE */ "", 30185 /* FDT_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 30186 /* FDT_ECC_ERR_2B_INITIATE */ "", 30187 /* FDT_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 30188 /* FDT_ECC_INTERRUPT_REGISTER */ "", 30189 /* FDT_ECC_INTERRUPT_REGISTER_MASK */ "", 30190 /* FDT_ECC_INTERRUPT_REGISTER_TEST */ "", 30191 /* FDT_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 30192 /* FDT_ERROR_INITIATION_DATA */ "", 30193 /* FDT_FABRIC_BYTES_CORE_0_CTX_CNT */ "", 30194 /* FDT_FABRIC_BYTES_CORE_1_CTX_CNT */ "", 30195 /* FDT_FABRIC_CELLS_CNT */ "", 30196 /* FDT_FABRIC_DATA_BYTE_CNT */ "", 30197 /* FDT_FABRIC_PIPE_MAPPING */ "", 30198 /* FDT_FABRIC_SRD_RATE_CNT */ "", 30199 /* FDT_FABRIC_TDM_PIPE */ "", 30200 /* FDT_FDT_CONTEXTS_FABRIC_MAPPING */ "", 30201 /* FDT_FDT_CONTEXTS_INTERLEAVING */ "", 30202 /* FDT_FDT_ENABLER_REGISTER */ "", 30203 /* FDT_FDT_LLFC_MAPPING_CORE */ "", 30204 /* FDT_FDT_REGISTER_1 */ "", 30205 /* FDT_FDT_REGISTER_2 */ "", 30206 /* FDT_FDT_REGISTER_3 */ "", 30207 /* FDT_FDT_REGISTER_4 */ "", 30208 /* FDT_FDT_REGISTER_5 */ "", 30209 /* FDT_FDT_REGISTER_6 */ "", 30210 /* FDT_FDT_SEGMENTATION_AND_INTERLEAVING */ "", 30211 /* FDT_FDT_SEGMENTATION_AND_LLFC_MAPPING */ "", 30212 /* FDT_FDT_WFD */ "", 30213 /* FDT_FDT_WFD_LINK_LFSR_SEED */ "", 30214 /* FDT_FMAC_TX_DATA_CELL_SHAPER_EN */ "", 30215 /* FDT_FMC_GCI_FLOW_CONTROL */ "", 30216 /* FDT_FMC_GCI_FLOW_CONTROL_CORE */ "", 30217 /* FDT_GCI_LINK_MASK */ "", 30218 /* FDT_GLOBAL_GENERAL_CFG_1 */ "", 30219 /* FDT_GLOBAL_GENERAL_CFG_2 */ "", 30220 /* FDT_GLOBAL_MEM_OPTIONS */ "", 30221 /* FDT_GTIMER_CONFIGURATION */ "", 30222 /* FDT_GTIMER_CYCLE */ "", 30223 /* FDT_GTIMER_TRIGGER */ "", 30224 /* FDT_INDIRECT_COMMAND */ "", 30225 /* FDT_INDIRECT_COMMAND_ADDRESS */ "", 30226 /* FDT_INDIRECT_COMMAND_DATA_INCREMENT */ "", 30227 /* FDT_INDIRECT_COMMAND_RD_DATA */ "", 30228 /* FDT_INDIRECT_COMMAND_WIDE_MEM */ "", 30229 /* FDT_INDIRECT_COMMAND_WR_DATA */ "", 30230 /* FDT_INDIRECT_FORCE_BUBBLE */ "", 30231 /* FDT_INITIATE_ECC_1B_ERRORS */ "", 30232 /* FDT_INITIATE_ECC_2B_ERRORS */ "", 30233 /* FDT_INITIATE_PARITY_ERRORS */ "", 30234 /* FDT_INTERRUPT_MASK_REGISTER */ "", 30235 /* FDT_INTERRUPT_REGISTER */ "", 30236 /* FDT_INTERRUPT_REGISTER_TEST */ "", 30237 /* FDT_IN_BAND_MANAGMENENT */ "", 30238 /* FDT_IN_BAND_STATUS_A */ "", 30239 /* FDT_IN_BAND_STATUS_B */ "", 30240 /* FDT_IPT_0_WFQ_CONFIG */ "", 30241 /* FDT_IPT_1_WFQ_CONFIG */ "", 30242 /* FDT_IPT_CTRL_FIFO_SER_FREEZE */ "", 30243 /* FDT_IPT_DESC_CELL_COUNTER */ "", 30244 /* FDT_IPT_FIFOS_WFQ_CONFIGURATION */ "", 30245 /* FDT_IRE_DESC_CELL_COUNTER */ "", 30246 /* FDT_LB_RR_PTR_CTX */ "", 30247 /* FDT_LCI */ "", 30248 /* FDT_LCI_LINK_FACTOR */ "", 30249 /* FDT_LCI_LINK_SCORE */ "", 30250 /* FDT_LCI_RATE */ "", 30251 /* FDT_LCI_SEVERITY_SCORE_THR */ "", 30252 /* FDT_LCI_STABEL */ "", 30253 /* FDT_LCI_STATUS */ "", 30254 /* FDT_LINK_BITMAP_CONFIGURATION */ "", 30255 /* FDT_LINK_BUNDLE_BITMAP */ "", 30256 /* FDT_LINK_LOAD_CONFIGURATION */ "", 30257 /* FDT_LINK_LOAD_CONFIGURATION_CORE */ "", 30258 /* FDT_LINK_READY_THR */ "", 30259 /* FDT_LINK_RESET */ "", 30260 /* FDT_LOAD_BALANCING_CONFIGURATION */ "", 30261 /* FDT_LOAD_BALANCING_SWITCH_CONFIGURATION */ "", 30262 /* FDT_LOCAL_TDM_CELLS_COUNTER */ "", 30263 /* FDT_MC_SIMULTANIOUS_REPLICATIONS_EN */ "", 30264 /* FDT_MESH_DEST_ID */ "", 30265 /* FDT_MESH_MC_DTQ_LOCAL_BACKPRESSURE_EN */ "", 30266 /* FDT_MESH_MC_RELICATION */ "", 30267 /* FDT_MIN_NOF_LINKS_DROP */ "", 30268 /* FDT_MIN_NOF_LINKS_DROP_CNT */ "", 30269 /* FDT_MULTICAST_ID_MASK */ "", 30270 /* FDT_NON_TDM_LINK_MASK */ "", 30271 /* FDT_PARITY_ERR_CNT */ "", 30272 /* FDT_PARITY_ERR_MONITOR_MEM_MASK */ "", 30273 /* FDT_PAR_ERR_INITIATE */ "", 30274 /* FDT_PAR_ERR_MEM_MASK */ "", 30275 /* FDT_PCMI_0 */ "", 30276 /* FDT_PCMI_1 */ "", 30277 /* FDT_PCMI_2 */ "", 30278 /* FDT_PCMI_3 */ "", 30279 /* FDT_PCMI_4 */ "", 30280 /* FDT_PCMI_0_S */ "", 30281 /* FDT_PCMI_0_T */ "", 30282 /* FDT_PCMI_1_S */ "", 30283 /* FDT_PCMI_1_T */ "", 30284 /* FDT_PCMI_2_S */ "", 30285 /* FDT_PCMI_2_T */ "", 30286 /* FDT_PCMI_3_S */ "", 30287 /* FDT_PCMI_3_T */ "", 30288 /* FDT_PCMI_4_S */ "", 30289 /* FDT_PCMI_4_T */ "", 30290 /* FDT_REG_0085 */ "", 30291 /* FDT_REG_0086 */ "", 30292 /* FDT_REG_0090 */ "", 30293 /* FDT_REG_0091 */ "", 30294 /* FDT_REG_0092 */ "", 30295 /* FDT_REG_0093 */ "", 30296 /* FDT_REG_0098 */ "", 30297 /* FDT_REG_0131 */ "", 30298 /* FDT_REG_0134 */ "", 30299 /* FDT_REG_0137 */ "", 30300 /* FDT_REG_0138 */ "", 30301 /* FDT_REG_0146 */ "", 30302 /* FDT_REG_0148 */ "", 30303 /* FDT_REG_0163 */ "", 30304 /* FDT_REG_0164 */ "", 30305 /* FDT_REG_0165 */ "", 30306 /* FDT_REG_0180 */ "", 30307 /* FDT_REG_0238 */ "", 30308 /* FDT_REG_0239 */ "", 30309 /* FDT_REG_0240 */ "", 30310 /* FDT_REG_0241 */ "", 30311 /* FDT_REG_0242 */ "", 30312 /* FDT_REG_0243 */ "", 30313 /* FDT_REG_0244 */ "", 30314 /* FDT_REG_0245 */ "", 30315 /* FDT_REG_00A0 */ "", 30316 /* FDT_REG_00A4 */ "", 30317 /* FDT_REG_00A6 */ "", 30318 /* FDT_REG_00AA */ "", 30319 /* FDT_REG_00AE */ "", 30320 /* FDT_REG_00AF */ "", 30321 /* FDT_REG_00C0 */ "", 30322 /* FDT_REG_00C1 */ "", 30323 /* FDT_REG_00C2 */ "", 30324 /* FDT_REG_00C3 */ "", 30325 /* FDT_REG_00C4 */ "", 30326 /* FDT_REG_00CE */ "", 30327 /* FDT_REG_00CF */ "", 30328 /* FDT_REG_00D0 */ "", 30329 /* FDT_REG_013B */ "", 30330 /* FDT_REG_013C */ "", 30331 /* FDT_REG_016B */ "", 30332 /* FDT_REG_016C */ "", 30333 /* FDT_REG_017B */ "", 30334 /* FDT_REG_017C */ "", 30335 /* FDT_REG_019E */ "", 30336 /* FDT_REG_020B */ "", 30337 /* FDT_REG_023D */ "", 30338 /* FDT_REG_023E */ "", 30339 /* FDT_REG_023F */ "", 30340 /* FDT_REG_024D */ "", 30341 /* FDT_REG_024E */ "", 30342 /* FDT_REG_024F */ "", 30343 /* FDT_RESERVED_MIRROR_ADDR */ "", 30344 /* FDT_RESERVED_MTCD */ "", 30345 /* FDT_RESERVED_MTCP */ "", 30346 /* FDT_RESERVED_SPARE_0 */ "", 30347 /* FDT_RESERVED_SPARE_1 */ "", 30348 /* FDT_RESERVED_SPARE_2 */ "", 30349 /* FDT_RESERVED_SPARE_3 */ "", 30350 /* FDT_SBUS_BROADCAST_ID */ "", 30351 /* FDT_SBUS_LAST_IN_CHAIN */ "", 30352 /* FDT_SIMPLE_PACKING_CONFIGURATION */ "", 30353 /* FDT_SPECIAL_CLOCK_CONTROLS */ "", 30354 /* FDT_TDM_CELLS_COUNTER */ "", 30355 /* FDT_TDM_CONFIGURATION */ "", 30356 /* FDT_TDM_LINK_MASK */ "", 30357 /* FDT_TRANSMITTED_DATA_CELLS_COUNTER */ "", 30358 /* FDT_TRANSMIT_CELL_OUTPUT_LINK_NUMBER */ "", 30359 /* FDT_TRANSMIT_DATA_CELL_TRIGGER */ "", 30360 /* FDT_UNREACHABLE_DESTINATION_DISCARDED */ "", 30361 /* FDT_UNREACHABLE_DESTINATION_DISCARDED_CELLS_COUNTER */ "", 30362 /* FDT_WFQ_0_CONFIG */ "", 30363 /* FDT_WFQ_1_CONFIG */ "", 30364 /* FDT_WFQ_CORE_CONFIG */ "", 30365 /* FE_CLRT */ "", 30366 /* FE_EXCESSIVE_DEFER_LIMIT */ "", 30367 /* FE_IPGR */ "", 30368 /* FE_IPGT */ "", 30369 /* FE_MAC1 */ "", 30370 /* FE_MAC2 */ "", 30371 /* FE_MAXF */ "", 30372 /* FE_SUPP */ "", 30373 /* FE_TEST */ "", 30374 /* FILTERMATCHCOUNT_ECC_STATUS */ "", 30375 /* FIRST_FRAGMENT_DROP_STATE_CELL */ "", 30376 /* FIRST_FRAGMENT_DROP_STATE_PACKET */ "", 30377 /* FLEXIBLE_IPV6_EXT_HDR */ "", 30378 /* FLEX_EDITOR_ECC_PARITY_CONTROL_1 */ "", 30379 /* FLEX_EDITOR_ECC_PARITY_CONTROL_2 */ "", 30380 /* FLEX_EDITOR_ECC_PARITY_CONTROL_3 */ "", 30381 /* FLEX_EDITOR_EN_COR_ERR_RPT_1 */ "", 30382 /* FLEX_EDITOR_EN_COR_ERR_RPT_2 */ "", 30383 /* FLEX_EDITOR_EN_COR_ERR_RPT_3 */ "", 30384 /* FLEX_EDITOR_ERROR_VECTOR */ "", 30385 /* FLEX_EDITOR_ERROR_VECTOR_PIPE0 */ "", 30386 /* FLEX_EDITOR_ERROR_VECTOR_PIPE1 */ "", 30387 /* FLEX_EDITOR_FIXED_L2_0_RAM_CONTROL_1 */ "", 30388 /* FLEX_EDITOR_FIXED_L2_0_RAM_CONTROL_1_PIPE0 */ "", 30389 /* FLEX_EDITOR_FIXED_L2_0_RAM_CONTROL_1_PIPE1 */ "", 30390 /* FLEX_EDITOR_FIXED_L2_1_RAM_CONTROL_1 */ "", 30391 /* FLEX_EDITOR_FIXED_L2_1_RAM_CONTROL_1_PIPE0 */ "", 30392 /* FLEX_EDITOR_FIXED_L2_1_RAM_CONTROL_1_PIPE1 */ "", 30393 /* FLEX_EDITOR_FIXED_LOOPBACK_0_RAM_CONTROL_1 */ "", 30394 /* FLEX_EDITOR_FIXED_LOOPBACK_0_RAM_CONTROL_1_PIPE0 */ "", 30395 /* FLEX_EDITOR_FIXED_LOOPBACK_0_RAM_CONTROL_1_PIPE1 */ "", 30396 /* FLEX_EDITOR_FIXED_TUNNEL_0_RAM_CONTROL_1 */ "", 30397 /* FLEX_EDITOR_FIXED_TUNNEL_0_RAM_CONTROL_1_PIPE0 */ "", 30398 /* FLEX_EDITOR_FIXED_TUNNEL_0_RAM_CONTROL_1_PIPE1 */ "", 30399 /* FLEX_EDITOR_FLEX_HDR_0_RAM_CONTROL_1 */ "", 30400 /* FLEX_EDITOR_FLEX_HDR_0_RAM_CONTROL_2 */ "", 30401 /* FLEX_EDITOR_FLEX_HDR_0_RAM_CONTROL_1_PIPE0 */ "", 30402 /* FLEX_EDITOR_FLEX_HDR_0_RAM_CONTROL_1_PIPE1 */ "", 30403 /* FLEX_EDITOR_FLEX_HDR_0_RAM_CONTROL_2_PIPE0 */ "", 30404 /* FLEX_EDITOR_FLEX_HDR_0_RAM_CONTROL_2_PIPE1 */ "", 30405 /* FLEX_EDITOR_FLEX_HDR_0_USER_FIELD_0 */ "", 30406 /* FLEX_EDITOR_FLEX_HDR_0_USER_FIELD_1 */ "", 30407 /* FLEX_EDITOR_FLEX_HDR_0_USER_FIELD_2 */ "", 30408 /* FLEX_EDITOR_FLEX_HDR_0_USER_FIELD_3 */ "", 30409 /* FLEX_EDITOR_FLEX_HDR_1_RAM_CONTROL_1 */ "", 30410 /* FLEX_EDITOR_FLEX_HDR_1_RAM_CONTROL_2 */ "", 30411 /* FLEX_EDITOR_FLEX_HDR_1_RAM_CONTROL_1_PIPE0 */ "", 30412 /* FLEX_EDITOR_FLEX_HDR_1_RAM_CONTROL_1_PIPE1 */ "", 30413 /* FLEX_EDITOR_FLEX_HDR_1_RAM_CONTROL_2_PIPE0 */ "", 30414 /* FLEX_EDITOR_FLEX_HDR_1_RAM_CONTROL_2_PIPE1 */ "", 30415 /* FLEX_EDITOR_FLEX_HDR_1_USER_FIELD_0 */ "", 30416 /* FLEX_EDITOR_FLEX_HDR_1_USER_FIELD_1 */ "", 30417 /* FLEX_EDITOR_FLEX_HDR_1_USER_FIELD_2 */ "", 30418 /* FLEX_EDITOR_FLEX_HDR_1_USER_FIELD_3 */ "", 30419 /* FLEX_EDITOR_FLEX_HDR_2_RAM_CONTROL_1 */ "", 30420 /* FLEX_EDITOR_FLEX_HDR_2_RAM_CONTROL_2 */ "", 30421 /* FLEX_EDITOR_FLEX_HDR_2_RAM_CONTROL_1_PIPE0 */ "", 30422 /* FLEX_EDITOR_FLEX_HDR_2_RAM_CONTROL_1_PIPE1 */ "", 30423 /* FLEX_EDITOR_FLEX_HDR_2_RAM_CONTROL_2_PIPE0 */ "", 30424 /* FLEX_EDITOR_FLEX_HDR_2_RAM_CONTROL_2_PIPE1 */ "", 30425 /* FLEX_EDITOR_FLEX_HDR_2_USER_FIELD_0 */ "", 30426 /* FLEX_EDITOR_FLEX_HDR_2_USER_FIELD_1 */ "", 30427 /* FLEX_EDITOR_FLEX_HDR_2_USER_FIELD_2 */ "", 30428 /* FLEX_EDITOR_FLEX_HDR_2_USER_FIELD_3 */ "", 30429 /* FLEX_EDITOR_HG_EH_CONTROL */ "", 30430 /* FLEX_EDITOR_HIGIG_HEADER_CONFIG */ "", 30431 /* FLEX_EDITOR_MHC_CHECKSUM_MASK_0_BITMAP_64 */ "", 30432 /* FLEX_EDITOR_MHC_CHECKSUM_MASK_1_BITMAP_64 */ "", 30433 /* FLEX_EDITOR_MIRROR_0_RAM_CONTROL_1 */ "", 30434 /* FLEX_EDITOR_MIRROR_0_RAM_CONTROL_1_PIPE0 */ "", 30435 /* FLEX_EDITOR_MIRROR_0_RAM_CONTROL_1_PIPE1 */ "", 30436 /* FLEX_EDITOR_MMU_PKT_LENGTH_ADJUST */ "", 30437 /* FLEX_EDITOR_RW_0_RAM_CONTROL_1 */ "", 30438 /* FLEX_EDITOR_RW_0_RAM_CONTROL_1_PIPE0 */ "", 30439 /* FLEX_EDITOR_RW_0_RAM_CONTROL_1_PIPE1 */ "", 30440 /* FLEX_EDITOR_RW_0_USER_FIELD_0 */ "", 30441 /* FLEX_EDITOR_RW_0_USER_FIELD_1 */ "", 30442 /* FLEX_EDITOR_RW_0_USER_FIELD_2 */ "", 30443 /* FLEX_EDITOR_RW_0_USER_FIELD_3 */ "", 30444 /* FLEX_EDITOR_RW_1_RAM_CONTROL_1 */ "", 30445 /* FLEX_EDITOR_RW_1_RAM_CONTROL_1_PIPE0 */ "", 30446 /* FLEX_EDITOR_RW_1_RAM_CONTROL_1_PIPE1 */ "", 30447 /* FLEX_EDITOR_RW_1_USER_FIELD_0 */ "", 30448 /* FLEX_EDITOR_RW_1_USER_FIELD_1 */ "", 30449 /* FLEX_EDITOR_RW_1_USER_FIELD_2 */ "", 30450 /* FLEX_EDITOR_RW_1_USER_FIELD_3 */ "", 30451 /* FLEX_EDITOR_TUNNEL_PIMDR1_CFG0 */ "", 30452 /* FLEX_EDITOR_TUNNEL_PIMDR1_CFG1 */ "", 30453 /* FLEX_EDITOR_TUNNEL_PIMDR2_CFG0 */ "", 30454 /* FLEX_EDITOR_TUNNEL_PIMDR2_CFG1 */ "", 30455 /* FLEX_EDITOR_VXLAN_CONTROL_64 */ "", 30456 /* FLEX_EDITOR_ZONE_0_M_E_RAM_CONTROL_1 */ "", 30457 /* FLEX_EDITOR_ZONE_0_M_E_RAM_CONTROL_2 */ "", 30458 /* FLEX_EDITOR_ZONE_0_M_E_RAM_CONTROL_1_PIPE0 */ "", 30459 /* FLEX_EDITOR_ZONE_0_M_E_RAM_CONTROL_1_PIPE1 */ "", 30460 /* FLEX_EDITOR_ZONE_0_M_E_RAM_CONTROL_2_PIPE0 */ "", 30461 /* FLEX_EDITOR_ZONE_0_M_E_RAM_CONTROL_2_PIPE1 */ "", 30462 /* FLEX_EDITOR_ZONE_1_M_E_RAM_CONTROL_1 */ "", 30463 /* FLEX_EDITOR_ZONE_1_M_E_RAM_CONTROL_2 */ "", 30464 /* FLEX_EDITOR_ZONE_1_M_E_RAM_CONTROL_1_PIPE0 */ "", 30465 /* FLEX_EDITOR_ZONE_1_M_E_RAM_CONTROL_1_PIPE1 */ "", 30466 /* FLEX_EDITOR_ZONE_1_M_E_RAM_CONTROL_2_PIPE0 */ "", 30467 /* FLEX_EDITOR_ZONE_1_M_E_RAM_CONTROL_2_PIPE1 */ "", 30468 /* FLEX_EDITOR_ZONE_2_M_E_RAM_CONTROL_1 */ "", 30469 /* FLEX_EDITOR_ZONE_2_M_E_RAM_CONTROL_2 */ "", 30470 /* FLEX_EDITOR_ZONE_2_M_E_RAM_CONTROL_1_PIPE0 */ "", 30471 /* FLEX_EDITOR_ZONE_2_M_E_RAM_CONTROL_1_PIPE1 */ "", 30472 /* FLEX_EDITOR_ZONE_2_M_E_RAM_CONTROL_2_PIPE0 */ "", 30473 /* FLEX_EDITOR_ZONE_2_M_E_RAM_CONTROL_2_PIPE1 */ "", 30474 /* FLEX_EDITOR_ZONE_3_M_E_RAM_CONTROL_1 */ "", 30475 /* FLEX_EDITOR_ZONE_3_M_E_RAM_CONTROL_2 */ "", 30476 /* FLEX_EDITOR_ZONE_3_M_E_RAM_CONTROL_1_PIPE0 */ "", 30477 /* FLEX_EDITOR_ZONE_3_M_E_RAM_CONTROL_1_PIPE1 */ "", 30478 /* FLEX_EDITOR_ZONE_3_M_E_RAM_CONTROL_2_PIPE0 */ "", 30479 /* FLEX_EDITOR_ZONE_3_M_E_RAM_CONTROL_2_PIPE1 */ "", 30480 /* FLEX_EDITOR_ZONE_4_M_E_RAM_CONTROL_1 */ "", 30481 /* FLEX_EDITOR_ZONE_4_M_E_RAM_CONTROL_2 */ "", 30482 /* FLEX_EDITOR_ZONE_4_M_E_RAM_CONTROL_1_PIPE0 */ "", 30483 /* FLEX_EDITOR_ZONE_4_M_E_RAM_CONTROL_1_PIPE1 */ "", 30484 /* FLEX_EDITOR_ZONE_4_M_E_RAM_CONTROL_2_PIPE0 */ "", 30485 /* FLEX_EDITOR_ZONE_4_M_E_RAM_CONTROL_2_PIPE1 */ "", 30486 /* FLEX_HASH_PHB_HVE_CONTROL_1 */ "", 30487 /* FLEX_HASH_PHB_HVE_CONTROL_2 */ "", 30488 /* FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_CONFIG_64 */ "", 30489 /* FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_CONFIG_64_PIPE0 */ "", 30490 /* FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_CONFIG_64_PIPE1 */ "", 30491 /* FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_STATUS */ "", 30492 /* FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_STATUS_PIPE0 */ "", 30493 /* FLEX_RTAG7_HASH_TCAM_ONLY_CAM_BIST_STATUS_PIPE1 */ "", 30494 /* FLOOD_LEARN_CONTROL */ "", 30495 /* FLOOD_LEARN_KEY_TYPE_PORT_A */ "", 30496 /* FLOOD_LEARN_KEY_TYPE_PORT_B */ "", 30497 /* FLOOD_LEARN_MATCH_PORT_A */ "", 30498 /* FLOOD_LEARN_MATCH_PORT_B */ "", 30499 /* FLOW_CONTROL_XOFF_STATE */ "", 30500 /* FLOW_TRACKER_CONFIG */ "", 30501 /* FLUSH_CONTROL */ "", 30502 /* FMAC_ASYNC_FIFO_ACCESS_READ_DATA */ "", 30503 /* FMAC_ASYNC_FIFO_ACCESS_TRIGGER */ "", 30504 /* FMAC_ASYNC_FIFO_CONFIGURATION */ "", 30505 /* FMAC_AUTO_DOC_NAME_12 */ "", 30506 /* FMAC_AUTO_DOC_NAME_36 */ "", 30507 /* FMAC_AUTO_DOC_NAME_37 */ "", 30508 /* FMAC_AUTO_DOC_NAME_38 */ "", 30509 /* FMAC_AUTO_DOC_NAME_39 */ "", 30510 /* FMAC_AUTO_DOC_NAME_40 */ "", 30511 /* FMAC_AUTO_DOC_NAME_41 */ "", 30512 /* FMAC_AUTO_DOC_NAME_42 */ "", 30513 /* FMAC_AUTO_DOC_NAME_43 */ "", 30514 /* FMAC_AUTO_DOC_NAME_85 */ "", 30515 /* FMAC_BEC_CONFIGURATION */ "", 30516 /* FMAC_BEC_STATUS */ "", 30517 /* FMAC_BER_GEN_BITMAP */ "", 30518 /* FMAC_BER_GEN_PERIOD */ "", 30519 /* FMAC_CNTRL_INTRLVD_MODE_REG */ "", 30520 /* FMAC_CONTROL_CELL_BURST_REGISTER */ "", 30521 /* FMAC_DATA_FIFO_WMK */ "", 30522 /* FMAC_ECC_1B_ERR_ADDR */ "", 30523 /* FMAC_ECC_1B_ERR_CNT */ "", 30524 /* FMAC_ECC_1B_ERR_MONITOR_MEM_MASK */ "", 30525 /* FMAC_ECC_2B_ERR_ADDR */ "", 30526 /* FMAC_ECC_2B_ERR_CNT */ "", 30527 /* FMAC_ECC_2B_ERR_MONITOR_MEM_MASK */ "", 30528 /* FMAC_ECC_ERR_1B_INITIATE */ "", 30529 /* FMAC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 30530 /* FMAC_ECC_ERR_2B_INITIATE */ "", 30531 /* FMAC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 30532 /* FMAC_ECC_INTERRUPT_REGISTER */ "", 30533 /* FMAC_ECC_INTERRUPT_REGISTER_MASK */ "", 30534 /* FMAC_ECC_INTERRUPT_REGISTER_TEST */ "", 30535 /* FMAC_EDS_CONFIGURATION */ "", 30536 /* FMAC_EDS_STATUS */ "", 30537 /* FMAC_ERROR_INITIATION */ "", 30538 /* FMAC_ERROR_INITIATION_DATA */ "", 30539 /* FMAC_FABRIC_SYSTEM_CONFIG_0 */ "", 30540 /* FMAC_FABRIC_SYSTEM_CONFIG_1 */ "", 30541 /* FMAC_FAP_GLOBAL_GENERAL_CFG_1 */ "", 30542 /* FMAC_FBIST_CONFIGURATION_A */ "", 30543 /* FMAC_FBIST_CONFIGURATION_B */ "", 30544 /* FMAC_FBIST_STATUS */ "", 30545 /* FMAC_FE_GLOBAL_GENERAL_CFG_1 */ "", 30546 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_1 */ "", 30547 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_2 */ "", 30548 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_3 */ "", 30549 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_4 */ "", 30550 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_5 */ "", 30551 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_6 */ "", 30552 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_7 */ "", 30553 /* FMAC_FMAC_INTERRUPT_MASK_REGISTER_8 */ "", 30554 /* FMAC_FMAC_INTERRUPT_REGISTER_1 */ "", 30555 /* FMAC_FMAC_INTERRUPT_REGISTER_2 */ "", 30556 /* FMAC_FMAC_INTERRUPT_REGISTER_3 */ "", 30557 /* FMAC_FMAC_INTERRUPT_REGISTER_4 */ "", 30558 /* FMAC_FMAC_INTERRUPT_REGISTER_5 */ "", 30559 /* FMAC_FMAC_INTERRUPT_REGISTER_6 */ "", 30560 /* FMAC_FMAC_INTERRUPT_REGISTER_7 */ "", 30561 /* FMAC_FMAC_INTERRUPT_REGISTER_8 */ "", 30562 /* FMAC_FMAC_INTERRUPT_REGISTER_1_TEST */ "", 30563 /* FMAC_FMAC_INTERRUPT_REGISTER_2_TEST */ "", 30564 /* FMAC_FMAC_INTERRUPT_REGISTER_3_TEST */ "", 30565 /* FMAC_FMAC_INTERRUPT_REGISTER_4_TEST */ "", 30566 /* FMAC_FMAC_INTERRUPT_REGISTER_5_TEST */ "", 30567 /* FMAC_FMAC_INTERRUPT_REGISTER_6_TEST */ "", 30568 /* FMAC_FMAC_INTERRUPT_REGISTER_7_TEST */ "", 30569 /* FMAC_FMAC_INTERRUPT_REGISTER_8_TEST */ "", 30570 /* FMAC_FMAL_COMMA_BURST_CONFIGURATION */ "", 30571 /* FMAC_FMAL_GENERAL_CONFIGURATION */ "", 30572 /* FMAC_FMAL_RCI_GCI_WMK */ "", 30573 /* FMAC_FMAL_RX_GENERAL_CONFIGURATION */ "", 30574 /* FMAC_FMAL_STATISTICS_COUNT_CONTROL */ "", 30575 /* FMAC_FMAL_STATISTICS_GTIMER */ "", 30576 /* FMAC_FMAL_STATISTICS_OUTPUT */ "", 30577 /* FMAC_FMAL_STATISTICS_OUTPUT_CONTROL */ "", 30578 /* FMAC_FMAL_TX_COMMA_BURST_CONFIGURATION */ "", 30579 /* FMAC_FMAL_TX_CONTROL_BURST_CONFIGURATION */ "", 30580 /* FMAC_FMAL_TX_DC_AUTO_ADJUST */ "", 30581 /* FMAC_FMAL_TX_GENERAL_CONFIGURATION */ "", 30582 /* FMAC_FMAL_TX_SIMPLE_UNPACKING_CNT */ "", 30583 /* FMAC_FPS_CONFIGURATION_BER */ "", 30584 /* FMAC_FPS_CONFIGURATION_RX_SYNC */ "", 30585 /* FMAC_FPS_RX_FEC_CONFIGURATION */ "", 30586 /* FMAC_FPS_RX_STATUS */ "", 30587 /* FMAC_FPS_TX_CONFIGURATION */ "", 30588 /* FMAC_GENERAL_CONFIGURATION_REGISTER */ "", 30589 /* FMAC_GLOBAL_GENERAL_CFG_1 */ "", 30590 /* FMAC_GLOBAL_GENERAL_FE_CFG_1 */ "", 30591 /* FMAC_GLOBAL_MEM_OPTIONS */ "", 30592 /* FMAC_GLOBAL_TEST_RX_IDL_PTRN */ "", 30593 /* FMAC_GLOBAL_TEST_TX_IDL_PTRN */ "", 30594 /* FMAC_GLOBAL_TEST_TX_PR_SEED_A */ "", 30595 /* FMAC_GLOBAL_TEST_TX_PR_SEED_B */ "", 30596 /* FMAC_GRACEFULL_POWER_ON_OFF */ "", 30597 /* FMAC_GTIMER_CONFIGURATION */ "", 30598 /* FMAC_GTIMER_CYCLE */ "", 30599 /* FMAC_GTIMER_TRIGGER */ "", 30600 /* FMAC_INTERRUPT_MASK_REGISTER */ "", 30601 /* FMAC_INTERRUPT_MASK_REGISTER_1 */ "", 30602 /* FMAC_INTERRUPT_MASK_REGISTER_2 */ "", 30603 /* FMAC_INTERRUPT_MASK_REGISTER_3 */ "", 30604 /* FMAC_INTERRUPT_MASK_REGISTER_4 */ "", 30605 /* FMAC_INTERRUPT_MASK_REGISTER_5 */ "", 30606 /* FMAC_INTERRUPT_MASK_REGISTER_6 */ "", 30607 /* FMAC_INTERRUPT_MASK_REGISTER_7 */ "", 30608 /* FMAC_INTERRUPT_MASK_REGISTER_8 */ "", 30609 /* FMAC_INTERRUPT_MASK_REGISTER_9 */ "", 30610 /* FMAC_INTERRUPT_REGISTER */ "", 30611 /* FMAC_INTERRUPT_REGISTER_1 */ "", 30612 /* FMAC_INTERRUPT_REGISTER_2 */ "", 30613 /* FMAC_INTERRUPT_REGISTER_3 */ "", 30614 /* FMAC_INTERRUPT_REGISTER_4 */ "", 30615 /* FMAC_INTERRUPT_REGISTER_5 */ "", 30616 /* FMAC_INTERRUPT_REGISTER_6 */ "", 30617 /* FMAC_INTERRUPT_REGISTER_7 */ "", 30618 /* FMAC_INTERRUPT_REGISTER_8 */ "", 30619 /* FMAC_INTERRUPT_REGISTER_9 */ "", 30620 /* FMAC_INTERRUPT_REGISTER_1_TEST */ "", 30621 /* FMAC_INTERRUPT_REGISTER_2_TEST */ "", 30622 /* FMAC_INTERRUPT_REGISTER_3_TEST */ "", 30623 /* FMAC_INTERRUPT_REGISTER_4_TEST */ "", 30624 /* FMAC_INTERRUPT_REGISTER_5_TEST */ "", 30625 /* FMAC_INTERRUPT_REGISTER_6_TEST */ "", 30626 /* FMAC_INTERRUPT_REGISTER_7_TEST */ "", 30627 /* FMAC_INTERRUPT_REGISTER_8_TEST */ "", 30628 /* FMAC_INTERRUPT_REGISTER_9_TEST */ "", 30629 /* FMAC_INTERRUPT_REGISTER_TEST */ "", 30630 /* FMAC_KPCS_CONFIGURATION */ "", 30631 /* FMAC_KPCS_RX_STATUS */ "", 30632 /* FMAC_KPCS_TEST_RX_CONFIGURATION */ "", 30633 /* FMAC_KPCS_TEST_RX_STATUS */ "", 30634 /* FMAC_KPCS_TEST_TX_CONFIGURATION */ "", 30635 /* FMAC_LEAKY_BUCKET */ "", 30636 /* FMAC_LEAKY_BUCKET_CONTROL_REGISTER */ "", 30637 /* FMAC_LFEC_CONFIGURATION */ "", 30638 /* FMAC_LINK_LEVEL_FLOW_CONTROL_CONFIGURATION_REGISTER */ "", 30639 /* FMAC_LINK_LEVEL_FLOW_CONTROL_ENABLE_REGISTER */ "", 30640 /* FMAC_LINK_TOPO_MODE_REG_0 */ "", 30641 /* FMAC_LINK_TOPO_MODE_REG_2 */ "", 30642 /* FMAC_LOOPBACK_ENABLE_REGISTER */ "", 30643 /* FMAC_MACT_PM_CREDIT_FILTER */ "", 30644 /* FMAC_PARITY_ERR_CNT */ "", 30645 /* FMAC_PAR_ERR_INITIATE */ "", 30646 /* FMAC_PAR_ERR_MEM_MASK */ "", 30647 /* FMAC_RECEIVE_RESET_REGISTER */ "", 30648 /* FMAC_REG_0050 */ "", 30649 /* FMAC_REG_0051 */ "", 30650 /* FMAC_REG_0052 */ "", 30651 /* FMAC_REG_0053 */ "", 30652 /* FMAC_REG_0054 */ "", 30653 /* FMAC_REG_0058 */ "", 30654 /* FMAC_REG_0065 */ "", 30655 /* FMAC_REG_0066 */ "", 30656 /* FMAC_REG_0068 */ "", 30657 /* FMAC_REG_0096 */ "", 30658 /* FMAC_REG_0098 */ "", 30659 /* FMAC_REG_0099 */ "", 30660 /* FMAC_REG_0102 */ "", 30661 /* FMAC_REG_0114 */ "", 30662 /* FMAC_REG_0116 */ "", 30663 /* FMAC_REG_0118 */ "", 30664 /* FMAC_REG_0119 */ "", 30665 /* FMAC_REG_0121 */ "", 30666 /* FMAC_REG_0122 */ "", 30667 /* FMAC_REG_0123 */ "", 30668 /* FMAC_REG_0139 */ "", 30669 /* FMAC_REG_0140 */ "", 30670 /* FMAC_REG_0151 */ "", 30671 /* FMAC_REG_0166 */ "", 30672 /* FMAC_REG_005A */ "", 30673 /* FMAC_REG_005B */ "", 30674 /* FMAC_REG_005C */ "", 30675 /* FMAC_REG_00A0 */ "", 30676 /* FMAC_REG_00C2 */ "", 30677 /* FMAC_REG_00C3 */ "", 30678 /* FMAC_REG_00F4 */ "", 30679 /* FMAC_REG_011A */ "", 30680 /* FMAC_REG_011C */ "", 30681 /* FMAC_REG_011D */ "", 30682 /* FMAC_REG_012A */ "", 30683 /* FMAC_REG_012C */ "", 30684 /* FMAC_REG_012D */ "", 30685 /* FMAC_REG_01A8 */ "", 30686 /* FMAC_REG_01AC */ "", 30687 /* FMAC_REG_01E9 */ "", 30688 /* FMAC_REG_01EA */ "", 30689 /* FMAC_REG_01EB */ "", 30690 /* FMAC_REG_01EC */ "", 30691 /* FMAC_REG_01ED */ "", 30692 /* FMAC_REG_01EE */ "", 30693 /* FMAC_REG_01EF */ "", 30694 /* FMAC_REG_01FA */ "", 30695 /* FMAC_REG_1E8 */ "", 30696 /* FMAC_RESERVED_MIRROR_ADDR */ "", 30697 /* FMAC_RESERVED_MTCD */ "", 30698 /* FMAC_RESERVED_MTCP */ "", 30699 /* FMAC_RESERVED_SPARE_0 */ "", 30700 /* FMAC_RESERVED_SPARE_1 */ "", 30701 /* FMAC_RESERVED_SPARE_2 */ "", 30702 /* FMAC_RESERVED_SPARE_3 */ "", 30703 /* FMAC_RETIMER */ "", 30704 /* FMAC_RSF_CONFIGURATION */ "", 30705 /* FMAC_RSF_STATUS */ "", 30706 /* FMAC_RX_LANE_SWAP_0 */ "", 30707 /* FMAC_RX_LANE_SWAP_1 */ "", 30708 /* FMAC_RX_LANE_SWAP_2 */ "", 30709 /* FMAC_RX_LANE_SWAP_3 */ "", 30710 /* FMAC_RX_RRR_CRL_OVF_DROP_CNT */ "", 30711 /* FMAC_RX_RRR_DATA_LINKDOWN_DROP_CNT */ "", 30712 /* FMAC_SBUS_BROADCAST_ID */ "", 30713 /* FMAC_SBUS_LAST_IN_CHAIN */ "", 30714 /* FMAC_SPARE_REGISTER_2 */ "", 30715 /* FMAC_SPARE_REGISTER_3 */ "", 30716 /* FMAC_SPECIAL_CLOCK_CONTROLS */ "", 30717 /* FMAC_TEST_CONFIGURATION */ "", 30718 /* FMAC_TEST_STATUS */ "", 30719 /* FMAC_TX_CELL_LIMIT */ "", 30720 /* FMAC_TX_LANE_SWAP_0 */ "", 30721 /* FMAC_TX_LANE_SWAP_1 */ "", 30722 /* FMAC_TX_LANE_SWAP_2 */ "", 30723 /* FMAC_TX_LANE_SWAP_3 */ "", 30724 /* FORWARDING_1_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 30725 /* FORWARDING_1_KEY_GEN_CAM_BIST_STATUS */ "", 30726 /* FORWARDING_1_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 30727 /* FORWARDING_1_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 30728 /* FORWARDING_1_KEY_GEN_SER_CONTROL */ "", 30729 /* FORWARDING_1_KEY_GEN_TM_CONTROL_64 */ "", 30730 /* FORWARDING_2_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 30731 /* FORWARDING_2_KEY_GEN_CAM_BIST_STATUS */ "", 30732 /* FORWARDING_2_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 30733 /* FORWARDING_2_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 30734 /* FORWARDING_2_KEY_GEN_SER_CONTROL */ "", 30735 /* FORWARDING_2_KEY_GEN_TM_CONTROL_64 */ "", 30736 /* FORWARDING_3_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 30737 /* FORWARDING_3_KEY_GEN_CAM_BIST_STATUS */ "", 30738 /* FORWARDING_3_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 30739 /* FORWARDING_3_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 30740 /* FORWARDING_3_KEY_GEN_SER_CONTROL */ "", 30741 /* FORWARDING_3_KEY_GEN_TM_CONTROL_64 */ "", 30742 /* FPALCFG_CID_0 */ "", 30743 /* FPALCFG_CID_1 */ "", 30744 /* FPALCFG_CID_2 */ "", 30745 /* FPALCFG_CID_3 */ "", 30746 /* FPALCFG_CID_4 */ "", 30747 /* FPALCFG_CID_5 */ "", 30748 /* FPALCFG_CID_6 */ "", 30749 /* FPALCFG_CID_7 */ "", 30750 /* FPALCFG_CID_8 */ "", 30751 /* FPALCFG_CID_9 */ "", 30752 /* FPALCFG_CID_10 */ "", 30753 /* FPALCFG_CID_11 */ "", 30754 /* FPALCFG_CID_12 */ "", 30755 /* FPALCFG_CID_13 */ "", 30756 /* FPALCFG_CID_14 */ "", 30757 /* FPALCFG_CID_15 */ "", 30758 /* FPCFG_CID_0 */ "", 30759 /* FPCFG_CID_1 */ "", 30760 /* FPCFG_CID_2 */ "", 30761 /* FPCFG_CID_3 */ "", 30762 /* FPCFG_CID_4 */ "", 30763 /* FPCFG_CID_5 */ "", 30764 /* FPCFG_CID_6 */ "", 30765 /* FPCFG_CID_7 */ "", 30766 /* FPCFG_CID_8 */ "", 30767 /* FPCFG_CID_9 */ "", 30768 /* FPCFG_CID_10 */ "", 30769 /* FPCFG_CID_11 */ "", 30770 /* FPCFG_CID_12 */ "", 30771 /* FPCFG_CID_13 */ "", 30772 /* FPCFG_CID_14 */ "", 30773 /* FPCFG_CID_15 */ "", 30774 /* FPCRCEC_CID_0 */ "", 30775 /* FPCRCEC_CID_1 */ "", 30776 /* FPCRCEC_CID_2 */ "", 30777 /* FPCRCEC_CID_3 */ "", 30778 /* FPCRCEC_CID_4 */ "", 30779 /* FPCRCEC_CID_5 */ "", 30780 /* FPCRCEC_CID_6 */ "", 30781 /* FPCRCEC_CID_7 */ "", 30782 /* FPCRCEC_CID_8 */ "", 30783 /* FPCRCEC_CID_9 */ "", 30784 /* FPCRCEC_CID_10 */ "", 30785 /* FPCRCEC_CID_11 */ "", 30786 /* FPCRCEC_CID_12 */ "", 30787 /* FPCRCEC_CID_13 */ "", 30788 /* FPCRCEC_CID_14 */ "", 30789 /* FPCRCEC_CID_15 */ "", 30790 /* FPDLCFG_CID_0 */ "", 30791 /* FPDLCFG_CID_1 */ "", 30792 /* FPDLCFG_CID_2 */ "", 30793 /* FPDLCFG_CID_3 */ "", 30794 /* FPDLCFG_CID_4 */ "", 30795 /* FPDLCFG_CID_5 */ "", 30796 /* FPDLCFG_CID_6 */ "", 30797 /* FPDLCFG_CID_7 */ "", 30798 /* FPDLCFG_CID_8 */ "", 30799 /* FPDLCFG_CID_9 */ "", 30800 /* FPDLCFG_CID_10 */ "", 30801 /* FPDLCFG_CID_11 */ "", 30802 /* FPDLCFG_CID_12 */ "", 30803 /* FPDLCFG_CID_13 */ "", 30804 /* FPDLCFG_CID_14 */ "", 30805 /* FPDLCFG_CID_15 */ "", 30806 /* FPDLSTAT_CID_0 */ "", 30807 /* FPDLSTAT_CID_1 */ "", 30808 /* FPDLSTAT_CID_2 */ "", 30809 /* FPDLSTAT_CID_3 */ "", 30810 /* FPDLSTAT_CID_4 */ "", 30811 /* FPDLSTAT_CID_5 */ "", 30812 /* FPDLSTAT_CID_6 */ "", 30813 /* FPDLSTAT_CID_7 */ "", 30814 /* FPDLSTAT_CID_8 */ "", 30815 /* FPDLSTAT_CID_9 */ "", 30816 /* FPDLSTAT_CID_10 */ "", 30817 /* FPDLSTAT_CID_11 */ "", 30818 /* FPDLSTAT_CID_12 */ "", 30819 /* FPDLSTAT_CID_13 */ "", 30820 /* FPDLSTAT_CID_14 */ "", 30821 /* FPDLSTAT_CID_15 */ "", 30822 /* FPEBEC_CID_0 */ "", 30823 /* FPEBEC_CID_1 */ "", 30824 /* FPEBEC_CID_2 */ "", 30825 /* FPEBEC_CID_3 */ "", 30826 /* FPEBEC_CID_4 */ "", 30827 /* FPEBEC_CID_5 */ "", 30828 /* FPEBEC_CID_6 */ "", 30829 /* FPEBEC_CID_7 */ "", 30830 /* FPEBEC_CID_8 */ "", 30831 /* FPEBEC_CID_9 */ "", 30832 /* FPEBEC_CID_10 */ "", 30833 /* FPEBEC_CID_11 */ "", 30834 /* FPEBEC_CID_12 */ "", 30835 /* FPEBEC_CID_13 */ "", 30836 /* FPEBEC_CID_14 */ "", 30837 /* FPEBEC_CID_15 */ "", 30838 /* FPEM_CONTROL */ "", 30839 /* FPFAESLC_CID_0 */ "", 30840 /* FPFAESLC_CID_1 */ "", 30841 /* FPFAESLC_CID_2 */ "", 30842 /* FPFAESLC_CID_3 */ "", 30843 /* FPFAESLC_CID_4 */ "", 30844 /* FPFAESLC_CID_5 */ "", 30845 /* FPFAESLC_CID_6 */ "", 30846 /* FPFAESLC_CID_7 */ "", 30847 /* FPFAESLC_CID_8 */ "", 30848 /* FPFAESLC_CID_9 */ "", 30849 /* FPFAESLC_CID_10 */ "", 30850 /* FPFAESLC_CID_11 */ "", 30851 /* FPFAESLC_CID_12 */ "", 30852 /* FPFAESLC_CID_13 */ "", 30853 /* FPFAESLC_CID_14 */ "", 30854 /* FPFAESLC_CID_15 */ "", 30855 /* FPHDLCTL_CID_0 */ "", 30856 /* FPHDLCTL_CID_1 */ "", 30857 /* FPHDLCTL_CID_2 */ "", 30858 /* FPHDLCTL_CID_3 */ "", 30859 /* FPHDLCTL_CID_4 */ "", 30860 /* FPHDLCTL_CID_5 */ "", 30861 /* FPHDLCTL_CID_6 */ "", 30862 /* FPHDLCTL_CID_7 */ "", 30863 /* FPHDLCTL_CID_8 */ "", 30864 /* FPHDLCTL_CID_9 */ "", 30865 /* FPHDLCTL_CID_10 */ "", 30866 /* FPHDLCTL_CID_11 */ "", 30867 /* FPHDLCTL_CID_12 */ "", 30868 /* FPHDLCTL_CID_13 */ "", 30869 /* FPHDLCTL_CID_14 */ "", 30870 /* FPHDLCTL_CID_15 */ "", 30871 /* FPHDLRXD_CID_0 */ "", 30872 /* FPHDLRXD_CID_1 */ "", 30873 /* FPHDLRXD_CID_2 */ "", 30874 /* FPHDLRXD_CID_3 */ "", 30875 /* FPHDLRXD_CID_4 */ "", 30876 /* FPHDLRXD_CID_5 */ "", 30877 /* FPHDLRXD_CID_6 */ "", 30878 /* FPHDLRXD_CID_7 */ "", 30879 /* FPHDLRXD_CID_8 */ "", 30880 /* FPHDLRXD_CID_9 */ "", 30881 /* FPHDLRXD_CID_10 */ "", 30882 /* FPHDLRXD_CID_11 */ "", 30883 /* FPHDLRXD_CID_12 */ "", 30884 /* FPHDLRXD_CID_13 */ "", 30885 /* FPHDLRXD_CID_14 */ "", 30886 /* FPHDLRXD_CID_15 */ "", 30887 /* FPHDLTXD_CID_0 */ "", 30888 /* FPHDLTXD_CID_1 */ "", 30889 /* FPHDLTXD_CID_2 */ "", 30890 /* FPHDLTXD_CID_3 */ "", 30891 /* FPHDLTXD_CID_4 */ "", 30892 /* FPHDLTXD_CID_5 */ "", 30893 /* FPHDLTXD_CID_6 */ "", 30894 /* FPHDLTXD_CID_7 */ "", 30895 /* FPHDLTXD_CID_8 */ "", 30896 /* FPHDLTXD_CID_9 */ "", 30897 /* FPHDLTXD_CID_10 */ "", 30898 /* FPHDLTXD_CID_11 */ "", 30899 /* FPHDLTXD_CID_12 */ "", 30900 /* FPHDLTXD_CID_13 */ "", 30901 /* FPHDLTXD_CID_14 */ "", 30902 /* FPHDLTXD_CID_15 */ "", 30903 /* FPINTE1_CID_0 */ "", 30904 /* FPINTE1_CID_1 */ "", 30905 /* FPINTE1_CID_2 */ "", 30906 /* FPINTE1_CID_3 */ "", 30907 /* FPINTE1_CID_4 */ "", 30908 /* FPINTE1_CID_5 */ "", 30909 /* FPINTE1_CID_6 */ "", 30910 /* FPINTE1_CID_7 */ "", 30911 /* FPINTE1_CID_8 */ "", 30912 /* FPINTE1_CID_9 */ "", 30913 /* FPINTE1_CID_10 */ "", 30914 /* FPINTE1_CID_11 */ "", 30915 /* FPINTE1_CID_12 */ "", 30916 /* FPINTE1_CID_13 */ "", 30917 /* FPINTE1_CID_14 */ "", 30918 /* FPINTE1_CID_15 */ "", 30919 /* FPINTS1_CID_0 */ "", 30920 /* FPINTS1_CID_1 */ "", 30921 /* FPINTS1_CID_2 */ "", 30922 /* FPINTS1_CID_3 */ "", 30923 /* FPINTS1_CID_4 */ "", 30924 /* FPINTS1_CID_5 */ "", 30925 /* FPINTS1_CID_6 */ "", 30926 /* FPINTS1_CID_7 */ "", 30927 /* FPINTS1_CID_8 */ "", 30928 /* FPINTS1_CID_9 */ "", 30929 /* FPINTS1_CID_10 */ "", 30930 /* FPINTS1_CID_11 */ "", 30931 /* FPINTS1_CID_12 */ "", 30932 /* FPINTS1_CID_13 */ "", 30933 /* FPINTS1_CID_14 */ "", 30934 /* FPINTS1_CID_15 */ "", 30935 /* FPINTS2_CID_0 */ "", 30936 /* FPINTS2_CID_1 */ "", 30937 /* FPINTS2_CID_2 */ "", 30938 /* FPINTS2_CID_3 */ "", 30939 /* FPINTS2_CID_4 */ "", 30940 /* FPINTS2_CID_5 */ "", 30941 /* FPINTS2_CID_6 */ "", 30942 /* FPINTS2_CID_7 */ "", 30943 /* FPINTS2_CID_8 */ "", 30944 /* FPINTS2_CID_9 */ "", 30945 /* FPINTS2_CID_10 */ "", 30946 /* FPINTS2_CID_11 */ "", 30947 /* FPINTS2_CID_12 */ "", 30948 /* FPINTS2_CID_13 */ "", 30949 /* FPINTS2_CID_14 */ "", 30950 /* FPINTS2_CID_15 */ "", 30951 /* FPLCVEC_CID_0 */ "", 30952 /* FPLCVEC_CID_1 */ "", 30953 /* FPLCVEC_CID_2 */ "", 30954 /* FPLCVEC_CID_3 */ "", 30955 /* FPLCVEC_CID_4 */ "", 30956 /* FPLCVEC_CID_5 */ "", 30957 /* FPLCVEC_CID_6 */ "", 30958 /* FPLCVEC_CID_7 */ "", 30959 /* FPLCVEC_CID_8 */ "", 30960 /* FPLCVEC_CID_9 */ "", 30961 /* FPLCVEC_CID_10 */ "", 30962 /* FPLCVEC_CID_11 */ "", 30963 /* FPLCVEC_CID_12 */ "", 30964 /* FPLCVEC_CID_13 */ "", 30965 /* FPLCVEC_CID_14 */ "", 30966 /* FPLCVEC_CID_15 */ "", 30967 /* FPMTSLP_CID_0 */ "", 30968 /* FPMTSLP_CID_1 */ "", 30969 /* FPMTSLP_CID_2 */ "", 30970 /* FPMTSLP_CID_3 */ "", 30971 /* FPMTSLP_CID_4 */ "", 30972 /* FPMTSLP_CID_5 */ "", 30973 /* FPMTSLP_CID_6 */ "", 30974 /* FPMTSLP_CID_7 */ "", 30975 /* FPMTSLP_CID_8 */ "", 30976 /* FPMTSLP_CID_9 */ "", 30977 /* FPMTSLP_CID_10 */ "", 30978 /* FPMTSLP_CID_11 */ "", 30979 /* FPMTSLP_CID_12 */ "", 30980 /* FPMTSLP_CID_13 */ "", 30981 /* FPMTSLP_CID_14 */ "", 30982 /* FPMTSLP_CID_15 */ "", 30983 /* FPNINTE2_CID_0 */ "", 30984 /* FPNINTE2_CID_1 */ "", 30985 /* FPNINTE2_CID_2 */ "", 30986 /* FPNINTE2_CID_3 */ "", 30987 /* FPNINTE2_CID_4 */ "", 30988 /* FPNINTE2_CID_5 */ "", 30989 /* FPNINTE2_CID_6 */ "", 30990 /* FPNINTE2_CID_7 */ "", 30991 /* FPNINTE2_CID_8 */ "", 30992 /* FPNINTE2_CID_9 */ "", 30993 /* FPNINTE2_CID_10 */ "", 30994 /* FPNINTE2_CID_11 */ "", 30995 /* FPNINTE2_CID_12 */ "", 30996 /* FPNINTE2_CID_13 */ "", 30997 /* FPNINTE2_CID_14 */ "", 30998 /* FPNINTE2_CID_15 */ "", 30999 /* FPRBCFG1 */ "", 31000 /* FPRBCFG2 */ "", 31001 /* FPRHFD_CID_0 */ "", 31002 /* FPRHFD_CID_1 */ "", 31003 /* FPRHFD_CID_2 */ "", 31004 /* FPRHFD_CID_3 */ "", 31005 /* FPRHFD_CID_4 */ "", 31006 /* FPRHFD_CID_5 */ "", 31007 /* FPRHFD_CID_6 */ "", 31008 /* FPRHFD_CID_7 */ "", 31009 /* FPRHFD_CID_8 */ "", 31010 /* FPRHFD_CID_9 */ "", 31011 /* FPRHFD_CID_10 */ "", 31012 /* FPRHFD_CID_11 */ "", 31013 /* FPRHFD_CID_12 */ "", 31014 /* FPRHFD_CID_13 */ "", 31015 /* FPRHFD_CID_14 */ "", 31016 /* FPRHFD_CID_15 */ "", 31017 /* FPRSBRP_CID_0 */ "", 31018 /* FPRSBRP_CID_1 */ "", 31019 /* FPRSBRP_CID_2 */ "", 31020 /* FPRSBRP_CID_3 */ "", 31021 /* FPRSBRP_CID_4 */ "", 31022 /* FPRSBRP_CID_5 */ "", 31023 /* FPRSBRP_CID_6 */ "", 31024 /* FPRSBRP_CID_7 */ "", 31025 /* FPRSBRP_CID_8 */ "", 31026 /* FPRSBRP_CID_9 */ "", 31027 /* FPRSBRP_CID_10 */ "", 31028 /* FPRSBRP_CID_11 */ "", 31029 /* FPRSBRP_CID_12 */ "", 31030 /* FPRSBRP_CID_13 */ "", 31031 /* FPRSBRP_CID_14 */ "", 31032 /* FPRSBRP_CID_15 */ "", 31033 /* FPRSBWP_CID_0 */ "", 31034 /* FPRSBWP_CID_1 */ "", 31035 /* FPRSBWP_CID_2 */ "", 31036 /* FPRSBWP_CID_3 */ "", 31037 /* FPRSBWP_CID_4 */ "", 31038 /* FPRSBWP_CID_5 */ "", 31039 /* FPRSBWP_CID_6 */ "", 31040 /* FPRSBWP_CID_7 */ "", 31041 /* FPRSBWP_CID_8 */ "", 31042 /* FPRSBWP_CID_9 */ "", 31043 /* FPRSBWP_CID_10 */ "", 31044 /* FPRSBWP_CID_11 */ "", 31045 /* FPRSBWP_CID_12 */ "", 31046 /* FPRSBWP_CID_13 */ "", 31047 /* FPRSBWP_CID_14 */ "", 31048 /* FPRSBWP_CID_15 */ "", 31049 /* FPRSIG1_CID_0 */ "", 31050 /* FPRSIG1_CID_1 */ "", 31051 /* FPRSIG1_CID_2 */ "", 31052 /* FPRSIG1_CID_3 */ "", 31053 /* FPRSIG1_CID_4 */ "", 31054 /* FPRSIG1_CID_5 */ "", 31055 /* FPRSIG1_CID_6 */ "", 31056 /* FPRSIG1_CID_7 */ "", 31057 /* FPRSIG1_CID_8 */ "", 31058 /* FPRSIG1_CID_9 */ "", 31059 /* FPRSIG1_CID_10 */ "", 31060 /* FPRSIG1_CID_11 */ "", 31061 /* FPRSIG1_CID_12 */ "", 31062 /* FPRSIG1_CID_13 */ "", 31063 /* FPRSIG1_CID_14 */ "", 31064 /* FPRSIG1_CID_15 */ "", 31065 /* FPRSIG2_CID_0 */ "", 31066 /* FPRSIG2_CID_1 */ "", 31067 /* FPRSIG2_CID_2 */ "", 31068 /* FPRSIG2_CID_3 */ "", 31069 /* FPRSIG2_CID_4 */ "", 31070 /* FPRSIG2_CID_5 */ "", 31071 /* FPRSIG2_CID_6 */ "", 31072 /* FPRSIG2_CID_7 */ "", 31073 /* FPRSIG2_CID_8 */ "", 31074 /* FPRSIG2_CID_9 */ "", 31075 /* FPRSIG2_CID_10 */ "", 31076 /* FPRSIG2_CID_11 */ "", 31077 /* FPRSIG2_CID_12 */ "", 31078 /* FPRSIG2_CID_13 */ "", 31079 /* FPRSIG2_CID_14 */ "", 31080 /* FPRSIG2_CID_15 */ "", 31081 /* FPRSIG3_CID_0 */ "", 31082 /* FPRSIG3_CID_1 */ "", 31083 /* FPRSIG3_CID_2 */ "", 31084 /* FPRSIG3_CID_3 */ "", 31085 /* FPRSIG3_CID_4 */ "", 31086 /* FPRSIG3_CID_5 */ "", 31087 /* FPRSIG3_CID_6 */ "", 31088 /* FPRSIG3_CID_7 */ "", 31089 /* FPRSIG3_CID_8 */ "", 31090 /* FPRSIG3_CID_9 */ "", 31091 /* FPRSIG3_CID_10 */ "", 31092 /* FPRSIG3_CID_11 */ "", 31093 /* FPRSIG3_CID_12 */ "", 31094 /* FPRSIG3_CID_13 */ "", 31095 /* FPRSIG3_CID_14 */ "", 31096 /* FPRSIG3_CID_15 */ "", 31097 /* FPRSIG4_CID_0 */ "", 31098 /* FPRSIG4_CID_1 */ "", 31099 /* FPRSIG4_CID_2 */ "", 31100 /* FPRSIG4_CID_3 */ "", 31101 /* FPRSIG4_CID_4 */ "", 31102 /* FPRSIG4_CID_5 */ "", 31103 /* FPRSIG4_CID_6 */ "", 31104 /* FPRSIG4_CID_7 */ "", 31105 /* FPRSIG4_CID_8 */ "", 31106 /* FPRSIG4_CID_9 */ "", 31107 /* FPRSIG4_CID_10 */ "", 31108 /* FPRSIG4_CID_11 */ "", 31109 /* FPRSIG4_CID_12 */ "", 31110 /* FPRSIG4_CID_13 */ "", 31111 /* FPRSIG4_CID_14 */ "", 31112 /* FPRSIG4_CID_15 */ "", 31113 /* FPRSIG5_CID_0 */ "", 31114 /* FPRSIG5_CID_1 */ "", 31115 /* FPRSIG5_CID_2 */ "", 31116 /* FPRSIG5_CID_3 */ "", 31117 /* FPRSIG5_CID_4 */ "", 31118 /* FPRSIG5_CID_5 */ "", 31119 /* FPRSIG5_CID_6 */ "", 31120 /* FPRSIG5_CID_7 */ "", 31121 /* FPRSIG5_CID_8 */ "", 31122 /* FPRSIG5_CID_9 */ "", 31123 /* FPRSIG5_CID_10 */ "", 31124 /* FPRSIG5_CID_11 */ "", 31125 /* FPRSIG5_CID_12 */ "", 31126 /* FPRSIG5_CID_13 */ "", 31127 /* FPRSIG5_CID_14 */ "", 31128 /* FPRSIG5_CID_15 */ "", 31129 /* FPRSIG6_CID_0 */ "", 31130 /* FPRSIG6_CID_1 */ "", 31131 /* FPRSIG6_CID_2 */ "", 31132 /* FPRSIG6_CID_3 */ "", 31133 /* FPRSIG6_CID_4 */ "", 31134 /* FPRSIG6_CID_5 */ "", 31135 /* FPRSIG6_CID_6 */ "", 31136 /* FPRSIG6_CID_7 */ "", 31137 /* FPRSIG6_CID_8 */ "", 31138 /* FPRSIG6_CID_9 */ "", 31139 /* FPRSIG6_CID_10 */ "", 31140 /* FPRSIG6_CID_11 */ "", 31141 /* FPRSIG6_CID_12 */ "", 31142 /* FPRSIG6_CID_13 */ "", 31143 /* FPRSIG6_CID_14 */ "", 31144 /* FPRSIG6_CID_15 */ "", 31145 /* FPRSIG7_CID_0 */ "", 31146 /* FPRSIG7_CID_1 */ "", 31147 /* FPRSIG7_CID_2 */ "", 31148 /* FPRSIG7_CID_3 */ "", 31149 /* FPRSIG7_CID_4 */ "", 31150 /* FPRSIG7_CID_5 */ "", 31151 /* FPRSIG7_CID_6 */ "", 31152 /* FPRSIG7_CID_7 */ "", 31153 /* FPRSIG7_CID_8 */ "", 31154 /* FPRSIG7_CID_9 */ "", 31155 /* FPRSIG7_CID_10 */ "", 31156 /* FPRSIG7_CID_11 */ "", 31157 /* FPRSIG7_CID_12 */ "", 31158 /* FPRSIG7_CID_13 */ "", 31159 /* FPRSIG7_CID_14 */ "", 31160 /* FPRSIG7_CID_15 */ "", 31161 /* FPRSIG8_CID_0 */ "", 31162 /* FPRSIG8_CID_1 */ "", 31163 /* FPRSIG8_CID_2 */ "", 31164 /* FPRSIG8_CID_3 */ "", 31165 /* FPRSIG8_CID_4 */ "", 31166 /* FPRSIG8_CID_5 */ "", 31167 /* FPRSIG8_CID_6 */ "", 31168 /* FPRSIG8_CID_7 */ "", 31169 /* FPRSIG8_CID_8 */ "", 31170 /* FPRSIG8_CID_9 */ "", 31171 /* FPRSIG8_CID_10 */ "", 31172 /* FPRSIG8_CID_11 */ "", 31173 /* FPRSIG8_CID_12 */ "", 31174 /* FPRSIG8_CID_13 */ "", 31175 /* FPRSIG8_CID_14 */ "", 31176 /* FPRSIG8_CID_15 */ "", 31177 /* FPRXNB1_CID_0 */ "", 31178 /* FPRXNB1_CID_1 */ "", 31179 /* FPRXNB1_CID_2 */ "", 31180 /* FPRXNB1_CID_3 */ "", 31181 /* FPRXNB1_CID_4 */ "", 31182 /* FPRXNB1_CID_5 */ "", 31183 /* FPRXNB1_CID_6 */ "", 31184 /* FPRXNB1_CID_7 */ "", 31185 /* FPRXNB1_CID_8 */ "", 31186 /* FPRXNB1_CID_9 */ "", 31187 /* FPRXNB1_CID_10 */ "", 31188 /* FPRXNB1_CID_11 */ "", 31189 /* FPRXNB1_CID_12 */ "", 31190 /* FPRXNB1_CID_13 */ "", 31191 /* FPRXNB1_CID_14 */ "", 31192 /* FPRXNB1_CID_15 */ "", 31193 /* FPRXNB2_CID_0 */ "", 31194 /* FPRXNB2_CID_1 */ "", 31195 /* FPRXNB2_CID_2 */ "", 31196 /* FPRXNB2_CID_3 */ "", 31197 /* FPRXNB2_CID_4 */ "", 31198 /* FPRXNB2_CID_5 */ "", 31199 /* FPRXNB2_CID_6 */ "", 31200 /* FPRXNB2_CID_7 */ "", 31201 /* FPRXNB2_CID_8 */ "", 31202 /* FPRXNB2_CID_9 */ "", 31203 /* FPRXNB2_CID_10 */ "", 31204 /* FPRXNB2_CID_11 */ "", 31205 /* FPRXNB2_CID_12 */ "", 31206 /* FPRXNB2_CID_13 */ "", 31207 /* FPRXNB2_CID_14 */ "", 31208 /* FPRXNB2_CID_15 */ "", 31209 /* FPRXNB3_CID_0 */ "", 31210 /* FPRXNB3_CID_1 */ "", 31211 /* FPRXNB3_CID_2 */ "", 31212 /* FPRXNB3_CID_3 */ "", 31213 /* FPRXNB3_CID_4 */ "", 31214 /* FPRXNB3_CID_5 */ "", 31215 /* FPRXNB3_CID_6 */ "", 31216 /* FPRXNB3_CID_7 */ "", 31217 /* FPRXNB3_CID_8 */ "", 31218 /* FPRXNB3_CID_9 */ "", 31219 /* FPRXNB3_CID_10 */ "", 31220 /* FPRXNB3_CID_11 */ "", 31221 /* FPRXNB3_CID_12 */ "", 31222 /* FPRXNB3_CID_13 */ "", 31223 /* FPRXNB3_CID_14 */ "", 31224 /* FPRXNB3_CID_15 */ "", 31225 /* FPSEFC_CID_0 */ "", 31226 /* FPSEFC_CID_1 */ "", 31227 /* FPSEFC_CID_2 */ "", 31228 /* FPSEFC_CID_3 */ "", 31229 /* FPSEFC_CID_4 */ "", 31230 /* FPSEFC_CID_5 */ "", 31231 /* FPSEFC_CID_6 */ "", 31232 /* FPSEFC_CID_7 */ "", 31233 /* FPSEFC_CID_8 */ "", 31234 /* FPSEFC_CID_9 */ "", 31235 /* FPSEFC_CID_10 */ "", 31236 /* FPSEFC_CID_11 */ "", 31237 /* FPSEFC_CID_12 */ "", 31238 /* FPSEFC_CID_13 */ "", 31239 /* FPSEFC_CID_14 */ "", 31240 /* FPSEFC_CID_15 */ "", 31241 /* FPSTAT1_CID_0 */ "", 31242 /* FPSTAT1_CID_1 */ "", 31243 /* FPSTAT1_CID_2 */ "", 31244 /* FPSTAT1_CID_3 */ "", 31245 /* FPSTAT1_CID_4 */ "", 31246 /* FPSTAT1_CID_5 */ "", 31247 /* FPSTAT1_CID_6 */ "", 31248 /* FPSTAT1_CID_7 */ "", 31249 /* FPSTAT1_CID_8 */ "", 31250 /* FPSTAT1_CID_9 */ "", 31251 /* FPSTAT1_CID_10 */ "", 31252 /* FPSTAT1_CID_11 */ "", 31253 /* FPSTAT1_CID_12 */ "", 31254 /* FPSTAT1_CID_13 */ "", 31255 /* FPSTAT1_CID_14 */ "", 31256 /* FPSTAT1_CID_15 */ "", 31257 /* FPSTAT2_CID_0 */ "", 31258 /* FPSTAT2_CID_1 */ "", 31259 /* FPSTAT2_CID_2 */ "", 31260 /* FPSTAT2_CID_3 */ "", 31261 /* FPSTAT2_CID_4 */ "", 31262 /* FPSTAT2_CID_5 */ "", 31263 /* FPSTAT2_CID_6 */ "", 31264 /* FPSTAT2_CID_7 */ "", 31265 /* FPSTAT2_CID_8 */ "", 31266 /* FPSTAT2_CID_9 */ "", 31267 /* FPSTAT2_CID_10 */ "", 31268 /* FPSTAT2_CID_11 */ "", 31269 /* FPSTAT2_CID_12 */ "", 31270 /* FPSTAT2_CID_13 */ "", 31271 /* FPSTAT2_CID_14 */ "", 31272 /* FPSTAT2_CID_15 */ "", 31273 /* FPTSBRP_CID_0 */ "", 31274 /* FPTSBRP_CID_1 */ "", 31275 /* FPTSBRP_CID_2 */ "", 31276 /* FPTSBRP_CID_3 */ "", 31277 /* FPTSBRP_CID_4 */ "", 31278 /* FPTSBRP_CID_5 */ "", 31279 /* FPTSBRP_CID_6 */ "", 31280 /* FPTSBRP_CID_7 */ "", 31281 /* FPTSBRP_CID_8 */ "", 31282 /* FPTSBRP_CID_9 */ "", 31283 /* FPTSBRP_CID_10 */ "", 31284 /* FPTSBRP_CID_11 */ "", 31285 /* FPTSBRP_CID_12 */ "", 31286 /* FPTSBRP_CID_13 */ "", 31287 /* FPTSBRP_CID_14 */ "", 31288 /* FPTSBRP_CID_15 */ "", 31289 /* FPTSBWP_CID_0 */ "", 31290 /* FPTSBWP_CID_1 */ "", 31291 /* FPTSBWP_CID_2 */ "", 31292 /* FPTSBWP_CID_3 */ "", 31293 /* FPTSBWP_CID_4 */ "", 31294 /* FPTSBWP_CID_5 */ "", 31295 /* FPTSBWP_CID_6 */ "", 31296 /* FPTSBWP_CID_7 */ "", 31297 /* FPTSBWP_CID_8 */ "", 31298 /* FPTSBWP_CID_9 */ "", 31299 /* FPTSBWP_CID_10 */ "", 31300 /* FPTSBWP_CID_11 */ "", 31301 /* FPTSBWP_CID_12 */ "", 31302 /* FPTSBWP_CID_13 */ "", 31303 /* FPTSBWP_CID_14 */ "", 31304 /* FPTSBWP_CID_15 */ "", 31305 /* FPTSIG1_CID_0 */ "", 31306 /* FPTSIG1_CID_1 */ "", 31307 /* FPTSIG1_CID_2 */ "", 31308 /* FPTSIG1_CID_3 */ "", 31309 /* FPTSIG1_CID_4 */ "", 31310 /* FPTSIG1_CID_5 */ "", 31311 /* FPTSIG1_CID_6 */ "", 31312 /* FPTSIG1_CID_7 */ "", 31313 /* FPTSIG1_CID_8 */ "", 31314 /* FPTSIG1_CID_9 */ "", 31315 /* FPTSIG1_CID_10 */ "", 31316 /* FPTSIG1_CID_11 */ "", 31317 /* FPTSIG1_CID_12 */ "", 31318 /* FPTSIG1_CID_13 */ "", 31319 /* FPTSIG1_CID_14 */ "", 31320 /* FPTSIG1_CID_15 */ "", 31321 /* FPTSIG2_CID_0 */ "", 31322 /* FPTSIG2_CID_1 */ "", 31323 /* FPTSIG2_CID_2 */ "", 31324 /* FPTSIG2_CID_3 */ "", 31325 /* FPTSIG2_CID_4 */ "", 31326 /* FPTSIG2_CID_5 */ "", 31327 /* FPTSIG2_CID_6 */ "", 31328 /* FPTSIG2_CID_7 */ "", 31329 /* FPTSIG2_CID_8 */ "", 31330 /* FPTSIG2_CID_9 */ "", 31331 /* FPTSIG2_CID_10 */ "", 31332 /* FPTSIG2_CID_11 */ "", 31333 /* FPTSIG2_CID_12 */ "", 31334 /* FPTSIG2_CID_13 */ "", 31335 /* FPTSIG2_CID_14 */ "", 31336 /* FPTSIG2_CID_15 */ "", 31337 /* FPTSIG3_CID_0 */ "", 31338 /* FPTSIG3_CID_1 */ "", 31339 /* FPTSIG3_CID_2 */ "", 31340 /* FPTSIG3_CID_3 */ "", 31341 /* FPTSIG3_CID_4 */ "", 31342 /* FPTSIG3_CID_5 */ "", 31343 /* FPTSIG3_CID_6 */ "", 31344 /* FPTSIG3_CID_7 */ "", 31345 /* FPTSIG3_CID_8 */ "", 31346 /* FPTSIG3_CID_9 */ "", 31347 /* FPTSIG3_CID_10 */ "", 31348 /* FPTSIG3_CID_11 */ "", 31349 /* FPTSIG3_CID_12 */ "", 31350 /* FPTSIG3_CID_13 */ "", 31351 /* FPTSIG3_CID_14 */ "", 31352 /* FPTSIG3_CID_15 */ "", 31353 /* FPTSIG4_CID_0 */ "", 31354 /* FPTSIG4_CID_1 */ "", 31355 /* FPTSIG4_CID_2 */ "", 31356 /* FPTSIG4_CID_3 */ "", 31357 /* FPTSIG4_CID_4 */ "", 31358 /* FPTSIG4_CID_5 */ "", 31359 /* FPTSIG4_CID_6 */ "", 31360 /* FPTSIG4_CID_7 */ "", 31361 /* FPTSIG4_CID_8 */ "", 31362 /* FPTSIG4_CID_9 */ "", 31363 /* FPTSIG4_CID_10 */ "", 31364 /* FPTSIG4_CID_11 */ "", 31365 /* FPTSIG4_CID_12 */ "", 31366 /* FPTSIG4_CID_13 */ "", 31367 /* FPTSIG4_CID_14 */ "", 31368 /* FPTSIG4_CID_15 */ "", 31369 /* FPTSIG5_CID_0 */ "", 31370 /* FPTSIG5_CID_1 */ "", 31371 /* FPTSIG5_CID_2 */ "", 31372 /* FPTSIG5_CID_3 */ "", 31373 /* FPTSIG5_CID_4 */ "", 31374 /* FPTSIG5_CID_5 */ "", 31375 /* FPTSIG5_CID_6 */ "", 31376 /* FPTSIG5_CID_7 */ "", 31377 /* FPTSIG5_CID_8 */ "", 31378 /* FPTSIG5_CID_9 */ "", 31379 /* FPTSIG5_CID_10 */ "", 31380 /* FPTSIG5_CID_11 */ "", 31381 /* FPTSIG5_CID_12 */ "", 31382 /* FPTSIG5_CID_13 */ "", 31383 /* FPTSIG5_CID_14 */ "", 31384 /* FPTSIG5_CID_15 */ "", 31385 /* FPTSIG6_CID_0 */ "", 31386 /* FPTSIG6_CID_1 */ "", 31387 /* FPTSIG6_CID_2 */ "", 31388 /* FPTSIG6_CID_3 */ "", 31389 /* FPTSIG6_CID_4 */ "", 31390 /* FPTSIG6_CID_5 */ "", 31391 /* FPTSIG6_CID_6 */ "", 31392 /* FPTSIG6_CID_7 */ "", 31393 /* FPTSIG6_CID_8 */ "", 31394 /* FPTSIG6_CID_9 */ "", 31395 /* FPTSIG6_CID_10 */ "", 31396 /* FPTSIG6_CID_11 */ "", 31397 /* FPTSIG6_CID_12 */ "", 31398 /* FPTSIG6_CID_13 */ "", 31399 /* FPTSIG6_CID_14 */ "", 31400 /* FPTSIG6_CID_15 */ "", 31401 /* FPTSIG7_CID_0 */ "", 31402 /* FPTSIG7_CID_1 */ "", 31403 /* FPTSIG7_CID_2 */ "", 31404 /* FPTSIG7_CID_3 */ "", 31405 /* FPTSIG7_CID_4 */ "", 31406 /* FPTSIG7_CID_5 */ "", 31407 /* FPTSIG7_CID_6 */ "", 31408 /* FPTSIG7_CID_7 */ "", 31409 /* FPTSIG7_CID_8 */ "", 31410 /* FPTSIG7_CID_9 */ "", 31411 /* FPTSIG7_CID_10 */ "", 31412 /* FPTSIG7_CID_11 */ "", 31413 /* FPTSIG7_CID_12 */ "", 31414 /* FPTSIG7_CID_13 */ "", 31415 /* FPTSIG7_CID_14 */ "", 31416 /* FPTSIG7_CID_15 */ "", 31417 /* FPTSIG8_CID_0 */ "", 31418 /* FPTSIG8_CID_1 */ "", 31419 /* FPTSIG8_CID_2 */ "", 31420 /* FPTSIG8_CID_3 */ "", 31421 /* FPTSIG8_CID_4 */ "", 31422 /* FPTSIG8_CID_5 */ "", 31423 /* FPTSIG8_CID_6 */ "", 31424 /* FPTSIG8_CID_7 */ "", 31425 /* FPTSIG8_CID_8 */ "", 31426 /* FPTSIG8_CID_9 */ "", 31427 /* FPTSIG8_CID_10 */ "", 31428 /* FPTSIG8_CID_11 */ "", 31429 /* FPTSIG8_CID_12 */ "", 31430 /* FPTSIG8_CID_13 */ "", 31431 /* FPTSIG8_CID_14 */ "", 31432 /* FPTSIG8_CID_15 */ "", 31433 /* FPTSLB1_CID_0 */ "", 31434 /* FPTSLB1_CID_1 */ "", 31435 /* FPTSLB1_CID_2 */ "", 31436 /* FPTSLB1_CID_3 */ "", 31437 /* FPTSLB1_CID_4 */ "", 31438 /* FPTSLB1_CID_5 */ "", 31439 /* FPTSLB1_CID_6 */ "", 31440 /* FPTSLB1_CID_7 */ "", 31441 /* FPTSLB1_CID_8 */ "", 31442 /* FPTSLB1_CID_9 */ "", 31443 /* FPTSLB1_CID_10 */ "", 31444 /* FPTSLB1_CID_11 */ "", 31445 /* FPTSLB1_CID_12 */ "", 31446 /* FPTSLB1_CID_13 */ "", 31447 /* FPTSLB1_CID_14 */ "", 31448 /* FPTSLB1_CID_15 */ "", 31449 /* FPTSLB2_CID_0 */ "", 31450 /* FPTSLB2_CID_1 */ "", 31451 /* FPTSLB2_CID_2 */ "", 31452 /* FPTSLB2_CID_3 */ "", 31453 /* FPTSLB2_CID_4 */ "", 31454 /* FPTSLB2_CID_5 */ "", 31455 /* FPTSLB2_CID_6 */ "", 31456 /* FPTSLB2_CID_7 */ "", 31457 /* FPTSLB2_CID_8 */ "", 31458 /* FPTSLB2_CID_9 */ "", 31459 /* FPTSLB2_CID_10 */ "", 31460 /* FPTSLB2_CID_11 */ "", 31461 /* FPTSLB2_CID_12 */ "", 31462 /* FPTSLB2_CID_13 */ "", 31463 /* FPTSLB2_CID_14 */ "", 31464 /* FPTSLB2_CID_15 */ "", 31465 /* FPTXNB1_CID_0 */ "", 31466 /* FPTXNB1_CID_1 */ "", 31467 /* FPTXNB1_CID_2 */ "", 31468 /* FPTXNB1_CID_3 */ "", 31469 /* FPTXNB1_CID_4 */ "", 31470 /* FPTXNB1_CID_5 */ "", 31471 /* FPTXNB1_CID_6 */ "", 31472 /* FPTXNB1_CID_7 */ "", 31473 /* FPTXNB1_CID_8 */ "", 31474 /* FPTXNB1_CID_9 */ "", 31475 /* FPTXNB1_CID_10 */ "", 31476 /* FPTXNB1_CID_11 */ "", 31477 /* FPTXNB1_CID_12 */ "", 31478 /* FPTXNB1_CID_13 */ "", 31479 /* FPTXNB1_CID_14 */ "", 31480 /* FPTXNB1_CID_15 */ "", 31481 /* FPTXNB2_CID_0 */ "", 31482 /* FPTXNB2_CID_1 */ "", 31483 /* FPTXNB2_CID_2 */ "", 31484 /* FPTXNB2_CID_3 */ "", 31485 /* FPTXNB2_CID_4 */ "", 31486 /* FPTXNB2_CID_5 */ "", 31487 /* FPTXNB2_CID_6 */ "", 31488 /* FPTXNB2_CID_7 */ "", 31489 /* FPTXNB2_CID_8 */ "", 31490 /* FPTXNB2_CID_9 */ "", 31491 /* FPTXNB2_CID_10 */ "", 31492 /* FPTXNB2_CID_11 */ "", 31493 /* FPTXNB2_CID_12 */ "", 31494 /* FPTXNB2_CID_13 */ "", 31495 /* FPTXNB2_CID_14 */ "", 31496 /* FPTXNB2_CID_15 */ "", 31497 /* FPTXNB3_CID_0 */ "", 31498 /* FPTXNB3_CID_1 */ "", 31499 /* FPTXNB3_CID_2 */ "", 31500 /* FPTXNB3_CID_3 */ "", 31501 /* FPTXNB3_CID_4 */ "", 31502 /* FPTXNB3_CID_5 */ "", 31503 /* FPTXNB3_CID_6 */ "", 31504 /* FPTXNB3_CID_7 */ "", 31505 /* FPTXNB3_CID_8 */ "", 31506 /* FPTXNB3_CID_9 */ "", 31507 /* FPTXNB3_CID_10 */ "", 31508 /* FPTXNB3_CID_11 */ "", 31509 /* FPTXNB3_CID_12 */ "", 31510 /* FPTXNB3_CID_13 */ "", 31511 /* FPTXNB3_CID_14 */ "", 31512 /* FPTXNB3_CID_15 */ "", 31513 /* FP_BUS_PARITY_CONTROL */ "", 31514 /* FP_BUS_PARITY_ERROR */ "", 31515 /* FP_CAM_BIST_CONFIG */ "", 31516 /* FP_CAM_BIST_CONTROL */ "", 31517 /* FP_CAM_BIST_DBG_DATA */ "", 31518 /* FP_CAM_BIST_DBG_DATA_VALID */ "", 31519 /* FP_CAM_BIST_DEBUG_CONTROL */ "", 31520 /* FP_CAM_BIST_DEBUG_DATA */ "", 31521 /* FP_CAM_BIST_DEBUG_SEND */ "", 31522 /* FP_CAM_BIST_ENABLE */ "", 31523 /* FP_CAM_BIST_ENABLE_LOWER */ "", 31524 /* FP_CAM_BIST_ENABLE_ONE_TCAM */ "", 31525 /* FP_CAM_BIST_ENABLE_TWO_TCAM */ "", 31526 /* FP_CAM_BIST_ENABLE_UPPER */ "", 31527 /* FP_CAM_BIST_S10_STATUS */ "", 31528 /* FP_CAM_BIST_S12_STATUS */ "", 31529 /* FP_CAM_BIST_S14_STATUS */ "", 31530 /* FP_CAM_BIST_S15_STATUS */ "", 31531 /* FP_CAM_BIST_S2_STATUS */ "", 31532 /* FP_CAM_BIST_S3_STATUS */ "", 31533 /* FP_CAM_BIST_S5_STATUS */ "", 31534 /* FP_CAM_BIST_S6_STATUS */ "", 31535 /* FP_CAM_BIST_S8_STATUS */ "", 31536 /* FP_CAM_BIST_STATUS */ "", 31537 /* FP_CAM_CONTROL */ "", 31538 /* FP_CAM_CONTROL_15 */ "", 31539 /* FP_CAM_CONTROL_64 */ "FP_CAM_CONTROL", 31540 /* FP_CAM_CONTROL_0_SLICE_11_0 */ "", 31541 /* FP_CAM_CONTROL_0_SLICE_7_0 */ "", 31542 /* FP_CAM_CONTROL_14_THRU_10 */ "", 31543 /* FP_CAM_CONTROL_1_SLICE_11_0 */ "", 31544 /* FP_CAM_CONTROL_1_SLICE_7_0 */ "", 31545 /* FP_CAM_CONTROL_2_SLICE_11_0 */ "", 31546 /* FP_CAM_CONTROL_4_THRU_0 */ "", 31547 /* FP_CAM_CONTROL_9_THRU_5 */ "", 31548 /* FP_CAM_CONTROL_LOWER */ "", 31549 /* FP_CAM_CONTROL_SLICE_11_4 */ "", 31550 /* FP_CAM_CONTROL_SLICE_11_8 */ "", 31551 /* FP_CAM_CONTROL_SLICE_15_8 */ "", 31552 /* FP_CAM_CONTROL_SLICE_15_12 */ "", 31553 /* FP_CAM_CONTROL_SLICE_3_0 */ "", 31554 /* FP_CAM_CONTROL_SLICE_7_0 */ "", 31555 /* FP_CAM_CONTROL_SLICE_7_4 */ "", 31556 /* FP_CAM_CONTROL_SLICE_9_4 */ "", 31557 /* FP_CAM_CONTROL_TM_13_THRU_0 */ "", 31558 /* FP_CAM_CONTROL_TM_7_THRU_0 */ "", 31559 /* FP_CAM_CONTROL_UPPER */ "", 31560 /* FP_CAM_DEBUG_CONTROL */ "", 31561 /* FP_CAM_DEBUG_DATA */ "", 31562 /* FP_CAM_DEBUG_DATA_0 */ "", 31563 /* FP_CAM_DEBUG_DATA_1 */ "", 31564 /* FP_CAM_DEBUG_DATA_2 */ "", 31565 /* FP_CAM_DEBUG_DATA_3 */ "", 31566 /* FP_CAM_DEBUG_DATA_4 */ "", 31567 /* FP_CAM_DEBUG_DATA_5 */ "", 31568 /* FP_CAM_DEBUG_GLOBAL_MASK */ "", 31569 /* FP_CAM_DEBUG_SEND */ "", 31570 /* FP_CAM_ENABLE */ "", 31571 /* FP_COUNTER_PDA */ "", 31572 /* FP_COUNTER_RAM_INIT_DATA0 */ "", 31573 /* FP_COUNTER_RAM_INIT_DATA1 */ "", 31574 /* FP_COUNTER_TM_0 */ "", 31575 /* FP_COUNTER_TM_1 */ "", 31576 /* FP_COUNTER_TM_2 */ "", 31577 /* FP_COUNTER_TM_3 */ "", 31578 /* FP_COUNTER_TM_4 */ "", 31579 /* FP_COUNTER_TM_5 */ "", 31580 /* FP_COUNTER_TM_POOLS_0_3 */ "", 31581 /* FP_COUNTER_TM_POOLS_12_15 */ "", 31582 /* FP_COUNTER_TM_POOLS_4_7 */ "", 31583 /* FP_COUNTER_TM_POOLS_8_11 */ "", 31584 /* FP_DEBUG_CONTROL */ "", 31585 /* FP_DEBUG_EVENT */ "", 31586 /* FP_DEBUG_EVENT_MASK */ "", 31587 /* FP_DEBUG_STATUS_0 */ "", 31588 /* FP_DEBUG_STATUS_1 */ "", 31589 /* FP_DEBUG_STATUS_2 */ "", 31590 /* FP_DOS_ATTACK_LOOKUP_STATUS_VECTOR_SEL */ "", 31591 /* FP_DOUBLE_WIDE_F1_SELECT */ "", 31592 /* FP_DOUBLE_WIDE_F4_SELECT */ "", 31593 /* FP_DOUBLE_WIDE_SELECT */ "", 31594 /* FP_ECMP_HASH_CONTROL */ "", 31595 /* FP_F4_SELECT */ "", 31596 /* FP_FIELD_SEL_PARITY_CONTROL */ "", 31597 /* FP_FIELD_SEL_PARITY_STATUS_INTR */ "", 31598 /* FP_FIELD_SEL_PARITY_STATUS_NACK */ "", 31599 /* FP_FORCE_FORWARDING_FIELD */ "", 31600 /* FP_GLOBAL_MASK_CAM_CONTROL_0_SLICE_11_0 */ "", 31601 /* FP_GLOBAL_MASK_CAM_CONTROL_0_SLICE_7_0 */ "", 31602 /* FP_GLOBAL_MASK_CAM_CONTROL_1_SLICE_11_0 */ "", 31603 /* FP_GLOBAL_MASK_CAM_CONTROL_1_SLICE_7_0 */ "", 31604 /* FP_GLOBAL_MASK_CAM_CONTROL_2_SLICE_11_0 */ "", 31605 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_11_4 */ "", 31606 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_11_8 */ "", 31607 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_15_8 */ "", 31608 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_15_12 */ "", 31609 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_3_0 */ "", 31610 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_7_0 */ "", 31611 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_7_4 */ "", 31612 /* FP_GLOBAL_MASK_CAM_CONTROL_SLICE_9_4 */ "", 31613 /* FP_GM_TCAM_BLK_SEL */ "", 31614 /* FP_GM_TCAM_BLK_SEL0 */ "", 31615 /* FP_GM_TCAM_BLK_SEL1 */ "", 31616 /* FP_GM_TCAM_BLK_SEL2 */ "", 31617 /* FP_GM_TCAM_BLK_SEL3 */ "", 31618 /* FP_GM_TCAM_BLK_SEL4 */ "", 31619 /* FP_GM_TCAM_BLK_SEL5 */ "", 31620 /* FP_GM_TCAM_BLK_SEL6 */ "", 31621 /* FP_GM_TCAM_BLK_SEL7 */ "", 31622 /* FP_HGPRXY_AUX_HDR_BITMAP_PRIORITY_MASK */ "", 31623 /* FP_LOOKUP_ENABLE */ "", 31624 /* FP_LOWER_GM_TCAM_BLK_SEL */ "", 31625 /* FP_LOWER_TCAM_BLK_SEL */ "", 31626 /* FP_METER_CONTROL */ "", 31627 /* FP_METER_RAM_INIT_DATA0 */ "", 31628 /* FP_METER_RAM_INIT_DATA1 */ "", 31629 /* FP_METER_STBY */ "", 31630 /* FP_METER_TABLE_POOL0_TM */ "", 31631 /* FP_METER_TABLE_POOL1_TM */ "", 31632 /* FP_METER_TABLE_POOL2_TM */ "", 31633 /* FP_METER_TABLE_POOL3_TM */ "", 31634 /* FP_METER_TABLE_POOL4_TM */ "", 31635 /* FP_METER_TABLE_POOL5_TM */ "", 31636 /* FP_METER_TABLE_POOL6_TM */ "", 31637 /* FP_METER_TABLE_POOL7_TM */ "", 31638 /* FP_METER_TABLE_TM */ "", 31639 /* FP_METER_TM */ "", 31640 /* FP_METER_TM0 */ "", 31641 /* FP_METER_TM1 */ "", 31642 /* FP_METER_TM2 */ "", 31643 /* FP_METER_TM3 */ "", 31644 /* FP_METER_TM0_PIPE0 */ "", 31645 /* FP_METER_TM0_PIPE1 */ "", 31646 /* FP_METER_TM0_PIPE2 */ "", 31647 /* FP_METER_TM0_PIPE3 */ "", 31648 /* FP_METER_TM1_PIPE0 */ "", 31649 /* FP_METER_TM1_PIPE1 */ "", 31650 /* FP_METER_TM1_PIPE2 */ "", 31651 /* FP_METER_TM1_PIPE3 */ "", 31652 /* FP_METER_TM2_PIPE0 */ "", 31653 /* FP_METER_TM2_PIPE1 */ "", 31654 /* FP_METER_TM2_PIPE2 */ "", 31655 /* FP_METER_TM2_PIPE3 */ "", 31656 /* FP_METER_TM3_PIPE0 */ "", 31657 /* FP_METER_TM3_PIPE1 */ "", 31658 /* FP_METER_TM3_PIPE2 */ "", 31659 /* FP_METER_TM3_PIPE3 */ "", 31660 /* FP_METER_TM_0 */ "", 31661 /* FP_METER_TM_1 */ "", 31662 /* FP_METER_TM_2 */ "", 31663 /* FP_METER_TM_3 */ "", 31664 /* FP_METER_TM_4 */ "", 31665 /* FP_METER_TM_5 */ "", 31666 /* FP_METER_TM_6 */ "", 31667 /* FP_METER_TM_7 */ "", 31668 /* FP_METER_TM_8 */ "", 31669 /* FP_METER_TM_9 */ "", 31670 /* FP_METER_TM_10 */ "", 31671 /* FP_METER_TM_11 */ "", 31672 /* FP_METER_TM_CONTROL */ "", 31673 /* FP_METER_TM_LOWER */ "", 31674 /* FP_METER_TM_PIPE0 */ "", 31675 /* FP_METER_TM_PIPE1 */ "", 31676 /* FP_METER_TM_PIPE2 */ "", 31677 /* FP_METER_TM_PIPE3 */ "", 31678 /* FP_MTU_CHECK_1_TM_CONTROL */ "", 31679 /* FP_MTU_CHECK_2_TM_CONTROL */ "", 31680 /* FP_NON_ROTATED_CAM_CONTROL */ "", 31681 /* FP_PAYLOAD_TOS_FN_SEL */ "", 31682 /* FP_POLICY_CONTROL */ "", 31683 /* FP_POLICY_LP_CONTROL_UPPER */ "", 31684 /* FP_POLICY_LVM */ "", 31685 /* FP_POLICY_LVM_PIPE0 */ "", 31686 /* FP_POLICY_LVM_PIPE1 */ "", 31687 /* FP_POLICY_LVM_PIPE2 */ "", 31688 /* FP_POLICY_LVM_PIPE3 */ "", 31689 /* FP_POLICY_PARITY_CONTROL */ "", 31690 /* FP_POLICY_PARITY_STATUS */ "", 31691 /* FP_POLICY_PDA */ "", 31692 /* FP_POLICY_PDA_64 */ "FP_POLICY_PDA", 31693 /* FP_POLICY_PDA_64_PIPE0 */ "FP_POLICY_PDA_PIPE0", 31694 /* FP_POLICY_PDA_64_PIPE1 */ "FP_POLICY_PDA_PIPE1", 31695 /* FP_POLICY_PDA_64_PIPE2 */ "FP_POLICY_PDA_PIPE2", 31696 /* FP_POLICY_PDA_64_PIPE3 */ "FP_POLICY_PDA_PIPE3", 31697 /* FP_POLICY_PM */ "", 31698 /* FP_POLICY_RAM_INIT_DATA0 */ "", 31699 /* FP_POLICY_RAM_INIT_DATA1 */ "", 31700 /* FP_POLICY_RAM_INIT_DATA2 */ "", 31701 /* FP_POLICY_TABLE_TM_CONTROL */ "", 31702 /* FP_POLICY_TM */ "", 31703 /* FP_POLICY_TM0 */ "", 31704 /* FP_POLICY_TM1 */ "", 31705 /* FP_POLICY_TM2 */ "", 31706 /* FP_POLICY_TM3 */ "", 31707 /* FP_POLICY_TM_0 */ "", 31708 /* FP_POLICY_TM_1 */ "", 31709 /* FP_POLICY_TM_2 */ "", 31710 /* FP_POLICY_TM_3 */ "", 31711 /* FP_POLICY_TM_4 */ "", 31712 /* FP_POLICY_TM_5 */ "", 31713 /* FP_POLICY_TM_LOWER */ "", 31714 /* FP_POLICY_TM_PIPE0 */ "", 31715 /* FP_POLICY_TM_PIPE1 */ "", 31716 /* FP_POLICY_TM_PIPE2 */ "", 31717 /* FP_POLICY_TM_PIPE3 */ "", 31718 /* FP_POLICY_TM_SLICES_0_3 */ "", 31719 /* FP_POLICY_TM_SLICES_12_15 */ "", 31720 /* FP_POLICY_TM_SLICES_4_7 */ "", 31721 /* FP_POLICY_TM_SLICES_8_11 */ "", 31722 /* FP_POLICY_TM_UPPER */ "", 31723 /* FP_PORT_METER_MAP_PARITY_CONTROL */ "", 31724 /* FP_PORT_METER_MAP_TM */ "", 31725 /* FP_RAM_CONTROL_1 */ "", 31726 /* FP_RAM_CONTROL_64 */ "FP_RAM_CONTROL", 31727 /* FP_RAM_DBGCTRL */ "FP_RAM_CONTROL", 31728 /* FP_ROTATED_CAM_CONTROL */ "", 31729 /* FP_SLICE_CONFIG */ "", 31730 /* FP_SLICE_ENABLE */ "", 31731 /* FP_SLICE_INDEX_CONTROL */ "", 31732 /* FP_SLICE_METER_MAP_ENABLE */ "", 31733 /* FP_SR_RX_HISTORY_TABLE_TM_CONTROL */ "", 31734 /* FP_SR_RX_TABLE_TM_CONTROL */ "", 31735 /* FP_SR_TX_TM_CONTROL */ "", 31736 /* FP_STORM_RAM_INIT_DATA */ "", 31737 /* FP_STORM_TM_CONTROL */ "", 31738 /* FP_SVM_TM_CONTROL_1 */ "", 31739 /* FP_SVM_TM_CONTROL_2 */ "", 31740 /* FP_TCAM_BLK_SEL */ "", 31741 /* FP_TCAM_BLK_SEL0 */ "", 31742 /* FP_TCAM_BLK_SEL1 */ "", 31743 /* FP_TCAM_BLK_SEL2 */ "", 31744 /* FP_TCAM_BLK_SEL3 */ "", 31745 /* FP_TCAM_BLK_SEL4 */ "", 31746 /* FP_TCAM_BLK_SEL5 */ "", 31747 /* FP_TCAM_BLK_SEL6 */ "", 31748 /* FP_TCAM_BLK_SEL7 */ "", 31749 /* FP_TCAM_ECC_RAM_INIT_DATA */ "", 31750 /* FP_TM */ "", 31751 /* FP_TM_PIPE0 */ "", 31752 /* FP_TM_PIPE1 */ "", 31753 /* FP_TM_PIPE2 */ "", 31754 /* FP_TM_PIPE3 */ "", 31755 /* FP_TM_PIPE4 */ "", 31756 /* FP_TM_PIPE5 */ "", 31757 /* FP_TM_PIPE6 */ "", 31758 /* FP_TM_PIPE7 */ "", 31759 /* FP_UDF_PARITY_CONTROL */ "", 31760 /* FP_UDF_PARITY_STATUS_INTR */ "", 31761 /* FP_UDF_PARITY_STATUS_NACK */ "", 31762 /* FP_UPPER_GM_TCAM_BLK_SEL */ "", 31763 /* FP_UPPER_TCAM_BLK_SEL */ "", 31764 /* FQP_DEQ_COUNTERS_CONFIG */ "", 31765 /* FQP_DISABLE_EGRESS_OFP */ "", 31766 /* FQP_ECC_1B_ERR_CNT */ "", 31767 /* FQP_ECC_2B_ERR_CNT */ "", 31768 /* FQP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 31769 /* FQP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 31770 /* FQP_ECC_INTERRUPT_REGISTER */ "", 31771 /* FQP_ECC_INTERRUPT_REGISTER_MASK */ "", 31772 /* FQP_ECC_INTERRUPT_REGISTER_TEST */ "", 31773 /* FQP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 31774 /* FQP_ERROR_INITIATION_DATA */ "", 31775 /* FQP_FQP_2_PQP_BYTES_RDY */ "", 31776 /* FQP_FQP_2_PQP_PD_RDY */ "", 31777 /* FQP_FQP_BLOCK_INIT_STATUS */ "", 31778 /* FQP_FQP_BUBBLE_CONFIGURATION */ "", 31779 /* FQP_FQP_BUBBLE_TRIGGER */ "", 31780 /* FQP_FQP_BYTES_COUNTER */ "", 31781 /* FQP_FQP_CANCEL_CNT */ "", 31782 /* FQP_FQP_CONFIGURATION */ "", 31783 /* FQP_FQP_DEBUG_HALT_CONFIGURATION */ "", 31784 /* FQP_FQP_DYNAMIC_RATE_ALLOCATOR */ "", 31785 /* FQP_FQP_PACKETS_COUNTER */ "", 31786 /* FQP_FQP_SCHEDULER_CONFIGURATION */ "", 31787 /* FQP_FQP_SEGMENTS_COUNTER */ "", 31788 /* FQP_FQP_TXI_BLOCK_CNT */ "", 31789 /* FQP_FQP_TXI_BLOCK_CNT_CONFIGURATION */ "", 31790 /* FQP_FQP_TXQ_CONFIGURATION */ "", 31791 /* FQP_FRAGMENTATION_NOT_READY_INDICATION */ "", 31792 /* FQP_FRAGMENTATION_QUEUES_EMPTY_INDICATION */ "", 31793 /* FQP_GTIMER_CONFIGURATION */ "", 31794 /* FQP_GTIMER_CYCLE */ "", 31795 /* FQP_IFC_IS_WORK_CONSERVING */ "", 31796 /* FQP_INDIRECT_COMMAND */ "", 31797 /* FQP_INDIRECT_COMMAND_ADDRESS */ "", 31798 /* FQP_INDIRECT_COMMAND_RD_DATA */ "", 31799 /* FQP_INDIRECT_COMMAND_WR_DATA */ "", 31800 /* FQP_INDIRECT_FORCE_BUBBLE */ "", 31801 /* FQP_INIT_FQP_TXI */ "", 31802 /* FQP_INTERRUPT_MASK_REGISTER */ "", 31803 /* FQP_INTERRUPT_REGISTER */ "", 31804 /* FQP_INTERRUPT_REGISTER_TEST */ "", 31805 /* FQP_PCMI_0 */ "", 31806 /* FQP_PCMI_1 */ "", 31807 /* FQP_PCMI_2 */ "", 31808 /* FQP_PCMI_3 */ "", 31809 /* FQP_PCMI_4 */ "", 31810 /* FQP_PCMI_0_S */ "", 31811 /* FQP_PCMI_0_T */ "", 31812 /* FQP_PCMI_1_S */ "", 31813 /* FQP_PCMI_1_T */ "", 31814 /* FQP_PCMI_2_S */ "", 31815 /* FQP_PCMI_2_T */ "", 31816 /* FQP_PCMI_3_S */ "", 31817 /* FQP_PCMI_3_T */ "", 31818 /* FQP_PCMI_4_S */ "", 31819 /* FQP_PCMI_4_T */ "", 31820 /* FQP_PHANTOM_QS_CFG */ "", 31821 /* FQP_PQP_AND_FQP_CALENDER_SETTING */ "", 31822 /* FQP_REG_0041 */ "", 31823 /* FQP_REG_0098 */ "", 31824 /* FQP_REG_00A0 */ "", 31825 /* FQP_REG_00A4 */ "", 31826 /* FQP_REG_00A6 */ "", 31827 /* FQP_REG_00AA */ "", 31828 /* FQP_REG_00C2 */ "", 31829 /* FQP_REG_00C5 */ "", 31830 /* FQP_RESERVED_MIRROR_ADDR */ "", 31831 /* FQP_RESERVED_MTCD */ "", 31832 /* FQP_RESERVED_MTCP */ "", 31833 /* FQP_RESERVED_SPARE_0 */ "", 31834 /* FQP_RESERVED_SPARE_1 */ "", 31835 /* FQP_RESERVED_SPARE_2 */ "", 31836 /* FQP_RESERVED_SPARE_3 */ "", 31837 /* FQP_SBUS_BROADCAST_ID */ "", 31838 /* FQP_SBUS_LAST_IN_CHAIN */ "", 31839 /* FQP_SPECIAL_CLOCK_CONTROLS */ "", 31840 /* FQP_TXI_CREDITS_COUNTER */ "", 31841 /* FQP_TXI_OVER_FLOW_STATUS */ "", 31842 /* FQP_TXI_UNDER_FLOW_STATUS */ "", 31843 /* FQP_TXQ_WATERMARK */ "", 31844 /* FRAME_PAD_ENABLE */ "", 31845 /* FRAME_PAD_SIZE */ "", 31846 /* FRBINTE1 */ "", 31847 /* FRBINTE2 */ "", 31848 /* FRBINTS1 */ "", 31849 /* FRBINTS2 */ "", 31850 /* FRCFG1 */ "", 31851 /* FRCFG2 */ "", 31852 /* FREE_LIST_DEBUG_TM */ "", 31853 /* FRM_ECC_ADDR0 */ "", 31854 /* FRM_ECC_ADDR1 */ "", 31855 /* FRM_ECC_ADDR2 */ "", 31856 /* FRM_ECC_ADDR3 */ "", 31857 /* FRM_ECC_ADDR4 */ "", 31858 /* FRM_ECC_ADDR5 */ "", 31859 /* FRM_ECC_ADDR6 */ "", 31860 /* FRM_ECC_ADDR7 */ "", 31861 /* FRM_ECC_ADDR8 */ "", 31862 /* FRM_ECC_ADDR9 */ "", 31863 /* FRM_ECC_ADDR10 */ "", 31864 /* FRM_ECC_ADDR11 */ "", 31865 /* FRM_ECC_ADDR12 */ "", 31866 /* FRM_ECC_ADDR13 */ "", 31867 /* FRM_ECC_ADDR14 */ "", 31868 /* FRM_ECC_ADDR15 */ "", 31869 /* FRM_ECC_ADDR16 */ "", 31870 /* FRM_ECC_ADDR17 */ "", 31871 /* FRM_ECC_ADDR18 */ "", 31872 /* FRM_ECC_ADDR19 */ "", 31873 /* FRM_ECC_ADDR20 */ "", 31874 /* FRM_ECC_ADDR21 */ "", 31875 /* FRM_ECC_ADDR22 */ "", 31876 /* FRM_ECC_ADDR23 */ "", 31877 /* FRM_ECC_ADDR24 */ "", 31878 /* FRM_ECC_ADDR25 */ "", 31879 /* FRM_ECC_ADDR26 */ "", 31880 /* FRM_ECC_ADDR27 */ "", 31881 /* FRM_ECC_ADDR28 */ "", 31882 /* FRM_ECC_ADDR29 */ "", 31883 /* FRM_ECC_ADDR30 */ "", 31884 /* FRM_ECC_ADDR31 */ "", 31885 /* FRM_ECC_CONFIG0 */ "", 31886 /* FRM_ECC_CONFIG1 */ "", 31887 /* FRM_ECC_CONFIG2 */ "", 31888 /* FRM_ECC_CONFIG3 */ "", 31889 /* FRM_ECC_CONFIG4 */ "", 31890 /* FRM_ECC_CONFIG5 */ "", 31891 /* FRM_ECC_CONFIG6 */ "", 31892 /* FRM_ECC_CONFIG7 */ "", 31893 /* FRM_ECC_CONFIG8 */ "", 31894 /* FRM_ECC_CONFIG9 */ "", 31895 /* FRM_ECC_CONFIG10 */ "", 31896 /* FRM_ECC_CONFIG11 */ "", 31897 /* FRM_ECC_CONFIG12 */ "", 31898 /* FRM_ECC_CONFIG13 */ "", 31899 /* FRM_ECC_CONFIG14 */ "", 31900 /* FRM_ECC_CONFIG15 */ "", 31901 /* FRM_ECC_CONFIG16 */ "", 31902 /* FRM_ECC_CONFIG17 */ "", 31903 /* FRM_ECC_CONFIG18 */ "", 31904 /* FRM_ECC_CONFIG19 */ "", 31905 /* FRM_ECC_CONFIG20 */ "", 31906 /* FRM_ECC_CONFIG21 */ "", 31907 /* FRM_ECC_CONFIG22 */ "", 31908 /* FRM_ECC_CONFIG23 */ "", 31909 /* FRM_ECC_CONFIG24 */ "", 31910 /* FRM_ECC_CONFIG25 */ "", 31911 /* FRM_ECC_CONFIG26 */ "", 31912 /* FRM_ECC_CONFIG27 */ "", 31913 /* FRM_ECC_CONFIG28 */ "", 31914 /* FRM_ECC_CONFIG29 */ "", 31915 /* FRM_ECC_CONFIG30 */ "", 31916 /* FRM_ECC_CONFIG31 */ "", 31917 /* FRM_ECC_ERROR0 */ "", 31918 /* FRM_ECC_ERROR1 */ "", 31919 /* FRM_ECC_ERROR2 */ "", 31920 /* FRM_ECC_ERROR3 */ "", 31921 /* FRM_ECC_ERROR0_MASK */ "", 31922 /* FRM_ECC_ERROR1_MASK */ "", 31923 /* FRM_ECC_ERROR2_MASK */ "", 31924 /* FRM_ECC_ERROR3_MASK */ "", 31925 /* FRM_LENGTH */ "", 31926 /* FROM_REMOTE_CPU_DA0 */ "", 31927 /* FROM_REMOTE_CPU_DA1 */ "", 31928 /* FROM_REMOTE_CPU_ETHERTYPE */ "", 31929 /* FROM_REMOTE_CPU_SIGNATURE */ "", 31930 /* FRPRBPAT1 */ "", 31931 /* FRPRBPAT2 */ "", 31932 /* FRPRBSTAT1 */ "", 31933 /* FRPRBSTAT2 */ "", 31934 /* FRPRTSEL1_1 */ "", 31935 /* FRPRTSEL1_2 */ "", 31936 /* FRPRTSEL2_1 */ "", 31937 /* FRPRTSEL2_2 */ "", 31938 /* FSRD_AUTO_DOC_NAME_2 */ "", 31939 /* FSRD_ECC_1B_ERR_CNT */ "", 31940 /* FSRD_ECC_2B_ERR_CNT */ "", 31941 /* FSRD_ECC_ERR_1B_INITIATE */ "", 31942 /* FSRD_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 31943 /* FSRD_ECC_ERR_2B_INITIATE */ "", 31944 /* FSRD_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 31945 /* FSRD_ECC_INTERRUPT_REGISTER */ "", 31946 /* FSRD_ECC_INTERRUPT_REGISTER_MASK */ "", 31947 /* FSRD_ECC_INTERRUPT_REGISTER_TEST */ "", 31948 /* FSRD_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 31949 /* FSRD_ERROR_INITIATION_DATA */ "", 31950 /* FSRD_FSRD_REGISTER_0 */ "", 31951 /* FSRD_GENERAL_CONFIGURTION */ "", 31952 /* FSRD_GLOBAL_MEM_OPTIONS */ "", 31953 /* FSRD_GTIMER_CONFIGURATION */ "", 31954 /* FSRD_GTIMER_CYCLE */ "", 31955 /* FSRD_GTIMER_TRIGGER */ "", 31956 /* FSRD_INDIRECT_COMMAND */ "", 31957 /* FSRD_INDIRECT_COMMAND_ADDRESS */ "", 31958 /* FSRD_INDIRECT_COMMAND_DATA_INCREMENT */ "", 31959 /* FSRD_INDIRECT_COMMAND_RD_DATA */ "", 31960 /* FSRD_INDIRECT_COMMAND_WIDE_MEM */ "", 31961 /* FSRD_INDIRECT_COMMAND_WR_DATA */ "", 31962 /* FSRD_INDIRECT_FORCE_BUBBLE */ "", 31963 /* FSRD_INTERRUPT_MASK_REGISTER */ "", 31964 /* FSRD_INTERRUPT_REGISTER */ "", 31965 /* FSRD_INTERRUPT_REGISTER_TEST */ "", 31966 /* FSRD_OUTPUT_DROP_COUNTER */ "", 31967 /* FSRD_PCMI_0 */ "", 31968 /* FSRD_PCMI_1 */ "", 31969 /* FSRD_PCMI_2 */ "", 31970 /* FSRD_PCMI_3 */ "", 31971 /* FSRD_PCMI_4 */ "", 31972 /* FSRD_PCMI_0_S */ "", 31973 /* FSRD_PCMI_0_T */ "", 31974 /* FSRD_PCMI_1_S */ "", 31975 /* FSRD_PCMI_1_T */ "", 31976 /* FSRD_PCMI_2_S */ "", 31977 /* FSRD_PCMI_2_T */ "", 31978 /* FSRD_PCMI_3_S */ "", 31979 /* FSRD_PCMI_3_T */ "", 31980 /* FSRD_PCMI_4_S */ "", 31981 /* FSRD_PCMI_4_T */ "", 31982 /* FSRD_QUAD_INTERRUPT_MASK_REGISTER */ "", 31983 /* FSRD_QUAD_INTERRUPT_REGISTER */ "", 31984 /* FSRD_QUAD_INTERRUPT_REGISTER_TEST */ "", 31985 /* FSRD_REG_0041 */ "", 31986 /* FSRD_REG_0050 */ "", 31987 /* FSRD_REG_0051 */ "", 31988 /* FSRD_REG_0052 */ "", 31989 /* FSRD_REG_0053 */ "", 31990 /* FSRD_REG_0054 */ "", 31991 /* FSRD_REG_0058 */ "", 31992 /* FSRD_REG_0084 */ "", 31993 /* FSRD_REG_0087 */ "", 31994 /* FSRD_REG_0090 */ "", 31995 /* FSRD_REG_0091 */ "", 31996 /* FSRD_REG_0092 */ "", 31997 /* FSRD_REG_0094 */ "", 31998 /* FSRD_REG_0170 */ "", 31999 /* FSRD_REG_009A */ "", 32000 /* FSRD_REG_009C */ "", 32001 /* FSRD_REG_00B0 */ "", 32002 /* FSRD_REG_00B1 */ "", 32003 /* FSRD_REG_00B2 */ "", 32004 /* FSRD_REG_00B3 */ "", 32005 /* FSRD_REG_00B4 */ "", 32006 /* FSRD_REG_00B5 */ "", 32007 /* FSRD_REG_00B6 */ "", 32008 /* FSRD_REG_00B7 */ "", 32009 /* FSRD_REG_00C2 */ "", 32010 /* FSRD_REG_017B */ "", 32011 /* FSRD_REG_01E9 */ "", 32012 /* FSRD_REG_01EA */ "", 32013 /* FSRD_REG_01EB */ "", 32014 /* FSRD_REG_01EC */ "", 32015 /* FSRD_REG_01ED */ "", 32016 /* FSRD_REG_01EE */ "", 32017 /* FSRD_REG_01EF */ "", 32018 /* FSRD_REG_01F0 */ "", 32019 /* FSRD_REG_01F1 */ "", 32020 /* FSRD_REG_01F2 */ "", 32021 /* FSRD_REG_01F3 */ "", 32022 /* FSRD_REG_1E8 */ "", 32023 /* FSRD_RESERVED_MIRROR_ADDR */ "", 32024 /* FSRD_RESERVED_MTCD */ "", 32025 /* FSRD_RESERVED_MTCP */ "", 32026 /* FSRD_RESERVED_PCMI_0 */ "", 32027 /* FSRD_RESERVED_PCMI_1 */ "", 32028 /* FSRD_RESERVED_PCMI_2 */ "", 32029 /* FSRD_RESERVED_PCMI_4 */ "", 32030 /* FSRD_RESERVED_PCMI_0_S */ "", 32031 /* FSRD_RESERVED_PCMI_0_T */ "", 32032 /* FSRD_RESERVED_PCMI_1_S */ "", 32033 /* FSRD_RESERVED_PCMI_1_T */ "", 32034 /* FSRD_RESERVED_PCMI_2_S */ "", 32035 /* FSRD_RESERVED_PCMI_2_T */ "", 32036 /* FSRD_RESERVED_PCMI_4_S */ "", 32037 /* FSRD_RESERVED_PCMI_4_T */ "", 32038 /* FSRD_RESERVED_SPARE_0 */ "", 32039 /* FSRD_RESERVED_SPARE_1 */ "", 32040 /* FSRD_RESERVED_SPARE_2 */ "", 32041 /* FSRD_RESERVED_SPARE_3 */ "", 32042 /* FSRD_RES_CAL_CONFIG */ "", 32043 /* FSRD_RES_CAL_CPU_OVERRIDE_REGISTER */ "", 32044 /* FSRD_RES_CAL_STATUS */ "", 32045 /* FSRD_RES_CAL_STICKY_CONFIG */ "", 32046 /* FSRD_SBUS_BROADCAST_ID */ "", 32047 /* FSRD_SBUS_LAST_IN_CHAIN */ "", 32048 /* FSRD_SPARE_REGISTER_3 */ "", 32049 /* FSRD_SPECIAL_CLOCK_CONTROLS */ "", 32050 /* FSRD_SRD_CTRL */ "", 32051 /* FSRD_SRD_LN_MODE */ "", 32052 /* FSRD_SRD_LN_OSR */ "", 32053 /* FSRD_SRD_LN_PAM */ "", 32054 /* FSRD_SRD_PLL_0_CTRL */ "", 32055 /* FSRD_SRD_PLL_1_CTRL */ "", 32056 /* FSRD_SRD_QUAD_CTRL */ "", 32057 /* FSRD_SRD_QUAD_LN_FORCE_SPEED_STRAPS */ "", 32058 /* FSRD_SRD_QUAD_LN_STRAPS */ "", 32059 /* FSRD_SRD_QUAD_STATUS */ "", 32060 /* FSRD_SRD_STATUS */ "", 32061 /* FSRD_SYNC_E_SELECT */ "", 32062 /* FSRD_TX_ILKN_CREDIT */ "", 32063 /* FSRD_WC_UC_MEM_ACCESS */ "", 32064 /* FSRD_WC_UC_MEM_MASK_BITMAP */ "", 32065 /* FT_ACTION_INHIBITED */ "", 32066 /* FT_AGE_CONTROL */ "", 32067 /* FT_CMDWAIT_TIMEOUT */ "", 32068 /* FT_CNTR_FIFO_STATUS */ "FT_CNTR_FIFO_STATUS", 32069 /* FT_CNTR_RAM_CONTROL */ "", 32070 /* FT_CNTR_SER_CONTROL */ "", 32071 /* FT_CONFIG */ "", 32072 /* FT_CTR_POOL */ "", 32073 /* FT_CURRENT_TIME */ "", 32074 /* FT_EVENT_CONFIG */ "", 32075 /* FT_EXPORT_FIFO_COUNTER */ "", 32076 /* FT_EXPORT_FIFO_READ_PTR */ "", 32077 /* FT_EXPORT_FIFO_WRITE_PTR */ "", 32078 /* FT_FLOWS_CREATED */ "", 32079 /* FT_FLOWS_MISSED_TCP */ "", 32080 /* FT_FLOWS_MISSED_UDP */ "", 32081 /* FT_HASH_CONTROL */ "", 32082 /* FT_HOLDWAIT_TIMEOUT */ "", 32083 /* FT_IN_USE */ "", 32084 /* FT_L4_INVALID */ "", 32085 /* FT_L4_PORTS_EXCLUDED */ "", 32086 /* FT_NEW_TIMEOUT */ "", 32087 /* FT_NO_COMMAND */ "", 32088 /* FT_PDA_CONTROL */ "", 32089 /* FT_POLICY_TM */ "", 32090 /* FT_RAM_CONTROL */ "", 32091 /* FT_REFRESH_CFG */ "", 32092 /* FT_RESULT_DA_LS */ "", 32093 /* FT_RESULT_DA_MS */ "", 32094 /* FT_RESULT_EXT_PORT */ "", 32095 /* FT_RESULT_LENGTH_TYPE */ "", 32096 /* FT_SER_CONTROL */ "", 32097 /* FT_SYN_DATA */ "", 32098 /* FT_UPDATE_ERR */ "", 32099 /* FUNCTIONAL_REFRESH_EN */ "", 32100 /* FUSE_REGS_FP_TCAM0 */ "", 32101 /* FUSE_REGS_ING_L3_NEXT_HOP_0 */ "", 32102 /* FUSE_REGS_L2_ENTRY_0 */ "", 32103 /* FUSE_REGS_L2_ENTRY_1 */ "", 32104 /* FUSE_REGS_VLAN_MAC_0 */ "", 32105 /* GATE_CTRL_PERIOD */ "", 32106 /* GBLBKPSTATUS */ "", 32107 /* GBLLIMITRESETLIMIT */ "", 32108 /* GBLLIMITSETLIMIT */ "", 32109 /* GCPOL */ "", 32110 /* GCTRL */ "", 32111 /* GE0_EEE_CONFIG */ "", 32112 /* GE0_GBODE_CELL_CNT */ "", 32113 /* GE0_GBODE_CELL_REQ_CNT */ "", 32114 /* GE0_GBOD_OVRFLW */ "", 32115 /* GE0_MIN_FRAG_SIZE */ "", 32116 /* GE0_S3MII_SPEED_DEBUG */ "", 32117 /* GE10_GBODE_CELL_CNT */ "", 32118 /* GE10_GBODE_CELL_REQ_CNT */ "", 32119 /* GE10_GBOD_OVRFLW */ "", 32120 /* GE11_GBODE_CELL_CNT */ "", 32121 /* GE11_GBODE_CELL_REQ_CNT */ "", 32122 /* GE11_GBOD_OVRFLW */ "", 32123 /* GE1_EEE_CONFIG */ "", 32124 /* GE1_GBODE_CELL_CNT */ "", 32125 /* GE1_GBODE_CELL_REQ_CNT */ "", 32126 /* GE1_GBOD_OVRFLW */ "", 32127 /* GE1_MIN_FRAG_SIZE */ "", 32128 /* GE1_S3MII_SPEED_DEBUG */ "", 32129 /* GE2_EEE_CONFIG */ "", 32130 /* GE2_GBODE_CELL_CNT */ "", 32131 /* GE2_GBODE_CELL_REQ_CNT */ "", 32132 /* GE2_GBOD_OVRFLW */ "", 32133 /* GE2_MIN_FRAG_SIZE */ "", 32134 /* GE2_S3MII_SPEED_DEBUG */ "", 32135 /* GE3_EEE_CONFIG */ "", 32136 /* GE3_GBODE_CELL_CNT */ "", 32137 /* GE3_GBODE_CELL_REQ_CNT */ "", 32138 /* GE3_GBOD_OVRFLW */ "", 32139 /* GE3_MIN_FRAG_SIZE */ "", 32140 /* GE3_S3MII_SPEED_DEBUG */ "", 32141 /* GE4_EEE_CONFIG */ "", 32142 /* GE4_GBODE_CELL_CNT */ "", 32143 /* GE4_GBODE_CELL_REQ_CNT */ "", 32144 /* GE4_GBOD_OVRFLW */ "", 32145 /* GE4_MIN_FRAG_SIZE */ "", 32146 /* GE4_S3MII_SPEED_DEBUG */ "", 32147 /* GE5_EEE_CONFIG */ "", 32148 /* GE5_GBODE_CELL_CNT */ "", 32149 /* GE5_GBODE_CELL_REQ_CNT */ "", 32150 /* GE5_GBOD_OVRFLW */ "", 32151 /* GE5_MIN_FRAG_SIZE */ "", 32152 /* GE5_S3MII_SPEED_DEBUG */ "", 32153 /* GE6_EEE_CONFIG */ "", 32154 /* GE6_GBODE_CELL_CNT */ "", 32155 /* GE6_GBODE_CELL_REQ_CNT */ "", 32156 /* GE6_GBOD_OVRFLW */ "", 32157 /* GE6_MIN_FRAG_SIZE */ "", 32158 /* GE6_S3MII_SPEED_DEBUG */ "", 32159 /* GE7_EEE_CONFIG */ "", 32160 /* GE7_GBODE_CELL_CNT */ "", 32161 /* GE7_GBODE_CELL_REQ_CNT */ "", 32162 /* GE7_GBOD_OVRFLW */ "", 32163 /* GE7_MIN_FRAG_SIZE */ "", 32164 /* GE7_S3MII_SPEED_DEBUG */ "", 32165 /* GE8_GBODE_CELL_CNT */ "", 32166 /* GE8_GBODE_CELL_REQ_CNT */ "", 32167 /* GE8_GBOD_OVRFLW */ "", 32168 /* GE9_GBODE_CELL_CNT */ "", 32169 /* GE9_GBODE_CELL_REQ_CNT */ "", 32170 /* GE9_GBOD_OVRFLW */ "", 32171 /* GENEVE_CONTROL */ "", 32172 /* GENEVE_DEFAULT_NETWORK_SVP */ "", 32173 /* GE_EGR_PKT_DROP_CTL */ "", 32174 /* GE_GBODE_CELL_CNT */ "", 32175 /* GE_GBODE_CELL_REQ_CNT */ "", 32176 /* GE_GBOD_OVRFLW */ "", 32177 /* GE_PORT_CONFIG */ "", 32178 /* GINTE */ "", 32179 /* GINTS */ "", 32180 /* GLB_PKTBUF_CTL */ "", 32181 /* GLB_PKTBUF_STS */ "", 32182 /* GLOBAL_EMIRROR_DROP_COUNT_64 */ "GLOBAL_EMIRROR_DROP_COUNT", 32183 /* GLOBAL_HDRM_COUNT */ "", 32184 /* GLOBAL_HDRM_LIMIT */ "", 32185 /* GLOBAL_MPLS_RANGE_1_LOWER */ "", 32186 /* GLOBAL_MPLS_RANGE_1_UPPER */ "", 32187 /* GLOBAL_MPLS_RANGE_2_LOWER */ "", 32188 /* GLOBAL_MPLS_RANGE_2_UPPER */ "", 32189 /* GLOBAL_SHARED_FILL_STATE_CONFIG */ "", 32190 /* GLOBAL_SP_WRED_AVG_QSIZE */ "", 32191 /* GLOBAL_SP_WRED_CONFIG */ "", 32192 /* GLOBAL_WREDAVGQSIZE_CELL */ "", 32193 /* GLOBAL_WREDAVGQSIZE_PACKET */ "", 32194 /* GLOBAL_WREDCONFIG_CELL */ "", 32195 /* GLOBAL_WREDCONFIG_ECCP */ "", 32196 /* GLOBAL_WREDCONFIG_PACKET */ "", 32197 /* GLOBAL_WREDPARAM_CELL */ "", 32198 /* GLOBAL_WREDPARAM_END_CELL */ "", 32199 /* GLOBAL_WREDPARAM_NONTCP_CELL */ "", 32200 /* GLOBAL_WREDPARAM_NONTCP_PACKET */ "", 32201 /* GLOBAL_WREDPARAM_PACKET */ "", 32202 /* GLOBAL_WREDPARAM_PRI0_END_CELL */ "", 32203 /* GLOBAL_WREDPARAM_PRI0_START_CELL */ "", 32204 /* GLOBAL_WREDPARAM_RED_CELL */ "", 32205 /* GLOBAL_WREDPARAM_RED_END_CELL */ "", 32206 /* GLOBAL_WREDPARAM_RED_PACKET */ "", 32207 /* GLOBAL_WREDPARAM_RED_START_CELL */ "", 32208 /* GLOBAL_WREDPARAM_START_CELL */ "", 32209 /* GLOBAL_WREDPARAM_YELLOW_CELL */ "", 32210 /* GLOBAL_WREDPARAM_YELLOW_END_CELL */ "", 32211 /* GLOBAL_WREDPARAM_YELLOW_PACKET */ "", 32212 /* GLOBAL_WREDPARAM_YELLOW_START_CELL */ "", 32213 /* GLOBAL_WRED_AVG_QSIZE_BUFFERE */ "", 32214 /* GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL0 */ "GLOBAL_WRED_AVG_QSIZE_BUFFERE", 32215 /* GLOBAL_WRED_AVG_QSIZE_BUFFERE_POOL1 */ "", 32216 /* GLOBAL_WRED_AVG_QSIZE_BUFFERI */ "", 32217 /* GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE */ "", 32218 /* GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL0 */ "GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE", 32219 /* GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERE_POOL1 */ "", 32220 /* GLOBAL_WRED_AVG_QSIZE_FRACTION_BUFFERI */ "", 32221 /* GLOBAL_WRED_AVG_QSIZE_FRACTION_QENTRY */ "", 32222 /* GLOBAL_WRED_AVG_QSIZE_QENTRY */ "", 32223 /* GLOBAL_WRED_CONFIG_BUFFERE */ "", 32224 /* GLOBAL_WRED_CONFIG_BUFFERE_POOL0 */ "GLOBAL_WRED_CONFIG_BUFFERE", 32225 /* GLOBAL_WRED_CONFIG_BUFFERE_POOL1 */ "", 32226 /* GLOBAL_WRED_CONFIG_BUFFERI */ "", 32227 /* GLOBAL_WRED_CONFIG_QENTRY */ "", 32228 /* GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE */ "", 32229 /* GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL0 */ "GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE", 32230 /* GLOBAL_WRED_DROP_THD_NONTCP_BUFFERE_POOL1 */ "", 32231 /* GLOBAL_WRED_DROP_THD_NONTCP_BUFFERI */ "", 32232 /* GLOBAL_WRED_DROP_THD_NONTCP_QENTRY */ "", 32233 /* GLOBAL_WRED_DROP_THD_TCP_BUFFERE */ "", 32234 /* GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL0 */ "GLOBAL_WRED_DROP_THD_TCP_BUFFERE", 32235 /* GLOBAL_WRED_DROP_THD_TCP_BUFFERE_POOL1 */ "", 32236 /* GLOBAL_WRED_DROP_THD_TCP_BUFFERI */ "", 32237 /* GLOBAL_WRED_DROP_THD_TCP_QENTRY */ "", 32238 /* GLOBAL_WRED_THD_0_ECCP */ "", 32239 /* GLOBAL_WRED_THD_1_ECCP */ "", 32240 /* GMAC0_BISTSTATUS */ "", 32241 /* GMAC0_CKSUM_CONTROL */ "", 32242 /* GMAC0_CLOCKCONTROLSTATUS */ "", 32243 /* GMAC0_DEVCONTROL */ "", 32244 /* GMAC0_DEVSTATUS */ "", 32245 /* GMAC0_EEECONTROL */ "", 32246 /* GMAC0_EEERXDURATIONCOUNT */ "", 32247 /* GMAC0_EEERXEVENTCOUNT */ "", 32248 /* GMAC0_EEETXDURATIONCOUNT */ "", 32249 /* GMAC0_EEETXEVENTCOUNT */ "", 32250 /* GMAC0_FIFOACCESSADDR */ "", 32251 /* GMAC0_FIFOACCESSBYTE */ "", 32252 /* GMAC0_FIFOACCESSDATA */ "", 32253 /* GMAC0_FLOWCNTL_TH */ "", 32254 /* GMAC0_GMACIDLE_CNT_TH */ "", 32255 /* GMAC0_GPIOOUTPUTEN */ "", 32256 /* GMAC0_GPIOSELECT */ "", 32257 /* GMAC0_GPTIMER */ "", 32258 /* GMAC0_INTMASK */ "", 32259 /* GMAC0_INTRCVLAZY */ "", 32260 /* GMAC0_INTSTATUS */ "", 32261 /* GMAC0_MEMORYECCSTATUS */ "", 32262 /* GMAC0_PHYACCESS */ "", 32263 /* GMAC0_PHYCONTROL */ "", 32264 /* GMAC0_POWERCONTROL */ "", 32265 /* GMAC0_RCVADDR_HIGH */ "", 32266 /* GMAC0_RCVADDR_LOW */ "", 32267 /* GMAC0_RCVCONTROL */ "", 32268 /* GMAC0_RCVPTR */ "", 32269 /* GMAC0_RCVSTATUS0 */ "", 32270 /* GMAC0_RCVSTATUS1 */ "", 32271 /* GMAC0_RXPRSR_L3 */ "", 32272 /* GMAC0_RXPRSR_MAXLEN */ "", 32273 /* GMAC0_RXPRSR_VLAN */ "", 32274 /* GMAC0_RXQCONTROL */ "", 32275 /* GMAC0_RXSACHANGES */ "", 32276 /* GMAC0_RXUNICASTPKTS */ "", 32277 /* GMAC0_RX_64 */ "", 32278 /* GMAC0_RX_1024_1522 */ "", 32279 /* GMAC0_RX_128_255 */ "", 32280 /* GMAC0_RX_1523_2047 */ "", 32281 /* GMAC0_RX_2048_4095 */ "", 32282 /* GMAC0_RX_256_511 */ "", 32283 /* GMAC0_RX_4096_8191 */ "", 32284 /* GMAC0_RX_512_1023 */ "", 32285 /* GMAC0_RX_65_127 */ "", 32286 /* GMAC0_RX_8192_MAX */ "", 32287 /* GMAC0_RX_ALIGN */ "", 32288 /* GMAC0_RX_ALL_OCTETS_HI */ "", 32289 /* GMAC0_RX_ALL_OCTETS_LO */ "", 32290 /* GMAC0_RX_ALL_PKTS */ "", 32291 /* GMAC0_RX_BRDCAST */ "", 32292 /* GMAC0_RX_CNTRL */ "", 32293 /* GMAC0_RX_CRC */ "", 32294 /* GMAC0_RX_CRC_ALIGN */ "", 32295 /* GMAC0_RX_DROP */ "", 32296 /* GMAC0_RX_FRAG */ "", 32297 /* GMAC0_RX_GD_OCTETS_HI */ "", 32298 /* GMAC0_RX_GD_OCTETS_LO */ "", 32299 /* GMAC0_RX_GD_PKTS */ "", 32300 /* GMAC0_RX_JAB */ "", 32301 /* GMAC0_RX_MULT */ "", 32302 /* GMAC0_RX_OVR */ "", 32303 /* GMAC0_RX_PAUS */ "", 32304 /* GMAC0_RX_SYM */ "", 32305 /* GMAC0_RX_UND */ "", 32306 /* GMAC0_SERDESCONTROL */ "", 32307 /* GMAC0_SERDESSTATUS0 */ "", 32308 /* GMAC0_SERDESSTATUS1 */ "", 32309 /* GMAC0_TXARB_WRR_TH */ "", 32310 /* GMAC0_TXQCONTROL */ "", 32311 /* GMAC0_TXQOSQ0OCTET_HI */ "", 32312 /* GMAC0_TXQOSQ0OCTET_LO */ "", 32313 /* GMAC0_TXQOSQ0PKT */ "", 32314 /* GMAC0_TXQOSQ1OCTET_HI */ "", 32315 /* GMAC0_TXQOSQ1OCTET_LO */ "", 32316 /* GMAC0_TXQOSQ1PKT */ "", 32317 /* GMAC0_TXQOSQ2OCTET_HI */ "", 32318 /* GMAC0_TXQOSQ2OCTET_LO */ "", 32319 /* GMAC0_TXQOSQ2PKT */ "", 32320 /* GMAC0_TXQOSQ3OCTET_HI */ "", 32321 /* GMAC0_TXQOSQ3OCTET_LO */ "", 32322 /* GMAC0_TXQOSQ3PKT */ "", 32323 /* GMAC0_TXQRXQMEMORYCONTROL */ "", 32324 /* GMAC0_TXUNICASTPKT */ "", 32325 /* GMAC0_TX_64 */ "", 32326 /* GMAC0_TX_1024_1522 */ "", 32327 /* GMAC0_TX_128_255 */ "", 32328 /* GMAC0_TX_1523_2047 */ "", 32329 /* GMAC0_TX_1_COL */ "", 32330 /* GMAC0_TX_2048_4095 */ "", 32331 /* GMAC0_TX_256_511 */ "", 32332 /* GMAC0_TX_4096_8191 */ "", 32333 /* GMAC0_TX_512_1023 */ "", 32334 /* GMAC0_TX_65_127 */ "", 32335 /* GMAC0_TX_8192_MAX */ "", 32336 /* GMAC0_TX_ALL_OCTETS_HI */ "", 32337 /* GMAC0_TX_ALL_OCTETS_LO */ "", 32338 /* GMAC0_TX_ALL_PKTS */ "", 32339 /* GMAC0_TX_BRDCAST */ "", 32340 /* GMAC0_TX_COL */ "", 32341 /* GMAC0_TX_CRS */ "", 32342 /* GMAC0_TX_DEF */ "", 32343 /* GMAC0_TX_EX_COL */ "", 32344 /* GMAC0_TX_FRAG */ "", 32345 /* GMAC0_TX_GD_OCTETS_HI */ "", 32346 /* GMAC0_TX_GD_OCTETS_LO */ "", 32347 /* GMAC0_TX_GD_PKTS */ "", 32348 /* GMAC0_TX_JAB */ "", 32349 /* GMAC0_TX_LATE */ "", 32350 /* GMAC0_TX_MULT */ "", 32351 /* GMAC0_TX_M_COL */ "", 32352 /* GMAC0_TX_OVER */ "", 32353 /* GMAC0_TX_PAUS */ "", 32354 /* GMAC0_TX_UNDERRUN */ "", 32355 /* GMAC0_XMTADDR_HIGH_0 */ "", 32356 /* GMAC0_XMTADDR_HIGH_1 */ "", 32357 /* GMAC0_XMTADDR_HIGH_2 */ "", 32358 /* GMAC0_XMTADDR_HIGH_3 */ "", 32359 /* GMAC0_XMTADDR_LOW_0 */ "", 32360 /* GMAC0_XMTADDR_LOW_1 */ "", 32361 /* GMAC0_XMTADDR_LOW_2 */ "", 32362 /* GMAC0_XMTADDR_LOW_3 */ "", 32363 /* GMAC0_XMTCONTROL_0 */ "", 32364 /* GMAC0_XMTCONTROL_1 */ "", 32365 /* GMAC0_XMTCONTROL_2 */ "", 32366 /* GMAC0_XMTCONTROL_3 */ "", 32367 /* GMAC0_XMTPTR_0 */ "", 32368 /* GMAC0_XMTPTR_1 */ "", 32369 /* GMAC0_XMTPTR_2 */ "", 32370 /* GMAC0_XMTPTR_3 */ "", 32371 /* GMAC0_XMTSTATUS0_0 */ "", 32372 /* GMAC0_XMTSTATUS0_1 */ "", 32373 /* GMAC0_XMTSTATUS0_2 */ "", 32374 /* GMAC0_XMTSTATUS0_3 */ "", 32375 /* GMAC0_XMTSTATUS1_0 */ "", 32376 /* GMAC0_XMTSTATUS1_1 */ "", 32377 /* GMAC0_XMTSTATUS1_2 */ "", 32378 /* GMAC0_XMTSTATUS1_3 */ "", 32379 /* GMAC1_BISTSTATUS */ "", 32380 /* GMAC1_CKSUM_CONTROL */ "", 32381 /* GMAC1_CLOCKCONTROLSTATUS */ "", 32382 /* GMAC1_DEVCONTROL */ "", 32383 /* GMAC1_DEVSTATUS */ "", 32384 /* GMAC1_EEECONTROL */ "", 32385 /* GMAC1_EEERXDURATIONCOUNT */ "", 32386 /* GMAC1_EEERXEVENTCOUNT */ "", 32387 /* GMAC1_EEETXDURATIONCOUNT */ "", 32388 /* GMAC1_EEETXEVENTCOUNT */ "", 32389 /* GMAC1_FIFOACCESSADDR */ "", 32390 /* GMAC1_FIFOACCESSBYTE */ "", 32391 /* GMAC1_FIFOACCESSDATA */ "", 32392 /* GMAC1_FLOWCNTL_TH */ "", 32393 /* GMAC1_GMACIDLE_CNT_TH */ "", 32394 /* GMAC1_GPIOOUTPUTEN */ "", 32395 /* GMAC1_GPIOSELECT */ "", 32396 /* GMAC1_GPTIMER */ "", 32397 /* GMAC1_INTMASK */ "", 32398 /* GMAC1_INTRCVLAZY */ "", 32399 /* GMAC1_INTSTATUS */ "", 32400 /* GMAC1_MEMORYECCSTATUS */ "", 32401 /* GMAC1_PHYACCESS */ "", 32402 /* GMAC1_PHYCONTROL */ "", 32403 /* GMAC1_POWERCONTROL */ "", 32404 /* GMAC1_RCVADDR_HIGH */ "", 32405 /* GMAC1_RCVADDR_LOW */ "", 32406 /* GMAC1_RCVCONTROL */ "", 32407 /* GMAC1_RCVPTR */ "", 32408 /* GMAC1_RCVSTATUS0 */ "", 32409 /* GMAC1_RCVSTATUS1 */ "", 32410 /* GMAC1_RXPRSR_L3 */ "", 32411 /* GMAC1_RXPRSR_MAXLEN */ "", 32412 /* GMAC1_RXPRSR_VLAN */ "", 32413 /* GMAC1_RXQCONTROL */ "", 32414 /* GMAC1_RXSACHANGES */ "", 32415 /* GMAC1_RXUNICASTPKTS */ "", 32416 /* GMAC1_RX_64 */ "", 32417 /* GMAC1_RX_1024_1522 */ "", 32418 /* GMAC1_RX_128_255 */ "", 32419 /* GMAC1_RX_1523_2047 */ "", 32420 /* GMAC1_RX_2048_4095 */ "", 32421 /* GMAC1_RX_256_511 */ "", 32422 /* GMAC1_RX_4096_8191 */ "", 32423 /* GMAC1_RX_512_1023 */ "", 32424 /* GMAC1_RX_65_127 */ "", 32425 /* GMAC1_RX_8192_MAX */ "", 32426 /* GMAC1_RX_ALIGN */ "", 32427 /* GMAC1_RX_ALL_OCTETS_HI */ "", 32428 /* GMAC1_RX_ALL_OCTETS_LO */ "", 32429 /* GMAC1_RX_ALL_PKTS */ "", 32430 /* GMAC1_RX_BRDCAST */ "", 32431 /* GMAC1_RX_CNTRL */ "", 32432 /* GMAC1_RX_CRC */ "", 32433 /* GMAC1_RX_CRC_ALIGN */ "", 32434 /* GMAC1_RX_DROP */ "", 32435 /* GMAC1_RX_FRAG */ "", 32436 /* GMAC1_RX_GD_OCTETS_HI */ "", 32437 /* GMAC1_RX_GD_OCTETS_LO */ "", 32438 /* GMAC1_RX_GD_PKTS */ "", 32439 /* GMAC1_RX_JAB */ "", 32440 /* GMAC1_RX_MULT */ "", 32441 /* GMAC1_RX_OVR */ "", 32442 /* GMAC1_RX_PAUS */ "", 32443 /* GMAC1_RX_SYM */ "", 32444 /* GMAC1_RX_UND */ "", 32445 /* GMAC1_SERDESCONTROL */ "", 32446 /* GMAC1_SERDESSTATUS0 */ "", 32447 /* GMAC1_SERDESSTATUS1 */ "", 32448 /* GMAC1_TXARB_WRR_TH */ "", 32449 /* GMAC1_TXQCONTROL */ "", 32450 /* GMAC1_TXQOSQ0OCTET_HI */ "", 32451 /* GMAC1_TXQOSQ0OCTET_LO */ "", 32452 /* GMAC1_TXQOSQ0PKT */ "", 32453 /* GMAC1_TXQOSQ1OCTET_HI */ "", 32454 /* GMAC1_TXQOSQ1OCTET_LO */ "", 32455 /* GMAC1_TXQOSQ1PKT */ "", 32456 /* GMAC1_TXQOSQ2OCTET_HI */ "", 32457 /* GMAC1_TXQOSQ2OCTET_LO */ "", 32458 /* GMAC1_TXQOSQ2PKT */ "", 32459 /* GMAC1_TXQOSQ3OCTET_HI */ "", 32460 /* GMAC1_TXQOSQ3OCTET_LO */ "", 32461 /* GMAC1_TXQOSQ3PKT */ "", 32462 /* GMAC1_TXQRXQMEMORYCONTROL */ "", 32463 /* GMAC1_TXUNICASTPKT */ "", 32464 /* GMAC1_TX_64 */ "", 32465 /* GMAC1_TX_1024_1522 */ "", 32466 /* GMAC1_TX_128_255 */ "", 32467 /* GMAC1_TX_1523_2047 */ "", 32468 /* GMAC1_TX_1_COL */ "", 32469 /* GMAC1_TX_2048_4095 */ "", 32470 /* GMAC1_TX_256_511 */ "", 32471 /* GMAC1_TX_4096_8191 */ "", 32472 /* GMAC1_TX_512_1023 */ "", 32473 /* GMAC1_TX_65_127 */ "", 32474 /* GMAC1_TX_8192_MAX */ "", 32475 /* GMAC1_TX_ALL_OCTETS_HI */ "", 32476 /* GMAC1_TX_ALL_OCTETS_LO */ "", 32477 /* GMAC1_TX_ALL_PKTS */ "", 32478 /* GMAC1_TX_BRDCAST */ "", 32479 /* GMAC1_TX_COL */ "", 32480 /* GMAC1_TX_CRS */ "", 32481 /* GMAC1_TX_DEF */ "", 32482 /* GMAC1_TX_EX_COL */ "", 32483 /* GMAC1_TX_FRAG */ "", 32484 /* GMAC1_TX_GD_OCTETS_HI */ "", 32485 /* GMAC1_TX_GD_OCTETS_LO */ "", 32486 /* GMAC1_TX_GD_PKTS */ "", 32487 /* GMAC1_TX_JAB */ "", 32488 /* GMAC1_TX_LATE */ "", 32489 /* GMAC1_TX_MULT */ "", 32490 /* GMAC1_TX_M_COL */ "", 32491 /* GMAC1_TX_OVER */ "", 32492 /* GMAC1_TX_PAUS */ "", 32493 /* GMAC1_TX_UNDERRUN */ "", 32494 /* GMAC1_XMTADDR_HIGH_0 */ "", 32495 /* GMAC1_XMTADDR_HIGH_1 */ "", 32496 /* GMAC1_XMTADDR_HIGH_2 */ "", 32497 /* GMAC1_XMTADDR_HIGH_3 */ "", 32498 /* GMAC1_XMTADDR_LOW_0 */ "", 32499 /* GMAC1_XMTADDR_LOW_1 */ "", 32500 /* GMAC1_XMTADDR_LOW_2 */ "", 32501 /* GMAC1_XMTADDR_LOW_3 */ "", 32502 /* GMAC1_XMTCONTROL_0 */ "", 32503 /* GMAC1_XMTCONTROL_1 */ "", 32504 /* GMAC1_XMTCONTROL_2 */ "", 32505 /* GMAC1_XMTCONTROL_3 */ "", 32506 /* GMAC1_XMTPTR_0 */ "", 32507 /* GMAC1_XMTPTR_1 */ "", 32508 /* GMAC1_XMTPTR_2 */ "", 32509 /* GMAC1_XMTPTR_3 */ "", 32510 /* GMAC1_XMTSTATUS0_0 */ "", 32511 /* GMAC1_XMTSTATUS0_1 */ "", 32512 /* GMAC1_XMTSTATUS0_2 */ "", 32513 /* GMAC1_XMTSTATUS0_3 */ "", 32514 /* GMAC1_XMTSTATUS1_0 */ "", 32515 /* GMAC1_XMTSTATUS1_1 */ "", 32516 /* GMAC1_XMTSTATUS1_2 */ "", 32517 /* GMAC1_XMTSTATUS1_3 */ "", 32518 /* GMACC0 */ "", 32519 /* GMACC1 */ "", 32520 /* GMACC2 */ "", 32521 /* GMHIGHBANK */ "", 32522 /* GMII_EEE_DELAY_ENTRY_TIMER */ "", 32523 /* GMII_EEE_WAKE_TIMER */ "", 32524 /* GMLOWBANK */ "", 32525 /* GMMEMWARMUP */ "", 32526 /* GPCSC */ "", 32527 /* GPE_CONTROL */ "", 32528 /* GPE_DEFAULT_NETWORK_SVP */ "", 32529 /* GPE_GENEVE_IPV6_CONTROL */ "", 32530 /* GPE_NEXT_PROTOCOL */ "", 32531 /* GPORT_CNTMAXSIZE */ "", 32532 /* GPORT_CONFIG */ "", 32533 /* GPORT_DROP_ON_WRONG_SOP_S0_CNT */ "", 32534 /* GPORT_DROP_ON_WRONG_SOP_S1_CNT */ "", 32535 /* GPORT_DROP_ON_WRONG_SOP_S3_CNT */ "", 32536 /* GPORT_DROP_ON_WRONG_SOP_S4_CNT */ "", 32537 /* GPORT_ECC_CONTROL */ "", 32538 /* GPORT_EHG_RX_DATA_PARITY_STATUS_INTR */ "", 32539 /* GPORT_EHG_RX_DATA_PARITY_STATUS_NACK */ "", 32540 /* GPORT_EHG_RX_MASK_PARITY_STATUS_INTR */ "", 32541 /* GPORT_EHG_RX_MASK_PARITY_STATUS_NACK */ "", 32542 /* GPORT_EHG_TX_DATA_PARITY_STATUS_INTR */ "", 32543 /* GPORT_EHG_TX_DATA_PARITY_STATUS_NACK */ "", 32544 /* GPORT_EXTRA_SERDES_CTL */ "", 32545 /* GPORT_FORCE_DOUBLE_BIT_ERROR */ "", 32546 /* GPORT_FORCE_SINGLE_BIT_ERROR */ "", 32547 /* GPORT_GBODE_TXFIFO_PARITY_STATUS_INTR */ "", 32548 /* GPORT_GBOD_RXFIFO_PARITY_STATUS_INTR */ "", 32549 /* GPORT_INTR_ENABLE */ "", 32550 /* GPORT_INTR_STATUS */ "", 32551 /* GPORT_LINK_STATUS_TO_CMIC */ "", 32552 /* GPORT_MAC_CRS_SEL */ "", 32553 /* GPORT_MODE_REG */ "", 32554 /* GPORT_PARITY_CONTROL */ "", 32555 /* GPORT_RSV_MASK */ "", 32556 /* GPORT_RX_EEE_LPI_DURATION_COUNTER */ "", 32557 /* GPORT_RX_EEE_LPI_EVENT_COUNTER */ "", 32558 /* GPORT_SERDES_CTL */ "", 32559 /* GPORT_SGMII0_CTRL_REG */ "", 32560 /* GPORT_SGMII0_STATUS0_REG */ "", 32561 /* GPORT_SGMII0_STATUS1_REG */ "", 32562 /* GPORT_SGMII1_CTRL_REG */ "", 32563 /* GPORT_SGMII1_STATUS0_REG */ "", 32564 /* GPORT_SGMII1_STATUS1_REG */ "", 32565 /* GPORT_SGNDET_EARLYCRS */ "", 32566 /* GPORT_SGN_DET_SEL */ "", 32567 /* GPORT_SOP_S0 */ "", 32568 /* GPORT_SOP_S1 */ "", 32569 /* GPORT_SOP_S3 */ "", 32570 /* GPORT_SOP_S4 */ "", 32571 /* GPORT_STAT_UPDATE_MASK */ "", 32572 /* GPORT_SW_FLOW_CONTROL */ "", 32573 /* GPORT_TPID */ "", 32574 /* GPORT_TS_TIMER_31_0_REG */ "", 32575 /* GPORT_TS_TIMER_47_32_REG */ "", 32576 /* GPORT_TXFIFO_ECC_DBE_STATUS */ "", 32577 /* GPORT_TXFIFO_ECC_SBE_STATUS */ "", 32578 /* GPORT_TX_EEE_LPI_DURATION_COUNTER */ "", 32579 /* GPORT_TX_EEE_LPI_EVENT_COUNTER */ "", 32580 /* GPORT_UMAC_CONTROL */ "", 32581 /* GPORT_WC_UCMEM_CTRL */ "", 32582 /* GPORT_XGXS0_CTRL_REG */ "", 32583 /* GPORT_XGXS0_LN0_STATUS0_REG */ "", 32584 /* GPORT_XGXS0_LN1_STATUS0_REG */ "", 32585 /* GPORT_XGXS0_LN2_STATUS0_REG */ "", 32586 /* GPORT_XGXS0_LN3_STATUS0_REG */ "", 32587 /* GR64 */ "", 32588 /* GR127 */ "", 32589 /* GR255 */ "", 32590 /* GR511 */ "", 32591 /* GR1023 */ "", 32592 /* GR1518 */ "", 32593 /* GR2047 */ "", 32594 /* GR4095 */ "", 32595 /* GR9216 */ "", 32596 /* GR16383 */ "", 32597 /* GR1023P */ "", 32598 /* GR127P */ "", 32599 /* GR1518P */ "", 32600 /* GR2047P */ "", 32601 /* GR255P */ "", 32602 /* GR4095P */ "", 32603 /* GR511P */ "", 32604 /* GR64P */ "", 32605 /* GR9216P */ "", 32606 /* GRALN */ "", 32607 /* GRALNP */ "", 32608 /* GRBCA */ "", 32609 /* GRBCAP */ "", 32610 /* GRBYT */ "", 32611 /* GRBYTP */ "", 32612 /* GRCDE */ "", 32613 /* GRCDEP */ "", 32614 /* GRDMFP */ "", 32615 /* GRFCR */ "", 32616 /* GRFCRP */ "", 32617 /* GRFCS */ "", 32618 /* GRFCSP */ "", 32619 /* GRFFSEP */ "", 32620 /* GRFLR */ "", 32621 /* GRFLRP */ "", 32622 /* GRFRG */ "", 32623 /* GRFRGP */ "", 32624 /* GRJBR */ "", 32625 /* GRJBRP */ "", 32626 /* GRMCA */ "", 32627 /* GRMCAP */ "", 32628 /* GRMFAEP */ "", 32629 /* GRMFAOP */ "", 32630 /* GRMGV */ "", 32631 /* GRMGVP */ "", 32632 /* GRMSEP */ "", 32633 /* GRMTUE */ "", 32634 /* GRMTUEP */ "", 32635 /* GRNFFP */ "", 32636 /* GRNFSEP */ "", 32637 /* GROVR */ "", 32638 /* GROVRP */ "", 32639 /* GRPFC */ "", 32640 /* GRPFC0 */ "", 32641 /* GRPFC1 */ "", 32642 /* GRPFC2 */ "", 32643 /* GRPFC3 */ "", 32644 /* GRPFC4 */ "", 32645 /* GRPFC5 */ "", 32646 /* GRPFC6 */ "", 32647 /* GRPFC7 */ "", 32648 /* GRPFCOFF0 */ "", 32649 /* GRPFCOFF1 */ "", 32650 /* GRPFCOFF2 */ "", 32651 /* GRPFCOFF3 */ "", 32652 /* GRPFCOFF4 */ "", 32653 /* GRPFCOFF5 */ "", 32654 /* GRPFCOFF6 */ "", 32655 /* GRPFCOFF7 */ "", 32656 /* GRPKT */ "", 32657 /* GRPKTP */ "", 32658 /* GRPOK */ "", 32659 /* GRPOKP */ "", 32660 /* GRRBYT */ "", 32661 /* GRRBYTP */ "", 32662 /* GRRMFP */ "", 32663 /* GRRPKT */ "", 32664 /* GRRPKTP */ "", 32665 /* GRUC */ "", 32666 /* GRUCP */ "", 32667 /* GRUND */ "", 32668 /* GRUNDP */ "", 32669 /* GRVMFP */ "", 32670 /* GRXCF */ "", 32671 /* GRXPF */ "", 32672 /* GRXPP */ "", 32673 /* GRXUO */ "", 32674 /* GRX_EEE_LPI_DURATION_COUNTER */ "", 32675 /* GRX_EEE_LPI_EVENT_COUNTER */ "", 32676 /* GSA0 */ "", 32677 /* GSA1 */ "", 32678 /* GSBU_OVERSUB_FC_CONFIG1 */ "", 32679 /* GT64 */ "", 32680 /* GT127 */ "", 32681 /* GT255 */ "", 32682 /* GT511 */ "", 32683 /* GT1023 */ "", 32684 /* GT1518 */ "", 32685 /* GT2047 */ "", 32686 /* GT4095 */ "", 32687 /* GT9216 */ "", 32688 /* GT16383 */ "", 32689 /* GT1023P */ "", 32690 /* GT127P */ "", 32691 /* GT1518P */ "", 32692 /* GT2047P */ "", 32693 /* GT255P */ "", 32694 /* GT4095P */ "", 32695 /* GT511P */ "", 32696 /* GT64P */ "", 32697 /* GT9216P */ "", 32698 /* GTBCA */ "", 32699 /* GTBCAP */ "", 32700 /* GTBYT */ "", 32701 /* GTBYTP */ "", 32702 /* GTDFR */ "", 32703 /* GTDFRP */ "", 32704 /* GTEDF */ "", 32705 /* GTEDFP */ "", 32706 /* GTFCS */ "", 32707 /* GTFCSP */ "", 32708 /* GTFRG */ "", 32709 /* GTFRGP */ "", 32710 /* GTJBR */ "", 32711 /* GTJBRP */ "", 32712 /* GTLCL */ "", 32713 /* GTLCLP */ "", 32714 /* GTMCA */ "", 32715 /* GTMCAP */ "", 32716 /* GTMCL */ "", 32717 /* GTMCLP */ "", 32718 /* GTMFAEP */ "", 32719 /* GTMGV */ "", 32720 /* GTMGVP */ "", 32721 /* GTNCL */ "", 32722 /* GTNCLP */ "", 32723 /* GTNFFP */ "", 32724 /* GTOVR */ "", 32725 /* GTOVRP */ "", 32726 /* GTPFC */ "", 32727 /* GTPFC0 */ "", 32728 /* GTPFC1 */ "", 32729 /* GTPFC2 */ "", 32730 /* GTPFC3 */ "", 32731 /* GTPFC4 */ "", 32732 /* GTPFC5 */ "", 32733 /* GTPFC6 */ "", 32734 /* GTPFC7 */ "", 32735 /* GTPFCOFF0 */ "", 32736 /* GTPFCOFF1 */ "", 32737 /* GTPFCOFF2 */ "", 32738 /* GTPFCOFF3 */ "", 32739 /* GTPFCOFF4 */ "", 32740 /* GTPFCOFF5 */ "", 32741 /* GTPFCOFF6 */ "", 32742 /* GTPFCOFF7 */ "", 32743 /* GTPKT */ "", 32744 /* GTPKTP */ "", 32745 /* GTPOK */ "", 32746 /* GTPOKP */ "", 32747 /* GTRMFP */ "", 32748 /* GTSCL */ "", 32749 /* GTSCLP */ "", 32750 /* GTUC */ "", 32751 /* GTUCP */ "", 32752 /* GTVMFP */ "", 32753 /* GTXCF */ "", 32754 /* GTXCL */ "", 32755 /* GTXCLP */ "", 32756 /* GTXPF */ "", 32757 /* GTXPP */ "", 32758 /* GTX_EEE_LPI_DURATION_COUNTER */ "", 32759 /* GTX_EEE_LPI_EVENT_COUNTER */ "", 32760 /* GXPORT_LAG_FAILOVER_CONFIG */ "", 32761 /* GXPORT_LAG_FAILOVER_STATUS */ "", 32762 /* HASH_CONTROL */ "", 32763 /* HASH_TABLE_PARITY_CONTROL */ "", 32764 /* HBC_BIST_ADDR_CONFIG */ "", 32765 /* HBC_BIST_BANK_REORDER */ "", 32766 /* HBC_BIST_COMMAND_CONFIG */ "", 32767 /* HBC_BIST_CONTROL */ "", 32768 /* HBC_BIST_DATA_CONFIG */ "", 32769 /* HBC_BIST_DATA_MISR_MAP */ "", 32770 /* HBC_BIST_DATA_PRESET */ "", 32771 /* HBC_BIST_DWORD_MISR_STATE */ "", 32772 /* HBC_BIST_ERR_COUNTERS */ "", 32773 /* HBC_BIST_PATTERN */ "", 32774 /* HBC_BIST_STATUS */ "", 32775 /* HBC_BLOCKED_BY_COHERENCY_CNT */ "", 32776 /* HBC_DATA_SOURCE_CONFIG */ "", 32777 /* HBC_DRAM_CHANNEL_BLOCKED_CONFIG */ "", 32778 /* HBC_DRAM_CHANNEL_BLOCKED_STATUS */ "", 32779 /* HBC_DSI_ASYNC_FIFO_CONFIG */ "", 32780 /* HBC_DSI_INTERRUPT_MASK_REGISTER */ "", 32781 /* HBC_DSI_INTERRUPT_REGISTER */ "", 32782 /* HBC_DSI_INTERRUPT_REGISTER_TEST */ "", 32783 /* HBC_ECC_1B_ERR_CNT */ "", 32784 /* HBC_ECC_2B_ERR_CNT */ "", 32785 /* HBC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 32786 /* HBC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 32787 /* HBC_ECC_INTERRUPT_REGISTER */ "", 32788 /* HBC_ECC_INTERRUPT_REGISTER_MASK */ "", 32789 /* HBC_ECC_INTERRUPT_REGISTER_TEST */ "", 32790 /* HBC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 32791 /* HBC_ERROR_INITIATION_DATA */ "", 32792 /* HBC_GTIMER_CONFIGURATION */ "", 32793 /* HBC_GTIMER_CYCLE */ "", 32794 /* HBC_HBM_COLUMN_ACCESS_TIMINGS */ "", 32795 /* HBC_HBM_COMMAND_COUNTERS */ "", 32796 /* HBC_HBM_CONFIG */ "", 32797 /* HBC_HBM_CPU_CONTROL */ "", 32798 /* HBC_HBM_ECC_ERR_INFO */ "", 32799 /* HBC_HBM_ERR_COUNTERS */ "", 32800 /* HBC_HBM_GENERAL_TIMINGS */ "", 32801 /* HBC_HBM_MODE_REGISTERS */ "", 32802 /* HBC_HBM_MODE_REGISTER_MANAGER_CONFIG */ "", 32803 /* HBC_HBM_PHY_CH_REGISTER_ACCESS_ERROR */ "", 32804 /* HBC_HBM_REFRESH_INTERVALS */ "", 32805 /* HBC_HBM_REFRESH_TIMINGS */ "", 32806 /* HBC_HBM_ROW_ACCESS_TIMINGS */ "", 32807 /* HBC_INDIRECT_COMMAND */ "", 32808 /* HBC_INDIRECT_COMMAND_ADDRESS */ "", 32809 /* HBC_INDIRECT_COMMAND_RD_DATA */ "", 32810 /* HBC_INDIRECT_COMMAND_WR_DATA */ "", 32811 /* HBC_INDIRECT_FORCE_BUBBLE */ "", 32812 /* HBC_INTERRUPT_MASK_REGISTER */ "", 32813 /* HBC_INTERRUPT_REGISTER */ "", 32814 /* HBC_INTERRUPT_REGISTER_TEST */ "", 32815 /* HBC_LAST_RETURNED_DATA */ "", 32816 /* HBC_PARITY_ERR_CNT */ "", 32817 /* HBC_PAR_ERR_MEM_MASK */ "", 32818 /* HBC_PIPELINES_BANK_REMAPPING */ "", 32819 /* HBC_PIPELINES_COMMAND_PIN_MUX */ "", 32820 /* HBC_PIPELINES_CONFIG */ "", 32821 /* HBC_PIPELINES_DEBUG */ "", 32822 /* HBC_PIPELINES_INTERRUPT_MASK_REGISTER */ "", 32823 /* HBC_PIPELINES_INTERRUPT_REGISTER */ "", 32824 /* HBC_PIPELINES_INTERRUPT_REGISTER_TEST */ "", 32825 /* HBC_PIPELINES_PHY_RCMD */ "", 32826 /* HBC_RDR_DS_TRANS_CNT */ "", 32827 /* HBC_RDR_INTERRUPT_MASK_REGISTER */ "", 32828 /* HBC_RDR_INTERRUPT_REGISTER */ "", 32829 /* HBC_RDR_INTERRUPT_REGISTER_TEST */ "", 32830 /* HBC_RDR_RD_INFO_WMK */ "", 32831 /* HBC_RDR_TOT_TRANS_CNT */ "", 32832 /* HBC_READ_DATA_REORDER_STATUS */ "", 32833 /* HBC_REG_0041 */ "", 32834 /* HBC_REG_00A4 */ "", 32835 /* HBC_REG_00A6 */ "", 32836 /* HBC_REG_00AA */ "", 32837 /* HBC_REG_00C2 */ "", 32838 /* HBC_RESERVED_MIRROR_ADDR */ "", 32839 /* HBC_RESERVED_MTCD */ "", 32840 /* HBC_RESERVED_MTCP */ "", 32841 /* HBC_RESERVED_SPARE_0 */ "", 32842 /* HBC_RESERVED_SPARE_1 */ "", 32843 /* HBC_RESERVED_SPARE_2 */ "", 32844 /* HBC_RESERVED_SPARE_3 */ "", 32845 /* HBC_RPBQ_CONFIG */ "", 32846 /* HBC_RPBQ_STATUS */ "", 32847 /* HBC_SBUS_BROADCAST_ID */ "", 32848 /* HBC_SBUS_LAST_IN_CHAIN */ "", 32849 /* HBC_SPECIAL_CLOCK_CONTROLS */ "", 32850 /* HBC_TSM_CONFIG */ "", 32851 /* HBC_TSM_DEBUG */ "", 32852 /* HBC_TSM_READ_WRITE_SWITCH_CONFIG */ "", 32853 /* HBC_WDB_STATUS */ "", 32854 /* HBC_WPBQ_CONFIG */ "", 32855 /* HBC_WPBQ_STATUS */ "", 32856 /* HBMC_ECC_INTERRUPT_REGISTER */ "", 32857 /* HBMC_ECC_INTERRUPT_REGISTER_MASK */ "", 32858 /* HBMC_ECC_INTERRUPT_REGISTER_TEST */ "", 32859 /* HBMC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 32860 /* HBMC_HBM_PHY_CHANNEL_CONTROL */ "", 32861 /* HBMC_HBM_PHY_CHM_REGISTER_ACCESS_ERROR */ "", 32862 /* HBMC_HBM_PHY_CONTROL */ "", 32863 /* HBMC_HBM_PLL_CONFIG */ "", 32864 /* HBMC_HBM_PLL_STATUS */ "", 32865 /* HBMC_HBM_REPAIR_CONTROL */ "", 32866 /* HBMC_HBM_REPAIR_STATUS */ "", 32867 /* HBMC_HBM_RESET_CONTROL */ "", 32868 /* HBMC_HBM_STATUS */ "", 32869 /* HBMC_INDIRECT_COMMAND */ "", 32870 /* HBMC_INDIRECT_COMMAND_ADDRESS */ "", 32871 /* HBMC_INDIRECT_COMMAND_RD_DATA */ "", 32872 /* HBMC_INDIRECT_COMMAND_WR_DATA */ "", 32873 /* HBMC_INDIRECT_FORCE_BUBBLE */ "", 32874 /* HBMC_INTERRUPT_MASK_REGISTER */ "", 32875 /* HBMC_INTERRUPT_REGISTER */ "", 32876 /* HBMC_INTERRUPT_REGISTER_TEST */ "", 32877 /* HBMC_REG_0041 */ "", 32878 /* HBMC_REG_009A */ "", 32879 /* HBMC_REG_009C */ "", 32880 /* HBMC_REG_00A4 */ "", 32881 /* HBMC_REG_00A6 */ "", 32882 /* HBMC_RESERVED_MIRROR_ADDR */ "", 32883 /* HBMC_RESERVED_MTCD */ "", 32884 /* HBMC_RESERVED_MTCP */ "", 32885 /* HBMC_RESERVED_SPARE_0 */ "", 32886 /* HBMC_RESERVED_SPARE_1 */ "", 32887 /* HBMC_RESERVED_SPARE_2 */ "", 32888 /* HBMC_RESERVED_SPARE_3 */ "", 32889 /* HBMC_SBUS_BROADCAST_ID */ "", 32890 /* HBMC_SBUS_LAST_IN_CHAIN */ "", 32891 /* HBMC_SPECIAL_CLOCK_CONTROLS */ "", 32892 /* HCFC_ERR */ "", 32893 /* HDR_CAPTURE_CONTROL */ "", 32894 /* HDR_CAPTURE_DATA */ "", 32895 /* HDR_CAPTURE_MDATA0 */ "", 32896 /* HDR_CAPTURE_MDATA1 */ "", 32897 /* HES_L0_CONFIG */ "", 32898 /* HES_PORT_CONFIG */ "", 32899 /* HES_Q_COSMASK */ "", 32900 /* HES_Q_COSWEIGHTS */ "", 32901 /* HES_Q_MINSP */ "", 32902 /* HES_Q_WERRCOUNT */ "", 32903 /* HG_COUNTERS_PARITY_CONTROL */ "", 32904 /* HG_COUNTERS_PARITY_STATUS_INTR */ "", 32905 /* HG_COUNTERS_PARITY_STATUS_NACK */ "", 32906 /* HG_EH_CONTROL */ "", 32907 /* HG_LOOKUP_DESTINATION */ "", 32908 /* HG_PKT_SIGNATURE_1 */ "", 32909 /* HG_PKT_SIGNATURE_2 */ "", 32910 /* HG_PKT_SIGNATURE_3 */ "", 32911 /* HG_TRUNK_BITMAP */ "", 32912 /* HG_TRUNK_BITMAP_64 */ "HG_TRUNK_BITMAP", 32913 /* HG_TRUNK_BITMAP_HI */ "", 32914 /* HG_TRUNK_BITMAP_LO */ "", 32915 /* HG_TRUNK_FAILOVER_ENABLE */ "", 32916 /* HG_TRUNK_FAILOVER_ENABLE_64 */ "HG_TRUNK_FAILOVER_ENABLE", 32917 /* HG_TRUNK_FAILOVER_ENABLE_HI */ "", 32918 /* HG_TRUNK_FAILOVER_ENABLE_LO */ "", 32919 /* HG_TRUNK_GROUP */ "", 32920 /* HG_TRUNK_GROUP_HI */ "", 32921 /* HG_TRUNK_RAND_LB_SEED */ "", 32922 /* HG_TRUNK_RAND_LB_SEED_PIPE0 */ "", 32923 /* HG_TRUNK_RAND_LB_SEED_PIPE1 */ "", 32924 /* HG_TRUNK_RAND_LB_SEED_PIPE2 */ "", 32925 /* HG_TRUNK_RAND_LB_SEED_PIPE3 */ "", 32926 /* HIGH_SPEED_PORT_BMP_0 */ "", 32927 /* HIGH_SPEED_PORT_BMP_1 */ "", 32928 /* HIGIGPORTBITMAP_0 */ "", 32929 /* HIGIGPORTBITMAP_1 */ "", 32930 /* HIGIGPORTBITMAP_2 */ "", 32931 /* HIGIG_AUX_HDR_BITMAP_PRIORITY_MASK */ "", 32932 /* HIGIG_BITMAP */ "", 32933 /* HIGIG_BITMAP_64 */ "HIGIG_BITMAP", 32934 /* HIGIG_BITMAP_HI */ "", 32935 /* HIGIG_BITMAP_LO */ "", 32936 /* HIGIG_TRUNK_CONTROL */ "", 32937 /* HIGIG_TRUNK_CONTROL_64 */ "HIGIG_TRUNK_CONTROL", 32938 /* HIGIG_TRUNK_CONTROL_HI */ "", 32939 /* HIGIG_TRUNK_CONTROL_LO */ "", 32940 /* HIGIG_TRUNK_GROUP */ "", 32941 /* HOLCOS0MINXQCNT */ "", 32942 /* HOLCOS1MINXQCNT */ "", 32943 /* HOLCOS2MINXQCNT */ "", 32944 /* HOLCOS3MINXQCNT */ "", 32945 /* HOLCOSCELLMAXLIMIT */ "", 32946 /* HOLCOSCELLMAXLIMIT_QGROUP */ "", 32947 /* HOLCOSCELLMAXLIMIT_QLAYER */ "", 32948 /* HOLCOSMINXQCNT */ "", 32949 /* HOLCOSMINXQCNT_QLAYER */ "", 32950 /* HOLCOSPKTRESETLIMIT */ "", 32951 /* HOLCOSPKTRESETLIMIT_QGROUP */ "", 32952 /* HOLCOSPKTRESETLIMIT_QLAYER */ "", 32953 /* HOLCOSPKTSETLIMIT */ "", 32954 /* HOLCOSPKTSETLIMIT_QGROUP */ "", 32955 /* HOLCOSPKTSETLIMIT_QLAYER */ "", 32956 /* HOLCOSSTATUS */ "", 32957 /* HOLCOSSTATUS_PBMP0 */ "", 32958 /* HOLCOSSTATUS_PBMP1 */ "", 32959 /* HOLCOSSTATUS_PBMP2 */ "", 32960 /* HOLCOSSTATUS_QGROUP */ "", 32961 /* HOLD */ "", 32962 /* HOLDROP_PKT_CNT */ "", 32963 /* HOLD_COS0 */ "", 32964 /* HOLD_COS1 */ "", 32965 /* HOLD_COS2 */ "", 32966 /* HOLD_COS3 */ "", 32967 /* HOLD_COS4 */ "", 32968 /* HOLD_COS5 */ "", 32969 /* HOLD_COS6 */ "", 32970 /* HOLD_COS7 */ "", 32971 /* HOLD_COS0_X */ "", 32972 /* HOLD_COS0_Y */ "", 32973 /* HOLD_COS1_X */ "", 32974 /* HOLD_COS1_Y */ "", 32975 /* HOLD_COS2_X */ "", 32976 /* HOLD_COS2_Y */ "", 32977 /* HOLD_COS3_X */ "", 32978 /* HOLD_COS3_Y */ "", 32979 /* HOLD_COS4_X */ "", 32980 /* HOLD_COS4_Y */ "", 32981 /* HOLD_COS5_X */ "", 32982 /* HOLD_COS5_Y */ "", 32983 /* HOLD_COS6_X */ "", 32984 /* HOLD_COS6_Y */ "", 32985 /* HOLD_COS7_X */ "", 32986 /* HOLD_COS7_Y */ "", 32987 /* HOLD_COS_PORT_SELECT */ "", 32988 /* HOLD_COS_QM */ "", 32989 /* HOLD_COS_QM_X */ "", 32990 /* HOLD_COS_QM_Y */ "", 32991 /* HOLD_COS_SC */ "", 32992 /* HOLD_COS_SC_X */ "", 32993 /* HOLD_COS_SC_Y */ "", 32994 /* HOLD_X */ "", 32995 /* HOLD_Y */ "", 32996 /* HOL_DROP */ "", 32997 /* HOL_STAT_BMAP */ "", 32998 /* HOL_STAT_BMAP_HI */ "", 32999 /* HOL_STAT_CPU */ "", 33000 /* HOL_STAT_PORT */ "", 33001 /* HPIPE0_OVR_SUB_GRP0_TBL */ "", 33002 /* HPIPE0_OVR_SUB_GRP1_TBL */ "", 33003 /* HPIPE0_OVR_SUB_GRP2_TBL */ "", 33004 /* HPIPE0_OVR_SUB_GRP3_TBL */ "", 33005 /* HPIPE0_OVR_SUB_GRP4_TBL */ "", 33006 /* HPIPE0_OVR_SUB_GRP5_TBL */ "", 33007 /* HPIPE0_OVR_SUB_GRP_CFG */ "", 33008 /* HPIPE0_PBLK0_CALENDAR */ "", 33009 /* HPIPE0_PBLK1_CALENDAR */ "", 33010 /* HPIPE0_PBLK2_CALENDAR */ "", 33011 /* HPIPE0_PBLK3_CALENDAR */ "", 33012 /* HPIPE0_PBLK4_CALENDAR */ "", 33013 /* HPIPE0_PBLK5_CALENDAR */ "", 33014 /* HPIPE0_PBLK6_CALENDAR */ "", 33015 /* HPIPE0_PBLK7_CALENDAR */ "", 33016 /* HPIPE0_PBLK8_CALENDAR */ "", 33017 /* HPIPE0_PBLK9_CALENDAR */ "", 33018 /* HPIPE1_OVR_SUB_GRP0_TBL */ "", 33019 /* HPIPE1_OVR_SUB_GRP1_TBL */ "", 33020 /* HPIPE1_OVR_SUB_GRP2_TBL */ "", 33021 /* HPIPE1_OVR_SUB_GRP3_TBL */ "", 33022 /* HPIPE1_OVR_SUB_GRP4_TBL */ "", 33023 /* HPIPE1_OVR_SUB_GRP5_TBL */ "", 33024 /* HPIPE1_OVR_SUB_GRP_CFG */ "", 33025 /* HPIPE1_PBLK0_CALENDAR */ "", 33026 /* HPIPE1_PBLK1_CALENDAR */ "", 33027 /* HPIPE1_PBLK2_CALENDAR */ "", 33028 /* HPIPE1_PBLK3_CALENDAR */ "", 33029 /* HPIPE1_PBLK4_CALENDAR */ "", 33030 /* HPIPE1_PBLK5_CALENDAR */ "", 33031 /* HPIPE1_PBLK6_CALENDAR */ "", 33032 /* HPIPE1_PBLK7_CALENDAR */ "", 33033 /* HPIPE1_PBLK8_CALENDAR */ "", 33034 /* HPIPE1_PBLK9_CALENDAR */ "", 33035 /* HSP_CONFIG */ "", 33036 /* HSP_EMPTY_STATUS_P0 */ "", 33037 /* HSP_EMPTY_STATUS_P1 */ "", 33038 /* HSP_EN_COR_ERR_RPT */ "", 33039 /* HSP_MEMORY_TM */ "", 33040 /* HSP_MEMORY_TM_0 */ "", 33041 /* HSP_MEMORY_TM_1 */ "", 33042 /* HSP_MEMORY_TM_2 */ "", 33043 /* HSP_MEMORY_TM_3 */ "", 33044 /* HSP_MEMORY_TM_4 */ "", 33045 /* HSP_PIPEX_SPECIAL_CONFIG */ "", 33046 /* HSP_PIPEY_SPECIAL_CONFIG */ "", 33047 /* HSP_SCHED_GLOBAL_CONFIG */ "", 33048 /* HSP_SCHED_L0_NODE_4_CONNECTION_CONFIG */ "", 33049 /* HSP_SCHED_L0_NODE_CONFIG */ "", 33050 /* HSP_SCHED_L0_NODE_CONNECTION_CONFIG */ "", 33051 /* HSP_SCHED_L0_NODE_WEIGHT */ "", 33052 /* HSP_SCHED_L1_NODE_CONFIG */ "", 33053 /* HSP_SCHED_L1_NODE_WEIGHT */ "", 33054 /* HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG0 */ "", 33055 /* HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG1 */ "", 33056 /* HSP_SCHED_L2_MC_CPU_QUEUE_CONFIG2 */ "", 33057 /* HSP_SCHED_L2_MC_QUEUE_CONFIG */ "", 33058 /* HSP_SCHED_L2_MC_QUEUE_WEIGHT */ "", 33059 /* HSP_SCHED_L2_UC_QUEUE_CONFIG */ "", 33060 /* HSP_SCHED_L2_UC_QUEUE_WEIGHT */ "", 33061 /* HSP_SCHED_PORT_CONFIG */ "", 33062 /* HSP_SCHED_PORT_PREEMPT_CONFIG */ "", 33063 /* HW_MAC_LEARNING */ "", 33064 /* IARB_CELL_DEBUG */ "", 33065 /* IARB_CELL_PKT_BYTES */ "", 33066 /* IARB_DBGCTRL */ "IARB_ECC_DEBUG", 33067 /* IARB_DEBUG */ "", 33068 /* IARB_DPP_CTRL */ "", 33069 /* IARB_DPP_CTRL_PIPE0 */ "", 33070 /* IARB_DPP_CTRL_PIPE1 */ "", 33071 /* IARB_DPP_CTRL_PIPE2 */ "", 33072 /* IARB_DPP_CTRL_PIPE3 */ "", 33073 /* IARB_DPP_CTRL_PIPE4 */ "", 33074 /* IARB_DPP_CTRL_PIPE5 */ "", 33075 /* IARB_DPP_CTRL_PIPE6 */ "", 33076 /* IARB_DPP_CTRL_PIPE7 */ "", 33077 /* IARB_ECC_ERROR */ "", 33078 /* IARB_ECC_ERROR_MASK */ "", 33079 /* IARB_EN_COR_ERR_RPT */ "", 33080 /* IARB_ERROR */ "", 33081 /* IARB_ERROR_MASK */ "", 33082 /* IARB_EVENT_FIFO_STATUS */ "", 33083 /* IARB_EVENT_FIFO_STATUS_PIPE0 */ "", 33084 /* IARB_EVENT_FIFO_STATUS_PIPE1 */ "", 33085 /* IARB_EVENT_FIFO_STATUS_PIPE2 */ "", 33086 /* IARB_EVENT_FIFO_STATUS_PIPE3 */ "", 33087 /* IARB_EVENT_FIFO_STATUS_PIPE4 */ "", 33088 /* IARB_EVENT_FIFO_STATUS_PIPE5 */ "", 33089 /* IARB_EVENT_FIFO_STATUS_PIPE6 */ "", 33090 /* IARB_EVENT_FIFO_STATUS_PIPE7 */ "", 33091 /* IARB_HDR_ECC_CONTROL */ "", 33092 /* IARB_HDR_ECC_STATUS_INTR */ "", 33093 /* IARB_HW_CONTROL */ "", 33094 /* IARB_HW_STATUS */ "", 33095 /* IARB_HW_STATUS_PIPE0 */ "", 33096 /* IARB_HW_STATUS_PIPE1 */ "", 33097 /* IARB_HW_STATUS_PIPE2 */ "", 33098 /* IARB_HW_STATUS_PIPE3 */ "", 33099 /* IARB_HW_STATUS_PIPE4 */ "", 33100 /* IARB_HW_STATUS_PIPE5 */ "", 33101 /* IARB_HW_STATUS_PIPE6 */ "", 33102 /* IARB_HW_STATUS_PIPE7 */ "", 33103 /* IARB_IL_ECC_STATUS */ "", 33104 /* IARB_LEARN_CONTROL */ "", 33105 /* IARB_LEARN_FIFO_2B_ERROR_STATUS */ "", 33106 /* IARB_LEARN_FIFO_ECC_CONTROL */ "", 33107 /* IARB_MY_MODID_SET_64 */ "", 33108 /* IARB_OAM_REFRESH_CONTROL */ "", 33109 /* IARB_OLP_CONFIG */ "", 33110 /* IARB_OLP_CONFIG_1 */ "", 33111 /* IARB_OPP_SCH_CONTROL */ "", 33112 /* IARB_PDU_ECC_STATUS */ "", 33113 /* IARB_PIPE_X_LERAN_FIFO_ECC_STATUS_INTR */ "", 33114 /* IARB_PIPE_Y_LERAN_FIFO_ECC_STATUS_INTR */ "", 33115 /* IARB_PKT_ECC_CONTROL */ "", 33116 /* IARB_PKT_ECC_STATUS_INTR */ "", 33117 /* IARB_PKT_PARITY_STATUS_INTR */ "", 33118 /* IARB_RAM_CONTROL */ "IARB_RAM_CONTROL", 33119 /* IARB_RAM_CONTROL_PIPE0 */ "IARB_RAM_CONTROL_PIPE0", 33120 /* IARB_RAM_CONTROL_PIPE1 */ "IARB_RAM_CONTROL_PIPE1", 33121 /* IARB_RAM_CONTROL_PIPE2 */ "IARB_RAM_CONTROL_PIPE2", 33122 /* IARB_RAM_CONTROL_PIPE3 */ "IARB_RAM_CONTROL_PIPE3", 33123 /* IARB_RAM_CONTROL_PIPE4 */ "IARB_RAM_CONTROL_PIPE4", 33124 /* IARB_RAM_CONTROL_PIPE5 */ "IARB_RAM_CONTROL_PIPE5", 33125 /* IARB_RAM_CONTROL_PIPE6 */ "IARB_RAM_CONTROL_PIPE6", 33126 /* IARB_RAM_CONTROL_PIPE7 */ "IARB_RAM_CONTROL_PIPE7", 33127 /* IARB_REGS_DEBUG */ "", 33128 /* IARB_SBUS_TIMER */ "", 33129 /* IARB_SER_CONTROL */ "", 33130 /* IARB_SER_SCAN_CONFIG */ "", 33131 /* IARB_SER_SCAN_CONFIG_PIPE0 */ "", 33132 /* IARB_SER_SCAN_CONFIG_PIPE1 */ "", 33133 /* IARB_SER_SCAN_CONFIG_PIPE2 */ "", 33134 /* IARB_SER_SCAN_CONFIG_PIPE3 */ "", 33135 /* IARB_SER_SCAN_CONFIG_PIPE4 */ "", 33136 /* IARB_SER_SCAN_CONFIG_PIPE5 */ "", 33137 /* IARB_SER_SCAN_CONFIG_PIPE6 */ "", 33138 /* IARB_SER_SCAN_CONFIG_PIPE7 */ "", 33139 /* IARB_SER_SCAN_STATUS */ "", 33140 /* IARB_SER_SCAN_STATUS_PIPE0 */ "", 33141 /* IARB_SER_SCAN_STATUS_PIPE1 */ "", 33142 /* IARB_SER_SCAN_STATUS_PIPE2 */ "", 33143 /* IARB_SER_SCAN_STATUS_PIPE3 */ "", 33144 /* IARB_SER_SCAN_STATUS_PIPE4 */ "", 33145 /* IARB_SER_SCAN_STATUS_PIPE5 */ "", 33146 /* IARB_SER_SCAN_STATUS_PIPE6 */ "", 33147 /* IARB_SER_SCAN_STATUS_PIPE7 */ "", 33148 /* IARB_TDM_CONTROL */ "", 33149 /* IARB_TDM_MAP */ "", 33150 /* IBCAST */ "", 33151 /* IBCAST_64 */ "IBCAST", 33152 /* IBCAST_BLOCK_MASK */ "", 33153 /* IBCAST_BLOCK_MASK_64 */ "IBCAST_BLOCK_MASK", 33154 /* IBCAST_BLOCK_MASK_HI */ "", 33155 /* IBCAST_BLOCK_MASK_HI_64 */ "IBCAST_BLOCK_MASK_HI_64", 33156 /* IBCAST_BLOCK_MASK_LO_64 */ "IBCAST_BLOCK_MASK_LO_64", 33157 /* IBOD_BOD_FIFO_CONTROL */ "", 33158 /* IBOD_CL0_FIFO_ALMOST_FULL_ASSERT_THRESHOLD */ "", 33159 /* IBOD_CL0_FIFO_ALMOST_FULL_DEASSERT_THRESHOLD */ "", 33160 /* IBOD_CL0_FIFO_ECC_STATUS_INTR */ "", 33161 /* IBOD_CL1_FIFO_ALMOST_FULL_ASSERT_THRESHOLD */ "", 33162 /* IBOD_CL1_FIFO_ALMOST_FULL_DEASSERT_THRESHOLD */ "", 33163 /* IBOD_CL1_FIFO_ECC_STATUS_INTR */ "", 33164 /* IBOD_CL2_FIFO_ALMOST_FULL_ASSERT_THRESHOLD */ "", 33165 /* IBOD_CL2_FIFO_ALMOST_FULL_DEASSERT_THRESHOLD */ "", 33166 /* IBOD_CL2_FIFO_ECC_STATUS_INTR */ "", 33167 /* IBOD_CLK_SHUTDOWN */ "", 33168 /* IBOD_FIFO_EMPTY */ "", 33169 /* IBOD_FIFO_FULL_ERR_STATUS */ "", 33170 /* IBOD_INTR_MASK */ "", 33171 /* IBOD_INTR_STATUS */ "", 33172 /* IBOD_MEM_STBY */ "", 33173 /* IBOD_MOOSE_CLP0_CTRL */ "", 33174 /* IBOD_MOOSE_CLP0_MH_0 */ "", 33175 /* IBOD_MOOSE_CLP0_MH_1 */ "", 33176 /* IBOD_MOOSE_CLP0_MH_2 */ "", 33177 /* IBOD_MOOSE_CLP0_MH_3 */ "", 33178 /* IBOD_MOOSE_CLP0_SH */ "", 33179 /* IBOD_MOOSE_CLP0_TS */ "", 33180 /* IBOD_MOOSE_CLP1_CTRL */ "", 33181 /* IBOD_MOOSE_CLP1_MH_0 */ "", 33182 /* IBOD_MOOSE_CLP1_MH_1 */ "", 33183 /* IBOD_MOOSE_CLP1_MH_2 */ "", 33184 /* IBOD_MOOSE_CLP1_MH_3 */ "", 33185 /* IBOD_MOOSE_CLP1_SH */ "", 33186 /* IBOD_MOOSE_CLP1_TS */ "", 33187 /* IBOD_MOOSE_XLP0_CTRL */ "", 33188 /* IBOD_MOOSE_XLP0_MH_0 */ "", 33189 /* IBOD_MOOSE_XLP0_MH_1 */ "", 33190 /* IBOD_MOOSE_XLP0_MH_2 */ "", 33191 /* IBOD_MOOSE_XLP0_MH_3 */ "", 33192 /* IBOD_MOOSE_XLP0_SH */ "", 33193 /* IBOD_MOOSE_XLP0_TS */ "", 33194 /* IBOD_MOOSE_XLP1_CTRL */ "", 33195 /* IBOD_MOOSE_XLP1_MH_0 */ "", 33196 /* IBOD_MOOSE_XLP1_MH_1 */ "", 33197 /* IBOD_MOOSE_XLP1_MH_2 */ "", 33198 /* IBOD_MOOSE_XLP1_MH_3 */ "", 33199 /* IBOD_MOOSE_XLP1_SH */ "", 33200 /* IBOD_MOOSE_XLP1_TS */ "", 33201 /* IBOD_MOOSE_XTP0_CTRL */ "", 33202 /* IBOD_MOOSE_XTP0_MH_0 */ "", 33203 /* IBOD_MOOSE_XTP0_MH_1 */ "", 33204 /* IBOD_MOOSE_XTP0_MH_2 */ "", 33205 /* IBOD_MOOSE_XTP0_MH_3 */ "", 33206 /* IBOD_MOOSE_XTP0_SH */ "", 33207 /* IBOD_MOOSE_XTP0_TS */ "", 33208 /* IBOD_MOOSE_XTP1_CTRL */ "", 33209 /* IBOD_MOOSE_XTP1_MH_0 */ "", 33210 /* IBOD_MOOSE_XTP1_MH_1 */ "", 33211 /* IBOD_MOOSE_XTP1_MH_2 */ "", 33212 /* IBOD_MOOSE_XTP1_MH_3 */ "", 33213 /* IBOD_MOOSE_XTP1_SH */ "", 33214 /* IBOD_MOOSE_XTP1_TS */ "", 33215 /* IBOD_MOOSE_XTP2_CTRL */ "", 33216 /* IBOD_MOOSE_XTP2_MH_0 */ "", 33217 /* IBOD_MOOSE_XTP2_MH_1 */ "", 33218 /* IBOD_MOOSE_XTP2_MH_2 */ "", 33219 /* IBOD_MOOSE_XTP2_MH_3 */ "", 33220 /* IBOD_MOOSE_XTP2_SH */ "", 33221 /* IBOD_MOOSE_XTP2_TS */ "", 33222 /* IBOD_MOOSE_XTP3_CTRL */ "", 33223 /* IBOD_MOOSE_XTP3_MH_0 */ "", 33224 /* IBOD_MOOSE_XTP3_MH_1 */ "", 33225 /* IBOD_MOOSE_XTP3_MH_2 */ "", 33226 /* IBOD_MOOSE_XTP3_MH_3 */ "", 33227 /* IBOD_MOOSE_XTP3_SH */ "", 33228 /* IBOD_MOOSE_XTP3_TS */ "", 33229 /* IBOD_XL0_FIFO_ECC_STATUS_INTR */ "", 33230 /* IBOD_XL1_FIFO_ECC_STATUS_INTR */ "", 33231 /* IBOD_XL_FIFO_ALMOST_FULL_ASSERT_DEASSERT_THRESHOLD */ "", 33232 /* IBOD_XT0_FIFO_ALMOST_FULL_ASSERT_THRESHOLD */ "", 33233 /* IBOD_XT0_FIFO_ALMOST_FULL_DEASSERT_THRESHOLD */ "", 33234 /* IBOD_XT0_FIFO_ECC_STATUS_INTR */ "", 33235 /* IBOD_XT1_FIFO_ALMOST_FULL_ASSERT_THRESHOLD */ "", 33236 /* IBOD_XT1_FIFO_ALMOST_FULL_DEASSERT_THRESHOLD */ "", 33237 /* IBOD_XT1_FIFO_ECC_STATUS_INTR */ "", 33238 /* IBOD_XT2_FIFO_ALMOST_FULL_ASSERT_THRESHOLD */ "", 33239 /* IBOD_XT2_FIFO_ALMOST_FULL_DEASSERT_THRESHOLD */ "", 33240 /* IBOD_XT2_FIFO_ECC_STATUS_INTR */ "", 33241 /* IBOD_XT3_FIFO_ALMOST_FULL_ASSERT_THRESHOLD */ "", 33242 /* IBOD_XT3_FIFO_ALMOST_FULL_DEASSERT_THRESHOLD */ "", 33243 /* IBOD_XT3_FIFO_ECC_STATUS_INTR */ "", 33244 /* IBPBKPSTATUS */ "", 33245 /* IBPBKPSTATUS_0 */ "", 33246 /* IBPBKPSTATUS_1 */ "", 33247 /* IBPBKPSTATUS_2 */ "", 33248 /* IBPCELLCOUNT */ "", 33249 /* IBPCELLSETLIMIT */ "", 33250 /* IBPDISCARDSETLIMIT */ "", 33251 /* IBPDISCSTATUS */ "", 33252 /* IBPPKTCOUNT */ "", 33253 /* IBPPKTSETLIMIT */ "", 33254 /* IBP_DROP_PKT_CNT */ "", 33255 /* IBUF_DEBUG_TM */ "", 33256 /* ICFG_A9JTAG_CONFIG_0 */ "", 33257 /* ICFG_A9JTAG_ECC_INTR_CLR */ "", 33258 /* ICFG_A9JTAG_ECC_INTR_EN */ "", 33259 /* ICFG_A9JTAG_ECC_INTR_STATUS */ "", 33260 /* ICFG_A9JTAG_ECC_LOG */ "", 33261 /* ICFG_AMAC_M0_RX_TM_CONFIG */ "", 33262 /* ICFG_AMAC_M0_RX_TM_CONFIG1 */ "", 33263 /* ICFG_AMAC_M0_TX_TM_CONFIG */ "", 33264 /* ICFG_AMAC_M0_TX_TM_CONFIG1 */ "", 33265 /* ICFG_AMAC_M0_UNIMAC_TM_CONFIG */ "", 33266 /* ICFG_AMAC_M0_UNIMAC_TM_CONFIG1 */ "", 33267 /* ICFG_AMAC_M1_RX_TM_CONFIG */ "", 33268 /* ICFG_AMAC_M1_RX_TM_CONFIG1 */ "", 33269 /* ICFG_AMAC_M1_TX_TM_CONFIG */ "", 33270 /* ICFG_AMAC_M1_TX_TM_CONFIG1 */ "", 33271 /* ICFG_AMAC_M1_UNIMAC_TM_CONFIG */ "", 33272 /* ICFG_AMAC_M1_UNIMAC_TM_CONFIG1 */ "", 33273 /* ICFG_AMAC_M2_RX_TM_CONFIG */ "", 33274 /* ICFG_AMAC_M2_TX_TM_CONFIG */ "", 33275 /* ICFG_AMAC_M2_UNIMAC_TM_CONFIG */ "", 33276 /* ICFG_ARMCSSYS_CONFIG_0 */ "", 33277 /* ICFG_ARMCSSYS_ECC_INTR_CLR */ "", 33278 /* ICFG_ARMCSSYS_ECC_INTR_EN */ "", 33279 /* ICFG_ARMCSSYS_ECC_INTR_STATUS */ "", 33280 /* ICFG_ARMCSSYS_ECC_LOG */ "", 33281 /* ICFG_ARMCSSYS_M0_IDM_IO_CONTROL_DIRECT */ "", 33282 /* ICFG_BOOTNIC */ "", 33283 /* ICFG_CCS_PKA_LIR_MEM_CTRL */ "", 33284 /* ICFG_CCS_PKA_OPCODE_FIFO_MEM_CTRL */ "", 33285 /* ICFG_CHIP_ID_REG */ "", 33286 /* ICFG_CHIP_LP_INTR_ENABLE_REG0 */ "", 33287 /* ICFG_CHIP_LP_INTR_ENABLE_REG1 */ "", 33288 /* ICFG_CHIP_LP_INTR_ENABLE_REG2 */ "", 33289 /* ICFG_CHIP_LP_INTR_ENABLE_REG3 */ "", 33290 /* ICFG_CHIP_LP_INTR_RAW_STATUS_REG0 */ "", 33291 /* ICFG_CHIP_LP_INTR_RAW_STATUS_REG1 */ "", 33292 /* ICFG_CHIP_LP_INTR_RAW_STATUS_REG2 */ "", 33293 /* ICFG_CHIP_LP_INTR_RAW_STATUS_REG3 */ "", 33294 /* ICFG_CHIP_LP_INTR_STATUS_REG0 */ "", 33295 /* ICFG_CHIP_LP_INTR_STATUS_REG1 */ "", 33296 /* ICFG_CHIP_LP_INTR_STATUS_REG2 */ "", 33297 /* ICFG_CHIP_LP_INTR_STATUS_REG3 */ "", 33298 /* ICFG_CHIP_REVISION_ID */ "", 33299 /* ICFG_CLK_GATING_CONTROL */ "", 33300 /* ICFG_CMICD_BASE_ADDRESS */ "", 33301 /* ICFG_CMICX_BASE_ADDRESS */ "", 33302 /* ICFG_CMIC_RCPU_SW_PROG_INTR */ "", 33303 /* ICFG_CMIC_RCPU_SW_PROG_INTR_CLR */ "", 33304 /* ICFG_CMIC_RCPU_SW_PROG_INTR_SET */ "", 33305 /* ICFG_CORTEXM0_U0_SW_PROG_INTR */ "", 33306 /* ICFG_CORTEXM0_U0_SW_PROG_INTR_CLR */ "", 33307 /* ICFG_CORTEXM0_U0_SW_PROG_INTR_SET */ "", 33308 /* ICFG_CORTEXM0_U1_SW_PROG_INTR */ "", 33309 /* ICFG_CORTEXM0_U1_SW_PROG_INTR_CLR */ "", 33310 /* ICFG_CORTEXM0_U1_SW_PROG_INTR_SET */ "", 33311 /* ICFG_CORTEXM0_U2_SW_PROG_INTR */ "", 33312 /* ICFG_CORTEXM0_U2_SW_PROG_INTR_CLR */ "", 33313 /* ICFG_CORTEXM0_U2_SW_PROG_INTR_SET */ "", 33314 /* ICFG_CORTEXM0_U3_SW_PROG_INTR */ "", 33315 /* ICFG_CORTEXM0_U3_SW_PROG_INTR_CLR */ "", 33316 /* ICFG_CORTEXM0_U3_SW_PROG_INTR_SET */ "", 33317 /* ICFG_CRU_STRAPS */ "", 33318 /* ICFG_CRYPTO_MEM_CONTROL_0 */ "", 33319 /* ICFG_CRYPTO_MEM_CONTROL_1 */ "", 33320 /* ICFG_DDR_STRAPS */ "", 33321 /* ICFG_DMAC_CH0_RD_ADDR */ "", 33322 /* ICFG_DMAC_CH0_WR_ADDR */ "", 33323 /* ICFG_DMAC_CH1_RD_ADDR */ "", 33324 /* ICFG_DMAC_CH1_WR_ADDR */ "", 33325 /* ICFG_DMAC_CH2_RD_ADDR */ "", 33326 /* ICFG_DMAC_CH2_WR_ADDR */ "", 33327 /* ICFG_DMAC_CH3_RD_ADDR */ "", 33328 /* ICFG_DMAC_CH3_WR_ADDR */ "", 33329 /* ICFG_DMAC_CH4_RD_ADDR */ "", 33330 /* ICFG_DMAC_CH4_WR_ADDR */ "", 33331 /* ICFG_DMAC_CH5_RD_ADDR */ "", 33332 /* ICFG_DMAC_CH5_WR_ADDR */ "", 33333 /* ICFG_DMAC_CH6_RD_ADDR */ "", 33334 /* ICFG_DMAC_CH6_WR_ADDR */ "", 33335 /* ICFG_DMAC_CH7_RD_ADDR */ "", 33336 /* ICFG_DMAC_CH7_WR_ADDR */ "", 33337 /* ICFG_DMAC_CH8_RD_ADDR */ "", 33338 /* ICFG_DMAC_CH8_WR_ADDR */ "", 33339 /* ICFG_DMAC_CONFIG_0 */ "", 33340 /* ICFG_DMAC_CONFIG_1 */ "", 33341 /* ICFG_DMAC_CONFIG_2 */ "", 33342 /* ICFG_DMAC_CONFIG_3 */ "", 33343 /* ICFG_DMAC_ECC_INTR_CLR */ "", 33344 /* ICFG_DMAC_ECC_INTR_EN */ "", 33345 /* ICFG_DMAC_ECC_INTR_STATUS */ "", 33346 /* ICFG_DMAC_ECC_LOG_1 */ "", 33347 /* ICFG_DMAC_ECC_LOG_2 */ "", 33348 /* ICFG_ECC_ERR_INTR_ENABLE */ "", 33349 /* ICFG_ECC_ERR_INTR_RAW_STATUS */ "", 33350 /* ICFG_ECC_ERR_INTR_STATUS */ "", 33351 /* ICFG_EN_COR_ERR_RPT */ "", 33352 /* ICFG_EROM_BASE_ADDRESS */ "", 33353 /* ICFG_GEN_PURPOSE_REG */ "", 33354 /* ICFG_GEN_PURPOSE_REG0 */ "", 33355 /* ICFG_GEN_PURPOSE_REG1 */ "", 33356 /* ICFG_GEN_PURPOSE_REG2 */ "", 33357 /* ICFG_GEN_PURPOSE_REG3 */ "", 33358 /* ICFG_GEN_PURPOSE_REG4 */ "", 33359 /* ICFG_GEN_PURPOSE_REG5 */ "", 33360 /* ICFG_GEN_PURPOSE_REG6 */ "", 33361 /* ICFG_GEN_PURPOSE_REG7 */ "", 33362 /* ICFG_GEN_PURPOSE_REG8 */ "", 33363 /* ICFG_GEN_PURPOSE_REG9 */ "", 33364 /* ICFG_GEN_PURPOSE_REG10 */ "", 33365 /* ICFG_GEN_PURPOSE_REG11 */ "", 33366 /* ICFG_GEN_PURPOSE_REG12 */ "", 33367 /* ICFG_GEN_PURPOSE_REG13 */ "", 33368 /* ICFG_GEN_PURPOSE_REG14 */ "", 33369 /* ICFG_GEN_PURPOSE_REG15 */ "", 33370 /* ICFG_IDM_INTR_ENABLE */ "", 33371 /* ICFG_IDM_INTR_RAW_STATUS */ "", 33372 /* ICFG_IDM_INTR_STATUS */ "", 33373 /* ICFG_IHOST_EXT_INTR_VECTOR_0 */ "", 33374 /* ICFG_IHOST_EXT_INTR_VECTOR_1 */ "", 33375 /* ICFG_IHOST_EXT_INTR_VECTOR_2 */ "", 33376 /* ICFG_IHOST_EXT_INTR_VECTOR_3 */ "", 33377 /* ICFG_IHOST_EXT_INTR_VECTOR_4 */ "", 33378 /* ICFG_IHOST_EXT_INTR_VECTOR_5 */ "", 33379 /* ICFG_IHOST_EXT_INTR_VECTOR_6 */ "", 33380 /* ICFG_IHOST_MEM_CONTROL_0 */ "", 33381 /* ICFG_IHOST_SSI_DEBUG_CONTROL */ "", 33382 /* ICFG_IHOST_SSI_DEBUG_STATUS */ "", 33383 /* ICFG_IHOST_SW_PROG_INTR */ "", 33384 /* ICFG_IHOST_SW_PROG_INTR_CLR */ "", 33385 /* ICFG_IHOST_SW_PROG_INTR_SET */ "", 33386 /* ICFG_IHOST_TO_MHOST_INTR */ "", 33387 /* ICFG_INTR_COUNTER_CTRL */ "", 33388 /* ICFG_INTR_COUNTER_LSB */ "", 33389 /* ICFG_INTR_COUNTER_MSB */ "", 33390 /* ICFG_IPROCGENRES1_SW_RST */ "", 33391 /* ICFG_IPROCGENRES_SW_RST */ "", 33392 /* ICFG_IPROCPERIPH_COMMON */ "", 33393 /* ICFG_IPROCPERIPH_I2CS0 */ "", 33394 /* ICFG_IPROCPERIPH_I2CS0_AXI */ "", 33395 /* ICFG_IPROCPERIPH_SPIS0 */ "", 33396 /* ICFG_IPROCPERIPH_SPIS0_AXI */ "", 33397 /* ICFG_IPROCPERIPH_SW_RST */ "", 33398 /* ICFG_IPROC_INT_ENABLE_WR1B_MODE */ "", 33399 /* ICFG_IPROC_IOPAD_CTRL_0 */ "", 33400 /* ICFG_IPROC_IOPAD_CTRL_1 */ "", 33401 /* ICFG_IPROC_IOPAD_CTRL_2 */ "", 33402 /* ICFG_IPROC_IOPAD_CTRL_3 */ "", 33403 /* ICFG_IPROC_IOPAD_CTRL_4 */ "", 33404 /* ICFG_IPROC_IOPAD_CTRL_5 */ "", 33405 /* ICFG_IPROC_IOPAD_CTRL_6 */ "", 33406 /* ICFG_IPROC_IOPAD_CTRL_7 */ "", 33407 /* ICFG_IPROC_IOPAD_CTRL_8 */ "", 33408 /* ICFG_IPROC_IOPAD_CTRL_9 */ "", 33409 /* ICFG_IPROC_IOPAD_CTRL_10 */ "", 33410 /* ICFG_IPROC_IOPAD_CTRL_11 */ "", 33411 /* ICFG_IPROC_IOPAD_CTRL_12 */ "", 33412 /* ICFG_IPROC_IOPAD_CTRL_13 */ "", 33413 /* ICFG_IPROC_IOPAD_CTRL_14 */ "", 33414 /* ICFG_IPROC_IOPAD_CTRL_15 */ "", 33415 /* ICFG_IPROC_IOPAD_CTRL_16 */ "", 33416 /* ICFG_IPROC_IOPAD_CTRL_17 */ "", 33417 /* ICFG_IPROC_IOPAD_CTRL_18 */ "", 33418 /* ICFG_IPROC_IOPAD_CTRL_19 */ "", 33419 /* ICFG_IPROC_IOPAD_CTRL_20 */ "", 33420 /* ICFG_IPROC_IOPAD_CTRL_21 */ "", 33421 /* ICFG_IPROC_IOPAD_CTRL_22 */ "", 33422 /* ICFG_IPROC_IOPAD_SW_OVERRIDE_CTRL */ "", 33423 /* ICFG_IP_CONTROL_CLK_EN */ "", 33424 /* ICFG_IP_CONTROL_SOFT_RESET */ "", 33425 /* ICFG_IP_DISABLE_STRAP_STATUS_0 */ "", 33426 /* ICFG_IP_DISABLE_STRAP_STATUS_1 */ "", 33427 /* ICFG_IP_REVID_0 */ "", 33428 /* ICFG_IP_REVID_1 */ "", 33429 /* ICFG_IP_REVID_2 */ "", 33430 /* ICFG_IP_REVID_3 */ "", 33431 /* ICFG_IP_REVID_4 */ "", 33432 /* ICFG_IP_REVID_5 */ "", 33433 /* ICFG_IP_REVID_6 */ "", 33434 /* ICFG_IP_REVID_7 */ "", 33435 /* ICFG_MEM_ECC_CTRL */ "", 33436 /* ICFG_MHOST0_STRAPS */ "", 33437 /* ICFG_MHOST0_SW_PROG_INTR */ "", 33438 /* ICFG_MHOST1_STRAPS */ "", 33439 /* ICFG_MHOST1_SW_PROG_INTR */ "", 33440 /* ICFG_MISC_SW_RST */ "", 33441 /* ICFG_MSIX_TABLE */ "", 33442 /* ICFG_NAND_CONFIG_0 */ "", 33443 /* ICFG_NAND_CONFIG_1 */ "", 33444 /* ICFG_NAND_CONFIG_2 */ "", 33445 /* ICFG_NAND_ECC_CTR */ "", 33446 /* ICFG_NAND_ECC_ERR_ADDR */ "", 33447 /* ICFG_NAND_ECC_STAT */ "", 33448 /* ICFG_NAND_S0_IDM_IO_CONTROL_DIRECT */ "", 33449 /* ICFG_NAND_S0_IDM_IO_STATUS */ "", 33450 /* ICFG_PAXB_0_RD_CMPL_BUF_0_MEM_CTRL */ "", 33451 /* ICFG_PAXB_0_RD_CMPL_BUF_1_MEM_CTRL */ "", 33452 /* ICFG_PAXB_0_RX_RD_CPL_BUF_MEM_CTRL */ "", 33453 /* ICFG_PAXB_0_RX_WR_DATA_BUF_MEM_CTRL */ "", 33454 /* ICFG_PAXB_0_WR_DATA_BUF_MEM_CTRL */ "", 33455 /* ICFG_PAXB_1_RD_CMPL_BUF_0_MEM_CTRL */ "", 33456 /* ICFG_PAXB_1_RD_CMPL_BUF_1_MEM_CTRL */ "", 33457 /* ICFG_PAXB_1_WR_DATA_BUF_MEM_CTRL */ "", 33458 /* ICFG_PCIE64B_ACCESS_MSB_31TO24 */ "", 33459 /* ICFG_PCIE64B_ACCESS_MSB_63TO32 */ "", 33460 /* ICFG_PCIE_0_DEBUG_BUF_MEM_CTRL */ "", 33461 /* ICFG_PCIE_0_DL_TO_TL_BUF_MEM_CTRL */ "", 33462 /* ICFG_PCIE_0_REPLAY_ADDR_BUF_MEM_CTRL */ "", 33463 /* ICFG_PCIE_0_REPLAY_DATA_BUF_MEM_CTRL */ "", 33464 /* ICFG_PCIE_0_STRAPS */ "", 33465 /* ICFG_PCIE_0_TL_TO_DL_BUF_MEM_CTRL */ "", 33466 /* ICFG_PCIE_1_DL_TO_TL_BUF_MEM_CTRL */ "", 33467 /* ICFG_PCIE_1_REPLAY_ADDR_BUF_MEM_CTRL */ "", 33468 /* ICFG_PCIE_1_REPLAY_DATA_BUF_MEM_CTRL */ "", 33469 /* ICFG_PCIE_1_STRAPS */ "", 33470 /* ICFG_PCIE_1_TL_TO_DL_BUF_MEM_CTRL */ "", 33471 /* ICFG_PCIE_SW_PROG_INTR */ "", 33472 /* ICFG_PCIE_SW_PROG_INTR_CLR */ "", 33473 /* ICFG_PCIE_SW_PROG_INTR_SET */ "", 33474 /* ICFG_PERIPHNIC */ "", 33475 /* ICFG_PKA_ECC_CTRL_REG1 */ "", 33476 /* ICFG_PKA_ECC_STAT_REG2 */ "", 33477 /* ICFG_PKA_ECC_STAT_REG3 */ "", 33478 /* ICFG_PKA_ECC_STAT_REG4 */ "", 33479 /* ICFG_PKA_MEM_CTRL */ "", 33480 /* ICFG_PNOR_CONFIG_CS_0 */ "", 33481 /* ICFG_PNOR_CONFIG_CS_1 */ "", 33482 /* ICFG_PNOR_CONFIG_CS_2 */ "", 33483 /* ICFG_PNOR_STRAPS */ "", 33484 /* ICFG_QSPI_S0_IDM_IO_CONTROL_DIRECT */ "", 33485 /* ICFG_QSPI_S0_IDM_IO_STATUS */ "", 33486 /* ICFG_ROM_S0_IDM_IO_CONTROL_DIRECT */ "", 33487 /* ICFG_ROM_S0_IDM_IO_STATUS */ "", 33488 /* ICFG_ROM_STRAPS */ "", 33489 /* ICFG_SDIO0_STRAPSTATUS_0 */ "", 33490 /* ICFG_SDIO0_STRAPSTATUS_1 */ "", 33491 /* ICFG_SDIO0_STRAPSTATUS_2 */ "", 33492 /* ICFG_SDIO0_STRAPSTATUS_3 */ "", 33493 /* ICFG_SDIO0_STRAPSTATUS_4 */ "", 33494 /* ICFG_SDIO0_STRAPSTATUS_5 */ "", 33495 /* ICFG_SDIO1_STRAPSTATUS_0 */ "", 33496 /* ICFG_SDIO1_STRAPSTATUS_1 */ "", 33497 /* ICFG_SDIO1_STRAPSTATUS_2 */ "", 33498 /* ICFG_SDIO1_STRAPSTATUS_3 */ "", 33499 /* ICFG_SDIO1_STRAPSTATUS_4 */ "", 33500 /* ICFG_SDIO1_STRAPSTATUS_5 */ "", 33501 /* ICFG_SDIO_CONFIG_0 */ "", 33502 /* ICFG_SDIO_CONFIG_1 */ "", 33503 /* ICFG_SER_CONTROL */ "", 33504 /* ICFG_SEU_FID */ "", 33505 /* ICFG_SOTP_CONFIG_0 */ "", 33506 /* ICFG_USB2D_CONFIG_0 */ "", 33507 /* ICFG_USB2D_CONFIG_1 */ "", 33508 /* ICFG_USB2D_CONFIG_2 */ "", 33509 /* ICFG_USB_BDC_DBG_REG1 */ "", 33510 /* ICFG_USB_BDC_DBG_REG2 */ "", 33511 /* ICFG_USB_BDC_ECC_CTRL_REG1 */ "", 33512 /* ICFG_USB_BDC_ECC_STAT_REG2 */ "", 33513 /* ICFG_USB_BDC_ECC_STAT_REG3 */ "", 33514 /* ICFG_USB_BDC_ECC_STAT_REG4 */ "", 33515 /* ICFG_USB_BDC_STAT */ "", 33516 /* ICFG_USB_CTRL */ "", 33517 /* ICFG_USB_CTRL2 */ "", 33518 /* ICFG_USB_DRD_DBG_REG1 */ "", 33519 /* ICFG_USB_DRD_DBG_REG2 */ "", 33520 /* ICFG_USB_PHY_CTRL */ "", 33521 /* ICFG_USB_STAT */ "", 33522 /* ICFG_USB_XHC_DBG_REG1 */ "", 33523 /* ICFG_USB_XHC_DBG_REG2 */ "", 33524 /* ICFG_USB_XHC_ECC_CTRL_REG1 */ "", 33525 /* ICFG_USB_XHC_ECC_CTRL_REG2 */ "", 33526 /* ICFG_USB_XHC_ECC_STAT_REG3 */ "", 33527 /* ICFG_USB_XHC_ECC_STAT_REG4 */ "", 33528 /* ICFG_USB_XHC_ECC_STAT_REG5 */ "", 33529 /* ICFG_USB_XHC_ECC_STAT_REG6 */ "", 33530 /* ICFG_USB_XHC_ECC_STAT_REG7 */ "", 33531 /* ICFG_USB_XHC_STAT */ "", 33532 /* ICHCTL_CHID_0 */ "", 33533 /* ICHCTL_CHID_1 */ "", 33534 /* ICHCTL_CHID_2 */ "", 33535 /* ICHCTL_CHID_3 */ "", 33536 /* ICHCTL_CHID_4 */ "", 33537 /* ICHCTL_CHID_5 */ "", 33538 /* ICHCTL_CHID_6 */ "", 33539 /* ICHCTL_CHID_7 */ "", 33540 /* ICHCTL_CHID_8 */ "", 33541 /* ICHCTL_CHID_9 */ "", 33542 /* ICHCTL_CHID_10 */ "", 33543 /* ICHCTL_CHID_11 */ "", 33544 /* ICHCTL_CHID_12 */ "", 33545 /* ICHCTL_CHID_13 */ "", 33546 /* ICHCTL_CHID_14 */ "", 33547 /* ICHCTL_CHID_15 */ "", 33548 /* ICHCTL_CHID_16 */ "", 33549 /* ICHCTL_CHID_17 */ "", 33550 /* ICHCTL_CHID_18 */ "", 33551 /* ICHCTL_CHID_19 */ "", 33552 /* ICHCTL_CHID_20 */ "", 33553 /* ICHCTL_CHID_21 */ "", 33554 /* ICHCTL_CHID_22 */ "", 33555 /* ICHCTL_CHID_23 */ "", 33556 /* ICHCTL_CHID_24 */ "", 33557 /* ICHCTL_CHID_25 */ "", 33558 /* ICHCTL_CHID_26 */ "", 33559 /* ICHCTL_CHID_27 */ "", 33560 /* ICHCTL_CHID_28 */ "", 33561 /* ICHCTL_CHID_29 */ "", 33562 /* ICHCTL_CHID_30 */ "", 33563 /* ICHCTL_CHID_31 */ "", 33564 /* ICHCTL_CHID_32 */ "", 33565 /* ICHCTL_CHID_33 */ "", 33566 /* ICHCTL_CHID_34 */ "", 33567 /* ICHCTL_CHID_35 */ "", 33568 /* ICHCTL_CHID_36 */ "", 33569 /* ICHCTL_CHID_37 */ "", 33570 /* ICHCTL_CHID_38 */ "", 33571 /* ICHCTL_CHID_39 */ "", 33572 /* ICHCTL_CHID_40 */ "", 33573 /* ICHCTL_CHID_41 */ "", 33574 /* ICHCTL_CHID_42 */ "", 33575 /* ICHCTL_CHID_43 */ "", 33576 /* ICHCTL_CHID_44 */ "", 33577 /* ICHCTL_CHID_45 */ "", 33578 /* ICHCTL_CHID_46 */ "", 33579 /* ICHCTL_CHID_47 */ "", 33580 /* ICHCTL_CHID_48 */ "", 33581 /* ICHCTL_CHID_49 */ "", 33582 /* ICHCTL_CHID_50 */ "", 33583 /* ICHCTL_CHID_51 */ "", 33584 /* ICHCTL_CHID_52 */ "", 33585 /* ICHCTL_CHID_53 */ "", 33586 /* ICHCTL_CHID_54 */ "", 33587 /* ICHCTL_CHID_55 */ "", 33588 /* ICHCTL_CHID_56 */ "", 33589 /* ICHCTL_CHID_57 */ "", 33590 /* ICHCTL_CHID_58 */ "", 33591 /* ICHCTL_CHID_59 */ "", 33592 /* ICHCTL_CHID_60 */ "", 33593 /* ICHCTL_CHID_61 */ "", 33594 /* ICHCTL_CHID_62 */ "", 33595 /* ICHCTL_CHID_63 */ "", 33596 /* ICMAP0_CID_0 */ "", 33597 /* ICMAP0_CID_1 */ "", 33598 /* ICMAP0_CID_2 */ "", 33599 /* ICMAP0_CID_3 */ "", 33600 /* ICMAP0_CID_4 */ "", 33601 /* ICMAP0_CID_5 */ "", 33602 /* ICMAP0_CID_6 */ "", 33603 /* ICMAP0_CID_7 */ "", 33604 /* ICMAP0_CID_8 */ "", 33605 /* ICMAP0_CID_9 */ "", 33606 /* ICMAP0_CID_10 */ "", 33607 /* ICMAP0_CID_11 */ "", 33608 /* ICMAP0_CID_12 */ "", 33609 /* ICMAP0_CID_13 */ "", 33610 /* ICMAP0_CID_14 */ "", 33611 /* ICMAP0_CID_15 */ "", 33612 /* ICMAP10_CID_0 */ "", 33613 /* ICMAP10_CID_1 */ "", 33614 /* ICMAP10_CID_2 */ "", 33615 /* ICMAP10_CID_3 */ "", 33616 /* ICMAP10_CID_4 */ "", 33617 /* ICMAP10_CID_5 */ "", 33618 /* ICMAP10_CID_6 */ "", 33619 /* ICMAP10_CID_7 */ "", 33620 /* ICMAP10_CID_8 */ "", 33621 /* ICMAP10_CID_9 */ "", 33622 /* ICMAP10_CID_10 */ "", 33623 /* ICMAP10_CID_11 */ "", 33624 /* ICMAP10_CID_12 */ "", 33625 /* ICMAP10_CID_13 */ "", 33626 /* ICMAP10_CID_14 */ "", 33627 /* ICMAP10_CID_15 */ "", 33628 /* ICMAP11_CID_0 */ "", 33629 /* ICMAP11_CID_1 */ "", 33630 /* ICMAP11_CID_2 */ "", 33631 /* ICMAP11_CID_3 */ "", 33632 /* ICMAP11_CID_4 */ "", 33633 /* ICMAP11_CID_5 */ "", 33634 /* ICMAP11_CID_6 */ "", 33635 /* ICMAP11_CID_7 */ "", 33636 /* ICMAP11_CID_8 */ "", 33637 /* ICMAP11_CID_9 */ "", 33638 /* ICMAP11_CID_10 */ "", 33639 /* ICMAP11_CID_11 */ "", 33640 /* ICMAP11_CID_12 */ "", 33641 /* ICMAP11_CID_13 */ "", 33642 /* ICMAP11_CID_14 */ "", 33643 /* ICMAP11_CID_15 */ "", 33644 /* ICMAP12_CID_0 */ "", 33645 /* ICMAP12_CID_1 */ "", 33646 /* ICMAP12_CID_2 */ "", 33647 /* ICMAP12_CID_3 */ "", 33648 /* ICMAP12_CID_4 */ "", 33649 /* ICMAP12_CID_5 */ "", 33650 /* ICMAP12_CID_6 */ "", 33651 /* ICMAP12_CID_7 */ "", 33652 /* ICMAP12_CID_8 */ "", 33653 /* ICMAP12_CID_9 */ "", 33654 /* ICMAP12_CID_10 */ "", 33655 /* ICMAP12_CID_11 */ "", 33656 /* ICMAP12_CID_12 */ "", 33657 /* ICMAP12_CID_13 */ "", 33658 /* ICMAP12_CID_14 */ "", 33659 /* ICMAP12_CID_15 */ "", 33660 /* ICMAP13_CID_0 */ "", 33661 /* ICMAP13_CID_1 */ "", 33662 /* ICMAP13_CID_2 */ "", 33663 /* ICMAP13_CID_3 */ "", 33664 /* ICMAP13_CID_4 */ "", 33665 /* ICMAP13_CID_5 */ "", 33666 /* ICMAP13_CID_6 */ "", 33667 /* ICMAP13_CID_7 */ "", 33668 /* ICMAP13_CID_8 */ "", 33669 /* ICMAP13_CID_9 */ "", 33670 /* ICMAP13_CID_10 */ "", 33671 /* ICMAP13_CID_11 */ "", 33672 /* ICMAP13_CID_12 */ "", 33673 /* ICMAP13_CID_13 */ "", 33674 /* ICMAP13_CID_14 */ "", 33675 /* ICMAP13_CID_15 */ "", 33676 /* ICMAP14_CID_0 */ "", 33677 /* ICMAP14_CID_1 */ "", 33678 /* ICMAP14_CID_2 */ "", 33679 /* ICMAP14_CID_3 */ "", 33680 /* ICMAP14_CID_4 */ "", 33681 /* ICMAP14_CID_5 */ "", 33682 /* ICMAP14_CID_6 */ "", 33683 /* ICMAP14_CID_7 */ "", 33684 /* ICMAP14_CID_8 */ "", 33685 /* ICMAP14_CID_9 */ "", 33686 /* ICMAP14_CID_10 */ "", 33687 /* ICMAP14_CID_11 */ "", 33688 /* ICMAP14_CID_12 */ "", 33689 /* ICMAP14_CID_13 */ "", 33690 /* ICMAP14_CID_14 */ "", 33691 /* ICMAP14_CID_15 */ "", 33692 /* ICMAP15_CID_0 */ "", 33693 /* ICMAP15_CID_1 */ "", 33694 /* ICMAP15_CID_2 */ "", 33695 /* ICMAP15_CID_3 */ "", 33696 /* ICMAP15_CID_4 */ "", 33697 /* ICMAP15_CID_5 */ "", 33698 /* ICMAP15_CID_6 */ "", 33699 /* ICMAP15_CID_7 */ "", 33700 /* ICMAP15_CID_8 */ "", 33701 /* ICMAP15_CID_9 */ "", 33702 /* ICMAP15_CID_10 */ "", 33703 /* ICMAP15_CID_11 */ "", 33704 /* ICMAP15_CID_12 */ "", 33705 /* ICMAP15_CID_13 */ "", 33706 /* ICMAP15_CID_14 */ "", 33707 /* ICMAP15_CID_15 */ "", 33708 /* ICMAP16_CID_0 */ "", 33709 /* ICMAP16_CID_1 */ "", 33710 /* ICMAP16_CID_2 */ "", 33711 /* ICMAP16_CID_3 */ "", 33712 /* ICMAP16_CID_4 */ "", 33713 /* ICMAP16_CID_5 */ "", 33714 /* ICMAP16_CID_6 */ "", 33715 /* ICMAP16_CID_7 */ "", 33716 /* ICMAP16_CID_8 */ "", 33717 /* ICMAP16_CID_9 */ "", 33718 /* ICMAP16_CID_10 */ "", 33719 /* ICMAP16_CID_11 */ "", 33720 /* ICMAP16_CID_12 */ "", 33721 /* ICMAP16_CID_13 */ "", 33722 /* ICMAP16_CID_14 */ "", 33723 /* ICMAP16_CID_15 */ "", 33724 /* ICMAP17_CID_0 */ "", 33725 /* ICMAP17_CID_1 */ "", 33726 /* ICMAP17_CID_2 */ "", 33727 /* ICMAP17_CID_3 */ "", 33728 /* ICMAP17_CID_4 */ "", 33729 /* ICMAP17_CID_5 */ "", 33730 /* ICMAP17_CID_6 */ "", 33731 /* ICMAP17_CID_7 */ "", 33732 /* ICMAP17_CID_8 */ "", 33733 /* ICMAP17_CID_9 */ "", 33734 /* ICMAP17_CID_10 */ "", 33735 /* ICMAP17_CID_11 */ "", 33736 /* ICMAP17_CID_12 */ "", 33737 /* ICMAP17_CID_13 */ "", 33738 /* ICMAP17_CID_14 */ "", 33739 /* ICMAP17_CID_15 */ "", 33740 /* ICMAP18_CID_0 */ "", 33741 /* ICMAP18_CID_1 */ "", 33742 /* ICMAP18_CID_2 */ "", 33743 /* ICMAP18_CID_3 */ "", 33744 /* ICMAP18_CID_4 */ "", 33745 /* ICMAP18_CID_5 */ "", 33746 /* ICMAP18_CID_6 */ "", 33747 /* ICMAP18_CID_7 */ "", 33748 /* ICMAP18_CID_8 */ "", 33749 /* ICMAP18_CID_9 */ "", 33750 /* ICMAP18_CID_10 */ "", 33751 /* ICMAP18_CID_11 */ "", 33752 /* ICMAP18_CID_12 */ "", 33753 /* ICMAP18_CID_13 */ "", 33754 /* ICMAP18_CID_14 */ "", 33755 /* ICMAP18_CID_15 */ "", 33756 /* ICMAP19_CID_0 */ "", 33757 /* ICMAP19_CID_1 */ "", 33758 /* ICMAP19_CID_2 */ "", 33759 /* ICMAP19_CID_3 */ "", 33760 /* ICMAP19_CID_4 */ "", 33761 /* ICMAP19_CID_5 */ "", 33762 /* ICMAP19_CID_6 */ "", 33763 /* ICMAP19_CID_7 */ "", 33764 /* ICMAP19_CID_8 */ "", 33765 /* ICMAP19_CID_9 */ "", 33766 /* ICMAP19_CID_10 */ "", 33767 /* ICMAP19_CID_11 */ "", 33768 /* ICMAP19_CID_12 */ "", 33769 /* ICMAP19_CID_13 */ "", 33770 /* ICMAP19_CID_14 */ "", 33771 /* ICMAP19_CID_15 */ "", 33772 /* ICMAP1_CID_0 */ "", 33773 /* ICMAP1_CID_1 */ "", 33774 /* ICMAP1_CID_2 */ "", 33775 /* ICMAP1_CID_3 */ "", 33776 /* ICMAP1_CID_4 */ "", 33777 /* ICMAP1_CID_5 */ "", 33778 /* ICMAP1_CID_6 */ "", 33779 /* ICMAP1_CID_7 */ "", 33780 /* ICMAP1_CID_8 */ "", 33781 /* ICMAP1_CID_9 */ "", 33782 /* ICMAP1_CID_10 */ "", 33783 /* ICMAP1_CID_11 */ "", 33784 /* ICMAP1_CID_12 */ "", 33785 /* ICMAP1_CID_13 */ "", 33786 /* ICMAP1_CID_14 */ "", 33787 /* ICMAP1_CID_15 */ "", 33788 /* ICMAP20_CID_0 */ "", 33789 /* ICMAP20_CID_1 */ "", 33790 /* ICMAP20_CID_2 */ "", 33791 /* ICMAP20_CID_3 */ "", 33792 /* ICMAP20_CID_4 */ "", 33793 /* ICMAP20_CID_5 */ "", 33794 /* ICMAP20_CID_6 */ "", 33795 /* ICMAP20_CID_7 */ "", 33796 /* ICMAP20_CID_8 */ "", 33797 /* ICMAP20_CID_9 */ "", 33798 /* ICMAP20_CID_10 */ "", 33799 /* ICMAP20_CID_11 */ "", 33800 /* ICMAP20_CID_12 */ "", 33801 /* ICMAP20_CID_13 */ "", 33802 /* ICMAP20_CID_14 */ "", 33803 /* ICMAP20_CID_15 */ "", 33804 /* ICMAP21_CID_0 */ "", 33805 /* ICMAP21_CID_1 */ "", 33806 /* ICMAP21_CID_2 */ "", 33807 /* ICMAP21_CID_3 */ "", 33808 /* ICMAP21_CID_4 */ "", 33809 /* ICMAP21_CID_5 */ "", 33810 /* ICMAP21_CID_6 */ "", 33811 /* ICMAP21_CID_7 */ "", 33812 /* ICMAP21_CID_8 */ "", 33813 /* ICMAP21_CID_9 */ "", 33814 /* ICMAP21_CID_10 */ "", 33815 /* ICMAP21_CID_11 */ "", 33816 /* ICMAP21_CID_12 */ "", 33817 /* ICMAP21_CID_13 */ "", 33818 /* ICMAP21_CID_14 */ "", 33819 /* ICMAP21_CID_15 */ "", 33820 /* ICMAP22_CID_0 */ "", 33821 /* ICMAP22_CID_1 */ "", 33822 /* ICMAP22_CID_2 */ "", 33823 /* ICMAP22_CID_3 */ "", 33824 /* ICMAP22_CID_4 */ "", 33825 /* ICMAP22_CID_5 */ "", 33826 /* ICMAP22_CID_6 */ "", 33827 /* ICMAP22_CID_7 */ "", 33828 /* ICMAP22_CID_8 */ "", 33829 /* ICMAP22_CID_9 */ "", 33830 /* ICMAP22_CID_10 */ "", 33831 /* ICMAP22_CID_11 */ "", 33832 /* ICMAP22_CID_12 */ "", 33833 /* ICMAP22_CID_13 */ "", 33834 /* ICMAP22_CID_14 */ "", 33835 /* ICMAP22_CID_15 */ "", 33836 /* ICMAP23_CID_0 */ "", 33837 /* ICMAP23_CID_1 */ "", 33838 /* ICMAP23_CID_2 */ "", 33839 /* ICMAP23_CID_3 */ "", 33840 /* ICMAP23_CID_4 */ "", 33841 /* ICMAP23_CID_5 */ "", 33842 /* ICMAP23_CID_6 */ "", 33843 /* ICMAP23_CID_7 */ "", 33844 /* ICMAP23_CID_8 */ "", 33845 /* ICMAP23_CID_9 */ "", 33846 /* ICMAP23_CID_10 */ "", 33847 /* ICMAP23_CID_11 */ "", 33848 /* ICMAP23_CID_12 */ "", 33849 /* ICMAP23_CID_13 */ "", 33850 /* ICMAP23_CID_14 */ "", 33851 /* ICMAP23_CID_15 */ "", 33852 /* ICMAP24_CID_0 */ "", 33853 /* ICMAP24_CID_1 */ "", 33854 /* ICMAP24_CID_2 */ "", 33855 /* ICMAP24_CID_3 */ "", 33856 /* ICMAP24_CID_4 */ "", 33857 /* ICMAP24_CID_5 */ "", 33858 /* ICMAP24_CID_6 */ "", 33859 /* ICMAP24_CID_7 */ "", 33860 /* ICMAP24_CID_8 */ "", 33861 /* ICMAP24_CID_9 */ "", 33862 /* ICMAP24_CID_10 */ "", 33863 /* ICMAP24_CID_11 */ "", 33864 /* ICMAP24_CID_12 */ "", 33865 /* ICMAP24_CID_13 */ "", 33866 /* ICMAP24_CID_14 */ "", 33867 /* ICMAP24_CID_15 */ "", 33868 /* ICMAP25_CID_0 */ "", 33869 /* ICMAP25_CID_1 */ "", 33870 /* ICMAP25_CID_2 */ "", 33871 /* ICMAP25_CID_3 */ "", 33872 /* ICMAP25_CID_4 */ "", 33873 /* ICMAP25_CID_5 */ "", 33874 /* ICMAP25_CID_6 */ "", 33875 /* ICMAP25_CID_7 */ "", 33876 /* ICMAP25_CID_8 */ "", 33877 /* ICMAP25_CID_9 */ "", 33878 /* ICMAP25_CID_10 */ "", 33879 /* ICMAP25_CID_11 */ "", 33880 /* ICMAP25_CID_12 */ "", 33881 /* ICMAP25_CID_13 */ "", 33882 /* ICMAP25_CID_14 */ "", 33883 /* ICMAP25_CID_15 */ "", 33884 /* ICMAP26_CID_0 */ "", 33885 /* ICMAP26_CID_1 */ "", 33886 /* ICMAP26_CID_2 */ "", 33887 /* ICMAP26_CID_3 */ "", 33888 /* ICMAP26_CID_4 */ "", 33889 /* ICMAP26_CID_5 */ "", 33890 /* ICMAP26_CID_6 */ "", 33891 /* ICMAP26_CID_7 */ "", 33892 /* ICMAP26_CID_8 */ "", 33893 /* ICMAP26_CID_9 */ "", 33894 /* ICMAP26_CID_10 */ "", 33895 /* ICMAP26_CID_11 */ "", 33896 /* ICMAP26_CID_12 */ "", 33897 /* ICMAP26_CID_13 */ "", 33898 /* ICMAP26_CID_14 */ "", 33899 /* ICMAP26_CID_15 */ "", 33900 /* ICMAP27_CID_0 */ "", 33901 /* ICMAP27_CID_1 */ "", 33902 /* ICMAP27_CID_2 */ "", 33903 /* ICMAP27_CID_3 */ "", 33904 /* ICMAP27_CID_4 */ "", 33905 /* ICMAP27_CID_5 */ "", 33906 /* ICMAP27_CID_6 */ "", 33907 /* ICMAP27_CID_7 */ "", 33908 /* ICMAP27_CID_8 */ "", 33909 /* ICMAP27_CID_9 */ "", 33910 /* ICMAP27_CID_10 */ "", 33911 /* ICMAP27_CID_11 */ "", 33912 /* ICMAP27_CID_12 */ "", 33913 /* ICMAP27_CID_13 */ "", 33914 /* ICMAP27_CID_14 */ "", 33915 /* ICMAP27_CID_15 */ "", 33916 /* ICMAP28_CID_0 */ "", 33917 /* ICMAP28_CID_1 */ "", 33918 /* ICMAP28_CID_2 */ "", 33919 /* ICMAP28_CID_3 */ "", 33920 /* ICMAP28_CID_4 */ "", 33921 /* ICMAP28_CID_5 */ "", 33922 /* ICMAP28_CID_6 */ "", 33923 /* ICMAP28_CID_7 */ "", 33924 /* ICMAP28_CID_8 */ "", 33925 /* ICMAP28_CID_9 */ "", 33926 /* ICMAP28_CID_10 */ "", 33927 /* ICMAP28_CID_11 */ "", 33928 /* ICMAP28_CID_12 */ "", 33929 /* ICMAP28_CID_13 */ "", 33930 /* ICMAP28_CID_14 */ "", 33931 /* ICMAP28_CID_15 */ "", 33932 /* ICMAP29_CID_0 */ "", 33933 /* ICMAP29_CID_1 */ "", 33934 /* ICMAP29_CID_2 */ "", 33935 /* ICMAP29_CID_3 */ "", 33936 /* ICMAP29_CID_4 */ "", 33937 /* ICMAP29_CID_5 */ "", 33938 /* ICMAP29_CID_6 */ "", 33939 /* ICMAP29_CID_7 */ "", 33940 /* ICMAP29_CID_8 */ "", 33941 /* ICMAP29_CID_9 */ "", 33942 /* ICMAP29_CID_10 */ "", 33943 /* ICMAP29_CID_11 */ "", 33944 /* ICMAP29_CID_12 */ "", 33945 /* ICMAP29_CID_13 */ "", 33946 /* ICMAP29_CID_14 */ "", 33947 /* ICMAP29_CID_15 */ "", 33948 /* ICMAP2_CID_0 */ "", 33949 /* ICMAP2_CID_1 */ "", 33950 /* ICMAP2_CID_2 */ "", 33951 /* ICMAP2_CID_3 */ "", 33952 /* ICMAP2_CID_4 */ "", 33953 /* ICMAP2_CID_5 */ "", 33954 /* ICMAP2_CID_6 */ "", 33955 /* ICMAP2_CID_7 */ "", 33956 /* ICMAP2_CID_8 */ "", 33957 /* ICMAP2_CID_9 */ "", 33958 /* ICMAP2_CID_10 */ "", 33959 /* ICMAP2_CID_11 */ "", 33960 /* ICMAP2_CID_12 */ "", 33961 /* ICMAP2_CID_13 */ "", 33962 /* ICMAP2_CID_14 */ "", 33963 /* ICMAP2_CID_15 */ "", 33964 /* ICMAP30_CID_0 */ "", 33965 /* ICMAP30_CID_1 */ "", 33966 /* ICMAP30_CID_2 */ "", 33967 /* ICMAP30_CID_3 */ "", 33968 /* ICMAP30_CID_4 */ "", 33969 /* ICMAP30_CID_5 */ "", 33970 /* ICMAP30_CID_6 */ "", 33971 /* ICMAP30_CID_7 */ "", 33972 /* ICMAP30_CID_8 */ "", 33973 /* ICMAP30_CID_9 */ "", 33974 /* ICMAP30_CID_10 */ "", 33975 /* ICMAP30_CID_11 */ "", 33976 /* ICMAP30_CID_12 */ "", 33977 /* ICMAP30_CID_13 */ "", 33978 /* ICMAP30_CID_14 */ "", 33979 /* ICMAP30_CID_15 */ "", 33980 /* ICMAP31_CID_0 */ "", 33981 /* ICMAP31_CID_1 */ "", 33982 /* ICMAP31_CID_2 */ "", 33983 /* ICMAP31_CID_3 */ "", 33984 /* ICMAP31_CID_4 */ "", 33985 /* ICMAP31_CID_5 */ "", 33986 /* ICMAP31_CID_6 */ "", 33987 /* ICMAP31_CID_7 */ "", 33988 /* ICMAP31_CID_8 */ "", 33989 /* ICMAP31_CID_9 */ "", 33990 /* ICMAP31_CID_10 */ "", 33991 /* ICMAP31_CID_11 */ "", 33992 /* ICMAP31_CID_12 */ "", 33993 /* ICMAP31_CID_13 */ "", 33994 /* ICMAP31_CID_14 */ "", 33995 /* ICMAP31_CID_15 */ "", 33996 /* ICMAP3_CID_0 */ "", 33997 /* ICMAP3_CID_1 */ "", 33998 /* ICMAP3_CID_2 */ "", 33999 /* ICMAP3_CID_3 */ "", 34000 /* ICMAP3_CID_4 */ "", 34001 /* ICMAP3_CID_5 */ "", 34002 /* ICMAP3_CID_6 */ "", 34003 /* ICMAP3_CID_7 */ "", 34004 /* ICMAP3_CID_8 */ "", 34005 /* ICMAP3_CID_9 */ "", 34006 /* ICMAP3_CID_10 */ "", 34007 /* ICMAP3_CID_11 */ "", 34008 /* ICMAP3_CID_12 */ "", 34009 /* ICMAP3_CID_13 */ "", 34010 /* ICMAP3_CID_14 */ "", 34011 /* ICMAP3_CID_15 */ "", 34012 /* ICMAP4_CID_0 */ "", 34013 /* ICMAP4_CID_1 */ "", 34014 /* ICMAP4_CID_2 */ "", 34015 /* ICMAP4_CID_3 */ "", 34016 /* ICMAP4_CID_4 */ "", 34017 /* ICMAP4_CID_5 */ "", 34018 /* ICMAP4_CID_6 */ "", 34019 /* ICMAP4_CID_7 */ "", 34020 /* ICMAP4_CID_8 */ "", 34021 /* ICMAP4_CID_9 */ "", 34022 /* ICMAP4_CID_10 */ "", 34023 /* ICMAP4_CID_11 */ "", 34024 /* ICMAP4_CID_12 */ "", 34025 /* ICMAP4_CID_13 */ "", 34026 /* ICMAP4_CID_14 */ "", 34027 /* ICMAP4_CID_15 */ "", 34028 /* ICMAP5_CID_0 */ "", 34029 /* ICMAP5_CID_1 */ "", 34030 /* ICMAP5_CID_2 */ "", 34031 /* ICMAP5_CID_3 */ "", 34032 /* ICMAP5_CID_4 */ "", 34033 /* ICMAP5_CID_5 */ "", 34034 /* ICMAP5_CID_6 */ "", 34035 /* ICMAP5_CID_7 */ "", 34036 /* ICMAP5_CID_8 */ "", 34037 /* ICMAP5_CID_9 */ "", 34038 /* ICMAP5_CID_10 */ "", 34039 /* ICMAP5_CID_11 */ "", 34040 /* ICMAP5_CID_12 */ "", 34041 /* ICMAP5_CID_13 */ "", 34042 /* ICMAP5_CID_14 */ "", 34043 /* ICMAP5_CID_15 */ "", 34044 /* ICMAP6_CID_0 */ "", 34045 /* ICMAP6_CID_1 */ "", 34046 /* ICMAP6_CID_2 */ "", 34047 /* ICMAP6_CID_3 */ "", 34048 /* ICMAP6_CID_4 */ "", 34049 /* ICMAP6_CID_5 */ "", 34050 /* ICMAP6_CID_6 */ "", 34051 /* ICMAP6_CID_7 */ "", 34052 /* ICMAP6_CID_8 */ "", 34053 /* ICMAP6_CID_9 */ "", 34054 /* ICMAP6_CID_10 */ "", 34055 /* ICMAP6_CID_11 */ "", 34056 /* ICMAP6_CID_12 */ "", 34057 /* ICMAP6_CID_13 */ "", 34058 /* ICMAP6_CID_14 */ "", 34059 /* ICMAP6_CID_15 */ "", 34060 /* ICMAP7_CID_0 */ "", 34061 /* ICMAP7_CID_1 */ "", 34062 /* ICMAP7_CID_2 */ "", 34063 /* ICMAP7_CID_3 */ "", 34064 /* ICMAP7_CID_4 */ "", 34065 /* ICMAP7_CID_5 */ "", 34066 /* ICMAP7_CID_6 */ "", 34067 /* ICMAP7_CID_7 */ "", 34068 /* ICMAP7_CID_8 */ "", 34069 /* ICMAP7_CID_9 */ "", 34070 /* ICMAP7_CID_10 */ "", 34071 /* ICMAP7_CID_11 */ "", 34072 /* ICMAP7_CID_12 */ "", 34073 /* ICMAP7_CID_13 */ "", 34074 /* ICMAP7_CID_14 */ "", 34075 /* ICMAP7_CID_15 */ "", 34076 /* ICMAP8_CID_0 */ "", 34077 /* ICMAP8_CID_1 */ "", 34078 /* ICMAP8_CID_2 */ "", 34079 /* ICMAP8_CID_3 */ "", 34080 /* ICMAP8_CID_4 */ "", 34081 /* ICMAP8_CID_5 */ "", 34082 /* ICMAP8_CID_6 */ "", 34083 /* ICMAP8_CID_7 */ "", 34084 /* ICMAP8_CID_8 */ "", 34085 /* ICMAP8_CID_9 */ "", 34086 /* ICMAP8_CID_10 */ "", 34087 /* ICMAP8_CID_11 */ "", 34088 /* ICMAP8_CID_12 */ "", 34089 /* ICMAP8_CID_13 */ "", 34090 /* ICMAP8_CID_14 */ "", 34091 /* ICMAP8_CID_15 */ "", 34092 /* ICMAP9_CID_0 */ "", 34093 /* ICMAP9_CID_1 */ "", 34094 /* ICMAP9_CID_2 */ "", 34095 /* ICMAP9_CID_3 */ "", 34096 /* ICMAP9_CID_4 */ "", 34097 /* ICMAP9_CID_5 */ "", 34098 /* ICMAP9_CID_6 */ "", 34099 /* ICMAP9_CID_7 */ "", 34100 /* ICMAP9_CID_8 */ "", 34101 /* ICMAP9_CID_9 */ "", 34102 /* ICMAP9_CID_10 */ "", 34103 /* ICMAP9_CID_11 */ "", 34104 /* ICMAP9_CID_12 */ "", 34105 /* ICMAP9_CID_13 */ "", 34106 /* ICMAP9_CID_14 */ "", 34107 /* ICMAP9_CID_15 */ "", 34108 /* ICMP_ERROR_TYPE */ "", 34109 /* ICONTROL_OPCODE */ "", 34110 /* ICONTROL_OPCODE_BITMAP */ "", 34111 /* ICONTROL_OPCODE_BITMAP_64 */ "ICONTROL_OPCODE_BITMAP", 34112 /* ICONTROL_OPCODE_BITMAP_HI */ "", 34113 /* ICONTROL_OPCODE_BITMAP_LO */ "", 34114 /* ICONTROL_OPCODE_BITMAP_PARITY_CONTROL */ "ICONTROL_OPCODE_BITMAP_PARITY_CONTROL", 34115 /* ICONTROL_OPCODE_BITMAP_PARITY_STATUS_INTR */ "ICONTROL_OPCODE_BITMAP_PARITY_STATUS_INTR", 34116 /* ICONTROL_OPCODE_BITMAP_PARITY_STATUS_NACK */ "ICONTROL_OPCODE_BITMAP_PARITY_STATUS_NACK", 34117 /* ICOS_MAP_SEL */ "", 34118 /* ICOS_SEL */ "", 34119 /* ICOS_SEL_2 */ "", 34120 /* ICTRL */ "", 34121 /* ICTRL_64 */ "ICTRL", 34122 /* IDB_CA0_BUFFER_CONFIG */ "", 34123 /* IDB_CA0_BUFFER_CONFIG_PIPE0 */ "", 34124 /* IDB_CA0_BUFFER_CONFIG_PIPE1 */ "", 34125 /* IDB_CA0_BUFFER_CONFIG_PIPE2 */ "", 34126 /* IDB_CA0_BUFFER_CONFIG_PIPE3 */ "", 34127 /* IDB_CA0_BUFFER_CONFIG_PIPE4 */ "", 34128 /* IDB_CA0_BUFFER_CONFIG_PIPE5 */ "", 34129 /* IDB_CA0_BUFFER_CONFIG_PIPE6 */ "", 34130 /* IDB_CA0_BUFFER_CONFIG_PIPE7 */ "", 34131 /* IDB_CA0_CONTROL */ "IDB_CA0_CONTROL", 34132 /* IDB_CA0_CONTROL_PIPE0 */ "IDB_CA0_CONTROL_PIPE0", 34133 /* IDB_CA0_CONTROL_PIPE1 */ "IDB_CA0_CONTROL_PIPE1", 34134 /* IDB_CA0_CONTROL_PIPE2 */ "IDB_CA0_CONTROL_PIPE2", 34135 /* IDB_CA0_CONTROL_PIPE3 */ "IDB_CA0_CONTROL_PIPE3", 34136 /* IDB_CA0_CONTROL_PIPE4 */ "IDB_CA0_CONTROL_PIPE4", 34137 /* IDB_CA0_CONTROL_PIPE5 */ "IDB_CA0_CONTROL_PIPE5", 34138 /* IDB_CA0_CONTROL_PIPE6 */ "IDB_CA0_CONTROL_PIPE6", 34139 /* IDB_CA0_CONTROL_PIPE7 */ "IDB_CA0_CONTROL_PIPE7", 34140 /* IDB_CA0_CT_CONTROL */ "IDB_CA0_CT_CONTROL", 34141 /* IDB_CA0_CT_CONTROL_PIPE0 */ "IDB_CA0_CT_CONTROL_PIPE0", 34142 /* IDB_CA0_CT_CONTROL_PIPE1 */ "IDB_CA0_CT_CONTROL_PIPE1", 34143 /* IDB_CA0_CT_CONTROL_PIPE2 */ "IDB_CA0_CT_CONTROL_PIPE2", 34144 /* IDB_CA0_CT_CONTROL_PIPE3 */ "IDB_CA0_CT_CONTROL_PIPE3", 34145 /* IDB_CA0_CT_CONTROL_PIPE4 */ "IDB_CA0_CT_CONTROL_PIPE4", 34146 /* IDB_CA0_CT_CONTROL_PIPE5 */ "IDB_CA0_CT_CONTROL_PIPE5", 34147 /* IDB_CA0_CT_CONTROL_PIPE6 */ "IDB_CA0_CT_CONTROL_PIPE6", 34148 /* IDB_CA0_CT_CONTROL_PIPE7 */ "IDB_CA0_CT_CONTROL_PIPE7", 34149 /* IDB_CA0_DBG_A */ "IDB_CA0_FORCE_SAF_CONFIG", 34150 /* IDB_CA0_DBG_A_PIPE0 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE0", 34151 /* IDB_CA0_DBG_A_PIPE1 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE1", 34152 /* IDB_CA0_DBG_A_PIPE2 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE2", 34153 /* IDB_CA0_DBG_A_PIPE3 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE3", 34154 /* IDB_CA0_DBG_A_PIPE4 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE4", 34155 /* IDB_CA0_DBG_A_PIPE5 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE5", 34156 /* IDB_CA0_DBG_A_PIPE6 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE6", 34157 /* IDB_CA0_DBG_A_PIPE7 */ "IDB_CA0_FORCE_SAF_CONFIG_PIPE7", 34158 /* IDB_CA0_DBG_B */ "IDB_CA0_LAG_DETECTION_CONFIG", 34159 /* IDB_CA0_DBG_B_PIPE0 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE0", 34160 /* IDB_CA0_DBG_B_PIPE1 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE1", 34161 /* IDB_CA0_DBG_B_PIPE2 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE2", 34162 /* IDB_CA0_DBG_B_PIPE3 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE3", 34163 /* IDB_CA0_DBG_B_PIPE4 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE4", 34164 /* IDB_CA0_DBG_B_PIPE5 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE5", 34165 /* IDB_CA0_DBG_B_PIPE6 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE6", 34166 /* IDB_CA0_DBG_B_PIPE7 */ "IDB_CA0_LAG_DETECTION_CONFIG_PIPE7", 34167 /* IDB_CA0_HW_STATUS */ "IDB_CA0_HW_STATUS", 34168 /* IDB_CA0_HW_STATUS_1 */ "IDB_CA0_HW_STATUS_1", 34169 /* IDB_CA0_HW_STATUS_2 */ "IDB_CA0_HW_STATUS_2", 34170 /* IDB_CA0_HW_STATUS_1_PIPE0 */ "IDB_CA0_HW_STATUS_1_PIPE0", 34171 /* IDB_CA0_HW_STATUS_1_PIPE1 */ "IDB_CA0_HW_STATUS_1_PIPE1", 34172 /* IDB_CA0_HW_STATUS_1_PIPE2 */ "IDB_CA0_HW_STATUS_1_PIPE2", 34173 /* IDB_CA0_HW_STATUS_1_PIPE3 */ "IDB_CA0_HW_STATUS_1_PIPE3", 34174 /* IDB_CA0_HW_STATUS_1_PIPE4 */ "IDB_CA0_HW_STATUS_1_PIPE4", 34175 /* IDB_CA0_HW_STATUS_1_PIPE5 */ "IDB_CA0_HW_STATUS_1_PIPE5", 34176 /* IDB_CA0_HW_STATUS_1_PIPE6 */ "IDB_CA0_HW_STATUS_1_PIPE6", 34177 /* IDB_CA0_HW_STATUS_1_PIPE7 */ "IDB_CA0_HW_STATUS_1_PIPE7", 34178 /* IDB_CA0_HW_STATUS_2_PIPE0 */ "IDB_CA0_HW_STATUS_2_PIPE0", 34179 /* IDB_CA0_HW_STATUS_2_PIPE1 */ "IDB_CA0_HW_STATUS_2_PIPE1", 34180 /* IDB_CA0_HW_STATUS_2_PIPE2 */ "IDB_CA0_HW_STATUS_2_PIPE2", 34181 /* IDB_CA0_HW_STATUS_2_PIPE3 */ "IDB_CA0_HW_STATUS_2_PIPE3", 34182 /* IDB_CA0_HW_STATUS_2_PIPE4 */ "IDB_CA0_HW_STATUS_2_PIPE4", 34183 /* IDB_CA0_HW_STATUS_2_PIPE5 */ "IDB_CA0_HW_STATUS_2_PIPE5", 34184 /* IDB_CA0_HW_STATUS_2_PIPE6 */ "IDB_CA0_HW_STATUS_2_PIPE6", 34185 /* IDB_CA0_HW_STATUS_2_PIPE7 */ "IDB_CA0_HW_STATUS_2_PIPE7", 34186 /* IDB_CA0_HW_STATUS_PIPE0 */ "IDB_CA0_HW_STATUS_PIPE0", 34187 /* IDB_CA0_HW_STATUS_PIPE1 */ "IDB_CA0_HW_STATUS_PIPE1", 34188 /* IDB_CA0_HW_STATUS_PIPE2 */ "IDB_CA0_HW_STATUS_PIPE2", 34189 /* IDB_CA0_HW_STATUS_PIPE3 */ "IDB_CA0_HW_STATUS_PIPE3", 34190 /* IDB_CA0_HW_STATUS_PIPE4 */ "IDB_CA0_HW_STATUS_PIPE4", 34191 /* IDB_CA0_HW_STATUS_PIPE5 */ "IDB_CA0_HW_STATUS_PIPE5", 34192 /* IDB_CA0_HW_STATUS_PIPE6 */ "IDB_CA0_HW_STATUS_PIPE6", 34193 /* IDB_CA0_HW_STATUS_PIPE7 */ "IDB_CA0_HW_STATUS_PIPE7", 34194 /* IDB_CA0_SER_CONTROL */ "IDB_CA0_SER_CONTROL", 34195 /* IDB_CA1_BUFFER_CONFIG */ "", 34196 /* IDB_CA1_BUFFER_CONFIG_PIPE0 */ "", 34197 /* IDB_CA1_BUFFER_CONFIG_PIPE1 */ "", 34198 /* IDB_CA1_BUFFER_CONFIG_PIPE2 */ "", 34199 /* IDB_CA1_BUFFER_CONFIG_PIPE3 */ "", 34200 /* IDB_CA1_BUFFER_CONFIG_PIPE4 */ "", 34201 /* IDB_CA1_BUFFER_CONFIG_PIPE5 */ "", 34202 /* IDB_CA1_BUFFER_CONFIG_PIPE6 */ "", 34203 /* IDB_CA1_BUFFER_CONFIG_PIPE7 */ "", 34204 /* IDB_CA1_CONTROL */ "IDB_CA1_CONTROL", 34205 /* IDB_CA1_CONTROL_PIPE0 */ "IDB_CA1_CONTROL_PIPE0", 34206 /* IDB_CA1_CONTROL_PIPE1 */ "IDB_CA1_CONTROL_PIPE1", 34207 /* IDB_CA1_CONTROL_PIPE2 */ "IDB_CA1_CONTROL_PIPE2", 34208 /* IDB_CA1_CONTROL_PIPE3 */ "IDB_CA1_CONTROL_PIPE3", 34209 /* IDB_CA1_CONTROL_PIPE4 */ "IDB_CA1_CONTROL_PIPE4", 34210 /* IDB_CA1_CONTROL_PIPE5 */ "IDB_CA1_CONTROL_PIPE5", 34211 /* IDB_CA1_CONTROL_PIPE6 */ "IDB_CA1_CONTROL_PIPE6", 34212 /* IDB_CA1_CONTROL_PIPE7 */ "IDB_CA1_CONTROL_PIPE7", 34213 /* IDB_CA1_CT_CONTROL */ "IDB_CA1_CT_CONTROL", 34214 /* IDB_CA1_CT_CONTROL_PIPE0 */ "IDB_CA1_CT_CONTROL_PIPE0", 34215 /* IDB_CA1_CT_CONTROL_PIPE1 */ "IDB_CA1_CT_CONTROL_PIPE1", 34216 /* IDB_CA1_CT_CONTROL_PIPE2 */ "IDB_CA1_CT_CONTROL_PIPE2", 34217 /* IDB_CA1_CT_CONTROL_PIPE3 */ "IDB_CA1_CT_CONTROL_PIPE3", 34218 /* IDB_CA1_CT_CONTROL_PIPE4 */ "IDB_CA1_CT_CONTROL_PIPE4", 34219 /* IDB_CA1_CT_CONTROL_PIPE5 */ "IDB_CA1_CT_CONTROL_PIPE5", 34220 /* IDB_CA1_CT_CONTROL_PIPE6 */ "IDB_CA1_CT_CONTROL_PIPE6", 34221 /* IDB_CA1_CT_CONTROL_PIPE7 */ "IDB_CA1_CT_CONTROL_PIPE7", 34222 /* IDB_CA1_DBG_A */ "IDB_CA1_FORCE_SAF_CONFIG", 34223 /* IDB_CA1_DBG_A_PIPE0 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE0", 34224 /* IDB_CA1_DBG_A_PIPE1 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE1", 34225 /* IDB_CA1_DBG_A_PIPE2 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE2", 34226 /* IDB_CA1_DBG_A_PIPE3 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE3", 34227 /* IDB_CA1_DBG_A_PIPE4 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE4", 34228 /* IDB_CA1_DBG_A_PIPE5 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE5", 34229 /* IDB_CA1_DBG_A_PIPE6 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE6", 34230 /* IDB_CA1_DBG_A_PIPE7 */ "IDB_CA1_FORCE_SAF_CONFIG_PIPE7", 34231 /* IDB_CA1_DBG_B */ "IDB_CA1_LAG_DETECTION_CONFIG", 34232 /* IDB_CA1_DBG_B_PIPE0 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE0", 34233 /* IDB_CA1_DBG_B_PIPE1 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE1", 34234 /* IDB_CA1_DBG_B_PIPE2 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE2", 34235 /* IDB_CA1_DBG_B_PIPE3 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE3", 34236 /* IDB_CA1_DBG_B_PIPE4 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE4", 34237 /* IDB_CA1_DBG_B_PIPE5 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE5", 34238 /* IDB_CA1_DBG_B_PIPE6 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE6", 34239 /* IDB_CA1_DBG_B_PIPE7 */ "IDB_CA1_LAG_DETECTION_CONFIG_PIPE7", 34240 /* IDB_CA1_HW_STATUS */ "IDB_CA1_HW_STATUS", 34241 /* IDB_CA1_HW_STATUS_1 */ "IDB_CA1_HW_STATUS_1", 34242 /* IDB_CA1_HW_STATUS_2 */ "IDB_CA1_HW_STATUS_2", 34243 /* IDB_CA1_HW_STATUS_1_PIPE0 */ "IDB_CA1_HW_STATUS_1_PIPE0", 34244 /* IDB_CA1_HW_STATUS_1_PIPE1 */ "IDB_CA1_HW_STATUS_1_PIPE1", 34245 /* IDB_CA1_HW_STATUS_1_PIPE2 */ "IDB_CA1_HW_STATUS_1_PIPE2", 34246 /* IDB_CA1_HW_STATUS_1_PIPE3 */ "IDB_CA1_HW_STATUS_1_PIPE3", 34247 /* IDB_CA1_HW_STATUS_1_PIPE4 */ "IDB_CA1_HW_STATUS_1_PIPE4", 34248 /* IDB_CA1_HW_STATUS_1_PIPE5 */ "IDB_CA1_HW_STATUS_1_PIPE5", 34249 /* IDB_CA1_HW_STATUS_1_PIPE6 */ "IDB_CA1_HW_STATUS_1_PIPE6", 34250 /* IDB_CA1_HW_STATUS_1_PIPE7 */ "IDB_CA1_HW_STATUS_1_PIPE7", 34251 /* IDB_CA1_HW_STATUS_2_PIPE0 */ "IDB_CA1_HW_STATUS_2_PIPE0", 34252 /* IDB_CA1_HW_STATUS_2_PIPE1 */ "IDB_CA1_HW_STATUS_2_PIPE1", 34253 /* IDB_CA1_HW_STATUS_2_PIPE2 */ "IDB_CA1_HW_STATUS_2_PIPE2", 34254 /* IDB_CA1_HW_STATUS_2_PIPE3 */ "IDB_CA1_HW_STATUS_2_PIPE3", 34255 /* IDB_CA1_HW_STATUS_2_PIPE4 */ "IDB_CA1_HW_STATUS_2_PIPE4", 34256 /* IDB_CA1_HW_STATUS_2_PIPE5 */ "IDB_CA1_HW_STATUS_2_PIPE5", 34257 /* IDB_CA1_HW_STATUS_2_PIPE6 */ "IDB_CA1_HW_STATUS_2_PIPE6", 34258 /* IDB_CA1_HW_STATUS_2_PIPE7 */ "IDB_CA1_HW_STATUS_2_PIPE7", 34259 /* IDB_CA1_HW_STATUS_PIPE0 */ "IDB_CA1_HW_STATUS_PIPE0", 34260 /* IDB_CA1_HW_STATUS_PIPE1 */ "IDB_CA1_HW_STATUS_PIPE1", 34261 /* IDB_CA1_HW_STATUS_PIPE2 */ "IDB_CA1_HW_STATUS_PIPE2", 34262 /* IDB_CA1_HW_STATUS_PIPE3 */ "IDB_CA1_HW_STATUS_PIPE3", 34263 /* IDB_CA1_HW_STATUS_PIPE4 */ "IDB_CA1_HW_STATUS_PIPE4", 34264 /* IDB_CA1_HW_STATUS_PIPE5 */ "IDB_CA1_HW_STATUS_PIPE5", 34265 /* IDB_CA1_HW_STATUS_PIPE6 */ "IDB_CA1_HW_STATUS_PIPE6", 34266 /* IDB_CA1_HW_STATUS_PIPE7 */ "IDB_CA1_HW_STATUS_PIPE7", 34267 /* IDB_CA1_SER_CONTROL */ "IDB_CA1_SER_CONTROL", 34268 /* IDB_CA2_BUFFER_CONFIG */ "", 34269 /* IDB_CA2_BUFFER_CONFIG_PIPE0 */ "", 34270 /* IDB_CA2_BUFFER_CONFIG_PIPE1 */ "", 34271 /* IDB_CA2_BUFFER_CONFIG_PIPE2 */ "", 34272 /* IDB_CA2_BUFFER_CONFIG_PIPE3 */ "", 34273 /* IDB_CA2_BUFFER_CONFIG_PIPE4 */ "", 34274 /* IDB_CA2_BUFFER_CONFIG_PIPE5 */ "", 34275 /* IDB_CA2_BUFFER_CONFIG_PIPE6 */ "", 34276 /* IDB_CA2_BUFFER_CONFIG_PIPE7 */ "", 34277 /* IDB_CA2_CONTROL */ "IDB_CA2_CONTROL", 34278 /* IDB_CA2_CONTROL_PIPE0 */ "IDB_CA2_CONTROL_PIPE0", 34279 /* IDB_CA2_CONTROL_PIPE1 */ "IDB_CA2_CONTROL_PIPE1", 34280 /* IDB_CA2_CONTROL_PIPE2 */ "IDB_CA2_CONTROL_PIPE2", 34281 /* IDB_CA2_CONTROL_PIPE3 */ "IDB_CA2_CONTROL_PIPE3", 34282 /* IDB_CA2_CONTROL_PIPE4 */ "IDB_CA2_CONTROL_PIPE4", 34283 /* IDB_CA2_CONTROL_PIPE5 */ "IDB_CA2_CONTROL_PIPE5", 34284 /* IDB_CA2_CONTROL_PIPE6 */ "IDB_CA2_CONTROL_PIPE6", 34285 /* IDB_CA2_CONTROL_PIPE7 */ "IDB_CA2_CONTROL_PIPE7", 34286 /* IDB_CA2_CT_CONTROL */ "IDB_CA2_CT_CONTROL", 34287 /* IDB_CA2_CT_CONTROL_PIPE0 */ "IDB_CA2_CT_CONTROL_PIPE0", 34288 /* IDB_CA2_CT_CONTROL_PIPE1 */ "IDB_CA2_CT_CONTROL_PIPE1", 34289 /* IDB_CA2_CT_CONTROL_PIPE2 */ "IDB_CA2_CT_CONTROL_PIPE2", 34290 /* IDB_CA2_CT_CONTROL_PIPE3 */ "IDB_CA2_CT_CONTROL_PIPE3", 34291 /* IDB_CA2_CT_CONTROL_PIPE4 */ "IDB_CA2_CT_CONTROL_PIPE4", 34292 /* IDB_CA2_CT_CONTROL_PIPE5 */ "IDB_CA2_CT_CONTROL_PIPE5", 34293 /* IDB_CA2_CT_CONTROL_PIPE6 */ "IDB_CA2_CT_CONTROL_PIPE6", 34294 /* IDB_CA2_CT_CONTROL_PIPE7 */ "IDB_CA2_CT_CONTROL_PIPE7", 34295 /* IDB_CA2_DBG_A */ "IDB_CA2_FORCE_SAF_CONFIG", 34296 /* IDB_CA2_DBG_A_PIPE0 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE0", 34297 /* IDB_CA2_DBG_A_PIPE1 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE1", 34298 /* IDB_CA2_DBG_A_PIPE2 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE2", 34299 /* IDB_CA2_DBG_A_PIPE3 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE3", 34300 /* IDB_CA2_DBG_A_PIPE4 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE4", 34301 /* IDB_CA2_DBG_A_PIPE5 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE5", 34302 /* IDB_CA2_DBG_A_PIPE6 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE6", 34303 /* IDB_CA2_DBG_A_PIPE7 */ "IDB_CA2_FORCE_SAF_CONFIG_PIPE7", 34304 /* IDB_CA2_DBG_B */ "IDB_CA2_LAG_DETECTION_CONFIG", 34305 /* IDB_CA2_DBG_B_PIPE0 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE0", 34306 /* IDB_CA2_DBG_B_PIPE1 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE1", 34307 /* IDB_CA2_DBG_B_PIPE2 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE2", 34308 /* IDB_CA2_DBG_B_PIPE3 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE3", 34309 /* IDB_CA2_DBG_B_PIPE4 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE4", 34310 /* IDB_CA2_DBG_B_PIPE5 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE5", 34311 /* IDB_CA2_DBG_B_PIPE6 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE6", 34312 /* IDB_CA2_DBG_B_PIPE7 */ "IDB_CA2_LAG_DETECTION_CONFIG_PIPE7", 34313 /* IDB_CA2_HW_STATUS */ "IDB_CA2_HW_STATUS", 34314 /* IDB_CA2_HW_STATUS_1 */ "IDB_CA2_HW_STATUS_1", 34315 /* IDB_CA2_HW_STATUS_2 */ "IDB_CA2_HW_STATUS_2", 34316 /* IDB_CA2_HW_STATUS_1_PIPE0 */ "IDB_CA2_HW_STATUS_1_PIPE0", 34317 /* IDB_CA2_HW_STATUS_1_PIPE1 */ "IDB_CA2_HW_STATUS_1_PIPE1", 34318 /* IDB_CA2_HW_STATUS_1_PIPE2 */ "IDB_CA2_HW_STATUS_1_PIPE2", 34319 /* IDB_CA2_HW_STATUS_1_PIPE3 */ "IDB_CA2_HW_STATUS_1_PIPE3", 34320 /* IDB_CA2_HW_STATUS_1_PIPE4 */ "IDB_CA2_HW_STATUS_1_PIPE4", 34321 /* IDB_CA2_HW_STATUS_1_PIPE5 */ "IDB_CA2_HW_STATUS_1_PIPE5", 34322 /* IDB_CA2_HW_STATUS_1_PIPE6 */ "IDB_CA2_HW_STATUS_1_PIPE6", 34323 /* IDB_CA2_HW_STATUS_1_PIPE7 */ "IDB_CA2_HW_STATUS_1_PIPE7", 34324 /* IDB_CA2_HW_STATUS_2_PIPE0 */ "IDB_CA2_HW_STATUS_2_PIPE0", 34325 /* IDB_CA2_HW_STATUS_2_PIPE1 */ "IDB_CA2_HW_STATUS_2_PIPE1", 34326 /* IDB_CA2_HW_STATUS_2_PIPE2 */ "IDB_CA2_HW_STATUS_2_PIPE2", 34327 /* IDB_CA2_HW_STATUS_2_PIPE3 */ "IDB_CA2_HW_STATUS_2_PIPE3", 34328 /* IDB_CA2_HW_STATUS_2_PIPE4 */ "IDB_CA2_HW_STATUS_2_PIPE4", 34329 /* IDB_CA2_HW_STATUS_2_PIPE5 */ "IDB_CA2_HW_STATUS_2_PIPE5", 34330 /* IDB_CA2_HW_STATUS_2_PIPE6 */ "IDB_CA2_HW_STATUS_2_PIPE6", 34331 /* IDB_CA2_HW_STATUS_2_PIPE7 */ "IDB_CA2_HW_STATUS_2_PIPE7", 34332 /* IDB_CA2_HW_STATUS_PIPE0 */ "IDB_CA2_HW_STATUS_PIPE0", 34333 /* IDB_CA2_HW_STATUS_PIPE1 */ "IDB_CA2_HW_STATUS_PIPE1", 34334 /* IDB_CA2_HW_STATUS_PIPE2 */ "IDB_CA2_HW_STATUS_PIPE2", 34335 /* IDB_CA2_HW_STATUS_PIPE3 */ "IDB_CA2_HW_STATUS_PIPE3", 34336 /* IDB_CA2_HW_STATUS_PIPE4 */ "IDB_CA2_HW_STATUS_PIPE4", 34337 /* IDB_CA2_HW_STATUS_PIPE5 */ "IDB_CA2_HW_STATUS_PIPE5", 34338 /* IDB_CA2_HW_STATUS_PIPE6 */ "IDB_CA2_HW_STATUS_PIPE6", 34339 /* IDB_CA2_HW_STATUS_PIPE7 */ "IDB_CA2_HW_STATUS_PIPE7", 34340 /* IDB_CA2_SER_CONTROL */ "IDB_CA2_SER_CONTROL", 34341 /* IDB_CA3_BUFFER_CONFIG */ "", 34342 /* IDB_CA3_BUFFER_CONFIG_PIPE0 */ "", 34343 /* IDB_CA3_BUFFER_CONFIG_PIPE1 */ "", 34344 /* IDB_CA3_BUFFER_CONFIG_PIPE2 */ "", 34345 /* IDB_CA3_BUFFER_CONFIG_PIPE3 */ "", 34346 /* IDB_CA3_BUFFER_CONFIG_PIPE4 */ "", 34347 /* IDB_CA3_BUFFER_CONFIG_PIPE5 */ "", 34348 /* IDB_CA3_BUFFER_CONFIG_PIPE6 */ "", 34349 /* IDB_CA3_BUFFER_CONFIG_PIPE7 */ "", 34350 /* IDB_CA3_CONTROL */ "IDB_CA3_CONTROL", 34351 /* IDB_CA3_CONTROL_PIPE0 */ "IDB_CA3_CONTROL_PIPE0", 34352 /* IDB_CA3_CONTROL_PIPE1 */ "IDB_CA3_CONTROL_PIPE1", 34353 /* IDB_CA3_CONTROL_PIPE2 */ "IDB_CA3_CONTROL_PIPE2", 34354 /* IDB_CA3_CONTROL_PIPE3 */ "IDB_CA3_CONTROL_PIPE3", 34355 /* IDB_CA3_CONTROL_PIPE4 */ "IDB_CA3_CONTROL_PIPE4", 34356 /* IDB_CA3_CONTROL_PIPE5 */ "IDB_CA3_CONTROL_PIPE5", 34357 /* IDB_CA3_CONTROL_PIPE6 */ "IDB_CA3_CONTROL_PIPE6", 34358 /* IDB_CA3_CONTROL_PIPE7 */ "IDB_CA3_CONTROL_PIPE7", 34359 /* IDB_CA3_CT_CONTROL */ "IDB_CA3_CT_CONTROL", 34360 /* IDB_CA3_CT_CONTROL_PIPE0 */ "IDB_CA3_CT_CONTROL_PIPE0", 34361 /* IDB_CA3_CT_CONTROL_PIPE1 */ "IDB_CA3_CT_CONTROL_PIPE1", 34362 /* IDB_CA3_CT_CONTROL_PIPE2 */ "IDB_CA3_CT_CONTROL_PIPE2", 34363 /* IDB_CA3_CT_CONTROL_PIPE3 */ "IDB_CA3_CT_CONTROL_PIPE3", 34364 /* IDB_CA3_CT_CONTROL_PIPE4 */ "IDB_CA3_CT_CONTROL_PIPE4", 34365 /* IDB_CA3_CT_CONTROL_PIPE5 */ "IDB_CA3_CT_CONTROL_PIPE5", 34366 /* IDB_CA3_CT_CONTROL_PIPE6 */ "IDB_CA3_CT_CONTROL_PIPE6", 34367 /* IDB_CA3_CT_CONTROL_PIPE7 */ "IDB_CA3_CT_CONTROL_PIPE7", 34368 /* IDB_CA3_DBG_A */ "IDB_CA3_FORCE_SAF_CONFIG", 34369 /* IDB_CA3_DBG_A_PIPE0 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE0", 34370 /* IDB_CA3_DBG_A_PIPE1 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE1", 34371 /* IDB_CA3_DBG_A_PIPE2 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE2", 34372 /* IDB_CA3_DBG_A_PIPE3 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE3", 34373 /* IDB_CA3_DBG_A_PIPE4 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE4", 34374 /* IDB_CA3_DBG_A_PIPE5 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE5", 34375 /* IDB_CA3_DBG_A_PIPE6 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE6", 34376 /* IDB_CA3_DBG_A_PIPE7 */ "IDB_CA3_FORCE_SAF_CONFIG_PIPE7", 34377 /* IDB_CA3_DBG_B */ "IDB_CA3_LAG_DETECTION_CONFIG", 34378 /* IDB_CA3_DBG_B_PIPE0 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE0", 34379 /* IDB_CA3_DBG_B_PIPE1 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE1", 34380 /* IDB_CA3_DBG_B_PIPE2 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE2", 34381 /* IDB_CA3_DBG_B_PIPE3 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE3", 34382 /* IDB_CA3_DBG_B_PIPE4 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE4", 34383 /* IDB_CA3_DBG_B_PIPE5 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE5", 34384 /* IDB_CA3_DBG_B_PIPE6 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE6", 34385 /* IDB_CA3_DBG_B_PIPE7 */ "IDB_CA3_LAG_DETECTION_CONFIG_PIPE7", 34386 /* IDB_CA3_HW_STATUS */ "IDB_CA3_HW_STATUS", 34387 /* IDB_CA3_HW_STATUS_1 */ "IDB_CA3_HW_STATUS_1", 34388 /* IDB_CA3_HW_STATUS_2 */ "IDB_CA3_HW_STATUS_2", 34389 /* IDB_CA3_HW_STATUS_1_PIPE0 */ "IDB_CA3_HW_STATUS_1_PIPE0", 34390 /* IDB_CA3_HW_STATUS_1_PIPE1 */ "IDB_CA3_HW_STATUS_1_PIPE1", 34391 /* IDB_CA3_HW_STATUS_1_PIPE2 */ "IDB_CA3_HW_STATUS_1_PIPE2", 34392 /* IDB_CA3_HW_STATUS_1_PIPE3 */ "IDB_CA3_HW_STATUS_1_PIPE3", 34393 /* IDB_CA3_HW_STATUS_1_PIPE4 */ "IDB_CA3_HW_STATUS_1_PIPE4", 34394 /* IDB_CA3_HW_STATUS_1_PIPE5 */ "IDB_CA3_HW_STATUS_1_PIPE5", 34395 /* IDB_CA3_HW_STATUS_1_PIPE6 */ "IDB_CA3_HW_STATUS_1_PIPE6", 34396 /* IDB_CA3_HW_STATUS_1_PIPE7 */ "IDB_CA3_HW_STATUS_1_PIPE7", 34397 /* IDB_CA3_HW_STATUS_2_PIPE0 */ "IDB_CA3_HW_STATUS_2_PIPE0", 34398 /* IDB_CA3_HW_STATUS_2_PIPE1 */ "IDB_CA3_HW_STATUS_2_PIPE1", 34399 /* IDB_CA3_HW_STATUS_2_PIPE2 */ "IDB_CA3_HW_STATUS_2_PIPE2", 34400 /* IDB_CA3_HW_STATUS_2_PIPE3 */ "IDB_CA3_HW_STATUS_2_PIPE3", 34401 /* IDB_CA3_HW_STATUS_2_PIPE4 */ "IDB_CA3_HW_STATUS_2_PIPE4", 34402 /* IDB_CA3_HW_STATUS_2_PIPE5 */ "IDB_CA3_HW_STATUS_2_PIPE5", 34403 /* IDB_CA3_HW_STATUS_2_PIPE6 */ "IDB_CA3_HW_STATUS_2_PIPE6", 34404 /* IDB_CA3_HW_STATUS_2_PIPE7 */ "IDB_CA3_HW_STATUS_2_PIPE7", 34405 /* IDB_CA3_HW_STATUS_PIPE0 */ "IDB_CA3_HW_STATUS_PIPE0", 34406 /* IDB_CA3_HW_STATUS_PIPE1 */ "IDB_CA3_HW_STATUS_PIPE1", 34407 /* IDB_CA3_HW_STATUS_PIPE2 */ "IDB_CA3_HW_STATUS_PIPE2", 34408 /* IDB_CA3_HW_STATUS_PIPE3 */ "IDB_CA3_HW_STATUS_PIPE3", 34409 /* IDB_CA3_HW_STATUS_PIPE4 */ "IDB_CA3_HW_STATUS_PIPE4", 34410 /* IDB_CA3_HW_STATUS_PIPE5 */ "IDB_CA3_HW_STATUS_PIPE5", 34411 /* IDB_CA3_HW_STATUS_PIPE6 */ "IDB_CA3_HW_STATUS_PIPE6", 34412 /* IDB_CA3_HW_STATUS_PIPE7 */ "IDB_CA3_HW_STATUS_PIPE7", 34413 /* IDB_CA3_SER_CONTROL */ "IDB_CA3_SER_CONTROL", 34414 /* IDB_CA_BSK_CONTROL */ "IDB_CA_BSK_CONTROL", 34415 /* IDB_CA_BSK_CONTROL_PIPE0 */ "IDB_CA_BSK_CONTROL_PIPE0", 34416 /* IDB_CA_BSK_ECC_STATUS */ "IDB_CA_BSK_ECC_STATUS", 34417 /* IDB_CA_BSK_ECC_STATUS_PIPE0 */ "IDB_CA_BSK_ECC_STATUS_PIPE0", 34418 /* IDB_CA_BSK_HW_STATUS */ "IDB_CA_BSK_HW_STATUS", 34419 /* IDB_CA_BSK_HW_STATUS_PIPE0 */ "IDB_CA_BSK_HW_STATUS_PIPE0", 34420 /* IDB_CA_CONTROL_1 */ "", 34421 /* IDB_CA_CONTROL_2 */ "", 34422 /* IDB_CA_CONTROL_1_PIPE0 */ "", 34423 /* IDB_CA_CONTROL_1_PIPE1 */ "", 34424 /* IDB_CA_CONTROL_1_PIPE2 */ "", 34425 /* IDB_CA_CONTROL_1_PIPE3 */ "", 34426 /* IDB_CA_CONTROL_1_PIPE4 */ "", 34427 /* IDB_CA_CONTROL_1_PIPE5 */ "", 34428 /* IDB_CA_CONTROL_1_PIPE6 */ "", 34429 /* IDB_CA_CONTROL_1_PIPE7 */ "", 34430 /* IDB_CA_CONTROL_2_PIPE0 */ "", 34431 /* IDB_CA_CONTROL_2_PIPE1 */ "", 34432 /* IDB_CA_CONTROL_2_PIPE2 */ "", 34433 /* IDB_CA_CONTROL_2_PIPE3 */ "", 34434 /* IDB_CA_CONTROL_2_PIPE4 */ "", 34435 /* IDB_CA_CONTROL_2_PIPE5 */ "", 34436 /* IDB_CA_CONTROL_2_PIPE6 */ "", 34437 /* IDB_CA_CONTROL_2_PIPE7 */ "", 34438 /* IDB_CA_CPU_CONTROL */ "IDB_CA_CPU_CONTROL", 34439 /* IDB_CA_CPU_CONTROL_PIPE0 */ "IDB_CA_CPU_CONTROL_PIPE0", 34440 /* IDB_CA_CPU_CONTROL_PIPE1 */ "IDB_CA_CPU_CONTROL_PIPE1", 34441 /* IDB_CA_CPU_CONTROL_PIPE2 */ "IDB_CA_CPU_CONTROL_PIPE2", 34442 /* IDB_CA_CPU_CONTROL_PIPE3 */ "IDB_CA_CPU_CONTROL_PIPE3", 34443 /* IDB_CA_CPU_CONTROL_PIPE4 */ "IDB_CA_CPU_CONTROL_PIPE4", 34444 /* IDB_CA_CPU_CONTROL_PIPE5 */ "IDB_CA_CPU_CONTROL_PIPE5", 34445 /* IDB_CA_CPU_CONTROL_PIPE6 */ "IDB_CA_CPU_CONTROL_PIPE6", 34446 /* IDB_CA_CPU_CONTROL_PIPE7 */ "IDB_CA_CPU_CONTROL_PIPE7", 34447 /* IDB_CA_CPU_CT_CONTROL */ "IDB_CA_CPU_CT_CONTROL", 34448 /* IDB_CA_CPU_CT_CONTROL_PIPE0 */ "IDB_CA_CPU_CT_CONTROL_PIPE0", 34449 /* IDB_CA_CPU_CT_CONTROL_PIPE1 */ "IDB_CA_CPU_CT_CONTROL_PIPE1", 34450 /* IDB_CA_CPU_CT_CONTROL_PIPE2 */ "IDB_CA_CPU_CT_CONTROL_PIPE2", 34451 /* IDB_CA_CPU_CT_CONTROL_PIPE3 */ "IDB_CA_CPU_CT_CONTROL_PIPE3", 34452 /* IDB_CA_CPU_ECC_STATUS */ "IDB_CA_CPU_ECC_STATUS", 34453 /* IDB_CA_CPU_ECC_STATUS_PIPE0 */ "IDB_CA_CPU_ECC_STATUS_PIPE0", 34454 /* IDB_CA_CPU_ECC_STATUS_PIPE1 */ "IDB_CA_CPU_ECC_STATUS_PIPE1", 34455 /* IDB_CA_CPU_ECC_STATUS_PIPE2 */ "IDB_CA_CPU_ECC_STATUS_PIPE2", 34456 /* IDB_CA_CPU_ECC_STATUS_PIPE3 */ "IDB_CA_CPU_ECC_STATUS_PIPE3", 34457 /* IDB_CA_CPU_ECC_STATUS_PIPE4 */ "IDB_CA_CPU_ECC_STATUS_PIPE4", 34458 /* IDB_CA_CPU_ECC_STATUS_PIPE5 */ "IDB_CA_CPU_ECC_STATUS_PIPE5", 34459 /* IDB_CA_CPU_ECC_STATUS_PIPE6 */ "IDB_CA_CPU_ECC_STATUS_PIPE6", 34460 /* IDB_CA_CPU_ECC_STATUS_PIPE7 */ "IDB_CA_CPU_ECC_STATUS_PIPE7", 34461 /* IDB_CA_CPU_HW_CONTROL */ "IDB_CA_CPU_HW_CONTROL", 34462 /* IDB_CA_CPU_HW_CONTROL_PIPE0 */ "IDB_CA_CPU_HW_CONTROL_PIPE0", 34463 /* IDB_CA_CPU_HW_CONTROL_PIPE1 */ "IDB_CA_CPU_HW_CONTROL_PIPE1", 34464 /* IDB_CA_CPU_HW_CONTROL_PIPE2 */ "IDB_CA_CPU_HW_CONTROL_PIPE2", 34465 /* IDB_CA_CPU_HW_CONTROL_PIPE3 */ "IDB_CA_CPU_HW_CONTROL_PIPE3", 34466 /* IDB_CA_CPU_HW_STATUS */ "IDB_CA_CPU_HW_STATUS", 34467 /* IDB_CA_CPU_HW_STATUS_PIPE0 */ "IDB_CA_CPU_HW_STATUS_PIPE0", 34468 /* IDB_CA_CPU_HW_STATUS_PIPE1 */ "IDB_CA_CPU_HW_STATUS_PIPE1", 34469 /* IDB_CA_CPU_HW_STATUS_PIPE2 */ "IDB_CA_CPU_HW_STATUS_PIPE2", 34470 /* IDB_CA_CPU_HW_STATUS_PIPE3 */ "IDB_CA_CPU_HW_STATUS_PIPE3", 34471 /* IDB_CA_CPU_HW_STATUS_PIPE4 */ "IDB_CA_CPU_HW_STATUS_PIPE4", 34472 /* IDB_CA_CPU_HW_STATUS_PIPE5 */ "IDB_CA_CPU_HW_STATUS_PIPE5", 34473 /* IDB_CA_CPU_HW_STATUS_PIPE6 */ "IDB_CA_CPU_HW_STATUS_PIPE6", 34474 /* IDB_CA_CPU_HW_STATUS_PIPE7 */ "IDB_CA_CPU_HW_STATUS_PIPE7", 34475 /* IDB_CA_CPU_SER_CONTROL */ "IDB_CA_CPU_SER_CONTROL", 34476 /* IDB_CA_ECC_STATUS */ "", 34477 /* IDB_CA_ECC_STATUS_PIPE0 */ "", 34478 /* IDB_CA_ECC_STATUS_PIPE1 */ "", 34479 /* IDB_CA_ECC_STATUS_PIPE2 */ "", 34480 /* IDB_CA_ECC_STATUS_PIPE3 */ "", 34481 /* IDB_CA_ECC_STATUS_PIPE4 */ "", 34482 /* IDB_CA_ECC_STATUS_PIPE5 */ "", 34483 /* IDB_CA_ECC_STATUS_PIPE6 */ "", 34484 /* IDB_CA_ECC_STATUS_PIPE7 */ "", 34485 /* IDB_CA_HW_ERR_STATUS */ "", 34486 /* IDB_CA_HW_ERR_STATUS_PIPE0 */ "", 34487 /* IDB_CA_HW_ERR_STATUS_PIPE1 */ "", 34488 /* IDB_CA_HW_ERR_STATUS_PIPE2 */ "", 34489 /* IDB_CA_HW_ERR_STATUS_PIPE3 */ "", 34490 /* IDB_CA_LPBK_CONTROL */ "IDB_CA_LPBK_CONTROL", 34491 /* IDB_CA_LPBK_CONTROL_PIPE0 */ "IDB_CA_LPBK_CONTROL_PIPE0", 34492 /* IDB_CA_LPBK_CONTROL_PIPE1 */ "IDB_CA_LPBK_CONTROL_PIPE1", 34493 /* IDB_CA_LPBK_CONTROL_PIPE2 */ "IDB_CA_LPBK_CONTROL_PIPE2", 34494 /* IDB_CA_LPBK_CONTROL_PIPE3 */ "IDB_CA_LPBK_CONTROL_PIPE3", 34495 /* IDB_CA_LPBK_CONTROL_PIPE4 */ "IDB_CA_LPBK_CONTROL_PIPE4", 34496 /* IDB_CA_LPBK_CONTROL_PIPE5 */ "IDB_CA_LPBK_CONTROL_PIPE5", 34497 /* IDB_CA_LPBK_CONTROL_PIPE6 */ "IDB_CA_LPBK_CONTROL_PIPE6", 34498 /* IDB_CA_LPBK_CONTROL_PIPE7 */ "IDB_CA_LPBK_CONTROL_PIPE7", 34499 /* IDB_CA_LPBK_CT_CONTROL */ "IDB_CA_LPBK_CT_CONTROL", 34500 /* IDB_CA_LPBK_CT_CONTROL_PIPE0 */ "IDB_CA_LPBK_CT_CONTROL_PIPE0", 34501 /* IDB_CA_LPBK_CT_CONTROL_PIPE1 */ "IDB_CA_LPBK_CT_CONTROL_PIPE1", 34502 /* IDB_CA_LPBK_CT_CONTROL_PIPE2 */ "IDB_CA_LPBK_CT_CONTROL_PIPE2", 34503 /* IDB_CA_LPBK_CT_CONTROL_PIPE3 */ "IDB_CA_LPBK_CT_CONTROL_PIPE3", 34504 /* IDB_CA_LPBK_ECC_STATUS */ "IDB_CA_LPBK_ECC_STATUS", 34505 /* IDB_CA_LPBK_ECC_STATUS_PIPE0 */ "IDB_CA_LPBK_ECC_STATUS_PIPE0", 34506 /* IDB_CA_LPBK_ECC_STATUS_PIPE1 */ "IDB_CA_LPBK_ECC_STATUS_PIPE1", 34507 /* IDB_CA_LPBK_ECC_STATUS_PIPE2 */ "IDB_CA_LPBK_ECC_STATUS_PIPE2", 34508 /* IDB_CA_LPBK_ECC_STATUS_PIPE3 */ "IDB_CA_LPBK_ECC_STATUS_PIPE3", 34509 /* IDB_CA_LPBK_ECC_STATUS_PIPE4 */ "IDB_CA_LPBK_ECC_STATUS_PIPE4", 34510 /* IDB_CA_LPBK_ECC_STATUS_PIPE5 */ "IDB_CA_LPBK_ECC_STATUS_PIPE5", 34511 /* IDB_CA_LPBK_ECC_STATUS_PIPE6 */ "IDB_CA_LPBK_ECC_STATUS_PIPE6", 34512 /* IDB_CA_LPBK_ECC_STATUS_PIPE7 */ "IDB_CA_LPBK_ECC_STATUS_PIPE7", 34513 /* IDB_CA_LPBK_HW_CONTROL */ "IDB_CA_LPBK_HW_CONTROL", 34514 /* IDB_CA_LPBK_HW_CONTROL_PIPE0 */ "IDB_CA_LPBK_HW_CONTROL_PIPE0", 34515 /* IDB_CA_LPBK_HW_CONTROL_PIPE1 */ "IDB_CA_LPBK_HW_CONTROL_PIPE1", 34516 /* IDB_CA_LPBK_HW_CONTROL_PIPE2 */ "IDB_CA_LPBK_HW_CONTROL_PIPE2", 34517 /* IDB_CA_LPBK_HW_CONTROL_PIPE3 */ "IDB_CA_LPBK_HW_CONTROL_PIPE3", 34518 /* IDB_CA_LPBK_HW_STATUS */ "IDB_CA_LPBK_HW_STATUS", 34519 /* IDB_CA_LPBK_HW_STATUS_PIPE0 */ "IDB_CA_LPBK_HW_STATUS_PIPE0", 34520 /* IDB_CA_LPBK_HW_STATUS_PIPE1 */ "IDB_CA_LPBK_HW_STATUS_PIPE1", 34521 /* IDB_CA_LPBK_HW_STATUS_PIPE2 */ "IDB_CA_LPBK_HW_STATUS_PIPE2", 34522 /* IDB_CA_LPBK_HW_STATUS_PIPE3 */ "IDB_CA_LPBK_HW_STATUS_PIPE3", 34523 /* IDB_CA_LPBK_HW_STATUS_PIPE4 */ "IDB_CA_LPBK_HW_STATUS_PIPE4", 34524 /* IDB_CA_LPBK_HW_STATUS_PIPE5 */ "IDB_CA_LPBK_HW_STATUS_PIPE5", 34525 /* IDB_CA_LPBK_HW_STATUS_PIPE6 */ "IDB_CA_LPBK_HW_STATUS_PIPE6", 34526 /* IDB_CA_LPBK_HW_STATUS_PIPE7 */ "IDB_CA_LPBK_HW_STATUS_PIPE7", 34527 /* IDB_CA_LPBK_SER_CONTROL */ "IDB_CA_LPBK_SER_CONTROL", 34528 /* IDB_CA_MGMT_CONTROL */ "IDB_CA_MGMT_CONTROL", 34529 /* IDB_CA_MGMT_CONTROL_PIPE0 */ "IDB_CA_MGMT_CONTROL_PIPE0", 34530 /* IDB_CA_MGMT_CONTROL_PIPE1 */ "IDB_CA_MGMT_CONTROL_PIPE1", 34531 /* IDB_CA_MGMT_CT_CONTROL */ "IDB_CA_MGMT_CT_CONTROL", 34532 /* IDB_CA_MGMT_CT_CONTROL_PIPE0 */ "IDB_CA_MGMT_CT_CONTROL_PIPE0", 34533 /* IDB_CA_MGMT_CT_CONTROL_PIPE1 */ "IDB_CA_MGMT_CT_CONTROL_PIPE1", 34534 /* IDB_CA_MGMT_ECC_STATUS */ "IDB_CA_MGMT_ECC_STATUS", 34535 /* IDB_CA_MGMT_ECC_STATUS_PIPE0 */ "IDB_CA_MGMT_ECC_STATUS_PIPE0", 34536 /* IDB_CA_MGMT_ECC_STATUS_PIPE1 */ "IDB_CA_MGMT_ECC_STATUS_PIPE1", 34537 /* IDB_CA_MGMT_HW_STATUS */ "IDB_CA_MGMT_HW_STATUS", 34538 /* IDB_CA_MGMT_HW_STATUS_PIPE0 */ "IDB_CA_MGMT_HW_STATUS_PIPE0", 34539 /* IDB_CA_MGMT_HW_STATUS_PIPE1 */ "IDB_CA_MGMT_HW_STATUS_PIPE1", 34540 /* IDB_CA_RAM_CONTROL */ "IDB_CA_RAM_CONTROL", 34541 /* IDB_CA_RAM_CONTROL_PIPE0 */ "IDB_CA_RAM_CONTROL_PIPE0", 34542 /* IDB_CA_RAM_CONTROL_PIPE1 */ "IDB_CA_RAM_CONTROL_PIPE1", 34543 /* IDB_CA_RAM_CONTROL_PIPE2 */ "IDB_CA_RAM_CONTROL_PIPE2", 34544 /* IDB_CA_RAM_CONTROL_PIPE3 */ "IDB_CA_RAM_CONTROL_PIPE3", 34545 /* IDB_CA_RAM_CONTROL_PIPE4 */ "IDB_CA_RAM_CONTROL_PIPE4", 34546 /* IDB_CA_RAM_CONTROL_PIPE5 */ "IDB_CA_RAM_CONTROL_PIPE5", 34547 /* IDB_CA_RAM_CONTROL_PIPE6 */ "IDB_CA_RAM_CONTROL_PIPE6", 34548 /* IDB_CA_RAM_CONTROL_PIPE7 */ "IDB_CA_RAM_CONTROL_PIPE7", 34549 /* IDB_DBG_B */ "IDB_FORCE_SAF_CONFIG", 34550 /* IDB_DBG_B_PIPE0 */ "IDB_FORCE_SAF_CONFIG_PIPE0", 34551 /* IDB_DBG_B_PIPE1 */ "IDB_FORCE_SAF_CONFIG_PIPE1", 34552 /* IDB_DBG_B_PIPE2 */ "IDB_FORCE_SAF_CONFIG_PIPE2", 34553 /* IDB_DBG_B_PIPE3 */ "IDB_FORCE_SAF_CONFIG_PIPE3", 34554 /* IDB_DBG_B_PIPE4 */ "IDB_FORCE_SAF_CONFIG_PIPE4", 34555 /* IDB_DBG_B_PIPE5 */ "IDB_FORCE_SAF_CONFIG_PIPE5", 34556 /* IDB_DBG_B_PIPE6 */ "IDB_FORCE_SAF_CONFIG_PIPE6", 34557 /* IDB_DBG_B_PIPE7 */ "IDB_FORCE_SAF_CONFIG_PIPE7", 34558 /* IDB_DPP_CTRL */ "", 34559 /* IDB_DPP_CTRL_PIPE0 */ "", 34560 /* IDB_DPP_CTRL_PIPE1 */ "", 34561 /* IDB_DPP_CTRL_PIPE2 */ "", 34562 /* IDB_DPP_CTRL_PIPE3 */ "", 34563 /* IDB_ECC_1B_ERR_CNT */ "", 34564 /* IDB_ECC_2B_ERR_CNT */ "", 34565 /* IDB_ECC_ERR_1B_INITIATE */ "", 34566 /* IDB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 34567 /* IDB_ECC_ERR_2B_INITIATE */ "", 34568 /* IDB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 34569 /* IDB_ECC_INTERRUPT_REGISTER */ "", 34570 /* IDB_ECC_INTERRUPT_REGISTER_MASK */ "", 34571 /* IDB_ECC_INTERRUPT_REGISTER_TEST */ "", 34572 /* IDB_EOP_EVENT_ECC_STATUS */ "IDB_EOP_EVENT_ECC_STATUS", 34573 /* IDB_EOP_EVENT_ECC_STATUS_PIPE0 */ "IDB_EOP_EVENT_ECC_STATUS_PIPE0", 34574 /* IDB_EOP_EVENT_ECC_STATUS_PIPE1 */ "IDB_EOP_EVENT_ECC_STATUS_PIPE1", 34575 /* IDB_EOP_EVENT_ECC_STATUS_PIPE2 */ "IDB_EOP_EVENT_ECC_STATUS_PIPE2", 34576 /* IDB_EOP_EVENT_ECC_STATUS_PIPE3 */ "IDB_EOP_EVENT_ECC_STATUS_PIPE3", 34577 /* IDB_ERROR_INITIATION_DATA */ "", 34578 /* IDB_GLOBAL_GENERAL_CFG_3 */ "", 34579 /* IDB_GLOBAL_MEM_OPTIONS */ "", 34580 /* IDB_GTIMER_CONFIGURATION */ "", 34581 /* IDB_HW_CONTROL */ "", 34582 /* IDB_HW_CONTROL_PIPE0 */ "", 34583 /* IDB_HW_CONTROL_PIPE1 */ "", 34584 /* IDB_HW_CONTROL_PIPE2 */ "", 34585 /* IDB_HW_CONTROL_PIPE3 */ "", 34586 /* IDB_HW_RESET_CONTROL */ "", 34587 /* IDB_HW_RESET_CONTROL_PIPE0 */ "", 34588 /* IDB_HW_RESET_CONTROL_PIPE1 */ "", 34589 /* IDB_HW_RESET_CONTROL_PIPE2 */ "", 34590 /* IDB_HW_RESET_CONTROL_PIPE3 */ "", 34591 /* IDB_HW_RESET_CONTROL_PIPE4 */ "", 34592 /* IDB_HW_RESET_CONTROL_PIPE5 */ "", 34593 /* IDB_HW_RESET_CONTROL_PIPE6 */ "", 34594 /* IDB_HW_RESET_CONTROL_PIPE7 */ "", 34595 /* IDB_INTERRUPT_MASK_REGISTER */ "", 34596 /* IDB_INTERRUPT_REGISTER */ "", 34597 /* IDB_INTERRUPT_REGISTER_TEST */ "", 34598 /* IDB_INTR_ENABLE */ "IDB_INTR_ENABLE", 34599 /* IDB_INTR_ENABLE_PIPE0 */ "IDB_INTR_ENABLE_PIPE0", 34600 /* IDB_INTR_ENABLE_PIPE1 */ "IDB_INTR_ENABLE_PIPE1", 34601 /* IDB_INTR_ENABLE_PIPE2 */ "IDB_INTR_ENABLE_PIPE2", 34602 /* IDB_INTR_ENABLE_PIPE3 */ "IDB_INTR_ENABLE_PIPE3", 34603 /* IDB_INTR_ENABLE_PIPE4 */ "IDB_INTR_ENABLE_PIPE4", 34604 /* IDB_INTR_ENABLE_PIPE5 */ "IDB_INTR_ENABLE_PIPE5", 34605 /* IDB_INTR_ENABLE_PIPE6 */ "IDB_INTR_ENABLE_PIPE6", 34606 /* IDB_INTR_ENABLE_PIPE7 */ "IDB_INTR_ENABLE_PIPE7", 34607 /* IDB_INTR_STATUS */ "IDB_INTR_STATUS", 34608 /* IDB_INTR_STATUS_PIPE0 */ "IDB_INTR_STATUS_PIPE0", 34609 /* IDB_INTR_STATUS_PIPE1 */ "IDB_INTR_STATUS_PIPE1", 34610 /* IDB_INTR_STATUS_PIPE2 */ "IDB_INTR_STATUS_PIPE2", 34611 /* IDB_INTR_STATUS_PIPE3 */ "IDB_INTR_STATUS_PIPE3", 34612 /* IDB_INTR_STATUS_PIPE4 */ "IDB_INTR_STATUS_PIPE4", 34613 /* IDB_INTR_STATUS_PIPE5 */ "IDB_INTR_STATUS_PIPE5", 34614 /* IDB_INTR_STATUS_PIPE6 */ "IDB_INTR_STATUS_PIPE6", 34615 /* IDB_INTR_STATUS_PIPE7 */ "IDB_INTR_STATUS_PIPE7", 34616 /* IDB_IS_TDM_CAL_ECC_STATUS */ "IDB_IS_TDM_CAL_ECC_STATUS", 34617 /* IDB_IS_TDM_CAL_ECC_STATUS_PIPE0 */ "IDB_IS_TDM_CAL_ECC_STATUS_PIPE0", 34618 /* IDB_IS_TDM_CAL_ECC_STATUS_PIPE1 */ "IDB_IS_TDM_CAL_ECC_STATUS_PIPE1", 34619 /* IDB_IS_TDM_CAL_ECC_STATUS_PIPE2 */ "IDB_IS_TDM_CAL_ECC_STATUS_PIPE2", 34620 /* IDB_IS_TDM_CAL_ECC_STATUS_PIPE3 */ "IDB_IS_TDM_CAL_ECC_STATUS_PIPE3", 34621 /* IDB_NULL_SLOT_PORT_NUM */ "IDB_NULL_SLOT_PORT_NUM", 34622 /* IDB_NULL_SLOT_PORT_NUM_PIPE0 */ "IDB_NULL_SLOT_PORT_NUM_PIPE0", 34623 /* IDB_NULL_SLOT_PORT_NUM_PIPE1 */ "IDB_NULL_SLOT_PORT_NUM_PIPE1", 34624 /* IDB_NULL_SLOT_PORT_NUM_PIPE2 */ "IDB_NULL_SLOT_PORT_NUM_PIPE2", 34625 /* IDB_NULL_SLOT_PORT_NUM_PIPE3 */ "IDB_NULL_SLOT_PORT_NUM_PIPE3", 34626 /* IDB_NULL_SLOT_PORT_NUM_PIPE4 */ "IDB_NULL_SLOT_PORT_NUM_PIPE4", 34627 /* IDB_NULL_SLOT_PORT_NUM_PIPE5 */ "IDB_NULL_SLOT_PORT_NUM_PIPE5", 34628 /* IDB_NULL_SLOT_PORT_NUM_PIPE6 */ "IDB_NULL_SLOT_PORT_NUM_PIPE6", 34629 /* IDB_NULL_SLOT_PORT_NUM_PIPE7 */ "IDB_NULL_SLOT_PORT_NUM_PIPE7", 34630 /* IDB_OBM0_48_BANK_CONFIG */ "IDB_OBM0_48_BANK_CONFIG", 34631 /* IDB_OBM0_48_BANK_CONFIG_PIPE0 */ "IDB_OBM0_48_BANK_CONFIG_PIPE0", 34632 /* IDB_OBM0_48_BUFFER_CONFIG */ "", 34633 /* IDB_OBM0_48_BUFFER_CONFIG_PIPE0 */ "", 34634 /* IDB_OBM0_48_CA_CONTROL */ "IDB_OBM0_48_CA_CONTROL", 34635 /* IDB_OBM0_48_CA_CONTROL_PIPE0 */ "IDB_OBM0_48_CA_CONTROL_PIPE0", 34636 /* IDB_OBM0_48_CA_ECC_STATUS */ "IDB_OBM0_48_CA_ECC_STATUS", 34637 /* IDB_OBM0_48_CA_ECC_STATUS_PIPE0 */ "IDB_OBM0_48_CA_ECC_STATUS_PIPE0", 34638 /* IDB_OBM0_48_CA_HW_STATUS */ "IDB_OBM0_48_CA_HW_STATUS", 34639 /* IDB_OBM0_48_CA_HW_STATUS_PIPE0 */ "IDB_OBM0_48_CA_HW_STATUS_PIPE0", 34640 /* IDB_OBM0_48_CA_POINTER_STATUS */ "IDB_OBM0_48_CA_POINTER_STATUS", 34641 /* IDB_OBM0_48_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM0_48_CA_POINTER_STATUS_PIPE0", 34642 /* IDB_OBM0_48_CONTROL */ "IDB_OBM0_48_CONTROL", 34643 /* IDB_OBM0_48_CONTROL_PIPE0 */ "IDB_OBM0_48_CONTROL_PIPE0", 34644 /* IDB_OBM0_48_DATA_ECC_STATUS */ "IDB_OBM0_48_DATA_ECC_STATUS", 34645 /* IDB_OBM0_48_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM0_48_DATA_ECC_STATUS_PIPE0", 34646 /* IDB_OBM0_48_FC_THRESHOLD */ "", 34647 /* IDB_OBM0_48_FC_THRESHOLD_1 */ "", 34648 /* IDB_OBM0_48_FC_THRESHOLD_1_PIPE0 */ "", 34649 /* IDB_OBM0_48_FC_THRESHOLD_PIPE0 */ "", 34650 /* IDB_OBM0_48_FLOW_CONTROL_CONFIG */ "", 34651 /* IDB_OBM0_48_FLOW_CONTROL_CONFIG_PIPE0 */ "", 34652 /* IDB_OBM0_48_FLOW_CONTROL_EVENT_COUNT */ "", 34653 /* IDB_OBM0_48_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 34654 /* IDB_OBM0_48_INNER_TPID */ "", 34655 /* IDB_OBM0_48_INNER_TPID_PIPE0 */ "", 34656 /* IDB_OBM0_48_LOSSLESS0_BYTE_DROP_COUNT */ "", 34657 /* IDB_OBM0_48_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 34658 /* IDB_OBM0_48_LOSSLESS0_PKT_DROP_COUNT */ "", 34659 /* IDB_OBM0_48_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 34660 /* IDB_OBM0_48_LOSSLESS1_BYTE_DROP_COUNT */ "", 34661 /* IDB_OBM0_48_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 34662 /* IDB_OBM0_48_LOSSLESS1_PKT_DROP_COUNT */ "", 34663 /* IDB_OBM0_48_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 34664 /* IDB_OBM0_48_LOSSY_HI_BYTE_DROP_COUNT */ "", 34665 /* IDB_OBM0_48_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 34666 /* IDB_OBM0_48_LOSSY_HI_PKT_DROP_COUNT */ "", 34667 /* IDB_OBM0_48_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 34668 /* IDB_OBM0_48_LOSSY_LO_BYTE_DROP_COUNT */ "", 34669 /* IDB_OBM0_48_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 34670 /* IDB_OBM0_48_LOSSY_LO_PKT_DROP_COUNT */ "", 34671 /* IDB_OBM0_48_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 34672 /* IDB_OBM0_48_MAX_USAGE */ "IDB_OBM0_48_MAX_USAGE", 34673 /* IDB_OBM0_48_MAX_USAGE_PIPE0 */ "IDB_OBM0_48_MAX_USAGE_PIPE0", 34674 /* IDB_OBM0_48_MAX_USAGE_SELECT */ "", 34675 /* IDB_OBM0_48_MAX_USAGE_SELECT_PIPE0 */ "", 34676 /* IDB_OBM0_48_NIV_ETHERTYPE */ "", 34677 /* IDB_OBM0_48_NIV_ETHERTYPE_PIPE0 */ "", 34678 /* IDB_OBM0_48_OUTER_TPID */ "", 34679 /* IDB_OBM0_48_OUTER_TPID_0 */ "", 34680 /* IDB_OBM0_48_OUTER_TPID_1 */ "", 34681 /* IDB_OBM0_48_OUTER_TPID_2 */ "", 34682 /* IDB_OBM0_48_OUTER_TPID_3 */ "", 34683 /* IDB_OBM0_48_OUTER_TPID_0_PIPE0 */ "", 34684 /* IDB_OBM0_48_OUTER_TPID_1_PIPE0 */ "", 34685 /* IDB_OBM0_48_OUTER_TPID_2_PIPE0 */ "", 34686 /* IDB_OBM0_48_OUTER_TPID_3_PIPE0 */ "", 34687 /* IDB_OBM0_48_OUTER_TPID_PIPE0 */ "", 34688 /* IDB_OBM0_48_OVERSUB_MON_ECC_STATUS */ "IDB_OBM0_48_OVERSUB_MON_ECC_STATUS", 34689 /* IDB_OBM0_48_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM0_48_OVERSUB_MON_ECC_STATUS_PIPE0", 34690 /* IDB_OBM0_48_PE_ETHERTYPE */ "", 34691 /* IDB_OBM0_48_PE_ETHERTYPE_PIPE0 */ "", 34692 /* IDB_OBM0_48_PORT_CONFIG */ "", 34693 /* IDB_OBM0_48_PORT_CONFIG_PIPE0 */ "", 34694 /* IDB_OBM0_48_PROTOCOL_CONTROL_0 */ "", 34695 /* IDB_OBM0_48_PROTOCOL_CONTROL_1 */ "", 34696 /* IDB_OBM0_48_PROTOCOL_CONTROL_2 */ "", 34697 /* IDB_OBM0_48_PROTOCOL_CONTROL_0_PIPE0 */ "", 34698 /* IDB_OBM0_48_PROTOCOL_CONTROL_1_PIPE0 */ "", 34699 /* IDB_OBM0_48_PROTOCOL_CONTROL_2_PIPE0 */ "", 34700 /* IDB_OBM0_48_RAM_CONTROL */ "IDB_OBM0_48_RAM_CONTROL", 34701 /* IDB_OBM0_48_RAM_CONTROL_PIPE0 */ "IDB_OBM0_48_RAM_CONTROL_PIPE0", 34702 /* IDB_OBM0_48_SER_CONTROL */ "IDB_OBM0_48_SER_CONTROL", 34703 /* IDB_OBM0_48_SER_CONTROL_PIPE0 */ "IDB_OBM0_48_SER_CONTROL_PIPE0", 34704 /* IDB_OBM0_48_SHARED_CONFIG */ "IDB_OBM0_48_SHARED_CONFIG", 34705 /* IDB_OBM0_48_SHARED_CONFIG_PIPE0 */ "IDB_OBM0_48_SHARED_CONFIG_PIPE0", 34706 /* IDB_OBM0_48_THRESHOLD */ "", 34707 /* IDB_OBM0_48_THRESHOLD_1 */ "", 34708 /* IDB_OBM0_48_THRESHOLD_1_PIPE0 */ "", 34709 /* IDB_OBM0_48_THRESHOLD_PIPE0 */ "", 34710 /* IDB_OBM0_48_USAGE */ "", 34711 /* IDB_OBM0_48_USAGE_PIPE0 */ "", 34712 /* IDB_OBM0_BANK_CONFIG */ "IDB_OBM0_BANK_CONFIG", 34713 /* IDB_OBM0_BANK_CONFIG_PIPE0 */ "IDB_OBM0_BANK_CONFIG_PIPE0", 34714 /* IDB_OBM0_BANK_CONFIG_PIPE1 */ "IDB_OBM0_BANK_CONFIG_PIPE1", 34715 /* IDB_OBM0_BANK_CONFIG_PIPE2 */ "IDB_OBM0_BANK_CONFIG_PIPE2", 34716 /* IDB_OBM0_BANK_CONFIG_PIPE3 */ "IDB_OBM0_BANK_CONFIG_PIPE3", 34717 /* IDB_OBM0_BUCKET_COUNT_CONFIG */ "", 34718 /* IDB_OBM0_BUFFER_CONFIG */ "", 34719 /* IDB_OBM0_BUFFER_CONFIG_PIPE0 */ "", 34720 /* IDB_OBM0_BUFFER_CONFIG_PIPE1 */ "", 34721 /* IDB_OBM0_BUFFER_CONFIG_PIPE2 */ "", 34722 /* IDB_OBM0_BUFFER_CONFIG_PIPE3 */ "", 34723 /* IDB_OBM0_BUFFER_CONFIG_PIPE4 */ "", 34724 /* IDB_OBM0_BUFFER_CONFIG_PIPE5 */ "", 34725 /* IDB_OBM0_BUFFER_CONFIG_PIPE6 */ "", 34726 /* IDB_OBM0_BUFFER_CONFIG_PIPE7 */ "", 34727 /* IDB_OBM0_CA_CONTROL */ "IDB_OBM0_CA_CONTROL", 34728 /* IDB_OBM0_CA_CONTROL_PIPE0 */ "IDB_OBM0_CA_CONTROL_PIPE0", 34729 /* IDB_OBM0_CA_CONTROL_PIPE1 */ "IDB_OBM0_CA_CONTROL_PIPE1", 34730 /* IDB_OBM0_CA_CONTROL_PIPE2 */ "IDB_OBM0_CA_CONTROL_PIPE2", 34731 /* IDB_OBM0_CA_CONTROL_PIPE3 */ "IDB_OBM0_CA_CONTROL_PIPE3", 34732 /* IDB_OBM0_CA_CT_CONTROL */ "IDB_OBM0_CA_CT_CONTROL", 34733 /* IDB_OBM0_CA_CT_CONTROL_PIPE0 */ "IDB_OBM0_CA_CT_CONTROL_PIPE0", 34734 /* IDB_OBM0_CA_CT_CONTROL_PIPE1 */ "IDB_OBM0_CA_CT_CONTROL_PIPE1", 34735 /* IDB_OBM0_CA_CT_CONTROL_PIPE2 */ "IDB_OBM0_CA_CT_CONTROL_PIPE2", 34736 /* IDB_OBM0_CA_CT_CONTROL_PIPE3 */ "IDB_OBM0_CA_CT_CONTROL_PIPE3", 34737 /* IDB_OBM0_CA_ECC_STATUS */ "IDB_OBM0_CA_ECC_STATUS", 34738 /* IDB_OBM0_CA_ECC_STATUS_PIPE0 */ "IDB_OBM0_CA_ECC_STATUS_PIPE0", 34739 /* IDB_OBM0_CA_ECC_STATUS_PIPE1 */ "IDB_OBM0_CA_ECC_STATUS_PIPE1", 34740 /* IDB_OBM0_CA_ECC_STATUS_PIPE2 */ "IDB_OBM0_CA_ECC_STATUS_PIPE2", 34741 /* IDB_OBM0_CA_ECC_STATUS_PIPE3 */ "IDB_OBM0_CA_ECC_STATUS_PIPE3", 34742 /* IDB_OBM0_CA_HW_CONTROL */ "IDB_OBM0_CA_HW_CONTROL", 34743 /* IDB_OBM0_CA_HW_CONTROL_PIPE0 */ "IDB_OBM0_CA_HW_CONTROL_PIPE0", 34744 /* IDB_OBM0_CA_HW_CONTROL_PIPE1 */ "IDB_OBM0_CA_HW_CONTROL_PIPE1", 34745 /* IDB_OBM0_CA_HW_CONTROL_PIPE2 */ "IDB_OBM0_CA_HW_CONTROL_PIPE2", 34746 /* IDB_OBM0_CA_HW_CONTROL_PIPE3 */ "IDB_OBM0_CA_HW_CONTROL_PIPE3", 34747 /* IDB_OBM0_CA_HW_STATUS */ "IDB_OBM0_CA_HW_STATUS", 34748 /* IDB_OBM0_CA_HW_STATUS_PIPE0 */ "IDB_OBM0_CA_HW_STATUS_PIPE0", 34749 /* IDB_OBM0_CA_HW_STATUS_PIPE1 */ "IDB_OBM0_CA_HW_STATUS_PIPE1", 34750 /* IDB_OBM0_CA_HW_STATUS_PIPE2 */ "IDB_OBM0_CA_HW_STATUS_PIPE2", 34751 /* IDB_OBM0_CA_HW_STATUS_PIPE3 */ "IDB_OBM0_CA_HW_STATUS_PIPE3", 34752 /* IDB_OBM0_CA_POINTER_STATUS */ "IDB_OBM0_CA_POINTER_STATUS", 34753 /* IDB_OBM0_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM0_CA_POINTER_STATUS_PIPE0", 34754 /* IDB_OBM0_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM0_CA_POINTER_STATUS_PIPE1", 34755 /* IDB_OBM0_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM0_CA_POINTER_STATUS_PIPE2", 34756 /* IDB_OBM0_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM0_CA_POINTER_STATUS_PIPE3", 34757 /* IDB_OBM0_CONTROL */ "IDB_OBM0_CONTROL", 34758 /* IDB_OBM0_CONTROL_PIPE0 */ "IDB_OBM0_CONTROL_PIPE0", 34759 /* IDB_OBM0_CONTROL_PIPE1 */ "IDB_OBM0_CONTROL_PIPE1", 34760 /* IDB_OBM0_CONTROL_PIPE2 */ "IDB_OBM0_CONTROL_PIPE2", 34761 /* IDB_OBM0_CONTROL_PIPE3 */ "IDB_OBM0_CONTROL_PIPE3", 34762 /* IDB_OBM0_CONTROL_PIPE4 */ "IDB_OBM0_CONTROL_PIPE4", 34763 /* IDB_OBM0_CONTROL_PIPE5 */ "IDB_OBM0_CONTROL_PIPE5", 34764 /* IDB_OBM0_CONTROL_PIPE6 */ "IDB_OBM0_CONTROL_PIPE6", 34765 /* IDB_OBM0_CONTROL_PIPE7 */ "IDB_OBM0_CONTROL_PIPE7", 34766 /* IDB_OBM0_CTRL_ECC_STATUS */ "IDB_OBM0_CTRL_ECC_STATUS", 34767 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE0 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE0", 34768 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE1 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE1", 34769 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE2 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE2", 34770 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE3 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE3", 34771 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE4 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE4", 34772 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE5 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE5", 34773 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE6 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE6", 34774 /* IDB_OBM0_CTRL_ECC_STATUS_PIPE7 */ "IDB_OBM0_CTRL_ECC_STATUS_PIPE7", 34775 /* IDB_OBM0_CT_THRESHOLD */ "", 34776 /* IDB_OBM0_CT_THRESHOLD_PIPE0 */ "", 34777 /* IDB_OBM0_CT_THRESHOLD_PIPE1 */ "", 34778 /* IDB_OBM0_CT_THRESHOLD_PIPE2 */ "", 34779 /* IDB_OBM0_CT_THRESHOLD_PIPE3 */ "", 34780 /* IDB_OBM0_CT_THRESHOLD_PIPE4 */ "", 34781 /* IDB_OBM0_CT_THRESHOLD_PIPE5 */ "", 34782 /* IDB_OBM0_CT_THRESHOLD_PIPE6 */ "", 34783 /* IDB_OBM0_CT_THRESHOLD_PIPE7 */ "", 34784 /* IDB_OBM0_DATA_ECC_STATUS */ "IDB_OBM0_DATA_ECC_STATUS", 34785 /* IDB_OBM0_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE0", 34786 /* IDB_OBM0_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE1", 34787 /* IDB_OBM0_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE2", 34788 /* IDB_OBM0_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE3", 34789 /* IDB_OBM0_DATA_ECC_STATUS_PIPE4 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE4", 34790 /* IDB_OBM0_DATA_ECC_STATUS_PIPE5 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE5", 34791 /* IDB_OBM0_DATA_ECC_STATUS_PIPE6 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE6", 34792 /* IDB_OBM0_DATA_ECC_STATUS_PIPE7 */ "IDB_OBM0_DATA_ECC_STATUS_PIPE7", 34793 /* IDB_OBM0_DBG_A */ "IDB_OBM0_FORCE_SAF_CONFIG", 34794 /* IDB_OBM0_DBG_A_PIPE0 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE0", 34795 /* IDB_OBM0_DBG_A_PIPE1 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE1", 34796 /* IDB_OBM0_DBG_A_PIPE2 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE2", 34797 /* IDB_OBM0_DBG_A_PIPE3 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE3", 34798 /* IDB_OBM0_DBG_A_PIPE4 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE4", 34799 /* IDB_OBM0_DBG_A_PIPE5 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE5", 34800 /* IDB_OBM0_DBG_A_PIPE6 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE6", 34801 /* IDB_OBM0_DBG_A_PIPE7 */ "IDB_OBM0_FORCE_SAF_CONFIG_PIPE7", 34802 /* IDB_OBM0_DBG_B */ "IDB_OBM0_LAG_DETECTION_CONFIG", 34803 /* IDB_OBM0_DBG_B_PIPE0 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE0", 34804 /* IDB_OBM0_DBG_B_PIPE1 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE1", 34805 /* IDB_OBM0_DBG_B_PIPE2 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE2", 34806 /* IDB_OBM0_DBG_B_PIPE3 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE3", 34807 /* IDB_OBM0_DBG_B_PIPE4 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE4", 34808 /* IDB_OBM0_DBG_B_PIPE5 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE5", 34809 /* IDB_OBM0_DBG_B_PIPE6 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE6", 34810 /* IDB_OBM0_DBG_B_PIPE7 */ "IDB_OBM0_LAG_DETECTION_CONFIG_PIPE7", 34811 /* IDB_OBM0_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 34812 /* IDB_OBM0_EXPRESS_ARRIVAL_PKT_COUNT */ "", 34813 /* IDB_OBM0_EXPRESS_BYTE_DROP_COUNT */ "", 34814 /* IDB_OBM0_EXPRESS_FLOW_CONTROL_CONFIG */ "", 34815 /* IDB_OBM0_EXPRESS_PKT_DROP_COUNT */ "", 34816 /* IDB_OBM0_FC_THRESHOLD */ "", 34817 /* IDB_OBM0_FC_THRESHOLD_0 */ "", 34818 /* IDB_OBM0_FC_THRESHOLD_1 */ "", 34819 /* IDB_OBM0_FC_THRESHOLD_1_PIPE0 */ "", 34820 /* IDB_OBM0_FC_THRESHOLD_1_PIPE1 */ "", 34821 /* IDB_OBM0_FC_THRESHOLD_1_PIPE2 */ "", 34822 /* IDB_OBM0_FC_THRESHOLD_1_PIPE3 */ "", 34823 /* IDB_OBM0_FC_THRESHOLD_1_PIPE4 */ "", 34824 /* IDB_OBM0_FC_THRESHOLD_1_PIPE5 */ "", 34825 /* IDB_OBM0_FC_THRESHOLD_1_PIPE6 */ "", 34826 /* IDB_OBM0_FC_THRESHOLD_1_PIPE7 */ "", 34827 /* IDB_OBM0_FC_THRESHOLD_PIPE0 */ "", 34828 /* IDB_OBM0_FC_THRESHOLD_PIPE1 */ "", 34829 /* IDB_OBM0_FC_THRESHOLD_PIPE2 */ "", 34830 /* IDB_OBM0_FC_THRESHOLD_PIPE3 */ "", 34831 /* IDB_OBM0_FC_THRESHOLD_PIPE4 */ "", 34832 /* IDB_OBM0_FC_THRESHOLD_PIPE5 */ "", 34833 /* IDB_OBM0_FC_THRESHOLD_PIPE6 */ "", 34834 /* IDB_OBM0_FC_THRESHOLD_PIPE7 */ "", 34835 /* IDB_OBM0_FLOW_CONTROL_CONFIG */ "", 34836 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE0 */ "", 34837 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE1 */ "", 34838 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE2 */ "", 34839 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE3 */ "", 34840 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE4 */ "", 34841 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE5 */ "", 34842 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE6 */ "", 34843 /* IDB_OBM0_FLOW_CONTROL_CONFIG_PIPE7 */ "", 34844 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT */ "", 34845 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 34846 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 34847 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 34848 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 34849 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE4 */ "", 34850 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE5 */ "", 34851 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE6 */ "", 34852 /* IDB_OBM0_FLOW_CONTROL_EVENT_COUNT_PIPE7 */ "", 34853 /* IDB_OBM0_FORCE_SAF_STATUS */ "", 34854 /* IDB_OBM0_FORCE_SAF_STATUS_PIPE0 */ "", 34855 /* IDB_OBM0_FORCE_SAF_STATUS_PIPE1 */ "", 34856 /* IDB_OBM0_HW_STATUS */ "IDB_OBM0_HW_STATUS", 34857 /* IDB_OBM0_HW_STATUS_PIPE0 */ "IDB_OBM0_HW_STATUS_PIPE0", 34858 /* IDB_OBM0_HW_STATUS_PIPE1 */ "IDB_OBM0_HW_STATUS_PIPE1", 34859 /* IDB_OBM0_HW_STATUS_PIPE2 */ "IDB_OBM0_HW_STATUS_PIPE2", 34860 /* IDB_OBM0_HW_STATUS_PIPE3 */ "IDB_OBM0_HW_STATUS_PIPE3", 34861 /* IDB_OBM0_HW_STATUS_PIPE4 */ "IDB_OBM0_HW_STATUS_PIPE4", 34862 /* IDB_OBM0_HW_STATUS_PIPE5 */ "IDB_OBM0_HW_STATUS_PIPE5", 34863 /* IDB_OBM0_HW_STATUS_PIPE6 */ "IDB_OBM0_HW_STATUS_PIPE6", 34864 /* IDB_OBM0_HW_STATUS_PIPE7 */ "IDB_OBM0_HW_STATUS_PIPE7", 34865 /* IDB_OBM0_INNER_TPID */ "", 34866 /* IDB_OBM0_INNER_TPID_PIPE0 */ "", 34867 /* IDB_OBM0_INNER_TPID_PIPE1 */ "", 34868 /* IDB_OBM0_INNER_TPID_PIPE2 */ "", 34869 /* IDB_OBM0_INNER_TPID_PIPE3 */ "", 34870 /* IDB_OBM0_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 34871 /* IDB_OBM0_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 34872 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT */ "", 34873 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 34874 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 34875 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 34876 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 34877 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE4 */ "", 34878 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE5 */ "", 34879 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE6 */ "", 34880 /* IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNT_PIPE7 */ "", 34881 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT */ "", 34882 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 34883 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 34884 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 34885 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 34886 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE4 */ "", 34887 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE5 */ "", 34888 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE6 */ "", 34889 /* IDB_OBM0_LOSSLESS0_PKT_DROP_COUNT_PIPE7 */ "", 34890 /* IDB_OBM0_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 34891 /* IDB_OBM0_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 34892 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT */ "", 34893 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 34894 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 34895 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 34896 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 34897 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE4 */ "", 34898 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE5 */ "", 34899 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE6 */ "", 34900 /* IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNT_PIPE7 */ "", 34901 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT */ "", 34902 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 34903 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 34904 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 34905 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 34906 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE4 */ "", 34907 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE5 */ "", 34908 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE6 */ "", 34909 /* IDB_OBM0_LOSSLESS1_PKT_DROP_COUNT_PIPE7 */ "", 34910 /* IDB_OBM0_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 34911 /* IDB_OBM0_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 34912 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT */ "", 34913 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 34914 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 34915 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 34916 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 34917 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE4 */ "", 34918 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE5 */ "", 34919 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE6 */ "", 34920 /* IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNT_PIPE7 */ "", 34921 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT */ "", 34922 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 34923 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 34924 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 34925 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 34926 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE4 */ "", 34927 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE5 */ "", 34928 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE6 */ "", 34929 /* IDB_OBM0_LOSSY_HI_PKT_DROP_COUNT_PIPE7 */ "", 34930 /* IDB_OBM0_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 34931 /* IDB_OBM0_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 34932 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT */ "", 34933 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 34934 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 34935 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 34936 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 34937 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE4 */ "", 34938 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE5 */ "", 34939 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE6 */ "", 34940 /* IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNT_PIPE7 */ "", 34941 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT */ "", 34942 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 34943 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 34944 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 34945 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 34946 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE4 */ "", 34947 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE5 */ "", 34948 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE6 */ "", 34949 /* IDB_OBM0_LOSSY_LO_PKT_DROP_COUNT_PIPE7 */ "", 34950 /* IDB_OBM0_MAX_USAGE */ "IDB_OBM0_MAX_USAGE", 34951 /* IDB_OBM0_MAX_USAGE_1 */ "IDB_OBM0_MAX_USAGE_1", 34952 /* IDB_OBM0_MAX_USAGE_2 */ "IDB_OBM0_MAX_USAGE_2", 34953 /* IDB_OBM0_MAX_USAGE_1_PIPE0 */ "IDB_OBM0_MAX_USAGE_1_PIPE0", 34954 /* IDB_OBM0_MAX_USAGE_1_PIPE1 */ "IDB_OBM0_MAX_USAGE_1_PIPE1", 34955 /* IDB_OBM0_MAX_USAGE_1_PIPE2 */ "IDB_OBM0_MAX_USAGE_1_PIPE2", 34956 /* IDB_OBM0_MAX_USAGE_1_PIPE3 */ "IDB_OBM0_MAX_USAGE_1_PIPE3", 34957 /* IDB_OBM0_MAX_USAGE_1_PIPE4 */ "IDB_OBM0_MAX_USAGE_1_PIPE4", 34958 /* IDB_OBM0_MAX_USAGE_1_PIPE5 */ "IDB_OBM0_MAX_USAGE_1_PIPE5", 34959 /* IDB_OBM0_MAX_USAGE_1_PIPE6 */ "IDB_OBM0_MAX_USAGE_1_PIPE6", 34960 /* IDB_OBM0_MAX_USAGE_1_PIPE7 */ "IDB_OBM0_MAX_USAGE_1_PIPE7", 34961 /* IDB_OBM0_MAX_USAGE_2_PIPE0 */ "IDB_OBM0_MAX_USAGE_2_PIPE0", 34962 /* IDB_OBM0_MAX_USAGE_2_PIPE1 */ "IDB_OBM0_MAX_USAGE_2_PIPE1", 34963 /* IDB_OBM0_MAX_USAGE_2_PIPE2 */ "IDB_OBM0_MAX_USAGE_2_PIPE2", 34964 /* IDB_OBM0_MAX_USAGE_2_PIPE3 */ "IDB_OBM0_MAX_USAGE_2_PIPE3", 34965 /* IDB_OBM0_MAX_USAGE_2_PIPE4 */ "IDB_OBM0_MAX_USAGE_2_PIPE4", 34966 /* IDB_OBM0_MAX_USAGE_2_PIPE5 */ "IDB_OBM0_MAX_USAGE_2_PIPE5", 34967 /* IDB_OBM0_MAX_USAGE_2_PIPE6 */ "IDB_OBM0_MAX_USAGE_2_PIPE6", 34968 /* IDB_OBM0_MAX_USAGE_2_PIPE7 */ "IDB_OBM0_MAX_USAGE_2_PIPE7", 34969 /* IDB_OBM0_MAX_USAGE_PIPE0 */ "IDB_OBM0_MAX_USAGE_PIPE0", 34970 /* IDB_OBM0_MAX_USAGE_PIPE1 */ "IDB_OBM0_MAX_USAGE_PIPE1", 34971 /* IDB_OBM0_MAX_USAGE_PIPE2 */ "IDB_OBM0_MAX_USAGE_PIPE2", 34972 /* IDB_OBM0_MAX_USAGE_PIPE3 */ "IDB_OBM0_MAX_USAGE_PIPE3", 34973 /* IDB_OBM0_MAX_USAGE_PIPE4 */ "IDB_OBM0_MAX_USAGE_PIPE4", 34974 /* IDB_OBM0_MAX_USAGE_PIPE5 */ "IDB_OBM0_MAX_USAGE_PIPE5", 34975 /* IDB_OBM0_MAX_USAGE_PIPE6 */ "IDB_OBM0_MAX_USAGE_PIPE6", 34976 /* IDB_OBM0_MAX_USAGE_PIPE7 */ "IDB_OBM0_MAX_USAGE_PIPE7", 34977 /* IDB_OBM0_MAX_USAGE_SELECT */ "", 34978 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE0 */ "", 34979 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE1 */ "", 34980 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE2 */ "", 34981 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE3 */ "", 34982 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE4 */ "", 34983 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE5 */ "", 34984 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE6 */ "", 34985 /* IDB_OBM0_MAX_USAGE_SELECT_PIPE7 */ "", 34986 /* IDB_OBM0_MONITOR_STATS_CONFIG */ "", 34987 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE0 */ "", 34988 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE1 */ "", 34989 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE2 */ "", 34990 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE3 */ "", 34991 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE4 */ "", 34992 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE5 */ "", 34993 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE6 */ "", 34994 /* IDB_OBM0_MONITOR_STATS_CONFIG_PIPE7 */ "", 34995 /* IDB_OBM0_NIV_ETHERTYPE */ "", 34996 /* IDB_OBM0_NIV_ETHERTYPE_PIPE0 */ "", 34997 /* IDB_OBM0_NIV_ETHERTYPE_PIPE1 */ "", 34998 /* IDB_OBM0_NIV_ETHERTYPE_PIPE2 */ "", 34999 /* IDB_OBM0_NIV_ETHERTYPE_PIPE3 */ "", 35000 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0 */ "", 35001 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1 */ "", 35002 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE0 */ "", 35003 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE1 */ "", 35004 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE2 */ "", 35005 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE3 */ "", 35006 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE4 */ "", 35007 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE5 */ "", 35008 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE6 */ "", 35009 /* IDB_OBM0_OPAQUE_TAG_CONFIG_0_PIPE7 */ "", 35010 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE0 */ "", 35011 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE1 */ "", 35012 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE2 */ "", 35013 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE3 */ "", 35014 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE4 */ "", 35015 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE5 */ "", 35016 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE6 */ "", 35017 /* IDB_OBM0_OPAQUE_TAG_CONFIG_1_PIPE7 */ "", 35018 /* IDB_OBM0_OUTER_TPID */ "", 35019 /* IDB_OBM0_OUTER_TPID_0 */ "", 35020 /* IDB_OBM0_OUTER_TPID_1 */ "", 35021 /* IDB_OBM0_OUTER_TPID_2 */ "", 35022 /* IDB_OBM0_OUTER_TPID_3 */ "", 35023 /* IDB_OBM0_OUTER_TPID_0_PIPE0 */ "", 35024 /* IDB_OBM0_OUTER_TPID_0_PIPE1 */ "", 35025 /* IDB_OBM0_OUTER_TPID_0_PIPE2 */ "", 35026 /* IDB_OBM0_OUTER_TPID_0_PIPE3 */ "", 35027 /* IDB_OBM0_OUTER_TPID_0_PIPE4 */ "", 35028 /* IDB_OBM0_OUTER_TPID_0_PIPE5 */ "", 35029 /* IDB_OBM0_OUTER_TPID_0_PIPE6 */ "", 35030 /* IDB_OBM0_OUTER_TPID_0_PIPE7 */ "", 35031 /* IDB_OBM0_OUTER_TPID_1_PIPE0 */ "", 35032 /* IDB_OBM0_OUTER_TPID_1_PIPE1 */ "", 35033 /* IDB_OBM0_OUTER_TPID_1_PIPE2 */ "", 35034 /* IDB_OBM0_OUTER_TPID_1_PIPE3 */ "", 35035 /* IDB_OBM0_OUTER_TPID_1_PIPE4 */ "", 35036 /* IDB_OBM0_OUTER_TPID_1_PIPE5 */ "", 35037 /* IDB_OBM0_OUTER_TPID_1_PIPE6 */ "", 35038 /* IDB_OBM0_OUTER_TPID_1_PIPE7 */ "", 35039 /* IDB_OBM0_OUTER_TPID_2_PIPE0 */ "", 35040 /* IDB_OBM0_OUTER_TPID_2_PIPE1 */ "", 35041 /* IDB_OBM0_OUTER_TPID_2_PIPE2 */ "", 35042 /* IDB_OBM0_OUTER_TPID_2_PIPE3 */ "", 35043 /* IDB_OBM0_OUTER_TPID_2_PIPE4 */ "", 35044 /* IDB_OBM0_OUTER_TPID_2_PIPE5 */ "", 35045 /* IDB_OBM0_OUTER_TPID_2_PIPE6 */ "", 35046 /* IDB_OBM0_OUTER_TPID_2_PIPE7 */ "", 35047 /* IDB_OBM0_OUTER_TPID_3_PIPE0 */ "", 35048 /* IDB_OBM0_OUTER_TPID_3_PIPE1 */ "", 35049 /* IDB_OBM0_OUTER_TPID_3_PIPE2 */ "", 35050 /* IDB_OBM0_OUTER_TPID_3_PIPE3 */ "", 35051 /* IDB_OBM0_OUTER_TPID_3_PIPE4 */ "", 35052 /* IDB_OBM0_OUTER_TPID_3_PIPE5 */ "", 35053 /* IDB_OBM0_OUTER_TPID_3_PIPE6 */ "", 35054 /* IDB_OBM0_OUTER_TPID_3_PIPE7 */ "", 35055 /* IDB_OBM0_OUTER_TPID_PIPE0 */ "", 35056 /* IDB_OBM0_OUTER_TPID_PIPE1 */ "", 35057 /* IDB_OBM0_OUTER_TPID_PIPE2 */ "", 35058 /* IDB_OBM0_OUTER_TPID_PIPE3 */ "", 35059 /* IDB_OBM0_OUTER_TPID_PIPE4 */ "", 35060 /* IDB_OBM0_OUTER_TPID_PIPE5 */ "", 35061 /* IDB_OBM0_OUTER_TPID_PIPE6 */ "", 35062 /* IDB_OBM0_OUTER_TPID_PIPE7 */ "", 35063 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS", 35064 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE0", 35065 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE1", 35066 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE2", 35067 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE3", 35068 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE4 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE4", 35069 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE5 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE5", 35070 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE6 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE6", 35071 /* IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE7 */ "IDB_OBM0_OVERSUB_MON_ECC_STATUS_PIPE7", 35072 /* IDB_OBM0_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM0_OVERSUB_MON_PARITY_STATUS", 35073 /* IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE0", 35074 /* IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE1", 35075 /* IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE2", 35076 /* IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM0_OVERSUB_MON_PARITY_STATUS_PIPE3", 35077 /* IDB_OBM0_PE_ETHERTYPE */ "", 35078 /* IDB_OBM0_PE_ETHERTYPE_PIPE0 */ "", 35079 /* IDB_OBM0_PE_ETHERTYPE_PIPE1 */ "", 35080 /* IDB_OBM0_PE_ETHERTYPE_PIPE2 */ "", 35081 /* IDB_OBM0_PE_ETHERTYPE_PIPE3 */ "", 35082 /* IDB_OBM0_PORT_CONFIG */ "", 35083 /* IDB_OBM0_PORT_CONFIG_PIPE0 */ "", 35084 /* IDB_OBM0_PORT_CONFIG_PIPE1 */ "", 35085 /* IDB_OBM0_PORT_CONFIG_PIPE2 */ "", 35086 /* IDB_OBM0_PORT_CONFIG_PIPE3 */ "", 35087 /* IDB_OBM0_PORT_CONFIG_PIPE4 */ "", 35088 /* IDB_OBM0_PORT_CONFIG_PIPE5 */ "", 35089 /* IDB_OBM0_PORT_CONFIG_PIPE6 */ "", 35090 /* IDB_OBM0_PORT_CONFIG_PIPE7 */ "", 35091 /* IDB_OBM0_POWER_SAVE */ "IDB_OBM0_POWER_SAVE", 35092 /* IDB_OBM0_PROTOCOL_CONTROL_0 */ "", 35093 /* IDB_OBM0_PROTOCOL_CONTROL_1 */ "", 35094 /* IDB_OBM0_PROTOCOL_CONTROL_2 */ "", 35095 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE0 */ "", 35096 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE1 */ "", 35097 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE2 */ "", 35098 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE3 */ "", 35099 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE4 */ "", 35100 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE5 */ "", 35101 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE6 */ "", 35102 /* IDB_OBM0_PROTOCOL_CONTROL_0_PIPE7 */ "", 35103 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE0 */ "", 35104 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE1 */ "", 35105 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE2 */ "", 35106 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE3 */ "", 35107 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE4 */ "", 35108 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE5 */ "", 35109 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE6 */ "", 35110 /* IDB_OBM0_PROTOCOL_CONTROL_1_PIPE7 */ "", 35111 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE0 */ "", 35112 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE1 */ "", 35113 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE2 */ "", 35114 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE3 */ "", 35115 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE4 */ "", 35116 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE5 */ "", 35117 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE6 */ "", 35118 /* IDB_OBM0_PROTOCOL_CONTROL_2_PIPE7 */ "", 35119 /* IDB_OBM0_QUEUE_ECC_STATUS */ "IDB_OBM0_QUEUE_ECC_STATUS", 35120 /* IDB_OBM0_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM0_QUEUE_ECC_STATUS_PIPE0", 35121 /* IDB_OBM0_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM0_QUEUE_ECC_STATUS_PIPE1", 35122 /* IDB_OBM0_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM0_QUEUE_ECC_STATUS_PIPE2", 35123 /* IDB_OBM0_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM0_QUEUE_ECC_STATUS_PIPE3", 35124 /* IDB_OBM0_QUEUE_SER_CONTROL */ "IDB_OBM0_QUEUE_SER_CONTROL", 35125 /* IDB_OBM0_Q_BANK_CONFIG */ "IDB_OBM0_Q_BANK_CONFIG", 35126 /* IDB_OBM0_Q_BANK_CONFIG_PIPE0 */ "IDB_OBM0_Q_BANK_CONFIG_PIPE0", 35127 /* IDB_OBM0_Q_BUFFER_CONFIG */ "", 35128 /* IDB_OBM0_Q_BUFFER_CONFIG_PIPE0 */ "", 35129 /* IDB_OBM0_Q_CA_CONTROL */ "IDB_OBM0_Q_CA_CONTROL", 35130 /* IDB_OBM0_Q_CA_CONTROL_PIPE0 */ "IDB_OBM0_Q_CA_CONTROL_PIPE0", 35131 /* IDB_OBM0_Q_CA_ECC_STATUS */ "IDB_OBM0_Q_CA_ECC_STATUS", 35132 /* IDB_OBM0_Q_CA_ECC_STATUS_PIPE0 */ "IDB_OBM0_Q_CA_ECC_STATUS_PIPE0", 35133 /* IDB_OBM0_Q_CA_HW_STATUS */ "", 35134 /* IDB_OBM0_Q_CA_HW_STATUS_PIPE0 */ "", 35135 /* IDB_OBM0_Q_CA_POINTER_STATUS */ "", 35136 /* IDB_OBM0_Q_CA_POINTER_STATUS_PIPE0 */ "", 35137 /* IDB_OBM0_Q_CONTROL */ "", 35138 /* IDB_OBM0_Q_CONTROL_PIPE0 */ "", 35139 /* IDB_OBM0_Q_CTRL */ "IDB_OBM0_Q_CTRL", 35140 /* IDB_OBM0_Q_CTRL_PIPE0 */ "IDB_OBM0_Q_CTRL_PIPE0", 35141 /* IDB_OBM0_Q_DATA_ECC_STATUS */ "IDB_OBM0_Q_DATA_ECC_STATUS", 35142 /* IDB_OBM0_Q_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM0_Q_DATA_ECC_STATUS_PIPE0", 35143 /* IDB_OBM0_Q_FC_THRESHOLD */ "", 35144 /* IDB_OBM0_Q_FC_THRESHOLD_1 */ "", 35145 /* IDB_OBM0_Q_FC_THRESHOLD_1_PIPE0 */ "", 35146 /* IDB_OBM0_Q_FC_THRESHOLD_PIPE0 */ "", 35147 /* IDB_OBM0_Q_FLOW_CONTROL_CONFIG */ "", 35148 /* IDB_OBM0_Q_FLOW_CONTROL_CONFIG_PIPE0 */ "", 35149 /* IDB_OBM0_Q_FLOW_CONTROL_EVENT_COUNT */ "", 35150 /* IDB_OBM0_Q_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 35151 /* IDB_OBM0_Q_INNER_TPID */ "", 35152 /* IDB_OBM0_Q_INNER_TPID_PIPE0 */ "", 35153 /* IDB_OBM0_Q_LOSSLESS0_BYTE_DROP_COUNT */ "", 35154 /* IDB_OBM0_Q_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 35155 /* IDB_OBM0_Q_LOSSLESS0_PKT_DROP_COUNT */ "", 35156 /* IDB_OBM0_Q_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 35157 /* IDB_OBM0_Q_LOSSLESS1_BYTE_DROP_COUNT */ "", 35158 /* IDB_OBM0_Q_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 35159 /* IDB_OBM0_Q_LOSSLESS1_PKT_DROP_COUNT */ "", 35160 /* IDB_OBM0_Q_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 35161 /* IDB_OBM0_Q_LOSSY_HI_BYTE_DROP_COUNT */ "", 35162 /* IDB_OBM0_Q_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 35163 /* IDB_OBM0_Q_LOSSY_HI_PKT_DROP_COUNT */ "", 35164 /* IDB_OBM0_Q_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 35165 /* IDB_OBM0_Q_LOSSY_LO_BYTE_DROP_COUNT */ "", 35166 /* IDB_OBM0_Q_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 35167 /* IDB_OBM0_Q_LOSSY_LO_PKT_DROP_COUNT */ "", 35168 /* IDB_OBM0_Q_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 35169 /* IDB_OBM0_Q_MAX_USAGE */ "IDB_OBM0_Q_MAX_USAGE", 35170 /* IDB_OBM0_Q_MAX_USAGE_PIPE0 */ "IDB_OBM0_Q_MAX_USAGE_PIPE0", 35171 /* IDB_OBM0_Q_MAX_USAGE_SELECT */ "", 35172 /* IDB_OBM0_Q_MAX_USAGE_SELECT_PIPE0 */ "", 35173 /* IDB_OBM0_Q_NIV_ETHERTYPE */ "", 35174 /* IDB_OBM0_Q_NIV_ETHERTYPE_PIPE0 */ "", 35175 /* IDB_OBM0_Q_OUTER_TPID */ "", 35176 /* IDB_OBM0_Q_OUTER_TPID_0 */ "", 35177 /* IDB_OBM0_Q_OUTER_TPID_1 */ "", 35178 /* IDB_OBM0_Q_OUTER_TPID_2 */ "", 35179 /* IDB_OBM0_Q_OUTER_TPID_3 */ "", 35180 /* IDB_OBM0_Q_OUTER_TPID_0_PIPE0 */ "", 35181 /* IDB_OBM0_Q_OUTER_TPID_1_PIPE0 */ "", 35182 /* IDB_OBM0_Q_OUTER_TPID_2_PIPE0 */ "", 35183 /* IDB_OBM0_Q_OUTER_TPID_3_PIPE0 */ "", 35184 /* IDB_OBM0_Q_OUTER_TPID_PIPE0 */ "", 35185 /* IDB_OBM0_Q_OVERSUB_MON_ECC_STATUS */ "IDB_OBM0_Q_OVERSUB_MON_ECC_STATUS", 35186 /* IDB_OBM0_Q_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM0_Q_OVERSUB_MON_ECC_STATUS_PIPE0", 35187 /* IDB_OBM0_Q_PE_ETHERTYPE */ "", 35188 /* IDB_OBM0_Q_PE_ETHERTYPE_PIPE0 */ "", 35189 /* IDB_OBM0_Q_PORT_CONFIG */ "", 35190 /* IDB_OBM0_Q_PORT_CONFIG_PIPE0 */ "", 35191 /* IDB_OBM0_Q_PROTOCOL_CONTROL_0 */ "", 35192 /* IDB_OBM0_Q_PROTOCOL_CONTROL_1 */ "", 35193 /* IDB_OBM0_Q_PROTOCOL_CONTROL_2 */ "", 35194 /* IDB_OBM0_Q_PROTOCOL_CONTROL_0_PIPE0 */ "", 35195 /* IDB_OBM0_Q_PROTOCOL_CONTROL_1_PIPE0 */ "", 35196 /* IDB_OBM0_Q_PROTOCOL_CONTROL_2_PIPE0 */ "", 35197 /* IDB_OBM0_Q_RAM_CONTROL */ "IDB_OBM0_Q_RAM_CONTROL", 35198 /* IDB_OBM0_Q_RAM_CONTROL_PIPE0 */ "IDB_OBM0_Q_RAM_CONTROL_PIPE0", 35199 /* IDB_OBM0_Q_SER_CONTROL */ "IDB_OBM0_Q_SER_CONTROL", 35200 /* IDB_OBM0_Q_SER_CONTROL_PIPE0 */ "IDB_OBM0_Q_SER_CONTROL_PIPE0", 35201 /* IDB_OBM0_Q_SHARED_CONFIG */ "IDB_OBM0_Q_SHARED_CONFIG", 35202 /* IDB_OBM0_Q_SHARED_CONFIG_PIPE0 */ "IDB_OBM0_Q_SHARED_CONFIG_PIPE0", 35203 /* IDB_OBM0_Q_THRESHOLD */ "", 35204 /* IDB_OBM0_Q_THRESHOLD_1 */ "", 35205 /* IDB_OBM0_Q_THRESHOLD_1_PIPE0 */ "", 35206 /* IDB_OBM0_Q_THRESHOLD_PIPE0 */ "", 35207 /* IDB_OBM0_Q_USAGE */ "", 35208 /* IDB_OBM0_Q_USAGE_PIPE0 */ "", 35209 /* IDB_OBM0_RAM_CONTROL */ "IDB_OBM0_RAM_CONTROL", 35210 /* IDB_OBM0_RAM_CONTROL_PIPE0 */ "IDB_OBM0_RAM_CONTROL_PIPE0", 35211 /* IDB_OBM0_RAM_CONTROL_PIPE1 */ "IDB_OBM0_RAM_CONTROL_PIPE1", 35212 /* IDB_OBM0_RAM_CONTROL_PIPE2 */ "IDB_OBM0_RAM_CONTROL_PIPE2", 35213 /* IDB_OBM0_RAM_CONTROL_PIPE3 */ "IDB_OBM0_RAM_CONTROL_PIPE3", 35214 /* IDB_OBM0_RAM_CONTROL_PIPE4 */ "IDB_OBM0_RAM_CONTROL_PIPE4", 35215 /* IDB_OBM0_RAM_CONTROL_PIPE5 */ "IDB_OBM0_RAM_CONTROL_PIPE5", 35216 /* IDB_OBM0_RAM_CONTROL_PIPE6 */ "IDB_OBM0_RAM_CONTROL_PIPE6", 35217 /* IDB_OBM0_RAM_CONTROL_PIPE7 */ "IDB_OBM0_RAM_CONTROL_PIPE7", 35218 /* IDB_OBM0_SER_CONTROL */ "IDB_OBM0_SER_CONTROL", 35219 /* IDB_OBM0_SER_CONTROL_PIPE0 */ "IDB_OBM0_SER_CONTROL_PIPE0", 35220 /* IDB_OBM0_SER_CONTROL_PIPE1 */ "IDB_OBM0_SER_CONTROL_PIPE1", 35221 /* IDB_OBM0_SHARED_CONFIG */ "IDB_OBM0_SHARED_CONFIG", 35222 /* IDB_OBM0_SHARED_CONFIG_PIPE0 */ "IDB_OBM0_SHARED_CONFIG_PIPE0", 35223 /* IDB_OBM0_SHARED_CONFIG_PIPE1 */ "IDB_OBM0_SHARED_CONFIG_PIPE1", 35224 /* IDB_OBM0_SHARED_CONFIG_PIPE2 */ "IDB_OBM0_SHARED_CONFIG_PIPE2", 35225 /* IDB_OBM0_SHARED_CONFIG_PIPE3 */ "IDB_OBM0_SHARED_CONFIG_PIPE3", 35226 /* IDB_OBM0_SHARED_CONFIG_PIPE4 */ "IDB_OBM0_SHARED_CONFIG_PIPE4", 35227 /* IDB_OBM0_SHARED_CONFIG_PIPE5 */ "IDB_OBM0_SHARED_CONFIG_PIPE5", 35228 /* IDB_OBM0_SHARED_CONFIG_PIPE6 */ "IDB_OBM0_SHARED_CONFIG_PIPE6", 35229 /* IDB_OBM0_SHARED_CONFIG_PIPE7 */ "IDB_OBM0_SHARED_CONFIG_PIPE7", 35230 /* IDB_OBM0_SHARED_USAGE */ "IDB_OBM0_SHARED_USAGE", 35231 /* IDB_OBM0_SHARED_USAGE_PIPE0 */ "IDB_OBM0_SHARED_USAGE_PIPE0", 35232 /* IDB_OBM0_SHARED_USAGE_PIPE1 */ "IDB_OBM0_SHARED_USAGE_PIPE1", 35233 /* IDB_OBM0_SHARED_USAGE_PIPE2 */ "IDB_OBM0_SHARED_USAGE_PIPE2", 35234 /* IDB_OBM0_SHARED_USAGE_PIPE3 */ "IDB_OBM0_SHARED_USAGE_PIPE3", 35235 /* IDB_OBM0_SPARE_REG */ "IDB_OBM0_SPARE_REG", 35236 /* IDB_OBM0_TDM */ "IDB_OBM0_TDM", 35237 /* IDB_OBM0_TDM_PIPE0 */ "IDB_OBM0_TDM_PIPE0", 35238 /* IDB_OBM0_TDM_PIPE1 */ "IDB_OBM0_TDM_PIPE1", 35239 /* IDB_OBM0_TDM_PIPE2 */ "IDB_OBM0_TDM_PIPE2", 35240 /* IDB_OBM0_TDM_PIPE3 */ "IDB_OBM0_TDM_PIPE3", 35241 /* IDB_OBM0_TDM_PIPE4 */ "IDB_OBM0_TDM_PIPE4", 35242 /* IDB_OBM0_TDM_PIPE5 */ "IDB_OBM0_TDM_PIPE5", 35243 /* IDB_OBM0_TDM_PIPE6 */ "IDB_OBM0_TDM_PIPE6", 35244 /* IDB_OBM0_TDM_PIPE7 */ "IDB_OBM0_TDM_PIPE7", 35245 /* IDB_OBM0_THRESHOLD */ "", 35246 /* IDB_OBM0_THRESHOLD_0 */ "", 35247 /* IDB_OBM0_THRESHOLD_1 */ "", 35248 /* IDB_OBM0_THRESHOLD_1_PIPE0 */ "", 35249 /* IDB_OBM0_THRESHOLD_1_PIPE1 */ "", 35250 /* IDB_OBM0_THRESHOLD_1_PIPE2 */ "", 35251 /* IDB_OBM0_THRESHOLD_1_PIPE3 */ "", 35252 /* IDB_OBM0_THRESHOLD_1_PIPE4 */ "", 35253 /* IDB_OBM0_THRESHOLD_1_PIPE5 */ "", 35254 /* IDB_OBM0_THRESHOLD_1_PIPE6 */ "", 35255 /* IDB_OBM0_THRESHOLD_1_PIPE7 */ "", 35256 /* IDB_OBM0_THRESHOLD_PIPE0 */ "", 35257 /* IDB_OBM0_THRESHOLD_PIPE1 */ "", 35258 /* IDB_OBM0_THRESHOLD_PIPE2 */ "", 35259 /* IDB_OBM0_THRESHOLD_PIPE3 */ "", 35260 /* IDB_OBM0_THRESHOLD_PIPE4 */ "", 35261 /* IDB_OBM0_THRESHOLD_PIPE5 */ "", 35262 /* IDB_OBM0_THRESHOLD_PIPE6 */ "", 35263 /* IDB_OBM0_THRESHOLD_PIPE7 */ "", 35264 /* IDB_OBM0_USAGE */ "", 35265 /* IDB_OBM0_USAGE_1 */ "", 35266 /* IDB_OBM0_USAGE_1_PIPE0 */ "", 35267 /* IDB_OBM0_USAGE_1_PIPE1 */ "", 35268 /* IDB_OBM0_USAGE_1_PIPE2 */ "", 35269 /* IDB_OBM0_USAGE_1_PIPE3 */ "", 35270 /* IDB_OBM0_USAGE_1_PIPE4 */ "", 35271 /* IDB_OBM0_USAGE_1_PIPE5 */ "", 35272 /* IDB_OBM0_USAGE_1_PIPE6 */ "", 35273 /* IDB_OBM0_USAGE_1_PIPE7 */ "", 35274 /* IDB_OBM0_USAGE_PIPE0 */ "", 35275 /* IDB_OBM0_USAGE_PIPE1 */ "", 35276 /* IDB_OBM0_USAGE_PIPE2 */ "", 35277 /* IDB_OBM0_USAGE_PIPE3 */ "", 35278 /* IDB_OBM0_USAGE_PIPE4 */ "", 35279 /* IDB_OBM0_USAGE_PIPE5 */ "", 35280 /* IDB_OBM0_USAGE_PIPE6 */ "", 35281 /* IDB_OBM0_USAGE_PIPE7 */ "", 35282 /* IDB_OBM10_BANK_CONFIG */ "IDB_OBM10_BANK_CONFIG", 35283 /* IDB_OBM10_BANK_CONFIG_PIPE0 */ "IDB_OBM10_BANK_CONFIG_PIPE0", 35284 /* IDB_OBM10_BANK_CONFIG_PIPE1 */ "IDB_OBM10_BANK_CONFIG_PIPE1", 35285 /* IDB_OBM10_BANK_CONFIG_PIPE2 */ "IDB_OBM10_BANK_CONFIG_PIPE2", 35286 /* IDB_OBM10_BANK_CONFIG_PIPE3 */ "IDB_OBM10_BANK_CONFIG_PIPE3", 35287 /* IDB_OBM10_BUFFER_CONFIG */ "", 35288 /* IDB_OBM10_BUFFER_CONFIG_PIPE0 */ "", 35289 /* IDB_OBM10_BUFFER_CONFIG_PIPE1 */ "", 35290 /* IDB_OBM10_CA_CONTROL */ "IDB_OBM10_CA_CONTROL", 35291 /* IDB_OBM10_CA_CONTROL_PIPE0 */ "IDB_OBM10_CA_CONTROL_PIPE0", 35292 /* IDB_OBM10_CA_CONTROL_PIPE1 */ "IDB_OBM10_CA_CONTROL_PIPE1", 35293 /* IDB_OBM10_CA_CONTROL_PIPE2 */ "IDB_OBM10_CA_CONTROL_PIPE2", 35294 /* IDB_OBM10_CA_CONTROL_PIPE3 */ "IDB_OBM10_CA_CONTROL_PIPE3", 35295 /* IDB_OBM10_CA_CT_CONTROL */ "IDB_OBM10_CA_CT_CONTROL", 35296 /* IDB_OBM10_CA_CT_CONTROL_PIPE0 */ "IDB_OBM10_CA_CT_CONTROL_PIPE0", 35297 /* IDB_OBM10_CA_CT_CONTROL_PIPE1 */ "IDB_OBM10_CA_CT_CONTROL_PIPE1", 35298 /* IDB_OBM10_CA_CT_CONTROL_PIPE2 */ "IDB_OBM10_CA_CT_CONTROL_PIPE2", 35299 /* IDB_OBM10_CA_CT_CONTROL_PIPE3 */ "IDB_OBM10_CA_CT_CONTROL_PIPE3", 35300 /* IDB_OBM10_CA_ECC_STATUS */ "IDB_OBM10_CA_ECC_STATUS", 35301 /* IDB_OBM10_CA_ECC_STATUS_PIPE0 */ "IDB_OBM10_CA_ECC_STATUS_PIPE0", 35302 /* IDB_OBM10_CA_ECC_STATUS_PIPE1 */ "IDB_OBM10_CA_ECC_STATUS_PIPE1", 35303 /* IDB_OBM10_CA_ECC_STATUS_PIPE2 */ "IDB_OBM10_CA_ECC_STATUS_PIPE2", 35304 /* IDB_OBM10_CA_ECC_STATUS_PIPE3 */ "IDB_OBM10_CA_ECC_STATUS_PIPE3", 35305 /* IDB_OBM10_CA_HW_STATUS */ "IDB_OBM10_CA_HW_STATUS", 35306 /* IDB_OBM10_CA_HW_STATUS_PIPE0 */ "IDB_OBM10_CA_HW_STATUS_PIPE0", 35307 /* IDB_OBM10_CA_HW_STATUS_PIPE1 */ "IDB_OBM10_CA_HW_STATUS_PIPE1", 35308 /* IDB_OBM10_CA_HW_STATUS_PIPE2 */ "IDB_OBM10_CA_HW_STATUS_PIPE2", 35309 /* IDB_OBM10_CA_HW_STATUS_PIPE3 */ "IDB_OBM10_CA_HW_STATUS_PIPE3", 35310 /* IDB_OBM10_CA_POINTER_STATUS */ "IDB_OBM10_CA_POINTER_STATUS", 35311 /* IDB_OBM10_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM10_CA_POINTER_STATUS_PIPE0", 35312 /* IDB_OBM10_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM10_CA_POINTER_STATUS_PIPE1", 35313 /* IDB_OBM10_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM10_CA_POINTER_STATUS_PIPE2", 35314 /* IDB_OBM10_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM10_CA_POINTER_STATUS_PIPE3", 35315 /* IDB_OBM10_CONTROL */ "IDB_OBM10_CONTROL", 35316 /* IDB_OBM10_CONTROL_PIPE0 */ "IDB_OBM10_CONTROL_PIPE0", 35317 /* IDB_OBM10_CONTROL_PIPE1 */ "IDB_OBM10_CONTROL_PIPE1", 35318 /* IDB_OBM10_CONTROL_PIPE2 */ "IDB_OBM10_CONTROL_PIPE2", 35319 /* IDB_OBM10_CONTROL_PIPE3 */ "IDB_OBM10_CONTROL_PIPE3", 35320 /* IDB_OBM10_CT_THRESHOLD */ "", 35321 /* IDB_OBM10_CT_THRESHOLD_PIPE0 */ "", 35322 /* IDB_OBM10_CT_THRESHOLD_PIPE1 */ "", 35323 /* IDB_OBM10_CT_THRESHOLD_PIPE2 */ "", 35324 /* IDB_OBM10_CT_THRESHOLD_PIPE3 */ "", 35325 /* IDB_OBM10_DATA_ECC_STATUS */ "IDB_OBM10_DATA_ECC_STATUS", 35326 /* IDB_OBM10_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM10_DATA_ECC_STATUS_PIPE0", 35327 /* IDB_OBM10_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM10_DATA_ECC_STATUS_PIPE1", 35328 /* IDB_OBM10_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM10_DATA_ECC_STATUS_PIPE2", 35329 /* IDB_OBM10_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM10_DATA_ECC_STATUS_PIPE3", 35330 /* IDB_OBM10_DBG_A */ "IDB_OBM10_FORCE_SAF_CONFIG", 35331 /* IDB_OBM10_DBG_A_PIPE0 */ "IDB_OBM10_FORCE_SAF_CONFIG_PIPE0", 35332 /* IDB_OBM10_DBG_A_PIPE1 */ "IDB_OBM10_FORCE_SAF_CONFIG_PIPE1", 35333 /* IDB_OBM10_DBG_A_PIPE2 */ "IDB_OBM10_FORCE_SAF_CONFIG_PIPE2", 35334 /* IDB_OBM10_DBG_A_PIPE3 */ "IDB_OBM10_FORCE_SAF_CONFIG_PIPE3", 35335 /* IDB_OBM10_FC_THRESHOLD */ "", 35336 /* IDB_OBM10_FC_THRESHOLD_1 */ "", 35337 /* IDB_OBM10_FC_THRESHOLD_1_PIPE0 */ "", 35338 /* IDB_OBM10_FC_THRESHOLD_1_PIPE1 */ "", 35339 /* IDB_OBM10_FC_THRESHOLD_1_PIPE2 */ "", 35340 /* IDB_OBM10_FC_THRESHOLD_1_PIPE3 */ "", 35341 /* IDB_OBM10_FC_THRESHOLD_PIPE0 */ "", 35342 /* IDB_OBM10_FC_THRESHOLD_PIPE1 */ "", 35343 /* IDB_OBM10_FC_THRESHOLD_PIPE2 */ "", 35344 /* IDB_OBM10_FC_THRESHOLD_PIPE3 */ "", 35345 /* IDB_OBM10_FLOW_CONTROL_CONFIG */ "", 35346 /* IDB_OBM10_FLOW_CONTROL_CONFIG_PIPE0 */ "", 35347 /* IDB_OBM10_FLOW_CONTROL_CONFIG_PIPE1 */ "", 35348 /* IDB_OBM10_FLOW_CONTROL_CONFIG_PIPE2 */ "", 35349 /* IDB_OBM10_FLOW_CONTROL_CONFIG_PIPE3 */ "", 35350 /* IDB_OBM10_FLOW_CONTROL_EVENT_COUNT */ "", 35351 /* IDB_OBM10_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 35352 /* IDB_OBM10_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 35353 /* IDB_OBM10_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 35354 /* IDB_OBM10_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 35355 /* IDB_OBM10_FORCE_SAF_STATUS */ "", 35356 /* IDB_OBM10_FORCE_SAF_STATUS_PIPE0 */ "", 35357 /* IDB_OBM10_FORCE_SAF_STATUS_PIPE1 */ "", 35358 /* IDB_OBM10_INNER_TPID */ "", 35359 /* IDB_OBM10_INNER_TPID_PIPE0 */ "", 35360 /* IDB_OBM10_INNER_TPID_PIPE1 */ "", 35361 /* IDB_OBM10_INNER_TPID_PIPE2 */ "", 35362 /* IDB_OBM10_INNER_TPID_PIPE3 */ "", 35363 /* IDB_OBM10_LOSSLESS0_BYTE_DROP_COUNT */ "", 35364 /* IDB_OBM10_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 35365 /* IDB_OBM10_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 35366 /* IDB_OBM10_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 35367 /* IDB_OBM10_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 35368 /* IDB_OBM10_LOSSLESS0_PKT_DROP_COUNT */ "", 35369 /* IDB_OBM10_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 35370 /* IDB_OBM10_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 35371 /* IDB_OBM10_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 35372 /* IDB_OBM10_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 35373 /* IDB_OBM10_LOSSLESS1_BYTE_DROP_COUNT */ "", 35374 /* IDB_OBM10_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 35375 /* IDB_OBM10_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 35376 /* IDB_OBM10_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 35377 /* IDB_OBM10_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 35378 /* IDB_OBM10_LOSSLESS1_PKT_DROP_COUNT */ "", 35379 /* IDB_OBM10_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 35380 /* IDB_OBM10_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 35381 /* IDB_OBM10_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 35382 /* IDB_OBM10_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 35383 /* IDB_OBM10_LOSSY_HI_BYTE_DROP_COUNT */ "", 35384 /* IDB_OBM10_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 35385 /* IDB_OBM10_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 35386 /* IDB_OBM10_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 35387 /* IDB_OBM10_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 35388 /* IDB_OBM10_LOSSY_HI_PKT_DROP_COUNT */ "", 35389 /* IDB_OBM10_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 35390 /* IDB_OBM10_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 35391 /* IDB_OBM10_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 35392 /* IDB_OBM10_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 35393 /* IDB_OBM10_LOSSY_LO_BYTE_DROP_COUNT */ "", 35394 /* IDB_OBM10_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 35395 /* IDB_OBM10_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 35396 /* IDB_OBM10_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 35397 /* IDB_OBM10_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 35398 /* IDB_OBM10_LOSSY_LO_PKT_DROP_COUNT */ "", 35399 /* IDB_OBM10_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 35400 /* IDB_OBM10_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 35401 /* IDB_OBM10_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 35402 /* IDB_OBM10_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 35403 /* IDB_OBM10_MAX_USAGE */ "IDB_OBM10_MAX_USAGE", 35404 /* IDB_OBM10_MAX_USAGE_1 */ "IDB_OBM10_MAX_USAGE_1", 35405 /* IDB_OBM10_MAX_USAGE_1_PIPE0 */ "IDB_OBM10_MAX_USAGE_1_PIPE0", 35406 /* IDB_OBM10_MAX_USAGE_1_PIPE1 */ "IDB_OBM10_MAX_USAGE_1_PIPE1", 35407 /* IDB_OBM10_MAX_USAGE_1_PIPE2 */ "IDB_OBM10_MAX_USAGE_1_PIPE2", 35408 /* IDB_OBM10_MAX_USAGE_1_PIPE3 */ "IDB_OBM10_MAX_USAGE_1_PIPE3", 35409 /* IDB_OBM10_MAX_USAGE_PIPE0 */ "IDB_OBM10_MAX_USAGE_PIPE0", 35410 /* IDB_OBM10_MAX_USAGE_PIPE1 */ "IDB_OBM10_MAX_USAGE_PIPE1", 35411 /* IDB_OBM10_MAX_USAGE_PIPE2 */ "IDB_OBM10_MAX_USAGE_PIPE2", 35412 /* IDB_OBM10_MAX_USAGE_PIPE3 */ "IDB_OBM10_MAX_USAGE_PIPE3", 35413 /* IDB_OBM10_MAX_USAGE_SELECT */ "", 35414 /* IDB_OBM10_MAX_USAGE_SELECT_PIPE0 */ "", 35415 /* IDB_OBM10_MAX_USAGE_SELECT_PIPE1 */ "", 35416 /* IDB_OBM10_MAX_USAGE_SELECT_PIPE2 */ "", 35417 /* IDB_OBM10_MAX_USAGE_SELECT_PIPE3 */ "", 35418 /* IDB_OBM10_NIV_ETHERTYPE */ "", 35419 /* IDB_OBM10_NIV_ETHERTYPE_PIPE0 */ "", 35420 /* IDB_OBM10_NIV_ETHERTYPE_PIPE1 */ "", 35421 /* IDB_OBM10_NIV_ETHERTYPE_PIPE2 */ "", 35422 /* IDB_OBM10_NIV_ETHERTYPE_PIPE3 */ "", 35423 /* IDB_OBM10_OUTER_TPID */ "", 35424 /* IDB_OBM10_OUTER_TPID_0 */ "", 35425 /* IDB_OBM10_OUTER_TPID_1 */ "", 35426 /* IDB_OBM10_OUTER_TPID_2 */ "", 35427 /* IDB_OBM10_OUTER_TPID_3 */ "", 35428 /* IDB_OBM10_OUTER_TPID_0_PIPE0 */ "", 35429 /* IDB_OBM10_OUTER_TPID_0_PIPE1 */ "", 35430 /* IDB_OBM10_OUTER_TPID_0_PIPE2 */ "", 35431 /* IDB_OBM10_OUTER_TPID_0_PIPE3 */ "", 35432 /* IDB_OBM10_OUTER_TPID_1_PIPE0 */ "", 35433 /* IDB_OBM10_OUTER_TPID_1_PIPE1 */ "", 35434 /* IDB_OBM10_OUTER_TPID_1_PIPE2 */ "", 35435 /* IDB_OBM10_OUTER_TPID_1_PIPE3 */ "", 35436 /* IDB_OBM10_OUTER_TPID_2_PIPE0 */ "", 35437 /* IDB_OBM10_OUTER_TPID_2_PIPE1 */ "", 35438 /* IDB_OBM10_OUTER_TPID_2_PIPE2 */ "", 35439 /* IDB_OBM10_OUTER_TPID_2_PIPE3 */ "", 35440 /* IDB_OBM10_OUTER_TPID_3_PIPE0 */ "", 35441 /* IDB_OBM10_OUTER_TPID_3_PIPE1 */ "", 35442 /* IDB_OBM10_OUTER_TPID_3_PIPE2 */ "", 35443 /* IDB_OBM10_OUTER_TPID_3_PIPE3 */ "", 35444 /* IDB_OBM10_OUTER_TPID_PIPE0 */ "", 35445 /* IDB_OBM10_OUTER_TPID_PIPE1 */ "", 35446 /* IDB_OBM10_OUTER_TPID_PIPE2 */ "", 35447 /* IDB_OBM10_OUTER_TPID_PIPE3 */ "", 35448 /* IDB_OBM10_OVERSUB_MON_ECC_STATUS */ "IDB_OBM10_OVERSUB_MON_ECC_STATUS", 35449 /* IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE0", 35450 /* IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE1", 35451 /* IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE2", 35452 /* IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM10_OVERSUB_MON_ECC_STATUS_PIPE3", 35453 /* IDB_OBM10_PE_ETHERTYPE */ "", 35454 /* IDB_OBM10_PE_ETHERTYPE_PIPE0 */ "", 35455 /* IDB_OBM10_PE_ETHERTYPE_PIPE1 */ "", 35456 /* IDB_OBM10_PE_ETHERTYPE_PIPE2 */ "", 35457 /* IDB_OBM10_PE_ETHERTYPE_PIPE3 */ "", 35458 /* IDB_OBM10_PORT_CONFIG */ "", 35459 /* IDB_OBM10_PORT_CONFIG_PIPE0 */ "", 35460 /* IDB_OBM10_PORT_CONFIG_PIPE1 */ "", 35461 /* IDB_OBM10_PORT_CONFIG_PIPE2 */ "", 35462 /* IDB_OBM10_PORT_CONFIG_PIPE3 */ "", 35463 /* IDB_OBM10_PROTOCOL_CONTROL_0 */ "", 35464 /* IDB_OBM10_PROTOCOL_CONTROL_1 */ "", 35465 /* IDB_OBM10_PROTOCOL_CONTROL_2 */ "", 35466 /* IDB_OBM10_PROTOCOL_CONTROL_0_PIPE0 */ "", 35467 /* IDB_OBM10_PROTOCOL_CONTROL_0_PIPE1 */ "", 35468 /* IDB_OBM10_PROTOCOL_CONTROL_0_PIPE2 */ "", 35469 /* IDB_OBM10_PROTOCOL_CONTROL_0_PIPE3 */ "", 35470 /* IDB_OBM10_PROTOCOL_CONTROL_1_PIPE0 */ "", 35471 /* IDB_OBM10_PROTOCOL_CONTROL_1_PIPE1 */ "", 35472 /* IDB_OBM10_PROTOCOL_CONTROL_1_PIPE2 */ "", 35473 /* IDB_OBM10_PROTOCOL_CONTROL_1_PIPE3 */ "", 35474 /* IDB_OBM10_PROTOCOL_CONTROL_2_PIPE0 */ "", 35475 /* IDB_OBM10_PROTOCOL_CONTROL_2_PIPE1 */ "", 35476 /* IDB_OBM10_PROTOCOL_CONTROL_2_PIPE2 */ "", 35477 /* IDB_OBM10_PROTOCOL_CONTROL_2_PIPE3 */ "", 35478 /* IDB_OBM10_QUEUE_ECC_STATUS */ "IDB_OBM10_QUEUE_ECC_STATUS", 35479 /* IDB_OBM10_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM10_QUEUE_ECC_STATUS_PIPE0", 35480 /* IDB_OBM10_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM10_QUEUE_ECC_STATUS_PIPE1", 35481 /* IDB_OBM10_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM10_QUEUE_ECC_STATUS_PIPE2", 35482 /* IDB_OBM10_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM10_QUEUE_ECC_STATUS_PIPE3", 35483 /* IDB_OBM10_RAM_CONTROL */ "IDB_OBM10_RAM_CONTROL", 35484 /* IDB_OBM10_RAM_CONTROL_PIPE0 */ "IDB_OBM10_RAM_CONTROL_PIPE0", 35485 /* IDB_OBM10_RAM_CONTROL_PIPE1 */ "IDB_OBM10_RAM_CONTROL_PIPE1", 35486 /* IDB_OBM10_RAM_CONTROL_PIPE2 */ "IDB_OBM10_RAM_CONTROL_PIPE2", 35487 /* IDB_OBM10_RAM_CONTROL_PIPE3 */ "IDB_OBM10_RAM_CONTROL_PIPE3", 35488 /* IDB_OBM10_SER_CONTROL */ "IDB_OBM10_SER_CONTROL", 35489 /* IDB_OBM10_SER_CONTROL_PIPE0 */ "IDB_OBM10_SER_CONTROL_PIPE0", 35490 /* IDB_OBM10_SER_CONTROL_PIPE1 */ "IDB_OBM10_SER_CONTROL_PIPE1", 35491 /* IDB_OBM10_SHARED_CONFIG */ "IDB_OBM10_SHARED_CONFIG", 35492 /* IDB_OBM10_SHARED_CONFIG_PIPE0 */ "IDB_OBM10_SHARED_CONFIG_PIPE0", 35493 /* IDB_OBM10_SHARED_CONFIG_PIPE1 */ "IDB_OBM10_SHARED_CONFIG_PIPE1", 35494 /* IDB_OBM10_SHARED_CONFIG_PIPE2 */ "IDB_OBM10_SHARED_CONFIG_PIPE2", 35495 /* IDB_OBM10_SHARED_CONFIG_PIPE3 */ "IDB_OBM10_SHARED_CONFIG_PIPE3", 35496 /* IDB_OBM10_SHARED_USAGE */ "IDB_OBM10_SHARED_USAGE", 35497 /* IDB_OBM10_SHARED_USAGE_PIPE0 */ "IDB_OBM10_SHARED_USAGE_PIPE0", 35498 /* IDB_OBM10_SHARED_USAGE_PIPE1 */ "IDB_OBM10_SHARED_USAGE_PIPE1", 35499 /* IDB_OBM10_SHARED_USAGE_PIPE2 */ "IDB_OBM10_SHARED_USAGE_PIPE2", 35500 /* IDB_OBM10_SHARED_USAGE_PIPE3 */ "IDB_OBM10_SHARED_USAGE_PIPE3", 35501 /* IDB_OBM10_THRESHOLD */ "", 35502 /* IDB_OBM10_THRESHOLD_1 */ "", 35503 /* IDB_OBM10_THRESHOLD_1_PIPE0 */ "", 35504 /* IDB_OBM10_THRESHOLD_1_PIPE1 */ "", 35505 /* IDB_OBM10_THRESHOLD_1_PIPE2 */ "", 35506 /* IDB_OBM10_THRESHOLD_1_PIPE3 */ "", 35507 /* IDB_OBM10_THRESHOLD_PIPE0 */ "", 35508 /* IDB_OBM10_THRESHOLD_PIPE1 */ "", 35509 /* IDB_OBM10_THRESHOLD_PIPE2 */ "", 35510 /* IDB_OBM10_THRESHOLD_PIPE3 */ "", 35511 /* IDB_OBM10_USAGE */ "", 35512 /* IDB_OBM10_USAGE_PIPE0 */ "", 35513 /* IDB_OBM10_USAGE_PIPE1 */ "", 35514 /* IDB_OBM10_USAGE_PIPE2 */ "", 35515 /* IDB_OBM10_USAGE_PIPE3 */ "", 35516 /* IDB_OBM11_BANK_CONFIG */ "IDB_OBM11_BANK_CONFIG", 35517 /* IDB_OBM11_BANK_CONFIG_PIPE0 */ "IDB_OBM11_BANK_CONFIG_PIPE0", 35518 /* IDB_OBM11_BANK_CONFIG_PIPE1 */ "IDB_OBM11_BANK_CONFIG_PIPE1", 35519 /* IDB_OBM11_BANK_CONFIG_PIPE2 */ "IDB_OBM11_BANK_CONFIG_PIPE2", 35520 /* IDB_OBM11_BANK_CONFIG_PIPE3 */ "IDB_OBM11_BANK_CONFIG_PIPE3", 35521 /* IDB_OBM11_BUFFER_CONFIG */ "", 35522 /* IDB_OBM11_BUFFER_CONFIG_PIPE0 */ "", 35523 /* IDB_OBM11_BUFFER_CONFIG_PIPE1 */ "", 35524 /* IDB_OBM11_CA_CONTROL */ "IDB_OBM11_CA_CONTROL", 35525 /* IDB_OBM11_CA_CONTROL_PIPE0 */ "IDB_OBM11_CA_CONTROL_PIPE0", 35526 /* IDB_OBM11_CA_CONTROL_PIPE1 */ "IDB_OBM11_CA_CONTROL_PIPE1", 35527 /* IDB_OBM11_CA_CONTROL_PIPE2 */ "IDB_OBM11_CA_CONTROL_PIPE2", 35528 /* IDB_OBM11_CA_CONTROL_PIPE3 */ "IDB_OBM11_CA_CONTROL_PIPE3", 35529 /* IDB_OBM11_CA_CT_CONTROL */ "IDB_OBM11_CA_CT_CONTROL", 35530 /* IDB_OBM11_CA_CT_CONTROL_PIPE0 */ "IDB_OBM11_CA_CT_CONTROL_PIPE0", 35531 /* IDB_OBM11_CA_CT_CONTROL_PIPE1 */ "IDB_OBM11_CA_CT_CONTROL_PIPE1", 35532 /* IDB_OBM11_CA_CT_CONTROL_PIPE2 */ "IDB_OBM11_CA_CT_CONTROL_PIPE2", 35533 /* IDB_OBM11_CA_CT_CONTROL_PIPE3 */ "IDB_OBM11_CA_CT_CONTROL_PIPE3", 35534 /* IDB_OBM11_CA_ECC_STATUS */ "IDB_OBM11_CA_ECC_STATUS", 35535 /* IDB_OBM11_CA_ECC_STATUS_PIPE0 */ "IDB_OBM11_CA_ECC_STATUS_PIPE0", 35536 /* IDB_OBM11_CA_ECC_STATUS_PIPE1 */ "IDB_OBM11_CA_ECC_STATUS_PIPE1", 35537 /* IDB_OBM11_CA_ECC_STATUS_PIPE2 */ "IDB_OBM11_CA_ECC_STATUS_PIPE2", 35538 /* IDB_OBM11_CA_ECC_STATUS_PIPE3 */ "IDB_OBM11_CA_ECC_STATUS_PIPE3", 35539 /* IDB_OBM11_CA_HW_STATUS */ "IDB_OBM11_CA_HW_STATUS", 35540 /* IDB_OBM11_CA_HW_STATUS_PIPE0 */ "IDB_OBM11_CA_HW_STATUS_PIPE0", 35541 /* IDB_OBM11_CA_HW_STATUS_PIPE1 */ "IDB_OBM11_CA_HW_STATUS_PIPE1", 35542 /* IDB_OBM11_CA_HW_STATUS_PIPE2 */ "IDB_OBM11_CA_HW_STATUS_PIPE2", 35543 /* IDB_OBM11_CA_HW_STATUS_PIPE3 */ "IDB_OBM11_CA_HW_STATUS_PIPE3", 35544 /* IDB_OBM11_CA_POINTER_STATUS */ "IDB_OBM11_CA_POINTER_STATUS", 35545 /* IDB_OBM11_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM11_CA_POINTER_STATUS_PIPE0", 35546 /* IDB_OBM11_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM11_CA_POINTER_STATUS_PIPE1", 35547 /* IDB_OBM11_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM11_CA_POINTER_STATUS_PIPE2", 35548 /* IDB_OBM11_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM11_CA_POINTER_STATUS_PIPE3", 35549 /* IDB_OBM11_CONTROL */ "IDB_OBM11_CONTROL", 35550 /* IDB_OBM11_CONTROL_PIPE0 */ "IDB_OBM11_CONTROL_PIPE0", 35551 /* IDB_OBM11_CONTROL_PIPE1 */ "IDB_OBM11_CONTROL_PIPE1", 35552 /* IDB_OBM11_CONTROL_PIPE2 */ "IDB_OBM11_CONTROL_PIPE2", 35553 /* IDB_OBM11_CONTROL_PIPE3 */ "IDB_OBM11_CONTROL_PIPE3", 35554 /* IDB_OBM11_CT_THRESHOLD */ "", 35555 /* IDB_OBM11_CT_THRESHOLD_PIPE0 */ "", 35556 /* IDB_OBM11_CT_THRESHOLD_PIPE1 */ "", 35557 /* IDB_OBM11_CT_THRESHOLD_PIPE2 */ "", 35558 /* IDB_OBM11_CT_THRESHOLD_PIPE3 */ "", 35559 /* IDB_OBM11_DATA_ECC_STATUS */ "IDB_OBM11_DATA_ECC_STATUS", 35560 /* IDB_OBM11_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM11_DATA_ECC_STATUS_PIPE0", 35561 /* IDB_OBM11_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM11_DATA_ECC_STATUS_PIPE1", 35562 /* IDB_OBM11_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM11_DATA_ECC_STATUS_PIPE2", 35563 /* IDB_OBM11_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM11_DATA_ECC_STATUS_PIPE3", 35564 /* IDB_OBM11_DBG_A */ "IDB_OBM11_FORCE_SAF_CONFIG", 35565 /* IDB_OBM11_DBG_A_PIPE0 */ "IDB_OBM11_FORCE_SAF_CONFIG_PIPE0", 35566 /* IDB_OBM11_DBG_A_PIPE1 */ "IDB_OBM11_FORCE_SAF_CONFIG_PIPE1", 35567 /* IDB_OBM11_DBG_A_PIPE2 */ "IDB_OBM11_FORCE_SAF_CONFIG_PIPE2", 35568 /* IDB_OBM11_DBG_A_PIPE3 */ "IDB_OBM11_FORCE_SAF_CONFIG_PIPE3", 35569 /* IDB_OBM11_FC_THRESHOLD */ "", 35570 /* IDB_OBM11_FC_THRESHOLD_1 */ "", 35571 /* IDB_OBM11_FC_THRESHOLD_1_PIPE0 */ "", 35572 /* IDB_OBM11_FC_THRESHOLD_1_PIPE1 */ "", 35573 /* IDB_OBM11_FC_THRESHOLD_1_PIPE2 */ "", 35574 /* IDB_OBM11_FC_THRESHOLD_1_PIPE3 */ "", 35575 /* IDB_OBM11_FC_THRESHOLD_PIPE0 */ "", 35576 /* IDB_OBM11_FC_THRESHOLD_PIPE1 */ "", 35577 /* IDB_OBM11_FC_THRESHOLD_PIPE2 */ "", 35578 /* IDB_OBM11_FC_THRESHOLD_PIPE3 */ "", 35579 /* IDB_OBM11_FLOW_CONTROL_CONFIG */ "", 35580 /* IDB_OBM11_FLOW_CONTROL_CONFIG_PIPE0 */ "", 35581 /* IDB_OBM11_FLOW_CONTROL_CONFIG_PIPE1 */ "", 35582 /* IDB_OBM11_FLOW_CONTROL_CONFIG_PIPE2 */ "", 35583 /* IDB_OBM11_FLOW_CONTROL_CONFIG_PIPE3 */ "", 35584 /* IDB_OBM11_FLOW_CONTROL_EVENT_COUNT */ "", 35585 /* IDB_OBM11_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 35586 /* IDB_OBM11_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 35587 /* IDB_OBM11_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 35588 /* IDB_OBM11_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 35589 /* IDB_OBM11_FORCE_SAF_STATUS */ "", 35590 /* IDB_OBM11_FORCE_SAF_STATUS_PIPE0 */ "", 35591 /* IDB_OBM11_FORCE_SAF_STATUS_PIPE1 */ "", 35592 /* IDB_OBM11_INNER_TPID */ "", 35593 /* IDB_OBM11_INNER_TPID_PIPE0 */ "", 35594 /* IDB_OBM11_INNER_TPID_PIPE1 */ "", 35595 /* IDB_OBM11_INNER_TPID_PIPE2 */ "", 35596 /* IDB_OBM11_INNER_TPID_PIPE3 */ "", 35597 /* IDB_OBM11_LOSSLESS0_BYTE_DROP_COUNT */ "", 35598 /* IDB_OBM11_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 35599 /* IDB_OBM11_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 35600 /* IDB_OBM11_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 35601 /* IDB_OBM11_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 35602 /* IDB_OBM11_LOSSLESS0_PKT_DROP_COUNT */ "", 35603 /* IDB_OBM11_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 35604 /* IDB_OBM11_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 35605 /* IDB_OBM11_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 35606 /* IDB_OBM11_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 35607 /* IDB_OBM11_LOSSLESS1_BYTE_DROP_COUNT */ "", 35608 /* IDB_OBM11_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 35609 /* IDB_OBM11_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 35610 /* IDB_OBM11_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 35611 /* IDB_OBM11_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 35612 /* IDB_OBM11_LOSSLESS1_PKT_DROP_COUNT */ "", 35613 /* IDB_OBM11_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 35614 /* IDB_OBM11_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 35615 /* IDB_OBM11_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 35616 /* IDB_OBM11_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 35617 /* IDB_OBM11_LOSSY_HI_BYTE_DROP_COUNT */ "", 35618 /* IDB_OBM11_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 35619 /* IDB_OBM11_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 35620 /* IDB_OBM11_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 35621 /* IDB_OBM11_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 35622 /* IDB_OBM11_LOSSY_HI_PKT_DROP_COUNT */ "", 35623 /* IDB_OBM11_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 35624 /* IDB_OBM11_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 35625 /* IDB_OBM11_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 35626 /* IDB_OBM11_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 35627 /* IDB_OBM11_LOSSY_LO_BYTE_DROP_COUNT */ "", 35628 /* IDB_OBM11_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 35629 /* IDB_OBM11_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 35630 /* IDB_OBM11_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 35631 /* IDB_OBM11_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 35632 /* IDB_OBM11_LOSSY_LO_PKT_DROP_COUNT */ "", 35633 /* IDB_OBM11_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 35634 /* IDB_OBM11_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 35635 /* IDB_OBM11_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 35636 /* IDB_OBM11_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 35637 /* IDB_OBM11_MAX_USAGE */ "IDB_OBM11_MAX_USAGE", 35638 /* IDB_OBM11_MAX_USAGE_1 */ "IDB_OBM11_MAX_USAGE_1", 35639 /* IDB_OBM11_MAX_USAGE_1_PIPE0 */ "IDB_OBM11_MAX_USAGE_1_PIPE0", 35640 /* IDB_OBM11_MAX_USAGE_1_PIPE1 */ "IDB_OBM11_MAX_USAGE_1_PIPE1", 35641 /* IDB_OBM11_MAX_USAGE_1_PIPE2 */ "IDB_OBM11_MAX_USAGE_1_PIPE2", 35642 /* IDB_OBM11_MAX_USAGE_1_PIPE3 */ "IDB_OBM11_MAX_USAGE_1_PIPE3", 35643 /* IDB_OBM11_MAX_USAGE_PIPE0 */ "IDB_OBM11_MAX_USAGE_PIPE0", 35644 /* IDB_OBM11_MAX_USAGE_PIPE1 */ "IDB_OBM11_MAX_USAGE_PIPE1", 35645 /* IDB_OBM11_MAX_USAGE_PIPE2 */ "IDB_OBM11_MAX_USAGE_PIPE2", 35646 /* IDB_OBM11_MAX_USAGE_PIPE3 */ "IDB_OBM11_MAX_USAGE_PIPE3", 35647 /* IDB_OBM11_MAX_USAGE_SELECT */ "", 35648 /* IDB_OBM11_MAX_USAGE_SELECT_PIPE0 */ "", 35649 /* IDB_OBM11_MAX_USAGE_SELECT_PIPE1 */ "", 35650 /* IDB_OBM11_MAX_USAGE_SELECT_PIPE2 */ "", 35651 /* IDB_OBM11_MAX_USAGE_SELECT_PIPE3 */ "", 35652 /* IDB_OBM11_NIV_ETHERTYPE */ "", 35653 /* IDB_OBM11_NIV_ETHERTYPE_PIPE0 */ "", 35654 /* IDB_OBM11_NIV_ETHERTYPE_PIPE1 */ "", 35655 /* IDB_OBM11_NIV_ETHERTYPE_PIPE2 */ "", 35656 /* IDB_OBM11_NIV_ETHERTYPE_PIPE3 */ "", 35657 /* IDB_OBM11_OUTER_TPID */ "", 35658 /* IDB_OBM11_OUTER_TPID_0 */ "", 35659 /* IDB_OBM11_OUTER_TPID_1 */ "", 35660 /* IDB_OBM11_OUTER_TPID_2 */ "", 35661 /* IDB_OBM11_OUTER_TPID_3 */ "", 35662 /* IDB_OBM11_OUTER_TPID_0_PIPE0 */ "", 35663 /* IDB_OBM11_OUTER_TPID_0_PIPE1 */ "", 35664 /* IDB_OBM11_OUTER_TPID_0_PIPE2 */ "", 35665 /* IDB_OBM11_OUTER_TPID_0_PIPE3 */ "", 35666 /* IDB_OBM11_OUTER_TPID_1_PIPE0 */ "", 35667 /* IDB_OBM11_OUTER_TPID_1_PIPE1 */ "", 35668 /* IDB_OBM11_OUTER_TPID_1_PIPE2 */ "", 35669 /* IDB_OBM11_OUTER_TPID_1_PIPE3 */ "", 35670 /* IDB_OBM11_OUTER_TPID_2_PIPE0 */ "", 35671 /* IDB_OBM11_OUTER_TPID_2_PIPE1 */ "", 35672 /* IDB_OBM11_OUTER_TPID_2_PIPE2 */ "", 35673 /* IDB_OBM11_OUTER_TPID_2_PIPE3 */ "", 35674 /* IDB_OBM11_OUTER_TPID_3_PIPE0 */ "", 35675 /* IDB_OBM11_OUTER_TPID_3_PIPE1 */ "", 35676 /* IDB_OBM11_OUTER_TPID_3_PIPE2 */ "", 35677 /* IDB_OBM11_OUTER_TPID_3_PIPE3 */ "", 35678 /* IDB_OBM11_OUTER_TPID_PIPE0 */ "", 35679 /* IDB_OBM11_OUTER_TPID_PIPE1 */ "", 35680 /* IDB_OBM11_OUTER_TPID_PIPE2 */ "", 35681 /* IDB_OBM11_OUTER_TPID_PIPE3 */ "", 35682 /* IDB_OBM11_OVERSUB_MON_ECC_STATUS */ "IDB_OBM11_OVERSUB_MON_ECC_STATUS", 35683 /* IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE0", 35684 /* IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE1", 35685 /* IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE2", 35686 /* IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM11_OVERSUB_MON_ECC_STATUS_PIPE3", 35687 /* IDB_OBM11_PE_ETHERTYPE */ "", 35688 /* IDB_OBM11_PE_ETHERTYPE_PIPE0 */ "", 35689 /* IDB_OBM11_PE_ETHERTYPE_PIPE1 */ "", 35690 /* IDB_OBM11_PE_ETHERTYPE_PIPE2 */ "", 35691 /* IDB_OBM11_PE_ETHERTYPE_PIPE3 */ "", 35692 /* IDB_OBM11_PORT_CONFIG */ "", 35693 /* IDB_OBM11_PORT_CONFIG_PIPE0 */ "", 35694 /* IDB_OBM11_PORT_CONFIG_PIPE1 */ "", 35695 /* IDB_OBM11_PORT_CONFIG_PIPE2 */ "", 35696 /* IDB_OBM11_PORT_CONFIG_PIPE3 */ "", 35697 /* IDB_OBM11_PROTOCOL_CONTROL_0 */ "", 35698 /* IDB_OBM11_PROTOCOL_CONTROL_1 */ "", 35699 /* IDB_OBM11_PROTOCOL_CONTROL_2 */ "", 35700 /* IDB_OBM11_PROTOCOL_CONTROL_0_PIPE0 */ "", 35701 /* IDB_OBM11_PROTOCOL_CONTROL_0_PIPE1 */ "", 35702 /* IDB_OBM11_PROTOCOL_CONTROL_0_PIPE2 */ "", 35703 /* IDB_OBM11_PROTOCOL_CONTROL_0_PIPE3 */ "", 35704 /* IDB_OBM11_PROTOCOL_CONTROL_1_PIPE0 */ "", 35705 /* IDB_OBM11_PROTOCOL_CONTROL_1_PIPE1 */ "", 35706 /* IDB_OBM11_PROTOCOL_CONTROL_1_PIPE2 */ "", 35707 /* IDB_OBM11_PROTOCOL_CONTROL_1_PIPE3 */ "", 35708 /* IDB_OBM11_PROTOCOL_CONTROL_2_PIPE0 */ "", 35709 /* IDB_OBM11_PROTOCOL_CONTROL_2_PIPE1 */ "", 35710 /* IDB_OBM11_PROTOCOL_CONTROL_2_PIPE2 */ "", 35711 /* IDB_OBM11_PROTOCOL_CONTROL_2_PIPE3 */ "", 35712 /* IDB_OBM11_QUEUE_ECC_STATUS */ "IDB_OBM11_QUEUE_ECC_STATUS", 35713 /* IDB_OBM11_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM11_QUEUE_ECC_STATUS_PIPE0", 35714 /* IDB_OBM11_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM11_QUEUE_ECC_STATUS_PIPE1", 35715 /* IDB_OBM11_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM11_QUEUE_ECC_STATUS_PIPE2", 35716 /* IDB_OBM11_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM11_QUEUE_ECC_STATUS_PIPE3", 35717 /* IDB_OBM11_RAM_CONTROL */ "IDB_OBM11_RAM_CONTROL", 35718 /* IDB_OBM11_RAM_CONTROL_PIPE0 */ "IDB_OBM11_RAM_CONTROL_PIPE0", 35719 /* IDB_OBM11_RAM_CONTROL_PIPE1 */ "IDB_OBM11_RAM_CONTROL_PIPE1", 35720 /* IDB_OBM11_RAM_CONTROL_PIPE2 */ "IDB_OBM11_RAM_CONTROL_PIPE2", 35721 /* IDB_OBM11_RAM_CONTROL_PIPE3 */ "IDB_OBM11_RAM_CONTROL_PIPE3", 35722 /* IDB_OBM11_SER_CONTROL */ "IDB_OBM11_SER_CONTROL", 35723 /* IDB_OBM11_SER_CONTROL_PIPE0 */ "IDB_OBM11_SER_CONTROL_PIPE0", 35724 /* IDB_OBM11_SER_CONTROL_PIPE1 */ "IDB_OBM11_SER_CONTROL_PIPE1", 35725 /* IDB_OBM11_SHARED_CONFIG */ "IDB_OBM11_SHARED_CONFIG", 35726 /* IDB_OBM11_SHARED_CONFIG_PIPE0 */ "IDB_OBM11_SHARED_CONFIG_PIPE0", 35727 /* IDB_OBM11_SHARED_CONFIG_PIPE1 */ "IDB_OBM11_SHARED_CONFIG_PIPE1", 35728 /* IDB_OBM11_SHARED_CONFIG_PIPE2 */ "IDB_OBM11_SHARED_CONFIG_PIPE2", 35729 /* IDB_OBM11_SHARED_CONFIG_PIPE3 */ "IDB_OBM11_SHARED_CONFIG_PIPE3", 35730 /* IDB_OBM11_SHARED_USAGE */ "IDB_OBM11_SHARED_USAGE", 35731 /* IDB_OBM11_SHARED_USAGE_PIPE0 */ "IDB_OBM11_SHARED_USAGE_PIPE0", 35732 /* IDB_OBM11_SHARED_USAGE_PIPE1 */ "IDB_OBM11_SHARED_USAGE_PIPE1", 35733 /* IDB_OBM11_SHARED_USAGE_PIPE2 */ "IDB_OBM11_SHARED_USAGE_PIPE2", 35734 /* IDB_OBM11_SHARED_USAGE_PIPE3 */ "IDB_OBM11_SHARED_USAGE_PIPE3", 35735 /* IDB_OBM11_THRESHOLD */ "", 35736 /* IDB_OBM11_THRESHOLD_1 */ "", 35737 /* IDB_OBM11_THRESHOLD_1_PIPE0 */ "", 35738 /* IDB_OBM11_THRESHOLD_1_PIPE1 */ "", 35739 /* IDB_OBM11_THRESHOLD_1_PIPE2 */ "", 35740 /* IDB_OBM11_THRESHOLD_1_PIPE3 */ "", 35741 /* IDB_OBM11_THRESHOLD_PIPE0 */ "", 35742 /* IDB_OBM11_THRESHOLD_PIPE1 */ "", 35743 /* IDB_OBM11_THRESHOLD_PIPE2 */ "", 35744 /* IDB_OBM11_THRESHOLD_PIPE3 */ "", 35745 /* IDB_OBM11_USAGE */ "", 35746 /* IDB_OBM11_USAGE_PIPE0 */ "", 35747 /* IDB_OBM11_USAGE_PIPE1 */ "", 35748 /* IDB_OBM11_USAGE_PIPE2 */ "", 35749 /* IDB_OBM11_USAGE_PIPE3 */ "", 35750 /* IDB_OBM12_BANK_CONFIG */ "IDB_OBM12_BANK_CONFIG", 35751 /* IDB_OBM12_BANK_CONFIG_PIPE0 */ "IDB_OBM12_BANK_CONFIG_PIPE0", 35752 /* IDB_OBM12_BANK_CONFIG_PIPE1 */ "IDB_OBM12_BANK_CONFIG_PIPE1", 35753 /* IDB_OBM12_BANK_CONFIG_PIPE2 */ "IDB_OBM12_BANK_CONFIG_PIPE2", 35754 /* IDB_OBM12_BANK_CONFIG_PIPE3 */ "IDB_OBM12_BANK_CONFIG_PIPE3", 35755 /* IDB_OBM12_BUFFER_CONFIG */ "", 35756 /* IDB_OBM12_BUFFER_CONFIG_PIPE0 */ "", 35757 /* IDB_OBM12_BUFFER_CONFIG_PIPE1 */ "", 35758 /* IDB_OBM12_CA_CONTROL */ "IDB_OBM12_CA_CONTROL", 35759 /* IDB_OBM12_CA_CONTROL_PIPE0 */ "IDB_OBM12_CA_CONTROL_PIPE0", 35760 /* IDB_OBM12_CA_CONTROL_PIPE1 */ "IDB_OBM12_CA_CONTROL_PIPE1", 35761 /* IDB_OBM12_CA_CONTROL_PIPE2 */ "IDB_OBM12_CA_CONTROL_PIPE2", 35762 /* IDB_OBM12_CA_CONTROL_PIPE3 */ "IDB_OBM12_CA_CONTROL_PIPE3", 35763 /* IDB_OBM12_CA_CT_CONTROL */ "IDB_OBM12_CA_CT_CONTROL", 35764 /* IDB_OBM12_CA_CT_CONTROL_PIPE0 */ "IDB_OBM12_CA_CT_CONTROL_PIPE0", 35765 /* IDB_OBM12_CA_CT_CONTROL_PIPE1 */ "IDB_OBM12_CA_CT_CONTROL_PIPE1", 35766 /* IDB_OBM12_CA_CT_CONTROL_PIPE2 */ "IDB_OBM12_CA_CT_CONTROL_PIPE2", 35767 /* IDB_OBM12_CA_CT_CONTROL_PIPE3 */ "IDB_OBM12_CA_CT_CONTROL_PIPE3", 35768 /* IDB_OBM12_CA_ECC_STATUS */ "IDB_OBM12_CA_ECC_STATUS", 35769 /* IDB_OBM12_CA_ECC_STATUS_PIPE0 */ "IDB_OBM12_CA_ECC_STATUS_PIPE0", 35770 /* IDB_OBM12_CA_ECC_STATUS_PIPE1 */ "IDB_OBM12_CA_ECC_STATUS_PIPE1", 35771 /* IDB_OBM12_CA_ECC_STATUS_PIPE2 */ "IDB_OBM12_CA_ECC_STATUS_PIPE2", 35772 /* IDB_OBM12_CA_ECC_STATUS_PIPE3 */ "IDB_OBM12_CA_ECC_STATUS_PIPE3", 35773 /* IDB_OBM12_CA_HW_STATUS */ "IDB_OBM12_CA_HW_STATUS", 35774 /* IDB_OBM12_CA_HW_STATUS_PIPE0 */ "IDB_OBM12_CA_HW_STATUS_PIPE0", 35775 /* IDB_OBM12_CA_HW_STATUS_PIPE1 */ "IDB_OBM12_CA_HW_STATUS_PIPE1", 35776 /* IDB_OBM12_CA_HW_STATUS_PIPE2 */ "IDB_OBM12_CA_HW_STATUS_PIPE2", 35777 /* IDB_OBM12_CA_HW_STATUS_PIPE3 */ "IDB_OBM12_CA_HW_STATUS_PIPE3", 35778 /* IDB_OBM12_CA_POINTER_STATUS */ "IDB_OBM12_CA_POINTER_STATUS", 35779 /* IDB_OBM12_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM12_CA_POINTER_STATUS_PIPE0", 35780 /* IDB_OBM12_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM12_CA_POINTER_STATUS_PIPE1", 35781 /* IDB_OBM12_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM12_CA_POINTER_STATUS_PIPE2", 35782 /* IDB_OBM12_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM12_CA_POINTER_STATUS_PIPE3", 35783 /* IDB_OBM12_CONTROL */ "IDB_OBM12_CONTROL", 35784 /* IDB_OBM12_CONTROL_PIPE0 */ "IDB_OBM12_CONTROL_PIPE0", 35785 /* IDB_OBM12_CONTROL_PIPE1 */ "IDB_OBM12_CONTROL_PIPE1", 35786 /* IDB_OBM12_CONTROL_PIPE2 */ "IDB_OBM12_CONTROL_PIPE2", 35787 /* IDB_OBM12_CONTROL_PIPE3 */ "IDB_OBM12_CONTROL_PIPE3", 35788 /* IDB_OBM12_CT_THRESHOLD */ "", 35789 /* IDB_OBM12_CT_THRESHOLD_PIPE0 */ "", 35790 /* IDB_OBM12_CT_THRESHOLD_PIPE1 */ "", 35791 /* IDB_OBM12_CT_THRESHOLD_PIPE2 */ "", 35792 /* IDB_OBM12_CT_THRESHOLD_PIPE3 */ "", 35793 /* IDB_OBM12_DATA_ECC_STATUS */ "IDB_OBM12_DATA_ECC_STATUS", 35794 /* IDB_OBM12_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM12_DATA_ECC_STATUS_PIPE0", 35795 /* IDB_OBM12_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM12_DATA_ECC_STATUS_PIPE1", 35796 /* IDB_OBM12_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM12_DATA_ECC_STATUS_PIPE2", 35797 /* IDB_OBM12_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM12_DATA_ECC_STATUS_PIPE3", 35798 /* IDB_OBM12_DBG_A */ "IDB_OBM12_FORCE_SAF_CONFIG", 35799 /* IDB_OBM12_DBG_A_PIPE0 */ "IDB_OBM12_FORCE_SAF_CONFIG_PIPE0", 35800 /* IDB_OBM12_DBG_A_PIPE1 */ "IDB_OBM12_FORCE_SAF_CONFIG_PIPE1", 35801 /* IDB_OBM12_DBG_A_PIPE2 */ "IDB_OBM12_FORCE_SAF_CONFIG_PIPE2", 35802 /* IDB_OBM12_DBG_A_PIPE3 */ "IDB_OBM12_FORCE_SAF_CONFIG_PIPE3", 35803 /* IDB_OBM12_FC_THRESHOLD */ "", 35804 /* IDB_OBM12_FC_THRESHOLD_1 */ "", 35805 /* IDB_OBM12_FC_THRESHOLD_1_PIPE0 */ "", 35806 /* IDB_OBM12_FC_THRESHOLD_1_PIPE1 */ "", 35807 /* IDB_OBM12_FC_THRESHOLD_1_PIPE2 */ "", 35808 /* IDB_OBM12_FC_THRESHOLD_1_PIPE3 */ "", 35809 /* IDB_OBM12_FC_THRESHOLD_PIPE0 */ "", 35810 /* IDB_OBM12_FC_THRESHOLD_PIPE1 */ "", 35811 /* IDB_OBM12_FC_THRESHOLD_PIPE2 */ "", 35812 /* IDB_OBM12_FC_THRESHOLD_PIPE3 */ "", 35813 /* IDB_OBM12_FLOW_CONTROL_CONFIG */ "", 35814 /* IDB_OBM12_FLOW_CONTROL_CONFIG_PIPE0 */ "", 35815 /* IDB_OBM12_FLOW_CONTROL_CONFIG_PIPE1 */ "", 35816 /* IDB_OBM12_FLOW_CONTROL_CONFIG_PIPE2 */ "", 35817 /* IDB_OBM12_FLOW_CONTROL_CONFIG_PIPE3 */ "", 35818 /* IDB_OBM12_FLOW_CONTROL_EVENT_COUNT */ "", 35819 /* IDB_OBM12_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 35820 /* IDB_OBM12_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 35821 /* IDB_OBM12_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 35822 /* IDB_OBM12_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 35823 /* IDB_OBM12_FORCE_SAF_STATUS */ "", 35824 /* IDB_OBM12_FORCE_SAF_STATUS_PIPE0 */ "", 35825 /* IDB_OBM12_FORCE_SAF_STATUS_PIPE1 */ "", 35826 /* IDB_OBM12_INNER_TPID */ "", 35827 /* IDB_OBM12_INNER_TPID_PIPE0 */ "", 35828 /* IDB_OBM12_INNER_TPID_PIPE1 */ "", 35829 /* IDB_OBM12_INNER_TPID_PIPE2 */ "", 35830 /* IDB_OBM12_INNER_TPID_PIPE3 */ "", 35831 /* IDB_OBM12_LOSSLESS0_BYTE_DROP_COUNT */ "", 35832 /* IDB_OBM12_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 35833 /* IDB_OBM12_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 35834 /* IDB_OBM12_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 35835 /* IDB_OBM12_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 35836 /* IDB_OBM12_LOSSLESS0_PKT_DROP_COUNT */ "", 35837 /* IDB_OBM12_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 35838 /* IDB_OBM12_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 35839 /* IDB_OBM12_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 35840 /* IDB_OBM12_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 35841 /* IDB_OBM12_LOSSLESS1_BYTE_DROP_COUNT */ "", 35842 /* IDB_OBM12_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 35843 /* IDB_OBM12_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 35844 /* IDB_OBM12_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 35845 /* IDB_OBM12_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 35846 /* IDB_OBM12_LOSSLESS1_PKT_DROP_COUNT */ "", 35847 /* IDB_OBM12_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 35848 /* IDB_OBM12_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 35849 /* IDB_OBM12_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 35850 /* IDB_OBM12_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 35851 /* IDB_OBM12_LOSSY_HI_BYTE_DROP_COUNT */ "", 35852 /* IDB_OBM12_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 35853 /* IDB_OBM12_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 35854 /* IDB_OBM12_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 35855 /* IDB_OBM12_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 35856 /* IDB_OBM12_LOSSY_HI_PKT_DROP_COUNT */ "", 35857 /* IDB_OBM12_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 35858 /* IDB_OBM12_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 35859 /* IDB_OBM12_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 35860 /* IDB_OBM12_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 35861 /* IDB_OBM12_LOSSY_LO_BYTE_DROP_COUNT */ "", 35862 /* IDB_OBM12_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 35863 /* IDB_OBM12_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 35864 /* IDB_OBM12_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 35865 /* IDB_OBM12_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 35866 /* IDB_OBM12_LOSSY_LO_PKT_DROP_COUNT */ "", 35867 /* IDB_OBM12_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 35868 /* IDB_OBM12_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 35869 /* IDB_OBM12_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 35870 /* IDB_OBM12_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 35871 /* IDB_OBM12_MAX_USAGE */ "IDB_OBM12_MAX_USAGE", 35872 /* IDB_OBM12_MAX_USAGE_1 */ "IDB_OBM12_MAX_USAGE_1", 35873 /* IDB_OBM12_MAX_USAGE_1_PIPE0 */ "IDB_OBM12_MAX_USAGE_1_PIPE0", 35874 /* IDB_OBM12_MAX_USAGE_1_PIPE1 */ "IDB_OBM12_MAX_USAGE_1_PIPE1", 35875 /* IDB_OBM12_MAX_USAGE_1_PIPE2 */ "IDB_OBM12_MAX_USAGE_1_PIPE2", 35876 /* IDB_OBM12_MAX_USAGE_1_PIPE3 */ "IDB_OBM12_MAX_USAGE_1_PIPE3", 35877 /* IDB_OBM12_MAX_USAGE_PIPE0 */ "IDB_OBM12_MAX_USAGE_PIPE0", 35878 /* IDB_OBM12_MAX_USAGE_PIPE1 */ "IDB_OBM12_MAX_USAGE_PIPE1", 35879 /* IDB_OBM12_MAX_USAGE_PIPE2 */ "IDB_OBM12_MAX_USAGE_PIPE2", 35880 /* IDB_OBM12_MAX_USAGE_PIPE3 */ "IDB_OBM12_MAX_USAGE_PIPE3", 35881 /* IDB_OBM12_MAX_USAGE_SELECT */ "", 35882 /* IDB_OBM12_MAX_USAGE_SELECT_PIPE0 */ "", 35883 /* IDB_OBM12_MAX_USAGE_SELECT_PIPE1 */ "", 35884 /* IDB_OBM12_MAX_USAGE_SELECT_PIPE2 */ "", 35885 /* IDB_OBM12_MAX_USAGE_SELECT_PIPE3 */ "", 35886 /* IDB_OBM12_NIV_ETHERTYPE */ "", 35887 /* IDB_OBM12_NIV_ETHERTYPE_PIPE0 */ "", 35888 /* IDB_OBM12_NIV_ETHERTYPE_PIPE1 */ "", 35889 /* IDB_OBM12_NIV_ETHERTYPE_PIPE2 */ "", 35890 /* IDB_OBM12_NIV_ETHERTYPE_PIPE3 */ "", 35891 /* IDB_OBM12_OUTER_TPID */ "", 35892 /* IDB_OBM12_OUTER_TPID_0 */ "", 35893 /* IDB_OBM12_OUTER_TPID_1 */ "", 35894 /* IDB_OBM12_OUTER_TPID_2 */ "", 35895 /* IDB_OBM12_OUTER_TPID_3 */ "", 35896 /* IDB_OBM12_OUTER_TPID_0_PIPE0 */ "", 35897 /* IDB_OBM12_OUTER_TPID_0_PIPE1 */ "", 35898 /* IDB_OBM12_OUTER_TPID_0_PIPE2 */ "", 35899 /* IDB_OBM12_OUTER_TPID_0_PIPE3 */ "", 35900 /* IDB_OBM12_OUTER_TPID_1_PIPE0 */ "", 35901 /* IDB_OBM12_OUTER_TPID_1_PIPE1 */ "", 35902 /* IDB_OBM12_OUTER_TPID_1_PIPE2 */ "", 35903 /* IDB_OBM12_OUTER_TPID_1_PIPE3 */ "", 35904 /* IDB_OBM12_OUTER_TPID_2_PIPE0 */ "", 35905 /* IDB_OBM12_OUTER_TPID_2_PIPE1 */ "", 35906 /* IDB_OBM12_OUTER_TPID_2_PIPE2 */ "", 35907 /* IDB_OBM12_OUTER_TPID_2_PIPE3 */ "", 35908 /* IDB_OBM12_OUTER_TPID_3_PIPE0 */ "", 35909 /* IDB_OBM12_OUTER_TPID_3_PIPE1 */ "", 35910 /* IDB_OBM12_OUTER_TPID_3_PIPE2 */ "", 35911 /* IDB_OBM12_OUTER_TPID_3_PIPE3 */ "", 35912 /* IDB_OBM12_OUTER_TPID_PIPE0 */ "", 35913 /* IDB_OBM12_OUTER_TPID_PIPE1 */ "", 35914 /* IDB_OBM12_OUTER_TPID_PIPE2 */ "", 35915 /* IDB_OBM12_OUTER_TPID_PIPE3 */ "", 35916 /* IDB_OBM12_OVERSUB_MON_ECC_STATUS */ "IDB_OBM12_OVERSUB_MON_ECC_STATUS", 35917 /* IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE0", 35918 /* IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE1", 35919 /* IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE2", 35920 /* IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM12_OVERSUB_MON_ECC_STATUS_PIPE3", 35921 /* IDB_OBM12_PE_ETHERTYPE */ "", 35922 /* IDB_OBM12_PE_ETHERTYPE_PIPE0 */ "", 35923 /* IDB_OBM12_PE_ETHERTYPE_PIPE1 */ "", 35924 /* IDB_OBM12_PE_ETHERTYPE_PIPE2 */ "", 35925 /* IDB_OBM12_PE_ETHERTYPE_PIPE3 */ "", 35926 /* IDB_OBM12_PORT_CONFIG */ "", 35927 /* IDB_OBM12_PORT_CONFIG_PIPE0 */ "", 35928 /* IDB_OBM12_PORT_CONFIG_PIPE1 */ "", 35929 /* IDB_OBM12_PORT_CONFIG_PIPE2 */ "", 35930 /* IDB_OBM12_PORT_CONFIG_PIPE3 */ "", 35931 /* IDB_OBM12_PROTOCOL_CONTROL_0 */ "", 35932 /* IDB_OBM12_PROTOCOL_CONTROL_1 */ "", 35933 /* IDB_OBM12_PROTOCOL_CONTROL_2 */ "", 35934 /* IDB_OBM12_PROTOCOL_CONTROL_0_PIPE0 */ "", 35935 /* IDB_OBM12_PROTOCOL_CONTROL_0_PIPE1 */ "", 35936 /* IDB_OBM12_PROTOCOL_CONTROL_0_PIPE2 */ "", 35937 /* IDB_OBM12_PROTOCOL_CONTROL_0_PIPE3 */ "", 35938 /* IDB_OBM12_PROTOCOL_CONTROL_1_PIPE0 */ "", 35939 /* IDB_OBM12_PROTOCOL_CONTROL_1_PIPE1 */ "", 35940 /* IDB_OBM12_PROTOCOL_CONTROL_1_PIPE2 */ "", 35941 /* IDB_OBM12_PROTOCOL_CONTROL_1_PIPE3 */ "", 35942 /* IDB_OBM12_PROTOCOL_CONTROL_2_PIPE0 */ "", 35943 /* IDB_OBM12_PROTOCOL_CONTROL_2_PIPE1 */ "", 35944 /* IDB_OBM12_PROTOCOL_CONTROL_2_PIPE2 */ "", 35945 /* IDB_OBM12_PROTOCOL_CONTROL_2_PIPE3 */ "", 35946 /* IDB_OBM12_QUEUE_ECC_STATUS */ "IDB_OBM12_QUEUE_ECC_STATUS", 35947 /* IDB_OBM12_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM12_QUEUE_ECC_STATUS_PIPE0", 35948 /* IDB_OBM12_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM12_QUEUE_ECC_STATUS_PIPE1", 35949 /* IDB_OBM12_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM12_QUEUE_ECC_STATUS_PIPE2", 35950 /* IDB_OBM12_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM12_QUEUE_ECC_STATUS_PIPE3", 35951 /* IDB_OBM12_RAM_CONTROL */ "IDB_OBM12_RAM_CONTROL", 35952 /* IDB_OBM12_RAM_CONTROL_PIPE0 */ "IDB_OBM12_RAM_CONTROL_PIPE0", 35953 /* IDB_OBM12_RAM_CONTROL_PIPE1 */ "IDB_OBM12_RAM_CONTROL_PIPE1", 35954 /* IDB_OBM12_RAM_CONTROL_PIPE2 */ "IDB_OBM12_RAM_CONTROL_PIPE2", 35955 /* IDB_OBM12_RAM_CONTROL_PIPE3 */ "IDB_OBM12_RAM_CONTROL_PIPE3", 35956 /* IDB_OBM12_SER_CONTROL */ "IDB_OBM12_SER_CONTROL", 35957 /* IDB_OBM12_SER_CONTROL_PIPE0 */ "IDB_OBM12_SER_CONTROL_PIPE0", 35958 /* IDB_OBM12_SER_CONTROL_PIPE1 */ "IDB_OBM12_SER_CONTROL_PIPE1", 35959 /* IDB_OBM12_SHARED_CONFIG */ "IDB_OBM12_SHARED_CONFIG", 35960 /* IDB_OBM12_SHARED_CONFIG_PIPE0 */ "IDB_OBM12_SHARED_CONFIG_PIPE0", 35961 /* IDB_OBM12_SHARED_CONFIG_PIPE1 */ "IDB_OBM12_SHARED_CONFIG_PIPE1", 35962 /* IDB_OBM12_SHARED_CONFIG_PIPE2 */ "IDB_OBM12_SHARED_CONFIG_PIPE2", 35963 /* IDB_OBM12_SHARED_CONFIG_PIPE3 */ "IDB_OBM12_SHARED_CONFIG_PIPE3", 35964 /* IDB_OBM12_SHARED_USAGE */ "IDB_OBM12_SHARED_USAGE", 35965 /* IDB_OBM12_SHARED_USAGE_PIPE0 */ "IDB_OBM12_SHARED_USAGE_PIPE0", 35966 /* IDB_OBM12_SHARED_USAGE_PIPE1 */ "IDB_OBM12_SHARED_USAGE_PIPE1", 35967 /* IDB_OBM12_SHARED_USAGE_PIPE2 */ "IDB_OBM12_SHARED_USAGE_PIPE2", 35968 /* IDB_OBM12_SHARED_USAGE_PIPE3 */ "IDB_OBM12_SHARED_USAGE_PIPE3", 35969 /* IDB_OBM12_THRESHOLD */ "", 35970 /* IDB_OBM12_THRESHOLD_1 */ "", 35971 /* IDB_OBM12_THRESHOLD_1_PIPE0 */ "", 35972 /* IDB_OBM12_THRESHOLD_1_PIPE1 */ "", 35973 /* IDB_OBM12_THRESHOLD_1_PIPE2 */ "", 35974 /* IDB_OBM12_THRESHOLD_1_PIPE3 */ "", 35975 /* IDB_OBM12_THRESHOLD_PIPE0 */ "", 35976 /* IDB_OBM12_THRESHOLD_PIPE1 */ "", 35977 /* IDB_OBM12_THRESHOLD_PIPE2 */ "", 35978 /* IDB_OBM12_THRESHOLD_PIPE3 */ "", 35979 /* IDB_OBM12_USAGE */ "", 35980 /* IDB_OBM12_USAGE_PIPE0 */ "", 35981 /* IDB_OBM12_USAGE_PIPE1 */ "", 35982 /* IDB_OBM12_USAGE_PIPE2 */ "", 35983 /* IDB_OBM12_USAGE_PIPE3 */ "", 35984 /* IDB_OBM13_BANK_CONFIG */ "IDB_OBM13_BANK_CONFIG", 35985 /* IDB_OBM13_BANK_CONFIG_PIPE0 */ "IDB_OBM13_BANK_CONFIG_PIPE0", 35986 /* IDB_OBM13_BANK_CONFIG_PIPE1 */ "IDB_OBM13_BANK_CONFIG_PIPE1", 35987 /* IDB_OBM13_BANK_CONFIG_PIPE2 */ "IDB_OBM13_BANK_CONFIG_PIPE2", 35988 /* IDB_OBM13_BANK_CONFIG_PIPE3 */ "IDB_OBM13_BANK_CONFIG_PIPE3", 35989 /* IDB_OBM13_BUFFER_CONFIG */ "", 35990 /* IDB_OBM13_BUFFER_CONFIG_PIPE0 */ "", 35991 /* IDB_OBM13_BUFFER_CONFIG_PIPE1 */ "", 35992 /* IDB_OBM13_CA_CONTROL */ "IDB_OBM13_CA_CONTROL", 35993 /* IDB_OBM13_CA_CONTROL_PIPE0 */ "IDB_OBM13_CA_CONTROL_PIPE0", 35994 /* IDB_OBM13_CA_CONTROL_PIPE1 */ "IDB_OBM13_CA_CONTROL_PIPE1", 35995 /* IDB_OBM13_CA_CONTROL_PIPE2 */ "IDB_OBM13_CA_CONTROL_PIPE2", 35996 /* IDB_OBM13_CA_CONTROL_PIPE3 */ "IDB_OBM13_CA_CONTROL_PIPE3", 35997 /* IDB_OBM13_CA_CT_CONTROL */ "IDB_OBM13_CA_CT_CONTROL", 35998 /* IDB_OBM13_CA_CT_CONTROL_PIPE0 */ "IDB_OBM13_CA_CT_CONTROL_PIPE0", 35999 /* IDB_OBM13_CA_CT_CONTROL_PIPE1 */ "IDB_OBM13_CA_CT_CONTROL_PIPE1", 36000 /* IDB_OBM13_CA_CT_CONTROL_PIPE2 */ "IDB_OBM13_CA_CT_CONTROL_PIPE2", 36001 /* IDB_OBM13_CA_CT_CONTROL_PIPE3 */ "IDB_OBM13_CA_CT_CONTROL_PIPE3", 36002 /* IDB_OBM13_CA_ECC_STATUS */ "IDB_OBM13_CA_ECC_STATUS", 36003 /* IDB_OBM13_CA_ECC_STATUS_PIPE0 */ "IDB_OBM13_CA_ECC_STATUS_PIPE0", 36004 /* IDB_OBM13_CA_ECC_STATUS_PIPE1 */ "IDB_OBM13_CA_ECC_STATUS_PIPE1", 36005 /* IDB_OBM13_CA_ECC_STATUS_PIPE2 */ "IDB_OBM13_CA_ECC_STATUS_PIPE2", 36006 /* IDB_OBM13_CA_ECC_STATUS_PIPE3 */ "IDB_OBM13_CA_ECC_STATUS_PIPE3", 36007 /* IDB_OBM13_CA_HW_STATUS */ "IDB_OBM13_CA_HW_STATUS", 36008 /* IDB_OBM13_CA_HW_STATUS_PIPE0 */ "IDB_OBM13_CA_HW_STATUS_PIPE0", 36009 /* IDB_OBM13_CA_HW_STATUS_PIPE1 */ "IDB_OBM13_CA_HW_STATUS_PIPE1", 36010 /* IDB_OBM13_CA_HW_STATUS_PIPE2 */ "IDB_OBM13_CA_HW_STATUS_PIPE2", 36011 /* IDB_OBM13_CA_HW_STATUS_PIPE3 */ "IDB_OBM13_CA_HW_STATUS_PIPE3", 36012 /* IDB_OBM13_CA_POINTER_STATUS */ "IDB_OBM13_CA_POINTER_STATUS", 36013 /* IDB_OBM13_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM13_CA_POINTER_STATUS_PIPE0", 36014 /* IDB_OBM13_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM13_CA_POINTER_STATUS_PIPE1", 36015 /* IDB_OBM13_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM13_CA_POINTER_STATUS_PIPE2", 36016 /* IDB_OBM13_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM13_CA_POINTER_STATUS_PIPE3", 36017 /* IDB_OBM13_CONTROL */ "IDB_OBM13_CONTROL", 36018 /* IDB_OBM13_CONTROL_PIPE0 */ "IDB_OBM13_CONTROL_PIPE0", 36019 /* IDB_OBM13_CONTROL_PIPE1 */ "IDB_OBM13_CONTROL_PIPE1", 36020 /* IDB_OBM13_CONTROL_PIPE2 */ "IDB_OBM13_CONTROL_PIPE2", 36021 /* IDB_OBM13_CONTROL_PIPE3 */ "IDB_OBM13_CONTROL_PIPE3", 36022 /* IDB_OBM13_CT_THRESHOLD */ "", 36023 /* IDB_OBM13_CT_THRESHOLD_PIPE0 */ "", 36024 /* IDB_OBM13_CT_THRESHOLD_PIPE1 */ "", 36025 /* IDB_OBM13_CT_THRESHOLD_PIPE2 */ "", 36026 /* IDB_OBM13_CT_THRESHOLD_PIPE3 */ "", 36027 /* IDB_OBM13_DATA_ECC_STATUS */ "IDB_OBM13_DATA_ECC_STATUS", 36028 /* IDB_OBM13_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM13_DATA_ECC_STATUS_PIPE0", 36029 /* IDB_OBM13_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM13_DATA_ECC_STATUS_PIPE1", 36030 /* IDB_OBM13_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM13_DATA_ECC_STATUS_PIPE2", 36031 /* IDB_OBM13_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM13_DATA_ECC_STATUS_PIPE3", 36032 /* IDB_OBM13_DBG_A */ "IDB_OBM13_FORCE_SAF_CONFIG", 36033 /* IDB_OBM13_DBG_A_PIPE0 */ "IDB_OBM13_FORCE_SAF_CONFIG_PIPE0", 36034 /* IDB_OBM13_DBG_A_PIPE1 */ "IDB_OBM13_FORCE_SAF_CONFIG_PIPE1", 36035 /* IDB_OBM13_DBG_A_PIPE2 */ "IDB_OBM13_FORCE_SAF_CONFIG_PIPE2", 36036 /* IDB_OBM13_DBG_A_PIPE3 */ "IDB_OBM13_FORCE_SAF_CONFIG_PIPE3", 36037 /* IDB_OBM13_FC_THRESHOLD */ "", 36038 /* IDB_OBM13_FC_THRESHOLD_1 */ "", 36039 /* IDB_OBM13_FC_THRESHOLD_1_PIPE0 */ "", 36040 /* IDB_OBM13_FC_THRESHOLD_1_PIPE1 */ "", 36041 /* IDB_OBM13_FC_THRESHOLD_1_PIPE2 */ "", 36042 /* IDB_OBM13_FC_THRESHOLD_1_PIPE3 */ "", 36043 /* IDB_OBM13_FC_THRESHOLD_PIPE0 */ "", 36044 /* IDB_OBM13_FC_THRESHOLD_PIPE1 */ "", 36045 /* IDB_OBM13_FC_THRESHOLD_PIPE2 */ "", 36046 /* IDB_OBM13_FC_THRESHOLD_PIPE3 */ "", 36047 /* IDB_OBM13_FLOW_CONTROL_CONFIG */ "", 36048 /* IDB_OBM13_FLOW_CONTROL_CONFIG_PIPE0 */ "", 36049 /* IDB_OBM13_FLOW_CONTROL_CONFIG_PIPE1 */ "", 36050 /* IDB_OBM13_FLOW_CONTROL_CONFIG_PIPE2 */ "", 36051 /* IDB_OBM13_FLOW_CONTROL_CONFIG_PIPE3 */ "", 36052 /* IDB_OBM13_FLOW_CONTROL_EVENT_COUNT */ "", 36053 /* IDB_OBM13_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 36054 /* IDB_OBM13_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 36055 /* IDB_OBM13_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 36056 /* IDB_OBM13_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 36057 /* IDB_OBM13_FORCE_SAF_STATUS */ "", 36058 /* IDB_OBM13_FORCE_SAF_STATUS_PIPE0 */ "", 36059 /* IDB_OBM13_FORCE_SAF_STATUS_PIPE1 */ "", 36060 /* IDB_OBM13_INNER_TPID */ "", 36061 /* IDB_OBM13_INNER_TPID_PIPE0 */ "", 36062 /* IDB_OBM13_INNER_TPID_PIPE1 */ "", 36063 /* IDB_OBM13_INNER_TPID_PIPE2 */ "", 36064 /* IDB_OBM13_INNER_TPID_PIPE3 */ "", 36065 /* IDB_OBM13_LOSSLESS0_BYTE_DROP_COUNT */ "", 36066 /* IDB_OBM13_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 36067 /* IDB_OBM13_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 36068 /* IDB_OBM13_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 36069 /* IDB_OBM13_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 36070 /* IDB_OBM13_LOSSLESS0_PKT_DROP_COUNT */ "", 36071 /* IDB_OBM13_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 36072 /* IDB_OBM13_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 36073 /* IDB_OBM13_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 36074 /* IDB_OBM13_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 36075 /* IDB_OBM13_LOSSLESS1_BYTE_DROP_COUNT */ "", 36076 /* IDB_OBM13_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 36077 /* IDB_OBM13_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 36078 /* IDB_OBM13_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 36079 /* IDB_OBM13_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 36080 /* IDB_OBM13_LOSSLESS1_PKT_DROP_COUNT */ "", 36081 /* IDB_OBM13_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 36082 /* IDB_OBM13_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 36083 /* IDB_OBM13_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 36084 /* IDB_OBM13_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 36085 /* IDB_OBM13_LOSSY_HI_BYTE_DROP_COUNT */ "", 36086 /* IDB_OBM13_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 36087 /* IDB_OBM13_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 36088 /* IDB_OBM13_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 36089 /* IDB_OBM13_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 36090 /* IDB_OBM13_LOSSY_HI_PKT_DROP_COUNT */ "", 36091 /* IDB_OBM13_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 36092 /* IDB_OBM13_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 36093 /* IDB_OBM13_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 36094 /* IDB_OBM13_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 36095 /* IDB_OBM13_LOSSY_LO_BYTE_DROP_COUNT */ "", 36096 /* IDB_OBM13_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 36097 /* IDB_OBM13_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 36098 /* IDB_OBM13_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 36099 /* IDB_OBM13_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 36100 /* IDB_OBM13_LOSSY_LO_PKT_DROP_COUNT */ "", 36101 /* IDB_OBM13_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 36102 /* IDB_OBM13_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 36103 /* IDB_OBM13_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 36104 /* IDB_OBM13_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 36105 /* IDB_OBM13_MAX_USAGE */ "IDB_OBM13_MAX_USAGE", 36106 /* IDB_OBM13_MAX_USAGE_1 */ "IDB_OBM13_MAX_USAGE_1", 36107 /* IDB_OBM13_MAX_USAGE_1_PIPE0 */ "IDB_OBM13_MAX_USAGE_1_PIPE0", 36108 /* IDB_OBM13_MAX_USAGE_1_PIPE1 */ "IDB_OBM13_MAX_USAGE_1_PIPE1", 36109 /* IDB_OBM13_MAX_USAGE_1_PIPE2 */ "IDB_OBM13_MAX_USAGE_1_PIPE2", 36110 /* IDB_OBM13_MAX_USAGE_1_PIPE3 */ "IDB_OBM13_MAX_USAGE_1_PIPE3", 36111 /* IDB_OBM13_MAX_USAGE_PIPE0 */ "IDB_OBM13_MAX_USAGE_PIPE0", 36112 /* IDB_OBM13_MAX_USAGE_PIPE1 */ "IDB_OBM13_MAX_USAGE_PIPE1", 36113 /* IDB_OBM13_MAX_USAGE_PIPE2 */ "IDB_OBM13_MAX_USAGE_PIPE2", 36114 /* IDB_OBM13_MAX_USAGE_PIPE3 */ "IDB_OBM13_MAX_USAGE_PIPE3", 36115 /* IDB_OBM13_MAX_USAGE_SELECT */ "", 36116 /* IDB_OBM13_MAX_USAGE_SELECT_PIPE0 */ "", 36117 /* IDB_OBM13_MAX_USAGE_SELECT_PIPE1 */ "", 36118 /* IDB_OBM13_MAX_USAGE_SELECT_PIPE2 */ "", 36119 /* IDB_OBM13_MAX_USAGE_SELECT_PIPE3 */ "", 36120 /* IDB_OBM13_NIV_ETHERTYPE */ "", 36121 /* IDB_OBM13_NIV_ETHERTYPE_PIPE0 */ "", 36122 /* IDB_OBM13_NIV_ETHERTYPE_PIPE1 */ "", 36123 /* IDB_OBM13_NIV_ETHERTYPE_PIPE2 */ "", 36124 /* IDB_OBM13_NIV_ETHERTYPE_PIPE3 */ "", 36125 /* IDB_OBM13_OUTER_TPID */ "", 36126 /* IDB_OBM13_OUTER_TPID_0 */ "", 36127 /* IDB_OBM13_OUTER_TPID_1 */ "", 36128 /* IDB_OBM13_OUTER_TPID_2 */ "", 36129 /* IDB_OBM13_OUTER_TPID_3 */ "", 36130 /* IDB_OBM13_OUTER_TPID_0_PIPE0 */ "", 36131 /* IDB_OBM13_OUTER_TPID_0_PIPE1 */ "", 36132 /* IDB_OBM13_OUTER_TPID_0_PIPE2 */ "", 36133 /* IDB_OBM13_OUTER_TPID_0_PIPE3 */ "", 36134 /* IDB_OBM13_OUTER_TPID_1_PIPE0 */ "", 36135 /* IDB_OBM13_OUTER_TPID_1_PIPE1 */ "", 36136 /* IDB_OBM13_OUTER_TPID_1_PIPE2 */ "", 36137 /* IDB_OBM13_OUTER_TPID_1_PIPE3 */ "", 36138 /* IDB_OBM13_OUTER_TPID_2_PIPE0 */ "", 36139 /* IDB_OBM13_OUTER_TPID_2_PIPE1 */ "", 36140 /* IDB_OBM13_OUTER_TPID_2_PIPE2 */ "", 36141 /* IDB_OBM13_OUTER_TPID_2_PIPE3 */ "", 36142 /* IDB_OBM13_OUTER_TPID_3_PIPE0 */ "", 36143 /* IDB_OBM13_OUTER_TPID_3_PIPE1 */ "", 36144 /* IDB_OBM13_OUTER_TPID_3_PIPE2 */ "", 36145 /* IDB_OBM13_OUTER_TPID_3_PIPE3 */ "", 36146 /* IDB_OBM13_OUTER_TPID_PIPE0 */ "", 36147 /* IDB_OBM13_OUTER_TPID_PIPE1 */ "", 36148 /* IDB_OBM13_OUTER_TPID_PIPE2 */ "", 36149 /* IDB_OBM13_OUTER_TPID_PIPE3 */ "", 36150 /* IDB_OBM13_OVERSUB_MON_ECC_STATUS */ "IDB_OBM13_OVERSUB_MON_ECC_STATUS", 36151 /* IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE0", 36152 /* IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE1", 36153 /* IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE2", 36154 /* IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM13_OVERSUB_MON_ECC_STATUS_PIPE3", 36155 /* IDB_OBM13_PE_ETHERTYPE */ "", 36156 /* IDB_OBM13_PE_ETHERTYPE_PIPE0 */ "", 36157 /* IDB_OBM13_PE_ETHERTYPE_PIPE1 */ "", 36158 /* IDB_OBM13_PE_ETHERTYPE_PIPE2 */ "", 36159 /* IDB_OBM13_PE_ETHERTYPE_PIPE3 */ "", 36160 /* IDB_OBM13_PORT_CONFIG */ "", 36161 /* IDB_OBM13_PORT_CONFIG_PIPE0 */ "", 36162 /* IDB_OBM13_PORT_CONFIG_PIPE1 */ "", 36163 /* IDB_OBM13_PORT_CONFIG_PIPE2 */ "", 36164 /* IDB_OBM13_PORT_CONFIG_PIPE3 */ "", 36165 /* IDB_OBM13_PROTOCOL_CONTROL_0 */ "", 36166 /* IDB_OBM13_PROTOCOL_CONTROL_1 */ "", 36167 /* IDB_OBM13_PROTOCOL_CONTROL_2 */ "", 36168 /* IDB_OBM13_PROTOCOL_CONTROL_0_PIPE0 */ "", 36169 /* IDB_OBM13_PROTOCOL_CONTROL_0_PIPE1 */ "", 36170 /* IDB_OBM13_PROTOCOL_CONTROL_0_PIPE2 */ "", 36171 /* IDB_OBM13_PROTOCOL_CONTROL_0_PIPE3 */ "", 36172 /* IDB_OBM13_PROTOCOL_CONTROL_1_PIPE0 */ "", 36173 /* IDB_OBM13_PROTOCOL_CONTROL_1_PIPE1 */ "", 36174 /* IDB_OBM13_PROTOCOL_CONTROL_1_PIPE2 */ "", 36175 /* IDB_OBM13_PROTOCOL_CONTROL_1_PIPE3 */ "", 36176 /* IDB_OBM13_PROTOCOL_CONTROL_2_PIPE0 */ "", 36177 /* IDB_OBM13_PROTOCOL_CONTROL_2_PIPE1 */ "", 36178 /* IDB_OBM13_PROTOCOL_CONTROL_2_PIPE2 */ "", 36179 /* IDB_OBM13_PROTOCOL_CONTROL_2_PIPE3 */ "", 36180 /* IDB_OBM13_QUEUE_ECC_STATUS */ "IDB_OBM13_QUEUE_ECC_STATUS", 36181 /* IDB_OBM13_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM13_QUEUE_ECC_STATUS_PIPE0", 36182 /* IDB_OBM13_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM13_QUEUE_ECC_STATUS_PIPE1", 36183 /* IDB_OBM13_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM13_QUEUE_ECC_STATUS_PIPE2", 36184 /* IDB_OBM13_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM13_QUEUE_ECC_STATUS_PIPE3", 36185 /* IDB_OBM13_RAM_CONTROL */ "IDB_OBM13_RAM_CONTROL", 36186 /* IDB_OBM13_RAM_CONTROL_PIPE0 */ "IDB_OBM13_RAM_CONTROL_PIPE0", 36187 /* IDB_OBM13_RAM_CONTROL_PIPE1 */ "IDB_OBM13_RAM_CONTROL_PIPE1", 36188 /* IDB_OBM13_RAM_CONTROL_PIPE2 */ "IDB_OBM13_RAM_CONTROL_PIPE2", 36189 /* IDB_OBM13_RAM_CONTROL_PIPE3 */ "IDB_OBM13_RAM_CONTROL_PIPE3", 36190 /* IDB_OBM13_SER_CONTROL */ "IDB_OBM13_SER_CONTROL", 36191 /* IDB_OBM13_SER_CONTROL_PIPE0 */ "IDB_OBM13_SER_CONTROL_PIPE0", 36192 /* IDB_OBM13_SER_CONTROL_PIPE1 */ "IDB_OBM13_SER_CONTROL_PIPE1", 36193 /* IDB_OBM13_SHARED_CONFIG */ "IDB_OBM13_SHARED_CONFIG", 36194 /* IDB_OBM13_SHARED_CONFIG_PIPE0 */ "IDB_OBM13_SHARED_CONFIG_PIPE0", 36195 /* IDB_OBM13_SHARED_CONFIG_PIPE1 */ "IDB_OBM13_SHARED_CONFIG_PIPE1", 36196 /* IDB_OBM13_SHARED_CONFIG_PIPE2 */ "IDB_OBM13_SHARED_CONFIG_PIPE2", 36197 /* IDB_OBM13_SHARED_CONFIG_PIPE3 */ "IDB_OBM13_SHARED_CONFIG_PIPE3", 36198 /* IDB_OBM13_SHARED_USAGE */ "IDB_OBM13_SHARED_USAGE", 36199 /* IDB_OBM13_SHARED_USAGE_PIPE0 */ "IDB_OBM13_SHARED_USAGE_PIPE0", 36200 /* IDB_OBM13_SHARED_USAGE_PIPE1 */ "IDB_OBM13_SHARED_USAGE_PIPE1", 36201 /* IDB_OBM13_SHARED_USAGE_PIPE2 */ "IDB_OBM13_SHARED_USAGE_PIPE2", 36202 /* IDB_OBM13_SHARED_USAGE_PIPE3 */ "IDB_OBM13_SHARED_USAGE_PIPE3", 36203 /* IDB_OBM13_THRESHOLD */ "", 36204 /* IDB_OBM13_THRESHOLD_1 */ "", 36205 /* IDB_OBM13_THRESHOLD_1_PIPE0 */ "", 36206 /* IDB_OBM13_THRESHOLD_1_PIPE1 */ "", 36207 /* IDB_OBM13_THRESHOLD_1_PIPE2 */ "", 36208 /* IDB_OBM13_THRESHOLD_1_PIPE3 */ "", 36209 /* IDB_OBM13_THRESHOLD_PIPE0 */ "", 36210 /* IDB_OBM13_THRESHOLD_PIPE1 */ "", 36211 /* IDB_OBM13_THRESHOLD_PIPE2 */ "", 36212 /* IDB_OBM13_THRESHOLD_PIPE3 */ "", 36213 /* IDB_OBM13_USAGE */ "", 36214 /* IDB_OBM13_USAGE_PIPE0 */ "", 36215 /* IDB_OBM13_USAGE_PIPE1 */ "", 36216 /* IDB_OBM13_USAGE_PIPE2 */ "", 36217 /* IDB_OBM13_USAGE_PIPE3 */ "", 36218 /* IDB_OBM14_BANK_CONFIG */ "IDB_OBM14_BANK_CONFIG", 36219 /* IDB_OBM14_BANK_CONFIG_PIPE0 */ "IDB_OBM14_BANK_CONFIG_PIPE0", 36220 /* IDB_OBM14_BANK_CONFIG_PIPE1 */ "IDB_OBM14_BANK_CONFIG_PIPE1", 36221 /* IDB_OBM14_BANK_CONFIG_PIPE2 */ "IDB_OBM14_BANK_CONFIG_PIPE2", 36222 /* IDB_OBM14_BANK_CONFIG_PIPE3 */ "IDB_OBM14_BANK_CONFIG_PIPE3", 36223 /* IDB_OBM14_BUFFER_CONFIG */ "", 36224 /* IDB_OBM14_BUFFER_CONFIG_PIPE0 */ "", 36225 /* IDB_OBM14_BUFFER_CONFIG_PIPE1 */ "", 36226 /* IDB_OBM14_CA_CONTROL */ "IDB_OBM14_CA_CONTROL", 36227 /* IDB_OBM14_CA_CONTROL_PIPE0 */ "IDB_OBM14_CA_CONTROL_PIPE0", 36228 /* IDB_OBM14_CA_CONTROL_PIPE1 */ "IDB_OBM14_CA_CONTROL_PIPE1", 36229 /* IDB_OBM14_CA_CONTROL_PIPE2 */ "IDB_OBM14_CA_CONTROL_PIPE2", 36230 /* IDB_OBM14_CA_CONTROL_PIPE3 */ "IDB_OBM14_CA_CONTROL_PIPE3", 36231 /* IDB_OBM14_CA_CT_CONTROL */ "IDB_OBM14_CA_CT_CONTROL", 36232 /* IDB_OBM14_CA_CT_CONTROL_PIPE0 */ "IDB_OBM14_CA_CT_CONTROL_PIPE0", 36233 /* IDB_OBM14_CA_CT_CONTROL_PIPE1 */ "IDB_OBM14_CA_CT_CONTROL_PIPE1", 36234 /* IDB_OBM14_CA_CT_CONTROL_PIPE2 */ "IDB_OBM14_CA_CT_CONTROL_PIPE2", 36235 /* IDB_OBM14_CA_CT_CONTROL_PIPE3 */ "IDB_OBM14_CA_CT_CONTROL_PIPE3", 36236 /* IDB_OBM14_CA_ECC_STATUS */ "IDB_OBM14_CA_ECC_STATUS", 36237 /* IDB_OBM14_CA_ECC_STATUS_PIPE0 */ "IDB_OBM14_CA_ECC_STATUS_PIPE0", 36238 /* IDB_OBM14_CA_ECC_STATUS_PIPE1 */ "IDB_OBM14_CA_ECC_STATUS_PIPE1", 36239 /* IDB_OBM14_CA_ECC_STATUS_PIPE2 */ "IDB_OBM14_CA_ECC_STATUS_PIPE2", 36240 /* IDB_OBM14_CA_ECC_STATUS_PIPE3 */ "IDB_OBM14_CA_ECC_STATUS_PIPE3", 36241 /* IDB_OBM14_CA_HW_STATUS */ "IDB_OBM14_CA_HW_STATUS", 36242 /* IDB_OBM14_CA_HW_STATUS_PIPE0 */ "IDB_OBM14_CA_HW_STATUS_PIPE0", 36243 /* IDB_OBM14_CA_HW_STATUS_PIPE1 */ "IDB_OBM14_CA_HW_STATUS_PIPE1", 36244 /* IDB_OBM14_CA_HW_STATUS_PIPE2 */ "IDB_OBM14_CA_HW_STATUS_PIPE2", 36245 /* IDB_OBM14_CA_HW_STATUS_PIPE3 */ "IDB_OBM14_CA_HW_STATUS_PIPE3", 36246 /* IDB_OBM14_CA_POINTER_STATUS */ "IDB_OBM14_CA_POINTER_STATUS", 36247 /* IDB_OBM14_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM14_CA_POINTER_STATUS_PIPE0", 36248 /* IDB_OBM14_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM14_CA_POINTER_STATUS_PIPE1", 36249 /* IDB_OBM14_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM14_CA_POINTER_STATUS_PIPE2", 36250 /* IDB_OBM14_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM14_CA_POINTER_STATUS_PIPE3", 36251 /* IDB_OBM14_CONTROL */ "IDB_OBM14_CONTROL", 36252 /* IDB_OBM14_CONTROL_PIPE0 */ "IDB_OBM14_CONTROL_PIPE0", 36253 /* IDB_OBM14_CONTROL_PIPE1 */ "IDB_OBM14_CONTROL_PIPE1", 36254 /* IDB_OBM14_CONTROL_PIPE2 */ "IDB_OBM14_CONTROL_PIPE2", 36255 /* IDB_OBM14_CONTROL_PIPE3 */ "IDB_OBM14_CONTROL_PIPE3", 36256 /* IDB_OBM14_CT_THRESHOLD */ "", 36257 /* IDB_OBM14_CT_THRESHOLD_PIPE0 */ "", 36258 /* IDB_OBM14_CT_THRESHOLD_PIPE1 */ "", 36259 /* IDB_OBM14_CT_THRESHOLD_PIPE2 */ "", 36260 /* IDB_OBM14_CT_THRESHOLD_PIPE3 */ "", 36261 /* IDB_OBM14_DATA_ECC_STATUS */ "IDB_OBM14_DATA_ECC_STATUS", 36262 /* IDB_OBM14_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM14_DATA_ECC_STATUS_PIPE0", 36263 /* IDB_OBM14_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM14_DATA_ECC_STATUS_PIPE1", 36264 /* IDB_OBM14_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM14_DATA_ECC_STATUS_PIPE2", 36265 /* IDB_OBM14_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM14_DATA_ECC_STATUS_PIPE3", 36266 /* IDB_OBM14_DBG_A */ "IDB_OBM14_FORCE_SAF_CONFIG", 36267 /* IDB_OBM14_DBG_A_PIPE0 */ "IDB_OBM14_FORCE_SAF_CONFIG_PIPE0", 36268 /* IDB_OBM14_DBG_A_PIPE1 */ "IDB_OBM14_FORCE_SAF_CONFIG_PIPE1", 36269 /* IDB_OBM14_DBG_A_PIPE2 */ "IDB_OBM14_FORCE_SAF_CONFIG_PIPE2", 36270 /* IDB_OBM14_DBG_A_PIPE3 */ "IDB_OBM14_FORCE_SAF_CONFIG_PIPE3", 36271 /* IDB_OBM14_FC_THRESHOLD */ "", 36272 /* IDB_OBM14_FC_THRESHOLD_1 */ "", 36273 /* IDB_OBM14_FC_THRESHOLD_1_PIPE0 */ "", 36274 /* IDB_OBM14_FC_THRESHOLD_1_PIPE1 */ "", 36275 /* IDB_OBM14_FC_THRESHOLD_1_PIPE2 */ "", 36276 /* IDB_OBM14_FC_THRESHOLD_1_PIPE3 */ "", 36277 /* IDB_OBM14_FC_THRESHOLD_PIPE0 */ "", 36278 /* IDB_OBM14_FC_THRESHOLD_PIPE1 */ "", 36279 /* IDB_OBM14_FC_THRESHOLD_PIPE2 */ "", 36280 /* IDB_OBM14_FC_THRESHOLD_PIPE3 */ "", 36281 /* IDB_OBM14_FLOW_CONTROL_CONFIG */ "", 36282 /* IDB_OBM14_FLOW_CONTROL_CONFIG_PIPE0 */ "", 36283 /* IDB_OBM14_FLOW_CONTROL_CONFIG_PIPE1 */ "", 36284 /* IDB_OBM14_FLOW_CONTROL_CONFIG_PIPE2 */ "", 36285 /* IDB_OBM14_FLOW_CONTROL_CONFIG_PIPE3 */ "", 36286 /* IDB_OBM14_FLOW_CONTROL_EVENT_COUNT */ "", 36287 /* IDB_OBM14_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 36288 /* IDB_OBM14_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 36289 /* IDB_OBM14_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 36290 /* IDB_OBM14_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 36291 /* IDB_OBM14_FORCE_SAF_STATUS */ "", 36292 /* IDB_OBM14_FORCE_SAF_STATUS_PIPE0 */ "", 36293 /* IDB_OBM14_FORCE_SAF_STATUS_PIPE1 */ "", 36294 /* IDB_OBM14_INNER_TPID */ "", 36295 /* IDB_OBM14_INNER_TPID_PIPE0 */ "", 36296 /* IDB_OBM14_INNER_TPID_PIPE1 */ "", 36297 /* IDB_OBM14_INNER_TPID_PIPE2 */ "", 36298 /* IDB_OBM14_INNER_TPID_PIPE3 */ "", 36299 /* IDB_OBM14_LOSSLESS0_BYTE_DROP_COUNT */ "", 36300 /* IDB_OBM14_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 36301 /* IDB_OBM14_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 36302 /* IDB_OBM14_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 36303 /* IDB_OBM14_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 36304 /* IDB_OBM14_LOSSLESS0_PKT_DROP_COUNT */ "", 36305 /* IDB_OBM14_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 36306 /* IDB_OBM14_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 36307 /* IDB_OBM14_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 36308 /* IDB_OBM14_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 36309 /* IDB_OBM14_LOSSLESS1_BYTE_DROP_COUNT */ "", 36310 /* IDB_OBM14_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 36311 /* IDB_OBM14_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 36312 /* IDB_OBM14_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 36313 /* IDB_OBM14_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 36314 /* IDB_OBM14_LOSSLESS1_PKT_DROP_COUNT */ "", 36315 /* IDB_OBM14_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 36316 /* IDB_OBM14_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 36317 /* IDB_OBM14_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 36318 /* IDB_OBM14_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 36319 /* IDB_OBM14_LOSSY_HI_BYTE_DROP_COUNT */ "", 36320 /* IDB_OBM14_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 36321 /* IDB_OBM14_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 36322 /* IDB_OBM14_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 36323 /* IDB_OBM14_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 36324 /* IDB_OBM14_LOSSY_HI_PKT_DROP_COUNT */ "", 36325 /* IDB_OBM14_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 36326 /* IDB_OBM14_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 36327 /* IDB_OBM14_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 36328 /* IDB_OBM14_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 36329 /* IDB_OBM14_LOSSY_LO_BYTE_DROP_COUNT */ "", 36330 /* IDB_OBM14_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 36331 /* IDB_OBM14_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 36332 /* IDB_OBM14_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 36333 /* IDB_OBM14_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 36334 /* IDB_OBM14_LOSSY_LO_PKT_DROP_COUNT */ "", 36335 /* IDB_OBM14_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 36336 /* IDB_OBM14_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 36337 /* IDB_OBM14_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 36338 /* IDB_OBM14_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 36339 /* IDB_OBM14_MAX_USAGE */ "IDB_OBM14_MAX_USAGE", 36340 /* IDB_OBM14_MAX_USAGE_1 */ "IDB_OBM14_MAX_USAGE_1", 36341 /* IDB_OBM14_MAX_USAGE_1_PIPE0 */ "IDB_OBM14_MAX_USAGE_1_PIPE0", 36342 /* IDB_OBM14_MAX_USAGE_1_PIPE1 */ "IDB_OBM14_MAX_USAGE_1_PIPE1", 36343 /* IDB_OBM14_MAX_USAGE_1_PIPE2 */ "IDB_OBM14_MAX_USAGE_1_PIPE2", 36344 /* IDB_OBM14_MAX_USAGE_1_PIPE3 */ "IDB_OBM14_MAX_USAGE_1_PIPE3", 36345 /* IDB_OBM14_MAX_USAGE_PIPE0 */ "IDB_OBM14_MAX_USAGE_PIPE0", 36346 /* IDB_OBM14_MAX_USAGE_PIPE1 */ "IDB_OBM14_MAX_USAGE_PIPE1", 36347 /* IDB_OBM14_MAX_USAGE_PIPE2 */ "IDB_OBM14_MAX_USAGE_PIPE2", 36348 /* IDB_OBM14_MAX_USAGE_PIPE3 */ "IDB_OBM14_MAX_USAGE_PIPE3", 36349 /* IDB_OBM14_MAX_USAGE_SELECT */ "", 36350 /* IDB_OBM14_MAX_USAGE_SELECT_PIPE0 */ "", 36351 /* IDB_OBM14_MAX_USAGE_SELECT_PIPE1 */ "", 36352 /* IDB_OBM14_MAX_USAGE_SELECT_PIPE2 */ "", 36353 /* IDB_OBM14_MAX_USAGE_SELECT_PIPE3 */ "", 36354 /* IDB_OBM14_NIV_ETHERTYPE */ "", 36355 /* IDB_OBM14_NIV_ETHERTYPE_PIPE0 */ "", 36356 /* IDB_OBM14_NIV_ETHERTYPE_PIPE1 */ "", 36357 /* IDB_OBM14_NIV_ETHERTYPE_PIPE2 */ "", 36358 /* IDB_OBM14_NIV_ETHERTYPE_PIPE3 */ "", 36359 /* IDB_OBM14_OUTER_TPID */ "", 36360 /* IDB_OBM14_OUTER_TPID_0 */ "", 36361 /* IDB_OBM14_OUTER_TPID_1 */ "", 36362 /* IDB_OBM14_OUTER_TPID_2 */ "", 36363 /* IDB_OBM14_OUTER_TPID_3 */ "", 36364 /* IDB_OBM14_OUTER_TPID_0_PIPE0 */ "", 36365 /* IDB_OBM14_OUTER_TPID_0_PIPE1 */ "", 36366 /* IDB_OBM14_OUTER_TPID_0_PIPE2 */ "", 36367 /* IDB_OBM14_OUTER_TPID_0_PIPE3 */ "", 36368 /* IDB_OBM14_OUTER_TPID_1_PIPE0 */ "", 36369 /* IDB_OBM14_OUTER_TPID_1_PIPE1 */ "", 36370 /* IDB_OBM14_OUTER_TPID_1_PIPE2 */ "", 36371 /* IDB_OBM14_OUTER_TPID_1_PIPE3 */ "", 36372 /* IDB_OBM14_OUTER_TPID_2_PIPE0 */ "", 36373 /* IDB_OBM14_OUTER_TPID_2_PIPE1 */ "", 36374 /* IDB_OBM14_OUTER_TPID_2_PIPE2 */ "", 36375 /* IDB_OBM14_OUTER_TPID_2_PIPE3 */ "", 36376 /* IDB_OBM14_OUTER_TPID_3_PIPE0 */ "", 36377 /* IDB_OBM14_OUTER_TPID_3_PIPE1 */ "", 36378 /* IDB_OBM14_OUTER_TPID_3_PIPE2 */ "", 36379 /* IDB_OBM14_OUTER_TPID_3_PIPE3 */ "", 36380 /* IDB_OBM14_OUTER_TPID_PIPE0 */ "", 36381 /* IDB_OBM14_OUTER_TPID_PIPE1 */ "", 36382 /* IDB_OBM14_OUTER_TPID_PIPE2 */ "", 36383 /* IDB_OBM14_OUTER_TPID_PIPE3 */ "", 36384 /* IDB_OBM14_OVERSUB_MON_ECC_STATUS */ "IDB_OBM14_OVERSUB_MON_ECC_STATUS", 36385 /* IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE0", 36386 /* IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE1", 36387 /* IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE2", 36388 /* IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM14_OVERSUB_MON_ECC_STATUS_PIPE3", 36389 /* IDB_OBM14_PE_ETHERTYPE */ "", 36390 /* IDB_OBM14_PE_ETHERTYPE_PIPE0 */ "", 36391 /* IDB_OBM14_PE_ETHERTYPE_PIPE1 */ "", 36392 /* IDB_OBM14_PE_ETHERTYPE_PIPE2 */ "", 36393 /* IDB_OBM14_PE_ETHERTYPE_PIPE3 */ "", 36394 /* IDB_OBM14_PORT_CONFIG */ "", 36395 /* IDB_OBM14_PORT_CONFIG_PIPE0 */ "", 36396 /* IDB_OBM14_PORT_CONFIG_PIPE1 */ "", 36397 /* IDB_OBM14_PORT_CONFIG_PIPE2 */ "", 36398 /* IDB_OBM14_PORT_CONFIG_PIPE3 */ "", 36399 /* IDB_OBM14_PROTOCOL_CONTROL_0 */ "", 36400 /* IDB_OBM14_PROTOCOL_CONTROL_1 */ "", 36401 /* IDB_OBM14_PROTOCOL_CONTROL_2 */ "", 36402 /* IDB_OBM14_PROTOCOL_CONTROL_0_PIPE0 */ "", 36403 /* IDB_OBM14_PROTOCOL_CONTROL_0_PIPE1 */ "", 36404 /* IDB_OBM14_PROTOCOL_CONTROL_0_PIPE2 */ "", 36405 /* IDB_OBM14_PROTOCOL_CONTROL_0_PIPE3 */ "", 36406 /* IDB_OBM14_PROTOCOL_CONTROL_1_PIPE0 */ "", 36407 /* IDB_OBM14_PROTOCOL_CONTROL_1_PIPE1 */ "", 36408 /* IDB_OBM14_PROTOCOL_CONTROL_1_PIPE2 */ "", 36409 /* IDB_OBM14_PROTOCOL_CONTROL_1_PIPE3 */ "", 36410 /* IDB_OBM14_PROTOCOL_CONTROL_2_PIPE0 */ "", 36411 /* IDB_OBM14_PROTOCOL_CONTROL_2_PIPE1 */ "", 36412 /* IDB_OBM14_PROTOCOL_CONTROL_2_PIPE2 */ "", 36413 /* IDB_OBM14_PROTOCOL_CONTROL_2_PIPE3 */ "", 36414 /* IDB_OBM14_QUEUE_ECC_STATUS */ "IDB_OBM14_QUEUE_ECC_STATUS", 36415 /* IDB_OBM14_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM14_QUEUE_ECC_STATUS_PIPE0", 36416 /* IDB_OBM14_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM14_QUEUE_ECC_STATUS_PIPE1", 36417 /* IDB_OBM14_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM14_QUEUE_ECC_STATUS_PIPE2", 36418 /* IDB_OBM14_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM14_QUEUE_ECC_STATUS_PIPE3", 36419 /* IDB_OBM14_RAM_CONTROL */ "IDB_OBM14_RAM_CONTROL", 36420 /* IDB_OBM14_RAM_CONTROL_PIPE0 */ "IDB_OBM14_RAM_CONTROL_PIPE0", 36421 /* IDB_OBM14_RAM_CONTROL_PIPE1 */ "IDB_OBM14_RAM_CONTROL_PIPE1", 36422 /* IDB_OBM14_RAM_CONTROL_PIPE2 */ "IDB_OBM14_RAM_CONTROL_PIPE2", 36423 /* IDB_OBM14_RAM_CONTROL_PIPE3 */ "IDB_OBM14_RAM_CONTROL_PIPE3", 36424 /* IDB_OBM14_SER_CONTROL */ "IDB_OBM14_SER_CONTROL", 36425 /* IDB_OBM14_SER_CONTROL_PIPE0 */ "IDB_OBM14_SER_CONTROL_PIPE0", 36426 /* IDB_OBM14_SER_CONTROL_PIPE1 */ "IDB_OBM14_SER_CONTROL_PIPE1", 36427 /* IDB_OBM14_SHARED_CONFIG */ "IDB_OBM14_SHARED_CONFIG", 36428 /* IDB_OBM14_SHARED_CONFIG_PIPE0 */ "IDB_OBM14_SHARED_CONFIG_PIPE0", 36429 /* IDB_OBM14_SHARED_CONFIG_PIPE1 */ "IDB_OBM14_SHARED_CONFIG_PIPE1", 36430 /* IDB_OBM14_SHARED_CONFIG_PIPE2 */ "IDB_OBM14_SHARED_CONFIG_PIPE2", 36431 /* IDB_OBM14_SHARED_CONFIG_PIPE3 */ "IDB_OBM14_SHARED_CONFIG_PIPE3", 36432 /* IDB_OBM14_SHARED_USAGE */ "IDB_OBM14_SHARED_USAGE", 36433 /* IDB_OBM14_SHARED_USAGE_PIPE0 */ "IDB_OBM14_SHARED_USAGE_PIPE0", 36434 /* IDB_OBM14_SHARED_USAGE_PIPE1 */ "IDB_OBM14_SHARED_USAGE_PIPE1", 36435 /* IDB_OBM14_SHARED_USAGE_PIPE2 */ "IDB_OBM14_SHARED_USAGE_PIPE2", 36436 /* IDB_OBM14_SHARED_USAGE_PIPE3 */ "IDB_OBM14_SHARED_USAGE_PIPE3", 36437 /* IDB_OBM14_THRESHOLD */ "", 36438 /* IDB_OBM14_THRESHOLD_1 */ "", 36439 /* IDB_OBM14_THRESHOLD_1_PIPE0 */ "", 36440 /* IDB_OBM14_THRESHOLD_1_PIPE1 */ "", 36441 /* IDB_OBM14_THRESHOLD_1_PIPE2 */ "", 36442 /* IDB_OBM14_THRESHOLD_1_PIPE3 */ "", 36443 /* IDB_OBM14_THRESHOLD_PIPE0 */ "", 36444 /* IDB_OBM14_THRESHOLD_PIPE1 */ "", 36445 /* IDB_OBM14_THRESHOLD_PIPE2 */ "", 36446 /* IDB_OBM14_THRESHOLD_PIPE3 */ "", 36447 /* IDB_OBM14_USAGE */ "", 36448 /* IDB_OBM14_USAGE_PIPE0 */ "", 36449 /* IDB_OBM14_USAGE_PIPE1 */ "", 36450 /* IDB_OBM14_USAGE_PIPE2 */ "", 36451 /* IDB_OBM14_USAGE_PIPE3 */ "", 36452 /* IDB_OBM15_BANK_CONFIG */ "IDB_OBM15_BANK_CONFIG", 36453 /* IDB_OBM15_BANK_CONFIG_PIPE0 */ "IDB_OBM15_BANK_CONFIG_PIPE0", 36454 /* IDB_OBM15_BANK_CONFIG_PIPE1 */ "IDB_OBM15_BANK_CONFIG_PIPE1", 36455 /* IDB_OBM15_BANK_CONFIG_PIPE2 */ "IDB_OBM15_BANK_CONFIG_PIPE2", 36456 /* IDB_OBM15_BANK_CONFIG_PIPE3 */ "IDB_OBM15_BANK_CONFIG_PIPE3", 36457 /* IDB_OBM15_BUFFER_CONFIG */ "", 36458 /* IDB_OBM15_BUFFER_CONFIG_PIPE0 */ "", 36459 /* IDB_OBM15_BUFFER_CONFIG_PIPE1 */ "", 36460 /* IDB_OBM15_CA_CONTROL */ "IDB_OBM15_CA_CONTROL", 36461 /* IDB_OBM15_CA_CONTROL_PIPE0 */ "IDB_OBM15_CA_CONTROL_PIPE0", 36462 /* IDB_OBM15_CA_CONTROL_PIPE1 */ "IDB_OBM15_CA_CONTROL_PIPE1", 36463 /* IDB_OBM15_CA_CONTROL_PIPE2 */ "IDB_OBM15_CA_CONTROL_PIPE2", 36464 /* IDB_OBM15_CA_CONTROL_PIPE3 */ "IDB_OBM15_CA_CONTROL_PIPE3", 36465 /* IDB_OBM15_CA_CT_CONTROL */ "IDB_OBM15_CA_CT_CONTROL", 36466 /* IDB_OBM15_CA_CT_CONTROL_PIPE0 */ "IDB_OBM15_CA_CT_CONTROL_PIPE0", 36467 /* IDB_OBM15_CA_CT_CONTROL_PIPE1 */ "IDB_OBM15_CA_CT_CONTROL_PIPE1", 36468 /* IDB_OBM15_CA_CT_CONTROL_PIPE2 */ "IDB_OBM15_CA_CT_CONTROL_PIPE2", 36469 /* IDB_OBM15_CA_CT_CONTROL_PIPE3 */ "IDB_OBM15_CA_CT_CONTROL_PIPE3", 36470 /* IDB_OBM15_CA_ECC_STATUS */ "IDB_OBM15_CA_ECC_STATUS", 36471 /* IDB_OBM15_CA_ECC_STATUS_PIPE0 */ "IDB_OBM15_CA_ECC_STATUS_PIPE0", 36472 /* IDB_OBM15_CA_ECC_STATUS_PIPE1 */ "IDB_OBM15_CA_ECC_STATUS_PIPE1", 36473 /* IDB_OBM15_CA_ECC_STATUS_PIPE2 */ "IDB_OBM15_CA_ECC_STATUS_PIPE2", 36474 /* IDB_OBM15_CA_ECC_STATUS_PIPE3 */ "IDB_OBM15_CA_ECC_STATUS_PIPE3", 36475 /* IDB_OBM15_CA_HW_STATUS */ "IDB_OBM15_CA_HW_STATUS", 36476 /* IDB_OBM15_CA_HW_STATUS_PIPE0 */ "IDB_OBM15_CA_HW_STATUS_PIPE0", 36477 /* IDB_OBM15_CA_HW_STATUS_PIPE1 */ "IDB_OBM15_CA_HW_STATUS_PIPE1", 36478 /* IDB_OBM15_CA_HW_STATUS_PIPE2 */ "IDB_OBM15_CA_HW_STATUS_PIPE2", 36479 /* IDB_OBM15_CA_HW_STATUS_PIPE3 */ "IDB_OBM15_CA_HW_STATUS_PIPE3", 36480 /* IDB_OBM15_CA_POINTER_STATUS */ "IDB_OBM15_CA_POINTER_STATUS", 36481 /* IDB_OBM15_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM15_CA_POINTER_STATUS_PIPE0", 36482 /* IDB_OBM15_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM15_CA_POINTER_STATUS_PIPE1", 36483 /* IDB_OBM15_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM15_CA_POINTER_STATUS_PIPE2", 36484 /* IDB_OBM15_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM15_CA_POINTER_STATUS_PIPE3", 36485 /* IDB_OBM15_CONTROL */ "IDB_OBM15_CONTROL", 36486 /* IDB_OBM15_CONTROL_PIPE0 */ "IDB_OBM15_CONTROL_PIPE0", 36487 /* IDB_OBM15_CONTROL_PIPE1 */ "IDB_OBM15_CONTROL_PIPE1", 36488 /* IDB_OBM15_CONTROL_PIPE2 */ "IDB_OBM15_CONTROL_PIPE2", 36489 /* IDB_OBM15_CONTROL_PIPE3 */ "IDB_OBM15_CONTROL_PIPE3", 36490 /* IDB_OBM15_CT_THRESHOLD */ "", 36491 /* IDB_OBM15_CT_THRESHOLD_PIPE0 */ "", 36492 /* IDB_OBM15_CT_THRESHOLD_PIPE1 */ "", 36493 /* IDB_OBM15_CT_THRESHOLD_PIPE2 */ "", 36494 /* IDB_OBM15_CT_THRESHOLD_PIPE3 */ "", 36495 /* IDB_OBM15_DATA_ECC_STATUS */ "IDB_OBM15_DATA_ECC_STATUS", 36496 /* IDB_OBM15_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM15_DATA_ECC_STATUS_PIPE0", 36497 /* IDB_OBM15_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM15_DATA_ECC_STATUS_PIPE1", 36498 /* IDB_OBM15_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM15_DATA_ECC_STATUS_PIPE2", 36499 /* IDB_OBM15_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM15_DATA_ECC_STATUS_PIPE3", 36500 /* IDB_OBM15_DBG_A */ "IDB_OBM15_FORCE_SAF_CONFIG", 36501 /* IDB_OBM15_DBG_A_PIPE0 */ "IDB_OBM15_FORCE_SAF_CONFIG_PIPE0", 36502 /* IDB_OBM15_DBG_A_PIPE1 */ "IDB_OBM15_FORCE_SAF_CONFIG_PIPE1", 36503 /* IDB_OBM15_DBG_A_PIPE2 */ "IDB_OBM15_FORCE_SAF_CONFIG_PIPE2", 36504 /* IDB_OBM15_DBG_A_PIPE3 */ "IDB_OBM15_FORCE_SAF_CONFIG_PIPE3", 36505 /* IDB_OBM15_FC_THRESHOLD */ "", 36506 /* IDB_OBM15_FC_THRESHOLD_1 */ "", 36507 /* IDB_OBM15_FC_THRESHOLD_1_PIPE0 */ "", 36508 /* IDB_OBM15_FC_THRESHOLD_1_PIPE1 */ "", 36509 /* IDB_OBM15_FC_THRESHOLD_1_PIPE2 */ "", 36510 /* IDB_OBM15_FC_THRESHOLD_1_PIPE3 */ "", 36511 /* IDB_OBM15_FC_THRESHOLD_PIPE0 */ "", 36512 /* IDB_OBM15_FC_THRESHOLD_PIPE1 */ "", 36513 /* IDB_OBM15_FC_THRESHOLD_PIPE2 */ "", 36514 /* IDB_OBM15_FC_THRESHOLD_PIPE3 */ "", 36515 /* IDB_OBM15_FLOW_CONTROL_CONFIG */ "", 36516 /* IDB_OBM15_FLOW_CONTROL_CONFIG_PIPE0 */ "", 36517 /* IDB_OBM15_FLOW_CONTROL_CONFIG_PIPE1 */ "", 36518 /* IDB_OBM15_FLOW_CONTROL_CONFIG_PIPE2 */ "", 36519 /* IDB_OBM15_FLOW_CONTROL_CONFIG_PIPE3 */ "", 36520 /* IDB_OBM15_FLOW_CONTROL_EVENT_COUNT */ "", 36521 /* IDB_OBM15_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 36522 /* IDB_OBM15_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 36523 /* IDB_OBM15_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 36524 /* IDB_OBM15_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 36525 /* IDB_OBM15_FORCE_SAF_STATUS */ "", 36526 /* IDB_OBM15_FORCE_SAF_STATUS_PIPE0 */ "", 36527 /* IDB_OBM15_FORCE_SAF_STATUS_PIPE1 */ "", 36528 /* IDB_OBM15_INNER_TPID */ "", 36529 /* IDB_OBM15_INNER_TPID_PIPE0 */ "", 36530 /* IDB_OBM15_INNER_TPID_PIPE1 */ "", 36531 /* IDB_OBM15_INNER_TPID_PIPE2 */ "", 36532 /* IDB_OBM15_INNER_TPID_PIPE3 */ "", 36533 /* IDB_OBM15_LOSSLESS0_BYTE_DROP_COUNT */ "", 36534 /* IDB_OBM15_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 36535 /* IDB_OBM15_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 36536 /* IDB_OBM15_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 36537 /* IDB_OBM15_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 36538 /* IDB_OBM15_LOSSLESS0_PKT_DROP_COUNT */ "", 36539 /* IDB_OBM15_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 36540 /* IDB_OBM15_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 36541 /* IDB_OBM15_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 36542 /* IDB_OBM15_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 36543 /* IDB_OBM15_LOSSLESS1_BYTE_DROP_COUNT */ "", 36544 /* IDB_OBM15_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 36545 /* IDB_OBM15_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 36546 /* IDB_OBM15_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 36547 /* IDB_OBM15_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 36548 /* IDB_OBM15_LOSSLESS1_PKT_DROP_COUNT */ "", 36549 /* IDB_OBM15_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 36550 /* IDB_OBM15_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 36551 /* IDB_OBM15_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 36552 /* IDB_OBM15_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 36553 /* IDB_OBM15_LOSSY_HI_BYTE_DROP_COUNT */ "", 36554 /* IDB_OBM15_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 36555 /* IDB_OBM15_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 36556 /* IDB_OBM15_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 36557 /* IDB_OBM15_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 36558 /* IDB_OBM15_LOSSY_HI_PKT_DROP_COUNT */ "", 36559 /* IDB_OBM15_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 36560 /* IDB_OBM15_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 36561 /* IDB_OBM15_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 36562 /* IDB_OBM15_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 36563 /* IDB_OBM15_LOSSY_LO_BYTE_DROP_COUNT */ "", 36564 /* IDB_OBM15_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 36565 /* IDB_OBM15_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 36566 /* IDB_OBM15_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 36567 /* IDB_OBM15_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 36568 /* IDB_OBM15_LOSSY_LO_PKT_DROP_COUNT */ "", 36569 /* IDB_OBM15_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 36570 /* IDB_OBM15_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 36571 /* IDB_OBM15_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 36572 /* IDB_OBM15_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 36573 /* IDB_OBM15_MAX_USAGE */ "IDB_OBM15_MAX_USAGE", 36574 /* IDB_OBM15_MAX_USAGE_1 */ "IDB_OBM15_MAX_USAGE_1", 36575 /* IDB_OBM15_MAX_USAGE_1_PIPE0 */ "IDB_OBM15_MAX_USAGE_1_PIPE0", 36576 /* IDB_OBM15_MAX_USAGE_1_PIPE1 */ "IDB_OBM15_MAX_USAGE_1_PIPE1", 36577 /* IDB_OBM15_MAX_USAGE_1_PIPE2 */ "IDB_OBM15_MAX_USAGE_1_PIPE2", 36578 /* IDB_OBM15_MAX_USAGE_1_PIPE3 */ "IDB_OBM15_MAX_USAGE_1_PIPE3", 36579 /* IDB_OBM15_MAX_USAGE_PIPE0 */ "IDB_OBM15_MAX_USAGE_PIPE0", 36580 /* IDB_OBM15_MAX_USAGE_PIPE1 */ "IDB_OBM15_MAX_USAGE_PIPE1", 36581 /* IDB_OBM15_MAX_USAGE_PIPE2 */ "IDB_OBM15_MAX_USAGE_PIPE2", 36582 /* IDB_OBM15_MAX_USAGE_PIPE3 */ "IDB_OBM15_MAX_USAGE_PIPE3", 36583 /* IDB_OBM15_MAX_USAGE_SELECT */ "", 36584 /* IDB_OBM15_MAX_USAGE_SELECT_PIPE0 */ "", 36585 /* IDB_OBM15_MAX_USAGE_SELECT_PIPE1 */ "", 36586 /* IDB_OBM15_MAX_USAGE_SELECT_PIPE2 */ "", 36587 /* IDB_OBM15_MAX_USAGE_SELECT_PIPE3 */ "", 36588 /* IDB_OBM15_NIV_ETHERTYPE */ "", 36589 /* IDB_OBM15_NIV_ETHERTYPE_PIPE0 */ "", 36590 /* IDB_OBM15_NIV_ETHERTYPE_PIPE1 */ "", 36591 /* IDB_OBM15_NIV_ETHERTYPE_PIPE2 */ "", 36592 /* IDB_OBM15_NIV_ETHERTYPE_PIPE3 */ "", 36593 /* IDB_OBM15_OUTER_TPID */ "", 36594 /* IDB_OBM15_OUTER_TPID_0 */ "", 36595 /* IDB_OBM15_OUTER_TPID_1 */ "", 36596 /* IDB_OBM15_OUTER_TPID_2 */ "", 36597 /* IDB_OBM15_OUTER_TPID_3 */ "", 36598 /* IDB_OBM15_OUTER_TPID_0_PIPE0 */ "", 36599 /* IDB_OBM15_OUTER_TPID_0_PIPE1 */ "", 36600 /* IDB_OBM15_OUTER_TPID_0_PIPE2 */ "", 36601 /* IDB_OBM15_OUTER_TPID_0_PIPE3 */ "", 36602 /* IDB_OBM15_OUTER_TPID_1_PIPE0 */ "", 36603 /* IDB_OBM15_OUTER_TPID_1_PIPE1 */ "", 36604 /* IDB_OBM15_OUTER_TPID_1_PIPE2 */ "", 36605 /* IDB_OBM15_OUTER_TPID_1_PIPE3 */ "", 36606 /* IDB_OBM15_OUTER_TPID_2_PIPE0 */ "", 36607 /* IDB_OBM15_OUTER_TPID_2_PIPE1 */ "", 36608 /* IDB_OBM15_OUTER_TPID_2_PIPE2 */ "", 36609 /* IDB_OBM15_OUTER_TPID_2_PIPE3 */ "", 36610 /* IDB_OBM15_OUTER_TPID_3_PIPE0 */ "", 36611 /* IDB_OBM15_OUTER_TPID_3_PIPE1 */ "", 36612 /* IDB_OBM15_OUTER_TPID_3_PIPE2 */ "", 36613 /* IDB_OBM15_OUTER_TPID_3_PIPE3 */ "", 36614 /* IDB_OBM15_OUTER_TPID_PIPE0 */ "", 36615 /* IDB_OBM15_OUTER_TPID_PIPE1 */ "", 36616 /* IDB_OBM15_OUTER_TPID_PIPE2 */ "", 36617 /* IDB_OBM15_OUTER_TPID_PIPE3 */ "", 36618 /* IDB_OBM15_OVERSUB_MON_ECC_STATUS */ "IDB_OBM15_OVERSUB_MON_ECC_STATUS", 36619 /* IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE0", 36620 /* IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE1", 36621 /* IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE2", 36622 /* IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM15_OVERSUB_MON_ECC_STATUS_PIPE3", 36623 /* IDB_OBM15_PE_ETHERTYPE */ "", 36624 /* IDB_OBM15_PE_ETHERTYPE_PIPE0 */ "", 36625 /* IDB_OBM15_PE_ETHERTYPE_PIPE1 */ "", 36626 /* IDB_OBM15_PE_ETHERTYPE_PIPE2 */ "", 36627 /* IDB_OBM15_PE_ETHERTYPE_PIPE3 */ "", 36628 /* IDB_OBM15_PORT_CONFIG */ "", 36629 /* IDB_OBM15_PORT_CONFIG_PIPE0 */ "", 36630 /* IDB_OBM15_PORT_CONFIG_PIPE1 */ "", 36631 /* IDB_OBM15_PORT_CONFIG_PIPE2 */ "", 36632 /* IDB_OBM15_PORT_CONFIG_PIPE3 */ "", 36633 /* IDB_OBM15_PROTOCOL_CONTROL_0 */ "", 36634 /* IDB_OBM15_PROTOCOL_CONTROL_1 */ "", 36635 /* IDB_OBM15_PROTOCOL_CONTROL_2 */ "", 36636 /* IDB_OBM15_PROTOCOL_CONTROL_0_PIPE0 */ "", 36637 /* IDB_OBM15_PROTOCOL_CONTROL_0_PIPE1 */ "", 36638 /* IDB_OBM15_PROTOCOL_CONTROL_0_PIPE2 */ "", 36639 /* IDB_OBM15_PROTOCOL_CONTROL_0_PIPE3 */ "", 36640 /* IDB_OBM15_PROTOCOL_CONTROL_1_PIPE0 */ "", 36641 /* IDB_OBM15_PROTOCOL_CONTROL_1_PIPE1 */ "", 36642 /* IDB_OBM15_PROTOCOL_CONTROL_1_PIPE2 */ "", 36643 /* IDB_OBM15_PROTOCOL_CONTROL_1_PIPE3 */ "", 36644 /* IDB_OBM15_PROTOCOL_CONTROL_2_PIPE0 */ "", 36645 /* IDB_OBM15_PROTOCOL_CONTROL_2_PIPE1 */ "", 36646 /* IDB_OBM15_PROTOCOL_CONTROL_2_PIPE2 */ "", 36647 /* IDB_OBM15_PROTOCOL_CONTROL_2_PIPE3 */ "", 36648 /* IDB_OBM15_QUEUE_ECC_STATUS */ "IDB_OBM15_QUEUE_ECC_STATUS", 36649 /* IDB_OBM15_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM15_QUEUE_ECC_STATUS_PIPE0", 36650 /* IDB_OBM15_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM15_QUEUE_ECC_STATUS_PIPE1", 36651 /* IDB_OBM15_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM15_QUEUE_ECC_STATUS_PIPE2", 36652 /* IDB_OBM15_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM15_QUEUE_ECC_STATUS_PIPE3", 36653 /* IDB_OBM15_RAM_CONTROL */ "IDB_OBM15_RAM_CONTROL", 36654 /* IDB_OBM15_RAM_CONTROL_PIPE0 */ "IDB_OBM15_RAM_CONTROL_PIPE0", 36655 /* IDB_OBM15_RAM_CONTROL_PIPE1 */ "IDB_OBM15_RAM_CONTROL_PIPE1", 36656 /* IDB_OBM15_RAM_CONTROL_PIPE2 */ "IDB_OBM15_RAM_CONTROL_PIPE2", 36657 /* IDB_OBM15_RAM_CONTROL_PIPE3 */ "IDB_OBM15_RAM_CONTROL_PIPE3", 36658 /* IDB_OBM15_SER_CONTROL */ "IDB_OBM15_SER_CONTROL", 36659 /* IDB_OBM15_SER_CONTROL_PIPE0 */ "IDB_OBM15_SER_CONTROL_PIPE0", 36660 /* IDB_OBM15_SER_CONTROL_PIPE1 */ "IDB_OBM15_SER_CONTROL_PIPE1", 36661 /* IDB_OBM15_SHARED_CONFIG */ "IDB_OBM15_SHARED_CONFIG", 36662 /* IDB_OBM15_SHARED_CONFIG_PIPE0 */ "IDB_OBM15_SHARED_CONFIG_PIPE0", 36663 /* IDB_OBM15_SHARED_CONFIG_PIPE1 */ "IDB_OBM15_SHARED_CONFIG_PIPE1", 36664 /* IDB_OBM15_SHARED_CONFIG_PIPE2 */ "IDB_OBM15_SHARED_CONFIG_PIPE2", 36665 /* IDB_OBM15_SHARED_CONFIG_PIPE3 */ "IDB_OBM15_SHARED_CONFIG_PIPE3", 36666 /* IDB_OBM15_SHARED_USAGE */ "IDB_OBM15_SHARED_USAGE", 36667 /* IDB_OBM15_SHARED_USAGE_PIPE0 */ "IDB_OBM15_SHARED_USAGE_PIPE0", 36668 /* IDB_OBM15_SHARED_USAGE_PIPE1 */ "IDB_OBM15_SHARED_USAGE_PIPE1", 36669 /* IDB_OBM15_SHARED_USAGE_PIPE2 */ "IDB_OBM15_SHARED_USAGE_PIPE2", 36670 /* IDB_OBM15_SHARED_USAGE_PIPE3 */ "IDB_OBM15_SHARED_USAGE_PIPE3", 36671 /* IDB_OBM15_THRESHOLD */ "", 36672 /* IDB_OBM15_THRESHOLD_1 */ "", 36673 /* IDB_OBM15_THRESHOLD_1_PIPE0 */ "", 36674 /* IDB_OBM15_THRESHOLD_1_PIPE1 */ "", 36675 /* IDB_OBM15_THRESHOLD_1_PIPE2 */ "", 36676 /* IDB_OBM15_THRESHOLD_1_PIPE3 */ "", 36677 /* IDB_OBM15_THRESHOLD_PIPE0 */ "", 36678 /* IDB_OBM15_THRESHOLD_PIPE1 */ "", 36679 /* IDB_OBM15_THRESHOLD_PIPE2 */ "", 36680 /* IDB_OBM15_THRESHOLD_PIPE3 */ "", 36681 /* IDB_OBM15_USAGE */ "", 36682 /* IDB_OBM15_USAGE_PIPE0 */ "", 36683 /* IDB_OBM15_USAGE_PIPE1 */ "", 36684 /* IDB_OBM15_USAGE_PIPE2 */ "", 36685 /* IDB_OBM15_USAGE_PIPE3 */ "", 36686 /* IDB_OBM16_BANK_CONFIG */ "IDB_OBM16_BANK_CONFIG", 36687 /* IDB_OBM16_BANK_CONFIG_PIPE0 */ "IDB_OBM16_BANK_CONFIG_PIPE0", 36688 /* IDB_OBM16_BUFFER_CONFIG */ "", 36689 /* IDB_OBM16_BUFFER_CONFIG_PIPE0 */ "", 36690 /* IDB_OBM16_CA_CONTROL */ "IDB_OBM16_CA_CONTROL", 36691 /* IDB_OBM16_CA_CONTROL_PIPE0 */ "IDB_OBM16_CA_CONTROL_PIPE0", 36692 /* IDB_OBM16_CA_CT_CONTROL */ "IDB_OBM16_CA_CT_CONTROL", 36693 /* IDB_OBM16_CA_CT_CONTROL_PIPE0 */ "IDB_OBM16_CA_CT_CONTROL_PIPE0", 36694 /* IDB_OBM16_CA_ECC_STATUS */ "IDB_OBM16_CA_ECC_STATUS", 36695 /* IDB_OBM16_CA_ECC_STATUS_PIPE0 */ "IDB_OBM16_CA_ECC_STATUS_PIPE0", 36696 /* IDB_OBM16_CA_HW_STATUS */ "IDB_OBM16_CA_HW_STATUS", 36697 /* IDB_OBM16_CA_HW_STATUS_PIPE0 */ "IDB_OBM16_CA_HW_STATUS_PIPE0", 36698 /* IDB_OBM16_CA_POINTER_STATUS */ "IDB_OBM16_CA_POINTER_STATUS", 36699 /* IDB_OBM16_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM16_CA_POINTER_STATUS_PIPE0", 36700 /* IDB_OBM16_CONTROL */ "IDB_OBM16_CONTROL", 36701 /* IDB_OBM16_CONTROL_PIPE0 */ "IDB_OBM16_CONTROL_PIPE0", 36702 /* IDB_OBM16_CT_THRESHOLD */ "", 36703 /* IDB_OBM16_CT_THRESHOLD_PIPE0 */ "", 36704 /* IDB_OBM16_DATA_ECC_STATUS */ "IDB_OBM16_DATA_ECC_STATUS", 36705 /* IDB_OBM16_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM16_DATA_ECC_STATUS_PIPE0", 36706 /* IDB_OBM16_DBG_A */ "IDB_OBM16_FORCE_SAF_CONFIG", 36707 /* IDB_OBM16_DBG_A_PIPE0 */ "IDB_OBM16_FORCE_SAF_CONFIG_PIPE0", 36708 /* IDB_OBM16_FC_THRESHOLD */ "", 36709 /* IDB_OBM16_FC_THRESHOLD_1 */ "", 36710 /* IDB_OBM16_FC_THRESHOLD_1_PIPE0 */ "", 36711 /* IDB_OBM16_FC_THRESHOLD_PIPE0 */ "", 36712 /* IDB_OBM16_FLOW_CONTROL_CONFIG */ "", 36713 /* IDB_OBM16_FLOW_CONTROL_CONFIG_PIPE0 */ "", 36714 /* IDB_OBM16_FLOW_CONTROL_EVENT_COUNT */ "", 36715 /* IDB_OBM16_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 36716 /* IDB_OBM16_FORCE_SAF_STATUS */ "", 36717 /* IDB_OBM16_FORCE_SAF_STATUS_PIPE0 */ "", 36718 /* IDB_OBM16_INNER_TPID */ "", 36719 /* IDB_OBM16_INNER_TPID_PIPE0 */ "", 36720 /* IDB_OBM16_LOSSLESS0_BYTE_DROP_COUNT */ "", 36721 /* IDB_OBM16_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 36722 /* IDB_OBM16_LOSSLESS0_PKT_DROP_COUNT */ "", 36723 /* IDB_OBM16_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 36724 /* IDB_OBM16_LOSSLESS1_BYTE_DROP_COUNT */ "", 36725 /* IDB_OBM16_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 36726 /* IDB_OBM16_LOSSLESS1_PKT_DROP_COUNT */ "", 36727 /* IDB_OBM16_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 36728 /* IDB_OBM16_LOSSY_HI_BYTE_DROP_COUNT */ "", 36729 /* IDB_OBM16_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 36730 /* IDB_OBM16_LOSSY_HI_PKT_DROP_COUNT */ "", 36731 /* IDB_OBM16_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 36732 /* IDB_OBM16_LOSSY_LO_BYTE_DROP_COUNT */ "", 36733 /* IDB_OBM16_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 36734 /* IDB_OBM16_LOSSY_LO_PKT_DROP_COUNT */ "", 36735 /* IDB_OBM16_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 36736 /* IDB_OBM16_MAX_USAGE */ "IDB_OBM16_MAX_USAGE", 36737 /* IDB_OBM16_MAX_USAGE_PIPE0 */ "IDB_OBM16_MAX_USAGE_PIPE0", 36738 /* IDB_OBM16_MAX_USAGE_SELECT */ "", 36739 /* IDB_OBM16_MAX_USAGE_SELECT_PIPE0 */ "", 36740 /* IDB_OBM16_NIV_ETHERTYPE */ "", 36741 /* IDB_OBM16_NIV_ETHERTYPE_PIPE0 */ "", 36742 /* IDB_OBM16_OUTER_TPID */ "", 36743 /* IDB_OBM16_OUTER_TPID_0 */ "", 36744 /* IDB_OBM16_OUTER_TPID_1 */ "", 36745 /* IDB_OBM16_OUTER_TPID_2 */ "", 36746 /* IDB_OBM16_OUTER_TPID_3 */ "", 36747 /* IDB_OBM16_OUTER_TPID_0_PIPE0 */ "", 36748 /* IDB_OBM16_OUTER_TPID_1_PIPE0 */ "", 36749 /* IDB_OBM16_OUTER_TPID_2_PIPE0 */ "", 36750 /* IDB_OBM16_OUTER_TPID_3_PIPE0 */ "", 36751 /* IDB_OBM16_OUTER_TPID_PIPE0 */ "", 36752 /* IDB_OBM16_OVERSUB_MON_ECC_STATUS */ "IDB_OBM16_OVERSUB_MON_ECC_STATUS", 36753 /* IDB_OBM16_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM16_OVERSUB_MON_ECC_STATUS_PIPE0", 36754 /* IDB_OBM16_PE_ETHERTYPE */ "", 36755 /* IDB_OBM16_PE_ETHERTYPE_PIPE0 */ "", 36756 /* IDB_OBM16_PORT_CONFIG */ "", 36757 /* IDB_OBM16_PORT_CONFIG_PIPE0 */ "", 36758 /* IDB_OBM16_PROTOCOL_CONTROL_0 */ "", 36759 /* IDB_OBM16_PROTOCOL_CONTROL_1 */ "", 36760 /* IDB_OBM16_PROTOCOL_CONTROL_2 */ "", 36761 /* IDB_OBM16_PROTOCOL_CONTROL_0_PIPE0 */ "", 36762 /* IDB_OBM16_PROTOCOL_CONTROL_1_PIPE0 */ "", 36763 /* IDB_OBM16_PROTOCOL_CONTROL_2_PIPE0 */ "", 36764 /* IDB_OBM16_RAM_CONTROL */ "IDB_OBM16_RAM_CONTROL", 36765 /* IDB_OBM16_RAM_CONTROL_PIPE0 */ "IDB_OBM16_RAM_CONTROL_PIPE0", 36766 /* IDB_OBM16_SER_CONTROL */ "IDB_OBM16_SER_CONTROL", 36767 /* IDB_OBM16_SER_CONTROL_PIPE0 */ "IDB_OBM16_SER_CONTROL_PIPE0", 36768 /* IDB_OBM16_SHARED_CONFIG */ "IDB_OBM16_SHARED_CONFIG", 36769 /* IDB_OBM16_SHARED_CONFIG_PIPE0 */ "IDB_OBM16_SHARED_CONFIG_PIPE0", 36770 /* IDB_OBM16_THRESHOLD */ "", 36771 /* IDB_OBM16_THRESHOLD_1 */ "", 36772 /* IDB_OBM16_THRESHOLD_1_PIPE0 */ "", 36773 /* IDB_OBM16_THRESHOLD_PIPE0 */ "", 36774 /* IDB_OBM16_USAGE */ "", 36775 /* IDB_OBM16_USAGE_PIPE0 */ "", 36776 /* IDB_OBM17_BANK_CONFIG */ "IDB_OBM17_BANK_CONFIG", 36777 /* IDB_OBM17_BANK_CONFIG_PIPE0 */ "IDB_OBM17_BANK_CONFIG_PIPE0", 36778 /* IDB_OBM17_BUFFER_CONFIG */ "", 36779 /* IDB_OBM17_BUFFER_CONFIG_PIPE0 */ "", 36780 /* IDB_OBM17_CA_CONTROL */ "IDB_OBM17_CA_CONTROL", 36781 /* IDB_OBM17_CA_CONTROL_PIPE0 */ "IDB_OBM17_CA_CONTROL_PIPE0", 36782 /* IDB_OBM17_CA_CT_CONTROL */ "IDB_OBM17_CA_CT_CONTROL", 36783 /* IDB_OBM17_CA_CT_CONTROL_PIPE0 */ "IDB_OBM17_CA_CT_CONTROL_PIPE0", 36784 /* IDB_OBM17_CA_ECC_STATUS */ "IDB_OBM17_CA_ECC_STATUS", 36785 /* IDB_OBM17_CA_ECC_STATUS_PIPE0 */ "IDB_OBM17_CA_ECC_STATUS_PIPE0", 36786 /* IDB_OBM17_CA_HW_STATUS */ "IDB_OBM17_CA_HW_STATUS", 36787 /* IDB_OBM17_CA_HW_STATUS_PIPE0 */ "IDB_OBM17_CA_HW_STATUS_PIPE0", 36788 /* IDB_OBM17_CA_POINTER_STATUS */ "IDB_OBM17_CA_POINTER_STATUS", 36789 /* IDB_OBM17_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM17_CA_POINTER_STATUS_PIPE0", 36790 /* IDB_OBM17_CONTROL */ "IDB_OBM17_CONTROL", 36791 /* IDB_OBM17_CONTROL_PIPE0 */ "IDB_OBM17_CONTROL_PIPE0", 36792 /* IDB_OBM17_CT_THRESHOLD */ "", 36793 /* IDB_OBM17_CT_THRESHOLD_PIPE0 */ "", 36794 /* IDB_OBM17_DATA_ECC_STATUS */ "IDB_OBM17_DATA_ECC_STATUS", 36795 /* IDB_OBM17_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM17_DATA_ECC_STATUS_PIPE0", 36796 /* IDB_OBM17_DBG_A */ "IDB_OBM17_FORCE_SAF_CONFIG", 36797 /* IDB_OBM17_DBG_A_PIPE0 */ "IDB_OBM17_FORCE_SAF_CONFIG_PIPE0", 36798 /* IDB_OBM17_FC_THRESHOLD */ "", 36799 /* IDB_OBM17_FC_THRESHOLD_1 */ "", 36800 /* IDB_OBM17_FC_THRESHOLD_1_PIPE0 */ "", 36801 /* IDB_OBM17_FC_THRESHOLD_PIPE0 */ "", 36802 /* IDB_OBM17_FLOW_CONTROL_CONFIG */ "", 36803 /* IDB_OBM17_FLOW_CONTROL_CONFIG_PIPE0 */ "", 36804 /* IDB_OBM17_FLOW_CONTROL_EVENT_COUNT */ "", 36805 /* IDB_OBM17_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 36806 /* IDB_OBM17_FORCE_SAF_STATUS */ "", 36807 /* IDB_OBM17_FORCE_SAF_STATUS_PIPE0 */ "", 36808 /* IDB_OBM17_INNER_TPID */ "", 36809 /* IDB_OBM17_INNER_TPID_PIPE0 */ "", 36810 /* IDB_OBM17_LOSSLESS0_BYTE_DROP_COUNT */ "", 36811 /* IDB_OBM17_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 36812 /* IDB_OBM17_LOSSLESS0_PKT_DROP_COUNT */ "", 36813 /* IDB_OBM17_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 36814 /* IDB_OBM17_LOSSLESS1_BYTE_DROP_COUNT */ "", 36815 /* IDB_OBM17_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 36816 /* IDB_OBM17_LOSSLESS1_PKT_DROP_COUNT */ "", 36817 /* IDB_OBM17_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 36818 /* IDB_OBM17_LOSSY_HI_BYTE_DROP_COUNT */ "", 36819 /* IDB_OBM17_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 36820 /* IDB_OBM17_LOSSY_HI_PKT_DROP_COUNT */ "", 36821 /* IDB_OBM17_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 36822 /* IDB_OBM17_LOSSY_LO_BYTE_DROP_COUNT */ "", 36823 /* IDB_OBM17_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 36824 /* IDB_OBM17_LOSSY_LO_PKT_DROP_COUNT */ "", 36825 /* IDB_OBM17_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 36826 /* IDB_OBM17_MAX_USAGE */ "IDB_OBM17_MAX_USAGE", 36827 /* IDB_OBM17_MAX_USAGE_PIPE0 */ "IDB_OBM17_MAX_USAGE_PIPE0", 36828 /* IDB_OBM17_MAX_USAGE_SELECT */ "", 36829 /* IDB_OBM17_MAX_USAGE_SELECT_PIPE0 */ "", 36830 /* IDB_OBM17_NIV_ETHERTYPE */ "", 36831 /* IDB_OBM17_NIV_ETHERTYPE_PIPE0 */ "", 36832 /* IDB_OBM17_OUTER_TPID */ "", 36833 /* IDB_OBM17_OUTER_TPID_0 */ "", 36834 /* IDB_OBM17_OUTER_TPID_1 */ "", 36835 /* IDB_OBM17_OUTER_TPID_2 */ "", 36836 /* IDB_OBM17_OUTER_TPID_3 */ "", 36837 /* IDB_OBM17_OUTER_TPID_0_PIPE0 */ "", 36838 /* IDB_OBM17_OUTER_TPID_1_PIPE0 */ "", 36839 /* IDB_OBM17_OUTER_TPID_2_PIPE0 */ "", 36840 /* IDB_OBM17_OUTER_TPID_3_PIPE0 */ "", 36841 /* IDB_OBM17_OUTER_TPID_PIPE0 */ "", 36842 /* IDB_OBM17_OVERSUB_MON_ECC_STATUS */ "IDB_OBM17_OVERSUB_MON_ECC_STATUS", 36843 /* IDB_OBM17_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM17_OVERSUB_MON_ECC_STATUS_PIPE0", 36844 /* IDB_OBM17_PE_ETHERTYPE */ "", 36845 /* IDB_OBM17_PE_ETHERTYPE_PIPE0 */ "", 36846 /* IDB_OBM17_PORT_CONFIG */ "", 36847 /* IDB_OBM17_PORT_CONFIG_PIPE0 */ "", 36848 /* IDB_OBM17_PROTOCOL_CONTROL_0 */ "", 36849 /* IDB_OBM17_PROTOCOL_CONTROL_1 */ "", 36850 /* IDB_OBM17_PROTOCOL_CONTROL_2 */ "", 36851 /* IDB_OBM17_PROTOCOL_CONTROL_0_PIPE0 */ "", 36852 /* IDB_OBM17_PROTOCOL_CONTROL_1_PIPE0 */ "", 36853 /* IDB_OBM17_PROTOCOL_CONTROL_2_PIPE0 */ "", 36854 /* IDB_OBM17_RAM_CONTROL */ "IDB_OBM17_RAM_CONTROL", 36855 /* IDB_OBM17_RAM_CONTROL_PIPE0 */ "IDB_OBM17_RAM_CONTROL_PIPE0", 36856 /* IDB_OBM17_SER_CONTROL */ "IDB_OBM17_SER_CONTROL", 36857 /* IDB_OBM17_SER_CONTROL_PIPE0 */ "IDB_OBM17_SER_CONTROL_PIPE0", 36858 /* IDB_OBM17_SHARED_CONFIG */ "IDB_OBM17_SHARED_CONFIG", 36859 /* IDB_OBM17_SHARED_CONFIG_PIPE0 */ "IDB_OBM17_SHARED_CONFIG_PIPE0", 36860 /* IDB_OBM17_THRESHOLD */ "", 36861 /* IDB_OBM17_THRESHOLD_1 */ "", 36862 /* IDB_OBM17_THRESHOLD_1_PIPE0 */ "", 36863 /* IDB_OBM17_THRESHOLD_PIPE0 */ "", 36864 /* IDB_OBM17_USAGE */ "", 36865 /* IDB_OBM17_USAGE_PIPE0 */ "", 36866 /* IDB_OBM18_BANK_CONFIG */ "IDB_OBM18_BANK_CONFIG", 36867 /* IDB_OBM18_BANK_CONFIG_PIPE0 */ "IDB_OBM18_BANK_CONFIG_PIPE0", 36868 /* IDB_OBM18_BUFFER_CONFIG */ "", 36869 /* IDB_OBM18_BUFFER_CONFIG_PIPE0 */ "", 36870 /* IDB_OBM18_CA_CONTROL */ "IDB_OBM18_CA_CONTROL", 36871 /* IDB_OBM18_CA_CONTROL_PIPE0 */ "IDB_OBM18_CA_CONTROL_PIPE0", 36872 /* IDB_OBM18_CA_CT_CONTROL */ "IDB_OBM18_CA_CT_CONTROL", 36873 /* IDB_OBM18_CA_CT_CONTROL_PIPE0 */ "IDB_OBM18_CA_CT_CONTROL_PIPE0", 36874 /* IDB_OBM18_CA_ECC_STATUS */ "IDB_OBM18_CA_ECC_STATUS", 36875 /* IDB_OBM18_CA_ECC_STATUS_PIPE0 */ "IDB_OBM18_CA_ECC_STATUS_PIPE0", 36876 /* IDB_OBM18_CA_HW_STATUS */ "IDB_OBM18_CA_HW_STATUS", 36877 /* IDB_OBM18_CA_HW_STATUS_PIPE0 */ "IDB_OBM18_CA_HW_STATUS_PIPE0", 36878 /* IDB_OBM18_CA_POINTER_STATUS */ "IDB_OBM18_CA_POINTER_STATUS", 36879 /* IDB_OBM18_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM18_CA_POINTER_STATUS_PIPE0", 36880 /* IDB_OBM18_CONTROL */ "IDB_OBM18_CONTROL", 36881 /* IDB_OBM18_CONTROL_PIPE0 */ "IDB_OBM18_CONTROL_PIPE0", 36882 /* IDB_OBM18_CT_THRESHOLD */ "", 36883 /* IDB_OBM18_CT_THRESHOLD_PIPE0 */ "", 36884 /* IDB_OBM18_DATA_ECC_STATUS */ "IDB_OBM18_DATA_ECC_STATUS", 36885 /* IDB_OBM18_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM18_DATA_ECC_STATUS_PIPE0", 36886 /* IDB_OBM18_DBG_A */ "IDB_OBM18_FORCE_SAF_CONFIG", 36887 /* IDB_OBM18_DBG_A_PIPE0 */ "IDB_OBM18_FORCE_SAF_CONFIG_PIPE0", 36888 /* IDB_OBM18_FC_THRESHOLD */ "", 36889 /* IDB_OBM18_FC_THRESHOLD_1 */ "", 36890 /* IDB_OBM18_FC_THRESHOLD_1_PIPE0 */ "", 36891 /* IDB_OBM18_FC_THRESHOLD_PIPE0 */ "", 36892 /* IDB_OBM18_FLOW_CONTROL_CONFIG */ "", 36893 /* IDB_OBM18_FLOW_CONTROL_CONFIG_PIPE0 */ "", 36894 /* IDB_OBM18_FLOW_CONTROL_EVENT_COUNT */ "", 36895 /* IDB_OBM18_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 36896 /* IDB_OBM18_FORCE_SAF_STATUS */ "", 36897 /* IDB_OBM18_FORCE_SAF_STATUS_PIPE0 */ "", 36898 /* IDB_OBM18_INNER_TPID */ "", 36899 /* IDB_OBM18_INNER_TPID_PIPE0 */ "", 36900 /* IDB_OBM18_LOSSLESS0_BYTE_DROP_COUNT */ "", 36901 /* IDB_OBM18_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 36902 /* IDB_OBM18_LOSSLESS0_PKT_DROP_COUNT */ "", 36903 /* IDB_OBM18_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 36904 /* IDB_OBM18_LOSSLESS1_BYTE_DROP_COUNT */ "", 36905 /* IDB_OBM18_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 36906 /* IDB_OBM18_LOSSLESS1_PKT_DROP_COUNT */ "", 36907 /* IDB_OBM18_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 36908 /* IDB_OBM18_LOSSY_HI_BYTE_DROP_COUNT */ "", 36909 /* IDB_OBM18_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 36910 /* IDB_OBM18_LOSSY_HI_PKT_DROP_COUNT */ "", 36911 /* IDB_OBM18_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 36912 /* IDB_OBM18_LOSSY_LO_BYTE_DROP_COUNT */ "", 36913 /* IDB_OBM18_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 36914 /* IDB_OBM18_LOSSY_LO_PKT_DROP_COUNT */ "", 36915 /* IDB_OBM18_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 36916 /* IDB_OBM18_MAX_USAGE */ "IDB_OBM18_MAX_USAGE", 36917 /* IDB_OBM18_MAX_USAGE_PIPE0 */ "IDB_OBM18_MAX_USAGE_PIPE0", 36918 /* IDB_OBM18_MAX_USAGE_SELECT */ "", 36919 /* IDB_OBM18_MAX_USAGE_SELECT_PIPE0 */ "", 36920 /* IDB_OBM18_NIV_ETHERTYPE */ "", 36921 /* IDB_OBM18_NIV_ETHERTYPE_PIPE0 */ "", 36922 /* IDB_OBM18_OUTER_TPID */ "", 36923 /* IDB_OBM18_OUTER_TPID_0 */ "", 36924 /* IDB_OBM18_OUTER_TPID_1 */ "", 36925 /* IDB_OBM18_OUTER_TPID_2 */ "", 36926 /* IDB_OBM18_OUTER_TPID_3 */ "", 36927 /* IDB_OBM18_OUTER_TPID_0_PIPE0 */ "", 36928 /* IDB_OBM18_OUTER_TPID_1_PIPE0 */ "", 36929 /* IDB_OBM18_OUTER_TPID_2_PIPE0 */ "", 36930 /* IDB_OBM18_OUTER_TPID_3_PIPE0 */ "", 36931 /* IDB_OBM18_OUTER_TPID_PIPE0 */ "", 36932 /* IDB_OBM18_OVERSUB_MON_ECC_STATUS */ "IDB_OBM18_OVERSUB_MON_ECC_STATUS", 36933 /* IDB_OBM18_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM18_OVERSUB_MON_ECC_STATUS_PIPE0", 36934 /* IDB_OBM18_PE_ETHERTYPE */ "", 36935 /* IDB_OBM18_PE_ETHERTYPE_PIPE0 */ "", 36936 /* IDB_OBM18_PORT_CONFIG */ "", 36937 /* IDB_OBM18_PORT_CONFIG_PIPE0 */ "", 36938 /* IDB_OBM18_PROTOCOL_CONTROL_0 */ "", 36939 /* IDB_OBM18_PROTOCOL_CONTROL_1 */ "", 36940 /* IDB_OBM18_PROTOCOL_CONTROL_2 */ "", 36941 /* IDB_OBM18_PROTOCOL_CONTROL_0_PIPE0 */ "", 36942 /* IDB_OBM18_PROTOCOL_CONTROL_1_PIPE0 */ "", 36943 /* IDB_OBM18_PROTOCOL_CONTROL_2_PIPE0 */ "", 36944 /* IDB_OBM18_RAM_CONTROL */ "IDB_OBM18_RAM_CONTROL", 36945 /* IDB_OBM18_RAM_CONTROL_PIPE0 */ "IDB_OBM18_RAM_CONTROL_PIPE0", 36946 /* IDB_OBM18_SER_CONTROL */ "IDB_OBM18_SER_CONTROL", 36947 /* IDB_OBM18_SER_CONTROL_PIPE0 */ "IDB_OBM18_SER_CONTROL_PIPE0", 36948 /* IDB_OBM18_SHARED_CONFIG */ "IDB_OBM18_SHARED_CONFIG", 36949 /* IDB_OBM18_SHARED_CONFIG_PIPE0 */ "IDB_OBM18_SHARED_CONFIG_PIPE0", 36950 /* IDB_OBM18_THRESHOLD */ "", 36951 /* IDB_OBM18_THRESHOLD_1 */ "", 36952 /* IDB_OBM18_THRESHOLD_1_PIPE0 */ "", 36953 /* IDB_OBM18_THRESHOLD_PIPE0 */ "", 36954 /* IDB_OBM18_USAGE */ "", 36955 /* IDB_OBM18_USAGE_PIPE0 */ "", 36956 /* IDB_OBM19_BANK_CONFIG */ "IDB_OBM19_BANK_CONFIG", 36957 /* IDB_OBM19_BANK_CONFIG_PIPE0 */ "IDB_OBM19_BANK_CONFIG_PIPE0", 36958 /* IDB_OBM19_BUFFER_CONFIG */ "", 36959 /* IDB_OBM19_BUFFER_CONFIG_PIPE0 */ "", 36960 /* IDB_OBM19_CA_CONTROL */ "IDB_OBM19_CA_CONTROL", 36961 /* IDB_OBM19_CA_CONTROL_PIPE0 */ "IDB_OBM19_CA_CONTROL_PIPE0", 36962 /* IDB_OBM19_CA_CT_CONTROL */ "IDB_OBM19_CA_CT_CONTROL", 36963 /* IDB_OBM19_CA_CT_CONTROL_PIPE0 */ "IDB_OBM19_CA_CT_CONTROL_PIPE0", 36964 /* IDB_OBM19_CA_ECC_STATUS */ "IDB_OBM19_CA_ECC_STATUS", 36965 /* IDB_OBM19_CA_ECC_STATUS_PIPE0 */ "IDB_OBM19_CA_ECC_STATUS_PIPE0", 36966 /* IDB_OBM19_CA_HW_STATUS */ "IDB_OBM19_CA_HW_STATUS", 36967 /* IDB_OBM19_CA_HW_STATUS_PIPE0 */ "IDB_OBM19_CA_HW_STATUS_PIPE0", 36968 /* IDB_OBM19_CA_POINTER_STATUS */ "IDB_OBM19_CA_POINTER_STATUS", 36969 /* IDB_OBM19_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM19_CA_POINTER_STATUS_PIPE0", 36970 /* IDB_OBM19_CONTROL */ "IDB_OBM19_CONTROL", 36971 /* IDB_OBM19_CONTROL_PIPE0 */ "IDB_OBM19_CONTROL_PIPE0", 36972 /* IDB_OBM19_CT_THRESHOLD */ "", 36973 /* IDB_OBM19_CT_THRESHOLD_PIPE0 */ "", 36974 /* IDB_OBM19_DATA_ECC_STATUS */ "IDB_OBM19_DATA_ECC_STATUS", 36975 /* IDB_OBM19_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM19_DATA_ECC_STATUS_PIPE0", 36976 /* IDB_OBM19_DBG_A */ "IDB_OBM19_FORCE_SAF_CONFIG", 36977 /* IDB_OBM19_DBG_A_PIPE0 */ "IDB_OBM19_FORCE_SAF_CONFIG_PIPE0", 36978 /* IDB_OBM19_FC_THRESHOLD */ "", 36979 /* IDB_OBM19_FC_THRESHOLD_1 */ "", 36980 /* IDB_OBM19_FC_THRESHOLD_1_PIPE0 */ "", 36981 /* IDB_OBM19_FC_THRESHOLD_PIPE0 */ "", 36982 /* IDB_OBM19_FLOW_CONTROL_CONFIG */ "", 36983 /* IDB_OBM19_FLOW_CONTROL_CONFIG_PIPE0 */ "", 36984 /* IDB_OBM19_FLOW_CONTROL_EVENT_COUNT */ "", 36985 /* IDB_OBM19_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 36986 /* IDB_OBM19_FORCE_SAF_STATUS */ "", 36987 /* IDB_OBM19_FORCE_SAF_STATUS_PIPE0 */ "", 36988 /* IDB_OBM19_INNER_TPID */ "", 36989 /* IDB_OBM19_INNER_TPID_PIPE0 */ "", 36990 /* IDB_OBM19_LOSSLESS0_BYTE_DROP_COUNT */ "", 36991 /* IDB_OBM19_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 36992 /* IDB_OBM19_LOSSLESS0_PKT_DROP_COUNT */ "", 36993 /* IDB_OBM19_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 36994 /* IDB_OBM19_LOSSLESS1_BYTE_DROP_COUNT */ "", 36995 /* IDB_OBM19_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 36996 /* IDB_OBM19_LOSSLESS1_PKT_DROP_COUNT */ "", 36997 /* IDB_OBM19_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 36998 /* IDB_OBM19_LOSSY_HI_BYTE_DROP_COUNT */ "", 36999 /* IDB_OBM19_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 37000 /* IDB_OBM19_LOSSY_HI_PKT_DROP_COUNT */ "", 37001 /* IDB_OBM19_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 37002 /* IDB_OBM19_LOSSY_LO_BYTE_DROP_COUNT */ "", 37003 /* IDB_OBM19_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 37004 /* IDB_OBM19_LOSSY_LO_PKT_DROP_COUNT */ "", 37005 /* IDB_OBM19_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 37006 /* IDB_OBM19_MAX_USAGE */ "IDB_OBM19_MAX_USAGE", 37007 /* IDB_OBM19_MAX_USAGE_PIPE0 */ "IDB_OBM19_MAX_USAGE_PIPE0", 37008 /* IDB_OBM19_MAX_USAGE_SELECT */ "", 37009 /* IDB_OBM19_MAX_USAGE_SELECT_PIPE0 */ "", 37010 /* IDB_OBM19_NIV_ETHERTYPE */ "", 37011 /* IDB_OBM19_NIV_ETHERTYPE_PIPE0 */ "", 37012 /* IDB_OBM19_OUTER_TPID */ "", 37013 /* IDB_OBM19_OUTER_TPID_0 */ "", 37014 /* IDB_OBM19_OUTER_TPID_1 */ "", 37015 /* IDB_OBM19_OUTER_TPID_2 */ "", 37016 /* IDB_OBM19_OUTER_TPID_3 */ "", 37017 /* IDB_OBM19_OUTER_TPID_0_PIPE0 */ "", 37018 /* IDB_OBM19_OUTER_TPID_1_PIPE0 */ "", 37019 /* IDB_OBM19_OUTER_TPID_2_PIPE0 */ "", 37020 /* IDB_OBM19_OUTER_TPID_3_PIPE0 */ "", 37021 /* IDB_OBM19_OUTER_TPID_PIPE0 */ "", 37022 /* IDB_OBM19_OVERSUB_MON_ECC_STATUS */ "IDB_OBM19_OVERSUB_MON_ECC_STATUS", 37023 /* IDB_OBM19_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM19_OVERSUB_MON_ECC_STATUS_PIPE0", 37024 /* IDB_OBM19_PE_ETHERTYPE */ "", 37025 /* IDB_OBM19_PE_ETHERTYPE_PIPE0 */ "", 37026 /* IDB_OBM19_PORT_CONFIG */ "", 37027 /* IDB_OBM19_PORT_CONFIG_PIPE0 */ "", 37028 /* IDB_OBM19_PROTOCOL_CONTROL_0 */ "", 37029 /* IDB_OBM19_PROTOCOL_CONTROL_1 */ "", 37030 /* IDB_OBM19_PROTOCOL_CONTROL_2 */ "", 37031 /* IDB_OBM19_PROTOCOL_CONTROL_0_PIPE0 */ "", 37032 /* IDB_OBM19_PROTOCOL_CONTROL_1_PIPE0 */ "", 37033 /* IDB_OBM19_PROTOCOL_CONTROL_2_PIPE0 */ "", 37034 /* IDB_OBM19_RAM_CONTROL */ "IDB_OBM19_RAM_CONTROL", 37035 /* IDB_OBM19_RAM_CONTROL_PIPE0 */ "IDB_OBM19_RAM_CONTROL_PIPE0", 37036 /* IDB_OBM19_SER_CONTROL */ "IDB_OBM19_SER_CONTROL", 37037 /* IDB_OBM19_SER_CONTROL_PIPE0 */ "IDB_OBM19_SER_CONTROL_PIPE0", 37038 /* IDB_OBM19_SHARED_CONFIG */ "IDB_OBM19_SHARED_CONFIG", 37039 /* IDB_OBM19_SHARED_CONFIG_PIPE0 */ "IDB_OBM19_SHARED_CONFIG_PIPE0", 37040 /* IDB_OBM19_THRESHOLD */ "", 37041 /* IDB_OBM19_THRESHOLD_1 */ "", 37042 /* IDB_OBM19_THRESHOLD_1_PIPE0 */ "", 37043 /* IDB_OBM19_THRESHOLD_PIPE0 */ "", 37044 /* IDB_OBM19_USAGE */ "", 37045 /* IDB_OBM19_USAGE_PIPE0 */ "", 37046 /* IDB_OBM1_48_BANK_CONFIG */ "IDB_OBM1_48_BANK_CONFIG", 37047 /* IDB_OBM1_48_BANK_CONFIG_PIPE0 */ "IDB_OBM1_48_BANK_CONFIG_PIPE0", 37048 /* IDB_OBM1_48_BUFFER_CONFIG */ "", 37049 /* IDB_OBM1_48_BUFFER_CONFIG_PIPE0 */ "", 37050 /* IDB_OBM1_48_CA_CONTROL */ "IDB_OBM1_48_CA_CONTROL", 37051 /* IDB_OBM1_48_CA_CONTROL_PIPE0 */ "IDB_OBM1_48_CA_CONTROL_PIPE0", 37052 /* IDB_OBM1_48_CA_ECC_STATUS */ "IDB_OBM1_48_CA_ECC_STATUS", 37053 /* IDB_OBM1_48_CA_ECC_STATUS_PIPE0 */ "IDB_OBM1_48_CA_ECC_STATUS_PIPE0", 37054 /* IDB_OBM1_48_CA_HW_STATUS */ "IDB_OBM1_48_CA_HW_STATUS", 37055 /* IDB_OBM1_48_CA_HW_STATUS_PIPE0 */ "IDB_OBM1_48_CA_HW_STATUS_PIPE0", 37056 /* IDB_OBM1_48_CA_POINTER_STATUS */ "IDB_OBM1_48_CA_POINTER_STATUS", 37057 /* IDB_OBM1_48_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM1_48_CA_POINTER_STATUS_PIPE0", 37058 /* IDB_OBM1_48_CONTROL */ "IDB_OBM1_48_CONTROL", 37059 /* IDB_OBM1_48_CONTROL_PIPE0 */ "IDB_OBM1_48_CONTROL_PIPE0", 37060 /* IDB_OBM1_48_DATA_ECC_STATUS */ "IDB_OBM1_48_DATA_ECC_STATUS", 37061 /* IDB_OBM1_48_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM1_48_DATA_ECC_STATUS_PIPE0", 37062 /* IDB_OBM1_48_FC_THRESHOLD */ "", 37063 /* IDB_OBM1_48_FC_THRESHOLD_1 */ "", 37064 /* IDB_OBM1_48_FC_THRESHOLD_1_PIPE0 */ "", 37065 /* IDB_OBM1_48_FC_THRESHOLD_PIPE0 */ "", 37066 /* IDB_OBM1_48_FLOW_CONTROL_CONFIG */ "", 37067 /* IDB_OBM1_48_FLOW_CONTROL_CONFIG_PIPE0 */ "", 37068 /* IDB_OBM1_48_FLOW_CONTROL_EVENT_COUNT */ "", 37069 /* IDB_OBM1_48_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 37070 /* IDB_OBM1_48_INNER_TPID */ "", 37071 /* IDB_OBM1_48_INNER_TPID_PIPE0 */ "", 37072 /* IDB_OBM1_48_LOSSLESS0_BYTE_DROP_COUNT */ "", 37073 /* IDB_OBM1_48_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 37074 /* IDB_OBM1_48_LOSSLESS0_PKT_DROP_COUNT */ "", 37075 /* IDB_OBM1_48_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 37076 /* IDB_OBM1_48_LOSSLESS1_BYTE_DROP_COUNT */ "", 37077 /* IDB_OBM1_48_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 37078 /* IDB_OBM1_48_LOSSLESS1_PKT_DROP_COUNT */ "", 37079 /* IDB_OBM1_48_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 37080 /* IDB_OBM1_48_LOSSY_HI_BYTE_DROP_COUNT */ "", 37081 /* IDB_OBM1_48_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 37082 /* IDB_OBM1_48_LOSSY_HI_PKT_DROP_COUNT */ "", 37083 /* IDB_OBM1_48_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 37084 /* IDB_OBM1_48_LOSSY_LO_BYTE_DROP_COUNT */ "", 37085 /* IDB_OBM1_48_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 37086 /* IDB_OBM1_48_LOSSY_LO_PKT_DROP_COUNT */ "", 37087 /* IDB_OBM1_48_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 37088 /* IDB_OBM1_48_MAX_USAGE */ "IDB_OBM1_48_MAX_USAGE", 37089 /* IDB_OBM1_48_MAX_USAGE_PIPE0 */ "IDB_OBM1_48_MAX_USAGE_PIPE0", 37090 /* IDB_OBM1_48_MAX_USAGE_SELECT */ "", 37091 /* IDB_OBM1_48_MAX_USAGE_SELECT_PIPE0 */ "", 37092 /* IDB_OBM1_48_NIV_ETHERTYPE */ "", 37093 /* IDB_OBM1_48_NIV_ETHERTYPE_PIPE0 */ "", 37094 /* IDB_OBM1_48_OUTER_TPID */ "", 37095 /* IDB_OBM1_48_OUTER_TPID_0 */ "", 37096 /* IDB_OBM1_48_OUTER_TPID_1 */ "", 37097 /* IDB_OBM1_48_OUTER_TPID_2 */ "", 37098 /* IDB_OBM1_48_OUTER_TPID_3 */ "", 37099 /* IDB_OBM1_48_OUTER_TPID_0_PIPE0 */ "", 37100 /* IDB_OBM1_48_OUTER_TPID_1_PIPE0 */ "", 37101 /* IDB_OBM1_48_OUTER_TPID_2_PIPE0 */ "", 37102 /* IDB_OBM1_48_OUTER_TPID_3_PIPE0 */ "", 37103 /* IDB_OBM1_48_OUTER_TPID_PIPE0 */ "", 37104 /* IDB_OBM1_48_OVERSUB_MON_ECC_STATUS */ "IDB_OBM1_48_OVERSUB_MON_ECC_STATUS", 37105 /* IDB_OBM1_48_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM1_48_OVERSUB_MON_ECC_STATUS_PIPE0", 37106 /* IDB_OBM1_48_PE_ETHERTYPE */ "", 37107 /* IDB_OBM1_48_PE_ETHERTYPE_PIPE0 */ "", 37108 /* IDB_OBM1_48_PORT_CONFIG */ "", 37109 /* IDB_OBM1_48_PORT_CONFIG_PIPE0 */ "", 37110 /* IDB_OBM1_48_PROTOCOL_CONTROL_0 */ "", 37111 /* IDB_OBM1_48_PROTOCOL_CONTROL_1 */ "", 37112 /* IDB_OBM1_48_PROTOCOL_CONTROL_2 */ "", 37113 /* IDB_OBM1_48_PROTOCOL_CONTROL_0_PIPE0 */ "", 37114 /* IDB_OBM1_48_PROTOCOL_CONTROL_1_PIPE0 */ "", 37115 /* IDB_OBM1_48_PROTOCOL_CONTROL_2_PIPE0 */ "", 37116 /* IDB_OBM1_48_RAM_CONTROL */ "IDB_OBM1_48_RAM_CONTROL", 37117 /* IDB_OBM1_48_RAM_CONTROL_PIPE0 */ "IDB_OBM1_48_RAM_CONTROL_PIPE0", 37118 /* IDB_OBM1_48_SER_CONTROL */ "IDB_OBM1_48_SER_CONTROL", 37119 /* IDB_OBM1_48_SER_CONTROL_PIPE0 */ "IDB_OBM1_48_SER_CONTROL_PIPE0", 37120 /* IDB_OBM1_48_SHARED_CONFIG */ "IDB_OBM1_48_SHARED_CONFIG", 37121 /* IDB_OBM1_48_SHARED_CONFIG_PIPE0 */ "IDB_OBM1_48_SHARED_CONFIG_PIPE0", 37122 /* IDB_OBM1_48_THRESHOLD */ "", 37123 /* IDB_OBM1_48_THRESHOLD_1 */ "", 37124 /* IDB_OBM1_48_THRESHOLD_1_PIPE0 */ "", 37125 /* IDB_OBM1_48_THRESHOLD_PIPE0 */ "", 37126 /* IDB_OBM1_48_USAGE */ "", 37127 /* IDB_OBM1_48_USAGE_PIPE0 */ "", 37128 /* IDB_OBM1_BANK_CONFIG */ "IDB_OBM1_BANK_CONFIG", 37129 /* IDB_OBM1_BANK_CONFIG_PIPE0 */ "IDB_OBM1_BANK_CONFIG_PIPE0", 37130 /* IDB_OBM1_BANK_CONFIG_PIPE1 */ "IDB_OBM1_BANK_CONFIG_PIPE1", 37131 /* IDB_OBM1_BANK_CONFIG_PIPE2 */ "IDB_OBM1_BANK_CONFIG_PIPE2", 37132 /* IDB_OBM1_BANK_CONFIG_PIPE3 */ "IDB_OBM1_BANK_CONFIG_PIPE3", 37133 /* IDB_OBM1_BUCKET_COUNT_CONFIG */ "", 37134 /* IDB_OBM1_BUFFER_CONFIG */ "", 37135 /* IDB_OBM1_BUFFER_CONFIG_PIPE0 */ "", 37136 /* IDB_OBM1_BUFFER_CONFIG_PIPE1 */ "", 37137 /* IDB_OBM1_BUFFER_CONFIG_PIPE2 */ "", 37138 /* IDB_OBM1_BUFFER_CONFIG_PIPE3 */ "", 37139 /* IDB_OBM1_BUFFER_CONFIG_PIPE4 */ "", 37140 /* IDB_OBM1_BUFFER_CONFIG_PIPE5 */ "", 37141 /* IDB_OBM1_BUFFER_CONFIG_PIPE6 */ "", 37142 /* IDB_OBM1_BUFFER_CONFIG_PIPE7 */ "", 37143 /* IDB_OBM1_CA_CONTROL */ "IDB_OBM1_CA_CONTROL", 37144 /* IDB_OBM1_CA_CONTROL_PIPE0 */ "IDB_OBM1_CA_CONTROL_PIPE0", 37145 /* IDB_OBM1_CA_CONTROL_PIPE1 */ "IDB_OBM1_CA_CONTROL_PIPE1", 37146 /* IDB_OBM1_CA_CONTROL_PIPE2 */ "IDB_OBM1_CA_CONTROL_PIPE2", 37147 /* IDB_OBM1_CA_CONTROL_PIPE3 */ "IDB_OBM1_CA_CONTROL_PIPE3", 37148 /* IDB_OBM1_CA_CT_CONTROL */ "IDB_OBM1_CA_CT_CONTROL", 37149 /* IDB_OBM1_CA_CT_CONTROL_PIPE0 */ "IDB_OBM1_CA_CT_CONTROL_PIPE0", 37150 /* IDB_OBM1_CA_CT_CONTROL_PIPE1 */ "IDB_OBM1_CA_CT_CONTROL_PIPE1", 37151 /* IDB_OBM1_CA_CT_CONTROL_PIPE2 */ "IDB_OBM1_CA_CT_CONTROL_PIPE2", 37152 /* IDB_OBM1_CA_CT_CONTROL_PIPE3 */ "IDB_OBM1_CA_CT_CONTROL_PIPE3", 37153 /* IDB_OBM1_CA_ECC_STATUS */ "IDB_OBM1_CA_ECC_STATUS", 37154 /* IDB_OBM1_CA_ECC_STATUS_PIPE0 */ "IDB_OBM1_CA_ECC_STATUS_PIPE0", 37155 /* IDB_OBM1_CA_ECC_STATUS_PIPE1 */ "IDB_OBM1_CA_ECC_STATUS_PIPE1", 37156 /* IDB_OBM1_CA_ECC_STATUS_PIPE2 */ "IDB_OBM1_CA_ECC_STATUS_PIPE2", 37157 /* IDB_OBM1_CA_ECC_STATUS_PIPE3 */ "IDB_OBM1_CA_ECC_STATUS_PIPE3", 37158 /* IDB_OBM1_CA_HW_CONTROL */ "IDB_OBM1_CA_HW_CONTROL", 37159 /* IDB_OBM1_CA_HW_CONTROL_PIPE0 */ "IDB_OBM1_CA_HW_CONTROL_PIPE0", 37160 /* IDB_OBM1_CA_HW_CONTROL_PIPE1 */ "IDB_OBM1_CA_HW_CONTROL_PIPE1", 37161 /* IDB_OBM1_CA_HW_CONTROL_PIPE2 */ "IDB_OBM1_CA_HW_CONTROL_PIPE2", 37162 /* IDB_OBM1_CA_HW_CONTROL_PIPE3 */ "IDB_OBM1_CA_HW_CONTROL_PIPE3", 37163 /* IDB_OBM1_CA_HW_STATUS */ "IDB_OBM1_CA_HW_STATUS", 37164 /* IDB_OBM1_CA_HW_STATUS_PIPE0 */ "IDB_OBM1_CA_HW_STATUS_PIPE0", 37165 /* IDB_OBM1_CA_HW_STATUS_PIPE1 */ "IDB_OBM1_CA_HW_STATUS_PIPE1", 37166 /* IDB_OBM1_CA_HW_STATUS_PIPE2 */ "IDB_OBM1_CA_HW_STATUS_PIPE2", 37167 /* IDB_OBM1_CA_HW_STATUS_PIPE3 */ "IDB_OBM1_CA_HW_STATUS_PIPE3", 37168 /* IDB_OBM1_CA_POINTER_STATUS */ "IDB_OBM1_CA_POINTER_STATUS", 37169 /* IDB_OBM1_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM1_CA_POINTER_STATUS_PIPE0", 37170 /* IDB_OBM1_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM1_CA_POINTER_STATUS_PIPE1", 37171 /* IDB_OBM1_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM1_CA_POINTER_STATUS_PIPE2", 37172 /* IDB_OBM1_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM1_CA_POINTER_STATUS_PIPE3", 37173 /* IDB_OBM1_CONTROL */ "IDB_OBM1_CONTROL", 37174 /* IDB_OBM1_CONTROL_PIPE0 */ "IDB_OBM1_CONTROL_PIPE0", 37175 /* IDB_OBM1_CONTROL_PIPE1 */ "IDB_OBM1_CONTROL_PIPE1", 37176 /* IDB_OBM1_CONTROL_PIPE2 */ "IDB_OBM1_CONTROL_PIPE2", 37177 /* IDB_OBM1_CONTROL_PIPE3 */ "IDB_OBM1_CONTROL_PIPE3", 37178 /* IDB_OBM1_CONTROL_PIPE4 */ "IDB_OBM1_CONTROL_PIPE4", 37179 /* IDB_OBM1_CONTROL_PIPE5 */ "IDB_OBM1_CONTROL_PIPE5", 37180 /* IDB_OBM1_CONTROL_PIPE6 */ "IDB_OBM1_CONTROL_PIPE6", 37181 /* IDB_OBM1_CONTROL_PIPE7 */ "IDB_OBM1_CONTROL_PIPE7", 37182 /* IDB_OBM1_CTRL_ECC_STATUS */ "IDB_OBM1_CTRL_ECC_STATUS", 37183 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE0 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE0", 37184 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE1 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE1", 37185 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE2 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE2", 37186 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE3 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE3", 37187 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE4 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE4", 37188 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE5 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE5", 37189 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE6 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE6", 37190 /* IDB_OBM1_CTRL_ECC_STATUS_PIPE7 */ "IDB_OBM1_CTRL_ECC_STATUS_PIPE7", 37191 /* IDB_OBM1_CT_THRESHOLD */ "", 37192 /* IDB_OBM1_CT_THRESHOLD_PIPE0 */ "", 37193 /* IDB_OBM1_CT_THRESHOLD_PIPE1 */ "", 37194 /* IDB_OBM1_CT_THRESHOLD_PIPE2 */ "", 37195 /* IDB_OBM1_CT_THRESHOLD_PIPE3 */ "", 37196 /* IDB_OBM1_CT_THRESHOLD_PIPE4 */ "", 37197 /* IDB_OBM1_CT_THRESHOLD_PIPE5 */ "", 37198 /* IDB_OBM1_CT_THRESHOLD_PIPE6 */ "", 37199 /* IDB_OBM1_CT_THRESHOLD_PIPE7 */ "", 37200 /* IDB_OBM1_DATA_ECC_STATUS */ "IDB_OBM1_DATA_ECC_STATUS", 37201 /* IDB_OBM1_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE0", 37202 /* IDB_OBM1_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE1", 37203 /* IDB_OBM1_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE2", 37204 /* IDB_OBM1_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE3", 37205 /* IDB_OBM1_DATA_ECC_STATUS_PIPE4 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE4", 37206 /* IDB_OBM1_DATA_ECC_STATUS_PIPE5 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE5", 37207 /* IDB_OBM1_DATA_ECC_STATUS_PIPE6 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE6", 37208 /* IDB_OBM1_DATA_ECC_STATUS_PIPE7 */ "IDB_OBM1_DATA_ECC_STATUS_PIPE7", 37209 /* IDB_OBM1_DBG_A */ "IDB_OBM1_FORCE_SAF_CONFIG", 37210 /* IDB_OBM1_DBG_A_PIPE0 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE0", 37211 /* IDB_OBM1_DBG_A_PIPE1 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE1", 37212 /* IDB_OBM1_DBG_A_PIPE2 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE2", 37213 /* IDB_OBM1_DBG_A_PIPE3 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE3", 37214 /* IDB_OBM1_DBG_A_PIPE4 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE4", 37215 /* IDB_OBM1_DBG_A_PIPE5 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE5", 37216 /* IDB_OBM1_DBG_A_PIPE6 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE6", 37217 /* IDB_OBM1_DBG_A_PIPE7 */ "IDB_OBM1_FORCE_SAF_CONFIG_PIPE7", 37218 /* IDB_OBM1_DBG_B */ "IDB_OBM1_LAG_DETECTION_CONFIG", 37219 /* IDB_OBM1_DBG_B_PIPE0 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE0", 37220 /* IDB_OBM1_DBG_B_PIPE1 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE1", 37221 /* IDB_OBM1_DBG_B_PIPE2 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE2", 37222 /* IDB_OBM1_DBG_B_PIPE3 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE3", 37223 /* IDB_OBM1_DBG_B_PIPE4 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE4", 37224 /* IDB_OBM1_DBG_B_PIPE5 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE5", 37225 /* IDB_OBM1_DBG_B_PIPE6 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE6", 37226 /* IDB_OBM1_DBG_B_PIPE7 */ "IDB_OBM1_LAG_DETECTION_CONFIG_PIPE7", 37227 /* IDB_OBM1_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 37228 /* IDB_OBM1_EXPRESS_ARRIVAL_PKT_COUNT */ "", 37229 /* IDB_OBM1_EXPRESS_BYTE_DROP_COUNT */ "", 37230 /* IDB_OBM1_EXPRESS_FLOW_CONTROL_CONFIG */ "", 37231 /* IDB_OBM1_EXPRESS_PKT_DROP_COUNT */ "", 37232 /* IDB_OBM1_FC_THRESHOLD */ "", 37233 /* IDB_OBM1_FC_THRESHOLD_0 */ "", 37234 /* IDB_OBM1_FC_THRESHOLD_1 */ "", 37235 /* IDB_OBM1_FC_THRESHOLD_1_PIPE0 */ "", 37236 /* IDB_OBM1_FC_THRESHOLD_1_PIPE1 */ "", 37237 /* IDB_OBM1_FC_THRESHOLD_1_PIPE2 */ "", 37238 /* IDB_OBM1_FC_THRESHOLD_1_PIPE3 */ "", 37239 /* IDB_OBM1_FC_THRESHOLD_1_PIPE4 */ "", 37240 /* IDB_OBM1_FC_THRESHOLD_1_PIPE5 */ "", 37241 /* IDB_OBM1_FC_THRESHOLD_1_PIPE6 */ "", 37242 /* IDB_OBM1_FC_THRESHOLD_1_PIPE7 */ "", 37243 /* IDB_OBM1_FC_THRESHOLD_PIPE0 */ "", 37244 /* IDB_OBM1_FC_THRESHOLD_PIPE1 */ "", 37245 /* IDB_OBM1_FC_THRESHOLD_PIPE2 */ "", 37246 /* IDB_OBM1_FC_THRESHOLD_PIPE3 */ "", 37247 /* IDB_OBM1_FC_THRESHOLD_PIPE4 */ "", 37248 /* IDB_OBM1_FC_THRESHOLD_PIPE5 */ "", 37249 /* IDB_OBM1_FC_THRESHOLD_PIPE6 */ "", 37250 /* IDB_OBM1_FC_THRESHOLD_PIPE7 */ "", 37251 /* IDB_OBM1_FLOW_CONTROL_CONFIG */ "", 37252 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE0 */ "", 37253 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE1 */ "", 37254 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE2 */ "", 37255 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE3 */ "", 37256 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE4 */ "", 37257 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE5 */ "", 37258 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE6 */ "", 37259 /* IDB_OBM1_FLOW_CONTROL_CONFIG_PIPE7 */ "", 37260 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT */ "", 37261 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 37262 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 37263 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 37264 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 37265 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE4 */ "", 37266 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE5 */ "", 37267 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE6 */ "", 37268 /* IDB_OBM1_FLOW_CONTROL_EVENT_COUNT_PIPE7 */ "", 37269 /* IDB_OBM1_FORCE_SAF_STATUS */ "", 37270 /* IDB_OBM1_FORCE_SAF_STATUS_PIPE0 */ "", 37271 /* IDB_OBM1_FORCE_SAF_STATUS_PIPE1 */ "", 37272 /* IDB_OBM1_HW_STATUS */ "IDB_OBM1_HW_STATUS", 37273 /* IDB_OBM1_HW_STATUS_PIPE0 */ "IDB_OBM1_HW_STATUS_PIPE0", 37274 /* IDB_OBM1_HW_STATUS_PIPE1 */ "IDB_OBM1_HW_STATUS_PIPE1", 37275 /* IDB_OBM1_HW_STATUS_PIPE2 */ "IDB_OBM1_HW_STATUS_PIPE2", 37276 /* IDB_OBM1_HW_STATUS_PIPE3 */ "IDB_OBM1_HW_STATUS_PIPE3", 37277 /* IDB_OBM1_HW_STATUS_PIPE4 */ "IDB_OBM1_HW_STATUS_PIPE4", 37278 /* IDB_OBM1_HW_STATUS_PIPE5 */ "IDB_OBM1_HW_STATUS_PIPE5", 37279 /* IDB_OBM1_HW_STATUS_PIPE6 */ "IDB_OBM1_HW_STATUS_PIPE6", 37280 /* IDB_OBM1_HW_STATUS_PIPE7 */ "IDB_OBM1_HW_STATUS_PIPE7", 37281 /* IDB_OBM1_INNER_TPID */ "", 37282 /* IDB_OBM1_INNER_TPID_PIPE0 */ "", 37283 /* IDB_OBM1_INNER_TPID_PIPE1 */ "", 37284 /* IDB_OBM1_INNER_TPID_PIPE2 */ "", 37285 /* IDB_OBM1_INNER_TPID_PIPE3 */ "", 37286 /* IDB_OBM1_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 37287 /* IDB_OBM1_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 37288 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT */ "", 37289 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 37290 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 37291 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 37292 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 37293 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE4 */ "", 37294 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE5 */ "", 37295 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE6 */ "", 37296 /* IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNT_PIPE7 */ "", 37297 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT */ "", 37298 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 37299 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 37300 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 37301 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 37302 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE4 */ "", 37303 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE5 */ "", 37304 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE6 */ "", 37305 /* IDB_OBM1_LOSSLESS0_PKT_DROP_COUNT_PIPE7 */ "", 37306 /* IDB_OBM1_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 37307 /* IDB_OBM1_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 37308 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT */ "", 37309 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 37310 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 37311 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 37312 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 37313 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE4 */ "", 37314 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE5 */ "", 37315 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE6 */ "", 37316 /* IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNT_PIPE7 */ "", 37317 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT */ "", 37318 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 37319 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 37320 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 37321 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 37322 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE4 */ "", 37323 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE5 */ "", 37324 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE6 */ "", 37325 /* IDB_OBM1_LOSSLESS1_PKT_DROP_COUNT_PIPE7 */ "", 37326 /* IDB_OBM1_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 37327 /* IDB_OBM1_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 37328 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT */ "", 37329 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 37330 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 37331 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 37332 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 37333 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE4 */ "", 37334 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE5 */ "", 37335 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE6 */ "", 37336 /* IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNT_PIPE7 */ "", 37337 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT */ "", 37338 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 37339 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 37340 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 37341 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 37342 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE4 */ "", 37343 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE5 */ "", 37344 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE6 */ "", 37345 /* IDB_OBM1_LOSSY_HI_PKT_DROP_COUNT_PIPE7 */ "", 37346 /* IDB_OBM1_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 37347 /* IDB_OBM1_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 37348 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT */ "", 37349 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 37350 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 37351 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 37352 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 37353 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE4 */ "", 37354 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE5 */ "", 37355 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE6 */ "", 37356 /* IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNT_PIPE7 */ "", 37357 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT */ "", 37358 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 37359 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 37360 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 37361 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 37362 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE4 */ "", 37363 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE5 */ "", 37364 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE6 */ "", 37365 /* IDB_OBM1_LOSSY_LO_PKT_DROP_COUNT_PIPE7 */ "", 37366 /* IDB_OBM1_MAX_USAGE */ "IDB_OBM1_MAX_USAGE", 37367 /* IDB_OBM1_MAX_USAGE_1 */ "IDB_OBM1_MAX_USAGE_1", 37368 /* IDB_OBM1_MAX_USAGE_2 */ "IDB_OBM1_MAX_USAGE_2", 37369 /* IDB_OBM1_MAX_USAGE_1_PIPE0 */ "IDB_OBM1_MAX_USAGE_1_PIPE0", 37370 /* IDB_OBM1_MAX_USAGE_1_PIPE1 */ "IDB_OBM1_MAX_USAGE_1_PIPE1", 37371 /* IDB_OBM1_MAX_USAGE_1_PIPE2 */ "IDB_OBM1_MAX_USAGE_1_PIPE2", 37372 /* IDB_OBM1_MAX_USAGE_1_PIPE3 */ "IDB_OBM1_MAX_USAGE_1_PIPE3", 37373 /* IDB_OBM1_MAX_USAGE_1_PIPE4 */ "IDB_OBM1_MAX_USAGE_1_PIPE4", 37374 /* IDB_OBM1_MAX_USAGE_1_PIPE5 */ "IDB_OBM1_MAX_USAGE_1_PIPE5", 37375 /* IDB_OBM1_MAX_USAGE_1_PIPE6 */ "IDB_OBM1_MAX_USAGE_1_PIPE6", 37376 /* IDB_OBM1_MAX_USAGE_1_PIPE7 */ "IDB_OBM1_MAX_USAGE_1_PIPE7", 37377 /* IDB_OBM1_MAX_USAGE_2_PIPE0 */ "IDB_OBM1_MAX_USAGE_2_PIPE0", 37378 /* IDB_OBM1_MAX_USAGE_2_PIPE1 */ "IDB_OBM1_MAX_USAGE_2_PIPE1", 37379 /* IDB_OBM1_MAX_USAGE_2_PIPE2 */ "IDB_OBM1_MAX_USAGE_2_PIPE2", 37380 /* IDB_OBM1_MAX_USAGE_2_PIPE3 */ "IDB_OBM1_MAX_USAGE_2_PIPE3", 37381 /* IDB_OBM1_MAX_USAGE_2_PIPE4 */ "IDB_OBM1_MAX_USAGE_2_PIPE4", 37382 /* IDB_OBM1_MAX_USAGE_2_PIPE5 */ "IDB_OBM1_MAX_USAGE_2_PIPE5", 37383 /* IDB_OBM1_MAX_USAGE_2_PIPE6 */ "IDB_OBM1_MAX_USAGE_2_PIPE6", 37384 /* IDB_OBM1_MAX_USAGE_2_PIPE7 */ "IDB_OBM1_MAX_USAGE_2_PIPE7", 37385 /* IDB_OBM1_MAX_USAGE_PIPE0 */ "IDB_OBM1_MAX_USAGE_PIPE0", 37386 /* IDB_OBM1_MAX_USAGE_PIPE1 */ "IDB_OBM1_MAX_USAGE_PIPE1", 37387 /* IDB_OBM1_MAX_USAGE_PIPE2 */ "IDB_OBM1_MAX_USAGE_PIPE2", 37388 /* IDB_OBM1_MAX_USAGE_PIPE3 */ "IDB_OBM1_MAX_USAGE_PIPE3", 37389 /* IDB_OBM1_MAX_USAGE_PIPE4 */ "IDB_OBM1_MAX_USAGE_PIPE4", 37390 /* IDB_OBM1_MAX_USAGE_PIPE5 */ "IDB_OBM1_MAX_USAGE_PIPE5", 37391 /* IDB_OBM1_MAX_USAGE_PIPE6 */ "IDB_OBM1_MAX_USAGE_PIPE6", 37392 /* IDB_OBM1_MAX_USAGE_PIPE7 */ "IDB_OBM1_MAX_USAGE_PIPE7", 37393 /* IDB_OBM1_MAX_USAGE_SELECT */ "", 37394 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE0 */ "", 37395 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE1 */ "", 37396 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE2 */ "", 37397 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE3 */ "", 37398 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE4 */ "", 37399 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE5 */ "", 37400 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE6 */ "", 37401 /* IDB_OBM1_MAX_USAGE_SELECT_PIPE7 */ "", 37402 /* IDB_OBM1_MONITOR_STATS_CONFIG */ "", 37403 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE0 */ "", 37404 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE1 */ "", 37405 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE2 */ "", 37406 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE3 */ "", 37407 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE4 */ "", 37408 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE5 */ "", 37409 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE6 */ "", 37410 /* IDB_OBM1_MONITOR_STATS_CONFIG_PIPE7 */ "", 37411 /* IDB_OBM1_NIV_ETHERTYPE */ "", 37412 /* IDB_OBM1_NIV_ETHERTYPE_PIPE0 */ "", 37413 /* IDB_OBM1_NIV_ETHERTYPE_PIPE1 */ "", 37414 /* IDB_OBM1_NIV_ETHERTYPE_PIPE2 */ "", 37415 /* IDB_OBM1_NIV_ETHERTYPE_PIPE3 */ "", 37416 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0 */ "", 37417 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1 */ "", 37418 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE0 */ "", 37419 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE1 */ "", 37420 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE2 */ "", 37421 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE3 */ "", 37422 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE4 */ "", 37423 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE5 */ "", 37424 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE6 */ "", 37425 /* IDB_OBM1_OPAQUE_TAG_CONFIG_0_PIPE7 */ "", 37426 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE0 */ "", 37427 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE1 */ "", 37428 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE2 */ "", 37429 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE3 */ "", 37430 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE4 */ "", 37431 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE5 */ "", 37432 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE6 */ "", 37433 /* IDB_OBM1_OPAQUE_TAG_CONFIG_1_PIPE7 */ "", 37434 /* IDB_OBM1_OUTER_TPID */ "", 37435 /* IDB_OBM1_OUTER_TPID_0 */ "", 37436 /* IDB_OBM1_OUTER_TPID_1 */ "", 37437 /* IDB_OBM1_OUTER_TPID_2 */ "", 37438 /* IDB_OBM1_OUTER_TPID_3 */ "", 37439 /* IDB_OBM1_OUTER_TPID_0_PIPE0 */ "", 37440 /* IDB_OBM1_OUTER_TPID_0_PIPE1 */ "", 37441 /* IDB_OBM1_OUTER_TPID_0_PIPE2 */ "", 37442 /* IDB_OBM1_OUTER_TPID_0_PIPE3 */ "", 37443 /* IDB_OBM1_OUTER_TPID_0_PIPE4 */ "", 37444 /* IDB_OBM1_OUTER_TPID_0_PIPE5 */ "", 37445 /* IDB_OBM1_OUTER_TPID_0_PIPE6 */ "", 37446 /* IDB_OBM1_OUTER_TPID_0_PIPE7 */ "", 37447 /* IDB_OBM1_OUTER_TPID_1_PIPE0 */ "", 37448 /* IDB_OBM1_OUTER_TPID_1_PIPE1 */ "", 37449 /* IDB_OBM1_OUTER_TPID_1_PIPE2 */ "", 37450 /* IDB_OBM1_OUTER_TPID_1_PIPE3 */ "", 37451 /* IDB_OBM1_OUTER_TPID_1_PIPE4 */ "", 37452 /* IDB_OBM1_OUTER_TPID_1_PIPE5 */ "", 37453 /* IDB_OBM1_OUTER_TPID_1_PIPE6 */ "", 37454 /* IDB_OBM1_OUTER_TPID_1_PIPE7 */ "", 37455 /* IDB_OBM1_OUTER_TPID_2_PIPE0 */ "", 37456 /* IDB_OBM1_OUTER_TPID_2_PIPE1 */ "", 37457 /* IDB_OBM1_OUTER_TPID_2_PIPE2 */ "", 37458 /* IDB_OBM1_OUTER_TPID_2_PIPE3 */ "", 37459 /* IDB_OBM1_OUTER_TPID_2_PIPE4 */ "", 37460 /* IDB_OBM1_OUTER_TPID_2_PIPE5 */ "", 37461 /* IDB_OBM1_OUTER_TPID_2_PIPE6 */ "", 37462 /* IDB_OBM1_OUTER_TPID_2_PIPE7 */ "", 37463 /* IDB_OBM1_OUTER_TPID_3_PIPE0 */ "", 37464 /* IDB_OBM1_OUTER_TPID_3_PIPE1 */ "", 37465 /* IDB_OBM1_OUTER_TPID_3_PIPE2 */ "", 37466 /* IDB_OBM1_OUTER_TPID_3_PIPE3 */ "", 37467 /* IDB_OBM1_OUTER_TPID_3_PIPE4 */ "", 37468 /* IDB_OBM1_OUTER_TPID_3_PIPE5 */ "", 37469 /* IDB_OBM1_OUTER_TPID_3_PIPE6 */ "", 37470 /* IDB_OBM1_OUTER_TPID_3_PIPE7 */ "", 37471 /* IDB_OBM1_OUTER_TPID_PIPE0 */ "", 37472 /* IDB_OBM1_OUTER_TPID_PIPE1 */ "", 37473 /* IDB_OBM1_OUTER_TPID_PIPE2 */ "", 37474 /* IDB_OBM1_OUTER_TPID_PIPE3 */ "", 37475 /* IDB_OBM1_OUTER_TPID_PIPE4 */ "", 37476 /* IDB_OBM1_OUTER_TPID_PIPE5 */ "", 37477 /* IDB_OBM1_OUTER_TPID_PIPE6 */ "", 37478 /* IDB_OBM1_OUTER_TPID_PIPE7 */ "", 37479 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS", 37480 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE0", 37481 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE1", 37482 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE2", 37483 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE3", 37484 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE4 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE4", 37485 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE5 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE5", 37486 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE6 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE6", 37487 /* IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE7 */ "IDB_OBM1_OVERSUB_MON_ECC_STATUS_PIPE7", 37488 /* IDB_OBM1_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM1_OVERSUB_MON_PARITY_STATUS", 37489 /* IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE0", 37490 /* IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE1", 37491 /* IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE2", 37492 /* IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM1_OVERSUB_MON_PARITY_STATUS_PIPE3", 37493 /* IDB_OBM1_PE_ETHERTYPE */ "", 37494 /* IDB_OBM1_PE_ETHERTYPE_PIPE0 */ "", 37495 /* IDB_OBM1_PE_ETHERTYPE_PIPE1 */ "", 37496 /* IDB_OBM1_PE_ETHERTYPE_PIPE2 */ "", 37497 /* IDB_OBM1_PE_ETHERTYPE_PIPE3 */ "", 37498 /* IDB_OBM1_PORT_CONFIG */ "", 37499 /* IDB_OBM1_PORT_CONFIG_PIPE0 */ "", 37500 /* IDB_OBM1_PORT_CONFIG_PIPE1 */ "", 37501 /* IDB_OBM1_PORT_CONFIG_PIPE2 */ "", 37502 /* IDB_OBM1_PORT_CONFIG_PIPE3 */ "", 37503 /* IDB_OBM1_PORT_CONFIG_PIPE4 */ "", 37504 /* IDB_OBM1_PORT_CONFIG_PIPE5 */ "", 37505 /* IDB_OBM1_PORT_CONFIG_PIPE6 */ "", 37506 /* IDB_OBM1_PORT_CONFIG_PIPE7 */ "", 37507 /* IDB_OBM1_POWER_SAVE */ "IDB_OBM1_POWER_SAVE", 37508 /* IDB_OBM1_PROTOCOL_CONTROL_0 */ "", 37509 /* IDB_OBM1_PROTOCOL_CONTROL_1 */ "", 37510 /* IDB_OBM1_PROTOCOL_CONTROL_2 */ "", 37511 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE0 */ "", 37512 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE1 */ "", 37513 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE2 */ "", 37514 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE3 */ "", 37515 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE4 */ "", 37516 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE5 */ "", 37517 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE6 */ "", 37518 /* IDB_OBM1_PROTOCOL_CONTROL_0_PIPE7 */ "", 37519 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE0 */ "", 37520 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE1 */ "", 37521 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE2 */ "", 37522 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE3 */ "", 37523 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE4 */ "", 37524 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE5 */ "", 37525 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE6 */ "", 37526 /* IDB_OBM1_PROTOCOL_CONTROL_1_PIPE7 */ "", 37527 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE0 */ "", 37528 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE1 */ "", 37529 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE2 */ "", 37530 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE3 */ "", 37531 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE4 */ "", 37532 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE5 */ "", 37533 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE6 */ "", 37534 /* IDB_OBM1_PROTOCOL_CONTROL_2_PIPE7 */ "", 37535 /* IDB_OBM1_QUEUE_ECC_STATUS */ "IDB_OBM1_QUEUE_ECC_STATUS", 37536 /* IDB_OBM1_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM1_QUEUE_ECC_STATUS_PIPE0", 37537 /* IDB_OBM1_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM1_QUEUE_ECC_STATUS_PIPE1", 37538 /* IDB_OBM1_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM1_QUEUE_ECC_STATUS_PIPE2", 37539 /* IDB_OBM1_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM1_QUEUE_ECC_STATUS_PIPE3", 37540 /* IDB_OBM1_QUEUE_SER_CONTROL */ "IDB_OBM1_QUEUE_SER_CONTROL", 37541 /* IDB_OBM1_Q_BANK_CONFIG */ "IDB_OBM1_Q_BANK_CONFIG", 37542 /* IDB_OBM1_Q_BANK_CONFIG_PIPE0 */ "IDB_OBM1_Q_BANK_CONFIG_PIPE0", 37543 /* IDB_OBM1_Q_BUFFER_CONFIG */ "", 37544 /* IDB_OBM1_Q_BUFFER_CONFIG_PIPE0 */ "", 37545 /* IDB_OBM1_Q_CA_CONTROL */ "IDB_OBM1_Q_CA_CONTROL", 37546 /* IDB_OBM1_Q_CA_CONTROL_PIPE0 */ "IDB_OBM1_Q_CA_CONTROL_PIPE0", 37547 /* IDB_OBM1_Q_CA_ECC_STATUS */ "IDB_OBM1_Q_CA_ECC_STATUS", 37548 /* IDB_OBM1_Q_CA_ECC_STATUS_PIPE0 */ "IDB_OBM1_Q_CA_ECC_STATUS_PIPE0", 37549 /* IDB_OBM1_Q_CA_HW_STATUS */ "", 37550 /* IDB_OBM1_Q_CA_HW_STATUS_PIPE0 */ "", 37551 /* IDB_OBM1_Q_CA_POINTER_STATUS */ "", 37552 /* IDB_OBM1_Q_CA_POINTER_STATUS_PIPE0 */ "", 37553 /* IDB_OBM1_Q_CONTROL */ "", 37554 /* IDB_OBM1_Q_CONTROL_PIPE0 */ "", 37555 /* IDB_OBM1_Q_CTRL */ "IDB_OBM1_Q_CTRL", 37556 /* IDB_OBM1_Q_CTRL_PIPE0 */ "IDB_OBM1_Q_CTRL_PIPE0", 37557 /* IDB_OBM1_Q_DATA_ECC_STATUS */ "IDB_OBM1_Q_DATA_ECC_STATUS", 37558 /* IDB_OBM1_Q_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM1_Q_DATA_ECC_STATUS_PIPE0", 37559 /* IDB_OBM1_Q_FC_THRESHOLD */ "", 37560 /* IDB_OBM1_Q_FC_THRESHOLD_1 */ "", 37561 /* IDB_OBM1_Q_FC_THRESHOLD_1_PIPE0 */ "", 37562 /* IDB_OBM1_Q_FC_THRESHOLD_PIPE0 */ "", 37563 /* IDB_OBM1_Q_FLOW_CONTROL_CONFIG */ "", 37564 /* IDB_OBM1_Q_FLOW_CONTROL_CONFIG_PIPE0 */ "", 37565 /* IDB_OBM1_Q_FLOW_CONTROL_EVENT_COUNT */ "", 37566 /* IDB_OBM1_Q_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 37567 /* IDB_OBM1_Q_INNER_TPID */ "", 37568 /* IDB_OBM1_Q_INNER_TPID_PIPE0 */ "", 37569 /* IDB_OBM1_Q_LOSSLESS0_BYTE_DROP_COUNT */ "", 37570 /* IDB_OBM1_Q_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 37571 /* IDB_OBM1_Q_LOSSLESS0_PKT_DROP_COUNT */ "", 37572 /* IDB_OBM1_Q_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 37573 /* IDB_OBM1_Q_LOSSLESS1_BYTE_DROP_COUNT */ "", 37574 /* IDB_OBM1_Q_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 37575 /* IDB_OBM1_Q_LOSSLESS1_PKT_DROP_COUNT */ "", 37576 /* IDB_OBM1_Q_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 37577 /* IDB_OBM1_Q_LOSSY_HI_BYTE_DROP_COUNT */ "", 37578 /* IDB_OBM1_Q_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 37579 /* IDB_OBM1_Q_LOSSY_HI_PKT_DROP_COUNT */ "", 37580 /* IDB_OBM1_Q_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 37581 /* IDB_OBM1_Q_LOSSY_LO_BYTE_DROP_COUNT */ "", 37582 /* IDB_OBM1_Q_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 37583 /* IDB_OBM1_Q_LOSSY_LO_PKT_DROP_COUNT */ "", 37584 /* IDB_OBM1_Q_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 37585 /* IDB_OBM1_Q_MAX_USAGE */ "IDB_OBM1_Q_MAX_USAGE", 37586 /* IDB_OBM1_Q_MAX_USAGE_PIPE0 */ "IDB_OBM1_Q_MAX_USAGE_PIPE0", 37587 /* IDB_OBM1_Q_MAX_USAGE_SELECT */ "", 37588 /* IDB_OBM1_Q_MAX_USAGE_SELECT_PIPE0 */ "", 37589 /* IDB_OBM1_Q_NIV_ETHERTYPE */ "", 37590 /* IDB_OBM1_Q_NIV_ETHERTYPE_PIPE0 */ "", 37591 /* IDB_OBM1_Q_OUTER_TPID */ "", 37592 /* IDB_OBM1_Q_OUTER_TPID_0 */ "", 37593 /* IDB_OBM1_Q_OUTER_TPID_1 */ "", 37594 /* IDB_OBM1_Q_OUTER_TPID_2 */ "", 37595 /* IDB_OBM1_Q_OUTER_TPID_3 */ "", 37596 /* IDB_OBM1_Q_OUTER_TPID_0_PIPE0 */ "", 37597 /* IDB_OBM1_Q_OUTER_TPID_1_PIPE0 */ "", 37598 /* IDB_OBM1_Q_OUTER_TPID_2_PIPE0 */ "", 37599 /* IDB_OBM1_Q_OUTER_TPID_3_PIPE0 */ "", 37600 /* IDB_OBM1_Q_OUTER_TPID_PIPE0 */ "", 37601 /* IDB_OBM1_Q_OVERSUB_MON_ECC_STATUS */ "IDB_OBM1_Q_OVERSUB_MON_ECC_STATUS", 37602 /* IDB_OBM1_Q_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM1_Q_OVERSUB_MON_ECC_STATUS_PIPE0", 37603 /* IDB_OBM1_Q_PE_ETHERTYPE */ "", 37604 /* IDB_OBM1_Q_PE_ETHERTYPE_PIPE0 */ "", 37605 /* IDB_OBM1_Q_PORT_CONFIG */ "", 37606 /* IDB_OBM1_Q_PORT_CONFIG_PIPE0 */ "", 37607 /* IDB_OBM1_Q_PROTOCOL_CONTROL_0 */ "", 37608 /* IDB_OBM1_Q_PROTOCOL_CONTROL_1 */ "", 37609 /* IDB_OBM1_Q_PROTOCOL_CONTROL_2 */ "", 37610 /* IDB_OBM1_Q_PROTOCOL_CONTROL_0_PIPE0 */ "", 37611 /* IDB_OBM1_Q_PROTOCOL_CONTROL_1_PIPE0 */ "", 37612 /* IDB_OBM1_Q_PROTOCOL_CONTROL_2_PIPE0 */ "", 37613 /* IDB_OBM1_Q_RAM_CONTROL */ "IDB_OBM1_Q_RAM_CONTROL", 37614 /* IDB_OBM1_Q_RAM_CONTROL_PIPE0 */ "IDB_OBM1_Q_RAM_CONTROL_PIPE0", 37615 /* IDB_OBM1_Q_SER_CONTROL */ "IDB_OBM1_Q_SER_CONTROL", 37616 /* IDB_OBM1_Q_SER_CONTROL_PIPE0 */ "IDB_OBM1_Q_SER_CONTROL_PIPE0", 37617 /* IDB_OBM1_Q_SHARED_CONFIG */ "IDB_OBM1_Q_SHARED_CONFIG", 37618 /* IDB_OBM1_Q_SHARED_CONFIG_PIPE0 */ "IDB_OBM1_Q_SHARED_CONFIG_PIPE0", 37619 /* IDB_OBM1_Q_THRESHOLD */ "", 37620 /* IDB_OBM1_Q_THRESHOLD_1 */ "", 37621 /* IDB_OBM1_Q_THRESHOLD_1_PIPE0 */ "", 37622 /* IDB_OBM1_Q_THRESHOLD_PIPE0 */ "", 37623 /* IDB_OBM1_Q_USAGE */ "", 37624 /* IDB_OBM1_Q_USAGE_PIPE0 */ "", 37625 /* IDB_OBM1_RAM_CONTROL */ "IDB_OBM1_RAM_CONTROL", 37626 /* IDB_OBM1_RAM_CONTROL_PIPE0 */ "IDB_OBM1_RAM_CONTROL_PIPE0", 37627 /* IDB_OBM1_RAM_CONTROL_PIPE1 */ "IDB_OBM1_RAM_CONTROL_PIPE1", 37628 /* IDB_OBM1_RAM_CONTROL_PIPE2 */ "IDB_OBM1_RAM_CONTROL_PIPE2", 37629 /* IDB_OBM1_RAM_CONTROL_PIPE3 */ "IDB_OBM1_RAM_CONTROL_PIPE3", 37630 /* IDB_OBM1_RAM_CONTROL_PIPE4 */ "IDB_OBM1_RAM_CONTROL_PIPE4", 37631 /* IDB_OBM1_RAM_CONTROL_PIPE5 */ "IDB_OBM1_RAM_CONTROL_PIPE5", 37632 /* IDB_OBM1_RAM_CONTROL_PIPE6 */ "IDB_OBM1_RAM_CONTROL_PIPE6", 37633 /* IDB_OBM1_RAM_CONTROL_PIPE7 */ "IDB_OBM1_RAM_CONTROL_PIPE7", 37634 /* IDB_OBM1_SER_CONTROL */ "IDB_OBM1_SER_CONTROL", 37635 /* IDB_OBM1_SER_CONTROL_PIPE0 */ "IDB_OBM1_SER_CONTROL_PIPE0", 37636 /* IDB_OBM1_SER_CONTROL_PIPE1 */ "IDB_OBM1_SER_CONTROL_PIPE1", 37637 /* IDB_OBM1_SHARED_CONFIG */ "IDB_OBM1_SHARED_CONFIG", 37638 /* IDB_OBM1_SHARED_CONFIG_PIPE0 */ "IDB_OBM1_SHARED_CONFIG_PIPE0", 37639 /* IDB_OBM1_SHARED_CONFIG_PIPE1 */ "IDB_OBM1_SHARED_CONFIG_PIPE1", 37640 /* IDB_OBM1_SHARED_CONFIG_PIPE2 */ "IDB_OBM1_SHARED_CONFIG_PIPE2", 37641 /* IDB_OBM1_SHARED_CONFIG_PIPE3 */ "IDB_OBM1_SHARED_CONFIG_PIPE3", 37642 /* IDB_OBM1_SHARED_CONFIG_PIPE4 */ "IDB_OBM1_SHARED_CONFIG_PIPE4", 37643 /* IDB_OBM1_SHARED_CONFIG_PIPE5 */ "IDB_OBM1_SHARED_CONFIG_PIPE5", 37644 /* IDB_OBM1_SHARED_CONFIG_PIPE6 */ "IDB_OBM1_SHARED_CONFIG_PIPE6", 37645 /* IDB_OBM1_SHARED_CONFIG_PIPE7 */ "IDB_OBM1_SHARED_CONFIG_PIPE7", 37646 /* IDB_OBM1_SHARED_USAGE */ "IDB_OBM1_SHARED_USAGE", 37647 /* IDB_OBM1_SHARED_USAGE_PIPE0 */ "IDB_OBM1_SHARED_USAGE_PIPE0", 37648 /* IDB_OBM1_SHARED_USAGE_PIPE1 */ "IDB_OBM1_SHARED_USAGE_PIPE1", 37649 /* IDB_OBM1_SHARED_USAGE_PIPE2 */ "IDB_OBM1_SHARED_USAGE_PIPE2", 37650 /* IDB_OBM1_SHARED_USAGE_PIPE3 */ "IDB_OBM1_SHARED_USAGE_PIPE3", 37651 /* IDB_OBM1_SPARE_REG */ "IDB_OBM1_SPARE_REG", 37652 /* IDB_OBM1_TDM */ "IDB_OBM1_TDM", 37653 /* IDB_OBM1_TDM_PIPE0 */ "IDB_OBM1_TDM_PIPE0", 37654 /* IDB_OBM1_TDM_PIPE1 */ "IDB_OBM1_TDM_PIPE1", 37655 /* IDB_OBM1_TDM_PIPE2 */ "IDB_OBM1_TDM_PIPE2", 37656 /* IDB_OBM1_TDM_PIPE3 */ "IDB_OBM1_TDM_PIPE3", 37657 /* IDB_OBM1_TDM_PIPE4 */ "IDB_OBM1_TDM_PIPE4", 37658 /* IDB_OBM1_TDM_PIPE5 */ "IDB_OBM1_TDM_PIPE5", 37659 /* IDB_OBM1_TDM_PIPE6 */ "IDB_OBM1_TDM_PIPE6", 37660 /* IDB_OBM1_TDM_PIPE7 */ "IDB_OBM1_TDM_PIPE7", 37661 /* IDB_OBM1_THRESHOLD */ "", 37662 /* IDB_OBM1_THRESHOLD_0 */ "", 37663 /* IDB_OBM1_THRESHOLD_1 */ "", 37664 /* IDB_OBM1_THRESHOLD_1_PIPE0 */ "", 37665 /* IDB_OBM1_THRESHOLD_1_PIPE1 */ "", 37666 /* IDB_OBM1_THRESHOLD_1_PIPE2 */ "", 37667 /* IDB_OBM1_THRESHOLD_1_PIPE3 */ "", 37668 /* IDB_OBM1_THRESHOLD_1_PIPE4 */ "", 37669 /* IDB_OBM1_THRESHOLD_1_PIPE5 */ "", 37670 /* IDB_OBM1_THRESHOLD_1_PIPE6 */ "", 37671 /* IDB_OBM1_THRESHOLD_1_PIPE7 */ "", 37672 /* IDB_OBM1_THRESHOLD_PIPE0 */ "", 37673 /* IDB_OBM1_THRESHOLD_PIPE1 */ "", 37674 /* IDB_OBM1_THRESHOLD_PIPE2 */ "", 37675 /* IDB_OBM1_THRESHOLD_PIPE3 */ "", 37676 /* IDB_OBM1_THRESHOLD_PIPE4 */ "", 37677 /* IDB_OBM1_THRESHOLD_PIPE5 */ "", 37678 /* IDB_OBM1_THRESHOLD_PIPE6 */ "", 37679 /* IDB_OBM1_THRESHOLD_PIPE7 */ "", 37680 /* IDB_OBM1_USAGE */ "", 37681 /* IDB_OBM1_USAGE_1 */ "", 37682 /* IDB_OBM1_USAGE_1_PIPE0 */ "", 37683 /* IDB_OBM1_USAGE_1_PIPE1 */ "", 37684 /* IDB_OBM1_USAGE_1_PIPE2 */ "", 37685 /* IDB_OBM1_USAGE_1_PIPE3 */ "", 37686 /* IDB_OBM1_USAGE_1_PIPE4 */ "", 37687 /* IDB_OBM1_USAGE_1_PIPE5 */ "", 37688 /* IDB_OBM1_USAGE_1_PIPE6 */ "", 37689 /* IDB_OBM1_USAGE_1_PIPE7 */ "", 37690 /* IDB_OBM1_USAGE_PIPE0 */ "", 37691 /* IDB_OBM1_USAGE_PIPE1 */ "", 37692 /* IDB_OBM1_USAGE_PIPE2 */ "", 37693 /* IDB_OBM1_USAGE_PIPE3 */ "", 37694 /* IDB_OBM1_USAGE_PIPE4 */ "", 37695 /* IDB_OBM1_USAGE_PIPE5 */ "", 37696 /* IDB_OBM1_USAGE_PIPE6 */ "", 37697 /* IDB_OBM1_USAGE_PIPE7 */ "", 37698 /* IDB_OBM2_48_BANK_CONFIG */ "IDB_OBM2_48_BANK_CONFIG", 37699 /* IDB_OBM2_48_BANK_CONFIG_PIPE0 */ "IDB_OBM2_48_BANK_CONFIG_PIPE0", 37700 /* IDB_OBM2_48_BUFFER_CONFIG */ "", 37701 /* IDB_OBM2_48_BUFFER_CONFIG_PIPE0 */ "", 37702 /* IDB_OBM2_48_CA_CONTROL */ "IDB_OBM2_48_CA_CONTROL", 37703 /* IDB_OBM2_48_CA_CONTROL_PIPE0 */ "IDB_OBM2_48_CA_CONTROL_PIPE0", 37704 /* IDB_OBM2_48_CA_ECC_STATUS */ "IDB_OBM2_48_CA_ECC_STATUS", 37705 /* IDB_OBM2_48_CA_ECC_STATUS_PIPE0 */ "IDB_OBM2_48_CA_ECC_STATUS_PIPE0", 37706 /* IDB_OBM2_48_CA_HW_STATUS */ "IDB_OBM2_48_CA_HW_STATUS", 37707 /* IDB_OBM2_48_CA_HW_STATUS_PIPE0 */ "IDB_OBM2_48_CA_HW_STATUS_PIPE0", 37708 /* IDB_OBM2_48_CA_POINTER_STATUS */ "IDB_OBM2_48_CA_POINTER_STATUS", 37709 /* IDB_OBM2_48_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM2_48_CA_POINTER_STATUS_PIPE0", 37710 /* IDB_OBM2_48_CONTROL */ "IDB_OBM2_48_CONTROL", 37711 /* IDB_OBM2_48_CONTROL_PIPE0 */ "IDB_OBM2_48_CONTROL_PIPE0", 37712 /* IDB_OBM2_48_DATA_ECC_STATUS */ "IDB_OBM2_48_DATA_ECC_STATUS", 37713 /* IDB_OBM2_48_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM2_48_DATA_ECC_STATUS_PIPE0", 37714 /* IDB_OBM2_48_FC_THRESHOLD */ "", 37715 /* IDB_OBM2_48_FC_THRESHOLD_1 */ "", 37716 /* IDB_OBM2_48_FC_THRESHOLD_1_PIPE0 */ "", 37717 /* IDB_OBM2_48_FC_THRESHOLD_PIPE0 */ "", 37718 /* IDB_OBM2_48_FLOW_CONTROL_CONFIG */ "", 37719 /* IDB_OBM2_48_FLOW_CONTROL_CONFIG_PIPE0 */ "", 37720 /* IDB_OBM2_48_FLOW_CONTROL_EVENT_COUNT */ "", 37721 /* IDB_OBM2_48_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 37722 /* IDB_OBM2_48_INNER_TPID */ "", 37723 /* IDB_OBM2_48_INNER_TPID_PIPE0 */ "", 37724 /* IDB_OBM2_48_LOSSLESS0_BYTE_DROP_COUNT */ "", 37725 /* IDB_OBM2_48_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 37726 /* IDB_OBM2_48_LOSSLESS0_PKT_DROP_COUNT */ "", 37727 /* IDB_OBM2_48_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 37728 /* IDB_OBM2_48_LOSSLESS1_BYTE_DROP_COUNT */ "", 37729 /* IDB_OBM2_48_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 37730 /* IDB_OBM2_48_LOSSLESS1_PKT_DROP_COUNT */ "", 37731 /* IDB_OBM2_48_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 37732 /* IDB_OBM2_48_LOSSY_HI_BYTE_DROP_COUNT */ "", 37733 /* IDB_OBM2_48_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 37734 /* IDB_OBM2_48_LOSSY_HI_PKT_DROP_COUNT */ "", 37735 /* IDB_OBM2_48_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 37736 /* IDB_OBM2_48_LOSSY_LO_BYTE_DROP_COUNT */ "", 37737 /* IDB_OBM2_48_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 37738 /* IDB_OBM2_48_LOSSY_LO_PKT_DROP_COUNT */ "", 37739 /* IDB_OBM2_48_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 37740 /* IDB_OBM2_48_MAX_USAGE */ "IDB_OBM2_48_MAX_USAGE", 37741 /* IDB_OBM2_48_MAX_USAGE_PIPE0 */ "IDB_OBM2_48_MAX_USAGE_PIPE0", 37742 /* IDB_OBM2_48_MAX_USAGE_SELECT */ "", 37743 /* IDB_OBM2_48_MAX_USAGE_SELECT_PIPE0 */ "", 37744 /* IDB_OBM2_48_NIV_ETHERTYPE */ "", 37745 /* IDB_OBM2_48_NIV_ETHERTYPE_PIPE0 */ "", 37746 /* IDB_OBM2_48_OUTER_TPID */ "", 37747 /* IDB_OBM2_48_OUTER_TPID_0 */ "", 37748 /* IDB_OBM2_48_OUTER_TPID_1 */ "", 37749 /* IDB_OBM2_48_OUTER_TPID_2 */ "", 37750 /* IDB_OBM2_48_OUTER_TPID_3 */ "", 37751 /* IDB_OBM2_48_OUTER_TPID_0_PIPE0 */ "", 37752 /* IDB_OBM2_48_OUTER_TPID_1_PIPE0 */ "", 37753 /* IDB_OBM2_48_OUTER_TPID_2_PIPE0 */ "", 37754 /* IDB_OBM2_48_OUTER_TPID_3_PIPE0 */ "", 37755 /* IDB_OBM2_48_OUTER_TPID_PIPE0 */ "", 37756 /* IDB_OBM2_48_OVERSUB_MON_ECC_STATUS */ "IDB_OBM2_48_OVERSUB_MON_ECC_STATUS", 37757 /* IDB_OBM2_48_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM2_48_OVERSUB_MON_ECC_STATUS_PIPE0", 37758 /* IDB_OBM2_48_PE_ETHERTYPE */ "", 37759 /* IDB_OBM2_48_PE_ETHERTYPE_PIPE0 */ "", 37760 /* IDB_OBM2_48_PORT_CONFIG */ "", 37761 /* IDB_OBM2_48_PORT_CONFIG_PIPE0 */ "", 37762 /* IDB_OBM2_48_PROTOCOL_CONTROL_0 */ "", 37763 /* IDB_OBM2_48_PROTOCOL_CONTROL_1 */ "", 37764 /* IDB_OBM2_48_PROTOCOL_CONTROL_2 */ "", 37765 /* IDB_OBM2_48_PROTOCOL_CONTROL_0_PIPE0 */ "", 37766 /* IDB_OBM2_48_PROTOCOL_CONTROL_1_PIPE0 */ "", 37767 /* IDB_OBM2_48_PROTOCOL_CONTROL_2_PIPE0 */ "", 37768 /* IDB_OBM2_48_RAM_CONTROL */ "IDB_OBM2_48_RAM_CONTROL", 37769 /* IDB_OBM2_48_RAM_CONTROL_PIPE0 */ "IDB_OBM2_48_RAM_CONTROL_PIPE0", 37770 /* IDB_OBM2_48_SER_CONTROL */ "IDB_OBM2_48_SER_CONTROL", 37771 /* IDB_OBM2_48_SER_CONTROL_PIPE0 */ "IDB_OBM2_48_SER_CONTROL_PIPE0", 37772 /* IDB_OBM2_48_SHARED_CONFIG */ "IDB_OBM2_48_SHARED_CONFIG", 37773 /* IDB_OBM2_48_SHARED_CONFIG_PIPE0 */ "IDB_OBM2_48_SHARED_CONFIG_PIPE0", 37774 /* IDB_OBM2_48_THRESHOLD */ "", 37775 /* IDB_OBM2_48_THRESHOLD_1 */ "", 37776 /* IDB_OBM2_48_THRESHOLD_1_PIPE0 */ "", 37777 /* IDB_OBM2_48_THRESHOLD_PIPE0 */ "", 37778 /* IDB_OBM2_48_USAGE */ "", 37779 /* IDB_OBM2_48_USAGE_PIPE0 */ "", 37780 /* IDB_OBM2_BANK_CONFIG */ "IDB_OBM2_BANK_CONFIG", 37781 /* IDB_OBM2_BANK_CONFIG_PIPE0 */ "IDB_OBM2_BANK_CONFIG_PIPE0", 37782 /* IDB_OBM2_BANK_CONFIG_PIPE1 */ "IDB_OBM2_BANK_CONFIG_PIPE1", 37783 /* IDB_OBM2_BANK_CONFIG_PIPE2 */ "IDB_OBM2_BANK_CONFIG_PIPE2", 37784 /* IDB_OBM2_BANK_CONFIG_PIPE3 */ "IDB_OBM2_BANK_CONFIG_PIPE3", 37785 /* IDB_OBM2_BUCKET_COUNT_CONFIG */ "", 37786 /* IDB_OBM2_BUFFER_CONFIG */ "", 37787 /* IDB_OBM2_BUFFER_CONFIG_PIPE0 */ "", 37788 /* IDB_OBM2_BUFFER_CONFIG_PIPE1 */ "", 37789 /* IDB_OBM2_BUFFER_CONFIG_PIPE2 */ "", 37790 /* IDB_OBM2_BUFFER_CONFIG_PIPE3 */ "", 37791 /* IDB_OBM2_BUFFER_CONFIG_PIPE4 */ "", 37792 /* IDB_OBM2_BUFFER_CONFIG_PIPE5 */ "", 37793 /* IDB_OBM2_BUFFER_CONFIG_PIPE6 */ "", 37794 /* IDB_OBM2_BUFFER_CONFIG_PIPE7 */ "", 37795 /* IDB_OBM2_CA_CONTROL */ "IDB_OBM2_CA_CONTROL", 37796 /* IDB_OBM2_CA_CONTROL_PIPE0 */ "IDB_OBM2_CA_CONTROL_PIPE0", 37797 /* IDB_OBM2_CA_CONTROL_PIPE1 */ "IDB_OBM2_CA_CONTROL_PIPE1", 37798 /* IDB_OBM2_CA_CONTROL_PIPE2 */ "IDB_OBM2_CA_CONTROL_PIPE2", 37799 /* IDB_OBM2_CA_CONTROL_PIPE3 */ "IDB_OBM2_CA_CONTROL_PIPE3", 37800 /* IDB_OBM2_CA_CT_CONTROL */ "IDB_OBM2_CA_CT_CONTROL", 37801 /* IDB_OBM2_CA_CT_CONTROL_PIPE0 */ "IDB_OBM2_CA_CT_CONTROL_PIPE0", 37802 /* IDB_OBM2_CA_CT_CONTROL_PIPE1 */ "IDB_OBM2_CA_CT_CONTROL_PIPE1", 37803 /* IDB_OBM2_CA_CT_CONTROL_PIPE2 */ "IDB_OBM2_CA_CT_CONTROL_PIPE2", 37804 /* IDB_OBM2_CA_CT_CONTROL_PIPE3 */ "IDB_OBM2_CA_CT_CONTROL_PIPE3", 37805 /* IDB_OBM2_CA_ECC_STATUS */ "IDB_OBM2_CA_ECC_STATUS", 37806 /* IDB_OBM2_CA_ECC_STATUS_PIPE0 */ "IDB_OBM2_CA_ECC_STATUS_PIPE0", 37807 /* IDB_OBM2_CA_ECC_STATUS_PIPE1 */ "IDB_OBM2_CA_ECC_STATUS_PIPE1", 37808 /* IDB_OBM2_CA_ECC_STATUS_PIPE2 */ "IDB_OBM2_CA_ECC_STATUS_PIPE2", 37809 /* IDB_OBM2_CA_ECC_STATUS_PIPE3 */ "IDB_OBM2_CA_ECC_STATUS_PIPE3", 37810 /* IDB_OBM2_CA_HW_CONTROL */ "IDB_OBM2_CA_HW_CONTROL", 37811 /* IDB_OBM2_CA_HW_CONTROL_PIPE0 */ "IDB_OBM2_CA_HW_CONTROL_PIPE0", 37812 /* IDB_OBM2_CA_HW_CONTROL_PIPE1 */ "IDB_OBM2_CA_HW_CONTROL_PIPE1", 37813 /* IDB_OBM2_CA_HW_CONTROL_PIPE2 */ "IDB_OBM2_CA_HW_CONTROL_PIPE2", 37814 /* IDB_OBM2_CA_HW_CONTROL_PIPE3 */ "IDB_OBM2_CA_HW_CONTROL_PIPE3", 37815 /* IDB_OBM2_CA_HW_STATUS */ "IDB_OBM2_CA_HW_STATUS", 37816 /* IDB_OBM2_CA_HW_STATUS_PIPE0 */ "IDB_OBM2_CA_HW_STATUS_PIPE0", 37817 /* IDB_OBM2_CA_HW_STATUS_PIPE1 */ "IDB_OBM2_CA_HW_STATUS_PIPE1", 37818 /* IDB_OBM2_CA_HW_STATUS_PIPE2 */ "IDB_OBM2_CA_HW_STATUS_PIPE2", 37819 /* IDB_OBM2_CA_HW_STATUS_PIPE3 */ "IDB_OBM2_CA_HW_STATUS_PIPE3", 37820 /* IDB_OBM2_CA_POINTER_STATUS */ "IDB_OBM2_CA_POINTER_STATUS", 37821 /* IDB_OBM2_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM2_CA_POINTER_STATUS_PIPE0", 37822 /* IDB_OBM2_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM2_CA_POINTER_STATUS_PIPE1", 37823 /* IDB_OBM2_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM2_CA_POINTER_STATUS_PIPE2", 37824 /* IDB_OBM2_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM2_CA_POINTER_STATUS_PIPE3", 37825 /* IDB_OBM2_CONTROL */ "IDB_OBM2_CONTROL", 37826 /* IDB_OBM2_CONTROL_PIPE0 */ "IDB_OBM2_CONTROL_PIPE0", 37827 /* IDB_OBM2_CONTROL_PIPE1 */ "IDB_OBM2_CONTROL_PIPE1", 37828 /* IDB_OBM2_CONTROL_PIPE2 */ "IDB_OBM2_CONTROL_PIPE2", 37829 /* IDB_OBM2_CONTROL_PIPE3 */ "IDB_OBM2_CONTROL_PIPE3", 37830 /* IDB_OBM2_CONTROL_PIPE4 */ "IDB_OBM2_CONTROL_PIPE4", 37831 /* IDB_OBM2_CONTROL_PIPE5 */ "IDB_OBM2_CONTROL_PIPE5", 37832 /* IDB_OBM2_CONTROL_PIPE6 */ "IDB_OBM2_CONTROL_PIPE6", 37833 /* IDB_OBM2_CONTROL_PIPE7 */ "IDB_OBM2_CONTROL_PIPE7", 37834 /* IDB_OBM2_CTRL_ECC_STATUS */ "IDB_OBM2_CTRL_ECC_STATUS", 37835 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE0 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE0", 37836 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE1 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE1", 37837 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE2 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE2", 37838 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE3 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE3", 37839 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE4 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE4", 37840 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE5 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE5", 37841 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE6 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE6", 37842 /* IDB_OBM2_CTRL_ECC_STATUS_PIPE7 */ "IDB_OBM2_CTRL_ECC_STATUS_PIPE7", 37843 /* IDB_OBM2_CT_THRESHOLD */ "", 37844 /* IDB_OBM2_CT_THRESHOLD_PIPE0 */ "", 37845 /* IDB_OBM2_CT_THRESHOLD_PIPE1 */ "", 37846 /* IDB_OBM2_CT_THRESHOLD_PIPE2 */ "", 37847 /* IDB_OBM2_CT_THRESHOLD_PIPE3 */ "", 37848 /* IDB_OBM2_CT_THRESHOLD_PIPE4 */ "", 37849 /* IDB_OBM2_CT_THRESHOLD_PIPE5 */ "", 37850 /* IDB_OBM2_CT_THRESHOLD_PIPE6 */ "", 37851 /* IDB_OBM2_CT_THRESHOLD_PIPE7 */ "", 37852 /* IDB_OBM2_DATA_ECC_STATUS */ "IDB_OBM2_DATA_ECC_STATUS", 37853 /* IDB_OBM2_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE0", 37854 /* IDB_OBM2_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE1", 37855 /* IDB_OBM2_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE2", 37856 /* IDB_OBM2_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE3", 37857 /* IDB_OBM2_DATA_ECC_STATUS_PIPE4 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE4", 37858 /* IDB_OBM2_DATA_ECC_STATUS_PIPE5 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE5", 37859 /* IDB_OBM2_DATA_ECC_STATUS_PIPE6 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE6", 37860 /* IDB_OBM2_DATA_ECC_STATUS_PIPE7 */ "IDB_OBM2_DATA_ECC_STATUS_PIPE7", 37861 /* IDB_OBM2_DBG_A */ "IDB_OBM2_FORCE_SAF_CONFIG", 37862 /* IDB_OBM2_DBG_A_PIPE0 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE0", 37863 /* IDB_OBM2_DBG_A_PIPE1 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE1", 37864 /* IDB_OBM2_DBG_A_PIPE2 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE2", 37865 /* IDB_OBM2_DBG_A_PIPE3 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE3", 37866 /* IDB_OBM2_DBG_A_PIPE4 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE4", 37867 /* IDB_OBM2_DBG_A_PIPE5 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE5", 37868 /* IDB_OBM2_DBG_A_PIPE6 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE6", 37869 /* IDB_OBM2_DBG_A_PIPE7 */ "IDB_OBM2_FORCE_SAF_CONFIG_PIPE7", 37870 /* IDB_OBM2_DBG_B */ "IDB_OBM2_LAG_DETECTION_CONFIG", 37871 /* IDB_OBM2_DBG_B_PIPE0 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE0", 37872 /* IDB_OBM2_DBG_B_PIPE1 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE1", 37873 /* IDB_OBM2_DBG_B_PIPE2 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE2", 37874 /* IDB_OBM2_DBG_B_PIPE3 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE3", 37875 /* IDB_OBM2_DBG_B_PIPE4 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE4", 37876 /* IDB_OBM2_DBG_B_PIPE5 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE5", 37877 /* IDB_OBM2_DBG_B_PIPE6 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE6", 37878 /* IDB_OBM2_DBG_B_PIPE7 */ "IDB_OBM2_LAG_DETECTION_CONFIG_PIPE7", 37879 /* IDB_OBM2_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 37880 /* IDB_OBM2_EXPRESS_ARRIVAL_PKT_COUNT */ "", 37881 /* IDB_OBM2_EXPRESS_BYTE_DROP_COUNT */ "", 37882 /* IDB_OBM2_EXPRESS_FLOW_CONTROL_CONFIG */ "", 37883 /* IDB_OBM2_EXPRESS_PKT_DROP_COUNT */ "", 37884 /* IDB_OBM2_FC_THRESHOLD */ "", 37885 /* IDB_OBM2_FC_THRESHOLD_0 */ "", 37886 /* IDB_OBM2_FC_THRESHOLD_1 */ "", 37887 /* IDB_OBM2_FC_THRESHOLD_1_PIPE0 */ "", 37888 /* IDB_OBM2_FC_THRESHOLD_1_PIPE1 */ "", 37889 /* IDB_OBM2_FC_THRESHOLD_1_PIPE2 */ "", 37890 /* IDB_OBM2_FC_THRESHOLD_1_PIPE3 */ "", 37891 /* IDB_OBM2_FC_THRESHOLD_1_PIPE4 */ "", 37892 /* IDB_OBM2_FC_THRESHOLD_1_PIPE5 */ "", 37893 /* IDB_OBM2_FC_THRESHOLD_1_PIPE6 */ "", 37894 /* IDB_OBM2_FC_THRESHOLD_1_PIPE7 */ "", 37895 /* IDB_OBM2_FC_THRESHOLD_PIPE0 */ "", 37896 /* IDB_OBM2_FC_THRESHOLD_PIPE1 */ "", 37897 /* IDB_OBM2_FC_THRESHOLD_PIPE2 */ "", 37898 /* IDB_OBM2_FC_THRESHOLD_PIPE3 */ "", 37899 /* IDB_OBM2_FC_THRESHOLD_PIPE4 */ "", 37900 /* IDB_OBM2_FC_THRESHOLD_PIPE5 */ "", 37901 /* IDB_OBM2_FC_THRESHOLD_PIPE6 */ "", 37902 /* IDB_OBM2_FC_THRESHOLD_PIPE7 */ "", 37903 /* IDB_OBM2_FLOW_CONTROL_CONFIG */ "", 37904 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE0 */ "", 37905 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE1 */ "", 37906 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE2 */ "", 37907 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE3 */ "", 37908 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE4 */ "", 37909 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE5 */ "", 37910 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE6 */ "", 37911 /* IDB_OBM2_FLOW_CONTROL_CONFIG_PIPE7 */ "", 37912 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT */ "", 37913 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 37914 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 37915 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 37916 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 37917 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE4 */ "", 37918 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE5 */ "", 37919 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE6 */ "", 37920 /* IDB_OBM2_FLOW_CONTROL_EVENT_COUNT_PIPE7 */ "", 37921 /* IDB_OBM2_FORCE_SAF_STATUS */ "", 37922 /* IDB_OBM2_FORCE_SAF_STATUS_PIPE0 */ "", 37923 /* IDB_OBM2_FORCE_SAF_STATUS_PIPE1 */ "", 37924 /* IDB_OBM2_HW_STATUS */ "IDB_OBM2_HW_STATUS", 37925 /* IDB_OBM2_HW_STATUS_PIPE0 */ "IDB_OBM2_HW_STATUS_PIPE0", 37926 /* IDB_OBM2_HW_STATUS_PIPE1 */ "IDB_OBM2_HW_STATUS_PIPE1", 37927 /* IDB_OBM2_HW_STATUS_PIPE2 */ "IDB_OBM2_HW_STATUS_PIPE2", 37928 /* IDB_OBM2_HW_STATUS_PIPE3 */ "IDB_OBM2_HW_STATUS_PIPE3", 37929 /* IDB_OBM2_HW_STATUS_PIPE4 */ "IDB_OBM2_HW_STATUS_PIPE4", 37930 /* IDB_OBM2_HW_STATUS_PIPE5 */ "IDB_OBM2_HW_STATUS_PIPE5", 37931 /* IDB_OBM2_HW_STATUS_PIPE6 */ "IDB_OBM2_HW_STATUS_PIPE6", 37932 /* IDB_OBM2_HW_STATUS_PIPE7 */ "IDB_OBM2_HW_STATUS_PIPE7", 37933 /* IDB_OBM2_INNER_TPID */ "", 37934 /* IDB_OBM2_INNER_TPID_PIPE0 */ "", 37935 /* IDB_OBM2_INNER_TPID_PIPE1 */ "", 37936 /* IDB_OBM2_INNER_TPID_PIPE2 */ "", 37937 /* IDB_OBM2_INNER_TPID_PIPE3 */ "", 37938 /* IDB_OBM2_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 37939 /* IDB_OBM2_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 37940 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT */ "", 37941 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 37942 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 37943 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 37944 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 37945 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE4 */ "", 37946 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE5 */ "", 37947 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE6 */ "", 37948 /* IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNT_PIPE7 */ "", 37949 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT */ "", 37950 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 37951 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 37952 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 37953 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 37954 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE4 */ "", 37955 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE5 */ "", 37956 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE6 */ "", 37957 /* IDB_OBM2_LOSSLESS0_PKT_DROP_COUNT_PIPE7 */ "", 37958 /* IDB_OBM2_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 37959 /* IDB_OBM2_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 37960 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT */ "", 37961 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 37962 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 37963 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 37964 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 37965 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE4 */ "", 37966 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE5 */ "", 37967 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE6 */ "", 37968 /* IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNT_PIPE7 */ "", 37969 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT */ "", 37970 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 37971 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 37972 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 37973 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 37974 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE4 */ "", 37975 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE5 */ "", 37976 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE6 */ "", 37977 /* IDB_OBM2_LOSSLESS1_PKT_DROP_COUNT_PIPE7 */ "", 37978 /* IDB_OBM2_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 37979 /* IDB_OBM2_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 37980 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT */ "", 37981 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 37982 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 37983 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 37984 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 37985 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE4 */ "", 37986 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE5 */ "", 37987 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE6 */ "", 37988 /* IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNT_PIPE7 */ "", 37989 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT */ "", 37990 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 37991 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 37992 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 37993 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 37994 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE4 */ "", 37995 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE5 */ "", 37996 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE6 */ "", 37997 /* IDB_OBM2_LOSSY_HI_PKT_DROP_COUNT_PIPE7 */ "", 37998 /* IDB_OBM2_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 37999 /* IDB_OBM2_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 38000 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT */ "", 38001 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 38002 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 38003 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 38004 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 38005 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE4 */ "", 38006 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE5 */ "", 38007 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE6 */ "", 38008 /* IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNT_PIPE7 */ "", 38009 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT */ "", 38010 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 38011 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 38012 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 38013 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 38014 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE4 */ "", 38015 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE5 */ "", 38016 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE6 */ "", 38017 /* IDB_OBM2_LOSSY_LO_PKT_DROP_COUNT_PIPE7 */ "", 38018 /* IDB_OBM2_MAX_USAGE */ "IDB_OBM2_MAX_USAGE", 38019 /* IDB_OBM2_MAX_USAGE_1 */ "IDB_OBM2_MAX_USAGE_1", 38020 /* IDB_OBM2_MAX_USAGE_2 */ "IDB_OBM2_MAX_USAGE_2", 38021 /* IDB_OBM2_MAX_USAGE_1_PIPE0 */ "IDB_OBM2_MAX_USAGE_1_PIPE0", 38022 /* IDB_OBM2_MAX_USAGE_1_PIPE1 */ "IDB_OBM2_MAX_USAGE_1_PIPE1", 38023 /* IDB_OBM2_MAX_USAGE_1_PIPE2 */ "IDB_OBM2_MAX_USAGE_1_PIPE2", 38024 /* IDB_OBM2_MAX_USAGE_1_PIPE3 */ "IDB_OBM2_MAX_USAGE_1_PIPE3", 38025 /* IDB_OBM2_MAX_USAGE_1_PIPE4 */ "IDB_OBM2_MAX_USAGE_1_PIPE4", 38026 /* IDB_OBM2_MAX_USAGE_1_PIPE5 */ "IDB_OBM2_MAX_USAGE_1_PIPE5", 38027 /* IDB_OBM2_MAX_USAGE_1_PIPE6 */ "IDB_OBM2_MAX_USAGE_1_PIPE6", 38028 /* IDB_OBM2_MAX_USAGE_1_PIPE7 */ "IDB_OBM2_MAX_USAGE_1_PIPE7", 38029 /* IDB_OBM2_MAX_USAGE_2_PIPE0 */ "IDB_OBM2_MAX_USAGE_2_PIPE0", 38030 /* IDB_OBM2_MAX_USAGE_2_PIPE1 */ "IDB_OBM2_MAX_USAGE_2_PIPE1", 38031 /* IDB_OBM2_MAX_USAGE_2_PIPE2 */ "IDB_OBM2_MAX_USAGE_2_PIPE2", 38032 /* IDB_OBM2_MAX_USAGE_2_PIPE3 */ "IDB_OBM2_MAX_USAGE_2_PIPE3", 38033 /* IDB_OBM2_MAX_USAGE_2_PIPE4 */ "IDB_OBM2_MAX_USAGE_2_PIPE4", 38034 /* IDB_OBM2_MAX_USAGE_2_PIPE5 */ "IDB_OBM2_MAX_USAGE_2_PIPE5", 38035 /* IDB_OBM2_MAX_USAGE_2_PIPE6 */ "IDB_OBM2_MAX_USAGE_2_PIPE6", 38036 /* IDB_OBM2_MAX_USAGE_2_PIPE7 */ "IDB_OBM2_MAX_USAGE_2_PIPE7", 38037 /* IDB_OBM2_MAX_USAGE_PIPE0 */ "IDB_OBM2_MAX_USAGE_PIPE0", 38038 /* IDB_OBM2_MAX_USAGE_PIPE1 */ "IDB_OBM2_MAX_USAGE_PIPE1", 38039 /* IDB_OBM2_MAX_USAGE_PIPE2 */ "IDB_OBM2_MAX_USAGE_PIPE2", 38040 /* IDB_OBM2_MAX_USAGE_PIPE3 */ "IDB_OBM2_MAX_USAGE_PIPE3", 38041 /* IDB_OBM2_MAX_USAGE_PIPE4 */ "IDB_OBM2_MAX_USAGE_PIPE4", 38042 /* IDB_OBM2_MAX_USAGE_PIPE5 */ "IDB_OBM2_MAX_USAGE_PIPE5", 38043 /* IDB_OBM2_MAX_USAGE_PIPE6 */ "IDB_OBM2_MAX_USAGE_PIPE6", 38044 /* IDB_OBM2_MAX_USAGE_PIPE7 */ "IDB_OBM2_MAX_USAGE_PIPE7", 38045 /* IDB_OBM2_MAX_USAGE_SELECT */ "", 38046 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE0 */ "", 38047 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE1 */ "", 38048 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE2 */ "", 38049 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE3 */ "", 38050 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE4 */ "", 38051 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE5 */ "", 38052 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE6 */ "", 38053 /* IDB_OBM2_MAX_USAGE_SELECT_PIPE7 */ "", 38054 /* IDB_OBM2_MONITOR_STATS_CONFIG */ "", 38055 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE0 */ "", 38056 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE1 */ "", 38057 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE2 */ "", 38058 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE3 */ "", 38059 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE4 */ "", 38060 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE5 */ "", 38061 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE6 */ "", 38062 /* IDB_OBM2_MONITOR_STATS_CONFIG_PIPE7 */ "", 38063 /* IDB_OBM2_NIV_ETHERTYPE */ "", 38064 /* IDB_OBM2_NIV_ETHERTYPE_PIPE0 */ "", 38065 /* IDB_OBM2_NIV_ETHERTYPE_PIPE1 */ "", 38066 /* IDB_OBM2_NIV_ETHERTYPE_PIPE2 */ "", 38067 /* IDB_OBM2_NIV_ETHERTYPE_PIPE3 */ "", 38068 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0 */ "", 38069 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1 */ "", 38070 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE0 */ "", 38071 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE1 */ "", 38072 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE2 */ "", 38073 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE3 */ "", 38074 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE4 */ "", 38075 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE5 */ "", 38076 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE6 */ "", 38077 /* IDB_OBM2_OPAQUE_TAG_CONFIG_0_PIPE7 */ "", 38078 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE0 */ "", 38079 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE1 */ "", 38080 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE2 */ "", 38081 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE3 */ "", 38082 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE4 */ "", 38083 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE5 */ "", 38084 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE6 */ "", 38085 /* IDB_OBM2_OPAQUE_TAG_CONFIG_1_PIPE7 */ "", 38086 /* IDB_OBM2_OUTER_TPID */ "", 38087 /* IDB_OBM2_OUTER_TPID_0 */ "", 38088 /* IDB_OBM2_OUTER_TPID_1 */ "", 38089 /* IDB_OBM2_OUTER_TPID_2 */ "", 38090 /* IDB_OBM2_OUTER_TPID_3 */ "", 38091 /* IDB_OBM2_OUTER_TPID_0_PIPE0 */ "", 38092 /* IDB_OBM2_OUTER_TPID_0_PIPE1 */ "", 38093 /* IDB_OBM2_OUTER_TPID_0_PIPE2 */ "", 38094 /* IDB_OBM2_OUTER_TPID_0_PIPE3 */ "", 38095 /* IDB_OBM2_OUTER_TPID_0_PIPE4 */ "", 38096 /* IDB_OBM2_OUTER_TPID_0_PIPE5 */ "", 38097 /* IDB_OBM2_OUTER_TPID_0_PIPE6 */ "", 38098 /* IDB_OBM2_OUTER_TPID_0_PIPE7 */ "", 38099 /* IDB_OBM2_OUTER_TPID_1_PIPE0 */ "", 38100 /* IDB_OBM2_OUTER_TPID_1_PIPE1 */ "", 38101 /* IDB_OBM2_OUTER_TPID_1_PIPE2 */ "", 38102 /* IDB_OBM2_OUTER_TPID_1_PIPE3 */ "", 38103 /* IDB_OBM2_OUTER_TPID_1_PIPE4 */ "", 38104 /* IDB_OBM2_OUTER_TPID_1_PIPE5 */ "", 38105 /* IDB_OBM2_OUTER_TPID_1_PIPE6 */ "", 38106 /* IDB_OBM2_OUTER_TPID_1_PIPE7 */ "", 38107 /* IDB_OBM2_OUTER_TPID_2_PIPE0 */ "", 38108 /* IDB_OBM2_OUTER_TPID_2_PIPE1 */ "", 38109 /* IDB_OBM2_OUTER_TPID_2_PIPE2 */ "", 38110 /* IDB_OBM2_OUTER_TPID_2_PIPE3 */ "", 38111 /* IDB_OBM2_OUTER_TPID_2_PIPE4 */ "", 38112 /* IDB_OBM2_OUTER_TPID_2_PIPE5 */ "", 38113 /* IDB_OBM2_OUTER_TPID_2_PIPE6 */ "", 38114 /* IDB_OBM2_OUTER_TPID_2_PIPE7 */ "", 38115 /* IDB_OBM2_OUTER_TPID_3_PIPE0 */ "", 38116 /* IDB_OBM2_OUTER_TPID_3_PIPE1 */ "", 38117 /* IDB_OBM2_OUTER_TPID_3_PIPE2 */ "", 38118 /* IDB_OBM2_OUTER_TPID_3_PIPE3 */ "", 38119 /* IDB_OBM2_OUTER_TPID_3_PIPE4 */ "", 38120 /* IDB_OBM2_OUTER_TPID_3_PIPE5 */ "", 38121 /* IDB_OBM2_OUTER_TPID_3_PIPE6 */ "", 38122 /* IDB_OBM2_OUTER_TPID_3_PIPE7 */ "", 38123 /* IDB_OBM2_OUTER_TPID_PIPE0 */ "", 38124 /* IDB_OBM2_OUTER_TPID_PIPE1 */ "", 38125 /* IDB_OBM2_OUTER_TPID_PIPE2 */ "", 38126 /* IDB_OBM2_OUTER_TPID_PIPE3 */ "", 38127 /* IDB_OBM2_OUTER_TPID_PIPE4 */ "", 38128 /* IDB_OBM2_OUTER_TPID_PIPE5 */ "", 38129 /* IDB_OBM2_OUTER_TPID_PIPE6 */ "", 38130 /* IDB_OBM2_OUTER_TPID_PIPE7 */ "", 38131 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS", 38132 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE0", 38133 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE1", 38134 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE2", 38135 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE3", 38136 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE4 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE4", 38137 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE5 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE5", 38138 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE6 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE6", 38139 /* IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE7 */ "IDB_OBM2_OVERSUB_MON_ECC_STATUS_PIPE7", 38140 /* IDB_OBM2_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM2_OVERSUB_MON_PARITY_STATUS", 38141 /* IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE0", 38142 /* IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE1", 38143 /* IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE2", 38144 /* IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM2_OVERSUB_MON_PARITY_STATUS_PIPE3", 38145 /* IDB_OBM2_PE_ETHERTYPE */ "", 38146 /* IDB_OBM2_PE_ETHERTYPE_PIPE0 */ "", 38147 /* IDB_OBM2_PE_ETHERTYPE_PIPE1 */ "", 38148 /* IDB_OBM2_PE_ETHERTYPE_PIPE2 */ "", 38149 /* IDB_OBM2_PE_ETHERTYPE_PIPE3 */ "", 38150 /* IDB_OBM2_PORT_CONFIG */ "", 38151 /* IDB_OBM2_PORT_CONFIG_PIPE0 */ "", 38152 /* IDB_OBM2_PORT_CONFIG_PIPE1 */ "", 38153 /* IDB_OBM2_PORT_CONFIG_PIPE2 */ "", 38154 /* IDB_OBM2_PORT_CONFIG_PIPE3 */ "", 38155 /* IDB_OBM2_PORT_CONFIG_PIPE4 */ "", 38156 /* IDB_OBM2_PORT_CONFIG_PIPE5 */ "", 38157 /* IDB_OBM2_PORT_CONFIG_PIPE6 */ "", 38158 /* IDB_OBM2_PORT_CONFIG_PIPE7 */ "", 38159 /* IDB_OBM2_POWER_SAVE */ "IDB_OBM2_POWER_SAVE", 38160 /* IDB_OBM2_PROTOCOL_CONTROL_0 */ "", 38161 /* IDB_OBM2_PROTOCOL_CONTROL_1 */ "", 38162 /* IDB_OBM2_PROTOCOL_CONTROL_2 */ "", 38163 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE0 */ "", 38164 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE1 */ "", 38165 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE2 */ "", 38166 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE3 */ "", 38167 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE4 */ "", 38168 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE5 */ "", 38169 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE6 */ "", 38170 /* IDB_OBM2_PROTOCOL_CONTROL_0_PIPE7 */ "", 38171 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE0 */ "", 38172 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE1 */ "", 38173 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE2 */ "", 38174 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE3 */ "", 38175 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE4 */ "", 38176 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE5 */ "", 38177 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE6 */ "", 38178 /* IDB_OBM2_PROTOCOL_CONTROL_1_PIPE7 */ "", 38179 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE0 */ "", 38180 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE1 */ "", 38181 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE2 */ "", 38182 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE3 */ "", 38183 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE4 */ "", 38184 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE5 */ "", 38185 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE6 */ "", 38186 /* IDB_OBM2_PROTOCOL_CONTROL_2_PIPE7 */ "", 38187 /* IDB_OBM2_QUEUE_ECC_STATUS */ "IDB_OBM2_QUEUE_ECC_STATUS", 38188 /* IDB_OBM2_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM2_QUEUE_ECC_STATUS_PIPE0", 38189 /* IDB_OBM2_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM2_QUEUE_ECC_STATUS_PIPE1", 38190 /* IDB_OBM2_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM2_QUEUE_ECC_STATUS_PIPE2", 38191 /* IDB_OBM2_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM2_QUEUE_ECC_STATUS_PIPE3", 38192 /* IDB_OBM2_QUEUE_SER_CONTROL */ "IDB_OBM2_QUEUE_SER_CONTROL", 38193 /* IDB_OBM2_Q_BANK_CONFIG */ "IDB_OBM2_Q_BANK_CONFIG", 38194 /* IDB_OBM2_Q_BANK_CONFIG_PIPE0 */ "IDB_OBM2_Q_BANK_CONFIG_PIPE0", 38195 /* IDB_OBM2_Q_BUFFER_CONFIG */ "", 38196 /* IDB_OBM2_Q_BUFFER_CONFIG_PIPE0 */ "", 38197 /* IDB_OBM2_Q_CA_CONTROL */ "IDB_OBM2_Q_CA_CONTROL", 38198 /* IDB_OBM2_Q_CA_CONTROL_PIPE0 */ "IDB_OBM2_Q_CA_CONTROL_PIPE0", 38199 /* IDB_OBM2_Q_CA_ECC_STATUS */ "IDB_OBM2_Q_CA_ECC_STATUS", 38200 /* IDB_OBM2_Q_CA_ECC_STATUS_PIPE0 */ "IDB_OBM2_Q_CA_ECC_STATUS_PIPE0", 38201 /* IDB_OBM2_Q_CA_HW_STATUS */ "", 38202 /* IDB_OBM2_Q_CA_HW_STATUS_PIPE0 */ "", 38203 /* IDB_OBM2_Q_CA_POINTER_STATUS */ "", 38204 /* IDB_OBM2_Q_CA_POINTER_STATUS_PIPE0 */ "", 38205 /* IDB_OBM2_Q_CONTROL */ "", 38206 /* IDB_OBM2_Q_CONTROL_PIPE0 */ "", 38207 /* IDB_OBM2_Q_CTRL */ "IDB_OBM2_Q_CTRL", 38208 /* IDB_OBM2_Q_CTRL_PIPE0 */ "IDB_OBM2_Q_CTRL_PIPE0", 38209 /* IDB_OBM2_Q_DATA_ECC_STATUS */ "IDB_OBM2_Q_DATA_ECC_STATUS", 38210 /* IDB_OBM2_Q_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM2_Q_DATA_ECC_STATUS_PIPE0", 38211 /* IDB_OBM2_Q_FC_THRESHOLD */ "", 38212 /* IDB_OBM2_Q_FC_THRESHOLD_1 */ "", 38213 /* IDB_OBM2_Q_FC_THRESHOLD_1_PIPE0 */ "", 38214 /* IDB_OBM2_Q_FC_THRESHOLD_PIPE0 */ "", 38215 /* IDB_OBM2_Q_FLOW_CONTROL_CONFIG */ "", 38216 /* IDB_OBM2_Q_FLOW_CONTROL_CONFIG_PIPE0 */ "", 38217 /* IDB_OBM2_Q_FLOW_CONTROL_EVENT_COUNT */ "", 38218 /* IDB_OBM2_Q_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 38219 /* IDB_OBM2_Q_INNER_TPID */ "", 38220 /* IDB_OBM2_Q_INNER_TPID_PIPE0 */ "", 38221 /* IDB_OBM2_Q_LOSSLESS0_BYTE_DROP_COUNT */ "", 38222 /* IDB_OBM2_Q_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 38223 /* IDB_OBM2_Q_LOSSLESS0_PKT_DROP_COUNT */ "", 38224 /* IDB_OBM2_Q_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 38225 /* IDB_OBM2_Q_LOSSLESS1_BYTE_DROP_COUNT */ "", 38226 /* IDB_OBM2_Q_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 38227 /* IDB_OBM2_Q_LOSSLESS1_PKT_DROP_COUNT */ "", 38228 /* IDB_OBM2_Q_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 38229 /* IDB_OBM2_Q_LOSSY_HI_BYTE_DROP_COUNT */ "", 38230 /* IDB_OBM2_Q_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 38231 /* IDB_OBM2_Q_LOSSY_HI_PKT_DROP_COUNT */ "", 38232 /* IDB_OBM2_Q_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 38233 /* IDB_OBM2_Q_LOSSY_LO_BYTE_DROP_COUNT */ "", 38234 /* IDB_OBM2_Q_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 38235 /* IDB_OBM2_Q_LOSSY_LO_PKT_DROP_COUNT */ "", 38236 /* IDB_OBM2_Q_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 38237 /* IDB_OBM2_Q_MAX_USAGE */ "IDB_OBM2_Q_MAX_USAGE", 38238 /* IDB_OBM2_Q_MAX_USAGE_PIPE0 */ "IDB_OBM2_Q_MAX_USAGE_PIPE0", 38239 /* IDB_OBM2_Q_MAX_USAGE_SELECT */ "", 38240 /* IDB_OBM2_Q_MAX_USAGE_SELECT_PIPE0 */ "", 38241 /* IDB_OBM2_Q_NIV_ETHERTYPE */ "", 38242 /* IDB_OBM2_Q_NIV_ETHERTYPE_PIPE0 */ "", 38243 /* IDB_OBM2_Q_OUTER_TPID */ "", 38244 /* IDB_OBM2_Q_OUTER_TPID_0 */ "", 38245 /* IDB_OBM2_Q_OUTER_TPID_1 */ "", 38246 /* IDB_OBM2_Q_OUTER_TPID_2 */ "", 38247 /* IDB_OBM2_Q_OUTER_TPID_3 */ "", 38248 /* IDB_OBM2_Q_OUTER_TPID_0_PIPE0 */ "", 38249 /* IDB_OBM2_Q_OUTER_TPID_1_PIPE0 */ "", 38250 /* IDB_OBM2_Q_OUTER_TPID_2_PIPE0 */ "", 38251 /* IDB_OBM2_Q_OUTER_TPID_3_PIPE0 */ "", 38252 /* IDB_OBM2_Q_OUTER_TPID_PIPE0 */ "", 38253 /* IDB_OBM2_Q_OVERSUB_MON_ECC_STATUS */ "IDB_OBM2_Q_OVERSUB_MON_ECC_STATUS", 38254 /* IDB_OBM2_Q_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM2_Q_OVERSUB_MON_ECC_STATUS_PIPE0", 38255 /* IDB_OBM2_Q_PE_ETHERTYPE */ "", 38256 /* IDB_OBM2_Q_PE_ETHERTYPE_PIPE0 */ "", 38257 /* IDB_OBM2_Q_PORT_CONFIG */ "", 38258 /* IDB_OBM2_Q_PORT_CONFIG_PIPE0 */ "", 38259 /* IDB_OBM2_Q_PROTOCOL_CONTROL_0 */ "", 38260 /* IDB_OBM2_Q_PROTOCOL_CONTROL_1 */ "", 38261 /* IDB_OBM2_Q_PROTOCOL_CONTROL_2 */ "", 38262 /* IDB_OBM2_Q_PROTOCOL_CONTROL_0_PIPE0 */ "", 38263 /* IDB_OBM2_Q_PROTOCOL_CONTROL_1_PIPE0 */ "", 38264 /* IDB_OBM2_Q_PROTOCOL_CONTROL_2_PIPE0 */ "", 38265 /* IDB_OBM2_Q_RAM_CONTROL */ "IDB_OBM2_Q_RAM_CONTROL", 38266 /* IDB_OBM2_Q_RAM_CONTROL_PIPE0 */ "IDB_OBM2_Q_RAM_CONTROL_PIPE0", 38267 /* IDB_OBM2_Q_SER_CONTROL */ "IDB_OBM2_Q_SER_CONTROL", 38268 /* IDB_OBM2_Q_SER_CONTROL_PIPE0 */ "IDB_OBM2_Q_SER_CONTROL_PIPE0", 38269 /* IDB_OBM2_Q_SHARED_CONFIG */ "IDB_OBM2_Q_SHARED_CONFIG", 38270 /* IDB_OBM2_Q_SHARED_CONFIG_PIPE0 */ "IDB_OBM2_Q_SHARED_CONFIG_PIPE0", 38271 /* IDB_OBM2_Q_THRESHOLD */ "", 38272 /* IDB_OBM2_Q_THRESHOLD_1 */ "", 38273 /* IDB_OBM2_Q_THRESHOLD_1_PIPE0 */ "", 38274 /* IDB_OBM2_Q_THRESHOLD_PIPE0 */ "", 38275 /* IDB_OBM2_Q_USAGE */ "", 38276 /* IDB_OBM2_Q_USAGE_PIPE0 */ "", 38277 /* IDB_OBM2_RAM_CONTROL */ "IDB_OBM2_RAM_CONTROL", 38278 /* IDB_OBM2_RAM_CONTROL_PIPE0 */ "IDB_OBM2_RAM_CONTROL_PIPE0", 38279 /* IDB_OBM2_RAM_CONTROL_PIPE1 */ "IDB_OBM2_RAM_CONTROL_PIPE1", 38280 /* IDB_OBM2_RAM_CONTROL_PIPE2 */ "IDB_OBM2_RAM_CONTROL_PIPE2", 38281 /* IDB_OBM2_RAM_CONTROL_PIPE3 */ "IDB_OBM2_RAM_CONTROL_PIPE3", 38282 /* IDB_OBM2_RAM_CONTROL_PIPE4 */ "IDB_OBM2_RAM_CONTROL_PIPE4", 38283 /* IDB_OBM2_RAM_CONTROL_PIPE5 */ "IDB_OBM2_RAM_CONTROL_PIPE5", 38284 /* IDB_OBM2_RAM_CONTROL_PIPE6 */ "IDB_OBM2_RAM_CONTROL_PIPE6", 38285 /* IDB_OBM2_RAM_CONTROL_PIPE7 */ "IDB_OBM2_RAM_CONTROL_PIPE7", 38286 /* IDB_OBM2_SER_CONTROL */ "IDB_OBM2_SER_CONTROL", 38287 /* IDB_OBM2_SER_CONTROL_PIPE0 */ "IDB_OBM2_SER_CONTROL_PIPE0", 38288 /* IDB_OBM2_SER_CONTROL_PIPE1 */ "IDB_OBM2_SER_CONTROL_PIPE1", 38289 /* IDB_OBM2_SHARED_CONFIG */ "IDB_OBM2_SHARED_CONFIG", 38290 /* IDB_OBM2_SHARED_CONFIG_PIPE0 */ "IDB_OBM2_SHARED_CONFIG_PIPE0", 38291 /* IDB_OBM2_SHARED_CONFIG_PIPE1 */ "IDB_OBM2_SHARED_CONFIG_PIPE1", 38292 /* IDB_OBM2_SHARED_CONFIG_PIPE2 */ "IDB_OBM2_SHARED_CONFIG_PIPE2", 38293 /* IDB_OBM2_SHARED_CONFIG_PIPE3 */ "IDB_OBM2_SHARED_CONFIG_PIPE3", 38294 /* IDB_OBM2_SHARED_CONFIG_PIPE4 */ "IDB_OBM2_SHARED_CONFIG_PIPE4", 38295 /* IDB_OBM2_SHARED_CONFIG_PIPE5 */ "IDB_OBM2_SHARED_CONFIG_PIPE5", 38296 /* IDB_OBM2_SHARED_CONFIG_PIPE6 */ "IDB_OBM2_SHARED_CONFIG_PIPE6", 38297 /* IDB_OBM2_SHARED_CONFIG_PIPE7 */ "IDB_OBM2_SHARED_CONFIG_PIPE7", 38298 /* IDB_OBM2_SHARED_USAGE */ "IDB_OBM2_SHARED_USAGE", 38299 /* IDB_OBM2_SHARED_USAGE_PIPE0 */ "IDB_OBM2_SHARED_USAGE_PIPE0", 38300 /* IDB_OBM2_SHARED_USAGE_PIPE1 */ "IDB_OBM2_SHARED_USAGE_PIPE1", 38301 /* IDB_OBM2_SHARED_USAGE_PIPE2 */ "IDB_OBM2_SHARED_USAGE_PIPE2", 38302 /* IDB_OBM2_SHARED_USAGE_PIPE3 */ "IDB_OBM2_SHARED_USAGE_PIPE3", 38303 /* IDB_OBM2_SPARE_REG */ "IDB_OBM2_SPARE_REG", 38304 /* IDB_OBM2_TDM */ "IDB_OBM2_TDM", 38305 /* IDB_OBM2_TDM_PIPE0 */ "IDB_OBM2_TDM_PIPE0", 38306 /* IDB_OBM2_TDM_PIPE1 */ "IDB_OBM2_TDM_PIPE1", 38307 /* IDB_OBM2_TDM_PIPE2 */ "IDB_OBM2_TDM_PIPE2", 38308 /* IDB_OBM2_TDM_PIPE3 */ "IDB_OBM2_TDM_PIPE3", 38309 /* IDB_OBM2_TDM_PIPE4 */ "IDB_OBM2_TDM_PIPE4", 38310 /* IDB_OBM2_TDM_PIPE5 */ "IDB_OBM2_TDM_PIPE5", 38311 /* IDB_OBM2_TDM_PIPE6 */ "IDB_OBM2_TDM_PIPE6", 38312 /* IDB_OBM2_TDM_PIPE7 */ "IDB_OBM2_TDM_PIPE7", 38313 /* IDB_OBM2_THRESHOLD */ "", 38314 /* IDB_OBM2_THRESHOLD_0 */ "", 38315 /* IDB_OBM2_THRESHOLD_1 */ "", 38316 /* IDB_OBM2_THRESHOLD_1_PIPE0 */ "", 38317 /* IDB_OBM2_THRESHOLD_1_PIPE1 */ "", 38318 /* IDB_OBM2_THRESHOLD_1_PIPE2 */ "", 38319 /* IDB_OBM2_THRESHOLD_1_PIPE3 */ "", 38320 /* IDB_OBM2_THRESHOLD_1_PIPE4 */ "", 38321 /* IDB_OBM2_THRESHOLD_1_PIPE5 */ "", 38322 /* IDB_OBM2_THRESHOLD_1_PIPE6 */ "", 38323 /* IDB_OBM2_THRESHOLD_1_PIPE7 */ "", 38324 /* IDB_OBM2_THRESHOLD_PIPE0 */ "", 38325 /* IDB_OBM2_THRESHOLD_PIPE1 */ "", 38326 /* IDB_OBM2_THRESHOLD_PIPE2 */ "", 38327 /* IDB_OBM2_THRESHOLD_PIPE3 */ "", 38328 /* IDB_OBM2_THRESHOLD_PIPE4 */ "", 38329 /* IDB_OBM2_THRESHOLD_PIPE5 */ "", 38330 /* IDB_OBM2_THRESHOLD_PIPE6 */ "", 38331 /* IDB_OBM2_THRESHOLD_PIPE7 */ "", 38332 /* IDB_OBM2_USAGE */ "", 38333 /* IDB_OBM2_USAGE_1 */ "", 38334 /* IDB_OBM2_USAGE_1_PIPE0 */ "", 38335 /* IDB_OBM2_USAGE_1_PIPE1 */ "", 38336 /* IDB_OBM2_USAGE_1_PIPE2 */ "", 38337 /* IDB_OBM2_USAGE_1_PIPE3 */ "", 38338 /* IDB_OBM2_USAGE_1_PIPE4 */ "", 38339 /* IDB_OBM2_USAGE_1_PIPE5 */ "", 38340 /* IDB_OBM2_USAGE_1_PIPE6 */ "", 38341 /* IDB_OBM2_USAGE_1_PIPE7 */ "", 38342 /* IDB_OBM2_USAGE_PIPE0 */ "", 38343 /* IDB_OBM2_USAGE_PIPE1 */ "", 38344 /* IDB_OBM2_USAGE_PIPE2 */ "", 38345 /* IDB_OBM2_USAGE_PIPE3 */ "", 38346 /* IDB_OBM2_USAGE_PIPE4 */ "", 38347 /* IDB_OBM2_USAGE_PIPE5 */ "", 38348 /* IDB_OBM2_USAGE_PIPE6 */ "", 38349 /* IDB_OBM2_USAGE_PIPE7 */ "", 38350 /* IDB_OBM3_BANK_CONFIG */ "IDB_OBM3_BANK_CONFIG", 38351 /* IDB_OBM3_BANK_CONFIG_PIPE0 */ "IDB_OBM3_BANK_CONFIG_PIPE0", 38352 /* IDB_OBM3_BANK_CONFIG_PIPE1 */ "IDB_OBM3_BANK_CONFIG_PIPE1", 38353 /* IDB_OBM3_BANK_CONFIG_PIPE2 */ "IDB_OBM3_BANK_CONFIG_PIPE2", 38354 /* IDB_OBM3_BANK_CONFIG_PIPE3 */ "IDB_OBM3_BANK_CONFIG_PIPE3", 38355 /* IDB_OBM3_BUCKET_COUNT_CONFIG */ "", 38356 /* IDB_OBM3_BUFFER_CONFIG */ "", 38357 /* IDB_OBM3_BUFFER_CONFIG_PIPE0 */ "", 38358 /* IDB_OBM3_BUFFER_CONFIG_PIPE1 */ "", 38359 /* IDB_OBM3_BUFFER_CONFIG_PIPE2 */ "", 38360 /* IDB_OBM3_BUFFER_CONFIG_PIPE3 */ "", 38361 /* IDB_OBM3_BUFFER_CONFIG_PIPE4 */ "", 38362 /* IDB_OBM3_BUFFER_CONFIG_PIPE5 */ "", 38363 /* IDB_OBM3_BUFFER_CONFIG_PIPE6 */ "", 38364 /* IDB_OBM3_BUFFER_CONFIG_PIPE7 */ "", 38365 /* IDB_OBM3_CA_CONTROL */ "IDB_OBM3_CA_CONTROL", 38366 /* IDB_OBM3_CA_CONTROL_PIPE0 */ "IDB_OBM3_CA_CONTROL_PIPE0", 38367 /* IDB_OBM3_CA_CONTROL_PIPE1 */ "IDB_OBM3_CA_CONTROL_PIPE1", 38368 /* IDB_OBM3_CA_CONTROL_PIPE2 */ "IDB_OBM3_CA_CONTROL_PIPE2", 38369 /* IDB_OBM3_CA_CONTROL_PIPE3 */ "IDB_OBM3_CA_CONTROL_PIPE3", 38370 /* IDB_OBM3_CA_CT_CONTROL */ "IDB_OBM3_CA_CT_CONTROL", 38371 /* IDB_OBM3_CA_CT_CONTROL_PIPE0 */ "IDB_OBM3_CA_CT_CONTROL_PIPE0", 38372 /* IDB_OBM3_CA_CT_CONTROL_PIPE1 */ "IDB_OBM3_CA_CT_CONTROL_PIPE1", 38373 /* IDB_OBM3_CA_CT_CONTROL_PIPE2 */ "IDB_OBM3_CA_CT_CONTROL_PIPE2", 38374 /* IDB_OBM3_CA_CT_CONTROL_PIPE3 */ "IDB_OBM3_CA_CT_CONTROL_PIPE3", 38375 /* IDB_OBM3_CA_ECC_STATUS */ "IDB_OBM3_CA_ECC_STATUS", 38376 /* IDB_OBM3_CA_ECC_STATUS_PIPE0 */ "IDB_OBM3_CA_ECC_STATUS_PIPE0", 38377 /* IDB_OBM3_CA_ECC_STATUS_PIPE1 */ "IDB_OBM3_CA_ECC_STATUS_PIPE1", 38378 /* IDB_OBM3_CA_ECC_STATUS_PIPE2 */ "IDB_OBM3_CA_ECC_STATUS_PIPE2", 38379 /* IDB_OBM3_CA_ECC_STATUS_PIPE3 */ "IDB_OBM3_CA_ECC_STATUS_PIPE3", 38380 /* IDB_OBM3_CA_HW_CONTROL */ "IDB_OBM3_CA_HW_CONTROL", 38381 /* IDB_OBM3_CA_HW_CONTROL_PIPE0 */ "IDB_OBM3_CA_HW_CONTROL_PIPE0", 38382 /* IDB_OBM3_CA_HW_CONTROL_PIPE1 */ "IDB_OBM3_CA_HW_CONTROL_PIPE1", 38383 /* IDB_OBM3_CA_HW_CONTROL_PIPE2 */ "IDB_OBM3_CA_HW_CONTROL_PIPE2", 38384 /* IDB_OBM3_CA_HW_CONTROL_PIPE3 */ "IDB_OBM3_CA_HW_CONTROL_PIPE3", 38385 /* IDB_OBM3_CA_HW_STATUS */ "IDB_OBM3_CA_HW_STATUS", 38386 /* IDB_OBM3_CA_HW_STATUS_PIPE0 */ "IDB_OBM3_CA_HW_STATUS_PIPE0", 38387 /* IDB_OBM3_CA_HW_STATUS_PIPE1 */ "IDB_OBM3_CA_HW_STATUS_PIPE1", 38388 /* IDB_OBM3_CA_HW_STATUS_PIPE2 */ "IDB_OBM3_CA_HW_STATUS_PIPE2", 38389 /* IDB_OBM3_CA_HW_STATUS_PIPE3 */ "IDB_OBM3_CA_HW_STATUS_PIPE3", 38390 /* IDB_OBM3_CA_POINTER_STATUS */ "IDB_OBM3_CA_POINTER_STATUS", 38391 /* IDB_OBM3_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM3_CA_POINTER_STATUS_PIPE0", 38392 /* IDB_OBM3_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM3_CA_POINTER_STATUS_PIPE1", 38393 /* IDB_OBM3_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM3_CA_POINTER_STATUS_PIPE2", 38394 /* IDB_OBM3_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM3_CA_POINTER_STATUS_PIPE3", 38395 /* IDB_OBM3_CONTROL */ "IDB_OBM3_CONTROL", 38396 /* IDB_OBM3_CONTROL_PIPE0 */ "IDB_OBM3_CONTROL_PIPE0", 38397 /* IDB_OBM3_CONTROL_PIPE1 */ "IDB_OBM3_CONTROL_PIPE1", 38398 /* IDB_OBM3_CONTROL_PIPE2 */ "IDB_OBM3_CONTROL_PIPE2", 38399 /* IDB_OBM3_CONTROL_PIPE3 */ "IDB_OBM3_CONTROL_PIPE3", 38400 /* IDB_OBM3_CONTROL_PIPE4 */ "IDB_OBM3_CONTROL_PIPE4", 38401 /* IDB_OBM3_CONTROL_PIPE5 */ "IDB_OBM3_CONTROL_PIPE5", 38402 /* IDB_OBM3_CONTROL_PIPE6 */ "IDB_OBM3_CONTROL_PIPE6", 38403 /* IDB_OBM3_CONTROL_PIPE7 */ "IDB_OBM3_CONTROL_PIPE7", 38404 /* IDB_OBM3_CTRL_ECC_STATUS */ "IDB_OBM3_CTRL_ECC_STATUS", 38405 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE0 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE0", 38406 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE1 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE1", 38407 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE2 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE2", 38408 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE3 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE3", 38409 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE4 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE4", 38410 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE5 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE5", 38411 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE6 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE6", 38412 /* IDB_OBM3_CTRL_ECC_STATUS_PIPE7 */ "IDB_OBM3_CTRL_ECC_STATUS_PIPE7", 38413 /* IDB_OBM3_CT_THRESHOLD */ "", 38414 /* IDB_OBM3_CT_THRESHOLD_PIPE0 */ "", 38415 /* IDB_OBM3_CT_THRESHOLD_PIPE1 */ "", 38416 /* IDB_OBM3_CT_THRESHOLD_PIPE2 */ "", 38417 /* IDB_OBM3_CT_THRESHOLD_PIPE3 */ "", 38418 /* IDB_OBM3_CT_THRESHOLD_PIPE4 */ "", 38419 /* IDB_OBM3_CT_THRESHOLD_PIPE5 */ "", 38420 /* IDB_OBM3_CT_THRESHOLD_PIPE6 */ "", 38421 /* IDB_OBM3_CT_THRESHOLD_PIPE7 */ "", 38422 /* IDB_OBM3_DATA_ECC_STATUS */ "IDB_OBM3_DATA_ECC_STATUS", 38423 /* IDB_OBM3_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE0", 38424 /* IDB_OBM3_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE1", 38425 /* IDB_OBM3_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE2", 38426 /* IDB_OBM3_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE3", 38427 /* IDB_OBM3_DATA_ECC_STATUS_PIPE4 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE4", 38428 /* IDB_OBM3_DATA_ECC_STATUS_PIPE5 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE5", 38429 /* IDB_OBM3_DATA_ECC_STATUS_PIPE6 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE6", 38430 /* IDB_OBM3_DATA_ECC_STATUS_PIPE7 */ "IDB_OBM3_DATA_ECC_STATUS_PIPE7", 38431 /* IDB_OBM3_DBG_A */ "IDB_OBM3_FORCE_SAF_CONFIG", 38432 /* IDB_OBM3_DBG_A_PIPE0 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE0", 38433 /* IDB_OBM3_DBG_A_PIPE1 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE1", 38434 /* IDB_OBM3_DBG_A_PIPE2 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE2", 38435 /* IDB_OBM3_DBG_A_PIPE3 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE3", 38436 /* IDB_OBM3_DBG_A_PIPE4 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE4", 38437 /* IDB_OBM3_DBG_A_PIPE5 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE5", 38438 /* IDB_OBM3_DBG_A_PIPE6 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE6", 38439 /* IDB_OBM3_DBG_A_PIPE7 */ "IDB_OBM3_FORCE_SAF_CONFIG_PIPE7", 38440 /* IDB_OBM3_DBG_B */ "IDB_OBM3_LAG_DETECTION_CONFIG", 38441 /* IDB_OBM3_DBG_B_PIPE0 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE0", 38442 /* IDB_OBM3_DBG_B_PIPE1 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE1", 38443 /* IDB_OBM3_DBG_B_PIPE2 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE2", 38444 /* IDB_OBM3_DBG_B_PIPE3 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE3", 38445 /* IDB_OBM3_DBG_B_PIPE4 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE4", 38446 /* IDB_OBM3_DBG_B_PIPE5 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE5", 38447 /* IDB_OBM3_DBG_B_PIPE6 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE6", 38448 /* IDB_OBM3_DBG_B_PIPE7 */ "IDB_OBM3_LAG_DETECTION_CONFIG_PIPE7", 38449 /* IDB_OBM3_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 38450 /* IDB_OBM3_EXPRESS_ARRIVAL_PKT_COUNT */ "", 38451 /* IDB_OBM3_EXPRESS_BYTE_DROP_COUNT */ "", 38452 /* IDB_OBM3_EXPRESS_FLOW_CONTROL_CONFIG */ "", 38453 /* IDB_OBM3_EXPRESS_PKT_DROP_COUNT */ "", 38454 /* IDB_OBM3_FC_THRESHOLD */ "", 38455 /* IDB_OBM3_FC_THRESHOLD_0 */ "", 38456 /* IDB_OBM3_FC_THRESHOLD_1 */ "", 38457 /* IDB_OBM3_FC_THRESHOLD_1_PIPE0 */ "", 38458 /* IDB_OBM3_FC_THRESHOLD_1_PIPE1 */ "", 38459 /* IDB_OBM3_FC_THRESHOLD_1_PIPE2 */ "", 38460 /* IDB_OBM3_FC_THRESHOLD_1_PIPE3 */ "", 38461 /* IDB_OBM3_FC_THRESHOLD_1_PIPE4 */ "", 38462 /* IDB_OBM3_FC_THRESHOLD_1_PIPE5 */ "", 38463 /* IDB_OBM3_FC_THRESHOLD_1_PIPE6 */ "", 38464 /* IDB_OBM3_FC_THRESHOLD_1_PIPE7 */ "", 38465 /* IDB_OBM3_FC_THRESHOLD_PIPE0 */ "", 38466 /* IDB_OBM3_FC_THRESHOLD_PIPE1 */ "", 38467 /* IDB_OBM3_FC_THRESHOLD_PIPE2 */ "", 38468 /* IDB_OBM3_FC_THRESHOLD_PIPE3 */ "", 38469 /* IDB_OBM3_FC_THRESHOLD_PIPE4 */ "", 38470 /* IDB_OBM3_FC_THRESHOLD_PIPE5 */ "", 38471 /* IDB_OBM3_FC_THRESHOLD_PIPE6 */ "", 38472 /* IDB_OBM3_FC_THRESHOLD_PIPE7 */ "", 38473 /* IDB_OBM3_FLOW_CONTROL_CONFIG */ "", 38474 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE0 */ "", 38475 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE1 */ "", 38476 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE2 */ "", 38477 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE3 */ "", 38478 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE4 */ "", 38479 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE5 */ "", 38480 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE6 */ "", 38481 /* IDB_OBM3_FLOW_CONTROL_CONFIG_PIPE7 */ "", 38482 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT */ "", 38483 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 38484 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 38485 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 38486 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 38487 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE4 */ "", 38488 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE5 */ "", 38489 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE6 */ "", 38490 /* IDB_OBM3_FLOW_CONTROL_EVENT_COUNT_PIPE7 */ "", 38491 /* IDB_OBM3_FORCE_SAF_STATUS */ "", 38492 /* IDB_OBM3_FORCE_SAF_STATUS_PIPE0 */ "", 38493 /* IDB_OBM3_FORCE_SAF_STATUS_PIPE1 */ "", 38494 /* IDB_OBM3_HW_STATUS */ "IDB_OBM3_HW_STATUS", 38495 /* IDB_OBM3_HW_STATUS_PIPE0 */ "IDB_OBM3_HW_STATUS_PIPE0", 38496 /* IDB_OBM3_HW_STATUS_PIPE1 */ "IDB_OBM3_HW_STATUS_PIPE1", 38497 /* IDB_OBM3_HW_STATUS_PIPE2 */ "IDB_OBM3_HW_STATUS_PIPE2", 38498 /* IDB_OBM3_HW_STATUS_PIPE3 */ "IDB_OBM3_HW_STATUS_PIPE3", 38499 /* IDB_OBM3_HW_STATUS_PIPE4 */ "IDB_OBM3_HW_STATUS_PIPE4", 38500 /* IDB_OBM3_HW_STATUS_PIPE5 */ "IDB_OBM3_HW_STATUS_PIPE5", 38501 /* IDB_OBM3_HW_STATUS_PIPE6 */ "IDB_OBM3_HW_STATUS_PIPE6", 38502 /* IDB_OBM3_HW_STATUS_PIPE7 */ "IDB_OBM3_HW_STATUS_PIPE7", 38503 /* IDB_OBM3_INNER_TPID */ "", 38504 /* IDB_OBM3_INNER_TPID_PIPE0 */ "", 38505 /* IDB_OBM3_INNER_TPID_PIPE1 */ "", 38506 /* IDB_OBM3_INNER_TPID_PIPE2 */ "", 38507 /* IDB_OBM3_INNER_TPID_PIPE3 */ "", 38508 /* IDB_OBM3_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 38509 /* IDB_OBM3_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 38510 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT */ "", 38511 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 38512 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 38513 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 38514 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 38515 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE4 */ "", 38516 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE5 */ "", 38517 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE6 */ "", 38518 /* IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNT_PIPE7 */ "", 38519 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT */ "", 38520 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 38521 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 38522 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 38523 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 38524 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE4 */ "", 38525 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE5 */ "", 38526 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE6 */ "", 38527 /* IDB_OBM3_LOSSLESS0_PKT_DROP_COUNT_PIPE7 */ "", 38528 /* IDB_OBM3_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 38529 /* IDB_OBM3_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 38530 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT */ "", 38531 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 38532 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 38533 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 38534 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 38535 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE4 */ "", 38536 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE5 */ "", 38537 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE6 */ "", 38538 /* IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNT_PIPE7 */ "", 38539 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT */ "", 38540 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 38541 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 38542 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 38543 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 38544 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE4 */ "", 38545 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE5 */ "", 38546 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE6 */ "", 38547 /* IDB_OBM3_LOSSLESS1_PKT_DROP_COUNT_PIPE7 */ "", 38548 /* IDB_OBM3_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 38549 /* IDB_OBM3_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 38550 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT */ "", 38551 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 38552 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 38553 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 38554 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 38555 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE4 */ "", 38556 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE5 */ "", 38557 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE6 */ "", 38558 /* IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNT_PIPE7 */ "", 38559 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT */ "", 38560 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 38561 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 38562 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 38563 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 38564 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE4 */ "", 38565 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE5 */ "", 38566 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE6 */ "", 38567 /* IDB_OBM3_LOSSY_HI_PKT_DROP_COUNT_PIPE7 */ "", 38568 /* IDB_OBM3_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 38569 /* IDB_OBM3_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 38570 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT */ "", 38571 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 38572 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 38573 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 38574 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 38575 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE4 */ "", 38576 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE5 */ "", 38577 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE6 */ "", 38578 /* IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNT_PIPE7 */ "", 38579 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT */ "", 38580 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 38581 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 38582 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 38583 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 38584 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE4 */ "", 38585 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE5 */ "", 38586 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE6 */ "", 38587 /* IDB_OBM3_LOSSY_LO_PKT_DROP_COUNT_PIPE7 */ "", 38588 /* IDB_OBM3_MAX_USAGE */ "IDB_OBM3_MAX_USAGE", 38589 /* IDB_OBM3_MAX_USAGE_1 */ "IDB_OBM3_MAX_USAGE_1", 38590 /* IDB_OBM3_MAX_USAGE_2 */ "IDB_OBM3_MAX_USAGE_2", 38591 /* IDB_OBM3_MAX_USAGE_1_PIPE0 */ "IDB_OBM3_MAX_USAGE_1_PIPE0", 38592 /* IDB_OBM3_MAX_USAGE_1_PIPE1 */ "IDB_OBM3_MAX_USAGE_1_PIPE1", 38593 /* IDB_OBM3_MAX_USAGE_1_PIPE2 */ "IDB_OBM3_MAX_USAGE_1_PIPE2", 38594 /* IDB_OBM3_MAX_USAGE_1_PIPE3 */ "IDB_OBM3_MAX_USAGE_1_PIPE3", 38595 /* IDB_OBM3_MAX_USAGE_1_PIPE4 */ "IDB_OBM3_MAX_USAGE_1_PIPE4", 38596 /* IDB_OBM3_MAX_USAGE_1_PIPE5 */ "IDB_OBM3_MAX_USAGE_1_PIPE5", 38597 /* IDB_OBM3_MAX_USAGE_1_PIPE6 */ "IDB_OBM3_MAX_USAGE_1_PIPE6", 38598 /* IDB_OBM3_MAX_USAGE_1_PIPE7 */ "IDB_OBM3_MAX_USAGE_1_PIPE7", 38599 /* IDB_OBM3_MAX_USAGE_2_PIPE0 */ "IDB_OBM3_MAX_USAGE_2_PIPE0", 38600 /* IDB_OBM3_MAX_USAGE_2_PIPE1 */ "IDB_OBM3_MAX_USAGE_2_PIPE1", 38601 /* IDB_OBM3_MAX_USAGE_2_PIPE2 */ "IDB_OBM3_MAX_USAGE_2_PIPE2", 38602 /* IDB_OBM3_MAX_USAGE_2_PIPE3 */ "IDB_OBM3_MAX_USAGE_2_PIPE3", 38603 /* IDB_OBM3_MAX_USAGE_2_PIPE4 */ "IDB_OBM3_MAX_USAGE_2_PIPE4", 38604 /* IDB_OBM3_MAX_USAGE_2_PIPE5 */ "IDB_OBM3_MAX_USAGE_2_PIPE5", 38605 /* IDB_OBM3_MAX_USAGE_2_PIPE6 */ "IDB_OBM3_MAX_USAGE_2_PIPE6", 38606 /* IDB_OBM3_MAX_USAGE_2_PIPE7 */ "IDB_OBM3_MAX_USAGE_2_PIPE7", 38607 /* IDB_OBM3_MAX_USAGE_PIPE0 */ "IDB_OBM3_MAX_USAGE_PIPE0", 38608 /* IDB_OBM3_MAX_USAGE_PIPE1 */ "IDB_OBM3_MAX_USAGE_PIPE1", 38609 /* IDB_OBM3_MAX_USAGE_PIPE2 */ "IDB_OBM3_MAX_USAGE_PIPE2", 38610 /* IDB_OBM3_MAX_USAGE_PIPE3 */ "IDB_OBM3_MAX_USAGE_PIPE3", 38611 /* IDB_OBM3_MAX_USAGE_PIPE4 */ "IDB_OBM3_MAX_USAGE_PIPE4", 38612 /* IDB_OBM3_MAX_USAGE_PIPE5 */ "IDB_OBM3_MAX_USAGE_PIPE5", 38613 /* IDB_OBM3_MAX_USAGE_PIPE6 */ "IDB_OBM3_MAX_USAGE_PIPE6", 38614 /* IDB_OBM3_MAX_USAGE_PIPE7 */ "IDB_OBM3_MAX_USAGE_PIPE7", 38615 /* IDB_OBM3_MAX_USAGE_SELECT */ "", 38616 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE0 */ "", 38617 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE1 */ "", 38618 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE2 */ "", 38619 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE3 */ "", 38620 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE4 */ "", 38621 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE5 */ "", 38622 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE6 */ "", 38623 /* IDB_OBM3_MAX_USAGE_SELECT_PIPE7 */ "", 38624 /* IDB_OBM3_MONITOR_STATS_CONFIG */ "", 38625 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE0 */ "", 38626 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE1 */ "", 38627 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE2 */ "", 38628 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE3 */ "", 38629 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE4 */ "", 38630 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE5 */ "", 38631 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE6 */ "", 38632 /* IDB_OBM3_MONITOR_STATS_CONFIG_PIPE7 */ "", 38633 /* IDB_OBM3_NIV_ETHERTYPE */ "", 38634 /* IDB_OBM3_NIV_ETHERTYPE_PIPE0 */ "", 38635 /* IDB_OBM3_NIV_ETHERTYPE_PIPE1 */ "", 38636 /* IDB_OBM3_NIV_ETHERTYPE_PIPE2 */ "", 38637 /* IDB_OBM3_NIV_ETHERTYPE_PIPE3 */ "", 38638 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0 */ "", 38639 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1 */ "", 38640 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE0 */ "", 38641 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE1 */ "", 38642 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE2 */ "", 38643 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE3 */ "", 38644 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE4 */ "", 38645 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE5 */ "", 38646 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE6 */ "", 38647 /* IDB_OBM3_OPAQUE_TAG_CONFIG_0_PIPE7 */ "", 38648 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE0 */ "", 38649 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE1 */ "", 38650 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE2 */ "", 38651 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE3 */ "", 38652 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE4 */ "", 38653 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE5 */ "", 38654 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE6 */ "", 38655 /* IDB_OBM3_OPAQUE_TAG_CONFIG_1_PIPE7 */ "", 38656 /* IDB_OBM3_OUTER_TPID */ "", 38657 /* IDB_OBM3_OUTER_TPID_0 */ "", 38658 /* IDB_OBM3_OUTER_TPID_1 */ "", 38659 /* IDB_OBM3_OUTER_TPID_2 */ "", 38660 /* IDB_OBM3_OUTER_TPID_3 */ "", 38661 /* IDB_OBM3_OUTER_TPID_0_PIPE0 */ "", 38662 /* IDB_OBM3_OUTER_TPID_0_PIPE1 */ "", 38663 /* IDB_OBM3_OUTER_TPID_0_PIPE2 */ "", 38664 /* IDB_OBM3_OUTER_TPID_0_PIPE3 */ "", 38665 /* IDB_OBM3_OUTER_TPID_0_PIPE4 */ "", 38666 /* IDB_OBM3_OUTER_TPID_0_PIPE5 */ "", 38667 /* IDB_OBM3_OUTER_TPID_0_PIPE6 */ "", 38668 /* IDB_OBM3_OUTER_TPID_0_PIPE7 */ "", 38669 /* IDB_OBM3_OUTER_TPID_1_PIPE0 */ "", 38670 /* IDB_OBM3_OUTER_TPID_1_PIPE1 */ "", 38671 /* IDB_OBM3_OUTER_TPID_1_PIPE2 */ "", 38672 /* IDB_OBM3_OUTER_TPID_1_PIPE3 */ "", 38673 /* IDB_OBM3_OUTER_TPID_1_PIPE4 */ "", 38674 /* IDB_OBM3_OUTER_TPID_1_PIPE5 */ "", 38675 /* IDB_OBM3_OUTER_TPID_1_PIPE6 */ "", 38676 /* IDB_OBM3_OUTER_TPID_1_PIPE7 */ "", 38677 /* IDB_OBM3_OUTER_TPID_2_PIPE0 */ "", 38678 /* IDB_OBM3_OUTER_TPID_2_PIPE1 */ "", 38679 /* IDB_OBM3_OUTER_TPID_2_PIPE2 */ "", 38680 /* IDB_OBM3_OUTER_TPID_2_PIPE3 */ "", 38681 /* IDB_OBM3_OUTER_TPID_2_PIPE4 */ "", 38682 /* IDB_OBM3_OUTER_TPID_2_PIPE5 */ "", 38683 /* IDB_OBM3_OUTER_TPID_2_PIPE6 */ "", 38684 /* IDB_OBM3_OUTER_TPID_2_PIPE7 */ "", 38685 /* IDB_OBM3_OUTER_TPID_3_PIPE0 */ "", 38686 /* IDB_OBM3_OUTER_TPID_3_PIPE1 */ "", 38687 /* IDB_OBM3_OUTER_TPID_3_PIPE2 */ "", 38688 /* IDB_OBM3_OUTER_TPID_3_PIPE3 */ "", 38689 /* IDB_OBM3_OUTER_TPID_3_PIPE4 */ "", 38690 /* IDB_OBM3_OUTER_TPID_3_PIPE5 */ "", 38691 /* IDB_OBM3_OUTER_TPID_3_PIPE6 */ "", 38692 /* IDB_OBM3_OUTER_TPID_3_PIPE7 */ "", 38693 /* IDB_OBM3_OUTER_TPID_PIPE0 */ "", 38694 /* IDB_OBM3_OUTER_TPID_PIPE1 */ "", 38695 /* IDB_OBM3_OUTER_TPID_PIPE2 */ "", 38696 /* IDB_OBM3_OUTER_TPID_PIPE3 */ "", 38697 /* IDB_OBM3_OUTER_TPID_PIPE4 */ "", 38698 /* IDB_OBM3_OUTER_TPID_PIPE5 */ "", 38699 /* IDB_OBM3_OUTER_TPID_PIPE6 */ "", 38700 /* IDB_OBM3_OUTER_TPID_PIPE7 */ "", 38701 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS", 38702 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE0", 38703 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE1", 38704 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE2", 38705 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE3", 38706 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE4 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE4", 38707 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE5 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE5", 38708 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE6 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE6", 38709 /* IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE7 */ "IDB_OBM3_OVERSUB_MON_ECC_STATUS_PIPE7", 38710 /* IDB_OBM3_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM3_OVERSUB_MON_PARITY_STATUS", 38711 /* IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE0", 38712 /* IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE1", 38713 /* IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE2", 38714 /* IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM3_OVERSUB_MON_PARITY_STATUS_PIPE3", 38715 /* IDB_OBM3_PE_ETHERTYPE */ "", 38716 /* IDB_OBM3_PE_ETHERTYPE_PIPE0 */ "", 38717 /* IDB_OBM3_PE_ETHERTYPE_PIPE1 */ "", 38718 /* IDB_OBM3_PE_ETHERTYPE_PIPE2 */ "", 38719 /* IDB_OBM3_PE_ETHERTYPE_PIPE3 */ "", 38720 /* IDB_OBM3_PORT_CONFIG */ "", 38721 /* IDB_OBM3_PORT_CONFIG_PIPE0 */ "", 38722 /* IDB_OBM3_PORT_CONFIG_PIPE1 */ "", 38723 /* IDB_OBM3_PORT_CONFIG_PIPE2 */ "", 38724 /* IDB_OBM3_PORT_CONFIG_PIPE3 */ "", 38725 /* IDB_OBM3_PORT_CONFIG_PIPE4 */ "", 38726 /* IDB_OBM3_PORT_CONFIG_PIPE5 */ "", 38727 /* IDB_OBM3_PORT_CONFIG_PIPE6 */ "", 38728 /* IDB_OBM3_PORT_CONFIG_PIPE7 */ "", 38729 /* IDB_OBM3_POWER_SAVE */ "IDB_OBM3_POWER_SAVE", 38730 /* IDB_OBM3_PROTOCOL_CONTROL_0 */ "", 38731 /* IDB_OBM3_PROTOCOL_CONTROL_1 */ "", 38732 /* IDB_OBM3_PROTOCOL_CONTROL_2 */ "", 38733 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE0 */ "", 38734 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE1 */ "", 38735 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE2 */ "", 38736 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE3 */ "", 38737 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE4 */ "", 38738 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE5 */ "", 38739 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE6 */ "", 38740 /* IDB_OBM3_PROTOCOL_CONTROL_0_PIPE7 */ "", 38741 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE0 */ "", 38742 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE1 */ "", 38743 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE2 */ "", 38744 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE3 */ "", 38745 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE4 */ "", 38746 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE5 */ "", 38747 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE6 */ "", 38748 /* IDB_OBM3_PROTOCOL_CONTROL_1_PIPE7 */ "", 38749 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE0 */ "", 38750 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE1 */ "", 38751 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE2 */ "", 38752 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE3 */ "", 38753 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE4 */ "", 38754 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE5 */ "", 38755 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE6 */ "", 38756 /* IDB_OBM3_PROTOCOL_CONTROL_2_PIPE7 */ "", 38757 /* IDB_OBM3_QUEUE_ECC_STATUS */ "IDB_OBM3_QUEUE_ECC_STATUS", 38758 /* IDB_OBM3_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM3_QUEUE_ECC_STATUS_PIPE0", 38759 /* IDB_OBM3_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM3_QUEUE_ECC_STATUS_PIPE1", 38760 /* IDB_OBM3_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM3_QUEUE_ECC_STATUS_PIPE2", 38761 /* IDB_OBM3_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM3_QUEUE_ECC_STATUS_PIPE3", 38762 /* IDB_OBM3_QUEUE_SER_CONTROL */ "IDB_OBM3_QUEUE_SER_CONTROL", 38763 /* IDB_OBM3_RAM_CONTROL */ "IDB_OBM3_RAM_CONTROL", 38764 /* IDB_OBM3_RAM_CONTROL_PIPE0 */ "IDB_OBM3_RAM_CONTROL_PIPE0", 38765 /* IDB_OBM3_RAM_CONTROL_PIPE1 */ "IDB_OBM3_RAM_CONTROL_PIPE1", 38766 /* IDB_OBM3_RAM_CONTROL_PIPE2 */ "IDB_OBM3_RAM_CONTROL_PIPE2", 38767 /* IDB_OBM3_RAM_CONTROL_PIPE3 */ "IDB_OBM3_RAM_CONTROL_PIPE3", 38768 /* IDB_OBM3_RAM_CONTROL_PIPE4 */ "IDB_OBM3_RAM_CONTROL_PIPE4", 38769 /* IDB_OBM3_RAM_CONTROL_PIPE5 */ "IDB_OBM3_RAM_CONTROL_PIPE5", 38770 /* IDB_OBM3_RAM_CONTROL_PIPE6 */ "IDB_OBM3_RAM_CONTROL_PIPE6", 38771 /* IDB_OBM3_RAM_CONTROL_PIPE7 */ "IDB_OBM3_RAM_CONTROL_PIPE7", 38772 /* IDB_OBM3_SER_CONTROL */ "IDB_OBM3_SER_CONTROL", 38773 /* IDB_OBM3_SER_CONTROL_PIPE0 */ "IDB_OBM3_SER_CONTROL_PIPE0", 38774 /* IDB_OBM3_SER_CONTROL_PIPE1 */ "IDB_OBM3_SER_CONTROL_PIPE1", 38775 /* IDB_OBM3_SHARED_CONFIG */ "IDB_OBM3_SHARED_CONFIG", 38776 /* IDB_OBM3_SHARED_CONFIG_PIPE0 */ "IDB_OBM3_SHARED_CONFIG_PIPE0", 38777 /* IDB_OBM3_SHARED_CONFIG_PIPE1 */ "IDB_OBM3_SHARED_CONFIG_PIPE1", 38778 /* IDB_OBM3_SHARED_CONFIG_PIPE2 */ "IDB_OBM3_SHARED_CONFIG_PIPE2", 38779 /* IDB_OBM3_SHARED_CONFIG_PIPE3 */ "IDB_OBM3_SHARED_CONFIG_PIPE3", 38780 /* IDB_OBM3_SHARED_CONFIG_PIPE4 */ "IDB_OBM3_SHARED_CONFIG_PIPE4", 38781 /* IDB_OBM3_SHARED_CONFIG_PIPE5 */ "IDB_OBM3_SHARED_CONFIG_PIPE5", 38782 /* IDB_OBM3_SHARED_CONFIG_PIPE6 */ "IDB_OBM3_SHARED_CONFIG_PIPE6", 38783 /* IDB_OBM3_SHARED_CONFIG_PIPE7 */ "IDB_OBM3_SHARED_CONFIG_PIPE7", 38784 /* IDB_OBM3_SHARED_USAGE */ "IDB_OBM3_SHARED_USAGE", 38785 /* IDB_OBM3_SHARED_USAGE_PIPE0 */ "IDB_OBM3_SHARED_USAGE_PIPE0", 38786 /* IDB_OBM3_SHARED_USAGE_PIPE1 */ "IDB_OBM3_SHARED_USAGE_PIPE1", 38787 /* IDB_OBM3_SHARED_USAGE_PIPE2 */ "IDB_OBM3_SHARED_USAGE_PIPE2", 38788 /* IDB_OBM3_SHARED_USAGE_PIPE3 */ "IDB_OBM3_SHARED_USAGE_PIPE3", 38789 /* IDB_OBM3_SPARE_REG */ "IDB_OBM3_SPARE_REG", 38790 /* IDB_OBM3_TDM */ "IDB_OBM3_TDM", 38791 /* IDB_OBM3_TDM_PIPE0 */ "IDB_OBM3_TDM_PIPE0", 38792 /* IDB_OBM3_TDM_PIPE1 */ "IDB_OBM3_TDM_PIPE1", 38793 /* IDB_OBM3_TDM_PIPE2 */ "IDB_OBM3_TDM_PIPE2", 38794 /* IDB_OBM3_TDM_PIPE3 */ "IDB_OBM3_TDM_PIPE3", 38795 /* IDB_OBM3_TDM_PIPE4 */ "IDB_OBM3_TDM_PIPE4", 38796 /* IDB_OBM3_TDM_PIPE5 */ "IDB_OBM3_TDM_PIPE5", 38797 /* IDB_OBM3_TDM_PIPE6 */ "IDB_OBM3_TDM_PIPE6", 38798 /* IDB_OBM3_TDM_PIPE7 */ "IDB_OBM3_TDM_PIPE7", 38799 /* IDB_OBM3_THRESHOLD */ "", 38800 /* IDB_OBM3_THRESHOLD_0 */ "", 38801 /* IDB_OBM3_THRESHOLD_1 */ "", 38802 /* IDB_OBM3_THRESHOLD_1_PIPE0 */ "", 38803 /* IDB_OBM3_THRESHOLD_1_PIPE1 */ "", 38804 /* IDB_OBM3_THRESHOLD_1_PIPE2 */ "", 38805 /* IDB_OBM3_THRESHOLD_1_PIPE3 */ "", 38806 /* IDB_OBM3_THRESHOLD_1_PIPE4 */ "", 38807 /* IDB_OBM3_THRESHOLD_1_PIPE5 */ "", 38808 /* IDB_OBM3_THRESHOLD_1_PIPE6 */ "", 38809 /* IDB_OBM3_THRESHOLD_1_PIPE7 */ "", 38810 /* IDB_OBM3_THRESHOLD_PIPE0 */ "", 38811 /* IDB_OBM3_THRESHOLD_PIPE1 */ "", 38812 /* IDB_OBM3_THRESHOLD_PIPE2 */ "", 38813 /* IDB_OBM3_THRESHOLD_PIPE3 */ "", 38814 /* IDB_OBM3_THRESHOLD_PIPE4 */ "", 38815 /* IDB_OBM3_THRESHOLD_PIPE5 */ "", 38816 /* IDB_OBM3_THRESHOLD_PIPE6 */ "", 38817 /* IDB_OBM3_THRESHOLD_PIPE7 */ "", 38818 /* IDB_OBM3_USAGE */ "", 38819 /* IDB_OBM3_USAGE_1 */ "", 38820 /* IDB_OBM3_USAGE_1_PIPE0 */ "", 38821 /* IDB_OBM3_USAGE_1_PIPE1 */ "", 38822 /* IDB_OBM3_USAGE_1_PIPE2 */ "", 38823 /* IDB_OBM3_USAGE_1_PIPE3 */ "", 38824 /* IDB_OBM3_USAGE_1_PIPE4 */ "", 38825 /* IDB_OBM3_USAGE_1_PIPE5 */ "", 38826 /* IDB_OBM3_USAGE_1_PIPE6 */ "", 38827 /* IDB_OBM3_USAGE_1_PIPE7 */ "", 38828 /* IDB_OBM3_USAGE_PIPE0 */ "", 38829 /* IDB_OBM3_USAGE_PIPE1 */ "", 38830 /* IDB_OBM3_USAGE_PIPE2 */ "", 38831 /* IDB_OBM3_USAGE_PIPE3 */ "", 38832 /* IDB_OBM3_USAGE_PIPE4 */ "", 38833 /* IDB_OBM3_USAGE_PIPE5 */ "", 38834 /* IDB_OBM3_USAGE_PIPE6 */ "", 38835 /* IDB_OBM3_USAGE_PIPE7 */ "", 38836 /* IDB_OBM4_BANK_CONFIG */ "IDB_OBM4_BANK_CONFIG", 38837 /* IDB_OBM4_BANK_CONFIG_PIPE0 */ "IDB_OBM4_BANK_CONFIG_PIPE0", 38838 /* IDB_OBM4_BANK_CONFIG_PIPE1 */ "IDB_OBM4_BANK_CONFIG_PIPE1", 38839 /* IDB_OBM4_BANK_CONFIG_PIPE2 */ "IDB_OBM4_BANK_CONFIG_PIPE2", 38840 /* IDB_OBM4_BANK_CONFIG_PIPE3 */ "IDB_OBM4_BANK_CONFIG_PIPE3", 38841 /* IDB_OBM4_BUCKET_COUNT_CONFIG */ "", 38842 /* IDB_OBM4_BUFFER_CONFIG */ "", 38843 /* IDB_OBM4_BUFFER_CONFIG_PIPE0 */ "", 38844 /* IDB_OBM4_BUFFER_CONFIG_PIPE1 */ "", 38845 /* IDB_OBM4_CA_CONTROL */ "IDB_OBM4_CA_CONTROL", 38846 /* IDB_OBM4_CA_CONTROL_PIPE0 */ "IDB_OBM4_CA_CONTROL_PIPE0", 38847 /* IDB_OBM4_CA_CONTROL_PIPE1 */ "IDB_OBM4_CA_CONTROL_PIPE1", 38848 /* IDB_OBM4_CA_CONTROL_PIPE2 */ "IDB_OBM4_CA_CONTROL_PIPE2", 38849 /* IDB_OBM4_CA_CONTROL_PIPE3 */ "IDB_OBM4_CA_CONTROL_PIPE3", 38850 /* IDB_OBM4_CA_CT_CONTROL */ "IDB_OBM4_CA_CT_CONTROL", 38851 /* IDB_OBM4_CA_CT_CONTROL_PIPE0 */ "IDB_OBM4_CA_CT_CONTROL_PIPE0", 38852 /* IDB_OBM4_CA_CT_CONTROL_PIPE1 */ "IDB_OBM4_CA_CT_CONTROL_PIPE1", 38853 /* IDB_OBM4_CA_CT_CONTROL_PIPE2 */ "IDB_OBM4_CA_CT_CONTROL_PIPE2", 38854 /* IDB_OBM4_CA_CT_CONTROL_PIPE3 */ "IDB_OBM4_CA_CT_CONTROL_PIPE3", 38855 /* IDB_OBM4_CA_ECC_STATUS */ "IDB_OBM4_CA_ECC_STATUS", 38856 /* IDB_OBM4_CA_ECC_STATUS_PIPE0 */ "IDB_OBM4_CA_ECC_STATUS_PIPE0", 38857 /* IDB_OBM4_CA_ECC_STATUS_PIPE1 */ "IDB_OBM4_CA_ECC_STATUS_PIPE1", 38858 /* IDB_OBM4_CA_ECC_STATUS_PIPE2 */ "IDB_OBM4_CA_ECC_STATUS_PIPE2", 38859 /* IDB_OBM4_CA_ECC_STATUS_PIPE3 */ "IDB_OBM4_CA_ECC_STATUS_PIPE3", 38860 /* IDB_OBM4_CA_HW_CONTROL */ "IDB_OBM4_CA_HW_CONTROL", 38861 /* IDB_OBM4_CA_HW_CONTROL_PIPE0 */ "IDB_OBM4_CA_HW_CONTROL_PIPE0", 38862 /* IDB_OBM4_CA_HW_CONTROL_PIPE1 */ "IDB_OBM4_CA_HW_CONTROL_PIPE1", 38863 /* IDB_OBM4_CA_HW_CONTROL_PIPE2 */ "IDB_OBM4_CA_HW_CONTROL_PIPE2", 38864 /* IDB_OBM4_CA_HW_CONTROL_PIPE3 */ "IDB_OBM4_CA_HW_CONTROL_PIPE3", 38865 /* IDB_OBM4_CA_HW_STATUS */ "IDB_OBM4_CA_HW_STATUS", 38866 /* IDB_OBM4_CA_HW_STATUS_PIPE0 */ "IDB_OBM4_CA_HW_STATUS_PIPE0", 38867 /* IDB_OBM4_CA_HW_STATUS_PIPE1 */ "IDB_OBM4_CA_HW_STATUS_PIPE1", 38868 /* IDB_OBM4_CA_HW_STATUS_PIPE2 */ "IDB_OBM4_CA_HW_STATUS_PIPE2", 38869 /* IDB_OBM4_CA_HW_STATUS_PIPE3 */ "IDB_OBM4_CA_HW_STATUS_PIPE3", 38870 /* IDB_OBM4_CA_POINTER_STATUS */ "IDB_OBM4_CA_POINTER_STATUS", 38871 /* IDB_OBM4_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM4_CA_POINTER_STATUS_PIPE0", 38872 /* IDB_OBM4_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM4_CA_POINTER_STATUS_PIPE1", 38873 /* IDB_OBM4_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM4_CA_POINTER_STATUS_PIPE2", 38874 /* IDB_OBM4_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM4_CA_POINTER_STATUS_PIPE3", 38875 /* IDB_OBM4_CONTROL */ "IDB_OBM4_CONTROL", 38876 /* IDB_OBM4_CONTROL_PIPE0 */ "IDB_OBM4_CONTROL_PIPE0", 38877 /* IDB_OBM4_CONTROL_PIPE1 */ "IDB_OBM4_CONTROL_PIPE1", 38878 /* IDB_OBM4_CONTROL_PIPE2 */ "IDB_OBM4_CONTROL_PIPE2", 38879 /* IDB_OBM4_CONTROL_PIPE3 */ "IDB_OBM4_CONTROL_PIPE3", 38880 /* IDB_OBM4_CT_THRESHOLD */ "", 38881 /* IDB_OBM4_CT_THRESHOLD_PIPE0 */ "", 38882 /* IDB_OBM4_CT_THRESHOLD_PIPE1 */ "", 38883 /* IDB_OBM4_CT_THRESHOLD_PIPE2 */ "", 38884 /* IDB_OBM4_CT_THRESHOLD_PIPE3 */ "", 38885 /* IDB_OBM4_DATA_ECC_STATUS */ "IDB_OBM4_DATA_ECC_STATUS", 38886 /* IDB_OBM4_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM4_DATA_ECC_STATUS_PIPE0", 38887 /* IDB_OBM4_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM4_DATA_ECC_STATUS_PIPE1", 38888 /* IDB_OBM4_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM4_DATA_ECC_STATUS_PIPE2", 38889 /* IDB_OBM4_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM4_DATA_ECC_STATUS_PIPE3", 38890 /* IDB_OBM4_DBG_A */ "IDB_OBM4_FORCE_SAF_CONFIG", 38891 /* IDB_OBM4_DBG_A_PIPE0 */ "IDB_OBM4_FORCE_SAF_CONFIG_PIPE0", 38892 /* IDB_OBM4_DBG_A_PIPE1 */ "IDB_OBM4_FORCE_SAF_CONFIG_PIPE1", 38893 /* IDB_OBM4_DBG_A_PIPE2 */ "IDB_OBM4_FORCE_SAF_CONFIG_PIPE2", 38894 /* IDB_OBM4_DBG_A_PIPE3 */ "IDB_OBM4_FORCE_SAF_CONFIG_PIPE3", 38895 /* IDB_OBM4_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 38896 /* IDB_OBM4_EXPRESS_ARRIVAL_PKT_COUNT */ "", 38897 /* IDB_OBM4_EXPRESS_BYTE_DROP_COUNT */ "", 38898 /* IDB_OBM4_EXPRESS_FLOW_CONTROL_CONFIG */ "", 38899 /* IDB_OBM4_EXPRESS_PKT_DROP_COUNT */ "", 38900 /* IDB_OBM4_FC_THRESHOLD */ "", 38901 /* IDB_OBM4_FC_THRESHOLD_0 */ "", 38902 /* IDB_OBM4_FC_THRESHOLD_1 */ "", 38903 /* IDB_OBM4_FC_THRESHOLD_1_PIPE0 */ "", 38904 /* IDB_OBM4_FC_THRESHOLD_1_PIPE1 */ "", 38905 /* IDB_OBM4_FC_THRESHOLD_1_PIPE2 */ "", 38906 /* IDB_OBM4_FC_THRESHOLD_1_PIPE3 */ "", 38907 /* IDB_OBM4_FC_THRESHOLD_PIPE0 */ "", 38908 /* IDB_OBM4_FC_THRESHOLD_PIPE1 */ "", 38909 /* IDB_OBM4_FC_THRESHOLD_PIPE2 */ "", 38910 /* IDB_OBM4_FC_THRESHOLD_PIPE3 */ "", 38911 /* IDB_OBM4_FLOW_CONTROL_CONFIG */ "", 38912 /* IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE0 */ "", 38913 /* IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE1 */ "", 38914 /* IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE2 */ "", 38915 /* IDB_OBM4_FLOW_CONTROL_CONFIG_PIPE3 */ "", 38916 /* IDB_OBM4_FLOW_CONTROL_EVENT_COUNT */ "", 38917 /* IDB_OBM4_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 38918 /* IDB_OBM4_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 38919 /* IDB_OBM4_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 38920 /* IDB_OBM4_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 38921 /* IDB_OBM4_FORCE_SAF_STATUS */ "", 38922 /* IDB_OBM4_FORCE_SAF_STATUS_PIPE0 */ "", 38923 /* IDB_OBM4_FORCE_SAF_STATUS_PIPE1 */ "", 38924 /* IDB_OBM4_INNER_TPID */ "", 38925 /* IDB_OBM4_INNER_TPID_PIPE0 */ "", 38926 /* IDB_OBM4_INNER_TPID_PIPE1 */ "", 38927 /* IDB_OBM4_INNER_TPID_PIPE2 */ "", 38928 /* IDB_OBM4_INNER_TPID_PIPE3 */ "", 38929 /* IDB_OBM4_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 38930 /* IDB_OBM4_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 38931 /* IDB_OBM4_LOSSLESS0_BYTE_DROP_COUNT */ "", 38932 /* IDB_OBM4_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 38933 /* IDB_OBM4_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 38934 /* IDB_OBM4_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 38935 /* IDB_OBM4_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 38936 /* IDB_OBM4_LOSSLESS0_PKT_DROP_COUNT */ "", 38937 /* IDB_OBM4_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 38938 /* IDB_OBM4_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 38939 /* IDB_OBM4_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 38940 /* IDB_OBM4_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 38941 /* IDB_OBM4_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 38942 /* IDB_OBM4_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 38943 /* IDB_OBM4_LOSSLESS1_BYTE_DROP_COUNT */ "", 38944 /* IDB_OBM4_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 38945 /* IDB_OBM4_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 38946 /* IDB_OBM4_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 38947 /* IDB_OBM4_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 38948 /* IDB_OBM4_LOSSLESS1_PKT_DROP_COUNT */ "", 38949 /* IDB_OBM4_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 38950 /* IDB_OBM4_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 38951 /* IDB_OBM4_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 38952 /* IDB_OBM4_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 38953 /* IDB_OBM4_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 38954 /* IDB_OBM4_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 38955 /* IDB_OBM4_LOSSY_HI_BYTE_DROP_COUNT */ "", 38956 /* IDB_OBM4_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 38957 /* IDB_OBM4_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 38958 /* IDB_OBM4_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 38959 /* IDB_OBM4_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 38960 /* IDB_OBM4_LOSSY_HI_PKT_DROP_COUNT */ "", 38961 /* IDB_OBM4_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 38962 /* IDB_OBM4_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 38963 /* IDB_OBM4_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 38964 /* IDB_OBM4_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 38965 /* IDB_OBM4_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 38966 /* IDB_OBM4_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 38967 /* IDB_OBM4_LOSSY_LO_BYTE_DROP_COUNT */ "", 38968 /* IDB_OBM4_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 38969 /* IDB_OBM4_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 38970 /* IDB_OBM4_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 38971 /* IDB_OBM4_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 38972 /* IDB_OBM4_LOSSY_LO_PKT_DROP_COUNT */ "", 38973 /* IDB_OBM4_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 38974 /* IDB_OBM4_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 38975 /* IDB_OBM4_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 38976 /* IDB_OBM4_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 38977 /* IDB_OBM4_MAX_USAGE */ "IDB_OBM4_MAX_USAGE", 38978 /* IDB_OBM4_MAX_USAGE_1 */ "IDB_OBM4_MAX_USAGE_1", 38979 /* IDB_OBM4_MAX_USAGE_1_PIPE0 */ "IDB_OBM4_MAX_USAGE_1_PIPE0", 38980 /* IDB_OBM4_MAX_USAGE_1_PIPE1 */ "IDB_OBM4_MAX_USAGE_1_PIPE1", 38981 /* IDB_OBM4_MAX_USAGE_1_PIPE2 */ "IDB_OBM4_MAX_USAGE_1_PIPE2", 38982 /* IDB_OBM4_MAX_USAGE_1_PIPE3 */ "IDB_OBM4_MAX_USAGE_1_PIPE3", 38983 /* IDB_OBM4_MAX_USAGE_PIPE0 */ "IDB_OBM4_MAX_USAGE_PIPE0", 38984 /* IDB_OBM4_MAX_USAGE_PIPE1 */ "IDB_OBM4_MAX_USAGE_PIPE1", 38985 /* IDB_OBM4_MAX_USAGE_PIPE2 */ "IDB_OBM4_MAX_USAGE_PIPE2", 38986 /* IDB_OBM4_MAX_USAGE_PIPE3 */ "IDB_OBM4_MAX_USAGE_PIPE3", 38987 /* IDB_OBM4_MAX_USAGE_SELECT */ "", 38988 /* IDB_OBM4_MAX_USAGE_SELECT_PIPE0 */ "", 38989 /* IDB_OBM4_MAX_USAGE_SELECT_PIPE1 */ "", 38990 /* IDB_OBM4_MAX_USAGE_SELECT_PIPE2 */ "", 38991 /* IDB_OBM4_MAX_USAGE_SELECT_PIPE3 */ "", 38992 /* IDB_OBM4_MONITOR_STATS_CONFIG */ "", 38993 /* IDB_OBM4_NIV_ETHERTYPE */ "", 38994 /* IDB_OBM4_NIV_ETHERTYPE_PIPE0 */ "", 38995 /* IDB_OBM4_NIV_ETHERTYPE_PIPE1 */ "", 38996 /* IDB_OBM4_NIV_ETHERTYPE_PIPE2 */ "", 38997 /* IDB_OBM4_NIV_ETHERTYPE_PIPE3 */ "", 38998 /* IDB_OBM4_OUTER_TPID */ "", 38999 /* IDB_OBM4_OUTER_TPID_0 */ "", 39000 /* IDB_OBM4_OUTER_TPID_1 */ "", 39001 /* IDB_OBM4_OUTER_TPID_2 */ "", 39002 /* IDB_OBM4_OUTER_TPID_3 */ "", 39003 /* IDB_OBM4_OUTER_TPID_0_PIPE0 */ "", 39004 /* IDB_OBM4_OUTER_TPID_0_PIPE1 */ "", 39005 /* IDB_OBM4_OUTER_TPID_0_PIPE2 */ "", 39006 /* IDB_OBM4_OUTER_TPID_0_PIPE3 */ "", 39007 /* IDB_OBM4_OUTER_TPID_1_PIPE0 */ "", 39008 /* IDB_OBM4_OUTER_TPID_1_PIPE1 */ "", 39009 /* IDB_OBM4_OUTER_TPID_1_PIPE2 */ "", 39010 /* IDB_OBM4_OUTER_TPID_1_PIPE3 */ "", 39011 /* IDB_OBM4_OUTER_TPID_2_PIPE0 */ "", 39012 /* IDB_OBM4_OUTER_TPID_2_PIPE1 */ "", 39013 /* IDB_OBM4_OUTER_TPID_2_PIPE2 */ "", 39014 /* IDB_OBM4_OUTER_TPID_2_PIPE3 */ "", 39015 /* IDB_OBM4_OUTER_TPID_3_PIPE0 */ "", 39016 /* IDB_OBM4_OUTER_TPID_3_PIPE1 */ "", 39017 /* IDB_OBM4_OUTER_TPID_3_PIPE2 */ "", 39018 /* IDB_OBM4_OUTER_TPID_3_PIPE3 */ "", 39019 /* IDB_OBM4_OUTER_TPID_PIPE0 */ "", 39020 /* IDB_OBM4_OUTER_TPID_PIPE1 */ "", 39021 /* IDB_OBM4_OUTER_TPID_PIPE2 */ "", 39022 /* IDB_OBM4_OUTER_TPID_PIPE3 */ "", 39023 /* IDB_OBM4_OVERSUB_MON_ECC_STATUS */ "IDB_OBM4_OVERSUB_MON_ECC_STATUS", 39024 /* IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE0", 39025 /* IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE1", 39026 /* IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE2", 39027 /* IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM4_OVERSUB_MON_ECC_STATUS_PIPE3", 39028 /* IDB_OBM4_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM4_OVERSUB_MON_PARITY_STATUS", 39029 /* IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE0", 39030 /* IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE1", 39031 /* IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE2", 39032 /* IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM4_OVERSUB_MON_PARITY_STATUS_PIPE3", 39033 /* IDB_OBM4_PE_ETHERTYPE */ "", 39034 /* IDB_OBM4_PE_ETHERTYPE_PIPE0 */ "", 39035 /* IDB_OBM4_PE_ETHERTYPE_PIPE1 */ "", 39036 /* IDB_OBM4_PE_ETHERTYPE_PIPE2 */ "", 39037 /* IDB_OBM4_PE_ETHERTYPE_PIPE3 */ "", 39038 /* IDB_OBM4_PORT_CONFIG */ "", 39039 /* IDB_OBM4_PORT_CONFIG_PIPE0 */ "", 39040 /* IDB_OBM4_PORT_CONFIG_PIPE1 */ "", 39041 /* IDB_OBM4_PORT_CONFIG_PIPE2 */ "", 39042 /* IDB_OBM4_PORT_CONFIG_PIPE3 */ "", 39043 /* IDB_OBM4_POWER_SAVE */ "IDB_OBM4_POWER_SAVE", 39044 /* IDB_OBM4_PROTOCOL_CONTROL_0 */ "", 39045 /* IDB_OBM4_PROTOCOL_CONTROL_1 */ "", 39046 /* IDB_OBM4_PROTOCOL_CONTROL_2 */ "", 39047 /* IDB_OBM4_PROTOCOL_CONTROL_0_PIPE0 */ "", 39048 /* IDB_OBM4_PROTOCOL_CONTROL_0_PIPE1 */ "", 39049 /* IDB_OBM4_PROTOCOL_CONTROL_0_PIPE2 */ "", 39050 /* IDB_OBM4_PROTOCOL_CONTROL_0_PIPE3 */ "", 39051 /* IDB_OBM4_PROTOCOL_CONTROL_1_PIPE0 */ "", 39052 /* IDB_OBM4_PROTOCOL_CONTROL_1_PIPE1 */ "", 39053 /* IDB_OBM4_PROTOCOL_CONTROL_1_PIPE2 */ "", 39054 /* IDB_OBM4_PROTOCOL_CONTROL_1_PIPE3 */ "", 39055 /* IDB_OBM4_PROTOCOL_CONTROL_2_PIPE0 */ "", 39056 /* IDB_OBM4_PROTOCOL_CONTROL_2_PIPE1 */ "", 39057 /* IDB_OBM4_PROTOCOL_CONTROL_2_PIPE2 */ "", 39058 /* IDB_OBM4_PROTOCOL_CONTROL_2_PIPE3 */ "", 39059 /* IDB_OBM4_QUEUE_ECC_STATUS */ "IDB_OBM4_QUEUE_ECC_STATUS", 39060 /* IDB_OBM4_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM4_QUEUE_ECC_STATUS_PIPE0", 39061 /* IDB_OBM4_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM4_QUEUE_ECC_STATUS_PIPE1", 39062 /* IDB_OBM4_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM4_QUEUE_ECC_STATUS_PIPE2", 39063 /* IDB_OBM4_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM4_QUEUE_ECC_STATUS_PIPE3", 39064 /* IDB_OBM4_QUEUE_SER_CONTROL */ "IDB_OBM4_QUEUE_SER_CONTROL", 39065 /* IDB_OBM4_RAM_CONTROL */ "IDB_OBM4_RAM_CONTROL", 39066 /* IDB_OBM4_RAM_CONTROL_PIPE0 */ "IDB_OBM4_RAM_CONTROL_PIPE0", 39067 /* IDB_OBM4_RAM_CONTROL_PIPE1 */ "IDB_OBM4_RAM_CONTROL_PIPE1", 39068 /* IDB_OBM4_RAM_CONTROL_PIPE2 */ "IDB_OBM4_RAM_CONTROL_PIPE2", 39069 /* IDB_OBM4_RAM_CONTROL_PIPE3 */ "IDB_OBM4_RAM_CONTROL_PIPE3", 39070 /* IDB_OBM4_SER_CONTROL */ "IDB_OBM4_SER_CONTROL", 39071 /* IDB_OBM4_SER_CONTROL_PIPE0 */ "IDB_OBM4_SER_CONTROL_PIPE0", 39072 /* IDB_OBM4_SER_CONTROL_PIPE1 */ "IDB_OBM4_SER_CONTROL_PIPE1", 39073 /* IDB_OBM4_SHARED_CONFIG */ "IDB_OBM4_SHARED_CONFIG", 39074 /* IDB_OBM4_SHARED_CONFIG_PIPE0 */ "IDB_OBM4_SHARED_CONFIG_PIPE0", 39075 /* IDB_OBM4_SHARED_CONFIG_PIPE1 */ "IDB_OBM4_SHARED_CONFIG_PIPE1", 39076 /* IDB_OBM4_SHARED_CONFIG_PIPE2 */ "IDB_OBM4_SHARED_CONFIG_PIPE2", 39077 /* IDB_OBM4_SHARED_CONFIG_PIPE3 */ "IDB_OBM4_SHARED_CONFIG_PIPE3", 39078 /* IDB_OBM4_SHARED_USAGE */ "IDB_OBM4_SHARED_USAGE", 39079 /* IDB_OBM4_SHARED_USAGE_PIPE0 */ "IDB_OBM4_SHARED_USAGE_PIPE0", 39080 /* IDB_OBM4_SHARED_USAGE_PIPE1 */ "IDB_OBM4_SHARED_USAGE_PIPE1", 39081 /* IDB_OBM4_SHARED_USAGE_PIPE2 */ "IDB_OBM4_SHARED_USAGE_PIPE2", 39082 /* IDB_OBM4_SHARED_USAGE_PIPE3 */ "IDB_OBM4_SHARED_USAGE_PIPE3", 39083 /* IDB_OBM4_SPARE_REG */ "IDB_OBM4_SPARE_REG", 39084 /* IDB_OBM4_THRESHOLD */ "", 39085 /* IDB_OBM4_THRESHOLD_0 */ "", 39086 /* IDB_OBM4_THRESHOLD_1 */ "", 39087 /* IDB_OBM4_THRESHOLD_1_PIPE0 */ "", 39088 /* IDB_OBM4_THRESHOLD_1_PIPE1 */ "", 39089 /* IDB_OBM4_THRESHOLD_1_PIPE2 */ "", 39090 /* IDB_OBM4_THRESHOLD_1_PIPE3 */ "", 39091 /* IDB_OBM4_THRESHOLD_PIPE0 */ "", 39092 /* IDB_OBM4_THRESHOLD_PIPE1 */ "", 39093 /* IDB_OBM4_THRESHOLD_PIPE2 */ "", 39094 /* IDB_OBM4_THRESHOLD_PIPE3 */ "", 39095 /* IDB_OBM4_USAGE */ "", 39096 /* IDB_OBM4_USAGE_PIPE0 */ "", 39097 /* IDB_OBM4_USAGE_PIPE1 */ "", 39098 /* IDB_OBM4_USAGE_PIPE2 */ "", 39099 /* IDB_OBM4_USAGE_PIPE3 */ "", 39100 /* IDB_OBM5_BANK_CONFIG */ "IDB_OBM5_BANK_CONFIG", 39101 /* IDB_OBM5_BANK_CONFIG_PIPE0 */ "IDB_OBM5_BANK_CONFIG_PIPE0", 39102 /* IDB_OBM5_BANK_CONFIG_PIPE1 */ "IDB_OBM5_BANK_CONFIG_PIPE1", 39103 /* IDB_OBM5_BANK_CONFIG_PIPE2 */ "IDB_OBM5_BANK_CONFIG_PIPE2", 39104 /* IDB_OBM5_BANK_CONFIG_PIPE3 */ "IDB_OBM5_BANK_CONFIG_PIPE3", 39105 /* IDB_OBM5_BUCKET_COUNT_CONFIG */ "", 39106 /* IDB_OBM5_BUFFER_CONFIG */ "", 39107 /* IDB_OBM5_BUFFER_CONFIG_PIPE0 */ "", 39108 /* IDB_OBM5_BUFFER_CONFIG_PIPE1 */ "", 39109 /* IDB_OBM5_CA_CONTROL */ "IDB_OBM5_CA_CONTROL", 39110 /* IDB_OBM5_CA_CONTROL_PIPE0 */ "IDB_OBM5_CA_CONTROL_PIPE0", 39111 /* IDB_OBM5_CA_CONTROL_PIPE1 */ "IDB_OBM5_CA_CONTROL_PIPE1", 39112 /* IDB_OBM5_CA_CONTROL_PIPE2 */ "IDB_OBM5_CA_CONTROL_PIPE2", 39113 /* IDB_OBM5_CA_CONTROL_PIPE3 */ "IDB_OBM5_CA_CONTROL_PIPE3", 39114 /* IDB_OBM5_CA_CT_CONTROL */ "IDB_OBM5_CA_CT_CONTROL", 39115 /* IDB_OBM5_CA_CT_CONTROL_PIPE0 */ "IDB_OBM5_CA_CT_CONTROL_PIPE0", 39116 /* IDB_OBM5_CA_CT_CONTROL_PIPE1 */ "IDB_OBM5_CA_CT_CONTROL_PIPE1", 39117 /* IDB_OBM5_CA_CT_CONTROL_PIPE2 */ "IDB_OBM5_CA_CT_CONTROL_PIPE2", 39118 /* IDB_OBM5_CA_CT_CONTROL_PIPE3 */ "IDB_OBM5_CA_CT_CONTROL_PIPE3", 39119 /* IDB_OBM5_CA_ECC_STATUS */ "IDB_OBM5_CA_ECC_STATUS", 39120 /* IDB_OBM5_CA_ECC_STATUS_PIPE0 */ "IDB_OBM5_CA_ECC_STATUS_PIPE0", 39121 /* IDB_OBM5_CA_ECC_STATUS_PIPE1 */ "IDB_OBM5_CA_ECC_STATUS_PIPE1", 39122 /* IDB_OBM5_CA_ECC_STATUS_PIPE2 */ "IDB_OBM5_CA_ECC_STATUS_PIPE2", 39123 /* IDB_OBM5_CA_ECC_STATUS_PIPE3 */ "IDB_OBM5_CA_ECC_STATUS_PIPE3", 39124 /* IDB_OBM5_CA_HW_CONTROL */ "IDB_OBM5_CA_HW_CONTROL", 39125 /* IDB_OBM5_CA_HW_CONTROL_PIPE0 */ "IDB_OBM5_CA_HW_CONTROL_PIPE0", 39126 /* IDB_OBM5_CA_HW_CONTROL_PIPE1 */ "IDB_OBM5_CA_HW_CONTROL_PIPE1", 39127 /* IDB_OBM5_CA_HW_CONTROL_PIPE2 */ "IDB_OBM5_CA_HW_CONTROL_PIPE2", 39128 /* IDB_OBM5_CA_HW_CONTROL_PIPE3 */ "IDB_OBM5_CA_HW_CONTROL_PIPE3", 39129 /* IDB_OBM5_CA_HW_STATUS */ "IDB_OBM5_CA_HW_STATUS", 39130 /* IDB_OBM5_CA_HW_STATUS_PIPE0 */ "IDB_OBM5_CA_HW_STATUS_PIPE0", 39131 /* IDB_OBM5_CA_HW_STATUS_PIPE1 */ "IDB_OBM5_CA_HW_STATUS_PIPE1", 39132 /* IDB_OBM5_CA_HW_STATUS_PIPE2 */ "IDB_OBM5_CA_HW_STATUS_PIPE2", 39133 /* IDB_OBM5_CA_HW_STATUS_PIPE3 */ "IDB_OBM5_CA_HW_STATUS_PIPE3", 39134 /* IDB_OBM5_CA_POINTER_STATUS */ "IDB_OBM5_CA_POINTER_STATUS", 39135 /* IDB_OBM5_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM5_CA_POINTER_STATUS_PIPE0", 39136 /* IDB_OBM5_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM5_CA_POINTER_STATUS_PIPE1", 39137 /* IDB_OBM5_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM5_CA_POINTER_STATUS_PIPE2", 39138 /* IDB_OBM5_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM5_CA_POINTER_STATUS_PIPE3", 39139 /* IDB_OBM5_CONTROL */ "IDB_OBM5_CONTROL", 39140 /* IDB_OBM5_CONTROL_PIPE0 */ "IDB_OBM5_CONTROL_PIPE0", 39141 /* IDB_OBM5_CONTROL_PIPE1 */ "IDB_OBM5_CONTROL_PIPE1", 39142 /* IDB_OBM5_CONTROL_PIPE2 */ "IDB_OBM5_CONTROL_PIPE2", 39143 /* IDB_OBM5_CONTROL_PIPE3 */ "IDB_OBM5_CONTROL_PIPE3", 39144 /* IDB_OBM5_CT_THRESHOLD */ "", 39145 /* IDB_OBM5_CT_THRESHOLD_PIPE0 */ "", 39146 /* IDB_OBM5_CT_THRESHOLD_PIPE1 */ "", 39147 /* IDB_OBM5_CT_THRESHOLD_PIPE2 */ "", 39148 /* IDB_OBM5_CT_THRESHOLD_PIPE3 */ "", 39149 /* IDB_OBM5_DATA_ECC_STATUS */ "IDB_OBM5_DATA_ECC_STATUS", 39150 /* IDB_OBM5_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM5_DATA_ECC_STATUS_PIPE0", 39151 /* IDB_OBM5_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM5_DATA_ECC_STATUS_PIPE1", 39152 /* IDB_OBM5_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM5_DATA_ECC_STATUS_PIPE2", 39153 /* IDB_OBM5_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM5_DATA_ECC_STATUS_PIPE3", 39154 /* IDB_OBM5_DBG_A */ "IDB_OBM5_FORCE_SAF_CONFIG", 39155 /* IDB_OBM5_DBG_A_PIPE0 */ "IDB_OBM5_FORCE_SAF_CONFIG_PIPE0", 39156 /* IDB_OBM5_DBG_A_PIPE1 */ "IDB_OBM5_FORCE_SAF_CONFIG_PIPE1", 39157 /* IDB_OBM5_DBG_A_PIPE2 */ "IDB_OBM5_FORCE_SAF_CONFIG_PIPE2", 39158 /* IDB_OBM5_DBG_A_PIPE3 */ "IDB_OBM5_FORCE_SAF_CONFIG_PIPE3", 39159 /* IDB_OBM5_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 39160 /* IDB_OBM5_EXPRESS_ARRIVAL_PKT_COUNT */ "", 39161 /* IDB_OBM5_EXPRESS_BYTE_DROP_COUNT */ "", 39162 /* IDB_OBM5_EXPRESS_FLOW_CONTROL_CONFIG */ "", 39163 /* IDB_OBM5_EXPRESS_PKT_DROP_COUNT */ "", 39164 /* IDB_OBM5_FC_THRESHOLD */ "", 39165 /* IDB_OBM5_FC_THRESHOLD_0 */ "", 39166 /* IDB_OBM5_FC_THRESHOLD_1 */ "", 39167 /* IDB_OBM5_FC_THRESHOLD_1_PIPE0 */ "", 39168 /* IDB_OBM5_FC_THRESHOLD_1_PIPE1 */ "", 39169 /* IDB_OBM5_FC_THRESHOLD_1_PIPE2 */ "", 39170 /* IDB_OBM5_FC_THRESHOLD_1_PIPE3 */ "", 39171 /* IDB_OBM5_FC_THRESHOLD_PIPE0 */ "", 39172 /* IDB_OBM5_FC_THRESHOLD_PIPE1 */ "", 39173 /* IDB_OBM5_FC_THRESHOLD_PIPE2 */ "", 39174 /* IDB_OBM5_FC_THRESHOLD_PIPE3 */ "", 39175 /* IDB_OBM5_FLOW_CONTROL_CONFIG */ "", 39176 /* IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE0 */ "", 39177 /* IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE1 */ "", 39178 /* IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE2 */ "", 39179 /* IDB_OBM5_FLOW_CONTROL_CONFIG_PIPE3 */ "", 39180 /* IDB_OBM5_FLOW_CONTROL_EVENT_COUNT */ "", 39181 /* IDB_OBM5_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 39182 /* IDB_OBM5_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 39183 /* IDB_OBM5_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 39184 /* IDB_OBM5_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 39185 /* IDB_OBM5_FORCE_SAF_STATUS */ "", 39186 /* IDB_OBM5_FORCE_SAF_STATUS_PIPE0 */ "", 39187 /* IDB_OBM5_FORCE_SAF_STATUS_PIPE1 */ "", 39188 /* IDB_OBM5_INNER_TPID */ "", 39189 /* IDB_OBM5_INNER_TPID_PIPE0 */ "", 39190 /* IDB_OBM5_INNER_TPID_PIPE1 */ "", 39191 /* IDB_OBM5_INNER_TPID_PIPE2 */ "", 39192 /* IDB_OBM5_INNER_TPID_PIPE3 */ "", 39193 /* IDB_OBM5_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 39194 /* IDB_OBM5_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 39195 /* IDB_OBM5_LOSSLESS0_BYTE_DROP_COUNT */ "", 39196 /* IDB_OBM5_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 39197 /* IDB_OBM5_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 39198 /* IDB_OBM5_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 39199 /* IDB_OBM5_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 39200 /* IDB_OBM5_LOSSLESS0_PKT_DROP_COUNT */ "", 39201 /* IDB_OBM5_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 39202 /* IDB_OBM5_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 39203 /* IDB_OBM5_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 39204 /* IDB_OBM5_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 39205 /* IDB_OBM5_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 39206 /* IDB_OBM5_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 39207 /* IDB_OBM5_LOSSLESS1_BYTE_DROP_COUNT */ "", 39208 /* IDB_OBM5_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 39209 /* IDB_OBM5_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 39210 /* IDB_OBM5_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 39211 /* IDB_OBM5_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 39212 /* IDB_OBM5_LOSSLESS1_PKT_DROP_COUNT */ "", 39213 /* IDB_OBM5_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 39214 /* IDB_OBM5_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 39215 /* IDB_OBM5_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 39216 /* IDB_OBM5_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 39217 /* IDB_OBM5_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 39218 /* IDB_OBM5_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 39219 /* IDB_OBM5_LOSSY_HI_BYTE_DROP_COUNT */ "", 39220 /* IDB_OBM5_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 39221 /* IDB_OBM5_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 39222 /* IDB_OBM5_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 39223 /* IDB_OBM5_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 39224 /* IDB_OBM5_LOSSY_HI_PKT_DROP_COUNT */ "", 39225 /* IDB_OBM5_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 39226 /* IDB_OBM5_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 39227 /* IDB_OBM5_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 39228 /* IDB_OBM5_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 39229 /* IDB_OBM5_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 39230 /* IDB_OBM5_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 39231 /* IDB_OBM5_LOSSY_LO_BYTE_DROP_COUNT */ "", 39232 /* IDB_OBM5_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 39233 /* IDB_OBM5_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 39234 /* IDB_OBM5_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 39235 /* IDB_OBM5_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 39236 /* IDB_OBM5_LOSSY_LO_PKT_DROP_COUNT */ "", 39237 /* IDB_OBM5_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 39238 /* IDB_OBM5_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 39239 /* IDB_OBM5_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 39240 /* IDB_OBM5_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 39241 /* IDB_OBM5_MAX_USAGE */ "IDB_OBM5_MAX_USAGE", 39242 /* IDB_OBM5_MAX_USAGE_1 */ "IDB_OBM5_MAX_USAGE_1", 39243 /* IDB_OBM5_MAX_USAGE_1_PIPE0 */ "IDB_OBM5_MAX_USAGE_1_PIPE0", 39244 /* IDB_OBM5_MAX_USAGE_1_PIPE1 */ "IDB_OBM5_MAX_USAGE_1_PIPE1", 39245 /* IDB_OBM5_MAX_USAGE_1_PIPE2 */ "IDB_OBM5_MAX_USAGE_1_PIPE2", 39246 /* IDB_OBM5_MAX_USAGE_1_PIPE3 */ "IDB_OBM5_MAX_USAGE_1_PIPE3", 39247 /* IDB_OBM5_MAX_USAGE_PIPE0 */ "IDB_OBM5_MAX_USAGE_PIPE0", 39248 /* IDB_OBM5_MAX_USAGE_PIPE1 */ "IDB_OBM5_MAX_USAGE_PIPE1", 39249 /* IDB_OBM5_MAX_USAGE_PIPE2 */ "IDB_OBM5_MAX_USAGE_PIPE2", 39250 /* IDB_OBM5_MAX_USAGE_PIPE3 */ "IDB_OBM5_MAX_USAGE_PIPE3", 39251 /* IDB_OBM5_MAX_USAGE_SELECT */ "", 39252 /* IDB_OBM5_MAX_USAGE_SELECT_PIPE0 */ "", 39253 /* IDB_OBM5_MAX_USAGE_SELECT_PIPE1 */ "", 39254 /* IDB_OBM5_MAX_USAGE_SELECT_PIPE2 */ "", 39255 /* IDB_OBM5_MAX_USAGE_SELECT_PIPE3 */ "", 39256 /* IDB_OBM5_MONITOR_STATS_CONFIG */ "", 39257 /* IDB_OBM5_NIV_ETHERTYPE */ "", 39258 /* IDB_OBM5_NIV_ETHERTYPE_PIPE0 */ "", 39259 /* IDB_OBM5_NIV_ETHERTYPE_PIPE1 */ "", 39260 /* IDB_OBM5_NIV_ETHERTYPE_PIPE2 */ "", 39261 /* IDB_OBM5_NIV_ETHERTYPE_PIPE3 */ "", 39262 /* IDB_OBM5_OUTER_TPID */ "", 39263 /* IDB_OBM5_OUTER_TPID_0 */ "", 39264 /* IDB_OBM5_OUTER_TPID_1 */ "", 39265 /* IDB_OBM5_OUTER_TPID_2 */ "", 39266 /* IDB_OBM5_OUTER_TPID_3 */ "", 39267 /* IDB_OBM5_OUTER_TPID_0_PIPE0 */ "", 39268 /* IDB_OBM5_OUTER_TPID_0_PIPE1 */ "", 39269 /* IDB_OBM5_OUTER_TPID_0_PIPE2 */ "", 39270 /* IDB_OBM5_OUTER_TPID_0_PIPE3 */ "", 39271 /* IDB_OBM5_OUTER_TPID_1_PIPE0 */ "", 39272 /* IDB_OBM5_OUTER_TPID_1_PIPE1 */ "", 39273 /* IDB_OBM5_OUTER_TPID_1_PIPE2 */ "", 39274 /* IDB_OBM5_OUTER_TPID_1_PIPE3 */ "", 39275 /* IDB_OBM5_OUTER_TPID_2_PIPE0 */ "", 39276 /* IDB_OBM5_OUTER_TPID_2_PIPE1 */ "", 39277 /* IDB_OBM5_OUTER_TPID_2_PIPE2 */ "", 39278 /* IDB_OBM5_OUTER_TPID_2_PIPE3 */ "", 39279 /* IDB_OBM5_OUTER_TPID_3_PIPE0 */ "", 39280 /* IDB_OBM5_OUTER_TPID_3_PIPE1 */ "", 39281 /* IDB_OBM5_OUTER_TPID_3_PIPE2 */ "", 39282 /* IDB_OBM5_OUTER_TPID_3_PIPE3 */ "", 39283 /* IDB_OBM5_OUTER_TPID_PIPE0 */ "", 39284 /* IDB_OBM5_OUTER_TPID_PIPE1 */ "", 39285 /* IDB_OBM5_OUTER_TPID_PIPE2 */ "", 39286 /* IDB_OBM5_OUTER_TPID_PIPE3 */ "", 39287 /* IDB_OBM5_OVERSUB_MON_ECC_STATUS */ "IDB_OBM5_OVERSUB_MON_ECC_STATUS", 39288 /* IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE0", 39289 /* IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE1", 39290 /* IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE2", 39291 /* IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM5_OVERSUB_MON_ECC_STATUS_PIPE3", 39292 /* IDB_OBM5_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM5_OVERSUB_MON_PARITY_STATUS", 39293 /* IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE0", 39294 /* IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE1", 39295 /* IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE2", 39296 /* IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM5_OVERSUB_MON_PARITY_STATUS_PIPE3", 39297 /* IDB_OBM5_PE_ETHERTYPE */ "", 39298 /* IDB_OBM5_PE_ETHERTYPE_PIPE0 */ "", 39299 /* IDB_OBM5_PE_ETHERTYPE_PIPE1 */ "", 39300 /* IDB_OBM5_PE_ETHERTYPE_PIPE2 */ "", 39301 /* IDB_OBM5_PE_ETHERTYPE_PIPE3 */ "", 39302 /* IDB_OBM5_PORT_CONFIG */ "", 39303 /* IDB_OBM5_PORT_CONFIG_PIPE0 */ "", 39304 /* IDB_OBM5_PORT_CONFIG_PIPE1 */ "", 39305 /* IDB_OBM5_PORT_CONFIG_PIPE2 */ "", 39306 /* IDB_OBM5_PORT_CONFIG_PIPE3 */ "", 39307 /* IDB_OBM5_POWER_SAVE */ "IDB_OBM5_POWER_SAVE", 39308 /* IDB_OBM5_PROTOCOL_CONTROL_0 */ "", 39309 /* IDB_OBM5_PROTOCOL_CONTROL_1 */ "", 39310 /* IDB_OBM5_PROTOCOL_CONTROL_2 */ "", 39311 /* IDB_OBM5_PROTOCOL_CONTROL_0_PIPE0 */ "", 39312 /* IDB_OBM5_PROTOCOL_CONTROL_0_PIPE1 */ "", 39313 /* IDB_OBM5_PROTOCOL_CONTROL_0_PIPE2 */ "", 39314 /* IDB_OBM5_PROTOCOL_CONTROL_0_PIPE3 */ "", 39315 /* IDB_OBM5_PROTOCOL_CONTROL_1_PIPE0 */ "", 39316 /* IDB_OBM5_PROTOCOL_CONTROL_1_PIPE1 */ "", 39317 /* IDB_OBM5_PROTOCOL_CONTROL_1_PIPE2 */ "", 39318 /* IDB_OBM5_PROTOCOL_CONTROL_1_PIPE3 */ "", 39319 /* IDB_OBM5_PROTOCOL_CONTROL_2_PIPE0 */ "", 39320 /* IDB_OBM5_PROTOCOL_CONTROL_2_PIPE1 */ "", 39321 /* IDB_OBM5_PROTOCOL_CONTROL_2_PIPE2 */ "", 39322 /* IDB_OBM5_PROTOCOL_CONTROL_2_PIPE3 */ "", 39323 /* IDB_OBM5_QUEUE_ECC_STATUS */ "IDB_OBM5_QUEUE_ECC_STATUS", 39324 /* IDB_OBM5_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM5_QUEUE_ECC_STATUS_PIPE0", 39325 /* IDB_OBM5_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM5_QUEUE_ECC_STATUS_PIPE1", 39326 /* IDB_OBM5_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM5_QUEUE_ECC_STATUS_PIPE2", 39327 /* IDB_OBM5_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM5_QUEUE_ECC_STATUS_PIPE3", 39328 /* IDB_OBM5_QUEUE_SER_CONTROL */ "IDB_OBM5_QUEUE_SER_CONTROL", 39329 /* IDB_OBM5_RAM_CONTROL */ "IDB_OBM5_RAM_CONTROL", 39330 /* IDB_OBM5_RAM_CONTROL_PIPE0 */ "IDB_OBM5_RAM_CONTROL_PIPE0", 39331 /* IDB_OBM5_RAM_CONTROL_PIPE1 */ "IDB_OBM5_RAM_CONTROL_PIPE1", 39332 /* IDB_OBM5_RAM_CONTROL_PIPE2 */ "IDB_OBM5_RAM_CONTROL_PIPE2", 39333 /* IDB_OBM5_RAM_CONTROL_PIPE3 */ "IDB_OBM5_RAM_CONTROL_PIPE3", 39334 /* IDB_OBM5_SER_CONTROL */ "IDB_OBM5_SER_CONTROL", 39335 /* IDB_OBM5_SER_CONTROL_PIPE0 */ "IDB_OBM5_SER_CONTROL_PIPE0", 39336 /* IDB_OBM5_SER_CONTROL_PIPE1 */ "IDB_OBM5_SER_CONTROL_PIPE1", 39337 /* IDB_OBM5_SHARED_CONFIG */ "IDB_OBM5_SHARED_CONFIG", 39338 /* IDB_OBM5_SHARED_CONFIG_PIPE0 */ "IDB_OBM5_SHARED_CONFIG_PIPE0", 39339 /* IDB_OBM5_SHARED_CONFIG_PIPE1 */ "IDB_OBM5_SHARED_CONFIG_PIPE1", 39340 /* IDB_OBM5_SHARED_CONFIG_PIPE2 */ "IDB_OBM5_SHARED_CONFIG_PIPE2", 39341 /* IDB_OBM5_SHARED_CONFIG_PIPE3 */ "IDB_OBM5_SHARED_CONFIG_PIPE3", 39342 /* IDB_OBM5_SHARED_USAGE */ "IDB_OBM5_SHARED_USAGE", 39343 /* IDB_OBM5_SHARED_USAGE_PIPE0 */ "IDB_OBM5_SHARED_USAGE_PIPE0", 39344 /* IDB_OBM5_SHARED_USAGE_PIPE1 */ "IDB_OBM5_SHARED_USAGE_PIPE1", 39345 /* IDB_OBM5_SHARED_USAGE_PIPE2 */ "IDB_OBM5_SHARED_USAGE_PIPE2", 39346 /* IDB_OBM5_SHARED_USAGE_PIPE3 */ "IDB_OBM5_SHARED_USAGE_PIPE3", 39347 /* IDB_OBM5_SPARE_REG */ "IDB_OBM5_SPARE_REG", 39348 /* IDB_OBM5_THRESHOLD */ "", 39349 /* IDB_OBM5_THRESHOLD_0 */ "", 39350 /* IDB_OBM5_THRESHOLD_1 */ "", 39351 /* IDB_OBM5_THRESHOLD_1_PIPE0 */ "", 39352 /* IDB_OBM5_THRESHOLD_1_PIPE1 */ "", 39353 /* IDB_OBM5_THRESHOLD_1_PIPE2 */ "", 39354 /* IDB_OBM5_THRESHOLD_1_PIPE3 */ "", 39355 /* IDB_OBM5_THRESHOLD_PIPE0 */ "", 39356 /* IDB_OBM5_THRESHOLD_PIPE1 */ "", 39357 /* IDB_OBM5_THRESHOLD_PIPE2 */ "", 39358 /* IDB_OBM5_THRESHOLD_PIPE3 */ "", 39359 /* IDB_OBM5_USAGE */ "", 39360 /* IDB_OBM5_USAGE_PIPE0 */ "", 39361 /* IDB_OBM5_USAGE_PIPE1 */ "", 39362 /* IDB_OBM5_USAGE_PIPE2 */ "", 39363 /* IDB_OBM5_USAGE_PIPE3 */ "", 39364 /* IDB_OBM6_BANK_CONFIG */ "IDB_OBM6_BANK_CONFIG", 39365 /* IDB_OBM6_BANK_CONFIG_PIPE0 */ "IDB_OBM6_BANK_CONFIG_PIPE0", 39366 /* IDB_OBM6_BANK_CONFIG_PIPE1 */ "IDB_OBM6_BANK_CONFIG_PIPE1", 39367 /* IDB_OBM6_BANK_CONFIG_PIPE2 */ "IDB_OBM6_BANK_CONFIG_PIPE2", 39368 /* IDB_OBM6_BANK_CONFIG_PIPE3 */ "IDB_OBM6_BANK_CONFIG_PIPE3", 39369 /* IDB_OBM6_BUCKET_COUNT_CONFIG */ "", 39370 /* IDB_OBM6_BUFFER_CONFIG */ "", 39371 /* IDB_OBM6_BUFFER_CONFIG_PIPE0 */ "", 39372 /* IDB_OBM6_BUFFER_CONFIG_PIPE1 */ "", 39373 /* IDB_OBM6_CA_CONTROL */ "IDB_OBM6_CA_CONTROL", 39374 /* IDB_OBM6_CA_CONTROL_PIPE0 */ "IDB_OBM6_CA_CONTROL_PIPE0", 39375 /* IDB_OBM6_CA_CONTROL_PIPE1 */ "IDB_OBM6_CA_CONTROL_PIPE1", 39376 /* IDB_OBM6_CA_CONTROL_PIPE2 */ "IDB_OBM6_CA_CONTROL_PIPE2", 39377 /* IDB_OBM6_CA_CONTROL_PIPE3 */ "IDB_OBM6_CA_CONTROL_PIPE3", 39378 /* IDB_OBM6_CA_CT_CONTROL */ "IDB_OBM6_CA_CT_CONTROL", 39379 /* IDB_OBM6_CA_CT_CONTROL_PIPE0 */ "IDB_OBM6_CA_CT_CONTROL_PIPE0", 39380 /* IDB_OBM6_CA_CT_CONTROL_PIPE1 */ "IDB_OBM6_CA_CT_CONTROL_PIPE1", 39381 /* IDB_OBM6_CA_CT_CONTROL_PIPE2 */ "IDB_OBM6_CA_CT_CONTROL_PIPE2", 39382 /* IDB_OBM6_CA_CT_CONTROL_PIPE3 */ "IDB_OBM6_CA_CT_CONTROL_PIPE3", 39383 /* IDB_OBM6_CA_ECC_STATUS */ "IDB_OBM6_CA_ECC_STATUS", 39384 /* IDB_OBM6_CA_ECC_STATUS_PIPE0 */ "IDB_OBM6_CA_ECC_STATUS_PIPE0", 39385 /* IDB_OBM6_CA_ECC_STATUS_PIPE1 */ "IDB_OBM6_CA_ECC_STATUS_PIPE1", 39386 /* IDB_OBM6_CA_ECC_STATUS_PIPE2 */ "IDB_OBM6_CA_ECC_STATUS_PIPE2", 39387 /* IDB_OBM6_CA_ECC_STATUS_PIPE3 */ "IDB_OBM6_CA_ECC_STATUS_PIPE3", 39388 /* IDB_OBM6_CA_HW_CONTROL */ "IDB_OBM6_CA_HW_CONTROL", 39389 /* IDB_OBM6_CA_HW_CONTROL_PIPE0 */ "IDB_OBM6_CA_HW_CONTROL_PIPE0", 39390 /* IDB_OBM6_CA_HW_CONTROL_PIPE1 */ "IDB_OBM6_CA_HW_CONTROL_PIPE1", 39391 /* IDB_OBM6_CA_HW_CONTROL_PIPE2 */ "IDB_OBM6_CA_HW_CONTROL_PIPE2", 39392 /* IDB_OBM6_CA_HW_CONTROL_PIPE3 */ "IDB_OBM6_CA_HW_CONTROL_PIPE3", 39393 /* IDB_OBM6_CA_HW_STATUS */ "IDB_OBM6_CA_HW_STATUS", 39394 /* IDB_OBM6_CA_HW_STATUS_PIPE0 */ "IDB_OBM6_CA_HW_STATUS_PIPE0", 39395 /* IDB_OBM6_CA_HW_STATUS_PIPE1 */ "IDB_OBM6_CA_HW_STATUS_PIPE1", 39396 /* IDB_OBM6_CA_HW_STATUS_PIPE2 */ "IDB_OBM6_CA_HW_STATUS_PIPE2", 39397 /* IDB_OBM6_CA_HW_STATUS_PIPE3 */ "IDB_OBM6_CA_HW_STATUS_PIPE3", 39398 /* IDB_OBM6_CA_POINTER_STATUS */ "IDB_OBM6_CA_POINTER_STATUS", 39399 /* IDB_OBM6_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM6_CA_POINTER_STATUS_PIPE0", 39400 /* IDB_OBM6_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM6_CA_POINTER_STATUS_PIPE1", 39401 /* IDB_OBM6_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM6_CA_POINTER_STATUS_PIPE2", 39402 /* IDB_OBM6_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM6_CA_POINTER_STATUS_PIPE3", 39403 /* IDB_OBM6_CONTROL */ "IDB_OBM6_CONTROL", 39404 /* IDB_OBM6_CONTROL_PIPE0 */ "IDB_OBM6_CONTROL_PIPE0", 39405 /* IDB_OBM6_CONTROL_PIPE1 */ "IDB_OBM6_CONTROL_PIPE1", 39406 /* IDB_OBM6_CONTROL_PIPE2 */ "IDB_OBM6_CONTROL_PIPE2", 39407 /* IDB_OBM6_CONTROL_PIPE3 */ "IDB_OBM6_CONTROL_PIPE3", 39408 /* IDB_OBM6_CT_THRESHOLD */ "", 39409 /* IDB_OBM6_CT_THRESHOLD_PIPE0 */ "", 39410 /* IDB_OBM6_CT_THRESHOLD_PIPE1 */ "", 39411 /* IDB_OBM6_CT_THRESHOLD_PIPE2 */ "", 39412 /* IDB_OBM6_CT_THRESHOLD_PIPE3 */ "", 39413 /* IDB_OBM6_DATA_ECC_STATUS */ "IDB_OBM6_DATA_ECC_STATUS", 39414 /* IDB_OBM6_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM6_DATA_ECC_STATUS_PIPE0", 39415 /* IDB_OBM6_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM6_DATA_ECC_STATUS_PIPE1", 39416 /* IDB_OBM6_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM6_DATA_ECC_STATUS_PIPE2", 39417 /* IDB_OBM6_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM6_DATA_ECC_STATUS_PIPE3", 39418 /* IDB_OBM6_DBG_A */ "IDB_OBM6_FORCE_SAF_CONFIG", 39419 /* IDB_OBM6_DBG_A_PIPE0 */ "IDB_OBM6_FORCE_SAF_CONFIG_PIPE0", 39420 /* IDB_OBM6_DBG_A_PIPE1 */ "IDB_OBM6_FORCE_SAF_CONFIG_PIPE1", 39421 /* IDB_OBM6_DBG_A_PIPE2 */ "IDB_OBM6_FORCE_SAF_CONFIG_PIPE2", 39422 /* IDB_OBM6_DBG_A_PIPE3 */ "IDB_OBM6_FORCE_SAF_CONFIG_PIPE3", 39423 /* IDB_OBM6_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 39424 /* IDB_OBM6_EXPRESS_ARRIVAL_PKT_COUNT */ "", 39425 /* IDB_OBM6_EXPRESS_BYTE_DROP_COUNT */ "", 39426 /* IDB_OBM6_EXPRESS_FLOW_CONTROL_CONFIG */ "", 39427 /* IDB_OBM6_EXPRESS_PKT_DROP_COUNT */ "", 39428 /* IDB_OBM6_FC_THRESHOLD */ "", 39429 /* IDB_OBM6_FC_THRESHOLD_0 */ "", 39430 /* IDB_OBM6_FC_THRESHOLD_1 */ "", 39431 /* IDB_OBM6_FC_THRESHOLD_1_PIPE0 */ "", 39432 /* IDB_OBM6_FC_THRESHOLD_1_PIPE1 */ "", 39433 /* IDB_OBM6_FC_THRESHOLD_1_PIPE2 */ "", 39434 /* IDB_OBM6_FC_THRESHOLD_1_PIPE3 */ "", 39435 /* IDB_OBM6_FC_THRESHOLD_PIPE0 */ "", 39436 /* IDB_OBM6_FC_THRESHOLD_PIPE1 */ "", 39437 /* IDB_OBM6_FC_THRESHOLD_PIPE2 */ "", 39438 /* IDB_OBM6_FC_THRESHOLD_PIPE3 */ "", 39439 /* IDB_OBM6_FLOW_CONTROL_CONFIG */ "", 39440 /* IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE0 */ "", 39441 /* IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE1 */ "", 39442 /* IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE2 */ "", 39443 /* IDB_OBM6_FLOW_CONTROL_CONFIG_PIPE3 */ "", 39444 /* IDB_OBM6_FLOW_CONTROL_EVENT_COUNT */ "", 39445 /* IDB_OBM6_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 39446 /* IDB_OBM6_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 39447 /* IDB_OBM6_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 39448 /* IDB_OBM6_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 39449 /* IDB_OBM6_FORCE_SAF_STATUS */ "", 39450 /* IDB_OBM6_FORCE_SAF_STATUS_PIPE0 */ "", 39451 /* IDB_OBM6_FORCE_SAF_STATUS_PIPE1 */ "", 39452 /* IDB_OBM6_INNER_TPID */ "", 39453 /* IDB_OBM6_INNER_TPID_PIPE0 */ "", 39454 /* IDB_OBM6_INNER_TPID_PIPE1 */ "", 39455 /* IDB_OBM6_INNER_TPID_PIPE2 */ "", 39456 /* IDB_OBM6_INNER_TPID_PIPE3 */ "", 39457 /* IDB_OBM6_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 39458 /* IDB_OBM6_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 39459 /* IDB_OBM6_LOSSLESS0_BYTE_DROP_COUNT */ "", 39460 /* IDB_OBM6_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 39461 /* IDB_OBM6_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 39462 /* IDB_OBM6_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 39463 /* IDB_OBM6_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 39464 /* IDB_OBM6_LOSSLESS0_PKT_DROP_COUNT */ "", 39465 /* IDB_OBM6_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 39466 /* IDB_OBM6_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 39467 /* IDB_OBM6_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 39468 /* IDB_OBM6_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 39469 /* IDB_OBM6_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 39470 /* IDB_OBM6_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 39471 /* IDB_OBM6_LOSSLESS1_BYTE_DROP_COUNT */ "", 39472 /* IDB_OBM6_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 39473 /* IDB_OBM6_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 39474 /* IDB_OBM6_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 39475 /* IDB_OBM6_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 39476 /* IDB_OBM6_LOSSLESS1_PKT_DROP_COUNT */ "", 39477 /* IDB_OBM6_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 39478 /* IDB_OBM6_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 39479 /* IDB_OBM6_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 39480 /* IDB_OBM6_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 39481 /* IDB_OBM6_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 39482 /* IDB_OBM6_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 39483 /* IDB_OBM6_LOSSY_HI_BYTE_DROP_COUNT */ "", 39484 /* IDB_OBM6_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 39485 /* IDB_OBM6_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 39486 /* IDB_OBM6_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 39487 /* IDB_OBM6_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 39488 /* IDB_OBM6_LOSSY_HI_PKT_DROP_COUNT */ "", 39489 /* IDB_OBM6_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 39490 /* IDB_OBM6_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 39491 /* IDB_OBM6_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 39492 /* IDB_OBM6_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 39493 /* IDB_OBM6_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 39494 /* IDB_OBM6_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 39495 /* IDB_OBM6_LOSSY_LO_BYTE_DROP_COUNT */ "", 39496 /* IDB_OBM6_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 39497 /* IDB_OBM6_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 39498 /* IDB_OBM6_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 39499 /* IDB_OBM6_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 39500 /* IDB_OBM6_LOSSY_LO_PKT_DROP_COUNT */ "", 39501 /* IDB_OBM6_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 39502 /* IDB_OBM6_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 39503 /* IDB_OBM6_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 39504 /* IDB_OBM6_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 39505 /* IDB_OBM6_MAX_USAGE */ "IDB_OBM6_MAX_USAGE", 39506 /* IDB_OBM6_MAX_USAGE_1 */ "IDB_OBM6_MAX_USAGE_1", 39507 /* IDB_OBM6_MAX_USAGE_1_PIPE0 */ "IDB_OBM6_MAX_USAGE_1_PIPE0", 39508 /* IDB_OBM6_MAX_USAGE_1_PIPE1 */ "IDB_OBM6_MAX_USAGE_1_PIPE1", 39509 /* IDB_OBM6_MAX_USAGE_1_PIPE2 */ "IDB_OBM6_MAX_USAGE_1_PIPE2", 39510 /* IDB_OBM6_MAX_USAGE_1_PIPE3 */ "IDB_OBM6_MAX_USAGE_1_PIPE3", 39511 /* IDB_OBM6_MAX_USAGE_PIPE0 */ "IDB_OBM6_MAX_USAGE_PIPE0", 39512 /* IDB_OBM6_MAX_USAGE_PIPE1 */ "IDB_OBM6_MAX_USAGE_PIPE1", 39513 /* IDB_OBM6_MAX_USAGE_PIPE2 */ "IDB_OBM6_MAX_USAGE_PIPE2", 39514 /* IDB_OBM6_MAX_USAGE_PIPE3 */ "IDB_OBM6_MAX_USAGE_PIPE3", 39515 /* IDB_OBM6_MAX_USAGE_SELECT */ "", 39516 /* IDB_OBM6_MAX_USAGE_SELECT_PIPE0 */ "", 39517 /* IDB_OBM6_MAX_USAGE_SELECT_PIPE1 */ "", 39518 /* IDB_OBM6_MAX_USAGE_SELECT_PIPE2 */ "", 39519 /* IDB_OBM6_MAX_USAGE_SELECT_PIPE3 */ "", 39520 /* IDB_OBM6_MONITOR_STATS_CONFIG */ "", 39521 /* IDB_OBM6_NIV_ETHERTYPE */ "", 39522 /* IDB_OBM6_NIV_ETHERTYPE_PIPE0 */ "", 39523 /* IDB_OBM6_NIV_ETHERTYPE_PIPE1 */ "", 39524 /* IDB_OBM6_NIV_ETHERTYPE_PIPE2 */ "", 39525 /* IDB_OBM6_NIV_ETHERTYPE_PIPE3 */ "", 39526 /* IDB_OBM6_OUTER_TPID */ "", 39527 /* IDB_OBM6_OUTER_TPID_0 */ "", 39528 /* IDB_OBM6_OUTER_TPID_1 */ "", 39529 /* IDB_OBM6_OUTER_TPID_2 */ "", 39530 /* IDB_OBM6_OUTER_TPID_3 */ "", 39531 /* IDB_OBM6_OUTER_TPID_0_PIPE0 */ "", 39532 /* IDB_OBM6_OUTER_TPID_0_PIPE1 */ "", 39533 /* IDB_OBM6_OUTER_TPID_0_PIPE2 */ "", 39534 /* IDB_OBM6_OUTER_TPID_0_PIPE3 */ "", 39535 /* IDB_OBM6_OUTER_TPID_1_PIPE0 */ "", 39536 /* IDB_OBM6_OUTER_TPID_1_PIPE1 */ "", 39537 /* IDB_OBM6_OUTER_TPID_1_PIPE2 */ "", 39538 /* IDB_OBM6_OUTER_TPID_1_PIPE3 */ "", 39539 /* IDB_OBM6_OUTER_TPID_2_PIPE0 */ "", 39540 /* IDB_OBM6_OUTER_TPID_2_PIPE1 */ "", 39541 /* IDB_OBM6_OUTER_TPID_2_PIPE2 */ "", 39542 /* IDB_OBM6_OUTER_TPID_2_PIPE3 */ "", 39543 /* IDB_OBM6_OUTER_TPID_3_PIPE0 */ "", 39544 /* IDB_OBM6_OUTER_TPID_3_PIPE1 */ "", 39545 /* IDB_OBM6_OUTER_TPID_3_PIPE2 */ "", 39546 /* IDB_OBM6_OUTER_TPID_3_PIPE3 */ "", 39547 /* IDB_OBM6_OUTER_TPID_PIPE0 */ "", 39548 /* IDB_OBM6_OUTER_TPID_PIPE1 */ "", 39549 /* IDB_OBM6_OUTER_TPID_PIPE2 */ "", 39550 /* IDB_OBM6_OUTER_TPID_PIPE3 */ "", 39551 /* IDB_OBM6_OVERSUB_MON_ECC_STATUS */ "IDB_OBM6_OVERSUB_MON_ECC_STATUS", 39552 /* IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE0", 39553 /* IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE1", 39554 /* IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE2", 39555 /* IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM6_OVERSUB_MON_ECC_STATUS_PIPE3", 39556 /* IDB_OBM6_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM6_OVERSUB_MON_PARITY_STATUS", 39557 /* IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE0", 39558 /* IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE1", 39559 /* IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE2", 39560 /* IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM6_OVERSUB_MON_PARITY_STATUS_PIPE3", 39561 /* IDB_OBM6_PE_ETHERTYPE */ "", 39562 /* IDB_OBM6_PE_ETHERTYPE_PIPE0 */ "", 39563 /* IDB_OBM6_PE_ETHERTYPE_PIPE1 */ "", 39564 /* IDB_OBM6_PE_ETHERTYPE_PIPE2 */ "", 39565 /* IDB_OBM6_PE_ETHERTYPE_PIPE3 */ "", 39566 /* IDB_OBM6_PORT_CONFIG */ "", 39567 /* IDB_OBM6_PORT_CONFIG_PIPE0 */ "", 39568 /* IDB_OBM6_PORT_CONFIG_PIPE1 */ "", 39569 /* IDB_OBM6_PORT_CONFIG_PIPE2 */ "", 39570 /* IDB_OBM6_PORT_CONFIG_PIPE3 */ "", 39571 /* IDB_OBM6_POWER_SAVE */ "IDB_OBM6_POWER_SAVE", 39572 /* IDB_OBM6_PROTOCOL_CONTROL_0 */ "", 39573 /* IDB_OBM6_PROTOCOL_CONTROL_1 */ "", 39574 /* IDB_OBM6_PROTOCOL_CONTROL_2 */ "", 39575 /* IDB_OBM6_PROTOCOL_CONTROL_0_PIPE0 */ "", 39576 /* IDB_OBM6_PROTOCOL_CONTROL_0_PIPE1 */ "", 39577 /* IDB_OBM6_PROTOCOL_CONTROL_0_PIPE2 */ "", 39578 /* IDB_OBM6_PROTOCOL_CONTROL_0_PIPE3 */ "", 39579 /* IDB_OBM6_PROTOCOL_CONTROL_1_PIPE0 */ "", 39580 /* IDB_OBM6_PROTOCOL_CONTROL_1_PIPE1 */ "", 39581 /* IDB_OBM6_PROTOCOL_CONTROL_1_PIPE2 */ "", 39582 /* IDB_OBM6_PROTOCOL_CONTROL_1_PIPE3 */ "", 39583 /* IDB_OBM6_PROTOCOL_CONTROL_2_PIPE0 */ "", 39584 /* IDB_OBM6_PROTOCOL_CONTROL_2_PIPE1 */ "", 39585 /* IDB_OBM6_PROTOCOL_CONTROL_2_PIPE2 */ "", 39586 /* IDB_OBM6_PROTOCOL_CONTROL_2_PIPE3 */ "", 39587 /* IDB_OBM6_QUEUE_ECC_STATUS */ "IDB_OBM6_QUEUE_ECC_STATUS", 39588 /* IDB_OBM6_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM6_QUEUE_ECC_STATUS_PIPE0", 39589 /* IDB_OBM6_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM6_QUEUE_ECC_STATUS_PIPE1", 39590 /* IDB_OBM6_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM6_QUEUE_ECC_STATUS_PIPE2", 39591 /* IDB_OBM6_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM6_QUEUE_ECC_STATUS_PIPE3", 39592 /* IDB_OBM6_QUEUE_SER_CONTROL */ "IDB_OBM6_QUEUE_SER_CONTROL", 39593 /* IDB_OBM6_RAM_CONTROL */ "IDB_OBM6_RAM_CONTROL", 39594 /* IDB_OBM6_RAM_CONTROL_PIPE0 */ "IDB_OBM6_RAM_CONTROL_PIPE0", 39595 /* IDB_OBM6_RAM_CONTROL_PIPE1 */ "IDB_OBM6_RAM_CONTROL_PIPE1", 39596 /* IDB_OBM6_RAM_CONTROL_PIPE2 */ "IDB_OBM6_RAM_CONTROL_PIPE2", 39597 /* IDB_OBM6_RAM_CONTROL_PIPE3 */ "IDB_OBM6_RAM_CONTROL_PIPE3", 39598 /* IDB_OBM6_SER_CONTROL */ "IDB_OBM6_SER_CONTROL", 39599 /* IDB_OBM6_SER_CONTROL_PIPE0 */ "IDB_OBM6_SER_CONTROL_PIPE0", 39600 /* IDB_OBM6_SER_CONTROL_PIPE1 */ "IDB_OBM6_SER_CONTROL_PIPE1", 39601 /* IDB_OBM6_SHARED_CONFIG */ "IDB_OBM6_SHARED_CONFIG", 39602 /* IDB_OBM6_SHARED_CONFIG_PIPE0 */ "IDB_OBM6_SHARED_CONFIG_PIPE0", 39603 /* IDB_OBM6_SHARED_CONFIG_PIPE1 */ "IDB_OBM6_SHARED_CONFIG_PIPE1", 39604 /* IDB_OBM6_SHARED_CONFIG_PIPE2 */ "IDB_OBM6_SHARED_CONFIG_PIPE2", 39605 /* IDB_OBM6_SHARED_CONFIG_PIPE3 */ "IDB_OBM6_SHARED_CONFIG_PIPE3", 39606 /* IDB_OBM6_SHARED_USAGE */ "IDB_OBM6_SHARED_USAGE", 39607 /* IDB_OBM6_SHARED_USAGE_PIPE0 */ "IDB_OBM6_SHARED_USAGE_PIPE0", 39608 /* IDB_OBM6_SHARED_USAGE_PIPE1 */ "IDB_OBM6_SHARED_USAGE_PIPE1", 39609 /* IDB_OBM6_SHARED_USAGE_PIPE2 */ "IDB_OBM6_SHARED_USAGE_PIPE2", 39610 /* IDB_OBM6_SHARED_USAGE_PIPE3 */ "IDB_OBM6_SHARED_USAGE_PIPE3", 39611 /* IDB_OBM6_SPARE_REG */ "IDB_OBM6_SPARE_REG", 39612 /* IDB_OBM6_THRESHOLD */ "", 39613 /* IDB_OBM6_THRESHOLD_0 */ "", 39614 /* IDB_OBM6_THRESHOLD_1 */ "", 39615 /* IDB_OBM6_THRESHOLD_1_PIPE0 */ "", 39616 /* IDB_OBM6_THRESHOLD_1_PIPE1 */ "", 39617 /* IDB_OBM6_THRESHOLD_1_PIPE2 */ "", 39618 /* IDB_OBM6_THRESHOLD_1_PIPE3 */ "", 39619 /* IDB_OBM6_THRESHOLD_PIPE0 */ "", 39620 /* IDB_OBM6_THRESHOLD_PIPE1 */ "", 39621 /* IDB_OBM6_THRESHOLD_PIPE2 */ "", 39622 /* IDB_OBM6_THRESHOLD_PIPE3 */ "", 39623 /* IDB_OBM6_USAGE */ "", 39624 /* IDB_OBM6_USAGE_PIPE0 */ "", 39625 /* IDB_OBM6_USAGE_PIPE1 */ "", 39626 /* IDB_OBM6_USAGE_PIPE2 */ "", 39627 /* IDB_OBM6_USAGE_PIPE3 */ "", 39628 /* IDB_OBM7_BANK_CONFIG */ "IDB_OBM7_BANK_CONFIG", 39629 /* IDB_OBM7_BANK_CONFIG_PIPE0 */ "IDB_OBM7_BANK_CONFIG_PIPE0", 39630 /* IDB_OBM7_BANK_CONFIG_PIPE1 */ "IDB_OBM7_BANK_CONFIG_PIPE1", 39631 /* IDB_OBM7_BANK_CONFIG_PIPE2 */ "IDB_OBM7_BANK_CONFIG_PIPE2", 39632 /* IDB_OBM7_BANK_CONFIG_PIPE3 */ "IDB_OBM7_BANK_CONFIG_PIPE3", 39633 /* IDB_OBM7_BUCKET_COUNT_CONFIG */ "", 39634 /* IDB_OBM7_BUFFER_CONFIG */ "", 39635 /* IDB_OBM7_BUFFER_CONFIG_PIPE0 */ "", 39636 /* IDB_OBM7_BUFFER_CONFIG_PIPE1 */ "", 39637 /* IDB_OBM7_CA_CONTROL */ "IDB_OBM7_CA_CONTROL", 39638 /* IDB_OBM7_CA_CONTROL_PIPE0 */ "IDB_OBM7_CA_CONTROL_PIPE0", 39639 /* IDB_OBM7_CA_CONTROL_PIPE1 */ "IDB_OBM7_CA_CONTROL_PIPE1", 39640 /* IDB_OBM7_CA_CONTROL_PIPE2 */ "IDB_OBM7_CA_CONTROL_PIPE2", 39641 /* IDB_OBM7_CA_CONTROL_PIPE3 */ "IDB_OBM7_CA_CONTROL_PIPE3", 39642 /* IDB_OBM7_CA_CT_CONTROL */ "IDB_OBM7_CA_CT_CONTROL", 39643 /* IDB_OBM7_CA_CT_CONTROL_PIPE0 */ "IDB_OBM7_CA_CT_CONTROL_PIPE0", 39644 /* IDB_OBM7_CA_CT_CONTROL_PIPE1 */ "IDB_OBM7_CA_CT_CONTROL_PIPE1", 39645 /* IDB_OBM7_CA_CT_CONTROL_PIPE2 */ "IDB_OBM7_CA_CT_CONTROL_PIPE2", 39646 /* IDB_OBM7_CA_CT_CONTROL_PIPE3 */ "IDB_OBM7_CA_CT_CONTROL_PIPE3", 39647 /* IDB_OBM7_CA_ECC_STATUS */ "IDB_OBM7_CA_ECC_STATUS", 39648 /* IDB_OBM7_CA_ECC_STATUS_PIPE0 */ "IDB_OBM7_CA_ECC_STATUS_PIPE0", 39649 /* IDB_OBM7_CA_ECC_STATUS_PIPE1 */ "IDB_OBM7_CA_ECC_STATUS_PIPE1", 39650 /* IDB_OBM7_CA_ECC_STATUS_PIPE2 */ "IDB_OBM7_CA_ECC_STATUS_PIPE2", 39651 /* IDB_OBM7_CA_ECC_STATUS_PIPE3 */ "IDB_OBM7_CA_ECC_STATUS_PIPE3", 39652 /* IDB_OBM7_CA_HW_CONTROL */ "IDB_OBM7_CA_HW_CONTROL", 39653 /* IDB_OBM7_CA_HW_CONTROL_PIPE0 */ "IDB_OBM7_CA_HW_CONTROL_PIPE0", 39654 /* IDB_OBM7_CA_HW_CONTROL_PIPE1 */ "IDB_OBM7_CA_HW_CONTROL_PIPE1", 39655 /* IDB_OBM7_CA_HW_CONTROL_PIPE2 */ "IDB_OBM7_CA_HW_CONTROL_PIPE2", 39656 /* IDB_OBM7_CA_HW_CONTROL_PIPE3 */ "IDB_OBM7_CA_HW_CONTROL_PIPE3", 39657 /* IDB_OBM7_CA_HW_STATUS */ "IDB_OBM7_CA_HW_STATUS", 39658 /* IDB_OBM7_CA_HW_STATUS_PIPE0 */ "IDB_OBM7_CA_HW_STATUS_PIPE0", 39659 /* IDB_OBM7_CA_HW_STATUS_PIPE1 */ "IDB_OBM7_CA_HW_STATUS_PIPE1", 39660 /* IDB_OBM7_CA_HW_STATUS_PIPE2 */ "IDB_OBM7_CA_HW_STATUS_PIPE2", 39661 /* IDB_OBM7_CA_HW_STATUS_PIPE3 */ "IDB_OBM7_CA_HW_STATUS_PIPE3", 39662 /* IDB_OBM7_CA_POINTER_STATUS */ "IDB_OBM7_CA_POINTER_STATUS", 39663 /* IDB_OBM7_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM7_CA_POINTER_STATUS_PIPE0", 39664 /* IDB_OBM7_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM7_CA_POINTER_STATUS_PIPE1", 39665 /* IDB_OBM7_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM7_CA_POINTER_STATUS_PIPE2", 39666 /* IDB_OBM7_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM7_CA_POINTER_STATUS_PIPE3", 39667 /* IDB_OBM7_CONTROL */ "IDB_OBM7_CONTROL", 39668 /* IDB_OBM7_CONTROL_PIPE0 */ "IDB_OBM7_CONTROL_PIPE0", 39669 /* IDB_OBM7_CONTROL_PIPE1 */ "IDB_OBM7_CONTROL_PIPE1", 39670 /* IDB_OBM7_CONTROL_PIPE2 */ "IDB_OBM7_CONTROL_PIPE2", 39671 /* IDB_OBM7_CONTROL_PIPE3 */ "IDB_OBM7_CONTROL_PIPE3", 39672 /* IDB_OBM7_CT_THRESHOLD */ "", 39673 /* IDB_OBM7_CT_THRESHOLD_PIPE0 */ "", 39674 /* IDB_OBM7_CT_THRESHOLD_PIPE1 */ "", 39675 /* IDB_OBM7_CT_THRESHOLD_PIPE2 */ "", 39676 /* IDB_OBM7_CT_THRESHOLD_PIPE3 */ "", 39677 /* IDB_OBM7_DATA_ECC_STATUS */ "IDB_OBM7_DATA_ECC_STATUS", 39678 /* IDB_OBM7_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM7_DATA_ECC_STATUS_PIPE0", 39679 /* IDB_OBM7_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM7_DATA_ECC_STATUS_PIPE1", 39680 /* IDB_OBM7_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM7_DATA_ECC_STATUS_PIPE2", 39681 /* IDB_OBM7_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM7_DATA_ECC_STATUS_PIPE3", 39682 /* IDB_OBM7_DBG_A */ "IDB_OBM7_FORCE_SAF_CONFIG", 39683 /* IDB_OBM7_DBG_A_PIPE0 */ "IDB_OBM7_FORCE_SAF_CONFIG_PIPE0", 39684 /* IDB_OBM7_DBG_A_PIPE1 */ "IDB_OBM7_FORCE_SAF_CONFIG_PIPE1", 39685 /* IDB_OBM7_DBG_A_PIPE2 */ "IDB_OBM7_FORCE_SAF_CONFIG_PIPE2", 39686 /* IDB_OBM7_DBG_A_PIPE3 */ "IDB_OBM7_FORCE_SAF_CONFIG_PIPE3", 39687 /* IDB_OBM7_EXPRESS_ARRIVAL_BYTE_COUNT */ "", 39688 /* IDB_OBM7_EXPRESS_ARRIVAL_PKT_COUNT */ "", 39689 /* IDB_OBM7_EXPRESS_BYTE_DROP_COUNT */ "", 39690 /* IDB_OBM7_EXPRESS_FLOW_CONTROL_CONFIG */ "", 39691 /* IDB_OBM7_EXPRESS_PKT_DROP_COUNT */ "", 39692 /* IDB_OBM7_FC_THRESHOLD */ "", 39693 /* IDB_OBM7_FC_THRESHOLD_0 */ "", 39694 /* IDB_OBM7_FC_THRESHOLD_1 */ "", 39695 /* IDB_OBM7_FC_THRESHOLD_1_PIPE0 */ "", 39696 /* IDB_OBM7_FC_THRESHOLD_1_PIPE1 */ "", 39697 /* IDB_OBM7_FC_THRESHOLD_1_PIPE2 */ "", 39698 /* IDB_OBM7_FC_THRESHOLD_1_PIPE3 */ "", 39699 /* IDB_OBM7_FC_THRESHOLD_PIPE0 */ "", 39700 /* IDB_OBM7_FC_THRESHOLD_PIPE1 */ "", 39701 /* IDB_OBM7_FC_THRESHOLD_PIPE2 */ "", 39702 /* IDB_OBM7_FC_THRESHOLD_PIPE3 */ "", 39703 /* IDB_OBM7_FLOW_CONTROL_CONFIG */ "", 39704 /* IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE0 */ "", 39705 /* IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE1 */ "", 39706 /* IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE2 */ "", 39707 /* IDB_OBM7_FLOW_CONTROL_CONFIG_PIPE3 */ "", 39708 /* IDB_OBM7_FLOW_CONTROL_EVENT_COUNT */ "", 39709 /* IDB_OBM7_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 39710 /* IDB_OBM7_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 39711 /* IDB_OBM7_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 39712 /* IDB_OBM7_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 39713 /* IDB_OBM7_FORCE_SAF_STATUS */ "", 39714 /* IDB_OBM7_FORCE_SAF_STATUS_PIPE0 */ "", 39715 /* IDB_OBM7_FORCE_SAF_STATUS_PIPE1 */ "", 39716 /* IDB_OBM7_INNER_TPID */ "", 39717 /* IDB_OBM7_INNER_TPID_PIPE0 */ "", 39718 /* IDB_OBM7_INNER_TPID_PIPE1 */ "", 39719 /* IDB_OBM7_INNER_TPID_PIPE2 */ "", 39720 /* IDB_OBM7_INNER_TPID_PIPE3 */ "", 39721 /* IDB_OBM7_LOSSLESS0_ARRIVAL_BYTE_COUNT */ "", 39722 /* IDB_OBM7_LOSSLESS0_ARRIVAL_PKT_COUNT */ "", 39723 /* IDB_OBM7_LOSSLESS0_BYTE_DROP_COUNT */ "", 39724 /* IDB_OBM7_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 39725 /* IDB_OBM7_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 39726 /* IDB_OBM7_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 39727 /* IDB_OBM7_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 39728 /* IDB_OBM7_LOSSLESS0_PKT_DROP_COUNT */ "", 39729 /* IDB_OBM7_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 39730 /* IDB_OBM7_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 39731 /* IDB_OBM7_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 39732 /* IDB_OBM7_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 39733 /* IDB_OBM7_LOSSLESS1_ARRIVAL_BYTE_COUNT */ "", 39734 /* IDB_OBM7_LOSSLESS1_ARRIVAL_PKT_COUNT */ "", 39735 /* IDB_OBM7_LOSSLESS1_BYTE_DROP_COUNT */ "", 39736 /* IDB_OBM7_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 39737 /* IDB_OBM7_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 39738 /* IDB_OBM7_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 39739 /* IDB_OBM7_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 39740 /* IDB_OBM7_LOSSLESS1_PKT_DROP_COUNT */ "", 39741 /* IDB_OBM7_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 39742 /* IDB_OBM7_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 39743 /* IDB_OBM7_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 39744 /* IDB_OBM7_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 39745 /* IDB_OBM7_LOSSY_HI_ARRIVAL_BYTE_COUNT */ "", 39746 /* IDB_OBM7_LOSSY_HI_ARRIVAL_PKT_COUNT */ "", 39747 /* IDB_OBM7_LOSSY_HI_BYTE_DROP_COUNT */ "", 39748 /* IDB_OBM7_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 39749 /* IDB_OBM7_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 39750 /* IDB_OBM7_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 39751 /* IDB_OBM7_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 39752 /* IDB_OBM7_LOSSY_HI_PKT_DROP_COUNT */ "", 39753 /* IDB_OBM7_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 39754 /* IDB_OBM7_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 39755 /* IDB_OBM7_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 39756 /* IDB_OBM7_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 39757 /* IDB_OBM7_LOSSY_LO_ARRIVAL_BYTE_COUNT */ "", 39758 /* IDB_OBM7_LOSSY_LO_ARRIVAL_PKT_COUNT */ "", 39759 /* IDB_OBM7_LOSSY_LO_BYTE_DROP_COUNT */ "", 39760 /* IDB_OBM7_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 39761 /* IDB_OBM7_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 39762 /* IDB_OBM7_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 39763 /* IDB_OBM7_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 39764 /* IDB_OBM7_LOSSY_LO_PKT_DROP_COUNT */ "", 39765 /* IDB_OBM7_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 39766 /* IDB_OBM7_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 39767 /* IDB_OBM7_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 39768 /* IDB_OBM7_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 39769 /* IDB_OBM7_MAX_USAGE */ "IDB_OBM7_MAX_USAGE", 39770 /* IDB_OBM7_MAX_USAGE_1 */ "IDB_OBM7_MAX_USAGE_1", 39771 /* IDB_OBM7_MAX_USAGE_1_PIPE0 */ "IDB_OBM7_MAX_USAGE_1_PIPE0", 39772 /* IDB_OBM7_MAX_USAGE_1_PIPE1 */ "IDB_OBM7_MAX_USAGE_1_PIPE1", 39773 /* IDB_OBM7_MAX_USAGE_1_PIPE2 */ "IDB_OBM7_MAX_USAGE_1_PIPE2", 39774 /* IDB_OBM7_MAX_USAGE_1_PIPE3 */ "IDB_OBM7_MAX_USAGE_1_PIPE3", 39775 /* IDB_OBM7_MAX_USAGE_PIPE0 */ "IDB_OBM7_MAX_USAGE_PIPE0", 39776 /* IDB_OBM7_MAX_USAGE_PIPE1 */ "IDB_OBM7_MAX_USAGE_PIPE1", 39777 /* IDB_OBM7_MAX_USAGE_PIPE2 */ "IDB_OBM7_MAX_USAGE_PIPE2", 39778 /* IDB_OBM7_MAX_USAGE_PIPE3 */ "IDB_OBM7_MAX_USAGE_PIPE3", 39779 /* IDB_OBM7_MAX_USAGE_SELECT */ "", 39780 /* IDB_OBM7_MAX_USAGE_SELECT_PIPE0 */ "", 39781 /* IDB_OBM7_MAX_USAGE_SELECT_PIPE1 */ "", 39782 /* IDB_OBM7_MAX_USAGE_SELECT_PIPE2 */ "", 39783 /* IDB_OBM7_MAX_USAGE_SELECT_PIPE3 */ "", 39784 /* IDB_OBM7_MONITOR_STATS_CONFIG */ "", 39785 /* IDB_OBM7_NIV_ETHERTYPE */ "", 39786 /* IDB_OBM7_NIV_ETHERTYPE_PIPE0 */ "", 39787 /* IDB_OBM7_NIV_ETHERTYPE_PIPE1 */ "", 39788 /* IDB_OBM7_NIV_ETHERTYPE_PIPE2 */ "", 39789 /* IDB_OBM7_NIV_ETHERTYPE_PIPE3 */ "", 39790 /* IDB_OBM7_OUTER_TPID */ "", 39791 /* IDB_OBM7_OUTER_TPID_0 */ "", 39792 /* IDB_OBM7_OUTER_TPID_1 */ "", 39793 /* IDB_OBM7_OUTER_TPID_2 */ "", 39794 /* IDB_OBM7_OUTER_TPID_3 */ "", 39795 /* IDB_OBM7_OUTER_TPID_0_PIPE0 */ "", 39796 /* IDB_OBM7_OUTER_TPID_0_PIPE1 */ "", 39797 /* IDB_OBM7_OUTER_TPID_0_PIPE2 */ "", 39798 /* IDB_OBM7_OUTER_TPID_0_PIPE3 */ "", 39799 /* IDB_OBM7_OUTER_TPID_1_PIPE0 */ "", 39800 /* IDB_OBM7_OUTER_TPID_1_PIPE1 */ "", 39801 /* IDB_OBM7_OUTER_TPID_1_PIPE2 */ "", 39802 /* IDB_OBM7_OUTER_TPID_1_PIPE3 */ "", 39803 /* IDB_OBM7_OUTER_TPID_2_PIPE0 */ "", 39804 /* IDB_OBM7_OUTER_TPID_2_PIPE1 */ "", 39805 /* IDB_OBM7_OUTER_TPID_2_PIPE2 */ "", 39806 /* IDB_OBM7_OUTER_TPID_2_PIPE3 */ "", 39807 /* IDB_OBM7_OUTER_TPID_3_PIPE0 */ "", 39808 /* IDB_OBM7_OUTER_TPID_3_PIPE1 */ "", 39809 /* IDB_OBM7_OUTER_TPID_3_PIPE2 */ "", 39810 /* IDB_OBM7_OUTER_TPID_3_PIPE3 */ "", 39811 /* IDB_OBM7_OUTER_TPID_PIPE0 */ "", 39812 /* IDB_OBM7_OUTER_TPID_PIPE1 */ "", 39813 /* IDB_OBM7_OUTER_TPID_PIPE2 */ "", 39814 /* IDB_OBM7_OUTER_TPID_PIPE3 */ "", 39815 /* IDB_OBM7_OVERSUB_MON_ECC_STATUS */ "IDB_OBM7_OVERSUB_MON_ECC_STATUS", 39816 /* IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE0", 39817 /* IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE1", 39818 /* IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE2", 39819 /* IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM7_OVERSUB_MON_ECC_STATUS_PIPE3", 39820 /* IDB_OBM7_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM7_OVERSUB_MON_PARITY_STATUS", 39821 /* IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE0 */ "IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE0", 39822 /* IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE1 */ "IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE1", 39823 /* IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE2 */ "IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE2", 39824 /* IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE3 */ "IDB_OBM7_OVERSUB_MON_PARITY_STATUS_PIPE3", 39825 /* IDB_OBM7_PE_ETHERTYPE */ "", 39826 /* IDB_OBM7_PE_ETHERTYPE_PIPE0 */ "", 39827 /* IDB_OBM7_PE_ETHERTYPE_PIPE1 */ "", 39828 /* IDB_OBM7_PE_ETHERTYPE_PIPE2 */ "", 39829 /* IDB_OBM7_PE_ETHERTYPE_PIPE3 */ "", 39830 /* IDB_OBM7_PORT_CONFIG */ "", 39831 /* IDB_OBM7_PORT_CONFIG_PIPE0 */ "", 39832 /* IDB_OBM7_PORT_CONFIG_PIPE1 */ "", 39833 /* IDB_OBM7_PORT_CONFIG_PIPE2 */ "", 39834 /* IDB_OBM7_PORT_CONFIG_PIPE3 */ "", 39835 /* IDB_OBM7_POWER_SAVE */ "IDB_OBM7_POWER_SAVE", 39836 /* IDB_OBM7_PROTOCOL_CONTROL_0 */ "", 39837 /* IDB_OBM7_PROTOCOL_CONTROL_1 */ "", 39838 /* IDB_OBM7_PROTOCOL_CONTROL_2 */ "", 39839 /* IDB_OBM7_PROTOCOL_CONTROL_0_PIPE0 */ "", 39840 /* IDB_OBM7_PROTOCOL_CONTROL_0_PIPE1 */ "", 39841 /* IDB_OBM7_PROTOCOL_CONTROL_0_PIPE2 */ "", 39842 /* IDB_OBM7_PROTOCOL_CONTROL_0_PIPE3 */ "", 39843 /* IDB_OBM7_PROTOCOL_CONTROL_1_PIPE0 */ "", 39844 /* IDB_OBM7_PROTOCOL_CONTROL_1_PIPE1 */ "", 39845 /* IDB_OBM7_PROTOCOL_CONTROL_1_PIPE2 */ "", 39846 /* IDB_OBM7_PROTOCOL_CONTROL_1_PIPE3 */ "", 39847 /* IDB_OBM7_PROTOCOL_CONTROL_2_PIPE0 */ "", 39848 /* IDB_OBM7_PROTOCOL_CONTROL_2_PIPE1 */ "", 39849 /* IDB_OBM7_PROTOCOL_CONTROL_2_PIPE2 */ "", 39850 /* IDB_OBM7_PROTOCOL_CONTROL_2_PIPE3 */ "", 39851 /* IDB_OBM7_QUEUE_ECC_STATUS */ "IDB_OBM7_QUEUE_ECC_STATUS", 39852 /* IDB_OBM7_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM7_QUEUE_ECC_STATUS_PIPE0", 39853 /* IDB_OBM7_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM7_QUEUE_ECC_STATUS_PIPE1", 39854 /* IDB_OBM7_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM7_QUEUE_ECC_STATUS_PIPE2", 39855 /* IDB_OBM7_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM7_QUEUE_ECC_STATUS_PIPE3", 39856 /* IDB_OBM7_QUEUE_SER_CONTROL */ "IDB_OBM7_QUEUE_SER_CONTROL", 39857 /* IDB_OBM7_RAM_CONTROL */ "IDB_OBM7_RAM_CONTROL", 39858 /* IDB_OBM7_RAM_CONTROL_PIPE0 */ "IDB_OBM7_RAM_CONTROL_PIPE0", 39859 /* IDB_OBM7_RAM_CONTROL_PIPE1 */ "IDB_OBM7_RAM_CONTROL_PIPE1", 39860 /* IDB_OBM7_RAM_CONTROL_PIPE2 */ "IDB_OBM7_RAM_CONTROL_PIPE2", 39861 /* IDB_OBM7_RAM_CONTROL_PIPE3 */ "IDB_OBM7_RAM_CONTROL_PIPE3", 39862 /* IDB_OBM7_SER_CONTROL */ "IDB_OBM7_SER_CONTROL", 39863 /* IDB_OBM7_SER_CONTROL_PIPE0 */ "IDB_OBM7_SER_CONTROL_PIPE0", 39864 /* IDB_OBM7_SER_CONTROL_PIPE1 */ "IDB_OBM7_SER_CONTROL_PIPE1", 39865 /* IDB_OBM7_SHARED_CONFIG */ "IDB_OBM7_SHARED_CONFIG", 39866 /* IDB_OBM7_SHARED_CONFIG_PIPE0 */ "IDB_OBM7_SHARED_CONFIG_PIPE0", 39867 /* IDB_OBM7_SHARED_CONFIG_PIPE1 */ "IDB_OBM7_SHARED_CONFIG_PIPE1", 39868 /* IDB_OBM7_SHARED_CONFIG_PIPE2 */ "IDB_OBM7_SHARED_CONFIG_PIPE2", 39869 /* IDB_OBM7_SHARED_CONFIG_PIPE3 */ "IDB_OBM7_SHARED_CONFIG_PIPE3", 39870 /* IDB_OBM7_SHARED_USAGE */ "IDB_OBM7_SHARED_USAGE", 39871 /* IDB_OBM7_SHARED_USAGE_PIPE0 */ "IDB_OBM7_SHARED_USAGE_PIPE0", 39872 /* IDB_OBM7_SHARED_USAGE_PIPE1 */ "IDB_OBM7_SHARED_USAGE_PIPE1", 39873 /* IDB_OBM7_SHARED_USAGE_PIPE2 */ "IDB_OBM7_SHARED_USAGE_PIPE2", 39874 /* IDB_OBM7_SHARED_USAGE_PIPE3 */ "IDB_OBM7_SHARED_USAGE_PIPE3", 39875 /* IDB_OBM7_SPARE_REG */ "IDB_OBM7_SPARE_REG", 39876 /* IDB_OBM7_THRESHOLD */ "", 39877 /* IDB_OBM7_THRESHOLD_0 */ "", 39878 /* IDB_OBM7_THRESHOLD_1 */ "", 39879 /* IDB_OBM7_THRESHOLD_1_PIPE0 */ "", 39880 /* IDB_OBM7_THRESHOLD_1_PIPE1 */ "", 39881 /* IDB_OBM7_THRESHOLD_1_PIPE2 */ "", 39882 /* IDB_OBM7_THRESHOLD_1_PIPE3 */ "", 39883 /* IDB_OBM7_THRESHOLD_PIPE0 */ "", 39884 /* IDB_OBM7_THRESHOLD_PIPE1 */ "", 39885 /* IDB_OBM7_THRESHOLD_PIPE2 */ "", 39886 /* IDB_OBM7_THRESHOLD_PIPE3 */ "", 39887 /* IDB_OBM7_USAGE */ "", 39888 /* IDB_OBM7_USAGE_PIPE0 */ "", 39889 /* IDB_OBM7_USAGE_PIPE1 */ "", 39890 /* IDB_OBM7_USAGE_PIPE2 */ "", 39891 /* IDB_OBM7_USAGE_PIPE3 */ "", 39892 /* IDB_OBM8_BANK_CONFIG */ "IDB_OBM8_BANK_CONFIG", 39893 /* IDB_OBM8_BANK_CONFIG_PIPE0 */ "IDB_OBM8_BANK_CONFIG_PIPE0", 39894 /* IDB_OBM8_BANK_CONFIG_PIPE1 */ "IDB_OBM8_BANK_CONFIG_PIPE1", 39895 /* IDB_OBM8_BANK_CONFIG_PIPE2 */ "IDB_OBM8_BANK_CONFIG_PIPE2", 39896 /* IDB_OBM8_BANK_CONFIG_PIPE3 */ "IDB_OBM8_BANK_CONFIG_PIPE3", 39897 /* IDB_OBM8_BUFFER_CONFIG */ "", 39898 /* IDB_OBM8_BUFFER_CONFIG_PIPE0 */ "", 39899 /* IDB_OBM8_BUFFER_CONFIG_PIPE1 */ "", 39900 /* IDB_OBM8_CA_CONTROL */ "IDB_OBM8_CA_CONTROL", 39901 /* IDB_OBM8_CA_CONTROL_PIPE0 */ "IDB_OBM8_CA_CONTROL_PIPE0", 39902 /* IDB_OBM8_CA_CONTROL_PIPE1 */ "IDB_OBM8_CA_CONTROL_PIPE1", 39903 /* IDB_OBM8_CA_CONTROL_PIPE2 */ "IDB_OBM8_CA_CONTROL_PIPE2", 39904 /* IDB_OBM8_CA_CONTROL_PIPE3 */ "IDB_OBM8_CA_CONTROL_PIPE3", 39905 /* IDB_OBM8_CA_CT_CONTROL */ "IDB_OBM8_CA_CT_CONTROL", 39906 /* IDB_OBM8_CA_CT_CONTROL_PIPE0 */ "IDB_OBM8_CA_CT_CONTROL_PIPE0", 39907 /* IDB_OBM8_CA_CT_CONTROL_PIPE1 */ "IDB_OBM8_CA_CT_CONTROL_PIPE1", 39908 /* IDB_OBM8_CA_CT_CONTROL_PIPE2 */ "IDB_OBM8_CA_CT_CONTROL_PIPE2", 39909 /* IDB_OBM8_CA_CT_CONTROL_PIPE3 */ "IDB_OBM8_CA_CT_CONTROL_PIPE3", 39910 /* IDB_OBM8_CA_ECC_STATUS */ "IDB_OBM8_CA_ECC_STATUS", 39911 /* IDB_OBM8_CA_ECC_STATUS_PIPE0 */ "IDB_OBM8_CA_ECC_STATUS_PIPE0", 39912 /* IDB_OBM8_CA_ECC_STATUS_PIPE1 */ "IDB_OBM8_CA_ECC_STATUS_PIPE1", 39913 /* IDB_OBM8_CA_ECC_STATUS_PIPE2 */ "IDB_OBM8_CA_ECC_STATUS_PIPE2", 39914 /* IDB_OBM8_CA_ECC_STATUS_PIPE3 */ "IDB_OBM8_CA_ECC_STATUS_PIPE3", 39915 /* IDB_OBM8_CA_HW_STATUS */ "IDB_OBM8_CA_HW_STATUS", 39916 /* IDB_OBM8_CA_HW_STATUS_PIPE0 */ "IDB_OBM8_CA_HW_STATUS_PIPE0", 39917 /* IDB_OBM8_CA_HW_STATUS_PIPE1 */ "IDB_OBM8_CA_HW_STATUS_PIPE1", 39918 /* IDB_OBM8_CA_HW_STATUS_PIPE2 */ "IDB_OBM8_CA_HW_STATUS_PIPE2", 39919 /* IDB_OBM8_CA_HW_STATUS_PIPE3 */ "IDB_OBM8_CA_HW_STATUS_PIPE3", 39920 /* IDB_OBM8_CA_POINTER_STATUS */ "IDB_OBM8_CA_POINTER_STATUS", 39921 /* IDB_OBM8_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM8_CA_POINTER_STATUS_PIPE0", 39922 /* IDB_OBM8_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM8_CA_POINTER_STATUS_PIPE1", 39923 /* IDB_OBM8_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM8_CA_POINTER_STATUS_PIPE2", 39924 /* IDB_OBM8_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM8_CA_POINTER_STATUS_PIPE3", 39925 /* IDB_OBM8_CONTROL */ "IDB_OBM8_CONTROL", 39926 /* IDB_OBM8_CONTROL_PIPE0 */ "IDB_OBM8_CONTROL_PIPE0", 39927 /* IDB_OBM8_CONTROL_PIPE1 */ "IDB_OBM8_CONTROL_PIPE1", 39928 /* IDB_OBM8_CONTROL_PIPE2 */ "IDB_OBM8_CONTROL_PIPE2", 39929 /* IDB_OBM8_CONTROL_PIPE3 */ "IDB_OBM8_CONTROL_PIPE3", 39930 /* IDB_OBM8_CT_THRESHOLD */ "", 39931 /* IDB_OBM8_CT_THRESHOLD_PIPE0 */ "", 39932 /* IDB_OBM8_CT_THRESHOLD_PIPE1 */ "", 39933 /* IDB_OBM8_CT_THRESHOLD_PIPE2 */ "", 39934 /* IDB_OBM8_CT_THRESHOLD_PIPE3 */ "", 39935 /* IDB_OBM8_DATA_ECC_STATUS */ "IDB_OBM8_DATA_ECC_STATUS", 39936 /* IDB_OBM8_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM8_DATA_ECC_STATUS_PIPE0", 39937 /* IDB_OBM8_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM8_DATA_ECC_STATUS_PIPE1", 39938 /* IDB_OBM8_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM8_DATA_ECC_STATUS_PIPE2", 39939 /* IDB_OBM8_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM8_DATA_ECC_STATUS_PIPE3", 39940 /* IDB_OBM8_DBG_A */ "IDB_OBM8_FORCE_SAF_CONFIG", 39941 /* IDB_OBM8_DBG_A_PIPE0 */ "IDB_OBM8_FORCE_SAF_CONFIG_PIPE0", 39942 /* IDB_OBM8_DBG_A_PIPE1 */ "IDB_OBM8_FORCE_SAF_CONFIG_PIPE1", 39943 /* IDB_OBM8_DBG_A_PIPE2 */ "IDB_OBM8_FORCE_SAF_CONFIG_PIPE2", 39944 /* IDB_OBM8_DBG_A_PIPE3 */ "IDB_OBM8_FORCE_SAF_CONFIG_PIPE3", 39945 /* IDB_OBM8_FC_THRESHOLD */ "", 39946 /* IDB_OBM8_FC_THRESHOLD_1 */ "", 39947 /* IDB_OBM8_FC_THRESHOLD_1_PIPE0 */ "", 39948 /* IDB_OBM8_FC_THRESHOLD_1_PIPE1 */ "", 39949 /* IDB_OBM8_FC_THRESHOLD_1_PIPE2 */ "", 39950 /* IDB_OBM8_FC_THRESHOLD_1_PIPE3 */ "", 39951 /* IDB_OBM8_FC_THRESHOLD_PIPE0 */ "", 39952 /* IDB_OBM8_FC_THRESHOLD_PIPE1 */ "", 39953 /* IDB_OBM8_FC_THRESHOLD_PIPE2 */ "", 39954 /* IDB_OBM8_FC_THRESHOLD_PIPE3 */ "", 39955 /* IDB_OBM8_FLOW_CONTROL_CONFIG */ "", 39956 /* IDB_OBM8_FLOW_CONTROL_CONFIG_PIPE0 */ "", 39957 /* IDB_OBM8_FLOW_CONTROL_CONFIG_PIPE1 */ "", 39958 /* IDB_OBM8_FLOW_CONTROL_CONFIG_PIPE2 */ "", 39959 /* IDB_OBM8_FLOW_CONTROL_CONFIG_PIPE3 */ "", 39960 /* IDB_OBM8_FLOW_CONTROL_EVENT_COUNT */ "", 39961 /* IDB_OBM8_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 39962 /* IDB_OBM8_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 39963 /* IDB_OBM8_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 39964 /* IDB_OBM8_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 39965 /* IDB_OBM8_FORCE_SAF_STATUS */ "", 39966 /* IDB_OBM8_FORCE_SAF_STATUS_PIPE0 */ "", 39967 /* IDB_OBM8_FORCE_SAF_STATUS_PIPE1 */ "", 39968 /* IDB_OBM8_INNER_TPID */ "", 39969 /* IDB_OBM8_INNER_TPID_PIPE0 */ "", 39970 /* IDB_OBM8_INNER_TPID_PIPE1 */ "", 39971 /* IDB_OBM8_INNER_TPID_PIPE2 */ "", 39972 /* IDB_OBM8_INNER_TPID_PIPE3 */ "", 39973 /* IDB_OBM8_LOSSLESS0_BYTE_DROP_COUNT */ "", 39974 /* IDB_OBM8_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 39975 /* IDB_OBM8_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 39976 /* IDB_OBM8_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 39977 /* IDB_OBM8_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 39978 /* IDB_OBM8_LOSSLESS0_PKT_DROP_COUNT */ "", 39979 /* IDB_OBM8_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 39980 /* IDB_OBM8_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 39981 /* IDB_OBM8_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 39982 /* IDB_OBM8_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 39983 /* IDB_OBM8_LOSSLESS1_BYTE_DROP_COUNT */ "", 39984 /* IDB_OBM8_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 39985 /* IDB_OBM8_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 39986 /* IDB_OBM8_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 39987 /* IDB_OBM8_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 39988 /* IDB_OBM8_LOSSLESS1_PKT_DROP_COUNT */ "", 39989 /* IDB_OBM8_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 39990 /* IDB_OBM8_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 39991 /* IDB_OBM8_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 39992 /* IDB_OBM8_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 39993 /* IDB_OBM8_LOSSY_HI_BYTE_DROP_COUNT */ "", 39994 /* IDB_OBM8_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 39995 /* IDB_OBM8_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 39996 /* IDB_OBM8_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 39997 /* IDB_OBM8_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 39998 /* IDB_OBM8_LOSSY_HI_PKT_DROP_COUNT */ "", 39999 /* IDB_OBM8_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 40000 /* IDB_OBM8_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 40001 /* IDB_OBM8_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 40002 /* IDB_OBM8_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 40003 /* IDB_OBM8_LOSSY_LO_BYTE_DROP_COUNT */ "", 40004 /* IDB_OBM8_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 40005 /* IDB_OBM8_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 40006 /* IDB_OBM8_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 40007 /* IDB_OBM8_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 40008 /* IDB_OBM8_LOSSY_LO_PKT_DROP_COUNT */ "", 40009 /* IDB_OBM8_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 40010 /* IDB_OBM8_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 40011 /* IDB_OBM8_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 40012 /* IDB_OBM8_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 40013 /* IDB_OBM8_MAX_USAGE */ "IDB_OBM8_MAX_USAGE", 40014 /* IDB_OBM8_MAX_USAGE_1 */ "IDB_OBM8_MAX_USAGE_1", 40015 /* IDB_OBM8_MAX_USAGE_1_PIPE0 */ "IDB_OBM8_MAX_USAGE_1_PIPE0", 40016 /* IDB_OBM8_MAX_USAGE_1_PIPE1 */ "IDB_OBM8_MAX_USAGE_1_PIPE1", 40017 /* IDB_OBM8_MAX_USAGE_1_PIPE2 */ "IDB_OBM8_MAX_USAGE_1_PIPE2", 40018 /* IDB_OBM8_MAX_USAGE_1_PIPE3 */ "IDB_OBM8_MAX_USAGE_1_PIPE3", 40019 /* IDB_OBM8_MAX_USAGE_PIPE0 */ "IDB_OBM8_MAX_USAGE_PIPE0", 40020 /* IDB_OBM8_MAX_USAGE_PIPE1 */ "IDB_OBM8_MAX_USAGE_PIPE1", 40021 /* IDB_OBM8_MAX_USAGE_PIPE2 */ "IDB_OBM8_MAX_USAGE_PIPE2", 40022 /* IDB_OBM8_MAX_USAGE_PIPE3 */ "IDB_OBM8_MAX_USAGE_PIPE3", 40023 /* IDB_OBM8_MAX_USAGE_SELECT */ "", 40024 /* IDB_OBM8_MAX_USAGE_SELECT_PIPE0 */ "", 40025 /* IDB_OBM8_MAX_USAGE_SELECT_PIPE1 */ "", 40026 /* IDB_OBM8_MAX_USAGE_SELECT_PIPE2 */ "", 40027 /* IDB_OBM8_MAX_USAGE_SELECT_PIPE3 */ "", 40028 /* IDB_OBM8_NIV_ETHERTYPE */ "", 40029 /* IDB_OBM8_NIV_ETHERTYPE_PIPE0 */ "", 40030 /* IDB_OBM8_NIV_ETHERTYPE_PIPE1 */ "", 40031 /* IDB_OBM8_NIV_ETHERTYPE_PIPE2 */ "", 40032 /* IDB_OBM8_NIV_ETHERTYPE_PIPE3 */ "", 40033 /* IDB_OBM8_OUTER_TPID */ "", 40034 /* IDB_OBM8_OUTER_TPID_0 */ "", 40035 /* IDB_OBM8_OUTER_TPID_1 */ "", 40036 /* IDB_OBM8_OUTER_TPID_2 */ "", 40037 /* IDB_OBM8_OUTER_TPID_3 */ "", 40038 /* IDB_OBM8_OUTER_TPID_0_PIPE0 */ "", 40039 /* IDB_OBM8_OUTER_TPID_0_PIPE1 */ "", 40040 /* IDB_OBM8_OUTER_TPID_0_PIPE2 */ "", 40041 /* IDB_OBM8_OUTER_TPID_0_PIPE3 */ "", 40042 /* IDB_OBM8_OUTER_TPID_1_PIPE0 */ "", 40043 /* IDB_OBM8_OUTER_TPID_1_PIPE1 */ "", 40044 /* IDB_OBM8_OUTER_TPID_1_PIPE2 */ "", 40045 /* IDB_OBM8_OUTER_TPID_1_PIPE3 */ "", 40046 /* IDB_OBM8_OUTER_TPID_2_PIPE0 */ "", 40047 /* IDB_OBM8_OUTER_TPID_2_PIPE1 */ "", 40048 /* IDB_OBM8_OUTER_TPID_2_PIPE2 */ "", 40049 /* IDB_OBM8_OUTER_TPID_2_PIPE3 */ "", 40050 /* IDB_OBM8_OUTER_TPID_3_PIPE0 */ "", 40051 /* IDB_OBM8_OUTER_TPID_3_PIPE1 */ "", 40052 /* IDB_OBM8_OUTER_TPID_3_PIPE2 */ "", 40053 /* IDB_OBM8_OUTER_TPID_3_PIPE3 */ "", 40054 /* IDB_OBM8_OUTER_TPID_PIPE0 */ "", 40055 /* IDB_OBM8_OUTER_TPID_PIPE1 */ "", 40056 /* IDB_OBM8_OUTER_TPID_PIPE2 */ "", 40057 /* IDB_OBM8_OUTER_TPID_PIPE3 */ "", 40058 /* IDB_OBM8_OVERSUB_MON_ECC_STATUS */ "IDB_OBM8_OVERSUB_MON_ECC_STATUS", 40059 /* IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE0", 40060 /* IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE1", 40061 /* IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE2", 40062 /* IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM8_OVERSUB_MON_ECC_STATUS_PIPE3", 40063 /* IDB_OBM8_OVERSUB_MON_PARITY_STATUS */ "IDB_OBM8_OVERSUB_MON_PARITY_STATUS", 40064 /* IDB_OBM8_PE_ETHERTYPE */ "", 40065 /* IDB_OBM8_PE_ETHERTYPE_PIPE0 */ "", 40066 /* IDB_OBM8_PE_ETHERTYPE_PIPE1 */ "", 40067 /* IDB_OBM8_PE_ETHERTYPE_PIPE2 */ "", 40068 /* IDB_OBM8_PE_ETHERTYPE_PIPE3 */ "", 40069 /* IDB_OBM8_PORT_CONFIG */ "", 40070 /* IDB_OBM8_PORT_CONFIG_PIPE0 */ "", 40071 /* IDB_OBM8_PORT_CONFIG_PIPE1 */ "", 40072 /* IDB_OBM8_PORT_CONFIG_PIPE2 */ "", 40073 /* IDB_OBM8_PORT_CONFIG_PIPE3 */ "", 40074 /* IDB_OBM8_POWER_SAVE */ "IDB_OBM8_POWER_SAVE", 40075 /* IDB_OBM8_PROTOCOL_CONTROL_0 */ "", 40076 /* IDB_OBM8_PROTOCOL_CONTROL_1 */ "", 40077 /* IDB_OBM8_PROTOCOL_CONTROL_2 */ "", 40078 /* IDB_OBM8_PROTOCOL_CONTROL_0_PIPE0 */ "", 40079 /* IDB_OBM8_PROTOCOL_CONTROL_0_PIPE1 */ "", 40080 /* IDB_OBM8_PROTOCOL_CONTROL_0_PIPE2 */ "", 40081 /* IDB_OBM8_PROTOCOL_CONTROL_0_PIPE3 */ "", 40082 /* IDB_OBM8_PROTOCOL_CONTROL_1_PIPE0 */ "", 40083 /* IDB_OBM8_PROTOCOL_CONTROL_1_PIPE1 */ "", 40084 /* IDB_OBM8_PROTOCOL_CONTROL_1_PIPE2 */ "", 40085 /* IDB_OBM8_PROTOCOL_CONTROL_1_PIPE3 */ "", 40086 /* IDB_OBM8_PROTOCOL_CONTROL_2_PIPE0 */ "", 40087 /* IDB_OBM8_PROTOCOL_CONTROL_2_PIPE1 */ "", 40088 /* IDB_OBM8_PROTOCOL_CONTROL_2_PIPE2 */ "", 40089 /* IDB_OBM8_PROTOCOL_CONTROL_2_PIPE3 */ "", 40090 /* IDB_OBM8_QUEUE_ECC_STATUS */ "IDB_OBM8_QUEUE_ECC_STATUS", 40091 /* IDB_OBM8_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM8_QUEUE_ECC_STATUS_PIPE0", 40092 /* IDB_OBM8_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM8_QUEUE_ECC_STATUS_PIPE1", 40093 /* IDB_OBM8_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM8_QUEUE_ECC_STATUS_PIPE2", 40094 /* IDB_OBM8_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM8_QUEUE_ECC_STATUS_PIPE3", 40095 /* IDB_OBM8_QUEUE_SER_CONTROL */ "IDB_OBM8_QUEUE_SER_CONTROL", 40096 /* IDB_OBM8_RAM_CONTROL */ "IDB_OBM8_RAM_CONTROL", 40097 /* IDB_OBM8_RAM_CONTROL_PIPE0 */ "IDB_OBM8_RAM_CONTROL_PIPE0", 40098 /* IDB_OBM8_RAM_CONTROL_PIPE1 */ "IDB_OBM8_RAM_CONTROL_PIPE1", 40099 /* IDB_OBM8_RAM_CONTROL_PIPE2 */ "IDB_OBM8_RAM_CONTROL_PIPE2", 40100 /* IDB_OBM8_RAM_CONTROL_PIPE3 */ "IDB_OBM8_RAM_CONTROL_PIPE3", 40101 /* IDB_OBM8_SER_CONTROL */ "IDB_OBM8_SER_CONTROL", 40102 /* IDB_OBM8_SER_CONTROL_PIPE0 */ "IDB_OBM8_SER_CONTROL_PIPE0", 40103 /* IDB_OBM8_SER_CONTROL_PIPE1 */ "IDB_OBM8_SER_CONTROL_PIPE1", 40104 /* IDB_OBM8_SHARED_CONFIG */ "IDB_OBM8_SHARED_CONFIG", 40105 /* IDB_OBM8_SHARED_CONFIG_PIPE0 */ "IDB_OBM8_SHARED_CONFIG_PIPE0", 40106 /* IDB_OBM8_SHARED_CONFIG_PIPE1 */ "IDB_OBM8_SHARED_CONFIG_PIPE1", 40107 /* IDB_OBM8_SHARED_CONFIG_PIPE2 */ "IDB_OBM8_SHARED_CONFIG_PIPE2", 40108 /* IDB_OBM8_SHARED_CONFIG_PIPE3 */ "IDB_OBM8_SHARED_CONFIG_PIPE3", 40109 /* IDB_OBM8_SHARED_USAGE */ "IDB_OBM8_SHARED_USAGE", 40110 /* IDB_OBM8_SHARED_USAGE_PIPE0 */ "IDB_OBM8_SHARED_USAGE_PIPE0", 40111 /* IDB_OBM8_SHARED_USAGE_PIPE1 */ "IDB_OBM8_SHARED_USAGE_PIPE1", 40112 /* IDB_OBM8_SHARED_USAGE_PIPE2 */ "IDB_OBM8_SHARED_USAGE_PIPE2", 40113 /* IDB_OBM8_SHARED_USAGE_PIPE3 */ "IDB_OBM8_SHARED_USAGE_PIPE3", 40114 /* IDB_OBM8_SPARE_REG */ "IDB_OBM8_SPARE_REG", 40115 /* IDB_OBM8_THRESHOLD */ "", 40116 /* IDB_OBM8_THRESHOLD_1 */ "", 40117 /* IDB_OBM8_THRESHOLD_1_PIPE0 */ "", 40118 /* IDB_OBM8_THRESHOLD_1_PIPE1 */ "", 40119 /* IDB_OBM8_THRESHOLD_1_PIPE2 */ "", 40120 /* IDB_OBM8_THRESHOLD_1_PIPE3 */ "", 40121 /* IDB_OBM8_THRESHOLD_PIPE0 */ "", 40122 /* IDB_OBM8_THRESHOLD_PIPE1 */ "", 40123 /* IDB_OBM8_THRESHOLD_PIPE2 */ "", 40124 /* IDB_OBM8_THRESHOLD_PIPE3 */ "", 40125 /* IDB_OBM8_USAGE */ "", 40126 /* IDB_OBM8_USAGE_PIPE0 */ "", 40127 /* IDB_OBM8_USAGE_PIPE1 */ "", 40128 /* IDB_OBM8_USAGE_PIPE2 */ "", 40129 /* IDB_OBM8_USAGE_PIPE3 */ "", 40130 /* IDB_OBM9_BANK_CONFIG */ "IDB_OBM9_BANK_CONFIG", 40131 /* IDB_OBM9_BANK_CONFIG_PIPE0 */ "IDB_OBM9_BANK_CONFIG_PIPE0", 40132 /* IDB_OBM9_BANK_CONFIG_PIPE1 */ "IDB_OBM9_BANK_CONFIG_PIPE1", 40133 /* IDB_OBM9_BANK_CONFIG_PIPE2 */ "IDB_OBM9_BANK_CONFIG_PIPE2", 40134 /* IDB_OBM9_BANK_CONFIG_PIPE3 */ "IDB_OBM9_BANK_CONFIG_PIPE3", 40135 /* IDB_OBM9_BUFFER_CONFIG */ "", 40136 /* IDB_OBM9_BUFFER_CONFIG_PIPE0 */ "", 40137 /* IDB_OBM9_BUFFER_CONFIG_PIPE1 */ "", 40138 /* IDB_OBM9_CA_CONTROL */ "IDB_OBM9_CA_CONTROL", 40139 /* IDB_OBM9_CA_CONTROL_PIPE0 */ "IDB_OBM9_CA_CONTROL_PIPE0", 40140 /* IDB_OBM9_CA_CONTROL_PIPE1 */ "IDB_OBM9_CA_CONTROL_PIPE1", 40141 /* IDB_OBM9_CA_CONTROL_PIPE2 */ "IDB_OBM9_CA_CONTROL_PIPE2", 40142 /* IDB_OBM9_CA_CONTROL_PIPE3 */ "IDB_OBM9_CA_CONTROL_PIPE3", 40143 /* IDB_OBM9_CA_CT_CONTROL */ "IDB_OBM9_CA_CT_CONTROL", 40144 /* IDB_OBM9_CA_CT_CONTROL_PIPE0 */ "IDB_OBM9_CA_CT_CONTROL_PIPE0", 40145 /* IDB_OBM9_CA_CT_CONTROL_PIPE1 */ "IDB_OBM9_CA_CT_CONTROL_PIPE1", 40146 /* IDB_OBM9_CA_CT_CONTROL_PIPE2 */ "IDB_OBM9_CA_CT_CONTROL_PIPE2", 40147 /* IDB_OBM9_CA_CT_CONTROL_PIPE3 */ "IDB_OBM9_CA_CT_CONTROL_PIPE3", 40148 /* IDB_OBM9_CA_ECC_STATUS */ "IDB_OBM9_CA_ECC_STATUS", 40149 /* IDB_OBM9_CA_ECC_STATUS_PIPE0 */ "IDB_OBM9_CA_ECC_STATUS_PIPE0", 40150 /* IDB_OBM9_CA_ECC_STATUS_PIPE1 */ "IDB_OBM9_CA_ECC_STATUS_PIPE1", 40151 /* IDB_OBM9_CA_ECC_STATUS_PIPE2 */ "IDB_OBM9_CA_ECC_STATUS_PIPE2", 40152 /* IDB_OBM9_CA_ECC_STATUS_PIPE3 */ "IDB_OBM9_CA_ECC_STATUS_PIPE3", 40153 /* IDB_OBM9_CA_HW_STATUS */ "IDB_OBM9_CA_HW_STATUS", 40154 /* IDB_OBM9_CA_HW_STATUS_PIPE0 */ "IDB_OBM9_CA_HW_STATUS_PIPE0", 40155 /* IDB_OBM9_CA_HW_STATUS_PIPE1 */ "IDB_OBM9_CA_HW_STATUS_PIPE1", 40156 /* IDB_OBM9_CA_HW_STATUS_PIPE2 */ "IDB_OBM9_CA_HW_STATUS_PIPE2", 40157 /* IDB_OBM9_CA_HW_STATUS_PIPE3 */ "IDB_OBM9_CA_HW_STATUS_PIPE3", 40158 /* IDB_OBM9_CA_POINTER_STATUS */ "IDB_OBM9_CA_POINTER_STATUS", 40159 /* IDB_OBM9_CA_POINTER_STATUS_PIPE0 */ "IDB_OBM9_CA_POINTER_STATUS_PIPE0", 40160 /* IDB_OBM9_CA_POINTER_STATUS_PIPE1 */ "IDB_OBM9_CA_POINTER_STATUS_PIPE1", 40161 /* IDB_OBM9_CA_POINTER_STATUS_PIPE2 */ "IDB_OBM9_CA_POINTER_STATUS_PIPE2", 40162 /* IDB_OBM9_CA_POINTER_STATUS_PIPE3 */ "IDB_OBM9_CA_POINTER_STATUS_PIPE3", 40163 /* IDB_OBM9_CONTROL */ "IDB_OBM9_CONTROL", 40164 /* IDB_OBM9_CONTROL_PIPE0 */ "IDB_OBM9_CONTROL_PIPE0", 40165 /* IDB_OBM9_CONTROL_PIPE1 */ "IDB_OBM9_CONTROL_PIPE1", 40166 /* IDB_OBM9_CONTROL_PIPE2 */ "IDB_OBM9_CONTROL_PIPE2", 40167 /* IDB_OBM9_CONTROL_PIPE3 */ "IDB_OBM9_CONTROL_PIPE3", 40168 /* IDB_OBM9_CT_THRESHOLD */ "", 40169 /* IDB_OBM9_CT_THRESHOLD_PIPE0 */ "", 40170 /* IDB_OBM9_CT_THRESHOLD_PIPE1 */ "", 40171 /* IDB_OBM9_CT_THRESHOLD_PIPE2 */ "", 40172 /* IDB_OBM9_CT_THRESHOLD_PIPE3 */ "", 40173 /* IDB_OBM9_DATA_ECC_STATUS */ "IDB_OBM9_DATA_ECC_STATUS", 40174 /* IDB_OBM9_DATA_ECC_STATUS_PIPE0 */ "IDB_OBM9_DATA_ECC_STATUS_PIPE0", 40175 /* IDB_OBM9_DATA_ECC_STATUS_PIPE1 */ "IDB_OBM9_DATA_ECC_STATUS_PIPE1", 40176 /* IDB_OBM9_DATA_ECC_STATUS_PIPE2 */ "IDB_OBM9_DATA_ECC_STATUS_PIPE2", 40177 /* IDB_OBM9_DATA_ECC_STATUS_PIPE3 */ "IDB_OBM9_DATA_ECC_STATUS_PIPE3", 40178 /* IDB_OBM9_DBG_A */ "IDB_OBM9_FORCE_SAF_CONFIG", 40179 /* IDB_OBM9_DBG_A_PIPE0 */ "IDB_OBM9_FORCE_SAF_CONFIG_PIPE0", 40180 /* IDB_OBM9_DBG_A_PIPE1 */ "IDB_OBM9_FORCE_SAF_CONFIG_PIPE1", 40181 /* IDB_OBM9_DBG_A_PIPE2 */ "IDB_OBM9_FORCE_SAF_CONFIG_PIPE2", 40182 /* IDB_OBM9_DBG_A_PIPE3 */ "IDB_OBM9_FORCE_SAF_CONFIG_PIPE3", 40183 /* IDB_OBM9_FC_THRESHOLD */ "", 40184 /* IDB_OBM9_FC_THRESHOLD_1 */ "", 40185 /* IDB_OBM9_FC_THRESHOLD_1_PIPE0 */ "", 40186 /* IDB_OBM9_FC_THRESHOLD_1_PIPE1 */ "", 40187 /* IDB_OBM9_FC_THRESHOLD_1_PIPE2 */ "", 40188 /* IDB_OBM9_FC_THRESHOLD_1_PIPE3 */ "", 40189 /* IDB_OBM9_FC_THRESHOLD_PIPE0 */ "", 40190 /* IDB_OBM9_FC_THRESHOLD_PIPE1 */ "", 40191 /* IDB_OBM9_FC_THRESHOLD_PIPE2 */ "", 40192 /* IDB_OBM9_FC_THRESHOLD_PIPE3 */ "", 40193 /* IDB_OBM9_FLOW_CONTROL_CONFIG */ "", 40194 /* IDB_OBM9_FLOW_CONTROL_CONFIG_PIPE0 */ "", 40195 /* IDB_OBM9_FLOW_CONTROL_CONFIG_PIPE1 */ "", 40196 /* IDB_OBM9_FLOW_CONTROL_CONFIG_PIPE2 */ "", 40197 /* IDB_OBM9_FLOW_CONTROL_CONFIG_PIPE3 */ "", 40198 /* IDB_OBM9_FLOW_CONTROL_EVENT_COUNT */ "", 40199 /* IDB_OBM9_FLOW_CONTROL_EVENT_COUNT_PIPE0 */ "", 40200 /* IDB_OBM9_FLOW_CONTROL_EVENT_COUNT_PIPE1 */ "", 40201 /* IDB_OBM9_FLOW_CONTROL_EVENT_COUNT_PIPE2 */ "", 40202 /* IDB_OBM9_FLOW_CONTROL_EVENT_COUNT_PIPE3 */ "", 40203 /* IDB_OBM9_FORCE_SAF_STATUS */ "", 40204 /* IDB_OBM9_FORCE_SAF_STATUS_PIPE0 */ "", 40205 /* IDB_OBM9_FORCE_SAF_STATUS_PIPE1 */ "", 40206 /* IDB_OBM9_INNER_TPID */ "", 40207 /* IDB_OBM9_INNER_TPID_PIPE0 */ "", 40208 /* IDB_OBM9_INNER_TPID_PIPE1 */ "", 40209 /* IDB_OBM9_INNER_TPID_PIPE2 */ "", 40210 /* IDB_OBM9_INNER_TPID_PIPE3 */ "", 40211 /* IDB_OBM9_LOSSLESS0_BYTE_DROP_COUNT */ "", 40212 /* IDB_OBM9_LOSSLESS0_BYTE_DROP_COUNT_PIPE0 */ "", 40213 /* IDB_OBM9_LOSSLESS0_BYTE_DROP_COUNT_PIPE1 */ "", 40214 /* IDB_OBM9_LOSSLESS0_BYTE_DROP_COUNT_PIPE2 */ "", 40215 /* IDB_OBM9_LOSSLESS0_BYTE_DROP_COUNT_PIPE3 */ "", 40216 /* IDB_OBM9_LOSSLESS0_PKT_DROP_COUNT */ "", 40217 /* IDB_OBM9_LOSSLESS0_PKT_DROP_COUNT_PIPE0 */ "", 40218 /* IDB_OBM9_LOSSLESS0_PKT_DROP_COUNT_PIPE1 */ "", 40219 /* IDB_OBM9_LOSSLESS0_PKT_DROP_COUNT_PIPE2 */ "", 40220 /* IDB_OBM9_LOSSLESS0_PKT_DROP_COUNT_PIPE3 */ "", 40221 /* IDB_OBM9_LOSSLESS1_BYTE_DROP_COUNT */ "", 40222 /* IDB_OBM9_LOSSLESS1_BYTE_DROP_COUNT_PIPE0 */ "", 40223 /* IDB_OBM9_LOSSLESS1_BYTE_DROP_COUNT_PIPE1 */ "", 40224 /* IDB_OBM9_LOSSLESS1_BYTE_DROP_COUNT_PIPE2 */ "", 40225 /* IDB_OBM9_LOSSLESS1_BYTE_DROP_COUNT_PIPE3 */ "", 40226 /* IDB_OBM9_LOSSLESS1_PKT_DROP_COUNT */ "", 40227 /* IDB_OBM9_LOSSLESS1_PKT_DROP_COUNT_PIPE0 */ "", 40228 /* IDB_OBM9_LOSSLESS1_PKT_DROP_COUNT_PIPE1 */ "", 40229 /* IDB_OBM9_LOSSLESS1_PKT_DROP_COUNT_PIPE2 */ "", 40230 /* IDB_OBM9_LOSSLESS1_PKT_DROP_COUNT_PIPE3 */ "", 40231 /* IDB_OBM9_LOSSY_HI_BYTE_DROP_COUNT */ "", 40232 /* IDB_OBM9_LOSSY_HI_BYTE_DROP_COUNT_PIPE0 */ "", 40233 /* IDB_OBM9_LOSSY_HI_BYTE_DROP_COUNT_PIPE1 */ "", 40234 /* IDB_OBM9_LOSSY_HI_BYTE_DROP_COUNT_PIPE2 */ "", 40235 /* IDB_OBM9_LOSSY_HI_BYTE_DROP_COUNT_PIPE3 */ "", 40236 /* IDB_OBM9_LOSSY_HI_PKT_DROP_COUNT */ "", 40237 /* IDB_OBM9_LOSSY_HI_PKT_DROP_COUNT_PIPE0 */ "", 40238 /* IDB_OBM9_LOSSY_HI_PKT_DROP_COUNT_PIPE1 */ "", 40239 /* IDB_OBM9_LOSSY_HI_PKT_DROP_COUNT_PIPE2 */ "", 40240 /* IDB_OBM9_LOSSY_HI_PKT_DROP_COUNT_PIPE3 */ "", 40241 /* IDB_OBM9_LOSSY_LO_BYTE_DROP_COUNT */ "", 40242 /* IDB_OBM9_LOSSY_LO_BYTE_DROP_COUNT_PIPE0 */ "", 40243 /* IDB_OBM9_LOSSY_LO_BYTE_DROP_COUNT_PIPE1 */ "", 40244 /* IDB_OBM9_LOSSY_LO_BYTE_DROP_COUNT_PIPE2 */ "", 40245 /* IDB_OBM9_LOSSY_LO_BYTE_DROP_COUNT_PIPE3 */ "", 40246 /* IDB_OBM9_LOSSY_LO_PKT_DROP_COUNT */ "", 40247 /* IDB_OBM9_LOSSY_LO_PKT_DROP_COUNT_PIPE0 */ "", 40248 /* IDB_OBM9_LOSSY_LO_PKT_DROP_COUNT_PIPE1 */ "", 40249 /* IDB_OBM9_LOSSY_LO_PKT_DROP_COUNT_PIPE2 */ "", 40250 /* IDB_OBM9_LOSSY_LO_PKT_DROP_COUNT_PIPE3 */ "", 40251 /* IDB_OBM9_MAX_USAGE */ "IDB_OBM9_MAX_USAGE", 40252 /* IDB_OBM9_MAX_USAGE_1 */ "IDB_OBM9_MAX_USAGE_1", 40253 /* IDB_OBM9_MAX_USAGE_1_PIPE0 */ "IDB_OBM9_MAX_USAGE_1_PIPE0", 40254 /* IDB_OBM9_MAX_USAGE_1_PIPE1 */ "IDB_OBM9_MAX_USAGE_1_PIPE1", 40255 /* IDB_OBM9_MAX_USAGE_1_PIPE2 */ "IDB_OBM9_MAX_USAGE_1_PIPE2", 40256 /* IDB_OBM9_MAX_USAGE_1_PIPE3 */ "IDB_OBM9_MAX_USAGE_1_PIPE3", 40257 /* IDB_OBM9_MAX_USAGE_PIPE0 */ "IDB_OBM9_MAX_USAGE_PIPE0", 40258 /* IDB_OBM9_MAX_USAGE_PIPE1 */ "IDB_OBM9_MAX_USAGE_PIPE1", 40259 /* IDB_OBM9_MAX_USAGE_PIPE2 */ "IDB_OBM9_MAX_USAGE_PIPE2", 40260 /* IDB_OBM9_MAX_USAGE_PIPE3 */ "IDB_OBM9_MAX_USAGE_PIPE3", 40261 /* IDB_OBM9_MAX_USAGE_SELECT */ "", 40262 /* IDB_OBM9_MAX_USAGE_SELECT_PIPE0 */ "", 40263 /* IDB_OBM9_MAX_USAGE_SELECT_PIPE1 */ "", 40264 /* IDB_OBM9_MAX_USAGE_SELECT_PIPE2 */ "", 40265 /* IDB_OBM9_MAX_USAGE_SELECT_PIPE3 */ "", 40266 /* IDB_OBM9_NIV_ETHERTYPE */ "", 40267 /* IDB_OBM9_NIV_ETHERTYPE_PIPE0 */ "", 40268 /* IDB_OBM9_NIV_ETHERTYPE_PIPE1 */ "", 40269 /* IDB_OBM9_NIV_ETHERTYPE_PIPE2 */ "", 40270 /* IDB_OBM9_NIV_ETHERTYPE_PIPE3 */ "", 40271 /* IDB_OBM9_OUTER_TPID */ "", 40272 /* IDB_OBM9_OUTER_TPID_0 */ "", 40273 /* IDB_OBM9_OUTER_TPID_1 */ "", 40274 /* IDB_OBM9_OUTER_TPID_2 */ "", 40275 /* IDB_OBM9_OUTER_TPID_3 */ "", 40276 /* IDB_OBM9_OUTER_TPID_0_PIPE0 */ "", 40277 /* IDB_OBM9_OUTER_TPID_0_PIPE1 */ "", 40278 /* IDB_OBM9_OUTER_TPID_0_PIPE2 */ "", 40279 /* IDB_OBM9_OUTER_TPID_0_PIPE3 */ "", 40280 /* IDB_OBM9_OUTER_TPID_1_PIPE0 */ "", 40281 /* IDB_OBM9_OUTER_TPID_1_PIPE1 */ "", 40282 /* IDB_OBM9_OUTER_TPID_1_PIPE2 */ "", 40283 /* IDB_OBM9_OUTER_TPID_1_PIPE3 */ "", 40284 /* IDB_OBM9_OUTER_TPID_2_PIPE0 */ "", 40285 /* IDB_OBM9_OUTER_TPID_2_PIPE1 */ "", 40286 /* IDB_OBM9_OUTER_TPID_2_PIPE2 */ "", 40287 /* IDB_OBM9_OUTER_TPID_2_PIPE3 */ "", 40288 /* IDB_OBM9_OUTER_TPID_3_PIPE0 */ "", 40289 /* IDB_OBM9_OUTER_TPID_3_PIPE1 */ "", 40290 /* IDB_OBM9_OUTER_TPID_3_PIPE2 */ "", 40291 /* IDB_OBM9_OUTER_TPID_3_PIPE3 */ "", 40292 /* IDB_OBM9_OUTER_TPID_PIPE0 */ "", 40293 /* IDB_OBM9_OUTER_TPID_PIPE1 */ "", 40294 /* IDB_OBM9_OUTER_TPID_PIPE2 */ "", 40295 /* IDB_OBM9_OUTER_TPID_PIPE3 */ "", 40296 /* IDB_OBM9_OVERSUB_MON_ECC_STATUS */ "IDB_OBM9_OVERSUB_MON_ECC_STATUS", 40297 /* IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE0 */ "IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE0", 40298 /* IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE1 */ "IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE1", 40299 /* IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE2 */ "IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE2", 40300 /* IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE3 */ "IDB_OBM9_OVERSUB_MON_ECC_STATUS_PIPE3", 40301 /* IDB_OBM9_PE_ETHERTYPE */ "", 40302 /* IDB_OBM9_PE_ETHERTYPE_PIPE0 */ "", 40303 /* IDB_OBM9_PE_ETHERTYPE_PIPE1 */ "", 40304 /* IDB_OBM9_PE_ETHERTYPE_PIPE2 */ "", 40305 /* IDB_OBM9_PE_ETHERTYPE_PIPE3 */ "", 40306 /* IDB_OBM9_PORT_CONFIG */ "", 40307 /* IDB_OBM9_PORT_CONFIG_PIPE0 */ "", 40308 /* IDB_OBM9_PORT_CONFIG_PIPE1 */ "", 40309 /* IDB_OBM9_PORT_CONFIG_PIPE2 */ "", 40310 /* IDB_OBM9_PORT_CONFIG_PIPE3 */ "", 40311 /* IDB_OBM9_PROTOCOL_CONTROL_0 */ "", 40312 /* IDB_OBM9_PROTOCOL_CONTROL_1 */ "", 40313 /* IDB_OBM9_PROTOCOL_CONTROL_2 */ "", 40314 /* IDB_OBM9_PROTOCOL_CONTROL_0_PIPE0 */ "", 40315 /* IDB_OBM9_PROTOCOL_CONTROL_0_PIPE1 */ "", 40316 /* IDB_OBM9_PROTOCOL_CONTROL_0_PIPE2 */ "", 40317 /* IDB_OBM9_PROTOCOL_CONTROL_0_PIPE3 */ "", 40318 /* IDB_OBM9_PROTOCOL_CONTROL_1_PIPE0 */ "", 40319 /* IDB_OBM9_PROTOCOL_CONTROL_1_PIPE1 */ "", 40320 /* IDB_OBM9_PROTOCOL_CONTROL_1_PIPE2 */ "", 40321 /* IDB_OBM9_PROTOCOL_CONTROL_1_PIPE3 */ "", 40322 /* IDB_OBM9_PROTOCOL_CONTROL_2_PIPE0 */ "", 40323 /* IDB_OBM9_PROTOCOL_CONTROL_2_PIPE1 */ "", 40324 /* IDB_OBM9_PROTOCOL_CONTROL_2_PIPE2 */ "", 40325 /* IDB_OBM9_PROTOCOL_CONTROL_2_PIPE3 */ "", 40326 /* IDB_OBM9_QUEUE_ECC_STATUS */ "IDB_OBM9_QUEUE_ECC_STATUS", 40327 /* IDB_OBM9_QUEUE_ECC_STATUS_PIPE0 */ "IDB_OBM9_QUEUE_ECC_STATUS_PIPE0", 40328 /* IDB_OBM9_QUEUE_ECC_STATUS_PIPE1 */ "IDB_OBM9_QUEUE_ECC_STATUS_PIPE1", 40329 /* IDB_OBM9_QUEUE_ECC_STATUS_PIPE2 */ "IDB_OBM9_QUEUE_ECC_STATUS_PIPE2", 40330 /* IDB_OBM9_QUEUE_ECC_STATUS_PIPE3 */ "IDB_OBM9_QUEUE_ECC_STATUS_PIPE3", 40331 /* IDB_OBM9_RAM_CONTROL */ "IDB_OBM9_RAM_CONTROL", 40332 /* IDB_OBM9_RAM_CONTROL_PIPE0 */ "IDB_OBM9_RAM_CONTROL_PIPE0", 40333 /* IDB_OBM9_RAM_CONTROL_PIPE1 */ "IDB_OBM9_RAM_CONTROL_PIPE1", 40334 /* IDB_OBM9_RAM_CONTROL_PIPE2 */ "IDB_OBM9_RAM_CONTROL_PIPE2", 40335 /* IDB_OBM9_RAM_CONTROL_PIPE3 */ "IDB_OBM9_RAM_CONTROL_PIPE3", 40336 /* IDB_OBM9_SER_CONTROL */ "IDB_OBM9_SER_CONTROL", 40337 /* IDB_OBM9_SER_CONTROL_PIPE0 */ "IDB_OBM9_SER_CONTROL_PIPE0", 40338 /* IDB_OBM9_SER_CONTROL_PIPE1 */ "IDB_OBM9_SER_CONTROL_PIPE1", 40339 /* IDB_OBM9_SHARED_CONFIG */ "IDB_OBM9_SHARED_CONFIG", 40340 /* IDB_OBM9_SHARED_CONFIG_PIPE0 */ "IDB_OBM9_SHARED_CONFIG_PIPE0", 40341 /* IDB_OBM9_SHARED_CONFIG_PIPE1 */ "IDB_OBM9_SHARED_CONFIG_PIPE1", 40342 /* IDB_OBM9_SHARED_CONFIG_PIPE2 */ "IDB_OBM9_SHARED_CONFIG_PIPE2", 40343 /* IDB_OBM9_SHARED_CONFIG_PIPE3 */ "IDB_OBM9_SHARED_CONFIG_PIPE3", 40344 /* IDB_OBM9_SHARED_USAGE */ "IDB_OBM9_SHARED_USAGE", 40345 /* IDB_OBM9_SHARED_USAGE_PIPE0 */ "IDB_OBM9_SHARED_USAGE_PIPE0", 40346 /* IDB_OBM9_SHARED_USAGE_PIPE1 */ "IDB_OBM9_SHARED_USAGE_PIPE1", 40347 /* IDB_OBM9_SHARED_USAGE_PIPE2 */ "IDB_OBM9_SHARED_USAGE_PIPE2", 40348 /* IDB_OBM9_SHARED_USAGE_PIPE3 */ "IDB_OBM9_SHARED_USAGE_PIPE3", 40349 /* IDB_OBM9_THRESHOLD */ "", 40350 /* IDB_OBM9_THRESHOLD_1 */ "", 40351 /* IDB_OBM9_THRESHOLD_1_PIPE0 */ "", 40352 /* IDB_OBM9_THRESHOLD_1_PIPE1 */ "", 40353 /* IDB_OBM9_THRESHOLD_1_PIPE2 */ "", 40354 /* IDB_OBM9_THRESHOLD_1_PIPE3 */ "", 40355 /* IDB_OBM9_THRESHOLD_PIPE0 */ "", 40356 /* IDB_OBM9_THRESHOLD_PIPE1 */ "", 40357 /* IDB_OBM9_THRESHOLD_PIPE2 */ "", 40358 /* IDB_OBM9_THRESHOLD_PIPE3 */ "", 40359 /* IDB_OBM9_USAGE */ "", 40360 /* IDB_OBM9_USAGE_PIPE0 */ "", 40361 /* IDB_OBM9_USAGE_PIPE1 */ "", 40362 /* IDB_OBM9_USAGE_PIPE2 */ "", 40363 /* IDB_OBM9_USAGE_PIPE3 */ "", 40364 /* IDB_OBM_MONITOR_CONFIG */ "", 40365 /* IDB_OBM_MONITOR_CONFIG_PIPE0 */ "", 40366 /* IDB_OBM_MONITOR_CONFIG_PIPE1 */ "", 40367 /* IDB_OBM_MONITOR_CONFIG_PIPE2 */ "", 40368 /* IDB_OBM_MONITOR_CONFIG_PIPE3 */ "", 40369 /* IDB_OBM_MONITOR_CONFIG_PIPE4 */ "", 40370 /* IDB_OBM_MONITOR_CONFIG_PIPE5 */ "", 40371 /* IDB_OBM_MONITOR_CONFIG_PIPE6 */ "", 40372 /* IDB_OBM_MONITOR_CONFIG_PIPE7 */ "", 40373 /* IDB_OBM_MON_HW_CONTROL */ "IDB_OBM_MON_HW_CONTROL", 40374 /* IDB_OBM_MON_HW_CONTROL_PIPE0 */ "IDB_OBM_MON_HW_CONTROL_PIPE0", 40375 /* IDB_OBM_MON_HW_CONTROL_PIPE1 */ "IDB_OBM_MON_HW_CONTROL_PIPE1", 40376 /* IDB_OBM_MON_HW_CONTROL_PIPE2 */ "IDB_OBM_MON_HW_CONTROL_PIPE2", 40377 /* IDB_OBM_MON_HW_CONTROL_PIPE3 */ "IDB_OBM_MON_HW_CONTROL_PIPE3", 40378 /* IDB_PA_RESET_CONTROL */ "IDB_PA_RESET_CONTROL", 40379 /* IDB_PA_RESET_CONTROL_PIPE0 */ "IDB_PA_RESET_CONTROL_PIPE0", 40380 /* IDB_PA_RESET_CONTROL_PIPE1 */ "IDB_PA_RESET_CONTROL_PIPE1", 40381 /* IDB_PA_RESET_CONTROL_PIPE2 */ "IDB_PA_RESET_CONTROL_PIPE2", 40382 /* IDB_PA_RESET_CONTROL_PIPE3 */ "IDB_PA_RESET_CONTROL_PIPE3", 40383 /* IDB_PA_RESET_CONTROL_PIPE4 */ "IDB_PA_RESET_CONTROL_PIPE4", 40384 /* IDB_PA_RESET_CONTROL_PIPE5 */ "IDB_PA_RESET_CONTROL_PIPE5", 40385 /* IDB_PA_RESET_CONTROL_PIPE6 */ "IDB_PA_RESET_CONTROL_PIPE6", 40386 /* IDB_PA_RESET_CONTROL_PIPE7 */ "IDB_PA_RESET_CONTROL_PIPE7", 40387 /* IDB_RAM_CONTROL */ "IDB_RAM_CONTROL", 40388 /* IDB_RAM_CONTROL_PIPE0 */ "IDB_RAM_CONTROL_PIPE0", 40389 /* IDB_RAM_CONTROL_PIPE1 */ "IDB_RAM_CONTROL_PIPE1", 40390 /* IDB_RAM_CONTROL_PIPE2 */ "IDB_RAM_CONTROL_PIPE2", 40391 /* IDB_RAM_CONTROL_PIPE3 */ "IDB_RAM_CONTROL_PIPE3", 40392 /* IDB_RESERVED_MIRROR_ADDR */ "", 40393 /* IDB_RESERVED_MTCD */ "", 40394 /* IDB_RESERVED_MTCP */ "", 40395 /* IDB_RESERVED_PCMI_0 */ "", 40396 /* IDB_RESERVED_PCMI_1 */ "", 40397 /* IDB_RESERVED_PCMI_2 */ "", 40398 /* IDB_RESERVED_PCMI_3 */ "", 40399 /* IDB_RESERVED_PCMI_4 */ "", 40400 /* IDB_RESERVED_PCMI_0_S */ "", 40401 /* IDB_RESERVED_PCMI_0_T */ "", 40402 /* IDB_RESERVED_PCMI_1_S */ "", 40403 /* IDB_RESERVED_PCMI_1_T */ "", 40404 /* IDB_RESERVED_PCMI_2_S */ "", 40405 /* IDB_RESERVED_PCMI_2_T */ "", 40406 /* IDB_RESERVED_PCMI_3_S */ "", 40407 /* IDB_RESERVED_PCMI_3_T */ "", 40408 /* IDB_RESERVED_PCMI_4_S */ "", 40409 /* IDB_RESERVED_PCMI_4_T */ "", 40410 /* IDB_RESERVED_SPARE_0 */ "", 40411 /* IDB_RESERVED_SPARE_1 */ "", 40412 /* IDB_RESERVED_SPARE_2 */ "", 40413 /* IDB_RESERVED_SPARE_3 */ "", 40414 /* IDB_SBUS_BROADCAST_ID */ "", 40415 /* IDB_SBUS_LAST_IN_CHAIN */ "", 40416 /* IDB_SBUS_TIMER */ "", 40417 /* IDB_SBUS_TIMER_PIPE0 */ "", 40418 /* IDB_SBUS_TIMER_PIPE1 */ "", 40419 /* IDB_SBUS_TIMER_PIPE2 */ "", 40420 /* IDB_SBUS_TIMER_PIPE3 */ "", 40421 /* IDB_SER_CONTROL */ "", 40422 /* IDB_SER_CONTROL_64 */ "IDB_SER_CONTROL", 40423 /* IDB_SER_SCAN_CONFIG */ "", 40424 /* IDB_SER_SCAN_CONFIG_PIPE0 */ "", 40425 /* IDB_SER_SCAN_CONFIG_PIPE1 */ "", 40426 /* IDB_SER_SCAN_CONFIG_PIPE2 */ "", 40427 /* IDB_SER_SCAN_CONFIG_PIPE3 */ "", 40428 /* IDB_SER_SCAN_STATUS */ "", 40429 /* IDB_SER_SCAN_STATUS_PIPE0 */ "", 40430 /* IDB_SER_SCAN_STATUS_PIPE1 */ "", 40431 /* IDB_SER_SCAN_STATUS_PIPE2 */ "", 40432 /* IDB_SER_SCAN_STATUS_PIPE3 */ "", 40433 /* IDB_SER_STATUS_0 */ "", 40434 /* IDB_SER_STATUS_1 */ "", 40435 /* IDB_SER_STATUS_2 */ "", 40436 /* IDB_SER_STATUS_0_PIPE0 */ "", 40437 /* IDB_SER_STATUS_0_PIPE1 */ "", 40438 /* IDB_SER_STATUS_0_PIPE2 */ "", 40439 /* IDB_SER_STATUS_0_PIPE3 */ "", 40440 /* IDB_SER_STATUS_1_PIPE0 */ "", 40441 /* IDB_SER_STATUS_1_PIPE1 */ "", 40442 /* IDB_SER_STATUS_1_PIPE2 */ "", 40443 /* IDB_SER_STATUS_1_PIPE3 */ "", 40444 /* IDB_SOP_EVENT_ECC_STATUS */ "IDB_SOP_EVENT_ECC_STATUS", 40445 /* IDB_SOP_EVENT_ECC_STATUS_PIPE0 */ "IDB_SOP_EVENT_ECC_STATUS_PIPE0", 40446 /* IDB_SOP_EVENT_ECC_STATUS_PIPE1 */ "IDB_SOP_EVENT_ECC_STATUS_PIPE1", 40447 /* IDB_SOP_EVENT_ECC_STATUS_PIPE2 */ "IDB_SOP_EVENT_ECC_STATUS_PIPE2", 40448 /* IDB_SOP_EVENT_ECC_STATUS_PIPE3 */ "IDB_SOP_EVENT_ECC_STATUS_PIPE3", 40449 /* IDISC_CLK_GATING_CONTROL */ "", 40450 /* IDM_GENRES_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 40451 /* IDM_GENRES_S0_IDM_ERROR_LOG_COMPLETE */ "", 40452 /* IDM_GENRES_S0_IDM_ERROR_LOG_CONTROL */ "", 40453 /* IDM_GENRES_S0_IDM_ERROR_LOG_FLAGS */ "", 40454 /* IDM_GENRES_S0_IDM_ERROR_LOG_ID */ "", 40455 /* IDM_GENRES_S0_IDM_ERROR_LOG_STATUS */ "", 40456 /* IDM_GENRES_S0_IDM_INTERRUPT_STATUS */ "", 40457 /* IDM_GENRES_S0_IDM_IO_CONTROL_DIRECT */ "", 40458 /* IDM_GENRES_S0_IDM_IO_STATUS */ "", 40459 /* IDM_GENRES_S0_IDM_RESET_CONTROL */ "", 40460 /* IDM_GENRES_S0_IDM_RESET_READ_ID */ "", 40461 /* IDM_GENRES_S0_IDM_RESET_STATUS */ "", 40462 /* IDM_GENRES_S0_IDM_RESET_WRITE_ID */ "", 40463 /* IDM_PERIPH_M0_IDM_INTERRUPT_STATUS */ "", 40464 /* IDM_PERIPH_M0_IDM_IO_CONTROL_DIRECT */ "", 40465 /* IDM_PERIPH_M0_IDM_RESET_CONTROL */ "", 40466 /* IDM_PERIPH_M0_IDM_RESET_STATUS */ "", 40467 /* IDM_PERIPH_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 40468 /* IDM_PERIPH_S0_IDM_ERROR_LOG_COMPLETE */ "", 40469 /* IDM_PERIPH_S0_IDM_ERROR_LOG_CONTROL */ "", 40470 /* IDM_PERIPH_S0_IDM_ERROR_LOG_FLAGS */ "", 40471 /* IDM_PERIPH_S0_IDM_ERROR_LOG_ID */ "", 40472 /* IDM_PERIPH_S0_IDM_ERROR_LOG_STATUS */ "", 40473 /* IDM_PERIPH_S0_IDM_INTERRUPT_STATUS */ "", 40474 /* IDM_PERIPH_S0_IDM_IO_CONTROL_DIRECT */ "", 40475 /* IDM_PERIPH_S0_IDM_IO_STATUS */ "", 40476 /* IDM_PERIPH_S0_IDM_RESET_CONTROL */ "", 40477 /* IDM_PERIPH_S0_IDM_RESET_READ_ID */ "", 40478 /* IDM_PERIPH_S0_IDM_RESET_STATUS */ "", 40479 /* IDM_PERIPH_S0_IDM_RESET_WRITE_ID */ "", 40480 /* IDR_BCN_REGISTER */ "", 40481 /* IDR_BLAME_REGISTER */ "", 40482 /* IDR_BUFFER_CHANGE_CONFIGURATION */ "", 40483 /* IDR_BUFFER_SELECTION_DECISION */ "", 40484 /* IDR_COMPATIBILITY_REGISTER */ "", 40485 /* IDR_COUNTERS_FAP_PORTS */ "", 40486 /* IDR_COUNTERS_REASSEMBLY_CONTEXTS */ "", 40487 /* IDR_DISCARDED_BYTES_CNT */ "", 40488 /* IDR_DISCARDED_OCTETS_CNT */ "", 40489 /* IDR_DISCARDED_PACKETS_CNT */ "", 40490 /* IDR_DRAM_FIFO_READ_DISABLE */ "", 40491 /* IDR_DRAM_FIFO_RECYCLE_TIMEOUT_CONFIGURATION */ "", 40492 /* IDR_DRAM_REJECT_MULTICAST_RANGE */ "", 40493 /* IDR_DROP_DESTINATION_CONFIGURATION */ "", 40494 /* IDR_DYNAMIC_CONFIGURATION */ "", 40495 /* IDR_ECC_1B_ERR_CNT */ "", 40496 /* IDR_ECC_2B_ERR_CNT */ "", 40497 /* IDR_ECC_ERR_1B_INITIATE */ "", 40498 /* IDR_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 40499 /* IDR_ECC_ERR_2B_INITIATE */ "", 40500 /* IDR_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 40501 /* IDR_ECC_INTERRUPT_REGISTER */ "", 40502 /* IDR_ECC_INTERRUPT_REGISTER_MASK */ "", 40503 /* IDR_ECC_INTERRUPT_REGISTER_TEST */ "", 40504 /* IDR_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 40505 /* IDR_ERROR_INITIATION_DATA */ "", 40506 /* IDR_FBC_BANK_IS_USED_BY_OCB */ "", 40507 /* IDR_FBC_CACHE_CONFIGURATION */ "", 40508 /* IDR_FBC_CACHE_POINTERS */ "", 40509 /* IDR_FBC_CACHE_WATERMARK_REG */ "", 40510 /* IDR_FBC_EXTERNAL_CONFIGURATION */ "", 40511 /* IDR_FBC_EXTERNAL_FULL_MULTICAST_LIMIT_HIGH */ "", 40512 /* IDR_FBC_EXTERNAL_FULL_MULTICAST_LIMIT_LOW */ "", 40513 /* IDR_FBC_EXTERNAL_LIMITS */ "", 40514 /* IDR_FBC_EXTERNAL_MINI_MULTICAST_LIMIT_HIGH */ "", 40515 /* IDR_FBC_EXTERNAL_MINI_MULTICAST_LIMIT_LOW */ "", 40516 /* IDR_FBC_EXTERNAL_OCB_MULTICAST_LIMIT_HIGH */ "", 40517 /* IDR_FBC_EXTERNAL_OCB_MULTICAST_LIMIT_LOW */ "", 40518 /* IDR_FBC_EXTERNAL_OCB_UNICAST_LIMIT_HIGH */ "", 40519 /* IDR_FBC_EXTERNAL_OCB_UNICAST_LIMIT_LOW */ "", 40520 /* IDR_FBC_EXTERNAL_POINTERS */ "", 40521 /* IDR_FBC_EXTERNAL_UNICAST_LIMIT_HIGH */ "", 40522 /* IDR_FBC_EXTERNAL_UNICAST_LIMIT_LOW */ "", 40523 /* IDR_FBC_FULL_MULTICAST_AUTOGEN_END */ "", 40524 /* IDR_FBC_FULL_MULTICAST_AUTOGEN_START */ "", 40525 /* IDR_FBC_FULL_MULTICAST_THRESHOLDS */ "", 40526 /* IDR_FBC_INTERNAL_THRESHOLDS */ "", 40527 /* IDR_FBC_MINI_MULTICAST_AUTOGEN_END */ "", 40528 /* IDR_FBC_MINI_MULTICAST_AUTOGEN_START */ "", 40529 /* IDR_FBC_MINI_MULTICAST_THRESHOLDS */ "", 40530 /* IDR_FBC_OCB_MULTICAST_AUTOGEN_END */ "", 40531 /* IDR_FBC_OCB_MULTICAST_AUTOGEN_START */ "", 40532 /* IDR_FBC_OCB_MULTICAST_THRESHOLDS */ "", 40533 /* IDR_FBC_OCB_UNICAST_AUTOGEN_END */ "", 40534 /* IDR_FBC_OCB_UNICAST_AUTOGEN_START */ "", 40535 /* IDR_FBC_OCB_UNICAST_THRESHOLDS */ "", 40536 /* IDR_FBC_RRG_POINTER_COUNT */ "", 40537 /* IDR_FBC_UNICAST_AUTOGEN_END */ "", 40538 /* IDR_FBC_UNICAST_AUTOGEN_START */ "", 40539 /* IDR_FBC_UNICAST_THRESHOLDS */ "", 40540 /* IDR_FBC_WRG_POINTER_COUNT */ "", 40541 /* IDR_FORCE_CRC_ERROR */ "", 40542 /* IDR_FULL_DRAM_REJECT_COUNTER */ "", 40543 /* IDR_FULL_MULTICAST_AUTOGEN_PTR */ "", 40544 /* IDR_GLBL_CFG */ "", 40545 /* IDR_GLOBAL_ADDR_TRANS_CFG */ "", 40546 /* IDR_GLOBAL_DRAM_NUMBER_SWAPPING */ "", 40547 /* IDR_GLOBAL_FULL_MC_DB_RANGE_0 */ "", 40548 /* IDR_GLOBAL_FULL_MC_DB_RANGE_1 */ "", 40549 /* IDR_GLOBAL_GENERAL_CFG_2 */ "", 40550 /* IDR_GLOBAL_GENERAL_CFG_3 */ "", 40551 /* IDR_GLOBAL_INGRESS_MULTICAST_INDICATION */ "", 40552 /* IDR_GLOBAL_MEM_OPTIONS */ "", 40553 /* IDR_GLOBAL_MINI_MC_DB_RANGE_0 */ "", 40554 /* IDR_GLOBAL_MINI_MC_DB_RANGE_1 */ "", 40555 /* IDR_GLOBAL_OCB_BANK_RANGE */ "", 40556 /* IDR_GLOBAL_OCB_BUF_RANGE_0 */ "", 40557 /* IDR_GLOBAL_OCB_BUF_RANGE_1 */ "", 40558 /* IDR_GLOBAL_SYS_HEADER_CFG */ "", 40559 /* IDR_GTIMER_CONFIGURATION */ "", 40560 /* IDR_GTIMER_TRIGGER */ "", 40561 /* IDR_INDIRECT_COMMAND */ "", 40562 /* IDR_INDIRECT_COMMAND_ADDRESS */ "", 40563 /* IDR_INDIRECT_COMMAND_DATA_INCREMENT */ "", 40564 /* IDR_INDIRECT_COMMAND_RD_DATA */ "", 40565 /* IDR_INDIRECT_COMMAND_WIDE_MEM */ "", 40566 /* IDR_INDIRECT_COMMAND_WR_DATA */ "", 40567 /* IDR_INDIRECT_FORCE_BUBBLE */ "", 40568 /* IDR_INDIRECT_WR_MASK */ "", 40569 /* IDR_INGRESS_MULTICAST_INDICATION */ "", 40570 /* IDR_INTERRUPT_MASK_REGISTER */ "", 40571 /* IDR_INTERRUPT_REGISTER */ "", 40572 /* IDR_INTERRUPT_REGISTER_TEST */ "", 40573 /* IDR_INVALID_METER_POINTER */ "", 40574 /* IDR_IQM_INTERFACE_COUNTER */ "", 40575 /* IDR_IQM_RETURNED_BUFFER */ "", 40576 /* IDR_IRE_INTERFACE_COUNTER */ "", 40577 /* IDR_IRE_READY_CLKS_CNT */ "", 40578 /* IDR_IRR_INTERFACE_COUNTER */ "", 40579 /* IDR_IRR_PACKET_CONSTRUCTOR */ "", 40580 /* IDR_MCDA_CBL_STAT_CTR */ "", 40581 /* IDR_MCDA_CFG */ "", 40582 /* IDR_MCDA_EBL_STAT_CTR */ "", 40583 /* IDR_MCDA_LAST_CMD_INDEX */ "", 40584 /* IDR_MCDA_REFRESH_CFG */ "", 40585 /* IDR_MCDA_STAT_CFG */ "", 40586 /* IDR_MCDB_CBL_STAT_CTR */ "", 40587 /* IDR_MCDB_CFG */ "", 40588 /* IDR_MCDB_EBL_STAT_CTR */ "", 40589 /* IDR_MCDB_LAST_CMD_INDEX */ "", 40590 /* IDR_MCDB_REFRESH_CFG */ "", 40591 /* IDR_MCDB_STAT_CFG */ "", 40592 /* IDR_MINI_MULTICAST_AUTOGEN_PTR */ "", 40593 /* IDR_MMU_DESC_CREDITS_CNT */ "", 40594 /* IDR_MMU_ECC_ERR_CNT */ "", 40595 /* IDR_MMU_ECC_ERR_REG */ "", 40596 /* IDR_MMU_INTERFACE_COUNTER */ "", 40597 /* IDR_MRPS_INTERFACE_COUNTER */ "", 40598 /* IDR_OCB_BUFFER_FIFO_WATERMARK_REG */ "", 40599 /* IDR_OCB_COMMITTED_MULTICAST_RANGE */ "", 40600 /* IDR_OCB_ELIGIBLE_MULTICAST_RANGE */ "", 40601 /* IDR_OCB_FIFO_READ_DISABLE */ "", 40602 /* IDR_OCB_INTERFACE_COUNTER */ "", 40603 /* IDR_OCB_MULTICAST_RANGE_0 */ "", 40604 /* IDR_OCB_MULTICAST_RANGE_1 */ "", 40605 /* IDR_OCB_USE_SHAPER */ "", 40606 /* IDR_OCCUPIED_DBUFF_STATUS */ "", 40607 /* IDR_OCCUPIED_DBUFF_THRESHOLD */ "", 40608 /* IDR_PACKET_SIZES */ "", 40609 /* IDR_PARITY_ERR_CNT */ "", 40610 /* IDR_PARTIAL_DRAM_REJECT_CONFIGURATION */ "", 40611 /* IDR_PARTIAL_DRAM_REJECT_COUNTER */ "", 40612 /* IDR_PAR_ERR_INITIATE */ "", 40613 /* IDR_PAR_ERR_MEM_MASK */ "", 40614 /* IDR_PAUSE_PIPE_STATUS_BMP */ "", 40615 /* IDR_RCT_CPU_REQUEST_REGISTER */ "", 40616 /* IDR_REASSEMBLY_CONTEXT_IS_OCB_ONLY */ "", 40617 /* IDR_REASSEMBLY_CONTEXT_PIPE_MAP */ "", 40618 /* IDR_REASSEMBLY_ERRORS */ "", 40619 /* IDR_REASSEMBLY_ERRORS_HIT */ "", 40620 /* IDR_REASSEMBLY_INTERRUPT_REGISTER */ "", 40621 /* IDR_REASSEMBLY_INTERRUPT_REGISTER_MASK */ "", 40622 /* IDR_REASSEMBLY_INTERRUPT_REGISTER_TEST */ "", 40623 /* IDR_REASSEMBLY_TIMEOUT */ "", 40624 /* IDR_RECEIVED_BYTES_CNT */ "", 40625 /* IDR_RECEIVED_OCTETS_CNT */ "", 40626 /* IDR_RECEIVED_PACKETS_CNT */ "", 40627 /* IDR_REG_0085 */ "", 40628 /* IDR_REG_0090 */ "", 40629 /* IDR_REG_0091 */ "", 40630 /* IDR_REG_0092 */ "", 40631 /* IDR_REG_0093 */ "", 40632 /* IDR_REG_0151 */ "", 40633 /* IDR_REG_0220 */ "", 40634 /* IDR_REG_0221 */ "", 40635 /* IDR_REG_0222 */ "", 40636 /* IDR_REG_0223 */ "", 40637 /* IDR_REG_0224 */ "", 40638 /* IDR_REG_0225 */ "", 40639 /* IDR_REG_0226 */ "", 40640 /* IDR_REG_0227 */ "", 40641 /* IDR_REG_0228 */ "", 40642 /* IDR_REG_0229 */ "", 40643 /* IDR_REG_0230 */ "", 40644 /* IDR_REG_0231 */ "", 40645 /* IDR_REG_0232 */ "", 40646 /* IDR_REG_0233 */ "", 40647 /* IDR_REG_0234 */ "", 40648 /* IDR_REG_0235 */ "", 40649 /* IDR_REG_0236 */ "", 40650 /* IDR_REG_0237 */ "", 40651 /* IDR_REG_0238 */ "", 40652 /* IDR_REG_0239 */ "", 40653 /* IDR_REG_0241 */ "", 40654 /* IDR_REG_0250 */ "", 40655 /* IDR_REG_00AE */ "", 40656 /* IDR_REG_00AF */ "", 40657 /* IDR_REG_00B4 */ "", 40658 /* IDR_REG_00B5 */ "", 40659 /* IDR_REG_00B6 */ "", 40660 /* IDR_REG_00B7 */ "", 40661 /* IDR_REG_00C1 */ "", 40662 /* IDR_REG_00C4 */ "", 40663 /* IDR_REG_00C5 */ "", 40664 /* IDR_REG_00C6 */ "", 40665 /* IDR_REG_00C7 */ "", 40666 /* IDR_REG_00C8 */ "", 40667 /* IDR_REG_00C9 */ "", 40668 /* IDR_REG_00CA */ "", 40669 /* IDR_REG_00CB */ "", 40670 /* IDR_REG_00CC */ "", 40671 /* IDR_REG_00CD */ "", 40672 /* IDR_REG_00CF */ "", 40673 /* IDR_REG_021B */ "", 40674 /* IDR_REG_021C */ "", 40675 /* IDR_REG_021D */ "", 40676 /* IDR_REG_021E */ "", 40677 /* IDR_REG_021F */ "", 40678 /* IDR_REG_022A */ "", 40679 /* IDR_REG_022B */ "", 40680 /* IDR_REG_022C */ "", 40681 /* IDR_REG_022D */ "", 40682 /* IDR_REG_022E */ "", 40683 /* IDR_REG_022F */ "", 40684 /* IDR_REG_023A */ "", 40685 /* IDR_REG_023B */ "", 40686 /* IDR_REG_023C */ "", 40687 /* IDR_REG_023D */ "", 40688 /* IDR_REG_023E */ "", 40689 /* IDR_REG_023F */ "", 40690 /* IDR_REG_025F */ "", 40691 /* IDR_REG_026E */ "", 40692 /* IDR_REG_027D */ "", 40693 /* IDR_REG_028C */ "", 40694 /* IDR_REG_029B */ "", 40695 /* IDR_REG_02AA */ "", 40696 /* IDR_REG_02B9 */ "", 40697 /* IDR_REG_02C8 */ "", 40698 /* IDR_RESERVED_MIRROR_ADDR */ "", 40699 /* IDR_RESERVED_MTCD */ "", 40700 /* IDR_RESERVED_MTCP */ "", 40701 /* IDR_RESERVED_PCMI_0 */ "", 40702 /* IDR_RESERVED_PCMI_1 */ "", 40703 /* IDR_RESERVED_PCMI_2 */ "", 40704 /* IDR_RESERVED_PCMI_3 */ "", 40705 /* IDR_RESERVED_PCMI_4 */ "", 40706 /* IDR_RESERVED_PCMI_0_S */ "", 40707 /* IDR_RESERVED_PCMI_0_T */ "", 40708 /* IDR_RESERVED_PCMI_1_S */ "", 40709 /* IDR_RESERVED_PCMI_1_T */ "", 40710 /* IDR_RESERVED_PCMI_2_S */ "", 40711 /* IDR_RESERVED_PCMI_2_T */ "", 40712 /* IDR_RESERVED_PCMI_3_S */ "", 40713 /* IDR_RESERVED_PCMI_3_T */ "", 40714 /* IDR_RESERVED_PCMI_4_S */ "", 40715 /* IDR_RESERVED_PCMI_4_T */ "", 40716 /* IDR_RESERVED_SPARE_0 */ "", 40717 /* IDR_RESERVED_SPARE_1 */ "", 40718 /* IDR_RESERVED_SPARE_2 */ "", 40719 /* IDR_RESERVED_SPARE_3 */ "", 40720 /* IDR_RESET_STATUS_REGISTER */ "", 40721 /* IDR_RRG_FULL_MULTICAST_POINTERS */ "", 40722 /* IDR_RRG_MINI_MULTICAST_POINTERS */ "", 40723 /* IDR_SBUS_BROADCAST_ID */ "", 40724 /* IDR_SBUS_LAST_IN_CHAIN */ "", 40725 /* IDR_SNOOP_MIRROR_IS_OCB_ELIGIBLE */ "", 40726 /* IDR_SPARE_REGISTER_2 */ "", 40727 /* IDR_STATIC_CONFIGURATION */ "", 40728 /* IDR_TIMEOUT_REG */ "", 40729 /* IDR_TIMEOUT_VALID_REG */ "", 40730 /* IDR_TRAFFIC_CLASS_IS_OCB_ONLY */ "", 40731 /* IDR_WATERMARK_REG */ "", 40732 /* IDR_WATERMARK_REG_1 */ "", 40733 /* IDR_WATERMARK_REG_2 */ "", 40734 /* IDR_WATERMARK_REG_3 */ "", 40735 /* IDR_WATERMARK_REG_4 */ "", 40736 /* IDR_WATERMARK_REG_5 */ "", 40737 /* IDR_WATERMARK_REG_6 */ "", 40738 /* IDR_WATERMARK_REG_7 */ "", 40739 /* IDR_WRG_COUNT_READY_THRESHOLD */ "", 40740 /* IDR_WRG_FULL_MULTICAST_POINTERS_H */ "", 40741 /* IDR_WRG_FULL_MULTICAST_POINTERS_L */ "", 40742 /* IDR_WRG_FULL_MULTICAST_POINTERS_M */ "", 40743 /* IDR_WRG_MINI_MULTICAST_POINTERS_H */ "", 40744 /* IDR_WRG_MINI_MULTICAST_POINTERS_L */ "", 40745 /* IDR_WRG_MINI_MULTICAST_POINTERS_M */ "", 40746 /* IE2E_CONTROL */ "", 40747 /* IECELL_CLEAR_DOUBLE_BIT_ERROR */ "", 40748 /* IECELL_CLEAR_MEM_OVERFLOW_STATUS */ "", 40749 /* IECELL_CLEAR_SINGLE_BIT_ERROR */ "", 40750 /* IECELL_CONFIG */ "", 40751 /* IECELL_ECC_CONTROL */ "", 40752 /* IECELL_FORCE_DOUBLE_BIT_ERROR */ "", 40753 /* IECELL_FORCE_SINGLE_BIT_ERROR */ "", 40754 /* IECELL_MEMORY_CONTROL */ "", 40755 /* IECELL_MEM_OVERFLOW_STATUS */ "", 40756 /* IECELL_RXFIFO_MEM_ECC_STATUS */ "", 40757 /* IECELL_TXFIFO_CELL_CNT */ "", 40758 /* IECELL_TXFIFO_CELL_REQ_CNT */ "", 40759 /* IECELL_TXFIFO_MEM_ECC_STATUS */ "", 40760 /* IECELL_TXFIFO_PKT_DROP_CTL */ "", 40761 /* IEEE1588_TIME_CONTROL */ "", 40762 /* IEEE1588_TIME_FRAC_SEC_LOWER */ "", 40763 /* IEEE1588_TIME_FRAC_SEC_UPPER */ "", 40764 /* IEEE1588_TIME_FREQ_CONTROL */ "", 40765 /* IEEE1588_TIME_LEAP_SEC_CONTROL */ "", 40766 /* IEEE1588_TIME_SEC */ "", 40767 /* IEGR_PORT */ "", 40768 /* IEGR_PORT_64 */ "IEGR_PORT", 40769 /* IEGR_PORT_L3UC_MODS */ "", 40770 /* IEMIRROR_CONTROL */ "", 40771 /* IEMIRROR_CONTROL1 */ "", 40772 /* IEMIRROR_CONTROL1_64 */ "IEMIRROR_CONTROL1", 40773 /* IEMIRROR_CONTROL1_HI */ "IEMIRROR_CONTROL1_HI", 40774 /* IEMIRROR_CONTROL1_LO */ "IEMIRROR_CONTROL1_LO", 40775 /* IEMIRROR_CONTROL2_64 */ "IEMIRROR_CONTROL2", 40776 /* IEMIRROR_CONTROL3_64 */ "IEMIRROR_CONTROL3", 40777 /* IEMIRROR_CONTROL_64 */ "IEMIRROR_CONTROL", 40778 /* IEMIRROR_CONTROL_HI */ "", 40779 /* IEMIRROR_CONTROL_HI_64 */ "IEMIRROR_CONTROL_HI_64", 40780 /* IEMIRROR_CONTROL_LO_64 */ "IEMIRROR_CONTROL_LO_64", 40781 /* IEP_ECC_1B_ERR_CNT */ "", 40782 /* IEP_ECC_2B_ERR_CNT */ "", 40783 /* IEP_ECC_ERR_1B_INITIATE */ "", 40784 /* IEP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 40785 /* IEP_ECC_ERR_2B_INITIATE */ "", 40786 /* IEP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 40787 /* IEP_ECC_INTERRUPT_REGISTER */ "", 40788 /* IEP_ECC_INTERRUPT_REGISTER_MASK */ "", 40789 /* IEP_ECC_INTERRUPT_REGISTER_TEST */ "", 40790 /* IEP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 40791 /* IEP_ERROR_INITIATION_DATA */ "", 40792 /* IEP_GLBL_CFG */ "", 40793 /* IEP_GLOBAL_GENERAL_CFG_2 */ "", 40794 /* IEP_GLOBAL_MEM_OPTIONS */ "", 40795 /* IEP_GTIMER_CONFIGURATION */ "", 40796 /* IEP_IDR_INTERFACE_DEBUG_COUNTERS */ "", 40797 /* IEP_INCOMING_COLOR_MAP */ "", 40798 /* IEP_INDIRECT_COMMAND */ "", 40799 /* IEP_INDIRECT_COMMAND_ADDRESS */ "", 40800 /* IEP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 40801 /* IEP_INDIRECT_COMMAND_RD_DATA */ "", 40802 /* IEP_INDIRECT_COMMAND_WIDE_MEM */ "", 40803 /* IEP_INDIRECT_COMMAND_WR_DATA */ "", 40804 /* IEP_INDIRECT_FORCE_BUBBLE */ "", 40805 /* IEP_INGRESS_IN_INTERFACE_DEBUG_COUNTERS */ "", 40806 /* IEP_INGRESS_OUT_INTERFACE_DEBUG_COUNTERS */ "", 40807 /* IEP_INIT_SEQ_ON */ "", 40808 /* IEP_INTERRUPT_MASK_REGISTER */ "", 40809 /* IEP_INTERRUPT_REGISTER */ "", 40810 /* IEP_INTERRUPT_REGISTER_TEST */ "", 40811 /* IEP_MCDA_CBL_STAT_CTR */ "", 40812 /* IEP_MCDA_CFG */ "", 40813 /* IEP_MCDA_EBL_STAT_CTR */ "", 40814 /* IEP_MCDA_LAST_CMD_INDEX */ "", 40815 /* IEP_MCDA_OOP_FIFO_CNT */ "", 40816 /* IEP_MCDA_OOP_FIFO_POINTER_MASK */ "", 40817 /* IEP_MCDA_OOP_FIFO_RD_RESULTS */ "", 40818 /* IEP_MCDA_REFRESH_CFG */ "", 40819 /* IEP_MCDA_STAT_CFG */ "", 40820 /* IEP_MCDA_WRAP_INDEX */ "", 40821 /* IEP_MCDB_CBL_STAT_CTR */ "", 40822 /* IEP_MCDB_CFG */ "", 40823 /* IEP_MCDB_EBL_STAT_CTR */ "", 40824 /* IEP_MCDB_LAST_CMD_INDEX */ "", 40825 /* IEP_MCDB_OOP_FIFO_CNT */ "", 40826 /* IEP_MCDB_OOP_FIFO_POINTER_MASK */ "", 40827 /* IEP_MCDB_OOP_FIFO_RD_RESULTS */ "", 40828 /* IEP_MCDB_REFRESH_CFG */ "", 40829 /* IEP_MCDB_STAT_CFG */ "", 40830 /* IEP_MCDB_WRAP_INDEX */ "", 40831 /* IEP_RESERVED_MIRROR_ADDR */ "", 40832 /* IEP_RESERVED_MTCD */ "", 40833 /* IEP_RESERVED_MTCP */ "", 40834 /* IEP_RESERVED_SPARE_0 */ "", 40835 /* IEP_RESERVED_SPARE_1 */ "", 40836 /* IEP_RESERVED_SPARE_2 */ "", 40837 /* IEP_RESERVED_SPARE_3 */ "", 40838 /* IEP_SBUS_BROADCAST_ID */ "", 40839 /* IEP_SBUS_LAST_IN_CHAIN */ "", 40840 /* IESMIF_CONTROL */ "", 40841 /* IESMIF_CONTROL2 */ "", 40842 /* IESMIF_ECB_ECC_STATUS_DBE */ "", 40843 /* IESMIF_ECB_ECC_STATUS_SBE */ "", 40844 /* IESMIF_ECB_SBE_SYNDROME12 */ "", 40845 /* IESMIF_ECC_CONTROL */ "", 40846 /* IESMIF_EN_COR_ERR_RPT */ "", 40847 /* IESMIF_INTR_CLEAR */ "", 40848 /* IESMIF_INTR_ENABLE */ "", 40849 /* IESMIF_INTR_STATUS */ "", 40850 /* IESMIF_MEMORY_CONTROL */ "", 40851 /* IESMIF_PARITY_CONTROL */ "", 40852 /* IESMIF_STATUS2 */ "", 40853 /* IESMIF_STATUS3 */ "", 40854 /* IESMIF_STATUS4 */ "", 40855 /* IESMIF_STATUS5 */ "", 40856 /* IESMIF_STATUS6 */ "", 40857 /* IESMIF_STATUS7 */ "", 40858 /* IFP_AUX_TAG_FIELD_BUS_CONTAINER_SEL */ "", 40859 /* IFP_AUX_TAG_FIELD_BUS_CONTAINER_SEL_PIPE0 */ "", 40860 /* IFP_AUX_TAG_FIELD_BUS_CONTAINER_SEL_PIPE1 */ "", 40861 /* IFP_BIST_CAM_MODE */ "", 40862 /* IFP_BIST_CAM_MODE_PIPE0 */ "", 40863 /* IFP_BIST_CAM_MODE_PIPE1 */ "", 40864 /* IFP_BIST_CAM_MODE_PIPE2 */ "", 40865 /* IFP_BIST_CAM_MODE_PIPE3 */ "", 40866 /* IFP_BUS_PARITY_DEBUG */ "", 40867 /* IFP_CLK_GATING_CONTROL */ "", 40868 /* IFP_CONFIG */ "", 40869 /* IFP_CONFIG_PIPE0 */ "", 40870 /* IFP_CONFIG_PIPE1 */ "", 40871 /* IFP_CONFIG_PIPE2 */ "", 40872 /* IFP_CONFIG_PIPE3 */ "", 40873 /* IFP_CONFIG_PIPE4 */ "", 40874 /* IFP_CONFIG_PIPE5 */ "", 40875 /* IFP_CONFIG_PIPE6 */ "", 40876 /* IFP_CONFIG_PIPE7 */ "", 40877 /* IFP_COUNTER_MUX_DATA_STAGING_PARITY_CONTROL */ "", 40878 /* IFP_COUNTER_MUX_DATA_STAGING_PARITY_STATUS_INTR */ "", 40879 /* IFP_COUNTER_MUX_RAM_CONTROL */ "", 40880 /* IFP_COUNTER_PARITY_CONTROL */ "", 40881 /* IFP_COUNTER_PARITY_STATUS */ "", 40882 /* IFP_COUNTER_PARITY_STATUS_INTR */ "", 40883 /* IFP_COUNTER_PARITY_STATUS_NACK */ "", 40884 /* IFP_COUNTER_RAM_CONTROL */ "", 40885 /* IFP_COUNTER_TM */ "", 40886 /* IFP_COUNTER_TM_SLICE_0_2 */ "", 40887 /* IFP_COUNTER_TM_SLICE_3_5 */ "", 40888 /* IFP_COUNTER_TM_SLICE_6_8 */ "", 40889 /* IFP_COUNTER_TM_SLICE_9_11 */ "", 40890 /* IFP_ECMP_HASH_CONTROL */ "", 40891 /* IFP_EN_COR_ERR_RPT */ "", 40892 /* IFP_GM_LOGICAL_TO_PHYSICAL_MAPPING */ "", 40893 /* IFP_HIGHWAY_PASSTHRU_TM_74 */ "", 40894 /* IFP_HIGHWAY_PASSTHRU_TM_144 */ "", 40895 /* IFP_HW_CONTROL */ "", 40896 /* IFP_ING_DVP_2_CONTROL */ "", 40897 /* IFP_ING_DVP_2_CONTROL_PIPE0 */ "", 40898 /* IFP_ING_DVP_2_CONTROL_PIPE1 */ "", 40899 /* IFP_ING_DVP_2_CONTROL_PIPE2 */ "", 40900 /* IFP_ING_DVP_2_CONTROL_PIPE3 */ "", 40901 /* IFP_ING_DVP_2_PARITY_CONTROL */ "", 40902 /* IFP_ING_DVP_2_PARITY_STATUS_INTR */ "", 40903 /* IFP_ING_DVP_2_PARITY_STATUS_NACK */ "", 40904 /* IFP_ING_ZONE_MATCH_ID_CONFIG */ "", 40905 /* IFP_ING_ZONE_MATCH_ID_CONFIG_PIPE0 */ "", 40906 /* IFP_ING_ZONE_MATCH_ID_CONFIG_PIPE1 */ "", 40907 /* IFP_KEY_CLASSID_SELECT */ "", 40908 /* IFP_LOGICAL_TABLE_CONFIG */ "", 40909 /* IFP_LOGICAL_TABLE_CONFIG_PIPE0 */ "", 40910 /* IFP_LOGICAL_TABLE_CONFIG_PIPE1 */ "", 40911 /* IFP_LOGICAL_TABLE_CONFIG_PIPE2 */ "", 40912 /* IFP_LOGICAL_TABLE_CONFIG_PIPE3 */ "", 40913 /* IFP_LOGICAL_TABLE_CONFIG_PIPE4 */ "", 40914 /* IFP_LOGICAL_TABLE_CONFIG_PIPE5 */ "", 40915 /* IFP_LOGICAL_TABLE_CONFIG_PIPE6 */ "", 40916 /* IFP_LOGICAL_TABLE_CONFIG_PIPE7 */ "", 40917 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG */ "", 40918 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2 */ "", 40919 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64 */ "", 40920 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE0 */ "", 40921 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE1 */ "", 40922 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE2 */ "", 40923 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_2_PIPE3 */ "", 40924 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE0 */ "", 40925 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE1 */ "", 40926 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE2 */ "", 40927 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE3 */ "", 40928 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE4 */ "", 40929 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE5 */ "", 40930 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE6 */ "", 40931 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_64_PIPE7 */ "", 40932 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE0 */ "", 40933 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE1 */ "", 40934 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE2 */ "", 40935 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE3 */ "", 40936 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE4 */ "", 40937 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE5 */ "", 40938 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE6 */ "", 40939 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_CONFIG_PIPE7 */ "", 40940 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA */ "", 40941 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE0 */ "", 40942 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE1 */ "", 40943 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE2 */ "", 40944 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE3 */ "", 40945 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE4 */ "", 40946 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE5 */ "", 40947 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE6 */ "", 40948 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_DBG_DATA_PIPE7 */ "", 40949 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS */ "", 40950 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE0 */ "", 40951 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE1 */ "", 40952 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE2 */ "", 40953 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE3 */ "", 40954 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE4 */ "", 40955 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE5 */ "", 40956 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE6 */ "", 40957 /* IFP_LOGICAL_TABLE_SELECT_CAM_BIST_STATUS_PIPE7 */ "", 40958 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL", 40959 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE0 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE0", 40960 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE1 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE1", 40961 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE2 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE2", 40962 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE3 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE3", 40963 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE4 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE4", 40964 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE5 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE5", 40965 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE6 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE6", 40966 /* IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRL_PIPE7 */ "IFP_LOGICAL_TABLE_SELECT_CAM_CONTROL_PIPE7", 40967 /* IFP_LOGICAL_TABLE_SELECT_CONFIG */ "", 40968 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE0 */ "", 40969 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE1 */ "", 40970 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE2 */ "", 40971 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE3 */ "", 40972 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE4 */ "", 40973 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE5 */ "", 40974 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE6 */ "", 40975 /* IFP_LOGICAL_TABLE_SELECT_CONFIG_PIPE7 */ "", 40976 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL", 40977 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE0 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE0", 40978 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE1 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE1", 40979 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE2 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE2", 40980 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE3 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE3", 40981 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE4 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE4", 40982 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE5 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE5", 40983 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE6 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE6", 40984 /* IFP_LOGICAL_TABLE_SELECT_DATA_CTRL_PIPE7 */ "IFP_LOGICAL_TABLE_SELECT_DATA_CONTROL_PIPE7", 40985 /* IFP_LOGICAL_TABLE_SELECT_TM */ "", 40986 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE0 */ "", 40987 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE1 */ "", 40988 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE2 */ "", 40989 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE3 */ "", 40990 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE4 */ "", 40991 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE5 */ "", 40992 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE6 */ "", 40993 /* IFP_LOGICAL_TABLE_SELECT_TM_PIPE7 */ "", 40994 /* IFP_METER_CONTROL */ "", 40995 /* IFP_METER_MUX_DATA_STAGING_PARITY_CONTROL */ "", 40996 /* IFP_METER_MUX_DATA_STAGING_PARITY_STATUS_INTR */ "", 40997 /* IFP_METER_MUX_RAM_CONTROL */ "", 40998 /* IFP_METER_PARITY_CONTROL */ "", 40999 /* IFP_METER_PARITY_STATUS */ "", 41000 /* IFP_METER_PARITY_STATUS_INTR */ "", 41001 /* IFP_METER_PARITY_STATUS_NACK */ "", 41002 /* IFP_METER_RAM_CONTROL */ "", 41003 /* IFP_METER_TABLE_TM_SLICE_0_2 */ "", 41004 /* IFP_METER_TABLE_TM_SLICE_12_14 */ "", 41005 /* IFP_METER_TABLE_TM_SLICE_15_15 */ "", 41006 /* IFP_METER_TABLE_TM_SLICE_3_5 */ "", 41007 /* IFP_METER_TABLE_TM_SLICE_6_8 */ "", 41008 /* IFP_METER_TABLE_TM_SLICE_9_11 */ "", 41009 /* IFP_METER_WRITE_LAST_REFRESH_NUMBER */ "", 41010 /* IFP_MTU_CHECK_1_TABLE_ECC_CONTROL */ "", 41011 /* IFP_MTU_CHECK_1_TABLE_ECC_STATUS_INTR */ "", 41012 /* IFP_MTU_CHECK_1_TABLE_PARITY_STATUS_INTR */ "", 41013 /* IFP_MTU_CHECK_2_TABLE_ECC_CONTROL */ "", 41014 /* IFP_MTU_CHECK_2_TABLE_ECC_STATUS_INTR */ "", 41015 /* IFP_MTU_CHECK_2_TABLE_PARITY_STATUS_INTR */ "", 41016 /* IFP_PARITY_CONTROL */ "", 41017 /* IFP_PARITY_ERROR */ "", 41018 /* IFP_PARITY_ERROR_MASK */ "", 41019 /* IFP_PASSTHRU_HW_RAM_CONTROL */ "", 41020 /* IFP_PASSTHRU_HW_RAM_CONTROL_PIPE0 */ "", 41021 /* IFP_PASSTHRU_HW_RAM_CONTROL_PIPE1 */ "", 41022 /* IFP_PKT_ECC_CONTROL */ "", 41023 /* IFP_POLICY_PARITY_CONTROL */ "", 41024 /* IFP_POLICY_PARITY_STATUS */ "", 41025 /* IFP_POLICY_PARITY_STATUS_INTR */ "", 41026 /* IFP_POLICY_PARITY_STATUS_NACK */ "", 41027 /* IFP_POLICY_RAM_CONTROL */ "", 41028 /* IFP_POLICY_TABLE_PARITY_CONTROL */ "", 41029 /* IFP_POLICY_TABLE_PARITY_STATUS */ "", 41030 /* IFP_POLICY_TABLE_TM_SLICE_0_2 */ "", 41031 /* IFP_POLICY_TABLE_TM_SLICE_3_5 */ "", 41032 /* IFP_POLICY_TABLE_TM_SLICE_6_8 */ "", 41033 /* IFP_POLICY_TABLE_TM_SLICE_9_11 */ "", 41034 /* IFP_PORT_METER_MAP_CONTROL */ "", 41035 /* IFP_PORT_METER_MAP_RAM_CONTROL */ "", 41036 /* IFP_PWR_WATCH_DOG_CONTROL */ "", 41037 /* IFP_PWR_WATCH_DOG_STATUS */ "", 41038 /* IFP_REDIRECTION_PROFILE_PARITY_CONTROL */ "IFP_REDIRECTION_PROFILE_PARITY_CONTROL", 41039 /* IFP_REDIRECTION_PROFILE_PARITY_STATUS_INTR */ "IFP_REDIRECTION_PROFILE_PARITY_STATUS_INTR", 41040 /* IFP_REDIRECTION_PROFILE_PARITY_STATUS_NACK */ "IFP_REDIRECTION_PROFILE_PARITY_STATUS_NACK", 41041 /* IFP_REFRESH_CONFIG */ "", 41042 /* IFP_REFRESH_CONFIG_PIPE0 */ "", 41043 /* IFP_REFRESH_CONFIG_PIPE1 */ "", 41044 /* IFP_REFRESH_CONFIG_PIPE2 */ "", 41045 /* IFP_REFRESH_CONFIG_PIPE3 */ "", 41046 /* IFP_REFRESH_CONFIG_PIPE4 */ "", 41047 /* IFP_REFRESH_CONFIG_PIPE5 */ "", 41048 /* IFP_REFRESH_CONFIG_PIPE6 */ "", 41049 /* IFP_REFRESH_CONFIG_PIPE7 */ "", 41050 /* IFP_SLICE_METER_MAP_ENABLE */ "", 41051 /* IFP_SLICE_METER_MAP_ENABLE_PIPE0 */ "", 41052 /* IFP_SLICE_METER_MAP_ENABLE_PIPE1 */ "", 41053 /* IFP_SLICE_METER_MAP_ENABLE_PIPE2 */ "", 41054 /* IFP_SLICE_METER_MAP_ENABLE_PIPE3 */ "", 41055 /* IFP_SLICE_METER_MAP_ENABLE_PIPE4 */ "", 41056 /* IFP_SLICE_METER_MAP_ENABLE_PIPE5 */ "", 41057 /* IFP_SLICE_METER_MAP_ENABLE_PIPE6 */ "", 41058 /* IFP_SLICE_METER_MAP_ENABLE_PIPE7 */ "", 41059 /* IFP_SN_HISTORY_0_TABLE_ECC_STATUS_INTR */ "", 41060 /* IFP_SN_HISTORY_0_TABLE_PARITY_STATUS_INTR */ "", 41061 /* IFP_SN_HISTORY_10_TABLE_ECC_STATUS_INTR */ "", 41062 /* IFP_SN_HISTORY_10_TABLE_PARITY_STATUS_INTR */ "", 41063 /* IFP_SN_HISTORY_11_TABLE_ECC_STATUS_INTR */ "", 41064 /* IFP_SN_HISTORY_11_TABLE_PARITY_STATUS_INTR */ "", 41065 /* IFP_SN_HISTORY_12_TABLE_ECC_STATUS_INTR */ "", 41066 /* IFP_SN_HISTORY_12_TABLE_PARITY_STATUS_INTR */ "", 41067 /* IFP_SN_HISTORY_13_TABLE_ECC_STATUS_INTR */ "", 41068 /* IFP_SN_HISTORY_13_TABLE_PARITY_STATUS_INTR */ "", 41069 /* IFP_SN_HISTORY_14_TABLE_ECC_STATUS_INTR */ "", 41070 /* IFP_SN_HISTORY_14_TABLE_PARITY_STATUS_INTR */ "", 41071 /* IFP_SN_HISTORY_15_TABLE_ECC_STATUS_INTR */ "", 41072 /* IFP_SN_HISTORY_15_TABLE_PARITY_STATUS_INTR */ "", 41073 /* IFP_SN_HISTORY_1_TABLE_ECC_STATUS_INTR */ "", 41074 /* IFP_SN_HISTORY_1_TABLE_PARITY_STATUS_INTR */ "", 41075 /* IFP_SN_HISTORY_2_TABLE_ECC_STATUS_INTR */ "", 41076 /* IFP_SN_HISTORY_2_TABLE_PARITY_STATUS_INTR */ "", 41077 /* IFP_SN_HISTORY_3_TABLE_ECC_STATUS_INTR */ "", 41078 /* IFP_SN_HISTORY_3_TABLE_PARITY_STATUS_INTR */ "", 41079 /* IFP_SN_HISTORY_4_TABLE_ECC_STATUS_INTR */ "", 41080 /* IFP_SN_HISTORY_4_TABLE_PARITY_STATUS_INTR */ "", 41081 /* IFP_SN_HISTORY_5_TABLE_ECC_STATUS_INTR */ "", 41082 /* IFP_SN_HISTORY_5_TABLE_PARITY_STATUS_INTR */ "", 41083 /* IFP_SN_HISTORY_6_TABLE_ECC_STATUS_INTR */ "", 41084 /* IFP_SN_HISTORY_6_TABLE_PARITY_STATUS_INTR */ "", 41085 /* IFP_SN_HISTORY_7_TABLE_ECC_STATUS_INTR */ "", 41086 /* IFP_SN_HISTORY_7_TABLE_PARITY_STATUS_INTR */ "", 41087 /* IFP_SN_HISTORY_8_TABLE_ECC_STATUS_INTR */ "", 41088 /* IFP_SN_HISTORY_8_TABLE_PARITY_STATUS_INTR */ "", 41089 /* IFP_SN_HISTORY_9_TABLE_ECC_STATUS_INTR */ "", 41090 /* IFP_SN_HISTORY_9_TABLE_PARITY_STATUS_INTR */ "", 41091 /* IFP_SR_RX_HISTORY_TABLE_ECC_CONTROL */ "", 41092 /* IFP_SR_RX_SETTING_TABLE_ECC_CONTROL */ "", 41093 /* IFP_SR_RX_SETTING_TABLE_ECC_STATUS_INTR */ "", 41094 /* IFP_SR_RX_SETTING_TABLE_PARITY_STATUS_INTR */ "", 41095 /* IFP_SR_RX_WRITEBACK_TABLE_ECC_CONTROL */ "", 41096 /* IFP_SR_RX_WRITEBACK_TABLE_ECC_STATUS_INTR */ "", 41097 /* IFP_SR_RX_WRITEBACK_TABLE_PARITY_STATUS_INTR */ "", 41098 /* IFP_SR_TX_ECC_CONTROL */ "", 41099 /* IFP_SR_TX_TABLE_ECC_STATUS_INTR */ "", 41100 /* IFP_SR_TX_TABLE_PARITY_STATUS_INTR */ "", 41101 /* IFP_STORM_CONTROL_METER_TM */ "", 41102 /* IFP_STORM_CONTROL_PARITY_CONTROL */ "", 41103 /* IFP_STORM_CONTROL_PARITY_STATUS */ "", 41104 /* IFP_STORM_CONTROL_PARITY_STATUS_INTR */ "", 41105 /* IFP_STORM_CONTROL_PARITY_STATUS_NACK */ "", 41106 /* IFP_STORM_RAM_CONTROL */ "", 41107 /* IFP_SVM_METER_PARITY_CONTROL */ "", 41108 /* IFP_SVM_METER_PARITY_STATUS */ "", 41109 /* IFP_SVM_POLICY_PARITY_CONTROL */ "", 41110 /* IFP_SVM_POLICY_PARITY_STATUS */ "", 41111 /* IFP_TCAM0_DBGCTRL */ "IFP_TCAM0_CONTROL", 41112 /* IFP_TCAM0_DBGCTRL_PIPE0 */ "IFP_TCAM0_CONTROL_PIPE0", 41113 /* IFP_TCAM0_DBGCTRL_PIPE1 */ "IFP_TCAM0_CONTROL_PIPE1", 41114 /* IFP_TCAM0_DBGCTRL_PIPE2 */ "IFP_TCAM0_CONTROL_PIPE2", 41115 /* IFP_TCAM0_DBGCTRL_PIPE3 */ "IFP_TCAM0_CONTROL_PIPE3", 41116 /* IFP_TCAM0_DBGCTRL_PIPE4 */ "IFP_TCAM0_CONTROL_PIPE4", 41117 /* IFP_TCAM0_DBGCTRL_PIPE5 */ "IFP_TCAM0_CONTROL_PIPE5", 41118 /* IFP_TCAM0_DBGCTRL_PIPE6 */ "IFP_TCAM0_CONTROL_PIPE6", 41119 /* IFP_TCAM0_DBGCTRL_PIPE7 */ "IFP_TCAM0_CONTROL_PIPE7", 41120 /* IFP_TCAM10_DBGCTRL */ "IFP_TCAM10_CONTROL", 41121 /* IFP_TCAM10_DBGCTRL_PIPE0 */ "IFP_TCAM10_CONTROL_PIPE0", 41122 /* IFP_TCAM10_DBGCTRL_PIPE1 */ "IFP_TCAM10_CONTROL_PIPE1", 41123 /* IFP_TCAM10_DBGCTRL_PIPE2 */ "IFP_TCAM10_CONTROL_PIPE2", 41124 /* IFP_TCAM10_DBGCTRL_PIPE3 */ "IFP_TCAM10_CONTROL_PIPE3", 41125 /* IFP_TCAM11_DBGCTRL */ "IFP_TCAM11_CONTROL", 41126 /* IFP_TCAM11_DBGCTRL_PIPE0 */ "IFP_TCAM11_CONTROL_PIPE0", 41127 /* IFP_TCAM11_DBGCTRL_PIPE1 */ "IFP_TCAM11_CONTROL_PIPE1", 41128 /* IFP_TCAM11_DBGCTRL_PIPE2 */ "IFP_TCAM11_CONTROL_PIPE2", 41129 /* IFP_TCAM11_DBGCTRL_PIPE3 */ "IFP_TCAM11_CONTROL_PIPE3", 41130 /* IFP_TCAM1_DBGCTRL */ "IFP_TCAM1_CONTROL", 41131 /* IFP_TCAM1_DBGCTRL_PIPE0 */ "IFP_TCAM1_CONTROL_PIPE0", 41132 /* IFP_TCAM1_DBGCTRL_PIPE1 */ "IFP_TCAM1_CONTROL_PIPE1", 41133 /* IFP_TCAM1_DBGCTRL_PIPE2 */ "IFP_TCAM1_CONTROL_PIPE2", 41134 /* IFP_TCAM1_DBGCTRL_PIPE3 */ "IFP_TCAM1_CONTROL_PIPE3", 41135 /* IFP_TCAM1_DBGCTRL_PIPE4 */ "IFP_TCAM1_CONTROL_PIPE4", 41136 /* IFP_TCAM1_DBGCTRL_PIPE5 */ "IFP_TCAM1_CONTROL_PIPE5", 41137 /* IFP_TCAM1_DBGCTRL_PIPE6 */ "IFP_TCAM1_CONTROL_PIPE6", 41138 /* IFP_TCAM1_DBGCTRL_PIPE7 */ "IFP_TCAM1_CONTROL_PIPE7", 41139 /* IFP_TCAM2_DBGCTRL */ "IFP_TCAM2_CONTROL", 41140 /* IFP_TCAM2_DBGCTRL_PIPE0 */ "IFP_TCAM2_CONTROL_PIPE0", 41141 /* IFP_TCAM2_DBGCTRL_PIPE1 */ "IFP_TCAM2_CONTROL_PIPE1", 41142 /* IFP_TCAM2_DBGCTRL_PIPE2 */ "IFP_TCAM2_CONTROL_PIPE2", 41143 /* IFP_TCAM2_DBGCTRL_PIPE3 */ "IFP_TCAM2_CONTROL_PIPE3", 41144 /* IFP_TCAM2_DBGCTRL_PIPE4 */ "IFP_TCAM2_CONTROL_PIPE4", 41145 /* IFP_TCAM2_DBGCTRL_PIPE5 */ "IFP_TCAM2_CONTROL_PIPE5", 41146 /* IFP_TCAM2_DBGCTRL_PIPE6 */ "IFP_TCAM2_CONTROL_PIPE6", 41147 /* IFP_TCAM2_DBGCTRL_PIPE7 */ "IFP_TCAM2_CONTROL_PIPE7", 41148 /* IFP_TCAM3_DBGCTRL */ "IFP_TCAM3_CONTROL", 41149 /* IFP_TCAM3_DBGCTRL_PIPE0 */ "IFP_TCAM3_CONTROL_PIPE0", 41150 /* IFP_TCAM3_DBGCTRL_PIPE1 */ "IFP_TCAM3_CONTROL_PIPE1", 41151 /* IFP_TCAM3_DBGCTRL_PIPE2 */ "IFP_TCAM3_CONTROL_PIPE2", 41152 /* IFP_TCAM3_DBGCTRL_PIPE3 */ "IFP_TCAM3_CONTROL_PIPE3", 41153 /* IFP_TCAM3_DBGCTRL_PIPE4 */ "IFP_TCAM3_CONTROL_PIPE4", 41154 /* IFP_TCAM3_DBGCTRL_PIPE5 */ "IFP_TCAM3_CONTROL_PIPE5", 41155 /* IFP_TCAM3_DBGCTRL_PIPE6 */ "IFP_TCAM3_CONTROL_PIPE6", 41156 /* IFP_TCAM3_DBGCTRL_PIPE7 */ "IFP_TCAM3_CONTROL_PIPE7", 41157 /* IFP_TCAM4_DBGCTRL */ "IFP_TCAM4_CONTROL", 41158 /* IFP_TCAM4_DBGCTRL_PIPE0 */ "IFP_TCAM4_CONTROL_PIPE0", 41159 /* IFP_TCAM4_DBGCTRL_PIPE1 */ "IFP_TCAM4_CONTROL_PIPE1", 41160 /* IFP_TCAM4_DBGCTRL_PIPE2 */ "IFP_TCAM4_CONTROL_PIPE2", 41161 /* IFP_TCAM4_DBGCTRL_PIPE3 */ "IFP_TCAM4_CONTROL_PIPE3", 41162 /* IFP_TCAM4_DBGCTRL_PIPE4 */ "IFP_TCAM4_CONTROL_PIPE4", 41163 /* IFP_TCAM4_DBGCTRL_PIPE5 */ "IFP_TCAM4_CONTROL_PIPE5", 41164 /* IFP_TCAM4_DBGCTRL_PIPE6 */ "IFP_TCAM4_CONTROL_PIPE6", 41165 /* IFP_TCAM4_DBGCTRL_PIPE7 */ "IFP_TCAM4_CONTROL_PIPE7", 41166 /* IFP_TCAM5_DBGCTRL */ "IFP_TCAM5_CONTROL", 41167 /* IFP_TCAM5_DBGCTRL_PIPE0 */ "IFP_TCAM5_CONTROL_PIPE0", 41168 /* IFP_TCAM5_DBGCTRL_PIPE1 */ "IFP_TCAM5_CONTROL_PIPE1", 41169 /* IFP_TCAM5_DBGCTRL_PIPE2 */ "IFP_TCAM5_CONTROL_PIPE2", 41170 /* IFP_TCAM5_DBGCTRL_PIPE3 */ "IFP_TCAM5_CONTROL_PIPE3", 41171 /* IFP_TCAM5_DBGCTRL_PIPE4 */ "IFP_TCAM5_CONTROL_PIPE4", 41172 /* IFP_TCAM5_DBGCTRL_PIPE5 */ "IFP_TCAM5_CONTROL_PIPE5", 41173 /* IFP_TCAM5_DBGCTRL_PIPE6 */ "IFP_TCAM5_CONTROL_PIPE6", 41174 /* IFP_TCAM5_DBGCTRL_PIPE7 */ "IFP_TCAM5_CONTROL_PIPE7", 41175 /* IFP_TCAM6_DBGCTRL */ "IFP_TCAM6_CONTROL", 41176 /* IFP_TCAM6_DBGCTRL_PIPE0 */ "IFP_TCAM6_CONTROL_PIPE0", 41177 /* IFP_TCAM6_DBGCTRL_PIPE1 */ "IFP_TCAM6_CONTROL_PIPE1", 41178 /* IFP_TCAM6_DBGCTRL_PIPE2 */ "IFP_TCAM6_CONTROL_PIPE2", 41179 /* IFP_TCAM6_DBGCTRL_PIPE3 */ "IFP_TCAM6_CONTROL_PIPE3", 41180 /* IFP_TCAM6_DBGCTRL_PIPE4 */ "IFP_TCAM6_CONTROL_PIPE4", 41181 /* IFP_TCAM6_DBGCTRL_PIPE5 */ "IFP_TCAM6_CONTROL_PIPE5", 41182 /* IFP_TCAM6_DBGCTRL_PIPE6 */ "IFP_TCAM6_CONTROL_PIPE6", 41183 /* IFP_TCAM6_DBGCTRL_PIPE7 */ "IFP_TCAM6_CONTROL_PIPE7", 41184 /* IFP_TCAM7_DBGCTRL */ "IFP_TCAM7_CONTROL", 41185 /* IFP_TCAM7_DBGCTRL_PIPE0 */ "IFP_TCAM7_CONTROL_PIPE0", 41186 /* IFP_TCAM7_DBGCTRL_PIPE1 */ "IFP_TCAM7_CONTROL_PIPE1", 41187 /* IFP_TCAM7_DBGCTRL_PIPE2 */ "IFP_TCAM7_CONTROL_PIPE2", 41188 /* IFP_TCAM7_DBGCTRL_PIPE3 */ "IFP_TCAM7_CONTROL_PIPE3", 41189 /* IFP_TCAM7_DBGCTRL_PIPE4 */ "IFP_TCAM7_CONTROL_PIPE4", 41190 /* IFP_TCAM7_DBGCTRL_PIPE5 */ "IFP_TCAM7_CONTROL_PIPE5", 41191 /* IFP_TCAM7_DBGCTRL_PIPE6 */ "IFP_TCAM7_CONTROL_PIPE6", 41192 /* IFP_TCAM7_DBGCTRL_PIPE7 */ "IFP_TCAM7_CONTROL_PIPE7", 41193 /* IFP_TCAM8_DBGCTRL */ "IFP_TCAM8_CONTROL", 41194 /* IFP_TCAM8_DBGCTRL_PIPE0 */ "IFP_TCAM8_CONTROL_PIPE0", 41195 /* IFP_TCAM8_DBGCTRL_PIPE1 */ "IFP_TCAM8_CONTROL_PIPE1", 41196 /* IFP_TCAM8_DBGCTRL_PIPE2 */ "IFP_TCAM8_CONTROL_PIPE2", 41197 /* IFP_TCAM8_DBGCTRL_PIPE3 */ "IFP_TCAM8_CONTROL_PIPE3", 41198 /* IFP_TCAM8_DBGCTRL_PIPE4 */ "IFP_TCAM8_CONTROL_PIPE4", 41199 /* IFP_TCAM8_DBGCTRL_PIPE5 */ "IFP_TCAM8_CONTROL_PIPE5", 41200 /* IFP_TCAM8_DBGCTRL_PIPE6 */ "IFP_TCAM8_CONTROL_PIPE6", 41201 /* IFP_TCAM8_DBGCTRL_PIPE7 */ "IFP_TCAM8_CONTROL_PIPE7", 41202 /* IFP_TCAM9_DBGCTRL */ "IFP_TCAM9_CONTROL", 41203 /* IFP_TCAM9_DBGCTRL_PIPE0 */ "IFP_TCAM9_CONTROL_PIPE0", 41204 /* IFP_TCAM9_DBGCTRL_PIPE1 */ "IFP_TCAM9_CONTROL_PIPE1", 41205 /* IFP_TCAM9_DBGCTRL_PIPE2 */ "IFP_TCAM9_CONTROL_PIPE2", 41206 /* IFP_TCAM9_DBGCTRL_PIPE3 */ "IFP_TCAM9_CONTROL_PIPE3", 41207 /* IFP_TCAM_3M_POOL0_BIST_CONFIG */ "", 41208 /* IFP_TCAM_3M_POOL0_BIST_CONFIG_PIPE0 */ "", 41209 /* IFP_TCAM_3M_POOL0_BIST_CONFIG_PIPE1 */ "", 41210 /* IFP_TCAM_3M_POOL0_BIST_CONFIG_PIPE2 */ "", 41211 /* IFP_TCAM_3M_POOL0_BIST_CONFIG_PIPE3 */ "", 41212 /* IFP_TCAM_3M_POOL0_BIST_DBG_DATA */ "", 41213 /* IFP_TCAM_3M_POOL0_BIST_DBG_DATA_PIPE0 */ "", 41214 /* IFP_TCAM_3M_POOL0_BIST_DBG_DATA_PIPE1 */ "", 41215 /* IFP_TCAM_3M_POOL0_BIST_DBG_DATA_PIPE2 */ "", 41216 /* IFP_TCAM_3M_POOL0_BIST_DBG_DATA_PIPE3 */ "", 41217 /* IFP_TCAM_3M_POOL0_BIST_STATUS */ "", 41218 /* IFP_TCAM_3M_POOL0_BIST_STATUS_PIPE0 */ "", 41219 /* IFP_TCAM_3M_POOL0_BIST_STATUS_PIPE1 */ "", 41220 /* IFP_TCAM_3M_POOL0_BIST_STATUS_PIPE2 */ "", 41221 /* IFP_TCAM_3M_POOL0_BIST_STATUS_PIPE3 */ "", 41222 /* IFP_TCAM_3M_POOL1_BIST_CONFIG */ "", 41223 /* IFP_TCAM_3M_POOL1_BIST_CONFIG_PIPE0 */ "", 41224 /* IFP_TCAM_3M_POOL1_BIST_CONFIG_PIPE1 */ "", 41225 /* IFP_TCAM_3M_POOL1_BIST_CONFIG_PIPE2 */ "", 41226 /* IFP_TCAM_3M_POOL1_BIST_CONFIG_PIPE3 */ "", 41227 /* IFP_TCAM_3M_POOL1_BIST_DBG_DATA */ "", 41228 /* IFP_TCAM_3M_POOL1_BIST_DBG_DATA_PIPE0 */ "", 41229 /* IFP_TCAM_3M_POOL1_BIST_DBG_DATA_PIPE1 */ "", 41230 /* IFP_TCAM_3M_POOL1_BIST_DBG_DATA_PIPE2 */ "", 41231 /* IFP_TCAM_3M_POOL1_BIST_DBG_DATA_PIPE3 */ "", 41232 /* IFP_TCAM_3M_POOL1_BIST_STATUS */ "", 41233 /* IFP_TCAM_3M_POOL1_BIST_STATUS_PIPE0 */ "", 41234 /* IFP_TCAM_3M_POOL1_BIST_STATUS_PIPE1 */ "", 41235 /* IFP_TCAM_3M_POOL1_BIST_STATUS_PIPE2 */ "", 41236 /* IFP_TCAM_3M_POOL1_BIST_STATUS_PIPE3 */ "", 41237 /* IFP_TCAM_3M_POOL2_BIST_CONFIG */ "", 41238 /* IFP_TCAM_3M_POOL2_BIST_CONFIG_PIPE0 */ "", 41239 /* IFP_TCAM_3M_POOL2_BIST_CONFIG_PIPE1 */ "", 41240 /* IFP_TCAM_3M_POOL2_BIST_CONFIG_PIPE2 */ "", 41241 /* IFP_TCAM_3M_POOL2_BIST_CONFIG_PIPE3 */ "", 41242 /* IFP_TCAM_3M_POOL2_BIST_DBG_DATA */ "", 41243 /* IFP_TCAM_3M_POOL2_BIST_DBG_DATA_PIPE0 */ "", 41244 /* IFP_TCAM_3M_POOL2_BIST_DBG_DATA_PIPE1 */ "", 41245 /* IFP_TCAM_3M_POOL2_BIST_DBG_DATA_PIPE2 */ "", 41246 /* IFP_TCAM_3M_POOL2_BIST_DBG_DATA_PIPE3 */ "", 41247 /* IFP_TCAM_3M_POOL2_BIST_STATUS */ "", 41248 /* IFP_TCAM_3M_POOL2_BIST_STATUS_PIPE0 */ "", 41249 /* IFP_TCAM_3M_POOL2_BIST_STATUS_PIPE1 */ "", 41250 /* IFP_TCAM_3M_POOL2_BIST_STATUS_PIPE2 */ "", 41251 /* IFP_TCAM_3M_POOL2_BIST_STATUS_PIPE3 */ "", 41252 /* IFP_TCAM_3M_POOL3_BIST_CONFIG */ "", 41253 /* IFP_TCAM_3M_POOL3_BIST_CONFIG_PIPE0 */ "", 41254 /* IFP_TCAM_3M_POOL3_BIST_CONFIG_PIPE1 */ "", 41255 /* IFP_TCAM_3M_POOL3_BIST_CONFIG_PIPE2 */ "", 41256 /* IFP_TCAM_3M_POOL3_BIST_CONFIG_PIPE3 */ "", 41257 /* IFP_TCAM_3M_POOL3_BIST_DBG_DATA */ "", 41258 /* IFP_TCAM_3M_POOL3_BIST_DBG_DATA_PIPE0 */ "", 41259 /* IFP_TCAM_3M_POOL3_BIST_DBG_DATA_PIPE1 */ "", 41260 /* IFP_TCAM_3M_POOL3_BIST_DBG_DATA_PIPE2 */ "", 41261 /* IFP_TCAM_3M_POOL3_BIST_DBG_DATA_PIPE3 */ "", 41262 /* IFP_TCAM_3M_POOL3_BIST_STATUS */ "", 41263 /* IFP_TCAM_3M_POOL3_BIST_STATUS_PIPE0 */ "", 41264 /* IFP_TCAM_3M_POOL3_BIST_STATUS_PIPE1 */ "", 41265 /* IFP_TCAM_3M_POOL3_BIST_STATUS_PIPE2 */ "", 41266 /* IFP_TCAM_3M_POOL3_BIST_STATUS_PIPE3 */ "", 41267 /* IFP_TCAM_CAM_CONTROL */ "", 41268 /* IFP_TCAM_CAM_CONTROL_PIPE0 */ "", 41269 /* IFP_TCAM_CAM_CONTROL_PIPE1 */ "", 41270 /* IFP_TCAM_CAM_CONTROL_PIPE2 */ "", 41271 /* IFP_TCAM_CAM_CONTROL_PIPE3 */ "", 41272 /* IFP_TCAM_CAM_CONTROL_PIPE4 */ "", 41273 /* IFP_TCAM_CAM_CONTROL_PIPE5 */ "", 41274 /* IFP_TCAM_CAM_CONTROL_PIPE6 */ "", 41275 /* IFP_TCAM_CAM_CONTROL_PIPE7 */ "", 41276 /* IFP_TCAM_POOL0_BISTCTRL */ "IFP_TCAM_POOL0_BIST_CONTROL", 41277 /* IFP_TCAM_POOL0_BISTCTRL_PIPE0 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE0", 41278 /* IFP_TCAM_POOL0_BISTCTRL_PIPE1 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE1", 41279 /* IFP_TCAM_POOL0_BISTCTRL_PIPE2 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE2", 41280 /* IFP_TCAM_POOL0_BISTCTRL_PIPE3 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE3", 41281 /* IFP_TCAM_POOL0_BISTCTRL_PIPE4 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE4", 41282 /* IFP_TCAM_POOL0_BISTCTRL_PIPE5 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE5", 41283 /* IFP_TCAM_POOL0_BISTCTRL_PIPE6 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE6", 41284 /* IFP_TCAM_POOL0_BISTCTRL_PIPE7 */ "IFP_TCAM_POOL0_BIST_CONTROL_PIPE7", 41285 /* IFP_TCAM_POOL0_BIST_CONFIG */ "", 41286 /* IFP_TCAM_POOL0_BIST_CONFIG_2 */ "", 41287 /* IFP_TCAM_POOL0_BIST_CONFIG_64 */ "", 41288 /* IFP_TCAM_POOL0_BIST_CONFIG_2_PIPE0 */ "", 41289 /* IFP_TCAM_POOL0_BIST_CONFIG_2_PIPE1 */ "", 41290 /* IFP_TCAM_POOL0_BIST_CONFIG_2_PIPE2 */ "", 41291 /* IFP_TCAM_POOL0_BIST_CONFIG_2_PIPE3 */ "", 41292 /* IFP_TCAM_POOL0_BIST_CONFIG_64_PIPE0 */ "", 41293 /* IFP_TCAM_POOL0_BIST_CONFIG_64_PIPE1 */ "", 41294 /* IFP_TCAM_POOL0_BIST_CONFIG_PIPE0 */ "", 41295 /* IFP_TCAM_POOL0_BIST_CONFIG_PIPE1 */ "", 41296 /* IFP_TCAM_POOL0_BIST_CONFIG_PIPE2 */ "", 41297 /* IFP_TCAM_POOL0_BIST_CONFIG_PIPE3 */ "", 41298 /* IFP_TCAM_POOL0_BIST_DBG_DATA */ "", 41299 /* IFP_TCAM_POOL0_BIST_DBG_DATA_PIPE0 */ "", 41300 /* IFP_TCAM_POOL0_BIST_DBG_DATA_PIPE1 */ "", 41301 /* IFP_TCAM_POOL0_BIST_DBG_DATA_PIPE2 */ "", 41302 /* IFP_TCAM_POOL0_BIST_DBG_DATA_PIPE3 */ "", 41303 /* IFP_TCAM_POOL0_BIST_STATUS */ "", 41304 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE0 */ "", 41305 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE1 */ "", 41306 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE2 */ "", 41307 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE3 */ "", 41308 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE4 */ "", 41309 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE5 */ "", 41310 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE6 */ "", 41311 /* IFP_TCAM_POOL0_BIST_STATUS_PIPE7 */ "", 41312 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64 */ "", 41313 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE0 */ "", 41314 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE1 */ "", 41315 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE2 */ "", 41316 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE3 */ "", 41317 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE4 */ "", 41318 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE5 */ "", 41319 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE6 */ "", 41320 /* IFP_TCAM_POOL0_CAM_BIST_CONFIG_64_PIPE7 */ "", 41321 /* IFP_TCAM_POOL0_DBGCTRL */ "IFP_TCAM_POOL0_CONTROL", 41322 /* IFP_TCAM_POOL0_DBGCTRL_PIPE0 */ "IFP_TCAM_POOL0_CONTROL_PIPE0", 41323 /* IFP_TCAM_POOL0_DBGCTRL_PIPE1 */ "IFP_TCAM_POOL0_CONTROL_PIPE1", 41324 /* IFP_TCAM_POOL1_BISTCTRL */ "IFP_TCAM_POOL1_BIST_CONTROL", 41325 /* IFP_TCAM_POOL1_BISTCTRL_PIPE0 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE0", 41326 /* IFP_TCAM_POOL1_BISTCTRL_PIPE1 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE1", 41327 /* IFP_TCAM_POOL1_BISTCTRL_PIPE2 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE2", 41328 /* IFP_TCAM_POOL1_BISTCTRL_PIPE3 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE3", 41329 /* IFP_TCAM_POOL1_BISTCTRL_PIPE4 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE4", 41330 /* IFP_TCAM_POOL1_BISTCTRL_PIPE5 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE5", 41331 /* IFP_TCAM_POOL1_BISTCTRL_PIPE6 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE6", 41332 /* IFP_TCAM_POOL1_BISTCTRL_PIPE7 */ "IFP_TCAM_POOL1_BIST_CONTROL_PIPE7", 41333 /* IFP_TCAM_POOL1_BIST_CONFIG */ "", 41334 /* IFP_TCAM_POOL1_BIST_CONFIG_2 */ "", 41335 /* IFP_TCAM_POOL1_BIST_CONFIG_64 */ "", 41336 /* IFP_TCAM_POOL1_BIST_CONFIG_2_PIPE0 */ "", 41337 /* IFP_TCAM_POOL1_BIST_CONFIG_2_PIPE1 */ "", 41338 /* IFP_TCAM_POOL1_BIST_CONFIG_2_PIPE2 */ "", 41339 /* IFP_TCAM_POOL1_BIST_CONFIG_2_PIPE3 */ "", 41340 /* IFP_TCAM_POOL1_BIST_CONFIG_64_PIPE0 */ "", 41341 /* IFP_TCAM_POOL1_BIST_CONFIG_64_PIPE1 */ "", 41342 /* IFP_TCAM_POOL1_BIST_CONFIG_PIPE0 */ "", 41343 /* IFP_TCAM_POOL1_BIST_CONFIG_PIPE1 */ "", 41344 /* IFP_TCAM_POOL1_BIST_CONFIG_PIPE2 */ "", 41345 /* IFP_TCAM_POOL1_BIST_CONFIG_PIPE3 */ "", 41346 /* IFP_TCAM_POOL1_BIST_DBG_DATA */ "", 41347 /* IFP_TCAM_POOL1_BIST_DBG_DATA_PIPE0 */ "", 41348 /* IFP_TCAM_POOL1_BIST_DBG_DATA_PIPE1 */ "", 41349 /* IFP_TCAM_POOL1_BIST_DBG_DATA_PIPE2 */ "", 41350 /* IFP_TCAM_POOL1_BIST_DBG_DATA_PIPE3 */ "", 41351 /* IFP_TCAM_POOL1_BIST_STATUS */ "", 41352 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE0 */ "", 41353 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE1 */ "", 41354 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE2 */ "", 41355 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE3 */ "", 41356 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE4 */ "", 41357 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE5 */ "", 41358 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE6 */ "", 41359 /* IFP_TCAM_POOL1_BIST_STATUS_PIPE7 */ "", 41360 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64 */ "", 41361 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE0 */ "", 41362 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE1 */ "", 41363 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE2 */ "", 41364 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE3 */ "", 41365 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE4 */ "", 41366 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE5 */ "", 41367 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE6 */ "", 41368 /* IFP_TCAM_POOL1_CAM_BIST_CONFIG_64_PIPE7 */ "", 41369 /* IFP_TCAM_POOL1_DBGCTRL */ "IFP_TCAM_POOL1_CONTROL", 41370 /* IFP_TCAM_POOL1_DBGCTRL_PIPE0 */ "IFP_TCAM_POOL1_CONTROL_PIPE0", 41371 /* IFP_TCAM_POOL1_DBGCTRL_PIPE1 */ "IFP_TCAM_POOL1_CONTROL_PIPE1", 41372 /* IFP_TCAM_POOL2_BISTCTRL */ "IFP_TCAM_POOL2_BIST_CONTROL", 41373 /* IFP_TCAM_POOL2_BISTCTRL_PIPE0 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE0", 41374 /* IFP_TCAM_POOL2_BISTCTRL_PIPE1 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE1", 41375 /* IFP_TCAM_POOL2_BISTCTRL_PIPE2 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE2", 41376 /* IFP_TCAM_POOL2_BISTCTRL_PIPE3 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE3", 41377 /* IFP_TCAM_POOL2_BISTCTRL_PIPE4 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE4", 41378 /* IFP_TCAM_POOL2_BISTCTRL_PIPE5 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE5", 41379 /* IFP_TCAM_POOL2_BISTCTRL_PIPE6 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE6", 41380 /* IFP_TCAM_POOL2_BISTCTRL_PIPE7 */ "IFP_TCAM_POOL2_BIST_CONTROL_PIPE7", 41381 /* IFP_TCAM_POOL2_BIST_CONFIG */ "", 41382 /* IFP_TCAM_POOL2_BIST_CONFIG_2 */ "", 41383 /* IFP_TCAM_POOL2_BIST_CONFIG_64 */ "", 41384 /* IFP_TCAM_POOL2_BIST_CONFIG_2_PIPE0 */ "", 41385 /* IFP_TCAM_POOL2_BIST_CONFIG_2_PIPE1 */ "", 41386 /* IFP_TCAM_POOL2_BIST_CONFIG_2_PIPE2 */ "", 41387 /* IFP_TCAM_POOL2_BIST_CONFIG_2_PIPE3 */ "", 41388 /* IFP_TCAM_POOL2_BIST_CONFIG_64_PIPE0 */ "", 41389 /* IFP_TCAM_POOL2_BIST_CONFIG_64_PIPE1 */ "", 41390 /* IFP_TCAM_POOL2_BIST_CONFIG_PIPE0 */ "", 41391 /* IFP_TCAM_POOL2_BIST_CONFIG_PIPE1 */ "", 41392 /* IFP_TCAM_POOL2_BIST_CONFIG_PIPE2 */ "", 41393 /* IFP_TCAM_POOL2_BIST_CONFIG_PIPE3 */ "", 41394 /* IFP_TCAM_POOL2_BIST_DBG_DATA */ "", 41395 /* IFP_TCAM_POOL2_BIST_DBG_DATA_PIPE0 */ "", 41396 /* IFP_TCAM_POOL2_BIST_DBG_DATA_PIPE1 */ "", 41397 /* IFP_TCAM_POOL2_BIST_DBG_DATA_PIPE2 */ "", 41398 /* IFP_TCAM_POOL2_BIST_DBG_DATA_PIPE3 */ "", 41399 /* IFP_TCAM_POOL2_BIST_STATUS */ "", 41400 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE0 */ "", 41401 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE1 */ "", 41402 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE2 */ "", 41403 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE3 */ "", 41404 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE4 */ "", 41405 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE5 */ "", 41406 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE6 */ "", 41407 /* IFP_TCAM_POOL2_BIST_STATUS_PIPE7 */ "", 41408 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64 */ "", 41409 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE0 */ "", 41410 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE1 */ "", 41411 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE2 */ "", 41412 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE3 */ "", 41413 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE4 */ "", 41414 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE5 */ "", 41415 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE6 */ "", 41416 /* IFP_TCAM_POOL2_CAM_BIST_CONFIG_64_PIPE7 */ "", 41417 /* IFP_TCAM_POOL2_DBGCTRL */ "IFP_TCAM_POOL2_CONTROL", 41418 /* IFP_TCAM_POOL2_DBGCTRL_PIPE0 */ "IFP_TCAM_POOL2_CONTROL_PIPE0", 41419 /* IFP_TCAM_POOL2_DBGCTRL_PIPE1 */ "IFP_TCAM_POOL2_CONTROL_PIPE1", 41420 /* IFP_TCAM_POOL3_BISTCTRL */ "IFP_TCAM_POOL3_BIST_CONTROL", 41421 /* IFP_TCAM_POOL3_BISTCTRL_PIPE0 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE0", 41422 /* IFP_TCAM_POOL3_BISTCTRL_PIPE1 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE1", 41423 /* IFP_TCAM_POOL3_BISTCTRL_PIPE2 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE2", 41424 /* IFP_TCAM_POOL3_BISTCTRL_PIPE3 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE3", 41425 /* IFP_TCAM_POOL3_BISTCTRL_PIPE4 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE4", 41426 /* IFP_TCAM_POOL3_BISTCTRL_PIPE5 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE5", 41427 /* IFP_TCAM_POOL3_BISTCTRL_PIPE6 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE6", 41428 /* IFP_TCAM_POOL3_BISTCTRL_PIPE7 */ "IFP_TCAM_POOL3_BIST_CONTROL_PIPE7", 41429 /* IFP_TCAM_POOL3_BIST_CONFIG */ "", 41430 /* IFP_TCAM_POOL3_BIST_CONFIG_2 */ "", 41431 /* IFP_TCAM_POOL3_BIST_CONFIG_64 */ "", 41432 /* IFP_TCAM_POOL3_BIST_CONFIG_2_PIPE0 */ "", 41433 /* IFP_TCAM_POOL3_BIST_CONFIG_2_PIPE1 */ "", 41434 /* IFP_TCAM_POOL3_BIST_CONFIG_2_PIPE2 */ "", 41435 /* IFP_TCAM_POOL3_BIST_CONFIG_2_PIPE3 */ "", 41436 /* IFP_TCAM_POOL3_BIST_CONFIG_64_PIPE0 */ "", 41437 /* IFP_TCAM_POOL3_BIST_CONFIG_64_PIPE1 */ "", 41438 /* IFP_TCAM_POOL3_BIST_CONFIG_PIPE0 */ "", 41439 /* IFP_TCAM_POOL3_BIST_CONFIG_PIPE1 */ "", 41440 /* IFP_TCAM_POOL3_BIST_CONFIG_PIPE2 */ "", 41441 /* IFP_TCAM_POOL3_BIST_CONFIG_PIPE3 */ "", 41442 /* IFP_TCAM_POOL3_BIST_DBG_DATA */ "", 41443 /* IFP_TCAM_POOL3_BIST_DBG_DATA_PIPE0 */ "", 41444 /* IFP_TCAM_POOL3_BIST_DBG_DATA_PIPE1 */ "", 41445 /* IFP_TCAM_POOL3_BIST_DBG_DATA_PIPE2 */ "", 41446 /* IFP_TCAM_POOL3_BIST_DBG_DATA_PIPE3 */ "", 41447 /* IFP_TCAM_POOL3_BIST_STATUS */ "", 41448 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE0 */ "", 41449 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE1 */ "", 41450 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE2 */ "", 41451 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE3 */ "", 41452 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE4 */ "", 41453 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE5 */ "", 41454 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE6 */ "", 41455 /* IFP_TCAM_POOL3_BIST_STATUS_PIPE7 */ "", 41456 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64 */ "", 41457 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE0 */ "", 41458 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE1 */ "", 41459 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE2 */ "", 41460 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE3 */ "", 41461 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE4 */ "", 41462 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE5 */ "", 41463 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE6 */ "", 41464 /* IFP_TCAM_POOL3_CAM_BIST_CONFIG_64_PIPE7 */ "", 41465 /* IFP_TCAM_POOL3_DBGCTRL */ "IFP_TCAM_POOL3_CONTROL", 41466 /* IFP_TCAM_POOL3_DBGCTRL_PIPE0 */ "IFP_TCAM_POOL3_CONTROL_PIPE0", 41467 /* IFP_TCAM_POOL3_DBGCTRL_PIPE1 */ "IFP_TCAM_POOL3_CONTROL_PIPE1", 41468 /* IFP_TCAM_POOL4_BIST_CONFIG_64 */ "", 41469 /* IFP_TCAM_POOL4_BIST_CONFIG_64_PIPE0 */ "", 41470 /* IFP_TCAM_POOL4_BIST_STATUS */ "", 41471 /* IFP_TCAM_POOL4_BIST_STATUS_PIPE0 */ "", 41472 /* IFP_TCAM_POOL4_DBGCTRL */ "IFP_TCAM_POOL4_CONTROL", 41473 /* IFP_TCAM_POOL4_DBGCTRL_PIPE0 */ "IFP_TCAM_POOL4_CONTROL_PIPE0", 41474 /* IFP_TCAM_POOL5_BIST_CONFIG_64 */ "", 41475 /* IFP_TCAM_POOL5_BIST_CONFIG_64_PIPE0 */ "", 41476 /* IFP_TCAM_POOL5_BIST_STATUS */ "", 41477 /* IFP_TCAM_POOL5_BIST_STATUS_PIPE0 */ "", 41478 /* IFP_TCAM_POOL5_DBGCTRL */ "IFP_TCAM_POOL5_CONTROL", 41479 /* IFP_TCAM_POOL5_DBGCTRL_PIPE0 */ "IFP_TCAM_POOL5_CONTROL_PIPE0", 41480 /* IFP_TSN_CONTROL */ "", 41481 /* IFP_WRONG_LAN_A_STATUS_INTR */ "", 41482 /* IFP_WRONG_LAN_B_STATUS_INTR */ "", 41483 /* IFWD1_EN_COR_ERR_RPT */ "", 41484 /* IFWD1_RAM_CONTROL_0 */ "", 41485 /* IFWD1_RAM_CONTROL_1 */ "", 41486 /* IFWD1_RAM_CONTROL_2 */ "", 41487 /* IFWD1_RAM_CONTROL_3 */ "", 41488 /* IFWD1_RAM_CONTROL_0_PIPE0 */ "", 41489 /* IFWD1_RAM_CONTROL_0_PIPE1 */ "", 41490 /* IFWD1_RAM_CONTROL_1_PIPE0 */ "", 41491 /* IFWD1_RAM_CONTROL_1_PIPE1 */ "", 41492 /* IFWD1_RAM_CONTROL_2_PIPE0 */ "", 41493 /* IFWD1_RAM_CONTROL_2_PIPE1 */ "", 41494 /* IFWD1_RAM_CONTROL_3_PIPE0 */ "", 41495 /* IFWD1_RAM_CONTROL_3_PIPE1 */ "", 41496 /* IFWD1_RAM_DBGCTRL_0_64 */ "IFWD1_RAM_CTRL", 41497 /* IFWD1_RAM_DBGCTRL_0_64_PIPE0 */ "IFWD1_RAM_CTRL_PIPE0", 41498 /* IFWD1_RAM_DBGCTRL_0_64_PIPE1 */ "IFWD1_RAM_CTRL_PIPE1", 41499 /* IFWD1_RAM_DBGCTRL_0_64_PIPE2 */ "IFWD1_RAM_CTRL_PIPE2", 41500 /* IFWD1_RAM_DBGCTRL_0_64_PIPE3 */ "IFWD1_RAM_CTRL_PIPE3", 41501 /* IFWD1_RAM_DBGCTRL_0_64_PIPE4 */ "IFWD1_RAM_CTRL_PIPE4", 41502 /* IFWD1_RAM_DBGCTRL_0_64_PIPE5 */ "IFWD1_RAM_CTRL_PIPE5", 41503 /* IFWD1_RAM_DBGCTRL_0_64_PIPE6 */ "IFWD1_RAM_CTRL_PIPE6", 41504 /* IFWD1_RAM_DBGCTRL_0_64_PIPE7 */ "IFWD1_RAM_CTRL_PIPE7", 41505 /* IFWD1_SER_CONTROL */ "", 41506 /* IFWD2_EN_COR_ERR_RPT */ "", 41507 /* IFWD2_RAM_CONTROL_0 */ "", 41508 /* IFWD2_RAM_CONTROL_0_PIPE0 */ "", 41509 /* IFWD2_RAM_CONTROL_0_PIPE1 */ "", 41510 /* IFWD2_SER_CONTROL */ "", 41511 /* IFWD_EN_COR_ERR_RPT */ "", 41512 /* IFWD_SER_CONTROL */ "", 41513 /* IGMP_MLD_PKT_CONTROL */ "", 41514 /* IHB_ACTION_DISABLE */ "", 41515 /* IHB_ACTION_PROFILE_GENERAL */ "", 41516 /* IHB_ACTION_PROFILE_IEEE_1588 */ "", 41517 /* IHB_ACTION_PROFILE_PACKET_HAS_SER */ "", 41518 /* IHB_ACTION_PROFILE_RPF */ "", 41519 /* IHB_ACTION_PROFILE_SAME_INTERFACE */ "", 41520 /* IHB_ACTION_PROFILE_SA_DROP_MAP */ "", 41521 /* IHB_ACTION_PROFILE_SA_NOT_FOUND_MAP */ "", 41522 /* IHB_ALL_ESADI_RBRIDGES */ "", 41523 /* IHB_APP_PREFIX_CONTROL */ "", 41524 /* IHB_BAD_REPLIES_COUNTER */ "", 41525 /* IHB_BUILD_OAM_TS_HEADER */ "", 41526 /* IHB_COE_ACTION_PROFILE */ "", 41527 /* IHB_COE_CFGS */ "", 41528 /* IHB_CONSISTENT_HASHING_CONFIGRATION */ "", 41529 /* IHB_CONSISTENT_HASHING_FORBIDDEN_TRAPS */ "", 41530 /* IHB_CONSISTENT_HASHING_LB_KEY_CFG */ "", 41531 /* IHB_CONSISTENT_HASHING_VARIABLES */ "", 41532 /* IHB_COS_PROFILE_TO_USE_LAYER_2_PCP_MAP */ "", 41533 /* IHB_CPU_INFO_REPLY_COUNTER */ "", 41534 /* IHB_CPU_INFO_REPLY_ERROR_COUNTER */ "", 41535 /* IHB_CPU_INFO_REPLY_OVF_COUNTER */ "", 41536 /* IHB_CPU_LOOKUP_REPLY_COUNTER */ "", 41537 /* IHB_CPU_LOOKUP_REPLY_ERROR_COUNTER */ "", 41538 /* IHB_CPU_LOOKUP_REPLY_OVF_COUNTER */ "", 41539 /* IHB_CPU_RECORDS_COUNTER */ "", 41540 /* IHB_CPU_RECORD_CONTROL */ "", 41541 /* IHB_CPU_RECORD_DATA_LSB */ "", 41542 /* IHB_CPU_RECORD_DATA_MSB */ "", 41543 /* IHB_CPU_RECORD_OPCODE */ "", 41544 /* IHB_CPU_RECORD_PRIO */ "", 41545 /* IHB_CPU_TRAP_CODE_PROFILE */ "", 41546 /* IHB_DBG_FER_TRAP */ "", 41547 /* IHB_DBG_FIRST_TM_COMMAND */ "", 41548 /* IHB_DBG_FLP_CONSISTENT_HASHING_PROGRAM */ "", 41549 /* IHB_DBG_FLP_FIFO */ "", 41550 /* IHB_DBG_FLP_PACKETS_REJECTED_BY_EGW_CNT */ "", 41551 /* IHB_DBG_FLP_PROGRAM_SELECTION_CAM_LINE */ "", 41552 /* IHB_DBG_FLP_SELECTED_PROGRAM */ "", 41553 /* IHB_DBG_FLP_TRAP_0 */ "", 41554 /* IHB_DBG_FLP_TRAP_1 */ "", 41555 /* IHB_DBG_IEEE_1588_IDENTIFICATION_CAM_LINE */ "", 41556 /* IHB_DBG_LAST_KEY_A */ "", 41557 /* IHB_DBG_LAST_KEY_B */ "", 41558 /* IHB_DBG_LAST_KEY_C */ "", 41559 /* IHB_DBG_LAST_KEY_D */ "", 41560 /* IHB_DBG_LAST_RESOLVED_TRAP */ "", 41561 /* IHB_DBG_LAST_TRAP_CHANGE_DESTINATION */ "", 41562 /* IHB_DBG_LAST_TRAP_CHANGE_DESTINATION_REG */ "", 41563 /* IHB_DBG_PMF_SELECTED_CAM_LINE_0 */ "", 41564 /* IHB_DBG_PMF_SELECTED_CAM_LINE_1 */ "", 41565 /* IHB_DBG_PMF_SELECTED_PROGRAM */ "", 41566 /* IHB_DEFAULT_LEM_PAYLOAD */ "", 41567 /* IHB_DEFAULT_TCAM_ACTION */ "", 41568 /* IHB_ECC_1B_ERR_CNT */ "", 41569 /* IHB_ECC_2B_ERR_CNT */ "", 41570 /* IHB_ECC_ERR_1B_INITIATE */ "", 41571 /* IHB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 41572 /* IHB_ECC_ERR_2B_INITIATE */ "", 41573 /* IHB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 41574 /* IHB_ECC_INTERRUPT_REGISTER */ "", 41575 /* IHB_ECC_INTERRUPT_REGISTER_MASK */ "", 41576 /* IHB_ECC_INTERRUPT_REGISTER_TEST */ "", 41577 /* IHB_ECMP_LB_KEY_CFG */ "", 41578 /* IHB_ELK_RESULT_CFG */ "", 41579 /* IHB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 41580 /* IHB_ERROR_INITIATION_DATA */ "", 41581 /* IHB_ETHERNET_ACTION_PROFILES */ "", 41582 /* IHB_FC_ACTION_PROFILES */ "", 41583 /* IHB_FEM_FES_COMPARE_SELECTION */ "", 41584 /* IHB_FERA_FIFO_CONFIG */ "", 41585 /* IHB_FER_GENERAL_CONFIGURATIONS */ "", 41586 /* IHB_FLP_GENERAL_CFG */ "", 41587 /* IHB_GENERAL_CFGS */ "", 41588 /* IHB_GLOBAL_GENERAL_CFG_3 */ "", 41589 /* IHB_GLOBAL_MEM_OPTIONS */ "", 41590 /* IHB_GLOBAL_PP_1 */ "", 41591 /* IHB_GLOBAL_PP_7 */ "", 41592 /* IHB_GLOBAL_PP_8 */ "", 41593 /* IHB_GLOBAL_SYS_HEADER_CFG */ "", 41594 /* IHB_GOOD_REPLIES_COUNTER */ "", 41595 /* IHB_GTIMER_CONFIGURATION */ "", 41596 /* IHB_GTIMER_TRIGGER */ "", 41597 /* IHB_HEADER_BELOW_IS_ETH_MAPPING */ "", 41598 /* IHB_ICMP_ACTION_PROFILES */ "", 41599 /* IHB_IGMP_ACTION_PROFILES */ "", 41600 /* IHB_IGNORE_CP_CFG */ "", 41601 /* IHB_INDIRECT_COMMAND */ "", 41602 /* IHB_INDIRECT_COMMAND_ADDRESS */ "", 41603 /* IHB_INDIRECT_COMMAND_DATA_INCREMENT */ "", 41604 /* IHB_INDIRECT_COMMAND_RD_DATA */ "", 41605 /* IHB_INDIRECT_COMMAND_WIDE_MEM */ "", 41606 /* IHB_INDIRECT_COMMAND_WR_DATA */ "", 41607 /* IHB_INDIRECT_FORCE_BUBBLE */ "", 41608 /* IHB_INDIRECT_WR_MASK */ "", 41609 /* IHB_INFO_DATA */ "", 41610 /* IHB_INFO_OPCODE */ "", 41611 /* IHB_INFO_REPLY */ "", 41612 /* IHB_INFO_REPLY_DATA */ "", 41613 /* IHB_INFO_SEQ_NUM */ "", 41614 /* IHB_INTERLAKEN_CFGS */ "", 41615 /* IHB_INTERNAL_FIELDS_DATA */ "", 41616 /* IHB_INTERRUPT_MASK_REGISTER */ "", 41617 /* IHB_INTERRUPT_REGISTER */ "", 41618 /* IHB_INTERRUPT_REGISTER_TEST */ "", 41619 /* IHB_INVALID_DESTINATION */ "", 41620 /* IHB_IN_LIF_ORIENTATION_MAP */ "", 41621 /* IHB_IN_LIF_UC_RPF_MODEL_IS_STRICT */ "", 41622 /* IHB_IN_RIF_UC_RPF_MODEL_IS_STRICT */ "", 41623 /* IHB_IPV4_ACTION_PROFILES */ "", 41624 /* IHB_IPV6_ACTION_PROFILES_0 */ "", 41625 /* IHB_IPV6_ACTION_PROFILES_1 */ "", 41626 /* IHB_ISEM_CAM_ENTRIES_COUNTER */ "", 41627 /* IHB_ISEM_DEFRAG_CONFIGURATION_REGISTER */ "", 41628 /* IHB_ISEM_DIAGNOSTICS */ "", 41629 /* IHB_ISEM_DIAGNOSTICS_ACCESSED_MODE */ "", 41630 /* IHB_ISEM_DIAGNOSTICS_INDEX */ "", 41631 /* IHB_ISEM_DIAGNOSTICS_KEY */ "", 41632 /* IHB_ISEM_DIAGNOSTICS_LOOKUP_RESULT */ "", 41633 /* IHB_ISEM_DIAGNOSTICS_READ_RESULT */ "", 41634 /* IHB_ISEM_ENTRIES_COUNTER */ "", 41635 /* IHB_ISEM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 41636 /* IHB_ISEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 41637 /* IHB_ISEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 41638 /* IHB_ISEM_ERROR_TABLE_COHERENCY_COUNTER */ "", 41639 /* IHB_ISEM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 41640 /* IHB_ISEM_INTERRUPT_MASK_REGISTER_ONE */ "", 41641 /* IHB_ISEM_INTERRUPT_REGISTER_ONE */ "", 41642 /* IHB_ISEM_INTERRUPT_REGISTER_ONE_TEST */ "", 41643 /* IHB_ISEM_KEY_TABLE_ENTRY_LIMIT */ "", 41644 /* IHB_ISEM_KILL_RESET_SEQUENCE */ "", 41645 /* IHB_ISEM_LAST_LOOKUP_MASTER */ "", 41646 /* IHB_ISEM_LAST_LOOKUP_SLAVE */ "", 41647 /* IHB_ISEM_LOOKUP_ARBITER_LOOKUP_COUNTER_MASTER */ "", 41648 /* IHB_ISEM_LOOKUP_ARBITER_LOOKUP_COUNTER_SLAVE */ "", 41649 /* IHB_ISEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 41650 /* IHB_ISEM_MANAGEMENT_UNIT_FAILURE */ "", 41651 /* IHB_ISEM_REQUESTS_COUNTER */ "", 41652 /* IHB_ISEM_RESET_STATUS_REGISTER */ "", 41653 /* IHB_ISEM_WARNING_INSERTED_EXISTING_COUNTER */ "", 41654 /* IHB_KEY_D_XOR_MASKS */ "", 41655 /* IHB_LAG_LB_KEY_CFG */ "", 41656 /* IHB_LAST_ERROR_SEQUENCE_RX */ "", 41657 /* IHB_LBP_FIFOS_STATUS */ "", 41658 /* IHB_LBP_GENERAL_CONFIG_0 */ "", 41659 /* IHB_LBP_GENERAL_CONFIG_1 */ "", 41660 /* IHB_LBP_GENERAL_CONFIG_2 */ "", 41661 /* IHB_LBP_GENERAL_CONFIG_3 */ "", 41662 /* IHB_LBP_GENERAL_CONFIG_4 */ "", 41663 /* IHB_LBP_GENERAL_CONFIG_5 */ "", 41664 /* IHB_LBP_GENERAL_CONFIG_6 */ "", 41665 /* IHB_LB_INDEX_OFFSET */ "", 41666 /* IHB_LB_KEY_PARSER_LEAF_CONTEXT_PROFILE */ "", 41667 /* IHB_LEARNING_CFG */ "", 41668 /* IHB_LEARNS_COUNTER */ "", 41669 /* IHB_LOOKUPS_COUNTER */ "", 41670 /* IHB_LOOKUP_REPLY */ "", 41671 /* IHB_LOOKUP_REPLY_DATA */ "", 41672 /* IHB_LOOKUP_REPLY_OPCODE */ "", 41673 /* IHB_LOOKUP_REPLY_SEQ_NUM */ "", 41674 /* IHB_LPM_QUERY_CNT */ "", 41675 /* IHB_LPM_QUERY_CONFIGURATION */ "", 41676 /* IHB_LPM_QUERY_KEY */ "", 41677 /* IHB_LPM_QUERY_PAYLOAD */ "", 41678 /* IHB_LSR_ACTION_PROFILE */ "", 41679 /* IHB_LSR_ELSP_RANGE */ "", 41680 /* IHB_LSR_P2P_SERVICE_CFG */ "", 41681 /* IHB_MEF_L_2_CP_DROP_BITMAP */ "", 41682 /* IHB_MEF_L_2_CP_PEER_BITMAP */ "", 41683 /* IHB_MPLS_ACTION_PROFILES */ "", 41684 /* IHB_MPLS_EXP_MAP */ "", 41685 /* IHB_NIF_PHYSICAL_ERR_COUNTER */ "", 41686 /* IHB_OAM_BFD_MISCONFIG */ "", 41687 /* IHB_OAM_BFD_OVER_IP_CFG */ "", 41688 /* IHB_OAM_BFD_YOUR_DISCR_TO_LIF_CFG */ "", 41689 /* IHB_OAM_COUNTER_DISABLE_MAP */ "", 41690 /* IHB_OAM_COUNTER_INCREMENT_BITMAP */ "", 41691 /* IHB_OAM_COUNTER_IN_RANGE_CFG */ "", 41692 /* IHB_OAM_COUNTER_NOT_IN_RANGE_CFG */ "", 41693 /* IHB_OAM_COUNTER_RANGE */ "", 41694 /* IHB_OAM_DEFAULT_ACC_MEP_PROFILES */ "", 41695 /* IHB_OAM_DEFAULT_COUNTERS */ "", 41696 /* IHB_OAM_DEFAULT_EGRESS_BITMAPS */ "", 41697 /* IHB_OAM_ETHERNET_CFG */ "", 41698 /* IHB_OAM_IDENTIFICATION_ENABLE */ "", 41699 /* IHB_OAM_IN_LIF_PROFILE_MAP */ "", 41700 /* IHB_OAM_MEP_BITMAP */ "", 41701 /* IHB_OAM_MEP_PASSIVE_ACTIVE_ENABLE */ "", 41702 /* IHB_OAM_MIP_BITMAP */ "", 41703 /* IHB_OAM_PACKET_INJECTED_BITMAP */ "", 41704 /* IHB_OAM_SUB_TYPE_MAP */ "", 41705 /* IHB_OEMA_CAM_ENTRIES_COUNTER */ "", 41706 /* IHB_OEMA_DIAGNOSTICS */ "", 41707 /* IHB_OEMA_DIAGNOSTICS_ACCESSED_MODE */ "", 41708 /* IHB_OEMA_DIAGNOSTICS_INDEX */ "", 41709 /* IHB_OEMA_DIAGNOSTICS_KEY */ "", 41710 /* IHB_OEMA_DIAGNOSTICS_LOOKUP_RESULT */ "", 41711 /* IHB_OEMA_DIAGNOSTICS_READ_RESULT */ "", 41712 /* IHB_OEMA_ENTRIES_COUNTER */ "", 41713 /* IHB_OEMA_ERROR_CAM_TABLE_FULL_COUNTER */ "", 41714 /* IHB_OEMA_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 41715 /* IHB_OEMA_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 41716 /* IHB_OEMA_ERROR_TABLE_COHERENCY_COUNTER */ "", 41717 /* IHB_OEMA_GENERAL_EM_CONFIGURATION_REGISTER */ "", 41718 /* IHB_OEMA_INTERRUPT_MASK_REGISTER_ONE */ "", 41719 /* IHB_OEMA_INTERRUPT_REGISTER_ONE */ "", 41720 /* IHB_OEMA_INTERRUPT_REGISTER_ONE_TEST */ "", 41721 /* IHB_OEMA_KEY_TABLE_ENTRY_LIMIT */ "", 41722 /* IHB_OEMA_LAST_LOOKUP */ "", 41723 /* IHB_OEMA_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 41724 /* IHB_OEMA_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 41725 /* IHB_OEMA_MANAGEMENT_UNIT_FAILURE */ "", 41726 /* IHB_OEMA_REQUESTS_COUNTER */ "", 41727 /* IHB_OEMA_RESET_STATUS_REGISTER */ "", 41728 /* IHB_OEMA_WARNING_INSERTED_EXISTING_COUNTER */ "", 41729 /* IHB_OEMB_CAM_ENTRIES_COUNTER */ "", 41730 /* IHB_OEMB_DIAGNOSTICS */ "", 41731 /* IHB_OEMB_DIAGNOSTICS_ACCESSED_MODE */ "", 41732 /* IHB_OEMB_DIAGNOSTICS_INDEX */ "", 41733 /* IHB_OEMB_DIAGNOSTICS_KEY */ "", 41734 /* IHB_OEMB_DIAGNOSTICS_LOOKUP_RESULT */ "", 41735 /* IHB_OEMB_DIAGNOSTICS_READ_RESULT */ "", 41736 /* IHB_OEMB_ENTRIES_COUNTER */ "", 41737 /* IHB_OEMB_ERROR_CAM_TABLE_FULL_COUNTER */ "", 41738 /* IHB_OEMB_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 41739 /* IHB_OEMB_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 41740 /* IHB_OEMB_ERROR_TABLE_COHERENCY_COUNTER */ "", 41741 /* IHB_OEMB_GENERAL_EM_CONFIGURATION_REGISTER */ "", 41742 /* IHB_OEMB_INTERRUPT_MASK_REGISTER_ONE */ "", 41743 /* IHB_OEMB_INTERRUPT_REGISTER_ONE */ "", 41744 /* IHB_OEMB_INTERRUPT_REGISTER_ONE_TEST */ "", 41745 /* IHB_OEMB_KEY_TABLE_ENTRY_LIMIT */ "", 41746 /* IHB_OEMB_LAST_LOOKUP */ "", 41747 /* IHB_OEMB_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 41748 /* IHB_OEMB_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 41749 /* IHB_OEMB_MANAGEMENT_UNIT_FAILURE */ "", 41750 /* IHB_OEMB_REQUESTS_COUNTER */ "", 41751 /* IHB_OEMB_RESET_STATUS_REGISTER */ "", 41752 /* IHB_OEMB_WARNING_INSERTED_EXISTING_COUNTER */ "", 41753 /* IHB_OUT_LIF_RANGE */ "", 41754 /* IHB_OUT_RIF_RANGE */ "", 41755 /* IHB_PACKET_HEADER_SIZE_RANGE */ "", 41756 /* IHB_PACKET_SIZE */ "", 41757 /* IHB_PARITY_ERR_CNT */ "", 41758 /* IHB_PAR_ERR_INITIATE */ "", 41759 /* IHB_PAR_ERR_MEM_MASK */ "", 41760 /* IHB_PASS_2_INITIAL_KEY */ "", 41761 /* IHB_PASS_2_PROGRAM_SELECTION_PROFILE */ "", 41762 /* IHB_PCMI_0 */ "", 41763 /* IHB_PCMI_1 */ "", 41764 /* IHB_PCMI_2 */ "", 41765 /* IHB_PCMI_3 */ "", 41766 /* IHB_PCMI_4 */ "", 41767 /* IHB_PCMI_0_S */ "", 41768 /* IHB_PCMI_0_T */ "", 41769 /* IHB_PCMI_1_S */ "", 41770 /* IHB_PCMI_1_T */ "", 41771 /* IHB_PCMI_2_S */ "", 41772 /* IHB_PCMI_2_T */ "", 41773 /* IHB_PCMI_3_S */ "", 41774 /* IHB_PCMI_3_T */ "", 41775 /* IHB_PCMI_4_S */ "", 41776 /* IHB_PCMI_4_T */ "", 41777 /* IHB_PETRAB_EEI_POP_COMMAND */ "", 41778 /* IHB_PETRAB_PPH_EEP_SOURCE */ "", 41779 /* IHB_PETRA_OUTLIF_MSB_MAPPED */ "", 41780 /* IHB_PHY_CHANNEL_CFGS */ "", 41781 /* IHB_PMF_FIFOS_SKIP_ENTRY */ "", 41782 /* IHB_PMF_GENERAL */ "", 41783 /* IHB_PMF_PFC_ACL_MAPPING */ "", 41784 /* IHB_PMF_PFC_IS_ETH */ "", 41785 /* IHB_PMF_PFC_PS_MAPPING */ "", 41786 /* IHB_PPH_FHEI_EEI_SIZE */ "", 41787 /* IHB_PPH_FHEI_FWD_SIZE */ "", 41788 /* IHB_PPH_FHEI_IVE_SIZE */ "", 41789 /* IHB_PPH_VSI_SOURCE */ "", 41790 /* IHB_PROTOCOL_TRAPS_PROGRAM_SELECT */ "", 41791 /* IHB_RECEIVE_FIFO_STATUS */ "", 41792 /* IHB_REG_0085 */ "", 41793 /* IHB_REG_0090 */ "", 41794 /* IHB_REG_0091 */ "", 41795 /* IHB_REG_0092 */ "", 41796 /* IHB_REG_0093 */ "", 41797 /* IHB_REG_0100 */ "", 41798 /* IHB_REG_0281 */ "", 41799 /* IHB_REG_0304 */ "", 41800 /* IHB_REG_0305 */ "", 41801 /* IHB_REG_0306 */ "", 41802 /* IHB_REG_0307 */ "", 41803 /* IHB_REG_0308 */ "", 41804 /* IHB_REG_0309 */ "", 41805 /* IHB_REG_008A */ "", 41806 /* IHB_REG_008B */ "", 41807 /* IHB_REG_008C */ "", 41808 /* IHB_REG_009A_1 */ "", 41809 /* IHB_REG_009A_2 */ "", 41810 /* IHB_REG_00A4 */ "", 41811 /* IHB_REG_00A4_1 */ "", 41812 /* IHB_REG_00A4_2 */ "", 41813 /* IHB_REG_00AA */ "", 41814 /* IHB_REG_00AE */ "", 41815 /* IHB_REG_00AF */ "", 41816 /* IHB_REG_00B4 */ "", 41817 /* IHB_REG_00B5 */ "", 41818 /* IHB_REG_00B6 */ "", 41819 /* IHB_REG_00B7 */ "", 41820 /* IHB_REG_00E0 */ "", 41821 /* IHB_REG_00E1 */ "", 41822 /* IHB_REG_00FE */ "", 41823 /* IHB_REG_00FF */ "", 41824 /* IHB_REG_028D */ "", 41825 /* IHB_REG_02C1 */ "", 41826 /* IHB_REG_02CD */ "", 41827 /* IHB_REG_02E0 */ "", 41828 /* IHB_REG_030A */ "", 41829 /* IHB_RESERVED_MIRROR_ADDR */ "", 41830 /* IHB_RESERVED_MTCD */ "", 41831 /* IHB_RESERVED_MTCP */ "", 41832 /* IHB_RESERVED_PCMI_0 */ "", 41833 /* IHB_RESERVED_PCMI_1 */ "", 41834 /* IHB_RESERVED_PCMI_2 */ "", 41835 /* IHB_RESERVED_PCMI_3 */ "", 41836 /* IHB_RESERVED_PCMI_4 */ "", 41837 /* IHB_RESERVED_PCMI_0_S */ "", 41838 /* IHB_RESERVED_PCMI_0_T */ "", 41839 /* IHB_RESERVED_PCMI_1_S */ "", 41840 /* IHB_RESERVED_PCMI_1_T */ "", 41841 /* IHB_RESERVED_PCMI_2_S */ "", 41842 /* IHB_RESERVED_PCMI_2_T */ "", 41843 /* IHB_RESERVED_PCMI_3_S */ "", 41844 /* IHB_RESERVED_PCMI_3_T */ "", 41845 /* IHB_RESERVED_PCMI_4_S */ "", 41846 /* IHB_RESERVED_PCMI_4_T */ "", 41847 /* IHB_RESERVED_SPARE_0 */ "", 41848 /* IHB_RESERVED_SPARE_1 */ "", 41849 /* IHB_RESERVED_SPARE_2 */ "", 41850 /* IHB_RESERVED_SPARE_3 */ "", 41851 /* IHB_RPF_CFG */ "", 41852 /* IHB_SA_LOOKUP_RESULT_MAPPING */ "", 41853 /* IHB_SBUS_BROADCAST_ID */ "", 41854 /* IHB_SBUS_LAST_IN_CHAIN */ "", 41855 /* IHB_SEQUENCE_EXPECTED */ "", 41856 /* IHB_SEQUENCE_TX */ "", 41857 /* IHB_SPR_CFGS */ "", 41858 /* IHB_SPR_DLY_CFGS */ "", 41859 /* IHB_TCAM_ACCESS_COUNTER */ "", 41860 /* IHB_TCAM_ACCESS_COUNTER_SELECTOR */ "", 41861 /* IHB_TCAM_BANK_BLOCK_OWNER */ "", 41862 /* IHB_TCAM_INTERFACE_ACCESS_BITMAP */ "", 41863 /* IHB_TCAM_MANAGER_0 */ "", 41864 /* IHB_TCAM_MANAGER_1 */ "", 41865 /* IHB_TCAM_MATCH_BITMAP */ "", 41866 /* IHB_TCAM_PROTECTION_ERROR */ "", 41867 /* IHB_TCAM_QUERY_FAILURE */ "", 41868 /* IHB_TCAM_RESET_BLOCK_BITMAP */ "", 41869 /* IHB_TCP_ACTION_PROFILES */ "", 41870 /* IHB_TOD_LAST_VALUE */ "", 41871 /* IHB_TRANSMIT_CFGS */ "", 41872 /* IHB_TRANSMIT_FIFO_STATUS */ "", 41873 /* IHB_TRAP_IF_ACCESSED */ "", 41874 /* IHB_TX_APP_PREFIX */ "", 41875 /* IHB_UDP_ACTION_PROFILES */ "", 41876 /* IHB_VID_VALID */ "", 41877 /* IHB_XOR_MASKS */ "", 41878 /* IHG_LOOKUP */ "", 41879 /* IHOST_A9CPU0_AUTHSTATUS */ "", 41880 /* IHOST_A9CPU0_BCR0 */ "", 41881 /* IHOST_A9CPU0_BCR1 */ "", 41882 /* IHOST_A9CPU0_BCR2 */ "", 41883 /* IHOST_A9CPU0_BCR3 */ "", 41884 /* IHOST_A9CPU0_BCR4 */ "", 41885 /* IHOST_A9CPU0_BCR5 */ "", 41886 /* IHOST_A9CPU0_BVR0 */ "", 41887 /* IHOST_A9CPU0_BVR1 */ "", 41888 /* IHOST_A9CPU0_BVR2 */ "", 41889 /* IHOST_A9CPU0_BVR3 */ "", 41890 /* IHOST_A9CPU0_BVR4 */ "", 41891 /* IHOST_A9CPU0_BVR5 */ "", 41892 /* IHOST_A9CPU0_CLAIMCLR */ "", 41893 /* IHOST_A9CPU0_CLAIMSET */ "", 41894 /* IHOST_A9CPU0_COMPID0 */ "", 41895 /* IHOST_A9CPU0_COMPID1 */ "", 41896 /* IHOST_A9CPU0_COMPID2 */ "", 41897 /* IHOST_A9CPU0_COMPID3 */ "", 41898 /* IHOST_A9CPU0_DEVTYPE */ "", 41899 /* IHOST_A9CPU0_DIDR */ "", 41900 /* IHOST_A9CPU0_DRCR */ "", 41901 /* IHOST_A9CPU0_DSCR */ "", 41902 /* IHOST_A9CPU0_DTRRX */ "", 41903 /* IHOST_A9CPU0_DTRTX */ "", 41904 /* IHOST_A9CPU0_ICTRL */ "", 41905 /* IHOST_A9CPU0_LOCKACCESS */ "", 41906 /* IHOST_A9CPU0_LOCKSTATUS */ "", 41907 /* IHOST_A9CPU0_PCSR */ "", 41908 /* IHOST_A9CPU0_PERID0 */ "", 41909 /* IHOST_A9CPU0_PERID1 */ "", 41910 /* IHOST_A9CPU0_PERID2 */ "", 41911 /* IHOST_A9CPU0_PERID3 */ "", 41912 /* IHOST_A9CPU0_PERID4 */ "", 41913 /* IHOST_A9CPU0_PRCR */ "", 41914 /* IHOST_A9CPU0_PRSR */ "", 41915 /* IHOST_A9CPU0_VCR */ "", 41916 /* IHOST_A9CPU0_WCR0 */ "", 41917 /* IHOST_A9CPU0_WCR1 */ "", 41918 /* IHOST_A9CPU0_WCR2 */ "", 41919 /* IHOST_A9CPU0_WCR3 */ "", 41920 /* IHOST_A9CPU0_WCR4 */ "", 41921 /* IHOST_A9CPU0_WCR5 */ "", 41922 /* IHOST_A9CPU0_WFAR */ "", 41923 /* IHOST_A9CPU0_WVR0 */ "", 41924 /* IHOST_A9CPU0_WVR1 */ "", 41925 /* IHOST_A9CPU0_WVR2 */ "", 41926 /* IHOST_A9CPU0_WVR3 */ "", 41927 /* IHOST_A9CPU0_WVR4 */ "", 41928 /* IHOST_A9CPU0_WVR5 */ "", 41929 /* IHOST_A9CPU1_AUTHSTATUS */ "", 41930 /* IHOST_A9CPU1_BCR0 */ "", 41931 /* IHOST_A9CPU1_BCR1 */ "", 41932 /* IHOST_A9CPU1_BCR2 */ "", 41933 /* IHOST_A9CPU1_BCR3 */ "", 41934 /* IHOST_A9CPU1_BCR4 */ "", 41935 /* IHOST_A9CPU1_BCR5 */ "", 41936 /* IHOST_A9CPU1_BVR0 */ "", 41937 /* IHOST_A9CPU1_BVR1 */ "", 41938 /* IHOST_A9CPU1_BVR2 */ "", 41939 /* IHOST_A9CPU1_BVR3 */ "", 41940 /* IHOST_A9CPU1_BVR4 */ "", 41941 /* IHOST_A9CPU1_BVR5 */ "", 41942 /* IHOST_A9CPU1_CLAIMCLR */ "", 41943 /* IHOST_A9CPU1_CLAIMSET */ "", 41944 /* IHOST_A9CPU1_COMPID0 */ "", 41945 /* IHOST_A9CPU1_COMPID1 */ "", 41946 /* IHOST_A9CPU1_COMPID2 */ "", 41947 /* IHOST_A9CPU1_COMPID3 */ "", 41948 /* IHOST_A9CPU1_DEVTYPE */ "", 41949 /* IHOST_A9CPU1_DIDR */ "", 41950 /* IHOST_A9CPU1_DRCR */ "", 41951 /* IHOST_A9CPU1_DSCR */ "", 41952 /* IHOST_A9CPU1_DTRRX */ "", 41953 /* IHOST_A9CPU1_DTRTX */ "", 41954 /* IHOST_A9CPU1_ICTRL */ "", 41955 /* IHOST_A9CPU1_LOCKACCESS */ "", 41956 /* IHOST_A9CPU1_LOCKSTATUS */ "", 41957 /* IHOST_A9CPU1_PCSR */ "", 41958 /* IHOST_A9CPU1_PERID0 */ "", 41959 /* IHOST_A9CPU1_PERID1 */ "", 41960 /* IHOST_A9CPU1_PERID2 */ "", 41961 /* IHOST_A9CPU1_PERID3 */ "", 41962 /* IHOST_A9CPU1_PERID4 */ "", 41963 /* IHOST_A9CPU1_PRCR */ "", 41964 /* IHOST_A9CPU1_PRSR */ "", 41965 /* IHOST_A9CPU1_VCR */ "", 41966 /* IHOST_A9CPU1_WCR0 */ "", 41967 /* IHOST_A9CPU1_WCR1 */ "", 41968 /* IHOST_A9CPU1_WCR2 */ "", 41969 /* IHOST_A9CPU1_WCR3 */ "", 41970 /* IHOST_A9CPU1_WCR4 */ "", 41971 /* IHOST_A9CPU1_WCR5 */ "", 41972 /* IHOST_A9CPU1_WFAR */ "", 41973 /* IHOST_A9CPU1_WVR0 */ "", 41974 /* IHOST_A9CPU1_WVR1 */ "", 41975 /* IHOST_A9CPU1_WVR2 */ "", 41976 /* IHOST_A9CPU1_WVR3 */ "", 41977 /* IHOST_A9CPU1_WVR4 */ "", 41978 /* IHOST_A9CPU1_WVR5 */ "", 41979 /* IHOST_A9CTI0_ASICCTL */ "", 41980 /* IHOST_A9CTI0_AUTHSTATUS */ "", 41981 /* IHOST_A9CTI0_CLAIMCLR */ "", 41982 /* IHOST_A9CTI0_CLAIMSET */ "", 41983 /* IHOST_A9CTI0_COMPID0 */ "", 41984 /* IHOST_A9CTI0_COMPID1 */ "", 41985 /* IHOST_A9CTI0_COMPID2 */ "", 41986 /* IHOST_A9CTI0_COMPID3 */ "", 41987 /* IHOST_A9CTI0_CTIAPPCLEAR */ "", 41988 /* IHOST_A9CTI0_CTIAPPPULSE */ "", 41989 /* IHOST_A9CTI0_CTIAPPSET */ "", 41990 /* IHOST_A9CTI0_CTICHGATE */ "", 41991 /* IHOST_A9CTI0_CTICHINSTATUS */ "", 41992 /* IHOST_A9CTI0_CTICHOUTSTATUS */ "", 41993 /* IHOST_A9CTI0_CTICONTROL */ "", 41994 /* IHOST_A9CTI0_CTIINEN0 */ "", 41995 /* IHOST_A9CTI0_CTIINEN1 */ "", 41996 /* IHOST_A9CTI0_CTIINEN2 */ "", 41997 /* IHOST_A9CTI0_CTIINEN3 */ "", 41998 /* IHOST_A9CTI0_CTIINEN4 */ "", 41999 /* IHOST_A9CTI0_CTIINEN5 */ "", 42000 /* IHOST_A9CTI0_CTIINEN6 */ "", 42001 /* IHOST_A9CTI0_CTIINEN7 */ "", 42002 /* IHOST_A9CTI0_CTIINTACK */ "", 42003 /* IHOST_A9CTI0_CTIOUTEN0 */ "", 42004 /* IHOST_A9CTI0_CTIOUTEN1 */ "", 42005 /* IHOST_A9CTI0_CTIOUTEN2 */ "", 42006 /* IHOST_A9CTI0_CTIOUTEN3 */ "", 42007 /* IHOST_A9CTI0_CTIOUTEN4 */ "", 42008 /* IHOST_A9CTI0_CTIOUTEN5 */ "", 42009 /* IHOST_A9CTI0_CTIOUTEN6 */ "", 42010 /* IHOST_A9CTI0_CTIOUTEN7 */ "", 42011 /* IHOST_A9CTI0_CTITRIGINSTATUS */ "", 42012 /* IHOST_A9CTI0_CTITRIGOUTSTATUS */ "", 42013 /* IHOST_A9CTI0_DEVID */ "", 42014 /* IHOST_A9CTI0_DEVTYPE */ "", 42015 /* IHOST_A9CTI0_ICTRL */ "", 42016 /* IHOST_A9CTI0_ITCHIN */ "", 42017 /* IHOST_A9CTI0_ITCHINACK */ "", 42018 /* IHOST_A9CTI0_ITCHOUT */ "", 42019 /* IHOST_A9CTI0_ITCHOUTACK */ "", 42020 /* IHOST_A9CTI0_ITTRIGIN */ "", 42021 /* IHOST_A9CTI0_ITTRIGINACK */ "", 42022 /* IHOST_A9CTI0_ITTRIGOUT */ "", 42023 /* IHOST_A9CTI0_ITTRIGOUTACK */ "", 42024 /* IHOST_A9CTI0_LOCKACCESS */ "", 42025 /* IHOST_A9CTI0_LOCKSTATUS */ "", 42026 /* IHOST_A9CTI0_PERID0 */ "", 42027 /* IHOST_A9CTI0_PERID1 */ "", 42028 /* IHOST_A9CTI0_PERID2 */ "", 42029 /* IHOST_A9CTI0_PERID3 */ "", 42030 /* IHOST_A9CTI0_PERID4 */ "", 42031 /* IHOST_A9CTI1_ASICCTL */ "", 42032 /* IHOST_A9CTI1_AUTHSTATUS */ "", 42033 /* IHOST_A9CTI1_CLAIMCLR */ "", 42034 /* IHOST_A9CTI1_CLAIMSET */ "", 42035 /* IHOST_A9CTI1_COMPID0 */ "", 42036 /* IHOST_A9CTI1_COMPID1 */ "", 42037 /* IHOST_A9CTI1_COMPID2 */ "", 42038 /* IHOST_A9CTI1_COMPID3 */ "", 42039 /* IHOST_A9CTI1_CTIAPPCLEAR */ "", 42040 /* IHOST_A9CTI1_CTIAPPPULSE */ "", 42041 /* IHOST_A9CTI1_CTIAPPSET */ "", 42042 /* IHOST_A9CTI1_CTICHGATE */ "", 42043 /* IHOST_A9CTI1_CTICHINSTATUS */ "", 42044 /* IHOST_A9CTI1_CTICHOUTSTATUS */ "", 42045 /* IHOST_A9CTI1_CTICONTROL */ "", 42046 /* IHOST_A9CTI1_CTIINEN0 */ "", 42047 /* IHOST_A9CTI1_CTIINEN1 */ "", 42048 /* IHOST_A9CTI1_CTIINEN2 */ "", 42049 /* IHOST_A9CTI1_CTIINEN3 */ "", 42050 /* IHOST_A9CTI1_CTIINEN4 */ "", 42051 /* IHOST_A9CTI1_CTIINEN5 */ "", 42052 /* IHOST_A9CTI1_CTIINEN6 */ "", 42053 /* IHOST_A9CTI1_CTIINEN7 */ "", 42054 /* IHOST_A9CTI1_CTIINTACK */ "", 42055 /* IHOST_A9CTI1_CTIOUTEN0 */ "", 42056 /* IHOST_A9CTI1_CTIOUTEN1 */ "", 42057 /* IHOST_A9CTI1_CTIOUTEN2 */ "", 42058 /* IHOST_A9CTI1_CTIOUTEN3 */ "", 42059 /* IHOST_A9CTI1_CTIOUTEN4 */ "", 42060 /* IHOST_A9CTI1_CTIOUTEN5 */ "", 42061 /* IHOST_A9CTI1_CTIOUTEN6 */ "", 42062 /* IHOST_A9CTI1_CTIOUTEN7 */ "", 42063 /* IHOST_A9CTI1_CTITRIGINSTATUS */ "", 42064 /* IHOST_A9CTI1_CTITRIGOUTSTATUS */ "", 42065 /* IHOST_A9CTI1_DEVID */ "", 42066 /* IHOST_A9CTI1_DEVTYPE */ "", 42067 /* IHOST_A9CTI1_ICTRL */ "", 42068 /* IHOST_A9CTI1_ITCHIN */ "", 42069 /* IHOST_A9CTI1_ITCHINACK */ "", 42070 /* IHOST_A9CTI1_ITCHOUT */ "", 42071 /* IHOST_A9CTI1_ITCHOUTACK */ "", 42072 /* IHOST_A9CTI1_ITTRIGIN */ "", 42073 /* IHOST_A9CTI1_ITTRIGINACK */ "", 42074 /* IHOST_A9CTI1_ITTRIGOUT */ "", 42075 /* IHOST_A9CTI1_ITTRIGOUTACK */ "", 42076 /* IHOST_A9CTI1_LOCKACCESS */ "", 42077 /* IHOST_A9CTI1_LOCKSTATUS */ "", 42078 /* IHOST_A9CTI1_PERID0 */ "", 42079 /* IHOST_A9CTI1_PERID1 */ "", 42080 /* IHOST_A9CTI1_PERID2 */ "", 42081 /* IHOST_A9CTI1_PERID3 */ "", 42082 /* IHOST_A9CTI1_PERID4 */ "", 42083 /* IHOST_A9PMU0_PMCCNTR */ "", 42084 /* IHOST_A9PMU0_PMCNTENCLR */ "", 42085 /* IHOST_A9PMU0_PMCNTENSET */ "", 42086 /* IHOST_A9PMU0_PMCR */ "", 42087 /* IHOST_A9PMU0_PMEVCNTR0 */ "", 42088 /* IHOST_A9PMU0_PMEVCNTR1 */ "", 42089 /* IHOST_A9PMU0_PMEVCNTR2 */ "", 42090 /* IHOST_A9PMU0_PMEVCNTR3 */ "", 42091 /* IHOST_A9PMU0_PMEVCNTR4 */ "", 42092 /* IHOST_A9PMU0_PMEVCNTR5 */ "", 42093 /* IHOST_A9PMU0_PMINTENCLR */ "", 42094 /* IHOST_A9PMU0_PMINTENSET */ "", 42095 /* IHOST_A9PMU0_PMOVSR */ "", 42096 /* IHOST_A9PMU0_PMSWINC */ "", 42097 /* IHOST_A9PMU0_PMUSERENR */ "", 42098 /* IHOST_A9PMU0_PMXEVTYPER0 */ "", 42099 /* IHOST_A9PMU0_PMXEVTYPER1 */ "", 42100 /* IHOST_A9PMU0_PMXEVTYPER2 */ "", 42101 /* IHOST_A9PMU0_PMXEVTYPER3 */ "", 42102 /* IHOST_A9PMU0_PMXEVTYPER4 */ "", 42103 /* IHOST_A9PMU0_PMXEVTYPER5 */ "", 42104 /* IHOST_A9PMU1_PMCCNTR */ "", 42105 /* IHOST_A9PMU1_PMCNTENCLR */ "", 42106 /* IHOST_A9PMU1_PMCNTENSET */ "", 42107 /* IHOST_A9PMU1_PMCR */ "", 42108 /* IHOST_A9PMU1_PMEVCNTR0 */ "", 42109 /* IHOST_A9PMU1_PMEVCNTR1 */ "", 42110 /* IHOST_A9PMU1_PMEVCNTR2 */ "", 42111 /* IHOST_A9PMU1_PMEVCNTR3 */ "", 42112 /* IHOST_A9PMU1_PMEVCNTR4 */ "", 42113 /* IHOST_A9PMU1_PMEVCNTR5 */ "", 42114 /* IHOST_A9PMU1_PMINTENCLR */ "", 42115 /* IHOST_A9PMU1_PMINTENSET */ "", 42116 /* IHOST_A9PMU1_PMOVSR */ "", 42117 /* IHOST_A9PMU1_PMSWINC */ "", 42118 /* IHOST_A9PMU1_PMUSERENR */ "", 42119 /* IHOST_A9PMU1_PMXEVTYPER0 */ "", 42120 /* IHOST_A9PMU1_PMXEVTYPER1 */ "", 42121 /* IHOST_A9PMU1_PMXEVTYPER2 */ "", 42122 /* IHOST_A9PMU1_PMXEVTYPER3 */ "", 42123 /* IHOST_A9PMU1_PMXEVTYPER4 */ "", 42124 /* IHOST_A9PMU1_PMXEVTYPER5 */ "", 42125 /* IHOST_A9PTM0_COMPID0 */ "", 42126 /* IHOST_A9PTM0_COMPID1 */ "", 42127 /* IHOST_A9PTM0_COMPID2 */ "", 42128 /* IHOST_A9PTM0_COMPID3 */ "", 42129 /* IHOST_A9PTM0_ETMACTR1 */ "", 42130 /* IHOST_A9PTM0_ETMACTR2 */ "", 42131 /* IHOST_A9PTM0_ETMACTR3 */ "", 42132 /* IHOST_A9PTM0_ETMACTR4 */ "", 42133 /* IHOST_A9PTM0_ETMACTR5 */ "", 42134 /* IHOST_A9PTM0_ETMACTR6 */ "", 42135 /* IHOST_A9PTM0_ETMACTR7 */ "", 42136 /* IHOST_A9PTM0_ETMACTR8 */ "", 42137 /* IHOST_A9PTM0_ETMACVR1 */ "", 42138 /* IHOST_A9PTM0_ETMACVR2 */ "", 42139 /* IHOST_A9PTM0_ETMACVR3 */ "", 42140 /* IHOST_A9PTM0_ETMACVR4 */ "", 42141 /* IHOST_A9PTM0_ETMACVR5 */ "", 42142 /* IHOST_A9PTM0_ETMACVR6 */ "", 42143 /* IHOST_A9PTM0_ETMACVR7 */ "", 42144 /* IHOST_A9PTM0_ETMACVR8 */ "", 42145 /* IHOST_A9PTM0_ETMAUXCR */ "", 42146 /* IHOST_A9PTM0_ETMCCER */ "", 42147 /* IHOST_A9PTM0_ETMCCR */ "", 42148 /* IHOST_A9PTM0_ETMCIDCMR */ "", 42149 /* IHOST_A9PTM0_ETMCIDCVR1 */ "", 42150 /* IHOST_A9PTM0_ETMCNTENR1 */ "", 42151 /* IHOST_A9PTM0_ETMCNTENR2 */ "", 42152 /* IHOST_A9PTM0_ETMCNTRLDEVR1 */ "", 42153 /* IHOST_A9PTM0_ETMCNTRLDEVR2 */ "", 42154 /* IHOST_A9PTM0_ETMCNTRLDVR1 */ "", 42155 /* IHOST_A9PTM0_ETMCNTRLDVR2 */ "", 42156 /* IHOST_A9PTM0_ETMCNTVR1 */ "", 42157 /* IHOST_A9PTM0_ETMCNTVR2 */ "", 42158 /* IHOST_A9PTM0_ETMCR */ "", 42159 /* IHOST_A9PTM0_ETMEXTINSELR */ "", 42160 /* IHOST_A9PTM0_ETMEXTOUTEVR1 */ "", 42161 /* IHOST_A9PTM0_ETMEXTOUTEVR2 */ "", 42162 /* IHOST_A9PTM0_ETMIDR */ "", 42163 /* IHOST_A9PTM0_ETMPDSR */ "", 42164 /* IHOST_A9PTM0_ETMSCR */ "", 42165 /* IHOST_A9PTM0_ETMSQ12EVR */ "", 42166 /* IHOST_A9PTM0_ETMSQ13EVR */ "", 42167 /* IHOST_A9PTM0_ETMSQ21EVR */ "", 42168 /* IHOST_A9PTM0_ETMSQ23EVR */ "", 42169 /* IHOST_A9PTM0_ETMSQ31EVR */ "", 42170 /* IHOST_A9PTM0_ETMSQ32EVR */ "", 42171 /* IHOST_A9PTM0_ETMSQR */ "", 42172 /* IHOST_A9PTM0_ETMSR */ "", 42173 /* IHOST_A9PTM0_ETMSSCR */ "", 42174 /* IHOST_A9PTM0_ETMSYNCFR */ "", 42175 /* IHOST_A9PTM0_ETMTECR1 */ "", 42176 /* IHOST_A9PTM0_ETMTEEVR */ "", 42177 /* IHOST_A9PTM0_ETMTRACEIDR */ "", 42178 /* IHOST_A9PTM0_ETMTRIGGER */ "", 42179 /* IHOST_A9PTM0_ETMTSEVR */ "", 42180 /* IHOST_A9PTM0_ITATBCTR0 */ "", 42181 /* IHOST_A9PTM0_ITATBCTR1 */ "", 42182 /* IHOST_A9PTM0_ITATBCTR2 */ "", 42183 /* IHOST_A9PTM0_ITATBDATA0 */ "", 42184 /* IHOST_A9PTM0_ITCTRL */ "", 42185 /* IHOST_A9PTM0_ITMISCIN */ "", 42186 /* IHOST_A9PTM0_ITMISCOUT */ "", 42187 /* IHOST_A9PTM0_ITTRIGGER */ "", 42188 /* IHOST_A9PTM0_PERID0 */ "", 42189 /* IHOST_A9PTM0_PERID1 */ "", 42190 /* IHOST_A9PTM0_PERID2 */ "", 42191 /* IHOST_A9PTM0_PERID3 */ "", 42192 /* IHOST_A9PTM0_PERID4 */ "", 42193 /* IHOST_A9PTM1_COMPID0 */ "", 42194 /* IHOST_A9PTM1_COMPID1 */ "", 42195 /* IHOST_A9PTM1_COMPID2 */ "", 42196 /* IHOST_A9PTM1_COMPID3 */ "", 42197 /* IHOST_A9PTM1_ETMACTR1 */ "", 42198 /* IHOST_A9PTM1_ETMACTR2 */ "", 42199 /* IHOST_A9PTM1_ETMACTR3 */ "", 42200 /* IHOST_A9PTM1_ETMACTR4 */ "", 42201 /* IHOST_A9PTM1_ETMACTR5 */ "", 42202 /* IHOST_A9PTM1_ETMACTR6 */ "", 42203 /* IHOST_A9PTM1_ETMACTR7 */ "", 42204 /* IHOST_A9PTM1_ETMACTR8 */ "", 42205 /* IHOST_A9PTM1_ETMACVR1 */ "", 42206 /* IHOST_A9PTM1_ETMACVR2 */ "", 42207 /* IHOST_A9PTM1_ETMACVR3 */ "", 42208 /* IHOST_A9PTM1_ETMACVR4 */ "", 42209 /* IHOST_A9PTM1_ETMACVR5 */ "", 42210 /* IHOST_A9PTM1_ETMACVR6 */ "", 42211 /* IHOST_A9PTM1_ETMACVR7 */ "", 42212 /* IHOST_A9PTM1_ETMACVR8 */ "", 42213 /* IHOST_A9PTM1_ETMAUXCR */ "", 42214 /* IHOST_A9PTM1_ETMCCER */ "", 42215 /* IHOST_A9PTM1_ETMCCR */ "", 42216 /* IHOST_A9PTM1_ETMCIDCMR */ "", 42217 /* IHOST_A9PTM1_ETMCIDCVR1 */ "", 42218 /* IHOST_A9PTM1_ETMCNTENR1 */ "", 42219 /* IHOST_A9PTM1_ETMCNTENR2 */ "", 42220 /* IHOST_A9PTM1_ETMCNTRLDEVR1 */ "", 42221 /* IHOST_A9PTM1_ETMCNTRLDEVR2 */ "", 42222 /* IHOST_A9PTM1_ETMCNTRLDVR1 */ "", 42223 /* IHOST_A9PTM1_ETMCNTRLDVR2 */ "", 42224 /* IHOST_A9PTM1_ETMCNTVR1 */ "", 42225 /* IHOST_A9PTM1_ETMCNTVR2 */ "", 42226 /* IHOST_A9PTM1_ETMCR */ "", 42227 /* IHOST_A9PTM1_ETMEXTINSELR */ "", 42228 /* IHOST_A9PTM1_ETMEXTOUTEVR1 */ "", 42229 /* IHOST_A9PTM1_ETMEXTOUTEVR2 */ "", 42230 /* IHOST_A9PTM1_ETMIDR */ "", 42231 /* IHOST_A9PTM1_ETMPDSR */ "", 42232 /* IHOST_A9PTM1_ETMSCR */ "", 42233 /* IHOST_A9PTM1_ETMSQ12EVR */ "", 42234 /* IHOST_A9PTM1_ETMSQ13EVR */ "", 42235 /* IHOST_A9PTM1_ETMSQ21EVR */ "", 42236 /* IHOST_A9PTM1_ETMSQ23EVR */ "", 42237 /* IHOST_A9PTM1_ETMSQ31EVR */ "", 42238 /* IHOST_A9PTM1_ETMSQ32EVR */ "", 42239 /* IHOST_A9PTM1_ETMSQR */ "", 42240 /* IHOST_A9PTM1_ETMSR */ "", 42241 /* IHOST_A9PTM1_ETMSSCR */ "", 42242 /* IHOST_A9PTM1_ETMSYNCFR */ "", 42243 /* IHOST_A9PTM1_ETMTECR1 */ "", 42244 /* IHOST_A9PTM1_ETMTEEVR */ "", 42245 /* IHOST_A9PTM1_ETMTRACEIDR */ "", 42246 /* IHOST_A9PTM1_ETMTRIGGER */ "", 42247 /* IHOST_A9PTM1_ETMTSEVR */ "", 42248 /* IHOST_A9PTM1_ITATBCTR0 */ "", 42249 /* IHOST_A9PTM1_ITATBCTR1 */ "", 42250 /* IHOST_A9PTM1_ITATBCTR2 */ "", 42251 /* IHOST_A9PTM1_ITATBDATA0 */ "", 42252 /* IHOST_A9PTM1_ITCTRL */ "", 42253 /* IHOST_A9PTM1_ITMISCIN */ "", 42254 /* IHOST_A9PTM1_ITMISCOUT */ "", 42255 /* IHOST_A9PTM1_ITTRIGGER */ "", 42256 /* IHOST_A9PTM1_PERID0 */ "", 42257 /* IHOST_A9PTM1_PERID1 */ "", 42258 /* IHOST_A9PTM1_PERID2 */ "", 42259 /* IHOST_A9PTM1_PERID3 */ "", 42260 /* IHOST_A9PTM1_PERID4 */ "", 42261 /* IHOST_ARM_FUNNEL_AUTHSTATUS */ "", 42262 /* IHOST_ARM_FUNNEL_CLAIM_TAG_CLEAR */ "", 42263 /* IHOST_ARM_FUNNEL_CLAIM_TAG_SET */ "", 42264 /* IHOST_ARM_FUNNEL_COMPONENT_ID0 */ "", 42265 /* IHOST_ARM_FUNNEL_COMPONENT_ID1 */ "", 42266 /* IHOST_ARM_FUNNEL_COMPONENT_ID2 */ "", 42267 /* IHOST_ARM_FUNNEL_COMPONENT_ID3 */ "", 42268 /* IHOST_ARM_FUNNEL_DEVICE_ID */ "", 42269 /* IHOST_ARM_FUNNEL_DEVICE_TYPE_IDENTIFIER */ "", 42270 /* IHOST_ARM_FUNNEL_FUNNEL_CONTROL */ "", 42271 /* IHOST_ARM_FUNNEL_ITATBCTR0 */ "", 42272 /* IHOST_ARM_FUNNEL_ITATBCTR1 */ "", 42273 /* IHOST_ARM_FUNNEL_ITATBCTR2 */ "", 42274 /* IHOST_ARM_FUNNEL_ITATBDATA0 */ "", 42275 /* IHOST_ARM_FUNNEL_ITCTRL */ "", 42276 /* IHOST_ARM_FUNNEL_LOCKACCESS */ "", 42277 /* IHOST_ARM_FUNNEL_LOCKSTATUS */ "", 42278 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID0 */ "", 42279 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID1 */ "", 42280 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID2 */ "", 42281 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID3 */ "", 42282 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID4 */ "", 42283 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID5 */ "", 42284 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID6 */ "", 42285 /* IHOST_ARM_FUNNEL_PERIPHERAL_ID7 */ "", 42286 /* IHOST_ARM_FUNNEL_PRIORITY_CONTROL */ "", 42287 /* IHOST_AXITRACE_ACP_ATM_ADDRHIGH_0 */ "", 42288 /* IHOST_AXITRACE_ACP_ATM_ADDRHIGH_1 */ "", 42289 /* IHOST_AXITRACE_ACP_ATM_ADDRLOW_0 */ "", 42290 /* IHOST_AXITRACE_ACP_ATM_ADDRLOW_1 */ "", 42291 /* IHOST_AXITRACE_ACP_ATM_ARBUSY */ "", 42292 /* IHOST_AXITRACE_ACP_ATM_ARCYCLES */ "", 42293 /* IHOST_AXITRACE_ACP_ATM_AWBUSY */ "", 42294 /* IHOST_AXITRACE_ACP_ATM_AWCYCLES */ "", 42295 /* IHOST_AXITRACE_ACP_ATM_BBUSY */ "", 42296 /* IHOST_AXITRACE_ACP_ATM_BCYCLES */ "", 42297 /* IHOST_AXITRACE_ACP_ATM_CMD */ "", 42298 /* IHOST_AXITRACE_ACP_ATM_CONFIG */ "", 42299 /* IHOST_AXITRACE_ACP_ATM_FILTER_0 */ "", 42300 /* IHOST_AXITRACE_ACP_ATM_FILTER_1 */ "", 42301 /* IHOST_AXITRACE_ACP_ATM_OUTIDS */ "", 42302 /* IHOST_AXITRACE_ACP_ATM_RBUSY */ "", 42303 /* IHOST_AXITRACE_ACP_ATM_RCYCLES */ "", 42304 /* IHOST_AXITRACE_ACP_ATM_RDBEATS */ "", 42305 /* IHOST_AXITRACE_ACP_ATM_RDCMDS */ "", 42306 /* IHOST_AXITRACE_ACP_ATM_RDMAX */ "", 42307 /* IHOST_AXITRACE_ACP_ATM_RDMIN */ "", 42308 /* IHOST_AXITRACE_ACP_ATM_RDOUTS */ "", 42309 /* IHOST_AXITRACE_ACP_ATM_RDSUM */ "", 42310 /* IHOST_AXITRACE_ACP_ATM_STATUS */ "", 42311 /* IHOST_AXITRACE_ACP_ATM_WBUSY */ "", 42312 /* IHOST_AXITRACE_ACP_ATM_WCYCLES */ "", 42313 /* IHOST_AXITRACE_ACP_ATM_WRBEATS */ "", 42314 /* IHOST_AXITRACE_ACP_ATM_WRCMDS */ "", 42315 /* IHOST_AXITRACE_ACP_ATM_WRMAX */ "", 42316 /* IHOST_AXITRACE_ACP_ATM_WRMIN */ "", 42317 /* IHOST_AXITRACE_ACP_ATM_WROUTS */ "", 42318 /* IHOST_AXITRACE_ACP_ATM_WRSUM */ "", 42319 /* IHOST_AXITRACE_M0_ATM_ADDRHIGH_0 */ "", 42320 /* IHOST_AXITRACE_M0_ATM_ADDRHIGH_1 */ "", 42321 /* IHOST_AXITRACE_M0_ATM_ADDRLOW_0 */ "", 42322 /* IHOST_AXITRACE_M0_ATM_ADDRLOW_1 */ "", 42323 /* IHOST_AXITRACE_M0_ATM_ARBUSY */ "", 42324 /* IHOST_AXITRACE_M0_ATM_ARCYCLES */ "", 42325 /* IHOST_AXITRACE_M0_ATM_AWBUSY */ "", 42326 /* IHOST_AXITRACE_M0_ATM_AWCYCLES */ "", 42327 /* IHOST_AXITRACE_M0_ATM_BBUSY */ "", 42328 /* IHOST_AXITRACE_M0_ATM_BCYCLES */ "", 42329 /* IHOST_AXITRACE_M0_ATM_CMD */ "", 42330 /* IHOST_AXITRACE_M0_ATM_CONFIG */ "", 42331 /* IHOST_AXITRACE_M0_ATM_FILTER_0 */ "", 42332 /* IHOST_AXITRACE_M0_ATM_FILTER_1 */ "", 42333 /* IHOST_AXITRACE_M0_ATM_OUTIDS */ "", 42334 /* IHOST_AXITRACE_M0_ATM_RBUSY */ "", 42335 /* IHOST_AXITRACE_M0_ATM_RCYCLES */ "", 42336 /* IHOST_AXITRACE_M0_ATM_RDBEATS */ "", 42337 /* IHOST_AXITRACE_M0_ATM_RDCMDS */ "", 42338 /* IHOST_AXITRACE_M0_ATM_RDMAX */ "", 42339 /* IHOST_AXITRACE_M0_ATM_RDMIN */ "", 42340 /* IHOST_AXITRACE_M0_ATM_RDOUTS */ "", 42341 /* IHOST_AXITRACE_M0_ATM_RDSUM */ "", 42342 /* IHOST_AXITRACE_M0_ATM_STATUS */ "", 42343 /* IHOST_AXITRACE_M0_ATM_WBUSY */ "", 42344 /* IHOST_AXITRACE_M0_ATM_WCYCLES */ "", 42345 /* IHOST_AXITRACE_M0_ATM_WRBEATS */ "", 42346 /* IHOST_AXITRACE_M0_ATM_WRCMDS */ "", 42347 /* IHOST_AXITRACE_M0_ATM_WRMAX */ "", 42348 /* IHOST_AXITRACE_M0_ATM_WRMIN */ "", 42349 /* IHOST_AXITRACE_M0_ATM_WROUTS */ "", 42350 /* IHOST_AXITRACE_M0_ATM_WRSUM */ "", 42351 /* IHOST_AXITRACE_M1_ATM_ADDRHIGH_0 */ "", 42352 /* IHOST_AXITRACE_M1_ATM_ADDRHIGH_1 */ "", 42353 /* IHOST_AXITRACE_M1_ATM_ADDRHIGH_2 */ "", 42354 /* IHOST_AXITRACE_M1_ATM_ADDRHIGH_3 */ "", 42355 /* IHOST_AXITRACE_M1_ATM_ADDRLOW_0 */ "", 42356 /* IHOST_AXITRACE_M1_ATM_ADDRLOW_1 */ "", 42357 /* IHOST_AXITRACE_M1_ATM_ADDRLOW_2 */ "", 42358 /* IHOST_AXITRACE_M1_ATM_ADDRLOW_3 */ "", 42359 /* IHOST_AXITRACE_M1_ATM_ARBUSY */ "", 42360 /* IHOST_AXITRACE_M1_ATM_ARCYCLES */ "", 42361 /* IHOST_AXITRACE_M1_ATM_AWBUSY */ "", 42362 /* IHOST_AXITRACE_M1_ATM_AWCYCLES */ "", 42363 /* IHOST_AXITRACE_M1_ATM_BBUSY */ "", 42364 /* IHOST_AXITRACE_M1_ATM_BCYCLES */ "", 42365 /* IHOST_AXITRACE_M1_ATM_CMD */ "", 42366 /* IHOST_AXITRACE_M1_ATM_CONFIG */ "", 42367 /* IHOST_AXITRACE_M1_ATM_FILTER_0 */ "", 42368 /* IHOST_AXITRACE_M1_ATM_FILTER_1 */ "", 42369 /* IHOST_AXITRACE_M1_ATM_FILTER_2 */ "", 42370 /* IHOST_AXITRACE_M1_ATM_FILTER_3 */ "", 42371 /* IHOST_AXITRACE_M1_ATM_OUTIDS */ "", 42372 /* IHOST_AXITRACE_M1_ATM_RBUSY */ "", 42373 /* IHOST_AXITRACE_M1_ATM_RCYCLES */ "", 42374 /* IHOST_AXITRACE_M1_ATM_RDBEATS */ "", 42375 /* IHOST_AXITRACE_M1_ATM_RDCMDS */ "", 42376 /* IHOST_AXITRACE_M1_ATM_RDMAX */ "", 42377 /* IHOST_AXITRACE_M1_ATM_RDMIN */ "", 42378 /* IHOST_AXITRACE_M1_ATM_RDOUTS */ "", 42379 /* IHOST_AXITRACE_M1_ATM_RDSUM */ "", 42380 /* IHOST_AXITRACE_M1_ATM_STATUS */ "", 42381 /* IHOST_AXITRACE_M1_ATM_WBUSY */ "", 42382 /* IHOST_AXITRACE_M1_ATM_WCYCLES */ "", 42383 /* IHOST_AXITRACE_M1_ATM_WRBEATS */ "", 42384 /* IHOST_AXITRACE_M1_ATM_WRCMDS */ "", 42385 /* IHOST_AXITRACE_M1_ATM_WRMAX */ "", 42386 /* IHOST_AXITRACE_M1_ATM_WRMIN */ "", 42387 /* IHOST_AXITRACE_M1_ATM_WROUTS */ "", 42388 /* IHOST_AXITRACE_M1_ATM_WRSUM */ "", 42389 /* IHOST_CONFIG_A72_CRM_ACP_CLK_DESC */ "", 42390 /* IHOST_CONFIG_A72_CRM_APB_BRIDGE_CONTROL */ "", 42391 /* IHOST_CONFIG_A72_CRM_APB_CLK_DESC */ "", 42392 /* IHOST_CONFIG_A72_CRM_ARM_CLK_DESC */ "", 42393 /* IHOST_CONFIG_A72_CRM_ATB_CLK_DESC */ "", 42394 /* IHOST_CONFIG_A72_CRM_AXI_CLK_DESC */ "", 42395 /* IHOST_CONFIG_A72_CRM_BOOT_STATUS */ "", 42396 /* IHOST_CONFIG_A72_CRM_CLOCK_CONTROL_0 */ "", 42397 /* IHOST_CONFIG_A72_CRM_CLOCK_CONTROL_1 */ "", 42398 /* IHOST_CONFIG_A72_CRM_CLOCK_ENABLE_0 */ "", 42399 /* IHOST_CONFIG_A72_CRM_CLOCK_IDLE_0 */ "", 42400 /* IHOST_CONFIG_A72_CRM_CLOCK_INTERRUPT_STATUS */ "", 42401 /* IHOST_CONFIG_A72_CRM_CLOCK_INT_ENABLE */ "", 42402 /* IHOST_CONFIG_A72_CRM_CLOCK_INT_ENABLE_0 */ "", 42403 /* IHOST_CONFIG_A72_CRM_CLOCK_MODE_CONTROL */ "", 42404 /* IHOST_CONFIG_A72_CRM_CLOCK_MONITOR */ "", 42405 /* IHOST_CONFIG_A72_CRM_CLOCK_MONITOR_DIVIDER */ "", 42406 /* IHOST_CONFIG_A72_CRM_CLOCK_SOURCE_DETECTION */ "", 42407 /* IHOST_CONFIG_A72_CRM_CLOCK_STATUS */ "", 42408 /* IHOST_CONFIG_A72_CRM_CLOCK_STATUS_0 */ "", 42409 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_0 */ "", 42410 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_1 */ "", 42411 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_DBGCTRL */ "", 42412 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_DBGROM_HI */ "", 42413 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_DBGROM_LO */ "", 42414 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA0_HI */ "", 42415 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA0_LO */ "", 42416 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA0_MID */ "", 42417 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA1_HI */ "", 42418 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA1_LO */ "", 42419 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA1_MID */ "", 42420 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA2_HI */ "", 42421 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA2_LO */ "", 42422 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA2_MID */ "", 42423 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA3_HI */ "", 42424 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA3_LO */ "", 42425 /* IHOST_CONFIG_A72_CRM_CORE_CONFIG_RVBA3_MID */ "", 42426 /* IHOST_CONFIG_A72_CRM_CRYSTAL_CONTROL */ "", 42427 /* IHOST_CONFIG_A72_CRM_DOMAIN_0_CONTROL */ "", 42428 /* IHOST_CONFIG_A72_CRM_DOMAIN_1_CONTROL */ "", 42429 /* IHOST_CONFIG_A72_CRM_DOMAIN_2_CONTROL */ "", 42430 /* IHOST_CONFIG_A72_CRM_DOMAIN_3_CONTROL */ "", 42431 /* IHOST_CONFIG_A72_CRM_DOMAIN_4_CONTROL */ "", 42432 /* IHOST_CONFIG_A72_CRM_IDLE_STATUS */ "", 42433 /* IHOST_CONFIG_A72_CRM_INTERRUPT_ENABLE */ "", 42434 /* IHOST_CONFIG_A72_CRM_INTERRUPT_STATUS */ "", 42435 /* IHOST_CONFIG_A72_CRM_MEASURE_COMMAND */ "", 42436 /* IHOST_CONFIG_A72_CRM_MEASURE_COMMAND_STATUS */ "", 42437 /* IHOST_CONFIG_A72_CRM_MEASURE_CONTROL */ "", 42438 /* IHOST_CONFIG_A72_CRM_MEASURE_CTRL_TIMER */ "", 42439 /* IHOST_CONFIG_A72_CRM_MEASURE_REFERENCE_TIMER_LSB */ "", 42440 /* IHOST_CONFIG_A72_CRM_MEASURE_REFERENCE_TIMER_MSB */ "", 42441 /* IHOST_CONFIG_A72_CRM_MEASURE_RESULT_EVENT */ "", 42442 /* IHOST_CONFIG_A72_CRM_MEASURE_RESULT_FREQ */ "", 42443 /* IHOST_CONFIG_A72_CRM_MEASURE_RESULT_LSB */ "", 42444 /* IHOST_CONFIG_A72_CRM_MEASURE_RESULT_MSB */ "", 42445 /* IHOST_CONFIG_A72_CRM_MEASURE_SELECTION_CLOCK */ "", 42446 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_IN_DOMAIN_0 */ "", 42447 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_IN_DOMAIN_1 */ "", 42448 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_IN_DOMAIN_2 */ "", 42449 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_IN_DOMAIN_3 */ "", 42450 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_IN_DOMAIN_4 */ "", 42451 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_OUT_DOMAIN_0 */ "", 42452 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_OUT_DOMAIN_1 */ "", 42453 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_OUT_DOMAIN_2 */ "", 42454 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_OUT_DOMAIN_3 */ "", 42455 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWROK_OUT_DOMAIN_4 */ "", 42456 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_IN_DOMAIN_0 */ "", 42457 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_IN_DOMAIN_1 */ "", 42458 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_IN_DOMAIN_2 */ "", 42459 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_IN_DOMAIN_3 */ "", 42460 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_IN_DOMAIN_4 */ "", 42461 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_OUT_DOMAIN_0 */ "", 42462 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_OUT_DOMAIN_1 */ "", 42463 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_OUT_DOMAIN_2 */ "", 42464 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_OUT_DOMAIN_3 */ "", 42465 /* IHOST_CONFIG_A72_CRM_MEM_ARRPWRON_OUT_DOMAIN_4 */ "", 42466 /* IHOST_CONFIG_A72_CRM_MISC_FUNCTION_0 */ "", 42467 /* IHOST_CONFIG_A72_CRM_PCLKDBG_DESC */ "", 42468 /* IHOST_CONFIG_A72_CRM_PLL0_CFG0_CTRL */ "", 42469 /* IHOST_CONFIG_A72_CRM_PLL0_CFG1_CTRL */ "", 42470 /* IHOST_CONFIG_A72_CRM_PLL0_CFG2_CTRL */ "", 42471 /* IHOST_CONFIG_A72_CRM_PLL0_CFG3_CTRL */ "", 42472 /* IHOST_CONFIG_A72_CRM_PLL0_CHANNEL0_DESCRIPTION */ "", 42473 /* IHOST_CONFIG_A72_CRM_PLL0_CHANNEL_CONTROL */ "", 42474 /* IHOST_CONFIG_A72_CRM_PLL0_CTRL1 */ "", 42475 /* IHOST_CONFIG_A72_CRM_PLL0_CTRL2 */ "", 42476 /* IHOST_CONFIG_A72_CRM_PLL0_CTRL3 */ "", 42477 /* IHOST_CONFIG_A72_CRM_PLL0_CTRL4 */ "", 42478 /* IHOST_CONFIG_A72_CRM_PLL0_CTRL_SSC0 */ "", 42479 /* IHOST_CONFIG_A72_CRM_PLL0_CTRL_SSC1 */ "", 42480 /* IHOST_CONFIG_A72_CRM_PLL0_CTRL_SSC2 */ "", 42481 /* IHOST_CONFIG_A72_CRM_PLL0_STATUS_OUT */ "", 42482 /* IHOST_CONFIG_A72_CRM_PLL_CHANNEL_BYPASS_ENABLE */ "", 42483 /* IHOST_CONFIG_A72_CRM_PLL_CHANNEL_STATUS */ "", 42484 /* IHOST_CONFIG_A72_CRM_PLL_COMMAND */ "", 42485 /* IHOST_CONFIG_A72_CRM_PLL_CTRL_STATUS_0 */ "", 42486 /* IHOST_CONFIG_A72_CRM_PLL_CTRL_STATUS_1 */ "", 42487 /* IHOST_CONFIG_A72_CRM_PLL_INTERRUPT_ENABLE */ "", 42488 /* IHOST_CONFIG_A72_CRM_PLL_INTERRUPT_STATUS */ "", 42489 /* IHOST_CONFIG_A72_CRM_PLL_PWR_ON */ "", 42490 /* IHOST_CONFIG_A72_CRM_PLL_STATUS */ "", 42491 /* IHOST_CONFIG_A72_CRM_PWROKOUT_STATUS */ "", 42492 /* IHOST_CONFIG_A72_CRM_PWROK_INTERRUPT_STATUS */ "", 42493 /* IHOST_CONFIG_A72_CRM_PWROK_INT_ENABLE */ "", 42494 /* IHOST_CONFIG_A72_CRM_PWROK_IN_DOMAIN_0 */ "", 42495 /* IHOST_CONFIG_A72_CRM_PWROK_IN_DOMAIN_1 */ "", 42496 /* IHOST_CONFIG_A72_CRM_PWROK_IN_DOMAIN_2 */ "", 42497 /* IHOST_CONFIG_A72_CRM_PWROK_IN_DOMAIN_3 */ "", 42498 /* IHOST_CONFIG_A72_CRM_PWROK_IN_DOMAIN_4 */ "", 42499 /* IHOST_CONFIG_A72_CRM_PWROK_OUT_DOMAIN_0 */ "", 42500 /* IHOST_CONFIG_A72_CRM_PWROK_OUT_DOMAIN_1 */ "", 42501 /* IHOST_CONFIG_A72_CRM_PWROK_OUT_DOMAIN_2 */ "", 42502 /* IHOST_CONFIG_A72_CRM_PWROK_OUT_DOMAIN_3 */ "", 42503 /* IHOST_CONFIG_A72_CRM_PWROK_OUT_DOMAIN_4 */ "", 42504 /* IHOST_CONFIG_A72_CRM_PWRONOUT_STATUS */ "", 42505 /* IHOST_CONFIG_A72_CRM_PWRON_INTERRUPT_STATUS */ "", 42506 /* IHOST_CONFIG_A72_CRM_PWRON_INT_ENABLE */ "", 42507 /* IHOST_CONFIG_A72_CRM_PWRON_IN_DOMAIN_0 */ "", 42508 /* IHOST_CONFIG_A72_CRM_PWRON_IN_DOMAIN_1 */ "", 42509 /* IHOST_CONFIG_A72_CRM_PWRON_IN_DOMAIN_2 */ "", 42510 /* IHOST_CONFIG_A72_CRM_PWRON_IN_DOMAIN_3 */ "", 42511 /* IHOST_CONFIG_A72_CRM_PWRON_IN_DOMAIN_4 */ "", 42512 /* IHOST_CONFIG_A72_CRM_PWRON_OUT_DOMAIN_0 */ "", 42513 /* IHOST_CONFIG_A72_CRM_PWRON_OUT_DOMAIN_1 */ "", 42514 /* IHOST_CONFIG_A72_CRM_PWRON_OUT_DOMAIN_2 */ "", 42515 /* IHOST_CONFIG_A72_CRM_PWRON_OUT_DOMAIN_3 */ "", 42516 /* IHOST_CONFIG_A72_CRM_PWRON_OUT_DOMAIN_4 */ "", 42517 /* IHOST_CONFIG_A72_CRM_RESETN_CONTROL */ "", 42518 /* IHOST_CONFIG_A72_CRM_RESETN_INTERRUPT_STATUS */ "", 42519 /* IHOST_CONFIG_A72_CRM_RESETN_INT_ENABLE_0 */ "", 42520 /* IHOST_CONFIG_A72_CRM_RESETN_INT_ENABLE_1 */ "", 42521 /* IHOST_CONFIG_A72_CRM_RESETN_STATUS */ "", 42522 /* IHOST_CONFIG_A72_CRM_RESETN_STATUS_0 */ "", 42523 /* IHOST_CONFIG_A72_CRM_RESETN_STATUS_1 */ "", 42524 /* IHOST_CONFIG_A72_CRM_RESETN_STATUS_INT_ENB */ "", 42525 /* IHOST_CONFIG_A72_CRM_SEL_DEBUG_VECTOR */ "", 42526 /* IHOST_CONFIG_A72_CRM_SIGNATURE_0 */ "", 42527 /* IHOST_CONFIG_A72_CRM_SIGNATURE_1 */ "", 42528 /* IHOST_CONFIG_A72_CRM_SIGNATURE_2 */ "", 42529 /* IHOST_CONFIG_A72_CRM_SIGNATURE_3 */ "", 42530 /* IHOST_CONFIG_A72_CRM_SOFTRESETN_0 */ "", 42531 /* IHOST_CONFIG_A72_CRM_SOFTRESETN_1 */ "", 42532 /* IHOST_CONFIG_A72_CRM_SPARE */ "", 42533 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM2_INTERRUPT_CONTROL */ "", 42534 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM2_INTERRUPT_ENABLE */ "", 42535 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM2_INTERRUPT_SIGNAL */ "", 42536 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM2_INTERRUPT_STATUS */ "", 42537 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM2_INTERRUPT_STATUS_ENABLE */ "", 42538 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM3_INTERRUPT_CONTROL */ "", 42539 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM4_INTERRUPT_CONTROL */ "", 42540 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_CONFIG_0 */ "", 42541 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_CONFIG_1 */ "", 42542 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_CONFIG_2 */ "", 42543 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_CONFIG_3 */ "", 42544 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_INTERRUPT_CONTROL */ "", 42545 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_INTERRUPT_ENABLE */ "", 42546 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_INTERRUPT_SIGNAL */ "", 42547 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_INTERRUPT_STATUS */ "", 42548 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_INTERRUPT_STATUS_ENABLE */ "", 42549 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_MEMORY_CONTROL_0 */ "", 42550 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_MEMORY_CONTROL_1 */ "", 42551 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_MEMORY_CONTROL_2 */ "", 42552 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_MEMORY_CONTROL_3 */ "", 42553 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_STATUS_0 */ "", 42554 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_STATUS_1 */ "", 42555 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_STATUS_2 */ "", 42556 /* IHOST_CONFIG_A72_CRM_SUBSYSTEM_STATUS_3 */ "", 42557 /* IHOST_CONFIG_A72_CRM_TMON_CLK_DESC */ "", 42558 /* IHOST_CONFIG_A72_CRM_TMON_CONTROL */ "", 42559 /* IHOST_CONFIG_A72_CRM_TMON_STATUS */ "", 42560 /* IHOST_CONFIG_A72_CRM_WASP_CONTROL */ "", 42561 /* IHOST_CONFIG_A72_SAT_TMR_CTRL */ "", 42562 /* IHOST_CONFIG_A72_SAT_TMR_GET_H */ "", 42563 /* IHOST_CONFIG_A72_SAT_TMR_GET_L */ "", 42564 /* IHOST_CONFIG_A72_SAT_TMR_INC_H */ "", 42565 /* IHOST_CONFIG_A72_SAT_TMR_INC_L */ "", 42566 /* IHOST_CONFIG_A72_SAT_TMR_SET_H */ "", 42567 /* IHOST_CONFIG_A72_SAT_TMR_SET_L */ "", 42568 /* IHOST_CONFIG_A72_TMON_CFG_ANALOG_CTRL */ "", 42569 /* IHOST_CONFIG_A72_TMON_CFG_ANALOG_PWRUP_WAIT */ "", 42570 /* IHOST_CONFIG_A72_TMON_CFG_BYPASS_ANALOG_CTRL */ "", 42571 /* IHOST_CONFIG_A72_TMON_CFG_CLEAR_INTERRUPT */ "", 42572 /* IHOST_CONFIG_A72_TMON_CFG_DIGITAL_CONTROL */ "", 42573 /* IHOST_CONFIG_A72_TMON_CFG_ENABLE */ "", 42574 /* IHOST_CONFIG_A72_TMON_CFG_INTERRUPT_HI_THRESH */ "", 42575 /* IHOST_CONFIG_A72_TMON_CFG_INTERRUPT_LO_THRESH */ "", 42576 /* IHOST_CONFIG_A72_TMON_CFG_INTERVAL_VALUE */ "", 42577 /* IHOST_CONFIG_A72_TMON_CFG_LAST_TEMP_VALUE */ "", 42578 /* IHOST_CONFIG_A72_TMON_CFG_NUM_OF_READINGS2TAKE */ "", 42579 /* IHOST_CONFIG_A72_TMON_CFG_RESET_THRESH */ "", 42580 /* IHOST_CONFIG_A72_TMON_CFG_SUPPLY_MODE */ "", 42581 /* IHOST_CRU_ICFG_CONFIG_CONTROL */ "", 42582 /* IHOST_CRU_ICFG_IHOST_STATUS */ "", 42583 /* IHOST_CRU_ICFG_OVERRIDE_CONTROL */ "", 42584 /* IHOST_CRU_ICFG_PCIE_ACCESS_63_TO_40_ADDR */ "", 42585 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_0 */ "", 42586 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_1 */ "", 42587 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_2 */ "", 42588 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_3 */ "", 42589 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_4 */ "", 42590 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_5 */ "", 42591 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_6 */ "", 42592 /* IHOST_CRU_ICFG_PEN_HOLDER_MODE_IHOST_INSTRUCTION_7 */ "", 42593 /* IHOST_CRU_ICFG_PERIPHBASE */ "", 42594 /* IHOST_CRU_ICFG_RVBARADDR_LSB */ "", 42595 /* IHOST_CRU_ICFG_RVBARADDR_MSB */ "", 42596 /* IHOST_DEBUG_A72_CTI0_ASICCTL */ "", 42597 /* IHOST_DEBUG_A72_CTI0_CLAIMCLR */ "", 42598 /* IHOST_DEBUG_A72_CTI0_CLAIMSET */ "", 42599 /* IHOST_DEBUG_A72_CTI0_COMPID0 */ "", 42600 /* IHOST_DEBUG_A72_CTI0_COMPID1 */ "", 42601 /* IHOST_DEBUG_A72_CTI0_COMPID2 */ "", 42602 /* IHOST_DEBUG_A72_CTI0_COMPID3 */ "", 42603 /* IHOST_DEBUG_A72_CTI0_CTIAPPCLEAR */ "", 42604 /* IHOST_DEBUG_A72_CTI0_CTIAPPPULSE */ "", 42605 /* IHOST_DEBUG_A72_CTI0_CTIAPPSET */ "", 42606 /* IHOST_DEBUG_A72_CTI0_CTIAUTHSTATUS_EL1 */ "", 42607 /* IHOST_DEBUG_A72_CTI0_CTICHINSTATUS */ "", 42608 /* IHOST_DEBUG_A72_CTI0_CTICHOUTSTATUS */ "", 42609 /* IHOST_DEBUG_A72_CTI0_CTICONTROL */ "", 42610 /* IHOST_DEBUG_A72_CTI0_CTIGATE */ "", 42611 /* IHOST_DEBUG_A72_CTI0_CTIINEN0 */ "", 42612 /* IHOST_DEBUG_A72_CTI0_CTIINEN1 */ "", 42613 /* IHOST_DEBUG_A72_CTI0_CTIINEN2 */ "", 42614 /* IHOST_DEBUG_A72_CTI0_CTIINEN3 */ "", 42615 /* IHOST_DEBUG_A72_CTI0_CTIINEN4 */ "", 42616 /* IHOST_DEBUG_A72_CTI0_CTIINEN5 */ "", 42617 /* IHOST_DEBUG_A72_CTI0_CTIINEN6 */ "", 42618 /* IHOST_DEBUG_A72_CTI0_CTIINEN7 */ "", 42619 /* IHOST_DEBUG_A72_CTI0_CTIINTACK */ "", 42620 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN0 */ "", 42621 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN1 */ "", 42622 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN2 */ "", 42623 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN3 */ "", 42624 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN4 */ "", 42625 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN5 */ "", 42626 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN6 */ "", 42627 /* IHOST_DEBUG_A72_CTI0_CTIOUTEN7 */ "", 42628 /* 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IHOST_DEBUG_A72_DEBUG0_ID_AA64ISAR0L_EL1 */ "", 42729 /* IHOST_DEBUG_A72_DEBUG0_ID_AA64MMFR0H_EL1 */ "", 42730 /* IHOST_DEBUG_A72_DEBUG0_ID_AA64MMFR0L_EL1 */ "", 42731 /* IHOST_DEBUG_A72_DEBUG0_ID_AA64PFR0H_EL1 */ "", 42732 /* IHOST_DEBUG_A72_DEBUG0_ID_AA64PFR0L_EL1 */ "", 42733 /* IHOST_DEBUG_A72_DEBUG0_MIDR_EL1 */ "", 42734 /* IHOST_DEBUG_A72_DEBUG0_OSLAR_EL1 */ "", 42735 /* IHOST_DEBUG_A72_PMU0_PMAUTHSTATUS */ "", 42736 /* IHOST_DEBUG_A72_PMU0_PMCCFILTR_EL0 */ "", 42737 /* IHOST_DEBUG_A72_PMU0_PMCCNTRH_EL0 */ "", 42738 /* IHOST_DEBUG_A72_PMU0_PMCCNTRL_EL0 */ "", 42739 /* IHOST_DEBUG_A72_PMU0_PMCCNTSRH */ "", 42740 /* IHOST_DEBUG_A72_PMU0_PMCCNTSRL */ "", 42741 /* IHOST_DEBUG_A72_PMU0_PMCEID0_EL0 */ "", 42742 /* IHOST_DEBUG_A72_PMU0_PMCEID1_EL0 */ "", 42743 /* IHOST_DEBUG_A72_PMU0_PMCFGR */ "", 42744 /* IHOST_DEBUG_A72_PMU0_PMCID0 */ "", 42745 /* IHOST_DEBUG_A72_PMU0_PMCID1 */ "", 42746 /* IHOST_DEBUG_A72_PMU0_PMCID2 */ "", 42747 /* IHOST_DEBUG_A72_PMU0_PMCID3 */ "", 42748 /* IHOST_DEBUG_A72_PMU0_PMCIDSR */ "", 42749 /* IHOST_DEBUG_A72_PMU0_PMCNTENCLR_EL0 */ "", 42750 /* IHOST_DEBUG_A72_PMU0_PMCNTENSET_EL0 */ "", 42751 /* IHOST_DEBUG_A72_PMU0_PMCR_EL0 */ "", 42752 /* IHOST_DEBUG_A72_PMU0_PMDEVAFF0 */ "", 42753 /* IHOST_DEBUG_A72_PMU0_PMDEVAFF1 */ "", 42754 /* IHOST_DEBUG_A72_PMU0_PMDEVARCH */ "", 42755 /* IHOST_DEBUG_A72_PMU0_PMDEVTYPE */ "", 42756 /* IHOST_DEBUG_A72_PMU0_PMEVCNTR0_EL0 */ "", 42757 /* IHOST_DEBUG_A72_PMU0_PMEVCNTR1_EL0 */ "", 42758 /* IHOST_DEBUG_A72_PMU0_PMEVCNTR2_EL0 */ "", 42759 /* IHOST_DEBUG_A72_PMU0_PMEVCNTR3_EL0 */ "", 42760 /* IHOST_DEBUG_A72_PMU0_PMEVCNTR4_EL0 */ "", 42761 /* IHOST_DEBUG_A72_PMU0_PMEVCNTR5_EL0 */ "", 42762 /* IHOST_DEBUG_A72_PMU0_PMEVCNTSR0 */ "", 42763 /* IHOST_DEBUG_A72_PMU0_PMEVCNTSR1 */ "", 42764 /* IHOST_DEBUG_A72_PMU0_PMEVCNTSR2 */ "", 42765 /* IHOST_DEBUG_A72_PMU0_PMEVCNTSR3 */ "", 42766 /* IHOST_DEBUG_A72_PMU0_PMEVCNTSR4 */ "", 42767 /* IHOST_DEBUG_A72_PMU0_PMEVCNTSR5 */ "", 42768 /* IHOST_DEBUG_A72_PMU0_PMEVTYPER0_EL0 */ "", 42769 /* IHOST_DEBUG_A72_PMU0_PMEVTYPER1_EL0 */ "", 42770 /* IHOST_DEBUG_A72_PMU0_PMEVTYPER2_EL0 */ "", 42771 /* IHOST_DEBUG_A72_PMU0_PMEVTYPER3_EL0 */ "", 42772 /* IHOST_DEBUG_A72_PMU0_PMEVTYPER4_EL0 */ "", 42773 /* IHOST_DEBUG_A72_PMU0_PMEVTYPER5_EL0 */ "", 42774 /* IHOST_DEBUG_A72_PMU0_PMINTENCLR_EL1 */ "", 42775 /* IHOST_DEBUG_A72_PMU0_PMINTENSET_EL1 */ "", 42776 /* IHOST_DEBUG_A72_PMU0_PMLAR */ "", 42777 /* IHOST_DEBUG_A72_PMU0_PMLSR */ "", 42778 /* IHOST_DEBUG_A72_PMU0_PMOVSR_EL0 */ "", 42779 /* IHOST_DEBUG_A72_PMU0_PMOVSSET_EL0 */ "", 42780 /* IHOST_DEBUG_A72_PMU0_PMOVSSR */ "", 42781 /* IHOST_DEBUG_A72_PMU0_PMPCSRHI */ "", 42782 /* IHOST_DEBUG_A72_PMU0_PMPCSRLO */ "", 42783 /* IHOST_DEBUG_A72_PMU0_PMPID0 */ "", 42784 /* IHOST_DEBUG_A72_PMU0_PMPID1 */ "", 42785 /* IHOST_DEBUG_A72_PMU0_PMPID2 */ "", 42786 /* IHOST_DEBUG_A72_PMU0_PMPID3 */ "", 42787 /* IHOST_DEBUG_A72_PMU0_PMPID4 */ "", 42788 /* IHOST_DEBUG_A72_PMU0_PMPID5 */ "", 42789 /* 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/* IHOST_DEBUG_A72_TRACE0_TRCIDR3 */ "", 42889 /* IHOST_DEBUG_A72_TRACE0_TRCIDR4 */ "", 42890 /* IHOST_DEBUG_A72_TRACE0_TRCIDR5 */ "", 42891 /* IHOST_DEBUG_A72_TRACE0_TRCIDR8 */ "", 42892 /* IHOST_DEBUG_A72_TRACE0_TRCIDR9 */ "", 42893 /* IHOST_DEBUG_A72_TRACE0_TRCIDR10 */ "", 42894 /* IHOST_DEBUG_A72_TRACE0_TRCIDR11 */ "", 42895 /* IHOST_DEBUG_A72_TRACE0_TRCIDR12 */ "", 42896 /* IHOST_DEBUG_A72_TRACE0_TRCIDR13 */ "", 42897 /* IHOST_DEBUG_A72_TRACE0_TRCITATBCTR0 */ "", 42898 /* IHOST_DEBUG_A72_TRACE0_TRCITATBCTR1 */ "", 42899 /* IHOST_DEBUG_A72_TRACE0_TRCITATBCTR2 */ "", 42900 /* IHOST_DEBUG_A72_TRACE0_TRCITATBDATA0 */ "", 42901 /* IHOST_DEBUG_A72_TRACE0_TRCITCTRL */ "", 42902 /* IHOST_DEBUG_A72_TRACE0_TRCITMISCIN */ "", 42903 /* IHOST_DEBUG_A72_TRACE0_TRCITMISCOUT */ "", 42904 /* IHOST_DEBUG_A72_TRACE0_TRCLAR */ "", 42905 /* IHOST_DEBUG_A72_TRACE0_TRCLSR */ "", 42906 /* IHOST_DEBUG_A72_TRACE0_TRCOSLAR */ "", 42907 /* IHOST_DEBUG_A72_TRACE0_TRCOSLSR */ "", 42908 /* IHOST_DEBUG_A72_TRACE0_TRCPDCR */ "", 42909 /* IHOST_DEBUG_A72_TRACE0_TRCPDSR */ "", 42910 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR0 */ "", 42911 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR1 */ "", 42912 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR2 */ "", 42913 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR3 */ "", 42914 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR4 */ "", 42915 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR5 */ "", 42916 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR6 */ "", 42917 /* IHOST_DEBUG_A72_TRACE0_TRCPIDR7 */ "", 42918 /* IHOST_DEBUG_A72_TRACE0_TRCPRGCTLR */ "", 42919 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR2 */ "", 42920 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR3 */ "", 42921 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR4 */ "", 42922 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR5 */ "", 42923 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR6 */ "", 42924 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR7 */ "", 42925 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR8 */ "", 42926 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR9 */ "", 42927 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR10 */ "", 42928 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR11 */ "", 42929 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR12 */ "", 42930 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR13 */ "", 42931 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR14 */ "", 42932 /* IHOST_DEBUG_A72_TRACE0_TRCRSCTLR15 */ "", 42933 /* IHOST_DEBUG_A72_TRACE0_TRCSEQEVR0 */ "", 42934 /* IHOST_DEBUG_A72_TRACE0_TRCSEQEVR1 */ "", 42935 /* IHOST_DEBUG_A72_TRACE0_TRCSEQEVR2 */ "", 42936 /* IHOST_DEBUG_A72_TRACE0_TRCSEQRSTEVR */ "", 42937 /* IHOST_DEBUG_A72_TRACE0_TRCSEQSTR */ "", 42938 /* IHOST_DEBUG_A72_TRACE0_TRCSSCCR0 */ "", 42939 /* IHOST_DEBUG_A72_TRACE0_TRCSSCSR0 */ "", 42940 /* IHOST_DEBUG_A72_TRACE0_TRCSTATR */ "", 42941 /* IHOST_DEBUG_A72_TRACE0_TRCSYNCPR */ "", 42942 /* IHOST_DEBUG_A72_TRACE0_TRCTRACEIDR */ "", 42943 /* IHOST_DEBUG_A72_TRACE0_TRCTSCTLR */ "", 42944 /* IHOST_DEBUG_A72_TRACE0_TRCVICTLR */ "", 42945 /* IHOST_DEBUG_A72_TRACE0_TRCVIIECTLR */ "", 42946 /* IHOST_DEBUG_A72_TRACE0_TRCVISSCTLR */ "", 42947 /* IHOST_DEBUG_A72_TRACE0_TRCVMIDCVRH0 */ "", 42948 /* IHOST_DEBUG_A72_TRACE0_TRCVMIDCVRL0 */ "", 42949 /* IHOST_GICCPU_ALIAS_BIN_PT_NS */ "", 42950 /* IHOST_GICCPU_BIN_PT */ "", 42951 /* IHOST_GICCPU_CONTROL */ "", 42952 /* IHOST_GICCPU_CPU_IDENT */ "", 42953 /* IHOST_GICCPU_EOI */ "", 42954 /* IHOST_GICCPU_HI_PEND */ "", 42955 /* IHOST_GICCPU_INTEG_ENABLE */ "", 42956 /* IHOST_GICCPU_INTEG_MATCH */ "", 42957 /* IHOST_GICCPU_INT_ACK */ "", 42958 /* IHOST_GICCPU_INT_CFG */ "", 42959 /* IHOST_GICCPU_INT_FIQ_SET */ "", 42960 /* IHOST_GICCPU_PRIORITY_MASK */ "", 42961 /* IHOST_GICCPU_RUN_PRIORITY */ "", 42962 /* IHOST_GICDIST_ACTIVE_STATUS0 */ "", 42963 /* IHOST_GICDIST_ACTIVE_STATUS1 */ "", 42964 /* IHOST_GICDIST_ACTIVE_STATUS2 */ "", 42965 /* IHOST_GICDIST_ACTIVE_STATUS3 */ "", 42966 /* IHOST_GICDIST_ACTIVE_STATUS4 */ "", 42967 /* IHOST_GICDIST_ACTIVE_STATUS5 */ "", 42968 /* IHOST_GICDIST_ACTIVE_STATUS6 */ "", 42969 /* IHOST_GICDIST_ACTIVE_STATUS7 */ "", 42970 /* IHOST_GICDIST_DIST_IDENT_REG */ "", 42971 /* IHOST_GICDIST_ENABLE_CLR0 */ "", 42972 /* IHOST_GICDIST_ENABLE_CLR1 */ "", 42973 /* IHOST_GICDIST_ENABLE_CLR2 */ "", 42974 /* IHOST_GICDIST_ENABLE_CLR3 */ "", 42975 /* IHOST_GICDIST_ENABLE_CLR4 */ "", 42976 /* IHOST_GICDIST_ENABLE_CLR5 */ "", 42977 /* IHOST_GICDIST_ENABLE_CLR6 */ "", 42978 /* IHOST_GICDIST_ENABLE_CLR7 */ "", 42979 /* IHOST_GICDIST_ENABLE_S */ "", 42980 /* IHOST_GICDIST_ENABLE_SET0 */ "", 42981 /* IHOST_GICDIST_ENABLE_SET1 */ "", 42982 /* IHOST_GICDIST_ENABLE_SET2 */ "", 42983 /* IHOST_GICDIST_ENABLE_SET3 */ "", 42984 /* IHOST_GICDIST_ENABLE_SET4 */ "", 42985 /* IHOST_GICDIST_ENABLE_SET5 */ "", 42986 /* IHOST_GICDIST_ENABLE_SET6 */ "", 42987 /* IHOST_GICDIST_ENABLE_SET7 */ "", 42988 /* IHOST_GICDIST_IC_TYPE_REG */ "", 42989 /* IHOST_GICDIST_INT_CONFIG0 */ "", 42990 /* IHOST_GICDIST_INT_CONFIG1 */ "", 42991 /* IHOST_GICDIST_INT_CONFIG2 */ "", 42992 /* IHOST_GICDIST_INT_CONFIG3 */ "", 42993 /* IHOST_GICDIST_INT_CONFIG4 */ "", 42994 /* IHOST_GICDIST_INT_CONFIG5 */ "", 42995 /* IHOST_GICDIST_INT_CONFIG6 */ "", 42996 /* IHOST_GICDIST_INT_CONFIG7 */ "", 42997 /* IHOST_GICDIST_INT_CONFIG8 */ "", 42998 /* IHOST_GICDIST_INT_CONFIG9 */ "", 42999 /* IHOST_GICDIST_INT_CONFIG10 */ "", 43000 /* IHOST_GICDIST_INT_CONFIG11 */ "", 43001 /* IHOST_GICDIST_INT_CONFIG12 */ "", 43002 /* IHOST_GICDIST_INT_CONFIG13 */ "", 43003 /* IHOST_GICDIST_INT_CONFIG14 */ "", 43004 /* IHOST_GICDIST_INT_CONFIG15 */ "", 43005 /* IHOST_GICDIST_INT_SECURITY0 */ "", 43006 /* IHOST_GICDIST_INT_SECURITY1 */ "", 43007 /* IHOST_GICDIST_INT_SECURITY2 */ "", 43008 /* IHOST_GICDIST_INT_SECURITY3 */ "", 43009 /* IHOST_GICDIST_INT_SECURITY4 */ "", 43010 /* IHOST_GICDIST_INT_SECURITY5 */ "", 43011 /* IHOST_GICDIST_INT_SECURITY6 */ "", 43012 /* IHOST_GICDIST_INT_SECURITY7 */ "", 43013 /* IHOST_GICDIST_PCELL_ID_0 */ "", 43014 /* IHOST_GICDIST_PCELL_ID_1 */ "", 43015 /* IHOST_GICDIST_PCELL_ID_2 */ "", 43016 /* IHOST_GICDIST_PCELL_ID_3 */ "", 43017 /* IHOST_GICDIST_PENDING_CLR0 */ "", 43018 /* IHOST_GICDIST_PENDING_CLR1 */ "", 43019 /* IHOST_GICDIST_PENDING_CLR2 */ "", 43020 /* IHOST_GICDIST_PENDING_CLR3 */ "", 43021 /* IHOST_GICDIST_PENDING_CLR4 */ "", 43022 /* IHOST_GICDIST_PENDING_CLR5 */ "", 43023 /* IHOST_GICDIST_PENDING_CLR6 */ "", 43024 /* IHOST_GICDIST_PENDING_CLR7 */ "", 43025 /* IHOST_GICDIST_PENDING_SET0 */ "", 43026 /* IHOST_GICDIST_PENDING_SET1 */ "", 43027 /* IHOST_GICDIST_PENDING_SET2 */ "", 43028 /* IHOST_GICDIST_PENDING_SET3 */ "", 43029 /* IHOST_GICDIST_PENDING_SET4 */ "", 43030 /* IHOST_GICDIST_PENDING_SET5 */ "", 43031 /* IHOST_GICDIST_PENDING_SET6 */ "", 43032 /* IHOST_GICDIST_PENDING_SET7 */ "", 43033 /* IHOST_GICDIST_PERIPH_ID_1 */ "", 43034 /* IHOST_GICDIST_PERIPH_ID_2 */ "", 43035 /* IHOST_GICDIST_PERIPH_ID_3 */ "", 43036 /* IHOST_GICDIST_PERIPH_ID_4 */ "", 43037 /* IHOST_GICDIST_PERIPH_ID_5 */ "", 43038 /* IHOST_GICDIST_PERIPH_ID_6 */ "", 43039 /* IHOST_GICDIST_PERIPH_ID_7 */ "", 43040 /* IHOST_GICDIST_PPI_STATUS */ "", 43041 /* IHOST_GICDIST_PRIORITY_LEVEL0 */ "", 43042 /* IHOST_GICDIST_PRIORITY_LEVEL1 */ "", 43043 /* IHOST_GICDIST_PRIORITY_LEVEL2 */ "", 43044 /* IHOST_GICDIST_PRIORITY_LEVEL3 */ "", 43045 /* IHOST_GICDIST_PRIORITY_LEVEL4 */ "", 43046 /* IHOST_GICDIST_PRIORITY_LEVEL5 */ "", 43047 /* IHOST_GICDIST_PRIORITY_LEVEL6 */ "", 43048 /* IHOST_GICDIST_PRIORITY_LEVEL7 */ "", 43049 /* IHOST_GICDIST_PRIORITY_LEVEL8 */ "", 43050 /* IHOST_GICDIST_PRIORITY_LEVEL9 */ "", 43051 /* IHOST_GICDIST_PRIORITY_LEVEL10 */ "", 43052 /* IHOST_GICDIST_PRIORITY_LEVEL11 */ "", 43053 /* IHOST_GICDIST_PRIORITY_LEVEL12 */ "", 43054 /* IHOST_GICDIST_PRIORITY_LEVEL13 */ "", 43055 /* IHOST_GICDIST_PRIORITY_LEVEL14 */ "", 43056 /* IHOST_GICDIST_PRIORITY_LEVEL15 */ "", 43057 /* IHOST_GICDIST_PRIORITY_LEVEL16 */ "", 43058 /* IHOST_GICDIST_PRIORITY_LEVEL17 */ "", 43059 /* IHOST_GICDIST_PRIORITY_LEVEL18 */ "", 43060 /* IHOST_GICDIST_PRIORITY_LEVEL19 */ "", 43061 /* IHOST_GICDIST_PRIORITY_LEVEL20 */ "", 43062 /* IHOST_GICDIST_PRIORITY_LEVEL21 */ "", 43063 /* IHOST_GICDIST_PRIORITY_LEVEL22 */ "", 43064 /* IHOST_GICDIST_PRIORITY_LEVEL23 */ "", 43065 /* IHOST_GICDIST_PRIORITY_LEVEL24 */ "", 43066 /* IHOST_GICDIST_PRIORITY_LEVEL25 */ "", 43067 /* IHOST_GICDIST_PRIORITY_LEVEL26 */ "", 43068 /* IHOST_GICDIST_PRIORITY_LEVEL27 */ "", 43069 /* IHOST_GICDIST_PRIORITY_LEVEL28 */ "", 43070 /* IHOST_GICDIST_PRIORITY_LEVEL29 */ "", 43071 /* IHOST_GICDIST_PRIORITY_LEVEL30 */ "", 43072 /* IHOST_GICDIST_PRIORITY_LEVEL31 */ "", 43073 /* IHOST_GICDIST_PRIORITY_LEVEL32 */ "", 43074 /* IHOST_GICDIST_PRIORITY_LEVEL33 */ "", 43075 /* IHOST_GICDIST_PRIORITY_LEVEL34 */ "", 43076 /* IHOST_GICDIST_PRIORITY_LEVEL35 */ "", 43077 /* IHOST_GICDIST_PRIORITY_LEVEL36 */ "", 43078 /* IHOST_GICDIST_PRIORITY_LEVEL37 */ "", 43079 /* IHOST_GICDIST_PRIORITY_LEVEL38 */ "", 43080 /* IHOST_GICDIST_PRIORITY_LEVEL39 */ "", 43081 /* IHOST_GICDIST_PRIORITY_LEVEL40 */ "", 43082 /* IHOST_GICDIST_PRIORITY_LEVEL41 */ "", 43083 /* IHOST_GICDIST_PRIORITY_LEVEL42 */ "", 43084 /* IHOST_GICDIST_PRIORITY_LEVEL43 */ "", 43085 /* IHOST_GICDIST_PRIORITY_LEVEL44 */ "", 43086 /* IHOST_GICDIST_PRIORITY_LEVEL45 */ "", 43087 /* IHOST_GICDIST_PRIORITY_LEVEL46 */ "", 43088 /* IHOST_GICDIST_PRIORITY_LEVEL47 */ "", 43089 /* IHOST_GICDIST_PRIORITY_LEVEL48 */ "", 43090 /* IHOST_GICDIST_PRIORITY_LEVEL49 */ "", 43091 /* IHOST_GICDIST_PRIORITY_LEVEL50 */ "", 43092 /* IHOST_GICDIST_PRIORITY_LEVEL51 */ "", 43093 /* IHOST_GICDIST_PRIORITY_LEVEL52 */ "", 43094 /* IHOST_GICDIST_PRIORITY_LEVEL53 */ "", 43095 /* IHOST_GICDIST_PRIORITY_LEVEL54 */ "", 43096 /* IHOST_GICDIST_PRIORITY_LEVEL55 */ "", 43097 /* IHOST_GICDIST_PRIORITY_LEVEL56 */ "", 43098 /* IHOST_GICDIST_PRIORITY_LEVEL57 */ "", 43099 /* IHOST_GICDIST_PRIORITY_LEVEL58 */ "", 43100 /* IHOST_GICDIST_PRIORITY_LEVEL59 */ "", 43101 /* IHOST_GICDIST_PRIORITY_LEVEL60 */ "", 43102 /* IHOST_GICDIST_PRIORITY_LEVEL61 */ "", 43103 /* IHOST_GICDIST_PRIORITY_LEVEL62 */ "", 43104 /* IHOST_GICDIST_PRIORITY_LEVEL63 */ "", 43105 /* IHOST_GICDIST_SPI_STATUS0 */ "", 43106 /* IHOST_GICDIST_SPI_STATUS1 */ "", 43107 /* IHOST_GICDIST_SPI_STATUS2 */ "", 43108 /* IHOST_GICDIST_SPI_STATUS3 */ "", 43109 /* IHOST_GICDIST_SPI_STATUS4 */ "", 43110 /* IHOST_GICDIST_SPI_STATUS5 */ "", 43111 /* IHOST_GICDIST_SPI_STATUS6 */ "", 43112 /* IHOST_GICDIST_SPI_TARGET0 */ "", 43113 /* IHOST_GICDIST_SPI_TARGET1 */ "", 43114 /* IHOST_GICDIST_SPI_TARGET2 */ "", 43115 /* IHOST_GICDIST_SPI_TARGET3 */ "", 43116 /* IHOST_GICDIST_SPI_TARGET4 */ "", 43117 /* IHOST_GICDIST_SPI_TARGET5 */ "", 43118 /* IHOST_GICDIST_SPI_TARGET6 */ "", 43119 /* IHOST_GICDIST_SPI_TARGET7 */ "", 43120 /* IHOST_GICDIST_SPI_TARGET8 */ "", 43121 /* IHOST_GICDIST_SPI_TARGET9 */ "", 43122 /* IHOST_GICDIST_SPI_TARGET10 */ "", 43123 /* IHOST_GICDIST_SPI_TARGET11 */ "", 43124 /* IHOST_GICDIST_SPI_TARGET12 */ "", 43125 /* IHOST_GICDIST_SPI_TARGET13 */ "", 43126 /* IHOST_GICDIST_SPI_TARGET14 */ "", 43127 /* IHOST_GICDIST_SPI_TARGET15 */ "", 43128 /* IHOST_GICDIST_SPI_TARGET16 */ "", 43129 /* IHOST_GICDIST_SPI_TARGET17 */ "", 43130 /* IHOST_GICDIST_SPI_TARGET18 */ "", 43131 /* IHOST_GICDIST_SPI_TARGET19 */ "", 43132 /* IHOST_GICDIST_SPI_TARGET20 */ "", 43133 /* IHOST_GICDIST_SPI_TARGET21 */ "", 43134 /* IHOST_GICDIST_SPI_TARGET22 */ "", 43135 /* IHOST_GICDIST_SPI_TARGET23 */ "", 43136 /* IHOST_GICDIST_SPI_TARGET24 */ "", 43137 /* IHOST_GICDIST_SPI_TARGET25 */ "", 43138 /* IHOST_GICDIST_SPI_TARGET26 */ "", 43139 /* IHOST_GICDIST_SPI_TARGET27 */ "", 43140 /* IHOST_GICDIST_SPI_TARGET28 */ "", 43141 /* IHOST_GICDIST_SPI_TARGET29 */ "", 43142 /* IHOST_GICDIST_SPI_TARGET30 */ "", 43143 /* IHOST_GICDIST_SPI_TARGET31 */ "", 43144 /* IHOST_GICDIST_SPI_TARGET32 */ "", 43145 /* IHOST_GICDIST_SPI_TARGET33 */ "", 43146 /* IHOST_GICDIST_SPI_TARGET34 */ "", 43147 /* IHOST_GICDIST_SPI_TARGET35 */ "", 43148 /* IHOST_GICDIST_SPI_TARGET36 */ "", 43149 /* IHOST_GICDIST_SPI_TARGET37 */ "", 43150 /* IHOST_GICDIST_SPI_TARGET38 */ "", 43151 /* IHOST_GICDIST_SPI_TARGET39 */ "", 43152 /* IHOST_GICDIST_SPI_TARGET40 */ "", 43153 /* IHOST_GICDIST_SPI_TARGET41 */ "", 43154 /* IHOST_GICDIST_SPI_TARGET42 */ "", 43155 /* IHOST_GICDIST_SPI_TARGET43 */ "", 43156 /* IHOST_GICDIST_SPI_TARGET44 */ "", 43157 /* IHOST_GICDIST_SPI_TARGET45 */ "", 43158 /* IHOST_GICDIST_SPI_TARGET46 */ "", 43159 /* IHOST_GICDIST_SPI_TARGET47 */ "", 43160 /* IHOST_GICDIST_SPI_TARGET48 */ "", 43161 /* IHOST_GICDIST_SPI_TARGET49 */ "", 43162 /* IHOST_GICDIST_SPI_TARGET50 */ "", 43163 /* IHOST_GICDIST_SPI_TARGET51 */ "", 43164 /* IHOST_GICDIST_SPI_TARGET52 */ "", 43165 /* IHOST_GICDIST_SPI_TARGET53 */ "", 43166 /* IHOST_GICDIST_SPI_TARGET54 */ "", 43167 /* IHOST_GICDIST_SPI_TARGET55 */ "", 43168 /* IHOST_GICDIST_SPI_TARGET56 */ "", 43169 /* IHOST_GICDIST_SPI_TARGET57 */ "", 43170 /* IHOST_GICDIST_SPI_TARGET58 */ "", 43171 /* IHOST_GICDIST_SPI_TARGET59 */ "", 43172 /* IHOST_GICDIST_SPI_TARGET60 */ "", 43173 /* IHOST_GICDIST_SPI_TARGET61 */ "", 43174 /* IHOST_GICDIST_SPI_TARGET62 */ "", 43175 /* IHOST_GICDIST_SPI_TARGET63 */ "", 43176 /* IHOST_GICDIST_STI_CONTROL */ "", 43177 /* IHOST_GICTR_GIC_CMD */ "", 43178 /* IHOST_GICTR_GIC_CONFIG */ "", 43179 /* IHOST_GICTR_GIC_FIQ_LAT0 */ "", 43180 /* IHOST_GICTR_GIC_FIQ_LAT1 */ "", 43181 /* IHOST_GICTR_GIC_IRQ_LAT0 */ "", 43182 /* IHOST_GICTR_GIC_IRQ_LAT1 */ "", 43183 /* IHOST_GICTR_GIC_OUTIDS */ "", 43184 /* IHOST_GICTR_GIC_STATUS */ "", 43185 /* IHOST_GIC_GIC400_GICC_ABPR */ "", 43186 /* IHOST_GIC_GIC400_GICC_AEOIR */ "", 43187 /* IHOST_GIC_GIC400_GICC_AHPPIR */ "", 43188 /* IHOST_GIC_GIC400_GICC_AIAR */ "", 43189 /* IHOST_GIC_GIC400_GICC_APR0 */ "", 43190 /* IHOST_GIC_GIC400_GICC_BPR */ "", 43191 /* IHOST_GIC_GIC400_GICC_CTLR */ "", 43192 /* IHOST_GIC_GIC400_GICC_DIR */ "", 43193 /* IHOST_GIC_GIC400_GICC_EOIR */ "", 43194 /* IHOST_GIC_GIC400_GICC_HPPIR */ "", 43195 /* IHOST_GIC_GIC400_GICC_IAR */ "", 43196 /* IHOST_GIC_GIC400_GICC_IIDR */ "", 43197 /* IHOST_GIC_GIC400_GICC_NSAPR0 */ "", 43198 /* IHOST_GIC_GIC400_GICC_PMR */ "", 43199 /* IHOST_GIC_GIC400_GICC_RPR */ "", 43200 /* IHOST_GIC_GIC400_GICD_CIDR0 */ "", 43201 /* IHOST_GIC_GIC400_GICD_CIDR1 */ "", 43202 /* IHOST_GIC_GIC400_GICD_CIDR2 */ "", 43203 /* IHOST_GIC_GIC400_GICD_CIDR3 */ "", 43204 /* IHOST_GIC_GIC400_GICD_CPENDSGIRN_0 */ "", 43205 /* IHOST_GIC_GIC400_GICD_CPENDSGIRN_1 */ "", 43206 /* IHOST_GIC_GIC400_GICD_CPENDSGIRN_2 */ "", 43207 /* IHOST_GIC_GIC400_GICD_CPENDSGIRN_3 */ "", 43208 /* IHOST_GIC_GIC400_GICD_CTLR */ "", 43209 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_0 */ "", 43210 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_1 */ "", 43211 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_2 */ "", 43212 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_3 */ "", 43213 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_4 */ "", 43214 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_5 */ "", 43215 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_6 */ "", 43216 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_7 */ "", 43217 /* IHOST_GIC_GIC400_GICD_ICACTIVERN_8 */ "", 43218 /* IHOST_GIC_GIC400_GICD_ICENABLERN_0 */ "", 43219 /* IHOST_GIC_GIC400_GICD_ICENABLERN_1 */ "", 43220 /* IHOST_GIC_GIC400_GICD_ICENABLERN_2 */ "", 43221 /* IHOST_GIC_GIC400_GICD_ICENABLERN_3 */ "", 43222 /* IHOST_GIC_GIC400_GICD_ICENABLERN_4 */ "", 43223 /* IHOST_GIC_GIC400_GICD_ICENABLERN_5 */ "", 43224 /* IHOST_GIC_GIC400_GICD_ICENABLERN_6 */ "", 43225 /* IHOST_GIC_GIC400_GICD_ICENABLERN_7 */ "", 43226 /* IHOST_GIC_GIC400_GICD_ICENABLERN_8 */ "", 43227 /* IHOST_GIC_GIC400_GICD_ICFGRN_0 */ "", 43228 /* IHOST_GIC_GIC400_GICD_ICFGRN_1 */ "", 43229 /* IHOST_GIC_GIC400_GICD_ICFGRN_2 */ "", 43230 /* IHOST_GIC_GIC400_GICD_ICFGRN_3 */ "", 43231 /* IHOST_GIC_GIC400_GICD_ICFGRN_4 */ "", 43232 /* IHOST_GIC_GIC400_GICD_ICFGRN_5 */ "", 43233 /* IHOST_GIC_GIC400_GICD_ICFGRN_6 */ "", 43234 /* IHOST_GIC_GIC400_GICD_ICFGRN_7 */ "", 43235 /* IHOST_GIC_GIC400_GICD_ICFGRN_8 */ "", 43236 /* IHOST_GIC_GIC400_GICD_ICFGRN_9 */ "", 43237 /* IHOST_GIC_GIC400_GICD_ICFGRN_10 */ "", 43238 /* IHOST_GIC_GIC400_GICD_ICFGRN_11 */ "", 43239 /* IHOST_GIC_GIC400_GICD_ICFGRN_12 */ "", 43240 /* IHOST_GIC_GIC400_GICD_ICFGRN_13 */ "", 43241 /* IHOST_GIC_GIC400_GICD_ICFGRN_14 */ "", 43242 /* IHOST_GIC_GIC400_GICD_ICFGRN_15 */ "", 43243 /* IHOST_GIC_GIC400_GICD_ICFGRN_16 */ "", 43244 /* IHOST_GIC_GIC400_GICD_ICFGRN_17 */ "", 43245 /* IHOST_GIC_GIC400_GICD_ICPENDRN_0 */ "", 43246 /* IHOST_GIC_GIC400_GICD_ICPENDRN_1 */ "", 43247 /* IHOST_GIC_GIC400_GICD_ICPENDRN_2 */ "", 43248 /* IHOST_GIC_GIC400_GICD_ICPENDRN_3 */ "", 43249 /* IHOST_GIC_GIC400_GICD_ICPENDRN_4 */ "", 43250 /* IHOST_GIC_GIC400_GICD_ICPENDRN_5 */ "", 43251 /* IHOST_GIC_GIC400_GICD_ICPENDRN_6 */ "", 43252 /* IHOST_GIC_GIC400_GICD_ICPENDRN_7 */ "", 43253 /* IHOST_GIC_GIC400_GICD_ICPENDRN_8 */ "", 43254 /* IHOST_GIC_GIC400_GICD_IGROUPRN_0 */ "", 43255 /* IHOST_GIC_GIC400_GICD_IGROUPRN_1 */ "", 43256 /* IHOST_GIC_GIC400_GICD_IGROUPRN_2 */ "", 43257 /* IHOST_GIC_GIC400_GICD_IGROUPRN_3 */ "", 43258 /* IHOST_GIC_GIC400_GICD_IGROUPRN_4 */ "", 43259 /* IHOST_GIC_GIC400_GICD_IGROUPRN_5 */ "", 43260 /* IHOST_GIC_GIC400_GICD_IGROUPRN_6 */ "", 43261 /* IHOST_GIC_GIC400_GICD_IGROUPRN_7 */ "", 43262 /* IHOST_GIC_GIC400_GICD_IGROUPRN_8 */ "", 43263 /* IHOST_GIC_GIC400_GICD_IIDR */ "", 43264 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_0 */ "", 43265 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_1 */ "", 43266 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_2 */ "", 43267 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_3 */ "", 43268 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_4 */ "", 43269 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_5 */ "", 43270 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_6 */ "", 43271 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_7 */ "", 43272 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_8 */ "", 43273 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_9 */ "", 43274 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_10 */ "", 43275 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_11 */ "", 43276 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_12 */ "", 43277 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_13 */ "", 43278 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_14 */ "", 43279 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_15 */ "", 43280 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_16 */ "", 43281 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_17 */ "", 43282 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_18 */ "", 43283 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_19 */ "", 43284 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_20 */ "", 43285 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_21 */ "", 43286 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_22 */ "", 43287 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_23 */ "", 43288 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_24 */ "", 43289 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_25 */ "", 43290 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_26 */ "", 43291 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_27 */ "", 43292 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_28 */ "", 43293 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_29 */ "", 43294 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_30 */ "", 43295 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_31 */ "", 43296 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_32 */ "", 43297 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_33 */ "", 43298 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_34 */ "", 43299 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_35 */ "", 43300 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_36 */ "", 43301 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_37 */ "", 43302 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_38 */ "", 43303 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_39 */ "", 43304 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_40 */ "", 43305 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_41 */ "", 43306 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_42 */ "", 43307 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_43 */ "", 43308 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_44 */ "", 43309 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_45 */ "", 43310 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_46 */ "", 43311 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_47 */ "", 43312 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_48 */ "", 43313 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_49 */ "", 43314 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_50 */ "", 43315 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_51 */ "", 43316 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_52 */ "", 43317 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_53 */ "", 43318 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_54 */ "", 43319 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_55 */ "", 43320 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_56 */ "", 43321 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_57 */ "", 43322 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_58 */ "", 43323 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_59 */ "", 43324 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_60 */ "", 43325 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_61 */ "", 43326 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_62 */ "", 43327 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_63 */ "", 43328 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_64 */ "", 43329 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_65 */ "", 43330 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_66 */ "", 43331 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_67 */ "", 43332 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_68 */ "", 43333 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_69 */ "", 43334 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_70 */ "", 43335 /* IHOST_GIC_GIC400_GICD_IPRIORITYRN_71 */ "", 43336 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_0 */ "", 43337 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_1 */ "", 43338 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_2 */ "", 43339 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_3 */ "", 43340 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_4 */ "", 43341 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_5 */ "", 43342 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_6 */ "", 43343 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_7 */ "", 43344 /* IHOST_GIC_GIC400_GICD_ISACTIVERN_8 */ "", 43345 /* IHOST_GIC_GIC400_GICD_ISENABLERN_0 */ "", 43346 /* IHOST_GIC_GIC400_GICD_ISENABLERN_1 */ "", 43347 /* IHOST_GIC_GIC400_GICD_ISENABLERN_2 */ "", 43348 /* IHOST_GIC_GIC400_GICD_ISENABLERN_3 */ "", 43349 /* IHOST_GIC_GIC400_GICD_ISENABLERN_4 */ "", 43350 /* IHOST_GIC_GIC400_GICD_ISENABLERN_5 */ "", 43351 /* IHOST_GIC_GIC400_GICD_ISENABLERN_6 */ "", 43352 /* IHOST_GIC_GIC400_GICD_ISENABLERN_7 */ "", 43353 /* IHOST_GIC_GIC400_GICD_ISENABLERN_8 */ "", 43354 /* IHOST_GIC_GIC400_GICD_ISPENDRN_0 */ "", 43355 /* IHOST_GIC_GIC400_GICD_ISPENDRN_1 */ "", 43356 /* IHOST_GIC_GIC400_GICD_ISPENDRN_2 */ "", 43357 /* IHOST_GIC_GIC400_GICD_ISPENDRN_3 */ "", 43358 /* IHOST_GIC_GIC400_GICD_ISPENDRN_4 */ "", 43359 /* IHOST_GIC_GIC400_GICD_ISPENDRN_5 */ "", 43360 /* IHOST_GIC_GIC400_GICD_ISPENDRN_6 */ "", 43361 /* IHOST_GIC_GIC400_GICD_ISPENDRN_7 */ "", 43362 /* IHOST_GIC_GIC400_GICD_ISPENDRN_8 */ "", 43363 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_0 */ "", 43364 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_1 */ "", 43365 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_2 */ "", 43366 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_3 */ "", 43367 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_4 */ "", 43368 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_5 */ "", 43369 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_6 */ "", 43370 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_7 */ "", 43371 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_8 */ "", 43372 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_9 */ "", 43373 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_10 */ "", 43374 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_11 */ "", 43375 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_12 */ "", 43376 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_13 */ "", 43377 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_14 */ "", 43378 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_15 */ "", 43379 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_16 */ "", 43380 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_17 */ "", 43381 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_18 */ "", 43382 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_19 */ "", 43383 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_20 */ "", 43384 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_21 */ "", 43385 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_22 */ "", 43386 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_23 */ "", 43387 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_24 */ "", 43388 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_25 */ "", 43389 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_26 */ "", 43390 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_27 */ "", 43391 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_28 */ "", 43392 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_29 */ "", 43393 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_30 */ "", 43394 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_31 */ "", 43395 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_32 */ "", 43396 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_33 */ "", 43397 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_34 */ "", 43398 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_35 */ "", 43399 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_36 */ "", 43400 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_37 */ "", 43401 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_38 */ "", 43402 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_39 */ "", 43403 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_40 */ "", 43404 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_41 */ "", 43405 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_42 */ "", 43406 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_43 */ "", 43407 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_44 */ "", 43408 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_45 */ "", 43409 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_46 */ "", 43410 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_47 */ "", 43411 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_48 */ "", 43412 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_49 */ "", 43413 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_50 */ "", 43414 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_51 */ "", 43415 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_52 */ "", 43416 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_53 */ "", 43417 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_54 */ "", 43418 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_55 */ "", 43419 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_56 */ "", 43420 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_57 */ "", 43421 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_58 */ "", 43422 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_59 */ "", 43423 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_60 */ "", 43424 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_61 */ "", 43425 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_62 */ "", 43426 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_63 */ "", 43427 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_64 */ "", 43428 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_65 */ "", 43429 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_66 */ "", 43430 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_67 */ "", 43431 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_68 */ "", 43432 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_69 */ "", 43433 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_70 */ "", 43434 /* IHOST_GIC_GIC400_GICD_ITARGETSRN_71 */ "", 43435 /* IHOST_GIC_GIC400_GICD_PIDR0 */ "", 43436 /* IHOST_GIC_GIC400_GICD_PIDR1 */ "", 43437 /* IHOST_GIC_GIC400_GICD_PIDR2 */ "", 43438 /* IHOST_GIC_GIC400_GICD_PIDR3 */ "", 43439 /* IHOST_GIC_GIC400_GICD_PIDR4 */ "", 43440 /* IHOST_GIC_GIC400_GICD_PIDR5 */ "", 43441 /* IHOST_GIC_GIC400_GICD_PIDR6 */ "", 43442 /* IHOST_GIC_GIC400_GICD_PIDR7 */ "", 43443 /* IHOST_GIC_GIC400_GICD_PPISR */ "", 43444 /* IHOST_GIC_GIC400_GICD_SGIR */ "", 43445 /* IHOST_GIC_GIC400_GICD_SPENDSGIRN_0 */ "", 43446 /* IHOST_GIC_GIC400_GICD_SPENDSGIRN_1 */ "", 43447 /* IHOST_GIC_GIC400_GICD_SPENDSGIRN_2 */ "", 43448 /* IHOST_GIC_GIC400_GICD_SPENDSGIRN_3 */ "", 43449 /* IHOST_GIC_GIC400_GICD_SPISRN_0 */ "", 43450 /* IHOST_GIC_GIC400_GICD_SPISRN_1 */ "", 43451 /* IHOST_GIC_GIC400_GICD_SPISRN_2 */ "", 43452 /* IHOST_GIC_GIC400_GICD_SPISRN_3 */ "", 43453 /* IHOST_GIC_GIC400_GICD_SPISRN_4 */ "", 43454 /* IHOST_GIC_GIC400_GICD_SPISRN_5 */ "", 43455 /* IHOST_GIC_GIC400_GICD_SPISRN_6 */ "", 43456 /* IHOST_GIC_GIC400_GICD_SPISRN_7 */ "", 43457 /* IHOST_GIC_GIC400_GICD_SPISRN_8 */ "", 43458 /* IHOST_GIC_GIC400_GICD_SPISRN_9 */ "", 43459 /* IHOST_GIC_GIC400_GICD_SPISRN_10 */ "", 43460 /* IHOST_GIC_GIC400_GICD_SPISRN_11 */ "", 43461 /* IHOST_GIC_GIC400_GICD_SPISRN_12 */ "", 43462 /* IHOST_GIC_GIC400_GICD_SPISRN_13 */ "", 43463 /* IHOST_GIC_GIC400_GICD_SPISRN_14 */ "", 43464 /* IHOST_GIC_GIC400_GICD_TYPER */ "", 43465 /* IHOST_GIC_GIC400_GICH_APR0 */ "", 43466 /* IHOST_GIC_GIC400_GICH_APR0_CPU0 */ "", 43467 /* IHOST_GIC_GIC400_GICH_EISR0 */ "", 43468 /* IHOST_GIC_GIC400_GICH_EISR0_CPU0 */ "", 43469 /* IHOST_GIC_GIC400_GICH_ELSR0 */ "", 43470 /* IHOST_GIC_GIC400_GICH_ELSR0_CPU0 */ "", 43471 /* IHOST_GIC_GIC400_GICH_HCR */ "", 43472 /* IHOST_GIC_GIC400_GICH_HCR_CPU0 */ "", 43473 /* IHOST_GIC_GIC400_GICH_LR0 */ "", 43474 /* IHOST_GIC_GIC400_GICH_LR1 */ "", 43475 /* IHOST_GIC_GIC400_GICH_LR2 */ "", 43476 /* IHOST_GIC_GIC400_GICH_LR3 */ "", 43477 /* IHOST_GIC_GIC400_GICH_LR0_CPU0 */ "", 43478 /* IHOST_GIC_GIC400_GICH_LR1_CPU0 */ "", 43479 /* IHOST_GIC_GIC400_GICH_LR2_CPU0 */ "", 43480 /* IHOST_GIC_GIC400_GICH_LR3_CPU0 */ "", 43481 /* IHOST_GIC_GIC400_GICH_MISR */ "", 43482 /* IHOST_GIC_GIC400_GICH_MISR_CPU0 */ "", 43483 /* IHOST_GIC_GIC400_GICH_VMCR */ "", 43484 /* IHOST_GIC_GIC400_GICH_VMCR_CPU0 */ "", 43485 /* IHOST_GIC_GIC400_GICH_VTR */ "", 43486 /* IHOST_GIC_GIC400_GICH_VTR_CPU0 */ "", 43487 /* IHOST_GIC_GIC400_GICV_ABPR */ "", 43488 /* IHOST_GIC_GIC400_GICV_AEOIR */ "", 43489 /* IHOST_GIC_GIC400_GICV_AHPPIR */ "", 43490 /* IHOST_GIC_GIC400_GICV_AIAR */ "", 43491 /* IHOST_GIC_GIC400_GICV_APR0 */ "", 43492 /* IHOST_GIC_GIC400_GICV_BPR */ "", 43493 /* IHOST_GIC_GIC400_GICV_CTLR */ "", 43494 /* IHOST_GIC_GIC400_GICV_DIR */ "", 43495 /* IHOST_GIC_GIC400_GICV_EOIR */ "", 43496 /* IHOST_GIC_GIC400_GICV_HPPIR */ "", 43497 /* IHOST_GIC_GIC400_GICV_IAR */ "", 43498 /* IHOST_GIC_GIC400_GICV_IIDR */ "", 43499 /* IHOST_GIC_GIC400_GICV_PMR */ "", 43500 /* IHOST_GIC_GIC400_GICV_RPR */ "", 43501 /* IHOST_GTIM_GLOB_COMP_HI */ "", 43502 /* IHOST_GTIM_GLOB_COMP_LOW */ "", 43503 /* IHOST_GTIM_GLOB_CTRL */ "", 43504 /* IHOST_GTIM_GLOB_HI */ "", 43505 /* IHOST_GTIM_GLOB_INCR */ "", 43506 /* IHOST_GTIM_GLOB_LOW */ "", 43507 /* IHOST_GTIM_GLOB_STATUS */ "", 43508 /* IHOST_ICFG_CONFIG_CONTROL */ "", 43509 /* IHOST_ICFG_EXT_INTR_VECTOR_0 */ "", 43510 /* IHOST_ICFG_EXT_INTR_VECTOR_1 */ "", 43511 /* IHOST_ICFG_EXT_INTR_VECTOR_2 */ "", 43512 /* IHOST_ICFG_EXT_INTR_VECTOR_3 */ "", 43513 /* IHOST_ICFG_EXT_INTR_VECTOR_4 */ "", 43514 /* IHOST_ICFG_EXT_INTR_VECTOR_5 */ "", 43515 /* IHOST_ICFG_EXT_INTR_VECTOR_6 */ "", 43516 /* IHOST_ICFG_MEM_TM_CONTROL */ "", 43517 /* IHOST_ICFG_OVERRIDE_CONTROL */ "", 43518 /* IHOST_ICFG_RVBARADDR_LSB */ "", 43519 /* IHOST_ICFG_RVBARADDR_MSB */ "", 43520 /* IHOST_ICFG_SSI_DEBUG_CONTROL */ "", 43521 /* IHOST_ICFG_SSI_DEBUG_STATUS */ "", 43522 /* IHOST_ICFG_SW_PROG_INTR_CLR */ "", 43523 /* IHOST_ICFG_SW_PROG_INTR_ENABLE */ "", 43524 /* IHOST_ICFG_SW_PROG_INTR_SET */ "", 43525 /* IHOST_ICFG_SW_PROG_INTR_STATUS */ "", 43526 /* IHOST_L2C_AUX_CONTROL */ "", 43527 /* IHOST_L2C_CACHE_ID */ "", 43528 /* IHOST_L2C_CACHE_SYNC */ "", 43529 /* IHOST_L2C_CACHE_TYPE */ "", 43530 /* IHOST_L2C_CLEAN_INDEX_WAY */ "", 43531 /* IHOST_L2C_CLEAN_PA */ "", 43532 /* IHOST_L2C_CLEAN_WAY */ "", 43533 /* IHOST_L2C_CONTROL */ "", 43534 /* IHOST_L2C_C_I_INDEX_WAY */ "", 43535 /* IHOST_L2C_C_I_PA */ "", 43536 /* IHOST_L2C_C_I_WAY */ "", 43537 /* IHOST_L2C_DATA_LOCKDOWN */ "", 43538 /* IHOST_L2C_DATA_RAM_CTRL */ "", 43539 /* IHOST_L2C_DEBUG_CTRL */ "", 43540 /* IHOST_L2C_EVENT_CTR0 */ "", 43541 /* IHOST_L2C_EVENT_CTR1 */ "", 43542 /* IHOST_L2C_EVENT_CTR_CFG0 */ "", 43543 /* IHOST_L2C_EVENT_CTR_CFG1 */ "", 43544 /* IHOST_L2C_EVENT_CTR_CTRL */ "", 43545 /* IHOST_L2C_FILT_END */ "", 43546 /* IHOST_L2C_FILT_START */ "", 43547 /* IHOST_L2C_INSTR_LOCKDOWN */ "", 43548 /* IHOST_L2C_INT_CLEAR */ "", 43549 /* IHOST_L2C_INT_MASK */ "", 43550 /* IHOST_L2C_INT_RAW_STATUS */ "", 43551 /* IHOST_L2C_INT_STATUS */ "", 43552 /* IHOST_L2C_INV_PA */ "", 43553 /* IHOST_L2C_INV_WAY */ "", 43554 /* IHOST_L2C_LOCK_LINE_EN */ "", 43555 /* IHOST_L2C_PREFETCH_OFFS */ "", 43556 /* IHOST_L2C_PWR_CTRL */ "", 43557 /* IHOST_L2C_TAG_RAM_CTRL */ "", 43558 /* IHOST_L2C_UNLOCK_WAY */ "", 43559 /* IHOST_M0_IDM_IDM_INTERRUPT_STATUS */ "", 43560 /* IHOST_M0_IDM_IDM_IO_CONTROL_DIRECT */ "", 43561 /* IHOST_M0_IDM_IDM_IO_STATUS */ "", 43562 /* IHOST_M0_IDM_IDM_RESET_CONTROL */ "", 43563 /* IHOST_M0_IDM_IDM_RESET_STATUS */ "", 43564 /* IHOST_M0_IDM_INTERRUPT_STATUS */ "", 43565 /* IHOST_M0_IDM_RESET_STATUS */ "", 43566 /* IHOST_M0_IO_CONTROL_DIRECT */ "", 43567 /* IHOST_M0_IO_STATUS */ "", 43568 /* IHOST_M0_RESET_CONTROL */ "", 43569 /* IHOST_M1_IDM_INTERRUPT_STATUS */ "", 43570 /* IHOST_M1_IDM_RESET_CONTROL */ "", 43571 /* IHOST_M1_IDM_RESET_STATUS */ "", 43572 /* IHOST_NIC_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 43573 /* IHOST_NIC_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 43574 /* IHOST_NIC_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 43575 /* IHOST_NIC_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 43576 /* IHOST_NIC_S0_IDM_IDM_ERROR_LOG_ID */ "", 43577 /* IHOST_NIC_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 43578 /* IHOST_NIC_S0_IDM_IDM_INTERRUPT_STATUS */ "", 43579 /* IHOST_NIC_S0_IDM_IDM_IO_CONTROL_DIRECT */ "", 43580 /* IHOST_NIC_S0_IDM_IDM_IO_STATUS */ "", 43581 /* IHOST_NIC_S0_IDM_IDM_RESET_CONTROL */ "", 43582 /* IHOST_NIC_S0_IDM_IDM_RESET_READ_ID */ "", 43583 /* IHOST_NIC_S0_IDM_IDM_RESET_STATUS */ "", 43584 /* IHOST_NIC_S0_IDM_IDM_RESET_WRITE_ID */ "", 43585 /* IHOST_PROC_CLK_ACTIVITY_MON1 */ "", 43586 /* IHOST_PROC_CLK_ACTIVITY_MON2 */ "", 43587 /* IHOST_PROC_CLK_APB0_CLKGATE */ "", 43588 /* IHOST_PROC_CLK_APB_CLKGATE_DBG1 */ "", 43589 /* IHOST_PROC_CLK_APB_DIV */ "", 43590 /* IHOST_PROC_CLK_APB_DIV_TRIGGER */ "", 43591 /* IHOST_PROC_CLK_ARM_DIV */ "", 43592 /* IHOST_PROC_CLK_ARM_PERIPH_CLKGATE */ "", 43593 /* IHOST_PROC_CLK_ARM_SEG_TRG */ "", 43594 /* IHOST_PROC_CLK_ARM_SEG_TRG_OVERRIDE */ "", 43595 /* IHOST_PROC_CLK_ARM_SWITCH_CLKGATE */ "", 43596 /* IHOST_PROC_CLK_ARM_SWITCH_DIV */ "", 43597 /* IHOST_PROC_CLK_ARM_SWITCH_TRIGGER */ "", 43598 /* IHOST_PROC_CLK_BUS_QUIESC */ "", 43599 /* IHOST_PROC_CLK_CLKGATE_DBG */ "", 43600 /* IHOST_PROC_CLK_CLKMON */ "", 43601 /* IHOST_PROC_CLK_CORE0_CLKGATE */ "", 43602 /* IHOST_PROC_CLK_CORE1_CLKGATE */ "", 43603 /* IHOST_PROC_CLK_INTEN */ "", 43604 /* IHOST_PROC_CLK_INTSTAT */ "", 43605 /* IHOST_PROC_CLK_KPROC_CCU_PROF_CNT */ "", 43606 /* IHOST_PROC_CLK_KPROC_CCU_PROF_CTL */ "", 43607 /* IHOST_PROC_CLK_KPROC_CCU_PROF_DBG */ "", 43608 /* IHOST_PROC_CLK_KPROC_CCU_PROF_SEL */ "", 43609 /* IHOST_PROC_CLK_LVM0_3 */ "", 43610 /* IHOST_PROC_CLK_LVM4_7 */ "", 43611 /* IHOST_PROC_CLK_LVM_EN */ "", 43612 /* IHOST_PROC_CLK_PL310_DIV */ "", 43613 /* IHOST_PROC_CLK_PL310_TRIGGER */ "", 43614 /* IHOST_PROC_CLK_PLLARMA */ "", 43615 /* IHOST_PROC_CLK_PLLARMB */ "", 43616 /* IHOST_PROC_CLK_PLLARMC */ "", 43617 /* IHOST_PROC_CLK_PLLARMCTRL0 */ "", 43618 /* IHOST_PROC_CLK_PLLARMCTRL1 */ "", 43619 /* IHOST_PROC_CLK_PLLARMCTRL2 */ "", 43620 /* IHOST_PROC_CLK_PLLARMCTRL3 */ "", 43621 /* IHOST_PROC_CLK_PLLARMCTRL4 */ "", 43622 /* IHOST_PROC_CLK_PLLARMCTRL5 */ "", 43623 /* IHOST_PROC_CLK_PLLARM_OFFSET */ "", 43624 /* IHOST_PROC_CLK_PLL_DEBUG */ "", 43625 /* IHOST_PROC_CLK_POLICY0_MASK */ "", 43626 /* IHOST_PROC_CLK_POLICY1_MASK */ "", 43627 /* IHOST_PROC_CLK_POLICY2_MASK */ "", 43628 /* IHOST_PROC_CLK_POLICY3_MASK */ "", 43629 /* IHOST_PROC_CLK_POLICY_CTL */ "", 43630 /* IHOST_PROC_CLK_POLICY_DBG */ "", 43631 /* IHOST_PROC_CLK_POLICY_FREQ */ "", 43632 /* IHOST_PROC_CLK_TGTMASK_DBG1 */ "", 43633 /* IHOST_PROC_CLK_VLT0_3 */ "", 43634 /* IHOST_PROC_CLK_VLT4_7 */ "", 43635 /* IHOST_PROC_CLK_WR_ACCESS */ "", 43636 /* IHOST_PROC_RST_A9_CORE_SOFT_RSTN */ "", 43637 /* IHOST_PROC_RST_SOFT_RSTN */ "", 43638 /* IHOST_PROC_RST_WR_ACCESS */ "", 43639 /* IHOST_PTIM_TIMER_COUNTER */ "", 43640 /* IHOST_PTIM_TIMER_CTRL */ "", 43641 /* IHOST_PTIM_TIMER_LOAD */ "", 43642 /* IHOST_PTIM_TIMER_STATUS */ "", 43643 /* IHOST_PTIM_WATCHDOG_COUNTER */ "", 43644 /* IHOST_PTIM_WATCHDOG_CTRL */ "", 43645 /* IHOST_PTIM_WATCHDOG_DISABLE */ "", 43646 /* IHOST_PTIM_WATCHDOG_LOAD */ "", 43647 /* IHOST_PTIM_WATCHDOG_RESET_STATUS */ "", 43648 /* IHOST_PTIM_WATCHDOG_STATUS */ "", 43649 /* IHOST_PWRWDOG0_IRDROP_CNT */ "", 43650 /* IHOST_PWRWDOG0_IRDROP_CTRL */ "", 43651 /* IHOST_PWRWDOG0_PWRWDOG_ACCU_CTRL */ "", 43652 /* IHOST_PWRWDOG0_PWRWDOG_ACCU_STAT */ "", 43653 /* IHOST_PWRWDOG0_PWRWDOG_CTRL */ "", 43654 /* IHOST_PWRWDOG0_PWRWDOG_DLYEN_CNT */ "", 43655 /* IHOST_PWRWDOG0_PWRWDOG_STAT */ "", 43656 /* IHOST_PWRWDOG0_PWRWDOG_STAT_CNT */ "", 43657 /* IHOST_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 43658 /* IHOST_S0_IDM_ERROR_LOG_COMPLETE */ "", 43659 /* IHOST_S0_IDM_ERROR_LOG_CONTROL */ "", 43660 /* IHOST_S0_IDM_ERROR_LOG_FLAGS */ "", 43661 /* IHOST_S0_IDM_ERROR_LOG_ID */ "", 43662 /* IHOST_S0_IDM_ERROR_LOG_STATUS */ "", 43663 /* IHOST_S0_IDM_INTERRUPT_STATUS */ "", 43664 /* IHOST_S0_IDM_RESET_READ_ID */ "", 43665 /* IHOST_S0_IDM_RESET_STATUS */ "", 43666 /* IHOST_S0_IDM_RESET_WRITE_ID */ "", 43667 /* IHOST_S0_IO_CONTROL_DIRECT */ "", 43668 /* IHOST_S0_IO_STATUS */ "", 43669 /* IHOST_S0_RESET_CONTROL */ "", 43670 /* IHOST_S1_IDM_ERROR_LOG_ADDR_LSB */ "", 43671 /* IHOST_S1_IDM_ERROR_LOG_COMPLETE */ "", 43672 /* IHOST_S1_IDM_ERROR_LOG_CONTROL */ "", 43673 /* IHOST_S1_IDM_ERROR_LOG_FLAGS */ "", 43674 /* IHOST_S1_IDM_ERROR_LOG_ID */ "", 43675 /* IHOST_S1_IDM_ERROR_LOG_STATUS */ "", 43676 /* IHOST_S1_IDM_INTERRUPT_STATUS */ "", 43677 /* IHOST_S1_IDM_RESET_READ_ID */ "", 43678 /* IHOST_S1_IDM_RESET_STATUS */ "", 43679 /* IHOST_S1_IDM_RESET_WRITE_ID */ "", 43680 /* IHOST_S1_IO_CONTROL_DIRECT */ "", 43681 /* IHOST_S1_IO_STATUS */ "", 43682 /* IHOST_S1_RESET_CONTROL */ "", 43683 /* IHOST_SCU_ACCESS_CONTROL */ "", 43684 /* IHOST_SCU_CONFIG */ "", 43685 /* IHOST_SCU_CONTROL */ "", 43686 /* IHOST_SCU_FILTER_END */ "", 43687 /* IHOST_SCU_FILTER_START */ "", 43688 /* IHOST_SCU_INVALIDATE_ALL */ "", 43689 /* IHOST_SCU_POWER_STATUS */ "", 43690 /* IHOST_SCU_SECURE_ACCESS */ "", 43691 /* IHOST_SECTRAP_M0_TRAP_ADDRESS */ "", 43692 /* IHOST_SECTRAP_M0_TRAP_CONFIG */ "", 43693 /* IHOST_SECTRAP_M0_TRAP_STATUS */ "", 43694 /* IHOST_SECTRAP_M1_TRAP_ADDRESS */ "", 43695 /* IHOST_SECTRAP_M1_TRAP_CONFIG */ "", 43696 /* IHOST_SECTRAP_M1_TRAP_STATUS */ "", 43697 /* IHOST_SWSTM_R_CONFIG */ "", 43698 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN00 */ "", 43699 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN01 */ "", 43700 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN02 */ "", 43701 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN03 */ "", 43702 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN04 */ "", 43703 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN05 */ "", 43704 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN06 */ "", 43705 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN07 */ "", 43706 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN08 */ "", 43707 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN09 */ "", 43708 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN10 */ "", 43709 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN11 */ "", 43710 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN12 */ "", 43711 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN13 */ "", 43712 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN14 */ "", 43713 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN15 */ "", 43714 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN16 */ "", 43715 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN17 */ "", 43716 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN18 */ "", 43717 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN19 */ "", 43718 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN20 */ "", 43719 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN21 */ "", 43720 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN22 */ "", 43721 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN23 */ "", 43722 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN24 */ "", 43723 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN25 */ "", 43724 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN26 */ "", 43725 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN27 */ "", 43726 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN28 */ "", 43727 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN29 */ "", 43728 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN30 */ "", 43729 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN31 */ "", 43730 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN32 */ "", 43731 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN33 */ "", 43732 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN34 */ "", 43733 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN35 */ "", 43734 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN36 */ "", 43735 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN37 */ "", 43736 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN38 */ "", 43737 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN39 */ "", 43738 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN40 */ "", 43739 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN41 */ "", 43740 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN42 */ "", 43741 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN43 */ "", 43742 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN44 */ "", 43743 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN45 */ "", 43744 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN46 */ "", 43745 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN47 */ "", 43746 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN48 */ "", 43747 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN49 */ "", 43748 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN50 */ "", 43749 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN51 */ "", 43750 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN52 */ "", 43751 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN53 */ "", 43752 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN54 */ "", 43753 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN55 */ "", 43754 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN56 */ "", 43755 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN57 */ "", 43756 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN58 */ "", 43757 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN59 */ "", 43758 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN60 */ "", 43759 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN61 */ "", 43760 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN62 */ "", 43761 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN63 */ "", 43762 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN64 */ "", 43763 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN65 */ "", 43764 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN66 */ "", 43765 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN67 */ "", 43766 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN68 */ "", 43767 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN69 */ "", 43768 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN70 */ "", 43769 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN71 */ "", 43770 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN72 */ "", 43771 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN73 */ "", 43772 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN74 */ "", 43773 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN75 */ "", 43774 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN76 */ "", 43775 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN77 */ "", 43776 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN78 */ "", 43777 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN79 */ "", 43778 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN80 */ "", 43779 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN81 */ "", 43780 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN82 */ "", 43781 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN83 */ "", 43782 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN84 */ "", 43783 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN85 */ "", 43784 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN86 */ "", 43785 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN87 */ "", 43786 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN88 */ "", 43787 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN89 */ "", 43788 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN90 */ "", 43789 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN91 */ "", 43790 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN92 */ "", 43791 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN93 */ "", 43792 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN94 */ "", 43793 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN95 */ "", 43794 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN96 */ "", 43795 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN97 */ "", 43796 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN98 */ "", 43797 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN99 */ "", 43798 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN0A */ "", 43799 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN0B */ "", 43800 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN0C */ "", 43801 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN0D */ "", 43802 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN0E */ "", 43803 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN0F */ "", 43804 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN1A */ "", 43805 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN1B */ "", 43806 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN1C */ "", 43807 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN1D */ "", 43808 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN1E */ "", 43809 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN1F */ "", 43810 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN2A */ "", 43811 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN2B */ "", 43812 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN2C */ "", 43813 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN2D */ "", 43814 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN2E */ "", 43815 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN2F */ "", 43816 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN3A */ "", 43817 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN3B */ "", 43818 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN3C */ "", 43819 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN3D */ "", 43820 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN3E */ "", 43821 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN3F */ "", 43822 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN4A */ "", 43823 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN4B */ "", 43824 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN4C */ "", 43825 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN4D */ "", 43826 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN4E */ "", 43827 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN4F */ "", 43828 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN5A */ "", 43829 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN5B */ "", 43830 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN5C */ "", 43831 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN5D */ "", 43832 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN5E */ "", 43833 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN5F */ "", 43834 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN6A */ "", 43835 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN6B */ "", 43836 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN6C */ "", 43837 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN6D */ "", 43838 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN6E */ "", 43839 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN6F */ "", 43840 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN7A */ "", 43841 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN7B */ "", 43842 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN7C */ "", 43843 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN7D */ "", 43844 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN7E */ "", 43845 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN7F */ "", 43846 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN8A */ "", 43847 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN8B */ "", 43848 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN8C */ "", 43849 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN8D */ "", 43850 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN8E */ "", 43851 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN8F */ "", 43852 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN9A */ "", 43853 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN9B */ "", 43854 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN9C */ "", 43855 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN9D */ "", 43856 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN9E */ "", 43857 /* IHOST_SWSTM_R_VAL_1BYTE_CHAN9F */ "", 43858 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA0 */ "", 43859 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA1 */ "", 43860 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA2 */ "", 43861 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA3 */ "", 43862 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA4 */ "", 43863 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA5 */ "", 43864 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA6 */ "", 43865 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA7 */ "", 43866 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA8 */ "", 43867 /* IHOST_SWSTM_R_VAL_1BYTE_CHANA9 */ "", 43868 /* IHOST_SWSTM_R_VAL_1BYTE_CHANAA */ "", 43869 /* IHOST_SWSTM_R_VAL_1BYTE_CHANAB */ "", 43870 /* IHOST_SWSTM_R_VAL_1BYTE_CHANAC */ "", 43871 /* IHOST_SWSTM_R_VAL_1BYTE_CHANAD */ "", 43872 /* IHOST_SWSTM_R_VAL_1BYTE_CHANAE */ "", 43873 /* IHOST_SWSTM_R_VAL_1BYTE_CHANAF */ "", 43874 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB0 */ "", 43875 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB1 */ "", 43876 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB2 */ "", 43877 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB3 */ "", 43878 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB4 */ "", 43879 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB5 */ "", 43880 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB6 */ "", 43881 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB7 */ "", 43882 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB8 */ "", 43883 /* IHOST_SWSTM_R_VAL_1BYTE_CHANB9 */ "", 43884 /* IHOST_SWSTM_R_VAL_1BYTE_CHANBA */ "", 43885 /* IHOST_SWSTM_R_VAL_1BYTE_CHANBB */ "", 43886 /* IHOST_SWSTM_R_VAL_1BYTE_CHANBC */ "", 43887 /* IHOST_SWSTM_R_VAL_1BYTE_CHANBD */ "", 43888 /* IHOST_SWSTM_R_VAL_1BYTE_CHANBE */ "", 43889 /* IHOST_SWSTM_R_VAL_1BYTE_CHANBF */ "", 43890 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC0 */ "", 43891 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC1 */ "", 43892 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC2 */ "", 43893 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC3 */ "", 43894 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC4 */ "", 43895 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC5 */ "", 43896 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC6 */ "", 43897 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC7 */ "", 43898 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC8 */ "", 43899 /* IHOST_SWSTM_R_VAL_1BYTE_CHANC9 */ "", 43900 /* IHOST_SWSTM_R_VAL_1BYTE_CHANCA */ "", 43901 /* IHOST_SWSTM_R_VAL_1BYTE_CHANCB */ "", 43902 /* IHOST_SWSTM_R_VAL_1BYTE_CHANCC */ "", 43903 /* IHOST_SWSTM_R_VAL_1BYTE_CHANCD */ "", 43904 /* IHOST_SWSTM_R_VAL_1BYTE_CHANCE */ "", 43905 /* IHOST_SWSTM_R_VAL_1BYTE_CHANCF */ "", 43906 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND0 */ "", 43907 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND1 */ "", 43908 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND2 */ "", 43909 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND3 */ "", 43910 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND4 */ "", 43911 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND5 */ "", 43912 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND6 */ "", 43913 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND7 */ "", 43914 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND8 */ "", 43915 /* IHOST_SWSTM_R_VAL_1BYTE_CHAND9 */ "", 43916 /* IHOST_SWSTM_R_VAL_1BYTE_CHANDA */ "", 43917 /* IHOST_SWSTM_R_VAL_1BYTE_CHANDB */ "", 43918 /* IHOST_SWSTM_R_VAL_1BYTE_CHANDC */ "", 43919 /* IHOST_SWSTM_R_VAL_1BYTE_CHANDD */ "", 43920 /* IHOST_SWSTM_R_VAL_1BYTE_CHANDE */ "", 43921 /* IHOST_SWSTM_R_VAL_1BYTE_CHANDF */ "", 43922 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE0 */ "", 43923 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE1 */ "", 43924 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE2 */ "", 43925 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE3 */ "", 43926 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE4 */ "", 43927 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE5 */ "", 43928 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE6 */ "", 43929 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE7 */ "", 43930 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE8 */ "", 43931 /* IHOST_SWSTM_R_VAL_1BYTE_CHANE9 */ "", 43932 /* IHOST_SWSTM_R_VAL_1BYTE_CHANEA */ "", 43933 /* IHOST_SWSTM_R_VAL_1BYTE_CHANEB */ "", 43934 /* IHOST_SWSTM_R_VAL_1BYTE_CHANEC */ "", 43935 /* IHOST_SWSTM_R_VAL_1BYTE_CHANED */ "", 43936 /* IHOST_SWSTM_R_VAL_1BYTE_CHANEE */ "", 43937 /* IHOST_SWSTM_R_VAL_1BYTE_CHANEF */ "", 43938 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF0 */ "", 43939 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF1 */ "", 43940 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF2 */ "", 43941 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF3 */ "", 43942 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF4 */ "", 43943 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF5 */ "", 43944 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF6 */ "", 43945 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF7 */ "", 43946 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF8 */ "", 43947 /* IHOST_SWSTM_R_VAL_1BYTE_CHANF9 */ "", 43948 /* IHOST_SWSTM_R_VAL_1BYTE_CHANFA */ "", 43949 /* IHOST_SWSTM_R_VAL_1BYTE_CHANFB */ "", 43950 /* IHOST_SWSTM_R_VAL_1BYTE_CHANFC */ "", 43951 /* IHOST_SWSTM_R_VAL_1BYTE_CHANFD */ "", 43952 /* IHOST_SWSTM_R_VAL_1BYTE_CHANFE */ "", 43953 /* IHOST_SWSTM_R_VAL_1BYTE_CHANFF */ "", 43954 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN00 */ "", 43955 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN01 */ "", 43956 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN02 */ "", 43957 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN03 */ "", 43958 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN04 */ "", 43959 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN05 */ "", 43960 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN06 */ "", 43961 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN07 */ "", 43962 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN08 */ "", 43963 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN09 */ "", 43964 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN10 */ "", 43965 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN11 */ "", 43966 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN12 */ "", 43967 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN13 */ "", 43968 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN14 */ "", 43969 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN15 */ "", 43970 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN16 */ "", 43971 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN17 */ "", 43972 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN18 */ "", 43973 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN19 */ "", 43974 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN20 */ "", 43975 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN21 */ "", 43976 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN22 */ "", 43977 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN23 */ "", 43978 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN24 */ "", 43979 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN25 */ "", 43980 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN26 */ "", 43981 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN27 */ "", 43982 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN28 */ "", 43983 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN29 */ "", 43984 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN30 */ "", 43985 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN31 */ "", 43986 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN32 */ "", 43987 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN33 */ "", 43988 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN34 */ "", 43989 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN35 */ "", 43990 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN36 */ "", 43991 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN37 */ "", 43992 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN38 */ "", 43993 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN39 */ "", 43994 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN40 */ "", 43995 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN41 */ "", 43996 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN42 */ "", 43997 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN43 */ "", 43998 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN44 */ "", 43999 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN45 */ "", 44000 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN46 */ "", 44001 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN47 */ "", 44002 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN48 */ "", 44003 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN49 */ "", 44004 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN50 */ "", 44005 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN51 */ "", 44006 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN52 */ "", 44007 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN53 */ "", 44008 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN54 */ "", 44009 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN55 */ "", 44010 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN56 */ "", 44011 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN57 */ "", 44012 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN58 */ "", 44013 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN59 */ "", 44014 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN60 */ "", 44015 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN61 */ "", 44016 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN62 */ "", 44017 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN63 */ "", 44018 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN64 */ "", 44019 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN65 */ "", 44020 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN66 */ "", 44021 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN67 */ "", 44022 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN68 */ "", 44023 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN69 */ "", 44024 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN70 */ "", 44025 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN71 */ "", 44026 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN72 */ "", 44027 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN73 */ "", 44028 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN74 */ "", 44029 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN75 */ "", 44030 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN76 */ "", 44031 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN77 */ "", 44032 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN78 */ "", 44033 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN79 */ "", 44034 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN80 */ "", 44035 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN81 */ "", 44036 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN82 */ "", 44037 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN83 */ "", 44038 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN84 */ "", 44039 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN85 */ "", 44040 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN86 */ "", 44041 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN87 */ "", 44042 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN88 */ "", 44043 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN89 */ "", 44044 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN90 */ "", 44045 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN91 */ "", 44046 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN92 */ "", 44047 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN93 */ "", 44048 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN94 */ "", 44049 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN95 */ "", 44050 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN96 */ "", 44051 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN97 */ "", 44052 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN98 */ "", 44053 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN99 */ "", 44054 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN0A */ "", 44055 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN0B */ "", 44056 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN0C */ "", 44057 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN0D */ "", 44058 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN0E */ "", 44059 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN0F */ "", 44060 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN1A */ "", 44061 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN1B */ "", 44062 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN1C */ "", 44063 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN1D */ "", 44064 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN1E */ "", 44065 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN1F */ "", 44066 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN2A */ "", 44067 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN2B */ "", 44068 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN2C */ "", 44069 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN2D */ "", 44070 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN2E */ "", 44071 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN2F */ "", 44072 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN3A */ "", 44073 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN3B */ "", 44074 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN3C */ "", 44075 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN3D */ "", 44076 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN3E */ "", 44077 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN3F */ "", 44078 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN4A */ "", 44079 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN4B */ "", 44080 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN4C */ "", 44081 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN4D */ "", 44082 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN4E */ "", 44083 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN4F */ "", 44084 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN5A */ "", 44085 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN5B */ "", 44086 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN5C */ "", 44087 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN5D */ "", 44088 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN5E */ "", 44089 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN5F */ "", 44090 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN6A */ "", 44091 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN6B */ "", 44092 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN6C */ "", 44093 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN6D */ "", 44094 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN6E */ "", 44095 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN6F */ "", 44096 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN7A */ "", 44097 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN7B */ "", 44098 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN7C */ "", 44099 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN7D */ "", 44100 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN7E */ "", 44101 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN7F */ "", 44102 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN8A */ "", 44103 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN8B */ "", 44104 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN8C */ "", 44105 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN8D */ "", 44106 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN8E */ "", 44107 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN8F */ "", 44108 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN9A */ "", 44109 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN9B */ "", 44110 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN9C */ "", 44111 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN9D */ "", 44112 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN9E */ "", 44113 /* IHOST_SWSTM_R_VAL_2BYTE_CHAN9F */ "", 44114 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA0 */ "", 44115 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA1 */ "", 44116 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA2 */ "", 44117 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA3 */ "", 44118 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA4 */ "", 44119 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA5 */ "", 44120 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA6 */ "", 44121 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA7 */ "", 44122 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA8 */ "", 44123 /* IHOST_SWSTM_R_VAL_2BYTE_CHANA9 */ "", 44124 /* IHOST_SWSTM_R_VAL_2BYTE_CHANAA */ "", 44125 /* IHOST_SWSTM_R_VAL_2BYTE_CHANAB */ "", 44126 /* IHOST_SWSTM_R_VAL_2BYTE_CHANAC */ "", 44127 /* IHOST_SWSTM_R_VAL_2BYTE_CHANAD */ "", 44128 /* IHOST_SWSTM_R_VAL_2BYTE_CHANAE */ "", 44129 /* IHOST_SWSTM_R_VAL_2BYTE_CHANAF */ "", 44130 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB0 */ "", 44131 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB1 */ "", 44132 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB2 */ "", 44133 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB3 */ "", 44134 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB4 */ "", 44135 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB5 */ "", 44136 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB6 */ "", 44137 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB7 */ "", 44138 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB8 */ "", 44139 /* IHOST_SWSTM_R_VAL_2BYTE_CHANB9 */ "", 44140 /* IHOST_SWSTM_R_VAL_2BYTE_CHANBA */ "", 44141 /* IHOST_SWSTM_R_VAL_2BYTE_CHANBB */ "", 44142 /* IHOST_SWSTM_R_VAL_2BYTE_CHANBC */ "", 44143 /* IHOST_SWSTM_R_VAL_2BYTE_CHANBD */ "", 44144 /* IHOST_SWSTM_R_VAL_2BYTE_CHANBE */ "", 44145 /* IHOST_SWSTM_R_VAL_2BYTE_CHANBF */ "", 44146 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC0 */ "", 44147 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC1 */ "", 44148 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC2 */ "", 44149 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC3 */ "", 44150 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC4 */ "", 44151 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC5 */ "", 44152 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC6 */ "", 44153 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC7 */ "", 44154 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC8 */ "", 44155 /* IHOST_SWSTM_R_VAL_2BYTE_CHANC9 */ "", 44156 /* IHOST_SWSTM_R_VAL_2BYTE_CHANCA */ "", 44157 /* IHOST_SWSTM_R_VAL_2BYTE_CHANCB */ "", 44158 /* IHOST_SWSTM_R_VAL_2BYTE_CHANCC */ "", 44159 /* IHOST_SWSTM_R_VAL_2BYTE_CHANCD */ "", 44160 /* IHOST_SWSTM_R_VAL_2BYTE_CHANCE */ "", 44161 /* IHOST_SWSTM_R_VAL_2BYTE_CHANCF */ "", 44162 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND0 */ "", 44163 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND1 */ "", 44164 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND2 */ "", 44165 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND3 */ "", 44166 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND4 */ "", 44167 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND5 */ "", 44168 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND6 */ "", 44169 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND7 */ "", 44170 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND8 */ "", 44171 /* IHOST_SWSTM_R_VAL_2BYTE_CHAND9 */ "", 44172 /* IHOST_SWSTM_R_VAL_2BYTE_CHANDA */ "", 44173 /* IHOST_SWSTM_R_VAL_2BYTE_CHANDB */ "", 44174 /* IHOST_SWSTM_R_VAL_2BYTE_CHANDC */ "", 44175 /* IHOST_SWSTM_R_VAL_2BYTE_CHANDD */ "", 44176 /* IHOST_SWSTM_R_VAL_2BYTE_CHANDE */ "", 44177 /* IHOST_SWSTM_R_VAL_2BYTE_CHANDF */ "", 44178 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE0 */ "", 44179 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE1 */ "", 44180 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE2 */ "", 44181 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE3 */ "", 44182 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE4 */ "", 44183 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE5 */ "", 44184 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE6 */ "", 44185 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE7 */ "", 44186 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE8 */ "", 44187 /* IHOST_SWSTM_R_VAL_2BYTE_CHANE9 */ "", 44188 /* IHOST_SWSTM_R_VAL_2BYTE_CHANEA */ "", 44189 /* IHOST_SWSTM_R_VAL_2BYTE_CHANEB */ "", 44190 /* IHOST_SWSTM_R_VAL_2BYTE_CHANEC */ "", 44191 /* IHOST_SWSTM_R_VAL_2BYTE_CHANED */ "", 44192 /* IHOST_SWSTM_R_VAL_2BYTE_CHANEE */ "", 44193 /* IHOST_SWSTM_R_VAL_2BYTE_CHANEF */ "", 44194 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF0 */ "", 44195 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF1 */ "", 44196 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF2 */ "", 44197 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF3 */ "", 44198 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF4 */ "", 44199 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF5 */ "", 44200 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF6 */ "", 44201 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF7 */ "", 44202 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF8 */ "", 44203 /* IHOST_SWSTM_R_VAL_2BYTE_CHANF9 */ "", 44204 /* IHOST_SWSTM_R_VAL_2BYTE_CHANFA */ "", 44205 /* IHOST_SWSTM_R_VAL_2BYTE_CHANFB */ "", 44206 /* IHOST_SWSTM_R_VAL_2BYTE_CHANFC */ "", 44207 /* IHOST_SWSTM_R_VAL_2BYTE_CHANFD */ "", 44208 /* IHOST_SWSTM_R_VAL_2BYTE_CHANFE */ "", 44209 /* IHOST_SWSTM_R_VAL_2BYTE_CHANFF */ "", 44210 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN00 */ "", 44211 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN01 */ "", 44212 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN02 */ "", 44213 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN03 */ "", 44214 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN04 */ "", 44215 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN05 */ "", 44216 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN06 */ "", 44217 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN07 */ "", 44218 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN08 */ "", 44219 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN09 */ "", 44220 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN10 */ "", 44221 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN11 */ "", 44222 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN12 */ "", 44223 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN13 */ "", 44224 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN14 */ "", 44225 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN15 */ "", 44226 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN16 */ "", 44227 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN17 */ "", 44228 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN18 */ "", 44229 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN19 */ "", 44230 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN20 */ "", 44231 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN21 */ "", 44232 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN22 */ "", 44233 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN23 */ "", 44234 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN24 */ "", 44235 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN25 */ "", 44236 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN26 */ "", 44237 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN27 */ "", 44238 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN28 */ "", 44239 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN29 */ "", 44240 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN30 */ "", 44241 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN31 */ "", 44242 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN32 */ "", 44243 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN33 */ "", 44244 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN34 */ "", 44245 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN35 */ "", 44246 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN36 */ "", 44247 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN37 */ "", 44248 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN38 */ "", 44249 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN39 */ "", 44250 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN40 */ "", 44251 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN41 */ "", 44252 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN42 */ "", 44253 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN43 */ "", 44254 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN44 */ "", 44255 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN45 */ "", 44256 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN46 */ "", 44257 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN47 */ "", 44258 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN48 */ "", 44259 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN49 */ "", 44260 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN50 */ "", 44261 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN51 */ "", 44262 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN52 */ "", 44263 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN53 */ "", 44264 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN54 */ "", 44265 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN55 */ "", 44266 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN56 */ "", 44267 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN57 */ "", 44268 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN58 */ "", 44269 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN59 */ "", 44270 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN60 */ "", 44271 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN61 */ "", 44272 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN62 */ "", 44273 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN63 */ "", 44274 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN64 */ "", 44275 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN65 */ "", 44276 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN66 */ "", 44277 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN67 */ "", 44278 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN68 */ "", 44279 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN69 */ "", 44280 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN70 */ "", 44281 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN71 */ "", 44282 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN72 */ "", 44283 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN73 */ "", 44284 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN74 */ "", 44285 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN75 */ "", 44286 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN76 */ "", 44287 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN77 */ "", 44288 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN78 */ "", 44289 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN79 */ "", 44290 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN80 */ "", 44291 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN81 */ "", 44292 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN82 */ "", 44293 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN83 */ "", 44294 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN84 */ "", 44295 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN85 */ "", 44296 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN86 */ "", 44297 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN87 */ "", 44298 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN88 */ "", 44299 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN89 */ "", 44300 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN90 */ "", 44301 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN91 */ "", 44302 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN92 */ "", 44303 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN93 */ "", 44304 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN94 */ "", 44305 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN95 */ "", 44306 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN96 */ "", 44307 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN97 */ "", 44308 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN98 */ "", 44309 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN99 */ "", 44310 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN0A */ "", 44311 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN0B */ "", 44312 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN0C */ "", 44313 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN0D */ "", 44314 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN0E */ "", 44315 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN0F */ "", 44316 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN1A */ "", 44317 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN1B */ "", 44318 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN1C */ "", 44319 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN1D */ "", 44320 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN1E */ "", 44321 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN1F */ "", 44322 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN2A */ "", 44323 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN2B */ "", 44324 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN2C */ "", 44325 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN2D */ "", 44326 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN2E */ "", 44327 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN2F */ "", 44328 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN3A */ "", 44329 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN3B */ "", 44330 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN3C */ "", 44331 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN3D */ "", 44332 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN3E */ "", 44333 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN3F */ "", 44334 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN4A */ "", 44335 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN4B */ "", 44336 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN4C */ "", 44337 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN4D */ "", 44338 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN4E */ "", 44339 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN4F */ "", 44340 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN5A */ "", 44341 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN5B */ "", 44342 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN5C */ "", 44343 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN5D */ "", 44344 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN5E */ "", 44345 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN5F */ "", 44346 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN6A */ "", 44347 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN6B */ "", 44348 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN6C */ "", 44349 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN6D */ "", 44350 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN6E */ "", 44351 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN6F */ "", 44352 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN7A */ "", 44353 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN7B */ "", 44354 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN7C */ "", 44355 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN7D */ "", 44356 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN7E */ "", 44357 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN7F */ "", 44358 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN8A */ "", 44359 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN8B */ "", 44360 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN8C */ "", 44361 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN8D */ "", 44362 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN8E */ "", 44363 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN8F */ "", 44364 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN9A */ "", 44365 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN9B */ "", 44366 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN9C */ "", 44367 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN9D */ "", 44368 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN9E */ "", 44369 /* IHOST_SWSTM_R_VAL_4BYTE_CHAN9F */ "", 44370 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA0 */ "", 44371 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA1 */ "", 44372 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA2 */ "", 44373 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA3 */ "", 44374 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA4 */ "", 44375 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA5 */ "", 44376 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA6 */ "", 44377 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA7 */ "", 44378 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA8 */ "", 44379 /* IHOST_SWSTM_R_VAL_4BYTE_CHANA9 */ "", 44380 /* IHOST_SWSTM_R_VAL_4BYTE_CHANAA */ "", 44381 /* IHOST_SWSTM_R_VAL_4BYTE_CHANAB */ "", 44382 /* IHOST_SWSTM_R_VAL_4BYTE_CHANAC */ "", 44383 /* IHOST_SWSTM_R_VAL_4BYTE_CHANAD */ "", 44384 /* IHOST_SWSTM_R_VAL_4BYTE_CHANAE */ "", 44385 /* IHOST_SWSTM_R_VAL_4BYTE_CHANAF */ "", 44386 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB0 */ "", 44387 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB1 */ "", 44388 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB2 */ "", 44389 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB3 */ "", 44390 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB4 */ "", 44391 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB5 */ "", 44392 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB6 */ "", 44393 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB7 */ "", 44394 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB8 */ "", 44395 /* IHOST_SWSTM_R_VAL_4BYTE_CHANB9 */ "", 44396 /* IHOST_SWSTM_R_VAL_4BYTE_CHANBA */ "", 44397 /* IHOST_SWSTM_R_VAL_4BYTE_CHANBB */ "", 44398 /* IHOST_SWSTM_R_VAL_4BYTE_CHANBC */ "", 44399 /* IHOST_SWSTM_R_VAL_4BYTE_CHANBD */ "", 44400 /* IHOST_SWSTM_R_VAL_4BYTE_CHANBE */ "", 44401 /* IHOST_SWSTM_R_VAL_4BYTE_CHANBF */ "", 44402 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC0 */ "", 44403 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC1 */ "", 44404 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC2 */ "", 44405 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC3 */ "", 44406 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC4 */ "", 44407 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC5 */ "", 44408 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC6 */ "", 44409 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC7 */ "", 44410 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC8 */ "", 44411 /* IHOST_SWSTM_R_VAL_4BYTE_CHANC9 */ "", 44412 /* IHOST_SWSTM_R_VAL_4BYTE_CHANCA */ "", 44413 /* IHOST_SWSTM_R_VAL_4BYTE_CHANCB */ "", 44414 /* IHOST_SWSTM_R_VAL_4BYTE_CHANCC */ "", 44415 /* IHOST_SWSTM_R_VAL_4BYTE_CHANCD */ "", 44416 /* IHOST_SWSTM_R_VAL_4BYTE_CHANCE */ "", 44417 /* IHOST_SWSTM_R_VAL_4BYTE_CHANCF */ "", 44418 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND0 */ "", 44419 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND1 */ "", 44420 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND2 */ "", 44421 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND3 */ "", 44422 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND4 */ "", 44423 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND5 */ "", 44424 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND6 */ "", 44425 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND7 */ "", 44426 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND8 */ "", 44427 /* IHOST_SWSTM_R_VAL_4BYTE_CHAND9 */ "", 44428 /* IHOST_SWSTM_R_VAL_4BYTE_CHANDA */ "", 44429 /* IHOST_SWSTM_R_VAL_4BYTE_CHANDB */ "", 44430 /* IHOST_SWSTM_R_VAL_4BYTE_CHANDC */ "", 44431 /* IHOST_SWSTM_R_VAL_4BYTE_CHANDD */ "", 44432 /* IHOST_SWSTM_R_VAL_4BYTE_CHANDE */ "", 44433 /* IHOST_SWSTM_R_VAL_4BYTE_CHANDF */ "", 44434 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE0 */ "", 44435 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE1 */ "", 44436 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE2 */ "", 44437 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE3 */ "", 44438 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE4 */ "", 44439 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE5 */ "", 44440 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE6 */ "", 44441 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE7 */ "", 44442 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE8 */ "", 44443 /* IHOST_SWSTM_R_VAL_4BYTE_CHANE9 */ "", 44444 /* IHOST_SWSTM_R_VAL_4BYTE_CHANEA */ "", 44445 /* IHOST_SWSTM_R_VAL_4BYTE_CHANEB */ "", 44446 /* IHOST_SWSTM_R_VAL_4BYTE_CHANEC */ "", 44447 /* IHOST_SWSTM_R_VAL_4BYTE_CHANED */ "", 44448 /* IHOST_SWSTM_R_VAL_4BYTE_CHANEE */ "", 44449 /* IHOST_SWSTM_R_VAL_4BYTE_CHANEF */ "", 44450 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF0 */ "", 44451 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF1 */ "", 44452 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF2 */ "", 44453 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF3 */ "", 44454 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF4 */ "", 44455 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF5 */ "", 44456 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF6 */ "", 44457 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF7 */ "", 44458 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF8 */ "", 44459 /* IHOST_SWSTM_R_VAL_4BYTE_CHANF9 */ "", 44460 /* IHOST_SWSTM_R_VAL_4BYTE_CHANFA */ "", 44461 /* IHOST_SWSTM_R_VAL_4BYTE_CHANFB */ "", 44462 /* IHOST_SWSTM_R_VAL_4BYTE_CHANFC */ "", 44463 /* IHOST_SWSTM_R_VAL_4BYTE_CHANFD */ "", 44464 /* IHOST_SWSTM_R_VAL_4BYTE_CHANFE */ "", 44465 /* IHOST_SWSTM_R_VAL_4BYTE_CHANFF */ "", 44466 /* IHOST_SWSTM_TS_R_CONFIG */ "", 44467 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN00 */ "", 44468 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN01 */ "", 44469 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN02 */ "", 44470 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN03 */ "", 44471 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN04 */ "", 44472 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN05 */ "", 44473 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN06 */ "", 44474 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN07 */ "", 44475 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN08 */ "", 44476 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN09 */ "", 44477 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN10 */ "", 44478 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN11 */ "", 44479 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN12 */ "", 44480 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN13 */ "", 44481 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN14 */ "", 44482 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN15 */ "", 44483 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN16 */ "", 44484 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN17 */ "", 44485 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN18 */ "", 44486 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN19 */ "", 44487 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN20 */ "", 44488 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN21 */ "", 44489 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN22 */ "", 44490 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN23 */ "", 44491 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN24 */ "", 44492 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN25 */ "", 44493 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN26 */ "", 44494 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN27 */ "", 44495 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN28 */ "", 44496 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN29 */ "", 44497 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN30 */ "", 44498 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN31 */ "", 44499 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN32 */ "", 44500 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN33 */ "", 44501 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN34 */ "", 44502 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN35 */ "", 44503 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN36 */ "", 44504 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN37 */ "", 44505 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN38 */ "", 44506 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN39 */ "", 44507 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN40 */ "", 44508 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN41 */ "", 44509 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN42 */ "", 44510 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN43 */ "", 44511 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN44 */ "", 44512 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN45 */ "", 44513 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN46 */ "", 44514 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN47 */ "", 44515 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN48 */ "", 44516 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN49 */ "", 44517 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN50 */ "", 44518 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN51 */ "", 44519 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN52 */ "", 44520 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN53 */ "", 44521 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN54 */ "", 44522 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN55 */ "", 44523 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN56 */ "", 44524 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN57 */ "", 44525 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN58 */ "", 44526 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN59 */ "", 44527 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN60 */ "", 44528 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN61 */ "", 44529 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN62 */ "", 44530 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN63 */ "", 44531 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN64 */ "", 44532 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN65 */ "", 44533 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN66 */ "", 44534 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN67 */ "", 44535 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN68 */ "", 44536 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN69 */ "", 44537 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN70 */ "", 44538 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN71 */ "", 44539 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN72 */ "", 44540 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN73 */ "", 44541 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN74 */ "", 44542 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN75 */ "", 44543 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN76 */ "", 44544 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN77 */ "", 44545 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN78 */ "", 44546 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN79 */ "", 44547 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN80 */ "", 44548 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN81 */ "", 44549 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN82 */ "", 44550 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN83 */ "", 44551 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN84 */ "", 44552 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN85 */ "", 44553 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN86 */ "", 44554 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN87 */ "", 44555 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN88 */ "", 44556 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN89 */ "", 44557 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN90 */ "", 44558 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN91 */ "", 44559 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN92 */ "", 44560 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN93 */ "", 44561 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN94 */ "", 44562 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN95 */ "", 44563 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN96 */ "", 44564 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN97 */ "", 44565 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN98 */ "", 44566 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN99 */ "", 44567 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN0A */ "", 44568 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN0B */ "", 44569 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN0C */ "", 44570 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN0D */ "", 44571 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN0E */ "", 44572 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN0F */ "", 44573 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN1A */ "", 44574 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN1B */ "", 44575 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN1C */ "", 44576 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN1D */ "", 44577 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN1E */ "", 44578 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN1F */ "", 44579 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN2A */ "", 44580 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN2B */ "", 44581 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN2C */ "", 44582 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN2D */ "", 44583 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN2E */ "", 44584 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN2F */ "", 44585 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN3A */ "", 44586 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN3B */ "", 44587 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN3C */ "", 44588 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN3D */ "", 44589 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN3E */ "", 44590 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN3F */ "", 44591 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN4A */ "", 44592 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN4B */ "", 44593 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN4C */ "", 44594 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN4D */ "", 44595 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN4E */ "", 44596 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN4F */ "", 44597 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN5A */ "", 44598 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN5B */ "", 44599 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN5C */ "", 44600 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN5D */ "", 44601 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN5E */ "", 44602 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN5F */ "", 44603 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN6A */ "", 44604 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN6B */ "", 44605 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN6C */ "", 44606 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN6D */ "", 44607 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN6E */ "", 44608 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN6F */ "", 44609 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN7A */ "", 44610 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN7B */ "", 44611 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN7C */ "", 44612 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN7D */ "", 44613 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN7E */ "", 44614 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN7F */ "", 44615 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN8A */ "", 44616 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN8B */ "", 44617 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN8C */ "", 44618 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN8D */ "", 44619 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN8E */ "", 44620 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN8F */ "", 44621 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN9A */ "", 44622 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN9B */ "", 44623 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN9C */ "", 44624 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN9D */ "", 44625 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN9E */ "", 44626 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAN9F */ "", 44627 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA0 */ "", 44628 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA1 */ "", 44629 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA2 */ "", 44630 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA3 */ "", 44631 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA4 */ "", 44632 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA5 */ "", 44633 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA6 */ "", 44634 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA7 */ "", 44635 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA8 */ "", 44636 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANA9 */ "", 44637 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANAA */ "", 44638 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANAB */ "", 44639 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANAC */ "", 44640 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANAD */ "", 44641 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANAE */ "", 44642 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANAF */ "", 44643 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB0 */ "", 44644 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB1 */ "", 44645 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB2 */ "", 44646 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB3 */ "", 44647 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB4 */ "", 44648 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB5 */ "", 44649 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB6 */ "", 44650 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB7 */ "", 44651 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB8 */ "", 44652 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANB9 */ "", 44653 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANBA */ "", 44654 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANBB */ "", 44655 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANBC */ "", 44656 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANBD */ "", 44657 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANBE */ "", 44658 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANBF */ "", 44659 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC0 */ "", 44660 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC1 */ "", 44661 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC2 */ "", 44662 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC3 */ "", 44663 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC4 */ "", 44664 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC5 */ "", 44665 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC6 */ "", 44666 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC7 */ "", 44667 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC8 */ "", 44668 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANC9 */ "", 44669 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANCA */ "", 44670 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANCB */ "", 44671 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANCC */ "", 44672 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANCD */ "", 44673 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANCE */ "", 44674 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANCF */ "", 44675 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND0 */ "", 44676 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND1 */ "", 44677 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND2 */ "", 44678 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND3 */ "", 44679 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND4 */ "", 44680 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND5 */ "", 44681 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND6 */ "", 44682 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND7 */ "", 44683 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND8 */ "", 44684 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHAND9 */ "", 44685 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANDA */ "", 44686 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANDB */ "", 44687 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANDC */ "", 44688 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANDD */ "", 44689 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANDE */ "", 44690 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANDF */ "", 44691 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE0 */ "", 44692 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE1 */ "", 44693 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE2 */ "", 44694 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE3 */ "", 44695 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE4 */ "", 44696 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE5 */ "", 44697 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE6 */ "", 44698 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE7 */ "", 44699 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE8 */ "", 44700 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANE9 */ "", 44701 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANEA */ "", 44702 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANEB */ "", 44703 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANEC */ "", 44704 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANED */ "", 44705 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANEE */ "", 44706 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANEF */ "", 44707 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF0 */ "", 44708 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF1 */ "", 44709 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF2 */ "", 44710 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF3 */ "", 44711 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF4 */ "", 44712 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF5 */ "", 44713 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF6 */ "", 44714 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF7 */ "", 44715 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF8 */ "", 44716 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANF9 */ "", 44717 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANFA */ "", 44718 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANFB */ "", 44719 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANFC */ "", 44720 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANFD */ "", 44721 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANFE */ "", 44722 /* IHOST_SWSTM_TS_R_VAL_1BYTE_CHANFF */ "", 44723 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN00 */ "", 44724 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN01 */ "", 44725 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN02 */ "", 44726 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN03 */ "", 44727 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN04 */ "", 44728 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN05 */ "", 44729 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN06 */ "", 44730 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN07 */ "", 44731 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN08 */ "", 44732 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN09 */ "", 44733 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN10 */ "", 44734 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN11 */ "", 44735 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN12 */ "", 44736 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN13 */ "", 44737 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN14 */ "", 44738 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN15 */ "", 44739 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN16 */ "", 44740 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN17 */ "", 44741 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN18 */ "", 44742 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN19 */ "", 44743 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN20 */ "", 44744 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN21 */ "", 44745 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN22 */ "", 44746 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN23 */ "", 44747 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN24 */ "", 44748 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN25 */ "", 44749 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN26 */ "", 44750 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN27 */ "", 44751 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN28 */ "", 44752 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN29 */ "", 44753 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN30 */ "", 44754 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN31 */ "", 44755 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN32 */ "", 44756 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN33 */ "", 44757 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN34 */ "", 44758 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN35 */ "", 44759 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN36 */ "", 44760 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN37 */ "", 44761 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN38 */ "", 44762 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN39 */ "", 44763 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN40 */ "", 44764 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN41 */ "", 44765 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN42 */ "", 44766 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN43 */ "", 44767 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN44 */ "", 44768 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN45 */ "", 44769 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN46 */ "", 44770 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN47 */ "", 44771 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN48 */ "", 44772 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN49 */ "", 44773 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN50 */ "", 44774 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN51 */ "", 44775 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN52 */ "", 44776 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN53 */ "", 44777 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN54 */ "", 44778 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN55 */ "", 44779 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN56 */ "", 44780 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN57 */ "", 44781 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN58 */ "", 44782 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN59 */ "", 44783 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN60 */ "", 44784 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN61 */ "", 44785 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN62 */ "", 44786 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN63 */ "", 44787 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN64 */ "", 44788 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN65 */ "", 44789 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN66 */ "", 44790 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN67 */ "", 44791 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN68 */ "", 44792 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN69 */ "", 44793 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN70 */ "", 44794 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN71 */ "", 44795 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN72 */ "", 44796 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN73 */ "", 44797 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN74 */ "", 44798 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN75 */ "", 44799 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN76 */ "", 44800 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN77 */ "", 44801 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN78 */ "", 44802 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN79 */ "", 44803 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN80 */ "", 44804 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN81 */ "", 44805 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN82 */ "", 44806 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN83 */ "", 44807 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN84 */ "", 44808 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN85 */ "", 44809 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN86 */ "", 44810 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN87 */ "", 44811 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN88 */ "", 44812 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN89 */ "", 44813 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN90 */ "", 44814 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN91 */ "", 44815 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN92 */ "", 44816 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN93 */ "", 44817 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN94 */ "", 44818 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN95 */ "", 44819 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN96 */ "", 44820 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN97 */ "", 44821 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN98 */ "", 44822 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN99 */ "", 44823 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN0A */ "", 44824 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN0B */ "", 44825 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN0C */ "", 44826 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN0D */ "", 44827 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN0E */ "", 44828 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN0F */ "", 44829 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN1A */ "", 44830 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN1B */ "", 44831 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN1C */ "", 44832 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN1D */ "", 44833 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN1E */ "", 44834 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN1F */ "", 44835 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN2A */ "", 44836 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN2B */ "", 44837 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN2C */ "", 44838 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN2D */ "", 44839 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN2E */ "", 44840 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN2F */ "", 44841 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN3A */ "", 44842 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN3B */ "", 44843 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN3C */ "", 44844 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN3D */ "", 44845 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN3E */ "", 44846 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN3F */ "", 44847 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN4A */ "", 44848 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN4B */ "", 44849 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN4C */ "", 44850 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN4D */ "", 44851 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN4E */ "", 44852 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN4F */ "", 44853 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN5A */ "", 44854 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN5B */ "", 44855 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN5C */ "", 44856 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN5D */ "", 44857 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN5E */ "", 44858 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN5F */ "", 44859 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN6A */ "", 44860 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN6B */ "", 44861 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN6C */ "", 44862 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN6D */ "", 44863 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN6E */ "", 44864 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN6F */ "", 44865 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN7A */ "", 44866 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN7B */ "", 44867 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN7C */ "", 44868 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN7D */ "", 44869 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN7E */ "", 44870 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN7F */ "", 44871 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN8A */ "", 44872 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN8B */ "", 44873 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN8C */ "", 44874 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN8D */ "", 44875 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN8E */ "", 44876 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN8F */ "", 44877 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN9A */ "", 44878 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN9B */ "", 44879 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN9C */ "", 44880 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN9D */ "", 44881 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN9E */ "", 44882 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAN9F */ "", 44883 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA0 */ "", 44884 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA1 */ "", 44885 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA2 */ "", 44886 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA3 */ "", 44887 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA4 */ "", 44888 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA5 */ "", 44889 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA6 */ "", 44890 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA7 */ "", 44891 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA8 */ "", 44892 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANA9 */ "", 44893 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANAA */ "", 44894 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANAB */ "", 44895 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANAC */ "", 44896 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANAD */ "", 44897 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANAE */ "", 44898 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANAF */ "", 44899 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB0 */ "", 44900 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB1 */ "", 44901 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB2 */ "", 44902 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB3 */ "", 44903 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB4 */ "", 44904 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB5 */ "", 44905 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB6 */ "", 44906 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB7 */ "", 44907 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB8 */ "", 44908 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANB9 */ "", 44909 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANBA */ "", 44910 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANBB */ "", 44911 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANBC */ "", 44912 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANBD */ "", 44913 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANBE */ "", 44914 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANBF */ "", 44915 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC0 */ "", 44916 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC1 */ "", 44917 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC2 */ "", 44918 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC3 */ "", 44919 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC4 */ "", 44920 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC5 */ "", 44921 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC6 */ "", 44922 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC7 */ "", 44923 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC8 */ "", 44924 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANC9 */ "", 44925 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANCA */ "", 44926 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANCB */ "", 44927 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANCC */ "", 44928 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANCD */ "", 44929 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANCE */ "", 44930 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANCF */ "", 44931 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND0 */ "", 44932 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND1 */ "", 44933 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND2 */ "", 44934 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND3 */ "", 44935 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND4 */ "", 44936 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND5 */ "", 44937 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND6 */ "", 44938 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND7 */ "", 44939 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND8 */ "", 44940 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHAND9 */ "", 44941 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANDA */ "", 44942 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANDB */ "", 44943 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANDC */ "", 44944 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANDD */ "", 44945 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANDE */ "", 44946 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANDF */ "", 44947 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE0 */ "", 44948 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE1 */ "", 44949 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE2 */ "", 44950 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE3 */ "", 44951 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE4 */ "", 44952 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE5 */ "", 44953 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE6 */ "", 44954 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE7 */ "", 44955 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE8 */ "", 44956 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANE9 */ "", 44957 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANEA */ "", 44958 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANEB */ "", 44959 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANEC */ "", 44960 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANED */ "", 44961 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANEE */ "", 44962 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANEF */ "", 44963 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF0 */ "", 44964 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF1 */ "", 44965 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF2 */ "", 44966 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF3 */ "", 44967 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF4 */ "", 44968 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF5 */ "", 44969 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF6 */ "", 44970 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF7 */ "", 44971 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF8 */ "", 44972 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANF9 */ "", 44973 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANFA */ "", 44974 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANFB */ "", 44975 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANFC */ "", 44976 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANFD */ "", 44977 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANFE */ "", 44978 /* IHOST_SWSTM_TS_R_VAL_2BYTE_CHANFF */ "", 44979 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN00 */ "", 44980 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN01 */ "", 44981 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN02 */ "", 44982 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN03 */ "", 44983 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN04 */ "", 44984 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN05 */ "", 44985 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN06 */ "", 44986 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN07 */ "", 44987 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN08 */ "", 44988 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN09 */ "", 44989 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN10 */ "", 44990 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN11 */ "", 44991 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN12 */ "", 44992 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN13 */ "", 44993 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN14 */ "", 44994 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN15 */ "", 44995 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN16 */ "", 44996 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN17 */ "", 44997 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN18 */ "", 44998 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN19 */ "", 44999 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN20 */ "", 45000 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN21 */ "", 45001 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN22 */ "", 45002 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN23 */ "", 45003 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN24 */ "", 45004 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN25 */ "", 45005 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN26 */ "", 45006 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN27 */ "", 45007 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN28 */ "", 45008 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN29 */ "", 45009 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN30 */ "", 45010 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN31 */ "", 45011 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN32 */ "", 45012 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN33 */ "", 45013 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN34 */ "", 45014 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN35 */ "", 45015 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN36 */ "", 45016 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN37 */ "", 45017 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN38 */ "", 45018 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN39 */ "", 45019 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN40 */ "", 45020 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN41 */ "", 45021 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN42 */ "", 45022 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN43 */ "", 45023 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN44 */ "", 45024 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN45 */ "", 45025 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN46 */ "", 45026 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN47 */ "", 45027 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN48 */ "", 45028 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN49 */ "", 45029 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN50 */ "", 45030 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN51 */ "", 45031 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN52 */ "", 45032 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN53 */ "", 45033 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN54 */ "", 45034 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN55 */ "", 45035 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN56 */ "", 45036 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN57 */ "", 45037 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN58 */ "", 45038 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN59 */ "", 45039 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN60 */ "", 45040 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN61 */ "", 45041 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN62 */ "", 45042 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN63 */ "", 45043 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN64 */ "", 45044 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN65 */ "", 45045 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN66 */ "", 45046 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN67 */ "", 45047 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN68 */ "", 45048 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN69 */ "", 45049 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN70 */ "", 45050 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN71 */ "", 45051 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN72 */ "", 45052 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN73 */ "", 45053 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN74 */ "", 45054 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN75 */ "", 45055 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN76 */ "", 45056 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN77 */ "", 45057 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN78 */ "", 45058 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN79 */ "", 45059 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN80 */ "", 45060 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN81 */ "", 45061 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN82 */ "", 45062 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN83 */ "", 45063 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN84 */ "", 45064 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN85 */ "", 45065 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN86 */ "", 45066 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN87 */ "", 45067 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN88 */ "", 45068 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN89 */ "", 45069 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN90 */ "", 45070 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN91 */ "", 45071 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN92 */ "", 45072 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN93 */ "", 45073 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN94 */ "", 45074 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN95 */ "", 45075 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN96 */ "", 45076 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN97 */ "", 45077 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN98 */ "", 45078 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN99 */ "", 45079 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN0A */ "", 45080 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN0B */ "", 45081 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN0C */ "", 45082 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN0D */ "", 45083 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN0E */ "", 45084 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN0F */ "", 45085 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN1A */ "", 45086 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN1B */ "", 45087 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN1C */ "", 45088 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN1D */ "", 45089 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN1E */ "", 45090 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN1F */ "", 45091 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN2A */ "", 45092 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN2B */ "", 45093 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN2C */ "", 45094 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN2D */ "", 45095 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN2E */ "", 45096 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN2F */ "", 45097 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN3A */ "", 45098 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN3B */ "", 45099 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN3C */ "", 45100 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN3D */ "", 45101 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN3E */ "", 45102 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN3F */ "", 45103 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN4A */ "", 45104 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN4B */ "", 45105 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN4C */ "", 45106 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN4D */ "", 45107 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN4E */ "", 45108 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN4F */ "", 45109 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN5A */ "", 45110 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN5B */ "", 45111 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN5C */ "", 45112 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN5D */ "", 45113 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN5E */ "", 45114 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN5F */ "", 45115 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN6A */ "", 45116 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN6B */ "", 45117 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN6C */ "", 45118 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN6D */ "", 45119 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN6E */ "", 45120 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN6F */ "", 45121 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN7A */ "", 45122 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN7B */ "", 45123 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN7C */ "", 45124 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN7D */ "", 45125 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN7E */ "", 45126 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN7F */ "", 45127 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN8A */ "", 45128 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN8B */ "", 45129 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN8C */ "", 45130 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN8D */ "", 45131 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN8E */ "", 45132 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN8F */ "", 45133 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN9A */ "", 45134 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN9B */ "", 45135 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN9C */ "", 45136 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN9D */ "", 45137 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN9E */ "", 45138 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAN9F */ "", 45139 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA0 */ "", 45140 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA1 */ "", 45141 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA2 */ "", 45142 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA3 */ "", 45143 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA4 */ "", 45144 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA5 */ "", 45145 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA6 */ "", 45146 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA7 */ "", 45147 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA8 */ "", 45148 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANA9 */ "", 45149 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANAA */ "", 45150 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANAB */ "", 45151 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANAC */ "", 45152 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANAD */ "", 45153 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANAE */ "", 45154 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANAF */ "", 45155 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB0 */ "", 45156 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB1 */ "", 45157 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB2 */ "", 45158 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB3 */ "", 45159 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB4 */ "", 45160 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB5 */ "", 45161 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB6 */ "", 45162 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB7 */ "", 45163 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB8 */ "", 45164 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANB9 */ "", 45165 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANBA */ "", 45166 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANBB */ "", 45167 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANBC */ "", 45168 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANBD */ "", 45169 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANBE */ "", 45170 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANBF */ "", 45171 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC0 */ "", 45172 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC1 */ "", 45173 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC2 */ "", 45174 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC3 */ "", 45175 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC4 */ "", 45176 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC5 */ "", 45177 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC6 */ "", 45178 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC7 */ "", 45179 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC8 */ "", 45180 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANC9 */ "", 45181 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANCA */ "", 45182 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANCB */ "", 45183 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANCC */ "", 45184 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANCD */ "", 45185 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANCE */ "", 45186 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANCF */ "", 45187 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND0 */ "", 45188 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND1 */ "", 45189 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND2 */ "", 45190 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND3 */ "", 45191 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND4 */ "", 45192 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND5 */ "", 45193 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND6 */ "", 45194 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND7 */ "", 45195 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND8 */ "", 45196 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHAND9 */ "", 45197 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANDA */ "", 45198 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANDB */ "", 45199 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANDC */ "", 45200 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANDD */ "", 45201 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANDE */ "", 45202 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANDF */ "", 45203 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE0 */ "", 45204 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE1 */ "", 45205 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE2 */ "", 45206 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE3 */ "", 45207 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE4 */ "", 45208 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE5 */ "", 45209 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE6 */ "", 45210 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE7 */ "", 45211 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE8 */ "", 45212 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANE9 */ "", 45213 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANEA */ "", 45214 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANEB */ "", 45215 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANEC */ "", 45216 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANED */ "", 45217 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANEE */ "", 45218 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANEF */ "", 45219 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF0 */ "", 45220 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF1 */ "", 45221 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF2 */ "", 45222 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF3 */ "", 45223 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF4 */ "", 45224 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF5 */ "", 45225 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF6 */ "", 45226 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF7 */ "", 45227 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF8 */ "", 45228 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANF9 */ "", 45229 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANFA */ "", 45230 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANFB */ "", 45231 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANFC */ "", 45232 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANFD */ "", 45233 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANFE */ "", 45234 /* IHOST_SWSTM_TS_R_VAL_4BYTE_CHANFF */ "", 45235 /* IHP_ACTION_PROFILE_ACCEPTABLE_FRAME_TYPES */ "", 45236 /* IHP_ACTION_PROFILE_IEEE_1588 */ "", 45237 /* IHP_ACTION_PROFILE_PBP_SA_DROP_MAP */ "", 45238 /* IHP_ACTION_PROFILE_SAME_INTERFACE */ "", 45239 /* IHP_ACTION_PROFILE_SA_DROP_MAP */ "", 45240 /* IHP_ACTION_PROFILE_SA_NOT_FOUND_MAP */ "", 45241 /* IHP_ALL_ESADI_RBRIDGES */ "", 45242 /* IHP_ALL_RBRIDGES_MAC_CONFIG */ "", 45243 /* IHP_APPLET_DEFAULT_PARSER_PROGRAM_POINTER */ "", 45244 /* IHP_APP_INJECTTION */ "", 45245 /* IHP_CONSISTENT_HASHING_CONFIGRATION */ "", 45246 /* IHP_COS_PROFILE_TO_USE_LAYER_2_PCP_MAP */ "", 45247 /* IHP_COS_PROFILE_USE_L_2 */ "", 45248 /* IHP_COS_PROFILE_USE_L_3 */ "", 45249 /* IHP_COUNTER_IN_LIF_RANGE_0 */ "", 45250 /* IHP_COUNTER_IN_LIF_RANGE_1 */ "", 45251 /* IHP_DBG_FLP_CONSISTENT_HASHING_PROGRAM */ "", 45252 /* IHP_DBG_FLP_FIFO */ "", 45253 /* IHP_DBG_FLP_LPM */ "", 45254 /* IHP_DBG_FLP_PACKETS_REJECTED_BY_EGW_CNT */ "", 45255 /* IHP_DBG_FLP_PROGRAM_SELECTION_CAM_LINE */ "", 45256 /* IHP_DBG_FLP_SELECTED_PROGRAM */ "", 45257 /* IHP_DBG_FLP_TRAP_0 */ "", 45258 /* IHP_DBG_FLP_TRAP_1 */ "", 45259 /* IHP_DBG_IEEE_1588_IDENTIFICATION_CAM_LINE */ "", 45260 /* IHP_DBG_LLR_TRAP_0 */ "", 45261 /* IHP_DBG_LLR_TRAP_1 */ "", 45262 /* IHP_DE_TO_DP_MAP */ "", 45263 /* IHP_DROP_PRECEDENCE_MAP_PCP */ "", 45264 /* IHP_ECC_1B_ERR_CNT */ "", 45265 /* IHP_ECC_2B_ERR_CNT */ "", 45266 /* IHP_ECC_ERR_1B_INITIATE */ "", 45267 /* IHP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 45268 /* IHP_ECC_ERR_2B_INITIATE */ "", 45269 /* IHP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 45270 /* IHP_ECC_INTERRUPT_REGISTER */ "", 45271 /* IHP_ECC_INTERRUPT_REGISTER_MASK */ "", 45272 /* IHP_ECC_INTERRUPT_REGISTER_TEST */ "", 45273 /* IHP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 45274 /* IHP_ERROR_INITIATION_DATA */ "", 45275 /* IHP_ETHERNET_ACTION_PROFILES */ "", 45276 /* IHP_ETHERNET_TAG_FORMAT */ "", 45277 /* IHP_ETHER_IP_CONFIG */ "", 45278 /* IHP_FC_ACTION_PROFILES */ "", 45279 /* IHP_FILTERING_ACTION_PROFILES */ "", 45280 /* IHP_FLPA_FIFO_CONFIG */ "", 45281 /* IHP_FLP_FIFOS_SKIP_ENTRY */ "", 45282 /* IHP_FLP_GENERAL_CFG */ "", 45283 /* IHP_FLP_PFC_IS_ETH */ "", 45284 /* IHP_FLP_PFC_IS_IPV4 */ "", 45285 /* IHP_FLP_PFC_IS_IPV6 */ "", 45286 /* IHP_FLP_PFC_IS_MPLS */ "", 45287 /* IHP_FLP_PFC_MPLS_P2P */ "", 45288 /* IHP_GENERAL_TRAP */ "", 45289 /* IHP_GLOBAL_GENERAL_CFG_3 */ "", 45290 /* IHP_GLOBAL_MEM_OPTIONS */ "", 45291 /* IHP_GLOBAL_PP_2 */ "", 45292 /* IHP_GLOBAL_PP_3 */ "", 45293 /* IHP_GLOBAL_PP_4 */ "", 45294 /* IHP_GLOBAL_PP_5 */ "", 45295 /* IHP_GLOBAL_PP_6 */ "", 45296 /* IHP_GLOBAL_PP_7 */ "", 45297 /* IHP_GLOBAL_PP_8 */ "", 45298 /* IHP_GRE_ETHERNET_TYPE_CUSTOM */ "", 45299 /* IHP_GRE_ETHERNET_TYPE_ETHERNET */ "", 45300 /* IHP_GRE_ETHERNET_TYPE_IPV4 */ "", 45301 /* IHP_GRE_ETHERNET_TYPE_IPV6 */ "", 45302 /* IHP_GRE_ETHERNET_TYPE_MPLS */ "", 45303 /* IHP_GRE_ETH_TYPE_CUSTOM */ "", 45304 /* IHP_GRE_ETH_TYPE_ETHERNET */ "", 45305 /* IHP_GRE_ETH_TYPE_IPV4 */ "", 45306 /* IHP_GRE_ETH_TYPE_IPV6 */ "", 45307 /* IHP_GRE_ETH_TYPE_MPLS */ "", 45308 /* IHP_GTIMER_CONFIGURATION */ "", 45309 /* IHP_GTIMER_TRIGGER */ "", 45310 /* IHP_HEADER_STACK_EXCEED_PROGRAM_ADDRESS */ "", 45311 /* IHP_HIGH_VSI_CONFIG */ "", 45312 /* IHP_HIGH_VSI_PROFILE */ "", 45313 /* IHP_ICMP_ACTION_PROFILES */ "", 45314 /* IHP_IGMP_ACTION_PROFILES */ "", 45315 /* IHP_IHP_ENABLERS */ "", 45316 /* IHP_INCOMING_UP_MAP */ "", 45317 /* IHP_INDIRECT_COMMAND */ "", 45318 /* IHP_INDIRECT_COMMAND_ADDRESS */ "", 45319 /* IHP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 45320 /* IHP_INDIRECT_COMMAND_RD_DATA */ "", 45321 /* IHP_INDIRECT_COMMAND_WIDE_MEM */ "", 45322 /* IHP_INDIRECT_COMMAND_WR_DATA */ "", 45323 /* IHP_INDIRECT_FORCE_BUBBLE */ "", 45324 /* IHP_INDIRECT_WR_MASK */ "", 45325 /* IHP_INITIAL_VLAN_ACTION_PROFILES */ "", 45326 /* IHP_INITIATE_ECC_1B_ERRORS */ "", 45327 /* IHP_INITIATE_ECC_2B_ERRORS */ "", 45328 /* IHP_INITIATE_PAR_ERR */ "", 45329 /* IHP_INNER_ETHERNET_TRAP */ "", 45330 /* IHP_INNER_ETHERNET_TRAP_ACTION_PROFILE_VECTOR */ "", 45331 /* IHP_INTERNAL_FIELDS_DATA */ "", 45332 /* IHP_INTERRUPT_MASK_REGISTER */ "", 45333 /* IHP_INTERRUPT_REGISTER */ "", 45334 /* IHP_INTERRUPT_REGISTER_TEST */ "", 45335 /* IHP_IPV4_ACTION_PROFILES */ "", 45336 /* IHP_IPV6_ACTION_PROFILES_0 */ "", 45337 /* IHP_IPV6_ACTION_PROFILES_1 */ "", 45338 /* IHP_IP_DEFAULT_ETHERNET_VSI */ "", 45339 /* IHP_IP_TOS_TO_OAM_PCP_0 */ "", 45340 /* IHP_IP_TOS_TO_OAM_PCP_1 */ "", 45341 /* IHP_ISA_CAM_ENTRIES_COUNTER */ "", 45342 /* IHP_ISA_DIAGNOSTICS */ "", 45343 /* IHP_ISA_DIAGNOSTICS_ACCESSED_MODE */ "", 45344 /* IHP_ISA_DIAGNOSTICS_INDEX */ "", 45345 /* IHP_ISA_DIAGNOSTICS_KEY */ "", 45346 /* IHP_ISA_DIAGNOSTICS_LOOKUP_RESULT */ "", 45347 /* IHP_ISA_DIAGNOSTICS_READ_RESULT */ "", 45348 /* IHP_ISA_ENTRIES_COUNTER */ "", 45349 /* IHP_ISA_ERROR_CAM_TABLE_FULL_COUNTER */ "", 45350 /* IHP_ISA_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 45351 /* IHP_ISA_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 45352 /* IHP_ISA_ERROR_TABLE_COHERENCY_COUNTER */ "", 45353 /* IHP_ISA_GENERAL_EM_CONFIGURATION_REGISTER */ "", 45354 /* IHP_ISA_INTERRUPT_MASK_REGISTER_ONE */ "", 45355 /* IHP_ISA_INTERRUPT_REGISTER_ONE */ "", 45356 /* IHP_ISA_INTERRUPT_REGISTER_ONE_TEST */ "", 45357 /* IHP_ISA_KEY_TABLE_ENTRY_LIMIT */ "", 45358 /* IHP_ISA_LAST_LOOKUP */ "", 45359 /* IHP_ISA_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 45360 /* IHP_ISA_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 45361 /* IHP_ISA_MANAGEMENT_UNIT_FAILURE */ "", 45362 /* IHP_ISA_REQUESTS_COUNTER */ "", 45363 /* IHP_ISA_RESET_STATUS_REGISTER */ "", 45364 /* IHP_ISA_WARNING_INSERTED_EXISTING_COUNTER */ "", 45365 /* IHP_ISB_CAM_ENTRIES_COUNTER */ "", 45366 /* IHP_ISB_DIAGNOSTICS */ "", 45367 /* IHP_ISB_DIAGNOSTICS_ACCESSED_MODE */ "", 45368 /* IHP_ISB_DIAGNOSTICS_INDEX */ "", 45369 /* IHP_ISB_DIAGNOSTICS_KEY */ "", 45370 /* IHP_ISB_DIAGNOSTICS_LOOKUP_RESULT */ "", 45371 /* IHP_ISB_DIAGNOSTICS_READ_RESULT */ "", 45372 /* IHP_ISB_ENTRIES_COUNTER */ "", 45373 /* IHP_ISB_ERROR_CAM_TABLE_FULL_COUNTER */ "", 45374 /* IHP_ISB_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 45375 /* IHP_ISB_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 45376 /* IHP_ISB_ERROR_TABLE_COHERENCY_COUNTER */ "", 45377 /* IHP_ISB_GENERAL_EM_CONFIGURATION_REGISTER */ "", 45378 /* IHP_ISB_INTERRUPT_MASK_REGISTER_ONE */ "", 45379 /* IHP_ISB_INTERRUPT_REGISTER_ONE */ "", 45380 /* IHP_ISB_INTERRUPT_REGISTER_ONE_TEST */ "", 45381 /* IHP_ISB_KEY_TABLE_ENTRY_LIMIT */ "", 45382 /* IHP_ISB_LAST_LOOKUP */ "", 45383 /* IHP_ISB_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 45384 /* IHP_ISB_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 45385 /* IHP_ISB_MANAGEMENT_UNIT_FAILURE */ "", 45386 /* IHP_ISB_REQUESTS_COUNTER */ "", 45387 /* IHP_ISB_RESET_STATUS_REGISTER */ "", 45388 /* IHP_ISB_WARNING_INSERTED_EXISTING_COUNTER */ "", 45389 /* IHP_LAST_GENERATED_VALUES */ "", 45390 /* IHP_LAST_RECEIVED_HEADER_REG_0 */ "", 45391 /* IHP_LAST_RECEIVED_HEADER_REG_1 */ "", 45392 /* IHP_LAST_RECEIVED_PORT */ "", 45393 /* IHP_LEARNING_CFG */ "", 45394 /* IHP_LEARN_DATA_VALUES_0 */ "", 45395 /* IHP_LEARN_DATA_VALUES_1 */ "", 45396 /* IHP_LINK_LAYER_LOOKUP_CFG */ "", 45397 /* IHP_LLR_FIFO_P_14_PIPE_FIXED_DELAY */ "", 45398 /* IHP_LLR_FIFO_P_14_PIPE_SKIP_ENTRY */ "", 45399 /* IHP_LL_MIRROR_VID_01 */ "", 45400 /* IHP_LL_MIRROR_VID_23 */ "", 45401 /* IHP_LL_MIRROR_VID_45 */ "", 45402 /* IHP_LSR_ACTION_PROFILE */ "", 45403 /* IHP_LSR_ELSP_RANGE */ "", 45404 /* IHP_LSR_P2P_SERVICE_CFG */ "", 45405 /* IHP_L_4_PORT_RANGES_2_TC_TABLE */ "", 45406 /* IHP_MACT_AGE_AGING_MODE */ "", 45407 /* IHP_MACT_AGE_AGING_RESOLUTION */ "", 45408 /* IHP_MACT_AGE_MACHINE_CONFIGURATION */ "", 45409 /* IHP_MACT_AGE_MACHINE_CURRENT_INDEX */ "", 45410 /* IHP_MACT_AGE_MACHINE_META_CYCLE */ "", 45411 /* IHP_MACT_AGE_MACHINE_STATUS */ "", 45412 /* IHP_MACT_AR_TO_PB_TRANSLATION_ERR_EVENT_COUNTER */ "", 45413 /* IHP_MACT_CAM_ENTRIES_COUNTER */ "", 45414 /* IHP_MACT_CMD_TO_CMD_TRANSLATION */ "", 45415 /* IHP_MACT_COUNTER_DB_CNTR_PTR_CONFIGURATION */ "", 45416 /* IHP_MACT_COUNTER_DB_LIF_PTR_RANGE_MAP */ "", 45417 /* IHP_MACT_COUNTER_LIMIT_CONFIGURATION */ "", 45418 /* IHP_MACT_COUNTER_LIMIT_MACT_DB_ENTRIES_COUNT */ "", 45419 /* IHP_MACT_CPU_REQUEST_REQUEST */ "", 45420 /* IHP_MACT_CPU_REQUEST_TRIGGER */ "", 45421 /* IHP_MACT_DIAGNOSTICS */ "", 45422 /* IHP_MACT_DIAGNOSTICS_ACCESSED_MODE */ "", 45423 /* IHP_MACT_DIAGNOSTICS_INDEX */ "", 45424 /* IHP_MACT_DIAGNOSTICS_KEY */ "", 45425 /* IHP_MACT_DIAGNOSTICS_LOOKUP_RESULT */ "", 45426 /* IHP_MACT_DIAGNOSTICS_READ_RESULT */ "", 45427 /* IHP_MACT_EGRESS_OPPORTUNISTIC_FIFO_DROP_COUNTER */ "", 45428 /* IHP_MACT_ENTRIES_COUNTER */ "", 45429 /* IHP_MACT_ERROR_CAM_TABLE_FULL_COUNTER */ "", 45430 /* IHP_MACT_ERROR_CHANGE_FAIL_NON_EXIST_COUNTER */ "", 45431 /* IHP_MACT_ERROR_CHANGE_REQUEST_OVER_STATIC_COUNTER */ "", 45432 /* IHP_MACT_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 45433 /* IHP_MACT_ERROR_LEARN_REQUEST_OVER_STATIC_COUNTER */ "", 45434 /* IHP_MACT_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 45435 /* IHP_MACT_ERROR_TABLE_COHERENCY_COUNTER */ "", 45436 /* IHP_MACT_EVENT */ "", 45437 /* IHP_MACT_EVENT_EXCEED_LIMIT_COUNTERS */ "", 45438 /* IHP_MACT_EVENT_FID_OR_LIF_EXCEED_LIMIT_CNTR_PTR */ "", 45439 /* IHP_MACT_EVENT_FIFO_CONFIGURATION */ "", 45440 /* IHP_MACT_EVENT_FIFO_EVENT_COUNTER */ "", 45441 /* IHP_MACT_EVENT_FIFO_EVENT_DROP_COUNTERS */ "", 45442 /* IHP_MACT_EVENT_FIFO_EVENT_FIFO_ENTRY_COUNT */ "", 45443 /* IHP_MACT_EVENT_FIFO_HIGH_THRESHOLD */ "", 45444 /* IHP_MACT_EVENT_FIFO_WATERMARK */ "", 45445 /* IHP_MACT_FCNT_RESET_SEQUENCE_CONTROL */ "", 45446 /* IHP_MACT_FLU_MACHINE_CONFIGURATION */ "", 45447 /* IHP_MACT_FLU_MACHINE_CURRENT_INDEX */ "", 45448 /* IHP_MACT_FLU_MACHINE_END_INDEX */ "", 45449 /* IHP_MACT_FLU_MACHINE_HIT_COUNTER */ "", 45450 /* IHP_MACT_FLU_MACHINE_STATUS */ "", 45451 /* IHP_MACT_GENERAL_EM_CONFIGURATION_REGISTER */ "", 45452 /* IHP_MACT_INGRESS_LEARN_TYPE */ "", 45453 /* IHP_MACT_INTERRUPT_MASK_REGISTER_ONE */ "", 45454 /* IHP_MACT_INTERRUPT_MASK_REGISTER_THREE */ "", 45455 /* IHP_MACT_INTERRUPT_MASK_REGISTER_TWO */ "", 45456 /* IHP_MACT_INTERRUPT_REGISTER_ONE */ "", 45457 /* IHP_MACT_INTERRUPT_REGISTER_ONE_TEST */ "", 45458 /* IHP_MACT_INTERRUPT_REGISTER_THREE */ "", 45459 /* IHP_MACT_INTERRUPT_REGISTER_THREE_TEST */ "", 45460 /* IHP_MACT_INTERRUPT_REGISTER_TWO */ "", 45461 /* IHP_MACT_INTERRUPT_REGISTER_TWO_TEST */ "", 45462 /* IHP_MACT_KEY_TABLE_ENTRY_LIMIT */ "", 45463 /* IHP_MACT_LEARN_FILTER_PROPERTIES */ "", 45464 /* IHP_MACT_LEARN_LOOKUP_EGRESS_LOOKUP_COUNTER */ "", 45465 /* IHP_MACT_LEARN_LOOKUP_GENERAL_CONFIGURATION */ "", 45466 /* IHP_MACT_LEARN_LOOKUP_INGRESS_LOOKUP_COUNTER */ "", 45467 /* IHP_MACT_LEARN_NOT_NEEDED_DROP_COUNTER */ "", 45468 /* IHP_MACT_LEL_ERR_DATA */ "", 45469 /* IHP_MACT_LOOKUP_ARBITER_DESTINATION_LOOKUP_COUNTER */ "", 45470 /* IHP_MACT_LOOKUP_ARBITER_LEARN_LOOKUP_COUNTER */ "", 45471 /* IHP_MACT_LOOKUP_ARBITER_LINK_LAYER_LOOKUP_COUNTER */ "", 45472 /* IHP_MACT_LOOKUP_ARBITER_SOURCE_LOOKUP_COUNTER */ "", 45473 /* IHP_MACT_LOOKUP_BURST_FIFO_PROPERTIES */ "", 45474 /* IHP_MACT_LOOKUP_FILTER_PROPERTIES */ "", 45475 /* IHP_MACT_LOOKUP_LOOKUP_MODE */ "", 45476 /* IHP_MACT_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 45477 /* IHP_MACT_MANAGEMENT_UNIT_FAILURE */ "", 45478 /* IHP_MACT_MNGMNT_REQ_CONFIGURATION */ "", 45479 /* IHP_MACT_MNGMNT_REQ_COUNTERS_A */ "", 45480 /* IHP_MACT_MNGMNT_REQ_COUNTERS_B */ "", 45481 /* IHP_MACT_MNGMNT_REQ_COUNTERS_C */ "", 45482 /* IHP_MACT_MNGMNT_REQ_EXCEED_LIMIT_CPU_ALLOWED_FID */ "", 45483 /* IHP_MACT_MNGMNT_REQ_EXCEED_LIMIT_FID */ "", 45484 /* IHP_MACT_MNGMNT_REQ_EXCEED_LIMIT_STATIC_ALLOWED_FID */ "", 45485 /* IHP_MACT_MNGMNT_REQ_FLU_DB_CONFIGURATION */ "", 45486 /* IHP_MACT_MNGMNT_REQ_REQUEST_COUNTER */ "", 45487 /* IHP_MACT_MNGMNT_REQ_REQUEST_FIFO_ENTRY_COUNT */ "", 45488 /* IHP_MACT_MNGMNT_REQ_REQUEST_FIFO_WATERMARK */ "", 45489 /* IHP_MACT_OLP_REQUEST_REQUEST */ "", 45490 /* IHP_MACT_OLP_REQUEST_TRIGGER */ "", 45491 /* IHP_MACT_PB_TO_AR_TRANSLATION_ERR_LEARN_COUNTER */ "", 45492 /* IHP_MACT_PB_TO_AR_TRANSLATION_ERR_REQUEST_COUNTER */ "", 45493 /* IHP_MACT_REPLY */ "", 45494 /* IHP_MACT_REPLY_FIFO_CONFIGURATION */ "", 45495 /* IHP_MACT_REPLY_FIFO_HIGH_THRESHOLD */ "", 45496 /* IHP_MACT_REPLY_FIFO_REPLY_COUNTER */ "", 45497 /* IHP_MACT_REPLY_FIFO_REPLY_DROP_COUNTERS */ "", 45498 /* IHP_MACT_REPLY_FIFO_REPLY_FIFO_ENTRY_COUNT */ "", 45499 /* IHP_MACT_REPLY_FIFO_WATERMARK */ "", 45500 /* IHP_MACT_REQUESTS_COUNTER */ "", 45501 /* IHP_MACT_RESET_STATUS_REGISTER */ "", 45502 /* IHP_MACT_WARNING_CHANGE_NON_EXIST_FROM_OTHER_COUNTER */ "", 45503 /* IHP_MACT_WARNING_CHANGE_NON_EXIST_FROM_SELF_COUNTER */ "", 45504 /* IHP_MACT_WARNING_INSERTED_EXISTING_COUNTER */ "", 45505 /* IHP_MACT_WARNING_LEARN_OVER_EXISTING_COUNTER */ "", 45506 /* IHP_MAC_LAYER_TRAP_ARP */ "", 45507 /* IHP_MAC_LAYER_TRAP_DHCP */ "", 45508 /* IHP_MAC_LAYER_TRAP_ICMP */ "", 45509 /* IHP_MAC_LAYER_TRAP_IGMP */ "", 45510 /* IHP_MAP_NEXT_PROTOCOL_TO_FWD_CODE */ "", 45511 /* IHP_MAP_VRID_TO_IP_VERSION */ "", 45512 /* IHP_MEF_L_2_CP_DROP_BITMAP */ "", 45513 /* IHP_MEF_L_2_CP_PEER_BITMAP */ "", 45514 /* IHP_MEF_L_2_CP_TRANSPARENT_BITMAP */ "", 45515 /* IHP_METER_TRAFFIC_CLASS_BITMAP */ "", 45516 /* IHP_MPLS_ACTION_PROFILES */ "", 45517 /* IHP_MPLS_EXP_MAP */ "", 45518 /* IHP_MPLS_LABEL_PROCEDURE_CONFIG */ "", 45519 /* IHP_MPLS_LABEL_RANGE_BASE_LIF */ "", 45520 /* IHP_MPLS_LABEL_RANGE_HIGH */ "", 45521 /* IHP_MPLS_LABEL_RANGE_LOW */ "", 45522 /* IHP_MPLS_LABEL_TERMINATION_ERROR_DATA */ "", 45523 /* IHP_MPLS_SPECIAL_LABELS_TO_TERMINATE */ "", 45524 /* IHP_MPLS_SPECIAL_LABEL_PROFILE_TABLE */ "", 45525 /* IHP_MY_ARP_IP_1 */ "", 45526 /* IHP_MY_ARP_IP_2 */ "", 45527 /* IHP_MY_B_MAC_LSB_BITMAP */ "", 45528 /* IHP_MY_B_MAC_MC */ "", 45529 /* IHP_MY_B_MAC_MSB */ "", 45530 /* IHP_MY_MAC */ "", 45531 /* IHP_MY_TRILL_NICKNAME */ "", 45532 /* IHP_OAM_BFD_MISCONFIG */ "", 45533 /* IHP_OAM_BFD_OVER_IP_CFG */ "", 45534 /* IHP_OAM_BFD_YOUR_DISCR_TO_LIF_CFG */ "", 45535 /* IHP_OAM_COUNTER_DISABLE_INNER_MAP */ "", 45536 /* IHP_OAM_COUNTER_DISABLE_MAP */ "", 45537 /* IHP_OAM_COUNTER_DISABLE_OUTER_MAP */ "", 45538 /* IHP_OAM_COUNTER_INCREMENT_BITMAP */ "", 45539 /* IHP_OAM_COUNTER_IN_RANGE_CFG */ "", 45540 /* IHP_OAM_COUNTER_NOT_IN_RANGE_CFG */ "", 45541 /* IHP_OAM_COUNTER_RANGE */ "", 45542 /* IHP_OAM_DEFAULT_ACC_MEP_PROFILES */ "", 45543 /* IHP_OAM_DEFAULT_COUNTERS */ "", 45544 /* IHP_OAM_DEFAULT_MP_TYPE_VECTOR */ "", 45545 /* IHP_OAM_EGRESS_KEY_SELECT */ "", 45546 /* IHP_OAM_ETHERNET_CFG */ "", 45547 /* IHP_OAM_IDENTIFICATION_ENABLE */ "", 45548 /* IHP_OAM_INGRESS_KEY_SELECT */ "", 45549 /* IHP_OAM_IN_LIF_PROFILE_MAP */ "", 45550 /* IHP_OAM_MP_TYPE_MAP */ "", 45551 /* IHP_OAM_PACKET_INJECTED_BITMAP */ "", 45552 /* IHP_OAM_PDU_DS_TO_PCP_0 */ "", 45553 /* IHP_OAM_PDU_DS_TO_PCP_1 */ "", 45554 /* IHP_OAM_PDU_DS_TO_PCP_2 */ "", 45555 /* IHP_OEMA_LKP_DISABLE */ "", 45556 /* IHP_OEMB_LKP_DISABLE */ "", 45557 /* IHP_PARITY_ERR_CNT */ "", 45558 /* IHP_PARSER_PEM_PROGRAM_ENCOUNTERED */ "", 45559 /* IHP_PAR_0_ERR_MEM_MASK */ "", 45560 /* IHP_PAR_1_ERR_MEM_MASK */ "", 45561 /* IHP_PAR_3_ERR_MEM_MASK */ "", 45562 /* IHP_PAR_ERR_INITIATE */ "", 45563 /* IHP_PAR_ERR_MEM_MASK */ "", 45564 /* IHP_PAR_ERR_MONITOR_MEM_MASK */ "", 45565 /* IHP_PBP_ACTION_PROFILES */ "", 45566 /* IHP_PBP_TE_BVID_RANGE */ "", 45567 /* IHP_PCMI_0 */ "", 45568 /* IHP_PCMI_1 */ "", 45569 /* IHP_PCMI_2 */ "", 45570 /* IHP_PCMI_3 */ "", 45571 /* IHP_PCMI_4 */ "", 45572 /* IHP_PCMI_0_S */ "", 45573 /* IHP_PCMI_0_T */ "", 45574 /* IHP_PCMI_1_S */ "", 45575 /* IHP_PCMI_1_T */ "", 45576 /* IHP_PCMI_2_S */ "", 45577 /* IHP_PCMI_2_T */ "", 45578 /* IHP_PCMI_3_S */ "", 45579 /* IHP_PCMI_3_T */ "", 45580 /* IHP_PCMI_4_S */ "", 45581 /* IHP_PCMI_4_T */ "", 45582 /* IHP_PCP_DECODING_TABLE */ "", 45583 /* IHP_PFC_IS_ETHERNET */ "", 45584 /* IHP_PFC_IS_IPV4 */ "", 45585 /* IHP_PFC_IS_IPV6 */ "", 45586 /* IHP_PFC_IS_MPLS */ "", 45587 /* IHP_PFC_IS_MPLS_OVER_IPV4 */ "", 45588 /* IHP_PFC_IS_MPLS_OVER_IPV6 */ "", 45589 /* IHP_PFC_IS_TRILL */ "", 45590 /* IHP_PFC_IS_UD */ "", 45591 /* IHP_PROGRAM_ILLEGEL_ADDRESS */ "", 45592 /* IHP_PROTOCOL_TRAPS_PROGRAM_SELECT */ "", 45593 /* IHP_PRSRA_FIFO_CONFIG */ "", 45594 /* IHP_RCVD_PACKET_COUNTER */ "", 45595 /* IHP_REG_0070 */ "", 45596 /* IHP_REG_0071 */ "", 45597 /* IHP_REG_0072 */ "", 45598 /* IHP_REG_0073 */ "", 45599 /* IHP_REG_0080 */ "", 45600 /* IHP_REG_0084 */ "", 45601 /* IHP_REG_0085 */ "", 45602 /* IHP_REG_0110 */ "", 45603 /* IHP_REG_0111 */ "", 45604 /* IHP_REG_0119 */ "", 45605 /* IHP_REG_0146 */ "", 45606 /* IHP_REG_0150 */ "", 45607 /* IHP_REG_0154 */ "", 45608 /* IHP_REG_0166 */ "", 45609 /* IHP_REG_0174 */ "", 45610 /* IHP_REG_0201 */ "", 45611 /* IHP_REG_0232 */ "", 45612 /* IHP_REG_0261 */ "", 45613 /* IHP_REG_0273 */ "", 45614 /* IHP_REG_0400 */ "", 45615 /* IHP_REG_0401 */ "", 45616 /* IHP_REG_0402 */ "", 45617 /* IHP_REG_0480 */ "", 45618 /* IHP_REG_0500 */ "", 45619 /* IHP_REG_007A */ "", 45620 /* IHP_REG_00A0 */ "", 45621 /* IHP_REG_00A3 */ "", 45622 /* IHP_REG_00A4 */ "", 45623 /* IHP_REG_00A5 */ "", 45624 /* IHP_REG_00A6 */ "", 45625 /* IHP_REG_00AA */ "", 45626 /* IHP_REG_00AE */ "", 45627 /* IHP_REG_00B0 */ "", 45628 /* IHP_REG_00B1 */ "", 45629 /* IHP_REG_00B2 */ "", 45630 /* IHP_REG_00B3 */ "", 45631 /* IHP_REG_00C1 */ "", 45632 /* IHP_REG_00CF */ "", 45633 /* IHP_REG_00D2 */ "", 45634 /* IHP_REG_00D3 */ "", 45635 /* IHP_REG_00D4 */ "", 45636 /* IHP_REG_00D5 */ "", 45637 /* IHP_REG_00D6 */ "", 45638 /* IHP_REG_00D9 */ "", 45639 /* IHP_REG_00DA */ "", 45640 /* IHP_REG_00DB */ "", 45641 /* IHP_REG_00E0 */ "", 45642 /* IHP_REG_00E1 */ "", 45643 /* IHP_REG_010C */ "", 45644 /* IHP_REG_010D */ "", 45645 /* IHP_REG_01CC */ "", 45646 /* IHP_REG_01CD */ "", 45647 /* IHP_REG_01CE */ "", 45648 /* IHP_REG_01CF */ "", 45649 /* IHP_REG_01D4 */ "", 45650 /* IHP_REG_01D5 */ "", 45651 /* IHP_REG_022B */ "", 45652 /* IHP_REG_022C */ "", 45653 /* IHP_REG_028A */ "", 45654 /* IHP_REG_02A1 */ "", 45655 /* IHP_REG_02B3 */ "", 45656 /* IHP_RESERVED_MIRROR_ADDR */ "", 45657 /* IHP_RESERVED_MTCD */ "", 45658 /* IHP_RESERVED_MTCP */ "", 45659 /* IHP_RESERVED_PCMI_0 */ "", 45660 /* IHP_RESERVED_PCMI_1 */ "", 45661 /* IHP_RESERVED_PCMI_2 */ "", 45662 /* IHP_RESERVED_PCMI_3 */ "", 45663 /* IHP_RESERVED_PCMI_4 */ "", 45664 /* IHP_RESERVED_PCMI_0_S */ "", 45665 /* IHP_RESERVED_PCMI_0_T */ "", 45666 /* IHP_RESERVED_PCMI_1_S */ "", 45667 /* IHP_RESERVED_PCMI_1_T */ "", 45668 /* IHP_RESERVED_PCMI_2_S */ "", 45669 /* IHP_RESERVED_PCMI_2_T */ "", 45670 /* IHP_RESERVED_PCMI_3_S */ "", 45671 /* IHP_RESERVED_PCMI_3_T */ "", 45672 /* IHP_RESERVED_PCMI_4_S */ "", 45673 /* IHP_RESERVED_PCMI_4_T */ "", 45674 /* IHP_RESERVED_SPARE_0 */ "", 45675 /* IHP_RESERVED_SPARE_1 */ "", 45676 /* IHP_RESERVED_SPARE_2 */ "", 45677 /* IHP_RESERVED_SPARE_3 */ "", 45678 /* IHP_RFC_6374_FLAGS */ "", 45679 /* IHP_RPF_CFG */ "", 45680 /* IHP_SA_LOOKUP_RESULT_MAPPING */ "", 45681 /* IHP_SBUS_BROADCAST_ID */ "", 45682 /* IHP_SBUS_LAST_IN_CHAIN */ "", 45683 /* IHP_SERVICE_TYPE_VALUES */ "", 45684 /* IHP_SHARED_BFID */ "", 45685 /* IHP_SYNC_COUNTER */ "", 45686 /* IHP_TCP_ACTION_PROFILES */ "", 45687 /* IHP_TM_FORWARDING_OFFSET_INDEX_MAPPING */ "", 45688 /* IHP_TPID_ADDITIONAL_VALUES */ "", 45689 /* IHP_TRAFFIC_CLASS_L_4_RANGE */ "", 45690 /* IHP_TRAFFIC_CLASS_L_4_RANGE_CFG */ "", 45691 /* IHP_TRAFFIC_CLASS_TO_USER_PRIORITY */ "", 45692 /* IHP_TRILL_DEFAULT_VSI */ "", 45693 /* IHP_TT_LIF_BANK_CONTETION_STATUS */ "", 45694 /* IHP_UDP_ACTION_PROFILES */ "", 45695 /* IHP_UNDEF_PROGRAM_DATA */ "", 45696 /* IHP_VRID_MY_MAC */ "", 45697 /* IHP_VSD_GENERAL_CFGS */ "", 45698 /* IHP_VSI_MASKS_BASE */ "", 45699 /* IHP_VSI_MASKS_KEY_A */ "", 45700 /* IHP_VSI_MASKS_KEY_B */ "", 45701 /* IHP_VSI_MASKS_KEY_C */ "", 45702 /* IHP_VSI_MASKS_RESULT_A */ "", 45703 /* IHP_VSI_MASKS_RESULT_B */ "", 45704 /* IHP_VSI_MASKS_RESULT_C */ "", 45705 /* IHP_VSI_MASK_PROFILE_MAP */ "", 45706 /* IHP_VSI_PROFILE_TO_VSI_ASSIGNMENT_MODE_TABLE */ "", 45707 /* IHP_VSI_PROFILE_TO_VSI_TABLE */ "", 45708 /* IHP_VTT_FEC_POINTER_PREFIX */ "", 45709 /* IHP_VTT_FIFOS_SKIP_ENTRY */ "", 45710 /* IHP_VTT_FLOW_ID_PREFIX */ "", 45711 /* IHP_VTT_GENERAL_CONFIGS_0 */ "", 45712 /* IHP_VTT_GENERAL_CONFIGS_1 */ "", 45713 /* IHP_VTT_INNER_ETHERNET_TERMINATION_ACTION */ "", 45714 /* IHP_VTT_MAP_0_DSCP_EXP_INDEX */ "", 45715 /* IHP_VTT_MAP_1_DSCP_EXP_INDEX */ "", 45716 /* IHP_VTT_MAX_IN_LIF_CFG */ "", 45717 /* IHP_VTT_MPLS_DUMMY_LIF */ "", 45718 /* IHP_VTT_MPLS_ENH_DUMMY_LIF_TERMINATION_PROFILE */ "", 45719 /* IHP_VTT_MPLS_ENH_EXCLUDE_SPECIAL_LABEL_BIT_MAP */ "", 45720 /* IHP_VTT_MPLS_ILLEGAL_LABEL_TRAP */ "", 45721 /* IHP_VTT_MPLS_ILLEGAL_RSRVD_LABEL_TRAP */ "", 45722 /* IHP_VTT_MPLS_LABEL_RANGE_PROFILE */ "", 45723 /* IHP_VTT_MPLS_TERMINATE_FIRST_LABEL_BIT_MAP */ "", 45724 /* IHP_VTT_MPLS_USE_HEADER_OFFSET_3_BIT_MAP */ "", 45725 /* IHP_VTT_PROGRAM_ENCOUNTERED */ "", 45726 /* IHP_VTT_TRAPS_ENCOUNTERED */ "", 45727 /* IHP_VTT_TRAP_STRENGTHS_0 */ "", 45728 /* IHP_VTT_TRAP_STRENGTHS_1 */ "", 45729 /* IHP_VTT_TRAP_STRENGTHS_2 */ "", 45730 /* IHP_VTT_TRAP_STRENGTHS_3 */ "", 45731 /* IHP_VTT_TRAP_STRENGTHS_4 */ "", 45732 /* IHP_VTT_TRAP_STRENGTHS_5 */ "", 45733 /* IHP_VTT_TRAP_STRENGTHS_6 */ "", 45734 /* IHP_VTT_TRAP_STRENGTHS_8 */ "", 45735 /* IHP_VTT_TRAP_STRENGTHS_9 */ "", 45736 /* IHP_VTT_TRAP_STRENGTHS_10 */ "", 45737 /* IHP_VTT_UNKNOWN_L_3_TRAP_STRENGTHS */ "", 45738 /* IHP_VT_LIF_BANK_CONTETION_STATUS */ "", 45739 /* IING_EGRMSKBMAP */ "", 45740 /* IING_EGRMSKBMAP_64 */ "IING_EGRMSKBMAP", 45741 /* IING_EGRMSKBMAP_HI */ "IING_EGRMSKBMAP_HI", 45742 /* IING_EGRMSKBMAP_LO */ "IING_EGRMSKBMAP_LO", 45743 /* IIPMC */ "", 45744 /* IIPMC_64 */ "IIPMC", 45745 /* IIRSEL_TM_REG_1 */ "", 45746 /* IKNOWN_MCAST_BLOCK_MASK */ "", 45747 /* IKNOWN_MCAST_BLOCK_MASK_64 */ "IKNOWN_MCAST_BLOCK_MASK", 45748 /* IKNOWN_MCAST_BLOCK_MASK_HI */ "IKNOWN_MCAST_BLOCK_MASK_HI", 45749 /* IKNOWN_MCAST_BLOCK_MASK_LO */ "IKNOWN_MCAST_BLOCK_MASK_LO", 45750 /* IL2L3_BUS_SER_CONTROL */ "", 45751 /* IL2LU_CONTROL */ "", 45752 /* IL2LU_INTR_ENABLE */ "", 45753 /* IL2LU_INTR_STATUS */ "", 45754 /* IL2LU_PWR_WATCH_DOG_CONTROL */ "", 45755 /* IL2LU_PWR_WATCH_DOG_STATUS */ "", 45756 /* IL2LU_SER_CONTROL */ "", 45757 /* IL2LU_TM_REG_1 */ "", 45758 /* IL2LU_WW_REG_1 */ "", 45759 /* IL2MC_TM_REG_1 */ "", 45760 /* IL3LU_CONTROL */ "", 45761 /* IL3LU_TM_REG_1 */ "", 45762 /* IL3MC_ERBFIFO_STATUS */ "", 45763 /* IL3MC_ERB_CTL */ "", 45764 /* IL3MC_ERB_INTR_CLEAR */ "", 45765 /* IL3MC_ERB_INTR_ENABLE */ "", 45766 /* IL3MC_ERB_INTR_STATUS */ "", 45767 /* IL3MC_EXTFP_POLICY_DED_INFO */ "", 45768 /* IL3MC_EXTFP_POLICY_SEC_INFO */ "", 45769 /* IL3MC_FP0RSPFIFO_RS_CTL */ "", 45770 /* IL3MC_FP0RSPFIFO_RS_STATUS */ "", 45771 /* IL3MC_FP1RSPFIFO_RS_CTL */ "", 45772 /* IL3MC_FP1RSPFIFO_RS_STATUS */ "", 45773 /* IL3MC_FPCREQFIFO_WS_STATUS */ "", 45774 /* IL3MC_IPCF_PTR_MISMATCH_INFO */ "", 45775 /* IL3MC_L2L3RSPFIFO_RS_CTL */ "", 45776 /* IL3MC_L2L3RSPFIFO_RS_STATUS */ "", 45777 /* IL3MC_TM_REG_1 */ "", 45778 /* ILAMAC_DEBUG_COUNT */ "", 45779 /* ILAMAC_RX_ALIGNMENT_ERRORS_COUNT */ "", 45780 /* ILAMAC_RX_ALIGNMENT_FAILURES_ERRORS_COUNT */ "", 45781 /* ILAMAC_RX_BAD_PACKETS_COUNT */ "", 45782 /* ILAMAC_RX_BAD_TYPE_ERRORS_COUNT */ "", 45783 /* ILAMAC_RX_BURSTMAX_ERRORS_COUNT */ "", 45784 /* ILAMAC_RX_BYTES_COUNT */ "", 45785 /* ILAMAC_RX_CHANOUT0 */ "", 45786 /* ILAMAC_RX_CHANOUT1 */ "", 45787 /* ILAMAC_RX_CONFIG */ "", 45788 /* ILAMAC_RX_CRC_ERRORS_COUNT */ "", 45789 /* ILAMAC_RX_DESCRAM_ERRORS_COUNT */ "", 45790 /* ILAMAC_RX_FRAMING_ERRORS_COUNT */ "", 45791 /* ILAMAC_RX_INTF_INTR0_CLEAR */ "", 45792 /* ILAMAC_RX_INTF_INTR0_ENABLE */ "", 45793 /* ILAMAC_RX_INTF_INTR0_STS */ "", 45794 /* ILAMAC_RX_INTF_INTR1_CLEAR */ "", 45795 /* ILAMAC_RX_INTF_INTR1_ENABLE */ "", 45796 /* ILAMAC_RX_INTF_INTR1_STS */ "", 45797 /* ILAMAC_RX_INTF_STATE0 */ "", 45798 /* ILAMAC_RX_INTF_STATE1 */ "", 45799 /* ILAMAC_RX_LANE_CRC_ERRORS_COUNT */ "", 45800 /* ILAMAC_RX_LANE_INTR0_CLEAR */ "", 45801 /* ILAMAC_RX_LANE_INTR0_ENABLE */ "", 45802 /* ILAMAC_RX_LANE_INTR0_STS */ "", 45803 /* ILAMAC_RX_LANE_INTR1_CLEAR */ "", 45804 /* ILAMAC_RX_LANE_INTR1_ENABLE */ "", 45805 /* ILAMAC_RX_LANE_INTR1_STS */ "", 45806 /* ILAMAC_RX_LANE_INTR2_CLEAR */ "", 45807 /* ILAMAC_RX_LANE_INTR2_ENABLE */ "", 45808 /* ILAMAC_RX_LANE_INTR2_STS */ "", 45809 /* ILAMAC_RX_LANE_INTR3_CLEAR */ "", 45810 /* ILAMAC_RX_LANE_INTR3_ENABLE */ "", 45811 /* ILAMAC_RX_LANE_INTR3_STS */ "", 45812 /* ILAMAC_RX_LANE_STATE */ "", 45813 /* ILAMAC_RX_PACKETS_COUNT */ "", 45814 /* ILAMAC_RX_WORD_SYNC_ERRORS_COUNT */ "", 45815 /* ILAMAC_TX_BYTES_COUNT */ "", 45816 /* ILAMAC_TX_CONFIG0 */ "", 45817 /* ILAMAC_TX_CONFIG1 */ "", 45818 /* ILAMAC_TX_CONFIG2 */ "", 45819 /* ILAMAC_TX_CONFIG3 */ "", 45820 /* ILAMAC_TX_CONFIG4 */ "", 45821 /* ILAMAC_TX_CONFIG5 */ "", 45822 /* ILAMAC_TX_INTF_STATE */ "", 45823 /* ILAMAC_TX_INTR_CLEAR */ "", 45824 /* ILAMAC_TX_INTR_ENABLE */ "", 45825 /* ILAMAC_TX_INTR_STS */ "", 45826 /* ILAMAC_TX_PACKETS_COUNT */ "", 45827 /* ILB_DEBUG_FIFO_STATUS_REG */ "", 45828 /* ILB_DEBUG_LAST_READ_REG */ "", 45829 /* ILB_DEBUG_LAST_WRITE_REG */ "", 45830 /* ILB_DEBUG_LBRG_HI_LO_STATUS_REG */ "", 45831 /* ILB_DEBUG_LBRG_STATUS_REG */ "", 45832 /* ILB_DEBUG_MAX_FIFO_OC_REG */ "", 45833 /* ILB_DEBUG_OUTPUT_FIFO_FC_REG */ "", 45834 /* ILB_DEBUG_SHARED_STATUS_REG */ "", 45835 /* ILB_DEBUG_STATUS_REG */ "", 45836 /* ILB_DMFIFO_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER */ "", 45837 /* ILB_DMFIFO_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER_MASK */ "", 45838 /* ILB_DMFIFO_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER_TEST */ "", 45839 /* ILB_DMFIFO_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER */ "", 45840 /* ILB_DMFIFO_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER_MASK */ "", 45841 /* ILB_DMFIFO_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER_TEST */ "", 45842 /* ILB_ECC_1B_ERR_CNT */ "", 45843 /* ILB_ECC_2B_ERR_CNT */ "", 45844 /* ILB_ECC_ERR_1B_INITIATE */ "", 45845 /* ILB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 45846 /* ILB_ECC_ERR_2B_INITIATE */ "", 45847 /* ILB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 45848 /* ILB_ECC_INTERRUPT_REGISTER */ "", 45849 /* ILB_ECC_INTERRUPT_REGISTER_MASK */ "", 45850 /* ILB_ECC_INTERRUPT_REGISTER_TEST */ "", 45851 /* ILB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 45852 /* ILB_ERROR_INITIATION_DATA */ "", 45853 /* ILB_FIFO_CNT */ "", 45854 /* ILB_FIFO_EMPTY_REG */ "", 45855 /* ILB_FIFO_LONG_SEGMENT_ERROR_INTERRUPT_REGISTER */ "", 45856 /* ILB_FIFO_LONG_SEGMENT_ERROR_INTERRUPT_REGISTER_MASK */ "", 45857 /* ILB_FIFO_LONG_SEGMENT_ERROR_INTERRUPT_REGISTER_TEST */ "", 45858 /* ILB_FIFO_OVERFLOW_ERROR_INTERRUPT_REGISTER */ "", 45859 /* ILB_FIFO_OVERFLOW_ERROR_INTERRUPT_REGISTER_MASK */ "", 45860 /* ILB_FIFO_OVERFLOW_ERROR_INTERRUPT_REGISTER_TEST */ "", 45861 /* ILB_FLUSH_ERROR_INTERRUPT_REGISTER */ "", 45862 /* ILB_FLUSH_ERROR_INTERRUPT_REGISTER_MASK */ "", 45863 /* ILB_FLUSH_ERROR_INTERRUPT_REGISTER_TEST */ "", 45864 /* ILB_FPC_FREE_ERROR_REG */ "", 45865 /* ILB_FPC_STATUS */ "", 45866 /* ILB_FRAGMENT_DROP_CNT_REG */ "", 45867 /* ILB_GLOBAL_GENERAL_CFG_3 */ "", 45868 /* ILB_GLOBAL_MEM_OPTIONS */ "", 45869 /* ILB_GROUP_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER */ "", 45870 /* ILB_GROUP_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER_MASK */ "", 45871 /* ILB_GROUP_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER_TEST */ "", 45872 /* ILB_GROUP_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER */ "", 45873 /* ILB_GROUP_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER_MASK */ "", 45874 /* ILB_GROUP_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER_TEST */ "", 45875 /* ILB_GROUP_GUARANTEE_CHANGED_ERROR_INTERRUPT_REGISTER */ "", 45876 /* ILB_GROUP_GUARANTEE_CHANGED_ERROR_INTERRUPT_REGISTER_MASK */ "", 45877 /* ILB_GROUP_GUARANTEE_CHANGED_ERROR_INTERRUPT_REGISTER_TEST */ "", 45878 /* ILB_GROUP_OUT_OF_BUFFERS_ERROR_INTERRUPT_REGISTER */ "", 45879 /* ILB_GROUP_OUT_OF_BUFFERS_ERROR_INTERRUPT_REGISTER_MASK */ "", 45880 /* ILB_GROUP_OUT_OF_BUFFERS_ERROR_INTERRUPT_REGISTER_TEST */ "", 45881 /* ILB_GTIMER_CONFIGURATION */ "", 45882 /* ILB_ILB_INIT_REG */ "", 45883 /* ILB_INDIRECT_COMMAND */ "", 45884 /* ILB_INDIRECT_COMMAND_ADDRESS */ "", 45885 /* ILB_INDIRECT_COMMAND_DATA_INCREMENT */ "", 45886 /* ILB_INDIRECT_COMMAND_RD_DATA */ "", 45887 /* ILB_INDIRECT_COMMAND_WIDE_MEM */ "", 45888 /* ILB_INDIRECT_COMMAND_WR_DATA */ "", 45889 /* ILB_INDIRECT_FORCE_BUBBLE */ "", 45890 /* ILB_INTERRUPT_MASK_REGISTER */ "", 45891 /* ILB_INTERRUPT_REGISTER */ "", 45892 /* ILB_INTERRUPT_REGISTER_TEST */ "", 45893 /* ILB_LBRG_CONFIGURATION */ "", 45894 /* ILB_MAX_OUT_OF_ORDER_ERROR_INTERRUPT_REGISTER */ "", 45895 /* ILB_MAX_OUT_OF_ORDER_ERROR_INTERRUPT_REGISTER_MASK */ "", 45896 /* ILB_MAX_OUT_OF_ORDER_ERROR_INTERRUPT_REGISTER_TEST */ "", 45897 /* ILB_MISC_CONFIG_REG */ "", 45898 /* ILB_MISSING_FRAGMENT_ERROR_INTERRUPT_REGISTER */ "", 45899 /* ILB_MISSING_FRAGMENT_ERROR_INTERRUPT_REGISTER_MASK */ "", 45900 /* ILB_MISSING_FRAGMENT_ERROR_INTERRUPT_REGISTER_TEST */ "", 45901 /* ILB_MODEM_FIFO_CONFIG */ "", 45902 /* ILB_MODEM_FIFO_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER */ "", 45903 /* ILB_MODEM_FIFO_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER_MASK */ "", 45904 /* ILB_MODEM_FIFO_COUNTER_OVERFLOW_ERROR_INTERRUPT_REGISTER_TEST */ "", 45905 /* ILB_MODEM_FIFO_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER */ "", 45906 /* ILB_MODEM_FIFO_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER_MASK */ "", 45907 /* ILB_MODEM_FIFO_COUNTER_UNDERFLOW_ERROR_INTERRUPT_REGISTER_TEST */ "", 45908 /* ILB_MODEM_NOT_IN_GROUP_ERROR_INTERRUPT_REGISTER */ "", 45909 /* ILB_MODEM_NOT_IN_GROUP_ERROR_INTERRUPT_REGISTER_MASK */ "", 45910 /* ILB_MODEM_NOT_IN_GROUP_ERROR_INTERRUPT_REGISTER_TEST */ "", 45911 /* ILB_MODEM_SPECIAL_SID_MASK */ "", 45912 /* ILB_REG_0106 */ "", 45913 /* ILB_REG_0110 */ "", 45914 /* ILB_REG_0113 */ "", 45915 /* ILB_REG_0114 */ "", 45916 /* ILB_REG_0115 */ "", 45917 /* ILB_REG_0124 */ "", 45918 /* ILB_REG_0125 */ "", 45919 /* ILB_REG_0128 */ "", 45920 /* ILB_REG_0129 */ "", 45921 /* ILB_REG_0130 */ "", 45922 /* ILB_REG_0139 */ "", 45923 /* ILB_REG_0148 */ "", 45924 /* ILB_REG_0191 */ "", 45925 /* ILB_REG_0192 */ "", 45926 /* ILB_REG_010F */ "", 45927 /* ILB_REG_011B */ "", 45928 /* ILB_REG_012A */ "", 45929 /* ILB_REG_013A */ "", 45930 /* ILB_REG_013D */ "", 45931 /* ILB_REG_013E */ "", 45932 /* ILB_REG_013F */ "", 45933 /* ILB_REG_018E */ "", 45934 /* ILB_REG_018F */ "", 45935 /* ILB_REG_019C */ "", 45936 /* ILB_REG_019D */ "", 45937 /* ILB_REG_01A5 */ "", 45938 /* ILB_REG_01B3 */ "", 45939 /* ILB_RESERVED_MIRROR_ADDR */ "", 45940 /* ILB_RESERVED_MTCD */ "", 45941 /* ILB_RESERVED_MTCP */ "", 45942 /* ILB_RESERVED_SPARE_0 */ "", 45943 /* ILB_RESERVED_SPARE_1 */ "", 45944 /* ILB_RESERVED_SPARE_2 */ "", 45945 /* ILB_RESERVED_SPARE_3 */ "", 45946 /* ILB_SBUS_BROADCAST_ID */ "", 45947 /* ILB_SBUS_LAST_IN_CHAIN */ "", 45948 /* ILB_SENT_PACKETS_CNT_REG */ "", 45949 /* ILB_SHARED_OUT_OF_BUFFERS_ERROR_INTERRUPT_REGISTER */ "", 45950 /* ILB_SHARED_OUT_OF_BUFFERS_ERROR_INTERRUPT_REGISTER_MASK */ "", 45951 /* ILB_SHARED_OUT_OF_BUFFERS_ERROR_INTERRUPT_REGISTER_TEST */ "", 45952 /* ILB_SPECIAL_FUNC_TPID_REG */ "", 45953 /* ILB_SPECIAL_SID */ "", 45954 /* ILB_WFQ_ARBITER_WEIGHT */ "", 45955 /* ILE_CLOCK_PD_POWER_DOWN */ "", 45956 /* ILE_ECC_1B_ERR_CNT */ "", 45957 /* ILE_ECC_2B_ERR_CNT */ "", 45958 /* ILE_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 45959 /* ILE_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 45960 /* ILE_ECC_INTERRUPT_REGISTER */ "", 45961 /* ILE_ECC_INTERRUPT_REGISTER_MASK */ "", 45962 /* ILE_ECC_INTERRUPT_REGISTER_TEST */ "", 45963 /* ILE_EGW_TO_ILE_LAST_RECEIVED_CONTROLS */ "", 45964 /* ILE_EGW_TO_ILE_LAST_RECEIVED_DATA */ "", 45965 /* ILE_EGW_TO_ILE_TX_DEBUG_EOP_AFTER_EOP */ "", 45966 /* ILE_EGW_TO_ILE_TX_DEBUG_PACKET_LARGER_THAN_256_BYTES */ "", 45967 /* ILE_EGW_TO_ILE_TX_DEBUG_SOP_AFTER_SOP */ "", 45968 /* ILE_ELK_CFG */ "", 45969 /* ILE_ELK_STATUS */ "", 45970 /* ILE_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 45971 /* ILE_ENABLE_INTERLAKEN */ "", 45972 /* ILE_ERROR_INITIATION_DATA */ "", 45973 /* ILE_FC_ILKN */ "", 45974 /* ILE_FC_LLFC_STOP_TX_FORCE */ "", 45975 /* ILE_FC_MASK_ILKN_CHFC_WHEN_LINK_FAIL */ "", 45976 /* ILE_FEC_AM_PERIOD_CONFIG */ "", 45977 /* ILE_FEC_BYPASS_CORRECTION_ENABLE */ "", 45978 /* ILE_FEC_DECODER_ALIGN_STATUS */ "", 45979 /* ILE_FEC_DECODER_AMPS_LOCK_STATUS */ "", 45980 /* ILE_FEC_DECODER_DESKEW_FAIL_STATUS */ "", 45981 /* ILE_FEC_DECODER_LANE_MAPPING */ "", 45982 /* ILE_FORCE_DATA_ON_TWO_SEG_ONLY */ "", 45983 /* ILE_GTIMER_CONFIGURATION */ "", 45984 /* ILE_GTIMER_CYCLE */ "", 45985 /* ILE_HRF_SEGMENTATION_PORT_0_BUFF_HAS_DATA */ "", 45986 /* ILE_ILE_TO_EGW_LAST_SENT_CONTROLS */ "", 45987 /* ILE_ILE_TO_EGW_LAST_SENT_DATA */ "", 45988 /* ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_CONTROLS */ "", 45989 /* ILE_ILE_TO_ILKN_CORE_WORD_LAST_SENT_DATA */ "", 45990 /* ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_CONTROLS */ "", 45991 /* ILE_ILKN_CORE_TO_ILE_WORD_LAST_RECEIVED_DATA */ "", 45992 /* ILE_ILKN_DEBUG_SELECT_LANE_FOR_COUNTERS */ "", 45993 /* ILE_ILKN_INVERT_POLARITY_SIGNALS */ "", 45994 /* ILE_ILKN_RESET */ "", 45995 /* ILE_ILKN_REVERT_SERDES_DATA_ORDER */ "", 45996 /* ILE_ILKN_RX_0_DEBUG_BUS */ "", 45997 /* ILE_ILKN_RX_1_DEBUG_BUS */ "", 45998 /* ILE_ILKN_RX_DEBUG_ALIGNMENT_ACHIEVED_COUNTER */ "", 45999 /* ILE_ILKN_RX_DEBUG_ALIGNMENT_LOST_COUNTER */ "", 46000 /* ILE_ILKN_RX_DEBUG_VALID_COUNTER */ "", 46001 /* ILE_ILKN_RX_DISABLE_RECEIVED_EOP_ERR */ "", 46002 /* ILE_ILKN_RX_DISABLE_RECEIVED_PORT_ERR */ "", 46003 /* ILE_ILKN_RX_DISABLE_RECEIVED_RX_ERR */ "", 46004 /* ILE_ILKN_RX_DISABLE_WORD */ "", 46005 /* ILE_ILKN_RX_RETRANSMIT_DEBUG_INFORMATION */ "", 46006 /* ILE_ILKN_RX_RETRANS_FSM_CLKS_IN_STATE_CNT */ "", 46007 /* ILE_ILKN_RX_RETRANS_FSM_ENTER_STATE_CNT */ "", 46008 /* ILE_ILKN_RX_RETRANS_FSM_STATE_TO_MONITOR */ "", 46009 /* ILE_ILKN_RX_SERDES_VALID */ "", 46010 /* ILE_ILKN_SERDES_DISABLE_MASKS */ "", 46011 /* ILE_ILKN_TX_0_DEBUG_BUS */ "", 46012 /* ILE_ILKN_TX_1_DEBUG_BUS */ "", 46013 /* ILE_ILKN_TX_CONF */ "", 46014 /* ILE_ILKN_TX_DEBUG_CREDIT_COUNTER */ "", 46015 /* ILE_ILKN_TX_DEBUG_VALID_COUNTER */ "", 46016 /* ILE_ILKN_TX_DISABLE_WORD */ "", 46017 /* ILE_ILKN_TX_FLUSH_SELECTOR */ "", 46018 /* ILE_ILKN_TX_MANUAL_SERDES_CREDIT_DEBUG */ "", 46019 /* ILE_ILKN_TX_PORT_0_WORD_ENABLE_FLUSH_ON_BURST_BOUNDARIES */ "", 46020 /* ILE_ILKN_TX_PORT_DATA_PCK_DEADLOCK_HAPPENED */ "", 46021 /* ILE_ILKN_TX_PORT_DISABLE_DATA_PCK_FLUSH_WHEN_DEADLOCK */ "", 46022 /* ILE_ILKN_TX_PORT_FORCE_DATA_PCK_FLUSH */ "", 46023 /* ILE_INDIRECT_COMMAND */ "", 46024 /* ILE_INDIRECT_COMMAND_ADDRESS */ "", 46025 /* ILE_INDIRECT_COMMAND_RD_DATA */ "", 46026 /* ILE_INDIRECT_COMMAND_WR_DATA */ "", 46027 /* ILE_INDIRECT_FORCE_BUBBLE */ "", 46028 /* ILE_INTERRUPT_MASK_REGISTER */ "", 46029 /* ILE_INTERRUPT_REGISTER */ "", 46030 /* ILE_INTERRUPT_REGISTER_TEST */ "", 46031 /* ILE_PCMI_0 */ "", 46032 /* ILE_PCMI_1 */ "", 46033 /* ILE_PCMI_2 */ "", 46034 /* ILE_PCMI_3 */ "", 46035 /* ILE_PCMI_4 */ "", 46036 /* ILE_PCMI_0_S */ "", 46037 /* ILE_PCMI_0_T */ "", 46038 /* ILE_PCMI_1_S */ "", 46039 /* ILE_PCMI_1_T */ "", 46040 /* ILE_PCMI_2_S */ "", 46041 /* ILE_PCMI_2_T */ "", 46042 /* ILE_PCMI_3_S */ "", 46043 /* ILE_PCMI_3_T */ "", 46044 /* ILE_PCMI_4_S */ "", 46045 /* ILE_PCMI_4_T */ "", 46046 /* ILE_REG_0041 */ "", 46047 /* ILE_REG_0098 */ "", 46048 /* ILE_REG_00A0 */ "", 46049 /* ILE_REG_00A4 */ "", 46050 /* ILE_REG_00A6 */ "", 46051 /* ILE_REG_00AA */ "", 46052 /* ILE_REG_00C2 */ "", 46053 /* ILE_RESERVED_MIRROR_ADDR */ "", 46054 /* ILE_RESERVED_MTCD */ "", 46055 /* ILE_RESERVED_MTCP */ "", 46056 /* ILE_RESERVED_SPARE_0 */ "", 46057 /* ILE_RESERVED_SPARE_1 */ "", 46058 /* ILE_RESERVED_SPARE_2 */ "", 46059 /* ILE_RESERVED_SPARE_3 */ "", 46060 /* ILE_RESET_WRAP_WITHOUT_ILKN_PORTS */ "", 46061 /* ILE_RX_BYTES_COUNTER */ "", 46062 /* ILE_RX_ELK_BURSTS_CNT */ "", 46063 /* ILE_RX_ELK_BURST_DROP_CNT */ "", 46064 /* ILE_RX_ELK_ERR_BURSTS_CNT */ "", 46065 /* ILE_RX_ELK_OCTETS_CNT */ "", 46066 /* ILE_RX_ERR_PKT_COUNTER */ "", 46067 /* ILE_RX_FEC_DECODER_CORRECTED_BIT_CNT */ "", 46068 /* ILE_RX_FEC_DECODER_CORRECTED_CODE_WORD_CNT */ "", 46069 /* ILE_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_0 */ "", 46070 /* ILE_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_1 */ "", 46071 /* ILE_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_2 */ "", 46072 /* ILE_RX_FEC_DECODER_LANE_SYMBOL_ERR_CNT_3 */ "", 46073 /* ILE_RX_FEC_DECODER_UNCORRECTED_CODE_WORD_CNT */ "", 46074 /* ILE_RX_FRAMELOCK */ "", 46075 /* ILE_RX_ILKN_STATUS */ "", 46076 /* ILE_RX_PKT_COUNTER */ "", 46077 /* ILE_SBUS_BROADCAST_ID */ "", 46078 /* ILE_SBUS_LAST_IN_CHAIN */ "", 46079 /* ILE_SET_FEC_TX_SERDES_EN_FROM_LANE */ "", 46080 /* ILE_SPECIAL_CLOCK_CONTROLS */ "", 46081 /* ILE_TRANSMIT_RETRANSMIT_DEBUG */ "", 46082 /* ILE_TX_BYTES_COUNTER */ "", 46083 /* ILE_TX_ELK_BURSTS_CNT */ "", 46084 /* ILE_TX_ELK_ERR_BURSTS_CNT */ "", 46085 /* ILE_TX_ELK_OCTETS_CNT */ "", 46086 /* ILE_TX_ERR_PKT_COUNTER */ "", 46087 /* ILE_TX_ILKN_0_FLUSHED_PACKETS_CNT */ "", 46088 /* ILE_TX_ILKN_1_FLUSHED_PACKETS_CNT */ "", 46089 /* ILE_TX_ILKN_CONTROL */ "", 46090 /* ILE_TX_ILKN_STATUS */ "", 46091 /* ILE_TX_PKT_COUNTER */ "", 46092 /* ILKN_PMH_ECC_1B_ERR_CNT */ "", 46093 /* ILKN_PMH_ECC_2B_ERR_CNT */ "", 46094 /* ILKN_PMH_ECC_ERR_1B_INITIATE */ "", 46095 /* ILKN_PMH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 46096 /* ILKN_PMH_ECC_ERR_2B_INITIATE */ "", 46097 /* ILKN_PMH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 46098 /* ILKN_PMH_ECC_INTERRUPT_REGISTER */ "", 46099 /* ILKN_PMH_ECC_INTERRUPT_REGISTER_MASK */ "", 46100 /* ILKN_PMH_ECC_INTERRUPT_REGISTER_TEST */ "", 46101 /* ILKN_PMH_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 46102 /* ILKN_PMH_ENABLE_INTERLAKEN */ "", 46103 /* ILKN_PMH_ERROR_INITIATION_DATA */ "", 46104 /* ILKN_PMH_GLOBAL_MEM_OPTIONS */ "", 46105 /* ILKN_PMH_GTIMER_CONFIGURATION */ "", 46106 /* ILKN_PMH_GTIMER_TRIGGER */ "", 46107 /* ILKN_PMH_ILKN_DEBUG_SELECT_LANE_FOR_COUNTERS */ "", 46108 /* ILKN_PMH_ILKN_FC_OOB_CONF */ "", 46109 /* ILKN_PMH_ILKN_GEN_CREDITS_BURST_FROM_SERDES */ "", 46110 /* ILKN_PMH_ILKN_INVERT_POLARITY_SIGNALS */ "", 46111 /* ILKN_PMH_ILKN_OVER_FABRIC */ "", 46112 /* ILKN_PMH_ILKN_RESET */ "", 46113 /* ILKN_PMH_ILKN_REVERT_SERDES_DATA_ORDER */ "", 46114 /* ILKN_PMH_ILKN_RX_0_DEBUG_BUS */ "", 46115 /* ILKN_PMH_ILKN_RX_1_DEBUG_BUS */ "", 46116 /* ILKN_PMH_ILKN_RX_DEBUG_VALID_COUNTER */ "", 46117 /* ILKN_PMH_ILKN_RX_RETRANSMIT_DEBUG_INFORMATION */ "", 46118 /* ILKN_PMH_ILKN_RX_RETRANS_FSM_CLKS_IN_STATE_CNT */ "", 46119 /* ILKN_PMH_ILKN_RX_RETRANS_FSM_ENTER_STATE_CNT */ "", 46120 /* ILKN_PMH_ILKN_RX_RETRANS_FSM_STATE_TO_MONITOR */ "", 46121 /* ILKN_PMH_ILKN_TX_0_DEBUG_BUS */ "", 46122 /* ILKN_PMH_ILKN_TX_1_DEBUG_BUS */ "", 46123 /* ILKN_PMH_ILKN_TX_CONF */ "", 46124 /* ILKN_PMH_ILKN_TX_DEBUG_CREDIT_COUNTER */ "", 46125 /* ILKN_PMH_ILKN_TX_DEBUG_VALID_COUNTER */ "", 46126 /* ILKN_PMH_ILKN_TX_MANUAL_SERDES_CREDIT_DEBUG */ "", 46127 /* ILKN_PMH_INDIRECT_COMMAND */ "", 46128 /* ILKN_PMH_INDIRECT_COMMAND_ADDRESS */ "", 46129 /* ILKN_PMH_INDIRECT_COMMAND_DATA_INCREMENT */ "", 46130 /* ILKN_PMH_INDIRECT_COMMAND_RD_DATA */ "", 46131 /* ILKN_PMH_INDIRECT_COMMAND_WIDE_MEM */ "", 46132 /* ILKN_PMH_INDIRECT_COMMAND_WR_DATA */ "", 46133 /* ILKN_PMH_INDIRECT_FORCE_BUBBLE */ "", 46134 /* ILKN_PMH_INDIRECT_WR_MASK */ "", 46135 /* ILKN_PMH_INTERRUPT_MASK_REGISTER */ "", 46136 /* ILKN_PMH_INTERRUPT_REGISTER */ "", 46137 /* ILKN_PMH_INTERRUPT_REGISTER_TEST */ "", 46138 /* ILKN_PMH_PARITY_ERR_CNT */ "", 46139 /* ILKN_PMH_PAR_ERR_INITIATE */ "", 46140 /* ILKN_PMH_PAR_ERR_MEM_MASK */ "", 46141 /* ILKN_PMH_RESERVED_MIRROR_ADDR */ "", 46142 /* ILKN_PMH_RESERVED_MTCD */ "", 46143 /* ILKN_PMH_RESERVED_MTCP */ "", 46144 /* ILKN_PMH_RESERVED_PCMI_0 */ "", 46145 /* ILKN_PMH_RESERVED_PCMI_1 */ "", 46146 /* ILKN_PMH_RESERVED_PCMI_2 */ "", 46147 /* ILKN_PMH_RESERVED_PCMI_3 */ "", 46148 /* ILKN_PMH_RESERVED_PCMI_4 */ "", 46149 /* ILKN_PMH_RESERVED_PCMI_0_S */ "", 46150 /* ILKN_PMH_RESERVED_PCMI_0_T */ "", 46151 /* ILKN_PMH_RESERVED_PCMI_1_S */ "", 46152 /* ILKN_PMH_RESERVED_PCMI_1_T */ "", 46153 /* ILKN_PMH_RESERVED_PCMI_2_S */ "", 46154 /* ILKN_PMH_RESERVED_PCMI_2_T */ "", 46155 /* ILKN_PMH_RESERVED_PCMI_3_S */ "", 46156 /* ILKN_PMH_RESERVED_PCMI_3_T */ "", 46157 /* ILKN_PMH_RESERVED_PCMI_4_S */ "", 46158 /* ILKN_PMH_RESERVED_PCMI_4_T */ "", 46159 /* ILKN_PMH_RESERVED_SPARE_0 */ "", 46160 /* ILKN_PMH_RESERVED_SPARE_1 */ "", 46161 /* ILKN_PMH_RESERVED_SPARE_2 */ "", 46162 /* ILKN_PMH_RESERVED_SPARE_3 */ "", 46163 /* ILKN_PMH_RESET_WRAP_WITHOUT_ILKN_PORTS */ "", 46164 /* ILKN_PMH_RX_BYTES_COUNTER */ "", 46165 /* ILKN_PMH_RX_ERR_PKT_COUNTER */ "", 46166 /* ILKN_PMH_RX_FRAMELOCK */ "", 46167 /* ILKN_PMH_RX_ILKN_STATUS */ "", 46168 /* ILKN_PMH_RX_PKT_COUNTER */ "", 46169 /* ILKN_PMH_SBUS_BROADCAST_ID */ "", 46170 /* ILKN_PMH_SBUS_LAST_IN_CHAIN */ "", 46171 /* ILKN_PMH_TRANSMIT_RETRANSMIT_DEBUG */ "", 46172 /* ILKN_PMH_TX_BYTES_COUNTER */ "", 46173 /* ILKN_PMH_TX_ERR_PKT_COUNTER */ "", 46174 /* ILKN_PMH_TX_ILKN_0_FLUSHED_PACKETS_CNT */ "", 46175 /* ILKN_PMH_TX_ILKN_1_FLUSHED_PACKETS_CNT */ "", 46176 /* ILKN_PMH_TX_ILKN_CONTROL */ "", 46177 /* ILKN_PMH_TX_ILKN_STATUS */ "", 46178 /* ILKN_PMH_TX_PKT_COUNTER */ "", 46179 /* ILKN_PML_ECC_1B_ERR_CNT */ "", 46180 /* ILKN_PML_ECC_2B_ERR_CNT */ "", 46181 /* ILKN_PML_ECC_ERR_1B_INITIATE */ "", 46182 /* ILKN_PML_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 46183 /* ILKN_PML_ECC_ERR_2B_INITIATE */ "", 46184 /* ILKN_PML_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 46185 /* ILKN_PML_ECC_INTERRUPT_REGISTER */ "", 46186 /* ILKN_PML_ECC_INTERRUPT_REGISTER_MASK */ "", 46187 /* ILKN_PML_ECC_INTERRUPT_REGISTER_TEST */ "", 46188 /* ILKN_PML_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 46189 /* ILKN_PML_ENABLE_INTERLAKEN */ "", 46190 /* ILKN_PML_ERROR_INITIATION_DATA */ "", 46191 /* ILKN_PML_GLOBAL_MEM_OPTIONS */ "", 46192 /* ILKN_PML_GTIMER_CONFIGURATION */ "", 46193 /* ILKN_PML_GTIMER_TRIGGER */ "", 46194 /* ILKN_PML_ILKN_DEBUG_SELECT_LANE_FOR_COUNTERS */ "", 46195 /* ILKN_PML_ILKN_FC_OOB_CONF */ "", 46196 /* ILKN_PML_ILKN_GEN_CREDITS_BURST_FROM_SERDES */ "", 46197 /* ILKN_PML_ILKN_INVERT_POLARITY_SIGNALS */ "", 46198 /* ILKN_PML_ILKN_OVER_FABRIC */ "", 46199 /* ILKN_PML_ILKN_RESET */ "", 46200 /* ILKN_PML_ILKN_REVERT_SERDES_DATA_ORDER */ "", 46201 /* ILKN_PML_ILKN_RX_0_DEBUG_BUS */ "", 46202 /* ILKN_PML_ILKN_RX_1_DEBUG_BUS */ "", 46203 /* ILKN_PML_ILKN_RX_DEBUG_VALID_COUNTER */ "", 46204 /* ILKN_PML_ILKN_RX_RETRANSMIT_DEBUG_INFORMATION */ "", 46205 /* ILKN_PML_ILKN_RX_RETRANS_FSM_CLKS_IN_STATE_CNT */ "", 46206 /* ILKN_PML_ILKN_RX_RETRANS_FSM_ENTER_STATE_CNT */ "", 46207 /* ILKN_PML_ILKN_RX_RETRANS_FSM_STATE_TO_MONITOR */ "", 46208 /* ILKN_PML_ILKN_TX_0_DEBUG_BUS */ "", 46209 /* ILKN_PML_ILKN_TX_1_DEBUG_BUS */ "", 46210 /* ILKN_PML_ILKN_TX_CONF */ "", 46211 /* ILKN_PML_ILKN_TX_DEBUG_CREDIT_COUNTER */ "", 46212 /* ILKN_PML_ILKN_TX_DEBUG_VALID_COUNTER */ "", 46213 /* ILKN_PML_ILKN_TX_MANUAL_SERDES_CREDIT_DEBUG */ "", 46214 /* ILKN_PML_INDIRECT_COMMAND */ "", 46215 /* ILKN_PML_INDIRECT_COMMAND_ADDRESS */ "", 46216 /* ILKN_PML_INDIRECT_COMMAND_DATA_INCREMENT */ "", 46217 /* ILKN_PML_INDIRECT_COMMAND_RD_DATA */ "", 46218 /* ILKN_PML_INDIRECT_COMMAND_WIDE_MEM */ "", 46219 /* ILKN_PML_INDIRECT_COMMAND_WR_DATA */ "", 46220 /* ILKN_PML_INDIRECT_FORCE_BUBBLE */ "", 46221 /* ILKN_PML_INDIRECT_WR_MASK */ "", 46222 /* ILKN_PML_INTERRUPT_MASK_REGISTER */ "", 46223 /* ILKN_PML_INTERRUPT_REGISTER */ "", 46224 /* ILKN_PML_INTERRUPT_REGISTER_TEST */ "", 46225 /* ILKN_PML_PARITY_ERR_CNT */ "", 46226 /* ILKN_PML_PAR_ERR_INITIATE */ "", 46227 /* ILKN_PML_PAR_ERR_MEM_MASK */ "", 46228 /* ILKN_PML_RESERVED_MIRROR_ADDR */ "", 46229 /* ILKN_PML_RESERVED_MTCD */ "", 46230 /* ILKN_PML_RESERVED_MTCP */ "", 46231 /* ILKN_PML_RESERVED_PCMI_0 */ "", 46232 /* ILKN_PML_RESERVED_PCMI_1 */ "", 46233 /* ILKN_PML_RESERVED_PCMI_2 */ "", 46234 /* ILKN_PML_RESERVED_PCMI_3 */ "", 46235 /* ILKN_PML_RESERVED_PCMI_4 */ "", 46236 /* ILKN_PML_RESERVED_PCMI_0_S */ "", 46237 /* ILKN_PML_RESERVED_PCMI_0_T */ "", 46238 /* ILKN_PML_RESERVED_PCMI_1_S */ "", 46239 /* ILKN_PML_RESERVED_PCMI_1_T */ "", 46240 /* ILKN_PML_RESERVED_PCMI_2_S */ "", 46241 /* ILKN_PML_RESERVED_PCMI_2_T */ "", 46242 /* ILKN_PML_RESERVED_PCMI_3_S */ "", 46243 /* ILKN_PML_RESERVED_PCMI_3_T */ "", 46244 /* ILKN_PML_RESERVED_PCMI_4_S */ "", 46245 /* ILKN_PML_RESERVED_PCMI_4_T */ "", 46246 /* ILKN_PML_RESERVED_SPARE_0 */ "", 46247 /* ILKN_PML_RESERVED_SPARE_1 */ "", 46248 /* ILKN_PML_RESERVED_SPARE_2 */ "", 46249 /* ILKN_PML_RESERVED_SPARE_3 */ "", 46250 /* ILKN_PML_RESET_WRAP_WITHOUT_ILKN_PORTS */ "", 46251 /* ILKN_PML_RX_BYTES_COUNTER */ "", 46252 /* ILKN_PML_RX_ERR_PKT_COUNTER */ "", 46253 /* ILKN_PML_RX_FRAMELOCK */ "", 46254 /* ILKN_PML_RX_ILKN_STATUS */ "", 46255 /* ILKN_PML_RX_PKT_COUNTER */ "", 46256 /* ILKN_PML_SBUS_BROADCAST_ID */ "", 46257 /* ILKN_PML_SBUS_LAST_IN_CHAIN */ "", 46258 /* ILKN_PML_TRANSMIT_RETRANSMIT_DEBUG */ "", 46259 /* ILKN_PML_TX_BYTES_COUNTER */ "", 46260 /* ILKN_PML_TX_ERR_PKT_COUNTER */ "", 46261 /* ILKN_PML_TX_ILKN_0_FLUSHED_PACKETS_CNT */ "", 46262 /* ILKN_PML_TX_ILKN_1_FLUSHED_PACKETS_CNT */ "", 46263 /* ILKN_PML_TX_ILKN_CONTROL */ "", 46264 /* ILKN_PML_TX_ILKN_STATUS */ "", 46265 /* ILKN_PML_TX_PKT_COUNTER */ "", 46266 /* ILKN_SLE_RX_AFIFO_WM */ "", 46267 /* ILKN_SLE_RX_ALIGN */ "", 46268 /* ILKN_SLE_RX_BADCTL_ERR */ "", 46269 /* ILKN_SLE_RX_BADCTL_ERR_2 */ "", 46270 /* ILKN_SLE_RX_BURST */ "", 46271 /* ILKN_SLE_RX_CAL_ACC */ "", 46272 /* ILKN_SLE_RX_CAL_INBAND */ "", 46273 /* ILKN_SLE_RX_CAL_INBAND_DYN */ "", 46274 /* ILKN_SLE_RX_CAL_OUTBAND */ "", 46275 /* ILKN_SLE_RX_CAL_OUTBAND_DYN */ "", 46276 /* ILKN_SLE_RX_CAL_RD */ "", 46277 /* ILKN_SLE_RX_CAL_WT */ "", 46278 /* ILKN_SLE_RX_CDR_CNT_FILL */ "", 46279 /* ILKN_SLE_RX_CDR_CNT_FILL_2 */ "", 46280 /* ILKN_SLE_RX_CDR_ERR */ "", 46281 /* ILKN_SLE_RX_CDR_ERR_2 */ "", 46282 /* ILKN_SLE_RX_CFG */ "", 46283 /* ILKN_SLE_RX_CRC_32_CNT_FILL */ "", 46284 /* ILKN_SLE_RX_CRC_32_CNT_FILL_2 */ "", 46285 /* ILKN_SLE_RX_CRC_32_ERR */ "", 46286 /* ILKN_SLE_RX_CRC_32_ERR_2 */ "", 46287 /* ILKN_SLE_RX_CTL */ "", 46288 /* ILKN_SLE_RX_DAT_AFIFO_CORR_ERR */ "", 46289 /* ILKN_SLE_RX_DAT_AFIFO_CORR_ERR_2 */ "", 46290 /* ILKN_SLE_RX_DAT_AFIFO_OFLW_ERR */ "", 46291 /* ILKN_SLE_RX_DAT_AFIFO_OFLW_ERR_2 */ "", 46292 /* ILKN_SLE_RX_DAT_AFIFO_UNCORR_ERR */ "", 46293 /* ILKN_SLE_RX_DAT_AFIFO_UNCORR_ERR_2 */ "", 46294 /* ILKN_SLE_RX_DEBUG_0 */ "", 46295 /* ILKN_SLE_RX_DEBUG_1 */ "", 46296 /* ILKN_SLE_RX_DEBUG_2 */ "", 46297 /* ILKN_SLE_RX_DEBUG_3 */ "", 46298 /* ILKN_SLE_RX_DEBUG_HOLD_0 */ "", 46299 /* ILKN_SLE_RX_DEBUG_HOLD_1 */ "", 46300 /* ILKN_SLE_RX_DEBUG_HOLD_2 */ "", 46301 /* ILKN_SLE_RX_DEBUG_HOLD_3 */ "", 46302 /* ILKN_SLE_RX_DEBUG_OBS_0 */ "", 46303 /* ILKN_SLE_RX_DEBUG_OBS_1 */ "", 46304 /* ILKN_SLE_RX_DEBUG_OBS_2 */ "", 46305 /* ILKN_SLE_RX_DEBUG_OBS_3 */ "", 46306 /* ILKN_SLE_RX_DSKW_FIFO_CORR_ERR */ "", 46307 /* ILKN_SLE_RX_DSKW_FIFO_CORR_ERR_2 */ "", 46308 /* ILKN_SLE_RX_DSKW_FIFO_UNCORR_ERR */ "", 46309 /* ILKN_SLE_RX_DSKW_FIFO_UNCORR_ERR_2 */ "", 46310 /* ILKN_SLE_RX_ERRINS_0 */ "", 46311 /* ILKN_SLE_RX_ERRINS_1 */ "", 46312 /* ILKN_SLE_RX_ERRINS_2 */ "", 46313 /* ILKN_SLE_RX_ERRINS_3 */ "", 46314 /* ILKN_SLE_RX_EXT_INT */ "", 46315 /* ILKN_SLE_RX_EXT_INT_2_ND */ "", 46316 /* ILKN_SLE_RX_EXT_INT_2_ND_MASK */ "", 46317 /* ILKN_SLE_RX_EXT_INT_FORCE */ "", 46318 /* ILKN_SLE_RX_EXT_INT_MASK */ "", 46319 /* ILKN_SLE_RX_FCOB_RETRANSMIT_SLOT */ "", 46320 /* ILKN_SLE_RX_FCOB_RETRANSMIT_SLOT_DY */ "", 46321 /* ILKN_SLE_RX_INFO */ "", 46322 /* ILKN_SLE_RX_INFO_2 */ "", 46323 /* ILKN_SLE_RX_INFO_3 */ "", 46324 /* ILKN_SLE_RX_INT */ "", 46325 /* ILKN_SLE_RX_INT_2_ND */ "", 46326 /* ILKN_SLE_RX_INT_2_ND_MASK */ "", 46327 /* ILKN_SLE_RX_INT_FORCE */ "", 46328 /* ILKN_SLE_RX_INT_MASK */ "", 46329 /* ILKN_SLE_RX_LANE */ "", 46330 /* ILKN_SLE_RX_LANE_2 */ "", 46331 /* ILKN_SLE_RX_METAFRAME */ "", 46332 /* ILKN_SLE_RX_MF_ERR */ "", 46333 /* ILKN_SLE_RX_MF_ERR_2 */ "", 46334 /* ILKN_SLE_RX_PIPE_ENABLE */ "", 46335 /* ILKN_SLE_RX_REMAP_LANE_14_10 */ "", 46336 /* ILKN_SLE_RX_REMAP_LANE_19_15 */ "", 46337 /* ILKN_SLE_RX_REMAP_LANE_24_20 */ "", 46338 /* ILKN_SLE_RX_REMAP_LANE_29_25 */ "", 46339 /* ILKN_SLE_RX_REMAP_LANE_34_30 */ "", 46340 /* ILKN_SLE_RX_REMAP_LANE_39_35 */ "", 46341 /* ILKN_SLE_RX_REMAP_LANE_44_40 */ "", 46342 /* ILKN_SLE_RX_REMAP_LANE_47_45 */ "", 46343 /* ILKN_SLE_RX_REMAP_LANE_4_0 */ "", 46344 /* ILKN_SLE_RX_REMAP_LANE_9_5 */ "", 46345 /* ILKN_SLE_RX_RETRANSMIT_CONFIG */ "", 46346 /* ILKN_SLE_RX_RETRANSMIT_TIME_CONFIG */ "", 46347 /* ILKN_SLE_RX_RETRANSMIT_TIME_CONFIG_2 */ "", 46348 /* ILKN_SLE_RX_SCRAM_ERR */ "", 46349 /* ILKN_SLE_RX_SCRAM_ERR_2 */ "", 46350 /* ILKN_SLE_RX_SEGMENT_ENABLE */ "", 46351 /* ILKN_SLE_RX_SERDES_TEST_CNTL */ "", 46352 /* ILKN_SLE_RX_SERDES_TEST_PATTERNA */ "", 46353 /* ILKN_SLE_RX_SERDES_TEST_PATTERNB */ "", 46354 /* ILKN_SLE_RX_SERDES_TEST_PATTERNC */ "", 46355 /* ILKN_SLE_RX_STATS_ACC */ "", 46356 /* ILKN_SLE_RX_STATS_FILL */ "", 46357 /* ILKN_SLE_RX_STATS_PARITY */ "", 46358 /* ILKN_SLE_RX_STATS_RD_BYTE_HIGH */ "", 46359 /* ILKN_SLE_RX_STATS_RD_BYTE_LOW */ "", 46360 /* ILKN_SLE_RX_STATS_RD_ERR_HIGH */ "", 46361 /* ILKN_SLE_RX_STATS_RD_ERR_LOW */ "", 46362 /* ILKN_SLE_RX_STATS_RD_FLAG */ "", 46363 /* ILKN_SLE_RX_STATS_RD_PARITY */ "", 46364 /* ILKN_SLE_RX_STATS_RD_PKT_HIGH */ "", 46365 /* ILKN_SLE_RX_STATS_RD_PKT_LOW */ "", 46366 /* ILKN_SLE_RX_STATS_WT_BYTE_HIGH */ "", 46367 /* ILKN_SLE_RX_STATS_WT_BYTE_LOW */ "", 46368 /* ILKN_SLE_RX_STATS_WT_ERR_HIGH */ "", 46369 /* ILKN_SLE_RX_STATS_WT_ERR_LOW */ "", 46370 /* ILKN_SLE_RX_STATS_WT_PARITY */ "", 46371 /* ILKN_SLE_RX_STATS_WT_PKT_HIGH */ "", 46372 /* ILKN_SLE_RX_STATS_WT_PKT_LOW */ "", 46373 /* ILKN_SLE_RX_STATUS_MSG */ "", 46374 /* ILKN_SLE_RX_STATUS_MSG_2 */ "", 46375 /* ILKN_SLE_RX_WRD_SYNC */ "", 46376 /* ILKN_SLE_RX_WRD_SYNC_2 */ "", 46377 /* ILKN_SLE_RX_WRD_SYNC_CHG */ "", 46378 /* ILKN_SLE_RX_WRD_SYNC_CHG_2 */ "", 46379 /* ILKN_SLE_RX_WRD_SYNC_CNT_FILL */ "", 46380 /* ILKN_SLE_RX_WRD_SYNC_CNT_FILL_2 */ "", 46381 /* ILKN_SLE_TX_AFIFO_WM */ "", 46382 /* ILKN_SLE_TX_BURST */ "", 46383 /* ILKN_SLE_TX_CAL_ACC */ "", 46384 /* ILKN_SLE_TX_CAL_INBAND */ "", 46385 /* ILKN_SLE_TX_CAL_INBAND_DYN */ "", 46386 /* ILKN_SLE_TX_CAL_OUTBAND */ "", 46387 /* ILKN_SLE_TX_CAL_OUTBAND_DYN */ "", 46388 /* ILKN_SLE_TX_CAL_RD */ "", 46389 /* ILKN_SLE_TX_CAL_WT */ "", 46390 /* ILKN_SLE_TX_CFG */ "", 46391 /* ILKN_SLE_TX_CTL */ "", 46392 /* ILKN_SLE_TX_DAT_AFIFO_CORR_ERR */ "", 46393 /* ILKN_SLE_TX_DAT_AFIFO_CORR_ERR_2 */ "", 46394 /* ILKN_SLE_TX_DAT_AFIFO_OFLW_ERR */ "", 46395 /* ILKN_SLE_TX_DAT_AFIFO_OFLW_ERR_2 */ "", 46396 /* ILKN_SLE_TX_DAT_AFIFO_UFLW_ERR */ "", 46397 /* ILKN_SLE_TX_DAT_AFIFO_UFLW_ERR_2 */ "", 46398 /* ILKN_SLE_TX_DAT_AFIFO_UNCORR_ERR */ "", 46399 /* ILKN_SLE_TX_DAT_AFIFO_UNCORR_ERR_2 */ "", 46400 /* ILKN_SLE_TX_DEBUG_0 */ "", 46401 /* ILKN_SLE_TX_DEBUG_1 */ "", 46402 /* ILKN_SLE_TX_DEBUG_2 */ "", 46403 /* ILKN_SLE_TX_DEBUG_3 */ "", 46404 /* ILKN_SLE_TX_DEBUG_HOLD_0 */ "", 46405 /* ILKN_SLE_TX_DEBUG_HOLD_1 */ "", 46406 /* ILKN_SLE_TX_DEBUG_HOLD_2 */ "", 46407 /* ILKN_SLE_TX_DEBUG_HOLD_3 */ "", 46408 /* ILKN_SLE_TX_DEBUG_OBS_0 */ "", 46409 /* ILKN_SLE_TX_DEBUG_OBS_1 */ "", 46410 /* ILKN_SLE_TX_DEBUG_OBS_2 */ "", 46411 /* ILKN_SLE_TX_DEBUG_OBS_3 */ "", 46412 /* ILKN_SLE_TX_ERRINS_0 */ "", 46413 /* ILKN_SLE_TX_ERRINS_1 */ "", 46414 /* ILKN_SLE_TX_ERRINS_2 */ "", 46415 /* ILKN_SLE_TX_ERRINS_3 */ "", 46416 /* ILKN_SLE_TX_FCOB_RETRANSMIT_SLOT */ "", 46417 /* ILKN_SLE_TX_FCOB_RETRANSMIT_SLOT_DY */ "", 46418 /* ILKN_SLE_TX_FIFO_CFG */ "", 46419 /* ILKN_SLE_TX_INFO */ "", 46420 /* ILKN_SLE_TX_INFO_2 */ "", 46421 /* ILKN_SLE_TX_INFO_3 */ "", 46422 /* ILKN_SLE_TX_INT */ "", 46423 /* ILKN_SLE_TX_INT_2_ND */ "", 46424 /* ILKN_SLE_TX_INT_2_ND_MASK */ "", 46425 /* ILKN_SLE_TX_INT_FORCE */ "", 46426 /* ILKN_SLE_TX_INT_MASK */ "", 46427 /* ILKN_SLE_TX_LANE */ "", 46428 /* ILKN_SLE_TX_LANE_2 */ "", 46429 /* ILKN_SLE_TX_METAFRAME */ "", 46430 /* ILKN_SLE_TX_MSG */ "", 46431 /* ILKN_SLE_TX_MSG_2 */ "", 46432 /* ILKN_SLE_TX_PIPE_ENABLE */ "", 46433 /* ILKN_SLE_TX_RATE_0 */ "", 46434 /* ILKN_SLE_TX_RATE_1 */ "", 46435 /* ILKN_SLE_TX_REMAP_LANE_14_10 */ "", 46436 /* ILKN_SLE_TX_REMAP_LANE_19_15 */ "", 46437 /* ILKN_SLE_TX_REMAP_LANE_24_20 */ "", 46438 /* ILKN_SLE_TX_REMAP_LANE_29_25 */ "", 46439 /* ILKN_SLE_TX_REMAP_LANE_34_30 */ "", 46440 /* ILKN_SLE_TX_REMAP_LANE_39_35 */ "", 46441 /* ILKN_SLE_TX_REMAP_LANE_44_40 */ "", 46442 /* ILKN_SLE_TX_REMAP_LANE_47_45 */ "", 46443 /* ILKN_SLE_TX_REMAP_LANE_4_0 */ "", 46444 /* ILKN_SLE_TX_REMAP_LANE_9_5 */ "", 46445 /* ILKN_SLE_TX_RETRANSMIT_CONFIG */ "", 46446 /* ILKN_SLE_TX_SEGMENT_ENABLE */ "", 46447 /* ILKN_SLE_TX_SERDES_AFIFO_STALL_SEL */ "", 46448 /* ILKN_SLE_TX_SERDES_TEST_CNTL */ "", 46449 /* ILKN_SLE_TX_SERDES_TEST_PATTERNA */ "", 46450 /* ILKN_SLE_TX_SERDES_TEST_PATTERNB */ "", 46451 /* ILKN_SLE_TX_SERDES_TEST_PATTERNC */ "", 46452 /* ILKN_SLE_TX_STATS_ACC */ "", 46453 /* ILKN_SLE_TX_STATS_FILL */ "", 46454 /* ILKN_SLE_TX_STATS_PARITY */ "", 46455 /* ILKN_SLE_TX_STATS_RD_BYTE_HIGH */ "", 46456 /* ILKN_SLE_TX_STATS_RD_BYTE_LOW */ "", 46457 /* ILKN_SLE_TX_STATS_RD_ERR_HIGH */ "", 46458 /* ILKN_SLE_TX_STATS_RD_ERR_LOW */ "", 46459 /* ILKN_SLE_TX_STATS_RD_FLAG */ "", 46460 /* ILKN_SLE_TX_STATS_RD_PARITY */ "", 46461 /* ILKN_SLE_TX_STATS_RD_PKT_HIGH */ "", 46462 /* ILKN_SLE_TX_STATS_RD_PKT_LOW */ "", 46463 /* ILKN_SLE_TX_STATS_WT_BYTE_HIGH */ "", 46464 /* ILKN_SLE_TX_STATS_WT_BYTE_LOW */ "", 46465 /* ILKN_SLE_TX_STATS_WT_ERR_HIGH */ "", 46466 /* ILKN_SLE_TX_STATS_WT_ERR_LOW */ "", 46467 /* ILKN_SLE_TX_STATS_WT_PARITY */ "", 46468 /* ILKN_SLE_TX_STATS_WT_PKT_HIGH */ "", 46469 /* ILKN_SLE_TX_STATS_WT_PKT_LOW */ "", 46470 /* ILKN_X4_CONTROL0_ILKN_CONTROL0 */ "", 46471 /* ILKN_X4_STATUS0_ILKN_STATUS0 */ "", 46472 /* ILOCAL_SW_DISABLE_DEFAULT_PBM */ "", 46473 /* ILOCAL_SW_DISABLE_DEFAULT_PBM_64 */ "ILOCAL_SW_DISABLE_DEFAULT_PBM", 46474 /* ILOCAL_SW_DISABLE_DEFAULT_PBM_HI */ "ILOCAL_SW_DISABLE_DEFAULT_PBM_HI", 46475 /* ILOCAL_SW_DISABLE_DEFAULT_PBM_LO */ "ILOCAL_SW_DISABLE_DEFAULT_PBM_LO", 46476 /* ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR */ "ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR", 46477 /* ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64 */ "ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR", 46478 /* ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_HI */ "ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_HI", 46479 /* ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_LO */ "ILOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_LO", 46480 /* ILPM_CONTROL */ "", 46481 /* ILPM_EN_COR_ERR_RPT */ "", 46482 /* ILPM_MEMORY_DBGCTRL_1 */ "ILPM_MEMORY_CONTROL_1", 46483 /* ILPM_SER_CONTROL */ "", 46484 /* ILPM_SER_CONTROL_1 */ "", 46485 /* ILPM_TM_REG_1 */ "", 46486 /* ILPM_TM_REG_2 */ "", 46487 /* ILTOMC */ "", 46488 /* ILTOMC_64 */ "ILTOMC", 46489 /* IL_DEBUG_CAT4K_OOBFC */ "", 46490 /* IL_DEBUG_CONFIG */ "", 46491 /* IL_DEBUG_CREDIT */ "", 46492 /* IL_ECC_DEBUG0 */ "", 46493 /* IL_ECC_ERROR_ADDR_0 */ "", 46494 /* IL_ECC_ERROR_ADDR_1 */ "", 46495 /* IL_ECC_ERROR_L2_INTERRUPT_MASK */ "", 46496 /* IL_ECC_ERROR_L2_INTR */ "", 46497 /* IL_ERRINJ_CMDSTS_DONE */ "", 46498 /* IL_ERRINJ_CMDSTS_GO */ "", 46499 /* IL_ERRINJ_CONFIG_CONTINUOUS */ "", 46500 /* IL_ERRINJ_CONFIG_COUNT */ "", 46501 /* IL_ERRINJ_CONFIG_LANE_0 */ "", 46502 /* IL_FLOWCONTROL_CONFIG */ "", 46503 /* IL_FLOWCONTROL_L2_INTERRUPT_MASK */ "", 46504 /* IL_FLOWCONTROL_L2_INTR */ "", 46505 /* IL_FLOWCONTROL_OOB_RX_STS */ "", 46506 /* IL_FLOWCONTROL_RXFC_OVERRIDE_VAL0 */ "", 46507 /* IL_FLOWCONTROL_RXFC_OVERRIDE_VAL1 */ "", 46508 /* IL_FLOWCONTROL_RXFC_STS0 */ "", 46509 /* IL_FLOWCONTROL_RXFC_STS1 */ "", 46510 /* IL_FLOWCONTROL_TXFC_OVERRIDE_VAL0 */ "", 46511 /* IL_FLOWCONTROL_TXFC_OVERRIDE_VAL1 */ "", 46512 /* IL_FLOWCONTROL_TXFC_STS0 */ "", 46513 /* IL_FLOWCONTROL_TXFC_STS1 */ "", 46514 /* IL_GLOBAL_CONFIG */ "", 46515 /* IL_GLOBAL_CONTROL */ "", 46516 /* IL_GLOBAL_ERROR_STATUS */ "", 46517 /* IL_IEEE_CRC32_CONFIG */ "", 46518 /* IL_LOOPBACK_CONFIG */ "", 46519 /* IL_MEMORY_INIT */ "", 46520 /* IL_MEMORY_INIT_DONE */ "", 46521 /* IL_MEM_DEBUG0 */ "", 46522 /* IL_MEM_DEBUG1 */ "", 46523 /* IL_MEM_DEBUG2 */ "", 46524 /* IL_MU_LLFC_CONTROL */ "", 46525 /* IL_MU_LLFC_STATUS */ "", 46526 /* IL_PKTCAP_CHANNEL_SEL_0 */ "", 46527 /* IL_PKTCAP_CHANNEL_SEL_1 */ "", 46528 /* IL_PKTCAP_CONFIG */ "", 46529 /* IL_PKTCAP_CONTROL */ "", 46530 /* IL_PKTCAP_PKTHDR_0 */ "", 46531 /* IL_PKTCAP_PKTHDR_1 */ "", 46532 /* IL_PKTCAP_PKTHDR_2 */ "", 46533 /* IL_PKTCAP_PKTHDR_3 */ "", 46534 /* IL_PKTCAP_PKTHDR_4 */ "", 46535 /* IL_PKTCAP_PKTHDR_5 */ "", 46536 /* IL_PKTCAP_PKTHDR_6 */ "", 46537 /* IL_PKTCAP_PKTHDR_7 */ "", 46538 /* IL_PKTCAP_PKTHDR_8 */ "", 46539 /* IL_PKTCAP_PKTHDR_9 */ "", 46540 /* IL_PKTCAP_PKTHDR_10 */ "", 46541 /* IL_PKTCAP_PKTHDR_11 */ "", 46542 /* IL_PKTCAP_PKTHDR_12 */ "", 46543 /* IL_PKTCAP_PKTHDR_13 */ "", 46544 /* IL_PKTCAP_PKTHDR_14 */ "", 46545 /* IL_PKTCAP_PKTHDR_15 */ "", 46546 /* IL_PKTCAP_PKTHDR_16 */ "", 46547 /* IL_PKTCAP_PKTHDR_17 */ "", 46548 /* IL_PKTCAP_PKTHDR_18 */ "", 46549 /* IL_PKTCAP_PKTHDR_19 */ "", 46550 /* IL_PKTCAP_PKTHDR_20 */ "", 46551 /* IL_PKTCAP_PKTHDR_21 */ "", 46552 /* IL_PKTCAP_PKTHDR_22 */ "", 46553 /* IL_PKTCAP_PKTHDR_23 */ "", 46554 /* IL_PKTCAP_PKTHDR_24 */ "", 46555 /* IL_PKTCAP_PKTHDR_25 */ "", 46556 /* IL_PKTCAP_PKTHDR_26 */ "", 46557 /* IL_PKTCAP_PKTHDR_27 */ "", 46558 /* IL_PKTCAP_PKTHDR_28 */ "", 46559 /* IL_PKTCAP_PKTHDR_29 */ "", 46560 /* IL_PKTCAP_PKTHDR_30 */ "", 46561 /* IL_PKTCAP_PKTHDR_31 */ "", 46562 /* IL_PKTCAP_PKTHDR_32 */ "", 46563 /* IL_PKTCAP_PKTHDR_33 */ "", 46564 /* IL_PKTCAP_PKTHDR_34 */ "", 46565 /* IL_PKTCAP_PKTHDR_35 */ "", 46566 /* IL_PKTCAP_PKTHDR_36 */ "", 46567 /* IL_PKTCAP_PKTHDR_37 */ "", 46568 /* IL_PKTCAP_PKTHDR_38 */ "", 46569 /* IL_PKTCAP_PKTHDR_39 */ "", 46570 /* IL_PKTCAP_PKTHDR_40 */ "", 46571 /* IL_PKTCAP_PKTHDR_41 */ "", 46572 /* IL_PKTCAP_PKTHDR_42 */ "", 46573 /* IL_PKTCAP_PKTHDR_43 */ "", 46574 /* IL_PKTCAP_PKTHDR_44 */ "", 46575 /* IL_PKTCAP_PKTHDR_45 */ "", 46576 /* IL_PKTCAP_PKTHDR_46 */ "", 46577 /* IL_PKTCAP_PKTHDR_47 */ "", 46578 /* IL_PKTCAP_PKTHDR_48 */ "", 46579 /* IL_PKTCAP_PKTHDR_49 */ "", 46580 /* IL_PKTCAP_PKTHDR_50 */ "", 46581 /* IL_PKTCAP_PKTHDR_51 */ "", 46582 /* IL_PKTCAP_PKTHDR_52 */ "", 46583 /* IL_PKTCAP_PKTHDR_53 */ "", 46584 /* IL_PKTCAP_PKTHDR_54 */ "", 46585 /* IL_PKTCAP_PKTHDR_55 */ "", 46586 /* IL_PKTCAP_PKTHDR_56 */ "", 46587 /* IL_PKTCAP_PKTHDR_57 */ "", 46588 /* IL_PKTCAP_PKTHDR_58 */ "", 46589 /* IL_PKTCAP_PKTHDR_59 */ "", 46590 /* IL_PKTCAP_PKTHDR_60 */ "", 46591 /* IL_PKTCAP_PKTHDR_61 */ "", 46592 /* IL_PKTCAP_PKTHDR_62 */ "", 46593 /* IL_PKTCAP_PKTHDR_63 */ "", 46594 /* IL_PKTCAP_PKTSB_0 */ "", 46595 /* IL_PKTCAP_PKTSB_1 */ "", 46596 /* IL_PKTCAP_PKTSB_2 */ "", 46597 /* IL_PKTCAP_PKTSB_3 */ "", 46598 /* IL_PKTCAP_PKTSB_4 */ "", 46599 /* IL_PKTCAP_PKTSB_5 */ "", 46600 /* IL_PKTCAP_PKTSB_6 */ "", 46601 /* IL_PKTCAP_PKTSB_7 */ "", 46602 /* IL_PKTCAP_STATUS */ "", 46603 /* IL_PKTINJ_CONFIG0 */ "", 46604 /* IL_PKTINJ_CONFIG1 */ "", 46605 /* IL_PKTINJ_CONFIG2 */ "", 46606 /* IL_PKTINJ_CONFIG3 */ "", 46607 /* IL_PKTINJ_CONFIG4 */ "", 46608 /* IL_PKTINJ_CONFIG5 */ "", 46609 /* IL_PKTINJ_CONTROL */ "", 46610 /* IL_PKTINJ_PKTHDR_0 */ "", 46611 /* IL_PKTINJ_PKTHDR_1 */ "", 46612 /* IL_PKTINJ_PKTHDR_2 */ "", 46613 /* IL_PKTINJ_PKTHDR_3 */ "", 46614 /* IL_PKTINJ_PKTHDR_4 */ "", 46615 /* IL_PKTINJ_PKTHDR_5 */ "", 46616 /* IL_PKTINJ_PKTHDR_6 */ "", 46617 /* IL_PKTINJ_PKTHDR_7 */ "", 46618 /* IL_PKTINJ_PKTHDR_8 */ "", 46619 /* IL_PKTINJ_PKTHDR_9 */ "", 46620 /* IL_PKTINJ_PKTHDR_10 */ "", 46621 /* IL_PKTINJ_PKTHDR_11 */ "", 46622 /* IL_PKTINJ_PKTHDR_12 */ "", 46623 /* IL_PKTINJ_PKTHDR_13 */ "", 46624 /* IL_PKTINJ_PKTHDR_14 */ "", 46625 /* IL_PKTINJ_PKTHDR_15 */ "", 46626 /* IL_PKTINJ_PKTHDR_16 */ "", 46627 /* IL_PKTINJ_PKTHDR_17 */ "", 46628 /* IL_PKTINJ_PKTHDR_18 */ "", 46629 /* IL_PKTINJ_PKTHDR_19 */ "", 46630 /* IL_PKTINJ_PKTHDR_20 */ "", 46631 /* IL_PKTINJ_PKTHDR_21 */ "", 46632 /* IL_PKTINJ_PKTHDR_22 */ "", 46633 /* IL_PKTINJ_PKTHDR_23 */ "", 46634 /* IL_PKTINJ_PKTHDR_24 */ "", 46635 /* IL_PKTINJ_PKTHDR_25 */ "", 46636 /* IL_PKTINJ_PKTHDR_26 */ "", 46637 /* IL_PKTINJ_PKTHDR_27 */ "", 46638 /* IL_PKTINJ_PKTHDR_28 */ "", 46639 /* IL_PKTINJ_PKTHDR_29 */ "", 46640 /* IL_PKTINJ_PKTHDR_30 */ "", 46641 /* IL_PKTINJ_PKTHDR_31 */ "", 46642 /* IL_PKTINJ_PKTHDR_32 */ "", 46643 /* IL_PKTINJ_PKTHDR_33 */ "", 46644 /* IL_PKTINJ_PKTHDR_34 */ "", 46645 /* IL_PKTINJ_PKTHDR_35 */ "", 46646 /* IL_PKTINJ_PKTHDR_36 */ "", 46647 /* IL_PKTINJ_PKTHDR_37 */ "", 46648 /* IL_PKTINJ_PKTHDR_38 */ "", 46649 /* IL_PKTINJ_PKTHDR_39 */ "", 46650 /* IL_PKTINJ_PKTHDR_40 */ "", 46651 /* IL_PKTINJ_PKTHDR_41 */ "", 46652 /* IL_PKTINJ_PKTHDR_42 */ "", 46653 /* IL_PKTINJ_PKTHDR_43 */ "", 46654 /* IL_PKTINJ_PKTHDR_44 */ "", 46655 /* IL_PKTINJ_PKTHDR_45 */ "", 46656 /* IL_PKTINJ_PKTHDR_46 */ "", 46657 /* IL_PKTINJ_PKTHDR_47 */ "", 46658 /* IL_PKTINJ_PKTHDR_48 */ "", 46659 /* IL_PKTINJ_PKTHDR_49 */ "", 46660 /* IL_PKTINJ_PKTHDR_50 */ "", 46661 /* IL_PKTINJ_PKTHDR_51 */ "", 46662 /* IL_PKTINJ_PKTHDR_52 */ "", 46663 /* IL_PKTINJ_PKTHDR_53 */ "", 46664 /* IL_PKTINJ_PKTHDR_54 */ "", 46665 /* IL_PKTINJ_PKTHDR_55 */ "", 46666 /* IL_PKTINJ_PKTHDR_56 */ "", 46667 /* IL_PKTINJ_PKTHDR_57 */ "", 46668 /* IL_PKTINJ_PKTHDR_58 */ "", 46669 /* IL_PKTINJ_PKTHDR_59 */ "", 46670 /* IL_PKTINJ_PKTHDR_60 */ "", 46671 /* IL_PKTINJ_PKTHDR_61 */ "", 46672 /* IL_PKTINJ_PKTHDR_62 */ "", 46673 /* IL_PKTINJ_PKTHDR_63 */ "", 46674 /* IL_PKTINJ_STATUS */ "", 46675 /* IL_RX_CDR_LOCK_CONTROL */ "", 46676 /* IL_RX_CHAN_ENABLE0 */ "", 46677 /* IL_RX_CHAN_ENABLE1 */ "", 46678 /* IL_RX_CONFIG */ "", 46679 /* IL_RX_CORE_CONFIG0 */ "", 46680 /* IL_RX_CORE_CONFIG1 */ "", 46681 /* IL_RX_CORE_CONTROL0 */ "", 46682 /* IL_RX_CORE_STATUS0 */ "", 46683 /* IL_RX_CORE_STATUS1 */ "", 46684 /* IL_RX_CORE_STATUS2 */ "", 46685 /* IL_RX_CORE_STAT_MU_0 */ "", 46686 /* IL_RX_ERRDET0_L2_INTERRUPT_MASK */ "", 46687 /* IL_RX_ERRDET0_L2_INTR */ "", 46688 /* IL_RX_ERRDET1_L2_INTERRUPT_MASK */ "", 46689 /* IL_RX_ERRDET1_L2_INTR */ "", 46690 /* IL_RX_ERRDET2_L2_INTERRUPT_MASK */ "", 46691 /* IL_RX_ERRDET2_L2_INTR */ "", 46692 /* IL_RX_ERRDET3_L2_INTERRUPT_MASK */ "", 46693 /* IL_RX_ERRDET3_L2_INTR */ "", 46694 /* IL_RX_ERRDET4_L2_INTERRUPT_MASK */ "", 46695 /* IL_RX_ERRDET4_L2_INTR */ "", 46696 /* IL_RX_ERRDET5_L2_INTERRUPT_MASK */ "", 46697 /* IL_RX_ERRDET5_L2_INTR */ "", 46698 /* IL_RX_LANE_SWAP_CONTROL_0 */ "", 46699 /* IL_RX_LANE_SWAP_CONTROL_1 */ "", 46700 /* IL_RX_LANE_SWAP_CONTROL_2 */ "", 46701 /* IL_RX_LANE_SWAP_CONTROL_3 */ "", 46702 /* IL_RX_LANE_SWAP_CONTROL_4 */ "", 46703 /* IL_RX_LANE_SWAP_CONTROL_5 */ "", 46704 /* IL_RX_LANE_SWAP_CONTROL_6 */ "", 46705 /* IL_RX_LANE_SWAP_CONTROL_7 */ "", 46706 /* IL_RX_LANE_SWAP_CONTROL_8 */ "", 46707 /* IL_RX_LANE_SWAP_CONTROL_9 */ "", 46708 /* IL_RX_LANE_SWAP_CONTROL_10 */ "", 46709 /* IL_RX_LANE_SWAP_CONTROL_11 */ "", 46710 /* IL_RX_LANE_SWAP_CONTROL_12 */ "", 46711 /* IL_RX_LANE_SWAP_CONTROL_13 */ "", 46712 /* IL_RX_LANE_SWAP_CONTROL_14 */ "", 46713 /* IL_RX_LANE_SWAP_CONTROL_15 */ "", 46714 /* IL_STATS_RXSAT0_INTERRUPT_MASK */ "", 46715 /* IL_STATS_RXSAT0_INTR */ "", 46716 /* IL_STATS_RXSAT1_INTERRUPT_MASK */ "", 46717 /* IL_STATS_RXSAT1_INTR */ "", 46718 /* IL_STATS_TXSAT0_INTERRUPT_MASK */ "", 46719 /* IL_STATS_TXSAT0_INTR */ "", 46720 /* IL_STATS_TXSAT1_INTERRUPT_MASK */ "", 46721 /* IL_STATS_TXSAT1_INTR */ "", 46722 /* IL_TX_CHAN_ENABLE0 */ "", 46723 /* IL_TX_CHAN_ENABLE1 */ "", 46724 /* IL_TX_CONFIG */ "", 46725 /* IL_TX_CORE_CONFIG0 */ "", 46726 /* IL_TX_CORE_CONFIG1 */ "", 46727 /* IL_TX_CORE_CONFIG2 */ "", 46728 /* IL_TX_CORE_CONTROL0 */ "", 46729 /* IL_TX_CORE_CONTROL_MU_0 */ "", 46730 /* IL_TX_ERRDET0_L2_INTERRUPT_MASK */ "", 46731 /* IL_TX_ERRDET0_L2_INTR */ "", 46732 /* IL_TX_LANE_SWAP_CONTROL_0 */ "", 46733 /* IL_TX_LANE_SWAP_CONTROL_1 */ "", 46734 /* IL_TX_LANE_SWAP_CONTROL_2 */ "", 46735 /* IL_TX_LANE_SWAP_CONTROL_3 */ "", 46736 /* IL_TX_LANE_SWAP_CONTROL_4 */ "", 46737 /* IL_TX_LANE_SWAP_CONTROL_5 */ "", 46738 /* IL_TX_LANE_SWAP_CONTROL_6 */ "", 46739 /* IL_TX_LANE_SWAP_CONTROL_7 */ "", 46740 /* IL_TX_LANE_SWAP_CONTROL_8 */ "", 46741 /* IL_TX_LANE_SWAP_CONTROL_9 */ "", 46742 /* IL_TX_LANE_SWAP_CONTROL_10 */ "", 46743 /* IL_TX_LANE_SWAP_CONTROL_11 */ "", 46744 /* IL_TX_LANE_SWAP_CONTROL_12 */ "", 46745 /* IL_TX_LANE_SWAP_CONTROL_13 */ "", 46746 /* IL_TX_LANE_SWAP_CONTROL_14 */ "", 46747 /* IL_TX_LANE_SWAP_CONTROL_15 */ "", 46748 /* IL_TX_REF_CLOCK_SELECT */ "", 46749 /* IMIRROR_BITMAP */ "", 46750 /* IMIRROR_BITMAP_64 */ "IMIRROR_BITMAP", 46751 /* IMIRROR_BITMAP_HI */ "", 46752 /* IMIRROR_BITMAP_LO */ "", 46753 /* IMIRROR_BITMAP_PARITY_CONTROL */ "", 46754 /* IMIRROR_BITMAP_PARITY_STATUS_INTR */ "", 46755 /* IMIRROR_BITMAP_PARITY_STATUS_NACK */ "", 46756 /* IMIRROR_CONTROL */ "", 46757 /* IMMU_FUSE_DEBUG0 */ "", 46758 /* IMMU_FUSE_DEBUG1 */ "", 46759 /* IMMU_FUSE_DEBUG2 */ "", 46760 /* IMPLS_CLK_GATING_CONTROL */ "", 46761 /* IMPLS_EN_COR_ERR_RPT */ "", 46762 /* IMPLS_SER_CONTROL */ "", 46763 /* IMP_ECC_1B_ERR_CNT */ "", 46764 /* IMP_ECC_2B_ERR_CNT */ "", 46765 /* IMP_ECC_ERR_1B_INITIATE */ "", 46766 /* IMP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 46767 /* IMP_ECC_ERR_2B_INITIATE */ "", 46768 /* IMP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 46769 /* IMP_ECC_INTERRUPT_REGISTER */ "", 46770 /* IMP_ECC_INTERRUPT_REGISTER_MASK */ "", 46771 /* IMP_ECC_INTERRUPT_REGISTER_TEST */ "", 46772 /* IMP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 46773 /* IMP_ERROR_INITIATION_DATA */ "", 46774 /* IMP_GLBL_CFG */ "", 46775 /* IMP_GLOBAL_GENERAL_CFG_2 */ "", 46776 /* IMP_GLOBAL_MEM_OPTIONS */ "", 46777 /* IMP_GTIMER_CONFIGURATION */ "", 46778 /* IMP_IDR_INTERFACE_DEBUG_COUNTERS */ "", 46779 /* IMP_INCOMING_COLOR_MAP */ "", 46780 /* IMP_INDIRECT_COMMAND */ "", 46781 /* IMP_INDIRECT_COMMAND_ADDRESS */ "", 46782 /* IMP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 46783 /* IMP_INDIRECT_COMMAND_RD_DATA */ "", 46784 /* IMP_INDIRECT_COMMAND_WIDE_MEM */ "", 46785 /* IMP_INDIRECT_COMMAND_WR_DATA */ "", 46786 /* IMP_INDIRECT_FORCE_BUBBLE */ "", 46787 /* IMP_INGRESS_IN_INTERFACE_DEBUG_COUNTERS */ "", 46788 /* IMP_INGRESS_OUT_INTERFACE_DEBUG_COUNTERS */ "", 46789 /* IMP_INIT_SEQ_ON */ "", 46790 /* IMP_INTERRUPT_MASK_REGISTER */ "", 46791 /* IMP_INTERRUPT_REGISTER */ "", 46792 /* IMP_INTERRUPT_REGISTER_TEST */ "", 46793 /* IMP_MCDA_CBL_STAT_CTR */ "", 46794 /* IMP_MCDA_CFG */ "", 46795 /* IMP_MCDA_EBL_STAT_CTR */ "", 46796 /* IMP_MCDA_LAST_CMD_INDEX */ "", 46797 /* IMP_MCDA_OOP_FIFO_CNT */ "", 46798 /* IMP_MCDA_OOP_FIFO_POINTER_MASK */ "", 46799 /* IMP_MCDA_OOP_FIFO_RD_RESULTS */ "", 46800 /* IMP_MCDA_REFRESH_CFG */ "", 46801 /* IMP_MCDA_STAT_CFG */ "", 46802 /* IMP_MCDA_WRAP_INDEX */ "", 46803 /* IMP_MCDB_CBL_STAT_CTR */ "", 46804 /* IMP_MCDB_CFG */ "", 46805 /* IMP_MCDB_EBL_STAT_CTR */ "", 46806 /* IMP_MCDB_LAST_CMD_INDEX */ "", 46807 /* IMP_MCDB_OOP_FIFO_CNT */ "", 46808 /* IMP_MCDB_OOP_FIFO_POINTER_MASK */ "", 46809 /* IMP_MCDB_OOP_FIFO_RD_RESULTS */ "", 46810 /* IMP_MCDB_REFRESH_CFG */ "", 46811 /* IMP_MCDB_STAT_CFG */ "", 46812 /* IMP_MCDB_WRAP_INDEX */ "", 46813 /* IMP_RESERVED_MIRROR_ADDR */ "", 46814 /* IMP_RESERVED_MTCD */ "", 46815 /* IMP_RESERVED_MTCP */ "", 46816 /* IMP_RESERVED_SPARE_0 */ "", 46817 /* IMP_RESERVED_SPARE_1 */ "", 46818 /* IMP_RESERVED_SPARE_2 */ "", 46819 /* IMP_RESERVED_SPARE_3 */ "", 46820 /* IMP_SBUS_BROADCAST_ID */ "", 46821 /* IMP_SBUS_LAST_IN_CHAIN */ "", 46822 /* IMRP4 */ "", 46823 /* IMRP6 */ "", 46824 /* IMRP4_64 */ "IMRP4", 46825 /* IMRP6_64 */ "IMRP6", 46826 /* ING_1588OMPLS */ "", 46827 /* ING_1588_INGRESS_CTRL_PARITY_CONTROL */ "", 46828 /* ING_1588_PARSING_CONTROL */ "", 46829 /* ING_1588_PROFILE_TABLE_PARITY_CONTROL */ "", 46830 /* ING_BYPASS_CTRL */ "", 46831 /* ING_CONFIG */ "", 46832 /* ING_CONFIG_2 */ "", 46833 /* ING_CONFIG_64 */ "ING_CONFIG", 46834 /* ING_COS_MODE */ "ING_COS_MODE_64", 46835 /* ING_COS_MODE_64 */ "", 46836 /* ING_DNAT_ADDRESS_TYPE_B0_PDA */ "", 46837 /* ING_DNAT_ADDRESS_TYPE_B0_TM */ "", 46838 /* ING_DNAT_ADDRESS_TYPE_B1_PDA */ "", 46839 /* ING_DNAT_ADDRESS_TYPE_B1_TM */ "", 46840 /* ING_DNAT_ADDRESS_TYPE_CAM_CONTROL */ "", 46841 /* ING_DNAT_ADDRESS_TYPE_HASH_CONTROL */ "", 46842 /* ING_DNAT_ADDRESS_TYPE_RAM_CONTROL */ "", 46843 /* ING_DNAT_ADDRESS_TYPE_RAM_CONTROL_PIPE0 */ "", 46844 /* ING_DNAT_ADDRESS_TYPE_RAM_CONTROL_PIPE1 */ "", 46845 /* ING_DNAT_ADDRESS_TYPE_RAM_CONTROL_PIPE2 */ "", 46846 /* ING_DNAT_ADDRESS_TYPE_RAM_CONTROL_PIPE3 */ "", 46847 /* ING_DNAT_ADDRESS_TYPE_TCAM_BIST_CONFIG */ "", 46848 /* ING_DNAT_ADDRESS_TYPE_TCAM_BIST_CONTROL */ "", 46849 /* ING_DNAT_ADDRESS_TYPE_TCAM_BIST_DBG_DATA */ "", 46850 /* ING_DNAT_ADDRESS_TYPE_TCAM_BIST_STATUS */ "", 46851 /* ING_DOP_CTRL_0_64 */ "", 46852 /* ING_DOP_CTRL_0_64_PIPE0 */ "", 46853 /* ING_DOP_CTRL_0_64_PIPE1 */ "", 46854 /* ING_DOP_CTRL_1_64 */ "", 46855 /* ING_DOP_CTRL_1_64_PIPE0 */ "", 46856 /* ING_DOP_CTRL_1_64_PIPE1 */ "", 46857 /* ING_DOP_CTRL_2_64 */ "", 46858 /* ING_DOP_CTRL_2_64_PIPE0 */ "", 46859 /* ING_DOP_CTRL_2_64_PIPE1 */ "", 46860 /* ING_DOP_STATUS_0 */ "", 46861 /* ING_DOP_STATUS_0_PIPE0 */ "", 46862 /* ING_DOP_STATUS_0_PIPE1 */ "", 46863 /* ING_DOP_STATUS_1_64 */ "", 46864 /* ING_DOP_STATUS_1_64_PIPE0 */ "", 46865 /* ING_DOP_STATUS_1_64_PIPE1 */ "", 46866 /* ING_DROPPKT_CNT */ "", 46867 /* ING_DROP_PG_MASK */ "", 46868 /* ING_DVP_PARITY_CONTROL */ "", 46869 /* ING_DVP_PARITY_STATUS_INTR */ "", 46870 /* ING_DVP_PARITY_STATUS_NACK */ "", 46871 /* ING_DVP_TABLE_DBGCTRL_0 */ "ING_DVP_TABLE_CONTROL_0", 46872 /* ING_DVP_TABLE_ECCP_CONTROL */ "", 46873 /* ING_DVP_TABLE_PARITY_CONTROL */ "", 46874 /* ING_DVP_TABLE_PARITY_STATUS_INTR */ "", 46875 /* ING_DVP_TABLE_PARITY_STATUS_NACK */ "", 46876 /* ING_EAV_CLASS */ "", 46877 /* ING_ECN_COUNTER_64 */ "ING_ECN_COUNTER", 46878 /* ING_EGRMSKBMAP */ "", 46879 /* ING_EGRMSKBMAP_64 */ "ING_EGRMSKBMAP", 46880 /* ING_EGRMSKBMAP_HI */ "ING_EGRMSKBMAP_HI", 46881 /* ING_EGRMSKBMAP_LO */ "ING_EGRMSKBMAP_LO", 46882 /* ING_EGRMSKBMAP_PARITY_CONTROL */ "", 46883 /* ING_EGRMSKBMAP_PARITY_STATUS_INTR */ "", 46884 /* ING_EGRMSKBMAP_PARITY_STATUS_NACK */ "", 46885 /* ING_EN_EFILTER_BITMAP */ "ING_EN_EFILTER_BITMAP", 46886 /* ING_EN_EFILTER_BITMAP_64 */ "ING_EN_EFILTER_BITMAP", 46887 /* ING_EN_EFILTER_BITMAP_HI */ "ING_EN_EFILTER_BITMAP_HI", 46888 /* ING_EN_EFILTER_BITMAP_LO */ "ING_EN_EFILTER_BITMAP_LO", 46889 /* ING_ETAG_PCP_MAPPING_CONTROL_DBGCTRL */ "ING_ETAG_PCP_MAPPING_CONTROL", 46890 /* ING_ETAG_PCP_MAPPING_CONTROL_DBGCTRL_PIPE0 */ "ING_ETAG_PCP_MAPPING_CONTROL_PIPE0", 46891 /* ING_ETAG_PCP_MAPPING_CONTROL_DBGCTRL_PIPE1 */ "ING_ETAG_PCP_MAPPING_CONTROL_PIPE1", 46892 /* ING_ETAG_PCP_MAPPING_CONTROL_DBGCTRL_PIPE2 */ "ING_ETAG_PCP_MAPPING_CONTROL_PIPE2", 46893 /* ING_ETAG_PCP_MAPPING_CONTROL_DBGCTRL_PIPE3 */ "ING_ETAG_PCP_MAPPING_CONTROL_PIPE3", 46894 /* ING_ETAG_PCP_MAPPING_DATA_DBGCTRL */ "ING_ETAG_PCP_MAPPING_DATA_CONTROL", 46895 /* ING_ETAG_PCP_MAPPING_PARITY_CONTROL */ "", 46896 /* ING_ETAG_PCP_MAPPING_PARITY_STATUS */ "", 46897 /* ING_EVENT_DEBUG */ "", 46898 /* ING_EVENT_DEBUG_2 */ "", 46899 /* ING_EVENT_DEBUG_3 */ "", 46900 /* ING_EVENT_DEBUG_4 */ "", 46901 /* ING_EVENT_DEBUG_2_PIPE0 */ "", 46902 /* ING_EVENT_DEBUG_2_PIPE1 */ "", 46903 /* ING_EVENT_DEBUG_2_PIPE2 */ "", 46904 /* ING_EVENT_DEBUG_2_PIPE3 */ "", 46905 /* ING_EVENT_DEBUG_2_PIPE4 */ "", 46906 /* ING_EVENT_DEBUG_2_PIPE5 */ "", 46907 /* ING_EVENT_DEBUG_2_PIPE6 */ "", 46908 /* ING_EVENT_DEBUG_2_PIPE7 */ "", 46909 /* ING_EVENT_DEBUG_2_X */ "", 46910 /* ING_EVENT_DEBUG_2_Y */ "", 46911 /* ING_EVENT_DEBUG_3_PIPE0 */ "", 46912 /* ING_EVENT_DEBUG_3_PIPE1 */ "", 46913 /* ING_EVENT_DEBUG_3_PIPE2 */ "", 46914 /* ING_EVENT_DEBUG_3_PIPE3 */ "", 46915 /* ING_EVENT_DEBUG_3_PIPE4 */ "", 46916 /* ING_EVENT_DEBUG_3_PIPE5 */ "", 46917 /* ING_EVENT_DEBUG_3_PIPE6 */ "", 46918 /* ING_EVENT_DEBUG_3_PIPE7 */ "", 46919 /* ING_EVENT_DEBUG_3_X */ "", 46920 /* ING_EVENT_DEBUG_3_Y */ "", 46921 /* ING_EVENT_DEBUG_4_PIPE0 */ "", 46922 /* ING_EVENT_DEBUG_4_PIPE1 */ "", 46923 /* ING_EVENT_DEBUG_4_PIPE2 */ "", 46924 /* ING_EVENT_DEBUG_4_PIPE3 */ "", 46925 /* ING_EVENT_DEBUG_4_PIPE4 */ "", 46926 /* ING_EVENT_DEBUG_4_PIPE5 */ "", 46927 /* ING_EVENT_DEBUG_4_PIPE6 */ "", 46928 /* ING_EVENT_DEBUG_4_PIPE7 */ "", 46929 /* ING_EVENT_DEBUG_MASK */ "", 46930 /* ING_EVENT_DEBUG_PIPE0 */ "", 46931 /* ING_EVENT_DEBUG_PIPE1 */ "", 46932 /* ING_EVENT_DEBUG_PIPE2 */ "", 46933 /* ING_EVENT_DEBUG_PIPE3 */ "", 46934 /* ING_EVENT_DEBUG_PIPE4 */ "", 46935 /* ING_EVENT_DEBUG_PIPE5 */ "", 46936 /* ING_EVENT_DEBUG_PIPE6 */ "", 46937 /* ING_EVENT_DEBUG_PIPE7 */ "", 46938 /* ING_EVENT_DEBUG_X */ "", 46939 /* ING_EVENT_DEBUG_Y */ "", 46940 /* ING_FCOE_ETHERTYPE */ "", 46941 /* ING_FLEX_CONFIG */ "", 46942 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_0 */ "", 46943 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_1 */ "", 46944 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_2 */ "", 46945 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_3 */ "", 46946 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_4 */ "", 46947 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_5 */ "", 46948 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_6 */ "", 46949 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_7 */ "", 46950 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_8 */ "", 46951 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_9 */ "", 46952 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_10 */ "", 46953 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_11 */ "", 46954 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_12 */ "", 46955 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_13 */ "", 46956 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_14 */ "", 46957 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_15 */ "", 46958 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_16 */ "", 46959 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_17 */ "", 46960 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_18 */ "", 46961 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_19 */ "", 46962 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_0 */ "", 46963 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_1 */ "", 46964 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_2 */ "", 46965 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_3 */ "", 46966 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_4 */ "", 46967 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_5 */ "", 46968 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_6 */ "", 46969 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_7 */ "", 46970 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_0 */ "", 46971 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_1 */ "", 46972 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_2 */ "", 46973 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_3 */ "", 46974 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_4 */ "", 46975 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_5 */ "", 46976 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_6 */ "", 46977 /* ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_7 */ "", 46978 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_0 */ "", 46979 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_1 */ "", 46980 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_2 */ "", 46981 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_3 */ "", 46982 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_4 */ "", 46983 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_5 */ "", 46984 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_6 */ "", 46985 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_7 */ "", 46986 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_8 */ "", 46987 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_9 */ "", 46988 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_10 */ "", 46989 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_11 */ "", 46990 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_12 */ "", 46991 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_13 */ "", 46992 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_14 */ "", 46993 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_15 */ "", 46994 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_16 */ "", 46995 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_17 */ "", 46996 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_18 */ "", 46997 /* ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_19 */ "", 46998 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0 */ "", 46999 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1 */ "", 47000 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2 */ "", 47001 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3 */ "", 47002 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4 */ "", 47003 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5 */ "", 47004 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6 */ "", 47005 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7 */ "", 47006 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8 */ "", 47007 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9 */ "", 47008 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10 */ "", 47009 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11 */ "", 47010 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12 */ "", 47011 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13 */ "", 47012 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14 */ "", 47013 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15 */ "", 47014 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16 */ "", 47015 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17 */ "", 47016 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18 */ "", 47017 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19 */ "", 47018 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE0 */ "", 47019 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE1 */ "", 47020 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE2 */ "", 47021 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE3 */ "", 47022 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE4 */ "", 47023 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE5 */ "", 47024 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE6 */ "", 47025 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_0_PIPE7 */ "", 47026 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE0 */ "", 47027 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE1 */ "", 47028 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE2 */ "", 47029 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE3 */ "", 47030 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE4 */ "", 47031 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE5 */ "", 47032 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE6 */ "", 47033 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_10_PIPE7 */ "", 47034 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE0 */ "", 47035 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE1 */ "", 47036 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE2 */ "", 47037 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE3 */ "", 47038 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE4 */ "", 47039 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE5 */ "", 47040 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE6 */ "", 47041 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_11_PIPE7 */ "", 47042 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE0 */ "", 47043 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE1 */ "", 47044 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE2 */ "", 47045 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE3 */ "", 47046 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE4 */ "", 47047 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE5 */ "", 47048 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE6 */ "", 47049 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_12_PIPE7 */ "", 47050 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE0 */ "", 47051 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE1 */ "", 47052 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE2 */ "", 47053 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE3 */ "", 47054 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE4 */ "", 47055 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE5 */ "", 47056 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE6 */ "", 47057 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_13_PIPE7 */ "", 47058 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE0 */ "", 47059 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE1 */ "", 47060 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE2 */ "", 47061 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE3 */ "", 47062 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE4 */ "", 47063 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE5 */ "", 47064 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE6 */ "", 47065 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_14_PIPE7 */ "", 47066 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE0 */ "", 47067 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE1 */ "", 47068 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE2 */ "", 47069 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE3 */ "", 47070 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE4 */ "", 47071 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE5 */ "", 47072 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE6 */ "", 47073 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_15_PIPE7 */ "", 47074 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE0 */ "", 47075 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE1 */ "", 47076 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE2 */ "", 47077 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE3 */ "", 47078 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE4 */ "", 47079 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE5 */ "", 47080 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE6 */ "", 47081 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_16_PIPE7 */ "", 47082 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE0 */ "", 47083 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE1 */ "", 47084 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE2 */ "", 47085 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE3 */ "", 47086 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE4 */ "", 47087 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE5 */ "", 47088 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE6 */ "", 47089 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_17_PIPE7 */ "", 47090 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE0 */ "", 47091 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE1 */ "", 47092 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE2 */ "", 47093 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE3 */ "", 47094 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE4 */ "", 47095 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE5 */ "", 47096 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE6 */ "", 47097 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_18_PIPE7 */ "", 47098 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE0 */ "", 47099 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE1 */ "", 47100 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE2 */ "", 47101 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE3 */ "", 47102 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE4 */ "", 47103 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE5 */ "", 47104 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE6 */ "", 47105 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_19_PIPE7 */ "", 47106 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE0 */ "", 47107 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE1 */ "", 47108 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE2 */ "", 47109 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE3 */ "", 47110 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE4 */ "", 47111 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE5 */ "", 47112 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE6 */ "", 47113 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_1_PIPE7 */ "", 47114 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE0 */ "", 47115 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE1 */ "", 47116 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE2 */ "", 47117 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE3 */ "", 47118 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE4 */ "", 47119 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE5 */ "", 47120 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE6 */ "", 47121 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_2_PIPE7 */ "", 47122 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE0 */ "", 47123 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE1 */ "", 47124 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE2 */ "", 47125 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE3 */ "", 47126 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE4 */ "", 47127 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE5 */ "", 47128 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE6 */ "", 47129 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_3_PIPE7 */ "", 47130 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE0 */ "", 47131 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE1 */ "", 47132 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE2 */ "", 47133 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE3 */ "", 47134 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE4 */ "", 47135 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE5 */ "", 47136 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE6 */ "", 47137 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_4_PIPE7 */ "", 47138 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE0 */ "", 47139 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE1 */ "", 47140 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE2 */ "", 47141 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE3 */ "", 47142 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE4 */ "", 47143 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE5 */ "", 47144 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE6 */ "", 47145 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_5_PIPE7 */ "", 47146 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE0 */ "", 47147 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE1 */ "", 47148 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE2 */ "", 47149 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE3 */ "", 47150 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE4 */ "", 47151 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE5 */ "", 47152 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE6 */ "", 47153 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_6_PIPE7 */ "", 47154 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE0 */ "", 47155 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE1 */ "", 47156 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE2 */ "", 47157 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE3 */ "", 47158 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE4 */ "", 47159 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE5 */ "", 47160 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE6 */ "", 47161 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_7_PIPE7 */ "", 47162 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE0 */ "", 47163 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE1 */ "", 47164 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE2 */ "", 47165 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE3 */ "", 47166 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE4 */ "", 47167 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE5 */ "", 47168 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE6 */ "", 47169 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_8_PIPE7 */ "", 47170 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE0 */ "", 47171 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE1 */ "", 47172 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE2 */ "", 47173 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE3 */ "", 47174 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE4 */ "", 47175 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE5 */ "", 47176 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE6 */ "", 47177 /* ING_FLEX_CTR_EVICTION_CONTROL_POOL_9_PIPE7 */ "", 47178 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0 */ "", 47179 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1 */ "", 47180 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2 */ "", 47181 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3 */ "", 47182 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4 */ "", 47183 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5 */ "", 47184 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6 */ "", 47185 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7 */ "", 47186 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8 */ "", 47187 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9 */ "", 47188 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10 */ "", 47189 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11 */ "", 47190 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12 */ "", 47191 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13 */ "", 47192 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14 */ "", 47193 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15 */ "", 47194 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16 */ "", 47195 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17 */ "", 47196 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18 */ "", 47197 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19 */ "", 47198 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE0 */ "", 47199 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE1 */ "", 47200 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE2 */ "", 47201 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE3 */ "", 47202 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE4 */ "", 47203 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE5 */ "", 47204 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE6 */ "", 47205 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_0_PIPE7 */ "", 47206 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE0 */ "", 47207 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE1 */ "", 47208 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE2 */ "", 47209 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE3 */ "", 47210 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE4 */ "", 47211 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE5 */ "", 47212 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE6 */ "", 47213 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_10_PIPE7 */ "", 47214 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE0 */ "", 47215 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE1 */ "", 47216 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE2 */ "", 47217 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE3 */ "", 47218 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE4 */ "", 47219 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE5 */ "", 47220 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE6 */ "", 47221 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_11_PIPE7 */ "", 47222 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE0 */ "", 47223 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE1 */ "", 47224 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE2 */ "", 47225 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE3 */ "", 47226 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE4 */ "", 47227 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE5 */ "", 47228 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE6 */ "", 47229 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_12_PIPE7 */ "", 47230 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE0 */ "", 47231 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE1 */ "", 47232 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE2 */ "", 47233 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE3 */ "", 47234 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE4 */ "", 47235 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE5 */ "", 47236 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE6 */ "", 47237 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_13_PIPE7 */ "", 47238 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE0 */ "", 47239 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE1 */ "", 47240 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE2 */ "", 47241 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE3 */ "", 47242 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE4 */ "", 47243 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE5 */ "", 47244 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE6 */ "", 47245 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_14_PIPE7 */ "", 47246 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE0 */ "", 47247 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE1 */ "", 47248 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE2 */ "", 47249 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE3 */ "", 47250 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE4 */ "", 47251 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE5 */ "", 47252 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE6 */ "", 47253 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_15_PIPE7 */ "", 47254 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE0 */ "", 47255 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE1 */ "", 47256 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE2 */ "", 47257 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE3 */ "", 47258 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE4 */ "", 47259 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE5 */ "", 47260 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE6 */ "", 47261 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_16_PIPE7 */ "", 47262 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE0 */ "", 47263 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE1 */ "", 47264 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE2 */ "", 47265 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE3 */ "", 47266 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE4 */ "", 47267 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE5 */ "", 47268 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE6 */ "", 47269 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_17_PIPE7 */ "", 47270 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE0 */ "", 47271 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE1 */ "", 47272 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE2 */ "", 47273 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE3 */ "", 47274 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE4 */ "", 47275 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE5 */ "", 47276 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE6 */ "", 47277 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_18_PIPE7 */ "", 47278 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE0 */ "", 47279 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE1 */ "", 47280 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE2 */ "", 47281 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE3 */ "", 47282 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE4 */ "", 47283 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE5 */ "", 47284 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE6 */ "", 47285 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_19_PIPE7 */ "", 47286 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE0 */ "", 47287 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE1 */ "", 47288 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE2 */ "", 47289 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE3 */ "", 47290 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE4 */ "", 47291 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE5 */ "", 47292 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE6 */ "", 47293 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_1_PIPE7 */ "", 47294 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE0 */ "", 47295 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE1 */ "", 47296 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE2 */ "", 47297 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE3 */ "", 47298 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE4 */ "", 47299 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE5 */ "", 47300 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE6 */ "", 47301 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_2_PIPE7 */ "", 47302 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE0 */ "", 47303 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE1 */ "", 47304 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE2 */ "", 47305 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE3 */ "", 47306 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE4 */ "", 47307 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE5 */ "", 47308 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE6 */ "", 47309 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_3_PIPE7 */ "", 47310 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE0 */ "", 47311 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE1 */ "", 47312 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE2 */ "", 47313 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE3 */ "", 47314 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE4 */ "", 47315 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE5 */ "", 47316 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE6 */ "", 47317 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_4_PIPE7 */ "", 47318 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE0 */ "", 47319 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE1 */ "", 47320 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE2 */ "", 47321 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE3 */ "", 47322 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE4 */ "", 47323 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE5 */ "", 47324 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE6 */ "", 47325 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_5_PIPE7 */ "", 47326 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE0 */ "", 47327 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE1 */ "", 47328 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE2 */ "", 47329 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE3 */ "", 47330 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE4 */ "", 47331 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE5 */ "", 47332 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE6 */ "", 47333 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_6_PIPE7 */ "", 47334 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE0 */ "", 47335 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE1 */ "", 47336 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE2 */ "", 47337 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE3 */ "", 47338 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE4 */ "", 47339 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE5 */ "", 47340 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE6 */ "", 47341 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_7_PIPE7 */ "", 47342 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE0 */ "", 47343 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE1 */ "", 47344 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE2 */ "", 47345 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE3 */ "", 47346 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE4 */ "", 47347 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE5 */ "", 47348 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE6 */ "", 47349 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_8_PIPE7 */ "", 47350 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE0 */ "", 47351 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE1 */ "", 47352 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE2 */ "", 47353 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE3 */ "", 47354 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE4 */ "", 47355 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE5 */ "", 47356 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE6 */ "", 47357 /* ING_FLEX_CTR_EVICTION_FAIL_POOL_9_PIPE7 */ "", 47358 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0 */ "", 47359 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1 */ "", 47360 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2 */ "", 47361 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3 */ "", 47362 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4 */ "", 47363 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5 */ "", 47364 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6 */ "", 47365 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7 */ "", 47366 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8 */ "", 47367 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9 */ "", 47368 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10 */ "", 47369 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11 */ "", 47370 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12 */ "", 47371 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13 */ "", 47372 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14 */ "", 47373 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15 */ "", 47374 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16 */ "", 47375 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17 */ "", 47376 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18 */ "", 47377 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19 */ "", 47378 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE0 */ "", 47379 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE1 */ "", 47380 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE2 */ "", 47381 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE3 */ "", 47382 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE4 */ "", 47383 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE5 */ "", 47384 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE6 */ "", 47385 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_0_PIPE7 */ "", 47386 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE0 */ "", 47387 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE1 */ "", 47388 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE2 */ "", 47389 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE3 */ "", 47390 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE4 */ "", 47391 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE5 */ "", 47392 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE6 */ "", 47393 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_10_PIPE7 */ "", 47394 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE0 */ "", 47395 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE1 */ "", 47396 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE2 */ "", 47397 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE3 */ "", 47398 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE4 */ "", 47399 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE5 */ "", 47400 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE6 */ "", 47401 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_11_PIPE7 */ "", 47402 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE0 */ "", 47403 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE1 */ "", 47404 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE2 */ "", 47405 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE3 */ "", 47406 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE4 */ "", 47407 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE5 */ "", 47408 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE6 */ "", 47409 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_12_PIPE7 */ "", 47410 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE0 */ "", 47411 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE1 */ "", 47412 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE2 */ "", 47413 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE3 */ "", 47414 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE4 */ "", 47415 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE5 */ "", 47416 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE6 */ "", 47417 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_13_PIPE7 */ "", 47418 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE0 */ "", 47419 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE1 */ "", 47420 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE2 */ "", 47421 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE3 */ "", 47422 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE4 */ "", 47423 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE5 */ "", 47424 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE6 */ "", 47425 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_14_PIPE7 */ "", 47426 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE0 */ "", 47427 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE1 */ "", 47428 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE2 */ "", 47429 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE3 */ "", 47430 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE4 */ "", 47431 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE5 */ "", 47432 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE6 */ "", 47433 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_15_PIPE7 */ "", 47434 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE0 */ "", 47435 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE1 */ "", 47436 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE2 */ "", 47437 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE3 */ "", 47438 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE4 */ "", 47439 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE5 */ "", 47440 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE6 */ "", 47441 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_16_PIPE7 */ "", 47442 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE0 */ "", 47443 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE1 */ "", 47444 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE2 */ "", 47445 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE3 */ "", 47446 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE4 */ "", 47447 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE5 */ "", 47448 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE6 */ "", 47449 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_17_PIPE7 */ "", 47450 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE0 */ "", 47451 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE1 */ "", 47452 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE2 */ "", 47453 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE3 */ "", 47454 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE4 */ "", 47455 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE5 */ "", 47456 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE6 */ "", 47457 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_18_PIPE7 */ "", 47458 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE0 */ "", 47459 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE1 */ "", 47460 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE2 */ "", 47461 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE3 */ "", 47462 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE4 */ "", 47463 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE5 */ "", 47464 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE6 */ "", 47465 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_19_PIPE7 */ "", 47466 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE0 */ "", 47467 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE1 */ "", 47468 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE2 */ "", 47469 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE3 */ "", 47470 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE4 */ "", 47471 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE5 */ "", 47472 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE6 */ "", 47473 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_1_PIPE7 */ "", 47474 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE0 */ "", 47475 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE1 */ "", 47476 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE2 */ "", 47477 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE3 */ "", 47478 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE4 */ "", 47479 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE5 */ "", 47480 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE6 */ "", 47481 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_2_PIPE7 */ "", 47482 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE0 */ "", 47483 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE1 */ "", 47484 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE2 */ "", 47485 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE3 */ "", 47486 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE4 */ "", 47487 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE5 */ "", 47488 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE6 */ "", 47489 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_3_PIPE7 */ "", 47490 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE0 */ "", 47491 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE1 */ "", 47492 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE2 */ "", 47493 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE3 */ "", 47494 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE4 */ "", 47495 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE5 */ "", 47496 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE6 */ "", 47497 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_4_PIPE7 */ "", 47498 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE0 */ "", 47499 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE1 */ "", 47500 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE2 */ "", 47501 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE3 */ "", 47502 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE4 */ "", 47503 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE5 */ "", 47504 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE6 */ "", 47505 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_5_PIPE7 */ "", 47506 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE0 */ "", 47507 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE1 */ "", 47508 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE2 */ "", 47509 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE3 */ "", 47510 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE4 */ "", 47511 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE5 */ "", 47512 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE6 */ "", 47513 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_6_PIPE7 */ "", 47514 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE0 */ "", 47515 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE1 */ "", 47516 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE2 */ "", 47517 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE3 */ "", 47518 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE4 */ "", 47519 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE5 */ "", 47520 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE6 */ "", 47521 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_7_PIPE7 */ "", 47522 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE0 */ "", 47523 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE1 */ "", 47524 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE2 */ "", 47525 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE3 */ "", 47526 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE4 */ "", 47527 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE5 */ "", 47528 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE6 */ "", 47529 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_8_PIPE7 */ "", 47530 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE0 */ "", 47531 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE1 */ "", 47532 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE2 */ "", 47533 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE3 */ "", 47534 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE4 */ "", 47535 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE5 */ "", 47536 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE6 */ "", 47537 /* ING_FLEX_CTR_EVICTION_LFSR_SEED_POOL_9_PIPE7 */ "", 47538 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_0 */ "", 47539 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_1 */ "", 47540 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_2 */ "", 47541 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_3 */ "", 47542 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_4 */ "", 47543 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_5 */ "", 47544 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_6 */ "", 47545 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_7 */ "", 47546 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_8 */ "", 47547 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_9 */ "", 47548 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_10 */ "", 47549 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_11 */ "", 47550 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_12 */ "", 47551 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_13 */ "", 47552 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_14 */ "", 47553 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_15 */ "", 47554 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_16 */ "", 47555 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_17 */ "", 47556 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_18 */ "", 47557 /* ING_FLEX_CTR_EVICTION_THRESHOLD_POOL_19 */ "", 47558 /* ING_FLEX_CTR_LM_CONFIG */ "", 47559 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_0 */ "", 47560 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_1 */ "", 47561 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_2 */ "", 47562 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_3 */ "", 47563 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_4 */ "", 47564 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_5 */ "", 47565 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_6 */ "", 47566 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_7 */ "", 47567 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_8 */ "", 47568 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_9 */ "", 47569 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_10 */ "", 47570 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_11 */ "", 47571 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_12 */ "", 47572 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_13 */ "", 47573 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_14 */ "", 47574 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_15 */ "", 47575 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_16 */ "", 47576 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_17 */ "", 47577 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_18 */ "", 47578 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_19 */ "", 47579 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_0 */ "", 47580 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_1 */ "", 47581 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_2 */ "", 47582 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_3 */ "", 47583 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_4 */ "", 47584 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_5 */ "", 47585 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_6 */ "", 47586 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_7 */ "", 47587 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_0 */ "", 47588 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_1 */ "", 47589 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_2 */ "", 47590 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_3 */ "", 47591 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_4 */ "", 47592 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_5 */ "", 47593 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_6 */ "", 47594 /* ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_7 */ "", 47595 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_0 */ "", 47596 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_1 */ "", 47597 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_2 */ "", 47598 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_3 */ "", 47599 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_4 */ "", 47600 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_5 */ "", 47601 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_6 */ "", 47602 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_7 */ "", 47603 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_8 */ "", 47604 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_9 */ "", 47605 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_10 */ "", 47606 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_11 */ "", 47607 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_12 */ "", 47608 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_13 */ "", 47609 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_14 */ "", 47610 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_15 */ "", 47611 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_16 */ "", 47612 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_17 */ "", 47613 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_18 */ "", 47614 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_19 */ "", 47615 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_20 */ "", 47616 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_21 */ "", 47617 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_22 */ "", 47618 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_23 */ "", 47619 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_24 */ "", 47620 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_25 */ "", 47621 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_26 */ "", 47622 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_27 */ "", 47623 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_28 */ "", 47624 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_29 */ "", 47625 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_30 */ "", 47626 /* ING_FLEX_CTR_PKT_ATTR_SELECTOR_KEY_31 */ "", 47627 /* ING_FLEX_CTR_PKT_PRI_MAP_PARITY_CONTROL */ "", 47628 /* ING_FLEX_CTR_PKT_RES_MAP_PARITY_CONTROL */ "", 47629 /* ING_FLEX_CTR_PKT_RES_MAP_PARITY_STATUS_INTR */ "", 47630 /* ING_FLEX_CTR_PKT_RES_MAP_PARITY_STATUS_NACK */ "", 47631 /* ING_FLEX_CTR_PRI_CNG_MAP_PARITY_CONTROL */ "", 47632 /* ING_FLEX_CTR_TOS_MAP_PARITY_CONTROL */ "", 47633 /* ING_GBP_ETHERTYPE */ "", 47634 /* ING_GTP_CONTROL */ "", 47635 /* ING_HASH_CONFIG_0 */ "", 47636 /* ING_HBFC_CNM_ETHERTYPE */ "", 47637 /* ING_HBFC_CNTAG_ETHERTYPE */ "", 47638 /* ING_HIGIG_TRUNK_OVERRIDE_PROFILE_PARITY_CONTROL */ "", 47639 /* ING_HIGIG_TRUNK_OVERRIDE_PROFILE_PARITY_STATUS_INTR */ "", 47640 /* ING_HIGIG_TRUNK_OVERRIDE_PROFILE_PARITY_STATUS_NACK */ "", 47641 /* ING_HW_RESET_CONTROL_1 */ "", 47642 /* ING_HW_RESET_CONTROL_2 */ "", 47643 /* ING_HW_RESET_CONTROL_1_PIPE0 */ "", 47644 /* ING_HW_RESET_CONTROL_1_PIPE1 */ "", 47645 /* ING_HW_RESET_CONTROL_1_PIPE2 */ "", 47646 /* ING_HW_RESET_CONTROL_1_PIPE3 */ "", 47647 /* ING_HW_RESET_CONTROL_1_PIPE4 */ "", 47648 /* ING_HW_RESET_CONTROL_1_PIPE5 */ "", 47649 /* ING_HW_RESET_CONTROL_1_PIPE6 */ "", 47650 /* ING_HW_RESET_CONTROL_1_PIPE7 */ "", 47651 /* ING_HW_RESET_CONTROL_2_PIPE0 */ "", 47652 /* ING_HW_RESET_CONTROL_2_PIPE1 */ "", 47653 /* ING_HW_RESET_CONTROL_2_PIPE2 */ "", 47654 /* ING_HW_RESET_CONTROL_2_PIPE3 */ "", 47655 /* ING_HW_RESET_CONTROL_2_PIPE4 */ "", 47656 /* ING_HW_RESET_CONTROL_2_PIPE5 */ "", 47657 /* ING_HW_RESET_CONTROL_2_PIPE6 */ "", 47658 /* ING_HW_RESET_CONTROL_2_PIPE7 */ "", 47659 /* ING_HW_RESET_CONTROL_2_X */ "", 47660 /* ING_HW_RESET_CONTROL_2_Y */ "", 47661 /* ING_ICNM_ID */ "", 47662 /* ING_ICNM_MACDA_LS */ "", 47663 /* ING_ICNM_MACDA_MS */ "", 47664 /* ING_ICNM_MACSA_LS */ "", 47665 /* ING_ICNM_MACSA_MS */ "", 47666 /* ING_IPFIX_CONFIG */ "", 47667 /* ING_IPFIX_CURRENT_TIME */ "", 47668 /* ING_IPFIX_DBG_CONTROL */ "", 47669 /* ING_IPFIX_EOP_BUF_PARITY_CONTROL */ "", 47670 /* ING_IPFIX_EOP_BUF_PARITY_STATUS_INTR */ "", 47671 /* ING_IPFIX_EOP_BUF_PARITY_STATUS_NACK */ "", 47672 /* ING_IPFIX_EXPORT_FIFO_COUNTER */ "", 47673 /* ING_IPFIX_EXPORT_FIFO_PARITY_CONTROL */ "", 47674 /* ING_IPFIX_EXPORT_FIFO_PARITY_STATUS */ "", 47675 /* ING_IPFIX_EXPORT_FIFO_PARITY_STATUS_NACK */ "", 47676 /* ING_IPFIX_EXPORT_FIFO_READ_PTR */ "", 47677 /* ING_IPFIX_EXPORT_FIFO_WRITE_PTR */ "", 47678 /* ING_IPFIX_FLOW_PARITY_CONTROL */ "", 47679 /* ING_IPFIX_FLOW_PARITY_STATUS_INTR */ "", 47680 /* ING_IPFIX_FLOW_PARITY_STATUS_NACK */ "", 47681 /* ING_IPFIX_FLOW_RATE_CONTROL */ "", 47682 /* ING_IPFIX_HASH_CONTROL */ "", 47683 /* ING_IPFIX_MAXIMUM_IDLE_AGE_SET */ "", 47684 /* ING_IPFIX_MAXIMUM_LIVE_TIME_SET */ "", 47685 /* ING_IPFIX_MINIMUM_LIVE_TIME_SET */ "", 47686 /* ING_IPFIX_MIRROR_CONTROL_64 */ "", 47687 /* ING_IPFIX_MISSED_BUCKET_FULL_COUNT */ "", 47688 /* ING_IPFIX_MISSED_EXPORT_FULL_COUNT */ "", 47689 /* ING_IPFIX_MISSED_PORT_LIMIT_COUNT */ "", 47690 /* ING_IPFIX_PDA_CONTROL */ "", 47691 /* ING_IPFIX_PORT_CONFIG */ "", 47692 /* ING_IPFIX_PORT_LIMIT_STATUS */ "", 47693 /* ING_IPFIX_PORT_RECORD_COUNT */ "", 47694 /* ING_IPFIX_PORT_RECORD_LIMIT_SET */ "", 47695 /* ING_IPFIX_PORT_SAMPLING_COUNTER */ "", 47696 /* ING_IPFIX_RAM_CONTROL */ "", 47697 /* ING_IPFIX_SAMPLING_LIMIT_SET */ "", 47698 /* ING_IPFIX_SER_CONTROL */ "", 47699 /* ING_IPFIX_SESSION_PARITY_CONTROL */ "", 47700 /* ING_IPFIX_SESSION_PARITY_STATUS */ "", 47701 /* ING_IPFIX_SESSION_PARITY_STATUS_INTR_0 */ "", 47702 /* ING_IPFIX_SESSION_PARITY_STATUS_INTR_1 */ "", 47703 /* ING_IPFIX_SESSION_PARITY_STATUS_NACK_0 */ "", 47704 /* ING_IPFIX_SESSION_PARITY_STATUS_NACK_1 */ "", 47705 /* ING_IPMC_PTR_CTRL */ "", 47706 /* ING_L2_TUNNEL_PARSE_CONTROL */ "", 47707 /* ING_L3_ECMP_BANK_SEL */ "", 47708 /* ING_L3_ECMP_GROUP_BANK_SEL */ "", 47709 /* ING_L3_NEXT_HOP_BANK_SEL */ "", 47710 /* ING_L3_NEXT_HOP_DBGCTRL */ "ING_L3_NEXT_HOP_CONTROL", 47711 /* ING_L3_NEXT_HOP_DEBUG */ "", 47712 /* ING_L3_NEXT_HOP_ECCP_CONTROL */ "", 47713 /* ING_L3_NEXT_HOP_PARITY_CONTROL */ "", 47714 /* ING_L3_NEXT_HOP_PARITY_STATUS */ "", 47715 /* ING_L3_NEXT_HOP_PARITY_STATUS_INTR */ "", 47716 /* ING_L3_NEXT_HOP_PARITY_STATUS_NACK */ "", 47717 /* ING_LATENCY_CONTROL */ "", 47718 /* ING_LLTAG_TPID */ "", 47719 /* ING_LMFC_EOP_BUFFER_0_PARITY_CONTROL */ "", 47720 /* ING_LMFC_EOP_BUFFER_1_PARITY_CONTROL */ "", 47721 /* ING_LMFC_EOP_BUFFER_2_PARITY_CONTROL */ "", 47722 /* ING_LM_RAM_CONTROL_1 */ "", 47723 /* ING_LM_RAM_CONTROL_0_64 */ "", 47724 /* ING_MEMRD_ALL_CTRL */ "", 47725 /* ING_MIRROR_COS_CONTROL */ "", 47726 /* ING_MISC_CONFIG */ "", 47727 /* ING_MISC_CONFIG2 */ "", 47728 /* ING_MISC_CONFIG3 */ "", 47729 /* ING_MISC_PORT_CONFIG */ "", 47730 /* ING_MODMAP_CTRL */ "", 47731 /* ING_MOD_MAP_DATA_CONTROL */ "", 47732 /* ING_MOD_MAP_PARITY_CONTROL */ "", 47733 /* ING_MOD_MAP_PARITY_STATUS */ "", 47734 /* ING_MPLS_INNER_TPID */ "", 47735 /* ING_MPLS_TPID */ "", 47736 /* ING_MPLS_TPID_0 */ "", 47737 /* ING_MPLS_TPID_1 */ "", 47738 /* ING_MPLS_TPID_2 */ "", 47739 /* ING_MPLS_TPID_3 */ "", 47740 /* ING_NIV_CONFIG */ "", 47741 /* ING_NIV_RX_FRAMES_ERROR_DROP */ "ING_NIV_RFED", 47742 /* ING_NIV_RX_FRAMES_ERROR_DROP_64 */ "ING_NIV_RX_FRAMES_ERROR_DROP", 47743 /* ING_NIV_RX_FRAMES_FORWARDING_DROP */ "ING_NIV_RFFD", 47744 /* ING_NIV_RX_FRAMES_FORWARDING_DROP_64 */ "ING_NIV_RX_FRAMES_FORWARDING_DROP", 47745 /* ING_NIV_RX_FRAMES_VLAN_TAGGED */ "ING_NIV_RFVT", 47746 /* ING_NIV_RX_FRAMES_VLAN_TAGGED_64 */ "ING_NIV_RX_FRAMES_VLAN_TAGGED", 47747 /* ING_OAM_LM_CNG_CONTROL */ "", 47748 /* ING_OAM_LM_COUNTERS_0_ECC_CONTROL */ "", 47749 /* ING_OAM_LM_COUNTERS_1_ECC_CONTROL */ "", 47750 /* ING_OAM_LM_COUNTERS_2_ECC_CONTROL */ "", 47751 /* ING_OLP_CONFIG_0_64 */ "", 47752 /* ING_OLP_CONFIG_1_64 */ "", 47753 /* ING_OUTER_TPID */ "", 47754 /* ING_OUTER_TPID_0 */ "", 47755 /* ING_OUTER_TPID_1 */ "", 47756 /* ING_OUTER_TPID_2 */ "", 47757 /* ING_OUTER_TPID_3 */ "", 47758 /* ING_PACKET_PROCESSING_CONTROL_0 */ "", 47759 /* ING_PACKET_PROCESSING_CONTROL_1 */ "", 47760 /* ING_PBI_DEBUG_CTRL_0_64 */ "", 47761 /* ING_PBI_DEBUG_CTRL_1_64 */ "", 47762 /* ING_PHYSICAL_PORT_TABLE_PARITY_CONTROL */ "", 47763 /* ING_PHYSICAL_PORT_TABLE_PARITY_STATUS_INTR */ "", 47764 /* ING_PHYSICAL_PORT_TABLE_PARITY_STATUS_NACK */ "", 47765 /* ING_PORT_THROTTLE_CFG */ "", 47766 /* ING_PORT_THROTTLE_ENABLE_64 */ "ING_PORT_THROTTLE_ENABLE", 47767 /* ING_PORT_THROTTLE_ENABLE_64_1 */ "ING_PORT_THROTTLE_ENABLE_1", 47768 /* ING_PRI_CNG_MAP_PARITY_CONTROL */ "", 47769 /* ING_PRI_CNG_MAP_PARITY_STATUS_INTR */ "", 47770 /* ING_PRI_CNG_MAP_PARITY_STATUS_NACK */ "", 47771 /* ING_PROC_CONTROL */ "", 47772 /* ING_PW_TERM_SEQ_NUM_PARITY_CONTROL */ "", 47773 /* ING_PW_TERM_SEQ_NUM_PARITY_STATUS_INTR */ "", 47774 /* ING_PW_TERM_SEQ_NUM_PARITY_STATUS_NACK */ "", 47775 /* ING_QCN_CNM_ETHERTYPE */ "", 47776 /* ING_QCN_CNTAG_ETHERTYPE */ "", 47777 /* ING_QUEUE_MAP_PARITY_CONTROL */ "", 47778 /* ING_QUEUE_MAP_PARITY_STATUS_INTR */ "", 47779 /* ING_QUEUE_MAP_PARITY_STATUS_NACK */ "", 47780 /* ING_Q_BEGIN */ "", 47781 /* ING_Q_BEGIN_PIPE0 */ "", 47782 /* ING_Q_BEGIN_PIPE1 */ "", 47783 /* ING_Q_BEGIN_PIPE2 */ "", 47784 /* ING_Q_BEGIN_PIPE3 */ "", 47785 /* ING_Q_BEGIN_PIPE4 */ "", 47786 /* ING_Q_BEGIN_PIPE5 */ "", 47787 /* ING_Q_BEGIN_PIPE6 */ "", 47788 /* ING_Q_BEGIN_PIPE7 */ "", 47789 /* ING_ROCE_CONTROL */ "", 47790 /* ING_RX_COUNTER_PARITY_CONTROL */ "", 47791 /* ING_RX_COUNTER_PARITY_STATUS */ "", 47792 /* ING_SAT_SAMP_DATA_PARITY_CONTROL */ "", 47793 /* ING_SAT_SAMP_TCAM_BIST_CONFIG */ "", 47794 /* ING_SAT_SAMP_TCAM_BIST_DBG_DATA */ "", 47795 /* ING_SAT_SAMP_TCAM_BIST_STATUS */ "", 47796 /* ING_SAT_SAMP_TCAM_DBGCTRL */ "ING_SAT_SAMP_TCAM_CONTROL", 47797 /* ING_SAT_SAMP_TM_CONTROL */ "", 47798 /* ING_SCTP_CONTROL */ "", 47799 /* ING_SERVICE_COUNTER_TABLE_PARITY_CONTROL */ "", 47800 /* ING_SERVICE_COUNTER_TABLE_PARITY_STATUS_INTR */ "", 47801 /* ING_SERVICE_COUNTER_TABLE_PARITY_STATUS_NACK */ "", 47802 /* ING_SERVICE_PRI_MAP_0_PARITY_CONTROL */ "", 47803 /* ING_SERVICE_PRI_MAP_1_PARITY_CONTROL */ "", 47804 /* ING_SERVICE_PRI_MAP_2_PARITY_CONTROL */ "", 47805 /* ING_SER_FIFO_CTRL */ "", 47806 /* ING_SER_FIFO_CTRL_PIPE0 */ "", 47807 /* ING_SER_FIFO_CTRL_PIPE1 */ "", 47808 /* ING_SER_FIFO_CTRL_PIPE2 */ "", 47809 /* ING_SER_FIFO_CTRL_PIPE3 */ "", 47810 /* ING_SER_FIFO_CTRL_PIPE4 */ "", 47811 /* ING_SER_FIFO_CTRL_PIPE5 */ "", 47812 /* ING_SER_FIFO_CTRL_PIPE6 */ "", 47813 /* ING_SER_FIFO_CTRL_PIPE7 */ "", 47814 /* ING_SER_FIFO_STATUS */ "", 47815 /* ING_SNAT_CAM_BIST_CONFIG */ "", 47816 /* ING_SNAT_CAM_BIST_CONFIG_64 */ "", 47817 /* ING_SNAT_CAM_BIST_CONFIG_64_PIPE0 */ "", 47818 /* ING_SNAT_CAM_BIST_CONFIG_64_PIPE1 */ "", 47819 /* ING_SNAT_CAM_BIST_CONFIG_64_PIPE2 */ "", 47820 /* ING_SNAT_CAM_BIST_CONFIG_64_PIPE3 */ "", 47821 /* ING_SNAT_CAM_BIST_CONFIG_PIPE0 */ "", 47822 /* ING_SNAT_CAM_BIST_CONFIG_PIPE1 */ "", 47823 /* ING_SNAT_CAM_BIST_CONFIG_PIPE2 */ "", 47824 /* ING_SNAT_CAM_BIST_CONFIG_PIPE3 */ "", 47825 /* ING_SNAT_CAM_BIST_CONTROL */ "", 47826 /* ING_SNAT_CAM_BIST_CONTROL_PIPE0 */ "", 47827 /* ING_SNAT_CAM_BIST_CONTROL_PIPE1 */ "", 47828 /* ING_SNAT_CAM_BIST_CONTROL_PIPE2 */ "", 47829 /* ING_SNAT_CAM_BIST_CONTROL_PIPE3 */ "", 47830 /* ING_SNAT_CAM_BIST_DBG_DATA */ "", 47831 /* ING_SNAT_CAM_BIST_DBG_DATA_PIPE0 */ "", 47832 /* ING_SNAT_CAM_BIST_DBG_DATA_PIPE1 */ "", 47833 /* ING_SNAT_CAM_BIST_DBG_DATA_PIPE2 */ "", 47834 /* ING_SNAT_CAM_BIST_DBG_DATA_PIPE3 */ "", 47835 /* ING_SNAT_CAM_BIST_STATUS */ "", 47836 /* ING_SNAT_CAM_BIST_STATUS_PIPE0 */ "", 47837 /* ING_SNAT_CAM_BIST_STATUS_PIPE1 */ "", 47838 /* ING_SNAT_CAM_BIST_STATUS_PIPE2 */ "", 47839 /* ING_SNAT_CAM_BIST_STATUS_PIPE3 */ "", 47840 /* ING_SNAT_CAM_CONTROL */ "", 47841 /* ING_SNAT_CAM_CONTROL_PIPE0 */ "", 47842 /* ING_SNAT_CAM_CONTROL_PIPE1 */ "", 47843 /* ING_SNAT_CAM_CONTROL_PIPE2 */ "", 47844 /* ING_SNAT_CAM_CONTROL_PIPE3 */ "", 47845 /* ING_SOURCE_PORT_IDENTITY_MASK */ "", 47846 /* ING_SVM_CONTROL */ "", 47847 /* ING_SVM_EN_COR_ERR_RPT */ "", 47848 /* ING_SVM_MACROFLOW_INDEX_TABLE_CONTROL */ "", 47849 /* ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_INTR */ "", 47850 /* ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_NACK */ "", 47851 /* ING_SVM_METER_TABLE_COM_CONTROL */ "", 47852 /* ING_SVM_METER_TABLE_CONFIG_CONTROL */ "", 47853 /* ING_SVM_METER_TABLE_CONTROL */ "", 47854 /* ING_SVM_METER_TABLE_EXC_CONTROL */ "", 47855 /* ING_SVM_METER_TABLE_LRN_CONTROL */ "", 47856 /* ING_SVM_METER_TABLE_PARITY_STATUS_INTR */ "", 47857 /* ING_SVM_METER_TABLE_PARITY_STATUS_NACK */ "", 47858 /* ING_SVM_METER_TABLE_PDA */ "", 47859 /* ING_SVM_OFFSET_TABLE_CONTROL */ "", 47860 /* ING_SVM_OFFSET_TABLE_PARITY_STATUS_INTR */ "", 47861 /* ING_SVM_OFFSET_TABLE_PARITY_STATUS_NACK */ "", 47862 /* ING_SVM_PKT_ATTR_SELECTOR_KEY_0 */ "", 47863 /* ING_SVM_PKT_ATTR_SELECTOR_KEY_1 */ "", 47864 /* ING_SVM_PKT_ATTR_SELECTOR_KEY_2 */ "", 47865 /* ING_SVM_PKT_ATTR_SELECTOR_KEY_3 */ "", 47866 /* ING_SVM_PKT_PRI_MAP_PARITY_CONTROL */ "", 47867 /* ING_SVM_PKT_RES_MAP_PARITY_CONTROL */ "", 47868 /* ING_SVM_POLICY_TABLE_CONTROL */ "", 47869 /* ING_SVM_POLICY_TABLE_PARITY_STATUS_INTR */ "", 47870 /* ING_SVM_POLICY_TABLE_PARITY_STATUS_NACK */ "", 47871 /* ING_SVM_SER_CONTROL */ "", 47872 /* ING_SVM_TOS_MAP_PARITY_CONTROL */ "", 47873 /* ING_SYS_RSVD_VID */ "", 47874 /* ING_TRILL_ADJACENCY */ "", 47875 /* ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED */ "", 47876 /* ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_64 */ "ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED", 47877 /* ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED */ "", 47878 /* ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_64 */ "ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED", 47879 /* ING_TRILL_RX_PKTS */ "", 47880 /* ING_TRILL_RX_PKTS_64 */ "ING_TRILL_RX_PKTS", 47881 /* ING_UNTAGGED_PHB_PARITY_CONTROL */ "", 47882 /* ING_UNTAGGED_PHB_PARITY_STATUS_INTR */ "", 47883 /* ING_UNTAGGED_PHB_PARITY_STATUS_NACK */ "", 47884 /* ING_VINTF_COUNTER_TABLE_PARITY_CONTROL */ "", 47885 /* ING_VINTF_COUNTER_TABLE_PARITY_STATUS_INTR */ "", 47886 /* ING_VINTF_COUNTER_TABLE_PARITY_STATUS_NACK */ "", 47887 /* ING_VLAN_COUNTER_PARITY_CONTROL */ "", 47888 /* ING_VLAN_COUNTER_PARITY_STATUS */ "", 47889 /* ING_VLAN_TAG_ACTION_PROFILE_CONTROL_DBGCTRL */ "ING_VLAN_TAG_ACTION_PROFILE_CONTROL", 47890 /* ING_VLAN_TAG_ACTION_PROFILE_CONTROL_DBGCTRL_PIPE0 */ "ING_VLAN_TAG_ACTION_PROFILE_CONTROL_PIPE0", 47891 /* ING_VLAN_TAG_ACTION_PROFILE_CONTROL_DBGCTRL_PIPE1 */ "ING_VLAN_TAG_ACTION_PROFILE_CONTROL_PIPE1", 47892 /* ING_VLAN_TAG_ACTION_PROFILE_CONTROL_DBGCTRL_PIPE2 */ "ING_VLAN_TAG_ACTION_PROFILE_CONTROL_PIPE2", 47893 /* ING_VLAN_TAG_ACTION_PROFILE_CONTROL_DBGCTRL_PIPE3 */ "ING_VLAN_TAG_ACTION_PROFILE_CONTROL_PIPE3", 47894 /* ING_VLAN_TAG_ACTION_PROFILE_DATA_DBGCTRL */ "ING_VLAN_TAG_ACTION_PROFILE_DATA_CONTROL", 47895 /* ING_VOQFC_ID */ "", 47896 /* ING_VOQFC_MACDA_LS */ "", 47897 /* ING_VOQFC_MACDA_MS */ "", 47898 /* ING_VP_VLAN_MEMBERSHIP_B0_PDA */ "", 47899 /* ING_VP_VLAN_MEMBERSHIP_B0_TM */ "", 47900 /* ING_VP_VLAN_MEMBERSHIP_B1_PDA */ "", 47901 /* ING_VP_VLAN_MEMBERSHIP_B1_TM */ "", 47902 /* ING_VP_VLAN_MEMBERSHIP_HASH_CONTROL */ "", 47903 /* ING_VP_VLAN_MEMBERSHIP_RAM_CONTROL */ "", 47904 /* ING_VXLAN_CONTROL */ "", 47905 /* ING_VXLT2_CONFIG */ "", 47906 /* ING_WESP_PROTO_CONTROL */ "", 47907 /* INITIAL_ING_L3_ECMP_BANK_SEL */ "", 47908 /* INITIAL_ING_L3_ECMP_GROUP_BANK_SEL */ "", 47909 /* INITIAL_ING_L3_NEXT_HOP_BANK_SEL */ "", 47910 /* INITIAL_ING_L3_NEXT_HOP_ECCP_CONTROL */ "", 47911 /* INITIAL_ING_L3_NEXT_HOP_PARITY_CONTROL */ "", 47912 /* INITIAL_ING_L3_NEXT_HOP_PARITY_STATUS */ "", 47913 /* INITIAL_ING_L3_NEXT_HOP_PARITY_STATUS_INTR */ "", 47914 /* INITIAL_ING_L3_NEXT_HOP_PARITY_STATUS_NACK */ "", 47915 /* INITIAL_L3_ECMP_ECCP_CONTROL */ "", 47916 /* INITIAL_L3_ECMP_GROUP_ECCP_CONTROL */ "", 47917 /* INITIAL_L3_ECMP_GROUP_PARITY_CONTROL */ "", 47918 /* INITIAL_L3_ECMP_GROUP_PARITY_STATUS */ "", 47919 /* INITIAL_L3_ECMP_GROUP_PARITY_STATUS_INTR */ "", 47920 /* INITIAL_L3_ECMP_GROUP_PARITY_STATUS_NACK */ "", 47921 /* INITIAL_L3_ECMP_PARITY_CONTROL */ "", 47922 /* INITIAL_L3_ECMP_PARITY_STATUS */ "", 47923 /* INITIAL_L3_ECMP_PARITY_STATUS_INTR */ "", 47924 /* INITIAL_L3_ECMP_PARITY_STATUS_NACK */ "", 47925 /* INITIAL_NHOP_PARITY_CONTROL */ "", 47926 /* INITIAL_NHOP_PARITY_STATUS */ "", 47927 /* INITIAL_NHOP_PARITY_STATUS_INTR */ "", 47928 /* INITIAL_NHOP_PARITY_STATUS_NACK */ "", 47929 /* INITIAL_PROT_NHI_TABLE_1_DMA_PARITY_CONTROL */ "", 47930 /* INITIAL_PROT_NHI_TABLE_1_DMA_PARITY_STATUS_INTR */ "", 47931 /* INITIAL_PROT_NHI_TABLE_1_DMA_PARITY_STATUS_NACK */ "", 47932 /* INITIAL_PROT_NHI_TABLE_ECCP_CONTROL */ "", 47933 /* INITIAL_PROT_NHI_TABLE_PARITY_CONTROL */ "", 47934 /* INITIAL_PROT_NHI_TABLE_PARITY_STATUS_INTR */ "", 47935 /* INITIAL_PROT_NHI_TABLE_PARITY_STATUS_NACK */ "", 47936 /* INI_ECMP_GRP_PARITY_CONTROL */ "", 47937 /* INI_ECMP_GRP_PARITY_STATUS_INTR */ "", 47938 /* INI_ECMP_GRP_PARITY_STATUS_NACK */ "", 47939 /* INI_L3_ECMP_PARITY_CONTROL */ "", 47940 /* INI_L3_ECMP_PARITY_STATUS_INTR */ "", 47941 /* INI_L3_ECMP_PARITY_STATUS_NACK */ "", 47942 /* INI_PROT_NHI_PARITY_CONTROL */ "", 47943 /* INI_PROT_NHI_PARITY_STATUS_INTR */ "", 47944 /* INI_PROT_NHI_PARITY_STATUS_NACK */ "", 47945 /* INNER_TPID */ "", 47946 /* INPUT_PORT_RX_ENABLE */ "", 47947 /* INPUT_PORT_RX_ENABLE0_64 */ "INPUT_PORT_RX_ENABLE0", 47948 /* INPUT_PORT_RX_ENABLE1_64 */ "INPUT_PORT_RX_ENABLE1", 47949 /* INPUT_PORT_RX_ENABLE_64 */ "INPUT_PORT_RX_ENABLE", 47950 /* INSTRUMENT_CPU_COS_CONFIG */ "", 47951 /* INTC_INTR_ENABLE_REG0 */ "", 47952 /* INTC_INTR_ENABLE_REG1 */ "", 47953 /* INTC_INTR_ENABLE_REG2 */ "", 47954 /* INTC_INTR_ENABLE_REG3 */ "", 47955 /* INTC_INTR_ENABLE_REG4 */ "", 47956 /* INTC_INTR_ENABLE_REG5 */ "", 47957 /* INTC_INTR_ENABLE_REG6 */ "", 47958 /* INTC_INTR_ENABLE_REG7 */ "", 47959 /* INTC_INTR_RAW_STATUS_REG0 */ "", 47960 /* INTC_INTR_RAW_STATUS_REG1 */ "", 47961 /* INTC_INTR_RAW_STATUS_REG2 */ "", 47962 /* INTC_INTR_RAW_STATUS_REG3 */ "", 47963 /* INTC_INTR_RAW_STATUS_REG4 */ "", 47964 /* INTC_INTR_RAW_STATUS_REG5 */ "", 47965 /* INTC_INTR_RAW_STATUS_REG6 */ "", 47966 /* INTC_INTR_RAW_STATUS_REG7 */ "", 47967 /* INTC_INTR_STATUS_REG0 */ "", 47968 /* INTC_INTR_STATUS_REG1 */ "", 47969 /* INTC_INTR_STATUS_REG2 */ "", 47970 /* INTC_INTR_STATUS_REG3 */ "", 47971 /* INTC_INTR_STATUS_REG4 */ "", 47972 /* INTC_INTR_STATUS_REG5 */ "", 47973 /* INTC_INTR_STATUS_REG6 */ "", 47974 /* INTC_INTR_STATUS_REG7 */ "", 47975 /* INTC_REMAP_BITPOS_REG0 */ "", 47976 /* INTC_REMAP_BITPOS_REG1 */ "", 47977 /* INTC_REMAP_BITPOS_REG2 */ "", 47978 /* INTC_REMAP_BITPOS_REG3 */ "", 47979 /* INTC_REMAP_BITPOS_REG4 */ "", 47980 /* INTC_REMAP_BITPOS_REG5 */ "", 47981 /* INTC_REMAP_BITPOS_REG6 */ "", 47982 /* INTC_REMAP_BITPOS_REG7 */ "", 47983 /* INTC_REMAP_BITPOS_REG8 */ "", 47984 /* INTC_REMAP_BITPOS_REG9 */ "", 47985 /* INTC_REMAP_BITPOS_REG10 */ "", 47986 /* INTC_REMAP_BITPOS_REG11 */ "", 47987 /* INTC_REMAP_BITPOS_REG12 */ "", 47988 /* INTC_REMAP_BITPOS_REG13 */ "", 47989 /* INTC_REMAP_BITPOS_REG14 */ "", 47990 /* INTC_REMAP_BITPOS_REG15 */ "", 47991 /* INTC_REMAP_BITPOS_REG16 */ "", 47992 /* INTC_REMAP_BITPOS_REG17 */ "", 47993 /* INTC_REMAP_BITPOS_REG18 */ "", 47994 /* INTC_REMAP_BITPOS_REG19 */ "", 47995 /* INTC_REMAP_BITPOS_REG20 */ "", 47996 /* INTC_REMAP_BITPOS_REG21 */ "", 47997 /* INTC_REMAP_BITPOS_REG22 */ "", 47998 /* INTC_REMAP_BITPOS_REG23 */ "", 47999 /* INTC_REMAP_BITPOS_REG24 */ "", 48000 /* INTC_REMAP_BITPOS_REG25 */ "", 48001 /* INTC_REMAP_BITPOS_REG26 */ "", 48002 /* INTC_REMAP_BITPOS_REG27 */ "", 48003 /* INTC_REMAP_BITPOS_REG28 */ "", 48004 /* INTC_REMAP_BITPOS_REG29 */ "", 48005 /* INTC_REMAP_BITPOS_REG30 */ "", 48006 /* INTC_REMAP_BITPOS_REG31 */ "", 48007 /* INTC_REMAP_BITPOS_REG32 */ "", 48008 /* INTC_REMAP_BITPOS_REG33 */ "", 48009 /* INTC_REMAP_BITPOS_REG34 */ "", 48010 /* INTC_REMAP_BITPOS_REG35 */ "", 48011 /* INTC_REMAP_BITPOS_REG36 */ "", 48012 /* INTC_REMAP_BITPOS_REG37 */ "", 48013 /* INTC_REMAP_BITPOS_REG38 */ "", 48014 /* INTC_REMAP_BITPOS_REG39 */ "", 48015 /* INTC_REMAP_BITPOS_REG40 */ "", 48016 /* INTC_REMAP_BITPOS_REG41 */ "", 48017 /* INTC_REMAP_BITPOS_REG42 */ "", 48018 /* INTC_REMAP_BITPOS_REG43 */ "", 48019 /* INTC_REMAP_BITPOS_REG44 */ "", 48020 /* INTC_REMAP_BITPOS_REG45 */ "", 48021 /* INTC_REMAP_BITPOS_REG46 */ "", 48022 /* INTC_REMAP_BITPOS_REG47 */ "", 48023 /* INTC_REMAP_BITPOS_REG48 */ "", 48024 /* INTC_REMAP_BITPOS_REG49 */ "", 48025 /* INTC_REMAP_BITPOS_REG50 */ "", 48026 /* INTC_REMAP_BITPOS_REG51 */ "", 48027 /* INTFI_CFG */ "", 48028 /* INTFI_DEBUG */ "", 48029 /* INTFI_DEBUG_FIFO_WR_POINTER */ "", 48030 /* INTFI_ECC_1B_COUNTER */ "", 48031 /* INTFI_ECC_2B_COUNTER */ "", 48032 /* INTFI_ECC_CONTROL */ "", 48033 /* INTFI_ECC_DEBUG */ "", 48034 /* INTFI_ECC_ERROR */ "", 48035 /* INTFI_ECC_INTR_MASK */ "", 48036 /* INTFI_ECC_STATUS */ "", 48037 /* INTFI_EN_COR_ERR_RPT */ "", 48038 /* INTFI_ERROR_MASK */ "", 48039 /* INTFI_ERROR_STATUS */ "", 48040 /* INTFI_HCFC_DEBUG */ "", 48041 /* INTFI_MAP_L0_TBL_ADDR */ "", 48042 /* INTFI_MAP_L1_TBL_ADDR */ "", 48043 /* INTFI_MAP_L2_TBL_ADDR */ "", 48044 /* INTFI_MAP_S1_TBL_ADDR */ "", 48045 /* INTFI_MAP_TBL_ADDR */ "", 48046 /* INTFI_MEMDEBUG */ "", 48047 /* INTFI_MEMORY_TM */ "", 48048 /* INTFI_OOBFC_MSG_RX_FAILED_CNT */ "", 48049 /* INTFI_OOB_HCFC_BAD_RXD_COUNT */ "", 48050 /* INTFI_OOB_HCFC_CAPTURE0 */ "", 48051 /* INTFI_OOB_HCFC_CAPTURE1 */ "", 48052 /* INTFI_OOB_HCFC_CAPTURE2 */ "", 48053 /* INTFI_OOB_HCFC_CAPTURE3 */ "", 48054 /* INTFI_OOB_HCFC_GOOD_RXD_COUNT */ "", 48055 /* INTFI_PORT_CFG */ "", 48056 /* INTFO_CONGST_ST */ "", 48057 /* INTFO_E2ECC_MERGE_MCQ_POOL */ "", 48058 /* INTFO_E2ECC_MERGE_RQE_POOL */ "", 48059 /* INTFO_E2ECC_POOL_STATE_REPORT_ENABLE */ "", 48060 /* INTFO_EN_COR_ERR_RPT */ "", 48061 /* INTFO_FCN_EN */ "", 48062 /* INTFO_HW_UPDATE_DIS */ "", 48063 /* INTFO_MEMDEBUG_CHFC_TC2PRI_TBL */ "", 48064 /* INTFO_MEM_TM */ "", 48065 /* INTFO_MERGE_MCQ_POOL */ "", 48066 /* INTFO_MERGE_RQE_POOL */ "", 48067 /* INTFO_OOBFC_MSG_RX_FAILED_CNT */ "", 48068 /* INTFO_OOBFC_MSG_RX_FAILED_CNT0 */ "", 48069 /* INTFO_OOBFC_MSG_RX_FAILED_CNT1 */ "", 48070 /* INTFO_OOBFC_MSG_RX_FAILED_CNT2 */ "", 48071 /* INTFO_OOBFC_MSG_RX_FAILED_CNT3 */ "", 48072 /* INTFO_QCN_SRAM_TM */ "", 48073 /* INTFO_STAT_MSG_FF_STATUS */ "", 48074 /* INTFO_STAT_QS_CMD_FF_STATUS */ "", 48075 /* INTFO_STAT_QS_RX_FF_STATUS */ "", 48076 /* INTFO_STAT_QS_RX_RA_FF_STATUS */ "", 48077 /* INTFO_STAT_QS_RX_RB_FF_STATUS */ "", 48078 /* INTFO_STAT_QS_RX_R_FF_STATUS */ "", 48079 /* INTFO_STAT_QS_RX_SA_FF_STATUS */ "", 48080 /* INTFO_STAT_QS_RX_SB_FF_STATUS */ "", 48081 /* INTFO_STAT_QS_RX_S_FF_STATUS */ "", 48082 /* INTFO_STAT_SP_CMD_FF_STATUS */ "", 48083 /* INTFO_STAT_THDI_SP_RX_FF_STATUS */ "", 48084 /* INTFO_STAT_THDI_SP_RX_RA_FF_STATUS */ "", 48085 /* INTFO_STAT_THDI_SP_RX_RB_FF_STATUS */ "", 48086 /* INTFO_STAT_THDI_SP_RX_SA_FF_STATUS */ "", 48087 /* INTFO_STAT_THDI_SP_RX_SB_FF_STATUS */ "", 48088 /* INTFO_STAT_THDM_SP_RX_FF_STATUS */ "", 48089 /* INTFO_STAT_THDM_SP_RX_RA_FF_STATUS */ "", 48090 /* INTFO_STAT_THDM_SP_RX_RB_FF_STATUS */ "", 48091 /* INTFO_STAT_THDM_SP_RX_SA_FF_STATUS */ "", 48092 /* INTFO_STAT_THDM_SP_RX_SB_FF_STATUS */ "", 48093 /* INT_CONTROL */ "", 48094 /* INT_CONTROL_1 */ "", 48095 /* INT_DETECT_CONFIG_0 */ "", 48096 /* INT_DETECT_CONFIG_1 */ "", 48097 /* INT_DETECT_CONFIG_2 */ "", 48098 /* INT_PARSE_CONTROL */ "", 48099 /* INT_PROCESS_CONFIG */ "", 48100 /* INT_REQUEST_VECTOR_CONFIG */ "", 48101 /* IOAM_CONTROL */ "", 48102 /* IP0_BISR */ "", 48103 /* IP0_BISR_REG */ "", 48104 /* IP0_EP_BISR_RD_DATA */ "", 48105 /* IP0_INTR_ENABLE */ "", 48106 /* IP0_INTR_ENABLE_PIPE0 */ "", 48107 /* IP0_INTR_ENABLE_PIPE1 */ "", 48108 /* IP0_INTR_ENABLE_PIPE2 */ "", 48109 /* IP0_INTR_ENABLE_PIPE3 */ "", 48110 /* IP0_INTR_STATUS */ "", 48111 /* IP0_INTR_STATUS_PIPE0 */ "", 48112 /* IP0_INTR_STATUS_PIPE1 */ "", 48113 /* IP0_INTR_STATUS_PIPE2 */ "", 48114 /* IP0_INTR_STATUS_PIPE3 */ "", 48115 /* IP0_INTR_STATUS_PIPE4 */ "", 48116 /* IP0_INTR_STATUS_PIPE5 */ "", 48117 /* IP0_INTR_STATUS_PIPE6 */ "", 48118 /* IP0_INTR_STATUS_PIPE7 */ "", 48119 /* IP1_BISR */ "", 48120 /* IP1_BISR_RD_DATA */ "", 48121 /* IP1_BISR_REG */ "", 48122 /* IP1_INTR_ENABLE */ "", 48123 /* IP1_INTR_ENABLE_1 */ "", 48124 /* IP1_INTR_STATUS */ "", 48125 /* IP1_INTR_STATUS_1 */ "", 48126 /* IP1_PARITY_INTR_STATUS */ "", 48127 /* IP2_BISR */ "", 48128 /* IP2_BISR_RD_DATA */ "", 48129 /* IP2_BISR_REG */ "", 48130 /* IP2_INTR_ENABLE */ "", 48131 /* IP2_INTR_ENABLE_1 */ "", 48132 /* IP2_INTR_ENABLE_2 */ "", 48133 /* IP2_INTR_STATUS */ "", 48134 /* IP2_INTR_STATUS_1 */ "", 48135 /* IP2_INTR_STATUS_2 */ "", 48136 /* IP2_PARITY_INTR_STATUS */ "", 48137 /* IP2_SR_INTR_ENABLE */ "", 48138 /* IP2_SR_INTR_STATUS */ "", 48139 /* IP2_SR_SN_INTR_ENABLE */ "", 48140 /* IP2_SR_SN_INTR_STATUS */ "", 48141 /* IP2_SR_TH_INTR_STATUS */ "", 48142 /* IP3_BISR */ "", 48143 /* IP3_BISR_REG */ "", 48144 /* IP3_INTR_ENABLE */ "", 48145 /* IP3_INTR_ENABLE_1 */ "", 48146 /* IP3_INTR_ENABLE_2 */ "", 48147 /* IP3_INTR_STATUS */ "", 48148 /* IP3_INTR_STATUS_1 */ "", 48149 /* IP3_INTR_STATUS_2 */ "", 48150 /* IP3_PARITY_INTR_STATUS */ "", 48151 /* IP4FD */ "", 48152 /* IP4_BISR_REG */ "", 48153 /* IP4_INTR_ENABLE */ "", 48154 /* IP4_INTR_STATUS */ "", 48155 /* IP4_PARITY_STATUS */ "", 48156 /* IP5_INTR_ENABLE */ "", 48157 /* IP5_INTR_ENABLE_1 */ "", 48158 /* IP5_INTR_ENABLE_2 */ "", 48159 /* IP5_INTR_STATUS */ "", 48160 /* IP5_INTR_STATUS_1 */ "", 48161 /* IP5_INTR_STATUS_2 */ "", 48162 /* IP6FD */ "", 48163 /* IP7_INTR_ENABLE */ "", 48164 /* IP7_INTR_STATUS */ "", 48165 /* IP7_INTR_STATUS_PIPE0 */ "", 48166 /* IP7_INTR_STATUS_PIPE1 */ "", 48167 /* IP7_INTR_STATUS_PIPE2 */ "", 48168 /* IP7_INTR_STATUS_PIPE3 */ "", 48169 /* IPARS1_EN_COR_ERR_RPT */ "", 48170 /* IPARS1_RAM_DBGCTRL_1 */ "IPARS1_RAM_CONTROL1", 48171 /* IPARS1_RAM_DBGCTRL_1_PIPE0 */ "IPARS1_RAM_CONTROL1_PIPE0", 48172 /* IPARS1_RAM_DBGCTRL_1_PIPE1 */ "IPARS1_RAM_CONTROL1_PIPE1", 48173 /* IPARS1_SER_CONTROL */ "", 48174 /* IPARS2_EN_COR_ERR_RPT */ "", 48175 /* IPARS2_RAM_DBGCTRL */ "IPARS2_RAM_CONTROL0", 48176 /* IPARS2_RAM_DBGCTRL_PIPE0 */ "IPARS2_RAM_CONTROL0_PIPE0", 48177 /* IPARS2_RAM_DBGCTRL_PIPE1 */ "IPARS2_RAM_CONTROL0_PIPE1", 48178 /* IPARS2_SER_CONTROL */ "", 48179 /* IPARS_BUS_PARITY_DEBUG */ "", 48180 /* IPARS_CLK_GATING_CONTROL */ "", 48181 /* IPARS_DBGCTRL */ "IPARS_ECC_DEBUG", 48182 /* IPARS_DEBUG */ "", 48183 /* IPARS_ECC_ERROR */ "", 48184 /* IPARS_ECC_ERROR_MASK */ "", 48185 /* IPARS_ECC_STATUS */ "", 48186 /* IPARS_EN_COR_ERR_RPT */ "", 48187 /* IPARS_HW_CONTROL */ "", 48188 /* IPARS_MEM_INIT */ "", 48189 /* IPARS_PACKET_BUFFER_CONTROL_INFO */ "", 48190 /* IPARS_PARITY_ERROR */ "", 48191 /* IPARS_PARITY_ERROR_MASK */ "", 48192 /* IPARS_REGS_DEBUG */ "", 48193 /* IPARS_SER_CONTROL */ "", 48194 /* IPARS_STM_ECC */ "", 48195 /* IPARS_TM_REG_1 */ "", 48196 /* IPEP_OTP_IN_64 */ "", 48197 /* IPEP_TEMPLATE_ECC_CONTROL */ "", 48198 /* IPEP_TEMPLATE_PARITY_CONTROL */ "", 48199 /* IPFIX_AGE_CONTROL */ "ING_IPFIX_AGE_CONTROL", 48200 /* IPFIX_RAM_CONTROL */ "", 48201 /* IPG_HD_BKP_CNTL */ "", 48202 /* IPIPE_PERR_CONTROL */ "IPIPE_PERR_CONTROL", 48203 /* IPMCGROUPMEMDEBUG */ "", 48204 /* IPMCGROUPTBLMEMDEBUG */ "", 48205 /* IPMCGRPMEMDEBUG */ "", 48206 /* IPMCIDXINCACONFIG */ "", 48207 /* IPMCIDXINCAEN */ "", 48208 /* IPMCIDXINCAEN_64 */ "IPMCIDXINCAEN", 48209 /* IPMCIDXINCBCONFIG */ "", 48210 /* IPMCIDXINCBEN */ "", 48211 /* IPMCIDXINCBEN_64 */ "IPMCIDXINCBEN", 48212 /* IPMCIDXINCCCONFIG */ "", 48213 /* IPMCIDXINCCEN */ "", 48214 /* IPMCIDXINCCEN_64 */ "IPMCIDXINCCEN", 48215 /* IPMCIDXINCCONFIG */ "", 48216 /* IPMCINTFTBLMEMDEBUG */ "", 48217 /* IPMCPARITYERRORPTR */ "", 48218 /* IPMCREPLICATIONCFG */ "", 48219 /* IPMCREPLICATIONCFG0 */ "", 48220 /* IPMCREPLICATIONCFG1 */ "", 48221 /* IPMCREPLICATIONCOUNT */ "", 48222 /* IPMCREPLICATIONCOUNT0 */ "", 48223 /* IPMCREPLICATIONCOUNT1 */ "", 48224 /* IPMCREPOVERLMTPBM */ "", 48225 /* IPMCREP_SRCHFAIL */ "", 48226 /* IPMCREP_SRCHFAIL_64 */ "IPMCREP_SRCHFAIL", 48227 /* IPMCVLANMEMDEBUG */ "", 48228 /* IPMC_GROUP_ERR_CLR */ "", 48229 /* IPMC_GROUP_ERR_CLR_0 */ "", 48230 /* IPMC_GROUP_ERR_CLR_1 */ "", 48231 /* IPMC_GROUP_ERR_CLR_2 */ "", 48232 /* IPMC_GROUP_ERR_PTR */ "", 48233 /* IPMC_GROUP_ERR_VLD */ "", 48234 /* IPMC_GROUP_ERR_VLD_0 */ "", 48235 /* IPMC_GROUP_ERR_VLD_1 */ "", 48236 /* IPMC_GROUP_ERR_VLD_2 */ "", 48237 /* IPMC_GROUP_MULTI_ERR */ "", 48238 /* IPMC_GROUP_MULTI_ERR_0 */ "", 48239 /* IPMC_GROUP_MULTI_ERR_1 */ "", 48240 /* IPMC_GROUP_MULTI_ERR_2 */ "", 48241 /* IPMC_L2_MTU */ "", 48242 /* IPMC_L2_MTU_0 */ "", 48243 /* IPMC_L2_MTU_1 */ "", 48244 /* IPMC_L2_MTU_2 */ "", 48245 /* IPMC_L2_MTU_3 */ "", 48246 /* IPMC_L2_MTU_4 */ "", 48247 /* IPMC_L2_MTU_5 */ "", 48248 /* IPMC_L2_MTU_6 */ "", 48249 /* IPMC_L2_MTU_7 */ "", 48250 /* IPMC_L3_MTU */ "", 48251 /* IPMC_L3_MTU_0 */ "", 48252 /* IPMC_L3_MTU_1 */ "", 48253 /* IPMC_L3_MTU_2 */ "", 48254 /* IPMC_L3_MTU_3 */ "", 48255 /* IPMC_L3_MTU_4 */ "", 48256 /* IPMC_L3_MTU_5 */ "", 48257 /* IPMC_L3_MTU_6 */ "", 48258 /* IPMC_L3_MTU_7 */ "", 48259 /* IPMC_MEMORY_DEBUG_TM */ "", 48260 /* IPMC_MTU_CONFIG */ "", 48261 /* IPOST_INTR_ENABLE */ "", 48262 /* IPOST_INTR_STATUS */ "", 48263 /* IPOST_INTR_STATUS_PIPE0 */ "", 48264 /* IPOST_INTR_STATUS_PIPE1 */ "", 48265 /* IPOST_INTR_STATUS_PIPE2 */ "", 48266 /* IPOST_INTR_STATUS_PIPE3 */ "", 48267 /* IPOST_INTR_STATUS_PIPE4 */ "", 48268 /* IPOST_INTR_STATUS_PIPE5 */ "", 48269 /* IPOST_INTR_STATUS_PIPE6 */ "", 48270 /* IPOST_INTR_STATUS_PIPE7 */ "", 48271 /* IPOST_RAM_CONTROL */ "", 48272 /* IPOST_RAM_CONTROL_PIPE0 */ "", 48273 /* IPOST_RAM_CONTROL_PIPE1 */ "", 48274 /* IPOST_RAM_CONTROL_PIPE2 */ "", 48275 /* IPOST_RAM_CONTROL_PIPE3 */ "", 48276 /* IPOST_RAM_CONTROL_PIPE4 */ "", 48277 /* IPOST_RAM_CONTROL_PIPE5 */ "", 48278 /* IPOST_RAM_CONTROL_PIPE6 */ "", 48279 /* IPOST_RAM_CONTROL_PIPE7 */ "", 48280 /* IPOST_SER_CONTROL */ "", 48281 /* IPPA_CFG_MAP_CTX_TO_LIF_LOOKUP_ENABLE */ "", 48282 /* IPPA_CFG_PROTOCOL_IS_ETH */ "", 48283 /* IPPA_CFG_PROTOCOL_IS_IPV4 */ "", 48284 /* IPPA_CFG_PROTOCOL_IS_IPV6 */ "", 48285 /* IPPA_CFG_PROTOCOL_IS_MAC_IN_MAC */ "", 48286 /* IPPA_CFG_PROTOCOL_IS_MPLS */ "", 48287 /* IPPA_CONTEXT_SELECTION_HIGH_PTC_MAPPING */ "", 48288 /* IPPA_CONTEXT_SELECTION_LOW_PTC_MAPPING */ "", 48289 /* IPPA_CS_INLIF_PROFILE_MAP_LSB */ "", 48290 /* IPPA_CS_INLIF_PROFILE_MAP_MSB */ "", 48291 /* IPPA_ECC_1B_ERR_CNT */ "", 48292 /* IPPA_ECC_2B_ERR_CNT */ "", 48293 /* IPPA_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 48294 /* IPPA_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 48295 /* IPPA_ECC_INTERRUPT_REGISTER */ "", 48296 /* IPPA_ECC_INTERRUPT_REGISTER_MASK */ "", 48297 /* IPPA_ECC_INTERRUPT_REGISTER_TEST */ "", 48298 /* IPPA_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 48299 /* IPPA_ERROR_INITIATION_DATA */ "", 48300 /* IPPA_ETHERNET_TRAP */ "", 48301 /* IPPA_ETHERNET_TRAP_ACTION_PROFILE_VECTOR */ "", 48302 /* IPPA_ETH_PCP_TO_OAM_PCP */ "", 48303 /* IPPA_EXTEND_VCP_ENABLE */ "", 48304 /* IPPA_FWD_DOMAIN_MASKS */ "", 48305 /* IPPA_FWD_DOMAIN_MASK_PROFILE_MAP */ "", 48306 /* IPPA_GTIMER_CONFIGURATION */ "", 48307 /* IPPA_GTIMER_CYCLE */ "", 48308 /* IPPA_HIGH_PTC_MAPPING */ "", 48309 /* IPPA_INDIRECT_COMMAND */ "", 48310 /* IPPA_INDIRECT_COMMAND_ADDRESS */ "", 48311 /* IPPA_INDIRECT_COMMAND_RD_DATA */ "", 48312 /* IPPA_INDIRECT_COMMAND_WIDE_MEM */ "", 48313 /* IPPA_INDIRECT_COMMAND_WR_DATA */ "", 48314 /* IPPA_INDIRECT_FORCE_BUBBLE */ "", 48315 /* IPPA_INDIRECT_WR_MASK */ "", 48316 /* IPPA_INITIAL_PCP_DEI_MAP_TYPE */ "", 48317 /* IPPA_INTERRUPT_MASK_REGISTER */ "", 48318 /* IPPA_INTERRUPT_REGISTER */ "", 48319 /* IPPA_INTERRUPT_REGISTER_TEST */ "", 48320 /* IPPA_IP_STAGE_SEL */ "", 48321 /* IPPA_IP_TOS_TO_OAM_PCP_0 */ "", 48322 /* IPPA_IP_TOS_TO_OAM_PCP_1 */ "", 48323 /* IPPA_LEARN_KEY_CONTEXT */ "", 48324 /* IPPA_LIF_TRAPS */ "", 48325 /* IPPA_LOW_PTC_MAPPING */ "", 48326 /* IPPA_MAC_IN_MAC_VSI */ "", 48327 /* IPPA_MAP_PARSER_CTX_TO_PROTOCOL */ "", 48328 /* IPPA_MAP_PORT_TO_LEARN_LIF_VEC */ "", 48329 /* IPPA_MAP_VRID_TO_IP_VERSION */ "", 48330 /* IPPA_MEF_L_2_CP_TRANSPARENT_BITMAP */ "", 48331 /* IPPA_MPLS_EXP_TO_OAM_PCP */ "", 48332 /* IPPA_MPLS_LABEL_PROCEDURE_CONFIG */ "", 48333 /* IPPA_MPLS_SPECIAL_LABEL_ATTRIBUTES */ "", 48334 /* IPPA_MY_B_MAC_LSB_BITMAP */ "", 48335 /* IPPA_MY_B_MAC_MC */ "", 48336 /* IPPA_MY_B_MAC_MSB */ "", 48337 /* IPPA_PARITY_ERR_CNT */ "", 48338 /* IPPA_PAR_ERR_MEM_MASK */ "", 48339 /* IPPA_PCMI_0 */ "", 48340 /* IPPA_PCMI_1 */ "", 48341 /* IPPA_PCMI_2 */ "", 48342 /* IPPA_PCMI_3 */ "", 48343 /* IPPA_PCMI_4 */ "", 48344 /* IPPA_PCMI_0_S */ "", 48345 /* IPPA_PCMI_0_T */ "", 48346 /* IPPA_PCMI_1_S */ "", 48347 /* IPPA_PCMI_1_T */ "", 48348 /* IPPA_PCMI_2_S */ "", 48349 /* IPPA_PCMI_2_T */ "", 48350 /* IPPA_PCMI_3_S */ "", 48351 /* IPPA_PCMI_3_T */ "", 48352 /* IPPA_PCMI_4_S */ "", 48353 /* IPPA_PCMI_4_T */ "", 48354 /* IPPA_REG_100 */ "", 48355 /* IPPA_REG_0420 */ "", 48356 /* IPPA_REG_0421 */ "", 48357 /* IPPA_REG_0905 */ "", 48358 /* IPPA_REG_0908 */ "", 48359 /* IPPA_REG_0955 */ "", 48360 /* IPPA_REG_0958 */ "", 48361 /* IPPA_REG_00A4 */ "", 48362 /* IPPA_REG_00A6 */ "", 48363 /* IPPA_REG_00AA */ "", 48364 /* IPPA_REG_00C2 */ "", 48365 /* IPPA_REG_090A */ "", 48366 /* IPPA_REG_095A */ "", 48367 /* IPPA_RESERVED_MIRROR_ADDR */ "", 48368 /* IPPA_RESERVED_MTCD */ "", 48369 /* IPPA_RESERVED_MTCP */ "", 48370 /* IPPA_RESERVED_SPARE_0 */ "", 48371 /* IPPA_RESERVED_SPARE_1 */ "", 48372 /* IPPA_RESERVED_SPARE_2 */ "", 48373 /* IPPA_RESERVED_SPARE_3 */ "", 48374 /* IPPA_SBUS_BROADCAST_ID */ "", 48375 /* IPPA_SBUS_LAST_IN_CHAIN */ "", 48376 /* IPPA_SECOND_STAGE_PARSING_SELECT */ "", 48377 /* IPPA_STATISTICS_INFO */ "", 48378 /* IPPA_STAT_OBJ_PROFILE_ATTR */ "", 48379 /* IPPA_VTB_ETHERNET_PROC_STAGE_SEL */ "", 48380 /* IPPA_VTDCS_TCAM_ECC_FIX_EN */ "", 48381 /* IPPA_VTDCS_TCAM_PROTECTION_ERROR */ "", 48382 /* IPPA_VTDCS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48383 /* IPPA_VTDCS_TCAM_RESET_BLOCK */ "", 48384 /* IPPA_VTECS_TCAM_ECC_FIX_EN */ "", 48385 /* IPPA_VTECS_TCAM_PROTECTION_ERROR */ "", 48386 /* IPPA_VTECS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48387 /* IPPA_VTECS_TCAM_RESET_BLOCK */ "", 48388 /* IPPA_VTT_ACTION_PROFILE_ACCEPTABLE_FRAME_TYPES */ "", 48389 /* IPPA_VTT_ETHERNET_TERMINATION_ACTION */ "", 48390 /* IPPA_VTT_GENERAL_CONFIGS_0 */ "", 48391 /* IPPA_VTT_MPLS_LABEL_RANGE_PROFILE */ "", 48392 /* IPPA_VTT_MPLS_PREPROCESSING_BOS_OR_TTL_TRAP */ "", 48393 /* IPPA_VTT_MY_MAC_VRID_VMV_SHIFT_VALUE */ "", 48394 /* IPPA_VTT_QOS_PROPAG_PROFILE_MAPPING */ "", 48395 /* IPPA_VTT_SPECIAL_LABELS_PROFILE */ "", 48396 /* IPPA_VTT_SPECIAL_LABEL_VALUES */ "", 48397 /* IPPA_VTT_ST_TH_LE_CONFIG */ "", 48398 /* IPPA_VTT_ST_TH_LE_CONTROL_FIFO_CFG */ "", 48399 /* IPPA_VTT_ST_TH_LE_LATENCY_COMPENSATION_FIFO_CFG */ "", 48400 /* IPPA_VTT_ST_TH_LE_VMV_SHIFT_VALUE_MAP */ "", 48401 /* IPPA_VTT_TRAP_STRENGTHS_0 */ "", 48402 /* IPPA_VTT_TRAP_STRENGTHS_1 */ "", 48403 /* IPPA_VTT_TRAP_STRENGTHS_2 */ "", 48404 /* IPPA_VTT_TRAP_STRENGTHS_3 */ "", 48405 /* IPPA_VTT_TRAP_STRENGTHS_4 */ "", 48406 /* IPPA_VTT_TRAP_STRENGTHS_5 */ "", 48407 /* IPPA_VTT_TRAP_STRENGTHS_6 */ "", 48408 /* IPPA_VTT_TRAP_STRENGTHS_7 */ "", 48409 /* IPPA_VTT_TRAP_STRENGTHS_8 */ "", 48410 /* IPPB_ACTION_PROFILE_IEEE_1588 */ "", 48411 /* IPPB_ACTION_PROFILE_SA_DROP_MAP */ "", 48412 /* IPPB_ACTION_PROFILE_SA_NOT_FOUND_MAP */ "", 48413 /* IPPB_ALL_ESADI_RBRIDGES */ "", 48414 /* IPPB_APP_DB_INDEX_MAP */ "", 48415 /* IPPB_ARP_TRAP_CFG */ "", 48416 /* IPPB_CS_INLIF_PROFILE_MAP_0 */ "", 48417 /* IPPB_CS_INLIF_PROFILE_MAP_1 */ "", 48418 /* IPPB_CURRENT_LAYER_STATISTICS_META_DATA_INFORMATION_MAP */ "", 48419 /* IPPB_CURRENT_LAYER_STATISTICS_META_DATA_INSTRUCTION_MAP */ "", 48420 /* IPPB_DBG_FLP_DATA_PATH_TRAP */ "", 48421 /* IPPB_DBG_FLP_LPM */ "", 48422 /* IPPB_DBG_FLP_PACKETS_REJECTED_BY_EGW_CNT */ "", 48423 /* IPPB_DBG_IEEE_1588_IDENTIFICATION_CAM_LINE */ "", 48424 /* IPPB_DSCP_REMARK_INHERITANCE_RESOLUTION_MPLS_CFG */ "", 48425 /* IPPB_DSCP_REMARK_PORT_CFG */ "", 48426 /* IPPB_ECC_1B_ERR_CNT */ "", 48427 /* IPPB_ECC_2B_ERR_CNT */ "", 48428 /* IPPB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 48429 /* IPPB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 48430 /* IPPB_ECC_INTERRUPT_REGISTER */ "", 48431 /* IPPB_ECC_INTERRUPT_REGISTER_MASK */ "", 48432 /* IPPB_ECC_INTERRUPT_REGISTER_TEST */ "", 48433 /* IPPB_ECN_PORT_CFG */ "", 48434 /* IPPB_EGRESS_OPPORTUNISTIC_FIFO_PROPERTIES */ "", 48435 /* IPPB_EGW_ENABLE_OPCODE_ERROR_HANDLING */ "", 48436 /* IPPB_EGW_OPCODE_ERROR_DROP_COUNTER */ "", 48437 /* IPPB_ELK_ERROR_TRAP_ACTION_PROFILE */ "", 48438 /* IPPB_ELK_FWD_RESULT_SIZE_MAP */ "", 48439 /* IPPB_ELK_KAPS_ACL_CFG */ "", 48440 /* IPPB_ELK_RESULT_TYPE */ "", 48441 /* IPPB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 48442 /* IPPB_ENABLE_KAPS_INTERFACE_DEFAULT */ "", 48443 /* IPPB_ERROR_INITIATION_DATA */ "", 48444 /* IPPB_ETHERNET_TRAPS_ACTION_PROFILES_CFG */ "", 48445 /* IPPB_EXEM_SELECTOR */ "", 48446 /* IPPB_FC_ACTION_PROFILES */ "", 48447 /* IPPB_FLPACS_TCAM_ECC_FIX_EN */ "", 48448 /* IPPB_FLPACS_TCAM_PROTECTION_ERROR */ "", 48449 /* IPPB_FLPACS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48450 /* IPPB_FLPACS_TCAM_RESET_BLOCK */ "", 48451 /* IPPB_FLPBCS_TCAM_ECC_FIX_EN */ "", 48452 /* IPPB_FLPBCS_TCAM_PROTECTION_ERROR */ "", 48453 /* IPPB_FLPBCS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48454 /* IPPB_FLPBCS_TCAM_RESET_BLOCK */ "", 48455 /* IPPB_FLPLE_CONFIG */ "", 48456 /* IPPB_FLPLE_CONTROL_FIFO_0_DEBUG_CFG */ "", 48457 /* IPPB_FLPLE_CONTROL_FIFO_1_DEBUG_CFG */ "", 48458 /* IPPB_FLPLE_DE_FIFO_DEBUG_CFG */ "", 48459 /* IPPB_FLPLE_ELK_FIFO_DEBUG_CFG */ "", 48460 /* IPPB_FLPLE_LATENCY_COMPENSATION_FIFO_DEBUG_CFG */ "", 48461 /* IPPB_FLPLE_VMV_SHIFT_VALUE_MAP */ "", 48462 /* IPPB_FLP_EGW_CREDIT_THRESHOLD */ "", 48463 /* IPPB_FLP_GENERAL_CFG */ "", 48464 /* IPPB_FLP_L_4_TRAP_TCP_EQUAL_PORTS */ "", 48465 /* IPPB_FLP_L_4_TRAP_TCP_FRAGMENT_INCOMPLETE_HEADER */ "", 48466 /* IPPB_FLP_L_4_TRAP_TCP_FRAGMENT_OFFSET_LARGER_THAN_8 */ "", 48467 /* IPPB_FLP_L_4_TRAP_TCP_SN_FLAGS_ZERO */ "", 48468 /* IPPB_FLP_L_4_TRAP_TCP_SN_ZERO_FLAGS */ "", 48469 /* IPPB_FLP_L_4_TRAP_TCP_SYN_FIN */ "", 48470 /* IPPB_FLP_L_4_TRAP_UDP_EQUAL_PORTS */ "", 48471 /* IPPB_FLP_VLAN_EDIT_PCP_DEI_MAP_CFG */ "", 48472 /* IPPB_GENERAL_CONFIG */ "", 48473 /* IPPB_GTIMER_CONFIGURATION */ "", 48474 /* IPPB_GTIMER_CYCLE */ "", 48475 /* IPPB_ICMP_NDP_NEIGHBOR_SOLICITATION_TYPE */ "", 48476 /* IPPB_ICMP_TRAP_CFG */ "", 48477 /* IPPB_IDENTIFICATION_APPDB */ "", 48478 /* IPPB_INDIRECT_COMMAND */ "", 48479 /* IPPB_INDIRECT_COMMAND_ADDRESS */ "", 48480 /* IPPB_INDIRECT_COMMAND_RD_DATA */ "", 48481 /* IPPB_INDIRECT_COMMAND_WIDE_MEM */ "", 48482 /* IPPB_INDIRECT_COMMAND_WR_DATA */ "", 48483 /* IPPB_INDIRECT_FORCE_BUBBLE */ "", 48484 /* IPPB_INDIRECT_WR_MASK */ "", 48485 /* IPPB_INGRESS_TRAP_PROFILE_SELECTOR_CFG */ "", 48486 /* IPPB_INTERRUPT_MASK_REGISTER */ "", 48487 /* IPPB_INTERRUPT_REGISTER */ "", 48488 /* IPPB_INTERRUPT_REGISTER_TEST */ "", 48489 /* IPPB_IPV4_ACTION_PROFILES_CFG */ "", 48490 /* IPPB_IPV6_ACTION_PROFILES_0_CFG */ "", 48491 /* IPPB_IPV6_ACTION_PROFILES_1_CFG */ "", 48492 /* IPPB_IS_8021_X_2_VAL */ "", 48493 /* IPPB_IS_ARP_VAL */ "", 48494 /* IPPB_IS_ETHERNET_VAL */ "", 48495 /* IPPB_IS_ICMPV6_VAL */ "", 48496 /* IPPB_IS_ICMP_VAL */ "", 48497 /* IPPB_IS_IGMP_VAL */ "", 48498 /* IPPB_IS_IPV4_VAL */ "", 48499 /* IPPB_IS_IPV6_VAL */ "", 48500 /* IPPB_IS_LARGE_EM */ "", 48501 /* IPPB_IS_LAYER_PROTOCOL_BFD_M_HOP_VAL */ "", 48502 /* IPPB_IS_LAYER_PROTOCOL_BFD_ONE_HOP_VAL */ "", 48503 /* IPPB_IS_MPLS_VAL */ "", 48504 /* IPPB_IS_UDP_VAL */ "", 48505 /* IPPB_LARGE_EM_LEARN_FILTER_PROPERTIES */ "", 48506 /* IPPB_LAYER_PLUS_ONE_STATISTICS_META_DATA_INFORMATION_MAP */ "", 48507 /* IPPB_LAYER_PLUS_ONE_STATISTICS_META_DATA_INSTRUCTION_MAP */ "", 48508 /* IPPB_LB_CLIENTS_CRC_32_BITS_SELECTION_BITMAP */ "", 48509 /* IPPB_LEARNING_CFG */ "", 48510 /* IPPB_LEL_BURST_FIFO_PROPERTIES */ "", 48511 /* IPPB_LEL_CONTROL_FIFO_PROPERTIES */ "", 48512 /* IPPB_LEL_ENTRY_FORMAT_INDEX_TO_VMV */ "", 48513 /* IPPB_LEL_ERR_DATA */ "", 48514 /* IPPB_LEL_INTERRUPT_MASK_REGISTER_ONE */ "", 48515 /* IPPB_LEL_INTERRUPT_REGISTER_ONE */ "", 48516 /* IPPB_LEL_INTERRUPT_REGISTER_ONE_TEST */ "", 48517 /* IPPB_MPLS_CRC_16_SEED */ "", 48518 /* IPPB_MPLS_CRC_32_FUNCTIONS_SELECTION_CFG */ "", 48519 /* IPPB_MPLS_LABEL_CRC_32_SEEDS */ "", 48520 /* IPPB_MPLS_LAYER_IDENTIFICATION_BITMAP_CFG */ "", 48521 /* IPPB_MPLS_RESERVED_LABEL_TYPES */ "", 48522 /* IPPB_MY_BFD_DIP_DESTINATION */ "", 48523 /* IPPB_MY_NDP_IP_1 */ "", 48524 /* IPPB_MY_NDP_IP_2 */ "", 48525 /* IPPB_OAM_BFD_MISCONFIG */ "", 48526 /* IPPB_OAM_BFD_YOUR_DISCR_TO_LIF_CFG */ "", 48527 /* IPPB_OAM_COUNTER_IN_RANGE_CFG_0 */ "", 48528 /* IPPB_OAM_COUNTER_IN_RANGE_CFG_1 */ "", 48529 /* IPPB_OAM_COUNTER_IN_RANGE_CFG_2 */ "", 48530 /* IPPB_OAM_COUNTER_NOT_IN_RANGE_CFG_0 */ "", 48531 /* IPPB_OAM_COUNTER_NOT_IN_RANGE_CFG_1 */ "", 48532 /* IPPB_OAM_COUNTER_NOT_IN_RANGE_CFG_2 */ "", 48533 /* IPPB_OAM_COUNTER_RANGE */ "", 48534 /* IPPB_OAM_DEFAULT_ACC_MEP_PROFILES */ "", 48535 /* IPPB_OAM_DEFAULT_COUNTERS */ "", 48536 /* IPPB_OAM_DEFAULT_INTERFACE */ "", 48537 /* IPPB_OAM_DEFAULT_MP_TYPE_VECTOR */ "", 48538 /* IPPB_OAM_ETHERNET_CFG */ "", 48539 /* IPPB_OAM_IDENTIFICATION_ENABLE */ "", 48540 /* IPPB_OAM_ID_RIF_THRESHOLD */ "", 48541 /* IPPB_OAM_IN_LIF_PROFILE_MAP */ "", 48542 /* IPPB_OAM_LIF_DB_ACCESS_PROFILE_EN_0 */ "", 48543 /* IPPB_OAM_LIF_DB_ACCESS_PROFILE_EN_1 */ "", 48544 /* IPPB_OAM_LIF_DB_ACCESS_PROFILE_EN_2 */ "", 48545 /* IPPB_OAM_LM_COUNTER_READ_IDX_SEL_MEM */ "", 48546 /* IPPB_OAM_PACKET_INJECTED_BITMAP */ "", 48547 /* IPPB_OAM_STATISTICS_CFG */ "", 48548 /* IPPB_OAM_VMV_SHIFT_VALUE_MAP */ "", 48549 /* IPPB_OUTLIF_PROFILE_CONFIGURATION */ "", 48550 /* IPPB_PARITY_ERR_CNT */ "", 48551 /* IPPB_PAR_ERR_MEM_MASK */ "", 48552 /* IPPB_PCMI_0 */ "", 48553 /* IPPB_PCMI_1 */ "", 48554 /* IPPB_PCMI_2 */ "", 48555 /* IPPB_PCMI_3 */ "", 48556 /* IPPB_PCMI_4 */ "", 48557 /* IPPB_PCMI_0_S */ "", 48558 /* IPPB_PCMI_0_T */ "", 48559 /* IPPB_PCMI_1_S */ "", 48560 /* IPPB_PCMI_1_T */ "", 48561 /* IPPB_PCMI_2_S */ "", 48562 /* IPPB_PCMI_2_T */ "", 48563 /* IPPB_PCMI_3_S */ "", 48564 /* IPPB_PCMI_3_T */ "", 48565 /* IPPB_PCMI_4_S */ "", 48566 /* IPPB_PCMI_4_T */ "", 48567 /* IPPB_PHB_ECN_INHERITANCE_RESOLUTION_MPLS_CFG */ "", 48568 /* IPPB_PHB_TC_DP_INHERITANCE_RESOLUTION_MPLS_CFG */ "", 48569 /* IPPB_PROG_TRAP_CFG */ "", 48570 /* IPPB_REG_0300 */ "", 48571 /* IPPB_REG_0301 */ "", 48572 /* IPPB_REG_0500 */ "", 48573 /* IPPB_REG_0501 */ "", 48574 /* IPPB_REG_600 */ "", 48575 /* IPPB_REG_1004 */ "", 48576 /* IPPB_REG_1007 */ "", 48577 /* IPPB_REG_1009 */ "", 48578 /* IPPB_REG_1104 */ "", 48579 /* IPPB_REG_1107 */ "", 48580 /* IPPB_REG_1109 */ "", 48581 /* IPPB_REG_00A4 */ "", 48582 /* IPPB_REG_00A6 */ "", 48583 /* IPPB_REG_00AA */ "", 48584 /* IPPB_REG_00C2 */ "", 48585 /* IPPB_REG_00C5 */ "", 48586 /* IPPB_REG_00E7 */ "", 48587 /* IPPB_REG_00F0 */ "", 48588 /* IPPB_RESERVED_MIRROR_ADDR */ "", 48589 /* IPPB_RESERVED_MTCD */ "", 48590 /* IPPB_RESERVED_MTCP */ "", 48591 /* IPPB_RESERVED_SPARE_0 */ "", 48592 /* IPPB_RESERVED_SPARE_1 */ "", 48593 /* IPPB_RESERVED_SPARE_2 */ "", 48594 /* IPPB_RESERVED_SPARE_3 */ "", 48595 /* IPPB_RFC_6374_FLAGS */ "", 48596 /* IPPB_SBUS_BROADCAST_ID */ "", 48597 /* IPPB_SBUS_LAST_IN_CHAIN */ "", 48598 /* IPPB_TCDP_PORT_CFG */ "", 48599 /* IPPB_TCP_ACTION_PROFILES_CFG */ "", 48600 /* IPPB_TRANSPLANT_WITH_WEAKER_STRENGTH_CFG */ "", 48601 /* IPPB_TTL_0_ACTION_PROFILE */ "", 48602 /* IPPB_TTL_1_ACTION_PROFILE */ "", 48603 /* IPPB_TTL_INHERITANCE_RESOLUTION_MPLS_CFG */ "", 48604 /* IPPB_UDP_ACTION_PROFILES_CFG */ "", 48605 /* IPPC_ACL_CONTEXT_PROFILE_MAP */ "", 48606 /* IPPC_ACTION_DISABLE */ "", 48607 /* IPPC_BIER_CFG */ "", 48608 /* IPPC_CPU_TRAP_CODE_PROFILE */ "", 48609 /* IPPC_DBG_LAST_FEM */ "", 48610 /* IPPC_DBG_LAST_FEM_NUM */ "", 48611 /* IPPC_DBG_LAST_FES */ "", 48612 /* IPPC_DBG_LAST_FES_NUM */ "", 48613 /* IPPC_DBG_LAST_KEY_A */ "", 48614 /* IPPC_DBG_LAST_KEY_B */ "", 48615 /* IPPC_DBG_LAST_KEY_C */ "", 48616 /* IPPC_DBG_LAST_KEY_D */ "", 48617 /* IPPC_DBG_LAST_KEY_E */ "", 48618 /* IPPC_DBG_LAST_KEY_F */ "", 48619 /* IPPC_DBG_LAST_KEY_G */ "", 48620 /* IPPC_DBG_LAST_KEY_H */ "", 48621 /* IPPC_DBG_LAST_KEY_I */ "", 48622 /* IPPC_DBG_LAST_KEY_J */ "", 48623 /* IPPC_DEFAULT_EXEM_ACTION */ "", 48624 /* IPPC_DEFAULT_MAPS_ACTION */ "", 48625 /* IPPC_DEFAULT_TCAM_ACTION */ "", 48626 /* IPPC_ECC_1B_ERR_CNT */ "", 48627 /* IPPC_ECC_2B_ERR_CNT */ "", 48628 /* IPPC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 48629 /* IPPC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 48630 /* IPPC_ECC_INTERRUPT_REGISTER */ "", 48631 /* IPPC_ECC_INTERRUPT_REGISTER_MASK */ "", 48632 /* IPPC_ECC_INTERRUPT_REGISTER_TEST */ "", 48633 /* IPPC_EGRESS_PARSING_INDEX */ "", 48634 /* IPPC_ELEPHANT_LEARN */ "", 48635 /* IPPC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 48636 /* IPPC_ERROR_INITIATION_DATA */ "", 48637 /* IPPC_EVENTOR_FIFO_CFG */ "", 48638 /* IPPC_FWD_CONTEXT_PROFILE_MAP */ "", 48639 /* IPPC_GTIMER_CONFIGURATION */ "", 48640 /* IPPC_GTIMER_CYCLE */ "", 48641 /* IPPC_INDIRECT_COMMAND */ "", 48642 /* IPPC_INDIRECT_COMMAND_ADDRESS */ "", 48643 /* IPPC_INDIRECT_COMMAND_RD_DATA */ "", 48644 /* IPPC_INDIRECT_COMMAND_WIDE_MEM */ "", 48645 /* IPPC_INDIRECT_COMMAND_WR_DATA */ "", 48646 /* IPPC_INDIRECT_FORCE_BUBBLE */ "", 48647 /* IPPC_INDIRECT_WR_MASK */ "", 48648 /* IPPC_INTERRUPT_MASK_REGISTER */ "", 48649 /* IPPC_INTERRUPT_REGISTER */ "", 48650 /* IPPC_INTERRUPT_REGISTER_TEST */ "", 48651 /* IPPC_INVALID_CPU_TRAP_QUALIFIER */ "", 48652 /* IPPC_MAP_1ST_CONTEXT_PROFILE */ "", 48653 /* IPPC_MDB_INTERFACES_MUX */ "", 48654 /* IPPC_OUT_LIF_RANGE */ "", 48655 /* IPPC_PACKET_HEADER_SIZE_RANGE */ "", 48656 /* IPPC_PARITY_ERR_CNT */ "", 48657 /* IPPC_PAR_ERR_MEM_MASK */ "", 48658 /* IPPC_PCMI_0 */ "", 48659 /* IPPC_PCMI_1 */ "", 48660 /* IPPC_PCMI_2 */ "", 48661 /* IPPC_PCMI_3 */ "", 48662 /* IPPC_PCMI_4 */ "", 48663 /* IPPC_PCMI_0_S */ "", 48664 /* IPPC_PCMI_0_T */ "", 48665 /* IPPC_PCMI_1_S */ "", 48666 /* IPPC_PCMI_1_T */ "", 48667 /* IPPC_PCMI_2_S */ "", 48668 /* IPPC_PCMI_2_T */ "", 48669 /* IPPC_PCMI_3_S */ "", 48670 /* IPPC_PCMI_3_T */ "", 48671 /* IPPC_PCMI_4_S */ "", 48672 /* IPPC_PCMI_4_T */ "", 48673 /* IPPC_PER_CONTEXT_LOOKUP_VALID_PASS_1 */ "", 48674 /* IPPC_PER_CONTEXT_LOOKUP_VALID_PASS_2 */ "", 48675 /* IPPC_PMFACSA_TCAM_ECC_FIX_EN */ "", 48676 /* IPPC_PMFACSA_TCAM_PROTECTION_ERROR */ "", 48677 /* IPPC_PMFACSA_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48678 /* IPPC_PMFACSA_TCAM_RESET_BLOCK */ "", 48679 /* IPPC_PMFACSB_TCAM_ECC_FIX_EN */ "", 48680 /* IPPC_PMFACSB_TCAM_PROTECTION_ERROR */ "", 48681 /* IPPC_PMFACSB_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48682 /* IPPC_PMFACSB_TCAM_RESET_BLOCK */ "", 48683 /* IPPC_PMF_GENERAL */ "", 48684 /* IPPC_PMF_PRTOCOL_IS_ETH */ "", 48685 /* IPPC_PMF_PRTOCOL_IS_L_4 */ "", 48686 /* IPPC_PMF_STATE_TABLE_CFG */ "", 48687 /* IPPC_PMF_STATISTIC_10_MAP */ "", 48688 /* IPPC_REG_0330 */ "", 48689 /* IPPC_REG_0331 */ "", 48690 /* IPPC_REG_0505 */ "", 48691 /* IPPC_REG_0508 */ "", 48692 /* IPPC_REG_0605 */ "", 48693 /* IPPC_REG_0608 */ "", 48694 /* IPPC_REG_700 */ "", 48695 /* IPPC_REG_00A4 */ "", 48696 /* IPPC_REG_00A6 */ "", 48697 /* IPPC_REG_00AA */ "", 48698 /* IPPC_REG_00C2 */ "", 48699 /* IPPC_REG_00F0 */ "", 48700 /* IPPC_REG_050A */ "", 48701 /* IPPC_REG_060A */ "", 48702 /* IPPC_RESERVED_MIRROR_ADDR */ "", 48703 /* IPPC_RESERVED_MTCD */ "", 48704 /* IPPC_RESERVED_MTCP */ "", 48705 /* IPPC_RESERVED_SPARE_0 */ "", 48706 /* IPPC_RESERVED_SPARE_1 */ "", 48707 /* IPPC_RESERVED_SPARE_2 */ "", 48708 /* IPPC_RESERVED_SPARE_3 */ "", 48709 /* IPPC_SBUS_BROADCAST_ID */ "", 48710 /* IPPC_SBUS_LAST_IN_CHAIN */ "", 48711 /* IPPC_SPECIAL_CLOCK_CONTROLS */ "", 48712 /* IPPC_TRJ_CFG */ "", 48713 /* IPPC_VID_VALID */ "", 48714 /* IPPD_ACL_CONTEXT_PROFILE_MAP */ "", 48715 /* IPPD_ACTION_DISABLE */ "", 48716 /* IPPD_ADDITIONAL_INFO_TO_UNKNOWN_ADDRESS_MAP */ "", 48717 /* IPPD_ALLOW_DEFAULT_ROUTE */ "", 48718 /* IPPD_APP_PREFIX_CONTROL */ "", 48719 /* IPPD_BAD_REPLIES_COUNTER */ "", 48720 /* IPPD_BUILD_OAM_TS_HEADER */ "", 48721 /* IPPD_COUNTER_PROFILE_MAP */ "", 48722 /* IPPD_CPU_INFO_REPLY_COUNTER */ "", 48723 /* IPPD_CPU_INFO_REPLY_ERROR_COUNTER */ "", 48724 /* IPPD_CPU_INFO_REPLY_OVF_COUNTER */ "", 48725 /* IPPD_CPU_LOOKUP_REPLY_COUNTER */ "", 48726 /* IPPD_CPU_LOOKUP_REPLY_ERROR_COUNTER */ "", 48727 /* IPPD_CPU_LOOKUP_REPLY_OVF_COUNTER */ "", 48728 /* IPPD_CPU_RECORDS_COUNTER */ "", 48729 /* IPPD_CPU_RECORD_CONTROL */ "", 48730 /* IPPD_CPU_RECORD_DATA_LSB */ "", 48731 /* IPPD_CPU_RECORD_DATA_MSB */ "", 48732 /* IPPD_CPU_RECORD_OPCODE */ "", 48733 /* IPPD_CPU_TRAP_CODE_PROFILE */ "", 48734 /* IPPD_DBG_LAST_FES */ "", 48735 /* IPPD_DBG_LAST_FES_NUM */ "", 48736 /* IPPD_DBG_LAST_KEY_A */ "", 48737 /* IPPD_DBG_LAST_KEY_B */ "", 48738 /* IPPD_DBG_LAST_KEY_C */ "", 48739 /* IPPD_DBG_LAST_RESOLVED_TRAP */ "", 48740 /* IPPD_DBG_LAST_TRAP_CHANGE_DESTINATION_REG */ "", 48741 /* IPPD_DEFAULT_EXEM_PAYLOAD */ "", 48742 /* IPPD_DEFAULT_MAPS_PAYLOAD */ "", 48743 /* IPPD_DEFAULT_TCAM_ACTION */ "", 48744 /* IPPD_ECC_1B_ERR_CNT */ "", 48745 /* IPPD_ECC_2B_ERR_CNT */ "", 48746 /* IPPD_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 48747 /* IPPD_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 48748 /* IPPD_ECC_INTERRUPT_REGISTER */ "", 48749 /* IPPD_ECC_INTERRUPT_REGISTER_MASK */ "", 48750 /* IPPD_ECC_INTERRUPT_REGISTER_TEST */ "", 48751 /* IPPD_ECMP_STAGE_BASE */ "", 48752 /* IPPD_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 48753 /* IPPD_FER_POINTER_CONSRUCTION */ "", 48754 /* IPPD_FER_TRAP_CFG */ "", 48755 /* IPPD_GENERAL_CFGS */ "", 48756 /* IPPD_GOOD_REPLIES_COUNTER */ "", 48757 /* IPPD_GTIMER_CONFIGURATION */ "", 48758 /* IPPD_GTIMER_CYCLE */ "", 48759 /* IPPD_INDIRECT_COMMAND */ "", 48760 /* IPPD_INDIRECT_COMMAND_ADDRESS */ "", 48761 /* IPPD_INDIRECT_COMMAND_RD_DATA */ "", 48762 /* IPPD_INDIRECT_COMMAND_WIDE_MEM */ "", 48763 /* IPPD_INDIRECT_COMMAND_WR_DATA */ "", 48764 /* IPPD_INDIRECT_FORCE_BUBBLE */ "", 48765 /* IPPD_INDIRECT_WR_MASK */ "", 48766 /* IPPD_INFO_REPLY */ "", 48767 /* IPPD_INTERLAKEN_CFGS */ "", 48768 /* IPPD_INTERRUPT_MASK_REGISTER */ "", 48769 /* IPPD_INTERRUPT_REGISTER */ "", 48770 /* IPPD_INTERRUPT_REGISTER_TEST */ "", 48771 /* IPPD_INVALID_DESTINATION */ "", 48772 /* IPPD_IN_LIF_ORIENTATION_MAP */ "", 48773 /* IPPD_IN_LIF_PROFILE_MAP */ "", 48774 /* IPPD_IPPD_SAMPLE_VALIDS */ "", 48775 /* IPPD_IS_ETHERNET */ "", 48776 /* IPPD_IS_IP */ "", 48777 /* IPPD_ITPP_TERMINATE_NETWORK_HEADERS */ "", 48778 /* IPPD_LAST_ERROR_SEQUENCE_RX */ "", 48779 /* IPPD_LBP_GENERAL_CONFIG_0 */ "", 48780 /* IPPD_LBP_GENERAL_CONFIG_1 */ "", 48781 /* IPPD_LBP_GENERAL_CONFIG_3 */ "", 48782 /* IPPD_LBP_HEADER_CONFIG */ "", 48783 /* IPPD_LBP_TIME_STAMP_FIFO_CONFIG */ "", 48784 /* IPPD_LEARN_PAYLOAD_STRENGTH_SIZE */ "", 48785 /* IPPD_LOOKUPS_COUNTER */ "", 48786 /* IPPD_LOOKUP_REPLY */ "", 48787 /* IPPD_MUX_EXEM_INTERFACE */ "", 48788 /* IPPD_NIF_PHYSICAL_ERR_COUNTER */ "", 48789 /* IPPD_OAM_SUB_TYPE_MAP */ "", 48790 /* IPPD_OUTLIF_OVERLOAD */ "", 48791 /* IPPD_OUT_LIF_RANGE */ "", 48792 /* IPPD_OUT_RIF_RANGE */ "", 48793 /* IPPD_PACKET_DATA_LATENCY_CONTROL_FIFO_CFG */ "", 48794 /* IPPD_PACKET_SIZE */ "", 48795 /* IPPD_PARITY_ERR_CNT */ "", 48796 /* IPPD_PAR_ERR_MEM_MASK */ "", 48797 /* IPPD_PASS_FIFO_CFG */ "", 48798 /* IPPD_PCMI_0 */ "", 48799 /* IPPD_PCMI_1 */ "", 48800 /* IPPD_PCMI_2 */ "", 48801 /* IPPD_PCMI_3 */ "", 48802 /* IPPD_PCMI_4 */ "", 48803 /* IPPD_PCMI_0_S */ "", 48804 /* IPPD_PCMI_0_T */ "", 48805 /* IPPD_PCMI_1_S */ "", 48806 /* IPPD_PCMI_1_T */ "", 48807 /* IPPD_PCMI_2_S */ "", 48808 /* IPPD_PCMI_2_T */ "", 48809 /* IPPD_PCMI_3_S */ "", 48810 /* IPPD_PCMI_3_T */ "", 48811 /* IPPD_PCMI_4_S */ "", 48812 /* IPPD_PCMI_4_T */ "", 48813 /* IPPD_PER_CONTEXT_LOOKUP_VALID */ "", 48814 /* IPPD_PHY_CHANNEL_CFGS */ "", 48815 /* IPPD_PMFBCS_TCAM_ECC_FIX_EN */ "", 48816 /* IPPD_PMFBCS_TCAM_PROTECTION_ERROR */ "", 48817 /* IPPD_PMFBCS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48818 /* IPPD_PMFBCS_TCAM_RESET_BLOCK */ "", 48819 /* IPPD_PMF_GENERAL */ "", 48820 /* IPPD_PPH_FHEI_FWD_SIZE */ "", 48821 /* IPPD_PPH_FHEI_IVE_SIZE */ "", 48822 /* IPPD_PPH_VSI_SOURCE */ "", 48823 /* IPPD_RECEIVE_FIFO_STATUS */ "", 48824 /* IPPD_REG_0400 */ "", 48825 /* IPPD_REG_0401 */ "", 48826 /* IPPD_REG_0705 */ "", 48827 /* IPPD_REG_0708 */ "", 48828 /* IPPD_REG_800 */ "", 48829 /* IPPD_REG_00C2 */ "", 48830 /* IPPD_REG_00C5 */ "", 48831 /* IPPD_REG_00C6 */ "", 48832 /* IPPD_REG_00F0 */ "", 48833 /* IPPD_REG_070A */ "", 48834 /* IPPD_RESERVED_MIRROR_ADDR */ "", 48835 /* IPPD_RESERVED_MTCD */ "", 48836 /* IPPD_RESERVED_MTCP */ "", 48837 /* IPPD_RESERVED_SPARE_0 */ "", 48838 /* IPPD_RESERVED_SPARE_1 */ "", 48839 /* IPPD_RESERVED_SPARE_2 */ "", 48840 /* IPPD_RESERVED_SPARE_3 */ "", 48841 /* IPPD_RESOLUTION_CFG */ "", 48842 /* IPPD_RESOLUTION_FACILITY_PROTECTION_LOGIC */ "", 48843 /* IPPD_RESOLUTION_FACILITY_TRAP_LOGIC */ "", 48844 /* IPPD_SBUS_BROADCAST_ID */ "", 48845 /* IPPD_SBUS_LAST_IN_CHAIN */ "", 48846 /* IPPD_SEQUENCE_EXPECTED */ "", 48847 /* IPPD_SEQUENCE_TX */ "", 48848 /* IPPD_SLB_PER_CONTEXT_ENABLE */ "", 48849 /* IPPD_SPECIAL_CLOCK_CONTROLS */ "", 48850 /* IPPD_SPR_CFGS */ "", 48851 /* IPPD_SPR_DLY_CFGS */ "", 48852 /* IPPD_STATISTIC_PROFILE_MAP */ "", 48853 /* IPPD_TOD_LAST_VALUE */ "", 48854 /* IPPD_TRANSMIT_CFGS */ "", 48855 /* IPPD_TRANSMIT_FIFO_STATUS */ "", 48856 /* IPPD_TX_APP_PREFIX */ "", 48857 /* IPPD_UDH_TYPE_TO_SIZE_MAP */ "", 48858 /* IPPD_XOR_INIT_DONE_REG */ "", 48859 /* IPPD_XOR_INIT_DONE_TABLE */ "", 48860 /* IPPE_ACTION_PROFILE_ACCEPTABLE_FRAME_TYPES */ "", 48861 /* IPPE_DBG_LLR_TRAP_0 */ "", 48862 /* IPPE_ECC_1B_ERR_CNT */ "", 48863 /* IPPE_ECC_2B_ERR_CNT */ "", 48864 /* IPPE_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 48865 /* IPPE_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 48866 /* IPPE_ECC_INTERRUPT_REGISTER */ "", 48867 /* IPPE_ECC_INTERRUPT_REGISTER_MASK */ "", 48868 /* IPPE_ECC_INTERRUPT_REGISTER_TEST */ "", 48869 /* IPPE_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 48870 /* IPPE_ERROR_INITIATION_DATA */ "", 48871 /* IPPE_EXTEND_VCP_EN */ "", 48872 /* IPPE_FILTERING_ACTION_PROFILES */ "", 48873 /* IPPE_GTIMER_CONFIGURATION */ "", 48874 /* IPPE_GTIMER_CYCLE */ "", 48875 /* IPPE_INDIRECT_COMMAND */ "", 48876 /* IPPE_INDIRECT_COMMAND_ADDRESS */ "", 48877 /* IPPE_INDIRECT_COMMAND_RD_DATA */ "", 48878 /* IPPE_INDIRECT_COMMAND_WIDE_MEM */ "", 48879 /* IPPE_INDIRECT_COMMAND_WR_DATA */ "", 48880 /* IPPE_INDIRECT_FORCE_BUBBLE */ "", 48881 /* IPPE_INDIRECT_WR_MASK */ "", 48882 /* IPPE_INTERRUPT_MASK_REGISTER */ "", 48883 /* IPPE_INTERRUPT_REGISTER */ "", 48884 /* IPPE_INTERRUPT_REGISTER_TEST */ "", 48885 /* IPPE_IPP_ENABLERS */ "", 48886 /* IPPE_IRE_VISIBILITY_BIT */ "", 48887 /* IPPE_LLRCS_TCAM_ECC_FIX_EN */ "", 48888 /* IPPE_LLRCS_TCAM_PROTECTION_ERROR */ "", 48889 /* IPPE_LLRCS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48890 /* IPPE_LLRCS_TCAM_RESET_BLOCK */ "", 48891 /* IPPE_LL_MIRROR_VID_01 */ "", 48892 /* IPPE_LL_MIRROR_VID_23 */ "", 48893 /* IPPE_LL_MIRROR_VID_45 */ "", 48894 /* IPPE_MIRROR_PROFILE_MAPPING */ "", 48895 /* IPPE_PARITY_ERR_CNT */ "", 48896 /* IPPE_PAR_ERR_MEM_MASK */ "", 48897 /* IPPE_PCMI_0 */ "", 48898 /* IPPE_PCMI_1 */ "", 48899 /* IPPE_PCMI_2 */ "", 48900 /* IPPE_PCMI_3 */ "", 48901 /* IPPE_PCMI_4 */ "", 48902 /* IPPE_PCMI_0_S */ "", 48903 /* IPPE_PCMI_0_T */ "", 48904 /* IPPE_PCMI_1_S */ "", 48905 /* IPPE_PCMI_1_T */ "", 48906 /* IPPE_PCMI_2_S */ "", 48907 /* IPPE_PCMI_2_T */ "", 48908 /* IPPE_PCMI_3_S */ "", 48909 /* IPPE_PCMI_3_T */ "", 48910 /* IPPE_PCMI_4_S */ "", 48911 /* IPPE_PCMI_4_T */ "", 48912 /* IPPE_PORT_VISIBILITY_CONFIG */ "", 48913 /* IPPE_PRTCAM_TCAM_ECC_FIX_EN */ "", 48914 /* IPPE_PRTCAM_TCAM_PROTECTION_ERROR */ "", 48915 /* IPPE_PRTCAM_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 48916 /* IPPE_PRTCAM_TCAM_RESET_BLOCK */ "", 48917 /* IPPE_PRT_FIFO_CONFIG */ "", 48918 /* IPPE_RECYC_FWD_PROFILE_MAPPING */ "", 48919 /* IPPE_RECYC_MRR_PROFILE_MAPPING */ "", 48920 /* IPPE_RECYC_SNP_PROFILE_MAPPING */ "", 48921 /* IPPE_REG_0100 */ "", 48922 /* IPPE_REG_0105 */ "", 48923 /* IPPE_REG_0114 */ "", 48924 /* IPPE_REG_0205 */ "", 48925 /* IPPE_REG_0208 */ "", 48926 /* IPPE_REG_0400 */ "", 48927 /* IPPE_REG_0401 */ "", 48928 /* IPPE_REG_0402 */ "", 48929 /* IPPE_REG_0403 */ "", 48930 /* IPPE_REG_500 */ "", 48931 /* IPPE_REG_0600 */ "", 48932 /* IPPE_REG_00A4 */ "", 48933 /* IPPE_REG_00A6 */ "", 48934 /* IPPE_REG_00AA */ "", 48935 /* IPPE_REG_00C2 */ "", 48936 /* IPPE_REG_020A */ "", 48937 /* IPPE_REG_0A05 */ "", 48938 /* IPPE_REG_0A08 */ "", 48939 /* IPPE_REG_0A0A */ "", 48940 /* IPPE_RESERVED_MIRROR_ADDR */ "", 48941 /* IPPE_RESERVED_MTCD */ "", 48942 /* IPPE_RESERVED_MTCP */ "", 48943 /* IPPE_RESERVED_SPARE_0 */ "", 48944 /* IPPE_RESERVED_SPARE_1 */ "", 48945 /* IPPE_RESERVED_SPARE_2 */ "", 48946 /* IPPE_RESERVED_SPARE_3 */ "", 48947 /* IPPE_SBUS_BROADCAST_ID */ "", 48948 /* IPPE_SBUS_LAST_IN_CHAIN */ "", 48949 /* IPPE_SYNC_COUNTER */ "", 48950 /* IPPE_VISIBILITY_CONFIG */ "", 48951 /* IPPE_VTT_FIFO_CONFIG */ "", 48952 /* IPPF_CFG_MAP_CTX_TO_LIF_LOOKUP_ENABLE */ "", 48953 /* IPPF_CFG_PROTOCOL_IS_ETH */ "", 48954 /* IPPF_CFG_PROTOCOL_IS_IPV4 */ "", 48955 /* IPPF_CFG_PROTOCOL_IS_IPV6 */ "", 48956 /* IPPF_CFG_PROTOCOL_IS_MAC_IN_MAC */ "", 48957 /* IPPF_CFG_PROTOCOL_IS_MPLS */ "", 48958 /* IPPF_COE_CFGS */ "", 48959 /* IPPF_CONTEXT_SELECTION_HIGH_PTC_MAPPING */ "", 48960 /* IPPF_CONTEXT_SELECTION_LOW_PTC_MAPPING */ "", 48961 /* IPPF_CS_INLIF_PROFILE_MAP_LSB */ "", 48962 /* IPPF_CS_INLIF_PROFILE_MAP_MSB */ "", 48963 /* IPPF_ECC_1B_ERR_CNT */ "", 48964 /* IPPF_ECC_2B_ERR_CNT */ "", 48965 /* IPPF_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 48966 /* IPPF_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 48967 /* IPPF_ECC_INTERRUPT_REGISTER */ "", 48968 /* IPPF_ECC_INTERRUPT_REGISTER_MASK */ "", 48969 /* IPPF_ECC_INTERRUPT_REGISTER_TEST */ "", 48970 /* IPPF_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 48971 /* IPPF_ERROR_INITIATION_DATA */ "", 48972 /* IPPF_ETHERNET_TRAP */ "", 48973 /* IPPF_ETHERNET_TRAP_ACTION_PROFILE_VECTOR */ "", 48974 /* IPPF_ETH_PCP_TO_OAM_PCP */ "", 48975 /* IPPF_FWD_DOMAIN_MASKS */ "", 48976 /* IPPF_FWD_DOMAIN_MASK_PROFILE_MAP */ "", 48977 /* IPPF_GTIMER_CONFIGURATION */ "", 48978 /* IPPF_GTIMER_CYCLE */ "", 48979 /* IPPF_HIGH_PTC_MAPPING */ "", 48980 /* IPPF_INDIRECT_COMMAND */ "", 48981 /* IPPF_INDIRECT_COMMAND_ADDRESS */ "", 48982 /* IPPF_INDIRECT_COMMAND_RD_DATA */ "", 48983 /* IPPF_INDIRECT_COMMAND_WIDE_MEM */ "", 48984 /* IPPF_INDIRECT_COMMAND_WR_DATA */ "", 48985 /* IPPF_INDIRECT_FORCE_BUBBLE */ "", 48986 /* IPPF_INDIRECT_WR_MASK */ "", 48987 /* IPPF_INITIAL_PCP_DEI_MAP_TYPE */ "", 48988 /* IPPF_INTERRUPT_MASK_REGISTER */ "", 48989 /* IPPF_INTERRUPT_REGISTER */ "", 48990 /* IPPF_INTERRUPT_REGISTER_TEST */ "", 48991 /* IPPF_IP_TOS_TO_OAM_PCP_0 */ "", 48992 /* IPPF_IP_TOS_TO_OAM_PCP_1 */ "", 48993 /* IPPF_LEARN_KEY_CONTEXT */ "", 48994 /* IPPF_LIF_TRAPS */ "", 48995 /* IPPF_LOW_PTC_MAPPING */ "", 48996 /* IPPF_MAC_IN_MAC_VSI */ "", 48997 /* IPPF_MAP_PARSER_CTX_TO_PROTOCOL */ "", 48998 /* IPPF_MAP_PORT_TO_LEARN_LIF_VEC */ "", 48999 /* IPPF_MAP_VRID_TO_IP_VERSION */ "", 49000 /* IPPF_MEF_L_2_CP_TRANSPARENT_BITMAP */ "", 49001 /* IPPF_MPLS_EXP_TO_OAM_PCP */ "", 49002 /* IPPF_MPLS_LABEL_PROCEDURE_CONFIG */ "", 49003 /* IPPF_MPLS_SPECIAL_LABEL_ATTRIBUTES */ "", 49004 /* IPPF_MY_B_MAC_LSB_BITMAP */ "", 49005 /* IPPF_MY_B_MAC_MC */ "", 49006 /* IPPF_MY_B_MAC_MSB */ "", 49007 /* IPPF_PARITY_ERR_CNT */ "", 49008 /* IPPF_PAR_ERR_MEM_MASK */ "", 49009 /* IPPF_PCMI_0 */ "", 49010 /* IPPF_PCMI_1 */ "", 49011 /* IPPF_PCMI_2 */ "", 49012 /* IPPF_PCMI_3 */ "", 49013 /* IPPF_PCMI_4 */ "", 49014 /* IPPF_PCMI_0_S */ "", 49015 /* IPPF_PCMI_0_T */ "", 49016 /* IPPF_PCMI_1_S */ "", 49017 /* IPPF_PCMI_1_T */ "", 49018 /* IPPF_PCMI_2_S */ "", 49019 /* IPPF_PCMI_2_T */ "", 49020 /* IPPF_PCMI_3_S */ "", 49021 /* IPPF_PCMI_3_T */ "", 49022 /* IPPF_PCMI_4_S */ "", 49023 /* IPPF_PCMI_4_T */ "", 49024 /* IPPF_REG_100 */ "", 49025 /* IPPF_REG_0310 */ "", 49026 /* IPPF_REG_0311 */ "", 49027 /* IPPF_REG_0555 */ "", 49028 /* IPPF_REG_0558 */ "", 49029 /* IPPF_REG_0605 */ "", 49030 /* IPPF_REG_0608 */ "", 49031 /* IPPF_REG_0855 */ "", 49032 /* IPPF_REG_0858 */ "", 49033 /* IPPF_REG_00A4 */ "", 49034 /* IPPF_REG_00A6 */ "", 49035 /* IPPF_REG_00AA */ "", 49036 /* IPPF_REG_00C2 */ "", 49037 /* IPPF_REG_03A0 */ "", 49038 /* IPPF_REG_03A1 */ "", 49039 /* IPPF_REG_055A */ "", 49040 /* IPPF_REG_060A */ "", 49041 /* IPPF_REG_085A */ "", 49042 /* IPPF_RESERVED_MIRROR_ADDR */ "", 49043 /* IPPF_RESERVED_MTCD */ "", 49044 /* IPPF_RESERVED_MTCP */ "", 49045 /* IPPF_RESERVED_SPARE_0 */ "", 49046 /* IPPF_RESERVED_SPARE_1 */ "", 49047 /* IPPF_RESERVED_SPARE_2 */ "", 49048 /* IPPF_RESERVED_SPARE_3 */ "", 49049 /* IPPF_SBUS_BROADCAST_ID */ "", 49050 /* IPPF_SBUS_LAST_IN_CHAIN */ "", 49051 /* IPPF_STATISTICS_INFO */ "", 49052 /* IPPF_STAT_OBJ_PROFILE_ATTR */ "", 49053 /* IPPF_VTACS_TCAM_ECC_FIX_EN */ "", 49054 /* IPPF_VTACS_TCAM_PROTECTION_ERROR */ "", 49055 /* IPPF_VTACS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 49056 /* IPPF_VTACS_TCAM_RESET_BLOCK */ "", 49057 /* IPPF_VTBCS_TCAM_ECC_FIX_EN */ "", 49058 /* IPPF_VTBCS_TCAM_PROTECTION_ERROR */ "", 49059 /* IPPF_VTBCS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 49060 /* IPPF_VTBCS_TCAM_RESET_BLOCK */ "", 49061 /* IPPF_VTCCS_TCAM_ECC_FIX_EN */ "", 49062 /* IPPF_VTCCS_TCAM_PROTECTION_ERROR */ "", 49063 /* IPPF_VTCCS_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 49064 /* IPPF_VTCCS_TCAM_RESET_BLOCK */ "", 49065 /* IPPF_VTT_ACTION_PROFILE_ACCEPTABLE_FRAME_TYPES */ "", 49066 /* IPPF_VTT_ETHERNET_TERMINATION_ACTION */ "", 49067 /* IPPF_VTT_GENERAL_CONFIGS_0 */ "", 49068 /* IPPF_VTT_MPLS_LABEL_RANGE_PROFILE */ "", 49069 /* IPPF_VTT_MPLS_PREPROCESSING_BOS_OR_TTL_TRAP */ "", 49070 /* IPPF_VTT_MY_MAC_VRID_VMV_SHIFT_VALUE */ "", 49071 /* IPPF_VTT_QOS_PROPAG_PROFILE_MAPPING */ "", 49072 /* IPPF_VTT_SPECIAL_LABELS_PROFILE */ "", 49073 /* IPPF_VTT_SPECIAL_LABEL_VALUES */ "", 49074 /* IPPF_VTT_ST_ONE_LE_CONTROL_FIFO_CFG */ "", 49075 /* IPPF_VTT_ST_ONE_LE_LATENCY_COMPENSATION_FIFO_CFG */ "", 49076 /* IPPF_VTT_ST_ONE_LE_VMV_SHIFT_VALUE_MAP */ "", 49077 /* IPPF_VTT_ST_TWO_LE_CONFIG */ "", 49078 /* IPPF_VTT_ST_TWO_LE_CONTROL_FIFO_CFG */ "", 49079 /* IPPF_VTT_ST_TWO_LE_LATENCY_COMPENSATION_FIFO_CFG */ "", 49080 /* IPPF_VTT_ST_TWO_LE_VMV_SHIFT_VALUE_MAP */ "", 49081 /* IPPF_VTT_TRAP_STRENGTHS_0 */ "", 49082 /* IPPF_VTT_TRAP_STRENGTHS_1 */ "", 49083 /* IPPF_VTT_TRAP_STRENGTHS_2 */ "", 49084 /* IPPF_VTT_TRAP_STRENGTHS_3 */ "", 49085 /* IPPF_VTT_TRAP_STRENGTHS_4 */ "", 49086 /* IPPF_VTT_TRAP_STRENGTHS_5 */ "", 49087 /* IPPF_VTT_TRAP_STRENGTHS_6 */ "", 49088 /* IPPF_VTT_TRAP_STRENGTHS_7 */ "", 49089 /* IPPF_VTT_TRAP_STRENGTHS_8 */ "", 49090 /* IPPF_VTT_TRAP_STRENGTHS_9 */ "", 49091 /* IPROCGENRES_PKA0_PKA_CONTROL_STATUS */ "", 49092 /* IPROCGENRES_PKA0_PKA_DATA_INPUT */ "", 49093 /* IPROCGENRES_PKA0_PKA_DATA_OUTPUT */ "", 49094 /* IPROCGENRES_PKA0_PKA_SCA_LFSR_SEED */ "", 49095 /* IPROCGENRES_RNG0_RNG_CTRL_0 */ "", 49096 /* IPROCGENRES_RNG0_RNG_FIFO_COUNT */ "", 49097 /* IPROCGENRES_RNG0_RNG_INT_ENABLE_0 */ "", 49098 /* IPROCGENRES_RNG0_RNG_INT_STATUS_0 */ "", 49099 /* IPROCGENRES_RNG0_RNG_RBG_SOFT_RESET */ "", 49100 /* IPROCGENRES_RNG0_RNG_REV_ID */ "", 49101 /* IPROCGENRES_RNG0_RNG_RNG_FIFO_DATA */ "", 49102 /* IPROCGENRES_RNG0_RNG_RNG_SOFT_RESET */ "", 49103 /* IPROCGENRES_RNG0_RNG_TOTAL_BIT_COUNT */ "", 49104 /* IPROCGENRES_RNG0_RNG_TOTAL_BIT_COUNT_THRESHOLD */ "", 49105 /* IPROCGENRES_TIM0_TIM_TIMER1BGLOAD */ "", 49106 /* IPROCGENRES_TIM0_TIM_TIMER1CONTROL */ "", 49107 /* IPROCGENRES_TIM0_TIM_TIMER1INTCLR */ "", 49108 /* IPROCGENRES_TIM0_TIM_TIMER1LOAD */ "", 49109 /* IPROCGENRES_TIM0_TIM_TIMER1MIS */ "", 49110 /* IPROCGENRES_TIM0_TIM_TIMER1RIS */ "", 49111 /* IPROCGENRES_TIM0_TIM_TIMER1VALUE */ "", 49112 /* IPROCGENRES_TIM0_TIM_TIMER2BGLOAD */ "", 49113 /* IPROCGENRES_TIM0_TIM_TIMER2CONTROL */ "", 49114 /* IPROCGENRES_TIM0_TIM_TIMER2INTCLR */ "", 49115 /* IPROCGENRES_TIM0_TIM_TIMER2LOAD */ "", 49116 /* IPROCGENRES_TIM0_TIM_TIMER2MIS */ "", 49117 /* IPROCGENRES_TIM0_TIM_TIMER2RIS */ "", 49118 /* IPROCGENRES_TIM0_TIM_TIMER2VALUE */ "", 49119 /* IPROCGENRES_TIM0_TIM_TIMERITCR */ "", 49120 /* IPROCGENRES_TIM0_TIM_TIMERITOP */ "", 49121 /* IPROCGENRES_TIM0_TIM_TIMERPCELLID0 */ "", 49122 /* IPROCGENRES_TIM0_TIM_TIMERPCELLID1 */ "", 49123 /* IPROCGENRES_TIM0_TIM_TIMERPCELLID2 */ "", 49124 /* IPROCGENRES_TIM0_TIM_TIMERPCELLID3 */ "", 49125 /* IPROCGENRES_TIM0_TIM_TIMERPERIPHID0 */ "", 49126 /* IPROCGENRES_TIM0_TIM_TIMERPERIPHID1 */ "", 49127 /* IPROCGENRES_TIM0_TIM_TIMERPERIPHID2 */ "", 49128 /* IPROCGENRES_TIM0_TIM_TIMERPERIPHID3 */ "", 49129 /* IPROCGENRES_TIM1_TIM_TIMER1BGLOAD */ "", 49130 /* IPROCGENRES_TIM1_TIM_TIMER1CONTROL */ "", 49131 /* IPROCGENRES_TIM1_TIM_TIMER1INTCLR */ "", 49132 /* IPROCGENRES_TIM1_TIM_TIMER1LOAD */ "", 49133 /* IPROCGENRES_TIM1_TIM_TIMER1MIS */ "", 49134 /* IPROCGENRES_TIM1_TIM_TIMER1RIS */ "", 49135 /* IPROCGENRES_TIM1_TIM_TIMER1VALUE */ "", 49136 /* IPROCGENRES_TIM1_TIM_TIMER2BGLOAD */ "", 49137 /* IPROCGENRES_TIM1_TIM_TIMER2CONTROL */ "", 49138 /* IPROCGENRES_TIM1_TIM_TIMER2INTCLR */ "", 49139 /* IPROCGENRES_TIM1_TIM_TIMER2LOAD */ "", 49140 /* IPROCGENRES_TIM1_TIM_TIMER2MIS */ "", 49141 /* IPROCGENRES_TIM1_TIM_TIMER2RIS */ "", 49142 /* IPROCGENRES_TIM1_TIM_TIMER2VALUE */ "", 49143 /* IPROCGENRES_TIM1_TIM_TIMERITCR */ "", 49144 /* IPROCGENRES_TIM1_TIM_TIMERITOP */ "", 49145 /* IPROCGENRES_TIM1_TIM_TIMERPCELLID0 */ "", 49146 /* IPROCGENRES_TIM1_TIM_TIMERPCELLID1 */ "", 49147 /* IPROCGENRES_TIM1_TIM_TIMERPCELLID2 */ "", 49148 /* IPROCGENRES_TIM1_TIM_TIMERPCELLID3 */ "", 49149 /* IPROCGENRES_TIM1_TIM_TIMERPERIPHID0 */ "", 49150 /* IPROCGENRES_TIM1_TIM_TIMERPERIPHID1 */ "", 49151 /* IPROCGENRES_TIM1_TIM_TIMERPERIPHID2 */ "", 49152 /* IPROCGENRES_TIM1_TIM_TIMERPERIPHID3 */ "", 49153 /* IPROCGENRES_TIM2_TIM_TIMER1BGLOAD */ "", 49154 /* IPROCGENRES_TIM2_TIM_TIMER1CONTROL */ "", 49155 /* IPROCGENRES_TIM2_TIM_TIMER1INTCLR */ "", 49156 /* IPROCGENRES_TIM2_TIM_TIMER1LOAD */ "", 49157 /* IPROCGENRES_TIM2_TIM_TIMER1MIS */ "", 49158 /* IPROCGENRES_TIM2_TIM_TIMER1RIS */ "", 49159 /* IPROCGENRES_TIM2_TIM_TIMER1VALUE */ "", 49160 /* IPROCGENRES_TIM2_TIM_TIMER2BGLOAD */ "", 49161 /* IPROCGENRES_TIM2_TIM_TIMER2CONTROL */ "", 49162 /* IPROCGENRES_TIM2_TIM_TIMER2INTCLR */ "", 49163 /* IPROCGENRES_TIM2_TIM_TIMER2LOAD */ "", 49164 /* IPROCGENRES_TIM2_TIM_TIMER2MIS */ "", 49165 /* IPROCGENRES_TIM2_TIM_TIMER2RIS */ "", 49166 /* IPROCGENRES_TIM2_TIM_TIMER2VALUE */ "", 49167 /* IPROCGENRES_TIM2_TIM_TIMERITCR */ "", 49168 /* IPROCGENRES_TIM2_TIM_TIMERITOP */ "", 49169 /* IPROCGENRES_TIM2_TIM_TIMERPCELLID0 */ "", 49170 /* IPROCGENRES_TIM2_TIM_TIMERPCELLID1 */ "", 49171 /* IPROCGENRES_TIM2_TIM_TIMERPCELLID2 */ "", 49172 /* IPROCGENRES_TIM2_TIM_TIMERPCELLID3 */ "", 49173 /* IPROCGENRES_TIM2_TIM_TIMERPERIPHID0 */ "", 49174 /* IPROCGENRES_TIM2_TIM_TIMERPERIPHID1 */ "", 49175 /* IPROCGENRES_TIM2_TIM_TIMERPERIPHID2 */ "", 49176 /* IPROCGENRES_TIM2_TIM_TIMERPERIPHID3 */ "", 49177 /* IPROCGENRES_TIM3_TIM_TIMER1BGLOAD */ "", 49178 /* IPROCGENRES_TIM3_TIM_TIMER1CONTROL */ "", 49179 /* IPROCGENRES_TIM3_TIM_TIMER1INTCLR */ "", 49180 /* IPROCGENRES_TIM3_TIM_TIMER1LOAD */ "", 49181 /* IPROCGENRES_TIM3_TIM_TIMER1MIS */ "", 49182 /* IPROCGENRES_TIM3_TIM_TIMER1RIS */ "", 49183 /* IPROCGENRES_TIM3_TIM_TIMER1VALUE */ "", 49184 /* IPROCGENRES_TIM3_TIM_TIMER2BGLOAD */ "", 49185 /* IPROCGENRES_TIM3_TIM_TIMER2CONTROL */ "", 49186 /* IPROCGENRES_TIM3_TIM_TIMER2INTCLR */ "", 49187 /* IPROCGENRES_TIM3_TIM_TIMER2LOAD */ "", 49188 /* IPROCGENRES_TIM3_TIM_TIMER2MIS */ "", 49189 /* IPROCGENRES_TIM3_TIM_TIMER2RIS */ "", 49190 /* IPROCGENRES_TIM3_TIM_TIMER2VALUE */ "", 49191 /* IPROCGENRES_TIM3_TIM_TIMERITCR */ "", 49192 /* IPROCGENRES_TIM3_TIM_TIMERITOP */ "", 49193 /* IPROCGENRES_TIM3_TIM_TIMERPCELLID0 */ "", 49194 /* IPROCGENRES_TIM3_TIM_TIMERPCELLID1 */ "", 49195 /* IPROCGENRES_TIM3_TIM_TIMERPCELLID2 */ "", 49196 /* IPROCGENRES_TIM3_TIM_TIMERPCELLID3 */ "", 49197 /* IPROCGENRES_TIM3_TIM_TIMERPERIPHID0 */ "", 49198 /* IPROCGENRES_TIM3_TIM_TIMERPERIPHID1 */ "", 49199 /* IPROCGENRES_TIM3_TIM_TIMERPERIPHID2 */ "", 49200 /* IPROCGENRES_TIM3_TIM_TIMERPERIPHID3 */ "", 49201 /* IPROCGENRES_TIM4_TIM_TIMER1BGLOAD */ "", 49202 /* IPROCGENRES_TIM4_TIM_TIMER1CONTROL */ "", 49203 /* IPROCGENRES_TIM4_TIM_TIMER1INTCLR */ "", 49204 /* IPROCGENRES_TIM4_TIM_TIMER1LOAD */ "", 49205 /* IPROCGENRES_TIM4_TIM_TIMER1MIS */ "", 49206 /* IPROCGENRES_TIM4_TIM_TIMER1RIS */ "", 49207 /* IPROCGENRES_TIM4_TIM_TIMER1VALUE */ "", 49208 /* IPROCGENRES_TIM4_TIM_TIMER2BGLOAD */ "", 49209 /* IPROCGENRES_TIM4_TIM_TIMER2CONTROL */ "", 49210 /* IPROCGENRES_TIM4_TIM_TIMER2INTCLR */ "", 49211 /* IPROCGENRES_TIM4_TIM_TIMER2LOAD */ "", 49212 /* IPROCGENRES_TIM4_TIM_TIMER2MIS */ "", 49213 /* IPROCGENRES_TIM4_TIM_TIMER2RIS */ "", 49214 /* IPROCGENRES_TIM4_TIM_TIMER2VALUE */ "", 49215 /* IPROCGENRES_TIM4_TIM_TIMERITCR */ "", 49216 /* IPROCGENRES_TIM4_TIM_TIMERITOP */ "", 49217 /* IPROCGENRES_TIM4_TIM_TIMERPCELLID0 */ "", 49218 /* IPROCGENRES_TIM4_TIM_TIMERPCELLID1 */ "", 49219 /* IPROCGENRES_TIM4_TIM_TIMERPCELLID2 */ "", 49220 /* IPROCGENRES_TIM4_TIM_TIMERPCELLID3 */ "", 49221 /* IPROCGENRES_TIM4_TIM_TIMERPERIPHID0 */ "", 49222 /* IPROCGENRES_TIM4_TIM_TIMERPERIPHID1 */ "", 49223 /* IPROCGENRES_TIM4_TIM_TIMERPERIPHID2 */ "", 49224 /* IPROCGENRES_TIM4_TIM_TIMERPERIPHID3 */ "", 49225 /* IPROCGENRES_TIM5_TIM_TIMER1BGLOAD */ "", 49226 /* IPROCGENRES_TIM5_TIM_TIMER1CONTROL */ "", 49227 /* IPROCGENRES_TIM5_TIM_TIMER1INTCLR */ "", 49228 /* IPROCGENRES_TIM5_TIM_TIMER1LOAD */ "", 49229 /* IPROCGENRES_TIM5_TIM_TIMER1MIS */ "", 49230 /* IPROCGENRES_TIM5_TIM_TIMER1RIS */ "", 49231 /* IPROCGENRES_TIM5_TIM_TIMER1VALUE */ "", 49232 /* IPROCGENRES_TIM5_TIM_TIMER2BGLOAD */ "", 49233 /* IPROCGENRES_TIM5_TIM_TIMER2CONTROL */ "", 49234 /* IPROCGENRES_TIM5_TIM_TIMER2INTCLR */ "", 49235 /* IPROCGENRES_TIM5_TIM_TIMER2LOAD */ "", 49236 /* IPROCGENRES_TIM5_TIM_TIMER2MIS */ "", 49237 /* IPROCGENRES_TIM5_TIM_TIMER2RIS */ "", 49238 /* IPROCGENRES_TIM5_TIM_TIMER2VALUE */ "", 49239 /* IPROCGENRES_TIM5_TIM_TIMERITCR */ "", 49240 /* IPROCGENRES_TIM5_TIM_TIMERITOP */ "", 49241 /* IPROCGENRES_TIM5_TIM_TIMERPCELLID0 */ "", 49242 /* IPROCGENRES_TIM5_TIM_TIMERPCELLID1 */ "", 49243 /* IPROCGENRES_TIM5_TIM_TIMERPCELLID2 */ "", 49244 /* IPROCGENRES_TIM5_TIM_TIMERPCELLID3 */ "", 49245 /* IPROCGENRES_TIM5_TIM_TIMERPERIPHID0 */ "", 49246 /* IPROCGENRES_TIM5_TIM_TIMERPERIPHID1 */ "", 49247 /* IPROCGENRES_TIM5_TIM_TIMERPERIPHID2 */ "", 49248 /* IPROCGENRES_TIM5_TIM_TIMERPERIPHID3 */ "", 49249 /* IPROCGENRES_WDT0_WDT_WDOGCONTROL */ "", 49250 /* IPROCGENRES_WDT0_WDT_WDOGINTCLR */ "", 49251 /* IPROCGENRES_WDT0_WDT_WDOGITCR */ "", 49252 /* IPROCGENRES_WDT0_WDT_WDOGITOP */ "", 49253 /* IPROCGENRES_WDT0_WDT_WDOGLOAD */ "", 49254 /* IPROCGENRES_WDT0_WDT_WDOGLOCK */ "", 49255 /* IPROCGENRES_WDT0_WDT_WDOGMIS */ "", 49256 /* IPROCGENRES_WDT0_WDT_WDOGPCELLID0 */ "", 49257 /* IPROCGENRES_WDT0_WDT_WDOGPCELLID1 */ "", 49258 /* IPROCGENRES_WDT0_WDT_WDOGPCELLID2 */ "", 49259 /* IPROCGENRES_WDT0_WDT_WDOGPCELLID3 */ "", 49260 /* IPROCGENRES_WDT0_WDT_WDOGPERIPHID0 */ "", 49261 /* IPROCGENRES_WDT0_WDT_WDOGPERIPHID1 */ "", 49262 /* IPROCGENRES_WDT0_WDT_WDOGPERIPHID2 */ "", 49263 /* IPROCGENRES_WDT0_WDT_WDOGPERIPHID3 */ "", 49264 /* IPROCGENRES_WDT0_WDT_WDOGRIS */ "", 49265 /* IPROCGENRES_WDT0_WDT_WDOGVALUE */ "", 49266 /* IPROCPERIPH_GPIO_GP_AUX_SEL */ "", 49267 /* IPROCPERIPH_GPIO_GP_DATA_IN */ "", 49268 /* IPROCPERIPH_GPIO_GP_DATA_OUT */ "", 49269 /* IPROCPERIPH_GPIO_GP_INIT_VAL */ "", 49270 /* IPROCPERIPH_GPIO_GP_INT_CLR */ "", 49271 /* IPROCPERIPH_GPIO_GP_INT_DE */ "", 49272 /* IPROCPERIPH_GPIO_GP_INT_EDGE */ "", 49273 /* IPROCPERIPH_GPIO_GP_INT_MSK */ "", 49274 /* IPROCPERIPH_GPIO_GP_INT_MSTAT */ "", 49275 /* IPROCPERIPH_GPIO_GP_INT_STAT */ "", 49276 /* IPROCPERIPH_GPIO_GP_INT_TYPE */ "", 49277 /* IPROCPERIPH_GPIO_GP_OUT_EN */ "", 49278 /* IPROCPERIPH_GPIO_GP_PAD_RES */ "", 49279 /* IPROCPERIPH_GPIO_GP_PRB_ENABLE */ "", 49280 /* IPROCPERIPH_GPIO_GP_PRB_OE */ "", 49281 /* IPROCPERIPH_GPIO_GP_RES_EN */ "", 49282 /* IPROCPERIPH_GPIO_GP_TEST_ENABLE */ "", 49283 /* IPROCPERIPH_GPIO_GP_TEST_INPUT */ "", 49284 /* IPROCPERIPH_GPIO_GP_TEST_OUTPUT */ "", 49285 /* IPROCPERIPH_PL022_SPI_SSPCPSR */ "", 49286 /* IPROCPERIPH_PL022_SPI_SSPCR0 */ "", 49287 /* IPROCPERIPH_PL022_SPI_SSPCR1 */ "", 49288 /* IPROCPERIPH_PL022_SPI_SSPDMACR */ "", 49289 /* IPROCPERIPH_PL022_SPI_SSPDR */ "", 49290 /* IPROCPERIPH_PL022_SPI_SSPICR */ "", 49291 /* IPROCPERIPH_PL022_SPI_SSPIMSC */ "", 49292 /* IPROCPERIPH_PL022_SPI_SSPITIP */ "", 49293 /* IPROCPERIPH_PL022_SPI_SSPITOP */ "", 49294 /* IPROCPERIPH_PL022_SPI_SSPMIS */ "", 49295 /* IPROCPERIPH_PL022_SPI_SSPPCELLID0 */ "", 49296 /* IPROCPERIPH_PL022_SPI_SSPPCELLID1 */ "", 49297 /* IPROCPERIPH_PL022_SPI_SSPPCELLID2 */ "", 49298 /* IPROCPERIPH_PL022_SPI_SSPPCELLID3 */ "", 49299 /* IPROCPERIPH_PL022_SPI_SSPPERIPHID0 */ "", 49300 /* IPROCPERIPH_PL022_SPI_SSPPERIPHID1 */ "", 49301 /* IPROCPERIPH_PL022_SPI_SSPPERIPHID2 */ "", 49302 /* IPROCPERIPH_PL022_SPI_SSPPERIPHID3 */ "", 49303 /* IPROCPERIPH_PL022_SPI_SSPRIS */ "", 49304 /* IPROCPERIPH_PL022_SPI_SSPSR */ "", 49305 /* IPROCPERIPH_PL022_SPI_SSPTCR */ "", 49306 /* IPROCPERIPH_PL022_SPI_SSPTDR */ "", 49307 /* IPROCPERIPH_SMBUS0_SMBUS_ADDRESS */ "", 49308 /* IPROCPERIPH_SMBUS0_SMBUS_BIT_BANG_CONTROL */ "", 49309 /* IPROCPERIPH_SMBUS0_SMBUS_CONFIG */ "", 49310 /* IPROCPERIPH_SMBUS0_SMBUS_EVENT_ENABLE */ "", 49311 /* IPROCPERIPH_SMBUS0_SMBUS_EVENT_STATUS */ "", 49312 /* IPROCPERIPH_SMBUS0_SMBUS_MASTER_COMMAND */ "", 49313 /* IPROCPERIPH_SMBUS0_SMBUS_MASTER_DATA_READ */ "", 49314 /* IPROCPERIPH_SMBUS0_SMBUS_MASTER_DATA_WRITE */ "", 49315 /* IPROCPERIPH_SMBUS0_SMBUS_MASTER_FIFO_CONTROL */ "", 49316 /* IPROCPERIPH_SMBUS0_SMBUS_SLAVE_COMMAND */ "", 49317 /* IPROCPERIPH_SMBUS0_SMBUS_SLAVE_DATA_READ */ "", 49318 /* IPROCPERIPH_SMBUS0_SMBUS_SLAVE_DATA_WRITE */ "", 49319 /* IPROCPERIPH_SMBUS0_SMBUS_SLAVE_FIFO_CONTROL */ "", 49320 /* IPROCPERIPH_SMBUS0_SMBUS_TIMING_CONFIG */ "", 49321 /* IPROCPERIPH_SMBUS0_SMBUS_TIMING_CONFIG_2 */ "", 49322 /* IPROCPERIPH_SMBUS1_SMBUS_ADDRESS */ "", 49323 /* IPROCPERIPH_SMBUS1_SMBUS_BIT_BANG_CONTROL */ "", 49324 /* IPROCPERIPH_SMBUS1_SMBUS_CONFIG */ "", 49325 /* IPROCPERIPH_SMBUS1_SMBUS_EVENT_ENABLE */ "", 49326 /* IPROCPERIPH_SMBUS1_SMBUS_EVENT_STATUS */ "", 49327 /* IPROCPERIPH_SMBUS1_SMBUS_MASTER_COMMAND */ "", 49328 /* IPROCPERIPH_SMBUS1_SMBUS_MASTER_DATA_READ */ "", 49329 /* IPROCPERIPH_SMBUS1_SMBUS_MASTER_DATA_WRITE */ "", 49330 /* IPROCPERIPH_SMBUS1_SMBUS_MASTER_FIFO_CONTROL */ "", 49331 /* IPROCPERIPH_SMBUS1_SMBUS_SLAVE_COMMAND */ "", 49332 /* IPROCPERIPH_SMBUS1_SMBUS_SLAVE_DATA_READ */ "", 49333 /* IPROCPERIPH_SMBUS1_SMBUS_SLAVE_DATA_WRITE */ "", 49334 /* IPROCPERIPH_SMBUS1_SMBUS_SLAVE_FIFO_CONTROL */ "", 49335 /* IPROCPERIPH_SMBUS1_SMBUS_TIMING_CONFIG */ "", 49336 /* IPROCPERIPH_SMBUS1_SMBUS_TIMING_CONFIG_2 */ "", 49337 /* IPROCPERIPH_SMBUS2_SMBUS_ADDRESS */ "", 49338 /* IPROCPERIPH_SMBUS2_SMBUS_BIT_BANG_CONTROL */ "", 49339 /* IPROCPERIPH_SMBUS2_SMBUS_CONFIG */ "", 49340 /* IPROCPERIPH_SMBUS2_SMBUS_EVENT_ENABLE */ "", 49341 /* IPROCPERIPH_SMBUS2_SMBUS_EVENT_STATUS */ "", 49342 /* IPROCPERIPH_SMBUS2_SMBUS_MASTER_COMMAND */ "", 49343 /* IPROCPERIPH_SMBUS2_SMBUS_MASTER_DATA_READ */ "", 49344 /* IPROCPERIPH_SMBUS2_SMBUS_MASTER_DATA_WRITE */ "", 49345 /* IPROCPERIPH_SMBUS2_SMBUS_MASTER_FIFO_CONTROL */ "", 49346 /* IPROCPERIPH_SMBUS2_SMBUS_SLAVE_COMMAND */ "", 49347 /* IPROCPERIPH_SMBUS2_SMBUS_SLAVE_DATA_READ */ "", 49348 /* IPROCPERIPH_SMBUS2_SMBUS_SLAVE_DATA_WRITE */ "", 49349 /* IPROCPERIPH_SMBUS2_SMBUS_SLAVE_FIFO_CONTROL */ "", 49350 /* IPROCPERIPH_SMBUS2_SMBUS_TIMING_CONFIG */ "", 49351 /* IPROCPERIPH_SMBUS2_SMBUS_TIMING_CONFIG_2 */ "", 49352 /* IPROCPERIPH_SMBUS3_SMBUS_ADDRESS */ "", 49353 /* IPROCPERIPH_SMBUS3_SMBUS_BIT_BANG_CONTROL */ "", 49354 /* IPROCPERIPH_SMBUS3_SMBUS_CONFIG */ "", 49355 /* IPROCPERIPH_SMBUS3_SMBUS_EVENT_ENABLE */ "", 49356 /* IPROCPERIPH_SMBUS3_SMBUS_EVENT_STATUS */ "", 49357 /* IPROCPERIPH_SMBUS3_SMBUS_MASTER_COMMAND */ "", 49358 /* IPROCPERIPH_SMBUS3_SMBUS_MASTER_DATA_READ */ "", 49359 /* IPROCPERIPH_SMBUS3_SMBUS_MASTER_DATA_WRITE */ "", 49360 /* IPROCPERIPH_SMBUS3_SMBUS_MASTER_FIFO_CONTROL */ "", 49361 /* IPROCPERIPH_SMBUS3_SMBUS_SLAVE_COMMAND */ "", 49362 /* IPROCPERIPH_SMBUS3_SMBUS_SLAVE_DATA_READ */ "", 49363 /* IPROCPERIPH_SMBUS3_SMBUS_SLAVE_DATA_WRITE */ "", 49364 /* IPROCPERIPH_SMBUS3_SMBUS_SLAVE_FIFO_CONTROL */ "", 49365 /* IPROCPERIPH_SMBUS3_SMBUS_TIMING_CONFIG */ "", 49366 /* IPROCPERIPH_SMBUS3_SMBUS_TIMING_CONFIG_2 */ "", 49367 /* IPROCPERIPH_UART0_UART_CPR */ "", 49368 /* IPROCPERIPH_UART0_UART_CTR */ "", 49369 /* IPROCPERIPH_UART0_UART_DLH_IER */ "", 49370 /* IPROCPERIPH_UART0_UART_DMASA */ "", 49371 /* IPROCPERIPH_UART0_UART_FAR */ "", 49372 /* IPROCPERIPH_UART0_UART_HTX */ "", 49373 /* IPROCPERIPH_UART0_UART_IIR_FCR */ "", 49374 /* IPROCPERIPH_UART0_UART_LCR */ "", 49375 /* IPROCPERIPH_UART0_UART_LSR */ "", 49376 /* IPROCPERIPH_UART0_UART_MCR */ "", 49377 /* IPROCPERIPH_UART0_UART_MSR */ "", 49378 /* IPROCPERIPH_UART0_UART_RBR_THR_DLL */ "", 49379 /* IPROCPERIPH_UART0_UART_RFL */ "", 49380 /* IPROCPERIPH_UART0_UART_RFW */ "", 49381 /* IPROCPERIPH_UART0_UART_SBCR */ "", 49382 /* IPROCPERIPH_UART0_UART_SCR */ "", 49383 /* IPROCPERIPH_UART0_UART_SDMAM */ "", 49384 /* IPROCPERIPH_UART0_UART_SFE */ "", 49385 /* IPROCPERIPH_UART0_UART_SRBR_STHR */ "", 49386 /* IPROCPERIPH_UART0_UART_SRBR_STHR0 */ "", 49387 /* IPROCPERIPH_UART0_UART_SRBR_STHR1 */ "", 49388 /* IPROCPERIPH_UART0_UART_SRBR_STHR2 */ "", 49389 /* IPROCPERIPH_UART0_UART_SRBR_STHR3 */ "", 49390 /* IPROCPERIPH_UART0_UART_SRBR_STHR4 */ "", 49391 /* IPROCPERIPH_UART0_UART_SRBR_STHR5 */ "", 49392 /* IPROCPERIPH_UART0_UART_SRBR_STHR6 */ "", 49393 /* IPROCPERIPH_UART0_UART_SRBR_STHR7 */ "", 49394 /* IPROCPERIPH_UART0_UART_SRBR_STHR8 */ "", 49395 /* IPROCPERIPH_UART0_UART_SRBR_STHR9 */ "", 49396 /* IPROCPERIPH_UART0_UART_SRBR_STHR10 */ "", 49397 /* IPROCPERIPH_UART0_UART_SRBR_STHR11 */ "", 49398 /* IPROCPERIPH_UART0_UART_SRBR_STHR12 */ "", 49399 /* IPROCPERIPH_UART0_UART_SRBR_STHR13 */ "", 49400 /* IPROCPERIPH_UART0_UART_SRBR_STHR14 */ "", 49401 /* IPROCPERIPH_UART0_UART_SRBR_STHR15 */ "", 49402 /* IPROCPERIPH_UART0_UART_SRR */ "", 49403 /* IPROCPERIPH_UART0_UART_SRT */ "", 49404 /* IPROCPERIPH_UART0_UART_SRTS */ "", 49405 /* IPROCPERIPH_UART0_UART_STET */ "", 49406 /* IPROCPERIPH_UART0_UART_TFL */ "", 49407 /* IPROCPERIPH_UART0_UART_TFR */ "", 49408 /* IPROCPERIPH_UART0_UART_UCV */ "", 49409 /* IPROCPERIPH_UART0_UART_USR */ "", 49410 /* IPROCPERIPH_UART1_UART_CPR */ "", 49411 /* IPROCPERIPH_UART1_UART_CTR */ "", 49412 /* IPROCPERIPH_UART1_UART_DLH_IER */ "", 49413 /* IPROCPERIPH_UART1_UART_DMASA */ "", 49414 /* IPROCPERIPH_UART1_UART_FAR */ "", 49415 /* IPROCPERIPH_UART1_UART_HTX */ "", 49416 /* IPROCPERIPH_UART1_UART_IIR_FCR */ "", 49417 /* IPROCPERIPH_UART1_UART_LCR */ "", 49418 /* IPROCPERIPH_UART1_UART_LSR */ "", 49419 /* IPROCPERIPH_UART1_UART_MCR */ "", 49420 /* IPROCPERIPH_UART1_UART_MSR */ "", 49421 /* IPROCPERIPH_UART1_UART_RBR_THR_DLL */ "", 49422 /* IPROCPERIPH_UART1_UART_RFL */ "", 49423 /* IPROCPERIPH_UART1_UART_RFW */ "", 49424 /* IPROCPERIPH_UART1_UART_SBCR */ "", 49425 /* IPROCPERIPH_UART1_UART_SCR */ "", 49426 /* IPROCPERIPH_UART1_UART_SDMAM */ "", 49427 /* IPROCPERIPH_UART1_UART_SFE */ "", 49428 /* IPROCPERIPH_UART1_UART_SRBR_STHR */ "", 49429 /* IPROCPERIPH_UART1_UART_SRBR_STHR0 */ "", 49430 /* IPROCPERIPH_UART1_UART_SRBR_STHR1 */ "", 49431 /* IPROCPERIPH_UART1_UART_SRBR_STHR2 */ "", 49432 /* IPROCPERIPH_UART1_UART_SRBR_STHR3 */ "", 49433 /* IPROCPERIPH_UART1_UART_SRBR_STHR4 */ "", 49434 /* IPROCPERIPH_UART1_UART_SRBR_STHR5 */ "", 49435 /* IPROCPERIPH_UART1_UART_SRBR_STHR6 */ "", 49436 /* IPROCPERIPH_UART1_UART_SRBR_STHR7 */ "", 49437 /* IPROCPERIPH_UART1_UART_SRBR_STHR8 */ "", 49438 /* IPROCPERIPH_UART1_UART_SRBR_STHR9 */ "", 49439 /* IPROCPERIPH_UART1_UART_SRBR_STHR10 */ "", 49440 /* IPROCPERIPH_UART1_UART_SRBR_STHR11 */ "", 49441 /* IPROCPERIPH_UART1_UART_SRBR_STHR12 */ "", 49442 /* IPROCPERIPH_UART1_UART_SRBR_STHR13 */ "", 49443 /* IPROCPERIPH_UART1_UART_SRBR_STHR14 */ "", 49444 /* IPROCPERIPH_UART1_UART_SRBR_STHR15 */ "", 49445 /* IPROCPERIPH_UART1_UART_SRR */ "", 49446 /* IPROCPERIPH_UART1_UART_SRT */ "", 49447 /* IPROCPERIPH_UART1_UART_SRTS */ "", 49448 /* IPROCPERIPH_UART1_UART_STET */ "", 49449 /* IPROCPERIPH_UART1_UART_TFL */ "", 49450 /* IPROCPERIPH_UART1_UART_TFR */ "", 49451 /* IPROCPERIPH_UART1_UART_UCV */ "", 49452 /* IPROCPERIPH_UART1_UART_USR */ "", 49453 /* IPROC_DDR_PLL_CTRL_REGISTER_0 */ "", 49454 /* IPROC_DDR_PLL_CTRL_REGISTER_1 */ "", 49455 /* IPROC_DDR_PLL_CTRL_REGISTER_2 */ "", 49456 /* IPROC_DDR_PLL_CTRL_REGISTER_3 */ "", 49457 /* IPROC_DDR_PLL_CTRL_REGISTER_4 */ "", 49458 /* IPROC_DDR_PLL_CTRL_REGISTER_5 */ "", 49459 /* IPROC_DDR_PLL_STATUS */ "", 49460 /* IPROC_WRAP_BSPLL0_SSC_CTRL0 */ "", 49461 /* IPROC_WRAP_BSPLL0_SSC_CTRL1 */ "", 49462 /* IPROC_WRAP_BSPLL0_SSC_STATUS */ "", 49463 /* IPROC_WRAP_BSPLL1_SSC_CTRL0 */ "", 49464 /* IPROC_WRAP_BSPLL1_SSC_CTRL1 */ "", 49465 /* IPROC_WRAP_BSPLL1_SSC_STATUS */ "", 49466 /* IPROC_WRAP_CHIP_OTP_STATUS_0_127_96 */ "", 49467 /* IPROC_WRAP_CHIP_OTP_STATUS_0_31_0 */ "", 49468 /* IPROC_WRAP_CHIP_OTP_STATUS_0_63_32 */ "", 49469 /* IPROC_WRAP_CHIP_OTP_STATUS_0_95_64 */ "", 49470 /* IPROC_WRAP_CHIP_OTP_STATUS_1_127_96 */ "", 49471 /* IPROC_WRAP_CHIP_OTP_STATUS_1_31_0 */ "", 49472 /* IPROC_WRAP_CHIP_OTP_STATUS_1_63_32 */ "", 49473 /* IPROC_WRAP_CHIP_OTP_STATUS_1_95_64 */ "", 49474 /* IPROC_WRAP_CHIP_OTP_STATUS_2_127_96 */ "", 49475 /* IPROC_WRAP_CHIP_OTP_STATUS_2_31_0 */ "", 49476 /* IPROC_WRAP_CHIP_OTP_STATUS_2_63_32 */ "", 49477 /* IPROC_WRAP_CHIP_OTP_STATUS_2_95_64 */ "", 49478 /* IPROC_WRAP_CHIP_OTP_STATUS_3_127_96 */ "", 49479 /* IPROC_WRAP_CHIP_OTP_STATUS_3_31_0 */ "", 49480 /* IPROC_WRAP_CHIP_OTP_STATUS_3_63_32 */ "", 49481 /* IPROC_WRAP_CHIP_OTP_STATUS_3_95_64 */ "", 49482 /* IPROC_WRAP_CHIP_SOTP_CTRL */ "", 49483 /* IPROC_WRAP_CHIP_SOTP_STATUS */ "", 49484 /* IPROC_WRAP_GEN_PLL_CTRL0 */ "", 49485 /* IPROC_WRAP_GEN_PLL_CTRL1 */ "", 49486 /* IPROC_WRAP_GEN_PLL_CTRL2 */ "", 49487 /* IPROC_WRAP_GEN_PLL_CTRL3 */ "", 49488 /* IPROC_WRAP_GEN_PLL_CTRL4 */ "", 49489 /* IPROC_WRAP_GEN_PLL_CTRL5 */ "", 49490 /* IPROC_WRAP_GEN_PLL_STATUS */ "", 49491 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_0 */ "", 49492 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_1 */ "", 49493 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_2 */ "", 49494 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_3 */ "", 49495 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_4 */ "", 49496 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_5 */ "", 49497 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_6 */ "", 49498 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_7 */ "", 49499 /* IPROC_WRAP_IPROC_DDR_PLL_CTRL_8 */ "", 49500 /* IPROC_WRAP_IPROC_DDR_PLL_STATUS */ "", 49501 /* IPROC_WRAP_IPROC_PLL_CTRL_0 */ "", 49502 /* IPROC_WRAP_IPROC_PLL_CTRL_1 */ "", 49503 /* IPROC_WRAP_IPROC_PLL_CTRL_2 */ "", 49504 /* IPROC_WRAP_IPROC_PLL_CTRL_3 */ "", 49505 /* IPROC_WRAP_IPROC_PLL_CTRL_4 */ "", 49506 /* IPROC_WRAP_IPROC_PLL_CTRL_5 */ "", 49507 /* IPROC_WRAP_IPROC_PLL_CTRL_6 */ "", 49508 /* IPROC_WRAP_IPROC_PLL_CTRL_7 */ "", 49509 /* IPROC_WRAP_IPROC_PLL_CTRL_8 */ "", 49510 /* IPROC_WRAP_IPROC_PLL_STATUS */ "", 49511 /* IPROC_WRAP_IPROC_STRAP_CTRL */ "", 49512 /* IPROC_WRAP_IPROC_STRAP_CTRL_0 */ "", 49513 /* IPROC_WRAP_IPROC_STRAP_CTRL_1 */ "", 49514 /* IPROC_WRAP_IPROC_XGPLL_CTRL_0 */ "", 49515 /* IPROC_WRAP_IPROC_XGPLL_CTRL_1 */ "", 49516 /* IPROC_WRAP_IPROC_XGPLL_CTRL_2 */ "", 49517 /* IPROC_WRAP_IPROC_XGPLL_CTRL_3 */ "", 49518 /* IPROC_WRAP_IPROC_XGPLL_CTRL_4 */ "", 49519 /* IPROC_WRAP_IPROC_XGPLL_CTRL_5 */ "", 49520 /* IPROC_WRAP_IPROC_XGPLL_CTRL_6 */ "", 49521 /* IPROC_WRAP_IPROC_XGPLL_CTRL_7 */ "", 49522 /* IPROC_WRAP_IPROC_XGPLL_CTRL_8 */ "", 49523 /* IPROC_WRAP_IPROC_XGPLL_STATUS */ "", 49524 /* IPROC_WRAP_LCPLL0_SSC_CTRL0 */ "", 49525 /* IPROC_WRAP_LCPLL0_SSC_CTRL1 */ "", 49526 /* IPROC_WRAP_LCPLL0_SSC_STATUS */ "", 49527 /* IPROC_WRAP_LCPLL1_SSC_CTRL0 */ "", 49528 /* IPROC_WRAP_LCPLL1_SSC_CTRL1 */ "", 49529 /* IPROC_WRAP_LCPLL1_SSC_STATUS */ "", 49530 /* IPROC_WRAP_MISC_CONTROL */ "", 49531 /* IPROC_WRAP_MISC_STATUS */ "", 49532 /* IPROC_WRAP_MISC_STATUS_0 */ "", 49533 /* IPROC_WRAP_MISC_STATUS_1 */ "", 49534 /* IPROC_WRAP_PCIE_PERST_CNT_MAX_VAL */ "", 49535 /* IPROC_WRAP_PCIE_PERST_CTRL */ "", 49536 /* IPROC_WRAP_PCIE_SERDES_CONTROL */ "", 49537 /* IPROC_WRAP_PCIE_SERDES_STATUS */ "", 49538 /* IPROC_WRAP_PERST_CNT_MAX_VAL */ "", 49539 /* IPROC_WRAP_SDIO_1P8_FAIL_CONTROL */ "", 49540 /* IPROC_WRAP_SDIO_CONTROL */ "", 49541 /* IPROC_WRAP_SDIO_CONTROL1 */ "", 49542 /* IPROC_WRAP_SDIO_CONTROL2 */ "", 49543 /* IPROC_WRAP_SDIO_CONTROL3 */ "", 49544 /* IPROC_WRAP_SDIO_CONTROL4 */ "", 49545 /* IPROC_WRAP_SDIO_CONTROL5 */ "", 49546 /* IPROC_WRAP_SDIO_IO_CTRL_STATE */ "", 49547 /* IPROC_WRAP_SDIO_PRESET_VALUE_0 */ "", 49548 /* IPROC_WRAP_SDIO_PRESET_VALUE_1 */ "", 49549 /* IPROC_WRAP_SDIO_PRESET_VALUE_2 */ "", 49550 /* IPROC_WRAP_SDIO_PRESET_VALUE_3 */ "", 49551 /* IPROC_WRAP_SECURITY_ENABLE */ "", 49552 /* IPROC_WRAP_SGMII_CTRL_REG */ "", 49553 /* IPROC_WRAP_SGMII_STATUS0_REG */ "", 49554 /* IPROC_WRAP_SGMII_STATUS1_REG */ "", 49555 /* IPROC_WRAP_SPARE_0 */ "", 49556 /* IPROC_WRAP_SPARE_1 */ "", 49557 /* IPROC_WRAP_TOP_STRAP_STATUS */ "", 49558 /* IPROC_WRAP_TOP_STRAP_STATUS_1 */ "", 49559 /* IPROC_WRAP_TS_INT_STATUS */ "", 49560 /* IPROC_WRAP_USB2_PHY_AFE_TST */ "", 49561 /* IPROC_WRAP_USBPHY_CTRL */ "", 49562 /* IPROC_WRAP_USBPHY_CTRL_0 */ "", 49563 /* IPROC_WRAP_USBPHY_CTRL_1 */ "", 49564 /* IPROC_WRAP_USBPHY_CTRL_2 */ "", 49565 /* IPROC_WRAP_USBPHY_CTRL_3 */ "", 49566 /* IPROC_WRAP_USBPHY_CTRL_4 */ "", 49567 /* IPROC_WRAP_USBPHY_CTRL_5 */ "", 49568 /* IPROC_WRAP_XGPLL_SSC_CTRL0 */ "", 49569 /* IPROC_WRAP_XGPLL_SSC_CTRL1 */ "", 49570 /* IPROC_WRAP_XGPLL_SSC_STATUS */ "", 49571 /* IPSEC_BFD_AUTHENTICATION_ERROR */ "", 49572 /* IPSEC_ECC_1B_ERR_CNT */ "", 49573 /* IPSEC_ECC_2B_ERR_CNT */ "", 49574 /* IPSEC_ECC_ERR_1B_INITIATE */ "", 49575 /* IPSEC_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 49576 /* IPSEC_ECC_ERR_2B_INITIATE */ "", 49577 /* IPSEC_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 49578 /* IPSEC_ECC_INTERRUPT_REGISTER */ "", 49579 /* IPSEC_ECC_INTERRUPT_REGISTER_MASK */ "", 49580 /* IPSEC_ECC_INTERRUPT_REGISTER_TEST */ "", 49581 /* IPSEC_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 49582 /* IPSEC_ERROR_INITIATION_DATA */ "", 49583 /* IPSEC_FRAGMENTATION_PACKET_INPUT_CNT */ "", 49584 /* IPSEC_FRG_TOO_MANY_FRAGMENTS_ERR_CNT */ "", 49585 /* IPSEC_GLOBAL_MEM_OPTIONS */ "", 49586 /* IPSEC_GLOBAL_SYS_HEADER_CFG */ "", 49587 /* IPSEC_GTIMER_CONFIGURATION */ "", 49588 /* IPSEC_INDIRECT_COMMAND */ "", 49589 /* IPSEC_INDIRECT_COMMAND_ADDRESS */ "", 49590 /* IPSEC_INDIRECT_COMMAND_DATA_INCREMENT */ "", 49591 /* IPSEC_INDIRECT_COMMAND_RD_DATA */ "", 49592 /* IPSEC_INDIRECT_COMMAND_WIDE_MEM */ "", 49593 /* IPSEC_INDIRECT_COMMAND_WR_DATA */ "", 49594 /* IPSEC_INDIRECT_FORCE_BUBBLE */ "", 49595 /* IPSEC_INTERRUPT_MASK_REGISTER */ "", 49596 /* IPSEC_INTERRUPT_REGISTER */ "", 49597 /* IPSEC_INTERRUPT_REGISTER_TEST */ "", 49598 /* IPSEC_IPSEC_AUTHENTICATION_ERROR */ "", 49599 /* IPSEC_IPSEC_INPUT_COUNTER */ "", 49600 /* IPSEC_IPSEC_OUTPUT_COUNTER */ "", 49601 /* IPSEC_PCMI_0 */ "", 49602 /* IPSEC_PCMI_1 */ "", 49603 /* IPSEC_PCMI_2 */ "", 49604 /* IPSEC_PCMI_3 */ "", 49605 /* IPSEC_PCMI_4 */ "", 49606 /* IPSEC_PCMI_0_S */ "", 49607 /* IPSEC_PCMI_0_T */ "", 49608 /* IPSEC_PCMI_1_S */ "", 49609 /* IPSEC_PCMI_1_T */ "", 49610 /* IPSEC_PCMI_2_S */ "", 49611 /* IPSEC_PCMI_2_T */ "", 49612 /* IPSEC_PCMI_3_S */ "", 49613 /* IPSEC_PCMI_3_T */ "", 49614 /* IPSEC_PCMI_4_S */ "", 49615 /* IPSEC_PCMI_4_T */ "", 49616 /* IPSEC_POST_PROCESSING_PACKET_INPUT_CNT */ "", 49617 /* IPSEC_POST_SIZE_ERROR_CNT */ "", 49618 /* IPSEC_PRGE_PACKET_INPUT_CNT */ "", 49619 /* IPSEC_REASSEMBLY_BYPASS_FIFO_MEM_ERR_CNT */ "", 49620 /* IPSEC_REASSEMBLY_CTX_0_CNT */ "", 49621 /* IPSEC_REASSEMBLY_CTX_1_CNT */ "", 49622 /* IPSEC_REASSEMBLY_CTX_2_CNT */ "", 49623 /* IPSEC_REASSEMBLY_CTX_3_CNT */ "", 49624 /* IPSEC_REASSEMBLY_CTX_4_CNT */ "", 49625 /* IPSEC_REASSEMBLY_CTX_5_CNT */ "", 49626 /* IPSEC_REASSEMBLY_CTX_6_CNT */ "", 49627 /* IPSEC_REASSEMBLY_CTX_7_CNT */ "", 49628 /* IPSEC_REASSEMBLY_CTX_FIFO_MEM_ERR_CNT */ "", 49629 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_0_CNT */ "", 49630 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_1_CNT */ "", 49631 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_2_CNT */ "", 49632 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_3_CNT */ "", 49633 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_4_CNT */ "", 49634 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_5_CNT */ "", 49635 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_6_CNT */ "", 49636 /* IPSEC_REASSEMBLY_FRG_ORDER_ERROR_CTX_7_CNT */ "", 49637 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_0_CNT */ "", 49638 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_1_CNT */ "", 49639 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_2_CNT */ "", 49640 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_3_CNT */ "", 49641 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_4_CNT */ "", 49642 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_5_CNT */ "", 49643 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_6_CNT */ "", 49644 /* IPSEC_REASSEMBLY_ID_ERROR_CTX_7_CNT */ "", 49645 /* IPSEC_REASSEMBLY_INPUT_ORDER_ERROR_CNT */ "", 49646 /* IPSEC_REASSEMBLY_IP_OPTIONS_CNT */ "", 49647 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_0_CNT */ "", 49648 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_1_CNT */ "", 49649 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_2_CNT */ "", 49650 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_3_CNT */ "", 49651 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_4_CNT */ "", 49652 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_5_CNT */ "", 49653 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_6_CNT */ "", 49654 /* IPSEC_REASSEMBLY_MIDDLE_FRG_CTX_7_CNT */ "", 49655 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_0_CNT */ "", 49656 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_1_CNT */ "", 49657 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_2_CNT */ "", 49658 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_3_CNT */ "", 49659 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_4_CNT */ "", 49660 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_5_CNT */ "", 49661 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_6_CNT */ "", 49662 /* IPSEC_REASSEMBLY_SZ_ERROR_CTX_7_CNT */ "", 49663 /* IPSEC_REG_00100 */ "", 49664 /* IPSEC_REG_0101 */ "", 49665 /* IPSEC_REG_0102 */ "", 49666 /* IPSEC_REG_0103 */ "", 49667 /* IPSEC_REG_0104 */ "", 49668 /* IPSEC_REG_0130 */ "", 49669 /* IPSEC_REG_0131 */ "", 49670 /* IPSEC_REG_0135 */ "", 49671 /* IPSEC_REG_0140 */ "", 49672 /* IPSEC_REG_0143 */ "", 49673 /* IPSEC_REG_0147 */ "", 49674 /* IPSEC_REG_0148 */ "", 49675 /* IPSEC_REG_0149 */ "", 49676 /* IPSEC_REG_0150 */ "", 49677 /* IPSEC_REG_0155 */ "", 49678 /* IPSEC_REG_0156 */ "", 49679 /* IPSEC_REG_0157 */ "", 49680 /* IPSEC_REG_0158 */ "", 49681 /* IPSEC_REG_0159 */ "", 49682 /* IPSEC_REG_012F */ "", 49683 /* IPSEC_REG_014A */ "", 49684 /* IPSEC_REG_014B */ "", 49685 /* IPSEC_REG_014C */ "", 49686 /* IPSEC_REG_014D */ "", 49687 /* IPSEC_REG_014E */ "", 49688 /* IPSEC_REG_014F */ "", 49689 /* IPSEC_REG_015A */ "", 49690 /* IPSEC_RESERVED_MIRROR_ADDR */ "", 49691 /* IPSEC_RESERVED_MTCD */ "", 49692 /* IPSEC_RESERVED_MTCP */ "", 49693 /* IPSEC_RESERVED_SPARE_0 */ "", 49694 /* IPSEC_RESERVED_SPARE_1 */ "", 49695 /* IPSEC_RESERVED_SPARE_2 */ "", 49696 /* IPSEC_RESERVED_SPARE_3 */ "", 49697 /* IPSEC_SBUS_BROADCAST_ID */ "", 49698 /* IPSEC_SBUS_LAST_IN_CHAIN */ "", 49699 /* IPSEC_SEQUENCE_ERROR_CNT */ "", 49700 /* IPSEC_SEQUENCE_NUMBER_WRAP_CNT */ "", 49701 /* IPSEC_SPU_BYPASS_FIFO_CPU_DATA */ "", 49702 /* IPSEC_SPU_CTRL_PACKET_INPUT_CNT */ "", 49703 /* IPSEC_SPU_WRAPPER_TOP_ECC_1B_ERR_CNT */ "", 49704 /* IPSEC_SPU_WRAPPER_TOP_ECC_2B_ERR_CNT */ "", 49705 /* IPSEC_SPU_WRAPPER_TOP_ECC_ERR_1B_INITIATE */ "", 49706 /* IPSEC_SPU_WRAPPER_TOP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 49707 /* IPSEC_SPU_WRAPPER_TOP_ECC_ERR_2B_INITIATE */ "", 49708 /* IPSEC_SPU_WRAPPER_TOP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 49709 /* IPSEC_SPU_WRAPPER_TOP_ECC_INTERRUPT_REGISTER */ "", 49710 /* IPSEC_SPU_WRAPPER_TOP_ECC_INTERRUPT_REGISTER_MASK */ "", 49711 /* IPSEC_SPU_WRAPPER_TOP_ECC_INTERRUPT_REGISTER_TEST */ "", 49712 /* IPSEC_SPU_WRAPPER_TOP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 49713 /* IPSEC_SPU_WRAPPER_TOP_ERROR_INITIATION_DATA */ "", 49714 /* IPSEC_SPU_WRAPPER_TOP_GLOBAL_MEM_OPTIONS */ "", 49715 /* IPSEC_SPU_WRAPPER_TOP_GTIMER_CONFIGURATION */ "", 49716 /* IPSEC_SPU_WRAPPER_TOP_INDIRECT_COMMAND */ "", 49717 /* IPSEC_SPU_WRAPPER_TOP_INDIRECT_COMMAND_ADDRESS */ "", 49718 /* IPSEC_SPU_WRAPPER_TOP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 49719 /* IPSEC_SPU_WRAPPER_TOP_INDIRECT_COMMAND_RD_DATA */ "", 49720 /* IPSEC_SPU_WRAPPER_TOP_INDIRECT_COMMAND_WIDE_MEM */ "", 49721 /* IPSEC_SPU_WRAPPER_TOP_INDIRECT_COMMAND_WR_DATA */ "", 49722 /* IPSEC_SPU_WRAPPER_TOP_INDIRECT_FORCE_BUBBLE */ "", 49723 /* IPSEC_SPU_WRAPPER_TOP_INTERRUPT_MASK_REGISTER */ "", 49724 /* IPSEC_SPU_WRAPPER_TOP_INTERRUPT_REGISTER */ "", 49725 /* IPSEC_SPU_WRAPPER_TOP_INTERRUPT_REGISTER_TEST */ "", 49726 /* IPSEC_SPU_WRAPPER_TOP_REG_0032 */ "", 49727 /* IPSEC_SPU_WRAPPER_TOP_REG_0033 */ "", 49728 /* IPSEC_SPU_WRAPPER_TOP_REG_0034 */ "", 49729 /* IPSEC_SPU_WRAPPER_TOP_REG_0035 */ "", 49730 /* IPSEC_SPU_WRAPPER_TOP_REG_0036 */ "", 49731 /* IPSEC_SPU_WRAPPER_TOP_REG_0037 */ "", 49732 /* IPSEC_SPU_WRAPPER_TOP_REG_000100 */ "", 49733 /* IPSEC_SPU_WRAPPER_TOP_REG_0101 */ "", 49734 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_MIRROR_ADDR */ "", 49735 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_MTCD */ "", 49736 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_MTCP */ "", 49737 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_MTCPRF */ "", 49738 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_0 */ "", 49739 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_1 */ "", 49740 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_2 */ "", 49741 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_3 */ "", 49742 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_4 */ "", 49743 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_0_S */ "", 49744 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_0_T */ "", 49745 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_1_S */ "", 49746 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_1_T */ "", 49747 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_2_S */ "", 49748 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_2_T */ "", 49749 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_3_S */ "", 49750 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_3_T */ "", 49751 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_4_S */ "", 49752 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_PCMI_4_T */ "", 49753 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_SPARE_0 */ "", 49754 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_SPARE_1 */ "", 49755 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_SPARE_2 */ "", 49756 /* IPSEC_SPU_WRAPPER_TOP_RESERVED_SPARE_3 */ "", 49757 /* IPSEC_SPU_WRAPPER_TOP_SBUS_BROADCAST_ID */ "", 49758 /* IPSEC_SPU_WRAPPER_TOP_SBUS_LAST_IN_CHAIN */ "", 49759 /* IPSEC_SPU_WRAPPER_TOP_SPU_RECEIVED_PACKETS_COUNTER_0 */ "", 49760 /* IPSEC_SPU_WRAPPER_TOP_SPU_RECEIVED_PACKETS_COUNTER_1 */ "", 49761 /* IPSEC_SPU_WRAPPER_TOP_SPU_RECEIVED_PACKETS_COUNTER_2 */ "", 49762 /* IPSEC_SPU_WRAPPER_TOP_SPU_RECEIVED_PACKETS_COUNTER_3 */ "", 49763 /* IPSEC_SPU_WRAPPER_TOP_SPU_RECEIVED_PACKETS_COUNTER_4 */ "", 49764 /* IPSEC_SPU_WRAPPER_TOP_SPU_RECEIVED_PACKETS_COUNTER_5 */ "", 49765 /* IPST_CREDIT_ARBITER_CONFIG */ "", 49766 /* IPST_CREDIT_ARBITER_DEBUG */ "", 49767 /* IPST_CREDIT_ARBITER_DROPS_CNT */ "", 49768 /* IPST_CREDIT_ARBITER_EIR_REJECT */ "", 49769 /* IPST_CREDIT_ARBITER_IPS_0_CNT */ "", 49770 /* IPST_CREDIT_ARBITER_IPS_1_CNT */ "", 49771 /* IPST_CREDIT_CONFIG_1 */ "", 49772 /* IPST_CREDIT_MSG_ERROR */ "", 49773 /* IPST_DBG_1_AVERAGE */ "", 49774 /* IPST_DBG_1_HIST_BIN_0 */ "", 49775 /* IPST_DBG_1_HIST_BIN_1 */ "", 49776 /* IPST_DBG_1_HIST_BIN_2 */ "", 49777 /* IPST_DBG_1_HIST_BIN_3 */ "", 49778 /* IPST_DBG_1_HIST_BIN_4 */ "", 49779 /* IPST_DBG_1_HIST_THRESHOLDS */ "", 49780 /* IPST_DBG_1_HIST_VALID */ "", 49781 /* IPST_DBG_1_MIN_MAX */ "", 49782 /* IPST_DBG_2_AVERAGE */ "", 49783 /* IPST_DBG_2_HIST_BIN_0 */ "", 49784 /* IPST_DBG_2_HIST_BIN_1 */ "", 49785 /* IPST_DBG_2_HIST_BIN_2 */ "", 49786 /* IPST_DBG_2_HIST_BIN_3 */ "", 49787 /* IPST_DBG_2_HIST_BIN_4 */ "", 49788 /* IPST_DBG_2_HIST_THRESHOLDS */ "", 49789 /* IPST_DBG_2_HIST_VALID */ "", 49790 /* IPST_DBG_2_MIN_MAX */ "", 49791 /* IPST_DBG_CONFIG_1 */ "", 49792 /* IPST_DBG_LATENCY_CFG */ "", 49793 /* IPST_DBG_LATENCY_FSM_CFG_1 */ "", 49794 /* IPST_DBG_LATENCY_FSM_CFG_2 */ "", 49795 /* IPST_DBG_LATENCY_FSM_CFG_3 */ "", 49796 /* IPST_DBG_LATENCY_STATUS_1 */ "", 49797 /* IPST_DBG_LATENCY_STATUS_2 */ "", 49798 /* IPST_ECC_1B_ERR_CNT */ "", 49799 /* IPST_ECC_2B_ERR_CNT */ "", 49800 /* IPST_ECC_ERR_1B_INITIATE */ "", 49801 /* IPST_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 49802 /* IPST_ECC_ERR_2B_INITIATE */ "", 49803 /* IPST_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 49804 /* IPST_ECC_INTERRUPT_REGISTER */ "", 49805 /* IPST_ECC_INTERRUPT_REGISTER_MASK */ "", 49806 /* IPST_ECC_INTERRUPT_REGISTER_TEST */ "", 49807 /* IPST_EIR_CREDIT_ARBITER_DROPS_CNT */ "", 49808 /* IPST_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 49809 /* IPST_ERROR_INITIATION_DATA */ "", 49810 /* IPST_FCT_NRDY_CNT */ "", 49811 /* IPST_FMC_IPS_WFQ_CONFIG */ "", 49812 /* IPST_FMC_TOP_SHAPER_CONFIG */ "", 49813 /* IPST_FSM_ARBITER_CONFIG */ "", 49814 /* IPST_FSM_GEN_CNT */ "", 49815 /* IPST_FSM_GEN_CONFIG_1 */ "", 49816 /* IPST_FSM_GEN_CONFIG_2 */ "", 49817 /* IPST_FSM_GEN_CONFIG_3 */ "", 49818 /* IPST_FSM_GEN_CONFIG_4 */ "", 49819 /* IPST_FSM_GEN_CONFIG_5 */ "", 49820 /* IPST_FSM_GEN_CONFIG_6 */ "", 49821 /* IPST_FSM_IPS_0_CNT */ "", 49822 /* IPST_FSM_IPS_1_CNT */ "", 49823 /* IPST_GLOBAL_FMC_0 */ "", 49824 /* IPST_GLOBAL_FMC_1 */ "", 49825 /* IPST_GLOBAL_GENERAL_CFG_2 */ "", 49826 /* IPST_GLOBAL_ISP_0 */ "", 49827 /* IPST_GLOBAL_ISP_1 */ "", 49828 /* IPST_GLOBAL_MEM_OPTIONS */ "", 49829 /* IPST_GTIMER_CONFIGURATION */ "", 49830 /* IPST_GTIMER_TRIGGER */ "", 49831 /* IPST_INDIRECT_COMMAND */ "", 49832 /* IPST_INDIRECT_COMMAND_ADDRESS */ "", 49833 /* IPST_INDIRECT_COMMAND_DATA_INCREMENT */ "", 49834 /* IPST_INDIRECT_COMMAND_RD_DATA */ "", 49835 /* IPST_INDIRECT_COMMAND_WIDE_MEM */ "", 49836 /* IPST_INDIRECT_COMMAND_WR_DATA */ "", 49837 /* IPST_INDIRECT_FORCE_BUBBLE */ "", 49838 /* IPST_INTERRUPT_MASK_REGISTER */ "", 49839 /* IPST_INTERRUPT_REGISTER */ "", 49840 /* IPST_INTERRUPT_REGISTER_TEST */ "", 49841 /* IPST_IRR_FLOW_CONTROL_CONFIG */ "", 49842 /* IPST_RESERVED_MIRROR_ADDR */ "", 49843 /* IPST_RESERVED_MTCD */ "", 49844 /* IPST_RESERVED_MTCP */ "", 49845 /* IPST_RESERVED_PCMI_0 */ "", 49846 /* IPST_RESERVED_PCMI_1 */ "", 49847 /* IPST_RESERVED_PCMI_2 */ "", 49848 /* IPST_RESERVED_PCMI_3 */ "", 49849 /* IPST_RESERVED_PCMI_4 */ "", 49850 /* IPST_RESERVED_PCMI_0_S */ "", 49851 /* IPST_RESERVED_PCMI_0_T */ "", 49852 /* IPST_RESERVED_PCMI_1_S */ "", 49853 /* IPST_RESERVED_PCMI_1_T */ "", 49854 /* IPST_RESERVED_PCMI_2_S */ "", 49855 /* IPST_RESERVED_PCMI_2_T */ "", 49856 /* IPST_RESERVED_PCMI_3_S */ "", 49857 /* IPST_RESERVED_PCMI_3_T */ "", 49858 /* IPST_RESERVED_PCMI_4_S */ "", 49859 /* IPST_RESERVED_PCMI_4_T */ "", 49860 /* IPST_RESERVED_SPARE_0 */ "", 49861 /* IPST_RESERVED_SPARE_1 */ "", 49862 /* IPST_RESERVED_SPARE_2 */ "", 49863 /* IPST_RESERVED_SPARE_3 */ "", 49864 /* IPST_SBUS_BROADCAST_ID */ "", 49865 /* IPST_SBUS_LAST_IN_CHAIN */ "", 49866 /* IPS_ACTIVATE_TIMER */ "", 49867 /* IPS_ACTIVE_PUSH_QUEUE_ID */ "", 49868 /* IPS_ACTIVE_PUSH_QUEUE_QNUM */ "", 49869 /* IPS_ACTIVE_QUEUE_COUNT */ "", 49870 /* IPS_ACTIVE_QUEUE_COUNT_ERR_INTERRUPT_REGISTER */ "", 49871 /* IPS_ACTIVE_QUEUE_COUNT_ERR_INTERRUPT_REGISTER_MASK */ "", 49872 /* IPS_ACTIVE_QUEUE_COUNT_ERR_INTERRUPT_REGISTER_TEST */ "", 49873 /* IPS_AUTO_CREDIT_MECHANISM_FIRST_QUEUE */ "", 49874 /* IPS_AUTO_CREDIT_MECHANISM_LAST_QUEUE */ "", 49875 /* IPS_AUTO_CREDIT_MECHANISM_RANGE */ "", 49876 /* IPS_AUTO_CREDIT_MECHANISM_RATE */ "", 49877 /* IPS_AUTO_CREDIT_MECHANISM_RATE_CONFIGURATION */ "", 49878 /* IPS_AUTO_DOC_NAME_2 */ "", 49879 /* IPS_AUTO_DOC_NAME_12 */ "", 49880 /* IPS_AUTO_DOC_NAME_23 */ "", 49881 /* IPS_AUTO_DOC_NAME_25 */ "", 49882 /* IPS_AUTO_DOC_NAME_28 */ "", 49883 /* IPS_AUTO_DOC_NAME_31 */ "", 49884 /* IPS_AUTO_DOC_NAME_45 */ "", 49885 /* IPS_AUTO_DOC_NAME_46 */ "", 49886 /* IPS_AUTO_DOC_NAME_47 */ "", 49887 /* IPS_AUTO_DOC_NAME_50 */ "", 49888 /* IPS_AUTO_DOC_NAME_52 */ "", 49889 /* IPS_AVOID_CAM_OVERFLOW */ "", 49890 /* IPS_AVOID_DRAM_CAM_FULL */ "", 49891 /* IPS_AVOID_FABRIC_CAM_FULL */ "", 49892 /* IPS_BFMC_1_CREDIT_COUNTER */ "", 49893 /* IPS_BFMC_2_CREDIT_COUNTER */ "", 49894 /* IPS_BFMC_3_CREDIT_COUNTER */ "", 49895 /* IPS_BFMC_CLASS_CONFIG */ "", 49896 /* IPS_BFMC_CLASS_CONFIGS */ "", 49897 /* IPS_BFMC_SHAPER_CONFIG */ "", 49898 /* IPS_BFMC_SHAPER_CONFIGS */ "", 49899 /* IPS_CAMFULL_DRAM_TO_FABRIC_DURATION_COUNT */ "", 49900 /* IPS_CAMFULL_SRAM_TO_FABRIC_DURATION_COUNT */ "", 49901 /* IPS_CAM_CURRENT_ENTRIES */ "", 49902 /* IPS_CAM_MAX_ENTRIES */ "", 49903 /* IPS_CAM_OVERFLOW_DEBUG */ "", 49904 /* IPS_CAPTURE_QUEUE_DESCRIPTOR */ "", 49905 /* IPS_CAPTURE_QUEUE_DESCRIPTOR_CONFIG */ "", 49906 /* IPS_CGM_REPORT_FILTER */ "", 49907 /* IPS_CIR_FC_CONFIG */ "", 49908 /* IPS_COMB_CIR_FLOW_CONTROL_TH_0 */ "", 49909 /* IPS_COMB_CIR_FLOW_CONTROL_TH_1 */ "", 49910 /* IPS_COMB_CIR_FLOW_CONTROL_TH_2 */ "", 49911 /* IPS_COMB_CIR_FLOW_CONTROL_TH_3 */ "", 49912 /* IPS_COMB_CIR_FLOW_CONTROL_TH_SEL */ "", 49913 /* IPS_COMB_EIR_CONFIG */ "", 49914 /* IPS_COMB_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_0 */ "", 49915 /* IPS_COMB_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_1 */ "", 49916 /* IPS_COMB_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_2 */ "", 49917 /* IPS_COMB_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_3 */ "", 49918 /* IPS_COMB_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_SEL */ "", 49919 /* IPS_CPTRD_EVENT_TRIGGER */ "", 49920 /* IPS_CPTRD_QUEUE_TRIGGER */ "", 49921 /* IPS_CRBAL_OVERFLOW_QNUM */ "", 49922 /* IPS_CRDT_FLOW_ID_CHECK */ "", 49923 /* IPS_CRDT_FLOW_ID_ERR_CAPTURE */ "", 49924 /* IPS_CRDT_FLOW_ID_ERR_CTR */ "", 49925 /* IPS_CRDT_LTNCY_CTR */ "", 49926 /* IPS_CRDT_LTNCY_QNUM */ "", 49927 /* IPS_CRDT_WD_CURRENT_TIME */ "", 49928 /* IPS_CRDT_WD_EVNT_CTR */ "", 49929 /* IPS_CRDT_WD_SCAN_RANGE */ "", 49930 /* IPS_CREDIT_BALANCE_RESOLUTION_REGISTER */ "", 49931 /* IPS_CREDIT_CONFIG */ "", 49932 /* IPS_CREDIT_DISCARD_COUNTER */ "", 49933 /* IPS_CREDIT_FABRIC_LATENCY_COUNTER */ "", 49934 /* IPS_CREDIT_FABRIC_LATENCY_COUNTER_CONFIG */ "", 49935 /* IPS_CREDIT_OVERFLOW_QUEUE_NUM */ "", 49936 /* IPS_CREDIT_VALUE_CONFIG */ "", 49937 /* IPS_CREDIT_VALUE_SELECT_CONFIGURATION */ "", 49938 /* IPS_CREDIT_WATCHDOG_CONFIGURATION */ "", 49939 /* IPS_CREDIT_WATCHDOG_CURRENT_TIME */ "", 49940 /* IPS_CRWD_EVENT_COUNTER */ "", 49941 /* IPS_CR_FLW_ID_VERIFY_1 */ "", 49942 /* IPS_CR_FLW_ID_VERIFY_2 */ "", 49943 /* IPS_CR_FLW_ID_VERIFY_3 */ "", 49944 /* IPS_CR_WD_BOTTOM_Q */ "", 49945 /* IPS_CR_WD_TOP_Q */ "", 49946 /* IPS_DEBUG_CONFIGURATIONS */ "", 49947 /* IPS_DEBUG_FILTER */ "", 49948 /* IPS_DELETED_CRDT_CTR */ "", 49949 /* IPS_DELETED_CREDIT_COUNTER */ "", 49950 /* IPS_DEL_QNUM */ "", 49951 /* IPS_DEL_QUEUE_NUMBER */ "", 49952 /* IPS_DEQ_CMD_BYTE_COUNTER */ "", 49953 /* IPS_DEQ_CMD_COUNTER */ "", 49954 /* IPS_DEQ_CMD_DRAM_TO_FABRIC_CRDT_ADJUST */ "", 49955 /* IPS_DEQ_CMD_SRAM_TO_DRAM_CRDT_ADJUST */ "", 49956 /* IPS_DEQ_CMD_SRAM_TO_FABRIC_CRDT_ADJUST */ "", 49957 /* IPS_DEQ_CMD_TIMEOUT_QUEUE_NUM */ "", 49958 /* IPS_DEQ_COMMAND_CREDIT_ADJUST */ "", 49959 /* IPS_DEQ_COMMAND_TIMEOUT_CONFIGURATION */ "", 49960 /* IPS_DEV_ID_MASK */ "", 49961 /* IPS_DEV_ID_TO_CONTEXT_MAP */ "", 49962 /* IPS_DISCARD_CRDT_CTR */ "", 49963 /* IPS_DQCQ_BYTES_CNT_0 */ "", 49964 /* IPS_DQCQ_BYTES_CNT_1 */ "", 49965 /* IPS_DQCQ_BYTES_CNT_2 */ "", 49966 /* IPS_DQCQ_BYTES_CNT_3 */ "", 49967 /* IPS_DQCQ_BYTES_CNT_4 */ "", 49968 /* IPS_DQCQ_BYTES_CNT_5 */ "", 49969 /* IPS_DQCQ_CIR_ONLY_STATUS */ "", 49970 /* IPS_DQCQ_DEPTH_CONFIG_0 */ "", 49971 /* IPS_DQCQ_DEPTH_CONFIG_1 */ "", 49972 /* IPS_DQCQ_DEPTH_CONFIG_2 */ "", 49973 /* IPS_DQCQ_DEPTH_CONFIG_3 */ "", 49974 /* IPS_DQCQ_DEPTH_CONFIG_4 */ "", 49975 /* IPS_DQCQ_DEPTH_CONFIG_5 */ "", 49976 /* IPS_DQCQ_EIR_FC_BYTES_TH */ "", 49977 /* IPS_DQCQ_EIR_FC_MASK_SETTINGS */ "", 49978 /* IPS_DQCQ_EIR_FC_STATUS */ "", 49979 /* IPS_DQCQ_EIR_FC_TH */ "", 49980 /* IPS_DQCQ_FMC_FC_STATUS */ "", 49981 /* IPS_DQCQ_FMC_FC_TH */ "", 49982 /* IPS_DQCQ_ID_FILTER */ "", 49983 /* IPS_DQCQ_IPT_FC_STATUS */ "", 49984 /* IPS_DQCQ_IPT_HP_FC_STOP_LP */ "", 49985 /* IPS_DQCQ_MAX_OCCUPANCY_HP */ "", 49986 /* IPS_DQCQ_MAX_OCCUPANCY_LP */ "", 49987 /* IPS_DQCQ_MAX_OCCUPANCY_SEL */ "", 49988 /* IPS_DQCQ_QUEUE_COUNT */ "", 49989 /* IPS_DQCQ_SCHEDULING_CONFIG_1 */ "", 49990 /* IPS_DQCQ_SCHEDULING_CONFIG_2 */ "", 49991 /* IPS_DQCQ_SCHEDULING_CONFIG_3 */ "", 49992 /* IPS_DQCQ_STATUS_0 */ "", 49993 /* IPS_DQCQ_STATUS_1 */ "", 49994 /* IPS_DQCQ_STATUS_2 */ "", 49995 /* IPS_DQCQ_STATUS_3 */ "", 49996 /* IPS_DQCQ_STATUS_4 */ "", 49997 /* IPS_DQCQ_STATUS_5 */ "", 49998 /* IPS_DQM_ACTIVE_QUEUE_COUNT */ "", 49999 /* IPS_DQM_ACTIVE_QUEUE_COUNT_A */ "", 50000 /* IPS_DQM_ACTIVE_QUEUE_COUNT_B */ "", 50001 /* IPS_DQM_ACTIVE_QUEUE_COUNT_C */ "", 50002 /* IPS_DQM_ACTIVE_QUEUE_COUNT_D */ "", 50003 /* IPS_DQM_DEQ_CMD_BYTES_CTR */ "", 50004 /* IPS_DQM_DEQ_CMD_CTR */ "", 50005 /* IPS_DQM_DEQ_EVNT_CTR */ "", 50006 /* IPS_DQM_DQCQ_DEPTH_CONFIG */ "", 50007 /* IPS_DQM_DQCQ_ERR_STATUS */ "", 50008 /* IPS_DQM_DQCQ_STATUS */ "", 50009 /* IPS_DQM_ENQ_EVNT_CTR */ "", 50010 /* IPS_DQM_HP_DQCQ_MAX_OCCUPANCY */ "", 50011 /* IPS_DQM_LP_DQCQ_MAX_OCCUPANCY */ "", 50012 /* IPS_DQM_MAX_DEQ_CMD_CRDT */ "", 50013 /* IPS_DQM_MAX_DEQ_CMD_CRDT_SEL */ "", 50014 /* IPS_DQM_MAX_DEQ_CMD_CRDT_TH */ "", 50015 /* IPS_DQM_NRDY_CNT */ "", 50016 /* IPS_DRAM_FMC_CREDIT_FLOW_CONTROL_THRESHOLD_1 */ "", 50017 /* IPS_DRAM_FMC_CREDIT_FLOW_CONTROL_THRESHOLD_2 */ "", 50018 /* IPS_DRAM_ONLY */ "", 50019 /* IPS_DRAM_ONLY_QUEUE_TYPE */ "", 50020 /* IPS_DRAM_TO_FABRIC_CAM_FULL_FIFO_STATUS */ "", 50021 /* IPS_DRAM_TO_FABRIC_COUNTERS_PER_QUEUE */ "", 50022 /* IPS_DRAM_TO_FABRIC_DURATION_COUNT */ "", 50023 /* IPS_DRAM_TO_FABRIC_FIFO_STATUS */ "", 50024 /* IPS_D_DEQ_CMD_COUNTER */ "", 50025 /* IPS_D_DQCQ_BYTES_CNT_HP */ "", 50026 /* IPS_D_DQCQ_BYTES_CNT_LP */ "", 50027 /* IPS_D_DQCQ_DEPTH_CONFIG */ "", 50028 /* IPS_D_DQCQ_ID_FILTER */ "", 50029 /* IPS_D_DQCQ_MAX_OCCUPANCY_HP */ "", 50030 /* IPS_D_DQCQ_MAX_OCCUPANCY_LP */ "", 50031 /* IPS_D_DQCQ_QUEUE_COUNT */ "", 50032 /* IPS_D_DQCQ_STATUS_HP */ "", 50033 /* IPS_D_DQCQ_STATUS_LP */ "", 50034 /* IPS_ECC_1B_ERR_CNT */ "", 50035 /* IPS_ECC_2B_ERR_CNT */ "", 50036 /* IPS_ECC_ERR_1B_INITIATE */ "", 50037 /* IPS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 50038 /* IPS_ECC_ERR_2B_INITIATE */ "", 50039 /* IPS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 50040 /* IPS_ECC_INTERRUPT_REGISTER */ "", 50041 /* IPS_ECC_INTERRUPT_REGISTER_MASK */ "", 50042 /* IPS_ECC_INTERRUPT_REGISTER_TEST */ "", 50043 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_0 */ "", 50044 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_1 */ "", 50045 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_2 */ "", 50046 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_3 */ "", 50047 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_0_D */ "", 50048 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_0_S */ "", 50049 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_1_D */ "", 50050 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_1_S */ "", 50051 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_2_D */ "", 50052 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_2_S */ "", 50053 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_3_D */ "", 50054 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_3_S */ "", 50055 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_SEL */ "", 50056 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_SEL_D */ "", 50057 /* IPS_EIR_BYTE_FLOW_CONTROL_TH_SEL_S */ "", 50058 /* IPS_EIR_CRDT_RJCT_BYTES_TH_SEL */ "", 50059 /* IPS_EIR_CRDT_RJCT_TH_SEL_SETTINGS */ "", 50060 /* IPS_EIR_CREDIT_REJECT_CONFIG */ "", 50061 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_THRESHOLD */ "", 50062 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_0 */ "", 50063 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_1 */ "", 50064 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_2 */ "", 50065 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_3 */ "", 50066 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_0_D */ "", 50067 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_0_S */ "", 50068 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_1_D */ "", 50069 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_1_S */ "", 50070 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_2_D */ "", 50071 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_2_S */ "", 50072 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_3_D */ "", 50073 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_3_S */ "", 50074 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_SEL */ "", 50075 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_SEL_D */ "", 50076 /* IPS_EIR_CREDIT_REJECT_FLOW_CONTROL_TH_SEL_S */ "", 50077 /* IPS_EIR_FC_BUNDLE */ "", 50078 /* IPS_EIR_FC_SETTINGS */ "", 50079 /* IPS_EIR_REJ_STATUS */ "", 50080 /* IPS_EMPTY_DQCQ_ID */ "", 50081 /* IPS_EMPTY_D_DQCQ_ID */ "", 50082 /* IPS_EMPTY_S_DQCQ_ID */ "", 50083 /* IPS_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 50084 /* IPS_ENQ_BLOCK_OVERFLOW_QNUM */ "", 50085 /* IPS_ERROR_INITIATION_DATA */ "", 50086 /* IPS_EXTEND_FORCE_BUBBLE */ "", 50087 /* IPS_FCR_CRDT_EVNT_CTR */ "", 50088 /* IPS_FCR_CREDIT_COUNTER */ "", 50089 /* IPS_FILTER_SQM_DEQ_ZERO_QSZ_UPDATE_EVNTS_COUNTER */ "", 50090 /* IPS_FILTER_SQM_ENQ_ZERO_QSZ_EVNTS_COUNTER */ "", 50091 /* IPS_FLOW_CONTROL_COUNTER */ "", 50092 /* IPS_FLOW_CONTROL_COUNT_SELECT */ "", 50093 /* IPS_FLOW_CONTROL_INDICATION_1 */ "", 50094 /* IPS_FLOW_CONTROL_INDICATION_2 */ "", 50095 /* IPS_FLOW_STATUS_FILTER */ "", 50096 /* IPS_FLOW_STATUS_FILTER_MASK */ "", 50097 /* IPS_FMC_BFMC_0_CRDT_CTR */ "", 50098 /* IPS_FMC_BFMC_1_CRDT_CTR */ "", 50099 /* IPS_FMC_BFMC_2_CRDT_CTR */ "", 50100 /* IPS_FMC_BFMC_RTRN_CRDT_CTR */ "", 50101 /* IPS_FMC_CLASS_MAPPING */ "", 50102 /* IPS_FMC_CREDIT_CNT_0 */ "", 50103 /* IPS_FMC_CREDIT_CNT_2 */ "", 50104 /* IPS_FMC_CREDIT_CNT_3 */ "", 50105 /* IPS_FMC_CREDIT_COUNTER_1 */ "", 50106 /* IPS_FMC_CREDIT_FLOW_CONTROL_THRESHOLD */ "", 50107 /* IPS_FMC_CREDIT_FLOW_CONTROL_THRESHOLD_1 */ "", 50108 /* IPS_FMC_CREDIT_FLOW_CONTROL_THRESHOLD_2 */ "", 50109 /* IPS_FMC_DQCQ_FLOW_CONTROL_CONFIG */ "", 50110 /* IPS_FMC_FC_BYTES_TH */ "", 50111 /* IPS_FMC_FC_BYTES_TH_SEL */ "", 50112 /* IPS_FMC_FC_TH_SEL */ "", 50113 /* IPS_FMC_GFMC_CRDT_CTR */ "", 50114 /* IPS_FMC_GFMC_RTRN_CRDT_CTR */ "", 50115 /* IPS_FMC_QNUM_RANGE */ "", 50116 /* IPS_FMC_RETURN_CREDIT_BFMC */ "", 50117 /* IPS_FMC_RETURN_CREDIT_GFMC */ "", 50118 /* IPS_FMC_SCHEDULER_CONFIGS */ "", 50119 /* IPS_FMC_SHAPER_CONFIG */ "", 50120 /* IPS_FMC_TOP_MAX_BURST_CONFIG */ "", 50121 /* IPS_FMC_TOP_SHAPER_CONFIG */ "", 50122 /* IPS_FMS_DELAY_COUNTER */ "", 50123 /* IPS_FMS_DELAY_COUNTER_CONFIGS */ "", 50124 /* IPS_FMS_DELAY_CTR */ "", 50125 /* IPS_FMS_DELAY_CTR_CONFIGS */ "", 50126 /* IPS_FMS_FLOW_STATUS_COUNTER */ "", 50127 /* IPS_FMS_FSM_STAMP_CONFIGURATION */ "", 50128 /* IPS_FMS_MAX_OCCUPANCY */ "", 50129 /* IPS_FMS_PARAMETERS */ "", 50130 /* IPS_FORCE_DQCQ_FC */ "", 50131 /* IPS_FORCE_FABRIC */ "", 50132 /* IPS_FORCE_LOCAL */ "", 50133 /* IPS_FSMRQ_DELAY_COUNTER */ "", 50134 /* IPS_FSMRQ_DELAY_COUNTER_CONFIGS */ "", 50135 /* IPS_FSMRQ_DELAY_CTR */ "", 50136 /* IPS_FSMRQ_DELAY_CTR_SETTINGS */ "", 50137 /* IPS_FSMRQ_FLOW_STATUS_COUNTER */ "", 50138 /* IPS_FSMRQ_FLOW_STATUS_CTR */ "", 50139 /* IPS_FSMRQ_MAX_DELAY_CTR */ "", 50140 /* IPS_FSMRQ_MAX_OCCUPANCY */ "", 50141 /* IPS_FSMRQ_REQ_QUEUES */ "", 50142 /* IPS_FSMRQ_STATUS */ "", 50143 /* IPS_FSM_ARBITER_SN */ "", 50144 /* IPS_FSM_EVNT_CTR */ "", 50145 /* IPS_FSM_FIFO_SETTINGS */ "", 50146 /* IPS_FSM_HP_FIFO_MAX_STATUS */ "", 50147 /* IPS_FSM_HP_FIFO_STATUS */ "", 50148 /* IPS_FSM_LP_FIFO_MAX_STATUS */ "", 50149 /* IPS_FSM_LP_FIFO_STATUS */ "", 50150 /* IPS_FSM_ON_MESSAGE_SHAPER */ "", 50151 /* IPS_FSM_SN_CNT */ "", 50152 /* IPS_FSM_STAMP_CONFIGURATION */ "", 50153 /* IPS_GFMC_CREDIT_COUNTER */ "", 50154 /* IPS_GFMC_SHAPER_CONFIG */ "", 50155 /* IPS_GFMC_SHAPER_CONFIGS */ "", 50156 /* IPS_GLBL_CRDT_EVNT_CTR */ "", 50157 /* IPS_GLBL_FLOW_STATUS_CTR */ "", 50158 /* IPS_GLBL_QM_EVNT_CTR */ "", 50159 /* IPS_GLBL_TX_FLOW_STATUS_CTR */ "", 50160 /* IPS_GLOBAL_CREDIT_COUNTER */ "", 50161 /* IPS_GLOBAL_DQCQ_MAP_CFG_1 */ "", 50162 /* IPS_GLOBAL_DQCQ_MAP_CFG_2 */ "", 50163 /* IPS_GLOBAL_DQM_REPORT_COUNTER */ "", 50164 /* IPS_GLOBAL_FLOW_STATUS_COUNTER */ "", 50165 /* IPS_GLOBAL_GENERAL_CFG_1 */ "", 50166 /* IPS_GLOBAL_GENERAL_CFG_2 */ "", 50167 /* IPS_GLOBAL_GENERAL_CFG_4 */ "", 50168 /* IPS_GLOBAL_IQM_REPORT_COUNTER */ "", 50169 /* IPS_GLOBAL_MEM_OPTIONS */ "", 50170 /* IPS_GLOBAL_ONE_PLUS_ONE_PORT_PROTECTION */ "", 50171 /* IPS_GLOBAL_SQM_REPORT_COUNTER */ "", 50172 /* IPS_GTIMER_CONFIGURATION */ "", 50173 /* IPS_GTIMER_CYCLE */ "", 50174 /* IPS_GTIMER_TRIGGER */ "", 50175 /* IPS_HIGH_PRIORITY_DQCQ_DEPTH_CONFIG_1 */ "", 50176 /* IPS_HIGH_PRIORITY_DQCQ_DEPTH_CONFIG_2 */ "", 50177 /* IPS_HIGH_QSIZE_IN_DQM_DQCQ_FC_SETTINGS */ "", 50178 /* IPS_HIGH_QSIZE_IN_DQM_DQCQ_FC_STATUS */ "", 50179 /* IPS_HIGH_QSIZE_IN_SQM_DQCQ_FC_SETTINGS */ "", 50180 /* IPS_HIGH_QSIZE_IN_SQM_DQCQ_FC_STATUS */ "", 50181 /* IPS_HP_DQCQ_DEQ_SCHEDULING_SETTINGS */ "", 50182 /* IPS_INDIRECT_COMMAND */ "", 50183 /* IPS_INDIRECT_COMMAND_ADDRESS */ "", 50184 /* IPS_INDIRECT_COMMAND_DATA_INCREMENT */ "", 50185 /* IPS_INDIRECT_COMMAND_RD_DATA */ "", 50186 /* IPS_INDIRECT_COMMAND_WIDE_MEM */ "", 50187 /* IPS_INDIRECT_COMMAND_WR_DATA */ "", 50188 /* IPS_INDIRECT_FORCE_BUBBLE */ "", 50189 /* IPS_INGRESS_SHAPE_DEQ_CONFIG */ "", 50190 /* IPS_INGRESS_SHAPE_SCHEDULER_CONFIG */ "", 50191 /* IPS_INS_CRDT_LTNCY_CTR */ "", 50192 /* IPS_INS_CREDIT_FABRIC_LATENCY_COUNTER */ "", 50193 /* IPS_INS_FMS_DELAY_COUNTER */ "", 50194 /* IPS_INS_FMS_DELAY_CTR */ "", 50195 /* IPS_INS_FSMRQ_DELAY_COUNTER */ "", 50196 /* IPS_INTERDIGITATED_MODE */ "", 50197 /* IPS_INTERRUPT_MASK_REGISTER */ "", 50198 /* IPS_INTERRUPT_REGISTER */ "", 50199 /* IPS_INTERRUPT_REGISTER_TEST */ "", 50200 /* IPS_INT_LP_DQCQ_FC_CONFIG */ "", 50201 /* IPS_INT_LP_DQCQ_FC_STATUS */ "", 50202 /* IPS_INT_LP_D_DQCQ_FC_CONFIG */ "", 50203 /* IPS_INT_LP_D_DQCQ_FC_STATUS */ "", 50204 /* IPS_INT_LP_S_DQCQ_FC_CONFIG */ "", 50205 /* IPS_INT_LP_S_DQCQ_FC_STATUS */ "", 50206 /* IPS_IPS_CREDIT_CONFIG */ "", 50207 /* IPS_IPS_CREDIT_CONFIG_1 */ "", 50208 /* IPS_IPS_CREDIT_CONFIG_2 */ "", 50209 /* IPS_IPS_CREDIT_CONFIG_3 */ "", 50210 /* IPS_IPS_CREDIT_CONFIG_4 */ "", 50211 /* IPS_IPS_GENERAL_CONFIGURATIONS */ "", 50212 /* IPS_IPS_REG_0 */ "", 50213 /* IPS_IPS_REG_1 */ "", 50214 /* IPS_IPS_REG_2 */ "", 50215 /* IPS_IPS_REG_3 */ "", 50216 /* IPS_IPT_FLOW_CONTROL_CONFIGURATION */ "", 50217 /* IPS_IPT_PDQ_EIR_FC_STATUS */ "", 50218 /* IPS_IQM_NRDY_CNT */ "", 50219 /* IPS_IQM_REPORT_FILTER */ "", 50220 /* IPS_IS_CREDIT_FLOW_CONTROL_THRESHOLD */ "", 50221 /* IPS_LATENCY_CAMFULL_DRAM_TO_FABRIC */ "", 50222 /* IPS_LATENCY_CAMFULL_SRAM_TO_FABRIC */ "", 50223 /* IPS_LATENCY_DRAM_TO_FABRIC */ "", 50224 /* IPS_LATENCY_SRAM_TO_FABRIC */ "", 50225 /* IPS_LCL_CRDT_EVNT_CTR */ "", 50226 /* IPS_LOST_CRDT_CTR */ "", 50227 /* IPS_LOST_CRDT_STATUS */ "", 50228 /* IPS_LOST_CREDIT_COUNTER */ "", 50229 /* IPS_LOST_CREDIT_QUEUE_NUMBER */ "", 50230 /* IPS_LOST_FMC_CRDT_CTR */ "", 50231 /* IPS_LOST_FMC_CREDIT_COUNTER */ "", 50232 /* IPS_LOW_PRIORITY_DQCQ_DEPTH_CONFIG_1 */ "", 50233 /* IPS_LOW_PRIORITY_DQCQ_DEPTH_CONFIG_2 */ "", 50234 /* IPS_LOW_PRIORITY_DQCQ_DEPTH_CONFIG_3 */ "", 50235 /* IPS_LOW_PRIORITY_DQCQ_DEPTH_CONFIG_4 */ "", 50236 /* IPS_MANUAL_OPERATION_QNUM */ "", 50237 /* IPS_MANUAL_QUEUE_OPERATION */ "", 50238 /* IPS_MANUAL_QUEUE_OPERATION_QUEUE_ID */ "", 50239 /* IPS_MASKED_IQM_EVENT_COUNTER */ "", 50240 /* IPS_MAX_ACTIVE_QUEUE_COUNT */ "", 50241 /* IPS_MAX_CAMFULL_DRAM_TO_FABRIC_DURATION_COUNT */ "", 50242 /* IPS_MAX_CAMFULL_SRAM_TO_FABRIC_DURATION_COUNT */ "", 50243 /* IPS_MAX_COUNT_PER_QUEUE */ "", 50244 /* IPS_MAX_CRBAL */ "", 50245 /* IPS_MAX_CR_BAL */ "", 50246 /* IPS_MAX_CR_BAL_QUEUE */ "", 50247 /* IPS_MAX_DEQ_COMMAND_CREDIT_CONFIG */ "", 50248 /* IPS_MAX_DEQ_COMMAND_CREDIT_CONFIG_2 */ "", 50249 /* IPS_MAX_DEQ_COMMAND_CREDIT_SELECTION */ "", 50250 /* IPS_MAX_DEQ_COMMAND_DQCQ_BASED_THRESHOLDS */ "", 50251 /* IPS_MAX_DQCQ_QUEUE_COUNT */ "", 50252 /* IPS_MAX_DQM_ACTIVE_QUEUE_COUNT */ "", 50253 /* IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_A */ "", 50254 /* IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_B */ "", 50255 /* IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_C */ "", 50256 /* IPS_MAX_DQM_ACTIVE_QUEUE_COUNT_D */ "", 50257 /* IPS_MAX_DRAM_TO_FABRIC_CAM_FULL_FIFO_STATUS */ "", 50258 /* IPS_MAX_DRAM_TO_FABRIC_COUNT */ "", 50259 /* IPS_MAX_DRAM_TO_FABRIC_DURATION_COUNT */ "", 50260 /* IPS_MAX_DRAM_TO_FABRIC_FIFO_STATUS */ "", 50261 /* IPS_MAX_D_DQCQ_QUEUE_COUNT */ "", 50262 /* IPS_MAX_FSMRQ_REQ_QUEUES */ "", 50263 /* IPS_MAX_ONE_PKT_IN_FLIGHT_DRAM_QUEUE_COUNT */ "", 50264 /* IPS_MAX_ONE_PKT_IN_FLIGHT_SRAM_QUEUE_COUNT */ "", 50265 /* IPS_MAX_ONE_PKT_IN_FLIGHT_SRAM_TO_DRAM_QUEUE_COUNT */ "", 50266 /* IPS_MAX_ONE_PKT_IN_FLIGHT_TOTAL_QUEUE_COUNT */ "", 50267 /* IPS_MAX_PORT_QUEUE_SIZE */ "", 50268 /* IPS_MAX_SQM_ACTIVE_QUEUE_COUNT */ "", 50269 /* IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_A */ "", 50270 /* IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_B */ "", 50271 /* IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_C */ "", 50272 /* IPS_MAX_SQM_ACTIVE_QUEUE_COUNT_D */ "", 50273 /* IPS_MAX_SRAM_TO_DRAM_COUNT */ "", 50274 /* IPS_MAX_SRAM_TO_FABRIC_CAM_FULL_FIFO_STATUS */ "", 50275 /* IPS_MAX_SRAM_TO_FABRIC_COUNT */ "", 50276 /* IPS_MAX_SRAM_TO_FABRIC_DURATION_COUNT */ "", 50277 /* IPS_MAX_SRAM_TO_FABRIC_FIFO_STATUS */ "", 50278 /* IPS_MAX_S_DEQ_COMMAND_CREDIT_CONFIG */ "", 50279 /* IPS_MAX_S_DEQ_COMMAND_CREDIT_CONFIG_2 */ "", 50280 /* IPS_MAX_S_DEQ_COMMAND_CREDIT_SELECTION */ "", 50281 /* IPS_MAX_S_DEQ_COMMAND_DQCQ_BASED_THRESHOLDS */ "", 50282 /* IPS_MAX_S_DQCQ_DRAM_QUEUE_COUNT */ "", 50283 /* IPS_MAX_S_DQCQ_QUEUE_COUNT */ "", 50284 /* IPS_MAX_TOTAL_DRAM_TO_FABRIC_LATENCY_COUNT */ "", 50285 /* IPS_MAX_TOTAL_SRAM_TO_DRAM_LATENCY_COUNT */ "", 50286 /* IPS_MAX_TOTAL_SRAM_TO_FABRIC_LATENCY_COUNT */ "", 50287 /* IPS_MIN_CRBAL */ "", 50288 /* IPS_MIN_CR_BAL */ "", 50289 /* IPS_MIN_CR_BAL_QUEUE */ "", 50290 /* IPS_MULT_PKT_DEQ_SETTINGS */ "", 50291 /* IPS_ONE_PACKET_DEQ_LIMIT_COUNTERS */ "", 50292 /* IPS_ONE_PKT_DEQ_DISABLE */ "", 50293 /* IPS_ONE_PKT_DEQ_LIMIT_CONFIG_1 */ "", 50294 /* IPS_ONE_PKT_DEQ_LIMIT_CONFIG_2 */ "", 50295 /* IPS_ONE_PKT_DEQ_LIMIT_QUEUE_TYPE */ "", 50296 /* IPS_ONE_PKT_DEQ_LIMIT_SETTINGS_1 */ "", 50297 /* IPS_ONE_PKT_DEQ_LIMIT_SETTINGS_2 */ "", 50298 /* IPS_ONE_PKT_DEQ_LIMIT_SETTINGS_3 */ "", 50299 /* IPS_ONE_PKT_IN_FLIGHT_DRAM_QUEUE_COUNT */ "", 50300 /* IPS_ONE_PKT_IN_FLIGHT_SRAM_QUEUE_COUNT */ "", 50301 /* IPS_ONE_PKT_IN_FLIGHT_SRAM_TO_DRAM_QUEUE_COUNT */ "", 50302 /* IPS_ONE_PKT_IN_FLIGHT_TOTAL_QUEUE_COUNT */ "", 50303 /* IPS_ONE_PLUS_ONE_PORT_PROTECTION_CFG */ "", 50304 /* IPS_OPDL_HP_CTR_MAX_STATUS */ "", 50305 /* IPS_OPDL_HP_CTR_STATUS */ "", 50306 /* IPS_OPDL_HP_MAP */ "", 50307 /* IPS_OPDL_LP_CTR_MAX_STATUS */ "", 50308 /* IPS_OPDL_LP_CTR_STATUS */ "", 50309 /* IPS_OPDL_LP_MAP */ "", 50310 /* IPS_OPDL_REJ_COUNTER */ "", 50311 /* IPS_OPDL_RJCT_CTR */ "", 50312 /* IPS_OVERFLOW_DQCQ_ID */ "", 50313 /* IPS_OVERFLOW_D_DQCQ_ID */ "", 50314 /* IPS_OVERFLOW_S_DQCQ_ID */ "", 50315 /* IPS_PARITY_ERR_CNT */ "", 50316 /* IPS_PAR_ERR_INITIATE */ "", 50317 /* IPS_PAR_ERR_MEM_MASK */ "", 50318 /* IPS_PDQ_EIR_FC_MASK_SETTINGS */ "", 50319 /* IPS_PRE_STAGE_ARBITER_THRESHOLDS */ "", 50320 /* IPS_PRE_STAGE_ARBITER_WEIGHTS */ "", 50321 /* IPS_PROGRAMMABLE_DQM_REPORT_COUNTER */ "", 50322 /* IPS_PROGRAMMABLE_IQM_REPORT_COUNTER */ "", 50323 /* IPS_PROGRAMMABLE_SQM_REPORT_COUNTER */ "", 50324 /* IPS_PTS_FLOW_CONTROL_CONFIGURATION */ "", 50325 /* IPS_PUSH_QUEUE_TYPES_CONFIG */ "", 50326 /* IPS_QTYPE_FILTER */ "", 50327 /* IPS_QUEUE_INTERDIGITATED_MODE */ "", 50328 /* IPS_QUEUE_IS_HIGH_PRIORITY */ "", 50329 /* IPS_QUEUE_IS_OCB_ONLY */ "", 50330 /* IPS_QUEUE_NUM_FILTER */ "", 50331 /* IPS_QUEUE_NUM_FILTER_MASK */ "", 50332 /* IPS_RECOVER_CONFIGIRATIONS */ "", 50333 /* IPS_REG_0041 */ "", 50334 /* IPS_REG_0090 */ "", 50335 /* IPS_REG_0091 */ "", 50336 /* IPS_REG_0092 */ "", 50337 /* IPS_REG_0093 */ "", 50338 /* IPS_REG_0096 */ "", 50339 /* IPS_REG_0097 */ "", 50340 /* IPS_REG_0098 */ "", 50341 /* IPS_REG_0101 */ "", 50342 /* IPS_REG_0104 */ "", 50343 /* IPS_REG_0105 */ "", 50344 /* IPS_REG_0141 */ "", 50345 /* IPS_REG_0144 */ "", 50346 /* IPS_REG_0147 */ "", 50347 /* IPS_REG_0169 */ "", 50348 /* IPS_REG_0170 */ "", 50349 /* IPS_REG_0189 */ "", 50350 /* IPS_REG_0210 */ "", 50351 /* IPS_REG_0211 */ "", 50352 /* IPS_REG_00A4 */ "", 50353 /* IPS_REG_00A6 */ "", 50354 /* IPS_REG_00BE */ "", 50355 /* IPS_REG_00BF */ "", 50356 /* IPS_REG_00C0 */ "", 50357 /* IPS_REG_00C1 */ "", 50358 /* IPS_REG_00C2 */ "", 50359 /* IPS_REG_00C3 */ "", 50360 /* IPS_REG_00C4 */ "", 50361 /* IPS_REG_00C5 */ "", 50362 /* IPS_REG_00C6 */ "", 50363 /* IPS_REG_014A */ "", 50364 /* IPS_REG_014B */ "", 50365 /* IPS_REG_014D */ "", 50366 /* IPS_REG_014E */ "", 50367 /* IPS_REG_016A */ "", 50368 /* IPS_REG_016C */ "", 50369 /* IPS_REG_016D */ "", 50370 /* IPS_REG_016F */ "", 50371 /* IPS_REJ_CREDITS_COUNTER */ "", 50372 /* IPS_RESERVED_MIRROR_ADDR */ "", 50373 /* IPS_RESERVED_MTCD */ "", 50374 /* IPS_RESERVED_MTCP */ "", 50375 /* IPS_RESERVED_SPARE_0 */ "", 50376 /* IPS_RESERVED_SPARE_1 */ "", 50377 /* IPS_RESERVED_SPARE_2 */ "", 50378 /* IPS_RESERVED_SPARE_3 */ "", 50379 /* IPS_RETURNED_CREDIT_COUNTER */ "", 50380 /* IPS_RJCT_CRDT_CTR */ "", 50381 /* IPS_RTRN_CRDT_CTR */ "", 50382 /* IPS_SBUS_BROADCAST_ID */ "", 50383 /* IPS_SBUS_LAST_IN_CHAIN */ "", 50384 /* IPS_SCH_CREDIT_COUNTER */ "", 50385 /* IPS_SCH_FLOW_STATUS_COUNTER */ "", 50386 /* IPS_SCH_TX_FIFO_CONFIGURATIONS */ "", 50387 /* IPS_SQM_ACTIVE_QUEUE_COUNT */ "", 50388 /* IPS_SQM_ACTIVE_QUEUE_COUNT_A */ "", 50389 /* IPS_SQM_ACTIVE_QUEUE_COUNT_B */ "", 50390 /* IPS_SQM_ACTIVE_QUEUE_COUNT_C */ "", 50391 /* IPS_SQM_ACTIVE_QUEUE_COUNT_D */ "", 50392 /* IPS_SQM_DEQ_CMD_BYTES_CTR */ "", 50393 /* IPS_SQM_DEQ_CMD_CTR */ "", 50394 /* IPS_SQM_DEQ_EVNT_CTR */ "", 50395 /* IPS_SQM_DEQ_TO_DRAM_CMD_BYTES_CTR */ "", 50396 /* IPS_SQM_DEQ_TO_DRAM_CMD_CTR */ "", 50397 /* IPS_SQM_DEQ_TO_DRAM_EVNT_CTR */ "", 50398 /* IPS_SQM_DQCQ_DEPTH_CONFIG */ "", 50399 /* IPS_SQM_DQCQ_ERR_STATUS */ "", 50400 /* IPS_SQM_DQCQ_STATUS */ "", 50401 /* IPS_SQM_ENQ_EVNT_CTR */ "", 50402 /* IPS_SQM_HP_DQCQ_MAX_OCCUPANCY */ "", 50403 /* IPS_SQM_LP_DQCQ_MAX_OCCUPANCY */ "", 50404 /* IPS_SQM_MAX_DEQ_CMD_CRDT */ "", 50405 /* IPS_SQM_MAX_DEQ_CMD_CRDT_SEL */ "", 50406 /* IPS_SQM_MAX_DEQ_CMD_CRDT_TH */ "", 50407 /* IPS_SQM_NRDY_CNT */ "", 50408 /* IPS_SRAM_FMC_CREDIT_FLOW_CONTROL_THRESHOLD_1 */ "", 50409 /* IPS_SRAM_FMC_CREDIT_FLOW_CONTROL_THRESHOLD_2 */ "", 50410 /* IPS_SRAM_TO_DRAM_CONFIGURATIONS */ "", 50411 /* IPS_SRAM_TO_DRAM_COUNTERS_PER_QUEUE */ "", 50412 /* IPS_SRAM_TO_DRAM_MAX_DEQ_CMD_CRDT */ "", 50413 /* IPS_SRAM_TO_FABRIC_CAM_FULL_FIFO_STATUS */ "", 50414 /* IPS_SRAM_TO_FABRIC_COUNTERS_PER_QUEUE */ "", 50415 /* IPS_SRAM_TO_FABRIC_DURATION_COUNT */ "", 50416 /* IPS_SRAM_TO_FABRIC_FIFO_STATUS */ "", 50417 /* IPS_STORED_CREDITS_USAGE_CONFIGURATION */ "", 50418 /* IPS_SYSTEM_RED_AGING_CONFIGURATION */ "", 50419 /* IPS_S_DEQ_CMD_BYTE_COUNTER */ "", 50420 /* IPS_S_DEQ_CMD_COUNTER */ "", 50421 /* IPS_S_DEQ_COMMAND_CREDIT_ADJUST */ "", 50422 /* IPS_S_DQCQ_BYTES_CNT_HP */ "", 50423 /* IPS_S_DQCQ_BYTES_CNT_LP */ "", 50424 /* IPS_S_DQCQ_DEPTH_CONFIG */ "", 50425 /* IPS_S_DQCQ_DRAM_QUEUE_COUNT */ "", 50426 /* IPS_S_DQCQ_ID_FILTER */ "", 50427 /* IPS_S_DQCQ_MAX_OCCUPANCY_HP */ "", 50428 /* IPS_S_DQCQ_MAX_OCCUPANCY_LP */ "", 50429 /* IPS_S_DQCQ_QUEUE_COUNT */ "", 50430 /* IPS_S_DQCQ_STATUS_HP */ "", 50431 /* IPS_S_DQCQ_STATUS_LP */ "", 50432 /* IPS_TIMER_CONFIGURATION */ "", 50433 /* IPS_TIME_IN_NORM */ "", 50434 /* IPS_TIME_IN_SLOW */ "", 50435 /* IPS_TOTAL_DRAM_TO_FABRIC_LATENCY_COUNT */ "", 50436 /* IPS_TOTAL_LATENCY_DRAM_TO_FABRIC */ "", 50437 /* IPS_TOTAL_LATENCY_SRAM_TO_DRAM */ "", 50438 /* IPS_TOTAL_LATENCY_SRAM_TO_FABRIC */ "", 50439 /* IPS_TOTAL_SRAM_TO_DRAM_LATENCY_COUNT */ "", 50440 /* IPS_TOTAL_SRAM_TO_FABRIC_LATENCY_COUNT */ "", 50441 /* IPS_UPDATE_INDICATION */ "", 50442 /* IPT_ARAD_PACKETS_FORMAT */ "", 50443 /* IPT_AUTO_DOC_NAME_15 */ "", 50444 /* IPT_AUTO_DOC_NAME_16 */ "", 50445 /* IPT_BIG_LAT_PKTS_CNTR */ "", 50446 /* IPT_CFG_BYTE_CNT */ "", 50447 /* IPT_CFG_BYTE_CNT_SRC_SEL */ "", 50448 /* IPT_CFG_EVENT_CNT */ "", 50449 /* IPT_CFG_EVENT_CNT_SEL */ "", 50450 /* IPT_CLOS_COMMON_SHAPERS_FC_MASK */ "", 50451 /* IPT_CNM_CONTORL */ "", 50452 /* IPT_CNM_ETHER_TYPE */ "", 50453 /* IPT_CNM_EXTERNAL_PP_SAMPLING_DATA_SIZE */ "", 50454 /* IPT_CNM_FTMH */ "", 50455 /* IPT_CNM_FTMH_2 */ "", 50456 /* IPT_CNM_FTMH_3 */ "", 50457 /* IPT_CNM_FTMH_DSP_EXT */ "", 50458 /* IPT_CNM_FTMH_LB_EXT */ "", 50459 /* IPT_CNM_FTMH_STACK_EXT */ "", 50460 /* IPT_CNM_GENERATED_PACKET_ACTUAL_SIZE */ "", 50461 /* IPT_CNM_INGRESS_VLAN_EDIT_CMD_MAP */ "", 50462 /* IPT_CNM_MAC_SA */ "", 50463 /* IPT_CNM_PDU */ "", 50464 /* IPT_CNM_PDU_CN_TAG */ "", 50465 /* IPT_CNM_PDU_CPID_MSB */ "", 50466 /* IPT_CNM_PPH */ "", 50467 /* IPT_CNM_PPHFHEI */ "", 50468 /* IPT_CNM_PPH_INLIF */ "", 50469 /* IPT_CNM_PPH_VSI */ "", 50470 /* IPT_CNM_XGS_FORMAT_CONTROL */ "", 50471 /* IPT_CNM_XGS_FORMAT_CPID_HIGH */ "", 50472 /* IPT_CNM_XGS_FORMAT_DATA */ "", 50473 /* IPT_CNM_XGS_FORMAT_FRC_LITE */ "", 50474 /* IPT_CNM_XGS_FORMAT_PPD_0 */ "", 50475 /* IPT_CNM_XGS_FORMAT_SAMPLED_DATA_SIZE */ "", 50476 /* IPT_CNM_XGS_FORMAT_SIGNATURE_DA */ "", 50477 /* IPT_CNM_XGS_FORMAT_SIGNATURE_ETHER_TYPE */ "", 50478 /* IPT_CNM_XGS_FORMAT_SIGNATURE_SA */ "", 50479 /* IPT_COMMON_SHAPERS_CAL */ "", 50480 /* IPT_COMMON_SHAPERS_DCR_FACTOR */ "", 50481 /* IPT_COMMON_SHAPERS_DECIDE_ON_EOBST */ "", 50482 /* IPT_COMMON_SHAPERS_DELAY */ "", 50483 /* IPT_COMMON_SHAPERS_MAX_CREDIT */ "", 50484 /* IPT_COMMON_SH_DELAY_JITTER */ "", 50485 /* IPT_CONTEXT_DEBUG */ "", 50486 /* IPT_CPU_DEL_BUFF_CNT */ "", 50487 /* IPT_CPU_D_BUFF_DELETE_CONTROL */ "", 50488 /* IPT_CPU_D_BUFF_RELEASE_CONTROL */ "", 50489 /* IPT_CPU_REL_BUFF_CNT */ "", 50490 /* IPT_CRC_ERROR_COUNTER */ "", 50491 /* IPT_CRC_ERROR_D_BUFF_DELETE_CONFIGS */ "", 50492 /* IPT_CRC_ERR_BUFF_FIFO_FULL_CNT */ "", 50493 /* IPT_CRC_ERR_DELETED_BUFFERS_FIFO_HEAD */ "", 50494 /* IPT_CRC_ERR_DELETED_BUFFERS_FIFO_STATUS */ "", 50495 /* IPT_CRC_ERR_DEL_BUFF_CNT */ "", 50496 /* IPT_CRC_ERR_RATE_CONFIGURATION_REGISTER_0 */ "", 50497 /* IPT_CRC_ERR_RATE_CONFIGURATION_REGISTER_1 */ "", 50498 /* IPT_CRC_ERR_RATE_WEIGHT_DEBUG */ "", 50499 /* IPT_CRC_ERR_WEIGHT_CONFIGURATION_REGISTER_0 */ "", 50500 /* IPT_CRC_ERR_WEIGHT_CONFIGURATION_REGISTER_1 */ "", 50501 /* IPT_CRPS_LATENCY_PTR_CFG */ "", 50502 /* IPT_DATA_QUEUE_EGQ_THRESHOLD */ "", 50503 /* IPT_DEBUG_CONTROLS */ "", 50504 /* IPT_DELETED_CNM_PKTS_CNT */ "", 50505 /* IPT_DELETED_LAT_PKTS_CNT */ "", 50506 /* IPT_DESTINATION_ID_FORMAT_TO_FABRIC */ "", 50507 /* IPT_DQCF_0_DQCQ_TH */ "", 50508 /* IPT_DQCF_0_EIR_CRDT_TH */ "", 50509 /* IPT_DQCF_0_MAX_SIZE */ "", 50510 /* IPT_DQCF_0_MC_TH */ "", 50511 /* IPT_DQCF_0_START */ "", 50512 /* IPT_DQCF_1_DQCQ_TH */ "", 50513 /* IPT_DQCF_1_EIR_CRDT_TH */ "", 50514 /* IPT_DQCF_1_MAX_SIZE */ "", 50515 /* IPT_DQCF_1_MC_TH */ "", 50516 /* IPT_DQCF_1_START */ "", 50517 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_01 */ "", 50518 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_23 */ "", 50519 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_10_11 */ "", 50520 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_12_13 */ "", 50521 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_14_15 */ "", 50522 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_4_5 */ "", 50523 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_6_7 */ "", 50524 /* IPT_DRAM_BUFFER_POINTER_QUEUE_DQCQ_THRESHOLD_8_9 */ "", 50525 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_0_1 */ "", 50526 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_10_11 */ "", 50527 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_12_13 */ "", 50528 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_14_15 */ "", 50529 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_2_3 */ "", 50530 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_4_5 */ "", 50531 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_6_7 */ "", 50532 /* IPT_DRAM_BUFFER_POINTER_QUEUE_EIR_CRDT_THRESHOLD_8_9 */ "", 50533 /* IPT_DRAM_BUFFER_POINTER_QUEUE_MULTICAST_THRESHOLD */ "", 50534 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_0_1 */ "", 50535 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_10_11 */ "", 50536 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_12_13 */ "", 50537 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_14_15 */ "", 50538 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_2_3 */ "", 50539 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_4_5 */ "", 50540 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_6_7 */ "", 50541 /* IPT_DRAM_BUFFER_POINTER_QUEUE_SIZE_8_9 */ "", 50542 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_0_1 */ "", 50543 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_10_11 */ "", 50544 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_12_13 */ "", 50545 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_14_15 */ "", 50546 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_2_3 */ "", 50547 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_4_5 */ "", 50548 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_6_7 */ "", 50549 /* IPT_DRAM_BUFFER_POINTER_QUEUE_START_ADDRESS_8_9 */ "", 50550 /* IPT_DROP_MC_LP_CONFIG */ "", 50551 /* IPT_DTQ_0_DQCF_CTRL */ "", 50552 /* IPT_DTQ_1_DQCF_CTRL */ "", 50553 /* IPT_DTQ_CONFIG */ "", 50554 /* IPT_DTQ_DEBUG */ "", 50555 /* IPT_DTQ_DQCF_TH */ "", 50556 /* IPT_DTQ_FAB_FC_TH */ "", 50557 /* IPT_DTQ_LOC_FC_TH */ "", 50558 /* IPT_DTQ_MAX_SIZE */ "", 50559 /* IPT_DTQ_OCB_FC_TH */ "", 50560 /* IPT_DTQ_START */ "", 50561 /* IPT_DTQ_TH */ "", 50562 /* IPT_ECC_1B_ERR_CNT */ "", 50563 /* IPT_ECC_2B_ERR_CNT */ "", 50564 /* IPT_ECC_ERR_1B_INITIATE */ "", 50565 /* IPT_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 50566 /* IPT_ECC_ERR_2B_INITIATE */ "", 50567 /* IPT_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 50568 /* IPT_ECC_ERR_INTERRUPT_MASK_REGISTER */ "", 50569 /* IPT_ECC_ERR_INTERRUPT_REGISTER */ "", 50570 /* IPT_ECC_ERR_INTERRUPT_REGISTER_TEST */ "", 50571 /* IPT_ECC_INTERRUPT_REGISTER */ "", 50572 /* IPT_ECC_INTERRUPT_REGISTER_MASK */ "", 50573 /* IPT_ECC_INTERRUPT_REGISTER_TEST */ "", 50574 /* IPT_EGQ_0_PKT_CNT */ "", 50575 /* IPT_EGQ_0_TXQ_RD_ADDR */ "", 50576 /* IPT_EGQ_0_TXQ_WR_ADDR */ "", 50577 /* IPT_EGQ_1_PKT_CNT */ "", 50578 /* IPT_EGQ_1_TXQ_RD_ADDR */ "", 50579 /* IPT_EGQ_1_TXQ_WR_ADDR */ "", 50580 /* IPT_EGQ_2_DQCF_FC_MAP */ "", 50581 /* IPT_EGQ_PKT_CNT */ "", 50582 /* IPT_EGQ_SKIP_ADDRESS_CFG */ "", 50583 /* IPT_EGQ_TX_IRDY_CNT */ "", 50584 /* IPT_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 50585 /* IPT_ENQ_0_PKT_CNT */ "", 50586 /* IPT_ENQ_1_PKT_CNT */ "", 50587 /* IPT_ENQ_PKT_CNT */ "", 50588 /* IPT_ERROR_INITIATION_DATA */ "", 50589 /* IPT_FABRIC_HEADER_EXTENDED_MODE */ "", 50590 /* IPT_FCB_CONFIG */ "", 50591 /* IPT_FDT_0_PKT_CNT */ "", 50592 /* IPT_FDT_1_PKT_CNT */ "", 50593 /* IPT_FDT_CTRL_IRDY_CNT */ "", 50594 /* IPT_FDT_NUM_LINKS_STATUS */ "", 50595 /* IPT_FDT_NUM_LINKS_STATUS_0 */ "", 50596 /* IPT_FDT_NUM_LINKS_STATUS_1 */ "", 50597 /* IPT_FDT_NUM_LINKS_STATUS_MAX_VAL */ "", 50598 /* IPT_FDT_NUM_LINKS_STATUS_MIN_VAL */ "", 50599 /* IPT_FDT_PKT_CNT */ "", 50600 /* IPT_FDT_QNUM_CNT_SEL */ "", 50601 /* IPT_FDT_SKIP_ADDRESS_CFG */ "", 50602 /* IPT_FDT_TXQ_RD_ADDR */ "", 50603 /* IPT_FDT_TXQ_WR_ADDR */ "", 50604 /* IPT_FIFOS_MAX_OCC_0 */ "", 50605 /* IPT_FIFOS_MAX_OCC_1 */ "", 50606 /* IPT_FIFOS_MAX_OCC_2 */ "", 50607 /* IPT_FIFOS_MAX_OCC_3 */ "", 50608 /* IPT_FIFOS_MAX_OCC_4 */ "", 50609 /* IPT_FIFOS_MAX_OCC_5 */ "", 50610 /* IPT_FIFOS_MAX_OC_1 */ "", 50611 /* IPT_FIFOS_STATE */ "", 50612 /* IPT_FIFOS_STATE_STICKY */ "", 50613 /* IPT_FIFO_INTERRUPT_REGISTER */ "", 50614 /* IPT_FIFO_INTERRUPT_REGISTER_MASK */ "", 50615 /* IPT_FIFO_INTERRUPT_REGISTER_TEST */ "", 50616 /* IPT_FLIPPED_LAT_PKTS_CNT */ "", 50617 /* IPT_FLOW_CONTROL_DEBUG */ "", 50618 /* IPT_FMC_FC_STATUS_VEC */ "", 50619 /* IPT_FMC_IPS_FC_MAP */ "", 50620 /* IPT_FORCE_LOCAL_OR_FABRIC */ "", 50621 /* IPT_GCI_BACKOFF_CS_WEIGHTS */ "", 50622 /* IPT_GCI_BACKOFF_MASK_LUT_1 */ "", 50623 /* IPT_GCI_BACKOFF_MASK_LUT_2 */ "", 50624 /* IPT_GCI_BACKOFF_MASK_LUT_3 */ "", 50625 /* IPT_GCI_BACKOFF_RANGE_THRESHOLDS */ "", 50626 /* IPT_GCI_BKFF_LEVEL */ "", 50627 /* IPT_GCI_CNT */ "", 50628 /* IPT_GCI_FC_ENABLE */ "", 50629 /* IPT_GCI_FLOW_CONTROL_TO_DTQ_MASK */ "", 50630 /* IPT_GCI_LEAKY_BUCKET_CONFIGURATION_REGISTER_0 */ "", 50631 /* IPT_GCI_LEAKY_BUCKET_CONFIGURATION_REGISTER_1 */ "", 50632 /* IPT_GCI_LEAKY_BUCKET_CONFIGURATION_REGISTER_2 */ "", 50633 /* IPT_GCI_LKY_MAX_OC_1 */ "", 50634 /* IPT_GLOBAL_DQCQ_MAP_CFG_1 */ "", 50635 /* IPT_GLOBAL_DQCQ_MAP_CFG_2 */ "", 50636 /* IPT_GLOBAL_FULL_MC_DB_RANGE_0 */ "", 50637 /* IPT_GLOBAL_FULL_MC_DB_RANGE_1 */ "", 50638 /* IPT_GLOBAL_GENERAL_CFG_1 */ "", 50639 /* IPT_GLOBAL_GENERAL_CFG_2 */ "", 50640 /* IPT_GLOBAL_GENERAL_CFG_3 */ "", 50641 /* IPT_GLOBAL_MEM_OPTIONS */ "", 50642 /* IPT_GLOBAL_MINI_MC_DB_RANGE_0 */ "", 50643 /* IPT_GLOBAL_MINI_MC_DB_RANGE_1 */ "", 50644 /* IPT_GLOBAL_OCB_BUF_RANGE_0 */ "", 50645 /* IPT_GLOBAL_OCB_BUF_RANGE_1 */ "", 50646 /* IPT_GLOBAL_SYS_HEADER_CFG */ "", 50647 /* IPT_GTIMER_CONFIGURATION */ "", 50648 /* IPT_GTIMER_CYCLE */ "", 50649 /* IPT_GTIMER_TRIGGER */ "", 50650 /* IPT_HEADER_FIELDS_STAMP_WHEN_OTHER */ "", 50651 /* IPT_INDIRECT_COMMAND */ "", 50652 /* IPT_INDIRECT_COMMAND_ADDRESS */ "", 50653 /* IPT_INDIRECT_COMMAND_DATA_INCREMENT */ "", 50654 /* IPT_INDIRECT_COMMAND_RD_DATA */ "", 50655 /* IPT_INDIRECT_COMMAND_WIDE_MEM */ "", 50656 /* IPT_INDIRECT_COMMAND_WR_DATA */ "", 50657 /* IPT_INDIRECT_FORCE_BUBBLE */ "", 50658 /* IPT_INDIRECT_WR_MASK */ "", 50659 /* IPT_INTERRUPT_MASK_REGISTER */ "", 50660 /* IPT_INTERRUPT_REGISTER */ "", 50661 /* IPT_INTERRUPT_REGISTER_TEST */ "", 50662 /* IPT_INTRNL_FMC_FC_MAP */ "", 50663 /* IPT_IPT_2_IPS_FC_STATUS_VEC */ "", 50664 /* IPT_IPT_2_IPS_FC_STATUS_VEC_2 */ "", 50665 /* IPT_IPT_DEBUG_CONTEXT_CONTROLS */ "", 50666 /* IPT_IPT_DEBUG_CONTEXT_OCB_CONTROLS */ "", 50667 /* IPT_IPT_DEBUG_CONTROLS */ "", 50668 /* IPT_IPT_DEBUG_GCI_CONTROLS */ "", 50669 /* IPT_IPT_ENABLES */ "", 50670 /* IPT_IPT_EOB_FDT_CNT */ "", 50671 /* IPT_IPT_FC_CNT */ "", 50672 /* IPT_IPT_FC_CNT_SEL */ "", 50673 /* IPT_IPT_FLOW_CONTROL_CONFIG */ "", 50674 /* IPT_IPT_FMC_IPS_FC_MAP */ "", 50675 /* IPT_IPT_FMC_IPS_FC_MAP_1 */ "", 50676 /* IPT_IPT_FMC_IPS_FC_MAP_2 */ "", 50677 /* IPT_IPT_INTRNL_FMC_FC_MAP */ "", 50678 /* IPT_IQM_0_DTQ_WRAP_BURST_COUNTERS */ "", 50679 /* IPT_IQM_1_DTQ_WRAP_BURST_COUNTERS */ "", 50680 /* IPT_IQM_CLOS_SHAPERS_FC_MASK */ "", 50681 /* IPT_IQM_DQCF_STOP_ONLY_AT_EOB */ "", 50682 /* IPT_IQM_DTQ_2_DQCF_FC_MAP */ "", 50683 /* IPT_IQM_LAST_SCH_BUFFER */ "", 50684 /* IPT_IQM_MC_TRAFFIC_JITTER_SHAPER_4 */ "", 50685 /* IPT_IQM_MC_TRAFFIC_JITTER_SHAPER_9 */ "", 50686 /* IPT_IQM_MC_TRAFFIC_JITTER_SHAPER_10 */ "", 50687 /* IPT_IQM_MESH_SHAPERS_FC_MASK */ "", 50688 /* IPT_IQM_SHAPERS_CAL */ "", 50689 /* IPT_IQM_SHAPERS_DCR_FACTOR */ "", 50690 /* IPT_IQM_SHAPERS_DECIDE_ON_EOBST */ "", 50691 /* IPT_IQM_SHAPERS_DELAY */ "", 50692 /* IPT_IQM_SHAPERS_MAX_CREDIT */ "", 50693 /* IPT_IQM_SHAPER_10_SLOW_START_CAL */ "", 50694 /* IPT_IQM_SHAPER_10_SLOW_START_DELAY */ "", 50695 /* IPT_IQM_SHAPER_4_SLOW_START_CAL */ "", 50696 /* IPT_IQM_SHAPER_4_SLOW_START_DELAY */ "", 50697 /* IPT_IQM_SHAPER_9_SLOW_START_CAL */ "", 50698 /* IPT_IQM_SHAPER_9_SLOW_START_DELAY */ "", 50699 /* IPT_IQM_SLOW_START_CFG_TIMER_PERIOD */ "", 50700 /* IPT_IQM_TX_IRDY_CNT */ "", 50701 /* IPT_IQM_TX_NIRDY_CNT */ "", 50702 /* IPT_IQM_WFQ_DEFAULT_PKT_SIZE */ "", 50703 /* IPT_IQM_WFQ_MASK_RD_SIZE */ "", 50704 /* IPT_IQM_WFQ_WEIGHTS */ "", 50705 /* IPT_IS_FULL_PKT_SNOOP_MIRROR */ "", 50706 /* IPT_ITE_CONFIG */ "", 50707 /* IPT_ITE_DEBUG */ "", 50708 /* IPT_ITE_DEBUG_FROM_ITPP */ "", 50709 /* IPT_ITE_DEBUG_TO_ITPP */ "", 50710 /* IPT_ITE_FIX_CONFIG */ "", 50711 /* IPT_ITE_INTERRUPT_REGISTER */ "", 50712 /* IPT_ITE_INTERRUPT_REGISTER_MASK */ "", 50713 /* IPT_ITE_INTERRUPT_REGISTER_TEST */ "", 50714 /* IPT_LST_RD_DBUFF */ "", 50715 /* IPT_MAPPING_QUEUE_TYPE_TO_MIRROR_PACKET */ "", 50716 /* IPT_MAPPING_QUEUE_TYPE_TO_SNOOP_PACKET */ "", 50717 /* IPT_MAPPING_QUEUE_TYPE_TO_TDM_PACKET */ "", 50718 /* IPT_MAPPING_TRAFFIC_CLASS */ "", 50719 /* IPT_MAX_LATENCY_1588_PKT */ "", 50720 /* IPT_MAX_LATENCY_CRPS_FIFOS */ "", 50721 /* IPT_MC_TRAFFIC_JITTER_SHAPER_4 */ "", 50722 /* IPT_MC_TRAFFIC_JITTER_SHAPER_5 */ "", 50723 /* IPT_MESH_COMMON_SHAPERS_FC_MASK */ "", 50724 /* IPT_MIX_MOP_DESC_CNTXTS_SIZE */ "", 50725 /* IPT_MIX_MOP_DESC_CNTXTS_START */ "", 50726 /* IPT_MIX_MOP_TH */ "", 50727 /* IPT_MIX_OCB_REQ_CNTXTS_SIZE */ "", 50728 /* IPT_MIX_OCB_REQ_CNTXTS_START */ "", 50729 /* IPT_MIX_OCB_RET_DATA_CNTXTS_SIZE */ "", 50730 /* IPT_MIX_OCB_RET_DATA_CNTXTS_START */ "", 50731 /* IPT_MMU_TXI_IRDY_CNT */ "", 50732 /* IPT_MOP_FC_CONFIG */ "", 50733 /* IPT_OCB_MOP_TH */ "", 50734 /* IPT_OCB_TXI_IRDY_CNT */ "", 50735 /* IPT_ONE_PLUS_ONE_PORT_PROTECTION */ "", 50736 /* IPT_PACKET_LATENCY_FORMAT */ "", 50737 /* IPT_PACKET_LATENCY_MEASURE_CFG */ "", 50738 /* IPT_PARITY_ERR_CNT */ "", 50739 /* IPT_PAR_ERR_INITIATE */ "", 50740 /* IPT_PAR_ERR_MEM_MASK */ "", 50741 /* IPT_PCMI_0 */ "", 50742 /* IPT_PCMI_1 */ "", 50743 /* IPT_PCMI_2 */ "", 50744 /* IPT_PCMI_3 */ "", 50745 /* IPT_PCMI_4 */ "", 50746 /* IPT_PCMI_0_S */ "", 50747 /* IPT_PCMI_0_T */ "", 50748 /* IPT_PCMI_1_S */ "", 50749 /* IPT_PCMI_1_T */ "", 50750 /* IPT_PCMI_2_S */ "", 50751 /* IPT_PCMI_2_T */ "", 50752 /* IPT_PCMI_3_S */ "", 50753 /* IPT_PCMI_3_T */ "", 50754 /* IPT_PCMI_4_S */ "", 50755 /* IPT_PCMI_4_T */ "", 50756 /* IPT_PCP_CONFIG */ "", 50757 /* IPT_PCP_DEBUG */ "", 50758 /* IPT_PCP_DEBUG_FIFO */ "", 50759 /* IPT_PDQ_CFG */ "", 50760 /* IPT_PDQ_CONFIG */ "", 50761 /* IPT_PDQ_DEBUG */ "", 50762 /* IPT_PDQ_DRAM_DELETE_CFG */ "", 50763 /* IPT_PDQ_DTQ_FC_ENABLE */ "", 50764 /* IPT_PDQ_DTQ_MIX_FC_ENABLE */ "", 50765 /* IPT_PDQ_DTQ_SRAM_FC_ENABLE */ "", 50766 /* IPT_PDQ_GLB_SHAPER_FC_CONFIG */ "", 50767 /* IPT_PDQ_MC_TH */ "", 50768 /* IPT_PDQ_OCB_CFG */ "", 50769 /* IPT_PDQ_OCB_DTQ_FC_ENABLE */ "", 50770 /* IPT_PDQ_PRIOIRTY_DEBUG */ "", 50771 /* IPT_PDQ_QUEUE_DEBUG */ "", 50772 /* IPT_PDQ_SRAM_DELETE_CFG */ "", 50773 /* IPT_PDQ_S_2D_CFG */ "", 50774 /* IPT_PDQ_S_2D_DEBUG */ "", 50775 /* IPT_PDQ_S_2D_GLB_DEBUG */ "", 50776 /* IPT_PKT_LST_RD_DBUFF */ "", 50777 /* IPT_PRIORITIZER_WFQ_CFGS */ "", 50778 /* IPT_QNUM_CNT_SEL */ "", 50779 /* IPT_RDF_CONFIG */ "", 50780 /* IPT_RDF_DEBUG */ "", 50781 /* IPT_RDF_GLB_DEBUG */ "", 50782 /* IPT_READ_FIFO_MIX_DTQ_FC_ENABLE */ "", 50783 /* IPT_READ_FIFO_SRAM_DTQ_FC_ENABLE */ "", 50784 /* IPT_REG_0041 */ "", 50785 /* IPT_REG_0085 */ "", 50786 /* IPT_REG_0086 */ "", 50787 /* IPT_REG_0087 */ "", 50788 /* IPT_REG_0090 */ "", 50789 /* IPT_REG_0091 */ "", 50790 /* IPT_REG_0092 */ "", 50791 /* IPT_REG_0093 */ "", 50792 /* IPT_REG_0101 */ "", 50793 /* IPT_REG_00A4 */ "", 50794 /* IPT_REG_00A6 */ "", 50795 /* IPT_REG_00AE */ "", 50796 /* IPT_REG_00AF */ "", 50797 /* IPT_REG_00C0 */ "", 50798 /* IPT_REG_00C1 */ "", 50799 /* IPT_REG_00C2 */ "", 50800 /* IPT_REG_00C3 */ "", 50801 /* IPT_REG_00C4 */ "", 50802 /* IPT_REG_00C5 */ "", 50803 /* IPT_REG_00C6 */ "", 50804 /* IPT_REG_00CE */ "", 50805 /* IPT_REG_00CF */ "", 50806 /* IPT_REG_01C0 */ "", 50807 /* IPT_REG_01C1 */ "", 50808 /* IPT_RESERVED_MIRROR_ADDR */ "", 50809 /* IPT_RESERVED_MTCD */ "", 50810 /* IPT_RESERVED_MTCP */ "", 50811 /* IPT_RESERVED_SPARE_0 */ "", 50812 /* IPT_RESERVED_SPARE_1 */ "", 50813 /* IPT_RESERVED_SPARE_2 */ "", 50814 /* IPT_RESERVED_SPARE_3 */ "", 50815 /* IPT_RRF_CONFIG */ "", 50816 /* IPT_RRF_FC_TH */ "", 50817 /* IPT_SBUS_BROADCAST_ID */ "", 50818 /* IPT_SBUS_LAST_IN_CHAIN */ "", 50819 /* IPT_SCHEDULING_GENERAL_CONFIGS */ "", 50820 /* IPT_SCS_DEBUG */ "", 50821 /* IPT_SHAPERS_GENERAL_CONFIGS */ "", 50822 /* IPT_SHAPER_01_CAL */ "", 50823 /* IPT_SHAPER_01_DELAY */ "", 50824 /* IPT_SHAPER_01_MAX_CREDIT */ "", 50825 /* IPT_SHAPER_23_CAL */ "", 50826 /* IPT_SHAPER_23_DELAY */ "", 50827 /* IPT_SHAPER_23_MAX_CREDIT */ "", 50828 /* IPT_SHAPER_45_CAL */ "", 50829 /* IPT_SHAPER_45_DELAY */ "", 50830 /* IPT_SHAPER_45_MAX_CREDIT */ "", 50831 /* IPT_SHAPER_4_SLOW_START_CAL */ "", 50832 /* IPT_SHAPER_4_SLOW_START_DELAY */ "", 50833 /* IPT_SHAPER_5_SLOW_START_CAL */ "", 50834 /* IPT_SHAPER_5_SLOW_START_DELAY */ "", 50835 /* IPT_SHAPER_67_CAL */ "", 50836 /* IPT_SHAPER_67_DELAY */ "", 50837 /* IPT_SHAPER_67_MAX_CREDIT */ "", 50838 /* IPT_SHAPER_8_CAL */ "", 50839 /* IPT_SHAPER_8_DELAY */ "", 50840 /* IPT_SHAPER_8_MAX_CREDIT */ "", 50841 /* IPT_SHAPER_DTQ_FC_ENABLE */ "", 50842 /* IPT_SHAPER_GENERAL_CONFIG */ "", 50843 /* IPT_SHAPER_STATUS */ "", 50844 /* IPT_SLOW_START_CFG_TIMER_PERIOD */ "", 50845 /* IPT_SPECIAL_CLOCK_CONTROLS */ "", 50846 /* IPT_SRAM_RRF_DEBUG */ "", 50847 /* IPT_SRAM_RRF_GLB_DEBUG */ "", 50848 /* IPT_STAMPING_FABRIC_HEADER_ENABLE */ "", 50849 /* IPT_STAMPING_FTMH_OUTLIF_ENABLE */ "", 50850 /* IPT_STAMPING_USR_DEF_OUTLIF_ENABLE */ "", 50851 /* IPT_TRANSMIT_DATA_QUEUE_SIZE_6 */ "", 50852 /* IPT_TRANSMIT_DATA_QUEUE_SIZE_0_1 */ "", 50853 /* IPT_TRANSMIT_DATA_QUEUE_SIZE_2_3 */ "", 50854 /* IPT_TRANSMIT_DATA_QUEUE_SIZE_4_5 */ "", 50855 /* IPT_TRANSMIT_DATA_QUEUE_START_ADRESS_6 */ "", 50856 /* IPT_TRANSMIT_DATA_QUEUE_START_ADRESS_0_1 */ "", 50857 /* IPT_TRANSMIT_DATA_QUEUE_START_ADRESS_2_3 */ "", 50858 /* IPT_TRANSMIT_DATA_QUEUE_START_ADRESS_4_5 */ "", 50859 /* IPT_TRANSMIT_DATA_QUEUE_THRESHOLD_6 */ "", 50860 /* IPT_TRANSMIT_DATA_QUEUE_THRESHOLD_0_1 */ "", 50861 /* IPT_TRANSMIT_DATA_QUEUE_THRESHOLD_2_3 */ "", 50862 /* IPT_TRANSMIT_DATA_QUEUE_THRESHOLD_4_5 */ "", 50863 /* IPT_UNUSED_OUTPUT */ "", 50864 /* IPT_WFQ_CFG */ "", 50865 /* IPT_WFQ_GENERAL_CONFIGS */ "", 50866 /* IPT_WFQ_MESH_CFG */ "", 50867 /* IPT_WFQ_WEIGHT_0 */ "", 50868 /* IPT_WFQ_WEIGHT_1 */ "", 50869 /* IPV4IPMCIDXINCCONFIG */ "", 50870 /* IPV4_FRAME_CHECKS */ "", 50871 /* IPV6IPMCIDXINCCONFIG */ "", 50872 /* IPV6_EXT_HEADER0 */ "", 50873 /* IPV6_EXT_HEADER1 */ "", 50874 /* IPV6_EXT_HEADER2 */ "", 50875 /* IPV6_EXT_HEADER3 */ "", 50876 /* IPV6_FRAME_CHECKS */ "", 50877 /* IPV6_MIN_FRAG_SIZE */ "", 50878 /* IPV6_SIP_DIP_LINK_LOCAL_DROP_CONFIG */ "", 50879 /* IP_COUNTERS_PARITY_CONTROL */ "", 50880 /* IP_COUNTERS_PARITY_STATUS_INTR */ "", 50881 /* IP_COUNTERS_PARITY_STATUS_NACK */ "", 50882 /* IP_MULTICAST_CAM_BIST_CONFIG_64 */ "", 50883 /* IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE0 */ "", 50884 /* IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE1 */ "", 50885 /* IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE2 */ "", 50886 /* IP_MULTICAST_CAM_BIST_CONFIG_64_PIPE3 */ "", 50887 /* IP_MULTICAST_CAM_BIST_STATUS */ "", 50888 /* IP_MULTICAST_CAM_BIST_STATUS_PIPE0 */ "", 50889 /* IP_MULTICAST_CAM_BIST_STATUS_PIPE1 */ "", 50890 /* IP_MULTICAST_CAM_BIST_STATUS_PIPE2 */ "", 50891 /* IP_MULTICAST_CAM_BIST_STATUS_PIPE3 */ "", 50892 /* IP_MULTICAST_CAM_SERCTRL */ "IP_MULTICAST_CAM_SER_CONTROL", 50893 /* IP_MULTICAST_TCAM_BIST_CONFIG */ "", 50894 /* IP_MULTICAST_TCAM_BIST_CONFIG_PIPE0 */ "", 50895 /* IP_MULTICAST_TCAM_BIST_CONFIG_PIPE1 */ "", 50896 /* IP_MULTICAST_TCAM_BIST_CONFIG_PIPE2 */ "", 50897 /* IP_MULTICAST_TCAM_BIST_CONFIG_PIPE3 */ "", 50898 /* IP_MULTICAST_TCAM_BIST_CONTROL */ "", 50899 /* IP_MULTICAST_TCAM_BIST_CONTROL_PIPE0 */ "", 50900 /* IP_MULTICAST_TCAM_BIST_CONTROL_PIPE1 */ "", 50901 /* IP_MULTICAST_TCAM_BIST_CONTROL_PIPE2 */ "", 50902 /* IP_MULTICAST_TCAM_BIST_CONTROL_PIPE3 */ "", 50903 /* IP_MULTICAST_TCAM_BIST_DBG_DATA */ "", 50904 /* IP_MULTICAST_TCAM_BIST_DBG_DATA_PIPE0 */ "", 50905 /* IP_MULTICAST_TCAM_BIST_DBG_DATA_PIPE1 */ "", 50906 /* IP_MULTICAST_TCAM_BIST_DBG_DATA_PIPE2 */ "", 50907 /* IP_MULTICAST_TCAM_BIST_DBG_DATA_PIPE3 */ "", 50908 /* IP_MULTICAST_TCAM_BIST_STATUS */ "", 50909 /* IP_MULTICAST_TCAM_BIST_STATUS_PIPE0 */ "", 50910 /* IP_MULTICAST_TCAM_BIST_STATUS_PIPE1 */ "", 50911 /* IP_MULTICAST_TCAM_BIST_STATUS_PIPE2 */ "", 50912 /* IP_MULTICAST_TCAM_BIST_STATUS_PIPE3 */ "", 50913 /* IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64 */ "", 50914 /* IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64_PIPE0 */ "", 50915 /* IP_MULTICAST_TCAM_CAM_BIST_CONFIG_64_PIPE1 */ "", 50916 /* IP_MULTICAST_TCAM_CAM_BIST_STATUS */ "", 50917 /* IP_MULTICAST_TCAM_CAM_BIST_STATUS_PIPE0 */ "", 50918 /* IP_MULTICAST_TCAM_CAM_BIST_STATUS_PIPE1 */ "", 50919 /* IP_PARSER0_HFE_SER_CONTROL */ "", 50920 /* IP_PARSER0_HFE_STAGE_TM_CONTROL_0 */ "", 50921 /* IP_PARSER0_HFE_STAGE_TM_CONTROL_0_PIPE0 */ "", 50922 /* IP_PARSER0_HFE_STAGE_TM_CONTROL_0_PIPE1 */ "", 50923 /* IP_PARSER0_HME_STAGE_CAM_BIST_CONFIG_0 */ "", 50924 /* IP_PARSER0_HME_STAGE_CAM_BIST_CONFIG_0_PIPE0 */ "", 50925 /* IP_PARSER0_HME_STAGE_CAM_BIST_CONFIG_0_PIPE1 */ "", 50926 /* IP_PARSER0_HME_STAGE_CONFIG_0 */ "", 50927 /* IP_PARSER0_HME_STAGE_DEBUG_STATUS_0 */ "", 50928 /* IP_PARSER0_HME_STAGE_DEBUG_STATUS_0_PIPE0 */ "", 50929 /* IP_PARSER0_HME_STAGE_DEBUG_STATUS_0_PIPE1 */ "", 50930 /* IP_PARSER0_HME_STAGE_SER_CONTROL */ "", 50931 /* IP_PARSER0_HME_STAGE_TCAM_BIST_STATUS_0 */ "", 50932 /* IP_PARSER0_HME_STAGE_TCAM_BIST_STATUS_0_PIPE0 */ "", 50933 /* IP_PARSER0_HME_STAGE_TCAM_BIST_STATUS_0_PIPE1 */ "", 50934 /* IP_PARSER0_HME_STAGE_TCAM_SER_CONTROL_0 */ "", 50935 /* IP_PARSER0_HME_STAGE_TM_CONTROL_0 */ "", 50936 /* IP_PARSER0_HME_STAGE_TM_CONTROL_0_PIPE0 */ "", 50937 /* IP_PARSER0_HME_STAGE_TM_CONTROL_0_PIPE1 */ "", 50938 /* IP_PARSER1_HFE_SER_CONTROL */ "", 50939 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_0 */ "", 50940 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_1 */ "", 50941 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_2 */ "", 50942 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_3 */ "", 50943 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_4 */ "", 50944 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_0_PIPE0 */ "", 50945 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_0_PIPE1 */ "", 50946 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_1_PIPE0 */ "", 50947 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_1_PIPE1 */ "", 50948 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_2_PIPE0 */ "", 50949 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_2_PIPE1 */ "", 50950 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_3_PIPE0 */ "", 50951 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_3_PIPE1 */ "", 50952 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_4_PIPE0 */ "", 50953 /* IP_PARSER1_HFE_STAGE_TM_CONTROL_4_PIPE1 */ "", 50954 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_0 */ "", 50955 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_1 */ "", 50956 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_2 */ "", 50957 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_3 */ "", 50958 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_4 */ "", 50959 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_0_PIPE0 */ "", 50960 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_0_PIPE1 */ "", 50961 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_1_PIPE0 */ "", 50962 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_1_PIPE1 */ "", 50963 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_2_PIPE0 */ "", 50964 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_2_PIPE1 */ "", 50965 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_3_PIPE0 */ "", 50966 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_3_PIPE1 */ "", 50967 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_4_PIPE0 */ "", 50968 /* IP_PARSER1_HME_STAGE_CAM_BIST_CONFIG_4_PIPE1 */ "", 50969 /* IP_PARSER1_HME_STAGE_CONFIG_0 */ "", 50970 /* IP_PARSER1_HME_STAGE_CONFIG_1 */ "", 50971 /* IP_PARSER1_HME_STAGE_CONFIG_2 */ "", 50972 /* IP_PARSER1_HME_STAGE_CONFIG_3 */ "", 50973 /* IP_PARSER1_HME_STAGE_CONFIG_4 */ "", 50974 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_0 */ "", 50975 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_1 */ "", 50976 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_2 */ "", 50977 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_3 */ "", 50978 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_4 */ "", 50979 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_0_PIPE0 */ "", 50980 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_0_PIPE1 */ "", 50981 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_1_PIPE0 */ "", 50982 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_1_PIPE1 */ "", 50983 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_2_PIPE0 */ "", 50984 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_2_PIPE1 */ "", 50985 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_3_PIPE0 */ "", 50986 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_3_PIPE1 */ "", 50987 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_4_PIPE0 */ "", 50988 /* IP_PARSER1_HME_STAGE_DEBUG_STATUS_4_PIPE1 */ "", 50989 /* IP_PARSER1_HME_STAGE_SER_CONTROL */ "", 50990 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_0 */ "", 50991 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_1 */ "", 50992 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_2 */ "", 50993 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_3 */ "", 50994 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_4 */ "", 50995 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_0_PIPE0 */ "", 50996 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_0_PIPE1 */ "", 50997 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_1_PIPE0 */ "", 50998 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_1_PIPE1 */ "", 50999 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_2_PIPE0 */ "", 51000 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_2_PIPE1 */ "", 51001 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_3_PIPE0 */ "", 51002 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_3_PIPE1 */ "", 51003 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_4_PIPE0 */ "", 51004 /* IP_PARSER1_HME_STAGE_TCAM_BIST_STATUS_4_PIPE1 */ "", 51005 /* IP_PARSER1_HME_STAGE_TCAM_SER_CONTROL_0 */ "", 51006 /* IP_PARSER1_HME_STAGE_TCAM_SER_CONTROL_1 */ "", 51007 /* IP_PARSER1_HME_STAGE_TCAM_SER_CONTROL_2 */ "", 51008 /* IP_PARSER1_HME_STAGE_TCAM_SER_CONTROL_3 */ "", 51009 /* IP_PARSER1_HME_STAGE_TCAM_SER_CONTROL_4 */ "", 51010 /* IP_PARSER1_HME_STAGE_TM_CONTROL_0 */ "", 51011 /* IP_PARSER1_HME_STAGE_TM_CONTROL_1 */ "", 51012 /* IP_PARSER1_HME_STAGE_TM_CONTROL_2 */ "", 51013 /* IP_PARSER1_HME_STAGE_TM_CONTROL_3 */ "", 51014 /* IP_PARSER1_HME_STAGE_TM_CONTROL_4 */ "", 51015 /* IP_PARSER1_HME_STAGE_TM_CONTROL_0_PIPE0 */ "", 51016 /* IP_PARSER1_HME_STAGE_TM_CONTROL_0_PIPE1 */ "", 51017 /* IP_PARSER1_HME_STAGE_TM_CONTROL_1_PIPE0 */ "", 51018 /* IP_PARSER1_HME_STAGE_TM_CONTROL_1_PIPE1 */ "", 51019 /* IP_PARSER1_HME_STAGE_TM_CONTROL_2_PIPE0 */ "", 51020 /* IP_PARSER1_HME_STAGE_TM_CONTROL_2_PIPE1 */ "", 51021 /* IP_PARSER1_HME_STAGE_TM_CONTROL_3_PIPE0 */ "", 51022 /* IP_PARSER1_HME_STAGE_TM_CONTROL_3_PIPE1 */ "", 51023 /* IP_PARSER1_HME_STAGE_TM_CONTROL_4_PIPE0 */ "", 51024 /* IP_PARSER1_HME_STAGE_TM_CONTROL_4_PIPE1 */ "", 51025 /* IP_PARSER1_MICE_CAM_BIST_CONFIG_0 */ "", 51026 /* IP_PARSER1_MICE_CAM_BIST_CONFIG_1 */ "", 51027 /* IP_PARSER1_MICE_CAM_BIST_CONFIG_0_PIPE0 */ "", 51028 /* IP_PARSER1_MICE_CAM_BIST_CONFIG_0_PIPE1 */ "", 51029 /* IP_PARSER1_MICE_CAM_BIST_CONFIG_1_PIPE0 */ "", 51030 /* IP_PARSER1_MICE_CAM_BIST_CONFIG_1_PIPE1 */ "", 51031 /* IP_PARSER1_MICE_SER_CONTROL */ "", 51032 /* IP_PARSER1_MICE_TCAM_BIST_STATUS_0 */ "", 51033 /* IP_PARSER1_MICE_TCAM_BIST_STATUS_1 */ "", 51034 /* IP_PARSER1_MICE_TCAM_BIST_STATUS_0_PIPE0 */ "", 51035 /* IP_PARSER1_MICE_TCAM_BIST_STATUS_0_PIPE1 */ "", 51036 /* IP_PARSER1_MICE_TCAM_BIST_STATUS_1_PIPE0 */ "", 51037 /* IP_PARSER1_MICE_TCAM_BIST_STATUS_1_PIPE1 */ "", 51038 /* IP_PARSER1_MICE_TCAM_SER_CONTROL_0 */ "", 51039 /* IP_PARSER1_MICE_TCAM_SER_CONTROL_1 */ "", 51040 /* IP_PARSER1_MICE_TCAM_TM_CONTROL_0 */ "", 51041 /* IP_PARSER1_MICE_TCAM_TM_CONTROL_1 */ "", 51042 /* IP_PARSER1_MICE_TCAM_TM_CONTROL_0_PIPE0 */ "", 51043 /* IP_PARSER1_MICE_TCAM_TM_CONTROL_0_PIPE1 */ "", 51044 /* IP_PARSER1_MICE_TCAM_TM_CONTROL_1_PIPE0 */ "", 51045 /* IP_PARSER1_MICE_TCAM_TM_CONTROL_1_PIPE1 */ "", 51046 /* IP_PARSER2_HFE_SER_CONTROL */ "", 51047 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_0 */ "", 51048 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_1 */ "", 51049 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_2 */ "", 51050 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_3 */ "", 51051 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_4 */ "", 51052 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_0_PIPE0 */ "", 51053 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_0_PIPE1 */ "", 51054 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_1_PIPE0 */ "", 51055 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_1_PIPE1 */ "", 51056 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_2_PIPE0 */ "", 51057 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_2_PIPE1 */ "", 51058 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_3_PIPE0 */ "", 51059 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_3_PIPE1 */ "", 51060 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_4_PIPE0 */ "", 51061 /* IP_PARSER2_HFE_STAGE_TM_CONTROL_4_PIPE1 */ "", 51062 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_0 */ "", 51063 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_1 */ "", 51064 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_2 */ "", 51065 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_3 */ "", 51066 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_4 */ "", 51067 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_0_PIPE0 */ "", 51068 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_0_PIPE1 */ "", 51069 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_1_PIPE0 */ "", 51070 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_1_PIPE1 */ "", 51071 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_2_PIPE0 */ "", 51072 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_2_PIPE1 */ "", 51073 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_3_PIPE0 */ "", 51074 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_3_PIPE1 */ "", 51075 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_4_PIPE0 */ "", 51076 /* IP_PARSER2_HME_STAGE_CAM_BIST_CONFIG_4_PIPE1 */ "", 51077 /* IP_PARSER2_HME_STAGE_CONFIG_0 */ "", 51078 /* IP_PARSER2_HME_STAGE_CONFIG_1 */ "", 51079 /* IP_PARSER2_HME_STAGE_CONFIG_2 */ "", 51080 /* IP_PARSER2_HME_STAGE_CONFIG_3 */ "", 51081 /* IP_PARSER2_HME_STAGE_CONFIG_4 */ "", 51082 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_0 */ "", 51083 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_1 */ "", 51084 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_2 */ "", 51085 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_3 */ "", 51086 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_4 */ "", 51087 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_0_PIPE0 */ "", 51088 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_0_PIPE1 */ "", 51089 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_1_PIPE0 */ "", 51090 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_1_PIPE1 */ "", 51091 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_2_PIPE0 */ "", 51092 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_2_PIPE1 */ "", 51093 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_3_PIPE0 */ "", 51094 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_3_PIPE1 */ "", 51095 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_4_PIPE0 */ "", 51096 /* IP_PARSER2_HME_STAGE_DEBUG_STATUS_4_PIPE1 */ "", 51097 /* IP_PARSER2_HME_STAGE_SER_CONTROL */ "", 51098 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_0 */ "", 51099 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_1 */ "", 51100 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_2 */ "", 51101 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_3 */ "", 51102 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_4 */ "", 51103 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_0_PIPE0 */ "", 51104 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_0_PIPE1 */ "", 51105 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_1_PIPE0 */ "", 51106 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_1_PIPE1 */ "", 51107 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_2_PIPE0 */ "", 51108 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_2_PIPE1 */ "", 51109 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_3_PIPE0 */ "", 51110 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_3_PIPE1 */ "", 51111 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_4_PIPE0 */ "", 51112 /* IP_PARSER2_HME_STAGE_TCAM_BIST_STATUS_4_PIPE1 */ "", 51113 /* IP_PARSER2_HME_STAGE_TCAM_SER_CONTROL_0 */ "", 51114 /* IP_PARSER2_HME_STAGE_TCAM_SER_CONTROL_1 */ "", 51115 /* IP_PARSER2_HME_STAGE_TCAM_SER_CONTROL_2 */ "", 51116 /* IP_PARSER2_HME_STAGE_TCAM_SER_CONTROL_3 */ "", 51117 /* IP_PARSER2_HME_STAGE_TCAM_SER_CONTROL_4 */ "", 51118 /* IP_PARSER2_HME_STAGE_TM_CONTROL_0 */ "", 51119 /* IP_PARSER2_HME_STAGE_TM_CONTROL_1 */ "", 51120 /* IP_PARSER2_HME_STAGE_TM_CONTROL_2 */ "", 51121 /* IP_PARSER2_HME_STAGE_TM_CONTROL_3 */ "", 51122 /* IP_PARSER2_HME_STAGE_TM_CONTROL_4 */ "", 51123 /* IP_PARSER2_HME_STAGE_TM_CONTROL_0_PIPE0 */ "", 51124 /* IP_PARSER2_HME_STAGE_TM_CONTROL_0_PIPE1 */ "", 51125 /* IP_PARSER2_HME_STAGE_TM_CONTROL_1_PIPE0 */ "", 51126 /* IP_PARSER2_HME_STAGE_TM_CONTROL_1_PIPE1 */ "", 51127 /* IP_PARSER2_HME_STAGE_TM_CONTROL_2_PIPE0 */ "", 51128 /* IP_PARSER2_HME_STAGE_TM_CONTROL_2_PIPE1 */ "", 51129 /* IP_PARSER2_HME_STAGE_TM_CONTROL_3_PIPE0 */ "", 51130 /* IP_PARSER2_HME_STAGE_TM_CONTROL_3_PIPE1 */ "", 51131 /* IP_PARSER2_HME_STAGE_TM_CONTROL_4_PIPE0 */ "", 51132 /* IP_PARSER2_HME_STAGE_TM_CONTROL_4_PIPE1 */ "", 51133 /* IP_PARSER2_MICE_CAM_BIST_CONFIG_0 */ "", 51134 /* IP_PARSER2_MICE_CAM_BIST_CONFIG_1 */ "", 51135 /* IP_PARSER2_MICE_CAM_BIST_CONFIG_0_PIPE0 */ "", 51136 /* IP_PARSER2_MICE_CAM_BIST_CONFIG_0_PIPE1 */ "", 51137 /* IP_PARSER2_MICE_CAM_BIST_CONFIG_1_PIPE0 */ "", 51138 /* IP_PARSER2_MICE_CAM_BIST_CONFIG_1_PIPE1 */ "", 51139 /* IP_PARSER2_MICE_SER_CONTROL */ "", 51140 /* IP_PARSER2_MICE_TCAM_BIST_STATUS_0 */ "", 51141 /* IP_PARSER2_MICE_TCAM_BIST_STATUS_1 */ "", 51142 /* IP_PARSER2_MICE_TCAM_BIST_STATUS_0_PIPE0 */ "", 51143 /* IP_PARSER2_MICE_TCAM_BIST_STATUS_0_PIPE1 */ "", 51144 /* IP_PARSER2_MICE_TCAM_BIST_STATUS_1_PIPE0 */ "", 51145 /* IP_PARSER2_MICE_TCAM_BIST_STATUS_1_PIPE1 */ "", 51146 /* IP_PARSER2_MICE_TCAM_SER_CONTROL_0 */ "", 51147 /* IP_PARSER2_MICE_TCAM_SER_CONTROL_1 */ "", 51148 /* IP_PARSER2_MICE_TCAM_TM_CONTROL_0 */ "", 51149 /* IP_PARSER2_MICE_TCAM_TM_CONTROL_1 */ "", 51150 /* IP_PARSER2_MICE_TCAM_TM_CONTROL_0_PIPE0 */ "", 51151 /* IP_PARSER2_MICE_TCAM_TM_CONTROL_0_PIPE1 */ "", 51152 /* IP_PARSER2_MICE_TCAM_TM_CONTROL_1_PIPE0 */ "", 51153 /* IP_PARSER2_MICE_TCAM_TM_CONTROL_1_PIPE1 */ "", 51154 /* IP_PROTOCOL_FILTER */ "", 51155 /* IP_SER_CLK_GATE_CTRL */ "", 51156 /* IP_TO_AXP_CREDIT_TRANSFER */ "", 51157 /* IP_TO_CMICM_CREDIT_TRANSFER */ "", 51158 /* IQMT_BANK_SELECT */ "", 51159 /* IQMT_BDBLL_BANK_SIZES */ "", 51160 /* IQMT_ECC_1B_ERR_CNT */ "", 51161 /* IQMT_ECC_2B_ERR_CNT */ "", 51162 /* IQMT_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 51163 /* IQMT_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 51164 /* IQMT_ECC_INTERRUPT_REGISTER */ "", 51165 /* IQMT_ECC_INTERRUPT_REGISTER_MASK */ "", 51166 /* IQMT_ECC_INTERRUPT_REGISTER_TEST */ "", 51167 /* IQMT_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 51168 /* IQMT_EPNI_0_EGRESS_ST_DROPPED_REPORT_COUNTER */ "", 51169 /* IQMT_EPNI_1_EGRESS_ST_DROPPED_REPORT_COUNTER */ "", 51170 /* IQMT_ERROR_INITIATION_DATA */ "", 51171 /* IQMT_GLOBAL_FULL_MC_DB_RANGE_0 */ "", 51172 /* IQMT_GLOBAL_FULL_MC_DB_RANGE_1 */ "", 51173 /* IQMT_GLOBAL_GENERAL_CFG_4 */ "", 51174 /* IQMT_GLOBAL_ISP_0 */ "", 51175 /* IQMT_GLOBAL_ISP_1 */ "", 51176 /* IQMT_GLOBAL_MEM_OPTIONS */ "", 51177 /* IQMT_GLOBAL_MINI_MC_DB_RANGE_0 */ "", 51178 /* IQMT_GLOBAL_MINI_MC_DB_RANGE_1 */ "", 51179 /* IQMT_GLOBAL_OCB_BUF_RANGE_0 */ "", 51180 /* IQMT_GLOBAL_OCB_BUF_RANGE_1 */ "", 51181 /* IQMT_GTIMER_CONFIGURATION */ "", 51182 /* IQMT_GTIMER_TRIGGER */ "", 51183 /* IQMT_INDIRECT_COMMAND */ "", 51184 /* IQMT_INDIRECT_COMMAND_ADDRESS */ "", 51185 /* IQMT_INDIRECT_COMMAND_DATA_INCREMENT */ "", 51186 /* IQMT_INDIRECT_COMMAND_RD_DATA */ "", 51187 /* IQMT_INDIRECT_COMMAND_WIDE_MEM */ "", 51188 /* IQMT_INDIRECT_COMMAND_WR_DATA */ "", 51189 /* IQMT_INDIRECT_FORCE_BUBBLE */ "", 51190 /* IQMT_INTERRUPT_MASK_REGISTER */ "", 51191 /* IQMT_INTERRUPT_REGISTER */ "", 51192 /* IQMT_INTERRUPT_REGISTER_TEST */ "", 51193 /* IQMT_IQMT_INIT */ "", 51194 /* IQMT_IQM_0_DEQUEUE_ST_DROPPED_REPORT_COUNTER */ "", 51195 /* IQMT_IQM_0_ENQUEUE_ST_DROPPED_REPORT_COUNTER */ "", 51196 /* IQMT_IQM_0_INGRESS_DEQ_ST_DROPPED_REPORT_COUNTER */ "", 51197 /* IQMT_IQM_0_ING_ENQ_RPT_DROP_CNT */ "", 51198 /* IQMT_IQM_0_SCR_PRD */ "", 51199 /* IQMT_IQM_1_DEQUEUE_ST_DROPPED_REPORT_COUNTER */ "", 51200 /* IQMT_IQM_1_ENQUEUE_ST_DROPPED_REPORT_COUNTER */ "", 51201 /* IQMT_IQM_1_INGRESS_DEQ_ST_DROPPED_REPORT_COUNTER */ "", 51202 /* IQMT_IQM_1_INGRESS_ENQ_ST_DROPPED_REPORT_COUNTER */ "", 51203 /* IQMT_IQM_1_SCR_PRD */ "", 51204 /* IQMT_IQM_BDB_OFFSET */ "", 51205 /* IQMT_MEM_BANK_SELECT */ "", 51206 /* IQMT_PARITY_ERR_CNT */ "", 51207 /* IQMT_PAR_ERR_INITIATE */ "", 51208 /* IQMT_PAR_ERR_MEM_MASK */ "", 51209 /* IQMT_PDM_CONFIGURATION */ "", 51210 /* IQMT_REG_00A4 */ "", 51211 /* IQMT_REG_00A6 */ "", 51212 /* IQMT_RESERVED_MIRROR_ADDR */ "", 51213 /* IQMT_RESERVED_MTCD */ "", 51214 /* IQMT_RESERVED_MTCP */ "", 51215 /* IQMT_RESERVED_PCMI_0 */ "", 51216 /* IQMT_RESERVED_PCMI_1 */ "", 51217 /* IQMT_RESERVED_PCMI_2 */ "", 51218 /* IQMT_RESERVED_PCMI_3 */ "", 51219 /* IQMT_RESERVED_PCMI_4 */ "", 51220 /* IQMT_RESERVED_PCMI_0_S */ "", 51221 /* IQMT_RESERVED_PCMI_0_T */ "", 51222 /* IQMT_RESERVED_PCMI_1_S */ "", 51223 /* IQMT_RESERVED_PCMI_1_T */ "", 51224 /* IQMT_RESERVED_PCMI_2_S */ "", 51225 /* IQMT_RESERVED_PCMI_2_T */ "", 51226 /* IQMT_RESERVED_PCMI_3_S */ "", 51227 /* IQMT_RESERVED_PCMI_3_T */ "", 51228 /* IQMT_RESERVED_PCMI_4_S */ "", 51229 /* IQMT_RESERVED_PCMI_4_T */ "", 51230 /* IQMT_RESERVED_SPARE_0 */ "", 51231 /* IQMT_RESERVED_SPARE_1 */ "", 51232 /* IQMT_RESERVED_SPARE_2 */ "", 51233 /* IQMT_RESERVED_SPARE_3 */ "", 51234 /* IQMT_RPT_PKTSIZE_COMPENSATION_SETTING */ "", 51235 /* IQMT_SBUS_BROADCAST_ID */ "", 51236 /* IQMT_SBUS_LAST_IN_CHAIN */ "", 51237 /* IQMT_STATISTICS_GENERAL_CONFIGUARTION */ "", 51238 /* IQMT_STATISTICS_REPORT_PORT_0 */ "", 51239 /* IQMT_STATISTICS_REPORT_PORT_1 */ "", 51240 /* IQMT_ST_RATE_LIMIT_PRD */ "", 51241 /* IQMT_ST_TX_FIFO_FLOW_CONTROL_MAP */ "", 51242 /* IQMT_ST_TX_FIFO_FLOW_CONTROL_TH */ "", 51243 /* IQM_AUTO_DOC_NAME_2 */ "", 51244 /* IQM_AUTO_DOC_NAME_5 */ "", 51245 /* IQM_AUTO_DOC_NAME_7 */ "", 51246 /* IQM_AUTO_DOC_NAME_9 */ "", 51247 /* IQM_BDB_CONFIGURATION */ "", 51248 /* IQM_BDB_DYN_SIZE_CNT */ "", 51249 /* IQM_BDB_DYN_SIZE_RJCT_TH_CFG */ "", 51250 /* IQM_BDB_DYN_SIZE_TH_CFG_1 */ "", 51251 /* IQM_BDB_DYN_SIZE_TH_CFG_2 */ "", 51252 /* IQM_BDB_DYN_SIZE_TH_CFG_3 */ "", 51253 /* IQM_BDB_DYN_SIZE_TH_CFG_4 */ "", 51254 /* IQM_BUFF_DYN_SIZE_CNT */ "", 51255 /* IQM_BUFF_DYN_SIZE_TH_CFG_1 */ "", 51256 /* IQM_BUFF_DYN_SIZE_TH_CFG_2 */ "", 51257 /* IQM_BUFF_DYN_SIZE_TH_CFG_3 */ "", 51258 /* IQM_BUFF_DYN_SIZE_TH_CFG_4 */ "", 51259 /* IQM_BURST_SETTINGS */ "", 51260 /* IQM_CNI_PACKET_COUNTERS */ "", 51261 /* IQM_CNM_PACKET_COUNTER */ "", 51262 /* IQM_CNM_PCKT_CNT */ "", 51263 /* IQM_CNTPROCESSOR_CONFIG_1 */ "", 51264 /* IQM_CNT_COMMAN_CFG_1_A */ "", 51265 /* IQM_CNT_COMMAN_CFG_1_B */ "", 51266 /* IQM_CNT_COMMAN_CFG_1_C */ "", 51267 /* IQM_CNT_COMMAN_CFG_1_D */ "", 51268 /* IQM_CNT_COMMAN_CFG_2_A */ "", 51269 /* IQM_CNT_COMMAN_CFG_2_B */ "", 51270 /* IQM_CNT_COMMAN_CFG_2_C */ "", 51271 /* IQM_CNT_COMMAN_CFG_2_D */ "", 51272 /* IQM_CNT_PROCESSOR_CONFIG_2 */ "", 51273 /* IQM_CP_CONFIGURATION */ "", 51274 /* IQM_CP_QUEUES_RANGE */ "", 51275 /* IQM_CP_QUEUES_RANGE_0 */ "", 51276 /* IQM_CP_QUEUES_RANGE_1 */ "", 51277 /* IQM_DELETED_PACKET_COUNTER */ "", 51278 /* IQM_DEQUEUE_BYTE_COUNTER */ "", 51279 /* IQM_DEQUEUE_DELETED_PACKET_COUNTER */ "", 51280 /* IQM_DEQUEUE_ISP_PACKET_COUNTER */ "", 51281 /* IQM_DEQUEUE_PACKET_COUNTER */ "", 51282 /* IQM_DEQ_INTERNAL_SETTING */ "", 51283 /* IQM_DRAM_BUFF_DYN_SIZE_RJCT_TH_CFG */ "", 51284 /* IQM_DRAM_DYN_SIZE_CNT */ "", 51285 /* IQM_DRAM_DYN_SIZE_RJCT_TH_CFG */ "", 51286 /* IQM_DRAM_DYN_SIZE_TH_CFG_0 */ "", 51287 /* IQM_DRAM_DYN_SIZE_TH_CFG_1 */ "", 51288 /* IQM_DRAM_DYN_SIZE_TH_CFG_2 */ "", 51289 /* IQM_DRAM_DYN_SIZE_TH_CFG_3 */ "", 51290 /* IQM_DRAM_ELIGIBLE_RJCT_MASK */ "", 51291 /* IQM_DRAM_REJECT_STATE */ "", 51292 /* IQM_DRAM_TO_FABRIC_LATENCY */ "", 51293 /* IQM_DRAM_TO_FABRIC_LATENCY_AVRG */ "", 51294 /* IQM_DRAM_TO_FABRIC_LATENCY_MAX */ "", 51295 /* IQM_DYNAMIC_BDBS_COUNTER */ "", 51296 /* IQM_DYNAMIC_BUFFER_BDS_COUNTER */ "", 51297 /* IQM_DYNAMIC_BYTE_COUNTER */ "", 51298 /* IQM_DYNAMIC_OCB_BUFFER_COUNTER */ "", 51299 /* IQM_DYN_REJECT_PACKET_COUNTERS */ "", 51300 /* IQM_ECC_1B_ERR_CNT */ "", 51301 /* IQM_ECC_2B_ERR_CNT */ "", 51302 /* IQM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 51303 /* IQM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 51304 /* IQM_ECC_INTERRUPT_REGISTER */ "", 51305 /* IQM_ECC_INTERRUPT_REGISTER_MASK */ "", 51306 /* IQM_ECC_INTERRUPT_REGISTER_TEST */ "", 51307 /* IQM_ECN_CONFIGURATION */ "", 51308 /* IQM_ECN_DSCRD_MSK_PACKET_COUNTER */ "", 51309 /* IQM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 51310 /* IQM_ENQUEUE_BYTE_COUNTER */ "", 51311 /* IQM_ENQUEUE_DISCARDED_PACKET_COUNTER */ "", 51312 /* IQM_ENQUEUE_PACKET_COUNTER */ "", 51313 /* IQM_ERROR_INITIATION_DATA */ "", 51314 /* IQM_FLOW_CONTROL_CONFIGURATION_FULL_MC_D_BS */ "", 51315 /* IQM_FLOW_CONTROL_CONFIGURATION_MINI_MC_D_BS */ "", 51316 /* IQM_FORCE_CMN */ "", 51317 /* IQM_FREE_BDB_MINIMUM_OCCUPANCY */ "", 51318 /* IQM_FREE_BDB_RANGE_VALUES */ "", 51319 /* IQM_FREE_BDB_THRESHOLD */ "", 51320 /* IQM_FREE_BDB_THRESHOLD_0 */ "", 51321 /* IQM_FREE_BDB_THRESHOLD_1 */ "", 51322 /* IQM_FREE_BDB_THRESHOLD_2 */ "", 51323 /* IQM_FREE_BD_COUNTER */ "", 51324 /* IQM_FREE_FULL_MULTICAST_DBUFFS_COUNTER */ "", 51325 /* IQM_FREE_FULL_MULTICAST_DBUFFS_MINIMUM_OCCUPANCY */ "", 51326 /* IQM_FREE_FULL_MULTICAST_DBUFF_RANGE_VALUES */ "", 51327 /* IQM_FREE_FULL_MULTICAST_DBUFF_THRESHOLD */ "", 51328 /* IQM_FREE_FULL_MULTICAST_DBUFF_THRESHOLD_0 */ "", 51329 /* IQM_FREE_FULL_MULTICAST_DBUFF_THRESHOLD_1 */ "", 51330 /* IQM_FREE_FULL_MULTICAST_DBUFF_THRESHOLD_2 */ "", 51331 /* IQM_FREE_MINI_MULTICAST_DBUFFS_COUNTER */ "", 51332 /* IQM_FREE_MINI_MULTICAST_DBUFFS_MINIMUM_OCCUPANCY */ "", 51333 /* IQM_FREE_MNMC_DBUFFS_MINIMUM_OCCUPANCY */ "", 51334 /* IQM_FREE_MNMC_DBUFF_RANGE_VALUES */ "", 51335 /* IQM_FREE_OCB_COUNTER */ "", 51336 /* IQM_FREE_OCB_COUNTERS */ "", 51337 /* IQM_FREE_OCB_MINIMUM_OCCUPANCY */ "", 51338 /* IQM_FREE_OCB_RANGE_VALUES */ "", 51339 /* IQM_FREE_OCB_THRESHOLD */ "", 51340 /* IQM_FREE_RESOURCE_REJECTED_PACKET_COUNTER_1 */ "", 51341 /* IQM_FREE_RESOURCE_REJECTED_PACKET_COUNTER_2 */ "", 51342 /* IQM_FREE_UNICAST_DBUFFS_COUNTER */ "", 51343 /* IQM_FREE_UNICAST_DBUFFS_MINIMUM_OCCUPANCY */ "", 51344 /* IQM_FREE_UNICAST_DBUFF_RANGE_VALUES */ "", 51345 /* IQM_FREE_UNICAST_DBUFF_THRESHOLD_0 */ "", 51346 /* IQM_FREE_UNICAST_DBUFF_THRESHOLD_1 */ "", 51347 /* IQM_FREE_UNICAST_DBUFF_THRESHOLD_2 */ "", 51348 /* IQM_FREE_U_MNMC_DBUFFS_COUNTER */ "", 51349 /* IQM_FREE_VOQ_DRAM_DYNAMIC_MINIMAL_OCCUPANCY */ "", 51350 /* IQM_FREE_VOQ_OCB_DYNAMIC_MINIMAL_OCCUPANCY */ "", 51351 /* IQM_FR_OCB_PRM_SEL_TH */ "", 51352 /* IQM_FR_RSRC_DYN_TH_SETTINGS */ "", 51353 /* IQM_FULL_USER_COUNT_START_INDEX */ "", 51354 /* IQM_GENERAL_CLEAR_FLOW_CONTROL_CONFIGURATION_D_BS_HIGH_PRIORITY */ "", 51355 /* IQM_GENERAL_CLEAR_FLOW_CONTROL_CONFIGURATION_D_BS_LOW_PRIORITY */ "", 51356 /* IQM_GENERAL_FLOW_CONTROL_CONFIGURATION_BDB */ "", 51357 /* IQM_GENERAL_FLOW_CONTROL_CONFIGURATION_BDB_HIGH_PRIORITY */ "", 51358 /* IQM_GENERAL_FLOW_CONTROL_CONFIGURATION_BDB_LOW_PRIORITY */ "", 51359 /* IQM_GENERAL_FLOW_CONTROL_CONFIGURATION_OCB */ "", 51360 /* IQM_GENERAL_REJECT_CLEAR_CONFIGURATION_D_BUFFS_0 */ "", 51361 /* IQM_GENERAL_REJECT_CLEAR_CONFIGURATION_D_BUFFS_1 */ "", 51362 /* IQM_GENERAL_REJECT_CLEAR_CONFIGURATION_D_BUFFS_2 */ "", 51363 /* IQM_GENERAL_REJECT_CLEAR_CONFIGURATION_D_BUFFS_3 */ "", 51364 /* IQM_GENERAL_REJECT_CONFIGURATION_BD_BS */ "", 51365 /* IQM_GENERAL_REJECT_CONFIGURATION_BD_BS_0 */ "", 51366 /* IQM_GENERAL_REJECT_CONFIGURATION_BD_BS_1 */ "", 51367 /* IQM_GENERAL_REJECT_CONFIGURATION_BD_BS_2 */ "", 51368 /* IQM_GENERAL_REJECT_CONFIGURATION_BD_BS_3 */ "", 51369 /* IQM_GENERAL_REJECT_CONFIGURATION_B_DS */ "", 51370 /* IQM_GENERAL_REJECT_CONFIGURATION_B_DS_0 */ "", 51371 /* IQM_GENERAL_REJECT_CONFIGURATION_B_DS_1 */ "", 51372 /* IQM_GENERAL_REJECT_CONFIGURATION_B_DS_2 */ "", 51373 /* IQM_GENERAL_REJECT_CONFIGURATION_B_DS_3 */ "", 51374 /* IQM_GENERAL_REJECT_SET_CONFIGURATION_D_BUFFS_0 */ "", 51375 /* IQM_GENERAL_REJECT_SET_CONFIGURATION_D_BUFFS_1 */ "", 51376 /* IQM_GENERAL_REJECT_SET_CONFIGURATION_D_BUFFS_2 */ "", 51377 /* IQM_GENERAL_REJECT_SET_CONFIGURATION_D_BUFFS_3 */ "", 51378 /* IQM_GENERAL_SET_FLOW_CONTROL_CONFIGURATION_D_BS_HIGH_PRIORITY */ "", 51379 /* IQM_GENERAL_SET_FLOW_CONTROL_CONFIGURATION_D_BS_LOW_PRIORITY */ "", 51380 /* IQM_GLBL_MIX_MAX_TH */ "", 51381 /* IQM_GLOBAL_FLOW_CONTROL_STATE */ "", 51382 /* IQM_GLOBAL_GENERAL_CFG_3 */ "", 51383 /* IQM_GLOBAL_GENERAL_CFG_4 */ "", 51384 /* IQM_GLOBAL_MEM_OPTIONS */ "", 51385 /* IQM_GLOBAL_REJECT_STATE */ "", 51386 /* IQM_GLOBAL_RESOURCE_COUNTERS */ "", 51387 /* IQM_GLOBAL_RESOURCE_COUNTERS_2 */ "", 51388 /* IQM_GLOBAL_RESOURCE_COUNTERS_BD */ "", 51389 /* IQM_GLOBAL_RESOURCE_COUNTERS_BD_2 */ "", 51390 /* IQM_GLOBAL_RESOURCE_MINIMUM_OCCUPANCY */ "", 51391 /* IQM_GLOBAL_TIME_COUNTER_CONFIGURATION */ "", 51392 /* IQM_GTIMER_CONFIGURATION */ "", 51393 /* IQM_GTIMER_CYCLE */ "", 51394 /* IQM_GTIMER_TRIGGER */ "", 51395 /* IQM_IDR_ERROR_REJECT_PACKET_COUNTERS */ "", 51396 /* IQM_INDIRECT_COMMAND */ "", 51397 /* IQM_INDIRECT_COMMAND_ADDRESS */ "", 51398 /* IQM_INDIRECT_COMMAND_DATA_INCREMENT */ "", 51399 /* IQM_INDIRECT_COMMAND_RD_DATA */ "", 51400 /* IQM_INDIRECT_COMMAND_WIDE_MEM */ "", 51401 /* IQM_INDIRECT_COMMAND_WR_DATA */ "", 51402 /* IQM_INDIRECT_FORCE_BUBBLE */ "", 51403 /* IQM_INDIRECT_WR_MASK */ "", 51404 /* IQM_INTERLOCK_CONFIG */ "", 51405 /* IQM_INTERLOCK_FMQ_TC_0_T_HS */ "", 51406 /* IQM_INTERLOCK_FMQ_TC_1_T_HS */ "", 51407 /* IQM_INTERLOCK_FMQ_TC_2_T_HS */ "", 51408 /* IQM_INTERLOCK_FMQ_TC_3_T_HS */ "", 51409 /* IQM_INTERLOCK_VOQ_TC_0_T_HS */ "", 51410 /* IQM_INTERLOCK_VOQ_TC_1_T_HS */ "", 51411 /* IQM_INTERLOCK_VOQ_TC_2_T_HS */ "", 51412 /* IQM_INTERLOCK_VOQ_TC_3_T_HS */ "", 51413 /* IQM_INTERNAL_FIFOS_THRESHOLDS */ "", 51414 /* IQM_INTERRUPT_MASK_REGISTER */ "", 51415 /* IQM_INTERRUPT_REGISTER */ "", 51416 /* IQM_INTERRUPT_REGISTER_TEST */ "", 51417 /* IQM_IQM_CNT_CMD_CONFIG_A */ "", 51418 /* IQM_IQM_CNT_CMD_CONFIG_B */ "", 51419 /* IQM_IQM_ENABLERS */ "", 51420 /* IQM_IQM_INIT */ "", 51421 /* IQM_IRPP_CNT_CMD_CONFIG_A */ "", 51422 /* IQM_IRPP_CNT_CMD_CONFIG_B */ "", 51423 /* IQM_IRR_ERROR_REJECTED_PACKET_COUNTERS */ "", 51424 /* IQM_ISP_PACKET_COUNTER */ "", 51425 /* IQM_LATENCY_SETTINGS */ "", 51426 /* IQM_LST_PDM_READ_ADDR */ "", 51427 /* IQM_LST_PDM_READ_DATA */ "", 51428 /* IQM_MAXIMUM_OCCUPANCY_QUEUE_SIZE */ "", 51429 /* IQM_MAXIMUM_OCCUPANCY_QUEUE_SIZE_0 */ "", 51430 /* IQM_MAXIMUM_OCCUPANCY_QUEUE_SIZE_1 */ "", 51431 /* IQM_MIX_SHRD_POOL_0_RSRC_FC_TH */ "", 51432 /* IQM_MIX_SHRD_POOL_0_RSRC_RJCT_TH */ "", 51433 /* IQM_MIX_SHRD_POOL_1_RSRC_FC_TH */ "", 51434 /* IQM_MIX_SHRD_POOL_1_RSRC_RJCT_TH */ "", 51435 /* IQM_OCB_DYN_SIZE_RJCT_TH_CFG */ "", 51436 /* IQM_OCB_SHRD_POOL_0_RSRC_FC_TH */ "", 51437 /* IQM_OCB_SHRD_POOL_0_RSRC_RJCT_TH */ "", 51438 /* IQM_OCB_SHRD_POOL_1_RSRC_FC_TH */ "", 51439 /* IQM_OCB_SHRD_POOL_1_RSRC_RJCT_TH */ "", 51440 /* IQM_OCCUPIED_BDB_COUNTER */ "", 51441 /* IQM_OCCUPIED_BD_COUNTER */ "", 51442 /* IQM_OCCUPIED_MNMC_DBUFFS_COUNTER */ "", 51443 /* IQM_OCCUPIED_UNICAST_DBUFFS_COUNTER */ "", 51444 /* IQM_ONE_WAY_BYPASS_MODE */ "", 51445 /* IQM_PACKET_QUEUES_CATEGORIES */ "", 51446 /* IQM_PACKET_QUEUES_CATEGORIES_0 */ "", 51447 /* IQM_PACKET_QUEUES_CATEGORIES_1 */ "", 51448 /* IQM_PACKET_QUEUES_CATEGORIES_2 */ "", 51449 /* IQM_PARITY_ERR_CNT */ "", 51450 /* IQM_PAR_ERR_INITIATE */ "", 51451 /* IQM_PAR_ERR_MEM_MASK */ "", 51452 /* IQM_PCMI_0 */ "", 51453 /* IQM_PCMI_1 */ "", 51454 /* IQM_PCMI_2 */ "", 51455 /* IQM_PCMI_3 */ "", 51456 /* IQM_PCMI_4 */ "", 51457 /* IQM_PCMI_0_S */ "", 51458 /* IQM_PCMI_0_T */ "", 51459 /* IQM_PCMI_1_S */ "", 51460 /* IQM_PCMI_1_T */ "", 51461 /* IQM_PCMI_2_S */ "", 51462 /* IQM_PCMI_2_T */ "", 51463 /* IQM_PCMI_3_S */ "", 51464 /* IQM_PCMI_3_T */ "", 51465 /* IQM_PCMI_4_S */ "", 51466 /* IQM_PCMI_4_T */ "", 51467 /* IQM_PDM_BD_EXT_CFG */ "", 51468 /* IQM_PDM_READ_CNT */ "", 51469 /* IQM_PDM_READ_RPLY_CNT */ "", 51470 /* IQM_PDM_VAL_READ_RPLY_CNT */ "", 51471 /* IQM_PORT_PROTECTION_SETTING */ "", 51472 /* IQM_PROGRAMMABLE_COUNTER_QUEUE_SELECT */ "", 51473 /* IQM_PROGRAMMABLE_COUNTER_QUEUE_SELECT_0 */ "", 51474 /* IQM_PROGRAMMABLE_COUNTER_QUEUE_SELECT_1 */ "", 51475 /* IQM_QDC_TAG_CTRL_DBG */ "", 51476 /* IQM_QDC_TAG_CTRL_DBG_SEL */ "", 51477 /* IQM_QM_RPRT_FIFO_MAX_STATUS */ "", 51478 /* IQM_QM_RPRT_FIFO_STATUS */ "", 51479 /* IQM_QM_RPRT_FIFO_THS */ "", 51480 /* IQM_QM_RPRT_TXI_NRDY_CTR */ "", 51481 /* IQM_QUEUE_DELETED_PACKET_COUNTER */ "", 51482 /* IQM_QUEUE_DEQUEUE_BYTE_COUNTER */ "", 51483 /* IQM_QUEUE_DEQUEUE_PACKET_COUNTER */ "", 51484 /* IQM_QUEUE_DEQ_DELETE_BYTE_COUNTER */ "", 51485 /* IQM_QUEUE_ENQUEUE_BYTE_COUNTER */ "", 51486 /* IQM_QUEUE_ENQUEUE_PACKET_COUNTER */ "", 51487 /* IQM_QUEUE_ENQ_DISCARDED_PACKET_COUNTER */ "", 51488 /* IQM_QUEUE_ENQ_DSCRD_BYTE_COUNTER */ "", 51489 /* IQM_QUEUE_MAXIMUM_OCCUPANCY_QUEUE_SIZE */ "", 51490 /* IQM_QUEUE_MAXIMUM_OCCUPANCY_QUEUE_SIZE_0 */ "", 51491 /* IQM_QUEUE_TOTAL_DISCARDED_PACKET_COUNTER */ "", 51492 /* IQM_RATE_CLASS_RD_WEIGHT */ "", 51493 /* IQM_REG_0041 */ "", 51494 /* IQM_REG_0085 */ "", 51495 /* IQM_REG_0090 */ "", 51496 /* IQM_REG_0091 */ "", 51497 /* IQM_REG_0092 */ "", 51498 /* IQM_REG_0093 */ "", 51499 /* IQM_REG_0124 */ "", 51500 /* IQM_REG_0236 */ "", 51501 /* IQM_REG_0237 */ "", 51502 /* IQM_REG_0239 */ "", 51503 /* IQM_REG_0241 */ "", 51504 /* IQM_REG_0243 */ "", 51505 /* IQM_REG_0245 */ "", 51506 /* IQM_REG_0258 */ "", 51507 /* IQM_REG_0259 */ "", 51508 /* IQM_REG_00A4 */ "", 51509 /* IQM_REG_00A6 */ "", 51510 /* IQM_REG_00A4_1 */ "", 51511 /* IQM_REG_00A4_2 */ "", 51512 /* IQM_REG_00AA */ "", 51513 /* IQM_REG_00AE */ "", 51514 /* IQM_REG_00B0 */ "", 51515 /* IQM_REG_00B1 */ "", 51516 /* IQM_REG_00B2 */ "", 51517 /* IQM_REG_00B3 */ "", 51518 /* IQM_REG_00B8 */ "", 51519 /* IQM_REG_00B9 */ "", 51520 /* IQM_REG_00BA */ "", 51521 /* IQM_REG_00BB */ "", 51522 /* IQM_REG_00BC */ "", 51523 /* IQM_REG_00BD */ "", 51524 /* IQM_REG_00BE */ "", 51525 /* IQM_REG_00BF */ "", 51526 /* IQM_REG_00C0 */ "", 51527 /* IQM_REG_00C1 */ "", 51528 /* IQM_REG_00C2 */ "", 51529 /* IQM_REG_00C3 */ "", 51530 /* IQM_REG_00C4 */ "", 51531 /* IQM_REG_00C5 */ "", 51532 /* IQM_REG_00C6 */ "", 51533 /* IQM_REG_00C7 */ "", 51534 /* IQM_REG_00C8 */ "", 51535 /* IQM_REG_00C9 */ "", 51536 /* IQM_REG_00CA */ "", 51537 /* IQM_REG_00CB */ "", 51538 /* IQM_REG_00CD */ "", 51539 /* IQM_REG_00CE */ "", 51540 /* IQM_REG_012C */ "", 51541 /* IQM_REG_023B */ "", 51542 /* IQM_REG_023D */ "", 51543 /* IQM_REG_023F */ "", 51544 /* IQM_REG_AF */ "", 51545 /* IQM_REJECT_ADMISSION */ "", 51546 /* IQM_REJECT_ADMISSION_A */ "", 51547 /* IQM_REJECT_ADMISSION_B */ "", 51548 /* IQM_REJECT_CONFIGURATION_FULL_MC_D_BS */ "", 51549 /* IQM_REJECT_CONFIGURATION_MINI_MC_D_BS */ "", 51550 /* IQM_REJECT_CONFIGURATION_OCBS */ "", 51551 /* IQM_REJECT_STATUS_BMP */ "", 51552 /* IQM_RESERVED_MIRROR_ADDR */ "", 51553 /* IQM_RESERVED_MTCD */ "", 51554 /* IQM_RESERVED_MTCP */ "", 51555 /* IQM_RESERVED_SPARE_0 */ "", 51556 /* IQM_RESERVED_SPARE_1 */ "", 51557 /* IQM_RESERVED_SPARE_2 */ "", 51558 /* IQM_RESERVED_SPARE_3 */ "", 51559 /* IQM_RJCT_BDB_PKT_CNT */ "", 51560 /* IQM_RJCT_BDB_PROTCT_PKT_CNT */ "", 51561 /* IQM_RJCT_BUFF_TYPE_ERR_PKT_CNT */ "", 51562 /* IQM_RJCT_CNM_PCKT_CNT */ "", 51563 /* IQM_RJCT_DB_PKT_CNT */ "", 51564 /* IQM_RJCT_DRAM_INELIGIBLE_PKT_CNT */ "", 51565 /* IQM_RJCT_GLBL_TESTS_MASK */ "", 51566 /* IQM_RJCT_ISP_DUP_PKT_CNT */ "", 51567 /* IQM_RJCT_MC_ERR_PKT_CNT */ "", 51568 /* IQM_RJCT_MC_OCB_TH_0 */ "", 51569 /* IQM_RJCT_MC_OCB_TH_1 */ "", 51570 /* IQM_RJCT_MC_OCB_TH_2 */ "", 51571 /* IQM_RJCT_MC_OCB_TH_3 */ "", 51572 /* IQM_RJCT_OC_BD_PKT_CNT */ "", 51573 /* IQM_RJCT_QNUM_OVF_PKT_CNT */ "", 51574 /* IQM_RJCT_QNVALID_ERR_PKT_CNT */ "", 51575 /* IQM_RJCT_RSRC_ERR_PKT_CNT */ "", 51576 /* IQM_RJCT_UC_OCB_TH_0 */ "", 51577 /* IQM_RJCT_UC_OCB_TH_1 */ "", 51578 /* IQM_RJCT_UC_OCB_TH_2 */ "", 51579 /* IQM_RJCT_UC_OCB_TH_3 */ "", 51580 /* IQM_SBUS_BROADCAST_ID */ "", 51581 /* IQM_SBUS_LAST_IN_CHAIN */ "", 51582 /* IQM_SCH_CMP_PTR_MAP */ "", 51583 /* IQM_SRAM_TO_DRAM_LATENCY */ "", 51584 /* IQM_SRAM_TO_DRAM_LATENCY_AVRG */ "", 51585 /* IQM_SRAM_TO_DRAM_LATENCY_MAX */ "", 51586 /* IQM_SRC_VSQ_GLBL_MIXED_HEADROOM_MIN_OCCUPANCY_LEVEL */ "", 51587 /* IQM_SRC_VSQ_GLBL_MIXED_HEADROOM_OCCUPANCY_LEVEL */ "", 51588 /* IQM_SRC_VSQ_GLBL_MIXED_SHARED_POOL_0_MIN_OCCUPANCY_LEVEL */ "", 51589 /* IQM_SRC_VSQ_GLBL_MIXED_SHARED_POOL_0_OCCUPANCY_LEVEL */ "", 51590 /* IQM_SRC_VSQ_GLBL_MIXED_SHARED_POOL_1_MIN_OCCUPANCY_LEVEL */ "", 51591 /* IQM_SRC_VSQ_GLBL_MIXED_SHARED_POOL_1_OCCUPANCY_LEVEL */ "", 51592 /* IQM_SRC_VSQ_GLBL_OCB_HEADROOM_MIN_OCCUPANCY_LEVEL */ "", 51593 /* IQM_SRC_VSQ_GLBL_OCB_HEADROOM_OCCUPANCY_LEVEL */ "", 51594 /* IQM_SRC_VSQ_GLBL_OCB_MAX_TH */ "", 51595 /* IQM_SRC_VSQ_GLBL_OCB_SHARED_POOL_0_MIN_OCCUPANCY_LEVEL */ "", 51596 /* IQM_SRC_VSQ_GLBL_OCB_SHARED_POOL_0_OCCUPANCY_LEVEL */ "", 51597 /* IQM_SRC_VSQ_GLBL_OCB_SHARED_POOL_1_MIN_OCCUPANCY_LEVEL */ "", 51598 /* IQM_SRC_VSQ_GLBL_OCB_SHARED_POOL_1_OCCUPANCY_LEVEL */ "", 51599 /* IQM_STATISTICST_DROP_COUNTER_0 */ "", 51600 /* IQM_STATISTICST_DROP_COUNTER_1 */ "", 51601 /* IQM_STATISTICS_BILL_REPORT_CONFIGURATION */ "", 51602 /* IQM_STATISTICS_REPORT_CONFIGURATIONS */ "", 51603 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_2 */ "", 51604 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_3 */ "", 51605 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_4 */ "", 51606 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_5 */ "", 51607 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_6 */ "", 51608 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_7 */ "", 51609 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_8 */ "", 51610 /* IQM_STATISTICS_REPORT_CONFIGURATIONS_9 */ "", 51611 /* IQM_STATISTICS_REPORT_QUEUE_RANGE_0 */ "", 51612 /* IQM_STATISTICS_REPORT_QUEUE_RANGE_1 */ "", 51613 /* IQM_STATISTICS_SCR_QUEUE_RANGE */ "", 51614 /* IQM_STATISTICS_TAG_CONFIGURATION */ "", 51615 /* IQM_STE_ENABLERS */ "", 51616 /* IQM_STE_RJCT_TESTS_MASK */ "", 51617 /* IQM_SYSTEM_RED_FREE_MNMC_DBUFF_THRESHOLD */ "", 51618 /* IQM_TOTAL_DISCARDED_PACKET_COUNTER */ "", 51619 /* IQM_TOT_DELETE_BYTE_COUNTER */ "", 51620 /* IQM_TOT_DSCRD_BYTE_COUNTER */ "", 51621 /* IQM_TO_DRAM_CMD_TXI_NRDY_CTR */ "", 51622 /* IQM_TO_FABRIC_CMD_TXI_NRDY_CTR */ "", 51623 /* IQM_VOQ_FADT_DYN_SIZE_SHRD_TH */ "", 51624 /* IQM_VSQ_DEQUEUE_PACKET_COUNTER */ "", 51625 /* IQM_VSQ_ENQUEUE_PACKET_COUNTER */ "", 51626 /* IQM_VSQ_MAXIMUM_OCCUPANCY_0 */ "", 51627 /* IQM_VSQ_MAXIMUM_OCCUPANCY_1 */ "", 51628 /* IQM_VSQ_PG_IS_OCB_ONLY */ "", 51629 /* IQM_VSQ_PROGRAMMABLE_COUNTER_SELECT */ "", 51630 /* IR64 */ "MAC_GRx64", 51631 /* IR127 */ "MAC_GRx127", 51632 /* IR255 */ "MAC_GRx255", 51633 /* IR511 */ "MAC_GRx511", 51634 /* IR1023 */ "MAC_GRx1023", 51635 /* IR1518 */ "MAC_GRx1518", 51636 /* IR2047 */ "MAC_GRx2047", 51637 /* IR4095 */ "MAC_GRx4095", 51638 /* IR9216 */ "MAC_GRx9216", 51639 /* IR16383 */ "MAC_GRx16383", 51640 /* IRBCA */ "MAC_GRxBCA", 51641 /* IRBYT */ "MAC_GRxByt", 51642 /* IRERBYT */ "MAC_GRxErrByt", 51643 /* IRERPKT */ "MAC_GRxFrErr", 51644 /* IRE_ALIGN_CONFIG */ "", 51645 /* IRE_ALIGN_DEBUG */ "", 51646 /* IRE_AUTO_DOC_NAME_2 */ "", 51647 /* IRE_BAD_REASSEMBLY_CONTEXT_PACKET_COUNTER */ "", 51648 /* IRE_BLAME_REGISTER */ "", 51649 /* IRE_CHICKEN_BITS */ "", 51650 /* IRE_CMIC_PKT_SRC_ID_DEST_IS_OAMP */ "", 51651 /* IRE_COMPATIBILITY_REGISTER */ "", 51652 /* IRE_CPU_CHANNEL */ "", 51653 /* IRE_CPU_CHANNEL_CONFIGURATION */ "", 51654 /* IRE_CPU_CHANNEL_IS_TDM */ "", 51655 /* IRE_CPU_CHANNEL_PIPE_MAP */ "", 51656 /* IRE_CPU_CREDITS_CNT */ "", 51657 /* IRE_CPU_CREDITS_COUNTER */ "", 51658 /* IRE_CPU_PACKET_COUNTER */ "", 51659 /* IRE_CPU_SHAPER */ "", 51660 /* IRE_DYNAMIC_CONFIGURATION */ "", 51661 /* IRE_ECC_1B_ERR_CNT */ "", 51662 /* IRE_ECC_2B_ERR_CNT */ "", 51663 /* IRE_ECC_ERR_1B_INITIATE */ "", 51664 /* IRE_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 51665 /* IRE_ECC_ERR_2B_INITIATE */ "", 51666 /* IRE_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 51667 /* IRE_ECC_INTERRUPT_REGISTER */ "", 51668 /* IRE_ECC_INTERRUPT_REGISTER_MASK */ "", 51669 /* IRE_ECC_INTERRUPT_REGISTER_TEST */ "", 51670 /* IRE_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 51671 /* IRE_ERROR_INITIATION_DATA */ "", 51672 /* IRE_EVENTOR_CREDITS_COUNTER */ "", 51673 /* IRE_EVENTOR_PACKET_COUNTER */ "", 51674 /* IRE_EVENTOR_REASSEMBLY_CONTEXT_CONFIGURATION */ "", 51675 /* IRE_EXTERNAL_IF_ERROR_INTERRUPT_REGISTER */ "", 51676 /* IRE_EXTERNAL_IF_ERROR_INTERRUPT_REGISTER_MASK */ "", 51677 /* IRE_EXTERNAL_IF_ERROR_INTERRUPT_REGISTER_TEST */ "", 51678 /* IRE_FDT_CREDITS_CNT */ "", 51679 /* IRE_FDT_INTERFACE_COUNTER */ "", 51680 /* IRE_GLOBAL_GENERAL_CFG_2 */ "", 51681 /* IRE_GLOBAL_GENERAL_CFG_3 */ "", 51682 /* IRE_GLOBAL_MEM_OPTIONS */ "", 51683 /* IRE_GLOBAL_SYS_HEADER_CFG */ "", 51684 /* IRE_GTIMER_CONFIGURATION */ "", 51685 /* IRE_GTIMER_CYCLE */ "", 51686 /* IRE_GTIMER_TRIGGER */ "", 51687 /* IRE_IDR_INTERFACE_COUNTER */ "", 51688 /* IRE_IHB_DEBUG_REGISTER_1 */ "", 51689 /* IRE_IHB_DEBUG_REGISTER_2 */ "", 51690 /* IRE_IHB_DEBUG_REGISTER_3 */ "", 51691 /* IRE_IHB_INTERFACE_COUNTER */ "", 51692 /* IRE_IHB_TM_CMD_HALF_1 */ "", 51693 /* IRE_IHB_TM_CMD_HALF_2 */ "", 51694 /* IRE_IHP_DEBUG_REGISTER */ "", 51695 /* IRE_IHP_FIFO_STATUS */ "", 51696 /* IRE_IHP_FIFO_THRESHOLDS */ "", 51697 /* IRE_IHP_INTERFACE_COUNTER */ "", 51698 /* IRE_IHP_SHAPER */ "", 51699 /* IRE_IHP_STATUS_REGISTER */ "", 51700 /* IRE_IHP_SYNC_CLKS_CNT */ "", 51701 /* IRE_INDIRECT_COMMAND */ "", 51702 /* IRE_INDIRECT_COMMAND_ADDRESS */ "", 51703 /* IRE_INDIRECT_COMMAND_DATA_INCREMENT */ "", 51704 /* IRE_INDIRECT_COMMAND_RD_DATA */ "", 51705 /* IRE_INDIRECT_COMMAND_WIDE_MEM */ "", 51706 /* IRE_INDIRECT_COMMAND_WR_DATA */ "", 51707 /* IRE_INDIRECT_FORCE_BUBBLE */ "", 51708 /* IRE_INDIRECT_WR_MASK */ "", 51709 /* IRE_INTERFACE_BASE_ADDR_CONFIGURATION */ "", 51710 /* IRE_INTERFACE_PORT_CONFIGURATION */ "", 51711 /* IRE_INTERNAL_INTERFACE_ERROR_INTERRUPT_REGISTER */ "", 51712 /* IRE_INTERNAL_INTERFACE_ERROR_INTERRUPT_REGISTER_MASK */ "", 51713 /* IRE_INTERNAL_INTERFACE_ERROR_INTERRUPT_REGISTER_TEST */ "", 51714 /* IRE_INTERRUPT_MASK_REGISTER */ "", 51715 /* IRE_INTERRUPT_REGISTER */ "", 51716 /* IRE_INTERRUPT_REGISTER_TEST */ "", 51717 /* IRE_INVALID_INTERFACE */ "", 51718 /* IRE_IPSEC_CREDITS_COUNTER */ "", 51719 /* IRE_IPSEC_PACKET_COUNTER */ "", 51720 /* IRE_IPSEC_REASSEMBLY_CONTEXT_CONFIGURATION */ "", 51721 /* IRE_IPV6_SR_CONFIGURATION */ "", 51722 /* IRE_IPV6_SR_DEBUG */ "", 51723 /* IRE_IRE_REGISTER_0 */ "", 51724 /* IRE_IRR_DEBUG_REGISTER */ "", 51725 /* IRE_LAST_CONTEXT_MAPPING */ "", 51726 /* IRE_LAST_RECEIVED_PACKET_RECORD */ "", 51727 /* IRE_NETWORK_INTERFACE_SHAPER */ "", 51728 /* IRE_NIF_CREDITS_CNT */ "", 51729 /* IRE_NIF_CREDITS_COUNTER */ "", 51730 /* IRE_NIF_ERROR_INTERRUPT_REGISTER */ "", 51731 /* IRE_NIF_ERROR_INTERRUPT_REGISTER_MASK */ "", 51732 /* IRE_NIF_ERROR_INTERRUPT_REGISTER_TEST */ "", 51733 /* IRE_NIF_PACKET_COUNTER */ "", 51734 /* IRE_OAMP_CREDITS_CNT */ "", 51735 /* IRE_OAMP_CREDITS_COUNTER */ "", 51736 /* IRE_OAMP_FAP_PORT_CONFIGURATION */ "", 51737 /* IRE_OAMP_PACKET_COUNTER */ "", 51738 /* IRE_OAMP_REASSEMBLY_CONTEXT_CONFIGURATION */ "", 51739 /* IRE_OAMP_TX_INTERFACE_COUNTER */ "", 51740 /* IRE_OLP_CREDITS_CNT */ "", 51741 /* IRE_OLP_CREDITS_COUNTER */ "", 51742 /* IRE_OLP_FAP_PORT_CONFIGURATION */ "", 51743 /* IRE_OLP_PACKET_COUNTER */ "", 51744 /* IRE_OLP_REASSEMBLY_CONTEXT_CONFIGURATION */ "", 51745 /* IRE_PACKET_EDIT_FIFO_STATUS */ "", 51746 /* IRE_PACKET_EDIT_FIFO_THRESHOLDS */ "", 51747 /* IRE_PARITY_ERR_CNT */ "", 51748 /* IRE_PAR_ERR_INITIATE */ "", 51749 /* IRE_PAR_ERR_MEM_MASK */ "", 51750 /* IRE_PCMI_0 */ "", 51751 /* IRE_PCMI_1 */ "", 51752 /* IRE_PCMI_2 */ "", 51753 /* IRE_PCMI_3 */ "", 51754 /* IRE_PCMI_4 */ "", 51755 /* IRE_PCMI_0_S */ "", 51756 /* IRE_PCMI_0_T */ "", 51757 /* IRE_PCMI_1_S */ "", 51758 /* IRE_PCMI_1_T */ "", 51759 /* IRE_PCMI_2_S */ "", 51760 /* IRE_PCMI_2_T */ "", 51761 /* IRE_PCMI_3_S */ "", 51762 /* IRE_PCMI_3_T */ "", 51763 /* IRE_PCMI_4_S */ "", 51764 /* IRE_PCMI_4_T */ "", 51765 /* IRE_PEF_STATUS_REGISTER */ "", 51766 /* IRE_PIPE_BAD_REASSEMBLY_CONTEXT_PACKET_COUNTER */ "", 51767 /* IRE_PPLB_CFG */ "", 51768 /* IRE_PPLB_CFG_LSB */ "", 51769 /* IRE_PPLB_CFG_MSB */ "", 51770 /* IRE_RCYH_CREDITS_COUNTER */ "", 51771 /* IRE_RCYH_PACKET_COUNTER */ "", 51772 /* IRE_RCYL_CREDITS_COUNTER */ "", 51773 /* IRE_RCYL_PACKET_COUNTER */ "", 51774 /* IRE_RCY_CONFIGURATIONS */ "", 51775 /* IRE_RCY_CREDITS_CNT */ "", 51776 /* IRE_RCY_CREDITS_COUNTER */ "", 51777 /* IRE_RCY_INTERFACE_ERROR_INTERRUPT_REGISTER */ "", 51778 /* IRE_RCY_INTERFACE_ERROR_INTERRUPT_REGISTER_MASK */ "", 51779 /* IRE_RCY_INTERFACE_ERROR_INTERRUPT_REGISTER_TEST */ "", 51780 /* IRE_RCY_PACKET_COUNTER */ "", 51781 /* IRE_RECYCLING_SHAPER */ "", 51782 /* IRE_REGISTER_INTERFACE_PACKET_CONTROL */ "", 51783 /* IRE_REGISTER_INTERFACE_PACKET_COUNTER */ "", 51784 /* IRE_REGISTER_INTERFACE_PACKET_DATA_BITS_1023_512 */ "", 51785 /* IRE_REGISTER_INTERFACE_PACKET_DATA_BITS_1535_1024 */ "", 51786 /* IRE_REGISTER_INTERFACE_PACKET_DATA_BITS_2047_1536 */ "", 51787 /* IRE_REGISTER_INTERFACE_PACKET_DATA_BITS_511_0 */ "", 51788 /* IRE_REGI_PACKET_COUNTER */ "", 51789 /* IRE_REGI_PKT_DATA */ "", 51790 /* IRE_REG_0085 */ "", 51791 /* IRE_REG_0090 */ "", 51792 /* IRE_REG_0091 */ "", 51793 /* IRE_REG_0092 */ "", 51794 /* IRE_REG_0093 */ "", 51795 /* IRE_REG_0114 */ "", 51796 /* IRE_REG_0118 */ "", 51797 /* IRE_REG_0200 */ "", 51798 /* IRE_REG_00A4 */ "", 51799 /* IRE_REG_00A6 */ "", 51800 /* IRE_REG_00AA */ "", 51801 /* IRE_REG_00AE */ "", 51802 /* IRE_REG_00AF */ "", 51803 /* IRE_REG_00B8 */ "", 51804 /* IRE_REG_00B9 */ "", 51805 /* IRE_REG_00BA */ "", 51806 /* IRE_REG_00BB */ "", 51807 /* IRE_REG_00C1 */ "", 51808 /* IRE_REG_00C2 */ "", 51809 /* IRE_REG_00C4 */ "", 51810 /* IRE_REG_00C5 */ "", 51811 /* IRE_REG_00C6 */ "", 51812 /* IRE_REG_00CF */ "", 51813 /* IRE_REG_011B */ "", 51814 /* IRE_REG_012D */ "", 51815 /* IRE_REG_FAP_PORT_CONFIGURATION */ "", 51816 /* IRE_REG_REASSEMBLY_CONTEXT_CONFIGURATION */ "", 51817 /* IRE_RESERVED_MIRROR_ADDR */ "", 51818 /* IRE_RESERVED_MTCD */ "", 51819 /* IRE_RESERVED_MTCP */ "", 51820 /* IRE_RESERVED_SPARE_0 */ "", 51821 /* IRE_RESERVED_SPARE_1 */ "", 51822 /* IRE_RESERVED_SPARE_2 */ "", 51823 /* IRE_RESERVED_SPARE_3 */ "", 51824 /* IRE_RESET_STATUS_REGISTER */ "", 51825 /* IRE_SAT_CREDITS_COUNTER */ "", 51826 /* IRE_SAT_PACKET_COUNTER */ "", 51827 /* IRE_SAT_TDM_PACKET_COUNTER */ "", 51828 /* IRE_SBUS_BROADCAST_ID */ "", 51829 /* IRE_SBUS_LAST_IN_CHAIN */ "", 51830 /* IRE_SET_FTMH_VERSION */ "", 51831 /* IRE_SPB_INTERFACE_COUNTER */ "", 51832 /* IRE_SPB_SHAPER */ "", 51833 /* IRE_SPECIAL_CLOCK_CONTROLS */ "", 51834 /* IRE_STATIC_CONFIGURATION */ "", 51835 /* IRE_SYS_CFG_RESERVED_1 */ "", 51836 /* IRE_TAG_SWAP_CONFIGURATION */ "", 51837 /* IRE_TAG_SWAP_ENABLE */ "", 51838 /* IRE_TAR_DEBUG_REGISTER */ "", 51839 /* IRE_TAR_STATUS_REGISTER */ "", 51840 /* IRE_TDM_CONFIGURATIONS */ "", 51841 /* IRE_TDM_CONTEXT_DROP */ "", 51842 /* IRE_TDM_CONTEXT_MAP */ "", 51843 /* IRE_TDM_MODE_MAP */ "", 51844 /* IRE_TDM_PACKET_COUNTER */ "", 51845 /* IRE_TDM_SIZE */ "", 51846 /* IRE_WATERMARK_REG */ "", 51847 /* IRE_WORD_FIFO_STATUS */ "", 51848 /* IRE_WORD_FIFO_THRESHOLDS */ "", 51849 /* IRFCS */ "MAC_GRxFCS", 51850 /* IRFLR */ "MAC_GRxFLR", 51851 /* IRFRG */ "MAC_GRxFrg", 51852 /* IRJBR */ "MAC_GRxJbr", 51853 /* IRJUNK */ "MAC_GRxIPJ", 51854 /* IRMAX */ "MAC_GRxMax", 51855 /* IRMCA */ "MAC_GRxMCA", 51856 /* IRMEB */ "MAC_GRxMEB", 51857 /* IRMEG */ "MAC_GRxMEG", 51858 /* IROVR */ "MAC_GRxOvr", 51859 /* IRPKT */ "MAC_GRxPkt", 51860 /* IRPOK */ "MAC_GRxPOK", 51861 /* IRR_ARBITER_CONFIGURATION */ "", 51862 /* IRR_BLAME_REGISTER */ "", 51863 /* IRR_COMPATIBILITY_REGISTER */ "", 51864 /* IRR_DYNAMIC_CONFIGURATION */ "", 51865 /* IRR_ECC_1B_ERR_CNT */ "", 51866 /* IRR_ECC_2B_ERR_CNT */ "", 51867 /* IRR_ECC_ERR_1B_INITIATE */ "", 51868 /* IRR_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 51869 /* IRR_ECC_ERR_2B_INITIATE */ "", 51870 /* IRR_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 51871 /* IRR_ECC_INTERRUPT_REGISTER */ "", 51872 /* IRR_ECC_INTERRUPT_REGISTER_MASK */ "", 51873 /* IRR_ECC_INTERRUPT_REGISTER_TEST */ "", 51874 /* IRR_EGQ_INTERFACE_COUNTER */ "", 51875 /* IRR_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 51876 /* IRR_ERROR_INITIATION_DATA */ "", 51877 /* IRR_ERR_IS_MAX_REPLICATION_MCID */ "", 51878 /* IRR_ERR_IS_REPLICATION_EMPTY_MCID */ "", 51879 /* IRR_ERR_MAX_REPLICATION_MCID */ "", 51880 /* IRR_ERR_REPLICATION_EMPTY_MCID */ "", 51881 /* IRR_ERR_REPLICATION_REGISTER */ "", 51882 /* IRR_FABRIC_MC_BASE_QUEUE */ "", 51883 /* IRR_FABRIC_MULTICAST_BASE_QUEUE */ "", 51884 /* IRR_FLOW_BASE_QUEUE */ "", 51885 /* IRR_FLOW_CONTROL_THRESHOLDS */ "", 51886 /* IRR_GLOBAL_GENERAL_CFG_3 */ "", 51887 /* IRR_GLOBAL_INGRESS_MULTICAST_INDICATION */ "", 51888 /* IRR_GLOBAL_MEM_OPTIONS */ "", 51889 /* IRR_GLOBAL_PP_7 */ "", 51890 /* IRR_GTIMER_CONFIGURATION */ "", 51891 /* IRR_GTIMER_TRIGGER */ "", 51892 /* IRR_IDR_INTERFACE_COUNTER */ "", 51893 /* IRR_IDR_READY_CLKS_CNT */ "", 51894 /* IRR_INDIRECT_COMMAND */ "", 51895 /* IRR_INDIRECT_COMMAND_ADDRESS */ "", 51896 /* IRR_INDIRECT_COMMAND_DATA_INCREMENT */ "", 51897 /* IRR_INDIRECT_COMMAND_RD_DATA */ "", 51898 /* IRR_INDIRECT_COMMAND_WIDE_MEM */ "", 51899 /* IRR_INDIRECT_COMMAND_WR_DATA */ "", 51900 /* IRR_INDIRECT_FORCE_BUBBLE */ "", 51901 /* IRR_INDIRECT_WR_MASK */ "", 51902 /* IRR_INTERRUPT_MASK_REGISTER */ "", 51903 /* IRR_INTERRUPT_REGISTER */ "", 51904 /* IRR_INTERRUPT_REGISTER_TEST */ "", 51905 /* IRR_IQM_CREDITS_CNT */ "", 51906 /* IRR_IQM_DATA_READY_CLKS_CNT */ "", 51907 /* IRR_IQM_ENQUEUE_COMMAND */ "", 51908 /* IRR_IQM_INTERFACE_COUNTER */ "", 51909 /* IRR_IQM_INVALID_DESTINATION_QUEUE */ "", 51910 /* IRR_IQM_SENT_PACKET_COUNTER */ "", 51911 /* IRR_IRR_CREDITS_CNT */ "", 51912 /* IRR_IS_IQM_INTERFACE_COUNTER */ "", 51913 /* IRR_IS_IQM_PC */ "", 51914 /* IRR_MAX_REPLICATIONS */ "", 51915 /* IRR_MCR_FIFO_CONFIG */ "", 51916 /* IRR_MC_ERR_STATUS_BMP */ "", 51917 /* IRR_MC_FIFO_DROP_CNT */ "", 51918 /* IRR_MIRROR_SIZE */ "", 51919 /* IRR_MULTICAST_FIFO_THRESHOLD */ "", 51920 /* IRR_MULTICAST_FIFO_THRESHOLDS */ "", 51921 /* IRR_OUTLIF_SELECTION */ "", 51922 /* IRR_PARITY_ERR_CNT */ "", 51923 /* IRR_PAR_ERR_INITIATE */ "", 51924 /* IRR_PAR_ERR_MEM_MASK */ "", 51925 /* IRR_PORT_IS_OUTBOUND_MIRROR */ "", 51926 /* IRR_REG_0085 */ "", 51927 /* IRR_REG_0090 */ "", 51928 /* IRR_REG_0091 */ "", 51929 /* IRR_REG_0092 */ "", 51930 /* IRR_REG_0093 */ "", 51931 /* IRR_REG_0168 */ "", 51932 /* IRR_REG_0200 */ "", 51933 /* IRR_REG_0201 */ "", 51934 /* IRR_REG_0202 */ "", 51935 /* IRR_REG_0208 */ "", 51936 /* IRR_REG_0209 */ "", 51937 /* IRR_REG_0210 */ "", 51938 /* IRR_REG_0216 */ "", 51939 /* IRR_REG_0217 */ "", 51940 /* IRR_REG_0218 */ "", 51941 /* IRR_REG_0219 */ "", 51942 /* IRR_REG_00AE */ "", 51943 /* IRR_REG_00AF */ "", 51944 /* IRR_REG_00B0 */ "", 51945 /* IRR_REG_00B1 */ "", 51946 /* IRR_REG_00B2 */ "", 51947 /* IRR_REG_00B3 */ "", 51948 /* IRR_REG_00CF */ "", 51949 /* IRR_REG_020F */ "", 51950 /* IRR_REG_021A */ "", 51951 /* IRR_REPLICATOION_ENGINES_CONFIGURATION */ "", 51952 /* IRR_RESEQUENCER_FIFO_INDEX */ "", 51953 /* IRR_RESERVED_MIRROR_ADDR */ "", 51954 /* IRR_RESERVED_MTCD */ "", 51955 /* IRR_RESERVED_MTCP */ "", 51956 /* IRR_RESERVED_PCMI_0 */ "", 51957 /* IRR_RESERVED_PCMI_1 */ "", 51958 /* IRR_RESERVED_PCMI_2 */ "", 51959 /* IRR_RESERVED_PCMI_3 */ "", 51960 /* IRR_RESERVED_PCMI_4 */ "", 51961 /* IRR_RESERVED_PCMI_0_S */ "", 51962 /* IRR_RESERVED_PCMI_0_T */ "", 51963 /* IRR_RESERVED_PCMI_1_S */ "", 51964 /* IRR_RESERVED_PCMI_1_T */ "", 51965 /* IRR_RESERVED_PCMI_2_S */ "", 51966 /* IRR_RESERVED_PCMI_2_T */ "", 51967 /* IRR_RESERVED_PCMI_3_S */ "", 51968 /* IRR_RESERVED_PCMI_3_T */ "", 51969 /* IRR_RESERVED_PCMI_4_S */ "", 51970 /* IRR_RESERVED_PCMI_4_T */ "", 51971 /* IRR_RESERVED_SPARE_0 */ "", 51972 /* IRR_RESERVED_SPARE_1 */ "", 51973 /* IRR_RESERVED_SPARE_2 */ "", 51974 /* IRR_RESERVED_SPARE_3 */ "", 51975 /* IRR_RESET_STATUS_REGISTER */ "", 51976 /* IRR_SBUS_BROADCAST_ID */ "", 51977 /* IRR_SBUS_LAST_IN_CHAIN */ "", 51978 /* IRR_SNOOP_SIZE */ "", 51979 /* IRR_STATIC_CONFIGURATION */ "", 51980 /* IRR_UC_FIFO_DROP_CNT */ "", 51981 /* IRR_UC_FIFO_FULL_DROP_CNT */ "", 51982 /* IRR_UC_FIFO_MIRROR_DROP_CNT */ "", 51983 /* IRR_UC_FIFO_SNOOP_DROP_CNT */ "", 51984 /* IRR_UC_FIFO_TH_CONFIG */ "", 51985 /* IRR_UNICAST_FIFO_THRESHOLDS */ "", 51986 /* IRR_WATERMARK_REG */ "", 51987 /* IRR_WATERMARK_REG_0 */ "", 51988 /* IRR_WATERMARK_REG_1 */ "", 51989 /* IRR_WATERMARK_REG_2 */ "", 51990 /* IRR_WATERMARK_REG_3 */ "", 51991 /* IRR_WATERMARK_REG_4 */ "", 51992 /* IRSEL1_CLK_GATING_CONTROL */ "", 51993 /* IRSEL1_EN_COR_ERR_RPT */ "", 51994 /* IRSEL1_RMEP_PDA_CONTROL */ "", 51995 /* IRSEL1_SER_CONTROL */ "", 51996 /* IRSEL2_CLK_GATING_CONTROL */ "", 51997 /* IRSEL2_EN_COR_ERR_RPT */ "", 51998 /* IRSEL2_IPMC_PDA_CONTROL */ "", 51999 /* IRSEL2_NEXT_HOP_PDA_CONTROL */ "", 52000 /* IRSEL2_SER_CONTROL */ "", 52001 /* IRSEL_EN_COR_ERR_RPT */ "", 52002 /* IRSEL_SER_CONTROL */ "", 52003 /* IRSEL_TM_REG_1 */ "", 52004 /* IRUC */ "MAC_GRxUC", 52005 /* IRUCA */ "MAC_GRxUCA", 52006 /* IRUND */ "MAC_GRxUnd", 52007 /* IRXCF */ "MAC_GRxCF", 52008 /* IRXPF */ "MAC_GRxPF", 52009 /* IRXPP */ "MAC_GRxPP", 52010 /* IRXUO */ "MAC_GRxUO", 52011 /* ISEC_AES_CALC_ICV_REG0 */ "", 52012 /* ISEC_AES_CALC_ICV_REG1 */ "", 52013 /* ISEC_AES_CALC_ICV_REG2 */ "", 52014 /* ISEC_AES_CALC_ICV_REG3 */ "", 52015 /* ISEC_AES_CNTRL */ "", 52016 /* ISEC_AES_ICV_FAIL_CNT */ "", 52017 /* ISEC_AES_ICV_PASS_CNT */ "", 52018 /* ISEC_AES_RCV_ICV_REG0 */ "", 52019 /* ISEC_AES_RCV_ICV_REG1 */ "", 52020 /* ISEC_AES_RCV_ICV_REG2 */ "", 52021 /* ISEC_AES_RCV_ICV_REG3 */ "", 52022 /* ISEC_AES_STATUS */ "", 52023 /* ISEC_CNTRL */ "", 52024 /* ISEC_CPU_MAC_ADDR0 */ "", 52025 /* ISEC_CPU_MAC_ADDR1 */ "", 52026 /* ISEC_CRC_APPEND */ "", 52027 /* ISEC_DEBUG_1 */ "", 52028 /* ISEC_DEBUG_PKT_CAPTURE */ "", 52029 /* ISEC_ECC_ERROR */ "", 52030 /* ISEC_ECC_ERROR_MASK */ "", 52031 /* ISEC_ERR_PKT_CNT */ "", 52032 /* ISEC_ETYPE_CONFIG */ "", 52033 /* ISEC_ETYPE_MAX_LEN */ "", 52034 /* ISEC_FIPS_CONTROL */ "", 52035 /* ISEC_FIPS_DATA_REG0 */ "", 52036 /* ISEC_FIPS_DATA_REG1 */ "", 52037 /* ISEC_FIPS_DATA_REG2 */ "", 52038 /* ISEC_FIPS_DATA_REG3 */ "", 52039 /* ISEC_FIPS_ENC_DATA_REG0 */ "", 52040 /* ISEC_FIPS_ENC_DATA_REG1 */ "", 52041 /* ISEC_FIPS_ENC_DATA_REG2 */ "", 52042 /* ISEC_FIPS_ENC_DATA_REG3 */ "", 52043 /* ISEC_FIPS_INDIRECT_ACCESS */ "", 52044 /* ISEC_FIPS_INDIRECT_ADDR */ "", 52045 /* ISEC_FIPS_INDIRECT_RD_DATA */ "", 52046 /* ISEC_FIPS_INDIRECT_WR_DATA */ "", 52047 /* ISEC_FIPS_IV_REG0 */ "", 52048 /* ISEC_FIPS_IV_REG1 */ "", 52049 /* ISEC_FIPS_IV_REG2 */ "", 52050 /* ISEC_FIPS_KEY_REG0 */ "", 52051 /* ISEC_FIPS_KEY_REG1 */ "", 52052 /* ISEC_FIPS_KEY_REG2 */ "", 52053 /* ISEC_FIPS_KEY_REG3 */ "", 52054 /* ISEC_FIPS_KEY_REG4 */ "", 52055 /* ISEC_FIPS_KEY_REG5 */ "", 52056 /* ISEC_FIPS_KEY_REG6 */ "", 52057 /* ISEC_FIPS_KEY_REG7 */ "", 52058 /* ISEC_FIPS_STATUS */ "", 52059 /* ISEC_FRMVLDT_RULE_CFG */ "", 52060 /* ISEC_FRM_VLDT_RULE */ "", 52061 /* ISEC_GLOBAL_CTRL */ "", 52062 /* ISEC_GLOBAL_PRE_SCALE */ "", 52063 /* ISEC_GLOBAL_TICK_TIME */ "", 52064 /* ISEC_GLOBAL_TIMER */ "", 52065 /* ISEC_MASTER_CTRL */ "", 52066 /* ISEC_MGMTRULE_CFG_DA_0_0 */ "", 52067 /* ISEC_MGMTRULE_CFG_DA_0_1 */ "", 52068 /* ISEC_MGMTRULE_CFG_DA_1_0 */ "", 52069 /* ISEC_MGMTRULE_CFG_DA_1_1 */ "", 52070 /* ISEC_MGMTRULE_CFG_DA_2_0 */ "", 52071 /* ISEC_MGMTRULE_CFG_DA_2_1 */ "", 52072 /* ISEC_MGMTRULE_CFG_DA_3_0 */ "", 52073 /* ISEC_MGMTRULE_CFG_DA_3_1 */ "", 52074 /* ISEC_MGMTRULE_CFG_DA_4_0 */ "", 52075 /* ISEC_MGMTRULE_CFG_DA_4_1 */ "", 52076 /* ISEC_MGMTRULE_CFG_DA_5_0 */ "", 52077 /* ISEC_MGMTRULE_CFG_DA_5_1 */ "", 52078 /* ISEC_MGMTRULE_CFG_DA_6_0 */ "", 52079 /* ISEC_MGMTRULE_CFG_DA_6_1 */ "", 52080 /* ISEC_MGMTRULE_CFG_DA_7_0 */ "", 52081 /* ISEC_MGMTRULE_CFG_DA_7_1 */ "", 52082 /* ISEC_MGMTRULE_CFG_ETYPE_0 */ "", 52083 /* ISEC_MGMTRULE_CFG_ETYPE_2 */ "", 52084 /* ISEC_MGMTRULE_CFG_ETYPE_4 */ "", 52085 /* ISEC_MGMTRULE_CFG_ETYPE_6 */ "", 52086 /* ISEC_MGMTRULE_DA_ETYPE_1ST_0 */ "", 52087 /* ISEC_MGMTRULE_DA_ETYPE_1ST_1 */ "", 52088 /* ISEC_MGMTRULE_DA_ETYPE_2ND_0 */ "", 52089 /* ISEC_MGMTRULE_DA_ETYPE_2ND_1 */ "", 52090 /* ISEC_MGMTRULE_DA_RANGE_HIGH_0 */ "", 52091 /* ISEC_MGMTRULE_DA_RANGE_HIGH_1 */ "", 52092 /* ISEC_MGMTRULE_DA_RANGE_LOW_0 */ "", 52093 /* ISEC_MGMTRULE_DA_RANGE_LOW_1 */ "", 52094 /* ISEC_MPLS_ETYPE */ "", 52095 /* ISEC_MTU0_1 */ "", 52096 /* ISEC_MTU2_3 */ "", 52097 /* ISEC_OLP_TX_ETYPE */ "", 52098 /* ISEC_OLP_TX_MAC_DA0 */ "", 52099 /* ISEC_OLP_TX_MAC_DA1 */ "", 52100 /* ISEC_OLP_TX_MAC_SA0 */ "", 52101 /* ISEC_OLP_TX_MAC_SA1 */ "", 52102 /* ISEC_OLP_TX_MISC */ "", 52103 /* ISEC_OLP_TX_TYPE */ "", 52104 /* ISEC_OLP_TX_VLAN */ "", 52105 /* ISEC_OVR_IV_REG0 */ "", 52106 /* ISEC_OVR_IV_REG1 */ "", 52107 /* ISEC_OVR_IV_REG2 */ "", 52108 /* ISEC_OVR_KEY_REG0 */ "", 52109 /* ISEC_OVR_KEY_REG1 */ "", 52110 /* ISEC_OVR_KEY_REG2 */ "", 52111 /* ISEC_OVR_KEY_REG3 */ "", 52112 /* ISEC_OVR_KEY_REG4 */ "", 52113 /* ISEC_OVR_KEY_REG5 */ "", 52114 /* ISEC_OVR_KEY_REG6 */ "", 52115 /* ISEC_OVR_KEY_REG7 */ "", 52116 /* ISEC_PN_EXPIRE_THD */ "", 52117 /* ISEC_PN_THD */ "", 52118 /* ISEC_PP_CNTRL */ "", 52119 /* ISEC_RUD_MGMT_RULE */ "", 52120 /* ISEC_RUD_MGMT_SPNUM_RULE0 */ "", 52121 /* ISEC_RUD_MGMT_SPNUM_RULE1 */ "", 52122 /* ISEC_RUD_MGMT_SPNUM_RULE2 */ "", 52123 /* ISEC_RUD_MGMT_SPNUM_RULE3 */ "", 52124 /* ISEC_RUD_MGMT_SPNUM_RULE4 */ "", 52125 /* ISEC_RUD_MGMT_SPNUM_RULE5 */ "", 52126 /* ISEC_RUD_MGMT_SPNUM_RULE6 */ "", 52127 /* ISEC_RUD_MGMT_SPNUM_RULE7 */ "", 52128 /* ISEC_RUD_MGMT_SPNUM_RULE8 */ "", 52129 /* ISEC_RUD_MGMT_SPNUM_RULE9 */ "", 52130 /* ISEC_RUD_MGMT_SPNUM_RULE10 */ "", 52131 /* ISEC_RUD_MGMT_SPNUM_RULE11 */ "", 52132 /* ISEC_RUD_MGMT_SPNUM_RULE12 */ "", 52133 /* ISEC_RUD_MGMT_SPNUM_RULE13 */ "", 52134 /* ISEC_RUD_MGMT_SPNUM_RULE14 */ "", 52135 /* ISEC_RUD_MGMT_SPNUM_RULE15 */ "", 52136 /* ISEC_RUD_MGMT_SPNUM_RULE16 */ "", 52137 /* ISEC_RUD_MGMT_SPNUM_RULE17 */ "", 52138 /* ISEC_RUD_MGMT_SPNUM_RULE18 */ "", 52139 /* ISEC_RUD_MGMT_SPNUM_RULE19 */ "", 52140 /* ISEC_RUD_MGMT_SPNUM_RULE20 */ "", 52141 /* ISEC_RUD_MGMT_SPNUM_RULE21 */ "", 52142 /* ISEC_RUD_MGMT_SPNUM_SPTCAM_MIS */ "", 52143 /* ISEC_RUNT_PKT_CNT */ "", 52144 /* ISEC_RUNT_THRESHOLD */ "", 52145 /* ISEC_SA_EXPIRY_INT */ "", 52146 /* ISEC_SA_EXPIRY_INT_MASK */ "", 52147 /* ISEC_SOFT_SA_EXPIRY_INT */ "", 52148 /* ISEC_SOFT_SA_EXPIRY_INT_MASK */ "", 52149 /* ISEC_SPECIAL_TPID */ "", 52150 /* ISEC_TOT_PKT_CNT */ "", 52151 /* ISEC_TPID0 */ "", 52152 /* ISEC_TPID1 */ "", 52153 /* ISEC_TPID2 */ "", 52154 /* ISEC_TPID3 */ "", 52155 /* ISEC_XPN_EXPIRE_THD0 */ "", 52156 /* ISEC_XPN_EXPIRE_THD1 */ "", 52157 /* ISM_HW_RESET_CONTROL_0 */ "", 52158 /* ISM_HW_RESET_CONTROL_1 */ "", 52159 /* ISM_INTR */ "", 52160 /* ISM_INTR_MASK */ "", 52161 /* ISM_SER_FIFO_CTRL */ "", 52162 /* ISS_BANK_CONFIG */ "", 52163 /* ISS_LOG_TO_PHY_BANK_MAP */ "", 52164 /* ISS_LOG_TO_PHY_BANK_MAP_2 */ "", 52165 /* ISS_LOG_TO_PHY_BANK_MAP_3 */ "", 52166 /* ISS_MEMORY_CONTROL_0 */ "", 52167 /* ISS_MEMORY_CONTROL_1 */ "", 52168 /* ISS_MEMORY_CONTROL_2 */ "", 52169 /* ISS_MEMORY_CONTROL_3 */ "", 52170 /* ISS_MEMORY_CONTROL_4 */ "", 52171 /* ISS_MEMORY_CONTROL_5 */ "", 52172 /* ISS_MEMORY_CONTROL_6 */ "", 52173 /* ISS_MEMORY_CONTROL_7 */ "", 52174 /* ISS_MEMORY_CONTROL_8 */ "", 52175 /* ISS_MEMORY_CONTROL_9 */ "", 52176 /* ISS_MEMORY_CONTROL_10 */ "", 52177 /* ISS_MEMORY_CONTROL_11 */ "", 52178 /* ISS_MEMORY_CONTROL_12 */ "", 52179 /* ISS_MEMORY_CONTROL_13 */ "", 52180 /* ISS_MEMORY_CONTROL_14 */ "", 52181 /* ISS_MEMORY_CONTROL_15 */ "", 52182 /* ISS_MEMORY_CONTROL_16 */ "", 52183 /* ISS_MEMORY_CONTROL_17 */ "", 52184 /* ISS_MEMORY_CONTROL_18 */ "", 52185 /* ISS_MEMORY_CONTROL_19 */ "", 52186 /* ISS_MEMORY_CONTROL_20 */ "", 52187 /* ISS_MEMORY_CONTROL_21 */ "", 52188 /* ISS_MEMORY_CONTROL_22 */ "", 52189 /* ISS_MEMORY_CONTROL_23 */ "", 52190 /* ISS_MEMORY_CONTROL_24 */ "", 52191 /* ISS_MEMORY_CONTROL_25 */ "", 52192 /* ISS_MEMORY_CONTROL_26 */ "", 52193 /* ISS_MEMORY_CONTROL_27 */ "", 52194 /* ISS_MEMORY_CONTROL_28 */ "", 52195 /* ISS_MEMORY_CONTROL_29 */ "", 52196 /* ISS_MEMORY_CONTROL_30 */ "", 52197 /* ISS_MEMORY_CONTROL_31 */ "", 52198 /* ISS_MEMORY_CONTROL_32 */ "", 52199 /* ISS_MEMORY_CONTROL_33 */ "", 52200 /* ISS_MEMORY_CONTROL_34 */ "", 52201 /* ISS_MEMORY_CONTROL_35 */ "", 52202 /* ISS_MEMORY_CONTROL_36 */ "", 52203 /* ISS_MEMORY_CONTROL_37 */ "", 52204 /* ISS_MEMORY_CONTROL_38 */ "", 52205 /* ISS_MEMORY_CONTROL_39 */ "", 52206 /* ISS_MEMORY_CONTROL_40 */ "", 52207 /* ISS_MEMORY_CONTROL_41 */ "", 52208 /* ISS_MEMORY_CONTROL_42 */ "", 52209 /* ISS_MEMORY_CONTROL_43 */ "", 52210 /* ISS_MEMORY_CONTROL_44 */ "", 52211 /* ISS_MEMORY_CONTROL_45 */ "", 52212 /* ISS_MEMORY_CONTROL_46 */ "", 52213 /* ISS_MEMORY_CONTROL_47 */ "", 52214 /* ISS_MEMORY_CONTROL_48 */ "", 52215 /* ISS_MEMORY_CONTROL_49 */ "", 52216 /* ISS_MEMORY_CONTROL_50 */ "", 52217 /* ISS_MEMORY_CONTROL_51 */ "", 52218 /* ISS_MEMORY_CONTROL_52 */ "", 52219 /* ISS_MEMORY_CONTROL_53 */ "", 52220 /* ISS_MEMORY_CONTROL_54 */ "", 52221 /* ISS_MEMORY_CONTROL_55 */ "", 52222 /* ISS_MEMORY_CONTROL_56 */ "", 52223 /* ISS_MEMORY_CONTROL_57 */ "", 52224 /* ISS_MEMORY_CONTROL_58 */ "", 52225 /* ISS_MEMORY_CONTROL_59 */ "", 52226 /* ISS_MEMORY_CONTROL_60 */ "", 52227 /* ISS_MEMORY_CONTROL_61 */ "", 52228 /* ISS_MEMORY_CONTROL_62 */ "", 52229 /* ISS_MEMORY_CONTROL_63 */ "", 52230 /* ISS_MEMORY_CONTROL_64 */ "", 52231 /* ISS_MEMORY_CONTROL_65 */ "", 52232 /* ISS_MEMORY_CONTROL_66 */ "", 52233 /* ISS_MEMORY_CONTROL_67 */ "", 52234 /* ISS_MEMORY_CONTROL_68 */ "", 52235 /* ISS_MEMORY_CONTROL_69 */ "", 52236 /* ISS_MEMORY_CONTROL_70 */ "", 52237 /* ISS_MEMORY_CONTROL_71 */ "", 52238 /* ISS_MEMORY_CONTROL_72 */ "", 52239 /* ISS_MEMORY_CONTROL_73 */ "", 52240 /* ISS_MEMORY_CONTROL_74 */ "", 52241 /* ISS_MEMORY_CONTROL_75 */ "", 52242 /* ISS_MEMORY_CONTROL_76 */ "", 52243 /* ISS_MEMORY_CONTROL_77 */ "", 52244 /* ISS_MEMORY_CONTROL_78 */ "", 52245 /* ISS_MEMORY_CONTROL_79 */ "", 52246 /* ISS_MEMORY_CONTROL_80 */ "", 52247 /* ISS_MEMORY_CONTROL_81 */ "", 52248 /* ISS_MEMORY_CONTROL_82 */ "", 52249 /* ISS_MEMORY_CONTROL_83 */ "", 52250 /* ISS_MEMORY_CONTROL_84 */ "", 52251 /* ISS_MEMORY_CONTROL_0_PIPE0 */ "", 52252 /* ISS_MEMORY_CONTROL_0_PIPE1 */ "", 52253 /* ISS_MEMORY_CONTROL_0_PIPE2 */ "", 52254 /* ISS_MEMORY_CONTROL_0_PIPE3 */ "", 52255 /* ISS_MEMORY_CONTROL_1_PIPE0 */ "", 52256 /* ISS_MEMORY_CONTROL_1_PIPE1 */ "", 52257 /* ISS_MEMORY_CONTROL_1_PIPE2 */ "", 52258 /* ISS_MEMORY_CONTROL_1_PIPE3 */ "", 52259 /* ISS_MEMORY_CONTROL_2_PIPE0 */ "", 52260 /* ISS_MEMORY_CONTROL_2_PIPE1 */ "", 52261 /* ISS_MEMORY_CONTROL_2_PIPE2 */ "", 52262 /* ISS_MEMORY_CONTROL_2_PIPE3 */ "", 52263 /* ISS_MEMORY_CONTROL_3_PIPE0 */ "", 52264 /* ISS_MEMORY_CONTROL_3_PIPE1 */ "", 52265 /* ISS_MEMORY_CONTROL_3_PIPE2 */ "", 52266 /* ISS_MEMORY_CONTROL_3_PIPE3 */ "", 52267 /* ISS_MEMORY_CONTROL_4_PIPE0 */ "", 52268 /* ISS_MEMORY_CONTROL_4_PIPE1 */ "", 52269 /* ISS_MEMORY_CONTROL_4_PIPE2 */ "", 52270 /* ISS_MEMORY_CONTROL_4_PIPE3 */ "", 52271 /* ISS_MEMORY_CONTROL_5_PIPE0 */ "", 52272 /* ISS_MEMORY_CONTROL_5_PIPE1 */ "", 52273 /* ISS_MEMORY_CONTROL_5_PIPE2 */ "", 52274 /* ISS_MEMORY_CONTROL_5_PIPE3 */ "", 52275 /* ISS_MEMORY_CONTROL_84_PIPE0 */ "", 52276 /* ISS_MEMORY_CONTROL_84_PIPE1 */ "", 52277 /* ISS_MEMORY_CONTROL_84_PIPE2 */ "", 52278 /* ISS_MEMORY_CONTROL_84_PIPE3 */ "", 52279 /* ISW1_BUS_PARITY_DEBUG */ "", 52280 /* ISW1_CLK_GATING_CONTROL */ "", 52281 /* ISW1_DSCP_TABLE_ECC_STATUS */ "", 52282 /* ISW1_ECC_DEBUG */ "", 52283 /* ISW1_ECC_ERROR */ "", 52284 /* ISW1_ECC_ERROR_MASK */ "", 52285 /* ISW1_EN_COR_ERR_RPT */ "", 52286 /* ISW1_ERROR */ "", 52287 /* ISW1_ERROR_MASK */ "", 52288 /* ISW1_HW_CONTROL */ "", 52289 /* ISW1_INIT_DATA */ "", 52290 /* ISW1_MEM_DEBUG */ "", 52291 /* ISW1_MEM_INIT */ "", 52292 /* ISW1_PARITY_ERROR */ "", 52293 /* ISW1_PARITY_ERROR_MASK */ "", 52294 /* ISW1_REGS_DEBUG */ "", 52295 /* ISW1_SER_CONTROL */ "", 52296 /* ISW1_TM_REG_1 */ "", 52297 /* ISW1_UFLOW_A_0_ECC_STATUS */ "", 52298 /* ISW1_UFLOW_A_1_ECC_STATUS */ "", 52299 /* ISW1_UFLOW_B_0_ECC_STATUS */ "", 52300 /* ISW1_UFLOW_B_1_ECC_STATUS */ "", 52301 /* ISW2_BUS_PARITY_DEBUG */ "", 52302 /* ISW2_CLK_GATING_CTRL */ "", 52303 /* ISW2_DEBUG0 */ "", 52304 /* ISW2_DEBUG1 */ "", 52305 /* ISW2_DEBUG2 */ "", 52306 /* ISW2_DEBUG3 */ "", 52307 /* ISW2_DEBUG_CAPTURE_CAPTURE_FILTER */ "", 52308 /* ISW2_DEBUG_CAPTURE_CSR */ "", 52309 /* ISW2_DEBUG_CAPTURE_ING_EVENT_SEL */ "", 52310 /* ISW2_DEBUG_CAPTURE_TRIGGER_FILTER */ "", 52311 /* ISW2_ECC_ERROR0 */ "", 52312 /* ISW2_ECC_ERROR1 */ "", 52313 /* ISW2_ECC_ERROR2 */ "", 52314 /* ISW2_ECC_ERROR0_MASK */ "", 52315 /* ISW2_ECC_ERROR1_MASK */ "", 52316 /* ISW2_ECC_ERROR2_MASK */ "", 52317 /* ISW2_HW_CONTROL */ "", 52318 /* ISW2_INIT_DATA0 */ "", 52319 /* ISW2_INIT_DATA1 */ "", 52320 /* ISW2_INIT_DATA2 */ "", 52321 /* ISW2_INIT_DATA3 */ "", 52322 /* ISW2_INIT_DATA4 */ "", 52323 /* ISW2_MEM_INIT0 */ "", 52324 /* ISW2_MEM_INIT1 */ "", 52325 /* ISW2_MEM_INIT2 */ "", 52326 /* ISW2_PARITY_ERROR */ "", 52327 /* ISW2_PARITY_ERROR_MASK */ "", 52328 /* ISW2_REGS_DEBUG */ "", 52329 /* ISW2_SER_CONTROL_0 */ "", 52330 /* ISW2_SER_CONTROL_1 */ "", 52331 /* ISW2_SER_CONTROL_2 */ "", 52332 /* ISW2_SER_CONTROL_0_64 */ "ISW2_SER_CONTROL_0", 52333 /* ISW2_TM_REG_1 */ "", 52334 /* ISW3_SER_CONTROL_1 */ "", 52335 /* ISW3_SER_CONTROL_2 */ "", 52336 /* ISW4_INTR_ENABLE */ "", 52337 /* ISW4_INTR_ENABLE_PIPE0 */ "", 52338 /* ISW4_INTR_STATUS */ "", 52339 /* ISW4_INTR_STATUS_PIPE0 */ "", 52340 /* ISW4_INTR_STATUS_PIPE1 */ "", 52341 /* ISW4_SPACING_COUNTER */ "", 52342 /* ISW4_SPACING_COUNTER_CONTROL */ "", 52343 /* ISW4_SPACING_COUNTER_PIPE0 */ "", 52344 /* ISW4_SPACING_COUNTER_PIPE1 */ "", 52345 /* ISW_ECC_EN */ "", 52346 /* ISW_EN_COR_ERR_RPT */ "", 52347 /* ISW_RAM_CONTROL */ "", 52348 /* ISW_RAM_CONTROL_PIPE0 */ "", 52349 /* ISW_RAM_CONTROL_PIPE1 */ "", 52350 /* ISW_RAM_CONTROL_PIPE2 */ "", 52351 /* ISW_RAM_CONTROL_PIPE3 */ "", 52352 /* ISW_RAM_CONTROL_PIPE4 */ "", 52353 /* ISW_RAM_CONTROL_PIPE5 */ "", 52354 /* ISW_RAM_CONTROL_PIPE6 */ "", 52355 /* ISW_RAM_CONTROL_PIPE7 */ "", 52356 /* ISW_SER_CONTROL */ "", 52357 /* IS_CAL_CONFIG */ "", 52358 /* IS_CAL_CONFIG_PIPE0 */ "", 52359 /* IS_CAL_CONFIG_PIPE1 */ "", 52360 /* IS_CAL_CONFIG_PIPE2 */ "", 52361 /* IS_CAL_CONFIG_PIPE3 */ "", 52362 /* IS_CAL_CONFIG_PIPE4 */ "", 52363 /* IS_CAL_CONFIG_PIPE5 */ "", 52364 /* IS_CAL_CONFIG_PIPE6 */ "", 52365 /* IS_CAL_CONFIG_PIPE7 */ "", 52366 /* IS_CBMG_VALUE */ "", 52367 /* IS_CBMG_VALUE_PIPE0 */ "", 52368 /* IS_CBMG_VALUE_PIPE1 */ "", 52369 /* IS_CBMG_VALUE_PIPE2 */ "", 52370 /* IS_CBMG_VALUE_PIPE3 */ "", 52371 /* IS_CBMG_VALUE_PIPE4 */ "", 52372 /* IS_CBMG_VALUE_PIPE5 */ "", 52373 /* IS_CBMG_VALUE_PIPE6 */ "", 52374 /* IS_CBMG_VALUE_PIPE7 */ "", 52375 /* IS_CMIC_RESERVED */ "", 52376 /* IS_CMIC_RESERVED_PIPE0 */ "", 52377 /* IS_CMIC_RESERVED_PIPE1 */ "", 52378 /* IS_CMIC_RESERVED_PIPE2 */ "", 52379 /* IS_CMIC_RESERVED_PIPE3 */ "", 52380 /* IS_CMIC_RESERVED_PIPE4 */ "", 52381 /* IS_CMIC_RESERVED_PIPE5 */ "", 52382 /* IS_CMIC_RESERVED_PIPE6 */ "", 52383 /* IS_CMIC_RESERVED_PIPE7 */ "", 52384 /* IS_CPU_LB_OPP_CFG */ "", 52385 /* IS_CPU_LB_OPP_CFG_PIPE0 */ "", 52386 /* IS_CPU_LB_OPP_CFG_PIPE1 */ "", 52387 /* IS_CPU_LB_OPP_CFG_PIPE2 */ "", 52388 /* IS_CPU_LB_OPP_CFG_PIPE3 */ "", 52389 /* IS_CPU_MGMT_LB_RATIOS */ "", 52390 /* IS_CPU_MGMT_LB_RATIOS_PIPE0 */ "", 52391 /* IS_CPU_MGMT_LB_RATIOS_PIPE1 */ "", 52392 /* IS_CPU_MGMT_LB_RATIOS_PIPE2 */ "", 52393 /* IS_CPU_MGMT_LB_RATIOS_PIPE3 */ "", 52394 /* IS_CPU_MGMT_LB_RATIOS_PIPE4 */ "", 52395 /* IS_CPU_MGMT_LB_RATIOS_PIPE5 */ "", 52396 /* IS_CPU_MGMT_LB_RATIOS_PIPE6 */ "", 52397 /* IS_CPU_MGMT_LB_RATIOS_PIPE7 */ "", 52398 /* IS_FEATURE_CTRL */ "", 52399 /* IS_FEATURE_CTRL_PIPE0 */ "", 52400 /* IS_FEATURE_CTRL_PIPE1 */ "", 52401 /* IS_FEATURE_CTRL_PIPE2 */ "", 52402 /* IS_FEATURE_CTRL_PIPE3 */ "", 52403 /* IS_FEATURE_CTRL_PIPE4 */ "", 52404 /* IS_FEATURE_CTRL_PIPE5 */ "", 52405 /* IS_FEATURE_CTRL_PIPE6 */ "", 52406 /* IS_FEATURE_CTRL_PIPE7 */ "", 52407 /* IS_HPIPE0_OVR_SUB_GRP0_TBL */ "", 52408 /* IS_HPIPE0_OVR_SUB_GRP0_TBL_PIPE0 */ "", 52409 /* IS_HPIPE0_OVR_SUB_GRP0_TBL_PIPE1 */ "", 52410 /* IS_HPIPE0_OVR_SUB_GRP0_TBL_PIPE2 */ "", 52411 /* IS_HPIPE0_OVR_SUB_GRP0_TBL_PIPE3 */ "", 52412 /* IS_HPIPE0_OVR_SUB_GRP1_TBL */ "", 52413 /* IS_HPIPE0_OVR_SUB_GRP1_TBL_PIPE0 */ "", 52414 /* IS_HPIPE0_OVR_SUB_GRP1_TBL_PIPE1 */ "", 52415 /* IS_HPIPE0_OVR_SUB_GRP1_TBL_PIPE2 */ "", 52416 /* IS_HPIPE0_OVR_SUB_GRP1_TBL_PIPE3 */ "", 52417 /* IS_HPIPE0_OVR_SUB_GRP2_TBL */ "", 52418 /* IS_HPIPE0_OVR_SUB_GRP2_TBL_PIPE0 */ "", 52419 /* IS_HPIPE0_OVR_SUB_GRP2_TBL_PIPE1 */ "", 52420 /* IS_HPIPE0_OVR_SUB_GRP2_TBL_PIPE2 */ "", 52421 /* IS_HPIPE0_OVR_SUB_GRP2_TBL_PIPE3 */ "", 52422 /* IS_HPIPE0_OVR_SUB_GRP3_TBL */ "", 52423 /* IS_HPIPE0_OVR_SUB_GRP3_TBL_PIPE0 */ "", 52424 /* IS_HPIPE0_OVR_SUB_GRP3_TBL_PIPE1 */ "", 52425 /* IS_HPIPE0_OVR_SUB_GRP3_TBL_PIPE2 */ "", 52426 /* IS_HPIPE0_OVR_SUB_GRP3_TBL_PIPE3 */ "", 52427 /* IS_HPIPE0_OVR_SUB_GRP4_TBL */ "", 52428 /* IS_HPIPE0_OVR_SUB_GRP4_TBL_PIPE0 */ "", 52429 /* IS_HPIPE0_OVR_SUB_GRP4_TBL_PIPE1 */ "", 52430 /* IS_HPIPE0_OVR_SUB_GRP4_TBL_PIPE2 */ "", 52431 /* IS_HPIPE0_OVR_SUB_GRP4_TBL_PIPE3 */ "", 52432 /* IS_HPIPE0_OVR_SUB_GRP5_TBL */ "", 52433 /* IS_HPIPE0_OVR_SUB_GRP5_TBL_PIPE0 */ "", 52434 /* IS_HPIPE0_OVR_SUB_GRP5_TBL_PIPE1 */ "", 52435 /* IS_HPIPE0_OVR_SUB_GRP5_TBL_PIPE2 */ "", 52436 /* IS_HPIPE0_OVR_SUB_GRP5_TBL_PIPE3 */ "", 52437 /* IS_HPIPE0_OVR_SUB_GRP_CFG */ "", 52438 /* IS_HPIPE0_OVR_SUB_GRP_CFG_PIPE0 */ "", 52439 /* IS_HPIPE0_OVR_SUB_GRP_CFG_PIPE1 */ "", 52440 /* IS_HPIPE0_OVR_SUB_GRP_CFG_PIPE2 */ "", 52441 /* IS_HPIPE0_OVR_SUB_GRP_CFG_PIPE3 */ "", 52442 /* IS_HPIPE0_PBLK0_CALENDAR */ "", 52443 /* IS_HPIPE0_PBLK0_CALENDAR_PIPE0 */ "", 52444 /* IS_HPIPE0_PBLK0_CALENDAR_PIPE1 */ "", 52445 /* IS_HPIPE0_PBLK0_CALENDAR_PIPE2 */ "", 52446 /* IS_HPIPE0_PBLK0_CALENDAR_PIPE3 */ "", 52447 /* IS_HPIPE0_PBLK1_CALENDAR */ "", 52448 /* IS_HPIPE0_PBLK1_CALENDAR_PIPE0 */ "", 52449 /* IS_HPIPE0_PBLK1_CALENDAR_PIPE1 */ "", 52450 /* IS_HPIPE0_PBLK1_CALENDAR_PIPE2 */ "", 52451 /* IS_HPIPE0_PBLK1_CALENDAR_PIPE3 */ "", 52452 /* IS_HPIPE0_PBLK2_CALENDAR */ "", 52453 /* IS_HPIPE0_PBLK2_CALENDAR_PIPE0 */ "", 52454 /* IS_HPIPE0_PBLK2_CALENDAR_PIPE1 */ "", 52455 /* IS_HPIPE0_PBLK2_CALENDAR_PIPE2 */ "", 52456 /* IS_HPIPE0_PBLK2_CALENDAR_PIPE3 */ "", 52457 /* IS_HPIPE0_PBLK3_CALENDAR */ "", 52458 /* IS_HPIPE0_PBLK3_CALENDAR_PIPE0 */ "", 52459 /* IS_HPIPE0_PBLK3_CALENDAR_PIPE1 */ "", 52460 /* IS_HPIPE0_PBLK3_CALENDAR_PIPE2 */ "", 52461 /* IS_HPIPE0_PBLK3_CALENDAR_PIPE3 */ "", 52462 /* IS_HPIPE0_PBLK4_CALENDAR */ "", 52463 /* IS_HPIPE0_PBLK4_CALENDAR_PIPE0 */ "", 52464 /* IS_HPIPE0_PBLK4_CALENDAR_PIPE1 */ "", 52465 /* IS_HPIPE0_PBLK4_CALENDAR_PIPE2 */ "", 52466 /* IS_HPIPE0_PBLK4_CALENDAR_PIPE3 */ "", 52467 /* IS_HPIPE0_PBLK5_CALENDAR */ "", 52468 /* IS_HPIPE0_PBLK5_CALENDAR_PIPE0 */ "", 52469 /* IS_HPIPE0_PBLK5_CALENDAR_PIPE1 */ "", 52470 /* IS_HPIPE0_PBLK5_CALENDAR_PIPE2 */ "", 52471 /* IS_HPIPE0_PBLK5_CALENDAR_PIPE3 */ "", 52472 /* IS_HPIPE0_PBLK6_CALENDAR */ "", 52473 /* IS_HPIPE0_PBLK6_CALENDAR_PIPE0 */ "", 52474 /* IS_HPIPE0_PBLK6_CALENDAR_PIPE1 */ "", 52475 /* IS_HPIPE0_PBLK6_CALENDAR_PIPE2 */ "", 52476 /* IS_HPIPE0_PBLK6_CALENDAR_PIPE3 */ "", 52477 /* IS_HPIPE0_PBLK7_CALENDAR */ "", 52478 /* IS_HPIPE0_PBLK7_CALENDAR_PIPE0 */ "", 52479 /* IS_HPIPE0_PBLK7_CALENDAR_PIPE1 */ "", 52480 /* IS_HPIPE0_PBLK7_CALENDAR_PIPE2 */ "", 52481 /* IS_HPIPE0_PBLK7_CALENDAR_PIPE3 */ "", 52482 /* IS_HPIPE0_PBLK8_CALENDAR */ "", 52483 /* IS_HPIPE0_PBLK8_CALENDAR_PIPE0 */ "", 52484 /* IS_HPIPE0_PBLK9_CALENDAR */ "", 52485 /* IS_HPIPE0_PBLK9_CALENDAR_PIPE0 */ "", 52486 /* IS_HPIPE1_OVR_SUB_GRP0_TBL */ "", 52487 /* IS_HPIPE1_OVR_SUB_GRP0_TBL_PIPE0 */ "", 52488 /* IS_HPIPE1_OVR_SUB_GRP0_TBL_PIPE1 */ "", 52489 /* IS_HPIPE1_OVR_SUB_GRP0_TBL_PIPE2 */ "", 52490 /* IS_HPIPE1_OVR_SUB_GRP0_TBL_PIPE3 */ "", 52491 /* IS_HPIPE1_OVR_SUB_GRP1_TBL */ "", 52492 /* IS_HPIPE1_OVR_SUB_GRP1_TBL_PIPE0 */ "", 52493 /* IS_HPIPE1_OVR_SUB_GRP1_TBL_PIPE1 */ "", 52494 /* IS_HPIPE1_OVR_SUB_GRP1_TBL_PIPE2 */ "", 52495 /* IS_HPIPE1_OVR_SUB_GRP1_TBL_PIPE3 */ "", 52496 /* IS_HPIPE1_OVR_SUB_GRP2_TBL */ "", 52497 /* IS_HPIPE1_OVR_SUB_GRP2_TBL_PIPE0 */ "", 52498 /* IS_HPIPE1_OVR_SUB_GRP2_TBL_PIPE1 */ "", 52499 /* IS_HPIPE1_OVR_SUB_GRP2_TBL_PIPE2 */ "", 52500 /* IS_HPIPE1_OVR_SUB_GRP2_TBL_PIPE3 */ "", 52501 /* IS_HPIPE1_OVR_SUB_GRP3_TBL */ "", 52502 /* IS_HPIPE1_OVR_SUB_GRP3_TBL_PIPE0 */ "", 52503 /* IS_HPIPE1_OVR_SUB_GRP3_TBL_PIPE1 */ "", 52504 /* IS_HPIPE1_OVR_SUB_GRP3_TBL_PIPE2 */ "", 52505 /* IS_HPIPE1_OVR_SUB_GRP3_TBL_PIPE3 */ "", 52506 /* IS_HPIPE1_OVR_SUB_GRP4_TBL */ "", 52507 /* IS_HPIPE1_OVR_SUB_GRP4_TBL_PIPE0 */ "", 52508 /* IS_HPIPE1_OVR_SUB_GRP4_TBL_PIPE1 */ "", 52509 /* IS_HPIPE1_OVR_SUB_GRP4_TBL_PIPE2 */ "", 52510 /* IS_HPIPE1_OVR_SUB_GRP4_TBL_PIPE3 */ "", 52511 /* IS_HPIPE1_OVR_SUB_GRP5_TBL */ "", 52512 /* IS_HPIPE1_OVR_SUB_GRP5_TBL_PIPE0 */ "", 52513 /* IS_HPIPE1_OVR_SUB_GRP5_TBL_PIPE1 */ "", 52514 /* IS_HPIPE1_OVR_SUB_GRP5_TBL_PIPE2 */ "", 52515 /* IS_HPIPE1_OVR_SUB_GRP5_TBL_PIPE3 */ "", 52516 /* IS_HPIPE1_OVR_SUB_GRP_CFG */ "", 52517 /* IS_HPIPE1_OVR_SUB_GRP_CFG_PIPE0 */ "", 52518 /* IS_HPIPE1_OVR_SUB_GRP_CFG_PIPE1 */ "", 52519 /* IS_HPIPE1_OVR_SUB_GRP_CFG_PIPE2 */ "", 52520 /* IS_HPIPE1_OVR_SUB_GRP_CFG_PIPE3 */ "", 52521 /* IS_HPIPE1_PBLK0_CALENDAR */ "", 52522 /* IS_HPIPE1_PBLK0_CALENDAR_PIPE0 */ "", 52523 /* IS_HPIPE1_PBLK0_CALENDAR_PIPE1 */ "", 52524 /* IS_HPIPE1_PBLK0_CALENDAR_PIPE2 */ "", 52525 /* IS_HPIPE1_PBLK0_CALENDAR_PIPE3 */ "", 52526 /* IS_HPIPE1_PBLK1_CALENDAR */ "", 52527 /* IS_HPIPE1_PBLK1_CALENDAR_PIPE0 */ "", 52528 /* IS_HPIPE1_PBLK1_CALENDAR_PIPE1 */ "", 52529 /* IS_HPIPE1_PBLK1_CALENDAR_PIPE2 */ "", 52530 /* IS_HPIPE1_PBLK1_CALENDAR_PIPE3 */ "", 52531 /* IS_HPIPE1_PBLK2_CALENDAR */ "", 52532 /* IS_HPIPE1_PBLK2_CALENDAR_PIPE0 */ "", 52533 /* IS_HPIPE1_PBLK2_CALENDAR_PIPE1 */ "", 52534 /* IS_HPIPE1_PBLK2_CALENDAR_PIPE2 */ "", 52535 /* IS_HPIPE1_PBLK2_CALENDAR_PIPE3 */ "", 52536 /* IS_HPIPE1_PBLK3_CALENDAR */ "", 52537 /* IS_HPIPE1_PBLK3_CALENDAR_PIPE0 */ "", 52538 /* IS_HPIPE1_PBLK3_CALENDAR_PIPE1 */ "", 52539 /* IS_HPIPE1_PBLK3_CALENDAR_PIPE2 */ "", 52540 /* IS_HPIPE1_PBLK3_CALENDAR_PIPE3 */ "", 52541 /* IS_HPIPE1_PBLK4_CALENDAR */ "", 52542 /* IS_HPIPE1_PBLK4_CALENDAR_PIPE0 */ "", 52543 /* IS_HPIPE1_PBLK4_CALENDAR_PIPE1 */ "", 52544 /* IS_HPIPE1_PBLK4_CALENDAR_PIPE2 */ "", 52545 /* IS_HPIPE1_PBLK4_CALENDAR_PIPE3 */ "", 52546 /* IS_HPIPE1_PBLK5_CALENDAR */ "", 52547 /* IS_HPIPE1_PBLK5_CALENDAR_PIPE0 */ "", 52548 /* IS_HPIPE1_PBLK5_CALENDAR_PIPE1 */ "", 52549 /* IS_HPIPE1_PBLK5_CALENDAR_PIPE2 */ "", 52550 /* IS_HPIPE1_PBLK5_CALENDAR_PIPE3 */ "", 52551 /* IS_HPIPE1_PBLK6_CALENDAR */ "", 52552 /* IS_HPIPE1_PBLK6_CALENDAR_PIPE0 */ "", 52553 /* IS_HPIPE1_PBLK6_CALENDAR_PIPE1 */ "", 52554 /* IS_HPIPE1_PBLK6_CALENDAR_PIPE2 */ "", 52555 /* IS_HPIPE1_PBLK6_CALENDAR_PIPE3 */ "", 52556 /* IS_HPIPE1_PBLK7_CALENDAR */ "", 52557 /* IS_HPIPE1_PBLK7_CALENDAR_PIPE0 */ "", 52558 /* IS_HPIPE1_PBLK7_CALENDAR_PIPE1 */ "", 52559 /* IS_HPIPE1_PBLK7_CALENDAR_PIPE2 */ "", 52560 /* IS_HPIPE1_PBLK7_CALENDAR_PIPE3 */ "", 52561 /* IS_HPIPE1_PBLK8_CALENDAR */ "", 52562 /* IS_HPIPE1_PBLK8_CALENDAR_PIPE0 */ "", 52563 /* IS_HPIPE1_PBLK9_CALENDAR */ "", 52564 /* IS_HPIPE1_PBLK9_CALENDAR_PIPE0 */ "", 52565 /* IS_MAX_SPACING */ "", 52566 /* IS_MAX_SPACING_PIPE0 */ "", 52567 /* IS_MAX_SPACING_PIPE1 */ "", 52568 /* IS_MAX_SPACING_PIPE2 */ "", 52569 /* IS_MAX_SPACING_PIPE3 */ "", 52570 /* IS_MAX_SPACING_PIPE4 */ "", 52571 /* IS_MAX_SPACING_PIPE5 */ "", 52572 /* IS_MAX_SPACING_PIPE6 */ "", 52573 /* IS_MAX_SPACING_PIPE7 */ "", 52574 /* IS_MIN_CELL_SPACING */ "", 52575 /* IS_MIN_CELL_SPACING_EOP_TO_SOP */ "", 52576 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE0 */ "", 52577 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE1 */ "", 52578 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE2 */ "", 52579 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE3 */ "", 52580 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE4 */ "", 52581 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE5 */ "", 52582 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE6 */ "", 52583 /* IS_MIN_CELL_SPACING_EOP_TO_SOP_PIPE7 */ "", 52584 /* IS_MIN_CELL_SPACING_PIPE0 */ "", 52585 /* IS_MIN_CELL_SPACING_PIPE1 */ "", 52586 /* IS_MIN_CELL_SPACING_PIPE2 */ "", 52587 /* IS_MIN_CELL_SPACING_PIPE3 */ "", 52588 /* IS_MIN_CELL_SPACING_PIPE4 */ "", 52589 /* IS_MIN_CELL_SPACING_PIPE5 */ "", 52590 /* IS_MIN_CELL_SPACING_PIPE6 */ "", 52591 /* IS_MIN_CELL_SPACING_PIPE7 */ "", 52592 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT */ "", 52593 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE0 */ "", 52594 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE1 */ "", 52595 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE2 */ "", 52596 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE3 */ "", 52597 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE4 */ "", 52598 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE5 */ "", 52599 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE6 */ "", 52600 /* IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE7 */ "", 52601 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY */ "", 52602 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE0 */ "", 52603 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE1 */ "", 52604 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE2 */ "", 52605 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE3 */ "", 52606 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE4 */ "", 52607 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE5 */ "", 52608 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE6 */ "", 52609 /* IS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY_PIPE7 */ "", 52610 /* IS_OPP_SCHED_CFG */ "", 52611 /* IS_OPP_SCHED_CFG_PIPE0 */ "", 52612 /* IS_OPP_SCHED_CFG_PIPE1 */ "", 52613 /* IS_OPP_SCHED_CFG_PIPE2 */ "", 52614 /* IS_OPP_SCHED_CFG_PIPE3 */ "", 52615 /* IS_OVR_SUB_GRP0_TBL */ "", 52616 /* IS_OVR_SUB_GRP0_TBL_PIPE0 */ "", 52617 /* IS_OVR_SUB_GRP0_TBL_PIPE1 */ "", 52618 /* IS_OVR_SUB_GRP0_TBL_PIPE2 */ "", 52619 /* IS_OVR_SUB_GRP0_TBL_PIPE3 */ "", 52620 /* IS_OVR_SUB_GRP1_TBL */ "", 52621 /* IS_OVR_SUB_GRP1_TBL_PIPE0 */ "", 52622 /* IS_OVR_SUB_GRP1_TBL_PIPE1 */ "", 52623 /* IS_OVR_SUB_GRP1_TBL_PIPE2 */ "", 52624 /* IS_OVR_SUB_GRP1_TBL_PIPE3 */ "", 52625 /* IS_OVR_SUB_GRP2_TBL */ "", 52626 /* IS_OVR_SUB_GRP2_TBL_PIPE0 */ "", 52627 /* IS_OVR_SUB_GRP2_TBL_PIPE1 */ "", 52628 /* IS_OVR_SUB_GRP2_TBL_PIPE2 */ "", 52629 /* IS_OVR_SUB_GRP2_TBL_PIPE3 */ "", 52630 /* IS_OVR_SUB_GRP3_TBL */ "", 52631 /* IS_OVR_SUB_GRP3_TBL_PIPE0 */ "", 52632 /* IS_OVR_SUB_GRP3_TBL_PIPE1 */ "", 52633 /* IS_OVR_SUB_GRP3_TBL_PIPE2 */ "", 52634 /* IS_OVR_SUB_GRP3_TBL_PIPE3 */ "", 52635 /* IS_OVR_SUB_GRP4_TBL */ "", 52636 /* IS_OVR_SUB_GRP4_TBL_PIPE0 */ "", 52637 /* IS_OVR_SUB_GRP4_TBL_PIPE1 */ "", 52638 /* IS_OVR_SUB_GRP4_TBL_PIPE2 */ "", 52639 /* IS_OVR_SUB_GRP4_TBL_PIPE3 */ "", 52640 /* IS_OVR_SUB_GRP5_TBL */ "", 52641 /* IS_OVR_SUB_GRP5_TBL_PIPE0 */ "", 52642 /* IS_OVR_SUB_GRP5_TBL_PIPE1 */ "", 52643 /* IS_OVR_SUB_GRP5_TBL_PIPE2 */ "", 52644 /* IS_OVR_SUB_GRP5_TBL_PIPE3 */ "", 52645 /* IS_OVR_SUB_GRP6_TBL */ "", 52646 /* IS_OVR_SUB_GRP6_TBL_PIPE0 */ "", 52647 /* IS_OVR_SUB_GRP6_TBL_PIPE1 */ "", 52648 /* IS_OVR_SUB_GRP6_TBL_PIPE2 */ "", 52649 /* IS_OVR_SUB_GRP6_TBL_PIPE3 */ "", 52650 /* IS_OVR_SUB_GRP7_TBL */ "", 52651 /* IS_OVR_SUB_GRP7_TBL_PIPE0 */ "", 52652 /* IS_OVR_SUB_GRP7_TBL_PIPE1 */ "", 52653 /* IS_OVR_SUB_GRP7_TBL_PIPE2 */ "", 52654 /* IS_OVR_SUB_GRP7_TBL_PIPE3 */ "", 52655 /* IS_OVR_SUB_GRP_CFG */ "", 52656 /* IS_OVR_SUB_GRP_CFG_PIPE0 */ "", 52657 /* IS_OVR_SUB_GRP_CFG_PIPE1 */ "", 52658 /* IS_OVR_SUB_GRP_CFG_PIPE2 */ "", 52659 /* IS_OVR_SUB_GRP_CFG_PIPE3 */ "", 52660 /* IS_PBLK0_CALENDAR */ "", 52661 /* IS_PBLK0_CALENDAR_PIPE0 */ "", 52662 /* IS_PBLK0_CALENDAR_PIPE1 */ "", 52663 /* IS_PBLK0_CALENDAR_PIPE2 */ "", 52664 /* IS_PBLK0_CALENDAR_PIPE3 */ "", 52665 /* IS_PBLK1_CALENDAR */ "", 52666 /* IS_PBLK1_CALENDAR_PIPE0 */ "", 52667 /* IS_PBLK1_CALENDAR_PIPE1 */ "", 52668 /* IS_PBLK1_CALENDAR_PIPE2 */ "", 52669 /* IS_PBLK1_CALENDAR_PIPE3 */ "", 52670 /* IS_PBLK2_CALENDAR */ "", 52671 /* IS_PBLK2_CALENDAR_PIPE0 */ "", 52672 /* IS_PBLK2_CALENDAR_PIPE1 */ "", 52673 /* IS_PBLK2_CALENDAR_PIPE2 */ "", 52674 /* IS_PBLK2_CALENDAR_PIPE3 */ "", 52675 /* IS_PBLK3_CALENDAR */ "", 52676 /* IS_PBLK3_CALENDAR_PIPE0 */ "", 52677 /* IS_PBLK3_CALENDAR_PIPE1 */ "", 52678 /* IS_PBLK3_CALENDAR_PIPE2 */ "", 52679 /* IS_PBLK3_CALENDAR_PIPE3 */ "", 52680 /* IS_PBLK4_CALENDAR */ "", 52681 /* IS_PBLK4_CALENDAR_PIPE0 */ "", 52682 /* IS_PBLK4_CALENDAR_PIPE1 */ "", 52683 /* IS_PBLK4_CALENDAR_PIPE2 */ "", 52684 /* IS_PBLK4_CALENDAR_PIPE3 */ "", 52685 /* IS_PBLK5_CALENDAR */ "", 52686 /* IS_PBLK5_CALENDAR_PIPE0 */ "", 52687 /* IS_PBLK5_CALENDAR_PIPE1 */ "", 52688 /* IS_PBLK5_CALENDAR_PIPE2 */ "", 52689 /* IS_PBLK5_CALENDAR_PIPE3 */ "", 52690 /* IS_PBLK6_CALENDAR */ "", 52691 /* IS_PBLK6_CALENDAR_PIPE0 */ "", 52692 /* IS_PBLK6_CALENDAR_PIPE1 */ "", 52693 /* IS_PBLK6_CALENDAR_PIPE2 */ "", 52694 /* IS_PBLK6_CALENDAR_PIPE3 */ "", 52695 /* IS_PBLK7_CALENDAR */ "", 52696 /* IS_PBLK7_CALENDAR_PIPE0 */ "", 52697 /* IS_PBLK7_CALENDAR_PIPE1 */ "", 52698 /* IS_PBLK7_CALENDAR_PIPE2 */ "", 52699 /* IS_PBLK7_CALENDAR_PIPE3 */ "", 52700 /* IS_PKSCH_CAL_CONFIG */ "", 52701 /* IS_PKSCH_CAL_CONFIG_PIPE0 */ "", 52702 /* IS_PKSCH_CAL_CONFIG_PIPE1 */ "", 52703 /* IS_PKSCH_CAL_CONFIG_PIPE2 */ "", 52704 /* IS_PKSCH_CAL_CONFIG_PIPE3 */ "", 52705 /* IS_PKSCH_CAL_CONFIG_PIPE4 */ "", 52706 /* IS_PKSCH_CAL_CONFIG_PIPE5 */ "", 52707 /* IS_PKSCH_CAL_CONFIG_PIPE6 */ "", 52708 /* IS_PKSCH_CAL_CONFIG_PIPE7 */ "", 52709 /* IS_PKSCH_CPU_MGMT_LB_RATIOS */ "", 52710 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE0 */ "", 52711 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE1 */ "", 52712 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE2 */ "", 52713 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE3 */ "", 52714 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE4 */ "", 52715 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE5 */ "", 52716 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE6 */ "", 52717 /* IS_PKSCH_CPU_MGMT_LB_RATIOS_PIPE7 */ "", 52718 /* IS_PKSCH_CREDIT_STS */ "", 52719 /* IS_PKSCH_PKT_CREDITS_PER_PIPE */ "", 52720 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE0 */ "", 52721 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE1 */ "", 52722 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE2 */ "", 52723 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE3 */ "", 52724 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE4 */ "", 52725 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE5 */ "", 52726 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE6 */ "", 52727 /* IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE7 */ "", 52728 /* IS_PKSCH_PKT_CREDITS_PER_PORT */ "", 52729 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE0 */ "", 52730 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE1 */ "", 52731 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE2 */ "", 52732 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE3 */ "", 52733 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE4 */ "", 52734 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE5 */ "", 52735 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE6 */ "", 52736 /* IS_PKSCH_PKT_CREDITS_PER_PORT_PIPE7 */ "", 52737 /* IS_TDM_CONFIG */ "", 52738 /* IS_TDM_CONFIG_PIPE0 */ "", 52739 /* IS_TDM_CONFIG_PIPE1 */ "", 52740 /* IS_TDM_CONFIG_PIPE2 */ "", 52741 /* IS_TDM_CONFIG_PIPE3 */ "", 52742 /* IS_TDM_DFT_REG */ "", 52743 /* IS_TDM_DFT_REG_PIPE0 */ "", 52744 /* IS_TDM_DFT_REG_PIPE1 */ "", 52745 /* IS_TDM_DFT_REG_PIPE2 */ "", 52746 /* IS_TDM_DFT_REG_PIPE3 */ "", 52747 /* IS_TDM_EN_COR_ERR_RPT */ "", 52748 /* IS_TDM_EN_COR_ERR_RPT_PIPE0 */ "", 52749 /* IS_TDM_EN_COR_ERR_RPT_PIPE1 */ "", 52750 /* IS_TDM_EN_COR_ERR_RPT_PIPE2 */ "", 52751 /* IS_TDM_EN_COR_ERR_RPT_PIPE3 */ "", 52752 /* IS_TDM_HSP */ "", 52753 /* IS_TDM_HSP_0 */ "", 52754 /* IS_TDM_HSP_1 */ "", 52755 /* IS_TDM_HSP_2 */ "", 52756 /* IS_TDM_HSP_0_PIPE0 */ "", 52757 /* IS_TDM_HSP_0_PIPE1 */ "", 52758 /* IS_TDM_HSP_1_PIPE0 */ "", 52759 /* IS_TDM_HSP_1_PIPE1 */ "", 52760 /* IS_TDM_HSP_2_PIPE0 */ "", 52761 /* IS_TDM_HSP_PIPE0 */ "", 52762 /* IS_TDM_HSP_PIPE1 */ "", 52763 /* IS_TDM_HSP_PIPE2 */ "", 52764 /* IS_TDM_HSP_PIPE3 */ "", 52765 /* IS_URG_CELL_SPACING */ "", 52766 /* IS_URG_CELL_SPACING_PIPE0 */ "", 52767 /* IS_URG_CELL_SPACING_PIPE1 */ "", 52768 /* IS_URG_CELL_SPACING_PIPE2 */ "", 52769 /* IS_URG_CELL_SPACING_PIPE3 */ "", 52770 /* IS_URG_CELL_SPACING_PIPE4 */ "", 52771 /* IS_URG_CELL_SPACING_PIPE5 */ "", 52772 /* IS_URG_CELL_SPACING_PIPE6 */ "", 52773 /* IS_URG_CELL_SPACING_PIPE7 */ "", 52774 /* IT64 */ "MAC_GTx64", 52775 /* IT127 */ "MAC_GTx127", 52776 /* IT255 */ "MAC_GTx255", 52777 /* IT511 */ "MAC_GTx511", 52778 /* IT1023 */ "MAC_GTx1023", 52779 /* IT1518 */ "MAC_GTx1518", 52780 /* IT2047 */ "MAC_GTx2047", 52781 /* IT4095 */ "MAC_GTx4095", 52782 /* IT9216 */ "MAC_GTx9216", 52783 /* IT16383 */ "MAC_GTx16383", 52784 /* ITAG_ETHERTYPE */ "", 52785 /* ITBCA */ "MAC_GTxBCA", 52786 /* ITBYT */ "MAC_GTxByt", 52787 /* ITERR */ "MAC_GTxErr", 52788 /* ITE_ALIGN_GENERAL_CONFIGURATION */ "", 52789 /* ITE_BIG_LAT_CNI_CNTR */ "", 52790 /* ITE_BIG_LAT_PKTS_CNTR */ "", 52791 /* ITE_CONFIG */ "", 52792 /* ITE_DEBUG_COUNTERS */ "", 52793 /* ITE_DELETED_LAT_PKTS_CNT */ "", 52794 /* ITE_ECC_1B_ERR_CNT */ "", 52795 /* ITE_ECC_2B_ERR_CNT */ "", 52796 /* ITE_ECC_ERR_1B_INITIATE */ "", 52797 /* ITE_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 52798 /* ITE_ECC_ERR_2B_INITIATE */ "", 52799 /* ITE_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 52800 /* ITE_ECC_INTERRUPT_REGISTER */ "", 52801 /* ITE_ECC_INTERRUPT_REGISTER_MASK */ "", 52802 /* ITE_ECC_INTERRUPT_REGISTER_TEST */ "", 52803 /* ITE_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 52804 /* ITE_ERROR_INITIATION_DATA */ "", 52805 /* ITE_GLOBAL_GENERAL_CFG_3 */ "", 52806 /* ITE_GLOBAL_MEM_OPTIONS */ "", 52807 /* ITE_GLOBAL_ONE_PLUS_ONE_PORT_PROTECTION */ "", 52808 /* ITE_GLOBAL_SYS_HEADER_CFG */ "", 52809 /* ITE_GTIMER_CONFIGURATION */ "", 52810 /* ITE_INCOMING_PACKET_CNTR */ "", 52811 /* ITE_INDIRECT_COMMAND */ "", 52812 /* ITE_INDIRECT_COMMAND_ADDRESS */ "", 52813 /* ITE_INDIRECT_COMMAND_DATA_INCREMENT */ "", 52814 /* ITE_INDIRECT_COMMAND_RD_DATA */ "", 52815 /* ITE_INDIRECT_COMMAND_WIDE_MEM */ "", 52816 /* ITE_INDIRECT_COMMAND_WR_DATA */ "", 52817 /* ITE_INDIRECT_FORCE_BUBBLE */ "", 52818 /* ITE_INTERRUPT_MASK_REGISTER */ "", 52819 /* ITE_INTERRUPT_REGISTER */ "", 52820 /* ITE_INTERRUPT_REGISTER_TEST */ "", 52821 /* ITE_ITPP_GENERAL_CFG */ "", 52822 /* ITE_LAST_GENERATED_VALUES */ "", 52823 /* ITE_LAST_PKT_HDR */ "", 52824 /* ITE_LAST_PKT_PRG */ "", 52825 /* ITE_LAST_RECEIVED_ATTRIBUTES */ "", 52826 /* ITE_LAST_RECEIVED_HEADER_0 */ "", 52827 /* ITE_LAST_RECEIVED_HEADER_1 */ "", 52828 /* ITE_MAPPING_FWD_CODE_TO_TERM_EN */ "", 52829 /* ITE_MAPPING_QUEUE_TYPE_TO_MIRROR_PACKET */ "", 52830 /* ITE_MAPPING_QUEUE_TYPE_TO_SNOOP_PACKET */ "", 52831 /* ITE_MAP_UDH_TYPE_TO_LENGTH */ "", 52832 /* ITE_MAX_LATENCY_LAT_PKT */ "", 52833 /* ITE_PACKET_LATENCY_FORMAT */ "", 52834 /* ITE_PACKET_LATENCY_MEASUREMENT */ "", 52835 /* ITE_PPH_RES_EN_TERM */ "", 52836 /* ITE_RESERVED_MIRROR_ADDR */ "", 52837 /* ITE_RESERVED_MTCD */ "", 52838 /* ITE_RESERVED_MTCP */ "", 52839 /* ITE_RESERVED_SPARE_0 */ "", 52840 /* ITE_RESERVED_SPARE_1 */ "", 52841 /* ITE_RESERVED_SPARE_2 */ "", 52842 /* ITE_RESERVED_SPARE_3 */ "", 52843 /* ITE_SBUS_BROADCAST_ID */ "", 52844 /* ITE_SBUS_LAST_IN_CHAIN */ "", 52845 /* ITE_SCHED_WRR_WEIGHT_COS0 */ "", 52846 /* ITE_SCHED_WRR_WEIGHT_COS1 */ "", 52847 /* ITE_SCHED_WRR_WEIGHT_COS2 */ "", 52848 /* ITE_SCHED_WRR_WEIGHT_COS3 */ "", 52849 /* ITE_SCHED_WRR_WEIGHT_COS4 */ "", 52850 /* ITE_SCHED_WRR_WEIGHT_COS5 */ "", 52851 /* ITE_SCHED_WRR_WEIGHT_COS6 */ "", 52852 /* ITE_SCHED_WRR_WEIGHT_COS7 */ "", 52853 /* ITE_SEGMENTS_GAP */ "", 52854 /* ITE_STAMPING_FABRIC_HEADER_ENABLE */ "", 52855 /* ITE_STAMPING_FTMH_OUTLIF_ENABLE */ "", 52856 /* ITE_STAMPING_PPH_OUTRIF_ENABLE */ "", 52857 /* ITE_STAMPING_USR_DEF_OUTLIF_ENABLE */ "", 52858 /* ITE_TO_EMC_WR_REQ_EOP_COUNT_DEBUG */ "", 52859 /* ITE_TO_EMC_WR_REQ_SOP_COUNT_DEBUG */ "", 52860 /* ITE_TXI_COUNTER */ "", 52861 /* ITFCS */ "MAC_GTxFCS", 52862 /* ITFRG */ "MAC_GTxFrg", 52863 /* ITMAX */ "MAC_GTxMAX", 52864 /* ITMCA */ "MAC_GTxMCA", 52865 /* ITOVR */ "MAC_GTxOvr", 52866 /* ITPKT */ "MAC_GTxPkt", 52867 /* ITPOK */ "MAC_GTxPOK", 52868 /* ITPPD_BIG_LAT_CNI_CNTR */ "", 52869 /* ITPPD_DELETED_LAT_PKTS_CNT */ "", 52870 /* ITPPD_ECC_1B_ERR_CNT */ "", 52871 /* ITPPD_ECC_2B_ERR_CNT */ "", 52872 /* ITPPD_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 52873 /* ITPPD_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 52874 /* ITPPD_ECC_INTERRUPT_REGISTER */ "", 52875 /* ITPPD_ECC_INTERRUPT_REGISTER_MASK */ "", 52876 /* ITPPD_ECC_INTERRUPT_REGISTER_TEST */ "", 52877 /* ITPPD_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 52878 /* ITPPD_ERROR_INITIATION_DATA */ "", 52879 /* ITPPD_GTIMER_CONFIGURATION */ "", 52880 /* ITPPD_GTIMER_CYCLE */ "", 52881 /* ITPPD_INCOMING_PACKET_CNTR */ "", 52882 /* ITPPD_INDIRECT_COMMAND */ "", 52883 /* ITPPD_INDIRECT_COMMAND_ADDRESS */ "", 52884 /* ITPPD_INDIRECT_COMMAND_RD_DATA */ "", 52885 /* ITPPD_INDIRECT_COMMAND_WR_DATA */ "", 52886 /* ITPPD_INDIRECT_FORCE_BUBBLE */ "", 52887 /* ITPPD_INTERRUPT_MASK_REGISTER */ "", 52888 /* ITPPD_INTERRUPT_REGISTER */ "", 52889 /* ITPPD_INTERRUPT_REGISTER_TEST */ "", 52890 /* ITPPD_ITPP_GENERAL_CFG */ "", 52891 /* ITPPD_LAST_GENERATED_HDR */ "", 52892 /* ITPPD_LAST_GENERATED_VALUES */ "", 52893 /* ITPPD_LAST_RECEIVED_ATTRIBUTES */ "", 52894 /* ITPPD_LAST_RECEIVED_HEADER_0 */ "", 52895 /* ITPPD_LAST_RECEIVED_HEADER_1 */ "", 52896 /* ITPPD_MAPPING_FWD_INFO_TO_EN_TERM */ "", 52897 /* ITPPD_MAPPING_QUEUE_TYPE_TO_SNIFF_PACKET */ "", 52898 /* ITPPD_MAX_LATENCY_LAT_PKT */ "", 52899 /* ITPPD_PACKET_LATENCY_FORMAT */ "", 52900 /* ITPPD_REG_0041 */ "", 52901 /* ITPPD_REG_00A4 */ "", 52902 /* ITPPD_REG_00A6 */ "", 52903 /* ITPPD_REG_00C2 */ "", 52904 /* ITPPD_REG_00C6 */ "", 52905 /* ITPPD_RESERVED_MIRROR_ADDR */ "", 52906 /* ITPPD_RESERVED_MTCD */ "", 52907 /* ITPPD_RESERVED_MTCP */ "", 52908 /* ITPPD_RESERVED_SPARE_0 */ "", 52909 /* ITPPD_RESERVED_SPARE_1 */ "", 52910 /* ITPPD_RESERVED_SPARE_2 */ "", 52911 /* ITPPD_RESERVED_SPARE_3 */ "", 52912 /* ITPPD_SBUS_BROADCAST_ID */ "", 52913 /* ITPPD_SBUS_LAST_IN_CHAIN */ "", 52914 /* ITPPD_SPECIAL_CLOCK_CONTROLS */ "", 52915 /* ITPPD_STAMPING_FABRIC_HEADER_ENABLE */ "", 52916 /* ITPPD_SYSTEM_HEADERS_PPH */ "", 52917 /* ITPPD_VOQ_TC_MAP */ "", 52918 /* ITPP_BIG_LAT_CNI_CNTR */ "", 52919 /* ITPP_DELETED_LAT_PKTS_CNT */ "", 52920 /* ITPP_ECC_1B_ERR_CNT */ "", 52921 /* ITPP_ECC_2B_ERR_CNT */ "", 52922 /* ITPP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 52923 /* ITPP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 52924 /* ITPP_ECC_INTERRUPT_REGISTER */ "", 52925 /* ITPP_ECC_INTERRUPT_REGISTER_MASK */ "", 52926 /* ITPP_ECC_INTERRUPT_REGISTER_TEST */ "", 52927 /* ITPP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 52928 /* ITPP_ERROR_INITIATION_DATA */ "", 52929 /* ITPP_GTIMER_CONFIGURATION */ "", 52930 /* ITPP_GTIMER_CYCLE */ "", 52931 /* ITPP_INCOMING_PACKET_CNTR */ "", 52932 /* ITPP_INDIRECT_COMMAND */ "", 52933 /* ITPP_INDIRECT_COMMAND_ADDRESS */ "", 52934 /* ITPP_INDIRECT_COMMAND_RD_DATA */ "", 52935 /* ITPP_INDIRECT_COMMAND_WR_DATA */ "", 52936 /* ITPP_INDIRECT_FORCE_BUBBLE */ "", 52937 /* ITPP_INTERRUPT_MASK_REGISTER */ "", 52938 /* ITPP_INTERRUPT_REGISTER */ "", 52939 /* ITPP_INTERRUPT_REGISTER_TEST */ "", 52940 /* ITPP_ITPP_GENERAL_CFG */ "", 52941 /* ITPP_LAST_GENERATED_HDR */ "", 52942 /* ITPP_LAST_GENERATED_VALUES */ "", 52943 /* ITPP_LAST_RECEIVED_ATTRIBUTES */ "", 52944 /* ITPP_LAST_RECEIVED_HEADER_0 */ "", 52945 /* ITPP_LAST_RECEIVED_HEADER_1 */ "", 52946 /* ITPP_MAPPING_FWD_INFO_TO_EN_TERM */ "", 52947 /* ITPP_MAPPING_QUEUE_TYPE_TO_SNIFF_PACKET */ "", 52948 /* ITPP_MAX_LATENCY_LAT_PKT */ "", 52949 /* ITPP_PACKET_LATENCY_FORMAT */ "", 52950 /* ITPP_REG_0041 */ "", 52951 /* ITPP_REG_00A4 */ "", 52952 /* ITPP_REG_00A6 */ "", 52953 /* ITPP_REG_00C2 */ "", 52954 /* ITPP_REG_00C6 */ "", 52955 /* ITPP_RESERVED_MIRROR_ADDR */ "", 52956 /* ITPP_RESERVED_MTCD */ "", 52957 /* ITPP_RESERVED_MTCP */ "", 52958 /* ITPP_RESERVED_SPARE_0 */ "", 52959 /* ITPP_RESERVED_SPARE_1 */ "", 52960 /* ITPP_RESERVED_SPARE_2 */ "", 52961 /* ITPP_RESERVED_SPARE_3 */ "", 52962 /* ITPP_SBUS_BROADCAST_ID */ "", 52963 /* ITPP_SBUS_LAST_IN_CHAIN */ "", 52964 /* ITPP_SPECIAL_CLOCK_CONTROLS */ "", 52965 /* ITPP_STAMPING_FABRIC_HEADER_ENABLE */ "", 52966 /* ITPP_SYSTEM_HEADERS_PPH */ "", 52967 /* ITPP_VOQ_TC_MAP */ "", 52968 /* ITUC */ "MAC_GTxUC", 52969 /* ITUCA */ "MAC_GTxUCA", 52970 /* ITUFL */ "MAC_GTxUfl", 52971 /* ITXPF */ "MAC_GTxPF", 52972 /* ITXPP */ "MAC_GTxPP", 52973 /* IUNHGI */ "", 52974 /* IUNHGI_64 */ "IUNHGI", 52975 /* IUNKNOWN_MCAST_BLOCK_MASK */ "", 52976 /* IUNKNOWN_MCAST_BLOCK_MASK_64 */ "IUNKNOWN_MCAST_BLOCK_MASK", 52977 /* IUNKNOWN_MCAST_BLOCK_MASK_HI */ "", 52978 /* IUNKNOWN_MCAST_BLOCK_MASK_HI_64 */ "IUNKNOWN_MCAST_BLOCK_MASK_HI_64", 52979 /* IUNKNOWN_MCAST_BLOCK_MASK_LO_64 */ "IUNKNOWN_MCAST_BLOCK_MASK_LO_64", 52980 /* IUNKNOWN_UCAST_BLOCK_MASK */ "", 52981 /* IUNKNOWN_UCAST_BLOCK_MASK_64 */ "IUNKNOWN_UCAST_BLOCK_MASK", 52982 /* IUNKNOWN_UCAST_BLOCK_MASK_HI */ "", 52983 /* IUNKNOWN_UCAST_BLOCK_MASK_HI_64 */ "IUNKNOWN_UCAST_BLOCK_MASK_HI_64", 52984 /* IUNKNOWN_UCAST_BLOCK_MASK_LO_64 */ "IUNKNOWN_UCAST_BLOCK_MASK_LO_64", 52985 /* IUNKOPC */ "", 52986 /* IUNKOPC_64 */ "IUNKOPC", 52987 /* IUSER_TRUNK_HASH_SELECT */ "", 52988 /* IVLAN_BUS_PARITY_DEBUG */ "", 52989 /* IVLAN_DBGCTRL */ "IVLAN_DEBUG", 52990 /* IVLAN_ECC_ERROR */ "", 52991 /* IVLAN_ECC_ERROR_MASK */ "", 52992 /* IVLAN_INIT */ "IVLAN_MEM_INIT", 52993 /* IVLAN_INIT_DATA0 */ "", 52994 /* IVLAN_INIT_DATA1 */ "", 52995 /* IVLAN_PARITY_ERROR */ "", 52996 /* IVLAN_PARITY_ERROR_MASK */ "", 52997 /* IVLAN_REGS_DEBUG */ "", 52998 /* IVLAN_SER_CONTROL */ "", 52999 /* IVLAN_TM_REG_1 */ "", 53000 /* IVP_CLK_GATING_CONTROL */ "", 53001 /* IVP_EN_COR_ERR_RPT */ "", 53002 /* IVP_MY_STATION_CAM_CONTROL */ "", 53003 /* IVP_MY_STATION_TCAM_1_BIST_CONFIG_64 */ "", 53004 /* IVP_MY_STATION_TCAM_1_BIST_CONFIG_64_PIPE0 */ "", 53005 /* IVP_MY_STATION_TCAM_1_BIST_CONFIG_64_PIPE1 */ "", 53006 /* IVP_MY_STATION_TCAM_1_BIST_STATUS */ "", 53007 /* IVP_MY_STATION_TCAM_1_BIST_STATUS_PIPE0 */ "", 53008 /* IVP_MY_STATION_TCAM_1_BIST_STATUS_PIPE1 */ "", 53009 /* IVP_RAM_CONTROL_0 */ "", 53010 /* IVP_RAM_CONTROL_1 */ "", 53011 /* IVP_RAM_CONTROL_2 */ "", 53012 /* IVP_RAM_CONTROL_3 */ "", 53013 /* IVP_RAM_CONTROL_4 */ "", 53014 /* IVP_RAM_CONTROL_0_PIPE0 */ "", 53015 /* IVP_RAM_CONTROL_0_PIPE1 */ "", 53016 /* IVP_RAM_CONTROL_1_PIPE0 */ "", 53017 /* IVP_RAM_CONTROL_1_PIPE1 */ "", 53018 /* IVP_RAM_CONTROL_2_PIPE0 */ "", 53019 /* IVP_RAM_CONTROL_2_PIPE1 */ "", 53020 /* IVP_RAM_CONTROL_3_PIPE0 */ "", 53021 /* IVP_RAM_CONTROL_3_PIPE1 */ "", 53022 /* IVP_RAM_CONTROL_4_PIPE0 */ "", 53023 /* IVP_RAM_CONTROL_4_PIPE1 */ "", 53024 /* IVP_SER_CONTROL */ "", 53025 /* IVXLT1_EN_COR_ERR_RPT */ "", 53026 /* IVXLT1_PT_HWY_RAM_CONTROL_DBGCTRL */ "IVXLT1_PT_HWY_RAM_CONTROL", 53027 /* IVXLT1_PT_HWY_RAM_CONTROL_DBGCTRL_PIPE0 */ "IVXLT1_PT_HWY_RAM_CONTROL_PIPE0", 53028 /* IVXLT1_PT_HWY_RAM_CONTROL_DBGCTRL_PIPE1 */ "IVXLT1_PT_HWY_RAM_CONTROL_PIPE1", 53029 /* IVXLT1_RAM_CONTROL_DBGCTRL */ "IVXLT1_RAM_CONTROL", 53030 /* IVXLT1_RAM_CONTROL_DBGCTRL_PIPE0 */ "IVXLT1_RAM_CONTROL_PIPE0", 53031 /* IVXLT1_RAM_CONTROL_DBGCTRL_PIPE1 */ "IVXLT1_RAM_CONTROL_PIPE1", 53032 /* IVXLT1_SER_CONTROL */ "", 53033 /* IVXLT2_EN_COR_ERR_RPT */ "", 53034 /* IVXLT2_RAM_CONTROL_2_DBGCTRL */ "IVXLT2_RAM_CONTROL_1", 53035 /* IVXLT2_RAM_CONTROL_2_DBGCTRL_PIPE0 */ "IVXLT2_RAM_CONTROL_1_PIPE0", 53036 /* IVXLT2_RAM_CONTROL_2_DBGCTRL_PIPE1 */ "IVXLT2_RAM_CONTROL_1_PIPE1", 53037 /* IVXLT2_RAM_CONTROL_DBGCTRL */ "IVXLT2_RAM_CONTROL", 53038 /* IVXLT2_RAM_CONTROL_DBGCTRL_PIPE0 */ "IVXLT2_RAM_CONTROL_PIPE0", 53039 /* IVXLT2_RAM_CONTROL_DBGCTRL_PIPE1 */ "IVXLT2_RAM_CONTROL_PIPE1", 53040 /* IVXLT2_SER_CONTROL */ "", 53041 /* IVXLT_BUS_PARITY_DEBUG */ "", 53042 /* IVXLT_CONTROL */ "", 53043 /* IVXLT_EN_COR_ERR_RPT */ "", 53044 /* IVXLT_PARITY_ERROR */ "", 53045 /* IVXLT_PARITY_ERROR_MASK */ "", 53046 /* IVXLT_PT_HWY_RAM_CONTROL_DBGCTRL */ "IVXLT_PT_HWY_RAM_CONTROL", 53047 /* IVXLT_PT_HWY_RAM_CONTROL_DBGCTRL_PIPE0 */ "IVXLT_PT_HWY_RAM_CONTROL_PIPE0", 53048 /* IVXLT_PT_HWY_RAM_CONTROL_DBGCTRL_PIPE1 */ "IVXLT_PT_HWY_RAM_CONTROL_PIPE1", 53049 /* IVXLT_PT_HWY_RAM_CONTROL_DBGCTRL_PIPE2 */ "IVXLT_PT_HWY_RAM_CONTROL_PIPE2", 53050 /* IVXLT_PT_HWY_RAM_CONTROL_DBGCTRL_PIPE3 */ "IVXLT_PT_HWY_RAM_CONTROL_PIPE3", 53051 /* IVXLT_SER_CONTROL */ "", 53052 /* IVXLT_TM_REG_1 */ "", 53053 /* IVXLT_TM_REG_2 */ "", 53054 /* JBCASCFG_CHID_0 */ "", 53055 /* JBCASCFG_CHID_1 */ "", 53056 /* JBCASCFG_CHID_2 */ "", 53057 /* JBCASCFG_CHID_3 */ "", 53058 /* JBCASCFG_CHID_4 */ "", 53059 /* JBCASCFG_CHID_5 */ "", 53060 /* JBCASCFG_CHID_6 */ "", 53061 /* JBCASCFG_CHID_7 */ "", 53062 /* JBCASCFG_CHID_8 */ "", 53063 /* JBCASCFG_CHID_9 */ "", 53064 /* JBCASCFG_CHID_10 */ "", 53065 /* JBCASCFG_CHID_11 */ "", 53066 /* JBCASCFG_CHID_12 */ "", 53067 /* JBCASCFG_CHID_13 */ "", 53068 /* JBCASCFG_CHID_14 */ "", 53069 /* JBCASCFG_CHID_15 */ "", 53070 /* JBCASCFG_CHID_16 */ "", 53071 /* JBCASCFG_CHID_17 */ "", 53072 /* JBCASCFG_CHID_18 */ "", 53073 /* JBCASCFG_CHID_19 */ "", 53074 /* JBCASCFG_CHID_20 */ "", 53075 /* JBCASCFG_CHID_21 */ "", 53076 /* JBCASCFG_CHID_22 */ "", 53077 /* JBCASCFG_CHID_23 */ "", 53078 /* JBCASCFG_CHID_24 */ "", 53079 /* JBCASCFG_CHID_25 */ "", 53080 /* JBCASCFG_CHID_26 */ "", 53081 /* JBCASCFG_CHID_27 */ "", 53082 /* JBCASCFG_CHID_28 */ "", 53083 /* JBCASCFG_CHID_29 */ "", 53084 /* JBCASCFG_CHID_30 */ "", 53085 /* JBCASCFG_CHID_31 */ "", 53086 /* JBCASCFG_CHID_32 */ "", 53087 /* JBCASCFG_CHID_33 */ "", 53088 /* JBCASCFG_CHID_34 */ "", 53089 /* JBCASCFG_CHID_35 */ "", 53090 /* JBCASCFG_CHID_36 */ "", 53091 /* JBCASCFG_CHID_37 */ "", 53092 /* JBCASCFG_CHID_38 */ "", 53093 /* JBCASCFG_CHID_39 */ "", 53094 /* JBCASCFG_CHID_40 */ "", 53095 /* JBCASCFG_CHID_41 */ "", 53096 /* JBCASCFG_CHID_42 */ "", 53097 /* JBCASCFG_CHID_43 */ "", 53098 /* JBCASCFG_CHID_44 */ "", 53099 /* JBCASCFG_CHID_45 */ "", 53100 /* JBCASCFG_CHID_46 */ "", 53101 /* JBCASCFG_CHID_47 */ "", 53102 /* JBCASCFG_CHID_48 */ "", 53103 /* JBCASCFG_CHID_49 */ "", 53104 /* JBCASCFG_CHID_50 */ "", 53105 /* JBCASCFG_CHID_51 */ "", 53106 /* JBCASCFG_CHID_52 */ "", 53107 /* JBCASCFG_CHID_53 */ "", 53108 /* JBCASCFG_CHID_54 */ "", 53109 /* JBCASCFG_CHID_55 */ "", 53110 /* JBCASCFG_CHID_56 */ "", 53111 /* JBCASCFG_CHID_57 */ "", 53112 /* JBCASCFG_CHID_58 */ "", 53113 /* JBCASCFG_CHID_59 */ "", 53114 /* JBCASCFG_CHID_60 */ "", 53115 /* JBCASCFG_CHID_61 */ "", 53116 /* JBCASCFG_CHID_62 */ "", 53117 /* JBCASCFG_CHID_63 */ "", 53118 /* JBCASWIN */ "", 53119 /* JBCHCFG1_CHID_0 */ "", 53120 /* JBCHCFG1_CHID_1 */ "", 53121 /* JBCHCFG1_CHID_2 */ "", 53122 /* JBCHCFG1_CHID_3 */ "", 53123 /* JBCHCFG1_CHID_4 */ "", 53124 /* JBCHCFG1_CHID_5 */ "", 53125 /* JBCHCFG1_CHID_6 */ "", 53126 /* JBCHCFG1_CHID_7 */ "", 53127 /* JBCHCFG1_CHID_8 */ "", 53128 /* JBCHCFG1_CHID_9 */ "", 53129 /* JBCHCFG1_CHID_10 */ "", 53130 /* JBCHCFG1_CHID_11 */ "", 53131 /* JBCHCFG1_CHID_12 */ "", 53132 /* JBCHCFG1_CHID_13 */ "", 53133 /* JBCHCFG1_CHID_14 */ "", 53134 /* JBCHCFG1_CHID_15 */ "", 53135 /* JBCHCFG1_CHID_16 */ "", 53136 /* JBCHCFG1_CHID_17 */ "", 53137 /* JBCHCFG1_CHID_18 */ "", 53138 /* JBCHCFG1_CHID_19 */ "", 53139 /* JBCHCFG1_CHID_20 */ "", 53140 /* JBCHCFG1_CHID_21 */ "", 53141 /* JBCHCFG1_CHID_22 */ "", 53142 /* JBCHCFG1_CHID_23 */ "", 53143 /* JBCHCFG1_CHID_24 */ "", 53144 /* JBCHCFG1_CHID_25 */ "", 53145 /* JBCHCFG1_CHID_26 */ "", 53146 /* JBCHCFG1_CHID_27 */ "", 53147 /* JBCHCFG1_CHID_28 */ "", 53148 /* JBCHCFG1_CHID_29 */ "", 53149 /* JBCHCFG1_CHID_30 */ "", 53150 /* JBCHCFG1_CHID_31 */ "", 53151 /* JBCHCFG1_CHID_32 */ "", 53152 /* JBCHCFG1_CHID_33 */ "", 53153 /* JBCHCFG1_CHID_34 */ "", 53154 /* JBCHCFG1_CHID_35 */ "", 53155 /* JBCHCFG1_CHID_36 */ "", 53156 /* JBCHCFG1_CHID_37 */ "", 53157 /* JBCHCFG1_CHID_38 */ "", 53158 /* JBCHCFG1_CHID_39 */ "", 53159 /* JBCHCFG1_CHID_40 */ "", 53160 /* JBCHCFG1_CHID_41 */ "", 53161 /* JBCHCFG1_CHID_42 */ "", 53162 /* JBCHCFG1_CHID_43 */ "", 53163 /* JBCHCFG1_CHID_44 */ "", 53164 /* JBCHCFG1_CHID_45 */ "", 53165 /* JBCHCFG1_CHID_46 */ "", 53166 /* JBCHCFG1_CHID_47 */ "", 53167 /* JBCHCFG1_CHID_48 */ "", 53168 /* JBCHCFG1_CHID_49 */ "", 53169 /* JBCHCFG1_CHID_50 */ "", 53170 /* JBCHCFG1_CHID_51 */ "", 53171 /* JBCHCFG1_CHID_52 */ "", 53172 /* JBCHCFG1_CHID_53 */ "", 53173 /* JBCHCFG1_CHID_54 */ "", 53174 /* JBCHCFG1_CHID_55 */ "", 53175 /* JBCHCFG1_CHID_56 */ "", 53176 /* JBCHCFG1_CHID_57 */ "", 53177 /* JBCHCFG1_CHID_58 */ "", 53178 /* JBCHCFG1_CHID_59 */ "", 53179 /* JBCHCFG1_CHID_60 */ "", 53180 /* JBCHCFG1_CHID_61 */ "", 53181 /* JBCHCFG1_CHID_62 */ "", 53182 /* JBCHCFG1_CHID_63 */ "", 53183 /* JBCHCFG2_CHID_0 */ "", 53184 /* JBCHCFG2_CHID_1 */ "", 53185 /* JBCHCFG2_CHID_2 */ "", 53186 /* JBCHCFG2_CHID_3 */ "", 53187 /* JBCHCFG2_CHID_4 */ "", 53188 /* JBCHCFG2_CHID_5 */ "", 53189 /* JBCHCFG2_CHID_6 */ "", 53190 /* JBCHCFG2_CHID_7 */ "", 53191 /* JBCHCFG2_CHID_8 */ "", 53192 /* JBCHCFG2_CHID_9 */ "", 53193 /* JBCHCFG2_CHID_10 */ "", 53194 /* JBCHCFG2_CHID_11 */ "", 53195 /* JBCHCFG2_CHID_12 */ "", 53196 /* JBCHCFG2_CHID_13 */ "", 53197 /* JBCHCFG2_CHID_14 */ "", 53198 /* JBCHCFG2_CHID_15 */ "", 53199 /* JBCHCFG2_CHID_16 */ "", 53200 /* JBCHCFG2_CHID_17 */ "", 53201 /* JBCHCFG2_CHID_18 */ "", 53202 /* JBCHCFG2_CHID_19 */ "", 53203 /* JBCHCFG2_CHID_20 */ "", 53204 /* JBCHCFG2_CHID_21 */ "", 53205 /* JBCHCFG2_CHID_22 */ "", 53206 /* JBCHCFG2_CHID_23 */ "", 53207 /* JBCHCFG2_CHID_24 */ "", 53208 /* JBCHCFG2_CHID_25 */ "", 53209 /* JBCHCFG2_CHID_26 */ "", 53210 /* JBCHCFG2_CHID_27 */ "", 53211 /* JBCHCFG2_CHID_28 */ "", 53212 /* JBCHCFG2_CHID_29 */ "", 53213 /* JBCHCFG2_CHID_30 */ "", 53214 /* JBCHCFG2_CHID_31 */ "", 53215 /* JBCHCFG2_CHID_32 */ "", 53216 /* JBCHCFG2_CHID_33 */ "", 53217 /* JBCHCFG2_CHID_34 */ "", 53218 /* JBCHCFG2_CHID_35 */ "", 53219 /* JBCHCFG2_CHID_36 */ "", 53220 /* JBCHCFG2_CHID_37 */ "", 53221 /* JBCHCFG2_CHID_38 */ "", 53222 /* JBCHCFG2_CHID_39 */ "", 53223 /* JBCHCFG2_CHID_40 */ "", 53224 /* JBCHCFG2_CHID_41 */ "", 53225 /* JBCHCFG2_CHID_42 */ "", 53226 /* JBCHCFG2_CHID_43 */ "", 53227 /* JBCHCFG2_CHID_44 */ "", 53228 /* JBCHCFG2_CHID_45 */ "", 53229 /* JBCHCFG2_CHID_46 */ "", 53230 /* JBCHCFG2_CHID_47 */ "", 53231 /* JBCHCFG2_CHID_48 */ "", 53232 /* JBCHCFG2_CHID_49 */ "", 53233 /* JBCHCFG2_CHID_50 */ "", 53234 /* JBCHCFG2_CHID_51 */ "", 53235 /* JBCHCFG2_CHID_52 */ "", 53236 /* JBCHCFG2_CHID_53 */ "", 53237 /* JBCHCFG2_CHID_54 */ "", 53238 /* JBCHCFG2_CHID_55 */ "", 53239 /* JBCHCFG2_CHID_56 */ "", 53240 /* JBCHCFG2_CHID_57 */ "", 53241 /* JBCHCFG2_CHID_58 */ "", 53242 /* JBCHCFG2_CHID_59 */ "", 53243 /* JBCHCFG2_CHID_60 */ "", 53244 /* JBCHCFG2_CHID_61 */ "", 53245 /* JBCHCFG2_CHID_62 */ "", 53246 /* JBCHCFG2_CHID_63 */ "", 53247 /* JBCSTAT_CHID_0 */ "", 53248 /* JBCSTAT_CHID_1 */ "", 53249 /* JBCSTAT_CHID_2 */ "", 53250 /* JBCSTAT_CHID_3 */ "", 53251 /* JBCSTAT_CHID_4 */ "", 53252 /* JBCSTAT_CHID_5 */ "", 53253 /* JBCSTAT_CHID_6 */ "", 53254 /* JBCSTAT_CHID_7 */ "", 53255 /* JBCSTAT_CHID_8 */ "", 53256 /* JBCSTAT_CHID_9 */ "", 53257 /* JBCSTAT_CHID_10 */ "", 53258 /* JBCSTAT_CHID_11 */ "", 53259 /* JBCSTAT_CHID_12 */ "", 53260 /* JBCSTAT_CHID_13 */ "", 53261 /* JBCSTAT_CHID_14 */ "", 53262 /* JBCSTAT_CHID_15 */ "", 53263 /* JBCSTAT_CHID_16 */ "", 53264 /* JBCSTAT_CHID_17 */ "", 53265 /* JBCSTAT_CHID_18 */ "", 53266 /* JBCSTAT_CHID_19 */ "", 53267 /* JBCSTAT_CHID_20 */ "", 53268 /* JBCSTAT_CHID_21 */ "", 53269 /* JBCSTAT_CHID_22 */ "", 53270 /* JBCSTAT_CHID_23 */ "", 53271 /* JBCSTAT_CHID_24 */ "", 53272 /* JBCSTAT_CHID_25 */ "", 53273 /* JBCSTAT_CHID_26 */ "", 53274 /* JBCSTAT_CHID_27 */ "", 53275 /* JBCSTAT_CHID_28 */ "", 53276 /* JBCSTAT_CHID_29 */ "", 53277 /* JBCSTAT_CHID_30 */ "", 53278 /* JBCSTAT_CHID_31 */ "", 53279 /* JBCSTAT_CHID_32 */ "", 53280 /* JBCSTAT_CHID_33 */ "", 53281 /* JBCSTAT_CHID_34 */ "", 53282 /* JBCSTAT_CHID_35 */ "", 53283 /* JBCSTAT_CHID_36 */ "", 53284 /* JBCSTAT_CHID_37 */ "", 53285 /* JBCSTAT_CHID_38 */ "", 53286 /* JBCSTAT_CHID_39 */ "", 53287 /* JBCSTAT_CHID_40 */ "", 53288 /* JBCSTAT_CHID_41 */ "", 53289 /* JBCSTAT_CHID_42 */ "", 53290 /* JBCSTAT_CHID_43 */ "", 53291 /* JBCSTAT_CHID_44 */ "", 53292 /* JBCSTAT_CHID_45 */ "", 53293 /* JBCSTAT_CHID_46 */ "", 53294 /* JBCSTAT_CHID_47 */ "", 53295 /* JBCSTAT_CHID_48 */ "", 53296 /* JBCSTAT_CHID_49 */ "", 53297 /* JBCSTAT_CHID_50 */ "", 53298 /* JBCSTAT_CHID_51 */ "", 53299 /* JBCSTAT_CHID_52 */ "", 53300 /* JBCSTAT_CHID_53 */ "", 53301 /* JBCSTAT_CHID_54 */ "", 53302 /* JBCSTAT_CHID_55 */ "", 53303 /* JBCSTAT_CHID_56 */ "", 53304 /* JBCSTAT_CHID_57 */ "", 53305 /* JBCSTAT_CHID_58 */ "", 53306 /* JBCSTAT_CHID_59 */ "", 53307 /* JBCSTAT_CHID_60 */ "", 53308 /* JBCSTAT_CHID_61 */ "", 53309 /* JBCSTAT_CHID_62 */ "", 53310 /* JBCSTAT_CHID_63 */ "", 53311 /* JBDEPC_TCID_0 */ "", 53312 /* JBDEPC_TCID_1 */ "", 53313 /* JBDEPC_TCID_2 */ "", 53314 /* JBDEPC_TCID_3 */ "", 53315 /* JBDEPC_TCID_4 */ "", 53316 /* JBDEPC_TCID_5 */ "", 53317 /* JBDEPC_TCID_6 */ "", 53318 /* JBDEPC_TCID_7 */ "", 53319 /* JBDEPC_TCID_8 */ "", 53320 /* JBDEPC_TCID_9 */ "", 53321 /* JBDEPC_TCID_10 */ "", 53322 /* JBDEPC_TCID_11 */ "", 53323 /* JBDEPC_TCID_12 */ "", 53324 /* JBDEPC_TCID_13 */ "", 53325 /* JBDEPC_TCID_14 */ "", 53326 /* JBDEPC_TCID_15 */ "", 53327 /* JBDMAX1_CHID_0 */ "", 53328 /* JBDMAX1_CHID_1 */ "", 53329 /* JBDMAX1_CHID_2 */ "", 53330 /* JBDMAX1_CHID_3 */ "", 53331 /* JBDMAX1_CHID_4 */ "", 53332 /* JBDMAX1_CHID_5 */ "", 53333 /* JBDMAX1_CHID_6 */ "", 53334 /* JBDMAX1_CHID_7 */ "", 53335 /* JBDMAX1_CHID_8 */ "", 53336 /* JBDMAX1_CHID_9 */ "", 53337 /* JBDMAX1_CHID_10 */ "", 53338 /* JBDMAX1_CHID_11 */ "", 53339 /* JBDMAX1_CHID_12 */ "", 53340 /* JBDMAX1_CHID_13 */ "", 53341 /* JBDMAX1_CHID_14 */ "", 53342 /* JBDMAX1_CHID_15 */ "", 53343 /* JBDMAX1_CHID_16 */ "", 53344 /* JBDMAX1_CHID_17 */ "", 53345 /* JBDMAX1_CHID_18 */ "", 53346 /* JBDMAX1_CHID_19 */ "", 53347 /* JBDMAX1_CHID_20 */ "", 53348 /* JBDMAX1_CHID_21 */ "", 53349 /* JBDMAX1_CHID_22 */ "", 53350 /* JBDMAX1_CHID_23 */ "", 53351 /* JBDMAX1_CHID_24 */ "", 53352 /* JBDMAX1_CHID_25 */ "", 53353 /* JBDMAX1_CHID_26 */ "", 53354 /* JBDMAX1_CHID_27 */ "", 53355 /* JBDMAX1_CHID_28 */ "", 53356 /* JBDMAX1_CHID_29 */ "", 53357 /* JBDMAX1_CHID_30 */ "", 53358 /* JBDMAX1_CHID_31 */ "", 53359 /* JBDMAX1_CHID_32 */ "", 53360 /* JBDMAX1_CHID_33 */ "", 53361 /* JBDMAX1_CHID_34 */ "", 53362 /* JBDMAX1_CHID_35 */ "", 53363 /* JBDMAX1_CHID_36 */ "", 53364 /* JBDMAX1_CHID_37 */ "", 53365 /* JBDMAX1_CHID_38 */ "", 53366 /* JBDMAX1_CHID_39 */ "", 53367 /* JBDMAX1_CHID_40 */ "", 53368 /* JBDMAX1_CHID_41 */ "", 53369 /* JBDMAX1_CHID_42 */ "", 53370 /* JBDMAX1_CHID_43 */ "", 53371 /* JBDMAX1_CHID_44 */ "", 53372 /* JBDMAX1_CHID_45 */ "", 53373 /* JBDMAX1_CHID_46 */ "", 53374 /* JBDMAX1_CHID_47 */ "", 53375 /* JBDMAX1_CHID_48 */ "", 53376 /* JBDMAX1_CHID_49 */ "", 53377 /* JBDMAX1_CHID_50 */ "", 53378 /* JBDMAX1_CHID_51 */ "", 53379 /* JBDMAX1_CHID_52 */ "", 53380 /* JBDMAX1_CHID_53 */ "", 53381 /* JBDMAX1_CHID_54 */ "", 53382 /* JBDMAX1_CHID_55 */ "", 53383 /* JBDMAX1_CHID_56 */ "", 53384 /* JBDMAX1_CHID_57 */ "", 53385 /* JBDMAX1_CHID_58 */ "", 53386 /* JBDMAX1_CHID_59 */ "", 53387 /* JBDMAX1_CHID_60 */ "", 53388 /* JBDMAX1_CHID_61 */ "", 53389 /* JBDMAX1_CHID_62 */ "", 53390 /* JBDMAX1_CHID_63 */ "", 53391 /* JBDMAX2_CHID_0 */ "", 53392 /* JBDMAX2_CHID_1 */ "", 53393 /* JBDMAX2_CHID_2 */ "", 53394 /* JBDMAX2_CHID_3 */ "", 53395 /* JBDMAX2_CHID_4 */ "", 53396 /* JBDMAX2_CHID_5 */ "", 53397 /* JBDMAX2_CHID_6 */ "", 53398 /* JBDMAX2_CHID_7 */ "", 53399 /* JBDMAX2_CHID_8 */ "", 53400 /* JBDMAX2_CHID_9 */ "", 53401 /* JBDMAX2_CHID_10 */ "", 53402 /* JBDMAX2_CHID_11 */ "", 53403 /* JBDMAX2_CHID_12 */ "", 53404 /* JBDMAX2_CHID_13 */ "", 53405 /* JBDMAX2_CHID_14 */ "", 53406 /* JBDMAX2_CHID_15 */ "", 53407 /* JBDMAX2_CHID_16 */ "", 53408 /* JBDMAX2_CHID_17 */ "", 53409 /* JBDMAX2_CHID_18 */ "", 53410 /* JBDMAX2_CHID_19 */ "", 53411 /* JBDMAX2_CHID_20 */ "", 53412 /* JBDMAX2_CHID_21 */ "", 53413 /* JBDMAX2_CHID_22 */ "", 53414 /* JBDMAX2_CHID_23 */ "", 53415 /* JBDMAX2_CHID_24 */ "", 53416 /* JBDMAX2_CHID_25 */ "", 53417 /* JBDMAX2_CHID_26 */ "", 53418 /* JBDMAX2_CHID_27 */ "", 53419 /* JBDMAX2_CHID_28 */ "", 53420 /* JBDMAX2_CHID_29 */ "", 53421 /* JBDMAX2_CHID_30 */ "", 53422 /* JBDMAX2_CHID_31 */ "", 53423 /* JBDMAX2_CHID_32 */ "", 53424 /* JBDMAX2_CHID_33 */ "", 53425 /* JBDMAX2_CHID_34 */ "", 53426 /* JBDMAX2_CHID_35 */ "", 53427 /* JBDMAX2_CHID_36 */ "", 53428 /* JBDMAX2_CHID_37 */ "", 53429 /* JBDMAX2_CHID_38 */ "", 53430 /* JBDMAX2_CHID_39 */ "", 53431 /* JBDMAX2_CHID_40 */ "", 53432 /* JBDMAX2_CHID_41 */ "", 53433 /* JBDMAX2_CHID_42 */ "", 53434 /* JBDMAX2_CHID_43 */ "", 53435 /* JBDMAX2_CHID_44 */ "", 53436 /* JBDMAX2_CHID_45 */ "", 53437 /* JBDMAX2_CHID_46 */ "", 53438 /* JBDMAX2_CHID_47 */ "", 53439 /* JBDMAX2_CHID_48 */ "", 53440 /* JBDMAX2_CHID_49 */ "", 53441 /* JBDMAX2_CHID_50 */ "", 53442 /* JBDMAX2_CHID_51 */ "", 53443 /* JBDMAX2_CHID_52 */ "", 53444 /* JBDMAX2_CHID_53 */ "", 53445 /* JBDMAX2_CHID_54 */ "", 53446 /* JBDMAX2_CHID_55 */ "", 53447 /* JBDMAX2_CHID_56 */ "", 53448 /* JBDMAX2_CHID_57 */ "", 53449 /* JBDMAX2_CHID_58 */ "", 53450 /* JBDMAX2_CHID_59 */ "", 53451 /* JBDMAX2_CHID_60 */ "", 53452 /* JBDMAX2_CHID_61 */ "", 53453 /* JBDMAX2_CHID_62 */ "", 53454 /* JBDMAX2_CHID_63 */ "", 53455 /* JBDMIN1_CHID_0 */ "", 53456 /* JBDMIN1_CHID_1 */ "", 53457 /* JBDMIN1_CHID_2 */ "", 53458 /* JBDMIN1_CHID_3 */ "", 53459 /* JBDMIN1_CHID_4 */ "", 53460 /* JBDMIN1_CHID_5 */ "", 53461 /* JBDMIN1_CHID_6 */ "", 53462 /* JBDMIN1_CHID_7 */ "", 53463 /* JBDMIN1_CHID_8 */ "", 53464 /* JBDMIN1_CHID_9 */ "", 53465 /* JBDMIN1_CHID_10 */ "", 53466 /* JBDMIN1_CHID_11 */ "", 53467 /* JBDMIN1_CHID_12 */ "", 53468 /* JBDMIN1_CHID_13 */ "", 53469 /* JBDMIN1_CHID_14 */ "", 53470 /* JBDMIN1_CHID_15 */ "", 53471 /* JBDMIN1_CHID_16 */ "", 53472 /* JBDMIN1_CHID_17 */ "", 53473 /* JBDMIN1_CHID_18 */ "", 53474 /* JBDMIN1_CHID_19 */ "", 53475 /* JBDMIN1_CHID_20 */ "", 53476 /* JBDMIN1_CHID_21 */ "", 53477 /* JBDMIN1_CHID_22 */ "", 53478 /* JBDMIN1_CHID_23 */ "", 53479 /* JBDMIN1_CHID_24 */ "", 53480 /* JBDMIN1_CHID_25 */ "", 53481 /* JBDMIN1_CHID_26 */ "", 53482 /* JBDMIN1_CHID_27 */ "", 53483 /* JBDMIN1_CHID_28 */ "", 53484 /* JBDMIN1_CHID_29 */ "", 53485 /* JBDMIN1_CHID_30 */ "", 53486 /* JBDMIN1_CHID_31 */ "", 53487 /* JBDMIN1_CHID_32 */ "", 53488 /* JBDMIN1_CHID_33 */ "", 53489 /* JBDMIN1_CHID_34 */ "", 53490 /* JBDMIN1_CHID_35 */ "", 53491 /* JBDMIN1_CHID_36 */ "", 53492 /* JBDMIN1_CHID_37 */ "", 53493 /* JBDMIN1_CHID_38 */ "", 53494 /* JBDMIN1_CHID_39 */ "", 53495 /* JBDMIN1_CHID_40 */ "", 53496 /* JBDMIN1_CHID_41 */ "", 53497 /* JBDMIN1_CHID_42 */ "", 53498 /* JBDMIN1_CHID_43 */ "", 53499 /* JBDMIN1_CHID_44 */ "", 53500 /* JBDMIN1_CHID_45 */ "", 53501 /* JBDMIN1_CHID_46 */ "", 53502 /* JBDMIN1_CHID_47 */ "", 53503 /* JBDMIN1_CHID_48 */ "", 53504 /* JBDMIN1_CHID_49 */ "", 53505 /* JBDMIN1_CHID_50 */ "", 53506 /* JBDMIN1_CHID_51 */ "", 53507 /* JBDMIN1_CHID_52 */ "", 53508 /* JBDMIN1_CHID_53 */ "", 53509 /* JBDMIN1_CHID_54 */ "", 53510 /* JBDMIN1_CHID_55 */ "", 53511 /* JBDMIN1_CHID_56 */ "", 53512 /* JBDMIN1_CHID_57 */ "", 53513 /* JBDMIN1_CHID_58 */ "", 53514 /* JBDMIN1_CHID_59 */ "", 53515 /* JBDMIN1_CHID_60 */ "", 53516 /* JBDMIN1_CHID_61 */ "", 53517 /* JBDMIN1_CHID_62 */ "", 53518 /* JBDMIN1_CHID_63 */ "", 53519 /* JBDMIN2_CHID_0 */ "", 53520 /* JBDMIN2_CHID_1 */ "", 53521 /* JBDMIN2_CHID_2 */ "", 53522 /* JBDMIN2_CHID_3 */ "", 53523 /* JBDMIN2_CHID_4 */ "", 53524 /* JBDMIN2_CHID_5 */ "", 53525 /* JBDMIN2_CHID_6 */ "", 53526 /* JBDMIN2_CHID_7 */ "", 53527 /* JBDMIN2_CHID_8 */ "", 53528 /* JBDMIN2_CHID_9 */ "", 53529 /* JBDMIN2_CHID_10 */ "", 53530 /* JBDMIN2_CHID_11 */ "", 53531 /* JBDMIN2_CHID_12 */ "", 53532 /* JBDMIN2_CHID_13 */ "", 53533 /* JBDMIN2_CHID_14 */ "", 53534 /* JBDMIN2_CHID_15 */ "", 53535 /* JBDMIN2_CHID_16 */ "", 53536 /* JBDMIN2_CHID_17 */ "", 53537 /* JBDMIN2_CHID_18 */ "", 53538 /* JBDMIN2_CHID_19 */ "", 53539 /* JBDMIN2_CHID_20 */ "", 53540 /* JBDMIN2_CHID_21 */ "", 53541 /* JBDMIN2_CHID_22 */ "", 53542 /* JBDMIN2_CHID_23 */ "", 53543 /* JBDMIN2_CHID_24 */ "", 53544 /* JBDMIN2_CHID_25 */ "", 53545 /* JBDMIN2_CHID_26 */ "", 53546 /* JBDMIN2_CHID_27 */ "", 53547 /* JBDMIN2_CHID_28 */ "", 53548 /* JBDMIN2_CHID_29 */ "", 53549 /* JBDMIN2_CHID_30 */ "", 53550 /* JBDMIN2_CHID_31 */ "", 53551 /* JBDMIN2_CHID_32 */ "", 53552 /* JBDMIN2_CHID_33 */ "", 53553 /* JBDMIN2_CHID_34 */ "", 53554 /* JBDMIN2_CHID_35 */ "", 53555 /* JBDMIN2_CHID_36 */ "", 53556 /* JBDMIN2_CHID_37 */ "", 53557 /* JBDMIN2_CHID_38 */ "", 53558 /* JBDMIN2_CHID_39 */ "", 53559 /* JBDMIN2_CHID_40 */ "", 53560 /* JBDMIN2_CHID_41 */ "", 53561 /* JBDMIN2_CHID_42 */ "", 53562 /* JBDMIN2_CHID_43 */ "", 53563 /* JBDMIN2_CHID_44 */ "", 53564 /* JBDMIN2_CHID_45 */ "", 53565 /* JBDMIN2_CHID_46 */ "", 53566 /* JBDMIN2_CHID_47 */ "", 53567 /* JBDMIN2_CHID_48 */ "", 53568 /* JBDMIN2_CHID_49 */ "", 53569 /* JBDMIN2_CHID_50 */ "", 53570 /* JBDMIN2_CHID_51 */ "", 53571 /* JBDMIN2_CHID_52 */ "", 53572 /* JBDMIN2_CHID_53 */ "", 53573 /* JBDMIN2_CHID_54 */ "", 53574 /* JBDMIN2_CHID_55 */ "", 53575 /* JBDMIN2_CHID_56 */ "", 53576 /* JBDMIN2_CHID_57 */ "", 53577 /* JBDMIN2_CHID_58 */ "", 53578 /* JBDMIN2_CHID_59 */ "", 53579 /* JBDMIN2_CHID_60 */ "", 53580 /* JBDMIN2_CHID_61 */ "", 53581 /* JBDMIN2_CHID_62 */ "", 53582 /* JBDMIN2_CHID_63 */ "", 53583 /* JBDSUM1_TCID_0 */ "", 53584 /* JBDSUM1_TCID_1 */ "", 53585 /* JBDSUM1_TCID_2 */ "", 53586 /* JBDSUM1_TCID_3 */ "", 53587 /* JBDSUM1_TCID_4 */ "", 53588 /* JBDSUM1_TCID_5 */ "", 53589 /* JBDSUM1_TCID_6 */ "", 53590 /* JBDSUM1_TCID_7 */ "", 53591 /* JBDSUM1_TCID_8 */ "", 53592 /* JBDSUM1_TCID_9 */ "", 53593 /* JBDSUM1_TCID_10 */ "", 53594 /* JBDSUM1_TCID_11 */ "", 53595 /* JBDSUM1_TCID_12 */ "", 53596 /* JBDSUM1_TCID_13 */ "", 53597 /* JBDSUM1_TCID_14 */ "", 53598 /* JBDSUM1_TCID_15 */ "", 53599 /* JBDSUM2_TCID_0 */ "", 53600 /* JBDSUM2_TCID_1 */ "", 53601 /* JBDSUM2_TCID_2 */ "", 53602 /* JBDSUM2_TCID_3 */ "", 53603 /* JBDSUM2_TCID_4 */ "", 53604 /* JBDSUM2_TCID_5 */ "", 53605 /* JBDSUM2_TCID_6 */ "", 53606 /* JBDSUM2_TCID_7 */ "", 53607 /* JBDSUM2_TCID_8 */ "", 53608 /* JBDSUM2_TCID_9 */ "", 53609 /* JBDSUM2_TCID_10 */ "", 53610 /* JBDSUM2_TCID_11 */ "", 53611 /* JBDSUM2_TCID_12 */ "", 53612 /* JBDSUM2_TCID_13 */ "", 53613 /* JBDSUM2_TCID_14 */ "", 53614 /* JBDSUM2_TCID_15 */ "", 53615 /* JBMISSPC_CHID_0 */ "", 53616 /* JBMISSPC_CHID_1 */ "", 53617 /* JBMISSPC_CHID_2 */ "", 53618 /* JBMISSPC_CHID_3 */ "", 53619 /* JBMISSPC_CHID_4 */ "", 53620 /* JBMISSPC_CHID_5 */ "", 53621 /* JBMISSPC_CHID_6 */ "", 53622 /* JBMISSPC_CHID_7 */ "", 53623 /* JBMISSPC_CHID_8 */ "", 53624 /* JBMISSPC_CHID_9 */ "", 53625 /* JBMISSPC_CHID_10 */ "", 53626 /* JBMISSPC_CHID_11 */ "", 53627 /* JBMISSPC_CHID_12 */ "", 53628 /* JBMISSPC_CHID_13 */ "", 53629 /* JBMISSPC_CHID_14 */ "", 53630 /* JBMISSPC_CHID_15 */ "", 53631 /* JBMISSPC_CHID_16 */ "", 53632 /* JBMISSPC_CHID_17 */ "", 53633 /* JBMISSPC_CHID_18 */ "", 53634 /* JBMISSPC_CHID_19 */ "", 53635 /* JBMISSPC_CHID_20 */ "", 53636 /* JBMISSPC_CHID_21 */ "", 53637 /* JBMISSPC_CHID_22 */ "", 53638 /* JBMISSPC_CHID_23 */ "", 53639 /* JBMISSPC_CHID_24 */ "", 53640 /* JBMISSPC_CHID_25 */ "", 53641 /* JBMISSPC_CHID_26 */ "", 53642 /* JBMISSPC_CHID_27 */ "", 53643 /* JBMISSPC_CHID_28 */ "", 53644 /* JBMISSPC_CHID_29 */ "", 53645 /* JBMISSPC_CHID_30 */ "", 53646 /* JBMISSPC_CHID_31 */ "", 53647 /* JBMISSPC_CHID_32 */ "", 53648 /* JBMISSPC_CHID_33 */ "", 53649 /* JBMISSPC_CHID_34 */ "", 53650 /* JBMISSPC_CHID_35 */ "", 53651 /* JBMISSPC_CHID_36 */ "", 53652 /* JBMISSPC_CHID_37 */ "", 53653 /* JBMISSPC_CHID_38 */ "", 53654 /* JBMISSPC_CHID_39 */ "", 53655 /* JBMISSPC_CHID_40 */ "", 53656 /* JBMISSPC_CHID_41 */ "", 53657 /* JBMISSPC_CHID_42 */ "", 53658 /* JBMISSPC_CHID_43 */ "", 53659 /* JBMISSPC_CHID_44 */ "", 53660 /* JBMISSPC_CHID_45 */ "", 53661 /* JBMISSPC_CHID_46 */ "", 53662 /* JBMISSPC_CHID_47 */ "", 53663 /* JBMISSPC_CHID_48 */ "", 53664 /* JBMISSPC_CHID_49 */ "", 53665 /* JBMISSPC_CHID_50 */ "", 53666 /* JBMISSPC_CHID_51 */ "", 53667 /* JBMISSPC_CHID_52 */ "", 53668 /* JBMISSPC_CHID_53 */ "", 53669 /* JBMISSPC_CHID_54 */ "", 53670 /* JBMISSPC_CHID_55 */ "", 53671 /* JBMISSPC_CHID_56 */ "", 53672 /* JBMISSPC_CHID_57 */ "", 53673 /* JBMISSPC_CHID_58 */ "", 53674 /* JBMISSPC_CHID_59 */ "", 53675 /* JBMISSPC_CHID_60 */ "", 53676 /* JBMISSPC_CHID_61 */ "", 53677 /* JBMISSPC_CHID_62 */ "", 53678 /* JBMISSPC_CHID_63 */ "", 53679 /* JBRSTRT_CHID_0 */ "", 53680 /* JBRSTRT_CHID_1 */ "", 53681 /* JBRSTRT_CHID_2 */ "", 53682 /* JBRSTRT_CHID_3 */ "", 53683 /* JBRSTRT_CHID_4 */ "", 53684 /* JBRSTRT_CHID_5 */ "", 53685 /* JBRSTRT_CHID_6 */ "", 53686 /* JBRSTRT_CHID_7 */ "", 53687 /* JBRSTRT_CHID_8 */ "", 53688 /* JBRSTRT_CHID_9 */ "", 53689 /* JBRSTRT_CHID_10 */ "", 53690 /* JBRSTRT_CHID_11 */ "", 53691 /* JBRSTRT_CHID_12 */ "", 53692 /* JBRSTRT_CHID_13 */ "", 53693 /* JBRSTRT_CHID_14 */ "", 53694 /* JBRSTRT_CHID_15 */ "", 53695 /* JBRSTRT_CHID_16 */ "", 53696 /* JBRSTRT_CHID_17 */ "", 53697 /* JBRSTRT_CHID_18 */ "", 53698 /* JBRSTRT_CHID_19 */ "", 53699 /* JBRSTRT_CHID_20 */ "", 53700 /* JBRSTRT_CHID_21 */ "", 53701 /* JBRSTRT_CHID_22 */ "", 53702 /* JBRSTRT_CHID_23 */ "", 53703 /* JBRSTRT_CHID_24 */ "", 53704 /* JBRSTRT_CHID_25 */ "", 53705 /* JBRSTRT_CHID_26 */ "", 53706 /* JBRSTRT_CHID_27 */ "", 53707 /* JBRSTRT_CHID_28 */ "", 53708 /* JBRSTRT_CHID_29 */ "", 53709 /* JBRSTRT_CHID_30 */ "", 53710 /* JBRSTRT_CHID_31 */ "", 53711 /* JBRSTRT_CHID_32 */ "", 53712 /* JBRSTRT_CHID_33 */ "", 53713 /* JBRSTRT_CHID_34 */ "", 53714 /* JBRSTRT_CHID_35 */ "", 53715 /* JBRSTRT_CHID_36 */ "", 53716 /* JBRSTRT_CHID_37 */ "", 53717 /* JBRSTRT_CHID_38 */ "", 53718 /* JBRSTRT_CHID_39 */ "", 53719 /* JBRSTRT_CHID_40 */ "", 53720 /* JBRSTRT_CHID_41 */ "", 53721 /* JBRSTRT_CHID_42 */ "", 53722 /* JBRSTRT_CHID_43 */ "", 53723 /* JBRSTRT_CHID_44 */ "", 53724 /* JBRSTRT_CHID_45 */ "", 53725 /* JBRSTRT_CHID_46 */ "", 53726 /* JBRSTRT_CHID_47 */ "", 53727 /* JBRSTRT_CHID_48 */ "", 53728 /* JBRSTRT_CHID_49 */ "", 53729 /* JBRSTRT_CHID_50 */ "", 53730 /* JBRSTRT_CHID_51 */ "", 53731 /* JBRSTRT_CHID_52 */ "", 53732 /* JBRSTRT_CHID_53 */ "", 53733 /* JBRSTRT_CHID_54 */ "", 53734 /* JBRSTRT_CHID_55 */ "", 53735 /* JBRSTRT_CHID_56 */ "", 53736 /* JBRSTRT_CHID_57 */ "", 53737 /* JBRSTRT_CHID_58 */ "", 53738 /* JBRSTRT_CHID_59 */ "", 53739 /* JBRSTRT_CHID_60 */ "", 53740 /* JBRSTRT_CHID_61 */ "", 53741 /* JBRSTRT_CHID_62 */ "", 53742 /* JBRSTRT_CHID_63 */ "", 53743 /* JBSLPCFG */ "", 53744 /* JBSLPCMD */ "", 53745 /* JBUNDRPC_CHID_0 */ "", 53746 /* JBUNDRPC_CHID_1 */ "", 53747 /* JBUNDRPC_CHID_2 */ "", 53748 /* JBUNDRPC_CHID_3 */ "", 53749 /* JBUNDRPC_CHID_4 */ "", 53750 /* JBUNDRPC_CHID_5 */ "", 53751 /* JBUNDRPC_CHID_6 */ "", 53752 /* JBUNDRPC_CHID_7 */ "", 53753 /* JBUNDRPC_CHID_8 */ "", 53754 /* JBUNDRPC_CHID_9 */ "", 53755 /* JBUNDRPC_CHID_10 */ "", 53756 /* JBUNDRPC_CHID_11 */ "", 53757 /* JBUNDRPC_CHID_12 */ "", 53758 /* JBUNDRPC_CHID_13 */ "", 53759 /* JBUNDRPC_CHID_14 */ "", 53760 /* JBUNDRPC_CHID_15 */ "", 53761 /* JBUNDRPC_CHID_16 */ "", 53762 /* JBUNDRPC_CHID_17 */ "", 53763 /* JBUNDRPC_CHID_18 */ "", 53764 /* JBUNDRPC_CHID_19 */ "", 53765 /* JBUNDRPC_CHID_20 */ "", 53766 /* JBUNDRPC_CHID_21 */ "", 53767 /* JBUNDRPC_CHID_22 */ "", 53768 /* JBUNDRPC_CHID_23 */ "", 53769 /* JBUNDRPC_CHID_24 */ "", 53770 /* JBUNDRPC_CHID_25 */ "", 53771 /* JBUNDRPC_CHID_26 */ "", 53772 /* JBUNDRPC_CHID_27 */ "", 53773 /* JBUNDRPC_CHID_28 */ "", 53774 /* JBUNDRPC_CHID_29 */ "", 53775 /* JBUNDRPC_CHID_30 */ "", 53776 /* JBUNDRPC_CHID_31 */ "", 53777 /* JBUNDRPC_CHID_32 */ "", 53778 /* JBUNDRPC_CHID_33 */ "", 53779 /* JBUNDRPC_CHID_34 */ "", 53780 /* JBUNDRPC_CHID_35 */ "", 53781 /* JBUNDRPC_CHID_36 */ "", 53782 /* JBUNDRPC_CHID_37 */ "", 53783 /* JBUNDRPC_CHID_38 */ "", 53784 /* JBUNDRPC_CHID_39 */ "", 53785 /* JBUNDRPC_CHID_40 */ "", 53786 /* JBUNDRPC_CHID_41 */ "", 53787 /* JBUNDRPC_CHID_42 */ "", 53788 /* JBUNDRPC_CHID_43 */ "", 53789 /* JBUNDRPC_CHID_44 */ "", 53790 /* JBUNDRPC_CHID_45 */ "", 53791 /* JBUNDRPC_CHID_46 */ "", 53792 /* JBUNDRPC_CHID_47 */ "", 53793 /* JBUNDRPC_CHID_48 */ "", 53794 /* JBUNDRPC_CHID_49 */ "", 53795 /* JBUNDRPC_CHID_50 */ "", 53796 /* JBUNDRPC_CHID_51 */ "", 53797 /* JBUNDRPC_CHID_52 */ "", 53798 /* JBUNDRPC_CHID_53 */ "", 53799 /* JBUNDRPC_CHID_54 */ "", 53800 /* JBUNDRPC_CHID_55 */ "", 53801 /* JBUNDRPC_CHID_56 */ "", 53802 /* JBUNDRPC_CHID_57 */ "", 53803 /* JBUNDRPC_CHID_58 */ "", 53804 /* JBUNDRPC_CHID_59 */ "", 53805 /* JBUNDRPC_CHID_60 */ "", 53806 /* JBUNDRPC_CHID_61 */ "", 53807 /* JBUNDRPC_CHID_62 */ "", 53808 /* JBUNDRPC_CHID_63 */ "", 53809 /* JTAG_M0_IDM_IDM_INTERRUPT_STATUS */ "", 53810 /* JTAG_M0_IDM_IDM_RESET_CONTROL */ "", 53811 /* JTAG_M0_IDM_IDM_RESET_STATUS */ "", 53812 /* KAPS_BBS_BB_DEBUG */ "", 53813 /* KAPS_BBS_BB_GLOBAL_CONFIG */ "", 53814 /* KAPS_BBS_BB_INIT_DONE */ "", 53815 /* KAPS_BBS_BRR_BB_DEBUG */ "", 53816 /* KAPS_BBS_ECC_1B_ERR_CNT */ "", 53817 /* KAPS_BBS_ECC_2B_ERR_CNT */ "", 53818 /* KAPS_BBS_ECC_ERR_1B_INITIATE */ "", 53819 /* KAPS_BBS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 53820 /* KAPS_BBS_ECC_ERR_2B_INITIATE */ "", 53821 /* KAPS_BBS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 53822 /* KAPS_BBS_ECC_INTERRUPT_REGISTER */ "", 53823 /* KAPS_BBS_ECC_INTERRUPT_REGISTER_MASK */ "", 53824 /* KAPS_BBS_ECC_INTERRUPT_REGISTER_TEST */ "", 53825 /* KAPS_BBS_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 53826 /* KAPS_BBS_ERROR_INITIATION_DATA */ "", 53827 /* KAPS_BBS_GLOBAL_MEM_OPTIONS */ "", 53828 /* KAPS_BBS_GTIMER_CONFIGURATION */ "", 53829 /* KAPS_BBS_GTIMER_TRIGGER */ "", 53830 /* KAPS_BBS_INDIRECT_COMMAND */ "", 53831 /* KAPS_BBS_INDIRECT_COMMAND_ADDRESS */ "", 53832 /* KAPS_BBS_INDIRECT_COMMAND_DATA_INCREMENT */ "", 53833 /* KAPS_BBS_INDIRECT_COMMAND_RD_DATA */ "", 53834 /* KAPS_BBS_INDIRECT_COMMAND_WIDE_MEM */ "", 53835 /* KAPS_BBS_INDIRECT_COMMAND_WR_DATA */ "", 53836 /* KAPS_BBS_INDIRECT_FORCE_BUBBLE */ "", 53837 /* KAPS_BBS_INDIRECT_WR_MASK */ "", 53838 /* KAPS_BBS_INTERRUPT_MASK_REGISTER */ "", 53839 /* KAPS_BBS_INTERRUPT_REGISTER */ "", 53840 /* KAPS_BBS_INTERRUPT_REGISTER_TEST */ "", 53841 /* KAPS_BBS_KAPS_BB_ERROR_REGISTER */ "", 53842 /* KAPS_BBS_KAPS_BB_ERROR_REGISTER_MASK */ "", 53843 /* KAPS_BBS_KAPS_BB_ERROR_REGISTER_TEST */ "", 53844 /* KAPS_BBS_PARITY_ERR_CNT */ "", 53845 /* KAPS_BBS_PAR_ERR_INITIATE */ "", 53846 /* KAPS_BBS_PAR_ERR_MEM_MASK */ "", 53847 /* KAPS_BBS_RESERVED_MIRROR_ADDR */ "", 53848 /* KAPS_BBS_RESERVED_MTCD */ "", 53849 /* KAPS_BBS_RESERVED_MTCP */ "", 53850 /* KAPS_BBS_RESERVED_PCMI_0 */ "", 53851 /* KAPS_BBS_RESERVED_PCMI_1 */ "", 53852 /* KAPS_BBS_RESERVED_PCMI_2 */ "", 53853 /* KAPS_BBS_RESERVED_PCMI_3 */ "", 53854 /* KAPS_BBS_RESERVED_PCMI_4 */ "", 53855 /* KAPS_BBS_RESERVED_PCMI_0_S */ "", 53856 /* KAPS_BBS_RESERVED_PCMI_0_T */ "", 53857 /* KAPS_BBS_RESERVED_PCMI_1_S */ "", 53858 /* KAPS_BBS_RESERVED_PCMI_1_T */ "", 53859 /* KAPS_BBS_RESERVED_PCMI_2_S */ "", 53860 /* KAPS_BBS_RESERVED_PCMI_2_T */ "", 53861 /* KAPS_BBS_RESERVED_PCMI_3_S */ "", 53862 /* KAPS_BBS_RESERVED_PCMI_3_T */ "", 53863 /* KAPS_BBS_RESERVED_PCMI_4_S */ "", 53864 /* KAPS_BBS_RESERVED_PCMI_4_T */ "", 53865 /* KAPS_BBS_RESERVED_SPARE_0 */ "", 53866 /* KAPS_BBS_RESERVED_SPARE_1 */ "", 53867 /* KAPS_BBS_RESERVED_SPARE_2 */ "", 53868 /* KAPS_BBS_RESERVED_SPARE_3 */ "", 53869 /* KAPS_BBS_SBUS_BROADCAST_ID */ "", 53870 /* KAPS_BBS_SBUS_LAST_IN_CHAIN */ "", 53871 /* KAPS_BB_DEBUG */ "", 53872 /* KAPS_BB_GLOBAL_CONFIG */ "", 53873 /* KAPS_BB_INIT_DONE */ "", 53874 /* KAPS_BB_LAST_SELECTED */ "", 53875 /* KAPS_BRR_BB_DEBUG */ "", 53876 /* KAPS_BRR_DEBUG */ "", 53877 /* KAPS_CONFIG */ "", 53878 /* KAPS_CONFIG_CFIFO */ "", 53879 /* KAPS_CONFIG_CFIFO_THRESH */ "", 53880 /* KAPS_CONFIG_FIFO_MON */ "", 53881 /* KAPS_CONFIG_RFIFO */ "", 53882 /* KAPS_CYCLES_OUT_OF_IDLE_0_CNT */ "", 53883 /* KAPS_CYCLES_OUT_OF_IDLE_1_CNT */ "", 53884 /* KAPS_ECC_1B_ERR_CNT */ "", 53885 /* KAPS_ECC_2B_ERR_CNT */ "", 53886 /* KAPS_ECC_ERR_1B_INITIATE */ "", 53887 /* KAPS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 53888 /* KAPS_ECC_ERR_2B_INITIATE */ "", 53889 /* KAPS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 53890 /* KAPS_ECC_INTERRUPT_REGISTER */ "", 53891 /* KAPS_ECC_INTERRUPT_REGISTER_MASK */ "", 53892 /* KAPS_ECC_INTERRUPT_REGISTER_TEST */ "", 53893 /* KAPS_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 53894 /* KAPS_ERROR_INITIATION_DATA */ "", 53895 /* KAPS_GLOBAL_DEBUG */ "", 53896 /* KAPS_GLOBAL_EVENT */ "", 53897 /* KAPS_GLOBAL_EVENT_MASK */ "", 53898 /* KAPS_GLOBAL_MEM_OPTIONS */ "", 53899 /* KAPS_GTIMER_CONFIGURATION */ "", 53900 /* KAPS_GTIMER_CYCLE */ "", 53901 /* KAPS_GTIMER_TRIGGER */ "", 53902 /* KAPS_HITBIT_COMMANDS_LINE */ "", 53903 /* KAPS_HITBIT_CONTROL */ "", 53904 /* KAPS_HITBIT_REPLYS_LINE */ "", 53905 /* KAPS_HITBIT_STM_LAST_CMD_DEBUG */ "", 53906 /* KAPS_IBC_COMMAND_DATA */ "", 53907 /* KAPS_IBC_COMMAND_WORD */ "", 53908 /* KAPS_IBC_CONFIG */ "", 53909 /* KAPS_IBC_FIFO_CORRECTABLE_STATUS */ "", 53910 /* KAPS_IBC_FIFO_ECC_DEBUG */ "", 53911 /* KAPS_IBC_FIFO_MEM_CONTROL */ "", 53912 /* KAPS_IBC_FIFO_TM_TEST_CTRL */ "", 53913 /* KAPS_IBC_FIFO_UNCORRECTABLE_STATUS */ "", 53914 /* KAPS_IBC_QUEUE_STATUS */ "", 53915 /* KAPS_IBC_RESPONSE_DATA */ "", 53916 /* KAPS_IBC_RESPONSE_WORD */ "", 53917 /* KAPS_INDIRECT_COMMAND */ "", 53918 /* KAPS_INDIRECT_COMMAND_ADDRESS */ "", 53919 /* KAPS_INDIRECT_COMMAND_DATA_INCREMENT */ "", 53920 /* KAPS_INDIRECT_COMMAND_RD_DATA */ "", 53921 /* KAPS_INDIRECT_COMMAND_WIDE_MEM */ "", 53922 /* KAPS_INDIRECT_COMMAND_WR_DATA */ "", 53923 /* KAPS_INDIRECT_FORCE_BUBBLE */ "", 53924 /* KAPS_INDIRECT_WR_MASK */ "", 53925 /* KAPS_INTERRUPT_MASK_REGISTER */ "", 53926 /* KAPS_INTERRUPT_REGISTER */ "", 53927 /* KAPS_INTERRUPT_REGISTER_TEST */ "", 53928 /* KAPS_KAPS_BB_ERROR_REGISTER */ "", 53929 /* KAPS_KAPS_BB_ERROR_REGISTER_MASK */ "", 53930 /* KAPS_KAPS_BB_ERROR_REGISTER_TEST */ "", 53931 /* KAPS_KAPS_ERROR_REGISTER */ "", 53932 /* KAPS_KAPS_ERROR_REGISTER_MASK */ "", 53933 /* KAPS_KAPS_ERROR_REGISTER_TEST */ "", 53934 /* KAPS_KAPS_REVISION */ "", 53935 /* KAPS_MEMORY_A_ERROR */ "", 53936 /* KAPS_MEMORY_A_ERROR_MASK */ "", 53937 /* KAPS_MEMORY_B_ERROR */ "", 53938 /* KAPS_MEMORY_B_ERROR_MASK */ "", 53939 /* KAPS_PARITY_ERR_CNT */ "", 53940 /* KAPS_PAR_ERR_INITIATE */ "", 53941 /* KAPS_PAR_ERR_MEM_MASK */ "", 53942 /* KAPS_PCMI_0 */ "", 53943 /* KAPS_PCMI_1 */ "", 53944 /* KAPS_PCMI_2 */ "", 53945 /* KAPS_PCMI_3 */ "", 53946 /* KAPS_PCMI_4 */ "", 53947 /* KAPS_PCMI_0_S */ "", 53948 /* KAPS_PCMI_0_T */ "", 53949 /* KAPS_PCMI_1_S */ "", 53950 /* KAPS_PCMI_1_T */ "", 53951 /* KAPS_PCMI_2_S */ "", 53952 /* KAPS_PCMI_2_T */ "", 53953 /* KAPS_PCMI_3_S */ "", 53954 /* KAPS_PCMI_3_T */ "", 53955 /* KAPS_PCMI_4_S */ "", 53956 /* KAPS_PCMI_4_T */ "", 53957 /* KAPS_PD_ASSIST_DEBUG */ "", 53958 /* KAPS_READ_DUMP_SINGLE_CMD_CNT */ "", 53959 /* KAPS_REG_0041 */ "", 53960 /* KAPS_REG_0149 */ "", 53961 /* KAPS_REG_00A4 */ "", 53962 /* KAPS_REG_00A6 */ "", 53963 /* KAPS_REG_00C2 */ "", 53964 /* KAPS_REG_014D */ "", 53965 /* KAPS_RESERVED_MIRROR_ADDR */ "", 53966 /* KAPS_RESERVED_MTCD */ "", 53967 /* KAPS_RESERVED_MTCP */ "", 53968 /* KAPS_RESERVED_PCMI_0 */ "", 53969 /* KAPS_RESERVED_PCMI_1 */ "", 53970 /* KAPS_RESERVED_PCMI_2 */ "", 53971 /* KAPS_RESERVED_PCMI_3 */ "", 53972 /* KAPS_RESERVED_PCMI_4 */ "", 53973 /* KAPS_RESERVED_PCMI_0_S */ "", 53974 /* KAPS_RESERVED_PCMI_0_T */ "", 53975 /* KAPS_RESERVED_PCMI_1_S */ "", 53976 /* KAPS_RESERVED_PCMI_1_T */ "", 53977 /* KAPS_RESERVED_PCMI_2_S */ "", 53978 /* KAPS_RESERVED_PCMI_2_T */ "", 53979 /* KAPS_RESERVED_PCMI_3_S */ "", 53980 /* KAPS_RESERVED_PCMI_3_T */ "", 53981 /* KAPS_RESERVED_PCMI_4_S */ "", 53982 /* KAPS_RESERVED_PCMI_4_T */ "", 53983 /* KAPS_RESERVED_SPARE_0 */ "", 53984 /* KAPS_RESERVED_SPARE_1 */ "", 53985 /* KAPS_RESERVED_SPARE_2 */ "", 53986 /* KAPS_RESERVED_SPARE_3 */ "", 53987 /* KAPS_REVISION */ "", 53988 /* KAPS_RPB_CAM_BIST_CONFIG */ "", 53989 /* KAPS_RPB_CAM_BIST_CONTROL */ "", 53990 /* KAPS_RPB_CAM_BIST_DBG_DATA */ "", 53991 /* KAPS_RPB_CAM_BIST_STATUS */ "", 53992 /* KAPS_RPB_DEBUG */ "", 53993 /* KAPS_RPB_GLOBAL_CONFIG */ "", 53994 /* KAPS_RPB_MEM_CONFIG */ "", 53995 /* KAPS_RPB_TCAM_A_SCAN_PAUSE */ "", 53996 /* KAPS_RPB_TCAM_B_SCAN_PAUSE */ "", 53997 /* KAPS_RPB_TCAM_ECC_CONFIG */ "", 53998 /* KAPS_RPB_TCAM_SCAN_CFGS */ "", 53999 /* KAPS_RPB_TCAM_SCAN_DEBUG_0 */ "", 54000 /* KAPS_RPB_TCAM_SCAN_DEBUG_1 */ "", 54001 /* KAPS_RPB_TCAM_SCAN_ERROR */ "", 54002 /* KAPS_RPB_TCAM_SCAN_ERROR_MASK */ "", 54003 /* KAPS_RPB_TCAM_SCAN_INDEX */ "", 54004 /* KAPS_RPB_TCAM_SCAN_STATUS */ "", 54005 /* KAPS_R_5_ATTN */ "", 54006 /* KAPS_R_5_AXI_CONFIG */ "", 54007 /* KAPS_R_5_AXI_ERROR_STATUS_0 */ "", 54008 /* KAPS_R_5_AXI_ERROR_STATUS_1 */ "", 54009 /* KAPS_R_5_CONFIGA */ "", 54010 /* KAPS_R_5_CORE_CONFIGA */ "", 54011 /* KAPS_R_5_CORE_CONFIGB */ "", 54012 /* KAPS_R_5_CORE_CONFIGC */ "", 54013 /* KAPS_R_5_CORE_CONFIGD */ "", 54014 /* KAPS_R_5_CORE_CONFIGE */ "", 54015 /* KAPS_R_5_CORE_CONTROL */ "", 54016 /* KAPS_R_5_CORE_MEM_CONTROL */ "", 54017 /* KAPS_R_5_COUNTERS */ "", 54018 /* KAPS_R_5_DAP_APB_ADDR */ "", 54019 /* KAPS_R_5_DAP_APB_CTRL */ "", 54020 /* KAPS_R_5_DAP_APB_RDATA */ "", 54021 /* KAPS_R_5_DAP_APB_WDATA */ "", 54022 /* KAPS_R_5_DEBUG_CONFIGA */ "", 54023 /* KAPS_R_5_DEBUG_CONFIGB */ "", 54024 /* KAPS_R_5_DEBUG_EBUS_PATTERN_0 */ "", 54025 /* KAPS_R_5_DEBUG_EBUS_PATTERN_1 */ "", 54026 /* KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK */ "", 54027 /* KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK */ "", 54028 /* KAPS_R_5_DEBUG_STATUS */ "", 54029 /* KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0 */ "", 54030 /* KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1 */ "", 54031 /* KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK */ "", 54032 /* KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK */ "", 54033 /* KAPS_R_5_ECC_ERR_RD_TCM_A */ "", 54034 /* KAPS_R_5_ECC_ERR_RD_TCM_B_0 */ "", 54035 /* KAPS_R_5_ECC_ERR_RD_TCM_B_1 */ "", 54036 /* KAPS_R_5_ECC_ERR_WR_TCM_A */ "", 54037 /* KAPS_R_5_ECC_ERR_WR_TCM_B_0 */ "", 54038 /* KAPS_R_5_ECC_ERR_WR_TCM_B_1 */ "", 54039 /* KAPS_R_5_FIFO_MON_EVENT */ "", 54040 /* KAPS_R_5_FIFO_MON_EVENT_MASK */ "", 54041 /* KAPS_R_5_TM_TEST_CTRL */ "", 54042 /* KAPS_SBUS_BROADCAST_ID */ "", 54043 /* KAPS_SBUS_LAST_IN_CHAIN */ "", 54044 /* KAPS_SEARCH_0A_ERROR */ "", 54045 /* KAPS_SEARCH_0A_ERROR_MASK */ "", 54046 /* KAPS_SEARCH_0B_ERROR */ "", 54047 /* KAPS_SEARCH_0B_ERROR_MASK */ "", 54048 /* KAPS_SEARCH_1A_ERROR */ "", 54049 /* KAPS_SEARCH_1A_ERROR_MASK */ "", 54050 /* KAPS_SEARCH_1B_ERROR */ "", 54051 /* KAPS_SEARCH_1B_ERROR_MASK */ "", 54052 /* KAPS_SINGLE_CMD_CNT */ "", 54053 /* KAPS_STATUS_CFIFO */ "", 54054 /* KAPS_STATUS_RFIFO */ "", 54055 /* KNOWN_MCAST_BLOCK_MASK */ "", 54056 /* KNOWN_MCAST_BLOCK_MASK_64 */ "KNOWN_MCAST_BLOCK_MASK", 54057 /* KNOWN_MCAST_BLOCK_MASK_HI */ "KNOWN_MCAST_BLOCK_MASK_HI", 54058 /* KNOWN_MCAST_BLOCK_MASK_LO */ "KNOWN_MCAST_BLOCK_MASK_LO", 54059 /* KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL */ "", 54060 /* KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR */ "", 54061 /* KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK */ "", 54062 /* L0_COSWEIGHTS */ "", 54063 /* L0_WERRCOUNT */ "", 54064 /* L2GRE_CONTROL */ "", 54065 /* L2GRE_DEFAULT_NETWORK_SVP */ "", 54066 /* L2GRE_DEFAULT_SVP */ "", 54067 /* L2L3_PASSTHRU_HIGHWAY_CONTROL */ "", 54068 /* L2MC_DBGCTRL */ "L2MC_CONTROL", 54069 /* L2MC_ECCP_CONTROL */ "", 54070 /* L2MC_PARITY_CONTROL */ "", 54071 /* L2MC_PARITY_STATUS */ "", 54072 /* L2MC_PARITY_STATUS_INTR */ "", 54073 /* L2MC_PARITY_STATUS_NACK */ "", 54074 /* L2_128_OVF_LEARNED_CNT */ "", 54075 /* L2_AGE_DEBUG */ "AGE_DEBUG", 54076 /* L2_AGE_DEBUG_2 */ "AGE_DEBUG_2", 54077 /* L2_AGE_TIMER */ "AGE_TIMER", 54078 /* L2_AUX_HASH_CONTROL */ "", 54079 /* L2_BULK_CONTROL */ "", 54080 /* L2_BULK_ECC_STATUS */ "", 54081 /* L2_BULK_KEY_TYPE_PORT_A */ "", 54082 /* L2_BULK_KEY_TYPE_PORT_B */ "", 54083 /* L2_BULK_MATCH_PORT_A */ "", 54084 /* L2_BULK_MATCH_PORT_B */ "", 54085 /* L2_BULK_MATCH_VLANS_CONTROL */ "", 54086 /* L2_ENDPOINT_ID_DBGCTRL_0 */ "L2_ENDPOINT_ID_CONTROL_0", 54087 /* L2_ENDPOINT_ID_DBGCTRL_1 */ "L2_ENDPOINT_ID_CONTROL_1", 54088 /* L2_ENDPOINT_ID_HASH_CONTROL */ "", 54089 /* L2_ENTRY_ADDR_MASK */ "", 54090 /* L2_ENTRY_COLLISION_CNT */ "", 54091 /* L2_ENTRY_CONTROL */ "", 54092 /* L2_ENTRY_CONTROL_0 */ "", 54093 /* L2_ENTRY_CONTROL_1 */ "", 54094 /* L2_ENTRY_CONTROL_2 */ "", 54095 /* L2_ENTRY_CONTROL_3 */ "", 54096 /* L2_ENTRY_CONTROL_4 */ "", 54097 /* L2_ENTRY_CONTROL_5 */ "", 54098 /* L2_ENTRY_CONTROL_6 */ "", 54099 /* L2_ENTRY_CONTROL_0_PIPE0 */ "", 54100 /* L2_ENTRY_CONTROL_0_PIPE1 */ "", 54101 /* L2_ENTRY_CONTROL_0_PIPE2 */ "", 54102 /* L2_ENTRY_CONTROL_0_PIPE3 */ "", 54103 /* L2_ENTRY_DA_DBGCTRL_0 */ "L2_ENTRY_DA_CONTROL_0", 54104 /* L2_ENTRY_DA_DBGCTRL_1 */ "L2_ENTRY_DA_CONTROL_1", 54105 /* L2_ENTRY_DA_DBGCTRL_2 */ "L2_ENTRY_DA_CONTROL_2", 54106 /* L2_ENTRY_DA_DBGCTRL_3 */ "L2_ENTRY_DA_CONTROL_3", 54107 /* L2_ENTRY_DA_DBGCTRL_4 */ "L2_ENTRY_DA_CONTROL_4", 54108 /* L2_ENTRY_DA_DBGCTRL_5 */ "L2_ENTRY_DA_CONTROL_5", 54109 /* L2_ENTRY_DA_DBGCTRL_6 */ "L2_ENTRY_DA_CONTROL_6", 54110 /* L2_ENTRY_DA_DBGCTRL_7 */ "L2_ENTRY_DA_CONTROL_7", 54111 /* L2_ENTRY_DA_DBGCTRL_8 */ "L2_ENTRY_DA_CONTROL_8", 54112 /* L2_ENTRY_DBGCTRL0 */ "L2_ENTRY_CONTROL0", 54113 /* L2_ENTRY_DBGCTRL1 */ "L2_ENTRY_CONTROL1", 54114 /* L2_ENTRY_DBGCTRL_0 */ "L2_ENTRY_CONTROL_0", 54115 /* L2_ENTRY_DBGCTRL_1 */ "L2_ENTRY_CONTROL_1", 54116 /* L2_ENTRY_DBGCTRL_2 */ "L2_ENTRY_CONTROL_2", 54117 /* L2_ENTRY_DBGCTRL_3 */ "L2_ENTRY_CONTROL_3", 54118 /* L2_ENTRY_DBGCTRL_4 */ "L2_ENTRY_CONTROL_4", 54119 /* L2_ENTRY_DBGCTRL_5 */ "L2_ENTRY_CONTROL_5", 54120 /* L2_ENTRY_DBGCTRL_6 */ "L2_ENTRY_CONTROL_6", 54121 /* L2_ENTRY_DBGCTRL_7 */ "L2_ENTRY_CONTROL_7", 54122 /* L2_ENTRY_ECC_CONTROL */ "", 54123 /* L2_ENTRY_FLEX_COUNTER_STRENGTH */ "", 54124 /* L2_ENTRY_LEARNED_CNT */ "", 54125 /* L2_ENTRY_LP_CONTROL */ "", 54126 /* L2_ENTRY_NO_LEARN_STATUS */ "", 54127 /* L2_ENTRY_OVF_NO_LEARN_STATUS */ "", 54128 /* L2_ENTRY_PARITY_CONTROL */ "", 54129 /* L2_ENTRY_PARITY_STATUS */ "", 54130 /* L2_ENTRY_PARITY_STATUS_0 */ "", 54131 /* L2_ENTRY_PARITY_STATUS_1 */ "", 54132 /* L2_ENTRY_PARITY_STATUS_INTR_0 */ "", 54133 /* L2_ENTRY_PARITY_STATUS_INTR_1 */ "", 54134 /* L2_ENTRY_PARITY_STATUS_NACK_0 */ "", 54135 /* L2_ENTRY_PARITY_STATUS_NACK_1 */ "", 54136 /* L2_ENTRY_SA_DBGCTRL_0 */ "L2_ENTRY_SA_CONTROL_0", 54137 /* L2_ENTRY_SA_DBGCTRL_1 */ "L2_ENTRY_SA_CONTROL_1", 54138 /* L2_ENTRY_SA_DBGCTRL_2 */ "L2_ENTRY_SA_CONTROL_2", 54139 /* L2_ENTRY_SA_DBGCTRL_3 */ "L2_ENTRY_SA_CONTROL_3", 54140 /* L2_ENTRY_SA_DBGCTRL_4 */ "L2_ENTRY_SA_CONTROL_4", 54141 /* L2_ENTRY_SA_DBGCTRL_5 */ "L2_ENTRY_SA_CONTROL_5", 54142 /* L2_ENTRY_SA_DBGCTRL_6 */ "L2_ENTRY_SA_CONTROL_6", 54143 /* L2_ENTRY_SA_DBGCTRL_7 */ "L2_ENTRY_SA_CONTROL_7", 54144 /* L2_ENTRY_SA_DBGCTRL_8 */ "L2_ENTRY_SA_CONTROL_8", 54145 /* L2_HITDA_DBGCTRL */ "L2_HITDA_CONTROL", 54146 /* L2_HITSA_DBGCTRL */ "L2_HITSA_CONTROL", 54147 /* L2_HIT_CONTROL */ "", 54148 /* L2_HIT_DBGCTRL */ "L2_HIT_CONTROL", 54149 /* L2_HIT_DBGCTRL_0 */ "L2_HIT_CONTROL_0", 54150 /* L2_HIT_DBGCTRL_01 */ "L2_HIT_CONTROL_01", 54151 /* L2_HIT_DBGCTRL_1 */ "L2_HIT_CONTROL_1", 54152 /* L2_HIT_DBGCTRL_02 */ "L2_HIT_CONTROL_02", 54153 /* L2_HIT_DBGCTRL_2 */ "L2_HIT_CONTROL_2", 54154 /* L2_HIT_DBGCTRL_3 */ "L2_HIT_CONTROL_3", 54155 /* L2_HIT_DBGCTRL_4 */ "L2_HIT_CONTROL_4", 54156 /* L2_HIT_DBGCTRL_0_PIPE0 */ "L2_HIT_CONTROL_0_PIPE0", 54157 /* L2_HIT_DBGCTRL_0_PIPE1 */ "L2_HIT_CONTROL_0_PIPE1", 54158 /* L2_HIT_DBGCTRL_0_PIPE2 */ "L2_HIT_CONTROL_0_PIPE2", 54159 /* L2_HIT_DBGCTRL_0_PIPE3 */ "L2_HIT_CONTROL_0_PIPE3", 54160 /* L2_ISS_BANK_CONFIG */ "", 54161 /* L2_ISS_LOG_TO_PHY_BANK_MAP */ "", 54162 /* L2_LEARN_CACHE_STATUS */ "", 54163 /* L2_LEARN_CACHE_STATUS_PIPE0 */ "", 54164 /* L2_LEARN_CACHE_STATUS_PIPE1 */ "", 54165 /* L2_LEARN_CACHE_STATUS_PIPE2 */ "", 54166 /* L2_LEARN_CACHE_STATUS_PIPE3 */ "", 54167 /* L2_LEARN_CACHE_STATUS_PIPE4 */ "", 54168 /* L2_LEARN_CACHE_STATUS_PIPE5 */ "", 54169 /* L2_LEARN_CACHE_STATUS_PIPE6 */ "", 54170 /* L2_LEARN_CACHE_STATUS_PIPE7 */ "", 54171 /* L2_LEARN_CONTROL */ "", 54172 /* L2_LEARN_COPY_CACHE_CTRL */ "", 54173 /* L2_LP_CONTROL_0 */ "", 54174 /* L2_LP_CONTROL_1 */ "", 54175 /* L2_LP_CONTROL_2 */ "", 54176 /* L2_LP_CONTROL_0_PIPE0 */ "", 54177 /* L2_LP_CONTROL_0_PIPE1 */ "", 54178 /* L2_LP_CONTROL_0_PIPE2 */ "", 54179 /* L2_LP_CONTROL_0_PIPE3 */ "", 54180 /* L2_MGMT_CONTROL */ "", 54181 /* L2_MGMT_HW_RESET_CONTROL_0 */ "", 54182 /* L2_MGMT_HW_RESET_CONTROL_1 */ "", 54183 /* L2_MGMT_INTR */ "", 54184 /* L2_MGMT_INTR_MASK */ "", 54185 /* L2_MGMT_SER_FIFO_CTRL */ "", 54186 /* L2_MOD_FIFO_CLAIM_AVAIL */ "", 54187 /* L2_MOD_FIFO_CNT */ "", 54188 /* L2_MOD_FIFO_DBGCTRL */ "L2_MOD_FIFO_CONTROL", 54189 /* L2_MOD_FIFO_ENABLE */ "", 54190 /* L2_MOD_FIFO_MEMORY_CONTROL_0 */ "", 54191 /* L2_MOD_FIFO_PARITY_CONTROL */ "", 54192 /* L2_MOD_FIFO_PARITY_STATUS_INTR */ "", 54193 /* L2_MOD_FIFO_PARITY_STATUS_NACK */ "", 54194 /* L2_MOD_FIFO_RD_PTR */ "", 54195 /* L2_MOD_FIFO_WR_PTR */ "", 54196 /* L2_NON_LEARNED_MESSAGE_MACSA */ "", 54197 /* L2_NON_LEARNED_MESSAGE_VLAN_PORT */ "", 54198 /* L2_PYLD_INIT_SHIFT_AMOUNT */ "", 54199 /* L2_TABLE_HASH_CONTROL */ "", 54200 /* L2_USER_ENTRY_CAM_BIST_CONFIG */ "", 54201 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64 */ "", 54202 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE0 */ "", 54203 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE1 */ "", 54204 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE2 */ "", 54205 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE3 */ "", 54206 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE4 */ "", 54207 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE5 */ "", 54208 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE6 */ "", 54209 /* L2_USER_ENTRY_CAM_BIST_CONFIG_64_PIPE7 */ "", 54210 /* L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE0 */ "", 54211 /* L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE1 */ "", 54212 /* L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE2 */ "", 54213 /* L2_USER_ENTRY_CAM_BIST_CONFIG_PIPE3 */ "", 54214 /* L2_USER_ENTRY_CAM_BIST_CONTROL */ "", 54215 /* L2_USER_ENTRY_CAM_BIST_DBGCTRL */ "L2_USER_ENTRY_CAM_BIST_CONTROL", 54216 /* L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE0 */ "L2_USER_ENTRY_CAM_BIST_CONTROL_PIPE0", 54217 /* L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE1 */ "L2_USER_ENTRY_CAM_BIST_CONTROL_PIPE1", 54218 /* L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE2 */ "L2_USER_ENTRY_CAM_BIST_CONTROL_PIPE2", 54219 /* L2_USER_ENTRY_CAM_BIST_DBGCTRL_PIPE3 */ "L2_USER_ENTRY_CAM_BIST_CONTROL_PIPE3", 54220 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA */ "", 54221 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE0 */ "", 54222 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE1 */ "", 54223 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE2 */ "", 54224 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE3 */ "", 54225 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE4 */ "", 54226 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE5 */ "", 54227 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE6 */ "", 54228 /* L2_USER_ENTRY_CAM_BIST_DBG_DATA_PIPE7 */ "", 54229 /* L2_USER_ENTRY_CAM_BIST_S10_STATUS */ "", 54230 /* L2_USER_ENTRY_CAM_BIST_S2_STATUS */ "", 54231 /* L2_USER_ENTRY_CAM_BIST_S3_STATUS */ "", 54232 /* L2_USER_ENTRY_CAM_BIST_S5_STATUS */ "", 54233 /* L2_USER_ENTRY_CAM_BIST_S6_STATUS */ "", 54234 /* L2_USER_ENTRY_CAM_BIST_S8_STATUS */ "", 54235 /* L2_USER_ENTRY_CAM_BIST_STATUS */ "", 54236 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE0 */ "", 54237 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE1 */ "", 54238 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE2 */ "", 54239 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE3 */ "", 54240 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE4 */ "", 54241 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE5 */ "", 54242 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE6 */ "", 54243 /* L2_USER_ENTRY_CAM_BIST_STATUS_PIPE7 */ "", 54244 /* L2_USER_ENTRY_CAM_CONTROL */ "", 54245 /* L2_USER_ENTRY_CAM_DBGCTRL */ "L2_USER_ENTRY_CAM_CONTROL", 54246 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE0 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE0", 54247 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE1 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE1", 54248 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE2 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE2", 54249 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE3 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE3", 54250 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE4 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE4", 54251 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE5 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE5", 54252 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE6 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE6", 54253 /* L2_USER_ENTRY_CAM_DBGCTRL_PIPE7 */ "L2_USER_ENTRY_CAM_CONTROL_PIPE7", 54254 /* L2_USER_ENTRY_CAM_SERCTRL */ "L2_USER_ENTRY_CAM_SER_CONTROL", 54255 /* L2_USER_ENTRY_DATA_DBGCTRL */ "L2_USER_ENTRY_DATA_CONTROL", 54256 /* L2_USER_ENTRY_DATA_DBGCTRL_PIPE0 */ "L2_USER_ENTRY_DATA_CONTROL_PIPE0", 54257 /* L2_USER_ENTRY_DATA_DBGCTRL_PIPE1 */ "L2_USER_ENTRY_DATA_CONTROL_PIPE1", 54258 /* L2_USER_ENTRY_DATA_DBGCTRL_PIPE2 */ "L2_USER_ENTRY_DATA_CONTROL_PIPE2", 54259 /* L2_USER_ENTRY_DATA_DBGCTRL_PIPE3 */ "L2_USER_ENTRY_DATA_CONTROL_PIPE3", 54260 /* L2_USER_ENTRY_DATA_ONLY_PARITY_CONTROL */ "", 54261 /* L2_USER_ENTRY_DATA_ONLY_PARITY_STATUS */ "", 54262 /* L2_USER_ENTRY_DATA_PARITY_CONTROL */ "", 54263 /* L2_USER_ENTRY_DATA_PARITY_STATUS_INTR */ "", 54264 /* L2_USER_ENTRY_DATA_PARITY_STATUS_NACK */ "", 54265 /* L2_USER_ENTRY_DBGCTRL */ "L2_USER_ENTRY_CONTROL", 54266 /* L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64 */ "", 54267 /* L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE0 */ "", 54268 /* L2_USER_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE1 */ "", 54269 /* L2_USER_ENTRY_ONLY_CAM_BIST_STATUS */ "", 54270 /* L2_USER_ENTRY_ONLY_CAM_BIST_STATUS_PIPE0 */ "", 54271 /* L2_USER_ENTRY_ONLY_CAM_BIST_STATUS_PIPE1 */ "", 54272 /* L3MC_DBGCTRL */ "L3MC_CONTROL", 54273 /* L3MC_PARITY_CONTROL */ "L3MC_PARITY_CONTROL", 54274 /* L3MC_PARITY_STATUS */ "L3MC_PARITY_STATUS", 54275 /* L3_AUX_HASH_CONTROL */ "", 54276 /* L3_DEFIP_128_CAM_BIST_CONFIG */ "", 54277 /* L3_DEFIP_128_CAM_BIST_CONTROL */ "", 54278 /* L3_DEFIP_128_CAM_BIST_DBG_DATA */ "", 54279 /* L3_DEFIP_128_CAM_BIST_STATUS */ "", 54280 /* L3_DEFIP_128_CAM_DBGCTRL */ "L3_DEFIP_128_CAM_CONTROL", 54281 /* L3_DEFIP_128_CAM_DBGCTRL0 */ "L3_DEFIP_128_CAM_CONTROL0", 54282 /* L3_DEFIP_128_CAM_ENABLE */ "", 54283 /* L3_DEFIP_128_DATA_DBGCTRL */ "L3_DEFIP_128_DATA_CONTROL", 54284 /* L3_DEFIP_128_DATA_PARITY_CONTROL */ "", 54285 /* L3_DEFIP_128_DATA_PARITY_STATUS_INTR */ "", 54286 /* L3_DEFIP_128_DATA_PARITY_STATUS_NACK */ "", 54287 /* L3_DEFIP_ALPM_CFG */ "", 54288 /* L3_DEFIP_AUX_CTRL */ "", 54289 /* L3_DEFIP_AUX_CTRL_1 */ "", 54290 /* L3_DEFIP_AUX_RAM_CTRL_0 */ "", 54291 /* L3_DEFIP_AUX_RAM_CTRL_1 */ "", 54292 /* L3_DEFIP_AUX_RAM_CTRL_0_32 */ "L3_DEFIP_AUX_RAM_CTRL_0", 54293 /* L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE0 */ "L3_DEFIP_AUX_RAM_CTRL_0_PIPE0", 54294 /* L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE1 */ "L3_DEFIP_AUX_RAM_CTRL_0_PIPE1", 54295 /* L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE2 */ "L3_DEFIP_AUX_RAM_CTRL_0_PIPE2", 54296 /* L3_DEFIP_AUX_RAM_CTRL_0_32_PIPE3 */ "L3_DEFIP_AUX_RAM_CTRL_0_PIPE3", 54297 /* L3_DEFIP_CAM_BIST_CONFIG */ "", 54298 /* L3_DEFIP_CAM_BIST_CONFIG_64 */ "", 54299 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE0 */ "", 54300 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE1 */ "", 54301 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE2 */ "", 54302 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE3 */ "", 54303 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE4 */ "", 54304 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE5 */ "", 54305 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE6 */ "", 54306 /* L3_DEFIP_CAM_BIST_CONFIG_64_PIPE7 */ "", 54307 /* L3_DEFIP_CAM_BIST_CONFIG_PIPE0 */ "", 54308 /* L3_DEFIP_CAM_BIST_CONFIG_PIPE1 */ "", 54309 /* L3_DEFIP_CAM_BIST_CONFIG_PIPE2 */ "", 54310 /* L3_DEFIP_CAM_BIST_CONFIG_PIPE3 */ "", 54311 /* L3_DEFIP_CAM_BIST_CONTROL */ "", 54312 /* L3_DEFIP_CAM_BIST_DBGCTRL */ "L3_DEFIP_CAM_BIST_CONTROL", 54313 /* L3_DEFIP_CAM_BIST_DBGCTRL_0 */ "L3_DEFIP_CAM_BIST_CONTROL_0", 54314 /* L3_DEFIP_CAM_BIST_DBGCTRL_1 */ "L3_DEFIP_CAM_BIST_CONTROL_1", 54315 /* L3_DEFIP_CAM_BIST_DBGCTRL_PIPE0 */ "L3_DEFIP_CAM_BIST_CONTROL_PIPE0", 54316 /* L3_DEFIP_CAM_BIST_DBGCTRL_PIPE1 */ "L3_DEFIP_CAM_BIST_CONTROL_PIPE1", 54317 /* L3_DEFIP_CAM_BIST_DBGCTRL_PIPE2 */ "L3_DEFIP_CAM_BIST_CONTROL_PIPE2", 54318 /* L3_DEFIP_CAM_BIST_DBGCTRL_PIPE3 */ "L3_DEFIP_CAM_BIST_CONTROL_PIPE3", 54319 /* L3_DEFIP_CAM_BIST_DBG_DATA */ "", 54320 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE0 */ "", 54321 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE1 */ "", 54322 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE2 */ "", 54323 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE3 */ "", 54324 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE4 */ "", 54325 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE5 */ "", 54326 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE6 */ "", 54327 /* L3_DEFIP_CAM_BIST_DBG_DATA_PIPE7 */ "", 54328 /* L3_DEFIP_CAM_BIST_S10_STATUS */ "", 54329 /* L3_DEFIP_CAM_BIST_S12_STATUS */ "", 54330 /* L3_DEFIP_CAM_BIST_S2_STATUS */ "", 54331 /* L3_DEFIP_CAM_BIST_S3_STATUS */ "", 54332 /* L3_DEFIP_CAM_BIST_S5_STATUS */ "", 54333 /* L3_DEFIP_CAM_BIST_S6_STATUS */ "", 54334 /* L3_DEFIP_CAM_BIST_S8_STATUS */ "", 54335 /* L3_DEFIP_CAM_BIST_STATUS */ "", 54336 /* L3_DEFIP_CAM_BIST_STATUS_PIPE0 */ "", 54337 /* L3_DEFIP_CAM_BIST_STATUS_PIPE1 */ "", 54338 /* L3_DEFIP_CAM_BIST_STATUS_PIPE2 */ "", 54339 /* L3_DEFIP_CAM_BIST_STATUS_PIPE3 */ "", 54340 /* L3_DEFIP_CAM_BIST_STATUS_PIPE4 */ "", 54341 /* L3_DEFIP_CAM_BIST_STATUS_PIPE5 */ "", 54342 /* L3_DEFIP_CAM_BIST_STATUS_PIPE6 */ "", 54343 /* L3_DEFIP_CAM_BIST_STATUS_PIPE7 */ "", 54344 /* L3_DEFIP_CAM_CONTROL0 */ "", 54345 /* L3_DEFIP_CAM_CONTROL1 */ "", 54346 /* L3_DEFIP_CAM_CONTROL2 */ "", 54347 /* L3_DEFIP_CAM_DBGCTRL0 */ "L3_DEFIP_CAM_CONTROL0", 54348 /* L3_DEFIP_CAM_DBGCTRL01 */ "L3_DEFIP_CAM_CONTROL01", 54349 /* L3_DEFIP_CAM_DBGCTRL1 */ "L3_DEFIP_CAM_CONTROL1", 54350 /* L3_DEFIP_CAM_DBGCTRL02 */ "L3_DEFIP_CAM_CONTROL02", 54351 /* L3_DEFIP_CAM_DBGCTRL2 */ "L3_DEFIP_CAM_CONTROL2", 54352 /* L3_DEFIP_CAM_DBGCTRL03 */ "L3_DEFIP_CAM_CONTROL03", 54353 /* L3_DEFIP_CAM_DBGCTRL3 */ "L3_DEFIP_CAM_CONTROL3", 54354 /* L3_DEFIP_CAM_DBGCTRL4 */ "L3_DEFIP_CAM_CONTROL4", 54355 /* L3_DEFIP_CAM_DBGCTRL5 */ "L3_DEFIP_CAM_CONTROL5", 54356 /* L3_DEFIP_CAM_DBGCTRL6 */ "L3_DEFIP_CAM_CONTROL6", 54357 /* L3_DEFIP_CAM_DBGCTRL7 */ "L3_DEFIP_CAM_CONTROL7", 54358 /* L3_DEFIP_CAM_DBGCTRL11 */ "L3_DEFIP_CAM_CONTROL11", 54359 /* L3_DEFIP_CAM_DBGCTRL12 */ "L3_DEFIP_CAM_CONTROL12", 54360 /* L3_DEFIP_CAM_DBGCTRL13 */ "L3_DEFIP_CAM_CONTROL13", 54361 /* L3_DEFIP_CAM_DBGCTRL21 */ "L3_DEFIP_CAM_CONTROL21", 54362 /* L3_DEFIP_CAM_DBGCTRL22 */ "L3_DEFIP_CAM_CONTROL22", 54363 /* L3_DEFIP_CAM_DBGCTRL23 */ "L3_DEFIP_CAM_CONTROL23", 54364 /* L3_DEFIP_CAM_DBGCTRL31 */ "L3_DEFIP_CAM_CONTROL31", 54365 /* L3_DEFIP_CAM_DBGCTRL32 */ "L3_DEFIP_CAM_CONTROL32", 54366 /* L3_DEFIP_CAM_DBGCTRL33 */ "L3_DEFIP_CAM_CONTROL33", 54367 /* L3_DEFIP_CAM_DBGCTRL41 */ "L3_DEFIP_CAM_CONTROL41", 54368 /* L3_DEFIP_CAM_DBGCTRL42 */ "L3_DEFIP_CAM_CONTROL42", 54369 /* L3_DEFIP_CAM_DBGCTRL43 */ "L3_DEFIP_CAM_CONTROL43", 54370 /* L3_DEFIP_CAM_DBGCTRL51 */ "L3_DEFIP_CAM_CONTROL51", 54371 /* L3_DEFIP_CAM_DBGCTRL52 */ "L3_DEFIP_CAM_CONTROL52", 54372 /* L3_DEFIP_CAM_DBGCTRL53 */ "L3_DEFIP_CAM_CONTROL53", 54373 /* L3_DEFIP_CAM_DBGCTRL0_64 */ "L3_DEFIP_CAM_CONTROL0", 54374 /* L3_DEFIP_CAM_DBGCTRL0_PIPE0 */ "L3_DEFIP_CAM_CONTROL0_PIPE0", 54375 /* L3_DEFIP_CAM_DBGCTRL0_PIPE1 */ "L3_DEFIP_CAM_CONTROL0_PIPE1", 54376 /* L3_DEFIP_CAM_DBGCTRL0_PIPE2 */ "L3_DEFIP_CAM_CONTROL0_PIPE2", 54377 /* L3_DEFIP_CAM_DBGCTRL0_PIPE3 */ "L3_DEFIP_CAM_CONTROL0_PIPE3", 54378 /* L3_DEFIP_CAM_DBGCTRL2_PIPE0 */ "L3_DEFIP_CAM_CONTROL2_PIPE0", 54379 /* L3_DEFIP_CAM_DBGCTRL2_PIPE1 */ "L3_DEFIP_CAM_CONTROL2_PIPE1", 54380 /* L3_DEFIP_CAM_DBGCTRL2_PIPE2 */ "L3_DEFIP_CAM_CONTROL2_PIPE2", 54381 /* L3_DEFIP_CAM_DBGCTRL2_PIPE3 */ "L3_DEFIP_CAM_CONTROL2_PIPE3", 54382 /* L3_DEFIP_CAM_DBGCTRL3_PIPE0 */ "L3_DEFIP_CAM_CONTROL3_PIPE0", 54383 /* L3_DEFIP_CAM_DBGCTRL3_PIPE1 */ "L3_DEFIP_CAM_CONTROL3_PIPE1", 54384 /* L3_DEFIP_CAM_DBGCTRL3_PIPE2 */ "L3_DEFIP_CAM_CONTROL3_PIPE2", 54385 /* L3_DEFIP_CAM_DBGCTRL3_PIPE3 */ "L3_DEFIP_CAM_CONTROL3_PIPE3", 54386 /* L3_DEFIP_CAM_DBGCTRL4_PIPE0 */ "L3_DEFIP_CAM_CONTROL4_PIPE0", 54387 /* L3_DEFIP_CAM_DBGCTRL4_PIPE1 */ "L3_DEFIP_CAM_CONTROL4_PIPE1", 54388 /* L3_DEFIP_CAM_DBGCTRL4_PIPE2 */ "L3_DEFIP_CAM_CONTROL4_PIPE2", 54389 /* L3_DEFIP_CAM_DBGCTRL4_PIPE3 */ "L3_DEFIP_CAM_CONTROL4_PIPE3", 54390 /* L3_DEFIP_CAM_DBGCTRL5_PIPE0 */ "L3_DEFIP_CAM_CONTROL5_PIPE0", 54391 /* L3_DEFIP_CAM_DBGCTRL5_PIPE1 */ "L3_DEFIP_CAM_CONTROL5_PIPE1", 54392 /* L3_DEFIP_CAM_DBGCTRL5_PIPE2 */ "L3_DEFIP_CAM_CONTROL5_PIPE2", 54393 /* L3_DEFIP_CAM_DBGCTRL5_PIPE3 */ "L3_DEFIP_CAM_CONTROL5_PIPE3", 54394 /* L3_DEFIP_CAM_DEBUG_DATA_0 */ "", 54395 /* L3_DEFIP_CAM_DEBUG_DATA_1 */ "", 54396 /* L3_DEFIP_CAM_DEBUG_DATA_2 */ "", 54397 /* L3_DEFIP_CAM_DEBUG_SEND */ "", 54398 /* L3_DEFIP_CAM_ENABLE */ "", 54399 /* L3_DEFIP_DATA_DBGCTRL */ "L3_DEFIP_DATA_CONTROL", 54400 /* L3_DEFIP_DATA_DBGCTRL_0 */ "L3_DEFIP_DATA_CONTROL_0", 54401 /* L3_DEFIP_DATA_DBGCTRL_1 */ "L3_DEFIP_DATA_CONTROL_1", 54402 /* L3_DEFIP_DATA_DBGCTRL_2 */ "L3_DEFIP_DATA_CONTROL_2", 54403 /* L3_DEFIP_DATA_DBGCTRL_3 */ "L3_DEFIP_DATA_CONTROL_3", 54404 /* L3_DEFIP_DATA_DBGCTRL_4 */ "L3_DEFIP_DATA_CONTROL_4", 54405 /* L3_DEFIP_DATA_DBGCTRL_5 */ "L3_DEFIP_DATA_CONTROL_5", 54406 /* L3_DEFIP_DATA_DBGCTRL_0_PIPE0 */ "L3_DEFIP_DATA_CONTROL_0_PIPE0", 54407 /* L3_DEFIP_DATA_DBGCTRL_0_PIPE1 */ "L3_DEFIP_DATA_CONTROL_0_PIPE1", 54408 /* L3_DEFIP_DATA_DBGCTRL_0_PIPE2 */ "L3_DEFIP_DATA_CONTROL_0_PIPE2", 54409 /* L3_DEFIP_DATA_DBGCTRL_0_PIPE3 */ "L3_DEFIP_DATA_CONTROL_0_PIPE3", 54410 /* L3_DEFIP_DATA_ECC_CONTROL */ "", 54411 /* L3_DEFIP_DATA_ECC_STATUS_INTR */ "", 54412 /* L3_DEFIP_DATA_ECC_STATUS_NACK */ "", 54413 /* L3_DEFIP_DATA_PARITY_CONTROL */ "", 54414 /* L3_DEFIP_DATA_PARITY_STATUS_INTR */ "", 54415 /* L3_DEFIP_DATA_PARITY_STATUS_NACK */ "", 54416 /* L3_DEFIP_DATA_PDA_CONTROL_0 */ "", 54417 /* L3_DEFIP_DATA_PDA_CONTROL_1 */ "", 54418 /* L3_DEFIP_DATA_PDA_CONTROL_2 */ "", 54419 /* L3_DEFIP_DATA_PDA_CONTROL_3 */ "", 54420 /* L3_DEFIP_KEY_SEL */ "", 54421 /* L3_DEFIP_KEY_SEL_0 */ "", 54422 /* L3_DEFIP_KEY_SEL_1 */ "", 54423 /* L3_DEFIP_ONLY_CAM_BIST_CONFIG_64 */ "", 54424 /* L3_DEFIP_ONLY_CAM_BIST_CONFIG_64_PIPE0 */ "", 54425 /* L3_DEFIP_ONLY_CAM_BIST_CONFIG_64_PIPE1 */ "", 54426 /* L3_DEFIP_ONLY_CAM_BIST_STATUS */ "", 54427 /* L3_DEFIP_ONLY_CAM_BIST_STATUS_PIPE0 */ "", 54428 /* L3_DEFIP_ONLY_CAM_BIST_STATUS_PIPE1 */ "", 54429 /* L3_DEFIP_PARITY_CONTROL */ "", 54430 /* L3_DEFIP_PARITY_STATUS */ "", 54431 /* L3_DEFIP_RPF_CONTROL */ "", 54432 /* L3_ECMP_DBGCTRL */ "L3_ECMP_CONTROL", 54433 /* L3_ECMP_GROUP_ECCP_CONTROL */ "L3_ECMP_GROUP_ECCP_CONTROL", 54434 /* L3_ECMP_GROUP_PARITY_CONTROL */ "L3_ECMP_GROUP_PARITY_CONTROL", 54435 /* L3_ECMP_GROUP_PARITY_STATUS */ "", 54436 /* L3_ECMP_GROUP_PARITY_STATUS_INTR */ "L3_ECMP_GROUP_PARITY_STATUS_INTR", 54437 /* L3_ECMP_GROUP_PARITY_STATUS_NACK */ "L3_ECMP_GROUP_PARITY_STATUS_NACK", 54438 /* L3_ECMP_PARITY_CONTROL */ "L3_ECMP_PARITY_CONTROL", 54439 /* L3_ECMP_PARITY_STATUS */ "", 54440 /* L3_ECMP_PARITY_STATUS_INTR */ "L3_ECMP_PARITY_STATUS_INTR", 54441 /* L3_ECMP_PARITY_STATUS_NACK */ "L3_ECMP_PARITY_STATUS_NACK", 54442 /* L3_ENTRY_ADDR_MASK */ "", 54443 /* L3_ENTRY_CONTROL */ "", 54444 /* L3_ENTRY_CONTROL_0 */ "", 54445 /* L3_ENTRY_CONTROL_1 */ "", 54446 /* L3_ENTRY_CONTROL_2 */ "", 54447 /* L3_ENTRY_CONTROL_3 */ "", 54448 /* L3_ENTRY_CONTROL_4 */ "", 54449 /* L3_ENTRY_CONTROL_5 */ "", 54450 /* L3_ENTRY_CONTROL_6 */ "", 54451 /* L3_ENTRY_CONTROL_7 */ "", 54452 /* L3_ENTRY_CONTROL_8 */ "", 54453 /* L3_ENTRY_CONTROL_9 */ "", 54454 /* L3_ENTRY_CONTROL_10 */ "", 54455 /* L3_ENTRY_CONTROL_0_PIPE0 */ "", 54456 /* L3_ENTRY_CONTROL_0_PIPE1 */ "", 54457 /* L3_ENTRY_CONTROL_0_PIPE2 */ "", 54458 /* L3_ENTRY_CONTROL_0_PIPE3 */ "", 54459 /* L3_ENTRY_CONTROL_1_PIPE0 */ "", 54460 /* L3_ENTRY_CONTROL_1_PIPE1 */ "", 54461 /* L3_ENTRY_CONTROL_1_PIPE2 */ "", 54462 /* L3_ENTRY_CONTROL_1_PIPE3 */ "", 54463 /* L3_ENTRY_DBGCTRL0 */ "L3_ENTRY_CONTROL0", 54464 /* L3_ENTRY_DBGCTRL00 */ "L3_ENTRY_CONTROL_00", 54465 /* L3_ENTRY_DBGCTRL01 */ "L3_ENTRY_CONTROL_01", 54466 /* L3_ENTRY_DBGCTRL1 */ "L3_ENTRY_CONTROL1", 54467 /* L3_ENTRY_DBGCTRL2 */ "L3_ENTRY_CONTROL_2", 54468 /* L3_ENTRY_DBGCTRL3 */ "L3_ENTRY_CONTROL_3", 54469 /* L3_ENTRY_DBGCTRL4 */ "L3_ENTRY_CONTROL_4", 54470 /* L3_ENTRY_DBGCTRL5 */ "L3_ENTRY_CONTROL_5", 54471 /* L3_ENTRY_DBGCTRL6 */ "L3_ENTRY_CONTROL_6", 54472 /* L3_ENTRY_DBGCTRL10 */ "L3_ENTRY_CONTROL_10", 54473 /* L3_ENTRY_DBGCTRL11 */ "L3_ENTRY_CONTROL_11", 54474 /* L3_ENTRY_DBGCTRL20 */ "L3_ENTRY_CONTROL_20", 54475 /* L3_ENTRY_DBGCTRL21 */ "L3_ENTRY_CONTROL_21", 54476 /* L3_ENTRY_DBGCTRL30 */ "L3_ENTRY_CONTROL_30", 54477 /* L3_ENTRY_DBGCTRL31 */ "L3_ENTRY_CONTROL_31", 54478 /* L3_ENTRY_DBGCTRL40 */ "L3_ENTRY_CONTROL_40", 54479 /* L3_ENTRY_DBGCTRL41 */ "L3_ENTRY_CONTROL_41", 54480 /* L3_ENTRY_DBGCTRL50 */ "L3_ENTRY_CONTROL_50", 54481 /* L3_ENTRY_DBGCTRL51 */ "L3_ENTRY_CONTROL_51", 54482 /* L3_ENTRY_DBGCTRL60 */ "L3_ENTRY_CONTROL_60", 54483 /* L3_ENTRY_DBGCTRL61 */ "L3_ENTRY_CONTROL_61", 54484 /* L3_ENTRY_DBGCTRL70 */ "L3_ENTRY_CONTROL_70", 54485 /* L3_ENTRY_DBGCTRL71 */ "L3_ENTRY_CONTROL_71", 54486 /* L3_ENTRY_ECC_CONTROL */ "", 54487 /* L3_ENTRY_ECC_STATUS_INTR_0 */ "", 54488 /* L3_ENTRY_ECC_STATUS_INTR_1 */ "", 54489 /* L3_ENTRY_ECC_STATUS_NACK_0 */ "", 54490 /* L3_ENTRY_ECC_STATUS_NACK_1 */ "", 54491 /* L3_ENTRY_LP_CONTROL */ "", 54492 /* L3_ENTRY_PARITY_CONTROL */ "", 54493 /* L3_ENTRY_PARITY_STATUS */ "", 54494 /* L3_ENTRY_PARITY_STATUS_0 */ "", 54495 /* L3_ENTRY_PARITY_STATUS_1 */ "", 54496 /* L3_ENTRY_PARITY_STATUS_INTR_0 */ "", 54497 /* L3_ENTRY_PARITY_STATUS_INTR_1 */ "", 54498 /* L3_ENTRY_PARITY_STATUS_NACK_0 */ "", 54499 /* L3_ENTRY_PARITY_STATUS_NACK_1 */ "", 54500 /* L3_HIT_DEBUG */ "", 54501 /* L3_IIF_DBGCTRL */ "L3_IIF_CONTROL", 54502 /* L3_IIF_ECC_CONTROL */ "", 54503 /* L3_IIF_PARITY_CONTROL */ "", 54504 /* L3_IIF_PARITY_STATUS */ "", 54505 /* L3_IIF_PARITY_STATUS_INTR */ "", 54506 /* L3_IIF_PARITY_STATUS_NACK */ "", 54507 /* L3_IIF_PDA_CONTROL */ "", 54508 /* L3_IPMC_1_ECCP_CONTROL */ "", 54509 /* L3_IPMC_1_PARITY_CONTROL */ "", 54510 /* L3_IPMC_1_PARITY_STATUS */ "", 54511 /* L3_IPMC_1_PARITY_STATUS_INTR */ "", 54512 /* L3_IPMC_1_PARITY_STATUS_NACK */ "", 54513 /* L3_IPMC_2_PARITY_CONTROL */ "L3_IPMC_2_PARITY_CONTROL", 54514 /* L3_IPMC_2_PARITY_STATUS_INTR */ "L3_IPMC_2_PARITY_STATUS_INTR", 54515 /* L3_IPMC_2_PARITY_STATUS_NACK */ "L3_IPMC_2_PARITY_STATUS_NACK", 54516 /* L3_IPMC_ECCP_CONTROL */ "L3_IPMC_ECCP_CONTROL", 54517 /* L3_IPMC_PARITY_CONTROL */ "L3MC_PARITY_CONTROL", 54518 /* L3_IPMC_PARITY_STATUS */ "L3MC_PARITY_STATUS", 54519 /* L3_IPMC_PARITY_STATUS_INTR */ "L3_IPMC_PARITY_STATUS_INTR", 54520 /* L3_IPMC_PARITY_STATUS_NACK */ "L3_IPMC_PARITY_STATUS_NACK", 54521 /* L3_IPMC_REMAP_PARITY_CONTROL */ "L3_IPMC_REMAP_PARITY_CONTROL", 54522 /* L3_IPMC_REMAP_PARITY_STATUS_INTR */ "L3_IPMC_REMAP_PARITY_STATUS_INTR", 54523 /* L3_IPMC_REMAP_PARITY_STATUS_NACK */ "L3_IPMC_REMAP_PARITY_STATUS_NACK", 54524 /* L3_ISS_BANK_CONFIG */ "", 54525 /* L3_ISS_LOG_TO_PHY_BANK_MAP */ "", 54526 /* L3_LP_CONTROL_0 */ "", 54527 /* L3_LP_CONTROL_1 */ "", 54528 /* L3_LP_CONTROL_2 */ "", 54529 /* L3_LP_CONTROL_3 */ "", 54530 /* L3_LP_CONTROL_4 */ "", 54531 /* L3_LP_CONTROL_0_PIPE0 */ "", 54532 /* L3_LP_CONTROL_0_PIPE1 */ "", 54533 /* L3_LP_CONTROL_0_PIPE2 */ "", 54534 /* L3_LP_CONTROL_0_PIPE3 */ "", 54535 /* L3_LP_CONTROL_1_PIPE0 */ "", 54536 /* L3_LP_CONTROL_1_PIPE1 */ "", 54537 /* L3_LP_CONTROL_1_PIPE2 */ "", 54538 /* L3_LP_CONTROL_1_PIPE3 */ "", 54539 /* L3_MTU_VALUES_ECC_CONTROL */ "", 54540 /* L3_MTU_VALUES_PARITY_CONTROL */ "", 54541 /* L3_MTU_VALUES_PARITY_STATUS */ "", 54542 /* L3_MTU_VALUES_PARITY_STATUS_INTR */ "", 54543 /* L3_MTU_VALUES_PARITY_STATUS_NACK */ "", 54544 /* L3_TABLE_HASH_CONTROL */ "", 54545 /* L3_TUNNEL_BIST_CONFIG_64 */ "", 54546 /* L3_TUNNEL_BIST_CONFIG_64_PIPE0 */ "", 54547 /* L3_TUNNEL_BIST_CONFIG_64_PIPE1 */ "", 54548 /* L3_TUNNEL_BIST_STATUS */ "", 54549 /* L3_TUNNEL_BIST_STATUS_PIPE0 */ "", 54550 /* L3_TUNNEL_BIST_STATUS_PIPE1 */ "", 54551 /* L3_TUNNEL_CAM_BIST_CONFIG */ "", 54552 /* L3_TUNNEL_CAM_BIST_CONFIG_64 */ "", 54553 /* L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE0 */ "", 54554 /* L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE1 */ "", 54555 /* L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE2 */ "", 54556 /* L3_TUNNEL_CAM_BIST_CONFIG_64_PIPE3 */ "", 54557 /* L3_TUNNEL_CAM_BIST_CONFIG_PIPE0 */ "", 54558 /* L3_TUNNEL_CAM_BIST_CONFIG_PIPE1 */ "", 54559 /* L3_TUNNEL_CAM_BIST_CONFIG_PIPE2 */ "", 54560 /* L3_TUNNEL_CAM_BIST_CONFIG_PIPE3 */ "", 54561 /* L3_TUNNEL_CAM_BIST_DBG_DATA */ "", 54562 /* L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE0 */ "", 54563 /* L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE1 */ "", 54564 /* L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE2 */ "", 54565 /* L3_TUNNEL_CAM_BIST_DBG_DATA_PIPE3 */ "", 54566 /* L3_TUNNEL_CAM_BIST_S10_STATUS */ "", 54567 /* L3_TUNNEL_CAM_BIST_S2_STATUS */ "", 54568 /* L3_TUNNEL_CAM_BIST_S3_STATUS */ "", 54569 /* L3_TUNNEL_CAM_BIST_S5_STATUS */ "", 54570 /* L3_TUNNEL_CAM_BIST_S6_STATUS */ "", 54571 /* L3_TUNNEL_CAM_BIST_S8_STATUS */ "", 54572 /* L3_TUNNEL_CAM_BIST_STATUS */ "", 54573 /* L3_TUNNEL_CAM_BIST_STATUS_PIPE0 */ "", 54574 /* L3_TUNNEL_CAM_BIST_STATUS_PIPE1 */ "", 54575 /* L3_TUNNEL_CAM_BIST_STATUS_PIPE2 */ "", 54576 /* L3_TUNNEL_CAM_BIST_STATUS_PIPE3 */ "", 54577 /* L3_TUNNEL_CAM_CONTROL */ "", 54578 /* L3_TUNNEL_CAM_DBGCTRL */ "L3_TUNNEL_CAM_CONTROL", 54579 /* L3_TUNNEL_CAM_DBGCTRL_64 */ "L3_TUNNEL_CAM_CONTROL", 54580 /* L3_TUNNEL_CAM_DBGCTRL_64_PIPE0 */ "L3_TUNNEL_CAM_CONTROL_PIPE0", 54581 /* L3_TUNNEL_CAM_DBGCTRL_64_PIPE1 */ "L3_TUNNEL_CAM_CONTROL_PIPE1", 54582 /* L3_TUNNEL_CAM_DBGCTRL_64_PIPE2 */ "L3_TUNNEL_CAM_CONTROL_PIPE2", 54583 /* L3_TUNNEL_CAM_DBGCTRL_64_PIPE3 */ "L3_TUNNEL_CAM_CONTROL_PIPE3", 54584 /* L3_TUNNEL_CAM_SER_CONTROL */ "", 54585 /* L3_TUNNEL_DATA_ONLY_PARITY_CONTROL */ "", 54586 /* L3_TUNNEL_DATA_ONLY_PARITY_STATUS */ "", 54587 /* L3_TUNNEL_KEY_SEL */ "", 54588 /* L3_TUNNEL_PARITY_CONTROL */ "", 54589 /* L3_TUNNEL_PARITY_STATUS_INTR */ "", 54590 /* L3_TUNNEL_PARITY_STATUS_NACK */ "", 54591 /* L4_DST_PORT_MAP */ "", 54592 /* L4_DST_PORT_MAP_PIPE0 */ "", 54593 /* L4_DST_PORT_MAP_PIPE1 */ "", 54594 /* L4_DST_PORT_MAP_PIPE2 */ "", 54595 /* L4_DST_PORT_MAP_PIPE3 */ "", 54596 /* L4_SRC_PORT_MAP */ "", 54597 /* L4_SRC_PORT_MAP_PIPE0 */ "", 54598 /* L4_SRC_PORT_MAP_PIPE1 */ "", 54599 /* L4_SRC_PORT_MAP_PIPE2 */ "", 54600 /* L4_SRC_PORT_MAP_PIPE3 */ "", 54601 /* LAG_FAILOVER_CONFIG */ "", 54602 /* LAG_FAILOVER_RATE_LIMITER */ "", 54603 /* LAG_FAILOVER_STATUS */ "", 54604 /* LARGE_SCALE_NAT_CONTROL */ "", 54605 /* LCM_ADMIT_DENY_DFL_FULL_CNT */ "", 54606 /* LCM_ADMIT_DROP_CNT */ "", 54607 /* LCM_ADMIT_DROP_CPU_CNT */ "", 54608 /* LCM_ADMIT_DROP_REASONS_DCH */ "", 54609 /* LCM_AUTO_DOC_NAME_0 */ "", 54610 /* LCM_AUTO_DOC_NAME_1 */ "", 54611 /* LCM_AUTO_DOC_NAME_2 */ "", 54612 /* LCM_AUTO_DOC_NAME_3 */ "", 54613 /* LCM_AUTO_DOC_NAME_4 */ "", 54614 /* LCM_AUTO_DOC_NAME_5 */ "", 54615 /* LCM_AUTO_DOC_NAME_6 */ "", 54616 /* LCM_AUTO_DOC_NAME_7 */ "", 54617 /* LCM_DCML_SEPARATION_REGISTER */ "", 54618 /* LCM_DFL_BANKS_MC_DROP_TH */ "", 54619 /* LCM_DFL_BANKS_TH */ "", 54620 /* LCM_DFL_FC_TH_METHOD_1 */ "", 54621 /* LCM_DFL_FC_TH_METHOD_2 */ "", 54622 /* LCM_DFL_GCI_COPIES_THRESHOLDS */ "", 54623 /* LCM_DFL_GCI_TH_METHOD_1 */ "", 54624 /* LCM_DFL_GCI_TH_METHOD_2 */ "", 54625 /* LCM_DFL_MC_COPIES_ADMIT_THRESHOLDS */ "", 54626 /* LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_1 */ "", 54627 /* LCM_DFL_PIPE_CLASS_SHARED_ADMIT_TH_METHOD_2 */ "", 54628 /* LCM_DFL_PIPE_COPIES_FRAG_CNT_INFO_P */ "", 54629 /* LCM_DFL_PIPE_MC_FRAG_CNT_INFO_P */ "", 54630 /* LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_DIFF_P */ "", 54631 /* LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_1_P */ "", 54632 /* LCM_DFL_PIPE_SHARED_FRAG_CNT_MAX_METHOD_2_P */ "", 54633 /* LCM_DFL_PIPE_SHARED_FRAG_CNT_REF */ "", 54634 /* LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_1_P */ "", 54635 /* LCM_DFL_PIPE_SHARED_FRAG_CNT_STAT_METHOD_2_P */ "", 54636 /* LCM_DFL_RCI_TH_METHOD_1 */ "", 54637 /* LCM_DFL_RCI_TH_METHOD_2 */ "", 54638 /* LCM_DISABLE_MAC */ "", 54639 /* LCM_DTL_ADMIT_LR_TH_PROFILE */ "", 54640 /* LCM_DTL_ADMIT_NLR_TH_PROFILE */ "", 54641 /* LCM_DTL_CPU_CELL_CNT */ "", 54642 /* LCM_DTL_CPU_TAGS_TH */ "", 54643 /* LCM_DTL_CPU_TAG_FIFO_STATUS */ "", 54644 /* LCM_DTL_DROPPED_IP_PR_P_0_CNT */ "", 54645 /* LCM_DTL_DROPPED_IP_PR_P_1_CNT */ "", 54646 /* LCM_DTL_DROPPED_IP_PR_P_2_CNT */ "", 54647 /* LCM_DTL_DROPPED_SRC_P_CNT */ "", 54648 /* LCM_DTL_FC_TH_LR_PROFILE */ "", 54649 /* LCM_DTL_FC_TH_NLR_PROFILE */ "", 54650 /* LCM_DTL_FIFOS_DEPTH_TYPE */ "", 54651 /* LCM_DTL_FRAG_MAX_LEVEL_LR_P */ "", 54652 /* LCM_DTL_FRAG_MAX_LEVEL_NLR_P */ "", 54653 /* LCM_DTL_GCI_TH_P_0_LR_PROFILE */ "", 54654 /* LCM_DTL_GCI_TH_P_0_NLR_PROFILE */ "", 54655 /* LCM_DTL_GCI_TH_P_1_LR_PROFILE */ "", 54656 /* LCM_DTL_GCI_TH_P_1_NLR_PROFILE */ "", 54657 /* LCM_DTL_GCI_TH_P_2_LR_PROFILE */ "", 54658 /* LCM_DTL_GCI_TH_P_2_NLR_PROFILE */ "", 54659 /* LCM_DTL_LCLRT_CPU_CELL_CNT */ "", 54660 /* LCM_DTL_LCLRT_DROPPED_IP_PR_P_0_CNT */ "", 54661 /* LCM_DTL_LCLRT_DROPPED_IP_PR_P_1_CNT */ "", 54662 /* LCM_DTL_LCLRT_DROPPED_IP_PR_P_2_CNT */ "", 54663 /* LCM_DTL_LCLRT_DROPPED_SRC_P_CNT */ "", 54664 /* LCM_DTL_LCLRT_LINK_TYPE */ "", 54665 /* LCM_DTL_LCLRT_TOTAL_IN_CELL_P_CNT */ "", 54666 /* LCM_DTL_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 54667 /* LCM_DTL_LINK_TYPE */ "", 54668 /* LCM_DTL_PIPES_WEIGHTS_REGISTER */ "", 54669 /* LCM_DTL_RCI_TH_P_0_LR_PROFILE */ "", 54670 /* LCM_DTL_RCI_TH_P_0_NLR_PROFILE */ "", 54671 /* LCM_DTL_RCI_TH_P_1_LR_PROFILE */ "", 54672 /* LCM_DTL_RCI_TH_P_1_NLR_PROFILE */ "", 54673 /* LCM_DTL_RCI_TH_P_2_LR_PROFILE */ "", 54674 /* LCM_DTL_RCI_TH_P_2_NLR_PROFILE */ "", 54675 /* LCM_DTL_TH_PROFILES_MAPPING */ "", 54676 /* LCM_DTL_TOTAL_IN_CELL_P_CNT */ "", 54677 /* LCM_DTL_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 54678 /* LCM_DTMLOP_PIPES_WEIGHTS_COUNTER_PN */ "", 54679 /* LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_2 */ "", 54680 /* LCM_DTMLOP_PIPES_WEIGHTS_REGISTER_3 */ "", 54681 /* LCM_DTML_ENABLERS */ "", 54682 /* LCM_DTM_ADMIT_CYCLE_TH_PROFILE */ "", 54683 /* LCM_DTM_ADMIT_JOB_FIFO_CYCLE_TH */ "", 54684 /* LCM_DTM_ADMIT_TH_PROFILE */ "", 54685 /* LCM_DTM_CNT_INFO_1 */ "", 54686 /* LCM_DTM_CNT_INFO_2 */ "", 54687 /* LCM_DTM_CNT_INFO_3 */ "", 54688 /* LCM_DTM_CNT_INFO_SELECT */ "", 54689 /* LCM_DTM_COPIES_RTP_FC_THRESHOLDS */ "", 54690 /* LCM_DTM_CPU_TAGS_STATUS */ "", 54691 /* LCM_DTM_CPU_TAGS_TH */ "", 54692 /* LCM_DTM_DTL_FLOW_CONTROL_CNT_P */ "", 54693 /* LCM_DTM_DYN_PIPES_WEIGHTS_REGISTER */ "", 54694 /* LCM_DTM_FC_TH_PROFILE */ "", 54695 /* LCM_DTM_FIFOS_DEPTH_TYPE */ "", 54696 /* LCM_DTM_FIFO_TYPE_BMP */ "", 54697 /* LCM_DTM_FRAG_CNT_INFO_P_0_DCH */ "", 54698 /* LCM_DTM_FRAG_CNT_INFO_P_1_DCH */ "", 54699 /* LCM_DTM_FRAG_CNT_INFO_P_2_DCH */ "", 54700 /* LCM_DTM_GCI_TH_PROFILE */ "", 54701 /* LCM_DTM_LATENCY_CFG */ "", 54702 /* LCM_DTM_LCLRT_DTL_FLOW_CONTROL_CNT_P */ "", 54703 /* LCM_DTM_LCLRT_PIPES_WEIGHTS_COUNTER_PN */ "", 54704 /* LCM_DTM_LCLRT_TOTAL_OUT_CELL_CNT_P */ "", 54705 /* LCM_DTM_LCLRT_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 54706 /* LCM_DTM_MASK_FC_AGING_PERIOD */ "", 54707 /* LCM_DTM_PIPES_WEIGHTS_COUNTER_PN */ "", 54708 /* LCM_DTM_PIPES_WEIGHTS_REGISTER */ "", 54709 /* LCM_DTM_PIPES_WEIGHTS_REGISTER_2 */ "", 54710 /* LCM_DTM_PIPES_WEIGHTS_REGISTER_3 */ "", 54711 /* LCM_DTM_RCI_TH_PROFILE */ "", 54712 /* LCM_DTM_TAG_CNT_INFO_P_0_DCH */ "", 54713 /* LCM_DTM_TAG_CNT_INFO_P_1_DCH */ "", 54714 /* LCM_DTM_TAG_CNT_INFO_P_2_DCH */ "", 54715 /* LCM_DTM_TOTAL_CELL_CNT_DCH_P_0 */ "", 54716 /* LCM_DTM_TOTAL_CELL_CNT_DCH_P_1 */ "", 54717 /* LCM_DTM_TOTAL_CELL_CNT_DCH_P_2 */ "", 54718 /* LCM_DTM_TOTAL_OUT_CELL_CNT_P */ "", 54719 /* LCM_DTM_WFQ_DYN_WEIGHT_THD_REGISTER */ "", 54720 /* LCM_DYN_PIPES_WEIGHTS_REGISTER */ "", 54721 /* LCM_ECC_1B_ERR_CNT */ "", 54722 /* LCM_ECC_2B_ERR_CNT */ "", 54723 /* LCM_ECC_ERR_1B_INITIATE */ "", 54724 /* LCM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 54725 /* LCM_ECC_ERR_2B_INITIATE */ "", 54726 /* LCM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 54727 /* LCM_ECC_INTERRUPT_REGISTER */ "", 54728 /* LCM_ECC_INTERRUPT_REGISTER_MASK */ "", 54729 /* LCM_ECC_INTERRUPT_REGISTER_TEST */ "", 54730 /* LCM_ERROR_INITIATION_DATA */ "", 54731 /* LCM_FAP_GLOBAL_GENERAL_CFG_1 */ "", 54732 /* LCM_FE_GLOBAL_DCH_CAPTURE_CELLS_DCML */ "", 54733 /* LCM_FE_GLOBAL_GENERAL_CFG_1 */ "", 54734 /* LCM_GLOBAL_MEM_OPTIONS */ "", 54735 /* LCM_GTIMER_CONFIGURATION */ "", 54736 /* LCM_GTIMER_CYCLE */ "", 54737 /* LCM_INTERRUPT_MASK_REGISTER */ "", 54738 /* LCM_INTERRUPT_REGISTER */ "", 54739 /* LCM_INTERRUPT_REGISTER_TEST */ "", 54740 /* LCM_LCLRT_FIFOS_DEPTH_TYPE */ "", 54741 /* LCM_LCM_ADMIT_ENABLERS */ "", 54742 /* LCM_LCM_FC_ENABLERS */ "", 54743 /* LCM_LCM_GCI_ENABLERS */ "", 54744 /* LCM_LCM_INTERRUPT_REGISTER */ "", 54745 /* LCM_LCM_INTERRUPT_REGISTER_MASK */ "", 54746 /* LCM_LCM_INTERRUPT_REGISTER_TEST */ "", 54747 /* LCM_LCM_RCI_ENABLERS */ "", 54748 /* LCM_LCM_REGISTER_0 */ "", 54749 /* LCM_LCM_REGISTER_1 */ "", 54750 /* LCM_LCM_REGISTER_2 */ "", 54751 /* LCM_LCM_REGISTER_3 */ "", 54752 /* LCM_LCM_REGISTER_5 */ "", 54753 /* LCM_LCM_REGISTER_6 */ "", 54754 /* LCM_LCM_REGISTER_7 */ "", 54755 /* LCM_LCM_REGISTER_8 */ "", 54756 /* LCM_LCM_REGISTER_9 */ "", 54757 /* LCM_LINK_CNT_INFO_1 */ "", 54758 /* LCM_LINK_CNT_INFO_2 */ "", 54759 /* LCM_LINK_CNT_INFO_3 */ "", 54760 /* LCM_LINK_CNT_INFO_4 */ "", 54761 /* LCM_LINK_CNT_INFO_5 */ "", 54762 /* LCM_LINK_CNT_INFO_6 */ "", 54763 /* LCM_LINK_CNT_INFO_7 */ "", 54764 /* LCM_LINK_CNT_INFO_SELECT */ "", 54765 /* LCM_LINK_FC_TH_PROFILE */ "", 54766 /* LCM_LINK_LEVEL_FLOW_CONTROL_P */ "", 54767 /* LCM_LINK_LOAD_COUNT_CFG */ "", 54768 /* LCM_LINK_LOAD_HYST_TH */ "", 54769 /* LCM_LINK_LOAD_HYST_TYPE */ "", 54770 /* LCM_LINK_RCI_GRNT_TH_PROFILE */ "", 54771 /* LCM_LINK_RCI_TOTAL_TH_PROFILE */ "", 54772 /* LCM_LINK_TH_PROFILE */ "", 54773 /* LCM_LINK_TH_PROFILES_MAPPING */ "", 54774 /* LCM_LLFC_RATE_CNT_P */ "", 54775 /* LCM_PIPES_MAPPING_EN */ "", 54776 /* LCM_PIPES_SEPARATION_REGISTER */ "", 54777 /* LCM_RCI_TABLE_PIPE */ "", 54778 /* LCM_READ_MECH_DEBUG_1 */ "", 54779 /* LCM_REMOTE_PRI_PIPE_IDX */ "", 54780 /* LCM_REMOTE_SEC_PIPE_IDX */ "", 54781 /* LCM_RESERVED_MIRROR_ADDR */ "", 54782 /* LCM_RESERVED_MTCD */ "", 54783 /* LCM_RESERVED_MTCP */ "", 54784 /* LCM_RESERVED_SPARE_0 */ "", 54785 /* LCM_RESERVED_SPARE_1 */ "", 54786 /* LCM_RESERVED_SPARE_2 */ "", 54787 /* LCM_RESERVED_SPARE_3 */ "", 54788 /* LCM_SBUS_BROADCAST_ID */ "", 54789 /* LCM_SBUS_LAST_IN_CHAIN */ "", 54790 /* LCM_THREE_PIPES_BMP */ "", 54791 /* LCM_TWO_PIPES_BMP */ "", 54792 /* LCM_TX_CPU_CELL_OUTPUT_LINK */ "", 54793 /* LCM_TX_CPU_CELL_TRG */ "", 54794 /* LEARN_CONTROL */ "", 54795 /* LEARN_FIFO_ECC_CONTROL */ "", 54796 /* LINK_LIST_DEBUG_TM */ "", 54797 /* LINK_MEM_MEM_DEBUG */ "", 54798 /* LINK_STATUS */ "", 54799 /* LINK_STATUS_64 */ "LINK_STATUS", 54800 /* LINK_STATUS_DEBOUNCE_TIMEOUT_0 */ "", 54801 /* LINK_STATUS_DEBOUNCE_TIMEOUT_1 */ "", 54802 /* LINK_STATUS_DEBOUNCE_TIMEOUT_2 */ "", 54803 /* LINK_STATUS_DEBOUNCE_TIMEOUT_3 */ "", 54804 /* LINK_STATUS_DEBOUNCE_TIMEOUT_4 */ "", 54805 /* LINK_STATUS_DEBOUNCE_TIMEOUT_5 */ "", 54806 /* LINK_STATUS_DEBOUNCE_TIMEOUT_6 */ "", 54807 /* LINK_STATUS_DEBOUNCE_TIMEOUT_7 */ "", 54808 /* LINK_STATUS_DEBOUNCE_TIMEOUT_8 */ "", 54809 /* LINK_STATUS_DEBOUNCE_TIMEOUT_9 */ "", 54810 /* LINK_STATUS_DEBOUNCE_TIMEOUT_10 */ "", 54811 /* LINK_STATUS_DEBOUNCE_TIMEOUT_11 */ "", 54812 /* LINK_STATUS_DEBOUNCE_TIMEOUT_12 */ "", 54813 /* LINK_STATUS_DEBOUNCE_TIMEOUT_13 */ "", 54814 /* LINK_STATUS_DEBOUNCE_TIMEOUT_14 */ "", 54815 /* LINK_STATUS_DEBOUNCE_TIMEOUT_15 */ "", 54816 /* LINK_STATUS_DEBOUNCE_TIMEOUT_16 */ "", 54817 /* LINK_STATUS_DEBOUNCE_TIMEOUT_17 */ "", 54818 /* LINK_STATUS_DEBOUNCE_TIMEOUT_18 */ "", 54819 /* LINK_STATUS_DEBOUNCE_TIMEOUT_19 */ "", 54820 /* LINK_STATUS_DEBOUNCE_TIMEOUT_20 */ "", 54821 /* LINK_STATUS_DEBOUNCE_TIMEOUT_21 */ "", 54822 /* LINK_STATUS_DEBOUNCE_TIMEOUT_22 */ "", 54823 /* LINK_STATUS_DEBOUNCE_TIMEOUT_23 */ "", 54824 /* LINK_STATUS_GLITCH_DETECT */ "", 54825 /* LINK_STATUS_HI */ "LINK_STATUS_HI", 54826 /* LINK_STATUS_LO */ "LINK_STATUS_LO", 54827 /* LINK_STATUS_TIMER */ "", 54828 /* LLS_ACTIVATION_EVENT_SEEN */ "", 54829 /* LLS_ACT_ECC_DEBUG */ "", 54830 /* LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_32_37 */ "", 54831 /* LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_38_43 */ "", 54832 /* LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_44_49 */ "", 54833 /* LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_50_55 */ "", 54834 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_15_8 */ "", 54835 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_23_16 */ "", 54836 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_31_24 */ "", 54837 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_39_32 */ "", 54838 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_47_40 */ "", 54839 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_55_48 */ "", 54840 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_63_56 */ "", 54841 /* LLS_ASF_CREDIT_THRESHOLD_FOR_PORTS_7_0 */ "", 54842 /* LLS_AXP_PORT_56_CFG_WEIGHT */ "", 54843 /* LLS_AXP_PORT_57_CFG_WEIGHT */ "", 54844 /* LLS_AXP_PORT_58_CFG_WEIGHT */ "", 54845 /* LLS_AXP_PORT_61_CFG_WEIGHT */ "", 54846 /* LLS_AXP_PORT_62_CFG_WEIGHT */ "", 54847 /* LLS_CAPT_ENQUEUE_VIOL_ID */ "", 54848 /* LLS_CAPT_LIST_HEAD_MISMATCH_ID */ "", 54849 /* LLS_CAPT_MAX_SHAPER_BUCKET_L0_OVERFLOW_ID */ "", 54850 /* LLS_CAPT_MAX_SHAPER_BUCKET_L0_UNDERFLOW_ID */ "", 54851 /* LLS_CAPT_MAX_SHAPER_BUCKET_L1_OVERFLOW_ID */ "", 54852 /* LLS_CAPT_MAX_SHAPER_BUCKET_L1_UNDERFLOW_ID */ "", 54853 /* LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID */ "", 54854 /* LLS_CAPT_MAX_SHAPER_BUCKET_L2_LOWER_UNDERFLOW_ID */ "", 54855 /* LLS_CAPT_MAX_SHAPER_BUCKET_L2_OVERFLOW_ID */ "", 54856 /* LLS_CAPT_MAX_SHAPER_BUCKET_L2_UNDERFLOW_ID */ "", 54857 /* LLS_CAPT_MAX_SHAPER_BUCKET_L2_UPPER_OVERFLOW_ID */ "", 54858 /* LLS_CAPT_MAX_SHAPER_BUCKET_L2_UPPER_UNDERFLOW_ID */ "", 54859 /* LLS_CAPT_MAX_SHAPER_BUCKET_PORT_OVERFLOW_ID */ "", 54860 /* LLS_CAPT_MAX_SHAPER_BUCKET_PORT_UNDERFLOW_ID */ "", 54861 /* LLS_CAPT_MAX_SHAPER_BUCKET_S0_OVERFLOW_ID */ "", 54862 /* LLS_CAPT_MAX_SHAPER_BUCKET_S0_UNDERFLOW_ID */ "", 54863 /* LLS_CAPT_MAX_SHAPER_BUCKET_S1_OVERFLOW_ID */ "", 54864 /* LLS_CAPT_MAX_SHAPER_BUCKET_S1_UNDERFLOW_ID */ "", 54865 /* LLS_CAPT_MIN_SHAPER_BUCKET_L0_OVERFLOW_ID */ "", 54866 /* LLS_CAPT_MIN_SHAPER_BUCKET_L0_UNDERFLOW_ID */ "", 54867 /* LLS_CAPT_MIN_SHAPER_BUCKET_L1_OVERFLOW_ID */ "", 54868 /* LLS_CAPT_MIN_SHAPER_BUCKET_L1_UNDERFLOW_ID */ "", 54869 /* LLS_CAPT_MIN_SHAPER_BUCKET_L2_LOWER_OVERFLOW_ID */ "", 54870 /* LLS_CAPT_MIN_SHAPER_BUCKET_L2_LOWER_UNDERFLOW_ID */ "", 54871 /* LLS_CAPT_MIN_SHAPER_BUCKET_L2_OVERFLOW_ID */ "", 54872 /* LLS_CAPT_MIN_SHAPER_BUCKET_L2_UNDERFLOW_ID */ "", 54873 /* LLS_CAPT_MIN_SHAPER_BUCKET_L2_UPPER_OVERFLOW_ID */ "", 54874 /* LLS_CAPT_MIN_SHAPER_BUCKET_L2_UPPER_UNDERFLOW_ID */ "", 54875 /* LLS_CAPT_PORT_1_IN_4_VIOL_ID */ "", 54876 /* LLS_CAPT_PORT_L2_COUNT_OVERFLOW_ID */ "", 54877 /* LLS_CAPT_PORT_L2_COUNT_UNDERRUN_ID */ "", 54878 /* LLS_CAPT_UPD2_L0_ERROR_MIN_OVERFLOW_ID */ "", 54879 /* LLS_CAPT_UPD2_L0_ERROR_MIN_UNDERRUN_ID */ "", 54880 /* LLS_CAPT_UPD2_L0_ERROR_OVERFLOW_ID */ "", 54881 /* LLS_CAPT_UPD2_L0_ERROR_UNDERRUN_ID */ "", 54882 /* LLS_CAPT_UPD2_L1_ERROR_MIN_OVERFLOW_ID */ "", 54883 /* LLS_CAPT_UPD2_L1_ERROR_MIN_UNDERRUN_ID */ "", 54884 /* LLS_CAPT_UPD2_L1_ERROR_OVERFLOW_ID */ "", 54885 /* LLS_CAPT_UPD2_L1_ERROR_UNDERRUN_ID */ "", 54886 /* LLS_CAPT_UPD2_L2_ERROR_MIN_OVERFLOW_ID */ "", 54887 /* LLS_CAPT_UPD2_L2_ERROR_MIN_UNDERRUN_ID */ "", 54888 /* LLS_CAPT_UPD2_L2_ERROR_OVERFLOW_ID */ "", 54889 /* LLS_CAPT_UPD2_L2_ERROR_UNDERRUN_ID */ "", 54890 /* LLS_CAPT_UPD2_PORT_ERROR_OVERFLOW_ID */ "", 54891 /* LLS_CAPT_UPD2_PORT_ERROR_UNDERRUN_ID */ "", 54892 /* LLS_CAPT_UPD2_S0_ERROR_OVERFLOW_ID */ "", 54893 /* LLS_CAPT_UPD2_S0_ERROR_UNDERRUN_ID */ "", 54894 /* LLS_CAPT_UPD2_S1_ERROR_OVERFLOW_ID */ "", 54895 /* LLS_CAPT_UPD2_S1_ERROR_UNDERRUN_ID */ "", 54896 /* LLS_CFG_ERR_BYTE_ADJUST */ "", 54897 /* LLS_CLEAR_S1_CREDITS */ "", 54898 /* LLS_COE_CPU_READ_S1_CREDIT */ "", 54899 /* LLS_COE_CREDIT_READ_ID */ "", 54900 /* LLS_CONFIG0 */ "", 54901 /* LLS_CONFIG_SPARE */ "", 54902 /* LLS_CONFIG_SP_MIN_PRIORITY */ "", 54903 /* LLS_DEBUG_DEQ_BLOCK */ "", 54904 /* LLS_DEBUG_ENQ_BLOCK_ON_L0 */ "", 54905 /* LLS_DEBUG_ENQ_BLOCK_ON_L1 */ "", 54906 /* LLS_DEBUG_ENQ_BLOCK_ON_L2 */ "", 54907 /* LLS_DEBUG_ENQ_BLOCK_ON_PORT */ "", 54908 /* LLS_DEBUG_FORCE_CPU_COSMASK0 */ "", 54909 /* LLS_DEBUG_FORCE_CPU_COSMASK1 */ "", 54910 /* LLS_DEBUG_INJECT_ACTIVATION */ "", 54911 /* LLS_DEBUG_INJECT_FLOWCONTROL1 */ "", 54912 /* LLS_DEBUG_INJECT_FLOWCONTROL2 */ "", 54913 /* LLS_DEBUG_INJECT_FLOWCONTROL3 */ "", 54914 /* LLS_DEBUG_INJECT_S0_MAX_ACTIVATION */ "", 54915 /* LLS_DEBUG_INJECT_S1_MAX_ACTIVATION */ "", 54916 /* LLS_DEBUG_P_WERR_MAX_SC_RESET */ "", 54917 /* LLS_DEBUG_WRR_CTRL */ "", 54918 /* LLS_DEQUEUE_EVENT_SEEN */ "", 54919 /* LLS_DYNAMIC_UPDATE_INT */ "", 54920 /* LLS_DYNAMIC_UPDATE_INT_MASK */ "", 54921 /* LLS_EN_COR_ERR_RPT_L0 */ "", 54922 /* LLS_EN_COR_ERR_RPT_L1 */ "", 54923 /* LLS_EN_COR_ERR_RPT_L2 */ "", 54924 /* LLS_EN_COR_ERR_RPT_PORT */ "", 54925 /* LLS_ERROR */ "", 54926 /* LLS_ERROR2 */ "", 54927 /* LLS_ERROR2_MASK */ "", 54928 /* LLS_ERROR_ECC_DEBUG */ "", 54929 /* LLS_ERROR_MASK */ "", 54930 /* LLS_ERROR_UPD2 */ "", 54931 /* LLS_ERROR_UPD2_MASK */ "", 54932 /* LLS_ERROR_VIOLATE_1IN4_TDM */ "", 54933 /* LLS_FC_CONFIG */ "", 54934 /* LLS_FIXED_DEQ_LEN */ "", 54935 /* LLS_INIT */ "", 54936 /* LLS_L0_CHILD_STATE1_ECC_STATUS */ "", 54937 /* LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUS */ "", 54938 /* LLS_L0_CHILD_WEIGHT_CFG_ECC_STATUS */ "", 54939 /* LLS_L0_CHILD_WEIGHT_WORKING_ECC_STATUS */ "", 54940 /* LLS_L0_CONFIG_ECC_STATUS */ "", 54941 /* LLS_L0_ECC_1B_COUNTER */ "", 54942 /* LLS_L0_ECC_2B_COUNTER */ "", 54943 /* LLS_L0_ECC_DEBUG */ "", 54944 /* LLS_L0_ECC_DEBUG1 */ "", 54945 /* LLS_L0_ECC_ERROR1 */ "", 54946 /* LLS_L0_ECC_ERROR1_MASK */ "", 54947 /* LLS_L0_EF_NEXT_ECC_STATUS */ "", 54948 /* LLS_L0_EMPTY_SEEN_STATUS */ "", 54949 /* LLS_L0_ERROR_ECC_STATUS */ "", 54950 /* LLS_L0_ERROR_MIN_ECC_STATUS */ "", 54951 /* LLS_L0_HEADS_TAILS_ECC_STATUS */ "", 54952 /* LLS_L0_MIN_BUCKET_C_ECC_STATUS */ "", 54953 /* LLS_L0_MIN_CONFIG_C_ECC_STATUS */ "", 54954 /* LLS_L0_MIN_NEXT_ECC_STATUS */ "", 54955 /* LLS_L0_PARENT_ECC_STATUS */ "", 54956 /* LLS_L0_PARENT_STATE_ECC_STATUS */ "", 54957 /* LLS_L0_SHAPER_BUCKET_C_ECC_STATUS */ "", 54958 /* LLS_L0_SHAPER_CONFIG_C_ECC_STATUS */ "", 54959 /* LLS_L0_WERR_MAX_SC_ECC_STATUS */ "", 54960 /* LLS_L0_WERR_NEXT_ECC_STATUS */ "", 54961 /* LLS_L1_CHILD_STATE1_ECC_STATUS */ "", 54962 /* LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUS */ "", 54963 /* LLS_L1_CHILD_WEIGHT_CFG_ECC_STATUS */ "", 54964 /* LLS_L1_CHILD_WEIGHT_WORKING_ECC_STATUS */ "", 54965 /* LLS_L1_CONFIG_ECC_STATUS */ "", 54966 /* LLS_L1_ECC_1B_COUNTER */ "", 54967 /* LLS_L1_ECC_2B_COUNTER */ "", 54968 /* LLS_L1_ECC_DEBUG1 */ "", 54969 /* LLS_L1_ECC_DEBUG1A */ "", 54970 /* LLS_L1_ECC_ERROR1 */ "", 54971 /* LLS_L1_ECC_ERROR1_MASK */ "", 54972 /* LLS_L1_EF_NEXT_ECC_STATUS */ "", 54973 /* LLS_L1_EMPTY_SEEN_STATUS */ "", 54974 /* LLS_L1_ERROR_ECC_STATUS */ "", 54975 /* LLS_L1_ERROR_MIN_ECC_STATUS */ "", 54976 /* LLS_L1_HEADS_TAILS_ECC_STATUS */ "", 54977 /* LLS_L1_MIN_BUCKET_C_ECC_STATUS */ "", 54978 /* LLS_L1_MIN_CONFIG_C_ECC_STATUS */ "", 54979 /* LLS_L1_MIN_NEXT_ECC_STATUS */ "", 54980 /* LLS_L1_PARENT_ECC_STATUS */ "", 54981 /* LLS_L1_PARENT_STATE_ECC_STATUS */ "", 54982 /* LLS_L1_SHAPER_BUCKET_C_ECC_STATUS */ "", 54983 /* LLS_L1_SHAPER_CONFIG_C_ECC_STATUS */ "", 54984 /* LLS_L1_WERR_MAX_SC_ECC_STATUS */ "", 54985 /* LLS_L1_WERR_NEXT_ECC_STATUS */ "", 54986 /* LLS_L2_ACT_MIN_ECC_STATUS */ "", 54987 /* LLS_L2_ACT_SHAPER_ECC_STATUS */ "", 54988 /* LLS_L2_ACT_XON_ECC_STATUS */ "", 54989 /* LLS_L2_CHILD_STATE1_ECC_STATUS */ "", 54990 /* LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUS */ "", 54991 /* LLS_L2_CHILD_WEIGHT_WORKING_ECC_STATUS */ "", 54992 /* LLS_L2_ECC_1B_COUNTER */ "", 54993 /* LLS_L2_ECC_2B_COUNTER */ "", 54994 /* LLS_L2_ECC_DEBUG1 */ "", 54995 /* LLS_L2_ECC_DEBUG2 */ "", 54996 /* LLS_L2_ECC_DEBUG3 */ "", 54997 /* LLS_L2_ECC_ERROR1 */ "", 54998 /* LLS_L2_ECC_ERROR1_MASK */ "", 54999 /* LLS_L2_EMPTY_SEEN_STATUS */ "", 55000 /* LLS_L2_ERROR_ECC_STATUS */ "", 55001 /* LLS_L2_ERROR_MIN_ECC_STATUS */ "", 55002 /* LLS_L2_MIN_BUCKET_C_ECC_STATUS */ "", 55003 /* LLS_L2_MIN_BUCKET_LOWER_C_ECC_STATUS */ "", 55004 /* LLS_L2_MIN_BUCKET_UPPER_C_ECC_STATUS */ "", 55005 /* LLS_L2_MIN_CONFIG_C_ECC_STATUS */ "", 55006 /* LLS_L2_MIN_CONFIG_LOWER_C_ECC_STATUS */ "", 55007 /* LLS_L2_MIN_CONFIG_UPPER_C_ECC_STATUS */ "", 55008 /* LLS_L2_MIN_NEXT_ECC_STATUS */ "", 55009 /* LLS_L2_PARENT_ECC_STATUS */ "", 55010 /* LLS_L2_SHAPER_BUCKET_C_ECC_STATUS */ "", 55011 /* LLS_L2_SHAPER_BUCKET_LOWER_C_ECC_STATUS */ "", 55012 /* LLS_L2_SHAPER_BUCKET_UPPER_C_ECC_STATUS */ "", 55013 /* LLS_L2_SHAPER_CONFIG_C_ECC_STATUS */ "", 55014 /* LLS_L2_SHAPER_CONFIG_LOWER_C_ECC_STATUS */ "", 55015 /* LLS_L2_SHAPER_CONFIG_UPPER_C_ECC_STATUS */ "", 55016 /* LLS_L2_WERR_NEXT_ECC_STATUS */ "", 55017 /* LLS_LB_L0_COS */ "", 55018 /* LLS_LINKPHY_CONFIG_COUNT_S1 */ "", 55019 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_001_000 */ "", 55020 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_000 */ "", 55021 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_003_002 */ "", 55022 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_005_004 */ "", 55023 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_004 */ "", 55024 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_007_006 */ "", 55025 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_009_008 */ "", 55026 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_008 */ "", 55027 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_011_010 */ "", 55028 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_013_012 */ "", 55029 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_012 */ "", 55030 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_015_014 */ "", 55031 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_017_016 */ "", 55032 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_016 */ "", 55033 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_019_018 */ "", 55034 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_021_020 */ "", 55035 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_020 */ "", 55036 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_023_022 */ "", 55037 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_025_024 */ "", 55038 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_027_024 */ "", 55039 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_027_026 */ "", 55040 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_029_028 */ "", 55041 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_031_028 */ "", 55042 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_031_030 */ "", 55043 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_033_032 */ "", 55044 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_035_034 */ "", 55045 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_037_036 */ "", 55046 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_039_038 */ "", 55047 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_041_040 */ "", 55048 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_043_042 */ "", 55049 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_045_044 */ "", 55050 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_047_046 */ "", 55051 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_049_048 */ "", 55052 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_051_050 */ "", 55053 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_053_052 */ "", 55054 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_055_054 */ "", 55055 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_057_056 */ "", 55056 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_059_058 */ "", 55057 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_061_060 */ "", 55058 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_063_062 */ "", 55059 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_065_064 */ "", 55060 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_067_066 */ "", 55061 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_069_068 */ "", 55062 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_071_070 */ "", 55063 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_073_072 */ "", 55064 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_075_074 */ "", 55065 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_077_076 */ "", 55066 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_079_078 */ "", 55067 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_081_080 */ "", 55068 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_083_082 */ "", 55069 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_085_084 */ "", 55070 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_087_086 */ "", 55071 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_089_088 */ "", 55072 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_091_090 */ "", 55073 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_093_092 */ "", 55074 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_095_094 */ "", 55075 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_097_096 */ "", 55076 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_099_098 */ "", 55077 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_101_100 */ "", 55078 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_103_102 */ "", 55079 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_105_104 */ "", 55080 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_107_106 */ "", 55081 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_109_108 */ "", 55082 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_111_110 */ "", 55083 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_113_112 */ "", 55084 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_115_114 */ "", 55085 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_117_116 */ "", 55086 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_119_118 */ "", 55087 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_121_120 */ "", 55088 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_123_122 */ "", 55089 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_125_124 */ "", 55090 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_127_126 */ "", 55091 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_129_128 */ "", 55092 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_131_130 */ "", 55093 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_133_132 */ "", 55094 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_135_134 */ "", 55095 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_137_136 */ "", 55096 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_139_138 */ "", 55097 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_141_140 */ "", 55098 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_143_142 */ "", 55099 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_145_144 */ "", 55100 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_147_146 */ "", 55101 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_149_148 */ "", 55102 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_151_150 */ "", 55103 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_153_152 */ "", 55104 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_155_154 */ "", 55105 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_157_156 */ "", 55106 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_159_158 */ "", 55107 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_161_160 */ "", 55108 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_163_162 */ "", 55109 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_165_164 */ "", 55110 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_167_166 */ "", 55111 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_169_168 */ "", 55112 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_171_170 */ "", 55113 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_173_172 */ "", 55114 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_175_174 */ "", 55115 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_177_176 */ "", 55116 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_179_178 */ "", 55117 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_181_180 */ "", 55118 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_183_182 */ "", 55119 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_185_184 */ "", 55120 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_187_186 */ "", 55121 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_189_188 */ "", 55122 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_191_190 */ "", 55123 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_193_192 */ "", 55124 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_195_194 */ "", 55125 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_197_196 */ "", 55126 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_199_198 */ "", 55127 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_201_200 */ "", 55128 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_203_202 */ "", 55129 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_205_204 */ "", 55130 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_207_206 */ "", 55131 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_209_208 */ "", 55132 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_211_210 */ "", 55133 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_213_212 */ "", 55134 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_215_214 */ "", 55135 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_217_216 */ "", 55136 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_219_218 */ "", 55137 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_221_220 */ "", 55138 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_223_222 */ "", 55139 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_225_224 */ "", 55140 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_227_226 */ "", 55141 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_229_228 */ "", 55142 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_231_230 */ "", 55143 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_233_232 */ "", 55144 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_235_234 */ "", 55145 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_237_236 */ "", 55146 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_239_238 */ "", 55147 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_241_240 */ "", 55148 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_243_242 */ "", 55149 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_245_244 */ "", 55150 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_247_246 */ "", 55151 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_249_248 */ "", 55152 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_251_250 */ "", 55153 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_253_252 */ "", 55154 /* LLS_LINKPHY_CONFIG_DST_STREAM_TO_S1_MAPPING_255_254 */ "", 55155 /* LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0 */ "", 55156 /* LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_127_96 */ "", 55157 /* LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_31_0 */ "", 55158 /* LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_63_32 */ "", 55159 /* LLS_LINKPHY_CONFIG_SEL_SPRI_S1_IN_S0_95_64 */ "", 55160 /* LLS_LINKPHY_CPU_READ_S1_CREDIT */ "", 55161 /* LLS_LINKPHY_CREDIT_READ_ID */ "", 55162 /* LLS_LINK_PHY_ENABLED_CONFIG */ "", 55163 /* LLS_LINK_PHY_SHAPE_S1_CONFIG */ "", 55164 /* LLS_MAX_REFRESH_ENABLE */ "", 55165 /* LLS_MEM_DCM_ERROR */ "", 55166 /* LLS_MEM_DCM_L0 */ "", 55167 /* LLS_MEM_DCM_L1 */ "", 55168 /* LLS_MEM_DCM_L2 */ "", 55169 /* LLS_MEM_DCM_L2_ACT */ "", 55170 /* LLS_MEM_DCM_PORT */ "", 55171 /* LLS_MEM_DEBUG_L0_0 */ "", 55172 /* LLS_MEM_DEBUG_L0_1 */ "", 55173 /* LLS_MEM_DEBUG_L0_2 */ "", 55174 /* LLS_MEM_DEBUG_L0_3 */ "", 55175 /* LLS_MEM_DEBUG_L0_4 */ "", 55176 /* LLS_MEM_DEBUG_L0_5 */ "", 55177 /* LLS_MEM_DEBUG_L0_6 */ "", 55178 /* LLS_MEM_DEBUG_L0_7 */ "", 55179 /* LLS_MEM_DEBUG_L0_8 */ "", 55180 /* LLS_MEM_DEBUG_L0_1A */ "", 55181 /* LLS_MEM_DEBUG_L0_1B */ "", 55182 /* LLS_MEM_DEBUG_L0_4A */ "", 55183 /* LLS_MEM_DEBUG_L0_4B */ "", 55184 /* LLS_MEM_DEBUG_L0_ERROR */ "", 55185 /* LLS_MEM_DEBUG_L1_2 */ "", 55186 /* LLS_MEM_DEBUG_L1_3 */ "", 55187 /* LLS_MEM_DEBUG_L1_4 */ "", 55188 /* LLS_MEM_DEBUG_L1_5 */ "", 55189 /* LLS_MEM_DEBUG_L1_6 */ "", 55190 /* LLS_MEM_DEBUG_L1_7 */ "", 55191 /* LLS_MEM_DEBUG_L1_8 */ "", 55192 /* LLS_MEM_DEBUG_L1_1A */ "", 55193 /* LLS_MEM_DEBUG_L1_1B */ "", 55194 /* LLS_MEM_DEBUG_L1_1C */ "", 55195 /* LLS_MEM_DEBUG_L1_1D */ "", 55196 /* LLS_MEM_DEBUG_L1_3A */ "", 55197 /* LLS_MEM_DEBUG_L1_4A */ "", 55198 /* LLS_MEM_DEBUG_L1_4B */ "", 55199 /* LLS_MEM_DEBUG_L1_ACT_MIN */ "", 55200 /* LLS_MEM_DEBUG_L1_ACT_SHAPER */ "", 55201 /* LLS_MEM_DEBUG_L1_ACT_XON */ "", 55202 /* LLS_MEM_DEBUG_L1_ERROR */ "", 55203 /* LLS_MEM_DEBUG_L1_XOFF */ "", 55204 /* LLS_MEM_DEBUG_L2_1 */ "", 55205 /* LLS_MEM_DEBUG_L2_2 */ "", 55206 /* LLS_MEM_DEBUG_L2_3 */ "", 55207 /* LLS_MEM_DEBUG_L2_4 */ "", 55208 /* LLS_MEM_DEBUG_L2_5 */ "", 55209 /* LLS_MEM_DEBUG_L2_6 */ "", 55210 /* LLS_MEM_DEBUG_L2_7 */ "", 55211 /* LLS_MEM_DEBUG_L2_1A */ "", 55212 /* LLS_MEM_DEBUG_L2_1B */ "", 55213 /* LLS_MEM_DEBUG_L2_1C */ "", 55214 /* LLS_MEM_DEBUG_L2_2A */ "", 55215 /* LLS_MEM_DEBUG_L2_ACT_ENQ */ "", 55216 /* LLS_MEM_DEBUG_L2_ACT_MIN */ "", 55217 /* LLS_MEM_DEBUG_L2_ACT_SHAPER */ "", 55218 /* LLS_MEM_DEBUG_L2_ACT_XON */ "", 55219 /* LLS_MEM_DEBUG_L2_ERROR */ "", 55220 /* LLS_MEM_DEBUG_L2_SHAPER_STATE_MAX */ "", 55221 /* LLS_MEM_DEBUG_L2_SHAPER_STATE_MIN */ "", 55222 /* LLS_MEM_DEBUG_L2_XOFF */ "", 55223 /* LLS_MEM_DEBUG_PORT1 */ "", 55224 /* LLS_MEM_DEBUG_PORT4 */ "", 55225 /* LLS_MEM_DEBUG_PORT_TDM */ "", 55226 /* LLS_MEM_DEBUG_PORT_WERR_MAX_SC */ "", 55227 /* LLS_MEM_DEBUG_S0_0 */ "", 55228 /* LLS_MEM_DEBUG_S0_ERROR */ "", 55229 /* LLS_MEM_DEBUG_S1_0 */ "", 55230 /* LLS_MEM_DEBUG_S1_1 */ "", 55231 /* LLS_MEM_DEBUG_S1_2 */ "", 55232 /* LLS_MEM_DEBUG_S1_3 */ "", 55233 /* LLS_MEM_DEBUG_S1_4 */ "", 55234 /* LLS_MEM_DEBUG_S1_5 */ "", 55235 /* LLS_MEM_DEBUG_S1_6 */ "", 55236 /* LLS_MEM_DEBUG_S1_7 */ "", 55237 /* LLS_MEM_DEBUG_S1_ERROR */ "", 55238 /* LLS_MEM_L0_TM_0 */ "", 55239 /* LLS_MEM_L0_TM_1 */ "", 55240 /* LLS_MEM_L0_TM_2 */ "", 55241 /* LLS_MEM_L0_TM_3 */ "", 55242 /* LLS_MEM_L0_TM_4 */ "", 55243 /* LLS_MEM_L0_TM_5 */ "", 55244 /* LLS_MEM_L0_TM_6 */ "", 55245 /* LLS_MEM_L0_TM_7 */ "", 55246 /* LLS_MEM_L0_TM_8 */ "", 55247 /* LLS_MEM_L0_TM_9 */ "", 55248 /* LLS_MEM_L1_TM_0 */ "", 55249 /* LLS_MEM_L1_TM_1 */ "", 55250 /* LLS_MEM_L1_TM_2 */ "", 55251 /* LLS_MEM_L1_TM_3 */ "", 55252 /* LLS_MEM_L1_TM_4 */ "", 55253 /* LLS_MEM_L1_TM_5 */ "", 55254 /* LLS_MEM_L1_TM_6 */ "", 55255 /* LLS_MEM_L1_TM_7 */ "", 55256 /* LLS_MEM_L1_TM_8 */ "", 55257 /* LLS_MEM_L1_TM_9 */ "", 55258 /* LLS_MEM_L2_TM_0 */ "", 55259 /* LLS_MEM_L2_TM_2 */ "", 55260 /* LLS_MEM_L2_TM_3 */ "", 55261 /* LLS_MEM_L2_TM_4 */ "", 55262 /* LLS_MEM_L2_TM_5 */ "", 55263 /* LLS_MEM_L2_TM_6 */ "", 55264 /* LLS_MEM_PORT_TM_0 */ "", 55265 /* LLS_MEM_PORT_TM_1 */ "", 55266 /* LLS_MIN_CAP_CONFIG */ "", 55267 /* LLS_MIN_CONFIG */ "", 55268 /* LLS_MIN_REFRESH_ENABLE */ "", 55269 /* LLS_MISC_ECC_ERROR1 */ "", 55270 /* LLS_MISC_ECC_ERROR1_MASK */ "", 55271 /* LLS_PER_PORT_WRR_PKT_MODE_0 */ "", 55272 /* LLS_PER_PORT_WRR_PKT_MODE_1 */ "", 55273 /* LLS_PER_PORT_WRR_PKT_MODE_2 */ "", 55274 /* LLS_PKT_ACC_CONFIG1 */ "", 55275 /* LLS_PKT_ACC_CONFIG2 */ "", 55276 /* LLS_PKT_ACC_CONFIG3 */ "", 55277 /* LLS_PORT_01_COE_CONFIG */ "", 55278 /* LLS_PORT_01_LINKPHY_CONFIG */ "", 55279 /* LLS_PORT_02_COE_CONFIG */ "", 55280 /* LLS_PORT_02_LINKPHY_CONFIG */ "", 55281 /* LLS_PORT_03_COE_CONFIG */ "", 55282 /* LLS_PORT_03_LINKPHY_CONFIG */ "", 55283 /* LLS_PORT_04_COE_CONFIG */ "", 55284 /* LLS_PORT_04_LINKPHY_CONFIG */ "", 55285 /* LLS_PORT_05_COE_CONFIG */ "", 55286 /* LLS_PORT_05_LINKPHY_CONFIG */ "", 55287 /* LLS_PORT_06_COE_CONFIG */ "", 55288 /* LLS_PORT_06_LINKPHY_CONFIG */ "", 55289 /* LLS_PORT_07_COE_CONFIG */ "", 55290 /* LLS_PORT_07_LINKPHY_CONFIG */ "", 55291 /* LLS_PORT_08_COE_CONFIG */ "", 55292 /* LLS_PORT_08_LINKPHY_CONFIG */ "", 55293 /* LLS_PORT_09_COE_CONFIG */ "", 55294 /* LLS_PORT_09_LINKPHY_CONFIG */ "", 55295 /* LLS_PORT_0_CREDIT */ "", 55296 /* LLS_PORT_10_COE_CONFIG */ "", 55297 /* LLS_PORT_10_CREDIT */ "", 55298 /* LLS_PORT_10_LINKPHY_CONFIG */ "", 55299 /* LLS_PORT_11_COE_CONFIG */ "", 55300 /* LLS_PORT_11_CREDIT */ "", 55301 /* LLS_PORT_11_LINKPHY_CONFIG */ "", 55302 /* LLS_PORT_12_COE_CONFIG */ "", 55303 /* LLS_PORT_12_CREDIT */ "", 55304 /* LLS_PORT_12_LINKPHY_CONFIG */ "", 55305 /* LLS_PORT_13_COE_CONFIG */ "", 55306 /* LLS_PORT_13_CREDIT */ "", 55307 /* LLS_PORT_13_LINKPHY_CONFIG */ "", 55308 /* LLS_PORT_14_COE_CONFIG */ "", 55309 /* LLS_PORT_14_CREDIT */ "", 55310 /* LLS_PORT_14_LINKPHY_CONFIG */ "", 55311 /* LLS_PORT_15_COE_CONFIG */ "", 55312 /* LLS_PORT_15_CREDIT */ "", 55313 /* LLS_PORT_15_LINKPHY_CONFIG */ "", 55314 /* LLS_PORT_16_COE_CONFIG */ "", 55315 /* LLS_PORT_16_CREDIT */ "", 55316 /* LLS_PORT_16_LINKPHY_CONFIG */ "", 55317 /* LLS_PORT_17_COE_CONFIG */ "", 55318 /* LLS_PORT_17_CREDIT */ "", 55319 /* LLS_PORT_17_LINKPHY_CONFIG */ "", 55320 /* LLS_PORT_18_COE_CONFIG */ "", 55321 /* LLS_PORT_18_CREDIT */ "", 55322 /* LLS_PORT_18_LINKPHY_CONFIG */ "", 55323 /* LLS_PORT_19_COE_CONFIG */ "", 55324 /* LLS_PORT_19_CREDIT */ "", 55325 /* LLS_PORT_19_LINKPHY_CONFIG */ "", 55326 /* LLS_PORT_1_CREDIT */ "", 55327 /* LLS_PORT_20_COE_CONFIG */ "", 55328 /* LLS_PORT_20_CREDIT */ "", 55329 /* LLS_PORT_20_LINKPHY_CONFIG */ "", 55330 /* LLS_PORT_21_COE_CONFIG */ "", 55331 /* LLS_PORT_21_CREDIT */ "", 55332 /* LLS_PORT_21_LINKPHY_CONFIG */ "", 55333 /* LLS_PORT_22_COE_CONFIG */ "", 55334 /* LLS_PORT_22_CREDIT */ "", 55335 /* LLS_PORT_22_LINKPHY_CONFIG */ "", 55336 /* LLS_PORT_23_COE_CONFIG */ "", 55337 /* LLS_PORT_23_CREDIT */ "", 55338 /* LLS_PORT_23_LINKPHY_CONFIG */ "", 55339 /* LLS_PORT_24_COE_CONFIG */ "", 55340 /* LLS_PORT_24_CREDIT */ "", 55341 /* LLS_PORT_24_LINKPHY_CONFIG */ "", 55342 /* LLS_PORT_25_COE_CONFIG */ "", 55343 /* LLS_PORT_25_CREDIT */ "", 55344 /* LLS_PORT_25_LINKPHY_CONFIG */ "", 55345 /* LLS_PORT_26_COE_CONFIG */ "", 55346 /* LLS_PORT_26_CREDIT */ "", 55347 /* LLS_PORT_26_LINKPHY_CONFIG */ "", 55348 /* LLS_PORT_27_COE_CONFIG */ "", 55349 /* LLS_PORT_27_CREDIT */ "", 55350 /* LLS_PORT_27_LINKPHY_CONFIG */ "", 55351 /* LLS_PORT_28_COE_CONFIG */ "", 55352 /* LLS_PORT_28_CREDIT */ "", 55353 /* LLS_PORT_28_LINKPHY_CONFIG */ "", 55354 /* LLS_PORT_29_CREDIT */ "", 55355 /* LLS_PORT_29_LINKPHY_CONFIG */ "", 55356 /* LLS_PORT_2_CREDIT */ "", 55357 /* LLS_PORT_30_CREDIT */ "", 55358 /* LLS_PORT_30_LINKPHY_CONFIG */ "", 55359 /* LLS_PORT_31_CREDIT */ "", 55360 /* LLS_PORT_31_LINKPHY_CONFIG */ "", 55361 /* LLS_PORT_32_CREDIT */ "", 55362 /* LLS_PORT_32_LINKPHY_CONFIG */ "", 55363 /* LLS_PORT_33_CREDIT */ "", 55364 /* LLS_PORT_33_LINKPHY_CONFIG */ "", 55365 /* LLS_PORT_34_CREDIT */ "", 55366 /* LLS_PORT_34_LINKPHY_CONFIG */ "", 55367 /* LLS_PORT_35_CREDIT */ "", 55368 /* LLS_PORT_35_LINKPHY_CONFIG */ "", 55369 /* LLS_PORT_36_CREDIT */ "", 55370 /* LLS_PORT_36_LINKPHY_CONFIG */ "", 55371 /* LLS_PORT_37_CREDIT */ "", 55372 /* LLS_PORT_37_LINKPHY_CONFIG */ "", 55373 /* LLS_PORT_38_CREDIT */ "", 55374 /* LLS_PORT_38_LINKPHY_CONFIG */ "", 55375 /* LLS_PORT_39_CREDIT */ "", 55376 /* LLS_PORT_39_LINKPHY_CONFIG */ "", 55377 /* LLS_PORT_3_CREDIT */ "", 55378 /* LLS_PORT_40_CREDIT */ "", 55379 /* LLS_PORT_40_LINKPHY_CONFIG */ "", 55380 /* LLS_PORT_41_CREDIT */ "", 55381 /* LLS_PORT_42_CREDIT */ "", 55382 /* LLS_PORT_43_CREDIT */ "", 55383 /* LLS_PORT_44_CREDIT */ "", 55384 /* LLS_PORT_45_CREDIT */ "", 55385 /* LLS_PORT_46_CREDIT */ "", 55386 /* LLS_PORT_47_CREDIT */ "", 55387 /* LLS_PORT_48_CREDIT */ "", 55388 /* LLS_PORT_49_CREDIT */ "", 55389 /* LLS_PORT_4_CREDIT */ "", 55390 /* LLS_PORT_50_CREDIT */ "", 55391 /* LLS_PORT_51_CREDIT */ "", 55392 /* LLS_PORT_52_CREDIT */ "", 55393 /* LLS_PORT_53_CREDIT */ "", 55394 /* LLS_PORT_54_CREDIT */ "", 55395 /* LLS_PORT_55_CREDIT */ "", 55396 /* LLS_PORT_56_CREDIT */ "", 55397 /* LLS_PORT_57_CREDIT */ "", 55398 /* LLS_PORT_58_CREDIT */ "", 55399 /* LLS_PORT_59_CREDIT */ "", 55400 /* LLS_PORT_5_CREDIT */ "", 55401 /* LLS_PORT_60_CREDIT */ "", 55402 /* LLS_PORT_61_CREDIT */ "", 55403 /* LLS_PORT_62_CREDIT */ "", 55404 /* LLS_PORT_6_CREDIT */ "", 55405 /* LLS_PORT_7_CREDIT */ "", 55406 /* LLS_PORT_8_CREDIT */ "", 55407 /* LLS_PORT_9_CREDIT */ "", 55408 /* LLS_PORT_COE_ENABLE */ "", 55409 /* LLS_PORT_COE_LINKPHY_ENABLE_LOWER */ "", 55410 /* LLS_PORT_COE_LINKPHY_ENABLE_UPPER */ "", 55411 /* LLS_PORT_ECC_1B_COUNTER */ "", 55412 /* LLS_PORT_ECC_2B_COUNTER */ "", 55413 /* LLS_PORT_ECC_DEBUG */ "", 55414 /* LLS_PORT_ECC_ERROR */ "", 55415 /* LLS_PORT_ECC_ERROR_MASK */ "", 55416 /* LLS_PORT_EMPTY_SEEN_STATUS */ "", 55417 /* LLS_PORT_L2_COUNT_CPU_ADDR */ "", 55418 /* LLS_PORT_L2_COUNT_CPU_DATA */ "", 55419 /* LLS_PORT_SHAPER_CONFIG_C_ECC_STATUS */ "", 55420 /* LLS_PORT_TDM_ECC_STATUS */ "", 55421 /* LLS_PORT_WERR_MAX_SC_ECC_STATUS */ "", 55422 /* LLS_S0S1_ECC_1B_COUNTER */ "", 55423 /* LLS_S0S1_ECC_2B_COUNTER */ "", 55424 /* LLS_S0_ERROR_ECC_STATUS */ "", 55425 /* LLS_S0_SHAPER_BUCKET_ECC_STATUS */ "", 55426 /* LLS_S0_SHAPER_CONFIG_C_ECC_STATUS */ "", 55427 /* LLS_S1_ECC_DEBUG */ "", 55428 /* LLS_S1_ERROR_ECC_STATUS */ "", 55429 /* LLS_S1_SHAPER_BUCKET_ECC_STATUS */ "", 55430 /* LLS_S1_SHAPER_CONFIG_C_ECC_STATUS */ "", 55431 /* LLS_S1_TAILS_ECC_STATUS */ "", 55432 /* LLS_SHAPER_CONFIG_CALC_REORDER */ "", 55433 /* LLS_SHAPER_LAST_ADDR_CONFIG0 */ "", 55434 /* LLS_SHAPER_LAST_ADDR_CONFIG1 */ "", 55435 /* LLS_SHAPER_LAST_ADDR_CONFIG2 */ "", 55436 /* LLS_SHAPER_LAST_ADDR_CONFIG3 */ "", 55437 /* LLS_SHAPER_REFRESH_CONFIG */ "", 55438 /* LLS_SHAPER_REFRESH_CONFIG1 */ "", 55439 /* LLS_SHAPER_UNDERRUN_MONITOR_0_CFG */ "", 55440 /* LLS_SHAPER_UNDERRUN_MONITOR_1_CFG */ "", 55441 /* LLS_SHAPER_UNDERRUN_MONITOR_2_CFG */ "", 55442 /* LLS_SHAPER_UNDERRUN_MONITOR_3_CFG */ "", 55443 /* LLS_SHAPER_UNDERRUN_MONITOR_SEEN */ "", 55444 /* LLS_SOFT_RESET */ "", 55445 /* LLS_SPARE_REGS1 */ "", 55446 /* LLS_SPARE_REGS2 */ "", 55447 /* LLS_SP_WERR_DYN_CHANGE_0 */ "", 55448 /* LLS_SP_WERR_DYN_CHANGE_1 */ "", 55449 /* LLS_SP_WERR_DYN_CHANGE_2 */ "", 55450 /* LLS_SP_WERR_DYN_CHANGE_3 */ "", 55451 /* LLS_SP_WERR_DYN_CHANGE_0A */ "", 55452 /* LLS_SP_WERR_DYN_CHANGE_0B */ "", 55453 /* LLS_SP_WERR_DYN_CHANGE_0C */ "", 55454 /* LLS_SP_WERR_DYN_CHANGE_1A */ "", 55455 /* LLS_SP_WERR_DYN_CHANGE_1B */ "", 55456 /* LLS_SP_WERR_DYN_CHANGE_1C */ "", 55457 /* LLS_SP_WERR_DYN_CHANGE_2A */ "", 55458 /* LLS_SP_WERR_DYN_CHANGE_2B */ "", 55459 /* LLS_SP_WERR_DYN_CHANGE_2C */ "", 55460 /* LLS_SP_WERR_DYN_CHANGE_3A */ "", 55461 /* LLS_SP_WERR_DYN_CHANGE_3B */ "", 55462 /* LLS_SP_WERR_DYN_CHANGE_3C */ "", 55463 /* LLS_TDM_AXP_SCHEDULING */ "", 55464 /* LLS_TDM_CAL_CFG */ "", 55465 /* LLS_TDM_CAL_CFG_SWITCH */ "", 55466 /* LLS_TDM_OPPORTUNISTIC_SPACING */ "", 55467 /* LLS_TDM_STATUS */ "", 55468 /* LLS_TREX2_DEBUG_ENABLE */ "", 55469 /* LLS_TWO_S1S_IN_S0_CONFIG */ "", 55470 /* LLS_XOFF_ECC_DEBUG */ "", 55471 /* LMEP_1_PARITY_CONTROL */ "", 55472 /* LMEP_1_PARITY_STATUS_INTR */ "", 55473 /* LMEP_1_PARITY_STATUS_NACK */ "", 55474 /* LMEP_COMMON */ "", 55475 /* LMEP_COMMON_1 */ "", 55476 /* LMEP_COMMON_2 */ "", 55477 /* LMEP_DA_PARITY_CONTROL */ "", 55478 /* LMEP_DA_PARITY_STATUS */ "", 55479 /* LMEP_DA_PDA_CONTROL */ "", 55480 /* LMEP_PARITY_CONTROL */ "", 55481 /* LMEP_PARITY_STATUS */ "", 55482 /* LMEP_PARITY_STATUS_INTR */ "", 55483 /* LMEP_PARITY_STATUS_NACK */ "", 55484 /* LMEP_PDA_CONTROL */ "", 55485 /* LOADING_BAND_THRESHOLD */ "", 55486 /* LOCAL_SW_DISABLE_CTRL */ "", 55487 /* LOCAL_SW_DISABLE_DEFAULT_PBM */ "", 55488 /* LOCAL_SW_DISABLE_DEFAULT_PBM_64 */ "LOCAL_SW_DISABLE_DEFAULT_PBM", 55489 /* LOCAL_SW_DISABLE_DEFAULT_PBM_HI */ "LOCAL_SW_DISABLE_DEFAULT_PBM_HI", 55490 /* LOCAL_SW_DISABLE_DEFAULT_PBM_LO */ "LOCAL_SW_DISABLE_DEFAULT_PBM_LO", 55491 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR */ "LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR", 55492 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_64 */ "LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR", 55493 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_HI */ "LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_HI", 55494 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_LO */ "LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_LO", 55495 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROL */ "", 55496 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTR */ "", 55497 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACK */ "", 55498 /* LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROL */ "", 55499 /* LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTR */ "", 55500 /* LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACK */ "", 55501 /* LOG_TO_PHY_PORT_MAPPING */ "", 55502 /* LOPSTH */ "", 55503 /* LPM_LOG_TO_PHY_BANK_MAP */ "", 55504 /* LPM_MEMORY_DBGCTRL */ "LPM_MEMORY_CONTROL_0", 55505 /* LPORT_ECC_CONTROL */ "", 55506 /* LPORT_ECC_STATUS_INTR */ "", 55507 /* LPORT_ECC_STATUS_NACK */ "", 55508 /* LPORT_FLEX_COUNTER_STRENGTH */ "", 55509 /* LPORT_TABLE_ECC_CONTROL */ "", 55510 /* LPORT_TABLE_ECC_STATUS_INTR */ "", 55511 /* LPORT_TABLE_PARITY_STATUS */ "", 55512 /* LWMCOSCELLSETLIMIT */ "", 55513 /* LWMCOSCELLSETLIMIT_QLAYER */ "", 55514 /* M0SSQ_M0_IDM_IDM_INTERRUPT_STATUS */ "", 55515 /* M0SSQ_M0_IDM_IDM_RESET_CONTROL */ "", 55516 /* M0SSQ_M0_IDM_IDM_RESET_STATUS */ "", 55517 /* M0SSQ_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 55518 /* M0SSQ_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 55519 /* M0SSQ_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 55520 /* M0SSQ_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 55521 /* M0SSQ_S0_IDM_IDM_ERROR_LOG_ID */ "", 55522 /* M0SSQ_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 55523 /* M0SSQ_S0_IDM_IDM_INTERRUPT_STATUS */ "", 55524 /* M0SSQ_S0_IDM_IDM_RESET_CONTROL */ "", 55525 /* M0SSQ_S0_IDM_IDM_RESET_READ_ID */ "", 55526 /* M0SSQ_S0_IDM_IDM_RESET_STATUS */ "", 55527 /* M0SSQ_S0_IDM_IDM_RESET_WRITE_ID */ "", 55528 /* M0SSQ_SRAM_LL_128K_CONTROL1 */ "", 55529 /* M0SSQ_SRAM_LL_128K_DYNAMIC_STANDBY_CONTROL1 */ "", 55530 /* M0SSQ_SRAM_LL_128K_DYNAMIC_STANDBY_CONTROL2 */ "", 55531 /* M0SSQ_SRAM_LL_128K_INTERRUPT_ENABLE */ "", 55532 /* M0SSQ_SRAM_LL_128K_INTERRUPT_STATUS */ "", 55533 /* M0SSQ_SRAM_LL_128K_MEMORY_CONTROL */ "", 55534 /* M0SSQ_SRAM_LL_128K_MEMORY_PDA */ "", 55535 /* M0SSQ_SRAM_LL_128K_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 55536 /* M0SSQ_SRAM_LL_128K_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 55537 /* M0SSQ_SRAM_LL_128K_MEM_1BIT_ECC_ERR_W0B0 */ "", 55538 /* M0SSQ_SRAM_LL_128K_MEM_1BIT_ECC_ERR_W0B1 */ "", 55539 /* M0SSQ_SRAM_LL_128K_MEM_1BIT_ECC_ERR_W1B0 */ "", 55540 /* M0SSQ_SRAM_LL_128K_MEM_1BIT_ECC_ERR_W1B1 */ "", 55541 /* M0SSQ_SRAM_LL_128K_MEM_PWR_CONTROL */ "", 55542 /* M0SSQ_SRAM_LL_128K_STATUS1 */ "", 55543 /* M0SSQ_SRAM_LL_128K_STATUS2 */ "", 55544 /* M0SSQ_SRAM_LL_128K_STATUS3 */ "", 55545 /* M0SSQ_SRAM_LL_128K_STATUS4 */ "", 55546 /* M0SSQ_SRAM_LL_128K_STATUS5 */ "", 55547 /* M0SSQ_SRAM_LL_128K_STATUS6 */ "", 55548 /* M0SSQ_SRAM_LL_128K_STATUS7 */ "", 55549 /* M0SSQ_SRAM_LL_128K_STATUS8 */ "", 55550 /* M0SSQ_SRAM_LL_128K_STATUS9 */ "", 55551 /* M0SSQ_SRAM_LL_128K_STATUS10 */ "", 55552 /* M7SS_CONFIG */ "", 55553 /* M7SS_CTRL */ "", 55554 /* M7SS_D0TCM_ECC_ERR_ADDR */ "", 55555 /* M7SS_D1TCM_ECC_ERR_ADDR */ "", 55556 /* M7SS_DTCM */ "", 55557 /* M7SS_ECOREVNUM_LSB */ "", 55558 /* M7SS_ECOREVNUM_MSB */ "", 55559 /* M7SS_INIT */ "", 55560 /* M7SS_ITCM */ "", 55561 /* M7SS_ITCM_ECC_ERR_ADDR */ "", 55562 /* M7SS_MISC0 */ "", 55563 /* M7SS_STATUS */ "", 55564 /* M7SS_SYSTICK_CFGSTCALIB */ "", 55565 /* MACMERGERHOLDCOUNT */ "", 55566 /* MACSEC_CNTRL */ "", 55567 /* MACSEC_CREDIT_ENABLE */ "", 55568 /* MACSEC_OLP_HEADER_TYPE */ "", 55569 /* MACSEC_PROG_TX_CRC */ "", 55570 /* MACT_APP_DB_TO_APP_DB_INDEX_MAP */ "", 55571 /* MACT_ECC_1B_ERR_CNT */ "", 55572 /* MACT_ECC_2B_ERR_CNT */ "", 55573 /* MACT_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 55574 /* MACT_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 55575 /* MACT_ECC_INTERRUPT_REGISTER */ "", 55576 /* MACT_ECC_INTERRUPT_REGISTER_MASK */ "", 55577 /* MACT_ECC_INTERRUPT_REGISTER_TEST */ "", 55578 /* MACT_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 55579 /* MACT_ERROR_INITIATION_DATA */ "", 55580 /* MACT_GTIMER_CONFIGURATION */ "", 55581 /* MACT_GTIMER_CYCLE */ "", 55582 /* MACT_INDIRECT_COMMAND */ "", 55583 /* MACT_INDIRECT_COMMAND_ADDRESS */ "", 55584 /* MACT_INDIRECT_COMMAND_RD_DATA */ "", 55585 /* MACT_INDIRECT_COMMAND_WR_DATA */ "", 55586 /* MACT_INDIRECT_FORCE_BUBBLE */ "", 55587 /* MACT_INTERRUPT_MASK_REGISTER */ "", 55588 /* MACT_INTERRUPT_REGISTER */ "", 55589 /* MACT_INTERRUPT_REGISTER_TEST */ "", 55590 /* MACT_IS_LARGE_EM */ "", 55591 /* MACT_LARGE_EM_COUNTER_LIMIT_CONFIGURATION */ "", 55592 /* MACT_LARGE_EM_CPU_EVENT */ "", 55593 /* MACT_LARGE_EM_DB_ENTRIES_COUNTER */ "", 55594 /* MACT_LARGE_EM_ERROR_DELETE_NON_EXIST_COUNTER */ "", 55595 /* MACT_LARGE_EM_ERROR_LEARN_REQUEST_OVER_STRONGER_COUNTER */ "", 55596 /* MACT_LARGE_EM_ERROR_REFRESH_REQUEST_OVER_STRONGER_COUNTER */ "", 55597 /* MACT_LARGE_EM_ERROR_TRANSPLANT_REQUEST_OVER_STRONGER_COUNTER */ "", 55598 /* MACT_LARGE_EM_EVENT_FIFO_CONFIGURATION */ "", 55599 /* MACT_LARGE_EM_EVENT_FIFO_EVENT_COUNTER */ "", 55600 /* MACT_LARGE_EM_EVENT_FIFO_EVENT_DROP_COUNTERS */ "", 55601 /* MACT_LARGE_EM_EVENT_FIFO_EVENT_FIFO_ENTRY_COUNT */ "", 55602 /* MACT_LARGE_EM_EVENT_FIFO_HIGH_THRESHOLD */ "", 55603 /* MACT_LARGE_EM_EVENT_FIFO_PROPERTIES */ "", 55604 /* MACT_LARGE_EM_INTERRUPT_MASK_REGISTER */ "", 55605 /* MACT_LARGE_EM_INTERRUPT_REGISTER */ "", 55606 /* MACT_LARGE_EM_LELA_COUNTERS_A */ "", 55607 /* MACT_LARGE_EM_LELA_COUNTERS_B */ "", 55608 /* MACT_LARGE_EM_LELA_EXCEED_LIMIT_FID */ "", 55609 /* MACT_LARGE_EM_LELB_COUNTERS_A */ "", 55610 /* MACT_LARGE_EM_LELB_COUNTERS_B */ "", 55611 /* MACT_LARGE_EM_LELB_EXCEED_LIMIT_FID */ "", 55612 /* MACT_LARGE_EM_MANAGEMENT_REQUEST_FIFO_PROPERTIES */ "", 55613 /* MACT_LARGE_EM_MNGMNT_REQ_CONFIGURATION */ "", 55614 /* MACT_LARGE_EM_MNGMNT_REQ_COUNTERS_A */ "", 55615 /* MACT_LARGE_EM_MNGMNT_REQ_COUNTERS_B */ "", 55616 /* MACT_LARGE_EM_MNGMNT_REQ_COUNTERS_C */ "", 55617 /* MACT_LARGE_EM_MNGMNT_REQ_EXCEED_LIMIT_ALLOWED_FID */ "", 55618 /* MACT_LARGE_EM_MNGMNT_REQ_EXCEED_LIMIT_FID */ "", 55619 /* MACT_LARGE_EM_MNGMNT_REQ_REQUEST_COUNTER */ "", 55620 /* MACT_LARGE_EM_MNGMNT_REQ_REQUEST_FIFO_ENTRY_COUNT */ "", 55621 /* MACT_LARGE_EM_MNGMNT_REQ_REQUEST_FIFO_WATERMARK */ "", 55622 /* MACT_LARGE_EM_MRQ_CONFIGURATION */ "", 55623 /* MACT_LARGE_EM_OLP_REQUEST_REQUEST */ "", 55624 /* MACT_LARGE_EM_OLP_REQUEST_TRIGGER */ "", 55625 /* MACT_LARGE_EM_REPLY */ "", 55626 /* MACT_LARGE_EM_REPLY_FIFO_CONFIGURATION */ "", 55627 /* MACT_LARGE_EM_REPLY_FIFO_ENTRY_COUNT */ "", 55628 /* MACT_LARGE_EM_REPLY_FIFO_HIGH_THRESHOLD */ "", 55629 /* MACT_LARGE_EM_REPLY_FIFO_REPLY_COUNTER */ "", 55630 /* MACT_LARGE_EM_REPLY_FIFO_REPLY_DROP_COUNTERS */ "", 55631 /* MACT_LARGE_EM_REPLY_FIFO_WATERMARK */ "", 55632 /* MACT_LARGE_EM_WARNING_LEARN_OVER_EXISTING_COUNTER */ "", 55633 /* MACT_LARGE_EM_WARNING_REFRESH_NON_EXIST_COUNTER */ "", 55634 /* MACT_LARGE_EM_WARNING_TRANSPLANT_NON_EXIST_COUNTER */ "", 55635 /* MACT_MACT_GENERAL_CONFIGURATION */ "", 55636 /* MACT_MACT_INTERRUPT_REGISTER_TEST */ "", 55637 /* MACT_PCMI_0 */ "", 55638 /* MACT_PCMI_0_S */ "", 55639 /* MACT_PCMI_0_T */ "", 55640 /* MACT_REG_0041 */ "", 55641 /* MACT_REG_00A4 */ "", 55642 /* MACT_REG_00A6 */ "", 55643 /* MACT_REG_00C2 */ "", 55644 /* MACT_RESERVED_MIRROR_ADDR */ "", 55645 /* MACT_RESERVED_MTCD */ "", 55646 /* MACT_RESERVED_MTCP */ "", 55647 /* MACT_RESERVED_SPARE_0 */ "", 55648 /* MACT_RESERVED_SPARE_1 */ "", 55649 /* MACT_RESERVED_SPARE_2 */ "", 55650 /* MACT_RESERVED_SPARE_3 */ "", 55651 /* MACT_SBUS_BROADCAST_ID */ "", 55652 /* MACT_SBUS_LAST_IN_CHAIN */ "", 55653 /* MACT_SPECIAL_CLOCK_CONTROLS */ "", 55654 /* MACT_VMV_TO_ENTRY_FORMAT_INDEX_MAP */ "", 55655 /* MAC_0 */ "", 55656 /* MAC_1 */ "", 55657 /* MAC_BLOCK_TABLE_PARITY_CONTROL */ "", 55658 /* MAC_BLOCK_TABLE_PARITY_STATUS */ "", 55659 /* MAC_BLOCK_TABLE_PARITY_STATUS_INTR */ "", 55660 /* MAC_BLOCK_TABLE_PARITY_STATUS_NACK */ "", 55661 /* MAC_CNTMAXSZ */ "", 55662 /* MAC_CORESPARE0 */ "", 55663 /* MAC_CTRL */ "", 55664 /* MAC_HCFC_CTRL */ "", 55665 /* MAC_HCFC_STATUS */ "", 55666 /* MAC_LIMIT_CONFIG */ "", 55667 /* MAC_LIMIT_ENABLE */ "", 55668 /* MAC_LIMIT_MEMORY_CONTROL_0 */ "", 55669 /* MAC_LIMIT_MEMORY_CONTROL_1 */ "", 55670 /* MAC_LIMIT_MEMORY_CONTROL_2 */ "", 55671 /* MAC_LIMIT_MEMORY_CONTROL_3 */ "", 55672 /* MAC_LIMIT_PARITY_CONTROL */ "", 55673 /* MAC_LIMIT_RAM_CONTROL_2 */ "", 55674 /* MAC_LIMIT_RAM_CONTROL_3 */ "", 55675 /* MAC_LIMIT_RAM_DBGCTRL */ "MAC_LIMIT_RAM_CONTROL", 55676 /* MAC_LIMIT_RAM_DBGCTRL_0 */ "MAC_LIMIT_RAM_CONTROL_0", 55677 /* MAC_LIMIT_RAM_DBGCTRL_1 */ "MAC_LIMIT_RAM_CONTROL_1", 55678 /* MAC_MEM_CTRL */ "", 55679 /* MAC_MERGE_CLEAR_STATUS */ "", 55680 /* MAC_MERGE_CONFIG */ "", 55681 /* MAC_MERGE_DEBUG_COUNTERS_DONE_STATUS */ "", 55682 /* MAC_MERGE_FRG_CNT_CONFIG */ "", 55683 /* MAC_MERGE_MFRM_CONFIG */ "", 55684 /* MAC_MERGE_RX_DEBUG_COUNTERS_CONFIG_0 */ "", 55685 /* MAC_MERGE_RX_DEBUG_COUNTERS_CONFIG_1 */ "", 55686 /* MAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0 */ "", 55687 /* MAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1 */ "", 55688 /* MAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2 */ "", 55689 /* MAC_MERGE_RX_DEBUG_COUNTERS_STATUS_3 */ "", 55690 /* MAC_MERGE_RX_DEBUG_COUNTERS_STATUS_4 */ "", 55691 /* MAC_MERGE_RX_TIMEOUT_CONFIG */ "", 55692 /* MAC_MERGE_SMD_CONFIG_0 */ "", 55693 /* MAC_MERGE_SMD_CONFIG_1 */ "", 55694 /* MAC_MERGE_SMD_CONFIG_2 */ "", 55695 /* MAC_MERGE_STATUS */ "", 55696 /* MAC_MERGE_TX_DEBUG_COUNTERS_CONFIG_0 */ "", 55697 /* MAC_MERGE_TX_DEBUG_COUNTERS_CONFIG_1 */ "", 55698 /* MAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0 */ "", 55699 /* MAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1 */ "", 55700 /* MAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2 */ "", 55701 /* MAC_MERGE_TX_DEBUG_COUNTERS_STATUS_3 */ "", 55702 /* MAC_MERGE_TX_DEBUG_COUNTERS_STATUS_4 */ "", 55703 /* MAC_MERGE_VERIFY_STATE */ "", 55704 /* MAC_MODE */ "", 55705 /* MAC_PFC_COS0_XOFF_CNT */ "", 55706 /* MAC_PFC_COS10_XOFF_CNT */ "", 55707 /* MAC_PFC_COS11_XOFF_CNT */ "", 55708 /* MAC_PFC_COS12_XOFF_CNT */ "", 55709 /* MAC_PFC_COS13_XOFF_CNT */ "", 55710 /* MAC_PFC_COS14_XOFF_CNT */ "", 55711 /* MAC_PFC_COS15_XOFF_CNT */ "", 55712 /* MAC_PFC_COS1_XOFF_CNT */ "", 55713 /* MAC_PFC_COS2_XOFF_CNT */ "", 55714 /* MAC_PFC_COS3_XOFF_CNT */ "", 55715 /* MAC_PFC_COS4_XOFF_CNT */ "", 55716 /* MAC_PFC_COS5_XOFF_CNT */ "", 55717 /* MAC_PFC_COS6_XOFF_CNT */ "", 55718 /* MAC_PFC_COS7_XOFF_CNT */ "", 55719 /* MAC_PFC_COS8_XOFF_CNT */ "", 55720 /* MAC_PFC_COS9_XOFF_CNT */ "", 55721 /* MAC_PFC_CTRL */ "", 55722 /* MAC_PFC_DA */ "", 55723 /* MAC_PFC_DA_0 */ "", 55724 /* MAC_PFC_DA_1 */ "", 55725 /* MAC_PFC_FIELD */ "", 55726 /* MAC_PFC_OPCODE */ "", 55727 /* MAC_PFC_REFRESH_CTRL */ "", 55728 /* MAC_PFC_TYPE */ "", 55729 /* MAC_RSV_MASK */ "", 55730 /* MAC_RXCTRL */ "", 55731 /* MAC_RXLLFCMSGCNT */ "", 55732 /* MAC_RXLLFCMSGFLDS */ "", 55733 /* MAC_RXLSSCTRL */ "", 55734 /* MAC_RXLSSSTAT */ "", 55735 /* MAC_RXMACSA */ "", 55736 /* MAC_RXMAXSZ */ "", 55737 /* MAC_RXMUXCTRL */ "", 55738 /* MAC_RXSPARE0 */ "", 55739 /* MAC_SPARE0 */ "", 55740 /* MAC_SPARE1 */ "", 55741 /* MAC_STAT_UPDATE_MASK */ "", 55742 /* MAC_TXCTRL */ "", 55743 /* MAC_TXLLFCCTRL */ "", 55744 /* MAC_TXLLFCMSGFLDS */ "", 55745 /* MAC_TXMACSA */ "", 55746 /* MAC_TXMAXSZ */ "", 55747 /* MAC_TXMUXCTRL */ "", 55748 /* MAC_TXPPPCTRL */ "", 55749 /* MAC_TXPSETHR */ "", 55750 /* MAC_TXSPARE0 */ "", 55751 /* MAC_TXTIMESTAMPFIFOREAD */ "", 55752 /* MAC_TXTIMESTAMPFIFOSTATUS */ "", 55753 /* MAC_TX_STATUS */ "", 55754 /* MAC_XGXS_CTRL */ "", 55755 /* MAC_XGXS_STAT */ "", 55756 /* MAID_PARITY_CONTROL */ "", 55757 /* MAID_PARITY_STATUS_INTR */ "", 55758 /* MAID_PARITY_STATUS_NACK */ "", 55759 /* MAID_REDUCTION_PARITY_CONTROL */ "", 55760 /* MAID_REDUCTION_PARITY_STATUS */ "", 55761 /* MAID_REDUCTION_PARITY_STATUS_INTR */ "", 55762 /* MAID_REDUCTION_PARITY_STATUS_NACK */ "", 55763 /* MAIN0_DEVICEINPKG5 */ "", 55764 /* MAIN0_ECC_1B_ERR_INTERRUPT_EN */ "", 55765 /* MAIN0_ECC_2B_ERR_INTERRUPT_EN */ "", 55766 /* MAIN0_ECC_CORRUPT_CONTROL_0 */ "", 55767 /* MAIN0_ECC_CORRUPT_CONTROL_1 */ "", 55768 /* MAIN0_ECC_DISABLE_CONTROL */ "", 55769 /* MAIN0_LOOPBACK_CONTROL */ "", 55770 /* MAIN0_MDIO_BROADCAST */ "", 55771 /* MAIN0_REGACCESS_TIMEOUT */ "", 55772 /* MAIN0_REGACCESS_TIMEOUT_STATUS */ "", 55773 /* MAIN0_SERDESID */ "", 55774 /* MAIN0_SETUP */ "", 55775 /* MAIN0_SPEED_CTRL */ "", 55776 /* MAIN0_SYNCE_CONTROL */ "", 55777 /* MAIN0_SYNCE_CONTROL_STAGE0 */ "", 55778 /* MAIN0_TICK_CONTROL_0 */ "", 55779 /* MAIN0_TICK_CONTROL_1 */ "", 55780 /* MAIN0_TM_CONTROL */ "", 55781 /* MAIN0_TS_1588_CTRL */ "", 55782 /* MAIN0_TS_TIMER_OFFSET */ "", 55783 /* MAXBUCKET */ "", 55784 /* MAXBUCKETCONFIG */ "", 55785 /* MAXBUCKETCONFIG1 */ "", 55786 /* MAXBUCKETCONFIG_64 */ "MAXBUCKETCONFIG", 55787 /* MAXBUCKETMEMDEBUG */ "", 55788 /* MAXBUCKET_FLAG */ "", 55789 /* MAXBUCKET_FLAG_QGROUP */ "", 55790 /* MAXBUCKET_FLAG_QLAYER */ "", 55791 /* MAXFR */ "", 55792 /* MA_INDEX_ECC_CONTROL */ "", 55793 /* MA_INDEX_PARITY_CONTROL */ "", 55794 /* MA_INDEX_PARITY_STATUS */ "", 55795 /* MA_INDEX_PARITY_STATUS_INTR */ "", 55796 /* MA_INDEX_PARITY_STATUS_NACK */ "", 55797 /* MA_STATE_ECCP_CONTROL */ "", 55798 /* MA_STATE_PARITY_CONTROL */ "", 55799 /* MA_STATE_PARITY_STATUS */ "", 55800 /* MA_STATE_PARITY_STATUS_INTR */ "", 55801 /* MA_STATE_PARITY_STATUS_NACK */ "", 55802 /* MB0_MEMDEBUG */ "", 55803 /* MB1_MEMDEBUG */ "", 55804 /* MB_MEMDEBUG */ "", 55805 /* MB_TCB_MEMDEBUG */ "", 55806 /* MCAST_STORM_CONTROL */ "", 55807 /* MCFIFOMEMDEBUG */ "", 55808 /* MCFIFO_CONFIG */ "", 55809 /* MCFP_MEM_DEBUG */ "", 55810 /* MCFP_MEM_DEBUG_TM */ "", 55811 /* MCP_ECC_1B_ERR_CNT */ "", 55812 /* MCP_ECC_2B_ERR_CNT */ "", 55813 /* MCP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 55814 /* MCP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 55815 /* MCP_ECC_INTERRUPT_REGISTER */ "", 55816 /* MCP_ECC_INTERRUPT_REGISTER_MASK */ "", 55817 /* MCP_ECC_INTERRUPT_REGISTER_TEST */ "", 55818 /* MCP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 55819 /* MCP_ENG_DB_BANK_ACCESS_ERR_SOURCE */ "", 55820 /* MCP_ENG_DB_BANK_SOURCE */ "", 55821 /* MCP_ERROR_INITIATION_DATA */ "", 55822 /* MCP_GTIMER_CONFIGURATION */ "", 55823 /* MCP_GTIMER_CYCLE */ "", 55824 /* MCP_INDIRECT_COMMAND */ "", 55825 /* MCP_INDIRECT_COMMAND_ADDRESS */ "", 55826 /* MCP_INDIRECT_COMMAND_RD_DATA */ "", 55827 /* MCP_INDIRECT_COMMAND_WR_DATA */ "", 55828 /* MCP_INDIRECT_FORCE_BUBBLE */ "", 55829 /* MCP_INTERRUPT_MASK_REGISTER */ "", 55830 /* MCP_INTERRUPT_REGISTER */ "", 55831 /* MCP_INTERRUPT_REGISTER_TEST */ "", 55832 /* MCP_PCMI_0 */ "", 55833 /* MCP_PCMI_1 */ "", 55834 /* MCP_PCMI_2 */ "", 55835 /* MCP_PCMI_3 */ "", 55836 /* MCP_PCMI_4 */ "", 55837 /* MCP_PCMI_0_S */ "", 55838 /* MCP_PCMI_0_T */ "", 55839 /* MCP_PCMI_1_S */ "", 55840 /* MCP_PCMI_1_T */ "", 55841 /* MCP_PCMI_2_S */ "", 55842 /* MCP_PCMI_2_T */ "", 55843 /* MCP_PCMI_3_S */ "", 55844 /* MCP_PCMI_3_T */ "", 55845 /* MCP_PCMI_4_S */ "", 55846 /* MCP_PCMI_4_T */ "", 55847 /* MCP_REG_0041 */ "", 55848 /* MCP_REG_00A4 */ "", 55849 /* MCP_REG_00A6 */ "", 55850 /* MCP_REG_00C2 */ "", 55851 /* MCP_RESERVED_MIRROR_ADDR */ "", 55852 /* MCP_RESERVED_MTCD */ "", 55853 /* MCP_RESERVED_MTCP */ "", 55854 /* MCP_RESERVED_SPARE_0 */ "", 55855 /* MCP_RESERVED_SPARE_1 */ "", 55856 /* MCP_RESERVED_SPARE_2 */ "", 55857 /* MCP_RESERVED_SPARE_3 */ "", 55858 /* MCP_SBUS_BROADCAST_ID */ "", 55859 /* MCP_SBUS_LAST_IN_CHAIN */ "", 55860 /* MCQE_MAPPER_MEM_DEBUG_TM */ "", 55861 /* MCQE_MEM_DEBUG */ "", 55862 /* MCQE_MEM_DEBUG_TM */ "", 55863 /* MCQN_MEM_DEBUG */ "", 55864 /* MCQN_MEM_DEBUG_TM */ "", 55865 /* MCQ_CONFIG */ "", 55866 /* MCQ_DIS_IPMC_REPLICATION0 */ "MCQ_DIS_IPMC_REPLICATION0", 55867 /* MCQ_DIS_IPMC_REPLICATION1 */ "MCQ_DIS_IPMC_REPLICATION1", 55868 /* MCQ_ERRINTR */ "", 55869 /* MCQ_FIFO_BASE_REG */ "", 55870 /* MCQ_FIFO_BASE_REG_56 */ "", 55871 /* MCQ_FIFO_BASE_REG_32_35 */ "", 55872 /* MCQ_FIFO_BASE_REG_36_39 */ "", 55873 /* MCQ_FIFO_BASE_REG_48_55 */ "", 55874 /* MCQ_FIFO_BASE_REG_CPU */ "", 55875 /* MCQ_FIFO_BASE_REG_PASSTHRU */ "", 55876 /* MCQ_FIFO_EMPTY_REG */ "", 55877 /* MCQ_GRPTBLERRPTR */ "", 55878 /* MCQ_IPMCREP_SRCHFAIL0 */ "", 55879 /* MCQ_IPMCREP_SRCHFAIL1 */ "", 55880 /* MCQ_IPMC_FAST_FLUSH */ "MCQ_IPMC_FAST_FLUSH0", 55881 /* MCQ_IPMC_FAST_FLUSH0 */ "MCQ_IPMC_FAST_FLUSH0", 55882 /* MCQ_IPMC_FAST_FLUSH1 */ "MCQ_IPMC_FAST_FLUSH1", 55883 /* MCQ_IPMC_REPLICATION_STAT0 */ "MCQ_IPMC_REPLICATION_STAT0", 55884 /* MCQ_IPMC_REPLICATION_STAT1 */ "MCQ_IPMC_REPLICATION_STAT1", 55885 /* MCQ_MCFIFOERRPORTBM */ "", 55886 /* MCQ_MCFIFOERRPTR */ "", 55887 /* MCQ_REPLHEADERRPTR */ "", 55888 /* MCQ_VLANTBLERRPTR */ "", 55889 /* MCS_MEM_POWER_DOWN_CONTROL */ "", 55890 /* MCS_MEM_POWER_DOWN_INPUTS */ "", 55891 /* MCS_MEM_TM_CONTROL_REG_1 */ "", 55892 /* MCS_MEM_TM_CONTROL_REG_2 */ "", 55893 /* MCS_MEM_TM_CONTROL_REG_3 */ "", 55894 /* MCS_MEM_TM_CONTROL_REG_4 */ "", 55895 /* MCS_MEM_TM_CONTROL_REG_5 */ "", 55896 /* MCS_MEM_TM_CONTROL_REG_6 */ "", 55897 /* MCS_MEM_TM_CONTROL_REG_7 */ "", 55898 /* MCS_MEM_TM_CONTROL_REG_8 */ "", 55899 /* MCS_MEM_TM_CONTROL_REG_9 */ "", 55900 /* MCS_MEM_TM_CONTROL_REG_10 */ "", 55901 /* MCS_MEM_TM_CONTROL_REG_11 */ "", 55902 /* MCS_MEM_TM_CONTROL_REG_12 */ "", 55903 /* MCTHD_MEMORY_DEBUG_TM */ "", 55904 /* MCT_AUTO_DOC_NAME_12 */ "", 55905 /* MCT_AUTO_DOC_NAME_13 */ "", 55906 /* MCT_AUTO_DOC_NAME_14 */ "", 55907 /* MCT_AUTO_DOC_NAME_15 */ "", 55908 /* MCT_AUTO_DOC_NAME_16 */ "", 55909 /* MCT_AUTO_DOC_NAME_17 */ "", 55910 /* MCT_AUTO_DOC_NAME_18 */ "", 55911 /* MCT_AUTO_DOC_NAME_19 */ "", 55912 /* MCT_ECC_1B_ERR_CNT */ "", 55913 /* MCT_ECC_2B_ERR_CNT */ "", 55914 /* MCT_ECC_ERR_1B_INITIATE */ "", 55915 /* MCT_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 55916 /* MCT_ECC_ERR_2B_INITIATE */ "", 55917 /* MCT_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 55918 /* MCT_ECC_INTERRUPT_REGISTER */ "", 55919 /* MCT_ECC_INTERRUPT_REGISTER_MASK */ "", 55920 /* MCT_ECC_INTERRUPT_REGISTER_TEST */ "", 55921 /* MCT_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 55922 /* MCT_ERROR_INITIATION_DATA */ "", 55923 /* MCT_GLOBAL_MEM_OPTIONS */ "", 55924 /* MCT_GTIMER_CONFIGURATION */ "", 55925 /* MCT_GTIMER_CYCLE */ "", 55926 /* MCT_INDIRECT_COMMAND */ "", 55927 /* MCT_INDIRECT_COMMAND_ADDRESS */ "", 55928 /* MCT_INDIRECT_COMMAND_DATA_INCREMENT */ "", 55929 /* MCT_INDIRECT_COMMAND_RD_DATA */ "", 55930 /* MCT_INDIRECT_COMMAND_WIDE_MEM */ "", 55931 /* MCT_INDIRECT_COMMAND_WR_DATA */ "", 55932 /* MCT_INDIRECT_FORCE_BUBBLE */ "", 55933 /* MCT_INTERRUPT_MASK_REGISTER */ "", 55934 /* MCT_INTERRUPT_REGISTER */ "", 55935 /* MCT_INTERRUPT_REGISTER_TEST */ "", 55936 /* MCT_RESERVED_MIRROR_ADDR */ "", 55937 /* MCT_RESERVED_MTCD */ "", 55938 /* MCT_RESERVED_MTCP */ "", 55939 /* MCT_RESERVED_SPARE_0 */ "", 55940 /* MCT_RESERVED_SPARE_1 */ "", 55941 /* MCT_RESERVED_SPARE_2 */ "", 55942 /* MCT_RESERVED_SPARE_3 */ "", 55943 /* MCT_SBUS_BROADCAST_ID */ "", 55944 /* MCT_SBUS_LAST_IN_CHAIN */ "", 55945 /* MC_CONTROL_1 */ "", 55946 /* MC_CONTROL_2 */ "", 55947 /* MC_CONTROL_3 */ "", 55948 /* MC_CONTROL_4 */ "", 55949 /* MC_CONTROL_5 */ "", 55950 /* MC_COS1_TO_LOOPBACK_COS_MAP_SPLIT0 */ "", 55951 /* MC_COS1_TO_LOOPBACK_COS_MAP_SPLIT1 */ "", 55952 /* MC_COS2_TO_LOOPBACK_COS_MAP_SPLIT0 */ "", 55953 /* MC_COS2_TO_LOOPBACK_COS_MAP_SPLIT1 */ "", 55954 /* MDB_ARM_KAPS_CONFIG */ "", 55955 /* MDB_ARM_KAPS_CONFIG_CFIFO */ "", 55956 /* MDB_ARM_KAPS_CONFIG_CFIFO_THRESH */ "", 55957 /* MDB_ARM_KAPS_CONFIG_FIFO_MON */ "", 55958 /* MDB_ARM_KAPS_CONFIG_RFIFO */ "", 55959 /* MDB_ARM_KAPS_GLOBAL_DEBUG */ "", 55960 /* MDB_ARM_KAPS_GLOBAL_EVENT */ "", 55961 /* MDB_ARM_KAPS_GLOBAL_EVENT_MASK */ "", 55962 /* MDB_ARM_KAPS_IBC_COMMAND_DATA */ "", 55963 /* MDB_ARM_KAPS_IBC_COMMAND_WORD */ "", 55964 /* MDB_ARM_KAPS_IBC_CONFIG */ "", 55965 /* MDB_ARM_KAPS_IBC_FIFO_CORRECTABLE_STATUS */ "", 55966 /* MDB_ARM_KAPS_IBC_FIFO_ECC_DEBUG */ "", 55967 /* MDB_ARM_KAPS_IBC_FIFO_MEM_CONTROL */ "", 55968 /* MDB_ARM_KAPS_IBC_FIFO_TM_TEST_CTRL */ "", 55969 /* MDB_ARM_KAPS_IBC_FIFO_UNCORRECTABLE_STATUS */ "", 55970 /* MDB_ARM_KAPS_IBC_QUEUE_STATUS */ "", 55971 /* MDB_ARM_KAPS_IBC_RESPONSE_DATA */ "", 55972 /* MDB_ARM_KAPS_IBC_RESPONSE_WORD */ "", 55973 /* MDB_ARM_KAPS_MEMORY_A_ERROR */ "", 55974 /* MDB_ARM_KAPS_MEMORY_A_ERROR_MASK */ "", 55975 /* MDB_ARM_KAPS_MEMORY_B_ERROR */ "", 55976 /* MDB_ARM_KAPS_MEMORY_B_ERROR_MASK */ "", 55977 /* MDB_ARM_KAPS_PD_ASSIST_DEBUG */ "", 55978 /* MDB_ARM_KAPS_REVISION */ "", 55979 /* MDB_ARM_KAPS_R_5_ATTN */ "", 55980 /* MDB_ARM_KAPS_R_5_AXI_CONFIG */ "", 55981 /* MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_0 */ "", 55982 /* MDB_ARM_KAPS_R_5_AXI_ERROR_STATUS_1 */ "", 55983 /* MDB_ARM_KAPS_R_5_CONFIGA */ "", 55984 /* MDB_ARM_KAPS_R_5_CORE_CONFIGA */ "", 55985 /* MDB_ARM_KAPS_R_5_CORE_CONFIGB */ "", 55986 /* MDB_ARM_KAPS_R_5_CORE_CONFIGC */ "", 55987 /* MDB_ARM_KAPS_R_5_CORE_CONFIGD */ "", 55988 /* MDB_ARM_KAPS_R_5_CORE_CONFIGE */ "", 55989 /* MDB_ARM_KAPS_R_5_CORE_CONTROL */ "", 55990 /* MDB_ARM_KAPS_R_5_CORE_MEM_CONTROL */ "", 55991 /* MDB_ARM_KAPS_R_5_COUNTERS */ "", 55992 /* MDB_ARM_KAPS_R_5_DAP_APB_ADDR */ "", 55993 /* MDB_ARM_KAPS_R_5_DAP_APB_CTRL */ "", 55994 /* MDB_ARM_KAPS_R_5_DAP_APB_RDATA */ "", 55995 /* MDB_ARM_KAPS_R_5_DAP_APB_WDATA */ "", 55996 /* MDB_ARM_KAPS_R_5_DEBUG_CONFIGA */ "", 55997 /* MDB_ARM_KAPS_R_5_DEBUG_CONFIGB */ "", 55998 /* MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_0 */ "", 55999 /* MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_1 */ "", 56000 /* MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_0_MASK */ "", 56001 /* MDB_ARM_KAPS_R_5_DEBUG_EBUS_PATTERN_1_MASK */ "", 56002 /* MDB_ARM_KAPS_R_5_DEBUG_STATUS */ "", 56003 /* MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0 */ "", 56004 /* MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1 */ "", 56005 /* MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_0_MASK */ "", 56006 /* MDB_ARM_KAPS_R_5_DEBUG_STATUS_EVENT_BUS_1_MASK */ "", 56007 /* MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_A */ "", 56008 /* MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_0 */ "", 56009 /* MDB_ARM_KAPS_R_5_ECC_ERR_RD_TCM_B_1 */ "", 56010 /* MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_A */ "", 56011 /* MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_0 */ "", 56012 /* MDB_ARM_KAPS_R_5_ECC_ERR_WR_TCM_B_1 */ "", 56013 /* MDB_ARM_KAPS_R_5_FIFO_MON_EVENT */ "", 56014 /* MDB_ARM_KAPS_R_5_FIFO_MON_EVENT_MASK */ "", 56015 /* MDB_ARM_KAPS_R_5_TM_TEST_CTRL */ "", 56016 /* MDB_ARM_KAPS_SEARCH_0_A_ERROR */ "", 56017 /* MDB_ARM_KAPS_SEARCH_0_A_ERROR_MASK */ "", 56018 /* MDB_ARM_KAPS_SEARCH_0_B_ERROR */ "", 56019 /* MDB_ARM_KAPS_SEARCH_0_B_ERROR_MASK */ "", 56020 /* MDB_ARM_KAPS_SEARCH_1_A_ERROR */ "", 56021 /* MDB_ARM_KAPS_SEARCH_1_A_ERROR_MASK */ "", 56022 /* MDB_ARM_KAPS_SEARCH_1_B_ERROR */ "", 56023 /* MDB_ARM_KAPS_SEARCH_1_B_ERROR_MASK */ "", 56024 /* MDB_ARM_KAPS_STATUS_CFIFO */ "", 56025 /* MDB_ARM_KAPS_STATUS_RFIFO */ "", 56026 /* MDB_ARM_REG_0000CF00 */ "", 56027 /* MDB_ARM_REG_0000EF00 */ "", 56028 /* MDB_CORE_0_ERPP_EXEM_4_DB_CNT */ "", 56029 /* MDB_CORE_0_ERPP_GLEM_DB_CNT */ "", 56030 /* MDB_CORE_0_ERPP_MC_ID_DB_CNT */ "", 56031 /* MDB_CORE_0_ETPP_0_EOEM_DB_CNT */ "", 56032 /* MDB_CORE_0_ETPP_0_ESEM_DB_CNT */ "", 56033 /* MDB_CORE_0_ETPP_0_GLEM_DB_CNT */ "", 56034 /* MDB_CORE_0_ETPP_1_EOEM_DB_CNT */ "", 56035 /* MDB_CORE_0_ETPP_1_ESEM_DB_CNT */ "", 56036 /* MDB_CORE_0_ETPP_1_GLEM_DB_CNT */ "", 56037 /* MDB_CORE_0_ETPP_2_EOEM_DB_CNT */ "", 56038 /* MDB_CORE_0_ETPP_2_GLEM_DB_CNT */ "", 56039 /* MDB_CORE_0_ETPP_3_EOEM_DB_CNT */ "", 56040 /* MDB_CORE_0_ETPP_EXEM_3_DB_CNT */ "", 56041 /* MDB_CORE_0_ETPP_MC_ID_DB_CNT */ "", 56042 /* MDB_CORE_0_FLP_0_IOEM_DB_CNT */ "", 56043 /* MDB_CORE_0_FLP_0_LEM_DB_CNT */ "", 56044 /* MDB_CORE_0_FLP_1_IOEM_DB_CNT */ "", 56045 /* MDB_CORE_0_FLP_1_LEM_DB_CNT */ "", 56046 /* MDB_CORE_0_FLP_2_IOEM_DB_CNT */ "", 56047 /* MDB_CORE_0_FLP_3_IOEM_DB_CNT */ "", 56048 /* MDB_CORE_0_IPP_0_EXEM_1_DB_CNT */ "", 56049 /* MDB_CORE_0_IPP_1_EXEM_1_DB_CNT */ "", 56050 /* MDB_CORE_0_IPP_2_EXEM_2_DB_CNT */ "", 56051 /* MDB_CORE_0_IPP_3_EXEM_2_DB_CNT */ "", 56052 /* MDB_CORE_0_IPP_4_EXEM_3_DB_CNT */ "", 56053 /* MDB_CORE_0_IPP_EXEM_4_DB_CNT */ "", 56054 /* MDB_CORE_0_VTT_0_ISEM_1_DB_CNT */ "", 56055 /* MDB_CORE_0_VTT_0_ISEM_2_DB_CNT */ "", 56056 /* MDB_CORE_0_VTT_0_ISEM_3_DB_CNT */ "", 56057 /* MDB_CORE_0_VTT_1_ISEM_1_DB_CNT */ "", 56058 /* MDB_CORE_0_VTT_1_ISEM_2_DB_CNT */ "", 56059 /* MDB_CORE_0_VTT_1_ISEM_3_DB_CNT */ "", 56060 /* MDB_CORE_1_ERPP_EXEM_4_DB_CNT */ "", 56061 /* MDB_CORE_1_ERPP_GLEM_DB_CNT */ "", 56062 /* MDB_CORE_1_ERPP_MC_ID_DB_CNT */ "", 56063 /* MDB_CORE_1_ETPP_0_EOEM_DB_CNT */ "", 56064 /* MDB_CORE_1_ETPP_0_ESEM_DB_CNT */ "", 56065 /* MDB_CORE_1_ETPP_0_GLEM_DB_CNT */ "", 56066 /* MDB_CORE_1_ETPP_1_EOEM_DB_CNT */ "", 56067 /* MDB_CORE_1_ETPP_1_ESEM_DB_CNT */ "", 56068 /* MDB_CORE_1_ETPP_1_GLEM_DB_CNT */ "", 56069 /* MDB_CORE_1_ETPP_2_EOEM_DB_CNT */ "", 56070 /* MDB_CORE_1_ETPP_2_GLEM_DB_CNT */ "", 56071 /* MDB_CORE_1_ETPP_3_EOEM_DB_CNT */ "", 56072 /* MDB_CORE_1_ETPP_EXEM_3_DB_CNT */ "", 56073 /* MDB_CORE_1_ETPP_MC_ID_DB_CNT */ "", 56074 /* MDB_CORE_1_FLP_0_IOEM_DB_CNT */ "", 56075 /* MDB_CORE_1_FLP_0_LEM_DB_CNT */ "", 56076 /* MDB_CORE_1_FLP_1_IOEM_DB_CNT */ "", 56077 /* MDB_CORE_1_FLP_1_LEM_DB_CNT */ "", 56078 /* MDB_CORE_1_FLP_2_IOEM_DB_CNT */ "", 56079 /* MDB_CORE_1_FLP_3_IOEM_DB_CNT */ "", 56080 /* MDB_CORE_1_IPP_0_EXEM_1_DB_CNT */ "", 56081 /* MDB_CORE_1_IPP_1_EXEM_1_DB_CNT */ "", 56082 /* MDB_CORE_1_IPP_2_EXEM_2_DB_CNT */ "", 56083 /* MDB_CORE_1_IPP_3_EXEM_2_DB_CNT */ "", 56084 /* MDB_CORE_1_IPP_4_EXEM_3_DB_CNT */ "", 56085 /* MDB_CORE_1_IPP_EXEM_4_DB_CNT */ "", 56086 /* MDB_CORE_1_VTT_0_ISEM_1_DB_CNT */ "", 56087 /* MDB_CORE_1_VTT_0_ISEM_2_DB_CNT */ "", 56088 /* MDB_CORE_1_VTT_0_ISEM_3_DB_CNT */ "", 56089 /* MDB_CORE_1_VTT_1_ISEM_1_DB_CNT */ "", 56090 /* MDB_CORE_1_VTT_1_ISEM_2_DB_CNT */ "", 56091 /* MDB_CORE_1_VTT_1_ISEM_3_DB_CNT */ "", 56092 /* MDB_ECC_1B_ERR_CNT */ "", 56093 /* MDB_ECC_2B_ERR_CNT */ "", 56094 /* MDB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 56095 /* MDB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 56096 /* MDB_ECC_INTERRUPT_REGISTER */ "", 56097 /* MDB_ECC_INTERRUPT_REGISTER_MASK */ "", 56098 /* MDB_ECC_INTERRUPT_REGISTER_TEST */ "", 56099 /* MDB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 56100 /* MDB_ERROR_INITIATION_DATA */ "", 56101 /* MDB_GTIMER_CONFIGURATION */ "", 56102 /* MDB_GTIMER_CYCLE */ "", 56103 /* MDB_INDIRECT_COMMAND */ "", 56104 /* MDB_INDIRECT_COMMAND_ADDRESS */ "", 56105 /* MDB_INDIRECT_COMMAND_RD_DATA */ "", 56106 /* MDB_INDIRECT_COMMAND_WR_DATA */ "", 56107 /* MDB_INDIRECT_FORCE_BUBBLE */ "", 56108 /* MDB_INDIRECT_WR_MASK */ "", 56109 /* MDB_OAMP_0_RMEP_DB_CNT */ "", 56110 /* MDB_OAMP_1_RMEP_DB_CNT */ "", 56111 /* MDB_PARITY_ERR_CNT */ "", 56112 /* MDB_PAR_ERR_MEM_MASK */ "", 56113 /* MDB_PCMI_0 */ "", 56114 /* MDB_PCMI_1 */ "", 56115 /* MDB_PCMI_2 */ "", 56116 /* MDB_PCMI_3 */ "", 56117 /* MDB_PCMI_4 */ "", 56118 /* MDB_PCMI_0_S */ "", 56119 /* MDB_PCMI_0_T */ "", 56120 /* MDB_PCMI_1_S */ "", 56121 /* MDB_PCMI_1_T */ "", 56122 /* MDB_PCMI_2_S */ "", 56123 /* MDB_PCMI_2_T */ "", 56124 /* MDB_PCMI_3_S */ "", 56125 /* MDB_PCMI_3_T */ "", 56126 /* MDB_PCMI_4_S */ "", 56127 /* MDB_PCMI_4_T */ "", 56128 /* MDB_REG_0000 */ "", 56129 /* MDB_REG_0010 */ "", 56130 /* MDB_REG_0018 */ "", 56131 /* MDB_REG_0041 */ "", 56132 /* MDB_REG_100 */ "", 56133 /* MDB_REG_102 */ "", 56134 /* MDB_REG_103 */ "", 56135 /* MDB_REG_104 */ "", 56136 /* MDB_REG_109 */ "", 56137 /* MDB_REG_110 */ "", 56138 /* MDB_REG_111 */ "", 56139 /* MDB_REG_112 */ "", 56140 /* MDB_REG_115 */ "", 56141 /* MDB_REG_117 */ "", 56142 /* MDB_REG_118 */ "", 56143 /* MDB_REG_119 */ "", 56144 /* MDB_REG_120 */ "", 56145 /* MDB_REG_121 */ "", 56146 /* MDB_REG_123 */ "", 56147 /* MDB_REG_124 */ "", 56148 /* MDB_REG_125 */ "", 56149 /* MDB_REG_127 */ "", 56150 /* MDB_REG_128 */ "", 56151 /* MDB_REG_130 */ "", 56152 /* MDB_REG_132 */ "", 56153 /* MDB_REG_134 */ "", 56154 /* MDB_REG_136 */ "", 56155 /* MDB_REG_138 */ "", 56156 /* MDB_REG_139 */ "", 56157 /* MDB_REG_140 */ "", 56158 /* MDB_REG_141 */ "", 56159 /* MDB_REG_142 */ "", 56160 /* MDB_REG_143 */ "", 56161 /* MDB_REG_144 */ "", 56162 /* MDB_REG_145 */ "", 56163 /* MDB_REG_149 */ "", 56164 /* MDB_REG_151 */ "", 56165 /* MDB_REG_152 */ "", 56166 /* MDB_REG_153 */ "", 56167 /* MDB_REG_157 */ "", 56168 /* MDB_REG_158 */ "", 56169 /* MDB_REG_159 */ "", 56170 /* MDB_REG_160 */ "", 56171 /* MDB_REG_161 */ "", 56172 /* MDB_REG_162 */ "", 56173 /* MDB_REG_163 */ "", 56174 /* MDB_REG_165 */ "", 56175 /* MDB_REG_166 */ "", 56176 /* MDB_REG_167 */ "", 56177 /* MDB_REG_173 */ "", 56178 /* MDB_REG_175 */ "", 56179 /* MDB_REG_181 */ "", 56180 /* MDB_REG_183 */ "", 56181 /* MDB_REG_185 */ "", 56182 /* MDB_REG_191 */ "", 56183 /* MDB_REG_193 */ "", 56184 /* MDB_REG_194 */ "", 56185 /* MDB_REG_195 */ "", 56186 /* MDB_REG_198 */ "", 56187 /* MDB_REG_199 */ "", 56188 /* MDB_REG_200 */ "", 56189 /* MDB_REG_201 */ "", 56190 /* MDB_REG_202 */ "", 56191 /* MDB_REG_205 */ "", 56192 /* MDB_REG_206 */ "", 56193 /* MDB_REG_207 */ "", 56194 /* MDB_REG_212 */ "", 56195 /* MDB_REG_214 */ "", 56196 /* MDB_REG_215 */ "", 56197 /* MDB_REG_216 */ "", 56198 /* MDB_REG_217 */ "", 56199 /* MDB_REG_218 */ "", 56200 /* MDB_REG_219 */ "", 56201 /* MDB_REG_220 */ "", 56202 /* MDB_REG_221 */ "", 56203 /* MDB_REG_223 */ "", 56204 /* MDB_REG_227 */ "", 56205 /* MDB_REG_229 */ "", 56206 /* MDB_REG_233 */ "", 56207 /* MDB_REG_235 */ "", 56208 /* MDB_REG_237 */ "", 56209 /* MDB_REG_238 */ "", 56210 /* MDB_REG_243 */ "", 56211 /* MDB_REG_244 */ "", 56212 /* MDB_REG_245 */ "", 56213 /* MDB_REG_246 */ "", 56214 /* MDB_REG_250 */ "", 56215 /* MDB_REG_252 */ "", 56216 /* MDB_REG_253 */ "", 56217 /* MDB_REG_254 */ "", 56218 /* MDB_REG_255 */ "", 56219 /* MDB_REG_256 */ "", 56220 /* MDB_REG_257 */ "", 56221 /* MDB_REG_258 */ "", 56222 /* MDB_REG_259 */ "", 56223 /* MDB_REG_260 */ "", 56224 /* MDB_REG_262 */ "", 56225 /* MDB_REG_263 */ "", 56226 /* MDB_REG_264 */ "", 56227 /* MDB_REG_265 */ "", 56228 /* MDB_REG_269 */ "", 56229 /* MDB_REG_270 */ "", 56230 /* MDB_REG_271 */ "", 56231 /* MDB_REG_273 */ "", 56232 /* MDB_REG_274 */ "", 56233 /* MDB_REG_276 */ "", 56234 /* MDB_REG_277 */ "", 56235 /* MDB_REG_278 */ "", 56236 /* MDB_REG_279 */ "", 56237 /* MDB_REG_280 */ "", 56238 /* MDB_REG_282 */ "", 56239 /* MDB_REG_283 */ "", 56240 /* MDB_REG_289 */ "", 56241 /* MDB_REG_290 */ "", 56242 /* MDB_REG_291 */ "", 56243 /* MDB_REG_292 */ "", 56244 /* MDB_REG_294 */ "", 56245 /* MDB_REG_296 */ "", 56246 /* MDB_REG_298 */ "", 56247 /* MDB_REG_299 */ "", 56248 /* MDB_REG_303 */ "", 56249 /* MDB_REG_304 */ "", 56250 /* MDB_REG_305 */ "", 56251 /* MDB_REG_306 */ "", 56252 /* MDB_REG_310 */ "", 56253 /* MDB_REG_311 */ "", 56254 /* MDB_REG_312 */ "", 56255 /* MDB_REG_313 */ "", 56256 /* MDB_REG_314 */ "", 56257 /* MDB_REG_315 */ "", 56258 /* MDB_REG_316 */ "", 56259 /* MDB_REG_317 */ "", 56260 /* MDB_REG_318 */ "", 56261 /* MDB_REG_319 */ "", 56262 /* MDB_REG_320 */ "", 56263 /* MDB_REG_321 */ "", 56264 /* MDB_REG_322 */ "", 56265 /* MDB_REG_323 */ "", 56266 /* MDB_REG_325 */ "", 56267 /* MDB_REG_326 */ "", 56268 /* MDB_REG_327 */ "", 56269 /* MDB_REG_329 */ "", 56270 /* MDB_REG_331 */ "", 56271 /* MDB_REG_332 */ "", 56272 /* MDB_REG_335 */ "", 56273 /* MDB_REG_337 */ "", 56274 /* MDB_REG_338 */ "", 56275 /* MDB_REG_339 */ "", 56276 /* MDB_REG_340 */ "", 56277 /* MDB_REG_343 */ "", 56278 /* MDB_REG_344 */ "", 56279 /* MDB_REG_345 */ "", 56280 /* MDB_REG_346 */ "", 56281 /* MDB_REG_348 */ "", 56282 /* MDB_REG_352 */ "", 56283 /* MDB_REG_354 */ "", 56284 /* MDB_REG_355 */ "", 56285 /* MDB_REG_356 */ "", 56286 /* MDB_REG_357 */ "", 56287 /* MDB_REG_358 */ "", 56288 /* MDB_REG_359 */ "", 56289 /* MDB_REG_360 */ "", 56290 /* MDB_REG_361 */ "", 56291 /* MDB_REG_362 */ "", 56292 /* MDB_REG_364 */ "", 56293 /* MDB_REG_365 */ "", 56294 /* MDB_REG_366 */ "", 56295 /* MDB_REG_370 */ "", 56296 /* MDB_REG_371 */ "", 56297 /* MDB_REG_372 */ "", 56298 /* MDB_REG_373 */ "", 56299 /* MDB_REG_374 */ "", 56300 /* MDB_REG_376 */ "", 56301 /* MDB_REG_377 */ "", 56302 /* MDB_REG_379 */ "", 56303 /* MDB_REG_380 */ "", 56304 /* MDB_REG_381 */ "", 56305 /* MDB_REG_382 */ "", 56306 /* MDB_REG_383 */ "", 56307 /* MDB_REG_385 */ "", 56308 /* MDB_REG_386 */ "", 56309 /* MDB_REG_389 */ "", 56310 /* MDB_REG_390 */ "", 56311 /* MDB_REG_391 */ "", 56312 /* MDB_REG_392 */ "", 56313 /* MDB_REG_394 */ "", 56314 /* MDB_REG_398 */ "", 56315 /* MDB_REG_400 */ "", 56316 /* MDB_REG_401 */ "", 56317 /* MDB_REG_402 */ "", 56318 /* MDB_REG_403 */ "", 56319 /* MDB_REG_404 */ "", 56320 /* MDB_REG_406 */ "", 56321 /* MDB_REG_407 */ "", 56322 /* MDB_REG_410 */ "", 56323 /* MDB_REG_412 */ "", 56324 /* MDB_REG_413 */ "", 56325 /* MDB_REG_415 */ "", 56326 /* MDB_REG_416 */ "", 56327 /* MDB_REG_417 */ "", 56328 /* MDB_REG_418 */ "", 56329 /* MDB_REG_419 */ "", 56330 /* MDB_REG_421 */ "", 56331 /* MDB_REG_422 */ "", 56332 /* MDB_REG_423 */ "", 56333 /* MDB_REG_424 */ "", 56334 /* MDB_REG_425 */ "", 56335 /* MDB_REG_426 */ "", 56336 /* MDB_REG_427 */ "", 56337 /* MDB_REG_428 */ "", 56338 /* MDB_REG_430 */ "", 56339 /* MDB_REG_433 */ "", 56340 /* MDB_REG_435 */ "", 56341 /* MDB_REG_436 */ "", 56342 /* MDB_REG_439 */ "", 56343 /* MDB_REG_440 */ "", 56344 /* MDB_REG_441 */ "", 56345 /* MDB_REG_447 */ "", 56346 /* MDB_REG_449 */ "", 56347 /* MDB_REG_450 */ "", 56348 /* MDB_REG_455 */ "", 56349 /* MDB_REG_456 */ "", 56350 /* MDB_REG_457 */ "", 56351 /* MDB_REG_458 */ "", 56352 /* MDB_REG_459 */ "", 56353 /* MDB_REG_460 */ "", 56354 /* MDB_REG_462 */ "", 56355 /* MDB_REG_463 */ "", 56356 /* MDB_REG_464 */ "", 56357 /* MDB_REG_466 */ "", 56358 /* MDB_REG_468 */ "", 56359 /* MDB_REG_470 */ "", 56360 /* MDB_REG_472 */ "", 56361 /* MDB_REG_474 */ "", 56362 /* MDB_REG_475 */ "", 56363 /* MDB_REG_476 */ "", 56364 /* MDB_REG_477 */ "", 56365 /* MDB_REG_478 */ "", 56366 /* MDB_REG_481 */ "", 56367 /* MDB_REG_483 */ "", 56368 /* MDB_REG_489 */ "", 56369 /* MDB_REG_496 */ "", 56370 /* MDB_REG_497 */ "", 56371 /* MDB_REG_498 */ "", 56372 /* MDB_REG_500 */ "", 56373 /* MDB_REG_501 */ "", 56374 /* MDB_REG_507 */ "", 56375 /* MDB_REG_508 */ "", 56376 /* MDB_REG_509 */ "", 56377 /* MDB_REG_510 */ "", 56378 /* MDB_REG_512 */ "", 56379 /* MDB_REG_513 */ "", 56380 /* MDB_REG_514 */ "", 56381 /* MDB_REG_515 */ "", 56382 /* MDB_REG_517 */ "", 56383 /* MDB_REG_519 */ "", 56384 /* MDB_REG_521 */ "", 56385 /* MDB_REG_525 */ "", 56386 /* MDB_REG_527 */ "", 56387 /* MDB_REG_528 */ "", 56388 /* MDB_REG_529 */ "", 56389 /* MDB_REG_530 */ "", 56390 /* MDB_REG_531 */ "", 56391 /* MDB_REG_533 */ "", 56392 /* MDB_REG_534 */ "", 56393 /* MDB_REG_536 */ "", 56394 /* MDB_REG_540 */ "", 56395 /* MDB_REG_541 */ "", 56396 /* MDB_REG_545 */ "", 56397 /* MDB_REG_547 */ "", 56398 /* MDB_REG_548 */ "", 56399 /* MDB_REG_549 */ "", 56400 /* MDB_REG_550 */ "", 56401 /* MDB_REG_551 */ "", 56402 /* MDB_REG_553 */ "", 56403 /* MDB_REG_554 */ "", 56404 /* MDB_REG_560 */ "", 56405 /* MDB_REG_562 */ "", 56406 /* MDB_REG_566 */ "", 56407 /* MDB_REG_567 */ "", 56408 /* MDB_REG_568 */ "", 56409 /* MDB_REG_570 */ "", 56410 /* MDB_REG_578 */ "", 56411 /* MDB_REG_580 */ "", 56412 /* MDB_REG_581 */ "", 56413 /* MDB_REG_587 */ "", 56414 /* MDB_REG_588 */ "", 56415 /* MDB_REG_592 */ "", 56416 /* MDB_REG_593 */ "", 56417 /* MDB_REG_594 */ "", 56418 /* MDB_REG_1000 */ "", 56419 /* MDB_REG_1002 */ "", 56420 /* MDB_REG_1003 */ "", 56421 /* MDB_REG_1004 */ "", 56422 /* MDB_REG_1005 */ "", 56423 /* MDB_REG_1006 */ "", 56424 /* MDB_REG_1007 */ "", 56425 /* MDB_REG_1008 */ "", 56426 /* MDB_REG_1009 */ "", 56427 /* MDB_REG_1010 */ "", 56428 /* MDB_REG_1011 */ "", 56429 /* MDB_REG_1012 */ "", 56430 /* MDB_REG_1013 */ "", 56431 /* MDB_REG_1014 */ "", 56432 /* MDB_REG_1015 */ "", 56433 /* MDB_REG_1016 */ "", 56434 /* MDB_REG_1017 */ "", 56435 /* MDB_REG_1018 */ "", 56436 /* MDB_REG_1019 */ "", 56437 /* MDB_REG_1020 */ "", 56438 /* MDB_REG_1021 */ "", 56439 /* MDB_REG_1022 */ "", 56440 /* MDB_REG_1023 */ "", 56441 /* MDB_REG_1024 */ "", 56442 /* MDB_REG_1025 */ "", 56443 /* MDB_REG_1026 */ "", 56444 /* MDB_REG_1027 */ "", 56445 /* MDB_REG_1028 */ "", 56446 /* MDB_REG_1029 */ "", 56447 /* MDB_REG_1030 */ "", 56448 /* MDB_REG_1031 */ "", 56449 /* MDB_REG_1032 */ "", 56450 /* MDB_REG_1033 */ "", 56451 /* MDB_REG_1034 */ "", 56452 /* MDB_REG_1035 */ "", 56453 /* MDB_REG_1036 */ "", 56454 /* MDB_REG_1037 */ "", 56455 /* MDB_REG_1038 */ "", 56456 /* MDB_REG_1039 */ "", 56457 /* MDB_REG_1047 */ "", 56458 /* MDB_REG_1048 */ "", 56459 /* MDB_REG_1049 */ "", 56460 /* MDB_REG_1050 */ "", 56461 /* MDB_REG_1051 */ "", 56462 /* MDB_REG_1052 */ "", 56463 /* MDB_REG_1060 */ "", 56464 /* MDB_REG_1061 */ "", 56465 /* MDB_REG_1062 */ "", 56466 /* MDB_REG_1063 */ "", 56467 /* MDB_REG_1064 */ "", 56468 /* MDB_REG_1065 */ "", 56469 /* MDB_REG_1073 */ "", 56470 /* MDB_REG_1074 */ "", 56471 /* MDB_REG_1075 */ "", 56472 /* MDB_REG_1076 */ "", 56473 /* MDB_REG_1077 */ "", 56474 /* MDB_REG_1078 */ "", 56475 /* MDB_REG_1079 */ "", 56476 /* MDB_REG_1080 */ "", 56477 /* MDB_REG_1089 */ "", 56478 /* MDB_REG_1090 */ "", 56479 /* MDB_REG_1091 */ "", 56480 /* MDB_REG_1092 */ "", 56481 /* MDB_REG_1093 */ "", 56482 /* MDB_REG_1094 */ "", 56483 /* MDB_REG_1103 */ "", 56484 /* MDB_REG_1104 */ "", 56485 /* MDB_REG_1105 */ "", 56486 /* MDB_REG_1106 */ "", 56487 /* MDB_REG_1107 */ "", 56488 /* MDB_REG_1108 */ "", 56489 /* MDB_REG_1113 */ "", 56490 /* MDB_REG_1114 */ "", 56491 /* MDB_REG_1115 */ "", 56492 /* MDB_REG_1116 */ "", 56493 /* MDB_REG_1117 */ "", 56494 /* MDB_REG_1118 */ "", 56495 /* MDB_REG_1127 */ "", 56496 /* MDB_REG_1128 */ "", 56497 /* MDB_REG_1129 */ "", 56498 /* MDB_REG_1130 */ "", 56499 /* MDB_REG_1131 */ "", 56500 /* MDB_REG_1132 */ "", 56501 /* MDB_REG_1134 */ "", 56502 /* MDB_REG_1135 */ "", 56503 /* MDB_REG_1136 */ "", 56504 /* MDB_REG_1137 */ "", 56505 /* MDB_REG_1138 */ "", 56506 /* MDB_REG_1139 */ "", 56507 /* MDB_REG_1142 */ "", 56508 /* MDB_REG_1143 */ "", 56509 /* MDB_REG_1144 */ "", 56510 /* MDB_REG_1145 */ "", 56511 /* MDB_REG_1146 */ "", 56512 /* MDB_REG_1147 */ "", 56513 /* MDB_REG_1150 */ "", 56514 /* MDB_REG_1151 */ "", 56515 /* MDB_REG_1152 */ "", 56516 /* MDB_REG_1153 */ "", 56517 /* MDB_REG_1154 */ "", 56518 /* MDB_REG_1155 */ "", 56519 /* MDB_REG_1158 */ "", 56520 /* MDB_REG_1159 */ "", 56521 /* MDB_REG_1160 */ "", 56522 /* MDB_REG_1161 */ "", 56523 /* MDB_REG_1162 */ "", 56524 /* MDB_REG_1163 */ "", 56525 /* MDB_REG_1166 */ "", 56526 /* MDB_REG_1167 */ "", 56527 /* MDB_REG_1168 */ "", 56528 /* MDB_REG_1169 */ "", 56529 /* MDB_REG_1170 */ "", 56530 /* MDB_REG_2000 */ "", 56531 /* MDB_REG_2001 */ "", 56532 /* MDB_REG_2002 */ "", 56533 /* MDB_REG_2004 */ "", 56534 /* MDB_REG_2005 */ "", 56535 /* MDB_REG_2007 */ "", 56536 /* MDB_REG_2008 */ "", 56537 /* MDB_REG_2010 */ "", 56538 /* MDB_REG_2011 */ "", 56539 /* MDB_REG_2013 */ "", 56540 /* MDB_REG_2014 */ "", 56541 /* MDB_REG_2015 */ "", 56542 /* MDB_REG_2016 */ "", 56543 /* MDB_REG_2018 */ "", 56544 /* MDB_REG_2019 */ "", 56545 /* MDB_REG_2021 */ "", 56546 /* MDB_REG_2022 */ "", 56547 /* MDB_REG_2024 */ "", 56548 /* MDB_REG_2025 */ "", 56549 /* MDB_REG_2027 */ "", 56550 /* MDB_REG_3000 */ "", 56551 /* MDB_REG_3002 */ "", 56552 /* MDB_REG_3004 */ "", 56553 /* MDB_REG_3005 */ "", 56554 /* MDB_REG_3011 */ "", 56555 /* MDB_REG_3012 */ "", 56556 /* MDB_REG_3018 */ "", 56557 /* MDB_REG_3019 */ "", 56558 /* MDB_REG_3020 */ "", 56559 /* MDB_REG_3021 */ "", 56560 /* MDB_REG_3022 */ "", 56561 /* MDB_REG_3023 */ "", 56562 /* MDB_REG_5000 */ "", 56563 /* MDB_REG_5001 */ "", 56564 /* MDB_REG_5005 */ "", 56565 /* MDB_REG_5006 */ "", 56566 /* MDB_REG_5007 */ "", 56567 /* MDB_REG_5008 */ "", 56568 /* MDB_REG_5009 */ "", 56569 /* MDB_REG_00A4 */ "", 56570 /* MDB_REG_00A6 */ "", 56571 /* MDB_REG_00AA */ "", 56572 /* MDB_REG_00C2 */ "", 56573 /* MDB_REG_00F0 */ "", 56574 /* MDB_REG_300B */ "", 56575 /* MDB_REG_300C */ "", 56576 /* MDB_REG_300D */ "", 56577 /* MDB_REG_300F */ "", 56578 /* MDB_REG_301A */ "", 56579 /* MDB_REG_500A */ "", 56580 /* MDB_REG_500C */ "", 56581 /* MDB_REG_500D */ "", 56582 /* MDB_RESERVED_MIRROR_ADDR */ "", 56583 /* MDB_RESERVED_MTCD */ "", 56584 /* MDB_RESERVED_MTCP */ "", 56585 /* MDB_RESERVED_SPARE_0 */ "", 56586 /* MDB_RESERVED_SPARE_1 */ "", 56587 /* MDB_RESERVED_SPARE_2 */ "", 56588 /* MDB_RESERVED_SPARE_3 */ "", 56589 /* MDB_SBUS_BROADCAST_ID */ "", 56590 /* MDB_SBUS_LAST_IN_CHAIN */ "", 56591 /* MDB_SPECIAL_CLOCK_CONTROLS */ "", 56592 /* MEM0_DEBUG */ "", 56593 /* MEM1_IPMCGRP_TBL_PARITYERRORPTR */ "", 56594 /* MEM1_IPMCGRP_TBL_PARITYERROR_STATUS */ "", 56595 /* MEM1_IPMCVLAN_TBL_PARITYERRORPTR */ "", 56596 /* MEM1_IPMCVLAN_TBL_PARITYERROR_STATUS */ "", 56597 /* MEMFAILINTMASK */ "", 56598 /* MEMFAILINTSTATUS */ "", 56599 /* MEMFAILINT_CLR */ "", 56600 /* MEMORY_TM_0 */ "", 56601 /* MEMORY_TM_1 */ "", 56602 /* MEMPDACTR */ "", 56603 /* MEM_CORRUPT_CTL_BITMAP */ "", 56604 /* MEM_CTRL_0 */ "", 56605 /* MEM_ERR_CNT0 */ "", 56606 /* MEM_FAIL_INT_CLEAR */ "MEM_FAIL_INT_CLEAR", 56607 /* MEM_FAIL_INT_CTR */ "", 56608 /* MEM_FAIL_INT_EN */ "MEM_FAIL_INT_EN", 56609 /* MEM_FAIL_INT_EN_64 */ "MEM_FAIL_INT_EN", 56610 /* MEM_FAIL_INT_STAT */ "MEM_FAIL_INT_STAT", 56611 /* MEM_FAIL_INT_STAT_64 */ "MEM_FAIL_INT_STAT", 56612 /* MEM_SER_FIFO_STS */ "", 56613 /* MESH_TOPOLOGY_AUTO_DOC_NAME_4 */ "", 56614 /* MESH_TOPOLOGY_AUTO_DOC_NAME_9 */ "", 56615 /* MESH_TOPOLOGY_AUTO_DOC_NAME_11 */ "", 56616 /* MESH_TOPOLOGY_AUTO_DOC_NAME_14 */ "", 56617 /* MESH_TOPOLOGY_AUTO_DOC_NAME_16 */ "", 56618 /* MESH_TOPOLOGY_AUTO_DOC_NAME_18 */ "", 56619 /* MESH_TOPOLOGY_AUTO_DOC_NAME_20 */ "", 56620 /* MESH_TOPOLOGY_AUTO_DOC_NAME_22 */ "", 56621 /* MESH_TOPOLOGY_AUTO_DOC_NAME_24 */ "", 56622 /* MESH_TOPOLOGY_AUTO_DOC_NAME_26 */ "", 56623 /* MESH_TOPOLOGY_AUTO_DOC_NAME_30 */ "", 56624 /* MESH_TOPOLOGY_AUTO_DOC_NAME_32 */ "", 56625 /* MESH_TOPOLOGY_AUTO_DOC_NAME_34 */ "", 56626 /* MESH_TOPOLOGY_AUTO_DOC_NAME_38 */ "", 56627 /* MESH_TOPOLOGY_AUTO_DOC_NAME_39 */ "", 56628 /* MESH_TOPOLOGY_AUTO_DOC_NAME_40 */ "", 56629 /* MESH_TOPOLOGY_AUTO_DOC_NAME_41 */ "", 56630 /* MESH_TOPOLOGY_AUTO_DOC_NAME_42 */ "", 56631 /* MESH_TOPOLOGY_AUTO_DOC_NAME_43 */ "", 56632 /* MESH_TOPOLOGY_AUTO_DOC_NAME_44 */ "", 56633 /* MESH_TOPOLOGY_AUTO_DOC_NAME_45 */ "", 56634 /* MESH_TOPOLOGY_AUTO_DOC_NAME_46 */ "", 56635 /* MESH_TOPOLOGY_AUTO_DOC_NAME_47 */ "", 56636 /* MESH_TOPOLOGY_AUTO_DOC_NAME_48 */ "", 56637 /* MESH_TOPOLOGY_AUTO_DOC_NAME_49 */ "", 56638 /* MESH_TOPOLOGY_AUTO_DOC_NAME_50 */ "", 56639 /* MESH_TOPOLOGY_AUTO_DOC_NAME_51 */ "", 56640 /* MESH_TOPOLOGY_AUTO_DOC_NAME_52 */ "", 56641 /* MESH_TOPOLOGY_AUTO_DOC_NAME_53 */ "", 56642 /* MESH_TOPOLOGY_AUTO_DOC_NAME_54 */ "", 56643 /* MESH_TOPOLOGY_AUTO_DOC_NAME_55 */ "", 56644 /* MESH_TOPOLOGY_AUTO_DOC_NAME_56 */ "", 56645 /* MESH_TOPOLOGY_AUTO_DOC_NAME_57 */ "", 56646 /* MESH_TOPOLOGY_AUTO_DOC_NAME_58 */ "", 56647 /* MESH_TOPOLOGY_AUTO_DOC_NAME_59 */ "", 56648 /* MESH_TOPOLOGY_AUTO_DOC_NAME_60 */ "", 56649 /* MESH_TOPOLOGY_AUTO_DOC_NAME_61 */ "", 56650 /* MESH_TOPOLOGY_AUTO_DOC_NAME_62 */ "", 56651 /* MESH_TOPOLOGY_AUTO_DOC_NAME_63 */ "", 56652 /* MESH_TOPOLOGY_AUTO_DOC_NAME_64 */ "", 56653 /* MESH_TOPOLOGY_AUTO_DOC_NAME_65 */ "", 56654 /* MESH_TOPOLOGY_AUTO_DOC_NAME_66 */ "", 56655 /* MESH_TOPOLOGY_AUTO_DOC_NAME_67 */ "", 56656 /* MESH_TOPOLOGY_AUTO_DOC_NAME_68 */ "", 56657 /* MESH_TOPOLOGY_AUTO_DOC_NAME_69 */ "", 56658 /* MESH_TOPOLOGY_AUTO_DOC_NAME_70 */ "", 56659 /* MESH_TOPOLOGY_AUTO_DOC_NAME_71 */ "", 56660 /* MESH_TOPOLOGY_AUTO_DOC_NAME_72 */ "", 56661 /* MESH_TOPOLOGY_AUTO_DOC_NAME_73 */ "", 56662 /* MESH_TOPOLOGY_AUTO_DOC_NAME_74 */ "", 56663 /* MESH_TOPOLOGY_AUTO_DOC_NAME_75 */ "", 56664 /* MESH_TOPOLOGY_AUTO_DOC_NAME_76 */ "", 56665 /* MESH_TOPOLOGY_AUTO_DOC_NAME_77 */ "", 56666 /* MESH_TOPOLOGY_AUTO_DOC_NAME_78 */ "", 56667 /* MESH_TOPOLOGY_AUTO_DOC_NAME_79 */ "", 56668 /* MESH_TOPOLOGY_AUTO_DOC_NAME_80 */ "", 56669 /* MESH_TOPOLOGY_AUTO_DOC_NAME_81 */ "", 56670 /* MESH_TOPOLOGY_AUTO_DOC_NAME_82 */ "", 56671 /* MESH_TOPOLOGY_AUTO_DOC_NAME_83 */ "", 56672 /* MESH_TOPOLOGY_AUTO_DOC_NAME_84 */ "", 56673 /* MESH_TOPOLOGY_AUTO_DOC_NAME_85 */ "", 56674 /* MESH_TOPOLOGY_AUTO_DOC_NAME_86 */ "", 56675 /* MESH_TOPOLOGY_AUTO_DOC_NAME_87 */ "", 56676 /* MESH_TOPOLOGY_AUTO_DOC_NAME_88 */ "", 56677 /* MESH_TOPOLOGY_AUTO_DOC_NAME_89 */ "", 56678 /* MESH_TOPOLOGY_AUTO_DOC_NAME_90 */ "", 56679 /* MESH_TOPOLOGY_AUTO_DOC_NAME_91 */ "", 56680 /* MESH_TOPOLOGY_AUTO_DOC_NAME_92 */ "", 56681 /* MESH_TOPOLOGY_AUTO_DOC_NAME_93 */ "", 56682 /* MESH_TOPOLOGY_AUTO_DOC_NAME_94 */ "", 56683 /* MESH_TOPOLOGY_AUTO_DOC_NAME_100 */ "", 56684 /* MESH_TOPOLOGY_AUTO_DOC_NAME_101 */ "", 56685 /* MESH_TOPOLOGY_AUTO_DOC_NAME_102 */ "", 56686 /* MESH_TOPOLOGY_AUTO_DOC_NAME_103 */ "", 56687 /* MESH_TOPOLOGY_AUTO_DOC_NAME_104 */ "", 56688 /* MESH_TOPOLOGY_AUTO_DOC_NAME_105 */ "", 56689 /* MESH_TOPOLOGY_AUTO_DOC_NAME_106 */ "", 56690 /* MESH_TOPOLOGY_AUTO_DOC_NAME_107 */ "", 56691 /* MESH_TOPOLOGY_AUTO_DOC_NAME_108 */ "", 56692 /* MESH_TOPOLOGY_AUTO_DOC_NAME_109 */ "", 56693 /* MESH_TOPOLOGY_AUTO_DOC_NAME_110 */ "", 56694 /* MESH_TOPOLOGY_AUTO_DOC_NAME_111 */ "", 56695 /* MESH_TOPOLOGY_ECC_INTERRUPT_REGISTER */ "", 56696 /* MESH_TOPOLOGY_ECC_INTERRUPT_REGISTER_MASK */ "", 56697 /* MESH_TOPOLOGY_ECC_INTERRUPT_REGISTER_TEST */ "", 56698 /* MESH_TOPOLOGY_FAP_DETECT_CTRL_CELLS_CNT */ "", 56699 /* MESH_TOPOLOGY_FE_GLOBAL_GENERAL_CFG_1 */ "", 56700 /* MESH_TOPOLOGY_FE_GLOBAL_GENERAL_CFG_2 */ "", 56701 /* MESH_TOPOLOGY_GLOBAL_GENERAL_CFG_1 */ "", 56702 /* MESH_TOPOLOGY_GLOBAL_GENERAL_CFG_2 */ "", 56703 /* MESH_TOPOLOGY_GLOBAL_GENERAL_FE_CFG_1 */ "", 56704 /* MESH_TOPOLOGY_GLOBAL_MEM_OPTIONS */ "", 56705 /* MESH_TOPOLOGY_GLOBAL_REG */ "", 56706 /* MESH_TOPOLOGY_GLOBAL_REG_1 */ "", 56707 /* MESH_TOPOLOGY_GTIMER_CONFIGURATION */ "", 56708 /* MESH_TOPOLOGY_GTIMER_CYCLE */ "", 56709 /* MESH_TOPOLOGY_GTIMER_TRIGGER */ "", 56710 /* MESH_TOPOLOGY_INIT */ "", 56711 /* MESH_TOPOLOGY_INTERNAL */ "", 56712 /* MESH_TOPOLOGY_INTERRUPT_MASK_REGISTER */ "", 56713 /* MESH_TOPOLOGY_INTERRUPT_REGISTER_TEST */ "", 56714 /* MESH_TOPOLOGY_MESH_INTERRUPTS */ "", 56715 /* MESH_TOPOLOGY_MESH_INTERRUPTS_MASKS */ "", 56716 /* MESH_TOPOLOGY_MESH_STATUSES */ "", 56717 /* MESH_TOPOLOGY_MESH_TOPOLOGY */ "", 56718 /* MESH_TOPOLOGY_MESH_TOPOLOGY_2 */ "", 56719 /* MESH_TOPOLOGY_MESH_TOPOLOGY_REG_0107 */ "", 56720 /* MESH_TOPOLOGY_MESH_TOPOLOGY_REG_0110 */ "", 56721 /* MESH_TOPOLOGY_REG_0000 */ "", 56722 /* MESH_TOPOLOGY_REG_0010 */ "", 56723 /* MESH_TOPOLOGY_REG_0018 */ "", 56724 /* MESH_TOPOLOGY_REG_50 */ "", 56725 /* MESH_TOPOLOGY_REG_51 */ "", 56726 /* MESH_TOPOLOGY_REG_52 */ "", 56727 /* MESH_TOPOLOGY_REG_53 */ "", 56728 /* MESH_TOPOLOGY_REG_0054 */ "", 56729 /* MESH_TOPOLOGY_REG_0058 */ "", 56730 /* MESH_TOPOLOGY_REG_86 */ "", 56731 /* MESH_TOPOLOGY_REG_88 */ "", 56732 /* MESH_TOPOLOGY_REG_0101 */ "", 56733 /* MESH_TOPOLOGY_REG_0102 */ "", 56734 /* MESH_TOPOLOGY_REG_0104 */ "", 56735 /* MESH_TOPOLOGY_REG_0105 */ "", 56736 /* MESH_TOPOLOGY_REG_0106 */ "", 56737 /* MESH_TOPOLOGY_REG_0107 */ "", 56738 /* MESH_TOPOLOGY_REG_0108 */ "", 56739 /* MESH_TOPOLOGY_REG_0109 */ "", 56740 /* MESH_TOPOLOGY_REG_0110 */ "", 56741 /* MESH_TOPOLOGY_REG_0111 */ "", 56742 /* MESH_TOPOLOGY_REG_0112 */ "", 56743 /* MESH_TOPOLOGY_REG_0113 */ "", 56744 /* MESH_TOPOLOGY_REG_0114 */ "", 56745 /* MESH_TOPOLOGY_REG_0115 */ "", 56746 /* MESH_TOPOLOGY_REG_0116 */ "", 56747 /* MESH_TOPOLOGY_REG_0117 */ "", 56748 /* MESH_TOPOLOGY_REG_0118 */ "", 56749 /* MESH_TOPOLOGY_REG_00C4 */ "", 56750 /* MESH_TOPOLOGY_REG_010A */ "", 56751 /* MESH_TOPOLOGY_REG_010B */ "", 56752 /* MESH_TOPOLOGY_REG_010C */ "", 56753 /* MESH_TOPOLOGY_REG_010D */ "", 56754 /* MESH_TOPOLOGY_REG_010E */ "", 56755 /* MESH_TOPOLOGY_REG_010F */ "", 56756 /* MESH_TOPOLOGY_REG_011B */ "", 56757 /* MESH_TOPOLOGY_REG_01A0 */ "", 56758 /* MESH_TOPOLOGY_REG_01A1 */ "", 56759 /* MESH_TOPOLOGY_REG_01A2 */ "", 56760 /* MESH_TOPOLOGY_REG_01A3 */ "", 56761 /* MESH_TOPOLOGY_REG_01A4 */ "", 56762 /* MESH_TOPOLOGY_REG_01A5 */ "", 56763 /* MESH_TOPOLOGY_REG_01A6 */ "", 56764 /* MESH_TOPOLOGY_REG_01A7 */ "", 56765 /* MESH_TOPOLOGY_REG_01A8 */ "", 56766 /* MESH_TOPOLOGY_REG_01A9 */ "", 56767 /* MESH_TOPOLOGY_REG_01AA */ "", 56768 /* MESH_TOPOLOGY_REG_01AB */ "", 56769 /* MESH_TOPOLOGY_REG_01AC */ "", 56770 /* MESH_TOPOLOGY_REG_01AD */ "", 56771 /* MESH_TOPOLOGY_REG_01AE */ "", 56772 /* MESH_TOPOLOGY_REG_01AF */ "", 56773 /* MESH_TOPOLOGY_REG_01B0 */ "", 56774 /* MESH_TOPOLOGY_REG_01B1 */ "", 56775 /* MESH_TOPOLOGY_REG_01B2 */ "", 56776 /* MESH_TOPOLOGY_REG_01B3 */ "", 56777 /* MESH_TOPOLOGY_REG_01B4 */ "", 56778 /* MESH_TOPOLOGY_REG_01B5 */ "", 56779 /* MESH_TOPOLOGY_REG_01B6 */ "", 56780 /* MESH_TOPOLOGY_REG_01B7 */ "", 56781 /* MESH_TOPOLOGY_REG_01B8 */ "", 56782 /* MESH_TOPOLOGY_REG_01B9 */ "", 56783 /* MESH_TOPOLOGY_REG_01BA */ "", 56784 /* MESH_TOPOLOGY_REG_01BB */ "", 56785 /* MESH_TOPOLOGY_REG_01BC */ "", 56786 /* MESH_TOPOLOGY_REG_01BD */ "", 56787 /* MESH_TOPOLOGY_REG_01BE */ "", 56788 /* MESH_TOPOLOGY_REG_01BF */ "", 56789 /* MESH_TOPOLOGY_REG_01C0 */ "", 56790 /* MESH_TOPOLOGY_REG_01C1 */ "", 56791 /* MESH_TOPOLOGY_REG_01C2 */ "", 56792 /* MESH_TOPOLOGY_REG_01C3 */ "", 56793 /* MESH_TOPOLOGY_REG_01C4 */ "", 56794 /* MESH_TOPOLOGY_REG_01C5 */ "", 56795 /* MESH_TOPOLOGY_REG_01C6 */ "", 56796 /* MESH_TOPOLOGY_REG_01C7 */ "", 56797 /* MESH_TOPOLOGY_REG_01C8 */ "", 56798 /* MESH_TOPOLOGY_REG_01C9 */ "", 56799 /* MESH_TOPOLOGY_REG_01CA */ "", 56800 /* MESH_TOPOLOGY_REG_01CB */ "", 56801 /* MESH_TOPOLOGY_REG_01CC */ "", 56802 /* MESH_TOPOLOGY_REG_01CD */ "", 56803 /* MESH_TOPOLOGY_REG_01CE */ "", 56804 /* MESH_TOPOLOGY_REG_01CF */ "", 56805 /* MESH_TOPOLOGY_REG_01D0 */ "", 56806 /* MESH_TOPOLOGY_REG_01D1 */ "", 56807 /* MESH_TOPOLOGY_REG_01D2 */ "", 56808 /* MESH_TOPOLOGY_REG_01D3 */ "", 56809 /* MESH_TOPOLOGY_REG_01D4 */ "", 56810 /* MESH_TOPOLOGY_REG_01D5 */ "", 56811 /* MESH_TOPOLOGY_REG_01D6 */ "", 56812 /* MESH_TOPOLOGY_REG_01D7 */ "", 56813 /* MESH_TOPOLOGY_REG_01D8 */ "", 56814 /* MESH_TOPOLOGY_REG_01D9 */ "", 56815 /* MESH_TOPOLOGY_REG_01DA */ "", 56816 /* MESH_TOPOLOGY_REG_01DB */ "", 56817 /* MESH_TOPOLOGY_REG_01DC */ "", 56818 /* MESH_TOPOLOGY_REG_01DD */ "", 56819 /* MESH_TOPOLOGY_REG_01DE */ "", 56820 /* MESH_TOPOLOGY_REG_01E2 */ "", 56821 /* MESH_TOPOLOGY_REG_01E4 */ "", 56822 /* MESH_TOPOLOGY_REG_1A0 */ "", 56823 /* MESH_TOPOLOGY_REG_5A */ "", 56824 /* MESH_TOPOLOGY_REG_5B */ "", 56825 /* MESH_TOPOLOGY_RESERVED_MIRROR_ADDR */ "", 56826 /* MESH_TOPOLOGY_RESERVED_MTCP */ "", 56827 /* MESH_TOPOLOGY_RESERVED_SPARE_0 */ "", 56828 /* MESH_TOPOLOGY_RESERVED_SPARE_1 */ "", 56829 /* MESH_TOPOLOGY_RESERVED_SPARE_2 */ "", 56830 /* MESH_TOPOLOGY_RESERVED_SPARE_3 */ "", 56831 /* MESH_TOPOLOGY_SBUS_BROADCAST_ID */ "", 56832 /* MESH_TOPOLOGY_SBUS_LAST_IN_CHAIN */ "", 56833 /* MESH_TOPOLOGY_SPECIAL_CLOCK_CONTROLS */ "", 56834 /* MESH_TOPOLOGY_STATUS_1 */ "", 56835 /* MESH_TOPOLOGY_STATUS_2 */ "", 56836 /* MESH_TOPOLOGY_SYNC_MSG_RX_ADJ_FACTOR */ "", 56837 /* MESH_TOPOLOGY_SYS_CONFIG_0 */ "", 56838 /* MESH_TOPOLOGY_SYS_CONFIG_1 */ "", 56839 /* MESH_TOPOLOGY_SYS_CONFIG_2 */ "", 56840 /* MESH_TOPOLOGY_SYS_CONFIG_3 */ "", 56841 /* MESH_TOPOLOGY_THRESHOLDS */ "", 56842 /* METER_EGR_PORT_GRAN */ "", 56843 /* METER_EGR_PORT_GRAN_0 */ "", 56844 /* METER_EGR_PORT_GRAN_1 */ "", 56845 /* METER_EGR_PORT_GRAN_2 */ "", 56846 /* METER_ING_PORT_GRAN */ "", 56847 /* METER_ING_PORT_GRAN_0 */ "", 56848 /* METER_ING_PORT_GRAN_1 */ "", 56849 /* METER_ING_PORT_GRAN_2 */ "", 56850 /* METER_SOURCE_PRIORITY */ "", 56851 /* MGMT_FRAME_ENABLE */ "", 56852 /* MHOST_0_ARCACHE_REMAP */ "", 56853 /* MHOST_0_ARSHARE_REMAP */ "", 56854 /* MHOST_0_AWCACHE_REMAP */ "", 56855 /* MHOST_0_AWSHARE_REMAP */ "", 56856 /* MHOST_0_AXITP_M0_REGS_ATM_ADDRHIGH_0 */ "", 56857 /* MHOST_0_AXITP_M0_REGS_ATM_ADDRHIGH_1 */ "", 56858 /* MHOST_0_AXITP_M0_REGS_ATM_ADDRLOW_0 */ "", 56859 /* MHOST_0_AXITP_M0_REGS_ATM_ADDRLOW_1 */ "", 56860 /* MHOST_0_AXITP_M0_REGS_ATM_ARBUSY */ "", 56861 /* MHOST_0_AXITP_M0_REGS_ATM_ARCYCLES */ "", 56862 /* MHOST_0_AXITP_M0_REGS_ATM_AWBUSY */ "", 56863 /* MHOST_0_AXITP_M0_REGS_ATM_AWCYCLES */ "", 56864 /* MHOST_0_AXITP_M0_REGS_ATM_BBUSY */ "", 56865 /* MHOST_0_AXITP_M0_REGS_ATM_BCYCLES */ "", 56866 /* MHOST_0_AXITP_M0_REGS_ATM_CMD */ "", 56867 /* MHOST_0_AXITP_M0_REGS_ATM_CONFIG */ "", 56868 /* MHOST_0_AXITP_M0_REGS_ATM_FILTER_0 */ "", 56869 /* MHOST_0_AXITP_M0_REGS_ATM_FILTER_1 */ "", 56870 /* MHOST_0_AXITP_M0_REGS_ATM_OUTIDS */ "", 56871 /* MHOST_0_AXITP_M0_REGS_ATM_RBUSY */ "", 56872 /* MHOST_0_AXITP_M0_REGS_ATM_RCYCLES */ "", 56873 /* MHOST_0_AXITP_M0_REGS_ATM_RDBEATS */ "", 56874 /* MHOST_0_AXITP_M0_REGS_ATM_RDCMDS */ "", 56875 /* MHOST_0_AXITP_M0_REGS_ATM_RDMAX */ "", 56876 /* MHOST_0_AXITP_M0_REGS_ATM_RDMIN */ "", 56877 /* MHOST_0_AXITP_M0_REGS_ATM_RDOUTS */ "", 56878 /* MHOST_0_AXITP_M0_REGS_ATM_RDSUM */ "", 56879 /* MHOST_0_AXITP_M0_REGS_ATM_STATUS */ "", 56880 /* MHOST_0_AXITP_M0_REGS_ATM_WBUSY */ "", 56881 /* MHOST_0_AXITP_M0_REGS_ATM_WCYCLES */ "", 56882 /* MHOST_0_AXITP_M0_REGS_ATM_WRBEATS */ "", 56883 /* MHOST_0_AXITP_M0_REGS_ATM_WRCMDS */ "", 56884 /* MHOST_0_AXITP_M0_REGS_ATM_WRMAX */ "", 56885 /* MHOST_0_AXITP_M0_REGS_ATM_WRMIN */ "", 56886 /* MHOST_0_AXITP_M0_REGS_ATM_WROUTS */ "", 56887 /* MHOST_0_AXITP_M0_REGS_ATM_WRSUM */ "", 56888 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRHIGH_0 */ "", 56889 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRHIGH_1 */ "", 56890 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRLOW_0 */ "", 56891 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRLOW_1 */ "", 56892 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_ARBUSY */ "", 56893 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_ARCYCLES */ "", 56894 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_AWBUSY */ "", 56895 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_AWCYCLES */ "", 56896 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_BBUSY */ "", 56897 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_BCYCLES */ "", 56898 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_CMD */ "", 56899 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_CONFIG */ "", 56900 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_FILTER_0 */ "", 56901 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_FILTER_1 */ "", 56902 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_OUTIDS */ "", 56903 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RBUSY */ "", 56904 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RCYCLES */ "", 56905 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDBEATS */ "", 56906 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDCMDS */ "", 56907 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDMAX */ "", 56908 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDMIN */ "", 56909 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDOUTS */ "", 56910 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDSUM */ "", 56911 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_STATUS */ "", 56912 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WBUSY */ "", 56913 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WCYCLES */ "", 56914 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRBEATS */ "", 56915 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRCMDS */ "", 56916 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRMAX */ "", 56917 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRMIN */ "", 56918 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WROUTS */ "", 56919 /* MHOST_0_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRSUM */ "", 56920 /* MHOST_0_CR5_AXI_FATAL_ERR_STATUS */ "", 56921 /* MHOST_0_CR5_CFG_CTRL */ "", 56922 /* MHOST_0_CR5_EVENTI_CONTROL */ "", 56923 /* MHOST_0_CR5_EVENTO_STATUS */ "", 56924 /* MHOST_0_CR5_PPH_CFG_CTRL */ "", 56925 /* MHOST_0_CR5_PPV_CFG_CTRL */ "", 56926 /* MHOST_0_CR5_PPX_CFG_CTRL */ "", 56927 /* MHOST_0_CR5_RST_CTRL */ "", 56928 /* MHOST_0_CR5_STANDBY_STATUS */ "", 56929 /* MHOST_0_CSATBFUNNEL_AUTHSTATUS */ "", 56930 /* MHOST_0_CSATBFUNNEL_CLAIMCLR */ "", 56931 /* MHOST_0_CSATBFUNNEL_CLAIMSET */ "", 56932 /* MHOST_0_CSATBFUNNEL_COMPID0 */ "", 56933 /* MHOST_0_CSATBFUNNEL_COMPID1 */ "", 56934 /* MHOST_0_CSATBFUNNEL_COMPID2 */ "", 56935 /* MHOST_0_CSATBFUNNEL_COMPID3 */ "", 56936 /* MHOST_0_CSATBFUNNEL_CTRL_REG */ "", 56937 /* MHOST_0_CSATBFUNNEL_DEVID */ "", 56938 /* MHOST_0_CSATBFUNNEL_DEVTYPE */ "", 56939 /* MHOST_0_CSATBFUNNEL_ITATBCTR0 */ "", 56940 /* MHOST_0_CSATBFUNNEL_ITATBCTR1 */ "", 56941 /* MHOST_0_CSATBFUNNEL_ITATBCTR2 */ "", 56942 /* MHOST_0_CSATBFUNNEL_ITATBDATA0 */ "", 56943 /* MHOST_0_CSATBFUNNEL_ITCTRL */ "", 56944 /* MHOST_0_CSATBFUNNEL_LOCKACCESS */ "", 56945 /* MHOST_0_CSATBFUNNEL_LOCKSTATUS */ "", 56946 /* MHOST_0_CSATBFUNNEL_PERIPHID0 */ "", 56947 /* MHOST_0_CSATBFUNNEL_PERIPHID1 */ "", 56948 /* MHOST_0_CSATBFUNNEL_PERIPHID2 */ "", 56949 /* MHOST_0_CSATBFUNNEL_PERIPHID3 */ "", 56950 /* MHOST_0_CSATBFUNNEL_PERIPHID4 */ "", 56951 /* MHOST_0_CSATBFUNNEL_PRIORITY_CTRL_REG */ "", 56952 /* MHOST_0_CSCTI_ASICCTL */ "", 56953 /* MHOST_0_CSCTI_AUTHSTATUS */ "", 56954 /* MHOST_0_CSCTI_CLAIMCLR */ "", 56955 /* MHOST_0_CSCTI_CLAIMSET */ "", 56956 /* MHOST_0_CSCTI_COMPID0 */ "", 56957 /* MHOST_0_CSCTI_COMPID1 */ "", 56958 /* MHOST_0_CSCTI_COMPID2 */ "", 56959 /* MHOST_0_CSCTI_COMPID3 */ "", 56960 /* MHOST_0_CSCTI_CTIAPPCLEAR */ "", 56961 /* MHOST_0_CSCTI_CTIAPPPULSE */ "", 56962 /* MHOST_0_CSCTI_CTIAPPSET */ "", 56963 /* MHOST_0_CSCTI_CTICHINSTATUS */ "", 56964 /* MHOST_0_CSCTI_CTICHOUTSTATUS */ "", 56965 /* MHOST_0_CSCTI_CTICONTROL */ "", 56966 /* MHOST_0_CSCTI_CTIGATE */ "", 56967 /* MHOST_0_CSCTI_CTIINEN0 */ "", 56968 /* MHOST_0_CSCTI_CTIINEN1 */ "", 56969 /* MHOST_0_CSCTI_CTIINEN2 */ "", 56970 /* MHOST_0_CSCTI_CTIINEN3 */ "", 56971 /* MHOST_0_CSCTI_CTIINEN4 */ "", 56972 /* MHOST_0_CSCTI_CTIINEN5 */ "", 56973 /* MHOST_0_CSCTI_CTIINEN6 */ "", 56974 /* MHOST_0_CSCTI_CTIINEN7 */ "", 56975 /* MHOST_0_CSCTI_CTIINTACK */ "", 56976 /* MHOST_0_CSCTI_CTIOUTEN0 */ "", 56977 /* MHOST_0_CSCTI_CTIOUTEN1 */ "", 56978 /* MHOST_0_CSCTI_CTIOUTEN2 */ "", 56979 /* MHOST_0_CSCTI_CTIOUTEN3 */ "", 56980 /* MHOST_0_CSCTI_CTIOUTEN4 */ "", 56981 /* MHOST_0_CSCTI_CTIOUTEN5 */ "", 56982 /* MHOST_0_CSCTI_CTIOUTEN6 */ "", 56983 /* MHOST_0_CSCTI_CTIOUTEN7 */ "", 56984 /* MHOST_0_CSCTI_CTITRIGINSTATUS */ "", 56985 /* MHOST_0_CSCTI_CTITRIGOUTSTATUS */ "", 56986 /* MHOST_0_CSCTI_DEVID */ "", 56987 /* MHOST_0_CSCTI_DEVTYPE */ "", 56988 /* MHOST_0_CSCTI_ITCHIN */ "", 56989 /* MHOST_0_CSCTI_ITCHINACK */ "", 56990 /* MHOST_0_CSCTI_ITCHOUT */ "", 56991 /* MHOST_0_CSCTI_ITCHOUTACK */ "", 56992 /* MHOST_0_CSCTI_ITCTRL */ "", 56993 /* MHOST_0_CSCTI_ITTRIGIN */ "", 56994 /* MHOST_0_CSCTI_ITTRIGINACK */ "", 56995 /* MHOST_0_CSCTI_ITTRIGOUT */ "", 56996 /* MHOST_0_CSCTI_ITTRIGOUTACK */ "", 56997 /* MHOST_0_CSCTI_LAR */ "", 56998 /* MHOST_0_CSCTI_LSR */ "", 56999 /* MHOST_0_CSCTI_PERIPHID0 */ "", 57000 /* MHOST_0_CSCTI_PERIPHID1 */ "", 57001 /* MHOST_0_CSCTI_PERIPHID2 */ "", 57002 /* MHOST_0_CSCTI_PERIPHID3 */ "", 57003 /* MHOST_0_CSCTI_PERIPHID4 */ "", 57004 /* MHOST_0_EVENTBUS_ECC_ERR_INTR_ENABLE */ "", 57005 /* MHOST_0_EVENTBUS_ECC_ERR_INTR_STATUS */ "", 57006 /* MHOST_0_EVENTBUS_ECC_ERR_PIN22 */ "", 57007 /* MHOST_0_EVENTBUS_ECC_ERR_PIN23 */ "", 57008 /* MHOST_0_EVENTBUS_ECC_ERR_PIN24 */ "", 57009 /* MHOST_0_EVENTBUS_ECC_ERR_PIN25 */ "", 57010 /* MHOST_0_EVENTBUS_ECC_ERR_PIN26 */ "", 57011 /* MHOST_0_EVENTBUS_ECC_ERR_PIN27 */ "", 57012 /* MHOST_0_EVENTBUS_ECC_ERR_PIN33 */ "", 57013 /* MHOST_0_EVENTBUS_ECC_ERR_PIN34 */ "", 57014 /* MHOST_0_EVENTBUS_ECC_ERR_PIN37 */ "", 57015 /* MHOST_0_EVENTBUS_ECC_ERR_PIN38 */ "", 57016 /* MHOST_0_EVENTBUS_ECC_ERR_PIN39 */ "", 57017 /* MHOST_0_EVENTBUS_ECC_ERR_PIN40 */ "", 57018 /* MHOST_0_EVENTBUS_ECC_ERR_PIN41 */ "", 57019 /* MHOST_0_EVENTBUS_ECC_ERR_PIN42 */ "", 57020 /* MHOST_0_EVENTBUS_ECC_ERR_PIN43 */ "", 57021 /* MHOST_0_EVENTBUS_ECC_ERR_PIN44 */ "", 57022 /* MHOST_0_EVENTBUS_ECC_ERR_PIN45 */ "", 57023 /* MHOST_0_EVENTBUS_ECC_ERR_PIN46 */ "", 57024 /* MHOST_0_EVENTBUS_ECC_ERR_PIN47 */ "", 57025 /* MHOST_0_EVENTBUS_ECC_ERR_PIN48 */ "", 57026 /* MHOST_0_GICTR_REGS_GIC_CMD */ "", 57027 /* MHOST_0_GICTR_REGS_GIC_CONFIG */ "", 57028 /* MHOST_0_GICTR_REGS_GIC_FIQ_LAT0 */ "", 57029 /* MHOST_0_GICTR_REGS_GIC_FIQ_LAT1 */ "", 57030 /* MHOST_0_GICTR_REGS_GIC_IRQ_LAT0 */ "", 57031 /* MHOST_0_GICTR_REGS_GIC_IRQ_LAT1 */ "", 57032 /* MHOST_0_GICTR_REGS_GIC_OUTIDS */ "", 57033 /* MHOST_0_GICTR_REGS_GIC_STATUS */ "", 57034 /* MHOST_0_MEM_LVM_CTRL */ "", 57035 /* MHOST_0_MEM_TM_CTRL_0 */ "", 57036 /* MHOST_0_MEM_TM_CTRL_1 */ "", 57037 /* MHOST_0_MEM_TM_CTRL_2 */ "", 57038 /* MHOST_0_MEM_TM_CTRL_3 */ "", 57039 /* MHOST_0_MEM_TM_CTRL_4 */ "", 57040 /* MHOST_0_MEM_TM_CTRL_5 */ "", 57041 /* MHOST_0_MEM_TM_CTRL_6 */ "", 57042 /* MHOST_0_MEM_TM_CTRL_7 */ "", 57043 /* MHOST_0_MEM_TM_CTRL_8 */ "", 57044 /* MHOST_0_MEM_TM_CTRL_9 */ "", 57045 /* MHOST_0_MEM_TM_CTRL_10 */ "", 57046 /* MHOST_0_MEM_TM_CTRL_11 */ "", 57047 /* MHOST_0_MEM_TM_CTRL_12 */ "", 57048 /* MHOST_0_MEM_TM_CTRL_13 */ "", 57049 /* MHOST_0_MHOST_DEBUG_CTRL */ "", 57050 /* MHOST_0_MHOST_INTR_MASK_0 */ "", 57051 /* MHOST_0_MHOST_INTR_MASK_1 */ "", 57052 /* MHOST_0_MHOST_INTR_MASK_2 */ "", 57053 /* MHOST_0_MHOST_INTR_MASK_3 */ "", 57054 /* MHOST_0_MHOST_INTR_MASK_4 */ "", 57055 /* MHOST_0_MHOST_INTR_MASK_5 */ "", 57056 /* MHOST_0_MHOST_INTR_MASK_6 */ "", 57057 /* MHOST_0_MHOST_INTR_MASK_7 */ "", 57058 /* MHOST_0_MHOST_INTR_OUT */ "", 57059 /* MHOST_0_MHOST_INTR_STATUS_0 */ "", 57060 /* MHOST_0_MHOST_INTR_STATUS_1 */ "", 57061 /* MHOST_0_MHOST_INTR_STATUS_2 */ "", 57062 /* MHOST_0_MHOST_INTR_STATUS_3 */ "", 57063 /* MHOST_0_MHOST_INTR_STATUS_4 */ "", 57064 /* MHOST_0_MHOST_INTR_STATUS_5 */ "", 57065 /* MHOST_0_MHOST_INTR_STATUS_6 */ "", 57066 /* MHOST_0_MHOST_INTR_STATUS_7 */ "", 57067 /* MHOST_0_MHOST_RAW_INTR_STATUS_0 */ "", 57068 /* MHOST_0_MHOST_RAW_INTR_STATUS_1 */ "", 57069 /* MHOST_0_MHOST_RAW_INTR_STATUS_2 */ "", 57070 /* MHOST_0_MHOST_RAW_INTR_STATUS_3 */ "", 57071 /* MHOST_0_MHOST_RAW_INTR_STATUS_4 */ "", 57072 /* MHOST_0_MHOST_RAW_INTR_STATUS_5 */ "", 57073 /* MHOST_0_MHOST_RAW_INTR_STATUS_6 */ "", 57074 /* MHOST_0_MHOST_RAW_INTR_STATUS_7 */ "", 57075 /* MHOST_0_MHOST_STRAP_STATUS */ "", 57076 /* MHOST_0_PCIE64B_ACCESS_MSB_31TO24 */ "", 57077 /* MHOST_0_PCIE64B_ACCESS_MSB_63TO32 */ "", 57078 /* MHOST_0_SW_STM_REGS_R_CONFIG */ "", 57079 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN00 */ "", 57080 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN01 */ "", 57081 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN02 */ "", 57082 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN03 */ "", 57083 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN04 */ "", 57084 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN05 */ "", 57085 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN06 */ "", 57086 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN07 */ "", 57087 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN08 */ "", 57088 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN09 */ "", 57089 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN10 */ "", 57090 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN11 */ "", 57091 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN12 */ "", 57092 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN13 */ "", 57093 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN14 */ "", 57094 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN15 */ "", 57095 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN16 */ "", 57096 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN17 */ "", 57097 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN18 */ "", 57098 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN19 */ "", 57099 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN20 */ "", 57100 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN21 */ "", 57101 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN22 */ "", 57102 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN23 */ "", 57103 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN24 */ "", 57104 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN25 */ "", 57105 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN26 */ "", 57106 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN27 */ "", 57107 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN28 */ "", 57108 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN29 */ "", 57109 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN30 */ "", 57110 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN31 */ "", 57111 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN32 */ "", 57112 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN33 */ "", 57113 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN34 */ "", 57114 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN35 */ "", 57115 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN36 */ "", 57116 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN37 */ "", 57117 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN38 */ "", 57118 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN39 */ "", 57119 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN40 */ "", 57120 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN41 */ "", 57121 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN42 */ "", 57122 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN43 */ "", 57123 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN44 */ "", 57124 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN45 */ "", 57125 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN46 */ "", 57126 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN47 */ "", 57127 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN48 */ "", 57128 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN49 */ "", 57129 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN50 */ "", 57130 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN51 */ "", 57131 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN52 */ "", 57132 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN53 */ "", 57133 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN54 */ "", 57134 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN55 */ "", 57135 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN56 */ "", 57136 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN57 */ "", 57137 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN58 */ "", 57138 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN59 */ "", 57139 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN60 */ "", 57140 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN61 */ "", 57141 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN62 */ "", 57142 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN63 */ "", 57143 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN64 */ "", 57144 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN65 */ "", 57145 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN66 */ "", 57146 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN67 */ "", 57147 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN68 */ "", 57148 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN69 */ "", 57149 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN70 */ "", 57150 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN71 */ "", 57151 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN72 */ "", 57152 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN73 */ "", 57153 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN74 */ "", 57154 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN75 */ "", 57155 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN76 */ "", 57156 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN77 */ "", 57157 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN78 */ "", 57158 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN79 */ "", 57159 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN80 */ "", 57160 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN81 */ "", 57161 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN82 */ "", 57162 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN83 */ "", 57163 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN84 */ "", 57164 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN85 */ "", 57165 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN86 */ "", 57166 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN87 */ "", 57167 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN88 */ "", 57168 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN89 */ "", 57169 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN90 */ "", 57170 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN91 */ "", 57171 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN92 */ "", 57172 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN93 */ "", 57173 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN94 */ "", 57174 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN95 */ "", 57175 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN96 */ "", 57176 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN97 */ "", 57177 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN98 */ "", 57178 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN99 */ "", 57179 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN0A */ "", 57180 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN0B */ "", 57181 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN0C */ "", 57182 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN0D */ "", 57183 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN0E */ "", 57184 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN0F */ "", 57185 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN1A */ "", 57186 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN1B */ "", 57187 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN1C */ "", 57188 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN1D */ "", 57189 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN1E */ "", 57190 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN1F */ "", 57191 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN2A */ "", 57192 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN2B */ "", 57193 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN2C */ "", 57194 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN2D */ "", 57195 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN2E */ "", 57196 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN2F */ "", 57197 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN3A */ "", 57198 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN3B */ "", 57199 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN3C */ "", 57200 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN3D */ "", 57201 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN3E */ "", 57202 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN3F */ "", 57203 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN4A */ "", 57204 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN4B */ "", 57205 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN4C */ "", 57206 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN4D */ "", 57207 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN4E */ "", 57208 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN4F */ "", 57209 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN5A */ "", 57210 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN5B */ "", 57211 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN5C */ "", 57212 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN5D */ "", 57213 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN5E */ "", 57214 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN5F */ "", 57215 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN6A */ "", 57216 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN6B */ "", 57217 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN6C */ "", 57218 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN6D */ "", 57219 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN6E */ "", 57220 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN6F */ "", 57221 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN7A */ "", 57222 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN7B */ "", 57223 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN7C */ "", 57224 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN7D */ "", 57225 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN7E */ "", 57226 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN7F */ "", 57227 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN8A */ "", 57228 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN8B */ "", 57229 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN8C */ "", 57230 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN8D */ "", 57231 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN8E */ "", 57232 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN8F */ "", 57233 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN9A */ "", 57234 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN9B */ "", 57235 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN9C */ "", 57236 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN9D */ "", 57237 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN9E */ "", 57238 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAN9F */ "", 57239 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA0 */ "", 57240 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA1 */ "", 57241 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA2 */ "", 57242 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA3 */ "", 57243 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA4 */ "", 57244 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA5 */ "", 57245 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA6 */ "", 57246 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA7 */ "", 57247 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA8 */ "", 57248 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANA9 */ "", 57249 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANAA */ "", 57250 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANAB */ "", 57251 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANAC */ "", 57252 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANAD */ "", 57253 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANAE */ "", 57254 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANAF */ "", 57255 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB0 */ "", 57256 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB1 */ "", 57257 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB2 */ "", 57258 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB3 */ "", 57259 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB4 */ "", 57260 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB5 */ "", 57261 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB6 */ "", 57262 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB7 */ "", 57263 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB8 */ "", 57264 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANB9 */ "", 57265 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANBA */ "", 57266 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANBB */ "", 57267 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANBC */ "", 57268 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANBD */ "", 57269 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANBE */ "", 57270 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANBF */ "", 57271 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC0 */ "", 57272 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC1 */ "", 57273 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC2 */ "", 57274 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC3 */ "", 57275 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC4 */ "", 57276 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC5 */ "", 57277 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC6 */ "", 57278 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC7 */ "", 57279 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC8 */ "", 57280 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANC9 */ "", 57281 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANCA */ "", 57282 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANCB */ "", 57283 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANCC */ "", 57284 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANCD */ "", 57285 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANCE */ "", 57286 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANCF */ "", 57287 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND0 */ "", 57288 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND1 */ "", 57289 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND2 */ "", 57290 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND3 */ "", 57291 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND4 */ "", 57292 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND5 */ "", 57293 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND6 */ "", 57294 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND7 */ "", 57295 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND8 */ "", 57296 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHAND9 */ "", 57297 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANDA */ "", 57298 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANDB */ "", 57299 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANDC */ "", 57300 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANDD */ "", 57301 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANDE */ "", 57302 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANDF */ "", 57303 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE0 */ "", 57304 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE1 */ "", 57305 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE2 */ "", 57306 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE3 */ "", 57307 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE4 */ "", 57308 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE5 */ "", 57309 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE6 */ "", 57310 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE7 */ "", 57311 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE8 */ "", 57312 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANE9 */ "", 57313 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANEA */ "", 57314 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANEB */ "", 57315 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANEC */ "", 57316 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANED */ "", 57317 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANEE */ "", 57318 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANEF */ "", 57319 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF0 */ "", 57320 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF1 */ "", 57321 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF2 */ "", 57322 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF3 */ "", 57323 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF4 */ "", 57324 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF5 */ "", 57325 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF6 */ "", 57326 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF7 */ "", 57327 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF8 */ "", 57328 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANF9 */ "", 57329 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANFA */ "", 57330 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANFB */ "", 57331 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANFC */ "", 57332 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANFD */ "", 57333 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANFE */ "", 57334 /* MHOST_0_SW_STM_REGS_R_VAL_1BYTE_CHANFF */ "", 57335 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN00 */ "", 57336 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN01 */ "", 57337 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN02 */ "", 57338 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN03 */ "", 57339 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN04 */ "", 57340 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN05 */ "", 57341 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN06 */ "", 57342 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN07 */ "", 57343 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN08 */ "", 57344 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN09 */ "", 57345 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN10 */ "", 57346 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN11 */ "", 57347 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN12 */ "", 57348 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN13 */ "", 57349 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN14 */ "", 57350 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN15 */ "", 57351 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN16 */ "", 57352 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN17 */ "", 57353 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN18 */ "", 57354 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN19 */ "", 57355 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN20 */ "", 57356 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN21 */ "", 57357 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN22 */ "", 57358 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN23 */ "", 57359 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN24 */ "", 57360 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN25 */ "", 57361 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN26 */ "", 57362 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN27 */ "", 57363 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN28 */ "", 57364 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN29 */ "", 57365 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN30 */ "", 57366 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN31 */ "", 57367 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN32 */ "", 57368 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN33 */ "", 57369 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN34 */ "", 57370 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN35 */ "", 57371 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN36 */ "", 57372 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN37 */ "", 57373 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN38 */ "", 57374 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN39 */ "", 57375 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN40 */ "", 57376 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN41 */ "", 57377 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN42 */ "", 57378 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN43 */ "", 57379 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN44 */ "", 57380 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN45 */ "", 57381 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN46 */ "", 57382 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN47 */ "", 57383 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN48 */ "", 57384 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN49 */ "", 57385 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN50 */ "", 57386 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN51 */ "", 57387 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN52 */ "", 57388 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN53 */ "", 57389 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN54 */ "", 57390 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN55 */ "", 57391 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN56 */ "", 57392 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN57 */ "", 57393 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN58 */ "", 57394 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN59 */ "", 57395 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN60 */ "", 57396 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN61 */ "", 57397 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN62 */ "", 57398 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN63 */ "", 57399 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN64 */ "", 57400 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN65 */ "", 57401 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN66 */ "", 57402 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN67 */ "", 57403 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN68 */ "", 57404 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN69 */ "", 57405 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN70 */ "", 57406 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN71 */ "", 57407 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN72 */ "", 57408 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN73 */ "", 57409 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN74 */ "", 57410 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN75 */ "", 57411 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN76 */ "", 57412 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN77 */ "", 57413 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN78 */ "", 57414 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN79 */ "", 57415 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN80 */ "", 57416 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN81 */ "", 57417 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN82 */ "", 57418 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN83 */ "", 57419 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN84 */ "", 57420 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN85 */ "", 57421 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN86 */ "", 57422 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN87 */ "", 57423 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN88 */ "", 57424 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN89 */ "", 57425 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN90 */ "", 57426 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN91 */ "", 57427 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN92 */ "", 57428 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN93 */ "", 57429 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN94 */ "", 57430 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN95 */ "", 57431 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN96 */ "", 57432 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN97 */ "", 57433 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN98 */ "", 57434 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN99 */ "", 57435 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN0A */ "", 57436 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN0B */ "", 57437 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN0C */ "", 57438 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN0D */ "", 57439 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN0E */ "", 57440 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN0F */ "", 57441 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN1A */ "", 57442 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN1B */ "", 57443 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN1C */ "", 57444 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN1D */ "", 57445 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN1E */ "", 57446 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN1F */ "", 57447 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN2A */ "", 57448 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN2B */ "", 57449 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN2C */ "", 57450 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN2D */ "", 57451 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN2E */ "", 57452 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN2F */ "", 57453 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN3A */ "", 57454 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN3B */ "", 57455 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN3C */ "", 57456 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN3D */ "", 57457 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN3E */ "", 57458 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN3F */ "", 57459 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN4A */ "", 57460 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN4B */ "", 57461 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN4C */ "", 57462 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN4D */ "", 57463 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN4E */ "", 57464 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN4F */ "", 57465 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN5A */ "", 57466 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN5B */ "", 57467 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN5C */ "", 57468 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN5D */ "", 57469 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN5E */ "", 57470 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN5F */ "", 57471 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN6A */ "", 57472 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN6B */ "", 57473 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN6C */ "", 57474 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN6D */ "", 57475 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN6E */ "", 57476 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN6F */ "", 57477 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN7A */ "", 57478 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN7B */ "", 57479 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN7C */ "", 57480 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN7D */ "", 57481 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN7E */ "", 57482 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN7F */ "", 57483 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN8A */ "", 57484 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN8B */ "", 57485 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN8C */ "", 57486 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN8D */ "", 57487 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN8E */ "", 57488 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN8F */ "", 57489 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN9A */ "", 57490 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN9B */ "", 57491 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN9C */ "", 57492 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN9D */ "", 57493 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN9E */ "", 57494 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAN9F */ "", 57495 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA0 */ "", 57496 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA1 */ "", 57497 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA2 */ "", 57498 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA3 */ "", 57499 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA4 */ "", 57500 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA5 */ "", 57501 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA6 */ "", 57502 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA7 */ "", 57503 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA8 */ "", 57504 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANA9 */ "", 57505 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANAA */ "", 57506 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANAB */ "", 57507 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANAC */ "", 57508 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANAD */ "", 57509 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANAE */ "", 57510 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANAF */ "", 57511 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB0 */ "", 57512 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB1 */ "", 57513 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB2 */ "", 57514 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB3 */ "", 57515 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB4 */ "", 57516 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB5 */ "", 57517 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB6 */ "", 57518 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB7 */ "", 57519 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB8 */ "", 57520 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANB9 */ "", 57521 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANBA */ "", 57522 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANBB */ "", 57523 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANBC */ "", 57524 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANBD */ "", 57525 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANBE */ "", 57526 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANBF */ "", 57527 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC0 */ "", 57528 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC1 */ "", 57529 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC2 */ "", 57530 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC3 */ "", 57531 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC4 */ "", 57532 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC5 */ "", 57533 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC6 */ "", 57534 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC7 */ "", 57535 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC8 */ "", 57536 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANC9 */ "", 57537 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANCA */ "", 57538 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANCB */ "", 57539 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANCC */ "", 57540 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANCD */ "", 57541 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANCE */ "", 57542 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANCF */ "", 57543 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND0 */ "", 57544 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND1 */ "", 57545 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND2 */ "", 57546 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND3 */ "", 57547 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND4 */ "", 57548 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND5 */ "", 57549 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND6 */ "", 57550 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND7 */ "", 57551 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND8 */ "", 57552 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHAND9 */ "", 57553 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANDA */ "", 57554 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANDB */ "", 57555 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANDC */ "", 57556 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANDD */ "", 57557 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANDE */ "", 57558 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANDF */ "", 57559 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE0 */ "", 57560 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE1 */ "", 57561 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE2 */ "", 57562 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE3 */ "", 57563 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE4 */ "", 57564 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE5 */ "", 57565 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE6 */ "", 57566 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE7 */ "", 57567 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE8 */ "", 57568 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANE9 */ "", 57569 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANEA */ "", 57570 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANEB */ "", 57571 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANEC */ "", 57572 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANED */ "", 57573 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANEE */ "", 57574 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANEF */ "", 57575 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF0 */ "", 57576 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF1 */ "", 57577 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF2 */ "", 57578 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF3 */ "", 57579 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF4 */ "", 57580 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF5 */ "", 57581 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF6 */ "", 57582 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF7 */ "", 57583 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF8 */ "", 57584 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANF9 */ "", 57585 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANFA */ "", 57586 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANFB */ "", 57587 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANFC */ "", 57588 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANFD */ "", 57589 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANFE */ "", 57590 /* MHOST_0_SW_STM_REGS_R_VAL_2BYTE_CHANFF */ "", 57591 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN00 */ "", 57592 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN01 */ "", 57593 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN02 */ "", 57594 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN03 */ "", 57595 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN04 */ "", 57596 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN05 */ "", 57597 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN06 */ "", 57598 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN07 */ "", 57599 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN08 */ "", 57600 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN09 */ "", 57601 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN10 */ "", 57602 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN11 */ "", 57603 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN12 */ "", 57604 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN13 */ "", 57605 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN14 */ "", 57606 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN15 */ "", 57607 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN16 */ "", 57608 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN17 */ "", 57609 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN18 */ "", 57610 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN19 */ "", 57611 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN20 */ "", 57612 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN21 */ "", 57613 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN22 */ "", 57614 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN23 */ "", 57615 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN24 */ "", 57616 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN25 */ "", 57617 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN26 */ "", 57618 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN27 */ "", 57619 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN28 */ "", 57620 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN29 */ "", 57621 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN30 */ "", 57622 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN31 */ "", 57623 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN32 */ "", 57624 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN33 */ "", 57625 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN34 */ "", 57626 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN35 */ "", 57627 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN36 */ "", 57628 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN37 */ "", 57629 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN38 */ "", 57630 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN39 */ "", 57631 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN40 */ "", 57632 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN41 */ "", 57633 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN42 */ "", 57634 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN43 */ "", 57635 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN44 */ "", 57636 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN45 */ "", 57637 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN46 */ "", 57638 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN47 */ "", 57639 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN48 */ "", 57640 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN49 */ "", 57641 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN50 */ "", 57642 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN51 */ "", 57643 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN52 */ "", 57644 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN53 */ "", 57645 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN54 */ "", 57646 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN55 */ "", 57647 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN56 */ "", 57648 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN57 */ "", 57649 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN58 */ "", 57650 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN59 */ "", 57651 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN60 */ "", 57652 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN61 */ "", 57653 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN62 */ "", 57654 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN63 */ "", 57655 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN64 */ "", 57656 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN65 */ "", 57657 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN66 */ "", 57658 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN67 */ "", 57659 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN68 */ "", 57660 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN69 */ "", 57661 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN70 */ "", 57662 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN71 */ "", 57663 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN72 */ "", 57664 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN73 */ "", 57665 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN74 */ "", 57666 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN75 */ "", 57667 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN76 */ "", 57668 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN77 */ "", 57669 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN78 */ "", 57670 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN79 */ "", 57671 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN80 */ "", 57672 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN81 */ "", 57673 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN82 */ "", 57674 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN83 */ "", 57675 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN84 */ "", 57676 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN85 */ "", 57677 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN86 */ "", 57678 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN87 */ "", 57679 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN88 */ "", 57680 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN89 */ "", 57681 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN90 */ "", 57682 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN91 */ "", 57683 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN92 */ "", 57684 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN93 */ "", 57685 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN94 */ "", 57686 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN95 */ "", 57687 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN96 */ "", 57688 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN97 */ "", 57689 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN98 */ "", 57690 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN99 */ "", 57691 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN0A */ "", 57692 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN0B */ "", 57693 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN0C */ "", 57694 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN0D */ "", 57695 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN0E */ "", 57696 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN0F */ "", 57697 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN1A */ "", 57698 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN1B */ "", 57699 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN1C */ "", 57700 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN1D */ "", 57701 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN1E */ "", 57702 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN1F */ "", 57703 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN2A */ "", 57704 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN2B */ "", 57705 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN2C */ "", 57706 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN2D */ "", 57707 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN2E */ "", 57708 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN2F */ "", 57709 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN3A */ "", 57710 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN3B */ "", 57711 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN3C */ "", 57712 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN3D */ "", 57713 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN3E */ "", 57714 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN3F */ "", 57715 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN4A */ "", 57716 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN4B */ "", 57717 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN4C */ "", 57718 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN4D */ "", 57719 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN4E */ "", 57720 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN4F */ "", 57721 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN5A */ "", 57722 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN5B */ "", 57723 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN5C */ "", 57724 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN5D */ "", 57725 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN5E */ "", 57726 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN5F */ "", 57727 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN6A */ "", 57728 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN6B */ "", 57729 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN6C */ "", 57730 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN6D */ "", 57731 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN6E */ "", 57732 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN6F */ "", 57733 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN7A */ "", 57734 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN7B */ "", 57735 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN7C */ "", 57736 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN7D */ "", 57737 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN7E */ "", 57738 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN7F */ "", 57739 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN8A */ "", 57740 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN8B */ "", 57741 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN8C */ "", 57742 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN8D */ "", 57743 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN8E */ "", 57744 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN8F */ "", 57745 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN9A */ "", 57746 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN9B */ "", 57747 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN9C */ "", 57748 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN9D */ "", 57749 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN9E */ "", 57750 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAN9F */ "", 57751 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA0 */ "", 57752 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA1 */ "", 57753 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA2 */ "", 57754 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA3 */ "", 57755 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA4 */ "", 57756 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA5 */ "", 57757 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA6 */ "", 57758 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA7 */ "", 57759 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA8 */ "", 57760 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANA9 */ "", 57761 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANAA */ "", 57762 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANAB */ "", 57763 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANAC */ "", 57764 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANAD */ "", 57765 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANAE */ "", 57766 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANAF */ "", 57767 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB0 */ "", 57768 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB1 */ "", 57769 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB2 */ "", 57770 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB3 */ "", 57771 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB4 */ "", 57772 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB5 */ "", 57773 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB6 */ "", 57774 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB7 */ "", 57775 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB8 */ "", 57776 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANB9 */ "", 57777 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANBA */ "", 57778 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANBB */ "", 57779 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANBC */ "", 57780 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANBD */ "", 57781 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANBE */ "", 57782 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANBF */ "", 57783 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC0 */ "", 57784 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC1 */ "", 57785 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC2 */ "", 57786 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC3 */ "", 57787 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC4 */ "", 57788 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC5 */ "", 57789 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC6 */ "", 57790 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC7 */ "", 57791 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC8 */ "", 57792 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANC9 */ "", 57793 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANCA */ "", 57794 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANCB */ "", 57795 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANCC */ "", 57796 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANCD */ "", 57797 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANCE */ "", 57798 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANCF */ "", 57799 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND0 */ "", 57800 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND1 */ "", 57801 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND2 */ "", 57802 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND3 */ "", 57803 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND4 */ "", 57804 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND5 */ "", 57805 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND6 */ "", 57806 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND7 */ "", 57807 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND8 */ "", 57808 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHAND9 */ "", 57809 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANDA */ "", 57810 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANDB */ "", 57811 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANDC */ "", 57812 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANDD */ "", 57813 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANDE */ "", 57814 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANDF */ "", 57815 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE0 */ "", 57816 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE1 */ "", 57817 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE2 */ "", 57818 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE3 */ "", 57819 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE4 */ "", 57820 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE5 */ "", 57821 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE6 */ "", 57822 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE7 */ "", 57823 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE8 */ "", 57824 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANE9 */ "", 57825 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANEA */ "", 57826 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANEB */ "", 57827 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANEC */ "", 57828 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANED */ "", 57829 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANEE */ "", 57830 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANEF */ "", 57831 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF0 */ "", 57832 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF1 */ "", 57833 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF2 */ "", 57834 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF3 */ "", 57835 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF4 */ "", 57836 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF5 */ "", 57837 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF6 */ "", 57838 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF7 */ "", 57839 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF8 */ "", 57840 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANF9 */ "", 57841 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANFA */ "", 57842 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANFB */ "", 57843 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANFC */ "", 57844 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANFD */ "", 57845 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANFE */ "", 57846 /* MHOST_0_SW_STM_REGS_R_VAL_4BYTE_CHANFF */ "", 57847 /* MHOST_0_TRACE_GLB_ACK */ "", 57848 /* MHOST_0_TRACE_GLB_REQ_CMD */ "", 57849 /* MHOST_1_ARCACHE_REMAP */ "", 57850 /* MHOST_1_ARSHARE_REMAP */ "", 57851 /* MHOST_1_AWCACHE_REMAP */ "", 57852 /* MHOST_1_AWSHARE_REMAP */ "", 57853 /* MHOST_1_AXITP_M0_REGS_ATM_ADDRHIGH_0 */ "", 57854 /* MHOST_1_AXITP_M0_REGS_ATM_ADDRHIGH_1 */ "", 57855 /* MHOST_1_AXITP_M0_REGS_ATM_ADDRLOW_0 */ "", 57856 /* MHOST_1_AXITP_M0_REGS_ATM_ADDRLOW_1 */ "", 57857 /* MHOST_1_AXITP_M0_REGS_ATM_ARBUSY */ "", 57858 /* MHOST_1_AXITP_M0_REGS_ATM_ARCYCLES */ "", 57859 /* MHOST_1_AXITP_M0_REGS_ATM_AWBUSY */ "", 57860 /* MHOST_1_AXITP_M0_REGS_ATM_AWCYCLES */ "", 57861 /* MHOST_1_AXITP_M0_REGS_ATM_BBUSY */ "", 57862 /* MHOST_1_AXITP_M0_REGS_ATM_BCYCLES */ "", 57863 /* MHOST_1_AXITP_M0_REGS_ATM_CMD */ "", 57864 /* MHOST_1_AXITP_M0_REGS_ATM_CONFIG */ "", 57865 /* MHOST_1_AXITP_M0_REGS_ATM_FILTER_0 */ "", 57866 /* MHOST_1_AXITP_M0_REGS_ATM_FILTER_1 */ "", 57867 /* MHOST_1_AXITP_M0_REGS_ATM_OUTIDS */ "", 57868 /* MHOST_1_AXITP_M0_REGS_ATM_RBUSY */ "", 57869 /* MHOST_1_AXITP_M0_REGS_ATM_RCYCLES */ "", 57870 /* MHOST_1_AXITP_M0_REGS_ATM_RDBEATS */ "", 57871 /* MHOST_1_AXITP_M0_REGS_ATM_RDCMDS */ "", 57872 /* MHOST_1_AXITP_M0_REGS_ATM_RDMAX */ "", 57873 /* MHOST_1_AXITP_M0_REGS_ATM_RDMIN */ "", 57874 /* MHOST_1_AXITP_M0_REGS_ATM_RDOUTS */ "", 57875 /* MHOST_1_AXITP_M0_REGS_ATM_RDSUM */ "", 57876 /* MHOST_1_AXITP_M0_REGS_ATM_STATUS */ "", 57877 /* MHOST_1_AXITP_M0_REGS_ATM_WBUSY */ "", 57878 /* MHOST_1_AXITP_M0_REGS_ATM_WCYCLES */ "", 57879 /* MHOST_1_AXITP_M0_REGS_ATM_WRBEATS */ "", 57880 /* MHOST_1_AXITP_M0_REGS_ATM_WRCMDS */ "", 57881 /* MHOST_1_AXITP_M0_REGS_ATM_WRMAX */ "", 57882 /* MHOST_1_AXITP_M0_REGS_ATM_WRMIN */ "", 57883 /* MHOST_1_AXITP_M0_REGS_ATM_WROUTS */ "", 57884 /* MHOST_1_AXITP_M0_REGS_ATM_WRSUM */ "", 57885 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRHIGH_0 */ "", 57886 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRHIGH_1 */ "", 57887 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRLOW_0 */ "", 57888 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_ADDRLOW_1 */ "", 57889 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_ARBUSY */ "", 57890 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_ARCYCLES */ "", 57891 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_AWBUSY */ "", 57892 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_AWCYCLES */ "", 57893 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_BBUSY */ "", 57894 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_BCYCLES */ "", 57895 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_CMD */ "", 57896 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_CONFIG */ "", 57897 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_FILTER_0 */ "", 57898 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_FILTER_1 */ "", 57899 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_OUTIDS */ "", 57900 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RBUSY */ "", 57901 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RCYCLES */ "", 57902 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDBEATS */ "", 57903 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDCMDS */ "", 57904 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDMAX */ "", 57905 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDMIN */ "", 57906 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDOUTS */ "", 57907 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_RDSUM */ "", 57908 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_STATUS */ "", 57909 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WBUSY */ "", 57910 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WCYCLES */ "", 57911 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRBEATS */ "", 57912 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRCMDS */ "", 57913 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRMAX */ "", 57914 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRMIN */ "", 57915 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WROUTS */ "", 57916 /* MHOST_1_AXI_M_TRACE_AXITP_M0_REGS_ATM_WRSUM */ "", 57917 /* MHOST_1_CR5_AXI_FATAL_ERR_STATUS */ "", 57918 /* MHOST_1_CR5_CFG_CTRL */ "", 57919 /* MHOST_1_CR5_EVENTI_CONTROL */ "", 57920 /* MHOST_1_CR5_EVENTO_STATUS */ "", 57921 /* MHOST_1_CR5_PPH_CFG_CTRL */ "", 57922 /* MHOST_1_CR5_PPV_CFG_CTRL */ "", 57923 /* MHOST_1_CR5_PPX_CFG_CTRL */ "", 57924 /* MHOST_1_CR5_RST_CTRL */ "", 57925 /* MHOST_1_CR5_STANDBY_STATUS */ "", 57926 /* MHOST_1_CSATBFUNNEL_AUTHSTATUS */ "", 57927 /* MHOST_1_CSATBFUNNEL_CLAIMCLR */ "", 57928 /* MHOST_1_CSATBFUNNEL_CLAIMSET */ "", 57929 /* MHOST_1_CSATBFUNNEL_COMPID0 */ "", 57930 /* MHOST_1_CSATBFUNNEL_COMPID1 */ "", 57931 /* MHOST_1_CSATBFUNNEL_COMPID2 */ "", 57932 /* MHOST_1_CSATBFUNNEL_COMPID3 */ "", 57933 /* MHOST_1_CSATBFUNNEL_CTRL_REG */ "", 57934 /* MHOST_1_CSATBFUNNEL_DEVID */ "", 57935 /* MHOST_1_CSATBFUNNEL_DEVTYPE */ "", 57936 /* MHOST_1_CSATBFUNNEL_ITATBCTR0 */ "", 57937 /* MHOST_1_CSATBFUNNEL_ITATBCTR1 */ "", 57938 /* MHOST_1_CSATBFUNNEL_ITATBCTR2 */ "", 57939 /* MHOST_1_CSATBFUNNEL_ITATBDATA0 */ "", 57940 /* MHOST_1_CSATBFUNNEL_ITCTRL */ "", 57941 /* MHOST_1_CSATBFUNNEL_LOCKACCESS */ "", 57942 /* MHOST_1_CSATBFUNNEL_LOCKSTATUS */ "", 57943 /* MHOST_1_CSATBFUNNEL_PERIPHID0 */ "", 57944 /* MHOST_1_CSATBFUNNEL_PERIPHID1 */ "", 57945 /* MHOST_1_CSATBFUNNEL_PERIPHID2 */ "", 57946 /* MHOST_1_CSATBFUNNEL_PERIPHID3 */ "", 57947 /* MHOST_1_CSATBFUNNEL_PERIPHID4 */ "", 57948 /* MHOST_1_CSATBFUNNEL_PRIORITY_CTRL_REG */ "", 57949 /* MHOST_1_CSCTI_ASICCTL */ "", 57950 /* MHOST_1_CSCTI_AUTHSTATUS */ "", 57951 /* MHOST_1_CSCTI_CLAIMCLR */ "", 57952 /* MHOST_1_CSCTI_CLAIMSET */ "", 57953 /* MHOST_1_CSCTI_COMPID0 */ "", 57954 /* MHOST_1_CSCTI_COMPID1 */ "", 57955 /* MHOST_1_CSCTI_COMPID2 */ "", 57956 /* MHOST_1_CSCTI_COMPID3 */ "", 57957 /* MHOST_1_CSCTI_CTIAPPCLEAR */ "", 57958 /* MHOST_1_CSCTI_CTIAPPPULSE */ "", 57959 /* MHOST_1_CSCTI_CTIAPPSET */ "", 57960 /* MHOST_1_CSCTI_CTICHINSTATUS */ "", 57961 /* MHOST_1_CSCTI_CTICHOUTSTATUS */ "", 57962 /* MHOST_1_CSCTI_CTICONTROL */ "", 57963 /* MHOST_1_CSCTI_CTIGATE */ "", 57964 /* MHOST_1_CSCTI_CTIINEN0 */ "", 57965 /* MHOST_1_CSCTI_CTIINEN1 */ "", 57966 /* MHOST_1_CSCTI_CTIINEN2 */ "", 57967 /* MHOST_1_CSCTI_CTIINEN3 */ "", 57968 /* MHOST_1_CSCTI_CTIINEN4 */ "", 57969 /* MHOST_1_CSCTI_CTIINEN5 */ "", 57970 /* MHOST_1_CSCTI_CTIINEN6 */ "", 57971 /* MHOST_1_CSCTI_CTIINEN7 */ "", 57972 /* MHOST_1_CSCTI_CTIINTACK */ "", 57973 /* MHOST_1_CSCTI_CTIOUTEN0 */ "", 57974 /* MHOST_1_CSCTI_CTIOUTEN1 */ "", 57975 /* MHOST_1_CSCTI_CTIOUTEN2 */ "", 57976 /* MHOST_1_CSCTI_CTIOUTEN3 */ "", 57977 /* MHOST_1_CSCTI_CTIOUTEN4 */ "", 57978 /* MHOST_1_CSCTI_CTIOUTEN5 */ "", 57979 /* MHOST_1_CSCTI_CTIOUTEN6 */ "", 57980 /* MHOST_1_CSCTI_CTIOUTEN7 */ "", 57981 /* MHOST_1_CSCTI_CTITRIGINSTATUS */ "", 57982 /* MHOST_1_CSCTI_CTITRIGOUTSTATUS */ "", 57983 /* MHOST_1_CSCTI_DEVID */ "", 57984 /* MHOST_1_CSCTI_DEVTYPE */ "", 57985 /* MHOST_1_CSCTI_ITCHIN */ "", 57986 /* MHOST_1_CSCTI_ITCHINACK */ "", 57987 /* MHOST_1_CSCTI_ITCHOUT */ "", 57988 /* MHOST_1_CSCTI_ITCHOUTACK */ "", 57989 /* MHOST_1_CSCTI_ITCTRL */ "", 57990 /* MHOST_1_CSCTI_ITTRIGIN */ "", 57991 /* MHOST_1_CSCTI_ITTRIGINACK */ "", 57992 /* MHOST_1_CSCTI_ITTRIGOUT */ "", 57993 /* MHOST_1_CSCTI_ITTRIGOUTACK */ "", 57994 /* MHOST_1_CSCTI_LAR */ "", 57995 /* MHOST_1_CSCTI_LSR */ "", 57996 /* MHOST_1_CSCTI_PERIPHID0 */ "", 57997 /* MHOST_1_CSCTI_PERIPHID1 */ "", 57998 /* MHOST_1_CSCTI_PERIPHID2 */ "", 57999 /* MHOST_1_CSCTI_PERIPHID3 */ "", 58000 /* MHOST_1_CSCTI_PERIPHID4 */ "", 58001 /* MHOST_1_EVENTBUS_ECC_ERR_INTR_ENABLE */ "", 58002 /* MHOST_1_EVENTBUS_ECC_ERR_INTR_STATUS */ "", 58003 /* MHOST_1_EVENTBUS_ECC_ERR_PIN22 */ "", 58004 /* MHOST_1_EVENTBUS_ECC_ERR_PIN23 */ "", 58005 /* MHOST_1_EVENTBUS_ECC_ERR_PIN24 */ "", 58006 /* MHOST_1_EVENTBUS_ECC_ERR_PIN25 */ "", 58007 /* MHOST_1_EVENTBUS_ECC_ERR_PIN26 */ "", 58008 /* MHOST_1_EVENTBUS_ECC_ERR_PIN27 */ "", 58009 /* MHOST_1_EVENTBUS_ECC_ERR_PIN33 */ "", 58010 /* MHOST_1_EVENTBUS_ECC_ERR_PIN34 */ "", 58011 /* MHOST_1_EVENTBUS_ECC_ERR_PIN37 */ "", 58012 /* MHOST_1_EVENTBUS_ECC_ERR_PIN38 */ "", 58013 /* MHOST_1_EVENTBUS_ECC_ERR_PIN39 */ "", 58014 /* MHOST_1_EVENTBUS_ECC_ERR_PIN40 */ "", 58015 /* MHOST_1_EVENTBUS_ECC_ERR_PIN41 */ "", 58016 /* MHOST_1_EVENTBUS_ECC_ERR_PIN42 */ "", 58017 /* MHOST_1_EVENTBUS_ECC_ERR_PIN43 */ "", 58018 /* MHOST_1_EVENTBUS_ECC_ERR_PIN44 */ "", 58019 /* MHOST_1_EVENTBUS_ECC_ERR_PIN45 */ "", 58020 /* MHOST_1_EVENTBUS_ECC_ERR_PIN46 */ "", 58021 /* MHOST_1_EVENTBUS_ECC_ERR_PIN47 */ "", 58022 /* MHOST_1_EVENTBUS_ECC_ERR_PIN48 */ "", 58023 /* MHOST_1_GICTR_REGS_GIC_CMD */ "", 58024 /* MHOST_1_GICTR_REGS_GIC_CONFIG */ "", 58025 /* MHOST_1_GICTR_REGS_GIC_FIQ_LAT0 */ "", 58026 /* MHOST_1_GICTR_REGS_GIC_FIQ_LAT1 */ "", 58027 /* MHOST_1_GICTR_REGS_GIC_IRQ_LAT0 */ "", 58028 /* MHOST_1_GICTR_REGS_GIC_IRQ_LAT1 */ "", 58029 /* MHOST_1_GICTR_REGS_GIC_OUTIDS */ "", 58030 /* MHOST_1_GICTR_REGS_GIC_STATUS */ "", 58031 /* MHOST_1_MEM_LVM_CTRL */ "", 58032 /* MHOST_1_MEM_TM_CTRL_0 */ "", 58033 /* MHOST_1_MEM_TM_CTRL_1 */ "", 58034 /* MHOST_1_MEM_TM_CTRL_2 */ "", 58035 /* MHOST_1_MEM_TM_CTRL_3 */ "", 58036 /* MHOST_1_MEM_TM_CTRL_4 */ "", 58037 /* MHOST_1_MEM_TM_CTRL_5 */ "", 58038 /* MHOST_1_MEM_TM_CTRL_6 */ "", 58039 /* MHOST_1_MEM_TM_CTRL_7 */ "", 58040 /* MHOST_1_MEM_TM_CTRL_8 */ "", 58041 /* MHOST_1_MEM_TM_CTRL_9 */ "", 58042 /* MHOST_1_MEM_TM_CTRL_10 */ "", 58043 /* MHOST_1_MEM_TM_CTRL_11 */ "", 58044 /* MHOST_1_MEM_TM_CTRL_12 */ "", 58045 /* MHOST_1_MEM_TM_CTRL_13 */ "", 58046 /* MHOST_1_MHOST_DEBUG_CTRL */ "", 58047 /* MHOST_1_MHOST_INTR_MASK_0 */ "", 58048 /* MHOST_1_MHOST_INTR_MASK_1 */ "", 58049 /* MHOST_1_MHOST_INTR_MASK_2 */ "", 58050 /* MHOST_1_MHOST_INTR_MASK_3 */ "", 58051 /* MHOST_1_MHOST_INTR_MASK_4 */ "", 58052 /* MHOST_1_MHOST_INTR_MASK_5 */ "", 58053 /* MHOST_1_MHOST_INTR_MASK_6 */ "", 58054 /* MHOST_1_MHOST_INTR_MASK_7 */ "", 58055 /* MHOST_1_MHOST_INTR_OUT */ "", 58056 /* MHOST_1_MHOST_INTR_STATUS_0 */ "", 58057 /* MHOST_1_MHOST_INTR_STATUS_1 */ "", 58058 /* MHOST_1_MHOST_INTR_STATUS_2 */ "", 58059 /* MHOST_1_MHOST_INTR_STATUS_3 */ "", 58060 /* MHOST_1_MHOST_INTR_STATUS_4 */ "", 58061 /* MHOST_1_MHOST_INTR_STATUS_5 */ "", 58062 /* MHOST_1_MHOST_INTR_STATUS_6 */ "", 58063 /* MHOST_1_MHOST_INTR_STATUS_7 */ "", 58064 /* MHOST_1_MHOST_RAW_INTR_STATUS_0 */ "", 58065 /* MHOST_1_MHOST_RAW_INTR_STATUS_1 */ "", 58066 /* MHOST_1_MHOST_RAW_INTR_STATUS_2 */ "", 58067 /* MHOST_1_MHOST_RAW_INTR_STATUS_3 */ "", 58068 /* MHOST_1_MHOST_RAW_INTR_STATUS_4 */ "", 58069 /* MHOST_1_MHOST_RAW_INTR_STATUS_5 */ "", 58070 /* MHOST_1_MHOST_RAW_INTR_STATUS_6 */ "", 58071 /* MHOST_1_MHOST_RAW_INTR_STATUS_7 */ "", 58072 /* MHOST_1_MHOST_STRAP_STATUS */ "", 58073 /* MHOST_1_PCIE64B_ACCESS_MSB_31TO24 */ "", 58074 /* MHOST_1_PCIE64B_ACCESS_MSB_63TO32 */ "", 58075 /* MHOST_1_SW_STM_REGS_R_CONFIG */ "", 58076 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN00 */ "", 58077 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN01 */ "", 58078 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN02 */ "", 58079 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN03 */ "", 58080 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN04 */ "", 58081 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN05 */ "", 58082 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN06 */ "", 58083 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN07 */ "", 58084 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN08 */ "", 58085 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN09 */ "", 58086 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN10 */ "", 58087 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN11 */ "", 58088 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN12 */ "", 58089 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN13 */ "", 58090 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN14 */ "", 58091 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN15 */ "", 58092 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN16 */ "", 58093 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN17 */ "", 58094 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN18 */ "", 58095 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN19 */ "", 58096 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN20 */ "", 58097 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN21 */ "", 58098 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN22 */ "", 58099 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN23 */ "", 58100 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN24 */ "", 58101 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN25 */ "", 58102 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN26 */ "", 58103 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN27 */ "", 58104 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN28 */ "", 58105 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN29 */ "", 58106 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN30 */ "", 58107 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN31 */ "", 58108 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN32 */ "", 58109 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN33 */ "", 58110 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN34 */ "", 58111 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN35 */ "", 58112 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN36 */ "", 58113 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN37 */ "", 58114 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN38 */ "", 58115 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN39 */ "", 58116 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN40 */ "", 58117 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN41 */ "", 58118 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN42 */ "", 58119 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN43 */ "", 58120 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN44 */ "", 58121 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN45 */ "", 58122 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN46 */ "", 58123 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN47 */ "", 58124 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN48 */ "", 58125 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN49 */ "", 58126 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN50 */ "", 58127 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN51 */ "", 58128 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN52 */ "", 58129 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN53 */ "", 58130 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN54 */ "", 58131 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN55 */ "", 58132 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN56 */ "", 58133 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN57 */ "", 58134 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN58 */ "", 58135 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN59 */ "", 58136 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN60 */ "", 58137 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN61 */ "", 58138 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN62 */ "", 58139 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN63 */ "", 58140 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN64 */ "", 58141 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN65 */ "", 58142 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN66 */ "", 58143 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN67 */ "", 58144 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN68 */ "", 58145 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN69 */ "", 58146 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN70 */ "", 58147 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN71 */ "", 58148 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN72 */ "", 58149 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN73 */ "", 58150 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN74 */ "", 58151 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN75 */ "", 58152 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN76 */ "", 58153 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN77 */ "", 58154 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN78 */ "", 58155 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN79 */ "", 58156 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN80 */ "", 58157 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN81 */ "", 58158 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN82 */ "", 58159 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN83 */ "", 58160 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN84 */ "", 58161 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN85 */ "", 58162 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN86 */ "", 58163 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN87 */ "", 58164 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN88 */ "", 58165 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN89 */ "", 58166 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN90 */ "", 58167 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN91 */ "", 58168 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN92 */ "", 58169 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN93 */ "", 58170 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN94 */ "", 58171 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN95 */ "", 58172 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN96 */ "", 58173 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN97 */ "", 58174 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN98 */ "", 58175 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN99 */ "", 58176 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN0A */ "", 58177 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN0B */ "", 58178 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN0C */ "", 58179 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN0D */ "", 58180 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN0E */ "", 58181 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN0F */ "", 58182 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN1A */ "", 58183 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN1B */ "", 58184 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN1C */ "", 58185 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN1D */ "", 58186 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN1E */ "", 58187 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN1F */ "", 58188 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN2A */ "", 58189 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN2B */ "", 58190 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN2C */ "", 58191 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN2D */ "", 58192 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN2E */ "", 58193 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN2F */ "", 58194 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN3A */ "", 58195 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN3B */ "", 58196 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN3C */ "", 58197 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN3D */ "", 58198 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN3E */ "", 58199 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN3F */ "", 58200 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN4A */ "", 58201 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN4B */ "", 58202 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN4C */ "", 58203 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN4D */ "", 58204 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN4E */ "", 58205 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN4F */ "", 58206 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN5A */ "", 58207 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN5B */ "", 58208 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN5C */ "", 58209 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN5D */ "", 58210 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN5E */ "", 58211 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN5F */ "", 58212 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN6A */ "", 58213 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN6B */ "", 58214 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN6C */ "", 58215 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN6D */ "", 58216 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN6E */ "", 58217 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN6F */ "", 58218 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN7A */ "", 58219 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN7B */ "", 58220 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN7C */ "", 58221 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN7D */ "", 58222 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN7E */ "", 58223 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN7F */ "", 58224 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN8A */ "", 58225 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN8B */ "", 58226 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN8C */ "", 58227 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN8D */ "", 58228 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN8E */ "", 58229 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN8F */ "", 58230 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN9A */ "", 58231 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN9B */ "", 58232 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN9C */ "", 58233 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN9D */ "", 58234 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN9E */ "", 58235 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAN9F */ "", 58236 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA0 */ "", 58237 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA1 */ "", 58238 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA2 */ "", 58239 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA3 */ "", 58240 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA4 */ "", 58241 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA5 */ "", 58242 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA6 */ "", 58243 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA7 */ "", 58244 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA8 */ "", 58245 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANA9 */ "", 58246 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANAA */ "", 58247 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANAB */ "", 58248 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANAC */ "", 58249 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANAD */ "", 58250 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANAE */ "", 58251 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANAF */ "", 58252 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB0 */ "", 58253 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB1 */ "", 58254 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB2 */ "", 58255 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB3 */ "", 58256 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB4 */ "", 58257 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB5 */ "", 58258 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB6 */ "", 58259 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB7 */ "", 58260 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB8 */ "", 58261 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANB9 */ "", 58262 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANBA */ "", 58263 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANBB */ "", 58264 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANBC */ "", 58265 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANBD */ "", 58266 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANBE */ "", 58267 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANBF */ "", 58268 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC0 */ "", 58269 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC1 */ "", 58270 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC2 */ "", 58271 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC3 */ "", 58272 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC4 */ "", 58273 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC5 */ "", 58274 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC6 */ "", 58275 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC7 */ "", 58276 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC8 */ "", 58277 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANC9 */ "", 58278 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANCA */ "", 58279 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANCB */ "", 58280 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANCC */ "", 58281 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANCD */ "", 58282 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANCE */ "", 58283 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANCF */ "", 58284 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND0 */ "", 58285 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND1 */ "", 58286 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND2 */ "", 58287 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND3 */ "", 58288 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND4 */ "", 58289 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND5 */ "", 58290 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND6 */ "", 58291 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND7 */ "", 58292 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND8 */ "", 58293 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHAND9 */ "", 58294 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANDA */ "", 58295 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANDB */ "", 58296 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANDC */ "", 58297 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANDD */ "", 58298 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANDE */ "", 58299 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANDF */ "", 58300 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE0 */ "", 58301 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE1 */ "", 58302 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE2 */ "", 58303 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE3 */ "", 58304 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE4 */ "", 58305 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE5 */ "", 58306 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE6 */ "", 58307 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE7 */ "", 58308 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE8 */ "", 58309 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANE9 */ "", 58310 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANEA */ "", 58311 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANEB */ "", 58312 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANEC */ "", 58313 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANED */ "", 58314 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANEE */ "", 58315 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANEF */ "", 58316 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF0 */ "", 58317 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF1 */ "", 58318 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF2 */ "", 58319 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF3 */ "", 58320 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF4 */ "", 58321 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF5 */ "", 58322 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF6 */ "", 58323 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF7 */ "", 58324 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF8 */ "", 58325 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANF9 */ "", 58326 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANFA */ "", 58327 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANFB */ "", 58328 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANFC */ "", 58329 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANFD */ "", 58330 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANFE */ "", 58331 /* MHOST_1_SW_STM_REGS_R_VAL_1BYTE_CHANFF */ "", 58332 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN00 */ "", 58333 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN01 */ "", 58334 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN02 */ "", 58335 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN03 */ "", 58336 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN04 */ "", 58337 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN05 */ "", 58338 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN06 */ "", 58339 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN07 */ "", 58340 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN08 */ "", 58341 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN09 */ "", 58342 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN10 */ "", 58343 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN11 */ "", 58344 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN12 */ "", 58345 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN13 */ "", 58346 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN14 */ "", 58347 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN15 */ "", 58348 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN16 */ "", 58349 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN17 */ "", 58350 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN18 */ "", 58351 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN19 */ "", 58352 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN20 */ "", 58353 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN21 */ "", 58354 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN22 */ "", 58355 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN23 */ "", 58356 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN24 */ "", 58357 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN25 */ "", 58358 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN26 */ "", 58359 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN27 */ "", 58360 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN28 */ "", 58361 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN29 */ "", 58362 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN30 */ "", 58363 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN31 */ "", 58364 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN32 */ "", 58365 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN33 */ "", 58366 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN34 */ "", 58367 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN35 */ "", 58368 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN36 */ "", 58369 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN37 */ "", 58370 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN38 */ "", 58371 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN39 */ "", 58372 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN40 */ "", 58373 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN41 */ "", 58374 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN42 */ "", 58375 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN43 */ "", 58376 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN44 */ "", 58377 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN45 */ "", 58378 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN46 */ "", 58379 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN47 */ "", 58380 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN48 */ "", 58381 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN49 */ "", 58382 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN50 */ "", 58383 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN51 */ "", 58384 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN52 */ "", 58385 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN53 */ "", 58386 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN54 */ "", 58387 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN55 */ "", 58388 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN56 */ "", 58389 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN57 */ "", 58390 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN58 */ "", 58391 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN59 */ "", 58392 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN60 */ "", 58393 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN61 */ "", 58394 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN62 */ "", 58395 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN63 */ "", 58396 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN64 */ "", 58397 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN65 */ "", 58398 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN66 */ "", 58399 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN67 */ "", 58400 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN68 */ "", 58401 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN69 */ "", 58402 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN70 */ "", 58403 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN71 */ "", 58404 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN72 */ "", 58405 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN73 */ "", 58406 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN74 */ "", 58407 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN75 */ "", 58408 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN76 */ "", 58409 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN77 */ "", 58410 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN78 */ "", 58411 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN79 */ "", 58412 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN80 */ "", 58413 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN81 */ "", 58414 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN82 */ "", 58415 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN83 */ "", 58416 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN84 */ "", 58417 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN85 */ "", 58418 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN86 */ "", 58419 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN87 */ "", 58420 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN88 */ "", 58421 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN89 */ "", 58422 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN90 */ "", 58423 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN91 */ "", 58424 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN92 */ "", 58425 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN93 */ "", 58426 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN94 */ "", 58427 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN95 */ "", 58428 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN96 */ "", 58429 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN97 */ "", 58430 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN98 */ "", 58431 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN99 */ "", 58432 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN0A */ "", 58433 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN0B */ "", 58434 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN0C */ "", 58435 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN0D */ "", 58436 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN0E */ "", 58437 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN0F */ "", 58438 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN1A */ "", 58439 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN1B */ "", 58440 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN1C */ "", 58441 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN1D */ "", 58442 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN1E */ "", 58443 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN1F */ "", 58444 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN2A */ "", 58445 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN2B */ "", 58446 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN2C */ "", 58447 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN2D */ "", 58448 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN2E */ "", 58449 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN2F */ "", 58450 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN3A */ "", 58451 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN3B */ "", 58452 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN3C */ "", 58453 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN3D */ "", 58454 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN3E */ "", 58455 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN3F */ "", 58456 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN4A */ "", 58457 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN4B */ "", 58458 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN4C */ "", 58459 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN4D */ "", 58460 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN4E */ "", 58461 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN4F */ "", 58462 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN5A */ "", 58463 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN5B */ "", 58464 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN5C */ "", 58465 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN5D */ "", 58466 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN5E */ "", 58467 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN5F */ "", 58468 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN6A */ "", 58469 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN6B */ "", 58470 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN6C */ "", 58471 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN6D */ "", 58472 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN6E */ "", 58473 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN6F */ "", 58474 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN7A */ "", 58475 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN7B */ "", 58476 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN7C */ "", 58477 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN7D */ "", 58478 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN7E */ "", 58479 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN7F */ "", 58480 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN8A */ "", 58481 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN8B */ "", 58482 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN8C */ "", 58483 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN8D */ "", 58484 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN8E */ "", 58485 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN8F */ "", 58486 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN9A */ "", 58487 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN9B */ "", 58488 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN9C */ "", 58489 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN9D */ "", 58490 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN9E */ "", 58491 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAN9F */ "", 58492 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA0 */ "", 58493 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA1 */ "", 58494 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA2 */ "", 58495 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA3 */ "", 58496 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA4 */ "", 58497 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA5 */ "", 58498 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA6 */ "", 58499 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA7 */ "", 58500 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA8 */ "", 58501 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANA9 */ "", 58502 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANAA */ "", 58503 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANAB */ "", 58504 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANAC */ "", 58505 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANAD */ "", 58506 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANAE */ "", 58507 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANAF */ "", 58508 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB0 */ "", 58509 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB1 */ "", 58510 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB2 */ "", 58511 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB3 */ "", 58512 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB4 */ "", 58513 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB5 */ "", 58514 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB6 */ "", 58515 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB7 */ "", 58516 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB8 */ "", 58517 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANB9 */ "", 58518 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANBA */ "", 58519 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANBB */ "", 58520 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANBC */ "", 58521 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANBD */ "", 58522 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANBE */ "", 58523 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANBF */ "", 58524 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC0 */ "", 58525 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC1 */ "", 58526 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC2 */ "", 58527 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC3 */ "", 58528 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC4 */ "", 58529 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC5 */ "", 58530 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC6 */ "", 58531 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC7 */ "", 58532 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC8 */ "", 58533 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANC9 */ "", 58534 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANCA */ "", 58535 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANCB */ "", 58536 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANCC */ "", 58537 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANCD */ "", 58538 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANCE */ "", 58539 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANCF */ "", 58540 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND0 */ "", 58541 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND1 */ "", 58542 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND2 */ "", 58543 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND3 */ "", 58544 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND4 */ "", 58545 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND5 */ "", 58546 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND6 */ "", 58547 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND7 */ "", 58548 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND8 */ "", 58549 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHAND9 */ "", 58550 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANDA */ "", 58551 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANDB */ "", 58552 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANDC */ "", 58553 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANDD */ "", 58554 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANDE */ "", 58555 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANDF */ "", 58556 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE0 */ "", 58557 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE1 */ "", 58558 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE2 */ "", 58559 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE3 */ "", 58560 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE4 */ "", 58561 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE5 */ "", 58562 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE6 */ "", 58563 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE7 */ "", 58564 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE8 */ "", 58565 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANE9 */ "", 58566 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANEA */ "", 58567 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANEB */ "", 58568 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANEC */ "", 58569 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANED */ "", 58570 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANEE */ "", 58571 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANEF */ "", 58572 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF0 */ "", 58573 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF1 */ "", 58574 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF2 */ "", 58575 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF3 */ "", 58576 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF4 */ "", 58577 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF5 */ "", 58578 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF6 */ "", 58579 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF7 */ "", 58580 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF8 */ "", 58581 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANF9 */ "", 58582 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANFA */ "", 58583 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANFB */ "", 58584 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANFC */ "", 58585 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANFD */ "", 58586 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANFE */ "", 58587 /* MHOST_1_SW_STM_REGS_R_VAL_2BYTE_CHANFF */ "", 58588 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN00 */ "", 58589 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN01 */ "", 58590 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN02 */ "", 58591 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN03 */ "", 58592 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN04 */ "", 58593 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN05 */ "", 58594 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN06 */ "", 58595 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN07 */ "", 58596 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN08 */ "", 58597 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN09 */ "", 58598 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN10 */ "", 58599 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN11 */ "", 58600 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN12 */ "", 58601 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN13 */ "", 58602 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN14 */ "", 58603 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN15 */ "", 58604 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN16 */ "", 58605 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN17 */ "", 58606 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN18 */ "", 58607 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN19 */ "", 58608 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN20 */ "", 58609 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN21 */ "", 58610 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN22 */ "", 58611 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN23 */ "", 58612 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN24 */ "", 58613 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN25 */ "", 58614 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN26 */ "", 58615 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN27 */ "", 58616 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN28 */ "", 58617 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN29 */ "", 58618 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN30 */ "", 58619 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN31 */ "", 58620 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN32 */ "", 58621 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN33 */ "", 58622 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN34 */ "", 58623 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN35 */ "", 58624 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN36 */ "", 58625 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN37 */ "", 58626 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN38 */ "", 58627 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN39 */ "", 58628 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN40 */ "", 58629 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN41 */ "", 58630 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN42 */ "", 58631 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN43 */ "", 58632 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN44 */ "", 58633 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN45 */ "", 58634 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN46 */ "", 58635 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN47 */ "", 58636 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN48 */ "", 58637 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN49 */ "", 58638 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN50 */ "", 58639 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN51 */ "", 58640 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN52 */ "", 58641 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN53 */ "", 58642 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN54 */ "", 58643 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN55 */ "", 58644 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN56 */ "", 58645 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN57 */ "", 58646 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN58 */ "", 58647 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN59 */ "", 58648 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN60 */ "", 58649 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN61 */ "", 58650 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN62 */ "", 58651 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN63 */ "", 58652 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN64 */ "", 58653 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN65 */ "", 58654 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN66 */ "", 58655 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN67 */ "", 58656 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN68 */ "", 58657 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN69 */ "", 58658 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN70 */ "", 58659 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN71 */ "", 58660 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN72 */ "", 58661 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN73 */ "", 58662 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN74 */ "", 58663 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN75 */ "", 58664 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN76 */ "", 58665 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN77 */ "", 58666 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN78 */ "", 58667 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN79 */ "", 58668 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN80 */ "", 58669 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN81 */ "", 58670 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN82 */ "", 58671 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN83 */ "", 58672 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN84 */ "", 58673 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN85 */ "", 58674 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN86 */ "", 58675 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN87 */ "", 58676 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN88 */ "", 58677 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN89 */ "", 58678 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN90 */ "", 58679 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN91 */ "", 58680 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN92 */ "", 58681 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN93 */ "", 58682 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN94 */ "", 58683 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN95 */ "", 58684 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN96 */ "", 58685 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN97 */ "", 58686 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN98 */ "", 58687 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN99 */ "", 58688 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN0A */ "", 58689 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN0B */ "", 58690 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN0C */ "", 58691 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN0D */ "", 58692 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN0E */ "", 58693 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN0F */ "", 58694 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN1A */ "", 58695 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN1B */ "", 58696 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN1C */ "", 58697 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN1D */ "", 58698 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN1E */ "", 58699 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN1F */ "", 58700 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN2A */ "", 58701 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN2B */ "", 58702 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN2C */ "", 58703 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN2D */ "", 58704 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN2E */ "", 58705 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN2F */ "", 58706 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN3A */ "", 58707 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN3B */ "", 58708 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN3C */ "", 58709 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN3D */ "", 58710 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN3E */ "", 58711 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN3F */ "", 58712 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN4A */ "", 58713 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN4B */ "", 58714 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN4C */ "", 58715 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN4D */ "", 58716 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN4E */ "", 58717 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN4F */ "", 58718 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN5A */ "", 58719 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN5B */ "", 58720 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN5C */ "", 58721 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN5D */ "", 58722 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN5E */ "", 58723 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN5F */ "", 58724 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN6A */ "", 58725 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN6B */ "", 58726 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN6C */ "", 58727 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN6D */ "", 58728 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN6E */ "", 58729 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN6F */ "", 58730 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN7A */ "", 58731 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN7B */ "", 58732 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN7C */ "", 58733 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN7D */ "", 58734 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN7E */ "", 58735 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN7F */ "", 58736 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN8A */ "", 58737 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN8B */ "", 58738 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN8C */ "", 58739 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN8D */ "", 58740 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN8E */ "", 58741 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN8F */ "", 58742 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN9A */ "", 58743 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN9B */ "", 58744 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN9C */ "", 58745 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN9D */ "", 58746 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN9E */ "", 58747 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAN9F */ "", 58748 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA0 */ "", 58749 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA1 */ "", 58750 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA2 */ "", 58751 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA3 */ "", 58752 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA4 */ "", 58753 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA5 */ "", 58754 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA6 */ "", 58755 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA7 */ "", 58756 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA8 */ "", 58757 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANA9 */ "", 58758 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANAA */ "", 58759 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANAB */ "", 58760 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANAC */ "", 58761 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANAD */ "", 58762 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANAE */ "", 58763 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANAF */ "", 58764 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB0 */ "", 58765 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB1 */ "", 58766 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB2 */ "", 58767 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB3 */ "", 58768 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB4 */ "", 58769 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB5 */ "", 58770 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB6 */ "", 58771 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB7 */ "", 58772 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB8 */ "", 58773 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANB9 */ "", 58774 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANBA */ "", 58775 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANBB */ "", 58776 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANBC */ "", 58777 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANBD */ "", 58778 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANBE */ "", 58779 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANBF */ "", 58780 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC0 */ "", 58781 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC1 */ "", 58782 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC2 */ "", 58783 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC3 */ "", 58784 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC4 */ "", 58785 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC5 */ "", 58786 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC6 */ "", 58787 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC7 */ "", 58788 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC8 */ "", 58789 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANC9 */ "", 58790 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANCA */ "", 58791 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANCB */ "", 58792 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANCC */ "", 58793 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANCD */ "", 58794 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANCE */ "", 58795 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANCF */ "", 58796 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND0 */ "", 58797 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND1 */ "", 58798 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND2 */ "", 58799 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND3 */ "", 58800 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND4 */ "", 58801 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND5 */ "", 58802 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND6 */ "", 58803 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND7 */ "", 58804 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND8 */ "", 58805 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHAND9 */ "", 58806 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANDA */ "", 58807 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANDB */ "", 58808 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANDC */ "", 58809 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANDD */ "", 58810 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANDE */ "", 58811 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANDF */ "", 58812 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE0 */ "", 58813 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE1 */ "", 58814 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE2 */ "", 58815 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE3 */ "", 58816 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE4 */ "", 58817 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE5 */ "", 58818 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE6 */ "", 58819 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE7 */ "", 58820 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE8 */ "", 58821 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANE9 */ "", 58822 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANEA */ "", 58823 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANEB */ "", 58824 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANEC */ "", 58825 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANED */ "", 58826 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANEE */ "", 58827 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANEF */ "", 58828 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF0 */ "", 58829 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF1 */ "", 58830 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF2 */ "", 58831 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF3 */ "", 58832 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF4 */ "", 58833 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF5 */ "", 58834 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF6 */ "", 58835 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF7 */ "", 58836 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF8 */ "", 58837 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANF9 */ "", 58838 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANFA */ "", 58839 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANFB */ "", 58840 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANFC */ "", 58841 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANFD */ "", 58842 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANFE */ "", 58843 /* MHOST_1_SW_STM_REGS_R_VAL_4BYTE_CHANFF */ "", 58844 /* MHOST_1_TRACE_GLB_ACK */ "", 58845 /* MHOST_1_TRACE_GLB_REQ_CMD */ "", 58846 /* MHOST_M0_IDM_IDM_INTERRUPT_STATUS */ "", 58847 /* MHOST_M0_IDM_IDM_RESET_STATUS */ "", 58848 /* MHOST_M0_IDM_IO_CONTROL_DIRECT */ "", 58849 /* MHOST_M0_IDM_M_IDM_RESET_CONTROL */ "", 58850 /* MHOST_M1_IDM_IDM_INTERRUPT_STATUS */ "", 58851 /* MHOST_M1_IDM_IDM_RESET_STATUS */ "", 58852 /* MHOST_M1_IDM_IO_CONTROL_DIRECT */ "", 58853 /* MHOST_M1_IDM_M_IDM_RESET_CONTROL */ "", 58854 /* MHOST_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 58855 /* MHOST_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 58856 /* MHOST_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 58857 /* MHOST_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 58858 /* MHOST_S0_IDM_IDM_ERROR_LOG_ID */ "", 58859 /* MHOST_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 58860 /* MHOST_S0_IDM_IDM_INTERRUPT_STATUS */ "", 58861 /* MHOST_S0_IDM_IDM_RESET_READ_ID */ "", 58862 /* MHOST_S0_IDM_IDM_RESET_STATUS */ "", 58863 /* MHOST_S0_IDM_IDM_RESET_WRITE_ID */ "", 58864 /* MHOST_S0_IDM_S_IDM_RESET_CONTROL */ "", 58865 /* MHOST_S1_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 58866 /* MHOST_S1_IDM_IDM_ERROR_LOG_COMPLETE */ "", 58867 /* MHOST_S1_IDM_IDM_ERROR_LOG_CONTROL */ "", 58868 /* MHOST_S1_IDM_IDM_ERROR_LOG_FLAGS */ "", 58869 /* MHOST_S1_IDM_IDM_ERROR_LOG_ID */ "", 58870 /* MHOST_S1_IDM_IDM_ERROR_LOG_STATUS */ "", 58871 /* MHOST_S1_IDM_IDM_INTERRUPT_STATUS */ "", 58872 /* MHOST_S1_IDM_IDM_RESET_READ_ID */ "", 58873 /* MHOST_S1_IDM_IDM_RESET_STATUS */ "", 58874 /* MHOST_S1_IDM_IDM_RESET_WRITE_ID */ "", 58875 /* MHOST_S1_IDM_S_IDM_RESET_CONTROL */ "", 58876 /* MHOST_TIM_TIMER1BGLOAD */ "", 58877 /* MHOST_TIM_TIMER1CONTROL */ "", 58878 /* MHOST_TIM_TIMER1INTCLR */ "", 58879 /* MHOST_TIM_TIMER1LOAD */ "", 58880 /* MHOST_TIM_TIMER1MIS */ "", 58881 /* MHOST_TIM_TIMER1RIS */ "", 58882 /* MHOST_TIM_TIMER1VALUE */ "", 58883 /* MHOST_TIM_TIMER2BGLOAD */ "", 58884 /* MHOST_TIM_TIMER2CONTROL */ "", 58885 /* MHOST_TIM_TIMER2INTCLR */ "", 58886 /* MHOST_TIM_TIMER2LOAD */ "", 58887 /* MHOST_TIM_TIMER2MIS */ "", 58888 /* MHOST_TIM_TIMER2RIS */ "", 58889 /* MHOST_TIM_TIMER2VALUE */ "", 58890 /* MHOST_TIM_TIMERITCR */ "", 58891 /* MHOST_TIM_TIMERITOP */ "", 58892 /* MHOST_TIM_TIMERPCELLID0 */ "", 58893 /* MHOST_TIM_TIMERPCELLID1 */ "", 58894 /* MHOST_TIM_TIMERPCELLID2 */ "", 58895 /* MHOST_TIM_TIMERPCELLID3 */ "", 58896 /* MHOST_TIM_TIMERPERIPHID0 */ "", 58897 /* MHOST_TIM_TIMERPERIPHID1 */ "", 58898 /* MHOST_TIM_TIMERPERIPHID2 */ "", 58899 /* MHOST_TIM_TIMERPERIPHID3 */ "", 58900 /* MHOST_UART_CPR */ "", 58901 /* MHOST_UART_CTR */ "", 58902 /* MHOST_UART_DLH_IER */ "", 58903 /* MHOST_UART_DMASA */ "", 58904 /* MHOST_UART_FAR */ "", 58905 /* MHOST_UART_HTX */ "", 58906 /* MHOST_UART_IIR_FCR */ "", 58907 /* MHOST_UART_LCR */ "", 58908 /* MHOST_UART_LPDLH */ "", 58909 /* MHOST_UART_LPDLL */ "", 58910 /* MHOST_UART_LSR */ "", 58911 /* MHOST_UART_MCR */ "", 58912 /* MHOST_UART_MSR */ "", 58913 /* MHOST_UART_RBR_THR_DLL */ "", 58914 /* MHOST_UART_RFL */ "", 58915 /* MHOST_UART_RFW */ "", 58916 /* MHOST_UART_SBCR */ "", 58917 /* MHOST_UART_SCR */ "", 58918 /* MHOST_UART_SDMAM */ "", 58919 /* MHOST_UART_SFE */ "", 58920 /* MHOST_UART_SRBR_STHR */ "", 58921 /* MHOST_UART_SRR */ "", 58922 /* MHOST_UART_SRT */ "", 58923 /* MHOST_UART_SRTS */ "", 58924 /* MHOST_UART_STET */ "", 58925 /* MHOST_UART_TFL */ "", 58926 /* MHOST_UART_TFR */ "", 58927 /* MHOST_UART_UCV */ "", 58928 /* MHOST_UART_USR */ "", 58929 /* MHOST_VICADDRESS */ "", 58930 /* MHOST_VICFIQSTATUS */ "", 58931 /* MHOST_VICINTENABLE */ "", 58932 /* MHOST_VICINTENCLEAR */ "", 58933 /* MHOST_VICINTSELECT */ "", 58934 /* MHOST_VICIRQSTATUS */ "", 58935 /* MHOST_VICPCELLID0 */ "", 58936 /* MHOST_VICPCELLID1 */ "", 58937 /* MHOST_VICPCELLID2 */ "", 58938 /* MHOST_VICPCELLID3 */ "", 58939 /* MHOST_VICPERIPHID0 */ "", 58940 /* MHOST_VICPERIPHID1 */ "", 58941 /* MHOST_VICPERIPHID2 */ "", 58942 /* MHOST_VICPERIPHID3 */ "", 58943 /* MHOST_VICPRIORITYDAISY */ "", 58944 /* MHOST_VICPROTECTION */ "", 58945 /* MHOST_VICRAWINTR */ "", 58946 /* MHOST_VICSOFTINT */ "", 58947 /* MHOST_VICSOFTINTCLEAR */ "", 58948 /* MHOST_VICSWPRIORITYMASK */ "", 58949 /* MHOST_VICVECTADDR0 */ "", 58950 /* MHOST_VICVECTADDR1 */ "", 58951 /* MHOST_VICVECTADDR2 */ "", 58952 /* MHOST_VICVECTADDR3 */ "", 58953 /* MHOST_VICVECTADDR4 */ "", 58954 /* MHOST_VICVECTADDR5 */ "", 58955 /* MHOST_VICVECTADDR6 */ "", 58956 /* MHOST_VICVECTADDR7 */ "", 58957 /* MHOST_VICVECTADDR8 */ "", 58958 /* MHOST_VICVECTADDR9 */ "", 58959 /* MHOST_VICVECTADDR10 */ "", 58960 /* MHOST_VICVECTADDR11 */ "", 58961 /* MHOST_VICVECTADDR12 */ "", 58962 /* MHOST_VICVECTADDR13 */ "", 58963 /* MHOST_VICVECTADDR14 */ "", 58964 /* MHOST_VICVECTADDR15 */ "", 58965 /* MHOST_VICVECTADDR16 */ "", 58966 /* MHOST_VICVECTADDR17 */ "", 58967 /* MHOST_VICVECTADDR18 */ "", 58968 /* MHOST_VICVECTADDR19 */ "", 58969 /* MHOST_VICVECTADDR20 */ "", 58970 /* MHOST_VICVECTADDR21 */ "", 58971 /* MHOST_VICVECTADDR22 */ "", 58972 /* MHOST_VICVECTADDR23 */ "", 58973 /* MHOST_VICVECTADDR24 */ "", 58974 /* MHOST_VICVECTADDR25 */ "", 58975 /* MHOST_VICVECTADDR26 */ "", 58976 /* MHOST_VICVECTADDR27 */ "", 58977 /* MHOST_VICVECTADDR28 */ "", 58978 /* MHOST_VICVECTADDR29 */ "", 58979 /* MHOST_VICVECTADDR30 */ "", 58980 /* MHOST_VICVECTADDR31 */ "", 58981 /* MHOST_VICVECTPRIORITY0 */ "", 58982 /* MHOST_VICVECTPRIORITY1 */ "", 58983 /* MHOST_VICVECTPRIORITY2 */ "", 58984 /* MHOST_VICVECTPRIORITY3 */ "", 58985 /* MHOST_VICVECTPRIORITY4 */ "", 58986 /* MHOST_VICVECTPRIORITY5 */ "", 58987 /* MHOST_VICVECTPRIORITY6 */ "", 58988 /* MHOST_VICVECTPRIORITY7 */ "", 58989 /* MHOST_VICVECTPRIORITY8 */ "", 58990 /* MHOST_VICVECTPRIORITY9 */ "", 58991 /* MHOST_VICVECTPRIORITY10 */ "", 58992 /* MHOST_VICVECTPRIORITY11 */ "", 58993 /* MHOST_VICVECTPRIORITY12 */ "", 58994 /* MHOST_VICVECTPRIORITY13 */ "", 58995 /* MHOST_VICVECTPRIORITY14 */ "", 58996 /* MHOST_VICVECTPRIORITY15 */ "", 58997 /* MHOST_VICVECTPRIORITY16 */ "", 58998 /* MHOST_VICVECTPRIORITY17 */ "", 58999 /* MHOST_VICVECTPRIORITY18 */ "", 59000 /* MHOST_VICVECTPRIORITY19 */ "", 59001 /* MHOST_VICVECTPRIORITY20 */ "", 59002 /* MHOST_VICVECTPRIORITY21 */ "", 59003 /* MHOST_VICVECTPRIORITY22 */ "", 59004 /* MHOST_VICVECTPRIORITY23 */ "", 59005 /* MHOST_VICVECTPRIORITY24 */ "", 59006 /* MHOST_VICVECTPRIORITY25 */ "", 59007 /* MHOST_VICVECTPRIORITY26 */ "", 59008 /* MHOST_VICVECTPRIORITY27 */ "", 59009 /* MHOST_VICVECTPRIORITY28 */ "", 59010 /* MHOST_VICVECTPRIORITY29 */ "", 59011 /* MHOST_VICVECTPRIORITY30 */ "", 59012 /* MHOST_VICVECTPRIORITY31 */ "", 59013 /* MHOST_WDT_WDOGCONTROL */ "", 59014 /* MHOST_WDT_WDOGINTCLR */ "", 59015 /* MHOST_WDT_WDOGITCR */ "", 59016 /* MHOST_WDT_WDOGITOP */ "", 59017 /* MHOST_WDT_WDOGLOAD */ "", 59018 /* MHOST_WDT_WDOGLOCK */ "", 59019 /* MHOST_WDT_WDOGMIS */ "", 59020 /* MHOST_WDT_WDOGPCELLID0 */ "", 59021 /* MHOST_WDT_WDOGPCELLID1 */ "", 59022 /* MHOST_WDT_WDOGPCELLID2 */ "", 59023 /* MHOST_WDT_WDOGPCELLID3 */ "", 59024 /* MHOST_WDT_WDOGPERIPHID0 */ "", 59025 /* MHOST_WDT_WDOGPERIPHID1 */ "", 59026 /* MHOST_WDT_WDOGPERIPHID2 */ "", 59027 /* MHOST_WDT_WDOGPERIPHID3 */ "", 59028 /* MHOST_WDT_WDOGRIS */ "", 59029 /* MHOST_WDT_WDOGVALUE */ "", 59030 /* MH_PRIORITY_SOURCE */ "", 59031 /* MIB_MODE */ "", 59032 /* MIIM_CH0_ADDRESS */ "", 59033 /* MIIM_CH0_CONTROL */ "", 59034 /* MIIM_CH0_PARAMS */ "", 59035 /* MIIM_CH0_STATUS */ "", 59036 /* MIIM_CH1_ADDRESS */ "", 59037 /* MIIM_CH1_CONTROL */ "", 59038 /* MIIM_CH1_PARAMS */ "", 59039 /* MIIM_CH1_STATUS */ "", 59040 /* MIIM_CH2_ADDRESS */ "", 59041 /* MIIM_CH2_CONTROL */ "", 59042 /* MIIM_CH2_PARAMS */ "", 59043 /* MIIM_CH2_STATUS */ "", 59044 /* MIIM_CH3_ADDRESS */ "", 59045 /* MIIM_CH3_CONTROL */ "", 59046 /* MIIM_CH3_PARAMS */ "", 59047 /* MIIM_CH3_STATUS */ "", 59048 /* MIIM_COMMON_CONTROL */ "", 59049 /* MIIM_DMA_CH0_CONFIG */ "", 59050 /* MIIM_DMA_CH0_CURR_DST_HOST_ADDRESS */ "", 59051 /* MIIM_DMA_CH0_CURR_SRC_HOST_ADDRESS */ "", 59052 /* MIIM_DMA_CH0_DATA_ONLY_MODE_ADDRESS */ "", 59053 /* MIIM_DMA_CH0_DATA_ONLY_MODE_PARAMS */ "", 59054 /* MIIM_DMA_CH0_DST_HOST_ADDRESS */ "", 59055 /* MIIM_DMA_CH0_SRC_HOST_ADDRESS */ "", 59056 /* MIIM_DMA_CH0_STATUS */ "", 59057 /* MIIM_DMA_CH1_CONFIG */ "", 59058 /* MIIM_DMA_CH1_CURR_DST_HOST_ADDRESS */ "", 59059 /* MIIM_DMA_CH1_CURR_SRC_HOST_ADDRESS */ "", 59060 /* MIIM_DMA_CH1_DATA_ONLY_MODE_ADDRESS */ "", 59061 /* MIIM_DMA_CH1_DATA_ONLY_MODE_PARAMS */ "", 59062 /* MIIM_DMA_CH1_DST_HOST_ADDRESS */ "", 59063 /* MIIM_DMA_CH1_SRC_HOST_ADDRESS */ "", 59064 /* MIIM_DMA_CH1_STATUS */ "", 59065 /* MIIM_INTERRUPT_ENABLE */ "", 59066 /* MIIM_INTERRUPT_STATUS */ "", 59067 /* MIIM_INT_PHY_LINK_CHANGE_INTR_ENABLE */ "", 59068 /* MIIM_INT_PHY_LINK_CHANGE_INTR_STATUS */ "", 59069 /* MIIM_INT_PHY_LINK_MASK_STATUS */ "", 59070 /* MIIM_INT_PHY_LINK_RAW_STATUS */ "", 59071 /* MIIM_INT_PHY_LINK_STATUS */ "", 59072 /* MIIM_LINK_SCAN_STATUS */ "", 59073 /* MIIM_RING0_CONTROL */ "", 59074 /* MIIM_RING10_CONTROL */ "", 59075 /* MIIM_RING11_CONTROL */ "", 59076 /* MIIM_RING1_CONTROL */ "", 59077 /* MIIM_RING2_CONTROL */ "", 59078 /* MIIM_RING3_CONTROL */ "", 59079 /* MIIM_RING4_CONTROL */ "", 59080 /* MIIM_RING5_CONTROL */ "", 59081 /* MIIM_RING6_CONTROL */ "", 59082 /* MIIM_RING7_CONTROL */ "", 59083 /* MIIM_RING8_CONTROL */ "", 59084 /* MIIM_RING9_CONTROL */ "", 59085 /* MII_EEE_DELAY_ENTRY_TIMER */ "", 59086 /* MII_EEE_WAKE_TIMER */ "", 59087 /* MIML_ETYPE */ "", 59088 /* MIML_TPID */ "", 59089 /* MIM_DEFAULT_NETWORK_SVP */ "", 59090 /* MIM_ENABLE */ "", 59091 /* MIM_ETHERTYPE */ "", 59092 /* MIM_LIP_2_LEP_FC_EN */ "", 59093 /* MINBUCKET */ "", 59094 /* MINBUCKETCONFIG */ "", 59095 /* MINBUCKETCONFIG1 */ "", 59096 /* MINBUCKETCONFIG_64 */ "MINBUCKETCONFIG", 59097 /* MINBUCKETCOS0CONFIG */ "", 59098 /* MINBUCKETCOS1CONFIG */ "", 59099 /* MINBUCKETCOS2CONFIG */ "", 59100 /* MINBUCKETCOS3CONFIG */ "", 59101 /* MINBUCKETMEMDEBUG */ "", 59102 /* MINBUCKET_FLAG */ "", 59103 /* MINBUCKET_FLAG_QGROUP */ "", 59104 /* MINBUCKET_FLAG_QLAYER */ "", 59105 /* MINSPCONFIG */ "", 59106 /* MINSPCONFIG_CPU */ "", 59107 /* MIRROR_CONTROL */ "", 59108 /* MIRROR_CPU_COS_CONFIG */ "", 59109 /* MIRROR_RQE_Q_NUM */ "", 59110 /* MIRROR_SELECT */ "", 59111 /* MISCCONFIG */ "", 59112 /* MISC_CONFIG */ "", 59113 /* MISC_CONFIG_PIPE0 */ "", 59114 /* MISC_CONFIG_PIPE1 */ "", 59115 /* MISSING_START_ERR_STAT */ "", 59116 /* MMRP_CONTROL_1 */ "", 59117 /* MMRP_CONTROL_2 */ "", 59118 /* MMU0_FUSE_DEBUG */ "", 59119 /* MMU0_PLL_DEBUG */ "", 59120 /* MMU1_FUSE_DEBUG */ "", 59121 /* MMU1_PLL_DEBUG */ "", 59122 /* MMU2_PLL_DEBUG */ "", 59123 /* MMUBISRDBGRDDATA */ "", 59124 /* MMUEAVENABLE */ "", 59125 /* MMUFLUSHCONTROL */ "", 59126 /* MMUFLUSHCONTROL_0 */ "", 59127 /* MMUFLUSHCONTROL_1 */ "", 59128 /* MMUFLUSHCONTROL_2 */ "", 59129 /* MMUPORTENABLE */ "", 59130 /* MMUPORTENABLE_0 */ "", 59131 /* MMUPORTENABLE_1 */ "", 59132 /* MMUPORTENABLE_2 */ "", 59133 /* MMUPORTTXENABLE */ "", 59134 /* MMUPORTTXENABLE_0 */ "", 59135 /* MMUPORTTXENABLE_1 */ "", 59136 /* MMUPORTTXENABLE_2 */ "", 59137 /* MMU_1DBG_A */ "FORCE_SAF", 59138 /* MMU_1DBG_A_HP0 */ "FORCE_SAF_HP0", 59139 /* MMU_1DBG_A_HP1 */ "FORCE_SAF_HP1", 59140 /* MMU_1DBG_C */ "DIP_ACTIVATION0", 59141 /* MMU_2DBG_C_0 */ "DIP_DEACTIVATION", 59142 /* MMU_2DBG_C_1 */ "DIP_INSERTION0", 59143 /* MMU_3DBG_C */ "DIP_INSERTION1", 59144 /* MMU_ADM_ECC_COUNTERS */ "", 59145 /* MMU_ADM_ECC_DEBUG_0 */ "", 59146 /* MMU_ADM_ECC_ERROR_0 */ "", 59147 /* MMU_ADM_ECC_ERROR_0_MASK */ "", 59148 /* MMU_ADM_ECC_STATUS_0 */ "", 59149 /* MMU_ADM_MEMDEBUG */ "", 59150 /* MMU_ADM_QUEUE_DB_DEBUG */ "", 59151 /* MMU_AGING_CTR_ECC_STATUS */ "", 59152 /* MMU_AGING_ENABLE_ECCP_MEM */ "", 59153 /* MMU_AGING_EN_COR_ERR_RPT */ "", 59154 /* MMU_AGING_EXP_ECC_STATUS */ "", 59155 /* MMU_BAC_ASYNC_FIFO_CFG */ "", 59156 /* MMU_BAC_RD_FIFO_STATUS_0 */ "", 59157 /* MMU_BAC_RD_FIFO_STATUS_1 */ "", 59158 /* MMU_BANK_ACCESS_CONTROLLER_CONFIGURATIONS */ "", 59159 /* MMU_BANK_ACCESS_CONTROLLER_CONFIGURATIONS_2 */ "", 59160 /* MMU_CCPE_FIFO_MEM_ECC_STATUS */ "", 59161 /* MMU_CCPE_MEM_ECC_STATUS */ "", 59162 /* MMU_CCPI_FIFO_MEM_ECC_STATUS */ "", 59163 /* MMU_CCPI_MEM_ECC_STATUS */ "", 59164 /* MMU_CCP_CMIC_RESERVED */ "", 59165 /* MMU_CCP_ECC_1B_COUNTER */ "", 59166 /* MMU_CCP_ECC_2B_COUNTER */ "", 59167 /* MMU_CCP_ENABLE_ECCP_MEM */ "", 59168 /* MMU_CCP_EN_COR_ERR_RPT */ "", 59169 /* MMU_CCP_TMBUS */ "", 59170 /* MMU_CELLDATA_ECC_STATUS */ "", 59171 /* MMU_CELLLINK_ECC_STATUS */ "", 59172 /* MMU_CFAP_ARBITER_BNK0_RANKER */ "", 59173 /* MMU_CFAP_ARBITER_BNK10_RANKER */ "", 59174 /* MMU_CFAP_ARBITER_BNK11_RANKER */ "", 59175 /* MMU_CFAP_ARBITER_BNK12_RANKER */ "", 59176 /* MMU_CFAP_ARBITER_BNK13_RANKER */ "", 59177 /* MMU_CFAP_ARBITER_BNK14_RANKER */ "", 59178 /* MMU_CFAP_ARBITER_BNK15_RANKER */ "", 59179 /* MMU_CFAP_ARBITER_BNK16_RANKER */ "", 59180 /* MMU_CFAP_ARBITER_BNK17_RANKER */ "", 59181 /* MMU_CFAP_ARBITER_BNK18_RANKER */ "", 59182 /* MMU_CFAP_ARBITER_BNK19_RANKER */ "", 59183 /* MMU_CFAP_ARBITER_BNK1_RANKER */ "", 59184 /* MMU_CFAP_ARBITER_BNK20_RANKER */ "", 59185 /* MMU_CFAP_ARBITER_BNK21_RANKER */ "", 59186 /* MMU_CFAP_ARBITER_BNK22_RANKER */ "", 59187 /* MMU_CFAP_ARBITER_BNK23_RANKER */ "", 59188 /* MMU_CFAP_ARBITER_BNK24_RANKER */ "", 59189 /* MMU_CFAP_ARBITER_BNK25_RANKER */ "", 59190 /* MMU_CFAP_ARBITER_BNK26_RANKER */ "", 59191 /* MMU_CFAP_ARBITER_BNK27_RANKER */ "", 59192 /* MMU_CFAP_ARBITER_BNK28_RANKER */ "", 59193 /* MMU_CFAP_ARBITER_BNK29_RANKER */ "", 59194 /* MMU_CFAP_ARBITER_BNK2_RANKER */ "", 59195 /* MMU_CFAP_ARBITER_BNK30_RANKER */ "", 59196 /* MMU_CFAP_ARBITER_BNK31_RANKER */ "", 59197 /* MMU_CFAP_ARBITER_BNK32_RANKER */ "", 59198 /* MMU_CFAP_ARBITER_BNK33_RANKER */ "", 59199 /* MMU_CFAP_ARBITER_BNK3_RANKER */ "", 59200 /* MMU_CFAP_ARBITER_BNK4_RANKER */ "", 59201 /* MMU_CFAP_ARBITER_BNK5_RANKER */ "", 59202 /* MMU_CFAP_ARBITER_BNK6_RANKER */ "", 59203 /* MMU_CFAP_ARBITER_BNK7_RANKER */ "", 59204 /* MMU_CFAP_ARBITER_BNK8_RANKER */ "", 59205 /* MMU_CFAP_ARBITER_BNK9_RANKER */ "", 59206 /* MMU_CFAP_ARBITER_CONTROL */ "", 59207 /* MMU_CFAP_ARBITER_MASK */ "", 59208 /* MMU_CFAP_ARBITER_RANDOM_SEED */ "", 59209 /* MMU_CFAP_BANKDISABLE_64 */ "", 59210 /* MMU_CFAP_BANKFULL */ "", 59211 /* MMU_CFAP_BANKSTATUS */ "", 59212 /* MMU_CFAP_BANK_PREFETCH_FIFO */ "", 59213 /* MMU_CFAP_BANK_SCRATCHPAD */ "", 59214 /* MMU_CFAP_BSTCONFIG */ "", 59215 /* MMU_CFAP_BSTSTAT */ "CFAP_BST_STAT", 59216 /* MMU_CFAP_BSTTHRS */ "CFAP_BST_THRESHOLD", 59217 /* MMU_CFAP_CMIC_RESERVED */ "", 59218 /* MMU_CFAP_COLLISION */ "", 59219 /* MMU_CFAP_CONFIG */ "", 59220 /* MMU_CFAP_DROP_CBP */ "", 59221 /* MMU_CFAP_DROP_COLLISION */ "", 59222 /* MMU_CFAP_DROP_FULL */ "", 59223 /* MMU_CFAP_ECC_STATUS */ "", 59224 /* MMU_CFAP_ENABLE_ECCP_MEM */ "", 59225 /* MMU_CFAP_EN_COR_ERR_RPT */ "", 59226 /* MMU_CFAP_FULL */ "", 59227 /* MMU_CFAP_FULLCOL_CONTROL */ "", 59228 /* MMU_CFAP_FULLTHRESHOLDSET */ "", 59229 /* MMU_CFAP_FULL_RESUME_OFFSET */ "", 59230 /* MMU_CFAP_INIT_64 */ "", 59231 /* MMU_CFAP_INT_EN */ "", 59232 /* MMU_CFAP_INT_SET */ "", 59233 /* MMU_CFAP_INT_STAT */ "", 59234 /* MMU_CFAP_STATUS */ "", 59235 /* MMU_CFAP_TMBUS */ "", 59236 /* MMU_CFG_HSP_CONFIG */ "", 59237 /* MMU_CFG_THDI_EXT_PACK_SEGMENT_COUNT_SETUP */ "", 59238 /* MMU_CFG_THDI_EXT_PACK_SEGMENT_COUNT_STATE */ "", 59239 /* MMU_CNM_FORCE_GEN */ "", 59240 /* MMU_CRB_CELL_CREDIT */ "", 59241 /* MMU_CRB_CMIC_RESERVED */ "", 59242 /* MMU_CRB_CONFIG */ "", 59243 /* MMU_CRB_CPU_INT_EN */ "", 59244 /* MMU_CRB_CPU_INT_SET */ "", 59245 /* MMU_CRB_CPU_INT_STAT */ "", 59246 /* MMU_CRB_CPU_INT_STAT_LOG */ "", 59247 /* MMU_CRB_CREDIT_DROP_CONFIG */ "", 59248 /* MMU_CRB_CREDIT_DROP_PKT_COUNT */ "", 59249 /* MMU_CRB_DEVICE_PORT_TO_MMU_PORT_MAPPING */ "", 59250 /* MMU_CRB_ENABLE_ECCP_MEM */ "", 59251 /* MMU_CRB_EN_COR_ERR_RPT */ "", 59252 /* MMU_CRB_INVALID_DESTINATION_PKT_COUNT */ "", 59253 /* MMU_CRB_INVALID_DESTINATION_PKT_ID */ "", 59254 /* MMU_CRB_PKT_DROP_CNTR_STAT */ "", 59255 /* MMU_CRB_RQE_QUEUE_CONFIG */ "", 59256 /* MMU_CRB_SRC_PORT_CFG */ "", 59257 /* MMU_CRB_TMBUS */ "", 59258 /* MMU_CRC_ERR_CNT_BANK */ "", 59259 /* MMU_CRC_ERR_CNT_BANK_11_10_9_8 */ "", 59260 /* MMU_CRC_ERR_CNT_BANK_15_14_13_12 */ "", 59261 /* MMU_CRC_ERR_CNT_BANK_19_18_17_16 */ "", 59262 /* MMU_CRC_ERR_CNT_BANK_23_22_21_20 */ "", 59263 /* MMU_CRC_ERR_CNT_BANK_27_26_25_24 */ "", 59264 /* MMU_CRC_ERR_CNT_BANK_31_30_29_28 */ "", 59265 /* MMU_CRC_ERR_CNT_BANK_35_34_33_32 */ "", 59266 /* MMU_CRC_ERR_CNT_BANK_39_38_37_36 */ "", 59267 /* MMU_CRC_ERR_CNT_BANK_3_2_1_0 */ "", 59268 /* MMU_CRC_ERR_CNT_BANK_43_42_41_40 */ "", 59269 /* MMU_CRC_ERR_CNT_BANK_47_46_45_44 */ "", 59270 /* MMU_CRC_ERR_CNT_BANK_51_50_49_48 */ "", 59271 /* MMU_CRC_ERR_CNT_BANK_55_54_53_52 */ "", 59272 /* MMU_CRC_ERR_CNT_BANK_59_58_57_56 */ "", 59273 /* MMU_CRC_ERR_CNT_BANK_63_62_61_60 */ "", 59274 /* MMU_CRC_ERR_CNT_BANK_7_6_5_4 */ "", 59275 /* MMU_CRC_ERR_CNT_OCB */ "", 59276 /* MMU_CTR_ECC_1B_COUNTER */ "", 59277 /* MMU_CTR_ECC_2B_COUNTER */ "", 59278 /* MMU_CTR_ENABLE_ECCP_MEM */ "", 59279 /* MMU_CTR_EN_COR_ERR_RPT */ "", 59280 /* MMU_CTR_MEM_ECC_STATUS */ "", 59281 /* MMU_CTR_PARITY_ERR */ "", 59282 /* MMU_DEBUG_REG */ "", 59283 /* MMU_DEQ_EN_COR_ERR_RPT */ "", 59284 /* MMU_DI_THR */ "DIP_ACTIVATION1", 59285 /* MMU_DQS_ENABLE_ECCP_MEM */ "", 59286 /* MMU_DQS_EN_COR_ERR_RPT */ "", 59287 /* MMU_DQS_REPL_PORT_AGG_MAP */ "", 59288 /* MMU_DQX_ENABLE_ECCP_MEM */ "", 59289 /* MMU_DQX_EN_COR_ERR_RPT */ "", 59290 /* MMU_DQX_MB0_CBI_ERR */ "", 59291 /* MMU_DQX_MB1_CBI_ERR */ "", 59292 /* MMU_DQX_MB_CBI_ERR */ "", 59293 /* MMU_DRAM_BLOCK */ "", 59294 /* MMU_DRAM_BLOCK_LEAKY_BUCKET_WATER_MARK */ "", 59295 /* MMU_DRAM_INDIRECT_ADDRESS */ "", 59296 /* MMU_DRAM_NUMBER_SWAPPING */ "", 59297 /* MMU_DRCA_RD_BYTE_COUNTER */ "", 59298 /* MMU_DRCA_WR_BYTE_COUNTER */ "", 59299 /* MMU_DRCB_RD_BYTE_COUNTER */ "", 59300 /* MMU_DRCB_WR_BYTE_COUNTER */ "", 59301 /* MMU_DRCC_RD_BYTE_COUNTER */ "", 59302 /* MMU_DRCC_WR_BYTE_COUNTER */ "", 59303 /* MMU_DRCD_RD_BYTE_COUNTER */ "", 59304 /* MMU_DRCD_WR_BYTE_COUNTER */ "", 59305 /* MMU_DRCE_RD_BYTE_COUNTER */ "", 59306 /* MMU_DRCE_WR_BYTE_COUNTER */ "", 59307 /* MMU_DRCF_RD_BYTE_COUNTER */ "", 59308 /* MMU_DRCF_WR_BYTE_COUNTER */ "", 59309 /* MMU_DRCG_RD_BYTE_COUNTER */ "", 59310 /* MMU_DRCG_WR_BYTE_COUNTER */ "", 59311 /* MMU_DRCH_RD_BYTE_COUNTER */ "", 59312 /* MMU_DRCH_WR_BYTE_COUNTER */ "", 59313 /* MMU_DRC_COUNTERS */ "", 59314 /* MMU_E2EFC_CNT_DEBUG_STATUS_0 */ "", 59315 /* MMU_E2EFC_CNT_DEBUG_STATUS_1 */ "", 59316 /* MMU_E2EFC_DEBUG_RX_RMT_IBP0 */ "", 59317 /* MMU_E2EFC_DEBUG_RX_RMT_IBP1 */ "", 59318 /* MMU_E2EFC_DEBUG_TX_RMT_IBP0 */ "", 59319 /* MMU_E2EFC_DEBUG_TX_RMT_IBP1 */ "", 59320 /* MMU_E2EFC_ERROR_0 */ "", 59321 /* MMU_E2EFC_ERROR_0_MASK */ "", 59322 /* MMU_EBCFG_CMIC_RESERVED */ "", 59323 /* MMU_EBCFG_CPU_INT_EN */ "MMU_EBCFG_CPU_INT_EN", 59324 /* MMU_EBCFG_CPU_INT_SET */ "MMU_EBCFG_CPU_INT_SET", 59325 /* MMU_EBCFG_CPU_INT_STAT */ "MMU_EBCFG_CPU_INT_STAT", 59326 /* MMU_EBCFG_ECC_SINGLE_BIT_ERRORS */ "", 59327 /* MMU_EBCFG_MEM_FAIL_INT_CTR */ "", 59328 /* MMU_EBCFG_MEM_SER_FIFO_STS */ "", 59329 /* MMU_EBCFP_CMIC_RESERVED */ "", 59330 /* MMU_EBCFP_CPU_INT_EN */ "", 59331 /* MMU_EBCFP_CPU_INT_SET */ "", 59332 /* MMU_EBCFP_CPU_INT_STAT */ "", 59333 /* MMU_EBCFP_DD_PURGE_STATUS */ "", 59334 /* MMU_EBCFP_EGR_PORT_CFG */ "", 59335 /* MMU_EBCFP_ENABLE_ECCP_MEM */ "", 59336 /* MMU_EBCFP_EN_COR_ERR_RPT */ "", 59337 /* MMU_EBCFP_FAP_FULL_THRESHOLD_RESET */ "", 59338 /* MMU_EBCFP_FAP_FULL_THRESHOLD_SET */ "", 59339 /* MMU_EBCFP_FORCE_CPU_INIT_TO_FAP */ "", 59340 /* MMU_EBCFP_INIT_DONE */ "", 59341 /* MMU_EBCFP_MMUQ_EBGRP_PROFILE */ "", 59342 /* MMU_EBCFP_MMU_PORT_TO_DEVICE_PORT_MAPPING */ "", 59343 /* MMU_EBCFP_MTRO_PORT_PROFILE_STATUS */ "", 59344 /* MMU_EBCFP_MTU_VIOLATION_STATUS */ "", 59345 /* MMU_EBCFP_OPT_EBGRP_MTU_PROFILE */ "", 59346 /* MMU_EBCFP_OPT_EBGRP_REDUCED_MTU */ "", 59347 /* MMU_EBCFP_POOL_COUNTER */ "", 59348 /* MMU_EBCFP_TMBUS */ "", 59349 /* MMU_EBCR_CMIC_RESERVED */ "", 59350 /* MMU_EBCR_ENABLE_ECCP_MEM */ "", 59351 /* MMU_EBCR_EN_COR_ERR_RPT */ "", 59352 /* MMU_EBCR_TMBUS */ "", 59353 /* MMU_EBCTM_BURST_CTRL_STS */ "", 59354 /* MMU_EBCTM_CMIC_RESERVED */ "", 59355 /* MMU_EBCTM_CNTR_0_STS */ "", 59356 /* MMU_EBCTM_CNTR_1_STS */ "", 59357 /* MMU_EBCTM_CPU_INT_EN */ "", 59358 /* MMU_EBCTM_CPU_INT_SET */ "", 59359 /* MMU_EBCTM_CPU_INT_STAT */ "", 59360 /* MMU_EBCTM_CPU_INT_STAT_LOG */ "", 59361 /* MMU_EBCTM_CT_BUDGET_CFG */ "", 59362 /* MMU_EBCTM_CT_BUDGET_SAF_COMMITMENT_CFG */ "", 59363 /* MMU_EBCTM_CT_FSM_STS */ "", 59364 /* MMU_EBCTM_CT_SPEED_0_CFG */ "", 59365 /* MMU_EBCTM_CT_SPEED_1_CFG */ "", 59366 /* MMU_EBCTM_CT_SPEED_2_CFG */ "", 59367 /* MMU_EBCTM_CT_SPEED_3_CFG */ "", 59368 /* MMU_EBCTM_CT_SPEED_4_CFG */ "", 59369 /* MMU_EBCTM_CT_SPEED_5_CFG */ "", 59370 /* MMU_EBCTM_CT_SPEED_6_CFG */ "", 59371 /* MMU_EBCTM_EB_TCT_CFG */ "", 59372 /* MMU_EBCTM_EPORT_CT_CFG */ "", 59373 /* MMU_EBCTM_EPORT_TCT_CFG */ "", 59374 /* MMU_EBCTM_MIN_MOP_SPACING_SPEED_BUCKET_0_CFG */ "", 59375 /* MMU_EBCTM_MIN_MOP_SPACING_SPEED_BUCKET_1_CFG */ "", 59376 /* MMU_EBCTM_MIN_MOP_SPACING_SPEED_BUCKET_2_CFG */ "", 59377 /* MMU_EBCTM_PORT_EMPTY_STS */ "", 59378 /* MMU_EBCTM_SRC_SPEED_0_TO_SPEED_BUCKET_MAP_CFG */ "", 59379 /* MMU_EBCTM_SRC_SPEED_1_TO_SPEED_BUCKET_MAP_CFG */ "", 59380 /* MMU_EBCTM_SRC_SPEED_2_TO_SPEED_BUCKET_MAP_CFG */ "", 59381 /* MMU_EBCTM_SRC_SPEED_3_TO_SPEED_BUCKET_MAP_CFG */ "", 59382 /* MMU_EBCTM_SRC_SPEED_4_TO_SPEED_BUCKET_MAP_CFG */ "", 59383 /* MMU_EBCTM_SRC_SPEED_5_TO_SPEED_BUCKET_MAP_CFG */ "", 59384 /* MMU_EBCTM_SRC_SPEED_6_TO_SPEED_BUCKET_MAP_CFG */ "", 59385 /* MMU_EBCTM_TCT_ENTER_SPEED_CFG */ "", 59386 /* MMU_EBCTM_TCT_EXIT_SPEED_CFG */ "", 59387 /* MMU_EBMB_CMIC_RESERVED */ "", 59388 /* MMU_EBMB_DEBUG */ "", 59389 /* MMU_EBMB_ENABLE_ECCP_MEM */ "", 59390 /* MMU_EBMB_EN_COR_ERR_RPT */ "", 59391 /* MMU_EBMB_TMBUS */ "", 59392 /* MMU_EBPCC_COUNTER_OVERFLOW */ "", 59393 /* MMU_EBPCC_COUNTER_UNDERFLOW */ "", 59394 /* MMU_EBPCC_CPU_INT_EN */ "", 59395 /* MMU_EBPCC_CPU_INT_SET */ "", 59396 /* MMU_EBPCC_CPU_INT_STAT */ "", 59397 /* MMU_EBPCC_EBQUEUE_CELL_CNT_STS */ "", 59398 /* MMU_EBPCC_EPORT_CFG */ "", 59399 /* MMU_EBPCC_MMUQ_SCHQ_CFG */ "", 59400 /* MMU_EBPCC_MMUQ_SCHQ_PROFILE */ "", 59401 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD0_SPEED_0_CFG */ "", 59402 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD0_SPEED_1_CFG */ "", 59403 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD0_SPEED_2_CFG */ "", 59404 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD0_SPEED_3_CFG */ "", 59405 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD0_SPEED_4_CFG */ "", 59406 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD0_SPEED_5_CFG */ "", 59407 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD0_SPEED_6_CFG */ "", 59408 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD1_SPEED_0_CFG */ "", 59409 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD1_SPEED_1_CFG */ "", 59410 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD1_SPEED_2_CFG */ "", 59411 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD1_SPEED_3_CFG */ "", 59412 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD1_SPEED_4_CFG */ "", 59413 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD1_SPEED_5_CFG */ "", 59414 /* MMU_EBPCC_PORTDEFICIT_THRESHOLD1_SPEED_6_CFG */ "", 59415 /* MMU_EBPCC_PORTDEFICIT_WARM_UP_SPEED_0_CFG */ "", 59416 /* MMU_EBPCC_PORTDEFICIT_WARM_UP_SPEED_1_CFG */ "", 59417 /* MMU_EBPCC_PORTDEFICIT_WARM_UP_SPEED_2_CFG */ "", 59418 /* MMU_EBPCC_PORTDEFICIT_WARM_UP_SPEED_3_CFG */ "", 59419 /* MMU_EBPCC_PORTDEFICIT_WARM_UP_SPEED_4_CFG */ "", 59420 /* MMU_EBPCC_PORTDEFICIT_WARM_UP_SPEED_5_CFG */ "", 59421 /* MMU_EBPCC_PORTDEFICIT_WARM_UP_SPEED_6_CFG */ "", 59422 /* MMU_EBPCC_RSVD_REG */ "", 59423 /* MMU_EBPCC_TCT_SPEED_0_CFG */ "", 59424 /* MMU_EBPCC_TCT_SPEED_1_CFG */ "", 59425 /* MMU_EBPCC_TCT_SPEED_2_CFG */ "", 59426 /* MMU_EBPCC_TCT_SPEED_3_CFG */ "", 59427 /* MMU_EBPCC_TCT_SPEED_4_CFG */ "", 59428 /* MMU_EBPCC_TCT_SPEED_5_CFG */ "", 59429 /* MMU_EBPCC_TCT_SPEED_6_CFG */ "", 59430 /* MMU_EBPTS_CAL_CONFIG */ "", 59431 /* MMU_EBPTS_CBMG_VALUE */ "", 59432 /* MMU_EBPTS_CMIC_RESERVED */ "", 59433 /* MMU_EBPTS_CPU_MGMT_LB_RATIOS */ "", 59434 /* MMU_EBPTS_EBSHP_DEBUG */ "", 59435 /* MMU_EBPTS_EBSHP_GLB_CONFIG */ "", 59436 /* MMU_EBPTS_EBSHP_PORT_CFG */ "", 59437 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG0_0 */ "", 59438 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG0_1 */ "", 59439 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG0_2 */ "", 59440 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG0_3 */ "", 59441 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG0_4 */ "", 59442 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG0_5 */ "", 59443 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG0_6 */ "", 59444 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG1_0 */ "", 59445 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG1_1 */ "", 59446 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG1_2 */ "", 59447 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG1_3 */ "", 59448 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG1_4 */ "", 59449 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG1_5 */ "", 59450 /* MMU_EBPTS_EBSHP_PORT_SPEED_CFG1_6 */ "", 59451 /* MMU_EBPTS_EDB_CREDIT_COUNTER */ "", 59452 /* MMU_EBPTS_EDB_PORT_CREDIT_THRESHOLD_0 */ "", 59453 /* MMU_EBPTS_EDB_PORT_CREDIT_THRESHOLD_1 */ "", 59454 /* MMU_EBPTS_ENABLE_ECCP_MEM */ "", 59455 /* MMU_EBPTS_EN_COR_ERR_RPT */ "", 59456 /* MMU_EBPTS_FEATURE_CTRL */ "", 59457 /* MMU_EBPTS_MAX_SPACING */ "", 59458 /* MMU_EBPTS_MIN_CELL_SPACING */ "", 59459 /* MMU_EBPTS_MIN_CELL_SPACING_EOP_TO_SOP */ "", 59460 /* MMU_EBPTS_MIN_PORT_PICK_SPACING_WITHIN_PKT */ "", 59461 /* MMU_EBPTS_MMU_PKSCH_PKT_CREDIT_RETURN_DELAY */ "", 59462 /* MMU_EBPTS_MMU_PORT_TO_PHY_PORT_MAPPING */ "", 59463 /* MMU_EBPTS_PKSCH_CAL_CONFIG */ "", 59464 /* MMU_EBPTS_PKSCH_CPU_MGMT_LB_RATIOS */ "", 59465 /* MMU_EBPTS_PKSCH_CREDIT_STS */ "", 59466 /* MMU_EBPTS_PKSCH_PKT_CREDITS_PER_PIPE */ "", 59467 /* MMU_EBPTS_PKSCH_PKT_CREDITS_PER_PORT */ "", 59468 /* MMU_EBPTS_TMBUS */ "", 59469 /* MMU_EBPTS_URG_CELL_SPACING */ "", 59470 /* MMU_EBQS_CMIC_RESERVED */ "", 59471 /* MMU_EBQS_CPU_INT_EN */ "", 59472 /* MMU_EBQS_CPU_INT_SET */ "", 59473 /* MMU_EBQS_CPU_INT_STAT */ "", 59474 /* MMU_EBQS_CPU_INT_STAT_LOG */ "", 59475 /* MMU_EBQS_DEBUG */ "", 59476 /* MMU_EBQS_EBPTS_PREFETCH_CNTL */ "", 59477 /* MMU_EBQS_EBQ_PROFILE */ "", 59478 /* MMU_EBQS_PFC_XOFF_CNTL */ "", 59479 /* MMU_EBQS_PORT_CFG */ "", 59480 /* MMU_EBQS_PORT_FLUSH */ "", 59481 /* MMU_EBTOQ_CMIC_RESERVED */ "", 59482 /* MMU_EBTOQ_CPU_INT_EN */ "", 59483 /* MMU_EBTOQ_CPU_INT_SET */ "", 59484 /* MMU_EBTOQ_CPU_INT_STAT */ "", 59485 /* MMU_EBTOQ_ENABLE_ECCP_MEM */ "", 59486 /* MMU_EBTOQ_EN_COR_ERR_RPT */ "", 59487 /* MMU_EBTOQ_FORCE_CPU_INIT */ "", 59488 /* MMU_EBTOQ_TMBUS */ "", 59489 /* MMU_ECC_1B_ERR_CNT */ "", 59490 /* MMU_ECC_2B_ERR_CNT */ "", 59491 /* MMU_ECC_DEBUG0 */ "", 59492 /* MMU_ECC_DEBUG1 */ "", 59493 /* MMU_ECC_ERROR0 */ "", 59494 /* MMU_ECC_ERROR1 */ "", 59495 /* MMU_ECC_ERROR0_MASK */ "", 59496 /* MMU_ECC_ERROR1_MASK */ "", 59497 /* MMU_ECC_ERR_1B_INITIATE */ "", 59498 /* MMU_ECC_ERR_1B_INITIATE_1 */ "", 59499 /* MMU_ECC_ERR_1B_INITIATE_2 */ "", 59500 /* MMU_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 59501 /* MMU_ECC_ERR_1B_MONITOR_MEM_MASK_1 */ "", 59502 /* MMU_ECC_ERR_1B_MONITOR_MEM_MASK_2 */ "", 59503 /* MMU_ECC_ERR_2B_INITIATE */ "", 59504 /* MMU_ECC_ERR_2B_INITIATE_1 */ "", 59505 /* MMU_ECC_ERR_2B_INITIATE_2 */ "", 59506 /* MMU_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 59507 /* MMU_ECC_ERR_2B_MONITOR_MEM_MASK_1 */ "", 59508 /* MMU_ECC_ERR_2B_MONITOR_MEM_MASK_2 */ "", 59509 /* MMU_ECC_INTERRUPT_REGISTER */ "", 59510 /* MMU_ECC_INTERRUPT_REGISTER_MASK */ "", 59511 /* MMU_ECC_INTERRUPT_REGISTER_TEST */ "", 59512 /* MMU_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 59513 /* MMU_ENQS_CT_FIFO_DFT */ "", 59514 /* MMU_ENQS_DEBUG */ "", 59515 /* MMU_ENQS_ENABLE_ECCP_MEM */ "", 59516 /* MMU_ENQS_EN_COR_ERR_RPT */ "", 59517 /* MMU_ENQS_NO_DEST */ "", 59518 /* MMU_ENQS_PBI_DB_DFT */ "", 59519 /* MMU_ENQS_PORT_NON_EMPTY_BMPA */ "", 59520 /* MMU_ENQS_PORT_NON_EMPTY_BMPB */ "", 59521 /* MMU_ENQS_PORT_NON_EMPTY_BMP_0 */ "", 59522 /* MMU_ENQS_PORT_NON_EMPTY_BMP_1 */ "", 59523 /* MMU_ENQX_ENABLE_ECCP_MEM */ "", 59524 /* MMU_ENQX_EN_COR_ERR_RPT */ "", 59525 /* MMU_ENQX_EN_COR_ERR_RPT_XPE0 */ "", 59526 /* MMU_ENQ_CBP_STORE_DEBUG_0 */ "", 59527 /* MMU_ENQ_CFAPI_INTERNAL_RECYCLE_DEBUG_0 */ "", 59528 /* MMU_ENQ_CFAPI_RECYCLE_FIFO_LEVEL */ "", 59529 /* MMU_ENQ_CFG_ECC_DEBUG_0 */ "", 59530 /* MMU_ENQ_CFG_ECC_ERROR_0 */ "", 59531 /* MMU_ENQ_CFG_ECC_ERROR_0_MASK */ "", 59532 /* MMU_ENQ_CFG_ECC_STATUS_0 */ "", 59533 /* MMU_ENQ_CFG_ECC_STATUS_1 */ "", 59534 /* MMU_ENQ_CFG_ECC_STATUS_2 */ "", 59535 /* MMU_ENQ_CFG_ECC_STATUS_3 */ "", 59536 /* MMU_ENQ_CFG_ECC_STATUS_4 */ "", 59537 /* MMU_ENQ_CONFIG_0 */ "", 59538 /* MMU_ENQ_DEBUG */ "", 59539 /* MMU_ENQ_DEST_PPP_CFG_0 */ "", 59540 /* MMU_ENQ_DEST_PPP_CFG_1 */ "", 59541 /* MMU_ENQ_DEST_PPP_CFG_2 */ "", 59542 /* MMU_ENQ_DEST_PPP_CFG_3 */ "", 59543 /* MMU_ENQ_DEST_PPP_CFG_4 */ "", 59544 /* MMU_ENQ_DEST_PPP_CFG_5 */ "", 59545 /* MMU_ENQ_ECC_COUNTERS */ "", 59546 /* MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_0 */ "", 59547 /* MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_1 */ "", 59548 /* MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_2 */ "", 59549 /* MMU_ENQ_EMA_COS_TO_FIFO_LOOKUP_3 */ "", 59550 /* MMU_ENQ_EMA_COS_TO_FIFO_PROFILE_0 */ "", 59551 /* MMU_ENQ_EMA_COS_TO_FIFO_PROFILE_1 */ "", 59552 /* MMU_ENQ_EMA_COS_TO_FIFO_PROFILE_2 */ "", 59553 /* MMU_ENQ_EMA_PACKET_NUM_IN_USE_HI_WATERMARK */ "", 59554 /* MMU_ENQ_EMA_QUEUE_SELECT_0 */ "", 59555 /* MMU_ENQ_EMA_QUEUE_SELECT_1 */ "", 59556 /* MMU_ENQ_EN_COR_ERR_RPT */ "", 59557 /* MMU_ENQ_ERROR_0 */ "", 59558 /* MMU_ENQ_ERROR_0_MASK */ "", 59559 /* MMU_ENQ_FAPCONFIG_0 */ "", 59560 /* MMU_ENQ_FAPFULLRESETPOINT_0 */ "", 59561 /* MMU_ENQ_FAPFULLSETPOINT_0 */ "", 59562 /* MMU_ENQ_FAPINIT_0 */ "", 59563 /* MMU_ENQ_FAPREADPOINTER_0 */ "", 59564 /* MMU_ENQ_FAPSTACKSTATUS_0 */ "", 59565 /* MMU_ENQ_FAP_ECC_DEBUG_0 */ "", 59566 /* MMU_ENQ_FAP_ECC_ERROR_0 */ "", 59567 /* MMU_ENQ_FAP_ECC_ERROR_0_MASK */ "", 59568 /* MMU_ENQ_FAP_ECC_STATUS_0 */ "", 59569 /* MMU_ENQ_FAP_MEMDEBUG_0 */ "", 59570 /* MMU_ENQ_FAP_WATERMARK */ "", 59571 /* MMU_ENQ_HIGIG_25_PRI_GRP0 */ "", 59572 /* MMU_ENQ_HIGIG_25_PRI_GRP1 */ "", 59573 /* MMU_ENQ_HIGIG_26_PRI_GRP0 */ "", 59574 /* MMU_ENQ_HIGIG_26_PRI_GRP1 */ "", 59575 /* MMU_ENQ_HIGIG_27_PRI_GRP0 */ "", 59576 /* MMU_ENQ_HIGIG_27_PRI_GRP1 */ "", 59577 /* MMU_ENQ_HIGIG_28_PRI_GRP0 */ "", 59578 /* MMU_ENQ_HIGIG_28_PRI_GRP1 */ "", 59579 /* MMU_ENQ_ILLEGAL_CELL_TYPE_0 */ "", 59580 /* MMU_ENQ_IP_PRI_TO_PG_PROFILE_0 */ "", 59581 /* MMU_ENQ_ITE_REORDER_DEBUG_0 */ "", 59582 /* MMU_ENQ_LOGICAL_PORT_TO_PORT_AGG_MAP */ "", 59583 /* MMU_ENQ_MC_EXT_DROP_COUNTER_0 */ "", 59584 /* MMU_ENQ_MC_INT_DROP_COUNTER_0 */ "", 59585 /* MMU_ENQ_MISSING_START_ERR_STAT_0 */ "", 59586 /* MMU_ENQ_MISSING_START_ERR_STAT_1 */ "", 59587 /* MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESH */ "", 59588 /* MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_0 */ "", 59589 /* MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_1 */ "", 59590 /* MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_2 */ "", 59591 /* MMU_ENQ_PACK_PKT_LEN_FIFO_DEBUG_0 */ "", 59592 /* MMU_ENQ_PACK_SRC_CTXT_FIFO_DEBUG_0 */ "", 59593 /* MMU_ENQ_PACK_SRC_CTXT_FPLL_DEBUG_0 */ "", 59594 /* MMU_ENQ_PBI_SOP_DB_TM */ "", 59595 /* MMU_ENQ_PIPE_DELAY_MEM_TM */ "", 59596 /* MMU_ENQ_PORT_EMPTY_BMP0 */ "", 59597 /* MMU_ENQ_PORT_EMPTY_BMP1 */ "", 59598 /* MMU_ENQ_POST_PAC_SAE_FIFO_DEBUG_0 */ "", 59599 /* MMU_ENQ_POST_PAC_SAE_FIFO_HI_WATERMARK */ "", 59600 /* MMU_ENQ_PROFILE_0_PRI_GRP0 */ "", 59601 /* MMU_ENQ_PROFILE_0_PRI_GRP1 */ "", 59602 /* MMU_ENQ_PROFILE_1_PRI_GRP0 */ "", 59603 /* MMU_ENQ_PROFILE_1_PRI_GRP1 */ "", 59604 /* MMU_ENQ_PROFILE_2_PRI_GRP0 */ "", 59605 /* MMU_ENQ_PROFILE_2_PRI_GRP1 */ "", 59606 /* MMU_ENQ_PROFILE_3_PRI_GRP0 */ "", 59607 /* MMU_ENQ_PROFILE_3_PRI_GRP1 */ "", 59608 /* MMU_ENQ_REORDER_FIFO_IN_USE_HI_WATERMARK */ "", 59609 /* MMU_ENQ_REPL_PORT_AGG_MAP */ "", 59610 /* MMU_ENQ_RQE_QUEUE_SELECT_0 */ "", 59611 /* MMU_ENQ_RQE_QUEUE_SELECT_1 */ "", 59612 /* MMU_ENQ_RQE_WR_COMPLETE_DEBUG_0 */ "", 59613 /* MMU_ENQ_SOP_STORE_DEBUG_0 */ "", 59614 /* MMU_ENQ_SRC_PORT_STATE_DEBUG_0 */ "", 59615 /* MMU_ENQ_START_BY_START_ERR_STAT_0 */ "", 59616 /* MMU_ENQ_START_BY_START_ERR_STAT_1 */ "", 59617 /* MMU_ENQ_TRACE_IF_CAPT_0 */ "", 59618 /* MMU_ENQ_TRACE_IF_CAPT_1 */ "", 59619 /* MMU_ENQ_TRACE_IF_CAPT_2 */ "", 59620 /* MMU_ENQ_TRACE_IF_CAPT_3 */ "", 59621 /* MMU_ENQ_TRACE_IF_CAPT_4 */ "", 59622 /* MMU_ENQ_TRACE_IF_CAPT_5 */ "", 59623 /* MMU_ENQ_TRACE_IF_CAPT_6 */ "", 59624 /* MMU_ENQ_TRACE_IF_CAPT_7 */ "", 59625 /* MMU_ENQ_TRACE_IF_CAPT_8 */ "", 59626 /* MMU_ENQ_TRACE_IF_CAPT_9 */ "", 59627 /* MMU_ENQ_TRACE_IF_CAPT_10 */ "", 59628 /* MMU_ENQ_TRACE_IF_CAPT_11 */ "", 59629 /* MMU_ENQ_TRACE_IF_CAPT_12 */ "", 59630 /* MMU_ENQ_TRACE_IF_CAPT_13 */ "", 59631 /* MMU_ENQ_TRACE_IF_CAPT_14 */ "", 59632 /* MMU_ENQ_TRACE_IF_CAPT_15 */ "", 59633 /* MMU_ENQ_TRACE_IF_CAPT_16 */ "", 59634 /* MMU_ENQ_TRACE_IF_CAPT_17 */ "", 59635 /* MMU_ENQ_TRACE_IF_CAPT_18 */ "", 59636 /* MMU_ENQ_TRACE_IF_CAPT_19 */ "", 59637 /* MMU_ENQ_TRACE_IF_CONTROL */ "", 59638 /* MMU_ENQ_TRACE_IF_COUNTER */ "", 59639 /* MMU_ENQ_TRACE_IF_MASK_FIELD_0 */ "", 59640 /* MMU_ENQ_TRACE_IF_MASK_FIELD_1 */ "", 59641 /* MMU_ENQ_TRACE_IF_MASK_FIELD_2 */ "", 59642 /* MMU_ENQ_TRACE_IF_MASK_FIELD_3 */ "", 59643 /* MMU_ENQ_TRACE_IF_MASK_FIELD_4 */ "", 59644 /* MMU_ENQ_TRACE_IF_MASK_FIELD_5 */ "", 59645 /* MMU_ENQ_TRACE_IF_MASK_FIELD_6 */ "", 59646 /* MMU_ENQ_TRACE_IF_MASK_FIELD_7 */ "", 59647 /* MMU_ENQ_TRACE_IF_MASK_FIELD_8 */ "", 59648 /* MMU_ENQ_TRACE_IF_MASK_FIELD_9 */ "", 59649 /* MMU_ENQ_TRACE_IF_MASK_FIELD_10 */ "", 59650 /* MMU_ENQ_TRACE_IF_MASK_FIELD_11 */ "", 59651 /* MMU_ENQ_TRACE_IF_MASK_FIELD_12 */ "", 59652 /* MMU_ENQ_TRACE_IF_MASK_FIELD_13 */ "", 59653 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_0 */ "", 59654 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_1 */ "", 59655 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_2 */ "", 59656 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_3 */ "", 59657 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_4 */ "", 59658 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_5 */ "", 59659 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_6 */ "", 59660 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_7 */ "", 59661 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_8 */ "", 59662 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_9 */ "", 59663 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_10 */ "", 59664 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_11 */ "", 59665 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_12 */ "", 59666 /* MMU_ENQ_TRACE_IF_VALUE_FIELD_13 */ "", 59667 /* MMU_EPRG_ENABLE_ECCP_MEM */ "", 59668 /* MMU_EPRG_EN_COR_ERR_RPT */ "", 59669 /* MMU_EPRG_FIFO_CONFIG */ "MMU_EPRG_FIFO_STATUS_CTRL_64", 59670 /* MMU_EPRG_FIFO_STATUS */ "", 59671 /* MMU_EPRG_MEM_TM */ "", 59672 /* MMU_ERROR_INITIATION_DATA */ "", 59673 /* MMU_ES_ARB_TDM_TABLE_ECC_STATUS */ "", 59674 /* MMU_FC_RX_EN */ "", 59675 /* MMU_FC_TX_EN */ "", 59676 /* MMU_FIFO_IRDY_TH */ "", 59677 /* MMU_FIFO_SIZES */ "", 59678 /* MMU_GCFG_ALL_CPU_INT_EN */ "MMU_GCFG_ALL_FAIL_INT_EN", 59679 /* MMU_GCFG_ALL_CPU_INT_STAT */ "MMU_GCFG_ALL_CPU_INT_STAT", 59680 /* MMU_GCFG_BST_HW_SNAPSHOT_EN */ "", 59681 /* MMU_GCFG_BST_SNAPSHOT_ACTION_EN */ "", 59682 /* MMU_GCFG_BST_TRACKING_ENABLE */ "", 59683 /* MMU_GCFG_DLB_REPORT_ENABLE */ "", 59684 /* MMU_GCFG_ECC_SINGLE_BIT_ERRORS */ "", 59685 /* MMU_GCFG_GLB_CPU_INT_CLEAR */ "MMU_GCFG_GLB_CPU_INT_CLEAR", 59686 /* MMU_GCFG_GLB_CPU_INT_EN */ "MMU_GCFG_GLB_CPU_INT_EN", 59687 /* MMU_GCFG_GLB_CPU_INT_STAT */ "MMU_GCFG_GLB_CPU_INT_STAT", 59688 /* MMU_GCFG_MEM_FAIL_INT_CTR */ "", 59689 /* MMU_GCFG_MEM_SER_FIFO_STS */ "", 59690 /* MMU_GCFG_MISCCONFIG */ "", 59691 /* MMU_GCFG_PARITY_EN */ "", 59692 /* MMU_GCFG_PKTSTAT_OOBSTAT */ "", 59693 /* MMU_GCFG_SPLITTER */ "", 59694 /* MMU_GCFG_SPLITTER_RESP_STATUS */ "", 59695 /* MMU_GCFG_SPLITTER_SBUS_ERR_CAPTURE */ "", 59696 /* MMU_GCFG_TCB_FREEZE */ "", 59697 /* MMU_GENERAL_CONFIGURATION_REGISTER */ "", 59698 /* MMU_GENERAL_CONFIGURATION_REGISTER_2 */ "", 59699 /* MMU_GLBCFG_BST_SNAPSHOT_ACTION_EN */ "", 59700 /* MMU_GLBCFG_BST_TRACKING_ENABLE */ "", 59701 /* MMU_GLBCFG_CMIC_RESERVED */ "", 59702 /* MMU_GLBCFG_CPU_INT_EN */ "MMU_GLBCFG_CPU_INT_EN", 59703 /* MMU_GLBCFG_CPU_INT_SET */ "MMU_GLBCFG_CPU_INT_SET", 59704 /* MMU_GLBCFG_CPU_INT_STAT */ "MMU_GLBCFG_CPU_INT_STAT", 59705 /* MMU_GLBCFG_ECC_SINGLE_BIT_ERRORS */ "", 59706 /* MMU_GLBCFG_MEM_FAIL_INT_CTR */ "", 59707 /* MMU_GLBCFG_MEM_SER_FIFO_STS */ "", 59708 /* MMU_GLBCFG_MISCCONFIG */ "", 59709 /* MMU_GLBCFG_PKTSTAT */ "", 59710 /* MMU_GLBCFG_SPLITTER */ "", 59711 /* MMU_GLBCFG_SPLITTER_RESP_STATUS */ "", 59712 /* MMU_GLBCFG_SPLITTER_SBUS_ERR_CAPTURE */ "", 59713 /* MMU_GLBCFG_TIMESTAMP */ "", 59714 /* MMU_GLBCFG_TMBUS */ "", 59715 /* MMU_GLBCFG_UTC_TIMESTAMP */ "", 59716 /* MMU_GLOBAL_ADDR_TRANS_CFG */ "", 59717 /* MMU_GLOBAL_DRAM_NUMBER_SWAPPING */ "", 59718 /* MMU_GLOBAL_FULL_MC_DB_RANGE_0 */ "", 59719 /* MMU_GLOBAL_FULL_MC_DB_RANGE_1 */ "", 59720 /* MMU_GLOBAL_GENERAL_CFG_3 */ "", 59721 /* MMU_GLOBAL_MEM_OPTIONS */ "", 59722 /* MMU_GTIMER_CONFIGURATION */ "", 59723 /* MMU_GTIMER_TRIGGER */ "", 59724 /* MMU_IDF_WATER_MARK */ "", 59725 /* MMU_IDR_DESCRIPTOR_COUNTER */ "", 59726 /* MMU_IDR_PACKET_COUNTER */ "", 59727 /* MMU_INDIRECT_COMMAND */ "", 59728 /* MMU_INDIRECT_COMMAND_ADDRESS */ "", 59729 /* MMU_INDIRECT_COMMAND_DATA_INCREMENT */ "", 59730 /* MMU_INDIRECT_COMMAND_RD_DATA */ "", 59731 /* MMU_INDIRECT_COMMAND_WIDE_MEM */ "", 59732 /* MMU_INDIRECT_COMMAND_WR_DATA */ "", 59733 /* MMU_INDIRECT_FORCE_BUBBLE */ "", 59734 /* MMU_INITIATE_OPP_CRC_ERR */ "", 59735 /* MMU_INTERRUPT_MASK */ "", 59736 /* MMU_INTERRUPT_MASK_REGISTER */ "", 59737 /* MMU_INTERRUPT_REGISTER */ "", 59738 /* MMU_INTERRUPT_REGISTER_TEST */ "", 59739 /* MMU_INTFI_CMIC_RESERVED */ "", 59740 /* MMU_INTFI_CPU_INT_EN */ "", 59741 /* MMU_INTFI_CPU_INT_SET */ "", 59742 /* MMU_INTFI_CPU_INT_STAT */ "", 59743 /* MMU_INTFI_DD_TIMER */ "", 59744 /* MMU_INTFI_DD_TIMER_CFG */ "", 59745 /* MMU_INTFI_DD_TIMER_ENABLE */ "", 59746 /* MMU_INTFI_DD_TIMER_INT_MASK */ "", 59747 /* MMU_INTFI_DD_TIMER_INT_SET */ "", 59748 /* MMU_INTFI_DD_TIMER_INT_STATUS */ "", 59749 /* MMU_INTFI_EGR_PORT_CFG */ "", 59750 /* MMU_INTFI_IGNORE_PFC_XOFF_PKT_DISCARD */ "", 59751 /* MMU_INTFI_IGNORE_PORT_PFC_XOFF */ "", 59752 /* MMU_INTFI_MMU_PORT_TO_EBGRP_FC_BKP */ "", 59753 /* MMU_INTFI_MMU_PORT_TO_MMU_QUEUES_FC_BKP */ "", 59754 /* MMU_INTFI_MMU_PORT_TO_PHY_PORT_MAPPING */ "", 59755 /* MMU_INTFI_PFCPRI_PROFILE */ "", 59756 /* MMU_INTFI_PORT_BKP_CFG */ "", 59757 /* MMU_INTFI_PORT_FC_BKP */ "", 59758 /* MMU_INTFI_PORT_PFC_STATE */ "", 59759 /* MMU_INTFO_CMIC_RESERVED */ "", 59760 /* MMU_INTFO_CONFIG0 */ "", 59761 /* MMU_INTFO_CONGST_ST */ "", 59762 /* MMU_INTFO_ENABLE_ECCP_MEM */ "", 59763 /* MMU_INTFO_EN_COR_ERR_RPT */ "", 59764 /* MMU_INTFO_FC_TX_CONFIG_1 */ "", 59765 /* MMU_INTFO_FC_TX_CONFIG_2 */ "", 59766 /* MMU_INTFO_HW_UPDATE_DIS */ "", 59767 /* MMU_INTFO_MMU_PORT_TO_PHY_PORT_MAPPING */ "", 59768 /* MMU_INTFO_OOBFC_CHANNEL_BASE_64 */ "MMU_INTFO_OOBFC_CHANNEL_BASE", 59769 /* MMU_INTFO_OOBFC_CONGST_ST_EN2 */ "MMU_INTFO_OOBFC_CONGST_ST_EN2", 59770 /* MMU_INTFO_OOBFC_CONGST_ST_EN0_64 */ "MMU_INTFO_OOBFC_CONGST_ST_EN0", 59771 /* MMU_INTFO_OOBFC_CONGST_ST_EN1_64 */ "MMU_INTFO_OOBFC_CONGST_ST_EN1", 59772 /* MMU_INTFO_OOBFC_ENG_PORT_EN2 */ "MMU_INTFO_OOBFC_ENG_PORT_EN2", 59773 /* MMU_INTFO_OOBFC_ENG_PORT_EN0_64 */ "MMU_INTFO_OOBFC_ENG_PORT_EN0", 59774 /* MMU_INTFO_OOBFC_ENG_PORT_EN1_64 */ "MMU_INTFO_OOBFC_ENG_PORT_EN1", 59775 /* MMU_INTFO_OOBFC_ENG_Q_MAP0 */ "", 59776 /* MMU_INTFO_OOBFC_ENG_Q_MAP1 */ "", 59777 /* MMU_INTFO_OOBFC_ENG_Q_MAP2 */ "", 59778 /* MMU_INTFO_OOBFC_ENG_Q_MAP3 */ "", 59779 /* MMU_INTFO_OOBFC_GCS */ "", 59780 /* MMU_INTFO_OOBFC_ING_PORT_EN2 */ "MMU_INTFO_OOBFC_ING_PORT_EN2", 59781 /* MMU_INTFO_OOBFC_ING_PORT_EN0_64 */ "MMU_INTFO_OOBFC_ING_PORT_EN0", 59782 /* MMU_INTFO_OOBFC_ING_PORT_EN1_64 */ "MMU_INTFO_OOBFC_ING_PORT_EN1", 59783 /* MMU_INTFO_OOBFC_MSG_TX_CNT */ "", 59784 /* MMU_INTFO_OOBFC_STS */ "", 59785 /* MMU_INTFO_OOBFC_TX_IDLE */ "", 59786 /* MMU_INTFO_OOBIF_TX_TEST */ "", 59787 /* MMU_INTFO_THDI_TO_OOBFC_SP_ST */ "", 59788 /* MMU_INTFO_THDO_TO_OOBFC_SP_MC_ST */ "", 59789 /* MMU_INTFO_THDO_TO_OOBFC_SP_MERGED_ST */ "", 59790 /* MMU_INTFO_THDO_TO_OOBFC_SP_ST */ "", 59791 /* MMU_INTFO_THDR_TO_OOBFC_SP_ST */ "", 59792 /* MMU_INTFO_TMBUS */ "", 59793 /* MMU_INTFO_TO_XPORT_BKP */ "", 59794 /* MMU_INTFO_XPORT_BKP_HW_UPDATE_DIS */ "", 59795 /* MMU_INTR */ "", 59796 /* MMU_INTR_MASK */ "", 59797 /* MMU_IPCTR_CONFIG_0 */ "", 59798 /* MMU_IPCTR_COUNTER1 */ "", 59799 /* MMU_IPCTR_COUNTER0_DRESOURCE */ "", 59800 /* MMU_IPCTR_COUNTER1_SNAP */ "", 59801 /* MMU_IPCTR_DROP_TYPE */ "", 59802 /* MMU_IPCTR_ECC_COUNTERS */ "", 59803 /* MMU_IPCTR_ECC_DEBUG_0 */ "", 59804 /* MMU_IPCTR_ECC_ERROR_0 */ "", 59805 /* MMU_IPCTR_ECC_ERROR_0_MASK */ "", 59806 /* MMU_IPCTR_ECC_STATUS_0 */ "", 59807 /* MMU_IPCTR_EMA_DROP_COUNTER */ "", 59808 /* MMU_IPCTR_MIRROR_ACCEPT_UC_DROP_COUNTER */ "", 59809 /* MMU_IPCTR_PG_COUNTER0_DEBUG_0 */ "", 59810 /* MMU_IPCTR_PG_COUNTER1_DEBUG_0 */ "", 59811 /* MMU_IPCTR_SRC_CONTEXT_COUNTER_DEBUG */ "", 59812 /* MMU_IPMC_GRP_TBL_ECC_STATUS */ "", 59813 /* MMU_IPMC_VLAN_TBL_ECC_STATUS */ "", 59814 /* MMU_IPT_DATA_FIFO_CONFIGURATION_REGISTER */ "", 59815 /* MMU_IPT_DESCRIPTOR_COUNTER */ "", 59816 /* MMU_IPT_PACKET_COUNTER */ "", 59817 /* MMU_ITE_CFG_ECC_DEBUG_0 */ "", 59818 /* MMU_ITE_CFG_ECC_ERROR_0 */ "", 59819 /* MMU_ITE_CFG_ECC_ERROR_0_MASK */ "", 59820 /* MMU_ITE_CFG_ECC_STATUS_0 */ "", 59821 /* MMU_ITE_CFG_ECC_STATUS_1 */ "", 59822 /* MMU_ITE_CTRL_DEBUG_0 */ "", 59823 /* MMU_ITE_DEBUG_STATUS_0 */ "", 59824 /* MMU_ITE_ECC_COUNTERS */ "", 59825 /* MMU_ITE_EMA_ACCEPT_COUNT */ "", 59826 /* MMU_ITE_EMA_DROP_COUNT */ "", 59827 /* MMU_ITE_EMA_POOL_CONG_DETECT_THRESH_0 */ "", 59828 /* MMU_ITE_EMA_POOL_CONG_DETECT_THRESH_1 */ "", 59829 /* MMU_ITE_EMA_POOL_CONG_DETECT_THRESH_2 */ "", 59830 /* MMU_ITE_EMA_POOL_STATUS */ "", 59831 /* MMU_ITE_EMA_STATUS */ "", 59832 /* MMU_ITE_EMC_BACKPRESSURE_DEBUG_CONFIG */ "", 59833 /* MMU_ITE_EMC_BACKPRESSURE_DEBUG_STATUS */ "", 59834 /* MMU_ITE_ERROR_0 */ "", 59835 /* MMU_ITE_ERROR_0_MASK */ "", 59836 /* MMU_ITE_PACKET_PTR_STORE_DEBUG_0 */ "", 59837 /* MMU_ITE_QMGR_FLL_DEBUG_0 */ "", 59838 /* MMU_ITE_QMGR_QLL_DEBUG_0 */ "", 59839 /* MMU_ITE_Q_FLUSH_STATUS_0 */ "", 59840 /* MMU_ITE_WORK_QUEUE_DEBUG_0 */ "", 59841 /* MMU_ITMCFG_CMIC_RESERVED */ "", 59842 /* MMU_ITMCFG_CPU_INT_EN */ "MMU_ITMCFG_CPU_INT_EN", 59843 /* MMU_ITMCFG_CPU_INT_SET */ "MMU_ITMCFG_CPU_INT_SET", 59844 /* MMU_ITMCFG_CPU_INT_STAT */ "MMU_ITMCFG_CPU_INT_STAT", 59845 /* MMU_ITMCFG_ECC_SINGLE_BIT_ERRORS */ "", 59846 /* MMU_ITMCFG_MEM_FAIL_INT_CTR */ "", 59847 /* MMU_ITMCFG_MEM_SER_FIFO_STS */ "", 59848 /* MMU_LBM_COUNTER */ "", 59849 /* MMU_LLFC_RX_CONFIG */ "", 59850 /* MMU_LLFC_TX_CONFIG */ "", 59851 /* MMU_LLFC_TX_CONFIG_1 */ "", 59852 /* MMU_LLFC_TX_CONFIG_2 */ "", 59853 /* MMU_LLFC_TX_CONFIG_3 */ "", 59854 /* MMU_LLFC_TX_CONFIG_4 */ "", 59855 /* MMU_MAX_CELL_LIMIT */ "", 59856 /* MMU_MB_CMIC_RESERVED */ "", 59857 /* MMU_MB_DEBUG */ "", 59858 /* MMU_MB_ENABLE_ECCP_MEM */ "", 59859 /* MMU_MB_EN_COR_ERR_RPT */ "", 59860 /* MMU_MB_TCB_ENABLE_ECCP_MEM */ "", 59861 /* MMU_MB_TCB_EN_COR_ERR_RPT */ "", 59862 /* MMU_MB_TMBUS */ "", 59863 /* MMU_MEM1_CLINKE_ECC_STATUS */ "", 59864 /* MMU_MEM1_CLINKI_ECC_STATUS */ "", 59865 /* MMU_MEM1_CLINK_ECC_COUNTERS */ "", 59866 /* MMU_MEM_FAIL_ADDR_64 */ "MMU_MEM_FAIL_ADDR", 59867 /* MMU_MISC_STATUS */ "", 59868 /* MMU_MMU_DDP_COUNTERS */ "", 59869 /* MMU_MTP_COS */ "", 59870 /* MMU_MTP_CPU_COS */ "", 59871 /* MMU_MTRO_CONFIG */ "", 59872 /* MMU_MTRO_COUNTER_OVERFLOW */ "", 59873 /* MMU_MTRO_CPU_INT_EN */ "", 59874 /* MMU_MTRO_CPU_INT_SET */ "", 59875 /* MMU_MTRO_CPU_INT_STAT */ "", 59876 /* MMU_MTRO_CPU_L1_TO_L0_MAPPING */ "", 59877 /* MMU_MTRO_CPU_PKT_ECC_STATUS */ "", 59878 /* MMU_MTRO_ENABLE_ECCP_MEM */ "", 59879 /* MMU_MTRO_EN_COR_ERR_RPT */ "", 59880 /* MMU_MTRO_HULL_MODE_ENABLE */ "", 59881 /* MMU_MTRO_MMUQ_SCHQ_CFG */ "", 59882 /* MMU_MTRO_MMUQ_SCHQ_PROFILE */ "", 59883 /* MMU_MTRO_PORT_ENTITY_DISABLE */ "", 59884 /* MMU_MTRO_RSVD_REG */ "", 59885 /* MMU_MTRO_SHAPE_G0_BUCKET_ECC_STATUS */ "", 59886 /* MMU_MTRO_SHAPE_G0_CONFIG_ECC_STATUS */ "", 59887 /* MMU_MTRO_SHAPE_G1_BUCKET_ECC_STATUS */ "", 59888 /* MMU_MTRO_SHAPE_G1_CONFIG_ECC_STATUS */ "", 59889 /* MMU_MTRO_SHAPE_G2_BUCKET_ECC_STATUS */ "", 59890 /* MMU_MTRO_SHAPE_G2_CONFIG_ECC_STATUS */ "", 59891 /* MMU_MTRO_SHAPE_G3_BUCKET_ECC_STATUS */ "", 59892 /* MMU_MTRO_SHAPE_G3_CONFIG_ECC_STATUS */ "", 59893 /* MMU_MTRO_TMBUS */ "", 59894 /* MMU_OCB_CONFIGURATION_REGISTER */ "", 59895 /* MMU_OQS_AGED_STATUS0 */ "", 59896 /* MMU_OQS_AGED_STATUS1 */ "", 59897 /* MMU_OQS_AGED_STATUS2 */ "", 59898 /* MMU_OQS_AGER_DST_PORT_MAP */ "", 59899 /* MMU_OQS_AGER_LIMIT */ "", 59900 /* MMU_OQS_AGER_Q_PROFILE_HP_MMUQ */ "", 59901 /* MMU_OQS_ARBITER_CONFIG */ "", 59902 /* MMU_OQS_CMIC_RESERVED */ "", 59903 /* MMU_OQS_CPU_INT_EN */ "", 59904 /* MMU_OQS_CPU_INT_SET */ "", 59905 /* MMU_OQS_CPU_INT_STAT */ "", 59906 /* MMU_OQS_DEBUG */ "", 59907 /* MMU_OQS_EMERGENCY_TIMEOUT */ "", 59908 /* MMU_OQS_ENABLE_ECCP_MEM */ "", 59909 /* MMU_OQS_ENQ_CONFIG */ "", 59910 /* MMU_OQS_EN_COR_ERR_RPT */ "", 59911 /* MMU_OQS_RECEPTION_FIFO_CONTROL */ "", 59912 /* MMU_OQS_TMBUS */ "", 59913 /* MMU_OQS_TOQ_CELL_TX_CREDIT */ "", 59914 /* MMU_OQS_WATERMARK */ "", 59915 /* MMU_OQS_WATERMARK_CONTROL */ "", 59916 /* MMU_OTP_IN */ "", 59917 /* MMU_OVQ_REPL_GROUP_DFT */ "", 59918 /* MMU_OVQ_REPL_GROUP_PDA */ "", 59919 /* MMU_PARITY_ERR_CNT */ "", 59920 /* MMU_PAR_ERR_INITIATE */ "", 59921 /* MMU_PAR_ERR_MEM_MASK */ "", 59922 /* MMU_PCMI_0 */ "", 59923 /* MMU_PCMI_1 */ "", 59924 /* MMU_PCMI_2 */ "", 59925 /* MMU_PCMI_3 */ "", 59926 /* MMU_PCMI_4 */ "", 59927 /* MMU_PCMI_0_S */ "", 59928 /* MMU_PCMI_0_T */ "", 59929 /* MMU_PCMI_1_S */ "", 59930 /* MMU_PCMI_1_T */ "", 59931 /* MMU_PCMI_2_S */ "", 59932 /* MMU_PCMI_2_T */ "", 59933 /* MMU_PCMI_3_S */ "", 59934 /* MMU_PCMI_3_T */ "", 59935 /* MMU_PCMI_4_S */ "", 59936 /* MMU_PCMI_4_T */ "", 59937 /* MMU_PDC_ASYNC_FIFO_CFG */ "", 59938 /* MMU_PDC_CONFIGURATION_REGISTER */ "", 59939 /* MMU_PEC_ASYNC_FIFO_CFG */ "", 59940 /* MMU_PHY_CALIB_EN */ "", 59941 /* MMU_PKTHDR0_ECC_STATUS */ "", 59942 /* MMU_PKTLENGTH_ECC_STATUS */ "", 59943 /* MMU_PKTLINK_ECC_STATUS */ "", 59944 /* MMU_PORT_CREDIT */ "", 59945 /* MMU_PORT_MMUQ_SCHQ_CFG */ "", 59946 /* MMU_PORT_PREEMPTION_CONFIG */ "", 59947 /* MMU_PORT_TO_DEVICE_PORT_MAPPING */ "", 59948 /* MMU_PORT_TO_LOGIC_PORT_MAPPING */ "", 59949 /* MMU_PORT_TO_PHY_PORT_MAPPING */ "", 59950 /* MMU_PORT_TO_SYSTEM_PORT_MAPPING */ "", 59951 /* MMU_PPSCH_CMIC_RESERVED */ "", 59952 /* MMU_PPSCH_ITM_BUBBLE_INSERTION_CYCLE */ "", 59953 /* MMU_PPSCH_RL_CREDIT */ "", 59954 /* MMU_PPSCH_SATISFIED_EB_INTERVAL */ "", 59955 /* MMU_PPSCH_SCHQ_MMUQ_PROFILE */ "", 59956 /* MMU_PQE_ENABLE_ECCP_MEM */ "", 59957 /* MMU_PQE_EN_COR_ERR_RPT */ "", 59958 /* MMU_PQE_LVM */ "", 59959 /* MMU_PREEMPT_RESUME_DELAY */ "", 59960 /* MMU_PTSCH_CAL_CONFIG */ "", 59961 /* MMU_PTSCH_CMIC_RESERVED */ "", 59962 /* MMU_PTSCH_CPU_MGMT_LB_RATIOS */ "", 59963 /* MMU_PTSCH_EB_CREDIT_CONFIG */ "", 59964 /* MMU_PTSCH_EB_SATISFIED_THRESHOLD */ "", 59965 /* MMU_PTSCH_FEATURE_CTRL */ "", 59966 /* MMU_PTSCH_MIN_SPACING_FOUR_CELL */ "", 59967 /* MMU_PTSCH_MIN_SPACING_ONE_CELL */ "", 59968 /* MMU_PTSCH_MIN_SPACING_THREE_CELL */ "", 59969 /* MMU_PTSCH_MIN_SPACING_TWO_CELL */ "", 59970 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING */ "", 59971 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB0 */ "", 59972 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB1 */ "", 59973 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB2 */ "", 59974 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB3 */ "", 59975 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB4 */ "", 59976 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB5 */ "", 59977 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB6 */ "", 59978 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB7 */ "", 59979 /* MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_PICK_MIN_SPACING */ "", 59980 /* MMU_QCN_CNM_CTRL_64 */ "", 59981 /* MMU_QCN_CNM_CTRL_0_64 */ "MMU_QCN_CNM_CTRL_0", 59982 /* MMU_QCN_CNM_CTRL_1_64 */ "MMU_QCN_CNM_CTRL_1", 59983 /* MMU_QCN_CNM_LIMIT */ "", 59984 /* MMU_QCN_CPQ_SEQ */ "", 59985 /* MMU_QCN_EN_COR_ERR_RPT */ "", 59986 /* MMU_QCN_MEM_DEBUG */ "", 59987 /* MMU_QCN_MEM_TM */ "", 59988 /* MMU_QCN_MEM_TM_1 */ "", 59989 /* MMU_QCN_PARITY_ERR */ "", 59990 /* MMU_QCN_QUEUE_STS */ "", 59991 /* MMU_QSCH_CPU_L1_QUEUE_MASK */ "", 59992 /* MMU_QSCH_CPU_L1_TO_L0_MAPPING */ "", 59993 /* MMU_QSCH_CPU_PORT_CONFIG */ "", 59994 /* MMU_QSCH_DEBUG_FORCE_CPU_COSMASK */ "", 59995 /* MMU_QSCH_ENABLE_ECCP_MEM */ "", 59996 /* MMU_QSCH_EN_COR_ERR_RPT */ "", 59997 /* MMU_QSCH_MMUQ_TO_SCHQ_MAP */ "", 59998 /* MMU_QSCH_PORT_CONFIG */ "", 59999 /* MMU_QSCH_PORT_EMPTY_STATUS */ "", 60000 /* MMU_QSCH_PORT_FLUSH */ "", 60001 /* MMU_QSCH_RESERVED */ "", 60002 /* MMU_QSCH_SPECIAL_CONFIG */ "", 60003 /* MMU_QSCH_STRONG_BIAS_THRESHOLD */ "", 60004 /* MMU_QSCH_TMBUS */ "", 60005 /* MMU_QSCH_VOQ_FAIRNESS_CONFIG */ "", 60006 /* MMU_QSTRUCT_ECC_1B_COUNTER */ "", 60007 /* MMU_QSTRUCT_ECC_2B_COUNTER */ "", 60008 /* MMU_RAF_TOTAL_SIZE_WATER_MARK */ "", 60009 /* MMU_REG_0085 */ "", 60010 /* MMU_REG_0086 */ "", 60011 /* MMU_REG_0087 */ "", 60012 /* MMU_REG_0090 */ "", 60013 /* MMU_REG_0091 */ "", 60014 /* MMU_REG_0092 */ "", 60015 /* MMU_REG_0093 */ "", 60016 /* MMU_REG_0102 */ "", 60017 /* MMU_REG_0103 */ "", 60018 /* MMU_REG_0104 */ "", 60019 /* MMU_REG_0106 */ "", 60020 /* MMU_REG_0107 */ "", 60021 /* MMU_REG_0108 */ "", 60022 /* MMU_REG_0109 */ "", 60023 /* MMU_REG_00AF */ "", 60024 /* MMU_REG_00B0 */ "", 60025 /* MMU_REG_00B1 */ "", 60026 /* MMU_REG_00B2 */ "", 60027 /* MMU_REG_00B3 */ "", 60028 /* MMU_REG_00B4 */ "", 60029 /* MMU_REG_00C1 */ "", 60030 /* MMU_REG_00CA */ "", 60031 /* MMU_REG_00CB */ "", 60032 /* MMU_REG_00CC */ "", 60033 /* MMU_REG_00CD */ "", 60034 /* MMU_REG_00CF */ "", 60035 /* MMU_REG_0B1 */ "", 60036 /* MMU_REPL_GRP_TBL_ECC_STATUS */ "", 60037 /* MMU_REPL_HEAD_TBL_ECC_STATUS */ "", 60038 /* MMU_REPL_LIST_TBL_ECC_STATUS */ "", 60039 /* MMU_REPL_MAP_TBL_ECC_STATUS */ "", 60040 /* MMU_REPL_STATE_ERRPTR */ "", 60041 /* MMU_REPL_STATE_MEMDEBUG */ "", 60042 /* MMU_REPL_STATE_TBL_ECC_STATUS */ "", 60043 /* MMU_RESERVED_MIRROR_ADDR */ "", 60044 /* MMU_RESERVED_MTCD */ "", 60045 /* MMU_RESERVED_MTCP */ "", 60046 /* MMU_RESERVED_PCMI_0 */ "", 60047 /* MMU_RESERVED_PCMI_1 */ "", 60048 /* MMU_RESERVED_PCMI_2 */ "", 60049 /* MMU_RESERVED_PCMI_3 */ "", 60050 /* MMU_RESERVED_PCMI_4 */ "", 60051 /* MMU_RESERVED_PCMI_0_S */ "", 60052 /* MMU_RESERVED_PCMI_0_T */ "", 60053 /* MMU_RESERVED_PCMI_1_S */ "", 60054 /* MMU_RESERVED_PCMI_1_T */ "", 60055 /* MMU_RESERVED_PCMI_2_S */ "", 60056 /* MMU_RESERVED_PCMI_2_T */ "", 60057 /* MMU_RESERVED_PCMI_3_S */ "", 60058 /* MMU_RESERVED_PCMI_3_T */ "", 60059 /* MMU_RESERVED_PCMI_4_S */ "", 60060 /* MMU_RESERVED_PCMI_4_T */ "", 60061 /* MMU_RESERVED_SPARE_0 */ "", 60062 /* MMU_RESERVED_SPARE_1 */ "", 60063 /* MMU_RESERVED_SPARE_2 */ "", 60064 /* MMU_RESERVED_SPARE_3 */ "", 60065 /* MMU_RL_BQ_DEBUG */ "", 60066 /* MMU_RL_CMIC_RESERVED */ "", 60067 /* MMU_RL_CONFIG */ "", 60068 /* MMU_RL_CPU_INT_EN */ "MMU_RL_CPU_INT_EN", 60069 /* MMU_RL_CPU_INT_SET */ "MMU_RL_CPU_INT_SET", 60070 /* MMU_RL_CPU_INT_STAT */ "MMU_RL_CPU_INT_STAT", 60071 /* MMU_RL_CT_TILE_ACTIVITY */ "", 60072 /* MMU_RL_CT_TILE_ACTIVITY2 */ "", 60073 /* MMU_RL_DEBUG */ "", 60074 /* MMU_RL_DEBUG_CNT_CONFIG */ "", 60075 /* MMU_RL_DEBUG_PKT_CNT */ "", 60076 /* MMU_RL_EBP_OVRD */ "", 60077 /* MMU_RL_EBQ_CONFIG */ "", 60078 /* MMU_RL_EBQ_DEBUG */ "", 60079 /* MMU_RL_ENABLE_ECCP_MEM */ "", 60080 /* MMU_RL_EN_COR_ERR_RPT */ "", 60081 /* MMU_RL_RQE_FIFO_DEBUG */ "", 60082 /* MMU_RL_TMBUS */ "", 60083 /* MMU_RQE_CELL_QUEUE_HEADA */ "", 60084 /* MMU_RQE_CELL_QUEUE_HEADB */ "", 60085 /* MMU_RQE_CELL_QUEUE_HEAD_STAT */ "", 60086 /* MMU_RQE_CELL_QUEUE_TAILA */ "", 60087 /* MMU_RQE_CELL_QUEUE_TAILB */ "", 60088 /* MMU_RQE_CELL_QUEUE_TAIL_STAT */ "", 60089 /* MMU_RQE_CMIC_RESERVED */ "", 60090 /* MMU_RQE_ENABLE_ECCP_MEM */ "", 60091 /* MMU_RQE_EN_COR_ERR_RPT */ "", 60092 /* MMU_RQE_FIFO_ECC_STATUS */ "", 60093 /* MMU_RQE_FREELIST_CONTROL */ "", 60094 /* MMU_RQE_INFOTBL_FL_PTR */ "", 60095 /* MMU_RQE_INFOTBL_FP_INIT */ "", 60096 /* MMU_RQE_INT_EN */ "", 60097 /* MMU_RQE_INT_SET */ "", 60098 /* MMU_RQE_INT_STAT */ "", 60099 /* MMU_RQE_INVALID_DST */ "", 60100 /* MMU_RQE_L3_PURGE_STAT */ "", 60101 /* MMU_RQE_MAX_SHAPER_EN */ "", 60102 /* MMU_RQE_MAX_SHAPER_LIMIT_COUNT */ "", 60103 /* MMU_RQE_MAX_SHAPER_RATE */ "", 60104 /* MMU_RQE_MAX_SHAPER_THRESHOLD */ "", 60105 /* MMU_RQE_MAX_SHAPER_THRESHOLD_CLEAR */ "", 60106 /* MMU_RQE_PKT_QUEUE_HEAD */ "", 60107 /* MMU_RQE_PKT_QUEUE_TAIL */ "", 60108 /* MMU_RQE_PRIORITY_SCHEDULING_TYPE */ "", 60109 /* MMU_RQE_PRIORITY_WERR_WEIGHT */ "", 60110 /* MMU_RQE_PTAIL_PHEAD_CNT_CELLQ */ "", 60111 /* MMU_RQE_PTAIL_PREFETCH_CNT_PKTQ */ "", 60112 /* MMU_RQE_QUEUE_SNAPSHOT_EN */ "", 60113 /* MMU_RQE_REPL_CONFIG */ "", 60114 /* MMU_RQE_REPL_PORT_AGG_MAP */ "", 60115 /* MMU_RQE_SCH_INACTIVE_CONTROL */ "", 60116 /* MMU_RQE_TMBUS */ "", 60117 /* MMU_RQE_TX_CREDIT_TO_RL */ "", 60118 /* MMU_RQE_TX_CREDIT_TO_SCB */ "", 60119 /* MMU_RQE_WERR_MAXSC_CLEAR */ "", 60120 /* MMU_RQE_WERR_MAXSC_RESET */ "", 60121 /* MMU_RQE_WERR_WORKING_COUNTS */ "", 60122 /* MMU_RQE_WERR_WORKING_COUNTS_CLEAR */ "", 60123 /* MMU_RXD_NODST_PKT */ "", 60124 /* MMU_RXD_PKT */ "", 60125 /* MMU_RXD_PKT_64 */ "MMU_RXD_PKT", 60126 /* MMU_SBUS_BROADCAST_ID */ "", 60127 /* MMU_SBUS_LAST_IN_CHAIN */ "", 60128 /* MMU_SCB_ARBITER_AGER_CFG */ "", 60129 /* MMU_SCB_ARBITER_CFG */ "", 60130 /* MMU_SCB_CMIC_RESERVED */ "", 60131 /* MMU_SCB_CPU_INT_EN */ "", 60132 /* MMU_SCB_CPU_INT_SET */ "", 60133 /* MMU_SCB_CPU_INT_STAT */ "", 60134 /* MMU_SCB_DEBUG */ "", 60135 /* MMU_SCB_ENABLE_ECCP_MEM */ "", 60136 /* MMU_SCB_EN_COR_ERR_RPT */ "", 60137 /* MMU_SCB_OQS_CREDITS */ "", 60138 /* MMU_SCB_OQS_IDLE_CYCLES_CNT */ "", 60139 /* MMU_SCB_SCQE_CNT_OVERFLOW */ "", 60140 /* MMU_SCB_SCQE_CNT_UNDERFLOW */ "", 60141 /* MMU_SCB_SCQ_CELL_CNT_STATUS */ "", 60142 /* MMU_SCB_SCQ_FAP_HWM_COUNT */ "", 60143 /* MMU_SCB_SCQ_FIFO_STATUS */ "", 60144 /* MMU_SCB_SCQ_FL_STATUS */ "", 60145 /* MMU_SCB_SCQ_HP_FIFO_OVERFLOW */ "", 60146 /* MMU_SCB_SCQ_HP_FIFO_UNDERFLOW */ "", 60147 /* MMU_SCB_SCQ_PKT_CELL_CNT_STATUS */ "", 60148 /* MMU_SCB_SOURCE_PORT_CFG */ "", 60149 /* MMU_SCB_SRAF_FIFO_THRESH */ "", 60150 /* MMU_SCB_SRAF_HWM_COUNT */ "", 60151 /* MMU_SCB_TMBUS */ "", 60152 /* MMU_SCFG_ECC_SINGLE_BIT_ERRORS */ "", 60153 /* MMU_SCFG_MEM_FAIL_INT_CTR */ "", 60154 /* MMU_SCFG_MEM_SER_FIFO_STS */ "", 60155 /* MMU_SCFG_MISCCONFIG */ "", 60156 /* MMU_SCFG_PARITY_EN */ "", 60157 /* MMU_SCFG_SC_CPU_INT_CLEAR */ "MMU_SCFG_SC_CPU_INT_CLEAR", 60158 /* MMU_SCFG_SC_CPU_INT_EN */ "MMU_SCFG_SC_CPU_INT_EN", 60159 /* MMU_SCFG_SC_CPU_INT_STAT */ "MMU_SCFG_SC_CPU_INT_STAT", 60160 /* MMU_SCFG_START_BY_START_ERROR */ "", 60161 /* MMU_SCFG_TOQ_MC_CFG0 */ "", 60162 /* MMU_SCFG_TOQ_MC_CFG1 */ "", 60163 /* MMU_SCFG_TOQ_MC_CFG2 */ "", 60164 /* MMU_SEDCFG_ECC_SINGLE_BIT_ERRORS */ "", 60165 /* MMU_SEDCFG_MEM_FAIL_INT_CTR */ "", 60166 /* MMU_SEDCFG_MEM_SER_FIFO_STS */ "", 60167 /* MMU_SEDCFG_MISCCONFIG */ "", 60168 /* MMU_SEDCFG_PARITY_EN */ "", 60169 /* MMU_SEDCFG_SED_CPU_INT_CLEAR */ "MMU_SEDCFG_SED_CPU_INT_CLEAR", 60170 /* MMU_SEDCFG_SED_CPU_INT_EN */ "MMU_SEDCFG_SED_CPU_INT_EN", 60171 /* MMU_SEDCFG_SED_CPU_INT_STAT */ "MMU_SEDCFG_SED_CPU_INT_STAT", 60172 /* MMU_SEDCFG_START_BY_START_ERROR */ "", 60173 /* MMU_SEDCFG_START_BY_START_ERROR_SPLIT0 */ "", 60174 /* MMU_SEDCFG_START_BY_START_ERROR_SPLIT1 */ "", 60175 /* MMU_STATUS */ "", 60176 /* MMU_TCB_ENABLE_ECCP_MEM */ "", 60177 /* MMU_TCB_EN_COR_ERR_RPT */ "", 60178 /* MMU_TDM_DEBUG */ "", 60179 /* MMU_TDM_EN_COR_ERR_RPT */ "", 60180 /* MMU_THDI_BSTCONFIG */ "", 60181 /* MMU_THDI_BST_HDRM_POOL */ "", 60182 /* MMU_THDI_BST_HDRM_POOL_CNT */ "", 60183 /* MMU_THDI_BST_PG_HDRM_PROFILE */ "", 60184 /* MMU_THDI_BST_PG_SHARED_PROFILE */ "", 60185 /* MMU_THDI_BST_PORTSP_SHARED_PROFILE */ "", 60186 /* MMU_THDI_BST_SP_SHARED */ "", 60187 /* MMU_THDI_BST_SP_SHARED_CNT */ "", 60188 /* MMU_THDI_BST_TRIGGER_STATUS_TYPE */ "", 60189 /* MMU_THDI_BUFFER_CELL_LIMIT_SP */ "", 60190 /* MMU_THDI_BYPASS */ "", 60191 /* MMU_THDI_CELL_RESET_LIMIT_OFFSET_SP */ "", 60192 /* MMU_THDI_CELL_SPAP_RED_OFFSET_SP */ "", 60193 /* MMU_THDI_CELL_SPAP_YELLOW_OFFSET_SP */ "", 60194 /* MMU_THDI_CMIC_RESERVED */ "", 60195 /* MMU_THDI_CPU_INT_EN */ "", 60196 /* MMU_THDI_CPU_INT_SET */ "", 60197 /* MMU_THDI_CPU_INT_STAT */ "", 60198 /* MMU_THDI_CPU_SPID_OVERRIDE_CTRL */ "", 60199 /* MMU_THDI_ENABLE_ECCP_MEM */ "", 60200 /* MMU_THDI_EN_COR_ERR_RPT */ "", 60201 /* MMU_THDI_FLOW_CONTROL_XOFF_STATE */ "", 60202 /* MMU_THDI_HDRM_BUFFER_CELL_LIMIT_HP */ "", 60203 /* MMU_THDI_HDRM_POOL_COUNT_HP */ "", 60204 /* MMU_THDI_HDRM_POOL_STATUS */ "", 60205 /* MMU_THDI_ING_PORT_CONFIG */ "", 60206 /* MMU_THDI_INTR */ "", 60207 /* MMU_THDI_INTR_MASK */ "", 60208 /* MMU_THDI_LOSSLESS_PG_DROP */ "", 60209 /* MMU_THDI_MC_SPID_OVERRIDE_CTRL */ "", 60210 /* MMU_THDI_MEM_INIT_STATUS */ "", 60211 /* MMU_THDI_MIRROR_SPID_OVERRIDE_CTRL */ "", 60212 /* MMU_THDI_NONUC_INPPRI_PG_PROFILE */ "", 60213 /* MMU_THDI_PFCPRI_PG_PROFILE */ "", 60214 /* MMU_THDI_PG_PROFILE */ "", 60215 /* MMU_THDI_PIPE_COUNTER_OVERFLOW_ID */ "", 60216 /* MMU_THDI_PIPE_COUNTER_UNDERFLOW_ID */ "", 60217 /* MMU_THDI_POOL_CONFIG */ "", 60218 /* MMU_THDI_POOL_COUNTER_OVERFLOW_ID */ "", 60219 /* MMU_THDI_POOL_COUNTER_UNDERFLOW_ID */ "", 60220 /* MMU_THDI_POOL_DROP_COUNT_HP */ "", 60221 /* MMU_THDI_POOL_DROP_STATE */ "", 60222 /* MMU_THDI_POOL_SHARED_COUNT_SP */ "", 60223 /* MMU_THDI_PORT_LIMIT_STATES */ "", 60224 /* MMU_THDI_SCR_CNT_STATUS */ "", 60225 /* MMU_THDI_TMBUS */ "", 60226 /* MMU_THDI_UC_INPPRI_PG_PROFILE */ "", 60227 /* MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE */ "", 60228 /* MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE0 */ "", 60229 /* MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE1 */ "", 60230 /* MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE2 */ "", 60231 /* MMU_THDM_DB_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE3 */ "", 60232 /* MMU_THDM_DB_DEVICE_BST_STAT */ "", 60233 /* MMU_THDM_DB_DEVICE_BYPASS */ "", 60234 /* MMU_THDM_DB_DEVICE_THR_CONFIG */ "", 60235 /* MMU_THDM_DB_ENABLE_ECCP_MEM */ "", 60236 /* MMU_THDM_DB_EN_COR_ERR_RPT */ "", 60237 /* MMU_THDM_DB_MEMORY_TM */ "", 60238 /* MMU_THDM_DB_PKTPTR_CACHE */ "MMU_THDM_DB_PKTPTR_CACHE", 60239 /* MMU_THDM_DB_PKTPTR_CACHE_STATUS */ "MMU_THDM_DB_PKTPTR_CACHE_STATUS", 60240 /* MMU_THDM_DB_POOL_DROP_STATES */ "", 60241 /* MMU_THDM_DB_POOL_MCUC_BST_STAT */ "", 60242 /* MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD */ "", 60243 /* MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE0 */ "", 60244 /* MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE1 */ "", 60245 /* MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE2 */ "", 60246 /* MMU_THDM_DB_POOL_MCUC_BST_THRESHOLD_XPE3 */ "", 60247 /* MMU_THDM_DB_POOL_MC_BST_STAT */ "", 60248 /* MMU_THDM_DB_POOL_MC_BST_THRESHOLD */ "", 60249 /* MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE0 */ "", 60250 /* MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE1 */ "", 60251 /* MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE2 */ "", 60252 /* MMU_THDM_DB_POOL_MC_BST_THRESHOLD_XPE3 */ "", 60253 /* MMU_THDM_DB_POOL_MC_SHARED_COUNT */ "", 60254 /* MMU_THDM_DB_POOL_RED_RESUME_LIMIT */ "", 60255 /* MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE0 */ "", 60256 /* MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE1 */ "", 60257 /* MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE2 */ "", 60258 /* MMU_THDM_DB_POOL_RED_RESUME_LIMIT_XPE3 */ "", 60259 /* MMU_THDM_DB_POOL_RED_SHARED_LIMIT */ "", 60260 /* MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE0 */ "", 60261 /* MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE1 */ "", 60262 /* MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE2 */ "", 60263 /* MMU_THDM_DB_POOL_RED_SHARED_LIMIT_XPE3 */ "", 60264 /* MMU_THDM_DB_POOL_RESUME_LIMIT */ "", 60265 /* MMU_THDM_DB_POOL_RESUME_LIMIT_XPE0 */ "", 60266 /* MMU_THDM_DB_POOL_RESUME_LIMIT_XPE1 */ "", 60267 /* MMU_THDM_DB_POOL_RESUME_LIMIT_XPE2 */ "", 60268 /* MMU_THDM_DB_POOL_RESUME_LIMIT_XPE3 */ "", 60269 /* MMU_THDM_DB_POOL_SHARED_COUNT */ "", 60270 /* MMU_THDM_DB_POOL_SHARED_LIMIT */ "", 60271 /* MMU_THDM_DB_POOL_SHARED_LIMIT_XPE0 */ "", 60272 /* MMU_THDM_DB_POOL_SHARED_LIMIT_XPE1 */ "", 60273 /* MMU_THDM_DB_POOL_SHARED_LIMIT_XPE2 */ "", 60274 /* MMU_THDM_DB_POOL_SHARED_LIMIT_XPE3 */ "", 60275 /* MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT */ "", 60276 /* MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE0 */ "", 60277 /* MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE1 */ "", 60278 /* MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE2 */ "", 60279 /* MMU_THDM_DB_POOL_YELLOW_RESUME_LIMIT_XPE3 */ "", 60280 /* MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT */ "", 60281 /* MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE0 */ "", 60282 /* MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE1 */ "", 60283 /* MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE2 */ "", 60284 /* MMU_THDM_DB_POOL_YELLOW_SHARED_LIMIT_XPE3 */ "", 60285 /* MMU_THDM_DB_PORTSP_BST_THRESHOLD */ "", 60286 /* MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE0 */ "", 60287 /* MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE1 */ "", 60288 /* MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE2 */ "", 60289 /* MMU_THDM_DB_PORTSP_BST_THRESHOLD_XPE3 */ "", 60290 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP0_64 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP0", 60291 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP1_64 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP1", 60292 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP", 60293 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_SPLIT0 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP_SPLIT0", 60294 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_SPLIT1 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP_SPLIT1", 60295 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_SPLIT0_XPE0 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP_SPLIT0", 60296 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_SPLIT1_XPE0 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP_SPLIT1", 60297 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE0 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP", 60298 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE1 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP", 60299 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE2 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP", 60300 /* MMU_THDM_DB_PORTSP_DROP_STATE_BMP_64_XPE3 */ "MMU_THDM_DB_PORTSP_DROP_STATE_BMP", 60301 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP0_64 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP0", 60302 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP1_64 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP1", 60303 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP", 60304 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_SPLIT0 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_SPLIT0", 60305 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_SPLIT1 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_SPLIT1", 60306 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_SPLIT0_XPE0 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_SPLIT0", 60307 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_SPLIT1_XPE0 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_SPLIT1", 60308 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE0 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP", 60309 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE1 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP", 60310 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE2 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP", 60311 /* MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP_64_XPE3 */ "MMU_THDM_DB_PORTSP_RED_DROP_STATE_BMP", 60312 /* MMU_THDM_DB_PORTSP_RX_ENABLE0_64 */ "THDM_DB_PORT_RX_ENABLE0", 60313 /* MMU_THDM_DB_PORTSP_RX_ENABLE1_64 */ "THDM_DB_PORT_RX_ENABLE1", 60314 /* MMU_THDM_DB_PORTSP_SHARED_COUNT */ "", 60315 /* MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE0 */ "", 60316 /* MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE1 */ "", 60317 /* MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE2 */ "", 60318 /* MMU_THDM_DB_PORTSP_SHARED_COUNT_XPE3 */ "", 60319 /* MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL */ "", 60320 /* MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE0 */ "", 60321 /* MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE1 */ "", 60322 /* MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE2 */ "", 60323 /* MMU_THDM_DB_PORTSP_THRESHOLD_PROFILE_SEL_XPE3 */ "", 60324 /* MMU_THDM_DB_PORTSP_TOTAL_COUNT */ "", 60325 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP0_64 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP0", 60326 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP1_64 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP1", 60327 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP", 60328 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT0 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT0", 60329 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT1 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT1", 60330 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT0_XPE0 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT0", 60331 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT1_XPE0 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT1", 60332 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE0 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP", 60333 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE1 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP", 60334 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE2 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP", 60335 /* MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP_64_XPE3 */ "MMU_THDM_DB_PORTSP_YELLOW_DROP_STATE_BMP", 60336 /* MMU_THDM_DB_PORT_RX_ENABLE_64 */ "THDM_DB_PORT_RX_ENABLE", 60337 /* MMU_THDM_DB_PORT_RX_ENABLE_64_SPLIT0 */ "THDM_DB_PORT_RX_ENABLE_SPLIT0", 60338 /* MMU_THDM_DB_PORT_RX_ENABLE_64_SPLIT1 */ "THDM_DB_PORT_RX_ENABLE_SPLIT1", 60339 /* MMU_THDM_DB_PORT_TOTAL_COUNT */ "", 60340 /* MMU_THDM_DB_PORT_TOTAL_COUNT_XPE0 */ "", 60341 /* MMU_THDM_DB_PORT_TOTAL_COUNT_XPE1 */ "", 60342 /* MMU_THDM_DB_PORT_TOTAL_COUNT_XPE2 */ "", 60343 /* MMU_THDM_DB_PORT_TOTAL_COUNT_XPE3 */ "", 60344 /* MMU_THDM_DB_QUEUE_E2E_DS */ "", 60345 /* MMU_THDM_DB_QUEUE_E2E_DS_0 */ "", 60346 /* MMU_THDM_DB_QUEUE_E2E_DS_1 */ "", 60347 /* MMU_THDM_DB_QUEUE_E2E_DS_EN */ "", 60348 /* MMU_THDM_DB_QUEUE_E2E_DS_EN_0 */ "", 60349 /* MMU_THDM_DB_QUEUE_E2E_DS_EN_1 */ "", 60350 /* MMU_THDM_DB_QUEUE_E2E_DS_XPE0 */ "", 60351 /* MMU_THDM_DB_QUEUE_E2E_DS_XPE1 */ "", 60352 /* MMU_THDM_DB_QUEUE_E2E_DS_XPE2 */ "", 60353 /* MMU_THDM_DB_QUEUE_E2E_DS_XPE3 */ "", 60354 /* MMU_THDM_DB_QUEUE_E2E_SPID */ "", 60355 /* MMU_THDM_DB_QUEUE_E2E_SPID_0 */ "", 60356 /* MMU_THDM_DB_QUEUE_E2E_SPID_1 */ "", 60357 /* MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE */ "", 60358 /* MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE0 */ "", 60359 /* MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE1 */ "", 60360 /* MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE2 */ "", 60361 /* MMU_THDM_DB_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE3 */ "", 60362 /* MMU_THDM_DB_QUEUE_RESUME_OFFSET_PROFILE_RED */ "", 60363 /* MMU_THDM_DB_QUEUE_RESUME_OFFSET_PROFILE_YELLOW */ "", 60364 /* MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE */ "", 60365 /* MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE0 */ "", 60366 /* MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE1 */ "", 60367 /* MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE2 */ "", 60368 /* MMU_THDM_MCQE_CPUQUEUE_BST_THRESHOLD_PROFILE_XPE3 */ "", 60369 /* MMU_THDM_MCQE_DEVICE_BST_STAT */ "", 60370 /* MMU_THDM_MCQE_DEVICE_BYPASS */ "", 60371 /* MMU_THDM_MCQE_DEVICE_THR_CONFIG */ "", 60372 /* MMU_THDM_MCQE_ENABLE_ECCP_MEM */ "", 60373 /* MMU_THDM_MCQE_EN_COR_ERR_RPT */ "", 60374 /* MMU_THDM_MCQE_MEMORY_TM */ "", 60375 /* MMU_THDM_MCQE_POOL_DROP_STATES */ "", 60376 /* MMU_THDM_MCQE_POOL_MC_BST_STAT */ "", 60377 /* MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD */ "", 60378 /* MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE0 */ "", 60379 /* MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE1 */ "", 60380 /* MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE2 */ "", 60381 /* MMU_THDM_MCQE_POOL_MC_BST_THRESHOLD_XPE3 */ "", 60382 /* MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT */ "", 60383 /* MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE0 */ "", 60384 /* MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE1 */ "", 60385 /* MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE2 */ "", 60386 /* MMU_THDM_MCQE_POOL_RED_RESUME_LIMIT_XPE3 */ "", 60387 /* MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT */ "", 60388 /* MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE0 */ "", 60389 /* MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE1 */ "", 60390 /* MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE2 */ "", 60391 /* MMU_THDM_MCQE_POOL_RED_SHARED_LIMIT_XPE3 */ "", 60392 /* MMU_THDM_MCQE_POOL_RESUME_LIMIT */ "", 60393 /* MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE0 */ "", 60394 /* MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE1 */ "", 60395 /* MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE2 */ "", 60396 /* MMU_THDM_MCQE_POOL_RESUME_LIMIT_XPE3 */ "", 60397 /* MMU_THDM_MCQE_POOL_SHARED_COUNT */ "", 60398 /* MMU_THDM_MCQE_POOL_SHARED_LIMIT */ "", 60399 /* MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE0 */ "", 60400 /* MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE1 */ "", 60401 /* MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE2 */ "", 60402 /* MMU_THDM_MCQE_POOL_SHARED_LIMIT_XPE3 */ "", 60403 /* MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT */ "", 60404 /* MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE0 */ "", 60405 /* MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE1 */ "", 60406 /* MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE2 */ "", 60407 /* MMU_THDM_MCQE_POOL_YELLOW_RESUME_LIMIT_XPE3 */ "", 60408 /* MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT */ "", 60409 /* MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE0 */ "", 60410 /* MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE1 */ "", 60411 /* MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE2 */ "", 60412 /* MMU_THDM_MCQE_POOL_YELLOW_SHARED_LIMIT_XPE3 */ "", 60413 /* MMU_THDM_MCQE_PORTSP_BST_THRESHOLD */ "", 60414 /* MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE0 */ "", 60415 /* MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE1 */ "", 60416 /* MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE2 */ "", 60417 /* MMU_THDM_MCQE_PORTSP_BST_THRESHOLD_XPE3 */ "", 60418 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP0_64 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP0", 60419 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP1_64 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP1", 60420 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP0", 60421 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_SPLIT0 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_SPLIT0", 60422 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_SPLIT1 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_SPLIT1", 60423 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_SPLIT0_XPE0 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_SPLIT0", 60424 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_SPLIT1_XPE0 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_SPLIT1", 60425 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE0 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP0", 60426 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE1 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP0", 60427 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE2 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP0", 60428 /* MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP_64_XPE3 */ "MMU_THDM_MCQE_PORTSP_DROP_STATE_BMP0", 60429 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP0_64 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP0", 60430 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP1_64 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP1", 60431 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP0", 60432 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_SPLIT0 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_SPLIT0", 60433 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_SPLIT1 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_SPLIT1", 60434 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_SPLIT0_XPE0 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_SPLIT0", 60435 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_SPLIT1_XPE0 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_SPLIT1", 60436 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE0 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP0", 60437 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE1 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP0", 60438 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE2 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP0", 60439 /* MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP_64_XPE3 */ "MMU_THDM_MCQE_PORTSP_RED_DROP_STATE_BMP0", 60440 /* MMU_THDM_MCQE_PORTSP_RX_ENABLE0_64 */ "THDM_MCQE_PORT_RX_ENABLE0", 60441 /* MMU_THDM_MCQE_PORTSP_RX_ENABLE1_64 */ "THDM_MCQE_PORT_RX_ENABLE1", 60442 /* MMU_THDM_MCQE_PORTSP_SHARED_COUNT */ "", 60443 /* MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE0 */ "", 60444 /* MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE1 */ "", 60445 /* MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE2 */ "", 60446 /* MMU_THDM_MCQE_PORTSP_SHARED_COUNT_XPE3 */ "", 60447 /* MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL */ "", 60448 /* MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE0 */ "", 60449 /* MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE1 */ "", 60450 /* MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE2 */ "", 60451 /* MMU_THDM_MCQE_PORTSP_THRESHOLD_PROFILE_SEL_XPE3 */ "", 60452 /* MMU_THDM_MCQE_PORTSP_TOTAL_COUNT */ "", 60453 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0", 60454 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE0 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP", 60455 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE1 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP", 60456 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE2 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP", 60457 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP0_64_XPE3 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP", 60458 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP1_64 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP1", 60459 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT0 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT0", 60460 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT1 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT1", 60461 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT0_XPE0 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT0", 60462 /* MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_64_SPLIT1_XPE0 */ "MMU_THDM_MCQE_PORTSP_YELLOW_DROP_STATE_BMP_SPLIT1", 60463 /* MMU_THDM_MCQE_PORT_RX_ENABLE_64 */ "THDM_MCQE_PORT_RX_ENABLE", 60464 /* MMU_THDM_MCQE_PORT_RX_ENABLE_64_SPLIT0 */ "THDM_MCQE_PORT_RX_ENABLE_SPLIT0", 60465 /* MMU_THDM_MCQE_PORT_RX_ENABLE_64_SPLIT1 */ "THDM_MCQE_PORT_RX_ENABLE_SPLIT1", 60466 /* MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE */ "", 60467 /* MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE0 */ "", 60468 /* MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE1 */ "", 60469 /* MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE2 */ "", 60470 /* MMU_THDM_MCQE_QUEUE_MC_BST_THRESHOLD_PROFILE_XPE3 */ "", 60471 /* MMU_THDM_MCQE_QUEUE_RESUME_OFFSET_PROFILE_RED */ "", 60472 /* MMU_THDM_MCQE_QUEUE_RESUME_OFFSET_PROFILE_YELLOW */ "", 60473 /* MMU_THDO_BST_CONFIG */ "", 60474 /* MMU_THDO_BST_CPU_INT_EN */ "", 60475 /* MMU_THDO_BST_CPU_INT_SET */ "", 60476 /* MMU_THDO_BST_CPU_INT_STAT */ "", 60477 /* MMU_THDO_BST_ENABLE_ECCP_MEM */ "", 60478 /* MMU_THDO_BST_EN_COR_ERR_RPT */ "", 60479 /* MMU_THDO_BST_STAT */ "", 60480 /* MMU_THDO_BST_STAT1 */ "", 60481 /* MMU_THDO_BST_TMBUS */ "", 60482 /* MMU_THDO_BYPASS */ "", 60483 /* MMU_THDO_CMIC_RESERVED */ "", 60484 /* MMU_THDO_CONFIG */ "", 60485 /* MMU_THDO_CONFIG_PORT */ "", 60486 /* MMU_THDO_COUNTER_OVERFLOW_ID */ "", 60487 /* MMU_THDO_COUNTER_UNDERFLOW_ID */ "", 60488 /* MMU_THDO_CPU_INT_EN */ "", 60489 /* MMU_THDO_CPU_INT_SET */ "", 60490 /* MMU_THDO_CPU_INT_STAT */ "", 60491 /* MMU_THDO_CPU_QUEUE_DROP_STATES_11_00 */ "", 60492 /* MMU_THDO_CPU_QUEUE_DROP_STATES_23_12 */ "", 60493 /* MMU_THDO_CPU_QUEUE_DROP_STATES_35_24 */ "", 60494 /* MMU_THDO_CPU_QUEUE_DROP_STATES_47_36 */ "", 60495 /* MMU_THDO_ENABLE_ECCP_MEM */ "", 60496 /* MMU_THDO_ENGINE_ENABLES_CFG */ "", 60497 /* MMU_THDO_EN_COR_ERR_RPT */ "", 60498 /* MMU_THDO_INTFO_INTERFACE_CONFIG */ "", 60499 /* MMU_THDO_IPG_SIZE */ "", 60500 /* MMU_THDO_MC_CPU_QUEUE_TOT_BST_THRESHOLD */ "", 60501 /* MMU_THDO_MC_CQE_PRT_SP_BST_THRESHOLD */ "", 60502 /* MMU_THDO_MC_CQE_SP_BST_THRESHOLD */ "", 60503 /* MMU_THDO_MC_POOL_BST_COUNT */ "", 60504 /* MMU_THDO_MC_QUEUE_TOT_BST_THRESHOLD */ "", 60505 /* MMU_THDO_MC_SHARED_CQE_DYNAMIC_THRESH_CAP */ "", 60506 /* MMU_THDO_MC_SHARED_CQE_POOL_CONFIG */ "", 60507 /* MMU_THDO_MC_SHARED_CQE_POOL_DROP_STATES */ "", 60508 /* MMU_THDO_MC_SHARED_CQE_POOL_RED_RESUME_LIMIT */ "", 60509 /* MMU_THDO_MC_SHARED_CQE_POOL_RED_SHARED_LIMIT */ "", 60510 /* MMU_THDO_MC_SHARED_CQE_POOL_RESUME_LIMIT */ "", 60511 /* MMU_THDO_MC_SHARED_CQE_POOL_SHARED_COUNT */ "", 60512 /* MMU_THDO_MC_SHARED_CQE_POOL_SHARED_LIMIT */ "", 60513 /* MMU_THDO_MC_SHARED_CQE_POOL_YELLOW_RESUME_LIMIT */ "", 60514 /* MMU_THDO_MC_SHARED_CQE_POOL_YELLOW_SHARED_LIMIT */ "", 60515 /* MMU_THDO_PRT_SP_SHR_BST_THRESHOLD */ "", 60516 /* MMU_THDO_QUE_TOT_BST_THRESHOLD */ "", 60517 /* MMU_THDO_SHARED_DB_DYNAMIC_THRESH_CAP */ "", 60518 /* MMU_THDO_SHARED_DB_POOL_CONFIG */ "", 60519 /* MMU_THDO_SHARED_DB_POOL_DROP_STATES */ "", 60520 /* MMU_THDO_SHARED_DB_POOL_RED_RESUME_LIMIT */ "", 60521 /* MMU_THDO_SHARED_DB_POOL_RED_SHARED_LIMIT */ "", 60522 /* MMU_THDO_SHARED_DB_POOL_RESUME_LIMIT */ "", 60523 /* MMU_THDO_SHARED_DB_POOL_SHARED_COUNT */ "", 60524 /* MMU_THDO_SHARED_DB_POOL_SHARED_COUNT_DEBUG_LOSSLESS */ "", 60525 /* MMU_THDO_SHARED_DB_POOL_SHARED_COUNT_DEBUG_MC */ "", 60526 /* MMU_THDO_SHARED_DB_POOL_SHARED_LIMIT */ "", 60527 /* MMU_THDO_SHARED_DB_POOL_YELLOW_RESUME_LIMIT */ "", 60528 /* MMU_THDO_SHARED_DB_POOL_YELLOW_SHARED_LIMIT */ "", 60529 /* MMU_THDO_SP_SHR_BST_THRESHOLD */ "", 60530 /* MMU_THDO_TMBUS */ "", 60531 /* MMU_THDO_UC_POOL_BST_COUNT */ "", 60532 /* MMU_THDO_VOQ_FAIRNESS_CFG */ "", 60533 /* MMU_THDR_DB_BST_STAT */ "", 60534 /* MMU_THDR_DB_BST_STAT_PRIQ */ "", 60535 /* MMU_THDR_DB_BST_STAT_SP */ "", 60536 /* MMU_THDR_DB_BST_THRESHOLD_PRIQ */ "", 60537 /* MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE0 */ "", 60538 /* MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE1 */ "", 60539 /* MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE2 */ "", 60540 /* MMU_THDR_DB_BST_THRESHOLD_PRIQ_XPE3 */ "", 60541 /* MMU_THDR_DB_BST_THRESHOLD_SP */ "", 60542 /* MMU_THDR_DB_BST_THRESHOLD_SP_XPE0 */ "", 60543 /* MMU_THDR_DB_BST_THRESHOLD_SP_XPE1 */ "", 60544 /* MMU_THDR_DB_BST_THRESHOLD_SP_XPE2 */ "", 60545 /* MMU_THDR_DB_BST_THRESHOLD_SP_XPE3 */ "", 60546 /* MMU_THDR_DB_BYPASS */ "", 60547 /* MMU_THDR_DB_CONFIG */ "", 60548 /* MMU_THDR_DB_CONFIG1_PRIQ */ "", 60549 /* MMU_THDR_DB_CONFIG_PRIQ */ "", 60550 /* MMU_THDR_DB_CONFIG_SP */ "", 60551 /* MMU_THDR_DB_CONFIG_SP_XPE0 */ "", 60552 /* MMU_THDR_DB_CONFIG_SP_XPE1 */ "", 60553 /* MMU_THDR_DB_CONFIG_SP_XPE2 */ "", 60554 /* MMU_THDR_DB_CONFIG_SP_XPE3 */ "", 60555 /* MMU_THDR_DB_LIMIT_COLOR_PRIQ */ "", 60556 /* MMU_THDR_DB_LIMIT_MIN_PRIQ */ "", 60557 /* MMU_THDR_DB_MIN_COUNT_PRIQ */ "", 60558 /* MMU_THDR_DB_RESET_OFFSET_COLOR_PRIQ */ "", 60559 /* MMU_THDR_DB_RESUME_COLOR_LIMIT_CALCULATED_PRIQ */ "", 60560 /* MMU_THDR_DB_RESUME_COLOR_LIMIT_SP */ "", 60561 /* MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE0 */ "", 60562 /* MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE1 */ "", 60563 /* MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE2 */ "", 60564 /* MMU_THDR_DB_RESUME_COLOR_LIMIT_SP_XPE3 */ "", 60565 /* MMU_THDR_DB_SHARED_COUNT_PRIQ */ "", 60566 /* MMU_THDR_DB_SHARED_COUNT_SP */ "", 60567 /* MMU_THDR_DB_SP_SHARED_LIMIT */ "", 60568 /* MMU_THDR_DB_SP_SHARED_LIMIT_XPE0 */ "", 60569 /* MMU_THDR_DB_SP_SHARED_LIMIT_XPE1 */ "", 60570 /* MMU_THDR_DB_SP_SHARED_LIMIT_XPE2 */ "", 60571 /* MMU_THDR_DB_SP_SHARED_LIMIT_XPE3 */ "", 60572 /* MMU_THDR_DB_STATUS_PRIQ */ "", 60573 /* MMU_THDR_DB_STATUS_SP */ "", 60574 /* MMU_THDR_QE_BST_CONFIG */ "", 60575 /* MMU_THDR_QE_BST_COUNT_PRIQ */ "", 60576 /* MMU_THDR_QE_BST_COUNT_SP */ "", 60577 /* MMU_THDR_QE_BST_STAT */ "", 60578 /* MMU_THDR_QE_BST_STAT_PRIQ */ "", 60579 /* MMU_THDR_QE_BST_STAT_SP */ "", 60580 /* MMU_THDR_QE_BST_THRESHOLD_PRIQ */ "", 60581 /* MMU_THDR_QE_BST_THRESHOLD_SP */ "", 60582 /* MMU_THDR_QE_BYPASS */ "", 60583 /* MMU_THDR_QE_CONFIG */ "", 60584 /* MMU_THDR_QE_CONFIG1_PRIQ */ "", 60585 /* MMU_THDR_QE_CONFIG_PRIQ */ "", 60586 /* MMU_THDR_QE_CONFIG_SP */ "", 60587 /* MMU_THDR_QE_COUNTER_OVERFLOW */ "", 60588 /* MMU_THDR_QE_COUNTER_UNDERFLOW */ "", 60589 /* MMU_THDR_QE_CPU_INT_EN */ "", 60590 /* MMU_THDR_QE_CPU_INT_SET */ "", 60591 /* MMU_THDR_QE_CPU_INT_STAT */ "", 60592 /* MMU_THDR_QE_DEBUG */ "", 60593 /* MMU_THDR_QE_DROP_COUNT_BYTE_PRIQ */ "", 60594 /* MMU_THDR_QE_DROP_COUNT_PKT_PRIQ */ "", 60595 /* MMU_THDR_QE_DROP_COUNT_RED_PKT_PRIQ */ "", 60596 /* MMU_THDR_QE_DROP_COUNT_YELLOW_PKT_PRIQ */ "", 60597 /* MMU_THDR_QE_LIMIT_COLOR_PRIQ */ "", 60598 /* MMU_THDR_QE_LIMIT_MIN_PRIQ */ "", 60599 /* MMU_THDR_QE_MIN_COUNT_PRIQ */ "", 60600 /* MMU_THDR_QE_RESET_OFFSET_COLOR_PRIQ */ "", 60601 /* MMU_THDR_QE_RESUME_COLOR_LIMIT_CALCULATED_PRIQ */ "", 60602 /* MMU_THDR_QE_RESUME_COLOR_LIMIT_PRIQ */ "", 60603 /* MMU_THDR_QE_RESUME_COLOR_LIMIT_SP */ "", 60604 /* MMU_THDR_QE_RESUME_LIMIT_PRIQ */ "", 60605 /* MMU_THDR_QE_RSVD_REG */ "", 60606 /* MMU_THDR_QE_SHARED_COLOR_LIMIT_PRIQ */ "", 60607 /* MMU_THDR_QE_SHARED_COLOR_LIMIT_SP */ "", 60608 /* MMU_THDR_QE_SHARED_COUNT_PRIQ */ "", 60609 /* MMU_THDR_QE_SHARED_COUNT_SP */ "", 60610 /* MMU_THDR_QE_STATUS */ "", 60611 /* MMU_THDR_QE_STATUS_PRIQ */ "", 60612 /* MMU_THDR_QE_STATUS_SP */ "", 60613 /* MMU_THDR_QE_TOTAL_COUNT_PRIQ */ "", 60614 /* MMU_THDU_ENABLE_ECCP_MEM */ "", 60615 /* MMU_THDU_EN_COR_ERR_RPT */ "", 60616 /* MMU_TOQ_BP_DEBUG0 */ "", 60617 /* MMU_TOQ_BP_DEBUG1 */ "", 60618 /* MMU_TOQ_CMIC_RESERVED */ "", 60619 /* MMU_TOQ_CONFIG */ "", 60620 /* MMU_TOQ_CPU_INT_EN */ "", 60621 /* MMU_TOQ_CPU_INT_SET */ "", 60622 /* MMU_TOQ_CPU_INT_STAT */ "", 60623 /* MMU_TOQ_DEBUG */ "", 60624 /* MMU_TOQ_ECC_1B_COUNTER */ "", 60625 /* MMU_TOQ_ECC_2B_COUNTER */ "", 60626 /* MMU_TOQ_ENABLE_ECCP_MEM */ "", 60627 /* MMU_TOQ_EN_COR_ERR_RPT */ "", 60628 /* MMU_TOQ_EOPE_ECC_STATUS */ "", 60629 /* MMU_TOQ_PORT_STATE_ECC_STATUS */ "", 60630 /* MMU_TOQ_QPACK_MODE_ECC_STATUS */ "", 60631 /* MMU_TOQ_REPL_PORT_AGG_MAP */ "", 60632 /* MMU_TOQ_STATE_ECC_STATUS */ "", 60633 /* MMU_TOQ_STATUS */ "", 60634 /* MMU_TOQ_TCACHE_DEBUG0 */ "", 60635 /* MMU_TOQ_TCACHE_DEBUG1 */ "", 60636 /* MMU_TOQ_TCACHE_DEBUG2 */ "", 60637 /* MMU_TOQ_TCACHE_DEBUG3 */ "", 60638 /* MMU_TOQ_TCACHE_DEBUG4 */ "", 60639 /* MMU_TOQ_TCACHE_DEBUG5 */ "", 60640 /* MMU_TOQ_TCACHE_DEBUG6 */ "", 60641 /* MMU_TOQ_TCACHE_DEBUG7 */ "", 60642 /* MMU_TOQ_TMBUS */ "", 60643 /* MMU_TOQ_TRACE_DEQ_CAPT_0 */ "", 60644 /* MMU_TOQ_TRACE_DEQ_CAPT_1 */ "", 60645 /* MMU_TOQ_TRACE_DEQ_CAPT_2 */ "", 60646 /* MMU_TOQ_TRACE_DEQ_CONTROL */ "", 60647 /* MMU_TOQ_TRACE_DEQ_COUNTER */ "", 60648 /* MMU_TOQ_TRACE_DEQ_MASK_FIELD */ "", 60649 /* MMU_TOQ_TRACE_DEQ_VALUE_FIELD */ "", 60650 /* MMU_TOQ_TRACE_ENQ_CAPT_0 */ "", 60651 /* MMU_TOQ_TRACE_ENQ_CAPT_1 */ "", 60652 /* MMU_TOQ_TRACE_ENQ_CONTROL */ "", 60653 /* MMU_TOQ_TRACE_ENQ_COUNTER */ "", 60654 /* MMU_TOQ_TRACE_ENQ_MASK_FIELD */ "", 60655 /* MMU_TOQ_TRACE_ENQ_VALUE_FIELD */ "", 60656 /* MMU_TO_LOGIC_PORT_MAPPING */ "", 60657 /* MMU_TO_PHY_PORT_MAPPING */ "", 60658 /* MMU_TO_XLP0_E2ECC_STATUS */ "", 60659 /* MMU_TO_XLP1_E2ECC_STATUS */ "", 60660 /* MMU_TO_XLP_BKP_STATUS */ "", 60661 /* MMU_TO_XPORT_BKP */ "", 60662 /* MMU_TSN_DELAY */ "", 60663 /* MMU_WRED_CFG_ECC_STATUS */ "", 60664 /* MMU_WRED_CMIC_RESERVED */ "", 60665 /* MMU_WRED_CONFIG */ "", 60666 /* MMU_WRED_CONFIG_READY */ "", 60667 /* MMU_WRED_CONG_NOTIFICATION_RESOLUTION_TABLE */ "", 60668 /* MMU_WRED_ENABLE_ECCP_MEM */ "", 60669 /* MMU_WRED_EN_COR_ERR_RPT */ "", 60670 /* MMU_WRED_MEM_INIT_STATUS */ "", 60671 /* MMU_WRED_POOL_CONFIG */ "", 60672 /* MMU_WRED_POOL_INST_CONG_LIMIT_0 */ "", 60673 /* MMU_WRED_POOL_INST_CONG_LIMIT_1 */ "", 60674 /* MMU_WRED_POOL_INST_CONG_LIMIT_2 */ "", 60675 /* MMU_WRED_POOL_INST_CONG_LIMIT_3 */ "", 60676 /* MMU_WRED_PORT_CFG_ECC_STATUS */ "", 60677 /* MMU_WRED_PORT_THD_0_ECC_STATUS */ "", 60678 /* MMU_WRED_PORT_THD_1_ECC_STATUS */ "", 60679 /* MMU_WRED_REFRESH_CONTROL */ "", 60680 /* MMU_WRED_THD_0_ECC_STATUS */ "", 60681 /* MMU_WRED_THD_1_ECC_STATUS */ "", 60682 /* MMU_WRED_TIME_DOMAIN */ "", 60683 /* MMU_WRED_TMBUS */ "", 60684 /* MMU_XCFG_ECC_SINGLE_BIT_ERRORS */ "", 60685 /* MMU_XCFG_MEM_FAIL_INT_CTR */ "", 60686 /* MMU_XCFG_MEM_SER_FIFO_STS */ "", 60687 /* MMU_XCFG_PARITY_EN */ "", 60688 /* MMU_XCFG_XPE_CPU_INT_CLEAR */ "MMU_XCFG_XPE_CPU_INT_CLEAR", 60689 /* MMU_XCFG_XPE_CPU_INT_EN */ "MMU_XCFG_XPE_CPU_INT_EN", 60690 /* MMU_XCFG_XPE_CPU_INT_STAT */ "MMU_XCFG_XPE_CPU_INT_STAT", 60691 /* MODPORT_MAP_EM_PARITY_CONTROL */ "", 60692 /* MODPORT_MAP_EM_PARITY_STATUS */ "", 60693 /* MODPORT_MAP_IM_PARITY_CONTROL */ "", 60694 /* MODPORT_MAP_IM_PARITY_STATUS */ "", 60695 /* MODPORT_MAP_M0_PARITY_STATUS_INTR */ "", 60696 /* MODPORT_MAP_M0_PARITY_STATUS_NACK */ "", 60697 /* MODPORT_MAP_M1_PARITY_STATUS_INTR */ "", 60698 /* MODPORT_MAP_M1_PARITY_STATUS_NACK */ "", 60699 /* MODPORT_MAP_M2_PARITY_STATUS_INTR */ "", 60700 /* MODPORT_MAP_M2_PARITY_STATUS_NACK */ "", 60701 /* MODPORT_MAP_M3_PARITY_STATUS_INTR */ "", 60702 /* MODPORT_MAP_M3_PARITY_STATUS_NACK */ "", 60703 /* MODPORT_MAP_MIRROR_1_PARITY_CONTROL */ "", 60704 /* MODPORT_MAP_MIRROR_1_PARITY_STATUS_INTR */ "", 60705 /* MODPORT_MAP_MIRROR_1_PARITY_STATUS_NACK */ "", 60706 /* MODPORT_MAP_MIRROR_ECC_CONTROL */ "", 60707 /* MODPORT_MAP_MIRROR_PARITY_CONTROL */ "", 60708 /* MODPORT_MAP_MIRROR_PARITY_STATUS_INTR */ "", 60709 /* MODPORT_MAP_MIRROR_PARITY_STATUS_NACK */ "", 60710 /* MODPORT_MAP_SEL */ "", 60711 /* MODPORT_MAP_SW_ECC_CONTROL */ "", 60712 /* MODPORT_MAP_SW_PARITY_CONTROL */ "", 60713 /* MODPORT_MAP_SW_PARITY_STATUS */ "", 60714 /* MODPORT_MAP_SW_PARITY_STATUS_INTR */ "", 60715 /* MODPORT_MAP_SW_PARITY_STATUS_NACK */ "", 60716 /* MOD_FIFO_CNT */ "", 60717 /* MOD_MAP_PARITY_CONTROL */ "", 60718 /* MOD_MAP_PARITY_STATUS_INTR */ "", 60719 /* MOD_MAP_PARITY_STATUS_NACK */ "", 60720 /* MORDRPC_CHID_0 */ "", 60721 /* MORDRPC_CHID_1 */ "", 60722 /* MORDRPC_CHID_2 */ "", 60723 /* MORDRPC_CHID_3 */ "", 60724 /* MORDRPC_CHID_4 */ "", 60725 /* MORDRPC_CHID_5 */ "", 60726 /* MORDRPC_CHID_6 */ "", 60727 /* MORDRPC_CHID_7 */ "", 60728 /* MORDRPC_CHID_8 */ "", 60729 /* MORDRPC_CHID_9 */ "", 60730 /* MORDRPC_CHID_10 */ "", 60731 /* MORDRPC_CHID_11 */ "", 60732 /* MORDRPC_CHID_12 */ "", 60733 /* MORDRPC_CHID_13 */ "", 60734 /* MORDRPC_CHID_14 */ "", 60735 /* MORDRPC_CHID_15 */ "", 60736 /* MORDRPC_CHID_16 */ "", 60737 /* MORDRPC_CHID_17 */ "", 60738 /* MORDRPC_CHID_18 */ "", 60739 /* MORDRPC_CHID_19 */ "", 60740 /* MORDRPC_CHID_20 */ "", 60741 /* MORDRPC_CHID_21 */ "", 60742 /* MORDRPC_CHID_22 */ "", 60743 /* MORDRPC_CHID_23 */ "", 60744 /* MORDRPC_CHID_24 */ "", 60745 /* MORDRPC_CHID_25 */ "", 60746 /* MORDRPC_CHID_26 */ "", 60747 /* MORDRPC_CHID_27 */ "", 60748 /* MORDRPC_CHID_28 */ "", 60749 /* MORDRPC_CHID_29 */ "", 60750 /* MORDRPC_CHID_30 */ "", 60751 /* MORDRPC_CHID_31 */ "", 60752 /* MORDRPC_CHID_32 */ "", 60753 /* MORDRPC_CHID_33 */ "", 60754 /* MORDRPC_CHID_34 */ "", 60755 /* MORDRPC_CHID_35 */ "", 60756 /* MORDRPC_CHID_36 */ "", 60757 /* MORDRPC_CHID_37 */ "", 60758 /* MORDRPC_CHID_38 */ "", 60759 /* MORDRPC_CHID_39 */ "", 60760 /* MORDRPC_CHID_40 */ "", 60761 /* MORDRPC_CHID_41 */ "", 60762 /* MORDRPC_CHID_42 */ "", 60763 /* MORDRPC_CHID_43 */ "", 60764 /* MORDRPC_CHID_44 */ "", 60765 /* MORDRPC_CHID_45 */ "", 60766 /* MORDRPC_CHID_46 */ "", 60767 /* MORDRPC_CHID_47 */ "", 60768 /* MORDRPC_CHID_48 */ "", 60769 /* MORDRPC_CHID_49 */ "", 60770 /* MORDRPC_CHID_50 */ "", 60771 /* MORDRPC_CHID_51 */ "", 60772 /* MORDRPC_CHID_52 */ "", 60773 /* MORDRPC_CHID_53 */ "", 60774 /* MORDRPC_CHID_54 */ "", 60775 /* MORDRPC_CHID_55 */ "", 60776 /* MORDRPC_CHID_56 */ "", 60777 /* MORDRPC_CHID_57 */ "", 60778 /* MORDRPC_CHID_58 */ "", 60779 /* MORDRPC_CHID_59 */ "", 60780 /* MORDRPC_CHID_60 */ "", 60781 /* MORDRPC_CHID_61 */ "", 60782 /* MORDRPC_CHID_62 */ "", 60783 /* MORDRPC_CHID_63 */ "", 60784 /* MOTP_CHECKSUM_STATUS */ "", 60785 /* MPB_EGR_EDIT_CTRL_ID_FIELD_SEL */ "", 60786 /* MPLS_CAM_DBGCTRL_0 */ "MPLS_CAM_CONTROL_0", 60787 /* MPLS_CAM_DBGCTRL_0_PIPE0 */ "MPLS_CAM_CONTROL_0_PIPE0", 60788 /* MPLS_CAM_DBGCTRL_0_PIPE1 */ "MPLS_CAM_CONTROL_0_PIPE1", 60789 /* MPLS_CAM_DBGCTRL_0_PIPE2 */ "MPLS_CAM_CONTROL_0_PIPE2", 60790 /* MPLS_CAM_DBGCTRL_0_PIPE3 */ "MPLS_CAM_CONTROL_0_PIPE3", 60791 /* MPLS_CONTROL_PKT_PARSER2_CONTEXT */ "", 60792 /* MPLS_DEFAULT_NETWORK_L3_IIF */ "", 60793 /* MPLS_DEFAULT_NETWORK_SVP */ "", 60794 /* MPLS_ENABLE */ "", 60795 /* MPLS_ENTROPY_LABEL_CONFIG_64 */ "", 60796 /* MPLS_ENTRY_DBGCTRL */ "MPLS_ENTRY_CONTROL", 60797 /* MPLS_ENTRY_DBGCTRL_0 */ "MPLS_ENTRY_CONTROL_0", 60798 /* MPLS_ENTRY_DBGCTRL_1 */ "MPLS_ENTRY_CONTROL_1", 60799 /* MPLS_ENTRY_DBGCTRL_2 */ "MPLS_ENTRY_CONTROL_2", 60800 /* MPLS_ENTRY_DBGCTRL_3 */ "MPLS_ENTRY_CONTROL_3", 60801 /* MPLS_ENTRY_DBGCTRL_4 */ "MPLS_ENTRY_CONTROL_4", 60802 /* MPLS_ENTRY_DBGCTRL_5 */ "MPLS_ENTRY_CONTROL_5", 60803 /* MPLS_ENTRY_DBGCTRL_6 */ "MPLS_ENTRY_CONTROL_6", 60804 /* MPLS_ENTRY_DBGCTRL_7 */ "MPLS_ENTRY_CONTROL_7", 60805 /* MPLS_ENTRY_DBGCTRL_0_PIPE0 */ "MPLS_ENTRY_CONTROL_0_PIPE0", 60806 /* MPLS_ENTRY_DBGCTRL_0_PIPE1 */ "MPLS_ENTRY_CONTROL_0_PIPE1", 60807 /* MPLS_ENTRY_DBGCTRL_0_PIPE2 */ "MPLS_ENTRY_CONTROL_0_PIPE2", 60808 /* MPLS_ENTRY_DBGCTRL_0_PIPE3 */ "MPLS_ENTRY_CONTROL_0_PIPE3", 60809 /* MPLS_ENTRY_ECC_CONTROL */ "", 60810 /* MPLS_ENTRY_HASH_CONTROL */ "", 60811 /* MPLS_ENTRY_LP_DATA_DBGCTRL_0 */ "MPLS_ENTRY_LP_DATA_CONTROL_0", 60812 /* MPLS_ENTRY_LP_DATA_DBGCTRL_0_PIPE0 */ "MPLS_ENTRY_LP_DATA_CONTROL_0_PIPE0", 60813 /* MPLS_ENTRY_LP_DATA_DBGCTRL_0_PIPE1 */ "MPLS_ENTRY_LP_DATA_CONTROL_0_PIPE1", 60814 /* MPLS_ENTRY_LP_DATA_DBGCTRL_0_PIPE2 */ "MPLS_ENTRY_LP_DATA_CONTROL_0_PIPE2", 60815 /* MPLS_ENTRY_LP_DATA_DBGCTRL_0_PIPE3 */ "MPLS_ENTRY_LP_DATA_CONTROL_0_PIPE3", 60816 /* MPLS_ENTRY_PARITY_CONTROL */ "", 60817 /* MPLS_ENTRY_PARITY_STATUS */ "", 60818 /* MPLS_ENTRY_PARITY_STATUS_INTR_0 */ "", 60819 /* MPLS_ENTRY_PARITY_STATUS_INTR_1 */ "", 60820 /* MPLS_ENTRY_PARITY_STATUS_NACK_0 */ "", 60821 /* MPLS_ENTRY_PARITY_STATUS_NACK_1 */ "", 60822 /* MPLS_ETHERTYPE */ "", 60823 /* MPLS_EVPN_CONTROL */ "", 60824 /* MPLS_EXTENDED_LABEL_LOOKUP_ENABLE */ "", 60825 /* MPLS_IP_NIBBLE_PEEKING_CTRL */ "", 60826 /* MPLS_MEMORY_DBGCTRL */ "MPLS_MEMORY_CONTROL", 60827 /* MPLS_MEMORY_DBGCTRL_0 */ "MPLS_MEMORY_CONTROL_0", 60828 /* MPLS_MEMORY_DBGCTRL_1 */ "MPLS_MEMORY_CONTROL_1", 60829 /* MPLS_MEMORY_DBGCTRL_2 */ "MPLS_MEMORY_CONTROL_2", 60830 /* MPLS_MEMORY_DBGCTRL_3 */ "MPLS_MEMORY_CONTROL_3", 60831 /* MPLS_MEMORY_DBGCTRL_0_64 */ "MPLS_MEMORY_CONTROL_0", 60832 /* MPLS_MEMORY_DBGCTRL_0_64_PIPE0 */ "MPLS_MEMORY_CONTROL_0_PIPE0", 60833 /* MPLS_MEMORY_DBGCTRL_0_64_PIPE1 */ "MPLS_MEMORY_CONTROL_0_PIPE1", 60834 /* MPLS_MEMORY_DBGCTRL_0_64_PIPE2 */ "MPLS_MEMORY_CONTROL_0_PIPE2", 60835 /* MPLS_MEMORY_DBGCTRL_0_64_PIPE3 */ "MPLS_MEMORY_CONTROL_0_PIPE3", 60836 /* MPLS_MEMORY_DBGCTRL_1_64 */ "MPLS_MEMORY_CONTROL_1", 60837 /* MPLS_MEMORY_DBGCTRL_1_64_PIPE0 */ "MPLS_MEMORY_CONTROL_1_PIPE0", 60838 /* MPLS_MEMORY_DBGCTRL_1_64_PIPE1 */ "MPLS_MEMORY_CONTROL_1_PIPE1", 60839 /* MPLS_MEMORY_DBGCTRL_1_64_PIPE2 */ "MPLS_MEMORY_CONTROL_1_PIPE2", 60840 /* MPLS_MEMORY_DBGCTRL_1_64_PIPE3 */ "MPLS_MEMORY_CONTROL_1_PIPE3", 60841 /* MPLS_MEMORY_DBGCTRL_2_PIPE0 */ "MPLS_MEMORY_CONTROL_2_PIPE0", 60842 /* MPLS_MEMORY_DBGCTRL_2_PIPE1 */ "MPLS_MEMORY_CONTROL_2_PIPE1", 60843 /* MPLS_MEMORY_DBGCTRL_2_PIPE2 */ "MPLS_MEMORY_CONTROL_2_PIPE2", 60844 /* MPLS_MEMORY_DBGCTRL_2_PIPE3 */ "MPLS_MEMORY_CONTROL_2_PIPE3", 60845 /* MPLS_MEMORY_DBGCTRL_3_PIPE0 */ "MPLS_MEMORY_CONTROL_3_PIPE0", 60846 /* MPLS_MEMORY_DBGCTRL_3_PIPE1 */ "MPLS_MEMORY_CONTROL_3_PIPE1", 60847 /* MPLS_MEMORY_DBGCTRL_3_PIPE2 */ "MPLS_MEMORY_CONTROL_3_PIPE2", 60848 /* MPLS_MEMORY_DBGCTRL_3_PIPE3 */ "MPLS_MEMORY_CONTROL_3_PIPE3", 60849 /* MPLS_RAM_DBGCTRL_0 */ "MPLS_RAM_CONTROL_0", 60850 /* MPLS_RAM_DBGCTRL_1 */ "MPLS_RAM_CONTROL_1", 60851 /* MPLS_RAM_DBGCTRL_2 */ "MPLS_RAM_CONTROL_2", 60852 /* MPLS_SER_CONTROL */ "", 60853 /* MPLS_STATION_CAM_BIST_CONFIG */ "", 60854 /* MPLS_STATION_CAM_BIST_CONTROL */ "", 60855 /* MPLS_STATION_CAM_BIST_DBG_DATA */ "", 60856 /* MPLS_STATION_CAM_BIST_STATUS */ "", 60857 /* MPLS_STATION_CAM_DBGCTRL */ "MPLS_STATION_CAM_CONTROL", 60858 /* MPLS_UNKNOWN_CONTROL_PACKET_COUNTER_CONTROL */ "", 60859 /* MP_GROUP_ECC_CONTROL */ "", 60860 /* MP_GROUP_HASH_CONTROL */ "", 60861 /* MRPS_AUTO_DOC_NAME_17 */ "", 60862 /* MRPS_AUTO_DOC_NAME_22 */ "", 60863 /* MRPS_AUTO_DOC_NAME_25 */ "", 60864 /* MRPS_AUTO_DOC_NAME_27 */ "", 60865 /* MRPS_AUTO_DOC_NAME_29 */ "", 60866 /* MRPS_AUTO_DOC_NAME_31 */ "", 60867 /* MRPS_AUTO_DOC_NAME_33 */ "", 60868 /* MRPS_AUTO_DOC_NAME_36 */ "", 60869 /* MRPS_ECC_1B_ERR_CNT */ "", 60870 /* MRPS_ECC_2B_ERR_CNT */ "", 60871 /* MRPS_ECC_ERR_1B_INITIATE */ "", 60872 /* MRPS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 60873 /* MRPS_ECC_ERR_2B_INITIATE */ "", 60874 /* MRPS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 60875 /* MRPS_ECC_INTERRUPT_REGISTER */ "", 60876 /* MRPS_ECC_INTERRUPT_REGISTER_MASK */ "", 60877 /* MRPS_ECC_INTERRUPT_REGISTER_TEST */ "", 60878 /* MRPS_EGR_ENG_ADDR_MAP */ "", 60879 /* MRPS_EGR_ENG_ADDR_RANGE */ "", 60880 /* MRPS_EGR_ENG_FILTER */ "", 60881 /* MRPS_EGR_ENG_GLOBAL_SETTINGS */ "", 60882 /* MRPS_EGR_ENG_IN_COLOR_MAP */ "", 60883 /* MRPS_EGR_ENG_OOP_FIFO_DATA */ "", 60884 /* MRPS_EGR_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER */ "", 60885 /* MRPS_EGR_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_MASK */ "", 60886 /* MRPS_EGR_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_TEST */ "", 60887 /* MRPS_EGR_ENG_OOP_FIFO_SETTINGS */ "", 60888 /* MRPS_EGR_ENG_OOP_FIFO_WR_CTR */ "", 60889 /* MRPS_EGR_ENG_RND_SETTINGS */ "", 60890 /* MRPS_EGR_ENG_STAT_CTR */ "", 60891 /* MRPS_EGR_ENG_STAT_SETTINGS */ "", 60892 /* MRPS_EGR_ENG_WRAP_INTERRUPT_REGISTER */ "", 60893 /* MRPS_EGR_ENG_WRAP_INTERRUPT_REGISTER_MASK */ "", 60894 /* MRPS_EGR_ENG_WRAP_INTERRUPT_REGISTER_TEST */ "", 60895 /* MRPS_EGR_GENERAL_SETTINGS */ "", 60896 /* MRPS_EGR_IN_COLOR_CTR */ "", 60897 /* MRPS_EGR_LAST_RX_CMD */ "", 60898 /* MRPS_EGR_OUT_COLOR_CTR */ "", 60899 /* MRPS_EGR_WRAP_ERR_INDEX */ "", 60900 /* MRPS_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 60901 /* MRPS_ERROR_INITIATION_DATA */ "", 60902 /* MRPS_GLBL_CFG */ "", 60903 /* MRPS_GLOBAL_GENERAL_CFG_2 */ "", 60904 /* MRPS_GLOBAL_MEM_OPTIONS */ "", 60905 /* MRPS_GTIMER_CONFIGURATION */ "", 60906 /* MRPS_GTIMER_CYCLE */ "", 60907 /* MRPS_GTIMER_TRIGGER */ "", 60908 /* MRPS_IDR_INTERFACE_DEBUG_COUNTERS */ "", 60909 /* MRPS_INCOMING_COLOR_MAP */ "", 60910 /* MRPS_INDIRECT_COMMAND */ "", 60911 /* MRPS_INDIRECT_COMMAND_ADDRESS */ "", 60912 /* MRPS_INDIRECT_COMMAND_DATA_INCREMENT */ "", 60913 /* MRPS_INDIRECT_COMMAND_RD_DATA */ "", 60914 /* MRPS_INDIRECT_COMMAND_WIDE_MEM */ "", 60915 /* MRPS_INDIRECT_COMMAND_WR_DATA */ "", 60916 /* MRPS_INDIRECT_FORCE_BUBBLE */ "", 60917 /* MRPS_INGRESS_IN_INTERFACE_DEBUG_COUNTERS */ "", 60918 /* MRPS_INGRESS_OUT_INTERFACE_DEBUG_COUNTERS */ "", 60919 /* MRPS_ING_ENG_ADDR_MAP */ "", 60920 /* MRPS_ING_ENG_ADDR_RANGE */ "", 60921 /* MRPS_ING_ENG_FILTER */ "", 60922 /* MRPS_ING_ENG_GLBL_PTR_EXP_SETTINGS */ "", 60923 /* MRPS_ING_ENG_GLOBAL_SETTINGS */ "", 60924 /* MRPS_ING_ENG_IN_COLOR_MAP */ "", 60925 /* MRPS_ING_ENG_OOP_FIFO_DATA */ "", 60926 /* MRPS_ING_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER */ "", 60927 /* MRPS_ING_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_MASK */ "", 60928 /* MRPS_ING_ENG_OOP_FIFO_NOT_EMPTY_INTERRUPT_REGISTER_TEST */ "", 60929 /* MRPS_ING_ENG_OOP_FIFO_SETTINGS */ "", 60930 /* MRPS_ING_ENG_OOP_FIFO_WR_CTR */ "", 60931 /* MRPS_ING_ENG_RND_SETTINGS */ "", 60932 /* MRPS_ING_ENG_STAT_CTR */ "", 60933 /* MRPS_ING_ENG_STAT_SETTINGS */ "", 60934 /* MRPS_ING_ENG_WRAP_INTERRUPT_REGISTER */ "", 60935 /* MRPS_ING_ENG_WRAP_INTERRUPT_REGISTER_MASK */ "", 60936 /* MRPS_ING_ENG_WRAP_INTERRUPT_REGISTER_TEST */ "", 60937 /* MRPS_ING_GENERAL_SETTINGS */ "", 60938 /* MRPS_ING_GLBL_ENG_FILTER */ "", 60939 /* MRPS_ING_GLBL_ENG_GLOBAL_SETTINGS */ "", 60940 /* MRPS_ING_GLBL_ENG_IN_BLACK_COLOR_CTR */ "", 60941 /* MRPS_ING_GLBL_ENG_IN_COLOR_MAP */ "", 60942 /* MRPS_ING_GLBL_ENG_IN_RED_COLOR_CTR */ "", 60943 /* MRPS_ING_GLBL_ENG_OOP_FIFO_DATA */ "", 60944 /* MRPS_ING_GLBL_ENG_OOP_FIFO_SETTINGS */ "", 60945 /* MRPS_ING_GLBL_ENG_RJCT_CTR */ "", 60946 /* MRPS_ING_GLBL_ENG_RND_SETTINGS */ "", 60947 /* MRPS_ING_GLBL_PTR_MAP */ "", 60948 /* MRPS_ING_IN_COLOR_CTR */ "", 60949 /* MRPS_ING_LAST_RX_CMD */ "", 60950 /* MRPS_ING_OUT_COLOR_CTR */ "", 60951 /* MRPS_ING_WRAP_ERR_INDEX */ "", 60952 /* MRPS_INIT_SEQ_ON */ "", 60953 /* MRPS_INIT_SEQ_ON_STATUS */ "", 60954 /* MRPS_INTERRUPT_MASK_REGISTER */ "", 60955 /* MRPS_INTERRUPT_REGISTER */ "", 60956 /* MRPS_INTERRUPT_REGISTER_TEST */ "", 60957 /* MRPS_MCDA_CBL_STAT_CTR */ "", 60958 /* MRPS_MCDA_CFG */ "", 60959 /* MRPS_MCDA_EBL_STAT_CTR */ "", 60960 /* MRPS_MCDA_LAST_CMD_INDEX */ "", 60961 /* MRPS_MCDA_REFRESH_CFG */ "", 60962 /* MRPS_MCDA_STAT_CFG */ "", 60963 /* MRPS_MCDA_WRAP_INDEX */ "", 60964 /* MRPS_MCDB_CBL_STAT_CTR */ "", 60965 /* MRPS_MCDB_CFG */ "", 60966 /* MRPS_MCDB_EBL_STAT_CTR */ "", 60967 /* MRPS_MCDB_LAST_CMD_INDEX */ "", 60968 /* MRPS_MCDB_REFRESH_CFG */ "", 60969 /* MRPS_MCDB_STAT_CFG */ "", 60970 /* MRPS_MCDB_WRAP_INDEX */ "", 60971 /* MRPS_REG_0041 */ "", 60972 /* MRPS_REG_00A4 */ "", 60973 /* MRPS_REG_00A6 */ "", 60974 /* MRPS_REG_00C2 */ "", 60975 /* MRPS_REG_02BF */ "", 60976 /* MRPS_REG_02C0 */ "", 60977 /* MRPS_REG_02C1 */ "", 60978 /* MRPS_REG_02C3 */ "", 60979 /* MRPS_REG_02C5 */ "", 60980 /* MRPS_REG_02C7 */ "", 60981 /* MRPS_REG_02C8 */ "", 60982 /* MRPS_REG_02CB */ "", 60983 /* MRPS_REG_02CE */ "", 60984 /* MRPS_RESERVED_MIRROR_ADDR */ "", 60985 /* MRPS_RESERVED_MTCD */ "", 60986 /* MRPS_RESERVED_MTCP */ "", 60987 /* MRPS_RESERVED_SPARE_0 */ "", 60988 /* MRPS_RESERVED_SPARE_1 */ "", 60989 /* MRPS_RESERVED_SPARE_2 */ "", 60990 /* MRPS_RESERVED_SPARE_3 */ "", 60991 /* MRPS_SBUS_BROADCAST_ID */ "", 60992 /* MRPS_SBUS_LAST_IN_CHAIN */ "", 60993 /* MRPS_SPECIAL_CLOCK_CONTROLS */ "", 60994 /* MSPI_CDRAM_00 */ "", 60995 /* MSPI_CDRAM_01 */ "", 60996 /* MSPI_CDRAM_02 */ "", 60997 /* MSPI_CDRAM_03 */ "", 60998 /* MSPI_CDRAM_04 */ "", 60999 /* MSPI_CDRAM_05 */ "", 61000 /* MSPI_CDRAM_06 */ "", 61001 /* MSPI_CDRAM_07 */ "", 61002 /* MSPI_CDRAM_08 */ "", 61003 /* MSPI_CDRAM_09 */ "", 61004 /* MSPI_CDRAM_10 */ "", 61005 /* MSPI_CDRAM_11 */ "", 61006 /* MSPI_CDRAM_12 */ "", 61007 /* MSPI_CDRAM_13 */ "", 61008 /* MSPI_CDRAM_14 */ "", 61009 /* MSPI_CDRAM_15 */ "", 61010 /* MSPI_CPTQP */ "", 61011 /* MSPI_ENDQP */ "", 61012 /* MSPI_NEWQP */ "", 61013 /* MSPI_RXRAM_00 */ "", 61014 /* MSPI_RXRAM_01 */ "", 61015 /* MSPI_RXRAM_02 */ "", 61016 /* MSPI_RXRAM_03 */ "", 61017 /* MSPI_RXRAM_04 */ "", 61018 /* MSPI_RXRAM_05 */ "", 61019 /* MSPI_RXRAM_06 */ "", 61020 /* MSPI_RXRAM_07 */ "", 61021 /* MSPI_RXRAM_08 */ "", 61022 /* MSPI_RXRAM_09 */ "", 61023 /* MSPI_RXRAM_10 */ "", 61024 /* MSPI_RXRAM_11 */ "", 61025 /* MSPI_RXRAM_12 */ "", 61026 /* MSPI_RXRAM_13 */ "", 61027 /* MSPI_RXRAM_14 */ "", 61028 /* MSPI_RXRAM_15 */ "", 61029 /* MSPI_RXRAM_16 */ "", 61030 /* MSPI_RXRAM_17 */ "", 61031 /* MSPI_RXRAM_18 */ "", 61032 /* MSPI_RXRAM_19 */ "", 61033 /* MSPI_RXRAM_20 */ "", 61034 /* MSPI_RXRAM_21 */ "", 61035 /* MSPI_RXRAM_22 */ "", 61036 /* MSPI_RXRAM_23 */ "", 61037 /* MSPI_RXRAM_24 */ "", 61038 /* MSPI_RXRAM_25 */ "", 61039 /* MSPI_RXRAM_26 */ "", 61040 /* MSPI_RXRAM_27 */ "", 61041 /* MSPI_RXRAM_28 */ "", 61042 /* MSPI_RXRAM_29 */ "", 61043 /* MSPI_RXRAM_30 */ "", 61044 /* MSPI_RXRAM_31 */ "", 61045 /* MSPI_SPCR2 */ "", 61046 /* MSPI_SPCR0_LSB */ "", 61047 /* MSPI_SPCR0_MSB */ "", 61048 /* MSPI_SPCR1_LSB */ "", 61049 /* MSPI_SPCR1_MSB */ "", 61050 /* MSPI_STATUS */ "", 61051 /* MSPI_TXRAM_00 */ "", 61052 /* MSPI_TXRAM_01 */ "", 61053 /* MSPI_TXRAM_02 */ "", 61054 /* MSPI_TXRAM_03 */ "", 61055 /* MSPI_TXRAM_04 */ "", 61056 /* MSPI_TXRAM_05 */ "", 61057 /* MSPI_TXRAM_06 */ "", 61058 /* MSPI_TXRAM_07 */ "", 61059 /* MSPI_TXRAM_08 */ "", 61060 /* MSPI_TXRAM_09 */ "", 61061 /* MSPI_TXRAM_10 */ "", 61062 /* MSPI_TXRAM_11 */ "", 61063 /* MSPI_TXRAM_12 */ "", 61064 /* MSPI_TXRAM_13 */ "", 61065 /* MSPI_TXRAM_14 */ "", 61066 /* MSPI_TXRAM_15 */ "", 61067 /* MSPI_TXRAM_16 */ "", 61068 /* MSPI_TXRAM_17 */ "", 61069 /* MSPI_TXRAM_18 */ "", 61070 /* MSPI_TXRAM_19 */ "", 61071 /* MSPI_TXRAM_20 */ "", 61072 /* MSPI_TXRAM_21 */ "", 61073 /* MSPI_TXRAM_22 */ "", 61074 /* MSPI_TXRAM_23 */ "", 61075 /* MSPI_TXRAM_24 */ "", 61076 /* MSPI_TXRAM_25 */ "", 61077 /* MSPI_TXRAM_26 */ "", 61078 /* MSPI_TXRAM_27 */ "", 61079 /* MSPI_TXRAM_28 */ "", 61080 /* MSPI_TXRAM_29 */ "", 61081 /* MSPI_TXRAM_30 */ "", 61082 /* MSPI_TXRAM_31 */ "", 61083 /* MTM_CONTINUES_BIER_ADDRESS_MODE */ "", 61084 /* MTM_DBG_EGR_LAST_MCDB_ADDR */ "", 61085 /* MTM_DBG_EQP_LAST_MCDB_ADDR */ "", 61086 /* MTM_DBG_ING_LAST_MCDB_ADDR */ "", 61087 /* MTM_ECC_1B_ERR_CNT */ "", 61088 /* MTM_ECC_2B_ERR_CNT */ "", 61089 /* MTM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 61090 /* MTM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 61091 /* MTM_ECC_INTERRUPT_REGISTER */ "", 61092 /* MTM_ECC_INTERRUPT_REGISTER_MASK */ "", 61093 /* MTM_ECC_INTERRUPT_REGISTER_TEST */ "", 61094 /* MTM_EGR_0_MCH_MCDB_REQUESTS_CTR */ "", 61095 /* MTM_EGR_0_MCH_REPLICATION_DISCARD_CTR */ "", 61096 /* MTM_EGR_0_MCL_MCDB_REQUESTS_CTR */ "", 61097 /* MTM_EGR_0_MCL_REPLICATION_DISCARD_CTR */ "", 61098 /* MTM_EGR_0_TDM_MCDB_REQUESTS_CTR */ "", 61099 /* MTM_EGR_0_TDM_REPLICATION_DISCARD_CTR */ "", 61100 /* MTM_EGR_0_UC_MCDB_REQUESTS_CTR */ "", 61101 /* MTM_EGR_0_UC_REPLICATION_DISCARD_CTR */ "", 61102 /* MTM_EGR_1_MCH_MCDB_REQUESTS_CTR */ "", 61103 /* MTM_EGR_1_MCH_REPLICATION_DISCARD_CTR */ "", 61104 /* MTM_EGR_1_MCL_MCDB_REQUESTS_CTR */ "", 61105 /* MTM_EGR_1_MCL_REPLICATION_DISCARD_CTR */ "", 61106 /* MTM_EGR_1_TDM_MCDB_REQUESTS_CTR */ "", 61107 /* MTM_EGR_1_TDM_REPLICATION_DISCARD_CTR */ "", 61108 /* MTM_EGR_1_UC_MCDB_REQUESTS_CTR */ "", 61109 /* MTM_EGR_1_UC_REPLICATION_DISCARD_CTR */ "", 61110 /* MTM_EGR_DISABLE */ "", 61111 /* MTM_EGR_ENG_DISABLE */ "", 61112 /* MTM_EGR_ERR_MAX_REPLICATION_MCID */ "", 61113 /* MTM_EGR_INVALID_CUD */ "", 61114 /* MTM_EGR_MAX_REPLICATIONS */ "", 61115 /* MTM_EGR_MCDB_BIER_OFFSET */ "", 61116 /* MTM_EGR_MCDB_OFFSET */ "", 61117 /* MTM_EGR_TDM_FULL_PACKET_MODE */ "", 61118 /* MTM_EG_ERR_REPLICATION_EMPTY_MCID */ "", 61119 /* MTM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 61120 /* MTM_EQP_0_MCDB_REQUESTS_CTR */ "", 61121 /* MTM_EQP_1_MCDB_REQUESTS_CTR */ "", 61122 /* MTM_EQP_MCDB_BIER_OFFSET */ "", 61123 /* MTM_ERROR_INITIATION_DATA */ "", 61124 /* MTM_GTIMER_CONFIGURATION */ "", 61125 /* MTM_GTIMER_CYCLE */ "", 61126 /* MTM_INDIRECT_COMMAND */ "", 61127 /* MTM_INDIRECT_COMMAND_ADDRESS */ "", 61128 /* MTM_INDIRECT_COMMAND_RD_DATA */ "", 61129 /* MTM_INDIRECT_COMMAND_WR_DATA */ "", 61130 /* MTM_INDIRECT_FORCE_BUBBLE */ "", 61131 /* MTM_ING_0_MCH_MCDB_REQUESTS_CTR */ "", 61132 /* MTM_ING_0_MCH_REPLICATION_DISCARD_CTR */ "", 61133 /* MTM_ING_0_MCL_MCDB_REQUESTS_CTR */ "", 61134 /* MTM_ING_0_MCL_REPLICATION_DISCARD_CTR */ "", 61135 /* MTM_ING_1_MCH_MCDB_REQUESTS_CTR */ "", 61136 /* MTM_ING_1_MCH_REPLICATION_DISCARD_CTR */ "", 61137 /* MTM_ING_1_MCL_MCDB_REQUESTS_CTR */ "", 61138 /* MTM_ING_1_MCL_REPLICATION_DISCARD_CTR */ "", 61139 /* MTM_ING_DISABLE */ "", 61140 /* MTM_ING_ENG_DISABLE */ "", 61141 /* MTM_ING_ERR_MAX_REPLICATION_MCID */ "", 61142 /* MTM_ING_ERR_REPLICATION_EMPTY_MCID */ "", 61143 /* MTM_ING_INVALID_CUD */ "", 61144 /* MTM_ING_MAX_REPLICATIONS */ "", 61145 /* MTM_ING_MCDB_BIER_OFFSET */ "", 61146 /* MTM_ING_MCDB_OFFSET */ "", 61147 /* MTM_INTERRUPT_MASK_REGISTER */ "", 61148 /* MTM_INTERRUPT_REGISTER */ "", 61149 /* MTM_INTERRUPT_REGISTER_TEST */ "", 61150 /* MTM_MCDB_BANK_COLLISION_CTR */ "", 61151 /* MTM_PCMI_0 */ "", 61152 /* MTM_PCMI_1 */ "", 61153 /* MTM_PCMI_2 */ "", 61154 /* MTM_PCMI_3 */ "", 61155 /* MTM_PCMI_4 */ "", 61156 /* MTM_PCMI_0_S */ "", 61157 /* MTM_PCMI_0_T */ "", 61158 /* MTM_PCMI_1_S */ "", 61159 /* MTM_PCMI_1_T */ "", 61160 /* MTM_PCMI_2_S */ "", 61161 /* MTM_PCMI_2_T */ "", 61162 /* MTM_PCMI_3_S */ "", 61163 /* MTM_PCMI_3_T */ "", 61164 /* MTM_PCMI_4_S */ "", 61165 /* MTM_PCMI_4_T */ "", 61166 /* MTM_REG_0041 */ "", 61167 /* MTM_REG_00A4 */ "", 61168 /* MTM_REG_00A6 */ "", 61169 /* MTM_REG_00C2 */ "", 61170 /* MTM_RESERVED_MIRROR_ADDR */ "", 61171 /* MTM_RESERVED_MTCD */ "", 61172 /* MTM_RESERVED_MTCP */ "", 61173 /* MTM_RESERVED_SPARE_0 */ "", 61174 /* MTM_RESERVED_SPARE_1 */ "", 61175 /* MTM_RESERVED_SPARE_2 */ "", 61176 /* MTM_RESERVED_SPARE_3 */ "", 61177 /* MTM_SBUS_BROADCAST_ID */ "", 61178 /* MTM_SBUS_LAST_IN_CHAIN */ "", 61179 /* MTM_X_4_BITMAP_FORMAT */ "", 61180 /* MTP_COS */ "", 61181 /* MTRI_BUCKET_OVERFLOW_INFO */ "", 61182 /* MTRI_BUCKET_OVERFLOW_INTR */ "", 61183 /* MTRI_BUCKET_OVERFLOW_MASK */ "", 61184 /* MTRI_CONFIG */ "", 61185 /* MTRI_EN_COR_ERR_RPT */ "", 61186 /* MTRI_IFG */ "", 61187 /* MTRI_MEMDEBUG */ "", 61188 /* MTRI_PORT_DISC */ "", 61189 /* MTRI_PORT_WARN */ "", 61190 /* MTRI_REFRESH_CONFIG */ "", 61191 /* MTROMEMDEBUG_CONFIG_0_L0 */ "", 61192 /* MTROMEMDEBUG_CONFIG_0_L1 */ "", 61193 /* MTROMEMDEBUG_CONFIG_0_L2 */ "", 61194 /* MTROMEMDEBUG_CONFIG_0_PORT */ "", 61195 /* MTROMEMDEBUG_CONFIG_0_S1 */ "", 61196 /* MTROMEMDEBUG_CONFIG_1_L0 */ "", 61197 /* MTROMEMDEBUG_CONFIG_1_L1 */ "", 61198 /* MTROMEMDEBUG_CONFIG_1_L2 */ "", 61199 /* MTROMEMDEBUG_CONFIG_1_PORT */ "", 61200 /* MTROMEMDEBUG_CONFIG_L0 */ "", 61201 /* MTROMEMDEBUG_CONFIG_L1 */ "", 61202 /* MTROMEMDEBUG_CONFIG_L2 */ "", 61203 /* MTRO_BUCKET_OVERFLOW_INFO */ "", 61204 /* MTRO_BUCKET_OVERFLOW_INTR */ "", 61205 /* MTRO_BUCKET_OVERFLOW_MASK */ "", 61206 /* MTRO_CONFIG */ "", 61207 /* MTRO_ENABLE_ECCP_MEM */ "", 61208 /* MTRO_EN_COR_ERR_RPT */ "", 61209 /* MTRO_EN_COR_ERR_RPT_0 */ "", 61210 /* MTRO_EN_COR_ERR_RPT_1 */ "", 61211 /* MTRO_MEMDEBUG_CONFIG_L0 */ "", 61212 /* MTRO_MEMDEBUG_CONFIG_L1 */ "", 61213 /* MTRO_MEMDEBUG_CONFIG_L2 */ "", 61214 /* MTRO_MEMDEBUG_CONFIG_L3 */ "", 61215 /* MTRO_MEMDEBUG_CONFIG_PORT */ "", 61216 /* MTRO_OVERFLOW_SEEN_L0_MAX_ID */ "", 61217 /* MTRO_OVERFLOW_SEEN_L0_MIN_ID */ "", 61218 /* MTRO_OVERFLOW_SEEN_L1_MAX_ID */ "", 61219 /* MTRO_OVERFLOW_SEEN_L1_MIN_ID */ "", 61220 /* MTRO_OVERFLOW_SEEN_L2_MAX_ID */ "", 61221 /* MTRO_OVERFLOW_SEEN_L2_MIN_ID */ "", 61222 /* MTRO_OVERFLOW_SEEN_PORT_ID */ "", 61223 /* MTRO_OVERFLOW_SEEN_S1_ID */ "", 61224 /* MTRO_OVERFLOW_UNDERRUN_STATUS */ "", 61225 /* MTRO_PG_METERED */ "", 61226 /* MTRO_PORT_ENTITY_DISABLE */ "", 61227 /* MTRO_PORT_ENTITY_DISABLE_SPLIT0 */ "", 61228 /* MTRO_PORT_ENTITY_DISABLE_SPLIT1 */ "", 61229 /* MTRO_PORT_METERED */ "", 61230 /* MTRO_REFRESH_CONFIG */ "", 61231 /* MTRO_REFRESH_STATUS */ "", 61232 /* MTRO_SHAPE_MAXMASK */ "", 61233 /* MTRO_SHAPE_MINMASK */ "", 61234 /* MTRO_UNDERRUN_CHECKER_0_0 */ "", 61235 /* MTRO_UNDERRUN_CHECKER_0_1 */ "", 61236 /* MTRO_UNDERRUN_CHECKER_0_2 */ "", 61237 /* MTRO_UNDERRUN_CHECKER_0_3 */ "", 61238 /* MTRO_UNDERRUN_MONITOR_STATUS */ "", 61239 /* MTRO_UNDERRUN_SEEN_L0_MAX_ID */ "", 61240 /* MTRO_UNDERRUN_SEEN_L0_MIN_ID */ "", 61241 /* MTRO_UNDERRUN_SEEN_L1_MAX_ID */ "", 61242 /* MTRO_UNDERRUN_SEEN_L1_MIN_ID */ "", 61243 /* MTRO_UNDERRUN_SEEN_L2_MAX_ID */ "", 61244 /* MTRO_UNDERRUN_SEEN_L2_MIN_ID */ "", 61245 /* MTRO_UNDERRUN_SEEN_PORT_ID */ "", 61246 /* MTRO_UNDERRUN_SEEN_S1_ID */ "", 61247 /* MTRPS_EM_ECC_1B_ERR_CNT */ "", 61248 /* MTRPS_EM_ECC_2B_ERR_CNT */ "", 61249 /* MTRPS_EM_ECC_ERR_1B_INITIATE */ "", 61250 /* MTRPS_EM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 61251 /* MTRPS_EM_ECC_ERR_2B_INITIATE */ "", 61252 /* MTRPS_EM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 61253 /* MTRPS_EM_ECC_INTERRUPT_REGISTER */ "", 61254 /* MTRPS_EM_ECC_INTERRUPT_REGISTER_MASK */ "", 61255 /* MTRPS_EM_ECC_INTERRUPT_REGISTER_TEST */ "", 61256 /* MTRPS_EM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 61257 /* MTRPS_EM_ERROR_INITIATION_DATA */ "", 61258 /* MTRPS_EM_GLBL_CFG */ "", 61259 /* MTRPS_EM_GLOBAL_GENERAL_CFG_2 */ "", 61260 /* MTRPS_EM_GLOBAL_MEM_OPTIONS */ "", 61261 /* MTRPS_EM_GTIMER_CONFIGURATION */ "", 61262 /* MTRPS_EM_GTIMER_TRIGGER */ "", 61263 /* MTRPS_EM_IDR_INTERFACE_DEBUG_COUNTERS */ "", 61264 /* MTRPS_EM_INCOMING_COLOR_MAP */ "", 61265 /* MTRPS_EM_INDIRECT_COMMAND */ "", 61266 /* MTRPS_EM_INDIRECT_COMMAND_ADDRESS */ "", 61267 /* MTRPS_EM_INDIRECT_COMMAND_DATA_INCREMENT */ "", 61268 /* MTRPS_EM_INDIRECT_COMMAND_RD_DATA */ "", 61269 /* MTRPS_EM_INDIRECT_COMMAND_WIDE_MEM */ "", 61270 /* MTRPS_EM_INDIRECT_COMMAND_WR_DATA */ "", 61271 /* MTRPS_EM_INDIRECT_FORCE_BUBBLE */ "", 61272 /* MTRPS_EM_INGRESS_IN_INTERFACE_DEBUG_COUNTERS */ "", 61273 /* MTRPS_EM_INGRESS_OUT_INTERFACE_DEBUG_COUNTERS */ "", 61274 /* MTRPS_EM_INIT_SEQ_ON */ "", 61275 /* MTRPS_EM_INTERRUPT_MASK_REGISTER */ "", 61276 /* MTRPS_EM_INTERRUPT_REGISTER */ "", 61277 /* MTRPS_EM_INTERRUPT_REGISTER_TEST */ "", 61278 /* MTRPS_EM_MCDA_CBL_STAT_CTR */ "", 61279 /* MTRPS_EM_MCDA_CFG */ "", 61280 /* MTRPS_EM_MCDA_EBL_STAT_CTR */ "", 61281 /* MTRPS_EM_MCDA_LAST_CMD_INDEX */ "", 61282 /* MTRPS_EM_MCDA_REFRESH_CFG */ "", 61283 /* MTRPS_EM_MCDA_STAT_CFG */ "", 61284 /* MTRPS_EM_MCDA_WRAP_INDEX */ "", 61285 /* MTRPS_EM_MCDB_CBL_STAT_CTR */ "", 61286 /* MTRPS_EM_MCDB_CFG */ "", 61287 /* MTRPS_EM_MCDB_EBL_STAT_CTR */ "", 61288 /* MTRPS_EM_MCDB_LAST_CMD_INDEX */ "", 61289 /* MTRPS_EM_MCDB_REFRESH_CFG */ "", 61290 /* MTRPS_EM_MCDB_STAT_CFG */ "", 61291 /* MTRPS_EM_MCDB_WRAP_INDEX */ "", 61292 /* MTRPS_EM_RESERVED_MIRROR_ADDR */ "", 61293 /* MTRPS_EM_RESERVED_MTCD */ "", 61294 /* MTRPS_EM_RESERVED_MTCP */ "", 61295 /* MTRPS_EM_RESERVED_SPARE_0 */ "", 61296 /* MTRPS_EM_RESERVED_SPARE_1 */ "", 61297 /* MTRPS_EM_RESERVED_SPARE_2 */ "", 61298 /* MTRPS_EM_RESERVED_SPARE_3 */ "", 61299 /* MTRPS_EM_SBUS_BROADCAST_ID */ "", 61300 /* MTRPS_EM_SBUS_LAST_IN_CHAIN */ "", 61301 /* MTU_PRIORITY */ "", 61302 /* MULTIPASS_LOOPBACK_BITMAP_64 */ "MULTIPASS_LOOPBACK_BITMAP", 61303 /* MULTI_MEM_ERR */ "", 61304 /* MXQ_R64 */ "MXQ_GRx64", 61305 /* MXQ_R127 */ "MXQ_GRx127", 61306 /* MXQ_R255 */ "MXQ_GRx255", 61307 /* MXQ_R511 */ "MXQ_GRx511", 61308 /* MXQ_R1023 */ "MXQ_GRx1023", 61309 /* MXQ_R1518 */ "MXQ_GRx1518", 61310 /* MXQ_R2047 */ "MXQ_GRx2047", 61311 /* MXQ_R4095 */ "MXQ_GRx4095", 61312 /* MXQ_R9216 */ "MXQ_GRx9216", 61313 /* MXQ_R16383 */ "MXQ_GRx16383", 61314 /* MXQ_RALN */ "MXQ_GRxALN", 61315 /* MXQ_RBCA */ "MXQ_GRxBCA", 61316 /* MXQ_RBYT */ "MXQ_GRxByt", 61317 /* MXQ_RDVLN */ "MXQ_GRxDVLN", 61318 /* MXQ_RERPKT */ "MXQ_GRxFrErr", 61319 /* MXQ_RFCR */ "MXQ_GRxFCR", 61320 /* MXQ_RFCS */ "MXQ_GRxFCS", 61321 /* MXQ_RFLR */ "MXQ_GRxFLR", 61322 /* MXQ_RFRG */ "MXQ_GRxFRG", 61323 /* MXQ_RJBR */ "MXQ_GRxJBR", 61324 /* MXQ_RMCA */ "MXQ_GRxMCA", 61325 /* MXQ_RMCRC */ "MXQ_GRxMCRC", 61326 /* MXQ_RMGV */ "MXQ_GRx1522", 61327 /* MXQ_RMTUE */ "MXQ_GRxMTUE", 61328 /* MXQ_ROVR */ "MXQ_GRxOVR", 61329 /* MXQ_RPFC0 */ "MXQ_GRxPFCP0", 61330 /* MXQ_RPFC1 */ "MXQ_GRxPFCP1", 61331 /* MXQ_RPFC2 */ "MXQ_GRxPFCP2", 61332 /* MXQ_RPFC3 */ "MXQ_GRxPFCP3", 61333 /* MXQ_RPFC4 */ "MXQ_GRxPFCP4", 61334 /* MXQ_RPFC5 */ "MXQ_GRxPFCP5", 61335 /* MXQ_RPFC6 */ "MXQ_GRxPFCP6", 61336 /* MXQ_RPFC7 */ "MXQ_GRxPFCP7", 61337 /* MXQ_RPFCOFF0 */ "MXQ_GRxPFCOFF0", 61338 /* MXQ_RPFCOFF1 */ "MXQ_GRxPFCOFF1", 61339 /* MXQ_RPFCOFF2 */ "MXQ_GRxPFCOFF2", 61340 /* MXQ_RPFCOFF3 */ "MXQ_GRxPFCOFF3", 61341 /* MXQ_RPFCOFF4 */ "MXQ_GRxPFCOFF4", 61342 /* MXQ_RPFCOFF5 */ "MXQ_GRxPFCOFF5", 61343 /* MXQ_RPFCOFF6 */ "MXQ_GRxPFCOFF6", 61344 /* MXQ_RPFCOFF7 */ "MXQ_GRxPFCOFF7", 61345 /* MXQ_RPKT */ "MXQ_GRxPkt", 61346 /* MXQ_RPOK */ "MXQ_GRxPOK", 61347 /* MXQ_RPRM */ "MXQ_GRxPRM", 61348 /* MXQ_RRBYT */ "MXQ_GRxRBYT", 61349 /* MXQ_RRPKT */ "MXQ_GRxRPKT", 61350 /* MXQ_RSCHCRC */ "MXQ_GRxSCHCRC", 61351 /* MXQ_RTRFU */ "MXQ_GRxTRFU", 61352 /* MXQ_RUCA */ "MXQ_GRxUCA", 61353 /* MXQ_RUND */ "MXQ_GRxUND", 61354 /* MXQ_RVLN */ "MXQ_GRxVLN", 61355 /* MXQ_RXCF */ "MXQ_GRxCF", 61356 /* MXQ_RXPF */ "MXQ_GRxPF", 61357 /* MXQ_RXPP */ "MXQ_GRxPP", 61358 /* MXQ_RXUDA */ "MXQ_GRxUDA", 61359 /* MXQ_RXUO */ "MXQ_GRxUO", 61360 /* MXQ_RXWSA */ "MXQ_GRxWSA", 61361 /* MXQ_RX_EEE_LPI_DURATION_COUNTER */ "", 61362 /* MXQ_RX_EEE_LPI_EVENT_COUNTER */ "", 61363 /* MXQ_RX_LLFC_CRC_COUNTER */ "", 61364 /* MXQ_RX_LLFC_LOG_COUNTER */ "", 61365 /* MXQ_RX_LLFC_PHY_COUNTER */ "", 61366 /* MXQ_T64 */ "MXQ_GTx64", 61367 /* MXQ_T127 */ "MXQ_GTx127", 61368 /* MXQ_T255 */ "MXQ_GTx255", 61369 /* MXQ_T511 */ "MXQ_GTx511", 61370 /* MXQ_T1023 */ "MXQ_GTx1023", 61371 /* MXQ_T1518 */ "MXQ_GTx1518", 61372 /* MXQ_T2047 */ "MXQ_GTx2047", 61373 /* MXQ_T4095 */ "MXQ_GTx4095", 61374 /* MXQ_T9216 */ "MXQ_GTx9216", 61375 /* MXQ_T16383 */ "MXQ_GTx16383", 61376 /* MXQ_TBCA */ "MXQ_GTxBCA", 61377 /* MXQ_TBYT */ "MXQ_GTxBYT", 61378 /* MXQ_TDFR */ "MXQ_GTxDFR", 61379 /* MXQ_TDVLN */ "MXQ_GTxDVLN", 61380 /* MXQ_TEDF */ "MXQ_GTxEDF", 61381 /* MXQ_TERR */ "MXQ_GTxErr", 61382 /* MXQ_TFCS */ "MXQ_GTxFCS", 61383 /* MXQ_TFRG */ "MXQ_GTxFRG", 61384 /* MXQ_TJBR */ "MXQ_GTxJBR", 61385 /* MXQ_TLCL */ "MXQ_GTxLCL", 61386 /* MXQ_TMCA */ "MXQ_GTxMCA", 61387 /* MXQ_TMCL */ "MXQ_GTxMCL", 61388 /* MXQ_TMGV */ "MXQ_GTx1522", 61389 /* MXQ_TNCL */ "MXQ_GTxNCL", 61390 /* MXQ_TOVR */ "MXQ_GTxOVR", 61391 /* MXQ_TPFC0 */ "MXQ_GTxPFCP0", 61392 /* MXQ_TPFC1 */ "MXQ_GTxPFCP1", 61393 /* MXQ_TPFC2 */ "MXQ_GTxPFCP2", 61394 /* MXQ_TPFC3 */ "MXQ_GTxPFCP3", 61395 /* MXQ_TPFC4 */ "MXQ_GTxPFCP4", 61396 /* MXQ_TPFC5 */ "MXQ_GTxPFCP5", 61397 /* MXQ_TPFC6 */ "MXQ_GTxPFCP6", 61398 /* MXQ_TPFC7 */ "MXQ_GTxPFCP7", 61399 /* MXQ_TPKT */ "MXQ_GTxPkt", 61400 /* MXQ_TPOK */ "MXQ_GTxPOK", 61401 /* MXQ_TRPKT */ "MXQ_GTxRPKT", 61402 /* MXQ_TSCL */ "MXQ_GTxSCL", 61403 /* MXQ_TUCA */ "MXQ_GTxUCA", 61404 /* MXQ_TUFL */ "MXQ_GTxUFL", 61405 /* MXQ_TVLN */ "MXQ_GTxVLN", 61406 /* MXQ_TXCF */ "MXQ_GTxCF", 61407 /* MXQ_TXCL */ "MXQ_GTxXCL", 61408 /* MXQ_TXPF */ "MXQ_GTxPF", 61409 /* MXQ_TXPP */ "MXQ_GTxPP", 61410 /* MXQ_TX_EEE_LPI_DURATION_COUNTER */ "", 61411 /* MXQ_TX_EEE_LPI_EVENT_COUNTER */ "", 61412 /* MXQ_TX_LLFC_LOG_COUNTER */ "", 61413 /* MXQ_XLMAC_TIMESTAMP_BYTE_ADJUST */ "", 61414 /* MY_MODID_CONFIG */ "", 61415 /* MY_MODID_CONFIG_2 */ "", 61416 /* MY_MODID_CONFIG_2_PIPE0 */ "", 61417 /* MY_MODID_CONFIG_2_PIPE1 */ "", 61418 /* MY_MODID_SET_64 */ "", 61419 /* MY_MODID_SET_2_64 */ "", 61420 /* MY_MODID_SET_3_64 */ "", 61421 /* MY_MODID_SET_4_64 */ "", 61422 /* MY_STATION_2_CAM_BIST_CONFIG */ "", 61423 /* MY_STATION_2_CAM_BIST_CONTROL */ "", 61424 /* MY_STATION_2_CAM_BIST_DBG_DATA */ "", 61425 /* MY_STATION_2_CAM_BIST_STATUS */ "", 61426 /* MY_STATION_2_CAM_CONTROL */ "", 61427 /* MY_STATION_2_DATA_CONTROL */ "", 61428 /* MY_STATION_CAM_BIST_CONFIG */ "", 61429 /* MY_STATION_CAM_BIST_CONFIG_64 */ "", 61430 /* MY_STATION_CAM_BIST_CONFIG_64_PIPE0 */ "", 61431 /* MY_STATION_CAM_BIST_CONFIG_64_PIPE1 */ "", 61432 /* MY_STATION_CAM_BIST_CONFIG_64_PIPE2 */ "", 61433 /* MY_STATION_CAM_BIST_CONFIG_64_PIPE3 */ "", 61434 /* MY_STATION_CAM_BIST_CONFIG_PIPE0 */ "", 61435 /* MY_STATION_CAM_BIST_CONFIG_PIPE1 */ "", 61436 /* MY_STATION_CAM_BIST_CONFIG_PIPE2 */ "", 61437 /* MY_STATION_CAM_BIST_CONFIG_PIPE3 */ "", 61438 /* MY_STATION_CAM_BIST_CONTROL */ "", 61439 /* MY_STATION_CAM_BIST_CONTROL_PIPE0 */ "", 61440 /* MY_STATION_CAM_BIST_CONTROL_PIPE1 */ "", 61441 /* MY_STATION_CAM_BIST_CONTROL_PIPE2 */ "", 61442 /* MY_STATION_CAM_BIST_CONTROL_PIPE3 */ "", 61443 /* MY_STATION_CAM_BIST_DBG_DATA */ "", 61444 /* MY_STATION_CAM_BIST_DBG_DATA_PIPE0 */ "", 61445 /* MY_STATION_CAM_BIST_DBG_DATA_PIPE1 */ "", 61446 /* MY_STATION_CAM_BIST_DBG_DATA_PIPE2 */ "", 61447 /* MY_STATION_CAM_BIST_DBG_DATA_PIPE3 */ "", 61448 /* MY_STATION_CAM_BIST_STATUS */ "", 61449 /* MY_STATION_CAM_BIST_STATUS_PIPE0 */ "", 61450 /* MY_STATION_CAM_BIST_STATUS_PIPE1 */ "", 61451 /* MY_STATION_CAM_BIST_STATUS_PIPE2 */ "", 61452 /* MY_STATION_CAM_BIST_STATUS_PIPE3 */ "", 61453 /* MY_STATION_CAM_CONTROL */ "", 61454 /* MY_STATION_CAM_CONTROL_PIPE0 */ "", 61455 /* MY_STATION_CAM_CONTROL_PIPE1 */ "", 61456 /* MY_STATION_CAM_CONTROL_PIPE2 */ "", 61457 /* MY_STATION_CAM_CONTROL_PIPE3 */ "", 61458 /* MY_STATION_CAM_DBGCTRL */ "MY_STATION_CAM_CONTROL", 61459 /* MY_STATION_DATA_PARITY_CONTROL */ "", 61460 /* MY_STATION_DATA_PARITY_STATUS_INTR */ "", 61461 /* MY_STATION_DATA_PARITY_STATUS_NACK */ "", 61462 /* MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_CONFIG_64 */ "", 61463 /* MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE0 */ "", 61464 /* MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_CONFIG_64_PIPE1 */ "", 61465 /* MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_STATUS */ "", 61466 /* MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_STATUS_PIPE0 */ "", 61467 /* MY_STATION_TCAM_2_ENTRY_ONLY_CAM_BIST_STATUS_PIPE1 */ "", 61468 /* MY_STATION_TCAM_CAM_BIST_CONFIG */ "", 61469 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE0 */ "", 61470 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE1 */ "", 61471 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE2 */ "", 61472 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE3 */ "", 61473 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE4 */ "", 61474 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE5 */ "", 61475 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE6 */ "", 61476 /* MY_STATION_TCAM_CAM_BIST_CONFIG_PIPE7 */ "", 61477 /* MY_STATION_TCAM_CAM_BIST_DBGCTRL */ "MY_STATION_TCAM_CAM_BIST_CONTROL", 61478 /* MY_STATION_TCAM_CAM_BIST_DBG_DATA */ "", 61479 /* MY_STATION_TCAM_CAM_BIST_STATUS */ "", 61480 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE0 */ "", 61481 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE1 */ "", 61482 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE2 */ "", 61483 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE3 */ "", 61484 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE4 */ "", 61485 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE5 */ "", 61486 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE6 */ "", 61487 /* MY_STATION_TCAM_CAM_BIST_STATUS_PIPE7 */ "", 61488 /* MY_STATION_TCAM_CAM_DBGCTRL */ "MY_STATION_TCAM_CAM_CONTROL", 61489 /* MY_STATION_TCAM_CAM_SERCTRL */ "MY_STATION_TCAM_CAM_CONTROL", 61490 /* MY_STATION_TCAM_DATA_DBGCTRL */ "MY_STATION_TCAM_DATA_CONTROL", 61491 /* MY_STATION_TCAM_DATA_ONLY_PARITY_STATUS_INTR */ "", 61492 /* MY_STATION_TCAM_DATA_ONLY_PARITY_STATUS_NACK */ "", 61493 /* MY_STATION_TCAM_DATA_PARITY_CONTROL */ "", 61494 /* MY_STATION_TCAM_DATA_PARITY_STATUS */ "", 61495 /* NAND_BLOCK_ERASE_COMPLETE */ "", 61496 /* NAND_COPY_BACK_COMPLETE */ "", 61497 /* NAND_DIRECT_READ_RD_MISS */ "", 61498 /* NAND_ECC_MIPS_CORR */ "", 61499 /* NAND_ECC_MIPS_UNCORR */ "", 61500 /* NAND_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 61501 /* NAND_IDM_IDM_ERROR_LOG_COMPLETE */ "", 61502 /* NAND_IDM_IDM_ERROR_LOG_CONTROL */ "", 61503 /* NAND_IDM_IDM_ERROR_LOG_FLAGS */ "", 61504 /* NAND_IDM_IDM_ERROR_LOG_ID */ "", 61505 /* NAND_IDM_IDM_ERROR_LOG_STATUS */ "", 61506 /* NAND_IDM_IDM_INTERRUPT_STATUS */ "", 61507 /* NAND_IDM_IDM_IO_CONTROL_DIRECT */ "", 61508 /* NAND_IDM_IDM_IO_STATUS */ "", 61509 /* NAND_IDM_IDM_RESET_CONTROL */ "", 61510 /* NAND_IDM_IDM_RESET_READ_ID */ "", 61511 /* NAND_IDM_IDM_RESET_STATUS */ "", 61512 /* NAND_IDM_IDM_RESET_WRITE_ID */ "", 61513 /* NAND_NAND_FLASH_ACC_CONTROL_CS0 */ "", 61514 /* NAND_NAND_FLASH_ACC_CONTROL_CS1 */ "", 61515 /* NAND_NAND_FLASH_BLK_WR_PROTECT */ "", 61516 /* NAND_NAND_FLASH_BLOCK_ERASE_ADDR */ "", 61517 /* NAND_NAND_FLASH_BLOCK_ERASE_EXT_ADDR */ "", 61518 /* NAND_NAND_FLASH_BLOCK_LOCK_STATUS */ "", 61519 /* NAND_NAND_FLASH_CMD_ADDRESS */ "", 61520 /* NAND_NAND_FLASH_CMD_END_ADDRESS */ "", 61521 /* NAND_NAND_FLASH_CMD_EXT_ADDRESS */ "", 61522 /* NAND_NAND_FLASH_CMD_START */ "", 61523 /* NAND_NAND_FLASH_CONFIG_CS0 */ "", 61524 /* NAND_NAND_FLASH_CONFIG_CS1 */ "", 61525 /* NAND_NAND_FLASH_COPY_BACK_ADDR */ "", 61526 /* NAND_NAND_FLASH_COPY_BACK_EXT_ADDR */ "", 61527 /* NAND_NAND_FLASH_CORR_ERROR_COUNT */ "", 61528 /* NAND_NAND_FLASH_CORR_STAT_THRESHOLD */ "", 61529 /* NAND_NAND_FLASH_CS_NAND_SELECT */ "", 61530 /* NAND_NAND_FLASH_CS_NAND_XOR */ "", 61531 /* NAND_NAND_FLASH_ECC_CORR_ADDR */ "", 61532 /* NAND_NAND_FLASH_ECC_CORR_EXT_ADDR */ "", 61533 /* NAND_NAND_FLASH_ECC_UNC_ADDR */ "", 61534 /* NAND_NAND_FLASH_ECC_UNC_EXT_ADDR */ "", 61535 /* NAND_NAND_FLASH_FLASH_CACHE0 */ "", 61536 /* NAND_NAND_FLASH_FLASH_CACHE1 */ "", 61537 /* NAND_NAND_FLASH_FLASH_CACHE2 */ "", 61538 /* NAND_NAND_FLASH_FLASH_CACHE3 */ "", 61539 /* NAND_NAND_FLASH_FLASH_CACHE4 */ "", 61540 /* NAND_NAND_FLASH_FLASH_CACHE5 */ "", 61541 /* NAND_NAND_FLASH_FLASH_CACHE6 */ "", 61542 /* NAND_NAND_FLASH_FLASH_CACHE7 */ "", 61543 /* NAND_NAND_FLASH_FLASH_CACHE8 */ "", 61544 /* NAND_NAND_FLASH_FLASH_CACHE9 */ "", 61545 /* NAND_NAND_FLASH_FLASH_CACHE10 */ "", 61546 /* NAND_NAND_FLASH_FLASH_CACHE11 */ "", 61547 /* NAND_NAND_FLASH_FLASH_CACHE12 */ "", 61548 /* NAND_NAND_FLASH_FLASH_CACHE13 */ "", 61549 /* NAND_NAND_FLASH_FLASH_CACHE14 */ "", 61550 /* NAND_NAND_FLASH_FLASH_CACHE15 */ "", 61551 /* NAND_NAND_FLASH_FLASH_CACHE16 */ "", 61552 /* NAND_NAND_FLASH_FLASH_CACHE17 */ "", 61553 /* NAND_NAND_FLASH_FLASH_CACHE18 */ "", 61554 /* NAND_NAND_FLASH_FLASH_CACHE19 */ "", 61555 /* NAND_NAND_FLASH_FLASH_CACHE20 */ "", 61556 /* NAND_NAND_FLASH_FLASH_CACHE21 */ "", 61557 /* NAND_NAND_FLASH_FLASH_CACHE22 */ "", 61558 /* NAND_NAND_FLASH_FLASH_CACHE23 */ "", 61559 /* NAND_NAND_FLASH_FLASH_CACHE24 */ "", 61560 /* NAND_NAND_FLASH_FLASH_CACHE25 */ "", 61561 /* NAND_NAND_FLASH_FLASH_CACHE26 */ "", 61562 /* NAND_NAND_FLASH_FLASH_CACHE27 */ "", 61563 /* NAND_NAND_FLASH_FLASH_CACHE28 */ "", 61564 /* NAND_NAND_FLASH_FLASH_CACHE29 */ "", 61565 /* NAND_NAND_FLASH_FLASH_CACHE30 */ "", 61566 /* NAND_NAND_FLASH_FLASH_CACHE31 */ "", 61567 /* NAND_NAND_FLASH_FLASH_CACHE32 */ "", 61568 /* NAND_NAND_FLASH_FLASH_CACHE33 */ "", 61569 /* NAND_NAND_FLASH_FLASH_CACHE34 */ "", 61570 /* NAND_NAND_FLASH_FLASH_CACHE35 */ "", 61571 /* NAND_NAND_FLASH_FLASH_CACHE36 */ "", 61572 /* NAND_NAND_FLASH_FLASH_CACHE37 */ "", 61573 /* NAND_NAND_FLASH_FLASH_CACHE38 */ "", 61574 /* NAND_NAND_FLASH_FLASH_CACHE39 */ "", 61575 /* NAND_NAND_FLASH_FLASH_CACHE40 */ "", 61576 /* NAND_NAND_FLASH_FLASH_CACHE41 */ "", 61577 /* NAND_NAND_FLASH_FLASH_CACHE42 */ "", 61578 /* NAND_NAND_FLASH_FLASH_CACHE43 */ "", 61579 /* NAND_NAND_FLASH_FLASH_CACHE44 */ "", 61580 /* NAND_NAND_FLASH_FLASH_CACHE45 */ "", 61581 /* NAND_NAND_FLASH_FLASH_CACHE46 */ "", 61582 /* NAND_NAND_FLASH_FLASH_CACHE47 */ "", 61583 /* NAND_NAND_FLASH_FLASH_CACHE48 */ "", 61584 /* NAND_NAND_FLASH_FLASH_CACHE49 */ "", 61585 /* NAND_NAND_FLASH_FLASH_CACHE50 */ "", 61586 /* NAND_NAND_FLASH_FLASH_CACHE51 */ "", 61587 /* NAND_NAND_FLASH_FLASH_CACHE52 */ "", 61588 /* NAND_NAND_FLASH_FLASH_CACHE53 */ "", 61589 /* NAND_NAND_FLASH_FLASH_CACHE54 */ "", 61590 /* NAND_NAND_FLASH_FLASH_CACHE55 */ "", 61591 /* NAND_NAND_FLASH_FLASH_CACHE56 */ "", 61592 /* NAND_NAND_FLASH_FLASH_CACHE57 */ "", 61593 /* NAND_NAND_FLASH_FLASH_CACHE58 */ "", 61594 /* NAND_NAND_FLASH_FLASH_CACHE59 */ "", 61595 /* NAND_NAND_FLASH_FLASH_CACHE60 */ "", 61596 /* NAND_NAND_FLASH_FLASH_CACHE61 */ "", 61597 /* NAND_NAND_FLASH_FLASH_CACHE62 */ "", 61598 /* NAND_NAND_FLASH_FLASH_CACHE63 */ "", 61599 /* NAND_NAND_FLASH_FLASH_CACHE64 */ "", 61600 /* NAND_NAND_FLASH_FLASH_CACHE65 */ "", 61601 /* NAND_NAND_FLASH_FLASH_CACHE66 */ "", 61602 /* NAND_NAND_FLASH_FLASH_CACHE67 */ "", 61603 /* NAND_NAND_FLASH_FLASH_CACHE68 */ "", 61604 /* NAND_NAND_FLASH_FLASH_CACHE69 */ "", 61605 /* NAND_NAND_FLASH_FLASH_CACHE70 */ "", 61606 /* NAND_NAND_FLASH_FLASH_CACHE71 */ "", 61607 /* NAND_NAND_FLASH_FLASH_CACHE72 */ "", 61608 /* NAND_NAND_FLASH_FLASH_CACHE73 */ "", 61609 /* NAND_NAND_FLASH_FLASH_CACHE74 */ "", 61610 /* NAND_NAND_FLASH_FLASH_CACHE75 */ "", 61611 /* NAND_NAND_FLASH_FLASH_CACHE76 */ "", 61612 /* NAND_NAND_FLASH_FLASH_CACHE77 */ "", 61613 /* NAND_NAND_FLASH_FLASH_CACHE78 */ "", 61614 /* NAND_NAND_FLASH_FLASH_CACHE79 */ "", 61615 /* NAND_NAND_FLASH_FLASH_CACHE80 */ "", 61616 /* NAND_NAND_FLASH_FLASH_CACHE81 */ "", 61617 /* NAND_NAND_FLASH_FLASH_CACHE82 */ "", 61618 /* NAND_NAND_FLASH_FLASH_CACHE83 */ "", 61619 /* NAND_NAND_FLASH_FLASH_CACHE84 */ "", 61620 /* NAND_NAND_FLASH_FLASH_CACHE85 */ "", 61621 /* NAND_NAND_FLASH_FLASH_CACHE86 */ "", 61622 /* NAND_NAND_FLASH_FLASH_CACHE87 */ "", 61623 /* NAND_NAND_FLASH_FLASH_CACHE88 */ "", 61624 /* NAND_NAND_FLASH_FLASH_CACHE89 */ "", 61625 /* NAND_NAND_FLASH_FLASH_CACHE90 */ "", 61626 /* NAND_NAND_FLASH_FLASH_CACHE91 */ "", 61627 /* NAND_NAND_FLASH_FLASH_CACHE92 */ "", 61628 /* NAND_NAND_FLASH_FLASH_CACHE93 */ "", 61629 /* NAND_NAND_FLASH_FLASH_CACHE94 */ "", 61630 /* NAND_NAND_FLASH_FLASH_CACHE95 */ "", 61631 /* NAND_NAND_FLASH_FLASH_CACHE96 */ "", 61632 /* NAND_NAND_FLASH_FLASH_CACHE97 */ "", 61633 /* NAND_NAND_FLASH_FLASH_CACHE98 */ "", 61634 /* NAND_NAND_FLASH_FLASH_CACHE99 */ "", 61635 /* NAND_NAND_FLASH_FLASH_CACHE100 */ "", 61636 /* NAND_NAND_FLASH_FLASH_CACHE101 */ "", 61637 /* NAND_NAND_FLASH_FLASH_CACHE102 */ "", 61638 /* NAND_NAND_FLASH_FLASH_CACHE103 */ "", 61639 /* NAND_NAND_FLASH_FLASH_CACHE104 */ "", 61640 /* NAND_NAND_FLASH_FLASH_CACHE105 */ "", 61641 /* NAND_NAND_FLASH_FLASH_CACHE106 */ "", 61642 /* NAND_NAND_FLASH_FLASH_CACHE107 */ "", 61643 /* NAND_NAND_FLASH_FLASH_CACHE108 */ "", 61644 /* NAND_NAND_FLASH_FLASH_CACHE109 */ "", 61645 /* NAND_NAND_FLASH_FLASH_CACHE110 */ "", 61646 /* NAND_NAND_FLASH_FLASH_CACHE111 */ "", 61647 /* NAND_NAND_FLASH_FLASH_CACHE112 */ "", 61648 /* NAND_NAND_FLASH_FLASH_CACHE113 */ "", 61649 /* NAND_NAND_FLASH_FLASH_CACHE114 */ "", 61650 /* NAND_NAND_FLASH_FLASH_CACHE115 */ "", 61651 /* NAND_NAND_FLASH_FLASH_CACHE116 */ "", 61652 /* NAND_NAND_FLASH_FLASH_CACHE117 */ "", 61653 /* NAND_NAND_FLASH_FLASH_CACHE118 */ "", 61654 /* NAND_NAND_FLASH_FLASH_CACHE119 */ "", 61655 /* NAND_NAND_FLASH_FLASH_CACHE120 */ "", 61656 /* NAND_NAND_FLASH_FLASH_CACHE121 */ "", 61657 /* NAND_NAND_FLASH_FLASH_CACHE122 */ "", 61658 /* NAND_NAND_FLASH_FLASH_CACHE123 */ "", 61659 /* NAND_NAND_FLASH_FLASH_CACHE124 */ "", 61660 /* NAND_NAND_FLASH_FLASH_CACHE125 */ "", 61661 /* NAND_NAND_FLASH_FLASH_CACHE126 */ "", 61662 /* NAND_NAND_FLASH_FLASH_CACHE127 */ "", 61663 /* NAND_NAND_FLASH_FLASH_DEVICE_ID */ "", 61664 /* NAND_NAND_FLASH_FLASH_DEVICE_ID_EXT */ "", 61665 /* NAND_NAND_FLASH_FLASH_READ_ADDR */ "", 61666 /* NAND_NAND_FLASH_FLASH_READ_EXT_ADDR */ "", 61667 /* NAND_NAND_FLASH_INIT_STATUS */ "", 61668 /* NAND_NAND_FLASH_INTFC_STATUS */ "", 61669 /* NAND_NAND_FLASH_INV_READ_ADDR */ "", 61670 /* NAND_NAND_FLASH_INV_READ_EXT_ADDR */ "", 61671 /* NAND_NAND_FLASH_LL_OP */ "", 61672 /* NAND_NAND_FLASH_LL_RDDATA */ "", 61673 /* NAND_NAND_FLASH_MPLANE_BASE_ADDRESS */ "", 61674 /* NAND_NAND_FLASH_MPLANE_BASE_EXT_ADDRESS */ "", 61675 /* NAND_NAND_FLASH_MULTIPLANE_CTRL */ "", 61676 /* NAND_NAND_FLASH_MULTIPLANE_OPCODES_1 */ "", 61677 /* NAND_NAND_FLASH_MULTIPLANE_OPCODES_2 */ "", 61678 /* NAND_NAND_FLASH_ONFI_DEBUG_DATA */ "", 61679 /* NAND_NAND_FLASH_ONFI_STATUS */ "", 61680 /* NAND_NAND_FLASH_PROGRAM_PAGE_ADDR */ "", 61681 /* NAND_NAND_FLASH_PROGRAM_PAGE_EXT_ADDR */ "", 61682 /* NAND_NAND_FLASH_READ_ERROR_COUNT */ "", 61683 /* NAND_NAND_FLASH_REVISION */ "", 61684 /* NAND_NAND_FLASH_SEMAPHORE */ "", 61685 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_0 */ "", 61686 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_4 */ "", 61687 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_8 */ "", 61688 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_10 */ "", 61689 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_14 */ "", 61690 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_18 */ "", 61691 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_20 */ "", 61692 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_24 */ "", 61693 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_28 */ "", 61694 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_30 */ "", 61695 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_34 */ "", 61696 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_38 */ "", 61697 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_1C */ "", 61698 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_2C */ "", 61699 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_3C */ "", 61700 /* NAND_NAND_FLASH_SPARE_AREA_READ_OFS_C */ "", 61701 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_0 */ "", 61702 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_4 */ "", 61703 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_8 */ "", 61704 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_10 */ "", 61705 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_14 */ "", 61706 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_18 */ "", 61707 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_20 */ "", 61708 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_24 */ "", 61709 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_28 */ "", 61710 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_30 */ "", 61711 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_34 */ "", 61712 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_38 */ "", 61713 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_1C */ "", 61714 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_2C */ "", 61715 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_3C */ "", 61716 /* NAND_NAND_FLASH_SPARE_AREA_WRITE_OFS_C */ "", 61717 /* NAND_NAND_FLASH_TIMING_1_CS0 */ "", 61718 /* NAND_NAND_FLASH_TIMING_1_CS1 */ "", 61719 /* NAND_NAND_FLASH_TIMING_2_CS0 */ "", 61720 /* NAND_NAND_FLASH_TIMING_2_CS1 */ "", 61721 /* NAND_NAND_FLASH_UNCORR_ERROR_COUNT */ "", 61722 /* NAND_NAND_RB_B */ "", 61723 /* NAND_PROGRAM_PAGE_COMPLETE */ "", 61724 /* NAND_RO_CTLR_READY */ "", 61725 /* NANOSYNC_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 61726 /* NANOSYNC_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 61727 /* NANOSYNC_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 61728 /* NANOSYNC_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 61729 /* NANOSYNC_S0_IDM_IDM_ERROR_LOG_ID */ "", 61730 /* NANOSYNC_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 61731 /* NANOSYNC_S0_IDM_IDM_INTERRUPT_STATUS */ "", 61732 /* NANOSYNC_S0_IDM_IDM_RESET_CONTROL */ "", 61733 /* NANOSYNC_S0_IDM_IDM_RESET_READ_ID */ "", 61734 /* NANOSYNC_S0_IDM_IDM_RESET_STATUS */ "", 61735 /* NANOSYNC_S0_IDM_IDM_RESET_WRITE_ID */ "", 61736 /* NBIH_ADDITIONAL_RESETS */ "", 61737 /* NBIH_BIST_CONTEXTS_MASK */ "", 61738 /* NBIH_BIST_CONTEXT_TO_EGQ_PORT_MAP */ "", 61739 /* NBIH_BIST_CONTEXT_TO_NIF_PORT_MAP */ "", 61740 /* NBIH_BIST_COUNTERS_OVF */ "", 61741 /* NBIH_BIST_ENABLE_ILKN_PORT */ "", 61742 /* NBIH_BIST_ERROR_GENERATOR */ "", 61743 /* NBIH_BIST_EVENTS_GENERATOR */ "", 61744 /* NBIH_BIST_EVENTS_STATUS */ "", 61745 /* NBIH_BIST_FLOW_FIRST_DESCRIPTOR */ "", 61746 /* NBIH_BIST_FLOW_SECOND_DESCRIPTOR */ "", 61747 /* NBIH_BIST_GENERAL_CONFIGURATION */ "", 61748 /* NBIH_BIST_RX_COUNTERS_1 */ "", 61749 /* NBIH_BIST_RX_COUNTERS_2 */ "", 61750 /* NBIH_BIST_RX_COUNTERS_3 */ "", 61751 /* NBIH_BIST_RX_FLOW_CNT */ "", 61752 /* NBIH_BIST_RX_OK_PKT_CNT */ "", 61753 /* NBIH_BIST_RX_SHAPER */ "", 61754 /* NBIH_BIST_SEED */ "", 61755 /* NBIH_BIST_STATUS */ "", 61756 /* NBIH_BIST_TX_ADDITIONAL_COUNTER */ "", 61757 /* NBIH_BIST_TX_PKT_CNT */ "", 61758 /* NBIH_BIST_TX_PKT_TH */ "", 61759 /* NBIH_ECC_1B_ERR_CNT */ "", 61760 /* NBIH_ECC_2B_ERR_CNT */ "", 61761 /* NBIH_ECC_ERR_1B_INITIATE */ "", 61762 /* NBIH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 61763 /* NBIH_ECC_ERR_2B_INITIATE */ "", 61764 /* NBIH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 61765 /* NBIH_ECC_INTERRUPT_REGISTER */ "", 61766 /* NBIH_ECC_INTERRUPT_REGISTER_MASK */ "", 61767 /* NBIH_ECC_INTERRUPT_REGISTER_TEST */ "", 61768 /* NBIH_EGQ_CORE_FOR_NIF_QMLF */ "", 61769 /* NBIH_EGQ_PORT_FOR_HRF */ "", 61770 /* NBIH_EGQ_PORT_FOR_NIF_PORT */ "", 61771 /* NBIH_ELK_CFG */ "", 61772 /* NBIH_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 61773 /* NBIH_ENABLE_INTERLAKEN */ "", 61774 /* NBIH_ENABLE_INTERLAKEN_HRF */ "", 61775 /* NBIH_ERROR_INITIATION_DATA */ "", 61776 /* NBIH_ETH_TX_GEN_LLFC_CNT */ "", 61777 /* NBIH_ETH_TX_LLFC_STOP_TX_CNT */ "", 61778 /* NBIH_FC_BIST */ "", 61779 /* NBIH_FC_CHOOSE_PORT_FOR_ETH_TX */ "", 61780 /* NBIH_FC_CHOOSE_PORT_FOR_PFC */ "", 61781 /* NBIH_FC_CHOOSE_PORT_FOR_QSGMII_TX */ "", 61782 /* NBIH_FC_GEN_SAFC_REFRESH_TIMER */ "", 61783 /* NBIH_FC_ILKN */ "", 61784 /* NBIH_FC_ILKN_RX_CHFC_CAL_LEN */ "", 61785 /* NBIH_FC_ILKN_RX_CHFC_FORCE */ "", 61786 /* NBIH_FC_ILKN_RX_CHFC_TO_CFC_MASK */ "", 61787 /* NBIH_FC_ILKN_RX_IB_CHFC_FROM_CFC_RAW */ "", 61788 /* NBIH_FC_ILKN_RX_IB_CHFC_FROM_PORT_RAW */ "", 61789 /* NBIH_FC_ILKN_RX_IB_CHFC_FROM_PORT_ROC */ "", 61790 /* NBIH_FC_ILKN_TX_GEN_CHFC_FROM_CFC_MASK */ "", 61791 /* NBIH_FC_ILKN_TX_GEN_IB_CHFC_FORCE */ "", 61792 /* NBIH_FC_ILKN_TX_GEN_IB_CHFC_ROC */ "", 61793 /* NBIH_FC_LLFC_STOP_TX_FORCE */ "", 61794 /* NBIH_FC_LLFC_STOP_TX_FROM_CFC_MASK */ "", 61795 /* NBIH_FC_MASK_FC_WHEN_LINK_FAIL */ "", 61796 /* NBIH_FC_PFC_CFG */ "", 61797 /* NBIH_FC_PFC_DEBUG_INDICATIONS */ "", 61798 /* NBIH_FC_PFC_QMLF_MASK */ "", 61799 /* NBIH_FC_PFC_RX_BITMAP_TYPE_A */ "", 61800 /* NBIH_FC_PFC_RX_BITMAP_TYPE_B */ "", 61801 /* NBIH_FC_PFC_RX_BITMAP_TYPE_PER_PORT */ "", 61802 /* NBIH_FC_PFC_TX_BITMAP_TYPE_A */ "", 61803 /* NBIH_FC_PFC_TX_BITMAP_TYPE_B */ "", 61804 /* NBIH_FC_PFC_TX_BITMAP_TYPE_C */ "", 61805 /* NBIH_FC_PFC_TX_BITMAP_TYPE_D */ "", 61806 /* NBIH_FC_PFC_TX_BITMAP_TYPE_PER_PORT */ "", 61807 /* NBIH_FC_RESET */ "", 61808 /* NBIH_FC_RTM_CONFIG */ "", 61809 /* NBIH_FC_RTM_TIMER */ "", 61810 /* NBIH_FC_RX_GEN_LLFC_FROM_QMLF */ "", 61811 /* NBIH_FC_RX_GEN_PFC_FROM_QMLF */ "", 61812 /* NBIH_FC_RX_LLFC_STOP_TX_FROM_MUBITS */ "", 61813 /* NBIH_FC_RX_MUBITS_TO_CFC */ "", 61814 /* NBIH_FC_TX_GEN_LLFC_FORCE */ "", 61815 /* NBIH_FC_TX_GEN_LLFC_FROM_CFC */ "", 61816 /* NBIH_FC_TX_GEN_LLFC_FROM_CFC_MASK */ "", 61817 /* NBIH_FC_TX_GEN_LLFC_FROM_CFC_OCB_MASK */ "", 61818 /* NBIH_FC_TX_GEN_LLFC_FROM_NPM_MASK */ "", 61819 /* NBIH_FC_TX_GEN_LLFC_FROM_QMLF_MASK */ "", 61820 /* NBIH_FC_TX_GEN_LLFC_TO_PM */ "", 61821 /* NBIH_FC_TX_GEN_PFC_FORCE */ "", 61822 /* NBIH_FC_TX_LLFC_STOP_TX_FROM_CFC */ "", 61823 /* NBIH_FC_TX_LLFC_STOP_TX_TO_PM */ "", 61824 /* NBIH_FC_TX_LLFC_STOP_TX_TO_PM_QSGMII_PORTS */ "", 61825 /* NBIH_FC_TX_LOW_PASS_FILTER */ "", 61826 /* NBIH_FC_TX_MUBITS_FROM_CFC */ "", 61827 /* NBIH_FIFO_WRITE_POINTER_QMLF_SELECT */ "", 61828 /* NBIH_FIFO_WRITE_POINTER_RESULT */ "", 61829 /* NBIH_GLOBAL_GENERAL_CFG_2 */ "", 61830 /* NBIH_GLOBAL_GENERAL_CFG_4 */ "", 61831 /* NBIH_GLOBAL_MEM_OPTIONS */ "", 61832 /* NBIH_GTIMER_CONFIGURATION */ "", 61833 /* NBIH_GTIMER_TRIGGER */ "", 61834 /* NBIH_HRF_RESET */ "", 61835 /* NBIH_HRF_RX_CONFIG_HRF */ "", 61836 /* NBIH_HRF_RX_CONTROLLER_LEVEL */ "", 61837 /* NBIH_HRF_RX_CONTROLLER_MAX_OCCUPANCY */ "", 61838 /* NBIH_HRF_RX_MEM_CONFIG */ "", 61839 /* NBIH_HRF_RX_PRD_THRESHOLDS_CONFIG_0 */ "", 61840 /* NBIH_HRF_RX_PRD_THRESHOLDS_CONFIG_1 */ "", 61841 /* NBIH_HRF_RX_PRD_THRESHOLDS_CONFIG_2 */ "", 61842 /* NBIH_HRF_RX_USE_EXTENDED_MEM_HRF */ "", 61843 /* NBIH_HRF_TX_CONFIG_HRF */ "", 61844 /* NBIH_HRF_TX_CONTROLLER_LEVEL */ "", 61845 /* NBIH_HRF_TX_CONTROLLER_MAX_OCCUPANCY */ "", 61846 /* NBIH_HRF_TX_EGRESS_CREDITS_DEBUG */ "", 61847 /* NBIH_HRF_TX_MEM_CONFIG */ "", 61848 /* NBIH_ILKN_0_PARSER_HARD_CONTROL */ "", 61849 /* NBIH_ILKN_0_PARSER_HARD_CONTROL_PLANE */ "", 61850 /* NBIH_ILKN_0_PARSER_HARD_ETHER_TYPE */ "", 61851 /* NBIH_ILKN_0_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 61852 /* NBIH_ILKN_0_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 61853 /* NBIH_ILKN_0_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 61854 /* NBIH_ILKN_0_PARSER_HARD_PORT_ETH_TPID */ "", 61855 /* NBIH_ILKN_0_PARSER_HARD_PORT_PROPERTIES */ "", 61856 /* NBIH_ILKN_0_PARSER_HARD_PORT_TYPE */ "", 61857 /* NBIH_ILKN_0_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 61858 /* NBIH_ILKN_0_PARSER_SOFT_KEY_CONSTRUCTION */ "", 61859 /* NBIH_ILKN_0_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 61860 /* NBIH_ILKN_0_PARSER_SOFT_TCAM_0_TO_7 */ "", 61861 /* NBIH_ILKN_0_PARSER_SOFT_TCAM_16_TO_23 */ "", 61862 /* NBIH_ILKN_0_PARSER_SOFT_TCAM_24_TO_31 */ "", 61863 /* NBIH_ILKN_0_PARSER_SOFT_TCAM_8_TO_15 */ "", 61864 /* NBIH_ILKN_1_PARSER_HARD_CONTROL */ "", 61865 /* NBIH_ILKN_1_PARSER_HARD_CONTROL_PLANE */ "", 61866 /* NBIH_ILKN_1_PARSER_HARD_ETHER_TYPE */ "", 61867 /* NBIH_ILKN_1_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 61868 /* NBIH_ILKN_1_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 61869 /* NBIH_ILKN_1_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 61870 /* NBIH_ILKN_1_PARSER_HARD_PORT_ETH_TPID */ "", 61871 /* NBIH_ILKN_1_PARSER_HARD_PORT_PROPERTIES */ "", 61872 /* NBIH_ILKN_1_PARSER_HARD_PORT_TYPE */ "", 61873 /* NBIH_ILKN_1_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 61874 /* NBIH_ILKN_1_PARSER_SOFT_KEY_CONSTRUCTION */ "", 61875 /* NBIH_ILKN_1_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 61876 /* NBIH_ILKN_1_PARSER_SOFT_TCAM_0_TO_7 */ "", 61877 /* NBIH_ILKN_1_PARSER_SOFT_TCAM_16_TO_23 */ "", 61878 /* NBIH_ILKN_1_PARSER_SOFT_TCAM_24_TO_31 */ "", 61879 /* NBIH_ILKN_1_PARSER_SOFT_TCAM_8_TO_15 */ "", 61880 /* NBIH_ILKN_CHANNEL_IS_TDM_PORT */ "", 61881 /* NBIH_ILKN_CHANNEL_IS_TDM_PORT_0 */ "", 61882 /* NBIH_ILKN_CHANNEL_IS_TDM_PORT_2 */ "", 61883 /* NBIH_ILKN_FC_OOB_CONF */ "", 61884 /* NBIH_ILKN_MULTIPLE_USE_BITS */ "", 61885 /* NBIH_ILKN_RX_LLFC_FROM_RX_CNT */ "", 61886 /* NBIH_ILKN_RX_TDM_AND_DATA_TRAFFIC_ON_SAME_HRF */ "", 61887 /* NBIH_ILKN_TX_GEN_LLFC_CNT */ "", 61888 /* NBIH_ILKN_TX_LLFC_STOP_TX_CNT */ "", 61889 /* NBIH_ILKN_TX_RETRANSMIT_CONFIG_HRF */ "", 61890 /* NBIH_INDIRECT_COMMAND */ "", 61891 /* NBIH_INDIRECT_COMMAND_ADDRESS */ "", 61892 /* NBIH_INDIRECT_COMMAND_DATA_INCREMENT */ "", 61893 /* NBIH_INDIRECT_COMMAND_RD_DATA */ "", 61894 /* NBIH_INDIRECT_COMMAND_WIDE_MEM */ "", 61895 /* NBIH_INDIRECT_COMMAND_WR_DATA */ "", 61896 /* NBIH_INDIRECT_FORCE_BUBBLE */ "", 61897 /* NBIH_INTERRUPT_MASK_REGISTER */ "", 61898 /* NBIH_INTERRUPT_REGISTER */ "", 61899 /* NBIH_INTERRUPT_REGISTER_TEST */ "", 61900 /* NBIH_LAST_RECEIVED_CONTROLS */ "", 61901 /* NBIH_LAST_RECEIVED_DATA */ "", 61902 /* NBIH_LAST_RECEIVED_DATA_ON_SOP */ "", 61903 /* NBIH_LAST_SENT_CONTROLS */ "", 61904 /* NBIH_LAST_SENT_DATA */ "", 61905 /* NBIH_LAST_SENT_DATA_ON_SOP */ "", 61906 /* NBIH_LINK_ACTIVE */ "", 61907 /* NBIH_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER */ "", 61908 /* NBIH_LINK_STATUS_CHANGE_INTERRUPT_REGISTER */ "", 61909 /* NBIH_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST */ "", 61910 /* NBIH_MEM_PTR_ASYNC_FIFO_ALWAYS_WRITE */ "", 61911 /* NBIH_MEM_PTR_ASYNC_FIFO_CLK_RATIO */ "", 61912 /* NBIH_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER */ "", 61913 /* NBIH_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER */ "", 61914 /* NBIH_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST */ "", 61915 /* NBIH_NIF_PMH_BIS_NUM_OF_SAMPLES_CFG */ "", 61916 /* NBIH_NIF_PMH_CLK_BYPASS_MUX */ "", 61917 /* NBIH_NIF_PMH_CLK_DATA_PATH_MUX */ "", 61918 /* NBIH_NIF_PMH_DATA_BYPASS_MUX */ "", 61919 /* NBIH_NIF_PMH_FGS_CFG */ "", 61920 /* NBIH_NIF_PMH_FGS_DEBUG */ "", 61921 /* NBIH_NIF_PMH_FGS_RSTN */ "", 61922 /* NBIH_NIF_PMH_FGS_SRDS_SIG_DET_CFG */ "", 61923 /* NBIH_NIF_PMH_RESOLVED_SPEED */ "", 61924 /* NBIH_NIF_PM_CFG */ "", 61925 /* NBIH_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION */ "", 61926 /* NBIH_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION */ "", 61927 /* NBIH_NIF_PM_EXTERNAL_LPI_INDICATION */ "", 61928 /* NBIH_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION */ "", 61929 /* NBIH_NIF_PM_ILKN_RX_RSTN */ "", 61930 /* NBIH_NIF_PM_ILKN_TX_RSTN */ "", 61931 /* NBIH_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS */ "", 61932 /* NBIH_NIF_TSC_LANE_STATUS */ "", 61933 /* NBIH_NUM_DROPPED_BURSTS_COUNTER_RX_HRF */ "", 61934 /* NBIH_PARITY_ERR_CNT */ "", 61935 /* NBIH_PAR_ERR_INITIATE */ "", 61936 /* NBIH_PAR_ERR_MEM_MASK */ "", 61937 /* NBIH_PKT_DROP_COUNTER_RX_HRF */ "", 61938 /* NBIH_PMH_ACCUMULATE_AND_SYNC_CYCLE_NUM */ "", 61939 /* NBIH_PM_EEE_LPI_DETECT */ "", 61940 /* NBIH_PM_STRAP_LED_INTRA_DELAY */ "", 61941 /* NBIH_PM_STRAP_LED_OUTPUT_DELAY */ "", 61942 /* NBIH_PM_TX_PLL_LOCK_STATUS */ "", 61943 /* NBIH_PORTS_INDICATIONS */ "", 61944 /* NBIH_PORT_METER_ADD_CFG_RX */ "", 61945 /* NBIH_PORT_METER_MASK_FOR_LLFC */ "", 61946 /* NBIH_PORT_METER_PORTS_RSTN */ "", 61947 /* NBIH_PORT_METER_RSTN */ "", 61948 /* NBIH_PORT_METER_THRESHOLDS_CFG */ "", 61949 /* NBIH_PRD_CONFIG */ "", 61950 /* NBIH_PRD_CONFIG_HRF_0 */ "", 61951 /* NBIH_PRD_CONFIG_HRF_2 */ "", 61952 /* NBIH_PRD_CONFIG_QMLF */ "", 61953 /* NBIH_PRD_EN */ "", 61954 /* NBIH_PRD_ERR_PKT_DROP_CNT_HRF */ "", 61955 /* NBIH_PRD_ERR_PKT_DROP_CNT_PORT */ "", 61956 /* NBIH_PRD_LAST_PKT_KEY */ "", 61957 /* NBIH_PRD_PKT_DROP_CNT_HRF */ "", 61958 /* NBIH_PRD_PKT_DROP_CNT_PORT */ "", 61959 /* NBIH_QMLF_0_PARSER_HARD_CONTROL */ "", 61960 /* NBIH_QMLF_0_PARSER_HARD_CONTROL_PLANE */ "", 61961 /* NBIH_QMLF_0_PARSER_HARD_ETHER_TYPE */ "", 61962 /* NBIH_QMLF_0_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 61963 /* NBIH_QMLF_0_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 61964 /* NBIH_QMLF_0_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 61965 /* NBIH_QMLF_0_PARSER_HARD_PORT_ETH_TPID */ "", 61966 /* NBIH_QMLF_0_PARSER_HARD_PORT_PROPERTIES */ "", 61967 /* NBIH_QMLF_0_PARSER_HARD_PORT_TYPE */ "", 61968 /* NBIH_QMLF_0_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 61969 /* NBIH_QMLF_0_PARSER_SOFT_KEY_CONSTRUCTION */ "", 61970 /* NBIH_QMLF_0_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 61971 /* NBIH_QMLF_0_PARSER_SOFT_TCAM_0_TO_7 */ "", 61972 /* NBIH_QMLF_0_PARSER_SOFT_TCAM_16_TO_23 */ "", 61973 /* NBIH_QMLF_0_PARSER_SOFT_TCAM_24_TO_31 */ "", 61974 /* NBIH_QMLF_0_PARSER_SOFT_TCAM_8_TO_15 */ "", 61975 /* NBIH_QMLF_1_PARSER_HARD_CONTROL */ "", 61976 /* NBIH_QMLF_1_PARSER_HARD_CONTROL_PLANE */ "", 61977 /* NBIH_QMLF_1_PARSER_HARD_ETHER_TYPE */ "", 61978 /* NBIH_QMLF_1_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 61979 /* NBIH_QMLF_1_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 61980 /* NBIH_QMLF_1_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 61981 /* NBIH_QMLF_1_PARSER_HARD_PORT_ETH_TPID */ "", 61982 /* NBIH_QMLF_1_PARSER_HARD_PORT_PROPERTIES */ "", 61983 /* NBIH_QMLF_1_PARSER_HARD_PORT_TYPE */ "", 61984 /* NBIH_QMLF_1_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 61985 /* NBIH_QMLF_1_PARSER_SOFT_KEY_CONSTRUCTION */ "", 61986 /* NBIH_QMLF_1_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 61987 /* NBIH_QMLF_1_PARSER_SOFT_TCAM_0_TO_7 */ "", 61988 /* NBIH_QMLF_1_PARSER_SOFT_TCAM_16_TO_23 */ "", 61989 /* NBIH_QMLF_1_PARSER_SOFT_TCAM_24_TO_31 */ "", 61990 /* NBIH_QMLF_1_PARSER_SOFT_TCAM_8_TO_15 */ "", 61991 /* NBIH_QMLF_2_PARSER_HARD_CONTROL */ "", 61992 /* NBIH_QMLF_2_PARSER_HARD_CONTROL_PLANE */ "", 61993 /* NBIH_QMLF_2_PARSER_HARD_ETHER_TYPE */ "", 61994 /* NBIH_QMLF_2_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 61995 /* NBIH_QMLF_2_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 61996 /* NBIH_QMLF_2_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 61997 /* NBIH_QMLF_2_PARSER_HARD_PORT_ETH_TPID */ "", 61998 /* NBIH_QMLF_2_PARSER_HARD_PORT_PROPERTIES */ "", 61999 /* NBIH_QMLF_2_PARSER_HARD_PORT_TYPE */ "", 62000 /* NBIH_QMLF_2_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62001 /* NBIH_QMLF_2_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62002 /* NBIH_QMLF_2_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62003 /* NBIH_QMLF_2_PARSER_SOFT_TCAM_0_TO_7 */ "", 62004 /* NBIH_QMLF_2_PARSER_SOFT_TCAM_16_TO_23 */ "", 62005 /* NBIH_QMLF_2_PARSER_SOFT_TCAM_24_TO_31 */ "", 62006 /* NBIH_QMLF_2_PARSER_SOFT_TCAM_8_TO_15 */ "", 62007 /* NBIH_QMLF_3_PARSER_HARD_CONTROL */ "", 62008 /* NBIH_QMLF_3_PARSER_HARD_CONTROL_PLANE */ "", 62009 /* NBIH_QMLF_3_PARSER_HARD_ETHER_TYPE */ "", 62010 /* NBIH_QMLF_3_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62011 /* NBIH_QMLF_3_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62012 /* NBIH_QMLF_3_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62013 /* NBIH_QMLF_3_PARSER_HARD_PORT_ETH_TPID */ "", 62014 /* NBIH_QMLF_3_PARSER_HARD_PORT_PROPERTIES */ "", 62015 /* NBIH_QMLF_3_PARSER_HARD_PORT_TYPE */ "", 62016 /* NBIH_QMLF_3_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62017 /* NBIH_QMLF_3_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62018 /* NBIH_QMLF_3_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62019 /* NBIH_QMLF_3_PARSER_SOFT_TCAM_0_TO_7 */ "", 62020 /* NBIH_QMLF_3_PARSER_SOFT_TCAM_16_TO_23 */ "", 62021 /* NBIH_QMLF_3_PARSER_SOFT_TCAM_24_TO_31 */ "", 62022 /* NBIH_QMLF_3_PARSER_SOFT_TCAM_8_TO_15 */ "", 62023 /* NBIH_QMLF_4_PARSER_HARD_CONTROL */ "", 62024 /* NBIH_QMLF_4_PARSER_HARD_CONTROL_PLANE */ "", 62025 /* NBIH_QMLF_4_PARSER_HARD_ETHER_TYPE */ "", 62026 /* NBIH_QMLF_4_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62027 /* NBIH_QMLF_4_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62028 /* NBIH_QMLF_4_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62029 /* NBIH_QMLF_4_PARSER_HARD_PORT_ETH_TPID */ "", 62030 /* NBIH_QMLF_4_PARSER_HARD_PORT_PROPERTIES */ "", 62031 /* NBIH_QMLF_4_PARSER_HARD_PORT_TYPE */ "", 62032 /* NBIH_QMLF_4_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62033 /* NBIH_QMLF_4_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62034 /* NBIH_QMLF_4_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62035 /* NBIH_QMLF_4_PARSER_SOFT_TCAM_0_TO_7 */ "", 62036 /* NBIH_QMLF_4_PARSER_SOFT_TCAM_16_TO_23 */ "", 62037 /* NBIH_QMLF_4_PARSER_SOFT_TCAM_24_TO_31 */ "", 62038 /* NBIH_QMLF_4_PARSER_SOFT_TCAM_8_TO_15 */ "", 62039 /* NBIH_QMLF_5_PARSER_HARD_CONTROL */ "", 62040 /* NBIH_QMLF_5_PARSER_HARD_CONTROL_PLANE */ "", 62041 /* NBIH_QMLF_5_PARSER_HARD_ETHER_TYPE */ "", 62042 /* NBIH_QMLF_5_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62043 /* NBIH_QMLF_5_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62044 /* NBIH_QMLF_5_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62045 /* NBIH_QMLF_5_PARSER_HARD_PORT_ETH_TPID */ "", 62046 /* NBIH_QMLF_5_PARSER_HARD_PORT_PROPERTIES */ "", 62047 /* NBIH_QMLF_5_PARSER_HARD_PORT_TYPE */ "", 62048 /* NBIH_QMLF_5_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62049 /* NBIH_QMLF_5_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62050 /* NBIH_QMLF_5_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62051 /* NBIH_QMLF_5_PARSER_SOFT_TCAM_0_TO_7 */ "", 62052 /* NBIH_QMLF_5_PARSER_SOFT_TCAM_16_TO_23 */ "", 62053 /* NBIH_QMLF_5_PARSER_SOFT_TCAM_24_TO_31 */ "", 62054 /* NBIH_QMLF_5_PARSER_SOFT_TCAM_8_TO_15 */ "", 62055 /* NBIH_QSGMII_TX_GEN_LLFC_CNT */ "", 62056 /* NBIH_QSGMII_TX_LLFC_STOP_TX_CNT */ "", 62057 /* NBIH_RECEIVED_RETRANSMIT_DEBUG */ "", 62058 /* NBIH_REG_0C06 */ "", 62059 /* NBIH_RESERVED_0 */ "", 62060 /* NBIH_RESERVED_MIRROR_ADDR */ "", 62061 /* NBIH_RESERVED_MTCD */ "", 62062 /* NBIH_RESERVED_MTCP */ "", 62063 /* NBIH_RESERVED_PCMI_0 */ "", 62064 /* NBIH_RESERVED_PCMI_1 */ "", 62065 /* NBIH_RESERVED_PCMI_2 */ "", 62066 /* NBIH_RESERVED_PCMI_3 */ "", 62067 /* NBIH_RESERVED_PCMI_4 */ "", 62068 /* NBIH_RESERVED_PCMI_0_S */ "", 62069 /* NBIH_RESERVED_PCMI_0_T */ "", 62070 /* NBIH_RESERVED_PCMI_1_S */ "", 62071 /* NBIH_RESERVED_PCMI_1_T */ "", 62072 /* NBIH_RESERVED_PCMI_2_S */ "", 62073 /* NBIH_RESERVED_PCMI_2_T */ "", 62074 /* NBIH_RESERVED_PCMI_3_S */ "", 62075 /* NBIH_RESERVED_PCMI_3_T */ "", 62076 /* NBIH_RESERVED_PCMI_4_S */ "", 62077 /* NBIH_RESERVED_PCMI_4_T */ "", 62078 /* NBIH_RESERVED_SPARE_0 */ "", 62079 /* NBIH_RESERVED_SPARE_1 */ "", 62080 /* NBIH_RESERVED_SPARE_2 */ "", 62081 /* NBIH_RESERVED_SPARE_3 */ "", 62082 /* NBIH_RES_CAL_0_STATUS */ "", 62083 /* NBIH_RES_CAL_1_STATUS */ "", 62084 /* NBIH_RX_CORE_0_BYTE_COUNTER */ "", 62085 /* NBIH_RX_CORE_0_PKT_COUNTER */ "", 62086 /* NBIH_RX_CORE_1_BYTE_COUNTER */ "", 62087 /* NBIH_RX_CORE_1_PKT_COUNTER */ "", 62088 /* NBIH_RX_ELK_BURSTS_CNT_ELK */ "", 62089 /* NBIH_RX_ELK_BURST_DROP_CNT_ELK */ "", 62090 /* NBIH_RX_ELK_ERR_BURSTS_CNT_ELK */ "", 62091 /* NBIH_RX_ELK_OCTETS_CNT_ELK */ "", 62092 /* NBIH_RX_ELK_STATUS */ "", 62093 /* NBIH_RX_ENABLE_DATAPATH */ "", 62094 /* NBIH_RX_MLF_ERROR_PM */ "", 62095 /* NBIH_RX_MLF_LEVEL_PM */ "", 62096 /* NBIH_RX_MLF_LLFC_THRESHOLDS_CONFIG */ "", 62097 /* NBIH_RX_MLF_MAX_OCCUPANCY */ "", 62098 /* NBIH_RX_MLF_PFC_THRESHOLDS_CONFIG */ "", 62099 /* NBIH_RX_MLF_PRD_THRESHOLDS_CONFIG */ "", 62100 /* NBIH_RX_NUM_TOTAL_DROPPED_EOPS */ "", 62101 /* NBIH_RX_PKT_DROP_COUNTER */ "", 62102 /* NBIH_RX_PKT_FC_DROP_COUNTER */ "", 62103 /* NBIH_RX_PKT_FC_ERR_COUNTER */ "", 62104 /* NBIH_RX_PORTS_SRSTN */ "", 62105 /* NBIH_RX_PORT_OVF */ "", 62106 /* NBIH_RX_PRD_VLAN_ETHERTYPE */ "", 62107 /* NBIH_RX_QMLF_CONFIG */ "", 62108 /* NBIH_RX_REQ_PIPE_0_HIGH_EN */ "", 62109 /* NBIH_RX_REQ_PIPE_0_LOW_EN */ "", 62110 /* NBIH_RX_REQ_PIPE_0_TDM_EN */ "", 62111 /* NBIH_RX_REQ_PIPE_1_HIGH_EN */ "", 62112 /* NBIH_RX_REQ_PIPE_1_LOW_EN */ "", 62113 /* NBIH_RX_REQ_PIPE_1_TDM_EN */ "", 62114 /* NBIH_RX_SCH_CONFIG_FOR_TDM_HRFS */ "", 62115 /* NBIH_RX_SCH_CONFIG_HRF */ "", 62116 /* NBIH_RX_SCH_CONFIG_HRF_4 */ "", 62117 /* NBIH_RX_SCH_CONFIG_HRF_5 */ "", 62118 /* NBIH_RX_SCH_CONFIG_HRF_8 */ "", 62119 /* NBIH_RX_SCH_CONFIG_HRF_9 */ "", 62120 /* NBIH_RX_SCH_DEBUG_CONF */ "", 62121 /* NBIH_RX_SCH_DEBUG_RESULT */ "", 62122 /* NBIH_RX_TDM_BYTE_COUNTER */ "", 62123 /* NBIH_RX_TDM_PKT_COUNTER */ "", 62124 /* NBIH_RX_THRESHOLD_AFTER_OVERFLOW_QMLF */ "", 62125 /* NBIH_RX_TOTAL_BYTE_COUNTER */ "", 62126 /* NBIH_RX_TOTAL_PKT_COUNTER */ "", 62127 /* NBIH_SBUS_BROADCAST_ID */ "", 62128 /* NBIH_SBUS_LAST_IN_CHAIN */ "", 62129 /* NBIH_SIF_CFG */ "", 62130 /* NBIH_STATS_BURSTS_CNT_PORT */ "", 62131 /* NBIH_STATS_OCTETS_CNT_PORT */ "", 62132 /* NBIH_SYNC_ETH_CFG */ "", 62133 /* NBIH_SYNC_ETH_COUNTER */ "", 62134 /* NBIH_SYNC_ETH_SQUELCH_DIS_TH_REG */ "", 62135 /* NBIH_SYNC_ETH_SQUELCH_EN_TH_REG */ "", 62136 /* NBIH_TXI_PIPE_0_NOT_READY */ "", 62137 /* NBIH_TXI_PIPE_1_NOT_READY */ "", 62138 /* NBIH_TXI_TDM_NOT_READY */ "", 62139 /* NBIH_TX_CORE_0_BYTE_COUNTER */ "", 62140 /* NBIH_TX_CORE_0_PKT_COUNTER */ "", 62141 /* NBIH_TX_CORE_1_BYTE_COUNTER */ "", 62142 /* NBIH_TX_CORE_1_PKT_COUNTER */ "", 62143 /* NBIH_TX_EGRESS_CREDITS_DEBUG_PM */ "", 62144 /* NBIH_TX_ELK_BURSTS_CNT_ELK */ "", 62145 /* NBIH_TX_ELK_OCTETS_CNT_ELK */ "", 62146 /* NBIH_TX_ENABLE_DATAPATH */ "", 62147 /* NBIH_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE */ "", 62148 /* NBIH_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE_HRF */ "", 62149 /* NBIH_TX_IGNORED_RETRANS_REQ_CNT_HRF */ "", 62150 /* NBIH_TX_MLF_LEVEL_PM */ "", 62151 /* NBIH_TX_MLF_MAX_OCCUPANCY */ "", 62152 /* NBIH_TX_MLF_NUM_CREDITS_FROM_PM */ "", 62153 /* NBIH_TX_MLF_OVERFLOW_PM */ "", 62154 /* NBIH_TX_NO_DATA_IN_BUFFER */ "", 62155 /* NBIH_TX_PORTS_CONFIG */ "", 62156 /* NBIH_TX_PORTS_SRSTN */ "", 62157 /* NBIH_TX_PORT_OVF */ "", 62158 /* NBIH_TX_QMLF_CONFIG */ "", 62159 /* NBIH_TX_RECEIVED_RETRANS_REQ_CNT_HRF */ "", 62160 /* NBIH_TX_TOTAL_BYTE_COUNTER */ "", 62161 /* NBIH_TX_TOTAL_PKT_COUNTER */ "", 62162 /* NBIH_TX_WRONG_PORT_FROM_EGQ_QMLF */ "", 62163 /* NBIL_ADDITIONAL_RESETS */ "", 62164 /* NBIL_ECC_1B_ERR_CNT */ "", 62165 /* NBIL_ECC_2B_ERR_CNT */ "", 62166 /* NBIL_ECC_ERR_1B_INITIATE */ "", 62167 /* NBIL_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 62168 /* NBIL_ECC_ERR_2B_INITIATE */ "", 62169 /* NBIL_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 62170 /* NBIL_ECC_INTERRUPT_REGISTER */ "", 62171 /* NBIL_ECC_INTERRUPT_REGISTER_MASK */ "", 62172 /* NBIL_ECC_INTERRUPT_REGISTER_TEST */ "", 62173 /* NBIL_ELK_CFG */ "", 62174 /* NBIL_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 62175 /* NBIL_ENABLE_INTERLAKEN */ "", 62176 /* NBIL_ERROR_INITIATION_DATA */ "", 62177 /* NBIL_FIFO_WRITE_POINTER_QMLF_SELECT */ "", 62178 /* NBIL_FIFO_WRITE_POINTER_RESULT */ "", 62179 /* NBIL_GLOBAL_GENERAL_CFG_2 */ "", 62180 /* NBIL_GLOBAL_GENERAL_CFG_4 */ "", 62181 /* NBIL_GLOBAL_MEM_OPTIONS */ "", 62182 /* NBIL_GTIMER_CONFIGURATION */ "", 62183 /* NBIL_GTIMER_TRIGGER */ "", 62184 /* NBIL_HRF_RESET */ "", 62185 /* NBIL_HRF_RX_CONFIG_HRF */ "", 62186 /* NBIL_HRF_RX_CONTROLLER_LEVEL */ "", 62187 /* NBIL_HRF_RX_CONTROLLER_MAX_OCCUPANCY */ "", 62188 /* NBIL_HRF_RX_MEM_CONFIG */ "", 62189 /* NBIL_HRF_RX_PRD_THRESHOLDS_CONFIG */ "", 62190 /* NBIL_HRF_RX_PRD_THRESHOLDS_CONFIG_0 */ "", 62191 /* NBIL_HRF_RX_PRD_THRESHOLDS_CONFIG_1 */ "", 62192 /* NBIL_HRF_RX_USE_EXTENDED_MEM_HRF */ "", 62193 /* NBIL_HRF_TX_CONFIG_HRF */ "", 62194 /* NBIL_HRF_TX_CONTROLLER_LEVEL */ "", 62195 /* NBIL_HRF_TX_CONTROLLER_MAX_OCCUPANCY */ "", 62196 /* NBIL_HRF_TX_EGRESS_CREDITS_DEBUG */ "", 62197 /* NBIL_HRF_TX_MEM_CONFIG */ "", 62198 /* NBIL_ILKN_0_PARSER_HARD_CONTROL */ "", 62199 /* NBIL_ILKN_0_PARSER_HARD_CONTROL_PLANE */ "", 62200 /* NBIL_ILKN_0_PARSER_HARD_ETHER_TYPE */ "", 62201 /* NBIL_ILKN_0_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62202 /* NBIL_ILKN_0_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62203 /* NBIL_ILKN_0_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62204 /* NBIL_ILKN_0_PARSER_HARD_PORT_ETH_TPID */ "", 62205 /* NBIL_ILKN_0_PARSER_HARD_PORT_PROPERTIES */ "", 62206 /* NBIL_ILKN_0_PARSER_HARD_PORT_TYPE */ "", 62207 /* NBIL_ILKN_0_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62208 /* NBIL_ILKN_0_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62209 /* NBIL_ILKN_0_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62210 /* NBIL_ILKN_0_PARSER_SOFT_TCAM_0_TO_7 */ "", 62211 /* NBIL_ILKN_0_PARSER_SOFT_TCAM_16_TO_23 */ "", 62212 /* NBIL_ILKN_0_PARSER_SOFT_TCAM_24_TO_31 */ "", 62213 /* NBIL_ILKN_0_PARSER_SOFT_TCAM_8_TO_15 */ "", 62214 /* NBIL_ILKN_1_PARSER_HARD_CONTROL */ "", 62215 /* NBIL_ILKN_1_PARSER_HARD_CONTROL_PLANE */ "", 62216 /* NBIL_ILKN_1_PARSER_HARD_ETHER_TYPE */ "", 62217 /* NBIL_ILKN_1_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62218 /* NBIL_ILKN_1_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62219 /* NBIL_ILKN_1_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62220 /* NBIL_ILKN_1_PARSER_HARD_PORT_ETH_TPID */ "", 62221 /* NBIL_ILKN_1_PARSER_HARD_PORT_PROPERTIES */ "", 62222 /* NBIL_ILKN_1_PARSER_HARD_PORT_TYPE */ "", 62223 /* NBIL_ILKN_1_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62224 /* NBIL_ILKN_1_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62225 /* NBIL_ILKN_1_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62226 /* NBIL_ILKN_1_PARSER_SOFT_TCAM_0_TO_7 */ "", 62227 /* NBIL_ILKN_1_PARSER_SOFT_TCAM_16_TO_23 */ "", 62228 /* NBIL_ILKN_1_PARSER_SOFT_TCAM_24_TO_31 */ "", 62229 /* NBIL_ILKN_1_PARSER_SOFT_TCAM_8_TO_15 */ "", 62230 /* NBIL_ILKN_CHANNEL_IS_TDM_PORT */ "", 62231 /* NBIL_ILKN_RX_TDM_AND_DATA_TRAFFIC_ON_SAME_HRF */ "", 62232 /* NBIL_ILKN_TX_RETRANSMIT_CONFIG_HRF */ "", 62233 /* NBIL_INDIRECT_COMMAND */ "", 62234 /* NBIL_INDIRECT_COMMAND_ADDRESS */ "", 62235 /* NBIL_INDIRECT_COMMAND_DATA_INCREMENT */ "", 62236 /* NBIL_INDIRECT_COMMAND_RD_DATA */ "", 62237 /* NBIL_INDIRECT_COMMAND_WIDE_MEM */ "", 62238 /* NBIL_INDIRECT_COMMAND_WR_DATA */ "", 62239 /* NBIL_INDIRECT_FORCE_BUBBLE */ "", 62240 /* NBIL_INTERRUPT_MASK_REGISTER */ "", 62241 /* NBIL_INTERRUPT_REGISTER */ "", 62242 /* NBIL_INTERRUPT_REGISTER_TEST */ "", 62243 /* NBIL_LAST_RECEIVED_CONTROLS */ "", 62244 /* NBIL_LAST_RECEIVED_DATA */ "", 62245 /* NBIL_LAST_RECEIVED_DATA_ON_SOP */ "", 62246 /* NBIL_LAST_SENT_CONTROLS */ "", 62247 /* NBIL_LAST_SENT_DATA */ "", 62248 /* NBIL_LAST_SENT_DATA_ON_SOP */ "", 62249 /* NBIL_LINK_ACTIVE */ "", 62250 /* NBIL_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER */ "", 62251 /* NBIL_LINK_STATUS_CHANGE_INTERRUPT_REGISTER */ "", 62252 /* NBIL_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST */ "", 62253 /* NBIL_LINK_STATUS_TO_CMIC_SEL_REG */ "", 62254 /* NBIL_MEM_PTR_ASYNC_FIFO_ALWAYS_WRITE */ "", 62255 /* NBIL_MEM_PTR_ASYNC_FIFO_CLK_RATIO */ "", 62256 /* NBIL_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER */ "", 62257 /* NBIL_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER */ "", 62258 /* NBIL_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST */ "", 62259 /* NBIL_NIF_PMH_RESOLVED_SPEED */ "", 62260 /* NBIL_NIF_PML_BIS_NUM_OF_SAMPLES_CFG */ "", 62261 /* NBIL_NIF_PML_CLK_DATA_PATH_MUX */ "", 62262 /* NBIL_NIF_PML_RESOLVED_SPEED */ "", 62263 /* NBIL_NIF_PM_CFG */ "", 62264 /* NBIL_NIF_PM_CFG_3 */ "", 62265 /* NBIL_NIF_PM_CFG_4 */ "", 62266 /* NBIL_NIF_PM_CFG_5 */ "", 62267 /* NBIL_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION */ "", 62268 /* NBIL_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION */ "", 62269 /* NBIL_NIF_PM_EXTERNAL_LPI_INDICATION */ "", 62270 /* NBIL_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION */ "", 62271 /* NBIL_NIF_PM_ILKN_RX_RSTN */ "", 62272 /* NBIL_NIF_PM_ILKN_TX_RSTN */ "", 62273 /* NBIL_NIF_TSC_LANE_STATUS */ "", 62274 /* NBIL_NUM_DROPPED_BURSTS_COUNTER_RX_HRF */ "", 62275 /* NBIL_PARITY_ERR_CNT */ "", 62276 /* NBIL_PAR_ERR_INITIATE */ "", 62277 /* NBIL_PAR_ERR_MEM_MASK */ "", 62278 /* NBIL_PHY_LED_PMLQ_BYPASS */ "", 62279 /* NBIL_PKT_DROP_COUNTER_RX_HRF */ "", 62280 /* NBIL_PML_ACCUMULATE_AND_SYNC_CYCLE_NUM */ "", 62281 /* NBIL_PM_STRAP_LED_INTRA_DELAY */ "", 62282 /* NBIL_PM_STRAP_LED_OUTPUT_DELAY */ "", 62283 /* NBIL_PM_TX_PLL_LOCK_STATUS */ "", 62284 /* NBIL_PORTS_INDICATIONS */ "", 62285 /* NBIL_PORT_EEE_LPI_DETECT */ "", 62286 /* NBIL_PORT_METER_ADD_CFG_RX */ "", 62287 /* NBIL_PORT_METER_MASK */ "", 62288 /* NBIL_PORT_METER_PORTS_RSTN */ "", 62289 /* NBIL_PORT_METER_RSTN */ "", 62290 /* NBIL_PORT_METER_THRESHOLDS_CFG */ "", 62291 /* NBIL_PRD_CONFIG */ "", 62292 /* NBIL_PRD_CONFIG_HRF_0 */ "", 62293 /* NBIL_PRD_CONFIG_QMLF */ "", 62294 /* NBIL_PRD_EN */ "", 62295 /* NBIL_PRD_ERR_PKT_DROP_CNT_HRF */ "", 62296 /* NBIL_PRD_ERR_PKT_DROP_CNT_HRF_0 */ "", 62297 /* NBIL_PRD_ERR_PKT_DROP_CNT_PORT */ "", 62298 /* NBIL_PRD_LAST_PKT_KEY */ "", 62299 /* NBIL_PRD_PKT_DROP_CNT_HRF */ "", 62300 /* NBIL_PRD_PKT_DROP_CNT_HRF_0 */ "", 62301 /* NBIL_PRD_PKT_DROP_CNT_PORT */ "", 62302 /* NBIL_QMLF_0_PARSER_HARD_CONTROL */ "", 62303 /* NBIL_QMLF_0_PARSER_HARD_CONTROL_PLANE */ "", 62304 /* NBIL_QMLF_0_PARSER_HARD_ETHER_TYPE */ "", 62305 /* NBIL_QMLF_0_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62306 /* NBIL_QMLF_0_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62307 /* NBIL_QMLF_0_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62308 /* NBIL_QMLF_0_PARSER_HARD_PORT_ETH_TPID */ "", 62309 /* NBIL_QMLF_0_PARSER_HARD_PORT_PROPERTIES */ "", 62310 /* NBIL_QMLF_0_PARSER_HARD_PORT_TYPE */ "", 62311 /* NBIL_QMLF_0_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62312 /* NBIL_QMLF_0_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62313 /* NBIL_QMLF_0_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62314 /* NBIL_QMLF_0_PARSER_SOFT_TCAM_0_TO_7 */ "", 62315 /* NBIL_QMLF_0_PARSER_SOFT_TCAM_16_TO_23 */ "", 62316 /* NBIL_QMLF_0_PARSER_SOFT_TCAM_24_TO_31 */ "", 62317 /* NBIL_QMLF_0_PARSER_SOFT_TCAM_8_TO_15 */ "", 62318 /* NBIL_QMLF_1_PARSER_HARD_CONTROL */ "", 62319 /* NBIL_QMLF_1_PARSER_HARD_CONTROL_PLANE */ "", 62320 /* NBIL_QMLF_1_PARSER_HARD_ETHER_TYPE */ "", 62321 /* NBIL_QMLF_1_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62322 /* NBIL_QMLF_1_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62323 /* NBIL_QMLF_1_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62324 /* NBIL_QMLF_1_PARSER_HARD_PORT_ETH_TPID */ "", 62325 /* NBIL_QMLF_1_PARSER_HARD_PORT_PROPERTIES */ "", 62326 /* NBIL_QMLF_1_PARSER_HARD_PORT_TYPE */ "", 62327 /* NBIL_QMLF_1_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62328 /* NBIL_QMLF_1_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62329 /* NBIL_QMLF_1_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62330 /* NBIL_QMLF_1_PARSER_SOFT_TCAM_0_TO_7 */ "", 62331 /* NBIL_QMLF_1_PARSER_SOFT_TCAM_16_TO_23 */ "", 62332 /* NBIL_QMLF_1_PARSER_SOFT_TCAM_24_TO_31 */ "", 62333 /* NBIL_QMLF_1_PARSER_SOFT_TCAM_8_TO_15 */ "", 62334 /* NBIL_QMLF_2_PARSER_HARD_CONTROL */ "", 62335 /* NBIL_QMLF_2_PARSER_HARD_CONTROL_PLANE */ "", 62336 /* NBIL_QMLF_2_PARSER_HARD_ETHER_TYPE */ "", 62337 /* NBIL_QMLF_2_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62338 /* NBIL_QMLF_2_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62339 /* NBIL_QMLF_2_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62340 /* NBIL_QMLF_2_PARSER_HARD_PORT_ETH_TPID */ "", 62341 /* NBIL_QMLF_2_PARSER_HARD_PORT_PROPERTIES */ "", 62342 /* NBIL_QMLF_2_PARSER_HARD_PORT_TYPE */ "", 62343 /* NBIL_QMLF_2_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62344 /* NBIL_QMLF_2_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62345 /* NBIL_QMLF_2_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62346 /* NBIL_QMLF_2_PARSER_SOFT_TCAM_0_TO_7 */ "", 62347 /* NBIL_QMLF_2_PARSER_SOFT_TCAM_16_TO_23 */ "", 62348 /* NBIL_QMLF_2_PARSER_SOFT_TCAM_24_TO_31 */ "", 62349 /* NBIL_QMLF_2_PARSER_SOFT_TCAM_8_TO_15 */ "", 62350 /* NBIL_QMLF_3_PARSER_HARD_CONTROL */ "", 62351 /* NBIL_QMLF_3_PARSER_HARD_CONTROL_PLANE */ "", 62352 /* NBIL_QMLF_3_PARSER_HARD_ETHER_TYPE */ "", 62353 /* NBIL_QMLF_3_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62354 /* NBIL_QMLF_3_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62355 /* NBIL_QMLF_3_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62356 /* NBIL_QMLF_3_PARSER_HARD_PORT_ETH_TPID */ "", 62357 /* NBIL_QMLF_3_PARSER_HARD_PORT_PROPERTIES */ "", 62358 /* NBIL_QMLF_3_PARSER_HARD_PORT_TYPE */ "", 62359 /* NBIL_QMLF_3_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62360 /* NBIL_QMLF_3_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62361 /* NBIL_QMLF_3_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62362 /* NBIL_QMLF_3_PARSER_SOFT_TCAM_0_TO_7 */ "", 62363 /* NBIL_QMLF_3_PARSER_SOFT_TCAM_16_TO_23 */ "", 62364 /* NBIL_QMLF_3_PARSER_SOFT_TCAM_24_TO_31 */ "", 62365 /* NBIL_QMLF_3_PARSER_SOFT_TCAM_8_TO_15 */ "", 62366 /* NBIL_QMLF_4_PARSER_HARD_CONTROL */ "", 62367 /* NBIL_QMLF_4_PARSER_HARD_CONTROL_PLANE */ "", 62368 /* NBIL_QMLF_4_PARSER_HARD_ETHER_TYPE */ "", 62369 /* NBIL_QMLF_4_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62370 /* NBIL_QMLF_4_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62371 /* NBIL_QMLF_4_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62372 /* NBIL_QMLF_4_PARSER_HARD_PORT_ETH_TPID */ "", 62373 /* NBIL_QMLF_4_PARSER_HARD_PORT_PROPERTIES */ "", 62374 /* NBIL_QMLF_4_PARSER_HARD_PORT_TYPE */ "", 62375 /* NBIL_QMLF_4_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62376 /* NBIL_QMLF_4_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62377 /* NBIL_QMLF_4_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62378 /* NBIL_QMLF_4_PARSER_SOFT_TCAM_0_TO_7 */ "", 62379 /* NBIL_QMLF_4_PARSER_SOFT_TCAM_16_TO_23 */ "", 62380 /* NBIL_QMLF_4_PARSER_SOFT_TCAM_24_TO_31 */ "", 62381 /* NBIL_QMLF_4_PARSER_SOFT_TCAM_8_TO_15 */ "", 62382 /* NBIL_QMLF_5_PARSER_HARD_CONTROL */ "", 62383 /* NBIL_QMLF_5_PARSER_HARD_CONTROL_PLANE */ "", 62384 /* NBIL_QMLF_5_PARSER_HARD_ETHER_TYPE */ "", 62385 /* NBIL_QMLF_5_PARSER_HARD_ETH_PCP_DEI_TO_PRIORITY_TABLE */ "", 62386 /* NBIL_QMLF_5_PARSER_HARD_IP_DSCP_TO_PRIORITY_TABLE */ "", 62387 /* NBIL_QMLF_5_PARSER_HARD_MPLS_EXP_TO_PRIORITY_TABLE */ "", 62388 /* NBIL_QMLF_5_PARSER_HARD_PORT_ETH_TPID */ "", 62389 /* NBIL_QMLF_5_PARSER_HARD_PORT_PROPERTIES */ "", 62390 /* NBIL_QMLF_5_PARSER_HARD_PORT_TYPE */ "", 62391 /* NBIL_QMLF_5_PARSER_HARD_TM_TC_DP_TO_PRIORITY_TABLE */ "", 62392 /* NBIL_QMLF_5_PARSER_SOFT_KEY_CONSTRUCTION */ "", 62393 /* NBIL_QMLF_5_PARSER_SOFT_PORT_SOFT_STAGE_ENABLE */ "", 62394 /* NBIL_QMLF_5_PARSER_SOFT_TCAM_0_TO_7 */ "", 62395 /* NBIL_QMLF_5_PARSER_SOFT_TCAM_16_TO_23 */ "", 62396 /* NBIL_QMLF_5_PARSER_SOFT_TCAM_24_TO_31 */ "", 62397 /* NBIL_QMLF_5_PARSER_SOFT_TCAM_8_TO_15 */ "", 62398 /* NBIL_RECEIVED_RETRANSMIT_DEBUG */ "", 62399 /* NBIL_REG_0A06 */ "", 62400 /* NBIL_REG_0A09_3 */ "", 62401 /* NBIL_REG_0A09_4 */ "", 62402 /* NBIL_REG_0A09_5 */ "", 62403 /* NBIL_RESERVED_0 */ "", 62404 /* NBIL_RESERVED_MIRROR_ADDR */ "", 62405 /* NBIL_RESERVED_MTCD */ "", 62406 /* NBIL_RESERVED_MTCP */ "", 62407 /* NBIL_RESERVED_PCMI_0 */ "", 62408 /* NBIL_RESERVED_PCMI_1 */ "", 62409 /* NBIL_RESERVED_PCMI_2 */ "", 62410 /* NBIL_RESERVED_PCMI_3 */ "", 62411 /* NBIL_RESERVED_PCMI_4 */ "", 62412 /* NBIL_RESERVED_PCMI_0_S */ "", 62413 /* NBIL_RESERVED_PCMI_0_T */ "", 62414 /* NBIL_RESERVED_PCMI_1_S */ "", 62415 /* NBIL_RESERVED_PCMI_1_T */ "", 62416 /* NBIL_RESERVED_PCMI_2_S */ "", 62417 /* NBIL_RESERVED_PCMI_2_T */ "", 62418 /* NBIL_RESERVED_PCMI_3_S */ "", 62419 /* NBIL_RESERVED_PCMI_3_T */ "", 62420 /* NBIL_RESERVED_PCMI_4_S */ "", 62421 /* NBIL_RESERVED_PCMI_4_T */ "", 62422 /* NBIL_RESERVED_SPARE_0 */ "", 62423 /* NBIL_RESERVED_SPARE_1 */ "", 62424 /* NBIL_RESERVED_SPARE_2 */ "", 62425 /* NBIL_RESERVED_SPARE_3 */ "", 62426 /* NBIL_RX_ELK_BURSTS_CNT */ "", 62427 /* NBIL_RX_ELK_BURST_DROP_CNT */ "", 62428 /* NBIL_RX_ELK_ERR_BURSTS_CNT */ "", 62429 /* NBIL_RX_ELK_OCTETS_CNT */ "", 62430 /* NBIL_RX_ELK_STATUS */ "", 62431 /* NBIL_RX_ENABLE_DATAPATH */ "", 62432 /* NBIL_RX_MLF_ERROR_PM */ "", 62433 /* NBIL_RX_MLF_ERROR_PM_3 */ "", 62434 /* NBIL_RX_MLF_ERROR_PM_4 */ "", 62435 /* NBIL_RX_MLF_ERROR_PM_5 */ "", 62436 /* NBIL_RX_MLF_LEVEL_PM */ "", 62437 /* NBIL_RX_MLF_LEVEL_PM_3 */ "", 62438 /* NBIL_RX_MLF_LEVEL_PM_4 */ "", 62439 /* NBIL_RX_MLF_LEVEL_PM_5 */ "", 62440 /* NBIL_RX_MLF_LLFC_THRESHOLDS_CONFIG */ "", 62441 /* NBIL_RX_MLF_MAX_OCCUPANCY */ "", 62442 /* NBIL_RX_MLF_PFC_THRESHOLDS_CONFIG */ "", 62443 /* NBIL_RX_MLF_PRD_THRESHOLDS_CONFIG */ "", 62444 /* NBIL_RX_NUM_TOTAL_DROPPED_EOPS */ "", 62445 /* NBIL_RX_PKT_DROP_COUNTER */ "", 62446 /* NBIL_RX_PKT_FC_DROP_COUNTER */ "", 62447 /* NBIL_RX_PKT_FC_ERR_COUNTER */ "", 62448 /* NBIL_RX_PORTS_SRSTN */ "", 62449 /* NBIL_RX_PORT_OVF */ "", 62450 /* NBIL_RX_PRD_PKT_DROP_CNT */ "", 62451 /* NBIL_RX_PRD_VLAN_ETHERTYPE */ "", 62452 /* NBIL_RX_QMLF_CONFIG */ "", 62453 /* NBIL_SBUS_BROADCAST_ID */ "", 62454 /* NBIL_SBUS_LAST_IN_CHAIN */ "", 62455 /* NBIL_SIF_CFG */ "", 62456 /* NBIL_STATS_BURSTS_CNT_PORT */ "", 62457 /* NBIL_STATS_OCTETS_CNT_PORT */ "", 62458 /* NBIL_TX_EGRESS_CREDITS_DEBUG_PM */ "", 62459 /* NBIL_TX_EGRESS_CREDITS_DEBUG_PM_3 */ "", 62460 /* NBIL_TX_EGRESS_CREDITS_DEBUG_PM_4 */ "", 62461 /* NBIL_TX_EGRESS_CREDITS_DEBUG_PM_5 */ "", 62462 /* NBIL_TX_ELK_BURSTS_CNT */ "", 62463 /* NBIL_TX_ELK_OCTETS_CNT */ "", 62464 /* NBIL_TX_ENABLE_DATAPATH */ "", 62465 /* NBIL_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE */ "", 62466 /* NBIL_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE_3 */ "", 62467 /* NBIL_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE_4 */ "", 62468 /* NBIL_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE_5 */ "", 62469 /* NBIL_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE_HRF */ "", 62470 /* NBIL_TX_IGNORED_RETRANS_REQ_CNT_HRF */ "", 62471 /* NBIL_TX_MLF_LEVEL_PM */ "", 62472 /* NBIL_TX_MLF_LEVEL_PM_3 */ "", 62473 /* NBIL_TX_MLF_LEVEL_PM_4 */ "", 62474 /* NBIL_TX_MLF_LEVEL_PM_5 */ "", 62475 /* NBIL_TX_MLF_MAX_OCCUPANCY */ "", 62476 /* NBIL_TX_MLF_NUM_CREDITS_FROM_PM */ "", 62477 /* NBIL_TX_MLF_NUM_CREDITS_FROM_PM_3 */ "", 62478 /* NBIL_TX_MLF_NUM_CREDITS_FROM_PM_4 */ "", 62479 /* NBIL_TX_MLF_NUM_CREDITS_FROM_PM_5 */ "", 62480 /* NBIL_TX_MLF_OVERFLOW_PM */ "", 62481 /* NBIL_TX_MLF_OVERFLOW_PM_3 */ "", 62482 /* NBIL_TX_MLF_OVERFLOW_PM_4 */ "", 62483 /* NBIL_TX_MLF_OVERFLOW_PM_5 */ "", 62484 /* NBIL_TX_NO_DATA_IN_BUFFER */ "", 62485 /* NBIL_TX_NO_DATA_IN_BUFFER_3 */ "", 62486 /* NBIL_TX_NO_DATA_IN_BUFFER_4 */ "", 62487 /* NBIL_TX_NO_DATA_IN_BUFFER_5 */ "", 62488 /* NBIL_TX_PORTS_CONFIG */ "", 62489 /* NBIL_TX_PORTS_SRSTN */ "", 62490 /* NBIL_TX_PORT_OVF */ "", 62491 /* NBIL_TX_QMLF_CONFIG */ "", 62492 /* NBIL_TX_RECEIVED_RETRANS_REQ_CNT_HRF */ "", 62493 /* NBIL_TX_WRONG_PORT_FROM_EGQ_QMLF */ "", 62494 /* NBI_BIST_CONTEXTS_MASK */ "", 62495 /* NBI_BIST_ERROR_GENERATOR */ "", 62496 /* NBI_BIST_EVENTS_GENERATOR */ "", 62497 /* NBI_BIST_EVENTS_STATUS */ "", 62498 /* NBI_BIST_FLOW_FIRST_DESCRIPTOR */ "", 62499 /* NBI_BIST_FLOW__SECOND_DESCRIPTOR */ "", 62500 /* NBI_BIST_GENERAL_CONFIGURATION */ "", 62501 /* NBI_BIST_RX_COUNTERS_1 */ "", 62502 /* NBI_BIST_RX_COUNTERS_2 */ "", 62503 /* NBI_BIST_RX_COUNTERS_3 */ "", 62504 /* NBI_BIST_RX_FLOW_COUNTER */ "", 62505 /* NBI_BIST_RX_OK_BURSTS_COUNTER */ "", 62506 /* NBI_BIST_RX_SHAPER */ "", 62507 /* NBI_BIST_SEED */ "", 62508 /* NBI_BIST_STATUS */ "", 62509 /* NBI_BIST_TX_ADDITIONAL_COUNTER */ "", 62510 /* NBI_BIST_TX_BURSTS_COUNTER */ "", 62511 /* NBI_BIST_TX_BURSTS_THRESHOLD */ "", 62512 /* NBI_CHOOSE_RX_WCLK_33_LANE_FOR_MLD */ "", 62513 /* NBI_CRC_32_LANE_ERR_INDICATION */ "", 62514 /* NBI_CRC_32_LANE_VALID_INDICATION */ "", 62515 /* NBI_DPRC_SHARED_DDR_PLL_CONFIG */ "", 62516 /* NBI_ECC_1B_ERR_CNT */ "", 62517 /* NBI_ECC_2B_ERR_CNT */ "", 62518 /* NBI_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 62519 /* NBI_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 62520 /* NBI_ECC_INTERRUPT_MASK_REGISTER */ "", 62521 /* NBI_ECC_INTERRUPT_REGISTER */ "", 62522 /* NBI_ECC_INTERRUPT_REGISTER_TEST */ "", 62523 /* NBI_EGR_FIFO_DATA_WATER_MARK */ "", 62524 /* NBI_ELK_CFG */ "", 62525 /* NBI_ELK_CFG_ON_ILKN_PORT_10 */ "", 62526 /* NBI_ENABLE_DATA_PATH */ "", 62527 /* NBI_ENABLE_INTERLAKEN */ "", 62528 /* NBI_ENABLE_PKT_BOUNDARY_LLFC */ "", 62529 /* NBI_ENABLE_PKT_GEN_REGISTER */ "", 62530 /* NBI_ERROR_INITIATION_DATA */ "", 62531 /* NBI_FC_BIST */ "", 62532 /* NBI_FC_CHOOSE_PORT_FOR_PFC */ "", 62533 /* NBI_FC_GEN_SAFC_REFRESH_TIMER */ "", 62534 /* NBI_FC_ILKN */ "", 62535 /* NBI_FC_ILKN_RX_0_CHFC_FORCE */ "", 62536 /* NBI_FC_ILKN_RX_0_CHFC_FROM_CFC_RAW */ "", 62537 /* NBI_FC_ILKN_RX_0_CHFC_FROM_PORT_RAW */ "", 62538 /* NBI_FC_ILKN_RX_0_CHFC_FROM_PORT_ROC */ "", 62539 /* NBI_FC_ILKN_RX_0_CHFC_TO_CFC_MASK */ "", 62540 /* NBI_FC_ILKN_RX_0_LLFC_FROM_RX_CNT */ "", 62541 /* NBI_FC_ILKN_RX_1_CHFC_FORCE */ "", 62542 /* NBI_FC_ILKN_RX_1_CHFC_FROM_CFC_RAW */ "", 62543 /* NBI_FC_ILKN_RX_1_CHFC_FROM_PORT_RAW */ "", 62544 /* NBI_FC_ILKN_RX_1_CHFC_FROM_PORT_ROC */ "", 62545 /* NBI_FC_ILKN_RX_1_CHFC_TO_CFC_MASK */ "", 62546 /* NBI_FC_ILKN_RX_1_LLFC_FROM_RX_CNT */ "", 62547 /* NBI_FC_ILKN_RX_CHFC_CAL_LEN */ "", 62548 /* NBI_FC_ILKN_TX_0_GEN_CHFC_FORCE */ "", 62549 /* NBI_FC_ILKN_TX_0_GEN_CHFC_FROM_CFC_MASK */ "", 62550 /* NBI_FC_ILKN_TX_0_GEN_CHFC_ROC */ "", 62551 /* NBI_FC_ILKN_TX_0_GEN_LLFC_CNT */ "", 62552 /* NBI_FC_ILKN_TX_0_LLFC_STOP_TX_CNT */ "", 62553 /* NBI_FC_ILKN_TX_1_GEN_CHFC_FORCE */ "", 62554 /* NBI_FC_ILKN_TX_1_GEN_CHFC_FROM_CFC_MASK */ "", 62555 /* NBI_FC_ILKN_TX_1_GEN_CHFC_ROC */ "", 62556 /* NBI_FC_ILKN_TX_1_GEN_LLFC_CNT */ "", 62557 /* NBI_FC_ILKN_TX_1_LLFC_STOP_TX_CNT */ "", 62558 /* NBI_FC_LLFC_STOP_TX_FORCE */ "", 62559 /* NBI_FC_LLFC_STOP_TX_FROM_CFC_MASK */ "", 62560 /* NBI_FC_MASK_FC_WHEN_LINK_FAIL */ "", 62561 /* NBI_FC_PFC_CFG */ "", 62562 /* NBI_FC_PFC_DEBUG_INDICATIONS */ "", 62563 /* NBI_FC_PFC_MLF_MASK */ "", 62564 /* NBI_FC_PFC_RX_BITMAP_TYPE_A */ "", 62565 /* NBI_FC_PFC_RX_BITMAP_TYPE_B */ "", 62566 /* NBI_FC_PFC_RX_BITMAP_TYPE_PER_PORT */ "", 62567 /* NBI_FC_PFC_TX_BITMAP_TYPE_A */ "", 62568 /* NBI_FC_PFC_TX_BITMAP_TYPE_B */ "", 62569 /* NBI_FC_PFC_TX_BITMAP_TYPE_PER_PORT */ "", 62570 /* NBI_FC_RESET */ "", 62571 /* NBI_FC_RTM_CONFIG */ "", 62572 /* NBI_FC_RTM_TIMER */ "", 62573 /* NBI_FC_RX_GEN_LLFC_FROM_MLF */ "", 62574 /* NBI_FC_RX_GEN_PFC_FROM_MLF */ "", 62575 /* NBI_FC_RX_LLFC_STOP_TX_FROM_MUBITS */ "", 62576 /* NBI_FC_RX_MUBITS_TO_CFC */ "", 62577 /* NBI_FC_TX_GEN_LLFC_FORCE */ "", 62578 /* NBI_FC_TX_GEN_LLFC_FROM_CFC */ "", 62579 /* NBI_FC_TX_GEN_LLFC_FROM_CFC_MASK */ "", 62580 /* NBI_FC_TX_GEN_LLFC_FROM_MLF_MASK */ "", 62581 /* NBI_FC_TX_GEN_LLFC_FROM_NPM_MASK */ "", 62582 /* NBI_FC_TX_GEN_LLFC_TO_XMAL */ "", 62583 /* NBI_FC_TX_GEN_PFC_FORCE */ "", 62584 /* NBI_FC_TX_LLFC_STOP_TX_FROM_CFC */ "", 62585 /* NBI_FC_TX_LLFC_STOP_TX_TO_XMAL */ "", 62586 /* NBI_FC_TX_LOW_PASS_FILTER */ "", 62587 /* NBI_FC_TX_MUBITS_FROM_CFC */ "", 62588 /* NBI_FIFO_STATUS_HISTOGRAM_PORTS */ "", 62589 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_0_BIN_0 */ "", 62590 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_0_BIN_1 */ "", 62591 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_0_BIN_2 */ "", 62592 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_0_BIN_3 */ "", 62593 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_0_TH */ "", 62594 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_1_BIN_0 */ "", 62595 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_1_BIN_1 */ "", 62596 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_1_BIN_2 */ "", 62597 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_1_BIN_3 */ "", 62598 /* NBI_FIFO_STATUS_HISTOGRAM_PORT_1_TH */ "", 62599 /* NBI_FIFO_WRITE_POINTER_MLF_SELECT */ "", 62600 /* NBI_FIFO_WRITE_POINTER_RESULT */ "", 62601 /* NBI_GTIMER_CONFIGURATION */ "", 62602 /* NBI_GTIMER_TRIGGER */ "", 62603 /* NBI_HRF_RX_CONTROLLER_CONFIG_1 */ "", 62604 /* NBI_HRF_RX_CONTROLLER_MAX_OCCUPANCY */ "", 62605 /* NBI_HRF_RX_CONTROLLER_STATUS */ "", 62606 /* NBI_HRF_TX_CONTROLLER_CONFIG */ "", 62607 /* NBI_HRF_TX_CONTROLLER_STATUS */ "", 62608 /* NBI_HRF_TX_MLF_MAX_OCCUPANCY */ "", 62609 /* NBI_ILKN_0_MULTIPLE_USE_BITS */ "", 62610 /* NBI_ILKN_0_RETRANS_SEQ_AT_DISC */ "", 62611 /* NBI_ILKN_1_MULTIPLE_USE_BITS */ "", 62612 /* NBI_ILKN_1_RETRANS_SEQ_AT_DISC */ "", 62613 /* NBI_ILKN_DEBUG_CONFIG */ "", 62614 /* NBI_ILKN_DEBUG_STATUS */ "", 62615 /* NBI_ILKN_INTERRUPT_MASK_REGISTER */ "", 62616 /* NBI_ILKN_INTERRUPT_REGISTER */ "", 62617 /* NBI_ILKN_INTERRUPT_REGISTER_TEST */ "", 62618 /* NBI_ILKN_INVERT_POLARITY_SIGNALS */ "", 62619 /* NBI_ILKN_MODE */ "", 62620 /* NBI_ILKN_MULTIPLE_USE_BITS_STATUS */ "", 62621 /* NBI_ILKN_RESET */ "", 62622 /* NBI_ILKN_RETRANSMIT_FSM_STATE_DEBUG_CONFIG */ "", 62623 /* NBI_ILKN_RX_0_RETRANSMIT_CONFIG */ "", 62624 /* NBI_ILKN_RX_0_RETRANSMIT_CONFIG_TIMERS */ "", 62625 /* NBI_ILKN_RX_0_RETRANSMIT_DEBUG_INFORMATION */ "", 62626 /* NBI_ILKN_RX_1_RETRANSMIT_CONFIG */ "", 62627 /* NBI_ILKN_RX_1_RETRANSMIT_CONFIG_TIMERS */ "", 62628 /* NBI_ILKN_RX_1_RETRANSMIT_DEBUG_INFORMATION */ "", 62629 /* NBI_ILKN_RX_FORCE_RESYNC */ "", 62630 /* NBI_ILKN_RX_LANES_RESET */ "", 62631 /* NBI_ILKN_TX_0_RETRANSMIT_CONFIG */ "", 62632 /* NBI_ILKN_TX_1_RETRANSMIT_CONFIG */ "", 62633 /* NBI_ILKN_TX_LANES_RESET */ "", 62634 /* NBI_INDIRECT_COMMAND */ "", 62635 /* NBI_INDIRECT_COMMAND_ADDRESS */ "", 62636 /* NBI_INDIRECT_COMMAND_DATA_INCREMENT */ "", 62637 /* NBI_INDIRECT_COMMAND_RD_DATA */ "", 62638 /* NBI_INDIRECT_COMMAND_WR_DATA */ "", 62639 /* NBI_INDIRECT_EGRESS_DATA_LSB_SEL */ "", 62640 /* NBI_INDIRECT_WR_MASK */ "", 62641 /* NBI_ING_FIFO_DATA_WATER_MARK */ "", 62642 /* NBI_INITIATE_1B_ECC_ERRORS */ "", 62643 /* NBI_INITIATE_2B_ECC_ERRORS */ "", 62644 /* NBI_INITIATE_PARITY_ERRORS */ "", 62645 /* NBI_INTERRUPT_MASK_REGISTER */ "", 62646 /* NBI_INTERRUPT_REGISTER */ "", 62647 /* NBI_INTERRUPT_REGISTER_TEST */ "", 62648 /* NBI_IPG_CRC_ERR_CNT */ "", 62649 /* NBI_IREN_RDY_CNT */ "", 62650 /* NBI_IRE_SHAPER_CNT */ "", 62651 /* NBI_LANE_BAD_FRAMING_LAYER_ERR */ "", 62652 /* NBI_LANE_FRAMING_ERR */ "", 62653 /* NBI_LANE_META_FRAME_LENGTH_ERR */ "", 62654 /* NBI_LANE_META_FRAME_REPEAT_ERR */ "", 62655 /* NBI_LANE_META_FRAME_SYNC_WORD_ERR */ "", 62656 /* NBI_LANE_SCRAMBLER_STATE_ERR */ "", 62657 /* NBI_LANE_SYNCHRONIZATION_ACHIEVED */ "", 62658 /* NBI_LANE_SYNCHRONIZATION_ERR */ "", 62659 /* NBI_LANE_WORD_SYNCHRONIZATION_ACHIEVED */ "", 62660 /* NBI_LAST_RECEIVED_CONTROLS */ "", 62661 /* NBI_LAST_RECEIVED_DATA */ "", 62662 /* NBI_LAST_SENT_CONTROLS */ "", 62663 /* NBI_LAST_SENT_DATA */ "", 62664 /* NBI_LINK_ACTIVE */ "", 62665 /* NBI_LINK_PARTNER_INTERFACE_STATUS */ "", 62666 /* NBI_LINK_PARTNER_LANES_STATUS */ "", 62667 /* NBI_LINK_PARTNER_LANES_STATUS_FROM_OOB */ "", 62668 /* NBI_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER */ "", 62669 /* NBI_LINK_STATUS_CHANGE_INTERRUPT_REGISTER */ "", 62670 /* NBI_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST */ "", 62671 /* NBI_LOOP_BACK_MODE */ "", 62672 /* NBI_MASK_ECC_PARITY_ERROR_FROM_DATA_PATH */ "", 62673 /* NBI_NBI_THROWN_BURSTS_COUNTERS_75P_INTERRUPT_MASK_REGISTER */ "", 62674 /* NBI_NBI_THROWN_BURSTS_COUNTERS_75P_INTERRUPT_REGISTER */ "", 62675 /* NBI_NBI_THROWN_BURSTS_COUNTERS_75P_INTERRUPT_REGISTER_TEST */ "", 62676 /* NBI_NIF_CONNECT_XLP_1_TO_NBI */ "", 62677 /* NBI_NIF_GENERAL_CONFIG */ "", 62678 /* NBI_NIF_PORTS_CFG */ "", 62679 /* NBI_NIF_STATISTIC_DUPLICATE_ENABLE */ "", 62680 /* NBI_NIF_WC_CFG */ "", 62681 /* NBI_NIF_WC_RX_SEQ_DONE */ "", 62682 /* NBI_NIF_WC_TX_PLL_OVERRIDE */ "", 62683 /* NBI_NPUN_RDY_CNT */ "", 62684 /* NBI_NPU_DATA_PATH_STATUS */ "", 62685 /* NBI_NUM_THROWN_BURSTS_COUNTER_RX_HRF_0 */ "", 62686 /* NBI_NUM_THROWN_BURSTS_COUNTER_RX_HRF_1 */ "", 62687 /* NBI_NUM_THROWN_BURSTS_COUNTER_RX_PORT_0 */ "", 62688 /* NBI_NUM_THROWN_BURSTS_COUNTER_RX_PORT_1 */ "", 62689 /* NBI_NUM_THROWN_BURSTS_COUNTER_RX_PORT_2 */ "", 62690 /* NBI_NUM_THROWN_BURSTS_COUNTER_RX_PORT_3 */ "", 62691 /* NBI_PARITY_ERR_CNT */ "", 62692 /* NBI_PARITY_ERR_MONITOR_MEM_MASK */ "", 62693 /* NBI_PKT_GEN_CAPTURE_CONTROLS */ "", 62694 /* NBI_PKT_GEN_CRC_CONTROLS */ "", 62695 /* NBI_PKT_GEN_CRC_SOP_MASK */ "", 62696 /* NBI_PKT_GEN_DATA_REGISTER_1023_512 */ "", 62697 /* NBI_PKT_GEN_DATA_REGISTER_1535_1024 */ "", 62698 /* NBI_PKT_GEN_DATA_REGISTER_2047_1536 */ "", 62699 /* NBI_PKT_GEN_DATA_REGISTER_511_0 */ "", 62700 /* NBI_PKT_GEN_DATA_REGISTER_HEADER_63_32 */ "", 62701 /* NBI_PKT_GEN_GENERAL_CONTROL_REGISTER */ "", 62702 /* NBI_PKT_GEN_INGRESS_MUX_ENABLE_REGISTER */ "", 62703 /* NBI_PKT_GEN_LFSR_CONTROL_REGISTER */ "", 62704 /* NBI_PKT_REC_CAPTURE_REGISTER */ "", 62705 /* NBI_PORTS_INDICATIONS */ "", 62706 /* NBI_PORT_EEE_LPI_RX_STATE */ "", 62707 /* NBI_PORT_EEE_LPI_TX_STATE */ "", 62708 /* NBI_PORT_METER_ADD_CFG_RX */ "", 62709 /* NBI_PORT_METER_MASK_FOR_LLFC */ "", 62710 /* NBI_PORT_METER_PORTS_RSTN */ "", 62711 /* NBI_PORT_METER_RSTN */ "", 62712 /* NBI_PORT_METER_THRESHOLDS_CFG */ "", 62713 /* NBI_PORT_TO_CHANNLE_MAPPING */ "", 62714 /* NBI_RECEIVED_RETRANSMIT_DEBUG */ "", 62715 /* NBI_REG_0085 */ "", 62716 /* NBI_REG_0090 */ "", 62717 /* NBI_REG_0091 */ "", 62718 /* NBI_REG_0092 */ "", 62719 /* NBI_REG_0093 */ "", 62720 /* NBI_REG_00AE */ "", 62721 /* NBI_REG_00AF */ "", 62722 /* NBI_REG_00B0 */ "", 62723 /* NBI_REG_00B1 */ "", 62724 /* NBI_REG_00B2 */ "", 62725 /* NBI_REG_00B3 */ "", 62726 /* NBI_REG_00B4 */ "", 62727 /* NBI_REG_00B5 */ "", 62728 /* NBI_REG_00B6 */ "", 62729 /* NBI_REG_00B7 */ "", 62730 /* NBI_REG_00BC */ "", 62731 /* NBI_REG_00BD */ "", 62732 /* NBI_REG_00BE */ "", 62733 /* NBI_REG_00BF */ "", 62734 /* NBI_REG_00CF */ "", 62735 /* NBI_RESET_NBI_WITHOUT_ILKN_PORTS */ "", 62736 /* NBI_RX_0_ILKN_CONTROL */ "", 62737 /* NBI_RX_1_ILKN_CONTROL */ "", 62738 /* NBI_RX_BYTE_CNT */ "", 62739 /* NBI_RX_BYTE_TOTAL_CNT */ "", 62740 /* NBI_RX_CFG_THRESHOLD */ "", 62741 /* NBI_RX_ELK_BURSTS_CNT */ "", 62742 /* NBI_RX_ELK_ERR_BURSTS_CNT */ "", 62743 /* NBI_RX_ELK_OCTETS_CNT */ "", 62744 /* NBI_RX_ELK_STATUS */ "", 62745 /* NBI_RX_ELK_THROWN_BURSTS_CNT */ "", 62746 /* NBI_RX_EOP_PKT_CNT */ "", 62747 /* NBI_RX_EOP_PKT_TOTAL_CNT */ "", 62748 /* NBI_RX_ERR_PKT_CNT */ "", 62749 /* NBI_RX_ERR_PKT_TOTAL_CNT */ "", 62750 /* NBI_RX_ILKN_0_BURST_ERR_CNT */ "", 62751 /* NBI_RX_ILKN_0_CRC_24_ERR_CNT */ "", 62752 /* NBI_RX_ILKN_0_MISALIGNED_CNT */ "", 62753 /* NBI_RX_ILKN_0_MISS_EOP_ERR_CNT */ "", 62754 /* NBI_RX_ILKN_0_MISS_SOP_ERR_CNT */ "", 62755 /* NBI_RX_ILKN_0_RETRANS_CRC_24_ERR_CNT */ "", 62756 /* NBI_RX_ILKN_0_RETRANS_FSM_CLKS_IN_STATE_CNT */ "", 62757 /* NBI_RX_ILKN_0_RETRANS_FSM_ENTER_STATE_CNT */ "", 62758 /* NBI_RX_ILKN_0_RETRANS_REACHED_TIMEOUT_ERR_CNT */ "", 62759 /* NBI_RX_ILKN_0_RETRANS_RETRY_ERR_CNT */ "", 62760 /* NBI_RX_ILKN_0_RETRANS_WDOG_ERR_CNT */ "", 62761 /* NBI_RX_ILKN_0_RETRANS_WRAP_AFTER_DISC_ERR_CNT */ "", 62762 /* NBI_RX_ILKN_0_RETRANS_WRAP_B_4_DISC_ERR_CNT */ "", 62763 /* NBI_RX_ILKN_0_SENT_RETRANS_REQ_CNT */ "", 62764 /* NBI_RX_ILKN_1_BURST_ERR_CNT */ "", 62765 /* NBI_RX_ILKN_1_CRC_24_ERR_CNT */ "", 62766 /* NBI_RX_ILKN_1_MISALIGNED_CNT */ "", 62767 /* NBI_RX_ILKN_1_MISS_EOP_ERR_CNT */ "", 62768 /* NBI_RX_ILKN_1_MISS_SOP_ERR_CNT */ "", 62769 /* NBI_RX_ILKN_1_RETRANS_CRC_24_ERR_CNT */ "", 62770 /* NBI_RX_ILKN_1_RETRANS_FSM_CLKS_IN_STATE_CNT */ "", 62771 /* NBI_RX_ILKN_1_RETRANS_FSM_ENTER_STATE_CNT */ "", 62772 /* NBI_RX_ILKN_1_RETRANS_REACHED_TIMEOUT_ERR_CNT */ "", 62773 /* NBI_RX_ILKN_1_RETRANS_RETRY_ERR_CNT */ "", 62774 /* NBI_RX_ILKN_1_RETRANS_WDOG_ERR_CNT */ "", 62775 /* NBI_RX_ILKN_1_RETRANS_WRAP_AFTER_DISC_ERR_CNT */ "", 62776 /* NBI_RX_ILKN_1_RETRANS_WRAP_B_4_DISC_ERR_CNT */ "", 62777 /* NBI_RX_ILKN_1_SENT_RETRANS_REQ_CNT */ "", 62778 /* NBI_RX_ILKN_CRC_32_ERR_CNT */ "", 62779 /* NBI_RX_ILKN_STATUS */ "", 62780 /* NBI_RX_ILKN_STATUS_PARITY_ERROR */ "", 62781 /* NBI_RX_MLF_CONFIG */ "", 62782 /* NBI_RX_MLF_LLFC_THRESHOLDS_CONFIG */ "", 62783 /* NBI_RX_MLF_MAX_OCCUPANCY */ "", 62784 /* NBI_RX_MLF_MAX_OCCUPANCY_1 */ "", 62785 /* NBI_RX_MLF_PFC_THRESHOLDS_CONFIG */ "", 62786 /* NBI_RX_MLF_RESET_PORTS */ "", 62787 /* NBI_RX_MLF_STATUS */ "", 62788 /* NBI_RX_MLF_STATUS_1 */ "", 62789 /* NBI_RX_NUM_RUNTS */ "", 62790 /* NBI_RX_NUM_THROWN_EOPS_COUNTER */ "", 62791 /* NBI_RX_OVF_DROP_CNT */ "", 62792 /* NBI_RX_OVF_ERR_CNT */ "", 62793 /* NBI_RX_PORT_OVF_PORT */ "", 62794 /* NBI_RX_REQUEST_HIGH_ENABLE */ "", 62795 /* NBI_RX_REQUEST_LOW_ENABLE */ "", 62796 /* NBI_RX_ROUND_ROBIN_REQ */ "", 62797 /* NBI_RX_SOP_PKT_CNT */ "", 62798 /* NBI_RX_SOP_PKT_TOTAL_CNT */ "", 62799 /* NBI_SBUS_BROADCAST_ID */ "", 62800 /* NBI_SBUS_LAST_IN_CHAIN */ "", 62801 /* NBI_STATISTICS */ "", 62802 /* NBI_STATISTICS_READ_DATA */ "", 62803 /* NBI_STATISTICS_READ_SELECT */ "", 62804 /* NBI_STATISTICS_RX_BINNING */ "", 62805 /* NBI_STATISTICS_RX_BURSTS_ERR_CNT */ "", 62806 /* NBI_STATISTICS_RX_BURSTS_OK_CNT */ "", 62807 /* NBI_STATISTICS_RX_FRAME_ERR_CNT */ "", 62808 /* NBI_STATISTICS_RX_TOTAL_LENG_CNT */ "", 62809 /* NBI_STATISTICS_STATUS */ "", 62810 /* NBI_STATISTICS_TX_BINNING */ "", 62811 /* NBI_STATISTICS_TX_BURSTS_CNT */ "", 62812 /* NBI_STATISTICS_TX_FRAME_ERR_CNT */ "", 62813 /* NBI_STATISTICS_TX_TOTAL_LENG_CNT */ "", 62814 /* NBI_STAT_CNT_75P_INTERRUPT_MASK_REGISTER */ "", 62815 /* NBI_STAT_CNT_75P_INTERRUPT_REGISTER */ "", 62816 /* NBI_STAT_CNT_75P_INTERRUPT_REGISTER_TEST */ "", 62817 /* NBI_STAT_INTERRUPT_MASK_REGISTER */ "", 62818 /* NBI_STAT_INTERRUPT_REGISTER */ "", 62819 /* NBI_STAT_INTERRUPT_REGISTER_TEST */ "", 62820 /* NBI_SYNC_ETH_CFG */ "", 62821 /* NBI_SYNC_ETH_COUNTER */ "", 62822 /* NBI_SYNC_ETH_SQUELCH_DIS_TH_REG */ "", 62823 /* NBI_SYNC_ETH_SQUELCH_EN_TH_REG */ "", 62824 /* NBI_TRANSMIT_RETRANSMIT_DEBUG */ "", 62825 /* NBI_TXI_IRDY */ "", 62826 /* NBI_TX_0_ILKN_CONTROL */ "", 62827 /* NBI_TX_0_ILKN_STATUS_PARITY_ERROR */ "", 62828 /* NBI_TX_1_ILKN_CONTROL */ "", 62829 /* NBI_TX_1_ILKN_STATUS_PARITY_ERR */ "", 62830 /* NBI_TX_BYTE_CNT */ "", 62831 /* NBI_TX_BYTE_TOTAL_CNT */ "", 62832 /* NBI_TX_CFG_THRESHOLD */ "", 62833 /* NBI_TX_ELK_BURSTS_CNT */ "", 62834 /* NBI_TX_ELK_OCTETS_CNT */ "", 62835 /* NBI_TX_EOP_PKT_CNT */ "", 62836 /* NBI_TX_EOP_PKT_TOTAL_CNT */ "", 62837 /* NBI_TX_ERR_PKT_CNT */ "", 62838 /* NBI_TX_ERR_PKT_TOTAL_CNT */ "", 62839 /* NBI_TX_FLUSH_EGRESS */ "", 62840 /* NBI_TX_ILKN_0_FLUSHED_BURSTS_CNT */ "", 62841 /* NBI_TX_ILKN_0_RECEIVED_RETRANS_REQ_CNT */ "", 62842 /* NBI_TX_ILKN_1_FLUSHED_BURSTS_CNT */ "", 62843 /* NBI_TX_ILKN_1_RECEIVED_RETRANS_REQ_CNT */ "", 62844 /* NBI_TX_ILKN_RATE_LIMITER_CONFIG */ "", 62845 /* NBI_TX_ILKN_STATUS */ "", 62846 /* NBI_TX_MLF_CONFIG */ "", 62847 /* NBI_TX_MLF_MAX_OCCUPANCY */ "", 62848 /* NBI_TX_MLF_NUM_CREDITS_FROM_UNIPORT */ "", 62849 /* NBI_TX_MLF_RESET_PORTS */ "", 62850 /* NBI_TX_MLF_STATUS */ "", 62851 /* NBI_TX_OVF_DROP_CNT */ "", 62852 /* NBI_TX_OVF_ERR_CNT */ "", 62853 /* NBI_TX_PORTS_CONFIG */ "", 62854 /* NBI_TX_PORT_OVF_PORT */ "", 62855 /* NBI_TX_SOP_PKT_CNT */ "", 62856 /* NBI_TX_SOP_PKT_TOTAL_CNT */ "", 62857 /* NBI_TX_STOP_EGRESS */ "", 62858 /* NBI_WC_BYPASS_MODE */ "", 62859 /* NHI_GROUP_TC_PROFILE_PARITY_CONTROL */ "", 62860 /* NIF_ADDITIONAL_RESETS */ "", 62861 /* NIF_BIST_CONTEXTS_MASK */ "", 62862 /* NIF_BIST_CONTEXT_TO_NIF_PORT_MAP */ "", 62863 /* NIF_BIST_COUNTERS_OVF */ "", 62864 /* NIF_BIST_EVENTS_GENERATOR */ "", 62865 /* NIF_BIST_EVENTS_STATUS */ "", 62866 /* NIF_BIST_FLOW_FIRST_DESCRIPTOR */ "", 62867 /* NIF_BIST_FLOW_SECOND_DESCRIPTOR */ "", 62868 /* NIF_BIST_GENERAL_CONFIGURATION */ "", 62869 /* NIF_BIST_RX_COUNTERS_1 */ "", 62870 /* NIF_BIST_RX_COUNTERS_2 */ "", 62871 /* NIF_BIST_RX_COUNTERS_3 */ "", 62872 /* NIF_BIST_RX_FLOW_CNT */ "", 62873 /* NIF_BIST_RX_OK_PKT_CNT */ "", 62874 /* NIF_BIST_RX_SHAPER */ "", 62875 /* NIF_BIST_SEED */ "", 62876 /* NIF_BIST_STATUS */ "", 62877 /* NIF_BIST_TX_ADDITIONAL_COUNTER */ "", 62878 /* NIF_BIST_TX_PKT_CNT */ "", 62879 /* NIF_BIST_TX_PKT_TH */ "", 62880 /* NIF_ECC_1B_ERR_CNT */ "", 62881 /* NIF_ECC_2B_ERR_CNT */ "", 62882 /* NIF_ECC_ERR_1B_INITIATE */ "", 62883 /* NIF_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 62884 /* NIF_ECC_ERR_2B_INITIATE */ "", 62885 /* NIF_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 62886 /* NIF_ECC_INTERRUPT_REGISTER */ "", 62887 /* NIF_ECC_INTERRUPT_REGISTER_MASK */ "", 62888 /* NIF_ECC_INTERRUPT_REGISTER_TEST */ "", 62889 /* NIF_EGQ_PORT_FOR_NIF_PORT */ "", 62890 /* NIF_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 62891 /* NIF_ERROR_INITIATION_DATA */ "", 62892 /* NIF_ETH_TX_GEN_LLFC_CNT */ "", 62893 /* NIF_ETH_TX_LLFC_STOP_TX_CNT */ "", 62894 /* NIF_FC_BIST */ "", 62895 /* NIF_FC_CHOOSE_PORT_FOR_ETH_TX */ "", 62896 /* NIF_FC_CHOOSE_PORT_FOR_PFC */ "", 62897 /* NIF_FC_GEN_SAFC_REFRESH_TIMER */ "", 62898 /* NIF_FC_LLFC_STOP_TX_FORCE */ "", 62899 /* NIF_FC_LLFC_STOP_TX_FROM_CFC_MASK */ "", 62900 /* NIF_FC_MASK_FC_WHEN_LINK_FAIL */ "", 62901 /* NIF_FC_PFC_CFG */ "", 62902 /* NIF_FC_PFC_DEBUG_INDICATIONS */ "", 62903 /* NIF_FC_PFC_QMLF_MASK */ "", 62904 /* NIF_FC_PFC_RX_BITMAP_MAP_8_TO_2_TYPE_A */ "", 62905 /* NIF_FC_PFC_RX_BITMAP_MAP_8_TO_2_TYPE_B */ "", 62906 /* NIF_FC_PFC_RX_BITMAP_MAP_FORCE_EN */ "", 62907 /* NIF_FC_PFC_RX_BITMAP_TYPE_A */ "", 62908 /* NIF_FC_PFC_RX_BITMAP_TYPE_B */ "", 62909 /* NIF_FC_PFC_RX_BITMAP_TYPE_PER_PORT */ "", 62910 /* NIF_FC_PFC_TX_BITMAP_TYPE_A */ "", 62911 /* NIF_FC_PFC_TX_BITMAP_TYPE_B */ "", 62912 /* NIF_FC_PFC_TX_BITMAP_TYPE_C */ "", 62913 /* NIF_FC_PFC_TX_BITMAP_TYPE_D */ "", 62914 /* NIF_FC_PFC_TX_BITMAP_TYPE_PER_PORT */ "", 62915 /* NIF_FC_RESET */ "", 62916 /* NIF_FC_RX_GEN_LLFC_FROM_QMLF */ "", 62917 /* NIF_FC_RX_GEN_PFC_FROM_QMLF */ "", 62918 /* NIF_FC_TX_GEN_LLFC_FORCE */ "", 62919 /* NIF_FC_TX_GEN_LLFC_FROM_CFC */ "", 62920 /* NIF_FC_TX_GEN_LLFC_FROM_CFC_MASK */ "", 62921 /* NIF_FC_TX_GEN_LLFC_FROM_CFC_OCB_MASK */ "", 62922 /* NIF_FC_TX_GEN_LLFC_FROM_NPM_MASK */ "", 62923 /* NIF_FC_TX_GEN_LLFC_FROM_QMLF_MASK */ "", 62924 /* NIF_FC_TX_GEN_LLFC_TO_PM */ "", 62925 /* NIF_FC_TX_GEN_PFC_FORCE */ "", 62926 /* NIF_FC_TX_LLFC_STOP_TX_FROM_CFC */ "", 62927 /* NIF_FC_TX_LLFC_STOP_TX_TO_PM */ "", 62928 /* NIF_FC_TX_LOW_PASS_FILTER */ "", 62929 /* NIF_FIFO_WRITE_POINTER_QMLF_SELECT */ "", 62930 /* NIF_FIFO_WRITE_POINTER_RESULT */ "", 62931 /* NIF_GLOBAL_MEM_OPTIONS */ "", 62932 /* NIF_GTIMER_CONFIGURATION */ "", 62933 /* NIF_INDIRECT_COMMAND */ "", 62934 /* NIF_INDIRECT_COMMAND_ADDRESS */ "", 62935 /* NIF_INDIRECT_COMMAND_DATA_INCREMENT */ "", 62936 /* NIF_INDIRECT_COMMAND_RD_DATA */ "", 62937 /* NIF_INDIRECT_COMMAND_WIDE_MEM */ "", 62938 /* NIF_INDIRECT_COMMAND_WR_DATA */ "", 62939 /* NIF_INDIRECT_FORCE_BUBBLE */ "", 62940 /* NIF_INTERRUPT_MASK_REGISTER */ "", 62941 /* NIF_INTERRUPT_REGISTER */ "", 62942 /* NIF_INTERRUPT_REGISTER_TEST */ "", 62943 /* NIF_LAST_RECEIVED_CONTROLS */ "", 62944 /* NIF_LAST_RECEIVED_DATA */ "", 62945 /* NIF_LAST_RECEIVED_DATA_ON_SOP */ "", 62946 /* NIF_LAST_SENT_CONTROLS */ "", 62947 /* NIF_LAST_SENT_DATA */ "", 62948 /* NIF_LAST_SENT_DATA_ON_SOP */ "", 62949 /* NIF_LINK_ACTIVE */ "", 62950 /* NIF_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER */ "", 62951 /* NIF_LINK_STATUS_CHANGE_INTERRUPT_REGISTER */ "", 62952 /* NIF_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST */ "", 62953 /* NIF_MEM_PTR_ASYNC_FIFO_ALWAYS_WRITE */ "", 62954 /* NIF_MEM_PTR_ASYNC_FIFO_CLK_RATIO */ "", 62955 /* NIF_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_MASK_REGISTER */ "", 62956 /* NIF_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER */ "", 62957 /* NIF_NBI_PKT_DROP_COUNTERS_75P_INTERRUPT_REGISTER_TEST */ "", 62958 /* NIF_NIF_PM_CFG */ "", 62959 /* NIF_NIF_PM_EXTERNAL_LINK_INTERRUPT_INDICATION */ "", 62960 /* NIF_NIF_PM_EXTERNAL_LOCAL_FAULT_INDICATION */ "", 62961 /* NIF_NIF_PM_EXTERNAL_LPI_INDICATION */ "", 62962 /* NIF_NIF_PM_EXTERNAL_REMOTE_FAULT_INDICATION */ "", 62963 /* NIF_NIF_PM_RESOLVED_SPEED */ "", 62964 /* NIF_NIF_PM_TERMINATE_RX_MAC_CTRL_PACKETS */ "", 62965 /* NIF_NIF_TSC_LANE_STATUS */ "", 62966 /* NIF_OOB_CONFIG */ "", 62967 /* NIF_OOB_INDICATIONS */ "", 62968 /* NIF_OOB_RSTN */ "", 62969 /* NIF_PARITY_ERR_CNT */ "", 62970 /* NIF_PAR_ERR_INITIATE */ "", 62971 /* NIF_PAR_ERR_MEM_MASK */ "", 62972 /* NIF_PCMI_0 */ "", 62973 /* NIF_PCMI_1 */ "", 62974 /* NIF_PCMI_2 */ "", 62975 /* NIF_PCMI_3 */ "", 62976 /* NIF_PCMI_4 */ "", 62977 /* NIF_PCMI_0_S */ "", 62978 /* NIF_PCMI_0_T */ "", 62979 /* NIF_PCMI_1_S */ "", 62980 /* NIF_PCMI_1_T */ "", 62981 /* NIF_PCMI_2_S */ "", 62982 /* NIF_PCMI_2_T */ "", 62983 /* NIF_PCMI_3_S */ "", 62984 /* NIF_PCMI_3_T */ "", 62985 /* NIF_PCMI_4_S */ "", 62986 /* NIF_PCMI_4_T */ "", 62987 /* NIF_PMX_MODE_SINGLE_OR_MULTI */ "", 62988 /* NIF_PM_ACCUMULATE_AND_SYNC_CYCLE_NUM */ "", 62989 /* NIF_PM_EEE_LPI_DETECT */ "", 62990 /* NIF_PM_MDIO_CTRL */ "", 62991 /* NIF_PM_PWRDWN_INDICATION */ "", 62992 /* NIF_PM_STRAP_LED_INTRA_DELAY */ "", 62993 /* NIF_PM_STRAP_LED_OUTPUT_DELAY */ "", 62994 /* NIF_PM_TIMESTAMPING_MODE */ "", 62995 /* NIF_PM_TX_PLL_LOCK_STATUS */ "", 62996 /* NIF_PORTS_INDICATIONS */ "", 62997 /* NIF_PRD_CONFIG_QMLF */ "", 62998 /* NIF_PRD_EN */ "", 62999 /* NIF_PRD_ERR_PKT_DROP_CNT_PORT */ "", 63000 /* NIF_PRD_LAST_PKT_KEY */ "", 63001 /* NIF_PRD_PKT_DROP_CNT_PORT */ "", 63002 /* NIF_RESERVED_MIRROR_ADDR */ "", 63003 /* NIF_RESERVED_MTCD */ "", 63004 /* NIF_RESERVED_MTCP */ "", 63005 /* NIF_RESERVED_SPARE_0 */ "", 63006 /* NIF_RESERVED_SPARE_1 */ "", 63007 /* NIF_RESERVED_SPARE_2 */ "", 63008 /* NIF_RESERVED_SPARE_3 */ "", 63009 /* NIF_RES_CAL_0_STATUS */ "", 63010 /* NIF_RES_CAL_1_STATUS */ "", 63011 /* NIF_RX_CORE_0_BYTE_COUNTER */ "", 63012 /* NIF_RX_CORE_0_PKT_COUNTER */ "", 63013 /* NIF_RX_ENABLE_DATAPATH */ "", 63014 /* NIF_RX_MLF_ERROR_PM */ "", 63015 /* NIF_RX_MLF_LEVEL_PM */ "", 63016 /* NIF_RX_MLF_LLFC_THRESHOLDS_CONFIG */ "", 63017 /* NIF_RX_MLF_MAX_OCCUPANCY */ "", 63018 /* NIF_RX_MLF_PFC_THRESHOLDS_CONFIG */ "", 63019 /* NIF_RX_MLF_PRD_THRESHOLDS_CONFIG */ "", 63020 /* NIF_RX_NUM_TOTAL_DROPPED_EOPS */ "", 63021 /* NIF_RX_PKT_DROP_COUNTER */ "", 63022 /* NIF_RX_PKT_FC_DROP_COUNTER */ "", 63023 /* NIF_RX_PKT_FC_ERR_COUNTER */ "", 63024 /* NIF_RX_PORTS_SRSTN */ "", 63025 /* NIF_RX_PORT_OVF */ "", 63026 /* NIF_RX_PRD_VLAN_ETHERTYPE */ "", 63027 /* NIF_RX_QMLF_CONFIG */ "", 63028 /* NIF_RX_REQ_PIPE_0_HIGH_EN */ "", 63029 /* NIF_RX_REQ_PIPE_0_LOW_EN */ "", 63030 /* NIF_RX_SCH_DEBUG_CONF */ "", 63031 /* NIF_RX_SCH_DEBUG_RESULT */ "", 63032 /* NIF_RX_THRESHOLD_AFTER_OVERFLOW_QMLF */ "", 63033 /* NIF_RX_TOTAL_BYTE_COUNTER */ "", 63034 /* NIF_RX_TOTAL_PKT_COUNTER */ "", 63035 /* NIF_SBUS_BROADCAST_ID */ "", 63036 /* NIF_SBUS_LAST_IN_CHAIN */ "", 63037 /* NIF_SIF_CFG */ "", 63038 /* NIF_STATS_BURSTS_CNT_PORT */ "", 63039 /* NIF_STATS_OCTETS_CNT_PORT */ "", 63040 /* NIF_SYNC_ETH_CFG */ "", 63041 /* NIF_SYNC_ETH_COUNTER */ "", 63042 /* NIF_SYNC_ETH_SQUELCH_DIS_TH_REG */ "", 63043 /* NIF_SYNC_ETH_SQUELCH_EN_TH_REG */ "", 63044 /* NIF_TXI_PIPE_0_NOT_READY */ "", 63045 /* NIF_TX_CORE_0_BYTE_COUNTER */ "", 63046 /* NIF_TX_CORE_0_PKT_COUNTER */ "", 63047 /* NIF_TX_EGRESS_CREDITS_DEBUG_PM */ "", 63048 /* NIF_TX_ENABLE_DATAPATH */ "", 63049 /* NIF_TX_ERROR_FROM_MEM_DIDNT_PROPAGATE */ "", 63050 /* NIF_TX_MLF_LEVEL_PM */ "", 63051 /* NIF_TX_MLF_MAX_OCCUPANCY */ "", 63052 /* NIF_TX_MLF_NUM_CREDITS_FROM_PM */ "", 63053 /* NIF_TX_MLF_OVERFLOW_PM */ "", 63054 /* NIF_TX_NO_DATA_IN_BUFFER */ "", 63055 /* NIF_TX_PORTS_CONFIG */ "", 63056 /* NIF_TX_PORTS_SRSTN */ "", 63057 /* NIF_TX_PORT_OVF */ "", 63058 /* NIF_TX_QMLF_CONFIG */ "", 63059 /* NIF_TX_TOTAL_BYTE_COUNTER */ "", 63060 /* NIF_TX_TOTAL_PKT_COUNTER */ "", 63061 /* NIF_TX_WRONG_PORT_FROM_EGQ_QMLF */ "", 63062 /* NIV_ERROR_DROP_PARITY_CONTROL */ "", 63063 /* NIV_ERROR_DROP_PARITY_STATUS_INTR */ "", 63064 /* NIV_ERROR_DROP_PARITY_STATUS_NACK */ "", 63065 /* NIV_ETHERTYPE */ "", 63066 /* NIV_FORWARDING_DROP_PARITY_CONTROL */ "", 63067 /* NIV_FORWARDING_DROP_PARITY_STATUS_INTR */ "", 63068 /* NIV_FORWARDING_DROP_PARITY_STATUS_NACK */ "", 63069 /* NIV_VLAN_TAGGED_PARITY_CONTROL */ "", 63070 /* NIV_VLAN_TAGGED_PARITY_STATUS_INTR */ "", 63071 /* NIV_VLAN_TAGGED_PARITY_STATUS_NACK */ "", 63072 /* NMG_ADDITIONAL_RESETS */ "", 63073 /* NMG_AUTO_DOC_NAME_1 */ "", 63074 /* NMG_AUTO_DOC_NAME_8 */ "", 63075 /* NMG_AUTO_DOC_NAME_12 */ "", 63076 /* NMG_AUTO_DOC_NAME_16 */ "", 63077 /* NMG_AUTO_DOC_NAME_20 */ "", 63078 /* NMG_AUTO_DOC_NAME_24 */ "", 63079 /* NMG_AUTO_DOC_NAME_28 */ "", 63080 /* NMG_AUTO_DOC_NAME_32 */ "", 63081 /* NMG_AUTO_DOC_NAME_53 */ "", 63082 /* NMG_AUTO_DOC_NAME_58 */ "", 63083 /* NMG_AUTO_DOC_NAME_59 */ "", 63084 /* NMG_BIST_CONTEXTS_MASK */ "", 63085 /* NMG_BIST_CONTEXT_TO_NIF_PORT_MAP */ "", 63086 /* NMG_BIST_COUNTERS_OVF */ "", 63087 /* NMG_BIST_FLOW_FIRST_DESCRIPTOR */ "", 63088 /* NMG_BIST_FLOW_SECOND_DESCRIPTOR */ "", 63089 /* NMG_BIST_GENERAL_CONFIGURATION */ "", 63090 /* NMG_BIST_RX_COUNTERS_1 */ "", 63091 /* NMG_BIST_RX_COUNTERS_2 */ "", 63092 /* NMG_BIST_RX_COUNTERS_3 */ "", 63093 /* NMG_BIST_RX_FLOW_CNT */ "", 63094 /* NMG_BIST_RX_OK_PKT_CNT */ "", 63095 /* NMG_BIST_RX_SHAPER */ "", 63096 /* NMG_BIST_SEED */ "", 63097 /* NMG_BIST_STATUS */ "", 63098 /* NMG_BIST_TX_ADDITIONAL_COUNTER */ "", 63099 /* NMG_BIST_TX_PKT_CNT */ "", 63100 /* NMG_BIST_TX_PKT_TH */ "", 63101 /* NMG_ECC_INTERRUPT_REGISTER */ "", 63102 /* NMG_ECC_INTERRUPT_REGISTER_MASK */ "", 63103 /* NMG_ECC_INTERRUPT_REGISTER_TEST */ "", 63104 /* NMG_EGQ_CRDT_BALANCE_CNT_PER_NIF_PORT */ "", 63105 /* NMG_EGQ_PORT_FOR_NIF_PORT */ "", 63106 /* NMG_EGQ_SEND_BICAST_WITH_NO_VALID */ "", 63107 /* NMG_ETH_LINK_STAUS_CHANGE */ "", 63108 /* NMG_FC_RX_PFC_CAL_LEN */ "", 63109 /* NMG_FLUSH_OR_STOP_RX_FIFO */ "", 63110 /* NMG_GTIMER_CONFIGURATION */ "", 63111 /* NMG_GTIMER_CYCLE */ "", 63112 /* NMG_INTERRUPT_MASK_REGISTER */ "", 63113 /* NMG_INTERRUPT_REGISTER */ "", 63114 /* NMG_INTERRUPT_REGISTER_TEST */ "", 63115 /* NMG_IRE_CRDT_FIX */ "", 63116 /* NMG_IRE_TXI_RXI_INDICATION */ "", 63117 /* NMG_LAST_RECEIVED_FROM_EGQ_CONTROLS */ "", 63118 /* NMG_LAST_RECEIVED_FROM_EGQ_DATA */ "", 63119 /* NMG_LAST_RECEIVED_FROM_EGQ_DATA_ON_SOP */ "", 63120 /* NMG_LAST_SENT_TO_IRE_CONTROLS */ "", 63121 /* NMG_LAST_SENT_TO_IRE_DATA */ "", 63122 /* NMG_LAST_SENT_TO_IRE_DATA_ON_SOP */ "", 63123 /* NMG_LINK_STATUS_CHANGE_INTERRUPT_MASK_REGISTER */ "", 63124 /* NMG_LINK_STATUS_CHANGE_INTERRUPT_REGISTER */ "", 63125 /* NMG_LINK_STATUS_CHANGE_INTERRUPT_REGISTER_TEST */ "", 63126 /* NMG_NON_TDM_TXI_RXI_ERR_COUNTER */ "", 63127 /* NMG_REG_0098 */ "", 63128 /* NMG_REG_00A0 */ "", 63129 /* NMG_REG_00AA */ "", 63130 /* NMG_REG_00C4 */ "", 63131 /* NMG_RESERVED_MIRROR_ADDR */ "", 63132 /* NMG_RESERVED_SPARE_0 */ "", 63133 /* NMG_RESERVED_SPARE_1 */ "", 63134 /* NMG_RESERVED_SPARE_2 */ "", 63135 /* NMG_RESERVED_SPARE_3 */ "", 63136 /* NMG_RX_CDU_UNIT_CONFIG */ "", 63137 /* NMG_RX_ILKN_VIRTUAL_TDM_MODE */ "", 63138 /* NMG_RX_PORTS_SRSTN */ "", 63139 /* NMG_RX_REQ_HIGH_EN */ "", 63140 /* NMG_RX_REQ_LOW_EN */ "", 63141 /* NMG_RX_REQ_LOW_RMC_EN */ "", 63142 /* NMG_RX_REQ_TDM_EN */ "", 63143 /* NMG_RX_SCH_DEBUG_CONF */ "", 63144 /* NMG_RX_SCH_DEBUG_RESULT */ "", 63145 /* NMG_RX_WITH_ERR_COUNTER */ "", 63146 /* NMG_SBUS_BROADCAST_ID */ "", 63147 /* NMG_SBUS_LAST_IN_CHAIN */ "", 63148 /* NMG_SIF_CFG */ "", 63149 /* NMG_SIF_EGQ_DIS_SIF_FOR_N_CYCLES_COUNTER */ "", 63150 /* NMG_SIF_EGQ_DIS_SIF_REQ */ "", 63151 /* NMG_SIF_IF_STICKY_VALUES */ "", 63152 /* NMG_SIF_IF_TABLE_TO_WIN_MACHINE */ "", 63153 /* NMG_SIF_LAST_SENT_CONTROLS */ "", 63154 /* NMG_SIF_LAST_SENT_DATA */ "", 63155 /* NMG_SIF_LAST_SENT_DATA_ON_SOP */ "", 63156 /* NMG_SIF_MAP_TABLE */ "", 63157 /* NMG_SIF_MISS_EOP_ERR_COUNTER */ "", 63158 /* NMG_SIF_MISS_SOP_ERR_COUNTER */ "", 63159 /* NMG_SIF_NO_TMC_CRDT_DIS_SIF_REQ */ "", 63160 /* NMG_SIF_TOTAL_PACKETS_COUNTER */ "", 63161 /* NMG_SIF_TOTAL_PACKETS_WITH_ERR_COUNTER */ "", 63162 /* NMG_STATS_BURSTS_CNT_PORT */ "", 63163 /* NMG_STATS_OCTETS_CNT_PORT */ "", 63164 /* NMG_SYNC_ETH_CFG */ "", 63165 /* NMG_SYNC_ETH_COUNTER */ "", 63166 /* NMG_SYNC_ETH_LINK_STATUS_CHANGES */ "", 63167 /* NMG_SYNC_ETH_SQUELCH_DIS_TH_REG */ "", 63168 /* NMG_SYNC_ETH_SQUELCH_EN_TH_REG */ "", 63169 /* NMG_TDM_TXI_RXI_ERR_COUNTER */ "", 63170 /* NMG_TXI_NOT_READY */ "", 63171 /* NMG_TXI_TDM_NOT_READY */ "", 63172 /* NMG_TX_PORTS_SRSTN */ "", 63173 /* NMG_TX_WITH_ERR_COUNTER */ "", 63174 /* NMG_UNIT_LOW_RMC_EN_IS_ALL_MASKED */ "", 63175 /* NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROL */ "", 63176 /* NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS */ "", 63177 /* NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_INTR */ "", 63178 /* NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_NACK */ "", 63179 /* NS_BROADSYNC0_CLK_EVENT_CTRL */ "", 63180 /* NS_BROADSYNC1_CLK_EVENT_CTRL */ "", 63181 /* NS_BROADSYNC_REF_CLK_GEN_CTRL */ "", 63182 /* NS_BROADSYNC_SYNC_MODE */ "", 63183 /* NS_BS0_BS_CLK_CTRL */ "", 63184 /* NS_BS0_BS_CONFIG */ "", 63185 /* NS_BS0_BS_HEARTBEAT_CTRL */ "", 63186 /* NS_BS0_BS_HEARTBEAT_DOWN_DURATION */ "", 63187 /* NS_BS0_BS_HEARTBEAT_UP_DURATION */ "", 63188 /* NS_BS0_BS_INITIAL_CRC */ "", 63189 /* NS_BS0_BS_INPUT_TIME_0 */ "", 63190 /* NS_BS0_BS_INPUT_TIME_1 */ "", 63191 /* NS_BS0_BS_INPUT_TIME_2 */ "", 63192 /* NS_BS0_BS_OUTPUT_TIME_0 */ "", 63193 /* NS_BS0_BS_OUTPUT_TIME_1 */ "", 63194 /* NS_BS0_BS_OUTPUT_TIME_2 */ "", 63195 /* NS_BS0_BS_TC_CTRL */ "", 63196 /* NS_BS1_BS_CLK_CTRL */ "", 63197 /* NS_BS1_BS_CONFIG */ "", 63198 /* NS_BS1_BS_HEARTBEAT_CTRL */ "", 63199 /* NS_BS1_BS_HEARTBEAT_DOWN_DURATION */ "", 63200 /* NS_BS1_BS_HEARTBEAT_UP_DURATION */ "", 63201 /* NS_BS1_BS_INITIAL_CRC */ "", 63202 /* NS_BS1_BS_INPUT_TIME_0 */ "", 63203 /* NS_BS1_BS_INPUT_TIME_1 */ "", 63204 /* NS_BS1_BS_INPUT_TIME_2 */ "", 63205 /* NS_BS1_BS_OUTPUT_TIME_0 */ "", 63206 /* NS_BS1_BS_OUTPUT_TIME_1 */ "", 63207 /* NS_BS1_BS_OUTPUT_TIME_2 */ "", 63208 /* NS_BS1_BS_TC_CTRL */ "", 63209 /* NS_COMMON_CTRL */ "", 63210 /* NS_GDPLL_DEBUG_M7DG_BSTATE */ "", 63211 /* NS_GDPLL_DEBUG_M7DG_ENABLE */ "", 63212 /* NS_GDPLL_DEBUG_M7DG_INT_ENABLE */ "", 63213 /* NS_GDPLL_DEBUG_M7DG_INT_STATUS */ "", 63214 /* NS_GDPLL_DEBUG_M7DG_RSTATE */ "", 63215 /* NS_GDPLL_DEBUG_M7DG_THRESHOLD */ "", 63216 /* NS_GDPLL_DEBUG_MEM0_ECC_CONTROL */ "", 63217 /* NS_GDPLL_DEBUG_MEM0_ECC_STATUS */ "", 63218 /* NS_GDPLL_DEBUG_MEM1_ECC_CONTROL */ "", 63219 /* NS_GDPLL_DEBUG_MEM1_ECC_STATUS */ "", 63220 /* NS_GDPLL_DEBUG_MEM_TM_CONTROL */ "", 63221 /* NS_GDPLL_GDPLL_COMMON_CTRL */ "", 63222 /* NS_GDPLL_GDPLL_COMMON_INT_ENABLE */ "", 63223 /* NS_GDPLL_GDPLL_COMMON_INT_STATUS */ "", 63224 /* NS_GDPLL_IA_ERROR_CODE */ "", 63225 /* NS_GDPLL_IA_IN_ENABLE0 */ "", 63226 /* NS_GDPLL_IA_IN_ENABLE1 */ "", 63227 /* NS_GDPLL_IA_IN_ENABLE2 */ "", 63228 /* NS_GDPLL_IA_IN_ENABLE3 */ "", 63229 /* NS_GDPLL_IA_IN_STATUS0 */ "", 63230 /* NS_GDPLL_IA_IN_STATUS1 */ "", 63231 /* NS_GDPLL_IA_IN_STATUS2 */ "", 63232 /* NS_GDPLL_IA_IN_STATUS3 */ "", 63233 /* NS_GDPLL_IA_MEM_ECC_CONTROL */ "", 63234 /* NS_GDPLL_IA_MEM_ECC_STATUS */ "", 63235 /* NS_GDPLL_IA_MEM_TM_CONTROL */ "", 63236 /* NS_GDPLL_IA_TS_PAIR_AVAILABLE0 */ "", 63237 /* NS_GDPLL_IA_TS_PAIR_AVAILABLE1 */ "", 63238 /* NS_GDPLL_IA_TS_PAIR_AVAILABLE2 */ "", 63239 /* NS_GDPLL_IA_TS_PAIR_AVAILABLE3 */ "", 63240 /* NS_GDPLL_IA_UPDATE_CONFIG */ "", 63241 /* NS_GDPLL_IA_WDOG_CONFIG */ "", 63242 /* NS_GDPLL_INPUT_ARRAY_TS_000_LSB */ "", 63243 /* NS_GDPLL_INPUT_ARRAY_TS_000_MSB */ "", 63244 /* NS_GDPLL_INPUT_ARRAY_TS_001_LSB */ "", 63245 /* NS_GDPLL_INPUT_ARRAY_TS_001_MSB */ "", 63246 /* NS_GDPLL_INPUT_ARRAY_TS_002_LSB */ "", 63247 /* NS_GDPLL_INPUT_ARRAY_TS_002_MSB */ "", 63248 /* NS_GDPLL_INPUT_ARRAY_TS_003_LSB */ "", 63249 /* NS_GDPLL_INPUT_ARRAY_TS_003_MSB */ "", 63250 /* NS_GDPLL_INPUT_ARRAY_TS_004_LSB */ "", 63251 /* NS_GDPLL_INPUT_ARRAY_TS_004_MSB */ "", 63252 /* NS_GDPLL_INPUT_ARRAY_TS_005_LSB */ "", 63253 /* NS_GDPLL_INPUT_ARRAY_TS_005_MSB */ "", 63254 /* NS_GDPLL_INPUT_ARRAY_TS_006_LSB */ "", 63255 /* NS_GDPLL_INPUT_ARRAY_TS_006_MSB */ "", 63256 /* NS_GDPLL_INPUT_ARRAY_TS_007_LSB */ "", 63257 /* NS_GDPLL_INPUT_ARRAY_TS_007_MSB */ "", 63258 /* NS_GDPLL_INPUT_ARRAY_TS_008_LSB */ "", 63259 /* NS_GDPLL_INPUT_ARRAY_TS_008_MSB */ "", 63260 /* NS_GDPLL_INPUT_ARRAY_TS_009_LSB */ "", 63261 /* NS_GDPLL_INPUT_ARRAY_TS_009_MSB */ "", 63262 /* NS_GDPLL_INPUT_ARRAY_TS_010_LSB */ "", 63263 /* NS_GDPLL_INPUT_ARRAY_TS_010_MSB */ "", 63264 /* NS_GDPLL_INPUT_ARRAY_TS_011_LSB */ "", 63265 /* NS_GDPLL_INPUT_ARRAY_TS_011_MSB */ "", 63266 /* NS_GDPLL_INPUT_ARRAY_TS_012_LSB */ "", 63267 /* NS_GDPLL_INPUT_ARRAY_TS_012_MSB */ "", 63268 /* NS_GDPLL_INPUT_ARRAY_TS_013_LSB */ "", 63269 /* NS_GDPLL_INPUT_ARRAY_TS_013_MSB */ "", 63270 /* NS_GDPLL_INPUT_ARRAY_TS_014_LSB */ "", 63271 /* NS_GDPLL_INPUT_ARRAY_TS_014_MSB */ "", 63272 /* NS_GDPLL_INPUT_ARRAY_TS_015_LSB */ "", 63273 /* NS_GDPLL_INPUT_ARRAY_TS_015_MSB */ "", 63274 /* NS_GDPLL_INPUT_ARRAY_TS_016_LSB */ "", 63275 /* NS_GDPLL_INPUT_ARRAY_TS_016_MSB */ "", 63276 /* NS_GDPLL_INPUT_ARRAY_TS_017_LSB */ "", 63277 /* NS_GDPLL_INPUT_ARRAY_TS_017_MSB */ "", 63278 /* NS_GDPLL_INPUT_ARRAY_TS_018_LSB */ "", 63279 /* NS_GDPLL_INPUT_ARRAY_TS_018_MSB */ "", 63280 /* NS_GDPLL_INPUT_ARRAY_TS_019_LSB */ "", 63281 /* NS_GDPLL_INPUT_ARRAY_TS_019_MSB */ "", 63282 /* NS_GDPLL_INPUT_ARRAY_TS_020_LSB */ "", 63283 /* NS_GDPLL_INPUT_ARRAY_TS_020_MSB */ "", 63284 /* NS_GDPLL_INPUT_ARRAY_TS_021_LSB */ "", 63285 /* NS_GDPLL_INPUT_ARRAY_TS_021_MSB */ "", 63286 /* NS_GDPLL_INPUT_ARRAY_TS_022_LSB */ "", 63287 /* NS_GDPLL_INPUT_ARRAY_TS_022_MSB */ "", 63288 /* NS_GDPLL_INPUT_ARRAY_TS_023_LSB */ "", 63289 /* NS_GDPLL_INPUT_ARRAY_TS_023_MSB */ "", 63290 /* NS_GDPLL_INPUT_ARRAY_TS_024_LSB */ "", 63291 /* NS_GDPLL_INPUT_ARRAY_TS_024_MSB */ "", 63292 /* NS_GDPLL_INPUT_ARRAY_TS_025_LSB */ "", 63293 /* NS_GDPLL_INPUT_ARRAY_TS_025_MSB */ "", 63294 /* NS_GDPLL_INPUT_ARRAY_TS_026_LSB */ "", 63295 /* NS_GDPLL_INPUT_ARRAY_TS_026_MSB */ "", 63296 /* NS_GDPLL_INPUT_ARRAY_TS_027_LSB */ "", 63297 /* NS_GDPLL_INPUT_ARRAY_TS_027_MSB */ "", 63298 /* NS_GDPLL_INPUT_ARRAY_TS_028_LSB */ "", 63299 /* NS_GDPLL_INPUT_ARRAY_TS_028_MSB */ "", 63300 /* NS_GDPLL_INPUT_ARRAY_TS_029_LSB */ "", 63301 /* NS_GDPLL_INPUT_ARRAY_TS_029_MSB */ "", 63302 /* NS_GDPLL_INPUT_ARRAY_TS_030_LSB */ "", 63303 /* NS_GDPLL_INPUT_ARRAY_TS_030_MSB */ "", 63304 /* NS_GDPLL_INPUT_ARRAY_TS_031_LSB */ "", 63305 /* NS_GDPLL_INPUT_ARRAY_TS_031_MSB */ "", 63306 /* NS_GDPLL_INPUT_ARRAY_TS_032_LSB */ "", 63307 /* NS_GDPLL_INPUT_ARRAY_TS_032_MSB */ "", 63308 /* NS_GDPLL_INPUT_ARRAY_TS_033_LSB */ "", 63309 /* NS_GDPLL_INPUT_ARRAY_TS_033_MSB */ "", 63310 /* NS_GDPLL_INPUT_ARRAY_TS_034_LSB */ "", 63311 /* NS_GDPLL_INPUT_ARRAY_TS_034_MSB */ "", 63312 /* NS_GDPLL_INPUT_ARRAY_TS_035_LSB */ "", 63313 /* NS_GDPLL_INPUT_ARRAY_TS_035_MSB */ "", 63314 /* NS_GDPLL_INPUT_ARRAY_TS_036_LSB */ "", 63315 /* NS_GDPLL_INPUT_ARRAY_TS_036_MSB */ "", 63316 /* NS_GDPLL_INPUT_ARRAY_TS_037_LSB */ "", 63317 /* NS_GDPLL_INPUT_ARRAY_TS_037_MSB */ "", 63318 /* NS_GDPLL_INPUT_ARRAY_TS_038_LSB */ "", 63319 /* NS_GDPLL_INPUT_ARRAY_TS_038_MSB */ "", 63320 /* NS_GDPLL_INPUT_ARRAY_TS_039_LSB */ "", 63321 /* NS_GDPLL_INPUT_ARRAY_TS_039_MSB */ "", 63322 /* NS_GDPLL_INPUT_ARRAY_TS_040_LSB */ "", 63323 /* NS_GDPLL_INPUT_ARRAY_TS_040_MSB */ "", 63324 /* NS_GDPLL_INPUT_ARRAY_TS_041_LSB */ "", 63325 /* NS_GDPLL_INPUT_ARRAY_TS_041_MSB */ "", 63326 /* NS_GDPLL_INPUT_ARRAY_TS_042_LSB */ "", 63327 /* NS_GDPLL_INPUT_ARRAY_TS_042_MSB */ "", 63328 /* NS_GDPLL_INPUT_ARRAY_TS_043_LSB */ "", 63329 /* NS_GDPLL_INPUT_ARRAY_TS_043_MSB */ "", 63330 /* NS_GDPLL_INPUT_ARRAY_TS_044_LSB */ "", 63331 /* NS_GDPLL_INPUT_ARRAY_TS_044_MSB */ "", 63332 /* NS_GDPLL_INPUT_ARRAY_TS_045_LSB */ "", 63333 /* NS_GDPLL_INPUT_ARRAY_TS_045_MSB */ "", 63334 /* NS_GDPLL_INPUT_ARRAY_TS_046_LSB */ "", 63335 /* NS_GDPLL_INPUT_ARRAY_TS_046_MSB */ "", 63336 /* NS_GDPLL_INPUT_ARRAY_TS_047_LSB */ "", 63337 /* NS_GDPLL_INPUT_ARRAY_TS_047_MSB */ "", 63338 /* NS_GDPLL_INPUT_ARRAY_TS_048_LSB */ "", 63339 /* NS_GDPLL_INPUT_ARRAY_TS_048_MSB */ "", 63340 /* NS_GDPLL_INPUT_ARRAY_TS_049_LSB */ "", 63341 /* NS_GDPLL_INPUT_ARRAY_TS_049_MSB */ "", 63342 /* NS_GDPLL_INPUT_ARRAY_TS_050_LSB */ "", 63343 /* NS_GDPLL_INPUT_ARRAY_TS_050_MSB */ "", 63344 /* NS_GDPLL_INPUT_ARRAY_TS_051_LSB */ "", 63345 /* NS_GDPLL_INPUT_ARRAY_TS_051_MSB */ "", 63346 /* NS_GDPLL_INPUT_ARRAY_TS_052_LSB */ "", 63347 /* NS_GDPLL_INPUT_ARRAY_TS_052_MSB */ "", 63348 /* NS_GDPLL_INPUT_ARRAY_TS_053_LSB */ "", 63349 /* NS_GDPLL_INPUT_ARRAY_TS_053_MSB */ "", 63350 /* NS_GDPLL_INPUT_ARRAY_TS_054_LSB */ "", 63351 /* NS_GDPLL_INPUT_ARRAY_TS_054_MSB */ "", 63352 /* NS_GDPLL_INPUT_ARRAY_TS_055_LSB */ "", 63353 /* NS_GDPLL_INPUT_ARRAY_TS_055_MSB */ "", 63354 /* NS_GDPLL_INPUT_ARRAY_TS_056_LSB */ "", 63355 /* NS_GDPLL_INPUT_ARRAY_TS_056_MSB */ "", 63356 /* NS_GDPLL_INPUT_ARRAY_TS_057_LSB */ "", 63357 /* NS_GDPLL_INPUT_ARRAY_TS_057_MSB */ "", 63358 /* NS_GDPLL_INPUT_ARRAY_TS_058_LSB */ "", 63359 /* NS_GDPLL_INPUT_ARRAY_TS_058_MSB */ "", 63360 /* NS_GDPLL_INPUT_ARRAY_TS_059_LSB */ "", 63361 /* NS_GDPLL_INPUT_ARRAY_TS_059_MSB */ "", 63362 /* NS_GDPLL_INPUT_ARRAY_TS_060_LSB */ "", 63363 /* NS_GDPLL_INPUT_ARRAY_TS_060_MSB */ "", 63364 /* NS_GDPLL_INPUT_ARRAY_TS_061_LSB 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63468 /* NS_GDPLL_INPUT_ARRAY_TS_113_LSB */ "", 63469 /* NS_GDPLL_INPUT_ARRAY_TS_113_MSB */ "", 63470 /* NS_GDPLL_INPUT_ARRAY_TS_114_LSB */ "", 63471 /* NS_GDPLL_INPUT_ARRAY_TS_114_MSB */ "", 63472 /* NS_GDPLL_INPUT_ARRAY_TS_115_LSB */ "", 63473 /* NS_GDPLL_INPUT_ARRAY_TS_115_MSB */ "", 63474 /* NS_GDPLL_INPUT_ARRAY_TS_116_LSB */ "", 63475 /* NS_GDPLL_INPUT_ARRAY_TS_116_MSB */ "", 63476 /* NS_GDPLL_INPUT_ARRAY_TS_117_LSB */ "", 63477 /* NS_GDPLL_INPUT_ARRAY_TS_117_MSB */ "", 63478 /* NS_GDPLL_INPUT_ARRAY_TS_118_LSB */ "", 63479 /* NS_GDPLL_INPUT_ARRAY_TS_118_MSB */ "", 63480 /* NS_GDPLL_INPUT_ARRAY_TS_119_LSB */ "", 63481 /* NS_GDPLL_INPUT_ARRAY_TS_119_MSB */ "", 63482 /* NS_GDPLL_INPUT_ARRAY_TS_120_LSB */ "", 63483 /* NS_GDPLL_INPUT_ARRAY_TS_120_MSB */ "", 63484 /* NS_GDPLL_INPUT_ARRAY_TS_121_LSB */ "", 63485 /* NS_GDPLL_INPUT_ARRAY_TS_121_MSB */ "", 63486 /* NS_GDPLL_INPUT_ARRAY_TS_122_LSB */ "", 63487 /* NS_GDPLL_INPUT_ARRAY_TS_122_MSB */ "", 63488 /* NS_GDPLL_INPUT_ARRAY_TS_123_LSB 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63530 /* NS_GDPLL_INPUT_ARRAY_TS_144_LSB */ "", 63531 /* NS_GDPLL_INPUT_ARRAY_TS_144_MSB */ "", 63532 /* NS_GDPLL_INPUT_ARRAY_TS_145_LSB */ "", 63533 /* NS_GDPLL_INPUT_ARRAY_TS_145_MSB */ "", 63534 /* NS_GDPLL_INPUT_ARRAY_TS_146_LSB */ "", 63535 /* NS_GDPLL_INPUT_ARRAY_TS_146_MSB */ "", 63536 /* NS_GDPLL_INPUT_ARRAY_TS_147_LSB */ "", 63537 /* NS_GDPLL_INPUT_ARRAY_TS_147_MSB */ "", 63538 /* NS_GDPLL_INPUT_ARRAY_TS_148_LSB */ "", 63539 /* NS_GDPLL_INPUT_ARRAY_TS_148_MSB */ "", 63540 /* NS_GDPLL_INPUT_ARRAY_TS_149_LSB */ "", 63541 /* NS_GDPLL_INPUT_ARRAY_TS_149_MSB */ "", 63542 /* NS_GDPLL_INPUT_ARRAY_TS_150_LSB */ "", 63543 /* NS_GDPLL_INPUT_ARRAY_TS_150_MSB */ "", 63544 /* NS_GDPLL_INPUT_ARRAY_TS_151_LSB */ "", 63545 /* NS_GDPLL_INPUT_ARRAY_TS_151_MSB */ "", 63546 /* NS_GDPLL_INPUT_ARRAY_TS_152_LSB */ "", 63547 /* NS_GDPLL_INPUT_ARRAY_TS_152_MSB */ "", 63548 /* NS_GDPLL_INPUT_ARRAY_TS_153_LSB */ "", 63549 /* NS_GDPLL_INPUT_ARRAY_TS_153_MSB */ "", 63550 /* NS_GDPLL_INPUT_ARRAY_TS_154_LSB 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63592 /* NS_GDPLL_INPUT_ARRAY_TS_175_LSB */ "", 63593 /* NS_GDPLL_INPUT_ARRAY_TS_175_MSB */ "", 63594 /* NS_GDPLL_INPUT_ARRAY_TS_176_LSB */ "", 63595 /* NS_GDPLL_INPUT_ARRAY_TS_176_MSB */ "", 63596 /* NS_GDPLL_INPUT_ARRAY_TS_177_LSB */ "", 63597 /* NS_GDPLL_INPUT_ARRAY_TS_177_MSB */ "", 63598 /* NS_GDPLL_INPUT_ARRAY_TS_178_LSB */ "", 63599 /* NS_GDPLL_INPUT_ARRAY_TS_178_MSB */ "", 63600 /* NS_GDPLL_INPUT_ARRAY_TS_179_LSB */ "", 63601 /* NS_GDPLL_INPUT_ARRAY_TS_179_MSB */ "", 63602 /* NS_GDPLL_INPUT_ARRAY_TS_180_LSB */ "", 63603 /* NS_GDPLL_INPUT_ARRAY_TS_180_MSB */ "", 63604 /* NS_GDPLL_INPUT_ARRAY_TS_181_LSB */ "", 63605 /* NS_GDPLL_INPUT_ARRAY_TS_181_MSB */ "", 63606 /* NS_GDPLL_INPUT_ARRAY_TS_182_LSB */ "", 63607 /* NS_GDPLL_INPUT_ARRAY_TS_182_MSB */ "", 63608 /* NS_GDPLL_INPUT_ARRAY_TS_183_LSB */ "", 63609 /* NS_GDPLL_INPUT_ARRAY_TS_183_MSB */ "", 63610 /* NS_GDPLL_INPUT_ARRAY_TS_184_LSB */ "", 63611 /* NS_GDPLL_INPUT_ARRAY_TS_184_MSB */ "", 63612 /* NS_GDPLL_INPUT_ARRAY_TS_185_LSB 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63654 /* NS_GDPLL_INPUT_ARRAY_TS_206_LSB */ "", 63655 /* NS_GDPLL_INPUT_ARRAY_TS_206_MSB */ "", 63656 /* NS_GDPLL_INPUT_ARRAY_TS_207_LSB */ "", 63657 /* NS_GDPLL_INPUT_ARRAY_TS_207_MSB */ "", 63658 /* NS_GDPLL_INPUT_ARRAY_TS_208_LSB */ "", 63659 /* NS_GDPLL_INPUT_ARRAY_TS_208_MSB */ "", 63660 /* NS_GDPLL_INPUT_ARRAY_TS_209_LSB */ "", 63661 /* NS_GDPLL_INPUT_ARRAY_TS_209_MSB */ "", 63662 /* NS_GDPLL_INPUT_ARRAY_TS_210_LSB */ "", 63663 /* NS_GDPLL_INPUT_ARRAY_TS_210_MSB */ "", 63664 /* NS_GDPLL_INPUT_ARRAY_TS_211_LSB */ "", 63665 /* NS_GDPLL_INPUT_ARRAY_TS_211_MSB */ "", 63666 /* NS_GDPLL_INPUT_ARRAY_TS_212_LSB */ "", 63667 /* NS_GDPLL_INPUT_ARRAY_TS_212_MSB */ "", 63668 /* NS_GDPLL_INPUT_ARRAY_TS_213_LSB */ "", 63669 /* NS_GDPLL_INPUT_ARRAY_TS_213_MSB */ "", 63670 /* NS_GDPLL_INPUT_ARRAY_TS_214_LSB */ "", 63671 /* NS_GDPLL_INPUT_ARRAY_TS_214_MSB */ "", 63672 /* NS_GDPLL_INPUT_ARRAY_TS_215_LSB */ "", 63673 /* NS_GDPLL_INPUT_ARRAY_TS_215_MSB */ "", 63674 /* NS_GDPLL_INPUT_ARRAY_TS_216_LSB */ "", 63675 /* NS_GDPLL_INPUT_ARRAY_TS_216_MSB */ "", 63676 /* NS_GDPLL_INPUT_ARRAY_TS_217_LSB */ "", 63677 /* NS_GDPLL_INPUT_ARRAY_TS_217_MSB */ "", 63678 /* NS_GDPLL_INPUT_ARRAY_TS_218_LSB */ "", 63679 /* NS_GDPLL_INPUT_ARRAY_TS_218_MSB */ "", 63680 /* NS_GDPLL_INPUT_ARRAY_TS_219_LSB */ "", 63681 /* NS_GDPLL_INPUT_ARRAY_TS_219_MSB */ "", 63682 /* NS_GDPLL_INPUT_ARRAY_TS_220_LSB */ "", 63683 /* NS_GDPLL_INPUT_ARRAY_TS_220_MSB */ "", 63684 /* NS_GDPLL_INPUT_ARRAY_TS_221_LSB */ "", 63685 /* NS_GDPLL_INPUT_ARRAY_TS_221_MSB */ "", 63686 /* NS_GDPLL_INPUT_ARRAY_TS_222_LSB */ "", 63687 /* NS_GDPLL_INPUT_ARRAY_TS_222_MSB */ "", 63688 /* NS_GDPLL_INPUT_ARRAY_TS_223_LSB */ "", 63689 /* NS_GDPLL_INPUT_ARRAY_TS_223_MSB */ "", 63690 /* NS_GDPLL_INPUT_ARRAY_TS_224_LSB */ "", 63691 /* NS_GDPLL_INPUT_ARRAY_TS_224_MSB */ "", 63692 /* NS_GDPLL_INPUT_ARRAY_TS_225_LSB */ "", 63693 /* NS_GDPLL_INPUT_ARRAY_TS_225_MSB */ "", 63694 /* NS_GDPLL_INPUT_ARRAY_TS_226_LSB */ "", 63695 /* NS_GDPLL_INPUT_ARRAY_TS_226_MSB */ "", 63696 /* NS_GDPLL_INPUT_ARRAY_TS_227_LSB */ "", 63697 /* NS_GDPLL_INPUT_ARRAY_TS_227_MSB */ "", 63698 /* NS_GDPLL_INPUT_ARRAY_TS_228_LSB */ "", 63699 /* NS_GDPLL_INPUT_ARRAY_TS_228_MSB */ "", 63700 /* NS_GDPLL_INPUT_ARRAY_TS_229_LSB */ "", 63701 /* NS_GDPLL_INPUT_ARRAY_TS_229_MSB */ "", 63702 /* NS_GDPLL_INPUT_ARRAY_TS_230_LSB */ "", 63703 /* NS_GDPLL_INPUT_ARRAY_TS_230_MSB */ "", 63704 /* NS_GDPLL_INPUT_ARRAY_TS_231_LSB */ "", 63705 /* NS_GDPLL_INPUT_ARRAY_TS_231_MSB */ "", 63706 /* NS_GDPLL_INPUT_ARRAY_TS_232_LSB */ "", 63707 /* NS_GDPLL_INPUT_ARRAY_TS_232_MSB */ "", 63708 /* NS_GDPLL_INPUT_ARRAY_TS_233_LSB */ "", 63709 /* NS_GDPLL_INPUT_ARRAY_TS_233_MSB */ "", 63710 /* NS_GDPLL_INPUT_ARRAY_TS_234_LSB */ "", 63711 /* NS_GDPLL_INPUT_ARRAY_TS_234_MSB */ "", 63712 /* NS_GDPLL_INPUT_ARRAY_TS_235_LSB */ "", 63713 /* NS_GDPLL_INPUT_ARRAY_TS_235_MSB */ "", 63714 /* NS_GDPLL_INPUT_ARRAY_TS_236_LSB */ "", 63715 /* NS_GDPLL_INPUT_ARRAY_TS_236_MSB */ "", 63716 /* NS_GDPLL_INPUT_ARRAY_TS_237_LSB */ "", 63717 /* NS_GDPLL_INPUT_ARRAY_TS_237_MSB */ "", 63718 /* NS_GDPLL_INPUT_ARRAY_TS_238_LSB */ "", 63719 /* NS_GDPLL_INPUT_ARRAY_TS_238_MSB */ "", 63720 /* NS_GDPLL_INPUT_ARRAY_TS_239_LSB */ "", 63721 /* NS_GDPLL_INPUT_ARRAY_TS_239_MSB */ "", 63722 /* NS_GDPLL_INPUT_ARRAY_TS_240_LSB */ "", 63723 /* NS_GDPLL_INPUT_ARRAY_TS_240_MSB */ "", 63724 /* NS_GDPLL_INPUT_ARRAY_TS_241_LSB */ "", 63725 /* NS_GDPLL_INPUT_ARRAY_TS_241_MSB */ "", 63726 /* NS_GDPLL_INPUT_ARRAY_TS_242_LSB */ "", 63727 /* NS_GDPLL_INPUT_ARRAY_TS_242_MSB */ "", 63728 /* NS_GDPLL_INPUT_ARRAY_TS_243_LSB */ "", 63729 /* NS_GDPLL_INPUT_ARRAY_TS_243_MSB */ "", 63730 /* NS_GDPLL_INPUT_ARRAY_TS_244_LSB */ "", 63731 /* NS_GDPLL_INPUT_ARRAY_TS_244_MSB */ "", 63732 /* NS_GDPLL_INPUT_ARRAY_TS_245_LSB */ "", 63733 /* NS_GDPLL_INPUT_ARRAY_TS_245_MSB */ "", 63734 /* NS_GDPLL_INPUT_ARRAY_TS_246_LSB */ "", 63735 /* NS_GDPLL_INPUT_ARRAY_TS_246_MSB */ "", 63736 /* NS_GDPLL_INPUT_ARRAY_TS_247_LSB */ "", 63737 /* NS_GDPLL_INPUT_ARRAY_TS_247_MSB */ "", 63738 /* NS_GDPLL_INPUT_ARRAY_TS_248_LSB */ "", 63739 /* NS_GDPLL_INPUT_ARRAY_TS_248_MSB */ "", 63740 /* NS_GDPLL_INPUT_ARRAY_TS_249_LSB */ "", 63741 /* NS_GDPLL_INPUT_ARRAY_TS_249_MSB */ "", 63742 /* NS_GDPLL_INPUT_ARRAY_TS_250_LSB */ "", 63743 /* NS_GDPLL_INPUT_ARRAY_TS_250_MSB */ "", 63744 /* NS_GDPLL_INPUT_ARRAY_TS_251_LSB */ "", 63745 /* NS_GDPLL_INPUT_ARRAY_TS_251_MSB */ "", 63746 /* NS_GDPLL_INPUT_ARRAY_TS_252_LSB */ "", 63747 /* NS_GDPLL_INPUT_ARRAY_TS_252_MSB */ "", 63748 /* NS_GDPLL_INPUT_ARRAY_TS_253_LSB */ "", 63749 /* NS_GDPLL_INPUT_ARRAY_TS_253_MSB */ "", 63750 /* NS_GDPLL_INPUT_ARRAY_TS_254_LSB */ "", 63751 /* NS_GDPLL_INPUT_ARRAY_TS_254_MSB */ "", 63752 /* NS_GDPLL_INPUT_ARRAY_TS_255_LSB */ "", 63753 /* NS_GDPLL_INPUT_ARRAY_TS_255_MSB */ "", 63754 /* NS_GDPLL_M7_CORE_INT_ENABLE */ "", 63755 /* NS_GDPLL_M7_CORE_INT_STATUS */ "", 63756 /* NS_GDPLL_M7_ERROR_INFO */ "", 63757 /* NS_GDPLL_M7_ERROR_INFO_INT */ "", 63758 /* NS_GDPLL_M7_TCM_1B_ECC_STATUS */ "", 63759 /* NS_GDPLL_M7_TCM_2B_ECC_INT_ENABLE */ "", 63760 /* NS_GDPLL_M7_TCM_2B_ECC_INT_STATUS */ "", 63761 /* NS_GDPLL_NCO_MEM_ECC_CONTROL */ "", 63762 /* NS_GDPLL_NCO_MEM_ECC_STATUS */ "", 63763 /* NS_GDPLL_NCO_MEM_TM_CONTROL */ "", 63764 /* NS_GDPLL_NCO_OUT_ENABLE0 */ "", 63765 /* NS_GDPLL_NCO_OUT_ENABLE1 */ "", 63766 /* NS_GDPLL_NCO_OUT_ENABLE2 */ "", 63767 /* NS_GDPLL_NCO_OUT_ENABLE3 */ "", 63768 /* NS_GDPLL_NCO_OUT_STATUS0 */ "", 63769 /* NS_GDPLL_NCO_OUT_STATUS1 */ "", 63770 /* NS_GDPLL_NCO_OUT_STATUS2 */ "", 63771 /* NS_GDPLL_NCO_OUT_STATUS3 */ "", 63772 /* NS_GDPLL_NCO_OVERLOAD_STATUS0 */ "", 63773 /* NS_GDPLL_NCO_OVERLOAD_STATUS1 */ "", 63774 /* NS_GDPLL_NCO_OVERLOAD_STATUS2 */ "", 63775 /* NS_GDPLL_NCO_OVERLOAD_STATUS3 */ "", 63776 /* NS_GDPLL_NCO_UPDATE_COMMON_CONTROL */ "", 63777 /* NS_GDPLL_NCO_UPDATE_CONTROL */ "", 63778 /* NS_GDPLL_OUTPUT_ARRAY_000_LSB */ "", 63779 /* NS_GDPLL_OUTPUT_ARRAY_000_MSB */ "", 63780 /* NS_GDPLL_OUTPUT_ARRAY_001_LSB */ "", 63781 /* NS_GDPLL_OUTPUT_ARRAY_001_MSB */ "", 63782 /* NS_GDPLL_OUTPUT_ARRAY_002_LSB */ "", 63783 /* NS_GDPLL_OUTPUT_ARRAY_002_MSB */ "", 63784 /* NS_GDPLL_OUTPUT_ARRAY_003_LSB */ "", 63785 /* NS_GDPLL_OUTPUT_ARRAY_003_MSB */ "", 63786 /* NS_GDPLL_OUTPUT_ARRAY_004_LSB */ "", 63787 /* NS_GDPLL_OUTPUT_ARRAY_004_MSB */ "", 63788 /* NS_GDPLL_OUTPUT_ARRAY_005_LSB */ "", 63789 /* NS_GDPLL_OUTPUT_ARRAY_005_MSB */ "", 63790 /* NS_GDPLL_OUTPUT_ARRAY_006_LSB */ "", 63791 /* NS_GDPLL_OUTPUT_ARRAY_006_MSB */ "", 63792 /* NS_GDPLL_OUTPUT_ARRAY_007_LSB */ "", 63793 /* NS_GDPLL_OUTPUT_ARRAY_007_MSB */ "", 63794 /* NS_GDPLL_OUTPUT_ARRAY_008_LSB */ "", 63795 /* NS_GDPLL_OUTPUT_ARRAY_008_MSB */ "", 63796 /* NS_GDPLL_OUTPUT_ARRAY_009_LSB */ "", 63797 /* NS_GDPLL_OUTPUT_ARRAY_009_MSB */ "", 63798 /* NS_GDPLL_OUTPUT_ARRAY_010_LSB */ "", 63799 /* NS_GDPLL_OUTPUT_ARRAY_010_MSB */ "", 63800 /* NS_GDPLL_OUTPUT_ARRAY_011_LSB */ "", 63801 /* NS_GDPLL_OUTPUT_ARRAY_011_MSB */ "", 63802 /* NS_GDPLL_OUTPUT_ARRAY_012_LSB */ "", 63803 /* NS_GDPLL_OUTPUT_ARRAY_012_MSB */ "", 63804 /* NS_GDPLL_OUTPUT_ARRAY_013_LSB */ "", 63805 /* NS_GDPLL_OUTPUT_ARRAY_013_MSB */ "", 63806 /* NS_GDPLL_OUTPUT_ARRAY_014_LSB */ "", 63807 /* NS_GDPLL_OUTPUT_ARRAY_014_MSB */ "", 63808 /* NS_GDPLL_OUTPUT_ARRAY_015_LSB */ "", 63809 /* NS_GDPLL_OUTPUT_ARRAY_015_MSB */ "", 63810 /* NS_GDPLL_OUTPUT_ARRAY_016_LSB */ "", 63811 /* NS_GDPLL_OUTPUT_ARRAY_016_MSB */ "", 63812 /* NS_GDPLL_OUTPUT_ARRAY_017_LSB */ "", 63813 /* NS_GDPLL_OUTPUT_ARRAY_017_MSB */ "", 63814 /* NS_GDPLL_OUTPUT_ARRAY_018_LSB */ "", 63815 /* NS_GDPLL_OUTPUT_ARRAY_018_MSB */ "", 63816 /* NS_GDPLL_OUTPUT_ARRAY_019_LSB */ "", 63817 /* NS_GDPLL_OUTPUT_ARRAY_019_MSB */ "", 63818 /* NS_GDPLL_OUTPUT_ARRAY_020_LSB */ "", 63819 /* NS_GDPLL_OUTPUT_ARRAY_020_MSB */ "", 63820 /* NS_GDPLL_OUTPUT_ARRAY_021_LSB */ "", 63821 /* NS_GDPLL_OUTPUT_ARRAY_021_MSB */ "", 63822 /* NS_GDPLL_OUTPUT_ARRAY_022_LSB */ "", 63823 /* NS_GDPLL_OUTPUT_ARRAY_022_MSB */ "", 63824 /* NS_GDPLL_OUTPUT_ARRAY_023_LSB */ "", 63825 /* NS_GDPLL_OUTPUT_ARRAY_023_MSB */ "", 63826 /* NS_GDPLL_OUTPUT_ARRAY_024_LSB */ "", 63827 /* NS_GDPLL_OUTPUT_ARRAY_024_MSB */ "", 63828 /* NS_GDPLL_OUTPUT_ARRAY_025_LSB */ "", 63829 /* NS_GDPLL_OUTPUT_ARRAY_025_MSB */ "", 63830 /* NS_GDPLL_OUTPUT_ARRAY_026_LSB */ "", 63831 /* NS_GDPLL_OUTPUT_ARRAY_026_MSB */ "", 63832 /* NS_GDPLL_OUTPUT_ARRAY_027_LSB */ "", 63833 /* NS_GDPLL_OUTPUT_ARRAY_027_MSB */ "", 63834 /* NS_GDPLL_OUTPUT_ARRAY_028_LSB */ "", 63835 /* NS_GDPLL_OUTPUT_ARRAY_028_MSB */ "", 63836 /* NS_GDPLL_OUTPUT_ARRAY_029_LSB */ "", 63837 /* NS_GDPLL_OUTPUT_ARRAY_029_MSB */ "", 63838 /* NS_GDPLL_OUTPUT_ARRAY_030_LSB */ "", 63839 /* NS_GDPLL_OUTPUT_ARRAY_030_MSB */ "", 63840 /* NS_GDPLL_OUTPUT_ARRAY_031_LSB */ "", 63841 /* NS_GDPLL_OUTPUT_ARRAY_031_MSB */ "", 63842 /* NS_GDPLL_OUTPUT_ARRAY_032_LSB */ "", 63843 /* NS_GDPLL_OUTPUT_ARRAY_032_MSB */ "", 63844 /* NS_GDPLL_OUTPUT_ARRAY_033_LSB */ "", 63845 /* NS_GDPLL_OUTPUT_ARRAY_033_MSB */ "", 63846 /* NS_GDPLL_OUTPUT_ARRAY_034_LSB */ "", 63847 /* NS_GDPLL_OUTPUT_ARRAY_034_MSB */ "", 63848 /* NS_GDPLL_OUTPUT_ARRAY_035_LSB */ "", 63849 /* NS_GDPLL_OUTPUT_ARRAY_035_MSB */ "", 63850 /* NS_GDPLL_OUTPUT_ARRAY_036_LSB */ "", 63851 /* NS_GDPLL_OUTPUT_ARRAY_036_MSB */ "", 63852 /* NS_GDPLL_OUTPUT_ARRAY_037_LSB */ "", 63853 /* NS_GDPLL_OUTPUT_ARRAY_037_MSB */ "", 63854 /* NS_GDPLL_OUTPUT_ARRAY_038_LSB */ "", 63855 /* NS_GDPLL_OUTPUT_ARRAY_038_MSB */ "", 63856 /* NS_GDPLL_OUTPUT_ARRAY_039_LSB */ "", 63857 /* NS_GDPLL_OUTPUT_ARRAY_039_MSB */ "", 63858 /* NS_GDPLL_OUTPUT_ARRAY_040_LSB */ "", 63859 /* NS_GDPLL_OUTPUT_ARRAY_040_MSB */ "", 63860 /* NS_GDPLL_OUTPUT_ARRAY_041_LSB */ "", 63861 /* NS_GDPLL_OUTPUT_ARRAY_041_MSB */ "", 63862 /* NS_GDPLL_OUTPUT_ARRAY_042_LSB */ "", 63863 /* NS_GDPLL_OUTPUT_ARRAY_042_MSB */ "", 63864 /* NS_GDPLL_OUTPUT_ARRAY_043_LSB */ "", 63865 /* NS_GDPLL_OUTPUT_ARRAY_043_MSB */ "", 63866 /* NS_GDPLL_OUTPUT_ARRAY_044_LSB */ "", 63867 /* NS_GDPLL_OUTPUT_ARRAY_044_MSB */ "", 63868 /* NS_GDPLL_OUTPUT_ARRAY_045_LSB */ "", 63869 /* NS_GDPLL_OUTPUT_ARRAY_045_MSB */ "", 63870 /* NS_GDPLL_OUTPUT_ARRAY_046_LSB */ "", 63871 /* NS_GDPLL_OUTPUT_ARRAY_046_MSB */ "", 63872 /* NS_GDPLL_OUTPUT_ARRAY_047_LSB */ "", 63873 /* NS_GDPLL_OUTPUT_ARRAY_047_MSB */ "", 63874 /* NS_GDPLL_OUTPUT_ARRAY_048_LSB */ "", 63875 /* NS_GDPLL_OUTPUT_ARRAY_048_MSB */ "", 63876 /* NS_GDPLL_OUTPUT_ARRAY_049_LSB */ "", 63877 /* NS_GDPLL_OUTPUT_ARRAY_049_MSB */ "", 63878 /* NS_GDPLL_OUTPUT_ARRAY_050_LSB */ "", 63879 /* NS_GDPLL_OUTPUT_ARRAY_050_MSB */ "", 63880 /* NS_GDPLL_OUTPUT_ARRAY_051_LSB */ "", 63881 /* NS_GDPLL_OUTPUT_ARRAY_051_MSB */ "", 63882 /* NS_GDPLL_OUTPUT_ARRAY_052_LSB */ "", 63883 /* NS_GDPLL_OUTPUT_ARRAY_052_MSB */ "", 63884 /* NS_GDPLL_OUTPUT_ARRAY_053_LSB */ "", 63885 /* NS_GDPLL_OUTPUT_ARRAY_053_MSB */ "", 63886 /* NS_GDPLL_OUTPUT_ARRAY_054_LSB */ "", 63887 /* NS_GDPLL_OUTPUT_ARRAY_054_MSB */ "", 63888 /* NS_GDPLL_OUTPUT_ARRAY_055_LSB */ "", 63889 /* NS_GDPLL_OUTPUT_ARRAY_055_MSB */ "", 63890 /* NS_GDPLL_OUTPUT_ARRAY_056_LSB */ "", 63891 /* NS_GDPLL_OUTPUT_ARRAY_056_MSB */ "", 63892 /* NS_GDPLL_OUTPUT_ARRAY_057_LSB */ "", 63893 /* NS_GDPLL_OUTPUT_ARRAY_057_MSB */ "", 63894 /* NS_GDPLL_OUTPUT_ARRAY_058_LSB */ "", 63895 /* NS_GDPLL_OUTPUT_ARRAY_058_MSB */ "", 63896 /* NS_GDPLL_OUTPUT_ARRAY_059_LSB */ "", 63897 /* NS_GDPLL_OUTPUT_ARRAY_059_MSB */ "", 63898 /* NS_GDPLL_OUTPUT_ARRAY_060_LSB */ "", 63899 /* NS_GDPLL_OUTPUT_ARRAY_060_MSB */ "", 63900 /* NS_GDPLL_OUTPUT_ARRAY_061_LSB */ "", 63901 /* NS_GDPLL_OUTPUT_ARRAY_061_MSB */ "", 63902 /* NS_GDPLL_OUTPUT_ARRAY_062_LSB */ "", 63903 /* NS_GDPLL_OUTPUT_ARRAY_062_MSB */ "", 63904 /* NS_GDPLL_OUTPUT_ARRAY_063_LSB */ "", 63905 /* NS_GDPLL_OUTPUT_ARRAY_063_MSB */ "", 63906 /* NS_GDPLL_OUTPUT_ARRAY_064_LSB */ "", 63907 /* NS_GDPLL_OUTPUT_ARRAY_064_MSB */ "", 63908 /* NS_GDPLL_OUTPUT_ARRAY_065_LSB */ "", 63909 /* NS_GDPLL_OUTPUT_ARRAY_065_MSB */ "", 63910 /* NS_GDPLL_OUTPUT_ARRAY_066_LSB */ "", 63911 /* NS_GDPLL_OUTPUT_ARRAY_066_MSB */ "", 63912 /* NS_GDPLL_OUTPUT_ARRAY_067_LSB */ "", 63913 /* NS_GDPLL_OUTPUT_ARRAY_067_MSB */ "", 63914 /* NS_GDPLL_OUTPUT_ARRAY_068_LSB */ "", 63915 /* NS_GDPLL_OUTPUT_ARRAY_068_MSB */ "", 63916 /* NS_GDPLL_OUTPUT_ARRAY_069_LSB */ "", 63917 /* NS_GDPLL_OUTPUT_ARRAY_069_MSB */ "", 63918 /* NS_GDPLL_OUTPUT_ARRAY_070_LSB */ "", 63919 /* NS_GDPLL_OUTPUT_ARRAY_070_MSB */ "", 63920 /* NS_GDPLL_OUTPUT_ARRAY_071_LSB */ "", 63921 /* NS_GDPLL_OUTPUT_ARRAY_071_MSB */ "", 63922 /* NS_GDPLL_OUTPUT_ARRAY_072_LSB */ "", 63923 /* NS_GDPLL_OUTPUT_ARRAY_072_MSB */ "", 63924 /* NS_GDPLL_OUTPUT_ARRAY_073_LSB */ "", 63925 /* NS_GDPLL_OUTPUT_ARRAY_073_MSB */ "", 63926 /* NS_GDPLL_OUTPUT_ARRAY_074_LSB */ "", 63927 /* NS_GDPLL_OUTPUT_ARRAY_074_MSB */ "", 63928 /* NS_GDPLL_OUTPUT_ARRAY_075_LSB */ "", 63929 /* NS_GDPLL_OUTPUT_ARRAY_075_MSB */ "", 63930 /* NS_GDPLL_OUTPUT_ARRAY_076_LSB */ "", 63931 /* NS_GDPLL_OUTPUT_ARRAY_076_MSB */ "", 63932 /* NS_GDPLL_OUTPUT_ARRAY_077_LSB */ "", 63933 /* NS_GDPLL_OUTPUT_ARRAY_077_MSB */ "", 63934 /* NS_GDPLL_OUTPUT_ARRAY_078_LSB */ "", 63935 /* NS_GDPLL_OUTPUT_ARRAY_078_MSB */ "", 63936 /* NS_GDPLL_OUTPUT_ARRAY_079_LSB */ "", 63937 /* NS_GDPLL_OUTPUT_ARRAY_079_MSB */ "", 63938 /* NS_GDPLL_OUTPUT_ARRAY_080_LSB */ "", 63939 /* NS_GDPLL_OUTPUT_ARRAY_080_MSB */ "", 63940 /* NS_GDPLL_OUTPUT_ARRAY_081_LSB */ "", 63941 /* NS_GDPLL_OUTPUT_ARRAY_081_MSB */ "", 63942 /* NS_GDPLL_OUTPUT_ARRAY_082_LSB */ "", 63943 /* NS_GDPLL_OUTPUT_ARRAY_082_MSB */ "", 63944 /* NS_GDPLL_OUTPUT_ARRAY_083_LSB */ "", 63945 /* NS_GDPLL_OUTPUT_ARRAY_083_MSB */ "", 63946 /* NS_GDPLL_OUTPUT_ARRAY_084_LSB */ "", 63947 /* NS_GDPLL_OUTPUT_ARRAY_084_MSB */ "", 63948 /* NS_GDPLL_OUTPUT_ARRAY_085_LSB */ "", 63949 /* NS_GDPLL_OUTPUT_ARRAY_085_MSB */ "", 63950 /* NS_GDPLL_OUTPUT_ARRAY_086_LSB */ "", 63951 /* NS_GDPLL_OUTPUT_ARRAY_086_MSB */ "", 63952 /* NS_GDPLL_OUTPUT_ARRAY_087_LSB */ "", 63953 /* NS_GDPLL_OUTPUT_ARRAY_087_MSB */ "", 63954 /* NS_GDPLL_OUTPUT_ARRAY_088_LSB */ "", 63955 /* NS_GDPLL_OUTPUT_ARRAY_088_MSB */ "", 63956 /* NS_GDPLL_OUTPUT_ARRAY_089_LSB */ "", 63957 /* NS_GDPLL_OUTPUT_ARRAY_089_MSB */ "", 63958 /* NS_GDPLL_OUTPUT_ARRAY_090_LSB */ "", 63959 /* NS_GDPLL_OUTPUT_ARRAY_090_MSB */ "", 63960 /* NS_GDPLL_OUTPUT_ARRAY_091_LSB */ "", 63961 /* NS_GDPLL_OUTPUT_ARRAY_091_MSB */ "", 63962 /* NS_GDPLL_OUTPUT_ARRAY_092_LSB */ "", 63963 /* NS_GDPLL_OUTPUT_ARRAY_092_MSB */ "", 63964 /* NS_GDPLL_OUTPUT_ARRAY_093_LSB */ "", 63965 /* NS_GDPLL_OUTPUT_ARRAY_093_MSB */ "", 63966 /* NS_GDPLL_OUTPUT_ARRAY_094_LSB */ "", 63967 /* NS_GDPLL_OUTPUT_ARRAY_094_MSB */ "", 63968 /* NS_GDPLL_OUTPUT_ARRAY_095_LSB */ "", 63969 /* NS_GDPLL_OUTPUT_ARRAY_095_MSB */ "", 63970 /* NS_GDPLL_OUTPUT_ARRAY_096_LSB */ "", 63971 /* NS_GDPLL_OUTPUT_ARRAY_096_MSB */ "", 63972 /* NS_GDPLL_OUTPUT_ARRAY_097_LSB */ "", 63973 /* NS_GDPLL_OUTPUT_ARRAY_097_MSB */ "", 63974 /* NS_GDPLL_OUTPUT_ARRAY_098_LSB */ "", 63975 /* NS_GDPLL_OUTPUT_ARRAY_098_MSB */ "", 63976 /* NS_GDPLL_OUTPUT_ARRAY_099_LSB */ "", 63977 /* NS_GDPLL_OUTPUT_ARRAY_099_MSB */ "", 63978 /* NS_GDPLL_OUTPUT_ARRAY_100_LSB */ "", 63979 /* NS_GDPLL_OUTPUT_ARRAY_100_MSB */ "", 63980 /* NS_GDPLL_OUTPUT_ARRAY_101_LSB */ "", 63981 /* NS_GDPLL_OUTPUT_ARRAY_101_MSB */ "", 63982 /* NS_GDPLL_OUTPUT_ARRAY_102_LSB */ "", 63983 /* NS_GDPLL_OUTPUT_ARRAY_102_MSB */ "", 63984 /* NS_GDPLL_OUTPUT_ARRAY_103_LSB */ "", 63985 /* NS_GDPLL_OUTPUT_ARRAY_103_MSB */ "", 63986 /* NS_GDPLL_OUTPUT_ARRAY_104_LSB */ "", 63987 /* NS_GDPLL_OUTPUT_ARRAY_104_MSB */ "", 63988 /* NS_GDPLL_OUTPUT_ARRAY_105_LSB */ "", 63989 /* NS_GDPLL_OUTPUT_ARRAY_105_MSB */ "", 63990 /* NS_GDPLL_OUTPUT_ARRAY_106_LSB */ "", 63991 /* NS_GDPLL_OUTPUT_ARRAY_106_MSB */ "", 63992 /* NS_GDPLL_OUTPUT_ARRAY_107_LSB */ "", 63993 /* NS_GDPLL_OUTPUT_ARRAY_107_MSB */ "", 63994 /* NS_GDPLL_OUTPUT_ARRAY_108_LSB */ "", 63995 /* NS_GDPLL_OUTPUT_ARRAY_108_MSB */ "", 63996 /* NS_GDPLL_OUTPUT_ARRAY_109_LSB */ "", 63997 /* NS_GDPLL_OUTPUT_ARRAY_109_MSB */ "", 63998 /* NS_GDPLL_OUTPUT_ARRAY_110_LSB */ "", 63999 /* NS_GDPLL_OUTPUT_ARRAY_110_MSB */ "", 64000 /* NS_GDPLL_OUTPUT_ARRAY_111_LSB */ "", 64001 /* NS_GDPLL_OUTPUT_ARRAY_111_MSB */ "", 64002 /* NS_GDPLL_OUTPUT_ARRAY_112_LSB */ "", 64003 /* NS_GDPLL_OUTPUT_ARRAY_112_MSB */ "", 64004 /* NS_GDPLL_OUTPUT_ARRAY_113_LSB */ "", 64005 /* NS_GDPLL_OUTPUT_ARRAY_113_MSB */ "", 64006 /* NS_GDPLL_OUTPUT_ARRAY_114_LSB */ "", 64007 /* NS_GDPLL_OUTPUT_ARRAY_114_MSB */ "", 64008 /* NS_GDPLL_OUTPUT_ARRAY_115_LSB */ "", 64009 /* NS_GDPLL_OUTPUT_ARRAY_115_MSB */ "", 64010 /* NS_GDPLL_OUTPUT_ARRAY_116_LSB */ "", 64011 /* NS_GDPLL_OUTPUT_ARRAY_116_MSB */ "", 64012 /* NS_GDPLL_OUTPUT_ARRAY_117_LSB */ "", 64013 /* NS_GDPLL_OUTPUT_ARRAY_117_MSB */ "", 64014 /* NS_GDPLL_OUTPUT_ARRAY_118_LSB */ "", 64015 /* NS_GDPLL_OUTPUT_ARRAY_118_MSB */ "", 64016 /* NS_GDPLL_OUTPUT_ARRAY_119_LSB */ "", 64017 /* NS_GDPLL_OUTPUT_ARRAY_119_MSB */ "", 64018 /* NS_GDPLL_OUTPUT_ARRAY_120_LSB */ "", 64019 /* NS_GDPLL_OUTPUT_ARRAY_120_MSB */ "", 64020 /* NS_GDPLL_OUTPUT_ARRAY_121_LSB */ "", 64021 /* NS_GDPLL_OUTPUT_ARRAY_121_MSB */ "", 64022 /* NS_GDPLL_OUTPUT_ARRAY_122_LSB */ "", 64023 /* NS_GDPLL_OUTPUT_ARRAY_122_MSB */ "", 64024 /* NS_GDPLL_OUTPUT_ARRAY_123_LSB */ "", 64025 /* NS_GDPLL_OUTPUT_ARRAY_123_MSB */ "", 64026 /* NS_GDPLL_OUTPUT_ARRAY_124_LSB */ "", 64027 /* NS_GDPLL_OUTPUT_ARRAY_124_MSB */ "", 64028 /* NS_GDPLL_OUTPUT_ARRAY_125_LSB */ "", 64029 /* NS_GDPLL_OUTPUT_ARRAY_125_MSB */ "", 64030 /* NS_GDPLL_OUTPUT_ARRAY_126_LSB */ "", 64031 /* NS_GDPLL_OUTPUT_ARRAY_126_MSB */ "", 64032 /* NS_GDPLL_OUTPUT_ARRAY_127_LSB */ "", 64033 /* NS_GDPLL_OUTPUT_ARRAY_127_MSB */ "", 64034 /* NS_GDPLL_TRIGGER_ACK */ "", 64035 /* NS_GDPLL_TRIGGER_FB_TS_LOWER */ "", 64036 /* NS_GDPLL_TRIGGER_FB_TS_UPPER */ "", 64037 /* NS_GDPLL_TRIGGER_REF_TS_LOWER */ "", 64038 /* NS_GDPLL_TRIGGER_REF_TS_UPPER */ "", 64039 /* NS_GDPLL_TRIGGER_UPDATE */ "", 64040 /* NS_GDPLL_WTCHDG_MEM_ECC_CONTROL */ "", 64041 /* NS_GDPLL_WTCHDG_MEM_ECC_STATUS */ "", 64042 /* NS_GDPLL_WTCHDG_MEM_TM_CONTROL */ "", 64043 /* NS_IA_SRC_FREQ_PPM_CHK_PROFILE_NOMINAL */ "", 64044 /* NS_IA_SRC_FREQ_PPM_CHK_PROFILE_VARIATION */ "", 64045 /* NS_MISC_CLK_EVENT_CTRL */ "", 64046 /* NS_MISC_EVENT_OVRD_STATUS */ "", 64047 /* NS_MISC_EVENT_STATUS */ "", 64048 /* NS_ROE_TS_INT_ENABLE */ "", 64049 /* NS_ROE_TS_INT_STATUS */ "", 64050 /* NS_RX_CDR_EVENT_OVRD_STATUS0 */ "", 64051 /* NS_RX_CDR_EVENT_OVRD_STATUS1 */ "", 64052 /* NS_RX_CDR_EVENT_STATUS0 */ "", 64053 /* NS_RX_CDR_EVENT_STATUS1 */ "", 64054 /* NS_TIMESYNC_COUNTER_CONFIG_SELECT */ "", 64055 /* NS_TIMESYNC_GPIO_0_CTRL */ "", 64056 /* NS_TIMESYNC_GPIO_0_DOWN_EVENT_CTRL */ "", 64057 /* NS_TIMESYNC_GPIO_0_OUTPUT_ENABLE */ "", 64058 /* NS_TIMESYNC_GPIO_0_PHASE_ADJUST_LOWER */ "", 64059 /* NS_TIMESYNC_GPIO_0_PHASE_ADJUST_UPPER */ "", 64060 /* NS_TIMESYNC_GPIO_0_UP_EVENT_CTRL */ "", 64061 /* NS_TIMESYNC_GPIO_1_CTRL */ "", 64062 /* NS_TIMESYNC_GPIO_1_DOWN_EVENT_CTRL */ "", 64063 /* NS_TIMESYNC_GPIO_1_OUTPUT_ENABLE */ "", 64064 /* NS_TIMESYNC_GPIO_1_PHASE_ADJUST_LOWER */ "", 64065 /* NS_TIMESYNC_GPIO_1_PHASE_ADJUST_UPPER */ "", 64066 /* NS_TIMESYNC_GPIO_1_UP_EVENT_CTRL */ "", 64067 /* NS_TIMESYNC_GPIO_2_CTRL */ "", 64068 /* NS_TIMESYNC_GPIO_2_DOWN_EVENT_CTRL */ "", 64069 /* NS_TIMESYNC_GPIO_2_OUTPUT_ENABLE */ "", 64070 /* NS_TIMESYNC_GPIO_2_PHASE_ADJUST_LOWER */ "", 64071 /* NS_TIMESYNC_GPIO_2_PHASE_ADJUST_UPPER */ "", 64072 /* NS_TIMESYNC_GPIO_2_UP_EVENT_CTRL */ "", 64073 /* NS_TIMESYNC_GPIO_3_CTRL */ "", 64074 /* NS_TIMESYNC_GPIO_3_DOWN_EVENT_CTRL */ "", 64075 /* NS_TIMESYNC_GPIO_3_OUTPUT_ENABLE */ "", 64076 /* NS_TIMESYNC_GPIO_3_PHASE_ADJUST_LOWER */ "", 64077 /* NS_TIMESYNC_GPIO_3_PHASE_ADJUST_UPPER */ "", 64078 /* NS_TIMESYNC_GPIO_3_UP_EVENT_CTRL */ "", 64079 /* NS_TIMESYNC_GPIO_4_CTRL */ "", 64080 /* NS_TIMESYNC_GPIO_4_DOWN_EVENT_CTRL */ "", 64081 /* NS_TIMESYNC_GPIO_4_OUTPUT_ENABLE */ "", 64082 /* NS_TIMESYNC_GPIO_4_PHASE_ADJUST_LOWER */ "", 64083 /* NS_TIMESYNC_GPIO_4_PHASE_ADJUST_UPPER */ "", 64084 /* NS_TIMESYNC_GPIO_4_UP_EVENT_CTRL */ "", 64085 /* NS_TIMESYNC_GPIO_5_CTRL */ "", 64086 /* NS_TIMESYNC_GPIO_5_DOWN_EVENT_CTRL */ "", 64087 /* NS_TIMESYNC_GPIO_5_OUTPUT_ENABLE */ "", 64088 /* NS_TIMESYNC_GPIO_5_PHASE_ADJUST_LOWER */ "", 64089 /* NS_TIMESYNC_GPIO_5_PHASE_ADJUST_UPPER */ "", 64090 /* NS_TIMESYNC_GPIO_5_UP_EVENT_CTRL */ "", 64091 /* NS_TIMESYNC_INPUT_TIME_FIFO_STATUS */ "", 64092 /* NS_TIMESYNC_INPUT_TIME_FIFO_TS_0 */ "", 64093 /* NS_TIMESYNC_INPUT_TIME_FIFO_TS_1 */ "", 64094 /* NS_TIMESYNC_INPUT_TIME_FIFO_TS_2 */ "", 64095 /* NS_TIMESYNC_INPUT_TIME_FIFO_TS_3 */ "", 64096 /* NS_TIMESYNC_MAPPER_FWD_CFG */ "", 64097 /* NS_TIMESYNC_MAPPER_PORT_ENABLE_0 */ "", 64098 /* NS_TIMESYNC_MAPPER_PORT_ENABLE_1 */ "", 64099 /* NS_TIMESYNC_MAPPER_PORT_ENABLE_2 */ "", 64100 /* NS_TIMESYNC_MAPPER_PORT_ENABLE_3 */ "", 64101 /* NS_TIMESYNC_MAPPER_RX_TYPE0_OVRD_STATUS */ "", 64102 /* NS_TIMESYNC_MAPPER_RX_TYPE0_STATUS */ "", 64103 /* NS_TIMESYNC_MAPPER_RX_TYPE1_OVRD_STATUS */ "", 64104 /* NS_TIMESYNC_MAPPER_RX_TYPE1_STATUS */ "", 64105 /* NS_TIMESYNC_MAPPER_RX_TYPE2_OVRD_STATUS */ "", 64106 /* NS_TIMESYNC_MAPPER_RX_TYPE2_STATUS */ "", 64107 /* NS_TIMESYNC_MAPPER_TYPE2_FORMAT */ "", 64108 /* NS_TIMESYNC_ROE_MAX_DELTA */ "", 64109 /* NS_TIMESYNC_RX_CDR_EVENT_CTRL */ "", 64110 /* NS_TIMESYNC_SERDES_LCPLL_EVENT_CTRL */ "", 64111 /* NS_TIMESYNC_TS0_ACCUMULATOR_0 */ "", 64112 /* NS_TIMESYNC_TS0_ACCUMULATOR_1 */ "", 64113 /* NS_TIMESYNC_TS0_ACCUMULATOR_2 */ "", 64114 /* NS_TIMESYNC_TS0_BS_INIT_CTRL */ "", 64115 /* NS_TIMESYNC_TS0_COUNTER_ENABLE */ "", 64116 /* NS_TIMESYNC_TS0_CURRENT_FREQ_CTRL_LOWER */ "", 64117 /* NS_TIMESYNC_TS0_CURRENT_FREQ_CTRL_UPPER */ "", 64118 /* NS_TIMESYNC_TS0_FREQ_CTRL_FRAC_LOWER */ "", 64119 /* NS_TIMESYNC_TS0_FREQ_CTRL_FRAC_UPPER */ "", 64120 /* NS_TIMESYNC_TS0_FREQ_CTRL_OFFSET_LOWER */ "", 64121 /* NS_TIMESYNC_TS0_FREQ_CTRL_OFFSET_UPPER */ "", 64122 /* NS_TIMESYNC_TS0_FREQ_CTRL_UPDATE_LOWER */ "", 64123 /* NS_TIMESYNC_TS0_FREQ_CTRL_UPDATE_UPPER */ "", 64124 /* NS_TIMESYNC_TS0_INIT_ACCUMULATOR_0 */ "", 64125 /* NS_TIMESYNC_TS0_INIT_ACCUMULATOR_1 */ "", 64126 /* NS_TIMESYNC_TS0_INIT_ACCUMULATOR_2 */ "", 64127 /* NS_TIMESYNC_TS0_TIMESTAMP_LOWER_STATUS */ "", 64128 /* NS_TIMESYNC_TS0_TIMESTAMP_UPPER_STATUS */ "", 64129 /* NS_TIMESYNC_TS0_TS_OFFSET_LOWER_STATUS */ "", 64130 /* NS_TIMESYNC_TS0_TS_OFFSET_UPPER_STATUS */ "", 64131 /* NS_TIMESYNC_TS1_ACCUMULATOR_0 */ "", 64132 /* NS_TIMESYNC_TS1_ACCUMULATOR_1 */ "", 64133 /* NS_TIMESYNC_TS1_ACCUMULATOR_2 */ "", 64134 /* NS_TIMESYNC_TS1_BS_INIT_CTRL */ "", 64135 /* NS_TIMESYNC_TS1_COUNTER_ENABLE */ "", 64136 /* NS_TIMESYNC_TS1_CURRENT_FREQ_CTRL_LOWER */ "", 64137 /* NS_TIMESYNC_TS1_CURRENT_FREQ_CTRL_UPPER */ "", 64138 /* NS_TIMESYNC_TS1_FREQ_CTRL_FRAC_LOWER */ "", 64139 /* NS_TIMESYNC_TS1_FREQ_CTRL_FRAC_UPPER */ "", 64140 /* NS_TIMESYNC_TS1_FREQ_CTRL_OFFSET_LOWER */ "", 64141 /* NS_TIMESYNC_TS1_FREQ_CTRL_OFFSET_UPPER */ "", 64142 /* NS_TIMESYNC_TS1_FREQ_CTRL_UPDATE_LOWER */ "", 64143 /* NS_TIMESYNC_TS1_FREQ_CTRL_UPDATE_UPPER */ "", 64144 /* NS_TIMESYNC_TS1_INIT_ACCUMULATOR_0 */ "", 64145 /* NS_TIMESYNC_TS1_INIT_ACCUMULATOR_1 */ "", 64146 /* NS_TIMESYNC_TS1_INIT_ACCUMULATOR_2 */ "", 64147 /* NS_TIMESYNC_TS1_TIMESTAMP_LOWER_STATUS */ "", 64148 /* NS_TIMESYNC_TS1_TIMESTAMP_UPPER_STATUS */ "", 64149 /* NS_TIMESYNC_TS1_TS_OFFSET_LOWER_STATUS */ "", 64150 /* NS_TIMESYNC_TS1_TS_OFFSET_UPPER_STATUS */ "", 64151 /* NS_TIMESYNC_TS_EVENT_FWD_CFG */ "", 64152 /* NS_TIMESYNC_TX_PI_CLK_EVENT_CTRL */ "", 64153 /* NS_TS_CAPTURE_STATUS */ "", 64154 /* NS_TS_CPU_FIFO_ECC_CONTROL */ "", 64155 /* NS_TS_CPU_FIFO_ECC_STATUS */ "", 64156 /* NS_TS_CPU_FIFO_TM_CONTROL */ "", 64157 /* NS_TS_INT_ENABLE */ "", 64158 /* NS_TS_INT_STATUS */ "", 64159 /* NS_TX_PI_EVENT_OVRD_STATUS0 */ "", 64160 /* NS_TX_PI_EVENT_OVRD_STATUS1 */ "", 64161 /* NS_TX_PI_EVENT_STATUS0 */ "", 64162 /* NS_TX_PI_EVENT_STATUS1 */ "", 64163 /* NTP_TIME_CONTROL */ "", 64164 /* NTP_TIME_FRAC_SEC_LOWER */ "", 64165 /* NTP_TIME_FRAC_SEC_UPPER */ "", 64166 /* NTP_TIME_FREQ_CONTROL */ "", 64167 /* NTP_TIME_LEAP_SEC_CONTROL */ "", 64168 /* NTP_TIME_SEC */ "", 64169 /* NTSW_AVS_PVTMON_TMON_RESULT */ "", 64170 /* NTSW_AVS_STATUS */ "", 64171 /* OAMP_ARBITER_CONTROL */ "", 64172 /* OAMP_ARBITER_WEIGHT */ "", 64173 /* OAMP_BFDCC_TX_MPLS */ "", 64174 /* OAMP_BFDCV_TX_MPLS */ "", 64175 /* OAMP_BFD_CC_MPLSTP_GACH */ "", 64176 /* OAMP_BFD_CC_MPLSTP_GAL */ "", 64177 /* OAMP_BFD_CC_PACKET */ "", 64178 /* OAMP_BFD_CV_MPLSTP_GACH */ "", 64179 /* OAMP_BFD_CV_MPLSTP_GAL */ "", 64180 /* OAMP_BFD_CV_MPLSTP_MEPID_TLV_TYPE */ "", 64181 /* OAMP_BFD_CV_MPLSTP_TLV_HEADER */ "", 64182 /* OAMP_BFD_CV_PACKET */ "", 64183 /* OAMP_BFD_DIAG_PROFILE */ "", 64184 /* OAMP_BFD_EMC_CONST */ "", 64185 /* OAMP_BFD_FLADS_PROFILE */ "", 64186 /* OAMP_BFD_FLAGS_PROFILE */ "", 64187 /* OAMP_BFD_IPV4_CONTROL */ "", 64188 /* OAMP_BFD_IPV4_ONE_HOP_TOS */ "", 64189 /* OAMP_BFD_IPV4_STATIC_REGISTER */ "", 64190 /* OAMP_BFD_IPV4_UDP_SPORT */ "", 64191 /* OAMP_BFD_I_MPLS_CONTROL */ "", 64192 /* OAMP_BFD_I_PWE_CONTROL */ "", 64193 /* OAMP_BFD_MPLS_DST_IP */ "", 64194 /* OAMP_BFD_MPLS_UDP_SPORT */ "", 64195 /* OAMP_BFD_MY_DISCRIMINATOR_RANGE_START */ "", 64196 /* OAMP_BFD_PDU_STATIC_REGISTER */ "", 64197 /* OAMP_BFD_PWE_CW */ "", 64198 /* OAMP_BFD_PWE_CW_0 */ "", 64199 /* OAMP_BFD_PWE_CW_1 */ "", 64200 /* OAMP_BFD_PWE_CW_2 */ "", 64201 /* OAMP_BFD_PWE_CW_3 */ "", 64202 /* OAMP_BFD_PWE_ROUTER_ALERT */ "", 64203 /* OAMP_BFD_REQ_INTERVAL_POINTER */ "", 64204 /* OAMP_BFD_TX_IPV4_MULTI_HOP */ "", 64205 /* OAMP_BFD_TX_MPLS */ "", 64206 /* OAMP_BFD_TX_RATE */ "", 64207 /* OAMP_BFM_UDP_SRC_PORT */ "", 64208 /* OAMP_CCM_MAC_SA */ "", 64209 /* OAMP_CCM_TPID_MAP */ "", 64210 /* OAMP_CCM_TX_RATE */ "", 64211 /* OAMP_CFG_SAT_TX_WRAP_AROUND_NUM */ "", 64212 /* OAMP_CPUPORT */ "", 64213 /* OAMP_DMA_ARBITER_WEIGHT */ "", 64214 /* OAMP_DMA_COS_MAP */ "", 64215 /* OAMP_DMA_FIFO_MAP */ "", 64216 /* OAMP_DMA_TX_CONTROL */ "", 64217 /* OAMP_DOWN_PTCH */ "", 64218 /* OAMP_DROPPED_EVENTS_COUNT */ "", 64219 /* OAMP_ECC_1B_ERR_CNT */ "", 64220 /* OAMP_ECC_2B_ERR_CNT */ "", 64221 /* OAMP_ECC_ERR_1B_INITIATE */ "", 64222 /* OAMP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 64223 /* OAMP_ECC_ERR_2B_INITIATE */ "", 64224 /* OAMP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 64225 /* OAMP_ECC_ERR_MONITOR_MEM_MASK */ "", 64226 /* OAMP_ECC_INTERRUPT_REGISTER */ "", 64227 /* OAMP_ECC_INTERRUPT_REGISTER_MASK */ "", 64228 /* OAMP_ECC_INTERRUPT_REGISTER_TEST */ "", 64229 /* OAMP_ENABLE */ "", 64230 /* OAMP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 64231 /* OAMP_ENABLE_INTERRUPT_MESSAGE_EVENT */ "", 64232 /* OAMP_ERROR_INITIATION_DATA */ "", 64233 /* OAMP_ETH_1731_MEP_PROFILE */ "", 64234 /* OAMP_ETH_MAID_MISS_INFO */ "", 64235 /* OAMP_ETH_MDL_MISS_INFO */ "", 64236 /* OAMP_ETH_OAM_CONTROL */ "", 64237 /* OAMP_ETH_PERIOD_MISS_INFO */ "", 64238 /* OAMP_FLEX_CRC_MISS_INFO */ "", 64239 /* OAMP_GACH_CHAN_TYPES */ "", 64240 /* OAMP_GLOBAL_F */ "", 64241 /* OAMP_GLOBAL_MEM_OPTIONS */ "", 64242 /* OAMP_GLOBAL_SYS_HEADER_CFG */ "", 64243 /* OAMP_GTIMER_CONFIGURATION */ "", 64244 /* OAMP_GTIMER_CYCLE */ "", 64245 /* OAMP_GTIMER_TRIGGER */ "", 64246 /* OAMP_HEADER_CONFIG */ "", 64247 /* OAMP_ICC_MAP_REG_1 */ "", 64248 /* OAMP_ICC_MAP_REG_2 */ "", 64249 /* OAMP_INDIRECT_COMMAND */ "", 64250 /* OAMP_INDIRECT_COMMAND_ADDRESS */ "", 64251 /* OAMP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 64252 /* OAMP_INDIRECT_COMMAND_RD_DATA */ "", 64253 /* OAMP_INDIRECT_COMMAND_WIDE_MEM */ "", 64254 /* OAMP_INDIRECT_COMMAND_WR_DATA */ "", 64255 /* OAMP_INDIRECT_FORCE_BUBBLE */ "", 64256 /* OAMP_INDIRECT_WR_MASK */ "", 64257 /* OAMP_INITIATE_ECC_ERR_0 */ "", 64258 /* OAMP_INITIATE_PAR_ERR_0 */ "", 64259 /* OAMP_INTERFACE_STAT_TLV */ "", 64260 /* OAMP_INTERRUPT_MASK_REGISTER */ "", 64261 /* OAMP_INTERRUPT_MESSAGE */ "", 64262 /* OAMP_INTERRUPT_REGISTER */ "", 64263 /* OAMP_INTERRUPT_REGISTER_TEST */ "", 64264 /* OAMP_IPV4_SRC_ADDR_SELECT */ "", 64265 /* OAMP_IPV4_TOS_TTL_SELECT */ "", 64266 /* OAMP_LMM_DA_OUI */ "", 64267 /* OAMP_MAP_OAM_ID */ "", 64268 /* OAMP_MDB_APP_DB */ "", 64269 /* OAMP_MEMORY_HAZARD_PROTECTION_EN */ "", 64270 /* OAMP_MEP_DB_FULL_ENTRY_THRESHOLD */ "", 64271 /* OAMP_MIN_NET_PKT_SIZE */ "", 64272 /* OAMP_MODE_REGISTER */ "", 64273 /* OAMP_MPLS_PWE_PROFILE */ "", 64274 /* OAMP_MY_DISC_MISS_INFO */ "", 64275 /* OAMP_NIBBLE_SELECT_FOR_PE */ "", 64276 /* OAMP_NUMBER_OF_RMEPS */ "", 64277 /* OAMP_OAMP_RAM_CTRL_0 */ "", 64278 /* OAMP_OAMP_RAM_CTRL_1 */ "", 64279 /* OAMP_OAMP_RAM_CTRL_2 */ "", 64280 /* OAMP_OAMP_RAM_CTRL_3 */ "", 64281 /* OAMP_OAMP_RAM_CTRL_4 */ "", 64282 /* OAMP_OAM_TS_OFFSET_PROFILE */ "", 64283 /* OAMP_OPCODE_CONFIG */ "", 64284 /* OAMP_OPCODE_FOR_COUNT */ "", 64285 /* OAMP_OPCODE_INFO */ "", 64286 /* OAMP_PARITY_ERR_CNT */ "", 64287 /* OAMP_PAR_0_ERR_MONITOR_MEM_MASK */ "", 64288 /* OAMP_PAR_ERR_INITIATE */ "", 64289 /* OAMP_PAR_ERR_MEM_MASK */ "", 64290 /* OAMP_PER_MEP_PROFILE_RX_COUNTER_CFG */ "", 64291 /* OAMP_PER_MEP_PROFILE_TX_COUNTER_CFG */ "", 64292 /* OAMP_PE_CONST */ "", 64293 /* OAMP_PE_FEM_CFG_1 */ "", 64294 /* OAMP_PE_FEM_CFG_2 */ "", 64295 /* OAMP_PE_FEM_MAP */ "", 64296 /* OAMP_PE_FIRST_INST */ "", 64297 /* OAMP_PE_INST */ "", 64298 /* OAMP_PE_PROF */ "", 64299 /* OAMP_PE_PTR */ "", 64300 /* OAMP_PE_STATUS */ "", 64301 /* OAMP_PE_STATUS_1 */ "", 64302 /* OAMP_PE_STATUS_2 */ "", 64303 /* OAMP_PORT_STAT_TLV */ "", 64304 /* OAMP_PROTECTION_PACKET_CONF */ "", 64305 /* OAMP_PROTECTION_PACKET_HEADER */ "", 64306 /* OAMP_PROTECTION_PACKET_HEADER_NUM_OF_BYTES */ "", 64307 /* OAMP_PR_2_FWDDP */ "", 64308 /* OAMP_PR_2_FW_DTC */ "", 64309 /* OAMP_PUNT_EVENT_HENDLING */ "", 64310 /* OAMP_PUNT_PKT_SYS_HDR */ "", 64311 /* OAMP_REG_0085 */ "", 64312 /* OAMP_REG_0086 */ "", 64313 /* OAMP_REG_0087 */ "", 64314 /* OAMP_REG_0090 */ "", 64315 /* OAMP_REG_0091 */ "", 64316 /* OAMP_REG_0092 */ "", 64317 /* OAMP_REG_0093 */ "", 64318 /* OAMP_REG_0098 */ "", 64319 /* OAMP_REG_0127 */ "", 64320 /* OAMP_REG_0129 */ "", 64321 /* OAMP_REG_0130 */ "", 64322 /* OAMP_REG_0141 */ "", 64323 /* OAMP_REG_0142 */ "", 64324 /* OAMP_REG_0154 */ "", 64325 /* OAMP_REG_0155 */ "", 64326 /* OAMP_REG_0165 */ "", 64327 /* OAMP_REG_0167 */ "", 64328 /* OAMP_REG_0168 */ "", 64329 /* OAMP_REG_0169 */ "", 64330 /* OAMP_REG_0199 */ "", 64331 /* OAMP_REG_0201 */ "", 64332 /* OAMP_REG_00A0 */ "", 64333 /* OAMP_REG_00A4 */ "", 64334 /* OAMP_REG_00A6 */ "", 64335 /* OAMP_REG_00AA */ "", 64336 /* OAMP_REG_00AD */ "", 64337 /* OAMP_REG_00AE */ "", 64338 /* OAMP_REG_00AF */ "", 64339 /* OAMP_REG_00B0 */ "", 64340 /* OAMP_REG_00B1 */ "", 64341 /* OAMP_REG_00B2 */ "", 64342 /* OAMP_REG_00B3 */ "", 64343 /* OAMP_REG_00C2 */ "", 64344 /* OAMP_REG_00C6 */ "", 64345 /* OAMP_REG_00CF */ "", 64346 /* OAMP_REG_011B */ "", 64347 /* OAMP_REG_011C */ "", 64348 /* OAMP_REG_016A */ "", 64349 /* OAMP_REG_016B */ "", 64350 /* OAMP_REG_020D */ "", 64351 /* OAMP_REMOTE_MEP_EXACT_MATCH_CAM_ENTRIES_COUNTER */ "", 64352 /* OAMP_REMOTE_MEP_EXACT_MATCH_DEFRAG_CONFIGURATION_REGISTER */ "", 64353 /* OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS */ "", 64354 /* OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_ACCESSED_MODE */ "", 64355 /* OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_INDEX */ "", 64356 /* OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_KEY */ "", 64357 /* OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_LOOKUP_RESULT */ "", 64358 /* OAMP_REMOTE_MEP_EXACT_MATCH_DIAGNOSTICS_READ_RESULT */ "", 64359 /* OAMP_REMOTE_MEP_EXACT_MATCH_ENTRIES_COUNTER */ "", 64360 /* OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_CAM_TABLE_FULL_COUNTER */ "", 64361 /* OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 64362 /* OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 64363 /* OAMP_REMOTE_MEP_EXACT_MATCH_ERROR_TABLE_COHERENCY_COUNTER */ "", 64364 /* OAMP_REMOTE_MEP_EXACT_MATCH_GENERAL_EM_CONFIGURATION_REGISTER */ "", 64365 /* OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_MASK_REGISTER_ONE */ "", 64366 /* OAMP_REMOTE_MEP_EXACT_MATCH_INTERRUPT_REGISTER_ONE */ "", 64367 /* OAMP_REMOTE_MEP_EXACT_MATCH_KEY_TABLE_ENTRY_LIMIT */ "", 64368 /* OAMP_REMOTE_MEP_EXACT_MATCH_KILL_RESET_SEQUENCE */ "", 64369 /* OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 64370 /* OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_UNIT_FAILURE */ "", 64371 /* OAMP_REMOTE_MEP_EXACT_MATCH_REQUESTS_COUNTER */ "", 64372 /* OAMP_REMOTE_MEP_EXACT_MATCH_RESET_STATUS_REGISTER */ "", 64373 /* OAMP_REMOTE_MEP_EXACT_MATCH_WARNING_INSERTED_EXISTING_COUNTER */ "", 64374 /* OAMP_RESERVED_MIRROR_ADDR */ "", 64375 /* OAMP_RESERVED_MTCD */ "", 64376 /* OAMP_RESERVED_MTCP */ "", 64377 /* OAMP_RESERVED_SPARE_0 */ "", 64378 /* OAMP_RESERVED_SPARE_1 */ "", 64379 /* OAMP_RESERVED_SPARE_2 */ "", 64380 /* OAMP_RESERVED_SPARE_3 */ "", 64381 /* OAMP_RFC_6374_DM_PDU_HEADER */ "", 64382 /* OAMP_RFC_6374_DM_PWE_CW */ "", 64383 /* OAMP_RFC_6374_FIX_QUALIFIER */ "", 64384 /* OAMP_RFC_6374_IGNORED */ "", 64385 /* OAMP_RFC_6374_LM_PDU_HEADER */ "", 64386 /* OAMP_RFC_6374_LM_PWE_CW */ "", 64387 /* OAMP_RFC_6374_LM_PWE_CW_0 */ "", 64388 /* OAMP_RFC_6374_LM_PWE_CW_1 */ "", 64389 /* OAMP_RMAPEM_CAM_ENTRIES_COUNTER */ "", 64390 /* OAMP_RMAPEM_DIAGNOSTICS */ "", 64391 /* OAMP_RMAPEM_DIAGNOSTICS_ACCESSED_MODE */ "", 64392 /* OAMP_RMAPEM_DIAGNOSTICS_INDEX */ "", 64393 /* OAMP_RMAPEM_DIAGNOSTICS_KEY */ "", 64394 /* OAMP_RMAPEM_DIAGNOSTICS_LOOKUP_RESULT */ "", 64395 /* OAMP_RMAPEM_DIAGNOSTICS_READ_RESULT */ "", 64396 /* OAMP_RMAPEM_ENTRIES_COUNTER */ "", 64397 /* OAMP_RMAPEM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 64398 /* OAMP_RMAPEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 64399 /* OAMP_RMAPEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 64400 /* OAMP_RMAPEM_ERROR_TABLE_COHERENCY_COUNTER */ "", 64401 /* OAMP_RMAPEM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 64402 /* OAMP_RMAPEM_INTERRUPT_MASK_REGISTER_ONE */ "", 64403 /* OAMP_RMAPEM_INTERRUPT_REGISTER_ONE */ "", 64404 /* OAMP_RMAPEM_INTERRUPT_REGISTER_ONE_TEST */ "", 64405 /* OAMP_RMAPEM_KEY_TABLE_ENTRY_LIMIT */ "", 64406 /* OAMP_RMAPEM_LAST_LOOKUP */ "", 64407 /* OAMP_RMAPEM_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 64408 /* OAMP_RMAPEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 64409 /* OAMP_RMAPEM_MANAGEMENT_UNIT_FAILURE */ "", 64410 /* OAMP_RMAPEM_MNGMNT_SER_INDICATION */ "", 64411 /* OAMP_RMAPEM_REQUESTS_COUNTER */ "", 64412 /* OAMP_RMAPEM_RESET_STATUS_REGISTER */ "", 64413 /* OAMP_RMAPEM_SER_DISABLES_MNGMNT */ "", 64414 /* OAMP_RMAPEM_WARNING_INSERTED_EXISTING_COUNTER */ "", 64415 /* OAMP_RMEP_PUNT_GOOD_TIMER */ "", 64416 /* OAMP_RSP_PKT_COUNTER */ "", 64417 /* OAMP_RXB_DEBUG */ "", 64418 /* OAMP_RXB_PKT_COUNTER */ "", 64419 /* OAMP_RX_PKT_COUNTER */ "", 64420 /* OAMP_RX_STATS_DATA_0 */ "", 64421 /* OAMP_RX_STATS_DATA_1 */ "", 64422 /* OAMP_RX_STATS_DATA_2 */ "", 64423 /* OAMP_RX_STATS_DATA_3 */ "", 64424 /* OAMP_RX_STATS_DATA_4 */ "", 64425 /* OAMP_RX_TRAP_CODES */ "", 64426 /* OAMP_R_MEP_DB_FULL_ENTRY_THRESHOLD */ "", 64427 /* OAMP_SAT_EVC_RATE_CONTROL */ "", 64428 /* OAMP_SAT_GEN_CONFIG */ "", 64429 /* OAMP_SAT_GEN_RATE_CONTROL */ "", 64430 /* OAMP_SAT_RX_CONFIG */ "", 64431 /* OAMP_SAT_RX_STAT */ "", 64432 /* OAMP_SAT_TX_CONFIG */ "", 64433 /* OAMP_SAT_TX_EVC_CNTR */ "", 64434 /* OAMP_SAT_TX_GEN_CNTR */ "", 64435 /* OAMP_SAT_TX_GEN_FLOW_RATE_CONTROL */ "", 64436 /* OAMP_SBUS_BROADCAST_ID */ "", 64437 /* OAMP_SBUS_LAST_IN_CHAIN */ "", 64438 /* OAMP_SD_SF_SCANNER_CFG */ "", 64439 /* OAMP_SD_SF_SHARE_CFG */ "", 64440 /* OAMP_SD_SF_Y_1711_CONF */ "", 64441 /* OAMP_SKIP_NEXT_BANK */ "", 64442 /* OAMP_SLM_CONFIG */ "", 64443 /* OAMP_SLM_MEASUREMENT_PERIOD_TIMER */ "", 64444 /* OAMP_SPARE_REGISTER_3 */ "", 64445 /* OAMP_SPECIAL_CLOCK_CONTROLS */ "", 64446 /* OAMP_SRC_IP_MISS_INFO */ "", 64447 /* OAMP_SRC_PORT_MISS_INFO */ "", 64448 /* OAMP_STATUS_1_REG */ "", 64449 /* OAMP_STATUS_2_REG */ "", 64450 /* OAMP_STAT_INTERRUPT_MESSAGE */ "", 64451 /* OAMP_TIMER_CONFIG */ "", 64452 /* OAMP_TRAP_CODE_MISS_INFO */ "", 64453 /* OAMP_TST_LBM_CTRL */ "", 64454 /* OAMP_TST_LBM_PACKET_HEADER */ "", 64455 /* OAMP_TST_LBM_PACKET_HEADER_NUM_OF_BYTES */ "", 64456 /* OAMP_TST_LBM_STATUS */ "", 64457 /* OAMP_TXM_BANK_SCAN_CONFIG */ "", 64458 /* OAMP_TXM_PKT_COUNTER */ "", 64459 /* OAMP_TXM_SLM_MEASUREMENT_PERIOD_TIMER */ "", 64460 /* OAMP_TXO_PKT_COUNTER */ "", 64461 /* OAMP_TXO_REQ_FIFO_DATA */ "", 64462 /* OAMP_TXO_REQ_STATUS */ "", 64463 /* OAMP_TX_JR_2_AS_OAM */ "", 64464 /* OAMP_TX_PPH */ "", 64465 /* OAMP_UDH */ "", 64466 /* OAMP_UP_PTCH */ "", 64467 /* OAMP_VALIDITY_CHECK_STICKY */ "", 64468 /* OAMP_YOUR_DISC_MISS_INFO */ "", 64469 /* OAMP_Y_1731O_MPLSTP_GACH */ "", 64470 /* OAMP_Y_1731O_MPLSTP_GAL */ "", 64471 /* OAMP_Y_1731O_PWE_GACH */ "", 64472 /* OAM_CCM_COUNT_64 */ "OAM_CCM_COUNT", 64473 /* OAM_CONTROL */ "", 64474 /* OAM_CONTROL_1 */ "", 64475 /* OAM_COPYTO_CPU_CONTROL */ "", 64476 /* OAM_COPYTO_CPU_CONTROL_FP_MEPS */ "", 64477 /* OAM_CURRENT_TIME */ "", 64478 /* OAM_C_INTERFACE_DROP_CONTROL */ "", 64479 /* OAM_C_INTERFACE_DROP_CONTROL_64 */ "OAM_C_INTERFACE_DROP_CONTROL", 64480 /* OAM_DROP_CONTROL */ "", 64481 /* OAM_ERROR_CONTROL */ "", 64482 /* OAM_ERROR_CONTROL_FP_MEPS */ "", 64483 /* OAM_FLEXIBLE_DOMAIN_CONTROL_PARITY_CONTROL */ "", 64484 /* OAM_INTF_PROC_SELECT_CONTROL_64 */ "OAM_INTF_PROC_SELECT_CONTROL", 64485 /* OAM_KEY_SELECT_CONTROL_64 */ "OAM_KEY_SELECT_CONTROL", 64486 /* OAM_LM_CNG_CONTROL */ "OAM_LM_CNG_CONTROL", 64487 /* OAM_LM_COUNTERS_0_PARITY_CONTROL */ "", 64488 /* OAM_LM_COUNTERS_0_PARITY_STATUS_INTR */ "", 64489 /* OAM_LM_COUNTERS_0_PARITY_STATUS_NACK */ "", 64490 /* OAM_LM_COUNTERS_1_PARITY_CONTROL */ "", 64491 /* OAM_LM_COUNTERS_1_PARITY_STATUS_INTR */ "", 64492 /* OAM_LM_COUNTERS_1_PARITY_STATUS_NACK */ "", 64493 /* OAM_LM_COUNTERS_PARITY_CONTROL */ "", 64494 /* OAM_LM_COUNTERS_PARITY_STATUS */ "", 64495 /* OAM_LM_COUNTERS_PARITY_STATUS_INTR */ "", 64496 /* OAM_LM_COUNTERS_PARITY_STATUS_NACK */ "", 64497 /* OAM_LM_CPU_DATA_CONTROL */ "OAM_LM_CPU_DATA_CONTROL", 64498 /* OAM_LPR_TM_CONTROL_0 */ "", 64499 /* OAM_LSP_INTERFACE_DROP_CONTROL_64 */ "OAM_LSP_INTERFACE_DROP_CONTROL", 64500 /* OAM_OPCODE_CONTROL_PROFILE_PARITY_CONTROL */ "", 64501 /* OAM_OPCODE_GROUP_PARITY_CONTROL */ "", 64502 /* OAM_PORT_INTERFACE_DROP_CONTROL */ "", 64503 /* OAM_PORT_INTERFACE_DROP_CONTROL_64 */ "OAM_PORT_INTERFACE_DROP_CONTROL", 64504 /* OAM_PW_INTERFACE_DROP_CONTROL_64 */ "OAM_PW_INTERFACE_DROP_CONTROL", 64505 /* OAM_SECTION_INTERFACE_DROP_CONTROL_64 */ "OAM_SECTION_INTERFACE_DROP_CONTROL", 64506 /* OAM_SEC_NS_COUNTER_64 */ "OAM_SEC_NS_COUNTER", 64507 /* OAM_SEC_NS_COUNTER_ENABLE */ "", 64508 /* OAM_SVP_INTERFACE_DROP_CONTROL */ "", 64509 /* OAM_S_C_INTERFACE_DROP_CONTROL */ "", 64510 /* OAM_S_C_INTERFACE_DROP_CONTROL_64 */ "OAM_S_C_INTERFACE_DROP_CONTROL", 64511 /* OAM_S_INTERFACE_DROP_CONTROL */ "", 64512 /* OAM_S_INTERFACE_DROP_CONTROL_64 */ "OAM_S_INTERFACE_DROP_CONTROL", 64513 /* OAM_S_INTERFACE_PASSIVE_PROCESSING_CONTROL */ "", 64514 /* OAM_TIMER_CONTROL */ "", 64515 /* OAM_TX_CONTROL */ "", 64516 /* OAM_VP_INTERFACE_DROP_CONTROL_64 */ "OAM_VP_INTERFACE_DROP_CONTROL", 64517 /* OCB_BANKS_FULL_TH_REGISTER */ "", 64518 /* OCB_BANK_ORDER_FIFO_STATUS */ "", 64519 /* OCB_DEBUG_CRC_FORCE_ERR */ "", 64520 /* OCB_DISABLE_BANK_DBG */ "", 64521 /* OCB_DISABLE_REQ_DBG */ "", 64522 /* OCB_DYNAMIC_CONFIGURATION */ "", 64523 /* OCB_ECC_1B_ERR_CNT */ "", 64524 /* OCB_ECC_2B_ERR_CNT */ "", 64525 /* OCB_ECC_ERR_1B_INITIATE */ "", 64526 /* OCB_ECC_ERR_1B_INITIATE_1 */ "", 64527 /* OCB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 64528 /* OCB_ECC_ERR_2B_INITIATE */ "", 64529 /* OCB_ECC_ERR_2B_INITIATE_1 */ "", 64530 /* OCB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 64531 /* OCB_ECC_INTERRUPT_REGISTER */ "", 64532 /* OCB_ECC_INTERRUPT_REGISTER_MASK */ "", 64533 /* OCB_ECC_INTERRUPT_REGISTER_TEST */ "", 64534 /* OCB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 64535 /* OCB_ERROR_INITIATION_DATA */ "", 64536 /* OCB_FBC_BANK_CFG */ "", 64537 /* OCB_FBC_BANK_INTERRUPT_REGISTER */ "", 64538 /* OCB_FBC_BANK_INTERRUPT_REGISTER_MASK */ "", 64539 /* OCB_FBC_BANK_INTERRUPT_REGISTER_TEST */ "", 64540 /* OCB_FREE_BUFFERS_BANK_STATUS_REGISTER */ "", 64541 /* OCB_FREE_BUFFERS_STATUS_REGISTER */ "", 64542 /* OCB_FREE_ERROR */ "", 64543 /* OCB_GENERAL_CONFIG */ "", 64544 /* OCB_GLOBALF */ "", 64545 /* OCB_GLOBAL_1 */ "", 64546 /* OCB_GLOBAL_GENERAL_CFG_3 */ "", 64547 /* OCB_GLOBAL_MEM_OPTIONS */ "", 64548 /* OCB_GLOBAL_OCB_BANK_RANGE */ "", 64549 /* OCB_GTIMER_CONFIGURATION */ "", 64550 /* OCB_GTIMER_CYCLE */ "", 64551 /* OCB_GTIMER_TRIGGER */ "", 64552 /* OCB_INDIRECT_COMMAND */ "", 64553 /* OCB_INDIRECT_COMMAND_ADDRESS */ "", 64554 /* OCB_INDIRECT_COMMAND_DATA_INCREMENT */ "", 64555 /* OCB_INDIRECT_COMMAND_RD_DATA */ "", 64556 /* OCB_INDIRECT_COMMAND_WIDE_MEM */ "", 64557 /* OCB_INDIRECT_COMMAND_WR_DATA */ "", 64558 /* OCB_INDIRECT_FORCE_BUBBLE */ "", 64559 /* OCB_INDIRECT_READ_DATA_0 */ "", 64560 /* OCB_INDIRECT_READ_DATA_1 */ "", 64561 /* OCB_INDIRECT_WRITE_DATA_0 */ "", 64562 /* OCB_INDIRECT_WRITE_DATA_1 */ "", 64563 /* OCB_INTERRUPT_MASK_REGISTER */ "", 64564 /* OCB_INTERRUPT_REGISTER */ "", 64565 /* OCB_INTERRUPT_REGISTER_TEST */ "", 64566 /* OCB_LAST_RD_ADDR */ "", 64567 /* OCB_LAST_RD_BANK */ "", 64568 /* OCB_LAST_RD_DBUFF_POINTER */ "", 64569 /* OCB_LAST_RD_OFFSET */ "", 64570 /* OCB_LAST_WR_ADDR */ "", 64571 /* OCB_LAST_WR_BANK */ "", 64572 /* OCB_LAST_WR_DBUFF_POINTER */ "", 64573 /* OCB_LAST_WR_OFFSET */ "", 64574 /* OCB_MASK_ECC_PER_BANK */ "", 64575 /* OCB_OCB_BANK_CRC_ERR */ "", 64576 /* OCB_OCB_CONFIGURATION_REGISTER */ "", 64577 /* OCB_OCB_CRC_ERR */ "", 64578 /* OCB_OCB_EVEN_RD_CTR */ "", 64579 /* OCB_OCB_EVEN_WR_CTR */ "", 64580 /* OCB_OCB_ODD_RD_CTR */ "", 64581 /* OCB_OCB_ODD_WR_CTR */ "", 64582 /* OCB_OCB_RD_CTR */ "", 64583 /* OCB_OCB_RD_CTR_BANK */ "", 64584 /* OCB_OCB_WR_CTR */ "", 64585 /* OCB_OCB_WR_CTR_BANK */ "", 64586 /* OCB_PARITY_ERR_CNT */ "", 64587 /* OCB_PAR_ERR_INITIATE */ "", 64588 /* OCB_PAR_ERR_MEM_MASK */ "", 64589 /* OCB_PCMI_0 */ "", 64590 /* OCB_PCMI_1 */ "", 64591 /* OCB_PCMI_2 */ "", 64592 /* OCB_PCMI_3 */ "", 64593 /* OCB_PCMI_4 */ "", 64594 /* OCB_PCMI_0_S */ "", 64595 /* OCB_PCMI_0_T */ "", 64596 /* OCB_PCMI_1_S */ "", 64597 /* OCB_PCMI_1_T */ "", 64598 /* OCB_PCMI_2_S */ "", 64599 /* OCB_PCMI_2_T */ "", 64600 /* OCB_PCMI_3_S */ "", 64601 /* OCB_PCMI_3_T */ "", 64602 /* OCB_PCMI_4_S */ "", 64603 /* OCB_PCMI_4_T */ "", 64604 /* OCB_RD_ADDR_FIFO_ALMOST_FULL_BANK */ "", 64605 /* OCB_READ_ADDR_FIFO_STATUS_BANK */ "", 64606 /* OCB_READ_DATA_FIFO_STATUS_BANK */ "", 64607 /* OCB_REG_0020 */ "", 64608 /* OCB_REG_0040 */ "", 64609 /* OCB_REG_0085 */ "", 64610 /* OCB_REG_0086 */ "", 64611 /* OCB_REG_0087 */ "", 64612 /* OCB_REG_0090 */ "", 64613 /* OCB_REG_0091 */ "", 64614 /* OCB_REG_0092 */ "", 64615 /* OCB_REG_0093 */ "", 64616 /* OCB_REG_00A4 */ "", 64617 /* OCB_REG_00A6 */ "", 64618 /* OCB_REG_00AF */ "", 64619 /* OCB_REG_00B4 */ "", 64620 /* OCB_REG_00B5 */ "", 64621 /* OCB_REG_00B6 */ "", 64622 /* OCB_REG_00B7 */ "", 64623 /* OCB_REG_00C1 */ "", 64624 /* OCB_REG_00C2 */ "", 64625 /* OCB_REG_00CF */ "", 64626 /* OCB_RESERVED_MIRROR_ADDR */ "", 64627 /* OCB_RESERVED_MTCD */ "", 64628 /* OCB_RESERVED_MTCP */ "", 64629 /* OCB_RESERVED_PCMI_0 */ "", 64630 /* OCB_RESERVED_PCMI_1 */ "", 64631 /* OCB_RESERVED_PCMI_2 */ "", 64632 /* OCB_RESERVED_PCMI_3 */ "", 64633 /* OCB_RESERVED_PCMI_4 */ "", 64634 /* OCB_RESERVED_PCMI_0_S */ "", 64635 /* OCB_RESERVED_PCMI_0_T */ "", 64636 /* OCB_RESERVED_PCMI_1_S */ "", 64637 /* OCB_RESERVED_PCMI_1_T */ "", 64638 /* OCB_RESERVED_PCMI_2_S */ "", 64639 /* OCB_RESERVED_PCMI_2_T */ "", 64640 /* OCB_RESERVED_PCMI_3_S */ "", 64641 /* OCB_RESERVED_PCMI_3_T */ "", 64642 /* OCB_RESERVED_PCMI_4_S */ "", 64643 /* OCB_RESERVED_PCMI_4_T */ "", 64644 /* OCB_RESERVED_SPARE_0 */ "", 64645 /* OCB_RESERVED_SPARE_1 */ "", 64646 /* OCB_RESERVED_SPARE_2 */ "", 64647 /* OCB_RESERVED_SPARE_3 */ "", 64648 /* OCB_RESET_STATUS_REGISTER */ "", 64649 /* OCB_SBUS_BROADCAST_ID */ "", 64650 /* OCB_SBUS_LAST_IN_CHAIN */ "", 64651 /* OCB_SPECIAL_CLOCK_CONTROLS */ "", 64652 /* OCB_STATISTICS_COUNTERS */ "", 64653 /* OCCG_ECC_INTERRUPT_REGISTER */ "", 64654 /* OCCG_ECC_INTERRUPT_REGISTER_MASK */ "", 64655 /* OCCG_ECC_INTERRUPT_REGISTER_TEST */ "", 64656 /* OCCG_GTIMER_CONFIGURATION */ "", 64657 /* OCCG_GTIMER_TRIGGER */ "", 64658 /* OCCG_INTERRUPT_MASK_REGISTER */ "", 64659 /* OCCG_INTERRUPT_REGISTER */ "", 64660 /* OCCG_INTERRUPT_REGISTER_TEST */ "", 64661 /* OCCG_REG_0050 */ "", 64662 /* OCCG_REG_0051 */ "", 64663 /* OCCG_REG_0052 */ "", 64664 /* OCCG_REG_0053 */ "", 64665 /* OCCG_REG_0055 */ "", 64666 /* OCCG_REG_0056 */ "", 64667 /* OCCG_REG_0059 */ "", 64668 /* OCCG_REG_0062 */ "", 64669 /* OCCG_REG_0063 */ "", 64670 /* OCCG_REG_0067 */ "", 64671 /* OCCG_REG_0068 */ "", 64672 /* OCCG_REG_0078 */ "", 64673 /* OCCG_REG_0087 */ "", 64674 /* OCCG_REG_0100 */ "", 64675 /* OCCG_REG_0104 */ "", 64676 /* OCCG_REG_0106 */ "", 64677 /* OCCG_REG_0110 */ "", 64678 /* OCCG_REG_0114 */ "", 64679 /* OCCG_REG_0115 */ "", 64680 /* OCCG_REG_0117 */ "", 64681 /* OCCG_REG_0118 */ "", 64682 /* OCCG_REG_0120 */ "", 64683 /* OCCG_REG_0130 */ "", 64684 /* OCCG_REG_0132 */ "", 64685 /* OCCG_REG_005A */ "", 64686 /* OCCG_REG_005E */ "", 64687 /* OCCG_REG_005F */ "", 64688 /* OCCG_REG_006A */ "", 64689 /* OCCG_REG_006B */ "", 64690 /* OCCG_REG_006F */ "", 64691 /* OCCG_REG_007C */ "", 64692 /* OCCG_REG_010A */ "", 64693 /* OCCG_REG_010B */ "", 64694 /* OCCG_REG_010F */ "", 64695 /* OCCG_RESERVED_MIRROR_ADDR */ "", 64696 /* OCCG_RESERVED_SPARE_0 */ "", 64697 /* OCCG_RESERVED_SPARE_1 */ "", 64698 /* OCCG_RESERVED_SPARE_2 */ "", 64699 /* OCCG_RESERVED_SPARE_3 */ "", 64700 /* OCCG_SBUS_BROADCAST_ID */ "", 64701 /* OCCG_SYNC_TEST_MODE_OPERATION */ "", 64702 /* OCCG_TEST_MODE_CMD_REG */ "", 64703 /* OCCG_TEST_MODE_CMD_RESULT_REG */ "", 64704 /* OLP_APP_DB_TO_APP_DB_INDEX_MAP */ "", 64705 /* OLP_APP_DB_TO_APP_DB_INDEX_MAP_FOR_ROUTING */ "", 64706 /* OLP_AUTO_DOC_NAME_0 */ "", 64707 /* OLP_AUTO_DOC_NAME_1 */ "", 64708 /* OLP_AUTO_DOC_NAME_2 */ "", 64709 /* OLP_AUTO_DOC_NAME_3 */ "", 64710 /* OLP_CFG_JR_2_CMD_TO_JR_CMD_MAP */ "", 64711 /* OLP_CFG_JR_CMD_TO_JR_2_CMD_MAP */ "", 64712 /* OLP_CFG_JR_LOGICAL_DB_TYPE */ "", 64713 /* OLP_CFG_JR_TO_JR_2_AGE */ "", 64714 /* OLP_CFG_JR_TO_JR_2_APP_DB */ "", 64715 /* OLP_CFG_JR_TO_JR_2_KEY_MASK */ "", 64716 /* OLP_CFG_JR_TO_JR_2_VMV */ "", 64717 /* OLP_CONFIGS_GENERAL */ "", 64718 /* OLP_DSP_ENGINE_CONFIGURATION */ "", 64719 /* OLP_DSP_HEADER */ "", 64720 /* OLP_ECC_1B_ERR_CNT */ "", 64721 /* OLP_ECC_2B_ERR_CNT */ "", 64722 /* OLP_ECC_ERR_1B_INITIATE */ "", 64723 /* OLP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 64724 /* OLP_ECC_ERR_2B_INITIATE */ "", 64725 /* OLP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 64726 /* OLP_ECC_INTERRUPT_REGISTER */ "", 64727 /* OLP_ECC_INTERRUPT_REGISTER_MASK */ "", 64728 /* OLP_ECC_INTERRUPT_REGISTER_TEST */ "", 64729 /* OLP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 64730 /* OLP_EP_TRANSACTION_COUNTER */ "", 64731 /* OLP_ERROR_INITIATION_DATA */ "", 64732 /* OLP_FIFO_0_EVENT_COUNTER */ "", 64733 /* OLP_FIFO_1_EVENT_COUNTER */ "", 64734 /* OLP_FIFO_DMA_EVENT_COUNTER */ "", 64735 /* OLP_GLOBAL_MEM_OPTIONS */ "", 64736 /* OLP_GLOBAL_PP_1 */ "", 64737 /* OLP_GLOBAL_REGISTER_1 */ "", 64738 /* OLP_GTIMER_CONFIGURATION */ "", 64739 /* OLP_GTIMER_CYCLE */ "", 64740 /* OLP_GTIMER_TRIGGER */ "", 64741 /* OLP_HEAD_OF_CPU_DSPG_CMD_FIFO */ "", 64742 /* OLP_INCOMING_BAD_PACKET_COUNTER */ "", 64743 /* OLP_INCOMING_EVENT_COUNTER */ "", 64744 /* OLP_INCOMING_VALID_DSP_COMMANDS_COUNTER */ "", 64745 /* OLP_INCOMING_VALID_PACKET_COUNTER */ "", 64746 /* OLP_INDIRECT_COMMAND */ "", 64747 /* OLP_INDIRECT_COMMAND_ADDRESS */ "", 64748 /* OLP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 64749 /* OLP_INDIRECT_COMMAND_RD_DATA */ "", 64750 /* OLP_INDIRECT_COMMAND_WIDE_MEM */ "", 64751 /* OLP_INDIRECT_COMMAND_WR_DATA */ "", 64752 /* OLP_INDIRECT_FORCE_BUBBLE */ "", 64753 /* OLP_INDIRECT_WR_MASK */ "", 64754 /* OLP_INTERRUPT_MASK_REGISTER */ "", 64755 /* OLP_INTERRUPT_REGISTER */ "", 64756 /* OLP_INTERRUPT_REGISTER_TEST */ "", 64757 /* OLP_IP_TRANSACTION_COUNTER */ "", 64758 /* OLP_LARGE_EM_MRQ_CONFIGURATION */ "", 64759 /* OLP_LEARN_CMD_DESTINATION_OFFSET */ "", 64760 /* OLP_LEARN_CMD_EEI_AND_FEC_JR_2_LEARN_PAYLOAD_INITIAL_VALUE */ "", 64761 /* OLP_LEARN_CMD_EEI_OFFSET */ "", 64762 /* OLP_LEARN_CMD_FEC_OFFSET */ "", 64763 /* OLP_LEARN_CMD_LIF_AND_DESTINATION_JR_2_LEARN_INFO_DATA_INITIAL_VALUE */ "", 64764 /* OLP_LEARN_CMD_OUT_LIF_OFFSET */ "", 64765 /* OLP_LPBK_EVENT_COUNTER */ "", 64766 /* OLP_OLP_GLOBAL_REGISTERS_0 */ "", 64767 /* OLP_OLP_LEARN_PAYLOAD_STRENGTH_SIZE */ "", 64768 /* OLP_OUTGOING_PACKET_COUNTER */ "", 64769 /* OLP_OUTGOING_REQUEST_COUNTER */ "", 64770 /* OLP_PARITY_ERR_CNT */ "", 64771 /* OLP_PAR_ERR_INITIATE */ "", 64772 /* OLP_PAR_ERR_MEM_MASK */ "", 64773 /* OLP_PIPE_SELECT */ "", 64774 /* OLP_REG_0041 */ "", 64775 /* OLP_REG_0085 */ "", 64776 /* OLP_REG_0090 */ "", 64777 /* OLP_REG_0091 */ "", 64778 /* OLP_REG_0092 */ "", 64779 /* OLP_REG_0093 */ "", 64780 /* OLP_REG_0098 */ "", 64781 /* OLP_REG_0100 */ "", 64782 /* OLP_REG_0109 */ "", 64783 /* OLP_REG_0111 */ "", 64784 /* OLP_REG_0112 */ "", 64785 /* OLP_REG_00A0 */ "", 64786 /* OLP_REG_00A4 */ "", 64787 /* OLP_REG_00A6 */ "", 64788 /* OLP_REG_00AA */ "", 64789 /* OLP_REG_00BF */ "", 64790 /* OLP_REG_00C2 */ "", 64791 /* OLP_REG_00C3 */ "", 64792 /* OLP_REG_00E7 */ "", 64793 /* OLP_REG_00F0 */ "", 64794 /* OLP_REG_010B */ "", 64795 /* OLP_REG_010D */ "", 64796 /* OLP_RESERVED_MIRROR_ADDR */ "", 64797 /* OLP_RESERVED_MTCD */ "", 64798 /* OLP_RESERVED_MTCP */ "", 64799 /* OLP_RESERVED_SPARE_0 */ "", 64800 /* OLP_RESERVED_SPARE_1 */ "", 64801 /* OLP_RESERVED_SPARE_2 */ "", 64802 /* OLP_RESERVED_SPARE_3 */ "", 64803 /* OLP_RX_CONFIGS_ARAD_DSP_SOURCE_DEVICE */ "", 64804 /* OLP_RX_CONFIGS_BCM_86650_DSP_SOURCE_DEVICE */ "", 64805 /* OLP_RX_CONFIGS_DSP_IDENTIFIER */ "", 64806 /* OLP_RX_CONFIGS_GENERAL */ "", 64807 /* OLP_SBUS_BROADCAST_ID */ "", 64808 /* OLP_SBUS_LAST_IN_CHAIN */ "", 64809 /* OLP_SPECIAL_CLOCK_CONTROLS */ "", 64810 /* OLP_TX_CONFIGS */ "", 64811 /* OLP_TX_CONFIGS_ARAD */ "", 64812 /* OLP_TX_CONFIGS_BCM_86650 */ "", 64813 /* OLP_TX_CONFIGS_PETRA_B */ "", 64814 /* OOBFC_CHANNEL_BASE_64 */ "OOBFC_CHANNEL_BASE", 64815 /* OOBFC_CHIF_CFG */ "", 64816 /* OOBFC_CHIF_CFG0 */ "", 64817 /* OOBFC_CHIF_CFG1 */ "", 64818 /* OOBFC_CHIF_CFG2 */ "", 64819 /* OOBFC_CHIF_CFG3 */ "", 64820 /* OOBFC_ENG_PORT_EN2 */ "OOBFC_ENG_PORT_EN2", 64821 /* OOBFC_ENG_PORT_EN0_64 */ "OOBFC_ENG_PORT_EN0", 64822 /* OOBFC_ENG_PORT_EN1_64 */ "OOBFC_ENG_PORT_EN1", 64823 /* OOBFC_ENG_PORT_EN_29 */ "OOBFC_ENG_PORT_EN", 64824 /* OOBFC_ENG_PORT_EN_41 */ "OOBFC_ENG_PORT_EN", 64825 /* OOBFC_ENG_PORT_EN_64 */ "OOBFC_ENG_PORT_EN", 64826 /* OOBFC_ENG_PORT_EN_0_64 */ "OOBFC_ENG_PORT_EN_0", 64827 /* OOBFC_ENG_PORT_EN_1_64 */ "OOBFC_ENG_PORT_EN_1", 64828 /* OOBFC_ENG_PORT_QSEL2 */ "OOBFC_ENG_PORT_QSEL2", 64829 /* OOBFC_ENG_PORT_QSEL0_64 */ "OOBFC_ENG_PORT_QSEL0", 64830 /* OOBFC_ENG_PORT_QSEL1_64 */ "OOBFC_ENG_PORT_QSEL1", 64831 /* OOBFC_ENG_PORT_QSEL_64 */ "OOBFC_ENG_PORT_QSEL", 64832 /* OOBFC_GCS */ "", 64833 /* OOBFC_INGRES_PORT_PG_PORT_ENA_64 */ "OOBFC_INGRES_PORT_PG_PORT_ENA", 64834 /* OOBFC_ING_PORT_EN2 */ "OOBFC_ING_PORT_EN2", 64835 /* OOBFC_ING_PORT_EN0_64 */ "OOBFC_ING_PORT_EN0", 64836 /* OOBFC_ING_PORT_EN1_64 */ "OOBFC_ING_PORT_EN1", 64837 /* OOBFC_ING_PORT_EN_29 */ "OOBFC_ING_PORT_EN", 64838 /* OOBFC_ING_PORT_EN_41 */ "OOBFC_ING_PORT_EN", 64839 /* OOBFC_ING_PORT_EN_64 */ "OOBFC_ING_PORT_EN", 64840 /* OOBFC_ING_PORT_EN_0_64 */ "OOBFC_ING_PORT_EN_0", 64841 /* OOBFC_ING_PORT_EN_1_64 */ "OOBFC_ING_PORT_EN_1", 64842 /* OOBFC_MSG_CRC_CNT */ "", 64843 /* OOBFC_MSG_CRC_CNT0 */ "", 64844 /* OOBFC_MSG_CRC_CNT1 */ "", 64845 /* OOBFC_MSG_CRC_CNT2 */ "", 64846 /* OOBFC_MSG_CRC_CNT3 */ "", 64847 /* OOBFC_MSG_REG0 */ "", 64848 /* OOBFC_MSG_REG1 */ "", 64849 /* OOBFC_MSG_RX_TOT_CNT */ "", 64850 /* OOBFC_MSG_RX_TOT_CNT0 */ "", 64851 /* OOBFC_MSG_RX_TOT_CNT1 */ "", 64852 /* OOBFC_MSG_RX_TOT_CNT2 */ "", 64853 /* OOBFC_MSG_RX_TOT_CNT3 */ "", 64854 /* OOBFC_MSG_TX_CNT */ "", 64855 /* OOBFC_STS */ "", 64856 /* OOBFC_TX_IDLE */ "", 64857 /* OOBFC_TX_MESSAGE_GAP */ "", 64858 /* OOBIF_DEBUG */ "", 64859 /* OOBIF_RX_TEST */ "", 64860 /* OOBIF_TX_TEST */ "", 64861 /* OOB_STATS_MSG_TX_CNT */ "", 64862 /* OOB_STATS_STS */ "", 64863 /* OOB_STATS_TX_IDLE */ "", 64864 /* OOB_STATS_TX_TEST */ "", 64865 /* OPAQUE_TAG_CONFIG_0 */ "", 64866 /* OPAQUE_TAG_CONFIG_1 */ "", 64867 /* OPP_SCHED_CFG */ "", 64868 /* OP_BUFFER_DROP_STATES */ "", 64869 /* OP_BUFFER_LIMIT_PRI0 */ "", 64870 /* OP_BUFFER_LIMIT_RED */ "", 64871 /* OP_BUFFER_LIMIT_RED_CELL */ "", 64872 /* OP_BUFFER_LIMIT_RED_CELLE */ "", 64873 /* OP_BUFFER_LIMIT_RED_CELLE_POOL0 */ "OP_BUFFER_LIMIT_RED_CELLE", 64874 /* OP_BUFFER_LIMIT_RED_CELLE_POOL1 */ "", 64875 /* OP_BUFFER_LIMIT_RED_CELLI */ "", 64876 /* OP_BUFFER_LIMIT_RED_PACKET */ "", 64877 /* OP_BUFFER_LIMIT_RED_QENTRY */ "", 64878 /* OP_BUFFER_LIMIT_RED_THDOEMA */ "", 64879 /* OP_BUFFER_LIMIT_RED_THDORDEQ */ "", 64880 /* OP_BUFFER_LIMIT_RED_THDORQEQ */ "", 64881 /* OP_BUFFER_LIMIT_RESUME_RED */ "", 64882 /* OP_BUFFER_LIMIT_RESUME_RED_CELL */ "", 64883 /* OP_BUFFER_LIMIT_RESUME_RED_CELLE */ "", 64884 /* OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0 */ "OP_BUFFER_LIMIT_RESUME_RED_CELLE", 64885 /* OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL1 */ "", 64886 /* OP_BUFFER_LIMIT_RESUME_RED_CELLI */ "", 64887 /* OP_BUFFER_LIMIT_RESUME_RED_PACKET */ "", 64888 /* OP_BUFFER_LIMIT_RESUME_RED_QENTRY */ "", 64889 /* OP_BUFFER_LIMIT_RESUME_RED_THDOEMA */ "", 64890 /* OP_BUFFER_LIMIT_RESUME_RED_THDORDEQ */ "", 64891 /* OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ */ "", 64892 /* OP_BUFFER_LIMIT_RESUME_YELLOW */ "", 64893 /* OP_BUFFER_LIMIT_RESUME_YELLOW_CELL */ "", 64894 /* OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE */ "", 64895 /* OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0 */ "OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE", 64896 /* OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL1 */ "", 64897 /* OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI */ "", 64898 /* OP_BUFFER_LIMIT_RESUME_YELLOW_PACKET */ "", 64899 /* OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY */ "", 64900 /* OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMA */ "", 64901 /* OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQ */ "", 64902 /* OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ */ "", 64903 /* OP_BUFFER_LIMIT_YELLOW */ "", 64904 /* OP_BUFFER_LIMIT_YELLOW_CELL */ "", 64905 /* OP_BUFFER_LIMIT_YELLOW_CELLE */ "", 64906 /* OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0 */ "OP_BUFFER_LIMIT_YELLOW_CELLE", 64907 /* OP_BUFFER_LIMIT_YELLOW_CELLE_POOL1 */ "", 64908 /* OP_BUFFER_LIMIT_YELLOW_CELLI */ "", 64909 /* OP_BUFFER_LIMIT_YELLOW_PACKET */ "", 64910 /* OP_BUFFER_LIMIT_YELLOW_QENTRY */ "", 64911 /* OP_BUFFER_LIMIT_YELLOW_THDOEMA */ "", 64912 /* OP_BUFFER_LIMIT_YELLOW_THDORDEQ */ "", 64913 /* OP_BUFFER_LIMIT_YELLOW_THDORQEQ */ "", 64914 /* OP_BUFFER_MAX_TOTAL_COUNT_CELL */ "", 64915 /* OP_BUFFER_SHARED_COUNT */ "", 64916 /* OP_BUFFER_SHARED_COUNT_CELL */ "", 64917 /* OP_BUFFER_SHARED_COUNT_CELLE */ "", 64918 /* OP_BUFFER_SHARED_COUNT_CELLE_POOL0 */ "OP_BUFFER_SHARED_COUNT_CELLE", 64919 /* OP_BUFFER_SHARED_COUNT_CELLE_POOL1 */ "", 64920 /* OP_BUFFER_SHARED_COUNT_CELLI */ "", 64921 /* OP_BUFFER_SHARED_COUNT_PACKET */ "", 64922 /* OP_BUFFER_SHARED_COUNT_QENTRY */ "", 64923 /* OP_BUFFER_SHARED_COUNT_THDOEMA */ "", 64924 /* OP_BUFFER_SHARED_COUNT_THDORDEQ */ "", 64925 /* OP_BUFFER_SHARED_COUNT_THDORQEQ */ "", 64926 /* OP_BUFFER_SHARED_LIMIT */ "", 64927 /* OP_BUFFER_SHARED_LIMIT_CELL */ "", 64928 /* OP_BUFFER_SHARED_LIMIT_CELLE */ "", 64929 /* OP_BUFFER_SHARED_LIMIT_CELLE_POOL0 */ "OP_BUFFER_SHARED_LIMIT_CELLE", 64930 /* OP_BUFFER_SHARED_LIMIT_CELLE_POOL1 */ "", 64931 /* OP_BUFFER_SHARED_LIMIT_CELLI */ "", 64932 /* OP_BUFFER_SHARED_LIMIT_PACKET */ "", 64933 /* OP_BUFFER_SHARED_LIMIT_QENTRY */ "", 64934 /* OP_BUFFER_SHARED_LIMIT_RESUME */ "", 64935 /* OP_BUFFER_SHARED_LIMIT_RESUME_CELL */ "", 64936 /* OP_BUFFER_SHARED_LIMIT_RESUME_CELLE */ "", 64937 /* OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0 */ "OP_BUFFER_SHARED_LIMIT_RESUME_CELLE", 64938 /* OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL1 */ "", 64939 /* OP_BUFFER_SHARED_LIMIT_RESUME_CELLI */ "", 64940 /* OP_BUFFER_SHARED_LIMIT_RESUME_PACKET */ "", 64941 /* OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY */ "", 64942 /* OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMA */ "", 64943 /* OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQ */ "", 64944 /* OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ */ "", 64945 /* OP_BUFFER_SHARED_LIMIT_THDOEMA */ "", 64946 /* OP_BUFFER_SHARED_LIMIT_THDORDEQ */ "", 64947 /* OP_BUFFER_SHARED_LIMIT_THDORQEQ */ "", 64948 /* OP_BUFFER_TOTAL_COUNT */ "", 64949 /* OP_BUFFER_TOTAL_COUNT_CELL */ "", 64950 /* OP_BUFFER_TOTAL_COUNT_PACKET */ "", 64951 /* OP_CPU_QUEUE_BST_STAT */ "THDO_CPU_QUEUE_BST_STAT", 64952 /* OP_CPU_QUEUE_BST_THRESHOLD */ "THDO_CPU_QUEUE_BST_THRESHOLD_PROFILE", 64953 /* OP_CPU_QUEUE_BST_THRESHOLD_PROFILE */ "THDO_CPU_QUEUE_BST_THRESHOLD", 64954 /* OP_CPU_QUEUE_BST_TRIGGER */ "OP_CPU_QUEUE_BST_TRIGGER", 64955 /* OP_E2ECC_PORT_CONFIG */ "", 64956 /* OP_EP_PORT_MAPPING_TABLE_0 */ "", 64957 /* OP_EP_PORT_MAPPING_TABLE_1 */ "", 64958 /* OP_EP_PORT_MAPPING_TABLE_2 */ "", 64959 /* OP_EX_PORT_CONFIG_COS_MIN_0 */ "", 64960 /* OP_EX_PORT_CONFIG_COS_MIN_1 */ "", 64961 /* OP_EX_PORT_CONFIG_COS_MIN_2 */ "", 64962 /* OP_EX_PORT_CONFIG_SPID_0 */ "", 64963 /* OP_EX_PORT_CONFIG_SPID_1 */ "", 64964 /* OP_EX_PORT_CONFIG_SPID_2 */ "", 64965 /* OP_EX_PORT_CONFIG_SPID_3 */ "", 64966 /* OP_EX_PORT_CONFIG_SPID_4 */ "", 64967 /* OP_EX_QUEUE_MIN_COUNT_CELL */ "", 64968 /* OP_EX_QUEUE_RESET_VALUE_CELL */ "", 64969 /* OP_EX_QUEUE_SHARED_COUNT_CELL */ "", 64970 /* OP_EX_QUEUE_TOTAL_COUNT_CELL */ "", 64971 /* OP_MCUC_SP_BST_STAT */ "THDO_SP_MCUC_BST_STAT", 64972 /* OP_MCUC_SP_BST_THRESHOLD */ "THDO_SP_MCUC_BST_THRESHOLD", 64973 /* OP_MC_SP_BST_STAT */ "THDO_SP_MC_BST_STAT", 64974 /* OP_MC_SP_BST_THRESHOLD */ "THDO_SP_MC_BST_THRESHOLD", 64975 /* OP_PORT_CONFIG */ "", 64976 /* OP_PORT_CONFIG1_CELL */ "", 64977 /* OP_PORT_CONFIGL */ "", 64978 /* OP_PORT_CONFIGU */ "", 64979 /* OP_PORT_CONFIG_CELL */ "", 64980 /* OP_PORT_CONFIG_PACKET */ "", 64981 /* OP_PORT_DROP_STATE_BMP */ "", 64982 /* OP_PORT_DROP_STATE_CELL_BMP0 */ "", 64983 /* OP_PORT_DROP_STATE_CELL_BMP1 */ "", 64984 /* OP_PORT_DROP_STATE_CELL_BMP0_64 */ "OP_PORT_DROP_STATE_CELL_BMP0", 64985 /* OP_PORT_DROP_STATE_CELL_BMP1_64 */ "OP_PORT_DROP_STATE_CELL_BMP1", 64986 /* OP_PORT_DROP_STATE_PACKET_BMP0 */ "", 64987 /* OP_PORT_DROP_STATE_PACKET_BMP1 */ "", 64988 /* OP_PORT_FIRST_FRAGMENT_COUNT_CELL */ "", 64989 /* OP_PORT_FIRST_FRAGMENT_COUNT_PACKET */ "", 64990 /* OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_CELL */ "", 64991 /* OP_PORT_FIRST_FRAGMENT_DISC_RESUME_THD_PACKET */ "", 64992 /* OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_CELL */ "", 64993 /* OP_PORT_FIRST_FRAGMENT_DISC_SET_THD_PACKET */ "", 64994 /* OP_PORT_LIMIT_COLOR_CELL */ "", 64995 /* OP_PORT_LIMIT_PRI0 */ "", 64996 /* OP_PORT_LIMIT_RED */ "", 64997 /* OP_PORT_LIMIT_RED_CELL */ "", 64998 /* OP_PORT_LIMIT_RED_PACKET */ "", 64999 /* OP_PORT_LIMIT_RESUME_COLOR_CELL */ "", 65000 /* OP_PORT_LIMIT_RESUME_RED_CELL */ "", 65001 /* OP_PORT_LIMIT_RESUME_RED_PACKET */ "", 65002 /* OP_PORT_LIMIT_RESUME_YELLOW_CELL */ "", 65003 /* OP_PORT_LIMIT_RESUME_YELLOW_PACKET */ "", 65004 /* OP_PORT_LIMIT_YELLOW */ "", 65005 /* OP_PORT_LIMIT_YELLOW_CELL */ "", 65006 /* OP_PORT_LIMIT_YELLOW_PACKET */ "", 65007 /* OP_PORT_MC_RED_DROP_STATE_CELL_BMP0_64 */ "OP_PORT_MC_RED_DROP_STATE_CELL_BMP0", 65008 /* OP_PORT_MC_YELLOW_DROP_STATE_CELL_BMP0_64 */ "OP_PORT_MC_YELLOW_DROP_STATE_CELL_BMP0", 65009 /* OP_PORT_REDIRECT_COUNT_CELL */ "", 65010 /* OP_PORT_REDIRECT_COUNT_PACKET */ "", 65011 /* OP_PORT_REDIRECT_DISC_RESUME_THD_CELL */ "", 65012 /* OP_PORT_REDIRECT_DISC_RESUME_THD_PACKET */ "", 65013 /* OP_PORT_REDIRECT_DISC_SET_THD_CELL */ "", 65014 /* OP_PORT_REDIRECT_DISC_SET_THD_PACKET */ "", 65015 /* OP_PORT_REDIRECT_XQ_COUNT_PACKET */ "", 65016 /* OP_PORT_REDIRECT_XQ_DISC_RESUME_THD_PACKET */ "", 65017 /* OP_PORT_REDIRECT_XQ_DISC_SET_THD_PACKET */ "", 65018 /* OP_PORT_SHARED_COUNT */ "", 65019 /* OP_PORT_SHARED_COUNT_CELL */ "", 65020 /* OP_PORT_SHARED_COUNT_PACKET */ "", 65021 /* OP_PORT_TOTAL_COUNT */ "", 65022 /* OP_PORT_TOTAL_COUNT_CELL */ "", 65023 /* OP_PORT_TOTAL_COUNT_PACKET */ "", 65024 /* OP_QUEUE_CONFIG */ "", 65025 /* OP_QUEUE_CONFIG1_CELL */ "", 65026 /* OP_QUEUE_CONFIG1_PACKET */ "", 65027 /* OP_QUEUE_CONFIG1_THDOEMA */ "", 65028 /* OP_QUEUE_CONFIG1_THDORDEE */ "", 65029 /* OP_QUEUE_CONFIG1_THDORDEI */ "", 65030 /* OP_QUEUE_CONFIG1_THDORDEQ */ "", 65031 /* OP_QUEUE_CONFIG1_THDORQEE */ "", 65032 /* OP_QUEUE_CONFIG1_THDORQEI */ "", 65033 /* OP_QUEUE_CONFIG1_THDORQEQ */ "", 65034 /* OP_QUEUE_CONFIGL */ "", 65035 /* OP_QUEUE_CONFIGU */ "", 65036 /* OP_QUEUE_CONFIG_CELL */ "", 65037 /* OP_QUEUE_CONFIG_PACKET */ "", 65038 /* OP_QUEUE_CONFIG_THDOEMA */ "", 65039 /* OP_QUEUE_CONFIG_THDORDEE */ "", 65040 /* OP_QUEUE_CONFIG_THDORDEI */ "", 65041 /* OP_QUEUE_CONFIG_THDORDEQ */ "", 65042 /* OP_QUEUE_CONFIG_THDORQEE */ "", 65043 /* OP_QUEUE_CONFIG_THDORQEI */ "", 65044 /* OP_QUEUE_CONFIG_THDORQEQ */ "", 65045 /* OP_QUEUE_FIRST_FRAGMENT_CONFIG_CELL */ "", 65046 /* OP_QUEUE_FIRST_FRAGMENT_CONFIG_PACKET */ "", 65047 /* OP_QUEUE_FIRST_FRAGMENT_COUNT_CELL */ "", 65048 /* OP_QUEUE_FIRST_FRAGMENT_COUNT_PACKET */ "", 65049 /* OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_CELL */ "", 65050 /* OP_QUEUE_FIRST_FRAGMENT_RESET_OFFSET_PACKET */ "", 65051 /* OP_QUEUE_LIMIT_COLOR_CELL */ "", 65052 /* OP_QUEUE_LIMIT_PRI0 */ "", 65053 /* OP_QUEUE_LIMIT_RED */ "", 65054 /* OP_QUEUE_LIMIT_RED_CELL */ "", 65055 /* OP_QUEUE_LIMIT_RED_PACKET */ "", 65056 /* OP_QUEUE_LIMIT_RED_THDOEMA */ "", 65057 /* OP_QUEUE_LIMIT_RED_THDORDEE */ "", 65058 /* OP_QUEUE_LIMIT_RED_THDORDEI */ "", 65059 /* OP_QUEUE_LIMIT_RED_THDORDEQ */ "", 65060 /* OP_QUEUE_LIMIT_RED_THDORQEE */ "", 65061 /* OP_QUEUE_LIMIT_RED_THDORQEI */ "", 65062 /* OP_QUEUE_LIMIT_RED_THDORQEQ */ "", 65063 /* OP_QUEUE_LIMIT_RESUME_COLOR_CELL */ "", 65064 /* OP_QUEUE_LIMIT_RESUME_COLOR_PACKET */ "", 65065 /* OP_QUEUE_LIMIT_YELLOW */ "", 65066 /* OP_QUEUE_LIMIT_YELLOW_CELL */ "", 65067 /* OP_QUEUE_LIMIT_YELLOW_PACKET */ "", 65068 /* OP_QUEUE_LIMIT_YELLOW_THDOEMA */ "", 65069 /* OP_QUEUE_LIMIT_YELLOW_THDORDEE */ "", 65070 /* OP_QUEUE_LIMIT_YELLOW_THDORDEI */ "", 65071 /* OP_QUEUE_LIMIT_YELLOW_THDORDEQ */ "", 65072 /* OP_QUEUE_LIMIT_YELLOW_THDORQEE */ "", 65073 /* OP_QUEUE_LIMIT_YELLOW_THDORQEI */ "", 65074 /* OP_QUEUE_LIMIT_YELLOW_THDORQEQ */ "", 65075 /* OP_QUEUE_MIN_COUNT */ "", 65076 /* OP_QUEUE_MIN_COUNT_CELL */ "", 65077 /* OP_QUEUE_MIN_COUNT_PACKET */ "", 65078 /* OP_QUEUE_MIN_COUNT_THDOEMA */ "", 65079 /* OP_QUEUE_MIN_COUNT_THDORDEE */ "", 65080 /* OP_QUEUE_MIN_COUNT_THDORDEI */ "", 65081 /* OP_QUEUE_MIN_COUNT_THDORDEQ */ "", 65082 /* OP_QUEUE_MIN_COUNT_THDORQEE */ "", 65083 /* OP_QUEUE_MIN_COUNT_THDORQEI */ "", 65084 /* OP_QUEUE_MIN_COUNT_THDORQEQ */ "", 65085 /* OP_QUEUE_REDIRECT_CONFIG_CELL */ "", 65086 /* OP_QUEUE_REDIRECT_CONFIG_PACKET */ "", 65087 /* OP_QUEUE_REDIRECT_COUNT_CELL */ "", 65088 /* OP_QUEUE_REDIRECT_COUNT_PACKET */ "", 65089 /* OP_QUEUE_REDIRECT_RESET_OFFSET_CELL */ "", 65090 /* OP_QUEUE_REDIRECT_RESET_OFFSET_PACKET */ "", 65091 /* OP_QUEUE_REDIRECT_XQ_CONFIG_PACKET */ "", 65092 /* OP_QUEUE_REDIRECT_XQ_COUNT_PACKET */ "", 65093 /* OP_QUEUE_REDIRECT_XQ_RESET_OFFSET_PACKET */ "", 65094 /* OP_QUEUE_RESET_OFFSET */ "", 65095 /* OP_QUEUE_RESET_OFFSET_CELL */ "", 65096 /* OP_QUEUE_RESET_OFFSET_PACKET */ "", 65097 /* OP_QUEUE_RESET_OFFSET_RED_THDOEMA */ "", 65098 /* OP_QUEUE_RESET_OFFSET_RED_THDORDEE */ "", 65099 /* OP_QUEUE_RESET_OFFSET_RED_THDORDEI */ "", 65100 /* OP_QUEUE_RESET_OFFSET_RED_THDORDEQ */ "", 65101 /* OP_QUEUE_RESET_OFFSET_RED_THDORQEE */ "", 65102 /* OP_QUEUE_RESET_OFFSET_RED_THDORQEI */ "", 65103 /* OP_QUEUE_RESET_OFFSET_RED_THDORQEQ */ "", 65104 /* OP_QUEUE_RESET_OFFSET_THDOEMA */ "", 65105 /* OP_QUEUE_RESET_OFFSET_THDORDEE */ "", 65106 /* OP_QUEUE_RESET_OFFSET_THDORDEI */ "", 65107 /* OP_QUEUE_RESET_OFFSET_THDORDEQ */ "", 65108 /* OP_QUEUE_RESET_OFFSET_THDORQEE */ "", 65109 /* OP_QUEUE_RESET_OFFSET_THDORQEI */ "", 65110 /* OP_QUEUE_RESET_OFFSET_THDORQEQ */ "", 65111 /* OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA */ "", 65112 /* OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEE */ "", 65113 /* OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEI */ "", 65114 /* OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ */ "", 65115 /* OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEE */ "", 65116 /* OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEI */ "", 65117 /* OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ */ "", 65118 /* OP_QUEUE_RESET_VALUE */ "", 65119 /* OP_QUEUE_RESET_VALUE_CELL */ "", 65120 /* OP_QUEUE_RESET_VALUE_PACKET */ "", 65121 /* OP_QUEUE_RESET_VALUE_THDOEMA */ "", 65122 /* OP_QUEUE_RESET_VALUE_THDORDEE */ "", 65123 /* OP_QUEUE_RESET_VALUE_THDORDEI */ "", 65124 /* OP_QUEUE_RESET_VALUE_THDORDEQ */ "", 65125 /* OP_QUEUE_RESET_VALUE_THDORQEE */ "", 65126 /* OP_QUEUE_RESET_VALUE_THDORQEI */ "", 65127 /* OP_QUEUE_RESET_VALUE_THDORQEQ */ "", 65128 /* OP_QUEUE_SHARED_COUNT */ "", 65129 /* OP_QUEUE_SHARED_COUNT_CELL */ "", 65130 /* OP_QUEUE_SHARED_COUNT_PACKET */ "", 65131 /* OP_QUEUE_SHARED_COUNT_THDOEMA */ "", 65132 /* OP_QUEUE_SHARED_COUNT_THDORDEE */ "", 65133 /* OP_QUEUE_SHARED_COUNT_THDORDEI */ "", 65134 /* OP_QUEUE_SHARED_COUNT_THDORDEQ */ "", 65135 /* OP_QUEUE_SHARED_COUNT_THDORQEE */ "", 65136 /* OP_QUEUE_SHARED_COUNT_THDORQEI */ "", 65137 /* OP_QUEUE_SHARED_COUNT_THDORQEQ */ "", 65138 /* OP_QUEUE_TOTAL_COUNT */ "", 65139 /* OP_QUEUE_TOTAL_COUNT_CELL */ "", 65140 /* OP_QUEUE_TOTAL_COUNT_PACKET */ "", 65141 /* OP_QUEUE_TOTAL_COUNT_THDOEMA */ "", 65142 /* OP_QUEUE_TOTAL_COUNT_THDORDEE */ "", 65143 /* OP_QUEUE_TOTAL_COUNT_THDORDEI */ "", 65144 /* OP_QUEUE_TOTAL_COUNT_THDORDEQ */ "", 65145 /* OP_QUEUE_TOTAL_COUNT_THDORQEE */ "", 65146 /* OP_QUEUE_TOTAL_COUNT_THDORQEI */ "", 65147 /* OP_QUEUE_TOTAL_COUNT_THDORQEQ */ "", 65148 /* OP_RESUME_OFFSET_COLOR_CELL_PROFILE */ "", 65149 /* OP_RESUME_OFFSET_COLOR_PACKET_PROFILE */ "", 65150 /* OP_SP_BST_THRESHOLD_SEL */ "", 65151 /* OP_THDU_CONFIG */ "", 65152 /* OP_THR_CONFIG */ "", 65153 /* OP_THR_CONFIG_PLUS */ "", 65154 /* OP_UC_PORT_BST_THRESHOLD */ "THDO_PORT_SP_BST_TRESHOLD", 65155 /* OP_UC_PORT_CONFIG1_CELL */ "", 65156 /* OP_UC_PORT_CONFIG_CELL */ "", 65157 /* OP_UC_PORT_DROP_STATE */ "", 65158 /* OP_UC_PORT_DROP_STATE_CELL_BMP0_64 */ "OP_UC_PORT_DROP_STATE_CELL_BMP0", 65159 /* OP_UC_PORT_DROP_STATE_CELL_BMP1_64 */ "OP_UC_PORT_DROP_STATE_CELL_BMP1", 65160 /* OP_UC_PORT_DROP_STATE_SPLIT0 */ "", 65161 /* OP_UC_PORT_DROP_STATE_SPLIT1 */ "", 65162 /* OP_UC_PORT_DROP_STATE_SPLIT0_XPE0 */ "", 65163 /* OP_UC_PORT_DROP_STATE_SPLIT1_XPE0 */ "", 65164 /* OP_UC_PORT_DROP_STATE_X */ "", 65165 /* OP_UC_PORT_DROP_STATE_X0 */ "", 65166 /* OP_UC_PORT_DROP_STATE_X1 */ "", 65167 /* OP_UC_PORT_DROP_STATE_XPE0 */ "", 65168 /* OP_UC_PORT_DROP_STATE_XPE1 */ "", 65169 /* OP_UC_PORT_DROP_STATE_XPE2 */ "", 65170 /* OP_UC_PORT_DROP_STATE_XPE3 */ "", 65171 /* OP_UC_PORT_DROP_STATE_Y */ "", 65172 /* OP_UC_PORT_LIMIT_COLOR_CELL */ "", 65173 /* OP_UC_PORT_LIMIT_RESUME_COLOR_CELL */ "", 65174 /* OP_UC_PORT_RED_DROP_STATE */ "", 65175 /* OP_UC_PORT_RED_DROP_STATE_SPLIT0 */ "", 65176 /* OP_UC_PORT_RED_DROP_STATE_SPLIT1 */ "", 65177 /* OP_UC_PORT_RED_DROP_STATE_SPLIT0_XPE0 */ "", 65178 /* OP_UC_PORT_RED_DROP_STATE_SPLIT1_XPE0 */ "", 65179 /* OP_UC_PORT_RED_DROP_STATE_X */ "", 65180 /* OP_UC_PORT_RED_DROP_STATE_X0 */ "", 65181 /* OP_UC_PORT_RED_DROP_STATE_X1 */ "", 65182 /* OP_UC_PORT_RED_DROP_STATE_XPE0 */ "", 65183 /* OP_UC_PORT_RED_DROP_STATE_XPE1 */ "", 65184 /* OP_UC_PORT_RED_DROP_STATE_XPE2 */ "", 65185 /* OP_UC_PORT_RED_DROP_STATE_XPE3 */ "", 65186 /* OP_UC_PORT_RED_DROP_STATE_Y */ "", 65187 /* OP_UC_PORT_SHARED_COUNT_CELL */ "", 65188 /* OP_UC_PORT_YELLOW_DROP_STATE */ "", 65189 /* OP_UC_PORT_YELLOW_DROP_STATE_SPLIT0 */ "", 65190 /* OP_UC_PORT_YELLOW_DROP_STATE_SPLIT1 */ "", 65191 /* OP_UC_PORT_YELLOW_DROP_STATE_SPLIT0_XPE0 */ "", 65192 /* OP_UC_PORT_YELLOW_DROP_STATE_SPLIT1_XPE0 */ "", 65193 /* OP_UC_PORT_YELLOW_DROP_STATE_X */ "", 65194 /* OP_UC_PORT_YELLOW_DROP_STATE_X0 */ "", 65195 /* OP_UC_PORT_YELLOW_DROP_STATE_X1 */ "", 65196 /* OP_UC_PORT_YELLOW_DROP_STATE_XPE0 */ "", 65197 /* OP_UC_PORT_YELLOW_DROP_STATE_XPE1 */ "", 65198 /* OP_UC_PORT_YELLOW_DROP_STATE_XPE2 */ "", 65199 /* OP_UC_PORT_YELLOW_DROP_STATE_XPE3 */ "", 65200 /* OP_UC_PORT_YELLOW_DROP_STATE_Y */ "", 65201 /* OP_UC_QGROUP_BST_THRESHOLD */ "THDO_UC_QGROUP_BST_THRESHOLD", 65202 /* OP_UC_QGROUP_DROP_STATE */ "", 65203 /* OP_UC_QGROUP_DROP_STATE_SPLIT0 */ "", 65204 /* OP_UC_QGROUP_DROP_STATE_SPLIT1 */ "", 65205 /* OP_UC_QGROUP_DROP_STATE_SPLIT0_XPE0 */ "", 65206 /* OP_UC_QGROUP_DROP_STATE_SPLIT1_XPE0 */ "", 65207 /* OP_UC_QGROUP_DROP_STATE_X */ "", 65208 /* OP_UC_QGROUP_DROP_STATE_XPE0 */ "", 65209 /* OP_UC_QGROUP_DROP_STATE_XPE1 */ "", 65210 /* OP_UC_QGROUP_DROP_STATE_XPE2 */ "", 65211 /* OP_UC_QGROUP_DROP_STATE_XPE3 */ "", 65212 /* OP_UC_QGROUP_DROP_STATE_Y */ "", 65213 /* OP_UC_QGROUP_RED_DROP_STATE */ "", 65214 /* OP_UC_QGROUP_RED_DROP_STATE_SPLIT0 */ "", 65215 /* OP_UC_QGROUP_RED_DROP_STATE_SPLIT1 */ "", 65216 /* OP_UC_QGROUP_RED_DROP_STATE_SPLIT0_XPE0 */ "", 65217 /* OP_UC_QGROUP_RED_DROP_STATE_SPLIT1_XPE0 */ "", 65218 /* OP_UC_QGROUP_RED_DROP_STATE_X */ "", 65219 /* OP_UC_QGROUP_RED_DROP_STATE_XPE0 */ "", 65220 /* OP_UC_QGROUP_RED_DROP_STATE_XPE1 */ "", 65221 /* OP_UC_QGROUP_RED_DROP_STATE_XPE2 */ "", 65222 /* OP_UC_QGROUP_RED_DROP_STATE_XPE3 */ "", 65223 /* OP_UC_QGROUP_RED_DROP_STATE_Y */ "", 65224 /* OP_UC_QGROUP_YELLOW_DROP_STATE */ "", 65225 /* OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT0 */ "", 65226 /* OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT1 */ "", 65227 /* OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT0_XPE0 */ "", 65228 /* OP_UC_QGROUP_YELLOW_DROP_STATE_SPLIT1_XPE0 */ "", 65229 /* OP_UC_QGROUP_YELLOW_DROP_STATE_X */ "", 65230 /* OP_UC_QGROUP_YELLOW_DROP_STATE_XPE0 */ "", 65231 /* OP_UC_QGROUP_YELLOW_DROP_STATE_XPE1 */ "", 65232 /* OP_UC_QGROUP_YELLOW_DROP_STATE_XPE2 */ "", 65233 /* OP_UC_QGROUP_YELLOW_DROP_STATE_XPE3 */ "", 65234 /* OP_UC_QGROUP_YELLOW_DROP_STATE_Y */ "", 65235 /* OP_UC_QUEUE_BST_THRESHOLD */ "THDO_UC_QUEUE_BST_THRESHOLD", 65236 /* OP_UC_QUEUE_DROP_STATE */ "", 65237 /* OP_UC_QUEUE_DROP_STATE_X */ "", 65238 /* OP_UC_QUEUE_DROP_STATE_XPE0 */ "", 65239 /* OP_UC_QUEUE_DROP_STATE_XPE1 */ "", 65240 /* OP_UC_QUEUE_DROP_STATE_XPE2 */ "", 65241 /* OP_UC_QUEUE_DROP_STATE_XPE3 */ "", 65242 /* OP_UC_QUEUE_DROP_STATE_Y */ "", 65243 /* OP_UC_QUEUE_MIN_COUNT_CELL */ "", 65244 /* OP_UC_QUEUE_RED_DROP_STATE */ "", 65245 /* OP_UC_QUEUE_RED_DROP_STATE_X */ "", 65246 /* OP_UC_QUEUE_RED_DROP_STATE_XPE0 */ "", 65247 /* OP_UC_QUEUE_RED_DROP_STATE_XPE1 */ "", 65248 /* OP_UC_QUEUE_RED_DROP_STATE_XPE2 */ "", 65249 /* OP_UC_QUEUE_RED_DROP_STATE_XPE3 */ "", 65250 /* OP_UC_QUEUE_RED_DROP_STATE_Y */ "", 65251 /* OP_UC_QUEUE_RESET_VALUE_CELL */ "", 65252 /* OP_UC_QUEUE_SHARED_COUNT_CELL */ "", 65253 /* OP_UC_QUEUE_TOTAL_COUNT_CELL */ "", 65254 /* OP_UC_QUEUE_YELLOW_DROP_STATE */ "", 65255 /* OP_UC_QUEUE_YELLOW_DROP_STATE_X */ "", 65256 /* OP_UC_QUEUE_YELLOW_DROP_STATE_XPE0 */ "", 65257 /* OP_UC_QUEUE_YELLOW_DROP_STATE_XPE1 */ "", 65258 /* OP_UC_QUEUE_YELLOW_DROP_STATE_XPE2 */ "", 65259 /* OP_UC_QUEUE_YELLOW_DROP_STATE_XPE3 */ "", 65260 /* OP_UC_QUEUE_YELLOW_DROP_STATE_Y */ "", 65261 /* OP_VOQ_MOP1B_CONFIG */ "", 65262 /* OP_VOQ_PORT_CONFIG */ "", 65263 /* OSC_EN */ "", 65264 /* OTPC_2_CONTROL */ "", 65265 /* OTPC_2_KEY0 */ "", 65266 /* OTPC_2_KEY1 */ "", 65267 /* OTPC_2_KEY2 */ "", 65268 /* OTPC_2_KEY3 */ "", 65269 /* OTPC_2_STATUS */ "", 65270 /* OTPC_CMD_START */ "", 65271 /* OTPC_CNTRL_0 */ "", 65272 /* OTPC_CNTRL_1 */ "", 65273 /* OTPC_COMMAND */ "", 65274 /* OTPC_CPUADDR_REG */ "", 65275 /* OTPC_CPU_DATA */ "", 65276 /* OTPC_CPU_STATUS */ "", 65277 /* OTPC_CPU_WRITE_REG */ "", 65278 /* OTPC_MODE_REG */ "", 65279 /* OTPC_SOFT_RESET_CNTRL */ "", 65280 /* OUTER_L2_FOR_IFP_AND_TRUNK */ "", 65281 /* OUTER_TPID_0 */ "", 65282 /* OUTER_TPID_1 */ "", 65283 /* OUTER_TPID_2 */ "", 65284 /* OUTER_TPID_3 */ "", 65285 /* OUTPUT_PORT_RX_ENABLE */ "", 65286 /* OUTPUT_PORT_RX_ENABLE0_64 */ "OUTPUT_PORT_RX_ENABLE0", 65287 /* OUTPUT_PORT_RX_ENABLE1_64 */ "OUTPUT_PORT_RX_ENABLE1", 65288 /* OUTPUT_PORT_RX_ENABLE_64 */ "OUTPUT_PORT_RX_ENABLE", 65289 /* OVERLAY_MODE */ "", 65290 /* OVF_L2_HITDA_ONLY */ "", 65291 /* OVF_L2_HITSA_ONLY */ "", 65292 /* OVQ_ADDRESS_RANGE_0 */ "", 65293 /* OVQ_ADDRESS_RANGE_1 */ "", 65294 /* OVQ_ADDRESS_RANGE_2 */ "", 65295 /* OVQ_ADDRESS_RANGE_3 */ "", 65296 /* OVQ_BLOCK_COUNTER */ "", 65297 /* OVQ_BUBBLE_SIZE_REG */ "", 65298 /* OVQ_BUBBLE_THRESHOLD */ "", 65299 /* OVQ_DFT */ "", 65300 /* OVQ_DISTRIBUTOR_DFT */ "", 65301 /* OVQ_DROP_THRESHOLD0 */ "", 65302 /* OVQ_DROP_THRESHOLD_REG */ "", 65303 /* OVQ_DROP_THRESHOLD_RESET_LIMIT */ "", 65304 /* OVQ_ECC_BITMAP */ "", 65305 /* OVQ_FLOWCONTROL_COUNTER */ "", 65306 /* OVQ_FLOWCONTROL_THRESHOLD */ "", 65307 /* OVQ_LINKED_LIST_REG */ "", 65308 /* OVQ_LINKED_LIST_SELECT */ "", 65309 /* OVQ_LINKED_NEXTPTR */ "", 65310 /* OVQ_LINKED_REG */ "", 65311 /* OVQ_MCQ_CREDITS */ "", 65312 /* OVQ_MCQ_STATE */ "", 65313 /* OVQ_SCANNER_MAX_POINTER */ "", 65314 /* OVQ_SCANNER_POINTER */ "", 65315 /* OVR_SUB_GRP0_TBL */ "", 65316 /* OVR_SUB_GRP1_TBL */ "", 65317 /* OVR_SUB_GRP2_TBL */ "", 65318 /* OVR_SUB_GRP3_TBL */ "", 65319 /* OVR_SUB_GRP4_TBL */ "", 65320 /* OVR_SUB_GRP5_TBL */ "", 65321 /* OVR_SUB_GRP6_TBL */ "", 65322 /* OVR_SUB_GRP7_TBL */ "", 65323 /* OVR_SUB_GRP_CFG */ "", 65324 /* PACKET_RESET_LIMIT_OFFSET_SP */ "", 65325 /* PACKET_SPAP_RED_OFFSET_SP */ "", 65326 /* PACKET_SPAP_YELLOW_OFFSET_SP */ "", 65327 /* PARITY_CHK_EN */ "", 65328 /* PARITY_EN */ "", 65329 /* PARITY_ERROR_COUNTER */ "", 65330 /* PARITY_ERROR_INTR_MASK */ "", 65331 /* PARITY_ERROR_STATUS_0 */ "", 65332 /* PARITY_ERROR_STATUS_1 */ "", 65333 /* PARITY_ERROR_STATUS_0_64 */ "", 65334 /* PARSER0_DEBUG_CONTROL */ "", 65335 /* PARSER0_DEBUG_CONTROL_PIPE0 */ "", 65336 /* PARSER0_DEBUG_CONTROL_PIPE1 */ "", 65337 /* PARSER0_OPAQUE_CONTAINER_SELECT */ "", 65338 /* PARSER1_CONFIG */ "", 65339 /* PARSER1_DEBUG_CONTROL */ "", 65340 /* PARSER1_DEBUG_CONTROL_PIPE0 */ "", 65341 /* PARSER1_DEBUG_CONTROL_PIPE1 */ "", 65342 /* PARSER1_DOS_CONTROL_3 */ "", 65343 /* PARSER1_FLEXIBLE_IPV6_EXT_HDR */ "", 65344 /* PARSER1_HVE_TCP_PARSE_CONTROL */ "", 65345 /* PARSER1_ING_INNER_TPID */ "", 65346 /* PARSER1_ING_INNER_TPID_0 */ "", 65347 /* PARSER1_ING_INNER_TPID_1 */ "", 65348 /* PARSER1_ING_INNER_TPID_2 */ "", 65349 /* PARSER1_ING_INNER_TPID_3 */ "", 65350 /* PARSER1_ING_OUTER_TPID */ "", 65351 /* PARSER1_ING_OUTER_TPID_0 */ "", 65352 /* PARSER1_ING_OUTER_TPID_1 */ "", 65353 /* PARSER1_ING_OUTER_TPID_2 */ "", 65354 /* PARSER1_ING_OUTER_TPID_3 */ "", 65355 /* PARSER1_IPV6_MIN_FRAG_SIZE */ "", 65356 /* PARSER1_USER_DEFINED_1_ETHERTYPE */ "", 65357 /* PARSER1_USER_DEFINED_1_IP_PROTOCOL */ "", 65358 /* PARSER1_USER_DEFINED_1_UDP_DEST_PORT */ "", 65359 /* PARSER1_USER_DEFINED_2_ETHERTYPE */ "", 65360 /* PARSER1_USER_DEFINED_2_IP_PROTOCOL */ "", 65361 /* PARSER1_USER_DEFINED_2_UDP_DEST_PORT */ "", 65362 /* PARSER2_CONFIG */ "", 65363 /* PARSER2_DEBUG_CONTROL */ "", 65364 /* PARSER2_DEBUG_CONTROL_PIPE0 */ "", 65365 /* PARSER2_DEBUG_CONTROL_PIPE1 */ "", 65366 /* PARSER2_DOS_CONTROL_3 */ "", 65367 /* PARSER2_FLEXIBLE_IPV6_EXT_HDR */ "", 65368 /* PARSER2_HVE_TCP_PARSE_CONTROL */ "", 65369 /* PARSER2_ING_INNER_TPID */ "", 65370 /* PARSER2_ING_INNER_TPID_0 */ "", 65371 /* PARSER2_ING_INNER_TPID_1 */ "", 65372 /* PARSER2_ING_INNER_TPID_2 */ "", 65373 /* PARSER2_ING_INNER_TPID_3 */ "", 65374 /* PARSER2_ING_OUTER_TPID */ "", 65375 /* PARSER2_ING_OUTER_TPID_0 */ "", 65376 /* PARSER2_ING_OUTER_TPID_1 */ "", 65377 /* PARSER2_ING_OUTER_TPID_2 */ "", 65378 /* PARSER2_ING_OUTER_TPID_3 */ "", 65379 /* PARSER2_IPV6_MIN_FRAG_SIZE */ "", 65380 /* PARSER2_USER_DEFINED_1_ETHERTYPE */ "", 65381 /* PARSER2_USER_DEFINED_1_IP_PROTOCOL */ "", 65382 /* PARSER2_USER_DEFINED_1_UDP_DEST_PORT */ "", 65383 /* PARSER2_USER_DEFINED_2_ETHERTYPE */ "", 65384 /* PARSER2_USER_DEFINED_2_IP_PROTOCOL */ "", 65385 /* PARSER2_USER_DEFINED_2_UDP_DEST_PORT */ "", 65386 /* PARS_LPORT_N_CPUTS_DBGCTRL */ "PARS_LPORT_N_CPUTS_CONTROL", 65387 /* PARS_N_VLAN_DBGCTRL */ "PARS_N_VLAN_CONTROL", 65388 /* PARS_PKT_N_UDF_DBGCTR */ "PARS_PKT_N_UDF_CONTROL", 65389 /* PARS_RAM_CONTROL */ "", 65390 /* PARS_RAM_CONTROL_PIPE0 */ "", 65391 /* PARS_RAM_CONTROL_PIPE1 */ "", 65392 /* PARS_RAM_CONTROL_PIPE2 */ "", 65393 /* PARS_RAM_CONTROL_PIPE3 */ "", 65394 /* PARS_RAM_CONTROL_PIPE4 */ "", 65395 /* PARS_RAM_CONTROL_PIPE5 */ "", 65396 /* PARS_RAM_CONTROL_PIPE6 */ "", 65397 /* PARS_RAM_CONTROL_PIPE7 */ "", 65398 /* PARS_RAM_DBGCTRL */ "PARS_RAM_CONTROL", 65399 /* PARS_RAM_DBGCTRL_1 */ "PARS_RAM_CONTROL1", 65400 /* PARS_RAM_DBGCTRL_2 */ "PARS_RAM_CONTROL_2", 65401 /* PARS_RAM_DBGCTRL_1_PIPE0 */ "PARS_RAM_CONTROL1_PIPE0", 65402 /* PARS_RAM_DBGCTRL_1_PIPE1 */ "PARS_RAM_CONTROL1_PIPE1", 65403 /* PARS_RAM_DBGCTRL_1_PIPE2 */ "PARS_RAM_CONTROL1_PIPE2", 65404 /* PARS_RAM_DBGCTRL_1_PIPE3 */ "PARS_RAM_CONTROL1_PIPE3", 65405 /* PARS_RAM_DBGCTRL_2_64 */ "PARS_RAM_CONTROL2", 65406 /* PARS_RAM_DBGCTRL_2_64_PIPE0 */ "PARS_RAM_CONTROL2_PIPE0", 65407 /* PARS_RAM_DBGCTRL_2_64_PIPE1 */ "PARS_RAM_CONTROL2_PIPE1", 65408 /* PARS_RAM_DBGCTRL_2_64_PIPE2 */ "PARS_RAM_CONTROL2_PIPE2", 65409 /* PARS_RAM_DBGCTRL_2_64_PIPE3 */ "PARS_RAM_CONTROL2_PIPE3", 65410 /* PARS_RAM_DBGCTRL_PIPE0 */ "PARS_RAM_CONTROL_PIPE0", 65411 /* PARS_RAM_DBGCTRL_PIPE1 */ "PARS_RAM_CONTROL_PIPE1", 65412 /* PARS_RAM_DBGCTRL_PIPE2 */ "PARS_RAM_CONTROL_PIPE2", 65413 /* PARS_RAM_DBGCTRL_PIPE3 */ "PARS_RAM_CONTROL_PIPE3", 65414 /* PARS_SER_CONTROL */ "", 65415 /* PARS_SRCTRUNKMAP_DBGCTRL */ "PARS_SRCTRUNKMAP_CONTROL", 65416 /* PARS_SRCTRUNKMAP_MODBASE_DBGCTRL */ "PARS_SRCTRUNKMAP_MODBASE_CONTROL", 65417 /* PARS_SRCTRUNKMAP_N_VLAN_DBGCTRL */ "PARS_SRCTRUNKMAP_N_VLAN_CONTROL", 65418 /* PARS_SR_LPORT_PROFILE_CONTROL */ "", 65419 /* PARTIAL_EDIT_CTRL_ID_CONFIG */ "", 65420 /* PASSTHRU_NLF_MTU_CHECK */ "", 65421 /* PASS_CONTROL_FRAME */ "", 65422 /* PAUSE_CONTROL */ "", 65423 /* PAUSE_QUANT */ "", 65424 /* PAXB_0_APB_ERR_EN_FOR_CFG_RD_CMPL */ "", 65425 /* PAXB_0_APB_TIMEOUT_COUNT */ "", 65426 /* PAXB_0_AXI_SLVERR_EN_FOR_MEM_RD_CMPL */ "", 65427 /* PAXB_0_CFG_ADDR */ "", 65428 /* PAXB_0_CFG_DATA */ "", 65429 /* PAXB_0_CLK_CONTROL */ "", 65430 /* PAXB_0_CMICD_TO_PCIE_INTR_EN */ "", 65431 /* PAXB_0_CONFIG_IND_ADDR */ "", 65432 /* PAXB_0_CONFIG_IND_DATA */ "", 65433 /* PAXB_0_EP_LTR_CONTROL */ "", 65434 /* PAXB_0_EP_LTR_STATUS */ "", 65435 /* PAXB_0_EP_OBFF_STATUS */ "", 65436 /* PAXB_0_EP_PM_CONTROL */ "", 65437 /* PAXB_0_EP_PM_STATUS */ "", 65438 /* PAXB_0_FUNC0_IMAP1 */ "", 65439 /* PAXB_0_FUNC0_IMAP2 */ "", 65440 /* PAXB_0_FUNC0_IMAP0_0 */ "", 65441 /* PAXB_0_FUNC0_IMAP0_1 */ "", 65442 /* PAXB_0_FUNC0_IMAP0_2 */ "", 65443 /* PAXB_0_FUNC0_IMAP0_3 */ "", 65444 /* PAXB_0_FUNC0_IMAP0_4 */ "", 65445 /* PAXB_0_FUNC0_IMAP0_5 */ "", 65446 /* PAXB_0_FUNC0_IMAP0_6 */ "", 65447 /* PAXB_0_FUNC0_IMAP0_7 */ "", 65448 /* PAXB_0_FUNC0_IMAP0_0123_REGS_TYPE */ "", 65449 /* PAXB_0_FUNC0_IMAP0_0_UPPER */ "", 65450 /* PAXB_0_FUNC0_IMAP0_1_UPPER */ "", 65451 /* PAXB_0_FUNC0_IMAP0_2_UPPER */ "", 65452 /* PAXB_0_FUNC0_IMAP0_3_UPPER */ "", 65453 /* PAXB_0_FUNC0_IMAP0_4_UPPER */ "", 65454 /* PAXB_0_FUNC0_IMAP0_5_UPPER */ "", 65455 /* PAXB_0_FUNC0_IMAP0_6_UPPER */ "", 65456 /* PAXB_0_FUNC0_IMAP0_7_UPPER */ "", 65457 /* PAXB_0_FUNC0_IMAP1_0 */ "", 65458 /* PAXB_0_FUNC0_IMAP1_1 */ "", 65459 /* PAXB_0_FUNC0_IMAP1_2 */ "", 65460 /* PAXB_0_FUNC0_IMAP1_3 */ "", 65461 /* PAXB_0_FUNC0_IMAP1_4 */ "", 65462 /* PAXB_0_FUNC0_IMAP1_5 */ "", 65463 /* PAXB_0_FUNC0_IMAP1_6 */ "", 65464 /* PAXB_0_FUNC0_IMAP1_7 */ "", 65465 /* PAXB_0_FUNC0_IMAP1_0_UPPER */ "", 65466 /* PAXB_0_FUNC0_IMAP1_1_UPPER */ "", 65467 /* PAXB_0_FUNC0_IMAP1_2_UPPER */ "", 65468 /* PAXB_0_FUNC0_IMAP1_3_UPPER */ "", 65469 /* PAXB_0_FUNC0_IMAP1_4_UPPER */ "", 65470 /* PAXB_0_FUNC0_IMAP1_5_UPPER */ "", 65471 /* PAXB_0_FUNC0_IMAP1_6_UPPER */ "", 65472 /* PAXB_0_FUNC0_IMAP1_7_UPPER */ "", 65473 /* PAXB_0_FUNC0_IMAP1_UPPER */ "", 65474 /* PAXB_0_FUNC0_IMAP2_UPPER */ "", 65475 /* PAXB_0_FUNC0_MSIX_ADDR_RAM_ECC_LOG */ "", 65476 /* PAXB_0_FUNC0_MSIX_DATA_RAM_ECC_LOG */ "", 65477 /* PAXB_0_FUNC1_IARR_1_SIZE */ "", 65478 /* PAXB_0_FUNC1_IARR_2_SIZE */ "", 65479 /* PAXB_0_FUNC1_IMAP1 */ "", 65480 /* PAXB_0_FUNC1_IMAP2 */ "", 65481 /* PAXB_0_FUNC1_IMAP0_0 */ "", 65482 /* PAXB_0_FUNC1_IMAP0_1 */ "", 65483 /* PAXB_0_FUNC1_IMAP0_2 */ "", 65484 /* PAXB_0_FUNC1_IMAP0_3 */ "", 65485 /* PAXB_0_FUNC1_IMAP0_4 */ "", 65486 /* PAXB_0_FUNC1_IMAP0_5 */ "", 65487 /* PAXB_0_FUNC1_IMAP0_6 */ "", 65488 /* PAXB_0_FUNC1_IMAP0_7 */ "", 65489 /* PAXB_0_FUNC1_IMAP0_0_UPPER */ "", 65490 /* PAXB_0_FUNC1_IMAP0_1_UPPER */ "", 65491 /* PAXB_0_FUNC1_IMAP0_2_UPPER */ "", 65492 /* PAXB_0_FUNC1_IMAP0_3_UPPER */ "", 65493 /* PAXB_0_FUNC1_IMAP0_4_UPPER */ "", 65494 /* PAXB_0_FUNC1_IMAP0_5_UPPER */ "", 65495 /* PAXB_0_FUNC1_IMAP0_6_UPPER */ "", 65496 /* PAXB_0_FUNC1_IMAP0_7_UPPER */ "", 65497 /* PAXB_0_FUNC1_IMAP1_0 */ "", 65498 /* PAXB_0_FUNC1_IMAP1_1 */ "", 65499 /* PAXB_0_FUNC1_IMAP1_2 */ "", 65500 /* PAXB_0_FUNC1_IMAP1_3 */ "", 65501 /* PAXB_0_FUNC1_IMAP1_4 */ "", 65502 /* PAXB_0_FUNC1_IMAP1_5 */ "", 65503 /* PAXB_0_FUNC1_IMAP1_6 */ "", 65504 /* PAXB_0_FUNC1_IMAP1_7 */ "", 65505 /* PAXB_0_FUNC1_IMAP1_0_UPPER */ "", 65506 /* PAXB_0_FUNC1_IMAP1_1_UPPER */ "", 65507 /* PAXB_0_FUNC1_IMAP1_2_UPPER */ "", 65508 /* PAXB_0_FUNC1_IMAP1_3_UPPER */ "", 65509 /* PAXB_0_FUNC1_IMAP1_4_UPPER */ "", 65510 /* PAXB_0_FUNC1_IMAP1_5_UPPER */ "", 65511 /* PAXB_0_FUNC1_IMAP1_6_UPPER */ "", 65512 /* PAXB_0_FUNC1_IMAP1_7_UPPER */ "", 65513 /* PAXB_0_FUNC1_IMAP1_UPPER */ "", 65514 /* PAXB_0_FUNC1_IMAP2_UPPER */ "", 65515 /* PAXB_0_GEN3_UC_LOADER_STATUS */ "", 65516 /* PAXB_0_IARR_0_LOWER */ "", 65517 /* PAXB_0_IARR_0_UPPER */ "", 65518 /* PAXB_0_IARR_1_LOWER */ "", 65519 /* PAXB_0_IARR_1_UPPER */ "", 65520 /* PAXB_0_IARR_2_LOWER */ "", 65521 /* PAXB_0_IARR_2_UPPER */ "", 65522 /* PAXB_0_IPROC_INTR_CTRL */ "", 65523 /* PAXB_0_MEM_CONTROL */ "", 65524 /* PAXB_0_MEM_ECC_ERR_LOG_0 */ "", 65525 /* PAXB_0_MEM_ECC_ERR_LOG_1 */ "", 65526 /* PAXB_0_MISC_INTR_EN */ "", 65527 /* PAXB_0_MSIX_PBA_VECT_31_0 */ "", 65528 /* PAXB_0_MSIX_PBA_VECT_63_32 */ "", 65529 /* PAXB_0_MSIX_TABLE_DATA_VECT0 */ "", 65530 /* PAXB_0_MSIX_TABLE_DATA_VECT1 */ "", 65531 /* PAXB_0_MSIX_TABLE_DATA_VECT2 */ "", 65532 /* PAXB_0_MSIX_TABLE_DATA_VECT3 */ "", 65533 /* PAXB_0_MSIX_TABLE_DATA_VECT4 */ "", 65534 /* PAXB_0_MSIX_TABLE_DATA_VECT5 */ "", 65535 /* PAXB_0_MSIX_TABLE_DATA_VECT6 */ "", 65536 /* PAXB_0_MSIX_TABLE_DATA_VECT7 */ "", 65537 /* PAXB_0_MSIX_TABLE_DATA_VECT8 */ "", 65538 /* PAXB_0_MSIX_TABLE_DATA_VECT9 */ "", 65539 /* PAXB_0_MSIX_TABLE_DATA_VECT10 */ "", 65540 /* PAXB_0_MSIX_TABLE_DATA_VECT11 */ "", 65541 /* PAXB_0_MSIX_TABLE_DATA_VECT12 */ "", 65542 /* PAXB_0_MSIX_TABLE_DATA_VECT13 */ "", 65543 /* PAXB_0_MSIX_TABLE_DATA_VECT14 */ "", 65544 /* PAXB_0_MSIX_TABLE_DATA_VECT15 */ "", 65545 /* PAXB_0_MSIX_TABLE_DATA_VECT16 */ "", 65546 /* PAXB_0_MSIX_TABLE_DATA_VECT17 */ "", 65547 /* PAXB_0_MSIX_TABLE_DATA_VECT18 */ "", 65548 /* PAXB_0_MSIX_TABLE_DATA_VECT19 */ "", 65549 /* PAXB_0_MSIX_TABLE_DATA_VECT20 */ "", 65550 /* PAXB_0_MSIX_TABLE_DATA_VECT21 */ "", 65551 /* PAXB_0_MSIX_TABLE_DATA_VECT22 */ "", 65552 /* PAXB_0_MSIX_TABLE_DATA_VECT23 */ "", 65553 /* PAXB_0_MSIX_TABLE_DATA_VECT24 */ "", 65554 /* PAXB_0_MSIX_TABLE_DATA_VECT25 */ "", 65555 /* PAXB_0_MSIX_TABLE_DATA_VECT26 */ "", 65556 /* PAXB_0_MSIX_TABLE_DATA_VECT27 */ "", 65557 /* PAXB_0_MSIX_TABLE_DATA_VECT28 */ "", 65558 /* PAXB_0_MSIX_TABLE_DATA_VECT29 */ "", 65559 /* PAXB_0_MSIX_TABLE_DATA_VECT30 */ "", 65560 /* PAXB_0_MSIX_TABLE_DATA_VECT31 */ "", 65561 /* PAXB_0_MSIX_TABLE_DATA_VECT32 */ "", 65562 /* PAXB_0_MSIX_TABLE_DATA_VECT33 */ "", 65563 /* PAXB_0_MSIX_TABLE_DATA_VECT34 */ "", 65564 /* PAXB_0_MSIX_TABLE_DATA_VECT35 */ "", 65565 /* PAXB_0_MSIX_TABLE_DATA_VECT36 */ "", 65566 /* PAXB_0_MSIX_TABLE_DATA_VECT37 */ "", 65567 /* PAXB_0_MSIX_TABLE_DATA_VECT38 */ "", 65568 /* PAXB_0_MSIX_TABLE_DATA_VECT39 */ "", 65569 /* PAXB_0_MSIX_TABLE_DATA_VECT40 */ "", 65570 /* PAXB_0_MSIX_TABLE_DATA_VECT41 */ "", 65571 /* PAXB_0_MSIX_TABLE_DATA_VECT42 */ "", 65572 /* PAXB_0_MSIX_TABLE_DATA_VECT43 */ "", 65573 /* PAXB_0_MSIX_TABLE_DATA_VECT44 */ "", 65574 /* PAXB_0_MSIX_TABLE_DATA_VECT45 */ "", 65575 /* PAXB_0_MSIX_TABLE_DATA_VECT46 */ "", 65576 /* PAXB_0_MSIX_TABLE_DATA_VECT47 */ "", 65577 /* PAXB_0_MSIX_TABLE_DATA_VECT48 */ "", 65578 /* PAXB_0_MSIX_TABLE_DATA_VECT49 */ "", 65579 /* PAXB_0_MSIX_TABLE_DATA_VECT50 */ "", 65580 /* PAXB_0_MSIX_TABLE_DATA_VECT51 */ "", 65581 /* PAXB_0_MSIX_TABLE_DATA_VECT52 */ "", 65582 /* PAXB_0_MSIX_TABLE_DATA_VECT53 */ "", 65583 /* PAXB_0_MSIX_TABLE_DATA_VECT54 */ "", 65584 /* PAXB_0_MSIX_TABLE_DATA_VECT55 */ "", 65585 /* PAXB_0_MSIX_TABLE_DATA_VECT56 */ "", 65586 /* PAXB_0_MSIX_TABLE_DATA_VECT57 */ "", 65587 /* PAXB_0_MSIX_TABLE_DATA_VECT58 */ "", 65588 /* PAXB_0_MSIX_TABLE_DATA_VECT59 */ "", 65589 /* PAXB_0_MSIX_TABLE_DATA_VECT60 */ "", 65590 /* PAXB_0_MSIX_TABLE_DATA_VECT61 */ "", 65591 /* PAXB_0_MSIX_TABLE_DATA_VECT62 */ "", 65592 /* PAXB_0_MSIX_TABLE_DATA_VECT63 */ "", 65593 /* PAXB_0_MSIX_TABLE_LADDR_VECT0 */ "", 65594 /* PAXB_0_MSIX_TABLE_LADDR_VECT1 */ "", 65595 /* PAXB_0_MSIX_TABLE_LADDR_VECT2 */ "", 65596 /* PAXB_0_MSIX_TABLE_LADDR_VECT3 */ "", 65597 /* PAXB_0_MSIX_TABLE_LADDR_VECT4 */ "", 65598 /* PAXB_0_MSIX_TABLE_LADDR_VECT5 */ "", 65599 /* PAXB_0_MSIX_TABLE_LADDR_VECT6 */ "", 65600 /* PAXB_0_MSIX_TABLE_LADDR_VECT7 */ "", 65601 /* PAXB_0_MSIX_TABLE_LADDR_VECT8 */ "", 65602 /* PAXB_0_MSIX_TABLE_LADDR_VECT9 */ "", 65603 /* PAXB_0_MSIX_TABLE_LADDR_VECT10 */ "", 65604 /* PAXB_0_MSIX_TABLE_LADDR_VECT11 */ "", 65605 /* PAXB_0_MSIX_TABLE_LADDR_VECT12 */ "", 65606 /* PAXB_0_MSIX_TABLE_LADDR_VECT13 */ "", 65607 /* PAXB_0_MSIX_TABLE_LADDR_VECT14 */ "", 65608 /* PAXB_0_MSIX_TABLE_LADDR_VECT15 */ "", 65609 /* PAXB_0_MSIX_TABLE_LADDR_VECT16 */ "", 65610 /* PAXB_0_MSIX_TABLE_LADDR_VECT17 */ "", 65611 /* PAXB_0_MSIX_TABLE_LADDR_VECT18 */ "", 65612 /* PAXB_0_MSIX_TABLE_LADDR_VECT19 */ "", 65613 /* PAXB_0_MSIX_TABLE_LADDR_VECT20 */ "", 65614 /* PAXB_0_MSIX_TABLE_LADDR_VECT21 */ "", 65615 /* PAXB_0_MSIX_TABLE_LADDR_VECT22 */ "", 65616 /* PAXB_0_MSIX_TABLE_LADDR_VECT23 */ "", 65617 /* PAXB_0_MSIX_TABLE_LADDR_VECT24 */ "", 65618 /* PAXB_0_MSIX_TABLE_LADDR_VECT25 */ "", 65619 /* PAXB_0_MSIX_TABLE_LADDR_VECT26 */ "", 65620 /* PAXB_0_MSIX_TABLE_LADDR_VECT27 */ "", 65621 /* PAXB_0_MSIX_TABLE_LADDR_VECT28 */ "", 65622 /* PAXB_0_MSIX_TABLE_LADDR_VECT29 */ "", 65623 /* PAXB_0_MSIX_TABLE_LADDR_VECT30 */ "", 65624 /* PAXB_0_MSIX_TABLE_LADDR_VECT31 */ "", 65625 /* PAXB_0_MSIX_TABLE_LADDR_VECT32 */ "", 65626 /* PAXB_0_MSIX_TABLE_LADDR_VECT33 */ "", 65627 /* PAXB_0_MSIX_TABLE_LADDR_VECT34 */ "", 65628 /* PAXB_0_MSIX_TABLE_LADDR_VECT35 */ "", 65629 /* PAXB_0_MSIX_TABLE_LADDR_VECT36 */ "", 65630 /* PAXB_0_MSIX_TABLE_LADDR_VECT37 */ "", 65631 /* PAXB_0_MSIX_TABLE_LADDR_VECT38 */ "", 65632 /* PAXB_0_MSIX_TABLE_LADDR_VECT39 */ "", 65633 /* PAXB_0_MSIX_TABLE_LADDR_VECT40 */ "", 65634 /* PAXB_0_MSIX_TABLE_LADDR_VECT41 */ "", 65635 /* PAXB_0_MSIX_TABLE_LADDR_VECT42 */ "", 65636 /* PAXB_0_MSIX_TABLE_LADDR_VECT43 */ "", 65637 /* PAXB_0_MSIX_TABLE_LADDR_VECT44 */ "", 65638 /* PAXB_0_MSIX_TABLE_LADDR_VECT45 */ "", 65639 /* PAXB_0_MSIX_TABLE_LADDR_VECT46 */ "", 65640 /* PAXB_0_MSIX_TABLE_LADDR_VECT47 */ "", 65641 /* PAXB_0_MSIX_TABLE_LADDR_VECT48 */ "", 65642 /* PAXB_0_MSIX_TABLE_LADDR_VECT49 */ "", 65643 /* PAXB_0_MSIX_TABLE_LADDR_VECT50 */ "", 65644 /* PAXB_0_MSIX_TABLE_LADDR_VECT51 */ "", 65645 /* PAXB_0_MSIX_TABLE_LADDR_VECT52 */ "", 65646 /* PAXB_0_MSIX_TABLE_LADDR_VECT53 */ "", 65647 /* PAXB_0_MSIX_TABLE_LADDR_VECT54 */ "", 65648 /* PAXB_0_MSIX_TABLE_LADDR_VECT55 */ "", 65649 /* PAXB_0_MSIX_TABLE_LADDR_VECT56 */ "", 65650 /* PAXB_0_MSIX_TABLE_LADDR_VECT57 */ "", 65651 /* PAXB_0_MSIX_TABLE_LADDR_VECT58 */ "", 65652 /* PAXB_0_MSIX_TABLE_LADDR_VECT59 */ "", 65653 /* PAXB_0_MSIX_TABLE_LADDR_VECT60 */ "", 65654 /* PAXB_0_MSIX_TABLE_LADDR_VECT61 */ "", 65655 /* PAXB_0_MSIX_TABLE_LADDR_VECT62 */ "", 65656 /* PAXB_0_MSIX_TABLE_LADDR_VECT63 */ "", 65657 /* PAXB_0_MSIX_TABLE_UADDR_VECT0 */ "", 65658 /* PAXB_0_MSIX_TABLE_UADDR_VECT1 */ "", 65659 /* PAXB_0_MSIX_TABLE_UADDR_VECT2 */ "", 65660 /* PAXB_0_MSIX_TABLE_UADDR_VECT3 */ "", 65661 /* PAXB_0_MSIX_TABLE_UADDR_VECT4 */ "", 65662 /* PAXB_0_MSIX_TABLE_UADDR_VECT5 */ "", 65663 /* PAXB_0_MSIX_TABLE_UADDR_VECT6 */ "", 65664 /* PAXB_0_MSIX_TABLE_UADDR_VECT7 */ "", 65665 /* PAXB_0_MSIX_TABLE_UADDR_VECT8 */ "", 65666 /* PAXB_0_MSIX_TABLE_UADDR_VECT9 */ "", 65667 /* PAXB_0_MSIX_TABLE_UADDR_VECT10 */ "", 65668 /* PAXB_0_MSIX_TABLE_UADDR_VECT11 */ "", 65669 /* PAXB_0_MSIX_TABLE_UADDR_VECT12 */ "", 65670 /* PAXB_0_MSIX_TABLE_UADDR_VECT13 */ "", 65671 /* PAXB_0_MSIX_TABLE_UADDR_VECT14 */ "", 65672 /* PAXB_0_MSIX_TABLE_UADDR_VECT15 */ "", 65673 /* PAXB_0_MSIX_TABLE_UADDR_VECT16 */ "", 65674 /* PAXB_0_MSIX_TABLE_UADDR_VECT17 */ "", 65675 /* PAXB_0_MSIX_TABLE_UADDR_VECT18 */ "", 65676 /* PAXB_0_MSIX_TABLE_UADDR_VECT19 */ "", 65677 /* PAXB_0_MSIX_TABLE_UADDR_VECT20 */ "", 65678 /* PAXB_0_MSIX_TABLE_UADDR_VECT21 */ "", 65679 /* PAXB_0_MSIX_TABLE_UADDR_VECT22 */ "", 65680 /* PAXB_0_MSIX_TABLE_UADDR_VECT23 */ "", 65681 /* PAXB_0_MSIX_TABLE_UADDR_VECT24 */ "", 65682 /* PAXB_0_MSIX_TABLE_UADDR_VECT25 */ "", 65683 /* PAXB_0_MSIX_TABLE_UADDR_VECT26 */ "", 65684 /* PAXB_0_MSIX_TABLE_UADDR_VECT27 */ "", 65685 /* PAXB_0_MSIX_TABLE_UADDR_VECT28 */ "", 65686 /* PAXB_0_MSIX_TABLE_UADDR_VECT29 */ "", 65687 /* PAXB_0_MSIX_TABLE_UADDR_VECT30 */ "", 65688 /* PAXB_0_MSIX_TABLE_UADDR_VECT31 */ "", 65689 /* PAXB_0_MSIX_TABLE_UADDR_VECT32 */ "", 65690 /* PAXB_0_MSIX_TABLE_UADDR_VECT33 */ "", 65691 /* PAXB_0_MSIX_TABLE_UADDR_VECT34 */ "", 65692 /* PAXB_0_MSIX_TABLE_UADDR_VECT35 */ "", 65693 /* PAXB_0_MSIX_TABLE_UADDR_VECT36 */ "", 65694 /* PAXB_0_MSIX_TABLE_UADDR_VECT37 */ "", 65695 /* PAXB_0_MSIX_TABLE_UADDR_VECT38 */ "", 65696 /* PAXB_0_MSIX_TABLE_UADDR_VECT39 */ "", 65697 /* PAXB_0_MSIX_TABLE_UADDR_VECT40 */ "", 65698 /* PAXB_0_MSIX_TABLE_UADDR_VECT41 */ "", 65699 /* PAXB_0_MSIX_TABLE_UADDR_VECT42 */ "", 65700 /* PAXB_0_MSIX_TABLE_UADDR_VECT43 */ "", 65701 /* PAXB_0_MSIX_TABLE_UADDR_VECT44 */ "", 65702 /* PAXB_0_MSIX_TABLE_UADDR_VECT45 */ "", 65703 /* PAXB_0_MSIX_TABLE_UADDR_VECT46 */ "", 65704 /* PAXB_0_MSIX_TABLE_UADDR_VECT47 */ "", 65705 /* PAXB_0_MSIX_TABLE_UADDR_VECT48 */ "", 65706 /* PAXB_0_MSIX_TABLE_UADDR_VECT49 */ "", 65707 /* PAXB_0_MSIX_TABLE_UADDR_VECT50 */ "", 65708 /* PAXB_0_MSIX_TABLE_UADDR_VECT51 */ "", 65709 /* PAXB_0_MSIX_TABLE_UADDR_VECT52 */ "", 65710 /* PAXB_0_MSIX_TABLE_UADDR_VECT53 */ "", 65711 /* PAXB_0_MSIX_TABLE_UADDR_VECT54 */ "", 65712 /* PAXB_0_MSIX_TABLE_UADDR_VECT55 */ "", 65713 /* PAXB_0_MSIX_TABLE_UADDR_VECT56 */ "", 65714 /* PAXB_0_MSIX_TABLE_UADDR_VECT57 */ "", 65715 /* PAXB_0_MSIX_TABLE_UADDR_VECT58 */ "", 65716 /* PAXB_0_MSIX_TABLE_UADDR_VECT59 */ "", 65717 /* PAXB_0_MSIX_TABLE_UADDR_VECT60 */ "", 65718 /* PAXB_0_MSIX_TABLE_UADDR_VECT61 */ "", 65719 /* PAXB_0_MSIX_TABLE_UADDR_VECT62 */ "", 65720 /* PAXB_0_MSIX_TABLE_UADDR_VECT63 */ "", 65721 /* PAXB_0_MSIX_TABLE_VC_VECT0 */ "", 65722 /* PAXB_0_MSIX_TABLE_VC_VECT1 */ "", 65723 /* PAXB_0_MSIX_TABLE_VC_VECT2 */ "", 65724 /* PAXB_0_MSIX_TABLE_VC_VECT3 */ "", 65725 /* PAXB_0_MSIX_TABLE_VC_VECT4 */ "", 65726 /* PAXB_0_MSIX_TABLE_VC_VECT5 */ "", 65727 /* PAXB_0_MSIX_TABLE_VC_VECT6 */ "", 65728 /* PAXB_0_MSIX_TABLE_VC_VECT7 */ "", 65729 /* PAXB_0_MSIX_TABLE_VC_VECT8 */ "", 65730 /* PAXB_0_MSIX_TABLE_VC_VECT9 */ "", 65731 /* PAXB_0_MSIX_TABLE_VC_VECT10 */ "", 65732 /* PAXB_0_MSIX_TABLE_VC_VECT11 */ "", 65733 /* PAXB_0_MSIX_TABLE_VC_VECT12 */ "", 65734 /* PAXB_0_MSIX_TABLE_VC_VECT13 */ "", 65735 /* PAXB_0_MSIX_TABLE_VC_VECT14 */ "", 65736 /* PAXB_0_MSIX_TABLE_VC_VECT15 */ "", 65737 /* PAXB_0_MSIX_TABLE_VC_VECT16 */ "", 65738 /* PAXB_0_MSIX_TABLE_VC_VECT17 */ "", 65739 /* PAXB_0_MSIX_TABLE_VC_VECT18 */ "", 65740 /* PAXB_0_MSIX_TABLE_VC_VECT19 */ "", 65741 /* PAXB_0_MSIX_TABLE_VC_VECT20 */ "", 65742 /* PAXB_0_MSIX_TABLE_VC_VECT21 */ "", 65743 /* PAXB_0_MSIX_TABLE_VC_VECT22 */ "", 65744 /* PAXB_0_MSIX_TABLE_VC_VECT23 */ "", 65745 /* PAXB_0_MSIX_TABLE_VC_VECT24 */ "", 65746 /* PAXB_0_MSIX_TABLE_VC_VECT25 */ "", 65747 /* PAXB_0_MSIX_TABLE_VC_VECT26 */ "", 65748 /* PAXB_0_MSIX_TABLE_VC_VECT27 */ "", 65749 /* PAXB_0_MSIX_TABLE_VC_VECT28 */ "", 65750 /* PAXB_0_MSIX_TABLE_VC_VECT29 */ "", 65751 /* PAXB_0_MSIX_TABLE_VC_VECT30 */ "", 65752 /* PAXB_0_MSIX_TABLE_VC_VECT31 */ "", 65753 /* PAXB_0_MSIX_TABLE_VC_VECT32 */ "", 65754 /* PAXB_0_MSIX_TABLE_VC_VECT33 */ "", 65755 /* PAXB_0_MSIX_TABLE_VC_VECT34 */ "", 65756 /* PAXB_0_MSIX_TABLE_VC_VECT35 */ "", 65757 /* PAXB_0_MSIX_TABLE_VC_VECT36 */ "", 65758 /* PAXB_0_MSIX_TABLE_VC_VECT37 */ "", 65759 /* PAXB_0_MSIX_TABLE_VC_VECT38 */ "", 65760 /* PAXB_0_MSIX_TABLE_VC_VECT39 */ "", 65761 /* PAXB_0_MSIX_TABLE_VC_VECT40 */ "", 65762 /* PAXB_0_MSIX_TABLE_VC_VECT41 */ "", 65763 /* PAXB_0_MSIX_TABLE_VC_VECT42 */ "", 65764 /* PAXB_0_MSIX_TABLE_VC_VECT43 */ "", 65765 /* PAXB_0_MSIX_TABLE_VC_VECT44 */ "", 65766 /* PAXB_0_MSIX_TABLE_VC_VECT45 */ "", 65767 /* PAXB_0_MSIX_TABLE_VC_VECT46 */ "", 65768 /* PAXB_0_MSIX_TABLE_VC_VECT47 */ "", 65769 /* PAXB_0_MSIX_TABLE_VC_VECT48 */ "", 65770 /* PAXB_0_MSIX_TABLE_VC_VECT49 */ "", 65771 /* PAXB_0_MSIX_TABLE_VC_VECT50 */ "", 65772 /* PAXB_0_MSIX_TABLE_VC_VECT51 */ "", 65773 /* PAXB_0_MSIX_TABLE_VC_VECT52 */ "", 65774 /* PAXB_0_MSIX_TABLE_VC_VECT53 */ "", 65775 /* PAXB_0_MSIX_TABLE_VC_VECT54 */ "", 65776 /* PAXB_0_MSIX_TABLE_VC_VECT55 */ "", 65777 /* PAXB_0_MSIX_TABLE_VC_VECT56 */ "", 65778 /* PAXB_0_MSIX_TABLE_VC_VECT57 */ "", 65779 /* PAXB_0_MSIX_TABLE_VC_VECT58 */ "", 65780 /* PAXB_0_MSIX_TABLE_VC_VECT59 */ "", 65781 /* PAXB_0_MSIX_TABLE_VC_VECT60 */ "", 65782 /* PAXB_0_MSIX_TABLE_VC_VECT61 */ "", 65783 /* PAXB_0_MSIX_TABLE_VC_VECT62 */ "", 65784 /* PAXB_0_MSIX_TABLE_VC_VECT63 */ "", 65785 /* PAXB_0_OARR_0 */ "", 65786 /* PAXB_0_OARR_1 */ "", 65787 /* PAXB_0_OARR_2 */ "", 65788 /* PAXB_0_OARR_0_UPPER */ "", 65789 /* PAXB_0_OARR_1_UPPER */ "", 65790 /* PAXB_0_OARR_2_UPPER */ "", 65791 /* PAXB_0_OARR_FUNC0_MSI_PAGE */ "", 65792 /* PAXB_0_OARR_FUNC0_MSI_PAGE_UPPER */ "", 65793 /* PAXB_0_OARR_FUNC1_MSI_PAGE */ "", 65794 /* PAXB_0_OARR_FUNC1_MSI_PAGE_UPPER */ "", 65795 /* PAXB_0_OMAP_0_LOWER */ "", 65796 /* PAXB_0_OMAP_0_UPPER */ "", 65797 /* PAXB_0_OMAP_1_LOWER */ "", 65798 /* PAXB_0_OMAP_1_UPPER */ "", 65799 /* PAXB_0_OMAP_2_LOWER */ "", 65800 /* PAXB_0_OMAP_2_UPPER */ "", 65801 /* PAXB_0_OMAP_SINGULAR */ "", 65802 /* PAXB_0_PAXB_DUMMYSLAVE_DEBUG_CTRL */ "", 65803 /* PAXB_0_PAXB_ECC_ERR_INTR_EN */ "", 65804 /* PAXB_0_PAXB_ECC_ERR_INTR_STATUS */ "", 65805 /* PAXB_0_PAXB_ENDIANNESS */ "", 65806 /* PAXB_0_PAXB_HOTSWAP_CTRL */ "", 65807 /* PAXB_0_PAXB_HOTSWAP_DEBUG_CTRL */ "", 65808 /* PAXB_0_PAXB_HOTSWAP_DEBUG_STAT */ "", 65809 /* PAXB_0_PAXB_HOTSWAP_STAT */ "", 65810 /* PAXB_0_PAXB_IC_INTRCLR_0 */ "", 65811 /* PAXB_0_PAXB_IC_INTRCLR_1 */ "", 65812 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_0 */ "", 65813 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_1 */ "", 65814 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_2 */ "", 65815 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_3 */ "", 65816 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_4 */ "", 65817 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_5 */ "", 65818 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_6 */ "", 65819 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_7 */ "", 65820 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_8 */ "", 65821 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_9 */ "", 65822 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_10 */ "", 65823 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_11 */ "", 65824 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_12 */ "", 65825 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_13 */ "", 65826 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_14 */ "", 65827 /* PAXB_0_PAXB_IC_INTRCLR_DELAY_15 */ "", 65828 /* PAXB_0_PAXB_IC_INTRCLR_MODE_0 */ "", 65829 /* PAXB_0_PAXB_IC_INTRCLR_MODE_1 */ "", 65830 /* PAXB_0_PAXB_IC_INTR_PACING_CTRL */ "", 65831 /* PAXB_0_PAXB_INTRCLR_DELAY_UNIT */ "", 65832 /* PAXB_0_PAXB_INTR_CLEAR */ "", 65833 /* PAXB_0_PAXB_INTR_EN */ "", 65834 /* PAXB_0_PAXB_INTR_STATUS */ "", 65835 /* PAXB_0_PAXB_MISC_CONFIG */ "", 65836 /* PAXB_0_PAXB_MISC_STATUS */ "", 65837 /* PAXB_0_PAXB_RD_CMPL_BUF_INIT_DONE */ "", 65838 /* PAXB_0_PAXB_RD_CMPL_BUF_INIT_START */ "", 65839 /* PAXB_0_PAXB_TX_ARBITER_PRIORITY */ "", 65840 /* PAXB_0_PAXB_TX_DEBUG_CFG */ "", 65841 /* PAXB_0_PCIE_DEBUG_BUF0_1_ECC_LOG */ "", 65842 /* PAXB_0_PCIE_DEBUG_BUF2_3_ECC_LOG */ "", 65843 /* PAXB_0_PCIE_DEBUG_BUF4_ECC_LOG */ "", 65844 /* PAXB_0_PCIE_DL_TO_TL_BUF_ECC_LOG */ "", 65845 /* PAXB_0_PCIE_EP_AXI_CONFIG */ "", 65846 /* PAXB_0_PCIE_ERROR_STATUS */ "", 65847 /* PAXB_0_PCIE_LINK_STATUS */ "", 65848 /* PAXB_0_PCIE_ORDERING_RULES_ENABLE */ "", 65849 /* PAXB_0_PCIE_PAXB_RX_DEBUG_CONTROL_0 */ "", 65850 /* PAXB_0_PCIE_PAXB_RX_DEBUG_STATUS_0 */ "", 65851 /* PAXB_0_PCIE_RC_AXI_CONFIG */ "", 65852 /* PAXB_0_PCIE_REPLAY_ADDR_BUF_ECC_LOG */ "", 65853 /* PAXB_0_PCIE_REPLAY_DATA_BUF_ECC_LOG */ "", 65854 /* PAXB_0_PCIE_SYS_EP_INT_CSR0 */ "", 65855 /* PAXB_0_PCIE_SYS_EP_INT_CSR1 */ "", 65856 /* PAXB_0_PCIE_SYS_EP_INT_EN0 */ "", 65857 /* PAXB_0_PCIE_SYS_EP_INT_EN1 */ "", 65858 /* PAXB_0_PCIE_SYS_EQ_0_OVERWRITTEN */ "", 65859 /* PAXB_0_PCIE_SYS_EQ_1_OVERWRITTEN */ "", 65860 /* PAXB_0_PCIE_SYS_EQ_2_OVERWRITTEN */ "", 65861 /* PAXB_0_PCIE_SYS_EQ_3_OVERWRITTEN */ "", 65862 /* PAXB_0_PCIE_SYS_EQ_4_OVERWRITTEN */ "", 65863 /* PAXB_0_PCIE_SYS_EQ_5_OVERWRITTEN */ "", 65864 /* PAXB_0_PCIE_SYS_EQ_HEAD_0 */ "", 65865 /* PAXB_0_PCIE_SYS_EQ_HEAD_1 */ "", 65866 /* PAXB_0_PCIE_SYS_EQ_HEAD_2 */ "", 65867 /* PAXB_0_PCIE_SYS_EQ_HEAD_3 */ "", 65868 /* PAXB_0_PCIE_SYS_EQ_HEAD_4 */ "", 65869 /* PAXB_0_PCIE_SYS_EQ_HEAD_5 */ "", 65870 /* PAXB_0_PCIE_SYS_EQ_PAGE */ "", 65871 /* PAXB_0_PCIE_SYS_EQ_PAGE_UPPER */ "", 65872 /* PAXB_0_PCIE_SYS_EQ_TAIL_0 */ "", 65873 /* PAXB_0_PCIE_SYS_EQ_TAIL_1 */ "", 65874 /* PAXB_0_PCIE_SYS_EQ_TAIL_2 */ "", 65875 /* PAXB_0_PCIE_SYS_EQ_TAIL_3 */ "", 65876 /* PAXB_0_PCIE_SYS_EQ_TAIL_4 */ "", 65877 /* PAXB_0_PCIE_SYS_EQ_TAIL_5 */ "", 65878 /* PAXB_0_PCIE_SYS_EQ_TAIL_EARLY_0 */ "", 65879 /* PAXB_0_PCIE_SYS_EQ_TAIL_EARLY_1 */ "", 65880 /* PAXB_0_PCIE_SYS_EQ_TAIL_EARLY_2 */ "", 65881 /* PAXB_0_PCIE_SYS_EQ_TAIL_EARLY_3 */ "", 65882 /* PAXB_0_PCIE_SYS_EQ_TAIL_EARLY_4 */ "", 65883 /* PAXB_0_PCIE_SYS_EQ_TAIL_EARLY_5 */ "", 65884 /* PAXB_0_PCIE_SYS_HOST_INTR_0 */ "", 65885 /* PAXB_0_PCIE_SYS_HOST_INTR_1 */ "", 65886 /* PAXB_0_PCIE_SYS_HOST_INTR_2 */ "", 65887 /* PAXB_0_PCIE_SYS_HOST_INTR_3 */ "", 65888 /* PAXB_0_PCIE_SYS_HOST_INTR_CSR */ "", 65889 /* PAXB_0_PCIE_SYS_HOST_INTR_EN */ "", 65890 /* PAXB_0_PCIE_SYS_MSI_CTRL_0 */ "", 65891 /* PAXB_0_PCIE_SYS_MSI_CTRL_1 */ "", 65892 /* PAXB_0_PCIE_SYS_MSI_CTRL_2 */ "", 65893 /* PAXB_0_PCIE_SYS_MSI_CTRL_3 */ "", 65894 /* PAXB_0_PCIE_SYS_MSI_CTRL_4 */ "", 65895 /* PAXB_0_PCIE_SYS_MSI_CTRL_5 */ "", 65896 /* PAXB_0_PCIE_SYS_MSI_INTR_EN */ "", 65897 /* PAXB_0_PCIE_SYS_MSI_PAGE */ "", 65898 /* PAXB_0_PCIE_SYS_MSI_PAGE_UPPER */ "", 65899 /* PAXB_0_PCIE_SYS_MSI_REQ */ "", 65900 /* PAXB_0_PCIE_SYS_RC_INTX_CSR */ "", 65901 /* PAXB_0_PCIE_SYS_RC_INTX_EN */ "", 65902 /* PAXB_0_PCIE_TL_TO_DL_BUF_ECC_LOG */ "", 65903 /* PAXB_0_RC_PM_CONTROL */ "", 65904 /* PAXB_0_RC_PM_STATUS */ "", 65905 /* PAXB_0_RESET_ENABLE_IN_PCIE_LINK_DOWN */ "", 65906 /* PAXB_0_RESET_STATUS */ "", 65907 /* PAXB_0_RX_RD_CPL_BUF_ECC_LOG */ "", 65908 /* PAXB_0_RX_WR_DATA_BUF_ECC_LOG */ "", 65909 /* PAXB_0_STRAP_STATUS */ "", 65910 /* PAXB_0_SW_PROG_INTR_CLR */ "", 65911 /* PAXB_0_SW_PROG_INTR_ENABLE */ "", 65912 /* PAXB_0_SW_PROG_INTR_SET */ "", 65913 /* PAXB_0_SW_PROG_INTR_STATUS */ "", 65914 /* PAXB_1_APB_ERR_EN_FOR_CFG_RD_CMPL */ "", 65915 /* PAXB_1_APB_TIMEOUT_COUNT */ "", 65916 /* PAXB_1_AXI_SLVERR_EN_FOR_MEM_RD_CMPL */ "", 65917 /* PAXB_1_CFG_ADDR */ "", 65918 /* PAXB_1_CFG_DATA */ "", 65919 /* PAXB_1_CLK_CONTROL */ "", 65920 /* PAXB_1_CMICD_TO_PCIE_INTR_EN */ "", 65921 /* PAXB_1_CONFIG_IND_ADDR */ "", 65922 /* PAXB_1_CONFIG_IND_DATA */ "", 65923 /* PAXB_1_EP_LTR_CONTROL */ "", 65924 /* PAXB_1_EP_LTR_STATUS */ "", 65925 /* PAXB_1_EP_OBFF_STATUS */ "", 65926 /* PAXB_1_EP_PM_CONTROL */ "", 65927 /* PAXB_1_EP_PM_STATUS */ "", 65928 /* PAXB_1_FUNC0_IMAP1 */ "", 65929 /* PAXB_1_FUNC0_IMAP2 */ "", 65930 /* PAXB_1_FUNC0_IMAP0_0 */ "", 65931 /* PAXB_1_FUNC0_IMAP0_1 */ "", 65932 /* PAXB_1_FUNC0_IMAP0_2 */ "", 65933 /* PAXB_1_FUNC0_IMAP0_3 */ "", 65934 /* PAXB_1_FUNC0_IMAP0_4 */ "", 65935 /* PAXB_1_FUNC0_IMAP0_5 */ "", 65936 /* PAXB_1_FUNC0_IMAP0_6 */ "", 65937 /* PAXB_1_FUNC0_IMAP0_7 */ "", 65938 /* PAXB_1_FUNC0_IMAP0_0123_REGS_TYPE */ "", 65939 /* PAXB_1_FUNC0_IMAP0_0_UPPER */ "", 65940 /* PAXB_1_FUNC0_IMAP0_1_UPPER */ "", 65941 /* PAXB_1_FUNC0_IMAP0_2_UPPER */ "", 65942 /* PAXB_1_FUNC0_IMAP0_3_UPPER */ "", 65943 /* PAXB_1_FUNC0_IMAP0_4_UPPER */ "", 65944 /* PAXB_1_FUNC0_IMAP0_5_UPPER */ "", 65945 /* PAXB_1_FUNC0_IMAP0_6_UPPER */ "", 65946 /* PAXB_1_FUNC0_IMAP0_7_UPPER */ "", 65947 /* PAXB_1_FUNC0_IMAP1_0 */ "", 65948 /* PAXB_1_FUNC0_IMAP1_1 */ "", 65949 /* PAXB_1_FUNC0_IMAP1_2 */ "", 65950 /* PAXB_1_FUNC0_IMAP1_3 */ "", 65951 /* PAXB_1_FUNC0_IMAP1_4 */ "", 65952 /* PAXB_1_FUNC0_IMAP1_5 */ "", 65953 /* PAXB_1_FUNC0_IMAP1_6 */ "", 65954 /* PAXB_1_FUNC0_IMAP1_7 */ "", 65955 /* PAXB_1_FUNC0_IMAP1_0_UPPER */ "", 65956 /* PAXB_1_FUNC0_IMAP1_1_UPPER */ "", 65957 /* PAXB_1_FUNC0_IMAP1_2_UPPER */ "", 65958 /* PAXB_1_FUNC0_IMAP1_3_UPPER */ "", 65959 /* PAXB_1_FUNC0_IMAP1_4_UPPER */ "", 65960 /* PAXB_1_FUNC0_IMAP1_5_UPPER */ "", 65961 /* PAXB_1_FUNC0_IMAP1_6_UPPER */ "", 65962 /* PAXB_1_FUNC0_IMAP1_7_UPPER */ "", 65963 /* PAXB_1_FUNC0_IMAP1_UPPER */ "", 65964 /* PAXB_1_FUNC0_IMAP2_UPPER */ "", 65965 /* PAXB_1_FUNC1_IARR_1_SIZE */ "", 65966 /* PAXB_1_FUNC1_IARR_2_SIZE */ "", 65967 /* PAXB_1_FUNC1_IMAP1 */ "", 65968 /* PAXB_1_FUNC1_IMAP2 */ "", 65969 /* PAXB_1_FUNC1_IMAP0_0 */ "", 65970 /* PAXB_1_FUNC1_IMAP0_1 */ "", 65971 /* PAXB_1_FUNC1_IMAP0_2 */ "", 65972 /* PAXB_1_FUNC1_IMAP0_3 */ "", 65973 /* PAXB_1_FUNC1_IMAP0_4 */ "", 65974 /* PAXB_1_FUNC1_IMAP0_5 */ "", 65975 /* PAXB_1_FUNC1_IMAP0_6 */ "", 65976 /* PAXB_1_FUNC1_IMAP0_7 */ "", 65977 /* PAXB_1_FUNC1_IMAP0_0_UPPER */ "", 65978 /* PAXB_1_FUNC1_IMAP0_1_UPPER */ "", 65979 /* PAXB_1_FUNC1_IMAP0_2_UPPER */ "", 65980 /* PAXB_1_FUNC1_IMAP0_3_UPPER */ "", 65981 /* PAXB_1_FUNC1_IMAP0_4_UPPER */ "", 65982 /* PAXB_1_FUNC1_IMAP0_5_UPPER */ "", 65983 /* PAXB_1_FUNC1_IMAP0_6_UPPER */ "", 65984 /* PAXB_1_FUNC1_IMAP0_7_UPPER */ "", 65985 /* PAXB_1_FUNC1_IMAP1_0 */ "", 65986 /* PAXB_1_FUNC1_IMAP1_1 */ "", 65987 /* PAXB_1_FUNC1_IMAP1_2 */ "", 65988 /* PAXB_1_FUNC1_IMAP1_3 */ "", 65989 /* PAXB_1_FUNC1_IMAP1_4 */ "", 65990 /* PAXB_1_FUNC1_IMAP1_5 */ "", 65991 /* PAXB_1_FUNC1_IMAP1_6 */ "", 65992 /* PAXB_1_FUNC1_IMAP1_7 */ "", 65993 /* PAXB_1_FUNC1_IMAP1_0_UPPER */ "", 65994 /* PAXB_1_FUNC1_IMAP1_1_UPPER */ "", 65995 /* PAXB_1_FUNC1_IMAP1_2_UPPER */ "", 65996 /* PAXB_1_FUNC1_IMAP1_3_UPPER */ "", 65997 /* PAXB_1_FUNC1_IMAP1_4_UPPER */ "", 65998 /* PAXB_1_FUNC1_IMAP1_5_UPPER */ "", 65999 /* PAXB_1_FUNC1_IMAP1_6_UPPER */ "", 66000 /* PAXB_1_FUNC1_IMAP1_7_UPPER */ "", 66001 /* PAXB_1_FUNC1_IMAP1_UPPER */ "", 66002 /* PAXB_1_FUNC1_IMAP2_UPPER */ "", 66003 /* PAXB_1_IARR_0_LOWER */ "", 66004 /* PAXB_1_IARR_0_UPPER */ "", 66005 /* PAXB_1_IARR_1_LOWER */ "", 66006 /* PAXB_1_IARR_1_UPPER */ "", 66007 /* PAXB_1_IARR_2_LOWER */ "", 66008 /* PAXB_1_IARR_2_UPPER */ "", 66009 /* PAXB_1_MEM_CONTROL */ "", 66010 /* PAXB_1_MEM_ECC_ERR_LOG_0 */ "", 66011 /* PAXB_1_MEM_ECC_ERR_LOG_1 */ "", 66012 /* PAXB_1_MISC_INTR_EN */ "", 66013 /* PAXB_1_OARR_0 */ "", 66014 /* PAXB_1_OARR_1 */ "", 66015 /* PAXB_1_OARR_2 */ "", 66016 /* PAXB_1_OARR_0_UPPER */ "", 66017 /* PAXB_1_OARR_1_UPPER */ "", 66018 /* PAXB_1_OARR_2_UPPER */ "", 66019 /* PAXB_1_OARR_FUNC0_MSI_PAGE */ "", 66020 /* PAXB_1_OARR_FUNC0_MSI_PAGE_UPPER */ "", 66021 /* PAXB_1_OARR_FUNC1_MSI_PAGE */ "", 66022 /* PAXB_1_OARR_FUNC1_MSI_PAGE_UPPER */ "", 66023 /* PAXB_1_OMAP_0_LOWER */ "", 66024 /* PAXB_1_OMAP_0_UPPER */ "", 66025 /* PAXB_1_OMAP_1_LOWER */ "", 66026 /* PAXB_1_OMAP_1_UPPER */ "", 66027 /* PAXB_1_OMAP_2_LOWER */ "", 66028 /* PAXB_1_OMAP_2_UPPER */ "", 66029 /* PAXB_1_PAXB_ENDIANNESS */ "", 66030 /* PAXB_1_PAXB_INTR_CLEAR */ "", 66031 /* PAXB_1_PAXB_INTR_EN */ "", 66032 /* PAXB_1_PAXB_INTR_STATUS */ "", 66033 /* PAXB_1_PAXB_MISC_CONFIG */ "", 66034 /* PAXB_1_PAXB_MISC_STATUS */ "", 66035 /* PAXB_1_PAXB_RD_CMPL_BUF_INIT_DONE */ "", 66036 /* PAXB_1_PAXB_RD_CMPL_BUF_INIT_START */ "", 66037 /* PAXB_1_PAXB_TX_ARBITER_PRIORITY */ "", 66038 /* PAXB_1_PAXB_TX_DEBUG_CFG */ "", 66039 /* PAXB_1_PCIE_DL_TO_TL_BUF_ECC_LOG */ "", 66040 /* PAXB_1_PCIE_EP_AXI_CONFIG */ "", 66041 /* PAXB_1_PCIE_ERROR_STATUS */ "", 66042 /* PAXB_1_PCIE_LINK_STATUS */ "", 66043 /* PAXB_1_PCIE_ORDERING_RULES_ENABLE */ "", 66044 /* PAXB_1_PCIE_PAXB_RX_DEBUG_CONTROL_0 */ "", 66045 /* PAXB_1_PCIE_PAXB_RX_DEBUG_STATUS_0 */ "", 66046 /* PAXB_1_PCIE_RC_AXI_CONFIG */ "", 66047 /* PAXB_1_PCIE_REPLAY_ADDR_BUF_ECC_LOG */ "", 66048 /* PAXB_1_PCIE_REPLAY_DATA_BUF_ECC_LOG */ "", 66049 /* PAXB_1_PCIE_SYS_EP_INT_CSR0 */ "", 66050 /* PAXB_1_PCIE_SYS_EP_INT_CSR1 */ "", 66051 /* PAXB_1_PCIE_SYS_EP_INT_EN0 */ "", 66052 /* PAXB_1_PCIE_SYS_EP_INT_EN1 */ "", 66053 /* PAXB_1_PCIE_SYS_EQ_0_OVERWRITTEN */ "", 66054 /* PAXB_1_PCIE_SYS_EQ_1_OVERWRITTEN */ "", 66055 /* PAXB_1_PCIE_SYS_EQ_2_OVERWRITTEN */ "", 66056 /* PAXB_1_PCIE_SYS_EQ_3_OVERWRITTEN */ "", 66057 /* PAXB_1_PCIE_SYS_EQ_4_OVERWRITTEN */ "", 66058 /* PAXB_1_PCIE_SYS_EQ_5_OVERWRITTEN */ "", 66059 /* PAXB_1_PCIE_SYS_EQ_HEAD_0 */ "", 66060 /* PAXB_1_PCIE_SYS_EQ_HEAD_1 */ "", 66061 /* PAXB_1_PCIE_SYS_EQ_HEAD_2 */ "", 66062 /* PAXB_1_PCIE_SYS_EQ_HEAD_3 */ "", 66063 /* PAXB_1_PCIE_SYS_EQ_HEAD_4 */ "", 66064 /* PAXB_1_PCIE_SYS_EQ_HEAD_5 */ "", 66065 /* PAXB_1_PCIE_SYS_EQ_PAGE */ "", 66066 /* PAXB_1_PCIE_SYS_EQ_PAGE_UPPER */ "", 66067 /* PAXB_1_PCIE_SYS_EQ_TAIL_0 */ "", 66068 /* PAXB_1_PCIE_SYS_EQ_TAIL_1 */ "", 66069 /* PAXB_1_PCIE_SYS_EQ_TAIL_2 */ "", 66070 /* PAXB_1_PCIE_SYS_EQ_TAIL_3 */ "", 66071 /* PAXB_1_PCIE_SYS_EQ_TAIL_4 */ "", 66072 /* PAXB_1_PCIE_SYS_EQ_TAIL_5 */ "", 66073 /* PAXB_1_PCIE_SYS_EQ_TAIL_EARLY_0 */ "", 66074 /* PAXB_1_PCIE_SYS_EQ_TAIL_EARLY_1 */ "", 66075 /* PAXB_1_PCIE_SYS_EQ_TAIL_EARLY_2 */ "", 66076 /* PAXB_1_PCIE_SYS_EQ_TAIL_EARLY_3 */ "", 66077 /* PAXB_1_PCIE_SYS_EQ_TAIL_EARLY_4 */ "", 66078 /* PAXB_1_PCIE_SYS_EQ_TAIL_EARLY_5 */ "", 66079 /* PAXB_1_PCIE_SYS_HOST_INTR_0 */ "", 66080 /* PAXB_1_PCIE_SYS_HOST_INTR_1 */ "", 66081 /* PAXB_1_PCIE_SYS_HOST_INTR_2 */ "", 66082 /* PAXB_1_PCIE_SYS_HOST_INTR_3 */ "", 66083 /* PAXB_1_PCIE_SYS_HOST_INTR_CSR */ "", 66084 /* PAXB_1_PCIE_SYS_HOST_INTR_EN */ "", 66085 /* PAXB_1_PCIE_SYS_MSI_CTRL_0 */ "", 66086 /* PAXB_1_PCIE_SYS_MSI_CTRL_1 */ "", 66087 /* PAXB_1_PCIE_SYS_MSI_CTRL_2 */ "", 66088 /* PAXB_1_PCIE_SYS_MSI_CTRL_3 */ "", 66089 /* PAXB_1_PCIE_SYS_MSI_CTRL_4 */ "", 66090 /* PAXB_1_PCIE_SYS_MSI_CTRL_5 */ "", 66091 /* PAXB_1_PCIE_SYS_MSI_INTR_EN */ "", 66092 /* PAXB_1_PCIE_SYS_MSI_PAGE */ "", 66093 /* PAXB_1_PCIE_SYS_MSI_PAGE_UPPER */ "", 66094 /* PAXB_1_PCIE_SYS_MSI_REQ */ "", 66095 /* PAXB_1_PCIE_SYS_RC_INTX_CSR */ "", 66096 /* PAXB_1_PCIE_SYS_RC_INTX_EN */ "", 66097 /* PAXB_1_PCIE_TL_TO_DL_BUF_ECC_LOG */ "", 66098 /* PAXB_1_RC_PM_CONTROL */ "", 66099 /* PAXB_1_RC_PM_STATUS */ "", 66100 /* PAXB_1_RESET_ENABLE_IN_PCIE_LINK_DOWN */ "", 66101 /* PAXB_1_RESET_STATUS */ "", 66102 /* PAXB_1_STRAP_STATUS */ "", 66103 /* PBCASCFG_CHID_0 */ "", 66104 /* PBCASCFG_CHID_1 */ "", 66105 /* PBCASCFG_CHID_2 */ "", 66106 /* PBCASCFG_CHID_3 */ "", 66107 /* PBCASCFG_CHID_4 */ "", 66108 /* PBCASCFG_CHID_5 */ "", 66109 /* PBCASCFG_CHID_6 */ "", 66110 /* PBCASCFG_CHID_7 */ "", 66111 /* PBCASCFG_CHID_8 */ "", 66112 /* PBCASCFG_CHID_9 */ "", 66113 /* PBCASCFG_CHID_10 */ "", 66114 /* PBCASCFG_CHID_11 */ "", 66115 /* PBCASCFG_CHID_12 */ "", 66116 /* PBCASCFG_CHID_13 */ "", 66117 /* PBCASCFG_CHID_14 */ "", 66118 /* PBCASCFG_CHID_15 */ "", 66119 /* PBCASCFG_CHID_16 */ "", 66120 /* PBCASCFG_CHID_17 */ "", 66121 /* PBCASCFG_CHID_18 */ "", 66122 /* PBCASCFG_CHID_19 */ "", 66123 /* PBCASCFG_CHID_20 */ "", 66124 /* PBCASCFG_CHID_21 */ "", 66125 /* PBCASCFG_CHID_22 */ "", 66126 /* PBCASCFG_CHID_23 */ "", 66127 /* PBCASCFG_CHID_24 */ "", 66128 /* PBCASCFG_CHID_25 */ "", 66129 /* PBCASCFG_CHID_26 */ "", 66130 /* PBCASCFG_CHID_27 */ "", 66131 /* PBCASCFG_CHID_28 */ "", 66132 /* PBCASCFG_CHID_29 */ "", 66133 /* PBCASCFG_CHID_30 */ "", 66134 /* PBCASCFG_CHID_31 */ "", 66135 /* PBCASCFG_CHID_32 */ "", 66136 /* PBCASCFG_CHID_33 */ "", 66137 /* PBCASCFG_CHID_34 */ "", 66138 /* PBCASCFG_CHID_35 */ "", 66139 /* PBCASCFG_CHID_36 */ "", 66140 /* PBCASCFG_CHID_37 */ "", 66141 /* PBCASCFG_CHID_38 */ "", 66142 /* PBCASCFG_CHID_39 */ "", 66143 /* PBCASCFG_CHID_40 */ "", 66144 /* PBCASCFG_CHID_41 */ "", 66145 /* PBCASCFG_CHID_42 */ "", 66146 /* PBCASCFG_CHID_43 */ "", 66147 /* PBCASCFG_CHID_44 */ "", 66148 /* PBCASCFG_CHID_45 */ "", 66149 /* PBCASCFG_CHID_46 */ "", 66150 /* PBCASCFG_CHID_47 */ "", 66151 /* PBCASCFG_CHID_48 */ "", 66152 /* PBCASCFG_CHID_49 */ "", 66153 /* PBCASCFG_CHID_50 */ "", 66154 /* PBCASCFG_CHID_51 */ "", 66155 /* PBCASCFG_CHID_52 */ "", 66156 /* PBCASCFG_CHID_53 */ "", 66157 /* PBCASCFG_CHID_54 */ "", 66158 /* PBCASCFG_CHID_55 */ "", 66159 /* PBCASCFG_CHID_56 */ "", 66160 /* PBCASCFG_CHID_57 */ "", 66161 /* PBCASCFG_CHID_58 */ "", 66162 /* PBCASCFG_CHID_59 */ "", 66163 /* PBCASCFG_CHID_60 */ "", 66164 /* PBCASCFG_CHID_61 */ "", 66165 /* PBCASCFG_CHID_62 */ "", 66166 /* PBCASCFG_CHID_63 */ "", 66167 /* PBCHCFG_CHID_0 */ "", 66168 /* PBCHCFG_CHID_1 */ "", 66169 /* PBCHCFG_CHID_2 */ "", 66170 /* PBCHCFG_CHID_3 */ "", 66171 /* PBCHCFG_CHID_4 */ "", 66172 /* PBCHCFG_CHID_5 */ "", 66173 /* PBCHCFG_CHID_6 */ "", 66174 /* PBCHCFG_CHID_7 */ "", 66175 /* PBCHCFG_CHID_8 */ "", 66176 /* PBCHCFG_CHID_9 */ "", 66177 /* PBCHCFG_CHID_10 */ "", 66178 /* PBCHCFG_CHID_11 */ "", 66179 /* PBCHCFG_CHID_12 */ "", 66180 /* PBCHCFG_CHID_13 */ "", 66181 /* PBCHCFG_CHID_14 */ "", 66182 /* PBCHCFG_CHID_15 */ "", 66183 /* PBCHCFG_CHID_16 */ "", 66184 /* PBCHCFG_CHID_17 */ "", 66185 /* PBCHCFG_CHID_18 */ "", 66186 /* PBCHCFG_CHID_19 */ "", 66187 /* PBCHCFG_CHID_20 */ "", 66188 /* PBCHCFG_CHID_21 */ "", 66189 /* PBCHCFG_CHID_22 */ "", 66190 /* PBCHCFG_CHID_23 */ "", 66191 /* PBCHCFG_CHID_24 */ "", 66192 /* PBCHCFG_CHID_25 */ "", 66193 /* PBCHCFG_CHID_26 */ "", 66194 /* PBCHCFG_CHID_27 */ "", 66195 /* PBCHCFG_CHID_28 */ "", 66196 /* PBCHCFG_CHID_29 */ "", 66197 /* PBCHCFG_CHID_30 */ "", 66198 /* PBCHCFG_CHID_31 */ "", 66199 /* PBCHCFG_CHID_32 */ "", 66200 /* PBCHCFG_CHID_33 */ "", 66201 /* PBCHCFG_CHID_34 */ "", 66202 /* PBCHCFG_CHID_35 */ "", 66203 /* PBCHCFG_CHID_36 */ "", 66204 /* PBCHCFG_CHID_37 */ "", 66205 /* PBCHCFG_CHID_38 */ "", 66206 /* PBCHCFG_CHID_39 */ "", 66207 /* PBCHCFG_CHID_40 */ "", 66208 /* PBCHCFG_CHID_41 */ "", 66209 /* PBCHCFG_CHID_42 */ "", 66210 /* PBCHCFG_CHID_43 */ "", 66211 /* PBCHCFG_CHID_44 */ "", 66212 /* PBCHCFG_CHID_45 */ "", 66213 /* PBCHCFG_CHID_46 */ "", 66214 /* PBCHCFG_CHID_47 */ "", 66215 /* PBCHCFG_CHID_48 */ "", 66216 /* PBCHCFG_CHID_49 */ "", 66217 /* PBCHCFG_CHID_50 */ "", 66218 /* PBCHCFG_CHID_51 */ "", 66219 /* PBCHCFG_CHID_52 */ "", 66220 /* PBCHCFG_CHID_53 */ "", 66221 /* PBCHCFG_CHID_54 */ "", 66222 /* PBCHCFG_CHID_55 */ "", 66223 /* PBCHCFG_CHID_56 */ "", 66224 /* PBCHCFG_CHID_57 */ "", 66225 /* PBCHCFG_CHID_58 */ "", 66226 /* PBCHCFG_CHID_59 */ "", 66227 /* PBCHCFG_CHID_60 */ "", 66228 /* PBCHCFG_CHID_61 */ "", 66229 /* PBCHCFG_CHID_62 */ "", 66230 /* PBCHCFG_CHID_63 */ "", 66231 /* PBI_SRC_INPUT_FC_MAPPING_TABLE_0 */ "", 66232 /* PBI_SRC_INPUT_FC_MAPPING_TABLE_1 */ "", 66233 /* PBI_SRC_INPUT_FC_MAPPING_TABLE_2 */ "", 66234 /* PBI_SRC_INPUT_MAPPING_TABLE_0 */ "", 66235 /* PBI_SRC_INPUT_MAPPING_TABLE_1 */ "", 66236 /* PBI_SRC_INPUT_MAPPING_TABLE_2 */ "", 66237 /* PBLK0_CALENDAR */ "", 66238 /* PBLK1_CALENDAR */ "", 66239 /* PBLK2_CALENDAR */ "", 66240 /* PBLK3_CALENDAR */ "", 66241 /* PBLK4_CALENDAR */ "", 66242 /* PBLK5_CALENDAR */ "", 66243 /* PBLK6_CALENDAR */ "", 66244 /* PBLK7_CALENDAR */ "", 66245 /* PCBRG1_CID_0 */ "", 66246 /* PCBRG1_CID_1 */ "", 66247 /* PCBRG1_CID_2 */ "", 66248 /* PCBRG1_CID_3 */ "", 66249 /* PCBRG1_CID_4 */ "", 66250 /* PCBRG1_CID_5 */ "", 66251 /* PCBRG1_CID_6 */ "", 66252 /* PCBRG1_CID_7 */ "", 66253 /* PCBRG1_CID_8 */ "", 66254 /* PCBRG1_CID_9 */ "", 66255 /* PCBRG1_CID_10 */ "", 66256 /* PCBRG1_CID_11 */ "", 66257 /* PCBRG1_CID_12 */ "", 66258 /* PCBRG1_CID_13 */ "", 66259 /* PCBRG1_CID_14 */ "", 66260 /* PCBRG1_CID_15 */ "", 66261 /* PCBRG2_CID_0 */ "", 66262 /* PCBRG2_CID_1 */ "", 66263 /* PCBRG2_CID_2 */ "", 66264 /* PCBRG2_CID_3 */ "", 66265 /* PCBRG2_CID_4 */ "", 66266 /* PCBRG2_CID_5 */ "", 66267 /* PCBRG2_CID_6 */ "", 66268 /* PCBRG2_CID_7 */ "", 66269 /* PCBRG2_CID_8 */ "", 66270 /* PCBRG2_CID_9 */ "", 66271 /* PCBRG2_CID_10 */ "", 66272 /* PCBRG2_CID_11 */ "", 66273 /* PCBRG2_CID_12 */ "", 66274 /* PCBRG2_CID_13 */ "", 66275 /* PCBRG2_CID_14 */ "", 66276 /* PCBRG2_CID_15 */ "", 66277 /* PCIE0_GEN3PHY_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 66278 /* PCIE0_GEN3PHY_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 66279 /* PCIE0_GEN3PHY_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 66280 /* PCIE0_GEN3PHY_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 66281 /* PCIE0_GEN3PHY_S0_IDM_IDM_ERROR_LOG_ID */ "", 66282 /* PCIE0_GEN3PHY_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 66283 /* PCIE0_GEN3PHY_S0_IDM_IDM_INTERRUPT_STATUS */ "", 66284 /* PCIE0_GEN3PHY_S0_IDM_IDM_IO_CONTROL_DIRECT */ "", 66285 /* PCIE0_GEN3PHY_S0_IDM_IDM_IO_STATUS */ "", 66286 /* PCIE0_GEN3PHY_S0_IDM_IDM_RESET_CONTROL */ "", 66287 /* PCIE0_GEN3PHY_S0_IDM_IDM_RESET_READ_ID */ "", 66288 /* PCIE0_GEN3PHY_S0_IDM_IDM_RESET_STATUS */ "", 66289 /* PCIE0_GEN3PHY_S0_IDM_IDM_RESET_WRITE_ID */ "", 66290 /* PCIE_ADDR_MSB_63_TO_32 */ "", 66291 /* PCIE_RST_CONTROL */ "", 66292 /* PDG_BISR_LOAD_BUSY_STATUS */ "", 66293 /* PDG_BISR_LOAD_BUSY_STATUS_1 */ "", 66294 /* PDG_BISR_LOAD_DONE_STATUS */ "", 66295 /* PDG_BISR_LOAD_DONE_STATUS_1 */ "", 66296 /* PDG_BISR_LOAD_GO_STATUS */ "", 66297 /* PDG_BISR_LOAD_GO_STATUS_1 */ "", 66298 /* PDG_BISR_LOAD_TIMEOUT_STATUS */ "", 66299 /* PDG_BISR_LOAD_TIMEOUT_STATUS_1 */ "", 66300 /* PDM_AUTO_DOC_NAME_0 */ "", 66301 /* PDM_AUTO_DOC_NAME_2 */ "", 66302 /* PDM_ECC_1B_ERR_CNT */ "", 66303 /* PDM_ECC_2B_ERR_CNT */ "", 66304 /* PDM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 66305 /* PDM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 66306 /* PDM_ECC_INTERRUPT_REGISTER */ "", 66307 /* PDM_ECC_INTERRUPT_REGISTER_MASK */ "", 66308 /* PDM_ECC_INTERRUPT_REGISTER_TEST */ "", 66309 /* PDM_ERROR_INITIATION_DATA */ "", 66310 /* PDM_FPC_CONTROL */ "", 66311 /* PDM_FPC_STATUS */ "", 66312 /* PDM_GTIMER_CONFIGURATION */ "", 66313 /* PDM_GTIMER_CYCLE */ "", 66314 /* PDM_INTERRUPT_MASK_REGISTER */ "", 66315 /* PDM_INTERRUPT_REGISTER */ "", 66316 /* PDM_INTERRUPT_REGISTER_TEST */ "", 66317 /* PDM_REG_0102 */ "", 66318 /* PDM_REG_0103 */ "", 66319 /* PDM_REG_00A4 */ "", 66320 /* PDM_REG_00A6 */ "", 66321 /* PDM_REG_00C2 */ "", 66322 /* PDM_RESERVED_MIRROR_ADDR */ "", 66323 /* PDM_RESERVED_MTCD */ "", 66324 /* PDM_RESERVED_MTCP */ "", 66325 /* PDM_RESERVED_SPARE_0 */ "", 66326 /* PDM_RESERVED_SPARE_1 */ "", 66327 /* PDM_RESERVED_SPARE_2 */ "", 66328 /* PDM_RESERVED_SPARE_3 */ "", 66329 /* PDM_SBUS_BROADCAST_ID */ "", 66330 /* PDM_SBUS_LAST_IN_CHAIN */ "", 66331 /* PDM_SPECIAL_CLOCK_CONTROLS */ "", 66332 /* PDTPMC_TCID_0 */ "", 66333 /* PDTPMC_TCID_1 */ "", 66334 /* PDTPMC_TCID_2 */ "", 66335 /* PDTPMC_TCID_3 */ "", 66336 /* PDTPMC_TCID_4 */ "", 66337 /* PDTPMC_TCID_5 */ "", 66338 /* PDTPMC_TCID_6 */ "", 66339 /* PDTPMC_TCID_7 */ "", 66340 /* PDTPMC_TCID_8 */ "", 66341 /* PDTPMC_TCID_9 */ "", 66342 /* PDTPMC_TCID_10 */ "", 66343 /* PDTPMC_TCID_11 */ "", 66344 /* PDTPMC_TCID_12 */ "", 66345 /* PDTPMC_TCID_13 */ "", 66346 /* PDTPMC_TCID_14 */ "", 66347 /* PDTPMC_TCID_15 */ "", 66348 /* PEM_ALU_0_CONFIG */ "", 66349 /* PEM_ALU_1_CONFIG */ "", 66350 /* PEM_ALU_2_CONFIG */ "", 66351 /* PEM_ALU_3_CONFIG */ "", 66352 /* PEM_ALU_4_CONFIG */ "", 66353 /* PEM_ALU_5_CONFIG */ "", 66354 /* PEM_ALU_6_CONFIG */ "", 66355 /* PEM_ALU_7_CONFIG */ "", 66356 /* PEM_ALU_8_CONFIG */ "", 66357 /* PEM_ALU_9_CONFIG */ "", 66358 /* PEM_ALU_CONFIG */ "", 66359 /* PEM_CAM_0_CONFIG */ "", 66360 /* PEM_CAM_1_CONFIG */ "", 66361 /* PEM_CAM_2_CONFIG */ "", 66362 /* PEM_CAM_3_CONFIG */ "", 66363 /* PEM_CAM_4_CONFIG */ "", 66364 /* PEM_CAM_5_CONFIG */ "", 66365 /* PEM_CAM_6_CONFIG */ "", 66366 /* PEM_CAM_7_CONFIG */ "", 66367 /* PEM_CAM_8_CONFIG */ "", 66368 /* PEM_CAM_9_CONFIG */ "", 66369 /* PEM_CAM_CONFIG */ "", 66370 /* PEM_CLOCK_PD_POWER_DOWN */ "", 66371 /* PEM_ECC_1B_ERR_CNT */ "", 66372 /* PEM_ECC_2B_ERR_CNT */ "", 66373 /* PEM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 66374 /* PEM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 66375 /* PEM_ECC_INTERRUPT_REGISTER */ "", 66376 /* PEM_ECC_INTERRUPT_REGISTER_MASK */ "", 66377 /* PEM_ECC_INTERRUPT_REGISTER_TEST */ "", 66378 /* PEM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 66379 /* PEM_ERROR_INITIATION_DATA */ "", 66380 /* PEM_GLOBAL_MEM_OPTIONS */ "", 66381 /* PEM_GTIMER_CONFIGURATION */ "", 66382 /* PEM_GTIMER_CYCLE */ "", 66383 /* PEM_INDIRECT_COMMAND */ "", 66384 /* PEM_INDIRECT_COMMAND_ADDRESS */ "", 66385 /* PEM_INDIRECT_COMMAND_DATA_INCREMENT */ "", 66386 /* PEM_INDIRECT_COMMAND_RD_DATA */ "", 66387 /* PEM_INDIRECT_COMMAND_WIDE_MEM */ "", 66388 /* PEM_INDIRECT_COMMAND_WR_DATA */ "", 66389 /* PEM_INDIRECT_FORCE_BUBBLE */ "", 66390 /* PEM_INTERRUPT_MASK_REGISTER */ "", 66391 /* PEM_INTERRUPT_REGISTER */ "", 66392 /* PEM_INTERRUPT_REGISTER_TEST */ "", 66393 /* PEM_MAP_0_CONFIG */ "", 66394 /* PEM_MAP_1_CONFIG */ "", 66395 /* PEM_MAP_2_CONFIG */ "", 66396 /* PEM_MAP_3_CONFIG */ "", 66397 /* PEM_MAP_4_CONFIG */ "", 66398 /* PEM_MAP_5_CONFIG */ "", 66399 /* PEM_MAP_6_CONFIG */ "", 66400 /* PEM_MAP_7_CONFIG */ "", 66401 /* PEM_MAP_8_CONFIG */ "", 66402 /* PEM_MAP_9_CONFIG */ "", 66403 /* PEM_MAP_CONFIG */ "", 66404 /* PEM_PARITY_ERR_CNT */ "", 66405 /* PEM_PAR_ERR_INITIATE */ "", 66406 /* PEM_PAR_ERR_MEM_MASK */ "", 66407 /* PEM_PCMI_0 */ "", 66408 /* PEM_PCMI_1 */ "", 66409 /* PEM_PCMI_2 */ "", 66410 /* PEM_PCMI_3 */ "", 66411 /* PEM_PCMI_4 */ "", 66412 /* PEM_PCMI_0_S */ "", 66413 /* PEM_PCMI_0_T */ "", 66414 /* PEM_PCMI_1_S */ "", 66415 /* PEM_PCMI_1_T */ "", 66416 /* PEM_PCMI_2_S */ "", 66417 /* PEM_PCMI_2_T */ "", 66418 /* PEM_PCMI_3_S */ "", 66419 /* PEM_PCMI_3_T */ "", 66420 /* PEM_PCMI_4_S */ "", 66421 /* PEM_PCMI_4_T */ "", 66422 /* PEM_PEM_BYPASS */ "", 66423 /* PEM_PRIO_0_CONFIG */ "", 66424 /* PEM_PRIO_1_CONFIG */ "", 66425 /* PEM_PRIO_2_CONFIG */ "", 66426 /* PEM_PRIO_3_CONFIG */ "", 66427 /* PEM_PRIO_4_CONFIG */ "", 66428 /* PEM_PRIO_5_CONFIG */ "", 66429 /* PEM_PRIO_6_CONFIG */ "", 66430 /* PEM_PRIO_7_CONFIG */ "", 66431 /* PEM_PRIO_8_CONFIG */ "", 66432 /* PEM_PRIO_9_CONFIG */ "", 66433 /* PEM_PRIO_CONFIG */ "", 66434 /* PEM_REG_0000 */ "", 66435 /* PEM_REG_0010 */ "", 66436 /* PEM_REG_0018 */ "", 66437 /* PEM_REG_0041 */ "", 66438 /* PEM_REG_0098 */ "", 66439 /* PEM_REG_0100 */ "", 66440 /* PEM_REG_0205 */ "", 66441 /* PEM_REG_0305 */ "", 66442 /* PEM_REG_0405 */ "", 66443 /* PEM_REG_0505 */ "", 66444 /* PEM_REG_00A0 */ "", 66445 /* PEM_REG_00A4 */ "", 66446 /* PEM_REG_00A6 */ "", 66447 /* PEM_REG_00AA */ "", 66448 /* PEM_REG_00C2 */ "", 66449 /* PEM_RESERVED_MIRROR_ADDR */ "", 66450 /* PEM_RESERVED_MTCD */ "", 66451 /* PEM_RESERVED_MTCP */ "", 66452 /* PEM_RESERVED_PCMI_0 */ "", 66453 /* PEM_RESERVED_PCMI_1 */ "", 66454 /* PEM_RESERVED_PCMI_2 */ "", 66455 /* PEM_RESERVED_PCMI_3 */ "", 66456 /* PEM_RESERVED_PCMI_4 */ "", 66457 /* PEM_RESERVED_PCMI_0_S */ "", 66458 /* PEM_RESERVED_PCMI_0_T */ "", 66459 /* PEM_RESERVED_PCMI_1_S */ "", 66460 /* PEM_RESERVED_PCMI_1_T */ "", 66461 /* PEM_RESERVED_PCMI_2_S */ "", 66462 /* PEM_RESERVED_PCMI_2_T */ "", 66463 /* PEM_RESERVED_PCMI_3_S */ "", 66464 /* PEM_RESERVED_PCMI_3_T */ "", 66465 /* PEM_RESERVED_PCMI_4_S */ "", 66466 /* PEM_RESERVED_PCMI_4_T */ "", 66467 /* PEM_RESERVED_SPARE_0 */ "", 66468 /* PEM_RESERVED_SPARE_1 */ "", 66469 /* PEM_RESERVED_SPARE_2 */ "", 66470 /* PEM_RESERVED_SPARE_3 */ "", 66471 /* PEM_ROUTER_INPUT_SELECT */ "", 66472 /* PEM_SBUS_BROADCAST_ID */ "", 66473 /* PEM_SBUS_LAST_IN_CHAIN */ "", 66474 /* PEM_SPECIAL_CLOCK_CONTROLS */ "", 66475 /* PERIPH_NIC_M0_IDM_IDM_INTERRUPT_STATUS */ "", 66476 /* PERIPH_NIC_M0_IDM_IDM_RESET_CONTROL */ "", 66477 /* PERIPH_NIC_M0_IDM_IDM_RESET_STATUS */ "", 66478 /* PERQ_XMT_COUNTER_BASE */ "", 66479 /* PERR_PTR_CTR */ "", 66480 /* PERR_PTR_EXP */ "", 66481 /* PERR_STAT */ "", 66482 /* PER_PORT_AGE_CONTROL */ "", 66483 /* PER_PORT_AGE_CONTROL_64 */ "", 66484 /* PER_PORT_REPL_CONTROL */ "", 66485 /* PE_ETHERTYPE */ "", 66486 /* PE_PARITY_ERRORS */ "", 66487 /* PE_SOP_EOP_ERRORS */ "", 66488 /* PE_UNCORRECTABLE_ECC_ERRORS */ "", 66489 /* PFAPCONFIG */ "", 66490 /* PFAPDEBUGSCR0 */ "", 66491 /* PFAPDEBUGSCR1 */ "", 66492 /* PFAPDEBUGSCR2 */ "", 66493 /* PFAPFULLTHRESHOLD */ "", 66494 /* PFAPMEMDEBUG */ "", 66495 /* PFAPPARITYERRORPTR */ "", 66496 /* PFAPREADPOINTER */ "", 66497 /* PFC_COS0_XOFF_CNT */ "", 66498 /* PFC_COS10_XOFF_CNT */ "", 66499 /* PFC_COS11_XOFF_CNT */ "", 66500 /* PFC_COS12_XOFF_CNT */ "", 66501 /* PFC_COS13_XOFF_CNT */ "", 66502 /* PFC_COS14_XOFF_CNT */ "", 66503 /* PFC_COS15_XOFF_CNT */ "", 66504 /* PFC_COS1_XOFF_CNT */ "", 66505 /* PFC_COS2_XOFF_CNT */ "", 66506 /* PFC_COS3_XOFF_CNT */ "", 66507 /* PFC_COS4_XOFF_CNT */ "", 66508 /* PFC_COS5_XOFF_CNT */ "", 66509 /* PFC_COS6_XOFF_CNT */ "", 66510 /* PFC_COS7_XOFF_CNT */ "", 66511 /* PFC_COS8_XOFF_CNT */ "", 66512 /* PFC_COS9_XOFF_CNT */ "", 66513 /* PFC_XOFF_TIMER */ "", 66514 /* PG0_HDRM_LIMIT_OFFSET */ "", 66515 /* PG1_HDRM_LIMIT_OFFSET */ "", 66516 /* PG2TC */ "", 66517 /* PG2_HDRM_LIMIT_OFFSET */ "", 66518 /* PG3_HDRM_LIMIT_OFFSET */ "", 66519 /* PG4_HDRM_LIMIT_OFFSET */ "", 66520 /* PG4_INTR_ENABLE */ "PORT_GROUP4_INTR_ENABLE", 66521 /* PG4_INTR_STATUS */ "PORT_GROUP4_INTR_STATUS", 66522 /* PG5_HDRM_LIMIT_OFFSET */ "", 66523 /* PG5_INTR_ENABLE */ "PORT_GROUP5_INTR_ENABLE", 66524 /* PG5_INTR_STATUS */ "PORT_GROUP5_INTR_STATUS", 66525 /* PG6_HDRM_LIMIT_OFFSET */ "", 66526 /* PG7_HDRM_LIMIT_OFFSET */ "", 66527 /* PGBKPSTATUS */ "", 66528 /* PGBKPSTATUS_0 */ "", 66529 /* PGBKPSTATUS_1 */ "", 66530 /* PGBKPSTATUS_2 */ "", 66531 /* PGCELLCNT */ "", 66532 /* PGCELLLIMIT */ "", 66533 /* PGDISCARDSETLIMIT */ "", 66534 /* PGDISCSTATUS */ "", 66535 /* PGDISCSTATUS_0 */ "", 66536 /* PGDISCSTATUS_1 */ "", 66537 /* PGDISCSTATUS_2 */ "", 66538 /* PGGBLSTATUS */ "", 66539 /* PGGBLSTATUS_0 */ "", 66540 /* PGGBLSTATUS_1 */ "", 66541 /* PGGBLSTATUS_2 */ "", 66542 /* PGW_BOD_CA0_ECC_STATUS */ "", 66543 /* PGW_BOD_CA1_ECC_STATUS */ "", 66544 /* PGW_BOD_CA2_ECC_STATUS */ "", 66545 /* PGW_BOD_CA3_ECC_STATUS */ "", 66546 /* PGW_BOD_CA4_ECC_STATUS */ "", 66547 /* PGW_BOD_CA5_ECC_STATUS */ "", 66548 /* PGW_BOD_CA6_ECC_STATUS */ "", 66549 /* PGW_BOD_CA7_ECC_STATUS */ "", 66550 /* PGW_BOD_CLP0_ECC_STATUS */ "", 66551 /* PGW_BOD_CLP1_ECC_STATUS */ "", 66552 /* PGW_BOD_ECC_ENABLE */ "", 66553 /* PGW_BOD_OVERFLOW_ERROR */ "", 66554 /* PGW_BOD_STATUS */ "", 66555 /* PGW_BOD_STATUS0 */ "", 66556 /* PGW_BOD_STATUS1 */ "", 66557 /* PGW_BOD_XLP0_ECC_STATUS */ "", 66558 /* PGW_BOD_XLP1_ECC_STATUS */ "", 66559 /* PGW_BOD_XLP2_ECC_STATUS */ "", 66560 /* PGW_BOD_XLP3_ECC_STATUS */ "", 66561 /* PGW_BOD_XLP4_ECC_STATUS */ "", 66562 /* PGW_BOD_XLP5_ECC_STATUS */ "", 66563 /* PGW_BOD_XLP6_ECC_STATUS */ "", 66564 /* PGW_CA_OVERFLOW_STATUS */ "", 66565 /* PGW_CA_OVERFLOW_STATUS_ENABLE */ "", 66566 /* PGW_CA_POWER_DOWN_ENABLE */ "", 66567 /* PGW_CELL_ASM_CA_FIFO_MEMORY0_TM_CONTROL */ "", 66568 /* PGW_CELL_ASM_CA_FIFO_MEMORY1_TM_CONTROL */ "", 66569 /* PGW_CELL_ASM_CLP0_FIFO_0_TM_CONTROL */ "", 66570 /* PGW_CELL_ASM_CLP0_FIFO_1_TM_CONTROL */ "", 66571 /* PGW_CELL_ASM_CLP0_FIFO_2_TM_CONTROL */ "", 66572 /* PGW_CELL_ASM_CLP0_FIFO_3_TM_CONTROL */ "", 66573 /* PGW_CELL_ASM_CLP0_FIFO_4_TM_CONTROL */ "", 66574 /* PGW_CELL_ASM_CLP0_FIFO_5_TM_CONTROL */ "", 66575 /* PGW_CELL_ASM_CLP0_FIFO_6_TM_CONTROL */ "", 66576 /* PGW_CELL_ASM_CLP1_FIFO_0_TM_CONTROL */ "", 66577 /* PGW_CELL_ASM_CLP1_FIFO_1_TM_CONTROL */ "", 66578 /* PGW_CELL_ASM_CLP1_FIFO_2_TM_CONTROL */ "", 66579 /* PGW_CELL_ASM_CLP1_FIFO_3_TM_CONTROL */ "", 66580 /* PGW_CELL_ASM_CLP1_FIFO_4_TM_CONTROL */ "", 66581 /* PGW_CELL_ASM_CLP1_FIFO_5_TM_CONTROL */ "", 66582 /* PGW_CELL_ASM_CLP1_FIFO_6_TM_CONTROL */ "", 66583 /* PGW_CELL_ASM_EMBEDDED_HG_CONTROL0 */ "", 66584 /* PGW_CELL_ASM_EMBEDDED_HG_CONTROL1 */ "", 66585 /* PGW_CELL_ASM_EMBEDDED_HG_ETHERTYPE */ "", 66586 /* PGW_CELL_ASM_XLP0_FIFO_0_TM_CONTROL */ "", 66587 /* PGW_CELL_ASM_XLP0_FIFO_1_TM_CONTROL */ "", 66588 /* PGW_CELL_ASM_XLP0_FIFO_2_TM_CONTROL */ "", 66589 /* PGW_CELL_ASM_XLP0_FIFO_3_TM_CONTROL */ "", 66590 /* PGW_CELL_ASM_XLP0_FIFO_4_TM_CONTROL */ "", 66591 /* PGW_CELL_ASM_XLP0_FIFO_5_TM_CONTROL */ "", 66592 /* PGW_CELL_ASM_XLP0_FIFO_6_TM_CONTROL */ "", 66593 /* PGW_CELL_ASM_XLP0_TM_CONTROL */ "", 66594 /* PGW_CELL_ASM_XLP1_FIFO_0_TM_CONTROL */ "", 66595 /* PGW_CELL_ASM_XLP1_FIFO_1_TM_CONTROL */ "", 66596 /* PGW_CELL_ASM_XLP1_FIFO_2_TM_CONTROL */ "", 66597 /* PGW_CELL_ASM_XLP1_FIFO_3_TM_CONTROL */ "", 66598 /* PGW_CELL_ASM_XLP1_FIFO_4_TM_CONTROL */ "", 66599 /* PGW_CELL_ASM_XLP1_FIFO_5_TM_CONTROL */ "", 66600 /* PGW_CELL_ASM_XLP1_FIFO_6_TM_CONTROL */ "", 66601 /* PGW_CELL_ASM_XLP1_TM_CONTROL */ "", 66602 /* PGW_CELL_ASM_XLP2_FIFO_0_TM_CONTROL */ "", 66603 /* PGW_CELL_ASM_XLP2_FIFO_1_TM_CONTROL */ "", 66604 /* PGW_CELL_ASM_XLP2_FIFO_2_TM_CONTROL */ "", 66605 /* PGW_CELL_ASM_XLP2_FIFO_3_TM_CONTROL */ "", 66606 /* PGW_CELL_ASM_XLP2_FIFO_4_TM_CONTROL */ "", 66607 /* PGW_CELL_ASM_XLP2_FIFO_5_TM_CONTROL */ "", 66608 /* PGW_CELL_ASM_XLP2_FIFO_6_TM_CONTROL */ "", 66609 /* PGW_CELL_ASM_XLP2_TM_CONTROL */ "", 66610 /* PGW_CELL_ASM_XLP3_FIFO_0_TM_CONTROL */ "", 66611 /* PGW_CELL_ASM_XLP3_FIFO_1_TM_CONTROL */ "", 66612 /* PGW_CELL_ASM_XLP3_FIFO_2_TM_CONTROL */ "", 66613 /* PGW_CELL_ASM_XLP3_FIFO_3_TM_CONTROL */ "", 66614 /* PGW_CELL_ASM_XLP3_FIFO_4_TM_CONTROL */ "", 66615 /* PGW_CELL_ASM_XLP3_FIFO_5_TM_CONTROL */ "", 66616 /* PGW_CELL_ASM_XLP3_FIFO_6_TM_CONTROL */ "", 66617 /* PGW_CELL_ASM_XLP3_TM_CONTROL */ "", 66618 /* PGW_CELL_ASM_XLP4_FIFO_0_TM_CONTROL */ "", 66619 /* PGW_CELL_ASM_XLP4_FIFO_1_TM_CONTROL */ "", 66620 /* PGW_CELL_ASM_XLP4_FIFO_2_TM_CONTROL */ "", 66621 /* PGW_CELL_ASM_XLP4_FIFO_3_TM_CONTROL */ "", 66622 /* PGW_CELL_ASM_XLP4_FIFO_4_TM_CONTROL */ "", 66623 /* PGW_CELL_ASM_XLP4_FIFO_5_TM_CONTROL */ "", 66624 /* PGW_CELL_ASM_XLP4_FIFO_6_TM_CONTROL */ "", 66625 /* PGW_CELL_ASM_XLP5_FIFO_0_TM_CONTROL */ "", 66626 /* PGW_CELL_ASM_XLP5_FIFO_1_TM_CONTROL */ "", 66627 /* PGW_CELL_ASM_XLP5_FIFO_2_TM_CONTROL */ "", 66628 /* PGW_CELL_ASM_XLP5_FIFO_3_TM_CONTROL */ "", 66629 /* PGW_CELL_ASM_XLP5_FIFO_4_TM_CONTROL */ "", 66630 /* PGW_CELL_ASM_XLP5_FIFO_5_TM_CONTROL */ "", 66631 /* PGW_CELL_ASM_XLP5_FIFO_6_TM_CONTROL */ "", 66632 /* PGW_CELL_ASM_XLP6_FIFO_0_TM_CONTROL */ "", 66633 /* PGW_CELL_ASM_XLP6_FIFO_1_TM_CONTROL */ "", 66634 /* PGW_CELL_ASM_XLP6_FIFO_2_TM_CONTROL */ "", 66635 /* PGW_CELL_ASM_XLP6_FIFO_3_TM_CONTROL */ "", 66636 /* PGW_CELL_ASM_XLP6_FIFO_4_TM_CONTROL */ "", 66637 /* PGW_CELL_ASM_XLP6_FIFO_5_TM_CONTROL */ "", 66638 /* PGW_CELL_ASM_XLP6_FIFO_6_TM_CONTROL */ "", 66639 /* PGW_CLMAC_TS_ECC_STATUS */ "", 66640 /* PGW_CLMAC_TX_ECC_STATUS */ "", 66641 /* PGW_CLOCK_GATE_DISABLE */ "", 66642 /* PGW_CLP_POWER_DOWN_ENABLE */ "", 66643 /* PGW_CL_CONFIG */ "", 66644 /* PGW_CL_ECC_CONTROL */ "", 66645 /* PGW_CL_INTR_ENABLE */ "", 66646 /* PGW_CL_INTR_STATUS */ "", 66647 /* PGW_CL_LED_CHAIN_CONFIG */ "", 66648 /* PGW_CL_RXFIFO_ECC_DBE_STATUS */ "", 66649 /* PGW_CL_RXFIFO_ECC_SBE_STATUS */ "", 66650 /* PGW_CL_RXFIFO_OVERFLOW_ERROR */ "", 66651 /* PGW_CL_RXFIFO_SOFT_RESET */ "", 66652 /* PGW_CL_SPARE0_REG */ "", 66653 /* PGW_CL_STSFIFO_ECC_DBE_STATUS */ "", 66654 /* PGW_CL_STSFIFO_ECC_SBE_STATUS */ "", 66655 /* PGW_CL_TM0_CONTROL */ "", 66656 /* PGW_CL_TM10_CONTROL */ "", 66657 /* PGW_CL_TM11_CONTROL */ "", 66658 /* PGW_CL_TM1_CONTROL */ "", 66659 /* PGW_CL_TM2_CONTROL */ "", 66660 /* PGW_CL_TM3_CONTROL */ "", 66661 /* PGW_CL_TM4_CONTROL */ "", 66662 /* PGW_CL_TM5_CONTROL */ "", 66663 /* PGW_CL_TM6_CONTROL */ "", 66664 /* PGW_CL_TM7_CONTROL */ "", 66665 /* PGW_CL_TM8_CONTROL */ "", 66666 /* PGW_CL_TM9_CONTROL */ "", 66667 /* PGW_CL_TXFIFO0_ECC_DBE_STATUS */ "", 66668 /* PGW_CL_TXFIFO0_ECC_SBE_STATUS */ "", 66669 /* PGW_CL_TXFIFO1_ECC_DBE_STATUS */ "", 66670 /* PGW_CL_TXFIFO1_ECC_SBE_STATUS */ "", 66671 /* PGW_CL_TXFIFO2_ECC_DBE_STATUS */ "", 66672 /* PGW_CL_TXFIFO2_ECC_SBE_STATUS */ "", 66673 /* PGW_CL_TXFIFO3_ECC_DBE_STATUS */ "", 66674 /* PGW_CL_TXFIFO3_ECC_SBE_STATUS */ "", 66675 /* PGW_CL_TXFIFO_CTRL */ "", 66676 /* PGW_CL_TXFIFO_OVERFLOW */ "", 66677 /* PGW_CNTMAXSIZE */ "", 66678 /* PGW_CPORT_TXFIFO_TM_CONTROL */ "", 66679 /* PGW_CTRL_0 */ "", 66680 /* PGW_ECC_CONTROL */ "", 66681 /* PGW_EEE_COUNTER_MODE */ "", 66682 /* PGW_ETM_MODE */ "", 66683 /* PGW_FORCE_DOUBLE_BIT_ERROR */ "", 66684 /* PGW_FORCE_SINGLE_BIT_ERROR */ "", 66685 /* PGW_GE0_INTR_ENABLE_TS */ "", 66686 /* PGW_GE0_INTR_STATUS_TS */ "", 66687 /* PGW_GE0_MODE_REG */ "", 66688 /* PGW_GE1_INTR_ENABLE_TS */ "", 66689 /* PGW_GE1_INTR_STATUS_TS */ "", 66690 /* PGW_GE1_MODE_REG */ "", 66691 /* PGW_GE8P0_INTR_ENABLE_TS */ "", 66692 /* PGW_GE8P0_INTR_STATUS_TS */ "", 66693 /* PGW_GE8P1_INTR_ENABLE_TS */ "", 66694 /* PGW_GE8P1_INTR_STATUS_TS */ "", 66695 /* PGW_GE8P2_INTR_ENABLE_TS */ "", 66696 /* PGW_GE8P2_INTR_STATUS_TS */ "", 66697 /* PGW_GENERAL_SPARE0 */ "", 66698 /* PGW_GE_BYPASS_LED_CHAIN_CONFIG */ "", 66699 /* PGW_GE_CONFIG */ "", 66700 /* PGW_GE_ECC_CONTROL */ "", 66701 /* PGW_GE_INTR_ENABLE */ "", 66702 /* PGW_GE_INTR_STATUS */ "", 66703 /* PGW_GE_LED_CHAIN_CONFIG */ "", 66704 /* PGW_GE_RXFIFO0_ECC_DBE_STATUS */ "", 66705 /* PGW_GE_RXFIFO0_ECC_SBE_STATUS */ "", 66706 /* PGW_GE_RXFIFO0_OVERFLOW_ERROR */ "", 66707 /* PGW_GE_RXFIFO1_ECC_DBE_STATUS */ "", 66708 /* PGW_GE_RXFIFO1_ECC_SBE_STATUS */ "", 66709 /* PGW_GE_RXFIFO1_OVERFLOW_ERROR */ "", 66710 /* PGW_GE_RXFIFO2_ECC_DBE_STATUS */ "", 66711 /* PGW_GE_RXFIFO2_ECC_SBE_STATUS */ "", 66712 /* PGW_GE_RXFIFO2_OVERFLOW_ERROR */ "", 66713 /* PGW_GE_RXFIFO3_ECC_DBE_STATUS */ "", 66714 /* PGW_GE_RXFIFO3_ECC_SBE_STATUS */ "", 66715 /* PGW_GE_RXFIFO3_OVERFLOW_ERROR */ "", 66716 /* PGW_GE_RXFIFO_SOFT_RESET */ "", 66717 /* PGW_GE_SPARE0_REG */ "", 66718 /* PGW_GE_STSFIFO0_ECC_DBE_STATUS */ "", 66719 /* PGW_GE_STSFIFO0_ECC_SBE_STATUS */ "", 66720 /* PGW_GE_STSFIFO1_ECC_DBE_STATUS */ "", 66721 /* PGW_GE_STSFIFO1_ECC_SBE_STATUS */ "", 66722 /* PGW_GE_STSFIFO2_ECC_DBE_STATUS */ "", 66723 /* PGW_GE_STSFIFO2_ECC_SBE_STATUS */ "", 66724 /* PGW_GE_STSFIFO3_ECC_DBE_STATUS */ "", 66725 /* PGW_GE_STSFIFO3_ECC_SBE_STATUS */ "", 66726 /* PGW_GE_SYNCE_REG */ "", 66727 /* PGW_GE_TM0_CONTROL */ "", 66728 /* PGW_GE_TM10_CONTROL */ "", 66729 /* PGW_GE_TM11_CONTROL */ "", 66730 /* PGW_GE_TM12_CONTROL */ "", 66731 /* PGW_GE_TM13_CONTROL */ "", 66732 /* PGW_GE_TM1_CONTROL */ "", 66733 /* PGW_GE_TM2_CONTROL */ "", 66734 /* PGW_GE_TM3_CONTROL */ "", 66735 /* PGW_GE_TM4_CONTROL */ "", 66736 /* PGW_GE_TM5_CONTROL */ "", 66737 /* PGW_GE_TM6_CONTROL */ "", 66738 /* PGW_GE_TM7_CONTROL */ "", 66739 /* PGW_GE_TM8_CONTROL */ "", 66740 /* PGW_GE_TM9_CONTROL */ "", 66741 /* PGW_GE_TXFIFO0_ECC_DBE_STATUS */ "", 66742 /* PGW_GE_TXFIFO0_ECC_SBE_STATUS */ "", 66743 /* PGW_GE_TXFIFO1_ECC_DBE_STATUS */ "", 66744 /* PGW_GE_TXFIFO1_ECC_SBE_STATUS */ "", 66745 /* PGW_GE_TXFIFO2_ECC_DBE_STATUS */ "", 66746 /* PGW_GE_TXFIFO2_ECC_SBE_STATUS */ "", 66747 /* PGW_GE_TXFIFO3_ECC_DBE_STATUS */ "", 66748 /* PGW_GE_TXFIFO3_ECC_SBE_STATUS */ "", 66749 /* PGW_GE_TXFIFO_OVERFLOW */ "", 66750 /* PGW_GX_BYPASS_LED_CHAIN_CONFIG */ "", 66751 /* PGW_GX_CONFIG */ "", 66752 /* PGW_GX_ECC_CONTROL */ "", 66753 /* PGW_GX_INTR_ENABLE */ "", 66754 /* PGW_GX_INTR_STATUS */ "", 66755 /* PGW_GX_RXFIFO0_ECC_DBE_STATUS */ "", 66756 /* PGW_GX_RXFIFO0_ECC_SBE_STATUS */ "", 66757 /* PGW_GX_RXFIFO0_OVERFLOW_ERROR */ "", 66758 /* PGW_GX_RXFIFO1_ECC_DBE_STATUS */ "", 66759 /* PGW_GX_RXFIFO1_ECC_SBE_STATUS */ "", 66760 /* PGW_GX_RXFIFO1_OVERFLOW_ERROR */ "", 66761 /* PGW_GX_RXFIFO_SOFT_RESET */ "", 66762 /* PGW_GX_SPARE0_REG */ "", 66763 /* PGW_GX_TM0_CONTROL */ "", 66764 /* PGW_GX_TM1_CONTROL */ "", 66765 /* PGW_GX_TM2_CONTROL */ "", 66766 /* PGW_GX_TM3_CONTROL */ "", 66767 /* PGW_GX_TM4_CONTROL */ "", 66768 /* PGW_GX_TM5_CONTROL */ "", 66769 /* PGW_GX_TM6_CONTROL */ "", 66770 /* PGW_GX_TM7_CONTROL */ "", 66771 /* PGW_GX_TM8_CONTROL */ "", 66772 /* PGW_GX_TXFIFO0_ECC_DBE_STATUS */ "", 66773 /* PGW_GX_TXFIFO0_ECC_SBE_STATUS */ "", 66774 /* PGW_GX_TXFIFO1_ECC_DBE_STATUS */ "", 66775 /* PGW_GX_TXFIFO1_ECC_SBE_STATUS */ "", 66776 /* PGW_GX_TXFIFO2_ECC_DBE_STATUS */ "", 66777 /* PGW_GX_TXFIFO2_ECC_SBE_STATUS */ "", 66778 /* PGW_GX_TXFIFO3_ECC_DBE_STATUS */ "", 66779 /* PGW_GX_TXFIFO3_ECC_SBE_STATUS */ "", 66780 /* PGW_GX_TXFIFO_CTRL */ "", 66781 /* PGW_GX_TXFIFO_OVERFLOW */ "", 66782 /* PGW_HSP_CONFIG_0 */ "", 66783 /* PGW_HSP_CONFIG_1 */ "", 66784 /* PGW_HSP_CONFIG_2 */ "", 66785 /* PGW_HSP_CONFIG_3 */ "", 66786 /* PGW_HSP_CONFIG_4 */ "", 66787 /* PGW_HSP_CONFIG_5 */ "", 66788 /* PGW_HSP_CONFIG_6 */ "", 66789 /* PGW_HSP_CONFIG_7 */ "", 66790 /* PGW_HSP_CONFIG_8 */ "", 66791 /* PGW_ING_HW_RESET_CONTROL_2 */ "", 66792 /* PGW_INTR_ENABLE */ "", 66793 /* PGW_INTR_STATUS */ "", 66794 /* PGW_LED_CHAIN_OUT_CONFIG */ "", 66795 /* PGW_LR_TDM2_REG_0 */ "", 66796 /* PGW_LR_TDM2_REG_1 */ "", 66797 /* PGW_LR_TDM2_REG_2 */ "", 66798 /* PGW_LR_TDM2_REG_3 */ "", 66799 /* PGW_LR_TDM2_REG_4 */ "", 66800 /* PGW_LR_TDM2_REG_5 */ "", 66801 /* PGW_LR_TDM2_REG_6 */ "", 66802 /* PGW_LR_TDM2_REG_7 */ "", 66803 /* PGW_LR_TDM2_REG_8 */ "", 66804 /* PGW_LR_TDM2_REG_9 */ "", 66805 /* PGW_LR_TDM2_REG_10 */ "", 66806 /* PGW_LR_TDM2_REG_11 */ "", 66807 /* PGW_LR_TDM2_REG_12 */ "", 66808 /* PGW_LR_TDM2_REG_13 */ "", 66809 /* PGW_LR_TDM2_REG_14 */ "", 66810 /* PGW_LR_TDM2_REG_15 */ "", 66811 /* PGW_LR_TDM2_REG_16 */ "", 66812 /* PGW_LR_TDM2_REG_17 */ "", 66813 /* PGW_LR_TDM2_REG_18 */ "", 66814 /* PGW_LR_TDM2_REG_19 */ "", 66815 /* PGW_LR_TDM2_REG_20 */ "", 66816 /* PGW_LR_TDM2_REG_21 */ "", 66817 /* PGW_LR_TDM2_REG_22 */ "", 66818 /* PGW_LR_TDM2_REG_23 */ "", 66819 /* PGW_LR_TDM2_REG_24 */ "", 66820 /* PGW_LR_TDM2_REG_25 */ "", 66821 /* PGW_LR_TDM2_REG_26 */ "", 66822 /* PGW_LR_TDM2_REG_27 */ "", 66823 /* PGW_LR_TDM2_REG_28 */ "", 66824 /* PGW_LR_TDM2_REG_29 */ "", 66825 /* PGW_LR_TDM2_REG_30 */ "", 66826 /* PGW_LR_TDM2_REG_31 */ "", 66827 /* PGW_LR_TDM2_REG_32 */ "", 66828 /* PGW_LR_TDM2_REG_33 */ "", 66829 /* PGW_LR_TDM2_REG_34 */ "", 66830 /* PGW_LR_TDM2_REG_35 */ "", 66831 /* PGW_LR_TDM2_REG_36 */ "", 66832 /* PGW_LR_TDM2_REG_37 */ "", 66833 /* PGW_LR_TDM2_REG_38 */ "", 66834 /* PGW_LR_TDM2_REG_39 */ "", 66835 /* PGW_LR_TDM_REG_0 */ "", 66836 /* PGW_LR_TDM_REG_1 */ "", 66837 /* PGW_LR_TDM_REG_2 */ "", 66838 /* PGW_LR_TDM_REG_3 */ "", 66839 /* PGW_LR_TDM_REG_4 */ "", 66840 /* PGW_LR_TDM_REG_5 */ "", 66841 /* PGW_LR_TDM_REG_6 */ "", 66842 /* PGW_LR_TDM_REG_7 */ "", 66843 /* PGW_LR_TDM_REG_8 */ "", 66844 /* PGW_LR_TDM_REG_9 */ "", 66845 /* PGW_LR_TDM_REG_10 */ "", 66846 /* PGW_LR_TDM_REG_11 */ "", 66847 /* PGW_LR_TDM_REG_12 */ "", 66848 /* PGW_LR_TDM_REG_13 */ "", 66849 /* PGW_LR_TDM_REG_14 */ "", 66850 /* PGW_LR_TDM_REG_15 */ "", 66851 /* PGW_LR_TDM_REG_16 */ "", 66852 /* PGW_LR_TDM_REG_17 */ "", 66853 /* PGW_LR_TDM_REG_18 */ "", 66854 /* PGW_LR_TDM_REG_19 */ "", 66855 /* PGW_LR_TDM_REG_20 */ "", 66856 /* PGW_LR_TDM_REG_21 */ "", 66857 /* PGW_LR_TDM_REG_22 */ "", 66858 /* PGW_LR_TDM_REG_23 */ "", 66859 /* PGW_LR_TDM_REG_24 */ "", 66860 /* PGW_LR_TDM_REG_25 */ "", 66861 /* PGW_LR_TDM_REG_26 */ "", 66862 /* PGW_LR_TDM_REG_27 */ "", 66863 /* PGW_LR_TDM_REG_28 */ "", 66864 /* PGW_LR_TDM_REG_29 */ "", 66865 /* PGW_LR_TDM_REG_30 */ "", 66866 /* PGW_LR_TDM_REG_31 */ "", 66867 /* PGW_LR_TDM_REG_32 */ "", 66868 /* PGW_LR_TDM_REG_33 */ "", 66869 /* PGW_LR_TDM_REG_34 */ "", 66870 /* PGW_LR_TDM_REG_35 */ "", 66871 /* PGW_LR_TDM_REG_36 */ "", 66872 /* PGW_LR_TDM_REG_37 */ "", 66873 /* PGW_LR_TDM_REG_38 */ "", 66874 /* PGW_LR_TDM_REG_39 */ "", 66875 /* PGW_MAC_RSV_MASK */ "", 66876 /* PGW_MIB_RESET */ "", 66877 /* PGW_MIB_RSC0_ECC_STATUS */ "", 66878 /* PGW_MIB_RSC1_ECC_STATUS */ "", 66879 /* PGW_MIB_RSC_DATA_HI_TM_CONTROL */ "", 66880 /* PGW_MIB_RSC_DATA_LO_TM_CONTROL */ "", 66881 /* PGW_MIB_TSC0_ECC_STATUS */ "", 66882 /* PGW_MIB_TSC1_ECC_STATUS */ "", 66883 /* PGW_MIB_TSC_DATA_HI_TM_CONTROL */ "", 66884 /* PGW_MIB_TSC_DATA_LO_TM_CONTROL */ "", 66885 /* PGW_OBM0_CONTROL */ "PGW_OBM0_CONTROL", 66886 /* PGW_OBM0_ECC_ENABLE */ "PGW_OBM0_ECC_ENABLE", 66887 /* PGW_OBM0_ECC_STATUS */ "PGW_OBM0_ECC_STATUS", 66888 /* PGW_OBM0_HIGH_PRI_BYTE_DROP */ "", 66889 /* PGW_OBM0_HIGH_PRI_PKT_DROP */ "", 66890 /* PGW_OBM0_INNER_TPID */ "", 66891 /* PGW_OBM0_LOW_PRI_BYTE_DROP */ "", 66892 /* PGW_OBM0_LOW_PRI_DROP_PROB */ "", 66893 /* PGW_OBM0_LOW_PRI_PKT_DROP */ "", 66894 /* PGW_OBM0_MAX_USAGE */ "PGW_OBM0_MAX_USAGE", 66895 /* PGW_OBM0_NIV_ETHERTYPE */ "", 66896 /* PGW_OBM0_OUTER_TPID */ "", 66897 /* PGW_OBM0_PE_ETHERTYPE */ "", 66898 /* PGW_OBM0_PRIORITY_MAP */ "", 66899 /* PGW_OBM0_SHARED_CONFIG */ "PGW_OBM0_SHARED_CONFIG", 66900 /* PGW_OBM0_THRESHOLD */ "", 66901 /* PGW_OBM0_THRESHOLD2 */ "", 66902 /* PGW_OBM0_TM_CONTROL */ "PGW_OBM0_TM_CONTROL", 66903 /* PGW_OBM0_USE_COUNTER */ "PGW_OBM0_USE_COUNTER", 66904 /* PGW_OBM1_CONTROL */ "PGW_OBM1_CONTROL", 66905 /* PGW_OBM1_ECC_ENABLE */ "PGW_OBM1_ECC_ENABLE", 66906 /* PGW_OBM1_ECC_STATUS */ "PGW_OBM1_ECC_STATUS", 66907 /* PGW_OBM1_HIGH_PRI_BYTE_DROP */ "", 66908 /* PGW_OBM1_HIGH_PRI_PKT_DROP */ "", 66909 /* PGW_OBM1_INNER_TPID */ "", 66910 /* PGW_OBM1_LOW_PRI_BYTE_DROP */ "", 66911 /* PGW_OBM1_LOW_PRI_DROP_PROB */ "", 66912 /* PGW_OBM1_LOW_PRI_PKT_DROP */ "", 66913 /* PGW_OBM1_MAX_USAGE */ "PGW_OBM1_MAX_USAGE", 66914 /* PGW_OBM1_NIV_ETHERTYPE */ "", 66915 /* PGW_OBM1_OUTER_TPID */ "", 66916 /* PGW_OBM1_PE_ETHERTYPE */ "", 66917 /* PGW_OBM1_PRIORITY_MAP */ "", 66918 /* PGW_OBM1_SHARED_CONFIG */ "PGW_OBM1_SHARED_CONFIG", 66919 /* PGW_OBM1_THRESHOLD */ "", 66920 /* PGW_OBM1_THRESHOLD2 */ "", 66921 /* PGW_OBM1_TM_CONTROL */ "PGW_OBM1_TM_CONTROL", 66922 /* PGW_OBM1_USE_COUNTER */ "PGW_OBM1_USE_COUNTER", 66923 /* PGW_OBM2_CONTROL */ "PGW_OBM2_CONTROL", 66924 /* PGW_OBM2_ECC_ENABLE */ "PGW_OBM2_ECC_ENABLE", 66925 /* PGW_OBM2_ECC_STATUS */ "PGW_OBM2_ECC_STATUS", 66926 /* PGW_OBM2_HIGH_PRI_BYTE_DROP */ "", 66927 /* PGW_OBM2_HIGH_PRI_PKT_DROP */ "", 66928 /* PGW_OBM2_INNER_TPID */ "", 66929 /* PGW_OBM2_LOW_PRI_BYTE_DROP */ "", 66930 /* PGW_OBM2_LOW_PRI_DROP_PROB */ "", 66931 /* PGW_OBM2_LOW_PRI_PKT_DROP */ "", 66932 /* PGW_OBM2_MAX_USAGE */ "PGW_OBM2_MAX_USAGE", 66933 /* PGW_OBM2_NIV_ETHERTYPE */ "", 66934 /* PGW_OBM2_OUTER_TPID */ "", 66935 /* PGW_OBM2_PE_ETHERTYPE */ "", 66936 /* PGW_OBM2_PRIORITY_MAP */ "", 66937 /* PGW_OBM2_SHARED_CONFIG */ "PGW_OBM2_SHARED_CONFIG", 66938 /* PGW_OBM2_THRESHOLD */ "", 66939 /* PGW_OBM2_THRESHOLD2 */ "", 66940 /* PGW_OBM2_TM_CONTROL */ "PGW_OBM2_TM_CONTROL", 66941 /* PGW_OBM2_USE_COUNTER */ "PGW_OBM2_USE_COUNTER", 66942 /* PGW_OBM3_CONTROL */ "PGW_OBM3_CONTROL", 66943 /* PGW_OBM3_ECC_ENABLE */ "PGW_OBM3_ECC_ENABLE", 66944 /* PGW_OBM3_ECC_STATUS */ "PGW_OBM3_ECC_STATUS", 66945 /* PGW_OBM3_HIGH_PRI_BYTE_DROP */ "", 66946 /* PGW_OBM3_HIGH_PRI_PKT_DROP */ "", 66947 /* PGW_OBM3_INNER_TPID */ "", 66948 /* PGW_OBM3_LOW_PRI_BYTE_DROP */ "", 66949 /* PGW_OBM3_LOW_PRI_DROP_PROB */ "", 66950 /* PGW_OBM3_LOW_PRI_PKT_DROP */ "", 66951 /* PGW_OBM3_MAX_USAGE */ "PGW_OBM3_MAX_USAGE", 66952 /* PGW_OBM3_NIV_ETHERTYPE */ "", 66953 /* PGW_OBM3_OUTER_TPID */ "", 66954 /* PGW_OBM3_PE_ETHERTYPE */ "", 66955 /* PGW_OBM3_PRIORITY_MAP */ "", 66956 /* PGW_OBM3_SHARED_CONFIG */ "PGW_OBM3_SHARED_CONFIG", 66957 /* PGW_OBM3_THRESHOLD */ "", 66958 /* PGW_OBM3_THRESHOLD2 */ "", 66959 /* PGW_OBM3_TM_CONTROL */ "PGW_OBM3_TM_CONTROL", 66960 /* PGW_OBM3_USE_COUNTER */ "PGW_OBM3_USE_COUNTER", 66961 /* PGW_OBM_DROP_STATUS */ "", 66962 /* PGW_OBM_DROP_STATUS_ENABLE */ "", 66963 /* PGW_OBM_MONITOR_CONFIG */ "", 66964 /* PGW_OBM_MON_HW_CONTROL */ "PGW_OBM_MON_HW_CONTROL", 66965 /* PGW_OBM_PARSING_CONTROL */ "", 66966 /* PGW_OBM_PORT0_FC_CONFIG */ "", 66967 /* PGW_OBM_PORT10_FC_CONFIG */ "", 66968 /* PGW_OBM_PORT11_FC_CONFIG */ "", 66969 /* PGW_OBM_PORT12_FC_CONFIG */ "", 66970 /* PGW_OBM_PORT13_FC_CONFIG */ "", 66971 /* PGW_OBM_PORT14_FC_CONFIG */ "", 66972 /* PGW_OBM_PORT15_FC_CONFIG */ "", 66973 /* PGW_OBM_PORT1_FC_CONFIG */ "", 66974 /* PGW_OBM_PORT2_FC_CONFIG */ "", 66975 /* PGW_OBM_PORT3_FC_CONFIG */ "", 66976 /* PGW_OBM_PORT4_FC_CONFIG */ "", 66977 /* PGW_OBM_PORT5_FC_CONFIG */ "", 66978 /* PGW_OBM_PORT6_FC_CONFIG */ "", 66979 /* PGW_OBM_PORT7_FC_CONFIG */ "", 66980 /* PGW_OBM_PORT8_FC_CONFIG */ "", 66981 /* PGW_OBM_PORT9_FC_CONFIG */ "", 66982 /* PGW_OS_PORT_SPACING_REG_0 */ "", 66983 /* PGW_OS_PORT_SPACING_REG_1 */ "", 66984 /* PGW_OS_PORT_SPACING_REG_2 */ "", 66985 /* PGW_OS_PORT_SPACING_REG_3 */ "", 66986 /* PGW_OS_PORT_SPACING_REG_4 */ "", 66987 /* PGW_OS_PORT_SPACING_REG_5 */ "", 66988 /* PGW_OS_PORT_SPACING_REG_6 */ "", 66989 /* PGW_OS_PORT_SPACING_REG_7 */ "", 66990 /* PGW_OS_PORT_SPACING_REG_8 */ "", 66991 /* PGW_OS_PORT_SPACING_REG_9 */ "", 66992 /* PGW_OS_PORT_SPACING_REG_10 */ "", 66993 /* PGW_OS_PORT_SPACING_REG_11 */ "", 66994 /* PGW_OS_TDM_REG_0 */ "", 66995 /* PGW_OS_TDM_REG_1 */ "", 66996 /* PGW_OS_TDM_REG_2 */ "", 66997 /* PGW_OS_TDM_REG_3 */ "", 66998 /* PGW_OS_TDM_REG_4 */ "", 66999 /* PGW_OS_TDM_REG_5 */ "", 67000 /* PGW_OS_TDM_REG_6 */ "", 67001 /* PGW_OS_TDM_REG_7 */ "", 67002 /* PGW_OS_TDM_REG_8 */ "", 67003 /* PGW_OS_TDM_REG_9 */ "", 67004 /* PGW_OS_TDM_REG_10 */ "", 67005 /* PGW_OS_TDM_REG_11 */ "", 67006 /* PGW_SER_CONTROL */ "", 67007 /* PGW_TDM_CONTROL */ "", 67008 /* PGW_TM_CONTROL */ "", 67009 /* PGW_TSC0_CTRL_REG */ "", 67010 /* PGW_TSC1_CTRL_REG */ "", 67011 /* PGW_TSC2_CTRL_REG */ "", 67012 /* PGW_TSC3_CTRL_REG */ "", 67013 /* PGW_XGXS_COUNTER_MODE */ "", 67014 /* PGW_XLMAC0_TX_ECC_STATUS */ "", 67015 /* PGW_XLMAC1_TX_ECC_STATUS */ "", 67016 /* PGW_XLMAC2_TX_ECC_STATUS */ "", 67017 /* PGW_XLMAC3_TX_ECC_STATUS */ "", 67018 /* PGW_XLP_POWER_DOWN_ENABLE */ "", 67019 /* PGW_XL_BYPASS_LED_CHAIN_CONFIG */ "", 67020 /* PGW_XL_CONFIG */ "", 67021 /* PGW_XL_ECC_CONTROL */ "", 67022 /* PGW_XL_INTR_ENABLE */ "", 67023 /* PGW_XL_INTR_STATUS */ "", 67024 /* PGW_XL_LED_CHAIN_CONFIG */ "", 67025 /* PGW_XL_RXFIFO_ECC_DBE_STATUS */ "", 67026 /* PGW_XL_RXFIFO_ECC_SBE_STATUS */ "", 67027 /* PGW_XL_RXFIFO_OVERFLOW_ERROR */ "", 67028 /* PGW_XL_RXFIFO_SOFT_RESET */ "", 67029 /* PGW_XL_SPARE0_REG */ "", 67030 /* PGW_XL_STSFIFO_ECC_DBE_STATUS */ "", 67031 /* PGW_XL_STSFIFO_ECC_SBE_STATUS */ "", 67032 /* PGW_XL_TM0_CONTROL */ "", 67033 /* PGW_XL_TM10_CONTROL */ "", 67034 /* PGW_XL_TM11_CONTROL */ "", 67035 /* PGW_XL_TM12_CONTROL */ "", 67036 /* PGW_XL_TM13_CONTROL */ "", 67037 /* PGW_XL_TM1_CONTROL */ "", 67038 /* PGW_XL_TM2_CONTROL */ "", 67039 /* PGW_XL_TM3_CONTROL */ "", 67040 /* PGW_XL_TM4_CONTROL */ "", 67041 /* PGW_XL_TM5_CONTROL */ "", 67042 /* PGW_XL_TM6_CONTROL */ "", 67043 /* PGW_XL_TM7_CONTROL */ "", 67044 /* PGW_XL_TM8_CONTROL */ "", 67045 /* PGW_XL_TM9_CONTROL */ "", 67046 /* PGW_XL_TXFIFO0_ECC_DBE_STATUS */ "", 67047 /* PGW_XL_TXFIFO0_ECC_DBE_STATUS_H */ "", 67048 /* PGW_XL_TXFIFO0_ECC_SBE_STATUS */ "", 67049 /* PGW_XL_TXFIFO0_ECC_SBE_STATUS_H */ "", 67050 /* PGW_XL_TXFIFO1_ECC_DBE_STATUS */ "", 67051 /* PGW_XL_TXFIFO1_ECC_DBE_STATUS_H */ "", 67052 /* PGW_XL_TXFIFO1_ECC_SBE_STATUS */ "", 67053 /* PGW_XL_TXFIFO1_ECC_SBE_STATUS_H */ "", 67054 /* PGW_XL_TXFIFO2_ECC_DBE_STATUS */ "", 67055 /* PGW_XL_TXFIFO2_ECC_DBE_STATUS_H */ "", 67056 /* PGW_XL_TXFIFO2_ECC_SBE_STATUS */ "", 67057 /* PGW_XL_TXFIFO2_ECC_SBE_STATUS_H */ "", 67058 /* PGW_XL_TXFIFO3_ECC_DBE_STATUS */ "", 67059 /* PGW_XL_TXFIFO3_ECC_DBE_STATUS_H */ "", 67060 /* PGW_XL_TXFIFO3_ECC_SBE_STATUS */ "", 67061 /* PGW_XL_TXFIFO3_ECC_SBE_STATUS_H */ "", 67062 /* PGW_XL_TXFIFO_CTRL */ "", 67063 /* PGW_XL_TXFIFO_OVERFLOW */ "", 67064 /* PG_COUNT */ "", 67065 /* PG_COUNT_CELL */ "", 67066 /* PG_COUNT_PACKET */ "", 67067 /* PG_CTRL0 */ "", 67068 /* PG_CTRL1 */ "", 67069 /* PG_GBL_HDRM_COUNT */ "", 67070 /* PG_HDRM_COUNT */ "", 67071 /* PG_HDRM_COUNT_CELL */ "", 67072 /* PG_HDRM_COUNT_PACKET */ "", 67073 /* PG_HDRM_LIMIT */ "", 67074 /* PG_HDRM_LIMIT_CELL */ "", 67075 /* PG_HDRM_LIMIT_PACKET */ "", 67076 /* PG_MIN */ "", 67077 /* PG_MIN_CELL */ "", 67078 /* PG_MIN_COUNT */ "", 67079 /* PG_MIN_COUNT_CELL */ "", 67080 /* PG_MIN_COUNT_PACKET */ "", 67081 /* PG_MIN_PACKET */ "", 67082 /* PG_PORT_MIN_COUNT */ "", 67083 /* PG_PORT_MIN_COUNT_CELL */ "", 67084 /* PG_PORT_MIN_COUNT_PACKET */ "", 67085 /* PG_RDE_COUNT_PACKET */ "", 67086 /* PG_RDE_MIN_COUNT_PACKET */ "", 67087 /* PG_RDE_MIN_PACKET */ "", 67088 /* PG_RDE_RESET_OFFSET_PACKET */ "", 67089 /* PG_RDE_RESET_VALUE_PACKET */ "", 67090 /* PG_RDE_SHARED_COUNT_PACKET */ "", 67091 /* PG_RDE_THRESH_SEL2 */ "", 67092 /* PG_RESET_FLOOR */ "", 67093 /* PG_RESET_FLOOR_CELL */ "", 67094 /* PG_RESET_OFFSET */ "", 67095 /* PG_RESET_OFFSET_CELL */ "", 67096 /* PG_RESET_OFFSET_PACKET */ "", 67097 /* PG_RESET_SEL */ "", 67098 /* PG_RESET_VALUE */ "", 67099 /* PG_RESET_VALUE_CELL */ "", 67100 /* PG_RESET_VALUE_PACKET */ "", 67101 /* PG_SHARED_COUNT */ "", 67102 /* PG_SHARED_COUNT_CELL */ "", 67103 /* PG_SHARED_COUNT_PACKET */ "", 67104 /* PG_SHARED_LIMIT_CELL */ "", 67105 /* PG_THRESH_SEL */ "", 67106 /* PG_THRESH_SEL2 */ "", 67107 /* PG_WL_COUNT_CELL */ "", 67108 /* PG_WL_COUNT_PACKET */ "", 67109 /* PG_WL_MIN_CELL */ "", 67110 /* PG_WL_MIN_COUNT_CELL */ "", 67111 /* PG_WL_MIN_COUNT_PACKET */ "", 67112 /* PG_WL_MIN_PACKET */ "", 67113 /* PG_WL_RESET_FLOOR_CELL */ "", 67114 /* PG_WL_RESET_OFFSET_CELL */ "", 67115 /* PG_WL_RESET_OFFSET_PACKET */ "", 67116 /* PG_WL_RESET_VALUE_CELL */ "", 67117 /* PG_WL_RESET_VALUE_PACKET */ "", 67118 /* PG_WL_SHARED_COUNT_CELL */ "", 67119 /* PG_WL_SHARED_COUNT_PACKET */ "", 67120 /* PG_WL_THRESH_SEL2 */ "", 67121 /* PHB2_COS_MAP_PARITY_CONTROL */ "", 67122 /* PHB2_COS_MAP_PARITY_STATUS_INTR */ "", 67123 /* PHB2_COS_MAP_PARITY_STATUS_NACK */ "", 67124 /* PHB_SELECT_TCAM_BIST_CONFIG_64 */ "", 67125 /* PHB_SELECT_TCAM_BIST_CONFIG_64_PIPE0 */ "", 67126 /* PHB_SELECT_TCAM_BIST_CONFIG_64_PIPE1 */ "", 67127 /* PHB_SELECT_TCAM_CAM_BIST_DBG_DATA */ "", 67128 /* PHB_SELECT_TCAM_CAM_BIST_DBG_DATA_PIPE0 */ "", 67129 /* PHB_SELECT_TCAM_CAM_BIST_DBG_DATA_PIPE1 */ "", 67130 /* PHB_SELECT_TCAM_CAM_BIST_STATUS */ "", 67131 /* PHB_SELECT_TCAM_CAM_BIST_STATUS_PIPE0 */ "", 67132 /* PHB_SELECT_TCAM_CAM_BIST_STATUS_PIPE1 */ "", 67133 /* PHB_SELECT_TCAM_CAM_CONTROL */ "", 67134 /* PHB_SELECT_TCAM_CAM_CONTROL_PIPE0 */ "", 67135 /* PHB_SELECT_TCAM_CAM_CONTROL_PIPE1 */ "", 67136 /* PHB_SELECT_TCAM_DATA_CONTROL */ "", 67137 /* PHB_SELECT_TCAM_DATA_CONTROL_PIPE0 */ "", 67138 /* PHB_SELECT_TCAM_DATA_CONTROL_PIPE1 */ "", 67139 /* PIFCSR */ "", 67140 /* PIPEMEMHI_DEBUG */ "", 67141 /* PIPEMEMLO_DEBUG */ "", 67142 /* PKTAGINGLIMIT */ "COS_LIMIT", 67143 /* PKTAGINGLIMIT0 */ "PRI_LIMIT0", 67144 /* PKTAGINGLIMIT1 */ "PRI_LIMIT1", 67145 /* PKTAGINGLIMIT_ */ "", 67146 /* PKTAGINGTIMER */ "AGING_GRAN", 67147 /* PKTBKPSTATUS */ "", 67148 /* PKTBKPSTATUS_0 */ "", 67149 /* PKTBKPSTATUS_1 */ "", 67150 /* PKTBKPSTATUS_2 */ "", 67151 /* PKTBUF_ESM_DROPCNT */ "", 67152 /* PKTBUF_ESM_OFFSET */ "", 67153 /* PKTEXTAGINGLIMIT0 */ "PRI_LIMIT0_EXT", 67154 /* PKTEXTAGINGLIMIT1 */ "PRI_LIMIT1_EXT", 67155 /* PKTEXTAGINGTIMER */ "AGING_GRAN_EXT", 67156 /* PKTGEN0_PCS_SEEDA0 */ "", 67157 /* PKTGEN0_PCS_SEEDA1 */ "", 67158 /* PKTGEN0_PCS_SEEDA2 */ "", 67159 /* PKTGEN0_PCS_SEEDA3 */ "", 67160 /* PKTGEN0_PCS_SEEDB0 */ "", 67161 /* PKTGEN0_PCS_SEEDB1 */ "", 67162 /* PKTGEN0_PCS_SEEDB2 */ "", 67163 /* PKTGEN0_PCS_SEEDB3 */ "", 67164 /* PKTGEN0_PKTGENCTRL1 */ "", 67165 /* PKTGEN0_PRTPCONTROL */ "", 67166 /* PKTGEN1_ERRORMASK0 */ "", 67167 /* PKTGEN1_ERRORMASK1 */ "", 67168 /* PKTGEN1_ERRORMASK2 */ "", 67169 /* PKTGEN1_ERRORMASK3 */ "", 67170 /* PKTGEN1_ERRORMASK4 */ "", 67171 /* PKTGEN1_ERR_INJ_EN0 */ "", 67172 /* PKTGEN1_ERR_INJ_EN1 */ "", 67173 /* PKTGEN1_GLASTEST_ACTADJ */ "", 67174 /* PKTGEN1_GLASTEST_ACTDATA_0 */ "", 67175 /* PKTGEN1_GLASTEST_ACTDATA_1 */ "", 67176 /* PKTGEN1_GLASTEST_ACTDATA_2 */ "", 67177 /* PKTGEN1_GLASTEST_CONTROL */ "", 67178 /* PKTGEN1_GLASTEST_EXP_0 */ "", 67179 /* PKTGEN1_GLASTEST_EXP_1 */ "", 67180 /* PKTGEN1_GLASTEST_EXP_2 */ "", 67181 /* PKTHDR0_0L_POWERDOWN_S0 */ "", 67182 /* PKTHDR0_0L_POWERDOWN_S1 */ "", 67183 /* PKTHDR0_0U_POWERDOWN_S2 */ "", 67184 /* PKTHDR0_1_POWERDOWN_S0 */ "", 67185 /* PKTHDR0_1_POWERDOWN_S1 */ "", 67186 /* PKTHDR0_1_POWERDOWN_S2 */ "", 67187 /* PKTHDRMEMDEBUG */ "", 67188 /* PKTHDRMEMDEBUG1 */ "", 67189 /* PKTHDR_ERR_CNT */ "", 67190 /* PKTINTAGINGLIMIT0 */ "PRI_LIMIT0_INT", 67191 /* PKTINTAGINGLIMIT1 */ "PRI_LIMIT1_INT", 67192 /* PKTINTAGINGTIMER */ "AGING_GRAN_INT", 67193 /* PKTLENGTHMEMDEBUG */ "", 67194 /* PKTLENGTH_POWERDOWN_S0 */ "", 67195 /* PKTLENGTH_POWERDOWN_S1 */ "", 67196 /* PKTLENGTH_POWERDOWN_S2 */ "", 67197 /* PKTLINKMEMDEBUG */ "", 67198 /* PKTMAXBUCKET */ "", 67199 /* PKTMAXBUCKETCONFIG */ "", 67200 /* PKTPORTMAXBUCKET */ "", 67201 /* PKTPORTMAXBUCKETCONFIG */ "", 67202 /* PKTSHAPECONFIG */ "", 67203 /* PKT_DROP_ENABLE */ "", 67204 /* PKT_FLOW_SELECT_TCAM_0_BIST_CONFIG_64 */ "", 67205 /* PKT_FLOW_SELECT_TCAM_0_BIST_CONFIG_64_PIPE0 */ "", 67206 /* PKT_FLOW_SELECT_TCAM_0_BIST_CONFIG_64_PIPE1 */ "", 67207 /* PKT_FLOW_SELECT_TCAM_0_BIST_STATUS */ "", 67208 /* PKT_FLOW_SELECT_TCAM_0_BIST_STATUS_PIPE0 */ "", 67209 /* PKT_FLOW_SELECT_TCAM_0_BIST_STATUS_PIPE1 */ "", 67210 /* PKT_FLOW_SELECT_TCAM_1_BIST_CONFIG_64 */ "", 67211 /* PKT_FLOW_SELECT_TCAM_1_BIST_CONFIG_64_PIPE0 */ "", 67212 /* PKT_FLOW_SELECT_TCAM_1_BIST_CONFIG_64_PIPE1 */ "", 67213 /* PKT_FLOW_SELECT_TCAM_1_BIST_STATUS */ "", 67214 /* PKT_FLOW_SELECT_TCAM_1_BIST_STATUS_PIPE0 */ "", 67215 /* PKT_FLOW_SELECT_TCAM_1_BIST_STATUS_PIPE1 */ "", 67216 /* PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_CONFIG_64 */ "", 67217 /* PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_CONFIG_64_PIPE0 */ "", 67218 /* PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_CONFIG_64_PIPE1 */ "", 67219 /* PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_STATUS */ "", 67220 /* PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_STATUS_PIPE0 */ "", 67221 /* PKT_FLOW_SELECT_TCAM_2_ONLY_CAM_BIST_STATUS_PIPE1 */ "", 67222 /* PKT_LINK_MEM_DEBUG_TM */ "", 67223 /* PLL_GLOBAL_MEM_OPTIONS */ "", 67224 /* PLL_GTIMER_CONFIGURATION */ "", 67225 /* PLL_GTIMER_TRIGGER */ "", 67226 /* PLL_INTERRUPT_MASK_REGISTER */ "", 67227 /* PLL_INTERRUPT_REGISTER */ "", 67228 /* PLL_INTERRUPT_REGISTER_TEST */ "", 67229 /* PLL_MISC_PLL_0_CONFIG */ "", 67230 /* PLL_MISC_PLL_0_STATUS */ "", 67231 /* PLL_RESERVED_MIRROR_ADDR */ "", 67232 /* PLL_RESERVED_MTCD */ "", 67233 /* PLL_RESERVED_MTCP */ "", 67234 /* PLL_RESERVED_PCMI_0 */ "", 67235 /* PLL_RESERVED_PCMI_1 */ "", 67236 /* PLL_RESERVED_PCMI_2 */ "", 67237 /* PLL_RESERVED_PCMI_3 */ "", 67238 /* PLL_RESERVED_PCMI_4 */ "", 67239 /* PLL_RESERVED_PCMI_0_S */ "", 67240 /* PLL_RESERVED_PCMI_0_T */ "", 67241 /* PLL_RESERVED_PCMI_1_S */ "", 67242 /* PLL_RESERVED_PCMI_1_T */ "", 67243 /* PLL_RESERVED_PCMI_2_S */ "", 67244 /* PLL_RESERVED_PCMI_2_T */ "", 67245 /* PLL_RESERVED_PCMI_3_S */ "", 67246 /* PLL_RESERVED_PCMI_3_T */ "", 67247 /* PLL_RESERVED_PCMI_4_S */ "", 67248 /* PLL_RESERVED_PCMI_4_T */ "", 67249 /* PLL_RESERVED_SPARE_0 */ "", 67250 /* PLL_RESERVED_SPARE_1 */ "", 67251 /* PLL_RESERVED_SPARE_2 */ "", 67252 /* PLL_RESERVED_SPARE_3 */ "", 67253 /* PLL_SBUS_BROADCAST_ID */ "", 67254 /* PLL_SBUS_LAST_IN_CHAIN */ "", 67255 /* PMD_X1_CONTROL */ "", 67256 /* PMD_X1_FCLK_PERIOD */ "", 67257 /* PMD_X1_MODE */ "", 67258 /* PMD_X1_OVERRIDE */ "", 67259 /* PMD_X1_PM_TIMER_OFFSET */ "", 67260 /* PMD_X1_STATUS */ "", 67261 /* PMD_X4_CONTROL */ "", 67262 /* PMD_X4_EEE_CONTROL */ "", 67263 /* PMD_X4_EEE_STATUS */ "", 67264 /* PMD_X4_LATCH_STATUS */ "", 67265 /* PMD_X4_MODE */ "", 67266 /* PMD_X4_OVERRIDE */ "", 67267 /* PMD_X4_PMD_RX_FIXED_LATENCY_FRAC */ "", 67268 /* PMD_X4_PMD_RX_FIXED_LATENCY_INT */ "", 67269 /* PMD_X4_PMD_TX_FIXED_LATENCY */ "", 67270 /* PMD_X4_RX_FIXED_LATENCY */ "", 67271 /* PMD_X4_STATUS */ "", 67272 /* PMD_X4_TX_FIXED_LATENCY */ "", 67273 /* PMD_X4_UI_VALUE_HI */ "", 67274 /* PMD_X4_UI_VALUE_LO */ "", 67275 /* PMON_AXI1_GLOBAL_TRIGGER */ "", 67276 /* PMON_AXI1_GLOBAL_TRIGGER_ENABLE */ "", 67277 /* PMON_AXI1_PERFORMANCE_MONITOR_MEMORY_CONTROL */ "", 67278 /* PMON_AXI1_PERFORMANCE_MONITOR_RESET_CONTROL */ "", 67279 /* PMON_AXI1_PMON_DEBUG_CONTROL */ "", 67280 /* PMON_AXI1_PMON_DEBUG_STATUS */ "", 67281 /* PMON_AXI1_PMON_INTR_EN */ "", 67282 /* PMON_AXI1_PMON_INTR_STATUS */ "", 67283 /* PMON_AXI1_SET_A_UNIT_0_BRESP_CHANNEL_PENDING */ "", 67284 /* PMON_AXI1_SET_A_UNIT_0_CTRL */ "", 67285 /* PMON_AXI1_SET_A_UNIT_0_ECC_ERR_LOG */ "", 67286 /* PMON_AXI1_SET_A_UNIT_0_EVNT_DEBUG_MODE_CTRL */ "", 67287 /* PMON_AXI1_SET_A_UNIT_0_EVNT_DEBUG_TIMEOUT */ "", 67288 /* PMON_AXI1_SET_A_UNIT_0_ID0 */ "", 67289 /* PMON_AXI1_SET_A_UNIT_0_ID1 */ "", 67290 /* PMON_AXI1_SET_A_UNIT_0_ID0_MASK */ "", 67291 /* PMON_AXI1_SET_A_UNIT_0_ID1_MASK */ "", 67292 /* PMON_AXI1_SET_A_UNIT_0_IDLE_TIME */ "", 67293 /* PMON_AXI1_SET_A_UNIT_0_LOOP_COUNT */ "", 67294 /* PMON_AXI1_SET_A_UNIT_0_MEASUREMENT_INTERVAL */ "", 67295 /* PMON_AXI1_SET_A_UNIT_0_PMON_FORMAT */ "", 67296 /* PMON_AXI1_SET_A_UNIT_0_RDFIFO_ECC_ERR_LOG */ "", 67297 /* PMON_AXI1_SET_A_UNIT_0_RD_CHANNEL_PENDING */ "", 67298 /* PMON_AXI1_SET_A_UNIT_0_RD_WR_FIFO_CTRL */ "", 67299 /* PMON_AXI1_SET_A_UNIT_0_READ_CHANNEL_FIFO_HIGH */ "", 67300 /* PMON_AXI1_SET_A_UNIT_0_READ_CHANNEL_FIFO_LOW */ "", 67301 /* PMON_AXI1_SET_A_UNIT_0_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67302 /* PMON_AXI1_SET_A_UNIT_0_START_ADDRESS */ "", 67303 /* PMON_AXI1_SET_A_UNIT_0_START_ADDRESS_MASK */ "", 67304 /* PMON_AXI1_SET_A_UNIT_0_START_ADDRESS_MASK_UPPER */ "", 67305 /* PMON_AXI1_SET_A_UNIT_0_START_ADDRESS_UPPER */ "", 67306 /* PMON_AXI1_SET_A_UNIT_0_STATUS */ "", 67307 /* PMON_AXI1_SET_A_UNIT_0_WRFIFO_ECC_ERR_LOG */ "", 67308 /* PMON_AXI1_SET_A_UNIT_0_WRITE_CHANNEL_FIFO_HIGH */ "", 67309 /* PMON_AXI1_SET_A_UNIT_0_WRITE_CHANNEL_FIFO_LOW */ "", 67310 /* PMON_AXI1_SET_A_UNIT_0_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67311 /* PMON_AXI1_SET_A_UNIT_0_WR_CHANNEL_PENDING */ "", 67312 /* PMON_AXI1_SET_A_UNIT_1_BRESP_CHANNEL_PENDING */ "", 67313 /* PMON_AXI1_SET_A_UNIT_1_CTRL */ "", 67314 /* PMON_AXI1_SET_A_UNIT_1_ECC_ERR_LOG */ "", 67315 /* PMON_AXI1_SET_A_UNIT_1_EVNT_DEBUG_MODE_CTRL */ "", 67316 /* PMON_AXI1_SET_A_UNIT_1_EVNT_DEBUG_TIMEOUT */ "", 67317 /* PMON_AXI1_SET_A_UNIT_1_ID0 */ "", 67318 /* PMON_AXI1_SET_A_UNIT_1_ID1 */ "", 67319 /* PMON_AXI1_SET_A_UNIT_1_ID0_MASK */ "", 67320 /* PMON_AXI1_SET_A_UNIT_1_ID1_MASK */ "", 67321 /* PMON_AXI1_SET_A_UNIT_1_IDLE_TIME */ "", 67322 /* PMON_AXI1_SET_A_UNIT_1_LOOP_COUNT */ "", 67323 /* PMON_AXI1_SET_A_UNIT_1_MEASUREMENT_INTERVAL */ "", 67324 /* PMON_AXI1_SET_A_UNIT_1_PMON_FORMAT */ "", 67325 /* PMON_AXI1_SET_A_UNIT_1_RDFIFO_ECC_ERR_LOG */ "", 67326 /* PMON_AXI1_SET_A_UNIT_1_RD_CHANNEL_PENDING */ "", 67327 /* PMON_AXI1_SET_A_UNIT_1_RD_WR_FIFO_CTRL */ "", 67328 /* PMON_AXI1_SET_A_UNIT_1_READ_CHANNEL_FIFO_HIGH */ "", 67329 /* PMON_AXI1_SET_A_UNIT_1_READ_CHANNEL_FIFO_LOW */ "", 67330 /* PMON_AXI1_SET_A_UNIT_1_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67331 /* PMON_AXI1_SET_A_UNIT_1_START_ADDRESS */ "", 67332 /* PMON_AXI1_SET_A_UNIT_1_START_ADDRESS_MASK */ "", 67333 /* PMON_AXI1_SET_A_UNIT_1_START_ADDRESS_MASK_UPPER */ "", 67334 /* PMON_AXI1_SET_A_UNIT_1_START_ADDRESS_UPPER */ "", 67335 /* PMON_AXI1_SET_A_UNIT_1_STATUS */ "", 67336 /* PMON_AXI1_SET_A_UNIT_1_WRFIFO_ECC_ERR_LOG */ "", 67337 /* PMON_AXI1_SET_A_UNIT_1_WRITE_CHANNEL_FIFO_HIGH */ "", 67338 /* PMON_AXI1_SET_A_UNIT_1_WRITE_CHANNEL_FIFO_LOW */ "", 67339 /* PMON_AXI1_SET_A_UNIT_1_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67340 /* PMON_AXI1_SET_A_UNIT_1_WR_CHANNEL_PENDING */ "", 67341 /* PMON_AXI1_SET_B_UNIT_0_BRESP_CHANNEL_PENDING */ "", 67342 /* PMON_AXI1_SET_B_UNIT_0_CTRL */ "", 67343 /* PMON_AXI1_SET_B_UNIT_0_ECC_ERR_LOG */ "", 67344 /* PMON_AXI1_SET_B_UNIT_0_EVNT_DEBUG_MODE_CTRL */ "", 67345 /* PMON_AXI1_SET_B_UNIT_0_EVNT_DEBUG_TIMEOUT */ "", 67346 /* PMON_AXI1_SET_B_UNIT_0_ID0 */ "", 67347 /* PMON_AXI1_SET_B_UNIT_0_ID1 */ "", 67348 /* PMON_AXI1_SET_B_UNIT_0_ID0_MASK */ "", 67349 /* PMON_AXI1_SET_B_UNIT_0_ID1_MASK */ "", 67350 /* PMON_AXI1_SET_B_UNIT_0_IDLE_TIME */ "", 67351 /* PMON_AXI1_SET_B_UNIT_0_LOOP_COUNT */ "", 67352 /* PMON_AXI1_SET_B_UNIT_0_MEASUREMENT_INTERVAL */ "", 67353 /* PMON_AXI1_SET_B_UNIT_0_PMON_FORMAT */ "", 67354 /* PMON_AXI1_SET_B_UNIT_0_RDFIFO_ECC_ERR_LOG */ "", 67355 /* PMON_AXI1_SET_B_UNIT_0_RD_CHANNEL_PENDING */ "", 67356 /* PMON_AXI1_SET_B_UNIT_0_RD_WR_FIFO_CTRL */ "", 67357 /* PMON_AXI1_SET_B_UNIT_0_READ_CHANNEL_FIFO_HIGH */ "", 67358 /* PMON_AXI1_SET_B_UNIT_0_READ_CHANNEL_FIFO_LOW */ "", 67359 /* PMON_AXI1_SET_B_UNIT_0_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67360 /* PMON_AXI1_SET_B_UNIT_0_START_ADDRESS */ "", 67361 /* PMON_AXI1_SET_B_UNIT_0_START_ADDRESS_MASK */ "", 67362 /* PMON_AXI1_SET_B_UNIT_0_START_ADDRESS_MASK_UPPER */ "", 67363 /* PMON_AXI1_SET_B_UNIT_0_START_ADDRESS_UPPER */ "", 67364 /* PMON_AXI1_SET_B_UNIT_0_STATUS */ "", 67365 /* PMON_AXI1_SET_B_UNIT_0_WRFIFO_ECC_ERR_LOG */ "", 67366 /* PMON_AXI1_SET_B_UNIT_0_WRITE_CHANNEL_FIFO_HIGH */ "", 67367 /* PMON_AXI1_SET_B_UNIT_0_WRITE_CHANNEL_FIFO_LOW */ "", 67368 /* PMON_AXI1_SET_B_UNIT_0_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67369 /* PMON_AXI1_SET_B_UNIT_0_WR_CHANNEL_PENDING */ "", 67370 /* PMON_AXI1_SET_B_UNIT_1_BRESP_CHANNEL_PENDING */ "", 67371 /* PMON_AXI1_SET_B_UNIT_1_CTRL */ "", 67372 /* PMON_AXI1_SET_B_UNIT_1_ECC_ERR_LOG */ "", 67373 /* PMON_AXI1_SET_B_UNIT_1_EVNT_DEBUG_MODE_CTRL */ "", 67374 /* PMON_AXI1_SET_B_UNIT_1_EVNT_DEBUG_TIMEOUT */ "", 67375 /* PMON_AXI1_SET_B_UNIT_1_ID0 */ "", 67376 /* PMON_AXI1_SET_B_UNIT_1_ID1 */ "", 67377 /* PMON_AXI1_SET_B_UNIT_1_ID0_MASK */ "", 67378 /* PMON_AXI1_SET_B_UNIT_1_ID1_MASK */ "", 67379 /* PMON_AXI1_SET_B_UNIT_1_IDLE_TIME */ "", 67380 /* PMON_AXI1_SET_B_UNIT_1_LOOP_COUNT */ "", 67381 /* PMON_AXI1_SET_B_UNIT_1_MEASUREMENT_INTERVAL */ "", 67382 /* PMON_AXI1_SET_B_UNIT_1_PMON_FORMAT */ "", 67383 /* PMON_AXI1_SET_B_UNIT_1_RDFIFO_ECC_ERR_LOG */ "", 67384 /* PMON_AXI1_SET_B_UNIT_1_RD_CHANNEL_PENDING */ "", 67385 /* PMON_AXI1_SET_B_UNIT_1_RD_WR_FIFO_CTRL */ "", 67386 /* PMON_AXI1_SET_B_UNIT_1_READ_CHANNEL_FIFO_HIGH */ "", 67387 /* PMON_AXI1_SET_B_UNIT_1_READ_CHANNEL_FIFO_LOW */ "", 67388 /* PMON_AXI1_SET_B_UNIT_1_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67389 /* PMON_AXI1_SET_B_UNIT_1_START_ADDRESS */ "", 67390 /* PMON_AXI1_SET_B_UNIT_1_START_ADDRESS_MASK */ "", 67391 /* PMON_AXI1_SET_B_UNIT_1_START_ADDRESS_MASK_UPPER */ "", 67392 /* PMON_AXI1_SET_B_UNIT_1_START_ADDRESS_UPPER */ "", 67393 /* PMON_AXI1_SET_B_UNIT_1_STATUS */ "", 67394 /* PMON_AXI1_SET_B_UNIT_1_WRFIFO_ECC_ERR_LOG */ "", 67395 /* PMON_AXI1_SET_B_UNIT_1_WRITE_CHANNEL_FIFO_HIGH */ "", 67396 /* PMON_AXI1_SET_B_UNIT_1_WRITE_CHANNEL_FIFO_LOW */ "", 67397 /* PMON_AXI1_SET_B_UNIT_1_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67398 /* PMON_AXI1_SET_B_UNIT_1_WR_CHANNEL_PENDING */ "", 67399 /* PMON_AXI_GLOBAL_TRIGGER */ "", 67400 /* PMON_AXI_GLOBAL_TRIGGER_ENABLE */ "", 67401 /* PMON_AXI_PERFORMANCE_MONITOR_MEMORY_CONTROL */ "", 67402 /* PMON_AXI_PERFORMANCE_MONITOR_RESET_CONTROL */ "", 67403 /* PMON_AXI_PMON_DEBUG_CONTROL */ "", 67404 /* PMON_AXI_PMON_DEBUG_STATUS */ "", 67405 /* PMON_AXI_PMON_INTR_EN */ "", 67406 /* PMON_AXI_PMON_INTR_STATUS */ "", 67407 /* PMON_AXI_SET_A_UNIT_0_BRESP_CHANNEL_PENDING */ "", 67408 /* PMON_AXI_SET_A_UNIT_0_CTRL */ "", 67409 /* PMON_AXI_SET_A_UNIT_0_ECC_ERR_LOG */ "", 67410 /* PMON_AXI_SET_A_UNIT_0_EVNT_DEBUG_MODE_CTRL */ "", 67411 /* PMON_AXI_SET_A_UNIT_0_EVNT_DEBUG_TIMEOUT */ "", 67412 /* PMON_AXI_SET_A_UNIT_0_ID0 */ "", 67413 /* PMON_AXI_SET_A_UNIT_0_ID1 */ "", 67414 /* PMON_AXI_SET_A_UNIT_0_ID0_MASK */ "", 67415 /* PMON_AXI_SET_A_UNIT_0_ID1_MASK */ "", 67416 /* PMON_AXI_SET_A_UNIT_0_IDLE_TIME */ "", 67417 /* PMON_AXI_SET_A_UNIT_0_LOOP_COUNT */ "", 67418 /* PMON_AXI_SET_A_UNIT_0_MEASUREMENT_INTERVAL */ "", 67419 /* PMON_AXI_SET_A_UNIT_0_PMON_FORMAT */ "", 67420 /* PMON_AXI_SET_A_UNIT_0_RDFIFO_ECC_ERR_LOG */ "", 67421 /* PMON_AXI_SET_A_UNIT_0_RD_CHANNEL_PENDING */ "", 67422 /* PMON_AXI_SET_A_UNIT_0_RD_WR_FIFO_CTRL */ "", 67423 /* PMON_AXI_SET_A_UNIT_0_READ_CHANNEL_FIFO_HIGH */ "", 67424 /* PMON_AXI_SET_A_UNIT_0_READ_CHANNEL_FIFO_LOW */ "", 67425 /* PMON_AXI_SET_A_UNIT_0_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67426 /* PMON_AXI_SET_A_UNIT_0_START_ADDRESS */ "", 67427 /* PMON_AXI_SET_A_UNIT_0_START_ADDRESS_MASK */ "", 67428 /* PMON_AXI_SET_A_UNIT_0_START_ADDRESS_MASK_UPPER */ "", 67429 /* PMON_AXI_SET_A_UNIT_0_START_ADDRESS_UPPER */ "", 67430 /* PMON_AXI_SET_A_UNIT_0_STATUS */ "", 67431 /* PMON_AXI_SET_A_UNIT_0_WRFIFO_ECC_ERR_LOG */ "", 67432 /* PMON_AXI_SET_A_UNIT_0_WRITE_CHANNEL_FIFO_HIGH */ "", 67433 /* PMON_AXI_SET_A_UNIT_0_WRITE_CHANNEL_FIFO_LOW */ "", 67434 /* PMON_AXI_SET_A_UNIT_0_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67435 /* PMON_AXI_SET_A_UNIT_0_WR_CHANNEL_PENDING */ "", 67436 /* PMON_AXI_SET_A_UNIT_1_BRESP_CHANNEL_PENDING */ "", 67437 /* PMON_AXI_SET_A_UNIT_1_CTRL */ "", 67438 /* PMON_AXI_SET_A_UNIT_1_ECC_ERR_LOG */ "", 67439 /* PMON_AXI_SET_A_UNIT_1_EVNT_DEBUG_MODE_CTRL */ "", 67440 /* PMON_AXI_SET_A_UNIT_1_EVNT_DEBUG_TIMEOUT */ "", 67441 /* PMON_AXI_SET_A_UNIT_1_ID0 */ "", 67442 /* PMON_AXI_SET_A_UNIT_1_ID1 */ "", 67443 /* PMON_AXI_SET_A_UNIT_1_ID0_MASK */ "", 67444 /* PMON_AXI_SET_A_UNIT_1_ID1_MASK */ "", 67445 /* PMON_AXI_SET_A_UNIT_1_IDLE_TIME */ "", 67446 /* PMON_AXI_SET_A_UNIT_1_LOOP_COUNT */ "", 67447 /* PMON_AXI_SET_A_UNIT_1_MEASUREMENT_INTERVAL */ "", 67448 /* PMON_AXI_SET_A_UNIT_1_PMON_FORMAT */ "", 67449 /* PMON_AXI_SET_A_UNIT_1_RDFIFO_ECC_ERR_LOG */ "", 67450 /* PMON_AXI_SET_A_UNIT_1_RD_CHANNEL_PENDING */ "", 67451 /* PMON_AXI_SET_A_UNIT_1_RD_WR_FIFO_CTRL */ "", 67452 /* PMON_AXI_SET_A_UNIT_1_READ_CHANNEL_FIFO_HIGH */ "", 67453 /* PMON_AXI_SET_A_UNIT_1_READ_CHANNEL_FIFO_LOW */ "", 67454 /* PMON_AXI_SET_A_UNIT_1_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67455 /* PMON_AXI_SET_A_UNIT_1_START_ADDRESS */ "", 67456 /* PMON_AXI_SET_A_UNIT_1_START_ADDRESS_MASK */ "", 67457 /* PMON_AXI_SET_A_UNIT_1_START_ADDRESS_MASK_UPPER */ "", 67458 /* PMON_AXI_SET_A_UNIT_1_START_ADDRESS_UPPER */ "", 67459 /* PMON_AXI_SET_A_UNIT_1_STATUS */ "", 67460 /* PMON_AXI_SET_A_UNIT_1_WRFIFO_ECC_ERR_LOG */ "", 67461 /* PMON_AXI_SET_A_UNIT_1_WRITE_CHANNEL_FIFO_HIGH */ "", 67462 /* PMON_AXI_SET_A_UNIT_1_WRITE_CHANNEL_FIFO_LOW */ "", 67463 /* PMON_AXI_SET_A_UNIT_1_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67464 /* PMON_AXI_SET_A_UNIT_1_WR_CHANNEL_PENDING */ "", 67465 /* PMON_AXI_SET_B_UNIT_0_BRESP_CHANNEL_PENDING */ "", 67466 /* PMON_AXI_SET_B_UNIT_0_CTRL */ "", 67467 /* PMON_AXI_SET_B_UNIT_0_ECC_ERR_LOG */ "", 67468 /* PMON_AXI_SET_B_UNIT_0_EVNT_DEBUG_MODE_CTRL */ "", 67469 /* PMON_AXI_SET_B_UNIT_0_EVNT_DEBUG_TIMEOUT */ "", 67470 /* PMON_AXI_SET_B_UNIT_0_ID0 */ "", 67471 /* PMON_AXI_SET_B_UNIT_0_ID1 */ "", 67472 /* PMON_AXI_SET_B_UNIT_0_ID0_MASK */ "", 67473 /* PMON_AXI_SET_B_UNIT_0_ID1_MASK */ "", 67474 /* PMON_AXI_SET_B_UNIT_0_IDLE_TIME */ "", 67475 /* PMON_AXI_SET_B_UNIT_0_LOOP_COUNT */ "", 67476 /* PMON_AXI_SET_B_UNIT_0_MEASUREMENT_INTERVAL */ "", 67477 /* PMON_AXI_SET_B_UNIT_0_PMON_FORMAT */ "", 67478 /* PMON_AXI_SET_B_UNIT_0_RDFIFO_ECC_ERR_LOG */ "", 67479 /* PMON_AXI_SET_B_UNIT_0_RD_CHANNEL_PENDING */ "", 67480 /* PMON_AXI_SET_B_UNIT_0_RD_WR_FIFO_CTRL */ "", 67481 /* PMON_AXI_SET_B_UNIT_0_READ_CHANNEL_FIFO_HIGH */ "", 67482 /* PMON_AXI_SET_B_UNIT_0_READ_CHANNEL_FIFO_LOW */ "", 67483 /* PMON_AXI_SET_B_UNIT_0_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67484 /* PMON_AXI_SET_B_UNIT_0_START_ADDRESS */ "", 67485 /* PMON_AXI_SET_B_UNIT_0_START_ADDRESS_MASK */ "", 67486 /* PMON_AXI_SET_B_UNIT_0_START_ADDRESS_MASK_UPPER */ "", 67487 /* PMON_AXI_SET_B_UNIT_0_START_ADDRESS_UPPER */ "", 67488 /* PMON_AXI_SET_B_UNIT_0_STATUS */ "", 67489 /* PMON_AXI_SET_B_UNIT_0_WRFIFO_ECC_ERR_LOG */ "", 67490 /* PMON_AXI_SET_B_UNIT_0_WRITE_CHANNEL_FIFO_HIGH */ "", 67491 /* PMON_AXI_SET_B_UNIT_0_WRITE_CHANNEL_FIFO_LOW */ "", 67492 /* PMON_AXI_SET_B_UNIT_0_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67493 /* PMON_AXI_SET_B_UNIT_0_WR_CHANNEL_PENDING */ "", 67494 /* PMON_AXI_SET_B_UNIT_1_BRESP_CHANNEL_PENDING */ "", 67495 /* PMON_AXI_SET_B_UNIT_1_CTRL */ "", 67496 /* PMON_AXI_SET_B_UNIT_1_ECC_ERR_LOG */ "", 67497 /* PMON_AXI_SET_B_UNIT_1_EVNT_DEBUG_MODE_CTRL */ "", 67498 /* PMON_AXI_SET_B_UNIT_1_EVNT_DEBUG_TIMEOUT */ "", 67499 /* PMON_AXI_SET_B_UNIT_1_ID0 */ "", 67500 /* PMON_AXI_SET_B_UNIT_1_ID1 */ "", 67501 /* PMON_AXI_SET_B_UNIT_1_ID0_MASK */ "", 67502 /* PMON_AXI_SET_B_UNIT_1_ID1_MASK */ "", 67503 /* PMON_AXI_SET_B_UNIT_1_IDLE_TIME */ "", 67504 /* PMON_AXI_SET_B_UNIT_1_LOOP_COUNT */ "", 67505 /* PMON_AXI_SET_B_UNIT_1_MEASUREMENT_INTERVAL */ "", 67506 /* PMON_AXI_SET_B_UNIT_1_PMON_FORMAT */ "", 67507 /* PMON_AXI_SET_B_UNIT_1_RDFIFO_ECC_ERR_LOG */ "", 67508 /* PMON_AXI_SET_B_UNIT_1_RD_CHANNEL_PENDING */ "", 67509 /* PMON_AXI_SET_B_UNIT_1_RD_WR_FIFO_CTRL */ "", 67510 /* PMON_AXI_SET_B_UNIT_1_READ_CHANNEL_FIFO_HIGH */ "", 67511 /* PMON_AXI_SET_B_UNIT_1_READ_CHANNEL_FIFO_LOW */ "", 67512 /* PMON_AXI_SET_B_UNIT_1_READ_CHANNEL_FIFO_LOW_UPPER */ "", 67513 /* PMON_AXI_SET_B_UNIT_1_START_ADDRESS */ "", 67514 /* PMON_AXI_SET_B_UNIT_1_START_ADDRESS_MASK */ "", 67515 /* PMON_AXI_SET_B_UNIT_1_START_ADDRESS_MASK_UPPER */ "", 67516 /* PMON_AXI_SET_B_UNIT_1_START_ADDRESS_UPPER */ "", 67517 /* PMON_AXI_SET_B_UNIT_1_STATUS */ "", 67518 /* PMON_AXI_SET_B_UNIT_1_WRFIFO_ECC_ERR_LOG */ "", 67519 /* PMON_AXI_SET_B_UNIT_1_WRITE_CHANNEL_FIFO_HIGH */ "", 67520 /* PMON_AXI_SET_B_UNIT_1_WRITE_CHANNEL_FIFO_LOW */ "", 67521 /* PMON_AXI_SET_B_UNIT_1_WRITE_CHANNEL_FIFO_LOW_UPPER */ "", 67522 /* PMON_AXI_SET_B_UNIT_1_WR_CHANNEL_PENDING */ "", 67523 /* PMQPORT_WC_UCMEM_CTRL */ "", 67524 /* PMQ_ECC */ "", 67525 /* PMQ_ECC_INIT_CTRL */ "", 67526 /* PMQ_ECC_INIT_STS */ "", 67527 /* PMQ_GP_ECCERR_STS */ "", 67528 /* PMQ_PM_VERSION_ID */ "", 67529 /* PMQ_UMAC_ECCERR_STS */ "", 67530 /* PMQ_XGXS0_CTRL_REG */ "", 67531 /* PMU_PDG_BISR_LOAD_DONE_STATUS */ "", 67532 /* PMU_PDG_BISR_LOAD_DONE_STATUS_1 */ "", 67533 /* PNOR_DIRECT_CMD */ "", 67534 /* PNOR_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 67535 /* PNOR_IDM_IDM_ERROR_LOG_COMPLETE */ "", 67536 /* PNOR_IDM_IDM_ERROR_LOG_CONTROL */ "", 67537 /* PNOR_IDM_IDM_ERROR_LOG_FLAGS */ "", 67538 /* PNOR_IDM_IDM_ERROR_LOG_ID */ "", 67539 /* PNOR_IDM_IDM_ERROR_LOG_STATUS */ "", 67540 /* PNOR_IDM_IDM_INTERRUPT_STATUS */ "", 67541 /* PNOR_IDM_IDM_IO_CONTROL_DIRECT */ "", 67542 /* PNOR_IDM_IDM_IO_STATUS */ "", 67543 /* PNOR_IDM_IDM_RESET_CONTROL */ "", 67544 /* PNOR_IDM_IDM_RESET_READ_ID */ "", 67545 /* PNOR_IDM_IDM_RESET_STATUS */ "", 67546 /* PNOR_IDM_IDM_RESET_WRITE_ID */ "", 67547 /* PNOR_MEMC_STATUS */ "", 67548 /* PNOR_MEMIF_CFG */ "", 67549 /* PNOR_MEM_CFG_CLR */ "", 67550 /* PNOR_MEM_CFG_SET */ "", 67551 /* PNOR_OPMODE0_0 */ "", 67552 /* PNOR_OPMODE0_1 */ "", 67553 /* PNOR_OPMODE0_2 */ "", 67554 /* PNOR_PCELL_ID_0 */ "", 67555 /* PNOR_PCELL_ID_1 */ "", 67556 /* PNOR_PCELL_ID_2 */ "", 67557 /* PNOR_PCELL_ID_3 */ "", 67558 /* PNOR_PERIPH_ID_0 */ "", 67559 /* PNOR_PERIPH_ID_1 */ "", 67560 /* PNOR_PERIPH_ID_2 */ "", 67561 /* PNOR_PERIPH_ID_3 */ "", 67562 /* PNOR_REFRESH_0 */ "", 67563 /* PNOR_SET_CYCLES */ "", 67564 /* PNOR_SET_OPMODE */ "", 67565 /* PNOR_SRAM_CYCLES0_0 */ "", 67566 /* PNOR_SRAM_CYCLES0_1 */ "", 67567 /* PNOR_SRAM_CYCLES0_2 */ "", 67568 /* PNOR_USER_CONFIG */ "", 67569 /* PNOR_USER_STATUS */ "", 67570 /* POOL_DROP_STATE */ "", 67571 /* PORTCNTMEMDEBUG */ "", 67572 /* PORTCNTMEMDEBUG1 */ "", 67573 /* PORTGRPMETERINGBUCKET */ "", 67574 /* PORTGRPMETERINGCONFIG */ "", 67575 /* PORTGRPMETERINGCONFIG1 */ "", 67576 /* PORTGRP_WDRRCOUNT */ "", 67577 /* PORTGRP_WDRR_CONFIG */ "", 67578 /* PORT_BRIDGE_BMAP */ "", 67579 /* PORT_BRIDGE_BMAP_64 */ "PORT_BRIDGE_BMAP", 67580 /* PORT_BRIDGE_BMAP_HI */ "", 67581 /* PORT_BRIDGE_BMAP_HI_64 */ "PORT_BRIDGE_BMAP_HI_64", 67582 /* PORT_BRIDGE_BMAP_LO_64 */ "PORT_BRIDGE_BMAP_LO_64", 67583 /* PORT_BRIDGE_MIRROR_BMAP */ "", 67584 /* PORT_BRIDGE_MIRROR_BMAP_64 */ "PORT_BRIDGE_MIRROR_BMAP", 67585 /* PORT_BRIDGE_MIRROR_BMAP_HI */ "PORT_BRIDGE_MIRROR_BMAP_HI", 67586 /* PORT_BRIDGE_MIRROR_BMAP_LO */ "PORT_BRIDGE_MIRROR_BMAP_LO", 67587 /* PORT_CBL_PARITY_CONTROL */ "", 67588 /* PORT_CBL_PARITY_STATUS_INTR */ "", 67589 /* PORT_CBL_PARITY_STATUS_NACK */ "", 67590 /* PORT_CBL_TABLE_MODBASE_PARITY_CONTROL */ "", 67591 /* PORT_CBL_TABLE_MODBASE_PARITY_STATUS_INTR */ "", 67592 /* PORT_CBL_TABLE_MODBASE_PARITY_STATUS_NACK */ "", 67593 /* PORT_CBL_TABLE_PARITY_CONTROL */ "", 67594 /* PORT_CBL_TABLE_PARITY_STATUS */ "", 67595 /* PORT_CBL_TABLE_PARITY_STATUS_INTR */ "", 67596 /* PORT_CBL_TABLE_PARITY_STATUS_NACK */ "", 67597 /* PORT_CDC_RXFIFO_CELL_CNT */ "", 67598 /* PORT_CDC_RXFIFO_ECC_STATUS */ "", 67599 /* PORT_CDC_RXFIFO_OVRFLW */ "", 67600 /* PORT_CDC_TXFIFO_CELL_CNT */ "", 67601 /* PORT_CDC_TXFIFO_CELL_REQ_CNT */ "", 67602 /* PORT_CDC_TXFIFO_ECC_STATUS */ "", 67603 /* PORT_CDC_TXFIFO_OVRFLW */ "", 67604 /* PORT_CMAC_MODE */ "", 67605 /* PORT_CNTMAXSIZE */ "", 67606 /* PORT_CONFIG */ "", 67607 /* PORT_CONFIG0 */ "", 67608 /* PORT_CONFIG1 */ "", 67609 /* PORT_CONFIG2 */ "", 67610 /* PORT_CONFIG3 */ "", 67611 /* PORT_COUNT */ "", 67612 /* PORT_COUNT_CELL */ "", 67613 /* PORT_COUNT_PACKET */ "", 67614 /* PORT_ECC_CONTROL */ "", 67615 /* PORT_EEE_CLOCK_GATE */ "", 67616 /* PORT_EEE_CORE0_CLOCK_GATE_COUNTER */ "", 67617 /* PORT_EEE_CORE1_CLOCK_GATE_COUNTER */ "", 67618 /* PORT_EEE_CORE2_CLOCK_GATE_COUNTER */ "", 67619 /* PORT_EEE_CORE_0_CLOCK_GATE_COUNTER */ "", 67620 /* PORT_EEE_CORE_1_CLOCK_GATE_COUNTER */ "", 67621 /* PORT_EEE_CORE_2_CLOCK_GATE_COUNTER */ "", 67622 /* PORT_EEE_COUNTER_MODE */ "", 67623 /* PORT_EEE_DURATION_TIMER_PULSE */ "", 67624 /* PORT_EHG0_RXFIFO_ECC_STATUS */ "", 67625 /* PORT_EHG0_RX_DATA_ECC_STATUS */ "", 67626 /* PORT_EHG0_RX_MASK_ECC_STATUS */ "", 67627 /* PORT_EHG0_TX_DATA_ECC_STATUS */ "", 67628 /* PORT_EHG1_RXFIFO_ECC_STATUS */ "", 67629 /* PORT_EHG1_RX_DATA_ECC_STATUS */ "", 67630 /* PORT_EHG1_RX_MASK_ECC_STATUS */ "", 67631 /* PORT_EHG1_TX_DATA_ECC_STATUS */ "", 67632 /* PORT_EHG2_RXFIFO_ECC_STATUS */ "", 67633 /* PORT_EHG2_RX_DATA_ECC_STATUS */ "", 67634 /* PORT_EHG2_RX_MASK_ECC_STATUS */ "", 67635 /* PORT_EHG2_TX_DATA_ECC_STATUS */ "", 67636 /* PORT_EHG_ECC_CONTROL */ "", 67637 /* PORT_EHG_FORCE_DOUBLE_BIT_ERROR */ "", 67638 /* PORT_EHG_FORCE_SINGLE_BIT_ERROR */ "", 67639 /* PORT_EHG_RXFIFO_CELL_CNT */ "", 67640 /* PORT_EHG_RXFIFO_OVRFLW */ "", 67641 /* PORT_EHG_RX_CONTROL */ "", 67642 /* PORT_EHG_RX_PKT_DROP */ "", 67643 /* PORT_EHG_TPID */ "", 67644 /* PORT_EHG_TX_CONTROL */ "", 67645 /* PORT_EHG_TX_IPV4ID */ "", 67646 /* PORT_ENABLE_REG */ "", 67647 /* PORT_FAULT_LINK_STATUS */ "", 67648 /* PORT_FC_STATUS */ "", 67649 /* PORT_FLEX_COUNTER_STRENGTH */ "", 67650 /* PORT_FORCE_DOUBLE_BIT_ERROR */ "", 67651 /* PORT_FORCE_SINGLE_BIT_ERROR */ "", 67652 /* PORT_GROUP4_BOD_FIFO_ECC_ENABLE */ "PORT_GROUP4_BOD_FIFO_ECC_ENABLE", 67653 /* PORT_GROUP4_BOD_FIFO_FULL_ERR_STATUS */ "PORT_GROUP4_BOD_FIFO_FULL_ERR_STATUS", 67654 /* PORT_GROUP4_CTRL_FIFO_FULL_ERR_STATUS */ "PORT_GROUP4_CTRL_FIFO_FULL_ERR_STATUS", 67655 /* PORT_GROUP4_ISO_ENABLE */ "PORT_GROUP4_ISO_ENABLE", 67656 /* PORT_GROUP4_TDM_CONTROL */ "PORT_GROUP4_TDM_CONTROL", 67657 /* PORT_GROUP4_TDM_REG_0 */ "PORT_GROUP4_TDM_REG_0", 67658 /* PORT_GROUP4_TDM_REG_1 */ "PORT_GROUP4_TDM_REG_1", 67659 /* PORT_GROUP4_TDM_REG_2 */ "PORT_GROUP4_TDM_REG_2", 67660 /* PORT_GROUP4_TDM_REG_3 */ "PORT_GROUP4_TDM_REG_3", 67661 /* PORT_GROUP4_TDM_REG_4 */ "PORT_GROUP4_TDM_REG_4", 67662 /* PORT_GROUP4_TDM_REG_5 */ "PORT_GROUP4_TDM_REG_5", 67663 /* PORT_GROUP4_TDM_REG_6 */ "PORT_GROUP4_TDM_REG_6", 67664 /* PORT_GROUP4_TDM_REG_7 */ "PORT_GROUP4_TDM_REG_7", 67665 /* PORT_GROUP4_XLP0_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP0_BOD_FIFO_ECC_STATUS_INTR", 67666 /* PORT_GROUP4_XLP0_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP0_CTRL_FIFO_ECC_STATUS_INTR", 67667 /* PORT_GROUP4_XLP1_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP1_BOD_FIFO_ECC_STATUS_INTR", 67668 /* PORT_GROUP4_XLP1_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP1_CTRL_FIFO_ECC_STATUS_INTR", 67669 /* PORT_GROUP4_XLP2_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP2_BOD_FIFO_ECC_STATUS_INTR", 67670 /* PORT_GROUP4_XLP2_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP2_CTRL_FIFO_ECC_STATUS_INTR", 67671 /* PORT_GROUP4_XLP3_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP3_BOD_FIFO_ECC_STATUS_INTR", 67672 /* PORT_GROUP4_XLP3_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP4_XLP3_CTRL_FIFO_ECC_STATUS_INTR", 67673 /* PORT_GROUP4_XLPORT_POWER_DOWN_ENABLE */ "PORT_GROUP4_XLPORT_POWER_DOWN_ENABLE", 67674 /* PORT_GROUP5_BOD_FIFO_ECC_ENABLE */ "PORT_GROUP5_BOD_FIFO_ECC_ENABLE", 67675 /* PORT_GROUP5_BOD_FIFO_FULL_ERR_STATUS */ "PORT_GROUP5_BOD_FIFO_FULL_ERR_STATUS", 67676 /* PORT_GROUP5_CTRL_FIFO_FULL_ERR_STATUS */ "PORT_GROUP5_CTRL_FIFO_FULL_ERR_STATUS", 67677 /* PORT_GROUP5_ISO_ENABLE */ "PORT_GROUP5_ISO_ENABLE", 67678 /* PORT_GROUP5_QGPORT_ENABLE */ "PORT_GROUP5_QGPORT_ENABLE", 67679 /* PORT_GROUP5_TDM_CONTROL */ "PORT_GROUP5_TDM_CONTROL", 67680 /* PORT_GROUP5_TDM_REG_0 */ "PORT_GROUP5_TDM_REG_0", 67681 /* PORT_GROUP5_TDM_REG_1 */ "PORT_GROUP5_TDM_REG_1", 67682 /* PORT_GROUP5_TDM_REG_2 */ "PORT_GROUP5_TDM_REG_2", 67683 /* PORT_GROUP5_TDM_REG_3 */ "PORT_GROUP5_TDM_REG_3", 67684 /* PORT_GROUP5_TDM_REG_4 */ "PORT_GROUP5_TDM_REG_4", 67685 /* PORT_GROUP5_TDM_REG_5 */ "PORT_GROUP5_TDM_REG_5", 67686 /* PORT_GROUP5_TDM_REG_6 */ "PORT_GROUP5_TDM_REG_6", 67687 /* PORT_GROUP5_TDM_REG_7 */ "PORT_GROUP5_TDM_REG_7", 67688 /* PORT_GROUP5_XLP0_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP0_BOD_FIFO_ECC_STATUS_INTR", 67689 /* PORT_GROUP5_XLP0_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP0_CTRL_FIFO_ECC_STATUS_INTR", 67690 /* PORT_GROUP5_XLP1_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP1_BOD_FIFO_ECC_STATUS_INTR", 67691 /* PORT_GROUP5_XLP1_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP1_CTRL_FIFO_ECC_STATUS_INTR", 67692 /* PORT_GROUP5_XLP2_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP2_BOD_FIFO_ECC_STATUS_INTR", 67693 /* PORT_GROUP5_XLP2_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP2_CTRL_FIFO_ECC_STATUS_INTR", 67694 /* PORT_GROUP5_XLP3_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP3_BOD_FIFO_ECC_STATUS_INTR", 67695 /* PORT_GROUP5_XLP3_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP3_CTRL_FIFO_ECC_STATUS_INTR", 67696 /* PORT_GROUP5_XLP4_BOD_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP4_BOD_FIFO_ECC_STATUS_INTR", 67697 /* PORT_GROUP5_XLP4_CTRL_FIFO_ECC_STATUS_INTR */ "PORT_GROUP5_XLP4_CTRL_FIFO_ECC_STATUS_INTR", 67698 /* PORT_GROUP5_XLPORT_POWER_DOWN_ENABLE */ "PORT_GROUP5_XLPORT_POWER_DOWN_ENABLE", 67699 /* PORT_HDRM_COUNT */ "", 67700 /* PORT_HDRM_ENABLE */ "", 67701 /* PORT_INITIAL_COPY_COUNT_WIDTH */ "", 67702 /* PORT_INTR_ENABLE */ "", 67703 /* PORT_INTR_STATUS */ "", 67704 /* PORT_LAG_FAILOVER_SET_PARITY_CONTROL */ "", 67705 /* PORT_LAG_FAILOVER_SET_PARITY_STATUS_INTR */ "", 67706 /* PORT_LAG_FAILOVER_SET_PARITY_STATUS_NACK */ "", 67707 /* PORT_LB_WREDAVGQSIZE_CELL */ "", 67708 /* PORT_LED_CHAIN_CONFIG */ "", 67709 /* PORT_LIMIT_STATES */ "", 67710 /* PORT_LIMIT_STATE_0 */ "", 67711 /* PORT_LIMIT_STATE_1 */ "", 67712 /* PORT_LINKSTATUS_DOWN */ "", 67713 /* PORT_LINKSTATUS_DOWN_CLEAR */ "", 67714 /* PORT_LLFC_CFG */ "", 67715 /* PORT_MAC_CONTROL */ "", 67716 /* PORT_MAX_PKT_SIZE */ "", 67717 /* PORT_MAX_SHARED_CELL */ "", 67718 /* PORT_MIB_RESET */ "", 67719 /* PORT_MIB_RSC0_ECC_STATUS */ "", 67720 /* PORT_MIB_RSC1_ECC_STATUS */ "", 67721 /* PORT_MIB_RSC_0_ECC_STATUS */ "", 67722 /* PORT_MIB_RSC_1_ECC_STATUS */ "", 67723 /* PORT_MIB_TSC0_ECC_STATUS */ "", 67724 /* PORT_MIB_TSC1_ECC_STATUS */ "", 67725 /* PORT_MIB_TSC_0_ECC_STATUS */ "", 67726 /* PORT_MIB_TSC_1_ECC_STATUS */ "", 67727 /* PORT_MIN */ "", 67728 /* PORT_MIN_CELL */ "", 67729 /* PORT_MIN_COUNT */ "", 67730 /* PORT_MIN_COUNT_CELL */ "", 67731 /* PORT_MIN_COUNT_PACKET */ "", 67732 /* PORT_MIN_PACKET */ "", 67733 /* PORT_MIN_PG_ENABLE */ "", 67734 /* PORT_MLD_CTRL_REG */ "", 67735 /* PORT_MODE_REG */ "", 67736 /* PORT_OR_TRUNK_MAC_COUNT_PARITY_CONTROL */ "", 67737 /* PORT_OR_TRUNK_MAC_COUNT_PARITY_STATUS_INTR */ "", 67738 /* PORT_OR_TRUNK_MAC_COUNT_PARITY_STATUS_NACK */ "", 67739 /* PORT_OR_TRUNK_MAC_LIMIT_PARITY_CONTROL */ "", 67740 /* PORT_OR_TRUNK_MAC_LIMIT_PARITY_STATUS_INTR */ "", 67741 /* PORT_OR_TRUNK_MAC_LIMIT_PARITY_STATUS_NACK */ "", 67742 /* PORT_OVQ_PAUSE_ENABLE0 */ "", 67743 /* PORT_OVQ_PAUSE_ENABLE1 */ "", 67744 /* PORT_OVQ_PAUSE_ENABLE_64 */ "PORT_OVQ_PAUSE_ENABLE", 67745 /* PORT_PAUSE_ENABLE */ "", 67746 /* PORT_PAUSE_ENABLE0_64 */ "PORT_PAUSE_ENABLE0", 67747 /* PORT_PAUSE_ENABLE1_64 */ "PORT_PAUSE_ENABLE1", 67748 /* PORT_PAUSE_ENABLE_64 */ "PORT_PAUSE_ENABLE", 67749 /* PORT_PFC_CFG0 */ "", 67750 /* PORT_PFC_CFG1 */ "", 67751 /* PORT_PFC_CFG2 */ "", 67752 /* PORT_PFC_CFG3 */ "", 67753 /* PORT_PG_SPID */ "", 67754 /* PORT_POWER_SAVE */ "", 67755 /* PORT_PRI_GRP */ "", 67756 /* PORT_PRI_GRP0 */ "", 67757 /* PORT_PRI_GRP1 */ "", 67758 /* PORT_PRI_GRP2 */ "", 67759 /* PORT_PRI_XON_ENABLE */ "", 67760 /* PORT_PROFILE_MAP */ "", 67761 /* PORT_QM_MIN */ "", 67762 /* PORT_QM_MIN_CELL */ "", 67763 /* PORT_QM_MIN_COUNT */ "", 67764 /* PORT_QM_MIN_COUNT_CELL */ "", 67765 /* PORT_QM_MIN_COUNT_PACKET */ "", 67766 /* PORT_QM_MIN_PACKET */ "", 67767 /* PORT_QM_SHARED_COUNT */ "", 67768 /* PORT_QM_SHARED_COUNT_CELL */ "", 67769 /* PORT_QM_SHARED_COUNT_PACKET */ "", 67770 /* PORT_RESET_FLOOR */ "", 67771 /* PORT_RESET_OFFSET */ "", 67772 /* PORT_RESET_VALUE */ "", 67773 /* PORT_RESUME_LIMIT_CELL */ "", 67774 /* PORT_SC_MIN */ "", 67775 /* PORT_SC_MIN_CELL */ "", 67776 /* PORT_SC_MIN_COUNT */ "", 67777 /* PORT_SC_MIN_COUNT_CELL */ "", 67778 /* PORT_SC_MIN_COUNT_PACKET */ "", 67779 /* PORT_SC_MIN_PACKET */ "", 67780 /* PORT_SC_SHARED_COUNT */ "", 67781 /* PORT_SC_SHARED_COUNT_CELL */ "", 67782 /* PORT_SC_SHARED_COUNT_PACKET */ "", 67783 /* PORT_SGNDET_EARLYCRS */ "", 67784 /* PORT_SHARED_COUNT */ "", 67785 /* PORT_SHARED_COUNT_CELL */ "", 67786 /* PORT_SHARED_COUNT_PACKET */ "", 67787 /* PORT_SHARED_LIMIT */ "", 67788 /* PORT_SHARED_LIMIT_CELL */ "", 67789 /* PORT_SHARED_LIMIT_PACKET */ "", 67790 /* PORT_SHARED_MAX_PG_ENABLE */ "", 67791 /* PORT_SOFT_RESET */ "", 67792 /* PORT_SPARE0_REG */ "", 67793 /* PORT_SP_WRED_AVG_QSIZE */ "", 67794 /* PORT_SP_WRED_CONFIG */ "", 67795 /* PORT_SW_FLOW_CONTROL */ "", 67796 /* PORT_TABLE_ECC_CONTROL */ "", 67797 /* PORT_TABLE_ECC_STATUS_INTR */ "", 67798 /* PORT_TABLE_ECC_STATUS_NACK */ "", 67799 /* PORT_TABLE_PARITY_STATUS_INTR */ "", 67800 /* PORT_TS_TIMER_31_0_REG */ "", 67801 /* PORT_TS_TIMER_47_32_REG */ "", 67802 /* PORT_TXFIFO0_ECC_STATUS */ "", 67803 /* PORT_TXFIFO1_ECC_STATUS */ "", 67804 /* PORT_TXFIFO2_ECC_STATUS */ "", 67805 /* PORT_TXFIFO_0_ECC_STATUS */ "", 67806 /* PORT_TXFIFO_1_ECC_STATUS */ "", 67807 /* PORT_TXFIFO_2_ECC_STATUS */ "", 67808 /* PORT_TXFIFO_CELL_CNT */ "", 67809 /* PORT_TXFIFO_CELL_REQ_CNT */ "", 67810 /* PORT_TXFIFO_OVRFLW */ "", 67811 /* PORT_TXFIFO_PKT_DROP_CTL */ "", 67812 /* PORT_WC_UCMEM_CTRL */ "", 67813 /* PORT_WREDAVGQSIZE_CELL */ "", 67814 /* PORT_WREDAVGQSIZE_PACKET */ "", 67815 /* PORT_WREDCONFIG_CELL */ "", 67816 /* PORT_WREDCONFIG_ECCP */ "", 67817 /* PORT_WREDCONFIG_PACKET */ "", 67818 /* PORT_WREDPARAM_CELL */ "", 67819 /* PORT_WREDPARAM_END_CELL */ "", 67820 /* PORT_WREDPARAM_NONTCP_CELL */ "", 67821 /* PORT_WREDPARAM_NONTCP_PACKET */ "", 67822 /* PORT_WREDPARAM_PACKET */ "", 67823 /* PORT_WREDPARAM_PRI0_END_CELL */ "", 67824 /* PORT_WREDPARAM_PRI0_START_CELL */ "", 67825 /* PORT_WREDPARAM_RED_CELL */ "", 67826 /* PORT_WREDPARAM_RED_END_CELL */ "", 67827 /* PORT_WREDPARAM_RED_PACKET */ "", 67828 /* PORT_WREDPARAM_RED_START_CELL */ "", 67829 /* PORT_WREDPARAM_START_CELL */ "", 67830 /* PORT_WREDPARAM_YELLOW_CELL */ "", 67831 /* PORT_WREDPARAM_YELLOW_END_CELL */ "", 67832 /* PORT_WREDPARAM_YELLOW_PACKET */ "", 67833 /* PORT_WREDPARAM_YELLOW_START_CELL */ "", 67834 /* PORT_WRED_THD_0_ECCP */ "", 67835 /* PORT_WRED_THD_1_ECCP */ "", 67836 /* PORT_XGXS0_CTRL_REG */ "", 67837 /* PORT_XGXS0_LN0_STATUS0_REG */ "", 67838 /* PORT_XGXS0_LN0_STATUS1_REG */ "", 67839 /* PORT_XGXS0_LN1_STATUS0_REG */ "", 67840 /* PORT_XGXS0_LN1_STATUS1_REG */ "", 67841 /* PORT_XGXS0_LN2_STATUS0_REG */ "", 67842 /* PORT_XGXS0_LN2_STATUS1_REG */ "", 67843 /* PORT_XGXS0_LN3_STATUS0_REG */ "", 67844 /* PORT_XGXS0_LN3_STATUS1_REG */ "", 67845 /* PORT_XGXS0_STATUS_GEN_REG */ "", 67846 /* PORT_XGXS1_CTRL_REG */ "", 67847 /* PORT_XGXS1_LN0_STATUS0_REG */ "", 67848 /* PORT_XGXS1_LN0_STATUS1_REG */ "", 67849 /* PORT_XGXS1_LN1_STATUS0_REG */ "", 67850 /* PORT_XGXS1_LN1_STATUS1_REG */ "", 67851 /* PORT_XGXS1_LN2_STATUS0_REG */ "", 67852 /* PORT_XGXS1_LN2_STATUS1_REG */ "", 67853 /* PORT_XGXS1_LN3_STATUS0_REG */ "", 67854 /* PORT_XGXS1_LN3_STATUS1_REG */ "", 67855 /* PORT_XGXS1_STATUS_GEN_REG */ "", 67856 /* PORT_XGXS2_CTRL_REG */ "", 67857 /* PORT_XGXS2_LN0_STATUS0_REG */ "", 67858 /* PORT_XGXS2_LN0_STATUS1_REG */ "", 67859 /* PORT_XGXS2_LN1_STATUS0_REG */ "", 67860 /* PORT_XGXS2_LN1_STATUS1_REG */ "", 67861 /* PORT_XGXS2_LN2_STATUS0_REG */ "", 67862 /* PORT_XGXS2_LN2_STATUS1_REG */ "", 67863 /* PORT_XGXS2_LN3_STATUS0_REG */ "", 67864 /* PORT_XGXS2_LN3_STATUS1_REG */ "", 67865 /* PORT_XGXS2_STATUS_GEN_REG */ "", 67866 /* PORT_XGXS_0_CTRL_REG */ "", 67867 /* PORT_XGXS_0_LN_0_STATUS_0_REG */ "", 67868 /* PORT_XGXS_0_LN_0_STATUS_1_REG */ "", 67869 /* PORT_XGXS_0_LN_1_STATUS_0_REG */ "", 67870 /* PORT_XGXS_0_LN_1_STATUS_1_REG */ "", 67871 /* PORT_XGXS_0_LN_2_STATUS_0_REG */ "", 67872 /* PORT_XGXS_0_LN_2_STATUS_1_REG */ "", 67873 /* PORT_XGXS_0_LN_3_STATUS_0_REG */ "", 67874 /* PORT_XGXS_0_LN_3_STATUS_1_REG */ "", 67875 /* PORT_XGXS_0_STATUS_GEN_REG */ "", 67876 /* PORT_XGXS_1_CTRL_REG */ "", 67877 /* PORT_XGXS_1_LN_0_STATUS_0_REG */ "", 67878 /* PORT_XGXS_1_LN_0_STATUS_1_REG */ "", 67879 /* PORT_XGXS_1_LN_1_STATUS_0_REG */ "", 67880 /* PORT_XGXS_1_LN_1_STATUS_1_REG */ "", 67881 /* PORT_XGXS_1_LN_2_STATUS_0_REG */ "", 67882 /* PORT_XGXS_1_LN_2_STATUS_1_REG */ "", 67883 /* PORT_XGXS_1_LN_3_STATUS_0_REG */ "", 67884 /* PORT_XGXS_1_LN_3_STATUS_1_REG */ "", 67885 /* PORT_XGXS_1_STATUS_GEN_REG */ "", 67886 /* PORT_XGXS_2_CTRL_REG */ "", 67887 /* PORT_XGXS_2_LN_0_STATUS_0_REG */ "", 67888 /* PORT_XGXS_2_LN_0_STATUS_1_REG */ "", 67889 /* PORT_XGXS_2_LN_1_STATUS_0_REG */ "", 67890 /* PORT_XGXS_2_LN_1_STATUS_1_REG */ "", 67891 /* PORT_XGXS_2_LN_2_STATUS_0_REG */ "", 67892 /* PORT_XGXS_2_LN_2_STATUS_1_REG */ "", 67893 /* PORT_XGXS_2_LN_3_STATUS_0_REG */ "", 67894 /* PORT_XGXS_2_LN_3_STATUS_1_REG */ "", 67895 /* PORT_XGXS_2_STATUS_GEN_REG */ "", 67896 /* PORT_XGXS_COUNTER_MODE */ "", 67897 /* PPDB_A_ECC_1B_ERR_CNT */ "", 67898 /* PPDB_A_ECC_2B_ERR_CNT */ "", 67899 /* PPDB_A_ECC_ERR_1B_INITIATE */ "", 67900 /* PPDB_A_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 67901 /* PPDB_A_ECC_ERR_2B_INITIATE */ "", 67902 /* PPDB_A_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 67903 /* PPDB_A_ECC_INTERRUPT_REGISTER */ "", 67904 /* PPDB_A_ECC_INTERRUPT_REGISTER_MASK */ "", 67905 /* PPDB_A_ECC_INTERRUPT_REGISTER_TEST */ "", 67906 /* PPDB_A_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 67907 /* PPDB_A_ERROR_INITIATION_DATA */ "", 67908 /* PPDB_A_GLOBAL_MEM_OPTIONS */ "", 67909 /* PPDB_A_GTIMER_CONFIGURATION */ "", 67910 /* PPDB_A_GTIMER_TRIGGER */ "", 67911 /* PPDB_A_INDIRECT_COMMAND */ "", 67912 /* PPDB_A_INDIRECT_COMMAND_ADDRESS */ "", 67913 /* PPDB_A_INDIRECT_COMMAND_DATA_INCREMENT */ "", 67914 /* PPDB_A_INDIRECT_COMMAND_RD_DATA */ "", 67915 /* PPDB_A_INDIRECT_COMMAND_WIDE_MEM */ "", 67916 /* PPDB_A_INDIRECT_COMMAND_WR_DATA */ "", 67917 /* PPDB_A_INDIRECT_FORCE_BUBBLE */ "", 67918 /* PPDB_A_INDIRECT_WR_MASK */ "", 67919 /* PPDB_A_INTERRUPT_MASK_REGISTER */ "", 67920 /* PPDB_A_INTERRUPT_REGISTER */ "", 67921 /* PPDB_A_INTERRUPT_REGISTER_TEST */ "", 67922 /* PPDB_A_ISEM_CAM_ENTRIES_COUNTER */ "", 67923 /* PPDB_A_ISEM_DEFRAG_CONFIGURATION_REGISTER */ "", 67924 /* PPDB_A_ISEM_DIAGNOSTICS */ "", 67925 /* PPDB_A_ISEM_DIAGNOSTICS_ACCESSED_MODE */ "", 67926 /* PPDB_A_ISEM_DIAGNOSTICS_INDEX */ "", 67927 /* PPDB_A_ISEM_DIAGNOSTICS_KEY */ "", 67928 /* PPDB_A_ISEM_DIAGNOSTICS_LOOKUP_RESULT */ "", 67929 /* PPDB_A_ISEM_DIAGNOSTICS_READ_RESULT */ "", 67930 /* PPDB_A_ISEM_ENTRIES_COUNTER */ "", 67931 /* PPDB_A_ISEM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 67932 /* PPDB_A_ISEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 67933 /* PPDB_A_ISEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 67934 /* PPDB_A_ISEM_ERROR_TABLE_COHERENCY_COUNTER */ "", 67935 /* PPDB_A_ISEM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 67936 /* PPDB_A_ISEM_INTERRUPT_MASK_REGISTER_ONE */ "", 67937 /* PPDB_A_ISEM_INTERRUPT_REGISTER_ONE */ "", 67938 /* PPDB_A_ISEM_INTERRUPT_REGISTER_ONE_TEST */ "", 67939 /* PPDB_A_ISEM_KEY_TABLE_ENTRY_LIMIT */ "", 67940 /* PPDB_A_ISEM_KILL_RESET_SEQUENCE */ "", 67941 /* PPDB_A_ISEM_LAST_LOOKUP */ "", 67942 /* PPDB_A_ISEM_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 67943 /* PPDB_A_ISEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 67944 /* PPDB_A_ISEM_MANAGEMENT_UNIT_FAILURE */ "", 67945 /* PPDB_A_ISEM_MNGMNT_SER_INDICATION */ "", 67946 /* PPDB_A_ISEM_REQUESTS_COUNTER */ "", 67947 /* PPDB_A_ISEM_RESET_STATUS_REGISTER */ "", 67948 /* PPDB_A_ISEM_SER_DISABLES_MNGMNT */ "", 67949 /* PPDB_A_ISEM_WARNING_INSERTED_EXISTING_COUNTER */ "", 67950 /* PPDB_A_OEMA_CAM_ENTRIES_COUNTER */ "", 67951 /* PPDB_A_OEMA_DEFRAG_CONFIGURATION_REGISTER */ "", 67952 /* PPDB_A_OEMA_DIAGNOSTICS */ "", 67953 /* PPDB_A_OEMA_DIAGNOSTICS_ACCESSED_MODE */ "", 67954 /* PPDB_A_OEMA_DIAGNOSTICS_INDEX */ "", 67955 /* PPDB_A_OEMA_DIAGNOSTICS_KEY */ "", 67956 /* PPDB_A_OEMA_DIAGNOSTICS_LOOKUP_RESULT */ "", 67957 /* PPDB_A_OEMA_DIAGNOSTICS_READ_RESULT */ "", 67958 /* PPDB_A_OEMA_ENTRIES_COUNTER */ "", 67959 /* PPDB_A_OEMA_ERROR_CAM_TABLE_FULL_COUNTER */ "", 67960 /* PPDB_A_OEMA_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 67961 /* PPDB_A_OEMA_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 67962 /* PPDB_A_OEMA_ERROR_TABLE_COHERENCY_COUNTER */ "", 67963 /* PPDB_A_OEMA_GENERAL_EM_CONFIGURATION_REGISTER */ "", 67964 /* PPDB_A_OEMA_INTERRUPT_MASK_REGISTER_ONE */ "", 67965 /* PPDB_A_OEMA_INTERRUPT_REGISTER_ONE */ "", 67966 /* PPDB_A_OEMA_INTERRUPT_REGISTER_ONE_TEST */ "", 67967 /* PPDB_A_OEMA_KEY_TABLE_ENTRY_LIMIT */ "", 67968 /* PPDB_A_OEMA_KILL_RESET_SEQUENCE */ "", 67969 /* PPDB_A_OEMA_LAST_LOOKUP_MASTER */ "", 67970 /* PPDB_A_OEMA_LAST_LOOKUP_SLAVE */ "", 67971 /* PPDB_A_OEMA_LOOKUP_ARBITER_LOOKUP_COUNTER_MASTER */ "", 67972 /* PPDB_A_OEMA_LOOKUP_ARBITER_LOOKUP_COUNTER_SLAVE */ "", 67973 /* PPDB_A_OEMA_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 67974 /* PPDB_A_OEMA_MANAGEMENT_UNIT_FAILURE */ "", 67975 /* PPDB_A_OEMA_MNGMNT_SER_INDICATION */ "", 67976 /* PPDB_A_OEMA_REQUESTS_COUNTER */ "", 67977 /* PPDB_A_OEMA_RESET_STATUS_REGISTER */ "", 67978 /* PPDB_A_OEMA_SER_DISABLES_MNGMNT */ "", 67979 /* PPDB_A_OEMA_WARNING_INSERTED_EXISTING_COUNTER */ "", 67980 /* PPDB_A_OEMB_CAM_ENTRIES_COUNTER */ "", 67981 /* PPDB_A_OEMB_DEFRAG_CONFIGURATION_REGISTER */ "", 67982 /* PPDB_A_OEMB_DIAGNOSTICS */ "", 67983 /* PPDB_A_OEMB_DIAGNOSTICS_ACCESSED_MODE */ "", 67984 /* PPDB_A_OEMB_DIAGNOSTICS_INDEX */ "", 67985 /* PPDB_A_OEMB_DIAGNOSTICS_KEY */ "", 67986 /* PPDB_A_OEMB_DIAGNOSTICS_LOOKUP_RESULT */ "", 67987 /* PPDB_A_OEMB_DIAGNOSTICS_READ_RESULT */ "", 67988 /* PPDB_A_OEMB_ENTRIES_COUNTER */ "", 67989 /* PPDB_A_OEMB_ERROR_CAM_TABLE_FULL_COUNTER */ "", 67990 /* PPDB_A_OEMB_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 67991 /* PPDB_A_OEMB_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 67992 /* PPDB_A_OEMB_ERROR_TABLE_COHERENCY_COUNTER */ "", 67993 /* PPDB_A_OEMB_GENERAL_EM_CONFIGURATION_REGISTER */ "", 67994 /* PPDB_A_OEMB_INTERRUPT_MASK_REGISTER_ONE */ "", 67995 /* PPDB_A_OEMB_INTERRUPT_REGISTER_ONE */ "", 67996 /* PPDB_A_OEMB_INTERRUPT_REGISTER_ONE_TEST */ "", 67997 /* PPDB_A_OEMB_KEY_TABLE_ENTRY_LIMIT */ "", 67998 /* PPDB_A_OEMB_KILL_RESET_SEQUENCE */ "", 67999 /* PPDB_A_OEMB_LAST_LOOKUP_MASTER */ "", 68000 /* PPDB_A_OEMB_LAST_LOOKUP_SLAVE */ "", 68001 /* PPDB_A_OEMB_LOOKUP_ARBITER_LOOKUP_COUNTER_MASTER */ "", 68002 /* PPDB_A_OEMB_LOOKUP_ARBITER_LOOKUP_COUNTER_SLAVE */ "", 68003 /* PPDB_A_OEMB_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 68004 /* PPDB_A_OEMB_MANAGEMENT_UNIT_FAILURE */ "", 68005 /* PPDB_A_OEMB_MNGMNT_SER_INDICATION */ "", 68006 /* PPDB_A_OEMB_REQUESTS_COUNTER */ "", 68007 /* PPDB_A_OEMB_RESET_STATUS_REGISTER */ "", 68008 /* PPDB_A_OEMB_SER_DISABLES_MNGMNT */ "", 68009 /* PPDB_A_OEMB_WARNING_INSERTED_EXISTING_COUNTER */ "", 68010 /* PPDB_A_REG_0100 */ "", 68011 /* PPDB_A_REG_0526 */ "", 68012 /* PPDB_A_REG_0528 */ "", 68013 /* PPDB_A_REG_0529 */ "", 68014 /* PPDB_A_RESERVED_MIRROR_ADDR */ "", 68015 /* PPDB_A_RESERVED_MTCD */ "", 68016 /* PPDB_A_RESERVED_MTCP */ "", 68017 /* PPDB_A_RESERVED_PCMI_0 */ "", 68018 /* PPDB_A_RESERVED_PCMI_1 */ "", 68019 /* PPDB_A_RESERVED_PCMI_2 */ "", 68020 /* PPDB_A_RESERVED_PCMI_3 */ "", 68021 /* PPDB_A_RESERVED_PCMI_4 */ "", 68022 /* PPDB_A_RESERVED_PCMI_0_S */ "", 68023 /* PPDB_A_RESERVED_PCMI_0_T */ "", 68024 /* PPDB_A_RESERVED_PCMI_1_S */ "", 68025 /* PPDB_A_RESERVED_PCMI_1_T */ "", 68026 /* PPDB_A_RESERVED_PCMI_2_S */ "", 68027 /* PPDB_A_RESERVED_PCMI_2_T */ "", 68028 /* PPDB_A_RESERVED_PCMI_3_S */ "", 68029 /* PPDB_A_RESERVED_PCMI_3_T */ "", 68030 /* PPDB_A_RESERVED_PCMI_4_S */ "", 68031 /* PPDB_A_RESERVED_PCMI_4_T */ "", 68032 /* PPDB_A_RESERVED_SPARE_0 */ "", 68033 /* PPDB_A_RESERVED_SPARE_1 */ "", 68034 /* PPDB_A_RESERVED_SPARE_2 */ "", 68035 /* PPDB_A_RESERVED_SPARE_3 */ "", 68036 /* PPDB_A_SBUS_BROADCAST_ID */ "", 68037 /* PPDB_A_SBUS_LAST_IN_CHAIN */ "", 68038 /* PPDB_A_TCAM_ACCESS_COUNTER */ "", 68039 /* PPDB_A_TCAM_ACCESS_COUNTER_SELECTOR */ "", 68040 /* PPDB_A_TCAM_BANK_BLOCK_OWNER */ "", 68041 /* PPDB_A_TCAM_INTERFACE_ACCESS_BITMAP */ "", 68042 /* PPDB_A_TCAM_MANAGER_0 */ "", 68043 /* PPDB_A_TCAM_MANAGER_1 */ "", 68044 /* PPDB_A_TCAM_MATCH_BITMAP */ "", 68045 /* PPDB_A_TCAM_PARITY_MACHINE_CONFIGURATION */ "", 68046 /* PPDB_A_TCAM_PROTECTION_ERROR */ "", 68047 /* PPDB_A_TCAM_QUERY_FAILURE */ "", 68048 /* PPDB_A_TCAM_RESET_BLOCK_BITMAP */ "", 68049 /* PPDB_B_CONSISTENT_HASHING_CONFIGRATION */ "", 68050 /* PPDB_B_ECC_1B_ERR_CNT */ "", 68051 /* PPDB_B_ECC_2B_ERR_CNT */ "", 68052 /* PPDB_B_ECC_ERR_1B_INITIATE */ "", 68053 /* PPDB_B_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 68054 /* PPDB_B_ECC_ERR_2B_INITIATE */ "", 68055 /* PPDB_B_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 68056 /* PPDB_B_ECC_INTERRUPT_REGISTER */ "", 68057 /* PPDB_B_ECC_INTERRUPT_REGISTER_MASK */ "", 68058 /* PPDB_B_ECC_INTERRUPT_REGISTER_TEST */ "", 68059 /* PPDB_B_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 68060 /* PPDB_B_ENABLE_KAPS_CRF */ "", 68061 /* PPDB_B_ERROR_INITIATION_DATA */ "", 68062 /* PPDB_B_GLOBAL_GENERAL_CFG_3 */ "", 68063 /* PPDB_B_GLOBAL_MEM_OPTIONS */ "", 68064 /* PPDB_B_GLOBAL_PP_1 */ "", 68065 /* PPDB_B_GLOBAL_PP_7 */ "", 68066 /* PPDB_B_GLOBAL_SYS_HEADER_CFG */ "", 68067 /* PPDB_B_GTIMER_CONFIGURATION */ "", 68068 /* PPDB_B_GTIMER_TRIGGER */ "", 68069 /* PPDB_B_INDIRECT_COMMAND */ "", 68070 /* PPDB_B_INDIRECT_COMMAND_ADDRESS */ "", 68071 /* PPDB_B_INDIRECT_COMMAND_DATA_INCREMENT */ "", 68072 /* PPDB_B_INDIRECT_COMMAND_RD_DATA */ "", 68073 /* PPDB_B_INDIRECT_COMMAND_WIDE_MEM */ "", 68074 /* PPDB_B_INDIRECT_COMMAND_WR_DATA */ "", 68075 /* PPDB_B_INDIRECT_FORCE_BUBBLE */ "", 68076 /* PPDB_B_INDIRECT_WR_MASK */ "", 68077 /* PPDB_B_INTERRUPT_MASK_REGISTER */ "", 68078 /* PPDB_B_INTERRUPT_REGISTER */ "", 68079 /* PPDB_B_INTERRUPT_REGISTER_TEST */ "", 68080 /* PPDB_B_ISEM_CAM_ENTRIES_COUNTER */ "", 68081 /* PPDB_B_ISEM_DEFRAG_CONFIGURATION_REGISTER */ "", 68082 /* PPDB_B_ISEM_DIAGNOSTICS */ "", 68083 /* PPDB_B_ISEM_DIAGNOSTICS_ACCESSED_MODE */ "", 68084 /* PPDB_B_ISEM_DIAGNOSTICS_INDEX */ "", 68085 /* PPDB_B_ISEM_DIAGNOSTICS_KEY */ "", 68086 /* PPDB_B_ISEM_DIAGNOSTICS_LOOKUP_RESULT */ "", 68087 /* PPDB_B_ISEM_DIAGNOSTICS_READ_RESULT */ "", 68088 /* PPDB_B_ISEM_ENTRIES_COUNTER */ "", 68089 /* PPDB_B_ISEM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 68090 /* PPDB_B_ISEM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 68091 /* PPDB_B_ISEM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 68092 /* PPDB_B_ISEM_ERROR_TABLE_COHERENCY_COUNTER */ "", 68093 /* PPDB_B_ISEM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 68094 /* PPDB_B_ISEM_INTERRUPT_MASK_REGISTER_ONE */ "", 68095 /* PPDB_B_ISEM_INTERRUPT_REGISTER_ONE */ "", 68096 /* PPDB_B_ISEM_INTERRUPT_REGISTER_ONE_TEST */ "", 68097 /* PPDB_B_ISEM_KEY_TABLE_ENTRY_LIMIT */ "", 68098 /* PPDB_B_ISEM_KILL_RESET_SEQUENCE */ "", 68099 /* PPDB_B_ISEM_LAST_LOOKUP */ "", 68100 /* PPDB_B_ISEM_LOOKUP_ARBITER_LOOKUP_COUNTER */ "", 68101 /* PPDB_B_ISEM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 68102 /* PPDB_B_ISEM_MANAGEMENT_UNIT_FAILURE */ "", 68103 /* PPDB_B_ISEM_MNGMNT_SER_INDICATION */ "", 68104 /* PPDB_B_ISEM_REQUESTS_COUNTER */ "", 68105 /* PPDB_B_ISEM_RESET_STATUS_REGISTER */ "", 68106 /* PPDB_B_ISEM_SER_DISABLES_MNGMNT */ "", 68107 /* PPDB_B_ISEM_WARNING_INSERTED_EXISTING_COUNTER */ "", 68108 /* PPDB_B_LARGE_EM_AGE_AGING_MODE */ "", 68109 /* PPDB_B_LARGE_EM_AGE_AGING_RESOLUTION */ "", 68110 /* PPDB_B_LARGE_EM_AGE_MACHINE_CONFIGURATION */ "", 68111 /* PPDB_B_LARGE_EM_AGE_MACHINE_CURRENT_INDEX */ "", 68112 /* PPDB_B_LARGE_EM_AGE_MACHINE_END_INDEX */ "", 68113 /* PPDB_B_LARGE_EM_AGE_MACHINE_META_CYCLE */ "", 68114 /* PPDB_B_LARGE_EM_AGE_MACHINE_START_INDEX */ "", 68115 /* PPDB_B_LARGE_EM_AGE_MACHINE_STATUS */ "", 68116 /* PPDB_B_LARGE_EM_AGE_OWN_SYSTEM_LAG_PORTS */ "", 68117 /* PPDB_B_LARGE_EM_AR_TO_JR_TRANSLATION */ "", 68118 /* PPDB_B_LARGE_EM_AR_TO_JR_TRANSLATION_ERR_REQUEST_COUNTER */ "", 68119 /* PPDB_B_LARGE_EM_CAM_ENTRIES_COUNTER */ "", 68120 /* PPDB_B_LARGE_EM_CMD_TO_CMD_TRANSLATION */ "", 68121 /* PPDB_B_LARGE_EM_COUNTER_DB_CNTR_PTR_CONFIGURATION */ "", 68122 /* PPDB_B_LARGE_EM_COUNTER_DB_LIF_PTR_RANGE_MAP */ "", 68123 /* PPDB_B_LARGE_EM_COUNTER_LIMIT_CONFIGURATION */ "", 68124 /* PPDB_B_LARGE_EM_COUNTER_LIMIT_LARGE_EM_DB_ENTRIES_COUNT */ "", 68125 /* PPDB_B_LARGE_EM_CPU_REQUEST_REQUEST */ "", 68126 /* PPDB_B_LARGE_EM_CPU_REQUEST_TRIGGER */ "", 68127 /* PPDB_B_LARGE_EM_DEFRAG_CONFIGURATION_REGISTER */ "", 68128 /* PPDB_B_LARGE_EM_DIAGNOSTICS */ "", 68129 /* PPDB_B_LARGE_EM_DIAGNOSTICS_ACCESSED_MODE */ "", 68130 /* PPDB_B_LARGE_EM_DIAGNOSTICS_INDEX */ "", 68131 /* PPDB_B_LARGE_EM_DIAGNOSTICS_KEY */ "", 68132 /* PPDB_B_LARGE_EM_DIAGNOSTICS_LOOKUP_RESULT */ "", 68133 /* PPDB_B_LARGE_EM_DIAGNOSTICS_READ_RESULT */ "", 68134 /* PPDB_B_LARGE_EM_EGRESS_OPPORTUNISTIC_FIFO_DROP_COUNTER */ "", 68135 /* PPDB_B_LARGE_EM_ENTRIES_COUNTER */ "", 68136 /* PPDB_B_LARGE_EM_ERROR_CAM_TABLE_FULL_COUNTER */ "", 68137 /* PPDB_B_LARGE_EM_ERROR_CHANGE_FAIL_NON_EXIST_COUNTER */ "", 68138 /* PPDB_B_LARGE_EM_ERROR_CHANGE_REQUEST_OVER_STATIC_COUNTER */ "", 68139 /* PPDB_B_LARGE_EM_ERROR_DELETE_UNKNOWN_KEY_COUNTER */ "", 68140 /* PPDB_B_LARGE_EM_ERROR_LEARN_REQUEST_OVER_STATIC_COUNTER */ "", 68141 /* PPDB_B_LARGE_EM_ERROR_REACHED_MAX_ENTRY_LIMIT_COUNTER */ "", 68142 /* PPDB_B_LARGE_EM_ERROR_TABLE_COHERENCY_COUNTER */ "", 68143 /* PPDB_B_LARGE_EM_EVENT */ "", 68144 /* PPDB_B_LARGE_EM_EVENT_EXCEED_LIMIT_COUNTERS */ "", 68145 /* PPDB_B_LARGE_EM_EVENT_FID_OR_LIF_EXCEED_LIMIT_CNTR_PTR */ "", 68146 /* PPDB_B_LARGE_EM_EVENT_FIFO_CONFIGURATION */ "", 68147 /* PPDB_B_LARGE_EM_EVENT_FIFO_EVENT_COUNTER */ "", 68148 /* PPDB_B_LARGE_EM_EVENT_FIFO_EVENT_DROP_COUNTERS */ "", 68149 /* PPDB_B_LARGE_EM_EVENT_FIFO_EVENT_FIFO_ENTRY_COUNT */ "", 68150 /* PPDB_B_LARGE_EM_EVENT_FIFO_HIGH_THRESHOLD */ "", 68151 /* PPDB_B_LARGE_EM_EVENT_FIFO_WATERMARK */ "", 68152 /* PPDB_B_LARGE_EM_FCNT_RESET_SEQUENCE_CONTROL */ "", 68153 /* PPDB_B_LARGE_EM_FLU_MACHINE_CONFIGURATION */ "", 68154 /* PPDB_B_LARGE_EM_FLU_MACHINE_CURRENT_INDEX */ "", 68155 /* PPDB_B_LARGE_EM_FLU_MACHINE_END_INDEX */ "", 68156 /* PPDB_B_LARGE_EM_FLU_MACHINE_HIT_COUNTER */ "", 68157 /* PPDB_B_LARGE_EM_FLU_MACHINE_STATUS */ "", 68158 /* PPDB_B_LARGE_EM_GENERAL_EM_CONFIGURATION_REGISTER */ "", 68159 /* PPDB_B_LARGE_EM_INGRESS_LEARN_TYPE */ "", 68160 /* PPDB_B_LARGE_EM_INTERRUPT_MASK_REGISTER_ONE */ "", 68161 /* PPDB_B_LARGE_EM_INTERRUPT_MASK_REGISTER_TWO */ "", 68162 /* PPDB_B_LARGE_EM_INTERRUPT_REGISTER_ONE */ "", 68163 /* PPDB_B_LARGE_EM_INTERRUPT_REGISTER_ONE_TEST */ "", 68164 /* PPDB_B_LARGE_EM_INTERRUPT_REGISTER_TWO */ "", 68165 /* PPDB_B_LARGE_EM_JR_TO_AR_TRANSLATION */ "", 68166 /* PPDB_B_LARGE_EM_JR_TO_AR_TRANSLATION_ERR_EVENT_COUNTER */ "", 68167 /* PPDB_B_LARGE_EM_KEY_TABLE_ENTRY_LIMIT */ "", 68168 /* PPDB_B_LARGE_EM_KILL_RESET_SEQUENCE */ "", 68169 /* PPDB_B_LARGE_EM_LEARN_FILTER_PROPERTIES */ "", 68170 /* PPDB_B_LARGE_EM_LEARN_LOOKUP_EGRESS_LOOKUP_COUNTER */ "", 68171 /* PPDB_B_LARGE_EM_LEARN_LOOKUP_GENERAL_CONFIGURATION */ "", 68172 /* PPDB_B_LARGE_EM_LEARN_LOOKUP_INGRESS_LOOKUP_COUNTER */ "", 68173 /* PPDB_B_LARGE_EM_LEARN_NOT_NEEDED_DROP_COUNTER */ "", 68174 /* PPDB_B_LARGE_EM_LEL_ERR_DATA */ "", 68175 /* PPDB_B_LARGE_EM_LOOKUP_ARBITER_CONFIGURATION */ "", 68176 /* PPDB_B_LARGE_EM_LOOKUP_ARBITER_DESTINATION_LOOKUP_COUNTER */ "", 68177 /* PPDB_B_LARGE_EM_LOOKUP_ARBITER_LEARN_LOOKUP_COUNTER */ "", 68178 /* PPDB_B_LARGE_EM_LOOKUP_ARBITER_SOURCE_LOOKUP_COUNTER */ "", 68179 /* PPDB_B_LARGE_EM_LOOKUP_BURST_FIFO_PROPERTIES */ "", 68180 /* PPDB_B_LARGE_EM_LOOKUP_FILTER_PROPERTIES */ "", 68181 /* PPDB_B_LARGE_EM_LOOKUP_LOOKUP_MODE */ "", 68182 /* PPDB_B_LARGE_EM_MANAGEMENT_UNIT_CONFIGURATION_REGISTER */ "", 68183 /* PPDB_B_LARGE_EM_MANAGEMENT_UNIT_FAILURE */ "", 68184 /* PPDB_B_LARGE_EM_MASTER_EGRESS_OPPORTUNISTIC_FIFO_DROP_COUNTER */ "", 68185 /* PPDB_B_LARGE_EM_MASTER_EVENT */ "", 68186 /* PPDB_B_LARGE_EM_MASTER_EVENT_FID_OR_LIF_EXCEED_LIMIT_CNTR_PTR */ "", 68187 /* PPDB_B_LARGE_EM_MASTER_EVENT_FIFO_EVENT_COUNTER */ "", 68188 /* PPDB_B_LARGE_EM_MASTER_EVENT_FIFO_EVENT_FIFO_ENTRY_COUNT */ "", 68189 /* PPDB_B_LARGE_EM_MASTER_EVENT_FIFO_WATERMARK */ "", 68190 /* PPDB_B_LARGE_EM_MASTER_JR_TO_AR_TRANSLATION_ERR_EVENT_COUNTER */ "", 68191 /* PPDB_B_LARGE_EM_MASTER_LEARN_LOOKUP_EGRESS_LOOKUP_COUNTER */ "", 68192 /* PPDB_B_LARGE_EM_MASTER_LEARN_LOOKUP_INGRESS_LOOKUP_COUNTER */ "", 68193 /* PPDB_B_LARGE_EM_MASTER_LEARN_NOT_NEEDED_DROP_COUNTER */ "", 68194 /* PPDB_B_LARGE_EM_MASTER_LEL_ERR_DATA */ "", 68195 /* PPDB_B_LARGE_EM_MASTER_LOOKUP_ARBITER_DESTINATION_LOOKUP_COUNTER */ "", 68196 /* PPDB_B_LARGE_EM_MASTER_LOOKUP_ARBITER_LEARN_LOOKUP_COUNTER */ "", 68197 /* PPDB_B_LARGE_EM_MASTER_LOOKUP_ARBITER_SOURCE_LOOKUP_COUNTER */ "", 68198 /* PPDB_B_LARGE_EM_MASTER_LOOKUP_BURST_FIFO_PROPERTIES */ "", 68199 /* PPDB_B_LARGE_EM_MNGMNT_REQ_CONFIGURATION */ "", 68200 /* PPDB_B_LARGE_EM_MNGMNT_REQ_COUNTERS_A */ "", 68201 /* PPDB_B_LARGE_EM_MNGMNT_REQ_COUNTERS_B */ "", 68202 /* PPDB_B_LARGE_EM_MNGMNT_REQ_COUNTERS_C */ "", 68203 /* PPDB_B_LARGE_EM_MNGMNT_REQ_EXCEED_LIMIT_CPU_ALLOWED_FID */ "", 68204 /* PPDB_B_LARGE_EM_MNGMNT_REQ_EXCEED_LIMIT_FID */ "", 68205 /* PPDB_B_LARGE_EM_MNGMNT_REQ_EXCEED_LIMIT_STATIC_ALLOWED_FID */ "", 68206 /* PPDB_B_LARGE_EM_MNGMNT_REQ_FLU_DB_CONFIGURATION */ "", 68207 /* PPDB_B_LARGE_EM_MNGMNT_REQ_REQUEST_COUNTER */ "", 68208 /* PPDB_B_LARGE_EM_MNGMNT_REQ_REQUEST_FIFO_ENTRY_COUNT */ "", 68209 /* PPDB_B_LARGE_EM_MNGMNT_REQ_REQUEST_FIFO_WATERMARK */ "", 68210 /* PPDB_B_LARGE_EM_MNGMNT_SER_INDICATION */ "", 68211 /* PPDB_B_LARGE_EM_OLP_REQUEST_REQUEST */ "", 68212 /* PPDB_B_LARGE_EM_OLP_REQUEST_TRIGGER */ "", 68213 /* PPDB_B_LARGE_EM_REPLY */ "", 68214 /* PPDB_B_LARGE_EM_REPLY_FIFO_CONFIGURATION */ "", 68215 /* PPDB_B_LARGE_EM_REPLY_FIFO_HIGH_THRESHOLD */ "", 68216 /* PPDB_B_LARGE_EM_REPLY_FIFO_REPLY_COUNTER */ "", 68217 /* PPDB_B_LARGE_EM_REPLY_FIFO_REPLY_DROP_COUNTERS */ "", 68218 /* PPDB_B_LARGE_EM_REPLY_FIFO_REPLY_FIFO_ENTRY_COUNT */ "", 68219 /* PPDB_B_LARGE_EM_REPLY_FIFO_WATERMARK */ "", 68220 /* PPDB_B_LARGE_EM_REQUESTS_COUNTER */ "", 68221 /* PPDB_B_LARGE_EM_RESET_STATUS_REGISTER */ "", 68222 /* PPDB_B_LARGE_EM_SER_DISABLES_MNGMNT */ "", 68223 /* PPDB_B_LARGE_EM_SLAVE_EGRESS_OPPORTUNISTIC_FIFO_DROP_COUNTER */ "", 68224 /* PPDB_B_LARGE_EM_SLAVE_EVENT */ "", 68225 /* PPDB_B_LARGE_EM_SLAVE_EVENT_FID_OR_LIF_EXCEED_LIMIT_CNTR_PTR */ "", 68226 /* PPDB_B_LARGE_EM_SLAVE_EVENT_FIFO_EVENT_COUNTER */ "", 68227 /* PPDB_B_LARGE_EM_SLAVE_EVENT_FIFO_EVENT_FIFO_ENTRY_COUNT */ "", 68228 /* PPDB_B_LARGE_EM_SLAVE_EVENT_FIFO_WATERMARK */ "", 68229 /* PPDB_B_LARGE_EM_SLAVE_JR_TO_AR_TRANSLATION_ERR_EVENT_COUNTER */ "", 68230 /* PPDB_B_LARGE_EM_SLAVE_LEARN_LOOKUP_EGRESS_LOOKUP_COUNTER */ "", 68231 /* PPDB_B_LARGE_EM_SLAVE_LEARN_LOOKUP_INGRESS_LOOKUP_COUNTER */ "", 68232 /* PPDB_B_LARGE_EM_SLAVE_LEARN_NOT_NEEDED_DROP_COUNTER */ "", 68233 /* PPDB_B_LARGE_EM_SLAVE_LEL_ERR_DATA */ "", 68234 /* PPDB_B_LARGE_EM_SLAVE_LOOKUP_ARBITER_DESTINATION_LOOKUP_COUNTER */ "", 68235 /* PPDB_B_LARGE_EM_SLAVE_LOOKUP_ARBITER_LEARN_LOOKUP_COUNTER */ "", 68236 /* PPDB_B_LARGE_EM_SLAVE_LOOKUP_ARBITER_SOURCE_LOOKUP_COUNTER */ "", 68237 /* PPDB_B_LARGE_EM_SLAVE_LOOKUP_BURST_FIFO_PROPERTIES */ "", 68238 /* PPDB_B_LARGE_EM_TRANSLATION_ERR */ "", 68239 /* PPDB_B_LARGE_EM_WARNING_CHANGE_NON_EXIST_FROM_OTHER_COUNTER */ "", 68240 /* PPDB_B_LARGE_EM_WARNING_CHANGE_NON_EXIST_FROM_SELF_COUNTER */ "", 68241 /* PPDB_B_LARGE_EM_WARNING_INSERTED_EXISTING_COUNTER */ "", 68242 /* PPDB_B_LARGE_EM_WARNING_LEARN_OVER_EXISTING_COUNTER */ "", 68243 /* PPDB_B_MACT_DISABLE_FEC_PREFIX */ "", 68244 /* PPDB_B_MACT_INTERRUPT_REGISTER_ONE_TEST */ "", 68245 /* PPDB_B_MACT_INTERRUPT_REGISTER_TWO_TEST */ "", 68246 /* PPDB_B_PCMI_0 */ "", 68247 /* PPDB_B_PCMI_1 */ "", 68248 /* PPDB_B_PCMI_2 */ "", 68249 /* PPDB_B_PCMI_3 */ "", 68250 /* PPDB_B_PCMI_4 */ "", 68251 /* PPDB_B_PCMI_0_S */ "", 68252 /* PPDB_B_PCMI_0_T */ "", 68253 /* PPDB_B_PCMI_1_S */ "", 68254 /* PPDB_B_PCMI_1_T */ "", 68255 /* PPDB_B_PCMI_2_S */ "", 68256 /* PPDB_B_PCMI_2_T */ "", 68257 /* PPDB_B_PCMI_3_S */ "", 68258 /* PPDB_B_PCMI_3_T */ "", 68259 /* PPDB_B_PCMI_4_S */ "", 68260 /* PPDB_B_PCMI_4_T */ "", 68261 /* PPDB_B_REG_0100 */ "", 68262 /* PPDB_B_RESERVED_MIRROR_ADDR */ "", 68263 /* PPDB_B_RESERVED_MTCD */ "", 68264 /* PPDB_B_RESERVED_MTCP */ "", 68265 /* PPDB_B_RESERVED_PCMI_0 */ "", 68266 /* PPDB_B_RESERVED_PCMI_1 */ "", 68267 /* PPDB_B_RESERVED_PCMI_2 */ "", 68268 /* PPDB_B_RESERVED_PCMI_3 */ "", 68269 /* PPDB_B_RESERVED_PCMI_4 */ "", 68270 /* PPDB_B_RESERVED_PCMI_0_S */ "", 68271 /* PPDB_B_RESERVED_PCMI_0_T */ "", 68272 /* PPDB_B_RESERVED_PCMI_1_S */ "", 68273 /* PPDB_B_RESERVED_PCMI_1_T */ "", 68274 /* PPDB_B_RESERVED_PCMI_2_S */ "", 68275 /* PPDB_B_RESERVED_PCMI_2_T */ "", 68276 /* PPDB_B_RESERVED_PCMI_3_S */ "", 68277 /* PPDB_B_RESERVED_PCMI_3_T */ "", 68278 /* PPDB_B_RESERVED_PCMI_4_S */ "", 68279 /* PPDB_B_RESERVED_PCMI_4_T */ "", 68280 /* PPDB_B_RESERVED_SPARE_0 */ "", 68281 /* PPDB_B_RESERVED_SPARE_1 */ "", 68282 /* PPDB_B_RESERVED_SPARE_2 */ "", 68283 /* PPDB_B_RESERVED_SPARE_3 */ "", 68284 /* PPDB_B_SBUS_BROADCAST_ID */ "", 68285 /* PPDB_B_SBUS_LAST_IN_CHAIN */ "", 68286 /* PPE_CREDIT_CONFIG */ "", 68287 /* PPE_CREDIT_CONFIG_PIPE0 */ "", 68288 /* PPE_CREDIT_CONFIG_PIPE1 */ "", 68289 /* PPE_CREDIT_CONFIG_PIPE2 */ "", 68290 /* PPE_CREDIT_CONFIG_PIPE3 */ "", 68291 /* PPE_CREDIT_COUNTER */ "", 68292 /* PPE_CREDIT_COUNTER_PIPE0 */ "", 68293 /* PPE_CREDIT_COUNTER_PIPE1 */ "", 68294 /* PPE_CREDIT_COUNTER_PIPE2 */ "", 68295 /* PPE_CREDIT_COUNTER_PIPE3 */ "", 68296 /* PPFC_EN */ "", 68297 /* PPFC_TX_PKT_XOFF_TIMER_0_1_VAL */ "", 68298 /* PPFC_TX_PKT_XOFF_TIMER_2_3_VAL */ "", 68299 /* PPFC_TX_PKT_XOFF_TIMER_4_5_VAL */ "", 68300 /* PPFC_TX_PKT_XOFF_TIMER_6_7_VAL */ "", 68301 /* PPPEMPTYSTATUS */ "", 68302 /* PPPEMPTYSTATUS_0 */ "", 68303 /* PPPEMPTYSTATUS_1 */ "", 68304 /* PPPEMPTYSTATUS_2 */ "", 68305 /* PPP_CTRL */ "", 68306 /* PPP_REFRESH_CTRL */ "", 68307 /* PP_C0_PORT_A_ADDR */ "", 68308 /* PP_C0_PORT_A_CMD */ "", 68309 /* PP_C0_PORT_A_DATA_0 */ "", 68310 /* PP_C0_PORT_A_DATA_1 */ "", 68311 /* PP_C0_PORT_A_DATA_2 */ "", 68312 /* PP_C0_PORT_A_DATA_3 */ "", 68313 /* PP_C0_PORT_B_ADDR */ "", 68314 /* PP_C0_PORT_B_CMD */ "", 68315 /* PP_C0_PORT_B_DATA_0 */ "", 68316 /* PP_C0_PORT_B_DATA_1 */ "", 68317 /* PP_C0_PORT_B_DATA_2 */ "", 68318 /* PP_C0_PORT_B_DATA_3 */ "", 68319 /* PP_C1_PORT_A_ADDR */ "", 68320 /* PP_C1_PORT_A_CMD */ "", 68321 /* PP_C1_PORT_A_DATA_0 */ "", 68322 /* PP_C1_PORT_A_DATA_1 */ "", 68323 /* PP_C1_PORT_A_DATA_2 */ "", 68324 /* PP_C1_PORT_A_DATA_3 */ "", 68325 /* PP_C1_PORT_B_ADDR */ "", 68326 /* PP_C1_PORT_B_CMD */ "", 68327 /* PP_C1_PORT_B_DATA_0 */ "", 68328 /* PP_C1_PORT_B_DATA_1 */ "", 68329 /* PP_C1_PORT_B_DATA_2 */ "", 68330 /* PP_C1_PORT_B_DATA_3 */ "", 68331 /* PP_C2_PORT_A_ADDR */ "", 68332 /* PP_C2_PORT_A_CMD */ "", 68333 /* PP_C2_PORT_A_DATA_0 */ "", 68334 /* PP_C2_PORT_A_DATA_1 */ "", 68335 /* PP_C2_PORT_A_DATA_2 */ "", 68336 /* PP_C2_PORT_A_DATA_3 */ "", 68337 /* PP_C2_PORT_B_ADDR */ "", 68338 /* PP_C2_PORT_B_CMD */ "", 68339 /* PP_C2_PORT_B_DATA_0 */ "", 68340 /* PP_C2_PORT_B_DATA_1 */ "", 68341 /* PP_C2_PORT_B_DATA_2 */ "", 68342 /* PP_C2_PORT_B_DATA_3 */ "", 68343 /* PP_C3_PORT_A_ADDR */ "", 68344 /* PP_C3_PORT_A_CMD */ "", 68345 /* PP_C3_PORT_A_DATA_0 */ "", 68346 /* PP_C3_PORT_A_DATA_1 */ "", 68347 /* PP_C3_PORT_A_DATA_2 */ "", 68348 /* PP_C3_PORT_A_DATA_3 */ "", 68349 /* PP_C3_PORT_B_ADDR */ "", 68350 /* PP_C3_PORT_B_CMD */ "", 68351 /* PP_C3_PORT_B_DATA_0 */ "", 68352 /* PP_C3_PORT_B_DATA_1 */ "", 68353 /* PP_C3_PORT_B_DATA_2 */ "", 68354 /* PP_C3_PORT_B_DATA_3 */ "", 68355 /* PP_MODULE_CONTROL */ "", 68356 /* PP_PROGRAM_GO */ "", 68357 /* PQE0_FIFOEMPTY0 */ "", 68358 /* PQE0_FIFOEMPTY1 */ "", 68359 /* PQE0_FIFOEMPTY_SPLIT0 */ "", 68360 /* PQE0_FIFOEMPTY_SPLIT1 */ "", 68361 /* PQE0_FIFOEMPTY_SPLIT2 */ "", 68362 /* PQE0_FIFOOVERFLOW0 */ "", 68363 /* PQE0_FIFOOVERFLOW1 */ "", 68364 /* PQE0_FIFOOVERFLOW_SPLIT0 */ "", 68365 /* PQE0_FIFOOVERFLOW_SPLIT1 */ "", 68366 /* PQE0_FIFOOVERFLOW_SPLIT2 */ "", 68367 /* PQE0_FIFOPTREQUAL0 */ "", 68368 /* PQE0_FIFOPTREQUAL1 */ "", 68369 /* PQE0_FIFOPTREQUAL_SPLIT0 */ "", 68370 /* PQE0_FIFOPTREQUAL_SPLIT1 */ "", 68371 /* PQE0_FIFOPTREQUAL_SPLIT2 */ "", 68372 /* PQE0_MEMCFG */ "", 68373 /* PQE0_MEMDEBUG */ "", 68374 /* PQE0_QCNEMPTY0 */ "", 68375 /* PQE0_QCNEMPTY1 */ "", 68376 /* PQE1_FIFOEMPTY0 */ "", 68377 /* PQE1_FIFOEMPTY1 */ "", 68378 /* PQE1_FIFOEMPTY_SPLIT0 */ "", 68379 /* PQE1_FIFOEMPTY_SPLIT1 */ "", 68380 /* PQE1_FIFOEMPTY_SPLIT2 */ "", 68381 /* PQE1_FIFOOVERFLOW0 */ "", 68382 /* PQE1_FIFOOVERFLOW1 */ "", 68383 /* PQE1_FIFOOVERFLOW_SPLIT0 */ "", 68384 /* PQE1_FIFOOVERFLOW_SPLIT1 */ "", 68385 /* PQE1_FIFOOVERFLOW_SPLIT2 */ "", 68386 /* PQE1_FIFOPTREQUAL0 */ "", 68387 /* PQE1_FIFOPTREQUAL1 */ "", 68388 /* PQE1_FIFOPTREQUAL_SPLIT0 */ "", 68389 /* PQE1_FIFOPTREQUAL_SPLIT1 */ "", 68390 /* PQE1_FIFOPTREQUAL_SPLIT2 */ "", 68391 /* PQE1_MEMCFG */ "", 68392 /* PQE1_MEMDEBUG */ "", 68393 /* PQE1_QCNEMPTY0 */ "", 68394 /* PQE1_QCNEMPTY1 */ "", 68395 /* PQEFIFOEMPTY0 */ "", 68396 /* PQEFIFOEMPTY1 */ "", 68397 /* PQEFIFOEMPTY0_64 */ "PQEFIFOEMPTY0", 68398 /* PQEFIFOEMPTY1_64 */ "PQEFIFOEMPTY1", 68399 /* PQEFIFOEMPTY_64 */ "PQEFIFOEMPTY", 68400 /* PQEFIFOOVERFLOW0 */ "", 68401 /* PQEFIFOOVERFLOW1 */ "", 68402 /* PQEFIFOOVERFLOW0_64 */ "PQEFIFOOVERFLOW0", 68403 /* PQEFIFOOVERFLOW1_64 */ "PQEFIFOOVERFLOW1", 68404 /* PQEFIFOOVERFLOW_64 */ "PQEFIFOOVERFLOW", 68405 /* PQEFIFOPTREQUAL0 */ "", 68406 /* PQEFIFOPTREQUAL1 */ "", 68407 /* PQEFIFOPTREQUAL0_64 */ "PQEFIFOPTREQUAL0", 68408 /* PQEFIFOPTREQUAL1_64 */ "PQEFIFOPTREQUAL1", 68409 /* PQEFIFOPTREQUAL_64 */ "PQEFIFOPTREQUAL", 68410 /* PQEMEMCFG */ "", 68411 /* PQEMEMDEBUG */ "", 68412 /* PQEPARITYERRORADR */ "", 68413 /* PQP_CAPTURE_ALL_PACKETS */ "", 68414 /* PQP_DELETE_FBC_FIFO_IRDY_STATUS */ "", 68415 /* PQP_DELETE_FIFO_CONFIGURATION */ "", 68416 /* PQP_DELETE_FIFO_STATUS */ "", 68417 /* PQP_DELETE_FIFO_WATERMARK */ "", 68418 /* PQP_DEQ_COUNTERS_CONFIG */ "", 68419 /* PQP_EBTR_ILLEGAL_TH */ "", 68420 /* PQP_ECC_1B_ERR_CNT */ "", 68421 /* PQP_ECC_2B_ERR_CNT */ "", 68422 /* PQP_ECC_ERR_1B_INITIATE */ "", 68423 /* PQP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 68424 /* PQP_ECC_ERR_2B_INITIATE */ "", 68425 /* PQP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 68426 /* PQP_ECC_INTERRUPT_REGISTER */ "", 68427 /* PQP_ECC_INTERRUPT_REGISTER_MASK */ "", 68428 /* PQP_ECC_INTERRUPT_REGISTER_TEST */ "", 68429 /* PQP_EGQ_BLOCK_INIT_STATUS */ "", 68430 /* PQP_EGRESS_QUEUES_EMPTY */ "", 68431 /* PQP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 68432 /* PQP_ENQ_COUNTERS_CONFIG */ "", 68433 /* PQP_ERROR_INITIATION_DATA */ "", 68434 /* PQP_FDC_LEVEL */ "", 68435 /* PQP_GTIMER_CONFIGURATION */ "", 68436 /* PQP_GTIMER_CYCLE */ "", 68437 /* PQP_INDIRECT_COMMAND */ "", 68438 /* PQP_INDIRECT_COMMAND_ADDRESS */ "", 68439 /* PQP_INDIRECT_COMMAND_RD_DATA */ "", 68440 /* PQP_INDIRECT_COMMAND_WR_DATA */ "", 68441 /* PQP_INDIRECT_FORCE_BUBBLE */ "", 68442 /* PQP_INTERRUPT_MASK_REGISTER */ "", 68443 /* PQP_INTERRUPT_REGISTER */ "", 68444 /* PQP_INTERRUPT_REGISTER_TEST */ "", 68445 /* PQP_INVALID_OTM */ "", 68446 /* PQP_LCD_FBC_FIFO_IRDY_STATUS */ "", 68447 /* PQP_LCD_FIFO_CONFIGURATION */ "", 68448 /* PQP_LCD_FIFO_STATUS */ "", 68449 /* PQP_PACKET_SIZES_BINS_COUNTER */ "", 68450 /* PQP_PACKET_SIZE_BINNING_CONFIGURATION */ "", 68451 /* PQP_PACKET_SIZE_BINNING_RANGE */ "", 68452 /* PQP_PD_SP_MAPPING */ "", 68453 /* PQP_PER_TXQ_MAX_BURST_FIX_ENABLE */ "", 68454 /* PQP_PQP_DISCARD_MULTICAST_PACKET_COUNTER */ "", 68455 /* PQP_PQP_DISCARD_UNICAST_PACKET_COUNTER */ "", 68456 /* PQP_PQP_ENQ_BYTES_COUNTER */ "", 68457 /* PQP_PQP_ENQ_PACKET_COUNTER */ "", 68458 /* PQP_PQP_LCD_MULTICAST_PACKET_COUNTER */ "", 68459 /* PQP_PQP_MULTICAST_BYTES_COUNTER */ "", 68460 /* PQP_PQP_MULTICAST_PACKET_COUNTER */ "", 68461 /* PQP_PQP_UNICAST_BYTES_COUNTER */ "", 68462 /* PQP_PQP_UNICAST_PACKET_COUNTER */ "", 68463 /* PQP_QPAIR_ALMOST_EMPTY_FORCE */ "", 68464 /* PQP_REG_0041 */ "", 68465 /* PQP_REG_0098 */ "", 68466 /* PQP_REG_0108 */ "", 68467 /* PQP_REG_00A0 */ "", 68468 /* PQP_REG_00AA */ "", 68469 /* PQP_REG_00C2 */ "", 68470 /* PQP_REG_00C5 */ "", 68471 /* PQP_RESERVED_MIRROR_ADDR */ "", 68472 /* PQP_RESERVED_MTCD */ "", 68473 /* PQP_RESERVED_MTCP */ "", 68474 /* PQP_RESERVED_SPARE_0 */ "", 68475 /* PQP_RESERVED_SPARE_1 */ "", 68476 /* PQP_RESERVED_SPARE_2 */ "", 68477 /* PQP_RESERVED_SPARE_3 */ "", 68478 /* PQP_SBUS_BROADCAST_ID */ "", 68479 /* PQP_SBUS_LAST_IN_CHAIN */ "", 68480 /* PQP_SPECIAL_CLOCK_CONTROLS */ "", 68481 /* PQP_TXQ_MAX_BURST_THRESHOLD */ "", 68482 /* PQP_VISIBILITY_PACKET_COUNTER */ "", 68483 /* PQP_VISIBILITY_PACKET_DEBUG */ "", 68484 /* PQ_C0_PORT_A_CMD */ "", 68485 /* PQ_C0_PORT_A_DATA_0 */ "", 68486 /* PQ_C0_PORT_A_DATA_1 */ "", 68487 /* PQ_C0_PORT_A_DATA_2 */ "", 68488 /* PQ_C0_PORT_A_DATA_3 */ "", 68489 /* PQ_C0_PORT_A_RADDR */ "", 68490 /* PQ_C0_PORT_A_WADDR */ "", 68491 /* PQ_C0_PORT_B_CMD */ "", 68492 /* PQ_C0_PORT_B_DATA_0 */ "", 68493 /* PQ_C0_PORT_B_DATA_1 */ "", 68494 /* PQ_C0_PORT_B_DATA_2 */ "", 68495 /* PQ_C0_PORT_B_DATA_3 */ "", 68496 /* PQ_C0_PORT_B_RADDR */ "", 68497 /* PQ_C0_PORT_B_WADDR */ "", 68498 /* PQ_C1_PORT_A_CMD */ "", 68499 /* PQ_C1_PORT_A_DATA_0 */ "", 68500 /* PQ_C1_PORT_A_DATA_1 */ "", 68501 /* PQ_C1_PORT_A_DATA_2 */ "", 68502 /* PQ_C1_PORT_A_DATA_3 */ "", 68503 /* PQ_C1_PORT_A_RADDR */ "", 68504 /* PQ_C1_PORT_A_WADDR */ "", 68505 /* PQ_C1_PORT_B_CMD */ "", 68506 /* PQ_C1_PORT_B_DATA_0 */ "", 68507 /* PQ_C1_PORT_B_DATA_1 */ "", 68508 /* PQ_C1_PORT_B_DATA_2 */ "", 68509 /* PQ_C1_PORT_B_DATA_3 */ "", 68510 /* PQ_C1_PORT_B_RADDR */ "", 68511 /* PQ_C1_PORT_B_WADDR */ "", 68512 /* PQ_C2_PORT_A_CMD */ "", 68513 /* PQ_C2_PORT_A_DATA_0 */ "", 68514 /* PQ_C2_PORT_A_DATA_1 */ "", 68515 /* PQ_C2_PORT_A_DATA_2 */ "", 68516 /* PQ_C2_PORT_A_DATA_3 */ "", 68517 /* PQ_C2_PORT_A_RADDR */ "", 68518 /* PQ_C2_PORT_A_WADDR */ "", 68519 /* PQ_C2_PORT_B_CMD */ "", 68520 /* PQ_C2_PORT_B_DATA_0 */ "", 68521 /* PQ_C2_PORT_B_DATA_1 */ "", 68522 /* PQ_C2_PORT_B_DATA_2 */ "", 68523 /* PQ_C2_PORT_B_DATA_3 */ "", 68524 /* PQ_C2_PORT_B_RADDR */ "", 68525 /* PQ_C2_PORT_B_WADDR */ "", 68526 /* PQ_C3_PORT_A_CMD */ "", 68527 /* PQ_C3_PORT_A_DATA_0 */ "", 68528 /* PQ_C3_PORT_A_DATA_1 */ "", 68529 /* PQ_C3_PORT_A_DATA_2 */ "", 68530 /* PQ_C3_PORT_A_DATA_3 */ "", 68531 /* PQ_C3_PORT_A_RADDR */ "", 68532 /* PQ_C3_PORT_A_WADDR */ "", 68533 /* PQ_C3_PORT_B_CMD */ "", 68534 /* PQ_C3_PORT_B_DATA_0 */ "", 68535 /* PQ_C3_PORT_B_DATA_1 */ "", 68536 /* PQ_C3_PORT_B_DATA_2 */ "", 68537 /* PQ_C3_PORT_B_DATA_3 */ "", 68538 /* PQ_C3_PORT_B_RADDR */ "", 68539 /* PQ_C3_PORT_B_WADDR */ "", 68540 /* PQ_MODULE_CONTROL */ "", 68541 /* PQ_PROGRAM_GO */ "", 68542 /* PRBPAT */ "", 68543 /* PRCNTSEL */ "", 68544 /* PRI2COS */ "", 68545 /* PRI2COS_2 */ "", 68546 /* PRI2COS_PFC */ "", 68547 /* PRIO2COS */ "", 68548 /* PRIO2COS_0_PRI0 */ "", 68549 /* PRIO2COS_0_PRI1 */ "", 68550 /* PRIO2COS_0_PRI2 */ "", 68551 /* PRIO2COS_0_PRI3 */ "", 68552 /* PRIO2COS_0_PRI4 */ "", 68553 /* PRIO2COS_0_PRI5 */ "", 68554 /* PRIO2COS_0_PRI6 */ "", 68555 /* PRIO2COS_0_PRI7 */ "", 68556 /* PRIO2COS_0_PRI8 */ "", 68557 /* PRIO2COS_0_PRI9 */ "", 68558 /* PRIO2COS_0_PRI10 */ "", 68559 /* PRIO2COS_0_PRI11 */ "", 68560 /* PRIO2COS_0_PRI12 */ "", 68561 /* PRIO2COS_0_PRI13 */ "", 68562 /* PRIO2COS_0_PRI14 */ "", 68563 /* PRIO2COS_0_PRI15 */ "", 68564 /* PRIO2COS_1_PRI0 */ "", 68565 /* PRIO2COS_1_PRI1 */ "", 68566 /* PRIO2COS_1_PRI2 */ "", 68567 /* PRIO2COS_1_PRI3 */ "", 68568 /* PRIO2COS_1_PRI4 */ "", 68569 /* PRIO2COS_1_PRI5 */ "", 68570 /* PRIO2COS_1_PRI6 */ "", 68571 /* PRIO2COS_1_PRI7 */ "", 68572 /* PRIO2COS_1_PRI8 */ "", 68573 /* PRIO2COS_1_PRI9 */ "", 68574 /* PRIO2COS_1_PRI10 */ "", 68575 /* PRIO2COS_1_PRI11 */ "", 68576 /* PRIO2COS_1_PRI12 */ "", 68577 /* PRIO2COS_1_PRI13 */ "", 68578 /* PRIO2COS_1_PRI14 */ "", 68579 /* PRIO2COS_1_PRI15 */ "", 68580 /* PRIO2COS_CBFC */ "", 68581 /* PRIO2COS_LLFC */ "", 68582 /* PRIO2COS_LLFC0 */ "", 68583 /* PRIO2COS_LLFC1 */ "", 68584 /* PRIO2COS_LLFC2 */ "", 68585 /* PRIO2COS_LLFC3 */ "", 68586 /* PRIO2COS_PROFILE */ "", 68587 /* PRIO2COS_PROFILE0 */ "", 68588 /* PRIO2COS_PROFILE1 */ "", 68589 /* PRIO2COS_PROFILE2 */ "", 68590 /* PRIO2COS_PROFILE3 */ "", 68591 /* PRIO2COS_PROFILE_64 */ "PRIO2COS_PROFILE", 68592 /* PRIO2EXTQ_LLFC */ "", 68593 /* PRIO2EXTQ_LLFC0 */ "", 68594 /* PRIO2EXTQ_LLFC1 */ "", 68595 /* PRIORITY_CONTROL */ "", 68596 /* PRIORITY_MAPPING_SELECT */ "", 68597 /* PRM_CORE_PLL_CFG */ "", 68598 /* PRM_CORE_PLL_CONFIG_127_0 */ "", 68599 /* PRM_CORE_PLL_CONFIG_255_128 */ "", 68600 /* PRM_CORE_PLL_CONFIG_383_256 */ "", 68601 /* PRM_CORE_PLL_STATUS */ "", 68602 /* PRM_GPIO_CFG */ "", 68603 /* PRM_GPIO_CONFIG */ "", 68604 /* PRM_JTAG_CTRL_CFG */ "", 68605 /* PROFILE0_PRI_GRP0 */ "", 68606 /* PROFILE0_PRI_GRP1 */ "", 68607 /* PROFILE1_PRI_GRP0 */ "", 68608 /* PROFILE1_PRI_GRP1 */ "", 68609 /* PROFILE2_PRI_GRP0 */ "", 68610 /* PROFILE2_PRI_GRP1 */ "", 68611 /* PROFILE3_PRI_GRP0 */ "", 68612 /* PROFILE3_PRI_GRP1 */ "", 68613 /* PROTOCOL_PKT_CONTROL */ "", 68614 /* PROT_NHI_CONFIG */ "", 68615 /* PRPLC */ "", 68616 /* PSAMP_CONTROL */ "", 68617 /* PSINTEQ */ "", 68618 /* PSINTQST */ "", 68619 /* PSLPMC_TCID_0 */ "", 68620 /* PSLPMC_TCID_1 */ "", 68621 /* PSLPMC_TCID_2 */ "", 68622 /* PSLPMC_TCID_3 */ "", 68623 /* PSLPMC_TCID_4 */ "", 68624 /* PSLPMC_TCID_5 */ "", 68625 /* PSLPMC_TCID_6 */ "", 68626 /* PSLPMC_TCID_7 */ "", 68627 /* PSLPMC_TCID_8 */ "", 68628 /* PSLPMC_TCID_9 */ "", 68629 /* PSLPMC_TCID_10 */ "", 68630 /* PSLPMC_TCID_11 */ "", 68631 /* PSLPMC_TCID_12 */ "", 68632 /* PSLPMC_TCID_13 */ "", 68633 /* PSLPMC_TCID_14 */ "", 68634 /* PSLPMC_TCID_15 */ "", 68635 /* PSLTH_TCID_0 */ "", 68636 /* PSLTH_TCID_1 */ "", 68637 /* PSLTH_TCID_2 */ "", 68638 /* PSLTH_TCID_3 */ "", 68639 /* PSLTH_TCID_4 */ "", 68640 /* PSLTH_TCID_5 */ "", 68641 /* PSLTH_TCID_6 */ "", 68642 /* PSLTH_TCID_7 */ "", 68643 /* PSLTH_TCID_8 */ "", 68644 /* PSLTH_TCID_9 */ "", 68645 /* PSLTH_TCID_10 */ "", 68646 /* PSLTH_TCID_11 */ "", 68647 /* PSLTH_TCID_12 */ "", 68648 /* PSLTH_TCID_13 */ "", 68649 /* PSLTH_TCID_14 */ "", 68650 /* PSLTH_TCID_15 */ "", 68651 /* PSYSTAT_CHID_0 */ "", 68652 /* PSYSTAT_CHID_1 */ "", 68653 /* PSYSTAT_CHID_2 */ "", 68654 /* PSYSTAT_CHID_3 */ "", 68655 /* PSYSTAT_CHID_4 */ "", 68656 /* PSYSTAT_CHID_5 */ "", 68657 /* PSYSTAT_CHID_6 */ "", 68658 /* PSYSTAT_CHID_7 */ "", 68659 /* PSYSTAT_CHID_8 */ "", 68660 /* PSYSTAT_CHID_9 */ "", 68661 /* PSYSTAT_CHID_10 */ "", 68662 /* PSYSTAT_CHID_11 */ "", 68663 /* PSYSTAT_CHID_12 */ "", 68664 /* PSYSTAT_CHID_13 */ "", 68665 /* PSYSTAT_CHID_14 */ "", 68666 /* PSYSTAT_CHID_15 */ "", 68667 /* PSYSTAT_CHID_16 */ "", 68668 /* PSYSTAT_CHID_17 */ "", 68669 /* PSYSTAT_CHID_18 */ "", 68670 /* PSYSTAT_CHID_19 */ "", 68671 /* PSYSTAT_CHID_20 */ "", 68672 /* PSYSTAT_CHID_21 */ "", 68673 /* PSYSTAT_CHID_22 */ "", 68674 /* PSYSTAT_CHID_23 */ "", 68675 /* PSYSTAT_CHID_24 */ "", 68676 /* PSYSTAT_CHID_25 */ "", 68677 /* PSYSTAT_CHID_26 */ "", 68678 /* PSYSTAT_CHID_27 */ "", 68679 /* PSYSTAT_CHID_28 */ "", 68680 /* PSYSTAT_CHID_29 */ "", 68681 /* PSYSTAT_CHID_30 */ "", 68682 /* PSYSTAT_CHID_31 */ "", 68683 /* PSYSTAT_CHID_32 */ "", 68684 /* PSYSTAT_CHID_33 */ "", 68685 /* PSYSTAT_CHID_34 */ "", 68686 /* PSYSTAT_CHID_35 */ "", 68687 /* PSYSTAT_CHID_36 */ "", 68688 /* PSYSTAT_CHID_37 */ "", 68689 /* PSYSTAT_CHID_38 */ "", 68690 /* PSYSTAT_CHID_39 */ "", 68691 /* PSYSTAT_CHID_40 */ "", 68692 /* PSYSTAT_CHID_41 */ "", 68693 /* PSYSTAT_CHID_42 */ "", 68694 /* PSYSTAT_CHID_43 */ "", 68695 /* PSYSTAT_CHID_44 */ "", 68696 /* PSYSTAT_CHID_45 */ "", 68697 /* PSYSTAT_CHID_46 */ "", 68698 /* PSYSTAT_CHID_47 */ "", 68699 /* PSYSTAT_CHID_48 */ "", 68700 /* PSYSTAT_CHID_49 */ "", 68701 /* PSYSTAT_CHID_50 */ "", 68702 /* PSYSTAT_CHID_51 */ "", 68703 /* PSYSTAT_CHID_52 */ "", 68704 /* PSYSTAT_CHID_53 */ "", 68705 /* PSYSTAT_CHID_54 */ "", 68706 /* PSYSTAT_CHID_55 */ "", 68707 /* PSYSTAT_CHID_56 */ "", 68708 /* PSYSTAT_CHID_57 */ "", 68709 /* PSYSTAT_CHID_58 */ "", 68710 /* PSYSTAT_CHID_59 */ "", 68711 /* PSYSTAT_CHID_60 */ "", 68712 /* PSYSTAT_CHID_61 */ "", 68713 /* PSYSTAT_CHID_62 */ "", 68714 /* PSYSTAT_CHID_63 */ "", 68715 /* PTP_DOMAIN_ID_MAP */ "", 68716 /* PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_CONTROL */ "", 68717 /* PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_STATUS_INTR */ "", 68718 /* PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_STATUS_NACK */ "", 68719 /* PTP_LOCK */ "", 68720 /* PTR_COPYTOCPU_MASK_0 */ "", 68721 /* PTR_COPYTOCPU_MASK_1 */ "", 68722 /* PTR_COPYTOCPU_MASK_2 */ "", 68723 /* PTS_ARB_DEBUG */ "", 68724 /* PTS_DEQ_CMD_IRDY_TH */ "", 68725 /* PTS_ECC_1B_ERR_CNT */ "", 68726 /* PTS_ECC_2B_ERR_CNT */ "", 68727 /* PTS_ECC_ERR_1B_INITIATE */ "", 68728 /* PTS_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 68729 /* PTS_ECC_ERR_2B_INITIATE */ "", 68730 /* PTS_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 68731 /* PTS_ECC_INTERRUPT_REGISTER */ "", 68732 /* PTS_ECC_INTERRUPT_REGISTER_MASK */ "", 68733 /* PTS_ECC_INTERRUPT_REGISTER_TEST */ "", 68734 /* PTS_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 68735 /* PTS_ERROR_INITIATION_DATA */ "", 68736 /* PTS_FIFOS_MAX_OCC_0 */ "", 68737 /* PTS_FMC_FC_STATUS_VEC */ "", 68738 /* PTS_GCI_BACKOFF_CS_WEIGHTS */ "", 68739 /* PTS_GCI_BACKOFF_MASK_LUT_1 */ "", 68740 /* PTS_GCI_BACKOFF_MASK_LUT_2 */ "", 68741 /* PTS_GCI_BACKOFF_MASK_LUT_3 */ "", 68742 /* PTS_GCI_BACKOFF_RANGE_THRESHOLDS */ "", 68743 /* PTS_GCI_BKFF_LEVEL */ "", 68744 /* PTS_GCI_CNT */ "", 68745 /* PTS_GCI_LEAKY_BUCKET_CONFIGURATION_REGISTER_0 */ "", 68746 /* PTS_GCI_LEAKY_BUCKET_CONFIGURATION_REGISTER_1 */ "", 68747 /* PTS_GCI_LEAKY_BUCKET_CONFIGURATION_REGISTER_2 */ "", 68748 /* PTS_GCI_LKY_MAX_OC_1 */ "", 68749 /* PTS_GLOBAL_GENERAL_CFG_1 */ "", 68750 /* PTS_GLOBAL_GENERAL_CFG_2 */ "", 68751 /* PTS_GLOBAL_MEM_OPTIONS */ "", 68752 /* PTS_GTIMER_CONFIGURATION */ "", 68753 /* PTS_INDIRECT_COMMAND */ "", 68754 /* PTS_INDIRECT_COMMAND_ADDRESS */ "", 68755 /* PTS_INDIRECT_COMMAND_DATA_INCREMENT */ "", 68756 /* PTS_INDIRECT_COMMAND_RD_DATA */ "", 68757 /* PTS_INDIRECT_COMMAND_WIDE_MEM */ "", 68758 /* PTS_INDIRECT_COMMAND_WR_DATA */ "", 68759 /* PTS_INDIRECT_FORCE_BUBBLE */ "", 68760 /* PTS_INTERRUPT_MASK_REGISTER */ "", 68761 /* PTS_INTERRUPT_REGISTER */ "", 68762 /* PTS_INTERRUPT_REGISTER_TEST */ "", 68763 /* PTS_IPT_FMC_IPS_FC_MAP */ "", 68764 /* PTS_IPT_INTRNL_FMC_FC_MAP */ "", 68765 /* PTS_PACKET_DEQUEUE_GENERAL_CONFIGS */ "", 68766 /* PTS_PDQ_MC_TH */ "", 68767 /* PTS_PDQ_OVTH_FC_MASK */ "", 68768 /* PTS_PDQ_STATUS_VEC */ "", 68769 /* PTS_PDQ_STATUS_VEC_FLIP_POLARITY */ "", 68770 /* PTS_PDQ_STATUS_VEC_STICKY */ "", 68771 /* PTS_PTS_CHICKEN_BITS */ "", 68772 /* PTS_PTS_DEBUG_CONTROLS */ "", 68773 /* PTS_PTS_FMC_IPS_FC_MAP */ "", 68774 /* PTS_PTS_TO_IPT_FC_STATUS_VEC */ "", 68775 /* PTS_PTS_TO_IPT_FC_STATUS_VEC_STICKY */ "", 68776 /* PTS_REG_0101 */ "", 68777 /* PTS_RESERVED_MIRROR_ADDR */ "", 68778 /* PTS_RESERVED_MTCD */ "", 68779 /* PTS_RESERVED_MTCP */ "", 68780 /* PTS_RESERVED_SPARE_0 */ "", 68781 /* PTS_RESERVED_SPARE_1 */ "", 68782 /* PTS_RESERVED_SPARE_2 */ "", 68783 /* PTS_RESERVED_SPARE_3 */ "", 68784 /* PTS_RXI_COUNTER */ "", 68785 /* PTS_SBUS_BROADCAST_ID */ "", 68786 /* PTS_SBUS_LAST_IN_CHAIN */ "", 68787 /* PTS_SHAPER_GENERAL_CONFIGS */ "", 68788 /* PTS_SHAPER_OVTH_FC_MASK */ "", 68789 /* PTS_SHAPER_STATUS */ "", 68790 /* PTS_SPB_MONITOR_DEBUG */ "", 68791 /* PTS_TXI_COUNTER */ "", 68792 /* PTS_WFQ_GENERAL_CONFIG */ "", 68793 /* PURGE_PKT_CNT */ "", 68794 /* PWIBLPC_CHID_0 */ "", 68795 /* PWIBLPC_CHID_1 */ "", 68796 /* PWIBLPC_CHID_2 */ "", 68797 /* PWIBLPC_CHID_3 */ "", 68798 /* PWIBLPC_CHID_4 */ "", 68799 /* PWIBLPC_CHID_5 */ "", 68800 /* PWIBLPC_CHID_6 */ "", 68801 /* PWIBLPC_CHID_7 */ "", 68802 /* PWIBLPC_CHID_8 */ "", 68803 /* PWIBLPC_CHID_9 */ "", 68804 /* PWIBLPC_CHID_10 */ "", 68805 /* PWIBLPC_CHID_11 */ "", 68806 /* PWIBLPC_CHID_12 */ "", 68807 /* PWIBLPC_CHID_13 */ "", 68808 /* PWIBLPC_CHID_14 */ "", 68809 /* PWIBLPC_CHID_15 */ "", 68810 /* PWIBLPC_CHID_16 */ "", 68811 /* PWIBLPC_CHID_17 */ "", 68812 /* PWIBLPC_CHID_18 */ "", 68813 /* PWIBLPC_CHID_19 */ "", 68814 /* PWIBLPC_CHID_20 */ "", 68815 /* PWIBLPC_CHID_21 */ "", 68816 /* PWIBLPC_CHID_22 */ "", 68817 /* PWIBLPC_CHID_23 */ "", 68818 /* PWIBLPC_CHID_24 */ "", 68819 /* PWIBLPC_CHID_25 */ "", 68820 /* PWIBLPC_CHID_26 */ "", 68821 /* PWIBLPC_CHID_27 */ "", 68822 /* PWIBLPC_CHID_28 */ "", 68823 /* PWIBLPC_CHID_29 */ "", 68824 /* PWIBLPC_CHID_30 */ "", 68825 /* PWIBLPC_CHID_31 */ "", 68826 /* PWIBLPC_CHID_32 */ "", 68827 /* PWIBLPC_CHID_33 */ "", 68828 /* PWIBLPC_CHID_34 */ "", 68829 /* PWIBLPC_CHID_35 */ "", 68830 /* PWIBLPC_CHID_36 */ "", 68831 /* PWIBLPC_CHID_37 */ "", 68832 /* PWIBLPC_CHID_38 */ "", 68833 /* PWIBLPC_CHID_39 */ "", 68834 /* PWIBLPC_CHID_40 */ "", 68835 /* PWIBLPC_CHID_41 */ "", 68836 /* PWIBLPC_CHID_42 */ "", 68837 /* PWIBLPC_CHID_43 */ "", 68838 /* PWIBLPC_CHID_44 */ "", 68839 /* PWIBLPC_CHID_45 */ "", 68840 /* PWIBLPC_CHID_46 */ "", 68841 /* PWIBLPC_CHID_47 */ "", 68842 /* PWIBLPC_CHID_48 */ "", 68843 /* PWIBLPC_CHID_49 */ "", 68844 /* PWIBLPC_CHID_50 */ "", 68845 /* PWIBLPC_CHID_51 */ "", 68846 /* PWIBLPC_CHID_52 */ "", 68847 /* PWIBLPC_CHID_53 */ "", 68848 /* PWIBLPC_CHID_54 */ "", 68849 /* PWIBLPC_CHID_55 */ "", 68850 /* PWIBLPC_CHID_56 */ "", 68851 /* PWIBLPC_CHID_57 */ "", 68852 /* PWIBLPC_CHID_58 */ "", 68853 /* PWIBLPC_CHID_59 */ "", 68854 /* PWIBLPC_CHID_60 */ "", 68855 /* PWIBLPC_CHID_61 */ "", 68856 /* PWIBLPC_CHID_62 */ "", 68857 /* PWIBLPC_CHID_63 */ "", 68858 /* PWIRPC_CHID_0 */ "", 68859 /* PWIRPC_CHID_1 */ "", 68860 /* PWIRPC_CHID_2 */ "", 68861 /* PWIRPC_CHID_3 */ "", 68862 /* PWIRPC_CHID_4 */ "", 68863 /* PWIRPC_CHID_5 */ "", 68864 /* PWIRPC_CHID_6 */ "", 68865 /* PWIRPC_CHID_7 */ "", 68866 /* PWIRPC_CHID_8 */ "", 68867 /* PWIRPC_CHID_9 */ "", 68868 /* PWIRPC_CHID_10 */ "", 68869 /* PWIRPC_CHID_11 */ "", 68870 /* PWIRPC_CHID_12 */ "", 68871 /* PWIRPC_CHID_13 */ "", 68872 /* PWIRPC_CHID_14 */ "", 68873 /* PWIRPC_CHID_15 */ "", 68874 /* PWIRPC_CHID_16 */ "", 68875 /* PWIRPC_CHID_17 */ "", 68876 /* PWIRPC_CHID_18 */ "", 68877 /* PWIRPC_CHID_19 */ "", 68878 /* PWIRPC_CHID_20 */ "", 68879 /* PWIRPC_CHID_21 */ "", 68880 /* PWIRPC_CHID_22 */ "", 68881 /* PWIRPC_CHID_23 */ "", 68882 /* PWIRPC_CHID_24 */ "", 68883 /* PWIRPC_CHID_25 */ "", 68884 /* PWIRPC_CHID_26 */ "", 68885 /* PWIRPC_CHID_27 */ "", 68886 /* PWIRPC_CHID_28 */ "", 68887 /* PWIRPC_CHID_29 */ "", 68888 /* PWIRPC_CHID_30 */ "", 68889 /* PWIRPC_CHID_31 */ "", 68890 /* PWIRPC_CHID_32 */ "", 68891 /* PWIRPC_CHID_33 */ "", 68892 /* PWIRPC_CHID_34 */ "", 68893 /* PWIRPC_CHID_35 */ "", 68894 /* PWIRPC_CHID_36 */ "", 68895 /* PWIRPC_CHID_37 */ "", 68896 /* PWIRPC_CHID_38 */ "", 68897 /* PWIRPC_CHID_39 */ "", 68898 /* PWIRPC_CHID_40 */ "", 68899 /* PWIRPC_CHID_41 */ "", 68900 /* PWIRPC_CHID_42 */ "", 68901 /* PWIRPC_CHID_43 */ "", 68902 /* PWIRPC_CHID_44 */ "", 68903 /* PWIRPC_CHID_45 */ "", 68904 /* PWIRPC_CHID_46 */ "", 68905 /* PWIRPC_CHID_47 */ "", 68906 /* PWIRPC_CHID_48 */ "", 68907 /* PWIRPC_CHID_49 */ "", 68908 /* PWIRPC_CHID_50 */ "", 68909 /* PWIRPC_CHID_51 */ "", 68910 /* PWIRPC_CHID_52 */ "", 68911 /* PWIRPC_CHID_53 */ "", 68912 /* PWIRPC_CHID_54 */ "", 68913 /* PWIRPC_CHID_55 */ "", 68914 /* PWIRPC_CHID_56 */ "", 68915 /* PWIRPC_CHID_57 */ "", 68916 /* PWIRPC_CHID_58 */ "", 68917 /* PWIRPC_CHID_59 */ "", 68918 /* PWIRPC_CHID_60 */ "", 68919 /* PWIRPC_CHID_61 */ "", 68920 /* PWIRPC_CHID_62 */ "", 68921 /* PWIRPC_CHID_63 */ "", 68922 /* PWOTPC_CHID_0 */ "", 68923 /* PWOTPC_CHID_1 */ "", 68924 /* PWOTPC_CHID_2 */ "", 68925 /* PWOTPC_CHID_3 */ "", 68926 /* PWOTPC_CHID_4 */ "", 68927 /* PWOTPC_CHID_5 */ "", 68928 /* PWOTPC_CHID_6 */ "", 68929 /* PWOTPC_CHID_7 */ "", 68930 /* PWOTPC_CHID_8 */ "", 68931 /* PWOTPC_CHID_9 */ "", 68932 /* PWOTPC_CHID_10 */ "", 68933 /* PWOTPC_CHID_11 */ "", 68934 /* PWOTPC_CHID_12 */ "", 68935 /* PWOTPC_CHID_13 */ "", 68936 /* PWOTPC_CHID_14 */ "", 68937 /* PWOTPC_CHID_15 */ "", 68938 /* PWOTPC_CHID_16 */ "", 68939 /* PWOTPC_CHID_17 */ "", 68940 /* PWOTPC_CHID_18 */ "", 68941 /* PWOTPC_CHID_19 */ "", 68942 /* PWOTPC_CHID_20 */ "", 68943 /* PWOTPC_CHID_21 */ "", 68944 /* PWOTPC_CHID_22 */ "", 68945 /* PWOTPC_CHID_23 */ "", 68946 /* PWOTPC_CHID_24 */ "", 68947 /* PWOTPC_CHID_25 */ "", 68948 /* PWOTPC_CHID_26 */ "", 68949 /* PWOTPC_CHID_27 */ "", 68950 /* PWOTPC_CHID_28 */ "", 68951 /* PWOTPC_CHID_29 */ "", 68952 /* PWOTPC_CHID_30 */ "", 68953 /* PWOTPC_CHID_31 */ "", 68954 /* PWOTPC_CHID_32 */ "", 68955 /* PWOTPC_CHID_33 */ "", 68956 /* PWOTPC_CHID_34 */ "", 68957 /* PWOTPC_CHID_35 */ "", 68958 /* PWOTPC_CHID_36 */ "", 68959 /* PWOTPC_CHID_37 */ "", 68960 /* PWOTPC_CHID_38 */ "", 68961 /* PWOTPC_CHID_39 */ "", 68962 /* PWOTPC_CHID_40 */ "", 68963 /* PWOTPC_CHID_41 */ "", 68964 /* PWOTPC_CHID_42 */ "", 68965 /* PWOTPC_CHID_43 */ "", 68966 /* PWOTPC_CHID_44 */ "", 68967 /* PWOTPC_CHID_45 */ "", 68968 /* PWOTPC_CHID_46 */ "", 68969 /* PWOTPC_CHID_47 */ "", 68970 /* PWOTPC_CHID_48 */ "", 68971 /* PWOTPC_CHID_49 */ "", 68972 /* PWOTPC_CHID_50 */ "", 68973 /* PWOTPC_CHID_51 */ "", 68974 /* PWOTPC_CHID_52 */ "", 68975 /* PWOTPC_CHID_53 */ "", 68976 /* PWOTPC_CHID_54 */ "", 68977 /* PWOTPC_CHID_55 */ "", 68978 /* PWOTPC_CHID_56 */ "", 68979 /* PWOTPC_CHID_57 */ "", 68980 /* PWOTPC_CHID_58 */ "", 68981 /* PWOTPC_CHID_59 */ "", 68982 /* PWOTPC_CHID_60 */ "", 68983 /* PWOTPC_CHID_61 */ "", 68984 /* PWOTPC_CHID_62 */ "", 68985 /* PWOTPC_CHID_63 */ "", 68986 /* PWR_WATCH_DOG_CONTROL_MB */ "", 68987 /* PWR_WATCH_DOG_CONTROL_MBX */ "", 68988 /* PWR_WATCH_DOG_CONTROL_MBY */ "", 68989 /* PWR_WATCH_DOG_STATUS_MB */ "", 68990 /* PWR_WATCH_DOG_STATUS_MBX */ "", 68991 /* PWR_WATCH_DOG_STATUS_MBY */ "", 68992 /* P_R64 */ "XLPMIB_GRx64", 68993 /* P_R127 */ "XLPMIB_GRx127", 68994 /* P_R255 */ "XLPMIB_GRx255", 68995 /* P_R511 */ "XLPMIB_GRx511", 68996 /* P_R1023 */ "XLPMIB_GRx1023", 68997 /* P_R1518 */ "XLPMIB_GRx1518", 68998 /* P_R2047 */ "XLPMIB_GRx2047", 68999 /* P_R4095 */ "XLPMIB_GRx4095", 69000 /* P_R9216 */ "XLPMIB_GRx9216", 69001 /* P_R16383 */ "XLPMIB_GRx16383", 69002 /* P_RALN */ "XLPMIB_GRxALN", 69003 /* P_RBCA */ "XLPMIB_GRxBCA", 69004 /* P_RBYT */ "XLPMIB_GRxByt", 69005 /* P_RDVLN */ "XLPMIB_GRxDVLN", 69006 /* P_RERPKT */ "XLPMIB_GRxFrErr", 69007 /* P_RFCR */ "XLPMIB_GRxFCR", 69008 /* P_RFCS */ "XLPMIB_GRxFCS", 69009 /* P_RFFMSE */ "XLPMIB_GRxFFMSE", 69010 /* P_RFLR */ "XLPMIB_GRxFLR", 69011 /* P_RFRG */ "XLPMIB_GRxFRG", 69012 /* P_RJBR */ "XLPMIB_GRxJBR", 69013 /* P_RMCA */ "XLPMIB_GRxMCA", 69014 /* P_RMCRC */ "XLPMIB_GRxMCRC", 69015 /* P_RMDIS */ "XLPMIB_GRxMDIS", 69016 /* P_RMFAE */ "XLPMIB_GRxMFAE", 69017 /* P_RMFAO */ "XLPMIB_GRxMFAO", 69018 /* P_RMFC */ "XLPMIB_GRxMFC", 69019 /* P_RMFSE */ "XLPMIB_GRxMFSE", 69020 /* P_RMGV */ "XLPMIB_GRx1522", 69021 /* P_RMTUE */ "XLPMIB_GRxMTUE", 69022 /* P_RNFFMSE */ "XLPMIB_GRxNFFMSE", 69023 /* P_ROVR */ "XLPMIB_GRxOVR", 69024 /* P_RPFC0 */ "XLPMIB_GRxPFCP0", 69025 /* P_RPFC1 */ "XLPMIB_GRxPFCP1", 69026 /* P_RPFC2 */ "XLPMIB_GRxPFCP2", 69027 /* P_RPFC3 */ "XLPMIB_GRxPFCP3", 69028 /* P_RPFC4 */ "XLPMIB_GRxPFCP4", 69029 /* P_RPFC5 */ "XLPMIB_GRxPFCP5", 69030 /* P_RPFC6 */ "XLPMIB_GRxPFCP6", 69031 /* P_RPFC7 */ "XLPMIB_GRxPFCP7", 69032 /* P_RPFCOFF7 */ "XLPMIB_GRxPFCOFF7", 69033 /* P_RPKT */ "XLPMIB_GRxPkt", 69034 /* P_RPOK */ "XLPMIB_GRxPOK", 69035 /* P_RPRM */ "XLPMIB_GRxPRM", 69036 /* P_RPROG0 */ "XLPMIB_GRxProg0", 69037 /* P_RPROG1 */ "XLPMIB_GRxProg1", 69038 /* P_RPROG2 */ "XLPMIB_GRxProg2", 69039 /* P_RPROG3 */ "XLPMIB_GRxProg3", 69040 /* P_RRBYT */ "XLPMIB_GRxRByt", 69041 /* P_RRPKT */ "XLPMIB_GRxRPkt", 69042 /* P_RSCHCRC */ "XLPMIB_GRxSCHCRC", 69043 /* P_RTRFU */ "XLPMIB_GRxTRFU", 69044 /* P_RUCA */ "XLPMIB_GRxUCA", 69045 /* P_RUND */ "XLPMIB_GRxUND", 69046 /* P_RVLN */ "XLPMIB_GRxVLN", 69047 /* P_RXCF */ "XLPMIB_GRxCF", 69048 /* P_RXPF */ "XLPMIB_GRxPF", 69049 /* P_RXPP */ "XLPMIB_GRxPP", 69050 /* P_RXUDA */ "XLPMIB_GRxUDA", 69051 /* P_RXUO */ "XLPMIB_GRxUO", 69052 /* P_RXWSA */ "XLPMIB_GRxWSA", 69053 /* P_RX_EEE_LPI_DURATION_COUNTER */ "XLPMIB_RX_EEE_LPI_DURATION_COUNTER", 69054 /* P_RX_EEE_LPI_EVENT_COUNTER */ "XLPMIB_RX_EEE_LPI_EVENT_COUNTER", 69055 /* P_RX_HCFC_COUNTER */ "XLPMIB_RX_HCFC_COUNTER", 69056 /* P_RX_HCFC_CRC_COUNTER */ "XLPMIB_RX_HCFC_CRC_COUNTER", 69057 /* P_RX_LLFC_CRC_COUNTER */ "XLPMIB_RX_LLFC_CRC_COUNTER", 69058 /* P_RX_LLFC_LOG_COUNTER */ "XLPMIB_RX_LLFC_LOG_COUNTER", 69059 /* P_RX_LLFC_PHY_COUNTER */ "XLPMIB_RX_LLFC_PHY_COUNTER", 69060 /* P_T64 */ "XLPMIB_GTx64", 69061 /* P_T127 */ "XLPMIB_GTx127", 69062 /* P_T255 */ "XLPMIB_GTx255", 69063 /* P_T511 */ "XLPMIB_GTx511", 69064 /* P_T1023 */ "XLPMIB_GTx1023", 69065 /* P_T1518 */ "XLPMIB_GTx1518", 69066 /* P_T2047 */ "XLPMIB_GTx2047", 69067 /* P_T4095 */ "XLPMIB_GTx4095", 69068 /* P_T9216 */ "XLPMIB_GTx9216", 69069 /* P_T16383 */ "XLPMIB_GTx16383", 69070 /* P_TBCA */ "XLPMIB_GTxBCA", 69071 /* P_TBYT */ "XLPMIB_GTxBYT", 69072 /* P_TDVLN */ "XLPMIB_GTxDVLN", 69073 /* P_TERR */ "XLPMIB_GTxErr", 69074 /* P_TFCS */ "XLPMIB_GTxFCS", 69075 /* P_TFRG */ "XLPMIB_GTxFRG", 69076 /* P_TJBR */ "XLPMIB_GTxJBR", 69077 /* P_TLCL */ "XLPMIB_GTxLCL", 69078 /* P_TMCA */ "XLPMIB_GTxMCA", 69079 /* P_TMCL */ "XLPMIB_GTxMCL", 69080 /* P_TMFAE */ "XLPMIB_GTxMFAE", 69081 /* P_TMFC */ "XLPMIB_GTxMFC", 69082 /* P_TMGV */ "XLPMIB_GTx1522", 69083 /* P_TNCL */ "XLPMIB_GTxNCL", 69084 /* P_TOVR */ "XLPMIB_GTxOVR", 69085 /* P_TPFC0 */ "XLPMIB_GTxPFCP0", 69086 /* P_TPFC1 */ "XLPMIB_GTxPFCP1", 69087 /* P_TPFC2 */ "XLPMIB_GTxPFCP2", 69088 /* P_TPFC3 */ "XLPMIB_GTxPFCP3", 69089 /* P_TPFC4 */ "XLPMIB_GTxPFCP4", 69090 /* P_TPFC5 */ "XLPMIB_GTxPFCP5", 69091 /* P_TPFC6 */ "XLPMIB_GTxPFCP6", 69092 /* P_TPFC7 */ "XLPMIB_GTxPFCP7", 69093 /* P_TPFCOFF0 */ "XLPMIB_GTxPFCOFF0", 69094 /* P_TPFCOFF1 */ "XLPMIB_GTxPFCOFF1", 69095 /* P_TPFCOFF2 */ "XLPMIB_GTxPFCOFF2", 69096 /* P_TPFCOFF3 */ "XLPMIB_GTxPFCOFF3", 69097 /* P_TPFCOFF4 */ "XLPMIB_GTxPFCOFF4", 69098 /* P_TPFCOFF5 */ "XLPMIB_GTxPFCOFF5", 69099 /* P_TPFCOFF6 */ "XLPMIB_GTxPFCOFF6", 69100 /* P_TPFCOFF7 */ "XLPMIB_GTxPFCOFF7", 69101 /* P_TPKT */ "XLPMIB_GTxPkt", 69102 /* P_TPOK */ "XLPMIB_GTxPOK", 69103 /* P_TRPKT */ "XLPMIB_GTxRPKT", 69104 /* P_TSCL */ "XLPMIB_GTxSCL", 69105 /* P_TSPARE0 */ "XLPMIB_GTxSPARE0", 69106 /* P_TSPARE1 */ "XLPMIB_GTxSPARE1", 69107 /* P_TSPARE2 */ "XLPMIB_GTxSPARE2", 69108 /* P_TSPARE3 */ "XLPMIB_GTxSPARE3", 69109 /* P_TUCA */ "XLPMIB_GTxUCA", 69110 /* P_TUFL */ "XLPMIB_GTxUFL", 69111 /* P_TVLN */ "XLPMIB_GTxVLN", 69112 /* P_TXCF */ "XLPMIB_GTxCF", 69113 /* P_TXCL */ "XLPMIB_GTxXCL", 69114 /* P_TXPF */ "XLPMIB_GTxPF", 69115 /* P_TXPP */ "XLPMIB_GTxPP", 69116 /* P_TX_EEE_LPI_DURATION_COUNTER */ "XLPMIB_TX_EEE_LPI_DURATION_COUNTER", 69117 /* P_TX_EEE_LPI_EVENT_COUNTER */ "XLPMIB_TX_EEE_LPI_EVENT_COUNTER", 69118 /* P_TX_HCFC_COUNTER */ "XLPMIB_TX_HCFC_COUNTER", 69119 /* P_TX_LLFC_LOG_COUNTER */ "XLPMIB_TX_LLFC_LOG_COUNTER", 69120 /* P_XTHOL */ "XLPMIB_XTHOL", 69121 /* QBLOCK_NEXT_MEMDEBUG */ "", 69122 /* QBLOCK_NEXT_MEM_ECC_STATUS_0 */ "", 69123 /* QBLOCK_NEXT_MEM_ECC_STATUS_1 */ "", 69124 /* QBLOCK_NEXT_MEM_ECC_STATUS_2 */ "", 69125 /* QBLOCK_NEXT_MEM_ECC_STATUS_3 */ "", 69126 /* QBLOCK_NEXT_MEM_ECC_STATUS_4 */ "", 69127 /* QBLOCK_NEXT_MEM_ECC_STATUS_5 */ "", 69128 /* QBLOCK_NEXT_MEM_ECC_STATUS_6 */ "", 69129 /* QBLOCK_NEXT_MEM_ECC_STATUS_7 */ "", 69130 /* QCN_CNM_PRP_CNT */ "", 69131 /* QCN_CNM_PRP_CTRL */ "", 69132 /* QCN_CNM_PRP_DLF_COUNT */ "", 69133 /* QCN_CNM_PRP_DLF_COUNT_X */ "", 69134 /* QCN_CNM_PRP_DLF_COUNT_Y */ "", 69135 /* QCN_CNM_RVD_TBL_ECC_ERR1 */ "", 69136 /* QCN_CNM_RVD_TBL_ECC_ERR2 */ "", 69137 /* QCN_CNM_TIMER_TBL_ECC_ERR1 */ "", 69138 /* QCN_CNM_TIMER_TBL_ECC_ERR2 */ "", 69139 /* QCN_PFC_STATE */ "", 69140 /* QCN_TBID_TBL_ECC_ERR1 */ "", 69141 /* QCN_TBID_TBL_ECC_ERR2 */ "", 69142 /* QCN_TOV_TBL_ECC_ERR1 */ "", 69143 /* QCN_TOV_TBL_ECC_ERR2 */ "", 69144 /* QDB_MEM_DEBUG */ "", 69145 /* QDB_MEM_DEBUG_TM */ "", 69146 /* QENTRY_LOWER_MEMDEBUG_0 */ "", 69147 /* QENTRY_LOWER_MEMDEBUG_1 */ "", 69148 /* QENTRY_LOWER_MEM_ECC_STATUS_0 */ "", 69149 /* QENTRY_LOWER_MEM_ECC_STATUS_1 */ "", 69150 /* QENTRY_LOWER_MEM_ECC_STATUS_2 */ "", 69151 /* QENTRY_LOWER_MEM_ECC_STATUS_3 */ "", 69152 /* QENTRY_LOWER_MEM_ECC_STATUS_4 */ "", 69153 /* QENTRY_LOWER_MEM_ECC_STATUS_5 */ "", 69154 /* QENTRY_LOWER_MEM_ECC_STATUS_6 */ "", 69155 /* QENTRY_LOWER_MEM_ECC_STATUS_7 */ "", 69156 /* QENTRY_L_MEMDEBUG */ "", 69157 /* QENTRY_MEM_ECC_STATUS_0 */ "", 69158 /* QENTRY_UPPER_MEMDEBUG_0 */ "", 69159 /* QENTRY_UPPER_MEMDEBUG_1 */ "", 69160 /* QENTRY_UPPER_MEM_ECC_STATUS_0 */ "", 69161 /* QENTRY_UPPER_MEM_ECC_STATUS_1 */ "", 69162 /* QENTRY_UPPER_MEM_ECC_STATUS_2 */ "", 69163 /* QENTRY_UPPER_MEM_ECC_STATUS_3 */ "", 69164 /* QENTRY_UPPER_MEM_ECC_STATUS_4 */ "", 69165 /* QENTRY_UPPER_MEM_ECC_STATUS_5 */ "", 69166 /* QENTRY_UPPER_MEM_ECC_STATUS_6 */ "", 69167 /* QENTRY_UPPER_MEM_ECC_STATUS_7 */ "", 69168 /* QENTRY_U_MEMDEBUG */ "", 69169 /* QE_INTEROP_CONFIG */ "", 69170 /* QGPORT_CONFIG */ "", 69171 /* QGPORT_MAC_XGXS_CTRL */ "", 69172 /* QGPORT_MAC_XGXS_STAT_GS0 */ "", 69173 /* QGPORT_MAC_XGXS_STAT_GS1 */ "", 69174 /* QGPORT_MAC_XGXS_STAT_GS2 */ "", 69175 /* QGPORT_MAC_XGXS_STAT_GS3 */ "", 69176 /* QPORT_CNTMAXSIZE */ "", 69177 /* QPORT_CONFIG */ "", 69178 /* QPORT_RSV_MASK */ "", 69179 /* QPORT_SGNDET_EARLYCRS */ "", 69180 /* QPORT_STAT_UPDATE_MASK */ "", 69181 /* QPORT_TPID */ "", 69182 /* QRH_ALLOWED_LINKS_PIPE_0_REGISTER */ "", 69183 /* QRH_ALLOWED_LINKS_PIPE_1_REGISTER */ "", 69184 /* QRH_ALLOWED_LINKS_PIPE_2_REGISTER */ "", 69185 /* QRH_ALL_MUL_DROP_TH */ "", 69186 /* QRH_AUTO_DOC_NAME_0 */ "", 69187 /* QRH_AUTO_DOC_NAME_1 */ "", 69188 /* QRH_CRH_INTERRUPT_MASK_REGISTER */ "", 69189 /* QRH_CRH_INTERRUPT_REGISTER */ "", 69190 /* QRH_CRH_INTERRUPT_REGISTER_TEST */ "", 69191 /* QRH_DRH_DROPPED_LOW_MUL */ "", 69192 /* QRH_DRH_FLOW_CONTROL_CNT_P */ "", 69193 /* QRH_DRH_INPUT_QUERY_CNT_P */ "", 69194 /* QRH_DRH_INTERRUPT_MASK_REGISTER */ "", 69195 /* QRH_DRH_INTERRUPT_REGISTER */ "", 69196 /* QRH_DRH_INTERRUPT_REGISTER_TEST */ "", 69197 /* QRH_DRH_LOAD_BALANCING_GENERAL_CONFIG */ "", 69198 /* QRH_DRH_LOAD_BALANCING_LEVEL_CONFIG */ "", 69199 /* QRH_DRH_LOAD_BALANCING_LEVEL_OPTIMIZATION */ "", 69200 /* QRH_DRH_MCSFF_HIT_COUNTER */ "", 69201 /* QRH_DRH_OUTPUT_REPLY_CNT_P */ "", 69202 /* QRH_DRH_REP_FIFO_STAT_P */ "", 69203 /* QRH_DRH_UNREACHABLEMULTICASTINFO */ "", 69204 /* QRH_DRH_WFQ_CONFIGURATIONS */ "", 69205 /* QRH_DYN_PIPES_WEIGHTS_REGISTER */ "", 69206 /* QRH_ECC_1B_ERR_CNT */ "", 69207 /* QRH_ECC_2B_ERR_CNT */ "", 69208 /* QRH_ECC_ERR_1B_INITIATE */ "", 69209 /* QRH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 69210 /* QRH_ECC_ERR_2B_INITIATE */ "", 69211 /* QRH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 69212 /* QRH_ECC_INTERRUPT_REGISTER */ "", 69213 /* QRH_ECC_INTERRUPT_REGISTER_MASK */ "", 69214 /* QRH_ECC_INTERRUPT_REGISTER_TEST */ "", 69215 /* QRH_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 69216 /* QRH_ERROR_INITIATION_DATA */ "", 69217 /* QRH_FE_GLOBAL_FE_DEST_IDS_1 */ "", 69218 /* QRH_FE_GLOBAL_FE_DEST_IDS_2 */ "", 69219 /* QRH_FE_GLOBAL_FE_DEST_IDS_3 */ "", 69220 /* QRH_FE_GLOBAL_FE_DEST_IDS_4 */ "", 69221 /* QRH_FE_GLOBAL_GENERAL_CFG_1 */ "", 69222 /* QRH_FE_GROUP_DEST_ID */ "", 69223 /* QRH_GLOBAL_MEM_OPTIONS */ "", 69224 /* QRH_GTIMER_CONFIGURATION */ "", 69225 /* QRH_GTIMER_CYCLE */ "", 69226 /* QRH_INDIRECT_COMMAND */ "", 69227 /* QRH_INDIRECT_COMMAND_ADDRESS */ "", 69228 /* QRH_INDIRECT_COMMAND_DATA_INCREMENT */ "", 69229 /* QRH_INDIRECT_COMMAND_RD_DATA */ "", 69230 /* QRH_INDIRECT_COMMAND_WIDE_MEM */ "", 69231 /* QRH_INDIRECT_COMMAND_WR_DATA */ "", 69232 /* QRH_INDIRECT_FORCE_BUBBLE */ "", 69233 /* QRH_INTERRUPT_MASK_REGISTER */ "", 69234 /* QRH_INTERRUPT_REGISTER */ "", 69235 /* QRH_INTERRUPT_REGISTER_TEST */ "", 69236 /* QRH_LCM_FC_CONFIG */ "", 69237 /* QRH_LOAD_BALANCE_MAX_DEBUG_LINK_P */ "", 69238 /* QRH_LOAD_BALANCE_MAX_LEVEL_P */ "", 69239 /* QRH_LOCAL_ROUTE_CONFIGURATIONS */ "", 69240 /* QRH_LOW_PR_MULTH */ "", 69241 /* QRH_LOW_PR_MUL_CTRL */ "", 69242 /* QRH_MASK_FC_AGING_PERIOD */ "", 69243 /* QRH_MULICAST_ALLOWED_LINKS_REGISTER */ "", 69244 /* QRH_MULTICAST_MODE_SELECTION */ "", 69245 /* QRH_PIPES_WEIGHTS_COUNTER_0 */ "", 69246 /* QRH_PIPES_WEIGHTS_COUNTER_1 */ "", 69247 /* QRH_PIPES_WEIGHTS_COUNTER_2 */ "", 69248 /* QRH_REACHABILITY_MESSAGE_GENERATOR_CONFIGURATION */ "", 69249 /* QRH_RESERVED_MIRROR_ADDR */ "", 69250 /* QRH_RESERVED_MTCD */ "", 69251 /* QRH_RESERVED_MTCP */ "", 69252 /* QRH_RESERVED_SPARE_0 */ "", 69253 /* QRH_RESERVED_SPARE_1 */ "", 69254 /* QRH_RESERVED_SPARE_2 */ "", 69255 /* QRH_RESERVED_SPARE_3 */ "", 69256 /* QRH_SBUS_BROADCAST_ID */ "", 69257 /* QRH_SBUS_LAST_IN_CHAIN */ "", 69258 /* QRH_SIMPLE_RR_LINKS_CONFIG */ "", 69259 /* QSPI_BSPI_REGISTERS_B0_CTRL */ "", 69260 /* QSPI_BSPI_REGISTERS_B0_STATUS */ "", 69261 /* QSPI_BSPI_REGISTERS_B1_CTRL */ "", 69262 /* QSPI_BSPI_REGISTERS_B1_STATUS */ "", 69263 /* QSPI_BSPI_REGISTERS_BITS_PER_CYCLE */ "", 69264 /* QSPI_BSPI_REGISTERS_BITS_PER_PHASE */ "", 69265 /* QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE */ "", 69266 /* QSPI_BSPI_REGISTERS_BSPI_PIO_DATA */ "", 69267 /* QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR */ "", 69268 /* QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE */ "", 69269 /* QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE */ "", 69270 /* QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE */ "", 69271 /* QSPI_BSPI_REGISTERS_BUSY_STATUS */ "", 69272 /* QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE */ "", 69273 /* QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE */ "", 69274 /* QSPI_BSPI_REGISTERS_INTR_STATUS */ "", 69275 /* QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL */ "", 69276 /* QSPI_BSPI_REGISTERS_REVISION_ID */ "", 69277 /* QSPI_BSPI_REGISTERS_SCRATCH */ "", 69278 /* QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL */ "", 69279 /* QSPI_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 69280 /* QSPI_IDM_IDM_ERROR_LOG_COMPLETE */ "", 69281 /* QSPI_IDM_IDM_ERROR_LOG_CONTROL */ "", 69282 /* QSPI_IDM_IDM_ERROR_LOG_FLAGS */ "", 69283 /* QSPI_IDM_IDM_ERROR_LOG_ID */ "", 69284 /* QSPI_IDM_IDM_ERROR_LOG_STATUS */ "", 69285 /* QSPI_IDM_IDM_INTERRUPT_STATUS */ "", 69286 /* QSPI_IDM_IDM_IO_CONTROL_DIRECT */ "", 69287 /* QSPI_IDM_IDM_IO_STATUS */ "", 69288 /* QSPI_IDM_IDM_RESET_CONTROL */ "", 69289 /* QSPI_IDM_IDM_RESET_READ_ID */ "", 69290 /* QSPI_IDM_IDM_RESET_STATUS */ "", 69291 /* QSPI_IDM_IDM_RESET_WRITE_ID */ "", 69292 /* QSPI_MSPI_CDRAM00 */ "", 69293 /* QSPI_MSPI_CDRAM01 */ "", 69294 /* QSPI_MSPI_CDRAM02 */ "", 69295 /* QSPI_MSPI_CDRAM03 */ "", 69296 /* QSPI_MSPI_CDRAM04 */ "", 69297 /* QSPI_MSPI_CDRAM05 */ "", 69298 /* QSPI_MSPI_CDRAM06 */ "", 69299 /* QSPI_MSPI_CDRAM07 */ "", 69300 /* QSPI_MSPI_CDRAM08 */ "", 69301 /* QSPI_MSPI_CDRAM09 */ "", 69302 /* QSPI_MSPI_CDRAM10 */ "", 69303 /* QSPI_MSPI_CDRAM11 */ "", 69304 /* QSPI_MSPI_CDRAM12 */ "", 69305 /* QSPI_MSPI_CDRAM13 */ "", 69306 /* QSPI_MSPI_CDRAM14 */ "", 69307 /* QSPI_MSPI_CDRAM15 */ "", 69308 /* QSPI_MSPI_CPTQP */ "", 69309 /* QSPI_MSPI_DISABLE_FLUSH_GEN */ "", 69310 /* QSPI_MSPI_ENDQP */ "", 69311 /* QSPI_MSPI_INTERRUPT_MSPI_DONE */ "", 69312 /* QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE */ "", 69313 /* QSPI_MSPI_MSPI_STATUS */ "", 69314 /* QSPI_MSPI_NEWQP */ "", 69315 /* QSPI_MSPI_RXRAM00 */ "", 69316 /* QSPI_MSPI_RXRAM01 */ "", 69317 /* QSPI_MSPI_RXRAM02 */ "", 69318 /* QSPI_MSPI_RXRAM03 */ "", 69319 /* QSPI_MSPI_RXRAM04 */ "", 69320 /* QSPI_MSPI_RXRAM05 */ "", 69321 /* QSPI_MSPI_RXRAM06 */ "", 69322 /* QSPI_MSPI_RXRAM07 */ "", 69323 /* QSPI_MSPI_RXRAM08 */ "", 69324 /* QSPI_MSPI_RXRAM09 */ "", 69325 /* QSPI_MSPI_RXRAM10 */ "", 69326 /* QSPI_MSPI_RXRAM11 */ "", 69327 /* QSPI_MSPI_RXRAM12 */ "", 69328 /* QSPI_MSPI_RXRAM13 */ "", 69329 /* QSPI_MSPI_RXRAM14 */ "", 69330 /* QSPI_MSPI_RXRAM15 */ "", 69331 /* QSPI_MSPI_RXRAM16 */ "", 69332 /* QSPI_MSPI_RXRAM17 */ "", 69333 /* QSPI_MSPI_RXRAM18 */ "", 69334 /* QSPI_MSPI_RXRAM19 */ "", 69335 /* QSPI_MSPI_RXRAM20 */ "", 69336 /* QSPI_MSPI_RXRAM21 */ "", 69337 /* QSPI_MSPI_RXRAM22 */ "", 69338 /* QSPI_MSPI_RXRAM23 */ "", 69339 /* QSPI_MSPI_RXRAM24 */ "", 69340 /* QSPI_MSPI_RXRAM25 */ "", 69341 /* QSPI_MSPI_RXRAM26 */ "", 69342 /* QSPI_MSPI_RXRAM27 */ "", 69343 /* QSPI_MSPI_RXRAM28 */ "", 69344 /* QSPI_MSPI_RXRAM29 */ "", 69345 /* QSPI_MSPI_RXRAM30 */ "", 69346 /* QSPI_MSPI_RXRAM31 */ "", 69347 /* QSPI_MSPI_SPCR2 */ "", 69348 /* QSPI_MSPI_SPCR0_LSB */ "", 69349 /* QSPI_MSPI_SPCR0_MSB */ "", 69350 /* QSPI_MSPI_SPCR1_LSB */ "", 69351 /* QSPI_MSPI_SPCR1_MSB */ "", 69352 /* QSPI_MSPI_TXRAM00 */ "", 69353 /* QSPI_MSPI_TXRAM01 */ "", 69354 /* QSPI_MSPI_TXRAM02 */ "", 69355 /* QSPI_MSPI_TXRAM03 */ "", 69356 /* QSPI_MSPI_TXRAM04 */ "", 69357 /* QSPI_MSPI_TXRAM05 */ "", 69358 /* QSPI_MSPI_TXRAM06 */ "", 69359 /* QSPI_MSPI_TXRAM07 */ "", 69360 /* QSPI_MSPI_TXRAM08 */ "", 69361 /* QSPI_MSPI_TXRAM09 */ "", 69362 /* QSPI_MSPI_TXRAM10 */ "", 69363 /* QSPI_MSPI_TXRAM11 */ "", 69364 /* QSPI_MSPI_TXRAM12 */ "", 69365 /* QSPI_MSPI_TXRAM13 */ "", 69366 /* QSPI_MSPI_TXRAM14 */ "", 69367 /* QSPI_MSPI_TXRAM15 */ "", 69368 /* QSPI_MSPI_TXRAM16 */ "", 69369 /* QSPI_MSPI_TXRAM17 */ "", 69370 /* QSPI_MSPI_TXRAM18 */ "", 69371 /* QSPI_MSPI_TXRAM19 */ "", 69372 /* QSPI_MSPI_TXRAM20 */ "", 69373 /* QSPI_MSPI_TXRAM21 */ "", 69374 /* QSPI_MSPI_TXRAM22 */ "", 69375 /* QSPI_MSPI_TXRAM23 */ "", 69376 /* QSPI_MSPI_TXRAM24 */ "", 69377 /* QSPI_MSPI_TXRAM25 */ "", 69378 /* QSPI_MSPI_TXRAM26 */ "", 69379 /* QSPI_MSPI_TXRAM27 */ "", 69380 /* QSPI_MSPI_TXRAM28 */ "", 69381 /* QSPI_MSPI_TXRAM29 */ "", 69382 /* QSPI_MSPI_TXRAM30 */ "", 69383 /* QSPI_MSPI_TXRAM31 */ "", 69384 /* QSPI_MSPI_WRITE_LOCK */ "", 69385 /* QSPI_RAF_CTRL */ "", 69386 /* QSPI_RAF_CURR_ADDR */ "", 69387 /* QSPI_RAF_ECC_LOG */ "", 69388 /* QSPI_RAF_FULLNESS */ "", 69389 /* QSPI_RAF_INTERRUPT_ECC_2B_UNCORRECTABLE_ERR_DETECTED */ "", 69390 /* QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED */ "", 69391 /* QSPI_RAF_INTERRUPT_LR_IMPATIENT */ "", 69392 /* QSPI_RAF_INTERRUPT_LR_OVERREAD */ "", 69393 /* QSPI_RAF_INTERRUPT_LR_SESSION_DONE */ "", 69394 /* QSPI_RAF_INTERRUPT_LR_TRUNCATED */ "", 69395 /* QSPI_RAF_NUM_WORDS */ "", 69396 /* QSPI_RAF_READ_DATA */ "", 69397 /* QSPI_RAF_START_ADDR */ "", 69398 /* QSPI_RAF_STATUS */ "", 69399 /* QSPI_RAF_WATERMARK */ "", 69400 /* QSPI_RAF_WORD_CNT */ "", 69401 /* QSTRUCT_FAP0_WATERMARK */ "", 69402 /* QSTRUCT_FAP1_WATERMARK */ "", 69403 /* QSTRUCT_FAP2_WATERMARK */ "", 69404 /* QSTRUCT_FAP3_WATERMARK */ "", 69405 /* QSTRUCT_FAPCONFIG */ "", 69406 /* QSTRUCT_FAPCONFIG_0 */ "", 69407 /* QSTRUCT_FAPCONFIG_1 */ "", 69408 /* QSTRUCT_FAPCONFIG_2 */ "", 69409 /* QSTRUCT_FAPCONFIG_3 */ "", 69410 /* QSTRUCT_FAPFULLRESETPOINT */ "", 69411 /* QSTRUCT_FAPFULLRESETPOINT_0 */ "", 69412 /* QSTRUCT_FAPFULLRESETPOINT_1 */ "", 69413 /* QSTRUCT_FAPFULLRESETPOINT_2 */ "", 69414 /* QSTRUCT_FAPFULLRESETPOINT_3 */ "", 69415 /* QSTRUCT_FAPFULLSETPOINT */ "", 69416 /* QSTRUCT_FAPFULLSETPOINT_0 */ "", 69417 /* QSTRUCT_FAPFULLSETPOINT_1 */ "", 69418 /* QSTRUCT_FAPFULLSETPOINT_2 */ "", 69419 /* QSTRUCT_FAPFULLSETPOINT_3 */ "", 69420 /* QSTRUCT_FAPINIT */ "", 69421 /* QSTRUCT_FAPINIT_0 */ "", 69422 /* QSTRUCT_FAPINIT_1 */ "", 69423 /* QSTRUCT_FAPINIT_2 */ "", 69424 /* QSTRUCT_FAPINIT_3 */ "", 69425 /* QSTRUCT_FAPOTPCONFIG */ "", 69426 /* QSTRUCT_FAPOTPCONFIG_0 */ "", 69427 /* QSTRUCT_FAPOTPCONFIG_1 */ "", 69428 /* QSTRUCT_FAPOTPCONFIG_2 */ "", 69429 /* QSTRUCT_FAPOTPCONFIG_3 */ "", 69430 /* QSTRUCT_FAPREADPOINTER */ "", 69431 /* QSTRUCT_FAPREADPOINTER_0 */ "", 69432 /* QSTRUCT_FAPREADPOINTER_1 */ "", 69433 /* QSTRUCT_FAPREADPOINTER_2 */ "", 69434 /* QSTRUCT_FAPREADPOINTER_3 */ "", 69435 /* QSTRUCT_FAPSTACKSTATUS */ "", 69436 /* QSTRUCT_FAPSTACKSTATUS_0 */ "", 69437 /* QSTRUCT_FAPSTACKSTATUS_1 */ "", 69438 /* QSTRUCT_FAPSTACKSTATUS_2 */ "", 69439 /* QSTRUCT_FAPSTACKSTATUS_3 */ "", 69440 /* QSTRUCT_FAP_BITMAP_ECC_DEBUG */ "", 69441 /* QSTRUCT_FAP_MEMDEBUG */ "", 69442 /* QSTRUCT_FAP_MEMDEBUG_BITMAP */ "", 69443 /* QSTRUCT_FAP_MEMDEBUG_STACK */ "", 69444 /* QSTRUCT_FAP_MEM_ECC_STATUS */ "", 69445 /* QSTRUCT_FAP_MEM_ECC_STATUS_0 */ "", 69446 /* QSTRUCT_FAP_MEM_ECC_STATUS_1 */ "", 69447 /* QSTRUCT_FAP_MEM_ECC_STATUS_2 */ "", 69448 /* QSTRUCT_FAP_MEM_ECC_STATUS_3 */ "", 69449 /* QSTRUCT_FAP_MEM_ERROR */ "", 69450 /* QSTRUCT_FAP_MEM_ERROR_MASK */ "", 69451 /* QSTRUCT_FAP_STACK_ECC_DEBUG */ "", 69452 /* QSTRUCT_FAP_WATERMARK */ "", 69453 /* QSTRUCT_INTERRUPT */ "", 69454 /* QSTRUCT_INTERRUPT_MASK */ "", 69455 /* QSTRUCT_QBLOCK_NEXT_ECC_DEBUG */ "", 69456 /* QSTRUCT_QBLOCK_NEXT_ERROR */ "", 69457 /* QSTRUCT_QBLOCK_NEXT_ERROR_0 */ "", 69458 /* QSTRUCT_QBLOCK_NEXT_ERROR_MASK */ "", 69459 /* QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0 */ "", 69460 /* QSTRUCT_QENTRY_ECC_DEBUG */ "", 69461 /* QSTRUCT_QENTRY_ERROR_0 */ "", 69462 /* QSTRUCT_QENTRY_ERROR_MASK_0 */ "", 69463 /* QSTRUCT_QENTRY_LOWER_ECC_DEBUG */ "", 69464 /* QSTRUCT_QENTRY_LOWER_ERROR */ "", 69465 /* QSTRUCT_QENTRY_LOWER_ERROR_MASK */ "", 69466 /* QSTRUCT_QENTRY_UPPER_ECC_DEBUG */ "", 69467 /* QSTRUCT_QENTRY_UPPER_ERROR */ "", 69468 /* QSTRUCT_QENTRY_UPPER_ERROR_MASK */ "", 69469 /* QUAD0_SERDES_CTRL */ "", 69470 /* QUAD0_SERDES_STATUS0 */ "", 69471 /* QUAD0_SERDES_STATUS1 */ "", 69472 /* QUAD1_SERDES_CTRL */ "", 69473 /* QUAD1_SERDES_STATUS0 */ "", 69474 /* QUAD1_SERDES_STATUS1 */ "", 69475 /* Q_SCHED_CPU_L0_NODE_CONFIG */ "", 69476 /* Q_SCHED_CPU_L1_MC_QUEUE_CONFIG */ "", 69477 /* Q_SCHED_CPU_L1_MC_QUEUE_L0_MAPPING */ "", 69478 /* Q_SCHED_CPU_L1_MC_QUEUE_MASK */ "", 69479 /* Q_SCHED_CPU_L2_NODE_CONFIG */ "", 69480 /* Q_SCHED_CPU_L3_MC_QUEUE_CONFIG */ "", 69481 /* Q_SCHED_CPU_L3_MC_QUEUE_L2_MAPPING */ "", 69482 /* Q_SCHED_CPU_L3_MC_QUEUE_MASK */ "", 69483 /* Q_SCHED_CPU_PORT_CONFIG */ "", 69484 /* Q_SCHED_DD_CHIP_CONFIG0 */ "", 69485 /* Q_SCHED_DD_CHIP_CONFIG1 */ "", 69486 /* Q_SCHED_DD_CHIP_CONFIG2 */ "", 69487 /* Q_SCHED_DD_CHIP_CONFIG3 */ "", 69488 /* Q_SCHED_DD_PORT_CONFIG */ "", 69489 /* Q_SCHED_DD_PORT_CONFIG_HIQ */ "", 69490 /* Q_SCHED_DD_TIMER */ "", 69491 /* Q_SCHED_DD_TIMER_A */ "", 69492 /* Q_SCHED_DD_TIMER_B */ "", 69493 /* Q_SCHED_DD_TIMER_ENABLE */ "", 69494 /* Q_SCHED_DD_TIMER_ENABLE_A */ "", 69495 /* Q_SCHED_DD_TIMER_ENABLE_B */ "", 69496 /* Q_SCHED_DD_TIMER_ENABLE_HIQ */ "", 69497 /* Q_SCHED_DD_TIMER_ENABLE_SPLIT0 */ "", 69498 /* Q_SCHED_DD_TIMER_ENABLE_SPLIT1 */ "", 69499 /* Q_SCHED_DD_TIMER_HIQ */ "", 69500 /* Q_SCHED_DD_TIMER_STATUS */ "", 69501 /* Q_SCHED_DD_TIMER_STATUS_A */ "", 69502 /* Q_SCHED_DD_TIMER_STATUS_A_MASK */ "", 69503 /* Q_SCHED_DD_TIMER_STATUS_B */ "", 69504 /* Q_SCHED_DD_TIMER_STATUS_B_MASK */ "", 69505 /* Q_SCHED_DD_TIMER_STATUS_HIQ */ "", 69506 /* Q_SCHED_DD_TIMER_STATUS_MASK */ "", 69507 /* Q_SCHED_DD_TIMER_STATUS_MASK_HIQ */ "", 69508 /* Q_SCHED_DD_TIMER_STATUS_MASK_SPLIT0 */ "", 69509 /* Q_SCHED_DD_TIMER_STATUS_MASK_SPLIT1 */ "", 69510 /* Q_SCHED_DD_TIMER_STATUS_SPLIT0 */ "", 69511 /* Q_SCHED_DD_TIMER_STATUS_SPLIT1 */ "", 69512 /* Q_SCHED_DEBUG_FORCE_CPU_COSMASK */ "", 69513 /* Q_SCHED_ENABLE_ECCP_MEM */ "", 69514 /* Q_SCHED_EN_COR_ERR_RPT */ "", 69515 /* Q_SCHED_INTERNAL_FLUSH_DISABLE_CONFIG */ "", 69516 /* Q_SCHED_L0_MEMORY_TM */ "", 69517 /* Q_SCHED_L0_NODE_CONFIG */ "", 69518 /* Q_SCHED_L0_NODE_CONFIG_HIQ */ "", 69519 /* Q_SCHED_L1_MC_QUEUE_CONFIG */ "", 69520 /* Q_SCHED_L1_MEMORY_TM */ "", 69521 /* Q_SCHED_L1_NODE_CONFIG */ "", 69522 /* Q_SCHED_L1_NODE_CONFIG_HIQ */ "", 69523 /* Q_SCHED_L1_UC_QUEUE_CONFIG */ "", 69524 /* Q_SCHED_L2_MEMORY_TM */ "", 69525 /* Q_SCHED_L2_NODE_CONFIG_HIQ_SPLIT0 */ "", 69526 /* Q_SCHED_L2_NODE_CONFIG_HIQ_SPLIT1 */ "", 69527 /* Q_SCHED_L2_NODE_CONFIG_NORMQ */ "Q_SCHED_L2_NODE_CONFIG", 69528 /* Q_SCHED_L3_MC_NODE_CONFIG_HIQ */ "", 69529 /* Q_SCHED_L3_MC_NODE_CONFIG_NORMQ */ "Q_SCHED_L3_MC_NODE_CONFIG", 69530 /* Q_SCHED_L3_MEMORY_TM */ "", 69531 /* Q_SCHED_L3_UC_NODE_CONFIG_HIQ */ "", 69532 /* Q_SCHED_L3_UC_NODE_CONFIG_NORMQ */ "Q_SCHED_L3_UC_NODE_CONFIG", 69533 /* Q_SCHED_PORT_CONFIG */ "", 69534 /* Q_SCHED_PORT_EMPTY_STATUS */ "", 69535 /* Q_SCHED_PORT_EMPTY_STATUS_SPLIT0 */ "", 69536 /* Q_SCHED_PORT_EMPTY_STATUS_SPLIT1 */ "", 69537 /* Q_SCHED_PORT_FLUSH */ "", 69538 /* Q_SCHED_PORT_FLUSH_SPLIT0 */ "", 69539 /* Q_SCHED_PORT_FLUSH_SPLIT1 */ "", 69540 /* Q_SCHED_RQE_SNAPSHOT */ "", 69541 /* Q_SCHED_SPECIAL_CONFIG */ "", 69542 /* R64 */ "MAC_GRx64", 69543 /* R127 */ "MAC_GRx127", 69544 /* R255 */ "MAC_GRx255", 69545 /* R511 */ "MAC_GRx511", 69546 /* R1023 */ "MAC_GRx1023", 69547 /* R1518 */ "MAC_GRx1518", 69548 /* R2047 */ "MAC_GRx2047", 69549 /* R4095 */ "MAC_GRx4095", 69550 /* R9216 */ "MAC_GRx9216", 69551 /* R16383 */ "MAC_GRx16383", 69552 /* RAICFG */ "", 69553 /* RALN */ "MAC_GRxALN", 69554 /* RAW_LINK_STATUS */ "", 69555 /* RAW_LINK_STATUS_CHANGE */ "", 69556 /* RAW_LINK_STATUS_CHANGE_MASK */ "", 69557 /* RAW_LINK_STATUS_STICKY */ "", 69558 /* RBC */ "", 69559 /* RBCA */ "MAC_GRxBCA", 69560 /* RBC_BYTE */ "", 69561 /* RBYT */ "MAC_GRxByt", 69562 /* RCHCFG_TCID_0 */ "", 69563 /* RCHCFG_TCID_1 */ "", 69564 /* RCHCFG_TCID_2 */ "", 69565 /* RCHCFG_TCID_3 */ "", 69566 /* RCHCFG_TCID_4 */ "", 69567 /* RCHCFG_TCID_5 */ "", 69568 /* RCHCFG_TCID_6 */ "", 69569 /* RCHCFG_TCID_7 */ "", 69570 /* RCHCFG_TCID_8 */ "", 69571 /* RCHCFG_TCID_9 */ "", 69572 /* RCHCFG_TCID_10 */ "", 69573 /* RCHCFG_TCID_11 */ "", 69574 /* RCHCFG_TCID_12 */ "", 69575 /* RCHCFG_TCID_13 */ "", 69576 /* RCHCFG_TCID_14 */ "", 69577 /* RCHCFG_TCID_15 */ "", 69578 /* RCOS0 */ "", 69579 /* RCOS1 */ "", 69580 /* RCOS2 */ "", 69581 /* RCOS3 */ "", 69582 /* RCOS4 */ "", 69583 /* RCOS5 */ "", 69584 /* RCOS6 */ "", 69585 /* RCOS7 */ "", 69586 /* RCOS14 */ "", 69587 /* RCOS15 */ "", 69588 /* RCOS0_BYTE */ "", 69589 /* RCOS14_BYTE */ "", 69590 /* RCOS15_BYTE */ "", 69591 /* RCOS1_BYTE */ "", 69592 /* RCOS2_BYTE */ "", 69593 /* RCOS3_BYTE */ "", 69594 /* RCOS4_BYTE */ "", 69595 /* RCOS5_BYTE */ "", 69596 /* RCOS6_BYTE */ "", 69597 /* RCOS7_BYTE */ "", 69598 /* RCVDTSO1_CID_0 */ "", 69599 /* RCVDTSO1_CID_1 */ "", 69600 /* RCVDTSO1_CID_2 */ "", 69601 /* RCVDTSO1_CID_3 */ "", 69602 /* RCVDTSO1_CID_4 */ "", 69603 /* RCVDTSO1_CID_5 */ "", 69604 /* RCVDTSO1_CID_6 */ "", 69605 /* RCVDTSO1_CID_7 */ "", 69606 /* RCVDTSO1_CID_8 */ "", 69607 /* RCVDTSO1_CID_9 */ "", 69608 /* RCVDTSO1_CID_10 */ "", 69609 /* RCVDTSO1_CID_11 */ "", 69610 /* RCVDTSO1_CID_12 */ "", 69611 /* RCVDTSO1_CID_13 */ "", 69612 /* RCVDTSO1_CID_14 */ "", 69613 /* RCVDTSO1_CID_15 */ "", 69614 /* RCVDTSO2_CID_0 */ "", 69615 /* RCVDTSO2_CID_1 */ "", 69616 /* RCVDTSO2_CID_2 */ "", 69617 /* RCVDTSO2_CID_3 */ "", 69618 /* RCVDTSO2_CID_4 */ "", 69619 /* RCVDTSO2_CID_5 */ "", 69620 /* RCVDTSO2_CID_6 */ "", 69621 /* RCVDTSO2_CID_7 */ "", 69622 /* RCVDTSO2_CID_8 */ "", 69623 /* RCVDTSO2_CID_9 */ "", 69624 /* RCVDTSO2_CID_10 */ "", 69625 /* RCVDTSO2_CID_11 */ "", 69626 /* RCVDTSO2_CID_12 */ "", 69627 /* RCVDTSO2_CID_13 */ "", 69628 /* RCVDTSO2_CID_14 */ "", 69629 /* RCVDTSO2_CID_15 */ "", 69630 /* RCV_COS_BYTES_ECC_STATUS */ "", 69631 /* RCV_COS_PKTS_ECC_STATUS */ "", 69632 /* RCV_DROP_AGG_ECC_STATUS */ "", 69633 /* RCV_DROP_BYTES_ECC_STATUS */ "", 69634 /* RCV_DROP_PKTS_ECC_STATUS */ "", 69635 /* RCV_HIGIG_CMD_STATS_ECC_STATUS */ "", 69636 /* RCV_IP_STATS_ECC_STATUS */ "", 69637 /* RCV_L2_BYTES_ECC_STATUS */ "", 69638 /* RCV_L2_PKTS_ECC_STATUS */ "", 69639 /* RCV_VLAN_STATS_ECC_STATUS */ "", 69640 /* RDBGC0 */ "", 69641 /* RDBGC1 */ "", 69642 /* RDBGC2 */ "", 69643 /* RDBGC3 */ "", 69644 /* RDBGC4 */ "", 69645 /* RDBGC5 */ "", 69646 /* RDBGC6 */ "", 69647 /* RDBGC7 */ "", 69648 /* RDBGC8 */ "", 69649 /* RDBGC0_64 */ "RDBGC0", 69650 /* RDBGC0_ECC_STATUS */ "", 69651 /* RDBGC0_SELECT */ "", 69652 /* RDBGC10_64 */ "RDBGC10", 69653 /* RDBGC10_SELECT */ "", 69654 /* RDBGC11_64 */ "RDBGC11", 69655 /* RDBGC11_SELECT */ "", 69656 /* RDBGC12_64 */ "RDBGC12", 69657 /* RDBGC12_SELECT */ "", 69658 /* RDBGC13_64 */ "RDBGC13", 69659 /* RDBGC13_SELECT */ "", 69660 /* RDBGC14_64 */ "RDBGC14", 69661 /* RDBGC14_SELECT */ "", 69662 /* RDBGC15_64 */ "RDBGC15", 69663 /* RDBGC15_SELECT */ "", 69664 /* RDBGC1_64 */ "RDBGC1", 69665 /* RDBGC1_ECC_STATUS */ "", 69666 /* RDBGC1_SELECT */ "", 69667 /* RDBGC2_64 */ "RDBGC2", 69668 /* RDBGC2_ECC_STATUS */ "", 69669 /* RDBGC2_SELECT */ "", 69670 /* RDBGC3_64 */ "RDBGC3", 69671 /* RDBGC3_ECC_STATUS */ "", 69672 /* RDBGC3_SELECT */ "", 69673 /* RDBGC4_64 */ "RDBGC4", 69674 /* RDBGC4_ECC_STATUS */ "", 69675 /* RDBGC4_SELECT */ "", 69676 /* RDBGC5_64 */ "RDBGC5", 69677 /* RDBGC5_ECC_STATUS */ "", 69678 /* RDBGC5_SELECT */ "", 69679 /* RDBGC6_64 */ "RDBGC6", 69680 /* RDBGC6_ECC_STATUS */ "", 69681 /* RDBGC6_SELECT */ "", 69682 /* RDBGC7_64 */ "RDBGC7", 69683 /* RDBGC7_ECC_STATUS */ "", 69684 /* RDBGC7_SELECT */ "", 69685 /* RDBGC8_64 */ "RDBGC8", 69686 /* RDBGC8_ECC_STATUS */ "", 69687 /* RDBGC8_SELECT */ "", 69688 /* RDBGC9_64 */ "RDBGC9", 69689 /* RDBGC9_SELECT */ "", 69690 /* RDBGC_MEM_INST0_PARITY_CONTROL */ "", 69691 /* RDBGC_MEM_INST0_PARITY_STATUS_INTR */ "", 69692 /* RDBGC_MEM_INST0_PARITY_STATUS_NACK */ "", 69693 /* RDBGC_MEM_INST1_PARITY_CONTROL */ "", 69694 /* RDBGC_MEM_INST1_PARITY_STATUS_INTR */ "", 69695 /* RDBGC_MEM_INST1_PARITY_STATUS_NACK */ "", 69696 /* RDBGC_MEM_INST2_PARITY_CONTROL */ "", 69697 /* RDBGC_MEM_INST2_PARITY_STATUS_INTR */ "", 69698 /* RDBGC_MEM_INST2_PARITY_STATUS_NACK */ "", 69699 /* RDBGC_SELECT_2 */ "", 69700 /* RDBGC_SELECT_3 */ "", 69701 /* RDBGC_SELECT_4 */ "", 69702 /* RDBGC_SELECT_5 */ "", 69703 /* RDBGC_SELECT_2_64 */ "RDBGC%d_SELECT_2", 69704 /* RDB_ALIGNER_STATUS */ "", 69705 /* RDB_CELLS_IN_USE_BANK_0 */ "", 69706 /* RDB_CELLS_IN_USE_BANK_1 */ "", 69707 /* RDB_CELLS_IN_USE_BANK_2 */ "", 69708 /* RDB_CELLS_IN_USE_BANK_3 */ "", 69709 /* RDB_CELLS_IN_USE_BANK_0_MAX */ "", 69710 /* RDB_CELLS_IN_USE_BANK_0_TRIGGER */ "", 69711 /* RDB_CELLS_IN_USE_BANK_1_MAX */ "", 69712 /* RDB_CELLS_IN_USE_BANK_1_TRIGGER */ "", 69713 /* RDB_CELLS_IN_USE_BANK_2_MAX */ "", 69714 /* RDB_CELLS_IN_USE_BANK_2_TRIGGER */ "", 69715 /* RDB_CELLS_IN_USE_BANK_3_MAX */ "", 69716 /* RDB_CELLS_IN_USE_BANK_3_TRIGGER */ "", 69717 /* RDB_CELLS_IN_USE_SKEW */ "", 69718 /* RDB_CELLS_IN_USE_SKEW_MAX */ "", 69719 /* RDB_CELLS_IN_USE_TOTAL */ "", 69720 /* RDB_CELLS_IN_USE_TOTAL_MAX */ "", 69721 /* RDB_CELLS_IN_USE_TOTAL_TRIGGER */ "", 69722 /* RDB_CELLS_IN_USE_TRIGGER_CTRL */ "", 69723 /* RDB_CNTR_DEQ_ADMIT_CTC_IP_CEL */ "", 69724 /* RDB_CNTR_DEQ_ADMIT_CTC_IP_PKT */ "", 69725 /* RDB_CNTR_DEQ_ADMIT_IP_CEL */ "", 69726 /* RDB_CNTR_DEQ_ADMIT_IP_PKT */ "", 69727 /* RDB_CNTR_DEQ_ADMIT_RDB_CEL */ "", 69728 /* RDB_CNTR_DEQ_ADMIT_REDIR_IP_CEL */ "", 69729 /* RDB_CNTR_DEQ_ADMIT_REDIR_IP_PKT */ "", 69730 /* RDB_CNTR_DEQ_DROP_IP_CEL */ "", 69731 /* RDB_CNTR_DEQ_DROP_IP_PKT */ "", 69732 /* RDB_CNTR_ENQ_ADMIT_CT_EP_CEL */ "", 69733 /* RDB_CNTR_ENQ_ADMIT_CT_PKT */ "", 69734 /* RDB_CNTR_ENQ_ADMIT_CT_RDB_CEL */ "", 69735 /* RDB_CNTR_ENQ_ADMIT_HI_EP_CEL */ "", 69736 /* RDB_CNTR_ENQ_ADMIT_HI_PKT */ "", 69737 /* RDB_CNTR_ENQ_ADMIT_HI_RDB_CEL */ "", 69738 /* RDB_CNTR_ENQ_ADMIT_LO_EP_CEL */ "", 69739 /* RDB_CNTR_ENQ_ADMIT_LO_PKT */ "", 69740 /* RDB_CNTR_ENQ_ADMIT_LO_RDB_CEL */ "", 69741 /* RDB_CNTR_ENQ_ADMIT_MID_EP_CEL */ "", 69742 /* RDB_CNTR_ENQ_ADMIT_MID_PKT */ "", 69743 /* RDB_CNTR_ENQ_ADMIT_MID_RDB_CEL */ "", 69744 /* RDB_CNTR_ENQ_DROP_CT_EP_CEL */ "", 69745 /* RDB_CNTR_ENQ_DROP_CT_PKT */ "", 69746 /* RDB_CNTR_ENQ_DROP_CT_RDB_CEL */ "", 69747 /* RDB_CNTR_ENQ_DROP_HI_EP_CEL */ "", 69748 /* RDB_CNTR_ENQ_DROP_HI_PKT */ "", 69749 /* RDB_CNTR_ENQ_DROP_HI_RDB_CEL */ "", 69750 /* RDB_CNTR_ENQ_DROP_LO_EP_CEL */ "", 69751 /* RDB_CNTR_ENQ_DROP_LO_PKT */ "", 69752 /* RDB_CNTR_ENQ_DROP_LO_RDB_CEL */ "", 69753 /* RDB_CNTR_ENQ_DROP_MID_EP_CEL */ "", 69754 /* RDB_CNTR_ENQ_DROP_MID_PKT */ "", 69755 /* RDB_CNTR_ENQ_DROP_MID_RDB_CEL */ "", 69756 /* RDB_CREDIT_ENABLE */ "", 69757 /* RDB_CUT_THRU_CELL_COUNT */ "", 69758 /* RDB_DEBUG */ "", 69759 /* RDB_DROP_STATE */ "", 69760 /* RDB_ECC_STATUS_BANK_0 */ "", 69761 /* RDB_ECC_STATUS_BANK_1 */ "", 69762 /* RDB_ECC_STATUS_BANK_2 */ "", 69763 /* RDB_ECC_STATUS_BANK_3 */ "", 69764 /* RDB_ECC_STATUS_CEL */ "", 69765 /* RDB_ECC_STATUS_CXT_AB */ "", 69766 /* RDB_ECC_STATUS_CXT_CD */ "", 69767 /* RDB_ECC_STATUS_FCP_0 */ "", 69768 /* RDB_ECC_STATUS_FCP_1 */ "", 69769 /* RDB_ECC_STATUS_FCP_2 */ "", 69770 /* RDB_ECC_STATUS_FCP_3 */ "", 69771 /* RDB_ECC_STATUS_PKT */ "", 69772 /* RDB_ENABLE */ "", 69773 /* RDB_FCP_BUF_0 */ "", 69774 /* RDB_FCP_BUF_1 */ "", 69775 /* RDB_FCP_BUF_2 */ "", 69776 /* RDB_FCP_BUF_3 */ "", 69777 /* RDB_FCP_PTRS_0 */ "", 69778 /* RDB_FCP_PTRS_1 */ "", 69779 /* RDB_FCP_PTRS_2 */ "", 69780 /* RDB_FCP_PTRS_3 */ "", 69781 /* RDB_FCP_SDW_0 */ "", 69782 /* RDB_FCP_SDW_1 */ "", 69783 /* RDB_FCP_SDW_2 */ "", 69784 /* RDB_FCP_SDW_3 */ "", 69785 /* RDB_FIRST_PASS */ "", 69786 /* RDB_FORCE_EOP_AND_STOP */ "", 69787 /* RDB_FORCE_EOP_AND_STOP_MASK */ "", 69788 /* RDB_INTR_MASK */ "", 69789 /* RDB_INTR_STATUS */ "", 69790 /* RDB_IP_CREDIT_COUNTER */ "", 69791 /* RDB_IP_STATUS */ "", 69792 /* RDB_MEM_READ_ONCE */ "", 69793 /* RDB_OUTPUT_QUEUE */ "", 69794 /* RDB_PKT_STATE */ "", 69795 /* RDB_PURGE_QUEUE */ "", 69796 /* RDB_RESERVED_CELLS */ "", 69797 /* RDB_RX_ENABLE */ "", 69798 /* RDB_SER_CONTROL */ "", 69799 /* RDB_SER_SEC_INTR */ "", 69800 /* RDB_STATUS */ "", 69801 /* RDB_THRESHOLD_HI */ "", 69802 /* RDB_THRESHOLD_LO */ "", 69803 /* RDB_THRESHOLD_MED */ "", 69804 /* RDB_TM_BANK */ "", 69805 /* RDB_TM_CEL_PKT */ "", 69806 /* RDB_TM_CXT_AB */ "", 69807 /* RDB_TM_CXT_CD */ "", 69808 /* RDB_TM_FCP */ "", 69809 /* RDECELLCNTING */ "", 69810 /* RDECELLCNTQ */ "", 69811 /* RDEDESCP_MEMDEBUG */ "", 69812 /* RDEECCPDROPCNT */ "", 69813 /* RDEERRORCODE */ "", 69814 /* RDEFREELIST */ "", 69815 /* RDEHDRMEMDEBUG */ "", 69816 /* RDEMEMDEBUG */ "", 69817 /* RDEMEMDEBUG_64 */ "RDEMEMDEBUG", 69818 /* RDEMINCELLLMTING */ "", 69819 /* RDEMINLMTCELLQ */ "", 69820 /* RDEMINLMTPKTQ */ "", 69821 /* RDEOVERLIMITDROPCNT */ "", 69822 /* RDEPARITYERRORPTR */ "", 69823 /* RDEPGMAPPING */ "", 69824 /* RDEPKTCNTQ */ "", 69825 /* RDEPORTMAXCELLEGR */ "", 69826 /* RDEQEMPTY */ "", 69827 /* RDEQFULLDROPCNT */ "", 69828 /* RDEQPKTCNT */ "", 69829 /* RDEQRST */ "", 69830 /* RDERDLIMIT */ "", 69831 /* RDERSTOFFSETCELLING */ "", 69832 /* RDERSTOFFSETCELLQ */ "", 69833 /* RDERSTOFFSETPKTQ */ "", 69834 /* RDESHRCELLLMTING */ "", 69835 /* RDESHRLMTCELLQ */ "", 69836 /* RDESHRLMTPKTQ */ "", 69837 /* RDETHDBYPASS */ "", 69838 /* RDETHDIDROPCNT */ "", 69839 /* RDETHDODROP */ "", 69840 /* RDETHDODROPCNT */ "", 69841 /* RDETOTALSHRLMTPKTEGR */ "", 69842 /* RDE_ADM_DPC_STORE_ECC_STATUS */ "", 69843 /* RDE_DEBUG_CTC_CTR */ "", 69844 /* RDE_DEBUG_DROP_CTR */ "", 69845 /* RDE_DEBUG_REDIR_CTR */ "", 69846 /* RDE_DEBUG_TM1 */ "", 69847 /* RDE_DEBUG_TM2 */ "", 69848 /* RDE_DEBUG_TM3 */ "", 69849 /* RDE_DEBUG_TM4 */ "", 69850 /* RDE_DEBUG_TM5 */ "", 69851 /* RDE_DEBUG_TM6 */ "", 69852 /* RDE_DEBUG_TM7 */ "", 69853 /* RDE_DEQ_CELL_FIFO_ECC_STATUS */ "", 69854 /* RDE_ECC_DEBUG */ "", 69855 /* RDE_GLOBAL_CONFIG */ "", 69856 /* RDE_ITE_REL_FIFO_ECC_STATUS */ "", 69857 /* RDE_POOL_SELECT */ "", 69858 /* RDE_PORT_COUNT_PACKET */ "", 69859 /* RDE_PORT_SHARED_COUNT_PACKET */ "", 69860 /* RDE_PORT_SHARED_LIMIT_PACKET */ "", 69861 /* RDE_PQE_CELL_FIFO_ECC_STATUS */ "", 69862 /* RDE_RPFAP_BITMAP_ECC_STATUS */ "", 69863 /* RDE_RPFAP_CONFIG */ "", 69864 /* RDE_RPFAP_FULLRESETPOINT */ "", 69865 /* RDE_RPFAP_FULLSETPOINT */ "", 69866 /* RDE_RPFAP_INIT */ "", 69867 /* RDE_RPFAP_LOWWATERMARK */ "", 69868 /* RDE_RPFAP_READPOINTER */ "", 69869 /* RDE_RPFAP_STACKSTATUS */ "", 69870 /* RDE_RPFAP_STACK_ECC_STATUS */ "", 69871 /* RDE_SER_COUNT */ "", 69872 /* RDE_SER_COUNT_2BIT */ "", 69873 /* RDE_SER_MASK */ "", 69874 /* RDE_SER_STATUS */ "", 69875 /* RDE_TXQ_PTRLL_ECC_STATUS */ "", 69876 /* RDE_TXQ_STATE_TBL_ECC_STATUS */ "", 69877 /* RDE_TXQ_TOQ_FIFO_TBL_ECC_STATUS */ "", 69878 /* RDISC */ "", 69879 /* RDISC_64 */ "RDISC", 69880 /* RDOS_DROP */ "", 69881 /* RDOT1Q */ "", 69882 /* RDROP */ "", 69883 /* RDVLN */ "MAC_GRxDVLN", 69884 /* REDIRECT_DROP_STATE_CELL */ "", 69885 /* REDIRECT_DROP_STATE_PACKET */ "", 69886 /* REDIRECT_XQ_DROP_STATE_PACKET */ "", 69887 /* RED_CNG_DROP_CNT */ "", 69888 /* REFRESH_COUNT_CONTROL */ "", 69889 /* REG_003300 */ "", 69890 /* REG_0020100 */ "", 69891 /* REG_0020200 */ "", 69892 /* REG_0020300 */ "", 69893 /* REG_0020400 */ "", 69894 /* REG_0020500 */ "", 69895 /* REG_0020600 */ "", 69896 /* REG_0020700 */ "", 69897 /* REG_0020800 */ "", 69898 /* REG_0020900 */ "", 69899 /* REG_0021900 */ "", 69900 /* REG_0022000 */ "", 69901 /* REG_0022100 */ "", 69902 /* REG_0022200 */ "", 69903 /* REG_0022300 */ "", 69904 /* REG_0022400 */ "", 69905 /* REG_0022500 */ "", 69906 /* REG_0022600 */ "", 69907 /* REG_0022700 */ "", 69908 /* REG_0022800 */ "", 69909 /* REG_0022900 */ "", 69910 /* REG_0023000 */ "", 69911 /* REG_0023100 */ "", 69912 /* REG_0023200 */ "", 69913 /* REG_0023300 */ "", 69914 /* REG_0023400 */ "", 69915 /* REG_0023500 */ "", 69916 /* REG_0023600 */ "", 69917 /* REG_0023700 */ "", 69918 /* REG_0023800 */ "", 69919 /* REG_0023900 */ "", 69920 /* REG_0024000 */ "", 69921 /* REG_0024100 */ "", 69922 /* REG_0024200 */ "", 69923 /* REG_0024300 */ "", 69924 /* REG_0024600 */ "", 69925 /* REG_0024800 */ "", 69926 /* REG_2028600 */ "", 69927 /* REG_2028700 */ "", 69928 /* REG_2028800 */ "", 69929 /* REG_2028900 */ "", 69930 /* REG_2029000 */ "", 69931 /* REG_2029100 */ "", 69932 /* REG_2029200 */ "", 69933 /* REG_2029300 */ "", 69934 /* REG_2029400 */ "", 69935 /* REG_2029700 */ "", 69936 /* REG_0020A00 */ "", 69937 /* REG_0020B00 */ "", 69938 /* REG_0020C00 */ "", 69939 /* REG_0020D00 */ "", 69940 /* REG_0020E00 */ "", 69941 /* REG_0020F00 */ "", 69942 /* REG_0021A00 */ "", 69943 /* REG_0021B00 */ "", 69944 /* REG_0021C00 */ "", 69945 /* REG_0021D00 */ "", 69946 /* REG_0021E00 */ "", 69947 /* REG_0021F00 */ "", 69948 /* REG_0022A00 */ "", 69949 /* REG_0022B00 */ "", 69950 /* REG_0022C00 */ "", 69951 /* REG_0022D00 */ "", 69952 /* REG_0022E00 */ "", 69953 /* REG_0022F00 */ "", 69954 /* REG_0023A00 */ "", 69955 /* REG_0023B00 */ "", 69956 /* REG_0023C00 */ "", 69957 /* REG_0023D00 */ "", 69958 /* REG_0023E00 */ "", 69959 /* REG_0023F00 */ "", 69960 /* REG_0024A00 */ "", 69961 /* REG_0024C00 */ "", 69962 /* REG_2028A00 */ "", 69963 /* REG_2028B00 */ "", 69964 /* REG_2028C00 */ "", 69965 /* REG_2028D00 */ "", 69966 /* REG_2028E00 */ "", 69967 /* REG_2028F00 */ "", 69968 /* REMOTE_CPU_DA_LS */ "", 69969 /* REMOTE_CPU_DA_MS */ "", 69970 /* REMOTE_CPU_LENGTH_TYPE */ "", 69971 /* REMOTE_PFC_CNT */ "", 69972 /* REMOTE_PFC_STATE */ "", 69973 /* REMOTE_PFC_XOFF_TC_TIME_OUT */ "", 69974 /* REMOTE_PFC_XOFF_TIME_TICK_SEL */ "", 69975 /* REORDPC_CHID_0 */ "", 69976 /* REORDPC_CHID_1 */ "", 69977 /* REORDPC_CHID_2 */ "", 69978 /* REORDPC_CHID_3 */ "", 69979 /* REORDPC_CHID_4 */ "", 69980 /* REORDPC_CHID_5 */ "", 69981 /* REORDPC_CHID_6 */ "", 69982 /* REORDPC_CHID_7 */ "", 69983 /* REORDPC_CHID_8 */ "", 69984 /* REORDPC_CHID_9 */ "", 69985 /* REORDPC_CHID_10 */ "", 69986 /* REORDPC_CHID_11 */ "", 69987 /* REORDPC_CHID_12 */ "", 69988 /* REORDPC_CHID_13 */ "", 69989 /* REORDPC_CHID_14 */ "", 69990 /* REORDPC_CHID_15 */ "", 69991 /* REORDPC_CHID_16 */ "", 69992 /* REORDPC_CHID_17 */ "", 69993 /* REORDPC_CHID_18 */ "", 69994 /* REORDPC_CHID_19 */ "", 69995 /* REORDPC_CHID_20 */ "", 69996 /* REORDPC_CHID_21 */ "", 69997 /* REORDPC_CHID_22 */ "", 69998 /* REORDPC_CHID_23 */ "", 69999 /* REORDPC_CHID_24 */ "", 70000 /* REORDPC_CHID_25 */ "", 70001 /* REORDPC_CHID_26 */ "", 70002 /* REORDPC_CHID_27 */ "", 70003 /* REORDPC_CHID_28 */ "", 70004 /* REORDPC_CHID_29 */ "", 70005 /* REORDPC_CHID_30 */ "", 70006 /* REORDPC_CHID_31 */ "", 70007 /* REORDPC_CHID_32 */ "", 70008 /* REORDPC_CHID_33 */ "", 70009 /* REORDPC_CHID_34 */ "", 70010 /* REORDPC_CHID_35 */ "", 70011 /* REORDPC_CHID_36 */ "", 70012 /* REORDPC_CHID_37 */ "", 70013 /* REORDPC_CHID_38 */ "", 70014 /* REORDPC_CHID_39 */ "", 70015 /* REORDPC_CHID_40 */ "", 70016 /* REORDPC_CHID_41 */ "", 70017 /* REORDPC_CHID_42 */ "", 70018 /* REORDPC_CHID_43 */ "", 70019 /* REORDPC_CHID_44 */ "", 70020 /* REORDPC_CHID_45 */ "", 70021 /* REORDPC_CHID_46 */ "", 70022 /* REORDPC_CHID_47 */ "", 70023 /* REORDPC_CHID_48 */ "", 70024 /* REORDPC_CHID_49 */ "", 70025 /* REORDPC_CHID_50 */ "", 70026 /* REORDPC_CHID_51 */ "", 70027 /* REORDPC_CHID_52 */ "", 70028 /* REORDPC_CHID_53 */ "", 70029 /* REORDPC_CHID_54 */ "", 70030 /* REORDPC_CHID_55 */ "", 70031 /* REORDPC_CHID_56 */ "", 70032 /* REORDPC_CHID_57 */ "", 70033 /* REORDPC_CHID_58 */ "", 70034 /* REORDPC_CHID_59 */ "", 70035 /* REORDPC_CHID_60 */ "", 70036 /* REORDPC_CHID_61 */ "", 70037 /* REORDPC_CHID_62 */ "", 70038 /* REORDPC_CHID_63 */ "", 70039 /* REPBUF_MEMORY_DEBUG_TM */ "", 70040 /* REPLHEADMEMDEBUG */ "", 70041 /* REPLICATION_FIFO_DEBUG_TM */ "", 70042 /* REPLIST_MEMDEBUG */ "", 70043 /* REPL_GROUP_INFO0_MEM_DEBUG_TM */ "", 70044 /* REPL_GROUP_INFO1_MEM_DEBUG_TM */ "", 70045 /* REPL_HEAD_PTR_REPLACE */ "REPL_HEAD_PTR_FLUSH", 70046 /* REP_FIFO_SNAPSHOT_DONE */ "", 70047 /* REP_FIFO_SNAPSHOT_EN */ "", 70048 /* REP_FIFO_SNAPSHOT_INIT */ "", 70049 /* REP_ID_REMAP_CONTROL */ "", 70050 /* RERPKT */ "MAC_GRxFrErr", 70051 /* RESCAL1_CTRL_0 */ "", 70052 /* RESCAL1_STATUS_0 */ "", 70053 /* RESCAL2_CTRL_0 */ "", 70054 /* RESCAL2_STATUS_0 */ "", 70055 /* RESCAL_CTRL_0 */ "", 70056 /* RESCAL_STATUS_0 */ "", 70057 /* RESET_ON_EMPTY_MAX_64 */ "RESET_ON_EMPTY_MAXBUCKET", 70058 /* REVCD */ "", 70059 /* RFCR */ "MAC_GRxFCR", 70060 /* RFCS */ "MAC_GRxFCS", 70061 /* RFLR */ "MAC_GRxFLR", 70062 /* RFRG */ "MAC_GRxFRG", 70063 /* RH_ECMP1_DROPS */ "", 70064 /* RH_ECMP1_DROPS_PIPE0 */ "", 70065 /* RH_ECMP1_DROPS_PIPE1 */ "", 70066 /* RH_ECMP2_DROPS */ "", 70067 /* RH_ECMP2_DROPS_PIPE0 */ "", 70068 /* RH_ECMP2_DROPS_PIPE1 */ "", 70069 /* RH_ECMP_ETHERTYPE_ELIGIBILITY_CONTROL */ "", 70070 /* RH_ECMP_FLOWSET_BANK_SEL */ "", 70071 /* RH_HGT_DROPS */ "", 70072 /* RH_HGT_DROPS_PIPE0 */ "", 70073 /* RH_HGT_DROPS_PIPE1 */ "", 70074 /* RH_HGT_ETHERTYPE_ELIGIBILITY_CONTROL */ "", 70075 /* RH_HGT_ETHERTYPE_ELIGIBILITY_CONTROL_PIPE0 */ "", 70076 /* RH_HGT_ETHERTYPE_ELIGIBILITY_CONTROL_PIPE1 */ "", 70077 /* RH_LAG_DROPS */ "", 70078 /* RH_LAG_DROPS_PIPE0 */ "", 70079 /* RH_LAG_DROPS_PIPE1 */ "", 70080 /* RH_LAG_ETHERTYPE_ELIGIBILITY_CONTROL */ "", 70081 /* RH_LAG_ETHERTYPE_ELIGIBILITY_CONTROL_PIPE0 */ "", 70082 /* RH_LAG_ETHERTYPE_ELIGIBILITY_CONTROL_PIPE1 */ "", 70083 /* RIPC4 */ "", 70084 /* RIPC6 */ "", 70085 /* RIPC4_64 */ "RIPC4", 70086 /* RIPC4_HDR_ERR */ "", 70087 /* RIPC4_MACSEC_HDR_ERR */ "", 70088 /* RIPC4_MACSEC_PLAIN */ "", 70089 /* RIPC4_PLAIN */ "", 70090 /* RIPC6_64 */ "RIPC6", 70091 /* RIPD4 */ "", 70092 /* RIPD6 */ "", 70093 /* RIPD4_64 */ "RIPD4", 70094 /* RIPD6_64 */ "RIPD6", 70095 /* RIPHCKS */ "", 70096 /* RIPHCKS_ECC_STATUS */ "", 70097 /* RIPHE4 */ "", 70098 /* RIPHE6 */ "", 70099 /* RIPHE4_64 */ "RIPHE4", 70100 /* RIPHE6_64 */ "RIPHE6", 70101 /* RJBR */ "MAC_GRxJBR", 70102 /* RMC */ "", 70103 /* RMCA */ "MAC_GRxMCA", 70104 /* RMCRC */ "MAC_GRxMCRC", 70105 /* RMC_BYTE */ "", 70106 /* RMEP_ECCP_CONTROL */ "", 70107 /* RMEP_MA_STATE_REFRESH_INDEX */ "", 70108 /* RMEP_PARITY_CONTROL */ "", 70109 /* RMEP_PARITY_STATUS */ "", 70110 /* RMEP_PARITY_STATUS_INTR */ "", 70111 /* RMEP_PARITY_STATUS_NACK */ "", 70112 /* RMGV */ "MAC_GRx1522", 70113 /* RMTUE */ "MAC_GRxMTUE", 70114 /* ROE_UDP_PORT */ "", 70115 /* ROM_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 70116 /* ROM_S0_IDM_ERROR_LOG_COMPLETE */ "", 70117 /* ROM_S0_IDM_ERROR_LOG_CONTROL */ "", 70118 /* ROM_S0_IDM_ERROR_LOG_FLAGS */ "", 70119 /* ROM_S0_IDM_ERROR_LOG_ID */ "", 70120 /* ROM_S0_IDM_ERROR_LOG_STATUS */ "", 70121 /* ROM_S0_IDM_INTERRUPT_STATUS */ "", 70122 /* ROM_S0_IDM_IO_CONTROL_DIRECT */ "", 70123 /* ROM_S0_IDM_IO_STATUS */ "", 70124 /* ROM_S0_IDM_RESET_CONTROL */ "", 70125 /* ROM_S0_IDM_RESET_READ_ID */ "", 70126 /* ROM_S0_IDM_RESET_STATUS */ "", 70127 /* ROM_S0_IDM_RESET_WRITE_ID */ "", 70128 /* ROVR */ "MAC_GRxOVR", 70129 /* RPARITYD */ "", 70130 /* RPFC0 */ "MAC_GRxPFCP0", 70131 /* RPFC1 */ "MAC_GRxPFCP1", 70132 /* RPFC2 */ "MAC_GRxPFCP2", 70133 /* RPFC3 */ "MAC_GRxPFCP3", 70134 /* RPFC4 */ "MAC_GRxPFCP4", 70135 /* RPFC5 */ "MAC_GRxPFCP5", 70136 /* RPFC6 */ "MAC_GRxPFCP6", 70137 /* RPFC7 */ "MAC_GRxPFCP7", 70138 /* RPFCOFF0 */ "MAC_GRxPFCOFF0", 70139 /* RPFCOFF1 */ "MAC_GRxPFCOFF1", 70140 /* RPFCOFF2 */ "MAC_GRxPFCOFF2", 70141 /* RPFCOFF3 */ "MAC_GRxPFCOFF3", 70142 /* RPFCOFF4 */ "MAC_GRxPFCOFF4", 70143 /* RPFCOFF5 */ "MAC_GRxPFCOFF5", 70144 /* RPFCOFF6 */ "MAC_GRxPFCOFF6", 70145 /* RPFCOFF7 */ "MAC_GRxPFCOFF7", 70146 /* RPFCOFF_0 */ "", 70147 /* RPFCOFF_1 */ "", 70148 /* RPFCOFF_2 */ "", 70149 /* RPFCOFF_3 */ "", 70150 /* RPFCOFF_4 */ "", 70151 /* RPFCOFF_5 */ "", 70152 /* RPFCOFF_6 */ "", 70153 /* RPFCOFF_7 */ "", 70154 /* RPFC_0 */ "", 70155 /* RPFC_1 */ "", 70156 /* RPFC_2 */ "", 70157 /* RPFC_3 */ "", 70158 /* RPFC_4 */ "", 70159 /* RPFC_5 */ "", 70160 /* RPFC_6 */ "", 70161 /* RPFC_7 */ "", 70162 /* RPKT */ "MAC_GRxPkt", 70163 /* RPOK */ "MAC_GRxPOK", 70164 /* RPORTD */ "", 70165 /* RPORTD_64 */ "RPORTD", 70166 /* RPRM */ "MAC_GRxPRM", 70167 /* RPROG0 */ "CLG2MIB_GRxProg0", 70168 /* RPROG1 */ "CLG2MIB_GRxProg1", 70169 /* RPROG2 */ "CLG2MIB_GRxProg2", 70170 /* RPROG3 */ "CLG2MIB_GRxProg3", 70171 /* RQE_DEBUG */ "", 70172 /* RQE_DEBUG_FREE_LIST_MEM */ "", 70173 /* RQE_DEBUG_FREE_LIST_OOP_CLR */ "", 70174 /* RQE_DEBUG_SAME_PORT_THDM_ERROR */ "", 70175 /* RQE_DEBUG_THDM_CHOKE_COUNTER */ "", 70176 /* RQE_DEBUG_TM1 */ "", 70177 /* RQE_DEBUG_TM2 */ "", 70178 /* RQE_DEBUG_TM3 */ "", 70179 /* RQE_DEBUG_TM4 */ "", 70180 /* RQE_DEBUG_TM5 */ "", 70181 /* RQE_DEBUG_TM6 */ "", 70182 /* RQE_DEBUG_TM7 */ "", 70183 /* RQE_DEBUG_TM8 */ "", 70184 /* RQE_DEBUG_TM9 */ "", 70185 /* RQE_DEBUG_TM_DCM1 */ "", 70186 /* RQE_DEBUG_TM_DCM2 */ "", 70187 /* RQE_DEBUG_TM_DCM3 */ "", 70188 /* RQE_DEBUG_TM_DCM4 */ "", 70189 /* RQE_DEBUG_TM_DCM5 */ "", 70190 /* RQE_DEBUG_TM_DCM6 */ "", 70191 /* RQE_DEBUG_TM_DCM7 */ "", 70192 /* RQE_ENABLE_SINGLE_PACKET_MODE */ "", 70193 /* RQE_ENABLE_THDM_PAUSE */ "", 70194 /* RQE_EN_COR_ERR_RPT */ "", 70195 /* RQE_EXTQ_REPLICATION_COUNT */ "", 70196 /* RQE_EXTQ_REPLICATION_LIMIT */ "", 70197 /* RQE_GLOBAL_CONFIG */ "", 70198 /* RQE_GLOBAL_DEBUG_STATUS */ "", 70199 /* RQE_MAXBUCKETCONFIG_L0_Q */ "", 70200 /* RQE_MAXBUCKETCONFIG_L1_Q */ "", 70201 /* RQE_MAXBUCKET_L0_Q */ "", 70202 /* RQE_MAXBUCKET_L1_Q */ "", 70203 /* RQE_MAX_SHAPER_EN */ "", 70204 /* RQE_MAX_SHAPER_LIMIT_COUNT */ "", 70205 /* RQE_MAX_SHAPER_RATE */ "", 70206 /* RQE_MAX_SHAPER_THRESHOLD */ "", 70207 /* RQE_MAX_SHAPER_THRESHOLD_CLEAR */ "", 70208 /* RQE_MIRROR_CONFIG */ "", 70209 /* RQE_PARITYERRORPOINTER1 */ "", 70210 /* RQE_PARITYERRORPOINTER2 */ "", 70211 /* RQE_PARITYERRORPOINTER3 */ "", 70212 /* RQE_PARITYERRORPOINTER4 */ "", 70213 /* RQE_PARITYERRORPOINTER5 */ "", 70214 /* RQE_PORT_CONFIG */ "", 70215 /* RQE_PP_PORT_CONFIG */ "RQE_PORT_CONFIG", 70216 /* RQE_PRIORITY_QUEUE_ENTRY */ "", 70217 /* RQE_PRIORITY_QUEUE_HEAD */ "", 70218 /* RQE_PRIORITY_QUEUE_TAIL */ "", 70219 /* RQE_PRIORITY_SCHEDULING_TYPE */ "", 70220 /* RQE_PRIORITY_WERR_WEIGHT */ "", 70221 /* RQE_QMGR_DEBUG0 */ "", 70222 /* RQE_QMGR_DEBUG1 */ "", 70223 /* RQE_QMGR_DEBUG2 */ "", 70224 /* RQE_QMGR_DEBUG3 */ "", 70225 /* RQE_QMGR_DEBUG4 */ "", 70226 /* RQE_QUEUE_OFFSET */ "", 70227 /* RQE_REPLICATION_ENTRY_COUNT */ "", 70228 /* RQE_REPLICATION_ENTRY_THRESHOLD */ "", 70229 /* RQE_REP_BUF_THRESHOLD */ "", 70230 /* RQE_REP_BUF_WATERMARK */ "", 70231 /* RQE_REP_BUF_WATERMARK_CLEAR */ "", 70232 /* RQE_SCHEDULER_CONFIG */ "", 70233 /* RQE_SCHEDULER_WEIGHT_L0_QUEUE */ "", 70234 /* RQE_SCHEDULER_WEIGHT_L1_QUEUE */ "", 70235 /* RQE_SER_COUNT */ "", 70236 /* RQE_SER_COUNT_2BIT */ "", 70237 /* RQE_SER_MASK */ "", 70238 /* RQE_SER_STATUS */ "", 70239 /* RQE_WERR_MAXSC_CLEAR */ "", 70240 /* RQE_WERR_MAXSC_RESET */ "", 70241 /* RQE_WERR_WORKING_COUNTS */ "", 70242 /* RQE_WERR_WORKING_COUNTS_CLEAR */ "", 70243 /* RQE_WORK_FIFO_CREDIT_COUNT */ "", 70244 /* RQE_WORK_FIFO_ENTRY_COUNT */ "", 70245 /* RQE_WORK_FIFO_ENTRY_THRESHOLD */ "", 70246 /* RQE_WORK_QUEUE_DEBUG_STATUS */ "", 70247 /* RQINQ */ "", 70248 /* RQP_AGING_STUCK_CONTEXTS */ "", 70249 /* RQP_BUBBLE_TRIGGER */ "", 70250 /* RQP_CELL_DECODER_DEBUG_COUNTERS */ "", 70251 /* RQP_CRC_DEBUG_COUNTERS */ "", 70252 /* RQP_CRPS_BUBBLE_REQ_CNTR */ "", 70253 /* RQP_CUP_DEBUG_COUNTERS */ "", 70254 /* RQP_DBG_CDC_ERR_MASK_DIS_CNT */ "", 70255 /* RQP_DBG_CUP_ERR_MASK_DIS_CNT */ "", 70256 /* RQP_DBG_PRP_SOP_DISCARD_MASK_DIS_CNT */ "", 70257 /* RQP_DBG_SOURCE_MASK_DIS_CNT */ "", 70258 /* RQP_ECC_1B_ERR_CNT */ "", 70259 /* RQP_ECC_2B_ERR_CNT */ "", 70260 /* RQP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 70261 /* RQP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 70262 /* RQP_ECC_INTERRUPT_REGISTER */ "", 70263 /* RQP_ECC_INTERRUPT_REGISTER_MASK */ "", 70264 /* RQP_ECC_INTERRUPT_REGISTER_TEST */ "", 70265 /* RQP_EMR_BUBBLE_CONFIGURATION */ "", 70266 /* RQP_EMR_DISCARDS_PACKET_COUNTER */ "", 70267 /* RQP_EMR_GENERAL_CONFIGURATION */ "", 70268 /* RQP_EMR_MC_HIGH_DISCARDS_COUNTER */ "", 70269 /* RQP_EMR_MC_HIGH_PACKET_COUNTER */ "", 70270 /* RQP_EMR_MC_LOW_DISCARDS_COUNTER */ "", 70271 /* RQP_EMR_MC_LOW_PACKET_COUNTER */ "", 70272 /* RQP_EMR_TDM_PACKET_COUNTER */ "", 70273 /* RQP_EMR_UNICAST_PACKET_COUNTER */ "", 70274 /* RQP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 70275 /* RQP_ERPP_BUBBLE_REQ_CNTR */ "", 70276 /* RQP_ERROR_INITIATION_DATA */ "", 70277 /* RQP_FILETER_DEBUG_COUNTERS */ "", 70278 /* RQP_FRF_FIFO_DEBUG */ "", 70279 /* RQP_GENERAL_RQP_CONFIG */ "", 70280 /* RQP_GENERAL_RQP_DEBUG_CONFIG */ "", 70281 /* RQP_GTIMER_CONFIGURATION */ "", 70282 /* RQP_GTIMER_CYCLE */ "", 70283 /* RQP_INDIRECT_COMMAND */ "", 70284 /* RQP_INDIRECT_COMMAND_ADDRESS */ "", 70285 /* RQP_INDIRECT_COMMAND_RD_DATA */ "", 70286 /* RQP_INDIRECT_COMMAND_WR_DATA */ "", 70287 /* RQP_INDIRECT_FORCE_BUBBLE */ "", 70288 /* RQP_INTERRUPT_MASK_REGISTER */ "", 70289 /* RQP_INTERRUPT_REGISTER */ "", 70290 /* RQP_INTERRUPT_REGISTER_TEST */ "", 70291 /* RQP_LAST_CDC_1_HEADER */ "", 70292 /* RQP_LAST_CDC_HEADER */ "", 70293 /* RQP_LAST_CUP_INFO */ "", 70294 /* RQP_LAST_PRP_SOP_HEADER */ "", 70295 /* RQP_LAST_PRP_TDM_HEADER */ "", 70296 /* RQP_LAST_REASSEMBLY_ERROR_MCID */ "", 70297 /* RQP_MAXIMUM_AND_MINIMUM_PACKET_SIZE */ "", 70298 /* RQP_MC_PRIORITY_LOOKUP_TABLE */ "", 70299 /* RQP_MULTICAST_FIFOS_ALMOST_FULL_CONFIG */ "", 70300 /* RQP_MULTICAST_FIFOS_CURR_LEVEL */ "", 70301 /* RQP_MULTICAST_FIFOS_DEPTH */ "", 70302 /* RQP_MULTICAST_FIFOS_FULL_CONFIG */ "", 70303 /* RQP_MULTICAST_FIFOS_MAX_LEVEL */ "", 70304 /* RQP_PACKET_REASSEMBLY_INTERRUPT_REGISTER */ "", 70305 /* RQP_PACKET_REASSEMBLY_INTERRUPT_REGISTER_MASK */ "", 70306 /* RQP_PARITY_ERR_CNT */ "", 70307 /* RQP_PAR_ERR_MEM_MASK */ "", 70308 /* RQP_PCMI_0 */ "", 70309 /* RQP_PCMI_1 */ "", 70310 /* RQP_PCMI_2 */ "", 70311 /* RQP_PCMI_3 */ "", 70312 /* RQP_PCMI_4 */ "", 70313 /* RQP_PCMI_0_S */ "", 70314 /* RQP_PCMI_0_T */ "", 70315 /* RQP_PCMI_1_S */ "", 70316 /* RQP_PCMI_1_T */ "", 70317 /* RQP_PCMI_2_S */ "", 70318 /* RQP_PCMI_2_T */ "", 70319 /* RQP_PCMI_3_S */ "", 70320 /* RQP_PCMI_3_T */ "", 70321 /* RQP_PCMI_4_S */ "", 70322 /* RQP_PCMI_4_T */ "", 70323 /* RQP_PKT_REAS_INT_REG_TEST */ "", 70324 /* RQP_PRP_DEBUG_COUNTERS */ "", 70325 /* RQP_PRS_CELL_COUNTERS */ "", 70326 /* RQP_PRS_CONFIGURATION */ "", 70327 /* RQP_PRS_DEBUG_CONFIGURATION */ "", 70328 /* RQP_PRS_DROP_CELL_CNT */ "", 70329 /* RQP_PRS_EGQ_COUNTERS */ "", 70330 /* RQP_PRS_FAB_EMPTY_COUNTERS */ "", 70331 /* RQP_PRS_FDA_COUNTERS */ "", 70332 /* RQP_PRS_FIFO_DEBUG */ "", 70333 /* RQP_PRS_INTERRUPT_REGISTER */ "", 70334 /* RQP_PRS_INTERRUPT_REGISTER_MASK */ "", 70335 /* RQP_PRS_INTERRUPT_REGISTER_TEST */ "", 70336 /* RQP_PRS_RQP_NOT_READY */ "", 70337 /* RQP_PRS_RQP_NOT_READY_AND_AF */ "", 70338 /* RQP_PRS_SRC_CHANGE_CNT */ "", 70339 /* RQP_RCM_DEBUG */ "", 70340 /* RQP_RCM_DEBUG_COUNTERS */ "", 70341 /* RQP_RCM_STATIC_CONFIG */ "", 70342 /* RQP_REG_0041 */ "", 70343 /* RQP_REG_00A4 */ "", 70344 /* RQP_REG_00A6 */ "", 70345 /* RQP_REG_00AA */ "", 70346 /* RQP_REG_00C2 */ "", 70347 /* RQP_REG_00C3 */ "", 70348 /* RQP_REG_00C5 */ "", 70349 /* RQP_REG_00C6 */ "", 70350 /* RQP_RELEASE_STUCK_CONTEXT */ "", 70351 /* RQP_RESERVED_MIRROR_ADDR */ "", 70352 /* RQP_RESERVED_MTCD */ "", 70353 /* RQP_RESERVED_MTCP */ "", 70354 /* RQP_RESERVED_SPARE_0 */ "", 70355 /* RQP_RESERVED_SPARE_1 */ "", 70356 /* RQP_RESERVED_SPARE_2 */ "", 70357 /* RQP_RESERVED_SPARE_3 */ "", 70358 /* RQP_RQP_AGING_CONFIG */ "", 70359 /* RQP_RQP_BLOCK_INIT_STATUS */ "", 70360 /* RQP_SBUS_BROADCAST_ID */ "", 70361 /* RQP_SBUS_LAST_IN_CHAIN */ "", 70362 /* RQP_SOURCE_IS_JR_2_BITMAP_1023_512 */ "", 70363 /* RQP_SOURCE_IS_JR_2_BITMAP_1535_1024 */ "", 70364 /* RQP_SOURCE_IS_JR_2_BITMAP_2047_1536 */ "", 70365 /* RQP_SOURCE_IS_JR_2_BITMAP_511_0 */ "", 70366 /* RQP_SPECIAL_CLOCK_CONTROLS */ "", 70367 /* RQP_TDM_GENERAL_CONFIGURATION */ "", 70368 /* RRBYT */ "MAC_RxRBYT", 70369 /* RREPLY */ "XLMIB_GRxReply", 70370 /* RRPKT */ "MAC_GRxRPKT", 70371 /* RR_COUNTER_1 */ "", 70372 /* RR_COUNTER_2 */ "", 70373 /* RSCHCRC */ "MAC_GRxSCHCRC", 70374 /* RSEL1_MISC_CONTROL */ "", 70375 /* RSEL1_RAM_CONTROL */ "", 70376 /* RSEL1_RAM_DBGCTRL */ "RSEL1_RAM_CONTROL", 70377 /* RSEL1_RAM_DBGCTRL4 */ "RSEL1_RAM_CONTROL4", 70378 /* RSEL1_RAM_DBGCTRL0_64 */ "RSEL1_RAM_CONTROL0_64", 70379 /* RSEL1_RAM_DBGCTRL0_64_PIPE0 */ "RSEL1_RAM_CONTROL0_64_PIPE0", 70380 /* RSEL1_RAM_DBGCTRL0_64_PIPE1 */ "RSEL1_RAM_CONTROL0_64_PIPE1", 70381 /* RSEL1_RAM_DBGCTRL1_64 */ "RSEL1_RAM_CONTROL1_64", 70382 /* RSEL1_RAM_DBGCTRL1_64_PIPE0 */ "RSEL1_RAM_CONTROL1_64_PIPE0", 70383 /* RSEL1_RAM_DBGCTRL1_64_PIPE1 */ "RSEL1_RAM_CONTROL1_64_PIPE1", 70384 /* RSEL1_RAM_DBGCTRL2_64 */ "RSEL1_RAM_CONTROL2_64", 70385 /* RSEL1_RAM_DBGCTRL2_64_PIPE0 */ "RSEL1_RAM_CONTROL2_64_PIPE0", 70386 /* RSEL1_RAM_DBGCTRL2_64_PIPE1 */ "RSEL1_RAM_CONTROL2_64_PIPE1", 70387 /* RSEL1_RAM_DBGCTRL2_64_PIPE2 */ "RSEL1_RAM_CONTROL2_64_PIPE2", 70388 /* RSEL1_RAM_DBGCTRL2_64_PIPE3 */ "RSEL1_RAM_CONTROL2_64_PIPE3", 70389 /* RSEL1_RAM_DBGCTRL3_64 */ "RSEL1_RAM_CONTROL3_64", 70390 /* RSEL1_RAM_DBGCTRL3_64_PIPE0 */ "RSEL1_RAM_CONTROL3_64_PIPE0", 70391 /* RSEL1_RAM_DBGCTRL3_64_PIPE1 */ "RSEL1_RAM_CONTROL3_64_PIPE1", 70392 /* RSEL1_RAM_DBGCTRL3_64_PIPE2 */ "RSEL1_RAM_CONTROL3_64_PIPE2", 70393 /* RSEL1_RAM_DBGCTRL3_64_PIPE3 */ "RSEL1_RAM_CONTROL3_64_PIPE3", 70394 /* RSEL1_RAM_DBGCTRL4_64 */ "RSEL1_RAM_CONTROL4_64", 70395 /* RSEL1_RAM_DBGCTRL4_PIPE0 */ "RSEL1_RAM_CONTROL4_PIPE0", 70396 /* RSEL1_RAM_DBGCTRL4_PIPE1 */ "RSEL1_RAM_CONTROL4_PIPE1", 70397 /* RSEL1_RAM_DBGCTRL4_PIPE2 */ "RSEL1_RAM_CONTROL4_PIPE2", 70398 /* RSEL1_RAM_DBGCTRL4_PIPE3 */ "RSEL1_RAM_CONTROL4_PIPE3", 70399 /* RSEL1_RAM_DBGCTRL_2 */ "RSEL1_RAM_CONTROL_2", 70400 /* RSEL1_RAM_DBGCTRL_3 */ "RSEL1_RAM_CONTROL_3", 70401 /* RSEL1_RAM_DBGCTRL_4 */ "RSEL1_RAM_CONTROL_4", 70402 /* RSEL1_RAM_DBGCTRL_5 */ "RSEL1_RAM_CONTROL_5", 70403 /* RSEL1_RAM_DBGCTRL_6 */ "RSEL1_RAM_CONTROL_6", 70404 /* RSEL1_RAM_DBGCTRL_7 */ "RSEL1_RAM_CONTROL_7", 70405 /* RSEL1_RAM_DBGCTRL_64 */ "RSEL1_RAM_CONTROL_64", 70406 /* RSEL1_RAM_DBGCTRL_64_PIPE0 */ "RSEL1_RAM_CONTROL_64_PIPE0", 70407 /* RSEL1_RAM_DBGCTRL_64_PIPE1 */ "RSEL1_RAM_CONTROL_64_PIPE1", 70408 /* RSEL1_RAM_DBGCTRL_64_PIPE2 */ "RSEL1_RAM_CONTROL_64_PIPE2", 70409 /* RSEL1_RAM_DBGCTRL_64_PIPE3 */ "RSEL1_RAM_CONTROL_64_PIPE3", 70410 /* RSEL2_CAM_DBGCTRL */ "RSEL2_CAM_CONTROL", 70411 /* RSEL2_CAM_DBGCTRL_PIPE0 */ "RSEL2_CAM_CONTROL_PIPE0", 70412 /* RSEL2_CAM_DBGCTRL_PIPE1 */ "RSEL2_CAM_CONTROL_PIPE1", 70413 /* RSEL2_CAM_DBGCTRL_PIPE2 */ "RSEL2_CAM_CONTROL_PIPE2", 70414 /* RSEL2_CAM_DBGCTRL_PIPE3 */ "RSEL2_CAM_CONTROL_PIPE3", 70415 /* RSEL2_HW_CONTROL */ "", 70416 /* RSEL2_RAM_CONTROL */ "", 70417 /* RSEL2_RAM_CONTROL_2 */ "", 70418 /* RSEL2_RAM_CONTROL_3 */ "", 70419 /* RSEL2_RAM_DBGCTRL */ "RSEL2_RAM_CONTROL", 70420 /* RSEL2_RAM_DBGCTRL5 */ "RSEL2_RAM_CONTROL5", 70421 /* RSEL2_RAM_DBGCTRL2_64 */ "RSEL2_RAM_CONTROL2_64", 70422 /* RSEL2_RAM_DBGCTRL2_64_PIPE0 */ "RSEL2_RAM_CONTROL2_64_PIPE0", 70423 /* RSEL2_RAM_DBGCTRL2_64_PIPE1 */ "RSEL2_RAM_CONTROL2_64_PIPE1", 70424 /* RSEL2_RAM_DBGCTRL2_64_PIPE2 */ "RSEL2_RAM_CONTROL2_64_PIPE2", 70425 /* RSEL2_RAM_DBGCTRL2_64_PIPE3 */ "RSEL2_RAM_CONTROL2_64_PIPE3", 70426 /* RSEL2_RAM_DBGCTRL3_64 */ "RSEL2_RAM_CONTROL3_64", 70427 /* RSEL2_RAM_DBGCTRL3_64_PIPE0 */ "RSEL2_RAM_CONTROL3_64_PIPE0", 70428 /* RSEL2_RAM_DBGCTRL3_64_PIPE1 */ "RSEL2_RAM_CONTROL3_64_PIPE1", 70429 /* RSEL2_RAM_DBGCTRL3_64_PIPE2 */ "RSEL2_RAM_CONTROL3_64_PIPE2", 70430 /* RSEL2_RAM_DBGCTRL3_64_PIPE3 */ "RSEL2_RAM_CONTROL3_64_PIPE3", 70431 /* RSEL2_RAM_DBGCTRL4_64 */ "RSEL2_RAM_CONTROL4_64", 70432 /* RSEL2_RAM_DBGCTRL4_64_PIPE0 */ "RSEL2_RAM_CONTROL4_64_PIPE0", 70433 /* RSEL2_RAM_DBGCTRL4_64_PIPE1 */ "RSEL2_RAM_CONTROL4_64_PIPE1", 70434 /* RSEL2_RAM_DBGCTRL4_64_PIPE2 */ "RSEL2_RAM_CONTROL4_64_PIPE2", 70435 /* RSEL2_RAM_DBGCTRL4_64_PIPE3 */ "RSEL2_RAM_CONTROL4_64_PIPE3", 70436 /* RSEL2_RAM_DBGCTRL5_PIPE0 */ "RSEL2_RAM_CONTROL5_PIPE0", 70437 /* RSEL2_RAM_DBGCTRL5_PIPE1 */ "RSEL2_RAM_CONTROL5_PIPE1", 70438 /* RSEL2_RAM_DBGCTRL5_PIPE2 */ "RSEL2_RAM_CONTROL5_PIPE2", 70439 /* RSEL2_RAM_DBGCTRL5_PIPE3 */ "RSEL2_RAM_CONTROL5_PIPE3", 70440 /* RSEL2_RAM_DBGCTRL_1 */ "RSEL2_RAM_CONTROL_1_64", 70441 /* RSEL2_RAM_DBGCTRL_64 */ "RSEL2_RAM_CONTROL_64", 70442 /* RSEL2_RAM_DBGCTRL_64_PIPE0 */ "RSEL2_RAM_CONTROL_64_PIPE0", 70443 /* RSEL2_RAM_DBGCTRL_64_PIPE1 */ "RSEL2_RAM_CONTROL_64_PIPE1", 70444 /* RSEL2_RAM_DBGCTRL_64_PIPE2 */ "RSEL2_RAM_CONTROL_64_PIPE2", 70445 /* RSEL2_RAM_DBGCTRL_64_PIPE3 */ "RSEL2_RAM_CONTROL_64_PIPE3", 70446 /* RSEL2_RAM_LP_CONTROL */ "", 70447 /* RSEL2_XOR_MEMORY_DEBUG */ "", 70448 /* RSEL_RAM_DBGCTRL_64 */ "RSEL_RAM_CONTROL_64", 70449 /* RSEL_RAM_DBGCTRL_64_PIPE0 */ "RSEL_RAM_CONTROL_64_PIPE0", 70450 /* RSEL_RAM_DBGCTRL_64_PIPE1 */ "RSEL_RAM_CONTROL_64_PIPE1", 70451 /* RSEL_RAM_DBGCTRL_64_PIPE2 */ "RSEL_RAM_CONTROL_64_PIPE2", 70452 /* RSEL_RAM_DBGCTRL_64_PIPE3 */ "RSEL_RAM_CONTROL_64_PIPE3", 70453 /* RSEL_RAM_DBGCTRL_64_PIPE4 */ "RSEL_RAM_CONTROL_64_PIPE4", 70454 /* RSEL_RAM_DBGCTRL_64_PIPE5 */ "RSEL_RAM_CONTROL_64_PIPE5", 70455 /* RSEL_RAM_DBGCTRL_64_PIPE6 */ "RSEL_RAM_CONTROL_64_PIPE6", 70456 /* RSEL_RAM_DBGCTRL_64_PIPE7 */ "RSEL_RAM_CONTROL_64_PIPE7", 70457 /* RSTOP_DROP */ "", 70458 /* RSTORM_BC */ "", 70459 /* RSTORM_BC_BYTE */ "", 70460 /* RSTORM_MC */ "", 70461 /* RSTORM_MC_BYTE */ "", 70462 /* RSTORM_UC */ "", 70463 /* RSTORM_UC_BYTE */ "", 70464 /* RSV_READ */ "", 70465 /* RTAG7_BASED_HASH_CONTROL */ "", 70466 /* RTAG7_FCOE_HASH_FIELD_BMAP */ "", 70467 /* RTAG7_FLOW_BASED_HASH_PARITY_CONTROL */ "", 70468 /* RTAG7_FLOW_BASED_HASH_PARITY_STATUS */ "", 70469 /* RTAG7_FLOW_BASED_HASH_PARITY_STATUS_INTR */ "", 70470 /* RTAG7_FLOW_BASED_HASH_PARITY_STATUS_NACK */ "", 70471 /* RTAG7_FLOW_PORT_HASH_CONTROL_DBGCTRL */ "RTAG7_FLOW_PORT_HASH_CONTROL", 70472 /* RTAG7_HASH_CONTROL */ "", 70473 /* RTAG7_HASH_CONTROL_2 */ "", 70474 /* RTAG7_HASH_CONTROL_3 */ "", 70475 /* RTAG7_HASH_CONTROL_4 */ "", 70476 /* RTAG7_HASH_CONTROL_64 */ "", 70477 /* RTAG7_HASH_CONTROL_2_64 */ "RTAG7_HASH_CONTROL_2", 70478 /* RTAG7_HASH_CONTROL_3_64 */ "", 70479 /* RTAG7_HASH_CONTROL_L2GRE_MASK_A */ "", 70480 /* RTAG7_HASH_CONTROL_L2GRE_MASK_B */ "", 70481 /* RTAG7_HASH_DLB_HGT */ "", 70482 /* RTAG7_HASH_ECMP */ "", 70483 /* RTAG7_HASH_ENTROPY_LABEL */ "", 70484 /* RTAG7_HASH_FIELD_BMAP_1 */ "", 70485 /* RTAG7_HASH_FIELD_BMAP_2 */ "", 70486 /* RTAG7_HASH_FIELD_BMAP_3 */ "", 70487 /* RTAG7_HASH_FIELD_BMAP_4 */ "", 70488 /* RTAG7_HASH_FIELD_BMAP_5 */ "", 70489 /* RTAG7_HASH_HG_TRUNK */ "", 70490 /* RTAG7_HASH_HG_TRUNK_FAILOVER */ "", 70491 /* RTAG7_HASH_LBID */ "", 70492 /* RTAG7_HASH_MPLS_ECMP */ "", 70493 /* RTAG7_HASH_PLFS */ "", 70494 /* RTAG7_HASH_SEED_A */ "", 70495 /* RTAG7_HASH_SEED_A_PIPE0 */ "", 70496 /* RTAG7_HASH_SEED_A_PIPE1 */ "", 70497 /* RTAG7_HASH_SEED_A_PIPE2 */ "", 70498 /* RTAG7_HASH_SEED_A_PIPE3 */ "", 70499 /* RTAG7_HASH_SEED_A_PIPE4 */ "", 70500 /* RTAG7_HASH_SEED_A_PIPE5 */ "", 70501 /* RTAG7_HASH_SEED_A_PIPE6 */ "", 70502 /* RTAG7_HASH_SEED_A_PIPE7 */ "", 70503 /* RTAG7_HASH_SEED_B */ "", 70504 /* RTAG7_HASH_SEED_B_PIPE0 */ "", 70505 /* RTAG7_HASH_SEED_B_PIPE1 */ "", 70506 /* RTAG7_HASH_SEED_B_PIPE2 */ "", 70507 /* RTAG7_HASH_SEED_B_PIPE3 */ "", 70508 /* RTAG7_HASH_SEED_B_PIPE4 */ "", 70509 /* RTAG7_HASH_SEED_B_PIPE5 */ "", 70510 /* RTAG7_HASH_SEED_B_PIPE6 */ "", 70511 /* RTAG7_HASH_SEED_B_PIPE7 */ "", 70512 /* RTAG7_HASH_SEL */ "", 70513 /* RTAG7_HASH_TRILL_ECMP */ "", 70514 /* RTAG7_HASH_TRUNK */ "", 70515 /* RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_1 */ "", 70516 /* RTAG7_IPV4_TCP_UDP_HASH_FIELD_BMAP_2 */ "", 70517 /* RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_1 */ "", 70518 /* RTAG7_IPV6_TCP_UDP_HASH_FIELD_BMAP_2 */ "", 70519 /* RTAG7_L2GRE_PAYLOAD_L2_HASH_FIELD_BMAP */ "", 70520 /* RTAG7_L2GRE_PAYLOAD_L3_HASH_FIELD_BMAP */ "", 70521 /* RTAG7_MIM_OUTER_HASH_FIELD_BMAP */ "", 70522 /* RTAG7_MIM_PAYLOAD_HASH_FIELD_BMAP */ "", 70523 /* RTAG7_MIM_PAYLOAD_L3_HASH_FIELD_BMAP */ "", 70524 /* RTAG7_MPLS_L2_PAYLOAD_HASH_FIELD_BMAP */ "", 70525 /* RTAG7_MPLS_L2_PAYLOAD_L3_HASH_FIELD_BMAP */ "", 70526 /* RTAG7_MPLS_L3_PAYLOAD_HASH_FIELD_BMAP */ "", 70527 /* RTAG7_MPLS_OUTER_HASH_FIELD_BMAP */ "", 70528 /* RTAG7_MPLS_OUTER_HASH_FIELD_BMAP_EXTENDED */ "", 70529 /* RTAG7_PORT_BASED_HASH_CONTROL */ "", 70530 /* RTAG7_PORT_BASED_HASH_PARITY_CONTROL */ "", 70531 /* RTAG7_PORT_BASED_HASH_PARITY_STATUS */ "", 70532 /* RTAG7_PORT_BASED_HASH_PARITY_STATUS_INTR */ "", 70533 /* RTAG7_PORT_BASED_HASH_PARITY_STATUS_NACK */ "", 70534 /* RTAG7_ROCEV1_HASH_FIELD_BMAP */ "", 70535 /* RTAG7_ROCEV2_HASH_FIELD_BMAP */ "", 70536 /* RTAG7_TRILL_PAYLOAD_L2_HASH_FIELD_BMAP */ "", 70537 /* RTAG7_TRILL_PAYLOAD_L3_HASH_FIELD_BMAP */ "", 70538 /* RTAG7_TRILL_TUNNEL_HASH_FIELD_BMAP */ "", 70539 /* RTAG7_VXLAN_PAYLOAD_L2_HASH_FIELD_BMAP */ "", 70540 /* RTAG7_VXLAN_PAYLOAD_L3_HASH_FIELD_BMAP */ "", 70541 /* RTPTSI1_TCID_0 */ "", 70542 /* RTPTSI1_TCID_1 */ "", 70543 /* RTPTSI1_TCID_2 */ "", 70544 /* RTPTSI1_TCID_3 */ "", 70545 /* RTPTSI1_TCID_4 */ "", 70546 /* RTPTSI1_TCID_5 */ "", 70547 /* RTPTSI1_TCID_6 */ "", 70548 /* RTPTSI1_TCID_7 */ "", 70549 /* RTPTSI1_TCID_8 */ "", 70550 /* RTPTSI1_TCID_9 */ "", 70551 /* RTPTSI1_TCID_10 */ "", 70552 /* RTPTSI1_TCID_11 */ "", 70553 /* RTPTSI1_TCID_12 */ "", 70554 /* RTPTSI1_TCID_13 */ "", 70555 /* RTPTSI1_TCID_14 */ "", 70556 /* RTPTSI1_TCID_15 */ "", 70557 /* RTPTSI2_TCID_0 */ "", 70558 /* RTPTSI2_TCID_1 */ "", 70559 /* RTPTSI2_TCID_2 */ "", 70560 /* RTPTSI2_TCID_3 */ "", 70561 /* RTPTSI2_TCID_4 */ "", 70562 /* RTPTSI2_TCID_5 */ "", 70563 /* RTPTSI2_TCID_6 */ "", 70564 /* RTPTSI2_TCID_7 */ "", 70565 /* RTPTSI2_TCID_8 */ "", 70566 /* RTPTSI2_TCID_9 */ "", 70567 /* RTPTSI2_TCID_10 */ "", 70568 /* RTPTSI2_TCID_11 */ "", 70569 /* RTPTSI2_TCID_12 */ "", 70570 /* RTPTSI2_TCID_13 */ "", 70571 /* RTPTSI2_TCID_14 */ "", 70572 /* RTPTSI2_TCID_15 */ "", 70573 /* RTPTSZ1 */ "", 70574 /* RTPTSZ2 */ "", 70575 /* RTP_ACL_RECEIVED */ "", 70576 /* RTP_ACL_VECTOR */ "", 70577 /* RTP_ALLOWED_LINKS */ "", 70578 /* RTP_ALLOWED_LINKS_CONTROL_CELLS_REGISTER */ "", 70579 /* RTP_ALLOWED_LINKS_FOR_REACHABILITY_MESSAGES */ "", 70580 /* RTP_ALLOWED_LINKS_PIPE_0_REGISTER */ "", 70581 /* RTP_ALLOWED_LINKS_PIPE_1_REGISTER */ "", 70582 /* RTP_ALLOWED_LINKS_PIPE_2_REGISTER */ "", 70583 /* RTP_ALLOWED_LINKS_REGISTER_PRIM */ "", 70584 /* RTP_ALLOWED_LINKS_REGISTER_SCND */ "", 70585 /* RTP_ALL_MUL_DROP_TH */ "", 70586 /* RTP_ALL_REACHABLE_AND_GROUP_REACHABLE_CFG */ "", 70587 /* RTP_ALL_REACHABLE_CFG */ "", 70588 /* RTP_ALL_REACHABLE_OVERRIDE */ "", 70589 /* RTP_ALL_REACHABLE_VECTOR */ "", 70590 /* RTP_ALRC_EXCLUDE */ "", 70591 /* RTP_AUTO_DOC_NAME_0 */ "", 70592 /* RTP_CRH_INTERRUPT_MASK_REGISTER */ "", 70593 /* RTP_CRH_INTERRUPT_REGISTER */ "", 70594 /* RTP_CRH_INTERRUPT_REGISTER_TEST */ "", 70595 /* RTP_DISCONNECT_FROM_ECI */ "", 70596 /* RTP_DRHPA_ECC_ERR_1B_INITIATE */ "", 70597 /* RTP_DRHPA_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 70598 /* RTP_DRHPA_ECC_ERR_2B_INITIATE */ "", 70599 /* RTP_DRHPA_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 70600 /* RTP_DRHPB_ECC_ERR_1B_INITIATE */ "", 70601 /* RTP_DRHPB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 70602 /* RTP_DRHPB_ECC_ERR_2B_INITIATE */ "", 70603 /* RTP_DRHPB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 70604 /* RTP_DRHP_DROPPED_LOW_MUL */ "", 70605 /* RTP_DRHP_INTERRUPT_MASK_REGISTER */ "", 70606 /* RTP_DRHP_INTERRUPT_REGISTER */ "", 70607 /* RTP_DRHP_INTERRUPT_REGISTER_TEST */ "", 70608 /* RTP_DRHP_MCSFF_HIT_COUNTER */ "", 70609 /* RTP_DRHP_UNREACHABLEMULTICASTINFO */ "", 70610 /* RTP_DRHS_DROPPED_LOW_MUL */ "", 70611 /* RTP_DRHS_INTERRUPT_MASK_REGISTER */ "", 70612 /* RTP_DRHS_INTERRUPT_REGISTER */ "", 70613 /* RTP_DRHS_UNREACHABLEMULTICASTINFO */ "", 70614 /* RTP_DRH_LOAD_BALANCING_CONFIG */ "", 70615 /* RTP_DRH_LOAD_BALANCING_FAULT_CONFIG */ "", 70616 /* RTP_DRH_LOAD_BALANCING_GENERAL_CONFIG */ "", 70617 /* RTP_DRH_LOAD_BALANCING_LEVEL_CONFIG */ "", 70618 /* RTP_DRH_LOAD_BALANCING_LEVEL_OPTIMIZATION */ "", 70619 /* RTP_DRH_LOAD_BALANCING_OPTIMIZATION */ "", 70620 /* RTP_DRH_LP_REPLICATION_CTRL */ "", 70621 /* RTP_ECC_1B_ERR_CNT */ "", 70622 /* RTP_ECC_1B_ERR_INTERRUPT_MASK_REGISTER */ "", 70623 /* RTP_ECC_1B_ERR_INTERRUPT_REGISTER */ "", 70624 /* RTP_ECC_2B_ERR_CNT */ "", 70625 /* RTP_ECC_2B_ERR_INTERRUPT_MASK_REGISTER */ "", 70626 /* RTP_ECC_2B_ERR_INTERRUPT_REGISTER */ "", 70627 /* RTP_ECC_ERR_1B_INITIATE */ "", 70628 /* RTP_ECC_ERR_1B_INITIATE_B */ "", 70629 /* RTP_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 70630 /* RTP_ECC_ERR_2B_INITIATE */ "", 70631 /* RTP_ECC_ERR_2B_INITIATE_B */ "", 70632 /* RTP_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 70633 /* RTP_ECC_INTERRUPT_REGISTER */ "", 70634 /* RTP_ECC_INTERRUPT_REGISTER_MASK */ "", 70635 /* RTP_ECC_INTERRUPT_REGISTER_TEST */ "", 70636 /* RTP_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 70637 /* RTP_ERROR_INITIATION_DATA */ "", 70638 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_0 */ "", 70639 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_1 */ "", 70640 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_2 */ "", 70641 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_3 */ "", 70642 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_4 */ "", 70643 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_5 */ "", 70644 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_6 */ "", 70645 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_7 */ "", 70646 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_8 */ "", 70647 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_9 */ "", 70648 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_10 */ "", 70649 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_11 */ "", 70650 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_12 */ "", 70651 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_13 */ "", 70652 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_14 */ "", 70653 /* RTP_EXCLUDE_DEST_ID_FOR_MC_LINKS_15 */ "", 70654 /* RTP_EXTERNAL_PADS_VALUE */ "", 70655 /* RTP_FE_GLOBAL_FE_DEST_IDS_1 */ "", 70656 /* RTP_FE_GLOBAL_FE_DEST_IDS_2 */ "", 70657 /* RTP_FE_GLOBAL_FE_DEST_IDS_3 */ "", 70658 /* RTP_FE_GLOBAL_FE_DEST_IDS_4 */ "", 70659 /* RTP_FE_GLOBAL_GENERAL_CFG_1 */ "", 70660 /* RTP_FORCE_LINK_INTEGRITY_DOWN */ "", 70661 /* RTP_FORCE_LINK_INTEGRITY_UP */ "", 70662 /* RTP_GENERAL_INTERRUPT_MASK_REGISTER */ "", 70663 /* RTP_GENERAL_INTERRUPT_REGISTER */ "", 70664 /* RTP_GENERAL_INTERRUPT_REGISTER_TEST */ "", 70665 /* RTP_GLOBAL_FE_DEST_IDS_1 */ "", 70666 /* RTP_GLOBAL_FE_DEST_IDS_2 */ "", 70667 /* RTP_GLOBAL_GENERAL_CFG_2 */ "", 70668 /* RTP_GLOBAL_GENERAL_FE_CFG_1 */ "", 70669 /* RTP_GLOBAL_MEM_OPTIONS */ "", 70670 /* RTP_GPD_MODE_DETECT_INFO */ "", 70671 /* RTP_GRACEFUL_POWER_DOWN_CONFIGURATION */ "", 70672 /* RTP_GTIMER_CONFIGURATION */ "", 70673 /* RTP_GTIMER_CYCLE */ "", 70674 /* RTP_GTIMER_TRIGGER */ "", 70675 /* RTP_INDIRECT_COMMAND */ "", 70676 /* RTP_INDIRECT_COMMAND_ADDRESS */ "", 70677 /* RTP_INDIRECT_COMMAND_DATA_INCREMENT */ "", 70678 /* RTP_INDIRECT_COMMAND_RD_DATA */ "", 70679 /* RTP_INDIRECT_COMMAND_WIDE_MEM */ "", 70680 /* RTP_INDIRECT_COMMAND_WR_DATA */ "", 70681 /* RTP_INDIRECT_FORCE_BUBBLE */ "", 70682 /* RTP_INTERRUPT_MASK_REGISTER */ "", 70683 /* RTP_INTERRUPT_REGISTER */ "", 70684 /* RTP_INTERRUPT_REGISTER_TEST */ "", 70685 /* RTP_LINK_ACTIVE_MASK */ "", 70686 /* RTP_LINK_BUNDLE_BITMAP */ "", 70687 /* RTP_LINK_INTEGRITY_VECTOR */ "", 70688 /* RTP_LINK_STATE_FOR_SC_HAND_FDT */ "", 70689 /* RTP_LINK_STATE_VECTOR */ "", 70690 /* RTP_LOCALLY_GENERATED_ACL */ "", 70691 /* RTP_LOCAL_ROUTE_CONFIGURATIONS */ "", 70692 /* RTP_LOW_PR_MULTH */ "", 70693 /* RTP_LOW_PR_MUL_CTRL */ "", 70694 /* RTP_MAXIMUM_BASE_INDEX */ "", 70695 /* RTP_MCLBT_GROUP_STATIC_CONFIG */ "", 70696 /* RTP_MC_DISTRIBUTION_MAP */ "", 70697 /* RTP_MC_TRAVERSE_RATE */ "", 70698 /* RTP_MIN_NUM_OF_LINKS_PER_FAP */ "", 70699 /* RTP_MIRROR_ADDRESS */ "", 70700 /* RTP_MNOL_DROP_CONFIGURATION */ "", 70701 /* RTP_MNOL_GCI_CONFIGURATION */ "", 70702 /* RTP_MULICAST_ALLOWED_LINKS_REGISTER */ "", 70703 /* RTP_MULTICAST_DISTRIBUTION_CONFIGURATION */ "", 70704 /* RTP_MULTICAST_DISTRIBUTION_CONFIGURATION_REGISTER */ "", 70705 /* RTP_MULTICAST_LINK_UP */ "", 70706 /* RTP_MULTICAST_MODE_SELECTION */ "", 70707 /* RTP_PARITY_ERR_CNT */ "", 70708 /* RTP_PAR_ERR_INITIATE */ "", 70709 /* RTP_PAR_ERR_INTERRUPT_MASK_REGISTER */ "", 70710 /* RTP_PAR_ERR_INTERRUPT_REGISTER */ "", 70711 /* RTP_PAR_ERR_MEM_MASK */ "", 70712 /* RTP_PCMI_0 */ "", 70713 /* RTP_PCMI_1 */ "", 70714 /* RTP_PCMI_2 */ "", 70715 /* RTP_PCMI_3 */ "", 70716 /* RTP_PCMI_0_S */ "", 70717 /* RTP_PCMI_0_T */ "", 70718 /* RTP_PCMI_1_S */ "", 70719 /* RTP_PCMI_1_T */ "", 70720 /* RTP_PCMI_2_S */ "", 70721 /* RTP_PCMI_2_T */ "", 70722 /* RTP_PCMI_3_S */ "", 70723 /* RTP_PCMI_3_T */ "", 70724 /* RTP_PIPE_ID_A_FOR_RM */ "", 70725 /* RTP_PIPE_ID_B_FOR_RM */ "", 70726 /* RTP_REACHABILITY_ALLOWED_LINKS_REGISTER */ "", 70727 /* RTP_REACHABILITY_CLEAR_LINKS_REGISTER */ "", 70728 /* RTP_REACHABILITY_INFO_ALLOWED_LINKS_REGISTER */ "", 70729 /* RTP_REACHABILITY_MESSAGE_GENERATOR_CONFIGURATION */ "", 70730 /* RTP_REACHABILITY_MESSAGE_PROCESSOR_CONFIGURATION */ "", 70731 /* RTP_REG_0041 */ "", 70732 /* RTP_REG_0049 */ "", 70733 /* RTP_REG_0050 */ "", 70734 /* RTP_REG_0051 */ "", 70735 /* RTP_REG_0052 */ "", 70736 /* RTP_REG_0054 */ "", 70737 /* RTP_REG_0058 */ "", 70738 /* RTP_REG_0063 */ "", 70739 /* RTP_REG_0067 */ "", 70740 /* RTP_REG_0069 */ "", 70741 /* RTP_REG_0074 */ "", 70742 /* RTP_REG_0086 */ "", 70743 /* RTP_REG_0090 */ "", 70744 /* RTP_REG_0091 */ "", 70745 /* RTP_REG_0092 */ "", 70746 /* RTP_REG_0093 */ "", 70747 /* RTP_REG_0097 */ "", 70748 /* RTP_REG_0098 */ "", 70749 /* RTP_REG_0162 */ "", 70750 /* RTP_REG_0203 */ "", 70751 /* RTP_REG_0273 */ "", 70752 /* RTP_REG_0275 */ "", 70753 /* RTP_REG_0277 */ "", 70754 /* RTP_REG_0279 */ "", 70755 /* RTP_REG_005A */ "", 70756 /* RTP_REG_00A0 */ "", 70757 /* RTP_REG_00A4 */ "", 70758 /* RTP_REG_00A6 */ "", 70759 /* RTP_REG_00AA */ "", 70760 /* RTP_REG_00AE */ "", 70761 /* RTP_REG_00AF */ "", 70762 /* RTP_REG_00C0 */ "", 70763 /* RTP_REG_00C2 */ "", 70764 /* RTP_REG_00C4 */ "", 70765 /* RTP_REG_00CF */ "", 70766 /* RTP_REG_01FA */ "", 70767 /* RTP_RESERVED_10 */ "", 70768 /* RTP_RESERVED_14 */ "", 70769 /* RTP_RESERVED_15 */ "", 70770 /* RTP_RESERVED_MIRROR_ADDR */ "", 70771 /* RTP_RESERVED_MTCD */ "", 70772 /* RTP_RESERVED_MTCP */ "", 70773 /* RTP_RESERVED_PCMI_0 */ "", 70774 /* RTP_RESERVED_PCMI_1 */ "", 70775 /* RTP_RESERVED_PCMI_2 */ "", 70776 /* RTP_RESERVED_PCMI_4 */ "", 70777 /* RTP_RESERVED_PCMI_0_S */ "", 70778 /* RTP_RESERVED_PCMI_0_T */ "", 70779 /* RTP_RESERVED_PCMI_1_S */ "", 70780 /* RTP_RESERVED_PCMI_1_T */ "", 70781 /* RTP_RESERVED_PCMI_2_S */ "", 70782 /* RTP_RESERVED_PCMI_2_T */ "", 70783 /* RTP_RESERVED_PCMI_4_S */ "", 70784 /* RTP_RESERVED_PCMI_4_T */ "", 70785 /* RTP_RESERVED_SPARE_0 */ "", 70786 /* RTP_RESERVED_SPARE_1 */ "", 70787 /* RTP_RESERVED_SPARE_2 */ "", 70788 /* RTP_RESERVED_SPARE_3 */ "", 70789 /* RTP_RTP_BY_PASS */ "", 70790 /* RTP_RTP_ENABLE */ "", 70791 /* RTP_SBUS_BROADCAST_ID */ "", 70792 /* RTP_SBUS_LAST_IN_CHAIN */ "", 70793 /* RTP_SCH_LINK_UP_CALC */ "", 70794 /* RTP_SPARE_REGISTER_2 */ "", 70795 /* RTP_SPARE_REGISTER_3 */ "", 70796 /* RTP_SPECIAL_CLOCK_CONTROLS */ "", 70797 /* RTP_UNICAST_ROUTE_UPDATE_DIRTY */ "", 70798 /* RTP_UNICAST_TABLE_LAST_UPDATE */ "", 70799 /* RTRFU */ "MAC_GRxTRFU", 70800 /* RTSECP */ "", 70801 /* RTSFPHC */ "", 70802 /* RTSGCFG */ "", 70803 /* RTS_DMAC_PL330_CC_0 */ "", 70804 /* RTS_DMAC_PL330_CC_1 */ "", 70805 /* RTS_DMAC_PL330_CC_2 */ "", 70806 /* RTS_DMAC_PL330_CC_3 */ "", 70807 /* RTS_DMAC_PL330_CC_4 */ "", 70808 /* RTS_DMAC_PL330_CC_5 */ "", 70809 /* RTS_DMAC_PL330_CC_6 */ "", 70810 /* RTS_DMAC_PL330_CC_7 */ "", 70811 /* RTS_DMAC_PL330_CPC0 */ "", 70812 /* RTS_DMAC_PL330_CPC1 */ "", 70813 /* RTS_DMAC_PL330_CPC2 */ "", 70814 /* RTS_DMAC_PL330_CPC3 */ "", 70815 /* RTS_DMAC_PL330_CPC4 */ "", 70816 /* RTS_DMAC_PL330_CPC5 */ "", 70817 /* RTS_DMAC_PL330_CPC6 */ "", 70818 /* RTS_DMAC_PL330_CPC7 */ "", 70819 /* RTS_DMAC_PL330_CR0 */ "", 70820 /* RTS_DMAC_PL330_CR1 */ "", 70821 /* RTS_DMAC_PL330_CR2 */ "", 70822 /* RTS_DMAC_PL330_CR3 */ "", 70823 /* RTS_DMAC_PL330_CR4 */ "", 70824 /* RTS_DMAC_PL330_CRDN */ "", 70825 /* RTS_DMAC_PL330_CS0 */ "", 70826 /* RTS_DMAC_PL330_CS1 */ "", 70827 /* RTS_DMAC_PL330_CS2 */ "", 70828 /* RTS_DMAC_PL330_CS3 */ "", 70829 /* RTS_DMAC_PL330_CS4 */ "", 70830 /* RTS_DMAC_PL330_CS5 */ "", 70831 /* RTS_DMAC_PL330_CS6 */ "", 70832 /* RTS_DMAC_PL330_CS7 */ "", 70833 /* RTS_DMAC_PL330_DA_0 */ "", 70834 /* RTS_DMAC_PL330_DA_1 */ "", 70835 /* RTS_DMAC_PL330_DA_2 */ "", 70836 /* RTS_DMAC_PL330_DA_3 */ "", 70837 /* RTS_DMAC_PL330_DA_4 */ "", 70838 /* RTS_DMAC_PL330_DA_5 */ "", 70839 /* RTS_DMAC_PL330_DA_6 */ "", 70840 /* RTS_DMAC_PL330_DA_7 */ "", 70841 /* RTS_DMAC_PL330_DBGCMD */ "", 70842 /* RTS_DMAC_PL330_DBGINST0 */ "", 70843 /* RTS_DMAC_PL330_DBGINST1 */ "", 70844 /* RTS_DMAC_PL330_DBGSTATUS */ "", 70845 /* RTS_DMAC_PL330_DPC */ "", 70846 /* RTS_DMAC_PL330_DS */ "", 70847 /* RTS_DMAC_PL330_FSC */ "", 70848 /* RTS_DMAC_PL330_FSM */ "", 70849 /* RTS_DMAC_PL330_FTC0 */ "", 70850 /* RTS_DMAC_PL330_FTC1 */ "", 70851 /* RTS_DMAC_PL330_FTC2 */ "", 70852 /* RTS_DMAC_PL330_FTC3 */ "", 70853 /* RTS_DMAC_PL330_FTC4 */ "", 70854 /* RTS_DMAC_PL330_FTC5 */ "", 70855 /* RTS_DMAC_PL330_FTC6 */ "", 70856 /* RTS_DMAC_PL330_FTC7 */ "", 70857 /* RTS_DMAC_PL330_FTM */ "", 70858 /* RTS_DMAC_PL330_INTCLR */ "", 70859 /* RTS_DMAC_PL330_INTEN */ "", 70860 /* RTS_DMAC_PL330_INTSTATUS */ "", 70861 /* RTS_DMAC_PL330_INT_EVENT_RIS */ "", 70862 /* RTS_DMAC_PL330_LC0_0 */ "", 70863 /* RTS_DMAC_PL330_LC0_1 */ "", 70864 /* RTS_DMAC_PL330_LC0_2 */ "", 70865 /* RTS_DMAC_PL330_LC0_3 */ "", 70866 /* RTS_DMAC_PL330_LC0_4 */ "", 70867 /* RTS_DMAC_PL330_LC0_5 */ "", 70868 /* RTS_DMAC_PL330_LC0_6 */ "", 70869 /* RTS_DMAC_PL330_LC0_7 */ "", 70870 /* RTS_DMAC_PL330_LC1_0 */ "", 70871 /* RTS_DMAC_PL330_LC1_1 */ "", 70872 /* RTS_DMAC_PL330_LC1_2 */ "", 70873 /* RTS_DMAC_PL330_LC1_3 */ "", 70874 /* RTS_DMAC_PL330_LC1_4 */ "", 70875 /* RTS_DMAC_PL330_LC1_5 */ "", 70876 /* RTS_DMAC_PL330_LC1_6 */ "", 70877 /* RTS_DMAC_PL330_LC1_7 */ "", 70878 /* RTS_DMAC_PL330_SA_0 */ "", 70879 /* RTS_DMAC_PL330_SA_1 */ "", 70880 /* RTS_DMAC_PL330_SA_2 */ "", 70881 /* RTS_DMAC_PL330_SA_3 */ "", 70882 /* RTS_DMAC_PL330_SA_4 */ "", 70883 /* RTS_DMAC_PL330_SA_5 */ "", 70884 /* RTS_DMAC_PL330_SA_6 */ "", 70885 /* RTS_DMAC_PL330_SA_7 */ "", 70886 /* RTS_DMAC_PL330_WD */ "", 70887 /* RTS_ICFG_CONFIG_0 */ "", 70888 /* RTS_ICFG_DMAC_CONFIG_0 */ "", 70889 /* RTS_ICFG_DMAC_CONFIG_1 */ "", 70890 /* RTS_ICFG_DMAC_ECC_INTR_CLR */ "", 70891 /* RTS_ICFG_DMAC_ECC_INTR_EN */ "", 70892 /* RTS_ICFG_DMAC_ECC_INTR_STATUS */ "", 70893 /* RTS_ICFG_DMAC_ECC_LOG_1 */ "", 70894 /* RTS_ICFG_DMAC_ECC_LOG_2 */ "", 70895 /* RTS_ICFG_DMAC_IO_CONTROL_DIRECT */ "", 70896 /* RTS_ICFG_DMAC_IO_STATUS */ "", 70897 /* RTS_ICFG_IP_DISABLE_STRAP_STATUS_0 */ "", 70898 /* RTS_ICFG_IP_REVID_0 */ "", 70899 /* RTS_ICFG_MEM_ECC_CTRL */ "", 70900 /* RTS_ICFG_MHOST0_IO_CONTROL_DIRECT */ "", 70901 /* RTS_ICFG_MHOST1_IO_CONTROL_DIRECT */ "", 70902 /* RTS_ICFG_MHOST2_IO_CONTROL_DIRECT */ "", 70903 /* RTS_ICFG_PCIE64B_ACCESS_MSB_31TO24 */ "", 70904 /* RTS_ICFG_PCIE64B_ACCESS_MSB_63TO32 */ "", 70905 /* RTS_ICFG_SRAM0_CONTROL */ "", 70906 /* RTS_ICFG_SRAM1_CONTROL */ "", 70907 /* RTS_ICFG_SRAM2_CONTROL */ "", 70908 /* RTS_ICFG_SRAM3_CONTROL */ "", 70909 /* RTS_ICFG_SRAM4_CONTROL */ "", 70910 /* RTS_ICFG_SRAM5_CONTROL */ "", 70911 /* RTS_ICFG_SRAM6_CONTROL */ "", 70912 /* RTS_ICFG_SRAM7_CONTROL */ "", 70913 /* RTS_M0_IDM_IDM_INTERRUPT_STATUS */ "", 70914 /* RTS_M0_IDM_IDM_RESET_STATUS */ "", 70915 /* RTS_M0_IDM_IO_CONTROL_DIRECT */ "", 70916 /* RTS_M0_IDM_M_IDM_RESET_CONTROL */ "", 70917 /* RTS_MHOST_1_ARCACHE_REMAP */ "", 70918 /* RTS_MHOST_1_ARSHARE_REMAP */ "", 70919 /* RTS_MHOST_1_AWCACHE_REMAP */ "", 70920 /* RTS_MHOST_1_AWSHARE_REMAP */ "", 70921 /* RTS_MHOST_1_CR5_AXI_FATAL_ERR_STATUS */ "", 70922 /* RTS_MHOST_1_CR5_CFG_CTRL */ "", 70923 /* RTS_MHOST_1_CR5_EVENTI_CONTROL */ "", 70924 /* RTS_MHOST_1_CR5_EVENTO_STATUS */ "", 70925 /* RTS_MHOST_1_CR5_PPH_CFG_CTRL */ "", 70926 /* RTS_MHOST_1_CR5_PPV_CFG_CTRL */ "", 70927 /* RTS_MHOST_1_CR5_PPX_CFG_CTRL */ "", 70928 /* RTS_MHOST_1_CR5_RST_CTRL */ "", 70929 /* RTS_MHOST_1_CR5_STANDBY_STATUS */ "", 70930 /* RTS_MHOST_1_MEM_LVM_CTRL */ "", 70931 /* RTS_MHOST_1_MEM_TM_CTRL_0 */ "", 70932 /* RTS_MHOST_1_MEM_TM_CTRL_1 */ "", 70933 /* RTS_MHOST_1_MEM_TM_CTRL_2 */ "", 70934 /* RTS_MHOST_1_MEM_TM_CTRL_3 */ "", 70935 /* RTS_MHOST_1_MEM_TM_CTRL_4 */ "", 70936 /* RTS_MHOST_1_MEM_TM_CTRL_5 */ "", 70937 /* RTS_MHOST_1_MEM_TM_CTRL_6 */ "", 70938 /* RTS_MHOST_1_MEM_TM_CTRL_7 */ "", 70939 /* RTS_MHOST_1_MEM_TM_CTRL_8 */ "", 70940 /* RTS_MHOST_1_MEM_TM_CTRL_9 */ "", 70941 /* RTS_MHOST_1_MEM_TM_CTRL_10 */ "", 70942 /* RTS_MHOST_1_MEM_TM_CTRL_11 */ "", 70943 /* RTS_MHOST_1_MEM_TM_CTRL_12 */ "", 70944 /* RTS_MHOST_1_MEM_TM_CTRL_13 */ "", 70945 /* RTS_MHOST_1_MHOST_DEBUG_CTRL */ "", 70946 /* RTS_MHOST_1_MHOST_INTR_MASK_0 */ "", 70947 /* RTS_MHOST_1_MHOST_INTR_MASK_1 */ "", 70948 /* RTS_MHOST_1_MHOST_INTR_MASK_2 */ "", 70949 /* RTS_MHOST_1_MHOST_INTR_MASK_3 */ "", 70950 /* RTS_MHOST_1_MHOST_INTR_MASK_4 */ "", 70951 /* RTS_MHOST_1_MHOST_INTR_MASK_5 */ "", 70952 /* RTS_MHOST_1_MHOST_INTR_MASK_6 */ "", 70953 /* RTS_MHOST_1_MHOST_INTR_MASK_7 */ "", 70954 /* RTS_MHOST_1_MHOST_INTR_OUT */ "", 70955 /* RTS_MHOST_1_MHOST_INTR_STATUS_0 */ "", 70956 /* RTS_MHOST_1_MHOST_INTR_STATUS_1 */ "", 70957 /* RTS_MHOST_1_MHOST_INTR_STATUS_2 */ "", 70958 /* RTS_MHOST_1_MHOST_INTR_STATUS_3 */ "", 70959 /* RTS_MHOST_1_MHOST_INTR_STATUS_4 */ "", 70960 /* RTS_MHOST_1_MHOST_INTR_STATUS_5 */ "", 70961 /* RTS_MHOST_1_MHOST_INTR_STATUS_6 */ "", 70962 /* RTS_MHOST_1_MHOST_INTR_STATUS_7 */ "", 70963 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_0 */ "", 70964 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_1 */ "", 70965 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_2 */ "", 70966 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_3 */ "", 70967 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_4 */ "", 70968 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_5 */ "", 70969 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_6 */ "", 70970 /* RTS_MHOST_1_MHOST_RAW_INTR_STATUS_7 */ "", 70971 /* RTS_MHOST_1_MHOST_STRAP_STATUS */ "", 70972 /* RTS_MHOST_1_TRACE_GLB_ACK */ "", 70973 /* RTS_MHOST_1_TRACE_GLB_REQ_CMD */ "", 70974 /* RTS_MHOST_2_ARCACHE_REMAP */ "", 70975 /* RTS_MHOST_2_ARSHARE_REMAP */ "", 70976 /* RTS_MHOST_2_AWCACHE_REMAP */ "", 70977 /* RTS_MHOST_2_AWSHARE_REMAP */ "", 70978 /* RTS_MHOST_2_CR5_AXI_FATAL_ERR_STATUS */ "", 70979 /* RTS_MHOST_2_CR5_CFG_CTRL */ "", 70980 /* RTS_MHOST_2_CR5_EVENTI_CONTROL */ "", 70981 /* RTS_MHOST_2_CR5_EVENTO_STATUS */ "", 70982 /* RTS_MHOST_2_CR5_PPH_CFG_CTRL */ "", 70983 /* RTS_MHOST_2_CR5_PPV_CFG_CTRL */ "", 70984 /* RTS_MHOST_2_CR5_PPX_CFG_CTRL */ "", 70985 /* RTS_MHOST_2_CR5_RST_CTRL */ "", 70986 /* RTS_MHOST_2_CR5_STANDBY_STATUS */ "", 70987 /* RTS_MHOST_2_MEM_LVM_CTRL */ "", 70988 /* RTS_MHOST_2_MEM_TM_CTRL_0 */ "", 70989 /* RTS_MHOST_2_MEM_TM_CTRL_1 */ "", 70990 /* RTS_MHOST_2_MEM_TM_CTRL_2 */ "", 70991 /* RTS_MHOST_2_MEM_TM_CTRL_3 */ "", 70992 /* RTS_MHOST_2_MEM_TM_CTRL_4 */ "", 70993 /* RTS_MHOST_2_MEM_TM_CTRL_5 */ "", 70994 /* RTS_MHOST_2_MEM_TM_CTRL_6 */ "", 70995 /* RTS_MHOST_2_MEM_TM_CTRL_7 */ "", 70996 /* RTS_MHOST_2_MEM_TM_CTRL_8 */ "", 70997 /* RTS_MHOST_2_MEM_TM_CTRL_9 */ "", 70998 /* RTS_MHOST_2_MEM_TM_CTRL_10 */ "", 70999 /* RTS_MHOST_2_MEM_TM_CTRL_11 */ "", 71000 /* RTS_MHOST_2_MEM_TM_CTRL_12 */ "", 71001 /* RTS_MHOST_2_MEM_TM_CTRL_13 */ "", 71002 /* RTS_MHOST_2_MHOST_DEBUG_CTRL */ "", 71003 /* RTS_MHOST_2_MHOST_INTR_MASK_0 */ "", 71004 /* RTS_MHOST_2_MHOST_INTR_MASK_1 */ "", 71005 /* RTS_MHOST_2_MHOST_INTR_MASK_2 */ "", 71006 /* RTS_MHOST_2_MHOST_INTR_MASK_3 */ "", 71007 /* RTS_MHOST_2_MHOST_INTR_MASK_4 */ "", 71008 /* RTS_MHOST_2_MHOST_INTR_MASK_5 */ "", 71009 /* RTS_MHOST_2_MHOST_INTR_MASK_6 */ "", 71010 /* RTS_MHOST_2_MHOST_INTR_MASK_7 */ "", 71011 /* RTS_MHOST_2_MHOST_INTR_OUT */ "", 71012 /* RTS_MHOST_2_MHOST_INTR_STATUS_0 */ "", 71013 /* RTS_MHOST_2_MHOST_INTR_STATUS_1 */ "", 71014 /* RTS_MHOST_2_MHOST_INTR_STATUS_2 */ "", 71015 /* RTS_MHOST_2_MHOST_INTR_STATUS_3 */ "", 71016 /* RTS_MHOST_2_MHOST_INTR_STATUS_4 */ "", 71017 /* RTS_MHOST_2_MHOST_INTR_STATUS_5 */ "", 71018 /* RTS_MHOST_2_MHOST_INTR_STATUS_6 */ "", 71019 /* RTS_MHOST_2_MHOST_INTR_STATUS_7 */ "", 71020 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_0 */ "", 71021 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_1 */ "", 71022 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_2 */ "", 71023 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_3 */ "", 71024 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_4 */ "", 71025 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_5 */ "", 71026 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_6 */ "", 71027 /* RTS_MHOST_2_MHOST_RAW_INTR_STATUS_7 */ "", 71028 /* RTS_MHOST_2_MHOST_STRAP_STATUS */ "", 71029 /* RTS_MHOST_2_TRACE_GLB_ACK */ "", 71030 /* RTS_MHOST_2_TRACE_GLB_REQ_CMD */ "", 71031 /* RTS_S0_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 71032 /* RTS_S0_IDM_IDM_ERROR_LOG_COMPLETE */ "", 71033 /* RTS_S0_IDM_IDM_ERROR_LOG_CONTROL */ "", 71034 /* RTS_S0_IDM_IDM_ERROR_LOG_FLAGS */ "", 71035 /* RTS_S0_IDM_IDM_ERROR_LOG_ID */ "", 71036 /* RTS_S0_IDM_IDM_ERROR_LOG_STATUS */ "", 71037 /* RTS_S0_IDM_IDM_INTERRUPT_STATUS */ "", 71038 /* RTS_S0_IDM_IDM_RESET_READ_ID */ "", 71039 /* RTS_S0_IDM_IDM_RESET_STATUS */ "", 71040 /* RTS_S0_IDM_IDM_RESET_WRITE_ID */ "", 71041 /* RTS_S0_IDM_S_IDM_RESET_CONTROL */ "", 71042 /* RTS_SRAM_LL_128K_0_CONTROL1 */ "", 71043 /* RTS_SRAM_LL_128K_0_DYNAMIC_STANDBY_CONTROL1 */ "", 71044 /* RTS_SRAM_LL_128K_0_DYNAMIC_STANDBY_CONTROL2 */ "", 71045 /* RTS_SRAM_LL_128K_0_INTERRUPT_ENABLE */ "", 71046 /* RTS_SRAM_LL_128K_0_INTERRUPT_STATUS */ "", 71047 /* RTS_SRAM_LL_128K_0_MEMORY_CONTROL */ "", 71048 /* RTS_SRAM_LL_128K_0_MEMORY_PDA */ "", 71049 /* RTS_SRAM_LL_128K_0_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71050 /* RTS_SRAM_LL_128K_0_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71051 /* RTS_SRAM_LL_128K_0_MEM_1BIT_ECC_ERR_W0B0 */ "", 71052 /* RTS_SRAM_LL_128K_0_MEM_1BIT_ECC_ERR_W0B1 */ "", 71053 /* RTS_SRAM_LL_128K_0_MEM_1BIT_ECC_ERR_W1B0 */ "", 71054 /* RTS_SRAM_LL_128K_0_MEM_1BIT_ECC_ERR_W1B1 */ "", 71055 /* RTS_SRAM_LL_128K_0_MEM_PWR_CONTROL */ "", 71056 /* RTS_SRAM_LL_128K_0_STATUS1 */ "", 71057 /* RTS_SRAM_LL_128K_0_STATUS2 */ "", 71058 /* RTS_SRAM_LL_128K_0_STATUS3 */ "", 71059 /* RTS_SRAM_LL_128K_0_STATUS4 */ "", 71060 /* RTS_SRAM_LL_128K_0_STATUS5 */ "", 71061 /* RTS_SRAM_LL_128K_0_STATUS6 */ "", 71062 /* RTS_SRAM_LL_128K_0_STATUS7 */ "", 71063 /* RTS_SRAM_LL_128K_0_STATUS8 */ "", 71064 /* RTS_SRAM_LL_128K_0_STATUS9 */ "", 71065 /* RTS_SRAM_LL_128K_0_STATUS10 */ "", 71066 /* RTS_SRAM_LL_128K_1_CONTROL1 */ "", 71067 /* RTS_SRAM_LL_128K_1_DYNAMIC_STANDBY_CONTROL1 */ "", 71068 /* RTS_SRAM_LL_128K_1_DYNAMIC_STANDBY_CONTROL2 */ "", 71069 /* RTS_SRAM_LL_128K_1_INTERRUPT_ENABLE */ "", 71070 /* RTS_SRAM_LL_128K_1_INTERRUPT_STATUS */ "", 71071 /* RTS_SRAM_LL_128K_1_MEMORY_CONTROL */ "", 71072 /* RTS_SRAM_LL_128K_1_MEMORY_PDA */ "", 71073 /* RTS_SRAM_LL_128K_1_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71074 /* RTS_SRAM_LL_128K_1_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71075 /* RTS_SRAM_LL_128K_1_MEM_1BIT_ECC_ERR_W0B0 */ "", 71076 /* RTS_SRAM_LL_128K_1_MEM_1BIT_ECC_ERR_W0B1 */ "", 71077 /* RTS_SRAM_LL_128K_1_MEM_1BIT_ECC_ERR_W1B0 */ "", 71078 /* RTS_SRAM_LL_128K_1_MEM_1BIT_ECC_ERR_W1B1 */ "", 71079 /* RTS_SRAM_LL_128K_1_MEM_PWR_CONTROL */ "", 71080 /* RTS_SRAM_LL_128K_1_STATUS1 */ "", 71081 /* RTS_SRAM_LL_128K_1_STATUS2 */ "", 71082 /* RTS_SRAM_LL_128K_1_STATUS3 */ "", 71083 /* RTS_SRAM_LL_128K_1_STATUS4 */ "", 71084 /* RTS_SRAM_LL_128K_1_STATUS5 */ "", 71085 /* RTS_SRAM_LL_128K_1_STATUS6 */ "", 71086 /* RTS_SRAM_LL_128K_1_STATUS7 */ "", 71087 /* RTS_SRAM_LL_128K_1_STATUS8 */ "", 71088 /* RTS_SRAM_LL_128K_1_STATUS9 */ "", 71089 /* RTS_SRAM_LL_128K_1_STATUS10 */ "", 71090 /* RTS_SRAM_LL_128K_2_CONTROL1 */ "", 71091 /* RTS_SRAM_LL_128K_2_DYNAMIC_STANDBY_CONTROL1 */ "", 71092 /* RTS_SRAM_LL_128K_2_DYNAMIC_STANDBY_CONTROL2 */ "", 71093 /* RTS_SRAM_LL_128K_2_INTERRUPT_ENABLE */ "", 71094 /* RTS_SRAM_LL_128K_2_INTERRUPT_STATUS */ "", 71095 /* RTS_SRAM_LL_128K_2_MEMORY_CONTROL */ "", 71096 /* RTS_SRAM_LL_128K_2_MEMORY_PDA */ "", 71097 /* RTS_SRAM_LL_128K_2_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71098 /* RTS_SRAM_LL_128K_2_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71099 /* RTS_SRAM_LL_128K_2_MEM_1BIT_ECC_ERR_W0B0 */ "", 71100 /* RTS_SRAM_LL_128K_2_MEM_1BIT_ECC_ERR_W0B1 */ "", 71101 /* RTS_SRAM_LL_128K_2_MEM_1BIT_ECC_ERR_W1B0 */ "", 71102 /* RTS_SRAM_LL_128K_2_MEM_1BIT_ECC_ERR_W1B1 */ "", 71103 /* RTS_SRAM_LL_128K_2_MEM_PWR_CONTROL */ "", 71104 /* RTS_SRAM_LL_128K_2_STATUS1 */ "", 71105 /* RTS_SRAM_LL_128K_2_STATUS2 */ "", 71106 /* RTS_SRAM_LL_128K_2_STATUS3 */ "", 71107 /* RTS_SRAM_LL_128K_2_STATUS4 */ "", 71108 /* RTS_SRAM_LL_128K_2_STATUS5 */ "", 71109 /* RTS_SRAM_LL_128K_2_STATUS6 */ "", 71110 /* RTS_SRAM_LL_128K_2_STATUS7 */ "", 71111 /* RTS_SRAM_LL_128K_2_STATUS8 */ "", 71112 /* RTS_SRAM_LL_128K_2_STATUS9 */ "", 71113 /* RTS_SRAM_LL_128K_2_STATUS10 */ "", 71114 /* RTS_SRAM_LL_128K_3_CONTROL1 */ "", 71115 /* RTS_SRAM_LL_128K_3_DYNAMIC_STANDBY_CONTROL1 */ "", 71116 /* RTS_SRAM_LL_128K_3_DYNAMIC_STANDBY_CONTROL2 */ "", 71117 /* RTS_SRAM_LL_128K_3_INTERRUPT_ENABLE */ "", 71118 /* RTS_SRAM_LL_128K_3_INTERRUPT_STATUS */ "", 71119 /* RTS_SRAM_LL_128K_3_MEMORY_CONTROL */ "", 71120 /* RTS_SRAM_LL_128K_3_MEMORY_PDA */ "", 71121 /* RTS_SRAM_LL_128K_3_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71122 /* RTS_SRAM_LL_128K_3_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71123 /* RTS_SRAM_LL_128K_3_MEM_1BIT_ECC_ERR_W0B0 */ "", 71124 /* RTS_SRAM_LL_128K_3_MEM_1BIT_ECC_ERR_W0B1 */ "", 71125 /* RTS_SRAM_LL_128K_3_MEM_1BIT_ECC_ERR_W1B0 */ "", 71126 /* RTS_SRAM_LL_128K_3_MEM_1BIT_ECC_ERR_W1B1 */ "", 71127 /* RTS_SRAM_LL_128K_3_MEM_PWR_CONTROL */ "", 71128 /* RTS_SRAM_LL_128K_3_STATUS1 */ "", 71129 /* RTS_SRAM_LL_128K_3_STATUS2 */ "", 71130 /* RTS_SRAM_LL_128K_3_STATUS3 */ "", 71131 /* RTS_SRAM_LL_128K_3_STATUS4 */ "", 71132 /* RTS_SRAM_LL_128K_3_STATUS5 */ "", 71133 /* RTS_SRAM_LL_128K_3_STATUS6 */ "", 71134 /* RTS_SRAM_LL_128K_3_STATUS7 */ "", 71135 /* RTS_SRAM_LL_128K_3_STATUS8 */ "", 71136 /* RTS_SRAM_LL_128K_3_STATUS9 */ "", 71137 /* RTS_SRAM_LL_128K_3_STATUS10 */ "", 71138 /* RTS_SRAM_LL_128K_4_CONTROL1 */ "", 71139 /* RTS_SRAM_LL_128K_4_DYNAMIC_STANDBY_CONTROL1 */ "", 71140 /* RTS_SRAM_LL_128K_4_DYNAMIC_STANDBY_CONTROL2 */ "", 71141 /* RTS_SRAM_LL_128K_4_INTERRUPT_ENABLE */ "", 71142 /* RTS_SRAM_LL_128K_4_INTERRUPT_STATUS */ "", 71143 /* RTS_SRAM_LL_128K_4_MEMORY_CONTROL */ "", 71144 /* RTS_SRAM_LL_128K_4_MEMORY_PDA */ "", 71145 /* RTS_SRAM_LL_128K_4_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71146 /* RTS_SRAM_LL_128K_4_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71147 /* RTS_SRAM_LL_128K_4_MEM_1BIT_ECC_ERR_W0B0 */ "", 71148 /* RTS_SRAM_LL_128K_4_MEM_1BIT_ECC_ERR_W0B1 */ "", 71149 /* RTS_SRAM_LL_128K_4_MEM_1BIT_ECC_ERR_W1B0 */ "", 71150 /* RTS_SRAM_LL_128K_4_MEM_1BIT_ECC_ERR_W1B1 */ "", 71151 /* RTS_SRAM_LL_128K_4_MEM_PWR_CONTROL */ "", 71152 /* RTS_SRAM_LL_128K_4_STATUS1 */ "", 71153 /* RTS_SRAM_LL_128K_4_STATUS2 */ "", 71154 /* RTS_SRAM_LL_128K_4_STATUS3 */ "", 71155 /* RTS_SRAM_LL_128K_4_STATUS4 */ "", 71156 /* RTS_SRAM_LL_128K_4_STATUS5 */ "", 71157 /* RTS_SRAM_LL_128K_4_STATUS6 */ "", 71158 /* RTS_SRAM_LL_128K_4_STATUS7 */ "", 71159 /* RTS_SRAM_LL_128K_4_STATUS8 */ "", 71160 /* RTS_SRAM_LL_128K_4_STATUS9 */ "", 71161 /* RTS_SRAM_LL_128K_4_STATUS10 */ "", 71162 /* RTS_SRAM_LL_128K_5_CONTROL1 */ "", 71163 /* RTS_SRAM_LL_128K_5_DYNAMIC_STANDBY_CONTROL1 */ "", 71164 /* RTS_SRAM_LL_128K_5_DYNAMIC_STANDBY_CONTROL2 */ "", 71165 /* RTS_SRAM_LL_128K_5_INTERRUPT_ENABLE */ "", 71166 /* RTS_SRAM_LL_128K_5_INTERRUPT_STATUS */ "", 71167 /* RTS_SRAM_LL_128K_5_MEMORY_CONTROL */ "", 71168 /* RTS_SRAM_LL_128K_5_MEMORY_PDA */ "", 71169 /* RTS_SRAM_LL_128K_5_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71170 /* RTS_SRAM_LL_128K_5_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71171 /* RTS_SRAM_LL_128K_5_MEM_1BIT_ECC_ERR_W0B0 */ "", 71172 /* RTS_SRAM_LL_128K_5_MEM_1BIT_ECC_ERR_W0B1 */ "", 71173 /* RTS_SRAM_LL_128K_5_MEM_1BIT_ECC_ERR_W1B0 */ "", 71174 /* RTS_SRAM_LL_128K_5_MEM_1BIT_ECC_ERR_W1B1 */ "", 71175 /* RTS_SRAM_LL_128K_5_MEM_PWR_CONTROL */ "", 71176 /* RTS_SRAM_LL_128K_5_STATUS1 */ "", 71177 /* RTS_SRAM_LL_128K_5_STATUS2 */ "", 71178 /* RTS_SRAM_LL_128K_5_STATUS3 */ "", 71179 /* RTS_SRAM_LL_128K_5_STATUS4 */ "", 71180 /* RTS_SRAM_LL_128K_5_STATUS5 */ "", 71181 /* RTS_SRAM_LL_128K_5_STATUS6 */ "", 71182 /* RTS_SRAM_LL_128K_5_STATUS7 */ "", 71183 /* RTS_SRAM_LL_128K_5_STATUS8 */ "", 71184 /* RTS_SRAM_LL_128K_5_STATUS9 */ "", 71185 /* RTS_SRAM_LL_128K_5_STATUS10 */ "", 71186 /* RTS_SRAM_LL_128K_6_CONTROL1 */ "", 71187 /* RTS_SRAM_LL_128K_6_DYNAMIC_STANDBY_CONTROL1 */ "", 71188 /* RTS_SRAM_LL_128K_6_DYNAMIC_STANDBY_CONTROL2 */ "", 71189 /* RTS_SRAM_LL_128K_6_INTERRUPT_ENABLE */ "", 71190 /* RTS_SRAM_LL_128K_6_INTERRUPT_STATUS */ "", 71191 /* RTS_SRAM_LL_128K_6_MEMORY_CONTROL */ "", 71192 /* RTS_SRAM_LL_128K_6_MEMORY_PDA */ "", 71193 /* RTS_SRAM_LL_128K_6_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71194 /* RTS_SRAM_LL_128K_6_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71195 /* RTS_SRAM_LL_128K_6_MEM_1BIT_ECC_ERR_W0B0 */ "", 71196 /* RTS_SRAM_LL_128K_6_MEM_1BIT_ECC_ERR_W0B1 */ "", 71197 /* RTS_SRAM_LL_128K_6_MEM_1BIT_ECC_ERR_W1B0 */ "", 71198 /* RTS_SRAM_LL_128K_6_MEM_1BIT_ECC_ERR_W1B1 */ "", 71199 /* RTS_SRAM_LL_128K_6_MEM_PWR_CONTROL */ "", 71200 /* RTS_SRAM_LL_128K_6_STATUS1 */ "", 71201 /* RTS_SRAM_LL_128K_6_STATUS2 */ "", 71202 /* RTS_SRAM_LL_128K_6_STATUS3 */ "", 71203 /* RTS_SRAM_LL_128K_6_STATUS4 */ "", 71204 /* RTS_SRAM_LL_128K_6_STATUS5 */ "", 71205 /* RTS_SRAM_LL_128K_6_STATUS6 */ "", 71206 /* RTS_SRAM_LL_128K_6_STATUS7 */ "", 71207 /* RTS_SRAM_LL_128K_6_STATUS8 */ "", 71208 /* RTS_SRAM_LL_128K_6_STATUS9 */ "", 71209 /* RTS_SRAM_LL_128K_6_STATUS10 */ "", 71210 /* RTS_SRAM_LL_128K_7_CONTROL1 */ "", 71211 /* RTS_SRAM_LL_128K_7_DYNAMIC_STANDBY_CONTROL1 */ "", 71212 /* RTS_SRAM_LL_128K_7_DYNAMIC_STANDBY_CONTROL2 */ "", 71213 /* RTS_SRAM_LL_128K_7_INTERRUPT_ENABLE */ "", 71214 /* RTS_SRAM_LL_128K_7_INTERRUPT_STATUS */ "", 71215 /* RTS_SRAM_LL_128K_7_MEMORY_CONTROL */ "", 71216 /* RTS_SRAM_LL_128K_7_MEMORY_PDA */ "", 71217 /* RTS_SRAM_LL_128K_7_MEM_1BIT_ECC_ERR_INTR_ENABLE */ "", 71218 /* RTS_SRAM_LL_128K_7_MEM_1BIT_ECC_ERR_INTR_STATUS */ "", 71219 /* RTS_SRAM_LL_128K_7_MEM_1BIT_ECC_ERR_W0B0 */ "", 71220 /* RTS_SRAM_LL_128K_7_MEM_1BIT_ECC_ERR_W0B1 */ "", 71221 /* RTS_SRAM_LL_128K_7_MEM_1BIT_ECC_ERR_W1B0 */ "", 71222 /* RTS_SRAM_LL_128K_7_MEM_1BIT_ECC_ERR_W1B1 */ "", 71223 /* RTS_SRAM_LL_128K_7_MEM_PWR_CONTROL */ "", 71224 /* RTS_SRAM_LL_128K_7_STATUS1 */ "", 71225 /* RTS_SRAM_LL_128K_7_STATUS2 */ "", 71226 /* RTS_SRAM_LL_128K_7_STATUS3 */ "", 71227 /* RTS_SRAM_LL_128K_7_STATUS4 */ "", 71228 /* RTS_SRAM_LL_128K_7_STATUS5 */ "", 71229 /* RTS_SRAM_LL_128K_7_STATUS6 */ "", 71230 /* RTS_SRAM_LL_128K_7_STATUS7 */ "", 71231 /* RTS_SRAM_LL_128K_7_STATUS8 */ "", 71232 /* RTS_SRAM_LL_128K_7_STATUS9 */ "", 71233 /* RTS_SRAM_LL_128K_7_STATUS10 */ "", 71234 /* RTUN */ "", 71235 /* RTUN_64 */ "RTUN", 71236 /* RUC */ "", 71237 /* RUCA */ "MAC_GRxUCA", 71238 /* RUC_64 */ "RUC", 71239 /* RUC_BYTE */ "", 71240 /* RUND */ "MAC_GRxUND", 71241 /* RVERIFY */ "XLMIB_GRxVerify", 71242 /* RVLN */ "MAC_GRxVLN", 71243 /* RVTAG3 */ "", 71244 /* RXCESCW_CHID_0 */ "", 71245 /* RXCESCW_CHID_1 */ "", 71246 /* RXCESCW_CHID_2 */ "", 71247 /* RXCESCW_CHID_3 */ "", 71248 /* RXCESCW_CHID_4 */ "", 71249 /* RXCESCW_CHID_5 */ "", 71250 /* RXCESCW_CHID_6 */ "", 71251 /* RXCESCW_CHID_7 */ "", 71252 /* RXCESCW_CHID_8 */ "", 71253 /* RXCESCW_CHID_9 */ "", 71254 /* RXCESCW_CHID_10 */ "", 71255 /* RXCESCW_CHID_11 */ "", 71256 /* RXCESCW_CHID_12 */ "", 71257 /* RXCESCW_CHID_13 */ "", 71258 /* RXCESCW_CHID_14 */ "", 71259 /* RXCESCW_CHID_15 */ "", 71260 /* RXCESCW_CHID_16 */ "", 71261 /* RXCESCW_CHID_17 */ "", 71262 /* RXCESCW_CHID_18 */ "", 71263 /* RXCESCW_CHID_19 */ "", 71264 /* RXCESCW_CHID_20 */ "", 71265 /* RXCESCW_CHID_21 */ "", 71266 /* RXCESCW_CHID_22 */ "", 71267 /* RXCESCW_CHID_23 */ "", 71268 /* RXCESCW_CHID_24 */ "", 71269 /* RXCESCW_CHID_25 */ "", 71270 /* RXCESCW_CHID_26 */ "", 71271 /* RXCESCW_CHID_27 */ "", 71272 /* RXCESCW_CHID_28 */ "", 71273 /* RXCESCW_CHID_29 */ "", 71274 /* RXCESCW_CHID_30 */ "", 71275 /* RXCESCW_CHID_31 */ "", 71276 /* RXCESCW_CHID_32 */ "", 71277 /* RXCESCW_CHID_33 */ "", 71278 /* RXCESCW_CHID_34 */ "", 71279 /* RXCESCW_CHID_35 */ "", 71280 /* RXCESCW_CHID_36 */ "", 71281 /* RXCESCW_CHID_37 */ "", 71282 /* RXCESCW_CHID_38 */ "", 71283 /* RXCESCW_CHID_39 */ "", 71284 /* RXCESCW_CHID_40 */ "", 71285 /* RXCESCW_CHID_41 */ "", 71286 /* RXCESCW_CHID_42 */ "", 71287 /* RXCESCW_CHID_43 */ "", 71288 /* RXCESCW_CHID_44 */ "", 71289 /* RXCESCW_CHID_45 */ "", 71290 /* RXCESCW_CHID_46 */ "", 71291 /* RXCESCW_CHID_47 */ "", 71292 /* RXCESCW_CHID_48 */ "", 71293 /* RXCESCW_CHID_49 */ "", 71294 /* RXCESCW_CHID_50 */ "", 71295 /* RXCESCW_CHID_51 */ "", 71296 /* RXCESCW_CHID_52 */ "", 71297 /* RXCESCW_CHID_53 */ "", 71298 /* RXCESCW_CHID_54 */ "", 71299 /* RXCESCW_CHID_55 */ "", 71300 /* RXCESCW_CHID_56 */ "", 71301 /* RXCESCW_CHID_57 */ "", 71302 /* RXCESCW_CHID_58 */ "", 71303 /* RXCESCW_CHID_59 */ "", 71304 /* RXCESCW_CHID_60 */ "", 71305 /* RXCESCW_CHID_61 */ "", 71306 /* RXCESCW_CHID_62 */ "", 71307 /* RXCESCW_CHID_63 */ "", 71308 /* RXCF */ "MAC_GRxCF", 71309 /* RXCHCFG_CHID_0 */ "", 71310 /* RXCHCFG_CHID_1 */ "", 71311 /* RXCHCFG_CHID_2 */ "", 71312 /* RXCHCFG_CHID_3 */ "", 71313 /* RXCHCFG_CHID_4 */ "", 71314 /* RXCHCFG_CHID_5 */ "", 71315 /* RXCHCFG_CHID_6 */ "", 71316 /* RXCHCFG_CHID_7 */ "", 71317 /* RXCHCFG_CHID_8 */ "", 71318 /* RXCHCFG_CHID_9 */ "", 71319 /* RXCHCFG_CHID_10 */ "", 71320 /* RXCHCFG_CHID_11 */ "", 71321 /* RXCHCFG_CHID_12 */ "", 71322 /* RXCHCFG_CHID_13 */ "", 71323 /* RXCHCFG_CHID_14 */ "", 71324 /* RXCHCFG_CHID_15 */ "", 71325 /* RXCHCFG_CHID_16 */ "", 71326 /* RXCHCFG_CHID_17 */ "", 71327 /* RXCHCFG_CHID_18 */ "", 71328 /* RXCHCFG_CHID_19 */ "", 71329 /* RXCHCFG_CHID_20 */ "", 71330 /* RXCHCFG_CHID_21 */ "", 71331 /* RXCHCFG_CHID_22 */ "", 71332 /* RXCHCFG_CHID_23 */ "", 71333 /* RXCHCFG_CHID_24 */ "", 71334 /* RXCHCFG_CHID_25 */ "", 71335 /* RXCHCFG_CHID_26 */ "", 71336 /* RXCHCFG_CHID_27 */ "", 71337 /* RXCHCFG_CHID_28 */ "", 71338 /* RXCHCFG_CHID_29 */ "", 71339 /* RXCHCFG_CHID_30 */ "", 71340 /* RXCHCFG_CHID_31 */ "", 71341 /* RXCHCFG_CHID_32 */ "", 71342 /* RXCHCFG_CHID_33 */ "", 71343 /* RXCHCFG_CHID_34 */ "", 71344 /* RXCHCFG_CHID_35 */ "", 71345 /* RXCHCFG_CHID_36 */ "", 71346 /* RXCHCFG_CHID_37 */ "", 71347 /* RXCHCFG_CHID_38 */ "", 71348 /* RXCHCFG_CHID_39 */ "", 71349 /* RXCHCFG_CHID_40 */ "", 71350 /* RXCHCFG_CHID_41 */ "", 71351 /* RXCHCFG_CHID_42 */ "", 71352 /* RXCHCFG_CHID_43 */ "", 71353 /* RXCHCFG_CHID_44 */ "", 71354 /* RXCHCFG_CHID_45 */ "", 71355 /* RXCHCFG_CHID_46 */ "", 71356 /* RXCHCFG_CHID_47 */ "", 71357 /* RXCHCFG_CHID_48 */ "", 71358 /* RXCHCFG_CHID_49 */ "", 71359 /* RXCHCFG_CHID_50 */ "", 71360 /* RXCHCFG_CHID_51 */ "", 71361 /* RXCHCFG_CHID_52 */ "", 71362 /* RXCHCFG_CHID_53 */ "", 71363 /* RXCHCFG_CHID_54 */ "", 71364 /* RXCHCFG_CHID_55 */ "", 71365 /* RXCHCFG_CHID_56 */ "", 71366 /* RXCHCFG_CHID_57 */ "", 71367 /* RXCHCFG_CHID_58 */ "", 71368 /* RXCHCFG_CHID_59 */ "", 71369 /* RXCHCFG_CHID_60 */ "", 71370 /* RXCHCFG_CHID_61 */ "", 71371 /* RXCHCFG_CHID_62 */ "", 71372 /* RXCHCFG_CHID_63 */ "", 71373 /* RXE2EIBPBKPSTATUS */ "", 71374 /* RXERRDSCRDSPKTS_ECC_STATUS */ "", 71375 /* RXFIFO_STAT */ "", 71376 /* RXFILLTH */ "", 71377 /* RXLP_COUNTER_MEM_PARITY_STATUS */ "", 71378 /* RXLP_COUNTER_MEM_PARITY_STATUS_NACK */ "", 71379 /* RXLP_CTRLBUF_ECC_STATUS */ "", 71380 /* RXLP_DATABUF_ECC_STATUS */ "", 71381 /* RXLP_DEBUG_COUNTER0_TRIGGER_SELECT */ "", 71382 /* RXLP_DEBUG_COUNTER1_TRIGGER_SELECT */ "", 71383 /* RXLP_DEBUG_COUNTER2_TRIGGER_SELECT */ "", 71384 /* RXLP_DEBUG_COUNTER3_TRIGGER_SELECT */ "", 71385 /* RXLP_DEBUG_COUNTER4_TRIGGER_SELECT */ "", 71386 /* RXLP_DEBUG_COUNTER5_TRIGGER_SELECT */ "", 71387 /* RXLP_DEBUG_COUNTER6_TRIGGER_SELECT */ "", 71388 /* RXLP_DEBUG_COUNTER7_TRIGGER_SELECT */ "", 71389 /* RXLP_DFC_CPU_UPDATE_REFRESH */ "", 71390 /* RXLP_DFC_FRAMES */ "", 71391 /* RXLP_DFC_FRAME_UNEXPECTED_MACDA */ "", 71392 /* RXLP_DFC_FRAME_UNEXPECTED_MACSA */ "", 71393 /* RXLP_DFC_HEADER_OPCODE_ERROR */ "", 71394 /* RXLP_DFC_HEADER_TIME_ERROR */ "", 71395 /* RXLP_DFC_LENGTH_CHECK_CONTROL */ "", 71396 /* RXLP_DFC_LENGTH_ERROR */ "", 71397 /* RXLP_DFC_MSG_START_BYTE_OFFSET */ "", 71398 /* RXLP_DFC_STATUS_CPU_UPDATE_ENABLE_HI */ "", 71399 /* RXLP_DFC_STATUS_CPU_UPDATE_ENABLE_LO */ "", 71400 /* RXLP_DFC_STATUS_HI */ "", 71401 /* RXLP_DFC_STATUS_LO */ "", 71402 /* RXLP_ECC_INTERRUPT_ENABLE */ "", 71403 /* RXLP_ECC_INTERRUPT_STATUS */ "", 71404 /* RXLP_ECC_PARITY_CONTROL */ "", 71405 /* RXLP_HW_RESET_CONTROL */ "", 71406 /* RXLP_IARBBUF_ECC_STATUS */ "", 71407 /* RXLP_INTERRUPT_DATA_LOG_ENABLE */ "", 71408 /* RXLP_INTERRUPT_DATA_LOG_VALID */ "", 71409 /* RXLP_INTERRUPT_DATA_SOURCE */ "", 71410 /* RXLP_INTERRUPT_ENABLE */ "", 71411 /* RXLP_INTERRUPT_STATUS */ "", 71412 /* RXLP_INT_STREAM_ID_BASE */ "", 71413 /* RXLP_LENGTH_FIELD_SELECTOR */ "", 71414 /* RXLP_PORT_ACTIVE_STREAM_BITMAP_HI */ "", 71415 /* RXLP_PORT_ACTIVE_STREAM_BITMAP_LO */ "", 71416 /* RXLP_PORT_DFC_DESTINATION_MAC_ADDR */ "", 71417 /* RXLP_PORT_DFC_MAC_TYPE */ "", 71418 /* RXLP_PORT_DFC_OPCODE */ "", 71419 /* RXLP_PORT_DFC_TIME */ "", 71420 /* RXLP_PORT_ENABLE */ "", 71421 /* RXLP_PORT_FAR_END_MAC_ADDR */ "", 71422 /* RXLP_PORT_LP_MODE_CONTROL */ "", 71423 /* RXLP_PORT_NEAR_END_MAC_ADDR */ "", 71424 /* RXLP_PORT_PURGE_CONTROL */ "", 71425 /* RXLP_PORT_STREAM_ID_BASE */ "", 71426 /* RXLP_PORT_VLAN_TPID */ "", 71427 /* RXLP_PURGE_MASTER_OVERRIDE */ "", 71428 /* RXLP_RAM_CONTROL_0 */ "", 71429 /* RXLP_RAM_CONTROL_1 */ "", 71430 /* RXLP_RAM_CONTROL_2 */ "", 71431 /* RXLP_RESIDUAL_CRC_ECC_STATUS */ "", 71432 /* RXLP_SW_FLUSH_CONTROL */ "", 71433 /* RXLP_TCI_FIELD_SELECTOR */ "", 71434 /* RXLP_TRIGGER_MEM_PARITY_STATUS */ "", 71435 /* RXLP_TRIGGER_MEM_PARITY_STATUS_NACK */ "", 71436 /* RXLP_UNEXPECTED_ETHERTYPE */ "", 71437 /* RXLP_UNKNOWN_STREAM_ID */ "", 71438 /* RXPACKETTYPE_ECC_STATUS */ "", 71439 /* RXPF */ "MAC_GRxPF", 71440 /* RXPP */ "MAC_GRxPP", 71441 /* RXSASTATSINVALIDPKTS_ECC_STATUS */ "", 71442 /* RXSASTATSNOTUSINGSAPKTS_ECC_STATUS */ "", 71443 /* RXSASTATSNOTVALIDPKTS_ECC_STATUS */ "", 71444 /* RXSASTATSOKPKTS_ECC_STATUS */ "", 71445 /* RXSASTATSUNUSEDSAPKTS_ECC_STATUS */ "", 71446 /* RXSCIUNKNOWNNONEPKTS_ECC_STATUS */ "", 71447 /* RXSCSTATSDELAYEDPKTS_ECC_STATUS */ "", 71448 /* RXSCSTATSINVALIDPKTS_ECC_STATUS */ "", 71449 /* RXSCSTATSLATEPKTS_ECC_STATUS */ "", 71450 /* RXSCSTATSNOTUSINGSAPKTS_ECC_STATUS */ "", 71451 /* RXSCSTATSNOTVALIDPKTS_ECC_STATUS */ "", 71452 /* RXSCSTATSOCTETSDECRYPTED_ECC_STATUS */ "", 71453 /* RXSCSTATSOCTETSVALIDATED_ECC_STATUS */ "", 71454 /* RXSCSTATSOKPKTS_ECC_STATUS */ "", 71455 /* RXSCSTATSUNCHECKEDPKTS_ECC_STATUS */ "", 71456 /* RXSCSTATSUNUSEDSAPKTS_ECC_STATUS */ "", 71457 /* RXTAGUNTAGNONEBAD_ECC_STATUS */ "", 71458 /* RXUDA */ "MAC_GRxUDA", 71459 /* RXUO */ "MAC_GRxUO", 71460 /* RXWSA */ "MAC_GRxWSA", 71461 /* RX_EEE_LPI_DURATION_COUNTER */ "XLMIB_RX_EEE_LPI_DURATION_COUNTER", 71462 /* RX_EEE_LPI_EVENT_COUNTER */ "XLMIB_RX_EEE_LPI_EVENT_COUNTER", 71463 /* RX_HCFC_COUNTER */ "XLMIB_RX_HCFC_COUNTER", 71464 /* RX_HCFC_CRC_COUNTER */ "XLMIB_RX_HCFC_CRC_COUNTER", 71465 /* RX_LLFC_CRC_COUNTER */ "XLMIB_RX_LLFC_CRC_COUNTER", 71466 /* RX_LLFC_LOG_COUNTER */ "XLMIB_RX_LLFC_LOG_COUNTER", 71467 /* RX_LLFC_PHY_COUNTER */ "XLMIB_RX_LLFC_PHY_COUNTER", 71468 /* RX_PAUSE_QUANTA_SCALE */ "", 71469 /* RX_PROT_GROUP_TABLE_1_DMA_PARITY_CONTROL */ "", 71470 /* RX_PROT_GROUP_TABLE_1_DMA_PARITY_STATUS_INTR */ "", 71471 /* RX_PROT_GROUP_TABLE_1_DMA_PARITY_STATUS_NACK */ "", 71472 /* RX_PROT_GROUP_TABLE_DBGCTRL */ "RX_PROT_GROUP_TABLE_CONTROL", 71473 /* RX_PROT_GROUP_TABLE_DMA_PARITY_CONTROL */ "", 71474 /* RX_PROT_GROUP_TABLE_DMA_PARITY_STATUS_INTR */ "", 71475 /* RX_PROT_GROUP_TABLE_DMA_PARITY_STATUS_NACK */ "", 71476 /* RX_X1_CONTROL0_CL91_CONFIG */ "", 71477 /* RX_X1_CONTROL0_DECODE_CONTROL_1 */ "", 71478 /* RX_X1_CONTROL0_DESKEW_WINDOWS_0 */ "", 71479 /* RX_X1_CONTROL0_DESKEW_WINDOWS_1 */ "", 71480 /* RX_X1_CONTROL0_RF_MEM_CTRL */ "", 71481 /* RX_X1_CONTROL0_RS_FEC_CONFIG */ "", 71482 /* RX_X1_CONTROL0_RX_LANE_SWAP */ "", 71483 /* RX_X1_CONTROL0_SRF_MEM_CTRL */ "", 71484 /* RX_X1_ECC_CORRUPT_0 */ "", 71485 /* RX_X1_ECC_DISABLE_ECC_MEM */ "", 71486 /* RX_X1_ECC_ECC_STATUS_AM_TBL */ "", 71487 /* RX_X1_ECC_ECC_STATUS_BASE_R_FEC */ "", 71488 /* RX_X1_ECC_ECC_STATUS_DESKEW */ "", 71489 /* RX_X1_ECC_ECC_STATUS_RSFEC_RBUF_MPP */ "", 71490 /* RX_X1_ECC_ECC_STATUS_RSFEC_RS400G_MPP */ "", 71491 /* RX_X1_ECC_ECC_STATUS_RX_1588_400G */ "", 71492 /* RX_X1_ECC_ECC_STATUS_RX_1588_MPP */ "", 71493 /* RX_X1_ECC_ECC_STATUS_SPD_TBL */ "", 71494 /* RX_X1_ECC_ECC_STATUS_TX_1588_400G */ "", 71495 /* RX_X1_ECC_ECC_STATUS_TX_1588_MPP */ "", 71496 /* RX_X1_ECC_ECC_STATUS_UM_TBL */ "", 71497 /* RX_X1_ECC_INTERRUPT_EN_1BIT */ "", 71498 /* RX_X1_ECC_INTERRUPT_EN_2BIT */ "", 71499 /* RX_X1_ECC_INTERRUPT_STATUS_1BIT */ "", 71500 /* RX_X1_ECC_INTERRUPT_STATUS_2BIT */ "", 71501 /* RX_X1_ECC_STATUS_FEC_MEM_0 */ "", 71502 /* RX_X1_ECC_STATUS_FEC_MEM_1 */ "", 71503 /* RX_X1_ECC_STATUS_FEC_MEM_2 */ "", 71504 /* RX_X1_ECC_STATUS_FEC_MEM_3 */ "", 71505 /* RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_HI */ "", 71506 /* RX_X1_STATUS0_STATUS_CL91_FEC_RAM1_LO */ "", 71507 /* RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_HI */ "", 71508 /* RX_X1_STATUS0_STATUS_CL91_FEC_RAM2_LO */ "", 71509 /* RX_X2_CONTROL0_MISC_0 */ "", 71510 /* RX_X2_CONTROL0_MISC_1 */ "", 71511 /* RX_X2_STATUS0_CL82_SCRIDLE_TEST_ERR */ "", 71512 /* RX_X4_CL91_STATUS0_CL91_RXP_STATUS */ "", 71513 /* RX_X4_CL91_STATUS0_FEC_ALGN_FSM_STATE */ "", 71514 /* RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_0 */ "", 71515 /* RX_X4_CL91_STATUS0_FEC_BIT_ERROR_COUNTER_1 */ "", 71516 /* RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_0 */ "", 71517 /* RX_X4_CL91_STATUS0_FEC_CORRECTED_COUNTER_1 */ "", 71518 /* RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_0 */ "", 71519 /* RX_X4_CL91_STATUS0_FEC_UNCORRECTED_COUNTER_1 */ "", 71520 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_0 */ "", 71521 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_1 */ "", 71522 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_2 */ "", 71523 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_LOW_3 */ "", 71524 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_0 */ "", 71525 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_1 */ "", 71526 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_2 */ "", 71527 /* RX_X4_CL91_STATUS1_CL91_FEC_SYMB_ERR_CNTR_UP_3 */ "", 71528 /* RX_X4_CONTROL0_BLKSYNC_CONFIG */ "", 71529 /* RX_X4_CONTROL0_CL36RX_CONTROL */ "", 71530 /* RX_X4_CONTROL0_CL91_RX_CONTROL_0 */ "", 71531 /* RX_X4_CONTROL0_CL91_THRESHOLD */ "", 71532 /* RX_X4_CONTROL0_CL91_TIMER */ "", 71533 /* RX_X4_CONTROL0_DECODE_CONTROL_0 */ "", 71534 /* RX_X4_CONTROL0_IEEE_25G_PARLLEL_DET_CTR */ "", 71535 /* RX_X4_CONTROL0_LINK_CONTROL */ "", 71536 /* RX_X4_CONTROL0_PCS_CONTROL_0 */ "", 71537 /* RX_X4_CONTROL0_PMA_CONTROL_0 */ "", 71538 /* RX_X4_CONTROL0_RS_FEC_RX_CONTROL_0 */ "", 71539 /* RX_X4_CONTROL0_RS_FEC_TIMER */ "", 71540 /* RX_X4_CONTROL0_RX_TS_CONTROL */ "", 71541 /* RX_X4_CONTROL0_SYNCE_FRACTIONAL_DIV */ "", 71542 /* RX_X4_CONTROL1_RXP_1588_SFD_TS_CONTROL */ "", 71543 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_FRAC_0 */ "", 71544 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_FRAC_1 */ "", 71545 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_FRAC_2 */ "", 71546 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_FRAC_3 */ "", 71547 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_FRAC_4 */ "", 71548 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_INT_0 */ "", 71549 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_INT_1 */ "", 71550 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_INT_2 */ "", 71551 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_INT_3 */ "", 71552 /* RX_X4_CONTROL1_RX_DESKEW_ADJ_INT_4 */ "", 71553 /* RX_X4_ECC_CORRUPT */ "", 71554 /* RX_X4_ECC_DISABLE_ECC_MEM */ "", 71555 /* RX_X4_ECC_INTERRUPT_EN_1BIT */ "", 71556 /* RX_X4_ECC_INTERRUPT_EN_2BIT */ "", 71557 /* RX_X4_ECC_INTERRUPT_STATUS_1BIT */ "", 71558 /* RX_X4_ECC_INTERRUPT_STATUS_2BIT */ "", 71559 /* RX_X4_ECC_STATUS_CL91_BUFFER_BLK_0 */ "", 71560 /* RX_X4_ECC_STATUS_CL91_BUFFER_BLK_1 */ "", 71561 /* RX_X4_ECC_STATUS_CL91_BUFFER_BLK_2 */ "", 71562 /* RX_X4_ECC_STATUS_DESKEW_MEM_0 */ "", 71563 /* RX_X4_ECC_STATUS_DESKEW_MEM_1 */ "", 71564 /* RX_X4_ECC_STATUS_DESKEW_MEM_2 */ "", 71565 /* RX_X4_FEC_CONTROL_FEC_0 */ "", 71566 /* RX_X4_FEC_CONTROL_FEC_1 */ "", 71567 /* RX_X4_FEC_CONTROL_FEC_2 */ "", 71568 /* RX_X4_FEC_CONTROL_FEC_3 */ "", 71569 /* RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_0 */ "", 71570 /* RX_X4_RS_FEC_STATUS0_FEC_BIT_ERROR_COUNTER_1 */ "", 71571 /* RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_0 */ "", 71572 /* RX_X4_RS_FEC_STATUS0_FEC_CORRECTED_COUNTER_1 */ "", 71573 /* RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_0 */ "", 71574 /* RX_X4_RS_FEC_STATUS0_FEC_UNCORRECTED_COUNTER_1 */ "", 71575 /* RX_X4_RS_FEC_STATUS0_RS_FEC_RXP_STATUS */ "", 71576 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_0 */ "", 71577 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_1 */ "", 71578 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_2 */ "", 71579 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_LOW_3 */ "", 71580 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_0 */ "", 71581 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_1 */ "", 71582 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_2 */ "", 71583 /* RX_X4_RS_FEC_STATUS1_RS_FEC_FEC_SYMB_ERR_CNTR_UP_3 */ "", 71584 /* RX_X4_STATUS0_AM_LOCK_LATCHED_STATUS */ "", 71585 /* RX_X4_STATUS0_BIPCOUNT_0 */ "", 71586 /* RX_X4_STATUS0_BIPCOUNT_1 */ "", 71587 /* RX_X4_STATUS0_BIPCOUNT_2 */ "", 71588 /* RX_X4_STATUS0_BLKSYNC_DBG0 */ "", 71589 /* RX_X4_STATUS0_BLKSYNC_DBG1 */ "", 71590 /* RX_X4_STATUS0_BLKSYNC_DBG2 */ "", 71591 /* RX_X4_STATUS0_BLKSYNC_STATUS */ "", 71592 /* RX_X4_STATUS0_BLOCK_LOCK_LATCHED_STATUS */ "", 71593 /* RX_X4_STATUS0_CL91_FC_STATUS */ "", 71594 /* RX_X4_STATUS0_PCS_LIVE_STATUS_0 */ "", 71595 /* RX_X4_STATUS0_PSLL_TO_VL_MAPPING_0 */ "", 71596 /* RX_X4_STATUS0_PSLL_TO_VL_MAPPING_1 */ "", 71597 /* RX_X4_STATUS0_RS_SYMBOL */ "", 71598 /* RX_X4_STATUS1_BER_HO */ "", 71599 /* RX_X4_STATUS1_BER_LO */ "", 71600 /* RX_X4_STATUS1_CL36RX_BERCOUNT */ "", 71601 /* RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_0 */ "", 71602 /* RX_X4_STATUS1_CL36RX_SYNCACQ_STATUS_1 */ "", 71603 /* RX_X4_STATUS1_CL49_SCRIDLE_TEST_ERR */ "", 71604 /* RX_X4_STATUS1_DECODE_STATUS_0 */ "", 71605 /* RX_X4_STATUS1_DECODE_STATUS_1 */ "", 71606 /* RX_X4_STATUS1_DECODE_STATUS_2 */ "", 71607 /* RX_X4_STATUS1_DECODE_STATUS_3 */ "", 71608 /* RX_X4_STATUS1_ERRORED_BLOCKS_HO */ "", 71609 /* RX_X4_STATUS1_IEEE_25G_PARLLEL_DET_STS */ "", 71610 /* RX_X4_STATUS1_PCS_LATCHED_STATUS_1 */ "", 71611 /* RX_X4_STATUS1_PCS_LIVE_STATUS_1 */ "", 71612 /* RX_X4_STATUS1_RL_MODE_HW_STATUS */ "", 71613 /* RX_X4_STATUS1_RL_MODE_SW_CONTROL */ "", 71614 /* RX_X4_STATUS1_RX_LATCHED_STATUS */ "", 71615 /* RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_0 */ "", 71616 /* RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_1 */ "", 71617 /* RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_2 */ "", 71618 /* RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_3 */ "", 71619 /* RX_X4_STATUS2_CL82_RX_AM_LATCHED_STATUS_PSLL_4 */ "", 71620 /* RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_0 */ "", 71621 /* RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_1 */ "", 71622 /* RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_2 */ "", 71623 /* RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_3 */ "", 71624 /* RX_X4_STATUS2_CL82_RX_AM_LIVE_STATUS_PSLL_4 */ "", 71625 /* RX_X4_STATUS2_CL91_FC_SLIP_CNT */ "", 71626 /* RX_X4_STATUS2_CL91_SYNC_STATUS */ "", 71627 /* RX_X4_STATUS2_FEC_SYNC_FSM_STATE */ "", 71628 /* RX_X4_STATUS2_RS_FEC_SYNC_STATUS */ "", 71629 /* RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_0 */ "", 71630 /* RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_1 */ "", 71631 /* RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_2 */ "", 71632 /* RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_3 */ "", 71633 /* RX_X4_STATUS3_FEC_BURST_ERR_STATUSL_4 */ "", 71634 /* RX_X4_STATUS3_FEC_DBG_ERRAH_0 */ "", 71635 /* RX_X4_STATUS3_FEC_DBG_ERRAH_1 */ "", 71636 /* RX_X4_STATUS3_FEC_DBG_ERRAH_2 */ "", 71637 /* RX_X4_STATUS3_FEC_DBG_ERRAH_3 */ "", 71638 /* RX_X4_STATUS3_FEC_DBG_ERRAH_4 */ "", 71639 /* RX_X4_STATUS3_FEC_DBG_ERRL_0 */ "", 71640 /* RX_X4_STATUS3_FEC_DBG_ERRL_1 */ "", 71641 /* RX_X4_STATUS3_FEC_DBG_ERRL_2 */ "", 71642 /* RX_X4_STATUS3_FEC_DBG_ERRL_3 */ "", 71643 /* RX_X4_STATUS3_FEC_DBG_ERRL_4 */ "", 71644 /* RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_0 */ "", 71645 /* RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_1 */ "", 71646 /* RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_2 */ "", 71647 /* RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_3 */ "", 71648 /* RX_X4_STATUS4_FEC_BURST_ERR_STATUSH_4 */ "", 71649 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSH_0 */ "", 71650 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSH_1 */ "", 71651 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSH_2 */ "", 71652 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSH_3 */ "", 71653 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSH_4 */ "", 71654 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSL_0 */ "", 71655 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSL_1 */ "", 71656 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSL_2 */ "", 71657 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSL_3 */ "", 71658 /* RX_X4_STATUS4_FEC_CORRECTEDBLKSL_4 */ "", 71659 /* RX_X4_STATUS4_PRTPERRORCOUNTER */ "", 71660 /* RX_X4_STATUS4_PRTPSTATUS */ "", 71661 /* RX_X4_STATUS5_AM_TS_INFO_0 */ "", 71662 /* RX_X4_STATUS5_AM_TS_INFO_1 */ "", 71663 /* RX_X4_STATUS5_AM_TS_INFO_2 */ "", 71664 /* RX_X4_STATUS5_AM_TS_INFO_3 */ "", 71665 /* RX_X4_STATUS5_AM_TS_INFO_4 */ "", 71666 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_0 */ "", 71667 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_1 */ "", 71668 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_2 */ "", 71669 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_3 */ "", 71670 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSH_4 */ "", 71671 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_0 */ "", 71672 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_1 */ "", 71673 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_2 */ "", 71674 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_3 */ "", 71675 /* RX_X4_STATUS5_FEC_UNCORRECTEDBLKSL_4 */ "", 71676 /* RX_X4_STATUS5_SKEW_OFFSETS_0 */ "", 71677 /* RX_X4_STATUS5_SKEW_OFFSETS_1 */ "", 71678 /* RX_X4_STATUS5_SKEW_OFFSETS_2 */ "", 71679 /* RX_X4_STATUS5_SKEW_OFFSETS_3 */ "", 71680 /* RX_X4_STATUS5_SKEW_OFFSETS_4 */ "", 71681 /* RX_X4_STATUS6_RX_DESKEW_AM_OFFSET0 */ "", 71682 /* RX_X4_STATUS6_RX_DESKEW_AM_OFFSET1 */ "", 71683 /* RX_X4_STATUS6_RX_DESKEW_AM_OFFSET2 */ "", 71684 /* RX_X4_STATUS6_RX_DESKEW_AM_OFFSET3 */ "", 71685 /* RX_X4_STATUS6_RX_DESKEW_AM_OFFSET4 */ "", 71686 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_ADJ0 */ "", 71687 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_ADJ1 */ "", 71688 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_ADJ2 */ "", 71689 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_ADJ3 */ "", 71690 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_ADJ4 */ "", 71691 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_CALC0 */ "", 71692 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_CALC1 */ "", 71693 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_CALC2 */ "", 71694 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_CALC3 */ "", 71695 /* RX_X4_STATUS6_RX_DESKEW_BASE_TS_CALC4 */ "", 71696 /* RX_X4_TEST_STATUS0_CL82_SCRIDLE_TEST_ERR */ "", 71697 /* R_64 */ "", 71698 /* R_127 */ "", 71699 /* R_255 */ "", 71700 /* R_511 */ "", 71701 /* R_1023 */ "", 71702 /* R_1518 */ "", 71703 /* R_2047 */ "", 71704 /* R_4095 */ "", 71705 /* R_9216 */ "", 71706 /* R_16383 */ "", 71707 /* S1V_CONFIG */ "", 71708 /* S1V_COSMASK */ "", 71709 /* S1V_COSWEIGHTS */ "", 71710 /* S1V_MINSPCONFIG */ "", 71711 /* S1V_WDRRCOUNT */ "", 71712 /* S2_CONFIG */ "", 71713 /* S2_COSMASK */ "", 71714 /* S2_COSWEIGHTS */ "", 71715 /* S2_MAXBUCKET */ "", 71716 /* S2_MAXBUCKETCONFIG_64 */ "MAXBUCKETCONFIG", 71717 /* S2_MINBUCKET */ "", 71718 /* S2_MINBUCKETCONFIG_64 */ "MINBUCKETCONFIG", 71719 /* S2_MINSPCONFIG */ "", 71720 /* S2_S3_ROUTING */ "", 71721 /* S2_WERRCOUNT */ "", 71722 /* S3_CONFIG */ "", 71723 /* S3_CONFIG_MC */ "", 71724 /* S3_COSMASK */ "", 71725 /* S3_COSMASK_MC */ "", 71726 /* S3_COSWEIGHTS */ "", 71727 /* S3_MAXBUCKET */ "", 71728 /* S3_MAXBUCKETCONFIG_64 */ "MAXBUCKETCONFIG", 71729 /* S3_MINBUCKET */ "", 71730 /* S3_MINBUCKETCONFIG_64 */ "MINBUCKETCONFIG", 71731 /* S3_MINSPCONFIG */ "", 71732 /* S3_MINSPCONFIG_MC */ "", 71733 /* S3_WERRCOUNT */ "", 71734 /* SA1_ECC_STATUS */ "", 71735 /* SA2_ECC_STATUS */ "", 71736 /* SAFC_PRI2COS_MAPPING_1 */ "", 71737 /* SAFC_PRI2COS_MAPPING_2 */ "", 71738 /* SAFC_RX_CONFIG_XPORT0 */ "", 71739 /* SAFC_RX_CONFIG_XPORT1 */ "", 71740 /* SAFC_RX_CONFIG_XPORT2 */ "", 71741 /* SAFC_RX_CONFIG_XPORT3 */ "", 71742 /* SAV_THDI_CFG_TM */ "", 71743 /* SBS_CONTROL */ "", 71744 /* SBS_IDB_CONTROL */ "", 71745 /* SBS_ISW4_CONTROL */ "", 71746 /* SCH_ASSIGNED_CREDIT_CONFIGURATION */ "", 71747 /* SCH_ASSIGNED_CREDIT_CONFIGURATION_1 */ "", 71748 /* SCH_ATTEMPTTO_ACTIVATE_ASHAPERWITH_BAD_PARAMETERS */ "", 71749 /* SCH_ATTEMPT_TO_ACTIVATE_A_SHAPER_WITH_BAD_PARAMETERS */ "", 71750 /* SCH_ATTEMPT_TO_ACTIVATE_BAD_FLOW_PARAMS */ "", 71751 /* SCH_ATTEMPT_TO_ACTIVATE_FLOW___SCHEDULER_WITH_BAD_PARAMETERS */ "", 71752 /* SCH_BFC_PARAMS */ "", 71753 /* SCH_CIR_SHAPERS_CONFIGURATION */ "", 71754 /* SCH_CIR_SHAPERS_CONFIGURATION_1 */ "", 71755 /* SCH_CREDIT_COUNTER */ "", 71756 /* SCH_CREDIT_COUNTER_CONFIGURATION_REG_1 */ "", 71757 /* SCH_CREDIT_COUNTER_CONFIGURATION_REG_2 */ "", 71758 /* SCH_CREDIT_SCHEDULER_COUNTER_IN_THE_CML_CONFIGURATION */ "", 71759 /* SCH_DBG_CML_CREDIT_SCHEDULER_COUNTER_CONFIGURATION */ "", 71760 /* SCH_DBG_CML_CREDIT_SCHEDULER_COUNTER_CONFIGURRATION */ "", 71761 /* SCH_DBG_CML_SCHEDULER_COUNTER */ "", 71762 /* SCH_DBG_CREDIT_COUNTER */ "", 71763 /* SCH_DBG_DVS_CREDIT_COUNTER_CONFIGURATION */ "", 71764 /* SCH_DBG_DVS_FC_COUNTERS_CONFIGURATION */ "", 71765 /* SCH_DBG_DVS_FLOW_CONTROL_COUNTER */ "", 71766 /* SCH_DBG_DVS_LINK_STATUS */ "", 71767 /* SCH_DBG_DVS_RCI_COUNTER */ "", 71768 /* SCH_DBG_DVS_RCI_COUNTERS_CONFIGURATION */ "", 71769 /* SCH_DBG_SMP_MESSAGE_COUNTER */ "", 71770 /* SCH_DBG_SMP_MESSAGE_COUNTER_CONFIGURATION */ "", 71771 /* SCH_DELETE_MECHANISM_CONFIGURATION_REGISTER */ "", 71772 /* SCH_DVS_CONFIG */ "", 71773 /* SCH_DVS_CONFIG_0 */ "", 71774 /* SCH_DVS_CONFIG_1 */ "", 71775 /* SCH_DVS_CONFIG_2 */ "", 71776 /* SCH_DVS_CREDIT_COUNTER */ "", 71777 /* SCH_DVS_CREDIT_COUNTER_CONFIGURATION_REGISTER */ "", 71778 /* SCH_DVS_CREDIT_SHARE_CONFIGURATION */ "", 71779 /* SCH_DVS_FC_COUNTERS_CONFIGURATION_REGISTER */ "", 71780 /* SCH_DVS_FLOW_CONTROL_COUNTER */ "", 71781 /* SCH_DVS_LINK_STATUS */ "", 71782 /* SCH_DVS_NIF_CONFIG */ "", 71783 /* SCH_DVS_RCI_COUNTER */ "", 71784 /* SCH_DVS_RCI_COUNTERS_CONFIGURATION_REGISTER */ "", 71785 /* SCH_DVS_WEIGHT_CONFIG */ "", 71786 /* SCH_DVS_WEIGHT_ENABLE */ "", 71787 /* SCH_ECC_1B_ERR_ADDR */ "", 71788 /* SCH_ECC_1B_ERR_CNT */ "", 71789 /* SCH_ECC_1B_ERR_INTERRUPT_MASK_REGISTER */ "", 71790 /* SCH_ECC_1B_ERR_INTERRUPT_REGISTER */ "", 71791 /* SCH_ECC_2B_ERR_ADDR */ "", 71792 /* SCH_ECC_2B_ERR_CNT */ "", 71793 /* SCH_ECC_2B_ERR_INTERRUPT_MASK_REGISTER */ "", 71794 /* SCH_ECC_2B_ERR_INTERRUPT_REGISTER */ "", 71795 /* SCH_ECC_ERR_1B_INITIATE */ "", 71796 /* SCH_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 71797 /* SCH_ECC_ERR_2B_INITIATE */ "", 71798 /* SCH_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 71799 /* SCH_ECC_INTERRUPT_REGISTER */ "", 71800 /* SCH_ECC_INTERRUPT_REGISTER_MASK */ "", 71801 /* SCH_ECC_INTERRUPT_REGISTER_TEST */ "", 71802 /* SCH_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 71803 /* SCH_ERROR_INITIATION_DATA */ "", 71804 /* SCH_FC_ENABLERS */ "", 71805 /* SCH_FORCE_PORT_FC_REGISTER */ "", 71806 /* SCH_FSF_COMPOSITE_CONFIGURATION */ "", 71807 /* SCH_GLOBAL_MEM_OPTIONS */ "", 71808 /* SCH_GLOBAL_TIMER_ACTIVATION_REGISTER */ "", 71809 /* SCH_GLOBAL_TIMER_CONFIGURATION_REGISTER */ "", 71810 /* SCH_GTIMER_CONFIGURATION */ "", 71811 /* SCH_GTIMER_CYCLE */ "", 71812 /* SCH_GTIMER_TRIGGER */ "", 71813 /* SCH_HR_PRIORITY_MASK */ "", 71814 /* SCH_INCORRECT_STATUS_MESSAGE */ "", 71815 /* SCH_INCORRECT_STATUS_MESSAGE___REGISTER_1 */ "", 71816 /* SCH_INCORRECT_STATUS_MESSAGE___REGISTER_2 */ "", 71817 /* SCH_INDIRECT_COMMAND */ "", 71818 /* SCH_INDIRECT_COMMAND_ADDRESS */ "", 71819 /* SCH_INDIRECT_COMMAND_DATA_INCREMENT */ "", 71820 /* SCH_INDIRECT_COMMAND_RD_DATA */ "", 71821 /* SCH_INDIRECT_COMMAND_WIDE_MEM */ "", 71822 /* SCH_INDIRECT_COMMAND_WR_DATA */ "", 71823 /* SCH_INDIRECT_FORCE_BUBBLE */ "", 71824 /* SCH_INDIRECT_WR_MASK */ "", 71825 /* SCH_INGRESS_SHAPING_PORT_CONFIGURATION */ "", 71826 /* SCH_INTERFACE_FC_MASK */ "", 71827 /* SCH_INTERRUPT_MASK_REGISTER */ "", 71828 /* SCH_INTERRUPT_REGISTER */ "", 71829 /* SCH_INTERRUPT_REGISTER_TEST */ "", 71830 /* SCH_LAST_FLOW_RESTART_EVENT */ "", 71831 /* SCH_LINKS_MASK */ "", 71832 /* SCH_LOW_RATE_FLOW_CONFIG_RANGE */ "", 71833 /* SCH_LOW_RATE_FLOW_EN_MASK */ "", 71834 /* SCH_MAX_PORT_QUEUE_SIZECOUNTER */ "", 71835 /* SCH_MAX_PORT_QUEUE_SIZE_COUNTER */ "", 71836 /* SCH_NIF_1P_PRIORITY_MODE_REGISTER */ "", 71837 /* SCH_NIF_2P_PRIORITY_MODE_REGISTER */ "", 71838 /* SCH_NIF_4P_PRIORITY_MODE_REGISTER */ "", 71839 /* SCH_OOB_FC_CONFIGURATION_REGISTER */ "", 71840 /* SCH_OOB_FC_STATUS_REGISTER */ "", 71841 /* SCH_PARITY_ERR_ADDR */ "", 71842 /* SCH_PARITY_ERR_CNT */ "", 71843 /* SCH_PAR_ERR_INITIATE */ "", 71844 /* SCH_PAR_ERR_INTERRUPT_MASK_REGISTER */ "", 71845 /* SCH_PAR_ERR_INTERRUPT_REGISTER */ "", 71846 /* SCH_PAR_ERR_MEM_MASK */ "", 71847 /* SCH_PCMI_0 */ "", 71848 /* SCH_PCMI_1 */ "", 71849 /* SCH_PCMI_2 */ "", 71850 /* SCH_PCMI_3 */ "", 71851 /* SCH_PCMI_4 */ "", 71852 /* SCH_PCMI_0_S */ "", 71853 /* SCH_PCMI_0_T */ "", 71854 /* SCH_PCMI_1_S */ "", 71855 /* SCH_PCMI_1_T */ "", 71856 /* SCH_PCMI_2_S */ "", 71857 /* SCH_PCMI_2_T */ "", 71858 /* SCH_PCMI_3_S */ "", 71859 /* SCH_PCMI_3_T */ "", 71860 /* SCH_PCMI_4_S */ "", 71861 /* SCH_PCMI_4_T */ "", 71862 /* SCH_PIR_SHAPERS_CONFIGURATION */ "", 71863 /* SCH_PIR_SHAPERS_CONFIGURATION_1 */ "", 71864 /* SCH_PS_1P_PRIORITY_MODE_REGISTER */ "", 71865 /* SCH_PS_2P_PRIORITY_MODE_REGISTER */ "", 71866 /* SCH_PS_4P_PRIORITY_MODE_REGISTER */ "", 71867 /* SCH_PS_CALENDAR_SELECT */ "", 71868 /* SCH_PS_PRIORITY_PROPAGATION_ENABLE */ "", 71869 /* SCH_RCI_BFC_PARAMS */ "", 71870 /* SCH_RCI_CREDIT_JITTER */ "", 71871 /* SCH_RCI_DECREMENT_VALUES */ "", 71872 /* SCH_RCI_PARAMS */ "", 71873 /* SCH_REBOUNDED_CREDIT_CONFIGURATION */ "", 71874 /* SCH_REBOUNDED_CREDIT_CONFIGURATION_1 */ "", 71875 /* SCH_REG_0041 */ "", 71876 /* SCH_REG_090 */ "", 71877 /* SCH_REG_091 */ "", 71878 /* SCH_REG_092 */ "", 71879 /* SCH_REG_093 */ "", 71880 /* SCH_REG_0103 */ "", 71881 /* SCH_REG_103 */ "", 71882 /* SCH_REG_0104 */ "", 71883 /* SCH_REG_0109 */ "", 71884 /* SCH_REG_0112 */ "", 71885 /* SCH_REG_0113 */ "", 71886 /* SCH_REG_0129 */ "", 71887 /* SCH_REG_0151 */ "", 71888 /* SCH_REG_0155 */ "", 71889 /* SCH_REG_0157 */ "", 71890 /* SCH_REG_0158 */ "", 71891 /* SCH_REG_0159 */ "", 71892 /* SCH_REG_0160 */ "", 71893 /* SCH_REG_0161 */ "", 71894 /* SCH_REG_0162 */ "", 71895 /* SCH_REG_0163 */ "", 71896 /* SCH_REG_0164 */ "", 71897 /* SCH_REG_0165 */ "", 71898 /* SCH_REG_0168 */ "", 71899 /* SCH_REG_0169 */ "", 71900 /* SCH_REG_0182 */ "", 71901 /* SCH_REG_213 */ "", 71902 /* SCH_REG_215 */ "", 71903 /* SCH_REG_00A4 */ "", 71904 /* SCH_REG_00A6 */ "", 71905 /* SCH_REG_00AA */ "", 71906 /* SCH_REG_00B4 */ "", 71907 /* SCH_REG_00B5 */ "", 71908 /* SCH_REG_00B6 */ "", 71909 /* SCH_REG_00B7 */ "", 71910 /* SCH_REG_00BC */ "", 71911 /* SCH_REG_00BD */ "", 71912 /* SCH_REG_00BE */ "", 71913 /* SCH_REG_00BF */ "", 71914 /* SCH_REG_00C2 */ "", 71915 /* SCH_REG_011A */ "", 71916 /* SCH_REG_012D */ "", 71917 /* SCH_REG_013B */ "", 71918 /* SCH_REG_013C */ "", 71919 /* SCH_REG_013E */ "", 71920 /* SCH_REG_015F */ "", 71921 /* SCH_REG_0AE */ "", 71922 /* SCH_REG_0AF */ "", 71923 /* SCH_REG_0E7 */ "", 71924 /* SCH_REG_0EB */ "", 71925 /* SCH_REG_0ED */ "", 71926 /* SCH_REG_0EE */ "", 71927 /* SCH_REG_0F4 */ "", 71928 /* SCH_REG_0F5 */ "", 71929 /* SCH_REG_0F6 */ "", 71930 /* SCH_REG_0F7 */ "", 71931 /* SCH_REG_0F8 */ "", 71932 /* SCH_REG_0F9 */ "", 71933 /* SCH_REG_0FA */ "", 71934 /* SCH_REG_0FD */ "", 71935 /* SCH_REG_0FE */ "", 71936 /* SCH_REG_0FF */ "", 71937 /* SCH_REG_10A */ "", 71938 /* SCH_REG_10B */ "", 71939 /* SCH_REG_11C */ "", 71940 /* SCH_REG_11D */ "", 71941 /* SCH_REG_12D */ "", 71942 /* SCH_REG_1A8 */ "", 71943 /* SCH_REG_1A9 */ "", 71944 /* SCH_REG_1AC */ "", 71945 /* SCH_REG_1BC */ "", 71946 /* SCH_REG_2AF */ "", 71947 /* SCH_RESERVED_1 */ "", 71948 /* SCH_RESERVED_2 */ "", 71949 /* SCH_RESERVED_3 */ "", 71950 /* SCH_RESERVED_4 */ "", 71951 /* SCH_RESERVED_5 */ "", 71952 /* SCH_RESERVED_6 */ "", 71953 /* SCH_RESERVED_7 */ "", 71954 /* SCH_RESERVED_8 */ "", 71955 /* SCH_RESERVED_9 */ "", 71956 /* SCH_RESERVED_10 */ "", 71957 /* SCH_RESERVED_11 */ "", 71958 /* SCH_RESERVED_12 */ "", 71959 /* SCH_RESERVED_13 */ "", 71960 /* SCH_RESERVED_14 */ "", 71961 /* SCH_RESERVED_15 */ "", 71962 /* SCH_RESERVED_16 */ "", 71963 /* SCH_RESERVED_17 */ "", 71964 /* SCH_RESERVED_18 */ "", 71965 /* SCH_RESERVED_19 */ "", 71966 /* SCH_RESERVED_20 */ "", 71967 /* SCH_RESERVED_21 */ "", 71968 /* SCH_RESERVED_22 */ "", 71969 /* SCH_RESERVED_23 */ "", 71970 /* SCH_RESERVED_24 */ "", 71971 /* SCH_RESERVED_25 */ "", 71972 /* SCH_RESERVED_MIRROR_ADDR */ "", 71973 /* SCH_RESERVED_MTCD */ "", 71974 /* SCH_RESERVED_MTCP */ "", 71975 /* SCH_RESERVED_PCMI_0 */ "", 71976 /* SCH_RESERVED_PCMI_1 */ "", 71977 /* SCH_RESERVED_PCMI_2 */ "", 71978 /* SCH_RESERVED_PCMI_3 */ "", 71979 /* SCH_RESERVED_PCMI_4 */ "", 71980 /* SCH_RESERVED_PCMI_0_S */ "", 71981 /* SCH_RESERVED_PCMI_0_T */ "", 71982 /* SCH_RESERVED_PCMI_1_S */ "", 71983 /* SCH_RESERVED_PCMI_1_T */ "", 71984 /* SCH_RESERVED_PCMI_2_S */ "", 71985 /* SCH_RESERVED_PCMI_2_T */ "", 71986 /* SCH_RESERVED_PCMI_3_S */ "", 71987 /* SCH_RESERVED_PCMI_3_T */ "", 71988 /* SCH_RESERVED_PCMI_4_S */ "", 71989 /* SCH_RESERVED_PCMI_4_T */ "", 71990 /* SCH_RESERVED_SPARE_0 */ "", 71991 /* SCH_RESERVED_SPARE_1 */ "", 71992 /* SCH_RESERVED_SPARE_2 */ "", 71993 /* SCH_RESERVED_SPARE_3 */ "", 71994 /* SCH_RETURNED_CREDITS_CFG_REGISTER */ "", 71995 /* SCH_SBUS_BROADCAST_ID */ "", 71996 /* SCH_SBUS_LAST_IN_CHAIN */ "", 71997 /* SCH_SCHEDULER_CONFIGURATION_REGISTER */ "", 71998 /* SCH_SCHEDULER_COUNTER */ "", 71999 /* SCH_SCHEDULER_NOT_VALID */ "", 72000 /* SCH_SCH_FABRIC_MULTICAST_PORT_CONFIGURATION_REGISTER_0 */ "", 72001 /* SCH_SCH_FABRIC_MULTICAST_PORT_CONFIGURATION_REGISTER_1 */ "", 72002 /* SCH_SCL_SMP_MESSAGES */ "", 72003 /* SCH_SCL___SMP_MESSAGES */ "", 72004 /* SCH_SELECT_FLOW_TO_QUEUE_MAPPING */ "", 72005 /* SCH_SHAPER_CONFIGURATION_REGISTER_1 */ "", 72006 /* SCH_SHARED_BUCKET_2_ACT_BITMAP */ "", 72007 /* SCH_SHARED_BUCKET_2_ACT_BITMAP_SWITCHED */ "", 72008 /* SCH_SHARED_BUCKET_2_INC_BITMAP */ "", 72009 /* SCH_SHARED_BUCKET_2_INC_BITMAP_SWITCHED */ "", 72010 /* SCH_SHARED_BUCKET_4_ACT_BITMAP */ "", 72011 /* SCH_SHARED_BUCKET_4_ACT_BITMAP_SWITCHED */ "", 72012 /* SCH_SHARED_BUCKET_4_INC_BITMAP */ "", 72013 /* SCH_SHARED_BUCKET_4_INC_BITMAP_SWITCHED */ "", 72014 /* SCH_SHARED_BUCKET_8_ACT_BITMAP */ "", 72015 /* SCH_SHARED_BUCKET_8_ACT_BITMAP_SWITCHED */ "", 72016 /* SCH_SHARED_BUCKET_8_INC_BITMAP */ "", 72017 /* SCH_SHARED_BUCKET_8_INC_BITMAP_SWITCHED */ "", 72018 /* SCH_SMP_BACK_UP_MESSAGES */ "", 72019 /* SCH_SMP_MESSAGE_COUNTER */ "", 72020 /* SCH_SMP_MESSAGE_COUNTER_AND_STATUS_CONFIGURATION */ "", 72021 /* SCH_SWITCH_CIR_EIR_IN_DUAL_SHAPERS */ "", 72022 /* SCH_SYSTEM_RED_CONFIGURATION */ "", 72023 /* SCQM_QGRP */ "", 72024 /* SC_BYTE_METER_CONFIG */ "", 72025 /* SC_CAM_BIST_CONFIG */ "", 72026 /* SC_CAM_BIST_CONTROL */ "", 72027 /* SC_CAM_BIST_DBG */ "", 72028 /* SC_CAM_BIST_STATUS */ "", 72029 /* SC_X1_CONTROL_PIPELINE_RESET_COUNT */ "", 72030 /* SC_X1_CONTROL_PLL_LOCK_TIMER */ "", 72031 /* SC_X1_CONTROL_PMD_LOCK_TIMER */ "", 72032 /* SC_X1_CONTROL_STATUS */ "", 72033 /* SC_X1_CONTROL_TX_RESET_COUNT */ "", 72034 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_0 */ "", 72035 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_1 */ "", 72036 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_2 */ "", 72037 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_3 */ "", 72038 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_4 */ "", 72039 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_5 */ "", 72040 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_6 */ "", 72041 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_7 */ "", 72042 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_8 */ "", 72043 /* SC_X1_SPEED_OVERRIDE0_OVERRIDE_SPEED */ "", 72044 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_0 */ "", 72045 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_1 */ "", 72046 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_2 */ "", 72047 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_3 */ "", 72048 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_4 */ "", 72049 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_5 */ "", 72050 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_6 */ "", 72051 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_7 */ "", 72052 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_8 */ "", 72053 /* SC_X1_SPEED_OVERRIDE1_OVERRIDE_SPEED */ "", 72054 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_0 */ "", 72055 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_1 */ "", 72056 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_2 */ "", 72057 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_3 */ "", 72058 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_4 */ "", 72059 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_5 */ "", 72060 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_6 */ "", 72061 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_7 */ "", 72062 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_8 */ "", 72063 /* SC_X1_SPEED_OVERRIDE2_OVERRIDE_SPEED */ "", 72064 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_0 */ "", 72065 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_1 */ "", 72066 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_2 */ "", 72067 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_3 */ "", 72068 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_4 */ "", 72069 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_5 */ "", 72070 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_6 */ "", 72071 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_7 */ "", 72072 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_8 */ "", 72073 /* SC_X1_SPEED_OVERRIDE3_OVERRIDE_SPEED */ "", 72074 /* SC_X4_CONTROL_BYPASS */ "", 72075 /* SC_X4_CONTROL_CONTROL */ "", 72076 /* SC_X4_CONTROL_DEBUG */ "", 72077 /* SC_X4_CONTROL_ERROR */ "", 72078 /* SC_X4_CONTROL_IEEE_25G_CONTROL */ "", 72079 /* SC_X4_CONTROL_MSA_25G_50G_CONTROL */ "", 72080 /* SC_X4_CONTROL_SC_X4_OVERRIDE */ "", 72081 /* SC_X4_CONTROL_SPARE0 */ "", 72082 /* SC_X4_CONTROL_SPARE1 */ "", 72083 /* SC_X4_CONTROL_STATUS */ "", 72084 /* SC_X4_CONTROL_SW_SPARE1 */ "", 72085 /* SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE0_TYPE */ "", 72086 /* SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE1_TYPE */ "", 72087 /* SC_X4_FIELD_OVERRIDE_ENABLE_FIELD_OVERRIDE_ENABLE2_TYPE */ "", 72088 /* SC_X4_FINAL_CONFIG_STATUS_FEC_STATUS */ "", 72089 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_0 */ "", 72090 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_1 */ "", 72091 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_2 */ "", 72092 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_3 */ "", 72093 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_4 */ "", 72094 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_5 */ "", 72095 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_6 */ "", 72096 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_7 */ "", 72097 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_8 */ "", 72098 /* SC_X4_FINAL_CONFIG_STATUS_RESOLVED_SPEED */ "", 72099 /* SDIO0_EMMCSDXC_ADMAADDR0 */ "", 72100 /* SDIO0_EMMCSDXC_ADMAERR */ "", 72101 /* SDIO0_EMMCSDXC_ARG */ "", 72102 /* SDIO0_EMMCSDXC_BLOCK */ "", 72103 /* SDIO0_EMMCSDXC_BOOTTIMEOUT */ "", 72104 /* SDIO0_EMMCSDXC_BUFDAT */ "", 72105 /* SDIO0_EMMCSDXC_CAPABILITIES1 */ "", 72106 /* SDIO0_EMMCSDXC_CAPABILITIES2 */ "", 72107 /* SDIO0_EMMCSDXC_CMD */ "", 72108 /* SDIO0_EMMCSDXC_CMDENTSTAT */ "", 72109 /* SDIO0_EMMCSDXC_CTRL */ "", 72110 /* SDIO0_EMMCSDXC_CTRL1 */ "", 72111 /* SDIO0_EMMCSDXC_DBGSEL */ "", 72112 /* SDIO0_EMMCSDXC_ERRSTAT */ "", 72113 /* SDIO0_EMMCSDXC_HCVERSIRQ */ "", 72114 /* SDIO0_EMMCSDXC_INTR */ "", 72115 /* SDIO0_EMMCSDXC_INTREN1 */ "", 72116 /* SDIO0_EMMCSDXC_INTREN2 */ "", 72117 /* SDIO0_EMMCSDXC_MAX_A1 */ "", 72118 /* SDIO0_EMMCSDXC_MAX_A2 */ "", 72119 /* SDIO0_EMMCSDXC_PRESETVAL1 */ "", 72120 /* SDIO0_EMMCSDXC_PRESETVAL2 */ "", 72121 /* SDIO0_EMMCSDXC_PRESETVAL3 */ "", 72122 /* SDIO0_EMMCSDXC_PRESETVAL4 */ "", 72123 /* SDIO0_EMMCSDXC_PSTATE */ "", 72124 /* SDIO0_EMMCSDXC_RESP0 */ "", 72125 /* SDIO0_EMMCSDXC_RESP2 */ "", 72126 /* SDIO0_EMMCSDXC_RESP4 */ "", 72127 /* SDIO0_EMMCSDXC_RESP6 */ "", 72128 /* SDIO0_EMMCSDXC_SBUSCTRL */ "", 72129 /* SDIO0_EMMCSDXC_SPI_INT */ "", 72130 /* SDIO0_EMMCSDXC_SYSADDR */ "", 72131 /* SDIO1_EMMCSDXC_ADMAADDR0 */ "", 72132 /* SDIO1_EMMCSDXC_ADMAERR */ "", 72133 /* SDIO1_EMMCSDXC_ARG */ "", 72134 /* SDIO1_EMMCSDXC_BLOCK */ "", 72135 /* SDIO1_EMMCSDXC_BOOTTIMEOUT */ "", 72136 /* SDIO1_EMMCSDXC_BUFDAT */ "", 72137 /* SDIO1_EMMCSDXC_CAPABILITIES1 */ "", 72138 /* SDIO1_EMMCSDXC_CAPABILITIES2 */ "", 72139 /* SDIO1_EMMCSDXC_CMD */ "", 72140 /* SDIO1_EMMCSDXC_CMDENTSTAT */ "", 72141 /* SDIO1_EMMCSDXC_CTRL */ "", 72142 /* SDIO1_EMMCSDXC_CTRL1 */ "", 72143 /* SDIO1_EMMCSDXC_DBGSEL */ "", 72144 /* SDIO1_EMMCSDXC_ERRSTAT */ "", 72145 /* SDIO1_EMMCSDXC_HCVERSIRQ */ "", 72146 /* SDIO1_EMMCSDXC_INTR */ "", 72147 /* SDIO1_EMMCSDXC_INTREN1 */ "", 72148 /* SDIO1_EMMCSDXC_INTREN2 */ "", 72149 /* SDIO1_EMMCSDXC_MAX_A1 */ "", 72150 /* SDIO1_EMMCSDXC_MAX_A2 */ "", 72151 /* SDIO1_EMMCSDXC_PRESETVAL1 */ "", 72152 /* SDIO1_EMMCSDXC_PRESETVAL2 */ "", 72153 /* SDIO1_EMMCSDXC_PRESETVAL3 */ "", 72154 /* SDIO1_EMMCSDXC_PRESETVAL4 */ "", 72155 /* SDIO1_EMMCSDXC_PSTATE */ "", 72156 /* SDIO1_EMMCSDXC_RESP0 */ "", 72157 /* SDIO1_EMMCSDXC_RESP2 */ "", 72158 /* SDIO1_EMMCSDXC_RESP4 */ "", 72159 /* SDIO1_EMMCSDXC_RESP6 */ "", 72160 /* SDIO1_EMMCSDXC_SBUSCTRL */ "", 72161 /* SDIO1_EMMCSDXC_SPI_INT */ "", 72162 /* SDIO1_EMMCSDXC_SYSADDR */ "", 72163 /* SDIO_IDM0_IDM_INTERRUPT_STATUS */ "", 72164 /* SDIO_IDM0_IDM_RESET_CONTROL */ "", 72165 /* SDIO_IDM0_IDM_RESET_STATUS */ "", 72166 /* SDIO_IDM0_IO_CONTROL_DIRECT */ "", 72167 /* SDIO_IDM1_IDM_INTERRUPT_STATUS */ "", 72168 /* SDIO_IDM1_IDM_RESET_CONTROL */ "", 72169 /* SDIO_IDM1_IDM_RESET_STATUS */ "", 72170 /* SDIO_IDM1_IO_CONTROL_DIRECT */ "", 72171 /* SDROM_REMAP_SELECT */ "", 72172 /* SDROM_REMAP_SELECT_ENABLE */ "", 72173 /* SECOND_MGMT_PORT */ "", 72174 /* SECTAG_ETHERTYPE */ "", 72175 /* SERVICE_COS_MAP_ECC_CONTROL */ "", 72176 /* SERVICE_COS_MAP_PARITY_CONTROL */ "", 72177 /* SERVICE_COS_MAP_PARITY_STATUS_INTR */ "", 72178 /* SERVICE_COS_MAP_PARITY_STATUS_NACK */ "", 72179 /* SER_CONFIG_REG */ "", 72180 /* SER_ERROR_0 */ "", 72181 /* SER_ERROR_1 */ "", 72182 /* SER_MISSED_EVENT */ "", 72183 /* SER_RANGE_0_ADDR_BITS */ "", 72184 /* SER_RANGE_0_ADDR_MASK */ "", 72185 /* SER_RANGE_0_CONFIG */ "", 72186 /* SER_RANGE_0_DISABLE */ "", 72187 /* SER_RANGE_0_END */ "", 72188 /* SER_RANGE_0_PROT_WORD_0 */ "", 72189 /* SER_RANGE_0_PROT_WORD_1 */ "", 72190 /* SER_RANGE_0_PROT_WORD_2 */ "", 72191 /* SER_RANGE_0_PROT_WORD_3 */ "", 72192 /* SER_RANGE_0_RESULT */ "", 72193 /* SER_RANGE_0_START */ "", 72194 /* SER_RANGE_10_ADDR_BITS */ "", 72195 /* SER_RANGE_10_ADDR_MASK */ "", 72196 /* SER_RANGE_10_CONFIG */ "", 72197 /* SER_RANGE_10_DISABLE */ "", 72198 /* SER_RANGE_10_END */ "", 72199 /* SER_RANGE_10_PROT_WORD_0 */ "", 72200 /* SER_RANGE_10_PROT_WORD_1 */ "", 72201 /* SER_RANGE_10_PROT_WORD_2 */ "", 72202 /* SER_RANGE_10_PROT_WORD_3 */ "", 72203 /* SER_RANGE_10_RESULT */ "", 72204 /* SER_RANGE_10_START */ "", 72205 /* SER_RANGE_11_ADDR_BITS */ "", 72206 /* SER_RANGE_11_ADDR_MASK */ "", 72207 /* SER_RANGE_11_CONFIG */ "", 72208 /* SER_RANGE_11_DISABLE */ "", 72209 /* SER_RANGE_11_END */ "", 72210 /* SER_RANGE_11_PROT_WORD_0 */ "", 72211 /* SER_RANGE_11_PROT_WORD_1 */ "", 72212 /* SER_RANGE_11_PROT_WORD_2 */ "", 72213 /* SER_RANGE_11_PROT_WORD_3 */ "", 72214 /* SER_RANGE_11_RESULT */ "", 72215 /* SER_RANGE_11_START */ "", 72216 /* SER_RANGE_12_ADDR_BITS */ "", 72217 /* SER_RANGE_12_ADDR_MASK */ "", 72218 /* SER_RANGE_12_CONFIG */ "", 72219 /* SER_RANGE_12_DISABLE */ "", 72220 /* SER_RANGE_12_END */ "", 72221 /* SER_RANGE_12_PROT_WORD_0 */ "", 72222 /* SER_RANGE_12_PROT_WORD_1 */ "", 72223 /* SER_RANGE_12_PROT_WORD_2 */ "", 72224 /* SER_RANGE_12_PROT_WORD_3 */ "", 72225 /* SER_RANGE_12_RESULT */ "", 72226 /* SER_RANGE_12_START */ "", 72227 /* SER_RANGE_13_ADDR_BITS */ "", 72228 /* SER_RANGE_13_ADDR_MASK */ "", 72229 /* SER_RANGE_13_CONFIG */ "", 72230 /* SER_RANGE_13_DISABLE */ "", 72231 /* SER_RANGE_13_END */ "", 72232 /* SER_RANGE_13_PROT_WORD_0 */ "", 72233 /* SER_RANGE_13_PROT_WORD_1 */ "", 72234 /* SER_RANGE_13_PROT_WORD_2 */ "", 72235 /* SER_RANGE_13_PROT_WORD_3 */ "", 72236 /* SER_RANGE_13_RESULT */ "", 72237 /* SER_RANGE_13_START */ "", 72238 /* SER_RANGE_14_ADDR_BITS */ "", 72239 /* SER_RANGE_14_ADDR_MASK */ "", 72240 /* SER_RANGE_14_CONFIG */ "", 72241 /* SER_RANGE_14_DISABLE */ "", 72242 /* SER_RANGE_14_END */ "", 72243 /* SER_RANGE_14_PROT_WORD_0 */ "", 72244 /* SER_RANGE_14_PROT_WORD_1 */ "", 72245 /* SER_RANGE_14_PROT_WORD_2 */ "", 72246 /* SER_RANGE_14_PROT_WORD_3 */ "", 72247 /* SER_RANGE_14_RESULT */ "", 72248 /* SER_RANGE_14_START */ "", 72249 /* SER_RANGE_15_ADDR_BITS */ "", 72250 /* SER_RANGE_15_ADDR_MASK */ "", 72251 /* SER_RANGE_15_CONFIG */ "", 72252 /* SER_RANGE_15_DISABLE */ "", 72253 /* SER_RANGE_15_END */ "", 72254 /* SER_RANGE_15_PROT_WORD_0 */ "", 72255 /* SER_RANGE_15_PROT_WORD_1 */ "", 72256 /* SER_RANGE_15_PROT_WORD_2 */ "", 72257 /* SER_RANGE_15_PROT_WORD_3 */ "", 72258 /* SER_RANGE_15_RESULT */ "", 72259 /* SER_RANGE_15_START */ "", 72260 /* SER_RANGE_16_ADDR_BITS */ "", 72261 /* SER_RANGE_16_ADDR_MASK */ "", 72262 /* SER_RANGE_16_CONFIG */ "", 72263 /* SER_RANGE_16_DISABLE */ "", 72264 /* SER_RANGE_16_END */ "", 72265 /* SER_RANGE_16_PROT_WORD_0 */ "", 72266 /* SER_RANGE_16_PROT_WORD_1 */ "", 72267 /* SER_RANGE_16_PROT_WORD_2 */ "", 72268 /* SER_RANGE_16_PROT_WORD_3 */ "", 72269 /* SER_RANGE_16_RESULT */ "", 72270 /* SER_RANGE_16_START */ "", 72271 /* SER_RANGE_17_ADDR_BITS */ "", 72272 /* SER_RANGE_17_ADDR_MASK */ "", 72273 /* SER_RANGE_17_CONFIG */ "", 72274 /* SER_RANGE_17_DISABLE */ "", 72275 /* SER_RANGE_17_END */ "", 72276 /* SER_RANGE_17_PROT_WORD_0 */ "", 72277 /* SER_RANGE_17_PROT_WORD_1 */ "", 72278 /* SER_RANGE_17_PROT_WORD_2 */ "", 72279 /* SER_RANGE_17_PROT_WORD_3 */ "", 72280 /* SER_RANGE_17_RESULT */ "", 72281 /* SER_RANGE_17_START */ "", 72282 /* SER_RANGE_18_ADDR_BITS */ "", 72283 /* SER_RANGE_18_ADDR_MASK */ "", 72284 /* SER_RANGE_18_CONFIG */ "", 72285 /* SER_RANGE_18_DISABLE */ "", 72286 /* SER_RANGE_18_END */ "", 72287 /* SER_RANGE_18_PROT_WORD_0 */ "", 72288 /* SER_RANGE_18_PROT_WORD_1 */ "", 72289 /* SER_RANGE_18_PROT_WORD_2 */ "", 72290 /* SER_RANGE_18_PROT_WORD_3 */ "", 72291 /* SER_RANGE_18_RESULT */ "", 72292 /* SER_RANGE_18_START */ "", 72293 /* SER_RANGE_19_ADDR_BITS */ "", 72294 /* SER_RANGE_19_ADDR_MASK */ "", 72295 /* SER_RANGE_19_CONFIG */ "", 72296 /* SER_RANGE_19_DISABLE */ "", 72297 /* SER_RANGE_19_END */ "", 72298 /* SER_RANGE_19_PROT_WORD_0 */ "", 72299 /* SER_RANGE_19_PROT_WORD_1 */ "", 72300 /* SER_RANGE_19_PROT_WORD_2 */ "", 72301 /* SER_RANGE_19_PROT_WORD_3 */ "", 72302 /* SER_RANGE_19_RESULT */ "", 72303 /* SER_RANGE_19_START */ "", 72304 /* SER_RANGE_1_ADDR_BITS */ "", 72305 /* SER_RANGE_1_ADDR_MASK */ "", 72306 /* SER_RANGE_1_CONFIG */ "", 72307 /* SER_RANGE_1_DISABLE */ "", 72308 /* SER_RANGE_1_END */ "", 72309 /* SER_RANGE_1_PROT_WORD_0 */ "", 72310 /* SER_RANGE_1_PROT_WORD_1 */ "", 72311 /* SER_RANGE_1_PROT_WORD_2 */ "", 72312 /* SER_RANGE_1_PROT_WORD_3 */ "", 72313 /* SER_RANGE_1_RESULT */ "", 72314 /* SER_RANGE_1_START */ "", 72315 /* SER_RANGE_20_ADDR_BITS */ "", 72316 /* SER_RANGE_20_ADDR_MASK */ "", 72317 /* SER_RANGE_20_CONFIG */ "", 72318 /* SER_RANGE_20_DISABLE */ "", 72319 /* SER_RANGE_20_END */ "", 72320 /* SER_RANGE_20_PROT_WORD_0 */ "", 72321 /* SER_RANGE_20_PROT_WORD_1 */ "", 72322 /* SER_RANGE_20_PROT_WORD_2 */ "", 72323 /* SER_RANGE_20_PROT_WORD_3 */ "", 72324 /* SER_RANGE_20_RESULT */ "", 72325 /* SER_RANGE_20_START */ "", 72326 /* SER_RANGE_21_ADDR_BITS */ "", 72327 /* SER_RANGE_21_ADDR_MASK */ "", 72328 /* SER_RANGE_21_CONFIG */ "", 72329 /* SER_RANGE_21_DISABLE */ "", 72330 /* SER_RANGE_21_END */ "", 72331 /* SER_RANGE_21_PROT_WORD_0 */ "", 72332 /* SER_RANGE_21_PROT_WORD_1 */ "", 72333 /* SER_RANGE_21_PROT_WORD_2 */ "", 72334 /* SER_RANGE_21_PROT_WORD_3 */ "", 72335 /* SER_RANGE_21_RESULT */ "", 72336 /* SER_RANGE_21_START */ "", 72337 /* SER_RANGE_22_ADDR_BITS */ "", 72338 /* SER_RANGE_22_ADDR_MASK */ "", 72339 /* SER_RANGE_22_CONFIG */ "", 72340 /* SER_RANGE_22_DISABLE */ "", 72341 /* SER_RANGE_22_END */ "", 72342 /* SER_RANGE_22_PROT_WORD_0 */ "", 72343 /* SER_RANGE_22_PROT_WORD_1 */ "", 72344 /* SER_RANGE_22_PROT_WORD_2 */ "", 72345 /* SER_RANGE_22_PROT_WORD_3 */ "", 72346 /* SER_RANGE_22_RESULT */ "", 72347 /* SER_RANGE_22_START */ "", 72348 /* SER_RANGE_23_ADDR_BITS */ "", 72349 /* SER_RANGE_23_ADDR_MASK */ "", 72350 /* SER_RANGE_23_CONFIG */ "", 72351 /* SER_RANGE_23_DISABLE */ "", 72352 /* SER_RANGE_23_END */ "", 72353 /* SER_RANGE_23_PROT_WORD_0 */ "", 72354 /* SER_RANGE_23_PROT_WORD_1 */ "", 72355 /* SER_RANGE_23_PROT_WORD_2 */ "", 72356 /* SER_RANGE_23_PROT_WORD_3 */ "", 72357 /* SER_RANGE_23_RESULT */ "", 72358 /* SER_RANGE_23_START */ "", 72359 /* SER_RANGE_24_ADDR_BITS */ "", 72360 /* SER_RANGE_24_ADDR_MASK */ "", 72361 /* SER_RANGE_24_CONFIG */ "", 72362 /* SER_RANGE_24_DISABLE */ "", 72363 /* SER_RANGE_24_END */ "", 72364 /* SER_RANGE_24_PROT_WORD_0 */ "", 72365 /* SER_RANGE_24_PROT_WORD_1 */ "", 72366 /* SER_RANGE_24_PROT_WORD_2 */ "", 72367 /* SER_RANGE_24_PROT_WORD_3 */ "", 72368 /* SER_RANGE_24_RESULT */ "", 72369 /* SER_RANGE_24_START */ "", 72370 /* SER_RANGE_25_ADDR_BITS */ "", 72371 /* SER_RANGE_25_ADDR_MASK */ "", 72372 /* SER_RANGE_25_CONFIG */ "", 72373 /* SER_RANGE_25_DISABLE */ "", 72374 /* SER_RANGE_25_END */ "", 72375 /* SER_RANGE_25_PROT_WORD_0 */ "", 72376 /* SER_RANGE_25_PROT_WORD_1 */ "", 72377 /* SER_RANGE_25_PROT_WORD_2 */ "", 72378 /* SER_RANGE_25_PROT_WORD_3 */ "", 72379 /* SER_RANGE_25_RESULT */ "", 72380 /* SER_RANGE_25_START */ "", 72381 /* SER_RANGE_26_ADDR_BITS */ "", 72382 /* SER_RANGE_26_ADDR_MASK */ "", 72383 /* SER_RANGE_26_CONFIG */ "", 72384 /* SER_RANGE_26_DISABLE */ "", 72385 /* SER_RANGE_26_END */ "", 72386 /* SER_RANGE_26_PROT_WORD_0 */ "", 72387 /* SER_RANGE_26_PROT_WORD_1 */ "", 72388 /* SER_RANGE_26_PROT_WORD_2 */ "", 72389 /* SER_RANGE_26_PROT_WORD_3 */ "", 72390 /* SER_RANGE_26_RESULT */ "", 72391 /* SER_RANGE_26_START */ "", 72392 /* SER_RANGE_27_ADDR_BITS */ "", 72393 /* SER_RANGE_27_ADDR_MASK */ "", 72394 /* SER_RANGE_27_CONFIG */ "", 72395 /* SER_RANGE_27_DISABLE */ "", 72396 /* SER_RANGE_27_END */ "", 72397 /* SER_RANGE_27_PROT_WORD_0 */ "", 72398 /* SER_RANGE_27_PROT_WORD_1 */ "", 72399 /* SER_RANGE_27_PROT_WORD_2 */ "", 72400 /* SER_RANGE_27_PROT_WORD_3 */ "", 72401 /* SER_RANGE_27_RESULT */ "", 72402 /* SER_RANGE_27_START */ "", 72403 /* SER_RANGE_28_ADDR_BITS */ "", 72404 /* SER_RANGE_28_ADDR_MASK */ "", 72405 /* SER_RANGE_28_CONFIG */ "", 72406 /* SER_RANGE_28_DISABLE */ "", 72407 /* SER_RANGE_28_END */ "", 72408 /* SER_RANGE_28_PROT_WORD_0 */ "", 72409 /* SER_RANGE_28_PROT_WORD_1 */ "", 72410 /* SER_RANGE_28_PROT_WORD_2 */ "", 72411 /* SER_RANGE_28_PROT_WORD_3 */ "", 72412 /* SER_RANGE_28_RESULT */ "", 72413 /* SER_RANGE_28_START */ "", 72414 /* SER_RANGE_29_ADDR_BITS */ "", 72415 /* SER_RANGE_29_ADDR_MASK */ "", 72416 /* SER_RANGE_29_CONFIG */ "", 72417 /* SER_RANGE_29_DISABLE */ "", 72418 /* SER_RANGE_29_END */ "", 72419 /* SER_RANGE_29_PROT_WORD_0 */ "", 72420 /* SER_RANGE_29_PROT_WORD_1 */ "", 72421 /* SER_RANGE_29_PROT_WORD_2 */ "", 72422 /* SER_RANGE_29_PROT_WORD_3 */ "", 72423 /* SER_RANGE_29_RESULT */ "", 72424 /* SER_RANGE_29_START */ "", 72425 /* SER_RANGE_2_ADDR_BITS */ "", 72426 /* SER_RANGE_2_ADDR_MASK */ "", 72427 /* SER_RANGE_2_CONFIG */ "", 72428 /* SER_RANGE_2_DISABLE */ "", 72429 /* SER_RANGE_2_END */ "", 72430 /* SER_RANGE_2_PROT_WORD_0 */ "", 72431 /* SER_RANGE_2_PROT_WORD_1 */ "", 72432 /* SER_RANGE_2_PROT_WORD_2 */ "", 72433 /* SER_RANGE_2_PROT_WORD_3 */ "", 72434 /* SER_RANGE_2_RESULT */ "", 72435 /* SER_RANGE_2_START */ "", 72436 /* SER_RANGE_30_ADDR_BITS */ "", 72437 /* SER_RANGE_30_ADDR_MASK */ "", 72438 /* SER_RANGE_30_CONFIG */ "", 72439 /* SER_RANGE_30_DISABLE */ "", 72440 /* SER_RANGE_30_END */ "", 72441 /* SER_RANGE_30_PROT_WORD_0 */ "", 72442 /* SER_RANGE_30_PROT_WORD_1 */ "", 72443 /* SER_RANGE_30_PROT_WORD_2 */ "", 72444 /* SER_RANGE_30_PROT_WORD_3 */ "", 72445 /* SER_RANGE_30_RESULT */ "", 72446 /* SER_RANGE_30_START */ "", 72447 /* SER_RANGE_31_ADDR_BITS */ "", 72448 /* SER_RANGE_31_ADDR_MASK */ "", 72449 /* SER_RANGE_31_CONFIG */ "", 72450 /* SER_RANGE_31_DISABLE */ "", 72451 /* SER_RANGE_31_END */ "", 72452 /* SER_RANGE_31_PROT_WORD_0 */ "", 72453 /* SER_RANGE_31_PROT_WORD_1 */ "", 72454 /* SER_RANGE_31_PROT_WORD_2 */ "", 72455 /* SER_RANGE_31_PROT_WORD_3 */ "", 72456 /* SER_RANGE_31_RESULT */ "", 72457 /* SER_RANGE_31_START */ "", 72458 /* SER_RANGE_3_ADDR_BITS */ "", 72459 /* SER_RANGE_3_ADDR_MASK */ "", 72460 /* SER_RANGE_3_CONFIG */ "", 72461 /* SER_RANGE_3_DISABLE */ "", 72462 /* SER_RANGE_3_END */ "", 72463 /* SER_RANGE_3_PROT_WORD_0 */ "", 72464 /* SER_RANGE_3_PROT_WORD_1 */ "", 72465 /* SER_RANGE_3_PROT_WORD_2 */ "", 72466 /* SER_RANGE_3_PROT_WORD_3 */ "", 72467 /* SER_RANGE_3_RESULT */ "", 72468 /* SER_RANGE_3_START */ "", 72469 /* SER_RANGE_4_ADDR_BITS */ "", 72470 /* SER_RANGE_4_ADDR_MASK */ "", 72471 /* SER_RANGE_4_CONFIG */ "", 72472 /* SER_RANGE_4_DISABLE */ "", 72473 /* SER_RANGE_4_END */ "", 72474 /* SER_RANGE_4_PROT_WORD_0 */ "", 72475 /* SER_RANGE_4_PROT_WORD_1 */ "", 72476 /* SER_RANGE_4_PROT_WORD_2 */ "", 72477 /* SER_RANGE_4_PROT_WORD_3 */ "", 72478 /* SER_RANGE_4_RESULT */ "", 72479 /* SER_RANGE_4_START */ "", 72480 /* SER_RANGE_5_ADDR_BITS */ "", 72481 /* SER_RANGE_5_ADDR_MASK */ "", 72482 /* SER_RANGE_5_CONFIG */ "", 72483 /* SER_RANGE_5_DISABLE */ "", 72484 /* SER_RANGE_5_END */ "", 72485 /* SER_RANGE_5_PROT_WORD_0 */ "", 72486 /* SER_RANGE_5_PROT_WORD_1 */ "", 72487 /* SER_RANGE_5_PROT_WORD_2 */ "", 72488 /* SER_RANGE_5_PROT_WORD_3 */ "", 72489 /* SER_RANGE_5_RESULT */ "", 72490 /* SER_RANGE_5_START */ "", 72491 /* SER_RANGE_6_ADDR_BITS */ "", 72492 /* SER_RANGE_6_ADDR_MASK */ "", 72493 /* SER_RANGE_6_CONFIG */ "", 72494 /* SER_RANGE_6_DISABLE */ "", 72495 /* SER_RANGE_6_END */ "", 72496 /* SER_RANGE_6_PROT_WORD_0 */ "", 72497 /* SER_RANGE_6_PROT_WORD_1 */ "", 72498 /* SER_RANGE_6_PROT_WORD_2 */ "", 72499 /* SER_RANGE_6_PROT_WORD_3 */ "", 72500 /* SER_RANGE_6_RESULT */ "", 72501 /* SER_RANGE_6_START */ "", 72502 /* SER_RANGE_7_ADDR_BITS */ "", 72503 /* SER_RANGE_7_ADDR_MASK */ "", 72504 /* SER_RANGE_7_CONFIG */ "", 72505 /* SER_RANGE_7_DISABLE */ "", 72506 /* SER_RANGE_7_END */ "", 72507 /* SER_RANGE_7_PROT_WORD_0 */ "", 72508 /* SER_RANGE_7_PROT_WORD_1 */ "", 72509 /* SER_RANGE_7_PROT_WORD_2 */ "", 72510 /* SER_RANGE_7_PROT_WORD_3 */ "", 72511 /* SER_RANGE_7_RESULT */ "", 72512 /* SER_RANGE_7_START */ "", 72513 /* SER_RANGE_8_ADDR_BITS */ "", 72514 /* SER_RANGE_8_ADDR_MASK */ "", 72515 /* SER_RANGE_8_CONFIG */ "", 72516 /* SER_RANGE_8_DISABLE */ "", 72517 /* SER_RANGE_8_END */ "", 72518 /* SER_RANGE_8_PROT_WORD_0 */ "", 72519 /* SER_RANGE_8_PROT_WORD_1 */ "", 72520 /* SER_RANGE_8_PROT_WORD_2 */ "", 72521 /* SER_RANGE_8_PROT_WORD_3 */ "", 72522 /* SER_RANGE_8_RESULT */ "", 72523 /* SER_RANGE_8_START */ "", 72524 /* SER_RANGE_9_ADDR_BITS */ "", 72525 /* SER_RANGE_9_ADDR_MASK */ "", 72526 /* SER_RANGE_9_CONFIG */ "", 72527 /* SER_RANGE_9_DISABLE */ "", 72528 /* SER_RANGE_9_END */ "", 72529 /* SER_RANGE_9_PROT_WORD_0 */ "", 72530 /* SER_RANGE_9_PROT_WORD_1 */ "", 72531 /* SER_RANGE_9_PROT_WORD_2 */ "", 72532 /* SER_RANGE_9_PROT_WORD_3 */ "", 72533 /* SER_RANGE_9_RESULT */ "", 72534 /* SER_RANGE_9_START */ "", 72535 /* SER_RANGE_ENABLE */ "", 72536 /* SER_RESULT_MEM_LVM */ "", 72537 /* SER_RESULT_MEM_PDA */ "", 72538 /* SER_RESULT_MEM_TM */ "", 72539 /* SER_RING_ERR_CTRL */ "", 72540 /* SET_BASE_TIME_ERROR_0 */ "", 72541 /* SET_BASE_TIME_ERROR_1 */ "", 72542 /* SET_BASE_TIME_ERROR_2 */ "", 72543 /* SET_BASE_TIME_ERROR_CLR_0 */ "", 72544 /* SET_BASE_TIME_ERROR_CLR_1 */ "", 72545 /* SET_BASE_TIME_ERROR_CLR_2 */ "", 72546 /* SET_NEXT_CYCLE_TIME_ERROR_0 */ "", 72547 /* SET_NEXT_CYCLE_TIME_ERROR_1 */ "", 72548 /* SET_NEXT_CYCLE_TIME_ERROR_2 */ "", 72549 /* SET_NEXT_CYCLE_TIME_ERROR_CLR_0 */ "", 72550 /* SET_NEXT_CYCLE_TIME_ERROR_CLR_1 */ "", 72551 /* SET_NEXT_CYCLE_TIME_ERROR_CLR_2 */ "", 72552 /* SEVPMC1C1 */ "", 72553 /* SEVPMC1C2 */ "", 72554 /* SEVPMC2C1 */ "", 72555 /* SEVPMC2C2 */ "", 72556 /* SEVPMC3C1 */ "", 72557 /* SEVPMC3C2 */ "", 72558 /* SEVPMC4C1 */ "", 72559 /* SEVPMC4C2 */ "", 72560 /* SEVPMDH1 */ "", 72561 /* SEVPMDH2 */ "", 72562 /* SEVPMG1C1 */ "", 72563 /* SEVPMG1C2 */ "", 72564 /* SEVPMG2C1 */ "", 72565 /* SEVPMG2C2 */ "", 72566 /* SEVPMG3C1 */ "", 72567 /* SEVPMG3C2 */ "", 72568 /* SEVPMG4C1 */ "", 72569 /* SEVPMG4C2 */ "", 72570 /* SEVPMG5C1 */ "", 72571 /* SEVPMG5C2 */ "", 72572 /* SEVPMG6C1 */ "", 72573 /* SEVPMG6C2 */ "", 72574 /* SEVPMG7C1 */ "", 72575 /* SEVPMG7C2 */ "", 72576 /* SEVPMG8C1 */ "", 72577 /* SEVPMG8C2 */ "", 72578 /* SEVPMSP1 */ "", 72579 /* SEVPMSP2 */ "", 72580 /* SFD_OFFSET */ "", 72581 /* SFLOW_EGR_RAND_SEED */ "", 72582 /* SFLOW_EGR_RAND_SEED_PIPE0 */ "", 72583 /* SFLOW_EGR_RAND_SEED_PIPE1 */ "", 72584 /* SFLOW_EGR_RAND_SEED_PIPE2 */ "", 72585 /* SFLOW_EGR_RAND_SEED_PIPE3 */ "", 72586 /* SFLOW_EGR_RAND_SEED_PIPE4 */ "", 72587 /* SFLOW_EGR_RAND_SEED_PIPE5 */ "", 72588 /* SFLOW_EGR_RAND_SEED_PIPE6 */ "", 72589 /* SFLOW_EGR_RAND_SEED_PIPE7 */ "", 72590 /* SFLOW_EGR_THRESHOLD */ "", 72591 /* SFLOW_ING_FLEX_RAND_SEED */ "", 72592 /* SFLOW_ING_FLEX_RAND_SEED_PIPE0 */ "", 72593 /* SFLOW_ING_FLEX_RAND_SEED_PIPE1 */ "", 72594 /* SFLOW_ING_FLEX_RAND_SEED_PIPE2 */ "", 72595 /* SFLOW_ING_FLEX_RAND_SEED_PIPE3 */ "", 72596 /* SFLOW_ING_FLEX_RAND_SEED_PIPE4 */ "", 72597 /* SFLOW_ING_FLEX_RAND_SEED_PIPE5 */ "", 72598 /* SFLOW_ING_FLEX_RAND_SEED_PIPE6 */ "", 72599 /* SFLOW_ING_FLEX_RAND_SEED_PIPE7 */ "", 72600 /* SFLOW_ING_MIRROR_CONFIG */ "", 72601 /* SFLOW_ING_RAND_SEED */ "", 72602 /* SFLOW_ING_RAND_SEED_PIPE0 */ "", 72603 /* SFLOW_ING_RAND_SEED_PIPE1 */ "", 72604 /* SFLOW_ING_RAND_SEED_PIPE2 */ "", 72605 /* SFLOW_ING_RAND_SEED_PIPE3 */ "", 72606 /* SFLOW_ING_RAND_SEED_PIPE4 */ "", 72607 /* SFLOW_ING_RAND_SEED_PIPE5 */ "", 72608 /* SFLOW_ING_RAND_SEED_PIPE6 */ "", 72609 /* SFLOW_ING_RAND_SEED_PIPE7 */ "", 72610 /* SFLOW_ING_THRESHOLD */ "", 72611 /* SFLOW_ING_THRESHOLD_PARITY_CONTROL */ "", 72612 /* SFLOW_ING_THRESHOLD_PARITY_STATUS_INTR */ "", 72613 /* SFLOW_ING_THRESHOLD_PARITY_STATUS_NACK */ "", 72614 /* SHAPING_CONTROL */ "SHAPING_CONTROL", 72615 /* SHAPING_MEM_WR_MODE */ "", 72616 /* SHAPING_MODE */ "SHAPING_MODE", 72617 /* SHAPING_MODE_24Q */ "", 72618 /* SHAPING_Q_GRAN */ "", 72619 /* SHAPING_Q_GRAN_QGROUP */ "", 72620 /* SHAPING_Q_GRAN_QLAYER_MAX0 */ "", 72621 /* SHAPING_Q_GRAN_QLAYER_MAX1 */ "", 72622 /* SHAPING_Q_GRAN_QLAYER_MIN0 */ "", 72623 /* SHAPING_Q_GRAN_QLAYER_MIN1 */ "", 72624 /* SHAPING_REF_FAIL */ "", 72625 /* SHARED_POOL_CTRL */ "", 72626 /* SHARED_POOL_CTRL_EXT1 */ "", 72627 /* SHARED_POOL_CTRL_EXT2 */ "", 72628 /* SHARED_TABLE_HASH_CONTROL */ "", 72629 /* SIF_AUTO_DOC_NAME_0 */ "", 72630 /* SIF_AUTO_DOC_NAME_1 */ "", 72631 /* SIF_AUTO_DOC_NAME_2 */ "", 72632 /* SIF_AUTO_DOC_NAME_3 */ "", 72633 /* SIF_AUTO_DOC_NAME_4 */ "", 72634 /* SIF_AUTO_DOC_NAME_5 */ "", 72635 /* SIF_AUTO_DOC_NAME_7 */ "", 72636 /* SIF_AUTO_DOC_NAME_8 */ "", 72637 /* SIF_BILLING_INPUT_FC_CTR */ "", 72638 /* SIF_BILLING_OUTPUT_FC_CTR */ "", 72639 /* SIF_ECC_1B_ERR_CNT */ "", 72640 /* SIF_ECC_2B_ERR_CNT */ "", 72641 /* SIF_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 72642 /* SIF_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 72643 /* SIF_ECC_INTERRUPT_REGISTER */ "", 72644 /* SIF_ECC_INTERRUPT_REGISTER_MASK */ "", 72645 /* SIF_ECC_INTERRUPT_REGISTER_TEST */ "", 72646 /* SIF_ENABLERS */ "", 72647 /* SIF_ERROR_INITIATION_DATA */ "", 72648 /* SIF_GTIMER_CONFIGURATION */ "", 72649 /* SIF_GTIMER_CYCLE */ "", 72650 /* SIF_INIT */ "", 72651 /* SIF_INTERRUPT_MASK_REGISTER */ "", 72652 /* SIF_INTERRUPT_REGISTER */ "", 72653 /* SIF_INTERRUPT_REGISTER_TEST */ "", 72654 /* SIF_QSIZE_INPUT_FC_CTR */ "", 72655 /* SIF_QSIZE_OUTPUT_FC_CTR */ "", 72656 /* SIF_REG_00A4 */ "", 72657 /* SIF_REG_00A6 */ "", 72658 /* SIF_REG_00C2 */ "", 72659 /* SIF_RESERVED_MIRROR_ADDR */ "", 72660 /* SIF_RESERVED_MTCD */ "", 72661 /* SIF_RESERVED_MTCP */ "", 72662 /* SIF_RESERVED_SPARE_0 */ "", 72663 /* SIF_RESERVED_SPARE_1 */ "", 72664 /* SIF_RESERVED_SPARE_2 */ "", 72665 /* SIF_RESERVED_SPARE_3 */ "", 72666 /* SIF_SBUS_BROADCAST_ID */ "", 72667 /* SIF_SBUS_LAST_IN_CHAIN */ "", 72668 /* SIF_ST_BILL_INPUT_PORT_SETTINGS */ "", 72669 /* SIF_ST_BILL_OPCODE_ERR_INTERRUPT_REGISTER */ "", 72670 /* SIF_ST_BILL_OPCODE_ERR_INTERRUPT_REGISTER_MASK */ "", 72671 /* SIF_ST_BILL_OPCODE_ERR_INTERRUPT_REGISTER_TEST */ "", 72672 /* SIF_ST_BILL_RPRT_CTR */ "", 72673 /* SIF_ST_BILL_RPRT_DROP_CTR */ "", 72674 /* SIF_ST_BILL_RPRT_DROP_ECC_CTR */ "", 72675 /* SIF_ST_PORT_FC_SETTINGS */ "", 72676 /* SIF_ST_PORT_SETTINGS */ "", 72677 /* SIF_ST_QSIZE_RPRT_CTR */ "", 72678 /* SIF_ST_QSIZE_RPRT_DROP_CTR */ "", 72679 /* SIF_ST_QSIZE_RPRT_DROP_ECC_CTR */ "", 72680 /* SIF_ST_QSIZE_SETTINGS */ "", 72681 /* SIF_ST_Q_SIZE_INPUT_PORT_FC_SETTINGS */ "", 72682 /* SIF_ST_RPRT_BILLING_RX_FIFO_ERR_INTERRUPT_REGISTER */ "", 72683 /* SIF_ST_RPRT_BILLING_RX_FIFO_ERR_INTERRUPT_REGISTER_MASK */ "", 72684 /* SIF_ST_RPRT_BILLING_RX_FIFO_ERR_INTERRUPT_REGISTER_TEST */ "", 72685 /* SIF_ST_RPRT_QSIZE_RX_FIFO_ERR_INTERRUPT_REGISTER */ "", 72686 /* SIF_ST_RPRT_QSIZE_RX_FIFO_ERR_INTERRUPT_REGISTER_MASK */ "", 72687 /* SIF_ST_RPRT_QSIZE_RX_FIFO_ERR_INTERRUPT_REGISTER_TEST */ "", 72688 /* SIMPLEREDCONFIG */ "", 72689 /* SLOT_PIPELINE_CONFIG */ "", 72690 /* SLOT_PIPELINE_ECC_STATUS_INTR */ "", 72691 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE0 */ "", 72692 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE1 */ "", 72693 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE2 */ "", 72694 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE3 */ "", 72695 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE4 */ "", 72696 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE5 */ "", 72697 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE6 */ "", 72698 /* SLOT_PIPELINE_ECC_STATUS_INTR_PIPE7 */ "", 72699 /* SLOT_REQ_INTERFACE */ "", 72700 /* SMAUIC_AXIIC_SMAU_M0_AR_B */ "", 72701 /* SMAUIC_AXIIC_SMAU_M0_AR_P */ "", 72702 /* SMAUIC_AXIIC_SMAU_M0_AR_R */ "", 72703 /* SMAUIC_AXIIC_SMAU_M0_AW_B */ "", 72704 /* SMAUIC_AXIIC_SMAU_M0_AW_P */ "", 72705 /* SMAUIC_AXIIC_SMAU_M0_AW_R */ "", 72706 /* SMAUIC_AXIIC_SMAU_M0_FN_MOD */ "", 72707 /* SMAUIC_AXIIC_SMAU_M0_KI */ "", 72708 /* SMAUIC_AXIIC_SMAU_M0_MAX_COMB_OT */ "", 72709 /* SMAUIC_AXIIC_SMAU_M0_MAX_OT */ "", 72710 /* SMAUIC_AXIIC_SMAU_M0_QOS_CNTL */ "", 72711 /* SMAUIC_AXIIC_SMAU_M0_QOS_RANGE */ "", 72712 /* SMAUIC_AXIIC_SMAU_M0_READ_QOS */ "", 72713 /* SMAUIC_AXIIC_SMAU_M0_TGT_LATENCY */ "", 72714 /* SMAUIC_AXIIC_SMAU_M0_WRITE_QOS */ "", 72715 /* SMAUIC_COMPONENT_ID0 */ "", 72716 /* SMAUIC_COMPONENT_ID1 */ "", 72717 /* SMAUIC_COMPONENT_ID2 */ "", 72718 /* SMAUIC_COMPONENT_ID3 */ "", 72719 /* SMAUIC_DDR_S0_FN_MOD_BM_ISS */ "", 72720 /* SMAUIC_DDR_S1_FN_MOD_BM_ISS */ "", 72721 /* SMAUIC_DDR_S2_FN_MOD_BM_ISS */ "", 72722 /* SMAUIC_DS_0_IDM_ERROR_LOG_ADDR_LSB */ "", 72723 /* SMAUIC_DS_0_IDM_ERROR_LOG_COMPLETE */ "", 72724 /* SMAUIC_DS_0_IDM_ERROR_LOG_CONTROL */ "", 72725 /* SMAUIC_DS_0_IDM_ERROR_LOG_FLAGS */ "", 72726 /* SMAUIC_DS_0_IDM_ERROR_LOG_ID */ "", 72727 /* SMAUIC_DS_0_IDM_ERROR_LOG_STATUS */ "", 72728 /* SMAUIC_DS_0_IDM_INTERRUPT_STATUS */ "", 72729 /* SMAUIC_DS_0_IDM_RESET_READ_ID */ "", 72730 /* SMAUIC_DS_0_IDM_RESET_STATUS */ "", 72731 /* SMAUIC_DS_0_IDM_RESET_WRITE_ID */ "", 72732 /* SMAUIC_IHOST_M1_AR_B */ "", 72733 /* SMAUIC_IHOST_M1_AR_P */ "", 72734 /* SMAUIC_IHOST_M1_AR_R */ "", 72735 /* SMAUIC_IHOST_M1_AW_B */ "", 72736 /* SMAUIC_IHOST_M1_AW_P */ "", 72737 /* SMAUIC_IHOST_M1_AW_R */ "", 72738 /* SMAUIC_IHOST_M1_FN_MOD */ "", 72739 /* SMAUIC_IHOST_M1_KI */ "", 72740 /* SMAUIC_IHOST_M1_MAX_COMB_OT */ "", 72741 /* SMAUIC_IHOST_M1_MAX_OT */ "", 72742 /* SMAUIC_IHOST_M1_QOS_CNTL */ "", 72743 /* SMAUIC_IHOST_M1_QOS_RANGE */ "", 72744 /* SMAUIC_IHOST_M1_READ_QOS */ "", 72745 /* SMAUIC_IHOST_M1_TGT_LATENCY */ "", 72746 /* SMAUIC_IHOST_M1_WRITE_QOS */ "", 72747 /* SMAUIC_PERIPHERAL_ID0 */ "", 72748 /* SMAUIC_PERIPHERAL_ID1 */ "", 72749 /* SMAUIC_PERIPHERAL_ID2 */ "", 72750 /* SMAUIC_PERIPHERAL_ID3 */ "", 72751 /* SMAUIC_PERIPHERAL_ID4 */ "", 72752 /* SMAUIC_PERIPHERAL_ID5 */ "", 72753 /* SMAUIC_PERIPHERAL_ID6 */ "", 72754 /* SMAUIC_PERIPHERAL_ID7 */ "", 72755 /* SMAUIC_SMAU_CRYPTO_FN_MOD_BM_ISS */ "", 72756 /* SMAUIC_SMAU_CRYPTO_M0_AR_B */ "", 72757 /* SMAUIC_SMAU_CRYPTO_M0_AR_P */ "", 72758 /* SMAUIC_SMAU_CRYPTO_M0_AR_R */ "", 72759 /* SMAUIC_SMAU_CRYPTO_M0_AW_B */ "", 72760 /* SMAUIC_SMAU_CRYPTO_M0_AW_P */ "", 72761 /* SMAUIC_SMAU_CRYPTO_M0_AW_R */ "", 72762 /* SMAUIC_SMAU_CRYPTO_M0_FN_MOD */ "", 72763 /* SMAUIC_SMAU_CRYPTO_M0_KI */ "", 72764 /* SMAUIC_SMAU_CRYPTO_M0_MAX_COMB_OT */ "", 72765 /* SMAUIC_SMAU_CRYPTO_M0_MAX_OT */ "", 72766 /* SMAUIC_SMAU_CRYPTO_M0_QOS_CNTL */ "", 72767 /* SMAUIC_SMAU_CRYPTO_M0_QOS_RANGE */ "", 72768 /* SMAUIC_SMAU_CRYPTO_M0_READ_QOS */ "", 72769 /* SMAUIC_SMAU_CRYPTO_M0_TGT_LATENCY */ "", 72770 /* SMAUIC_SMAU_CRYPTO_M0_WRITE_QOS */ "", 72771 /* SMAU_CACHE_CONTROL */ "", 72772 /* SMAU_CACHE_CTRL_DEBUG1 */ "", 72773 /* SMAU_CACHE_CTRL_DEBUG2 */ "", 72774 /* SMAU_CACHE_CTRL_DEBUG3 */ "", 72775 /* SMAU_CACHE_CTRL_STATUS1 */ "", 72776 /* SMAU_CACHE_CTRL_STATUS2 */ "", 72777 /* SMAU_CACHE_CTRL_STATUS3 */ "", 72778 /* SMAU_CACHE_ECC_STATUS1 */ "", 72779 /* SMAU_CACHE_ECC_STATUS2 */ "", 72780 /* SMAU_CACHE_ECC_STATUS3 */ "", 72781 /* SMAU_CACHE_ECC_STATUS4 */ "", 72782 /* SMAU_CONTROL */ "", 72783 /* SMAU_CRYPTO_AXI_PARAMS */ "", 72784 /* SMAU_CRYPTO_DEBUG_SEL0 */ "", 72785 /* SMAU_CRYPTO_M0_IDM_INTERRUPT_STATUS */ "", 72786 /* SMAU_CRYPTO_M0_IDM_RESET_CONTROL */ "", 72787 /* SMAU_CRYPTO_M0_IDM_RESET_STATUS */ "", 72788 /* SMAU_CRYPTO_PARAMS_0 */ "", 72789 /* SMAU_CRYPTO_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 72790 /* SMAU_CRYPTO_S0_IDM_ERROR_LOG_COMPLETE */ "", 72791 /* SMAU_CRYPTO_S0_IDM_ERROR_LOG_CONTROL */ "", 72792 /* SMAU_CRYPTO_S0_IDM_ERROR_LOG_FLAGS */ "", 72793 /* SMAU_CRYPTO_S0_IDM_ERROR_LOG_ID */ "", 72794 /* SMAU_CRYPTO_S0_IDM_ERROR_LOG_STATUS */ "", 72795 /* SMAU_CRYPTO_S0_IDM_INTERRUPT_STATUS */ "", 72796 /* SMAU_CRYPTO_S0_IDM_IO_CONTROL_DIRECT */ "", 72797 /* SMAU_CRYPTO_S0_IDM_IO_STATUS */ "", 72798 /* SMAU_CRYPTO_S0_IDM_RESET_CONTROL */ "", 72799 /* SMAU_CRYPTO_S0_IDM_RESET_READ_ID */ "", 72800 /* SMAU_CRYPTO_S0_IDM_RESET_STATUS */ "", 72801 /* SMAU_CRYPTO_S0_IDM_RESET_WRITE_ID */ "", 72802 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW0_LUT0 */ "", 72803 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW0_LUT1 */ "", 72804 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW1_LUT0 */ "", 72805 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW1_LUT1 */ "", 72806 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW2_LUT0 */ "", 72807 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW2_LUT1 */ "", 72808 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW3_LUT0 */ "", 72809 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW3_LUT1 */ "", 72810 /* SMAU_DDR_ADDR_SCRAMBLER_WINDOW4_LUT0 */ "", 72811 /* SMAU_DDR_AES_KEY_ENGINE0_WORD0 */ "", 72812 /* SMAU_DDR_AES_KEY_ENGINE0_WORD1 */ "", 72813 /* SMAU_DDR_AES_KEY_ENGINE0_WORD2 */ "", 72814 /* SMAU_DDR_AES_KEY_ENGINE0_WORD3 */ "", 72815 /* SMAU_DDR_AES_KEY_ENGINE0_WORD4 */ "", 72816 /* SMAU_DDR_AES_KEY_ENGINE0_WORD5 */ "", 72817 /* SMAU_DDR_AES_KEY_ENGINE0_WORD6 */ "", 72818 /* SMAU_DDR_AES_KEY_ENGINE0_WORD7 */ "", 72819 /* SMAU_DDR_AES_KEY_ENGINE1_WORD0 */ "", 72820 /* SMAU_DDR_AES_KEY_ENGINE1_WORD1 */ "", 72821 /* SMAU_DDR_AES_KEY_ENGINE1_WORD2 */ "", 72822 /* SMAU_DDR_AES_KEY_ENGINE1_WORD3 */ "", 72823 /* SMAU_DDR_AES_KEY_ENGINE1_WORD4 */ "", 72824 /* SMAU_DDR_AES_KEY_ENGINE1_WORD5 */ "", 72825 /* SMAU_DDR_AES_KEY_ENGINE1_WORD6 */ "", 72826 /* SMAU_DDR_AES_KEY_ENGINE1_WORD7 */ "", 72827 /* SMAU_DDR_ARD_AAD_WORD0 */ "", 72828 /* SMAU_DDR_ARD_AAD_WORD1 */ "", 72829 /* SMAU_DDR_ARD_AAD_WORD2 */ "", 72830 /* SMAU_DDR_ARD_AAD_WORD3 */ "", 72831 /* SMAU_DDR_CW0_DATA_WINDOW_BASE */ "", 72832 /* SMAU_DDR_CW0_DATA_WINDOW_END */ "", 72833 /* SMAU_DDR_CW0_HASH_WINDOW_BASE */ "", 72834 /* SMAU_DDR_CW0_HASH_WINDOW_END */ "", 72835 /* SMAU_DDR_CW0_PARAMS */ "", 72836 /* SMAU_DDR_CW1_DATA_WINDOW_BASE */ "", 72837 /* SMAU_DDR_CW1_DATA_WINDOW_END */ "", 72838 /* SMAU_DDR_CW1_HASH_WINDOW_BASE */ "", 72839 /* SMAU_DDR_CW1_HASH_WINDOW_END */ "", 72840 /* SMAU_DDR_CW1_PARAMS */ "", 72841 /* SMAU_DDR_CW2_DATA_WINDOW_BASE */ "", 72842 /* SMAU_DDR_CW2_DATA_WINDOW_END */ "", 72843 /* SMAU_DDR_CW2_HASH_WINDOW_BASE */ "", 72844 /* SMAU_DDR_CW2_HASH_WINDOW_END */ "", 72845 /* SMAU_DDR_CW2_PARAMS */ "", 72846 /* SMAU_DDR_CW3_DATA_WINDOW_BASE */ "", 72847 /* SMAU_DDR_CW3_DATA_WINDOW_END */ "", 72848 /* SMAU_DDR_CW3_HASH_WINDOW_BASE */ "", 72849 /* SMAU_DDR_CW3_HASH_WINDOW_END */ "", 72850 /* SMAU_DDR_CW3_PARAMS */ "", 72851 /* SMAU_DDR_CW_INIT_COUNTER */ "", 72852 /* SMAU_DDR_CW_LOAD_INIT_COUNTER */ "", 72853 /* SMAU_DDR_DATA_SCRAMBLER_MASH_FUNCTION */ "", 72854 /* SMAU_DDR_HSALT_WORD0 */ "", 72855 /* SMAU_DDR_HSALT_WORD1 */ "", 72856 /* SMAU_DDR_HSALT_WORD2 */ "", 72857 /* SMAU_DDR_HSALT_WORD3 */ "", 72858 /* SMAU_DDR_SCRAMBLER_CTRL */ "", 72859 /* SMAU_DDR_TZ_BASE */ "", 72860 /* SMAU_DDR_TZ_END */ "", 72861 /* SMAU_DEBUG_DECRYPTION_ADDR_CHANNEL */ "", 72862 /* SMAU_DEBUG_DECRYPTION_TOP */ "", 72863 /* SMAU_DEBUG_ENCRYPTION_TOP */ "", 72864 /* SMAU_DEBUG_ENCRYPTION_WR_RESP */ "", 72865 /* SMAU_DEBUG_INV_RD_DATA_CONV */ "", 72866 /* SMAU_DEBUG_INV_WR_TRANS_CONV */ "", 72867 /* SMAU_DEBUG_RD_DATA_CONV */ "", 72868 /* SMAU_DEBUG_RD_TRANS_CONV */ "", 72869 /* SMAU_DEBUG_WR_TRANS_CONV */ "", 72870 /* SMAU_DECRYPTION_LFSR_POLY */ "", 72871 /* SMAU_DECRYPTION_LFSR_SEED */ "", 72872 /* SMAU_DECRYPTION_LOAD_LFSR_SEED */ "", 72873 /* SMAU_DECRYPTION_PARAMS */ "", 72874 /* SMAU_ENCRYPTION_LFSR_POLY */ "", 72875 /* SMAU_ENCRYPTION_LFSR_SEED */ "", 72876 /* SMAU_ENCRYPTION_LOAD_LFSR_SEED */ "", 72877 /* SMAU_ENCRYPTION_PARAMS */ "", 72878 /* SMAU_FLASH0_TZ_BASE */ "", 72879 /* SMAU_FLASH0_TZ_END */ "", 72880 /* SMAU_FLASH1_TZ_BASE */ "", 72881 /* SMAU_FLASH1_TZ_END */ "", 72882 /* SMAU_FLASH2_TZ_BASE */ "", 72883 /* SMAU_FLASH2_TZ_END */ "", 72884 /* SMAU_FLASH3_TZ_BASE */ "", 72885 /* SMAU_FLASH3_TZ_END */ "", 72886 /* SMAU_FLASH_CW0_DATA_WINDOW_BASE */ "", 72887 /* SMAU_FLASH_CW0_DATA_WINDOW_END */ "", 72888 /* SMAU_FLASH_CW0_PARAMS */ "", 72889 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD0 */ "", 72890 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD1 */ "", 72891 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD2 */ "", 72892 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD3 */ "", 72893 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD4 */ "", 72894 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD5 */ "", 72895 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD6 */ "", 72896 /* SMAU_FLASH_CW1_AES_KEY_ENGINE0_WORD7 */ "", 72897 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD0 */ "", 72898 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD1 */ "", 72899 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD2 */ "", 72900 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD3 */ "", 72901 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD4 */ "", 72902 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD5 */ "", 72903 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD6 */ "", 72904 /* SMAU_FLASH_CW1_AES_KEY_ENGINE1_WORD7 */ "", 72905 /* SMAU_FLASH_CW1_DATA_WINDOW_BASE */ "", 72906 /* SMAU_FLASH_CW1_DATA_WINDOW_END */ "", 72907 /* SMAU_FLASH_CW1_PARAMS */ "", 72908 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD0 */ "", 72909 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD1 */ "", 72910 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD2 */ "", 72911 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD3 */ "", 72912 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD4 */ "", 72913 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD5 */ "", 72914 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD6 */ "", 72915 /* SMAU_FLASH_CW2_AES_KEY_ENGINE0_WORD7 */ "", 72916 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD0 */ "", 72917 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD1 */ "", 72918 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD2 */ "", 72919 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD3 */ "", 72920 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD4 */ "", 72921 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD5 */ "", 72922 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD6 */ "", 72923 /* SMAU_FLASH_CW2_AES_KEY_ENGINE1_WORD7 */ "", 72924 /* SMAU_FLASH_CW2_DATA_WINDOW_BASE */ "", 72925 /* SMAU_FLASH_CW2_DATA_WINDOW_END */ "", 72926 /* SMAU_FLASH_CW2_PARAMS */ "", 72927 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD0 */ "", 72928 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD1 */ "", 72929 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD2 */ "", 72930 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD3 */ "", 72931 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD4 */ "", 72932 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD5 */ "", 72933 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD6 */ "", 72934 /* SMAU_FLASH_CW3_AES_KEY_ENGINE0_WORD7 */ "", 72935 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD0 */ "", 72936 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD1 */ "", 72937 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD2 */ "", 72938 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD3 */ "", 72939 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD4 */ "", 72940 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD5 */ "", 72941 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD6 */ "", 72942 /* SMAU_FLASH_CW3_AES_KEY_ENGINE1_WORD7 */ "", 72943 /* SMAU_FLASH_CW3_DATA_WINDOW_BASE */ "", 72944 /* SMAU_FLASH_CW3_DATA_WINDOW_END */ "", 72945 /* SMAU_FLASH_CW3_PARAMS */ "", 72946 /* SMAU_IHOST_AXI_PARAMS */ "", 72947 /* SMAU_INTERRUPT_ENABLE */ "", 72948 /* SMAU_INTERRUPT_STATUS */ "", 72949 /* SMAU_MEM_TM0 */ "", 72950 /* SMAU_MEM_TM1 */ "", 72951 /* SMAU_PW_BASE */ "", 72952 /* SMAU_PW_END */ "", 72953 /* SMAU_PW_VALID */ "", 72954 /* SMAU_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 72955 /* SMAU_S0_IDM_ERROR_LOG_COMPLETE */ "", 72956 /* SMAU_S0_IDM_ERROR_LOG_CONTROL */ "", 72957 /* SMAU_S0_IDM_ERROR_LOG_FLAGS */ "", 72958 /* SMAU_S0_IDM_ERROR_LOG_ID */ "", 72959 /* SMAU_S0_IDM_ERROR_LOG_STATUS */ "", 72960 /* SMAU_S0_IDM_INTERRUPT_STATUS */ "", 72961 /* SMAU_S0_IDM_IO_CONTROL_DIRECT */ "", 72962 /* SMAU_S0_IDM_IO_STATUS */ "", 72963 /* SMAU_S0_IDM_RESET_CONTROL */ "", 72964 /* SMAU_S0_IDM_RESET_READ_ID */ "", 72965 /* SMAU_S0_IDM_RESET_STATUS */ "", 72966 /* SMAU_S0_IDM_RESET_WRITE_ID */ "", 72967 /* SMAU_SMAU_CID */ "", 72968 /* SMAU_SMAU_NIC_IDM_TZ_BASE */ "", 72969 /* SMAU_SMAU_NIC_IDM_TZ_END */ "", 72970 /* SMAU_STATUS */ "", 72971 /* SMBUS_TIMING_CONFIG_2 */ "", 72972 /* SMMEMDEBUG */ "", 72973 /* SM_NLF_MTU_CHECK */ "", 72974 /* SNAT_DISCARDS */ "", 72975 /* SNAT_DISCARDS_64 */ "SNAT_DISCARDS", 72976 /* SNAT_DISCARDS_64_PIPE0 */ "SNAT_DISCARDS_PIPE0", 72977 /* SNAT_DISCARDS_64_PIPE1 */ "SNAT_DISCARDS_PIPE1", 72978 /* SNAT_DISCARDS_64_PIPE2 */ "SNAT_DISCARDS_PIPE2", 72979 /* SNAT_DISCARDS_64_PIPE3 */ "SNAT_DISCARDS_PIPE3", 72980 /* SNAT_DISCARDS_PIPE0 */ "", 72981 /* SNAT_DISCARDS_PIPE1 */ "", 72982 /* SNAT_DISCARDS_PIPE2 */ "", 72983 /* SNAT_DISCARDS_PIPE3 */ "", 72984 /* SNAT_TRANSLATIONS */ "", 72985 /* SNAT_TRANSLATIONS_64 */ "SNAT_TRANSLATIONS", 72986 /* SNAT_TRANSLATIONS_64_PIPE0 */ "SNAT_TRANSLATIONS_PIPE0", 72987 /* SNAT_TRANSLATIONS_64_PIPE1 */ "SNAT_TRANSLATIONS_PIPE1", 72988 /* SNAT_TRANSLATIONS_64_PIPE2 */ "SNAT_TRANSLATIONS_PIPE2", 72989 /* SNAT_TRANSLATIONS_64_PIPE3 */ "SNAT_TRANSLATIONS_PIPE3", 72990 /* SNAT_TRANSLATIONS_NEEDED */ "", 72991 /* SNAT_TRANSLATIONS_NEEDED_64 */ "SNAT_TRANSLATIONS_NEEDED", 72992 /* SNAT_TRANSLATIONS_NEEDED_64_PIPE0 */ "SNAT_TRANSLATIONS_NEEDED_PIPE0", 72993 /* SNAT_TRANSLATIONS_NEEDED_64_PIPE1 */ "SNAT_TRANSLATIONS_NEEDED_PIPE1", 72994 /* SNAT_TRANSLATIONS_NEEDED_64_PIPE2 */ "SNAT_TRANSLATIONS_NEEDED_PIPE2", 72995 /* SNAT_TRANSLATIONS_NEEDED_64_PIPE3 */ "SNAT_TRANSLATIONS_NEEDED_PIPE3", 72996 /* SNAT_TRANSLATIONS_NEEDED_PIPE0 */ "", 72997 /* SNAT_TRANSLATIONS_NEEDED_PIPE1 */ "", 72998 /* SNAT_TRANSLATIONS_NEEDED_PIPE2 */ "", 72999 /* SNAT_TRANSLATIONS_NEEDED_PIPE3 */ "", 73000 /* SNAT_TRANSLATIONS_PIPE0 */ "", 73001 /* SNAT_TRANSLATIONS_PIPE1 */ "", 73002 /* SNAT_TRANSLATIONS_PIPE2 */ "", 73003 /* SNAT_TRANSLATIONS_PIPE3 */ "", 73004 /* SOFTRESETPBM */ "", 73005 /* SOFTRESETPBM_0 */ "", 73006 /* SOFTRESETPBM_1 */ "", 73007 /* SOFTRESETPBM_2 */ "", 73008 /* SOME_RDI_DEFECT_STATUS */ "", 73009 /* SOME_RMEP_CCM_DEFECT_STATUS */ "", 73010 /* SOP_CNT */ "", 73011 /* SOP_CNT_XPE0 */ "", 73012 /* SOTP_REGS_CHIP_CTRL */ "", 73013 /* SOTP_REGS_OTP_ADDR */ "", 73014 /* SOTP_REGS_OTP_BAD_ADDR */ "", 73015 /* SOTP_REGS_OTP_CTRL_0 */ "", 73016 /* SOTP_REGS_OTP_ECCCNT */ "", 73017 /* SOTP_REGS_OTP_PROG_CONTROL */ "", 73018 /* SOTP_REGS_OTP_RDDATA_0 */ "", 73019 /* SOTP_REGS_OTP_RDDATA_1 */ "", 73020 /* SOTP_REGS_OTP_RD_LOCK */ "", 73021 /* SOTP_REGS_OTP_STATUS_0 */ "", 73022 /* SOTP_REGS_OTP_STATUS_1 */ "", 73023 /* SOTP_REGS_OTP_WRDATA_0 */ "", 73024 /* SOTP_REGS_OTP_WRDATA_1 */ "", 73025 /* SOTP_REGS_OTP_WR_LOCK */ "", 73026 /* SOTP_REGS_ROM_BLOCK_END */ "", 73027 /* SOTP_REGS_ROM_BLOCK_START */ "", 73028 /* SOTP_REGS_SMAU_CTRL */ "", 73029 /* SOTP_REGS_SOTP_CHIP_STATES */ "", 73030 /* SOTP_REGS_SR_STATE_0 */ "", 73031 /* SOTP_REGS_SR_STATE_1 */ "", 73032 /* SOTP_REGS_SR_STATE_2 */ "", 73033 /* SOTP_REGS_SR_STATE_3 */ "", 73034 /* SOTP_REGS_SR_STATE_4 */ "", 73035 /* SOTP_REGS_SR_STATE_5 */ "", 73036 /* SOTP_REGS_SR_STATE_6 */ "", 73037 /* SOTP_REGS_SR_STATE_7 */ "", 73038 /* SOURCE_TRUNK_MAP_MODBASE_PARITY_CONTROL */ "", 73039 /* SOURCE_TRUNK_MAP_MODBASE_PARITY_STATUS */ "", 73040 /* SOURCE_TRUNK_MAP_MODVIEW_PARITY_CONTROL */ "", 73041 /* SOURCE_TRUNK_MAP_MODVIEW_PARITY_STATUS_INTR */ "", 73042 /* SOURCE_TRUNK_MAP_MODVIEW_PARITY_STATUS_NACK */ "", 73043 /* SOURCE_TRUNK_MAP_PARITY_CONTROL */ "", 73044 /* SOURCE_TRUNK_MAP_PARITY_STATUS */ "", 73045 /* SOURCE_VP_ECC_CONTROL */ "", 73046 /* SOURCE_VP_PARITY_CONTROL */ "", 73047 /* SOURCE_VP_PARITY_STATUS */ "", 73048 /* SOURCE_VP_PARITY_STATUS_INTR */ "", 73049 /* SOURCE_VP_PARITY_STATUS_NACK */ "", 73050 /* SOURCE_VP_PDA_CONTROL_0 */ "", 73051 /* SOURCE_VP_PDA_CONTROL_1 */ "", 73052 /* SP0_POOL_MODE */ "", 73053 /* SPARE_NLF_MTU_CHECK */ "", 73054 /* SPB_ALMOST_FULL_0_SRAM_REJECT_COUNTER */ "", 73055 /* SPB_ALMOST_FULL_1_SRAM_REJECT_COUNTER */ "", 73056 /* SPB_ALMOST_FULL_2_SRAM_REJECT_COUNTER */ "", 73057 /* SPB_ALMOST_FULL_SRAM_REJECT_COUNTER */ "", 73058 /* SPB_ALMOST_FULL_SRAM_REJECT_GLB_COUNTER */ "", 73059 /* SPB_AUTO_DOC_NAME_19 */ "", 73060 /* SPB_BRC_DEBUG */ "", 73061 /* SPB_BRC_DEBUG_2 */ "", 73062 /* SPB_BRC_S_2D_DEBUG */ "", 73063 /* SPB_BRC_S_2F_DEBUG */ "", 73064 /* SPB_COUNTERS_REASSEMBLYCONTEXTS */ "", 73065 /* SPB_CPU_REQUEST_REASSEMBLY_CONTEXT */ "", 73066 /* SPB_CPU_REQUEST_REGISTER */ "", 73067 /* SPB_DEBUG_COUNTERS */ "", 73068 /* SPB_DISCARDED_BYTES_CNT */ "", 73069 /* SPB_DISCARDED_PACKETS_CNT */ "", 73070 /* SPB_DROP_DESTINATION_CONFIGURATION */ "", 73071 /* SPB_DYNAMIC_CONFIGURATION */ "", 73072 /* SPB_ECC_1B_ERR_CNT */ "", 73073 /* SPB_ECC_2B_ERR_CNT */ "", 73074 /* SPB_ECC_ERR_1B_INITIATE */ "", 73075 /* SPB_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 73076 /* SPB_ECC_ERR_2B_INITIATE */ "", 73077 /* SPB_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 73078 /* SPB_ECC_INTERRUPT_REGISTER */ "", 73079 /* SPB_ECC_INTERRUPT_REGISTER_MASK */ "", 73080 /* SPB_ECC_INTERRUPT_REGISTER_TEST */ "", 73081 /* SPB_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 73082 /* SPB_ERROR_INITIATION_DATA */ "", 73083 /* SPB_FBC_STATUS */ "", 73084 /* SPB_FIFO_INTERRUPT_REGISTER */ "", 73085 /* SPB_FIFO_INTERRUPT_REGISTER_MASK */ "", 73086 /* SPB_FIFO_INTERRUPT_REGISTER_TEST */ "", 73087 /* SPB_FORCE_CRC_ERROR */ "", 73088 /* SPB_FPC_FREE_ERROR */ "", 73089 /* SPB_FPC_STATUS */ "", 73090 /* SPB_FULL_SRAM_REJECT_COUNTER */ "", 73091 /* SPB_GLOBAL_GENERAL_CFG_3 */ "", 73092 /* SPB_GLOBAL_MEM_OPTIONS */ "", 73093 /* SPB_GTIMER_CONFIGURATION */ "", 73094 /* SPB_GTIMER_CYCLE */ "", 73095 /* SPB_INDIRECT_COMMAND */ "", 73096 /* SPB_INDIRECT_COMMAND_ADDRESS */ "", 73097 /* SPB_INDIRECT_COMMAND_DATA_INCREMENT */ "", 73098 /* SPB_INDIRECT_COMMAND_RD_DATA */ "", 73099 /* SPB_INDIRECT_COMMAND_WIDE_MEM */ "", 73100 /* SPB_INDIRECT_COMMAND_WR_DATA */ "", 73101 /* SPB_INDIRECT_FORCE_BUBBLE */ "", 73102 /* SPB_INTERRUPT_MASK_REGISTER */ "", 73103 /* SPB_INTERRUPT_REGISTER */ "", 73104 /* SPB_INTERRUPT_REGISTER_TEST */ "", 73105 /* SPB_LAST_BUFF_RELEASE_CMD */ "", 73106 /* SPB_LAST_DBM_READ */ "", 73107 /* SPB_LAST_DBM_WRITE */ "", 73108 /* SPB_LAST_DEQ_CMD */ "", 73109 /* SPB_LAST_DEQ_PKT */ "", 73110 /* SPB_LAST_LEARN_INFO */ "", 73111 /* SPB_LAST_LEARN_INFO_RPRT */ "", 73112 /* SPB_LAST_REAS_REPORT */ "", 73113 /* SPB_LAST_REL_RPRT */ "", 73114 /* SPB_LAST_TX_RPRT */ "", 73115 /* SPB_LEARN_INFO_COUNTER */ "", 73116 /* SPB_OCB_STATUS */ "", 73117 /* SPB_OW_PP_PORT_WITH_RSM_CONTEXT */ "", 73118 /* SPB_PACKET_REASSEMBLY_INTERRUPT_REGISTER_MASK */ "", 73119 /* SPB_PACKET_REJECT_TH */ "", 73120 /* SPB_PARITY_ERR_CNT */ "", 73121 /* SPB_PAR_ERR_MEM_MASK */ "", 73122 /* SPB_PCMI_0 */ "", 73123 /* SPB_PCMI_1 */ "", 73124 /* SPB_PCMI_2 */ "", 73125 /* SPB_PCMI_3 */ "", 73126 /* SPB_PCMI_4 */ "", 73127 /* SPB_PCMI_0_S */ "", 73128 /* SPB_PCMI_0_T */ "", 73129 /* SPB_PCMI_1_S */ "", 73130 /* SPB_PCMI_1_T */ "", 73131 /* SPB_PCMI_2_S */ "", 73132 /* SPB_PCMI_2_T */ "", 73133 /* SPB_PCMI_3_S */ "", 73134 /* SPB_PCMI_3_T */ "", 73135 /* SPB_PCMI_4_S */ "", 73136 /* SPB_PCMI_4_T */ "", 73137 /* SPB_PEC_DEBUG */ "", 73138 /* SPB_PEC_DEBUG_2 */ "", 73139 /* SPB_PEC_STATUS */ "", 73140 /* SPB_PTC_STATUS */ "", 73141 /* SPB_PTC_S_2D_DEBUG */ "", 73142 /* SPB_PTC_S_2F_DEBUG */ "", 73143 /* SPB_REASSEMBLY_ERRORS */ "", 73144 /* SPB_REASSEMBLY_INTERRUPT_REGISTER */ "", 73145 /* SPB_REASSEMBLY_INTERRUPT_REGISTER_MASK */ "", 73146 /* SPB_REASSEMBLY_INTERRUPT_REGISTER_TEST */ "", 73147 /* SPB_REASSEMBLY_TIMEOUT */ "", 73148 /* SPB_RECEIVED_BYTES_CNT */ "", 73149 /* SPB_RECEIVED_PACKETS_CNT */ "", 73150 /* SPB_REG_0041 */ "", 73151 /* SPB_REG_0106 */ "", 73152 /* SPB_REG_00A4 */ "", 73153 /* SPB_REG_00A6 */ "", 73154 /* SPB_REG_00AA */ "", 73155 /* SPB_REG_00C2 */ "", 73156 /* SPB_REG_00C5 */ "", 73157 /* SPB_RESERVED_MIRROR_ADDR */ "", 73158 /* SPB_RESERVED_MTCD */ "", 73159 /* SPB_RESERVED_MTCP */ "", 73160 /* SPB_RESERVED_PCMI_0 */ "", 73161 /* SPB_RESERVED_PCMI_1 */ "", 73162 /* SPB_RESERVED_PCMI_2 */ "", 73163 /* SPB_RESERVED_PCMI_3 */ "", 73164 /* SPB_RESERVED_PCMI_4 */ "", 73165 /* SPB_RESERVED_PCMI_0_S */ "", 73166 /* SPB_RESERVED_PCMI_0_T */ "", 73167 /* SPB_RESERVED_PCMI_1_S */ "", 73168 /* SPB_RESERVED_PCMI_1_T */ "", 73169 /* SPB_RESERVED_PCMI_2_S */ "", 73170 /* SPB_RESERVED_PCMI_2_T */ "", 73171 /* SPB_RESERVED_PCMI_3_S */ "", 73172 /* SPB_RESERVED_PCMI_3_T */ "", 73173 /* SPB_RESERVED_PCMI_4_S */ "", 73174 /* SPB_RESERVED_PCMI_4_T */ "", 73175 /* SPB_RESERVED_SPARE_0 */ "", 73176 /* SPB_RESERVED_SPARE_1 */ "", 73177 /* SPB_RESERVED_SPARE_2 */ "", 73178 /* SPB_RESERVED_SPARE_3 */ "", 73179 /* SPB_RESET_STATUS_REGISTER */ "", 73180 /* SPB_RXI_COUNTER */ "", 73181 /* SPB_SBUS_BROADCAST_ID */ "", 73182 /* SPB_SBUS_LAST_IN_CHAIN */ "", 73183 /* SPB_SPECIAL_CLOCK_CONTROLS */ "", 73184 /* SPB_STATIC_CONFIGURATION */ "", 73185 /* SPB_S_2D_RPC_CFG */ "", 73186 /* SPB_S_2F_RPC_CFG */ "", 73187 /* SPB_TIMEOUT_REG */ "", 73188 /* SPB_TIMEOUT_VALID_REG */ "", 73189 /* SPB_TXI_COUNTER */ "", 73190 /* SPEED_LIMIT_ENTRY0_PHYSICAL_PORT_NUMBER */ "", 73191 /* SPEED_LIMIT_ENTRY10_PHYSICAL_PORT_NUMBER */ "", 73192 /* SPEED_LIMIT_ENTRY11_PHYSICAL_PORT_NUMBER */ "", 73193 /* SPEED_LIMIT_ENTRY12_PHYSICAL_PORT_NUMBER */ "", 73194 /* SPEED_LIMIT_ENTRY13_PHYSICAL_PORT_NUMBER */ "", 73195 /* SPEED_LIMIT_ENTRY14_PHYSICAL_PORT_NUMBER */ "", 73196 /* SPEED_LIMIT_ENTRY15_PHYSICAL_PORT_NUMBER */ "", 73197 /* SPEED_LIMIT_ENTRY16_PHYSICAL_PORT_NUMBER */ "", 73198 /* SPEED_LIMIT_ENTRY17_PHYSICAL_PORT_NUMBER */ "", 73199 /* SPEED_LIMIT_ENTRY18_PHYSICAL_PORT_NUMBER */ "", 73200 /* SPEED_LIMIT_ENTRY19_PHYSICAL_PORT_NUMBER */ "", 73201 /* SPEED_LIMIT_ENTRY1_PHYSICAL_PORT_NUMBER */ "", 73202 /* SPEED_LIMIT_ENTRY20_PHYSICAL_PORT_NUMBER */ "", 73203 /* SPEED_LIMIT_ENTRY21_PHYSICAL_PORT_NUMBER */ "", 73204 /* SPEED_LIMIT_ENTRY22_PHYSICAL_PORT_NUMBER */ "", 73205 /* SPEED_LIMIT_ENTRY23_PHYSICAL_PORT_NUMBER */ "", 73206 /* SPEED_LIMIT_ENTRY24_PHYSICAL_PORT_NUMBER */ "", 73207 /* SPEED_LIMIT_ENTRY25_PHYSICAL_PORT_NUMBER */ "", 73208 /* SPEED_LIMIT_ENTRY26_PHYSICAL_PORT_NUMBER */ "", 73209 /* SPEED_LIMIT_ENTRY27_PHYSICAL_PORT_NUMBER */ "", 73210 /* SPEED_LIMIT_ENTRY28_PHYSICAL_PORT_NUMBER */ "", 73211 /* SPEED_LIMIT_ENTRY29_PHYSICAL_PORT_NUMBER */ "", 73212 /* SPEED_LIMIT_ENTRY2_PHYSICAL_PORT_NUMBER */ "", 73213 /* SPEED_LIMIT_ENTRY30_PHYSICAL_PORT_NUMBER */ "", 73214 /* SPEED_LIMIT_ENTRY31_PHYSICAL_PORT_NUMBER */ "", 73215 /* SPEED_LIMIT_ENTRY32_PHYSICAL_PORT_NUMBER */ "", 73216 /* SPEED_LIMIT_ENTRY33_PHYSICAL_PORT_NUMBER */ "", 73217 /* SPEED_LIMIT_ENTRY34_PHYSICAL_PORT_NUMBER */ "", 73218 /* SPEED_LIMIT_ENTRY35_PHYSICAL_PORT_NUMBER */ "", 73219 /* SPEED_LIMIT_ENTRY36_PHYSICAL_PORT_NUMBER */ "", 73220 /* SPEED_LIMIT_ENTRY37_PHYSICAL_PORT_NUMBER */ "", 73221 /* SPEED_LIMIT_ENTRY38_PHYSICAL_PORT_NUMBER */ "", 73222 /* SPEED_LIMIT_ENTRY39_PHYSICAL_PORT_NUMBER */ "", 73223 /* SPEED_LIMIT_ENTRY3_PHYSICAL_PORT_NUMBER */ "", 73224 /* SPEED_LIMIT_ENTRY4_PHYSICAL_PORT_NUMBER */ "", 73225 /* SPEED_LIMIT_ENTRY5_PHYSICAL_PORT_NUMBER */ "", 73226 /* SPEED_LIMIT_ENTRY6_PHYSICAL_PORT_NUMBER */ "", 73227 /* SPEED_LIMIT_ENTRY7_PHYSICAL_PORT_NUMBER */ "", 73228 /* SPEED_LIMIT_ENTRY8_PHYSICAL_PORT_NUMBER */ "", 73229 /* SPEED_LIMIT_ENTRY9_PHYSICAL_PORT_NUMBER */ "", 73230 /* SPL_CALIB_0 */ "", 73231 /* SPL_CALIB_1 */ "", 73232 /* SPL_CALIB_2 */ "", 73233 /* SPL_FREQ_MON_EN_0 */ "", 73234 /* SPL_FREQ_MON_EN_1 */ "", 73235 /* SPL_FREQ_MON_EN_2 */ "", 73236 /* SPL_HIGH_THRESH_0 */ "", 73237 /* SPL_HIGH_THRESH_1 */ "", 73238 /* SPL_HIGH_THRESH_2 */ "", 73239 /* SPL_LOW_THRESH_0 */ "", 73240 /* SPL_LOW_THRESH_1 */ "", 73241 /* SPL_LOW_THRESH_2 */ "", 73242 /* SPL_MONITOR_POINT_0 */ "", 73243 /* SPL_MONITOR_POINT_1 */ "", 73244 /* SPL_MONITOR_POINT_2 */ "", 73245 /* SPL_RST_CNT_THRESH_0 */ "", 73246 /* SPL_RST_CNT_THRESH_1 */ "", 73247 /* SPL_RST_CNT_THRESH_2 */ "", 73248 /* SPL_RST_CNT_THRESH_3 */ "", 73249 /* SPL_RST_CNT_VAL_0 */ "", 73250 /* SPL_RST_CNT_VAL_1 */ "", 73251 /* SPL_RST_CNT_VAL_2 */ "", 73252 /* SPL_RST_CNT_VAL_3 */ "", 73253 /* SPL_RST_MON_EN_0 */ "", 73254 /* SPL_RST_MON_EN_1 */ "", 73255 /* SPL_RST_MON_EN_2 */ "", 73256 /* SPL_RST_MON_EN_3 */ "", 73257 /* SPL_WDOG */ "", 73258 /* SPL_WIN_CNT_THRESH_0 */ "", 73259 /* SPL_WIN_CNT_THRESH_1 */ "", 73260 /* SPL_WIN_CNT_THRESH_2 */ "", 73261 /* SPL_WIN_CNT_THRESH_3 */ "", 73262 /* SPL_WIN_CNT_VAL_0 */ "", 73263 /* SPL_WIN_CNT_VAL_1 */ "", 73264 /* SPL_WIN_CNT_VAL_2 */ "", 73265 /* SPL_WIN_CNT_VAL_3 */ "", 73266 /* SPORT_CTL_REG */ "", 73267 /* SPORT_ECC_CONTROL */ "", 73268 /* SPORT_FORCE_DOUBLE_BIT_ERROR */ "", 73269 /* SPORT_FORCE_SINGLE_BIT_ERROR */ "", 73270 /* SPORT_INTR_ENABLE */ "", 73271 /* SPORT_INTR_STATUS */ "", 73272 /* SPORT_RX_FIFO_MEM_ECC_STATUS */ "", 73273 /* SPORT_TX_FIFO_MEM_ECC_STATUS */ "", 73274 /* SPUM_APB_REGS_CRKEY_MASK_1 */ "", 73275 /* SPUM_APB_REGS_CRKEY_MASK_2 */ "", 73276 /* SPUM_APB_REGS_CRKEY_MASK_3 */ "", 73277 /* SPUM_APB_REGS_CRKEY_MASK_4 */ "", 73278 /* SPUM_APB_REGS_CRKEY_MASK_5 */ "", 73279 /* SPUM_APB_REGS_CRKEY_MASK_6 */ "", 73280 /* SPUM_APB_REGS_CRKEY_MASK_7 */ "", 73281 /* SPUM_APB_REGS_CRKEY_MASK_8 */ "", 73282 /* SPUM_APB_REGS_CTRL */ "", 73283 /* SPUM_APB_REGS_DATA_1_SEED */ "", 73284 /* SPUM_APB_REGS_DATA_2_SEED */ "", 73285 /* SPUM_APB_REGS_DATA_3_SEED */ "", 73286 /* SPUM_APB_REGS_DATA_4_SEED */ "", 73287 /* SPUM_APB_REGS_DATA_5_SEED */ "", 73288 /* SPUM_APB_REGS_DATA_6_SEED */ "", 73289 /* SPUM_APB_REGS_DATA_7_SEED */ "", 73290 /* SPUM_APB_REGS_DATA_8_SEED */ "", 73291 /* SPUM_APB_REGS_DATA_9_SEED */ "", 73292 /* SPUM_APB_REGS_DATA_MASK_1 */ "", 73293 /* SPUM_APB_REGS_DATA_MASK_2 */ "", 73294 /* SPUM_APB_REGS_DPA_CFG */ "", 73295 /* SPUM_APB_REGS_KCBAR */ "", 73296 /* SPUM_APB_REGS_KCECC */ "", 73297 /* SPUM_APB_REGS_KEY_1_SEED */ "", 73298 /* SPUM_APB_REGS_KEY_2_SEED */ "", 73299 /* SPUM_APB_REGS_KEY_3_SEED */ "", 73300 /* SPUM_APB_REGS_KEY_4_SEED */ "", 73301 /* SPUM_APB_REGS_KEY_5_SEED */ "", 73302 /* SPUM_APB_REGS_KEY_6_SEED */ "", 73303 /* SPUM_APB_REGS_KEY_7_SEED */ "", 73304 /* SPUM_APB_REGS_KEY_8_SEED */ "", 73305 /* SPUM_APB_REGS_KEY_9_SEED */ "", 73306 /* SPUM_APB_REGS_RAND_STALL_1 */ "", 73307 /* SPUM_APB_REGS_RAND_STALL_2 */ "", 73308 /* SPUM_APB_REGS_RDI_1 */ "", 73309 /* SPUM_APB_REGS_RDI_2 */ "", 73310 /* SPUM_APB_REGS_STAT */ "", 73311 /* SPUM_AXI_REGS_AXI_ACCESS */ "", 73312 /* SPUM_AXI_REGS_AXI_DBG0 */ "", 73313 /* SPUM_AXI_REGS_AXI_DBG1 */ "", 73314 /* SPUM_AXI_REGS_AXI_REACT */ "", 73315 /* SPUM_AXI_REGS_DMA_CTL */ "", 73316 /* SPUM_AXI_REGS_DMA_STAT */ "", 73317 /* SPUM_AXI_REGS_FIFO_IN */ "", 73318 /* SPUM_AXI_REGS_FIFO_OUT */ "", 73319 /* SPUM_AXI_REGS_FIFO_STAT */ "", 73320 /* SPUM_AXI_REGS_INT_MASK */ "", 73321 /* SPUM_AXI_REGS_INT_STAT */ "", 73322 /* SPUM_AXI_REGS_IN_DMA_SIZE */ "", 73323 /* SPUM_AXI_REGS_OUT_DMA_SIZE */ "", 73324 /* SPUM_AXI_REGS_VIO_ADDR_STAT */ "", 73325 /* SPUM_AXI_REGS_VIO_CTL_STAT */ "", 73326 /* SP_CAM_BIST_CONFIG */ "", 73327 /* SP_CAM_BIST_CONTROL */ "", 73328 /* SP_CAM_BIST_DBG */ "", 73329 /* SP_CAM_BIST_STATUS */ "", 73330 /* SP_GLB_CTRL */ "", 73331 /* SP_GLB_INTR_EN */ "", 73332 /* SP_GLB_INTR_STATUS */ "", 73333 /* SP_GLB_MIB_CTRL */ "", 73334 /* SP_GLB_MIB_STS0 */ "", 73335 /* SP_GLB_MIB_STS1 */ "", 73336 /* SP_GLB_OLP_RX_TYPE */ "", 73337 /* SP_GLB_PRESCALE */ "", 73338 /* SP_GLB_SA_STS_SAK_EXPIRED_P0 */ "", 73339 /* SP_GLB_SA_STS_SAK_EXPIRED_P1 */ "", 73340 /* SP_GLB_SA_STS_SAK_EXPIRED_P2 */ "", 73341 /* SP_GLB_SA_STS_SAK_EXPIRED_P3 */ "", 73342 /* SP_GLB_SECTAG_ETYPE0_1 */ "", 73343 /* SP_GLB_SECTAG_ETYPE2_3 */ "", 73344 /* SP_GLB_TIMETICK */ "", 73345 /* SP_TEST1 */ "", 73346 /* SP_TEST2 */ "", 73347 /* SP_TEST3 */ "", 73348 /* SP_TEST4 */ "", 73349 /* SP_TEST5 */ "", 73350 /* SQFSUM1_TCID_0 */ "", 73351 /* SQFSUM1_TCID_1 */ "", 73352 /* SQFSUM1_TCID_2 */ "", 73353 /* SQFSUM1_TCID_3 */ "", 73354 /* SQFSUM1_TCID_4 */ "", 73355 /* SQFSUM1_TCID_5 */ "", 73356 /* SQFSUM1_TCID_6 */ "", 73357 /* SQFSUM1_TCID_7 */ "", 73358 /* SQFSUM1_TCID_8 */ "", 73359 /* SQFSUM1_TCID_9 */ "", 73360 /* SQFSUM1_TCID_10 */ "", 73361 /* SQFSUM1_TCID_11 */ "", 73362 /* SQFSUM1_TCID_12 */ "", 73363 /* SQFSUM1_TCID_13 */ "", 73364 /* SQFSUM1_TCID_14 */ "", 73365 /* SQFSUM1_TCID_15 */ "", 73366 /* SQFSUM2_TCID_0 */ "", 73367 /* SQFSUM2_TCID_1 */ "", 73368 /* SQFSUM2_TCID_2 */ "", 73369 /* SQFSUM2_TCID_3 */ "", 73370 /* SQFSUM2_TCID_4 */ "", 73371 /* SQFSUM2_TCID_5 */ "", 73372 /* SQFSUM2_TCID_6 */ "", 73373 /* SQFSUM2_TCID_7 */ "", 73374 /* SQFSUM2_TCID_8 */ "", 73375 /* SQFSUM2_TCID_9 */ "", 73376 /* SQFSUM2_TCID_10 */ "", 73377 /* SQFSUM2_TCID_11 */ "", 73378 /* SQFSUM2_TCID_12 */ "", 73379 /* SQFSUM2_TCID_13 */ "", 73380 /* SQFSUM2_TCID_14 */ "", 73381 /* SQFSUM2_TCID_15 */ "", 73382 /* SQM_AUTO_DOC_NAME_9 */ "", 73383 /* SQM_AUTO_DOC_NAME_12 */ "", 73384 /* SQM_AUTO_DOC_NAME_27 */ "", 73385 /* SQM_AUTO_DOC_NAME_28 */ "", 73386 /* SQM_AUTO_DOC_NAME_32 */ "", 73387 /* SQM_AUTO_DOC_NAME_36 */ "", 73388 /* SQM_AUTO_DOC_NAME_38 */ "", 73389 /* SQM_AUTO_DOC_NAME_40 */ "", 73390 /* SQM_AUTO_DOC_NAME_42 */ "", 73391 /* SQM_AUTO_DOC_NAME_45 */ "", 73392 /* SQM_AUTO_DOC_NAME_48 */ "", 73393 /* SQM_AUTO_DOC_NAME_51 */ "", 73394 /* SQM_BUNDLE_DEQ_CTR */ "", 73395 /* SQM_DCC_NO_ACTIVE_READS_CTR */ "", 73396 /* SQM_DCC_READ_ACTIVE_CTR_STATUS */ "", 73397 /* SQM_DEQ_BUNDLE_SETTINGS */ "", 73398 /* SQM_DEQ_DRAM_BUNDLE_SETTINGS */ "", 73399 /* SQM_DEQ_FAB_BUNDLE_SETTINGS */ "", 73400 /* SQM_DEQ_READ_WEIGHT */ "", 73401 /* SQM_ECC_1B_ERR_CNT */ "", 73402 /* SQM_ECC_2B_ERR_CNT */ "", 73403 /* SQM_ECC_ERR_1B_INITIATE */ "", 73404 /* SQM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 73405 /* SQM_ECC_ERR_2B_INITIATE */ "", 73406 /* SQM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 73407 /* SQM_ECC_INTERRUPT_REGISTER */ "", 73408 /* SQM_ECC_INTERRUPT_REGISTER_MASK */ "", 73409 /* SQM_ECC_INTERRUPT_REGISTER_TEST */ "", 73410 /* SQM_ENABLERS */ "", 73411 /* SQM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 73412 /* SQM_ERROR_INITIATION_DATA */ "", 73413 /* SQM_FPC_CACHE_CLEAN */ "", 73414 /* SQM_FPC_FREE_ERROR_PTR */ "", 73415 /* SQM_FR_PDB_CTR */ "", 73416 /* SQM_GLOBAL_MEM_OPTIONS */ "", 73417 /* SQM_GTIMER_CONFIGURATION */ "", 73418 /* SQM_GTIMER_CYCLE */ "", 73419 /* SQM_INDIRECT_COMMAND */ "", 73420 /* SQM_INDIRECT_COMMAND_ADDRESS */ "", 73421 /* SQM_INDIRECT_COMMAND_DATA_INCREMENT */ "", 73422 /* SQM_INDIRECT_COMMAND_RD_DATA */ "", 73423 /* SQM_INDIRECT_COMMAND_WIDE_MEM */ "", 73424 /* SQM_INDIRECT_COMMAND_WR_DATA */ "", 73425 /* SQM_INDIRECT_FORCE_BUBBLE */ "", 73426 /* SQM_INIT_ON */ "", 73427 /* SQM_INTERNAL_SETTINGS */ "", 73428 /* SQM_INTERRUPT_MASK_REGISTER */ "", 73429 /* SQM_INTERRUPT_REGISTER */ "", 73430 /* SQM_INTERRUPT_REGISTER_TEST */ "", 73431 /* SQM_LAST_DEQ_CMD */ "", 73432 /* SQM_LAST_ENQ_CMD */ "", 73433 /* SQM_PDB_ALLOCATE_NRDY_CTR */ "", 73434 /* SQM_PDB_RELEASE_NRDY_CTR */ "", 73435 /* SQM_PDM_RD_ACCESS_DROP_CTR */ "", 73436 /* SQM_PDM_RD_ACCESS_VALID_CTR */ "", 73437 /* SQM_PDM_WR_ACCESS_VALID_CTR */ "", 73438 /* SQM_PEND_RD_COMP_SIZE */ "", 73439 /* SQM_PKT_DEQ_CTR */ "", 73440 /* SQM_PKT_ENQ_CTR */ "", 73441 /* SQM_QDC_ERR_INTERRUPT_REGISTER */ "", 73442 /* SQM_QDC_ERR_INTERRUPT_REGISTER_MASK */ "", 73443 /* SQM_QDC_ERR_INTERRUPT_REGISTER_TEST */ "", 73444 /* SQM_REG_0041 */ "", 73445 /* SQM_REG_0106 */ "", 73446 /* SQM_REG_0107 */ "", 73447 /* SQM_REG_0120 */ "", 73448 /* SQM_REG_0122 */ "", 73449 /* SQM_REG_0125 */ "", 73450 /* SQM_REG_0127 */ "", 73451 /* SQM_REG_0128 */ "", 73452 /* SQM_REG_00A4 */ "", 73453 /* SQM_REG_00A6 */ "", 73454 /* SQM_REG_00C2 */ "", 73455 /* SQM_REG_00C7 */ "", 73456 /* SQM_REG_011B */ "", 73457 /* SQM_REG_011C */ "", 73458 /* SQM_REG_011E */ "", 73459 /* SQM_REG_011F */ "", 73460 /* SQM_RESERVED_MIRROR_ADDR */ "", 73461 /* SQM_RESERVED_MTCD */ "", 73462 /* SQM_RESERVED_MTCP */ "", 73463 /* SQM_RESERVED_SPARE_0 */ "", 73464 /* SQM_RESERVED_SPARE_1 */ "", 73465 /* SQM_RESERVED_SPARE_2 */ "", 73466 /* SQM_RESERVED_SPARE_3 */ "", 73467 /* SQM_SBUS_BROADCAST_ID */ "", 73468 /* SQM_SBUS_LAST_IN_CHAIN */ "", 73469 /* SQM_SQM_ENABLERS */ "", 73470 /* SQM_SQM_INIT */ "", 73471 /* SQM_TO_DRAM_IQM_PKT_TX_NRDY_CTR */ "", 73472 /* SQM_TO_DRAM_TX_BUNDLE_FIFO_MAX_STATUS */ "", 73473 /* SQM_TO_DRAM_TX_PD_FIFO_MAX_STATUS */ "", 73474 /* SQM_TO_FABRIC_IQM_PKT_TX_NRDY_CTR */ "", 73475 /* SQM_TO_FABRIC_TX_BUNDLE_FIFO_MAX_STATUS */ "", 73476 /* SQM_TO_FABRIC_TX_PD_FIFO_MAX_STATUS */ "", 73477 /* SQM_TX_FIFO_ERR_INTERRUPT_REGISTER */ "", 73478 /* SQM_TX_FIFO_ERR_INTERRUPT_REGISTER_MASK */ "", 73479 /* SQM_TX_FIFO_ERR_INTERRUPT_REGISTER_TEST */ "", 73480 /* SQM_UPDT_RPRT_SETTINGS */ "", 73481 /* SRAM_0_ECC_ERROR_ADDRESS */ "", 73482 /* SRAM_0_ECC_ERROR_STATUS */ "", 73483 /* SRAM_1_ECC_ERROR_ADDRESS */ "", 73484 /* SRAM_1_ECC_ERROR_STATUS */ "", 73485 /* SRAM_2_ECC_ERROR_ADDRESS */ "", 73486 /* SRAM_2_ECC_ERROR_STATUS */ "", 73487 /* SRAM_3_ECC_ERROR_ADDRESS */ "", 73488 /* SRAM_3_ECC_ERROR_STATUS */ "", 73489 /* SRAM_4_ECC_ERROR_ADDRESS */ "", 73490 /* SRAM_4_ECC_ERROR_STATUS */ "", 73491 /* SRAM_5_ECC_ERROR_ADDRESS */ "", 73492 /* SRAM_5_ECC_ERROR_STATUS */ "", 73493 /* SRAM_6_ECC_ERROR_ADDRESS */ "", 73494 /* SRAM_6_ECC_ERROR_STATUS */ "", 73495 /* SRAM_7_ECC_ERROR_ADDRESS */ "", 73496 /* SRAM_7_ECC_ERROR_STATUS */ "", 73497 /* SRAM_ECC_INTR_CLEAR */ "", 73498 /* SRAM_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 73499 /* SRAM_IDM_IDM_ERROR_LOG_COMPLETE */ "", 73500 /* SRAM_IDM_IDM_ERROR_LOG_CONTROL */ "", 73501 /* SRAM_IDM_IDM_ERROR_LOG_FLAGS */ "", 73502 /* SRAM_IDM_IDM_ERROR_LOG_ID */ "", 73503 /* SRAM_IDM_IDM_ERROR_LOG_STATUS */ "", 73504 /* SRAM_IDM_IDM_INTERRUPT_STATUS */ "", 73505 /* SRAM_IDM_IDM_IO_CONTROL_DIRECT */ "", 73506 /* SRAM_IDM_IDM_IO_STATUS */ "", 73507 /* SRAM_IDM_IDM_RESET_CONTROL */ "", 73508 /* SRAM_IDM_IDM_RESET_READ_ID */ "", 73509 /* SRAM_IDM_IDM_RESET_STATUS */ "", 73510 /* SRAM_IDM_IDM_RESET_WRITE_ID */ "", 73511 /* SRAM_LL_1024K_0_CONTROL1 */ "", 73512 /* SRAM_LL_1024K_0_DYNAMIC_STANDBY_CONTROL1 */ "", 73513 /* SRAM_LL_1024K_0_DYNAMIC_STANDBY_CONTROL2 */ "", 73514 /* SRAM_LL_1024K_0_INTERRUPT_ENABLE */ "", 73515 /* SRAM_LL_1024K_0_INTERRUPT_STATUS */ "", 73516 /* SRAM_LL_1024K_0_MEMORY_CONTROL */ "", 73517 /* SRAM_LL_1024K_0_MEMORY_PDA */ "", 73518 /* SRAM_LL_1024K_0_MEM_PWR_CONTROL */ "", 73519 /* SRAM_LL_1024K_0_STATUS1 */ "", 73520 /* SRAM_LL_1024K_0_STATUS2 */ "", 73521 /* SRAM_LL_1024K_0_STATUS3 */ "", 73522 /* SRAM_LL_1024K_0_STATUS4 */ "", 73523 /* SRAM_LL_1024K_0_STATUS5 */ "", 73524 /* SRAM_LL_1024K_0_STATUS6 */ "", 73525 /* SRAM_LL_1024K_0_STATUS7 */ "", 73526 /* SRAM_LL_1024K_0_STATUS8 */ "", 73527 /* SRAM_LL_1024K_0_STATUS9 */ "", 73528 /* SRAM_LL_1024K_0_STATUS10 */ "", 73529 /* SRAM_LL_32K_CONTROL1 */ "", 73530 /* SRAM_LL_32K_DYNAMIC_STANDBY_CONTROL1 */ "", 73531 /* SRAM_LL_32K_DYNAMIC_STANDBY_CONTROL2 */ "", 73532 /* SRAM_LL_32K_IDM_IDM_ERROR_LOG_ADDR_LSB */ "", 73533 /* SRAM_LL_32K_IDM_IDM_ERROR_LOG_COMPLETE */ "", 73534 /* SRAM_LL_32K_IDM_IDM_ERROR_LOG_CONTROL */ "", 73535 /* SRAM_LL_32K_IDM_IDM_ERROR_LOG_FLAGS */ "", 73536 /* SRAM_LL_32K_IDM_IDM_ERROR_LOG_ID */ "", 73537 /* SRAM_LL_32K_IDM_IDM_ERROR_LOG_STATUS */ "", 73538 /* SRAM_LL_32K_IDM_IDM_INTERRUPT_STATUS */ "", 73539 /* SRAM_LL_32K_IDM_IDM_IO_CONTROL_DIRECT */ "", 73540 /* SRAM_LL_32K_IDM_IDM_IO_STATUS */ "", 73541 /* SRAM_LL_32K_IDM_IDM_RESET_CONTROL */ "", 73542 /* SRAM_LL_32K_IDM_IDM_RESET_READ_ID */ "", 73543 /* SRAM_LL_32K_IDM_IDM_RESET_STATUS */ "", 73544 /* SRAM_LL_32K_IDM_IDM_RESET_WRITE_ID */ "", 73545 /* SRAM_LL_32K_INTERRUPT_ENABLE */ "", 73546 /* SRAM_LL_32K_INTERRUPT_STATUS */ "", 73547 /* SRAM_LL_32K_MEMORY_CONTROL */ "", 73548 /* SRAM_LL_32K_MEMORY_PDA */ "", 73549 /* SRAM_LL_32K_MEM_PWR_CONTROL */ "", 73550 /* SRAM_LL_32K_STATUS1 */ "", 73551 /* SRAM_LL_32K_STATUS2 */ "", 73552 /* SRAM_LL_32K_STATUS3 */ "", 73553 /* SRAM_LL_32K_STATUS4 */ "", 73554 /* SRAM_LL_32K_STATUS5 */ "", 73555 /* SRAM_LL_32K_STATUS6 */ "", 73556 /* SRAM_LL_32K_STATUS7 */ "", 73557 /* SRAM_LL_32K_STATUS8 */ "", 73558 /* SRAM_LL_32K_STATUS9 */ "", 73559 /* SRAM_LL_32K_STATUS10 */ "", 73560 /* SRAM_MEM_ARRAY_CTRL */ "", 73561 /* SRAM_MEM_ARRAY_CTRL2 */ "", 73562 /* SRAM_MEM_BAD_ADDR */ "", 73563 /* SRAM_MEM_BAD_CMD */ "", 73564 /* SRAM_MEM_BAD_DATA */ "", 73565 /* SRAM_MEM_BAD_ECC */ "", 73566 /* SRAM_MEM_CNT */ "", 73567 /* SRAM_MEM_CTRL */ "", 73568 /* SRAM_MEM_OPEN_BASE0 */ "", 73569 /* SRAM_MEM_OPEN_BASE1 */ "", 73570 /* SRAM_MEM_OPEN_BASE2 */ "", 73571 /* SRAM_MEM_OPEN_BASE3 */ "", 73572 /* SRAM_MEM_OPEN_ENA0 */ "", 73573 /* SRAM_MEM_OPEN_ENA1 */ "", 73574 /* SRAM_MEM_OPEN_ENA2 */ "", 73575 /* SRAM_MEM_OPEN_ENA3 */ "", 73576 /* SRAM_MEM_OPEN_END0 */ "", 73577 /* SRAM_MEM_OPEN_END1 */ "", 73578 /* SRAM_MEM_OPEN_END2 */ "", 73579 /* SRAM_MEM_OPEN_END3 */ "", 73580 /* SRAM_MEM_STATUS */ "", 73581 /* SRAM_S0_IDM_ERROR_LOG_ADDR_LSB */ "", 73582 /* SRAM_S0_IDM_ERROR_LOG_COMPLETE */ "", 73583 /* SRAM_S0_IDM_ERROR_LOG_CONTROL */ "", 73584 /* SRAM_S0_IDM_ERROR_LOG_FLAGS */ "", 73585 /* SRAM_S0_IDM_ERROR_LOG_ID */ "", 73586 /* SRAM_S0_IDM_ERROR_LOG_STATUS */ "", 73587 /* SRAM_S0_IDM_INTERRUPT_STATUS */ "", 73588 /* SRAM_S0_IDM_IO_CONTROL_DIRECT */ "", 73589 /* SRAM_S0_IDM_IO_STATUS */ "", 73590 /* SRAM_S0_IDM_RESET_CONTROL */ "", 73591 /* SRAM_S0_IDM_RESET_READ_ID */ "", 73592 /* SRAM_S0_IDM_RESET_STATUS */ "", 73593 /* SRAM_S0_IDM_RESET_WRITE_ID */ "", 73594 /* SRC_COMPRESSION_CAM_BIST_CONFIG */ "", 73595 /* SRC_COMPRESSION_CAM_BIST_CONFIG_2 */ "", 73596 /* SRC_COMPRESSION_CAM_BIST_CONFIG_64 */ "", 73597 /* SRC_COMPRESSION_CAM_BIST_CONFIG_2_PIPE0 */ "", 73598 /* SRC_COMPRESSION_CAM_BIST_CONFIG_2_PIPE1 */ "", 73599 /* SRC_COMPRESSION_CAM_BIST_CONFIG_2_PIPE2 */ "", 73600 /* SRC_COMPRESSION_CAM_BIST_CONFIG_2_PIPE3 */ "", 73601 /* SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE0 */ "", 73602 /* SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE1 */ "", 73603 /* SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE2 */ "", 73604 /* SRC_COMPRESSION_CAM_BIST_CONFIG_64_PIPE3 */ "", 73605 /* SRC_COMPRESSION_CAM_BIST_CONFIG_PIPE0 */ "", 73606 /* SRC_COMPRESSION_CAM_BIST_CONFIG_PIPE1 */ "", 73607 /* SRC_COMPRESSION_CAM_BIST_CONFIG_PIPE2 */ "", 73608 /* SRC_COMPRESSION_CAM_BIST_CONFIG_PIPE3 */ "", 73609 /* SRC_COMPRESSION_CAM_BIST_DBG_DATA */ "", 73610 /* SRC_COMPRESSION_CAM_BIST_DBG_DATA_PIPE0 */ "", 73611 /* SRC_COMPRESSION_CAM_BIST_DBG_DATA_PIPE1 */ "", 73612 /* SRC_COMPRESSION_CAM_BIST_DBG_DATA_PIPE2 */ "", 73613 /* SRC_COMPRESSION_CAM_BIST_DBG_DATA_PIPE3 */ "", 73614 /* SRC_COMPRESSION_CAM_BIST_STATUS */ "", 73615 /* SRC_COMPRESSION_CAM_BIST_STATUS_PIPE0 */ "", 73616 /* SRC_COMPRESSION_CAM_BIST_STATUS_PIPE1 */ "", 73617 /* SRC_COMPRESSION_CAM_BIST_STATUS_PIPE2 */ "", 73618 /* SRC_COMPRESSION_CAM_BIST_STATUS_PIPE3 */ "", 73619 /* SRC_COMPRESSION_CAM_DBGCTRL */ "SRC_COMPRESSION_CAM_CONTROL", 73620 /* SRC_COMPRESSION_CAM_DBGCTRL_PIPE0 */ "SRC_COMPRESSION_CAM_CONTROL_PIPE0", 73621 /* SRC_COMPRESSION_CAM_DBGCTRL_PIPE1 */ "SRC_COMPRESSION_CAM_CONTROL_PIPE1", 73622 /* SRC_COMPRESSION_CAM_DBGCTRL_PIPE2 */ "SRC_COMPRESSION_CAM_CONTROL_PIPE2", 73623 /* SRC_COMPRESSION_CAM_DBGCTRL_PIPE3 */ "SRC_COMPRESSION_CAM_CONTROL_PIPE3", 73624 /* SRC_COMPRESSION_RAM_DBGCTRL */ "SRC_COMPRESSION_RAM_CONTROL", 73625 /* SRC_COMPRESSION_RAM_DBGCTRL_PIPE0 */ "SRC_COMPRESSION_RAM_CONTROL_PIPE0", 73626 /* SRC_COMPRESSION_RAM_DBGCTRL_PIPE1 */ "SRC_COMPRESSION_RAM_CONTROL_PIPE1", 73627 /* SRC_COMPRESSION_RAM_DBGCTRL_PIPE2 */ "SRC_COMPRESSION_RAM_CONTROL_PIPE2", 73628 /* SRC_COMPRESSION_RAM_DBGCTRL_PIPE3 */ "SRC_COMPRESSION_RAM_CONTROL_PIPE3", 73629 /* SRC_INTF */ "", 73630 /* SRC_MODID_BLOCK_PARITY_CONTROL */ "", 73631 /* SRC_MODID_BLOCK_PARITY_STATUS */ "", 73632 /* SRC_MODID_EGRESS_ECC_CONTROL */ "", 73633 /* SRC_MODID_EGRESS_PARITY_CONTROL */ "", 73634 /* SRC_MODID_EGRESS_PARITY_STATUS_INTR */ "", 73635 /* SRC_MODID_EGRESS_PARITY_STATUS_NACK */ "", 73636 /* SRC_MODID_EGRESS_SEL */ "", 73637 /* SRC_MODID_INGRESS_BLOCK_PARITY_CONTROL */ "", 73638 /* SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_INTR */ "", 73639 /* SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_NACK */ "", 73640 /* SRC_MOD_ID */ "", 73641 /* SRC_TRUNK_ECC_CONTROL */ "", 73642 /* SRC_TRUNK_ECC_STATUS_INTR */ "", 73643 /* SRC_TRUNK_ECC_STATUS_NACK */ "", 73644 /* SRC_TRUNK_MAP_PDA_CONTROL */ "", 73645 /* SRC_TRUNK_PARITY_CONTROL */ "", 73646 /* SRC_TRUNK_PARITY_STATUS */ "", 73647 /* SRP_CONTROL_1 */ "", 73648 /* SRP_CONTROL_2 */ "", 73649 /* SR_AGING_TIMER */ "", 73650 /* SR_FLOW_COUNT_POOL0_PARITY_CONTROL */ "", 73651 /* SR_FLOW_COUNT_POOL0_PARITY_STATUS */ "", 73652 /* SR_FLOW_COUNT_POOL1_PARITY_CONTROL */ "", 73653 /* SR_FLOW_COUNT_POOL1_PARITY_STATUS */ "", 73654 /* SR_FLOW_COUNT_POOL2_PARITY_CONTROL */ "", 73655 /* SR_FLOW_COUNT_POOL2_PARITY_STATUS */ "", 73656 /* SR_FLOW_COUNT_POOL3_PARITY_CONTROL */ "", 73657 /* SR_FLOW_COUNT_POOL3_PARITY_STATUS */ "", 73658 /* SR_FLOW_COUNT_POOL4_PARITY_CONTROL */ "", 73659 /* SR_FLOW_COUNT_POOL4_PARITY_STATUS */ "", 73660 /* SR_FLOW_COUNT_POOL5_PARITY_CONTROL */ "", 73661 /* SR_FLOW_COUNT_POOL5_PARITY_STATUS */ "", 73662 /* SR_FLOW_COUNT_POOL6_PARITY_CONTROL */ "", 73663 /* SR_FLOW_COUNT_POOL6_PARITY_STATUS */ "", 73664 /* SR_FLOW_COUNT_POOL7_PARITY_CONTROL */ "", 73665 /* SR_FLOW_COUNT_POOL7_PARITY_STATUS */ "", 73666 /* SR_FLOW_COUNT_THRESHOLD_OWN_RX */ "", 73667 /* SR_FLOW_COUNT_THRESHOLD_RX */ "", 73668 /* SR_FLOW_COUNT_THRESHOLD_RX_DUPLICATES */ "", 73669 /* SR_FLOW_COUNT_THRESHOLD_RX_ERROR */ "", 73670 /* SR_FLOW_COUNT_THRESHOLD_RX_OUTOFORDER */ "", 73671 /* SR_FLOW_COUNT_THRESHOLD_RX_PASSED */ "", 73672 /* SR_FLOW_COUNT_THRESHOLD_RX_TAGGED */ "", 73673 /* SR_FLOW_COUNT_THRESHOLD_RX_TAG_ERROR */ "", 73674 /* SR_FLOW_COUNT_THRESHOLD_RX_WRONG_LAN */ "", 73675 /* SR_FLOW_COUNT_THRESHOLD_SN_WINDOW_CYCLE */ "", 73676 /* SR_FLOW_COUNT_THRESHOLD_TX */ "", 73677 /* SR_FLOW_COUNT_THRESHOLD_TX_TAGGED */ "", 73678 /* SR_FLOW_COUNT_THRESHOLD_UNEXPECTED_FRAME */ "", 73679 /* SR_FLOW_EGR_COUNTER_CONTROL_PARITY_STATUS */ "", 73680 /* SR_FLOW_ING_COUNTER_CONTROL_ECC_CONTROL */ "", 73681 /* SR_FLOW_ING_COUNTER_CONTROL_ECC_STATUS */ "", 73682 /* SR_FLOW_ING_COUNTER_CONTROL_PARITY_STATUS */ "", 73683 /* SR_FLOW_THRESHOLD_MTU_ERROR */ "", 73684 /* SR_FLOW_THRESHOLD_PROXY_MAC_ERROR */ "", 73685 /* SR_FLOW_THRESHOLD_SN_WINDOW_RESET */ "", 73686 /* SR_FLOW_THRESHOLD_STU_ERROR */ "", 73687 /* SR_FLOW_THRESHOLD_TX_MTU_ERROR */ "", 73688 /* SR_FLOW_THRESHOLD_TX_STU_ERROR */ "", 73689 /* SR_LPORT_PROFILE_TABLE_ECC_CONTROL */ "", 73690 /* SR_LPORT_PROFILE_TABLE_ECC_STATUS_INTR */ "", 73691 /* SR_LPORT_PROFILE_TABLE_PARITY_STATUS */ "", 73692 /* SR_MAC_PROXY_PROFILE_ECC_CONTROL */ "", 73693 /* SR_MAC_PROXY_PROFILE_ECC_STATUS_INTR */ "", 73694 /* SR_MAC_PROXY_PROFILE_PARITY_STATUS */ "", 73695 /* SR_OUT_OF_ORDER_CONTROL */ "", 73696 /* SR_PORT_COUNT_OWN_RX_PARITY_CONTROL */ "", 73697 /* SR_PORT_COUNT_OWN_RX_PARITY_STATUS */ "", 73698 /* SR_PORT_COUNT_RX_DUPLICATES_PARITY_CONTROL */ "", 73699 /* SR_PORT_COUNT_RX_DUPLICATES_PARITY_STATUS */ "", 73700 /* SR_PORT_COUNT_RX_ERROR_PARITY_CONTROL */ "", 73701 /* SR_PORT_COUNT_RX_ERROR_PARITY_STATUS */ "", 73702 /* SR_PORT_COUNT_RX_LOST_PARITY_CONTROL */ "", 73703 /* SR_PORT_COUNT_RX_LOST_PARITY_STATUS */ "", 73704 /* SR_PORT_COUNT_RX_OUTOFORDER_PARITY_CONTROL */ "", 73705 /* SR_PORT_COUNT_RX_OUTOFORDER_PARITY_STATUS */ "", 73706 /* SR_PORT_COUNT_RX_PARITY_CONTROL */ "", 73707 /* SR_PORT_COUNT_RX_PARITY_STATUS */ "", 73708 /* SR_PORT_COUNT_RX_PASSED_PARITY_CONTROL */ "", 73709 /* SR_PORT_COUNT_RX_PASSED_PARITY_STATUS */ "", 73710 /* SR_PORT_COUNT_RX_TAGGED_PARITY_CONTROL */ "", 73711 /* SR_PORT_COUNT_RX_TAGGED_PARITY_STATUS */ "", 73712 /* SR_PORT_COUNT_RX_TAG_ERROR_PARITY_CONTROL */ "", 73713 /* SR_PORT_COUNT_RX_TAG_ERROR_PARITY_STATUS */ "", 73714 /* SR_PORT_COUNT_RX_WRONG_LAN_PARITY_CONTROL */ "", 73715 /* SR_PORT_COUNT_RX_WRONG_LAN_PARITY_STATUS */ "", 73716 /* SR_PORT_COUNT_THRESHOLD_OWN_RX */ "", 73717 /* SR_PORT_COUNT_THRESHOLD_PROXY_MAC_ERROR */ "", 73718 /* SR_PORT_COUNT_THRESHOLD_RX */ "", 73719 /* SR_PORT_COUNT_THRESHOLD_RX_DUPLICATES */ "", 73720 /* SR_PORT_COUNT_THRESHOLD_RX_ERROR */ "", 73721 /* SR_PORT_COUNT_THRESHOLD_RX_OUTOFORDER */ "", 73722 /* SR_PORT_COUNT_THRESHOLD_RX_PASSED */ "", 73723 /* SR_PORT_COUNT_THRESHOLD_RX_TAGGED */ "", 73724 /* SR_PORT_COUNT_THRESHOLD_RX_TAG_ERROR */ "", 73725 /* SR_PORT_COUNT_THRESHOLD_RX_WRONG_LAN */ "", 73726 /* SR_PORT_COUNT_THRESHOLD_TX */ "", 73727 /* SR_PORT_COUNT_THRESHOLD_TX_TAGGED */ "", 73728 /* SR_PORT_COUNT_THRESHOLD_UNEXPECTED_FRAME */ "", 73729 /* SR_PORT_COUNT_TX_PARITY_STATUS */ "", 73730 /* SR_PORT_COUNT_TX_TAGGED_PARITY_STATUS */ "", 73731 /* SR_PORT_COUNT_UNEXPECTED_FRAME_PARITY_CONTROL */ "", 73732 /* SR_PORT_COUNT_UNEXPECTED_FRAME_PARITY_STATUS */ "", 73733 /* SR_PORT_MTU_ERROR_PARITY_CONTROL */ "", 73734 /* SR_PORT_MTU_ERROR_PARITY_STATUS */ "", 73735 /* SR_PORT_PROXY_MAC_ERROR_PARITY_CONTROL */ "", 73736 /* SR_PORT_PROXY_MAC_ERROR_PARITY_STATUS */ "", 73737 /* SR_PORT_SN_WINDOW_RESET_PARITY_CONTROL */ "", 73738 /* SR_PORT_SN_WINDOW_RESET_PARITY_STATUS */ "", 73739 /* SR_PORT_STU_ERROR_PARITY_CONTROL */ "", 73740 /* SR_PORT_STU_ERROR_PARITY_STATUS */ "", 73741 /* SR_PORT_TABLE_ECC_CONTROL */ "", 73742 /* SR_PORT_TABLE_ECC_STATUS_INTR */ "", 73743 /* SR_PORT_TABLE_PARITY_STATUS_INTR */ "", 73744 /* SR_PORT_TABLE_RAM_CONTROL */ "", 73745 /* SR_PORT_THRESHOLD_MTU_ERROR */ "", 73746 /* SR_PORT_THRESHOLD_SN_WINDOW_RESET */ "", 73747 /* SR_PORT_THRESHOLD_STU_ERROR */ "", 73748 /* SR_PORT_THRESHOLD_TX_MTU_ERROR */ "", 73749 /* SR_PORT_THRESHOLD_TX_STU_ERROR */ "", 73750 /* SR_PORT_TX_MTU_ERROR_PARITY_STATUS */ "", 73751 /* SR_PORT_TX_STU_ERROR_PARITY_STATUS */ "", 73752 /* SR_RX_FLOW_ID_CONTROL */ "", 73753 /* SR_RX_FLOW_ID_POOL_ECC_CONTROL */ "", 73754 /* SR_RX_FLOW_ID_POOL_ECC_STATUS_INTR */ "", 73755 /* SR_RX_FLOW_ID_POOL_PARITY_STATUS_INTR */ "", 73756 /* SR_RX_FLOW_ID_POOL_RAM_CONTROL */ "", 73757 /* SR_RX_LINK_LIST_STATUS */ "", 73758 /* SR_TX_FLOW_ID_CONTROL */ "", 73759 /* SR_TX_FLOW_ID_POOL_ECC_CONTROL */ "", 73760 /* SR_TX_FLOW_ID_POOL_ECC_STATUS_INTR */ "", 73761 /* SR_TX_FLOW_ID_POOL_PARITY_STATUS_INTR */ "", 73762 /* SR_TX_FLOW_ID_POOL_RAM_CONTROL */ "", 73763 /* SR_TX_LINK_LIST_STATUS */ "", 73764 /* STAGE0_BANK_COLUMN_DISABLE */ "", 73765 /* STAGE0_BANK_SIZE */ "", 73766 /* STAGE0_HASH_OFFSET */ "", 73767 /* STAGE0_MEMORY_CONTROL_0 */ "", 73768 /* STAGE0_MEMORY_CONTROL_1 */ "", 73769 /* STAGE0_MEMORY_CONTROL_2 */ "", 73770 /* STAGE0_MEMORY_CONTROL_3 */ "", 73771 /* STAGE0_MEMORY_CONTROL_4 */ "", 73772 /* STAGE0_MEMORY_CONTROL_5 */ "", 73773 /* STAGE0_MEMORY_CONTROL_6 */ "", 73774 /* STAGE0_MEMORY_CONTROL_7 */ "", 73775 /* STAGE0_MEMORY_CONTROL_8 */ "", 73776 /* STAGE0_MEMORY_CONTROL_9 */ "", 73777 /* STAGE0_MEMORY_CONTROL_10 */ "", 73778 /* STAGE0_MEMORY_CONTROL_11 */ "", 73779 /* STAGE0_MEMORY_CONTROL_12 */ "", 73780 /* STAGE0_MEMORY_CONTROL_13 */ "", 73781 /* STAGE0_MEMORY_CONTROL_14 */ "", 73782 /* STAGE0_MEMORY_CONTROL_15 */ "", 73783 /* STAGE0_MEMORY_CONTROL_16 */ "", 73784 /* STAGE0_MEMORY_CONTROL_17 */ "", 73785 /* STAGE0_MEMORY_CONTROL_18 */ "", 73786 /* STAGE0_MEMORY_CONTROL_19 */ "", 73787 /* STAGE0_MEMORY_CONTROL_20 */ "", 73788 /* STAGE0_MEMORY_CONTROL_21 */ "", 73789 /* STAGE0_MEMORY_CONTROL_22 */ "", 73790 /* STAGE0_MEMORY_CONTROL_23 */ "", 73791 /* STAGE0_MEMORY_CONTROL_24 */ "", 73792 /* STAGE0_MEMORY_CONTROL_25 */ "", 73793 /* STAGE0_MEMORY_CONTROL_26 */ "", 73794 /* STAGE0_MEMORY_CONTROL_27 */ "", 73795 /* STAGE1_BANK_COLUMN_DISABLE */ "", 73796 /* STAGE1_BANK_SIZE */ "", 73797 /* STAGE1_HASH_OFFSET */ "", 73798 /* STAGE1_MEMORY_CONTROL_0 */ "", 73799 /* STAGE1_MEMORY_CONTROL_1 */ "", 73800 /* STAGE1_MEMORY_CONTROL_2 */ "", 73801 /* STAGE1_MEMORY_CONTROL_3 */ "", 73802 /* STAGE1_MEMORY_CONTROL_4 */ "", 73803 /* STAGE1_MEMORY_CONTROL_5 */ "", 73804 /* STAGE1_MEMORY_CONTROL_6 */ "", 73805 /* STAGE1_MEMORY_CONTROL_7 */ "", 73806 /* STAGE1_MEMORY_CONTROL_8 */ "", 73807 /* STAGE1_MEMORY_CONTROL_9 */ "", 73808 /* STAGE1_MEMORY_CONTROL_10 */ "", 73809 /* STAGE1_MEMORY_CONTROL_11 */ "", 73810 /* STAGE1_MEMORY_CONTROL_12 */ "", 73811 /* STAGE1_MEMORY_CONTROL_13 */ "", 73812 /* STAGE1_MEMORY_CONTROL_14 */ "", 73813 /* STAGE1_MEMORY_CONTROL_15 */ "", 73814 /* STAGE1_MEMORY_CONTROL_16 */ "", 73815 /* STAGE1_MEMORY_CONTROL_17 */ "", 73816 /* STAGE1_MEMORY_CONTROL_18 */ "", 73817 /* STAGE1_MEMORY_CONTROL_19 */ "", 73818 /* STAGE1_MEMORY_CONTROL_20 */ "", 73819 /* STAGE1_MEMORY_CONTROL_21 */ "", 73820 /* STAGE1_MEMORY_CONTROL_22 */ "", 73821 /* STAGE1_MEMORY_CONTROL_23 */ "", 73822 /* STAGE1_MEMORY_CONTROL_24 */ "", 73823 /* STAGE1_MEMORY_CONTROL_25 */ "", 73824 /* STAGE1_MEMORY_CONTROL_26 */ "", 73825 /* STAGE1_MEMORY_CONTROL_27 */ "", 73826 /* STAGE2_BANK_COLUMN_DISABLE */ "", 73827 /* STAGE2_BANK_SIZE */ "", 73828 /* STAGE2_HASH_OFFSET */ "", 73829 /* STAGE2_MEMORY_CONTROL_0 */ "", 73830 /* STAGE2_MEMORY_CONTROL_1 */ "", 73831 /* STAGE2_MEMORY_CONTROL_2 */ "", 73832 /* STAGE2_MEMORY_CONTROL_3 */ "", 73833 /* STAGE2_MEMORY_CONTROL_4 */ "", 73834 /* STAGE2_MEMORY_CONTROL_5 */ "", 73835 /* STAGE2_MEMORY_CONTROL_6 */ "", 73836 /* STAGE2_MEMORY_CONTROL_7 */ "", 73837 /* STAGE2_MEMORY_CONTROL_8 */ "", 73838 /* STAGE2_MEMORY_CONTROL_9 */ "", 73839 /* STAGE2_MEMORY_CONTROL_10 */ "", 73840 /* STAGE2_MEMORY_CONTROL_11 */ "", 73841 /* STAGE2_MEMORY_CONTROL_12 */ "", 73842 /* STAGE2_MEMORY_CONTROL_13 */ "", 73843 /* STAGE2_MEMORY_CONTROL_14 */ "", 73844 /* STAGE2_MEMORY_CONTROL_15 */ "", 73845 /* STAGE2_MEMORY_CONTROL_16 */ "", 73846 /* STAGE2_MEMORY_CONTROL_17 */ "", 73847 /* STAGE2_MEMORY_CONTROL_18 */ "", 73848 /* STAGE2_MEMORY_CONTROL_19 */ "", 73849 /* STAGE2_MEMORY_CONTROL_20 */ "", 73850 /* STAGE2_MEMORY_CONTROL_21 */ "", 73851 /* STAGE2_MEMORY_CONTROL_22 */ "", 73852 /* STAGE2_MEMORY_CONTROL_23 */ "", 73853 /* STAGE2_MEMORY_CONTROL_24 */ "", 73854 /* STAGE2_MEMORY_CONTROL_25 */ "", 73855 /* STAGE2_MEMORY_CONTROL_26 */ "", 73856 /* STAGE2_MEMORY_CONTROL_27 */ "", 73857 /* STAGE3_BANK_COLUMN_DISABLE */ "", 73858 /* STAGE3_BANK_SIZE */ "", 73859 /* STAGE3_HASH_OFFSET */ "", 73860 /* STAGE3_MEMORY_CONTROL_0 */ "", 73861 /* STAGE3_MEMORY_CONTROL_1 */ "", 73862 /* STAGE3_MEMORY_CONTROL_2 */ "", 73863 /* STAGE3_MEMORY_CONTROL_3 */ "", 73864 /* STAGE3_MEMORY_CONTROL_4 */ "", 73865 /* STAGE3_MEMORY_CONTROL_5 */ "", 73866 /* STAGE3_MEMORY_CONTROL_6 */ "", 73867 /* STAGE3_MEMORY_CONTROL_7 */ "", 73868 /* STAGE3_MEMORY_CONTROL_8 */ "", 73869 /* STAGE3_MEMORY_CONTROL_9 */ "", 73870 /* STAGE3_MEMORY_CONTROL_10 */ "", 73871 /* STAGE3_MEMORY_CONTROL_11 */ "", 73872 /* STAGE3_MEMORY_CONTROL_12 */ "", 73873 /* STAGE3_MEMORY_CONTROL_13 */ "", 73874 /* STAGE3_MEMORY_CONTROL_14 */ "", 73875 /* STAGE3_MEMORY_CONTROL_15 */ "", 73876 /* STAGE3_MEMORY_CONTROL_16 */ "", 73877 /* STAGE3_MEMORY_CONTROL_17 */ "", 73878 /* STAGE3_MEMORY_CONTROL_18 */ "", 73879 /* STAGE3_MEMORY_CONTROL_19 */ "", 73880 /* STAGE3_MEMORY_CONTROL_20 */ "", 73881 /* STAGE3_MEMORY_CONTROL_21 */ "", 73882 /* STAGE3_MEMORY_CONTROL_22 */ "", 73883 /* STAGE3_MEMORY_CONTROL_23 */ "", 73884 /* STAGE3_MEMORY_CONTROL_24 */ "", 73885 /* STAGE3_MEMORY_CONTROL_25 */ "", 73886 /* STAGE3_MEMORY_CONTROL_26 */ "", 73887 /* STAGE3_MEMORY_CONTROL_27 */ "", 73888 /* STAGE_INTR */ "", 73889 /* START_BY_START_ERROR */ "", 73890 /* START_BY_START_ERROR0_64 */ "START_BY_START_ERROR0", 73891 /* START_BY_START_ERROR1_64 */ "START_BY_START_ERROR1", 73892 /* START_BY_START_ERROR_0 */ "", 73893 /* START_BY_START_ERROR_1 */ "", 73894 /* START_BY_START_ERROR_64 */ "START_BY_START_ERROR", 73895 /* START_BY_START_ERR_STAT */ "", 73896 /* STATS_INTF_CONFIG_ID */ "", 73897 /* STATS_INTF_REPORT_EN */ "", 73898 /* STORM_CONTROL_METER_CONFIG */ "", 73899 /* STORM_CONTROL_METER_CONFIG_PARITY_CONTROL */ "", 73900 /* STORM_CONTROL_METER_MAPPING */ "", 73901 /* STORM_CONTROL_METER_RAM_CONTROL */ "", 73902 /* STORM_CONTROL_METER_RAM_CONTROL_PIPE0 */ "", 73903 /* STORM_CONTROL_METER_RAM_CONTROL_PIPE1 */ "", 73904 /* STORM_CONTROL_METER_RAM_CONTROL_PIPE2 */ "", 73905 /* STORM_CONTROL_METER_RAM_CONTROL_PIPE3 */ "", 73906 /* STSOSPER1_SI_0 */ "", 73907 /* STSOSPER1_SI_1 */ "", 73908 /* STSOSPER2_SI_0 */ "", 73909 /* STSOSPER2_SI_1 */ "", 73910 /* STU_PRIORITY */ "", 73911 /* ST_TRANS_TBL_ECC_ERR1 */ "", 73912 /* ST_TRANS_TBL_ECC_ERR2 */ "", 73913 /* SUBPORT_TAG_SGPP_MAP_CAM_BIST_CONFIG */ "", 73914 /* SUBPORT_TAG_SGPP_MAP_CAM_BIST_DBGCTRL */ "SUBPORT_TAG_SGPP_MAP_CAM_BIST_CONTROL", 73915 /* SUBPORT_TAG_SGPP_MAP_CAM_BIST_DBG_DATA */ "", 73916 /* SUBPORT_TAG_SGPP_MAP_CAM_BIST_STATUS */ "", 73917 /* SUBPORT_TAG_SGPP_MAP_CAM_DBGCTRL */ "SUBPORT_TAG_SGPP_MAP_CAM_CONTROL", 73918 /* SUBPORT_TAG_TO_PP_PORT_MAP_CAM_BIST_CONFIG */ "", 73919 /* SUBPORT_TAG_TO_PP_PORT_MAP_CAM_BIST_DBG_DATA */ "", 73920 /* SUBPORT_TAG_TO_PP_PORT_MAP_CAM_BIST_STATUS */ "", 73921 /* SUBPORT_TAG_TO_PP_PORT_MAP_CAM_DBGCTRL */ "SUBPORT_TAG_TO_PP_PORT_MAP_CAM_CONTROL", 73922 /* SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY_PARITY_CONTROL */ "", 73923 /* SUBPORT_TAG_TO_PP_PORT_MAP_DATA_PARITY_CONTROL */ "", 73924 /* SUBPORT_TAG_TO_PP_PORT_MAP_DATA_PARITY_STATUS_INTR */ "", 73925 /* SUBPORT_TAG_TO_PP_PORT_MAP_DATA_PARITY_STATUS_NACK */ "", 73926 /* SUBPORT_TAG_TO_PP_PORT_MAP_ONLY_BIST_CONFIG */ "", 73927 /* SUBPORT_TAG_TO_PP_PORT_MAP_ONLY_BIST_DBG_DATA */ "", 73928 /* SUBPORT_TAG_TO_PP_PORT_MAP_ONLY_BIST_STATUS */ "", 73929 /* SUBPORT_TAG_TO_PP_PORT_MAP_TM_CONTROL */ "", 73930 /* SUBPORT_TAG_TPID */ "", 73931 /* SUBPORT_TAG_TPID_0 */ "", 73932 /* SUBPORT_TAG_TPID_1 */ "", 73933 /* SUBPORT_TAG_TPID_2 */ "", 73934 /* SUBPORT_TAG_TPID_3 */ "", 73935 /* SUSPEND_WAMU_PQ */ "", 73936 /* SVC_METER_OFFSET_TCAM_BIST_CONFIG */ "", 73937 /* SVC_METER_OFFSET_TCAM_BIST_DBG_DATA */ "", 73938 /* SVC_METER_OFFSET_TCAM_BIST_STATUS */ "", 73939 /* SVC_METER_OFFSET_TCAM_DBGCTRL */ "SVC_METER_OFFSET_TCAM_CONTROL", 73940 /* SVM_TSN_CONTROL */ "", 73941 /* SW1_RAM_DBGCTRL */ "SW1_RAM_CONTROL", 73942 /* SW1_RAM_DBGCTRL3 */ "SW1_RAM_CONTROL3", 73943 /* SW1_RAM_DBGCTRL2_64 */ "SW1_RAM_CONTROL2_64", 73944 /* SW1_RAM_DBGCTRL2_64_PIPE0 */ "SW1_RAM_CONTROL2_64_PIPE0", 73945 /* SW1_RAM_DBGCTRL2_64_PIPE1 */ "SW1_RAM_CONTROL2_64_PIPE1", 73946 /* SW1_RAM_DBGCTRL2_64_PIPE2 */ "SW1_RAM_CONTROL2_64_PIPE2", 73947 /* SW1_RAM_DBGCTRL2_64_PIPE3 */ "SW1_RAM_CONTROL2_64_PIPE3", 73948 /* SW1_RAM_DBGCTRL3_64 */ "SW1_RAM_CONTROL3_64", 73949 /* SW1_RAM_DBGCTRL_2 */ "SW1_RAM_CONTROL_2", 73950 /* SW1_RAM_DBGCTRL_3 */ "SW1_RAM_CONTROL_3", 73951 /* SW1_RAM_DBGCTRL_4 */ "SW1_RAM_CONTROL_4", 73952 /* SW1_RAM_DBGCTRL_5 */ "SW1_RAM_CONTROL_5", 73953 /* SW1_RAM_DBGCTRL_64 */ "SW1_RAM_CONTROL_64", 73954 /* SW1_RAM_DBGCTRL_64_PIPE0 */ "SW1_RAM_CONTROL_64_PIPE0", 73955 /* SW1_RAM_DBGCTRL_64_PIPE1 */ "SW1_RAM_CONTROL_64_PIPE1", 73956 /* SW1_RAM_DBGCTRL_64_PIPE2 */ "SW1_RAM_CONTROL_64_PIPE2", 73957 /* SW1_RAM_DBGCTRL_64_PIPE3 */ "SW1_RAM_CONTROL_64_PIPE3", 73958 /* SW2_EOP_BUFFER_A_PARITY_CONTROL */ "", 73959 /* SW2_EOP_BUFFER_A_PARITY_STATUS_INTR */ "", 73960 /* SW2_EOP_BUFFER_B_PARITY_CONTROL */ "", 73961 /* SW2_EOP_BUFFER_B_PARITY_STATUS_INTR */ "", 73962 /* SW2_EOP_BUFFER_C_PARITY_CONTROL */ "", 73963 /* SW2_EOP_BUFFER_C_PARITY_STATUS_INTR */ "", 73964 /* SW2_FP_DST_ACTION_CONTROL */ "", 73965 /* SW2_HW_CONTROL */ "", 73966 /* SW2_IFP_DST_ACTION_CONTROL */ "", 73967 /* SW2_OAM_LM_COUNTERS_PDA_CONTROL0 */ "", 73968 /* SW2_OAM_LM_COUNTERS_PDA_CONTROL1 */ "", 73969 /* SW2_RAM_CONTROL_0 */ "", 73970 /* SW2_RAM_CONTROL_1 */ "", 73971 /* SW2_RAM_CONTROL_2 */ "", 73972 /* SW2_RAM_CONTROL_3 */ "", 73973 /* SW2_RAM_CONTROL_4 */ "", 73974 /* SW2_RAM_CONTROL_5 */ "", 73975 /* SW2_RAM_CONTROL_6 */ "", 73976 /* SW2_RAM_CONTROL_7 */ "", 73977 /* SW2_RAM_CONTROL_8 */ "", 73978 /* SW2_RAM_CONTROL_9 */ "", 73979 /* SW2_RAM_CONTROL_10 */ "", 73980 /* SW2_RAM_CONTROL_11 */ "", 73981 /* SW2_RAM_CONTROL_12 */ "", 73982 /* SW2_RAM_CONTROL_13 */ "", 73983 /* SW2_RAM_CONTROL_1_64 */ "SW2_RAM_CONTROL_1", 73984 /* SW2_RAM_CONTROL_1_64_PIPE0 */ "SW2_RAM_CONTROL_1_PIPE0", 73985 /* SW2_RAM_CONTROL_1_64_PIPE1 */ "SW2_RAM_CONTROL_1_PIPE1", 73986 /* SW2_RAM_CONTROL_1_64_PIPE2 */ "SW2_RAM_CONTROL_1_PIPE2", 73987 /* SW2_RAM_CONTROL_1_64_PIPE3 */ "SW2_RAM_CONTROL_1_PIPE3", 73988 /* SW2_RAM_CONTROL_2_64 */ "SW2_RAM_CONTROL_2", 73989 /* SW2_RAM_CONTROL_2_64_PIPE0 */ "SW2_RAM_CONTROL_2_PIPE0", 73990 /* SW2_RAM_CONTROL_2_64_PIPE1 */ "SW2_RAM_CONTROL_2_PIPE1", 73991 /* SW2_RAM_CONTROL_2_64_PIPE2 */ "SW2_RAM_CONTROL_2_PIPE2", 73992 /* SW2_RAM_CONTROL_2_64_PIPE3 */ "SW2_RAM_CONTROL_2_PIPE3", 73993 /* SW2_RAM_CONTROL_3_64 */ "SW2_RAM_CONTROL_3", 73994 /* SW2_RAM_CONTROL_3_64_PIPE0 */ "SW2_RAM_CONTROL_3_PIPE0", 73995 /* SW2_RAM_CONTROL_3_64_PIPE1 */ "SW2_RAM_CONTROL_3_PIPE1", 73996 /* SW2_RAM_CONTROL_3_64_PIPE2 */ "SW2_RAM_CONTROL_3_PIPE2", 73997 /* SW2_RAM_CONTROL_3_64_PIPE3 */ "SW2_RAM_CONTROL_3_PIPE3", 73998 /* SW2_RAM_CONTROL_4_64 */ "SW2_RAM_CONTROL_4", 73999 /* SW2_RAM_CONTROL_4_64_PIPE0 */ "SW2_RAM_CONTROL_4_PIPE0", 74000 /* SW2_RAM_CONTROL_4_64_PIPE1 */ "SW2_RAM_CONTROL_4_PIPE1", 74001 /* SW2_RAM_CONTROL_4_64_PIPE2 */ "SW2_RAM_CONTROL_4_PIPE2", 74002 /* SW2_RAM_CONTROL_4_64_PIPE3 */ "SW2_RAM_CONTROL_4_PIPE3", 74003 /* SW2_RAM_CONTROL_5_64 */ "SW2_RAM_CONTROL_5", 74004 /* SW2_RAM_CONTROL_5_64_PIPE0 */ "SW2_RAM_CONTROL_5_PIPE0", 74005 /* SW2_RAM_CONTROL_5_64_PIPE1 */ "SW2_RAM_CONTROL_5_PIPE1", 74006 /* SW2_RAM_CONTROL_5_64_PIPE2 */ "SW2_RAM_CONTROL_5_PIPE2", 74007 /* SW2_RAM_CONTROL_5_64_PIPE3 */ "SW2_RAM_CONTROL_5_PIPE3", 74008 /* SW2_RAM_CONTROL_6_64 */ "SW2_RAM_CONTROL_6", 74009 /* SW2_RAM_CONTROL_6_64_PIPE0 */ "SW2_RAM_CONTROL_6_PIPE0", 74010 /* SW2_RAM_CONTROL_6_64_PIPE1 */ "SW2_RAM_CONTROL_6_PIPE1", 74011 /* SW2_RAM_CONTROL_6_64_PIPE2 */ "SW2_RAM_CONTROL_6_PIPE2", 74012 /* SW2_RAM_CONTROL_6_64_PIPE3 */ "SW2_RAM_CONTROL_6_PIPE3", 74013 /* SW2_RAM_CONTROL_7_64 */ "SW2_RAM_CONTROL_7", 74014 /* SW2_RAM_CONTROL_7_64_PIPE0 */ "SW2_RAM_CONTROL_7_PIPE0", 74015 /* SW2_RAM_CONTROL_7_64_PIPE1 */ "SW2_RAM_CONTROL_7_PIPE1", 74016 /* SW2_RAM_CONTROL_7_64_PIPE2 */ "SW2_RAM_CONTROL_7_PIPE2", 74017 /* SW2_RAM_CONTROL_7_64_PIPE3 */ "SW2_RAM_CONTROL_7_PIPE3", 74018 /* SW2_RAM_CONTROL_8_64 */ "SW2_RAM_CONTROL_8", 74019 /* SW2_RAM_CONTROL_8_64_PIPE0 */ "SW2_RAM_CONTROL_8_PIPE0", 74020 /* SW2_RAM_CONTROL_8_64_PIPE1 */ "SW2_RAM_CONTROL_8_PIPE1", 74021 /* SW2_RAM_CONTROL_8_64_PIPE2 */ "SW2_RAM_CONTROL_8_PIPE2", 74022 /* SW2_RAM_CONTROL_8_64_PIPE3 */ "SW2_RAM_CONTROL_8_PIPE3", 74023 /* SW3_RAM_CONTROL_2 */ "", 74024 /* SW3_RAM_CONTROL_3 */ "", 74025 /* SW3_RAM_CONTROL_4 */ "", 74026 /* SW3_RAM_CONTROL_5 */ "", 74027 /* SW3_RAM_CONTROL_6 */ "", 74028 /* SW3_RAM_CONTROL_7 */ "", 74029 /* SW3_RAM_CONTROL_2_PIPE0 */ "", 74030 /* SW3_RAM_CONTROL_2_PIPE1 */ "", 74031 /* SW3_RAM_CONTROL_2_PIPE2 */ "", 74032 /* SW3_RAM_CONTROL_2_PIPE3 */ "", 74033 /* SW3_RAM_CONTROL_3_PIPE0 */ "", 74034 /* SW3_RAM_CONTROL_3_PIPE1 */ "", 74035 /* SW3_RAM_CONTROL_3_PIPE2 */ "", 74036 /* SW3_RAM_CONTROL_3_PIPE3 */ "", 74037 /* SW3_RAM_CONTROL_4_PIPE0 */ "", 74038 /* SW3_RAM_CONTROL_4_PIPE1 */ "", 74039 /* SW3_RAM_CONTROL_4_PIPE2 */ "", 74040 /* SW3_RAM_CONTROL_4_PIPE3 */ "", 74041 /* SW3_RAM_CONTROL_5_PIPE0 */ "", 74042 /* SW3_RAM_CONTROL_5_PIPE1 */ "", 74043 /* SW3_RAM_CONTROL_5_PIPE2 */ "", 74044 /* SW3_RAM_CONTROL_5_PIPE3 */ "", 74045 /* SW3_RAM_CONTROL_6_PIPE0 */ "", 74046 /* SW3_RAM_CONTROL_6_PIPE1 */ "", 74047 /* SW3_RAM_CONTROL_6_PIPE2 */ "", 74048 /* SW3_RAM_CONTROL_6_PIPE3 */ "", 74049 /* SW3_RAM_CONTROL_7_PIPE0 */ "", 74050 /* SW3_RAM_CONTROL_7_PIPE1 */ "", 74051 /* SW3_RAM_CONTROL_7_PIPE2 */ "", 74052 /* SW3_RAM_CONTROL_7_PIPE3 */ "", 74053 /* SW4_RAM_CONTROL */ "", 74054 /* SW4_RAM_CONTROL_PIPE0 */ "", 74055 /* SW4_RAM_CONTROL_PIPE1 */ "", 74056 /* SW4_RAM_CONTROL_PIPE2 */ "", 74057 /* SW4_RAM_CONTROL_PIPE3 */ "", 74058 /* SW4_SER_CONTROL */ "", 74059 /* SW_HW_CONTROL */ "", 74060 /* SW_IFP_DST_ACTION_CONTROL */ "", 74061 /* SYNCE_X4_FRACTIONAL_DIV */ "", 74062 /* SYNCE_X4_INTEGER_DIV */ "", 74063 /* SYSBRG1_SI_0 */ "", 74064 /* SYSBRG1_SI_1 */ "", 74065 /* SYSBRG2_SI_0 */ "", 74066 /* SYSBRG2_SI_1 */ "", 74067 /* SYSCFG_MODBASE_RAM_CONTROL */ "", 74068 /* SYSCLKCFG1_SI_0 */ "", 74069 /* SYSCLKCFG1_SI_1 */ "", 74070 /* SYSCLKCFG2_SI_0 */ "", 74071 /* SYSCLKCFG2_SI_1 */ "", 74072 /* SYSCLTS1_SI_0 */ "", 74073 /* SYSCLTS1_SI_1 */ "", 74074 /* SYSCLTS2_SI_0 */ "", 74075 /* SYSCLTS2_SI_1 */ "", 74076 /* SYSTEM_CONFIG_MODVIEW_PARITY_CONTROL */ "", 74077 /* SYSTEM_CONFIG_MODVIEW_PARITY_STATUS_INTR */ "", 74078 /* SYSTEM_CONFIG_MODVIEW_PARITY_STATUS_NACK */ "", 74079 /* SYSTEM_CONFIG_PARITY_CONTROL */ "", 74080 /* SYSTEM_CONFIG_PARITY_STATUS_INTR */ "", 74081 /* SYSTEM_CONFIG_PARITY_STATUS_NACK */ "", 74082 /* SYSTEM_CONFIG_TABLE_MODBASE_PARITY_CONTROL */ "", 74083 /* SYSTEM_CONFIG_TABLE_MODBASE_PARITY_STATUS */ "", 74084 /* SYSTEM_CONFIG_TABLE_PARITY_CONTROL */ "", 74085 /* SYSTEM_CONFIG_TABLE_PARITY_STATUS */ "", 74086 /* SYSTSO1_SI_0 */ "", 74087 /* SYSTSO1_SI_1 */ "", 74088 /* SYSTSO2_SI_0 */ "", 74089 /* SYSTSO2_SI_1 */ "", 74090 /* SYSTSOFPH_SI_0 */ "", 74091 /* SYSTSOFPH_SI_1 */ "", 74092 /* SYS_CONTROL */ "", 74093 /* SYS_MAC_ACTION */ "SYS_MAC_LIMIT_CONTROL_3", 74094 /* SYS_MAC_COUNT */ "SYS_MAC_LIMIT_CONTROL_1", 74095 /* SYS_MAC_LIMIT */ "SYS_MAC_LIMIT_CONTROL_2", 74096 /* SYS_MAC_LIMIT_CONTROL */ "MAC_LIMIT_CONTROL", 74097 /* T64 */ "MAC_GTx64", 74098 /* T127 */ "MAC_GTx127", 74099 /* T255 */ "MAC_GTx255", 74100 /* T511 */ "MAC_GTx511", 74101 /* T1023 */ "MAC_GTx1023", 74102 /* T1518 */ "MAC_GTx1518", 74103 /* T2047 */ "MAC_GTx2047", 74104 /* T4095 */ "MAC_GTx4095", 74105 /* T9216 */ "MAC_GTx9216", 74106 /* T16383 */ "MAC_GTx16383", 74107 /* TABLE0_BANK_CONFIG */ "", 74108 /* TABLE1_BANK_CONFIG */ "", 74109 /* TABLE2_BANK_CONFIG */ "", 74110 /* TABLE3_BANK_CONFIG */ "", 74111 /* TABLE4_BANK_CONFIG */ "", 74112 /* TAF_ASYNC_FIFO_OVERFLOW_0 */ "", 74113 /* TAF_ASYNC_FIFO_OVERFLOW_1 */ "", 74114 /* TAF_ASYNC_FIFO_OVERFLOW_2 */ "", 74115 /* TAF_ASYNC_FIFO_OVERFLOW_3 */ "", 74116 /* TAF_ASYNC_FIFO_OVERFLOW_CLR_0 */ "", 74117 /* TAF_ASYNC_FIFO_OVERFLOW_CLR_1 */ "", 74118 /* TAF_ASYNC_FIFO_OVERFLOW_CLR_2 */ "", 74119 /* TAF_ASYNC_FIFO_OVERFLOW_CLR_3 */ "", 74120 /* TAF_BASE_TIME_FRAC_0 */ "", 74121 /* TAF_BASE_TIME_FRAC_1 */ "", 74122 /* TAF_BASE_TIME_SEC_0 */ "", 74123 /* TAF_BASE_TIME_SEC_1 */ "", 74124 /* TAF_CONFIG_0 */ "", 74125 /* TAF_CONFIG_1 */ "", 74126 /* TAF_CONFIG_2 */ "", 74127 /* TAF_CTL_TBL_PTR_ERR_0 */ "", 74128 /* TAF_CTL_TBL_PTR_ERR_1 */ "", 74129 /* TAF_CTL_TBL_PTR_ERR_2 */ "", 74130 /* TAF_CTL_TBL_PTR_ERR_3 */ "", 74131 /* TAF_CTL_TBL_PTR_ERR_CLR_0 */ "", 74132 /* TAF_CTL_TBL_PTR_ERR_CLR_1 */ "", 74133 /* TAF_CTL_TBL_PTR_ERR_CLR_2 */ "", 74134 /* TAF_CTL_TBL_PTR_ERR_CLR_3 */ "", 74135 /* TAF_CYCLE_TIME_0 */ "", 74136 /* TAF_CYCLE_TIME_1 */ "", 74137 /* TAF_CYCLE_TIME_EXTENSION_0 */ "", 74138 /* TAF_CYCLE_TIME_EXTENSION_1 */ "", 74139 /* TAF_ERR_CNT */ "", 74140 /* TAF_GATE_CTRL_PERIOD */ "", 74141 /* TAF_GATE_ID_LOOKUP_ECC_CONTROL */ "", 74142 /* TAF_GATE_ID_LOOKUP_ECC_STATUS_INTR */ "", 74143 /* TAF_GATE_ID_LOOKUP_PARITY_STATUS */ "", 74144 /* TAF_GSG_STATUS */ "", 74145 /* TAF_MEMFAILINTMASK */ "", 74146 /* TAF_MEMFAILINTSTATUS */ "", 74147 /* TAF_MEMFAILINT_CLR */ "", 74148 /* TAF_MEM_CORRUPT_CTL_BITMAP */ "", 74149 /* TAF_MEM_TM */ "", 74150 /* TAF_MISCCONFIG */ "", 74151 /* TAF_PARITY_ERR_CLR_0 */ "", 74152 /* TAF_PARITY_ERR_CLR_1 */ "", 74153 /* TAF_PARITY_ERR_CLR_2 */ "", 74154 /* TAF_PARITY_ERR_CLR_3 */ "", 74155 /* TAF_PARITY_ERR_STATUS */ "", 74156 /* TAF_PARITY_ERR_VLD_0 */ "", 74157 /* TAF_PARITY_ERR_VLD_1 */ "", 74158 /* TAF_PARITY_ERR_VLD_2 */ "", 74159 /* TAF_PARITY_ERR_VLD_3 */ "", 74160 /* TAF_PER_PORT_PACKET_CONTEXT */ "", 74161 /* TAF_PTP_LOCK */ "", 74162 /* TAF_SET_BASE_TIME_ERROR_0 */ "", 74163 /* TAF_SET_BASE_TIME_ERROR_1 */ "", 74164 /* TAF_SET_BASE_TIME_ERROR_2 */ "", 74165 /* TAF_SET_BASE_TIME_ERROR_3 */ "", 74166 /* TAF_SET_BASE_TIME_ERROR_CLR_0 */ "", 74167 /* TAF_SET_BASE_TIME_ERROR_CLR_1 */ "", 74168 /* TAF_SET_BASE_TIME_ERROR_CLR_2 */ "", 74169 /* TAF_SET_BASE_TIME_ERROR_CLR_3 */ "", 74170 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_0 */ "", 74171 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_1 */ "", 74172 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_2 */ "", 74173 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_3 */ "", 74174 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_CLR_0 */ "", 74175 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_CLR_1 */ "", 74176 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_CLR_2 */ "", 74177 /* TAF_SET_NEXT_CYCLE_TIME_ERROR_CLR_3 */ "", 74178 /* TAF_TBL_SWITCH_DONE_0 */ "", 74179 /* TAF_TBL_SWITCH_DONE_1 */ "", 74180 /* TAF_TBL_SWITCH_DONE_2 */ "", 74181 /* TAF_TBL_SWITCH_DONE_3 */ "", 74182 /* TAF_TBL_SWITCH_DONE_CLR_0 */ "", 74183 /* TAF_TBL_SWITCH_DONE_CLR_1 */ "", 74184 /* TAF_TBL_SWITCH_DONE_CLR_2 */ "", 74185 /* TAF_TBL_SWITCH_DONE_CLR_3 */ "", 74186 /* TAF_TOD_TIME_OFFSET */ "", 74187 /* TAG_0 */ "", 74188 /* TAG_1 */ "", 74189 /* TAR_ECC_1B_ERR_CNT */ "", 74190 /* TAR_ECC_2B_ERR_CNT */ "", 74191 /* TAR_ECC_ERR_1B_INITIATE */ "", 74192 /* TAR_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 74193 /* TAR_ECC_ERR_2B_INITIATE */ "", 74194 /* TAR_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 74195 /* TAR_ECC_INTERRUPT_REGISTER */ "", 74196 /* TAR_ECC_INTERRUPT_REGISTER_MASK */ "", 74197 /* TAR_ECC_INTERRUPT_REGISTER_TEST */ "", 74198 /* TAR_EGRESS_MCDB_REQUESTS_CTR */ "", 74199 /* TAR_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 74200 /* TAR_ERROR_INITIATION_DATA */ "", 74201 /* TAR_ERR_REPLICATION_REGISTER */ "", 74202 /* TAR_FABRIC_MC_BASE_QUEUE */ "", 74203 /* TAR_FLOW_AGR_SETTINGS */ "", 74204 /* TAR_FLOW_BASE_QUEUE */ "", 74205 /* TAR_GLOBAL_GENERAL_CFG_3 */ "", 74206 /* TAR_GLOBAL_MEM_OPTIONS */ "", 74207 /* TAR_GLOBAL_PP_7 */ "", 74208 /* TAR_GTIMER_CONFIGURATION */ "", 74209 /* TAR_INDIRECT_COMMAND */ "", 74210 /* TAR_INDIRECT_COMMAND_ADDRESS */ "", 74211 /* TAR_INDIRECT_COMMAND_DATA_INCREMENT */ "", 74212 /* TAR_INDIRECT_COMMAND_RD_DATA */ "", 74213 /* TAR_INDIRECT_COMMAND_WIDE_MEM */ "", 74214 /* TAR_INDIRECT_COMMAND_WR_DATA */ "", 74215 /* TAR_INDIRECT_FORCE_BUBBLE */ "", 74216 /* TAR_INGRESS_MCH_MCDB_REQUESTS_CTR */ "", 74217 /* TAR_INGRESS_MCL_MCDB_REQUESTS_CTR */ "", 74218 /* TAR_INTERRUPT_MASK_REGISTER */ "", 74219 /* TAR_INTERRUPT_REGISTER */ "", 74220 /* TAR_INTERRUPT_REGISTER_TEST */ "", 74221 /* TAR_INVALID_CUD */ "", 74222 /* TAR_INVALID_DESTINATION_QUEUE */ "", 74223 /* TAR_IRE_DEST_REQUESTS_CTR */ "", 74224 /* TAR_MAX_REPLICATIONS */ "", 74225 /* TAR_MCH_FWD_RX_REP_CTR */ "", 74226 /* TAR_MCH_LAST_REP_CMD_RX */ "", 74227 /* TAR_MCH_MIRROR_RX_REP_CTR */ "", 74228 /* TAR_MCH_SNOOP_RX_REP_CTR */ "", 74229 /* TAR_MCL_FWD_RX_REP_CTR */ "", 74230 /* TAR_MCL_LAST_REP_CMD_RX */ "", 74231 /* TAR_MCL_MIRROR_RX_REP_CTR */ "", 74232 /* TAR_MCL_SNOOP_RX_REP_CTR */ "", 74233 /* TAR_OUTLIF_SELECTION */ "", 74234 /* TAR_REPLICATOION_ENGINES_CONFIGURATION */ "", 74235 /* TAR_RESERVED_MIRROR_ADDR */ "", 74236 /* TAR_RESERVED_MTCD */ "", 74237 /* TAR_RESERVED_MTCP */ "", 74238 /* TAR_RESERVED_SPARE_0 */ "", 74239 /* TAR_RESERVED_SPARE_1 */ "", 74240 /* TAR_RESERVED_SPARE_2 */ "", 74241 /* TAR_RESERVED_SPARE_3 */ "", 74242 /* TAR_SBUS_BROADCAST_ID */ "", 74243 /* TAR_SBUS_LAST_IN_CHAIN */ "", 74244 /* TAR_SNOOP_MIRROR_SIZE */ "", 74245 /* TAR_STATIC_CONFIGURATION */ "", 74246 /* TAR_TAR_DEST_REQUESTS_CTR */ "", 74247 /* TAR_UC_FWD_RX_REP_CTR */ "", 74248 /* TAR_UC_LAST_REP_CMD_RX */ "", 74249 /* TAR_UC_MIRROR_RX_REP_CTR */ "", 74250 /* TAR_UC_SNOOP_RX_REP_CTR */ "", 74251 /* TAS_ASYNC_FIFO_OVERFLOW_0 */ "", 74252 /* TAS_ASYNC_FIFO_OVERFLOW_1 */ "", 74253 /* TAS_ASYNC_FIFO_OVERFLOW_2 */ "", 74254 /* TAS_ASYNC_FIFO_OVERFLOW_CLR_0 */ "", 74255 /* TAS_ASYNC_FIFO_OVERFLOW_CLR_1 */ "", 74256 /* TAS_ASYNC_FIFO_OVERFLOW_CLR_2 */ "", 74257 /* TAS_CONFIG_0 */ "", 74258 /* TAS_CONFIG_1 */ "", 74259 /* TAS_CONFIG_2 */ "", 74260 /* TAS_CTL_TBL_PTR_ERR_0 */ "", 74261 /* TAS_CTL_TBL_PTR_ERR_1 */ "", 74262 /* TAS_CTL_TBL_PTR_ERR_2 */ "", 74263 /* TAS_CTL_TBL_PTR_ERR_CLR_0 */ "", 74264 /* TAS_CTL_TBL_PTR_ERR_CLR_1 */ "", 74265 /* TAS_CTL_TBL_PTR_ERR_CLR_2 */ "", 74266 /* TAS_ERR_CNT */ "", 74267 /* TAS_GATE_PURGE_ENABLE */ "", 74268 /* TAS_MEM_TM */ "", 74269 /* TAS_OVERRUN_PKT_CNT_EXPRESS */ "", 74270 /* TAS_OVERRUN_PKT_CNT_PREEMPT */ "", 74271 /* TAS_PARITY_ERR_CLR_0 */ "", 74272 /* TAS_PARITY_ERR_CLR_1 */ "", 74273 /* TAS_PARITY_ERR_CLR_2 */ "", 74274 /* TAS_PARITY_ERR_STATUS */ "", 74275 /* TAS_PARITY_ERR_VLD_0 */ "", 74276 /* TAS_PARITY_ERR_VLD_1 */ "", 74277 /* TAS_PARITY_ERR_VLD_2 */ "", 74278 /* TAS_TBL_SWITCH_DONE_0 */ "", 74279 /* TAS_TBL_SWITCH_DONE_1 */ "", 74280 /* TAS_TBL_SWITCH_DONE_2 */ "", 74281 /* TAS_TBL_SWITCH_DONE_CLR_0 */ "", 74282 /* TAS_TBL_SWITCH_DONE_CLR_1 */ "", 74283 /* TAS_TBL_SWITCH_DONE_CLR_2 */ "", 74284 /* TBCA */ "MAC_GTxBCA", 74285 /* TBYT */ "MAC_GTxBYT", 74286 /* TCAM_ECC_1B_ERR_CNT */ "", 74287 /* TCAM_ECC_2B_ERR_CNT */ "", 74288 /* TCAM_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 74289 /* TCAM_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 74290 /* TCAM_ECC_INTERRUPT_REGISTER */ "", 74291 /* TCAM_ECC_INTERRUPT_REGISTER_MASK */ "", 74292 /* TCAM_ECC_INTERRUPT_REGISTER_TEST */ "", 74293 /* TCAM_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 74294 /* TCAM_ERROR_INITIATION_DATA */ "", 74295 /* TCAM_GTIMER_CONFIGURATION */ "", 74296 /* TCAM_GTIMER_CYCLE */ "", 74297 /* TCAM_INDIRECT_COMMAND */ "", 74298 /* TCAM_INDIRECT_COMMAND_ADDRESS */ "", 74299 /* TCAM_INDIRECT_COMMAND_RD_DATA */ "", 74300 /* TCAM_INDIRECT_COMMAND_WR_DATA */ "", 74301 /* TCAM_INDIRECT_FORCE_BUBBLE */ "", 74302 /* TCAM_INDIRECT_WR_MASK */ "", 74303 /* TCAM_INTERRUPT_MASK_REGISTER */ "", 74304 /* TCAM_INTERRUPT_REGISTER */ "", 74305 /* TCAM_INTERRUPT_REGISTER_TEST */ "", 74306 /* TCAM_PCMI_0 */ "", 74307 /* TCAM_PCMI_1 */ "", 74308 /* TCAM_PCMI_2 */ "", 74309 /* TCAM_PCMI_3 */ "", 74310 /* TCAM_PCMI_4 */ "", 74311 /* TCAM_PCMI_0_S */ "", 74312 /* TCAM_PCMI_0_T */ "", 74313 /* TCAM_PCMI_1_S */ "", 74314 /* TCAM_PCMI_1_T */ "", 74315 /* TCAM_PCMI_2_S */ "", 74316 /* TCAM_PCMI_2_T */ "", 74317 /* TCAM_PCMI_3_S */ "", 74318 /* TCAM_PCMI_3_T */ "", 74319 /* TCAM_PCMI_4_S */ "", 74320 /* TCAM_PCMI_4_T */ "", 74321 /* TCAM_REG_0041 */ "", 74322 /* TCAM_REG_0207 */ "", 74323 /* TCAM_REG_0211 */ "", 74324 /* TCAM_REG_00A4 */ "", 74325 /* TCAM_REG_00A6 */ "", 74326 /* TCAM_REG_00C2 */ "", 74327 /* TCAM_REG_020A */ "", 74328 /* TCAM_REG_020C */ "", 74329 /* TCAM_REG_020F */ "", 74330 /* TCAM_RESERVED_MIRROR_ADDR */ "", 74331 /* TCAM_RESERVED_MTCD */ "", 74332 /* TCAM_RESERVED_MTCP */ "", 74333 /* TCAM_RESERVED_SPARE_0 */ "", 74334 /* TCAM_RESERVED_SPARE_1 */ "", 74335 /* TCAM_RESERVED_SPARE_2 */ "", 74336 /* TCAM_RESERVED_SPARE_3 */ "", 74337 /* TCAM_SBUS_BROADCAST_ID */ "", 74338 /* TCAM_SBUS_LAST_IN_CHAIN */ "", 74339 /* TCAM_TCAM_ACCESS_COUNTER */ "", 74340 /* TCAM_TCAM_ACCESS_COUNTER_SELECTOR */ "", 74341 /* TCAM_TCAM_BANK_BLOCK_OWNER */ "", 74342 /* TCAM_TCAM_ECC_FIX_EN */ "", 74343 /* TCAM_TCAM_INTERFACE_ACCESS_BITMAP */ "", 74344 /* TCAM_TCAM_MANAGER_0 */ "", 74345 /* TCAM_TCAM_MANAGER_1 */ "", 74346 /* TCAM_TCAM_MATCH_BITMAP */ "", 74347 /* TCAM_TCAM_PROTECTION_ERROR */ "", 74348 /* TCAM_TCAM_PROTECTION_MACHINE_CONFIGURATION */ "", 74349 /* TCAM_TCAM_PROTECTION_TRIGGER */ "", 74350 /* TCAM_TCAM_QUERY_FAILURE */ "", 74351 /* TCAM_TCAM_RESET_BLOCK_BITMAP */ "", 74352 /* TCAM_TCAM_VTT_IF_SELECT */ "", 74353 /* TCB_BUFFER_READY */ "", 74354 /* TCB_BUFFER_STATUS */ "", 74355 /* TCB_CONFIG */ "", 74356 /* TCB_CURRENT_PHASE */ "", 74357 /* TCB_DISABLE_FROZEN_COUNT_DOWN */ "", 74358 /* TCB_EVENT_BUFFER_OVERFLOW_COUNTER */ "", 74359 /* TCB_FREEZE_DELAY */ "", 74360 /* TCB_ILLEGAL_CPU_ACCESS */ "", 74361 /* TCB_MEM_TM */ "", 74362 /* TCB_SAMPLE_RANDOM_SEED */ "", 74363 /* TCB_THRESHOLD_PROFILE */ "", 74364 /* TCPUDP_PROTOCOL */ "", 74365 /* TCPUDP_PROTOCOL_ENABLE */ "", 74366 /* TCP_FN_RAM_DBGCTRL */ "TCP_FN_RAM_CONTROL", 74367 /* TCP_FN_RAM_DBGCTRL_PIPE0 */ "TCP_FN_RAM_CONTROL_PIPE0", 74368 /* TCP_FN_RAM_DBGCTRL_PIPE1 */ "TCP_FN_RAM_CONTROL_PIPE1", 74369 /* TCP_FN_RAM_DBGCTRL_PIPE2 */ "TCP_FN_RAM_CONTROL_PIPE2", 74370 /* TCP_FN_RAM_DBGCTRL_PIPE3 */ "TCP_FN_RAM_CONTROL_PIPE3", 74371 /* TCP_FN_RAM_DBGCTRL_PIPE4 */ "TCP_FN_RAM_CONTROL_PIPE4", 74372 /* TCP_FN_RAM_DBGCTRL_PIPE5 */ "TCP_FN_RAM_CONTROL_PIPE5", 74373 /* TCP_FN_RAM_DBGCTRL_PIPE6 */ "TCP_FN_RAM_CONTROL_PIPE6", 74374 /* TCP_FN_RAM_DBGCTRL_PIPE7 */ "TCP_FN_RAM_CONTROL_PIPE7", 74375 /* TD2P_CMIC_TIMESYNC_TM */ "CMIC_TIMESYNC_TM", 74376 /* TDACT */ "", 74377 /* TDBGC0 */ "", 74378 /* TDBGC1 */ "", 74379 /* TDBGC2 */ "", 74380 /* TDBGC3 */ "", 74381 /* TDBGC4 */ "", 74382 /* TDBGC5 */ "", 74383 /* TDBGC6 */ "", 74384 /* TDBGC7 */ "", 74385 /* TDBGC8 */ "", 74386 /* TDBGC9 */ "", 74387 /* TDBGC10 */ "", 74388 /* TDBGC11 */ "", 74389 /* TDBGC0_64 */ "TDBGC0", 74390 /* TDBGC0_SELECT */ "", 74391 /* TDBGC10_64 */ "TDBGC10", 74392 /* TDBGC10_SELECT */ "", 74393 /* TDBGC11_64 */ "TDBGC11", 74394 /* TDBGC11_SELECT */ "", 74395 /* TDBGC12_64 */ "TDBGC12", 74396 /* TDBGC12_SELECT */ "", 74397 /* TDBGC13_64 */ "TDBGC13", 74398 /* TDBGC13_SELECT */ "", 74399 /* TDBGC14_64 */ "TDBGC14", 74400 /* TDBGC14_SELECT */ "", 74401 /* TDBGC15_64 */ "TDBGC15", 74402 /* TDBGC15_SELECT */ "", 74403 /* TDBGC1_64 */ "TDBGC1", 74404 /* TDBGC1_SELECT */ "", 74405 /* TDBGC2_64 */ "TDBGC2", 74406 /* TDBGC2_SELECT */ "", 74407 /* TDBGC3_64 */ "TDBGC3", 74408 /* TDBGC3_SELECT */ "", 74409 /* TDBGC4_64 */ "TDBGC4", 74410 /* TDBGC4_SELECT */ "", 74411 /* TDBGC5_64 */ "TDBGC5", 74412 /* TDBGC5_SELECT */ "", 74413 /* TDBGC6_64 */ "TDBGC6", 74414 /* TDBGC6_SELECT */ "", 74415 /* TDBGC7_64 */ "TDBGC7", 74416 /* TDBGC7_SELECT */ "", 74417 /* TDBGC8_64 */ "TDBGC8", 74418 /* TDBGC8_SELECT */ "", 74419 /* TDBGC9_64 */ "TDBGC9", 74420 /* TDBGC9_SELECT */ "", 74421 /* TDBGC_SELECT_2 */ "", 74422 /* TDFR */ "MAC_GTxDFR", 74423 /* TDM_CONFIG */ "", 74424 /* TDM_DFT_REG */ "", 74425 /* TDM_EN */ "", 74426 /* TDM_EN_COR_ERR_RPT */ "", 74427 /* TDM_HSP */ "", 74428 /* TDM_HSP_0 */ "", 74429 /* TDM_HSP_1 */ "", 74430 /* TDM_HSP_2 */ "", 74431 /* TDM_SYNC */ "", 74432 /* TDU_ADDRESS_TRANSLATION_CONFIG */ "", 74433 /* TDU_ADDRESS_TRANSLATION_MATRIX */ "", 74434 /* TDU_DRAM_BLOCKED_CONFIG */ "", 74435 /* TDU_DRAM_BLOCKED_STATUS */ "", 74436 /* TDU_ECC_1B_ERR_CNT */ "", 74437 /* TDU_ECC_2B_ERR_CNT */ "", 74438 /* TDU_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 74439 /* TDU_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 74440 /* TDU_ECC_INTERRUPT_REGISTER */ "", 74441 /* TDU_ECC_INTERRUPT_REGISTER_MASK */ "", 74442 /* TDU_ECC_INTERRUPT_REGISTER_TEST */ "", 74443 /* TDU_ERROR_INITIATION_DATA */ "", 74444 /* TDU_GTIMER_CONFIGURATION */ "", 74445 /* TDU_GTIMER_CYCLE */ "", 74446 /* TDU_INTERRUPT_MASK_REGISTER */ "", 74447 /* TDU_INTERRUPT_REGISTER */ "", 74448 /* TDU_INTERRUPT_REGISTER_TEST */ "", 74449 /* TDU_PCMI_0 */ "", 74450 /* TDU_PCMI_1 */ "", 74451 /* TDU_PCMI_2 */ "", 74452 /* TDU_PCMI_3 */ "", 74453 /* TDU_PCMI_4 */ "", 74454 /* TDU_PCMI_0_S */ "", 74455 /* TDU_PCMI_0_T */ "", 74456 /* TDU_PCMI_1_S */ "", 74457 /* TDU_PCMI_1_T */ "", 74458 /* TDU_PCMI_2_S */ "", 74459 /* TDU_PCMI_2_T */ "", 74460 /* TDU_PCMI_3_S */ "", 74461 /* TDU_PCMI_3_T */ "", 74462 /* TDU_PCMI_4_S */ "", 74463 /* TDU_PCMI_4_T */ "", 74464 /* TDU_READ_DATA_PATH_CONFIG */ "", 74465 /* TDU_READ_DATA_PATH_COUNTERS */ "", 74466 /* TDU_READ_REQUEST_PATH_CONFIG */ "", 74467 /* TDU_READ_REQUEST_PATH_COUNTERS */ "", 74468 /* TDU_READ_REQUEST_PER_BANK_COUNT */ "", 74469 /* TDU_READ_REQUEST_PER_CHANNEL_COUNT */ "", 74470 /* TDU_READ_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT */ "", 74471 /* TDU_REG_00A4 */ "", 74472 /* TDU_REG_00A6 */ "", 74473 /* TDU_REG_00C2 */ "", 74474 /* TDU_RESERVED_MIRROR_ADDR */ "", 74475 /* TDU_RESERVED_MTCD */ "", 74476 /* TDU_RESERVED_MTCP */ "", 74477 /* TDU_RESERVED_SPARE_0 */ "", 74478 /* TDU_RESERVED_SPARE_1 */ "", 74479 /* TDU_RESERVED_SPARE_2 */ "", 74480 /* TDU_RESERVED_SPARE_3 */ "", 74481 /* TDU_SBUS_BROADCAST_ID */ "", 74482 /* TDU_SBUS_LAST_IN_CHAIN */ "", 74483 /* TDU_WRITE_REQUEST_PATH_CONFIG */ "", 74484 /* TDU_WRITE_REQUEST_PATH_COUNTERS */ "", 74485 /* TDU_WRITE_REQUEST_PER_BANK_COUNT */ "", 74486 /* TDU_WRITE_REQUEST_PER_CHANNEL_COUNT */ "", 74487 /* TDU_WRITE_REQUEST_PER_LOGICAL_ADDRESS_BIT_COUNT */ "", 74488 /* TDVLN */ "MAC_GTxDVLN", 74489 /* TECMUX1 */ "", 74490 /* TECMUX2 */ "", 74491 /* TEDF */ "MAC_GTxEDF", 74492 /* TEPCFG_CID_0 */ "", 74493 /* TEPCFG_CID_1 */ "", 74494 /* TEPCFG_CID_2 */ "", 74495 /* TEPCFG_CID_3 */ "", 74496 /* TEPCFG_CID_4 */ "", 74497 /* TEPCFG_CID_5 */ "", 74498 /* TEPCFG_CID_6 */ "", 74499 /* TEPCFG_CID_7 */ "", 74500 /* TEPCFG_CID_8 */ "", 74501 /* TEPCFG_CID_9 */ "", 74502 /* TEPCFG_CID_10 */ "", 74503 /* TEPCFG_CID_11 */ "", 74504 /* TEPCFG_CID_12 */ "", 74505 /* TEPCFG_CID_13 */ "", 74506 /* TEPCFG_CID_14 */ "", 74507 /* TEPCFG_CID_15 */ "", 74508 /* TERR */ "MAC_GTxErr", 74509 /* TEST2 */ "", 74510 /* TFCS */ "MAC_GTxFCS", 74511 /* TFRG */ "MAC_GTxFRG", 74512 /* THDIEMA_BUFFER_CELL_LIMIT_SP */ "", 74513 /* THDIEMA_BUFFER_CELL_LIMIT_SP_SHARED */ "", 74514 /* THDIEMA_CELL_RESET_LIMIT_OFFSET_SP */ "", 74515 /* THDIEMA_CELL_SPAP_RED_OFFSET_SP */ "", 74516 /* THDIEMA_CELL_SPAP_YELLOW_OFFSET_SP */ "", 74517 /* THDIEMA_COLOR_AWARE */ "", 74518 /* THDIEMA_ECC_ERROR_SINGLE_BIT_ERROR_CNT */ "", 74519 /* THDIEMA_FLOW_CONTROL_XOFF_STATE */ "", 74520 /* THDIEMA_GLOBAL_HDRM_COUNT */ "", 74521 /* THDIEMA_GLOBAL_HDRM_LIMIT */ "", 74522 /* THDIEMA_INPUT_PORT_RX_ENABLE0_64 */ "THDIEMA_INPUT_PORT_RX_ENABLE0", 74523 /* THDIEMA_INPUT_PORT_RX_ENABLE1_64 */ "THDIEMA_INPUT_PORT_RX_ENABLE1", 74524 /* THDIEMA_INPUT_PORT_RX_ENABLE_64 */ "THDIEMA_INPUT_PORT_RX_ENABLE", 74525 /* THDIEMA_MEMORY_TM_0 */ "", 74526 /* THDIEMA_MEMORY_TM_1 */ "", 74527 /* THDIEMA_PARITY_ERROR_COUNTER */ "", 74528 /* THDIEMA_PARITY_ERROR_INTR_MASK */ "", 74529 /* THDIEMA_PARITY_ERROR_STATUS_0 */ "", 74530 /* THDIEMA_PARITY_ERROR_STATUS_1 */ "", 74531 /* THDIEMA_PG_GBL_HDRM_COUNT */ "", 74532 /* THDIEMA_PG_HDRM_COUNT_CELL */ "", 74533 /* THDIEMA_PG_HDRM_LIMIT_CELL */ "", 74534 /* THDIEMA_PG_MIN_CELL */ "", 74535 /* THDIEMA_PG_MIN_COUNT_CELL */ "", 74536 /* THDIEMA_PG_PORT_MIN_COUNT_CELL */ "", 74537 /* THDIEMA_PG_RESET_FLOOR_CELL */ "", 74538 /* THDIEMA_PG_RESET_OFFSET_CELL */ "", 74539 /* THDIEMA_PG_RESET_VALUE_CELL */ "", 74540 /* THDIEMA_PG_SHARED_COUNT_CELL */ "", 74541 /* THDIEMA_PG_SHARED_LIMIT_CELL */ "", 74542 /* THDIEMA_POOL_DROP_STATE */ "", 74543 /* THDIEMA_PORT_COUNT_CELL */ "", 74544 /* THDIEMA_PORT_FC_STATUS */ "", 74545 /* THDIEMA_PORT_LIMIT_STATES */ "", 74546 /* THDIEMA_PORT_LIMIT_STATE_0 */ "", 74547 /* THDIEMA_PORT_LIMIT_STATE_1 */ "", 74548 /* THDIEMA_PORT_MAX_PKT_SIZE */ "", 74549 /* THDIEMA_PORT_MAX_SHARED_CELL */ "", 74550 /* THDIEMA_PORT_MIN_CELL */ "", 74551 /* THDIEMA_PORT_MIN_COUNT_CELL */ "", 74552 /* THDIEMA_PORT_MIN_PG_ENABLE */ "", 74553 /* THDIEMA_PORT_OVQ_PAUSE_ENABLE0 */ "", 74554 /* THDIEMA_PORT_OVQ_PAUSE_ENABLE1 */ "", 74555 /* THDIEMA_PORT_OVQ_PAUSE_ENABLE_64 */ "THDIEMA_PORT_OVQ_PAUSE_ENABLE", 74556 /* THDIEMA_PORT_PAUSE_ENABLE0_64 */ "THDIEMA_PORT_PAUSE_ENABLE0", 74557 /* THDIEMA_PORT_PAUSE_ENABLE1_64 */ "THDIEMA_PORT_PAUSE_ENABLE1", 74558 /* THDIEMA_PORT_PAUSE_ENABLE_64 */ "THDIEMA_PORT_PAUSE_ENABLE", 74559 /* THDIEMA_PORT_PG_SPID */ "", 74560 /* THDIEMA_PORT_PRI_GRP0 */ "", 74561 /* THDIEMA_PORT_PRI_GRP1 */ "", 74562 /* THDIEMA_PORT_PRI_XON_ENABLE */ "", 74563 /* THDIEMA_PORT_PROFILE_MAP */ "", 74564 /* THDIEMA_PORT_RESUME_LIMIT_CELL */ "", 74565 /* THDIEMA_PORT_SHARED_COUNT_CELL */ "", 74566 /* THDIEMA_PORT_SHARED_MAX_PG_ENABLE */ "", 74567 /* THDIEMA_PROFILE0_PRI_GRP0 */ "", 74568 /* THDIEMA_PROFILE0_PRI_GRP1 */ "", 74569 /* THDIEMA_PROFILE1_PRI_GRP0 */ "", 74570 /* THDIEMA_PROFILE1_PRI_GRP1 */ "", 74571 /* THDIEMA_PROFILE2_PRI_GRP0 */ "", 74572 /* THDIEMA_PROFILE2_PRI_GRP1 */ "", 74573 /* THDIEMA_PROFILE3_PRI_GRP0 */ "", 74574 /* THDIEMA_PROFILE3_PRI_GRP1 */ "", 74575 /* THDIEMA_RDE_POOL_SELECT */ "", 74576 /* THDIEMA_THDI_BYPASS */ "", 74577 /* THDIEMA_TOTAL_BUFFER_COUNT_CELL */ "", 74578 /* THDIEMA_TOTAL_BUFFER_COUNT_CELL_SP */ "", 74579 /* THDIEMA_TOTAL_BUFFER_COUNT_CELL_SP_SHARED */ "", 74580 /* THDIEMA_USE_SP_SHARED */ "", 74581 /* THDIEXT_BUFFER_CELL_LIMIT_SP */ "", 74582 /* THDIEXT_BUFFER_CELL_LIMIT_SP_SHARED */ "", 74583 /* THDIEXT_CELL_RESET_LIMIT_OFFSET_SP */ "", 74584 /* THDIEXT_CELL_SPAP_RED_OFFSET_SP */ "", 74585 /* THDIEXT_CELL_SPAP_YELLOW_OFFSET_SP */ "", 74586 /* THDIEXT_COLOR_AWARE */ "", 74587 /* THDIEXT_ECC_ERROR_SINGLE_BIT_ERROR_CNT */ "", 74588 /* THDIEXT_FLOW_CONTROL_XOFF_STATE */ "", 74589 /* THDIEXT_GLOBAL_HDRM_COUNT */ "", 74590 /* THDIEXT_GLOBAL_HDRM_LIMIT */ "", 74591 /* THDIEXT_INPUT_PORT_RX_ENABLE0_64 */ "THDIEXT_INPUT_PORT_RX_ENABLE0", 74592 /* THDIEXT_INPUT_PORT_RX_ENABLE1_64 */ "THDIEXT_INPUT_PORT_RX_ENABLE1", 74593 /* THDIEXT_INPUT_PORT_RX_ENABLE_64 */ "THDIEXT_INPUT_PORT_RX_ENABLE", 74594 /* THDIEXT_MEMORY_TM_0 */ "", 74595 /* THDIEXT_MEMORY_TM_1 */ "", 74596 /* THDIEXT_PARITY_ERROR_COUNTER */ "", 74597 /* THDIEXT_PARITY_ERROR_INTR_MASK */ "", 74598 /* THDIEXT_PARITY_ERROR_STATUS_0 */ "", 74599 /* THDIEXT_PARITY_ERROR_STATUS_1 */ "", 74600 /* THDIEXT_PG_GBL_HDRM_COUNT */ "", 74601 /* THDIEXT_PG_HDRM_COUNT_CELL */ "", 74602 /* THDIEXT_PG_HDRM_LIMIT_CELL */ "", 74603 /* THDIEXT_PG_MIN_CELL */ "", 74604 /* THDIEXT_PG_MIN_COUNT_CELL */ "", 74605 /* THDIEXT_PG_PORT_MIN_COUNT_CELL */ "", 74606 /* THDIEXT_PG_RESET_FLOOR_CELL */ "", 74607 /* THDIEXT_PG_RESET_OFFSET_CELL */ "", 74608 /* THDIEXT_PG_RESET_VALUE_CELL */ "", 74609 /* THDIEXT_PG_SHARED_COUNT_CELL */ "", 74610 /* THDIEXT_PG_SHARED_LIMIT_CELL */ "", 74611 /* THDIEXT_POOL_DROP_STATE */ "", 74612 /* THDIEXT_PORT_COUNT_CELL */ "", 74613 /* THDIEXT_PORT_FC_STATUS */ "", 74614 /* THDIEXT_PORT_LIMIT_STATES */ "", 74615 /* THDIEXT_PORT_LIMIT_STATE_0 */ "", 74616 /* THDIEXT_PORT_LIMIT_STATE_1 */ "", 74617 /* THDIEXT_PORT_MAX_PKT_SIZE */ "", 74618 /* THDIEXT_PORT_MAX_SHARED_CELL */ "", 74619 /* THDIEXT_PORT_MIN_CELL */ "", 74620 /* THDIEXT_PORT_MIN_COUNT_CELL */ "", 74621 /* THDIEXT_PORT_MIN_PG_ENABLE */ "", 74622 /* THDIEXT_PORT_OVQ_PAUSE_ENABLE0 */ "", 74623 /* THDIEXT_PORT_OVQ_PAUSE_ENABLE1 */ "", 74624 /* THDIEXT_PORT_OVQ_PAUSE_ENABLE_64 */ "THDIEXT_PORT_OVQ_PAUSE_ENABLE", 74625 /* THDIEXT_PORT_PAUSE_ENABLE0_64 */ "THDIEXT_PORT_PAUSE_ENABLE0", 74626 /* THDIEXT_PORT_PAUSE_ENABLE1_64 */ "THDIEXT_PORT_PAUSE_ENABLE1", 74627 /* THDIEXT_PORT_PAUSE_ENABLE_64 */ "THDIEXT_PORT_PAUSE_ENABLE", 74628 /* THDIEXT_PORT_PG_SPID */ "", 74629 /* THDIEXT_PORT_PRI_GRP0 */ "", 74630 /* THDIEXT_PORT_PRI_GRP1 */ "", 74631 /* THDIEXT_PORT_PRI_XON_ENABLE */ "", 74632 /* THDIEXT_PORT_PROFILE_MAP */ "", 74633 /* THDIEXT_PORT_RESUME_LIMIT_CELL */ "", 74634 /* THDIEXT_PORT_SHARED_COUNT_CELL */ "", 74635 /* THDIEXT_PORT_SHARED_MAX_PG_ENABLE */ "", 74636 /* THDIEXT_PROFILE0_PRI_GRP0 */ "", 74637 /* THDIEXT_PROFILE0_PRI_GRP1 */ "", 74638 /* THDIEXT_PROFILE1_PRI_GRP0 */ "", 74639 /* THDIEXT_PROFILE1_PRI_GRP1 */ "", 74640 /* THDIEXT_PROFILE2_PRI_GRP0 */ "", 74641 /* THDIEXT_PROFILE2_PRI_GRP1 */ "", 74642 /* THDIEXT_PROFILE3_PRI_GRP0 */ "", 74643 /* THDIEXT_PROFILE3_PRI_GRP1 */ "", 74644 /* THDIEXT_RDE_POOL_SELECT */ "", 74645 /* THDIEXT_THDI_BYPASS */ "", 74646 /* THDIEXT_TOTAL_BUFFER_COUNT_CELL */ "", 74647 /* THDIEXT_TOTAL_BUFFER_COUNT_CELL_SP */ "", 74648 /* THDIEXT_TOTAL_BUFFER_COUNT_CELL_SP_SHARED */ "", 74649 /* THDIEXT_USE_SP_SHARED */ "", 74650 /* THDIQEN_BUFFER_CELL_LIMIT_SP */ "", 74651 /* THDIQEN_BUFFER_CELL_LIMIT_SP_SHARED */ "", 74652 /* THDIQEN_CELL_RESET_LIMIT_OFFSET_SP */ "", 74653 /* THDIQEN_CELL_SPAP_RED_OFFSET_SP */ "", 74654 /* THDIQEN_CELL_SPAP_YELLOW_OFFSET_SP */ "", 74655 /* THDIQEN_COLOR_AWARE */ "", 74656 /* THDIQEN_ECC_ERROR_SINGLE_BIT_ERROR_CNT */ "", 74657 /* THDIQEN_FLOW_CONTROL_XOFF_STATE */ "", 74658 /* THDIQEN_GLOBAL_HDRM_COUNT */ "", 74659 /* THDIQEN_GLOBAL_HDRM_LIMIT */ "", 74660 /* THDIQEN_INPUT_PORT_RX_ENABLE0_64 */ "THDIQEN_INPUT_PORT_RX_ENABLE0", 74661 /* THDIQEN_INPUT_PORT_RX_ENABLE1_64 */ "THDIQEN_INPUT_PORT_RX_ENABLE1", 74662 /* THDIQEN_INPUT_PORT_RX_ENABLE_64 */ "THDIQEN_INPUT_PORT_RX_ENABLE", 74663 /* THDIQEN_MEMORY_TM_0 */ "", 74664 /* THDIQEN_MEMORY_TM_1 */ "", 74665 /* THDIQEN_PARITY_ERROR_COUNTER */ "", 74666 /* THDIQEN_PARITY_ERROR_INTR_MASK */ "", 74667 /* THDIQEN_PARITY_ERROR_STATUS_0 */ "", 74668 /* THDIQEN_PARITY_ERROR_STATUS_1 */ "", 74669 /* THDIQEN_PG_GBL_HDRM_COUNT */ "", 74670 /* THDIQEN_PG_HDRM_COUNT_CELL */ "", 74671 /* THDIQEN_PG_HDRM_LIMIT_CELL */ "", 74672 /* THDIQEN_PG_MIN_CELL */ "", 74673 /* THDIQEN_PG_MIN_COUNT_CELL */ "", 74674 /* THDIQEN_PG_PORT_MIN_COUNT_CELL */ "", 74675 /* THDIQEN_PG_RESET_FLOOR_CELL */ "", 74676 /* THDIQEN_PG_RESET_OFFSET_CELL */ "", 74677 /* THDIQEN_PG_RESET_VALUE_CELL */ "", 74678 /* THDIQEN_PG_SHARED_COUNT_CELL */ "", 74679 /* THDIQEN_PG_SHARED_LIMIT_CELL */ "", 74680 /* THDIQEN_POOL_DROP_STATE */ "", 74681 /* THDIQEN_PORT_COUNT_CELL */ "", 74682 /* THDIQEN_PORT_FC_STATUS */ "", 74683 /* THDIQEN_PORT_LIMIT_STATES */ "", 74684 /* THDIQEN_PORT_LIMIT_STATE_0 */ "", 74685 /* THDIQEN_PORT_LIMIT_STATE_1 */ "", 74686 /* THDIQEN_PORT_MAX_PKT_SIZE */ "", 74687 /* THDIQEN_PORT_MAX_SHARED_CELL */ "", 74688 /* THDIQEN_PORT_MIN_CELL */ "", 74689 /* THDIQEN_PORT_MIN_COUNT_CELL */ "", 74690 /* THDIQEN_PORT_MIN_PG_ENABLE */ "", 74691 /* THDIQEN_PORT_OVQ_PAUSE_ENABLE0 */ "", 74692 /* THDIQEN_PORT_OVQ_PAUSE_ENABLE1 */ "", 74693 /* THDIQEN_PORT_OVQ_PAUSE_ENABLE_64 */ "THDIQEN_PORT_OVQ_PAUSE_ENABLE", 74694 /* THDIQEN_PORT_PAUSE_ENABLE0_64 */ "THDIQEN_PORT_PAUSE_ENABLE0", 74695 /* THDIQEN_PORT_PAUSE_ENABLE1_64 */ "THDIQEN_PORT_PAUSE_ENABLE1", 74696 /* THDIQEN_PORT_PAUSE_ENABLE_64 */ "THDIQEN_PORT_PAUSE_ENABLE", 74697 /* THDIQEN_PORT_PG_SPID */ "", 74698 /* THDIQEN_PORT_PRI_GRP0 */ "", 74699 /* THDIQEN_PORT_PRI_GRP1 */ "", 74700 /* THDIQEN_PORT_PRI_XON_ENABLE */ "", 74701 /* THDIQEN_PORT_PROFILE_MAP */ "", 74702 /* THDIQEN_PORT_RESUME_LIMIT_CELL */ "", 74703 /* THDIQEN_PORT_SHARED_COUNT_CELL */ "", 74704 /* THDIQEN_PORT_SHARED_MAX_PG_ENABLE */ "", 74705 /* THDIQEN_PROFILE0_PRI_GRP0 */ "", 74706 /* THDIQEN_PROFILE0_PRI_GRP1 */ "", 74707 /* THDIQEN_PROFILE1_PRI_GRP0 */ "", 74708 /* THDIQEN_PROFILE1_PRI_GRP1 */ "", 74709 /* THDIQEN_PROFILE2_PRI_GRP0 */ "", 74710 /* THDIQEN_PROFILE2_PRI_GRP1 */ "", 74711 /* THDIQEN_PROFILE3_PRI_GRP0 */ "", 74712 /* THDIQEN_PROFILE3_PRI_GRP1 */ "", 74713 /* THDIQEN_RDE_POOL_SELECT */ "", 74714 /* THDIQEN_THDI_BYPASS */ "", 74715 /* THDIQEN_TOTAL_BUFFER_COUNT_CELL */ "", 74716 /* THDIQEN_TOTAL_BUFFER_COUNT_CELL_SP */ "", 74717 /* THDIQEN_TOTAL_BUFFER_COUNT_CELL_SP_SHARED */ "", 74718 /* THDIQEN_USE_SP_SHARED */ "", 74719 /* THDIRQE_BUFFER_CELL_LIMIT_SP */ "", 74720 /* THDIRQE_BUFFER_CELL_LIMIT_SP_SHARED */ "", 74721 /* THDIRQE_CELL_RESET_LIMIT_OFFSET_SP */ "", 74722 /* THDIRQE_CELL_SPAP_RED_OFFSET_SP */ "", 74723 /* THDIRQE_CELL_SPAP_YELLOW_OFFSET_SP */ "", 74724 /* THDIRQE_COLOR_AWARE */ "", 74725 /* THDIRQE_ECC_ERROR_SINGLE_BIT_ERROR_CNT */ "", 74726 /* THDIRQE_FLOW_CONTROL_XOFF_STATE */ "", 74727 /* THDIRQE_GLOBAL_HDRM_COUNT */ "", 74728 /* THDIRQE_GLOBAL_HDRM_LIMIT */ "", 74729 /* THDIRQE_INPUT_PORT_RX_ENABLE0_64 */ "THDIRQE_INPUT_PORT_RX_ENABLE0", 74730 /* THDIRQE_INPUT_PORT_RX_ENABLE1_64 */ "THDIRQE_INPUT_PORT_RX_ENABLE1", 74731 /* THDIRQE_INPUT_PORT_RX_ENABLE_64 */ "THDIRQE_INPUT_PORT_RX_ENABLE", 74732 /* THDIRQE_MEMORY_TM_0 */ "", 74733 /* THDIRQE_MEMORY_TM_1 */ "", 74734 /* THDIRQE_PARITY_ERROR_COUNTER */ "", 74735 /* THDIRQE_PARITY_ERROR_INTR_MASK */ "", 74736 /* THDIRQE_PARITY_ERROR_STATUS_0 */ "", 74737 /* THDIRQE_PARITY_ERROR_STATUS_1 */ "", 74738 /* THDIRQE_PG_GBL_HDRM_COUNT */ "", 74739 /* THDIRQE_PG_HDRM_COUNT_CELL */ "", 74740 /* THDIRQE_PG_HDRM_LIMIT_CELL */ "", 74741 /* THDIRQE_PG_MIN_CELL */ "", 74742 /* THDIRQE_PG_MIN_COUNT_CELL */ "", 74743 /* THDIRQE_PG_PORT_MIN_COUNT_CELL */ "", 74744 /* THDIRQE_PG_RESET_FLOOR_CELL */ "", 74745 /* THDIRQE_PG_RESET_OFFSET_CELL */ "", 74746 /* THDIRQE_PG_RESET_VALUE_CELL */ "", 74747 /* THDIRQE_PG_SHARED_COUNT_CELL */ "", 74748 /* THDIRQE_PG_SHARED_LIMIT_CELL */ "", 74749 /* THDIRQE_POOL_DROP_STATE */ "", 74750 /* THDIRQE_PORT_COUNT_CELL */ "", 74751 /* THDIRQE_PORT_FC_STATUS */ "", 74752 /* THDIRQE_PORT_LIMIT_STATES */ "", 74753 /* THDIRQE_PORT_LIMIT_STATE_0 */ "", 74754 /* THDIRQE_PORT_LIMIT_STATE_1 */ "", 74755 /* THDIRQE_PORT_MAX_PKT_SIZE */ "", 74756 /* THDIRQE_PORT_MAX_SHARED_CELL */ "", 74757 /* THDIRQE_PORT_MIN_CELL */ "", 74758 /* THDIRQE_PORT_MIN_COUNT_CELL */ "", 74759 /* THDIRQE_PORT_MIN_PG_ENABLE */ "", 74760 /* THDIRQE_PORT_OVQ_PAUSE_ENABLE0 */ "", 74761 /* THDIRQE_PORT_OVQ_PAUSE_ENABLE1 */ "", 74762 /* THDIRQE_PORT_OVQ_PAUSE_ENABLE_64 */ "THDIRQE_PORT_OVQ_PAUSE_ENABLE", 74763 /* THDIRQE_PORT_PAUSE_ENABLE0_64 */ "THDIRQE_PORT_PAUSE_ENABLE0", 74764 /* THDIRQE_PORT_PAUSE_ENABLE1_64 */ "THDIRQE_PORT_PAUSE_ENABLE1", 74765 /* THDIRQE_PORT_PAUSE_ENABLE_64 */ "THDIRQE_PORT_PAUSE_ENABLE", 74766 /* THDIRQE_PORT_PG_SPID */ "", 74767 /* THDIRQE_PORT_PRI_GRP0 */ "", 74768 /* THDIRQE_PORT_PRI_GRP1 */ "", 74769 /* THDIRQE_PORT_PRI_XON_ENABLE */ "", 74770 /* THDIRQE_PORT_PROFILE_MAP */ "", 74771 /* THDIRQE_PORT_RESUME_LIMIT_CELL */ "", 74772 /* THDIRQE_PORT_SHARED_COUNT_CELL */ "", 74773 /* THDIRQE_PORT_SHARED_MAX_PG_ENABLE */ "", 74774 /* THDIRQE_PROFILE0_PRI_GRP0 */ "", 74775 /* THDIRQE_PROFILE0_PRI_GRP1 */ "", 74776 /* THDIRQE_PROFILE1_PRI_GRP0 */ "", 74777 /* THDIRQE_PROFILE1_PRI_GRP1 */ "", 74778 /* THDIRQE_PROFILE2_PRI_GRP0 */ "", 74779 /* THDIRQE_PROFILE2_PRI_GRP1 */ "", 74780 /* THDIRQE_PROFILE3_PRI_GRP0 */ "", 74781 /* THDIRQE_PROFILE3_PRI_GRP1 */ "", 74782 /* THDIRQE_RDE_POOL_SELECT */ "", 74783 /* THDIRQE_THDI_BYPASS */ "", 74784 /* THDIRQE_TOTAL_BUFFER_COUNT_CELL */ "", 74785 /* THDIRQE_TOTAL_BUFFER_COUNT_CELL_SP */ "", 74786 /* THDIRQE_TOTAL_BUFFER_COUNT_CELL_SP_SHARED */ "", 74787 /* THDIRQE_USE_SP_SHARED */ "", 74788 /* THDI_BST_PG_HDRM_PROFILE */ "", 74789 /* THDI_BST_PG_HDRM_PROFILE_XPE0 */ "", 74790 /* THDI_BST_PG_HDRM_PROFILE_XPE1 */ "", 74791 /* THDI_BST_PG_HDRM_PROFILE_XPE2 */ "", 74792 /* THDI_BST_PG_HDRM_PROFILE_XPE3 */ "", 74793 /* THDI_BST_PG_SHARED_PROFILE */ "", 74794 /* THDI_BST_PG_SHARED_PROFILE_XPE0 */ "", 74795 /* THDI_BST_PG_SHARED_PROFILE_XPE1 */ "", 74796 /* THDI_BST_PG_SHARED_PROFILE_XPE2 */ "", 74797 /* THDI_BST_PG_SHARED_PROFILE_XPE3 */ "", 74798 /* THDI_BST_PROFILE_THRESH_PG_HDRM */ "THDI_PORT_PG_BST_THRESHOLD_HDRM", 74799 /* THDI_BST_PROFILE_THRESH_PG_SHARED */ "THDI_PORT_PG_BST_THRESHOLD_SHARED", 74800 /* THDI_BST_PROFILE_THRESH_PORT_SHARED */ "THDI_PORT_SP_BST_THRESHOLD", 74801 /* THDI_BST_PROFILE_THRESH_SP */ "THDI_SP_BST_THRESHOLD", 74802 /* THDI_BST_SHADOW_SP */ "THDI_SP_BST_STAT", 74803 /* THDI_BST_SP_GLOBAL_SHARED_CNT */ "", 74804 /* THDI_BST_SP_GLOBAL_SHARED_PROFILE */ "", 74805 /* THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE0 */ "", 74806 /* THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE1 */ "", 74807 /* THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE2 */ "", 74808 /* THDI_BST_SP_GLOBAL_SHARED_PROFILE_XPE3 */ "", 74809 /* THDI_BST_SP_SHARED_PROFILE */ "", 74810 /* THDI_BST_SP_SHARED_PROFILE_XPE0 */ "", 74811 /* THDI_BST_SP_SHARED_PROFILE_XPE1 */ "", 74812 /* THDI_BST_SP_SHARED_PROFILE_XPE2 */ "", 74813 /* THDI_BST_SP_SHARED_PROFILE_XPE3 */ "", 74814 /* THDI_BST_TRIGGER_STATUS */ "", 74815 /* THDI_BST_TRIGGER_STATUS_32 */ "THDI_BST_TRIGGER_STATUS", 74816 /* THDI_BST_TRIGGER_STATUS_32_XPE0 */ "THDI_BST_TRIGGER_STATUS_XPE0", 74817 /* THDI_BST_TRIGGER_STATUS_32_XPE1 */ "THDI_BST_TRIGGER_STATUS_XPE1", 74818 /* THDI_BST_TRIGGER_STATUS_32_XPE2 */ "THDI_BST_TRIGGER_STATUS_XPE2", 74819 /* THDI_BST_TRIGGER_STATUS_32_XPE3 */ "THDI_BST_TRIGGER_STATUS_XPE3", 74820 /* THDI_BST_TRIGGER_STATUS_PIPEX */ "", 74821 /* THDI_BST_TRIGGER_STATUS_PIPEY */ "", 74822 /* THDI_BST_TRIGGER_STATUS_TYPE */ "", 74823 /* THDI_BST_TRIGGER_STATUS_TYPE_PIPEX */ "", 74824 /* THDI_BST_TRIGGER_STATUS_TYPE_PIPEY */ "", 74825 /* THDI_BST_TRIGGER_STATUS_TYPE_XPE0 */ "", 74826 /* THDI_BST_TRIGGER_STATUS_TYPE_XPE1 */ "", 74827 /* THDI_BST_TRIGGER_STATUS_TYPE_XPE2 */ "", 74828 /* THDI_BST_TRIGGER_STATUS_TYPE_XPE3 */ "", 74829 /* THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL */ "", 74830 /* THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE0 */ "", 74831 /* THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE1 */ "", 74832 /* THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE2 */ "", 74833 /* THDI_BUFFER_CELL_LIMIT_PUBLIC_POOL_XPE3 */ "", 74834 /* THDI_BUFFER_CELL_LIMIT_SP */ "", 74835 /* THDI_BUFFER_CELL_LIMIT_SP_XPE0 */ "", 74836 /* THDI_BUFFER_CELL_LIMIT_SP_XPE1 */ "", 74837 /* THDI_BUFFER_CELL_LIMIT_SP_XPE2 */ "", 74838 /* THDI_BUFFER_CELL_LIMIT_SP_XPE3 */ "", 74839 /* THDI_BYPASS */ "", 74840 /* THDI_CELL_RESET_LIMIT_OFFSET_SP */ "", 74841 /* THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE0 */ "", 74842 /* THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE1 */ "", 74843 /* THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE2 */ "", 74844 /* THDI_CELL_RESET_LIMIT_OFFSET_SP_XPE3 */ "", 74845 /* THDI_CELL_SPAP_RED_OFFSET_SP */ "", 74846 /* THDI_CELL_SPAP_RED_OFFSET_SP_XPE0 */ "", 74847 /* THDI_CELL_SPAP_RED_OFFSET_SP_XPE1 */ "", 74848 /* THDI_CELL_SPAP_RED_OFFSET_SP_XPE2 */ "", 74849 /* THDI_CELL_SPAP_RED_OFFSET_SP_XPE3 */ "", 74850 /* THDI_CELL_SPAP_YELLOW_OFFSET_SP */ "", 74851 /* THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE0 */ "", 74852 /* THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE1 */ "", 74853 /* THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE2 */ "", 74854 /* THDI_CELL_SPAP_YELLOW_OFFSET_SP_XPE3 */ "", 74855 /* THDI_EN_COR_ERR_RPT */ "", 74856 /* THDI_FDR_EVENT_STATUS */ "", 74857 /* THDI_FLOW_CONTROL_XOFF_STATE */ "", 74858 /* THDI_FLOW_CONTROL_XOFF_STATE_XPE0 */ "", 74859 /* THDI_FLOW_CONTROL_XOFF_STATE_XPE1 */ "", 74860 /* THDI_FLOW_CONTROL_XOFF_STATE_XPE2 */ "", 74861 /* THDI_FLOW_CONTROL_XOFF_STATE_XPE3 */ "", 74862 /* THDI_GLOBAL_HDRM_COUNT */ "", 74863 /* THDI_GLOBAL_HDRM_COUNT_PIPEX */ "", 74864 /* THDI_GLOBAL_HDRM_COUNT_PIPEY */ "", 74865 /* THDI_GLOBAL_HDRM_COUNT_XPE0 */ "", 74866 /* THDI_GLOBAL_HDRM_COUNT_XPE1 */ "", 74867 /* THDI_GLOBAL_HDRM_COUNT_XPE2 */ "", 74868 /* THDI_GLOBAL_HDRM_COUNT_XPE3 */ "", 74869 /* THDI_GLOBAL_HDRM_LIMIT */ "", 74870 /* THDI_GLOBAL_HDRM_LIMIT_PIPEX */ "", 74871 /* THDI_GLOBAL_HDRM_LIMIT_PIPEY */ "", 74872 /* THDI_GLOBAL_HDRM_RESERVED */ "", 74873 /* THDI_GLOBAL_HDRM_RESERVED_PIPEX */ "", 74874 /* THDI_GLOBAL_HDRM_RESERVED_PIPEY */ "", 74875 /* THDI_GLOBAL_HDRM_RESERVED_XPE0 */ "", 74876 /* THDI_GLOBAL_HDRM_RESERVED_XPE1 */ "", 74877 /* THDI_GLOBAL_HDRM_RESERVED_XPE2 */ "", 74878 /* THDI_GLOBAL_HDRM_RESERVED_XPE3 */ "", 74879 /* THDI_HDRM_BUFFER_CELL_LIMIT_HP */ "", 74880 /* THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE0 */ "", 74881 /* THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE1 */ "", 74882 /* THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE2 */ "", 74883 /* THDI_HDRM_BUFFER_CELL_LIMIT_HP_XPE3 */ "", 74884 /* THDI_HDRM_POOL_CFG */ "", 74885 /* THDI_HDRM_POOL_COUNT_HP */ "", 74886 /* THDI_HDRM_POOL_PEAK_COUNT_HP */ "", 74887 /* THDI_HDRM_POOL_STATUS */ "", 74888 /* THDI_HDRM_PORT_PG_HPID */ "", 74889 /* THDI_INPUT_PORT_XON_ENABLES */ "THDI_INPUT_PORT_XON_ENABLES", 74890 /* THDI_MEMORY_PTPG_CFG_MEM_TM */ "", 74891 /* THDI_MEMORY_PTPG_CFG_MEM_TM_0 */ "", 74892 /* THDI_MEMORY_PTPG_CFG_MEM_TM_1 */ "", 74893 /* THDI_MEMORY_PTSP_CFG_MEM_TM */ "", 74894 /* THDI_MEMORY_PTSP_CFG_MEM_TM_0 */ "", 74895 /* THDI_MEMORY_PTSP_CFG_MEM_TM_1 */ "", 74896 /* THDI_MEMORY_TM */ "", 74897 /* THDI_MEMORY_TM_0 */ "", 74898 /* THDI_MEMORY_TM_1 */ "", 74899 /* THDI_MEM_INIT_STATUS */ "", 74900 /* THDI_MEM_INIT_STATUS_XPE0 */ "", 74901 /* THDI_MEM_INIT_STATUS_XPE1 */ "", 74902 /* THDI_MEM_INIT_STATUS_XPE2 */ "", 74903 /* THDI_MEM_INIT_STATUS_XPE3 */ "", 74904 /* THDI_PG_FDR_MODE_ENABLE */ "", 74905 /* THDI_POOL_CONFIG */ "", 74906 /* THDI_POOL_DROP_STATE */ "", 74907 /* THDI_POOL_SHARED_COUNT_SP */ "", 74908 /* THDI_PORT_LIMIT_STATES */ "", 74909 /* THDI_PORT_LIMIT_STATES_XPE0 */ "", 74910 /* THDI_PORT_LIMIT_STATES_XPE1 */ "", 74911 /* THDI_PORT_LIMIT_STATES_XPE2 */ "", 74912 /* THDI_PORT_LIMIT_STATES_XPE3 */ "", 74913 /* THDI_PORT_MAX_PKT_SIZE */ "", 74914 /* THDI_PORT_PG_SPID */ "", 74915 /* THDI_PORT_PRI_GRP0 */ "", 74916 /* THDI_PORT_PRI_GRP1 */ "", 74917 /* THDI_TOTAL_CELL_COUNT_PUBLIC_POOL */ "", 74918 /* THDI_TO_OOBFC_SP_ST */ "", 74919 /* THDO_BST_PORT_ECC_ERROR_ADDRESS */ "", 74920 /* THDO_BST_QGROUP_ECC_ERROR_ADDRESS */ "", 74921 /* THDO_BST_QUEUE_ECC_ERROR_ADDRESS */ "", 74922 /* THDO_BST_STAT */ "THDO_BST_TRIGGER_STATUS", 74923 /* THDO_BYPASS */ "", 74924 /* THDO_CONFIG_PORT_ECC_ERROR_ADDRESS */ "", 74925 /* THDO_CONFIG_QGROUP_ECC_ERROR_ADDRESS */ "", 74926 /* THDO_CONFIG_QUEUE_ECC_ERROR_ADDRESS */ "", 74927 /* THDO_COUNTER_PORT_ECC_ERROR_ADDRESS */ "", 74928 /* THDO_COUNTER_QGROUP_ECC_ERROR_ADDRESS */ "", 74929 /* THDO_COUNTER_QUEUE_ECC_ERROR_ADDRESS */ "", 74930 /* THDO_CTRO_ECC_ERROR_ADDR */ "", 74931 /* THDO_DEBUG */ "", 74932 /* THDO_DEBUG_DCM_PM */ "", 74933 /* THDO_DEBUG_TM_UC0 */ "", 74934 /* THDO_DEBUG_TM_UC1 */ "", 74935 /* THDO_DEBUG_TM_UCSP0 */ "", 74936 /* THDO_DEBUG_TM_UCSP1 */ "", 74937 /* THDO_DROP_CTR_CONFIG */ "", 74938 /* THDO_INTEROP_CONFIG */ "", 74939 /* THDO_INTEROP_CONFIG_PLUS */ "", 74940 /* THDO_MEMDEBUG_CTRO_UC_DTYPE */ "", 74941 /* THDO_MEMDEBUG_CTRO_UC_PKT_STORE */ "", 74942 /* THDO_MEMDEBUG_OPNCONFIG */ "", 74943 /* THDO_MEMDEBUG_OPNCOUNT */ "", 74944 /* THDO_MEMDEBUG_OPNOFFSET */ "", 74945 /* THDO_MEMDEBUG_OPNSTATUS */ "", 74946 /* THDO_MEMDEBUG_QCONFIG */ "", 74947 /* THDO_MEMDEBUG_QCOUNT */ "", 74948 /* THDO_MEMDEBUG_QOFFSET */ "", 74949 /* THDO_MEMDEBUG_QRESET */ "", 74950 /* THDO_MEMDEBUG_QSTATUS */ "", 74951 /* THDO_MEMORY_TM_0 */ "", 74952 /* THDO_MEMORY_TM_1 */ "", 74953 /* THDO_MISCCONFIG */ "", 74954 /* THDO_OFFSET_QGROUP_ECC_ERROR_ADDRESS */ "", 74955 /* THDO_OFFSET_QUEUE_ECC_ERROR_ADDRESS */ "", 74956 /* THDO_PARITY_ERROR_ADDRESS */ "", 74957 /* THDO_PARITY_ERROR_COUNT */ "", 74958 /* THDO_PARITY_ERROR_COUNT_2BIT */ "", 74959 /* THDO_PARITY_ERROR_MASK1 */ "", 74960 /* THDO_PARITY_ERROR_MASK2 */ "", 74961 /* THDO_PARITY_ERROR_STATUS1 */ "", 74962 /* THDO_PARITY_ERROR_STATUS2 */ "", 74963 /* THDO_PARITY_ERROR_STATUS_64 */ "THDO_PARITY_ERROR_STATUS", 74964 /* THDO_PORT_DISABLE_CFG1 */ "", 74965 /* THDO_PORT_DISABLE_STATUS */ "", 74966 /* THDO_PORT_E2ECC_COS_SPID */ "", 74967 /* THDO_QUEUE_DISABLE_CFG1 */ "", 74968 /* THDO_QUEUE_DISABLE_CFG2 */ "", 74969 /* THDO_QUEUE_DISABLE_STATUS */ "", 74970 /* THDO_Q_TO_QGRP_MAP_ECC_ERROR_ADDRESS */ "", 74971 /* THDO_RDE_SP_SELECT */ "", 74972 /* THDO_RDE_WORK_QUEUE_DROP_STATUS_64 */ "THDO_RDE_WORK_QUEUE_DROP_STATUS", 74973 /* THDO_RESUME_QGROUP_ECC_ERROR_ADDRESS */ "", 74974 /* THDO_RESUME_QUEUE_ECC_ERROR_ADDRESS */ "", 74975 /* THDO_RQE_WORK_QUEUE_DROP_STATUS_64 */ "THDO_RQE_WORK_QUEUE_DROP_STATUS", 74976 /* THDO_TO_OOBFC_SP_ST */ "", 74977 /* THDO_UNICAST_DROP_EMIRROR_CNT */ "", 74978 /* THDU_BST_STAT */ "", 74979 /* THDU_BYPASS */ "", 74980 /* THDU_CNG_STATE_RESET */ "", 74981 /* THDU_CNG_STATE_RESET_X */ "", 74982 /* THDU_CNG_STATE_RESET_XPE0 */ "", 74983 /* THDU_CNG_STATE_RESET_XPE1 */ "", 74984 /* THDU_CNG_STATE_RESET_XPE2 */ "", 74985 /* THDU_CNG_STATE_RESET_XPE3 */ "", 74986 /* THDU_CNG_STATE_RESET_Y */ "", 74987 /* THDU_DEBUG */ "", 74988 /* THDU_MEMORY_0_TM */ "", 74989 /* THDU_MEMORY_1_TM */ "", 74990 /* THDU_MEMORY_1_TM_64 */ "THDU_MEMORY_1_TM", 74991 /* THDU_OUTPUT_PORT_RX_ENABLE0_64 */ "THDU_OUTPUT_PORT_RX_ENABLE0", 74992 /* THDU_OUTPUT_PORT_RX_ENABLE1_64 */ "THDU_OUTPUT_PORT_RX_ENABLE1", 74993 /* THDU_OUTPUT_PORT_RX_ENABLE_64 */ "THDU_OUTPUT_PORT_RX_ENABLE", 74994 /* THDU_OUTPUT_PORT_RX_ENABLE_64_XPE0 */ "THDU_OUTPUT_PORT_RX_ENABLE", 74995 /* THDU_OUTPUT_PORT_RX_ENABLE_64_XPE1 */ "THDU_OUTPUT_PORT_RX_ENABLE", 74996 /* THDU_OUTPUT_PORT_RX_ENABLE_64_XPE2 */ "THDU_OUTPUT_PORT_RX_ENABLE", 74997 /* THDU_OUTPUT_PORT_RX_ENABLE_64_XPE3 */ "THDU_OUTPUT_PORT_RX_ENABLE", 74998 /* THDU_OUTPUT_PORT_RX_ENABLE_SPLIT0 */ "THDU_OUTPUT_PORT_RX_ENABLE_SPLIT0", 74999 /* THDU_OUTPUT_PORT_RX_ENABLE_SPLIT1 */ "THDU_OUTPUT_PORT_RX_ENABLE_SPLIT1", 75000 /* THDU_OUTPUT_PORT_RX_ENABLE_SPLIT0_XPE0 */ "THDU_OUTPUT_PORT_RX_ENABLE_SPLIT0", 75001 /* THDU_OUTPUT_PORT_RX_ENABLE_SPLIT1_XPE0 */ "THDU_OUTPUT_PORT_RX_ENABLE_SPLIT1", 75002 /* THDU_PORT_E2ECC_COS_SPID */ "", 75003 /* THDU_PORT_E2ECC_COS_SPID_XPE0 */ "", 75004 /* THDU_PORT_E2ECC_COS_SPID_XPE1 */ "", 75005 /* THDU_PORT_E2ECC_COS_SPID_XPE2 */ "", 75006 /* THDU_PORT_E2ECC_COS_SPID_XPE3 */ "", 75007 /* THD_MISC_CONTROL */ "THDU_DEBUG", 75008 /* TICK_MODE */ "", 75009 /* TIMER_RAW_INTR_STATUS */ "", 75010 /* TIME_DOMAIN */ "", 75011 /* TIME_DOMAIN_CONFIG */ "", 75012 /* TJBDMAX1_TCID_0 */ "", 75013 /* TJBDMAX1_TCID_1 */ "", 75014 /* TJBDMAX1_TCID_2 */ "", 75015 /* TJBDMAX1_TCID_3 */ "", 75016 /* TJBDMAX1_TCID_4 */ "", 75017 /* TJBDMAX1_TCID_5 */ "", 75018 /* TJBDMAX1_TCID_6 */ "", 75019 /* TJBDMAX1_TCID_7 */ "", 75020 /* TJBDMAX1_TCID_8 */ "", 75021 /* TJBDMAX1_TCID_9 */ "", 75022 /* TJBDMAX1_TCID_10 */ "", 75023 /* TJBDMAX1_TCID_11 */ "", 75024 /* TJBDMAX1_TCID_12 */ "", 75025 /* TJBDMAX1_TCID_13 */ "", 75026 /* TJBDMAX1_TCID_14 */ "", 75027 /* TJBDMAX1_TCID_15 */ "", 75028 /* TJBDMAX2_TCID_0 */ "", 75029 /* TJBDMAX2_TCID_1 */ "", 75030 /* TJBDMAX2_TCID_2 */ "", 75031 /* TJBDMAX2_TCID_3 */ "", 75032 /* TJBDMAX2_TCID_4 */ "", 75033 /* TJBDMAX2_TCID_5 */ "", 75034 /* TJBDMAX2_TCID_6 */ "", 75035 /* TJBDMAX2_TCID_7 */ "", 75036 /* TJBDMAX2_TCID_8 */ "", 75037 /* TJBDMAX2_TCID_9 */ "", 75038 /* TJBDMAX2_TCID_10 */ "", 75039 /* TJBDMAX2_TCID_11 */ "", 75040 /* TJBDMAX2_TCID_12 */ "", 75041 /* TJBDMAX2_TCID_13 */ "", 75042 /* TJBDMAX2_TCID_14 */ "", 75043 /* TJBDMAX2_TCID_15 */ "", 75044 /* TJBR */ "MAC_GTxJBR", 75045 /* TLCL */ "MAC_GTxLCL", 75046 /* TMCA */ "MAC_GTxMCA", 75047 /* TMCL */ "MAC_GTxMCL", 75048 /* TMGV */ "MAC_GTx1522", 75049 /* TMON_ADC_STS0 */ "", 75050 /* TMON_CTRL0 */ "", 75051 /* TMON_CTRL1 */ "", 75052 /* TM_RESEQMEM */ "", 75053 /* TNCL */ "MAC_GTxNCL", 75054 /* TOD_TIME_OFFSET */ "", 75055 /* TOP_ARS_WRAP_CLK_PMB_EN */ "", 75056 /* TOP_AVS_CONTROL */ "", 75057 /* TOP_AVS_CTRL */ "", 75058 /* TOP_AVS_INTR_STATUS */ "", 75059 /* TOP_AVS_SEL_REG */ "", 75060 /* TOP_AVS_TMON_RESULT */ "", 75061 /* TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0 */ "", 75062 /* TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1 */ "", 75063 /* TOP_BROAD_SYNC0_LCPLL_SAMPLE_DIV_CTRL */ "", 75064 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_0 */ "", 75065 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1 */ "", 75066 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_2 */ "", 75067 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3 */ "", 75068 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_4 */ "", 75069 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_5 */ "", 75070 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_6 */ "", 75071 /* TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_7 */ "", 75072 /* TOP_BROAD_SYNC0_PLL_STATUS */ "", 75073 /* TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0 */ "", 75074 /* TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1 */ "", 75075 /* TOP_BROAD_SYNC1_LCPLL_SAMPLE_DIV_CTRL */ "", 75076 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_0 */ "", 75077 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1 */ "", 75078 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_2 */ "", 75079 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3 */ "", 75080 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_4 */ "", 75081 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_5 */ "", 75082 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_6 */ "", 75083 /* TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_7 */ "", 75084 /* TOP_BROAD_SYNC1_PLL_STATUS */ "", 75085 /* TOP_BROAD_SYNC_PLL_CTRL_REGISTER_0 */ "", 75086 /* TOP_BROAD_SYNC_PLL_CTRL_REGISTER_1 */ "", 75087 /* TOP_BROAD_SYNC_PLL_CTRL_REGISTER_2 */ "", 75088 /* TOP_BROAD_SYNC_PLL_CTRL_REGISTER_3 */ "", 75089 /* TOP_BROAD_SYNC_PLL_CTRL_REGISTER_4 */ "", 75090 /* TOP_BROAD_SYNC_PLL_STATUS */ "", 75091 /* TOP_BS0_CLK_INPUT_DLY_CTRL */ "", 75092 /* TOP_BS0_CLK_OUTPUT_DLY_CTRL */ "", 75093 /* TOP_BS0_HB_INPUT_DLY_CTRL */ "", 75094 /* TOP_BS0_HB_OUTPUT_DLY_CTRL */ "", 75095 /* TOP_BS0_PAD_CONTROL */ "", 75096 /* TOP_BS0_TC_INPUT_DLY_CTRL */ "", 75097 /* TOP_BS0_TC_OUTPUT_DLY_CTRL */ "", 75098 /* TOP_BS1_CLK_INPUT_DLY_CTRL */ "", 75099 /* TOP_BS1_CLK_OUTPUT_DLY_CTRL */ "", 75100 /* TOP_BS1_HB_INPUT_DLY_CTRL */ "", 75101 /* TOP_BS1_HB_OUTPUT_DLY_CTRL */ "", 75102 /* TOP_BS1_PAD_CONTROL */ "", 75103 /* TOP_BS1_TC_INPUT_DLY_CTRL */ "", 75104 /* TOP_BS1_TC_OUTPUT_DLY_CTRL */ "", 75105 /* TOP_BS_PLL0_CTRL_0 */ "", 75106 /* TOP_BS_PLL0_CTRL_1 */ "", 75107 /* TOP_BS_PLL0_CTRL_2 */ "", 75108 /* TOP_BS_PLL0_CTRL_3 */ "", 75109 /* TOP_BS_PLL0_CTRL_4 */ "", 75110 /* TOP_BS_PLL0_CTRL_5 */ "", 75111 /* TOP_BS_PLL0_CTRL_6 */ "", 75112 /* TOP_BS_PLL0_CTRL_7 */ "", 75113 /* TOP_BS_PLL0_CTRL_8 */ "", 75114 /* TOP_BS_PLL0_STATUS */ "", 75115 /* TOP_BS_PLL1_CTRL_0 */ "", 75116 /* TOP_BS_PLL1_CTRL_1 */ "", 75117 /* TOP_BS_PLL1_CTRL_2 */ "", 75118 /* TOP_BS_PLL1_CTRL_3 */ "", 75119 /* TOP_BS_PLL1_CTRL_4 */ "", 75120 /* TOP_BS_PLL1_CTRL_5 */ "", 75121 /* TOP_BS_PLL1_CTRL_6 */ "", 75122 /* TOP_BS_PLL1_CTRL_7 */ "", 75123 /* TOP_BS_PLL1_CTRL_8 */ "", 75124 /* TOP_BS_PLL1_STATUS */ "", 75125 /* TOP_BS_PLL_CTRL_0 */ "", 75126 /* TOP_BS_PLL_CTRL_1 */ "", 75127 /* TOP_BS_PLL_CTRL_2 */ "", 75128 /* TOP_BS_PLL_CTRL_3 */ "", 75129 /* TOP_BS_PLL_CTRL_4 */ "", 75130 /* TOP_BS_PLL_CTRL_5 */ "", 75131 /* TOP_BS_PLL_STATUS */ "", 75132 /* TOP_CES_PLL_CTRL_REGISTER_0 */ "", 75133 /* TOP_CES_PLL_CTRL_REGISTER_1 */ "", 75134 /* TOP_CES_PLL_CTRL_REGISTER_2 */ "", 75135 /* TOP_CES_PLL_CTRL_REGISTER_3 */ "", 75136 /* TOP_CES_PLL_CTRL_REGISTER_4 */ "", 75137 /* TOP_CES_PLL_CTRL_REGISTER_5 */ "", 75138 /* TOP_CES_PLL_STATUS */ "", 75139 /* TOP_CI_DDR_PHY_REG_CTRL */ "", 75140 /* TOP_CI_DDR_PHY_REG_DATA */ "", 75141 /* TOP_CI_PHY_CONTROL */ "", 75142 /* TOP_CI_PHY_STATUS */ "", 75143 /* TOP_CLOCKING_ENFORCE_PCG */ "", 75144 /* TOP_CLOCKING_ENFORCE_PSG */ "", 75145 /* TOP_CMICD_IOPAD_CTRL_0 */ "", 75146 /* TOP_CMICD_IOPAD_CTRL_1 */ "", 75147 /* TOP_CMICD_IOPAD_CTRL_2 */ "", 75148 /* TOP_CMICD_IOPAD_CTRL_3 */ "", 75149 /* TOP_CORE_CLK_FREQ_SEL */ "", 75150 /* TOP_CORE_LDO_CTRL */ "", 75151 /* TOP_CORE_PLL0_CTRL_0 */ "", 75152 /* TOP_CORE_PLL0_CTRL_1 */ "", 75153 /* TOP_CORE_PLL0_CTRL_2 */ "", 75154 /* TOP_CORE_PLL0_CTRL_3 */ "", 75155 /* TOP_CORE_PLL0_CTRL_4 */ "", 75156 /* TOP_CORE_PLL0_CTRL_5 */ "", 75157 /* TOP_CORE_PLL0_CTRL_6 */ "", 75158 /* TOP_CORE_PLL0_CTRL_7 */ "", 75159 /* TOP_CORE_PLL0_CTRL_8 */ "", 75160 /* TOP_CORE_PLL0_CTRL_9 */ "", 75161 /* TOP_CORE_PLL0_CTRL_10 */ "", 75162 /* TOP_CORE_PLL0_CTRL_11 */ "", 75163 /* TOP_CORE_PLL0_CTRL_REGISTER_0 */ "", 75164 /* TOP_CORE_PLL0_CTRL_REGISTER_1 */ "", 75165 /* TOP_CORE_PLL0_CTRL_REGISTER_2 */ "", 75166 /* TOP_CORE_PLL0_CTRL_REGISTER_3 */ "", 75167 /* TOP_CORE_PLL0_CTRL_REGISTER_4 */ "", 75168 /* TOP_CORE_PLL0_CTRL_REGISTER_5 */ "", 75169 /* TOP_CORE_PLL0_CTRL_REGISTER_6 */ "", 75170 /* TOP_CORE_PLL0_STATUS */ "", 75171 /* TOP_CORE_PLL1_CTRL_0 */ "", 75172 /* TOP_CORE_PLL1_CTRL_1 */ "", 75173 /* TOP_CORE_PLL1_CTRL_2 */ "", 75174 /* TOP_CORE_PLL1_CTRL_3 */ "", 75175 /* TOP_CORE_PLL1_CTRL_4 */ "", 75176 /* TOP_CORE_PLL1_STATUS */ "", 75177 /* TOP_CORE_PLL_CTRL0 */ "", 75178 /* TOP_CORE_PLL_CTRL1 */ "", 75179 /* TOP_CORE_PLL_CTRL2 */ "", 75180 /* TOP_CORE_PLL_CTRL3 */ "", 75181 /* TOP_CORE_PLL_CTRL4 */ "", 75182 /* TOP_CORE_PLL_CTRL5 */ "", 75183 /* TOP_CORE_PLL_CTRL6 */ "", 75184 /* TOP_CORE_PLL_CTRL7 */ "", 75185 /* TOP_CORE_PLL_CTRL8 */ "", 75186 /* TOP_CORE_PLL_CTRL9 */ "", 75187 /* TOP_CORE_PLL_CTRL_0 */ "", 75188 /* TOP_CORE_PLL_CTRL_1 */ "", 75189 /* TOP_CORE_PLL_CTRL_2 */ "", 75190 /* TOP_CORE_PLL_CTRL_3 */ "", 75191 /* TOP_CORE_PLL_CTRL_4 */ "", 75192 /* TOP_CORE_PLL_CTRL_5 */ "", 75193 /* TOP_CORE_PLL_STATUS */ "", 75194 /* TOP_CORE_PLL_STATUS_1 */ "", 75195 /* TOP_CPU2TAP_MEM_TM */ "", 75196 /* TOP_CTRL_CONFIG */ "", 75197 /* TOP_DDR_PLL0_CTRL_REGISTER_0 */ "", 75198 /* TOP_DDR_PLL0_CTRL_REGISTER_1 */ "", 75199 /* TOP_DDR_PLL0_CTRL_REGISTER_2 */ "", 75200 /* TOP_DDR_PLL0_CTRL_REGISTER_3 */ "", 75201 /* TOP_DDR_PLL0_CTRL_REGISTER_4 */ "", 75202 /* TOP_DDR_PLL0_CTRL_REGISTER_5 */ "", 75203 /* TOP_DDR_PLL0_STATUS */ "", 75204 /* TOP_DEV_REV_ID */ "", 75205 /* TOP_DPLL_LDO_CTRL */ "", 75206 /* TOP_FREQUENCY_SWITCH_STATUS */ "", 75207 /* TOP_FREQUENCY_SWITCH_STATUS_0 */ "", 75208 /* TOP_FREQUENCY_SWITCH_STATUS_1 */ "", 75209 /* TOP_FUNC_DEBUG_STATUS_0 */ "", 75210 /* TOP_FUNC_DEBUG_STATUS_1 */ "", 75211 /* TOP_FUNC_DEBUG_STATUS_SEL */ "", 75212 /* TOP_GMII_IO_CTRL */ "", 75213 /* TOP_GPHY_ENERGY_DET_APD */ "", 75214 /* TOP_GPHY_ENERGY_DET_MASKED */ "", 75215 /* TOP_GPHY_ENERGY_DET_RAW */ "", 75216 /* TOP_GPHY_INTR_EN */ "", 75217 /* TOP_GPHY_INTR_STS */ "", 75218 /* TOP_GPIO_HYS_EN_CTRL */ "", 75219 /* TOP_GPIO_PULL_CTRL */ "", 75220 /* TOP_GPIO_SEL0_CTRL */ "", 75221 /* TOP_GPIO_SEL1_CTRL */ "", 75222 /* TOP_GPIO_SEL2_CTRL */ "", 75223 /* TOP_GPIO_SLEW_CTRL */ "", 75224 /* TOP_HW_TAP_CONTROL */ "", 75225 /* TOP_HW_TAP_MEM_DEBUG */ "", 75226 /* TOP_HW_TAP_MEM_ECC_CTRL */ "", 75227 /* TOP_HW_TAP_MEM_ECC_CTRL1 */ "", 75228 /* TOP_HW_TAP_MEM_ECC_CTRL_0 */ "", 75229 /* TOP_HW_TAP_MEM_ECC_CTRL_1 */ "", 75230 /* TOP_HW_TAP_MEM_ECC_STATUS */ "", 75231 /* TOP_HW_TAP_MEM_IF_ECC_CTRL */ "", 75232 /* TOP_HW_TAP_MEM_OTP_ECC_CTRL */ "", 75233 /* TOP_HW_TAP_READ_VAILD_DEBUG_STATUS */ "", 75234 /* TOP_HW_TAP_READ_VALID_DEBUG_STATUS */ "", 75235 /* TOP_INTR_STATUS */ "", 75236 /* TOP_INT_REV_ID_REG */ "", 75237 /* TOP_IPROC_GPIO_CONTROL */ "", 75238 /* TOP_IPROC_PLL_CTRL_0 */ "", 75239 /* TOP_IPROC_PLL_CTRL_1 */ "", 75240 /* TOP_IPROC_PLL_CTRL_2 */ "", 75241 /* TOP_IPROC_PLL_CTRL_3 */ "", 75242 /* TOP_IPROC_PLL_CTRL_4 */ "", 75243 /* TOP_IPROC_PLL_CTRL_5 */ "", 75244 /* TOP_IPROC_PLL_CTRL_6 */ "", 75245 /* TOP_IPROC_PLL_CTRL_7 */ "", 75246 /* TOP_IPROC_PLL_CTRL_8 */ "", 75247 /* TOP_IPROC_PLL_CTRL_9 */ "", 75248 /* TOP_IPROC_PLL_CTRL_10 */ "", 75249 /* TOP_IPROC_PLL_CTRL_11 */ "", 75250 /* TOP_IPROC_PLL_STATUS */ "", 75251 /* TOP_L1_RCVD_CLK_BKUP_CTRL */ "", 75252 /* TOP_L1_RCVD_CLK_CONTROL */ "", 75253 /* TOP_L1_RCVD_CLK_CTRL */ "", 75254 /* TOP_L1_RCVD_CLK_VALID_STATUS_0 */ "", 75255 /* TOP_L1_RCVD_CLK_VALID_STATUS_1 */ "", 75256 /* TOP_L1_RCVD_CLK_VALID_STATUS_2 */ "", 75257 /* TOP_L1_RCVD_CLK_VALID_STATUS_3 */ "", 75258 /* TOP_L1_RCVD_CLK_VALID_STATUS_4 */ "", 75259 /* TOP_L1_RCVD_CLK_VALID_STATUS_5 */ "", 75260 /* TOP_L1_RCVD_CLK_VALID_STATUS_6 */ "", 75261 /* TOP_L1_RCVD_CLK_VALID_STATUS_7 */ "", 75262 /* TOP_L1_SYNCE_CLK_LINK_STATUS_1 */ "", 75263 /* TOP_L1_SYNCE_CLK_LINK_STATUS_2 */ "", 75264 /* TOP_LCPLL_SOFT_RESET_REG */ "", 75265 /* TOP_LOS_SEL_REG */ "", 75266 /* TOP_LVM_CONTROL */ "", 75267 /* TOP_MASTER_LCPLL_FBDIV_CTRL_0 */ "", 75268 /* TOP_MASTER_LCPLL_FBDIV_CTRL_1 */ "", 75269 /* TOP_MASTER_LCPLL_SAMPLE_DIV_CTRL */ "", 75270 /* TOP_MBIST_MEM0_TM_CTRL */ "", 75271 /* TOP_MBIST_MEM1_TM_CTRL */ "", 75272 /* TOP_MCS_PLL_CTRL_0 */ "", 75273 /* TOP_MCS_PLL_CTRL_1 */ "", 75274 /* TOP_MCS_PLL_CTRL_2 */ "", 75275 /* TOP_MCS_PLL_CTRL_3 */ "", 75276 /* TOP_MCS_PLL_CTRL_4 */ "", 75277 /* TOP_MCS_PLL_CTRL_5 */ "", 75278 /* TOP_MCS_PLL_CTRL_6 */ "", 75279 /* TOP_MCS_PLL_STATUS */ "", 75280 /* TOP_MEM_PWR_DWN_BITMAP0_STATUS */ "", 75281 /* TOP_MEM_PWR_DWN_BITMAP1_STATUS */ "", 75282 /* TOP_MEM_PWR_DWN_CTRL_CONFIG */ "", 75283 /* TOP_MISC_CONTROL */ "", 75284 /* TOP_MISC_CONTROL_0 */ "", 75285 /* TOP_MISC_CONTROL_1 */ "", 75286 /* TOP_MISC_CONTROL_2 */ "", 75287 /* TOP_MISC_CONTROL_3 */ "", 75288 /* TOP_MISC_CONTROL_4 */ "", 75289 /* TOP_MISC_CONTROL_5 */ "", 75290 /* TOP_MISC_GENERIC_CONTROL */ "", 75291 /* TOP_MISC_GENERIC_STATUS */ "", 75292 /* TOP_MISC_STATUS */ "", 75293 /* TOP_MISC_STATUS_0 */ "", 75294 /* TOP_MISC_STATUS_1 */ "", 75295 /* TOP_MISC_STATUS_2 */ "", 75296 /* TOP_MMU_DDR_PHY_CTRL */ "", 75297 /* TOP_MMU_PLL1_CTRL0 */ "", 75298 /* TOP_MMU_PLL1_CTRL1 */ "", 75299 /* TOP_MMU_PLL1_CTRL2 */ "", 75300 /* TOP_MMU_PLL1_CTRL3 */ "", 75301 /* TOP_MMU_PLL1_SSC_CTRL */ "", 75302 /* TOP_MMU_PLL2_CTRL0 */ "", 75303 /* TOP_MMU_PLL2_CTRL1 */ "", 75304 /* TOP_MMU_PLL2_CTRL2 */ "", 75305 /* TOP_MMU_PLL2_CTRL3 */ "", 75306 /* TOP_MMU_PLL2_SSC_CTRL */ "", 75307 /* TOP_MMU_PLL3_CTRL0 */ "", 75308 /* TOP_MMU_PLL3_CTRL1 */ "", 75309 /* TOP_MMU_PLL3_CTRL2 */ "", 75310 /* TOP_MMU_PLL3_CTRL3 */ "", 75311 /* TOP_MMU_PLL3_SSC_CTRL */ "", 75312 /* TOP_MMU_PLL_INIT */ "", 75313 /* TOP_MMU_PLL_STATUS0 */ "", 75314 /* TOP_MMU_PLL_STATUS1 */ "", 75315 /* TOP_OOBFC_CONTROL */ "", 75316 /* TOP_OSC_COUNT_STAT */ "", 75317 /* TOP_OTP_LDO_CTRL */ "", 75318 /* TOP_PARALLEL_LED_CTRL */ "", 75319 /* TOP_PARALLEL_LED_FAULT_STATUS_0 */ "", 75320 /* TOP_PARALLEL_LED_FAULT_STATUS_1 */ "", 75321 /* TOP_PARALLEL_LED_FAULT_STATUS_MIX */ "", 75322 /* TOP_PLL_BYP_AND_REFCLK_CONTROL */ "", 75323 /* TOP_PM_CLK_TERMINATION */ "", 75324 /* TOP_PM_HIGH_V_DISABLE */ "", 75325 /* TOP_PM_PORT_EN_STATUS_0 */ "", 75326 /* TOP_PM_PORT_EN_STATUS_1 */ "", 75327 /* TOP_PM_PORT_EN_STATUS_2 */ "", 75328 /* TOP_PM_PORT_EN_STATUS_3 */ "", 75329 /* TOP_PM_PORT_EN_STATUS_4 */ "", 75330 /* TOP_PM_PORT_EN_STATUS_5 */ "", 75331 /* TOP_PM_PORT_EN_STATUS_6 */ "", 75332 /* TOP_PM_PORT_EN_STATUS_7 */ "", 75333 /* TOP_PM_PORT_EN_STATUS_8 */ "", 75334 /* TOP_PP_PLL_CTRL_0 */ "", 75335 /* TOP_PP_PLL_CTRL_1 */ "", 75336 /* TOP_PP_PLL_CTRL_2 */ "", 75337 /* TOP_PP_PLL_CTRL_3 */ "", 75338 /* TOP_PP_PLL_CTRL_4 */ "", 75339 /* TOP_PP_PLL_STATUS */ "", 75340 /* TOP_PVTMON_0_CTRL_0 */ "", 75341 /* TOP_PVTMON_0_CTRL_1 */ "", 75342 /* TOP_PVTMON_0_INTR_THRESHOLD */ "", 75343 /* TOP_PVTMON_10_INTR_THRESHOLD */ "", 75344 /* TOP_PVTMON_11_INTR_THRESHOLD */ "", 75345 /* TOP_PVTMON_12_INTR_THRESHOLD */ "", 75346 /* TOP_PVTMON_13_17_CTRL_0 */ "", 75347 /* TOP_PVTMON_13_17_CTRL_1 */ "", 75348 /* TOP_PVTMON_13_INTR_THRESHOLD */ "", 75349 /* TOP_PVTMON_14_INTR_THRESHOLD */ "", 75350 /* TOP_PVTMON_15_INTR_THRESHOLD */ "", 75351 /* TOP_PVTMON_1_CTRL_0 */ "", 75352 /* TOP_PVTMON_1_CTRL_1 */ "", 75353 /* TOP_PVTMON_1_INTR_THRESHOLD */ "", 75354 /* TOP_PVTMON_2_1_0_DAC_DATA */ "", 75355 /* TOP_PVTMON_2_CTRL_0 */ "", 75356 /* TOP_PVTMON_2_CTRL_1 */ "", 75357 /* TOP_PVTMON_2_INTR_THRESHOLD */ "", 75358 /* TOP_PVTMON_3_CTRL_0 */ "", 75359 /* TOP_PVTMON_3_CTRL_1 */ "", 75360 /* TOP_PVTMON_3_INTR_THRESHOLD */ "", 75361 /* TOP_PVTMON_4_CTRL_0 */ "", 75362 /* TOP_PVTMON_4_CTRL_1 */ "", 75363 /* TOP_PVTMON_4_INTR_THRESHOLD */ "", 75364 /* TOP_PVTMON_5_4_3_DAC_DATA */ "", 75365 /* TOP_PVTMON_5_INTR_THRESHOLD */ "", 75366 /* TOP_PVTMON_6_INTR_THRESHOLD */ "", 75367 /* TOP_PVTMON_7_6_DAC_DATA */ "", 75368 /* TOP_PVTMON_7_INTR_THRESHOLD */ "", 75369 /* TOP_PVTMON_8_INTR_THRESHOLD */ "", 75370 /* TOP_PVTMON_9_INTR_THRESHOLD */ "", 75371 /* TOP_PVTMON_CALIBRATION */ "", 75372 /* TOP_PVTMON_CTRL_0 */ "", 75373 /* TOP_PVTMON_CTRL_1 */ "", 75374 /* TOP_PVTMON_CTRL_2 */ "", 75375 /* TOP_PVTMON_CTRL_3 */ "", 75376 /* TOP_PVTMON_INTR_MASK */ "", 75377 /* TOP_PVTMON_INTR_MASK_0 */ "", 75378 /* TOP_PVTMON_INTR_STATUS */ "", 75379 /* TOP_PVTMON_INTR_STATUS_0 */ "", 75380 /* TOP_PVTMON_MASK */ "", 75381 /* TOP_PVTMON_RESULT_0 */ "", 75382 /* TOP_PVTMON_RESULT_1 */ "", 75383 /* TOP_PVTMON_RESULT_2 */ "", 75384 /* TOP_PVTMON_RESULT_3 */ "", 75385 /* TOP_PVTMON_RESULT_4 */ "", 75386 /* TOP_PVTMON_RESULT_5 */ "", 75387 /* TOP_PVTMON_RESULT_6 */ "", 75388 /* TOP_PVTMON_RESULT_7 */ "", 75389 /* TOP_PVTMON_RESULT_8 */ "", 75390 /* TOP_PVTMON_RESULT_9 */ "", 75391 /* TOP_PVTMON_RESULT_10 */ "", 75392 /* TOP_PVTMON_RESULT_11 */ "", 75393 /* TOP_PVTMON_RESULT_12 */ "", 75394 /* TOP_PVTMON_RESULT_13 */ "", 75395 /* TOP_PVTMON_RESULT_14 */ "", 75396 /* TOP_PVTMON_RESULT_15 */ "", 75397 /* TOP_PVTMON_VDAC_DATA */ "", 75398 /* TOP_QGPHY_CTRL_0 */ "", 75399 /* TOP_QGPHY_CTRL_1 */ "", 75400 /* TOP_QGPHY_CTRL_2 */ "", 75401 /* TOP_QSGMII2X_CTRL */ "", 75402 /* TOP_QUAD0_LDO_CTRL */ "", 75403 /* TOP_QUAD0_MDIO_CONFIG_0 */ "", 75404 /* TOP_QUAD0_MDIO_CONFIG_1 */ "", 75405 /* TOP_QUAD0_MDIO_CONFIG_2 */ "", 75406 /* TOP_QUAD1_LDO_CTRL */ "", 75407 /* TOP_QUAD1_MDIO_CONFIG_0 */ "", 75408 /* TOP_QUAD1_MDIO_CONFIG_1 */ "", 75409 /* TOP_QUAD1_MDIO_CONFIG_2 */ "", 75410 /* TOP_QUAD2_LDO_CTRL */ "", 75411 /* TOP_QUAD3_LDO_CTRL */ "", 75412 /* TOP_RESCAL0_CTRL */ "", 75413 /* TOP_RESCAL0_RESULT_0 */ "", 75414 /* TOP_RESCAL0_RESULT_1 */ "", 75415 /* TOP_RESCAL1_CTRL */ "", 75416 /* TOP_RESCAL1_RESULT_0 */ "", 75417 /* TOP_RESCAL1_RESULT_1 */ "", 75418 /* TOP_RESCAL2_CTRL */ "", 75419 /* TOP_RESCAL2_RESULT_0 */ "", 75420 /* TOP_RESCAL2_RESULT_1 */ "", 75421 /* TOP_RESCAL3_CTRL */ "", 75422 /* TOP_RESCAL3_RESULT_0 */ "", 75423 /* TOP_RESCAL3_RESULT_1 */ "", 75424 /* TOP_RESCAL_0_CONTROL */ "", 75425 /* TOP_RESCAL_0_STATUS_0 */ "", 75426 /* TOP_RESCAL_0_STATUS_1 */ "", 75427 /* TOP_RESCAL_1_CONTROL */ "", 75428 /* TOP_RESCAL_1_STATUS_0 */ "", 75429 /* TOP_RESCAL_1_STATUS_1 */ "", 75430 /* TOP_RESCAL_2_CONTROL */ "", 75431 /* TOP_RESCAL_2_STATUS_0 */ "", 75432 /* TOP_RESCAL_2_STATUS_1 */ "", 75433 /* TOP_RESCAL_3_CONTROL */ "", 75434 /* TOP_RESCAL_3_STATUS_0 */ "", 75435 /* TOP_RESCAL_3_STATUS_1 */ "", 75436 /* TOP_RESCAL_4_CONTROL */ "", 75437 /* TOP_RESCAL_4_STATUS_0 */ "", 75438 /* TOP_RESCAL_4_STATUS_1 */ "", 75439 /* TOP_RESCAL_5_STATUS_0 */ "", 75440 /* TOP_RESCAL_5_STATUS_1 */ "", 75441 /* TOP_RESCAL_6_STATUS_0 */ "", 75442 /* TOP_RESCAL_6_STATUS_1 */ "", 75443 /* TOP_RESCAL_7_STATUS_0 */ "", 75444 /* TOP_RESCAL_7_STATUS_1 */ "", 75445 /* TOP_RESCAL_8_STATUS_0 */ "", 75446 /* TOP_RESCAL_8_STATUS_1 */ "", 75447 /* TOP_RESCAL_CONTROL */ "", 75448 /* TOP_RESCAL_STATUS_0 */ "", 75449 /* TOP_RESCAL_STATUS_1 */ "", 75450 /* TOP_RING_OSC_CTRL */ "", 75451 /* TOP_RING_OSC_V1P8_CTRL */ "", 75452 /* TOP_SDIO_MISC_CONTROL */ "", 75453 /* TOP_SERDES_LCPLL_FBDIV_CTRL_0 */ "", 75454 /* TOP_SERDES_LCPLL_FBDIV_CTRL_1 */ "", 75455 /* TOP_SERDES_LCPLL_SAMPLE_DIV_CTRL */ "", 75456 /* TOP_SGMII_CTRL_REG */ "", 75457 /* TOP_SGMII_STATUS0_REG */ "", 75458 /* TOP_SGMII_STATUS1_REG */ "", 75459 /* TOP_SOFT_RESET_REG */ "", 75460 /* TOP_SOFT_RESET_REG_2 */ "", 75461 /* TOP_SOFT_RESET_REG_3 */ "", 75462 /* TOP_SOFT_RESET_REG_4 */ "", 75463 /* TOP_SPARE_CTRL0 */ "", 75464 /* TOP_SPARE_CTRL1 */ "", 75465 /* TOP_SRAM_VTMON_CTRL */ "", 75466 /* TOP_STRAP_STATUS */ "", 75467 /* TOP_STRAP_STATUS_1 */ "", 75468 /* TOP_SWITCH_FEATURE_ENABLE */ "", 75469 /* TOP_SWITCH_FEATURE_ENABLE_0 */ "", 75470 /* TOP_SWITCH_FEATURE_ENABLE_1 */ "", 75471 /* TOP_SWITCH_FEATURE_ENABLE_2 */ "", 75472 /* TOP_SWITCH_FEATURE_ENABLE_3 */ "", 75473 /* TOP_SWITCH_FEATURE_ENABLE_4 */ "", 75474 /* TOP_SWITCH_FEATURE_ENABLE_5 */ "", 75475 /* TOP_SWITCH_FEATURE_ENABLE_6 */ "", 75476 /* TOP_SWITCH_FEATURE_ENABLE_7 */ "", 75477 /* TOP_SW_BOND_OVRD_CTRL0 */ "", 75478 /* TOP_SW_BOND_OVRD_CTRL1 */ "", 75479 /* TOP_SYNCE_CTRL */ "", 75480 /* TOP_TAP_CONTROL */ "", 75481 /* TOP_TDPLL_SOFT_RESET_REG */ "", 75482 /* TOP_THERMAL_PVTMON_CALIBRATION */ "", 75483 /* TOP_THERMAL_PVTMON_CTRL */ "", 75484 /* TOP_THERMAL_PVTMON_CTRL_2 */ "", 75485 /* TOP_THERMAL_PVTMON_RESULT_0 */ "", 75486 /* TOP_THERMAL_PVTMON_RESULT_1 */ "", 75487 /* TOP_THERMAL_PVTMON_RESULT_2 */ "", 75488 /* TOP_THERMAL_PVTMON_RESULT_3 */ "", 75489 /* TOP_TIME_SYNC_PLL_CTRL_REGISTER_0 */ "", 75490 /* TOP_TIME_SYNC_PLL_CTRL_REGISTER_1 */ "", 75491 /* TOP_TIME_SYNC_PLL_CTRL_REGISTER_2 */ "", 75492 /* TOP_TIME_SYNC_PLL_CTRL_REGISTER_3 */ "", 75493 /* TOP_TIME_SYNC_PLL_CTRL_REGISTER_4 */ "", 75494 /* TOP_TIME_SYNC_PLL_CTRL_REGISTER_5 */ "", 75495 /* TOP_TIME_SYNC_PLL_STATUS */ "", 75496 /* TOP_TMON0_RESULT */ "", 75497 /* TOP_TMON1_RESULT */ "", 75498 /* TOP_TMON2_RESULT */ "", 75499 /* TOP_TMON_CTRL */ "", 75500 /* TOP_TMON_CTRL_0 */ "", 75501 /* TOP_TMON_CTRL_1 */ "", 75502 /* TOP_TOP_CORE_PLL_STATUS_1 */ "", 75503 /* TOP_TOP_CORE_PLL_STATUS_2 */ "", 75504 /* TOP_TOP_CORE_PLL_STATUS_3 */ "", 75505 /* TOP_TSCE_CONFIG */ "", 75506 /* TOP_TSC_0_RESOLVED_SPEED_STATUS */ "", 75507 /* TOP_TSC_0_RESOLVED_SPEED_STATUS_1 */ "", 75508 /* TOP_TSC_10_RESOLVED_SPEED_STATUS */ "", 75509 /* TOP_TSC_11_RESOLVED_SPEED_STATUS */ "", 75510 /* TOP_TSC_12_RESOLVED_SPEED_STATUS */ "", 75511 /* TOP_TSC_13_RESOLVED_SPEED_STATUS */ "", 75512 /* TOP_TSC_14_RESOLVED_SPEED_STATUS */ "", 75513 /* TOP_TSC_15_RESOLVED_SPEED_STATUS */ "", 75514 /* TOP_TSC_16_RESOLVED_SPEED_STATUS */ "", 75515 /* TOP_TSC_17_RESOLVED_SPEED_STATUS */ "", 75516 /* TOP_TSC_18_RESOLVED_SPEED_STATUS */ "", 75517 /* TOP_TSC_19_RESOLVED_SPEED_STATUS */ "", 75518 /* TOP_TSC_1_RESOLVED_SPEED_STATUS */ "", 75519 /* TOP_TSC_1_RESOLVED_SPEED_STATUS_1 */ "", 75520 /* TOP_TSC_20_RESOLVED_SPEED_STATUS */ "", 75521 /* TOP_TSC_21_RESOLVED_SPEED_STATUS */ "", 75522 /* TOP_TSC_22_RESOLVED_SPEED_STATUS */ "", 75523 /* TOP_TSC_23_RESOLVED_SPEED_STATUS */ "", 75524 /* TOP_TSC_24_RESOLVED_SPEED_STATUS */ "", 75525 /* TOP_TSC_25_RESOLVED_SPEED_STATUS */ "", 75526 /* TOP_TSC_26_RESOLVED_SPEED_STATUS */ "", 75527 /* TOP_TSC_27_RESOLVED_SPEED_STATUS */ "", 75528 /* TOP_TSC_28_RESOLVED_SPEED_STATUS */ "", 75529 /* TOP_TSC_29_RESOLVED_SPEED_STATUS */ "", 75530 /* TOP_TSC_2_RESOLVED_SPEED_STATUS */ "", 75531 /* TOP_TSC_2_RESOLVED_SPEED_STATUS_1 */ "", 75532 /* TOP_TSC_30_RESOLVED_SPEED_STATUS */ "", 75533 /* TOP_TSC_31_RESOLVED_SPEED_STATUS */ "", 75534 /* TOP_TSC_32_RESOLVED_SPEED_STATUS */ "", 75535 /* TOP_TSC_3_RESOLVED_SPEED_STATUS */ "", 75536 /* TOP_TSC_4_RESOLVED_SPEED_STATUS */ "", 75537 /* TOP_TSC_5_RESOLVED_SPEED_STATUS */ "", 75538 /* TOP_TSC_6_RESOLVED_SPEED_STATUS */ "", 75539 /* TOP_TSC_7_RESOLVED_SPEED_STATUS */ "", 75540 /* TOP_TSC_8_RESOLVED_SPEED_STATUS */ "", 75541 /* TOP_TSC_9_RESOLVED_SPEED_STATUS */ "", 75542 /* TOP_TSC_AFE_PLL_STATUS */ "", 75543 /* TOP_TSC_AFE_PLL_STATUS_1 */ "", 75544 /* TOP_TSC_DISABLE */ "", 75545 /* TOP_TSC_DISABLE_STATUS */ "", 75546 /* TOP_TSC_ENABLE */ "", 75547 /* TOP_TSC_ENABLE_1 */ "", 75548 /* TOP_TSC_ENABLE_2 */ "", 75549 /* TOP_TSC_SYNCE_DIV_CONFIG_0 */ "", 75550 /* TOP_TSC_SYNCE_DIV_CONFIG_1 */ "", 75551 /* TOP_TS_GPIO_0_INPUT_EVENT_DLY_CTRL */ "", 75552 /* TOP_TS_GPIO_0_OUTPUT_EVENT_DLY_CTRL */ "", 75553 /* TOP_TS_GPIO_1_INPUT_EVENT_DLY_CTRL */ "", 75554 /* TOP_TS_GPIO_1_OUTPUT_EVENT_DLY_CTRL */ "", 75555 /* TOP_TS_GPIO_2_INPUT_EVENT_DLY_CTRL */ "", 75556 /* TOP_TS_GPIO_2_OUTPUT_EVENT_DLY_CTRL */ "", 75557 /* TOP_TS_GPIO_3_INPUT_EVENT_DLY_CTRL */ "", 75558 /* TOP_TS_GPIO_3_OUTPUT_EVENT_DLY_CTRL */ "", 75559 /* TOP_TS_GPIO_4_INPUT_EVENT_DLY_CTRL */ "", 75560 /* TOP_TS_GPIO_4_OUTPUT_EVENT_DLY_CTRL */ "", 75561 /* TOP_TS_GPIO_5_INPUT_EVENT_DLY_CTRL */ "", 75562 /* TOP_TS_GPIO_5_OUTPUT_EVENT_DLY_CTRL */ "", 75563 /* TOP_TS_PLL_CTRL_0 */ "", 75564 /* TOP_TS_PLL_CTRL_1 */ "", 75565 /* TOP_TS_PLL_CTRL_2 */ "", 75566 /* TOP_TS_PLL_CTRL_3 */ "", 75567 /* TOP_TS_PLL_CTRL_4 */ "", 75568 /* TOP_TS_PLL_CTRL_5 */ "", 75569 /* TOP_TS_PLL_CTRL_6 */ "", 75570 /* TOP_TS_PLL_CTRL_7 */ "", 75571 /* TOP_TS_PLL_CTRL_8 */ "", 75572 /* TOP_TS_PLL_CTRL_9 */ "", 75573 /* TOP_TS_PLL_DITHER_FSM_CTRL_0 */ "", 75574 /* TOP_TS_PLL_DITHER_FSM_CTRL_1 */ "", 75575 /* TOP_TS_PLL_DITHER_FSM_CTRL_2 */ "", 75576 /* TOP_TS_PLL_DITHER_FSM_CTRL_3 */ "", 75577 /* TOP_TS_PLL_STATUS */ "", 75578 /* TOP_TS_TIMER_47_32_REG */ "", 75579 /* TOP_UC_TAP_CONTROL */ "", 75580 /* TOP_UC_TAP_READ_DATA */ "", 75581 /* TOP_UC_TAP_WRITE_DATA */ "", 75582 /* TOP_UPI_CTRL_0 */ "", 75583 /* TOP_UPI_CTRL_1 */ "", 75584 /* TOP_UPI_RING_OSC_V1P8_CTRL */ "", 75585 /* TOP_UPI_STATUS_0 */ "", 75586 /* TOP_UPI_STATUS_1 */ "", 75587 /* TOP_UPI_STATUS_2 */ "", 75588 /* TOP_UPI_STATUS_3 */ "", 75589 /* TOP_UPI_STATUS_4 */ "", 75590 /* TOP_UPI_STATUS_5 */ "", 75591 /* TOP_UPI_STATUS_6 */ "", 75592 /* TOP_UPI_STATUS_7 */ "", 75593 /* TOP_UPI_STATUS_8 */ "", 75594 /* TOP_UPI_STATUS_9 */ "", 75595 /* TOP_UPI_STATUS_10 */ "", 75596 /* TOP_UPI_STATUS_11 */ "", 75597 /* TOP_UPI_STATUS_12 */ "", 75598 /* TOP_UPI_STATUS_13 */ "", 75599 /* TOP_UPI_STATUS_14 */ "", 75600 /* TOP_UPI_STATUS_15 */ "", 75601 /* TOP_UPI_STATUS_16 */ "", 75602 /* TOP_UPI_STATUS_17 */ "", 75603 /* TOP_UPI_STATUS_18 */ "", 75604 /* TOP_UPI_STATUS_19 */ "", 75605 /* TOP_UPI_STATUS_20 */ "", 75606 /* TOP_UPI_STATUS_21 */ "", 75607 /* TOP_XG0_LCPLL_FBDIV_CTRL_0 */ "", 75608 /* TOP_XG0_LCPLL_FBDIV_CTRL_1 */ "", 75609 /* TOP_XG0_LCPLL_SAMPLE_DIV_CTRL */ "", 75610 /* TOP_XG1_LCPLL_FBDIV_CTRL_0 */ "", 75611 /* TOP_XG1_LCPLL_FBDIV_CTRL_1 */ "", 75612 /* TOP_XG1_LCPLL_SAMPLE_DIV_CTRL */ "", 75613 /* TOP_XGXS0_PLL_CONTROL_1 */ "", 75614 /* TOP_XGXS0_PLL_CONTROL_2 */ "", 75615 /* TOP_XGXS0_PLL_CONTROL_3 */ "", 75616 /* TOP_XGXS0_PLL_CONTROL_4 */ "", 75617 /* TOP_XGXS0_PLL_CONTROL_5 */ "", 75618 /* TOP_XGXS0_PLL_CONTROL_6 */ "", 75619 /* TOP_XGXS0_PLL_CONTROL_7 */ "", 75620 /* TOP_XGXS0_PLL_CONTROL_8 */ "", 75621 /* TOP_XGXS0_PLL_STATUS */ "", 75622 /* TOP_XGXS1_PLL_CONTROL_1 */ "", 75623 /* TOP_XGXS1_PLL_CONTROL_2 */ "", 75624 /* TOP_XGXS1_PLL_CONTROL_3 */ "", 75625 /* TOP_XGXS1_PLL_CONTROL_4 */ "", 75626 /* TOP_XGXS1_PLL_CONTROL_5 */ "", 75627 /* TOP_XGXS1_PLL_CONTROL_6 */ "", 75628 /* TOP_XGXS1_PLL_CONTROL_7 */ "", 75629 /* TOP_XGXS1_PLL_CONTROL_8 */ "", 75630 /* TOP_XGXS1_PLL_STATUS */ "", 75631 /* TOP_XGXS_MDIO_CONFIG_0 */ "", 75632 /* TOP_XGXS_MDIO_CONFIG_1 */ "", 75633 /* TOP_XGXS_MDIO_CONFIG_2 */ "", 75634 /* TOP_XGXS_MDIO_CONFIG_3 */ "", 75635 /* TOP_XGXS_MDIO_CONFIG_4 */ "", 75636 /* TOP_XGXS_MDIO_CONFIG_5 */ "", 75637 /* TOP_XGXS_MDIO_CONFIG_6 */ "", 75638 /* TOP_XGXS_MDIO_CONFIG_7 */ "", 75639 /* TOP_XGXS_MDIO_CONFIG_8 */ "", 75640 /* TOP_XGXS_MDIO_CONFIG_9 */ "", 75641 /* TOP_XGXS_MDIO_CONFIG_10 */ "", 75642 /* TOP_XGXS_MDIO_CONFIG_SGMII */ "", 75643 /* TOP_XG_PLL0_CTRL_0 */ "", 75644 /* TOP_XG_PLL0_CTRL_1 */ "", 75645 /* TOP_XG_PLL0_CTRL_2 */ "", 75646 /* TOP_XG_PLL0_CTRL_3 */ "", 75647 /* TOP_XG_PLL0_CTRL_4 */ "", 75648 /* TOP_XG_PLL0_CTRL_5 */ "", 75649 /* TOP_XG_PLL0_CTRL_6 */ "", 75650 /* TOP_XG_PLL0_CTRL_7 */ "", 75651 /* TOP_XG_PLL0_CTRL_8 */ "", 75652 /* TOP_XG_PLL0_CTRL_9 */ "", 75653 /* TOP_XG_PLL0_CTRL_10 */ "", 75654 /* TOP_XG_PLL0_CTRL_11 */ "", 75655 /* TOP_XG_PLL0_CTRL_12 */ "", 75656 /* TOP_XG_PLL0_CTRL_13 */ "", 75657 /* TOP_XG_PLL0_STATUS */ "", 75658 /* TOP_XG_PLL1_CTRL_0 */ "", 75659 /* TOP_XG_PLL1_CTRL_1 */ "", 75660 /* TOP_XG_PLL1_CTRL_2 */ "", 75661 /* TOP_XG_PLL1_CTRL_3 */ "", 75662 /* TOP_XG_PLL1_CTRL_4 */ "", 75663 /* TOP_XG_PLL1_CTRL_5 */ "", 75664 /* TOP_XG_PLL1_CTRL_6 */ "", 75665 /* TOP_XG_PLL1_CTRL_7 */ "", 75666 /* TOP_XG_PLL1_CTRL_8 */ "", 75667 /* TOP_XG_PLL1_CTRL_9 */ "", 75668 /* TOP_XG_PLL1_CTRL_10 */ "", 75669 /* TOP_XG_PLL1_CTRL_11 */ "", 75670 /* TOP_XG_PLL1_CTRL_12 */ "", 75671 /* TOP_XG_PLL1_CTRL_13 */ "", 75672 /* TOP_XG_PLL1_STATUS */ "", 75673 /* TOP_XG_PLL2_CTRL_0 */ "", 75674 /* TOP_XG_PLL2_CTRL_1 */ "", 75675 /* TOP_XG_PLL2_CTRL_2 */ "", 75676 /* TOP_XG_PLL2_CTRL_3 */ "", 75677 /* TOP_XG_PLL2_CTRL_4 */ "", 75678 /* TOP_XG_PLL2_CTRL_5 */ "", 75679 /* TOP_XG_PLL2_CTRL_6 */ "", 75680 /* TOP_XG_PLL2_CTRL_7 */ "", 75681 /* TOP_XG_PLL2_CTRL_8 */ "", 75682 /* TOP_XG_PLL2_CTRL_9 */ "", 75683 /* TOP_XG_PLL2_STATUS */ "", 75684 /* TOP_XG_PLL3_CTRL_0 */ "", 75685 /* TOP_XG_PLL3_CTRL_1 */ "", 75686 /* TOP_XG_PLL3_CTRL_2 */ "", 75687 /* TOP_XG_PLL3_CTRL_3 */ "", 75688 /* TOP_XG_PLL3_CTRL_4 */ "", 75689 /* TOP_XG_PLL3_CTRL_5 */ "", 75690 /* TOP_XG_PLL3_CTRL_6 */ "", 75691 /* TOP_XG_PLL3_CTRL_7 */ "", 75692 /* TOP_XG_PLL3_CTRL_8 */ "", 75693 /* TOP_XG_PLL3_CTRL_9 */ "", 75694 /* TOP_XG_PLL3_STATUS */ "", 75695 /* TOP_XTAL_CTRL */ "", 75696 /* TOP_XTAL_CTRL0 */ "", 75697 /* TOQEMPTY */ "", 75698 /* TOQEMPTY_64 */ "TOQEMPTY", 75699 /* TOQEMPTY_CPU_PORT_0 */ "", 75700 /* TOQEMPTY_CPU_PORT_1 */ "", 75701 /* TOQ_ACTIVATEQ */ "", 75702 /* TOQ_ACTIVATEQ_64 */ "TOQ_ACTIVATEQ", 75703 /* TOQ_ACTIVATEQ_CPU_PORT_0 */ "", 75704 /* TOQ_ACTIVATEQ_CPU_PORT_1 */ "", 75705 /* TOQ_BW_LIMITING_MIDPKT_EN */ "", 75706 /* TOQ_BW_LIMITING_MIDPKT_EN0 */ "", 75707 /* TOQ_BW_LIMITING_MIDPKT_EN1 */ "", 75708 /* TOQ_CELLHDRERRPTR */ "", 75709 /* TOQ_CELLLINKERRPTR */ "", 75710 /* TOQ_CONFIG */ "", 75711 /* TOQ_CONFIG_64 */ "TOQ_CONFIG", 75712 /* TOQ_COS_SWITCH_STATUS */ "", 75713 /* TOQ_CPQLINKERRPTR */ "", 75714 /* TOQ_DEBUG_EXT_PQE_WATERMARK */ "", 75715 /* TOQ_DEBUG_INT_PQE_WATERMARK */ "", 75716 /* TOQ_DEBUG_PQE_CREDIT */ "", 75717 /* TOQ_DEBUG_REG1 */ "", 75718 /* TOQ_DIS_IPMC_REPLICATION */ "", 75719 /* TOQ_DIS_IPMC_REPLICATION_64 */ "TOQ_DIS_IPMC_REPLICATION", 75720 /* TOQ_ECC_DEBUG */ "", 75721 /* TOQ_EG_CREDIT */ "", 75722 /* TOQ_EMPTY_DEQ_STATUS */ "", 75723 /* TOQ_ENQIPMCGRPERRPTR0 */ "", 75724 /* TOQ_ENQIPMCGRPERRPTR1 */ "", 75725 /* TOQ_ENQ_DROP_CNT */ "", 75726 /* TOQ_EP_BP_STATUS */ "", 75727 /* TOQ_EP_CREDIT */ "", 75728 /* TOQ_ERRINTR */ "", 75729 /* TOQ_ERRINTR0 */ "", 75730 /* TOQ_ERRINTR1 */ "", 75731 /* TOQ_ERRINTR0_64 */ "TOQ_ERRINTR0", 75732 /* TOQ_ERROR */ "", 75733 /* TOQ_ERROR1 */ "", 75734 /* TOQ_ERROR2 */ "", 75735 /* TOQ_ERROR1_MASK */ "", 75736 /* TOQ_ERROR2_MASK */ "", 75737 /* TOQ_ERROR_MASK */ "", 75738 /* TOQ_EXT_MEM_BW_MAP_TABLE */ "", 75739 /* TOQ_EXT_MEM_BW_TIMER_CFG */ "", 75740 /* TOQ_FAST_FLUSH */ "", 75741 /* TOQ_FATAL */ "", 75742 /* TOQ_FLUSH0 */ "", 75743 /* TOQ_FLUSH1 */ "", 75744 /* TOQ_FLUSH2 */ "", 75745 /* TOQ_FLUSH3 */ "", 75746 /* TOQ_GEN_CFG */ "", 75747 /* TOQ_GEN_CFG1 */ "", 75748 /* TOQ_INTERRUPT */ "", 75749 /* TOQ_INTERRUPT_MASK */ "", 75750 /* TOQ_IPMCERRINTR */ "", 75751 /* TOQ_IPMCGRPERRPTR0 */ "", 75752 /* TOQ_IPMCGRPERRPTR1 */ "", 75753 /* TOQ_IPMCVLANERRPTR */ "", 75754 /* TOQ_IPMC_FAST_FLUSH */ "", 75755 /* TOQ_IPMC_FAST_FLUSH_64 */ "TOQ_IPMC_FAST_FLUSH", 75756 /* TOQ_IPMC_REPLICATION_STAT */ "", 75757 /* TOQ_IPMC_REPLICATION_STAT_64 */ "TOQ_IPMC_REPLICATION_STAT", 75758 /* TOQ_LINKPHY_ENABLE */ "", 75759 /* TOQ_MC_CACHE_COUNT_DEBUG */ "", 75760 /* TOQ_MC_CACHE_DEBUG */ "", 75761 /* TOQ_MC_CFG0 */ "", 75762 /* TOQ_MC_CFG1 */ "", 75763 /* TOQ_MC_CFG2 */ "", 75764 /* TOQ_MEM_DEBUG */ "", 75765 /* TOQ_MEM_DEBUG0 */ "", 75766 /* TOQ_MEM_DEBUG1 */ "", 75767 /* TOQ_MEM_DEBUG2 */ "", 75768 /* TOQ_MEM_DEBUG3 */ "", 75769 /* TOQ_MEM_DEBUG4 */ "", 75770 /* TOQ_PKTHDR1ERRPTR */ "", 75771 /* TOQ_PKTLINKERRINTR */ "", 75772 /* TOQ_PKTLINKERRPTR */ "", 75773 /* TOQ_PORT_ACTIVATE_PIPE0 */ "", 75774 /* TOQ_PORT_ACTIVATE_PIPE1 */ "", 75775 /* TOQ_PORT_BW_CTRL */ "", 75776 /* TOQ_PORT_NOTEMPTY_PIPE0 */ "", 75777 /* TOQ_PORT_NOTEMPTY_PIPE1 */ "", 75778 /* TOQ_PORT_STATUS */ "", 75779 /* TOQ_PORT_STATUS_MASK */ "", 75780 /* TOQ_PORT_STATUS_PIPE0 */ "", 75781 /* TOQ_PORT_STATUS_PIPE1 */ "", 75782 /* TOQ_PTR_SEL_CFG */ "", 75783 /* TOQ_PTR_SEL_STATUS0 */ "", 75784 /* TOQ_PTR_SEL_STATUS1 */ "", 75785 /* TOQ_QEN_ACCOUNT_CFG */ "", 75786 /* TOQ_QUEUESTAT */ "", 75787 /* TOQ_QUEUESTAT_64 */ "TOQ_QUEUESTAT", 75788 /* TOQ_QUEUESTAT_CPU_PORT_0 */ "", 75789 /* TOQ_QUEUESTAT_CPU_PORT_1 */ "", 75790 /* TOQ_QUEUE_FLUSH0 */ "", 75791 /* TOQ_QUEUE_FLUSH1 */ "", 75792 /* TOQ_QUEUE_FLUSH2 */ "", 75793 /* TOQ_QUEUE_FLUSH3 */ "", 75794 /* TOQ_RDEFIFOERRPTR */ "", 75795 /* TOQ_RDE_THRESHOLD */ "TOQ_RDE_THRESHOLD", 75796 /* TOQ_SPARE */ "TOQ_SPARE", 75797 /* TOQ_STATUS */ "", 75798 /* TOQ_UCQDBERRPTR */ "", 75799 /* TOQ_UCQRPERRPTR */ "", 75800 /* TOQ_UCQWPERRPTR */ "", 75801 /* TOQ_UC_CACHE_COUNT_DEBUG */ "", 75802 /* TOQ_UC_CACHE_DEBUG */ "", 75803 /* TOQ_WAMULINKERRPTR */ "", 75804 /* TOQ_WLP_THROTTLE */ "TOQ_WLP_THROTTLE", 75805 /* TOS_FN_PARITY_CONTROL */ "", 75806 /* TOS_FN_PARITY_STATUS_INTR */ "", 75807 /* TOS_FN_PARITY_STATUS_NACK */ "", 75808 /* TOS_FN_RAM_DBGCTRL */ "TOS_FN_RAM_CONTROL", 75809 /* TOS_FN_RAM_DBGCTRL_PIPE0 */ "TOS_FN_RAM_CONTROL_PIPE0", 75810 /* TOS_FN_RAM_DBGCTRL_PIPE1 */ "TOS_FN_RAM_CONTROL_PIPE1", 75811 /* TOS_FN_RAM_DBGCTRL_PIPE2 */ "TOS_FN_RAM_CONTROL_PIPE2", 75812 /* TOS_FN_RAM_DBGCTRL_PIPE3 */ "TOS_FN_RAM_CONTROL_PIPE3", 75813 /* TOS_FN_RAM_DBGCTRL_PIPE4 */ "TOS_FN_RAM_CONTROL_PIPE4", 75814 /* TOS_FN_RAM_DBGCTRL_PIPE5 */ "TOS_FN_RAM_CONTROL_PIPE5", 75815 /* TOS_FN_RAM_DBGCTRL_PIPE6 */ "TOS_FN_RAM_CONTROL_PIPE6", 75816 /* TOS_FN_RAM_DBGCTRL_PIPE7 */ "TOS_FN_RAM_CONTROL_PIPE7", 75817 /* TOTALDYNCELLLIMIT */ "", 75818 /* TOTALDYNCELLRESETLIMIT */ "", 75819 /* TOTALDYNCELLSETLIMIT */ "", 75820 /* TOTALDYNCELLUSED */ "", 75821 /* TOTAL_BUFFER_COUNT */ "", 75822 /* TOTAL_BUFFER_COUNT_CELL */ "", 75823 /* TOTAL_BUFFER_COUNT_CELL_SP */ "", 75824 /* TOTAL_BUFFER_COUNT_CELL_SP_SHARED */ "", 75825 /* TOTAL_BUFFER_COUNT_PACKET */ "", 75826 /* TOTAL_BUFFER_COUNT_PACKET_SP */ "", 75827 /* TOTAL_BUFFER_COUNT_PACKET_SP_SHARED */ "", 75828 /* TOTAL_LIMIT_STATE */ "", 75829 /* TOTAL_SHARED_AVAIL_THRESH */ "", 75830 /* TOTAL_SHARED_COUNT */ "", 75831 /* TOTAL_SHARED_COUNT_CELL */ "", 75832 /* TOTAL_SHARED_COUNT_PACKET */ "", 75833 /* TOTAL_SHARED_LIMIT */ "", 75834 /* TOTAL_SHARED_LIMIT_CELL */ "", 75835 /* TOTAL_SHARED_LIMIT_PACKET */ "", 75836 /* TOT_PKT_CNT */ "", 75837 /* TOVR */ "MAC_GTxOVR", 75838 /* TPCE */ "", 75839 /* TPCE_64 */ "TPCE", 75840 /* TPCHST */ "", 75841 /* TPECFG */ "", 75842 /* TPFC0 */ "MAC_GTxPFCP0", 75843 /* TPFC1 */ "MAC_GTxPFCP1", 75844 /* TPFC2 */ "MAC_GTxPFCP2", 75845 /* TPFC3 */ "MAC_GTxPFCP3", 75846 /* TPFC4 */ "MAC_GTxPFCP4", 75847 /* TPFC5 */ "MAC_GTxPFCP5", 75848 /* TPFC6 */ "MAC_GTxPFCP6", 75849 /* TPFC7 */ "MAC_GTxPFCP7", 75850 /* TPFCOFF0 */ "CLG2MIB_GTxPFCOFF0", 75851 /* TPFCOFF1 */ "CLG2MIB_GTxPFCOFF1", 75852 /* TPFCOFF2 */ "CLG2MIB_GTxPFCOFF2", 75853 /* TPFCOFF3 */ "CLG2MIB_GTxPFCOFF3", 75854 /* TPFCOFF4 */ "CLG2MIB_GTxPFCOFF4", 75855 /* TPFCOFF5 */ "CLG2MIB_GTxPFCOFF5", 75856 /* TPFCOFF6 */ "CLG2MIB_GTxPFCOFF6", 75857 /* TPFCOFF7 */ "CLG2MIB_GTxPFCOFF7", 75858 /* TPFC_0 */ "", 75859 /* TPFC_1 */ "", 75860 /* TPFC_2 */ "", 75861 /* TPFC_3 */ "", 75862 /* TPFC_4 */ "", 75863 /* TPFC_5 */ "", 75864 /* TPFC_6 */ "", 75865 /* TPFC_7 */ "", 75866 /* TPKT */ "MAC_GTxPkt", 75867 /* TPOK */ "MAC_GTxPOK", 75868 /* TPPCFG */ "", 75869 /* TRACE_IF_DEQ_CAPT_0 */ "", 75870 /* TRACE_IF_DEQ_CAPT_1 */ "", 75871 /* TRACE_IF_DEQ_CONTROL */ "", 75872 /* TRACE_IF_DEQ_COUNTER */ "", 75873 /* TRACE_IF_DEQ_MASK_FIELD */ "", 75874 /* TRACE_IF_DEQ_VALUE_FIELD */ "", 75875 /* TRACE_IF_ENQ_CAPT_0 */ "", 75876 /* TRACE_IF_ENQ_CAPT_1 */ "", 75877 /* TRACE_IF_ENQ_CONTROL */ "", 75878 /* TRACE_IF_ENQ_COUNTER */ "", 75879 /* TRACE_IF_ENQ_MASK_FIELD */ "", 75880 /* TRACE_IF_ENQ_VALUE_FIELD */ "", 75881 /* TREPLY */ "XLMIB_GTxReply", 75882 /* TRILL_DROP_CONTROL */ "", 75883 /* TRILL_RBRIDGE_NICKNAME_SELECT */ "", 75884 /* TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_CONTROL */ "", 75885 /* TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_STATUS_INTR */ "", 75886 /* TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_STATUS_NACK */ "", 75887 /* TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_CONTROL */ "", 75888 /* TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_STATUS_INTR */ "", 75889 /* TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_STATUS_NACK */ "", 75890 /* TRILL_RX_PKTS_PARITY_CONTROL */ "", 75891 /* TRILL_RX_PKTS_PARITY_STATUS_INTR */ "", 75892 /* TRILL_RX_PKTS_PARITY_STATUS_NACK */ "", 75893 /* TRPKT */ "MAC_GTxRPKT", 75894 /* TRUNK_BITMAP_ECC_STATUS */ "", 75895 /* TRUNK_BITMAP_TABLE_PARITY_CONTROL */ "", 75896 /* TRUNK_BITMAP_TABLE_PARITY_STATUS */ "", 75897 /* TRUNK_BITMAP_TABLE_PARITY_STATUS_INTR */ "", 75898 /* TRUNK_BITMAP_TABLE_PARITY_STATUS_NACK */ "", 75899 /* TRUNK_EGR_MASK_PARITY_CONTROL */ "", 75900 /* TRUNK_EGR_MASK_PARITY_STATUS */ "", 75901 /* TRUNK_EGR_MASK_PARITY_STATUS_INTR */ "", 75902 /* TRUNK_EGR_MASK_PARITY_STATUS_NACK */ "", 75903 /* TRUNK_GROUP_PARITY_CONTROL */ "", 75904 /* TRUNK_GROUP_PARITY_STATUS */ "", 75905 /* TRUNK_GROUP_PARITY_STATUS_INTR */ "", 75906 /* TRUNK_GROUP_PARITY_STATUS_NACK */ "", 75907 /* TRUNK_MEMBER_PARITY_CONTROL */ "", 75908 /* TRUNK_MEMBER_PARITY_STATUS_INTR */ "", 75909 /* TRUNK_MEMBER_PARITY_STATUS_NACK */ "", 75910 /* TRUNK_RAND_LB_SEED */ "", 75911 /* TRUNK_RAND_LB_SEED_PIPE0 */ "", 75912 /* TRUNK_RAND_LB_SEED_PIPE1 */ "", 75913 /* TRUNK_RAND_LB_SEED_PIPE2 */ "", 75914 /* TRUNK_RAND_LB_SEED_PIPE3 */ "", 75915 /* TRUNK_RAND_LB_SEED_PIPE4 */ "", 75916 /* TRUNK_RAND_LB_SEED_PIPE5 */ "", 75917 /* TRUNK_RAND_LB_SEED_PIPE6 */ "", 75918 /* TRUNK_RAND_LB_SEED_PIPE7 */ "", 75919 /* TS125M1 */ "", 75920 /* TS125M2 */ "", 75921 /* TSCL */ "MAC_GTxSCL", 75922 /* TSOFPH_CID_0 */ "", 75923 /* TSOFPH_CID_1 */ "", 75924 /* TSOFPH_CID_2 */ "", 75925 /* TSOFPH_CID_3 */ "", 75926 /* TSOFPH_CID_4 */ "", 75927 /* TSOFPH_CID_5 */ "", 75928 /* TSOFPH_CID_6 */ "", 75929 /* TSOFPH_CID_7 */ "", 75930 /* TSOFPH_CID_8 */ "", 75931 /* TSOFPH_CID_9 */ "", 75932 /* TSOFPH_CID_10 */ "", 75933 /* TSOFPH_CID_11 */ "", 75934 /* TSOFPH_CID_12 */ "", 75935 /* TSOFPH_CID_13 */ "", 75936 /* TSOFPH_CID_14 */ "", 75937 /* TSOFPH_CID_15 */ "", 75938 /* TSOSPER1_CID_0 */ "", 75939 /* TSOSPER1_CID_1 */ "", 75940 /* TSOSPER1_CID_2 */ "", 75941 /* TSOSPER1_CID_3 */ "", 75942 /* TSOSPER1_CID_4 */ "", 75943 /* TSOSPER1_CID_5 */ "", 75944 /* TSOSPER1_CID_6 */ "", 75945 /* TSOSPER1_CID_7 */ "", 75946 /* TSOSPER1_CID_8 */ "", 75947 /* TSOSPER1_CID_9 */ "", 75948 /* TSOSPER1_CID_10 */ "", 75949 /* TSOSPER1_CID_11 */ "", 75950 /* TSOSPER1_CID_12 */ "", 75951 /* TSOSPER1_CID_13 */ "", 75952 /* TSOSPER1_CID_14 */ "", 75953 /* TSOSPER1_CID_15 */ "", 75954 /* TSOSPER2_CID_0 */ "", 75955 /* TSOSPER2_CID_1 */ "", 75956 /* TSOSPER2_CID_2 */ "", 75957 /* TSOSPER2_CID_3 */ "", 75958 /* TSOSPER2_CID_4 */ "", 75959 /* TSOSPER2_CID_5 */ "", 75960 /* TSOSPER2_CID_6 */ "", 75961 /* TSOSPER2_CID_7 */ "", 75962 /* TSOSPER2_CID_8 */ "", 75963 /* TSOSPER2_CID_9 */ "", 75964 /* TSOSPER2_CID_10 */ "", 75965 /* TSOSPER2_CID_11 */ "", 75966 /* TSOSPER2_CID_12 */ "", 75967 /* TSOSPER2_CID_13 */ "", 75968 /* TSOSPER2_CID_14 */ "", 75969 /* TSOSPER2_CID_15 */ "", 75970 /* TSPARE0 */ "CLG2MIB_GTxSPARE0", 75971 /* TSPARE1 */ "CLG2MIB_GTxSPARE1", 75972 /* TSPARE2 */ "CLG2MIB_GTxSPARE2", 75973 /* TSPARE3 */ "CLG2MIB_GTxSPARE3", 75974 /* TS_CONTROL */ "", 75975 /* TS_CONTROL_1 */ "", 75976 /* TS_CONTROL_2 */ "", 75977 /* TS_STATUS_CNTRL */ "", 75978 /* TS_TO_CORE_SYNC_ENABLE */ "", 75979 /* TS_TO_CORE_SYNC_ENABLE_PIPE0 */ "", 75980 /* TS_TO_CORE_SYNC_ENABLE_PIPE1 */ "", 75981 /* TS_TO_CORE_SYNC_ENABLE_PIPE2 */ "", 75982 /* TS_TO_CORE_SYNC_ENABLE_PIPE3 */ "", 75983 /* TTL_FN_PARITY_CONTROL */ "", 75984 /* TTL_FN_PARITY_STATUS_INTR */ "", 75985 /* TTL_FN_PARITY_STATUS_NACK */ "", 75986 /* TTL_FN_RAM_DBGCTRL */ "TTL_FN_RAM_CONTROL", 75987 /* TTL_FN_RAM_DBGCTRL_PIPE0 */ "TTL_FN_RAM_CONTROL_PIPE0", 75988 /* TTL_FN_RAM_DBGCTRL_PIPE1 */ "TTL_FN_RAM_CONTROL_PIPE1", 75989 /* TTL_FN_RAM_DBGCTRL_PIPE2 */ "TTL_FN_RAM_CONTROL_PIPE2", 75990 /* TTL_FN_RAM_DBGCTRL_PIPE3 */ "TTL_FN_RAM_CONTROL_PIPE3", 75991 /* TTL_FN_RAM_DBGCTRL_PIPE4 */ "TTL_FN_RAM_CONTROL_PIPE4", 75992 /* TTL_FN_RAM_DBGCTRL_PIPE5 */ "TTL_FN_RAM_CONTROL_PIPE5", 75993 /* TTL_FN_RAM_DBGCTRL_PIPE6 */ "TTL_FN_RAM_CONTROL_PIPE6", 75994 /* TTL_FN_RAM_DBGCTRL_PIPE7 */ "TTL_FN_RAM_CONTROL_PIPE7", 75995 /* TUCA */ "MAC_GTxUCA", 75996 /* TUFL */ "MAC_GTxUFL", 75997 /* TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 75998 /* TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_STATUS */ "", 75999 /* TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 76000 /* TUNNEL_ADAPT_1_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 76001 /* TUNNEL_ADAPT_1_KEY_GEN_SER_CONTROL */ "", 76002 /* TUNNEL_ADAPT_1_KEY_GEN_TM_CONTROL_64 */ "", 76003 /* TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 76004 /* TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_STATUS */ "", 76005 /* TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 76006 /* TUNNEL_ADAPT_2_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 76007 /* TUNNEL_ADAPT_2_KEY_GEN_SER_CONTROL */ "", 76008 /* TUNNEL_ADAPT_2_KEY_GEN_TM_CONTROL_64 */ "", 76009 /* TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 76010 /* TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_STATUS */ "", 76011 /* TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 76012 /* TUNNEL_ADAPT_3_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 76013 /* TUNNEL_ADAPT_3_KEY_GEN_SER_CONTROL */ "", 76014 /* TUNNEL_ADAPT_3_KEY_GEN_TM_CONTROL_64 */ "", 76015 /* TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_CONFIG_64 */ "", 76016 /* TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_STATUS */ "", 76017 /* TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_STATUS_PIPE0 */ "", 76018 /* TUNNEL_ADAPT_4_KEY_GEN_CAM_BIST_STATUS_PIPE1 */ "", 76019 /* TUNNEL_ADAPT_4_KEY_GEN_SER_CONTROL */ "", 76020 /* TUNNEL_ADAPT_4_KEY_GEN_TM_CONTROL_64 */ "", 76021 /* TUNNEL_TERM_LOOPBACK_PROFILE */ "", 76022 /* TVERIFY */ "XLMIB_GTxVerify", 76023 /* TVLN */ "MAC_GTxVLN", 76024 /* TWO_LAYER_SCH_MODE */ "", 76025 /* TXAEMPTH */ "", 76026 /* TXAFULLTH */ "", 76027 /* TXCASCFG_CHID_0 */ "", 76028 /* TXCASCFG_CHID_1 */ "", 76029 /* TXCASCFG_CHID_2 */ "", 76030 /* TXCASCFG_CHID_3 */ "", 76031 /* TXCASCFG_CHID_4 */ "", 76032 /* TXCASCFG_CHID_5 */ "", 76033 /* TXCASCFG_CHID_6 */ "", 76034 /* TXCASCFG_CHID_7 */ "", 76035 /* TXCASCFG_CHID_8 */ "", 76036 /* TXCASCFG_CHID_9 */ "", 76037 /* TXCASCFG_CHID_10 */ "", 76038 /* TXCASCFG_CHID_11 */ "", 76039 /* TXCASCFG_CHID_12 */ "", 76040 /* TXCASCFG_CHID_13 */ "", 76041 /* TXCASCFG_CHID_14 */ "", 76042 /* TXCASCFG_CHID_15 */ "", 76043 /* TXCASCFG_CHID_16 */ "", 76044 /* TXCASCFG_CHID_17 */ "", 76045 /* TXCASCFG_CHID_18 */ "", 76046 /* TXCASCFG_CHID_19 */ "", 76047 /* TXCASCFG_CHID_20 */ "", 76048 /* TXCASCFG_CHID_21 */ "", 76049 /* TXCASCFG_CHID_22 */ "", 76050 /* TXCASCFG_CHID_23 */ "", 76051 /* TXCASCFG_CHID_24 */ "", 76052 /* TXCASCFG_CHID_25 */ "", 76053 /* TXCASCFG_CHID_26 */ "", 76054 /* TXCASCFG_CHID_27 */ "", 76055 /* TXCASCFG_CHID_28 */ "", 76056 /* TXCASCFG_CHID_29 */ "", 76057 /* TXCASCFG_CHID_30 */ "", 76058 /* TXCASCFG_CHID_31 */ "", 76059 /* TXCASCFG_CHID_32 */ "", 76060 /* TXCASCFG_CHID_33 */ "", 76061 /* TXCASCFG_CHID_34 */ "", 76062 /* TXCASCFG_CHID_35 */ "", 76063 /* TXCASCFG_CHID_36 */ "", 76064 /* TXCASCFG_CHID_37 */ "", 76065 /* TXCASCFG_CHID_38 */ "", 76066 /* TXCASCFG_CHID_39 */ "", 76067 /* TXCASCFG_CHID_40 */ "", 76068 /* TXCASCFG_CHID_41 */ "", 76069 /* TXCASCFG_CHID_42 */ "", 76070 /* TXCASCFG_CHID_43 */ "", 76071 /* TXCASCFG_CHID_44 */ "", 76072 /* TXCASCFG_CHID_45 */ "", 76073 /* TXCASCFG_CHID_46 */ "", 76074 /* TXCASCFG_CHID_47 */ "", 76075 /* TXCASCFG_CHID_48 */ "", 76076 /* TXCASCFG_CHID_49 */ "", 76077 /* TXCASCFG_CHID_50 */ "", 76078 /* TXCASCFG_CHID_51 */ "", 76079 /* TXCASCFG_CHID_52 */ "", 76080 /* TXCASCFG_CHID_53 */ "", 76081 /* TXCASCFG_CHID_54 */ "", 76082 /* TXCASCFG_CHID_55 */ "", 76083 /* TXCASCFG_CHID_56 */ "", 76084 /* TXCASCFG_CHID_57 */ "", 76085 /* TXCASCFG_CHID_58 */ "", 76086 /* TXCASCFG_CHID_59 */ "", 76087 /* TXCASCFG_CHID_60 */ "", 76088 /* TXCASCFG_CHID_61 */ "", 76089 /* TXCASCFG_CHID_62 */ "", 76090 /* TXCASCFG_CHID_63 */ "", 76091 /* TXCASDEL */ "", 76092 /* TXCF */ "MAC_GTxCF", 76093 /* TXCL */ "MAC_GTxXCL", 76094 /* TXFIFO_STAT */ "", 76095 /* TXFILLTH */ "", 76096 /* TXHDRCFG_CHID_0 */ "", 76097 /* TXHDRCFG_CHID_1 */ "", 76098 /* TXHDRCFG_CHID_2 */ "", 76099 /* TXHDRCFG_CHID_3 */ "", 76100 /* TXHDRCFG_CHID_4 */ "", 76101 /* TXHDRCFG_CHID_5 */ "", 76102 /* TXHDRCFG_CHID_6 */ "", 76103 /* TXHDRCFG_CHID_7 */ "", 76104 /* TXHDRCFG_CHID_8 */ "", 76105 /* TXHDRCFG_CHID_9 */ "", 76106 /* TXHDRCFG_CHID_10 */ "", 76107 /* TXHDRCFG_CHID_11 */ "", 76108 /* TXHDRCFG_CHID_12 */ "", 76109 /* TXHDRCFG_CHID_13 */ "", 76110 /* TXHDRCFG_CHID_14 */ "", 76111 /* TXHDRCFG_CHID_15 */ "", 76112 /* TXHDRCFG_CHID_16 */ "", 76113 /* TXHDRCFG_CHID_17 */ "", 76114 /* TXHDRCFG_CHID_18 */ "", 76115 /* TXHDRCFG_CHID_19 */ "", 76116 /* TXHDRCFG_CHID_20 */ "", 76117 /* TXHDRCFG_CHID_21 */ "", 76118 /* TXHDRCFG_CHID_22 */ "", 76119 /* TXHDRCFG_CHID_23 */ "", 76120 /* TXHDRCFG_CHID_24 */ "", 76121 /* TXHDRCFG_CHID_25 */ "", 76122 /* TXHDRCFG_CHID_26 */ "", 76123 /* TXHDRCFG_CHID_27 */ "", 76124 /* TXHDRCFG_CHID_28 */ "", 76125 /* TXHDRCFG_CHID_29 */ "", 76126 /* TXHDRCFG_CHID_30 */ "", 76127 /* TXHDRCFG_CHID_31 */ "", 76128 /* TXHDRCFG_CHID_32 */ "", 76129 /* TXHDRCFG_CHID_33 */ "", 76130 /* TXHDRCFG_CHID_34 */ "", 76131 /* TXHDRCFG_CHID_35 */ "", 76132 /* TXHDRCFG_CHID_36 */ "", 76133 /* TXHDRCFG_CHID_37 */ "", 76134 /* TXHDRCFG_CHID_38 */ "", 76135 /* TXHDRCFG_CHID_39 */ "", 76136 /* TXHDRCFG_CHID_40 */ "", 76137 /* TXHDRCFG_CHID_41 */ "", 76138 /* TXHDRCFG_CHID_42 */ "", 76139 /* TXHDRCFG_CHID_43 */ "", 76140 /* TXHDRCFG_CHID_44 */ "", 76141 /* TXHDRCFG_CHID_45 */ "", 76142 /* TXHDRCFG_CHID_46 */ "", 76143 /* TXHDRCFG_CHID_47 */ "", 76144 /* TXHDRCFG_CHID_48 */ "", 76145 /* TXHDRCFG_CHID_49 */ "", 76146 /* TXHDRCFG_CHID_50 */ "", 76147 /* TXHDRCFG_CHID_51 */ "", 76148 /* TXHDRCFG_CHID_52 */ "", 76149 /* TXHDRCFG_CHID_53 */ "", 76150 /* TXHDRCFG_CHID_54 */ "", 76151 /* TXHDRCFG_CHID_55 */ "", 76152 /* TXHDRCFG_CHID_56 */ "", 76153 /* TXHDRCFG_CHID_57 */ "", 76154 /* TXHDRCFG_CHID_58 */ "", 76155 /* TXHDRCFG_CHID_59 */ "", 76156 /* TXHDRCFG_CHID_60 */ "", 76157 /* TXHDRCFG_CHID_61 */ "", 76158 /* TXHDRCFG_CHID_62 */ "", 76159 /* TXHDRCFG_CHID_63 */ "", 76160 /* TXLLFCMSGCNT */ "", 76161 /* TXLP_COUNTER_MEM_PARITY_STATUS */ "", 76162 /* TXLP_COUNTER_MEM_PARITY_STATUS_NACK */ "", 76163 /* TXLP_CSTATEBUF_PARITY_STATUS */ "", 76164 /* TXLP_CTRLBUF_ECC_STATUS */ "", 76165 /* TXLP_DATABUF_ECC_STATUS */ "", 76166 /* TXLP_DEBUG_COUNTER_SELECT0 */ "", 76167 /* TXLP_DEBUG_COUNTER_SELECT1 */ "", 76168 /* TXLP_DEBUG_COUNTER_SELECT2 */ "", 76169 /* TXLP_DEBUG_COUNTER_SELECT3 */ "", 76170 /* TXLP_DEBUG_COUNTER_SELECT4 */ "", 76171 /* TXLP_DEBUG_COUNTER_SELECT5 */ "", 76172 /* TXLP_DEBUG_COUNTER_SELECT6 */ "", 76173 /* TXLP_DEBUG_COUNTER_SELECT7 */ "", 76174 /* TXLP_ECC_PARITY_CONTROL */ "", 76175 /* TXLP_HW_RESET_CONTROL_0 */ "", 76176 /* TXLP_HW_RESET_CONTROL_1 */ "", 76177 /* TXLP_INT2EXT_STREAM_MAP_PARITY_STATUS */ "", 76178 /* TXLP_INT2EXT_STREAM_MAP_PARITY_STATUS_NACK */ "", 76179 /* TXLP_INTR_ENABLE */ "", 76180 /* TXLP_INTR_STATUS */ "", 76181 /* TXLP_INT_STREAM_ID_BASE */ "", 76182 /* TXLP_LENGTH_FIELD_SELECTOR */ "", 76183 /* TXLP_MIN_STARTCNT */ "", 76184 /* TXLP_PFC_CONTROL */ "", 76185 /* TXLP_PORT_CREDIT_RESET */ "", 76186 /* TXLP_PORT_ENABLE */ "", 76187 /* TXLP_PORT_FAR_END_MAC_ADDR */ "", 76188 /* TXLP_PORT_LP_MODE_CONTROL */ "", 76189 /* TXLP_PORT_NEAR_END_MAC_ADDR */ "", 76190 /* TXLP_PORT_PKT_CTRL */ "", 76191 /* TXLP_PORT_PKT_SOP_ENABLE */ "", 76192 /* TXLP_PORT_VLAN_TPID */ "", 76193 /* TXLP_RAM_CONTROL_0 */ "", 76194 /* TXLP_RAM_CONTROL_1 */ "", 76195 /* TXLP_RAM_CONTROL_2 */ "", 76196 /* TXLP_RAM_CONTROL_3 */ "", 76197 /* TXLP_RAM_CONTROL_4 */ "", 76198 /* TXLP_RAM_CONTROL_5 */ "", 76199 /* TXLP_RAM_CONTROL_6 */ "", 76200 /* TXLP_RESICRCBUF_PARITY_STATUS */ "", 76201 /* TXLP_RESIDATABUF_ECC_STATUS */ "", 76202 /* TXLP_TCI_FIELD_SELECTOR */ "", 76203 /* TXLP_TRIGGER_MEM_PARITY_STATUS */ "", 76204 /* TXLP_TRIGGER_MEM_PARITY_STATUS_NACK */ "", 76205 /* TXPF */ "MAC_GTxPF", 76206 /* TXPP */ "MAC_GTxPP", 76207 /* TXPREAMBLE */ "", 76208 /* TXQ_DESTINATION_ID_FORMAT_TO_FABRIC */ "", 76209 /* TXQ_DTQ_CRDIT_STATUS */ "", 76210 /* TXQ_DTQ_STATUS */ "", 76211 /* TXQ_ECC_1B_ERR_CNT */ "", 76212 /* TXQ_ECC_2B_ERR_CNT */ "", 76213 /* TXQ_ECC_ERR_1B_INITIATE */ "", 76214 /* TXQ_ECC_ERR_1B_MONITOR_MEM_MASK */ "", 76215 /* TXQ_ECC_ERR_2B_INITIATE */ "", 76216 /* TXQ_ECC_ERR_2B_MONITOR_MEM_MASK */ "", 76217 /* TXQ_ECC_INTERRUPT_REGISTER */ "", 76218 /* TXQ_ECC_INTERRUPT_REGISTER_MASK */ "", 76219 /* TXQ_ECC_INTERRUPT_REGISTER_TEST */ "", 76220 /* TXQ_EGQ_COUNTER */ "", 76221 /* TXQ_ENABLE_DYNAMIC_MEMORY_ACCESS */ "", 76222 /* TXQ_ERROR_INITIATION_DATA */ "", 76223 /* TXQ_FC_STATUS_VEC */ "", 76224 /* TXQ_FDT_COUNTER */ "", 76225 /* TXQ_FDT_PRG_COUNTER_CFG */ "", 76226 /* TXQ_GLOBAL_GENERAL_CFG_1 */ "", 76227 /* TXQ_GLOBAL_MEM_OPTIONS */ "", 76228 /* TXQ_GLOBAL_ONE_PLUS_ONE_PORT_PROTECTION */ "", 76229 /* TXQ_GTIMER_CONFIGURATION */ "", 76230 /* TXQ_INDIRECT_COMMAND */ "", 76231 /* TXQ_INDIRECT_COMMAND_ADDRESS */ "", 76232 /* TXQ_INDIRECT_COMMAND_DATA_INCREMENT */ "", 76233 /* TXQ_INDIRECT_COMMAND_RD_DATA */ "", 76234 /* TXQ_INDIRECT_COMMAND_WIDE_MEM */ "", 76235 /* TXQ_INDIRECT_COMMAND_WR_DATA */ "", 76236 /* TXQ_INDIRECT_FORCE_BUBBLE */ "", 76237 /* TXQ_INTERRUPT_MASK_REGISTER */ "", 76238 /* TXQ_INTERRUPT_REGISTER */ "", 76239 /* TXQ_INTERRUPT_REGISTER_TEST */ "", 76240 /* TXQ_LOCAL_FIFO_CFG */ "", 76241 /* TXQ_LTQ_STATUS */ "", 76242 /* TXQ_PDQ_STATUS_VEC_FLIP_POLARITY */ "", 76243 /* TXQ_RESERVED_MIRROR_ADDR */ "", 76244 /* TXQ_RESERVED_MTCD */ "", 76245 /* TXQ_RESERVED_MTCP */ "", 76246 /* TXQ_RESERVED_SPARE_0 */ "", 76247 /* TXQ_RESERVED_SPARE_1 */ "", 76248 /* TXQ_RESERVED_SPARE_2 */ "", 76249 /* TXQ_RESERVED_SPARE_3 */ "", 76250 /* TXQ_RXI_COUNTER */ "", 76251 /* TXQ_SBUS_BROADCAST_ID */ "", 76252 /* TXQ_SBUS_LAST_IN_CHAIN */ "", 76253 /* TXQ_TXI_COUNTER */ "", 76254 /* TXQ_TXQ_DEBUG_CONFIGURATION */ "", 76255 /* TXQ_TXQ_GENERAL_CONFIGURATION */ "", 76256 /* TXRTPTS1_CHID_0 */ "", 76257 /* TXRTPTS1_CHID_1 */ "", 76258 /* TXRTPTS1_CHID_2 */ "", 76259 /* TXRTPTS1_CHID_3 */ "", 76260 /* TXRTPTS1_CHID_4 */ "", 76261 /* TXRTPTS1_CHID_5 */ "", 76262 /* TXRTPTS1_CHID_6 */ "", 76263 /* TXRTPTS1_CHID_7 */ "", 76264 /* TXRTPTS1_CHID_8 */ "", 76265 /* TXRTPTS1_CHID_9 */ "", 76266 /* TXRTPTS1_CHID_10 */ "", 76267 /* TXRTPTS1_CHID_11 */ "", 76268 /* TXRTPTS1_CHID_12 */ "", 76269 /* TXRTPTS1_CHID_13 */ "", 76270 /* TXRTPTS1_CHID_14 */ "", 76271 /* TXRTPTS1_CHID_15 */ "", 76272 /* TXRTPTS1_CHID_16 */ "", 76273 /* TXRTPTS1_CHID_17 */ "", 76274 /* TXRTPTS1_CHID_18 */ "", 76275 /* TXRTPTS1_CHID_19 */ "", 76276 /* TXRTPTS1_CHID_20 */ "", 76277 /* TXRTPTS1_CHID_21 */ "", 76278 /* TXRTPTS1_CHID_22 */ "", 76279 /* TXRTPTS1_CHID_23 */ "", 76280 /* TXRTPTS1_CHID_24 */ "", 76281 /* TXRTPTS1_CHID_25 */ "", 76282 /* TXRTPTS1_CHID_26 */ "", 76283 /* TXRTPTS1_CHID_27 */ "", 76284 /* TXRTPTS1_CHID_28 */ "", 76285 /* TXRTPTS1_CHID_29 */ "", 76286 /* TXRTPTS1_CHID_30 */ "", 76287 /* TXRTPTS1_CHID_31 */ "", 76288 /* TXRTPTS1_CHID_32 */ "", 76289 /* TXRTPTS1_CHID_33 */ "", 76290 /* TXRTPTS1_CHID_34 */ "", 76291 /* TXRTPTS1_CHID_35 */ "", 76292 /* TXRTPTS1_CHID_36 */ "", 76293 /* TXRTPTS1_CHID_37 */ "", 76294 /* TXRTPTS1_CHID_38 */ "", 76295 /* TXRTPTS1_CHID_39 */ "", 76296 /* TXRTPTS1_CHID_40 */ "", 76297 /* TXRTPTS1_CHID_41 */ "", 76298 /* TXRTPTS1_CHID_42 */ "", 76299 /* TXRTPTS1_CHID_43 */ "", 76300 /* TXRTPTS1_CHID_44 */ "", 76301 /* TXRTPTS1_CHID_45 */ "", 76302 /* TXRTPTS1_CHID_46 */ "", 76303 /* TXRTPTS1_CHID_47 */ "", 76304 /* TXRTPTS1_CHID_48 */ "", 76305 /* TXRTPTS1_CHID_49 */ "", 76306 /* TXRTPTS1_CHID_50 */ "", 76307 /* TXRTPTS1_CHID_51 */ "", 76308 /* TXRTPTS1_CHID_52 */ "", 76309 /* TXRTPTS1_CHID_53 */ "", 76310 /* TXRTPTS1_CHID_54 */ "", 76311 /* TXRTPTS1_CHID_55 */ "", 76312 /* TXRTPTS1_CHID_56 */ "", 76313 /* TXRTPTS1_CHID_57 */ "", 76314 /* TXRTPTS1_CHID_58 */ "", 76315 /* TXRTPTS1_CHID_59 */ "", 76316 /* TXRTPTS1_CHID_60 */ "", 76317 /* TXRTPTS1_CHID_61 */ "", 76318 /* TXRTPTS1_CHID_62 */ "", 76319 /* TXRTPTS1_CHID_63 */ "", 76320 /* TXRTPTS2_CHID_0 */ "", 76321 /* TXRTPTS2_CHID_1 */ "", 76322 /* TXRTPTS2_CHID_2 */ "", 76323 /* TXRTPTS2_CHID_3 */ "", 76324 /* TXRTPTS2_CHID_4 */ "", 76325 /* TXRTPTS2_CHID_5 */ "", 76326 /* TXRTPTS2_CHID_6 */ "", 76327 /* TXRTPTS2_CHID_7 */ "", 76328 /* TXRTPTS2_CHID_8 */ "", 76329 /* TXRTPTS2_CHID_9 */ "", 76330 /* TXRTPTS2_CHID_10 */ "", 76331 /* TXRTPTS2_CHID_11 */ "", 76332 /* TXRTPTS2_CHID_12 */ "", 76333 /* TXRTPTS2_CHID_13 */ "", 76334 /* TXRTPTS2_CHID_14 */ "", 76335 /* TXRTPTS2_CHID_15 */ "", 76336 /* TXRTPTS2_CHID_16 */ "", 76337 /* TXRTPTS2_CHID_17 */ "", 76338 /* TXRTPTS2_CHID_18 */ "", 76339 /* TXRTPTS2_CHID_19 */ "", 76340 /* TXRTPTS2_CHID_20 */ "", 76341 /* TXRTPTS2_CHID_21 */ "", 76342 /* TXRTPTS2_CHID_22 */ "", 76343 /* TXRTPTS2_CHID_23 */ "", 76344 /* TXRTPTS2_CHID_24 */ "", 76345 /* TXRTPTS2_CHID_25 */ "", 76346 /* TXRTPTS2_CHID_26 */ "", 76347 /* TXRTPTS2_CHID_27 */ "", 76348 /* TXRTPTS2_CHID_28 */ "", 76349 /* TXRTPTS2_CHID_29 */ "", 76350 /* TXRTPTS2_CHID_30 */ "", 76351 /* TXRTPTS2_CHID_31 */ "", 76352 /* TXRTPTS2_CHID_32 */ "", 76353 /* TXRTPTS2_CHID_33 */ "", 76354 /* TXRTPTS2_CHID_34 */ "", 76355 /* TXRTPTS2_CHID_35 */ "", 76356 /* TXRTPTS2_CHID_36 */ "", 76357 /* TXRTPTS2_CHID_37 */ "", 76358 /* TXRTPTS2_CHID_38 */ "", 76359 /* TXRTPTS2_CHID_39 */ "", 76360 /* TXRTPTS2_CHID_40 */ "", 76361 /* TXRTPTS2_CHID_41 */ "", 76362 /* TXRTPTS2_CHID_42 */ "", 76363 /* TXRTPTS2_CHID_43 */ "", 76364 /* TXRTPTS2_CHID_44 */ "", 76365 /* TXRTPTS2_CHID_45 */ "", 76366 /* TXRTPTS2_CHID_46 */ "", 76367 /* TXRTPTS2_CHID_47 */ "", 76368 /* TXRTPTS2_CHID_48 */ "", 76369 /* TXRTPTS2_CHID_49 */ "", 76370 /* TXRTPTS2_CHID_50 */ "", 76371 /* TXRTPTS2_CHID_51 */ "", 76372 /* TXRTPTS2_CHID_52 */ "", 76373 /* TXRTPTS2_CHID_53 */ "", 76374 /* TXRTPTS2_CHID_54 */ "", 76375 /* TXRTPTS2_CHID_55 */ "", 76376 /* TXRTPTS2_CHID_56 */ "", 76377 /* TXRTPTS2_CHID_57 */ "", 76378 /* TXRTPTS2_CHID_58 */ "", 76379 /* TXRTPTS2_CHID_59 */ "", 76380 /* TXRTPTS2_CHID_60 */ "", 76381 /* TXRTPTS2_CHID_61 */ "", 76382 /* TXRTPTS2_CHID_62 */ "", 76383 /* TXRTPTS2_CHID_63 */ "", 76384 /* TX_CNT_CONFIG */ "", 76385 /* TX_CNT_CONFIG_64 */ "TX_CNT_CONFIG", 76386 /* TX_EEE_LPI_DURATION_COUNTER */ "XLMIB_TX_EEE_LPI_DURATION_COUNTER", 76387 /* TX_EEE_LPI_EVENT_COUNTER */ "XLMIB_TX_EEE_LPI_EVENT_COUNTER", 76388 /* TX_HCFC_COUNTER */ "XLMIB_TX_HCFC_COUNTER", 76389 /* TX_IPG_LENGTH */ "", 76390 /* TX_LLFC_LOG_COUNTER */ "XLMIB_TX_LLFC_LOG_COUNTER", 76391 /* TX_PAD_THRESHOLD */ "", 76392 /* TX_PKT_CNT */ "", 76393 /* TX_PKT_CNT_64 */ "TX_PKT_CNT", 76394 /* TX_PKT_CNT_31_0 */ "", 76395 /* TX_PKT_CNT_39_32 */ "", 76396 /* TX_PKT_CNT_39_32_SNAP */ "", 76397 /* TX_PREAMBLE */ "", 76398 /* TX_TS_DATA */ "", 76399 /* TX_TS_SEQ_ID */ "", 76400 /* TX_X1_CONTROL0_GLAS_TPMA_ADJ_01 */ "", 76401 /* TX_X1_CONTROL0_GLAS_TPMA_ADJ_23 */ "", 76402 /* TX_X1_CONTROL0_GLAS_TPMA_ADJ_45 */ "", 76403 /* TX_X1_CONTROL0_GLAS_TPMA_ADJ_67 */ "", 76404 /* TX_X1_CONTROL0_GLAS_TPMA_ADJ_0_1 */ "", 76405 /* TX_X1_CONTROL0_GLAS_TPMA_ADJ_2_3 */ "", 76406 /* TX_X1_CONTROL0_GLAS_TPMA_CONTROL */ "", 76407 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_0 */ "", 76408 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_1 */ "", 76409 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_2 */ "", 76410 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_3 */ "", 76411 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_4 */ "", 76412 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_5 */ "", 76413 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_6 */ "", 76414 /* TX_X1_CONTROL0_GLAS_TPMA_DATA_7 */ "", 76415 /* TX_X1_CONTROL0_TS_DEBUG_WORD0_VALUE */ "", 76416 /* TX_X1_CONTROL0_TS_DEBUG_WORD1_VALUE */ "", 76417 /* TX_X1_CONTROL0_TS_DEBUG_WORD2_VALUE */ "", 76418 /* TX_X1_CONTROL0_TX_LANE_SWAP */ "", 76419 /* TX_X2_CONTROL0_CL82_0 */ "", 76420 /* TX_X2_STATUS0_CL82_TX_STATUS_0 */ "", 76421 /* TX_X2_STATUS0_CL82_TX_STATUS_1 */ "", 76422 /* TX_X4_CONTROL0_CL36TX_CONTROL */ "", 76423 /* TX_X4_CONTROL0_ENCODE_0 */ "", 76424 /* TX_X4_CONTROL0_ERROR_CONTROL */ "", 76425 /* TX_X4_CONTROL0_MISC */ "", 76426 /* TX_X4_CONTROL0_RS_SYMBOL */ "", 76427 /* TX_X4_CONTROL0_TX_CONTROL0 */ "", 76428 /* TX_X4_CONTROL0_TX_TS_CONTROL */ "", 76429 /* TX_X4_CONTROL0_TX_TS_POINT_CONTROL */ "", 76430 /* TX_X4_CREDIT0_CREDIT0 */ "", 76431 /* TX_X4_CREDIT0_CREDIT1 */ "", 76432 /* TX_X4_CREDIT0_LOOPCNT */ "", 76433 /* TX_X4_CREDIT0_MAC_CREDITGENCNT */ "", 76434 /* TX_X4_STATUS0_ENCODE_STATUS_0 */ "", 76435 /* TX_X4_STATUS0_ENCODE_STATUS_1 */ "", 76436 /* TX_X4_STATUS0_PCS_STATUS_LATCHED */ "", 76437 /* TX_X4_STATUS0_PCS_STATUS_LIVE */ "", 76438 /* TX_X4_STATUS0_PMA_STATUS */ "", 76439 /* TX_X4_STATUS0_TX_1588_TIMESTAMP_HI */ "", 76440 /* TX_X4_STATUS0_TX_1588_TIMESTAMP_LO */ "", 76441 /* TX_X4_STATUS0_TX_1588_TIMESTAMP_MID */ "", 76442 /* TX_X4_STATUS0_TX_1588_TIMESTAMP_STATUS */ "", 76443 /* TX_X4_STATUS0_TX_TS_SEQ_ID */ "", 76444 /* TZPC_TRUSTZONE_ERROR_ENABLE */ "", 76445 /* TZPC_TRUSTZONE_ERROR_INTERRUPT_CLEAR */ "", 76446 /* TZPC_TRUSTZONE_ERROR_INTERRUPT_STATUS */ "", 76447 /* TZPC_TZPCDECPROT0CLR */ "", 76448 /* TZPC_TZPCDECPROT0SET */ "", 76449 /* TZPC_TZPCDECPROT0STAT */ "", 76450 /* TZPC_TZPCDECPROT1CLR */ "", 76451 /* TZPC_TZPCDECPROT1SET */ "", 76452 /* TZPC_TZPCDECPROT1STAT */ "", 76453 /* TZPC_TZPCDECPROT2CLR */ "", 76454 /* TZPC_TZPCDECPROT2SET */ "", 76455 /* TZPC_TZPCDECPROT2STAT */ "", 76456 /* TZPC_TZPCR0SIZE */ "", 76457 /* T_64 */ "", 76458 /* T_127 */ "", 76459 /* T_255 */ "", 76460 /* T_511 */ "", 76461 /* T_1023 */ "", 76462 /* T_1518 */ "", 76463 /* T_2047 */ "", 76464 /* T_4095 */ "", 76465 /* T_9216 */ "", 76466 /* T_16383 */ "", 76467 /* U0_LED_ACCU_CTRL */ "", 76468 /* U0_LED_ACCU_STATUS */ "", 76469 /* U0_LED_CLK_DIV_CTRL */ "", 76470 /* U0_LED_INTR_ENABLE */ "", 76471 /* U0_LED_REFRESH_CTRL */ "", 76472 /* U0_LED_SEND_CTRL */ "", 76473 /* U0_LED_SEND_CTRL_0 */ "", 76474 /* U0_LED_SEND_CTRL_1 */ "", 76475 /* U0_LED_SEND_CTRL_2 */ "", 76476 /* U0_LED_SEND_CTRL_3 */ "", 76477 /* U0_LED_SEND_CTRL_4 */ "", 76478 /* U0_LED_SEND_STATUS */ "", 76479 /* U0_LED_SRAM_CTRL */ "", 76480 /* U0_LED_SRAM_ECC_CTRL */ "", 76481 /* U0_LED_SRAM_ECC_STATUS */ "", 76482 /* U0_LED_SW_CNFG_LINK_1023_992 */ "", 76483 /* U0_LED_SW_CNFG_LINK_127_96 */ "", 76484 /* U0_LED_SW_CNFG_LINK_159_128 */ "", 76485 /* U0_LED_SW_CNFG_LINK_191_160 */ "", 76486 /* U0_LED_SW_CNFG_LINK_223_192 */ "", 76487 /* U0_LED_SW_CNFG_LINK_255_224 */ "", 76488 /* U0_LED_SW_CNFG_LINK_287_256 */ "", 76489 /* U0_LED_SW_CNFG_LINK_319_288 */ "", 76490 /* U0_LED_SW_CNFG_LINK_31_0 */ "", 76491 /* U0_LED_SW_CNFG_LINK_351_320 */ "", 76492 /* U0_LED_SW_CNFG_LINK_383_352 */ "", 76493 /* U0_LED_SW_CNFG_LINK_415_384 */ "", 76494 /* U0_LED_SW_CNFG_LINK_447_416 */ "", 76495 /* U0_LED_SW_CNFG_LINK_479_448 */ "", 76496 /* U0_LED_SW_CNFG_LINK_511_480 */ "", 76497 /* U0_LED_SW_CNFG_LINK_543_512 */ "", 76498 /* U0_LED_SW_CNFG_LINK_575_544 */ "", 76499 /* U0_LED_SW_CNFG_LINK_607_576 */ "", 76500 /* U0_LED_SW_CNFG_LINK_639_608 */ "", 76501 /* U0_LED_SW_CNFG_LINK_63_32 */ "", 76502 /* U0_LED_SW_CNFG_LINK_671_640 */ "", 76503 /* U0_LED_SW_CNFG_LINK_703_672 */ "", 76504 /* U0_LED_SW_CNFG_LINK_735_704 */ "", 76505 /* U0_LED_SW_CNFG_LINK_767_736 */ "", 76506 /* U0_LED_SW_CNFG_LINK_799_768 */ "", 76507 /* U0_LED_SW_CNFG_LINK_831_800 */ "", 76508 /* U0_LED_SW_CNFG_LINK_863_832 */ "", 76509 /* U0_LED_SW_CNFG_LINK_895_864 */ "", 76510 /* U0_LED_SW_CNFG_LINK_927_896 */ "", 76511 /* U0_LED_SW_CNFG_LINK_959_928 */ "", 76512 /* U0_LED_SW_CNFG_LINK_95_64 */ "", 76513 /* U0_LED_SW_CNFG_LINK_991_960 */ "", 76514 /* U0_M0SSQ_ADDR_REMAP_WINDOW_0_LSB */ "", 76515 /* U0_M0SSQ_ADDR_REMAP_WINDOW_0_MSB */ "", 76516 /* U0_M0SSQ_ADDR_REMAP_WINDOW_1_LSB */ "", 76517 /* U0_M0SSQ_ADDR_REMAP_WINDOW_1_MSB */ "", 76518 /* U0_M0SSQ_ADDR_REMAP_WINDOW_2_LSB */ "", 76519 /* U0_M0SSQ_ADDR_REMAP_WINDOW_2_MSB */ "", 76520 /* U0_M0SSQ_ADDR_REMAP_WINDOW_3_LSB */ "", 76521 /* U0_M0SSQ_ADDR_REMAP_WINDOW_3_MSB */ "", 76522 /* U0_M0SSQ_ADDR_REMAP_WINDOW_4_LSB */ "", 76523 /* U0_M0SSQ_ADDR_REMAP_WINDOW_4_MSB */ "", 76524 /* U0_M0SSQ_ADDR_REMAP_WINDOW_5_LSB */ "", 76525 /* U0_M0SSQ_ADDR_REMAP_WINDOW_5_MSB */ "", 76526 /* U0_M0SSQ_ADDR_REMAP_WINDOW_6_LSB */ "", 76527 /* U0_M0SSQ_ADDR_REMAP_WINDOW_6_MSB */ "", 76528 /* U0_M0SSQ_ADDR_REMAP_WINDOW_7_LSB */ "", 76529 /* U0_M0SSQ_ADDR_REMAP_WINDOW_7_MSB */ "", 76530 /* U0_M0SSQ_CTRL */ "", 76531 /* U0_M0SSQ_ECC_CTRL */ "", 76532 /* U0_M0SSQ_ECC_STATUS */ "", 76533 /* U0_M0SSQ_INTR_ENABLE */ "", 76534 /* U0_M0SS_CONTROL */ "", 76535 /* U0_M0SS_DEBUG_CONTROL */ "", 76536 /* U0_M0SS_ECC_CTRL */ "", 76537 /* U0_M0SS_ECC_STATUS */ "", 76538 /* U0_M0SS_ECO */ "", 76539 /* U0_M0SS_INTR_127_96 */ "", 76540 /* U0_M0SS_INTR_159_128 */ "", 76541 /* U0_M0SS_INTR_191_160 */ "", 76542 /* U0_M0SS_INTR_223_192 */ "", 76543 /* U0_M0SS_INTR_255_224 */ "", 76544 /* U0_M0SS_INTR_31_0 */ "", 76545 /* U0_M0SS_INTR_63_32 */ "", 76546 /* U0_M0SS_INTR_95_64 */ "", 76547 /* U0_M0SS_INTR_CONTROL */ "", 76548 /* U0_M0SS_INTR_ENABLE */ "", 76549 /* U0_M0SS_INTR_MASK_127_96 */ "", 76550 /* U0_M0SS_INTR_MASK_159_128 */ "", 76551 /* U0_M0SS_INTR_MASK_191_160 */ "", 76552 /* U0_M0SS_INTR_MASK_223_192 */ "", 76553 /* U0_M0SS_INTR_MASK_255_224 */ "", 76554 /* U0_M0SS_INTR_MASK_31_0 */ "", 76555 /* U0_M0SS_INTR_MASK_63_32 */ "", 76556 /* U0_M0SS_INTR_MASK_95_64 */ "", 76557 /* U0_M0SS_RAW_INTR_127_96 */ "", 76558 /* U0_M0SS_RAW_INTR_159_128 */ "", 76559 /* U0_M0SS_RAW_INTR_191_160 */ "", 76560 /* U0_M0SS_RAW_INTR_223_192 */ "", 76561 /* U0_M0SS_RAW_INTR_255_224 */ "", 76562 /* U0_M0SS_RAW_INTR_31_0 */ "", 76563 /* U0_M0SS_RAW_INTR_63_32 */ "", 76564 /* U0_M0SS_RAW_INTR_95_64 */ "", 76565 /* U0_M0SS_STATUS */ "", 76566 /* U0_M0SS_TCM_CTRL */ "", 76567 /* U0_SW_PROG_INTR_CLR */ "", 76568 /* U0_SW_PROG_INTR_ENABLE */ "", 76569 /* U0_SW_PROG_INTR_SET */ "", 76570 /* U0_SW_PROG_INTR_STATUS */ "", 76571 /* U1_M0SS_CONTROL */ "", 76572 /* U1_M0SS_DEBUG_CONTROL */ "", 76573 /* U1_M0SS_ECC_CTRL */ "", 76574 /* U1_M0SS_ECC_STATUS */ "", 76575 /* U1_M0SS_ECO */ "", 76576 /* U1_M0SS_INTR_127_96 */ "", 76577 /* U1_M0SS_INTR_159_128 */ "", 76578 /* U1_M0SS_INTR_191_160 */ "", 76579 /* U1_M0SS_INTR_223_192 */ "", 76580 /* U1_M0SS_INTR_255_224 */ "", 76581 /* U1_M0SS_INTR_31_0 */ "", 76582 /* U1_M0SS_INTR_63_32 */ "", 76583 /* U1_M0SS_INTR_95_64 */ "", 76584 /* U1_M0SS_INTR_CONTROL */ "", 76585 /* U1_M0SS_INTR_ENABLE */ "", 76586 /* U1_M0SS_INTR_MASK_127_96 */ "", 76587 /* U1_M0SS_INTR_MASK_159_128 */ "", 76588 /* U1_M0SS_INTR_MASK_191_160 */ "", 76589 /* U1_M0SS_INTR_MASK_223_192 */ "", 76590 /* U1_M0SS_INTR_MASK_255_224 */ "", 76591 /* U1_M0SS_INTR_MASK_31_0 */ "", 76592 /* U1_M0SS_INTR_MASK_63_32 */ "", 76593 /* U1_M0SS_INTR_MASK_95_64 */ "", 76594 /* U1_M0SS_RAW_INTR_127_96 */ "", 76595 /* U1_M0SS_RAW_INTR_159_128 */ "", 76596 /* U1_M0SS_RAW_INTR_191_160 */ "", 76597 /* U1_M0SS_RAW_INTR_223_192 */ "", 76598 /* U1_M0SS_RAW_INTR_255_224 */ "", 76599 /* U1_M0SS_RAW_INTR_31_0 */ "", 76600 /* U1_M0SS_RAW_INTR_63_32 */ "", 76601 /* U1_M0SS_RAW_INTR_95_64 */ "", 76602 /* U1_M0SS_STATUS */ "", 76603 /* U1_M0SS_TCM_CTRL */ "", 76604 /* U1_SW_PROG_INTR_CLR */ "", 76605 /* U1_SW_PROG_INTR_ENABLE */ "", 76606 /* U1_SW_PROG_INTR_SET */ "", 76607 /* U1_SW_PROG_INTR_STATUS */ "", 76608 /* U2_M0SS_CONTROL */ "", 76609 /* U2_M0SS_DEBUG_CONTROL */ "", 76610 /* U2_M0SS_ECC_CTRL */ "", 76611 /* U2_M0SS_ECC_STATUS */ "", 76612 /* U2_M0SS_ECO */ "", 76613 /* U2_M0SS_INTR_127_96 */ "", 76614 /* U2_M0SS_INTR_159_128 */ "", 76615 /* U2_M0SS_INTR_191_160 */ "", 76616 /* U2_M0SS_INTR_223_192 */ "", 76617 /* U2_M0SS_INTR_255_224 */ "", 76618 /* U2_M0SS_INTR_31_0 */ "", 76619 /* U2_M0SS_INTR_63_32 */ "", 76620 /* U2_M0SS_INTR_95_64 */ "", 76621 /* U2_M0SS_INTR_CONTROL */ "", 76622 /* U2_M0SS_INTR_ENABLE */ "", 76623 /* U2_M0SS_INTR_MASK_127_96 */ "", 76624 /* U2_M0SS_INTR_MASK_159_128 */ "", 76625 /* U2_M0SS_INTR_MASK_191_160 */ "", 76626 /* U2_M0SS_INTR_MASK_223_192 */ "", 76627 /* U2_M0SS_INTR_MASK_255_224 */ "", 76628 /* U2_M0SS_INTR_MASK_31_0 */ "", 76629 /* U2_M0SS_INTR_MASK_63_32 */ "", 76630 /* U2_M0SS_INTR_MASK_95_64 */ "", 76631 /* U2_M0SS_RAW_INTR_127_96 */ "", 76632 /* U2_M0SS_RAW_INTR_159_128 */ "", 76633 /* U2_M0SS_RAW_INTR_191_160 */ "", 76634 /* U2_M0SS_RAW_INTR_223_192 */ "", 76635 /* U2_M0SS_RAW_INTR_255_224 */ "", 76636 /* U2_M0SS_RAW_INTR_31_0 */ "", 76637 /* U2_M0SS_RAW_INTR_63_32 */ "", 76638 /* U2_M0SS_RAW_INTR_95_64 */ "", 76639 /* U2_M0SS_STATUS */ "", 76640 /* U2_M0SS_TCM_CTRL */ "", 76641 /* U2_SW_PROG_INTR_CLR */ "", 76642 /* U2_SW_PROG_INTR_ENABLE */ "", 76643 /* U2_SW_PROG_INTR_SET */ "", 76644 /* U2_SW_PROG_INTR_STATUS */ "", 76645 /* U3_M0SS_CONTROL */ "", 76646 /* U3_M0SS_DEBUG_CONTROL */ "", 76647 /* U3_M0SS_ECC_CTRL */ "", 76648 /* U3_M0SS_ECC_STATUS */ "", 76649 /* U3_M0SS_ECO */ "", 76650 /* U3_M0SS_INTR_127_96 */ "", 76651 /* U3_M0SS_INTR_159_128 */ "", 76652 /* U3_M0SS_INTR_191_160 */ "", 76653 /* U3_M0SS_INTR_223_192 */ "", 76654 /* U3_M0SS_INTR_255_224 */ "", 76655 /* U3_M0SS_INTR_31_0 */ "", 76656 /* U3_M0SS_INTR_63_32 */ "", 76657 /* U3_M0SS_INTR_95_64 */ "", 76658 /* U3_M0SS_INTR_CONTROL */ "", 76659 /* U3_M0SS_INTR_ENABLE */ "", 76660 /* U3_M0SS_INTR_MASK_127_96 */ "", 76661 /* U3_M0SS_INTR_MASK_159_128 */ "", 76662 /* U3_M0SS_INTR_MASK_191_160 */ "", 76663 /* U3_M0SS_INTR_MASK_223_192 */ "", 76664 /* U3_M0SS_INTR_MASK_255_224 */ "", 76665 /* U3_M0SS_INTR_MASK_31_0 */ "", 76666 /* U3_M0SS_INTR_MASK_63_32 */ "", 76667 /* U3_M0SS_INTR_MASK_95_64 */ "", 76668 /* U3_M0SS_RAW_INTR_127_96 */ "", 76669 /* U3_M0SS_RAW_INTR_159_128 */ "", 76670 /* U3_M0SS_RAW_INTR_191_160 */ "", 76671 /* U3_M0SS_RAW_INTR_223_192 */ "", 76672 /* U3_M0SS_RAW_INTR_255_224 */ "", 76673 /* U3_M0SS_RAW_INTR_31_0 */ "", 76674 /* U3_M0SS_RAW_INTR_63_32 */ "", 76675 /* U3_M0SS_RAW_INTR_95_64 */ "", 76676 /* U3_M0SS_STATUS */ "", 76677 /* U3_M0SS_TCM_CTRL */ "", 76678 /* U3_SW_PROG_INTR_CLR */ "", 76679 /* U3_SW_PROG_INTR_ENABLE */ "", 76680 /* U3_SW_PROG_INTR_SET */ "", 76681 /* U3_SW_PROG_INTR_STATUS */ "", 76682 /* UCQDBMEMDEBUG */ "", 76683 /* UCQRPMEMDEBUG */ "", 76684 /* UCQWPMEMDEBUG */ "", 76685 /* UCQ_CONFIG */ "", 76686 /* UCQ_COS_EMPTY_REG */ "", 76687 /* UCQ_EXTCOS1_EMPTY_REG */ "", 76688 /* UCQ_FREE_MEMDEBUG */ "", 76689 /* UCQ_FREE_MEMECC_ERRPTR */ "", 76690 /* UCQ_UCQE0_MEMDEBUG */ "", 76691 /* UCQ_UCQE1_MEMDEBUG */ "", 76692 /* UCQ_UCQE2_MEMDEBUG */ "", 76693 /* UCQ_UCQE3_MEMDEBUG */ "", 76694 /* UCQ_UCQE_MEMECC_ERRPTR */ "", 76695 /* UC_0_CONFIG */ "", 76696 /* UC_0_DEBUG_CONFIG */ "", 76697 /* UC_0_DEBUG_STATUS */ "", 76698 /* UC_0_RST_CONTROL */ "", 76699 /* UC_0_STATUS */ "", 76700 /* UC_0_TIMER_INTR_MASK */ "", 76701 /* UC_1_CONFIG */ "", 76702 /* UC_1_DEBUG_CONFIG */ "", 76703 /* UC_1_DEBUG_STATUS */ "", 76704 /* UC_1_RST_CONTROL */ "", 76705 /* UC_1_STATUS */ "", 76706 /* UC_1_TIMER_INTR_MASK */ "", 76707 /* UC_HG_QUEUE_MODE */ "PORT_INITIAL_COPY_COUNT_WIDTH", 76708 /* UDF_CAM_BIST_CONFIG */ "", 76709 /* UDF_CAM_BIST_CONFIG_64 */ "", 76710 /* UDF_CAM_BIST_CONFIG_64_PIPE0 */ "", 76711 /* UDF_CAM_BIST_CONFIG_64_PIPE1 */ "", 76712 /* UDF_CAM_BIST_CONFIG_64_PIPE2 */ "", 76713 /* UDF_CAM_BIST_CONFIG_64_PIPE3 */ "", 76714 /* UDF_CAM_BIST_CONFIG_PIPE0 */ "", 76715 /* UDF_CAM_BIST_CONFIG_PIPE1 */ "", 76716 /* UDF_CAM_BIST_CONFIG_PIPE2 */ "", 76717 /* UDF_CAM_BIST_CONFIG_PIPE3 */ "", 76718 /* UDF_CAM_BIST_DBG_DATA */ "", 76719 /* UDF_CAM_BIST_DBG_DATA_PIPE0 */ "", 76720 /* UDF_CAM_BIST_DBG_DATA_PIPE1 */ "", 76721 /* UDF_CAM_BIST_DBG_DATA_PIPE2 */ "", 76722 /* UDF_CAM_BIST_DBG_DATA_PIPE3 */ "", 76723 /* UDF_CAM_BIST_STATUS */ "", 76724 /* UDF_CAM_BIST_STATUS_PIPE0 */ "", 76725 /* UDF_CAM_BIST_STATUS_PIPE1 */ "", 76726 /* UDF_CAM_BIST_STATUS_PIPE2 */ "", 76727 /* UDF_CAM_BIST_STATUS_PIPE3 */ "", 76728 /* UDF_CAM_DBGCTRL */ "UDF_CAM_CONTROL", 76729 /* UDF_CAM_DBGCTRL_PIPE0 */ "UDF_CAM_CONTROL_PIPE0", 76730 /* UDF_CAM_DBGCTRL_PIPE1 */ "UDF_CAM_CONTROL_PIPE1", 76731 /* UDF_CAM_DBGCTRL_PIPE2 */ "UDF_CAM_CONTROL_PIPE2", 76732 /* UDF_CAM_DBGCTRL_PIPE3 */ "UDF_CAM_CONTROL_PIPE3", 76733 /* UDF_CAM_SERCTRL */ "UDF_CAM_SER_CONTROL", 76734 /* UDF_ETHERTYPE_MATCH */ "", 76735 /* UDF_IPPROTO_MATCH */ "", 76736 /* UDF_OFFSET_ECC_CONTROL */ "", 76737 /* UDF_OFFSET_PARITY_CONTROL */ "", 76738 /* UDF_OFFSET_PARITY_STATUS */ "", 76739 /* UDF_TCAM_CAM_BIST_CONFIG */ "", 76740 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE0 */ "", 76741 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE1 */ "", 76742 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE2 */ "", 76743 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE3 */ "", 76744 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE4 */ "", 76745 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE5 */ "", 76746 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE6 */ "", 76747 /* UDF_TCAM_CAM_BIST_CONFIG_PIPE7 */ "", 76748 /* UDF_TCAM_CAM_BIST_STATUS */ "", 76749 /* UDF_TCAM_CAM_BIST_STATUS_PIPE0 */ "", 76750 /* UDF_TCAM_CAM_BIST_STATUS_PIPE1 */ "", 76751 /* UDF_TCAM_CAM_BIST_STATUS_PIPE2 */ "", 76752 /* UDF_TCAM_CAM_BIST_STATUS_PIPE3 */ "", 76753 /* UDF_TCAM_CAM_BIST_STATUS_PIPE4 */ "", 76754 /* UDF_TCAM_CAM_BIST_STATUS_PIPE5 */ "", 76755 /* UDF_TCAM_CAM_BIST_STATUS_PIPE6 */ "", 76756 /* UDF_TCAM_CAM_BIST_STATUS_PIPE7 */ "", 76757 /* UFLOW_AGED_COUNT */ "", 76758 /* UFLOW_DEBUG_RANGE */ "", 76759 /* UFLOW_HASH_CONTROL_RTAG7 */ "", 76760 /* UFLOW_INACTIVE_COUNT */ "", 76761 /* UFLOW_LFSR_CONTROL */ "", 76762 /* UFLOW_PORT_CONTROL */ "", 76763 /* UFLOW_REBALANCE_COUNT */ "", 76764 /* UFLOW_TABLE_CONTROL */ "", 76765 /* UFLOW_TABLE_SIZE */ "", 76766 /* UFLOW_TIMER_CONTROL */ "", 76767 /* UFLOW_TIMER_STATUS */ "", 76768 /* UMAC_EEE_CTRL */ "", 76769 /* UMAC_EEE_REF_COUNT */ "", 76770 /* UMAC_REV_ID */ "", 76771 /* UMAC_RX_PKT_DROP_STATUS */ "", 76772 /* UMAC_SYMMETRIC_IDLE_THRESHOLD */ "", 76773 /* UMAC_TIMESTAMP_ADJUST */ "", 76774 /* UMAN_EP_FLSH_WAIT_CNTR */ "", 76775 /* UMAN_IP_FLSH_WAIT_CNTR */ "", 76776 /* UMAN_LINKUP_DLY_CNTR */ "", 76777 /* UNIMAC0_COMMAND_CONFIG */ "", 76778 /* UNIMAC0_FLUSH_CONTROL */ "", 76779 /* UNIMAC0_FRM_LENGTH */ "", 76780 /* UNIMAC0_GMII_EEE_DELAY_ENTRY_TIMER */ "", 76781 /* UNIMAC0_GMII_EEE_WAKE_TIMER */ "", 76782 /* UNIMAC0_IPG_HD_BKP_CNTL */ "", 76783 /* UNIMAC0_MACSEC_CNTRL */ "", 76784 /* UNIMAC0_MAC_0 */ "", 76785 /* UNIMAC0_MAC_1 */ "", 76786 /* UNIMAC0_MAC_MODE */ "", 76787 /* UNIMAC0_MAC_PFC_CTRL */ "", 76788 /* UNIMAC0_MAC_PFC_DA_0 */ "", 76789 /* UNIMAC0_MAC_PFC_DA_1 */ "", 76790 /* UNIMAC0_MAC_PFC_OPCODE */ "", 76791 /* UNIMAC0_MAC_PFC_REFRESH_CTRL */ "", 76792 /* UNIMAC0_MAC_PFC_TYPE */ "", 76793 /* UNIMAC0_MII_EEE_DELAY_ENTRY_TIMER */ "", 76794 /* UNIMAC0_MII_EEE_WAKE_TIMER */ "", 76795 /* UNIMAC0_PAUSE_CONTROL */ "", 76796 /* UNIMAC0_PAUSE_QUANT */ "", 76797 /* UNIMAC0_PFC_XOFF_TIMER */ "", 76798 /* UNIMAC0_RXFIFO_STAT */ "", 76799 /* UNIMAC0_RX_PAUSE_QUANTA_SCALE */ "", 76800 /* UNIMAC0_SFD_OFFSET */ "", 76801 /* UNIMAC0_TAG_0 */ "", 76802 /* UNIMAC0_TAG_1 */ "", 76803 /* UNIMAC0_TS_STATUS_CNTRL */ "", 76804 /* UNIMAC0_TXFIFO_STAT */ "", 76805 /* UNIMAC0_TX_IPG_LENGTH */ "", 76806 /* UNIMAC0_TX_PREAMBLE */ "", 76807 /* UNIMAC0_TX_TS_DATA */ "", 76808 /* UNIMAC0_TX_TS_SEQ_ID */ "", 76809 /* UNIMAC0_UMAC_EEE_CTRL */ "", 76810 /* UNIMAC0_UMAC_EEE_REF_COUNT */ "", 76811 /* UNIMAC0_UMAC_REV_ID */ "", 76812 /* UNIMAC0_UMAC_RX_PKT_DROP_STATUS */ "", 76813 /* UNIMAC0_UMAC_SYMMETRIC_IDLE_THRESHOLD */ "", 76814 /* UNIMAC1_COMMAND_CONFIG */ "", 76815 /* UNIMAC1_FLUSH_CONTROL */ "", 76816 /* UNIMAC1_FRM_LENGTH */ "", 76817 /* UNIMAC1_GMII_EEE_DELAY_ENTRY_TIMER */ "", 76818 /* UNIMAC1_GMII_EEE_WAKE_TIMER */ "", 76819 /* UNIMAC1_IPG_HD_BKP_CNTL */ "", 76820 /* UNIMAC1_MACSEC_CNTRL */ "", 76821 /* UNIMAC1_MAC_0 */ "", 76822 /* UNIMAC1_MAC_1 */ "", 76823 /* UNIMAC1_MAC_MODE */ "", 76824 /* UNIMAC1_MAC_PFC_CTRL */ "", 76825 /* UNIMAC1_MAC_PFC_DA_0 */ "", 76826 /* UNIMAC1_MAC_PFC_DA_1 */ "", 76827 /* UNIMAC1_MAC_PFC_OPCODE */ "", 76828 /* UNIMAC1_MAC_PFC_REFRESH_CTRL */ "", 76829 /* UNIMAC1_MAC_PFC_TYPE */ "", 76830 /* UNIMAC1_MII_EEE_DELAY_ENTRY_TIMER */ "", 76831 /* UNIMAC1_MII_EEE_WAKE_TIMER */ "", 76832 /* UNIMAC1_PAUSE_CONTROL */ "", 76833 /* UNIMAC1_PAUSE_QUANT */ "", 76834 /* UNIMAC1_PFC_XOFF_TIMER */ "", 76835 /* UNIMAC1_RXFIFO_STAT */ "", 76836 /* UNIMAC1_RX_PAUSE_QUANTA_SCALE */ "", 76837 /* UNIMAC1_SFD_OFFSET */ "", 76838 /* UNIMAC1_TAG_0 */ "", 76839 /* UNIMAC1_TAG_1 */ "", 76840 /* UNIMAC1_TS_STATUS_CNTRL */ "", 76841 /* UNIMAC1_TXFIFO_STAT */ "", 76842 /* UNIMAC1_TX_IPG_LENGTH */ "", 76843 /* UNIMAC1_TX_PREAMBLE */ "", 76844 /* UNIMAC1_TX_TS_DATA */ "", 76845 /* UNIMAC1_TX_TS_SEQ_ID */ "", 76846 /* UNIMAC1_UMAC_EEE_CTRL */ "", 76847 /* UNIMAC1_UMAC_EEE_REF_COUNT */ "", 76848 /* UNIMAC1_UMAC_REV_ID */ "", 76849 /* UNIMAC1_UMAC_RX_PKT_DROP_STATUS */ "", 76850 /* UNIMAC1_UMAC_SYMMETRIC_IDLE_THRESHOLD */ "", 76851 /* UNIMAC_PFC_CTRL */ "MAC_PFC_CTRL", 76852 /* UNKNOWN_HGI_BITMAP */ "", 76853 /* UNKNOWN_HGI_BITMAP_64 */ "UNKNOWN_HGI_BITMAP", 76854 /* UNKNOWN_HGI_BITMAP_HI */ "", 76855 /* UNKNOWN_HGI_BITMAP_LO */ "", 76856 /* UNKNOWN_HGI_BITMAP_PARITY_CONTROL */ "", 76857 /* UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTR */ "", 76858 /* UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACK */ "", 76859 /* UNKNOWN_MCAST_BLOCK_MASK */ "", 76860 /* UNKNOWN_MCAST_BLOCK_MASK_64 */ "UNKNOWN_MCAST_BLOCK_MASK", 76861 /* UNKNOWN_MCAST_BLOCK_MASK_HI */ "", 76862 /* UNKNOWN_MCAST_BLOCK_MASK_HI_64 */ "UNKNOWN_MCAST_BLOCK_MASK_HI_64", 76863 /* UNKNOWN_MCAST_BLOCK_MASK_LO_64 */ "UNKNOWN_MCAST_BLOCK_MASK_LO_64", 76864 /* UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROL */ "", 76865 /* UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTR */ "", 76866 /* UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACK */ "", 76867 /* UNKNOWN_UCAST_BLOCK_MASK */ "", 76868 /* UNKNOWN_UCAST_BLOCK_MASK_64 */ "UNKNOWN_UCAST_BLOCK_MASK", 76869 /* UNKNOWN_UCAST_BLOCK_MASK_HI */ "", 76870 /* UNKNOWN_UCAST_BLOCK_MASK_HI_64 */ "UNKNOWN_UCAST_BLOCK_MASK_HI_64", 76871 /* UNKNOWN_UCAST_BLOCK_MASK_LO_64 */ "UNKNOWN_UCAST_BLOCK_MASK_LO_64", 76872 /* UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROL */ "", 76873 /* UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTR */ "", 76874 /* UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACK */ "", 76875 /* UPMEP_TX_SOBMH_HDR_0_64 */ "", 76876 /* UPMEP_TX_SOBMH_HDR_1_64 */ "", 76877 /* USB2D_DEVCONFIG */ "", 76878 /* USB2D_DEVCTRL */ "", 76879 /* USB2D_DEVINTR */ "", 76880 /* USB2D_DEVINTRMASK */ "", 76881 /* USB2D_DEVSTATUS */ "", 76882 /* USB2D_ENDPNTINTR */ "", 76883 /* USB2D_ENDPNTINTRMASK */ "", 76884 /* USB2D_ENDPNT_IN_BUFFER_0 */ "", 76885 /* USB2D_ENDPNT_IN_BUFFER_1 */ "", 76886 /* USB2D_ENDPNT_IN_BUFFER_2 */ "", 76887 /* USB2D_ENDPNT_IN_BUFFER_3 */ "", 76888 /* USB2D_ENDPNT_IN_BUFFER_4 */ "", 76889 /* USB2D_ENDPNT_IN_BUFFER_5 */ "", 76890 /* USB2D_ENDPNT_IN_BUFFER_6 */ "", 76891 /* USB2D_ENDPNT_IN_BUFFER_7 */ "", 76892 /* USB2D_ENDPNT_IN_BUFFER_8 */ "", 76893 /* USB2D_ENDPNT_IN_BUFFER_9 */ "", 76894 /* USB2D_ENDPNT_IN_CTRL_0 */ "", 76895 /* USB2D_ENDPNT_IN_CTRL_1 */ "", 76896 /* USB2D_ENDPNT_IN_CTRL_2 */ "", 76897 /* USB2D_ENDPNT_IN_CTRL_3 */ "", 76898 /* USB2D_ENDPNT_IN_CTRL_4 */ "", 76899 /* USB2D_ENDPNT_IN_CTRL_5 */ "", 76900 /* USB2D_ENDPNT_IN_CTRL_6 */ "", 76901 /* USB2D_ENDPNT_IN_CTRL_7 */ "", 76902 /* USB2D_ENDPNT_IN_CTRL_8 */ "", 76903 /* USB2D_ENDPNT_IN_CTRL_9 */ "", 76904 /* USB2D_ENDPNT_IN_DATADESCR_0 */ "", 76905 /* USB2D_ENDPNT_IN_DATADESCR_1 */ "", 76906 /* USB2D_ENDPNT_IN_DATADESCR_2 */ "", 76907 /* USB2D_ENDPNT_IN_DATADESCR_3 */ "", 76908 /* USB2D_ENDPNT_IN_DATADESCR_4 */ "", 76909 /* USB2D_ENDPNT_IN_DATADESCR_5 */ "", 76910 /* USB2D_ENDPNT_IN_DATADESCR_6 */ "", 76911 /* USB2D_ENDPNT_IN_DATADESCR_7 */ "", 76912 /* USB2D_ENDPNT_IN_DATADESCR_8 */ "", 76913 /* USB2D_ENDPNT_IN_DATADESCR_9 */ "", 76914 /* USB2D_ENDPNT_IN_MAXPACKSIZE_0 */ "", 76915 /* USB2D_ENDPNT_IN_MAXPACKSIZE_1 */ "", 76916 /* USB2D_ENDPNT_IN_MAXPACKSIZE_2 */ "", 76917 /* USB2D_ENDPNT_IN_MAXPACKSIZE_3 */ "", 76918 /* USB2D_ENDPNT_IN_MAXPACKSIZE_4 */ "", 76919 /* USB2D_ENDPNT_IN_MAXPACKSIZE_5 */ "", 76920 /* USB2D_ENDPNT_IN_MAXPACKSIZE_6 */ "", 76921 /* USB2D_ENDPNT_IN_MAXPACKSIZE_7 */ "", 76922 /* USB2D_ENDPNT_IN_MAXPACKSIZE_8 */ "", 76923 /* USB2D_ENDPNT_IN_MAXPACKSIZE_9 */ "", 76924 /* USB2D_ENDPNT_IN_STATUS_0 */ "", 76925 /* USB2D_ENDPNT_IN_STATUS_1 */ "", 76926 /* USB2D_ENDPNT_IN_STATUS_2 */ "", 76927 /* USB2D_ENDPNT_IN_STATUS_3 */ "", 76928 /* USB2D_ENDPNT_IN_STATUS_4 */ "", 76929 /* USB2D_ENDPNT_IN_STATUS_5 */ "", 76930 /* USB2D_ENDPNT_IN_STATUS_6 */ "", 76931 /* USB2D_ENDPNT_IN_STATUS_7 */ "", 76932 /* USB2D_ENDPNT_IN_STATUS_8 */ "", 76933 /* USB2D_ENDPNT_IN_STATUS_9 */ "", 76934 /* USB2D_ENDPNT_OUT_BUFSIZE_0 */ "", 76935 /* USB2D_ENDPNT_OUT_BUFSIZE_1 */ "", 76936 /* USB2D_ENDPNT_OUT_BUFSIZE_2 */ "", 76937 /* USB2D_ENDPNT_OUT_BUFSIZE_3 */ "", 76938 /* USB2D_ENDPNT_OUT_BUFSIZE_4 */ "", 76939 /* USB2D_ENDPNT_OUT_BUFSIZE_5 */ "", 76940 /* USB2D_ENDPNT_OUT_BUFSIZE_6 */ "", 76941 /* USB2D_ENDPNT_OUT_BUFSIZE_7 */ "", 76942 /* USB2D_ENDPNT_OUT_BUFSIZE_8 */ "", 76943 /* USB2D_ENDPNT_OUT_BUFSIZE_9 */ "", 76944 /* USB2D_ENDPNT_OUT_CTRL_0 */ "", 76945 /* USB2D_ENDPNT_OUT_CTRL_1 */ "", 76946 /* USB2D_ENDPNT_OUT_CTRL_2 */ "", 76947 /* USB2D_ENDPNT_OUT_CTRL_3 */ "", 76948 /* USB2D_ENDPNT_OUT_CTRL_4 */ "", 76949 /* USB2D_ENDPNT_OUT_CTRL_5 */ "", 76950 /* USB2D_ENDPNT_OUT_CTRL_6 */ "", 76951 /* USB2D_ENDPNT_OUT_CTRL_7 */ "", 76952 /* USB2D_ENDPNT_OUT_CTRL_8 */ "", 76953 /* USB2D_ENDPNT_OUT_CTRL_9 */ "", 76954 /* USB2D_ENDPNT_OUT_DATADESCR_0 */ "", 76955 /* USB2D_ENDPNT_OUT_DATADESCR_1 */ "", 76956 /* USB2D_ENDPNT_OUT_DATADESCR_2 */ "", 76957 /* USB2D_ENDPNT_OUT_DATADESCR_3 */ "", 76958 /* USB2D_ENDPNT_OUT_DATADESCR_4 */ "", 76959 /* USB2D_ENDPNT_OUT_DATADESCR_5 */ "", 76960 /* USB2D_ENDPNT_OUT_DATADESCR_6 */ "", 76961 /* USB2D_ENDPNT_OUT_DATADESCR_7 */ "", 76962 /* USB2D_ENDPNT_OUT_DATADESCR_8 */ "", 76963 /* USB2D_ENDPNT_OUT_DATADESCR_9 */ "", 76964 /* USB2D_ENDPNT_OUT_SETUPBUF_0 */ "", 76965 /* USB2D_ENDPNT_OUT_SETUPBUF_1 */ "", 76966 /* USB2D_ENDPNT_OUT_SETUPBUF_2 */ "", 76967 /* USB2D_ENDPNT_OUT_SETUPBUF_3 */ "", 76968 /* USB2D_ENDPNT_OUT_SETUPBUF_4 */ "", 76969 /* USB2D_ENDPNT_OUT_SETUPBUF_5 */ "", 76970 /* USB2D_ENDPNT_OUT_SETUPBUF_6 */ "", 76971 /* USB2D_ENDPNT_OUT_SETUPBUF_7 */ "", 76972 /* USB2D_ENDPNT_OUT_SETUPBUF_8 */ "", 76973 /* USB2D_ENDPNT_OUT_SETUPBUF_9 */ "", 76974 /* USB2D_ENDPNT_OUT_STATUS_0 */ "", 76975 /* USB2D_ENDPNT_OUT_STATUS_1 */ "", 76976 /* USB2D_ENDPNT_OUT_STATUS_2 */ "", 76977 /* USB2D_ENDPNT_OUT_STATUS_3 */ "", 76978 /* USB2D_ENDPNT_OUT_STATUS_4 */ "", 76979 /* USB2D_ENDPNT_OUT_STATUS_5 */ "", 76980 /* USB2D_ENDPNT_OUT_STATUS_6 */ "", 76981 /* USB2D_ENDPNT_OUT_STATUS_7 */ "", 76982 /* USB2D_ENDPNT_OUT_STATUS_8 */ "", 76983 /* USB2D_ENDPNT_OUT_STATUS_9 */ "", 76984 /* USB2D_IDM_IDM_INTERRUPT_STATUS */ "", 76985 /* USB2D_IDM_IDM_IO_CONTROL_DIRECT */ "", 76986 /* USB2D_IDM_IDM_IO_STATUS */ "", 76987 /* USB2D_IDM_IDM_RESET_CONTROL */ "", 76988 /* USB2D_IDM_IDM_RESET_STATUS */ "", 76989 /* USB2D_LPMCTRLSTATUS */ "", 76990 /* USB2D_RECPACKFRAMNO_0 */ "", 76991 /* USB2D_RECPACKFRAMNO_1 */ "", 76992 /* USB2D_RECPACKFRAMNO_2 */ "", 76993 /* USB2D_RECPACKFRAMNO_3 */ "", 76994 /* USB2D_RECPACKFRAMNO_4 */ "", 76995 /* USB2D_RECPACKFRAMNO_5 */ "", 76996 /* USB2D_RECPACKFRAMNO_6 */ "", 76997 /* USB2D_RECPACKFRAMNO_7 */ "", 76998 /* USB2D_RECPACKFRAMNO_8 */ "", 76999 /* USB2D_RECPACKFRAMNO_9 */ "", 77000 /* USB2D_RELEASE_NUMBER */ "", 77001 /* USB2D_UDC20_ENDPOINT0 */ "", 77002 /* USB2D_UDC20_ENDPOINT1 */ "", 77003 /* USB2D_UDC20_ENDPOINT2 */ "", 77004 /* USB2D_UDC20_ENDPOINT3 */ "", 77005 /* USB2D_UDC20_ENDPOINT4 */ "", 77006 /* USB2D_UDC20_ENDPOINT5 */ "", 77007 /* USB2D_UDC20_ENDPOINT6 */ "", 77008 /* USB2D_UDC20_ENDPOINT7 */ "", 77009 /* USB2D_UDC20_ENDPOINT8 */ "", 77010 /* USB2D_UDC20_ENDPOINT9 */ "", 77011 /* USB2_IDM_IDM_INTERRUPT_STATUS */ "", 77012 /* USB2_IDM_IDM_IO_CONTROL_DIRECT */ "", 77013 /* USB2_IDM_IDM_IO_STATUS */ "", 77014 /* USB2_IDM_IDM_RESET_CONTROL */ "", 77015 /* USB2_IDM_IDM_RESET_STATUS */ "", 77016 /* USBD_BDC_AIUDMA */ "", 77017 /* USBD_BDC_AIUIEPS0 */ "", 77018 /* USBD_BDC_AIUIEPS1 */ "", 77019 /* USBD_BDC_AIUIEPS2 */ "", 77020 /* USBD_BDC_AIUIEPS3 */ "", 77021 /* USBD_BDC_AIUIEPS4 */ "", 77022 /* USBD_BDC_AIUIEPS5 */ "", 77023 /* USBD_BDC_AIUOEPS0 */ "", 77024 /* USBD_BDC_AIUOEPS1 */ "", 77025 /* USBD_BDC_AIUOEPS3 */ "", 77026 /* USBD_BDC_AIUOEPS4 */ "", 77027 /* USBD_BDC_AIUOEPS5 */ "", 77028 /* USBD_BDC_AIUOPS2 */ "", 77029 /* USBD_BDC_AXILPM */ "", 77030 /* USBD_BDC_AXIQOS */ "", 77031 /* USBD_BDC_AXIRDA */ "", 77032 /* USBD_BDC_AXIWRA */ "", 77033 /* USBD_BDC_BDCCAP0 */ "", 77034 /* USBD_BDC_BDCCAP1 */ "", 77035 /* USBD_BDC_BDCCFG0 */ "", 77036 /* USBD_BDC_BDCCFG1 */ "", 77037 /* USBD_BDC_BDCSC */ "", 77038 /* USBD_BDC_BIUSPC */ "", 77039 /* USBD_BDC_CMDPAR0 */ "", 77040 /* USBD_BDC_CMDPAR1 */ "", 77041 /* USBD_BDC_CMDPAR2 */ "", 77042 /* USBD_BDC_CMDSC */ "", 77043 /* USBD_BDC_CSRSPC */ "", 77044 /* USBD_BDC_DVCNPH */ "", 77045 /* USBD_BDC_DVCNPL */ "", 77046 /* USBD_BDC_DVCSA */ "", 77047 /* USBD_BDC_DVCSB */ "", 77048 /* USBD_BDC_DVCSC */ "", 77049 /* USBD_BDC_DVCSD */ "", 77050 /* USBD_BDC_DVCSTP */ "", 77051 /* USBD_BDC_ECHAIU */ "", 77052 /* USBD_BDC_ECHBIU */ "", 77053 /* USBD_BDC_ECHCSR */ "", 77054 /* USBD_BDC_ECHDVC */ "", 77055 /* USBD_BDC_ECHFSC */ "", 77056 /* USBD_BDC_ECHIRA */ "", 77057 /* USBD_BDC_ECHLNK */ "", 77058 /* USBD_BDC_ECHPHY */ "", 77059 /* USBD_BDC_ECHPRT */ "", 77060 /* USBD_BDC_ECHRBV */ "", 77061 /* USBD_BDC_ECHRSV */ "", 77062 /* USBD_BDC_ECHRSV2 */ "", 77063 /* USBD_BDC_EPS0 */ "", 77064 /* USBD_BDC_EPS1 */ "", 77065 /* USBD_BDC_EPS2 */ "", 77066 /* USBD_BDC_EPS3 */ "", 77067 /* USBD_BDC_EPS4 */ "", 77068 /* USBD_BDC_EPS5 */ "", 77069 /* USBD_BDC_EPS6 */ "", 77070 /* USBD_BDC_EPS7 */ "", 77071 /* USBD_BDC_EXCPBA */ "", 77072 /* USBD_BDC_FSCHIC */ "", 77073 /* USBD_BDC_FSCHOC */ "", 77074 /* USBD_BDC_FSCIBDC0 */ "", 77075 /* USBD_BDC_FSCIBDC1 */ "", 77076 /* USBD_BDC_FSCIBDC2 */ "", 77077 /* USBD_BDC_FSCIBDC3 */ "", 77078 /* USBD_BDC_FSCIBDC4 */ "", 77079 /* USBD_BDC_FSCIBDC5 */ "", 77080 /* USBD_BDC_FSCIBDC6 */ "", 77081 /* USBD_BDC_FSCICH0 */ "", 77082 /* USBD_BDC_FSCICH1 */ "", 77083 /* USBD_BDC_FSCICH2 */ "", 77084 /* USBD_BDC_FSCICH3 */ "", 77085 /* USBD_BDC_FSCICH4 */ "", 77086 /* USBD_BDC_FSCICH5 */ "", 77087 /* USBD_BDC_FSCICH6 */ "", 77088 /* USBD_BDC_FSCICHX0 */ "", 77089 /* USBD_BDC_FSCICHX1 */ "", 77090 /* USBD_BDC_FSCICHX2 */ "", 77091 /* USBD_BDC_FSCICHX3 */ "", 77092 /* USBD_BDC_FSCICHX4 */ "", 77093 /* USBD_BDC_FSCICHX5 */ "", 77094 /* USBD_BDC_FSCICHX6 */ "", 77095 /* USBD_BDC_FSCLIC */ "", 77096 /* USBD_BDC_FSCLOC */ "", 77097 /* USBD_BDC_FSCNIC */ "", 77098 /* USBD_BDC_FSCNOC */ "", 77099 /* USBD_BDC_FSCOBDC1 */ "", 77100 /* USBD_BDC_FSCOBDC2 */ "", 77101 /* USBD_BDC_FSCOBDC3 */ "", 77102 /* USBD_BDC_FSCOBDC4 */ "", 77103 /* USBD_BDC_FSCOBDC5 */ "", 77104 /* USBD_BDC_FSCOBDC6 */ "", 77105 /* USBD_BDC_FSCODBC0 */ "", 77106 /* USBD_BDC_FSCOUT */ "", 77107 /* USBD_BDC_INTCLS0 */ "", 77108 /* USBD_BDC_INTCLS1 */ "", 77109 /* USBD_BDC_INTCLS2 */ "", 77110 /* USBD_BDC_INTCLS3 */ "", 77111 /* USBD_BDC_IRAADR */ "", 77112 /* USBD_BDC_IRADAT */ "", 77113 /* USBD_BDC_LNKHSC */ "", 77114 /* USBD_BDC_LNKHSR */ "", 77115 /* USBD_BDC_MFNUM */ "", 77116 /* USBD_BDC_OSC0 */ "", 77117 /* USBD_BDC_OSC1 */ "", 77118 /* USBD_BDC_OSC2 */ "", 77119 /* USBD_BDC_OSC3 */ "", 77120 /* USBD_BDC_PHYSSP */ "", 77121 /* USBD_BDC_PHYU2P */ "", 77122 /* USBD_BDC_PRTHSC */ "", 77123 /* USBD_BDC_PRTHSR */ "", 77124 /* USBD_BDC_RBVMGN */ "", 77125 /* USBD_BDC_RBVPDT */ "", 77126 /* USBD_BDC_SPBBAH */ "", 77127 /* USBD_BDC_SPBBAL */ "", 77128 /* USBD_BDC_SRRBAH0 */ "", 77129 /* USBD_BDC_SRRBAH1 */ "", 77130 /* USBD_BDC_SRRBAH2 */ "", 77131 /* USBD_BDC_SRRBAH3 */ "", 77132 /* USBD_BDC_SRRBAL0 */ "", 77133 /* USBD_BDC_SRRBAL1 */ "", 77134 /* USBD_BDC_SRRBAL2 */ "", 77135 /* USBD_BDC_SRRBAL3 */ "", 77136 /* USBD_BDC_SRRINT0 */ "", 77137 /* USBD_BDC_SRRINT1 */ "", 77138 /* USBD_BDC_SRRINT2 */ "", 77139 /* USBD_BDC_SRRINT3 */ "", 77140 /* USBD_BDC_USPPM2 */ "", 77141 /* USBD_BDC_USPPMS */ "", 77142 /* USBD_BDC_USPSC */ "", 77143 /* USBD_BDC_USPTDS */ "", 77144 /* USBD_BDC_XSFNTF */ "", 77145 /* USBH_ASYNCLISTADDR */ "", 77146 /* USBH_CONFIGFLAG */ "", 77147 /* USBH_CTRLDSSEGMENT */ "", 77148 /* USBH_EHCI_INCRX_STRAP */ "", 77149 /* USBH_EHCI_LPSMC_STATE */ "", 77150 /* USBH_EHCI_STATUS */ "", 77151 /* USBH_EHCI_XFER */ "", 77152 /* USBH_FRAME_LENADJ */ "", 77153 /* USBH_FRINDEX */ "", 77154 /* USBH_GPIO_OE */ "", 77155 /* USBH_GPIO_SEL */ "", 77156 /* USBH_HCBULKCURRENTED */ "", 77157 /* USBH_HCBULKHEADED */ "", 77158 /* USBH_HCCAPBASE */ "", 77159 /* USBH_HCCOMMANDSTATUS */ "", 77160 /* USBH_HCCONTOLCURRENTED */ "", 77161 /* USBH_HCCONTROL */ "", 77162 /* USBH_HCCONTROLHEADED */ "", 77163 /* USBH_HCCPARAMS */ "", 77164 /* USBH_HCDONEHEAD */ "", 77165 /* USBH_HCFMINTERVAL */ "", 77166 /* USBH_HCFMNUMBER */ "", 77167 /* USBH_HCFMREMAINING */ "", 77168 /* USBH_HCHCCA */ "", 77169 /* USBH_HCINTERRUPTDISABLE */ "", 77170 /* USBH_HCINTERRUPTENABLE */ "", 77171 /* USBH_HCINTERRUPTSTATUS */ "", 77172 /* USBH_HCLSTHRESHOLD */ "", 77173 /* USBH_HCPERIODCURRENTED */ "", 77174 /* USBH_HCPERIODICSTART */ "", 77175 /* USBH_HCREVISION */ "", 77176 /* USBH_HCRHDESCRIPTORA */ "", 77177 /* USBH_HCRHDESCRIPTORB */ "", 77178 /* USBH_HCRHPORT00 */ "", 77179 /* USBH_HCRHPORT01 */ "", 77180 /* USBH_HCRHPORT02 */ "", 77181 /* USBH_HCRHSTATUS */ "", 77182 /* USBH_HCSPARAMS */ "", 77183 /* USBH_INSNREG00 */ "", 77184 /* USBH_INSNREG01 */ "", 77185 /* USBH_INSNREG02 */ "", 77186 /* USBH_INSNREG03 */ "", 77187 /* USBH_INSNREG04 */ "", 77188 /* USBH_INSNREG05 */ "", 77189 /* USBH_INSNREG06 */ "", 77190 /* USBH_INSNREG07 */ "", 77191 /* USBH_INSNREG08 */ "", 77192 /* USBH_INTR_CONTROL */ "", 77193 /* USBH_MDIO_CTRL */ "", 77194 /* USBH_MDIO_RDDAT */ "", 77195 /* USBH_OHCI_CCS_STS */ "", 77196 /* USBH_OHCI_EHCI_STRAP */ "", 77197 /* USBH_OHCI_PWR_STS */ "", 77198 /* USBH_PERIODICLISTBASE */ "", 77199 /* USBH_PHY_CTRL_P0 */ "", 77200 /* USBH_PHY_CTRL_P1 */ "", 77201 /* USBH_PHY_CTRL_P2 */ "", 77202 /* USBH_PORTSC_0 */ "", 77203 /* USBH_PORTSC_1 */ "", 77204 /* USBH_PORTSC_2 */ "", 77205 /* USBH_SB_ADDRHI */ "", 77206 /* USBH_SHIM_CTRL */ "", 77207 /* USBH_SHIM_MASTER_STATUS */ "", 77208 /* USBH_SHIM_SLAVE_STATUS */ "", 77209 /* USBH_TP_CTL */ "", 77210 /* USBH_TP_OUTP0 */ "", 77211 /* USBH_TP_OUTP1 */ "", 77212 /* USBH_TP_OUTP2 */ "", 77213 /* USBH_USB2H_STDCELL_SRAM_PARAM */ "", 77214 /* USBH_USBCMD */ "", 77215 /* USBH_USBINTR */ "", 77216 /* USBH_USBSTS */ "", 77217 /* USBH_UTMI_P0CTL */ "", 77218 /* USBH_UTMI_P1CTL */ "", 77219 /* USBH_UTMI_P2CTL */ "", 77220 /* USBH_XHC_AIUCFG */ "", 77221 /* USBH_XHC_AIUDMA */ "", 77222 /* USBH_XHC_AIUFLA */ "", 77223 /* USBH_XHC_AXILPM */ "", 77224 /* USBH_XHC_AXIQOS */ "", 77225 /* USBH_XHC_AXIRDA */ "", 77226 /* USBH_XHC_AXIWRA */ "", 77227 /* USBH_XHC_BIUSPC */ "", 77228 /* USBH_XHC_CONFIG */ "", 77229 /* USBH_XHC_CPARAMS1 */ "", 77230 /* USBH_XHC_CPARAMS2 */ "", 77231 /* USBH_XHC_CPLIVER */ "", 77232 /* USBH_XHC_CRCRH */ "", 77233 /* USBH_XHC_CRCRL */ "", 77234 /* USBH_XHC_CSRSPC */ "", 77235 /* USBH_XHC_CTTMTS0 */ "", 77236 /* USBH_XHC_CTTMTS1 */ "", 77237 /* USBH_XHC_DBLCMD */ "", 77238 /* USBH_XHC_DBLDVX1 */ "", 77239 /* USBH_XHC_DBLDVX2 */ "", 77240 /* USBH_XHC_DBLDVX3 */ "", 77241 /* USBH_XHC_DBLDVX4 */ "", 77242 /* USBH_XHC_DBLDVX5 */ "", 77243 /* USBH_XHC_DBLDVX6 */ "", 77244 /* USBH_XHC_DBLDVX7 */ "", 77245 /* USBH_XHC_DBLDVX8 */ "", 77246 /* USBH_XHC_DBLDVX9 */ "", 77247 /* USBH_XHC_DBLDVX10 */ "", 77248 /* USBH_XHC_DBLDVX11 */ "", 77249 /* USBH_XHC_DBLDVX12 */ "", 77250 /* USBH_XHC_DBLDVX13 */ "", 77251 /* USBH_XHC_DBLDVX14 */ "", 77252 /* USBH_XHC_DBLDVX15 */ "", 77253 /* USBH_XHC_DBLDVX16 */ "", 77254 /* USBH_XHC_DBOFF */ "", 77255 /* USBH_XHC_DCBAAPH */ "", 77256 /* USBH_XHC_DCBAAPL */ "", 77257 /* USBH_XHC_DNCTRL */ "", 77258 /* USBH_XHC_ECHAIU */ "", 77259 /* USBH_XHC_ECHBIU */ "", 77260 /* USBH_XHC_ECHCSR */ "", 77261 /* USBH_XHC_ECHCTT */ "", 77262 /* USBH_XHC_ECHDBG */ "", 77263 /* USBH_XHC_ECHFSC */ "", 77264 /* USBH_XHC_ECHHST */ "", 77265 /* USBH_XHC_ECHIOV */ "", 77266 /* USBH_XHC_ECHIRA */ "", 77267 /* USBH_XHC_ECHMSI */ "", 77268 /* USBH_XHC_ECHPMG */ "", 77269 /* USBH_XHC_ECHPMGCSD */ "", 77270 /* USBH_XHC_ECHPRT */ "", 77271 /* USBH_XHC_ECHRBV */ "", 77272 /* USBH_XHC_ECHRH2 */ "", 77273 /* USBH_XHC_ECHRHS */ "", 77274 /* USBH_XHC_ECHRSV2 */ "", 77275 /* USBH_XHC_ECHRSVO */ "", 77276 /* USBH_XHC_ECHSPT2 */ "", 77277 /* USBH_XHC_ECHSPT3 */ "", 77278 /* USBH_XHC_ECHSSP */ "", 77279 /* USBH_XHC_ECHU2P */ "", 77280 /* USBH_XHC_ERDPH0 */ "", 77281 /* USBH_XHC_ERDPH1 */ "", 77282 /* USBH_XHC_ERDPL0 */ "", 77283 /* USBH_XHC_ERDPL1 */ "", 77284 /* USBH_XHC_ERSTBAH0 */ "", 77285 /* USBH_XHC_ERSTBAH1 */ "", 77286 /* USBH_XHC_ERSTBAL0 */ "", 77287 /* USBH_XHC_ERSTBAL1 */ "", 77288 /* USBH_XHC_ERSTSZ0 */ "", 77289 /* USBH_XHC_ERSTSZ1 */ "", 77290 /* USBH_XHC_HSTDBG */ "", 77291 /* USBH_XHC_HSTNPH */ "", 77292 /* USBH_XHC_HSTNPL */ "", 77293 /* USBH_XHC_IMAN0 */ "", 77294 /* USBH_XHC_IMAN1 */ "", 77295 /* USBH_XHC_IMOD0 */ "", 77296 /* USBH_XHC_IMOD1 */ "", 77297 /* USBH_XHC_IRAADR */ "", 77298 /* USBH_XHC_IRADAT */ "", 77299 /* USBH_XHC_MFINDEX */ "", 77300 /* USBH_XHC_PAGESIZE */ "", 77301 /* USBH_XHC_PNSTR2 */ "", 77302 /* USBH_XHC_PORTLI1 */ "", 77303 /* USBH_XHC_PORTPM1 */ "", 77304 /* USBH_XHC_PORTSC1 */ "", 77305 /* USBH_XHC_PSUM2 */ "", 77306 /* USBH_XHC_PTSLTYP2 */ "", 77307 /* USBH_XHC_RTOFF */ "", 77308 /* USBH_XHC_SPARAMS1 */ "", 77309 /* USBH_XHC_SPARAMS2 */ "", 77310 /* USBH_XHC_SPARAMS3 */ "", 77311 /* USBH_XHC_USBCMD */ "", 77312 /* USBH_XHC_USBSTS */ "", 77313 /* USB_NIC_M0_IDM_IDM_INTERRUPT_STATUS */ "", 77314 /* USB_NIC_M0_IDM_IDM_RESET_CONTROL */ "", 77315 /* USB_NIC_M0_IDM_IDM_RESET_STATUS */ "", 77316 /* USER_OTP_BONDOPTION_127_96_REG */ "", 77317 /* USER_OTP_BONDOPTION_159_128_REG */ "", 77318 /* USER_OTP_BONDOPTION_191_160_REG */ "", 77319 /* USER_OTP_BONDOPTION_223_192_REG */ "", 77320 /* USER_OTP_BONDOPTION_255_224_REG */ "", 77321 /* USER_OTP_BONDOPTION_287_256_REG */ "", 77322 /* USER_OTP_BONDOPTION_319_288_REG */ "", 77323 /* USER_OTP_BONDOPTION_31_0_REG */ "", 77324 /* USER_OTP_BONDOPTION_351_320_REG */ "", 77325 /* USER_OTP_BONDOPTION_383_352_REG */ "", 77326 /* USER_OTP_BONDOPTION_415_384_REG */ "", 77327 /* USER_OTP_BONDOPTION_447_416_REG */ "", 77328 /* USER_OTP_BONDOPTION_479_448_REG */ "", 77329 /* USER_OTP_BONDOPTION_511_480_REG */ "", 77330 /* USER_OTP_BONDOPTION_63_32_REG */ "", 77331 /* USER_OTP_BONDOPTION_95_64_REG */ "", 77332 /* USER_TRUNK_HASH_SELECT */ "", 77333 /* USE_SP_SHARED */ "", 77334 /* VBS_FC_CONFIG */ "", 77335 /* VFI_1_PARITY_CONTROL */ "", 77336 /* VFI_1_PARITY_STATUS_INTR */ "", 77337 /* VFI_1_PARITY_STATUS_NACK */ "", 77338 /* VFI_DBGCTRL */ "VFI_CONTROL", 77339 /* VFI_ECC_CONTROL */ "", 77340 /* VFI_PARITY_CONTROL */ "", 77341 /* VFI_PARITY_STATUS */ "", 77342 /* VFI_PARITY_STATUS_INTR */ "", 77343 /* VFI_PARITY_STATUS_NACK */ "", 77344 /* VFI_PDA_CONTROL */ "", 77345 /* VFP_CAM_BIST_CONFIG */ "", 77346 /* VFP_CAM_BIST_CONFIG_2 */ "", 77347 /* VFP_CAM_BIST_CONFIG_64 */ "", 77348 /* VFP_CAM_BIST_CONFIG_2_PIPE0 */ "", 77349 /* VFP_CAM_BIST_CONFIG_2_PIPE1 */ "", 77350 /* VFP_CAM_BIST_CONFIG_2_PIPE2 */ "", 77351 /* VFP_CAM_BIST_CONFIG_2_PIPE3 */ "", 77352 /* VFP_CAM_BIST_CONFIG_64_PIPE0 */ "", 77353 /* VFP_CAM_BIST_CONFIG_64_PIPE1 */ "", 77354 /* VFP_CAM_BIST_CONFIG_64_PIPE2 */ "", 77355 /* VFP_CAM_BIST_CONFIG_64_PIPE3 */ "", 77356 /* VFP_CAM_BIST_CONFIG_64_PIPE4 */ "", 77357 /* VFP_CAM_BIST_CONFIG_64_PIPE5 */ "", 77358 /* VFP_CAM_BIST_CONFIG_64_PIPE6 */ "", 77359 /* VFP_CAM_BIST_CONFIG_64_PIPE7 */ "", 77360 /* VFP_CAM_BIST_CONFIG_PIPE0 */ "", 77361 /* VFP_CAM_BIST_CONFIG_PIPE1 */ "", 77362 /* VFP_CAM_BIST_CONFIG_PIPE2 */ "", 77363 /* VFP_CAM_BIST_CONFIG_PIPE3 */ "", 77364 /* VFP_CAM_BIST_CONFIG_PIPE4 */ "", 77365 /* VFP_CAM_BIST_CONFIG_PIPE5 */ "", 77366 /* VFP_CAM_BIST_CONFIG_PIPE6 */ "", 77367 /* VFP_CAM_BIST_CONFIG_PIPE7 */ "", 77368 /* VFP_CAM_BIST_CONTROL */ "", 77369 /* VFP_CAM_BIST_CONTROL_PIPE0 */ "", 77370 /* VFP_CAM_BIST_CONTROL_PIPE1 */ "", 77371 /* VFP_CAM_BIST_CONTROL_PIPE2 */ "", 77372 /* VFP_CAM_BIST_CONTROL_PIPE3 */ "", 77373 /* VFP_CAM_BIST_CONTROL_PIPE4 */ "", 77374 /* VFP_CAM_BIST_CONTROL_PIPE5 */ "", 77375 /* VFP_CAM_BIST_CONTROL_PIPE6 */ "", 77376 /* VFP_CAM_BIST_CONTROL_PIPE7 */ "", 77377 /* VFP_CAM_BIST_DBG_DATA */ "", 77378 /* VFP_CAM_BIST_DBG_DATA_PIPE0 */ "", 77379 /* VFP_CAM_BIST_DBG_DATA_PIPE1 */ "", 77380 /* VFP_CAM_BIST_DBG_DATA_PIPE2 */ "", 77381 /* VFP_CAM_BIST_DBG_DATA_PIPE3 */ "", 77382 /* VFP_CAM_BIST_DBG_DATA_PIPE4 */ "", 77383 /* VFP_CAM_BIST_DBG_DATA_PIPE5 */ "", 77384 /* VFP_CAM_BIST_DBG_DATA_PIPE6 */ "", 77385 /* VFP_CAM_BIST_DBG_DATA_PIPE7 */ "", 77386 /* VFP_CAM_BIST_S10_STATUS */ "", 77387 /* VFP_CAM_BIST_S12_STATUS */ "", 77388 /* VFP_CAM_BIST_S14_STATUS */ "", 77389 /* VFP_CAM_BIST_S15_STATUS */ "", 77390 /* VFP_CAM_BIST_S2_STATUS */ "", 77391 /* VFP_CAM_BIST_S3_STATUS */ "", 77392 /* VFP_CAM_BIST_S5_STATUS */ "", 77393 /* VFP_CAM_BIST_S6_STATUS */ "", 77394 /* VFP_CAM_BIST_S8_STATUS */ "", 77395 /* VFP_CAM_BIST_STATUS */ "", 77396 /* VFP_CAM_BIST_STATUS_PIPE0 */ "", 77397 /* VFP_CAM_BIST_STATUS_PIPE1 */ "", 77398 /* VFP_CAM_BIST_STATUS_PIPE2 */ "", 77399 /* VFP_CAM_BIST_STATUS_PIPE3 */ "", 77400 /* VFP_CAM_BIST_STATUS_PIPE4 */ "", 77401 /* VFP_CAM_BIST_STATUS_PIPE5 */ "", 77402 /* VFP_CAM_BIST_STATUS_PIPE6 */ "", 77403 /* VFP_CAM_BIST_STATUS_PIPE7 */ "", 77404 /* VFP_CAM_CONTROL_3_THRU_0 */ "", 77405 /* VFP_CAM_CONTROL_SLICE_3_0 */ "", 77406 /* VFP_CAM_CONTROL_SLICE_3_0_64 */ "", 77407 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE0 */ "", 77408 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE1 */ "", 77409 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE2 */ "", 77410 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE3 */ "", 77411 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE4 */ "", 77412 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE5 */ "", 77413 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE6 */ "", 77414 /* VFP_CAM_CONTROL_SLICE_3_0_PIPE7 */ "", 77415 /* VFP_CAM_CONTROL_TM_7_THRU_0 */ "", 77416 /* VFP_CAM_DEBUG_DATA_0 */ "", 77417 /* VFP_CAM_DEBUG_DATA_1 */ "", 77418 /* VFP_CAM_DEBUG_DATA_2 */ "", 77419 /* VFP_CAM_DEBUG_DATA_3 */ "", 77420 /* VFP_CAM_DEBUG_DATA_4 */ "", 77421 /* VFP_CAM_DEBUG_DATA_5 */ "", 77422 /* VFP_CAM_DEBUG_GLOBAL_MASK */ "", 77423 /* VFP_CAM_DEBUG_SEND */ "", 77424 /* VFP_CAM_SER_CONTROL */ "", 77425 /* VFP_FLEX_COUNTER_STRENGTH */ "", 77426 /* VFP_KEY_CONTROL */ "", 77427 /* VFP_KEY_CONTROL_1 */ "", 77428 /* VFP_KEY_CONTROL_2 */ "", 77429 /* VFP_KEY_CONTROL_1_PIPE0 */ "", 77430 /* VFP_KEY_CONTROL_1_PIPE1 */ "", 77431 /* VFP_KEY_CONTROL_1_PIPE2 */ "", 77432 /* VFP_KEY_CONTROL_1_PIPE3 */ "", 77433 /* VFP_KEY_CONTROL_1_PIPE4 */ "", 77434 /* VFP_KEY_CONTROL_1_PIPE5 */ "", 77435 /* VFP_KEY_CONTROL_1_PIPE6 */ "", 77436 /* VFP_KEY_CONTROL_1_PIPE7 */ "", 77437 /* VFP_KEY_CONTROL_2_PIPE0 */ "", 77438 /* VFP_KEY_CONTROL_2_PIPE1 */ "", 77439 /* VFP_KEY_CONTROL_2_PIPE2 */ "", 77440 /* VFP_KEY_CONTROL_2_PIPE3 */ "", 77441 /* VFP_KEY_CONTROL_2_PIPE4 */ "", 77442 /* VFP_KEY_CONTROL_2_PIPE5 */ "", 77443 /* VFP_KEY_CONTROL_2_PIPE6 */ "", 77444 /* VFP_KEY_CONTROL_2_PIPE7 */ "", 77445 /* VFP_POLICY_ECC_CONTROL */ "", 77446 /* VFP_POLICY_PARITY_CONTROL */ "", 77447 /* VFP_POLICY_PARITY_STATUS_INTR */ "", 77448 /* VFP_POLICY_PARITY_STATUS_NACK */ "", 77449 /* VFP_POLICY_TABLE_PARITY_CONTROL */ "", 77450 /* VFP_POLICY_TABLE_PARITY_STATUS */ "", 77451 /* VFP_POLICY_TABLE_PDA */ "", 77452 /* VFP_POLICY_TABLE_RAM_CONTROL */ "", 77453 /* VFP_POLICY_TABLE_RAM_CONTROL_64 */ "VFP_POLICY_TABLE_RAM_CONTROL", 77454 /* VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE0 */ "VFP_POLICY_TABLE_RAM_CONTROL_PIPE0", 77455 /* VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE1 */ "VFP_POLICY_TABLE_RAM_CONTROL_PIPE1", 77456 /* VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE2 */ "VFP_POLICY_TABLE_RAM_CONTROL_PIPE2", 77457 /* VFP_POLICY_TABLE_RAM_CONTROL_64_PIPE3 */ "VFP_POLICY_TABLE_RAM_CONTROL_PIPE3", 77458 /* VFP_POLICY_TABLE_RAM_CONTROL_PIPE0 */ "", 77459 /* VFP_POLICY_TABLE_RAM_CONTROL_PIPE1 */ "", 77460 /* VFP_POLICY_TABLE_RAM_CONTROL_PIPE2 */ "", 77461 /* VFP_POLICY_TABLE_RAM_CONTROL_PIPE3 */ "", 77462 /* VFP_SLICE_CONTROL */ "", 77463 /* VFP_SLICE_CONTROL_PIPE0 */ "", 77464 /* VFP_SLICE_CONTROL_PIPE1 */ "", 77465 /* VFP_SLICE_CONTROL_PIPE2 */ "", 77466 /* VFP_SLICE_CONTROL_PIPE3 */ "", 77467 /* VFP_SLICE_CONTROL_PIPE4 */ "", 77468 /* VFP_SLICE_CONTROL_PIPE5 */ "", 77469 /* VFP_SLICE_CONTROL_PIPE6 */ "", 77470 /* VFP_SLICE_CONTROL_PIPE7 */ "", 77471 /* VFP_SLICE_MAP */ "", 77472 /* VFP_SLICE_MAP_PIPE0 */ "", 77473 /* VFP_SLICE_MAP_PIPE1 */ "", 77474 /* VFP_SLICE_MAP_PIPE2 */ "", 77475 /* VFP_SLICE_MAP_PIPE3 */ "", 77476 /* VFP_SLICE_MAP_PIPE4 */ "", 77477 /* VFP_SLICE_MAP_PIPE5 */ "", 77478 /* VFP_SLICE_MAP_PIPE6 */ "", 77479 /* VFP_SLICE_MAP_PIPE7 */ "", 77480 /* VFP_TCAM_BLKSEL */ "", 77481 /* VFP_TM */ "", 77482 /* VFP_TM_PIPE0 */ "", 77483 /* VFP_TM_PIPE1 */ "", 77484 /* VFP_TM_PIPE2 */ "", 77485 /* VFP_TM_PIPE3 */ "", 77486 /* VFP_TM_PIPE4 */ "", 77487 /* VFP_TM_PIPE5 */ "", 77488 /* VFP_TM_PIPE6 */ "", 77489 /* VFP_TM_PIPE7 */ "", 77490 /* VLAN_COS_MAP_PARITY_CONTROL */ "", 77491 /* VLAN_COS_MAP_PARITY_STATUS_INTR */ "", 77492 /* VLAN_COS_MAP_PARITY_STATUS_NACK */ "", 77493 /* VLAN_CTRL */ "", 77494 /* VLAN_DBGCTRL */ "VLAN_CONTROL", 77495 /* VLAN_DBGCTRL_0 */ "VLAN_CONTROL_0", 77496 /* VLAN_DBGCTRL_1 */ "VLAN_CONTROL_1", 77497 /* VLAN_DEFAULT_PBM */ "", 77498 /* VLAN_DEFAULT_PBM_HI */ "", 77499 /* VLAN_DEFAULT_PBM_LO */ "", 77500 /* VLAN_ECC_CONTROL */ "", 77501 /* VLAN_ECC_STATUS */ "", 77502 /* VLAN_ING_PRI_CNG_MAP_DBGCTRL */ "VLAN_ING_PRI_CNG_MAP_CONTROL", 77503 /* VLAN_MAC_AUX_HASH_CONTROL */ "", 77504 /* VLAN_MAC_DBGCTRL */ "VLAN_MAC_CONTROL", 77505 /* VLAN_MAC_OR_XLATE_PARITY_CONTROL */ "", 77506 /* VLAN_MAC_OR_XLATE_PARITY_STATUS */ "", 77507 /* VLAN_MEMORY_DBGCTRL */ "VLAN_MEMORY_CONTROL", 77508 /* VLAN_MEMORY_DBGCTRL_0 */ "VLAN_MEMORY_CONTROL_0", 77509 /* VLAN_MEMORY_DBGCTRL_1 */ "VLAN_MEMORY_CONTROL_1", 77510 /* VLAN_MEMORY_DBGCTRL_0_PIPE0 */ "VLAN_MEMORY_CONTROL_0_PIPE0", 77511 /* VLAN_MEMORY_DBGCTRL_0_PIPE1 */ "VLAN_MEMORY_CONTROL_0_PIPE1", 77512 /* VLAN_MEMORY_DBGCTRL_0_PIPE2 */ "VLAN_MEMORY_CONTROL_0_PIPE2", 77513 /* VLAN_MEMORY_DBGCTRL_0_PIPE3 */ "VLAN_MEMORY_CONTROL_0_PIPE3", 77514 /* VLAN_MEMORY_DBGCTRL_1_PIPE0 */ "VLAN_MEMORY_CONTROL_1_PIPE0", 77515 /* VLAN_MEMORY_DBGCTRL_1_PIPE1 */ "VLAN_MEMORY_CONTROL_1_PIPE1", 77516 /* VLAN_MEMORY_DBGCTRL_1_PIPE2 */ "VLAN_MEMORY_CONTROL_1_PIPE2", 77517 /* VLAN_MEMORY_DBGCTRL_1_PIPE3 */ "VLAN_MEMORY_CONTROL_1_PIPE3", 77518 /* VLAN_MPLS_PARITY_CONTROL */ "", 77519 /* VLAN_MPLS_PARITY_STATUS_INTR */ "", 77520 /* VLAN_MPLS_PARITY_STATUS_NACK */ "", 77521 /* VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROL */ "", 77522 /* VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTR */ "", 77523 /* VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_NACK */ "", 77524 /* VLAN_OR_VFI_MAC_LIMIT_ECC_CONTROL */ "", 77525 /* VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROL */ "", 77526 /* VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTR */ "", 77527 /* VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_NACK */ "", 77528 /* VLAN_PARITY_CONTROL */ "", 77529 /* VLAN_PARITY_STATUS */ "", 77530 /* VLAN_PARITY_STATUS_INTR */ "", 77531 /* VLAN_PARITY_STATUS_NACK */ "", 77532 /* VLAN_PROFILE_2_ECC_STATUS */ "", 77533 /* VLAN_PROFILE_2_PARITY_CONTROL */ "", 77534 /* VLAN_PROFILE_2_PARITY_STATUS */ "", 77535 /* VLAN_PROFILE_2_PARITY_STATUS_INTR */ "", 77536 /* VLAN_PROFILE_2_PARITY_STATUS_NACK */ "", 77537 /* VLAN_PROFILE_PARITY_CONTROL */ "", 77538 /* VLAN_PROFILE_TAB */ "", 77539 /* VLAN_PROTOCOL_DATA_DBGCTRL */ "VLAN_PROTOCOL_DATA_CONTROL", 77540 /* VLAN_PROTOCOL_DATA_DBGCTRL_PIPE0 */ "VLAN_PROTOCOL_DATA_CONTROL_PIPE0", 77541 /* VLAN_PROTOCOL_DATA_DBGCTRL_PIPE1 */ "VLAN_PROTOCOL_DATA_CONTROL_PIPE1", 77542 /* VLAN_PROTOCOL_DATA_DBGCTRL_PIPE2 */ "VLAN_PROTOCOL_DATA_CONTROL_PIPE2", 77543 /* VLAN_PROTOCOL_DATA_DBGCTRL_PIPE3 */ "VLAN_PROTOCOL_DATA_CONTROL_PIPE3", 77544 /* VLAN_PROTOCOL_DATA_PARITY_CONTROL */ "", 77545 /* VLAN_PROTOCOL_DATA_PARITY_STATUS */ "", 77546 /* VLAN_PROT_ECC_CONTROL */ "", 77547 /* VLAN_PROT_PARITY_CONTROL */ "", 77548 /* VLAN_PROT_PARITY_STATUS_INTR */ "", 77549 /* VLAN_PROT_PARITY_STATUS_NACK */ "", 77550 /* VLAN_RAM_DBGCTRL */ "VLAN_RAM_CONTROL", 77551 /* VLAN_RANGE_PARITY_CONTROL */ "", 77552 /* VLAN_RANGE_PARITY_STATUS_INTR */ "", 77553 /* VLAN_RANGE_PARITY_STATUS_NACK */ "", 77554 /* VLAN_STACKING_MODE */ "", 77555 /* VLAN_STG_ADDR_MASK */ "", 77556 /* VLAN_STG_DBGCTRL */ "VLAN_STG_CONTROL", 77557 /* VLAN_STG_ECC_STATUS */ "", 77558 /* VLAN_STG_PARITY_CONTROL */ "", 77559 /* VLAN_STG_PARITY_STATUS */ "", 77560 /* VLAN_STG_PARITY_STATUS_INTR */ "", 77561 /* VLAN_STG_PARITY_STATUS_NACK */ "", 77562 /* VLAN_SUBNET_CAM_BIST_CONFIG */ "", 77563 /* VLAN_SUBNET_CAM_BIST_CONFIG_64 */ "", 77564 /* VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE0 */ "", 77565 /* VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE1 */ "", 77566 /* VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE2 */ "", 77567 /* VLAN_SUBNET_CAM_BIST_CONFIG_64_PIPE3 */ "", 77568 /* VLAN_SUBNET_CAM_BIST_CONFIG_PIPE0 */ "", 77569 /* VLAN_SUBNET_CAM_BIST_CONFIG_PIPE1 */ "", 77570 /* VLAN_SUBNET_CAM_BIST_CONFIG_PIPE2 */ "", 77571 /* VLAN_SUBNET_CAM_BIST_CONFIG_PIPE3 */ "", 77572 /* VLAN_SUBNET_CAM_BIST_CONTROL */ "", 77573 /* VLAN_SUBNET_CAM_BIST_DBG_DATA */ "", 77574 /* VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE0 */ "", 77575 /* VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE1 */ "", 77576 /* VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE2 */ "", 77577 /* VLAN_SUBNET_CAM_BIST_DBG_DATA_PIPE3 */ "", 77578 /* VLAN_SUBNET_CAM_BIST_DEBUG_DATA_VALID */ "", 77579 /* VLAN_SUBNET_CAM_BIST_DEBUG_SEND */ "", 77580 /* VLAN_SUBNET_CAM_BIST_S10_STATUS */ "", 77581 /* VLAN_SUBNET_CAM_BIST_S2_STATUS */ "", 77582 /* VLAN_SUBNET_CAM_BIST_S3_STATUS */ "", 77583 /* VLAN_SUBNET_CAM_BIST_S5_STATUS */ "", 77584 /* VLAN_SUBNET_CAM_BIST_S6_STATUS */ "", 77585 /* VLAN_SUBNET_CAM_BIST_S8_STATUS */ "", 77586 /* VLAN_SUBNET_CAM_BIST_STATUS */ "", 77587 /* VLAN_SUBNET_CAM_BIST_STATUS_PIPE0 */ "", 77588 /* VLAN_SUBNET_CAM_BIST_STATUS_PIPE1 */ "", 77589 /* VLAN_SUBNET_CAM_BIST_STATUS_PIPE2 */ "", 77590 /* VLAN_SUBNET_CAM_BIST_STATUS_PIPE3 */ "", 77591 /* VLAN_SUBNET_CAM_CONTROL */ "", 77592 /* VLAN_SUBNET_CAM_DBGCTRL */ "VLAN_SUBNET_CAM_CONTROL", 77593 /* VLAN_SUBNET_CAM_DBGCTRL_PIPE0 */ "VLAN_SUBNET_CAM_CONTROL_PIPE0", 77594 /* VLAN_SUBNET_CAM_DBGCTRL_PIPE1 */ "VLAN_SUBNET_CAM_CONTROL_PIPE1", 77595 /* VLAN_SUBNET_CAM_DBGCTRL_PIPE2 */ "VLAN_SUBNET_CAM_CONTROL_PIPE2", 77596 /* VLAN_SUBNET_CAM_DBGCTRL_PIPE3 */ "VLAN_SUBNET_CAM_CONTROL_PIPE3", 77597 /* VLAN_SUBNET_DATA_DBGCTRL */ "VLAN_SUBNET_DATA_CONTROL", 77598 /* VLAN_SUBNET_DATA_DBGCTRL_PIPE0 */ "VLAN_SUBNET_DATA_CONTROL_PIPE0", 77599 /* VLAN_SUBNET_DATA_DBGCTRL_PIPE1 */ "VLAN_SUBNET_DATA_CONTROL_PIPE1", 77600 /* VLAN_SUBNET_DATA_DBGCTRL_PIPE2 */ "VLAN_SUBNET_DATA_CONTROL_PIPE2", 77601 /* VLAN_SUBNET_DATA_DBGCTRL_PIPE3 */ "VLAN_SUBNET_DATA_CONTROL_PIPE3", 77602 /* VLAN_SUBNET_DATA_PARITY_CONTROL */ "", 77603 /* VLAN_SUBNET_DATA_PARITY_STATUS */ "", 77604 /* VLAN_SUBNET_ONLY_BIST_CONFIG_64 */ "", 77605 /* VLAN_SUBNET_ONLY_BIST_CONFIG_64_PIPE0 */ "", 77606 /* VLAN_SUBNET_ONLY_BIST_CONFIG_64_PIPE1 */ "", 77607 /* VLAN_SUBNET_ONLY_BIST_STATUS */ "", 77608 /* VLAN_SUBNET_ONLY_BIST_STATUS_PIPE0 */ "", 77609 /* VLAN_SUBNET_ONLY_BIST_STATUS_PIPE1 */ "", 77610 /* VLAN_SUBNET_PARITY_CONTROL */ "", 77611 /* VLAN_SUBNET_PARITY_STATUS_INTR */ "", 77612 /* VLAN_SUBNET_PARITY_STATUS_NACK */ "", 77613 /* VLAN_TAG_ACTION_PROFILE_DBGCTRL */ "VLAN_TAG_ACTION_PROFILE_CONTROL", 77614 /* VLAN_XLATE_CAM_BIST_CONFIG */ "", 77615 /* VLAN_XLATE_CAM_BIST_CONTROL */ "", 77616 /* VLAN_XLATE_CAM_BIST_DBG_DATA */ "", 77617 /* VLAN_XLATE_CAM_BIST_DEBUG_DATA_VALID */ "", 77618 /* VLAN_XLATE_CAM_BIST_DEBUG_SEND */ "", 77619 /* VLAN_XLATE_CAM_BIST_S10_STATUS */ "", 77620 /* VLAN_XLATE_CAM_BIST_S2_STATUS */ "", 77621 /* VLAN_XLATE_CAM_BIST_S3_STATUS */ "", 77622 /* VLAN_XLATE_CAM_BIST_S5_STATUS */ "", 77623 /* VLAN_XLATE_CAM_BIST_S6_STATUS */ "", 77624 /* VLAN_XLATE_CAM_BIST_S8_STATUS */ "", 77625 /* VLAN_XLATE_CAM_BIST_STATUS */ "", 77626 /* VLAN_XLATE_CAM_CONTROL */ "", 77627 /* VLAN_XLATE_CAM_DBGCTRL */ "VLAN_XLATE_CAM_CONTROL", 77628 /* VLAN_XLATE_DATA_DBGCTRL */ "VLAN_XLATE_DATA_CONTROL", 77629 /* VLAN_XLATE_DATA_DBGCTRL_0 */ "VLAN_XLATE_DATA_CONTROL_0", 77630 /* VLAN_XLATE_DATA_DBGCTRL_1 */ "VLAN_XLATE_DATA_CONTROL_1", 77631 /* VLAN_XLATE_DATA_DBGCTRL_2 */ "VLAN_XLATE_DATA_CONTROL_2", 77632 /* VLAN_XLATE_DATA_DBGCTRL_3 */ "VLAN_XLATE_DATA_CONTROL_3", 77633 /* VLAN_XLATE_DATA_DBGCTRL_4 */ "VLAN_XLATE_DATA_CONTROL_4", 77634 /* VLAN_XLATE_DATA_DBGCTRL_5 */ "VLAN_XLATE_DATA_CONTROL_5", 77635 /* VLAN_XLATE_DATA_DBGCTRL_6 */ "VLAN_XLATE_DATA_CONTROL_6", 77636 /* VLAN_XLATE_DATA_DBGCTRL_7 */ "VLAN_XLATE_DATA_CONTROL_7", 77637 /* VLAN_XLATE_DBGCTRL */ "VLAN_XLATE_CONTROL", 77638 /* VLAN_XLATE_DBGCTRL_0 */ "VLAN_XLATE_CONTROL_0", 77639 /* VLAN_XLATE_DBGCTRL_1 */ "VLAN_XLATE_CONTROL_1", 77640 /* VLAN_XLATE_DBGCTRL_0_PIPE0 */ "VLAN_XLATE_CONTROL_0_PIPE0", 77641 /* VLAN_XLATE_DBGCTRL_0_PIPE1 */ "VLAN_XLATE_CONTROL_0_PIPE1", 77642 /* VLAN_XLATE_DBGCTRL_0_PIPE2 */ "VLAN_XLATE_CONTROL_0_PIPE2", 77643 /* VLAN_XLATE_DBGCTRL_0_PIPE3 */ "VLAN_XLATE_CONTROL_0_PIPE3", 77644 /* VLAN_XLATE_DEBUG_DATA_0 */ "", 77645 /* VLAN_XLATE_DEBUG_DATA_1 */ "", 77646 /* VLAN_XLATE_ECC_CONTROL */ "", 77647 /* VLAN_XLATE_HASH_CONTROL */ "", 77648 /* VLAN_XLATE_LP_DATA_DBGCTRL_0 */ "VLAN_XLATE_LP_DATA_CONTROL_0", 77649 /* VLAN_XLATE_LP_DATA_DBGCTRL_1 */ "VLAN_XLATE_LP_DATA_CONTROL_1", 77650 /* VLAN_XLATE_LP_DATA_DBGCTRL_2 */ "VLAN_XLATE_LP_DATA_CONTROL_2", 77651 /* VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE0 */ "VLAN_XLATE_LP_DATA_CONTROL_0_PIPE0", 77652 /* VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE1 */ "VLAN_XLATE_LP_DATA_CONTROL_0_PIPE1", 77653 /* VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE2 */ "VLAN_XLATE_LP_DATA_CONTROL_0_PIPE2", 77654 /* VLAN_XLATE_LP_DATA_DBGCTRL_0_PIPE3 */ "VLAN_XLATE_LP_DATA_CONTROL_0_PIPE3", 77655 /* VLAN_XLATE_PARITY_CONTROL */ "", 77656 /* VLAN_XLATE_PARITY_STATUS */ "", 77657 /* VLAN_XLATE_PARITY_STATUS_0 */ "", 77658 /* VLAN_XLATE_PARITY_STATUS_1 */ "", 77659 /* VLAN_XLATE_PARITY_STATUS_INTR_0 */ "", 77660 /* VLAN_XLATE_PARITY_STATUS_INTR_1 */ "", 77661 /* VLAN_XLATE_PARITY_STATUS_NACK_0 */ "", 77662 /* VLAN_XLATE_PARITY_STATUS_NACK_1 */ "", 77663 /* VMON_ADC_CTRL0 */ "", 77664 /* VMON_CTRL0 */ "", 77665 /* VMON_CTRL1 */ "", 77666 /* VOQFC_CNT */ "", 77667 /* VOQFC_MSG_PORT_SEL0 */ "", 77668 /* VOQFC_MSG_PORT_SEL1 */ "", 77669 /* VOQFC_MSG_PORT_SEL2 */ "", 77670 /* VOQFC_MSG_PORT_SEL3 */ "", 77671 /* VOQFC_MSG_PORT_SEL4 */ "", 77672 /* VOQFC_MSG_PORT_SEL5 */ "", 77673 /* VOQFC_MSG_PORT_SEL6 */ "", 77674 /* VOQFC_MSG_PORT_SEL7 */ "", 77675 /* VOQFC_STATE_MERGE_GRP0 */ "", 77676 /* VOQFC_STATE_MERGE_GRP1 */ "", 77677 /* VOQFC_STATE_MERGE_GRP2 */ "", 77678 /* VOQFC_STATE_MERGE_GRP3 */ "", 77679 /* VOQFC_STATE_MERGE_GRP4 */ "", 77680 /* VOQFC_STATE_MERGE_GRP5 */ "", 77681 /* VOQFC_STATE_MERGE_GRP6 */ "", 77682 /* VOQFC_STATE_MERGE_GRP7 */ "", 77683 /* VOQFC_STATE_PORT0_64 */ "VOQFC_STATE_PORT0", 77684 /* VOQFC_STATE_PORT1_64 */ "VOQFC_STATE_PORT1", 77685 /* VOQFC_STATE_PORT2_64 */ "VOQFC_STATE_PORT2", 77686 /* VOQFC_STATE_PORT3_64 */ "VOQFC_STATE_PORT3", 77687 /* VOQFC_STATE_PORT4_64 */ "VOQFC_STATE_PORT4", 77688 /* VOQFC_STATE_PORT5_64 */ "VOQFC_STATE_PORT5", 77689 /* VOQFC_STATE_PORT6_64 */ "VOQFC_STATE_PORT6", 77690 /* VOQFC_STATE_PORT7_64 */ "VOQFC_STATE_PORT7", 77691 /* VOQ_COS_MAP_PARITY_CONTROL */ "", 77692 /* VOQ_COS_MAP_PARITY_STATUS_INTR */ "", 77693 /* VOQ_COS_MAP_PARITY_STATUS_NACK */ "", 77694 /* VOQ_WRED_AVG_QSIZE */ "", 77695 /* VP_CAM_DBGCTRL */ "VP_CAM_CONTROL", 77696 /* VP_CAM_DBGCTRL_PIPE0 */ "VP_CAM_CONTROL_PIPE0", 77697 /* VP_CAM_DBGCTRL_PIPE1 */ "VP_CAM_CONTROL_PIPE1", 77698 /* VP_CAM_DBGCTRL_PIPE2 */ "VP_CAM_CONTROL_PIPE2", 77699 /* VP_CAM_DBGCTRL_PIPE3 */ "VP_CAM_CONTROL_PIPE3", 77700 /* VP_GROUP_CHECK_ENABLE */ "", 77701 /* VP_RAM_CONTROL_0 */ "", 77702 /* VP_RAM_CONTROL_1 */ "", 77703 /* VP_RAM_CONTROL_2 */ "", 77704 /* VP_RAM_CONTROL_3 */ "", 77705 /* VP_RAM_CONTROL_4 */ "", 77706 /* VP_RAM_CONTROL_5 */ "", 77707 /* VP_RAM_CONTROL_6 */ "", 77708 /* VP_RAM_CONTROL_7 */ "", 77709 /* VP_RAM_CONTROL_8 */ "", 77710 /* VP_RAM_CONTROL_0_PIPE0 */ "", 77711 /* VP_RAM_CONTROL_0_PIPE1 */ "", 77712 /* VP_RAM_CONTROL_0_PIPE2 */ "", 77713 /* VP_RAM_CONTROL_0_PIPE3 */ "", 77714 /* VP_RAM_CONTROL_1_PIPE0 */ "", 77715 /* VP_RAM_CONTROL_1_PIPE1 */ "", 77716 /* VP_RAM_CONTROL_1_PIPE2 */ "", 77717 /* VP_RAM_CONTROL_1_PIPE3 */ "", 77718 /* VP_RAM_CONTROL_2_PIPE0 */ "", 77719 /* VP_RAM_CONTROL_2_PIPE1 */ "", 77720 /* VP_RAM_CONTROL_2_PIPE2 */ "", 77721 /* VP_RAM_CONTROL_2_PIPE3 */ "", 77722 /* VP_RAM_CONTROL_3_PIPE0 */ "", 77723 /* VP_RAM_CONTROL_3_PIPE1 */ "", 77724 /* VP_RAM_CONTROL_3_PIPE2 */ "", 77725 /* VP_RAM_CONTROL_3_PIPE3 */ "", 77726 /* VP_RAM_CONTROL_4_PIPE0 */ "", 77727 /* VP_RAM_CONTROL_4_PIPE1 */ "", 77728 /* VP_RAM_CONTROL_4_PIPE2 */ "", 77729 /* VP_RAM_CONTROL_4_PIPE3 */ "", 77730 /* VP_RAM_CONTROL_5_PIPE0 */ "", 77731 /* VP_RAM_CONTROL_5_PIPE1 */ "", 77732 /* VP_RAM_CONTROL_5_PIPE2 */ "", 77733 /* VP_RAM_CONTROL_5_PIPE3 */ "", 77734 /* VP_RAM_CONTROL_6_PIPE0 */ "", 77735 /* VP_RAM_CONTROL_6_PIPE1 */ "", 77736 /* VP_RAM_CONTROL_6_PIPE2 */ "", 77737 /* VP_RAM_CONTROL_6_PIPE3 */ "", 77738 /* VP_RAM_CONTROL_7_PIPE0 */ "", 77739 /* VP_RAM_CONTROL_7_PIPE1 */ "", 77740 /* VP_RAM_CONTROL_7_PIPE2 */ "", 77741 /* VP_RAM_CONTROL_7_PIPE3 */ "", 77742 /* VP_RAM_CONTROL_8_PIPE0 */ "", 77743 /* VP_RAM_CONTROL_8_PIPE1 */ "", 77744 /* VP_RAM_CONTROL_8_PIPE2 */ "", 77745 /* VP_RAM_CONTROL_8_PIPE3 */ "", 77746 /* VP_SER_CONTROL */ "", 77747 /* VRF_CONTROL */ "", 77748 /* VRF_MASK */ "", 77749 /* VRF_PARITY_CONTROL */ "", 77750 /* VRF_PARITY_STATUS_INTR */ "", 77751 /* VRF_PARITY_STATUS_NACK */ "", 77752 /* VRF_PDA_CONTROL */ "", 77753 /* VXLAN_CONTROL */ "", 77754 /* VXLAN_DEFAULT_NETWORK_SVP */ "", 77755 /* VXLAN_EVPN_CONTROL */ "", 77756 /* VXLAN_IPV6_CONTROL */ "", 77757 /* VXLT1_MISS_TOCPU_DROP */ "", 77758 /* VXLT2_MISS_TOCPU_DROP */ "", 77759 /* VXLT_DEBUG_CONTROL_0 */ "", 77760 /* VXLT_DEBUG_CONTROL_1 */ "", 77761 /* VXLT_DEBUG_EVENT */ "", 77762 /* VXLT_DEBUG_EVENT_MASK */ "", 77763 /* VXLT_DEBUG_STATUS */ "", 77764 /* VXLT_DEBUG_STATUS_XLATE_0_A */ "", 77765 /* VXLT_DEBUG_STATUS_XLATE_0_B */ "", 77766 /* VXLT_DEBUG_STATUS_XLATE_1_A */ "", 77767 /* VXLT_DEBUG_STATUS_XLATE_1_B */ "", 77768 /* VXLT_FLEX_COUNTER_STRENGTH */ "", 77769 /* VXLT_PROTOCOL_INIT_DATA_DBGCTRL */ "VXLT_PROTOCOL_INIT_DATA", 77770 /* VXLT_RAM_CONTROL_DBGCTRL */ "VXLT_RAM_CONTROL", 77771 /* VXLT_SUBNET_DATA_RAM_DBGCTRL */ "VXLT_SUBNET_DATA_INIT_DATA", 77772 /* VXLT_SUBNET_ECC_RAM_DBGCTRL */ "VXLT_SUBNET_ECC_RAM_INIT_DATA", 77773 /* VXLT_XLATE_INIT_DATA_0_DBGCTRL */ "VXLT_XLATE_INIT_DATA_0", 77774 /* VXLT_XLATE_INIT_DATA_1_DBGCTRL */ "VXLT_XLATE_INIT_DATA_1", 77775 /* WAMUCELLCNTPG */ "", 77776 /* WAMUDROPCNT2BERR */ "", 77777 /* WAMUDROPCNTAGING */ "", 77778 /* WAMUDROPCNTGLBTHDIPKT */ "", 77779 /* WAMUDROPCNTLEN */ "", 77780 /* WAMUDROPCNTLENBYTE */ "", 77781 /* WAMUDROPCNTLRU */ "", 77782 /* WAMUDROPCNTNOLRU */ "", 77783 /* WAMUDROPCNTNOLRUBYTE */ "", 77784 /* WAMUDROPCNTTHD */ "", 77785 /* WAMUDROPCNTTHDBYTE */ "", 77786 /* WAMUDROPCNTTHDIBYTE */ "", 77787 /* WAMUDROPCNTTHDIPKT */ "", 77788 /* WAMUDROPCNTTHDOBYTE */ "", 77789 /* WAMUDROPCNTTHDOPKT */ "", 77790 /* WAMUDROPCNTTYPE */ "", 77791 /* WAMULINKMEMDEBUG */ "", 77792 /* WAMUMEMDEBUG */ "", 77793 /* WAMUMINLMTPG */ "", 77794 /* WAMUMINLMTPKTQ */ "", 77795 /* WAMUNONFRAGMCNT */ "", 77796 /* WAMUPARITYERRADR */ "", 77797 /* WAMUPKTCNTPG */ "", 77798 /* WAMUPKTCNTQ */ "", 77799 /* WAMUREASMBCNT */ "", 77800 /* WAMURSTOFFSETCELLPG */ "", 77801 /* WAMURSTOFFSETPKTPG */ "", 77802 /* WAMURSTOFFSETPKTQ */ "", 77803 /* WAMUSHRLMTCELLPG */ "", 77804 /* WAMUSHRLMTPKTPG */ "", 77805 /* WAMUSHRLMTPKTQ */ "", 77806 /* WAMUSTATUS */ "", 77807 /* WAMUTBFRAGMCNT */ "", 77808 /* WAMUTHDBYPASS */ "", 77809 /* WAMUTHDDROPST */ "", 77810 /* WAMUTOTALSHRLMTING */ "", 77811 /* WAMUTOTALSHRLMTPKTEGR */ "", 77812 /* WAMU_PG_FIRST_FRAGMENT_DROP_OFFSET */ "", 77813 /* WAMU_PG_MIN_CELL */ "", 77814 /* WAMU_PG_MIN_COUNT_CELL */ "", 77815 /* WAMU_PG_RESET_FLOOR_CELL */ "", 77816 /* WAMU_PG_RESET_OFFSET_CELL */ "", 77817 /* WAMU_PG_RESUME_LIMIT */ "", 77818 /* WAMU_PG_SHARED_COUNT_CELL */ "", 77819 /* WAMU_PG_SHARED_LIMIT_CELL */ "", 77820 /* WAMU_PG_XOFF_STATE */ "", 77821 /* WAMU_POOL_SELECT */ "", 77822 /* WAMU_PORT_SHARED_COUNT_CELL */ "", 77823 /* WAMU_PRI_GRP */ "", 77824 /* WAMU_TOTAL_COUNT_CELL */ "", 77825 /* WCL_CTL */ "", 77826 /* WCL_CUR_STS */ "", 77827 /* WCL_INTR_CLEAR */ "", 77828 /* WCL_INTR_ENABLE */ "", 77829 /* WCL_INTR_STS */ "", 77830 /* WCL_RX_LOST_LOCK_COUNT */ "", 77831 /* WDRRCOUNT */ "", 77832 /* WDT0_WDOGCONTROL */ "", 77833 /* WDT0_WDOGINTCLR */ "", 77834 /* WDT0_WDOGITCR */ "", 77835 /* WDT0_WDOGITOP */ "", 77836 /* WDT0_WDOGLOAD */ "", 77837 /* WDT0_WDOGLOCK */ "", 77838 /* WDT0_WDOGMIS */ "", 77839 /* WDT0_WDOGPCELLID0 */ "", 77840 /* WDT0_WDOGPCELLID1 */ "", 77841 /* WDT0_WDOGPCELLID2 */ "", 77842 /* WDT0_WDOGPCELLID3 */ "", 77843 /* WDT0_WDOGPERIPHID0 */ "", 77844 /* WDT0_WDOGPERIPHID1 */ "", 77845 /* WDT0_WDOGPERIPHID2 */ "", 77846 /* WDT0_WDOGPERIPHID3 */ "", 77847 /* WDT0_WDOGRIS */ "", 77848 /* WDT0_WDOGVALUE */ "", 77849 /* WDT1_WDOGCONTROL */ "", 77850 /* WDT1_WDOGINTCLR */ "", 77851 /* WDT1_WDOGITCR */ "", 77852 /* WDT1_WDOGITOP */ "", 77853 /* WDT1_WDOGLOAD */ "", 77854 /* WDT1_WDOGLOCK */ "", 77855 /* WDT1_WDOGMIS */ "", 77856 /* WDT1_WDOGPCELLID0 */ "", 77857 /* WDT1_WDOGPCELLID1 */ "", 77858 /* WDT1_WDOGPCELLID2 */ "", 77859 /* WDT1_WDOGPCELLID3 */ "", 77860 /* WDT1_WDOGPERIPHID0 */ "", 77861 /* WDT1_WDOGPERIPHID1 */ "", 77862 /* WDT1_WDOGPERIPHID2 */ "", 77863 /* WDT1_WDOGPERIPHID3 */ "", 77864 /* WDT1_WDOGRIS */ "", 77865 /* WDT1_WDOGVALUE */ "", 77866 /* WDT_0_RESET_MASK */ "", 77867 /* WDT_1_RESET_MASK */ "", 77868 /* WERRCOUNT */ "", 77869 /* WLAN_DECAP_NLF_MTU_CHECK */ "", 77870 /* WLAN_ENCAP_NLF_MTU_CHECK */ "", 77871 /* WLAN_SVP_ECC_CONTROL */ "", 77872 /* WLAN_SVP_ECC_STATUS_INTR */ "", 77873 /* WLAN_SVP_ECC_STATUS_NACK */ "", 77874 /* WL_DROP_POLICY */ "", 77875 /* WL_PORT_COUNT_CELL */ "", 77876 /* WL_PORT_COUNT_PACKET */ "", 77877 /* WL_PORT_SHARED_COUNT_CELL */ "", 77878 /* WL_PORT_SHARED_COUNT_PACKET */ "", 77879 /* WL_PORT_SHARED_LIMIT_CELL */ "", 77880 /* WL_PORT_SHARED_LIMIT_PACKET */ "", 77881 /* WORKFIFO_MEMORY_DEBUG_TM */ "", 77882 /* WREDAVGQSIZE_CELL */ "", 77883 /* WREDAVGQSIZE_PACKET */ "", 77884 /* WREDCONFIG_CELL */ "", 77885 /* WREDCONFIG_ECCP */ "", 77886 /* WREDCONFIG_PACKET */ "", 77887 /* WREDMEMDEBUG_AVG_QSIZE */ "", 77888 /* WREDMEMDEBUG_AVG_QSIZE_QG_TM */ "", 77889 /* WREDMEMDEBUG_AVG_QSIZE_TM */ "", 77890 /* WREDMEMDEBUG_AVG_QSIZE_X_PIPE_TM */ "", 77891 /* WREDMEMDEBUG_AVG_QSIZE_Y_PIPE_TM */ "", 77892 /* WREDMEMDEBUG_CFG_CELL */ "", 77893 /* WREDMEMDEBUG_CFG_PACKET */ "", 77894 /* WREDMEMDEBUG_CONFIG */ "", 77895 /* WREDMEMDEBUG_CONFIG_QG_TM */ "", 77896 /* WREDMEMDEBUG_CONFIG_TM */ "", 77897 /* WREDMEMDEBUG_CONFIG_X_PIPE_TM */ "", 77898 /* WREDMEMDEBUG_CONFIG_Y_PIPE_TM */ "", 77899 /* WREDMEMDEBUG_DROP_CURVE_PROFILE_TM */ "", 77900 /* WREDMEMDEBUG_DROP_MARK_PROFILES_TM */ "", 77901 /* WREDMEMDEBUG_DROP_THD_UC_DEQ0 */ "", 77902 /* WREDMEMDEBUG_DROP_THD_UC_DEQ1 */ "", 77903 /* WREDMEMDEBUG_DROP_THD_UC_ENQ0 */ "", 77904 /* WREDMEMDEBUG_DROP_THD_UC_ENQ1 */ "", 77905 /* WREDMEMDEBUG_MARK_THD_TM */ "", 77906 /* WREDMEMDEBUG_OPN_AVG_QSIZE */ "", 77907 /* WREDMEMDEBUG_OPN_CONFIG */ "", 77908 /* WREDMEMDEBUG_OPN_DROP_THD_DEQ */ "", 77909 /* WREDMEMDEBUG_OPN_DROP_THD_ENQ */ "", 77910 /* WREDMEMDEBUG_PORT_SP_DROP_THD */ "", 77911 /* WREDMEMDEBUG_PORT_SP_DROP_THD_MARK_TM */ "", 77912 /* WREDMEMDEBUG_PORT_SP_DROP_THD_TM */ "", 77913 /* WREDMEMDEBUG_PORT_SP_DROP_THD_X_PIPE_TM */ "", 77914 /* WREDMEMDEBUG_PORT_SP_DROP_THD_Y_PIPE_TM */ "", 77915 /* WREDMEMDEBUG_PORT_SP_SHARED_COUNT */ "", 77916 /* WREDMEMDEBUG_PORT_SP_SHARED_COUNT_TM */ "", 77917 /* WREDMEMDEBUG_PORT_SP_SHARED_COUNT_X_PIPE_TM */ "", 77918 /* WREDMEMDEBUG_PORT_SP_SHARED_COUNT_Y_PIPE_TM */ "", 77919 /* WREDMEMDEBUG_PROFILE */ "", 77920 /* WREDMEMDEBUG_QGROUP_DROP_THD */ "", 77921 /* WREDMEMDEBUG_QGROUP_DROP_THD_X_PIPE_TM */ "", 77922 /* WREDMEMDEBUG_QGROUP_DROP_THD_Y_PIPE_TM */ "", 77923 /* WREDMEMDEBUG_QGROUP_SHARED_COUNT */ "", 77924 /* WREDMEMDEBUG_QGROUP_SHARED_COUNT_X_PIPE_TM */ "", 77925 /* WREDMEMDEBUG_QGROUP_SHARED_COUNT_Y_PIPE_TM */ "", 77926 /* WREDMEMDEBUG_QUEUE_AVG_QSIZE */ "", 77927 /* WREDMEMDEBUG_QUEUE_CONFIG */ "", 77928 /* WREDMEMDEBUG_QUEUE_DROP_THD_DEQ */ "", 77929 /* WREDMEMDEBUG_QUEUE_DROP_THD_ENQ */ "", 77930 /* WREDMEMDEBUG_QUEUE_OPN_MAP */ "", 77931 /* WREDMEMDEBUG_THD_0_CELL */ "", 77932 /* WREDMEMDEBUG_THD_0_PACKET */ "", 77933 /* WREDMEMDEBUG_THD_1_CELL */ "", 77934 /* WREDMEMDEBUG_THD_1_PACKET */ "", 77935 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_0_TM */ "", 77936 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_1_TM */ "", 77937 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ */ "", 77938 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_0_TM */ "", 77939 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_X_PIPE_1_TM */ "", 77940 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_Y_PIPE_0_TM */ "", 77941 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_DEQ_Y_PIPE_1_TM */ "", 77942 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ */ "", 77943 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_0_TM */ "", 77944 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_X_PIPE_1_TM */ "", 77945 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_0_TM */ "", 77946 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_1_TM */ "", 77947 /* WREDMEMDEBUG_UC_QUEUE_DROP_THD_MARK_TM */ "", 77948 /* WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT */ "", 77949 /* WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_TM */ "", 77950 /* WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_X_PIPE_TM */ "", 77951 /* WREDMEMDEBUG_UC_QUEUE_TOTAL_COUNT_Y_PIPE_TM */ "", 77952 /* WREDPARAM_CELL */ "", 77953 /* WREDPARAM_END_CELL */ "", 77954 /* WREDPARAM_NONTCP_CELL */ "", 77955 /* WREDPARAM_NONTCP_PACKET */ "", 77956 /* WREDPARAM_PACKET */ "", 77957 /* WREDPARAM_PRI0_END_CELL */ "", 77958 /* WREDPARAM_PRI0_START_CELL */ "", 77959 /* WREDPARAM_RED_CELL */ "", 77960 /* WREDPARAM_RED_END_CELL */ "", 77961 /* WREDPARAM_RED_PACKET */ "", 77962 /* WREDPARAM_RED_START_CELL */ "", 77963 /* WREDPARAM_START_CELL */ "", 77964 /* WREDPARAM_YELLOW_CELL */ "", 77965 /* WREDPARAM_YELLOW_END_CELL */ "", 77966 /* WREDPARAM_YELLOW_PACKET */ "", 77967 /* WREDPARAM_YELLOW_START_CELL */ "", 77968 /* WRED_AVG_QSIZE */ "", 77969 /* WRED_AVG_QSIZE_PARITY_ERR_PTR */ "", 77970 /* WRED_AVG_QSIZE_QG_PARITY_ERR_PTR */ "", 77971 /* WRED_CONFIG */ "", 77972 /* WRED_CONFIG_PARITY_ERR_PTR */ "", 77973 /* WRED_CONFIG_QG_PARITY_ERR_PTR */ "", 77974 /* WRED_CONG_NOTIFICATION_RESOLUTION_TABLE */ "", 77975 /* WRED_DEBUG_ENQ_DROP_GLOBAL */ "", 77976 /* WRED_DEBUG_ENQ_DROP_PORT */ "", 77977 /* WRED_DROP_COUNTER */ "", 77978 /* WRED_DROP_CTR_CONFIG */ "", 77979 /* WRED_DROP_CTR_CONFIG_COLOR_MASK_QLAYER */ "", 77980 /* WRED_DROP_CTR_CONFIG_QLAYER_0 */ "", 77981 /* WRED_DROP_CTR_CONFIG_QLAYER_1 */ "", 77982 /* WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTR */ "", 77983 /* WRED_DROP_PROFILE_RED_PARITY_ERR_PTR */ "", 77984 /* WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTR */ "", 77985 /* WRED_DROP_THD_READ_CONTROL */ "", 77986 /* WRED_DROP_THD_READ_DATA */ "", 77987 /* WRED_EN_COR_ERR_RPT_X_PIPE */ "", 77988 /* WRED_EN_COR_ERR_RPT_Y_PIPE */ "", 77989 /* WRED_ERR_CLR */ "", 77990 /* WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTR */ "", 77991 /* WRED_MARK_PROFILE_RED_PARITY_ERR_PTR */ "", 77992 /* WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTR */ "", 77993 /* WRED_MARK_THD_PARITY_ERR_PTR */ "", 77994 /* WRED_MEM_INIT_STATUS */ "", 77995 /* WRED_MISCCONFIG */ "", 77996 /* WRED_PARITY_ERROR_BITMAP */ "", 77997 /* WRED_PARITY_ERROR_INFO */ "", 77998 /* WRED_PARITY_ERROR_INFO_2BIT */ "", 77999 /* WRED_PARITY_ERROR_MASK */ "", 78000 /* WRED_PARITY_ERROR_POINTER */ "", 78001 /* WRED_PARITY_ERR_COUNTER */ "", 78002 /* WRED_PARITY_ERR_STATUS */ "", 78003 /* WRED_POOL_INST_CONG_LIMIT_0 */ "", 78004 /* WRED_POOL_INST_CONG_LIMIT_1 */ "", 78005 /* WRED_POOL_INST_CONG_LIMIT_2 */ "", 78006 /* WRED_POOL_INST_CONG_LIMIT_3 */ "", 78007 /* WRED_POOL_INST_CONG_LIMIT_0_XPE0 */ "", 78008 /* WRED_POOL_INST_CONG_LIMIT_0_XPE1 */ "", 78009 /* WRED_POOL_INST_CONG_LIMIT_0_XPE2 */ "", 78010 /* WRED_POOL_INST_CONG_LIMIT_0_XPE3 */ "", 78011 /* WRED_POOL_INST_CONG_LIMIT_1_XPE0 */ "", 78012 /* WRED_POOL_INST_CONG_LIMIT_1_XPE1 */ "", 78013 /* WRED_POOL_INST_CONG_LIMIT_1_XPE2 */ "", 78014 /* WRED_POOL_INST_CONG_LIMIT_1_XPE3 */ "", 78015 /* WRED_POOL_INST_CONG_LIMIT_2_XPE0 */ "", 78016 /* WRED_POOL_INST_CONG_LIMIT_2_XPE1 */ "", 78017 /* WRED_POOL_INST_CONG_LIMIT_2_XPE2 */ "", 78018 /* WRED_POOL_INST_CONG_LIMIT_2_XPE3 */ "", 78019 /* WRED_POOL_INST_CONG_LIMIT_3_XPE0 */ "", 78020 /* WRED_POOL_INST_CONG_LIMIT_3_XPE1 */ "", 78021 /* WRED_POOL_INST_CONG_LIMIT_3_XPE2 */ "", 78022 /* WRED_POOL_INST_CONG_LIMIT_3_XPE3 */ "", 78023 /* WRED_PROFILE0_PARITY_ERROR_POINTER */ "", 78024 /* WRED_PROFILE1_PARITY_ERROR_POINTER */ "", 78025 /* WRED_PROFILE2_PARITY_ERROR_POINTER */ "", 78026 /* WRED_PROFILE3_PARITY_ERROR_POINTER */ "", 78027 /* WRED_PROFILE4_PARITY_ERROR_POINTER */ "", 78028 /* WRED_PROFILE5_PARITY_ERROR_POINTER */ "", 78029 /* WRED_PROFILE_PARITY_ERROR_BITMAP */ "", 78030 /* WRED_PROFILE_PARITY_ERROR_MASK */ "", 78031 /* WRED_QGROUP_THD_READ_CONTROL */ "", 78032 /* WRED_QGROUP_THD_READ_DATA */ "", 78033 /* WRED_REFRESH_CONTROL */ "", 78034 /* WRED_REFRESH_PORT_CONTROL */ "", 78035 /* WRED_REFRESH_PORT_CONTROL_0 */ "", 78036 /* WRED_REFRESH_PORT_CONTROL_1 */ "", 78037 /* WRED_REFRESH_PORT_CONTROL_2 */ "", 78038 /* WRED_REFRESH_TICK_ERROR_STATUS */ "", 78039 /* WRED_THD_0_ECCP */ "", 78040 /* WRED_THD_1_ECCP */ "", 78041 /* WRRWEIGHTS */ "", 78042 /* WRRWEIGHT_COS */ "WRRWEIGHTS_COS", 78043 /* WRRWEIGHT_COS_QGROUP */ "", 78044 /* WRRWEIGHT_COS_QLAYER */ "", 78045 /* XBOD_OVRFLW */ "", 78046 /* XCON_CCM_DEFECT_STATUS */ "", 78047 /* XGPORT_EXTRA_XGXS_NEWCTL_REG */ "", 78048 /* XGPORT_EXTRA_XGXS_NEWSTATUS0_REG */ "", 78049 /* XGPORT_EXTRA_XGXS_NEWSTATUS1_REG */ "", 78050 /* XGPORT_EXTRA_XGXS_NEWSTATUS2_REG */ "", 78051 /* XGPORT_EXTRA_XGXS_NEWSTATUS3_REG */ "", 78052 /* XGPORT_MODE_REG */ "", 78053 /* XGPORT_SERDES_CTL */ "", 78054 /* XGPORT_XGXS_CTRL */ "", 78055 /* XGPORT_XGXS_NEWCTL_REG */ "", 78056 /* XGPORT_XGXS_NEWSTATUS0_REG */ "", 78057 /* XGPORT_XGXS_NEWSTATUS1_REG */ "", 78058 /* XGPORT_XGXS_NEWSTATUS2_REG */ "", 78059 /* XGPORT_XGXS_NEWSTATUS3_REG */ "", 78060 /* XGPORT_XGXS_STAT */ "", 78061 /* XHOL_D0 */ "", 78062 /* XHOL_D1 */ "", 78063 /* XHOL_D2 */ "", 78064 /* XHOL_D3 */ "", 78065 /* XHOL_MH0 */ "", 78066 /* XHOL_MH1 */ "", 78067 /* XHOL_MH2 */ "", 78068 /* XHOL_MH3 */ "", 78069 /* XHOL_RX_MH_DATA0 */ "", 78070 /* XHOL_RX_MH_DATA1 */ "", 78071 /* XHOL_RX_MH_DATA2 */ "", 78072 /* XHOL_RX_MH_DATA3 */ "", 78073 /* XHOL_RX_MH_MASK0 */ "", 78074 /* XHOL_RX_MH_MASK1 */ "", 78075 /* XHOL_RX_MH_MASK2 */ "", 78076 /* XHOL_RX_MH_MASK3 */ "", 78077 /* XHOL_RX_PKT_DATA0 */ "", 78078 /* XHOL_RX_PKT_DATA1 */ "", 78079 /* XHOL_RX_PKT_DATA2 */ "", 78080 /* XHOL_RX_PKT_DATA3 */ "", 78081 /* XHOL_RX_PKT_MASK0 */ "", 78082 /* XHOL_RX_PKT_MASK1 */ "", 78083 /* XHOL_RX_PKT_MASK2 */ "", 78084 /* XHOL_RX_PKT_MASK3 */ "", 78085 /* XIBP_D0 */ "", 78086 /* XIBP_D1 */ "", 78087 /* XIBP_D2 */ "", 78088 /* XIBP_D3 */ "", 78089 /* XIBP_MH0 */ "", 78090 /* XIBP_MH1 */ "", 78091 /* XIBP_MH2 */ "", 78092 /* XIBP_MH3 */ "", 78093 /* XLMAC_B0_CLEAR_ECC_STATUS */ "", 78094 /* XLMAC_B0_CLEAR_FIFO_STATUS */ "", 78095 /* XLMAC_B0_CLEAR_RX_LSS_STATUS */ "", 78096 /* XLMAC_B0_CTRL */ "", 78097 /* XLMAC_B0_E2ECC_DATA_HDR_0 */ "", 78098 /* XLMAC_B0_E2ECC_DATA_HDR_1 */ "", 78099 /* XLMAC_B0_E2ECC_MODULE_HDR_0 */ "", 78100 /* XLMAC_B0_E2ECC_MODULE_HDR_1 */ "", 78101 /* XLMAC_B0_E2EFC_DATA_HDR_0 */ "", 78102 /* XLMAC_B0_E2EFC_DATA_HDR_1 */ "", 78103 /* XLMAC_B0_E2EFC_MODULE_HDR_0 */ "", 78104 /* XLMAC_B0_E2EFC_MODULE_HDR_1 */ "", 78105 /* XLMAC_B0_E2E_CTRL */ "", 78106 /* XLMAC_B0_ECC_CTRL */ "", 78107 /* XLMAC_B0_ECC_FORCE_DOUBLE_BIT_ERR */ "", 78108 /* XLMAC_B0_ECC_FORCE_SINGLE_BIT_ERR */ "", 78109 /* XLMAC_B0_EEE_1_SEC_LINK_STATUS_TIMER */ "", 78110 /* XLMAC_B0_EEE_CTRL */ "", 78111 /* XLMAC_B0_EEE_TIMERS */ "", 78112 /* XLMAC_B0_FIFO_STATUS */ "", 78113 /* XLMAC_B0_GMII_EEE_CTRL */ "", 78114 /* XLMAC_B0_HIGIG_HDR_0 */ "", 78115 /* XLMAC_B0_HIGIG_HDR_1 */ "", 78116 /* XLMAC_B0_LAG_FAILOVER_STATUS */ "", 78117 /* XLMAC_B0_LLFC_CTRL */ "", 78118 /* XLMAC_B0_MEM_CTRL */ "", 78119 /* XLMAC_B0_MODE */ "", 78120 /* XLMAC_B0_PAUSE_CTRL */ "", 78121 /* XLMAC_B0_PFC_CTRL */ "", 78122 /* XLMAC_B0_PFC_DA */ "", 78123 /* XLMAC_B0_PFC_OPCODE */ "", 78124 /* XLMAC_B0_PFC_TYPE */ "", 78125 /* XLMAC_B0_RX_CDC_ECC_STATUS */ "", 78126 /* XLMAC_B0_RX_CTRL */ "", 78127 /* XLMAC_B0_RX_LLFC_MSG_FIELDS */ "", 78128 /* XLMAC_B0_RX_LSS_CTRL */ "", 78129 /* XLMAC_B0_RX_LSS_STATUS */ "", 78130 /* XLMAC_B0_RX_MAC_SA */ "", 78131 /* XLMAC_B0_RX_MAX_SIZE */ "", 78132 /* XLMAC_B0_RX_VLAN_TAG */ "", 78133 /* XLMAC_B0_SPARE0 */ "", 78134 /* XLMAC_B0_SPARE1 */ "", 78135 /* XLMAC_B0_TIMESTAMP_ADJUST */ "", 78136 /* XLMAC_B0_TIMESTAMP_BYTE_ADJUST */ "", 78137 /* XLMAC_B0_TXFIFO_CELL_CNT */ "", 78138 /* XLMAC_B0_TXFIFO_CELL_REQ_CNT */ "", 78139 /* XLMAC_B0_TX_CDC_ECC_STATUS */ "", 78140 /* XLMAC_B0_TX_CRC_CORRUPT_CTRL */ "", 78141 /* XLMAC_B0_TX_CTRL */ "", 78142 /* XLMAC_B0_TX_LLFC_MSG_FIELDS */ "", 78143 /* XLMAC_B0_TX_MAC_SA */ "", 78144 /* XLMAC_B0_TX_TIMESTAMP_FIFO_DATA */ "", 78145 /* XLMAC_B0_TX_TIMESTAMP_FIFO_STATUS */ "", 78146 /* XLMAC_B0_VERSION_ID */ "", 78147 /* XLMAC_CLEAR_ECC_STATUS */ "", 78148 /* XLMAC_CLEAR_FIFO_STATUS */ "", 78149 /* XLMAC_CLEAR_RX_LSS_STATUS */ "", 78150 /* XLMAC_CTRL */ "", 78151 /* XLMAC_E2ECC_DATA_HDR_0 */ "", 78152 /* XLMAC_E2ECC_DATA_HDR_1 */ "", 78153 /* XLMAC_E2ECC_MODULE_HDR_0 */ "", 78154 /* XLMAC_E2ECC_MODULE_HDR_1 */ "", 78155 /* XLMAC_E2EFC_DATA_HDR_0 */ "", 78156 /* XLMAC_E2EFC_DATA_HDR_1 */ "", 78157 /* XLMAC_E2EFC_MODULE_HDR_0 */ "", 78158 /* XLMAC_E2EFC_MODULE_HDR_1 */ "", 78159 /* XLMAC_E2E_CTRL */ "", 78160 /* XLMAC_ECC_CTRL */ "", 78161 /* XLMAC_ECC_FORCE_DOUBLE_BIT_ERR */ "", 78162 /* XLMAC_ECC_FORCE_SINGLE_BIT_ERR */ "", 78163 /* XLMAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 78164 /* XLMAC_EEE_CTRL */ "", 78165 /* XLMAC_EEE_TIMERS */ "", 78166 /* XLMAC_FIFO_STATUS */ "", 78167 /* XLMAC_GMII_EEE_CTRL */ "", 78168 /* XLMAC_HIGIG_HDR_0 */ "", 78169 /* XLMAC_HIGIG_HDR_1 */ "", 78170 /* XLMAC_INTR_ENABLE */ "", 78171 /* XLMAC_INTR_STATUS */ "", 78172 /* XLMAC_LAG_FAILOVER_STATUS */ "", 78173 /* XLMAC_LLFC_CTRL */ "", 78174 /* XLMAC_MACSEC_CTRL */ "", 78175 /* XLMAC_MEM_CTRL */ "", 78176 /* XLMAC_MERGE_CLEAR_STATUS */ "", 78177 /* XLMAC_MERGE_CONFIG */ "", 78178 /* XLMAC_MERGE_CTRL_SECRET_CONFIG */ "", 78179 /* XLMAC_MERGE_FRG_CNT_CONFIG */ "", 78180 /* XLMAC_MERGE_RX_DEBUG_COUNTERS_CONFIG */ "", 78181 /* XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_0 */ "", 78182 /* XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_1 */ "", 78183 /* XLMAC_MERGE_RX_DEBUG_COUNTERS_STATUS_2 */ "", 78184 /* XLMAC_MERGE_RX_TIMEOUT_CONFIG */ "", 78185 /* XLMAC_MERGE_SMD_CONFIG_0 */ "", 78186 /* XLMAC_MERGE_SMD_CONFIG_1 */ "", 78187 /* XLMAC_MERGE_STATUS */ "", 78188 /* XLMAC_MERGE_TX_DEBUG_COUNTERS_CONFIG */ "", 78189 /* XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_0 */ "", 78190 /* XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_1 */ "", 78191 /* XLMAC_MERGE_TX_DEBUG_COUNTERS_STATUS_2 */ "", 78192 /* XLMAC_MERGE_VERIFY_STATE */ "", 78193 /* XLMAC_MODE */ "", 78194 /* XLMAC_PAUSE_CTRL */ "", 78195 /* XLMAC_PFC_CTRL */ "", 78196 /* XLMAC_PFC_DA */ "", 78197 /* XLMAC_PFC_OPCODE */ "", 78198 /* XLMAC_PFC_TYPE */ "", 78199 /* XLMAC_RX_CDC_ECC_STATUS */ "", 78200 /* XLMAC_RX_CTRL */ "", 78201 /* XLMAC_RX_LLFC_MSG_FIELDS */ "", 78202 /* XLMAC_RX_LSS_CTRL */ "", 78203 /* XLMAC_RX_LSS_STATUS */ "", 78204 /* XLMAC_RX_MAC_SA */ "", 78205 /* XLMAC_RX_MAX_SIZE */ "", 78206 /* XLMAC_RX_VLAN_TAG */ "", 78207 /* XLMAC_SPARE0 */ "", 78208 /* XLMAC_SPARE1 */ "", 78209 /* XLMAC_TIMESTAMP_ADJUST */ "", 78210 /* XLMAC_TIMESTAMP_BYTE_ADJUST */ "", 78211 /* XLMAC_TXFIFO_CELL_CNT */ "", 78212 /* XLMAC_TXFIFO_CELL_REQ_CNT */ "", 78213 /* XLMAC_TX_CDC_ECC_STATUS */ "", 78214 /* XLMAC_TX_CRC_CORRUPT_CTRL */ "", 78215 /* XLMAC_TX_CTRL */ "", 78216 /* XLMAC_TX_EP_CREDITS_CONFIG */ "", 78217 /* XLMAC_TX_LLFC_MSG_FIELDS */ "", 78218 /* XLMAC_TX_MAC_SA */ "", 78219 /* XLMAC_TX_TIMESTAMP_FIFO_DATA */ "", 78220 /* XLMAC_TX_TIMESTAMP_FIFO_STATUS */ "", 78221 /* XLMAC_VERSION_ID */ "", 78222 /* XLMIB_R64 */ "XLMIB_GRx64", 78223 /* XLMIB_R127 */ "XLMIB_GRx127", 78224 /* XLMIB_R255 */ "XLMIB_GRx255", 78225 /* XLMIB_R511 */ "XLMIB_GRx511", 78226 /* XLMIB_R1023 */ "XLMIB_GRx1023", 78227 /* XLMIB_R1518 */ "XLMIB_GRx1518", 78228 /* XLMIB_R2047 */ "XLMIB_GRx2047", 78229 /* XLMIB_R4095 */ "XLMIB_GRx4095", 78230 /* XLMIB_R9216 */ "XLMIB_GRx9216", 78231 /* XLMIB_R16383 */ "XLMIB_GRx16383", 78232 /* XLMIB_RALN */ "XLMIB_GRxALN", 78233 /* XLMIB_RBCA */ "XLMIB_GRxBCA", 78234 /* XLMIB_RBYT */ "XLMIB_GRxByt", 78235 /* XLMIB_RDVLN */ "XLMIB_GRxDVLN", 78236 /* XLMIB_RERPKT */ "XLMIB_GRxFrErr", 78237 /* XLMIB_RFCR */ "XLMIB_GRxFCR", 78238 /* XLMIB_RFCS */ "XLMIB_GRxFCS", 78239 /* XLMIB_RFLR */ "XLMIB_GRxFLR", 78240 /* XLMIB_RFRG */ "XLMIB_GRxFRG", 78241 /* XLMIB_RJBR */ "XLMIB_GRxJBR", 78242 /* XLMIB_RMCA */ "XLMIB_GRxMCA", 78243 /* XLMIB_RMCRC */ "XLMIB_GRxMCRC", 78244 /* XLMIB_RMGV */ "XLMIB_GRx1522", 78245 /* XLMIB_RMTUE */ "XLMIB_GRxMTUE", 78246 /* XLMIB_ROVR */ "XLMIB_GRxOVR", 78247 /* XLMIB_RPFC0 */ "XLMIB_GRxPFCP0", 78248 /* XLMIB_RPFC1 */ "XLMIB_GRxPFCP1", 78249 /* XLMIB_RPFC2 */ "XLMIB_GRxPFCP2", 78250 /* XLMIB_RPFC3 */ "XLMIB_GRxPFCP3", 78251 /* XLMIB_RPFC4 */ "XLMIB_GRxPFCP4", 78252 /* XLMIB_RPFC5 */ "XLMIB_GRxPFCP5", 78253 /* XLMIB_RPFC6 */ "XLMIB_GRxPFCP6", 78254 /* XLMIB_RPFC7 */ "XLMIB_GRxPFCP7", 78255 /* XLMIB_RPFCOFF0 */ "XLMIB_GRxPFCOFF0", 78256 /* XLMIB_RPFCOFF1 */ "XLMIB_GRxPFCOFF1", 78257 /* XLMIB_RPFCOFF2 */ "XLMIB_GRxPFCOFF2", 78258 /* XLMIB_RPFCOFF3 */ "XLMIB_GRxPFCOFF3", 78259 /* XLMIB_RPFCOFF4 */ "XLMIB_GRxPFCOFF4", 78260 /* XLMIB_RPFCOFF5 */ "XLMIB_GRxPFCOFF5", 78261 /* XLMIB_RPFCOFF6 */ "XLMIB_GRxPFCOFF6", 78262 /* XLMIB_RPFCOFF7 */ "XLMIB_GRxPFCOFF7", 78263 /* XLMIB_RPKT */ "XLMIB_GRxPkt", 78264 /* XLMIB_RPOK */ "XLMIB_GRxPOK", 78265 /* XLMIB_RPRM */ "XLMIB_GRxPRM", 78266 /* XLMIB_RPROG0 */ "XLMIB_GRxProg0", 78267 /* XLMIB_RPROG1 */ "XLMIB_GRxProg1", 78268 /* XLMIB_RPROG2 */ "XLMIB_GRxProg2", 78269 /* XLMIB_RPROG3 */ "XLMIB_GRxProg3", 78270 /* XLMIB_RRBYT */ "XLMIB_GRxRByt", 78271 /* XLMIB_RREPLY */ "XLMIB_GRxReply", 78272 /* XLMIB_RRPKT */ "XLMIB_GRxRPkt", 78273 /* XLMIB_RSCHCRC */ "XLMIB_GRxSCHCRC", 78274 /* XLMIB_RTRFU */ "XLMIB_GRxTRFU", 78275 /* XLMIB_RUCA */ "XLMIB_GRxUCA", 78276 /* XLMIB_RUND */ "XLMIB_GRxUND", 78277 /* XLMIB_RVERIFY */ "XLMIB_GRxVerify", 78278 /* XLMIB_RVLN */ "XLMIB_GRxVLN", 78279 /* XLMIB_RXCF */ "XLMIB_GRxCF", 78280 /* XLMIB_RXPF */ "XLMIB_GRxPF", 78281 /* XLMIB_RXPP */ "XLMIB_GRxPP", 78282 /* XLMIB_RXUDA */ "XLMIB_GRxUDA", 78283 /* XLMIB_RXUO */ "XLMIB_GRxUO", 78284 /* XLMIB_RXWSA */ "XLMIB_GRxWSA", 78285 /* XLMIB_RX_EEE_LPI_DURATION_COUNTER */ "XLMIB_RX_EEE_LPI_DURATION_COUNTER", 78286 /* XLMIB_RX_EEE_LPI_EVENT_COUNTER */ "XLMIB_RX_EEE_LPI_EVENT_COUNTER", 78287 /* XLMIB_RX_HCFC_COUNTER */ "XLMIB_RX_HCFC_COUNTER", 78288 /* XLMIB_RX_HCFC_CRC_COUNTER */ "XLMIB_RX_HCFC_CRC_COUNTER", 78289 /* XLMIB_RX_LLFC_CRC_COUNTER */ "XLMIB_RX_LLFC_CRC_COUNTER", 78290 /* XLMIB_RX_LLFC_LOG_COUNTER */ "XLMIB_RX_LLFC_LOG_COUNTER", 78291 /* XLMIB_RX_LLFC_PHY_COUNTER */ "XLMIB_RX_LLFC_PHY_COUNTER", 78292 /* XLMIB_T64 */ "XLMIB_GTx64", 78293 /* XLMIB_T127 */ "XLMIB_GTx127", 78294 /* XLMIB_T255 */ "XLMIB_GTx255", 78295 /* XLMIB_T511 */ "XLMIB_GTx511", 78296 /* XLMIB_T1023 */ "XLMIB_GTx1023", 78297 /* XLMIB_T1518 */ "XLMIB_GTx1518", 78298 /* XLMIB_T2047 */ "XLMIB_GTx2047", 78299 /* XLMIB_T4095 */ "XLMIB_GTx4095", 78300 /* XLMIB_T9216 */ "XLMIB_GTx9216", 78301 /* XLMIB_T16383 */ "XLMIB_GTx16383", 78302 /* XLMIB_TBCA */ "XLMIB_GTxBCA", 78303 /* XLMIB_TBYT */ "XLMIB_GTxBYT", 78304 /* XLMIB_TDFR */ "XLMIB_GTxDFR", 78305 /* XLMIB_TDVLN */ "XLMIB_GTxDVLN", 78306 /* XLMIB_TEDF */ "XLMIB_GTxEDF", 78307 /* XLMIB_TERR */ "XLMIB_GTxErr", 78308 /* XLMIB_TFCS */ "XLMIB_GTxFCS", 78309 /* XLMIB_TFRG */ "XLMIB_GTxFRG", 78310 /* XLMIB_TJBR */ "XLMIB_GTxJBR", 78311 /* XLMIB_TLCL */ "XLMIB_GTxLCL", 78312 /* XLMIB_TMCA */ "XLMIB_GTxMCA", 78313 /* XLMIB_TMCL */ "XLMIB_GTxMCL", 78314 /* XLMIB_TMGV */ "XLMIB_GTx1522", 78315 /* XLMIB_TNCL */ "XLMIB_GTxNCL", 78316 /* XLMIB_TOVR */ "XLMIB_GTxOVR", 78317 /* XLMIB_TPFC0 */ "XLMIB_GTxPFCP0", 78318 /* XLMIB_TPFC1 */ "XLMIB_GTxPFCP1", 78319 /* XLMIB_TPFC2 */ "XLMIB_GTxPFCP2", 78320 /* XLMIB_TPFC3 */ "XLMIB_GTxPFCP3", 78321 /* XLMIB_TPFC4 */ "XLMIB_GTxPFCP4", 78322 /* XLMIB_TPFC5 */ "XLMIB_GTxPFCP5", 78323 /* XLMIB_TPFC6 */ "XLMIB_GTxPFCP6", 78324 /* XLMIB_TPFC7 */ "XLMIB_GTxPFCP7", 78325 /* XLMIB_TPFCOFF0 */ "XLMIB_GTxPFCOFF0", 78326 /* XLMIB_TPFCOFF1 */ "XLMIB_GTxPFCOFF1", 78327 /* XLMIB_TPFCOFF2 */ "XLMIB_GTxPFCOFF2", 78328 /* XLMIB_TPFCOFF3 */ "XLMIB_GTxPFCOFF3", 78329 /* XLMIB_TPFCOFF4 */ "XLMIB_GTxPFCOFF4", 78330 /* XLMIB_TPFCOFF5 */ "XLMIB_GTxPFCOFF5", 78331 /* XLMIB_TPFCOFF6 */ "XLMIB_GTxPFCOFF6", 78332 /* XLMIB_TPFCOFF7 */ "XLMIB_GTxPFCOFF7", 78333 /* XLMIB_TPKT */ "XLMIB_GTxPkt", 78334 /* XLMIB_TPOK */ "XLMIB_GTxPOK", 78335 /* XLMIB_TREPLY */ "XLMIB_GTxReply", 78336 /* XLMIB_TRPKT */ "XLMIB_GTxRPKT", 78337 /* XLMIB_TSCL */ "XLMIB_GTxSCL", 78338 /* XLMIB_TSPARE0 */ "XLMIB_GTxSPARE0", 78339 /* XLMIB_TSPARE1 */ "XLMIB_GTxSPARE1", 78340 /* XLMIB_TSPARE2 */ "XLMIB_GTxSPARE2", 78341 /* XLMIB_TSPARE3 */ "XLMIB_GTxSPARE3", 78342 /* XLMIB_TUCA */ "XLMIB_GTxUCA", 78343 /* XLMIB_TUFL */ "XLMIB_GTxUFL", 78344 /* XLMIB_TVERIFY */ "XLMIB_GTxVerify", 78345 /* XLMIB_TVLN */ "XLMIB_GTxVLN", 78346 /* XLMIB_TXCF */ "XLMIB_GTxCF", 78347 /* XLMIB_TXCL */ "XLMIB_GTxXCL", 78348 /* XLMIB_TXPF */ "XLMIB_GTxPF", 78349 /* XLMIB_TXPP */ "XLMIB_GTxPP", 78350 /* XLMIB_TX_EEE_LPI_DURATION_COUNTER */ "XLMIB_TX_EEE_LPI_DURATION_COUNTER", 78351 /* XLMIB_TX_EEE_LPI_EVENT_COUNTER */ "XLMIB_TX_EEE_LPI_EVENT_COUNTER", 78352 /* XLMIB_TX_HCFC_COUNTER */ "XLMIB_TX_HCFC_COUNTER", 78353 /* XLMIB_TX_LLFC_LOG_COUNTER */ "XLMIB_TX_LLFC_LOG_COUNTER", 78354 /* XLMIB_XTHOL */ "XLMIB_XTHOL", 78355 /* XLPMIB_R64 */ "XLPMIB_GRx64", 78356 /* XLPMIB_R127 */ "XLPMIB_GRx127", 78357 /* XLPMIB_R255 */ "XLPMIB_GRx255", 78358 /* XLPMIB_R511 */ "XLPMIB_GRx511", 78359 /* XLPMIB_R1023 */ "XLPMIB_GRx1023", 78360 /* XLPMIB_R1518 */ "XLPMIB_GRx1518", 78361 /* XLPMIB_R2047 */ "XLPMIB_GRx2047", 78362 /* XLPMIB_R4095 */ "XLPMIB_GRx4095", 78363 /* XLPMIB_R9216 */ "XLPMIB_GRx9216", 78364 /* XLPMIB_R16383 */ "XLPMIB_GRx16383", 78365 /* XLPMIB_RALN */ "XLPMIB_GRxALN", 78366 /* XLPMIB_RBCA */ "XLPMIB_GRxBCA", 78367 /* XLPMIB_RBYT */ "XLPMIB_GRxByt", 78368 /* XLPMIB_RDVLN */ "XLPMIB_GRxDVLN", 78369 /* XLPMIB_RERPKT */ "XLPMIB_GRxFrErr", 78370 /* XLPMIB_RFCR */ "XLPMIB_GRxFCR", 78371 /* XLPMIB_RFCS */ "XLPMIB_GRxFCS", 78372 /* XLPMIB_RFFMSE */ "XLPMIB_GRxFFMSE", 78373 /* XLPMIB_RFLR */ "XLPMIB_GRxFLR", 78374 /* XLPMIB_RFRG */ "XLPMIB_GRxFRG", 78375 /* XLPMIB_RJBR */ "XLPMIB_GRxJBR", 78376 /* XLPMIB_RMCA */ "XLPMIB_GRxMCA", 78377 /* XLPMIB_RMCRC */ "XLPMIB_GRxMCRC", 78378 /* XLPMIB_RMDIS */ "XLPMIB_GRxMDIS", 78379 /* XLPMIB_RMFAE */ "XLPMIB_GRxMFAE", 78380 /* XLPMIB_RMFAO */ "XLPMIB_GRxMFAO", 78381 /* XLPMIB_RMFC */ "XLPMIB_GRxMFC", 78382 /* XLPMIB_RMFSE */ "XLPMIB_GRxMFSE", 78383 /* XLPMIB_RMGV */ "XLPMIB_GRx1522", 78384 /* XLPMIB_RMTUE */ "XLPMIB_GRxMTUE", 78385 /* XLPMIB_RNFFMSE */ "XLPMIB_GRxNFFMSE", 78386 /* XLPMIB_ROVR */ "XLPMIB_GRxOVR", 78387 /* XLPMIB_RPFC0 */ "XLPMIB_GRxPFCP0", 78388 /* XLPMIB_RPFC1 */ "XLPMIB_GRxPFCP1", 78389 /* XLPMIB_RPFC2 */ "XLPMIB_GRxPFCP2", 78390 /* XLPMIB_RPFC3 */ "XLPMIB_GRxPFCP3", 78391 /* XLPMIB_RPFC4 */ "XLPMIB_GRxPFCP4", 78392 /* XLPMIB_RPFC5 */ "XLPMIB_GRxPFCP5", 78393 /* XLPMIB_RPFC6 */ "XLPMIB_GRxPFCP6", 78394 /* XLPMIB_RPFC7 */ "XLPMIB_GRxPFCP7", 78395 /* XLPMIB_RPFCOFF7 */ "XLPMIB_GRxPFCOFF7", 78396 /* XLPMIB_RPKT */ "XLPMIB_GRxPkt", 78397 /* XLPMIB_RPOK */ "XLPMIB_GRxPOK", 78398 /* XLPMIB_RPRM */ "XLPMIB_GRxPRM", 78399 /* XLPMIB_RPROG0 */ "XLPMIB_GRxProg0", 78400 /* XLPMIB_RPROG1 */ "XLPMIB_GRxProg1", 78401 /* XLPMIB_RPROG2 */ "XLPMIB_GRxProg2", 78402 /* XLPMIB_RPROG3 */ "XLPMIB_GRxProg3", 78403 /* XLPMIB_RRBYT */ "XLPMIB_GRxRByt", 78404 /* XLPMIB_RRPKT */ "XLPMIB_GRxRPkt", 78405 /* XLPMIB_RSCHCRC */ "XLPMIB_GRxSCHCRC", 78406 /* XLPMIB_RTRFU */ "XLPMIB_GRxTRFU", 78407 /* XLPMIB_RUCA */ "XLPMIB_GRxUCA", 78408 /* XLPMIB_RUND */ "XLPMIB_GRxUND", 78409 /* XLPMIB_RVLN */ "XLPMIB_GRxVLN", 78410 /* XLPMIB_RXCF */ "XLPMIB_GRxCF", 78411 /* XLPMIB_RXPF */ "XLPMIB_GRxPF", 78412 /* XLPMIB_RXPP */ "XLPMIB_GRxPP", 78413 /* XLPMIB_RXUDA */ "XLPMIB_GRxUDA", 78414 /* XLPMIB_RXUO */ "XLPMIB_GRxUO", 78415 /* XLPMIB_RXWSA */ "XLPMIB_GRxWSA", 78416 /* XLPMIB_RX_EEE_LPI_DURATION_COUNTER */ "XLPMIB_RX_EEE_LPI_DURATION_COUNTER", 78417 /* XLPMIB_RX_EEE_LPI_EVENT_COUNTER */ "XLPMIB_RX_EEE_LPI_EVENT_COUNTER", 78418 /* XLPMIB_RX_HCFC_COUNTER */ "XLPMIB_RX_HCFC_COUNTER", 78419 /* XLPMIB_RX_HCFC_CRC_COUNTER */ "XLPMIB_RX_HCFC_CRC_COUNTER", 78420 /* XLPMIB_RX_LLFC_CRC_COUNTER */ "XLPMIB_RX_LLFC_CRC_COUNTER", 78421 /* XLPMIB_RX_LLFC_LOG_COUNTER */ "XLPMIB_RX_LLFC_LOG_COUNTER", 78422 /* XLPMIB_RX_LLFC_PHY_COUNTER */ "XLPMIB_RX_LLFC_PHY_COUNTER", 78423 /* XLPMIB_T64 */ "XLPMIB_GTx64", 78424 /* XLPMIB_T127 */ "XLPMIB_GTx127", 78425 /* XLPMIB_T255 */ "XLPMIB_GTx255", 78426 /* XLPMIB_T511 */ "XLPMIB_GTx511", 78427 /* XLPMIB_T1023 */ "XLPMIB_GTx1023", 78428 /* XLPMIB_T1518 */ "XLPMIB_GTx1518", 78429 /* XLPMIB_T2047 */ "XLPMIB_GTx2047", 78430 /* XLPMIB_T4095 */ "XLPMIB_GTx4095", 78431 /* XLPMIB_T9216 */ "XLPMIB_GTx9216", 78432 /* XLPMIB_T16383 */ "XLPMIB_GTx16383", 78433 /* XLPMIB_TBCA */ "XLPMIB_GTxBCA", 78434 /* XLPMIB_TBYT */ "XLPMIB_GTxBYT", 78435 /* XLPMIB_TDVLN */ "XLPMIB_GTxDVLN", 78436 /* XLPMIB_TERR */ "XLPMIB_GTxErr", 78437 /* XLPMIB_TFCS */ "XLPMIB_GTxFCS", 78438 /* XLPMIB_TFRG */ "XLPMIB_GTxFRG", 78439 /* XLPMIB_TJBR */ "XLPMIB_GTxJBR", 78440 /* XLPMIB_TLCL */ "XLPMIB_GTxLCL", 78441 /* XLPMIB_TMCA */ "XLPMIB_GTxMCA", 78442 /* XLPMIB_TMCL */ "XLPMIB_GTxMCL", 78443 /* XLPMIB_TMFAE */ "XLPMIB_GTxMFAE", 78444 /* XLPMIB_TMFC */ "XLPMIB_GTxMFC", 78445 /* XLPMIB_TMGV */ "XLPMIB_GTx1522", 78446 /* XLPMIB_TNCL */ "XLPMIB_GTxNCL", 78447 /* XLPMIB_TOVR */ "XLPMIB_GTxOVR", 78448 /* XLPMIB_TPFC0 */ "XLPMIB_GTxPFCP0", 78449 /* XLPMIB_TPFC1 */ "XLPMIB_GTxPFCP1", 78450 /* XLPMIB_TPFC2 */ "XLPMIB_GTxPFCP2", 78451 /* XLPMIB_TPFC3 */ "XLPMIB_GTxPFCP3", 78452 /* XLPMIB_TPFC4 */ "XLPMIB_GTxPFCP4", 78453 /* XLPMIB_TPFC5 */ "XLPMIB_GTxPFCP5", 78454 /* XLPMIB_TPFC6 */ "XLPMIB_GTxPFCP6", 78455 /* XLPMIB_TPFC7 */ "XLPMIB_GTxPFCP7", 78456 /* XLPMIB_TPFCOFF0 */ "XLPMIB_GTxPFCOFF0", 78457 /* XLPMIB_TPFCOFF1 */ "XLPMIB_GTxPFCOFF1", 78458 /* XLPMIB_TPFCOFF2 */ "XLPMIB_GTxPFCOFF2", 78459 /* XLPMIB_TPFCOFF3 */ "XLPMIB_GTxPFCOFF3", 78460 /* XLPMIB_TPFCOFF4 */ "XLPMIB_GTxPFCOFF4", 78461 /* XLPMIB_TPFCOFF5 */ "XLPMIB_GTxPFCOFF5", 78462 /* XLPMIB_TPFCOFF6 */ "XLPMIB_GTxPFCOFF6", 78463 /* XLPMIB_TPFCOFF7 */ "XLPMIB_GTxPFCOFF7", 78464 /* XLPMIB_TPKT */ "XLPMIB_GTxPkt", 78465 /* XLPMIB_TPOK */ "XLPMIB_GTxPOK", 78466 /* XLPMIB_TRPKT */ "XLPMIB_GTxRPKT", 78467 /* XLPMIB_TSCL */ "XLPMIB_GTxSCL", 78468 /* XLPMIB_TSPARE0 */ "XLPMIB_GTxSPARE0", 78469 /* XLPMIB_TSPARE1 */ "XLPMIB_GTxSPARE1", 78470 /* XLPMIB_TSPARE2 */ "XLPMIB_GTxSPARE2", 78471 /* XLPMIB_TSPARE3 */ "XLPMIB_GTxSPARE3", 78472 /* XLPMIB_TUCA */ "XLPMIB_GTxUCA", 78473 /* XLPMIB_TUFL */ "XLPMIB_GTxUFL", 78474 /* XLPMIB_TVLN */ "XLPMIB_GTxVLN", 78475 /* XLPMIB_TXCF */ "XLPMIB_GTxCF", 78476 /* XLPMIB_TXCL */ "XLPMIB_GTxXCL", 78477 /* XLPMIB_TXPF */ "XLPMIB_GTxPF", 78478 /* XLPMIB_TXPP */ "XLPMIB_GTxPP", 78479 /* XLPMIB_TX_EEE_LPI_DURATION_COUNTER */ "XLPMIB_TX_EEE_LPI_DURATION_COUNTER", 78480 /* XLPMIB_TX_EEE_LPI_EVENT_COUNTER */ "XLPMIB_TX_EEE_LPI_EVENT_COUNTER", 78481 /* XLPMIB_TX_HCFC_COUNTER */ "XLPMIB_TX_HCFC_COUNTER", 78482 /* XLPMIB_TX_LLFC_LOG_COUNTER */ "XLPMIB_TX_LLFC_LOG_COUNTER", 78483 /* XLPMIB_XTHOL */ "XLPMIB_XTHOL", 78484 /* XLPORT_BOD_OVERFLOW_ERROR */ "", 78485 /* XLPORT_BOD_XLP0_ECC_STATUS */ "", 78486 /* XLPORT_CNTMAXSIZE */ "", 78487 /* XLPORT_CONFIG */ "", 78488 /* XLPORT_ECC_CONTROL */ "", 78489 /* XLPORT_EEE_CLOCK_GATE */ "", 78490 /* XLPORT_EEE_CORE0_CLOCK_GATE_COUNTER */ "", 78491 /* XLPORT_EEE_COUNTER_MODE */ "", 78492 /* XLPORT_EEE_DURATION_TIMER_PULSE */ "", 78493 /* XLPORT_ENABLE_REG */ "", 78494 /* XLPORT_FAULT_LINK_STATUS */ "", 78495 /* XLPORT_FLOW_CONTROL_CONFIG */ "", 78496 /* XLPORT_FORCE_DOUBLE_BIT_ERROR */ "", 78497 /* XLPORT_FORCE_SINGLE_BIT_ERROR */ "", 78498 /* XLPORT_GENERAL_SPARE0 */ "", 78499 /* XLPORT_GENERAL_SPARE1_REG */ "", 78500 /* XLPORT_GENERAL_SPARE2_REG */ "", 78501 /* XLPORT_GENERAL_SPARE3_REG */ "", 78502 /* XLPORT_GENERAL_SPARE4_REG */ "", 78503 /* XLPORT_GENERAL_SPARE5_REG */ "", 78504 /* XLPORT_GENERAL_SPARE6_REG */ "", 78505 /* XLPORT_GENERAL_SPARE7_REG */ "", 78506 /* XLPORT_INTR_ENABLE */ "", 78507 /* XLPORT_INTR_STATUS */ "", 78508 /* XLPORT_LAG_FAILOVER_CONFIG */ "", 78509 /* XLPORT_LED_CHAIN_CONFIG */ "", 78510 /* XLPORT_LINKSTATUS_DOWN */ "", 78511 /* XLPORT_LINKSTATUS_DOWN_CLEAR */ "", 78512 /* XLPORT_MAC_CONTROL */ "", 78513 /* XLPORT_MAC_RSV_MASK */ "", 78514 /* XLPORT_MEMORY_CONTROL0 */ "", 78515 /* XLPORT_MEMORY_CONTROL1 */ "", 78516 /* XLPORT_MEMORY_CONTROL2 */ "", 78517 /* XLPORT_MIB_MIN_FRAG_SIZE */ "", 78518 /* XLPORT_MIB_PROG_RANGE_CNTR0_CONFIG */ "", 78519 /* XLPORT_MIB_PROG_RANGE_CNTR1_CONFIG */ "", 78520 /* XLPORT_MIB_PROG_RANGE_CNTR2_CONFIG */ "", 78521 /* XLPORT_MIB_PROG_RANGE_CNTR3_CONFIG */ "", 78522 /* XLPORT_MIB_RESET */ "", 78523 /* XLPORT_MIB_RSC0_ECC_STATUS */ "", 78524 /* XLPORT_MIB_RSC1_ECC_STATUS */ "", 78525 /* XLPORT_MIB_RSC_MEM0_ECC_STATUS */ "", 78526 /* XLPORT_MIB_RSC_MEM1_ECC_STATUS */ "", 78527 /* XLPORT_MIB_RSC_MEM2_ECC_STATUS */ "", 78528 /* XLPORT_MIB_RSC_MEM3_ECC_STATUS */ "", 78529 /* XLPORT_MIB_RSC_MEM4_ECC_STATUS */ "", 78530 /* XLPORT_MIB_RSC_RAM_CONTROL */ "", 78531 /* XLPORT_MIB_TSC0_ECC_STATUS */ "", 78532 /* XLPORT_MIB_TSC1_ECC_STATUS */ "", 78533 /* XLPORT_MIB_TSC_MEM0_ECC_STATUS */ "", 78534 /* XLPORT_MIB_TSC_MEM1_ECC_STATUS */ "", 78535 /* XLPORT_MIB_TSC_MEM2_ECC_STATUS */ "", 78536 /* XLPORT_MIB_TSC_MEM3_ECC_STATUS */ "", 78537 /* XLPORT_MIB_TSC_RAM_CONTROL */ "", 78538 /* XLPORT_MODE_REG */ "", 78539 /* XLPORT_PMD_PLL_CTRL_CONFIG */ "", 78540 /* XLPORT_PM_VERSION_ID */ "", 78541 /* XLPORT_PORT_ENABLE */ "", 78542 /* XLPORT_PORT_SPARE0 */ "", 78543 /* XLPORT_PORT_SPARE1 */ "", 78544 /* XLPORT_PORT_SPARE2 */ "", 78545 /* XLPORT_PORT_SPARE3 */ "", 78546 /* XLPORT_POWER_SAVE */ "", 78547 /* XLPORT_SBUS_CONTROL */ "", 78548 /* XLPORT_SGNDET_EARLYCRS */ "", 78549 /* XLPORT_SOFT_RESET */ "", 78550 /* XLPORT_SPARE0_REG */ "", 78551 /* XLPORT_SW_FLOW_CONTROL */ "", 78552 /* XLPORT_TM_CONTROL */ "", 78553 /* XLPORT_TSC_PLL_LOCK_STATUS */ "", 78554 /* XLPORT_TS_TIMER_31_0_REG */ "", 78555 /* XLPORT_TS_TIMER_47_32_REG */ "", 78556 /* XLPORT_TXFIFO0_ECC_STATUS */ "", 78557 /* XLPORT_TXFIFO1_ECC_STATUS */ "", 78558 /* XLPORT_TXFIFO2_ECC_STATUS */ "", 78559 /* XLPORT_TXFIFO3_ECC_STATUS */ "", 78560 /* XLPORT_TXFIFO_CTRL */ "", 78561 /* XLPORT_TXFIFO_MEM_ECC_STATUS */ "", 78562 /* XLPORT_TXFIFO_OVERFLOW */ "", 78563 /* XLPORT_TXPI_CSR_CTRL1 */ "", 78564 /* XLPORT_TXPI_CSR_OVER_EN */ "", 78565 /* XLPORT_TXPI_CSR_OVER_VAL_0_HIGH */ "", 78566 /* XLPORT_TXPI_CSR_OVER_VAL_0_LOW */ "", 78567 /* XLPORT_TXPI_CSR_OVER_VAL_1_HIGH */ "", 78568 /* XLPORT_TXPI_CSR_OVER_VAL_1_LOW */ "", 78569 /* XLPORT_TXPI_CSR_OVER_VAL_2_HIGH */ "", 78570 /* XLPORT_TXPI_CSR_OVER_VAL_2_LOW */ "", 78571 /* XLPORT_TXPI_CSR_OVER_VAL_3_HIGH */ "", 78572 /* XLPORT_TXPI_CSR_OVER_VAL_3_LOW */ "", 78573 /* XLPORT_TXPI_DATA_OUT_STS_0_HIGH */ "", 78574 /* XLPORT_TXPI_DATA_OUT_STS_0_LOW */ "", 78575 /* XLPORT_TXPI_DATA_OUT_STS_1_HIGH */ "", 78576 /* XLPORT_TXPI_DATA_OUT_STS_1_LOW */ "", 78577 /* XLPORT_TXPI_DATA_OUT_STS_2_HIGH */ "", 78578 /* XLPORT_TXPI_DATA_OUT_STS_2_LOW */ "", 78579 /* XLPORT_TXPI_DATA_OUT_STS_3_HIGH */ "", 78580 /* XLPORT_TXPI_DATA_OUT_STS_3_LOW */ "", 78581 /* XLPORT_TXPI_LANE_SELECTION */ "", 78582 /* XLPORT_WC_UCMEM_CTRL */ "", 78583 /* XLPORT_XGXS0_CTRL_REG */ "", 78584 /* XLPORT_XGXS0_LN0_STATUS0_REG */ "", 78585 /* XLPORT_XGXS0_LN1_STATUS0_REG */ "", 78586 /* XLPORT_XGXS0_LN2_STATUS0_REG */ "", 78587 /* XLPORT_XGXS0_LN3_STATUS0_REG */ "", 78588 /* XLPORT_XGXS0_STATUS0_REG */ "", 78589 /* XLPORT_XGXS0_STATUS1_REG */ "", 78590 /* XLPORT_XGXS1_STATUS0_REG */ "", 78591 /* XLPORT_XGXS1_STATUS1_REG */ "", 78592 /* XLPORT_XGXS2_STATUS0_REG */ "", 78593 /* XLPORT_XGXS2_STATUS1_REG */ "", 78594 /* XLPORT_XGXS3_STATUS0_REG */ "", 78595 /* XLPORT_XGXS3_STATUS1_REG */ "", 78596 /* XLPORT_XGXS_COUNTER_MODE */ "", 78597 /* XLPORT_XGXS_CTRL_REG */ "", 78598 /* XLPORT_XGXS_STATUS_GEN_REG */ "", 78599 /* XLPORT_XMAC_CONTROL */ "", 78600 /* XLP_EEE_COUNTER_MODE */ "", 78601 /* XLP_REG_060200 */ "", 78602 /* XLP_REG_060300 */ "", 78603 /* XLP_REG_061500 */ "", 78604 /* XLP_REG_062000 */ "", 78605 /* XLP_REG_062200 */ "", 78606 /* XLP_REG_062500 */ "", 78607 /* XLP_REG_2022300 */ "", 78608 /* XLP_REG_061E00 */ "", 78609 /* XLP_REG_061F00 */ "", 78610 /* XLP_TO_MMU_BKP_STATUS */ "", 78611 /* XLP_TXFIFO_CELL_CNT */ "", 78612 /* XLP_TXFIFO_CELL_REQ_CNT */ "", 78613 /* XLP_TXFIFO_OVRFLW */ "", 78614 /* XLP_TXFIFO_PKT_DROP_CTL */ "", 78615 /* XLP_XMAC_CLEAR_FIFO_STATUS */ "", 78616 /* XLP_XMAC_CLEAR_RX_LSS_STATUS */ "", 78617 /* XLP_XMAC_CTRL */ "", 78618 /* XLP_XMAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 78619 /* XLP_XMAC_EEE_CTRL */ "", 78620 /* XLP_XMAC_EEE_TIMERS */ "", 78621 /* XLP_XMAC_FIFO_STATUS */ "", 78622 /* XLP_XMAC_GMII_EEE_CTRL */ "", 78623 /* XLP_XMAC_LH_HDR_3 */ "", 78624 /* XLP_XMAC_LLFC_CTRL */ "", 78625 /* XLP_XMAC_MODE */ "", 78626 /* XLP_XMAC_OSTS_TIMESTAMP_ADJUST */ "", 78627 /* XLP_XMAC_PAUSE_CTRL */ "", 78628 /* XLP_XMAC_PFC_CTRL */ "", 78629 /* XLP_XMAC_PFC_DA */ "", 78630 /* XLP_XMAC_PFC_OPCODE */ "", 78631 /* XLP_XMAC_PFC_TYPE */ "", 78632 /* XLP_XMAC_RX_CTRL */ "", 78633 /* XLP_XMAC_RX_LLFC_MSG_FIELDS */ "", 78634 /* XLP_XMAC_RX_LSS_CTRL */ "", 78635 /* XLP_XMAC_RX_LSS_STATUS */ "", 78636 /* XLP_XMAC_RX_MAC_SA */ "", 78637 /* XLP_XMAC_RX_MAX_SIZE */ "", 78638 /* XLP_XMAC_RX_VLAN_TAG */ "", 78639 /* XLP_XMAC_TX_CTRL */ "", 78640 /* XLP_XMAC_TX_FIFO_CREDITS */ "", 78641 /* XLP_XMAC_TX_LLFC_MSG_FIELDS */ "", 78642 /* XLP_XMAC_TX_MAC_SA */ "", 78643 /* XLP_XMAC_TX_TIMESTAMP_FIFO_DATA */ "", 78644 /* XLP_XMAC_TX_TIMESTAMP_FIFO_STATUS */ "", 78645 /* XLP_XMAC_VERSION_ID */ "", 78646 /* XMAC_CLEAR_FIFO_STATUS */ "", 78647 /* XMAC_CLEAR_RX_LSS_STATUS */ "", 78648 /* XMAC_CTRL */ "", 78649 /* XMAC_EEE_1_SEC_LINK_STATUS_TIMER */ "", 78650 /* XMAC_EEE_CTRL */ "", 78651 /* XMAC_EEE_TIMERS */ "", 78652 /* XMAC_FIFO_STATUS */ "", 78653 /* XMAC_GMII_EEE_CTRL */ "", 78654 /* XMAC_HCFC_CTRL */ "", 78655 /* XMAC_LLFC_CTRL */ "", 78656 /* XMAC_MACSEC_CTRL */ "", 78657 /* XMAC_MODE */ "", 78658 /* XMAC_OSTS_TIMESTAMP_ADJUST */ "", 78659 /* XMAC_PAUSE_CTRL */ "", 78660 /* XMAC_PFC_CTRL */ "", 78661 /* XMAC_PFC_DA */ "", 78662 /* XMAC_PFC_OPCODE */ "", 78663 /* XMAC_PFC_TYPE */ "", 78664 /* XMAC_RX_CTRL */ "", 78665 /* XMAC_RX_LLFC_MSG_FIELDS */ "", 78666 /* XMAC_RX_LSS_CTRL */ "", 78667 /* XMAC_RX_LSS_STATUS */ "", 78668 /* XMAC_RX_MAC_SA */ "", 78669 /* XMAC_RX_MAX_SIZE */ "", 78670 /* XMAC_RX_VLAN_TAG */ "", 78671 /* XMAC_SPARE0 */ "", 78672 /* XMAC_SPARE1 */ "", 78673 /* XMAC_TX_CTRL */ "", 78674 /* XMAC_TX_FIFO_CREDITS */ "", 78675 /* XMAC_TX_LLFC_MSG_FIELDS */ "", 78676 /* XMAC_TX_MAC_SA */ "", 78677 /* XMAC_TX_TIMESTAMP_FIFO_DATA */ "", 78678 /* XMAC_TX_TIMESTAMP_FIFO_STATUS */ "", 78679 /* XMAC_VERSION_ID */ "", 78680 /* XMODID */ "", 78681 /* XMODID_DUAL_EN */ "", 78682 /* XMODID_EN */ "", 78683 /* XPAUSE_D0 */ "", 78684 /* XPAUSE_D1 */ "", 78685 /* XPAUSE_D2 */ "", 78686 /* XPAUSE_D3 */ "", 78687 /* XPAUSE_MH0 */ "", 78688 /* XPAUSE_MH1 */ "", 78689 /* XPAUSE_MH2 */ "", 78690 /* XPAUSE_MH3 */ "", 78691 /* XPAUSE_RX_DA_LS */ "", 78692 /* XPAUSE_RX_DA_MS */ "", 78693 /* XPAUSE_RX_LENGTH_TYPE */ "", 78694 /* XPAUSE_RX_OPCODE */ "", 78695 /* XPAUSE_TX_PKT_XOFF_VAL */ "", 78696 /* XPAUSE_WATCHDOG_INIT_VAL */ "", 78697 /* XPAUSE_WATCHDOG_THRESH */ "", 78698 /* XPORT_CONFIG */ "", 78699 /* XPORT_ECC_CONTROL */ "", 78700 /* XPORT_EEE_DURATION_TIMER_PULSE */ "", 78701 /* XPORT_FORCE_DOUBLE_BIT_ERROR */ "", 78702 /* XPORT_FORCE_SINGLE_BIT_ERROR */ "", 78703 /* XPORT_INTR_ENABLE */ "", 78704 /* XPORT_INTR_STATUS */ "", 78705 /* XPORT_LINKSTATUS_DOWN */ "", 78706 /* XPORT_LINKSTATUS_DOWN_CLEAR */ "", 78707 /* XPORT_MEMORY_CONTROL */ "", 78708 /* XPORT_MEMORY_CONTROL0 */ "", 78709 /* XPORT_MEMORY_CONTROL1 */ "", 78710 /* XPORT_MEMORY_CONTROL2 */ "", 78711 /* XPORT_MIB_RESET */ "", 78712 /* XPORT_MIB_RSC_MEM0_ECC_STATUS */ "", 78713 /* XPORT_MIB_RSC_MEM1_ECC_STATUS */ "", 78714 /* XPORT_MIB_RSC_MEM2_ECC_STATUS */ "", 78715 /* XPORT_MIB_RSC_MEM3_ECC_STATUS */ "", 78716 /* XPORT_MIB_RSC_MEM4_ECC_STATUS */ "", 78717 /* XPORT_MIB_TSC_MEM0_ECC_STATUS */ "", 78718 /* XPORT_MIB_TSC_MEM1_ECC_STATUS */ "", 78719 /* XPORT_MIB_TSC_MEM2_ECC_STATUS */ "", 78720 /* XPORT_MIB_TSC_MEM3_ECC_STATUS */ "", 78721 /* XPORT_MODE_REG */ "", 78722 /* XPORT_PFC_STATE */ "", 78723 /* XPORT_PORT_ENABLE */ "", 78724 /* XPORT_RXFIFO_MEM0_ECC_STATUS */ "", 78725 /* XPORT_RXFIFO_MEM1_ECC_STATUS */ "", 78726 /* XPORT_RXFIFO_MEM2_ECC_STATUS */ "", 78727 /* XPORT_RXFIFO_MEM3_ECC_STATUS */ "", 78728 /* XPORT_RXFIFO_MEM4_ECC_STATUS */ "", 78729 /* XPORT_RXFIFO_MEM_ECC_STATUS */ "", 78730 /* XPORT_RX_FIFO_MEM_ECC_STATUS */ "", 78731 /* XPORT_SW_FLOW_CONTROL */ "", 78732 /* XPORT_TO_MMU_BKP */ "", 78733 /* XPORT_TO_MMU_BKP_64 */ "XPORT_TO_MMU_BKP", 78734 /* XPORT_TO_MMU_BKP_HG */ "", 78735 /* XPORT_TXFIFO_MEM_ECC_STATUS */ "", 78736 /* XPORT_TX_FIFO_MEM_ECC_STATUS */ "", 78737 /* XPORT_WC_UCMEM_CTRL */ "", 78738 /* XPORT_XGXS0_STATUS0_REG */ "", 78739 /* XPORT_XGXS0_STATUS1_REG */ "", 78740 /* XPORT_XGXS1_STATUS0_REG */ "", 78741 /* XPORT_XGXS1_STATUS1_REG */ "", 78742 /* XPORT_XGXS2_STATUS0_REG */ "", 78743 /* XPORT_XGXS2_STATUS1_REG */ "", 78744 /* XPORT_XGXS3_STATUS0_REG */ "", 78745 /* XPORT_XGXS3_STATUS1_REG */ "", 78746 /* XPORT_XGXS_COUNTER_MODE */ "", 78747 /* XPORT_XGXS_CTRL */ "", 78748 /* XPORT_XGXS_GEN_STATUS_REG */ "", 78749 /* XPORT_XGXS_NEWCTL_REG */ "", 78750 /* XPORT_XGXS_NEWSTATUS0_REG */ "", 78751 /* XPORT_XGXS_NEWSTATUS1_REG */ "", 78752 /* XPORT_XGXS_NEWSTATUS2_REG */ "", 78753 /* XPORT_XGXS_NEWSTATUS3_REG */ "", 78754 /* XPORT_XGXS_STATUS_REG */ "", 78755 /* XPORT_XLMAC_CONTROL */ "", 78756 /* XPORT_XMAC_CONTROL */ "", 78757 /* XP_EEE_COUNTER_MODE */ "", 78758 /* XP_EGR_PKT_DROP_CTL */ "", 78759 /* XP_FIFO_OVERFLOW_STATUS */ "", 78760 /* XP_TXFIFO_CELL_CNT */ "", 78761 /* XP_TXFIFO_CELL_REQ_CNT */ "", 78762 /* XP_TXFIFO_OVRFLW */ "", 78763 /* XP_TXFIFO_PKT_DROP_CTL */ "", 78764 /* XP_XBODE_CELL_CNT */ "", 78765 /* XP_XBODE_CELL_REQ_CNT */ "", 78766 /* XQCOSARBSEL */ "", 78767 /* XQCOSARBSEL_QGROUP */ "", 78768 /* XQCOSARBSEL_QLAYER */ "", 78769 /* XQCOSPTR */ "", 78770 /* XQCOSPTRCTL */ "", 78771 /* XQEMPTY */ "", 78772 /* XQEMPTY_DEBUG */ "", 78773 /* XQEMPTY_DEBUG_EN */ "", 78774 /* XQEMPTY_DEBUG_QLAYER_QBMP0 */ "", 78775 /* XQEMPTY_DEBUG_QLAYER_QBMP1 */ "", 78776 /* XQEMPTY_QLAYER_QBMP0 */ "", 78777 /* XQEMPTY_QLAYER_QBMP1 */ "", 78778 /* XQFLLMEMDEBUG */ "", 78779 /* XQFLLPARITYERRORPTR */ "", 78780 /* XQFLLPTR */ "", 78781 /* XQFLL_ERR_CLR */ "", 78782 /* XQFLL_ERR_CLR_0 */ "", 78783 /* XQFLL_ERR_CLR_1 */ "", 78784 /* XQFLL_ERR_CLR_2 */ "", 78785 /* XQFLL_ERR_VLD */ "", 78786 /* XQFLL_ERR_VLD_0 */ "", 78787 /* XQFLL_ERR_VLD_1 */ "", 78788 /* XQFLL_ERR_VLD_2 */ "", 78789 /* XQFLL_MULTI_ERR */ "", 78790 /* XQFLL_MULTI_ERR_0 */ "", 78791 /* XQFLL_MULTI_ERR_1 */ "", 78792 /* XQFLL_MULTI_ERR_2 */ "", 78793 /* XQMEMDEBUG */ "", 78794 /* XQPARITYERRORPBM */ "", 78795 /* XQPARITYERRORPTR */ "", 78796 /* XQPORT_EHG_RX_DATA_PARITY_STATUS_INTR */ "", 78797 /* XQPORT_EHG_RX_DATA_PARITY_STATUS_NACK */ "", 78798 /* XQPORT_EHG_RX_MASK_PARITY_STATUS_INTR */ "", 78799 /* XQPORT_EHG_RX_MASK_PARITY_STATUS_NACK */ "", 78800 /* XQPORT_EHG_TX_DATA_PARITY_STATUS_INTR */ "", 78801 /* XQPORT_EHG_TX_DATA_PARITY_STATUS_NACK */ "", 78802 /* XQPORT_FORCE_DOUBLE_BIT_ERROR */ "", 78803 /* XQPORT_FORCE_SINGLE_BIT_ERROR */ "", 78804 /* XQPORT_INTR_ENABLE */ "", 78805 /* XQPORT_INTR_STATUS */ "", 78806 /* XQPORT_MODE_REG */ "", 78807 /* XQPORT_PARITY_CONTROL */ "", 78808 /* XQPORT_XGXS_NEWCTL_REG */ "", 78809 /* XQPORT_XGXS_NEWSTATUS0_REG */ "", 78810 /* XQPORT_XGXS_NEWSTATUS1_REG */ "", 78811 /* XQPORT_XGXS_NEWSTATUS2_REG */ "", 78812 /* XQPORT_XGXS_NEWSTATUS3_REG */ "", 78813 /* XQPORT_XQBODE_TXFIFO_PARITY_STATUS_INTR */ "", 78814 /* XQPORT_XQBOD_RXFIFO_PARITY_STATUS_INTR */ "", 78815 /* XQREADPOINTER */ "", 78816 /* XQ_ERR_CLR */ "", 78817 /* XQ_ERR_CLR_0 */ "", 78818 /* XQ_ERR_CLR_1 */ "", 78819 /* XQ_ERR_CLR_2 */ "", 78820 /* XQ_ERR_CNT */ "", 78821 /* XQ_ERR_VLD */ "", 78822 /* XQ_ERR_VLD_0 */ "", 78823 /* XQ_ERR_VLD_1 */ "", 78824 /* XQ_ERR_VLD_2 */ "", 78825 /* XQ_MULTI_ERR */ "", 78826 /* XQ_MULTI_ERR_0 */ "", 78827 /* XQ_MULTI_ERR_1 */ "", 78828 /* XQ_MULTI_ERR_2 */ "", 78829 /* XTHOL */ "XTHOL", 78830 /* XTHOL_64 */ "", 78831 /* XTIBP */ "", 78832 /* XTPSE */ "", 78833 /* X_CPU_SLOT_COUNT */ "", 78834 /* X_GPORT_CNTMAXSIZE */ "", 78835 /* X_GPORT_CONFIG */ "", 78836 /* X_GPORT_SGNDET_EARLYCRS */ "", 78837 /* X_TDM_EN */ "", 78838 /* YELLOW_CNG_DROP_CNT */ "", 78839 /* Y_CPU_SLOT_COUNT */ "", 78840 /* Y_TDM_EN */ "",