allmems_desc.i (1905077B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allmems_desc.i 12 * Purpose: Memory descriptions. 13 */ 14 15 /* AGM_MONITOR_TABLE */ "Aggregation Group Monitor Table.", 16 /* ALLOWED_PORT_BITMAP_PROFILE */ "allowed port profile table for L3_TUNNEL.", 17 /* ALTERNATE_EMIRROR_BITMAP */ "Source Modid based blocking mask table", 18 /* ALT_TTL_FN */ "TTL FUNCTION TABLE FOR IFP.", 19 /* ALT_TTL_FN_PIPE0 */ "TTL FUNCTION TABLE FOR IFP.", 20 /* ALT_TTL_FN_PIPE1 */ "TTL FUNCTION TABLE FOR IFP.", 21 /* ALT_TTL_FN_PIPE2 */ "TTL FUNCTION TABLE FOR IFP.", 22 /* ALT_TTL_FN_PIPE3 */ "TTL FUNCTION TABLE FOR IFP.", 23 /* ALT_TTL_FN_PIPE4 */ "TTL FUNCTION TABLE FOR IFP.", 24 /* ALT_TTL_FN_PIPE5 */ "TTL FUNCTION TABLE FOR IFP.", 25 /* ALT_TTL_FN_PIPE6 */ "TTL FUNCTION TABLE FOR IFP.", 26 /* ALT_TTL_FN_PIPE7 */ "TTL FUNCTION TABLE FOR IFP.", 27 /* AM_TABLE */ "TSC External Memory Interface to program AM_TABLE", 28 /* AM_TOP_MEM_1 */ "mem1", 29 /* AM_TOP_MEM_2 */ "mem2", 30 /* ARB_TDM_TABLE */ "Arbiter TDM Table", 31 /* ARB_TDM_TABLE_0 */ "MMU to EPIPE Arbiter TDM Table, PIPE 0", 32 /* ARB_TDM_TABLE_1 */ "MMU to EPIPE Arbiter TDM Table, PIPE 1", 33 /* AXP_CH_NLF_INPUT_COUNTER_TABLE */ "Byte and Packet counts for data flow into each NLF. NLF Number is used as index.", 34 /* AXP_CH_NLF_OUTPUT_COUNTER_TABLE */ "Byte and Packet counts for data flow into each NLF. NLF number used as index.", 35 /* AXP_SM_CHAR_REMAP0 */ "Character Remap Table for data to Regex Engine 0.", 36 /* AXP_SM_CHAR_REMAP1 */ "Character Remap Table for data to Regex Engine 1.", 37 /* AXP_SM_CHAR_REMAP2 */ "Character Remap Table for data to Regex Engine 2.", 38 /* AXP_SM_CHAR_REMAP3 */ "Character Remap Table for data to Regex Engine 3.", 39 /* AXP_SM_CHAR_REMAP4 */ "Character Remap Table for data to Regex Engine 4.", 40 /* AXP_SM_CHAR_REMAP5 */ "Character Remap Table for data to Regex Engine 5.", 41 /* AXP_SM_CHAR_REMAP6 */ "Character Remap Table for data to Regex Engine 6.", 42 /* AXP_SM_CHAR_REMAP7 */ "Character Remap Table for data to Regex Engine 7.", 43 /* AXP_SM_CHAR_REMAP8 */ "Character Remap Table for data to Regex Engine 8.", 44 /* AXP_SM_CHAR_REMAP9 */ "Character Remap Table for data to Regex Engine 9.", 45 /* AXP_SM_CHAR_REMAP10 */ "Character Remap Table for data to Regex Engine 10.", 46 /* AXP_SM_CHAR_REMAP11 */ "Character Remap Table for data to Regex Engine 11.", 47 /* AXP_SM_CHAR_REMAP12 */ "Character Remap Table for data to Regex Engine 12.", 48 /* AXP_SM_CHAR_REMAP13 */ "Character Remap Table for data to Regex Engine 13.", 49 /* AXP_SM_CHAR_REMAP14 */ "Character Remap Table for data to Regex Engine 14.", 50 /* AXP_SM_CHAR_REMAP15 */ "Character Remap Table for data to Regex Engine 15.", 51 /* AXP_SM_CHAR_REMAP16 */ "Character Remap Table for data to Regex Engine 16.", 52 /* AXP_SM_CHAR_REMAP17 */ "Character Remap Table for data to Regex Engine 17.", 53 /* AXP_SM_CHAR_REMAP18 */ "Character Remap Table for data to Regex Engine 18.", 54 /* AXP_SM_CHAR_REMAP19 */ "Character Remap Table for data to Regex Engine 19.", 55 /* AXP_SM_CHAR_REMAP20 */ "Character Remap Table for data to Regex Engine 20.", 56 /* AXP_SM_CHAR_REMAP21 */ "Character Remap Table for data to Regex Engine 21.", 57 /* AXP_SM_CHAR_REMAP22 */ "Character Remap Table for data to Regex Engine 22.", 58 /* AXP_SM_CHAR_REMAP23 */ "Character Remap Table for data to Regex Engine 23.", 59 /* AXP_SM_CHAR_REMAP24 */ "Character Remap Table for data to Regex Engine 24.", 60 /* AXP_SM_CHAR_REMAP25 */ "Character Remap Table for data to Regex Engine 25.", 61 /* AXP_SM_CHAR_REMAP26 */ "Character Remap Table for data to Regex Engine 26.", 62 /* AXP_SM_CHAR_REMAP27 */ "Character Remap Table for data to Regex Engine 27.", 63 /* AXP_SM_CHAR_REMAP28 */ "Character Remap Table for data to Regex Engine 28.", 64 /* AXP_SM_CHAR_REMAP29 */ "Character Remap Table for data to Regex Engine 29.", 65 /* AXP_SM_CHAR_REMAP30 */ "Character Remap Table for data to Regex Engine 30.", 66 /* AXP_SM_CHAR_REMAP31 */ "Character Remap Table for data to Regex Engine 31.", 67 /* AXP_SM_FLOW_TABLE_BULK_MATCH_DATA */ "Flow Table Bulk Clear Data registers.", 68 /* AXP_SM_FLOW_TABLE_BULK_MATCH_MASK */ "Flow Table Bulk Clear Mask Control registers.", 69 /* AXP_SM_FLOW_TABLE_BULK_REPLACE_DATA */ "Flow Table Bulk Clear Data registers.", 70 /* AXP_SM_FLOW_TABLE_BULK_REPLACE_MASK */ "Flow Table Bulk Clear Mask Control registers.", 71 /* AXP_SM_FLOW_TABLE_MEM */ "Signature Match Flow Table Memory (one entry per flow)", 72 /* AXP_SM_MATCH_COUNTERS_MEM0 */ "Match Counters 0 (one set of counters per rule)", 73 /* AXP_SM_MATCH_COUNTERS_MEM1 */ "Match Counters 1 (one set of counters per rule)", 74 /* AXP_SM_MATCH_COUNTERS_MEM2 */ "Match Counters 2 (one set of counters per rule)", 75 /* AXP_SM_MATCH_COUNTERS_MEM3 */ "Match Counters 3 (one set of counters per rule)", 76 /* AXP_SM_MATCH_TABLE_BULK_MATCH_DATA */ "Match Table Bulk Clear Data registers.", 77 /* AXP_SM_MATCH_TABLE_BULK_MATCH_MASK */ "Match Table Bulk Clear Mask Control registers.", 78 /* AXP_SM_MATCH_TABLE_BULK_REPLACE_DATA */ "Match Table Bulk Clear Data registers.", 79 /* AXP_SM_MATCH_TABLE_BULK_REPLACE_MASK */ "Match Table Bulk Clear Mask Control registers.", 80 /* AXP_SM_MATCH_TABLE_MEM0 */ "Match Table Memory 0 (one entry per rule ID)", 81 /* AXP_SM_MATCH_TABLE_MEM1 */ "Match Table Memory 1 (one entry per rule ID)", 82 /* AXP_SM_MATCH_TABLE_MEM2 */ "Match Table Memory 2 (one entry per rule ID)", 83 /* AXP_SM_MATCH_TABLE_MEM3 */ "Match Table Memory 3 (one entry per rule ID)", 84 /* AXP_SM_PACKET_BUFFER_MEM */ "Packet Buffer Memory", 85 /* AXP_SM_STATE_TABLE_BULK_MATCH_DATA */ "State Table Bulk Clear Data registers.", 86 /* AXP_SM_STATE_TABLE_BULK_MATCH_MASK */ "State Table Bulk Clear Mask Control registers.", 87 /* AXP_SM_STATE_TABLE_BULK_REPLACE_DATA */ "State Table Bulk Clear Data registers.", 88 /* AXP_SM_STATE_TABLE_BULK_REPLACE_MASK */ "State Table Bulk Clear Mask Control registers.", 89 /* AXP_SM_STATE_TABLE_MEM0 */ "State Table Memory 0", 90 /* AXP_SM_STATE_TABLE_MEM1 */ "State Table Memory 1", 91 /* AXP_SM_STATE_TABLE_MEM2 */ "State Table Memory 2", 92 /* AXP_SM_STATE_TABLE_MEM3 */ "State Table Memory 3", 93 /* AXP_SM_STATE_TABLE_MEM4 */ "State Table Memory 4", 94 /* AXP_SM_STATE_TABLE_MEM5 */ "State Table Memory 5", 95 /* AXP_SM_STATE_TABLE_MEM6 */ "State Table Memory 6", 96 /* AXP_SM_STATE_TABLE_MEM7 */ "State Table Memory 7", 97 /* AXP_WLAN_COS_MAP */ "Final Output Port[5:0], INT_PRI", 98 /* AXP_WRX_SVP_ASSIGNMENT */ "WLAN SVP Assignment Table", 99 /* AXP_WRX_WCD */ "Wireless Client Database Table", 100 /* AXP_WTX_DSCP_MAP */ "MAP the PRI/CFI bits for tunnel outer vlan", 101 /* AXP_WTX_DVP_PROFILE */ "DVP Based properties for WLAN TX", 102 /* AXP_WTX_FRAG_ID */ "Tunnel ID used for CAPWAP FRAG ID and IPv4 ID", 103 /* AXP_WTX_PRI_MAP */ "MAP the PRI/CFI bits for tunnel outer vlan", 104 /* AXP_WTX_TRUNK_BLOCK_MASK */ "Contains trunk nonunicast blockmask", 105 /* AXP_WTX_TRUNK_GROUP_BITMAP */ "Contains trunk group bitmap", 106 /* AXP_WTX_TUNNEL */ "DVP Based properties for WLAN TX", 107 /* BCAST_BLOCK_MASK */ "Broadcast Block Mask, FeatureSpecific-Ethernet.", 108 /* BDM_BDM */ "Bundle descriptor memory for DQM-BDM. 16 descriptors per entry.", 109 /* BDM_BDM_FPC */ "Free pointer memory for DQM-BDM.", 110 /* BLH_FSRD_WL_EXT_MEM */ "SerDes PRAM interface.", 111 /* BRCM_RESERVED_CPM_18 */ "", 112 /* BRCM_RESERVED_CPM_19 */ "", 113 /* BRCM_RESERVED_CPM_20 */ "", 114 /* BRCM_RESERVED_CPM_21 */ "", 115 /* BRCM_RESERVED_CPM_23 */ "", 116 /* BRCM_RESERVED_CPM_24 */ "", 117 /* BRCM_RESERVED_CPM_25 */ "", 118 /* BRCM_RESERVED_CPM_26 */ "", 119 /* BRCM_RESERVED_CPM_27 */ "", 120 /* BRCM_RESERVED_CPM_28 */ "", 121 /* BRCM_RESERVED_CPM_29 */ "", 122 /* BRCM_RESERVED_CPM_30 */ "", 123 /* BRCM_RESERVED_CPM_31 */ "", 124 /* BRCM_RESERVED_CPM_32 */ "", 125 /* BRCM_RESERVED_CPM_33 */ "", 126 /* BRCM_RESERVED_CPM_34 */ "", 127 /* BRCM_RESERVED_CPM_35 */ "", 128 /* BRCM_RESERVED_CPM_36 */ "", 129 /* BRCM_RESERVED_CPM_37 */ "", 130 /* BRCM_RESERVED_CPM_38 */ "", 131 /* BRCM_RESERVED_CPM_39 */ "", 132 /* BRCM_RESERVED_CPM_40 */ "", 133 /* BRCM_RESERVED_CPM_41 */ "", 134 /* BRCM_RESERVED_CPM_42 */ "", 135 /* BRCM_RESERVED_CPM_44 */ "", 136 /* BRCM_RESERVED_CPM_45 */ "", 137 /* BRCM_RESERVED_CPM_46 */ "", 138 /* BRCM_RESERVED_CPM_47 */ "", 139 /* BRCM_RESERVED_CPM_48 */ "", 140 /* BRCM_RESERVED_CPM_49 */ "", 141 /* BRCM_RESERVED_CPM_50 */ "", 142 /* BRCM_RESERVED_CPM_51 */ "", 143 /* BRCM_RESERVED_CPM_52 */ "", 144 /* BRCM_RESERVED_CPM_53 */ "", 145 /* BRCM_RESERVED_CPM_54 */ "", 146 /* BRCM_RESERVED_CPM_55 */ "", 147 /* BRCM_RESERVED_CPM_56 */ "", 148 /* BRCM_RESERVED_CPM_57 */ "", 149 /* BRCM_RESERVED_CPM_58 */ "", 150 /* BRCM_RESERVED_CPM_59 */ "", 151 /* BRCM_RESERVED_CPM_60 */ "", 152 /* BRCM_RESERVED_CPM_61 */ "", 153 /* BRCM_RESERVED_CPM_62 */ "", 154 /* BRCM_RESERVED_CPM_63 */ "", 155 /* BRCM_RESERVED_CPM_335 */ "", 156 /* BRCM_RESERVED_CPM_336 */ "", 157 /* BRCM_RESERVED_CPM_337 */ "", 158 /* BRCM_RESERVED_CPM_338 */ "", 159 /* BRCM_RESERVED_CPM_339 */ "", 160 /* BRCM_RESERVED_CPM_340 */ "", 161 /* BRCM_RESERVED_CPM_341 */ "", 162 /* BRCM_RESERVED_CPM_342 */ "", 163 /* BRDC_CCH_CHF */ "", 164 /* BRDC_CCH_CLF */ "", 165 /* BRDC_CCH_QUERY_DATA_FIFO */ "", 166 /* BRDC_CCH_REACH_FIFO */ "", 167 /* BRDC_DCML_AUTO_DOC_NAME_50 */ "INTERNAL", 168 /* BRDC_DCML_AUTO_DOC_NAME_51 */ "INTERNAL", 169 /* BRDC_DCML_AUTO_DOC_NAME_52 */ "INTERNAL", 170 /* BRDC_DCML_AUTO_DOC_NAME_53 */ "INTERNAL", 171 /* BRDC_DCML_AUTO_DOC_NAME_54 */ "INTERNAL", 172 /* BRDC_DCML_AUTO_DOC_NAME_55 */ "INTERNAL", 173 /* BRDC_DCML_CDM_FIFOS_MEM */ "25 fifos (24 dest. + 1 Gsync) x 36 entries X 122 bit per entry", 174 /* BRDC_FSRD_FSRD_PROM_MEM */ "SerDes PRAM interface.", 175 /* BRDC_FSRD_FSRD_WL_EXT_MEM */ "WarpLite 8051 memory interface.", 176 /* BRDC_HBC_BANK_ORDER_FIFO */ "Fifo holding the bank for each pending read transaction in order of arrival", 177 /* BRDC_HBC_ECC_INFO_FIFO */ "fifo holding transaction information for reporting of ECC errors", 178 /* BRDC_HBC_HBM_DRAM_CPU_ACCESS */ "Dram CPU access", 179 /* BRDC_HBC_HBM_PHY_CH_REGISTER_ACCESS */ "Interface for PHY register access", 180 /* BRDC_HBC_RDR_CHUNK_STORAGE */ "Reassembly memory - Number of lines is the maximum number of banks.", 181 /* BRDC_HBC_RDR_INFO_FIFO */ "Read reassembly info fifo", 182 /* BRDC_HBC_READ_DATA_ASYNC_FIFO */ "Read data async fifo", 183 /* BRDC_HBC_READ_DATA_REORDER */ "Read data reorder memory", 184 /* BRDC_HBC_READ_PER_BANK_QUEUES */ "memory holding per bank read request queues", 185 /* BRDC_HBC_READ_REQUEST_ASYNC_FIFO */ "Read request async fifo", 186 /* BRDC_HBC_WRITE_DATA_ASYNC_FIFO */ "Write data async fifo", 187 /* BRDC_HBC_WRITE_DATA_BUFFER */ "Holds the data for write requests currently in the PBQ", 188 /* BRDC_HBC_WRITE_LATENCY_DELAY */ "data buffer for write latency delay", 189 /* BRDC_HBC_WRITE_PER_BANK_QUEUES */ "memory holding per bank write request queues", 190 /* BRDC_HBC_WRITE_REQUEST_ASYNC_FIFO */ "Write Request async fifo", 191 /* BRDC_LCM_AUTO_DOC_NAME_15 */ "INTERNAL", 192 /* BRDC_LCM_AUTO_DOC_NAME_16 */ "INTERNAL", 193 /* BRDC_LCM_AUTO_DOC_NAME_17 */ "INTERNAL", 194 /* BRDC_LCM_AUTO_DOC_NAME_18 */ "INTERNAL", 195 /* BRDC_LCM_AUTO_DOC_NAME_19 */ "INTERNAL", 196 /* BRDC_QRH_CUCT */ "2Kx192 CRH unicast routing and distribution table. Provides direct access to table.", 197 /* BRDC_QRH_DLLU */ "192x10x4 DRH last link used table. Information is kept per link bundle.", 198 /* BRDC_QRH_DUCT */ "2Kx192 DRH unicast routing and distribution table. Provides direct access to table.", 199 /* BRDC_QRH_FFLB */ "Fault FAPS load balancing. Maps each FAP to load balancing context. There are total 4 contexts. By default all FAPs maps to context 0. Address is bits 10:4 of FAP ID. Data for each FAP contaion 2 bits. 4 LSBs of FAP ID is offset in units of 2 bits. For example in address 15, bits 1:0 are FAP 240, bits 3:2 are FAP 241, up to bits 31:30 which are FAP 255.", 200 /* BRDC_QRH_MCLBT */ "192x192 DRH multicast load balancing table. Provides direct access to table . All tables should be written with the same values for proper operation.", 201 /* BRDC_QRH_MCSFF */ "MultiCase Source Fap Filter - filtering out replication which were originated in the same FAP Address: List of FAPS - FAP-ID List Of Links - group-ID (similar to MCLBT index). Data itself is as following: Bit 11: enable (if set enables this feature for this link-group ID) Bit 10:0: FAP-ID connected to this link group Note this works only in FE2 single stage and FE3", 202 /* BRDC_QRH_MNOL */ "Minimum number of link", 203 /* BRDC_QRH_RESERVED_21 */ "INTERNAL", 204 /* BRDC_QRH_RESERVED_22 */ "INTERNAL", 205 /* BRDC_QRH_RESERVED_23 */ "INTERNAL", 206 /* BSAFE_CMD_DATA_IN */ "Command Data Out Register", 207 /* BSAFE_CMD_DATA_OUT */ "Command Data Out Register", 208 /* BSC_AG_AGE_TABLE */ "FLOW TRACKER ENGINE AGE CONTROL: Scan Table", 209 /* BSC_DG_ALU16_0_EVENT_COUNTER */ "ALU16_0 Counter.", 210 /* BSC_DG_ALU16_1_EVENT_COUNTER */ "ALU16_1 Counter.", 211 /* BSC_DG_ALU16_2_EVENT_COUNTER */ "ALU16_2 Counter.", 212 /* BSC_DG_ALU16_3_EVENT_COUNTER */ "ALU16_3 Counter.", 213 /* BSC_DG_ALU16_4_EVENT_COUNTER */ "ALU16_4 Counter.", 214 /* BSC_DG_ALU16_5_EVENT_COUNTER */ "ALU16_5 Counter.", 215 /* BSC_DG_ALU16_6_EVENT_COUNTER */ "ALU16_6 Counter.", 216 /* BSC_DG_ALU16_7_EVENT_COUNTER */ "ALU16_7 Counter.", 217 /* BSC_DG_ALU32_0_EVENT_COUNTER */ "ALU32_0 Counter.", 218 /* BSC_DG_ALU32_10_EVENT_COUNTER */ "ALU32_10 Counter.", 219 /* BSC_DG_ALU32_11_EVENT_COUNTER */ "ALU32_11 Counter.", 220 /* BSC_DG_ALU32_1_EVENT_COUNTER */ "ALU32_1 Counter.", 221 /* BSC_DG_ALU32_2_EVENT_COUNTER */ "ALU32_2 Counter.", 222 /* BSC_DG_ALU32_3_EVENT_COUNTER */ "ALU32_3 Counter.", 223 /* BSC_DG_ALU32_4_EVENT_COUNTER */ "ALU32_4 Counter.", 224 /* BSC_DG_ALU32_5_EVENT_COUNTER */ "ALU32_5 Counter.", 225 /* BSC_DG_ALU32_6_EVENT_COUNTER */ "ALU32_6 Counter.", 226 /* BSC_DG_ALU32_7_EVENT_COUNTER */ "ALU32_7 Counter.", 227 /* BSC_DG_ALU32_8_EVENT_COUNTER */ "ALU32_8 Counter.", 228 /* BSC_DG_ALU32_9_EVENT_COUNTER */ "ALU32_9 Counter.", 229 /* BSC_DG_COPY_TO_COLLECTOR_COUNTER */ "Opaque State 1 Counter.", 230 /* BSC_DG_FLOW_METER_EXCEED_COUNTER */ "Flow Exceed Counter.", 231 /* BSC_DG_FLOW_OPAQUE_COUNTER_0 */ "Flow TCP Closed Counter.", 232 /* BSC_DG_FLOW_OPAQUE_COUNTER_1 */ "Flow Estabilished Counter.", 233 /* BSC_DG_GROUP_ALU16_PROFILE_0 */ "BSC_DG_GROUP_ALU16 Profile Table.", 234 /* BSC_DG_GROUP_ALU16_PROFILE_1 */ "BSC_DG_GROUP_ALU16 Profile Table.", 235 /* BSC_DG_GROUP_ALU16_PROFILE_2 */ "BSC_DG_GROUP_ALU16 Profile Table.", 236 /* BSC_DG_GROUP_ALU16_PROFILE_3 */ "BSC_DG_GROUP_ALU16 Profile Table.", 237 /* BSC_DG_GROUP_ALU16_PROFILE_4 */ "BSC_DG_GROUP_ALU16 Profile Table.", 238 /* BSC_DG_GROUP_ALU16_PROFILE_5 */ "BSC_DG_GROUP_ALU16 Profile Table.", 239 /* BSC_DG_GROUP_ALU16_PROFILE_6 */ "BSC_DG_GROUP_ALU16 Profile Table.", 240 /* BSC_DG_GROUP_ALU16_PROFILE_7 */ "BSC_DG_GROUP_ALU16 Profile Table.", 241 /* BSC_DG_GROUP_ALU32_PROFILE_0 */ "BSC_DG_GROUP_ALU32 Profile Table.", 242 /* BSC_DG_GROUP_ALU32_PROFILE_1 */ "BSC_DG_GROUP_ALU32 Profile Table.", 243 /* BSC_DG_GROUP_ALU32_PROFILE_2 */ "BSC_DG_GROUP_ALU32 Profile Table.", 244 /* BSC_DG_GROUP_ALU32_PROFILE_3 */ "BSC_DG_GROUP_ALU32 Profile Table.", 245 /* BSC_DG_GROUP_ALU32_PROFILE_4 */ "BSC_DG_GROUP_ALU32 Profile Table.", 246 /* BSC_DG_GROUP_ALU32_PROFILE_5 */ "BSC_DG_GROUP_ALU32 Profile Table.", 247 /* BSC_DG_GROUP_ALU32_PROFILE_6 */ "BSC_DG_GROUP_ALU32 Profile Table.", 248 /* BSC_DG_GROUP_ALU32_PROFILE_7 */ "BSC_DG_GROUP_ALU32 Profile Table.", 249 /* BSC_DG_GROUP_ALU32_PROFILE_8 */ "BSC_DG_GROUP_ALU32 Profile Table.", 250 /* BSC_DG_GROUP_ALU32_PROFILE_9 */ "BSC_DG_GROUP_ALU32 Profile Table.", 251 /* BSC_DG_GROUP_ALU32_PROFILE_10 */ "BSC_DG_GROUP_ALU32 Profile Table.", 252 /* BSC_DG_GROUP_ALU32_PROFILE_11 */ "BSC_DG_GROUP_ALU32 Profile Table.", 253 /* BSC_DG_GROUP_COPY_TO_COLLECTOR_PROFILE */ "COPY TO COLLECTOR Profile Table.", 254 /* BSC_DG_GROUP_LOAD16_PROFILE */ "BSC_DG_GROUP_LOAD16 Profile Table.", 255 /* BSC_DG_GROUP_LOAD8_PROFILE */ "BSC_DG_GROUP_LOAD8 Profile Table.", 256 /* BSC_DG_GROUP_METER_PROFILE */ "BSC_DG_GROUP_METER Profile Table.", 257 /* BSC_DG_GROUP_TABLE */ "Group Table for Data Related Attributes.", 258 /* BSC_DG_GROUP_TIMESTAMP_PROFILE */ "Timestap Profile Table.", 259 /* BSC_DG_METER_EXCEED_COUNTER */ "Meter Exceed Counter.", 260 /* BSC_DG_OPAQUE_STATE_0_COUNTER */ "Opaque State 0 Counter.", 261 /* BSC_DG_OPAQUE_STATE_1_COUNTER */ "Opaque State 1 Counter.", 262 /* BSC_DT_FLEX_SESSION_DATA_DOUBLE */ "BROADSCAN DATA: Flex Session Data Table - Double Wide View", 263 /* BSC_DT_FLEX_SESSION_DATA_SINGLE */ "BROADSCAN DATA: Flex Session Data Table - Single Wide View", 264 /* BSC_DT_FLEX_STATE_TRANSITION_TABLE */ "BROADSCAN DATA: Flex State Transition Table", 265 /* BSC_DT_KMAP_CONTROL_3 */ "BROADSCAN DATA: Kmap Inputs Select Control to select 4 bits out of 8 bit to feed to KAMP", 266 /* BSC_DT_PDE_PROFILE */ "BROADSCAN DATA: PDE Profile Table", 267 /* BSC_EX_COLLECTOR_CONFIG */ "BROADSCAN IPFIX: Collector Config", 268 /* BSC_EX_COLLECTOR_IPFIX_PACKET_BUILD */ "BROADSCAN IPFIX: Collector FIFO Mapping", 269 /* BSC_EX_EXPORT_FIFO */ "BROADSCAN IPFIX: Export FIFO", 270 /* BSC_EX_HDR_CONSTRUCT_CFG */ "BROADSCAN IPFIX: Header construction config, NOTE - only HDR_UPDATE_CTRL_0 supports PAYLOAD_CHKSUM_EN=0 when FLEX_HDR_EDIT_TYPE==CHKSUM", 271 /* BSC_IPFIX_STATS */ "BROADSCAN IPFIX: Stats", 272 /* BSC_KG_ACTIVE_COUNTER */ "Flow Active Counter.", 273 /* BSC_KG_AGE_OUT_COUNTER */ "Flow Active Counter.", 274 /* BSC_KG_AGE_OUT_PROFILE */ "BSC_KG_AGE_OUT Profile Table.", 275 /* BSC_KG_EXCEED_COUNTER */ "Flow Active Counter.", 276 /* BSC_KG_FLOW_ACTIVE_COUNTER */ "Flow Active Counter.", 277 /* BSC_KG_FLOW_AGE_OUT_COUNTER */ "Flow Estabilished Counter.", 278 /* BSC_KG_FLOW_EXCEED_COUNTER */ "Flow Exceed Counter.", 279 /* BSC_KG_FLOW_EXCEED_PROFILE */ "Flow Exceed Profile Table.", 280 /* BSC_KG_FLOW_LEARNED_COUNTER */ "Flow Learned Counter.", 281 /* BSC_KG_FLOW_MISSED_COUNTER */ "Flow Missed Counter.", 282 /* BSC_KG_GROUP_TABLE */ "FT Group Kglue Table.", 283 /* BSC_KG_LEARNED_COUNTER */ "Flow Active Counter.", 284 /* BSC_KG_LEARN_ELIGIBLE_COUNTER */ "Flow Active Counter.", 285 /* BSC_KG_LEARN_MISS_EXPORT_FIFO_FULL_COUNTER */ "Flow Active Counter.", 286 /* BSC_KG_MISSED_COUNTER */ "Flow Active Counter.", 287 /* BSC_KG_SESSION_TABLE_HIT_COUNTER */ "Flow Active Counter.", 288 /* BSC_KT_PURGE_BUFFER */ "BROADSCAN KEY Purge Buffer: This memory will be used to squash the hit subsequent packet hit once CRC error occured on EOP.", 289 /* BSC_TS_UTC_CONVERSION */ "BROADSCAN IPFIX: Timestamp UTC Conversion control. This one-entry table stores 1588 ToD values (UTC time) as computed by the time synchronization algorithm on the ARM core. The entry is to be updated once per second.", 290 /* BSD_EOP_CONTEXT_BUF */ "BROADSCAN DATA EOP CONTEXT BUFFER: Hardware Context Buffer. Read Access only for Debug purpose.", 291 /* BSD_POLICY_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table BSD_POLICY.", 292 /* BSK_ALU_DATA_LTS_MUX_CTRL_PLUS_MASK */ "BROADSCAN SESSION_DATA Keygen Control 1 plus Mask - stores Mux sel and Mask", 293 /* BSK_ALU_DATA_LTS_MUX_CTRL_PLUS_MASK_PIPE0 */ "BROADSCAN SESSION_DATA Keygen Control 1 plus Mask - stores Mux sel and Mask", 294 /* BSK_FTFP_COMBO_TCAM_POLICY */ "BROADSCAN FTFP TCAM", 295 /* BSK_FTFP_LTS_LOGICAL_TBL_SEL_SRAM */ "BSK : Flex key lookup control sram", 296 /* BSK_FTFP_LTS_LOGICAL_TBL_SEL_TCAM */ "BSK FTFP LTS : Key Selection TCAM", 297 /* BSK_FTFP_LTS_MASK_0 */ "BSK_FTFP_LTS : Lookup2 key mask", 298 /* BSK_FTFP_LTS_MASK_1 */ "BSK_FTFP_LTS : Lookup2 key mask", 299 /* BSK_FTFP_LTS_MASK_0_PIPE0 */ "BSK_FTFP_LTS : Lookup2 key mask", 300 /* BSK_FTFP_LTS_MASK_1_PIPE0 */ "BSK_FTFP_LTS : Lookup2 key mask", 301 /* BSK_FTFP_LTS_MUX_CTRL_0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 302 /* BSK_FTFP_LTS_MUX_CTRL_1 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 303 /* BSK_FTFP_LTS_MUX_CTRL_0_PIPE0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 304 /* BSK_FTFP_LTS_MUX_CTRL_1_PIPE0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 305 /* BSK_FTFP_LTS_MUX_CTRL_2_PLUS_MASK */ "BROADSCAN FTFP Keygen Control 2 - stores Mux sel plus Mask", 306 /* BSK_FTFP_LTS_MUX_CTRL_2_PLUS_MASK_PIPE0 */ "BROADSCAN FTFP Keygen Control 2 - stores Mux sel plus Mask", 307 /* BSK_FTFP_POLICY */ "BROADSCAN FTFP Policy", 308 /* BSK_FTFP_TCAM */ "BROADSCAN FTFP TCAM", 309 /* BSK_KMAP_CONTROL_0 */ "BROADSCAN DATA: Kmap Inputs Select Control to select 4 bits out of 8 bit to feed to KAMP", 310 /* BSK_KMAP_CONTROL_1 */ "BROADSCAN DATA: Kmap Inputs Select Control to select 4 bits out of 8 bit to feed to KAMP", 311 /* BSK_KMAP_CONTROL_2 */ "BROADSCAN DATA: Kmap Inputs Select Control to select 4 bits out of 8 bit to feed to KAMP", 312 /* BSK_SESSION_DATA_LTS_MASK_0 */ "BSK_FTFP_LTS : Lookup2 key mask", 313 /* BSK_SESSION_DATA_LTS_MASK_0_PIPE0 */ "BSK_FTFP_LTS : Lookup2 key mask", 314 /* BSK_SESSION_DATA_LTS_MUX_CTRL_0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 315 /* BSK_SESSION_DATA_LTS_MUX_CTRL_0_PIPE0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 316 /* BSK_SESSION_DATA_LTS_MUX_CTRL_1_PLUS_MASK */ "BROADSCAN SESSION_DATA Keygen Control 1 plus Mask - stores Mux sel and Mask", 317 /* BSK_SESSION_DATA_LTS_MUX_CTRL_1_PLUS_MASK_PIPE0 */ "BROADSCAN SESSION_DATA Keygen Control 1 plus Mask - stores Mux sel and Mask", 318 /* BSK_SESSION_KEY_LTS_MASK_0 */ "BSK_FTFP_LTS : Lookup2 key mask", 319 /* BSK_SESSION_KEY_LTS_MASK_1 */ "BSK_FTFP_LTS : Lookup2 key mask", 320 /* BSK_SESSION_KEY_LTS_MASK_0_PIPE0 */ "BSK_FTFP_LTS : Lookup2 key mask", 321 /* BSK_SESSION_KEY_LTS_MASK_1_PIPE0 */ "BSK_FTFP_LTS : Lookup2 key mask", 322 /* BSK_SESSION_KEY_LTS_MUX_CTRL_0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 323 /* BSK_SESSION_KEY_LTS_MUX_CTRL_1 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 324 /* BSK_SESSION_KEY_LTS_MUX_CTRL_0_PIPE0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 325 /* BSK_SESSION_KEY_LTS_MUX_CTRL_1_PIPE0 */ "BROADSCAN FTFP Keygen Control 0 - stores Mux sel", 326 /* BSK_SESSION_KEY_LTS_MUX_CTRL_2_PLUS_MASK */ "BROADSCAN SESSION_KEY Keygen Control 2 - stores Mux sel plus Mask", 327 /* BSK_SESSION_KEY_LTS_MUX_CTRL_2_PLUS_MASK_PIPE0 */ "BROADSCAN SESSION_KEY Keygen Control 2 - stores Mux sel plus Mask", 328 /* CCH_CHF */ "", 329 /* CCH_CLF */ "", 330 /* CCH_QUERY_DATA_FIFO */ "", 331 /* CCH_REACH_FIFO */ "", 332 /* CCS_CDM_FIFOS_MEM */ "37 fifos (36 dest. + 1 Gsync) x 36 entries X 122 bit per entry", 333 /* CCS_QUERY_DATA_FIFO */ "", 334 /* CCS_REACH_FIFO */ "", 335 /* CDMIB_MEM */ "PM8x50 MIB memory", 336 /* CDPORT_TSC_UCMEM_DATA */ "TSC External Memory Interface to program micro-code memory", 337 /* CDUM_INSTRUMENTATION_STATS_MEM_PFC_MEMA */ "instrumentation statistics mem. Per port pfc0 and pfc1 - 0 to 1 transactions , max interval duration, and duty cycle.", 338 /* CDUM_INSTRUMENTATION_STATS_MEM_PFC_MEMB */ "instrumentation statistics mem. Per port pfc2 and pfc3 - 0 to 1 transactions , max interval duration, and duty cycle.", 339 /* CDUM_INSTRUMENTATION_STATS_MEM_PFC_MEMC */ "instrumentation statistics mem. Per port pfc4 and pfc5 - 0 to 1 transactions , max interval duration, and duty cycle.", 340 /* CDUM_INSTRUMENTATION_STATS_MEM_PFC_MEMD */ "instrumentation statistics mem. Per port pfc6 and pfc7 - 0 to 1 transactions , max interval duration, and duty cycle.", 341 /* CDUM_INSTRUMENTATION_STATS_MEM_TRAFFIC_MEMA */ "instrumentation statistics mem. Per port - rx pkt/byte 64 bit counters", 342 /* CDUM_INSTRUMENTATION_STATS_MEM_TRAFFIC_MEMB */ "instrumentation statistics mem. Per port - rx pkt/byte 64 bit counters", 343 /* CDUM_RX_DATA_ASYNC_ALIGNER */ "rx data aligning from pm interface at tsc_clk to core_clk", 344 /* CDUM_RX_MEMA_CTRL */ "rx ctrl memory a", 345 /* CDUM_RX_MEMA_DATA */ "rx data memory a", 346 /* CDUM_RX_MEMB_CTRL */ "rx ctrl memory a", 347 /* CDUM_RX_MEMB_DATA */ "rx data memory b", 348 /* CDUM_RX_MEMC_CTRL */ "rx ctrl memory a", 349 /* CDUM_RX_MEMC_DATA */ "rx data memory c", 350 /* CDUM_RX_MEMD_CTRL */ "rx ctrl memory a", 351 /* CDUM_RX_MEMD_DATA */ "rx data memory d", 352 /* CDUM_RX_MEME_CTRL */ "rx ctrl memory e", 353 /* CDUM_RX_MEME_DATA */ "rx data memory e", 354 /* CDUM_RX_MEMF_CTRL */ "rx ctrl memory f", 355 /* CDUM_RX_MEMF_DATA */ "rx data memory f", 356 /* CDUM_RX_MEMG_CTRL */ "rx ctrl memory g", 357 /* CDUM_RX_MEMG_DATA */ "rx data memory g", 358 /* CDUM_RX_MEMH_CTRL */ "rx ctrl memory h", 359 /* CDUM_RX_MEMH_DATA */ "rx data memory h", 360 /* CDUM_RX_MEMI_CTRL */ "rx ctrl memory i", 361 /* CDUM_RX_MEMI_DATA */ "rx data memory i", 362 /* CDUM_RX_MEMJ_CTRL */ "rx ctrl memory j", 363 /* CDUM_RX_MEMJ_DATA */ "rx data memory j", 364 /* CDUM_RX_MEMK_CTRL */ "rx ctrl memory k", 365 /* CDUM_RX_MEMK_DATA */ "rx data memory k", 366 /* CDUM_RX_MEML_CTRL */ "rx ctrl memory l", 367 /* CDUM_RX_MEML_DATA */ "rx data memory l", 368 /* CDUM_RX_MEMM_CTRL */ "rx ctrl memory m", 369 /* CDUM_RX_MEMM_DATA */ "rx data memory m", 370 /* CDUM_RX_MEMN_CTRL */ "rx ctrl memory n", 371 /* CDUM_RX_MEMN_DATA */ "rx data memory n", 372 /* CDUM_RX_MEMO_CTRL */ "rx ctrl memory o", 373 /* CDUM_RX_MEMO_DATA */ "rx data memory o", 374 /* CDUM_RX_MEMP_CTRL */ "rx ctrl memory p", 375 /* CDUM_RX_MEMP_DATA */ "rx data memory p", 376 /* CDUM_TX_MEMA */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 377 /* CDUM_TX_MEMA_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 378 /* CDUM_TX_MEMB */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 379 /* CDUM_TX_MEMB_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 380 /* CDUM_TX_MEMC */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 381 /* CDUM_TX_MEMC_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 382 /* CDUM_TX_MEMD */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 383 /* CDUM_TX_MEMD_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 384 /* CDUM_TX_MEME */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 385 /* CDUM_TX_MEME_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 386 /* CDUM_TX_MEMF */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 387 /* CDUM_TX_MEMF_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 388 /* CDUM_TX_MEMG */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 389 /* CDUM_TX_MEMG_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 390 /* CDUM_TX_MEMH */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 391 /* CDUM_TX_MEMH_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 392 /* CDUM_TX_MEMI */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 393 /* CDUM_TX_MEMI_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 394 /* CDUM_TX_MEMJ */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 395 /* CDUM_TX_MEMJ_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 396 /* CDU_INSTRUMENTATION_STATS_MEM_PFC_MEMA */ "instrumentation statistics mem. Per port pfc0 and pfc1 - 0 to 1 transactions , max interval duration, and duty cycle.", 397 /* CDU_INSTRUMENTATION_STATS_MEM_PFC_MEMB */ "instrumentation statistics mem. Per port pfc2 and pfc3 - 0 to 1 transactions , max interval duration, and duty cycle.", 398 /* CDU_INSTRUMENTATION_STATS_MEM_PFC_MEMC */ "instrumentation statistics mem. Per port pfc4 and pfc5 - 0 to 1 transactions , max interval duration, and duty cycle.", 399 /* CDU_INSTRUMENTATION_STATS_MEM_PFC_MEMD */ "instrumentation statistics mem. Per port pfc6 and pfc7 - 0 to 1 transactions , max interval duration, and duty cycle.", 400 /* CDU_INSTRUMENTATION_STATS_MEM_TRAFFIC_MEMA */ "instrumentation statistics mem. Per port - rx pkt/byte 64 bit counters", 401 /* CDU_INSTRUMENTATION_STATS_MEM_TRAFFIC_MEMB */ "instrumentation statistics mem. Per port - rx pkt/byte 64 bit counters", 402 /* CDU_RX_DATA_ASYNC_ALIGNER */ "rx data aligning from pm interface at tsc_clk to core_clk", 403 /* CDU_RX_MEMA_CTRL */ "rx ctrl memory a", 404 /* CDU_RX_MEMA_DATA */ "rx data memory a", 405 /* CDU_RX_MEMB_CTRL */ "rx ctrl memory a", 406 /* CDU_RX_MEMB_DATA */ "rx data memory b", 407 /* CDU_RX_MEMC_CTRL */ "rx ctrl memory a", 408 /* CDU_RX_MEMC_DATA */ "rx data memory c", 409 /* CDU_RX_MEMD_CTRL */ "rx ctrl memory a", 410 /* CDU_RX_MEMD_DATA */ "rx data memory d", 411 /* CDU_RX_MEME_CTRL */ "rx ctrl memory e", 412 /* CDU_RX_MEME_DATA */ "rx data memory e", 413 /* CDU_RX_MEMF_CTRL */ "rx ctrl memory f", 414 /* CDU_RX_MEMF_DATA */ "rx data memory f", 415 /* CDU_RX_MEMG_CTRL */ "rx ctrl memory g", 416 /* CDU_RX_MEMG_DATA */ "rx data memory g", 417 /* CDU_RX_MEMH_CTRL */ "rx ctrl memory h", 418 /* CDU_RX_MEMH_DATA */ "rx data memory h", 419 /* CDU_RX_MEMI_CTRL */ "rx ctrl memory i", 420 /* CDU_RX_MEMI_DATA */ "rx data memory i", 421 /* CDU_RX_MEMJ_CTRL */ "rx ctrl memory j", 422 /* CDU_RX_MEMJ_DATA */ "rx data memory j", 423 /* CDU_RX_MEMK_CTRL */ "rx ctrl memory k", 424 /* CDU_RX_MEMK_DATA */ "rx data memory k", 425 /* CDU_RX_MEML_CTRL */ "rx ctrl memory l", 426 /* CDU_RX_MEML_DATA */ "rx data memory l", 427 /* CDU_RX_MEMM_CTRL */ "rx ctrl memory m", 428 /* CDU_RX_MEMM_DATA */ "rx data memory m", 429 /* CDU_RX_MEMN_CTRL */ "rx ctrl memory n", 430 /* CDU_RX_MEMN_DATA */ "rx data memory n", 431 /* CDU_RX_MEMO_CTRL */ "rx ctrl memory o", 432 /* CDU_RX_MEMO_DATA */ "rx data memory o", 433 /* CDU_RX_MEMP_CTRL */ "rx ctrl memory p", 434 /* CDU_RX_MEMP_DATA */ "rx data memory p", 435 /* CDU_TX_MEMA */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 436 /* CDU_TX_MEMA_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 437 /* CDU_TX_MEMB */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 438 /* CDU_TX_MEMB_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 439 /* CDU_TX_MEMC */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 440 /* CDU_TX_MEMC_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 441 /* CDU_TX_MEMD */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 442 /* CDU_TX_MEMD_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 443 /* CDU_TX_MEME */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 444 /* CDU_TX_MEME_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 445 /* CDU_TX_MEMF */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 446 /* CDU_TX_MEMF_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 447 /* CDU_TX_MEMG */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 448 /* CDU_TX_MEMG_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 449 /* CDU_TX_MEMH */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 450 /* CDU_TX_MEMH_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 451 /* CDU_TX_MEMI */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 452 /* CDU_TX_MEMI_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 453 /* CDU_TX_MEMJ */ "tx DATA memory for CDU ports (400G port , 50G SerDes)", 454 /* CDU_TX_MEMJ_CTRL */ "tx CTRL memory for CDU ports (400G port , 50G SerDes)", 455 /* CELL_BUFFER0 */ "Isw2 cell buffer0. This is a logical memory 256 bits wide protected by a 10 bit ECC. Physically, the data is actually interleaved across 4 RAM arrays. Functionally, this is a read only memory, it reads out bits [255:0] of the addressed cell data.", 456 /* CELL_BUFFER1 */ "Isw2 cell buffer1. This is a logical memory 256 bits wide protected by a 10 bit ECC. Physically, the data is actually interleaved across 4 RAM arrays. Functionally, this is a read only memory, it reads out bits [511:256] of the addressed cell data.", 457 /* CELL_BUFFER2 */ "Isw2 cell buffer2. This is a logical memory 256 bits wide protected by a 10 bit ECC. Physically, the data is actually interleaved across 4 RAM arrays. Functionally, this is a read only memory, it reads out bits [767:512] of the addressed cell data.", 458 /* CELL_BUFFER3 */ "Isw2 cell buffer3. This is a logical memory 256 bits wide protected by a 10 bit ECC. Physically, the data is actually interleaved across 4 RAM arrays. Functionally, this is a read only memory, it reads out bits [1023:768] of the addressed cell data.", 459 /* CENTRAL_CTR_EVICTION_FIFO */ "Central Counter eviction fifo", 460 /* CFC_CAT_2_TC_CGM_MAP_HCFC */ "Mapping configuration of category2 and TC VSQs (24-31) to 512 HCFC bitmap.", 461 /* CFC_CAT_2_TC_CGM_MAP_NIF */ "Mapping configuration of category2 and TC VSQs (24-31) to 576 PFC bitmap presented to the NIF.\n Notes:\n * Bitmap is presented to the NIF only if Cat2TcMapEna is set of the corresponding VSQ.\n * If flow control is set, all bitmap set bits will be set. Else, all bitmap bits will be reset with no considuration for previous decision.", 462 /* CFC_CAT_2_TC_IQM_0_MAP_HCFC */ "Mapping configuration of category2 and TC VSQs (24-31) to 512 HCFC bitmap.", 463 /* CFC_CAT_2_TC_IQM_0_MAP_NIF */ "Mapping configuration of category2 and TC VSQs (24-31) to 576 PFC bitmap presented to the NIF.\n Notes:\n * Bitmap is presented to the NIF only if Cat2TcMapEna is set of the corresponding VSQ.\n * If flow control is set, all bitmap set bits will be set. Else, all bitmap bits will be reset with no considuration for previous decision.", 464 /* CFC_CAT_2_TC_IQM_1_MAP_HCFC */ "Mapping configuration of category2 and TC VSQs (24-31) to 512 HCFC bitmap.", 465 /* CFC_CAT_2_TC_IQM_1_MAP_NIF */ "Mapping configuration of category2 and TC VSQs (56-63) to 576 PFC bitmap presented to the NIF.\n Notes:\n * Bitmap is presented to the NIF only if Cat2TcMapEna is set of the corresponding VSQ.\n * If flow control is set, all bitmap set bits will be set. Else, all bitmap bits will be reset with no considuration for previous decision.", 466 /* CFC_CAT_2_TC_MAP_HCFC */ "Mapping configuration of category2 and TC VSQs (20-27) to 256 HCFC bitmap.", 467 /* CFC_CAT_2_TC_MAP_NIF */ "Mapping configuration of category2 and TC VSQs (20-27) to 256 PFC bitmap presented to the NIF.\n Notes:\n * Bitmap is presented to the NIF only if Cat2TcMapEna is set of the corresponding VSQ.\n * If flow control is set, all bitmap set bits will be set. Else, all bitmap bits will be reset with no considuration for previous decision.", 468 /* CFC_CFC_MEMORY_0 */ "INTERNAL", 469 /* CFC_GENERIC_BITMAP_IQM_0_MAP */ "Mapping configuration of generic bitmap", 470 /* CFC_GENERIC_BITMAP_IQM_1_MAP */ "Mapping configuration of generic bitmap", 471 /* CFC_GENERIC_BITMAP_NIF_0_MAP */ "Mapping configuration of generic bitmap", 472 /* CFC_GENERIC_BITMAP_NIF_1_MAP */ "Mapping configuration of generic bitmap", 473 /* CFC_GENERIC_BITMAP_NIF_2_MAP */ "Mapping configuration of generic bitmap", 474 /* CFC_GENERIC_BITMAP_NIF_3_MAP */ "Mapping configuration of generic bitmap", 475 /* CFC_GENERIC_BITMAP_NIF_4_MAP */ "Mapping configuration of generic bitmap", 476 /* CFC_GENERIC_BITMAP_NIF_5_MAP */ "Mapping configuration of generic bitmap", 477 /* CFC_GENERIC_BITMAP_NIF_6_MAP */ "Mapping configuration of generic bitmap", 478 /* CFC_GENERIC_BITMAP_NIF_7_MAP */ "Mapping configuration of generic bitmap", 479 /* CFC_GLB_RSC_CGM_MAP */ "Mapping configuration of IQM0 global resources indication to 512 PFC/128 LLFC bitmap", 480 /* CFC_GLB_RSC_IQM_0_MAP */ "Mapping configuration of IQM0 global resources indication to 512 PFC/128 LLFC bitmap", 481 /* CFC_GLB_RSC_IQM_1_MAP */ "Mapping configuration of IQM1 global resources indication to 512 PFC/128 LLFC bitmap", 482 /* CFC_ILKN_INB_RX_0_CAL */ "Mapping of the ILKN-Inb-RX-0 received FC status frames\n Note:\n PP / Ilkn inband according to IlknInbRx0Sel", 483 /* CFC_ILKN_INB_RX_1_CAL */ "Mapping of the ILKN-Inb-RX-1 received FC status frames\n Note:\n PP / Ilkn inband according to IlknInbRx1Sel", 484 /* CFC_ILKN_INB_RX_2_CAL */ "Mapping of the ILKN-Inb-RX-2 received FC status frames\n Note:\n PP / Ilkn inband according to IlknInbRx2Sel", 485 /* CFC_ILKN_INB_RX_3_CAL */ "Mapping of the ILKN-Inb-RX-3 received FC status frames\n Note:\n PP / Ilkn inband according to IlknInbRx3Sel", 486 /* CFC_ILKN_INB_RX_4_CAL */ "Mapping of the ILKN-Inb-RX-4 received FC status frames\n Note:\n PP / Ilkn inband according to IlknInbRx4Sel", 487 /* CFC_ILKN_INB_RX_5_CAL */ "Mapping of the ILKN-Inb-RX-5 received FC status frames\n Note:\n PP / Ilkn inband according to IlknInbRx5Sel", 488 /* CFC_ILKN_INB_TX_0_CAL */ "Mapping of the ILKN-Inb-TX-0 calendar channels to the possible generated FC indications.", 489 /* CFC_ILKN_INB_TX_1_CAL */ "Mapping of the ILKN-TX-1 calendar channels to the possible generated FC indications.", 490 /* CFC_ILKN_INB_TX_2_CAL */ "Mapping of the ILKN-TX-2 calendar channels to the possible generated FC indications.", 491 /* CFC_ILKN_INB_TX_3_CAL */ "Mapping of the ILKN-TX-3 calendar channels to the possible generated FC indications.", 492 /* CFC_ILKN_INB_TX_4_CAL */ "Mapping of the ILKN-TX-4 calendar channels to the possible generated FC indications.", 493 /* CFC_ILKN_INB_TX_5_CAL */ "Mapping of the ILKN-TX-5 calendar channels to the possible generated FC indications.", 494 /* CFC_ILKN_PP_RX_4_CAL */ "Mapping of the PP-RX received FC status frames to the possible generated FC indications", 495 /* CFC_ILKN_RX_0_CAL */ "Mapping of the ILKN-RX-0 received FC status frames\n Note:\n - In-Band / OOB according to IlknRx0Sel", 496 /* CFC_ILKN_RX_1_CAL */ "Mapping of the ILKN-RX-1 received FC status frames\n Note:\n - In-Band / OOB according to IlknRx1Sel", 497 /* CFC_ILKN_TX_0_CAL */ "Mapping of the ILKN-TX-0 calendar channels to the possible generated FC indications.\n Note:\n - In-Band / OOB according to IlknTx0Sel", 498 /* CFC_ILKN_TX_1_CAL */ "Mapping of the ILKN-TX-1 calendar channels to the possible generated FC indications.\n Note:\n - In-Band / OOB according to IlknTx1Sel", 499 /* CFC_NIF_PFC_MAP */ "Maping the 256 NIF PFC signals.\n Four FC indications are handled in each clock. Each entry refers to 4 consecutive PFC indications.", 500 /* CFC_NIF_SHR_MAP */ "Maping the 256 NIF FCV signals towards the Scheduler HR interface.\n Four FC indications are handled in each clock. Each entry refers to 4 consecutive FCV indications. (this mapping works same as NifPfcMap and share some design resources with it)", 501 /* CFC_OOB_RX_0_CAL */ "Mapping of the SPI/HCFC/ILKN-OOB-RX-0 received FC status frames\n Note:\n - OOB-RX-0 uses only RX interface 0 in the PADS.", 502 /* CFC_OOB_RX_1_CAL */ "Mapping of the SPI/HCFC/ILKN-OOB-RX-1 received FC status frames\n Note:\n - OOB-RX-1 uses only RX interface 1 in the PADS.", 503 /* CFC_OOB_RX_CAL */ "Mapping of the SPI/HCFC/ILKN-OOB-RX-0 received FC status frames\n Note:\n - OOB-RX-0 uses only RX interface 0 in the PADS.", 504 /* CFC_OOB_TX_0_CAL */ "Mapping of the SPI/HCFC/ILKN-OOB-TX-0 calendar channels to the possible generated FC indications.\n Note:\n - OOB-TX-0 uses only TX interface 0 in the PADS.", 505 /* CFC_OOB_TX_1_CAL */ "Mapping of the SPI/HCFC/ILKN-OOB-TX-1 calendar channels to the possible generated FC indications.\n Note:\n - SPI-OOB-TX-1 uses only TX interface 1 in the PADS.", 506 /* CFC_OOB_TX_CAL */ "Mapping of the SPI/HCFC/ILKN-OOB-TX-0 calendar channels to the possible generated FC indications.\n Note:\n - OOB-TX-0 uses only TX interface 0 in the PADS.", 507 /* CFC_PP_RX_4_CAL */ "Mapping of the PP-RX received FC status frames", 508 /* CFC_QPAIR_HR_MAP */ "Map each EGQ-Qpair (EGQ-PFC) to a corresponding SCH-HR (SCH-PFC). For NON-LAG flow control, the mapping is 1:1. Access this table with qp_index/4. Each entry has 4 HR indexes.", 509 /* CFC_RCL_VSQ_CGM_MAP */ "Recycle VSQ To Egress PFC mapping.", 510 /* CFC_RCL_VSQ_IQM_0_MAP */ "Recycle VSQ To PFC mapping.", 511 /* CFC_RCL_VSQ_IQM_1_MAP */ "Recycle VSQ To PFC mapping.", 512 /* CFC_RCL_VSQ_MAP */ "Recycle VSQ To PFC mapping.", 513 /* CFC_SPI_OOB_RX_0_CAL */ "Mapping of the SPI-OOB-RX-0 received FC status frames\n Note:\n - SPI-OOB-RX-0 uses only RX interface 0 in the PADS.", 514 /* CFC_SPI_OOB_RX_1_CAL */ "Mapping of the SPI-OOB-RX-1 received FC status frames\n Note:\n - SPI-OOB-RX-1 uses only RX interface 1 in the PADS.", 515 /* CFC_SPI_OOB_TX_0_CAL */ "Mapping of the SPI-OOB-TX-0 calendar channels to the possible generated FC indications.\n Note:\n - SPI-OOB-TX-0 uses only TX interface 0 in the PADS.", 516 /* CFC_SPI_OOB_TX_1_CAL */ "Mapping of the SPI-OOB-TX-1 calendar channels to the possible generated FC indications.\n Note:\n - SPI-OOB-TX-1 uses only TX interface 1 in the PADS.", 517 /* CGM_ADMT_RATE_LIMITER_TABLE */ "INTERNAL", 518 /* CGM_AUTO_DOC_NAME_75 */ "INTERNAL", 519 /* CGM_AUTO_DOC_NAME_78 */ "INTERNAL", 520 /* CGM_AUTO_DOC_NAME_87 */ "INTERNAL", 521 /* CGM_AUTO_DOC_NAME_90 */ "INTERNAL", 522 /* CGM_AUTO_DOC_NAME_91 */ "INTERNAL", 523 /* CGM_AUTO_DOC_NAME_92 */ "INTERNAL", 524 /* CGM_AUTO_DOC_NAME_93 */ "INTERNAL", 525 /* CGM_AUTO_DOC_NAME_94 */ "INTERNAL", 526 /* CGM_AUTO_DOC_NAME_97 */ "INTERNAL", 527 /* CGM_AUTO_DOC_NAME_98 */ "INTERNAL", 528 /* CGM_AUTO_DOC_NAME_99 */ "INTERNAL", 529 /* CGM_AUTO_DOC_NAME_100 */ "INTERNAL", 530 /* CGM_AUTO_DOC_NAME_101 */ "INTERNAL", 531 /* CGM_AUTO_DOC_NAME_102 */ "INTERNAL", 532 /* CGM_AUTO_DOC_NAME_103 */ "INTERNAL", 533 /* CGM_AUTO_DOC_NAME_104 */ "INTERNAL", 534 /* CGM_AUTO_DOC_NAME_105 */ "INTERNAL", 535 /* CGM_AUTO_DOC_NAME_106 */ "INTERNAL", 536 /* CGM_CNI_PRMS */ "CNI (Congestion Notification Indication) reject parameters.\n Access usign VOQ.Rate-Class.", 537 /* CGM_CNI_STATUS */ "VOQ CNI status.\n Holds for each VOQ its current CNI status.\n\n Each entry hold 32 statuses for 32 VOQs\n Access to the table using VOQ14:5", 538 /* CGM_DESTINATION_TABLE */ "System-Port-ID Mapping table. Access by System-Port-ID", 539 /* CGM_DP_MAPPING */ "Maps dp-meter-cmd, incoming dp, Ethernet-meter-dp and meter-processor-dp to ingress-DP and egress-DP.\n Egress-DP is stamped to the FTMH and ingress-DP is forward to IQM.\n key to the table:\n dp-meter-cmd, incoming-dp, Ethernet-meter-dp, mrps-dp", 540 /* CGM_DRAM_RPRT_RX */ "DRAM report RX FIFO.\n\n Access to this FIFO is forbidden.", 541 /* CGM_DROP_REASON_RJCT_MASK */ "Drop-Reason reject mask table.\n Defines for 8 drop-reasons its relevant admission tests.\n\n Each entry holds masks for a single drop reason.", 542 /* CGM_DTF_TX_RPRT_PEND_FIFO */ "DRAM-To-Fabric TX command update pending FIFO memory", 543 /* CGM_ETH_MTR_PTR_MAP */ "Access to this table using pointers from PP that calculated according to:\n (In-PP-Port)*5+Packet-Type-Value.\n\n Packet-Type-Value:\n 0x0 - Unknown Unicast\n 0x1 - Known Unicast\n 0x2 - Unknown MC\n 0c3 - Known MC\n 0x4 - BC (Broadcast)\n\n In-PP-Port value is 0-255, the", 544 /* CGM_FLOW_AGR_MAP */ "Flow-Aggregate mapping table Map Flow-Aggregate-ID octet to Flow-Quartet and Lag-Group.", 545 /* CGM_FLOW_ATTRIBUTES */ "Flow attributes table Map Flow-ID quarted to Flow-Profile. Access by Flow-ID15:4 and pick profile from the entry using Flow-ID3:2", 546 /* CGM_GLBL_FR_DRAM_DP_RJCT_TH */ "Global free DRAM resources reject thresholds Access using DP Note: reject status is maintained per DP", 547 /* CGM_GLBL_FR_DRAM_RJCT_TH */ "Global free DRAM resources reject thresholds", 548 /* CGM_GLBL_FR_DRAM_TC_RJCT_TH */ "Global free DRAM resources reject thresholds Access using TC Note: reject status is maintained per TC", 549 /* CGM_GLBL_FR_SRAM_DP_RJCT_TH */ "Global free SRAM resources reject thresholds Access using VOQ.Sram-Only, DP Note: reject status is maintained per VOQ.SRAM-Only, DP", 550 /* CGM_GLBL_FR_SRAM_RJCT_TH */ "Global free SRAM resources reject thresholds", 551 /* CGM_GLBL_FR_SRAM_TC_RJCT_TH */ "Global free SRAM resources reject thresholds Access using Sram-Only, TC Note: reject status is maintained per VOQ.SRAM-Only, TC", 552 /* CGM_HAPM */ "Header-Append-Pointer mapping table\n\n Access to this table using Header-Append-Pointer", 553 /* CGM_INSTRUMENTATION_MEMORY */ "Instrumentation FIFO memory. This FIFOs hold the recorded data in a single sampling interval.", 554 /* CGM_INSTRUMENTATION_MEMORY_0 */ "Instrumentation FIFO memory 0", 555 /* CGM_INSTRUMENTATION_MEMORY_1 */ "Instrumentation FIFO memory 1", 556 /* CGM_INSTRUMENTATION_MEMORY_2 */ "Instrumentation FIFO memory 2", 557 /* CGM_INSTRUMENTATION_MEMORY_3 */ "Instrumentation FIFO memory 3", 558 /* CGM_INT_TM_STAT_PTR_MAP */ "Internal TM Statistics Pointer Map. Used to map 13 MSBs of the Queue-Number to 13MSBs of statistics pointer. Statistics-Pointer = IntTmStatPtrMapqueue_number15:3 queue_number2:0", 559 /* CGM_IPPPM */ "In-PP-Port to mapping table\n Maps Incoming PP-Port to PB-VSQs indexes (LLFC & PG).\n\n Access to this table using In-PP-Port\n\n VSQ-E (LLFC) = NIF-Port\n VSQ-F (PG) = PG-Base + VsqPgTcBitmapTcBitmapIndex, TC", 560 /* CGM_IPP_HCP */ "In-PP-Port Header-Compensation-Profile table.\n\n Access to this table using In-PP-Port", 561 /* CGM_IPP_HEADER_COMPENSATION */ "In-PP-Port Header-Compensation-Profile table. Access by In-PP-Port", 562 /* CGM_IPP_MAP */ "In-PP-Port to mapping table Access by In-PP-Port VSQ-E (LLFC) = NIF-Port VSQ-F (PG) = PG-Base + VsqPgTcBitmapTcBitmapIndex, TC", 563 /* CGM_IRPP_CTR_CPM */ "IRPP header compenstaion - Header-Compensation-Profile mapping.\n (Map Header-Compensation-Profile to header delta)", 564 /* CGM_IRPP_CTR_HCM */ "IRPP header compenstaion - Header-Compensation mask table.\n Access using IRPP-Counter-Pointer-A/B MSBs\n\n Note:\n - Entries 0 to 31 are assinged to Counter-A logic\n - Entries 32 to 53 are assinged to Counter-B logic", 565 /* CGM_IS_ING_MC */ "Define for the lower 64k Multicast-ID whether they are Ingress-MC or Fabric/Egress-MC.\n\n Each entry holds 32b for 32 MC-IDs.\n Access to this table using MC-ID15:5.\n MC-ID4:0 selects the relevant bit in the entry.", 566 /* CGM_LAG_ATTRIBUTES */ "LAG attributes table. Access by Lag-Group-ID(14)", 567 /* CGM_LAG_GROUP_PROFILE */ "LAG group profile table. Access by Lag-Profile", 568 /* CGM_LAG_MEMBER_TABLE */ "LAG member table. (aka E-LAG Indirect Table) Access by Lag-Profile", 569 /* CGM_LAG_STAT_ATTRIBUTES */ "LAG statistics attributes table. Access by Lag-Profile", 570 /* CGM_MEMBER_TO_DSP_MAPPING */ "LAG mapping table (aka Member to DSP mapping table) Given the LAG and its member specifies the destination. Entry into table is Partiotion, LAG, LAG-Member.", 571 /* CGM_MEM_0000000 */ "INTERNAL", 572 /* CGM_MEM_100000 */ "INTERNAL", 573 /* CGM_MEM_1000000 */ "INTERNAL", 574 /* CGM_MEM_1010000 */ "INTERNAL", 575 /* CGM_MEM_1050000 */ "INTERNAL", 576 /* CGM_MEM_1060000 */ "INTERNAL", 577 /* CGM_MEM_1070000 */ "INTERNAL", 578 /* CGM_MEM_10A0000 */ "INTERNAL", 579 /* CGM_MEM_B40000 */ "INTERNAL", 580 /* CGM_MEM_B60000 */ "INTERNAL", 581 /* CGM_MEM_B80000 */ "INTERNAL", 582 /* CGM_MEM_BA0000 */ "INTERNAL", 583 /* CGM_MEM_BC0000 */ "INTERNAL", 584 /* CGM_MEM_FB0000 */ "INTERNAL", 585 /* CGM_MEM_FC0000 */ "INTERNAL", 586 /* CGM_MEM_FD0000 */ "INTERNAL", 587 /* CGM_MEM_FE0000 */ "INTERNAL", 588 /* CGM_MEM_FF0000 */ "INTERNAL", 589 /* CGM_MRPS_IN_DP_MAPPING */ "Maps dp-meter-cmd, incoming dp, Ethernet-meter-dp and Ethernet-meter-invalid to MRPS in-DP and in-Drop.\n key to the table:\n dp-meter-cmd, incoming-dp, Ethernet-meter-dp, Ethernet-meter-invalid", 590 /* CGM_PB_VSQ_POOL_FC_TH */ "PB-VSQ flow control.\n Access to this table using Priority, Pool", 591 /* CGM_PB_VSQ_PRMS */ "PB-VSQ (Port-Base VSQs) parameters table\n\n Access to this table using PG (VSQ-F) Index", 592 /* CGM_PB_VSQ_RJCT_MASK */ "PB-VSQ reject mask table.\n Mask admission tests based on PB-VSQ parameters.\n\n Access to this table using:\n 3 - PG.Is-Lossless\n 2:0 - PG.Admit-Profile", 593 /* CGM_PB_VSQ_SRAM_BUFFERS_RJCT_MAP */ "PB-VSQ SRAM-Buffers reject mapping table.\n Map all current admission reject statuses into single reject bit.\n\n Address to this table is:\n 2:0 - PG.Admit-Profile\n 3 - Total-Free-Shared-Resource-Status\n 4 - Port-PG-Shared-Resource-Status\n 5 - Headroom-Extension-Reject-Status\n 6 - Total-Free-Headroom-Resource-Status\n 7 - Port-Headroom-Resource-Status\n 8 - PG-Headroom-Nominal-Resource-Status\n 9 - VOQ-Grntd-Status\n 11:10 - VSQ-Grntd-Status\n\n Each entry holds 384 reject statuses for every PG.Admit-Pro ...", 594 /* CGM_PB_VSQ_SRAM_PDS_RJCT_MAP */ "PB-VSQ SRAM-PDs reject mapping table.\n Map all current admission reject statuses into single reject bit.\n\n Address to this table is:\n 2:0 - PG.Admit-Profile\n 3 - Total-Free-Shared-Resource-Status\n 4 - Port-PG-Shared-Resource-Status\n 5 - Headroom-Extension-Reject-Status\n 6 - Total-Free-Headroom-Resource-Status\n 7 - Port-Headroom-Resource-Status\n 8 - PG-Headroom-Nominal-Resource-Status\n 9 - VOQ-Grntd-Status\n 11:10 - VSQ-Grntd-Status\n\n Each entry holds 384 reject statuses for every PG.Admit-Profile ...", 595 /* CGM_PB_VSQ_TC_BITMAP */ "VSQ PG TC bitmap table. Maps In-PP-Port.TcBitmapIndex, TC to PG-Offset. Access by TC. Each entry holds 16 PG-Offsets(8) for 16 In-PP-Port.TcBitmapIndex. VSQ-E (LLFC) = NIF-Port VSQ-F (PG) = PG-Base + VsqPgTcBitmapTcBitmapIndex, TC", 596 /* CGM_PB_VSQ_WORDS_RJCT_MAP */ "PB-VSQ Words reject mapping table.\n Map all current admission reject statuses into single reject bit.\n\n Address to this table is:\n 2:0 - PG.Admit-Profile\n 3 - Total-Free-Shared-Resource-Reject-Status\n 4 - Port-PG-Shared-Resource-Reject-Status\n 5 - Total-Free-Headroom-Resource-Reject-Status\n 6 - Port-PG-Headroom-Resource-Reject-Status\n 7 - VOQ-Grntd-Status\n 9:8 - VSQ-Grntd-Status\n\n Each entry holds 96 reject statuses for every PG.Admit-Profile.", 597 /* CGM_PCM */ "Packet-Constructor memory.\n Hold packet data waiting for TAR processing completion.\n\n Access to this is forbidden.", 598 /* CGM_PP_RJCT_MASK */ "PP reject mask table.\n Mask admission tests based on Admit-Profile generated by the PP.\n Access to this table using PP.Admit-Profile(3)", 599 /* CGM_QSPM */ "VOQ to System-Port mapping table.\n Access with VOQ14:2 (Every quartet is assigned to System-Port).\n\n Used for System-RED admission logic", 600 /* CGM_REP_CMD_FIFO_OCCUPANCY_RJCT_TH */ "Table holds a set of thresholds to prevent TAR FIFOs overflow. Key = FIFO-Type(2), TM-Command-Type(2), DP (2) FIFO-Type encoding is: 0x0 - MCH 0x1 - MCL 0x2 - UC TM-Command encoding is: 0x0 - FWD 0x1 - SNIF0 0x2 - SNIF1 0x3 - SNIF2 In case FIFO level cross a threshold, the specific command for packets with a specific DP on a specific FIFO is canceled. When applied on SNIF copies, the SNIF copy will not be generated. When applieed on FW copy, the FWD copy will be generated and rejected.", 601 /* CGM_REP_CMD_FIFO_SRAM_RSRC_RJCT_TH */ "Table holds a set of thresholds to protect SPB resources to be exhausting due to packet replications. Key = FIFO-Type(2), TM-Command-Type(2), DP (2) FIFO-Type encoding is: 0x0 - MCH 0x1 - MCL 0x2 - UC TM-Command encoding is: 0x0 - FWD 0x1 - SNIF0 0x2 - SNIF1 0x3 - SNIF2 Each entry holds 2 sets of 2 thresholds. One set to protect Packet-Descriptors, and one set to protect Buffers. Each set hold set and clear threshold for hysteresis. In case resource availability level is below a threshold, the ...", 602 /* CGM_SCH_CPM */ "Credit (SCH) header compenstaion - Header-Compensation-Profile mapping.\n (Map Header-Compensation-Profile to header delta)", 603 /* CGM_SCH_HCM */ "Credit (SCH) header compenstaion - Header-Compensation mask table.\n Access using VOQ.Credit-Class", 604 /* CGM_SMOOTH_DIVISION */ "Smooth division is used in lag resolution in case LagAttributes == 1. Maps LAG-Profile and Lag-LB-Key to a Member. Access this table with either Lag-Profile(6), Lag-LB-Key15:10 or Lag-Profile(6), Lag-LB-Key7:2 (according to LagLbKeySmoothDivisionUseMsb). Each entry hold 4 member. selection using Lag-LB-Key9:8 or Lag-LB-Key1:0 (according to LagLbKeySmoothDivisionUseMsb).", 605 /* CGM_SNIF_ACTION_TABLE */ "SNIFF action tables Note: - table 0 assinged to SNIFF-0 copies (access with SNIFF-Command) - table 1 assinged to SNIFF-1 copies (access with SNIFF-Command) - table 2 assinged to SNIFF-2 copies (access with SNIF-Command)", 606 /* CGM_SNIF_TM_TABLE */ "Snoop-Mirror TM table. Allows overwrite fields from the TM command per TM/Snoop-Command Note: - table 0 assinged to SNIFF-0 copies (access with SNIFF-Command) - table 1 assinged to SNIFF-1 copies (access with SNIFF-Command) - table 2 assinged to SNIFF-2 copies (access with SNIF-Command)", 607 /* CGM_SNP_MRR_RJCT_TABLE */ "Snoop-Mirror reject table.\n\n Note:\n - Entries 0 to 15 are assinged to Snoop copies (access with Snoop-Command)\n - Entries 16 to 32 are assinged to Mirror copies (access with Mirror-Command)", 608 /* CGM_SNP_MRR_TM_TABLE */ "Snoop-Mirror TM table.\n Allows overwrite fields from the TM command per TM/Snoop-Command\n\n Note:\n - Entries 0 to 15 are assinged to Snoop copies (access with Snoop-Command)\n - Entries 16 to 32 are assinged to Mirror copies (access with Mirror-Command)", 609 /* CGM_STACK_FEC_RESOLVE */ "Access if UseStackResolve is set and destination is system port and resolved-queue16:6 == 11'h7ff. Access with Resolved-queue7:2 Lag-LB-Key7:4 The resolved StackLag is used to access StackTrunkResolve.", 610 /* CGM_STACK_TRUNK_RESOLVE */ "Access if UseStackResolve is set and destination is system port and resolved-queue16:6 == 11'h7ff. Access with StackLag, Lag-LB-Key7:4", 611 /* CGM_STAT_CPM */ "Statistics header compenstaion - Header-Compensation-Profile mapping.\n (Map Header-Compensation-Profile to header delta)", 612 /* CGM_STAT_HCM */ "Statistics header compenstaion - Header-Compensation mask table.\n Access using Statistics-Pointer MSBs", 613 /* CGM_STAT_SCRB_TH */ "Scrubber buffer thresholds (Static)\n Each entry include buffer thresholds to be compared to occupied or free buffer counters, this defines the Global-Buffer-Consumption field in the scrubber statistics report (used in Qsize statistics report mode).\n The thresholds define 16 ranges of buffer occupancy.\n Each line coresponds to another level of thresholds.\n The IQM will present the worst result of the 3 buffers types.\n The reference is either to free-buffer or occupied-buffer counters, as defined ...", 614 /* CGM_STD_UPDT_PEND_FIFO */ "SRAM-To-DRAM TX command update pending FIFO memory", 615 /* CGM_ST_PORT_DATA */ "Statistics-Port data FIFO.\n\n Access to this FIFO is forbidden.", 616 /* CGM_SYS_RED_QSIZE */ "System-RED size table Holds for each System-Port the maximal size. Access by System-Port14:4. Used for for System-RED admission logic", 617 /* CGM_SYS_RED_QSIZE_RANGES */ "Source Q size range thresholds.\n Defines 16 ranges of the instantaneous VOQ words size that define the 4-bit System-RED-VOQ size value.\n\n VOQ-Words-Size below RangeThN is defined with Source-VOQ-Size N.\n\n Note:\n - Units of Words (16B)\n - Maximal Value allowed is 2^28 - any value above will disable this TH", 618 /* CGM_SYS_RED_RJCT_PRMS */ "System RED reject parameters.\n Access using VOQ.Rate-Class, DP", 619 /* CGM_SYS_RED_SIZE */ "System-RED size table\n Holds for each System-Port the maximal size.\n Access using System-Port.\n\n Used for for System-RED admission logic", 620 /* CGM_TAR_FIFO */ "TAR descriptors FIFO.\n Holds descriptor of UC/MCH/MCL ready for process by TAR.\n\n Access to this table is forbidden.", 621 /* CGM_TAR_FIFO_RJCT_TH */ "TAR descriptors FIFO reject threshold\n\n Access to this table using FIFO-ID, DP\n FIFO-ID: 0x0 - UC, 0x1 - MCH, 0x2 - MCL", 622 /* CGM_TELEMETRY_QSIZE_RANGES */ "Telemetry Queue-Size Ranges table. Used to map VOQ Queue-Size to 8 queue size ranges.", 623 /* CGM_TM_CTR_CPM */ "TM header compenstaion - Header-Compensation-Profile mapping.\n (Map Header-Compensation-Profile to header delta)", 624 /* CGM_TM_CTR_HCM */ "TM header compenstaion - Header-Compensation mask table.\n Access using TM-Counter-Pointer-A/B MSBs\n\n Note:\n - Entries 0 to 31 are assinged to Counter-A logic\n - Entries 32 to 53 are assinged to Counter-B logic", 625 /* CGM_TRAFFIC_CLASS_MAPPING */ "Map packet traffic class (after metering) to VOQ offset. Entries 0-31 used by system port VOQ resolution. Entries 32-63 used by flow_id VOQ resolution. Entries 64-71 used by fabric MC VOQ resolution.", 626 /* CGM_TX_CMD_UPDT_PEND_FIFO */ "TX command update pending FIFO memory", 627 /* CGM_VOQ_AVRG_PRMS */ "VOQ Average parameters table.\n\n Access using VOQ.Rate-Class\n\n Average-Size = (Average-Size - (Average-Size >>AvrgWeight) +\n (VSQ-Words-Size >>AvrgWeight))", 628 /* CGM_VOQ_CNI_PRMS */ "CNI (Congestion Notification Indication) reject parameters. Access usign VOQ.Rate-Class.", 629 /* CGM_VOQ_CNI_STATUS */ "VOQ CNI status table. Table hold all instantaneous VOQ CNI status Access by VOQ15:5.", 630 /* CGM_VOQ_CONGESTION_PRMS */ "VOQ Words Flow-Controls parameters. When flow control crossed, VOQ congestion report will be generated and interrupt will be raised Access by VOQ.Rate-Class", 631 /* CGM_VOQ_DRAM_BLOCK_RJCT_PRMS */ "VOQ DRAM block parameters.\n Holds parameters for defining thresholds for DRAM-Block.\n\n Access using VOQ.Rate-Class", 632 /* CGM_VOQ_DRAM_BLOCK_STATE */ "VOQ DRAM block state.\n Define for each VOQ its DRAM block state.\n This is dynamic memory -> access for debug purpose only.\n\n Each entry holds 16 states for 16 VOQs.\n Access to this table using VOQ14:4.\n VOQ3:0 selects the relevant VOQ state in the entry.", 633 /* CGM_VOQ_DRAM_BOUND_PRMS */ "VOQ DRAM bound parameters.\n Holds parameters for defining thresholds according which VOQ will be indicated to move traffic from SRAM to DRAM.\n\n Access using VOQ.Rate-Class", 634 /* CGM_VOQ_DRAM_BOUND_PRMS_EXT */ "VOQ DRAM bound parameters extension. Holds parameters for defining thresholds according which VOQ will be indicated to move traffic from SRAM to DRAM. Access by VOQ.Rate-Class", 635 /* CGM_VOQ_DRAM_BOUND_STATE */ "VOQ DRAM Bound state.\n Holds one of the following DRAM-Bound state (2) per VOQ:\n 0x0 - Sram-To-Fabric\n 0x1 - Congested\n 0x2 - Recovery\n\n Each entry holds 16 states for 16 VOQs.\n Address to the table using VOQ14:4", 636 /* CGM_VOQ_DRAM_RECOVERY_CACHE_PRMS */ "VOQ DRAM bound recovery cache parameters Holds parameters for defining thresholds for recovery from MIX-S to SRAM. Access by VOQ.Rate-Class", 637 /* CGM_VOQ_DRAM_RECOVERY_PRMS */ "VOQ DRAM recovery parameters. Holds parameters for defining thresholds for recovery from DRAM to SRAM. Access using VOQ.Rate-Class", 638 /* CGM_VOQ_DRAM_RECOVERY_PRMS_EXT */ "VOQ DRAM recoery parameters extension. Holds parameters for defining thresholds for recovery from DRAM to SRAM. Access by VOQ.Rate-Class", 639 /* CGM_VOQ_GRNTD_PRMS */ "VOQ Guaranteed parameters table\n Table holds static threshold for guaranteed space allocation per VOQ.\n Allocation is seperated for each resource: Words, SRAM-Words and SRAM-PDs.\n\n Access to this table is by VOQ.Rate-Class.", 640 /* CGM_VOQ_GRNTD_RJCT_MASK */ "VOQ Guaranteed reject mask table.\n Mask admission tests based on VOQ state in guaranteed.\n\n Access to this table using:\n 2 - VOQ-Words-In-Guranteed\n 1 - VOQ-SRAM-Words-In-Guranteed\n 0 - VOQ-SRAM-PDs-In-Guranteed", 641 /* CGM_VOQ_HCP */ "VOQ Header-Compensation-Profile table.\n\n Access to this table using VOQ.Credit-Class\n Note: only first 32 entries are used.", 642 /* CGM_VOQ_HEADER_COMPENSATION */ "VOQ Header-Compensation-Profile table. Access by VOQ.Credit-Class", 643 /* CGM_VOQ_LATENCY_RANGES */ "VOQ latency range thresholds.\n Defines 8 ranges of the VOQ latency that define the 3-bit VOQ-Latency value.\n Access by Latency-Flow-Profile", 644 /* CGM_VOQ_LATENCY_RJCT_PRMS */ "System Latency reject parameters.\n Access by VOQ.Rate-Class, DP", 645 /* CGM_VOQ_PROFILES */ "VOQ-Profiles table.\n Table hold all profiles required for ENQ/DEQ process.\n Access to this table using VOQ13:2.\n Entry holds 4 sets of profiles for 4 VOQs (selecting between sets using VOQ1:0.", 646 /* CGM_VOQ_SHRD_FR_RJCT_TH */ "VOQ shared occupancy reject thresholds. Access by VOQ.Sram-Only, DP. Note: reject status is maintained per VOQ.SRAM-Only, DP", 647 /* CGM_VOQ_SHRD_OC_RJCT_TH */ "VOQ shared occupancy reject thresholds.\n Access to this table using DP.", 648 /* CGM_VOQ_SIZE */ "VOQ-Sizes table.\n Table hold all instantaneous VOQ sizes.\n Access to this table using VOQ.", 649 /* CGM_VOQ_SRAM_BUFFERS_RJCT_PRMS */ "VOQ SRAM-Words reject parameters Table holds set of parameters for FADT (Fair-Adaptive-Dynamic-Th) admission logic (on VOQ SRAM-Buffers size) Access by VOQ.Rate-Class, DP Note: - Max value is 2^18", 650 /* CGM_VOQ_SRAM_DRAM_ONLY_MODE */ "VOQ SRAM-DRAM only mode.\n Define for VOQ.Rate-Class its SRAM-DRAM operation mode.", 651 /* CGM_VOQ_SRAM_PDS_RJCT_PRMS */ "VOQ SRAM-PDs reject parameters\n Table holds set of parameters for FADT (Fair-Adaptive-Dynamic-Th) admission logic (on VOQ SRAM-Words size)\n\n Access to the table using VOQ.Rate-Class, DP\n\n Note:\n - Max value is 2^15", 652 /* CGM_VOQ_SRAM_WORDS_RJCT_PRMS */ "VOQ SRAM-Words reject parameters\n Table holds set of parameters for FADT (Fair-Adaptive-Dynamic-Th) admission logic (on VOQ SRAM-Words size)\n\n Access to the table using VOQ.Rate-Class, DP\n\n Note:\n - Max value is 2^18", 653 /* CGM_VOQ_STATE_MEM */ "VOQ-State table. Table hold all instantaneous VOQ states.", 654 /* CGM_VOQ_VSQS_PRMS */ "VOQ - VSQ parameters.\n This table hold for each VOQ its VSQ parameters (for QB-VSQs).\n\n Each entry holds 4 sets of parameters for 4 VOQs.\n Access to this table using VOQ14:2.\n VOQ1:0 selects the relevant set in the entry.", 655 /* CGM_VOQ_WORDS_AVRG_PRMS */ "VOQ Average parameters table. Access by VOQ.Rate-Class", 656 /* CGM_VOQ_WORDS_RJCT_PRMS */ "VOQ Words reject parameters\n Table holds set of parameters for FADT (Fair-Adaptive-Dynamic-Th) admission logic (on VOQ Words size)\n\n Access to the table using VOQ.Rate-Class, DP\n\n Note:\n - Max value is 2^28", 657 /* CGM_VSQA_AVRG_PRMS */ "VSQ - Group A - Average parameters table.\n\n Access using VSQ.Rate-Class\n\n Average-Size = (Average-Size - (Average-Size >>AvrgWeight) +\n (VSQ-Words-Size >>AvrgWeight))", 658 /* CGM_VSQA_FC_PRMS */ "VSQ - Group A - Flow-Control parameters table Access to the table using VSQ.Rate-Class", 659 /* CGM_VSQA_MAX_SIZE */ "VSQ - Group A - Max size tracking memory", 660 /* CGM_VSQA_MAX_SIZE_MEM */ "VSQ - Group A - Max size tracking memory", 661 /* CGM_VSQA_PRMS */ "VSQ (Virtual Statistics Queue) - Group A (Categoty) parameters.\n Access table using VSQ-A-Index.", 662 /* CGM_VSQA_RJCT_PRMS */ "VSQ - Group A - reject parameters table Access to the table using VSQ.Rate-Class, DP", 663 /* CGM_VSQA_SRAM_BUFFERS_FC_PRMS */ "VSQ - Group A - Flow-Control SRAM-Buffers parameters table\n\n Access to the table using VSQ.Rate-Class", 664 /* CGM_VSQA_SRAM_BUFFERS_RJCT_PRMS */ "VSQ - Group A - SRAM-Buffers-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 665 /* CGM_VSQA_SRAM_BUFFERS_SIZE */ "Instantaneous VSQ-A SRAM-Buffers Size memory.\n Access to this table (for debug purpose only) using VSQ-A Index", 666 /* CGM_VSQA_SRAM_BUFFERS_STATE */ "Instantaneous VSQ-A SRAM-Buffers Size memory. Access by VSQ-A Index", 667 /* CGM_VSQA_SRAM_PDS_FC_PRMS */ "VSQ - Group A - Flow-Control SRAM-PDs parameters table\n\n Access to the table using VSQ.Rate-Class", 668 /* CGM_VSQA_SRAM_PDS_RJCT_PRMS */ "VSQ - Group A - SRAM-PDs-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 669 /* CGM_VSQA_SRAM_PDS_SIZE */ "Instantaneous VSQ-A SRAM-PDs Size memory.\n Access to this table (for debug purpose only) using VSQ-A Index", 670 /* CGM_VSQA_SRAM_PDS_STATE */ "Instantaneous VSQ-A SRAM-PDs Size memory. Access by VSQ-A Index", 671 /* CGM_VSQA_WORDS_AVRG_PRMS */ "VSQ - Group A - Average parameters table. Access by VSQ.Rate-Class", 672 /* CGM_VSQA_WORDS_FC_PRMS */ "VSQ - Group A - Flow-Control Words parameters table\n\n Access to the table using VSQ.Rate-Class", 673 /* CGM_VSQA_WORDS_RJCT_PRMS */ "VSQ - Group A - Words-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 674 /* CGM_VSQA_WORDS_SIZE */ "Instantaneous VSQ-A Words Size memory.\n Access to this table (for debug purpose only) using VSQ-A Index", 675 /* CGM_VSQA_WORDS_STATE */ "Instantaneous VSQ-A Words Size memory. Access by VSQ-A Index", 676 /* CGM_VSQA_WRED_RJCT_PRMS */ "VSQ - Group A - WRED asmission test parameters table\n\n Access using VSQ.Rate-Class, DP", 677 /* CGM_VSQB_AVRG_PRMS */ "VSQ - Group B - Average parameters table.\n\n Access using VSQ.Rate-Class\n\n Average-Size = (Average-Size - (Average-Size >>AvrgWeight) +\n (VSQ-Words-Size >>AvrgWeight))", 678 /* CGM_VSQB_FC_PRMS */ "VSQ - Group B - Flow-Control parameters table Access to the table using VSQ.Rate-Class", 679 /* CGM_VSQB_MAX_SIZE */ "VSQ - Group B - Max size tracking memory", 680 /* CGM_VSQB_MAX_SIZE_MEM */ "VSQ - Group B - Max size tracking memory", 681 /* CGM_VSQB_PRMS */ "VSQ (Virtual Statistics Queue) - Group B (Categoty x VOQ.TC) parameters.\n Access table using VSQ-B-Index.", 682 /* CGM_VSQB_RJCT_PRMS */ "VSQ - Group B - reject parameters table Access using VSQ.Rate-Class, DP", 683 /* CGM_VSQB_SRAM_BUFFERS_FC_PRMS */ "VSQ - Group B - Flow-Control SRAM-Buffers parameters table\n\n Access to the table using VSQ.Rate-Class", 684 /* CGM_VSQB_SRAM_BUFFERS_RJCT_PRMS */ "VSQ - Group B - SRAM-Buffers-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 685 /* CGM_VSQB_SRAM_BUFFERS_SIZE */ "Instantaneous VSQ-B SRAM-Buffers Size memory.\n Access to this table (for debug purpose only) using VSQ-B Index", 686 /* CGM_VSQB_SRAM_BUFFERS_STATE */ "Instantaneous VSQ-B SRAM-Buffers Size memory. Access by VSQ-B Index", 687 /* CGM_VSQB_SRAM_PDS_FC_PRMS */ "VSQ - Group B - Flow-Control SRAM-PDs parameters table\n\n Access to the table using VSQ.Rate-Class", 688 /* CGM_VSQB_SRAM_PDS_RJCT_PRMS */ "VSQ - Group B - SRAM-PDs-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 689 /* CGM_VSQB_SRAM_PDS_SIZE */ "Instantaneous VSQ-A SRAM-PDs Size memory.\n Access to this table (for debug purpose only) using VSQ-B Index", 690 /* CGM_VSQB_SRAM_PDS_STATE */ "Instantaneous VSQ-A SRAM-PDs Size memory. Access by VSQ-B Index", 691 /* CGM_VSQB_WORDS_AVRG_PRMS */ "VSQ - Group B - Average parameters table. Access by VSQ.Rate-Class", 692 /* CGM_VSQB_WORDS_FC_PRMS */ "VSQ - Group B - Flow-Control Words parameters table\n\n Access to the table using VSQ.Rate-Class", 693 /* CGM_VSQB_WORDS_RJCT_PRMS */ "VSQ - Group B - Words-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 694 /* CGM_VSQB_WORDS_SIZE */ "Instantaneous VSQ-B Words Size memory.\n Access to this table (for debug purpose only) using VSQ-B Index", 695 /* CGM_VSQB_WORDS_STATE */ "Instantaneous VSQ-B Words Size memory. Access by VSQ-B Index", 696 /* CGM_VSQB_WRED_RJCT_PRMS */ "VSQ - Group B - WRED asmission test parameters table\n\n Access using VSQ.Rate-Class, DP", 697 /* CGM_VSQC_AVRG_PRMS */ "VSQ - Group C - Average parameters table.\n\n Access using VSQ.Rate-Class\n\n Average-Size = (Average-Size - (Average-Size >>AvrgWeight) +\n (VSQ-Words-Size >>AvrgWeight))", 698 /* CGM_VSQC_FC_PRMS */ "VSQ - Group C - Flow-Control parameters table Access to the table using VSQ.Rate-Class", 699 /* CGM_VSQC_MAX_SIZE */ "VSQ - Group C - Max size tracking memory", 700 /* CGM_VSQC_MAX_SIZE_MEM */ "VSQ - Group C - Max size tracking memory", 701 /* CGM_VSQC_PRMS */ "VSQ (Virtual Statistics Queue) - Group B (Categoty x VOQ.Connection-Class) parameters.\n Access table using VSQ-C-Index.", 702 /* CGM_VSQC_RJCT_PRMS */ "VSQ - Group C - reject parameters table Access using VSQ.Rate-Class, DP", 703 /* CGM_VSQC_SRAM_BUFFERS_FC_PRMS */ "VSQ - Group C - Flow-Control SRAM-Buffers parameters table\n\n Access to the table using VSQ.Rate-Class", 704 /* CGM_VSQC_SRAM_BUFFERS_RJCT_PRMS */ "VSQ - Group C - SRAM-Buffers-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 705 /* CGM_VSQC_SRAM_BUFFERS_SIZE */ "Instantaneous VSQ-C SRAM-Buffers Size memory.\n Access to this table (for debug purpose only) using VSQ-C Index", 706 /* CGM_VSQC_SRAM_BUFFERS_STATE */ "Instantaneous VSQ-C SRAM-Buffers Size memory. Access by VSQ-C Index", 707 /* CGM_VSQC_SRAM_PDS_FC_PRMS */ "VSQ - Group C - Flow-Control SRAM-PDs parameters table\n\n Access to the table using VSQ.Rate-Class", 708 /* CGM_VSQC_SRAM_PDS_RJCT_PRMS */ "VSQ - Group C - SRAM-PDs-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 709 /* CGM_VSQC_SRAM_PDS_SIZE */ "Instantaneous VSQ-C SRAM-PDs Size memory.\n Access to this table (for debug purpose only) using VSQ-D Index", 710 /* CGM_VSQC_SRAM_PDS_STATE */ "Instantaneous VSQ-C SRAM-PDs Size memory. Access by VSQ-D Index", 711 /* CGM_VSQC_WORDS_AVRG_PRMS */ "VSQ - Group C - Average parameters table. Access by VSQ.Rate-Class", 712 /* CGM_VSQC_WORDS_FC_PRMS */ "VSQ - Group C - Flow-Control Words parameters table\n\n Access to the table using VSQ.Rate-Class", 713 /* CGM_VSQC_WORDS_RJCT_PRMS */ "VSQ - Group C - Words-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 714 /* CGM_VSQC_WORDS_SIZE */ "Instantaneous VSQ-C Words Size memory.\n Access to this table (for debug purpose only) using VSQ-C Index", 715 /* CGM_VSQC_WORDS_STATE */ "Instantaneous VSQ-C Words Size memory. Access by VSQ-C Index", 716 /* CGM_VSQC_WRED_RJCT_PRMS */ "VSQ - Group C - WRED asmission test parameters table\n\n Access using VSQ.Rate-Class, DP", 717 /* CGM_VSQD_AVRG_PRMS */ "VSQ - Group D - Average parameters table.\n\n Access using VSQ.Rate-Class\n\n Average-Size = (Average-Size - (Average-Size >>AvrgWeight) +\n (VSQ-Words-Size >>AvrgWeight))", 718 /* CGM_VSQD_FC_PRMS */ "VSQ - Group D - Flow-Control parameters table Access to the table using VSQ.Rate-Class", 719 /* CGM_VSQD_MAX_SIZE */ "VSQ - Group D - Max size tracking memory", 720 /* CGM_VSQD_MAX_SIZE_MEM */ "VSQ - Group D - Max size tracking memory", 721 /* CGM_VSQD_PRMS */ "VSQ (Virtual Statistics Queue) - Group B (Statistics-VSQ-Ptr) parameters.\n Access table using VSQ-D-Index.", 722 /* CGM_VSQD_RJCT_PRMS */ "VSQ - Group D - reject parameters table Access using VSQ.Rate-Class, DP", 723 /* CGM_VSQD_SRAM_BUFFERS_FC_PRMS */ "VSQ - Group D - Flow-Control SRAM-Buffers parameters table\n\n Access to the table using VSQ.Rate-Class", 724 /* CGM_VSQD_SRAM_BUFFERS_RJCT_PRMS */ "VSQ - Group D - SRAM-Buffers-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 725 /* CGM_VSQD_SRAM_BUFFERS_SIZE */ "Instantaneous VSQ-D SRAM-Buffers Size memory.\n Access to this table (for debug purpose only) using VSQ-D Index", 726 /* CGM_VSQD_SRAM_BUFFERS_STATE */ "Instantaneous VSQ-D SRAM-Buffers Size memory. Access by VSQ-D Index", 727 /* CGM_VSQD_SRAM_PDS_FC_PRMS */ "VSQ - Group D - Flow-Control SRAM-PDs parameters table\n\n Access to the table using VSQ.Rate-Class", 728 /* CGM_VSQD_SRAM_PDS_RJCT_PRMS */ "VSQ - Group D - SRAM-PDs-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 729 /* CGM_VSQD_SRAM_PDS_SIZE */ "Instantaneous VSQ-D SRAM-PDs Size memory.\n Access to this table (for debug purpose only) using VSQ-E Index", 730 /* CGM_VSQD_SRAM_PDS_STATE */ "Instantaneous VSQ-D SRAM-PDs Size memory. Access by VSQ-E Index", 731 /* CGM_VSQD_WORDS_AVRG_PRMS */ "VSQ - Group D - Average parameters table. Access by VSQ.Rate-Class", 732 /* CGM_VSQD_WORDS_FC_PRMS */ "VSQ - Group D - Flow-Control Words parameters table\n\n Access to the table using VSQ.Rate-Class", 733 /* CGM_VSQD_WORDS_RJCT_PRMS */ "VSQ - Group D - Words-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 734 /* CGM_VSQD_WORDS_SIZE */ "Instantaneous VSQ-D Words Size memory.\n Access to this table (for debug purpose only) using VSQ-D Index", 735 /* CGM_VSQD_WORDS_STATE */ "Instantaneous VSQ-D Words Size memory. Access by VSQ-D Index", 736 /* CGM_VSQD_WRED_RJCT_PRMS */ "VSQ - Group D - WRED asmission test parameters table\n\n Access using VSQ.Rate-Class, DP", 737 /* CGM_VSQE_AVRG_PRMS */ "VSQ - Group E - Average parameters table.\n\n Access using VSQ.Rate-Class\n\n Average-Size = (Average-Size - (Average-Size >>AvrgWeight) +\n (VSQ-Words-Size >>AvrgWeight))", 738 /* CGM_VSQE_FC_PRMS */ "VSQ - Group E - Flow-Control parameters table Access to the table using PG.Pool-ID, VSQ.Rate-Class", 739 /* CGM_VSQE_MAX_SIZE */ "VSQ - Group E - Max size tracking memory", 740 /* CGM_VSQE_MAX_SIZE_MEM */ "VSQ - Group E - Max size tracking memory", 741 /* CGM_VSQE_PRMS */ "VSQ (Virtual Statistics Queue) - Group E (LLFC) parameters.\n Access table using VSQ-E-Index.", 742 /* CGM_VSQE_RJCT_PRMS */ "VSQ - Group E - reject parameters table Access to the table using Pool-ID, VSQ.Rate-Class, DP", 743 /* CGM_VSQE_SRAM_BUFFERS_FC_PRMS */ "VSQ - Group E - Flow-Control SRAM-Buffers parameters table\n\n Access to the table using PG.Pool-ID, VSQ.Rate-Class", 744 /* CGM_VSQE_SRAM_BUFFERS_RJCT_PRMS */ "VSQ - Group E - SRAM-Buffers-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using Pool-ID, VSQ.Rate-Class", 745 /* CGM_VSQE_SRAM_BUFFERS_SIZE */ "Instantaneous VSQ-E (LLFC) SRAM-Buffers Size memory.\n Access to this table (for debug purpose only) using VSQ-E Index", 746 /* CGM_VSQE_SRAM_BUFFERS_STATE */ "Instantaneous VSQ-E (LLFC) SRAM-Buffers Size memory. Access by VSQ-E Index", 747 /* CGM_VSQE_SRAM_PDS_FC_PRMS */ "VSQ - Group E - Flow-Control SRAM-PDs parameters table\n\n Access to the table using PG.Pool-ID, VSQ.Rate-Class", 748 /* CGM_VSQE_SRAM_PDS_RJCT_PRMS */ "VSQ - Group E - SRAM-PDs-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using Pool-ID, VSQ.Rate-Class", 749 /* CGM_VSQE_SRAM_PDS_SIZE */ "Instantaneous VSQ-E (LLFC) SRAM-PDs Size memory.\n Access to this table (for debug purpose only) using VSQ-A Index", 750 /* CGM_VSQE_SRAM_PDS_STATE */ "Instantaneous VSQ-E (LLFC) SRAM-PDs Size memory. Access by VSQ-E Index", 751 /* CGM_VSQE_WORDS_AVRG_PRMS */ "VSQ - Group E - Average parameters table. Access by VSQ.Rate-Class", 752 /* CGM_VSQE_WORDS_FC_PRMS */ "VSQ - Group E - Flow-Control Words parameters table\n\n Access to the table using PG.Pool-ID, VSQ.Rate-Class", 753 /* CGM_VSQE_WORDS_RJCT_PRMS */ "VSQ - Group E - Words-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using Pool-ID, VSQ.Rate-Class", 754 /* CGM_VSQE_WORDS_SIZE */ "Instantaneous VSQ-E (LLFC) Words Size memory.\n Access to this table (for debug purpose only) using VSQ-E Index", 755 /* CGM_VSQE_WORDS_STATE */ "Instantaneous VSQ-E (LLFC) Words Size memory. Access by VSQ-E Index", 756 /* CGM_VSQE_WRED_RJCT_PRMS */ "VSQ - Group E - WRED asmission test parameters table\n\n Access using VSQ.Rate-Class, DP", 757 /* CGM_VSQF_AVRG_PRMS */ "VSQ - Group F - Average parameters table.\n\n Access using VSQ.Rate-Class\n\n Average-Size = (Average-Size - (Average-Size >>AvrgWeight) +\n (VSQ-Words-Size >>AvrgWeight))", 758 /* CGM_VSQF_FC_PRMS */ "VSQ - Group F - Flow-Control Words parameters table Access to the table using VSQ.Rate-Class", 759 /* CGM_VSQF_MAX_SIZE */ "VSQ - Group F - Max size tracking memory", 760 /* CGM_VSQF_MAX_SIZE_MEM */ "VSQ - Group F - Max size tracking memory", 761 /* CGM_VSQF_PRMS */ "VSQ (Virtual Statistics Queue) - Group F (PFC/PG) parameters.\n Access table using VSQ-F-Index.", 762 /* CGM_VSQF_RJCT_PRMS */ "VSQ - Group F - reject parameters table Access using VSQ.Rate-Class, DP", 763 /* CGM_VSQF_SRAM_BUFFERS_FC_PRMS */ "VSQ - Group F - Flow-Control SRAM-Buffers parameters table\n\n Access to the table using VSQ.Rate-Class", 764 /* CGM_VSQF_SRAM_BUFFERS_RJCT_PRMS */ "VSQ - Group F - SRAM-Buffers-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using Pool-ID, VSQ.Rate-Class", 765 /* CGM_VSQF_SRAM_BUFFERS_SIZE */ "Instantaneous VSQ-F (PFC/PG) SRAM-Buffers Size memory.\n Access to this table (for debug purpose only) using VSQ-F Index", 766 /* CGM_VSQF_SRAM_BUFFERS_STATE */ "Instantaneous VSQ-F (PFC/PG) SRAM-Buffers Size memory. Access by VSQ-F Index", 767 /* CGM_VSQF_SRAM_PDS_FC_PRMS */ "VSQ - Group F - Flow-Control SRAM-PDs parameters table\n\n Access to the table using VSQ.Rate-Class", 768 /* CGM_VSQF_SRAM_PDS_RJCT_PRMS */ "VSQ - Group F - SRAM-PDs-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using VSQ.Rate-Class", 769 /* CGM_VSQF_SRAM_PDS_SIZE */ "Instantaneous VSQ-F (PFC/PG) SRAM-PDs Size memory.\n Access to this table (for debug purpose only) using VSQ-F Index", 770 /* CGM_VSQF_SRAM_PDS_STATE */ "Instantaneous VSQ-F (PFC/PG) SRAM-PDs Size memory. Access by VSQ-F Index", 771 /* CGM_VSQF_WORDS_AVRG_PRMS */ "VSQ - Group F - Average parameters table. Access by VSQ.Rate-Class", 772 /* CGM_VSQF_WORDS_FC_PRMS */ "VSQ - Group F - Flow-Control Words parameters table\n\n Access to the table using VSQ.Rate-Class", 773 /* CGM_VSQF_WORDS_RJCT_PRMS */ "VSQ - Group F - Words-Size reject parameters table\n\n Each entry hold statis threshold per DP.\n Access to the table using Pool-ID, VSQ.Rate-Class", 774 /* CGM_VSQF_WORDS_SIZE */ "Instantaneous VSQ-F (PFC/PG) Words Size memory.\n Access to this table (for debug purpose only) using VSQ-F Index", 775 /* CGM_VSQF_WORDS_STATE */ "Instantaneous VSQ-F (PFC/PG) Words Size memory. Access by VSQ-F Index", 776 /* CGM_VSQF_WRED_RJCT_PRMS */ "VSQ - Group F - WRED asmission test parameters table\n\n Access using VSQ.Rate-Class, DP", 777 /* CGM_VSQ_GRNTD_RJCT_MASK */ "VSQ Guaranteed reject mask table.\n Mask admission tests based on VSQ state in guaranteed.\n\n Access to this table using:\n 2 - VSQ-Words-In-Guranteed\n 1 - VSQ-SRAM-Buffers-In-Guranteed\n 0 - VSQ-SRAM-PDs-In-Guranteed", 778 /* CGM_VSQ_PG_TC_BITMAP */ "VSQ PG TC bitmap table.\n Maps In-PP-Port.TcBitmapIndex, TC to PG-Offset.\n\n Access to this table using TC.\n Each entry holds 16 PG-Offsets(8) for 16 In-PP-Port.TcBitmapIndex.\n\n VSQ-E (LLFC) = NIF-Port\n VSQ-F (PG) = PG-Base + VsqPgTcBitmapTcBitmapIndex, TC", 779 /* CGM_VSQ_SHRD_FR_RJCT_TH */ "VSQ shared occupancy reject thresholds. Access by PG.Pool-ID, DP.", 780 /* CGM_VSQ_SHRD_OC_RJCT_TH */ "VSQ shared occupancy reject thresholds.\n Access to this table using DP.", 781 /* CLPORT_WC_UCMEM_DATA */ "", 782 /* CNG_MAP */ "CNG Mapping MEMORY", 783 /* CNG_STRENGTH_PROFILE */ "CNG Strength Profile.", 784 /* COS_MAP_SEL */ "Select one of four sections of COS_MAP table.", 785 /* CPMPORT_WC_UCMEM_DATA */ "PMD External Memory Interface to program micro-controller memory", 786 /* CPRI_BFA_TAB0_CFG_0 */ "Basic frame assembly mapping table copy 0 Port 0", 787 /* CPRI_BFA_TAB0_CFG_1 */ "Basic frame assembly mapping table copy 0 Port 1", 788 /* CPRI_BFA_TAB0_CFG_2 */ "Basic frame assembly mapping table copy 0 Port 2", 789 /* CPRI_BFA_TAB0_CFG_3 */ "Basic frame assembly mapping table copy 0 Port 3", 790 /* CPRI_BFA_TAB1_CFG_0 */ "Basic frame assembly mapping table copy 1 Port 0", 791 /* CPRI_BFA_TAB1_CFG_1 */ "Basic frame assembly mapping table copy 1 Port 1", 792 /* CPRI_BFA_TAB1_CFG_2 */ "Basic frame assembly mapping table copy 1 Port 2", 793 /* CPRI_BFA_TAB1_CFG_3 */ "Basic frame assembly mapping table copy 1 Port 3", 794 /* CPRI_BFP_TAB0_CFG_0 */ "Basic frame parser mapping table copy 0 Port 0", 795 /* CPRI_BFP_TAB0_CFG_1 */ "Basic frame parser mapping table copy 0 Port 1", 796 /* CPRI_BFP_TAB0_CFG_2 */ "Basic frame parser mapping table copy 0 Port 2", 797 /* CPRI_BFP_TAB0_CFG_3 */ "Basic frame parser mapping table copy 0 Port 3", 798 /* CPRI_BFP_TAB1_CFG_0 */ "Basic frame parser mapping table copy 1 Port 0", 799 /* CPRI_BFP_TAB1_CFG_1 */ "Basic frame parser mapping table copy 1 Port 1", 800 /* CPRI_BFP_TAB1_CFG_2 */ "Basic frame parser mapping table copy 1 Port 2", 801 /* CPRI_BFP_TAB1_CFG_3 */ "Basic frame parser mapping table copy 1 Port 3", 802 /* CPRI_CA_MAP_STATE_TAB_STS_0 */ "Container assembly mapping state table Port 0. Addressed by AxCC ID.", 803 /* CPRI_CA_MAP_STATE_TAB_STS_1 */ "Container assembly mapping state table Port 1. Addressed by AxCC ID.", 804 /* CPRI_CA_MAP_STATE_TAB_STS_2 */ "Container assembly mapping state table Port 2. Addressed by AxCC ID.", 805 /* CPRI_CA_MAP_STATE_TAB_STS_3 */ "Container assembly mapping state table Port 3. Addressed by AxCC ID.", 806 /* CPRI_CA_MAP_TAB_CFG_0 */ "Container assembly mapping table Port 0. Addressed by AxCC ID.", 807 /* CPRI_CA_MAP_TAB_CFG_1 */ "Container assembly mapping table Port 1. Addressed by AxCC ID.", 808 /* CPRI_CA_MAP_TAB_CFG_2 */ "Container assembly mapping table Port 2. Addressed by AxCC ID.", 809 /* CPRI_CA_MAP_TAB_CFG_3 */ "Container assembly mapping table Port 3. Addressed by AxCC ID.", 810 /* CPRI_CA_PAY_TAB_CFG_0 */ "Container assembly payload table memory Port 0. Addressed by AxCC ID.", 811 /* CPRI_CA_PAY_TAB_CFG_1 */ "Container assembly payload table memory Port 1. Addressed by AxCC ID.", 812 /* CPRI_CA_PAY_TAB_CFG_2 */ "Container assembly payload table memory Port 2. Addressed by AxCC ID.", 813 /* CPRI_CA_PAY_TAB_CFG_3 */ "Container assembly payload table memory Port 3. Addressed by AxCC ID.", 814 /* CPRI_CPRSR_IQ_PK_BUFF_CFG_0 */ "Container parser iq_pk_buff memory Port 0. Indexed using AxCC ID", 815 /* CPRI_CPRSR_IQ_PK_BUFF_CFG_1 */ "Container parser iq_pk_buff memory Port 1. Indexed using AxCC ID", 816 /* CPRI_CPRSR_IQ_PK_BUFF_CFG_2 */ "Container parser iq_pk_buff memory Port 2. Indexed using AxCC ID", 817 /* CPRI_CPRSR_IQ_PK_BUFF_CFG_3 */ "Container parser iq_pk_buff memory Port 3. Indexed using AxCC ID", 818 /* CPRI_CPRSR_MAP_STATE_TAB_STS_0 */ "Container parser mapping state table Port 0. Indexed using AxCC ID", 819 /* CPRI_CPRSR_MAP_STATE_TAB_STS_1 */ "Container parser mapping state table Port 1. Indexed using AxCC ID", 820 /* CPRI_CPRSR_MAP_STATE_TAB_STS_2 */ "Container parser mapping state table Port 2. Indexed using AxCC ID", 821 /* CPRI_CPRSR_MAP_STATE_TAB_STS_3 */ "Container parser mapping state table Port 3. Indexed using AxCC ID", 822 /* CPRI_CPRSR_MAP_TAB_CFG_0 */ "Container parser mapping table Port 0. Indexed using AxCC_ID.", 823 /* CPRI_CPRSR_MAP_TAB_CFG_1 */ "Container parser mapping table Port 1. Indexed using AxCC ID", 824 /* CPRI_CPRSR_MAP_TAB_CFG_2 */ "Container parser mapping table Port 2. Indexed using AxCC ID", 825 /* CPRI_CPRSR_MAP_TAB_CFG_3 */ "Container parser mapping table Port 3. Indexed using AxCC ID", 826 /* CPRI_CWA_GCW_CFG_TAB_CFG_0 */ "Generic Control Word configuration table entry.", 827 /* CPRI_CWA_GCW_CFG_TAB_CFG_1 */ "Generic Control Word configuration table entry.", 828 /* CPRI_CWA_GCW_CFG_TAB_CFG_2 */ "Generic Control Word configuration table entry.", 829 /* CPRI_CWA_GCW_CFG_TAB_CFG_3 */ "Generic Control Word configuration table entry.", 830 /* CPRI_CWA_GCW_REGS_CFG_0 */ "Generic Control Word configuration table entry.", 831 /* CPRI_CWA_GCW_REGS_CFG_1 */ "Generic Control Word configuration table entry.", 832 /* CPRI_CWA_GCW_REGS_CFG_2 */ "Generic Control Word configuration table entry.", 833 /* CPRI_CWA_GCW_REGS_CFG_3 */ "Generic Control Word configuration table entry.", 834 /* CPRI_CWA_VSD_CTRL_CONFIG_CFG_0 */ "Per flow axc data config table Port 0. Addressed by section number.", 835 /* CPRI_CWA_VSD_CTRL_CONFIG_CFG_1 */ "Per flow axc data config table Port 1. Addressed by section number.", 836 /* CPRI_CWA_VSD_CTRL_CONFIG_CFG_2 */ "Per flow axc data config table Port 2. Addressed by section number.", 837 /* CPRI_CWA_VSD_CTRL_CONFIG_CFG_3 */ "Per flow axc data config table Port 3. Addressed by section number.", 838 /* CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_0 */ "VSD control flow ID mapping table.", 839 /* CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_1 */ "VSD control flow ID mapping table.", 840 /* CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_2 */ "VSD control flow ID mapping table.", 841 /* CPRI_CWA_VSD_CTRL_FLOWID_MAP_TAB_CFG_3 */ "VSD control flow ID mapping table.", 842 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER0_STS_0 */ "Per flow ctrl axc data from decap Port 0. Addressed by section number.", 843 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER0_STS_1 */ "Per flow ctrl axc data from decap Port 1. Addressed by section number.", 844 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER0_STS_2 */ "Per flow ctrl axc data from decap Port 2. Addressed by section number.", 845 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER0_STS_3 */ "Per flow ctrl axc data from decap Port 3. Addressed by section number.", 846 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER1_STS_0 */ "Per flow ctrl axc data from decap Port 0. Addressed by section number.", 847 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER1_STS_1 */ "Per flow ctrl axc data from decap Port 1. Addressed by section number.", 848 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER1_STS_2 */ "Per flow ctrl axc data from decap Port 2. Addressed by section number.", 849 /* CPRI_CWA_VSD_CTRL_FLOW_BUFFER1_STS_3 */ "Per flow ctrl axc data from decap Port 3. Addressed by section number.", 850 /* CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_0 */ "VSD control group assign configuration table.", 851 /* CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_1 */ "VSD control group assign configuration table.", 852 /* CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_2 */ "VSD control group assign configuration table.", 853 /* CPRI_CWA_VSD_CTRL_GRP_ASSIGN_CFG_TAB_CFG_3 */ "VSD control group assign configuration table.", 854 /* CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_0 */ "VSD control group configuration table.", 855 /* CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_1 */ "VSD control group configuration table.", 856 /* CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_2 */ "VSD control group configuration table.", 857 /* CPRI_CWA_VSD_CTRL_GRP_CFG_TAB_CFG_3 */ "VSD control group configuration table.", 858 /* CPRI_CWA_VSD_RAW_LOC_TAB_CFG_0 */ "VSD Raw Stream location configuration table entry.", 859 /* CPRI_CWA_VSD_RAW_LOC_TAB_CFG_1 */ "VSD Raw Stream location configuration table entry.", 860 /* CPRI_CWA_VSD_RAW_LOC_TAB_CFG_2 */ "VSD Raw Stream location configuration table entry.", 861 /* CPRI_CWA_VSD_RAW_LOC_TAB_CFG_3 */ "VSD Raw Stream location configuration table entry.", 862 /* CPRI_CWA_VSD_RAW_MAP_TAB_CFG_0 */ "VSD Raw Stream mapping configuration table entry.", 863 /* CPRI_CWA_VSD_RAW_MAP_TAB_CFG_1 */ "VSD Raw Stream mapping configuration table entry.", 864 /* CPRI_CWA_VSD_RAW_MAP_TAB_CFG_2 */ "VSD Raw Stream mapping configuration table entry.", 865 /* CPRI_CWA_VSD_RAW_MAP_TAB_CFG_3 */ "VSD Raw Stream mapping configuration table entry.", 866 /* CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_0 */ "CPRI DECAP Classification using ROE_VERSION and ROE_PKT_TYPE for PORT-0", 867 /* CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_1 */ "CPRI DECAP Classification using ROE_VERSION and ROE_PKT_TYPE for PORT-1: Uses Incoming RoE Header FLOWID as Index", 868 /* CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_2 */ "CPRI DECAP Classification using ROE_VERSION and ROE_PKT_TYPE for PORT-2: Uses Incoming RoE Header FLOWID as Index", 869 /* CPRI_DECAP_CLS_TO_QUEUE_LOOKUP_3 */ "CPRI DECAP Classification using ROE_VERSION and ROE_PKT_TYPE for PORT-3: Uses Incoming RoE Header FLOWID as Index", 870 /* CPRI_DECAP_COMP_TAB_0 */ "Decap Compression table for both RAMs Used for processing 4 samples at a time used in compression look-up For Port-0. This memory should not be accessed when datapath is active (cip_dp_rst_n==1)", 871 /* CPRI_DECAP_COMP_TAB_1 */ "Decap Compression table for both RAMs Used for processing 4 samples at a time used in compression look-up For Port-1.", 872 /* CPRI_DECAP_COMP_TAB_2 */ "Decap Compression table for both RAMs Used for processing 4 samples at a time used in compression look-up For Port-2.", 873 /* CPRI_DECAP_COMP_TAB_3 */ "Decap Compression table for both RAMs Used for processing 4 samples at a time used in compression look-up For Port-3.", 874 /* CPRI_DECAP_DATA_0 */ "Decap Queue Setup For Port-0, Uses Queue Index", 875 /* CPRI_DECAP_DATA_1 */ "Decap Queue Setup For Port-1, Uses Queue Index", 876 /* CPRI_DECAP_DATA_2 */ "Decap Queue Setup For Port-2, Uses Queue Index", 877 /* CPRI_DECAP_DATA_3 */ "Decap Queue Setup For Port-3, Uses Queue Index", 878 /* CPRI_DECAP_FLOWID_QUE_LOOKUP_0 */ "CPRI Decap DECAP_FLOWID to Queue Lookup Table for Port-0: Uses Flow ID as Index", 879 /* CPRI_DECAP_FLOWID_QUE_LOOKUP_1 */ "CPRI Decap DECAP_FLOWID to Queue Lookup Table for Port-1: Uses Flow ID as Index", 880 /* CPRI_DECAP_FLOWID_QUE_LOOKUP_2 */ "CPRI Decap DECAP_FLOWID to Queue Lookup Table Port-2: Uses Flow ID as Index", 881 /* CPRI_DECAP_FLOWID_QUE_LOOKUP_3 */ "CPRI Decap DECAP_FLOWID to Queue Lookup Table Port-3: Uses Flow ID as Index", 882 /* CPRI_DECAP_FLOW_CONTROL_0 */ "CPRI Decap Flow Control to MMU for Port-0", 883 /* CPRI_DECAP_FLOW_CONTROL_1 */ "CPRI Decap Flow Control to MMU for Port-1", 884 /* CPRI_DECAP_FLOW_CONTROL_2 */ "CPRI Decap Flow Control to MMU for Port-2", 885 /* CPRI_DECAP_FLOW_CONTROL_3 */ "CPRI Decap Flow Control to MMU for Port-3", 886 /* CPRI_DECAP_ORDERING_INFO_TAB_0 */ "CPRI Decap Ordering Table INFO Table for Port-0:Uses Ordering Index LOOKUP as Index to this table", 887 /* CPRI_DECAP_ORDERING_INFO_TAB_1 */ "CPRI Decap Ordering Table INFO Table for Port-1:Uses Ordering Index LOOKUP as Index to this table", 888 /* CPRI_DECAP_ORDERING_INFO_TAB_2 */ "CPRI Decap Ordering Table INFO Table for Port-2:Uses Ordering Index LOOKUP as Index to this table", 889 /* CPRI_DECAP_ORDERING_INFO_TAB_3 */ "CPRI Decap Ordering Table INFO Table for Port-3:Uses Ordering Index LOOKUP as Index to this table", 890 /* CPRI_DECAP_ORDERING_SEQOFF_TAB_0 */ "CPRI Decap Ordering Table SEQOFF Table for Port-0:Uses Ordering Index LOOKUP as Index to this table", 891 /* CPRI_DECAP_ORDERING_SEQOFF_TAB_1 */ "CPRI Decap Ordering Table SEQOFF Table for Port-1:Uses Ordering Index LOOKUP as Index to this table", 892 /* CPRI_DECAP_ORDERING_SEQOFF_TAB_2 */ "CPRI Decap Ordering Table SEQOFF Table for Port-2:Uses Ordering Index LOOKUP as Index to this table", 893 /* CPRI_DECAP_ORDERING_SEQOFF_TAB_3 */ "CPRI Decap Ordering Table SEQOFF Table for Port-3:Uses Ordering Index LOOKUP as Index to this table", 894 /* CPRI_DECAP_QUEUE_STATS_0 */ "Decap Queue Statistics For Port-0, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is read-only memory. This is READONLY memory. SBUS write should not be issued to this memory.", 895 /* CPRI_DECAP_QUEUE_STATS_1 */ "Decap Queue Statistics For Port-1, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is READONLY memory. SBUS write should not be issued to this memory.", 896 /* CPRI_DECAP_QUEUE_STATS_2 */ "Decap Queue Statistics For Port-2, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is READONLY memory. SBUS write should not be issued to this memory.", 897 /* CPRI_DECAP_QUEUE_STATS_3 */ "Decap Queue Statistics For Port-3, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is READONLY memory. SBUS write should not be issued to this memory.", 898 /* CPRI_DECAP_QUEUE_STS_0 */ "Decap Queue Setup For Port-0, Uses Queue Index", 899 /* CPRI_DECAP_QUEUE_STS_1 */ "Decap Queue Setup For Port-0, Uses Queue Index", 900 /* CPRI_DECAP_QUEUE_STS_2 */ "Decap Queue Setup For Port-2, Uses Queue Index", 901 /* CPRI_DECAP_QUEUE_STS_3 */ "Decap Queue Setup For Port-3, Uses Queue Index", 902 /* CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_0 */ "CPRI DECAP QUEUE NUMBER to ORDERING INFO INDEX PORT-0: Uses Queue-NUM as index derived from FLOW-ID to Queue NUM lookup", 903 /* CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_1 */ "CPRI DECAP QUEUE NUMBER to ORDERING INFO INDEX PORT-1: Uses Queue-NUM as index derived from FLOW-ID to Queue NUM lookup", 904 /* CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_2 */ "CPRI DECAP QUEUE NUMBER to ORDERING INFO INDEX PORT-2: Uses Queue-NUM as index derived from FLOW-ID to Queue NUM lookup", 905 /* CPRI_DECAP_QUE_NUM_TO_ORDERING_INDEX_3 */ "CPRI DECAP QUEUE NUMBER to ORDERING INFO INDEX PORT-3: Uses Queue-NUM as index derived from FLOW-ID to Queue NUM lookup", 906 /* CPRI_DECAP_ULAW_LUT_0 */ "Decap uLaw Tabl For Port-0.", 907 /* CPRI_DECAP_ULAW_LUT_1 */ "Decap uLaw Tabl For Port-1.", 908 /* CPRI_DECAP_ULAW_LUT_2 */ "Decap uLaw Tabl For Port-2.", 909 /* CPRI_DECAP_ULAW_LUT_3 */ "Decap uLaw Tabl For Port-3.", 910 /* CPRI_ENCAP_DATA_0 */ "Encap Queue Setup For Port-0, Uses Queue Index", 911 /* CPRI_ENCAP_DATA_1 */ "Encap Queue Setup For Port-1, Uses Queue Index", 912 /* CPRI_ENCAP_DATA_2 */ "Encap Queue Setup For Port-2, Uses Queue Index", 913 /* CPRI_ENCAP_DATA_3 */ "Encap Queue Setup For Port-3, Uses Queue Index", 914 /* CPRI_ENCAP_ORDERING_INFO_STS_0 */ "CPRI Encap Ordering INFO Status, in other words, current seq_number value", 915 /* CPRI_ENCAP_ORDERING_INFO_STS_1 */ "CPRI Encap Ordering INFO Status, in other words, current seq_number value", 916 /* CPRI_ENCAP_ORDERING_INFO_STS_2 */ "CPRI Encap Ordering INFO Status, in other words, current seq_number value", 917 /* CPRI_ENCAP_ORDERING_INFO_STS_3 */ "CPRI Encap Ordering INFO Status, in other words, current seq_number value", 918 /* CPRI_ENCAP_ORDERING_INFO_TAB_0 */ "CPRI Encap Ordering Table INFO Table for Port-0: Uses Ordering Info Index", 919 /* CPRI_ENCAP_ORDERING_INFO_TAB_1 */ "CPRI Encap Ordering Table INFO Table for Port-1: Uses Ordering Info Index", 920 /* CPRI_ENCAP_ORDERING_INFO_TAB_2 */ "CPRI Encap Ordering Table INFO Table for Port-2: Uses Ordering Info Index", 921 /* CPRI_ENCAP_ORDERING_INFO_TAB_3 */ "CPRI Encap Ordering Table INFO Table for Port-3: Uses Ordering Info Index", 922 /* CPRI_ENCAP_QUEUE_STATS_0 */ "Encap Queue Statistics For Port-0, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is READONLY memory. SBUS write should not be issued to this memory.", 923 /* CPRI_ENCAP_QUEUE_STATS_1 */ "Encap Queue Statistics For Port-1, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is READONLY memory. SBUS write should not be issued to this memory.", 924 /* CPRI_ENCAP_QUEUE_STATS_2 */ "Encap Queue Statistics For Port-2, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is READONLY memory. SBUS write should not be issued to this memory.", 925 /* CPRI_ENCAP_QUEUE_STATS_3 */ "Encap Queue Statistics For Port-3, Uses Queue Index, These fields clears on READ. The statistics will saturate at their maximum value. This is READONLY memory. SBUS write should not be issued to this memory.", 926 /* CPRI_ENCAP_QUEUE_STS_0 */ "Encap Queue Setup For Port-0, Uses Queue Index", 927 /* CPRI_ENCAP_QUEUE_STS_1 */ "Encap Queue Setup For Port-0, Uses Queue Index", 928 /* CPRI_ENCAP_QUEUE_STS_2 */ "Encap Queue Setup For Port-2, Uses Queue Index", 929 /* CPRI_ENCAP_QUEUE_STS_3 */ "Encap Queue Setup For Port-3, Uses Queue Index", 930 /* CPRI_ENCAP_QUE_CTL_FLOWID_TAB_0 */ "CPRI Encap Special FLOWID for Control Queues Port-0: Uses SMPROC TAG from RxFramer as Index", 931 /* CPRI_ENCAP_QUE_CTL_FLOWID_TAB_1 */ "CPRI Encap Special FLOWID for Control Queues Port-1: Uses SMPROC TAG from RxFramer as Index", 932 /* CPRI_ENCAP_QUE_CTL_FLOWID_TAB_2 */ "CPRI Encap Special FLOWID for Control Queues Port-2: Uses SMPROC TAG from RxFramer as Index", 933 /* CPRI_ENCAP_QUE_CTL_FLOWID_TAB_3 */ "CPRI Encap Special FLOWID for Control Queues Port-3: Uses SMPROC TAG from RxFramer as Index", 934 /* CPRI_ENCAP_QUE_DA_TAB_0 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-0: Uses DA Index in ETH HDR CFG", 935 /* CPRI_ENCAP_QUE_DA_TAB_1 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-1: Uses DA Index in ETH HDR CFG", 936 /* CPRI_ENCAP_QUE_DA_TAB_2 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-2: Uses DA Index in ETH HDR CFG", 937 /* CPRI_ENCAP_QUE_DA_TAB_3 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-3: Uses DA Index in ETH HDR CFG", 938 /* CPRI_ENCAP_QUE_ETH_HDR_0 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-0: Uses Queue Num as Index", 939 /* CPRI_ENCAP_QUE_ETH_HDR_1 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-1:Uses Queue Num As index", 940 /* CPRI_ENCAP_QUE_ETH_HDR_2 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-2:Uses Queue Num As index", 941 /* CPRI_ENCAP_QUE_ETH_HDR_3 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-3:Uses Queue Num As index", 942 /* CPRI_ENCAP_QUE_SA_TAB_0 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-0: Uses SA Index in ETH HDR CFG", 943 /* CPRI_ENCAP_QUE_SA_TAB_1 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-1: Uses SA Index in ETH HDR CFG", 944 /* CPRI_ENCAP_QUE_SA_TAB_2 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-2", 945 /* CPRI_ENCAP_QUE_SA_TAB_3 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-3: Uses SA Index in ETH HDR CFG", 946 /* CPRI_ENCAP_QUE_VLAN0_TAB_0 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-0:: Uses VLAN Index in ETH HDR CFG", 947 /* CPRI_ENCAP_QUE_VLAN0_TAB_1 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-1:Uses VLAN Index in ETH HDR CFG", 948 /* CPRI_ENCAP_QUE_VLAN0_TAB_2 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-2:Uses VLAN Index in ETH HDR CFG", 949 /* CPRI_ENCAP_QUE_VLAN0_TAB_3 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-3:Uses VLAN Index in ETH HDR CFG", 950 /* CPRI_ENCAP_QUE_VLAN1_TAB_0 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-0:Uses VLAN Index in ETH HDR CFG", 951 /* CPRI_ENCAP_QUE_VLAN1_TAB_1 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-1:Uses VLAN Index in ETH HDR CFG", 952 /* CPRI_ENCAP_QUE_VLAN1_TAB_2 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-2:Uses VLAN Index in ETH HDR CFG", 953 /* CPRI_ENCAP_QUE_VLAN1_TAB_3 */ "CPRI Encap Dest ADDR, Src ADDR and VLAN Lookup for Port-3:Uses VLAN Index in ETH HDR CFG", 954 /* CPRI_GCW_CFG_TAB_CFG_0 */ "Generic Control Word configuration table entry.", 955 /* CPRI_GCW_CFG_TAB_CFG_1 */ "Generic Control Word configuration table entry.", 956 /* CPRI_GCW_CFG_TAB_CFG_2 */ "Generic Control Word configuration table entry.", 957 /* CPRI_GCW_CFG_TAB_CFG_3 */ "Generic Control Word configuration table entry.", 958 /* CPRI_HDR_CMP_TAB_CFG_0 */ "CPRI Header comparison table Port 0. All entries are read simultaneously and the entry with matching data is used.", 959 /* CPRI_HDR_CMP_TAB_CFG_1 */ "CPRI Header comparison table Port 1. All entries are read simultaneously and the entry with matching data is used.", 960 /* CPRI_HDR_CMP_TAB_CFG_2 */ "CPRI Header comparison table Port 2. All entries are read simultaneously and the entry with matching data is used.", 961 /* CPRI_HDR_CMP_TAB_CFG_3 */ "CPRI Header comparison table Port 3. All entries are read simultaneously and the entry with matching data is used.", 962 /* CPRI_IQU_BUFFER_STS_0 */ "IQ unpacking buffer payload table Port 0. Addressed by AxC ID.", 963 /* CPRI_IQU_BUFFER_STS_1 */ "IQ unpacking buffer payload table Port 1. Addressed by AxC ID.", 964 /* CPRI_IQU_BUFFER_STS_2 */ "IQ unpacking buffer payload table Port 2. Addressed by AxC ID.", 965 /* CPRI_IQU_BUFFER_STS_3 */ "IQ unpacking buffer payload table Port 3. Addressed by AxC ID.", 966 /* CPRI_IQU_STATE_STS_0 */ "IQ unpacking buffer state table Port 0. Addressed by AxC ID.", 967 /* CPRI_IQU_STATE_STS_1 */ "IQ unpacking buffer state table Port 1. Addressed by AxC ID.", 968 /* CPRI_IQU_STATE_STS_2 */ "IQ unpacking buffer state table Port 2. Addressed by AxC ID.", 969 /* CPRI_IQU_STATE_STS_3 */ "IQ unpacking buffer state table Port 3. Addressed by AxC ID.", 970 /* CPRI_IQ_PK_BUFF_AXC_PLD_STS_0 */ "IQ packing buffer payload table Port 0. Indexed using AxC ID", 971 /* CPRI_IQ_PK_BUFF_AXC_PLD_STS_1 */ "IQ packing buffer payload table Port 1. Indexed using AxC ID", 972 /* CPRI_IQ_PK_BUFF_AXC_PLD_STS_2 */ "IQ packing buffer payload table Port 2. Indexed using AxC ID", 973 /* CPRI_IQ_PK_BUFF_AXC_PLD_STS_3 */ "IQ packing buffer payload table Port 3. Indexed using AxC ID", 974 /* CPRI_IQ_PK_BUFF_AXC_STATE_STS_0 */ "IQ packing buffer state table Port 0. Indexed using AxC ID", 975 /* CPRI_IQ_PK_BUFF_AXC_STATE_STS_1 */ "IQ packing buffer state table Port 1. Indexed using AxC ID", 976 /* CPRI_IQ_PK_BUFF_AXC_STATE_STS_2 */ "IQ packing buffer state table Port 2. Indexed using AxC ID", 977 /* CPRI_IQ_PK_BUFF_AXC_STATE_STS_3 */ "IQ packing buffer state table Port 3. Indexed using AxC ID", 978 /* CPRI_VSDCTRL_CFLW_BUF_TAB_STS_0 */ "Control flow buffer memory Port 0. Indexed using section number.", 979 /* CPRI_VSDCTRL_CFLW_BUF_TAB_STS_1 */ "Control flow buffer memory Port 1. Indexed using section number.", 980 /* CPRI_VSDCTRL_CFLW_BUF_TAB_STS_2 */ "Control flow buffer memory Port 2. Indexed using section number.", 981 /* CPRI_VSDCTRL_CFLW_BUF_TAB_STS_3 */ "Control flow buffer memory Port 3. Indexed using section number.", 982 /* CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_0 */ "Control flow packet generation config memory Port 0. Indexed using section number.", 983 /* CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_1 */ "Control flow packet generation config memory Port 1. Indexed using section number.", 984 /* CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_2 */ "Control flow packet generation config memory Port 2", 985 /* CPRI_VSDCTRL_CFLW_PGC_TAB_CFG_3 */ "Control flow packet generation config memory Port 3", 986 /* CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_0 */ "Group to sector assignment config table. Indexed by address from the GRP_CFG_TAB and offset from the vacate FSM.", 987 /* CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_1 */ "Group to sector assignment config table. Indexed by address from the GRP_CFG_TAB and offset from the vacate FSM.", 988 /* CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_2 */ "Group to sector assignment config table. Indexed by address from the GRP_CFG_TAB and offset from the vacate FSM.", 989 /* CPRI_VSDCTRL_GRP_ASSIGN_TAB_CFG_3 */ "Group to sector assignment config table. Indexed by address from the GRP_CFG_TAB and offset from the vacate FSM.", 990 /* CPRI_VSDCTRL_GRP_CFG_TAB_CFG_0 */ "Indicates the base group pointer and the flow_id. Indexed by group_id.", 991 /* CPRI_VSDCTRL_GRP_CFG_TAB_CFG_1 */ "Indicates the base group pointer and the flow_id. Indexed by group_id.", 992 /* CPRI_VSDCTRL_GRP_CFG_TAB_CFG_2 */ "Indicates the base group pointer and the flow_id. Indexed by group_id.", 993 /* CPRI_VSDCTRL_GRP_CFG_TAB_CFG_3 */ "Indicates the base group pointer and the flow_id. Indexed by group_id.", 994 /* CPRI_VSDCTRL_GRP_STT_TAB_STS_0 */ "Indicates the number of sections accumulated per group_id. Indexed by group_id.", 995 /* CPRI_VSDCTRL_GRP_STT_TAB_STS_1 */ "Indicates the number of sections accumulated per group_id. Indexed by group_id.", 996 /* CPRI_VSDCTRL_GRP_STT_TAB_STS_2 */ "Indicates the number of sections accumulated per group_id. Indexed by group_id.", 997 /* CPRI_VSDCTRL_GRP_STT_TAB_STS_3 */ "Indicates the number of sections accumulated per group_id. Indexed by group_id.", 998 /* CPRI_VSDCTRL_NUM_SEC_TAB_CFG_0 */ "Indicates the number of sections per group_id. Indexed by group_id.", 999 /* CPRI_VSDCTRL_NUM_SEC_TAB_CFG_1 */ "Indicates the number of sections per group_id. Indexed by group_id.", 1000 /* CPRI_VSDCTRL_NUM_SEC_TAB_CFG_2 */ "Indicates the number of sections per group_id. Indexed by group_id.", 1001 /* CPRI_VSDCTRL_NUM_SEC_TAB_CFG_3 */ "Indicates the number of sections per group_id. Indexed by group_id.", 1002 /* CPRI_VSDRAW_FLT_TAB_CFG_0 */ "VSD Raw Stream filtering configuration table entry.", 1003 /* CPRI_VSDRAW_FLT_TAB_CFG_1 */ "VSD Raw Stream filtering configuration table entry.", 1004 /* CPRI_VSDRAW_FLT_TAB_CFG_2 */ "VSD Raw Stream filtering configuration table entry.", 1005 /* CPRI_VSDRAW_FLT_TAB_CFG_3 */ "VSD Raw Stream filtering configuration table entry.", 1006 /* CPRI_VSDRAW_LOC_TAB_CFG_0 */ "VSD Raw Stream location configuration table entry.", 1007 /* CPRI_VSDRAW_LOC_TAB_CFG_1 */ "VSD Raw Stream location configuration table entry.", 1008 /* CPRI_VSDRAW_LOC_TAB_CFG_2 */ "VSD Raw Stream location configuration table entry.", 1009 /* CPRI_VSDRAW_LOC_TAB_CFG_3 */ "VSD Raw Stream location configuration table entry.", 1010 /* CPRI_VSDRAW_STATE_TAB_STS_0 */ "VSD Raw Stream extraction state table entry.", 1011 /* CPRI_VSDRAW_STATE_TAB_STS_1 */ "VSD Raw Stream extraction state table entry.", 1012 /* CPRI_VSDRAW_STATE_TAB_STS_2 */ "VSD Raw Stream extraction state table entry.", 1013 /* CPRI_VSDRAW_STATE_TAB_STS_3 */ "VSD Raw Stream extraction state table entry.", 1014 /* CPU_COS_MAP */ "index by COPYTO_CPU reasons code and internal priorities", 1015 /* CPU_COS_MAP_DATA_ONLY */ "CPU_COS_MAP Data SRAM for CPU_COS_MAP TCAM", 1016 /* CPU_COS_MAP_ONLY */ "CPU_COS_MAP TCAM only view", 1017 /* CPU_PBM */ "Specifies the port(s) that is (are) CPU.", 1018 /* CPU_PBM_2 */ "Specifies the port(s) that is (are) CPU.", 1019 /* CPU_TS_MAP */ "vlan range match table", 1020 /* CRPS_CRPS_0_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 32k counters pairs of Crps0. Each entry in the memory holds 2 counters: packets and bytes (octets).\n Accroding to the congiration in Crps0CountMode each entry may behave as a single wide counter.", 1021 /* CRPS_CRPS_0_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps0CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg0).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1022 /* CRPS_CRPS_0_PRE_READ_MEM */ "INTERNAL", 1023 /* CRPS_CRPS_0_TO_3_PRE_READ_MEM */ "INTERNAL", 1024 /* CRPS_CRPS_10_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps10. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps10CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1025 /* CRPS_CRPS_10_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps10CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg10).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1026 /* CRPS_CRPS_10_PRE_READ_MEM */ "INTERNAL", 1027 /* CRPS_CRPS_11_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps11. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps11CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1028 /* CRPS_CRPS_11_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps1CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg11).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1029 /* CRPS_CRPS_11_PRE_READ_MEM */ "INTERNAL", 1030 /* CRPS_CRPS_12_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps12. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps12CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1031 /* CRPS_CRPS_12_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps12CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg12).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1032 /* CRPS_CRPS_12_PRE_READ_MEM */ "INTERNAL", 1033 /* CRPS_CRPS_12_TO_16_PRE_READ_MEM */ "INTERNAL", 1034 /* CRPS_CRPS_12_TO_17_PRE_READ_MEM */ "INTERNAL", 1035 /* CRPS_CRPS_13_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps13. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps13CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1036 /* CRPS_CRPS_13_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps13CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg13).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1037 /* CRPS_CRPS_13_PRE_READ_MEM */ "INTERNAL", 1038 /* CRPS_CRPS_14_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps14. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps14CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1039 /* CRPS_CRPS_14_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps14CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg14).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1040 /* CRPS_CRPS_14_PRE_READ_MEM */ "INTERNAL", 1041 /* CRPS_CRPS_15_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps15. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps15CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1042 /* CRPS_CRPS_15_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps15CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg15).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1043 /* CRPS_CRPS_15_PRE_READ_MEM */ "INTERNAL", 1044 /* CRPS_CRPS_16_CNTS_MEM */ "CounterProcessor TM - counters memory.\n This memory holds all 4k counters pairs of CrpsTM0. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps16CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1045 /* CRPS_CRPS_16_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in CrpsTm0CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg16).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1046 /* CRPS_CRPS_16_PRE_READ_MEM */ "INTERNAL", 1047 /* CRPS_CRPS_17_CNTS_MEM */ "CounterProcessor TM - counters memory.\n This memory holds all 4k counters pairs of CrpsTM1. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps17CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1048 /* CRPS_CRPS_17_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in CrpsTm1CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg17).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1049 /* CRPS_CRPS_17_PRE_READ_MEM */ "INTERNAL", 1050 /* CRPS_CRPS_1_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 32k counters pairs of Crps1. Each entry in the memory holds 2 counters: packets and bytes (octets).\n Accroding to the congiration in Crps1CountMode each entry may behave as a single wide counter.", 1051 /* CRPS_CRPS_1_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps1CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg1).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1052 /* CRPS_CRPS_1_PRE_READ_MEM */ "INTERNAL", 1053 /* CRPS_CRPS_2_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 32k counters pairs of Crps2. Each entry in the memory holds 2 counters: packets and bytes (octets).\n Accroding to the congiration in Crps2CountMode each entry may behave as a single wide counter.", 1054 /* CRPS_CRPS_2_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps2CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg2).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1055 /* CRPS_CRPS_2_PRE_READ_MEM */ "INTERNAL", 1056 /* CRPS_CRPS_3_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 32k counters pairs of Crps3. Each entry in the memory holds 2 counters: packets and bytes (octets).\n Accroding to the congiration in Crps3CountMode each entry may behave as a single wide counter.", 1057 /* CRPS_CRPS_3_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps3CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg3).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1058 /* CRPS_CRPS_3_PRE_READ_MEM */ "INTERNAL", 1059 /* CRPS_CRPS_4_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps4. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps4CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1060 /* CRPS_CRPS_4_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps4CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg4).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1061 /* CRPS_CRPS_4_PRE_READ_MEM */ "INTERNAL", 1062 /* CRPS_CRPS_4_TO_7_PRE_READ_MEM */ "INTERNAL", 1063 /* CRPS_CRPS_5_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps5. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps5CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1064 /* CRPS_CRPS_5_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps5CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg5).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1065 /* CRPS_CRPS_5_PRE_READ_MEM */ "INTERNAL", 1066 /* CRPS_CRPS_6_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps6. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps6CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1067 /* CRPS_CRPS_6_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps6CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg6).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1068 /* CRPS_CRPS_6_PRE_READ_MEM */ "INTERNAL", 1069 /* CRPS_CRPS_7_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps7. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps7CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1070 /* CRPS_CRPS_7_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps7CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg7).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1071 /* CRPS_CRPS_7_PRE_READ_MEM */ "INTERNAL", 1072 /* CRPS_CRPS_8_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps8. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps8CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1073 /* CRPS_CRPS_8_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps1CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg8).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1074 /* CRPS_CRPS_8_PRE_READ_MEM */ "INTERNAL", 1075 /* CRPS_CRPS_8_TO_11_PRE_READ_MEM */ "INTERNAL", 1076 /* CRPS_CRPS_9_CNTS_MEM */ "CounterProcessor - counters memory.\n This memory holds all 16k counters pairs of Crps9. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps9CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1077 /* CRPS_CRPS_9_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n This memory holds an indication per each entry in Crps9CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg9).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1078 /* CRPS_CRPS_9_PRE_READ_MEM */ "INTERNAL", 1079 /* CRPS_CRPS_CNTS_MEM */ "CounterProcessor - counters memory.\n Each memory holds all 16k counters pairs of Crps0-16. Each entry in the memory holds 2 counters: packets and bytes (octets) as described below, or 2 counters of 32 bits each according to configuration in Crps0-16CountMode\n Accroding to CrpsCntSrcMode each entry may behave as a single wide counter.", 1080 /* CRPS_CRPS_DMA_PRE_READ_MEM */ "INTERNAL", 1081 /* CRPS_CRPS_EXPANSION_MAP_A_MEM */ "INTERNAL", 1082 /* CRPS_CRPS_EXPANSION_MAP_B_MEM */ "INTERNAL", 1083 /* CRPS_CRPS_EXPANSION_MAP_C_MEM */ "INTERNAL", 1084 /* CRPS_CRPS_OVTH_MEM */ "CounterProcessor - over the threshold memory.\n Each memory holds an indication per each entry in Crps0-16CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg0-16).\n This memory is used by the scanner module to search counters that are over the threshold and should be read first (LR(T)).", 1085 /* CRPS_CRPS_OVTH_MEM_A */ "CounterProcessor - over the threshold memory. Each memory holds an indication per each entry in Crps0-7 CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg0-7). This memory is used by the scanner module to search counters that are over the threshold and should be read first.", 1086 /* CRPS_CRPS_OVTH_MEM_B */ "CounterProcessor - over the threshold memory. Each memory holds an indication per each entry in Crps8-15 CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg8-15). This memory is used by the scanner module to search counters that are over the threshold and should be read first.", 1087 /* CRPS_CRPS_OVTH_MEM_C */ "CounterProcessor - over the threshold memory. Each memory holds an indication per each entry in Crps16-21 CntsMem whether one of the counters in the entry's counters pair is over the threshold (thresholds are configured in CrpsThresholdsCfg16-21). This memory is used by the scanner module to search counters that are over the threshold and should be read first.", 1088 /* CRPS_CRPS_PRE_READ_MEM */ "INTERNAL", 1089 /* CRPS_CRPS_TYPE_MAP_MEM */ "CounterProcessor - crps type mapping to address jump", 1090 /* CRPS_EGQ_0_CNTCMD_HDR_CMP_PROFILE_MAPPING_TABLE */ "EGQ0 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port-Profile(4) -> Cntcmd-Header-Compensation", 1091 /* CRPS_EGQ_1_CNTCMD_HDR_CMP_PROFILE_MAPPING_TABLE */ "EGQ1 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port-Profile(4) -> Cntcmd-Header-Compensation", 1092 /* CRPS_EGQ_OFFSET_BMAP */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the Egq multiplied by the group size that is configured in EgqGroupSize.\n The offset is determined differently per each group size.", 1093 /* CRPS_EGQ_TM_CNTCMD_HDR_CMP_PROFILE_MAPPING_TABLE */ "EGQ-TM Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port-Profile(4) -> Cntcmd-Header-Compensation", 1094 /* CRPS_EPNI_0_CNTCMD_HDR_CMP_PROFILE_MAPPING_TABLE */ "EPNI0 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port-Profile(4) -> Cntcmd-Header-Compensation", 1095 /* CRPS_EPNI_1_CNTCMD_HDR_CMP_PROFILE_MAPPING_TABLE */ "EPNI1 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port-Profile(4) -> Cntcmd-Header-Compensation", 1096 /* CRPS_EPNI_OFFSET_BMAP_A */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the EpniA multiplied by the group size that is configured in EpniAGroupSize.\n The offset is determined differently per each group size.", 1097 /* CRPS_EPNI_OFFSET_BMAP_B */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the EpniB multiplied by the group size that is configured in EpniBGroupSize.\n The offset is determined differently per each group size.", 1098 /* CRPS_HEADER_APPEND_PTR_TO_EGQ_0_CNTCMD_HDR_CMP_MAPPING_TABLE */ "EGQ0 Header-Compensation calculation, to be added to incoming packet size:\n Header-Append-Ptr -> Header-Append-Ptr-Compensation", 1099 /* CRPS_HEADER_APPEND_PTR_TO_EGQ_1_CNTCMD_HDR_CMP_MAPPING_TABLE */ "EGQ1 Header-Compensation calculation, to be added to incoming packet size:\n Header-Append-Ptr -> Header-Append-Ptr-Compensation", 1100 /* CRPS_HEADER_APPEND_PTR_TO_EGQ_TM_CNTCMD_HDR_CMP_MAPPING_TABLE */ "EGQ1 Header-Compensation calculation, to be added to incoming packet size:\n Header-Append-Ptr -> Header-Append-Ptr-Compensation", 1101 /* CRPS_HEADER_APPEND_PTR_TO_EPNI_0_CNTCMD_HDR_CMP_MAPPING_TABLE */ "EPNI0 Header-Compensation calculation, to be added to incoming packet size:\n Header-Append-Ptr -> Header-Append-Ptr-Compensation", 1102 /* CRPS_HEADER_APPEND_PTR_TO_EPNI_1_CNTCMD_HDR_CMP_MAPPING_TABLE */ "EPNI1 Header-Compensation calculation, to be added to incoming packet size:\n Header-Append-Ptr -> Header-Append-Ptr-Compensation", 1103 /* CRPS_IN_PP_PORT_TO_EGQ_0_CNTCMD_HDR_CMP_PROFILE_TABLE */ "EGQ0 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port -> Cntcmd-Hdr-Cmp-Profile table", 1104 /* CRPS_IN_PP_PORT_TO_EGQ_1_CNTCMD_HDR_CMP_PROFILE_TABLE */ "EGQ1 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port -> Cntcmd-Hdr-Cmp-Profile table", 1105 /* CRPS_IN_PP_PORT_TO_EGQ_TM_CNTCMD_HDR_CMP_PROFILE_TABLE */ "EGQ-TM Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port -> Cntcmd-Hdr-Cmp-Profile table", 1106 /* CRPS_IN_PP_PORT_TO_EPNI_0_CNTCMD_HDR_CMP_PROFILE_TABLE */ "EPNI0 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port -> Cntcmd-Hdr-Cmp-Profile table", 1107 /* CRPS_IN_PP_PORT_TO_EPNI_1_CNTCMD_HDR_CMP_PROFILE_TABLE */ "EPNI1 Header-Compensation calculation, to be added to incoming packet size:\n In-PP-Port -> Cntcmd-Hdr-Cmp-Profile table", 1108 /* CRPS_IQM_OFFSET_BMAP_A */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the IqmA multiplied by the group size that is configured in IqmAGroupSize.\n The offset is determined differently per each group size.", 1109 /* CRPS_IQM_OFFSET_BMAP_B */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the IqmB multiplied by the group size that is configured in IqmBGroupSize.\n The offset is determined differently per each group size.", 1110 /* CRPS_IQM_OFFSET_BMAP_C */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the IqmC multiplied by the group size that is configured in IqmCGroupSize.\n The offset is determined differently per each group size.", 1111 /* CRPS_IQM_OFFSET_BMAP_D */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the IqmD multiplied by the group size that is configured in IqmDGroupSize.\n The offset is determined differently per each group size.", 1112 /* CRPS_IRPP_OFFSET_BMAP_A */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the IrppA multiplied by the group size that is configured in IrppAGroupSize.\n The offset is determined differently per each group size.", 1113 /* CRPS_IRPP_OFFSET_BMAP_B */ "Counter Processor - group size offset bitmap configuration - each line is for a Crps group size: 1, 2(REJ), 2(dp), 4, 5.\n This mapping is used to determine the counter pair's offset within the group. The group number is determined by the counter ID given in the interface from the IrppB multiplied by the group size that is configured in IrppBGroupSize.\n The offset is determined differently per each group size.", 1114 /* CRPS_MEM_0080000 */ "INTERNAL", 1115 /* CRPS_MEM_0090000 */ "INTERNAL", 1116 /* CRPS_MEM_0100000 */ "INTERNAL", 1117 /* CRPS_MEM_0110000 */ "INTERNAL", 1118 /* CRPS_MEM_0120000 */ "INTERNAL", 1119 /* CRPS_MEM_0130000 */ "INTERNAL", 1120 /* CRPS_MEM_0140000 */ "INTERNAL", 1121 /* CRPS_MEM_00A0000 */ "INTERNAL", 1122 /* CRPS_MEM_00B0000 */ "INTERNAL", 1123 /* CRPS_MEM_00C0000 */ "INTERNAL", 1124 /* CRPS_MEM_00D0000 */ "INTERNAL", 1125 /* CRPS_MEM_00E0000 */ "INTERNAL", 1126 /* CRPS_MEM_00F0000 */ "INTERNAL", 1127 /* CTRL_PKT_SIGNATURE_1 */ "Source Virtual Port Properties required earlier in processing", 1128 /* CTRL_PKT_SIGNATURE_2 */ "Source Virtual Port Properties required earlier in processing", 1129 /* CTRL_PKT_SIGNATURE_3 */ "Source Virtual Port Properties required earlier in processing", 1130 /* CTRL_PKT_SIGNATURE_4 */ "Source Virtual Port Properties required earlier in processing", 1131 /* CTR_DEQ_STATUS_MEM */ "", 1132 /* CTR_FLEX_COUNT_0 */ "", 1133 /* CTR_FLEX_COUNT_1 */ "", 1134 /* CTR_FLEX_COUNT_2 */ "", 1135 /* CTR_FLEX_COUNT_3 */ "", 1136 /* CTR_FLEX_COUNT_4 */ "", 1137 /* CTR_FLEX_COUNT_5 */ "", 1138 /* CTR_FLEX_COUNT_6 */ "", 1139 /* CTR_FLEX_COUNT_7 */ "", 1140 /* CTR_FLEX_COUNT_8 */ "", 1141 /* CTR_FLEX_COUNT_9 */ "", 1142 /* CTR_FLEX_COUNT_10 */ "", 1143 /* CTR_FLEX_COUNT_11 */ "", 1144 /* CTR_MEM */ "Counter Memory - refer to CTR spec for addresses of different counters", 1145 /* CUSTOM_HEADER_MATCH */ "TCAM FOR CUSTOM HEADER", 1146 /* CUSTOM_HEADER_POLICY_TABLE */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE VFP", 1147 /* CUT_THROUGH_ATTRIBUTE */ "Cut-Through attribution table: Indexed by {Priority (1bit), Flow_id/Circuit_id (12 bits)}", 1148 /* CXXPORT_WC_UCMEM_DATA0 */ "Warpcore External Memory Interface to program micro-controller memory of TSC_4_E_0", 1149 /* CXXPORT_WC_UCMEM_DATA1 */ "Warpcore External Memory Interface to program micro-controller memory of TSC_4_E_1", 1150 /* CXXPORT_WC_UCMEM_DATA2 */ "Warpcore External Memory Interface to program micro-controller memory of TSC_4_E_2", 1151 /* CXX_CXXPORT_WC_UCMEM_DATA_0 */ "", 1152 /* CXX_CXXPORT_WC_UCMEM_DATA_1 */ "", 1153 /* CXX_CXXPORT_WC_UCMEM_DATA_2 */ "", 1154 /* DCH_DDP_REPLY_FIFO_P */ "", 1155 /* DCH_DDP_TAG_FIFO_P */ "", 1156 /* DCH_IFMAA_H */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1157 /* DCH_IFMAA_L */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1158 /* DCH_IFMAB_H */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1159 /* DCH_IFMAB_L */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1160 /* DCH_IFMBA_H */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1161 /* DCH_IFMBA_L */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1162 /* DCH_IFMBB_H */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1163 /* DCH_IFMBB_L */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1164 /* DCH_IFMCA_H */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1165 /* DCH_IFMCA_L */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1166 /* DCH_IFMCB_H */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1167 /* DCH_IFMCB_L */ "ifm(a/b/c)(a/b)_(h/l): (a/b/c): links (0-7/8-15/16-23) (a/b): inner mac link indexes (0-3/4-7) (h/l): memory high/low", 1168 /* DCH_ITMAA_P */ "", 1169 /* DCH_ITMAB_P */ "", 1170 /* DCH_ITMBA_P */ "", 1171 /* DCH_ITMBB_P */ "", 1172 /* DCH_ITMCA_P */ "", 1173 /* DCH_ITMCB_P */ "", 1174 /* DCH_ITMD_P */ "", 1175 /* DCH_ITM_0_P */ "", 1176 /* DCH_ITM_1_P */ "", 1177 /* DCH_ITM_2_P */ "", 1178 /* DCH_ITM_3_P */ "", 1179 /* DCH_ITM_4_P */ "", 1180 /* DCH_ITM_5_P */ "", 1181 /* DCH_MEM_400000 */ "INTERNAL", 1182 /* DCH_MEM_00500000 */ "INTERNAL", 1183 /* DCH_MEM_00600000 */ "INTERNAL", 1184 /* DCH_MEM_00700000 */ "INTERNAL", 1185 /* DCH_MEM_00800000 */ "INTERNAL", 1186 /* DCH_MEM_00900000 */ "INTERNAL", 1187 /* DCH_MEM_01000000 */ "INTERNAL", 1188 /* DCH_MEM_01100000 */ "INTERNAL", 1189 /* DCH_MEM_00A00000 */ "INTERNAL", 1190 /* DCH_MEM_00B00000 */ "INTERNAL", 1191 /* DCH_MEM_00C00000 */ "INTERNAL", 1192 /* DCH_MEM_00D00000 */ "INTERNAL", 1193 /* DCH_MEM_00E00000 */ "INTERNAL", 1194 /* DCH_MEM_00F00000 */ "INTERNAL", 1195 /* DCL_CHF */ "", 1196 /* DCL_CLF */ "", 1197 /* DCL_CPU_H */ "cpu fifo high memory.\n For reading a cpu cell from fifo read first address of this memory. Fifo pop is then done internally. Two sbus reads from the same address are needed for reading an entry, since memory is wide.", 1198 /* DCL_CPU_L */ "cpu fifo low memory.\n Reading from this memory is done by reading cpu_h first memory address.", 1199 /* DCL_MEM_01200000 */ "INTERNAL", 1200 /* DCL_MEM_01300000 */ "INTERNAL", 1201 /* DCL_MEM_01400000 */ "INTERNAL", 1202 /* DCL_MEM_01500000 */ "INTERNAL", 1203 /* DCL_MEM_01600000 */ "INTERNAL", 1204 /* DCL_MEM_01700000 */ "INTERNAL", 1205 /* DCL_MEM_01800000 */ "INTERNAL", 1206 /* DCL_MEM_01900000 */ "INTERNAL", 1207 /* DCL_MEM_02000000 */ "INTERNAL", 1208 /* DCL_MEM_02100000 */ "INTERNAL", 1209 /* DCL_MEM_02200000 */ "INTERNAL", 1210 /* DCL_MEM_01A00000 */ "INTERNAL", 1211 /* DCL_MEM_01B00000 */ "INTERNAL", 1212 /* DCL_MEM_01C00000 */ "INTERNAL", 1213 /* DCL_MEM_01D00000 */ "INTERNAL", 1214 /* DCL_MEM_01E00000 */ "INTERNAL", 1215 /* DCL_MEM_01F00000 */ "INTERNAL", 1216 /* DCML_AUTO_DOC_NAME_50 */ "INTERNAL", 1217 /* DCML_AUTO_DOC_NAME_51 */ "INTERNAL", 1218 /* DCML_AUTO_DOC_NAME_52 */ "INTERNAL", 1219 /* DCML_AUTO_DOC_NAME_53 */ "INTERNAL", 1220 /* DCML_AUTO_DOC_NAME_54 */ "INTERNAL", 1221 /* DCML_AUTO_DOC_NAME_55 */ "INTERNAL", 1222 /* DCML_CDM_FIFOS_MEM */ "25 fifos (24 dest. + 1 Gsync) x 36 entries X 122 bit per entry", 1223 /* DCM_MEM_01000000 */ "INTERNAL", 1224 /* DCM_MEM_01100000 */ "INTERNAL", 1225 /* DCM_MEM_01200000 */ "INTERNAL", 1226 /* DCM_MEM_01300000 */ "INTERNAL", 1227 /* DCM_MEM_00D00000 */ "INTERNAL", 1228 /* DCM_MEM_00E00000 */ "INTERNAL", 1229 /* DCM_MEM_00F00000 */ "INTERNAL", 1230 /* DCM_MEM_C00000 */ "INTERNAL", 1231 /* DCM_MTMA_P */ "", 1232 /* DCM_MTMB_P */ "", 1233 /* DCM_MTMC_P */ "", 1234 /* DCM_MTMD_P */ "", 1235 /* DDHA_MACRO_0_ABK_BANK_A */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks0,2,4,6\n AbkBank1 -> PhysicalEntryBanks8,10,12,14", 1236 /* DDHA_MACRO_0_ABK_BANK_B */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks1,3,5,7\n AbkBank1 -> PhysicalEntryBanks9,11,13,15", 1237 /* DDHA_MACRO_0_ENTRY_BANK */ "Interface for accessing PhysicalEntryBanks memories\n EntryBank0 -> PhysicalEntryBanks0..3\n EntryBank1 -> PhysicalEntryBanks4..7", 1238 /* DDHA_MACRO_0_PHYSICAL_ABK_BANK */ "", 1239 /* DDHA_MACRO_0_PHYSICAL_ENTRY_BANK */ "", 1240 /* DDHA_MACRO_1_ABK_BANK_A */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks0,2,4,6\n AbkBank1 -> PhysicalEntryBanks8,10,12,14", 1241 /* DDHA_MACRO_1_ABK_BANK_B */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks1,3,5,7\n AbkBank1 -> PhysicalEntryBanks9,11,13,15", 1242 /* DDHA_MACRO_1_ENTRY_BANK */ "Interface for accessing PhysicalEntryBanks memories\n EntryBank0 -> PhysicalEntryBanks0..3\n EntryBank1 -> PhysicalEntryBanks4..7", 1243 /* DDHA_MACRO_1_PHYSICAL_ABK_BANK */ "", 1244 /* DDHA_MACRO_1_PHYSICAL_ENTRY_BANK */ "", 1245 /* DDHA_MEM_1800000 */ "INTERNAL", 1246 /* DDHA_MEM_3800000 */ "INTERNAL", 1247 /* DDHB_MACRO_0_ABK_BANK_A */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks0,2,4,6\n AbkBank1 -> PhysicalEntryBanks8,10,12,14", 1248 /* DDHB_MACRO_0_ABK_BANK_B */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks1,3,5,7\n AbkBank1 -> PhysicalEntryBanks9,11,13,15", 1249 /* DDHB_MACRO_0_ENTRY_BANK */ "Interface for accessing PhysicalEntryBanks memories\n EntryBank0 -> PhysicalEntryBanks0..3\n EntryBank1 -> PhysicalEntryBanks4..7", 1250 /* DDHB_MACRO_0_PHYSICAL_ABK_BANK */ "", 1251 /* DDHB_MACRO_0_PHYSICAL_ENTRY_BANK */ "", 1252 /* DDHB_MACRO_1_ABK_BANK_A */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks0,2,4,6\n AbkBank1 -> PhysicalEntryBanks8,10,12,14", 1253 /* DDHB_MACRO_1_ABK_BANK_B */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks1,3,5,7\n AbkBank1 -> PhysicalEntryBanks9,11,13,15", 1254 /* DDHB_MACRO_1_ENTRY_BANK */ "Interface for accessing PhysicalEntryBanks memories\n EntryBank0 -> PhysicalEntryBanks0..3\n EntryBank1 -> PhysicalEntryBanks4..7", 1255 /* DDHB_MACRO_1_PHYSICAL_ABK_BANK */ "", 1256 /* DDHB_MACRO_1_PHYSICAL_ENTRY_BANK */ "", 1257 /* DDHB_MEM_2C00000 */ "INTERNAL", 1258 /* DDHB_MEM_C00000 */ "INTERNAL", 1259 /* DDP_BEC_WAIT_FIF */ "FIFO of data waiting for buffer pointers", 1260 /* DDP_BTC_IPT_RXI */ "Tx cmd rxi", 1261 /* DDP_BTC_MMU_RXI_MEM */ "Btc mmu rxi memory", 1262 /* DDP_DBDF */ "Dequeue Bundle Descriptor FIFO", 1263 /* DDP_DBLF */ "Dequeue Buffer List FIFO", 1264 /* DDP_FBC */ "Free Buffer Cache", 1265 /* DDP_ITE_DRAM_PEF */ "Packet Edit FIFO", 1266 /* DDP_ITE_DRAM_WDF */ "Word Data FIFO", 1267 /* DDP_MAX_LATENCY */ "The MLM measures latency from the packet OAM-TS extension.\n In this memory the 8 maximal latency's are kept, with the pointer associated with them", 1268 /* DDP_PKP_RX_CFIF */ "Packet Packing RXI Control FIFO", 1269 /* DDP_PKP_RX_DFIF */ "Packet Packing RXI Data FIFO,\n store up to 2 Jambo (20kB) + 100 cycles = 260", 1270 /* DDP_PKUP_RX_DFIF */ "Packet Un-Packing RXI Data FIFO", 1271 /* DEBUG_CAPTURE */ "Isw2 debug capture buffer", 1272 /* DEST_MOD_PROXY_TABLE */ "DEST MODID table for WLAN proxy status .", 1273 /* DEST_TRUNK_BITMAP */ "Destination Trunk Bitmap Table.", 1274 /* DEVICE_LOOPBACK_PORTS_BITMAP */ "Defines set of device loopback ports.", 1275 /* DEVICE_STREAM_ID_TO_PP_PORT_MAP */ "Port Table, FeatureSpecific-Ethernet.", 1276 /* DHC_MACRO_ABK_BANK_A */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks0,2,4,6\n AbkBank1 -> PhysicalEntryBanks8,10,12,14", 1277 /* DHC_MACRO_ABK_BANK_B */ "Interface for accessing PhysicalAbkBanks memories\n AbkBank0 -> PhysicalEntryBanks1,3,5,7\n AbkBank1 -> PhysicalEntryBanks9,11,13,15", 1278 /* DHC_MACRO_ENTRY_BANK */ "Interface for accessing PhysicalEntryBanks memories\n EntryBank0 -> PhysicalEntryBanks0..3\n EntryBank1 -> PhysicalEntryBanks4..7", 1279 /* DHC_MACRO_PHYSICAL_ABK_BANK */ "", 1280 /* DHC_MACRO_PHYSICAL_ENTRY_BANK */ "", 1281 /* DHC_MEM_1800000 */ "INTERNAL", 1282 /* DLB_ECMP_EEM_CONFIGURATION */ "EtherType eligibility configuration", 1283 /* DLB_ECMP_ETHERTYPE_ELIGIBILITY_MAP */ "Ethernet Type Eligiblity table", 1284 /* DLB_ECMP_FINAL_MEMBERS_QUALITY_MEASURE */ "Final Member Quality Measure.", 1285 /* DLB_ECMP_FINAL_MEMBERS_QUALITY_MEASURE_PIPE0 */ "Final Member Quality Measure.", 1286 /* DLB_ECMP_FINAL_MEMBERS_QUALITY_MEASURE_PIPE1 */ "Final Member Quality Measure.", 1287 /* DLB_ECMP_FINAL_MEMBERS_QUALITY_MEASURE_PIPE2 */ "Final Member Quality Measure.", 1288 /* DLB_ECMP_FINAL_MEMBERS_QUALITY_MEASURE_PIPE3 */ "Final Member Quality Measure.", 1289 /* DLB_ECMP_FLOWSET */ "DLB_ECMP Flow Set Timestamp and Member Information. This table is indexed by a hash of the packet flow. CPU access is for debug purpose only.", 1290 /* DLB_ECMP_FLOWSET_MEMBER */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1291 /* DLB_ECMP_FLOWSET_MEMBER_PIPE0 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1292 /* DLB_ECMP_FLOWSET_MEMBER_PIPE1 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1293 /* DLB_ECMP_FLOWSET_MEMBER_PIPE2 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1294 /* DLB_ECMP_FLOWSET_MEMBER_PIPE3 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1295 /* DLB_ECMP_FLOWSET_MEMBER_PIPE4 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1296 /* DLB_ECMP_FLOWSET_MEMBER_PIPE5 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1297 /* DLB_ECMP_FLOWSET_MEMBER_PIPE6 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1298 /* DLB_ECMP_FLOWSET_MEMBER_PIPE7 */ "DLB_ECMP Flow Set Assigned ECMP Member.", 1299 /* DLB_ECMP_FLOWSET_PIPE0 */ "DLB_ECMP Flow Set Assigned Port Member.", 1300 /* DLB_ECMP_FLOWSET_PIPE1 */ "DLB_ECMP Flow Set Assigned Port Member.", 1301 /* DLB_ECMP_FLOWSET_PIPE2 */ "DLB_ECMP Flow Set Assigned Port Member.", 1302 /* DLB_ECMP_FLOWSET_PIPE3 */ "DLB_ECMP Flow Set Assigned Port Member.", 1303 /* DLB_ECMP_FLOWSET_PIPE4 */ "DLB_ECMP Flow Set Assigned Port Member.", 1304 /* DLB_ECMP_FLOWSET_PIPE5 */ "DLB_ECMP Flow Set Assigned Port Member.", 1305 /* DLB_ECMP_FLOWSET_PIPE6 */ "DLB_ECMP Flow Set Assigned Port Member.", 1306 /* DLB_ECMP_FLOWSET_PIPE7 */ "DLB_ECMP Flow Set Assigned Port Member.", 1307 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE */ "DLB_ECMP Flow Set Page. This table is indexed by a hash of the packet flow. CPU access is for debug purpose only.", 1308 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE0 */ "DLB_ECMP Flow Set Page-Number table.", 1309 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE1 */ "DLB_ECMP Flow Set Page-Number table.", 1310 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE2 */ "DLB_ECMP Flow Set Page-Number table.", 1311 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE3 */ "DLB_ECMP Flow Set Page-Number table.", 1312 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE4 */ "DLB_ECMP Flow Set Page-Number table.", 1313 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE5 */ "DLB_ECMP Flow Set Page-Number table.", 1314 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE6 */ "DLB_ECMP Flow Set Page-Number table.", 1315 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PIPE7 */ "DLB_ECMP Flow Set Page-Number table.", 1316 /* DLB_ECMP_GLB_QUANTIZE_THRESHOLD */ "DLB_ECMP Quantization Thresholds table.", 1317 /* DLB_ECMP_GROUP_ALT_NHI_MEMBERS_0_TO_12 */ "ECMP DLB Member next hop index", 1318 /* DLB_ECMP_GROUP_ALT_NHI_MEMBERS_13_TO_25 */ "ECMP DLB Member next hop index", 1319 /* DLB_ECMP_GROUP_ALT_NHI_MEMBERS_26_TO_38 */ "ECMP DLB Member next hop index", 1320 /* DLB_ECMP_GROUP_ALT_NHI_MEMBERS_39_TO_51 */ "ECMP DLB Member next hop index", 1321 /* DLB_ECMP_GROUP_ALT_NHI_MEMBERS_52_TO_63 */ "ECMP DLB Member next hop index", 1322 /* DLB_ECMP_GROUP_ALT_PORT_MEMBERS_0_TO_15 */ "ECMP DLB Member Egress port", 1323 /* DLB_ECMP_GROUP_ALT_PORT_MEMBERS_16_TO_31 */ "ECMP DLB Member Egress port", 1324 /* DLB_ECMP_GROUP_ALT_PORT_MEMBERS_32_TO_47 */ "ECMP DLB Member Egress port", 1325 /* DLB_ECMP_GROUP_ALT_PORT_MEMBERS_48_TO_63 */ "ECMP DLB Member Egress port", 1326 /* DLB_ECMP_GROUP_CONTROL */ "ECMP DLB Group Control configuration. Indexed by L3_ECMP_GROUP.DLB_ID.", 1327 /* DLB_ECMP_GROUP_MEMBERSHIP */ "DLB_ECMP Group Membership for each group. Indexed by L3_ECMP_GROUP.DLB_ID.", 1328 /* DLB_ECMP_GROUP_MONITOR_CONTROL */ "Link Status Control.", 1329 /* DLB_ECMP_GROUP_NHI_MEMBERS_0_TO_12 */ "ECMP DLB Member next hop index", 1330 /* DLB_ECMP_GROUP_NHI_MEMBERS_13_TO_25 */ "ECMP DLB Member next hop index", 1331 /* DLB_ECMP_GROUP_NHI_MEMBERS_26_TO_38 */ "ECMP DLB Member next hop index", 1332 /* DLB_ECMP_GROUP_NHI_MEMBERS_39_TO_51 */ "ECMP DLB Member next hop index", 1333 /* DLB_ECMP_GROUP_NHI_MEMBERS_52_TO_63 */ "ECMP DLB Member next hop index", 1334 /* DLB_ECMP_GROUP_PORT_MEMBERS_0_TO_15 */ "ECMP DLB Member Egress port", 1335 /* DLB_ECMP_GROUP_PORT_MEMBERS_16_TO_31 */ "ECMP DLB Member Egress port", 1336 /* DLB_ECMP_GROUP_PORT_MEMBERS_32_TO_47 */ "ECMP DLB Member Egress port", 1337 /* DLB_ECMP_GROUP_PORT_MEMBERS_48_TO_63 */ "ECMP DLB Member Egress port", 1338 /* DLB_ECMP_GROUP_PORT_TO_MEMBER */ "Member Hardware Link Status", 1339 /* DLB_ECMP_GROUP_STATS */ "DLB_ECMP Statistics for each group.", 1340 /* DLB_ECMP_GROUP_STATS_PIPE0 */ "DLB_ECMP Group Member Statistic.", 1341 /* DLB_ECMP_GROUP_STATS_PIPE1 */ "DLB_ECMP Group Member Statistic.", 1342 /* DLB_ECMP_GROUP_STATS_PIPE2 */ "DLB_ECMP Group Member Statistic.", 1343 /* DLB_ECMP_GROUP_STATS_PIPE3 */ "DLB_ECMP Group Member Statistic.", 1344 /* DLB_ECMP_GROUP_STATS_PIPE4 */ "DLB_ECMP Group Member Statistic.", 1345 /* DLB_ECMP_GROUP_STATS_PIPE5 */ "DLB_ECMP Group Member Statistic.", 1346 /* DLB_ECMP_GROUP_STATS_PIPE6 */ "DLB_ECMP Group Member Statistic.", 1347 /* DLB_ECMP_GROUP_STATS_PIPE7 */ "DLB_ECMP Group Member Statistic.", 1348 /* DLB_ECMP_HIST_GROUP_LOAD */ "DLB_ECMP Historical Group loading, CPU access is for debug purpose only.", 1349 /* DLB_ECMP_HIST_LOAD */ "DLB_ECMP Historical Loading for each member, CPU access is for debug purpose only. Even read can be a problem, disable DLB_ECMP_QUALITY_CONTROL.ENABLE_AVG_CALC first.", 1350 /* DLB_ECMP_HIST_QSIZE */ "DLB_ECMP Historical QSize for each member, CPU access is for debug purpose only.", 1351 /* DLB_ECMP_INST_GROUP_LOAD */ "DLB_ECMP Instant Group Loading, CPU access is for debug purpose only.", 1352 /* DLB_ECMP_INST_LOAD */ "DLB_ECMP Instant Load for each member, CPU access is for debug purpose only.", 1353 /* DLB_ECMP_INST_QSIZE */ "DLB_ECMP Instant Qsize for each member, CPU access is for debug purpose only.", 1354 /* DLB_ECMP_LINK_CONTROL */ "Link Status Control.", 1355 /* DLB_ECMP_MEMBERSHIP_REVERSE_MAP */ "DLB_ECMP Member Group Map", 1356 /* DLB_ECMP_MEMBER_ATTRIBUTE */ "DLB_ECMP Member Attributes table for next hop. Indexed by DLB_ECMP_FLOWSET.MEMBER_ID.", 1357 /* DLB_ECMP_MEMBER_STATUS */ "DLB_ECMP Mmeber Status for each member. CPU access is for debug purpose only.", 1358 /* DLB_ECMP_MEMBER_SW_STATE */ "DLB_ECMP SW per member up/down configuration.", 1359 /* DLB_ECMP_OPTIMAL_CANDIDATE */ "DLB_ECMP Optimal Candidate selection result, CPU access is for debug purpose only.", 1360 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE0 */ "DLB_ECMP Optimal Candidate table.", 1361 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE1 */ "DLB_ECMP Optimal Candidate table.", 1362 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE2 */ "DLB_ECMP Optimal Candidate table.", 1363 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE3 */ "DLB_ECMP Optimal Candidate table.", 1364 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE4 */ "DLB_ECMP Optimal Candidate table.", 1365 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE5 */ "DLB_ECMP Optimal Candidate table.", 1366 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE6 */ "DLB_ECMP Optimal Candidate table.", 1367 /* DLB_ECMP_OPTIMAL_CANDIDATE_PIPE7 */ "DLB_ECMP Optimal Candidate table.", 1368 /* DLB_ECMP_PLA_QUANTIZE_THRESHOLD */ "DLB_ECMP Physical Link Accounting Quality Threshold", 1369 /* DLB_ECMP_PORT_AVG_QUALITY_MEASURE */ "Configuration for averaged load calculation used in ECMP feature.", 1370 /* DLB_ECMP_PORT_AVG_QUALITY_MEASURE_PIPE0 */ "Configuration for averaged load calculation used in ECMP feature.", 1371 /* DLB_ECMP_PORT_AVG_QUALITY_MEASURE_PIPE1 */ "Configuration for averaged load calculation used in ECMP feature.", 1372 /* DLB_ECMP_PORT_AVG_QUALITY_MEASURE_PIPE2 */ "Configuration for averaged load calculation used in ECMP feature.", 1373 /* DLB_ECMP_PORT_AVG_QUALITY_MEASURE_PIPE3 */ "Configuration for averaged load calculation used in ECMP feature.", 1374 /* DLB_ECMP_PORT_INST_QUALITY_MEASURE */ "Configuration for instant load calculation used in ECMP feature.", 1375 /* DLB_ECMP_PORT_INST_QUALITY_MEASURE_PIPE0 */ "Configuration for instant load calculation used in ECMP feature.", 1376 /* DLB_ECMP_PORT_INST_QUALITY_MEASURE_PIPE1 */ "Configuration for instant load calculation used in ECMP feature.", 1377 /* DLB_ECMP_PORT_INST_QUALITY_MEASURE_PIPE2 */ "Configuration for instant load calculation used in ECMP feature.", 1378 /* DLB_ECMP_PORT_INST_QUALITY_MEASURE_PIPE3 */ "Configuration for instant load calculation used in ECMP feature.", 1379 /* DLB_ECMP_PORT_QUALITY_MAPPING */ "DLB_ECMP Quality Mapping.", 1380 /* DLB_ECMP_PORT_QUALITY_UPDATE_MEASURE_CONTROL */ "DLB Port Quality Update Measure Control.", 1381 /* DLB_ECMP_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE0 */ "DLB Port Quality Update Measure Control.", 1382 /* DLB_ECMP_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE1 */ "DLB Port Quality Update Measure Control.", 1383 /* DLB_ECMP_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE2 */ "DLB Port Quality Update Measure Control.", 1384 /* DLB_ECMP_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE3 */ "DLB Port Quality Update Measure Control.", 1385 /* DLB_ECMP_PORT_STATE */ "Member Hardware Link Status", 1386 /* DLB_ECMP_QUALITY_CONTROL */ "DLB_ECMP Quality Control Configuration. Indexed by Member_ID.", 1387 /* DLB_ECMP_QUALITY_MAPPING */ "DLB_ECMP Quality Mapping table.", 1388 /* DLB_ECMP_QUALITY_RESULT */ "DLB_ECMP Quality Result for each member. CPU access is for debug purpose only.", 1389 /* DLB_ECMP_QUANTIZED_AVG_QUALITY_MEASURE */ "DLB Flow Set Page.", 1390 /* DLB_ECMP_QUANTIZED_AVG_QUALITY_MEASURE_PIPE0 */ "DLB Flow Set Page.", 1391 /* DLB_ECMP_QUANTIZED_AVG_QUALITY_MEASURE_PIPE1 */ "DLB Flow Set Page.", 1392 /* DLB_ECMP_QUANTIZED_AVG_QUALITY_MEASURE_PIPE2 */ "DLB Flow Set Page.", 1393 /* DLB_ECMP_QUANTIZED_AVG_QUALITY_MEASURE_PIPE3 */ "DLB Flow Set Page.", 1394 /* DLB_ECMP_QUANTIZE_CONTROL */ "Configuration for Credit metric quantization calculation. Software access to this register is only possible when QUALITY_CONTROL.AVERAGE_CALCULATION_ENABLE is cleared.", 1395 /* DLB_ECMP_SER_FIFO */ "DLB CM SER FIFO", 1396 /* DLB_ECMP_VLA_EXPECTED_LOADING_THRESHOLD */ "Virtual link accounting expected loading threshold", 1397 /* DLB_ECMP_VLA_MEMBER_IMBALANCE_THRESHOLD */ "DLB_ECMP Virtual Link Accounting Profile", 1398 /* DLB_ECMP_VLA_QUALITY_MEASURE_CONTROL */ "Virtual link accounting configuration table", 1399 /* DLB_HGT_ETHERTYPE_ELIGIBILITY_MAP */ "Ethernet Type Eligiblity table", 1400 /* DLB_HGT_FLOWSET */ "DLB_HGT Flow Set Timestamp and Member Information. This table is indexed by a hash of the packet flow. CPU access is for debug purpose only.", 1401 /* DLB_HGT_FLOWSET_PORT */ "DLB_HGT Flow Set Assigned Member.", 1402 /* DLB_HGT_FLOWSET_PORT_X */ "DLB_HGT Flow Set Assigned Member.", 1403 /* DLB_HGT_FLOWSET_PORT_Y */ "DLB_HGT Flow Set Assigned Member.", 1404 /* DLB_HGT_FLOWSET_TIMESTAMP */ "DLB_HGT Flow Set Observation Timestamp.", 1405 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE */ "DLB_HGT Flow Set Page-Number table.", 1406 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE_X */ "DLB_HGT Flow Set Page-Number table.", 1407 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE_Y */ "DLB_HGT Flow Set Page-Number table.", 1408 /* DLB_HGT_FLOWSET_TIMESTAMP_X */ "DLB_HGT Flow Set Observation Timestamp.", 1409 /* DLB_HGT_FLOWSET_TIMESTAMP_Y */ "DLB_HGT Flow Set Observation Timestamp.", 1410 /* DLB_HGT_FLOWSET_X */ "DLB_HGT Flow Set Assigned Member.", 1411 /* DLB_HGT_FLOWSET_Y */ "DLB_HGT Flow Set Assigned Member.", 1412 /* DLB_HGT_GLB_QUANTIZE_THRESHOLDS */ "DLB_HGT Quantization Thresholds table.", 1413 /* DLB_HGT_GROUP_CONTROL */ "DLB_HGT Group Parameters.", 1414 /* DLB_HGT_GROUP_CONTROL_X */ "DLB_HGT Group Parameters.", 1415 /* DLB_HGT_GROUP_CONTROL_Y */ "DLB_HGT Group Parameters.", 1416 /* DLB_HGT_GROUP_MEMBERSHIP */ "DLB_HGT Group Member Bitmap.", 1417 /* DLB_HGT_GROUP_STATS */ "DLB_HGT Group Member Bitmap.", 1418 /* DLB_HGT_GROUP_STATS_X */ "DLB_HGT Group Member Bitmap.", 1419 /* DLB_HGT_GROUP_STATS_Y */ "DLB_HGT Group Member Bitmap.", 1420 /* DLB_HGT_HIST_LOAD */ "DLB_HGT Historical Load for each member, CPU access is for debug purpose only.", 1421 /* DLB_HGT_INST_LOAD */ "DLB HGT Instant Load for each member, contains the queue size and byte_count. CPU access is for debug purpose only.", 1422 /* DLB_HGT_LAG_EEM_CONFIGURATION */ "EtherType eligibility configuration", 1423 /* DLB_HGT_LAG_ETHERTYPE_ELIGIBILITY_MAP */ "EtherType based DLB Eligibility Configuration", 1424 /* DLB_HGT_LAG_FINAL_MEMBERS_QUALITY_MEASURE */ "Final Member Quality Measure.", 1425 /* DLB_HGT_LAG_FINAL_MEMBERS_QUALITY_MEASURE_PIPE0 */ "Final Member Quality Measure.", 1426 /* DLB_HGT_LAG_FINAL_MEMBERS_QUALITY_MEASURE_PIPE1 */ "Final Member Quality Measure.", 1427 /* DLB_HGT_LAG_FINAL_MEMBERS_QUALITY_MEASURE_PIPE2 */ "Final Member Quality Measure.", 1428 /* DLB_HGT_LAG_FINAL_MEMBERS_QUALITY_MEASURE_PIPE3 */ "Final Member Quality Measure.", 1429 /* DLB_HGT_LAG_FLOWSET */ "DLB Flow Set Assigned Port Member.", 1430 /* DLB_HGT_LAG_FLOWSET_PIPE0 */ "DLB Flow Set Assigned Port Member.", 1431 /* DLB_HGT_LAG_FLOWSET_PIPE1 */ "DLB Flow Set Assigned Port Member.", 1432 /* DLB_HGT_LAG_FLOWSET_PIPE2 */ "DLB Flow Set Assigned Port Member.", 1433 /* DLB_HGT_LAG_FLOWSET_PIPE3 */ "DLB Flow Set Assigned Port Member.", 1434 /* DLB_HGT_LAG_FLOWSET_TIMESTAMP_PAGE */ "DLB Flow Set Page-Number table.", 1435 /* DLB_HGT_LAG_FLOWSET_TIMESTAMP_PAGE_PIPE0 */ "DLB Flow Set Page-Number table.", 1436 /* DLB_HGT_LAG_FLOWSET_TIMESTAMP_PAGE_PIPE1 */ "DLB Flow Set Page-Number table.", 1437 /* DLB_HGT_LAG_FLOWSET_TIMESTAMP_PAGE_PIPE2 */ "DLB Flow Set Page-Number table.", 1438 /* DLB_HGT_LAG_FLOWSET_TIMESTAMP_PAGE_PIPE3 */ "DLB Flow Set Page-Number table.", 1439 /* DLB_HGT_LAG_GLB_QUANTIZE_THRESHOLD */ "DLB Quantization Thresholds table.", 1440 /* DLB_HGT_LAG_GROUP_CONTROL */ "DLB Group Parameters.", 1441 /* DLB_HGT_LAG_GROUP_MEMBERSHIP */ "DLB Group Member Bitmap.", 1442 /* DLB_HGT_LAG_GROUP_STATS */ "DLB Group Member Statistic.", 1443 /* DLB_HGT_LAG_GROUP_STATS_PIPE0 */ "DLB Group Member Statistic.", 1444 /* DLB_HGT_LAG_GROUP_STATS_PIPE1 */ "DLB Group Member Statistic.", 1445 /* DLB_HGT_LAG_GROUP_STATS_PIPE2 */ "DLB Group Member Statistic.", 1446 /* DLB_HGT_LAG_GROUP_STATS_PIPE3 */ "DLB Group Member Statistic.", 1447 /* DLB_HGT_LAG_LINK_CONTROL */ "Link Status Control.", 1448 /* DLB_HGT_LAG_OPTIMAL_CANDIDATE */ "DLB Optimal Candidate table.", 1449 /* DLB_HGT_LAG_OPTIMAL_CANDIDATE_PIPE0 */ "DLB Optimal Candidate table.", 1450 /* DLB_HGT_LAG_OPTIMAL_CANDIDATE_PIPE1 */ "DLB Optimal Candidate table.", 1451 /* DLB_HGT_LAG_OPTIMAL_CANDIDATE_PIPE2 */ "DLB Optimal Candidate table.", 1452 /* DLB_HGT_LAG_OPTIMAL_CANDIDATE_PIPE3 */ "DLB Optimal Candidate table.", 1453 /* DLB_HGT_LAG_PORT_AVG_QUALITY_MEASURE */ "Configuration for averaged load calculation.", 1454 /* DLB_HGT_LAG_PORT_AVG_QUALITY_MEASURE_PIPE0 */ "Configuration for averaged load calculation.", 1455 /* DLB_HGT_LAG_PORT_AVG_QUALITY_MEASURE_PIPE1 */ "Configuration for averaged load calculation.", 1456 /* DLB_HGT_LAG_PORT_AVG_QUALITY_MEASURE_PIPE2 */ "Configuration for averaged load calculation.", 1457 /* DLB_HGT_LAG_PORT_AVG_QUALITY_MEASURE_PIPE3 */ "Configuration for averaged load calculation.", 1458 /* DLB_HGT_LAG_PORT_INST_QUALITY_MEASURE */ "Configuration for instant load calculation.", 1459 /* DLB_HGT_LAG_PORT_INST_QUALITY_MEASURE_PIPE0 */ "Configuration for instant load calculation.", 1460 /* DLB_HGT_LAG_PORT_INST_QUALITY_MEASURE_PIPE1 */ "Configuration for instant load calculation.", 1461 /* DLB_HGT_LAG_PORT_INST_QUALITY_MEASURE_PIPE2 */ "Configuration for instant load calculation.", 1462 /* DLB_HGT_LAG_PORT_INST_QUALITY_MEASURE_PIPE3 */ "Configuration for instant load calculation.", 1463 /* DLB_HGT_LAG_PORT_QUALITY_MAPPING */ "DLB Members Quality Mapping.", 1464 /* DLB_HGT_LAG_PORT_QUALITY_UPDATE_MEASURE_CONTROL */ "DLB Port Quality Update Measure Control.", 1465 /* DLB_HGT_LAG_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE0 */ "DLB Port Quality Update Measure Control.", 1466 /* DLB_HGT_LAG_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE1 */ "DLB Port Quality Update Measure Control.", 1467 /* DLB_HGT_LAG_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE2 */ "DLB Port Quality Update Measure Control.", 1468 /* DLB_HGT_LAG_PORT_QUALITY_UPDATE_MEASURE_CONTROL_PIPE3 */ "DLB Port Quality Update Measure Control.", 1469 /* DLB_HGT_LAG_PORT_STATE */ "Member Hardware Link Status", 1470 /* DLB_HGT_LAG_QUANTIZED_AVG_QUALITY_MEASURE */ "DLB Flow Set Page.", 1471 /* DLB_HGT_LAG_QUANTIZED_AVG_QUALITY_MEASURE_PIPE0 */ "DLB Flow Set Page.", 1472 /* DLB_HGT_LAG_QUANTIZED_AVG_QUALITY_MEASURE_PIPE1 */ "DLB Flow Set Page.", 1473 /* DLB_HGT_LAG_QUANTIZED_AVG_QUALITY_MEASURE_PIPE2 */ "DLB Flow Set Page.", 1474 /* DLB_HGT_LAG_QUANTIZED_AVG_QUALITY_MEASURE_PIPE3 */ "DLB Flow Set Page.", 1475 /* DLB_HGT_LAG_QUANTIZE_CONTROL */ "Configuration for Credit metric quantization calculation. Software access to this register is only possible when QUALITY_CONTROL.AVERAGE_CALCULATION_ENABLE is cleared.", 1476 /* DLB_HGT_LINK_CONTROL */ "DLB_HGT Software Link Status Control.", 1477 /* DLB_HGT_MEMBER_ATTRIBUTE */ "DLB_HGT Member Attribute table for port number. Indexed by DLB_HGT_FLOWSET.MEMBER_ID.", 1478 /* DLB_HGT_MEMBER_HW_STATE */ "Member Hardware Link Status", 1479 /* DLB_HGT_MEMBER_STATUS */ "DLB_HGT Member Status for each member. CPU access is for debug purpose only.", 1480 /* DLB_HGT_MEMBER_SW_STATE */ "DLB_HGT SW per member up/down configuration.", 1481 /* DLB_HGT_OPTIMAL_CANDIDATE */ "DLB_HGT Optimal Candidate table.", 1482 /* DLB_HGT_OPTIMAL_CANDIDATE_X */ "DLB_HGT Optimal Candidate table.", 1483 /* DLB_HGT_OPTIMAL_CANDIDATE_Y */ "DLB_HGT Optimal Candidate table.", 1484 /* DLB_HGT_PLA_QUANTIZE_THRESHOLD */ "DLB_HGT Quantization Thresholds table.", 1485 /* DLB_HGT_PORT_MEMBER_MAP */ "DLB_HGT Port number to Member ID mapping table.", 1486 /* DLB_HGT_PORT_QUALITY_MAPPING */ "DLB_HGT Quality Mapping.", 1487 /* DLB_HGT_PORT_STATE */ "DLB_HGT Hardware Link State.", 1488 /* DLB_HGT_QUALITY_CONTROL */ "DLB_HGT Per member configuration. Indexed by Member_ID.", 1489 /* DLB_HGT_QUALITY_MAPPING */ "DLB_HGT Quality Mapping table. Contains member quality for each member profile.", 1490 /* DLB_HGT_QUALITY_RESULT */ "DLB_HGT Quality Result for each member. CPU access is for debug purpose only.", 1491 /* DLB_HGT_QUANTIZE_THRESHOLD */ "DLB_HGT Quantization Thresholds table.", 1492 /* DLB_HGT_RR_SELECTION_POINTER */ "Indicates the most recent selected member for each DLB group.", 1493 /* DLB_LAG_ETHERTYPE_ELIGIBILITY_MAP */ "Ethernet Type Eligiblity table", 1494 /* DLB_LAG_FLOWSET */ "DLB_LAG Flow Set Timestamp and Member Information. This table is indexed by a hash of the packet flow. CPU access is for debug purpose only.", 1495 /* DLB_LAG_FLOWSET_TIMESTAMP_PAGE */ "DLB_LAG Flow Set Page. This table is indexed by a hash of the packet flow. CPU access is for debug purpose only.", 1496 /* DLB_LAG_GROUP_CONTROL */ "LAG DLB Group Control configuration.", 1497 /* DLB_LAG_GROUP_MEMBERSHIP */ "DLB_LAG Group Membership for each group.", 1498 /* DLB_LAG_GROUP_STATS */ "DLB_LAG Statistics for each group.", 1499 /* DLB_LAG_HIST_GROUP_LOAD */ "DLB_LAG Historical Group Load, CPU access is for debug purpose only.", 1500 /* DLB_LAG_HIST_LOAD */ "DLB_LAG Historical Load for each member, CPU access is for debug purpose only. Even read can be a problem, disable DLB_LAG_QUALITY_CONTROL.ENABLE_AVG_CALC first.", 1501 /* DLB_LAG_HIST_QSIZE */ "DLB_LAG Historical QSIZE for each member, CPU access is for debug purpose only.", 1502 /* DLB_LAG_INST_GROUP_LOAD */ "DLB_LAG Instant Group Load, CPU access is for debug purpose only.", 1503 /* DLB_LAG_INST_LOAD */ "DLB_LAG Instant Load for each member, CPU access is for debug purpose only.", 1504 /* DLB_LAG_INST_QSIZE */ "DLB_LAG Instant Queue Size for each member, CPU access is for debug purpose only.", 1505 /* DLB_LAG_MEMBERSHIP_REVERSE_MAP */ "DLB_LAG Member Group Map.", 1506 /* DLB_LAG_MEMBER_ATTRIBUTE */ "DLB_LAG Member Attribute table for modid, portid. Indexed by DLB_LAG_FLOWSET.MEMBER_ID.", 1507 /* DLB_LAG_MEMBER_STATUS */ "DLB_LAG Member Status for each member. CPU access is for debug purpose only.", 1508 /* DLB_LAG_MEMBER_SW_STATE */ "DLB_LAG SW per member up/down configuration.", 1509 /* DLB_LAG_OPTIMAL_CANDIDATE */ "DLB_LAG Optimal Candidate selection result, CPU access is for debug purpose only.", 1510 /* DLB_LAG_PLA_QUANTIZE_THRESHOLD */ "DLB_LAG Physical Link Accounting Quality Threshold", 1511 /* DLB_LAG_QUALITY_CONTROL */ "DLB_LAG Quality Control. Indexed by Member_ID.", 1512 /* DLB_LAG_QUALITY_MAPPING */ "DLB_LAG Quality mapping table.", 1513 /* DLB_LAG_QUALITY_RESULT */ "DLB_LAG Quality Result for each member. CPU access is for debug purpose only.", 1514 /* DLB_LAG_VLA_EXPECTED_LOADING_THRESHOLD */ "Virtual link accounting expected loading threshold", 1515 /* DLB_LAG_VLA_MEMBER_IMBALANCE_THRESHOLD */ "DLB_LAG Virtual Link Accounting Threshold Profile .", 1516 /* DLB_LAG_VLA_QUALITY_MEASURE_CONTROL */ "Virtual link accounting configuration table", 1517 /* DO_NOT_FT_ENTRY */ "BROADSCAN: Table to enable SW to enforce DO_NOT_FT while inserting SW entries", 1518 /* DQM_AUTO_DOC_NAME_37 */ "INTERNAL", 1519 /* DQM_AUTO_DOC_NAME_47 */ "INTERNAL", 1520 /* DQM_AUTO_DOC_NAME_51 */ "INTERNAL", 1521 /* DQM_AUTO_DOC_NAME_57 */ "INTERNAL", 1522 /* DQM_AUTO_DOC_NAME_62 */ "INTERNAL", 1523 /* DQM_AUTO_DOC_NAME_65 */ "INTERNAL", 1524 /* DQM_BDB_LINK_LIST */ "BDBLL - BDB link list", 1525 /* DQM_BDM */ "Bundle descriptor memory access", 1526 /* DQM_BUNDLE_DESCRIPTOR_MEMORY */ "Full Multicast User Count\n Number of duplications of the FullMulticast Dbuffs (UserCnt+1).", 1527 /* DQM_QUEUE_DATA_MEMORY */ "QDM", 1528 /* DQM_TX_BUNDLE_BUFFER_FIFOS_MEMORY */ "INTERNAL", 1529 /* DQM_TX_BUNDLE_DESCRIPTOR_FIFOS_MEMORY */ "INTERNAL", 1530 /* DRCA_DWF */ "Data write FIFO", 1531 /* DRCA_READ_DATA_FIFO */ "DRC Read data Memory", 1532 /* DRCA_RXI_MEM */ "DRC RXI Memory", 1533 /* DRCA_WR_CRC_FIFO */ "write CRC FIFO", 1534 /* DRCB_DWF */ "Data write FIFO", 1535 /* DRCB_READ_DATA_FIFO */ "DRC Read data Memory", 1536 /* DRCB_RXI_MEM */ "DRC RXI Memory", 1537 /* DRCB_WR_CRC_FIFO */ "write CRC FIFO", 1538 /* DRCC_DWF */ "Data write FIFO", 1539 /* DRCC_READ_DATA_FIFO */ "DRC Read data Memory", 1540 /* DRCC_RXI_MEM */ "DRC RXI Memory", 1541 /* DRCC_WR_CRC_FIFO */ "write CRC FIFO", 1542 /* DRCD_DWF */ "Data write FIFO", 1543 /* DRCD_RXI_MEM */ "DRC RXI Memory", 1544 /* DRCD_WR_CRC_FIFO */ "write CRC FIFO", 1545 /* DRCE_DWF */ "Data write FIFO", 1546 /* DRCE_RXI_MEM */ "DRC RXI Memory", 1547 /* DRCE_WR_CRC_FIFO */ "write CRC FIFO", 1548 /* DRCF_DWF */ "Data write FIFO", 1549 /* DRCF_RXI_MEM */ "DRC RXI Memory", 1550 /* DRCF_WR_CRC_FIFO */ "write CRC FIFO", 1551 /* DRCG_DWF */ "Data write FIFO", 1552 /* DRCG_RXI_MEM */ "DRC RXI Memory", 1553 /* DRCG_WR_CRC_FIFO */ "write CRC FIFO", 1554 /* DRCH_DWF */ "Data write FIFO", 1555 /* DRCH_RXI_MEM */ "DRC RXI Memory", 1556 /* DRCH_WR_CRC_FIFO */ "write CRC FIFO", 1557 /* DROP_VECTOR_MASK */ "This is used to compress drop reasons into a 8-bit drop status indicator for IFP.", 1558 /* DSCP_STRENGTH_PROFILE */ "DSCP Strength Profile.", 1559 /* DSCP_TABLE */ "Diff Serv Code Point Table", 1560 /* DST_COMPRESSION */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1561 /* DST_COMPRESSION_DATA_ONLY */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1562 /* DST_COMPRESSION_DATA_ONLY_PIPE0 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1563 /* DST_COMPRESSION_DATA_ONLY_PIPE1 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1564 /* DST_COMPRESSION_DATA_ONLY_PIPE2 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1565 /* DST_COMPRESSION_DATA_ONLY_PIPE3 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1566 /* DST_COMPRESSION_PIPE0 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1567 /* DST_COMPRESSION_PIPE1 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1568 /* DST_COMPRESSION_PIPE2 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1569 /* DST_COMPRESSION_PIPE3 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1570 /* DST_COMPRESSION_TCAM_ONLY */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1571 /* DST_COMPRESSION_TCAM_ONLY_PIPE0 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1572 /* DST_COMPRESSION_TCAM_ONLY_PIPE1 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1573 /* DST_COMPRESSION_TCAM_ONLY_PIPE2 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1574 /* DST_COMPRESSION_TCAM_ONLY_PIPE3 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 1575 /* E2E_HOL_STATUS */ "Remote Module End-to-End HOL Status Table", 1576 /* E2E_HOL_STATUS_1 */ "Remote Module End-to-End HOL Status Table", 1577 /* ECGM_FDCM */ "Packet descriptors per Interface", 1578 /* ECGM_FDCMAX */ "DCM-MAX - maximum packet descriptors per Interface.", 1579 /* ECGM_FDCT_TABLE */ "PD's and DB's thresholds per interface table. The index to this table is INTERFACE-PROFILE(3),PRIORITY(1). The result is set of thresholds corresponding to per interface resources.", 1580 /* ECGM_FQSM */ "FQSM - DB'S per Interface Memory.", 1581 /* ECGM_FQSMAX */ "FQSM-MAX - maximum data buffers per interface Memory.", 1582 /* ECGM_PDCM */ "Unicast and Multicast packet descriptors counters per OTM-Port Memory.", 1583 /* ECGM_PDCMAX */ "PDCM-MAX - maximum unicast and multicast packet descriptors per OTM-Port Memory.", 1584 /* ECGM_PDCT_TABLE */ "This memory defines per OTM-Port-Profile the thresholds related to packet descriptors tests in CGM.", 1585 /* ECGM_PQSM */ "Unicast and Multicast consumed data buffers counters per OTM-Port.", 1586 /* ECGM_PQSMAX */ "PQSM-MAX - maximum unicast and multicast DB's per OTM-Port Memory.", 1587 /* ECGM_PQST_TABLE */ "Data buffers thresholds per Otm-Port-Profile table.\n This memory defines per OTM-Port-Profile the thresholds related to data buffers tests per OTM-Port in CGM.", 1588 /* ECGM_QDCM */ "Packet descriptors per queue Memory.", 1589 /* ECGM_QDCMAX */ "DCM-MAX - maximum packet descriptors per queue Memory.", 1590 /* ECGM_QDCT_TABLE */ "PD's thresholds per queue table. The index to this table is CGM-PORT-PROFILE(4),Egress-Tc(3). The result is set of thresholds corresponding to per queue resources.", 1591 /* ECGM_QQSM */ "QQSM - DB'S per Queue Memory.", 1592 /* ECGM_QQSMAX */ "QQSM-MAX - maximum data buffers per queue Memory.", 1593 /* ECGM_QQST_TABLE */ "Data buffers thresholds per queue table.", 1594 /* ECI_AUTO_DOC_NAME_48 */ "INTERNAL", 1595 /* ECI_CMDMEM */ "", 1596 /* ECI_DATA_MEM */ "", 1597 /* ECI_ECI_PIR_RXI_MEM */ "Fifo that holds the data received from EPNI0/1 to ECI", 1598 /* ECI_EGR_MCT */ "Multicast table", 1599 /* ECI_EGR_MCT_MAPPING */ "Multicast table mapping.\n Address is MC-ID17:3.\n Selection beweern McMap0 to McMap7 is according to MC-ID2:0.\n The result from this table is used to access the EgrMct memory", 1600 /* ECI_EGR_PORT_MAP */ "Mappoing of FTMH output port to channel ID and framer interface number.", 1601 /* ECI_MBU_MEM */ "INTERNAL", 1602 /* ECI_MEM_0 */ "", 1603 /* ECI_MEM_1 */ "", 1604 /* ECI_MEM_2 */ "", 1605 /* ECI_MEM_3 */ "", 1606 /* ECI_MEM_4 */ "", 1607 /* ECI_MEM_00010000 */ "INTERNAL", 1608 /* ECI_MEM_0_SHDW */ "", 1609 /* ECI_MEM_1_SHDW */ "", 1610 /* ECI_MEM_2_SHDW */ "", 1611 /* ECI_PKT_SRC_TO_CHANNEL_MAP */ "Map incoming PktSrcId (from CPU interface) to CPU channel. Channel plus base address will access CtxtMap and CpuTdmCtxtMap.", 1612 /* ECI_RESERVED_48 */ "INTERNAL", 1613 /* ECI_SAM_CTRL */ "Single entry memory that activates the sbus acceleration machine. need to write the 640b data in order to configure the machine. the valid bit indicates that SAM had finished.", 1614 /* ECI_TDM_CONFIG */ "TDM configuration for each TDM context.\n The index to this table is 80xframerNdx + channel_ID", 1615 /* ECI_ZIKARON_MBU */ "INTERNAL", 1616 /* ECMP_DLB_CONTROL */ "DLB Enables for ECMP.", 1617 /* ECMP_GROUP_HIERARCHICAL */ "First level ECMP group table for hierarchical ECMP.", 1618 /* EDB_1DBG_B */ "FORCE SAF control", 1619 /* EDB_AC_ENTRY_WITH_DATA_FORMAT */ "Encapsulation-Stack AC Format", 1620 /* EDB_AC_HALF_ENTRY_FORMAT */ "Encapsulation-Stack AC Format", 1621 /* EDB_DATA_FORMAT */ "Encapsulation-Stack Data Format", 1622 /* EDB_DBF */ "Data Buffers EGQ", 1623 /* EDB_DBF_0 */ "Data Buffers EGQ0", 1624 /* EDB_DBF_1 */ "Data Buffers EGQ1, used in EGQ0 in clear channel mode", 1625 /* EDB_DBF_BANK */ "Data Buffers EGQ", 1626 /* EDB_DBF_LSB_BANK */ "Data Buffers EGQ", 1627 /* EDB_DEVICE_TO_PHYSICAL_PORT_NUMBER_MAPPING */ "Egress Device to Physical Port Number Mapping Register. Indexed by the (logical) Device port number, and provides the corresponding physical port number.", 1628 /* EDB_EEDB_BANK */ "The encapsulation data is maintained in an Egress Encapsulation Database (EEDB)that is specific per egress device. This database contains tunneling and link layer information.\n The EEDB is built from 16 banks, each of them of 2K entries. Each entry if pointed by an Out-LIF or EEI. Every address (tables row) may include one or two entries.", 1629 /* EDB_EEDB_MAP_TO_PROTECTION_PTR */ "Specify per bank (one of 22 lower banks) if it supports protection pointer functionality. Maps each bank to where its protection pointer is located & holds enable for this feature for the specified bank.", 1630 /* EDB_EEDB_TOP_BANK */ "The top 8 banks of the EEDB have 1k entries each.\n TopBank3..0 - are equivalent to Bank22\n TopBank7..4 - are equivalent to Bank23", 1631 /* EDB_ESEM_0_ACDT_AUX */ "INTERNAL", 1632 /* EDB_ESEM_0_ACDT_H */ "INTERNAL", 1633 /* EDB_ESEM_0_KEYT_AUX */ "INTERNAL", 1634 /* EDB_ESEM_0_KEYT_PLDT_H */ "INTERNAL", 1635 /* EDB_ESEM_0_MAA_CAM */ "INTERNAL", 1636 /* EDB_ESEM_0_MAA_CAM_PAYLOAD */ "INTERNAL", 1637 /* EDB_ESEM_0_MANAGEMENT_MEMORY_H */ "INTERNAL", 1638 /* EDB_ESEM_0_MANAGEMENT_REQUEST */ "Management requests", 1639 /* EDB_ESEM_0_PLDT_AUX */ "INTERNAL", 1640 /* EDB_ESEM_0_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 1641 /* EDB_ESEM_1_ACDT_AUX */ "INTERNAL", 1642 /* EDB_ESEM_1_ACDT_H */ "INTERNAL", 1643 /* EDB_ESEM_1_KEYT_AUX */ "INTERNAL", 1644 /* EDB_ESEM_1_KEYT_PLDT_H */ "INTERNAL", 1645 /* EDB_ESEM_1_MAA_CAM */ "INTERNAL", 1646 /* EDB_ESEM_1_MAA_CAM_PAYLOAD */ "INTERNAL", 1647 /* EDB_ESEM_1_MANAGEMENT_MEMORY_H */ "INTERNAL", 1648 /* EDB_ESEM_1_MANAGEMENT_REQUEST */ "Management requests", 1649 /* EDB_ESEM_1_PLDT_AUX */ "INTERNAL", 1650 /* EDB_ESEM_1_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 1651 /* EDB_ESEM_ACDT_AUX */ "INTERNAL", 1652 /* EDB_ESEM_ACDT_H */ "INTERNAL", 1653 /* EDB_ESEM_KEYT_AUX */ "INTERNAL", 1654 /* EDB_ESEM_KEYT_PLDT_H */ "INTERNAL", 1655 /* EDB_ESEM_MAA_CAM */ "INTERNAL", 1656 /* EDB_ESEM_MAA_CAM_PAYLOAD */ "INTERNAL", 1657 /* EDB_ESEM_MANAGEMENT_MEMORY_H */ "INTERNAL", 1658 /* EDB_ESEM_MANAGEMENT_REQUEST */ "Management requests", 1659 /* EDB_ESEM_PLDT_AUX */ "INTERNAL", 1660 /* EDB_ESEM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 1661 /* EDB_FBM */ "Represents the dynamic status of each bacnk of the EGQ 1K Buffers. Each entry represents a bitmap of 32 buffers indicating, per buffer, whether it is free or occupied.", 1662 /* EDB_GLEM_ACDT_AUX */ "INTERNAL", 1663 /* EDB_GLEM_ACDT_H */ "INTERNAL", 1664 /* EDB_GLEM_ACDT_MASTER_H */ "INTERNAL", 1665 /* EDB_GLEM_ACDT_SLAVE_H */ "INTERNAL", 1666 /* EDB_GLEM_KEYT_AUX */ "INTERNAL", 1667 /* EDB_GLEM_KEYT_PLDT_H */ "INTERNAL", 1668 /* EDB_GLEM_MAA_CAM */ "INTERNAL", 1669 /* EDB_GLEM_MAA_CAM_PAYLOAD */ "INTERNAL", 1670 /* EDB_GLEM_MANAGEMENT_MEMORY_H */ "INTERNAL", 1671 /* EDB_GLEM_MANAGEMENT_REQUEST */ "Management requests", 1672 /* EDB_GLEM_PLDT_AUX */ "INTERNAL", 1673 /* EDB_GLEM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 1674 /* EDB_IPV4_TUNNEL_FORMAT */ "Encapsulation-Stack IPv4 Tunnel Format", 1675 /* EDB_IP_CUT_THRU_CLASS */ "To select the cut-through class based on ingress port number", 1676 /* EDB_LINK_LAYER_OR_ARP_FORMAT */ "Encapsulation-Stack Link Layer or ARP Format", 1677 /* EDB_LINK_LAYER_OR_ARP_NEW_FORMAT */ "Encapsulation-Stack Link Layer or New ARP Format", 1678 /* EDB_MAP_OUTLIF_TO_DSP */ "Egress Replication Database Entry Formats 6 and 7, generate up to three copies, each with unique OutLIF. The PP-DSP is generated by mapping the OutLIF through this table.\n The index to the table is OutLif (18 bits) and the result is PP-DSP corresponding to the OutLif.", 1679 /* EDB_MPLS_POP_FORMAT */ "Encapsulation-Stack MPLS Pop Format", 1680 /* EDB_MPLS_PUSH_FORMAT */ "Encapsulation-Stack MPLS Push Format", 1681 /* EDB_MPLS_SWAP_FORMAT */ "Encapsulation-Stack MPLS Swap Format", 1682 /* EDB_OUTRIF_TABLE */ "This table holds the outrif information instead of keeping it in the eedb.\n The data that was omitted is: Drop outlif-profile oam-lif-set vsi arp-pointer-valid arp-pointer.\n Instead we use RifProfileTable (index taken from this table) to establish: drop (1) outlif-profile (6) oam-lif-set (1).\n VSI = 0,RIF14:0 and ARP-pointer is never valid.\n The system can support upto 32k outrifs, in a resolution of 4k (4k, 8k, 12k...).\n Each row in the table holds 8 outrif-entries. an outrif-entry holds ...", 1683 /* EDB_OUT_RIF_FORMAT */ "Encapsulation-Stack Out-RIF Format", 1684 /* EDB_PROTECTION_ENTRY */ "EEDB format when used to hold 15 bits protection pointers to the ProtectionPtrTable. There are 4 Pointers per row, the relevant one is selected according to outlif2:1.\n For (Coupled mode & wide ees entry, i.e the outlif pointed to mpls or ip): bit14 in the protection pointer must be equal to the data in ProtectionPtrTable1'b0, protection-ptr13:0 in order to PASS the packet.\n For (Coupled mode + half entry) OR* De-Coupled mode + full entry): all 15 bits are the ...", 1685 /* EDB_RIF_PROFILE_TABLE */ "RifProfileTable (index taken from OutrifTable) to establish: drop (1) outlif-profile (6) oam-lif-set (1).", 1686 /* EDB_SER_FIFO */ "EDB SER FIFO", 1687 /* EDB_SER_FIFO_PIPE0 */ "EDB SER FIFO", 1688 /* EDB_SER_FIFO_PIPE1 */ "EDB SER FIFO", 1689 /* EDB_SER_FIFO_PIPE2 */ "EDB SER FIFO", 1690 /* EDB_SER_FIFO_PIPE3 */ "EDB SER FIFO", 1691 /* EDB_SER_FIFO_PIPE4 */ "EDB SER FIFO", 1692 /* EDB_SER_FIFO_PIPE5 */ "EDB SER FIFO", 1693 /* EDB_SER_FIFO_PIPE6 */ "EDB SER FIFO", 1694 /* EDB_SER_FIFO_PIPE7 */ "EDB SER FIFO", 1695 /* EDB_TRILL_FORMAT_FULL_ENTRY */ "Encapsulation-Stack TRILL Full Entry Format", 1696 /* EDB_TRILL_FORMAT_HALF_ENTRY */ "Encapsulation-Stack TRILL Half Entry Format", 1697 /* EDB_XMIT_START_COUNT */ "Determine the transmit start count threshold for cut-through and SAF mode", 1698 /* EDB_XMIT_START_COUNT_PIPE0 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1699 /* EDB_XMIT_START_COUNT_PIPE1 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1700 /* EDB_XMIT_START_COUNT_PIPE2 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1701 /* EDB_XMIT_START_COUNT_PIPE3 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1702 /* EDB_XMIT_START_COUNT_PIPE4 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1703 /* EDB_XMIT_START_COUNT_PIPE5 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1704 /* EDB_XMIT_START_COUNT_PIPE6 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1705 /* EDB_XMIT_START_COUNT_PIPE7 */ "Determine the transmit start count threshold for cut-through and SAF mode", 1706 /* EFFECTIVE_PHB_SELECT */ "Provides PHB select", 1707 /* EFP_COUNTER_TABLE */ "COUNTER TABLE FOR THE EFP", 1708 /* EFP_COUNTER_TABLE_PIPE0 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1709 /* EFP_COUNTER_TABLE_PIPE1 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1710 /* EFP_COUNTER_TABLE_PIPE2 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1711 /* EFP_COUNTER_TABLE_PIPE3 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1712 /* EFP_COUNTER_TABLE_PIPE4 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1713 /* EFP_COUNTER_TABLE_PIPE5 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1714 /* EFP_COUNTER_TABLE_PIPE6 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1715 /* EFP_COUNTER_TABLE_PIPE7 */ "Counter Table for the EFP. It will count the number of packets and bytes for those packets when directed to do so by an EFP action.", 1716 /* EFP_COUNTER_TABLE_X */ "COUNTER TABLE FOR THE EFP", 1717 /* EFP_COUNTER_TABLE_Y */ "COUNTER TABLE FOR THE EFP", 1718 /* EFP_METER_TABLE */ "METER TABLE STRUCTURES FOR THE EFP", 1719 /* EFP_METER_TABLE_PIPE0 */ "Meter Table Structures for the EFP.", 1720 /* EFP_METER_TABLE_PIPE1 */ "Meter Table Structures for the EFP.", 1721 /* EFP_METER_TABLE_PIPE2 */ "Meter Table Structures for the EFP.", 1722 /* EFP_METER_TABLE_PIPE3 */ "Meter Table Structures for the EFP.", 1723 /* EFP_METER_TABLE_X */ "METER TABLE STRUCTURES FOR THE EFP", 1724 /* EFP_METER_TABLE_Y */ "METER TABLE STRUCTURES FOR THE EFP", 1725 /* EFP_POLICY_TABLE */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE EFP", 1726 /* EFP_POLICY_TABLE_PIPE0 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1727 /* EFP_POLICY_TABLE_PIPE1 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1728 /* EFP_POLICY_TABLE_PIPE2 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1729 /* EFP_POLICY_TABLE_PIPE3 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1730 /* EFP_POLICY_TABLE_PIPE4 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1731 /* EFP_POLICY_TABLE_PIPE5 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1732 /* EFP_POLICY_TABLE_PIPE6 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1733 /* EFP_POLICY_TABLE_PIPE7 */ "Policy Table for determining actions in the EFP. This table will give the associated EFP action for the associated matching EFP_TCAM entry.", 1734 /* EFP_TCAM */ "TCAM FOR EFP", 1735 /* EFP_TCAM_PIPE0 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1736 /* EFP_TCAM_PIPE1 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1737 /* EFP_TCAM_PIPE2 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1738 /* EFP_TCAM_PIPE3 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1739 /* EFP_TCAM_PIPE4 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1740 /* EFP_TCAM_PIPE5 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1741 /* EFP_TCAM_PIPE6 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1742 /* EFP_TCAM_PIPE7 */ "TCAM for EFP. This will match the EFP keys based on packet fields and will determine the highest matching entry. The individual key bits can be masked using the MASK field to determine a match. This table works in conjunction with the EFP_POLICY_TABLE.", 1743 /* EGQ_ACTION_PROFILE_TABLE */ "Action profile table, used to configure per action profile its properties.\n Every address in this table corresponds with an action profile. Table has 8 entries.", 1744 /* EGQ_AUX_TABLE */ "The auxiliary data table is used in various stages of the PP for different applications. It is a 64K bit table. Its functionality is determined by Fallback For Bridge VLAN Commands register field AuxiliaryDataTableMode as follows:\n In Split-Horizon mode the table is used by the ERPP to determine for each AC the orientation (Hub or scope). In this mode table size is 64K x 1.\n In PBB mode the table is used by the ETPP to determine for the first 8K source syste ...", 1745 /* EGQ_BUF_LINK */ "Buffers link memory", 1746 /* EGQ_CBM */ "Credit Balance Memory. This memory holds the credit balance of the OFP.", 1747 /* EGQ_CCM */ "Calendars select sequence configuration memory", 1748 /* EGQ_CH_0_SCM */ "Channelize Interface 0 Shaper Calendar Memory", 1749 /* EGQ_CH_1_SCM */ "Channelize Interface 1 Shaper Calendar Memory", 1750 /* EGQ_CH_2_SCM */ "Channelize Interface 2 Shaper Calendar Memory", 1751 /* EGQ_CH_3_SCM */ "Channelize Interface 3 Shaper Calendar Memory", 1752 /* EGQ_CH_4_SCM */ "Channelize Interface 4 Shaper Calendar Memory", 1753 /* EGQ_CH_5_SCM */ "Channelize Interface 5 Shaper Calendar Memory", 1754 /* EGQ_CH_6_SCM */ "Channelize Interface 6 Shaper Calendar Memory", 1755 /* EGQ_CH_7_SCM */ "Channelize Interface 7 Shaper Calendar Memory", 1756 /* EGQ_CH_8_SCM */ "Channelize Interface 8 Shaper Calendar Memory", 1757 /* EGQ_CH_9_SCM */ "Channelize Interface 9 Shaper Calendar Memory", 1758 /* EGQ_CH_SCM_0 */ "Shaper Calendar Memory for channelized interfaces 0", 1759 /* EGQ_CH_SCM_1 */ "Shaper Calendar Memory for channelized interface 1", 1760 /* EGQ_CH_SCM_2 */ "Shaper Calendar Memory for channelized interface 2", 1761 /* EGQ_CH_SCM_3 */ "Shaper Calendar Memory for channelized interface 3", 1762 /* EGQ_CH_SCM_4 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1763 /* EGQ_CH_SCM_5 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1764 /* EGQ_CH_SCM_6 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1765 /* EGQ_CH_SCM_7 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1766 /* EGQ_CH_SCM_8 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1767 /* EGQ_CH_SCM_9 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1768 /* EGQ_CH_SCM_10 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1769 /* EGQ_CH_SCM_11 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1770 /* EGQ_CH_SCM_12 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1771 /* EGQ_CH_SCM_13 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1772 /* EGQ_CH_SCM_14 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1773 /* EGQ_CH_SCM_15 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1774 /* EGQ_CH_SCM_16 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1775 /* EGQ_CH_SCM_17 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1776 /* EGQ_CH_SCM_18 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1777 /* EGQ_CH_SCM_19 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1778 /* EGQ_CH_SCM_20 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1779 /* EGQ_CH_SCM_21 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1780 /* EGQ_CH_SCM_22 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1781 /* EGQ_CH_SCM_23 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1782 /* EGQ_CH_SCM_24 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1783 /* EGQ_CH_SCM_25 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1784 /* EGQ_CH_SCM_26 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1785 /* EGQ_CH_SCM_27 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1786 /* EGQ_CH_SCM_28 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1787 /* EGQ_CH_SCM_29 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1788 /* EGQ_CH_SCM_30 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1789 /* EGQ_CH_SCM_31 */ "Shaper Calendar Memories for channelized interfaces 4 to 31.", 1790 /* EGQ_CNM_QUANTA_TO_FC_MAP */ "CnmQuantaToFcMap", 1791 /* EGQ_CRM */ "CRC16 Reminder Memory", 1792 /* EGQ_DCM */ "This table contains the number of descriptors stored in each queue in PQP. In dex to the table is queue number in range 0 to 511.", 1793 /* EGQ_DFM */ "Delete Queue FIFO", 1794 /* EGQ_DPM */ "TC- Cast WFQ scheduler counters memory.", 1795 /* EGQ_DPM_8P */ "EIR WFQ scheduler counters memory.", 1796 /* EGQ_DSP_PTR_MAP */ "The PP-DSP parameter for unicast packet is received from FTMH header, while for Egress multicast copy its generated by the multicast replication machine.\n This table maps the PP-DSP field to the following parameters:\n Out-TM-Port\n Out-PP-Port\n Destination-System-Port", 1797 /* EGQ_DWM */ "The table contains 256 entries, one entry per Q-Pair. Each entry defines the weights of the UC and MC queues connected to this Q-Pair. Weight of 0 for one queue indicates that this qyeye has SP over the other. When both have equal weights, this implies simple RR. Maximum weight difference is 255:1.\n Rate Calculation:\n UC rate = (Q-Pair rate) * (MC weight) / (UC weight + MC weight)\n MC rate = (Q-Pair rate) * (UC weight) / (UC weight + MC weigh ...", 1798 /* EGQ_DWM_8P */ "The table consist from 32 entries, one entry per Port Scheduler (group of 8 Q-Pairs). Defines the weights of the 8 traffic class groups (TCG) connected to this scheduler. Enables WFQ and SP relation between the 8 TCGs. Weight of 0 for a class indicates that this class has SP over the other classes. When all have equal weights, this implies simple RR. Maximum weight difference is 255:1. the lower the rate the higher the bandwidth.\n Rate Calculation:\n TCG(i) rat ...", 1799 /* EGQ_EGRESS_SHAPER_CONFIGURATION */ "Egress Shaper Confgiuration.\n Entries 0-31 refer to Shaper Calendars 0-31.\n Entry 32 refers to Non-chanelized Shaper Calendar Memory.\n Entry 33 refers to Q-Pairs Shaper Calendar Memory.\n Entry 34 refers to TCGs Shaper Calendar Memory.", 1800 /* EGQ_EOPM */ "RCM EOP master counter", 1801 /* EGQ_EOPS */ "RCM EOP slave counter", 1802 /* EGQ_EPS_PRIO_MAP */ "Mapping each priority (Q-pair) to TCG.\n This table contains 32 entries. One entry per Port Scheduler (a queue group of 8 Q-Pairs).\n Each queue group is configured by PsMode register as either:\n One Eight-Priority ETM-Port (8P-Port)\n Four Two-Priority ETM-Ports (2P-Port)\n Eight One-Priority ETM-Ports (1P-Port)\n This register is relevant only when the corresponding queue group is working ...", 1803 /* EGQ_FBM */ "Represents the dynamic status of the EGQ 12K Buffers. Each entry represents a bitmap of 64 buffers indicating, per buffer, whether it is free or occupied.", 1804 /* EGQ_FCM */ "RCM Free Context Memory", 1805 /* EGQ_FDCM */ "Packet descriptors per Interface", 1806 /* EGQ_FDCMAX */ "DCM-MAX - maximum packet descriptors per Interface.", 1807 /* EGQ_FDM */ "Represents the dynamic status of the EGQ 32K Descriptors. Each entry represents a bitmap of 128 packet descriptors indicating, per descriptor, whether it is free or occupied.", 1808 /* EGQ_FQP_NIF_PORT_MUX */ "Round robin for NIF ports in NIF ports scheduler.", 1809 /* EGQ_FQSM */ "FQSM - DBS per Interface Memory.", 1810 /* EGQ_FQSMAX */ "FQSM-MAX - maximum data buffers per interface Memory.", 1811 /* EGQ_FRM */ "FDA RXI Memory", 1812 /* EGQ_HEADER_MAP */ "This table is used when the system works in Petra FTMH system header format mode.\n The table is used to select the source of the parser records fields from different location in packet system header.", 1813 /* EGQ_IVEC_TABLE */ "Ingress VLAN editing command.\n This table has 64 entries. It is pointed by FHEI.Ingress-VLAN-Edit-Command", 1814 /* EGQ_LRM */ "Local interafce (TXQ) RXI Memory", 1815 /* EGQ_MAP_OUTLIF_TO_DSP */ "Egress Replication Database Entry Formats 6 and 7, generate up to three copies, each with unique OutLIF. The PP-DSP is generated by mapping the OutLIF through this table.\n The index to the table is OutLif (16 bits) and the result is PP-DSP corresponding to the OutLif.", 1816 /* EGQ_MAP_PS_TO_IFC */ "Mapping for each Egress interface the Port Schedulers (queue group of 8 Q-Pairs) which belong to it.\n The index to this table is the egress intercae number according to the following encoding:\n 0-27 - NIF ports 0-27, 28- Cmic, 29 - OLP, 30 - OAM and 31 - RCY.\n The result is 32 bits bitamp represnts the Port Schedulers which mapped to the corresponding interface.", 1817 /* EGQ_MC_1_FIFO */ "Multicast Class 1 FIFO descriptors", 1818 /* EGQ_MC_2_FIFO */ "Multicast Class 2 FIFO descriptors", 1819 /* EGQ_MC_BITMAP_MAPPING */ "Mapping Bitmap location to DSP-PTR(8).", 1820 /* EGQ_MC_ENQ_FIFO */ "Multicast Copies Enqueue FIFO of descriptors.", 1821 /* EGQ_MC_SP_TC_MAP */ "RQP should drop MC packets based on data buffers consumption. The decision whether to drop a packet or forward it is resolved by the CGM block that passes the indication to the RQP. The RQP map SYS-TC2:0SYS-DP1:0 to CGM-SP(1),CGM-SE(2),CGM-TC(3) and forward them to the CGM.", 1822 /* EGQ_NONCH_SCM */ "Non-chanelized Shaper Calendar Memory", 1823 /* EGQ_PCM */ "Packed Cell Memory", 1824 /* EGQ_PCP_DEI_DP_MAPPING_TABLE */ "PCP-DEI Mapping Table for IVE, maps DP+INLIF_Profile+Selected_PCP_DEI to new PCP-DEI", 1825 /* EGQ_PCT */ "Per Port Configuration Table. This table contains 256 entries. The address to this table is Q-Pair number.\n If SpecialFlowControl is set, then the address is as following:\n 1. Entries 0-7 corresponding to OTM-Port 0 UC queues.\n 2. Entries 8-15 corresponding to OTM-Port 8 UC queues.\n 3. Entries 16-23 correspoinding to OTM-Port 0 MC queues.\n 4. Entries 24-31 corresponding to OTM-Port 8 MC queues.\n ...", 1826 /* EGQ_PDCM */ "Unicast and Multicast packet descriptors counters per OTM-Port Memory.", 1827 /* EGQ_PDCMAX */ "PDCM-MAX - maximum unicast and multicast packet descriptors per OTM-Port Memory.", 1828 /* EGQ_PDCT_TABLE */ "This memory defines per OTM-Port-Profile the thresholds related to packet descriptors tests in CGM.", 1829 /* EGQ_PDM */ "packet descriptors memory", 1830 /* EGQ_PER_IFC_CFG */ "Per EGQ interface configuration in FQP. The FQP (Transmit queues) block maintains a queue per interface (124 NIF ports, Cmic, OLP, OAM and RCY).", 1831 /* EGQ_PER_PORT_LB_RANGE */ "Second Load-Blanace range for each OTM-Port. The first range is defines in PPCT table.", 1832 /* EGQ_PLM */ "packet link memory", 1833 /* EGQ_PMC */ "Per Port Maxmimum Credits Balance.\n Each entry holds the maximum credit balance that the OFP can accumulate, indicating the burst size of the OFP. Each entry associated with OFP.", 1834 /* EGQ_PMF_KEY_GEN_LSB */ "Program Instruction Table per program for all 4 keys LSB for instructions 5-7", 1835 /* EGQ_PMF_KEY_GEN_MSB */ "Program Instruction Table per program for all 4 keys MSB for instructions 1-4", 1836 /* EGQ_PMF_PROGRAM_SELECTION_CAM */ "Value: 150h0 Mask: 150h0", 1837 /* EGQ_PMF_P_7_FIFO */ "Pipe-FIFO", 1838 /* EGQ_PPCT */ "Per OTM-Port Configuration Table, allowing configuring port-related features for each one of the 256 ports. Each address corresponds with a port, with identical fields definitions per entry.", 1839 /* EGQ_PP_PPCT */ "Per PP-Port packet processing configuration table, allowing configuring port-related PP features for each one of the 256 ports. Each address corresponds with a port, with identical fields definitions per entry.", 1840 /* EGQ_PQP_NIF_PORT_MUX */ "Round robin for egress interfaces in interface selection scheduler in EPS", 1841 /* EGQ_PQSM */ "Unicast and Multicast consumed data buffers counters per OTM-Port.", 1842 /* EGQ_PQSMAX */ "PQSM-MAX - maximum unicast and multicast DBs per OTM-Port Memory.", 1843 /* EGQ_PQST_TABLE */ "Data buffers thresholds per Otm-Port-Profile table.\n This memory defines per OTM-Port-Profile the thresholds related to data buffers tests per OTM-Port in CGM.", 1844 /* EGQ_QDCM */ "Packet descriptors per queue Memory.", 1845 /* EGQ_QDCMAX */ "DCM-MAX - maximum packet descriptors per queue Memory.", 1846 /* EGQ_QDCT_TABLE */ "PDs thresholds per queue table. The index to this table is CGM-PORT-PROFILE(4),Egress-Tc(3). The result is set of thresholds corresponding to per queue resources.", 1847 /* EGQ_QM_0 */ "OFPs Queue FIFOs memory used for buffering the FQP descriptors.", 1848 /* EGQ_QM_1 */ "OFPs Queue FIFOs memory used for buffering the FQP descriptors.", 1849 /* EGQ_QM_2 */ "OFPs Queue FIFOs memory used for buffering the FQP descriptors.", 1850 /* EGQ_QM_3 */ "OFPs Queue FIFOs memory used for buffering the FQP descriptors.", 1851 /* EGQ_QP_CBM */ "Credit Balance Memory. This memory holds the credit balance per Q-Pair.", 1852 /* EGQ_QP_PMC */ "Per Q-Pair Maxmimum Credits Balance.\n Each entry holds the maximum credit balance that the Q-Pair can accumulate, indicating the burst size of the Q-Pair. Each entry associated with Q-Pair.", 1853 /* EGQ_QP_SCM */ "Q-Pairs Shaper Calendar Memory.", 1854 /* EGQ_QQSM */ "QQSM - DBS per Queue Memory.", 1855 /* EGQ_QQSMAX */ "QQSM-MAX - maximum data buffers per queue Memory.", 1856 /* EGQ_QQST_TABLE */ "Data buffers thresholds per queue table.", 1857 /* EGQ_RCM */ "Reassembly contexts memory allocation used for fabric primary pipe traffic. Index to this memory is FAB_PIPE_ID1:0 & FAP ID10:0\n The reassembly contexts allocation mode in the Fabric primary interface, may be one from the following options, according to RcmPrimaryMode register:\n 0 - Static allocation mode, in this mode reassembly context is feagured from the FAP_ID9:0 and context mask + base address.\n 1 - Semi-dynamic allocation mode, RQP con ...", 1858 /* EGQ_RCMMC */ "Reassembly contexts memory allocation used for fabric secondary pipe traffic. Index to this memory is FAP ID10:0\n The reassembly contexts allocation mode in the Fabric secondary interface, may be one from the following options, according to RcmSecondaryMode register:\n 0 - Static allocation mode, in this mode reassembly context equals to FAP_ID7:0. in this mode, this memory is not in use.\n 1 - Semi-dynamic allocation mode, RQP context is detrm ...", 1859 /* EGQ_RCMUC */ "Reassembly contexts memory allocation used for fabric primary pipe traffic. Index to this memory is FAP ID10:0\n The reassembly contexts allocation mode in the Fabric primary interface, may be one from the following options, according to RcmPrimaryMode register:\n 0 - Static allocation mode, in this mode reassembly context equals to FAP_ID7:0/8:0. in this mode, this memory is not in use.\n 1 - Semi-dynamic allocation mode, RQP context is detrmin ...", 1860 /* EGQ_RCNT */ "Read Counter Memory", 1861 /* EGQ_RDM */ "read desc memory", 1862 /* EGQ_RDMMC */ "RQP segment reassembly descriptors used for VSC256 Secondary pipe traffic.\n Index is reassembly context.", 1863 /* EGQ_RDMUC */ "RQP segment reassembly descriptors used for VSC256 Primary pipe traffic.\n Index is reassembly context.", 1864 /* EGQ_RPDM */ "RQP Packet reassembly descriptors (PRP)", 1865 /* EGQ_RPDMHDR */ "Packet reassembly descriptors for packet header(PRP)", 1866 /* EGQ_RRDM */ "RQP Segment reassembly descriptors (FSR) used for VSC128 traffic", 1867 /* EGQ_RSM */ "Cell Unpack Reassembly Memory (state)", 1868 /* EGQ_SEGM */ "Segment Memory for EGQ0.", 1869 /* EGQ_SOPM */ "RCM SOP master counter + context", 1870 /* EGQ_SOPS */ "RCM SOP slave counter", 1871 /* EGQ_TCG_CBM */ "Credit Balance Memory. This memory holds the credit balance per TCG.", 1872 /* EGQ_TCG_PMC */ "Per TCG Maxmimum Credits Balance.\n Each entry holds the maximum credit balance that the TCG can accumulate, indicating the burst size of the TCG. Each entry associated with TCG.", 1873 /* EGQ_TCG_SCM */ "TCG Shaper Calendar Memory.", 1874 /* EGQ_TC_DP_MAP */ "Lookup table used to map Port-COS-Map-Profile(3), Egress-MC(1), SYS-TC(3),SYS-DP(2) to the following parameters: Egress-TC(3) and CGM-MC-DP(2).\n The Egress-TC + Base-Queue-Num determines the final queue number the packet will be enqueued to it.", 1875 /* EGQ_TSM */ "TDM (in PRP) Segment Memory", 1876 /* EGQ_TTL_SCOPE */ "For each packet, a range of allowed TTL values is defined. There are eight such TTL values, each of them 8b, and this table attaches each VSI with the allowed TTL scope values.\n The eight TTL scope values are defined in Ttl Scope.Each entry in this table configures eight consecutive VSI entries.", 1877 /* EGQ_UCFIFO */ "EHP Unicast FIFO Descriptors", 1878 /* EGQ_USM */ "Unpacked Segment Memory", 1879 /* EGQ_USMFTMH */ "Unpacked Segment Memory", 1880 /* EGQ_VLAN_TABLE */ "Vlan Membership Table. This table contains 8K entries. Used in egress multicast in bitmap mode.", 1881 /* EGQ_VSI_MEMBERSHIP */ "VSI membership table configuration table, correlating each OTM port with a VSI. Each address corresponds with a VSI (0 through 4095), with identical fields definitions per entry.", 1882 /* EGQ_VSI_PROFILE */ "This table sets for each VSI an action profile. There are four such profiles. Each entry in this table configures sixteen consecutive VSI profile entries.", 1883 /* EGQ_WDM */ "write desc memory", 1884 /* EGR_1588_SA */ "1588 Protocol Control table", 1885 /* EGR_ADAPT_1_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table(EGR_ADAPT1).", 1886 /* EGR_ADAPT_1_FIXED_KEY_TABLE_ATTRS */ "Contains fixed key type attributes.", 1887 /* EGR_ADAPT_1_KEY_GEN_1_MASK */ "EGR_ADAPT_1 : Lookup1 key mask", 1888 /* EGR_ADAPT_1_KEY_GEN_1_MASK_PIPE0 */ "EGR_ADAPT_1 : Lookup1 key mask", 1889 /* EGR_ADAPT_1_KEY_GEN_1_MUX_CTRL */ "EGR_ADAPT_1 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 1890 /* EGR_ADAPT_1_KEY_GEN_1_MUX_CTRL_PIPE0 */ "EGR_ADAPT_1 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 1891 /* EGR_ADAPT_1_KEY_GEN_2_MASK */ "EGR_ADAPT_1 :Lookup2 key mask", 1892 /* EGR_ADAPT_1_KEY_GEN_2_MASK_PIPE0 */ "EGR_ADAPT_1 :Lookup2 key mask", 1893 /* EGR_ADAPT_1_KEY_GEN_2_MUX_CTRL */ "EGR_ADAPT_1: Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 1894 /* EGR_ADAPT_1_KEY_GEN_2_MUX_CTRL_PIPE0 */ "EGR_ADAPT_1: Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 1895 /* EGR_ADAPT_1_LOGICAL_TBL_SEL_SRAM */ "EGR_ADAPT_1 : Flex key lookup control sram", 1896 /* EGR_ADAPT_1_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "EGR_ADAPT_1 : Flex key lookup control sram", 1897 /* EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM */ "EGR_ADAPT_1 : Key Selection TCAM", 1898 /* EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "EGR_ADAPT_1 : Key Selection TCAM", 1899 /* EGR_ADAPT_1_MISS_POLICY */ "When there is a miss in the EGR_ADAPT_1 (VXLT_1) table, then the MISS_POLICY_IDX from the FlexKey control sram or the EGR_ADAPT_1_FIXED_KEY_TABLE_ATTRS is used to lookup this table to provide the policy data for this miss condition.", 1900 /* EGR_ADAPT_1_POLICY_STRENGTH_PROFILE */ "Contains bitmap of the actions generated by the associated table.", 1901 /* EGR_ADAPT_2_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table(EGR_ADAPT1).", 1902 /* EGR_ADAPT_2_FIXED_KEY_TABLE_ATTRS */ "Contains fixed key type attributes.", 1903 /* EGR_ADAPT_2_KEY_GEN_1_MASK */ "EGR_VLAN_SLATE_2 : Lookup1 key mask", 1904 /* EGR_ADAPT_2_KEY_GEN_1_MASK_PIPE0 */ "EGR_VLAN_SLATE_2 : Lookup1 key mask", 1905 /* EGR_ADAPT_2_KEY_GEN_1_MUX_CTRL */ "EGR_ADAPT_2 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 1906 /* EGR_ADAPT_2_KEY_GEN_1_MUX_CTRL_PIPE0 */ "EGR_ADAPT_2 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 1907 /* EGR_ADAPT_2_KEY_GEN_2_MASK */ "EGR_ADAPT_2 : Lookup2 key mask", 1908 /* EGR_ADAPT_2_KEY_GEN_2_MASK_PIPE0 */ "EGR_ADAPT_2 : Lookup2 key mask", 1909 /* EGR_ADAPT_2_KEY_GEN_2_MUX_CTRL */ "EGR_ADAPT_2 : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 1910 /* EGR_ADAPT_2_KEY_GEN_2_MUX_CTRL_PIPE0 */ "EGR_ADAPT_2 : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 1911 /* EGR_ADAPT_2_LOGICAL_TBL_SEL_SRAM */ "EGR_ADAPT_2: Flex key lookup control sram", 1912 /* EGR_ADAPT_2_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "EGR_ADAPT_2: Flex key lookup control sram", 1913 /* EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM */ "EGR_ADAPT_2 : Key Selection TCAM", 1914 /* EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "EGR_ADAPT_2 : Key Selection TCAM", 1915 /* EGR_ADAPT_2_MISS_POLICY */ "When there is a miss in the EGR_ADAPT_2 (VXLT_2) table, then the MISS_POLICY_IDX from the FlexKey control sram or the EGR_ADAPT_2_FIXED_KEY_TABLE_ATTRS is used to lookup this table to provide the policy data for this miss condition.", 1916 /* EGR_ADAPT_2_POLICY_STRENGTH_PROFILE */ "Contains bitmap of the actions generated by the associated table.", 1917 /* EGR_AXP_PORT_PROPERTY */ "Indexed by the Loopback Type", 1918 /* EGR_COS_MAP */ "Egress COS MAP Table for the Redirect COS queue", 1919 /* EGR_COUNTER_CONTROL */ "Specifies control fields Egress for the MMU Counters and Meters.", 1920 /* EGR_CPU_COS_MAP */ "Egress CPU COS MAP Table for the Redirect COS queue", 1921 /* EGR_DELETE_CONTROL */ "This block generates part of the OFFSET_CTRL_ID to the packet editor in the namespace of the ingress packet.", 1922 /* EGR_DGPP_TO_NHI */ "Maps DGPP to a next hop index.", 1923 /* EGR_DGPP_TO_NHI_MODBASE */ "Modid-based pointer to EGR_DGPP_TO_NHI table.", 1924 /* EGR_DNX_HEADER */ "This table provides a 30-Byte default value for DNX Header Initialization. Some fields which vary with session can be overridden (captured in SAT Header Map document).", 1925 /* EGR_DOP_STORAGE_MEM */ "used to store DOP-data", 1926 /* EGR_DOP_STORAGE_MEM_PIPE0 */ "used to store DOP-data", 1927 /* EGR_DOP_STORAGE_MEM_PIPE1 */ "used to store DOP-data", 1928 /* EGR_DSCP_ECN_MAP */ "Egress DSCP Table to select the new dscp for outer tunnel header packets.", 1929 /* EGR_DSCP_TABLE */ "Egress DSCP Table to select the new dscp for outer tunnel header packets.", 1930 /* EGR_DVP_ATTRIBUTE */ "Egress DVP Attribute Table, FeatureSpecific-Ethernet.", 1931 /* EGR_DVP_ATTRIBUTE_1 */ "Egress DVP Attribute_1 Table, FeatureSpecific-Ethernet.", 1932 /* EGR_DVP_ATTRIBUTE_ACTION_MASK_PROFILE */ "EGR_DVP_ATTRIBUTE Action Mask Profile table", 1933 /* EGR_DVP_ATTRIBUTE_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table(EGR_DVP_ATTRIBUTE).", 1934 /* EGR_DVP_ATTRIBUTE_EARLY_ACTION_PROFILE */ "Contains bitmap of the EARLY actions generated by the associated table(EGR_DVP_ATTRIBUTE).", 1935 /* EGR_ECN_COUNTER */ "Number of packets transmitted from this port with ECN error.", 1936 /* EGR_EDB_XMIT_CTRL */ "Egress transmission control", 1937 /* EGR_EFFECTIVE_PHB_SELECT */ "This table is used to select 3x Effective PHB & CNG that is fed to Flex Counter as Packet Attribute and is used as Flex Counter Offset", 1938 /* EGR_EHG_QOS_MAPPING_TABLE */ "Maps internal priority / CFI to DSCP and VLAN priority/CFI", 1939 /* EGR_EINITBUF_DATA_RAM_0 */ "Used only for Debug purposes: INITBUF [255:0].There should not be any packet traffic in EP when CPU is accessing this table.Else data integrity cannot be guaranteed.", 1940 /* EGR_EINITBUF_DATA_RAM_1 */ "Used only for Debug purposes: INITBUF [511:256] .There should not be any packet traffic in EP when CPU is accessing this table.Else data integrity cannot be guaranteed.", 1941 /* EGR_EINITBUF_DATA_RAM_2 */ "Used only for Debug purposes: INITBUF [767:512] .There should not be any packet traffic in EP when CPU is accessing this table.Else data integrity cannot be guaranteed.", 1942 /* EGR_EINITBUF_DATA_RAM_3 */ "Used only for Debug purposes: INITBUF [1023:768] .There should not be any packet traffic in EP when CPU is accessing this table.Else data integrity cannot be guaranteed.", 1943 /* EGR_EINITBUF_ECC_RAM */ "Used only for Debug purposes: INITBUF ECC .There should not be any packet traffic in EP when CPU is accessing this table.Else data integrity cannot be guaranteed.", 1944 /* EGR_EM_MTP_INDEX */ "Mirror to Port Table.\nIndex is constructed using pbe.mtp_index[6:0] field.\nWe use {pbe.mtp_index[5:4],pbe.mtp_index[2:0]} as index into this table.", 1945 /* EGR_ENABLE */ "Egress Enable (per physical port)", 1946 /* EGR_EP_REDIRECT_EM_MTP_INDEX */ "Mirror to Port Table.\nIndex is constructed using pbe.mtp_index[6:0] field.\nWe use {pbe.mtp_index[5:4],pbe.mtp_index[2:0]} as index into this table.", 1947 /* EGR_ERSPAN */ "Contains the ERSPAN header for each MTP (first 4 for IM_MTPs, second 4 entries for EM_MTPs; address::: for IM copy: {0, IM_MTP_INDEX[4:3]} for EM copy: {1, EM_MTP_INDEX[4:3]}. Note: ERSPAN is not supported in Draco Mirror mode.", 1948 /* EGR_ETAG_PCP_MAPPING */ "Mapping table for Internal Priority and CNG to ETAG PCP/DE.", 1949 /* EGR_EXP_TO_INT_CN_MAPPING_TABLE */ "Map MPLS EXP to INT_CN. Used at ingress chip of MPLS encapsulations.", 1950 /* EGR_FCOE_CONTROL_1 */ "Per-chip control.", 1951 /* EGR_FC_HEADER_TYPE */ "FCoE Header Type.", 1952 /* EGR_FIELD_EXTRACTION_PROFILE_1_TCAM */ "TCAM that allows the Ingress pipeline to drive field extraction in the Egress pipeline.", 1953 /* EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_DATA_ONLY */ "Policy Table which allows the ingress pipeline to drive the field extraction in the Egress pipeline. Provides the extraction profile ID that is used by the HFE.", 1954 /* EGR_FIELD_EXTRACTION_PROFILE_1_TCAM_ONLY */ "TCAM that allows the Ingress pipeline to drive field extraction in the Egress pipeline.", 1955 /* EGR_FIELD_EXTRACTION_PROFILE_2_TCAM */ "TCAM that allows the Ingress pipeline to drive field extraction in the Egress pipeline.", 1956 /* EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_DATA_ONLY */ "Policy Table which allows the ingress pipeline to drive the field extraction in the Egress pipeline. Provides the extraction profile ID that is used by the HFE.", 1957 /* EGR_FIELD_EXTRACTION_PROFILE_2_TCAM_ONLY */ "TCAM that allows the Ingress pipeline to drive field extraction in the Egress pipeline.", 1958 /* EGR_FIELD_EXTRACTION_PROFILE_CONTROL */ "The control selects which HFE_HVE_PROFILE_PTR should be used from EGR_ZONE_x_MATCH_ID_ATTR table for zone field extraction.", 1959 /* EGR_FLEX_CONTAINER_UPDATE_PROFILE_0 */ "For Multi-Domain Filter check feature .", 1960 /* EGR_FLEX_CONTAINER_UPDATE_PROFILE_1 */ "For Multi-Domain Filter check feature .", 1961 /* EGR_FLEX_CTR_COS_MAP */ "This table is used to map packet MMU_COS and UNICAST_QUEUING bit to compressed values to count using flex counter.", 1962 /* EGR_FLEX_CTR_COUNTER_TABLE_0 */ "Counter Table for flexible counter updates", 1963 /* EGR_FLEX_CTR_COUNTER_TABLE_1 */ "Counter Table for flexible counter updates", 1964 /* EGR_FLEX_CTR_COUNTER_TABLE_2 */ "Counter Table for flexible counter updates", 1965 /* EGR_FLEX_CTR_COUNTER_TABLE_3 */ "Counter Table for flexible counter updates", 1966 /* EGR_FLEX_CTR_COUNTER_TABLE_4 */ "Counter Table for flexible counter updates", 1967 /* EGR_FLEX_CTR_COUNTER_TABLE_5 */ "Counter Table for flexible counter updates", 1968 /* EGR_FLEX_CTR_COUNTER_TABLE_6 */ "Counter Table for flexible counter updates", 1969 /* EGR_FLEX_CTR_COUNTER_TABLE_7 */ "Counter Table for flexible counter updates", 1970 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE0 */ "Counter Table for flexible counter updates", 1971 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE1 */ "Counter Table for flexible counter updates", 1972 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE2 */ "Counter Table for flexible counter updates", 1973 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE3 */ "Counter Table for flexible counter updates", 1974 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE4 */ "Counter Table for flexible counter updates", 1975 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE5 */ "Counter Table for flexible counter updates", 1976 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE6 */ "Counter Table for flexible counter updates", 1977 /* EGR_FLEX_CTR_COUNTER_TABLE_0_PIPE7 */ "Counter Table for flexible counter updates", 1978 /* EGR_FLEX_CTR_COUNTER_TABLE_0_X */ "Counter Table for flexible counter updates", 1979 /* EGR_FLEX_CTR_COUNTER_TABLE_0_Y */ "Counter Table for flexible counter updates", 1980 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE0 */ "Counter Table for flexible counter updates", 1981 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE1 */ "Counter Table for flexible counter updates", 1982 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE2 */ "Counter Table for flexible counter updates", 1983 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE3 */ "Counter Table for flexible counter updates", 1984 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE4 */ "Counter Table for flexible counter updates", 1985 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE5 */ "Counter Table for flexible counter updates", 1986 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE6 */ "Counter Table for flexible counter updates", 1987 /* EGR_FLEX_CTR_COUNTER_TABLE_1_PIPE7 */ "Counter Table for flexible counter updates", 1988 /* EGR_FLEX_CTR_COUNTER_TABLE_1_X */ "Counter Table for flexible counter updates", 1989 /* EGR_FLEX_CTR_COUNTER_TABLE_1_Y */ "Counter Table for flexible counter updates", 1990 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE0 */ "Counter Table for flexible counter updates", 1991 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE1 */ "Counter Table for flexible counter updates", 1992 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE2 */ "Counter Table for flexible counter updates", 1993 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE3 */ "Counter Table for flexible counter updates", 1994 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE4 */ "Counter Table for flexible counter updates", 1995 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE5 */ "Counter Table for flexible counter updates", 1996 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE6 */ "Counter Table for flexible counter updates", 1997 /* EGR_FLEX_CTR_COUNTER_TABLE_2_PIPE7 */ "Counter Table for flexible counter updates", 1998 /* EGR_FLEX_CTR_COUNTER_TABLE_2_X */ "Counter Table for flexible counter updates", 1999 /* EGR_FLEX_CTR_COUNTER_TABLE_2_Y */ "Counter Table for flexible counter updates", 2000 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE0 */ "Counter Table for flexible counter updates", 2001 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE1 */ "Counter Table for flexible counter updates", 2002 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE2 */ "Counter Table for flexible counter updates", 2003 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE3 */ "Counter Table for flexible counter updates", 2004 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE4 */ "Counter Table for flexible counter updates", 2005 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE5 */ "Counter Table for flexible counter updates", 2006 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE6 */ "Counter Table for flexible counter updates", 2007 /* EGR_FLEX_CTR_COUNTER_TABLE_3_PIPE7 */ "Counter Table for flexible counter updates", 2008 /* EGR_FLEX_CTR_COUNTER_TABLE_3_X */ "Counter Table for flexible counter updates", 2009 /* EGR_FLEX_CTR_COUNTER_TABLE_3_Y */ "Counter Table for flexible counter updates", 2010 /* EGR_FLEX_CTR_OFFSET_TABLE_0 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2011 /* EGR_FLEX_CTR_OFFSET_TABLE_1 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2012 /* EGR_FLEX_CTR_OFFSET_TABLE_2 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2013 /* EGR_FLEX_CTR_OFFSET_TABLE_3 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2014 /* EGR_FLEX_CTR_OFFSET_TABLE_4 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2015 /* EGR_FLEX_CTR_OFFSET_TABLE_5 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2016 /* EGR_FLEX_CTR_OFFSET_TABLE_6 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2017 /* EGR_FLEX_CTR_OFFSET_TABLE_7 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 2018 /* EGR_FLEX_CTR_PKT_PRI_MAP */ "PKT_PRI_MAP", 2019 /* EGR_FLEX_CTR_PKT_RES_MAP */ "PKT_RES_MAP", 2020 /* EGR_FLEX_CTR_PORT_MAP */ "PORT_MAP", 2021 /* EGR_FLEX_CTR_PRI_CNG_MAP */ "PRI_CNG_MAP", 2022 /* EGR_FLEX_CTR_TOS_MAP */ "TOS_MAP", 2023 /* EGR_FLEX_PREEMPT_START_LOOKUP0 */ "Egress EDB Flex Preemption Start Action Lookup", 2024 /* EGR_FLEX_PREEMPT_START_LOOKUP1 */ "Egress EDB Flex Preemption Start Action Lookup", 2025 /* EGR_FLEX_PREEMPT_START_LOOKUP2 */ "Egress EDB Flex Preemption Start Action Lookup", 2026 /* EGR_FLEX_PREEMPT_START_LOOKUP3 */ "Egress EDB Flex Preemption Start Action Lookup", 2027 /* EGR_FLEX_PREEMPT_START_LOOKUP4 */ "Egress EDB Flex Preemption Start Action Lookup", 2028 /* EGR_FLEX_PREEMPT_START_LOOKUP5 */ "Egress EDB Flex Preemption Start Action Lookup", 2029 /* EGR_FLEX_PREEMPT_START_LOOKUP6 */ "Egress EDB Flex Preemption Start Action Lookup", 2030 /* EGR_FLEX_PREEMPT_START_LOOKUP7 */ "Egress EDB Flex Preemption Start Action Lookup", 2031 /* EGR_FLEX_PREEMPT_START_LOOKUP8 */ "Egress EDB Flex Preemption Start Action Lookup", 2032 /* EGR_FLEX_PREEMPT_START_LOOKUP9 */ "Egress EDB Flex Preemption Start Action Lookup", 2033 /* EGR_FLEX_PREEMPT_START_LOOKUP10 */ "Egress EDB Flex Preemption Start Action Lookup", 2034 /* EGR_FLEX_PREEMPT_START_LOOKUP11 */ "Egress EDB Flex Preemption Start Action Lookup", 2035 /* EGR_FLEX_PREEMPT_START_LOOKUP12 */ "Egress EDB Flex Preemption Start Action Lookup", 2036 /* EGR_FLEX_PREEMPT_START_LOOKUP13 */ "Egress EDB Flex Preemption Start Action Lookup", 2037 /* EGR_FLEX_PREEMPT_START_LOOKUP14 */ "Egress EDB Flex Preemption Start Action Lookup", 2038 /* EGR_FLEX_PREEMPT_START_LOOKUP15 */ "Egress EDB Flex Preemption Start Action Lookup", 2039 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP0 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2040 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP1 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2041 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP2 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2042 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP3 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2043 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP4 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2044 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP5 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2045 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP6 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2046 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP7 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2047 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP8 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2048 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP9 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2049 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP10 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2050 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP11 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2051 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP12 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2052 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP13 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2053 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP14 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2054 /* EGR_FLEX_PREEMPT_TERMINATE_LOOKUP15 */ "Egress EDB Flex Preemption Terminate Action Lookup", 2055 /* EGR_FLEX_PREEMPT_XFR_COUNT0 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2056 /* EGR_FLEX_PREEMPT_XFR_COUNT1 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2057 /* EGR_FLEX_PREEMPT_XFR_COUNT2 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2058 /* EGR_FLEX_PREEMPT_XFR_COUNT3 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2059 /* EGR_FLEX_PREEMPT_XFR_COUNT4 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2060 /* EGR_FLEX_PREEMPT_XFR_COUNT5 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2061 /* EGR_FLEX_PREEMPT_XFR_COUNT6 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2062 /* EGR_FLEX_PREEMPT_XFR_COUNT7 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2063 /* EGR_FLEX_PREEMPT_XFR_COUNT8 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2064 /* EGR_FLEX_PREEMPT_XFR_COUNT9 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2065 /* EGR_FLEX_PREEMPT_XFR_COUNT10 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2066 /* EGR_FLEX_PREEMPT_XFR_COUNT11 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2067 /* EGR_FLEX_PREEMPT_XFR_COUNT12 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2068 /* EGR_FLEX_PREEMPT_XFR_COUNT13 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2069 /* EGR_FLEX_PREEMPT_XFR_COUNT14 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2070 /* EGR_FLEX_PREEMPT_XFR_COUNT15 */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 2071 /* EGR_FORCE_REGEN_CRC_DST */ "Force regen CRC per logical destination port", 2072 /* EGR_FORCE_REGEN_CRC_SRC */ "Force regen CRC per logical source port", 2073 /* EGR_FRAGMENT_ID_TABLE */ "IPv4 / CAPWAP Tunnel Fragment ID Table", 2074 /* EGR_FRAGMENT_ID_TABLE_PIPE0 */ "IPv4 Tunnel Fragment ID Table.", 2075 /* EGR_FRAGMENT_ID_TABLE_PIPE1 */ "IPv4 Tunnel Fragment ID Table.", 2076 /* EGR_FRAGMENT_ID_TABLE_PIPE2 */ "IPv4 Tunnel Fragment ID Table.", 2077 /* EGR_FRAGMENT_ID_TABLE_PIPE3 */ "IPv4 Tunnel Fragment ID Table.", 2078 /* EGR_FRAGMENT_ID_TABLE_PIPE4 */ "IPv4 Tunnel Fragment ID Table.", 2079 /* EGR_FRAGMENT_ID_TABLE_PIPE5 */ "IPv4 Tunnel Fragment ID Table.", 2080 /* EGR_FRAGMENT_ID_TABLE_PIPE6 */ "IPv4 Tunnel Fragment ID Table.", 2081 /* EGR_FRAGMENT_ID_TABLE_PIPE7 */ "IPv4 Tunnel Fragment ID Table.", 2082 /* EGR_FRAGMENT_ID_TABLE_X */ "IPv4 Tunnel Fragment ID Table.", 2083 /* EGR_FRAGMENT_ID_TABLE_Y */ "IPv4 Tunnel Fragment ID Table.", 2084 /* EGR_GPP_ATTRIBUTES */ "Per-GPP attributes table, PORT view.", 2085 /* EGR_GPP_ATTRIBUTES_MODBASE */ "Per-GPP attributes MODBASE table.", 2086 /* EGR_HDR_ID_EFPPARS_EN */ "This maps the HDR_ID to the index for lookup in HDR_ID_EFPPARS_PROFILE_TBALE to provide container IDs for Efppars field extraction", 2087 /* EGR_HDR_ID_EFPPARS_PROFILE_TABLE */ "This provides container ID and flags for Efppars extraction", 2088 /* EGR_HEADER_ENCAP_DATA */ "Engress header encap data, index by PBE.HEADER_ENCAP_INDEX.", 2089 /* EGR_HISTO_LATENCY_LIMIT */ "Sets the latency limit in 64ns quanta.", 2090 /* EGR_HISTO_MON_0_Q_LATENCY_LIMIT_SEL */ "Select one of the 32 latency limits for this queue / bkt for Monitor 0.", 2091 /* EGR_HISTO_MON_1_Q_LATENCY_LIMIT_SEL */ "Select one of the 32 latency limits for this queue / bkt for Monitor 1.", 2092 /* EGR_HISTO_MON_2_Q_LATENCY_LIMIT_SEL */ "Select one of the 32 latency limits for this queue / bkt for Monitor 2.", 2093 /* EGR_HISTO_MON_3_Q_LATENCY_LIMIT_SEL */ "Select one of the 32 latency limits for this queue / bkt.", 2094 /* EGR_IFP_MOD_FIELDS */ "L2 Modifications needed due to the IFP", 2095 /* EGR_IL_CHANNEL_MAP */ "Maps Port/Cos to Interlaken Channel Number", 2096 /* EGR_IM_MTP_INDEX */ "Mirror to Port Table to be used for IM tagged packets.\nIndex is constructed using pbe.mtp_index[6:0] field.\nWe use {pbe.mtp_index[4:3],pbe.mtp_index[2:0]} as index into this table.", 2097 /* EGR_ING_PORT */ "Configuration Register for Ingress Port. This is different for each GE, 10GE port. FeatureSpecific-Ethernet.", 2098 /* EGR_INT_CN_TO_EXP_MAPPING_TABLE */ "Map INT_CN to MPLS EXP. Used in MPLS encapsulation.", 2099 /* EGR_INT_CN_TO_IP_MAPPING */ "Egress Internal CN update table", 2100 /* EGR_INT_CN_TO_PKT_ECN_MAPPING */ "Egress Internal CN to IP ECN Mapping Table.", 2101 /* EGR_INT_CN_UPDATE */ "Egress Internal CN update table", 2102 /* EGR_IPFIX_DSCP_XLATE_TABLE */ "IPFIX DSCP Translation Table -- Address = {IP_DSCP_PROFILE[1:0], pkt_dscp[5:0]}", 2103 /* EGR_IPFIX_EOP_BUFFER */ "IPFIX EOP BUFFER - to save info per-port from SOP cells to EOP cells.", 2104 /* EGR_IPFIX_EXPORT_FIFO */ "Egress IPFIX Export FIFO", 2105 /* EGR_IPFIX_IPV4_MASK_SET_A */ "IPFIX IPv4 Address Masks", 2106 /* EGR_IPFIX_IPV6_MASK_SET_A */ "IPFIX IPv6 Address Masks", 2107 /* EGR_IPFIX_PROFILE */ "Egress IPFIX Per-Port Profile Pointers", 2108 /* EGR_IPFIX_SESSION_TABLE */ "Egress IPFIX Session Table", 2109 /* EGR_IPMC */ "Per IPMC group attributes needed in EP, FeatureSpecific-Ethernet", 2110 /* EGR_IPMC_CFG2 */ "Configuration Register for IPMC related modifications.", 2111 /* EGR_IP_ADDRESS_PROFILE */ "Destination IP Values for use when doing MPLS Packet Modifications.", 2112 /* EGR_IP_CUT_THRU_CLASS */ "To select the cut-through class based on ingress port number", 2113 /* EGR_IP_ECN_TO_EXP_MAPPING_TABLE */ "Map IP ECN to MPLS EXP. Used in MPLS encapulation.", 2114 /* EGR_IP_TO_INT_CN_MAPPING */ "IP ECN to INT_CN Mapping for IPinIP tunnels", 2115 /* EGR_IP_TUNNEL */ "Egress IP Tunnel Table. Used to Make new Tunnel Header.", 2116 /* EGR_IP_TUNNEL_ACTION_MASK_PROFILE */ "EGR_IP_TUNNEL Action Mask Profile table", 2117 /* EGR_IP_TUNNEL_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table(EGR_IP_TUNNEL).", 2118 /* EGR_IP_TUNNEL_IPV6 */ "IPV6 view of the Egress IP Tunnel Table. Used to make new IPV6 Tunnel Header. FeatureSpecific-Ethernet", 2119 /* EGR_IP_TUNNEL_MPLS */ "MPLS view of the Egress IP Tunnel Table. Used to make new MPLS Tunnel Header. Note there are 4 entries per location. FeatureSpecific-Ethernet", 2120 /* EGR_IP_TUNNEL_MPLS_DOUBLE_WIDE */ "MPLS Double wude View of the Egress IP Tunnel Table. Used to make new MPLS Tunnel Header. Note there are 8 entries per location.", 2121 /* EGR_L2_TAG_INHERIT_ACTION_MASK_PROFILE */ "Ingress Action Mask Profile table", 2122 /* EGR_L2_TAG_INHERIT_PROFILE */ "Ingress Action Mask Profile table", 2123 /* EGR_L3_INTF */ "L3 Interface Table", 2124 /* EGR_L3_INTF_ACTION_MASK_PROFILE */ "EGR_L3_INTF Action Mask Profile table", 2125 /* EGR_L3_INTF_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table(EGR_L3_INTF).", 2126 /* EGR_L3_INTF_EARLY_ACTION_PROFILE */ "Contains bitmap of the EARLY actions generated by the associated table(EGR_L3_INTF).", 2127 /* EGR_L3_NEXT_HOP */ "Next Hop Table", 2128 /* EGR_L3_NEXT_HOP_1 */ "Inidividual protection state for each tunnel.", 2129 /* EGR_L3_NEXT_HOP_2 */ "Non-shared portion of Egress Next Hop Table (entry 0 is reserved).", 2130 /* EGR_L3_NEXT_HOP_ACTION_MASK_PROFILE */ "EGR_L3_NEXT_HOP Action Mask Profile table", 2131 /* EGR_L3_NEXT_HOP_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table(EGR_L3_NEXT_HOP).", 2132 /* EGR_L3_NEXT_HOP_EARLY_ACTION_PROFILE */ "Contains bitmap of the EARLY actions generated by the associated table(EGR_L3_NEXT_HOP).", 2133 /* EGR_LABEL_PRECEDENCE_PROFILE_TABLE */ "Profile table for MPLS label prcedence.", 2134 /* EGR_LINK_LOCAL_MAC_ADDRESS */ "Egress LINK_LOCAL_MAC_ADDRESS register.", 2135 /* EGR_LM_COUNTER_CONTROL */ "Per opcode OAM LM packets counter control.", 2136 /* EGR_LPORT_PROFILE */ "LPORT Profile table for packets destined to subtending ports", 2137 /* EGR_MACDA_OUI_PROFILE */ "Derive MAC DA from the Profile Index from l3uc_ext view in ingress pipeline.", 2138 /* EGR_MAC_DA_PROFILE */ "MAC-DA values for use when doing MPLS packet mods, FeatureSpecific-Ethernet", 2139 /* EGR_MAP_MH */ "Used for mapping incoming PBE MH_PRIORITY into a new MH_PRIORITY/TC For Higig+/Higig2 header, on a per-egress-port basis.", 2140 /* EGR_MASK */ "Egress Mask Table", 2141 /* EGR_MASK_MODBASE */ "Specifies the port(s) that is (are) CPU.", 2142 /* EGR_MAX_USED_ENTRIES */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2143 /* EGR_MAX_USED_ENTRIES_X */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2144 /* EGR_MAX_USED_ENTRIES_Y */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2145 /* EGR_MA_INDEX */ ".", 2146 /* EGR_MFRAME_COUNTER */ "Counter for the egress port preemptable packets", 2147 /* EGR_MIM_ISID_DOT1P_MAPPING_TABLE */ "Egress VLAN Tag Action Profile Table.", 2148 /* EGR_MIRROR_ENCAP_CONTROL */ "Contains the Mirror Encap controls for each of the 8 Mirror Encap Indices.", 2149 /* EGR_MIRROR_ENCAP_DATA_1 */ "Contains the Base Header portion of Mirror Encap Data for each of the 8 Mirror Encap Indices.", 2150 /* EGR_MIRROR_ENCAP_DATA_2 */ "Contains the Optional Header portion of Mirror Encap Data for each of the 8 Mirror Encap Indices.", 2151 /* EGR_MIRROR_SEQ */ "Sequence Number for PSAMP or SFLOW packets.", 2152 /* EGR_MIRROR_SEQ_PIPE0 */ "Sequence Number for PSAMP or SFLOW packets.", 2153 /* EGR_MIRROR_SEQ_PIPE1 */ "Sequence Number for PSAMP or SFLOW packets.", 2154 /* EGR_MIRROR_SEQ_PIPE2 */ "Sequence Number for PSAMP or SFLOW packets.", 2155 /* EGR_MIRROR_SEQ_PIPE3 */ "Sequence Number for PSAMP or SFLOW packets.", 2156 /* EGR_MIRROR_SEQ_PIPE4 */ "Sequence Number for PSAMP or SFLOW packets.", 2157 /* EGR_MIRROR_SEQ_PIPE5 */ "Sequence Number for PSAMP or SFLOW packets.", 2158 /* EGR_MIRROR_SEQ_PIPE6 */ "Sequence Number for PSAMP or SFLOW packets.", 2159 /* EGR_MIRROR_SEQ_PIPE7 */ "Sequence Number for PSAMP or SFLOW packets.", 2160 /* EGR_MIRROR_TABLE */ "Contains the Mirror Encapsulation controls for each of the 8 Mirror Encapsulation Indices.", 2161 /* EGR_MIRROR_TABLE_PIPE0 */ "Contains the Mirror Encapsulation controls for each of the 8 Mirror Encapsulation Indices.", 2162 /* EGR_MIRROR_TABLE_PIPE1 */ "Contains the Mirror Encapsulation controls for each of the 8 Mirror Encapsulation Indices.", 2163 /* EGR_MIRROR_USER_META_DATA */ "", 2164 /* EGR_MIRROR_ZERO_OFFSET_PROFILE */ "Mirror packet payload zeroing offset profile table.", 2165 /* EGR_MMU_CELL_CREDIT */ "Set the maximum cell credit sent to MMU for each lane. Index by phyiscal port num", 2166 /* EGR_MMU_CREDIT_LIMIT */ "This one is to limit the register counts to the MMU even with the large buffer. It needs to be programmed before putting the egr_enable to see it's taking effect.\nWhen disable, ep_to_mmu_cell_req will be sending to MMU based on the buffer size.\nWhen enable, ep_to_mmu_cell_req will be only be issued when the EGR_MMU_REQUESTS smaller or equal to the EGR_MMU_CREDIT_LIMIT.", 2167 /* EGR_MMU_CREDIT_LIMIT_X */ "This one is to limit the register counts to the MMU even with the large buffer. It needs to be programmed before putting the egr_enable to see it's taking effect.\nWhen disable, ep_to_mmu_cell_req will be sending to MMU based on the buffer size.\nWhen enable, ep_to_mmu_cell_req will be only be issued when the EGR_MMU_REQUESTS smaller or equal to the EGR_MMU_CREDIT_LIMIT.", 2168 /* EGR_MMU_CREDIT_LIMIT_Y */ "This one is to limit the register counts to the MMU even with the large buffer. It needs to be programmed before putting the egr_enable to see it's taking effect.\nWhen disable, ep_to_mmu_cell_req will be sending to MMU based on the buffer size.\nWhen enable, ep_to_mmu_cell_req will be only be issued when the EGR_MMU_REQUESTS smaller or equal to the EGR_MMU_CREDIT_LIMIT.", 2169 /* EGR_MMU_REQUESTS */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2170 /* EGR_MMU_REQUESTS_X */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2171 /* EGR_MMU_REQUESTS_Y */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2172 /* EGR_MOD_MAP_TABLE */ "Egress Module Remapping Table", 2173 /* EGR_MPLS_EXP_MAPPING_1 */ "Mapping table for Internal Priority and CNG to MPLS labels EXP. Address = {VC_AND_SWAP_LABEL.MPLS_EXP_MAPPING_PTR, int_PRI, CNG}. FeatureSpecific-MPLS", 2174 /* EGR_MPLS_EXP_MAPPING_2 */ "Mapping table for Internal Priority and CNG to MPLS labels EXP. Address = {EGR_IP_TUNNEL_MPLS.MPLS_EXP_MAPPING_PTR, int_PRI, CNG} FeatureSpecific-MPLS", 2175 /* EGR_MPLS_EXP_MAPPING_3 */ "This table provides the Effective PHB & CNG for each label", 2176 /* EGR_MPLS_EXP_PRI_MAPPING */ "Mapping table for EXP to .1p/cfi. Address = {MPLS_EXP_MAPPING_PTR, new_exp} FeatureSpecific-MPLS", 2177 /* EGR_MPLS_PRI_MAPPING */ "Mapping table for Internal Priority and CNG to MPLS labels EXP. Address = {MPLS_EXP_MAPPING_PTR, int_PRI, CNG} FeatureSpecific-MPLS", 2178 /* EGR_MPLS_VC_AND_SWAP_LABEL_TABLE */ "MPLS VC and SWAP Label Table, FeatureSpecific-MPLS", 2179 /* EGR_MP_GROUP */ ".", 2180 /* EGR_MTU */ "Egress MTU Register.", 2181 /* EGR_MTU_CHECK */ "Egress MTU check mapping table.", 2182 /* EGR_MTU_PROFILE */ "MTU check table, Indexed by MTU_PROFILE_INDEX (5 bits)", 2183 /* EGR_MULTICAST_MAC_ADDR */ "My STATION", 2184 /* EGR_NAT_PACKET_EDIT_INFO */ "Per-chip control.", 2185 /* EGR_NETWORK_PRUNE_CONTROL */ "Per DVP_NETWORK_GROUP Prune enable for multipe Split Horizon Groups", 2186 /* EGR_OAM_DGLP_PROFILE */ "EGR_OAM_DGLP_PROFILE", 2187 /* EGR_OAM_FLEXIBLE_DOMAIN_CONTROL */ "index:{PRE VXLT IVID VALID,PRE VXLT OVID VALID,POST VXLT IVID VALID,POST VXLT OVID VALID,DVP VALID}", 2188 /* EGR_OAM_LM_COUNTERS_0 */ "Packet counter for OAM Loss Measurement pool 0", 2189 /* EGR_OAM_LM_COUNTERS_1 */ "Packet counter for OAM Loss Measurement pool 1", 2190 /* EGR_OAM_LM_COUNTERS_2 */ "Packet counter for OAM Loss Measurement pool 0", 2191 /* EGR_OAM_MAC_ADDRESS */ "loopback reply message construction requires per port MACDA value", 2192 /* EGR_OAM_OPCODE_CONTROL_PROFILE */ ".", 2193 /* EGR_OAM_OPCODE_GROUP */ ".", 2194 /* EGR_OLP_CONFIG */ "Contains OLP-HDR related items", 2195 /* EGR_OLP_CONFIG_1 */ "Contains OLP-HDR related items", 2196 /* EGR_OLP_CONFIG_2 */ "Contains OLP-HDR related items", 2197 /* EGR_OLP_DGPP_CONFIG */ "Contains OLP-HDR related items", 2198 /* EGR_OLP_DGPP_CONFIG_1 */ "Contains OLP-HDR related items", 2199 /* EGR_OLP_HEADER_TYPE_MAPPING */ "This Table provides a flexible mapping between OLP_HDR_COMPRESSED to the\nactual OLP_HDR_TYPE and OLP_HDR_SUBTYPE.\nINDEX (4bits): {MEP_TYPE(1b), OLP_HDR_TYPE_COMPRESSED(3b)}\nMEP_TYPE: 0 = Down-MEP/IFP, 1= UP-MEP\n#To be Updated later\n#MEP_TYPE COMPRESSED_HDR_TYPE HDR_TYPE HDR_SUBTYPE\n#==========================================================================\n# Downmep/IFP 3'b000 8'd1(L2_HDR) 8'd0(NULL)\n# Downmep/IFP 3'b001 8'd0(OAM_H ...", 2200 /* EGR_OLP_HEADER_TYPE_MAPPING_1 */ "This Table provides a flexible mapping between OLP_HDR_COMPRESSED to the\nactual OLP_HDR_TYPE and OLP_HDR_SUBTYPE.\nINDEX (4bits): {MEP_TYPE(1b), OLP_HDR_TYPE_COMPRESSED(3b)}\nMEP_TYPE: 0 = Down-MEP/IFP, 1= UP-MEP\n#MEP_TYPE COMPRESSED_HDR_TYPE HDR_TYPE HDR_SUBTYPE\n#==========================================================================\n# Downmep/IFP 3'b000 8'd1(L2_HDR) 8'd0(NULL)\n# Downmep/IFP 3'b001 8'd0(OAM_HDR) 8'd2(CCM/BHH- ...", 2201 /* EGR_OUTER_PRI_CFI_MAPPING_FOR_BYPASS */ "Egress VLAN Tag Action Profile Table for Low Latency EP Path.", 2202 /* EGR_PCP_DE_MAPPING */ "Mapping table for Internal Priority and CNG to LLTAG/ETAG PCP,DE. Address = {LLTAG/ETAG PCP DE MAPPING PTR[3:0],int_PRI, CNG} FeatureSpecific-PON n/w", 2203 /* EGR_PERQ_XMT_COUNTERS */ "Per-port Per-queue transmit counters (48 per port, 54 ports)", 2204 /* EGR_PERQ_XMT_COUNTERS_BASE_ADDR */ "Per-port Per-queue transmit counters Base Address.", 2205 /* EGR_PERQ_XMT_COUNTERS_PIPE0 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 34*20 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%34)*20 + COS from MMU + !UNICAST*10\n e.g. device port 68,\n unicast cos 5 = 48+ (68%34)*20+5+0*10=53\n unicast cos 6 = 48+ (68%34 ...", 2206 /* EGR_PERQ_XMT_COUNTERS_PIPE1 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 34*20 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%34)*20 + COS from MMU + !UNICAST*10\n e.g. device port 68,\n unicast cos 5 = 48+ (68%34)*20+5+0*10=53\n unicast cos 6 = 48+ (68%34 ...", 2207 /* EGR_PERQ_XMT_COUNTERS_PIPE2 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 34*20 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%34)*20 + COS from MMU + !UNICAST*10\n e.g. device port 68,\n unicast cos 5 = 48+ (68%34)*20+5+0*10=53\n unicast cos 6 = 48+ (68%34 ...", 2208 /* EGR_PERQ_XMT_COUNTERS_PIPE3 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 34*20 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%34)*20 + COS from MMU + !UNICAST*10\n e.g. device port 68,\n unicast cos 5 = 48+ (68%34)*20+5+0*10=53\n unicast cos 6 = 48+ (68%34 ...", 2209 /* EGR_PERQ_XMT_COUNTERS_PIPE4 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 20*12 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%20)*12 + COS from MMU", 2210 /* EGR_PERQ_XMT_COUNTERS_PIPE5 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 20*12 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%20)*12 + COS from MMU", 2211 /* EGR_PERQ_XMT_COUNTERS_PIPE6 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 20*12 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%20)*12 + COS from MMU", 2212 /* EGR_PERQ_XMT_COUNTERS_PIPE7 */ "Per-port Per-queue Transmit Counters.\n Use fix scheme, per pipe, 34 ports,\n 48 (for cpu) + 20*12 (for loopback, management and front panel port)\n\n index = if (device_port_num == CPU_port)\n COS from MMU\n else\n 48 + (device_port_num%20)*12 + COS from MMU", 2213 /* EGR_PERQ_XMT_COUNTERS_X */ "Per-port Per-queue transmit counters.", 2214 /* EGR_PERQ_XMT_COUNTERS_Y */ "Per-port Per-queue transmit counters.", 2215 /* EGR_PER_PORT_BUFFER_OVERFLOW */ "Egress port buffer overflow status indicator", 2216 /* EGR_PER_PORT_BUFFER_SFT_RESET */ "Egress port buffer reset (per port)", 2217 /* EGR_PER_Q_ECN_MARKED */ "Error counters for ECN enhancement feature", 2218 /* EGR_PFC_CONTROL */ "control the PFC (Priority Flow Control) feature of the egress. It should be only used for the XLPORT.", 2219 /* EGR_PHYSICAL_PORT */ "Configuration Register for Ingress Port. This is different for each GE, 10GE port. FeatureSpecific-Ethernet.", 2220 /* EGR_PKT_ECN_TO_EXP_MAPPING_1 */ "Map IP ECN to MPLS EXP. Used in MPLS encapulation.", 2221 /* EGR_PKT_ECN_TO_EXP_MAPPING_2 */ "Map IP ECN to MPLS EXP. Used in MPLS encapulation.", 2222 /* EGR_PKT_ECN_TO_EXP_MAPPING_3 */ "Map IP ECN to MPLS EXP. Used in MPLS encapulation.", 2223 /* EGR_PKT_ECN_TO_EXP_MAPPING_4 */ "Map IP ECN to MPLS EXP. Used in MPLS encapulation.", 2224 /* EGR_PKT_FLOW_SELECT_TCAM */ "Policy Table for generating the EGR_PKT_FLOW_ID and controls for the Field Bus Construction block, Adaptation lookups, and the Editor Control Blocks.", 2225 /* EGR_PKT_FLOW_SELECT_TCAM_DATA_ONLY */ "Policy Table for generating the EGR_PKT_FLOW_ID and controls for the Field Bus Construction block, Adaptation lookups, and the Editor Control Blocks.", 2226 /* EGR_PKT_FLOW_SELECT_TCAM_ONLY */ "TCAM whose policy table assign the EGR_PKT_FLOW_ID and generates the controls for the Field Bus Construction block, Adaptation lookups, and Editor Control blocks.", 2227 /* EGR_PKT_FLOW_ZONE_SELECT_PROFILE */ "Egress Packet flow Zone select Profile Table.", 2228 /* EGR_PORT */ "Configuration Register for a Port. This is different for each GE, 10GE port. FeatureSpecific-Ethernet.", 2229 /* EGR_PORT_1 */ "Another per-port configuration Register for Egress port.", 2230 /* EGR_PORT_CREDIT_RESET */ "To clear the port credit(per physical port", 2231 /* EGR_PORT_MNFS_MFS_CONFIG */ "Egress port MNFS & MFS for preemptible traffic", 2232 /* EGR_PORT_PKT_SOP_ENABLE */ "Egress DOP Enable (per physical port).\n[0]=CPU,[1-12]=Front-Panel,[13]=LPBK", 2233 /* EGR_PORT_PREEMPTION_MODE */ "Egress port Preemption Mode", 2234 /* EGR_PORT_REQUESTS */ "This table contains the cell requests asserted by individual port blocks (XLPORT's and CMIC).\nMeaning of cell request is different for different ports, but this register has no\nunderstanding of those meanings. All it shows is the number of times cell_request signal\nwas asserted by each port to TP.", 2235 /* EGR_PORT_REQUESTS_X */ "This table contains the cell requests asserted by individual port blocks (XLPORT's and CMIC).\nMeaning of cell request is different for different ports, but this register has no\nunderstanding of those meanings. All it shows is the number of times cell_request signal\nwas asserted by each port to TP.", 2236 /* EGR_PORT_REQUESTS_Y */ "This table contains the cell requests asserted by individual port blocks (XLPORT's and CMIC).\nMeaning of cell request is different for different ports, but this register has no\nunderstanding of those meanings. All it shows is the number of times cell_request signal\nwas asserted by each port to TP.", 2237 /* EGR_PP_PORT_GPP_TRANSLATION_1 */ "PP Port to GPP Translation Table", 2238 /* EGR_PP_PORT_GPP_TRANSLATION_2 */ "PP Port to GPP Translation Table", 2239 /* EGR_PREEMPT_EDB_XMIT_CTRL */ "Egress transmission control, valid only for front panel ports", 2240 /* EGR_PREEMPT_ENABLE */ "Egress Enable (per physical port)", 2241 /* EGR_PREEMPT_MAX_USED_ENTRIES */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2242 /* EGR_PREEMPT_MMU_CREDIT_LIMIT */ "This one is to limit the register counts to the MMU even with the large buffer. It needs to be programmed before putting the egr_enable to see it's taking effect.\nWhen disable, ep_to_mmu_cell_req will be sending to MMU based on the buffer size.\nWhen enable, ep_to_mmu_cell_req will be only be issued when the EGR_MMU_REQUESTS smaller or equal to the EGR_MMU_CREDIT_LIMIT.", 2243 /* EGR_PREEMPT_MMU_REQUESTS */ "This register contains the cell requests asserted by TP for individual ports to MMU.\nMeaning of cell request is 1664 bits data. All it shows is the number of times cell_request signal\nwas asserted by TP to MMU for each port.", 2244 /* EGR_PREEMPT_PER_PORT_BUFFER_OVERFLOW */ "Egress port buffer overflow status indicator", 2245 /* EGR_PREEMPT_PFC_CONTROL */ "control the PFC (Priority Flow Control) feature of the egress. It should be only used for the XLPORT.", 2246 /* EGR_PRI_CNG_MAP */ "Per port egress priority/CFI mapping table", 2247 /* EGR_PW_INIT_COUNTERS */ "L2 MPLS Pseudo-wire Initiation Pkt/byte counters with SEQNUM overlay-- indexed by PW number", 2248 /* EGR_PW_INIT_COUNTERS_PIPE0 */ "L2 MPLS Pseudo-wire Initiation SEQNUM Table -- indexed by PW number.", 2249 /* EGR_PW_INIT_COUNTERS_PIPE1 */ "L2 MPLS Pseudo-wire Initiation SEQNUM Table -- indexed by PW number.", 2250 /* EGR_PW_INIT_COUNTERS_PIPE2 */ "L2 MPLS Pseudo-wire Initiation SEQNUM Table -- indexed by PW number.", 2251 /* EGR_PW_INIT_COUNTERS_PIPE3 */ "L2 MPLS Pseudo-wire Initiation SEQNUM Table -- indexed by PW number.", 2252 /* EGR_PW_INIT_COUNTERS_X */ "L2 MPLS Pseudo-wire Initiation SEQNUM Table -- indexed by PW number.", 2253 /* EGR_PW_INIT_COUNTERS_Y */ "L2 MPLS Pseudo-wire Initiation SEQNUM Table -- indexed by PW number.", 2254 /* EGR_QCN_CNM_CONTROL_TABLE */ "QCN CNM Control table.", 2255 /* EGR_QOS_CTRL_TCAM */ "TCAM which generates profile pointers for deriving strengths for QoS and DOT1P markings.", 2256 /* EGR_QOS_CTRL_TCAM_DATA_ONLY */ "TCAM policy table which generates profile pointers for deriving strengths for QoS and DOT1P markings.", 2257 /* EGR_QOS_CTRL_TCAM_ONLY */ "TCAM which generates profile pointers for deriving strengths for QoS and DOT1P markings.", 2258 /* EGR_QOS_ECN_PROFILE */ "For Multi-Domain Filter check feature .", 2259 /* EGR_QUEUE_TO_PP_PORT_MAP */ "Queue To DGPP Map Table, FeatureSpecific-Ethernet.", 2260 /* EGR_SAT_CONFIG_MAC_SA */ "This table is indexed using destination PP port to obtain MAC-SA for a multicast packet looped back using SAT-LLB function.", 2261 /* EGR_SAT_SAMP_DATA */ "Service Activation Detection ACTION-DATA for UPMEPs", 2262 /* EGR_SAT_SAMP_DATA_1 */ "Contains OLP-HDR related items for SAT-UPSAMP processing.This is a shadow table of the original EGR_SAT_SAMP_DATA table and stores only a subset of fields.Looked up only in Pass-B", 2263 /* EGR_SAT_SAMP_TCAM */ "Service Activation Detection TCAM for UPMEPs", 2264 /* EGR_SCI_TABLE */ "Egress SCI Table to lookup security attributes for MACSEC SecTag contruction.", 2265 /* EGR_SEQUENCE_NUMBER_PROFILE */ "Contains bitmap of the actions generated by the associated table.", 2266 /* EGR_SEQUENCE_NUMBER_TABLE */ "The table maintains the sequence number values. This is the table that subsumes the functionality of the EGR_FRAGMENT_ID_TABLE and the EGR_PW_INIT_COUNTERS. The index is provided by the Egress Object Tables", 2267 /* EGR_SEQUENCE_NUMBER_TABLE_PIPE0 */ "The table maintains the sequence number values. This is the table that subsumes the functionality of the EGR_FRAGMENT_ID_TABLE and the EGR_PW_INIT_COUNTERS. The index is provided by the Egress Object Tables", 2268 /* EGR_SEQUENCE_NUMBER_TABLE_PIPE1 */ "The table maintains the sequence number values. This is the table that subsumes the functionality of the EGR_FRAGMENT_ID_TABLE and the EGR_PW_INIT_COUNTERS. The index is provided by the Egress Object Tables", 2269 /* EGR_SERVICE_COUNTER_TABLE */ "Egress Virtual Port / Interface Counters", 2270 /* EGR_SERVICE_COUNTER_TABLE_X */ "Egress Virtual Port / Interface Counters.", 2271 /* EGR_SERVICE_COUNTER_TABLE_Y */ "Egress Virtual Port / Interface Counters.", 2272 /* EGR_SERVICE_PRI_MAP */ "Egress Class of Service instance priority value to OAM LM counter offset mapping table", 2273 /* EGR_SERVICE_PRI_MAP_0 */ "Ingress Class of Service instance priority value to OAM LM counter offset mapping table", 2274 /* EGR_SERVICE_PRI_MAP_1 */ "Ingress Class of Service instance priority value to OAM LM counter offset mapping table", 2275 /* EGR_SERVICE_PRI_MAP_2 */ "Ingress Class of Service instance priority value to OAM LM counter offset mapping table", 2276 /* EGR_SER_FIFO */ "EGR SER FIFO", 2277 /* EGR_SER_FIFO_2 */ "EGR SER FIFO", 2278 /* EGR_SER_FIFO_2_PIPE0 */ "EGR SER FIFO", 2279 /* EGR_SER_FIFO_2_PIPE1 */ "EGR SER FIFO", 2280 /* EGR_SER_FIFO_2_PIPE2 */ "EGR SER FIFO", 2281 /* EGR_SER_FIFO_2_PIPE3 */ "EGR SER FIFO", 2282 /* EGR_SER_FIFO_2_PIPE4 */ "EGR SER FIFO", 2283 /* EGR_SER_FIFO_2_PIPE5 */ "EGR SER FIFO", 2284 /* EGR_SER_FIFO_2_PIPE6 */ "EGR SER FIFO", 2285 /* EGR_SER_FIFO_2_PIPE7 */ "EGR SER FIFO", 2286 /* EGR_SER_FIFO_PIPE0 */ "EGR SER FIFO", 2287 /* EGR_SER_FIFO_PIPE1 */ "EGR SER FIFO", 2288 /* EGR_SER_FIFO_PIPE2 */ "EGR SER FIFO", 2289 /* EGR_SER_FIFO_PIPE3 */ "EGR SER FIFO", 2290 /* EGR_SER_FIFO_PIPE4 */ "EGR SER FIFO", 2291 /* EGR_SER_FIFO_PIPE5 */ "EGR SER FIFO", 2292 /* EGR_SER_FIFO_PIPE6 */ "EGR SER FIFO", 2293 /* EGR_SER_FIFO_PIPE7 */ "EGR SER FIFO", 2294 /* EGR_SER_FIFO_X */ "EGR SER FIFO", 2295 /* EGR_SER_FIFO_Y */ "EGR SER FIFO", 2296 /* EGR_SHAPING_CONTROL */ "Specifies control fields Egress for the MMU Shaping Bus.", 2297 /* EGR_SPECIAL_PKT_HANDLING_PROFILE */ "Special packet Action Profile Table.", 2298 /* EGR_SR_ETHERTYPES */ "Egress SR Ether type setting regsiter.", 2299 /* EGR_SR_FLOW_COUNT_POOL0 */ "Counts number over this flow.", 2300 /* EGR_SR_FLOW_COUNT_POOL1 */ "Counts number over this flow.", 2301 /* EGR_STRENGTH_PROFILE */ "Contains strengths that are used to assign objects from the egress object tables.", 2302 /* EGR_STU_CHECK */ "Egress STU check mapping table.", 2303 /* EGR_STU_PROFILE */ "STU check table, Indexed by STU_PROFILE_INDEX (5 bits)", 2304 /* EGR_SUBPORT_TAG_DOT1P_MAP */ "PHB to Outgoing SubPort Tag's PCP, DE mapping table", 2305 /* EGR_TDM_PORT_MAP */ "To enable the physical port map", 2306 /* EGR_TRILL_PARSE_CONTROL */ "Trill parse control.", 2307 /* EGR_TRILL_PARSE_CONTROL_2 */ "Trill parse control (second copy).", 2308 /* EGR_TRILL_RBRIDGE_NICKNAMES */ "Table that defines the TRILL RBridge nickname to use when sending out a packet. The index is derived from the ingress VLAN table.", 2309 /* EGR_TRILL_TREE_PROFILE */ "Trill Tree profile table.", 2310 /* EGR_TS_ING_PORT_MAP */ "Source identifier to be put on the TS SHIM header.", 2311 /* EGR_TS_UTC_CONVERSION */ "This one-entry table stores 1588 ToD values (UTC time) as computed by the time synchronization algorithm on the ARM core. The entry is to be updated once per second.", 2312 /* EGR_TS_UTC_CONVERSION_2 */ "This one-entry table stores 1588 ToD values (UTC time) as computed by the time synchronization algorithm on the ARM core. The entry is to be updated once per second.", 2313 /* EGR_TUNNEL_ECN_ENCAP */ "Egress Internal CN Update Table", 2314 /* EGR_TUNNEL_ECN_ENCAP_2 */ "Egress Internal CN Update Table for no-IP payload packets", 2315 /* EGR_TX_PROT_GROUP_TABLE */ "Protection Switching Drop Enable.", 2316 /* EGR_VC_AND_SWAP_ACTION_MASK_PROFILE */ "EGR_MPLS_VC_AND_SWAP_LABEL_TABLE Action Mask Profile table", 2317 /* EGR_VC_AND_SWAP_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table(EGR_MPLS_VC_AND_SWAP_LABEL_TABLE).", 2318 /* EGR_VC_AND_SWAP_EARLY_ACTION_PROFILE */ "Contains bitmap of the EARLY actions generated by the associated table(EGR_MPLS_VC_AND_SWAP_LABEL_TABLE).", 2319 /* EGR_VFI */ "Egress WLAN Destination Virtual Port Table, FeatureSpecific-Wireless", 2320 /* EGR_VFT_FIELDS_PROFILE */ "A profile table to generate static fields of the VFT header", 2321 /* EGR_VFT_PRI_MAP */ "It contains the VFT pri for FCOE.", 2322 /* EGR_VINTF_COUNTER_TABLE */ "Egress Virtual Port / Interface Counters", 2323 /* EGR_VINTF_COUNTER_TABLE_X */ "Egress Virtual Port / Interface Counters.", 2324 /* EGR_VINTF_COUNTER_TABLE_Y */ "Egress Virtual Port / Interface Counters.", 2325 /* EGR_VLAN */ "Vlan Membership Table for Egress", 2326 /* EGR_VLAN_CONTROL_1 */ "Controls Vlan Translate and VLAN membership related functions.", 2327 /* EGR_VLAN_CONTROL_2 */ "Controls Vlan Translate and VLAN membership related functions.", 2328 /* EGR_VLAN_CONTROL_3 */ "Controls Vlan Translate and VLAN membership related functions.", 2329 /* EGR_VLAN_COUNTER_PRI_COS_MAP */ "VLAN_COUNTER PRI_COS mapping.", 2330 /* EGR_VLAN_COUNTER_TABLE */ "EGR_VLAN action counter.", 2331 /* EGR_VLAN_STG */ "Egress Spanning Tree Stage Table", 2332 /* EGR_VLAN_TAG_ACTION_PROFILE */ "Egress VLAN Tag Action Profile Table.", 2333 /* EGR_VLAN_TAG_ACTION_PROFILE_2 */ "Egress VLAN Tag Action Profile Table.", 2334 /* EGR_VLAN_VFI_MEMBERSHIP */ "Egress VLAN VFI member table", 2335 /* EGR_VLAN_VFI_UNTAG */ "VLAN/VFI Untag Port bitmap.", 2336 /* EGR_VLAN_X */ "Vlan Membership Table for Egress.", 2337 /* EGR_VLAN_XLATE */ "Egress Vlan Translate CAM-RAM Combined View.", 2338 /* EGR_VLAN_XLATE_1_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2339 /* EGR_VLAN_XLATE_1_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2340 /* EGR_VLAN_XLATE_1_DOUBLE */ "Egress Vlan Translate Lookup Table.", 2341 /* EGR_VLAN_XLATE_1_ECC */ "ECC Table.", 2342 /* EGR_VLAN_XLATE_1_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 2343 /* EGR_VLAN_XLATE_1_KEY_ATTRIBUTES */ "Key Attributes Table.", 2344 /* EGR_VLAN_XLATE_1_LP */ "ECC Table.", 2345 /* EGR_VLAN_XLATE_1_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2346 /* EGR_VLAN_XLATE_1_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2347 /* EGR_VLAN_XLATE_1_SINGLE */ "Egress Vlan Translate Lookup Table.", 2348 /* EGR_VLAN_XLATE_2_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2349 /* EGR_VLAN_XLATE_2_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2350 /* EGR_VLAN_XLATE_2_DOUBLE */ "Egress Vlan Translate Lookup Table.", 2351 /* EGR_VLAN_XLATE_2_ECC */ "ECC Table.", 2352 /* EGR_VLAN_XLATE_2_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 2353 /* EGR_VLAN_XLATE_2_KEY_ATTRIBUTES */ "Key Attributes Table.", 2354 /* EGR_VLAN_XLATE_2_LP */ "ECC Table.", 2355 /* EGR_VLAN_XLATE_2_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2356 /* EGR_VLAN_XLATE_2_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2357 /* EGR_VLAN_XLATE_2_SINGLE */ "Egress Vlan Translate Lookup Table.", 2358 /* EGR_VLAN_XLATE_DATA_ONLY */ "Egress Vlan Translate Data Table only", 2359 /* EGR_VLAN_XLATE_ECC */ "Egress VLAN Translate Lookup Table.", 2360 /* EGR_VLAN_XLATE_LP */ "EGR_VLAN_XLATE LP Control Table.", 2361 /* EGR_VLAN_XLATE_MASK */ "Egress Vlan Translate CAM-RAM Combined View with mask for ports 0-9. FeatureSpecific-Ethernet", 2362 /* EGR_VLAN_XLATE_ONLY */ "Egress Vlan Translate CAM only.", 2363 /* EGR_VLAN_XLATE_OVERFLOW */ "Overflow for Egress Vlan Translate Lookup Table. FeatureSpecific-Ethernet.", 2364 /* EGR_VLAN_XLATE_SCRATCH */ "Egress Vlan Translate Scratch Table. FeatureSpecific-Ethernet - Useful for software to keep temproary entries.", 2365 /* EGR_VLAN_Y */ "Vlan Membership Table for Egress.", 2366 /* EGR_VNTAG_ETAG_PROFILE */ "VNTAG or ETAG Profile Pointer.", 2367 /* EGR_VPLAG_GROUP */ "Egress VP group table.", 2368 /* EGR_VPLAG_MEMBER */ "Egress VP member table.", 2369 /* EGR_VP_VLAN_MEMBERSHIP */ "Egress VP VLAN member table.", 2370 /* EGR_VP_VLAN_MEMBERSHIP_ACTION_A */ "Action of whether to prepend/append data from remap table to the key into hash A of EGR_VP_VLAN_MEMBERSHIP table.", 2371 /* EGR_VP_VLAN_MEMBERSHIP_ACTION_B */ "Action of whether to prepend/append data from remap table to the key into hash B of EGR_VP_VLAN_MEMBERSHIP table.", 2372 /* EGR_VP_VLAN_MEMBERSHIP_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2373 /* EGR_VP_VLAN_MEMBERSHIP_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2374 /* EGR_VP_VLAN_MEMBERSHIP_ECC */ "ECC Table for Egress VP VLAN Member Table.", 2375 /* EGR_VP_VLAN_MEMBERSHIP_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 2376 /* EGR_VP_VLAN_MEMBERSHIP_KEY_ATTRIBUTES */ "Key Attributes Table.", 2377 /* EGR_VP_VLAN_MEMBERSHIP_REMAP_A */ "Remapping table for hash key into hash A of EGR_VP_VLAN_MEMBERSHIP table.", 2378 /* EGR_VP_VLAN_MEMBERSHIP_REMAP_B */ "Remapping table for hash key into hash B of EGR_VP_VLAN_MEMBERSHIP table.", 2379 /* EGR_VP_VLAN_MEMBERSHIP_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2380 /* EGR_VP_VLAN_MEMBERSHIP_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 2381 /* EGR_VSAN_INTPRI_MAP */ "Indexed by 3b IPRI + 2b COLOR + 3b FCOE_VSAN_PRI_MAPPING_PROFILE.", 2382 /* EGR_VXLAN_HEADER */ "Direct index table, provides VXLAN header fields: Flags & Reserved fields. Used during ENCAP.", 2383 /* EGR_VXLT_ACTION_TABLE_A */ "Remapping Table for Ingress VXLT Hash (key+1).", 2384 /* EGR_VXLT_ACTION_TABLE_B */ "Remapping Table for Ingress VXLT Hash (key+1).", 2385 /* EGR_VXLT_REMAP_TABLE_A */ "Remapping Table for Ingress VXLT Hash (key+1).", 2386 /* EGR_VXLT_REMAP_TABLE_B */ "Remapping Table for Ingress VXLT Hash (key+1).", 2387 /* EGR_WLAN_ATTRIBUTES */ "Used for mapping incoming PBE MH_PRIORITY into a new MH_PRIORITY/TC For Higig+/Higig2 header, on a per-egress-port basis.", 2388 /* EGR_WLAN_DVP */ "Egress WLAN Destination Virtual Port Table, FeatureSpecific-Wireless", 2389 /* EGR_XMIT_START_COUNT */ "Determine the transmit start count threshold for cut-through and SAF mode", 2390 /* EGR_XMIT_START_COUNT_PIPE0 */ "Determine the transmit start count threshold for cut-through and SAF mode", 2391 /* EGR_XMIT_START_COUNT_PIPE1 */ "Determine the transmit start count threshold for cut-through and SAF mode", 2392 /* EGR_XMIT_START_COUNT_PIPE2 */ "Determine the transmit start count threshold for cut-through and SAF mode", 2393 /* EGR_XMIT_START_COUNT_PIPE3 */ "Determine the transmit start count threshold for cut-through and SAF mode", 2394 /* EGR_ZONE_0_EDITOR_CONTROL_TCAM */ "TCAM which controls the system header construction. System headers include Higig, Loopback, HG extension header or any other vendor system headers.", 2395 /* EGR_ZONE_0_EDITOR_CONTROL_TCAM_DATA_ONLY */ "Policy Table for EGR_ZONE_0_EDITOR_CONTROL TCAM.", 2396 /* EGR_ZONE_0_EDITOR_CONTROL_TCAM_ONLY */ "TCAM which controls the system header construction. System headers include Higig, Loopback, HG extension header or any other vendor system headers.", 2397 /* EGR_ZONE_0_MATCH_ID_ATTRIBUTES_TABLE */ "Egress Zone Match ID Attributes Table", 2398 /* EGR_ZONE_0_VAR_LEN_HDR1_PROFILE */ "Egress Zone Variable Length Header profile table", 2399 /* EGR_ZONE_0_VAR_LEN_HDR2_PROFILE */ "Egress Zone Variable Length Header profile table", 2400 /* EGR_ZONE_1_DOT1P_MAPPING_TABLE_1 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2401 /* EGR_ZONE_1_DOT1P_MAPPING_TABLE_2 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2402 /* EGR_ZONE_1_DOT1P_MAPPING_TABLE_3 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2403 /* EGR_ZONE_1_DOT1P_MAPPING_TABLE_4 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2404 /* EGR_ZONE_1_DOT1P_STRENGTH_PROFILE_1 */ "Contains strengths that are used to assign QoS from the egress object tables.", 2405 /* EGR_ZONE_1_DOT1P_STRENGTH_PROFILE_2 */ "Contains strengths that are used to assign QoS from the egress object tables.", 2406 /* EGR_ZONE_1_EDITOR_CONTROL_TCAM */ "TCAM which controls the header construction in Zone 1.", 2407 /* EGR_ZONE_1_EDITOR_CONTROL_TCAM_DATA_ONLY */ "Policy Table for EGR_ZONE_1_EDITOR_CONTROL TCAM.", 2408 /* EGR_ZONE_1_EDITOR_CONTROL_TCAM_ONLY */ "TCAM which controls the header construction in Zone 1.", 2409 /* EGR_ZONE_1_L2_TAG_CONTROL_PROFILE_DEL */ "Produces the EDIT_ID_DEL_Zi index.", 2410 /* EGR_ZONE_1_L2_TAG_CONTROL_PROFILE_INS */ "Produces the EDIT_ID_INS_Zi index and generates 2 editor engines and corresponding profiles.", 2411 /* EGR_ZONE_1_L2_TAG_CONTROL_PROFILE_RW */ "Produces the EDIT_ID_RW_Zi index and generates 2 editor engines and corresponding profiles.", 2412 /* EGR_ZONE_1_MATCH_ID_ATTRIBUTES_TABLE */ "Egress Zone Match ID Attributes Table", 2413 /* EGR_ZONE_1_QOS_MAPPING_TABLE */ "QoS mapping table. Maps the {QOS_MAPPING_PTR[7:0], INT_PRI[3:0], CNG[1:0]} to QoS. where QOS_MAPPING_PTR is port_num", 2414 /* EGR_ZONE_1_QOS_STRENGTH_PROFILE */ "Contains strengths that are used to assign QoS from the egress object tables.", 2415 /* EGR_ZONE_1_VAR_LEN_HDR1_PROFILE */ "Egress Zone Variable Length Header profile table", 2416 /* EGR_ZONE_1_VAR_LEN_HDR2_PROFILE */ "Egress Zone Variable Length Header profile table", 2417 /* EGR_ZONE_2_EDITOR_CONTROL_TCAM */ "TCAM which controls the header construction in Zone 2.", 2418 /* EGR_ZONE_2_EDITOR_CONTROL_TCAM_DATA_ONLY */ "Policy Table for EGR_ZONE_2_EDITOR_CONTROL TCAM.", 2419 /* EGR_ZONE_2_EDITOR_CONTROL_TCAM_ONLY */ "TCAM which controls the header construction in Zone 2.", 2420 /* EGR_ZONE_2_MATCH_ID_ATTRIBUTES_TABLE */ "Egress Zone Match ID Attributes Table", 2421 /* EGR_ZONE_2_QOS_MAPPING_TABLE */ "QoS mapping table. Maps the {QOS_MAPPING_PTR[7:0], INT_PRI[3:0], CNG[1:0]} to QoS. where QOS_MAPPING_PTR is port_num", 2422 /* EGR_ZONE_2_QOS_STRENGTH_PROFILE */ "Contains strengths that are used to assign QoS from the egress object tables.", 2423 /* EGR_ZONE_2_VAR_LEN_HDR1_PROFILE */ "Egress Zone Variable Length Header profile table", 2424 /* EGR_ZONE_2_VAR_LEN_HDR2_PROFILE */ "Egress Zone Variable Length Header profile table", 2425 /* EGR_ZONE_3_DOT1P_MAPPING_TABLE_1 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2426 /* EGR_ZONE_3_DOT1P_MAPPING_TABLE_2 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2427 /* EGR_ZONE_3_DOT1P_MAPPING_TABLE_3 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2428 /* EGR_ZONE_3_DOT1P_MAPPING_TABLE_4 */ "DOT1P mapping table. Maps the {PRI_CFI_MAPPING_PTR[3:0], INT_PRI[3:0], CNG[1:0]} to PRI, CFI.", 2429 /* EGR_ZONE_3_DOT1P_STRENGTH_PROFILE_1 */ "Contains strengths that are used to assign QoS from the egress object tables.", 2430 /* EGR_ZONE_3_DOT1P_STRENGTH_PROFILE_2 */ "Contains strengths that are used to assign QoS from the egress object tables.", 2431 /* EGR_ZONE_3_EDITOR_CONTROL_TCAM */ "TCAM which controls the construction of headers in Zone 3", 2432 /* EGR_ZONE_3_EDITOR_CONTROL_TCAM_DATA_ONLY */ "Egress Zone Match ID Attributes Table", 2433 /* EGR_ZONE_3_EDITOR_CONTROL_TCAM_ONLY */ "TCAM which controls the construction of headers in Zone 3", 2434 /* EGR_ZONE_3_L2_TAG_CONTROL_PROFILE_DEL */ "Produces the EDIT_ID_DEL_Zi index.", 2435 /* EGR_ZONE_3_L2_TAG_CONTROL_PROFILE_INS */ "Produces the EDIT_ID_INS_Zi index and generates 2 editor engines and corresponding profiles.", 2436 /* EGR_ZONE_3_L2_TAG_CONTROL_PROFILE_RW */ "Produces the EDIT_ID_RW_Zi index and generates 2 editor engines and corresponding profiles.", 2437 /* EGR_ZONE_3_MATCH_ID_ATTRIBUTES_TABLE */ "Egress Zone Match ID Attributes Table", 2438 /* EGR_ZONE_3_QOS_MAPPING_TABLE */ "QoS mapping table. Maps the {QOS_MAPPING_PTR[7:0], INT_PRI[3:0], CNG[1:0]} to QoS. where QOS_MAPPING_PTR is port_num", 2439 /* EGR_ZONE_3_QOS_STRENGTH_PROFILE */ "Contains strengths that are used to assign QoS from the egress object tables.", 2440 /* EGR_ZONE_3_VAR_LEN_HDR1_PROFILE */ "Egress Zone Variable Length Header profile table", 2441 /* EGR_ZONE_3_VAR_LEN_HDR2_PROFILE */ "Egress Zone Variable Length Header profile table", 2442 /* EGR_ZONE_4_EDITOR_CONTROL_TCAM */ "TCAM which controls the construction of headers in Zone 4", 2443 /* EGR_ZONE_4_EDITOR_CONTROL_TCAM_DATA_ONLY */ "Egress Zone Match ID Attributes Table", 2444 /* EGR_ZONE_4_EDITOR_CONTROL_TCAM_ONLY */ "TCAM which controls the construction of headers in Zone 4", 2445 /* EGR_ZONE_4_MATCH_ID_ATTRIBUTES_TABLE */ "Egress Zone Match ID Attributes Table", 2446 /* EGR_ZONE_4_QOS_MAPPING_TABLE */ "QoS mapping table. Maps the {QOS_MAPPING_PTR[7:0], INT_PRI[3:0], CNG[1:0]} to QoS. where QOS_MAPPING_PTR is port_num", 2447 /* EGR_ZONE_4_QOS_STRENGTH_PROFILE */ "Contains strengths that are used to assign QoS from the egress object tables.", 2448 /* EGR_ZONE_4_VAR_LEN_HDR1_PROFILE */ "Egress Zone Variable Length Header profile table", 2449 /* EGR_ZONE_4_VAR_LEN_HDR2_PROFILE */ "Egress Zone Variable Length Header profile table", 2450 /* EH_MASK_PROFILE */ "EH Tag Mask Profile. Used in conjunction with the HG_EH_TAG_MODIFY action", 2451 /* EH_MASK_PROFILE_PIPE0 */ "EH Tag Mask Profile. Used in conjunction with the HG_EH_TAG_MODIFY action", 2452 /* EH_MASK_PROFILE_PIPE1 */ "EH Tag Mask Profile. Used in conjunction with the HG_EH_TAG_MODIFY action", 2453 /* EH_MASK_PROFILE_PIPE2 */ "EH Tag Mask Profile. Used in conjunction with the HG_EH_TAG_MODIFY action", 2454 /* EH_MASK_PROFILE_PIPE3 */ "EH Tag Mask Profile. Used in conjunction with the HG_EH_TAG_MODIFY action", 2455 /* EMIRROR_CONTROL */ "Egress mirror bitmap register, FeatureSpecific-Ethernet.", 2456 /* EMIRROR_CONTROL1 */ "Egress mirror bitmap register, FeatureSpecific-Ethernet.", 2457 /* EMIRROR_CONTROL2 */ "Egress mirror bitmap register, FeatureSpecific-Ethernet.", 2458 /* EMIRROR_CONTROL3 */ "Egress mirror bitmap register, FeatureSpecific-Ethernet.", 2459 /* EM_MTP_INDEX */ "Egress Mirror to Port Table", 2460 /* ENDPOINT_COS_MAP */ "Provides a mapped cos offset value to be added to the final uc queue value. index by {ENDPOINT_COS_MAP_PROFILE_INDEX, INT_PRI}", 2461 /* ENDPOINT_QUEUE_MAP */ "Endpoint Queue Map table.", 2462 /* EPC_LINK_BMAP */ "Link status register under software control.", 2463 /* EPNI_ACE_TABLE */ "The ACE table maps ACE-pointer to a program selection and variable. The table contains 4K entries, each entry contains 2-bit program selection variable and 8-bit program variable. The index to each entry in the table is ACE-pointer11:0 with ACE-pointer11:1 setting the register address and ACE-pointer0 selects one of two entries in that register.", 2464 /* EPNI_ACE_TO_FHEI */ "The ACE to Forwarding Header Editing Information (FHEI) table contains 512 entries, each entry maps an ACE-pointer to an FHEI information. Every register includes a single entry with information about the FHEI.", 2465 /* EPNI_ACE_TO_OUT_LIF */ "The ACE to Out-LIF table contains 1K entries, each entry maps an ACE-pointer to an Out-LIF. Every register includes two 16-bit entries, thus ACE-Pointer9:1 sets the register address in the table, and ACE-Pointer0 set the entry number within the field.", 2466 /* EPNI_ACE_TO_OUT_PP_PORT */ "The ACE to Out-PP-Port table contains 4K entries, each entry maps an ACE-pointer to an Out-PP-Port. Every register includes four 8-bit entries, thus ACE-Pointer11:2 sets the register address in the table, and ACE-Pointer1:0 set the entry number within the field.", 2467 /* EPNI_ACM */ "Context Memory for packet alignment control", 2468 /* EPNI_AC_ENTRY_WITH_DATA_FORMAT */ "Encapsulation-Stack AC Format", 2469 /* EPNI_AC_FORMAT */ "Encapsulation-Stack AC Format", 2470 /* EPNI_AC_FORMAT_WITH_DATA */ "Encapsulation-Stack AC Format", 2471 /* EPNI_AC_HALF_ENTRY_FORMAT */ "Encapsulation-Stack AC Format", 2472 /* EPNI_ALIGNER_MIRR_QP_TO_CHANNEL_MAP */ "Map Mirror QP to output channel (8 bits)", 2473 /* EPNI_ALIGNER_QP_TO_CHANNEL_MAP */ "Map QP to output channel (8 bits)", 2474 /* EPNI_ALIGNER_QP_TO_CMIC_MAP */ "Map QP to cpu cos and source port.\n Relevant for traffic for Cmic only", 2475 /* EPNI_ASM */ "Context Memory for packet alignment data (remind segment)", 2476 /* EPNI_CFG_ETHER_TYPE_INDEX */ "Used for ROO application; holds the ether_type, tpid_0, tpid_1 for the native Eth. Accessed with Ether-Type-Index (4bits) field which is a part of the new ARP-LL entry format.", 2477 /* EPNI_CFG_MAPPING_TO_OAM_PCP */ "This table maps the TC2:0oam-lif-profile1:0 to oam-pcp. There are 32 possible values. (Jericho-BF15)", 2478 /* EPNI_COS_PROFILE_TABLE */ "This table is used to map each cos-profile (16 profiles) recieved from the PMF to TC DP parameters.", 2479 /* EPNI_COUNTER_SOURCE_MAP */ "Counter pointer source configuration table. The table maps counter mode and LIF range to the source of a counter pointer, for both counters 0 and 1. The table contains 256 entries, each entry is addressed by Counter-0-Mode is LIF, Counter-1-Mode is LIF, LIF-0-Range , LIF-1-Range, LIF-2-Range. The two msb of an address, Counter-0-Mode is LIF, Counter-1-Mode is LIF check if Counter 0/1-Mode are equal to LIF. If so, the corresponding bit is set. Otherwise it is zero. A counter source may be either ...", 2480 /* EPNI_CPM */ "CPU FIFO SEG DATA Memory", 2481 /* EPNI_DATA_FORMAT */ "Encapsulation-Stack Data Format", 2482 /* EPNI_DSCP_EXP_TO_PCP_DEI */ "The DSCP to PCP-DEI table contains 4K entries, each entry maps DSCP-EXP to PCP-DEI. Every register contains 8 entries.A table index is set by Header-Code, Out-DSCP-EXP7:3. Out-DSCP-EXP2:0 sets the entry number in a register.", 2483 /* EPNI_DSCP_REMARK */ "When handling the forwarding header and the packets header code is IPv4 or IPv6, this mapping table is used to map the 8-bit value to Out-DSCP-EXP field.\n o The entry address is set by IPv4|6 ,Drop-Precedence, Profile , In-DSCP-EXP 7:2\n , and the entry number within the address is set by In-Dscp-Exp1:0. Meaning, there are 8K rows in the table, each with four 8-bit entries.", 2484 /* EPNI_DSP_PTR_MAP */ "The PP-DSP parameter for unicast packet is received from FTMH header, while for Egress multicast copy its generated by the multicast replication machine.\n This table maps the PP-DSP field to the following parameters:\n Out-TM-Port\n Out-PP-Port\n Destination-System-Port", 2485 /* EPNI_EEDB_BANK */ "The encapsulation data is maintained in an Egress Encapsulation Database (EEDB)that is specific per egress device. This database contains tunneling and link layer information.\n The EEDB is built from 16 banks, each of them of 2K entries. Each entry if pointed by an Out-LIF or EEI. Every address (tables row) may include one or two entries.", 2486 /* EPNI_EGRESS_MEMBERSHIP */ "Egress membership table configuration table, correlating each OTM port with a VLAN or VSI. Each address corresponds with a VLAN/VSI (0 through 4095), with identical fields definitions per entry.", 2487 /* EPNI_ESEM_MANAGEMENT_REQUEST */ "Management requests", 2488 /* EPNI_ESEM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 2489 /* EPNI_ETH_OAM_OPCODE_MAP */ "This table is used for mapping OAM-Header.Opcode to internal opcode used in the device.\n The index to the table is OAM-Header.Opcode7:0 and the result is 4 bits oam-opcode. The oam-opcode is used in accessing OAM-Trap-Engine by ETPP.", 2490 /* EPNI_ETPP_BYPASS */ "ETPP Bypass Memory", 2491 /* EPNI_ETPP_BYPASS_LSB */ "ETPP Bypass Memory of 128B LSB.", 2492 /* EPNI_EVEC_TABLE */ "The Packet-Is-MEF-L2CP (1), Incoming-Tag-Format (4), VLAN-Edit-Profile (4) to Egress VLAN Editing Command (EVEC) table contains 512 entries, each entry maps an Packet-Is-MEF-L2CP (1), Incoming-Tag-Format (4), VLAN-Edit-Profile (4) o an egress VLAN editing command. Every register includes two entries with information about the command. Each entry includes 7 fields as described below.", 2493 /* EPNI_EVENTORM */ "Eventor FIFO SEG DATA Memory", 2494 /* EPNI_EXP_REMARK */ "When handling the forwarding header and the packets header code is MPLS, this mapping table is used to map the 8-bit value to Out-DSCP-EXP field.\n The entry address is set by Drop-Precedence, Remark-Profile, In-Dscp-Exp2, and the entry number within the address is set by In-Dscp-Exp1:0. Meaning, there are 128 rows in the table, each with four 8-bit entries.", 2495 /* EPNI_HEADER_MAP */ "This table is used when the system works in Petra FTMH system header format mode.\n The table is used to select the source of the parser records fields from different location in packet system header.", 2496 /* EPNI_IFC_2_NIF_PORT_MAP */ "Map EGQ/EPNI internal interface number to NIF port number 1. pm_num(4),\n 2. pm_internal_port(4),\n 3. bicast_valid(1),\n 4. bicast_pm_num(4),\n 5. bicast_pm_internal_port(4)\n 6. nif_port(7)", 2497 /* EPNI_IPSEC_SEG */ "IPSEC FIFO SEG DATA Memory", 2498 /* EPNI_IPV4_TUNNEL_FORMAT */ "Encapsulation-Stack IPv4 Tunnel Format", 2499 /* EPNI_IP_TOS_MARKING */ "This table is used in etpp_forwarding, it holds TOS and Exp Marking and it is relevant for IP or MPLS packets when the in-lif profile enables it (see register EnableDscpMarking). The access (address) to this table is FTMH.TC(3), DP*(1), FHEI.In-LIF-Profile(2), Out-PP-Port.Marking-Profile(2)", 2500 /* EPNI_IP_TOS_MARKING_TABLE */ "This table is used in etpp_forwarding, it holds TOS and Exp Marking and it is relevant for IP or MPLS packets when the in-lif profile enables it (see register EnableDscpMarking). The access (address) to this table is: when DP-Mapping enabled- FTMH.TC(3), DP*(1), FHEI.In-LIF-Profile(2), OutLIF.ReMark-Profile(4), when DP-Mapping disabled- FTMH.TC(3), DP(2), FHEI.In-LIF-Profile(2), OutLIF.ReMark-Profile(3)", 2501 /* EPNI_ISID_TABLE */ "When a packets encapsulation mode is GRE-4B or GRE-8B, then a GRE header is constructed and added to packet-header. Part of it is a mapping of a key that is a concatenation of VSI.I-SID , LB-Key. The value of VSI.I-SID is given by this table, which maps VSI to I-SID value. This value is also used during link layer construction when out-PP port is PBP where I-SID is set to the value given in this table.\n Each entry in this table maps one VSI value to I-SID.", 2502 /* EPNI_IVEC_TABLE */ "Ingress VLAN editing command.\n This table has 64 entries. It is pointed by FHEI.Ingress-VLAN-Edit-Command", 2503 /* EPNI_LBG */ "LBG FIFO memory", 2504 /* EPNI_LBG_CALENDAR */ "LBG arbitration calendar table", 2505 /* EPNI_LBG_FIFO_CONFIG */ "The Index of the memory is the LBG FIFO number.\n There are 6 link bonding groups. For each LBG there are two FIFOs. All FIFOs share the same 384 entries memory. This table contains the Link Bonding FIFOs configuration.\n The FIFOs corresponding to LBG0 are FIFO 0 and 1, the FIFOs corresponding to LBG1 are FIFO 2 and 3, and so on.", 2506 /* EPNI_LBG_MAPPING */ "Per LBG group bitmap mapping of modems", 2507 /* EPNI_LBG_MODEM_CONFIG */ "Per LBG Modem Configuration memory", 2508 /* EPNI_LBG_REM */ "LBG Remainder memory", 2509 /* EPNI_LFEM_FIELD_SELECT_MAP */ "LFEM field selct map", 2510 /* EPNI_LINK_LAYER_OR_ARP_FORMAT */ "Encapsulation-Stack Link Layer or ARP Format", 2511 /* EPNI_LINK_LAYER_VLAN_PROCESSING_LLVP */ "The Link Layer VLAN Processing (LLVP) table contains 256 entries, each entry maps a concatenation of Out-PP-Port.LLVP-Profile(3) , Packet-Tag-Format(5) to VLAN edit command parameters. Each field in this table represents such a parameter.", 2512 /* EPNI_LINK_P_16_FIFO */ "LinkP16Fifo", 2513 /* EPNI_LINK_P_22_FIFO */ "LinkP22Fifo", 2514 /* EPNI_LINK_P_9_FIFO */ "LinkP9Fifo", 2515 /* EPNI_LLVP_TABLE */ "The Link Layer VLAN Processing (LLVP) table contains 256 entries, each entry maps a concatenation of Out-PP-Port.LLVP-Profile(3) , Packet-Tag-Format(5) to VLAN edit command parameters. Each field in this table represents such a parameter.", 2516 /* EPNI_MAP_HEADER_CODE_TO_MPLS_LABEL */ "Map header code to mpls label. Use the label from this table when ReservedMplsProfileTable.LabelType == 2", 2517 /* EPNI_MAX_LATENCY_TRACK */ "The ETPP measures latency from the packet OAM-TS extension.\n In this memory the 8 maximal latency's are kept, with the pointer associated with them", 2518 /* EPNI_MEM_520000 */ "INTERNAL", 2519 /* EPNI_MEM_600000 */ "INTERNAL", 2520 /* EPNI_MEM_610000 */ "INTERNAL", 2521 /* EPNI_MEM_620000 */ "INTERNAL", 2522 /* EPNI_MEM_630000 */ "INTERNAL", 2523 /* EPNI_MEM_640000 */ "INTERNAL", 2524 /* EPNI_MEM_650000 */ "INTERNAL", 2525 /* EPNI_MEM_660000 */ "INTERNAL", 2526 /* EPNI_MEM_670000 */ "INTERNAL", 2527 /* EPNI_MEM_760000 */ "INTERNAL", 2528 /* EPNI_MEM_770000 */ "INTERNAL", 2529 /* EPNI_MEM_7000000 */ "INTERNAL", 2530 /* EPNI_MEM_5A0000 */ "INTERNAL", 2531 /* EPNI_MEM_5B0000 */ "INTERNAL", 2532 /* EPNI_MEM_5D0000 */ "INTERNAL", 2533 /* EPNI_MEM_6C0000 */ "INTERNAL", 2534 /* EPNI_MEM_6D0000 */ "INTERNAL", 2535 /* EPNI_MIRROR_PROFILE_MAP */ "Mirroring-Profile Mapping Table.\n This table is used to map each mirror-profile (16 profiles) to Mirror-Command and Forward-Disable bit. Note that if Mirror-Profile = 0, no mirroring is done. The entry corresponding to Mirror-Profile = 0, should be configured to zero.", 2536 /* EPNI_MIRROR_PROFILE_TABLE */ "The mirror profile table maps VID index and Out-PP port to a program a mirror profile. The table contains 2K entries, each entry contains 4-bit mirror profile. The index to each register is out-PP-port, with VID-index selecting one of eight entries in that register.", 2537 /* EPNI_MPLS_CMD_PROFILE */ "The MPLS command decode table is used to decode each of the MPLS commands. Each entry corresponds to an MPLS command.", 2538 /* EPNI_MPLS_POP_FORMAT */ "Encapsulation-Stack MPLS Pop Format", 2539 /* EPNI_MPLS_PUSH_FORMAT */ "Encapsulation-Stack MPLS Push Format", 2540 /* EPNI_MPLS_SWAP_FORMAT */ "Encapsulation-Stack MPLS Swap Format", 2541 /* EPNI_MY_CFM_MAC_TABLE */ "My-CFM-MAC table. The table maps My-CFM-MAC address to OAM trap engine. The table contains 256 entries, one entry per PP port.\n The purpose of the register to decide if to trap a packet to the OAM engine. The field MacLsbsBitmap is a bitmap, with every bit corresponding to MAC DA7:0. If the bit corresponding with MAC DA7:0 is set and MacMsbs field in the the table is equal to MAC DA47:8 then OAM-My-CFM-MAC is set.", 2542 /* EPNI_NATIVE_DSCP_EXP_TO_PCP_DEI */ "The DSCP to PCP-DEI table contains 4K entries, each entry maps DSCP-EXP to PCP-DEI. Every register contains 8 entries.A table index is set by Header-Code, Out-DSCP-EXP7:3. Out-DSCP-EXP2:0 sets the entry number in a register.", 2543 /* EPNI_NATIVE_EVEC_TABLE */ "The Packet-Is-MEF-L2CP (1), Incoming-Tag-Format (4), VLAN-Edit-Profile (5) to Egress VLAN Editing Command (EVEC) table contains 512 entries, each entry maps an Packet-Is-MEF-L2CP (1), Incoming-Tag-Format (4), VLAN-Edit-Profile (5) o an egress VLAN editing command. Every register includes two entries with information about the command. Each entry includes 7 fields as described below.", 2544 /* EPNI_NATIVE_LINK_P_16_FIFO */ "NativeLinkP16Fifo", 2545 /* EPNI_NATIVE_LINK_P_9_FIFO */ "NativeLinkP9Fifo", 2546 /* EPNI_NATIVE_PCP_DEI_MAP */ "The PCP-DEI table contains 1024 entries, each entry maps PCP-DEI profile and PCP-DEI map key to primary VLAN bits15:12. Every register contains 8 entries.A table index is set by PCP-DEI-Profile, PCP-DEI-Map-Key 5:3. PCP-DEI-Map-Key2:0 sets the entry number in a register.", 2547 /* EPNI_NATIVE_PCP_DEI_TABLE */ "The PCP-DEI table contains 1024 entries, each entry maps PCP-DEI profile and PCP-DEI map key to primary VLAN bits15:12. Every register contains 8 entries.A table index is set by PCP-DEI-Profile, PCP-DEI-Map-Key 5:3. PCP-DEI-Map-Key2:0 sets the entry number in a register.", 2548 /* EPNI_OAM */ "OAM FIFO SEG DATA Memory", 2549 /* EPNI_OAMM */ "OAM FIFO SEG DATA Memory", 2550 /* EPNI_OLM */ "OLP FIFO SEG DATA Memory", 2551 /* EPNI_OLPM */ "OLP FIFO SEG DATA Memory", 2552 /* EPNI_OUTLIF_PROFILE_TO_PRGE_DATA */ "Map Outlif-Profile fields to a 6 bit Value for PRGE Resolved Data", 2553 /* EPNI_OUTLIF_PROFILE_TO_PRGE_PROGRAM */ "Map Outlif-Profile fields to a 6 bit Value for PRGE Program selection", 2554 /* EPNI_OUTLIF_TO_OAM_LIF_PROFILE_MAP */ "This table maps the outlif-profile (6) from the eedb entry to oam-profile (2). The oam-profile is used to resolve oam-pcp in etpp_term. There are 64 oam-profiles. (Jericho-BF15)", 2555 /* EPNI_OUT_RIF_FORMAT */ "Encapsulation-Stack Out-RIF Format", 2556 /* EPNI_PACKETPROCESSING_PORT_CONFIGURATION_TABLE */ "Per port packet processing configuration table, allowing configuring port-related PP features for each one of the 256 ports. Each address corresponds with a port, with identical fields definitions per entry.", 2557 /* EPNI_PACKET_PROCESSING_PORT_CONFIGURATION_TABLE_PP_PCT */ "Per port packet processing configuration table, allowing configuring port-related PP features for each one of the 256 ports. Each address corresponds with a port, with identical fields definitions per entry.", 2558 /* EPNI_PARSER_FIFO */ "ParserFifo", 2559 /* EPNI_PARSER_PEM_CAM */ "Parser Pem Cam is used to override the pem-context. It is located at the PRP. Is there is a match and (context-valid == 1) and the packet (is_applet==0) than the prp needs to override the context value received from the applet with the context value recived from the CAM.", 2560 /* EPNI_PCP_DEI_DP_MAPPING_TABLE */ "PCP-DEI Mapping Table for IVE, maps DP+INLIF_Profile+Selected_PCP_DEI to new PCP-DEI", 2561 /* EPNI_PCP_DEI_MAP */ "The PCP-DEI table contains 1024 entries, each entry maps PCP-DEI profile and PCP-DEI map key to primary VLAN bits15:12. Every register contains 8 entries.A table index is set by PCP-DEI-Profile, PCP-DEI-Map-Key 5:3. PCP-DEI-Map-Key2:0 sets the entry number in a register.", 2562 /* EPNI_PCP_DEI_TABLE */ "The PCP-DEI table contains 1024 entries, each entry maps PCP-DEI profile and PCP-DEI map key to primary VLAN bits15:12. Every register contains 8 entries.A table index is set by PCP-DEI-Profile, PCP-DEI-Map-Key 5:3. PCP-DEI-Map-Key2:0 sets the entry number in a register.", 2563 /* EPNI_PMF_MIRROR_PROFILE_TABLE */ "This table is used to map each mirror-profile (16 profiles) recieved from the PMF to Trap parameters. Each profile defines the following parameters: Mirror command(4), mirror enable(1), forward enable (1), mirror strength (2), forward strength (2)", 2564 /* EPNI_PMM */ "Mirroring FIFO SEG DATA Memory", 2565 /* EPNI_PP_COUNTER_TABLE */ "Per port counter configuration table, allowing configuring counter features for each one of the 256 ports. Each address corresponds with a port, with identical fields definitions per entry.", 2566 /* EPNI_PP_PCT */ "Per port packet processing configuration table, allowing configuring port-related PP features for each one of the 256 ports. Each address corresponds with a port, with identical fields definitions per entry.", 2567 /* EPNI_PP_REMARK_PROFILE */ "This table defines the remark-profile per port. It is used in etpp_forwarding to determine new ToSxp for IPMPLS headers", 2568 /* EPNI_PRGE_DATA */ "Programmable editor data", 2569 /* EPNI_PRGE_INSTRUCTION_0 */ "Programmable Editor (PRGE) instruction 0", 2570 /* EPNI_PRGE_INSTRUCTION_1 */ "Programmable Editor (PRGE) instructions 1 through 11", 2571 /* EPNI_PRGE_INSTRUCTION_2 */ "Programmable Editor (PRGE) instructions 1 through 11", 2572 /* EPNI_PRGE_INSTRUCTION_3 */ "Programmable Editor (PRGE) instructions 1 through 11", 2573 /* EPNI_PRGE_INSTRUCTION_4 */ "Programmable Editor (PRGE) instructions 1 through 11", 2574 /* EPNI_PRGE_INSTRUCTION_5 */ "Programmable Editor (PRGE) instructions 1 through 11", 2575 /* EPNI_PRGE_INSTRUCTION_6 */ "Programmable Editor (PRGE) instructions 1 through 11", 2576 /* EPNI_PRGE_INSTRUCTION_7 */ "Programmable Editor (PRGE) instructions 1 through 11", 2577 /* EPNI_PRGE_INSTRUCTION_8 */ "Programmable Editor (PRGE) instructions 1 through 11", 2578 /* EPNI_PRGE_INSTRUCTION_9 */ "Programmable Editor (PRGE) instructions 1 through 11", 2579 /* EPNI_PRGE_INSTRUCTION_10 */ "Programmable Editor (PRGE) instructions 1 through 11", 2580 /* EPNI_PRGE_INSTRUCTION_11 */ "Programmable Editor (PRGE) instructions 1 through 11", 2581 /* EPNI_PRGE_INSTRUCTION_12 */ "Programmable Editor (PRGE) instructions 1 through 13", 2582 /* EPNI_PRGE_INSTRUCTION_13 */ "Programmable Editor (PRGE) instructions 1 through 13", 2583 /* EPNI_PRGE_PROGRAM */ "Programmable editor program", 2584 /* EPNI_PRGE_PROGRAM_SELECTION_CAM */ "Programmable Editor (PRGE) program selection CAM. The CAM has 24 entries, representing 24 rules, which map the CAM entry to one of 16 programs. Each CAM entry creates such a program key.", 2585 /* EPNI_PRM */ "RCY FIFO Memory", 2586 /* EPNI_PROTECTION_PTR_TABLE */ "Specify tunnel state per protection pointer. The Pointer is read from the EEDB for banks that support this feature.\n Bits 14:6 in the address are used to select the row, bits5:0 select the tunnel state.", 2587 /* EPNI_PRP_P_10_FIFO */ "PrpP10Fifo", 2588 /* EPNI_PRP_P_12_FIFO */ "PrpP12Fifo", 2589 /* EPNI_PRP_P_6_FIFO */ "", 2590 /* EPNI_PRP_P_9_FIFO */ "", 2591 /* EPNI_PTM */ "Trap FIFO SEG DATA Memory", 2592 /* EPNI_REC_CMD_CONF */ "Per recycle command configuration", 2593 /* EPNI_REMARK_IPV4_TO_DSCP */ "Map Ipv4 ramek key to Dscp (8)\n Encapsulation-Editor\n Note: 4 values per entry", 2594 /* EPNI_REMARK_IPV4_TO_EXP */ "Map Ipv4 ramek key to Exp(3)\n Encapsulation-Editor\n Note: 8 values per entry", 2595 /* EPNI_REMARK_IPV6_TO_DSCP */ "Map Ipv6 ramek key to Dscp (8)\n Encapsulation-Editor\n Note: 4 values per entry", 2596 /* EPNI_REMARK_IPV6_TO_EXP */ "Map Ipv4 ramek key to Exp(3)\n Encapsulation-Editor\n Note: 8 values per entry", 2597 /* EPNI_REMARK_MPLS_TO_DSCP */ "Map MPLS remark key to DSCP (8)", 2598 /* EPNI_REMARK_MPLS_TO_EXP */ "Map MPLS remark key to EXP (3)", 2599 /* EPNI_RESERVED_MPLS_PROFILE_TABLE */ "This table maps mpls ReservedMplsProfile from MplsCmdProfile table to parameters used to build a single reserved mpls label. The reserved labels can be built when the action processed by the encapsulation module is MPLS-Push and the ReservedMplsProfile points to a valid entry in this table. The type of the reserved label is determined by the LabelType.", 2600 /* EPNI_ROO_VSI */ "This table is used to resolve the number of tags on the native Eth in Routing-Over-Overlay packets. The number of tags is defined per VSI.\n There are 8 values in each row, corresponding to 8 VSIs.\n VSI14:3 - pointer to mem, VSI2:0 - bit select.", 2601 /* EPNI_SATM */ "SAT FIFO SEG DATA Memory", 2602 /* EPNI_SAT_SEG */ "SAT FIFO SEG DATA Memory", 2603 /* EPNI_SPANNING_TREE_PROTOCOL_STATE_MEMORY_STP */ "The topology ID to Spanning Tree protocol state table contains 64 entries, each entry maps a topology ID, retrieved from Ingress topology-ID table to per PP-Port STP state. Every register is a bitmap, each bit corresponding to an out-PP port. The regier address is pointed by topology ID.", 2604 /* EPNI_STP */ "The topology ID to Spanning Tree protocol state table contains 64 entries, each entry maps a topology ID, retrieved from Ingress topology-ID table to per PP-Port STP state. Every register is a bitmap, each bit corresponding to an out-PP port. The regier address is pointed by topology ID.", 2605 /* EPNI_TRILL_FORMAT */ "Encapsulation-Stack TRILL Format", 2606 /* EPNI_TRILL_FORMAT_B_0 */ "Encapsulation-Stack TRILL Format", 2607 /* EPNI_TX_TAG_TABLE */ "The Outer-VID to VLAN tag manipulation table contains 4K entries, each entry maps an Outer-VID to VLAN tag manipulation. The manipulation manifests as a selection if to transmit the outer-VID or not. Every register is a bitmap, each bit corresponding to an out-PP port. The regier address is pointed by the Outer-VID.", 2608 /* EPRE_CPUM */ "CPU FIFO SEG DATA Memory", 2609 /* EPRE_HPMM */ "High priority Mirroring FIFO SEG DATA Memory", 2610 /* EPRE_HPM_SEG_SIZE_A */ "HP Mirroring FIFO SEG SIZE A DATA Memory", 2611 /* EPRE_HPM_SEG_SIZE_B */ "HP Mirroring FIFO SEG SIZE B DATA Memory", 2612 /* EPRE_LMM */ "Lossless Mirroring FIFO SEG DATA Memory", 2613 /* EPRE_LMM_SEG_SIZE_A */ "Lossless Mirroring FIFO SEG SIZE A DATA Memory", 2614 /* EPRE_LMM_SEG_SIZE_B */ "Lossless Mirroring FIFO SEG SIZE B DATA Memory", 2615 /* EPRE_RCYM */ "RCY FIFO Memory", 2616 /* EPRE_RCY_SEG_SIZE_A */ "RCY FIFO SEG SIZE A DATA Memory", 2617 /* EPRE_RCY_SEG_SIZE_B */ "RCY SEG SIZE B DATA Memory", 2618 /* EPS_CAL_CAL_INDX_MUX */ "Calendar of calendar shaper.", 2619 /* EPS_DPM */ "TC- Cast WFQ scheduler counters memory.", 2620 /* EPS_DPM_8P_DEQ */ "EIR WFQ scheduler counters memory. Read in DEQ pipe", 2621 /* EPS_DPM_8P_SCH */ "EIR WFQ scheduler counters memory. Read in EPS port scheduler pipe", 2622 /* EPS_DWM */ "The table contains 512 entries, one entry per Q-Pair. Each entry defines the weights of the UC and MC queues connected to this Q-Pair. Weight of 0 for one queue indicates that this qyeye has SP over the other. When both have equal weights, this implies simple RR. Maximum weight difference is 255:1.\n Rate Calculation:\n UC rate = (Q-Pair rate) * (MC weight) / (UC weight + MC weight)\n MC rate = (Q-Pair rate) * (UC weight) / (UC weight + MC weight)", 2623 /* EPS_DWM_8P */ "The table consist from 64 entries, one entry per Port Scheduler (group of 8 Q-Pairs). Defines the weights of the 8 traffic class groups (TCG) connected to this scheduler. Enables WFQ and SP relation between the 8 TCGs. Weight of 0 for a class indicates that this class has SP over the other classes. When all have equal weights, this implies simple RR. Maximum weight difference is 255:1. the lower the rate the higher the bandwidth.\n Rate Calculation:\n TCG(i) rate = (WFQ Total Rate) / (TCG(i) weigh ...", 2624 /* EPS_EPS_PRIO_MAP */ "Mapping each priority (Q-pair) to TCG.\n This table contains 64 entries. One entry per Port Scheduler (a queue group of 8 Q-Pairs).\n Each queue group is configured by PsMode register as either:\n One Eight-Priority ETM-Port (8P-Port)\n Two Four-Priority ETM-Port (4P-Port)\n Four Two-Priority ETM-Ports (2P-Port)\n Eight One-Priority ETM-Ports (1P-Port)\n This register is relevant only when the corresponding queue group is working in 8P-Port or 4P-Port mode. In this mode, this register defines for e ...", 2625 /* EPS_HEADR_CMPNS_CAL_HP_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per calendar.", 2626 /* EPS_HEADR_CMPNS_CAL_LP_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per calendar.", 2627 /* EPS_HEADR_CMPNS_OTM_HIGH_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per QP base high priority", 2628 /* EPS_HEADR_CMPNS_OTM_LOW_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per QP base low priority", 2629 /* EPS_HEADR_CMPNS_QP_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per QP", 2630 /* EPS_HEADR_CMPNS_TCG_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per TCG.", 2631 /* EPS_HEADR_CMPNS_WFQ_CAST_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per Cast counter.", 2632 /* EPS_HEADR_CMPNS_WFQ_TCG_CBM */ "Header Cmpnsensation Credit Balance Memory. This memory holds the credit balance per TCG counter.", 2633 /* EPS_IFC_CFG */ "Configuration per IFC port (0-31)", 2634 /* EPS_IFC_CFG_2 */ "Configuration per IFC port (32-63)", 2635 /* EPS_OTM_CALENDAR_CRDT_TABLE */ "OTM Calendar credit table", 2636 /* EPS_OTM_CFG */ "Configuration per OTM port (0-255)", 2637 /* EPS_OTM_CFG_2 */ "Configuration per OTM port (256-511)", 2638 /* EPS_OTM_HIGH_CAL_CRDT_BALANCE */ "Credit Balance Memory for calendar of High priority ports. This memory holds the credit balance of the OTM calendar shapers", 2639 /* EPS_OTM_HIGH_CRDT_BALANCE */ "Credit Balance Memory for High peiority ports. This memory holds the credit balance of the OTM shapers", 2640 /* EPS_OTM_HP_CRDT_TABLE */ "OTM HP credit table", 2641 /* EPS_OTM_HP_PPC_DB */ "Hold the data base (current mask and current index) of the high priority OTM schedular PPC", 2642 /* EPS_OTM_LOW_CAL_CRDT_BALANCE */ "Credit Balance Memory for calendar of Low priority ports. This memory holds the credit balance of the OTM calendar shapers", 2643 /* EPS_OTM_LOW_CRDT_BALANCE */ "Credit Balance Memory for Low peiority ports. This memory holds the credit balance of the OTM shapers", 2644 /* EPS_OTM_LP_CRDT_TABLE */ "OTM LP credit table.\n Mist be configured same as OtmHpCrdtTable !!!!", 2645 /* EPS_OTM_LP_PPC_DB */ "Hold the data base (current mask and current index) of the low priority OTM schedular PPC", 2646 /* EPS_OTM_SHAPER_LENGTH */ "Egress Shaper Confgiuration.", 2647 /* EPS_OTM_TOTAL_CRDT_BALANCE */ "Credit Balance Memory for ports. This memory holds the credit balance of the OTM shapers", 2648 /* EPS_PQP_NIF_PORT_MUX */ "Round robin for egress interfaces in interface selection scheduler in EPS", 2649 /* EPS_QP_CBM */ "Credit Balance Memory. This memory holds the credit balance per Q-Pair.", 2650 /* EPS_QP_CFG */ "Configuration per Q pair (0-255)", 2651 /* EPS_QP_CFG_2 */ "Configuration per Q pair (256-511)", 2652 /* EPS_QP_CREDIT_TABLE */ "Q-Pairs Shaper credit table", 2653 /* EPS_TCG_CBM */ "Credit Balance Memory. This memory holds the credit balance per TCG.", 2654 /* EPS_TCG_CFG */ "Configuration per TCG port (0-255)", 2655 /* EPS_TCG_CFG_2 */ "Configuration per TCG port (256-511)", 2656 /* EPS_TCG_CREDIT_TABLE */ "TCG Shaper credit table", 2657 /* EP_CTC_RES_TABLE */ "TCAM FOR EFPMOD.", 2658 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_0 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2659 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_1 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2660 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_2 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2661 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_3 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2662 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_4 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2663 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_5 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2664 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_6 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2665 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_7 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2666 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_8 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2667 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_9 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2668 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_10 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2669 /* EP_PARSER0_HFE_CONT_PROFILE_TABLE_11 */ "Parser EP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2670 /* EP_PARSER0_HFE_POLICY_TABLE_0 */ "Parser EP_PARSER0 This table provides HFE commands for stage ITER_I", 2671 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_0 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2672 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_1 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2673 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_2 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2674 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_3 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2675 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_4 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2676 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_5 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2677 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_6 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2678 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_7 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2679 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_8 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2680 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_9 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2681 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_10 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2682 /* EP_PARSER1_HFE_CONT_PROFILE_TABLE_11 */ "Parser EP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 2683 /* EP_PARSER1_HFE_POLICY_TABLE_0 */ "Parser EP_PARSER1 This table provides HFE commands for stage ITER_I", 2684 /* EP_PARSER1_HFE_POLICY_TABLE_1 */ "Parser EP_PARSER1 This table provides HFE commands for stage ITER_I", 2685 /* EP_PARSER1_HFE_POLICY_TABLE_2 */ "Parser EP_PARSER1 This table provides HFE commands for stage ITER_I", 2686 /* EP_PARSER1_HFE_POLICY_TABLE_3 */ "Parser EP_PARSER1 This table provides HFE commands for stage ITER_I", 2687 /* EP_REDIRECT_EM_MTP_INDEX */ "Egress Mirror to Port Table", 2688 /* EP_UAT_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 2689 /* EP_VLAN_XLATE_1 */ "", 2690 /* EP_VLAN_XLATE_1_HIT_ONLY */ "Egress Vlan Translate Lookup Table. FeatureSpecific-Ethernet.", 2691 /* ERPP_ACCEPTABLE_FRAME_TYPE_TABLE */ "Acceptable Frame Type Table used to configure per tag format (2 tags without the priority bit) and per PP-PPCT. Acceptable-Frame-Type-Profile", 2692 /* ERPP_CFG_ENABLE_FILTER_PER_FWD_CONTEXT */ "Each filter can be enable/disable per forwarding context.", 2693 /* ERPP_CFG_ENABLE_FILTER_PER_OUTLIF_PROFILE */ "Each filter can be enable/disable per outlif_profile.\n The outlif profile arrives from the GLEM result or (in case GLEM trap is required) from the per_port_table.", 2694 /* ERPP_CFG_ENABLE_FILTER_PER_PORT_TABLE */ "Each filter can be enable/disable per Port (DSP pointer).", 2695 /* ERPP_CFG_FHEI_UPPER_LAYER_TYPE_MAP */ "Mapping J-Mode Fhei-Upper-Layer-Protocol(4),Fhei-Cw(1) to J2 Fhei-Upper-Layer-Type(5)", 2696 /* ERPP_CFG_INLIF_DP_PROFILE_MAP */ "DP INLIF Profile for Inner and Outer PCP-DEI mapping in IVE, according to IN-LIF Profile from FHEI. 4 sets of INLIF_DP_Profile_outer,INLIF_DP_Profile_inner for 256 IN-LIF Profiles", 2697 /* ERPP_CFG_INLIF_PROFILE_MAPPED_IN_JERICHO_MODE */ "Backwards compatibility (for J-Mode):\n Inlif_profile = F(FHEI.In-LIF-Profile(2),PPH.In-LIF-Orientation(2), PPH.Reserved(2))", 2698 /* ERPP_CFG_INLIF_SELECTED */ "This table gets the address (valid bits: IP-MC, J-Mode and UC/MC) and his outputs are the decisions for ILIF0-1 (2bits for each OutLIF)", 2699 /* ERPP_CFG_MAPPING_FWD_CONTEXT */ "Forward Context Mapping - it maps the the fwd_context(5) to:\n same_if_filter(2)\n mtu_profile(3)", 2700 /* ERPP_CFG_MAPPING_INLIF_PROFILE */ "Inlif Orientation - it maps the the inlif profile to incoming orientation", 2701 /* ERPP_CFG_MAPPING_OUTLIF_PROFILE */ "Outlif Mapping - it maps the the outlif profile to specific filters uses", 2702 /* ERPP_CFG_MTU */ "Set MTU size for each profile. MTU may be up to 16KB.\n MTU is set by default to 16KB.\n Mapping the MTU Profile to MTU(14):\n MTU(14) = Map IF-MTU-Profile(3),UFC-MTU-Profile(2)", 2703 /* ERPP_CFG_OUTLIF_SELECTED */ "This table gets the address (valid bits from the JOutRIF&CUD&EEI&LifExt resolutions) and his outputs are the decisions for OutLIF0-3 (1bit for Outlif0 and 2bits for the rest).", 2704 /* ERPP_CFG_SAME_INTERFACE_FILTER */ "The following memory is used for Source Equal Destination filter, the mem default value should filters the following cases:\n ((ports are equal) AND (both interfaces are ports)) OR ((Ports are equal) and (both interfaces are not ports) and (interfaces are equal)).\n The address to the memory is:same_interface_filter_mapped_by_inlif_profile(2), sys_port_equal(1), inlif_is_port(1), outlif_is_port(1)\n And the location of the relevant data is mapped by: lifs_equal(1), same_interface_filter_mapped_by_o ...", 2705 /* ERPP_COUNTER_0_TYPE_TABLE */ "Counter profile to counter type table.\n Every address in this table corresponds with counter profile 0 for counter type. Table has 8 entries.", 2706 /* ERPP_COUNTER_1_TYPE_TABLE */ "Counter profile to counter type table.\n Every address in this table corresponds with counter profile 1 for counter type. Table has 8 entries.", 2707 /* ERPP_DSP_IN_LAG_TABLE */ "The table maps the Lag-LB-Key(8) and the Lag.Group-ID(6) to a dsp_ptr(8).\n The address for the table is the Group-ID.MSBs(6),LB-Key.MSB(6) and the 8bits data is taken by the LB-Key.LSBs(2).", 2708 /* ERPP_EFES_ACTION_MASK */ "Program Instruction Table per program for all 8 keys", 2709 /* ERPP_EGRESS_MCDB_FORMAT_CFG */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2710 /* ERPP_EPMFCS_ACTION */ "EpmfcsAction", 2711 /* ERPP_EPMFCS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 2712 /* ERPP_EPMFCS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 2713 /* ERPP_EPMFCS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 2714 /* ERPP_EPMFCS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 2715 /* ERPP_EPMFCS_TCAM_HIT_INDICATION */ "EpmfcsTcamHitIndication", 2716 /* ERPP_FES_2ND_INSTRUCTION */ "Program Instruction Table per program for all 8 keys", 2717 /* ERPP_FHEI_MPLS_UPPER_LAYER_PROTOCOL_TO_PES_MAPPING_TABLE */ "Mapping FHEI Upper Layer Protocol(5b) to PES Access1 parsing context (5b). Table has 32 entries.", 2718 /* ERPP_FIFO_DSP_1 */ "FIFO for Control sample", 2719 /* ERPP_FIFO_EXEM */ "FIFO for lem lookup result", 2720 /* ERPP_FIFO_TCAM_PASS_1 */ "FIFO for tcam 1st pass lookup result", 2721 /* ERPP_FORWARD_ACTION_PROFILE_TABLE */ "Action profile table, used to configure per action profile its properties.\n Every address in this table corresponds with an action profile. Table has 8 entries.", 2722 /* ERPP_FORWARD_CONTEXT_METADATA_TABLE */ "Forward context metadata table.\n Every address in this table corresponds with forward context metadata, used for the counter expansion i/f. Table has 32 entries.", 2723 /* ERPP_FWD_CONTEXT_SELECTION_CAM */ "Fwd Context Selection - maps pph_forwarding_layer_additional_info(4), fwd_layer_type(5), ftmh_tm_action_type(2), fwd_code_port_profile(2), is_tdm(1), is_applet(1) to new fwd_Context", 2724 /* ERPP_INITIAL_ACTIONS_FIFO */ "FIFO for holding fields of initial key", 2725 /* ERPP_IVEC_TABLE */ "Ingress VLAN editing command.\n This table has 128 entries. It is pointed by FHEI.Ingress-VLAN-Edit-Command", 2726 /* ERPP_LIF_EXTENSION_FORMAT_CFG */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2727 /* ERPP_L_4_OPS */ "Used to calculate L4Ops. The relevant bit of the L4Ops is set to '1' if:\n (source_port >= source_port_min ) &\n (source_port <= source_port_max ) &\n (destination_port >= destination_port_min ) &\n (destination_port <= destination_port_max )\n Reset Value:\n Value: 64'h0 Mask: 64'h0", 2728 /* ERPP_MEM_1500000 */ "INTERNAL", 2729 /* ERPP_MEM_15F0000 */ "INTERNAL", 2730 /* ERPP_MEM_16E0000 */ "INTERNAL", 2731 /* ERPP_MEM_17D0000 */ "INTERNAL", 2732 /* ERPP_MEM_18C0000 */ "INTERNAL", 2733 /* ERPP_MEM_7E0000 */ "INTERNAL", 2734 /* ERPP_MEM_8D0000 */ "INTERNAL", 2735 /* ERPP_MEM_9C0000 */ "INTERNAL", 2736 /* ERPP_MEM_AB0000 */ "INTERNAL", 2737 /* ERPP_MEM_BA0000 */ "INTERNAL", 2738 /* ERPP_MEM_F000000 */ "INTERNAL", 2739 /* ERPP_NETWORK_HEADERS_FIFO */ "This FIFO hold lower 128b of the packet header while the block is parsing the system headers. This is concatenated back to the packet before the parsing of the network headers.", 2740 /* ERPP_OUTLIF_PROFILE_TO_COUNTER_PROFILE_TABLE */ "Outlif profile to counter profile table, may be used as counter profile for crps.\n Every address in this table corresponds with counter profiles (0,1) for an outlif profile. Table has 8 entries.", 2741 /* ERPP_PARSING_START_TYPE_MAPPING_TABLE */ "Parsing start type to PES protocol type mapping table , used for mapping the (ftmh) parsing start type to Network headers PES protocol type. Table has 32 entries.", 2742 /* ERPP_PCP_DEI_DP_MAPPING_TABLE */ "PCP-DEI Mapping Table for IVE, maps DP+INLIF_Profile+Selected_PCP_DEI to new PCP-DEI", 2743 /* ERPP_PER_PORT_TABLE */ "The PP-PER_PORT parameter for unicast packet is received from FTMH header, while for Egress multicast copy its generated by the multicast replication machine.\n Per OTM-Port Configuration Table, allowing configuring port-related features for each one of the 256 ports. Each address corresponds with a port, with identical fields definitions per entry.\n Per PP-Port packet processing configuration table, allowing configuring port-related PP features for each one of the 256 ports. Each address corresp ...", 2744 /* ERPP_PMF_FES_PROGRAM */ "This table holds the Program and Key-Select for Field-Extraction-Macros.\n lines 0-31 : for FESs 0-15\n lines 32-63 : for instructions 16-31", 2745 /* ERPP_PMF_KBR_PASS */ "Program Instruction Table per program for all 8 keys", 2746 /* ERPP_PMF_PASS_KEY_GEN */ "Program Instruction Table per program for all 8 keys", 2747 /* ERPP_PRP_PP_DSP_PTR_TABLE */ "The PP-DSP parameter for unicast packet is received from FTMH header, while for Egress multicast copy its generated by the multicast replication machine.\n This table maps the PP-DSP field to the following parameters:\n Out-TM-Port\n Out-PP-Port\n Destination-System-Port", 2748 /* ERPP_PRP_SAVE_NETWORK_HEADER_FIFO */ "Pipe-FIFO - When getting the network header, waiting for all pipe ready.\n Wait for the data from the GLEM.\n The Depth will be 40 lines because:\n time_to_get_data_from_glem -(network_header_delay - read_req_to_glem)\n 64-(32-5)=37 so the depth will be 40 for any case that the time to the info from GLEM will be longer then 64.", 2749 /* ERPP_PRP_WAIT_FOR_GLEM_FIFO */ "Pipe-FIFO - Before GLEM results.\n When waiting for local OufLIF from GLEM need to delay all the Sys-Hdr data,\n The data is sent to the pipe only when the system_header arrives.", 2750 /* ERPP_SYSTEM_HEADERS_CONTAINER_FIFO */ "This FIFO is located after the PSG and used to hold the parsed system headers until a response from MCDB access has arrived", 2751 /* ERPP_TM_DATA_BYPASS_FIFO */ "Holds ERPP TM data bypass", 2752 /* ERPP_TM_FIELDS_FIFO */ "This FIFO holds several pipe fields during the parser block. Fields are dependent if the parser is instanced in ERPP or ETPP\n ERPP:\n 4'd0,\n p0_first_packet, //width = 1\n p0_tc_map_profile, //width = 4\n p0_mc_pp_dsp, //width = 9\n p0_discard, //width = 1\n p0_cud_outlif_or_mcdb_ptr //width = 22\n p0_pem_is_applet, //width = 1\n p0_pem_is_applet, //width = 1\n ...", 2753 /* ERPP_TM_PP_DSP_PTR_TABLE */ "The PP-DSP parameter for unicast packet is received from FTMH header, while for Egress multicast copy its generated by the multicast replication machine.\n This table maps the PP-DSP field to the following parameters:\n Out-TM-Port\n Out-PP-Port\n Destination-System-Port", 2754 /* ESBS_PORT_TO_PIPE_MAPPING */ "ESBS Port to Pipe Mapping table.", 2755 /* ESEC_MIB0 */ "esec_mib0 ESEC MIB 1024 x 625b", 2756 /* ESEC_MIB1 */ "esec_mib1 ESEC MIB 1024 x 98b", 2757 /* ESEC_MISC_COUNTERS */ "ESEC_Debug Counters, per-port", 2758 /* ESEC_OUTMGMTPKTS_COUNT */ "ESEC_Outmgmtpkts Counter", 2759 /* ESEC_PKT_HEADER_CAPTURE_BUFFER */ "Store the first 256 bytes of a packet that is captured by the packet header capture logic. Each entry contains 16 bytes of a packet data along with the associated information such as sop, eop. This table is partitioned into four sections, with each section dedicated to one port and capable of holding up to 256-byte of a packet from that port. SOP always starts at the frist entry of each partition ( entry 0, 16, 32, or 48 )", 2760 /* ESEC_SA_KEY_TABLE */ "SA Key table", 2761 /* ESEC_SA_TABLE */ "SA attribute Table", 2762 /* ESEC_SC_TABLE */ "ESEC SC Index (SCI) Table", 2763 /* ESM_ACL_ACTION_CONTROL */ "Table used to control ESM ACL actions.", 2764 /* ESM_ACL_PROFILE */ "Table used to profile ESM ACL actions.", 2765 /* ESM_HWTL_OBSERVED_ET_RSP */ "Observed ext_tcam_rsp from ETU", 2766 /* ESM_KEY_ID_TO_FIELD_MAPPER */ "Fields Mapper for ESM Key Generator.", 2767 /* ESM_L3_PROTOCOL_FN */ "ESM L3 Protocol Function table. Indexed by l3_protocol field generated in IMPLS/IPARS stage.", 2768 /* ESM_PKT_TYPE_ID */ "TCAM for generating Packet Type IDs to be used in ESM Key Generation. It's recommended to have a default entry with all bits masked, say entry 255, which will match in case no other entry matches. This will give a facility of programming the default packet_type value. In case of a miss from the TCAM though, hardware will take packet_type value as zero.", 2769 /* ESM_PKT_TYPE_ID_DATA_ONLY */ "TCAM for generating Packet Type IDs to be used in ESM Key Generation.", 2770 /* ESM_PKT_TYPE_ID_ONLY */ "TCAM for generating Packet Type IDs to be used in ESM Key Generation.", 2771 /* ESM_RANGE_CHECK */ "RANGE CHECK VALUES FOR ESM Key Generation logic", 2772 /* ESM_SEARCH_PROFILE */ "It is looked up with {PACKET_TYPE_ID(5),ESM_SEARCH_PROFILE_INDEX(6)} and gives out index to ESM_KEY_ID_TO_FIELD_MAPPER TABLE.", 2773 /* ES_ARB_TDM_TABLE */ "MMU to EPIPE Arbiter TDM Table", 2774 /* ES_PIPE0_LLS_L0_CHILD_STATE1 */ "ES PIPE 0 L0 Child Status 1 Database", 2775 /* ES_PIPE0_LLS_L0_CHILD_WEIGHT_CFG */ "ES PIPE 0 L0 Child Weight Config Database", 2776 /* ES_PIPE0_LLS_L0_CHILD_WEIGHT_WORKING */ "ES PIPE 0 L0 Child Working Weight and Count Database", 2777 /* ES_PIPE0_LLS_L0_ERROR */ "ES PIPE 0 L0 Error database containing difference between expected scheduling amount and actual scheduling amount", 2778 /* ES_PIPE0_LLS_L0_HEADS_TAILS */ "ES PIPE 0 L0 Heads and Tails Database", 2779 /* ES_PIPE0_LLS_L0_MEMA_CONFIG */ "ES PIPE 0 L0 Configuration Database. NOTE : This is a replicated database whose contents must match ES_PIPE0_LLS_L0_MEMB_CONFIG", 2780 /* ES_PIPE0_LLS_L0_MEMB_CONFIG */ "ES PIPE 0 L0 Configuration Database NOTE : This is a replicated database whose contents must match ES_PIPE0_LLS_L0_MEMA_CONFIG", 2781 /* ES_PIPE0_LLS_L0_MIN_NEXT */ "ES PIPE 0 L0 Child Min Linked List Next Database", 2782 /* ES_PIPE0_LLS_L0_PARENT */ "ES PIPE 0 L0 Parent Database", 2783 /* ES_PIPE0_LLS_L0_PARENT_STATE */ "ES PIPE 0 L0 Parent State Database", 2784 /* ES_PIPE0_LLS_L0_WERR_MAX_SC */ "ES PIPE 0 L0 Max Surplus Count Database", 2785 /* ES_PIPE0_LLS_L0_WERR_NEXT */ "ES PIPE 0 L0 Child WERR Linked List Next Database", 2786 /* ES_PIPE0_LLS_L0_XOFF */ "ES PIPE 0 L0 XOFF Database", 2787 /* ES_PIPE0_LLS_L1_CHILD_STATE1 */ "ES PIPE 0 L1 Child Status 1 Database", 2788 /* ES_PIPE0_LLS_L1_CHILD_WEIGHT_CFG */ "ES PIPE 0 L1 Child Weight Config Database", 2789 /* ES_PIPE0_LLS_L1_CHILD_WEIGHT_WORKING */ "ES PIPE 0 L1 Child Working Weight and Count Database", 2790 /* ES_PIPE0_LLS_L1_ERROR */ "ES PIPE 0 L1 Error database containing difference between expected scheduling amount and actual scheduling amount", 2791 /* ES_PIPE0_LLS_L1_HEADS_TAILS */ "ES PIPE 0 L1 Heads Tails Database", 2792 /* ES_PIPE0_LLS_L1_MEMA_CONFIG */ "ES PIPE 0 L1 Configuration Database NOTE : This is a replicated database whose contents must match ES_PIPE0_LLS_L1_MEMB_CONFIG", 2793 /* ES_PIPE0_LLS_L1_MEMB_CONFIG */ "ES PIPE 0 L1 Configuration Database NOTE : This is a replicated database whose contents must match ES_PIPE0_LLS_L1_MEMA_CONFIG", 2794 /* ES_PIPE0_LLS_L1_MIN_NEXT */ "ES PIPE 0 L1 Child Min Linked List Next Database", 2795 /* ES_PIPE0_LLS_L1_PARENT */ "ES PIPE 0 L1 Parent Database", 2796 /* ES_PIPE0_LLS_L1_PARENT_STATE */ "ES PIPE 0 L1 Parent State Database", 2797 /* ES_PIPE0_LLS_L1_WERR_MAX_SC */ "ES PIPE 0 L1 Max Surplus Count Database", 2798 /* ES_PIPE0_LLS_L1_WERR_NEXT */ "ES PIPE 0 L1 Child WERR Linked List Next Database", 2799 /* ES_PIPE0_LLS_L1_XOFF */ "ES PIPE 0 Port XOFF Database", 2800 /* ES_PIPE0_LLS_L2_CHILD_STATE1 */ "ES PIPE 0 L2 Child state database", 2801 /* ES_PIPE0_LLS_L2_CHILD_WEIGHT_CFG */ "ES PIPE 0 L2 Child Weight Config and count Database", 2802 /* ES_PIPE0_LLS_L2_CHILD_WEIGHT_WORKING */ "ES PIPE 0 L2 Child Working Weight and count Database", 2803 /* ES_PIPE0_LLS_L2_ERROR */ "ES PIPE 0 L2 Error database containing difference between expected scheduling amount and actual scheduling amount", 2804 /* ES_PIPE0_LLS_L2_MIN_NEXT */ "ES PIPE 0 L2 Child MIN Linked List Next Database 4 entries per word", 2805 /* ES_PIPE0_LLS_L2_PARENT */ "ES PIPE 0 L2 Parent Database", 2806 /* ES_PIPE0_LLS_L2_WERR_NEXT */ "ES PIPE 0 L2 Child WERR Linked List Next Database 4 entries per word", 2807 /* ES_PIPE0_LLS_L2_XOFF */ "ES PIPE 0 L2 XOFF Database", 2808 /* ES_PIPE0_LLS_PORT_HEADS_TAILS */ "ES PIPE 0 Port Heads Tails Database", 2809 /* ES_PIPE0_LLS_PORT_MEMA_CONFIG */ "ES PIPE 0 Port Configuration Database. NOTE : This is a replicated database, so contents must match ES_PIPE0_LLS_PORT_MEMB_CONFIG", 2810 /* ES_PIPE0_LLS_PORT_MEMB_CONFIG */ "ES PIPE 0 Port Configuration Database. NOTE : This is a replicated database, so contents must match ES_PIPE0_LLS_PORT_MEMA_CONFIG", 2811 /* ES_PIPE0_LLS_PORT_PARENT_STATE */ "ES PIPE 0 Port Parent State Database", 2812 /* ES_PIPE0_LLS_PORT_WERR_MAX_SC */ "ES PIPE 0 Port Max Surplus Count Database", 2813 /* ES_PIPE0_TDM_TABLE_0 */ "MMU to EPIPE Arbiter TDM Table 0, PIPE X", 2814 /* ES_PIPE0_TDM_TABLE_1 */ "MMU to EPIPE Arbiter TDM Table 1 (shadow table), PIPE X", 2815 /* ES_PIPE1_LLS_L0_CHILD_STATE1 */ "ES PIPE 1 L0 Child Status 1 Database", 2816 /* ES_PIPE1_LLS_L0_CHILD_WEIGHT_CFG */ "ES PIPE 1 L0 Child Weight Config Database", 2817 /* ES_PIPE1_LLS_L0_CHILD_WEIGHT_WORKING */ "ES PIPE 1 L0 Child Working Weight and Count Database", 2818 /* ES_PIPE1_LLS_L0_ERROR */ "ES PIPE 1 L0 Error database containing difference between expected scheduling amount and actual scheduling amount", 2819 /* ES_PIPE1_LLS_L0_HEADS_TAILS */ "ES PIPE 1 L0 Heads and Tails Database", 2820 /* ES_PIPE1_LLS_L0_MEMA_CONFIG */ "ES PIPE 1 L0 Configuration Database NOTE : This is a replicated database whose contents must match ES_PIPE1_LLS_L0_MEMB_CONFIG", 2821 /* ES_PIPE1_LLS_L0_MEMB_CONFIG */ "ES PIPE 1 L0 Configuration Database NOTE : This is a replicated database whose contents must match ES_PIPE1_LLS_L0_MEMA_CONFIG", 2822 /* ES_PIPE1_LLS_L0_MIN_NEXT */ "ES PIPE 1 L0 Child Min Linked List Next Database", 2823 /* ES_PIPE1_LLS_L0_PARENT */ "ES PIPE 1 L0 Parent Database", 2824 /* ES_PIPE1_LLS_L0_PARENT_STATE */ "ES PIPE 1 L0 Parent State Database", 2825 /* ES_PIPE1_LLS_L0_WERR_MAX_SC */ "ES PIPE 1 L0 Max Surplus Count Database", 2826 /* ES_PIPE1_LLS_L0_WERR_NEXT */ "ES PIPE 1 L0 Child WERR Linked List Next Database", 2827 /* ES_PIPE1_LLS_L0_XOFF */ "ES PIPE 1 L0 XOFF Database", 2828 /* ES_PIPE1_LLS_L1_CHILD_STATE1 */ "ES PIPE 1 L1 Child Status 1 Database", 2829 /* ES_PIPE1_LLS_L1_CHILD_WEIGHT_CFG */ "ES PIPE 1 L1 Child Weight Config Database", 2830 /* ES_PIPE1_LLS_L1_CHILD_WEIGHT_WORKING */ "ES PIPE 1 L1 Child Working Weight and Count Database", 2831 /* ES_PIPE1_LLS_L1_ERROR */ "ES PIPE 1 L1 Error database containing difference between expected scheduling amount and actual scheduling amount", 2832 /* ES_PIPE1_LLS_L1_HEADS_TAILS */ "ES PIPE 1 L1 Heads Tails Database", 2833 /* ES_PIPE1_LLS_L1_MEMA_CONFIG */ "ES PIPE 1 L1 Configuration Database. NOTE : This is a replicated database whose contents must match ES_PIPE1_LLS_L1_MEMB_CONFIG", 2834 /* ES_PIPE1_LLS_L1_MEMB_CONFIG */ "ES PIPE 1 L1 Configuration Database. NOTE : This is a replicated database whose contents must match ES_PIPE1_LLS_L1_MEMA_CONFIG", 2835 /* ES_PIPE1_LLS_L1_MIN_NEXT */ "ES PIPE 1 L1 Child Min Linked List Next Database", 2836 /* ES_PIPE1_LLS_L1_PARENT */ "ES PIPE 1 L1 Parent Database", 2837 /* ES_PIPE1_LLS_L1_PARENT_STATE */ "ES PIPE 1 L1 Parent State Database", 2838 /* ES_PIPE1_LLS_L1_WERR_MAX_SC */ "ES PIPE 1 L1 Max Surplus Count Database", 2839 /* ES_PIPE1_LLS_L1_WERR_NEXT */ "ES PIPE 1 L1 Child WERR Linked List Next Database", 2840 /* ES_PIPE1_LLS_L1_XOFF */ "ES PIPE 1 Port XOFF Database", 2841 /* ES_PIPE1_LLS_L2_CHILD_STATE1 */ "ES PIPE 1 L2 Child state database", 2842 /* ES_PIPE1_LLS_L2_CHILD_WEIGHT_CFG */ "ES PIPE 1 L2 Child Weight Config and count Database", 2843 /* ES_PIPE1_LLS_L2_CHILD_WEIGHT_WORKING */ "ES PIPE 1 L2 Child Working Weight and count Database", 2844 /* ES_PIPE1_LLS_L2_ERROR */ "ES PIPE 1 L2 Error database containing difference between expected scheduling amount and actual scheduling amount", 2845 /* ES_PIPE1_LLS_L2_MIN_NEXT */ "ES PIPE 1 L2 Child MIN Linked List Next Database 4 entries per word", 2846 /* ES_PIPE1_LLS_L2_PARENT */ "ES PIPE 1 L2 Parent Database", 2847 /* ES_PIPE1_LLS_L2_WERR_NEXT */ "ES PIPE 1 L2 Child WERR Linked List Next Database 4 entries per word", 2848 /* ES_PIPE1_LLS_L2_XOFF */ "ES PIPE 1 L2 XOFF Database", 2849 /* ES_PIPE1_LLS_PORT_HEADS_TAILS */ "ES PIPE 1 Port Heads Tails Database", 2850 /* ES_PIPE1_LLS_PORT_MEMA_CONFIG */ "ES PIPE 1 Port Configuration Database. NOTE : This is a replicated database, so contents must match ES_PIPE1_LLS_PORT_MEMB_CONFIG", 2851 /* ES_PIPE1_LLS_PORT_MEMB_CONFIG */ "ES PIPE 1 Port Configuration Database. NOTE : This is a replicated database, so contents must match ES_PIPE1_LLS_PORT_MEMA_CONFIG", 2852 /* ES_PIPE1_LLS_PORT_PARENT_STATE */ "ES PIPE 1 Port Parent State Database", 2853 /* ES_PIPE1_LLS_PORT_WERR_MAX_SC */ "ES PIPE 1 Port Max Surplus Count Database", 2854 /* ES_PIPE1_TDM_TABLE_0 */ "MMU to EPIPE Arbiter TDM Table 0, PIPE X", 2855 /* ES_PIPE1_TDM_TABLE_1 */ "MMU to EPIPE Arbiter TDM Table 1 (shadow table), PIPE X", 2856 /* ETPPA_ACCEPTABLE_FRAME_TYPE_TABLE */ "Acceptable Frame Type Table used to configure per tag format (3 tags without the priority bit) and per PP-PPCT. Acceptable-Frame-Type-Profile", 2857 /* ETPPA_CFG_FHEI_UPPER_LAYER_TYPE_MAP */ "Mapping J-Mode Fhei-Upper-Layer-Protocol(4),Fhei-Cw(1) to J2 Fhei-Upper-Layer-Type(5)", 2858 /* ETPPA_CFG_INLIF_DP_PROFILE_MAP */ "DP INLIF Profile for Inner and Outer PCP-DEI mapping in IVE, according to IN-LIF Profile from FHEI. 4 sets of INLIF_DP_Profile_outer,INLIF_DP_Profile_inner for 256 IN-LIF Profiles", 2859 /* ETPPA_CFG_INLIF_PROFILE_MAPPED_IN_JERICHO_MODE */ "Backwards compatibility (for J-Mode):\n Inlif_profile = F(FHEI.In-LIF-Profile(2),PPH.In-LIF-Orientation(2), PPH.Reserved(2))", 2860 /* ETPPA_CFG_MAP_INGRESS_REMARK_PROFILE */ "Mapping InlifProfile(8) to IngressRemarkProfile(3)", 2861 /* ETPPA_DSP_DATA_TABLE */ "ETPP DSP mapping Table", 2862 /* ETPPA_EEI_MPLS_PUSH_2_EES_MAP */ "Mapping the EEI Type (3) to eei_mpls_push.Type(6),Data(94)", 2863 /* ETPPA_ETPP_BYPASS_CTRL */ "ETPP Bypass Control Memory", 2864 /* ETPPA_ETPP_BYPASS_DATA */ "ETPP Bypass Data Memory", 2865 /* ETPPA_FHEI_MPLS_UPPER_LAYER_PROTOCOL_TO_PES_MAPPING_TABLE */ "Mapping FHEI Upper Layer Protocol(5b) to PES Access1 parsing context (5b). Table has 32 entries.", 2866 /* ETPPA_IVEC_TABLE */ "Ingress VLAN editing command.\n This table has 128 entries. It is pointed by FHEI.Ingress-VLAN-Edit-Command", 2867 /* ETPPA_JERICHO_INGRESS_NWK_QOS_TABLE */ "Jericho Mode Ingress Network QOS Mapping Table", 2868 /* ETPPA_LAYER_NWK_QOS_TABLE */ "Layer Network QOS Mapping Table", 2869 /* ETPPA_LIF_EXTENSION_FORMAT_CFG */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2870 /* ETPPA_MEM_220000 */ "INTERNAL", 2871 /* ETPPA_MEM_240000 */ "INTERNAL", 2872 /* ETPPA_MEM_400000 */ "INTERNAL", 2873 /* ETPPA_MEM_1000000 */ "INTERNAL", 2874 /* ETPPA_MEM_2400000 */ "INTERNAL", 2875 /* ETPPA_MEM_10F0000 */ "INTERNAL", 2876 /* ETPPA_MEM_11E0000 */ "INTERNAL", 2877 /* ETPPA_MEM_12D0000 */ "INTERNAL", 2878 /* ETPPA_MEM_13C0000 */ "INTERNAL", 2879 /* ETPPA_MEM_4F0000 */ "INTERNAL", 2880 /* ETPPA_MEM_5E0000 */ "INTERNAL", 2881 /* ETPPA_MEM_6D0000 */ "INTERNAL", 2882 /* ETPPA_MEM_7C0000 */ "INTERNAL", 2883 /* ETPPA_MEM_F000000 */ "INTERNAL", 2884 /* ETPPA_NETWORK_HEADERS_FIFO */ "This FIFO hold lower 128b of the packet header while the block is parsing the system headers. This is concatenated back to the packet before the parsing of the network headers.", 2885 /* ETPPA_PARSING_START_TYPE_MAPPING_TABLE */ "Parsing start type to PES protocol type mapping table , used for mapping the (ftmh) parsing start type to Network headers PES protocol type. Table has 32 entries.", 2886 /* ETPPA_PCP_DEI_DP_MAPPING_TABLE */ "PCP-DEI Mapping Table for IVE, maps DP+INLIF_Profile+Selected_PCP_DEI to new PCP-DEI", 2887 /* ETPPA_PER_PORT_TABLE */ "ETPP Per Port Attributes", 2888 /* ETPPA_PRP_EES_ARR_CONFIGURATION */ "ETPP PRP EES ARR Format Configuration", 2889 /* ETPPA_PRP_EES_ARR_PREFIX_TABLE */ "ETPP PRP EES ARR Prefix Table", 2890 /* ETPPA_PRP_FES_MASK_BITS_TABLE */ "Fes Mask Bits\n Each field of the FES outputs as a mask bits (two option of mask bits for each entry(field)).", 2891 /* ETPPA_PRP_FES_PROGRAM_TABLE */ "Program Instruction Table per program for all 8 keys (all 8 FES)\n The number of lines of the memory is derived as a result of the type (there are 6bits type)\n All the 8 FES use this memory in the relevant fields (0-7)", 2892 /* ETPPA_PRP_FWD_CODE_CAM */ "ETPPA PRP Forward Code Selection CAM", 2893 /* ETPPA_PRP_NETWORK_HEADER_FIFO */ "Pipe-FIFO - Before MDB results.\n The FIFO will wait to the data from the EEDB (if cfg_eedb_enabled valid)", 2894 /* ETPPA_PRP_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 2895 /* ETPPA_PRP_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 2896 /* ETPPA_PRP_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 2897 /* ETPPA_PRP_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 2898 /* ETPPA_PRP_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 2899 /* ETPPA_PRP_PEM_CAM */ "ETPP PRP PEM Context Selection CAM", 2900 /* ETPPA_PRP_SYSTEM_HEADER_FIFO */ "Pipe-FIFO - Before MDB results.\n The FIFO will wait to the data from the EEDB (if cfg_eedb_enabled valid) or the network_header(if the cfg_eedb_enabled is not valid)", 2901 /* ETPPA_SYSTEM_HEADERS_CONTAINER_FIFO */ "This FIFO is located after the PSG and used to hold the parsed system headers until a response from MCDB access has arrived", 2902 /* ETPPA_TERMINATION_CONTEXT_SELECTION_CAM */ "Termination Context Selection - maps several fields to termination context(6).\n Rows 0-31", 2903 /* ETPPA_TM_FIELDS_FIFO */ "This FIFO holds several pipe fields during the parser block. Fields are dependent if the parser is instanced in ERPP or ETPP\n ERPP:\n 4'd0,\n p0_first_packet, //width = 1\n p0_tc_map_profile, //width = 4\n p0_mc_pp_dsp, //width = 9\n p0_discard, //width = 1\n p0_cud_outlif_or_mcdb_ptr //width = 22\n p0_pem_is_applet, //width = 1\n p0_pem_is_applet, //width = 1\n ...", 2904 /* ETPPB_ADDITIONAL_HEADERS_MAP_TABLE_0 */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for the first (outermost) additional headers builder", 2905 /* ETPPB_ADDITIONAL_HEADERS_MAP_TABLE_1 */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for the second additional headers builder", 2906 /* ETPPB_ADDITIONAL_HEADERS_MAP_TABLE_2 */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for the third (innermost) additional headers builder", 2907 /* ETPPB_ADDITIONAL_HEADERS_PROFILE_MAP */ "Address = LIF_Additional_Headers_Profile(5b), ContextInfoTablecontext.Additional_Headers_Profile(4b)", 2908 /* ETPPB_BIT_CRUNCHER_DOUBLE_INSTRUCTION */ "Double instruction and candidate header select format", 2909 /* ETPPB_BIT_CRUNCHER_INSTRUCTION */ "Single Bit Cruncher Instructions structure", 2910 /* ETPPB_CFG_ENC_MAP_PROTOCOL_QOS */ "Protocol QOS Mapping Table\n MapQoS-VAR-Map(5), Type(3) to Protocol-QoS-Map(5), OuLIF-RemarkOrKeep(1)", 2911 /* ETPPB_CURRENT_NEXT_PROTOCOL_MAP */ "Address = Current_Next_Protocol_Namespace(3b), Current_Protocol-Type(5b)", 2912 /* ETPPB_EGRESS_MEMBERSHIP */ "Per VLAN/VSI Port membership", 2913 /* ETPPB_ENCAPSULATION_2_CONTEXT_ENABLERS */ "Per Context variables", 2914 /* ETPPB_ENCAPSULATION_2_DATA_FIFO */ "Per Context variables", 2915 /* ETPPB_ENCAPSULATION_3_CONTEXT_ENABLERS */ "Per Context variables", 2916 /* ETPPB_ENCAPSULATION_3_CONTEXT_SELECTION_CAM */ "ETPP Encapsulation3 Stage Context Selection CAM", 2917 /* ETPPB_ENCAPSULATION_3_DATA_FIFO */ "Per Context variables", 2918 /* ETPPB_ENCAPSULATION_4_CONTEXT_ENABLERS */ "Per Context variables", 2919 /* ETPPB_ENCAPSULATION_4_CONTEXT_SELECTION_CAM */ "ETPP Encapsulation4 Stage Context Selection CAM", 2920 /* ETPPB_ENCAPSULATION_4_DATA_FIFO */ "Per Context variables", 2921 /* ETPPB_ENCAPSULATION_5_CONTEXT_ENABLERS */ "Per Context variables", 2922 /* ETPPB_ENCAPSULATION_5_CONTEXT_SELECTION_CAM */ "ETPP Encapsulation5 Stage Context Selection CAM", 2923 /* ETPPB_ENCAPSULATION_5_DATA_FIFO */ "Per Context variables", 2924 /* ETPPB_ENC_1_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 8 double instructions.", 2925 /* ETPPB_ENC_1_CANDIDATE_HDR_FIFO */ "Encapsulation1 Candidate Header FIFO", 2926 /* ETPPB_ENC_1_CONTEXT_FIFO */ "Encapsulation1 Context FIFO", 2927 /* ETPPB_ENC_2_ARR_0_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2928 /* ETPPB_ENC_2_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 8 double instructions.", 2929 /* ETPPB_ENC_2_CANDIDATE_HDR_FIFO */ "Encapsulation2 Candidate Header FIFO", 2930 /* ETPPB_ENC_2_CONSTANT_TABLE */ "32 bit Constant value Per BitCrunch Context", 2931 /* ETPPB_ENC_2_CONTEXT_FIFO */ "Encapsulation2 Context FIFO", 2932 /* ETPPB_ENC_2_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 2933 /* ETPPB_ENC_2_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 2934 /* ETPPB_ENC_2_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 2935 /* ETPPB_ENC_2_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 2936 /* ETPPB_ENC_2_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 2937 /* ETPPB_ENC_2_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 2938 /* ETPPB_ENC_3_ARR_0_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2939 /* ETPPB_ENC_3_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 8 double instructions.", 2940 /* ETPPB_ENC_3_CANDIDATE_HDR_FIFO */ "Encapsulation3 Candidate Header FIFO", 2941 /* ETPPB_ENC_3_CONSTANT_TABLE */ "32 bit Constant value Per BitCrunch Context", 2942 /* ETPPB_ENC_3_CONTEXT_FIFO */ "Encapsulation3 Context FIFO", 2943 /* ETPPB_ENC_3_CONTEXT_SELECTION_PER_PORT_PROFILE */ "Address = Out-PP-Port\n Output - 2 bit per port profile for next stage context selection", 2944 /* ETPPB_ENC_3_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 2945 /* ETPPB_ENC_3_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 2946 /* ETPPB_ENC_3_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 2947 /* ETPPB_ENC_3_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 2948 /* ETPPB_ENC_3_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 2949 /* ETPPB_ENC_3_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 2950 /* ETPPB_ENC_4_ARR_0_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2951 /* ETPPB_ENC_4_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 8 double instructions.", 2952 /* ETPPB_ENC_4_CANDIDATE_HDR_FIFO */ "Encapsulation4 Candidate Header FIFO", 2953 /* ETPPB_ENC_4_CONSTANT_TABLE */ "32 bit Constant value Per BitCrunch Context", 2954 /* ETPPB_ENC_4_CONTEXT_FIFO */ "Encapsulation4 Context FIFO", 2955 /* ETPPB_ENC_4_CONTEXT_SELECTION_PER_PORT_PROFILE */ "Address = Out-PP-Port\n Output - 2 bit per port profile for next stage context selection", 2956 /* ETPPB_ENC_4_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 2957 /* ETPPB_ENC_4_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 2958 /* ETPPB_ENC_4_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 2959 /* ETPPB_ENC_4_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 2960 /* ETPPB_ENC_4_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 2961 /* ETPPB_ENC_4_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 2962 /* ETPPB_ENC_5_ARR_0_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2963 /* ETPPB_ENC_5_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 8 double instructions.", 2964 /* ETPPB_ENC_5_CANDIDATE_HDR_FIFO */ "Encapsulation5 Candidate Header FIFO", 2965 /* ETPPB_ENC_5_CONSTANT_TABLE */ "32 bit Constant value Per BitCrunch Context", 2966 /* ETPPB_ENC_5_CONTEXT_FIFO */ "Encapsulation5 Context FIFO", 2967 /* ETPPB_ENC_5_CONTEXT_SELECTION_PER_PORT_PROFILE */ "Address = Out-PP-Port\n Output - 2 bit per port profile for next stage context selection", 2968 /* ETPPB_ENC_5_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 2969 /* ETPPB_ENC_5_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 2970 /* ETPPB_ENC_5_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 2971 /* ETPPB_ENC_5_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 2972 /* ETPPB_ENC_5_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 2973 /* ETPPB_ENC_5_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 2974 /* ETPPB_ENC_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 2975 /* ETPPB_FWD_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 8 double instructions.", 2976 /* ETPPB_FWD_CANDIDATE_HDR_FIFO */ "Forwarding Candidate Header FIFO", 2977 /* ETPPB_FWD_CONTEXT_FIFO */ "Forwarding Context FIFO", 2978 /* ETPPB_MAIN_HEADER_MAP_TABLE */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for main header", 2979 /* ETPPB_MEM_500000 */ "INTERNAL", 2980 /* ETPPB_MEM_510000 */ "INTERNAL", 2981 /* ETPPB_MEM_520000 */ "INTERNAL", 2982 /* ETPPB_MEM_600000 */ "INTERNAL", 2983 /* ETPPB_MEM_620000 */ "INTERNAL", 2984 /* ETPPB_MEM_700000 */ "INTERNAL", 2985 /* ETPPB_MEM_720000 */ "INTERNAL", 2986 /* ETPPB_MEM_800000 */ "INTERNAL", 2987 /* ETPPB_MEM_820000 */ "INTERNAL", 2988 /* ETPPB_MEM_1500000 */ "INTERNAL", 2989 /* ETPPB_MEM_1520000 */ "INTERNAL", 2990 /* ETPPB_MEM_510000_1 */ "INTERNAL", 2991 /* ETPPB_MEM_510000_2 */ "INTERNAL", 2992 /* ETPPB_MEM_610000_0 */ "INTERNAL", 2993 /* ETPPB_MEM_810000_0 */ "INTERNAL", 2994 /* ETPPB_MEM_F000000 */ "INTERNAL", 2995 /* ETPPB_MTU_MAP_TABLE */ "Used For MTU-Filter in FWD&ENC\n address5:0 = mtu_profile(3b), protocol_type_compressed(3b)", 2996 /* ETPPB_NEW_QOS_MAP */ "New QOS Mapping Table\n Map Protocol-QoS-Map(5), QoS&DP(10) to New-QoS-VAR(8)\n Table is accessed with Address14:4 where:\n Address = Protocol-QoS-Map(5), QoS&DP(10)", 2997 /* ETPPB_NWK_QOS_IDX_MAP */ "Map Nwk-QoS-Idx(5b) to Pipe-Mapped-QoS&DP(10b), Pipe-Nwk-QoS-Var-O2(8b)", 2998 /* ETPPB_PROTOCOL_TYPE_COMPRESSED_MAP */ "Per Context variables", 2999 /* ETPPB_QOS_DP_MAP */ "New QOS and DP Mapping Table\n Map Remark-Profile.Nwk-Qos-Map(5), QoS&DP(10) to New-QoS&DP(10)\n Table is accessed with Address14:4 where:\n Address = Remark-Profile.Nwk-Qos-Map(5), QoS&DP(10)", 3000 /* ETPPB_SIT_PROFILE_MAP_TABLE */ "Address = SIT_Profile(3b)", 3001 /* ETPPB_SOURCE_ADRS_MAP_0 */ "Source_Address(128b), mapped by Source_Idx7:2 (6b)", 3002 /* ETPPB_SOURCE_ADRS_MAP_1 */ "Source_Address(128b), mapped by Source_Idx7:2 (6b)", 3003 /* ETPPB_STP_STATE */ "Per Topology ID Port STP State", 3004 /* ETPPB_TERM_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 16 double instructions.", 3005 /* ETPPB_TERM_CANDIDATE_HDR_FIFO */ "Termination Candidate Header FIFO", 3006 /* ETPPB_TERM_CONTEXT_FIFO */ "Termination Context FIFO", 3007 /* ETPPB_TRAP_BIT_CRUNCHER_PROGRAM */ "Memory of bit cruncher instructions per candidate header. Mem line per context. 12 double instructions.", 3008 /* ETPPB_TRAP_BYPASS_FIFO */ "Collecting Bypassed Data from FWD Stage, Bypassing the ENC stages", 3009 /* ETPPB_TRAP_CANDIDATE_HDR_FIFO */ "Trap Candidate Header FIFO", 3010 /* ETPPB_TRAP_CONSTANT_TABLE */ "Per Context 32 bit Constant", 3011 /* ETPPB_TRAP_CONTEXT_ENABLERS */ "Trap Forward Action Table - Forwarding information is retrieved from this Table - The trap_context is mapped to Forwarding information.\n This table is set as MultiCycle, and cannot be altered during traffic (on live contexts)", 3012 /* ETPPB_TRAP_CONTEXT_FIFO */ "Trap Context FIFO", 3013 /* ETPPB_TRAP_CONTEXT_SELECTION_CAM */ "ETPP Trap Stage Context Selection CAM", 3014 /* ETPPB_TRAP_CONTEXT_SELECTION_PER_PORT_PROFILE */ "Address = Out-PP-Port\n Output - 2 bit per port profile for next stage context selection", 3015 /* ETPPB_TRAP_ORIGINAL_FTMH_FIFO */ "Collecting original FTMH from the RQP", 3016 /* ETPPB_TRAP_OUTCOME_FIFO */ "Trap Additional Data FIFO", 3017 /* ETPPB_TRAP_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 3018 /* ETPPB_TRAP_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 3019 /* ETPPB_TRAP_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 3020 /* ETPPB_TRAP_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 3021 /* ETPPB_TRAP_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 3022 /* ETPPB_TRAP_PER_PP_PORT_TABLE */ "ETPP Trap Per Port Attributes", 3023 /* ETPPB_VID_MIRROR_PROFILE_TABLE */ "OutPortMirrorProfile is mapped by vid_index(3),Out_pp_port(8)", 3024 /* ETPPB_VLAN_EDIT_PROFILE_MAP_TABLE */ "Address = VLAN_Edit_Profile(6b)", 3025 /* ETPPC_ADDITIONAL_HEADERS_MAP_TABLE_0 */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for the first (outermost) additional headers builder", 3026 /* ETPPC_ADDITIONAL_HEADERS_MAP_TABLE_1 */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for the second additional headers builder", 3027 /* ETPPC_ADDITIONAL_HEADERS_MAP_TABLE_2 */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for the third (innermost) additional headers builder", 3028 /* ETPPC_ADDITIONAL_HEADERS_PROFILE_MAP */ "Address = LIF_Additional_Headers_Profile(5b), ContextInfoTablecontext.Additional_Headers_Profile(4b)", 3029 /* ETPPC_BIER_BIT_MASK_FIFO */ "FIFO all over the pipe (PRP, TERM) to be read in FWD stage. Assuming 512 CC.", 3030 /* ETPPC_CFG_EM_ACCESS_CMD */ "ESEM Access Command Table", 3031 /* ETPPC_CFG_ENC_MAP_PROTOCOL_QOS */ "Protocol QOS Mapping Table for ENC Stage\n MapQoS-VAR-Map(5), Type(3) to Protocol-QoS-Map(5), OuLIF-RemarkOrKeep(1).", 3032 /* ETPPC_CFG_FWD_MAP_PROTOCOL_QOS */ "Protocol QOS Mapping Table for FWD Stage\n MapQoS-VAR-Map(5), Type(3) to Protocol-QoS-Map(5), OuLIF-RemarkOrKeep(1).", 3033 /* ETPPC_CFG_INLIF_DP_PROFILE_MAP */ "DP INLIF Profile for Inner and Outer PCP-DEI mapping in IVE, according to IN-LIF Profile from FHEI. 4 sets of INLIF_DP_Profile_outer,INLIF_DP_Profile_inner for 256 IN-LIF Profiles", 3034 /* ETPPC_CFG_TERM_MAP_PROTOCOL_QOS */ "Protocol QOS Mapping Table for Termination Stage\n MapQoS-VAR-Map(5), Type(3) to Protocol-QoS-Map(5), OuLIF-RemarkOrKeep(1).", 3035 /* ETPPC_CURRENT_NEXT_PROTOCOL_MAP */ "Address = Current_Next_Protocol_Namespace(3b), Current_Protocol-Type(5b)", 3036 /* ETPPC_EDITING_PER_PORT_TABLE */ "Editing Per Port Table (Address = PP-DSP(8b))", 3037 /* ETPPC_ENCAPSULATION_1_CONTEXT_ENABLERS */ "Per Context variables", 3038 /* ETPPC_ENCAPSULATION_1_CONTEXT_SELECTION_CAM */ "ETPP Encapsulation1 Stage Context Selection CAM", 3039 /* ETPPC_ENCAPSULATION_1_DATA_FIFO */ "Per Context variables", 3040 /* ETPPC_ENCAPSULATION_2_CONTEXT_SELECTION_CAM */ "ETPP Encapsulation2 Stage Context Selection CAM", 3041 /* ETPPC_ENC_1_ARR_0_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 3042 /* ETPPC_ENC_1_CONSTANT_TABLE */ "32 bit Constant value Per BitCrunch Context", 3043 /* ETPPC_ENC_1_CONTEXT_SELECTION_PER_PORT_PROFILE */ "Address = Out-PP-Port\n Output - 2 bit per port profile for next stage context selection", 3044 /* ETPPC_ENC_1_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 3045 /* ETPPC_ENC_1_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 3046 /* ETPPC_ENC_1_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 3047 /* ETPPC_ENC_1_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 3048 /* ETPPC_ENC_1_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 3049 /* ETPPC_ENC_1_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 3050 /* ETPPC_ENC_2_CONTEXT_SELECTION_PER_PORT_PROFILE */ "Address = Out-PP-Port\n Output - 2 bit per port profile for next stage context selection", 3051 /* ETPPC_ENC_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 3052 /* ETPPC_ESEM_DEFAULT_RESULT_TABLE */ "ETPP Termination EES ARR Format Configuration", 3053 /* ETPPC_ESEM_RESULT_FIFO */ "ESEM1 & 2 Results FIFO", 3054 /* ETPPC_ETH_OAM_OPCODE_MAP */ "This table is used for mapping OAM-Header.Opcode to internal opcode used in the device.\n The index to the table is OAM-Header.Opcode7:0 and the result is 4 bits oam-opcode. The oam-opcode is used in accessing OAM-Trap-Engine by ETPP.", 3055 /* ETPPC_EXEM_RESULT_FIFO */ "EXEM Result FIFO", 3056 /* ETPPC_FORWARDING_CONTEXT_ENABLERS */ "Enable Context Table for FWD Stage", 3057 /* ETPPC_FORWARDING_CONTEXT_SELECTION_CAM */ "ETPP Forwarding Stage Context Selection CAM", 3058 /* ETPPC_FORWARDING_FORMAT_CONFIGURATION_TABLE_0 */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 3059 /* ETPPC_FORWARDING_FORMAT_CONFIGURATION_TABLE_1 */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position", 3060 /* ETPPC_FORWARDING_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 3061 /* ETPPC_FWD_BYPASS_FIFO */ "FIFO For Bypass", 3062 /* ETPPC_FWD_CONSTANT_TABLE */ "Constant bits to be sent to the bit cruncher", 3063 /* ETPPC_FWD_MAP_EGRESS_VLAN_EDITING_TABLE */ "The table contains EVE command configurations.\n Address: packet_is_mef_l2cp(1b), ive_incoming_tag_structure(5b), egrss_vlan_edit_profile(6b)", 3064 /* ETPPC_FWD_MAP_EGRESS_VLAN_EDIT_COMMAND_TABLE */ "EVE (Egress Vlan Edit) configurations.\n Address: egress_vlan_edit_command(7b)", 3065 /* ETPPC_FWD_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 3066 /* ETPPC_FWD_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 3067 /* ETPPC_FWD_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 3068 /* ETPPC_FWD_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 3069 /* ETPPC_FWD_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 3070 /* ETPPC_FWD_PLUS_1_REMARKING_TABLE */ "Forward Plus1 remarking configuration table.\n Accessed with: Fwd_Plus1_Lyr_Protocol(2), FWD_Plus1_Remark_Profile(2), ftmh_ECN_Enable(1), FWD_Plus1_Explicit_Remark_Profile(2)", 3071 /* ETPPC_INLIF_ORIENTATION_MAPPING */ "Inlif Profile to orientaion mapping", 3072 /* ETPPC_IVEC_TABLE */ "Ingress VLAN editing command.\n This table has 128 entries. It is pointed by FHEI.Ingress-VLAN-Edit-Command", 3073 /* ETPPC_LATENCY_PROFILE_TABLE */ "Latency Profile Table", 3074 /* ETPPC_LAYER_NWK_QOS_TABLE */ "Layer Network QOS Mapping Table", 3075 /* ETPPC_LLVP_TABLE */ "The Link Layer VLAN Processing (LLVP) table contains 1024 entries, each entry maps a concatenation of Out-PP-Port.LLVP-Profile(3) , IVE-Packet-Tag-Format(7) to VLAN edit command parameters. Each field in this table represents such a parameter.", 3076 /* ETPPC_MAIN_HEADER_MAP_TABLE */ "Address = Additional_Headers_Profile(5b)\n\n Contains data for main header", 3077 /* ETPPC_MAP_FWD_QOS_DP_TO_TYPE_FWD */ "Configurations for QoS and DP calculations. Mapping QoS and DP into various properties to be used in procedures.\n Address: forward_code(6b), ftmh_ecn_enable(1b)", 3078 /* ETPPC_MAX_LATENCY_TRACK */ "The ETPP measures latency from the packet OAM-TS extension.\n In this memory the 8 maximal latency's are kept, with the pointer associated with them", 3079 /* ETPPC_MEM_0 */ "INTERNAL", 3080 /* ETPPC_MEM_20000 */ "INTERNAL", 3081 /* ETPPC_MEM_140000 */ "INTERNAL", 3082 /* ETPPC_MEM_160000 */ "INTERNAL", 3083 /* ETPPC_MEM_180000 */ "INTERNAL", 3084 /* ETPPC_MEM_10000_0 */ "INTERNAL", 3085 /* ETPPC_MEM_1A0000 */ "INTERNAL", 3086 /* ETPPC_MEM_F000000 */ "INTERNAL", 3087 /* ETPPC_MTU_MAP_TABLE */ "Used For MTU-Filter in FWD&ENC\n address5:0 = mtu_profile(3b, protocol_type_compressed(3b)", 3088 /* ETPPC_MY_CFM_MAC_TABLE */ "My-CFM-MAC table. The table maps My-CFM-MAC address to OAM trap engine. The table contains 256 entries, one entry per PP port.\n The purpose of the register to decide if to trap a packet to the OAM engine. The field MacLsbsBitmap is a bitmap, with every bit corresponding to MAC DA7:0. If the bit corresponding with MAC DA7:0 is set and MacMsbs field in the the table is equal to MAC DA47:8 then OAM-My-CFM-MAC is set.", 3089 /* ETPPC_NEW_QOS_MAP */ "New QOS Mapping Table\n Map Protocol-QoS-Map(5), QoS&DP(10) to New-QoS-VAR(8)\n Table is accessed with Address14:4 where:\n Address = Protocol-QoS-Map(5), QoS&DP(10)", 3090 /* ETPPC_NWK_QOS_IDX_MAP */ "Map Nwk-QoS-Idx(5b) to Pipe-Mapped-QoS&DP(10b), Pipe-Nwk-QoS-Var-O2(8b)", 3091 /* ETPPC_OAMA */ "Map MP type (4b), Opcode (4b), MP Profile (4b), My CFM MAC (1b), Inject, DA is MC", 3092 /* ETPPC_OAMB */ "Map OAM-ACC-MEP-MP-Prof (4), OAM-Opcode (4), My-CFM-MAC (1), Inject(1), DA-IS-MC(1)", 3093 /* ETPPC_OAM_COUNTER_DISABLE_MAP */ "enable the counter per counter interface. A bitmap with a selector nof_valid_lm_lifs(2),oamb_dis_cnt(1),in_lif_valid_for_lm(1), mp_type(4)", 3094 /* ETPPC_OAM_KEY_TABLE */ "OAM Key configuration table.\n Accessed with:\n packet_is_oam,oam_ctr_ptr_vld,nof_valid_lm_lifs(2),oam_injection", 3095 /* ETPPC_OAM_MP_TYPE_MAP */ "MP Type Map used in MP type calculation oam_is_bfd(1),nof_mep_below_mdl(3),mdl_mp_type(2),nof_above_mdl(3)", 3096 /* ETPPC_OEM_RESULT_FIFO */ "OEM Results FIFO - OEM1 (MEP DB), OEM2/3/4 (LIF DB)", 3097 /* ETPPC_PCP_DEI_DP_MAPPING_TABLE */ "PCP-DEI Mapping Table for IVE, maps DP+INLIF_Profile+Selected_PCP_DEI to new PCP-DEI", 3098 /* ETPPC_PROTECTION_TABLE */ "Prtoection Data Base for Egress Protection.\n Table is accessed using ProtectionPointer17:5", 3099 /* ETPPC_PROTOCOL_TYPE_COMPRESSED_MAP */ "Per Context variables", 3100 /* ETPPC_QOS_DP_MAP */ "New QOS and DP Mapping Table\n Map Remark-Profile.Nwk-Qos-Map(5), QoS&DP(10) to New-QoS&DP(10)\n Table is accessed with Address14:4 where:\n Address = Remark-Profile.Nwk-Qos-Map(5), QoS&DP(10)", 3101 /* ETPPC_SIT_PROFILE_MAP_TABLE */ "Address = SIT_Profile(3b)", 3102 /* ETPPC_SOURCE_ADRS_MAP */ "Source_Address(128b), mapped by Source_Idx7:2 (6b)", 3103 /* ETPPC_TERMINATION_CONTEXT_ENABLERS */ "Per Context Enablers.\n This table is set as MultiCycle towards the design. A live context cannot be changed while traffic flow.", 3104 /* ETPPC_TERM_CONSTANT_TABLE */ "Per Context Constant value for Candidate header Control BUS", 3105 /* ETPPC_TERM_ETPS_ARR_1_CONFIGURATION */ "ETPP Termination EES ARR1 Format Configuration", 3106 /* ETPPC_TERM_ETPS_ARR_2_CONFIGURATION */ "ETPP Termination EES ARR2 Format Configuration", 3107 /* ETPPC_TERM_ETPS_ARR_PREFIX_TABLE */ "ETPP Termination ETPS ARR Prefix Table", 3108 /* ETPPC_TERM_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 3109 /* ETPPC_TERM_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 3110 /* ETPPC_TERM_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 3111 /* ETPPC_TERM_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 3112 /* ETPPC_TERM_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 3113 /* ETPPC_TERM_PIPE_FIFO_1 */ "Termination Pipe FIFO (first).\n Holds Data while accessing the MDB (ESEM and OAM)", 3114 /* ETPPC_TERM_PIPE_FIFO_2 */ "Termination Pipe FIFO (first).\n Holds Data while accessing the MRPS and CRPS", 3115 /* ETPPC_VLAN_EDIT_PROFILE_MAP_TABLE */ "Address = VLAN_Edit_Profile(6b)", 3116 /* ETPPC_VSD_RESULT_FIFO */ "VSD 1 & 2 Results FIFO", 3117 /* ETRAP_COLOR_EN_EGR_PORT_BMP */ "Egr port bitmap for enabling color re-assignment.", 3118 /* ETRAP_FILTER_0_TABLE */ "Elephant trap bloom filter counter table.", 3119 /* ETRAP_FILTER_0_TABLE_PIPE0 */ "Elephant trap bloom filter counter table.", 3120 /* ETRAP_FILTER_0_TABLE_PIPE1 */ "Elephant trap bloom filter counter table.", 3121 /* ETRAP_FILTER_0_TABLE_PIPE2 */ "Elephant trap bloom filter counter table.", 3122 /* ETRAP_FILTER_0_TABLE_PIPE3 */ "Elephant trap bloom filter counter table.", 3123 /* ETRAP_FILTER_0_TABLE_PIPE4 */ "Elephant trap bloom filter counter table.", 3124 /* ETRAP_FILTER_0_TABLE_PIPE5 */ "Elephant trap bloom filter counter table.", 3125 /* ETRAP_FILTER_0_TABLE_PIPE6 */ "Elephant trap bloom filter counter table.", 3126 /* ETRAP_FILTER_0_TABLE_PIPE7 */ "Elephant trap bloom filter counter table.", 3127 /* ETRAP_FILTER_1_TABLE */ "Elephant trap bloom filter counter table.", 3128 /* ETRAP_FILTER_1_TABLE_PIPE0 */ "Elephant trap bloom filter counter table.", 3129 /* ETRAP_FILTER_1_TABLE_PIPE1 */ "Elephant trap bloom filter counter table.", 3130 /* ETRAP_FILTER_1_TABLE_PIPE2 */ "Elephant trap bloom filter counter table.", 3131 /* ETRAP_FILTER_1_TABLE_PIPE3 */ "Elephant trap bloom filter counter table.", 3132 /* ETRAP_FILTER_1_TABLE_PIPE4 */ "Elephant trap bloom filter counter table.", 3133 /* ETRAP_FILTER_1_TABLE_PIPE5 */ "Elephant trap bloom filter counter table.", 3134 /* ETRAP_FILTER_1_TABLE_PIPE6 */ "Elephant trap bloom filter counter table.", 3135 /* ETRAP_FILTER_1_TABLE_PIPE7 */ "Elephant trap bloom filter counter table.", 3136 /* ETRAP_FILTER_2_TABLE */ "Elephant trap bloom filter counter table.", 3137 /* ETRAP_FILTER_2_TABLE_PIPE0 */ "Elephant trap bloom filter counter table.", 3138 /* ETRAP_FILTER_2_TABLE_PIPE1 */ "Elephant trap bloom filter counter table.", 3139 /* ETRAP_FILTER_2_TABLE_PIPE2 */ "Elephant trap bloom filter counter table.", 3140 /* ETRAP_FILTER_2_TABLE_PIPE3 */ "Elephant trap bloom filter counter table.", 3141 /* ETRAP_FILTER_2_TABLE_PIPE4 */ "Elephant trap bloom filter counter table.", 3142 /* ETRAP_FILTER_2_TABLE_PIPE5 */ "Elephant trap bloom filter counter table.", 3143 /* ETRAP_FILTER_2_TABLE_PIPE6 */ "Elephant trap bloom filter counter table.", 3144 /* ETRAP_FILTER_2_TABLE_PIPE7 */ "Elephant trap bloom filter counter table.", 3145 /* ETRAP_FILTER_3_TABLE */ "Elephant trap bloom filter counter table.", 3146 /* ETRAP_FILTER_3_TABLE_PIPE0 */ "Elephant trap bloom filter counter table.", 3147 /* ETRAP_FILTER_3_TABLE_PIPE1 */ "Elephant trap bloom filter counter table.", 3148 /* ETRAP_FILTER_3_TABLE_PIPE2 */ "Elephant trap bloom filter counter table.", 3149 /* ETRAP_FILTER_3_TABLE_PIPE3 */ "Elephant trap bloom filter counter table.", 3150 /* ETRAP_FILTER_3_TABLE_PIPE4 */ "Elephant trap bloom filter counter table.", 3151 /* ETRAP_FILTER_3_TABLE_PIPE5 */ "Elephant trap bloom filter counter table.", 3152 /* ETRAP_FILTER_3_TABLE_PIPE6 */ "Elephant trap bloom filter counter table.", 3153 /* ETRAP_FILTER_3_TABLE_PIPE7 */ "Elephant trap bloom filter counter table.", 3154 /* ETRAP_FLOW_COUNT_LEFT_TABLE */ "Elephant trap flow table (counter portion).", 3155 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE0 */ "Elephant trap flow table (counter portion).", 3156 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE1 */ "Elephant trap flow table (counter portion).", 3157 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE2 */ "Elephant trap flow table (counter portion).", 3158 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE3 */ "Elephant trap flow table (counter portion).", 3159 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE4 */ "Elephant trap flow table (counter portion).", 3160 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE5 */ "Elephant trap flow table (counter portion).", 3161 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE6 */ "Elephant trap flow table (counter portion).", 3162 /* ETRAP_FLOW_COUNT_LEFT_TABLE_PIPE7 */ "Elephant trap flow table (counter portion).", 3163 /* ETRAP_FLOW_COUNT_RIGHT_TABLE */ "Elephant trap flow table (counter portion).", 3164 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE0 */ "Elephant trap flow table (counter portion).", 3165 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE1 */ "Elephant trap flow table (counter portion).", 3166 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE2 */ "Elephant trap flow table (counter portion).", 3167 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE3 */ "Elephant trap flow table (counter portion).", 3168 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE4 */ "Elephant trap flow table (counter portion).", 3169 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE5 */ "Elephant trap flow table (counter portion).", 3170 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE6 */ "Elephant trap flow table (counter portion).", 3171 /* ETRAP_FLOW_COUNT_RIGHT_TABLE_PIPE7 */ "Elephant trap flow table (counter portion).", 3172 /* ETRAP_FLOW_CTRL_LEFT_TABLE */ "Elephant trap flow table (control portion).", 3173 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE0 */ "Elephant trap flow table (control portion).", 3174 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE1 */ "Elephant trap flow table (control portion).", 3175 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE2 */ "Elephant trap flow table (control portion).", 3176 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE3 */ "Elephant trap flow table (control portion).", 3177 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE4 */ "Elephant trap flow table (control portion).", 3178 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE5 */ "Elephant trap flow table (control portion).", 3179 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE6 */ "Elephant trap flow table (control portion).", 3180 /* ETRAP_FLOW_CTRL_LEFT_TABLE_PIPE7 */ "Elephant trap flow table (control portion).", 3181 /* ETRAP_FLOW_CTRL_RIGHT_TABLE */ "Elephant trap flow table (control portion).", 3182 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE0 */ "Elephant trap flow table (control portion).", 3183 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE1 */ "Elephant trap flow table (control portion).", 3184 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE2 */ "Elephant trap flow table (control portion).", 3185 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE3 */ "Elephant trap flow table (control portion).", 3186 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE4 */ "Elephant trap flow table (control portion).", 3187 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE5 */ "Elephant trap flow table (control portion).", 3188 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE6 */ "Elephant trap flow table (control portion).", 3189 /* ETRAP_FLOW_CTRL_RIGHT_TABLE_PIPE7 */ "Elephant trap flow table (control portion).", 3190 /* ETRAP_FLOW_HASH_L0_TABLE */ "Elephant trap flow table (hash portion).", 3191 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3192 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3193 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3194 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3195 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3196 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3197 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3198 /* ETRAP_FLOW_HASH_L0_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3199 /* ETRAP_FLOW_HASH_L1_TABLE */ "Elephant trap flow table (hash portion).", 3200 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3201 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3202 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3203 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3204 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3205 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3206 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3207 /* ETRAP_FLOW_HASH_L1_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3208 /* ETRAP_FLOW_HASH_L2_TABLE */ "Elephant trap flow table (hash portion).", 3209 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3210 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3211 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3212 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3213 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3214 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3215 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3216 /* ETRAP_FLOW_HASH_L2_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3217 /* ETRAP_FLOW_HASH_L3_TABLE */ "Elephant trap flow table (hash portion).", 3218 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3219 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3220 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3221 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3222 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3223 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3224 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3225 /* ETRAP_FLOW_HASH_L3_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3226 /* ETRAP_FLOW_HASH_L4_TABLE */ "Elephant trap flow table (hash portion).", 3227 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3228 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3229 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3230 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3231 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3232 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3233 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3234 /* ETRAP_FLOW_HASH_L4_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3235 /* ETRAP_FLOW_HASH_R0_TABLE */ "Elephant trap flow table (hash portion).", 3236 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3237 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3238 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3239 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3240 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3241 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3242 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3243 /* ETRAP_FLOW_HASH_R0_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3244 /* ETRAP_FLOW_HASH_R1_TABLE */ "Elephant trap flow table (hash portion).", 3245 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3246 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3247 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3248 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3249 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3250 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3251 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3252 /* ETRAP_FLOW_HASH_R1_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3253 /* ETRAP_FLOW_HASH_R2_TABLE */ "Elephant trap flow table (hash portion).", 3254 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3255 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3256 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3257 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3258 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3259 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3260 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3261 /* ETRAP_FLOW_HASH_R2_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3262 /* ETRAP_FLOW_HASH_R3_TABLE */ "Elephant trap flow table (hash portion).", 3263 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3264 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3265 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3266 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3267 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3268 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3269 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3270 /* ETRAP_FLOW_HASH_R3_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3271 /* ETRAP_FLOW_HASH_R4_TABLE */ "Elephant trap flow table (hash portion).", 3272 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE0 */ "Elephant trap flow table (hash portion).", 3273 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE1 */ "Elephant trap flow table (hash portion).", 3274 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE2 */ "Elephant trap flow table (hash portion).", 3275 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE3 */ "Elephant trap flow table (hash portion).", 3276 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE4 */ "Elephant trap flow table (hash portion).", 3277 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE5 */ "Elephant trap flow table (hash portion).", 3278 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE6 */ "Elephant trap flow table (hash portion).", 3279 /* ETRAP_FLOW_HASH_R4_TABLE_PIPE7 */ "Elephant trap flow table (hash portion).", 3280 /* ETRAP_INT_PRI_REMAP_TABLE */ "Elephant trap internal priority remap table.", 3281 /* ETRAP_LKUP_EN_ING_PORT */ "Elephant trap lookup enable per ingress port.", 3282 /* ETRAP_QUEUE_EN_EGR_PORT_BMP */ "Egr port bitmap for enabling queue re-assignment.", 3283 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT */ "Elephant trap lookup enable per ingress port.", 3284 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3285 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3286 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3287 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3288 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3289 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3290 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3291 /* ETRAP_SAMPLE_FLOW_COUNT_LEFT_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3292 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT */ "Elephant trap lookup enable per ingress port.", 3293 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3294 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3295 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3296 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3297 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3298 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3299 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3300 /* ETRAP_SAMPLE_FLOW_COUNT_RIGHT_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3301 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT */ "Elephant trap lookup enable per ingress port.", 3302 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3303 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3304 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3305 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3306 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3307 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3308 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3309 /* ETRAP_SAMPLE_FLOW_CTRL_LEFT_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3310 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT */ "Elephant trap lookup enable per ingress port.", 3311 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3312 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3313 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3314 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3315 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3316 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3317 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3318 /* ETRAP_SAMPLE_FLOW_CTRL_RIGHT_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3319 /* ETRAP_SAMPLE_FLOW_HASH_L0 */ "Elephant trap lookup enable per ingress port.", 3320 /* ETRAP_SAMPLE_FLOW_HASH_L1 */ "Elephant trap lookup enable per ingress port.", 3321 /* ETRAP_SAMPLE_FLOW_HASH_L2 */ "Elephant trap lookup enable per ingress port.", 3322 /* ETRAP_SAMPLE_FLOW_HASH_L3 */ "Elephant trap lookup enable per ingress port.", 3323 /* ETRAP_SAMPLE_FLOW_HASH_L4 */ "Elephant trap lookup enable per ingress port.", 3324 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3325 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3326 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3327 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3328 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3329 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3330 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3331 /* ETRAP_SAMPLE_FLOW_HASH_L0_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3332 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3333 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3334 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3335 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3336 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3337 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3338 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3339 /* ETRAP_SAMPLE_FLOW_HASH_L1_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3340 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3341 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3342 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3343 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3344 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3345 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3346 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3347 /* ETRAP_SAMPLE_FLOW_HASH_L2_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3348 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3349 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3350 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3351 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3352 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3353 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3354 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3355 /* ETRAP_SAMPLE_FLOW_HASH_L3_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3356 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3357 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3358 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3359 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3360 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3361 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3362 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3363 /* ETRAP_SAMPLE_FLOW_HASH_L4_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3364 /* ETRAP_SAMPLE_FLOW_HASH_R0 */ "Elephant trap lookup enable per ingress port.", 3365 /* ETRAP_SAMPLE_FLOW_HASH_R1 */ "Elephant trap lookup enable per ingress port.", 3366 /* ETRAP_SAMPLE_FLOW_HASH_R2 */ "Elephant trap lookup enable per ingress port.", 3367 /* ETRAP_SAMPLE_FLOW_HASH_R3 */ "Elephant trap lookup enable per ingress port.", 3368 /* ETRAP_SAMPLE_FLOW_HASH_R4 */ "Elephant trap lookup enable per ingress port.", 3369 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3370 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3371 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3372 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3373 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3374 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3375 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3376 /* ETRAP_SAMPLE_FLOW_HASH_R0_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3377 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3378 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3379 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3380 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3381 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3382 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3383 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3384 /* ETRAP_SAMPLE_FLOW_HASH_R1_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3385 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3386 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3387 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3388 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3389 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3390 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3391 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3392 /* ETRAP_SAMPLE_FLOW_HASH_R2_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3393 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3394 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3395 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3396 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3397 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3398 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3399 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3400 /* ETRAP_SAMPLE_FLOW_HASH_R3_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3401 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE0 */ "Elephant trap lookup enable per ingress port.", 3402 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE1 */ "Elephant trap lookup enable per ingress port.", 3403 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE2 */ "Elephant trap lookup enable per ingress port.", 3404 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE3 */ "Elephant trap lookup enable per ingress port.", 3405 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE4 */ "Elephant trap lookup enable per ingress port.", 3406 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE5 */ "Elephant trap lookup enable per ingress port.", 3407 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE6 */ "Elephant trap lookup enable per ingress port.", 3408 /* ETRAP_SAMPLE_FLOW_HASH_R4_PIPE7 */ "Elephant trap lookup enable per ingress port.", 3409 /* ETU_DBG_REQ_REUSE_FREE_ENTRY */ "Request for reuse of free tcam entry", 3410 /* ETU_DBG_RX_LAST_RSP */ "The last response send back from TCAM", 3411 /* ETU_DBG_RX_RAW_RSP */ "Response for raw request", 3412 /* ETU_TX_RAW_REQ_DATA_WORD */ "ETU TX FIFO RAW_REQ access DATA WORD Portion", 3413 /* ET_INST_OPC_TABLE */ "Stores opcodes of Instructions used by ESMIF stage for searching databases in ext_tcam", 3414 /* ET_PA_XLAT */ "Defines mapping of 20bit ext_tcam_phy_adr to associated data entry adr in ext_sram, and also to on-chip hit bits.\n It is indexed by 6 msbs (bits 19:14) of ext_tcam_phy_adr[19:0]", 3415 /* ET_PA_XLAT_DEBUG */ "External tcam physical address translation table. All entries of the identical 256 deep PD memories can be read/write", 3416 /* ET_UINST_MEM */ "Each entry specifies a double micro-instruction that can be driven to ext_tcam.\n Mechanism if uinst_mem is intended to be used for INVALIDATing, SEARCHing entries in tables for which these commands are not supported.\n Also note that uinst_mem mechanism affects only the TCAM portion of entry. Associated Data is NOT altered - that must be done separately", 3417 /* EVNT_ASSIGNED_CMIC_ENGINE_TABLE */ "AssignedCmicEngineTable", 3418 /* EVNT_BINNING_TABLE */ "this table will contain the binning information", 3419 /* EVNT_CMIC_ENG_PROPERTIES */ "context properties (BD_addr in cmic, etc..)", 3420 /* EVNT_CONTEXT_PROPERTIES */ "context properties (BD_addr in cmic, etc..).\n 0 - RX\n 1 - TX", 3421 /* EVNT_DATA_BUFFER_RX */ "RX data buffer", 3422 /* EVNT_DATA_BUFFER_TX */ "TX data buffer", 3423 /* EVNT_EVENTS_MAIN_MEM */ "this table represents the main memory. The memory devided into banks as follow, this row is used for the defines of the all memory", 3424 /* EVNT_EVENTS_MAIN_MEM_BANK */ "tx events mem - contain Buffer descriptors and events data.\n Memory contains both Tx and Rx buffer descriptors and events data", 3425 /* EVNT_PROFILE_TABLE */ "events profiles table", 3426 /* EVNT_SPACE_REGIONS */ "Space Regions.\n RX - 0\n TX - 1", 3427 /* EVNT_TRANSACTION_ENGINE_BIT_MAPPING */ "Transaction Engine Mapping mem - mapping the event ID to transaction engine(s)", 3428 /* EVNT_TX_EVENT_ID_TO_CONTEXT_ID_MAP */ "mapping event ID to context ID", 3429 /* EXACT_MATCH_2 */ "ISS Table view for supporting 2 Exact Match Keys of width 128b or 160b.", 3430 /* EXACT_MATCH_4 */ "Table view when the ISS is in the 320b Search Mode for Exact Match searches.", 3431 /* EXACT_MATCH_2_ENTRY_ONLY */ "DATA ONLY View of the ISS table when supporting 2 search ekys(128b and 160b).", 3432 /* EXACT_MATCH_2_ENTRY_ONLY_PIPE0 */ "DATA ONLY View of the ISS table when supporting 2 search ekys(128b and 160b).", 3433 /* EXACT_MATCH_2_ENTRY_ONLY_PIPE1 */ "DATA ONLY View of the ISS table when supporting 2 search ekys(128b and 160b).", 3434 /* EXACT_MATCH_2_ENTRY_ONLY_PIPE2 */ "DATA ONLY View of the ISS table when supporting 2 search ekys(128b and 160b).", 3435 /* EXACT_MATCH_2_ENTRY_ONLY_PIPE3 */ "DATA ONLY View of the ISS table when supporting 2 search ekys(128b and 160b).", 3436 /* EXACT_MATCH_2_PIPE0 */ "ISS Table view for supporting 2 Exact Match Keys of width 128b or 160b.", 3437 /* EXACT_MATCH_2_PIPE1 */ "ISS Table view for supporting 2 Exact Match Keys of width 128b or 160b.", 3438 /* EXACT_MATCH_2_PIPE2 */ "ISS Table view for supporting 2 Exact Match Keys of width 128b or 160b.", 3439 /* EXACT_MATCH_2_PIPE3 */ "ISS Table view for supporting 2 Exact Match Keys of width 128b or 160b.", 3440 /* EXACT_MATCH_4_ENTRY_ONLY */ "Data ONLY view for the ISS table in 320b Search Mode for Exact Match Searches.", 3441 /* EXACT_MATCH_4_ENTRY_ONLY_PIPE0 */ "Data ONLY view for the ISS table in 320b Search Mode for Exact Match Searches.", 3442 /* EXACT_MATCH_4_ENTRY_ONLY_PIPE1 */ "Data ONLY view for the ISS table in 320b Search Mode for Exact Match Searches.", 3443 /* EXACT_MATCH_4_ENTRY_ONLY_PIPE2 */ "Data ONLY view for the ISS table in 320b Search Mode for Exact Match Searches.", 3444 /* EXACT_MATCH_4_ENTRY_ONLY_PIPE3 */ "Data ONLY view for the ISS table in 320b Search Mode for Exact Match Searches.", 3445 /* EXACT_MATCH_4_PIPE0 */ "Table view when the ISS is in the 320b Search Mode for Exact Match searches.", 3446 /* EXACT_MATCH_4_PIPE1 */ "Table view when the ISS is in the 320b Search Mode for Exact Match searches.", 3447 /* EXACT_MATCH_4_PIPE2 */ "Table view when the ISS is in the 320b Search Mode for Exact Match searches.", 3448 /* EXACT_MATCH_4_PIPE3 */ "Table view when the ISS is in the 320b Search Mode for Exact Match searches.", 3449 /* EXACT_MATCH_ACTION_PROFILE */ "Action Set Bitmap for first EM Lookup Data", 3450 /* EXACT_MATCH_ACTION_PROFILE_PIPE0 */ "Action Set Bitmap for first EM Lookup Data", 3451 /* EXACT_MATCH_ACTION_PROFILE_PIPE1 */ "Action Set Bitmap for first EM Lookup Data", 3452 /* EXACT_MATCH_ACTION_PROFILE_PIPE2 */ "Action Set Bitmap for first EM Lookup Data", 3453 /* EXACT_MATCH_ACTION_PROFILE_PIPE3 */ "Action Set Bitmap for first EM Lookup Data", 3454 /* EXACT_MATCH_ACTION_PROFILE_PIPE4 */ "Action Set Bitmap for first EM Lookup Data", 3455 /* EXACT_MATCH_ACTION_PROFILE_PIPE5 */ "Action Set Bitmap for first EM Lookup Data", 3456 /* EXACT_MATCH_ACTION_PROFILE_PIPE6 */ "Action Set Bitmap for first EM Lookup Data", 3457 /* EXACT_MATCH_ACTION_PROFILE_PIPE7 */ "Action Set Bitmap for first EM Lookup Data", 3458 /* EXACT_MATCH_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3459 /* EXACT_MATCH_ACTION_TABLE_A_PIPE0 */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3460 /* EXACT_MATCH_ACTION_TABLE_A_PIPE1 */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3461 /* EXACT_MATCH_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3462 /* EXACT_MATCH_ACTION_TABLE_B_PIPE0 */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3463 /* EXACT_MATCH_ACTION_TABLE_B_PIPE1 */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3464 /* EXACT_MATCH_DEFAULT_POLICY */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3465 /* EXACT_MATCH_DEFAULT_POLICY_PIPE0 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3466 /* EXACT_MATCH_DEFAULT_POLICY_PIPE1 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3467 /* EXACT_MATCH_DEFAULT_POLICY_PIPE2 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3468 /* EXACT_MATCH_DEFAULT_POLICY_PIPE3 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3469 /* EXACT_MATCH_DEFAULT_POLICY_PIPE4 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3470 /* EXACT_MATCH_DEFAULT_POLICY_PIPE5 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3471 /* EXACT_MATCH_DEFAULT_POLICY_PIPE6 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3472 /* EXACT_MATCH_DEFAULT_POLICY_PIPE7 */ "This Data Structure provides the default policy to be used if there is a miss in the EM Lookups.A packet can have 2 parallel lookups in this table.", 3473 /* EXACT_MATCH_ECC */ "ECC Table.", 3474 /* EXACT_MATCH_ECC_PIPE0 */ "ECC Table.", 3475 /* EXACT_MATCH_ECC_PIPE1 */ "ECC Table.", 3476 /* EXACT_MATCH_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 3477 /* EXACT_MATCH_HASH_CONTROL_PIPE0 */ "Hash Table control register (implemented as sbus table).", 3478 /* EXACT_MATCH_HASH_CONTROL_PIPE1 */ "Hash Table control register (implemented as sbus table).", 3479 /* EXACT_MATCH_HIT_ONLY */ "FP Exact Match Hit Bit Table", 3480 /* EXACT_MATCH_KEY_ATTRIBUTES */ "Key Attributes Table.", 3481 /* EXACT_MATCH_KEY_ATTRIBUTES_PIPE0 */ "Key Attributes Table.", 3482 /* EXACT_MATCH_KEY_ATTRIBUTES_PIPE1 */ "Key Attributes Table.", 3483 /* EXACT_MATCH_KEY_BUFFER */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3484 /* EXACT_MATCH_KEY_BUFFER_PIPE0 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3485 /* EXACT_MATCH_KEY_BUFFER_PIPE1 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3486 /* EXACT_MATCH_KEY_BUFFER_PIPE2 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3487 /* EXACT_MATCH_KEY_BUFFER_PIPE3 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3488 /* EXACT_MATCH_KEY_BUFFER_PIPE4 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3489 /* EXACT_MATCH_KEY_BUFFER_PIPE5 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3490 /* EXACT_MATCH_KEY_BUFFER_PIPE6 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3491 /* EXACT_MATCH_KEY_BUFFER_PIPE7 */ "Records lookup key of L3_ENTRY lookup for visibility packets.", 3492 /* EXACT_MATCH_KEY_GEN_MASK */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3493 /* EXACT_MATCH_KEY_GEN_MASK_PIPE0 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3494 /* EXACT_MATCH_KEY_GEN_MASK_PIPE1 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3495 /* EXACT_MATCH_KEY_GEN_MASK_PIPE2 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3496 /* EXACT_MATCH_KEY_GEN_MASK_PIPE3 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3497 /* EXACT_MATCH_KEY_GEN_MASK_PIPE4 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3498 /* EXACT_MATCH_KEY_GEN_MASK_PIPE5 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3499 /* EXACT_MATCH_KEY_GEN_MASK_PIPE6 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3500 /* EXACT_MATCH_KEY_GEN_MASK_PIPE7 */ "This data structure stores a per logical table mask for the Exact Match Keys.", 3501 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE */ "Key Generator Profile Table that provides instructions for Key Generation", 3502 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE0 */ "Key Generator Profile Table that provides instructions for Key Generation", 3503 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE1 */ "Key Generator Profile Table that provides instructions for Key Generation", 3504 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE2 */ "Key Generator Profile Table that provides instructions for Key Generation", 3505 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE3 */ "Key Generator Profile Table that provides instructions for Key Generation", 3506 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE4 */ "Key Generator Profile Table that provides instructions for Key Generation", 3507 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE5 */ "Key Generator Profile Table that provides instructions for Key Generation", 3508 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE6 */ "Key Generator Profile Table that provides instructions for Key Generation", 3509 /* EXACT_MATCH_KEY_GEN_PROGRAM_PROFILE_PIPE7 */ "Key Generator Profile Table that provides instructions for Key Generation", 3510 /* EXACT_MATCH_LOGICAL_TABLE_SELECT */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3511 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3512 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE0 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3513 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE1 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3514 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE2 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3515 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE3 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3516 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE4 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3517 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE5 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3518 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE6 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3519 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE7 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3520 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3521 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3522 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3523 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3524 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3525 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3526 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3527 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3528 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3529 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3530 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3531 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3532 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3533 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE4 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3534 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE5 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3535 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE6 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3536 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE7 */ "TCAM used to select the Key Generation Profile for the 2 EM lookups.", 3537 /* EXACT_MATCH_LP */ "ECC Table.", 3538 /* EXACT_MATCH_LP_PIPE0 */ "ECC Table.", 3539 /* EXACT_MATCH_LP_PIPE1 */ "ECC Table.", 3540 /* EXACT_MATCH_QOS_ACTIONS_PROFILE */ "QoS Actions Profile Table for EM Lookup 0", 3541 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE0 */ "QoS Actions Profile Table for EM Lookup 0", 3542 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE1 */ "QoS Actions Profile Table for EM Lookup 0", 3543 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE2 */ "QoS Actions Profile Table for EM Lookup 0", 3544 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE3 */ "QoS Actions Profile Table for EM Lookup 0", 3545 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE4 */ "QoS Actions Profile Table for EM Lookup 0", 3546 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE5 */ "QoS Actions Profile Table for EM Lookup 0", 3547 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE6 */ "QoS Actions Profile Table for EM Lookup 0", 3548 /* EXACT_MATCH_QOS_ACTIONS_PROFILE_PIPE7 */ "QoS Actions Profile Table for EM Lookup 0", 3549 /* EXACT_MATCH_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3550 /* EXACT_MATCH_REMAP_TABLE_A_PIPE0 */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3551 /* EXACT_MATCH_REMAP_TABLE_A_PIPE1 */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3552 /* EXACT_MATCH_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3553 /* EXACT_MATCH_REMAP_TABLE_B_PIPE0 */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3554 /* EXACT_MATCH_REMAP_TABLE_B_PIPE1 */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 3555 /* EXP_TABLE */ "Exp Table. Indexed by {scr_port[4:0], mpls_exp[2:0]}", 3556 /* EXT_ACL144_TCAM */ "This view supports only READ, WRITE operations.", 3557 /* EXT_ACL144_TCAM_IPV4 */ "ACL144_IPV4 Software overlay of EXT_ACL144_TCAM", 3558 /* EXT_ACL144_TCAM_IPV6 */ "ACL144_IPV6 Software overlay of EXT_ACL144_TCAM", 3559 /* EXT_ACL144_TCAM_L2 */ "ACL144_L2 Software overlay of EXT_ACL144_TCAM", 3560 /* EXT_ACL160_FP_POLICY_1X */ "ACL160 policy software overlay of EXT_FP_POLICY_1X", 3561 /* EXT_ACL160_FP_POLICY_2X */ "ACL160 policy software overlay of EXT_FP_POLICY_2X", 3562 /* EXT_ACL160_FP_POLICY_3X */ "ACL160 policy software overlay of EXT_FP_POLICY_3X", 3563 /* EXT_ACL160_FP_POLICY_4X */ "ACL160 policy software overlay of EXT_FP_POLICY_4X", 3564 /* EXT_ACL160_FP_POLICY_6X */ "ACL160 policy software overlay of EXT_FP_POLICY_6X", 3565 /* EXT_ACL160_TCAM */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE FP, FeatureSpecific-FP.", 3566 /* EXT_ACL288_TCAM */ "This view supports only READ, WRITE operations.", 3567 /* EXT_ACL288_TCAM_IPV4 */ "ACL288_IPV4 Software overlay of EXT_ACL288_TCAM", 3568 /* EXT_ACL288_TCAM_L2 */ "ACL288_L2 Software overlay of EXT_ACL288_TCAM", 3569 /* EXT_ACL320_FP_POLICY_1X */ "ACL320 policy software overlay of EXT_FP_POLICY_1X", 3570 /* EXT_ACL320_FP_POLICY_2X */ "ACL320 policy software overlay of EXT_FP_POLICY_2X", 3571 /* EXT_ACL320_FP_POLICY_3X */ "ACL320 policy software overlay of EXT_FP_POLICY_3X", 3572 /* EXT_ACL320_FP_POLICY_4X */ "ACL320 policy software overlay of EXT_FP_POLICY_4X", 3573 /* EXT_ACL320_FP_POLICY_6X */ "ACL320 policy software overlay of EXT_FP_POLICY_6X", 3574 /* EXT_ACL320_TCAM */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE FP, FeatureSpecific-FP.", 3575 /* EXT_ACL360_TCAM_DATA */ "This view supports only READ, WRITE operations.\n For READs, this view returns only the data portion of entry, mask portion of entry read from ext_tcam is stored in onchip_mask_mem. For WRITEs, this view ASSUMES that mask partion of the entry was CORRECTLY PRELOADED earlier into onchip_mask_mem", 3576 /* EXT_ACL360_TCAM_DATA_IPV6_SHORT */ "ACL360_IPV6_SHORT Software overlay of EXT_ACL360_TCAM_DATA", 3577 /* EXT_ACL360_TCAM_MASK */ "This view supports only READ, WRITE operations.\n Note: This is an on-chip memory so Response Word will NOT be returned.\n Note: READ, WRITE to this view DOES NOT RESULT in any accesses to ext_tcam.\n WRITE operation allows preloading of mask word into onchip_mask_mem, READ operation causes the contents of onchip_mask_mem to be returned", 3578 /* EXT_ACL360_TCAM_MASK_IPV6_SHORT */ "ACL360_TCAM_MASK Software overlay of EXT_ACL480_TCAM_MASK", 3579 /* EXT_ACL432_TCAM_DATA */ "This view supports only READ, WRITE operations.\n For READs, this view returns only the data portion of entry, mask portion of entry read from ext_tcam is stored in onchip_mask_mem. For WRITEs, this view ASSUMES that mask partion of the entry was CORRECTLY PRELOADED earlier into onchip_mask_mem", 3580 /* EXT_ACL432_TCAM_DATA_IPV6_LONG */ "ACL432_IPV6_LONG Software overlay of EXT_ACL432_TCAM_DATA", 3581 /* EXT_ACL432_TCAM_DATA_L2_IPV4 */ "ACL432_L2_IPV4 Software overlay of EXT_ACL432_TCAM_DATA", 3582 /* EXT_ACL432_TCAM_DATA_L2_IPV6 */ "ACL432_L2_IPV6 Software overlay of EXT_ACL432_TCAM_DATA", 3583 /* EXT_ACL432_TCAM_MASK */ "This view supports only READ, WRITE operations.\n Note: This is an on-chip memory so Response Word will NOT be returned.\n Note: READ, WRITE to this view DOES NOT RESULT in any accesses to ext_tcam.\n WRITE operation allows preloading of mask word into onchip_mask_mem, READ operation causes the contents of onchip_mask_mem to be returned", 3584 /* EXT_ACL432_TCAM_MASK_IPV6_LONG */ "ACL432_TCAM_MASK Software overlay of EXT_ACL480_TCAM_MASK", 3585 /* EXT_ACL432_TCAM_MASK_L2_IPV6 */ "ACL432_TCAM_MASK Software overlay of EXT_ACL480_TCAM_MASK", 3586 /* EXT_ACL480_FP_POLICY_1X */ "ACL480 policy software overlay of EXT_FP_POLICY_1X", 3587 /* EXT_ACL480_FP_POLICY_2X */ "ACL480 policy software overlay of EXT_FP_POLICY_2X", 3588 /* EXT_ACL480_FP_POLICY_3X */ "ACL480 policy software overlay of EXT_FP_POLICY_3X", 3589 /* EXT_ACL480_FP_POLICY_4X */ "ACL480 policy software overlay of EXT_FP_POLICY_4X", 3590 /* EXT_ACL480_FP_POLICY_6X */ "ACL480 policy software overlay of EXT_FP_POLICY_6X", 3591 /* EXT_ACL480_TCAM_DATA */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE FP, FeatureSpecific-FP.", 3592 /* EXT_ACL480_TCAM_MASK */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE FP, FeatureSpecific-FP.", 3593 /* EXT_ACL80_FP_POLICY_1X */ "ACL80 policy software overlay of EXT_FP_POLICY_1X", 3594 /* EXT_ACL80_FP_POLICY_2X */ "ACL80 policy software overlay of EXT_FP_POLICY_2X", 3595 /* EXT_ACL80_FP_POLICY_3X */ "ACL80 policy software overlay of EXT_FP_POLICY_3X", 3596 /* EXT_ACL80_FP_POLICY_4X */ "ACL80 policy software overlay of EXT_FP_POLICY_4X", 3597 /* EXT_ACL80_FP_POLICY_6X */ "ACL80 policy software overlay of EXT_FP_POLICY_6X", 3598 /* EXT_ACL80_TCAM */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE FP, FeatureSpecific-FP.", 3599 /* EXT_DEFIP_DATA */ "This view supports only READ, WRITE operations.", 3600 /* EXT_DEFIP_DATA_IPV4 */ "EXT_DEFIP_DATA_IPV4 Software overlay of EXT_DEFIP_DATA", 3601 /* EXT_DEFIP_DATA_IPV6_64 */ "EXT_DEFIP_DATA_IPV6_64 Software overlay of EXT_DEFIP_DATA", 3602 /* EXT_DEFIP_DATA_IPV6_128 */ "EXT_DEFIP_DATA_IPV6_128 Software overlay of EXT_DEFIP_DATA", 3603 /* EXT_DST_HBITS */ "HW managed EXT_DST_HBITS table.", 3604 /* EXT_DST_HIT_BITS */ "On-chip dst_hit bits for ext tables.\n Note: this view requires ext_tcam_phy_adr\n Note: this view does not take into account HBIT_EN in ET_PA_XLAT table", 3605 /* EXT_DST_HIT_BITS_IPV4 */ "EXT_DST_HIT_BITS_IPV4 Software overlay of EXT_DST_HIT_BITS", 3606 /* EXT_DST_HIT_BITS_IPV4_UCAST */ "EXT_DST_HIT_BITS_IPV4_UCAST Software overlay of EXT_DST_HIT_BITS", 3607 /* EXT_DST_HIT_BITS_IPV4_UCAST_WIDE */ "EXT_DST_HIT_BITS_IPV4_UCAST_WIDE Software overlay of EXT_DST_HIT_BITS", 3608 /* EXT_DST_HIT_BITS_IPV6_64 */ "EXT_DST_HIT_BITS_IPV6_64 Software overlay of EXT_DST_HIT_BITS", 3609 /* EXT_DST_HIT_BITS_IPV6_128 */ "EXT_DST_HIT_BITS_IPV6_128 Software overlay of EXT_DST_HIT_BITS", 3610 /* EXT_DST_HIT_BITS_IPV6_128_UCAST */ "EXT_DST_HIT_BITS_IPV6_128_UCAST Software overlay of EXT_DST_HIT_BITS", 3611 /* EXT_DST_HIT_BITS_IPV6_128_UCAST_WIDE */ "EXT_DST_HIT_BITS_IPV6_128_UCAST_WIDE Software overlay of EXT_DST_HIT_BITS", 3612 /* EXT_DST_HIT_BITS_L2 */ "EXT_DST_HIT_BITS_L2 Software overlay of EXT_DST_HIT_BITS", 3613 /* EXT_DST_HIT_BITS_L2_WIDE */ "EXT_DST_HIT_BITS_L2_WIDE Software overlay of EXT_DST_HIT_BITS", 3614 /* EXT_FP_CNTR */ "This view supports only READ, WRITE operations.", 3615 /* EXT_FP_CNTR8 */ "READ, WRITE to this view provides access to 8 consecutive ext_fp_counters\n If resultant counter address in ext_sram does not fall on boundary of 8 x 72bits, the reads will wrap-around in a block of 8 counters", 3616 /* EXT_FP_CNTR8_ACL144_IPV4 */ "EXT_FP_CNTR8_ACL144_IPV4 Software overlay of EXT_FP_CNTR8", 3617 /* EXT_FP_CNTR8_ACL144_IPV6 */ "EXT_FP_CNTR8_ACL144_IPV6 Software overlay of EXT_FP_CNTR8", 3618 /* EXT_FP_CNTR8_ACL144_L2 */ "EXT_FP_CNTR8_ACL144_L2 Software overlay of EXT_FP_CNTR", 3619 /* EXT_FP_CNTR8_ACL288_IPV4 */ "EXT_FP_CNTR8_ACL288_IPV4 Software overlay of EXT_FP_CNTR8", 3620 /* EXT_FP_CNTR8_ACL288_L2 */ "EXT_FP_CNTR8_ACL288_L2 Software overlay of EXT_FP_CNTR8", 3621 /* EXT_FP_CNTR8_ACL360_IPV6_SHORT */ "EXT_FP_CNTR8_ACL360_IPV6_SHORT Software overlay of EXT_FP_CNTR8", 3622 /* EXT_FP_CNTR8_ACL432_IPV6_LONG */ "EXT_FP_CNTR8_ACL432_IPV6_LONG Software overlay of EXT_FP_CNTR8", 3623 /* EXT_FP_CNTR8_ACL432_L2_IPV4 */ "EXT_FP_CNTR8_ACL432_L2_IPV4 Software overlay of EXT_FP_CNTR8", 3624 /* EXT_FP_CNTR8_ACL432_L2_IPV6 */ "EXT_FP_CNTR8_ACL432_L2_IPV6 Software overlay of EXT_FP_CNTR8", 3625 /* EXT_FP_CNTR_ACL144_IPV4 */ "EXT_FP_CNTR_ACL144_IPV4 Software overlay of EXT_FP_CNTR", 3626 /* EXT_FP_CNTR_ACL144_IPV6 */ "EXT_FP_CNTR_ACL144_IPV6 Software overlay of EXT_FP_CNTR", 3627 /* EXT_FP_CNTR_ACL144_L2 */ "EXT_FP_CNTR_ACL144_L2 Software overlay of EXT_FP_CNTR", 3628 /* EXT_FP_CNTR_ACL288_IPV4 */ "EXT_FP_CNTR_ACL288_IPV4 Software overlay of EXT_FP_CNTR", 3629 /* EXT_FP_CNTR_ACL288_L2 */ "EXT_FP_CNTR_ACL288_L2 Software overlay of EXT_FP_CNTR", 3630 /* EXT_FP_CNTR_ACL360_IPV6_SHORT */ "EXT_FP_CNTR_ACL360_IPV6_SHORT Software overlay of EXT_FP_CNTR", 3631 /* EXT_FP_CNTR_ACL432_IPV6_LONG */ "EXT_FP_CNTR_ACL432_IPV6_LONG Software overlay of EXT_FP_CNTR", 3632 /* EXT_FP_CNTR_ACL432_L2_IPV4 */ "EXT_FP_CNTR_ACL432_L2_IPV4 Software overlay of EXT_FP_CNTR", 3633 /* EXT_FP_CNTR_ACL432_L2_IPV6 */ "EXT_FP_CNTR_ACL432_L2_IPV6 Software overlay of EXT_FP_CNTR", 3634 /* EXT_FP_POLICY */ "This view supports only READ, WRITE operations.", 3635 /* EXT_FP_POLICY_1X */ "External FP Policy. 35 bit.", 3636 /* EXT_FP_POLICY_2X */ "External FP Policy, 70 bits data", 3637 /* EXT_FP_POLICY_3X */ "External FP Policy. 105 bit data", 3638 /* EXT_FP_POLICY_4X */ "External FP Policy, 140 bit data", 3639 /* EXT_FP_POLICY_6X */ "External FP Policy, 210 bit data", 3640 /* EXT_FP_POLICY_ACL144_IPV4 */ "EXT_FP_POLICY_ACL144_IPV4 Software overlay of EXT_FP_POLICY", 3641 /* EXT_FP_POLICY_ACL144_IPV6 */ "EXT_FP_POLICY_ACL144_IPV6 Software overlay of EXT_FP_POLICY", 3642 /* EXT_FP_POLICY_ACL144_IPV4_1X */ "EXT_FP_POLICY_ACL144_IPV4 Software overlay of EXT_FP_POLICY_1X", 3643 /* EXT_FP_POLICY_ACL144_IPV4_2X */ "EXT_FP_POLICY_ACL144_IPV4 Software overlay of EXT_FP_POLICY_2X", 3644 /* EXT_FP_POLICY_ACL144_IPV4_3X */ "EXT_FP_POLICY_ACL144_IPV4 Software overlay of EXT_FP_POLICY_3X", 3645 /* EXT_FP_POLICY_ACL144_IPV4_4X */ "EXT_FP_POLICY_ACL144_IPV4 Software overlay of EXT_FP_POLICY_4X", 3646 /* EXT_FP_POLICY_ACL144_IPV4_6X */ "EXT_FP_POLICY_ACL144_IPV4 Software overlay of EXT_FP_POLICY_6X", 3647 /* EXT_FP_POLICY_ACL144_IPV6_1X */ "EXT_FP_POLICY_ACL144_IPV6_1X Software overlay of EXT_FP_POLICY_1X", 3648 /* EXT_FP_POLICY_ACL144_IPV6_2X */ "EXT_FP_POLICY_ACL144_IPV6_2X Software overlay of EXT_FP_POLICY_2X", 3649 /* EXT_FP_POLICY_ACL144_IPV6_3X */ "EXT_FP_POLICY_ACL144_IPV6_3X Software overlay of EXT_FP_POLICY_3X", 3650 /* EXT_FP_POLICY_ACL144_IPV6_4X */ "EXT_FP_POLICY_ACL144_IPV6_4X Software overlay of EXT_FP_POLICY_4X", 3651 /* EXT_FP_POLICY_ACL144_IPV6_6X */ "EXT_FP_POLICY_ACL144_IPV6_6X Software overlay of EXT_FP_POLICY_6X", 3652 /* EXT_FP_POLICY_ACL144_L2 */ "EXT_FP_POLICY_ACL144_L2 Software overlay of EXT_FP_POLICY", 3653 /* EXT_FP_POLICY_ACL144_L2_1X */ "EXT_FP_POLICY_ACL144_L2_1X Software overlay of EXT_FP_POLICY_1X", 3654 /* EXT_FP_POLICY_ACL144_L2_2X */ "EXT_FP_POLICY_ACL144_L2_2X Software overlay of EXT_FP_POLICY_2X", 3655 /* EXT_FP_POLICY_ACL144_L2_3X */ "EXT_FP_POLICY_ACL144_L2_3X Software overlay of EXT_FP_POLICY_3X", 3656 /* EXT_FP_POLICY_ACL144_L2_4X */ "EXT_FP_POLICY_ACL144_L2_4X Software overlay of EXT_FP_POLICY_4X", 3657 /* EXT_FP_POLICY_ACL144_L2_6X */ "EXT_FP_POLICY_ACL144_L2_6X Software overlay of EXT_FP_POLICY_6X", 3658 /* EXT_FP_POLICY_ACL288_IPV4 */ "EXT_FP_POLICY_ACL288_IPV4 Software overlay of EXT_FP_POLICY", 3659 /* EXT_FP_POLICY_ACL288_IPV4_1X */ "EXT_FP_POLICY_ACL288_IPV4_1X Software overlay of EXT_FP_POLICY_1X", 3660 /* EXT_FP_POLICY_ACL288_IPV4_2X */ "EXT_FP_POLICY_ACL288_IPV4_2X Software overlay of EXT_FP_POLICY_2X", 3661 /* EXT_FP_POLICY_ACL288_IPV4_3X */ "EXT_FP_POLICY_ACL288_IPV4_3X Software overlay of EXT_FP_POLICY_3X", 3662 /* EXT_FP_POLICY_ACL288_IPV4_4X */ "EXT_FP_POLICY_ACL288_IPV4_4X Software overlay of EXT_FP_POLICY_4X", 3663 /* EXT_FP_POLICY_ACL288_IPV4_6X */ "EXT_FP_POLICY_ACL288_IPV4_6X Software overlay of EXT_FP_POLICY_6X", 3664 /* EXT_FP_POLICY_ACL288_L2 */ "EXT_FP_POLICY_ACL288_L2 Software overlay of EXT_FP_POLICY", 3665 /* EXT_FP_POLICY_ACL288_L2_1X */ "EXT_FP_POLICY_ACL288_L2_1X Software overlay of EXT_FP_POLICY_1X", 3666 /* EXT_FP_POLICY_ACL288_L2_2X */ "EXT_FP_POLICY_ACL288_L2_2X Software overlay of EXT_FP_POLICY_2X", 3667 /* EXT_FP_POLICY_ACL288_L2_3X */ "EXT_FP_POLICY_ACL288_L2_3X Software overlay of EXT_FP_POLICY_3X", 3668 /* EXT_FP_POLICY_ACL288_L2_4X */ "EXT_FP_POLICY_ACL288_L2_4X Software overlay of EXT_FP_POLICY_4X", 3669 /* EXT_FP_POLICY_ACL288_L2_6X */ "EXT_FP_POLICY_ACL288_L2_6X Software overlay of EXT_FP_POLICY_6X", 3670 /* EXT_FP_POLICY_ACL360_IPV6_SHORT */ "EXT_FP_POLICY_ACL360_IPV6_SHORT Software overlay of EXT_FP_POLICY", 3671 /* EXT_FP_POLICY_ACL360_IPV6_SHORT_1X */ "EXT_FP_POLICY_ACL360_IPV6_SHORT_1X Software overlay of EXT_FP_POLICY_1X", 3672 /* EXT_FP_POLICY_ACL360_IPV6_SHORT_2X */ "EXT_FP_POLICY_ACL360_IPV6_SHORT_2X Software overlay of EXT_FP_POLICY_2X", 3673 /* EXT_FP_POLICY_ACL360_IPV6_SHORT_3X */ "EXT_FP_POLICY_ACL360_IPV6_SHORT_3X Software overlay of EXT_FP_POLICY_3X", 3674 /* EXT_FP_POLICY_ACL360_IPV6_SHORT_4X */ "EXT_FP_POLICY_ACL360_IPV6_SHORT_4X Software overlay of EXT_FP_POLICY_4X", 3675 /* EXT_FP_POLICY_ACL360_IPV6_SHORT_6X */ "EXT_FP_POLICY_ACL360_IPV6_SHORT_6X Software overlay of EXT_FP_POLICY_6X", 3676 /* EXT_FP_POLICY_ACL432_IPV6_LONG */ "EXT_FP_POLICY_ACL432_IPV6_LONG Software overlay of EXT_FP_POLICY", 3677 /* EXT_FP_POLICY_ACL432_IPV6_LONG_1X */ "EXT_FP_POLICY_ACL432_IPV6_LONG_1X Software overlay of EXT_FP_POLICY_1X", 3678 /* EXT_FP_POLICY_ACL432_IPV6_LONG_2X */ "EXT_FP_POLICY_ACL432_IPV6_LONG_2X Software overlay of EXT_FP_POLICY_2X", 3679 /* EXT_FP_POLICY_ACL432_IPV6_LONG_3X */ "EXT_FP_POLICY_ACL432_IPV6_LONG_3X Software overlay of EXT_FP_POLICY_3X", 3680 /* EXT_FP_POLICY_ACL432_IPV6_LONG_4X */ "EXT_FP_POLICY_ACL432_IPV6_LONG_4X Software overlay of EXT_FP_POLICY_4X", 3681 /* EXT_FP_POLICY_ACL432_IPV6_LONG_6X */ "EXT_FP_POLICY_ACL432_IPV6_LONG_6X Software overlay of EXT_FP_POLICY_6X", 3682 /* EXT_FP_POLICY_ACL432_L2_IPV4 */ "EXT_FP_POLICY_ACL432_L2_IPV4 Software overlay of EXT_FP_POLICY", 3683 /* EXT_FP_POLICY_ACL432_L2_IPV6 */ "EXT_FP_POLICY_ACL432_L2_IPV6 Software overlay of EXT_FP_POLICY", 3684 /* EXT_FP_POLICY_ACL432_L2_IPV4_1X */ "EXT_FP_POLICY_ACL432_L2_IPV4_1X Software overlay of EXT_FP_POLICY_1X", 3685 /* EXT_FP_POLICY_ACL432_L2_IPV4_2X */ "EXT_FP_POLICY_ACL432_L2_IPV4_2X Software overlay of EXT_FP_POLICY_2X", 3686 /* EXT_FP_POLICY_ACL432_L2_IPV4_3X */ "EXT_FP_POLICY_ACL432_L2_IPV4_3X Software overlay of EXT_FP_POLICY_3X", 3687 /* EXT_FP_POLICY_ACL432_L2_IPV4_4X */ "EXT_FP_POLICY_ACL432_L2_IPV4_4X Software overlay of EXT_FP_POLICY_4X", 3688 /* EXT_FP_POLICY_ACL432_L2_IPV4_6X */ "EXT_FP_POLICY_ACL432_L2_IPV4_6X Software overlay of EXT_FP_POLICY_6X", 3689 /* EXT_FP_POLICY_ACL432_L2_IPV6_1X */ "EXT_FP_POLICY_ACL432_L2_IPV6_1X Software overlay of EXT_FP_POLICY_1X", 3690 /* EXT_FP_POLICY_ACL432_L2_IPV6_2X */ "EXT_FP_POLICY_ACL432_L2_IPV6_2X Software overlay of EXT_FP_POLICY_2X", 3691 /* EXT_FP_POLICY_ACL432_L2_IPV6_3X */ "EXT_FP_POLICY_ACL432_L2_IPV6_3X Software overlay of EXT_FP_POLICY_3X", 3692 /* EXT_FP_POLICY_ACL432_L2_IPV6_4X */ "EXT_FP_POLICY_ACL432_L2_IPV6_4X Software overlay of EXT_FP_POLICY_4X", 3693 /* EXT_FP_POLICY_ACL432_L2_IPV6_6X */ "EXT_FP_POLICY_ACL432_L2_IPV6_6X Software overlay of EXT_FP_POLICY_6X", 3694 /* EXT_IFP_ACTION_PROFILE */ "This table expands a 7-bit pointer from the external ACL lookup into the profiled actions described in the fields of this table. These actions are then resolved along with the internal IFP actions. FeatureSpecific-Ethernet", 3695 /* EXT_IPV4_DEFIP */ "This view supports only READ, WRITE operations.", 3696 /* EXT_IPV4_DEFIP_TCAM */ "This view supports only READ, WRITE operations.", 3697 /* EXT_IPV4_TCAM */ "TCAM only view for EXT_IPV4_UCAST, EXT_IPV4_UCAST_WIDE, EXT_IPV4_DEFIP", 3698 /* EXT_IPV4_UCAST */ "Unified view with EXT_L3_UCAST_DATA and EXT_IPV4_TCAM", 3699 /* EXT_IPV4_UCAST_TCAM */ "EXT_IPV4_UCAST_TCAM Software overlay of EXT_IPV4_TCAM", 3700 /* EXT_IPV4_UCAST_WIDE */ "Unified view with EXT_L3_UCAST_DATA_WIDE and EXT_IPV4_TCAM", 3701 /* EXT_IPV4_UCAST_WIDE_TCAM */ "EXT_IPV4_UCAST_WIDE_TCAM Software overlay of EXT_IPV4_TCAM", 3702 /* EXT_IPV6_128_DEFIP */ "This view supports only READ, WRITE operations.", 3703 /* EXT_IPV6_128_DEFIP_TCAM */ "This view supports only READ, WRITE operations.", 3704 /* EXT_IPV6_128_TCAM */ "TCAM view for EXT_IPV6_128_UCAST, EXT_IPV6_128_UCAST_WIDE and EXT_IPV6_128_DEFIP", 3705 /* EXT_IPV6_128_UCAST */ "Unified view with EXT_L3_UCAST_DATA and EXT_IPV6_128_TCAM", 3706 /* EXT_IPV6_128_UCAST_TCAM */ "EXT_IPV6_128_UCAST_TCAM Software overlay of EXT_IPV6_128_TCAM", 3707 /* EXT_IPV6_128_UCAST_WIDE */ "Unified view with EXT_L3_UCAST_DATA_WIDE and EXT_IPV6_128_TCAM", 3708 /* EXT_IPV6_128_UCAST_WIDE_TCAM */ "EXT_IPV6_128_UCAST_WIDE_TCAM Software overlay of EXT_IPV6_128_TCAM", 3709 /* EXT_IPV6_64_DEFIP */ "This view supports only READ, WRITE operations.", 3710 /* EXT_IPV6_64_DEFIP_TCAM */ "This view supports only READ, WRITE operations.", 3711 /* EXT_IPV6_64_TCAM */ "TCAM only view for EXT_IPV6_64_DEFIP", 3712 /* EXT_L2_ENTRY */ "This view supports only INSERT, DELETE, LOOKUP operations. 72b Local Mask field in TCAM is implicitly {11'h7FF, 61'h0}.\n Note: DELETE operation for this table only results in the entry being marked FREE and not to be INVALIDATED", 3713 /* EXT_L2_ENTRY_1 */ "EXT_L2_ENTRY_1, Single base entry views. FeatureSpecific-Ethernet.", 3714 /* EXT_L2_ENTRY_2 */ "EXT_L2_ENTRY_2, Single base entry views. FeatureSpecific-Ethernet.", 3715 /* EXT_L2_ENTRY_DATA */ "This view supports only READ, WRITE operations and is intended for debug purposes.", 3716 /* EXT_L2_ENTRY_DATA_ONLY */ "EXT_L2_ENTRY_DATA_ONLY.", 3717 /* EXT_L2_ENTRY_DATA_ONLY_WIDE */ "EXT_L2_ENTRY_DATA_ONLY_WIDE.", 3718 /* EXT_L2_ENTRY_TCAM */ "This view supports only READ, WRITE operations and is intended for debug purposes.", 3719 /* EXT_L2_ENTRY_TCAM_WIDE */ "EXT_L2_ENTRY_TCAM_WIDE Software overlay of EXT_L2_ENTRY_TCAM", 3720 /* EXT_L2_MOD_FIFO */ "Format of entry in ext_L2MODFIFO\n This table supports FIFO_POP command. FIFO_PUSH, MEM_RD, MEM_WR are supported for debug only. The format of entry here is also the format of sbus_rsp for LOOKUP, INSERT, DELETE directed to EXT_L2_ENTRY table", 3721 /* EXT_L3_UCAST_DATA */ "Unicast data for IPV4, IPV6", 3722 /* EXT_L3_UCAST_DATA_IPV4 */ "EXT_L3_UCAST_DATA_IPV4 Software overlay of EXT_L3_UCAST_DATA", 3723 /* EXT_L3_UCAST_DATA_IPV6_128 */ "EXT_L3_UCAST_DATA_IPV6_128 Software overlay of EXT_L3_UCAST_DATA", 3724 /* EXT_L3_UCAST_DATA_WIDE */ "Unicast data for IPV4, IPV6", 3725 /* EXT_L3_UCAST_DATA_WIDE_IPV4 */ "EXT_L3_UCAST_DATA_WIDE_IPV4 Software overlay of EXT_L3_UCAST_DATA_WIDE", 3726 /* EXT_L3_UCAST_DATA_WIDE_IPV6_128 */ "EXT_L3_UCAST_DATA_WIDE_IPV6_128 Software overlay of EXT_L3_UCAST_DATA_WIDE", 3727 /* EXT_LOC_SRC_HBITS */ "HW managed EXT_LOC_SRC_HBITS table.", 3728 /* EXT_LOC_SRC_HIT_BITS_L2 */ "EXT_LOC_SRC_HIT_BITS_L2 Software overlay of EXT_LOC_SRC_HBITS", 3729 /* EXT_LOC_SRC_HIT_BITS_L2_WIDE */ "EXT_LOC_SRC_HIT_BITS_L2_WIDE Software overlay of EXT_LOC_SRC_HBITS", 3730 /* EXT_SRC_HBITS */ "HW managed EXT_SRC_HBITS table.", 3731 /* EXT_SRC_HIT_BITS */ "On-chip src_hit bits for ext tables.\n Note: this view requires ext_tcam_phy_adr\n Note: this view does not take into account HBIT_EN in ET_PA_XLAT table", 3732 /* EXT_SRC_HIT_BITS_IPV4 */ "EXT_SRC_HIT_BITS_IPV4 Software overlay of EXT_SRC_HIT_BITS", 3733 /* EXT_SRC_HIT_BITS_IPV4_UCAST */ "EXT_SRC_HIT_BITS_IPV4_UCAST Software overlay of EXT_SRC_HIT_BITS", 3734 /* EXT_SRC_HIT_BITS_IPV4_UCAST_WIDE */ "EXT_SRC_HIT_BITS_IPV4_UCAST_WIDE Software overlay of EXT_SRC_HIT_BITS", 3735 /* EXT_SRC_HIT_BITS_IPV6_64 */ "EXT_SRC_HIT_BITS_IPV6_64 Software overlay of EXT_SRC_HIT_BITS", 3736 /* EXT_SRC_HIT_BITS_IPV6_128 */ "EXT_SRC_HIT_BITS_IPV6_128 Software overlay of EXT_SRC_HIT_BITS", 3737 /* EXT_SRC_HIT_BITS_IPV6_128_UCAST */ "EXT_SRC_HIT_BITS_IPV6_128_UCAST Software overlay of EXT_SRC_HIT_BITS", 3738 /* EXT_SRC_HIT_BITS_IPV6_128_UCAST_WIDE */ "EXT_SRC_HIT_BITS_IPV6_128_UCAST_WIDE Software overlay of EXT_SRC_HIT_BITS", 3739 /* EXT_SRC_HIT_BITS_L2 */ "EXT_SRC_HIT_BITS_L2 Software overlay of EXT_SRC_HIT_BITS", 3740 /* EXT_SRC_HIT_BITS_L2_WIDE */ "EXT_SRC_HIT_BITS_L2_WIDE Software overlay of EXT_SRC_HIT_BITS", 3741 /* EXT_TCAM_VBIT */ "ext_tcam Vbit view", 3742 /* EXT_TCAM_VBIT_ACL80 */ "EXT_TCAM_VBIT_ACL80 Software overlay of EXT_TCAM_VBIT", 3743 /* EXT_TCAM_VBIT_ACL160 */ "EXT_TCAM_VBIT_ACL160 Software overlay of EXT_TCAM_VBIT", 3744 /* EXT_TCAM_VBIT_ACL320 */ "EXT_TCAM_VBIT_ACL320 Software overlay of EXT_TCAM_VBIT", 3745 /* EXT_TCAM_VBIT_ACL480 */ "EXT_TCAM_VBIT_ACL480 Software overlay of EXT_TCAM_VBIT", 3746 /* EXT_TCAM_VBIT_DEFIP_IPV4 */ "EXT_TCAM_VBIT_DEFIP_IPV4 Software overlay of EXT_TCAM_VBIT", 3747 /* EXT_TCAM_VBIT_DEFIP_IPV6_64 */ "EXT_TCAM_VBIT_DEFIP_IPV6_64 Software overlay of EXT_TCAM_VBIT", 3748 /* EXT_TCAM_VBIT_DEFIP_IPV6_128 */ "EXT_TCAM_VBIT_DEFIP_IPV6_128 Software overlay of EXT_TCAM_VBIT", 3749 /* EXT_TCAM_VBIT_IPV4_UCAST */ "EXT_TCAM_VBIT_IPV4_UCAST Software overlay of EXT_TCAM_VBIT", 3750 /* EXT_TCAM_VBIT_IPV4_UCAST_WIDE */ "EXT_TCAM_VBIT_IPV4_UCAST_WIDE Software overlay of EXT_TCAM_VBIT", 3751 /* EXT_TCAM_VBIT_IPV6_128_UCAST */ "EXT_TCAM_VBIT_IPV6_128_UCAST Software overlay of EXT_TCAM_VBIT", 3752 /* EXT_TCAM_VBIT_IPV6_128_UCAST_WIDE */ "EXT_TCAM_VBIT_IPV6_128_UCAST_WIDE Software overlay of EXT_TCAM_VBIT", 3753 /* EXT_TCAM_VBIT_L2_ENTRY_1 */ "EXT_TCAM_VBIT_L2_ENTRY_1 Software overlay of EXT_TCAM_VBIT", 3754 /* EXT_TCAM_VBIT_L2_ENTRY_2 */ "EXT_TCAM_VBIT_L2_ENTRY_2 Software overlay of EXT_TCAM_VBIT", 3755 /* EXT_TM_MANAGED_PORT */ "contains a port bitmap indicating all local ports managed by Arad", 3756 /* FAST_TRUNK_GROUP */ "Contains the members in each FAST LAG group.", 3757 /* FAST_TRUNK_PORTS_1 */ "Contains the members in each FAST LAG group.", 3758 /* FAST_TRUNK_PORTS_2 */ "Contains the members in each FAST LAG group.", 3759 /* FAST_TRUNK_SIZE */ "Contains trunk size and mode in each FAST LAG group.", 3760 /* FCOE_CS_CTL_FN */ "FCOE hop count to FN mapping table", 3761 /* FCOE_HOP_COUNT_FN */ "FCOE hop count to FN mapping table", 3762 /* FCR_EFMSM */ "", 3763 /* FCR_EFMS_SOURCE_PIPE */ "Address is bits 10:3 of the source device id. Each line represents 8 source devices.\n If bit is set, flow-status cell with the relevant source device will bypass the EFMS.", 3764 /* FCR_FCR_CRM_0 */ "Flow-status, credit and reachability cells FIFOs for links 0-15. Width 110 data bits(control cell). 8 bits for ECC.", 3765 /* FCR_FCR_CRM_1 */ "Flow-status, credit and reachability cells FIFOs for links 16-31 Width 110 data bits(control cell). 8 bits for ECC.", 3766 /* FCR_FCR_CRM_2 */ "Flow-status, credit and reachability cells FIFOs for links 32-47 number). Width 110 data bits(control cell). 8 bits for ECC.", 3767 /* FCR_FCR_CRM_3 */ "Flow-status, credit and reachability cells FIFOs for links 48-63 Width 110 data bits(control cell). 8 bits for ECC.", 3768 /* FCR_FCR_CRM_4 */ "Flow-status, credit and reachability cells FIFOs for links 64-79. Width 110 data bits(control cell). 8 bits for ECC.", 3769 /* FCR_FCR_CRM_5 */ "Flow-status, credit and reachability cells FIFOs for links 80-95. Width 110 data bits(control cell). 8 bits for ECC.", 3770 /* FCR_FCR_CRM_6 */ "Flow-status, credit and reachability cells FIFOs for links 96-111. Width 110 data bits(control cell). 8 bits for ECC.", 3771 /* FCR_FCR_CRM_A */ "", 3772 /* FCR_FCR_CRM_B */ "", 3773 /* FCR_LOCAL_FIFOS */ "Flow-status cells fifo for local inter face towards core0", 3774 /* FCT_FCT_REACH_OUT */ "Reachability out FIFO", 3775 /* FC_HEADER_TYPE */ "FCoE Header Type.", 3776 /* FC_MAP_PROFILE */ "FC MAP", 3777 /* FDA_AUTO_DOC_NAME_32 */ "INTERNAL", 3778 /* FDA_AUTO_DOC_NAME_33 */ "INTERNAL", 3779 /* FDA_AUTO_DOC_NAME_34 */ "INTERNAL", 3780 /* FDA_AUTO_DOC_NAME_35 */ "INTERNAL", 3781 /* FDA_FDA_MC */ "For each mc_id:\n bit mc_id * 2 + 0 indicates ceill is replicated to egq0\n bit mc_id * 2 + 1 indicates cell is replicated to egq1\n Each row contains 32 mc_ids", 3782 /* FDA_FDA_MEMORY_0 */ "INTERNAL", 3783 /* FDA_MEM_1002000 */ "INTERNAL", 3784 /* FDA_MEM_1003000 */ "INTERNAL", 3785 /* FDA_MEM_1004000 */ "INTERNAL", 3786 /* FDA_MEM_1005000 */ "INTERNAL", 3787 /* FDA_MEM_1006000 */ "INTERNAL", 3788 /* FDA_MEM_1007000 */ "INTERNAL", 3789 /* FDA_MEM_1008000 */ "INTERNAL", 3790 /* FDA_MEM_1009000 */ "INTERNAL", 3791 /* FDA_MEM_1010000 */ "INTERNAL", 3792 /* FDA_MEM_1011000 */ "INTERNAL", 3793 /* FDR_AUTO_DOC_NAME_66 */ "INTERNAL", 3794 /* FDR_AUTO_DOC_NAME_67 */ "INTERNAL", 3795 /* FDR_AUTO_DOC_NAME_68 */ "INTERNAL", 3796 /* FDR_AUTO_DOC_NAME_69 */ "INTERNAL", 3797 /* FDR_AUTO_DOC_NAME_70 */ "INTERNAL", 3798 /* FDR_AUTO_DOC_NAME_71 */ "INTERNAL", 3799 /* FDR_AUTO_DOC_NAME_72 */ "INTERNAL", 3800 /* FDR_AUTO_DOC_NAME_73 */ "INTERNAL", 3801 /* FDR_AUTO_DOC_NAME_74 */ "INTERNAL", 3802 /* FDR_FDR_MC */ "For each mc_id: bit mc_id * 2 + 0 indicates cell is replicated to egq0 bit mc_id * 2 + 1 indicates cell is replicated to egq1 Each row contains 64 mc_ids", 3803 /* FDR_MEM_100000 */ "INTERNAL", 3804 /* FDR_MEM_200000 */ "INTERNAL", 3805 /* FDR_MEM_300000 */ "INTERNAL", 3806 /* FDR_MEM_400000 */ "INTERNAL", 3807 /* FDR_MEM_500000 */ "INTERNAL", 3808 /* FDR_MEM_600000 */ "INTERNAL", 3809 /* FDR_MEM_700000 */ "INTERNAL", 3810 /* FDR_MEM_800000 */ "INTERNAL", 3811 /* FDR_MEM_900000 */ "INTERNAL", 3812 /* FDR_MEM_A00000 */ "INTERNAL", 3813 /* FDR_MEM_B00000 */ "INTERNAL", 3814 /* FDR_MEM_C00000 */ "INTERNAL", 3815 /* FDTL_MCT_PAYLOAD */ "FDT fabric output pipe: 14Macs X 2Cores X 4(1024b entries) = 112instances Depth = 8Links X 12Cells = 96 8 Cells non-tdm 4 Cells tdm For J2 - tdm is not supported, depth=64", 3816 /* FDT_IN_BAND_MEM */ "InBand topology table. Each row represent one potential replication of the InBand cell.", 3817 /* FDT_IPT_CTRL_FIFO */ "hold the IPT descriptor with the RTP bitmap", 3818 /* FDT_IPT_DESC */ "Input pipe IPT descriptors fifo", 3819 /* FDT_IPT_MESH_MC */ "In mesh mode: IPT MC replication. Address is bits 15:5 of MCID.\n In fabric mode: Packing control and minimum number of links. Address is destination device.", 3820 /* FDT_IPT_PAYLOAD */ "Input pipe IPT payload fifo", 3821 /* FDT_IPT_PAYLOAD_FIFO */ "Holds the IPT Payload fifo", 3822 /* FDT_IRE_TDM_FIFO */ "hold the IPT descriptor with the RTP bitmap", 3823 /* FDT_IRE_TDM_MASKS */ "36 masks used to select the available links used by IRE TDM packets.\n Index by pointer configured by the IRE.", 3824 /* FDT_MEM_100000 */ "INTERNAL", 3825 /* FDT_MESH_MC */ "In mesh mode: IPT MC replication. Address is bits 15:5 of MCID. In fabric mode: Destinaion FAP looad balancing context and minimum number of links. Address is destination device.", 3826 /* FDT_WFD */ "Weighted Fabric Distribution memload_balancing_ctx = 112 link_thr Each row represents a load balancing context. Width = 112Links X 7bits thr. Thr/127 is the probablity to select the link.", 3827 /* FIELD_BUS_MERGE_PROFILE */ "Flex Flow FIELD_BUS merge Profile Table.", 3828 /* FIELD_BUS_MERGE_PROFILE_0 */ "Flex Flow FIELD_BUS merge Profile Table.", 3829 /* FILTERMATCHCOUNT */ "Number of Pre-Crypto Filter Match Hits for each Rule", 3830 /* FLEX_BIN_HASH_PROFILE_0 */ "Flex RTAG7 hash Profile Table 0, cover bin 0-12.", 3831 /* FLEX_BIN_HASH_PROFILE_1 */ "Flex RTAG7 hash Profile Table 1, cover bin 13-25.", 3832 /* FLEX_BIN_HASH_PROFILE_2 */ "Flex RTAG7 hash Profile Table 2, cover bin 26-38.", 3833 /* FLEX_BIN_HASH_PROFILE_3 */ "Flex RTAG7 hash Profile Table 3, cover bin 39-51.", 3834 /* FLEX_CTR_ACTION_MASK_PROFILE */ "Flex counter enable profile.", 3835 /* FLEX_EDITOR_FIXED_HDR_L2_0_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3836 /* FLEX_EDITOR_FIXED_HDR_L2_0_PROFILE_TABLE */ "This controls the type of headers constructed", 3837 /* FLEX_EDITOR_FIXED_HDR_L2_1_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3838 /* FLEX_EDITOR_FIXED_HDR_L2_1_PROFILE_TABLE */ "This controls the type of headers constructed", 3839 /* FLEX_EDITOR_FIXED_HDR_L3_0_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3840 /* FLEX_EDITOR_FIXED_HDR_L3_0_PROFILE_TABLE */ "This controls the type of headers constructed", 3841 /* FLEX_EDITOR_FIXED_HDR_LOOPBACK_0_PROFILE_TABLE */ "This controls the type of loopback headers constructed", 3842 /* FLEX_EDITOR_FIXED_HDR_SYS_0_PROFILE_TABLE */ "This controls the type of headers constructed", 3843 /* FLEX_EDITOR_FIXED_HDR_TUNNEL_0_GRE_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3844 /* FLEX_EDITOR_FIXED_HDR_TUNNEL_0_PROFILE_TABLE */ "This controls the type of headers constructed", 3845 /* FLEX_EDITOR_FIXED_HDR_TUNNEL_0_UDP_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3846 /* FLEX_EDITOR_FIXED_HDR_TUNNEL_0_VXLAN_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3847 /* FLEX_EDITOR_FLEX_HDR_0_16BIT_FS_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3848 /* FLEX_EDITOR_FLEX_HDR_0_32BIT_FS_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3849 /* FLEX_EDITOR_FLEX_HDR_0_ALU_PROFILE_TABLE */ "This provides the commands for the ALU operations in the flex hc engine", 3850 /* FLEX_EDITOR_FLEX_HDR_0_HC_PROFILE_TABLE */ "This provides the commands to shift the new fields for the rewrite", 3851 /* FLEX_EDITOR_FLEX_HDR_0_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3852 /* FLEX_EDITOR_FLEX_HDR_0_OW_PROFILE_TABLE */ "This provides the commands for overwriting fixed header with flex header fields", 3853 /* FLEX_EDITOR_FLEX_HDR_0_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3854 /* FLEX_EDITOR_FLEX_HDR_1_16BIT_FS_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3855 /* FLEX_EDITOR_FLEX_HDR_1_32BIT_FS_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3856 /* FLEX_EDITOR_FLEX_HDR_1_ALU_PROFILE_TABLE */ "This provides the commands for the ALU operations in the flex hc engine", 3857 /* FLEX_EDITOR_FLEX_HDR_1_HC_PROFILE_TABLE */ "This provides the commands to shift the new fields for the rewrite", 3858 /* FLEX_EDITOR_FLEX_HDR_1_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3859 /* FLEX_EDITOR_FLEX_HDR_1_OW_PROFILE_TABLE */ "This provides the commands for overwriting fixed header with flex header fields", 3860 /* FLEX_EDITOR_FLEX_HDR_1_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3861 /* FLEX_EDITOR_FLEX_HDR_2_16BIT_FS_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3862 /* FLEX_EDITOR_FLEX_HDR_2_32BIT_FS_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3863 /* FLEX_EDITOR_FLEX_HDR_2_ALU_PROFILE_TABLE */ "This provides the commands for the ALU operations in the flex hc engine", 3864 /* FLEX_EDITOR_FLEX_HDR_2_HC_PROFILE_TABLE */ "This provides the commands to shift the new fields for the rewrite", 3865 /* FLEX_EDITOR_FLEX_HDR_2_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3866 /* FLEX_EDITOR_FLEX_HDR_2_OW_PROFILE_TABLE */ "This provides the commands for overwriting fixed header with flex header fields", 3867 /* FLEX_EDITOR_FLEX_HDR_2_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3868 /* FLEX_EDITOR_MHC_CHECKSUM_0_PROFILE_TABLE */ "This provides the commands for multi-header module checksum computation", 3869 /* FLEX_EDITOR_MHC_CHECKSUM_1_PROFILE_TABLE */ "This provides the commands for multi-header module checksum computation", 3870 /* FLEX_EDITOR_MHC_CHECKSUM_2_PROFILE_TABLE */ "This provides the commands for multi-header module checksum computation", 3871 /* FLEX_EDITOR_MHC_CRC_0_PROFILE_TABLE */ "This provides the commands for multi-header module CRC operations", 3872 /* FLEX_EDITOR_MIRROR_ENCAP_0_PROFILE_1_TABLE */ "This controls the mirror encap headers constructed", 3873 /* FLEX_EDITOR_MIRROR_ENCAP_0_PROFILE_2_TABLE */ "This controls the mirror encap headers constructed", 3874 /* FLEX_EDITOR_MIRROR_ENCAP_0_PROFILE_3_TABLE */ "This controls the mirror encap headers constructed", 3875 /* FLEX_EDITOR_RW_0_ALU_PROFILE_TABLE */ "This provides the commands for the ALU operations in the rewrite engine", 3876 /* FLEX_EDITOR_RW_0_FS_PROFILE_TABLE */ "This provides the selection of the containers for rewrite fields", 3877 /* FLEX_EDITOR_RW_0_HC_PROFILE_TABLE */ "This provides the commands to shift the new fields for the rewrite", 3878 /* FLEX_EDITOR_RW_0_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3879 /* FLEX_EDITOR_RW_0_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3880 /* FLEX_EDITOR_RW_1_ALU_PROFILE_TABLE */ "This provides the commands for the ALU operations in the rewrite engine", 3881 /* FLEX_EDITOR_RW_1_FS_PROFILE_TABLE */ "This provides the selection of the containers for rewrite fields", 3882 /* FLEX_EDITOR_RW_1_HC_PROFILE_TABLE */ "This provides the commands to shift the new fields for the rewrite", 3883 /* FLEX_EDITOR_RW_1_NEXT_PROTO_TABLE */ "This provides the next proto values for the header construction", 3884 /* FLEX_EDITOR_RW_1_PROFILE_TABLE */ "This provides the profile pointer to ALU and HC profile tables", 3885 /* FLEX_EDITOR_ZONE_0_EDIT_ID_DEL_TABLE */ "This provides the commands for headers deletion from Edit_ID_Del", 3886 /* FLEX_EDITOR_ZONE_0_EDIT_ID_INS_1_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3887 /* FLEX_EDITOR_ZONE_0_EDIT_ID_INS_2_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3888 /* FLEX_EDITOR_ZONE_0_EDIT_ID_RW_TABLE */ "This provides the commands for headers rewrite from Edit_ID_Rw", 3889 /* FLEX_EDITOR_ZONE_0_MATCH_ID_COMMAND_PROFILE_TABLE */ "This provides the command profile, e.g. CRC, CHECKSUM base on Match_ID", 3890 /* FLEX_EDITOR_ZONE_0_MATCH_ID_TABLE */ "This provides the ingress headers structure and property from Match_ID", 3891 /* FLEX_EDITOR_ZONE_1_EDIT_ID_DEL_TABLE */ "This provides the commands for headers deletion from Edit_ID_Del", 3892 /* FLEX_EDITOR_ZONE_1_EDIT_ID_INS_1_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3893 /* FLEX_EDITOR_ZONE_1_EDIT_ID_INS_2_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3894 /* FLEX_EDITOR_ZONE_1_EDIT_ID_RW_TABLE */ "This provides the commands for headers rewrite from Edit_ID_Rw", 3895 /* FLEX_EDITOR_ZONE_1_MATCH_ID_COMMAND_PROFILE_TABLE */ "This provides the command profile, e.g. CRC, CHECKSUM base on Match_ID", 3896 /* FLEX_EDITOR_ZONE_1_MATCH_ID_TABLE */ "This provides the ingress headers structure and property from Match_ID", 3897 /* FLEX_EDITOR_ZONE_2_EDIT_ID_DEL_TABLE */ "This provides the commands for headers deletion from Edit_ID_Del", 3898 /* FLEX_EDITOR_ZONE_2_EDIT_ID_INS_1_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3899 /* FLEX_EDITOR_ZONE_2_EDIT_ID_INS_2_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3900 /* FLEX_EDITOR_ZONE_2_EDIT_ID_RW_TABLE */ "This provides the commands for headers rewrite from Edit_ID_Rw", 3901 /* FLEX_EDITOR_ZONE_2_MATCH_ID_COMMAND_PROFILE_TABLE */ "This provides the command profile, e.g. CRC, CHECKSUM base on Match_ID", 3902 /* FLEX_EDITOR_ZONE_2_MATCH_ID_TABLE */ "This provides the ingress headers structure and property from Match_ID", 3903 /* FLEX_EDITOR_ZONE_3_EDIT_ID_DEL_TABLE */ "This provides the commands for headers deletion from Edit_ID_Del", 3904 /* FLEX_EDITOR_ZONE_3_EDIT_ID_INS_1_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3905 /* FLEX_EDITOR_ZONE_3_EDIT_ID_INS_2_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3906 /* FLEX_EDITOR_ZONE_3_EDIT_ID_RW_TABLE */ "This provides the commands for headers rewrite from Edit_ID_Rw", 3907 /* FLEX_EDITOR_ZONE_3_MATCH_ID_COMMAND_PROFILE_TABLE */ "This provides the command profile, e.g. CRC, CHECKSUM base on Match_ID", 3908 /* FLEX_EDITOR_ZONE_3_MATCH_ID_TABLE */ "This provides the ingress headers structure and property from Match_ID", 3909 /* FLEX_EDITOR_ZONE_4_EDIT_ID_DEL_TABLE */ "This provides the commands for headers deletion from Edit_ID_Del", 3910 /* FLEX_EDITOR_ZONE_4_EDIT_ID_INS_1_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3911 /* FLEX_EDITOR_ZONE_4_EDIT_ID_INS_2_TABLE */ "This provides the commands for headers insertion from Edit_ID_Ins", 3912 /* FLEX_EDITOR_ZONE_4_EDIT_ID_RW_TABLE */ "This provides the commands for headers rewrite from Edit_ID_Rw", 3913 /* FLEX_EDITOR_ZONE_4_MATCH_ID_COMMAND_PROFILE_TABLE */ "This provides the command profile, e.g. CRC, CHECKSUM base on Match_ID", 3914 /* FLEX_EDITOR_ZONE_4_MATCH_ID_TABLE */ "This provides the ingress headers structure and property from Match_ID", 3915 /* FLEX_RTAG7_HASH_TCAM */ "Combined FLEX_RTAG7_HASH TCAM/Data RAM for Flex RTAG7 hash.", 3916 /* FLEX_RTAG7_HASH_TCAM_DATA_ONLY */ "Data SRAM for FLEX_RTAG7_HASH_TCAM TCAM.", 3917 /* FLEX_RTAG7_HASH_TCAM_ONLY */ "TCAM for Flex RTAG7 HASH.", 3918 /* FLOOD_LEARN_MATCH_VLANS_PORT_A */ "VLAN Membership bitmap for PORT_A for FLOOD_LEARN.", 3919 /* FLOOD_LEARN_MATCH_VLANS_PORT_B */ "VLAN Membership bitmap for PORT_B for FLOOD_LEARN.", 3920 /* FLOW_SN_WINDOW_RESET_INDICATION */ "FLOW SN_WINDOW reset indication table.", 3921 /* FMAC_RX_FEC_BUFFER_0 */ "", 3922 /* FMAC_RX_FEC_BUFFER_1 */ "", 3923 /* FMAC_RX_RRR_CTRL */ "", 3924 /* FMAC_RX_RRR_DATA */ "", 3925 /* FMAC_RX_RRR_HEADER */ "", 3926 /* FMAC_TX_TRR_DATA_HEADER */ "", 3927 /* FMAC_TX_TRR_DATA_PAYLOAD */ "", 3928 /* FORWARDING_1_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table FORWARDING_1.", 3929 /* FORWARDING_1_FIXED_KEY_TABLE_ATTRS */ "FORWARDING_1 Fixed Key Table Attributes.", 3930 /* FORWARDING_1_KEY_GEN_1_MASK */ "L2_ENTRY : Lookup1 key mask", 3931 /* FORWARDING_1_KEY_GEN_1_MASK_PIPE0 */ "L2_ENTRY : Lookup1 key mask", 3932 /* FORWARDING_1_KEY_GEN_1_MUX_CTRL */ "L2_ENTRY : Lookup 1 key. Key Generator Profile Table that provides instructions for Key Generation", 3933 /* FORWARDING_1_KEY_GEN_1_MUX_CTRL_PIPE0 */ "L2_ENTRY : Lookup 1 key. Key Generator Profile Table that provides instructions for Key Generation", 3934 /* FORWARDING_1_KEY_GEN_2_MASK */ ":2_ENTRY : Lookup2 key mask", 3935 /* FORWARDING_1_KEY_GEN_2_MASK_PIPE0 */ ":2_ENTRY : Lookup2 key mask", 3936 /* FORWARDING_1_KEY_GEN_2_MUX_CTRL */ "L2_ENTRY : Lookup 2 key. Key Generator Profile Table that provides instructions for Key Generation", 3937 /* FORWARDING_1_KEY_GEN_2_MUX_CTRL_PIPE0 */ "L2_ENTRY : Lookup 2 key. Key Generator Profile Table that provides instructions for Key Generation", 3938 /* FORWARDING_1_LOGICAL_TBL_SEL_SRAM */ "L2_ENTRY : Flex key lookup control sram", 3939 /* FORWARDING_1_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "L2_ENTRY : Flex key lookup control sram", 3940 /* FORWARDING_1_LOGICAL_TBL_SEL_TCAM */ "L2_ENTRY : Key Selection TCAM", 3941 /* FORWARDING_1_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "L2_ENTRY : Key Selection TCAM", 3942 /* FORWARDING_1_MISS_POLICY */ "VLAN_XLATE_1 Table Miss Policy.", 3943 /* FORWARDING_1_POLICY_STRENGTH_PROFILE */ "Packet Process Header Valid Check Profile Table 2.", 3944 /* FORWARDING_2_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table FORWARDING_2.", 3945 /* FORWARDING_2_FIXED_KEY_TABLE_ATTRS */ "FORWARDING_2 Fixed Key Table Attributes.", 3946 /* FORWARDING_2_KEY_GEN_1_MASK */ "L3_ENTRY : Lookup1 key[127:0] mask", 3947 /* FORWARDING_2_KEY_GEN_1_MASK_PIPE0 */ "L3_ENTRY : Lookup1 key[127:0] mask", 3948 /* FORWARDING_2_KEY_GEN_1_MUX_CTRL */ "L3_ENTRY : Lookup 1 key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 3949 /* FORWARDING_2_KEY_GEN_1_MUX_CTRL_PIPE0 */ "L3_ENTRY : Lookup 1 key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 3950 /* FORWARDING_2_KEY_GEN_2_MASK */ "L3_ENTRY : Lookup1 key[255:128] mask", 3951 /* FORWARDING_2_KEY_GEN_2_MASK_PIPE0 */ "L3_ENTRY : Lookup1 key[255:128] mask", 3952 /* FORWARDING_2_KEY_GEN_2_MUX_CTRL */ "L3_ENTRY : Lookup 1 key [255:128] Key Generator Profile Table that provides instructions for Key Generation", 3953 /* FORWARDING_2_KEY_GEN_2_MUX_CTRL_PIPE0 */ "L3_ENTRY : Lookup 1 key [255:128] Key Generator Profile Table that provides instructions for Key Generation", 3954 /* FORWARDING_2_KEY_GEN_3_MASK */ "L3_ENTRY : Lookup1 key[383:256] mask", 3955 /* FORWARDING_2_KEY_GEN_3_MASK_PIPE0 */ "L3_ENTRY : Lookup1 key[383:256] mask", 3956 /* FORWARDING_2_KEY_GEN_3_MUX_CTRL */ "L3_ENTRY : Lookup 1 key [383:256] Key Generator Profile Table that provides instructions for Key Generation", 3957 /* FORWARDING_2_KEY_GEN_3_MUX_CTRL_PIPE0 */ "L3_ENTRY : Lookup 1 key [383:256] Key Generator Profile Table that provides instructions for Key Generation", 3958 /* FORWARDING_2_KEY_GEN_4_MASK */ "L3_ENTRY : Lookup2 key[127:0] mask", 3959 /* FORWARDING_2_KEY_GEN_4_MASK_PIPE0 */ "L3_ENTRY : Lookup2 key[127:0] mask", 3960 /* FORWARDING_2_KEY_GEN_4_MUX_CTRL */ "L3_ENTRY : Lookup 2 key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 3961 /* FORWARDING_2_KEY_GEN_4_MUX_CTRL_PIPE0 */ "L3_ENTRY : Lookup 2 key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 3962 /* FORWARDING_2_KEY_GEN_5_MASK */ "L3_ENTRY : Lookup2 key[255:128] mask", 3963 /* FORWARDING_2_KEY_GEN_5_MASK_PIPE0 */ "L3_ENTRY : Lookup2 key[255:128] mask", 3964 /* FORWARDING_2_KEY_GEN_5_MUX_CTRL */ "L3_ENTRY : Lookup 2 key [255:128] Key Generator Profile Table that provides instructions for Key Generation", 3965 /* FORWARDING_2_KEY_GEN_5_MUX_CTRL_PIPE0 */ "L3_ENTRY : Lookup 2 key [255:128] Key Generator Profile Table that provides instructions for Key Generation", 3966 /* FORWARDING_2_KEY_GEN_6_MASK */ "L3_ENTRY : Lookup2 key[383:256] mask", 3967 /* FORWARDING_2_KEY_GEN_6_MASK_PIPE0 */ "L3_ENTRY : Lookup2 key[383:256] mask", 3968 /* FORWARDING_2_KEY_GEN_6_MUX_CTRL */ "L3_ENTRY : Lookup 2 key [383:256] Key Generator Profile Table that provides instructions for Key Generation", 3969 /* FORWARDING_2_KEY_GEN_6_MUX_CTRL_PIPE0 */ "L3_ENTRY : Lookup 2 key [383:256] Key Generator Profile Table that provides instructions for Key Generation", 3970 /* FORWARDING_2_LOGICAL_TBL_SEL_SRAM */ "L3_ENTRY : Flex key lookup control sram", 3971 /* FORWARDING_2_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "L3_ENTRY : Flex key lookup control sram", 3972 /* FORWARDING_2_LOGICAL_TBL_SEL_TCAM */ "L3_ENTRY : Key Selection TCAM", 3973 /* FORWARDING_2_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "L3_ENTRY : Key Selection TCAM", 3974 /* FORWARDING_2_MISS_POLICY */ "VLAN_XLATE_1 Table Miss Policy.", 3975 /* FORWARDING_2_POLICY_STRENGTH_PROFILE */ "Packet Process Header Valid Check Profile Table 2.", 3976 /* FORWARDING_3_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table FORWARDING_3.", 3977 /* FORWARDING_3_FIXED_KEY_TABLE_ATTRS */ "FORWARDING_3 Fixed Key Table Attributes.", 3978 /* FORWARDING_3_KEY_GEN_1_MASK */ "LPM : Lookup1 key[127:0] mask", 3979 /* FORWARDING_3_KEY_GEN_1_MASK_PIPE0 */ "LPM : Lookup1 key[127:0] mask", 3980 /* FORWARDING_3_KEY_GEN_1_MUX_CTRL */ "LPM : Lookup1 key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 3981 /* FORWARDING_3_KEY_GEN_1_MUX_CTRL_PIPE0 */ "LPM : Lookup1 key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 3982 /* FORWARDING_3_KEY_GEN_2_MASK */ "LPM : Lookup1 key[255:128] mask", 3983 /* FORWARDING_3_KEY_GEN_2_MASK_PIPE0 */ "LPM : Lookup1 key[255:128] mask", 3984 /* FORWARDING_3_KEY_GEN_2_MUX_CTRL */ "LPM : Lookup 1 key [255:128] Key Generator Profile Table that provides instructions for Key Generation", 3985 /* FORWARDING_3_KEY_GEN_2_MUX_CTRL_PIPE0 */ "LPM : Lookup 1 key [255:128] Key Generator Profile Table that provides instructions for Key Generation", 3986 /* FORWARDING_3_KEY_GEN_3_MASK */ "LPM : Lookup2 key[127:0] mask", 3987 /* FORWARDING_3_KEY_GEN_3_MASK_PIPE0 */ "LPM : Lookup2 key[127:0] mask", 3988 /* FORWARDING_3_KEY_GEN_3_MUX_CTRL */ "LPM : Lookup 2 key[127:0] Key Generator Profile Table that provides instructions for Key Generation", 3989 /* FORWARDING_3_KEY_GEN_3_MUX_CTRL_PIPE0 */ "LPM : Lookup 2 key[127:0] Key Generator Profile Table that provides instructions for Key Generation", 3990 /* FORWARDING_3_KEY_GEN_4_MASK */ "LPM : Lookup2 key[255:128] mask", 3991 /* FORWARDING_3_KEY_GEN_4_MASK_PIPE0 */ "LPM : Lookup2 key[255:128] mask", 3992 /* FORWARDING_3_KEY_GEN_4_MUX_CTRL */ "LPM : Lookup 2 key[255:128] Key Generator Profile Table that provides instructions for Key Generation", 3993 /* FORWARDING_3_KEY_GEN_4_MUX_CTRL_PIPE0 */ "LPM : Lookup 2 key[255:128] Key Generator Profile Table that provides instructions for Key Generation", 3994 /* FORWARDING_3_KEY_GEN_5_MASK */ "LPM : Lookup3 key[127:0] mask", 3995 /* FORWARDING_3_KEY_GEN_5_MASK_PIPE0 */ "LPM : Lookup3 key[127:0] mask", 3996 /* FORWARDING_3_KEY_GEN_5_MUX_CTRL */ "LPM : Lookup 3 key[127:0] Key Generator Profile Table that provides instructions for Key Generation", 3997 /* FORWARDING_3_KEY_GEN_5_MUX_CTRL_PIPE0 */ "LPM : Lookup 3 key[127:0] Key Generator Profile Table that provides instructions for Key Generation", 3998 /* FORWARDING_3_KEY_GEN_6_MASK */ "LPM : Lookup4 key[127:0] mask", 3999 /* FORWARDING_3_KEY_GEN_6_MASK_PIPE0 */ "LPM : Lookup4 key[127:0] mask", 4000 /* FORWARDING_3_KEY_GEN_6_MUX_CTRL */ "LPM : Lookup 4 key[127:0] Key Generator Profile Table that provides instructions for Key Generation", 4001 /* FORWARDING_3_KEY_GEN_6_MUX_CTRL_PIPE0 */ "LPM : Lookup 4 key[127:0] Key Generator Profile Table that provides instructions for Key Generation", 4002 /* FORWARDING_3_LOGICAL_TBL_SEL_SRAM */ "LPM(L3_DEFIP) : Flex key lookup control sram", 4003 /* FORWARDING_3_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "LPM(L3_DEFIP) : Flex key lookup control sram", 4004 /* FORWARDING_3_LOGICAL_TBL_SEL_TCAM */ "LPM(L3_DEFIP) : Key Selection TCAM", 4005 /* FORWARDING_3_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "LPM(L3_DEFIP) : Key Selection TCAM", 4006 /* FORWARDING_3_MISS_POLICY */ "VLAN_XLATE_1 Table Miss Policy.", 4007 /* FORWARDING_3_POLICY_STRENGTH_PROFILE */ "Packet Process Header Valid Check Profile Table 2.", 4008 /* FPEM_ECC */ "FPEM ECC Table", 4009 /* FPEM_ECC_PIPE0 */ "FPEM ECC Table", 4010 /* FPEM_ECC_PIPE1 */ "FPEM ECC Table", 4011 /* FPEM_ECC_PIPE2 */ "FPEM ECC Table", 4012 /* FPEM_ECC_PIPE3 */ "FPEM ECC Table", 4013 /* FPEM_LP */ "FPEM LP Control Table.", 4014 /* FP_COUNTER_TABLE */ "COUNTER TABLE FOR THE FP", 4015 /* FP_COUNTER_TABLE_X */ "COUNTER TABLE FOR THE FP in IPX. FeatureSpecific-FP", 4016 /* FP_COUNTER_TABLE_Y */ "COUNTER TABLE FOR THE FP in IPY. FeatureSpecific-FP", 4017 /* FP_FLEX_KEY_SELECTOR */ "Controls classid selection into HG header.", 4018 /* FP_GLOBAL_MASK_TCAM */ "PORT BITMAP TCAM ENTRY FOR EACH IFP_TCAM ENTRY.", 4019 /* FP_GLOBAL_MASK_TCAM_X */ "IPB view of the IFP_TCAM.", 4020 /* FP_GLOBAL_MASK_TCAM_Y */ "IPB view of the IFP_TCAM.", 4021 /* FP_GM_FIELDS */ "Fields view of IFP_GM TCAM.", 4022 /* FP_GM_FIELDS_X */ "Fields view of IFP_GM TCAM.", 4023 /* FP_GM_FIELDS_Y */ "Fields view of IFP_GM TCAM.", 4024 /* FP_HG_CLASSID_SELECT */ "Controls classid selection into HG header.", 4025 /* FP_I2E_CLASSID_SELECT */ "Selects one classid from IP tables to be passed to EP.", 4026 /* FP_METER_CONTROL */ "Extra number of bytes that can be added(IFP, preamble) to achieve actual Ethernet throughput", 4027 /* FP_METER_TABLE */ "METER TABLE STRUCTURES FOR THE FP", 4028 /* FP_METER_TABLE_X */ "METER TABLE STRUCTURES FOR THE FP in IPX. FeatureSpecific-FP", 4029 /* FP_METER_TABLE_Y */ "METER TABLE STRUCTURES FOR THE FP in IPY. FeatureSpecific-FP", 4030 /* FP_POLICY_TABLE */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE FP", 4031 /* FP_PORT_FIELD_SEL */ "FIELD SELECT VALUE FOR EACH SLICE IN THE FP", 4032 /* FP_PORT_METER_MAP */ "FP_PORT_METER_MAP TABLE STRUCTURES FOR THE FP, FeatureSpecific-FP", 4033 /* FP_RANGE_CHECK */ "RANGE CHECK VALUES FOR FP", 4034 /* FP_SC_BCAST_METER_TABLE */ "SC METER TABLE STRUCTURES FOR THE FP. Indexed using ingress port number.", 4035 /* FP_SC_DLF_METER_TABLE */ "SC METER TABLE STRUCTURES FOR THE FP. Indexed using ingress port number.", 4036 /* FP_SC_MCAST_METER_TABLE */ "SC METER TABLE STRUCTURES FOR THE FP. Indexed using ingress port number.", 4037 /* FP_SC_METER_TABLE */ "SC METER TABLE STRUCTURES FOR THE FP", 4038 /* FP_SLICE_ENTRY_PORT_SEL */ "ENTRIES ENABLED FOR EACH SOURCE PORT FOR EACH SLICE. The index for this table is created by concatenating {Ingress Port(6bits) and Slice Number(3bits)}.", 4039 /* FP_SLICE_KEY_CONTROL */ "SLICE KEY GENERATION CONTROLS FOR IFP, FeatureSpecific-FP", 4040 /* FP_SLICE_MAP */ "SLICE MAPPING CONTROLS FOR IFP", 4041 /* FP_STORM_CONTROL_METERS */ "STORM CONTROL METER TABLE STRUCTURES FOR THE FP, FeatureSpecific-FP", 4042 /* FP_STORM_CONTROL_METERS_X */ "STORM CONTROL METER TABLE STRUCTURES FOR THE FP, FeatureSpecific-FP.", 4043 /* FP_STORM_CONTROL_METERS_Y */ "STORM CONTROL METER TABLE STRUCTURES FOR THE FP, FeatureSpecific-FP.", 4044 /* FP_TCAM */ "TCAM FOR FP", 4045 /* FP_TCAM_PLUS_POLICY */ "TCAM AND POLICY TABLE VIEW FOR FP", 4046 /* FP_TCAM_X */ "FP TCAM in IPX", 4047 /* FP_TCAM_Y */ "FP TCAM in IPY", 4048 /* FP_UDF_OFFSET */ "FP UDF offset table", 4049 /* FP_UDF_OFFSET_PIPE0 */ "FP UDF Offset Table.", 4050 /* FP_UDF_OFFSET_PIPE1 */ "FP UDF Offset Table.", 4051 /* FP_UDF_OFFSET_PIPE2 */ "FP UDF Offset Table.", 4052 /* FP_UDF_OFFSET_PIPE3 */ "FP UDF Offset Table.", 4053 /* FP_UDF_OFFSET_PIPE4 */ "FP UDF Offset Table.", 4054 /* FP_UDF_OFFSET_PIPE5 */ "FP UDF Offset Table.", 4055 /* FP_UDF_OFFSET_PIPE6 */ "FP UDF Offset Table.", 4056 /* FP_UDF_OFFSET_PIPE7 */ "FP UDF Offset Table.", 4057 /* FP_UDF_TCAM */ "FP UDF tcam table, FeatureSpecific-FP", 4058 /* FP_UDF_TCAM_PIPE0 */ "FP UDF TCAM Table.", 4059 /* FP_UDF_TCAM_PIPE1 */ "FP UDF TCAM Table.", 4060 /* FP_UDF_TCAM_PIPE2 */ "FP UDF TCAM Table.", 4061 /* FP_UDF_TCAM_PIPE3 */ "FP UDF TCAM Table.", 4062 /* FP_UDF_TCAM_PIPE4 */ "FP UDF TCAM Table.", 4063 /* FP_UDF_TCAM_PIPE5 */ "FP UDF TCAM Table.", 4064 /* FP_UDF_TCAM_PIPE6 */ "FP UDF TCAM Table.", 4065 /* FP_UDF_TCAM_PIPE7 */ "FP UDF TCAM Table.", 4066 /* FQP_BUF_LINK */ "Buffers link memory", 4067 /* FQP_DBF_PIPE_FIFO */ "DBF pipe FIFO for data pending for DBF data to return", 4068 /* FQP_ETS_CRDT_TABLE */ "ETS credit table", 4069 /* FQP_FQP_NIF_PORT_MUX */ "Round robin for NIF ports in NIF ports scheduler.", 4070 /* FQP_OTM_METER_CRDT_BALANCE */ "Credit Balance Memory for OTM metering", 4071 /* FQP_OTM_METER_NIF_DC */ "DC compensation for IPG and CRC\n entry per 9 bits OTM", 4072 /* FQP_OTM_METER_TABLE */ "ETS credit table", 4073 /* FQP_PER_IFC_CFG */ "Per EGQ interface configuration in FQP. The FQP (Transmit queues) block maintains a queue per interface (124 NIF ports, Cmic, OLP, OAM and RCY).", 4074 /* FQP_PHANTOM_QS_CFG */ "Per OTM port Phantom Qs configuration", 4075 /* FQP_RCNT */ "Read Counter Memory", 4076 /* FQP_TXQ */ "Transmit Queue FIFOs memory used for buffering the FQP descriptors.\n Contain all fields that are used in ETS pipe", 4077 /* FQP_TXQ_NO_BUF */ "Transmit Queue FIFOs memory used for buffering the FQP descriptors.\n Contain all fields that are not used in ETS pipe", 4078 /* FSRD_FSRD_PROM_MEM */ "SerDes PRAM interface.", 4079 /* FSRD_FSRD_WL_EXT_MEM */ "WarpLite 8051 memory interface.", 4080 /* FSRD_MAC_OUTPUT_BUFFER */ "Shared output buffer memory", 4081 /* FT_AGE_PROFILE */ "DPI Flow Tracker. Age profile for inactivity timeout", 4082 /* FT_COMMAND */ "Phantom Flow Tracker Command Structure. SW writes to this single entry table to trigger HW actions. NOT READABLE.", 4083 /* FT_COMMAND_PIPE0 */ "Phantom Flow Tracker Command Structure. SW writes to this single entry table to trigger HW actions. NOT READABLE.", 4084 /* FT_DST_LAG_CONFIG */ "DPI Flow Tracker L4 destination lag enable", 4085 /* FT_DST_PORT_CONFIG */ "DPI Flow Tracker L4 destination port enable", 4086 /* FT_EOP_TBL */ "DPI Flow Tracker. stores data between sop/eop cells", 4087 /* FT_EXPORT_CNTR_ONLY */ "DPI Flow Tracker Export Fifo counters", 4088 /* FT_EXPORT_DATA_ONLY */ "Flow tracker export fifo.", 4089 /* FT_EXPORT_FIFO */ "DPI Flow Tracker Export Fifo", 4090 /* FT_GROUP_TABLE_CNT */ "Flow Tracker Group Counter Table. Index is group_id. HW managed flow count per group_id.", 4091 /* FT_GROUP_TABLE_CNT_PIPE0 */ "Flow Tracker Group Counter Table. Index is group_id. HW managed flow count per group_id.", 4092 /* FT_GROUP_TABLE_CONFIG */ "Flow Tracker Group Config Table. Index is group_id. Stores default associated data used by HW learn and Flow Threshold per group_id.", 4093 /* FT_GROUP_TABLE_CONFIG_PIPE0 */ "Flow Tracker Group Config Table. Index is group_id. Stores default associated data used by HW learn and Flow Threshold per group_id.", 4094 /* FT_HITBIT */ "Flow Tracker hitbit table. Tracks EXACT_MATCH Hash Table hitbits when flow tracker enabled.", 4095 /* FT_HITBIT_PIPE0 */ "Flow Tracker hitbit table. Tracks EXACT_MATCH Hash Table hitbits when flow tracker enabled.", 4096 /* FT_KEY_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 4097 /* FT_KEY_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 4098 /* FT_KEY_DOUBLE */ "flow tracker hash table double wide view.", 4099 /* FT_KEY_DOUBLE_PIPE0 */ "flow tracker hash table double wide view.", 4100 /* FT_KEY_ECC */ "ECC Table.", 4101 /* FT_KEY_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 4102 /* FT_KEY_KEY_ATTRIBUTES */ "Key Attributes Table.", 4103 /* FT_KEY_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 4104 /* FT_KEY_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 4105 /* FT_KEY_SINGLE */ "", 4106 /* FT_KEY_SS0_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 4107 /* FT_KEY_SS1_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 4108 /* FT_L4PORT */ "DPI Flow Tracker L4 Port filtering", 4109 /* FT_POLICY */ "Flow tracker policy table.", 4110 /* FT_SESSION */ "DPI Flow Tracker Session Table", 4111 /* FT_SESSION_IPV6 */ "DPI Flow Tracker Session Table", 4112 /* GPORT_EHG_RX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 4113 /* GPORT_EHG_RX_TUNNEL_MASK */ "Embedded Higig Rx tunnel data memory", 4114 /* GPORT_EHG_TX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 4115 /* GPORT_WC_UCMEM_DATA */ "Warpcore External Memory Interface to program micro-controller memory", 4116 /* GTP_PORT_TABLE */ "GTP_PORT_TABLE.", 4117 /* HBC_BANK_ORDER_FIFO */ "Fifo holding the bank for each pending read transaction in order of arrival", 4118 /* HBC_ECC_INFO_FIFO */ "fifo holding transaction information for reporting of ECC errors", 4119 /* HBC_HBM_DRAM_CPU_ACCESS */ "Dram CPU access", 4120 /* HBC_HBM_PHY_CH_REGISTER_ACCESS */ "Interface for PHY register access", 4121 /* HBC_RDR_CHUNK_STORAGE */ "Reassembly memory - Number of lines is the maximum number of banks.", 4122 /* HBC_RDR_INFO_FIFO */ "Read reassembly info fifo", 4123 /* HBC_READ_DATA_ASYNC_FIFO */ "Read data async fifo", 4124 /* HBC_READ_DATA_REORDER */ "Read data reorder memory", 4125 /* HBC_READ_PER_BANK_QUEUES */ "memory holding per bank read request queues", 4126 /* HBC_READ_REQUEST_ASYNC_FIFO */ "Read request async fifo", 4127 /* HBC_WRITE_DATA_ASYNC_FIFO */ "Write data async fifo", 4128 /* HBC_WRITE_DATA_BUFFER */ "Holds the data for write requests currently in the PBQ", 4129 /* HBC_WRITE_LATENCY_DELAY */ "data buffer for write latency delay", 4130 /* HBC_WRITE_PER_BANK_QUEUES */ "memory holding per bank write request queues", 4131 /* HBC_WRITE_REQUEST_ASYNC_FIFO */ "Write Request async fifo", 4132 /* HBMC_HBM_PHY_CHM_REGISTER_ACCESS */ "HBM PHY midstack register access error", 4133 /* HGT_DLB_CONTROL */ "HG-Trunk DLB Control.", 4134 /* HG_TRUNK_BITMAP */ "HiGig Trunk [0-31] Membership Bitmap.", 4135 /* HG_TRUNK_FAILOVER_ENABLE */ "HiGig Trunk Failover Enable Register.", 4136 /* HG_TRUNK_FAILOVER_SET */ "Higig Trunk Failover Set Table", 4137 /* HG_TRUNK_GROUP */ "HG Trunk group table.", 4138 /* HG_TRUNK_MEMBER */ "Contains the list of all HG Trunk members.", 4139 /* HG_TRUNK_MODE */ "HiGig Trunk Group Load Balancing Mode.", 4140 /* HG_TRUNK_RR_CNT */ "HiGig Trunk Group Round Robin Count.", 4141 /* HG_TRUNK_RR_CNT_PIPE0 */ "HiGig Trunk Group Round Robin Count.", 4142 /* HG_TRUNK_RR_CNT_PIPE1 */ "HiGig Trunk Group Round Robin Count.", 4143 /* HG_TRUNK_RR_CNT_PIPE2 */ "HiGig Trunk Group Round Robin Count.", 4144 /* HG_TRUNK_RR_CNT_PIPE3 */ "HiGig Trunk Group Round Robin Count.", 4145 /* HIGIG_TRUNK_CONTROL */ "HiGig Trunk Control Register.", 4146 /* HSP_SCHED_L0_ACCUM_COMP_MEM_0 */ "Hardware internal working memory in pipe X", 4147 /* HSP_SCHED_L0_ACCUM_COMP_MEM_1 */ "Hardware internal working memory in pipe Y", 4148 /* HSP_SCHED_L0_CREDIT_MEM_0 */ "Hardware internal working memory in pipe X", 4149 /* HSP_SCHED_L0_CREDIT_MEM_1 */ "Hardware internal working memory in pipe Y", 4150 /* HSP_SCHED_L0_NODE_WEIGHT */ "Hardware internal working memory in pipe X", 4151 /* HSP_SCHED_L1_ACCUM_COMP_MEM_0 */ "Hardware internal working memory in pipe X", 4152 /* HSP_SCHED_L1_ACCUM_COMP_MEM_1 */ "Hardware internal working memory in pipe Y", 4153 /* HSP_SCHED_L1_CREDIT_MEM_0 */ "Hardware internal working memory in pipe X", 4154 /* HSP_SCHED_L1_CREDIT_MEM_1 */ "Hardware internal working memory in pipe Y", 4155 /* HSP_SCHED_L1_NODE_WEIGHT */ "Hardware internal working memory in pipe X", 4156 /* HSP_SCHED_L2_ACCUM_COMP_MEM_0 */ "Hardware internal working memory in pipe X", 4157 /* HSP_SCHED_L2_ACCUM_COMP_MEM_1 */ "Hardware internal working memory in pipe Y", 4158 /* HSP_SCHED_L2_CREDIT_MEM_0 */ "Hardware internal working memory in pipe X", 4159 /* HSP_SCHED_L2_CREDIT_MEM_1 */ "Hardware internal working memory in pipe Y", 4160 /* HSP_SCHED_L2_MC_QUEUE_WEIGHT */ "Hardware internal working memory in pipe X", 4161 /* HSP_SCHED_L2_UC_QUEUE_WEIGHT */ "Hardware internal working memory in pipe X", 4162 /* HSP_SCHED_LAST_PORT_INFO */ "Hardware internal working memory in pipe X", 4163 /* HSP_SCHED_LAST_PREEMPT_PORT_INFO */ "Hardware internal working memory in pipe X", 4164 /* HSP_UCQ_FREE */ "HSP UCQ Structure Free List and Next Pointer Memory", 4165 /* HSP_UCQ_UCQE */ "HSP Unicast QEntry memory. Contains FIFO block linked lists for each HSP UC queue", 4166 /* HVE_DOS_ATTACK_MASK */ "DOS Attack Mask.", 4167 /* IARB_ING_PHYSICAL_PORT */ "Per Physical port OLP Enable Control", 4168 /* IARB_ING_PORT_TABLE */ "Per ingress port OLP Enable Control", 4169 /* IARB_MAIN_TDM */ "TDM TABLE configuration, Set to 0, select port_group5. Set to 1, select port_group4. Set to 2, select extra slot.", 4170 /* IARB_MAIN_TDM_X */ "TDM TABLE configuration, Set to 0, select PGW0. Set to 1, select PGW1. Set to 2, select extra slot.", 4171 /* IARB_MAIN_TDM_Y */ "TDM TABLE configuration, Set to 0, select PGW0. Set to 1, select PGW1. Set to 2, select extra slot.", 4172 /* IARB_TDM_TABLE */ "Arbiter TDM Table", 4173 /* IARB_TDM_TABLE_1 */ "Arbiter TDM Table - 1", 4174 /* IBOD_MOOSE_CLP0_CTRL_MEM */ "moose imem data", 4175 /* IBOD_MOOSE_CLP0_DATA_MEM_0 */ "moose dmem data", 4176 /* IBOD_MOOSE_CLP0_DATA_MEM_1 */ "moose dmem data", 4177 /* IBOD_MOOSE_CLP1_CTRL_MEM */ "moose imem data", 4178 /* IBOD_MOOSE_CLP1_DATA_MEM_0 */ "moose dmem data", 4179 /* IBOD_MOOSE_CLP1_DATA_MEM_1 */ "moose dmem data", 4180 /* IBOD_MOOSE_CLP2_CTRL_MEM */ "moose imem data", 4181 /* IBOD_MOOSE_CLP2_DATA_MEM_0 */ "moose dmem data", 4182 /* IBOD_MOOSE_CLP2_DATA_MEM_1 */ "moose dmem data", 4183 /* IBOD_MOOSE_XLP0_CTRL_MEM */ "moose imem data", 4184 /* IBOD_MOOSE_XLP0_DATA_MEM */ "moose dmem data", 4185 /* IBOD_MOOSE_XLP1_CTRL_MEM */ "moose imem data", 4186 /* IBOD_MOOSE_XLP1_DATA_MEM */ "moose dmem data", 4187 /* IBOD_MOOSE_XTP0_CTRL_MEM */ "moose imem data", 4188 /* IBOD_MOOSE_XTP0_DATA_MEM */ "moose dmem data", 4189 /* IBOD_MOOSE_XTP1_CTRL_MEM */ "moose imem data", 4190 /* IBOD_MOOSE_XTP1_DATA_MEM */ "moose dmem data", 4191 /* IBOD_MOOSE_XTP2_CTRL_MEM */ "moose imem data", 4192 /* IBOD_MOOSE_XTP2_DATA_MEM */ "moose dmem data", 4193 /* IBOD_MOOSE_XTP3_CTRL_MEM */ "moose imem data", 4194 /* IBOD_MOOSE_XTP3_DATA_MEM */ "moose dmem data", 4195 /* ICONTROL_OPCODE_BITMAP */ "Higig control packet's switching bitmap register.", 4196 /* IDB_DBM_12K */ "Data Buffer Memory", 4197 /* IDB_DBM_1K */ "Data Buffer Memoryn 1k each, shared with ILB", 4198 /* IDB_DBM_8K */ "Data Buffer Memory", 4199 /* IDB_OBM0_48_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4200 /* IDB_OBM0_48_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4201 /* IDB_OBM0_48_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4202 /* IDB_OBM0_48_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4203 /* IDB_OBM0_48_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4204 /* IDB_OBM0_48_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4205 /* IDB_OBM0_48_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4206 /* IDB_OBM0_48_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4207 /* IDB_OBM0_48_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4208 /* IDB_OBM0_48_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4209 /* IDB_OBM0_48_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4210 /* IDB_OBM0_48_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4211 /* IDB_OBM0_48_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4212 /* IDB_OBM0_48_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4213 /* IDB_OBM0_48_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4214 /* IDB_OBM0_48_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4215 /* IDB_OBM0_48_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4216 /* IDB_OBM0_48_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4217 /* IDB_OBM0_48_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4218 /* IDB_OBM0_48_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4219 /* IDB_OBM0_48_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4220 /* IDB_OBM0_48_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4221 /* IDB_OBM0_48_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4222 /* IDB_OBM0_48_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4223 /* IDB_OBM0_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4224 /* IDB_OBM0_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4225 /* IDB_OBM0_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4226 /* IDB_OBM0_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4227 /* IDB_OBM0_DSCP_MAP_PORT4 */ "Priority table based on DSCP.", 4228 /* IDB_OBM0_DSCP_MAP_PORT5 */ "Priority table based on DSCP.", 4229 /* IDB_OBM0_DSCP_MAP_PORT6 */ "Priority table based on DSCP.", 4230 /* IDB_OBM0_DSCP_MAP_PORT7 */ "Priority table based on DSCP.", 4231 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4232 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4233 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4234 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4235 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE4 */ "Priority table based on DSCP.", 4236 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE5 */ "Priority table based on DSCP.", 4237 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE6 */ "Priority table based on DSCP.", 4238 /* IDB_OBM0_DSCP_MAP_PORT0_PIPE7 */ "Priority table based on DSCP.", 4239 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4240 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4241 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4242 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4243 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE4 */ "Priority table based on DSCP.", 4244 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE5 */ "Priority table based on DSCP.", 4245 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE6 */ "Priority table based on DSCP.", 4246 /* IDB_OBM0_DSCP_MAP_PORT1_PIPE7 */ "Priority table based on DSCP.", 4247 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4248 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4249 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4250 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4251 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE4 */ "Priority table based on DSCP.", 4252 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE5 */ "Priority table based on DSCP.", 4253 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE6 */ "Priority table based on DSCP.", 4254 /* IDB_OBM0_DSCP_MAP_PORT2_PIPE7 */ "Priority table based on DSCP.", 4255 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4256 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4257 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4258 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4259 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE4 */ "Priority table based on DSCP.", 4260 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE5 */ "Priority table based on DSCP.", 4261 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE6 */ "Priority table based on DSCP.", 4262 /* IDB_OBM0_DSCP_MAP_PORT3_PIPE7 */ "Priority table based on DSCP.", 4263 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE0 */ "Priority table based on DSCP.", 4264 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE1 */ "Priority table based on DSCP.", 4265 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE2 */ "Priority table based on DSCP.", 4266 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE3 */ "Priority table based on DSCP.", 4267 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE4 */ "Priority table based on DSCP.", 4268 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE5 */ "Priority table based on DSCP.", 4269 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE6 */ "Priority table based on DSCP.", 4270 /* IDB_OBM0_DSCP_MAP_PORT4_PIPE7 */ "Priority table based on DSCP.", 4271 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE0 */ "Priority table based on DSCP.", 4272 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE1 */ "Priority table based on DSCP.", 4273 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE2 */ "Priority table based on DSCP.", 4274 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE3 */ "Priority table based on DSCP.", 4275 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE4 */ "Priority table based on DSCP.", 4276 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE5 */ "Priority table based on DSCP.", 4277 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE6 */ "Priority table based on DSCP.", 4278 /* IDB_OBM0_DSCP_MAP_PORT5_PIPE7 */ "Priority table based on DSCP.", 4279 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE0 */ "Priority table based on DSCP.", 4280 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE1 */ "Priority table based on DSCP.", 4281 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE2 */ "Priority table based on DSCP.", 4282 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE3 */ "Priority table based on DSCP.", 4283 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE4 */ "Priority table based on DSCP.", 4284 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE5 */ "Priority table based on DSCP.", 4285 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE6 */ "Priority table based on DSCP.", 4286 /* IDB_OBM0_DSCP_MAP_PORT6_PIPE7 */ "Priority table based on DSCP.", 4287 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE0 */ "Priority table based on DSCP.", 4288 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE1 */ "Priority table based on DSCP.", 4289 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE2 */ "Priority table based on DSCP.", 4290 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE3 */ "Priority table based on DSCP.", 4291 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE4 */ "Priority table based on DSCP.", 4292 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE5 */ "Priority table based on DSCP.", 4293 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE6 */ "Priority table based on DSCP.", 4294 /* IDB_OBM0_DSCP_MAP_PORT7_PIPE7 */ "Priority table based on DSCP.", 4295 /* IDB_OBM0_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4296 /* IDB_OBM0_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4297 /* IDB_OBM0_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4298 /* IDB_OBM0_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4299 /* IDB_OBM0_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4300 /* IDB_OBM0_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4301 /* IDB_OBM0_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4302 /* IDB_OBM0_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4303 /* IDB_OBM0_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4304 /* IDB_OBM0_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4305 /* IDB_OBM0_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4306 /* IDB_OBM0_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4307 /* IDB_OBM0_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4308 /* IDB_OBM0_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4309 /* IDB_OBM0_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4310 /* IDB_OBM0_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4311 /* IDB_OBM0_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4312 /* IDB_OBM0_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4313 /* IDB_OBM0_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4314 /* IDB_OBM0_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4315 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4316 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE0 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4317 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE1 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4318 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE2 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4319 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE3 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4320 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE4 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4321 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE5 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4322 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE6 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4323 /* IDB_OBM0_IOM_STATS_WINDOW_RESULTS_PIPE7 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4324 /* IDB_OBM0_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 4325 /* IDB_OBM0_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 4326 /* IDB_OBM0_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 4327 /* IDB_OBM0_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 4328 /* IDB_OBM0_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4329 /* IDB_OBM0_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4330 /* IDB_OBM0_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4331 /* IDB_OBM0_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4332 /* IDB_OBM0_PRI_MAP_PORT4 */ "Priority table based on PCP", 4333 /* IDB_OBM0_PRI_MAP_PORT5 */ "Priority table based on PCP", 4334 /* IDB_OBM0_PRI_MAP_PORT6 */ "Priority table based on PCP", 4335 /* IDB_OBM0_PRI_MAP_PORT7 */ "Priority table based on PCP", 4336 /* IDB_OBM0_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4337 /* IDB_OBM0_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 4338 /* IDB_OBM0_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 4339 /* IDB_OBM0_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 4340 /* IDB_OBM0_PRI_MAP_PORT0_PIPE4 */ "Priority table based on PCP.", 4341 /* IDB_OBM0_PRI_MAP_PORT0_PIPE5 */ "Priority table based on PCP.", 4342 /* IDB_OBM0_PRI_MAP_PORT0_PIPE6 */ "Priority table based on PCP.", 4343 /* IDB_OBM0_PRI_MAP_PORT0_PIPE7 */ "Priority table based on PCP.", 4344 /* IDB_OBM0_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4345 /* IDB_OBM0_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 4346 /* IDB_OBM0_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 4347 /* IDB_OBM0_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 4348 /* IDB_OBM0_PRI_MAP_PORT1_PIPE4 */ "Priority table based on PCP", 4349 /* IDB_OBM0_PRI_MAP_PORT1_PIPE5 */ "Priority table based on PCP", 4350 /* IDB_OBM0_PRI_MAP_PORT1_PIPE6 */ "Priority table based on PCP", 4351 /* IDB_OBM0_PRI_MAP_PORT1_PIPE7 */ "Priority table based on PCP", 4352 /* IDB_OBM0_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4353 /* IDB_OBM0_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 4354 /* IDB_OBM0_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 4355 /* IDB_OBM0_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 4356 /* IDB_OBM0_PRI_MAP_PORT2_PIPE4 */ "Priority table based on PCP", 4357 /* IDB_OBM0_PRI_MAP_PORT2_PIPE5 */ "Priority table based on PCP", 4358 /* IDB_OBM0_PRI_MAP_PORT2_PIPE6 */ "Priority table based on PCP", 4359 /* IDB_OBM0_PRI_MAP_PORT2_PIPE7 */ "Priority table based on PCP", 4360 /* IDB_OBM0_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4361 /* IDB_OBM0_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 4362 /* IDB_OBM0_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 4363 /* IDB_OBM0_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 4364 /* IDB_OBM0_PRI_MAP_PORT3_PIPE4 */ "Priority table based on PCP", 4365 /* IDB_OBM0_PRI_MAP_PORT3_PIPE5 */ "Priority table based on PCP", 4366 /* IDB_OBM0_PRI_MAP_PORT3_PIPE6 */ "Priority table based on PCP", 4367 /* IDB_OBM0_PRI_MAP_PORT3_PIPE7 */ "Priority table based on PCP", 4368 /* IDB_OBM0_PRI_MAP_PORT4_PIPE0 */ "Priority table based on PCP", 4369 /* IDB_OBM0_PRI_MAP_PORT4_PIPE1 */ "Priority table based on PCP", 4370 /* IDB_OBM0_PRI_MAP_PORT4_PIPE2 */ "Priority table based on PCP", 4371 /* IDB_OBM0_PRI_MAP_PORT4_PIPE3 */ "Priority table based on PCP", 4372 /* IDB_OBM0_PRI_MAP_PORT4_PIPE4 */ "Priority table based on PCP", 4373 /* IDB_OBM0_PRI_MAP_PORT4_PIPE5 */ "Priority table based on PCP", 4374 /* IDB_OBM0_PRI_MAP_PORT4_PIPE6 */ "Priority table based on PCP", 4375 /* IDB_OBM0_PRI_MAP_PORT4_PIPE7 */ "Priority table based on PCP", 4376 /* IDB_OBM0_PRI_MAP_PORT5_PIPE0 */ "Priority table based on PCP", 4377 /* IDB_OBM0_PRI_MAP_PORT5_PIPE1 */ "Priority table based on PCP", 4378 /* IDB_OBM0_PRI_MAP_PORT5_PIPE2 */ "Priority table based on PCP", 4379 /* IDB_OBM0_PRI_MAP_PORT5_PIPE3 */ "Priority table based on PCP", 4380 /* IDB_OBM0_PRI_MAP_PORT5_PIPE4 */ "Priority table based on PCP", 4381 /* IDB_OBM0_PRI_MAP_PORT5_PIPE5 */ "Priority table based on PCP", 4382 /* IDB_OBM0_PRI_MAP_PORT5_PIPE6 */ "Priority table based on PCP", 4383 /* IDB_OBM0_PRI_MAP_PORT5_PIPE7 */ "Priority table based on PCP", 4384 /* IDB_OBM0_PRI_MAP_PORT6_PIPE0 */ "Priority table based on PCP", 4385 /* IDB_OBM0_PRI_MAP_PORT6_PIPE1 */ "Priority table based on PCP", 4386 /* IDB_OBM0_PRI_MAP_PORT6_PIPE2 */ "Priority table based on PCP", 4387 /* IDB_OBM0_PRI_MAP_PORT6_PIPE3 */ "Priority table based on PCP", 4388 /* IDB_OBM0_PRI_MAP_PORT6_PIPE4 */ "Priority table based on PCP", 4389 /* IDB_OBM0_PRI_MAP_PORT6_PIPE5 */ "Priority table based on PCP", 4390 /* IDB_OBM0_PRI_MAP_PORT6_PIPE6 */ "Priority table based on PCP", 4391 /* IDB_OBM0_PRI_MAP_PORT6_PIPE7 */ "Priority table based on PCP", 4392 /* IDB_OBM0_PRI_MAP_PORT7_PIPE0 */ "Priority table based on PCP", 4393 /* IDB_OBM0_PRI_MAP_PORT7_PIPE1 */ "Priority table based on PCP", 4394 /* IDB_OBM0_PRI_MAP_PORT7_PIPE2 */ "Priority table based on PCP", 4395 /* IDB_OBM0_PRI_MAP_PORT7_PIPE3 */ "Priority table based on PCP", 4396 /* IDB_OBM0_PRI_MAP_PORT7_PIPE4 */ "Priority table based on PCP", 4397 /* IDB_OBM0_PRI_MAP_PORT7_PIPE5 */ "Priority table based on PCP", 4398 /* IDB_OBM0_PRI_MAP_PORT7_PIPE6 */ "Priority table based on PCP", 4399 /* IDB_OBM0_PRI_MAP_PORT7_PIPE7 */ "Priority table based on PCP", 4400 /* IDB_OBM0_Q_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4401 /* IDB_OBM0_Q_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4402 /* IDB_OBM0_Q_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4403 /* IDB_OBM0_Q_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4404 /* IDB_OBM0_Q_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4405 /* IDB_OBM0_Q_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4406 /* IDB_OBM0_Q_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4407 /* IDB_OBM0_Q_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4408 /* IDB_OBM0_Q_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4409 /* IDB_OBM0_Q_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4410 /* IDB_OBM0_Q_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4411 /* IDB_OBM0_Q_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4412 /* IDB_OBM0_Q_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4413 /* IDB_OBM0_Q_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4414 /* IDB_OBM0_Q_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4415 /* IDB_OBM0_Q_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4416 /* IDB_OBM0_Q_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4417 /* IDB_OBM0_Q_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4418 /* IDB_OBM0_Q_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4419 /* IDB_OBM0_Q_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4420 /* IDB_OBM0_Q_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4421 /* IDB_OBM0_Q_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4422 /* IDB_OBM0_Q_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4423 /* IDB_OBM0_Q_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4424 /* IDB_OBM10_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4425 /* IDB_OBM10_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4426 /* IDB_OBM10_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4427 /* IDB_OBM10_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4428 /* IDB_OBM10_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4429 /* IDB_OBM10_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4430 /* IDB_OBM10_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4431 /* IDB_OBM10_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4432 /* IDB_OBM10_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4433 /* IDB_OBM10_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4434 /* IDB_OBM10_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4435 /* IDB_OBM10_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4436 /* IDB_OBM10_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4437 /* IDB_OBM10_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4438 /* IDB_OBM10_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4439 /* IDB_OBM10_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4440 /* IDB_OBM10_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4441 /* IDB_OBM10_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4442 /* IDB_OBM10_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4443 /* IDB_OBM10_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4444 /* IDB_OBM10_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4445 /* IDB_OBM10_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4446 /* IDB_OBM10_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4447 /* IDB_OBM10_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4448 /* IDB_OBM10_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4449 /* IDB_OBM10_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4450 /* IDB_OBM10_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4451 /* IDB_OBM10_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4452 /* IDB_OBM10_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4453 /* IDB_OBM10_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4454 /* IDB_OBM10_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4455 /* IDB_OBM10_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4456 /* IDB_OBM10_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4457 /* IDB_OBM10_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4458 /* IDB_OBM10_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4459 /* IDB_OBM10_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4460 /* IDB_OBM10_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4461 /* IDB_OBM10_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4462 /* IDB_OBM10_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4463 /* IDB_OBM10_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4464 /* IDB_OBM10_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4465 /* IDB_OBM10_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4466 /* IDB_OBM10_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4467 /* IDB_OBM10_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4468 /* IDB_OBM10_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4469 /* IDB_OBM10_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 4470 /* IDB_OBM10_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 4471 /* IDB_OBM10_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 4472 /* IDB_OBM10_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4473 /* IDB_OBM10_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 4474 /* IDB_OBM10_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 4475 /* IDB_OBM10_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 4476 /* IDB_OBM10_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4477 /* IDB_OBM10_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 4478 /* IDB_OBM10_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 4479 /* IDB_OBM10_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 4480 /* IDB_OBM10_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4481 /* IDB_OBM10_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 4482 /* IDB_OBM10_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 4483 /* IDB_OBM10_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 4484 /* IDB_OBM11_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4485 /* IDB_OBM11_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4486 /* IDB_OBM11_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4487 /* IDB_OBM11_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4488 /* IDB_OBM11_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4489 /* IDB_OBM11_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4490 /* IDB_OBM11_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4491 /* IDB_OBM11_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4492 /* IDB_OBM11_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4493 /* IDB_OBM11_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4494 /* IDB_OBM11_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4495 /* IDB_OBM11_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4496 /* IDB_OBM11_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4497 /* IDB_OBM11_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4498 /* IDB_OBM11_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4499 /* IDB_OBM11_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4500 /* IDB_OBM11_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4501 /* IDB_OBM11_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4502 /* IDB_OBM11_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4503 /* IDB_OBM11_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4504 /* IDB_OBM11_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4505 /* IDB_OBM11_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4506 /* IDB_OBM11_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4507 /* IDB_OBM11_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4508 /* IDB_OBM11_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4509 /* IDB_OBM11_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4510 /* IDB_OBM11_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4511 /* IDB_OBM11_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4512 /* IDB_OBM11_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4513 /* IDB_OBM11_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4514 /* IDB_OBM11_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4515 /* IDB_OBM11_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4516 /* IDB_OBM11_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4517 /* IDB_OBM11_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4518 /* IDB_OBM11_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4519 /* IDB_OBM11_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4520 /* IDB_OBM11_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4521 /* IDB_OBM11_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4522 /* IDB_OBM11_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4523 /* IDB_OBM11_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4524 /* IDB_OBM11_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4525 /* IDB_OBM11_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4526 /* IDB_OBM11_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4527 /* IDB_OBM11_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4528 /* IDB_OBM11_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4529 /* IDB_OBM11_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 4530 /* IDB_OBM11_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 4531 /* IDB_OBM11_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 4532 /* IDB_OBM11_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4533 /* IDB_OBM11_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 4534 /* IDB_OBM11_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 4535 /* IDB_OBM11_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 4536 /* IDB_OBM11_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4537 /* IDB_OBM11_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 4538 /* IDB_OBM11_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 4539 /* IDB_OBM11_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 4540 /* IDB_OBM11_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4541 /* IDB_OBM11_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 4542 /* IDB_OBM11_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 4543 /* IDB_OBM11_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 4544 /* IDB_OBM12_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4545 /* IDB_OBM12_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4546 /* IDB_OBM12_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4547 /* IDB_OBM12_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4548 /* IDB_OBM12_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4549 /* IDB_OBM12_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4550 /* IDB_OBM12_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4551 /* IDB_OBM12_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4552 /* IDB_OBM12_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4553 /* IDB_OBM12_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4554 /* IDB_OBM12_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4555 /* IDB_OBM12_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4556 /* IDB_OBM12_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4557 /* IDB_OBM12_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4558 /* IDB_OBM12_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4559 /* IDB_OBM12_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4560 /* IDB_OBM12_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4561 /* IDB_OBM12_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4562 /* IDB_OBM12_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4563 /* IDB_OBM12_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4564 /* IDB_OBM12_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4565 /* IDB_OBM12_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4566 /* IDB_OBM12_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4567 /* IDB_OBM12_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4568 /* IDB_OBM12_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4569 /* IDB_OBM12_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4570 /* IDB_OBM12_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4571 /* IDB_OBM12_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4572 /* IDB_OBM12_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4573 /* IDB_OBM12_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4574 /* IDB_OBM12_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4575 /* IDB_OBM12_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4576 /* IDB_OBM12_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4577 /* IDB_OBM12_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4578 /* IDB_OBM12_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4579 /* IDB_OBM12_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4580 /* IDB_OBM12_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4581 /* IDB_OBM12_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4582 /* IDB_OBM12_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4583 /* IDB_OBM12_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4584 /* IDB_OBM12_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4585 /* IDB_OBM12_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4586 /* IDB_OBM12_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4587 /* IDB_OBM12_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4588 /* IDB_OBM12_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4589 /* IDB_OBM12_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 4590 /* IDB_OBM12_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 4591 /* IDB_OBM12_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 4592 /* IDB_OBM12_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4593 /* IDB_OBM12_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 4594 /* IDB_OBM12_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 4595 /* IDB_OBM12_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 4596 /* IDB_OBM12_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4597 /* IDB_OBM12_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 4598 /* IDB_OBM12_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 4599 /* IDB_OBM12_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 4600 /* IDB_OBM12_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4601 /* IDB_OBM12_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 4602 /* IDB_OBM12_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 4603 /* IDB_OBM12_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 4604 /* IDB_OBM13_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4605 /* IDB_OBM13_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4606 /* IDB_OBM13_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4607 /* IDB_OBM13_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4608 /* IDB_OBM13_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4609 /* IDB_OBM13_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4610 /* IDB_OBM13_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4611 /* IDB_OBM13_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4612 /* IDB_OBM13_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4613 /* IDB_OBM13_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4614 /* IDB_OBM13_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4615 /* IDB_OBM13_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4616 /* IDB_OBM13_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4617 /* IDB_OBM13_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4618 /* IDB_OBM13_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4619 /* IDB_OBM13_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4620 /* IDB_OBM13_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4621 /* IDB_OBM13_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4622 /* IDB_OBM13_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4623 /* IDB_OBM13_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4624 /* IDB_OBM13_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4625 /* IDB_OBM13_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4626 /* IDB_OBM13_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4627 /* IDB_OBM13_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4628 /* IDB_OBM13_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4629 /* IDB_OBM13_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4630 /* IDB_OBM13_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4631 /* IDB_OBM13_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4632 /* IDB_OBM13_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4633 /* IDB_OBM13_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4634 /* IDB_OBM13_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4635 /* IDB_OBM13_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4636 /* IDB_OBM13_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4637 /* IDB_OBM13_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4638 /* IDB_OBM13_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4639 /* IDB_OBM13_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4640 /* IDB_OBM13_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4641 /* IDB_OBM13_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4642 /* IDB_OBM13_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4643 /* IDB_OBM13_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4644 /* IDB_OBM13_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4645 /* IDB_OBM13_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4646 /* IDB_OBM13_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4647 /* IDB_OBM13_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4648 /* IDB_OBM13_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4649 /* IDB_OBM13_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 4650 /* IDB_OBM13_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 4651 /* IDB_OBM13_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 4652 /* IDB_OBM13_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4653 /* IDB_OBM13_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 4654 /* IDB_OBM13_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 4655 /* IDB_OBM13_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 4656 /* IDB_OBM13_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4657 /* IDB_OBM13_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 4658 /* IDB_OBM13_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 4659 /* IDB_OBM13_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 4660 /* IDB_OBM13_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4661 /* IDB_OBM13_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 4662 /* IDB_OBM13_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 4663 /* IDB_OBM13_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 4664 /* IDB_OBM14_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4665 /* IDB_OBM14_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4666 /* IDB_OBM14_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4667 /* IDB_OBM14_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4668 /* IDB_OBM14_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4669 /* IDB_OBM14_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4670 /* IDB_OBM14_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4671 /* IDB_OBM14_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4672 /* IDB_OBM14_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4673 /* IDB_OBM14_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4674 /* IDB_OBM14_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4675 /* IDB_OBM14_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4676 /* IDB_OBM14_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4677 /* IDB_OBM14_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4678 /* IDB_OBM14_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4679 /* IDB_OBM14_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4680 /* IDB_OBM14_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4681 /* IDB_OBM14_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4682 /* IDB_OBM14_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4683 /* IDB_OBM14_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4684 /* IDB_OBM14_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4685 /* IDB_OBM14_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4686 /* IDB_OBM14_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4687 /* IDB_OBM14_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4688 /* IDB_OBM14_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4689 /* IDB_OBM14_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4690 /* IDB_OBM14_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4691 /* IDB_OBM14_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4692 /* IDB_OBM14_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4693 /* IDB_OBM14_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4694 /* IDB_OBM14_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4695 /* IDB_OBM14_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4696 /* IDB_OBM14_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4697 /* IDB_OBM14_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4698 /* IDB_OBM14_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4699 /* IDB_OBM14_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4700 /* IDB_OBM14_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4701 /* IDB_OBM14_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4702 /* IDB_OBM14_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4703 /* IDB_OBM14_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4704 /* IDB_OBM14_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4705 /* IDB_OBM14_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4706 /* IDB_OBM14_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4707 /* IDB_OBM14_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4708 /* IDB_OBM14_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4709 /* IDB_OBM14_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 4710 /* IDB_OBM14_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 4711 /* IDB_OBM14_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 4712 /* IDB_OBM14_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4713 /* IDB_OBM14_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 4714 /* IDB_OBM14_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 4715 /* IDB_OBM14_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 4716 /* IDB_OBM14_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4717 /* IDB_OBM14_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 4718 /* IDB_OBM14_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 4719 /* IDB_OBM14_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 4720 /* IDB_OBM14_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4721 /* IDB_OBM14_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 4722 /* IDB_OBM14_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 4723 /* IDB_OBM14_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 4724 /* IDB_OBM15_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4725 /* IDB_OBM15_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4726 /* IDB_OBM15_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4727 /* IDB_OBM15_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4728 /* IDB_OBM15_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4729 /* IDB_OBM15_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4730 /* IDB_OBM15_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4731 /* IDB_OBM15_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4732 /* IDB_OBM15_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4733 /* IDB_OBM15_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4734 /* IDB_OBM15_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4735 /* IDB_OBM15_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4736 /* IDB_OBM15_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4737 /* IDB_OBM15_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4738 /* IDB_OBM15_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4739 /* IDB_OBM15_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4740 /* IDB_OBM15_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4741 /* IDB_OBM15_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4742 /* IDB_OBM15_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4743 /* IDB_OBM15_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4744 /* IDB_OBM15_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4745 /* IDB_OBM15_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4746 /* IDB_OBM15_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4747 /* IDB_OBM15_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4748 /* IDB_OBM15_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4749 /* IDB_OBM15_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4750 /* IDB_OBM15_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4751 /* IDB_OBM15_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4752 /* IDB_OBM15_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4753 /* IDB_OBM15_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4754 /* IDB_OBM15_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4755 /* IDB_OBM15_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4756 /* IDB_OBM15_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4757 /* IDB_OBM15_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4758 /* IDB_OBM15_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4759 /* IDB_OBM15_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4760 /* IDB_OBM15_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4761 /* IDB_OBM15_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4762 /* IDB_OBM15_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4763 /* IDB_OBM15_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4764 /* IDB_OBM15_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4765 /* IDB_OBM15_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4766 /* IDB_OBM15_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4767 /* IDB_OBM15_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4768 /* IDB_OBM15_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4769 /* IDB_OBM15_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 4770 /* IDB_OBM15_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 4771 /* IDB_OBM15_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 4772 /* IDB_OBM15_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4773 /* IDB_OBM15_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 4774 /* IDB_OBM15_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 4775 /* IDB_OBM15_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 4776 /* IDB_OBM15_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4777 /* IDB_OBM15_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 4778 /* IDB_OBM15_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 4779 /* IDB_OBM15_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 4780 /* IDB_OBM15_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4781 /* IDB_OBM15_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 4782 /* IDB_OBM15_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 4783 /* IDB_OBM15_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 4784 /* IDB_OBM16_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4785 /* IDB_OBM16_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4786 /* IDB_OBM16_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4787 /* IDB_OBM16_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4788 /* IDB_OBM16_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4789 /* IDB_OBM16_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4790 /* IDB_OBM16_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4791 /* IDB_OBM16_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4792 /* IDB_OBM16_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4793 /* IDB_OBM16_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4794 /* IDB_OBM16_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4795 /* IDB_OBM16_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4796 /* IDB_OBM16_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4797 /* IDB_OBM16_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4798 /* IDB_OBM16_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4799 /* IDB_OBM16_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4800 /* IDB_OBM16_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4801 /* IDB_OBM16_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4802 /* IDB_OBM16_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4803 /* IDB_OBM16_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4804 /* IDB_OBM16_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4805 /* IDB_OBM16_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4806 /* IDB_OBM16_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4807 /* IDB_OBM16_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4808 /* IDB_OBM17_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4809 /* IDB_OBM17_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4810 /* IDB_OBM17_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4811 /* IDB_OBM17_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4812 /* IDB_OBM17_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4813 /* IDB_OBM17_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4814 /* IDB_OBM17_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4815 /* IDB_OBM17_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4816 /* IDB_OBM17_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4817 /* IDB_OBM17_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4818 /* IDB_OBM17_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4819 /* IDB_OBM17_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4820 /* IDB_OBM17_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4821 /* IDB_OBM17_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4822 /* IDB_OBM17_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4823 /* IDB_OBM17_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4824 /* IDB_OBM17_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4825 /* IDB_OBM17_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4826 /* IDB_OBM17_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4827 /* IDB_OBM17_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4828 /* IDB_OBM17_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4829 /* IDB_OBM17_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4830 /* IDB_OBM17_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4831 /* IDB_OBM17_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4832 /* IDB_OBM18_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4833 /* IDB_OBM18_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4834 /* IDB_OBM18_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4835 /* IDB_OBM18_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4836 /* IDB_OBM18_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4837 /* IDB_OBM18_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4838 /* IDB_OBM18_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4839 /* IDB_OBM18_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4840 /* IDB_OBM18_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4841 /* IDB_OBM18_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4842 /* IDB_OBM18_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4843 /* IDB_OBM18_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4844 /* IDB_OBM18_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4845 /* IDB_OBM18_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4846 /* IDB_OBM18_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4847 /* IDB_OBM18_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4848 /* IDB_OBM18_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4849 /* IDB_OBM18_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4850 /* IDB_OBM18_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4851 /* IDB_OBM18_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4852 /* IDB_OBM18_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4853 /* IDB_OBM18_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4854 /* IDB_OBM18_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4855 /* IDB_OBM18_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4856 /* IDB_OBM19_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4857 /* IDB_OBM19_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4858 /* IDB_OBM19_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4859 /* IDB_OBM19_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4860 /* IDB_OBM19_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4861 /* IDB_OBM19_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4862 /* IDB_OBM19_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4863 /* IDB_OBM19_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4864 /* IDB_OBM19_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4865 /* IDB_OBM19_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4866 /* IDB_OBM19_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4867 /* IDB_OBM19_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4868 /* IDB_OBM19_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4869 /* IDB_OBM19_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4870 /* IDB_OBM19_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4871 /* IDB_OBM19_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4872 /* IDB_OBM19_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4873 /* IDB_OBM19_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4874 /* IDB_OBM19_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4875 /* IDB_OBM19_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4876 /* IDB_OBM19_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4877 /* IDB_OBM19_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4878 /* IDB_OBM19_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4879 /* IDB_OBM19_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4880 /* IDB_OBM1_48_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4881 /* IDB_OBM1_48_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4882 /* IDB_OBM1_48_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4883 /* IDB_OBM1_48_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4884 /* IDB_OBM1_48_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4885 /* IDB_OBM1_48_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4886 /* IDB_OBM1_48_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4887 /* IDB_OBM1_48_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4888 /* IDB_OBM1_48_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4889 /* IDB_OBM1_48_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4890 /* IDB_OBM1_48_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4891 /* IDB_OBM1_48_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4892 /* IDB_OBM1_48_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4893 /* IDB_OBM1_48_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4894 /* IDB_OBM1_48_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4895 /* IDB_OBM1_48_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4896 /* IDB_OBM1_48_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 4897 /* IDB_OBM1_48_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 4898 /* IDB_OBM1_48_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 4899 /* IDB_OBM1_48_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 4900 /* IDB_OBM1_48_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 4901 /* IDB_OBM1_48_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 4902 /* IDB_OBM1_48_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 4903 /* IDB_OBM1_48_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 4904 /* IDB_OBM1_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 4905 /* IDB_OBM1_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 4906 /* IDB_OBM1_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 4907 /* IDB_OBM1_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 4908 /* IDB_OBM1_DSCP_MAP_PORT4 */ "Priority table based on DSCP.", 4909 /* IDB_OBM1_DSCP_MAP_PORT5 */ "Priority table based on DSCP.", 4910 /* IDB_OBM1_DSCP_MAP_PORT6 */ "Priority table based on DSCP.", 4911 /* IDB_OBM1_DSCP_MAP_PORT7 */ "Priority table based on DSCP.", 4912 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 4913 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 4914 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 4915 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 4916 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE4 */ "Priority table based on DSCP.", 4917 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE5 */ "Priority table based on DSCP.", 4918 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE6 */ "Priority table based on DSCP.", 4919 /* IDB_OBM1_DSCP_MAP_PORT0_PIPE7 */ "Priority table based on DSCP.", 4920 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 4921 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 4922 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 4923 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 4924 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE4 */ "Priority table based on DSCP.", 4925 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE5 */ "Priority table based on DSCP.", 4926 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE6 */ "Priority table based on DSCP.", 4927 /* IDB_OBM1_DSCP_MAP_PORT1_PIPE7 */ "Priority table based on DSCP.", 4928 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 4929 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 4930 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 4931 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 4932 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE4 */ "Priority table based on DSCP.", 4933 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE5 */ "Priority table based on DSCP.", 4934 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE6 */ "Priority table based on DSCP.", 4935 /* IDB_OBM1_DSCP_MAP_PORT2_PIPE7 */ "Priority table based on DSCP.", 4936 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 4937 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 4938 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 4939 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 4940 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE4 */ "Priority table based on DSCP.", 4941 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE5 */ "Priority table based on DSCP.", 4942 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE6 */ "Priority table based on DSCP.", 4943 /* IDB_OBM1_DSCP_MAP_PORT3_PIPE7 */ "Priority table based on DSCP.", 4944 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE0 */ "Priority table based on DSCP.", 4945 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE1 */ "Priority table based on DSCP.", 4946 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE2 */ "Priority table based on DSCP.", 4947 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE3 */ "Priority table based on DSCP.", 4948 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE4 */ "Priority table based on DSCP.", 4949 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE5 */ "Priority table based on DSCP.", 4950 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE6 */ "Priority table based on DSCP.", 4951 /* IDB_OBM1_DSCP_MAP_PORT4_PIPE7 */ "Priority table based on DSCP.", 4952 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE0 */ "Priority table based on DSCP.", 4953 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE1 */ "Priority table based on DSCP.", 4954 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE2 */ "Priority table based on DSCP.", 4955 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE3 */ "Priority table based on DSCP.", 4956 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE4 */ "Priority table based on DSCP.", 4957 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE5 */ "Priority table based on DSCP.", 4958 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE6 */ "Priority table based on DSCP.", 4959 /* IDB_OBM1_DSCP_MAP_PORT5_PIPE7 */ "Priority table based on DSCP.", 4960 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE0 */ "Priority table based on DSCP.", 4961 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE1 */ "Priority table based on DSCP.", 4962 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE2 */ "Priority table based on DSCP.", 4963 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE3 */ "Priority table based on DSCP.", 4964 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE4 */ "Priority table based on DSCP.", 4965 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE5 */ "Priority table based on DSCP.", 4966 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE6 */ "Priority table based on DSCP.", 4967 /* IDB_OBM1_DSCP_MAP_PORT6_PIPE7 */ "Priority table based on DSCP.", 4968 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE0 */ "Priority table based on DSCP.", 4969 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE1 */ "Priority table based on DSCP.", 4970 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE2 */ "Priority table based on DSCP.", 4971 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE3 */ "Priority table based on DSCP.", 4972 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE4 */ "Priority table based on DSCP.", 4973 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE5 */ "Priority table based on DSCP.", 4974 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE6 */ "Priority table based on DSCP.", 4975 /* IDB_OBM1_DSCP_MAP_PORT7_PIPE7 */ "Priority table based on DSCP.", 4976 /* IDB_OBM1_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 4977 /* IDB_OBM1_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 4978 /* IDB_OBM1_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 4979 /* IDB_OBM1_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 4980 /* IDB_OBM1_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 4981 /* IDB_OBM1_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 4982 /* IDB_OBM1_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 4983 /* IDB_OBM1_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 4984 /* IDB_OBM1_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 4985 /* IDB_OBM1_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 4986 /* IDB_OBM1_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 4987 /* IDB_OBM1_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 4988 /* IDB_OBM1_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 4989 /* IDB_OBM1_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 4990 /* IDB_OBM1_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 4991 /* IDB_OBM1_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 4992 /* IDB_OBM1_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 4993 /* IDB_OBM1_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 4994 /* IDB_OBM1_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 4995 /* IDB_OBM1_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 4996 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4997 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE0 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4998 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE1 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 4999 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE2 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5000 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE3 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5001 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE4 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5002 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE5 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5003 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE6 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5004 /* IDB_OBM1_IOM_STATS_WINDOW_RESULTS_PIPE7 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5005 /* IDB_OBM1_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 5006 /* IDB_OBM1_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 5007 /* IDB_OBM1_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 5008 /* IDB_OBM1_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 5009 /* IDB_OBM1_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5010 /* IDB_OBM1_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5011 /* IDB_OBM1_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5012 /* IDB_OBM1_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5013 /* IDB_OBM1_PRI_MAP_PORT4 */ "Priority table based on PCP", 5014 /* IDB_OBM1_PRI_MAP_PORT5 */ "Priority table based on PCP", 5015 /* IDB_OBM1_PRI_MAP_PORT6 */ "Priority table based on PCP", 5016 /* IDB_OBM1_PRI_MAP_PORT7 */ "Priority table based on PCP", 5017 /* IDB_OBM1_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5018 /* IDB_OBM1_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5019 /* IDB_OBM1_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5020 /* IDB_OBM1_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5021 /* IDB_OBM1_PRI_MAP_PORT0_PIPE4 */ "Priority table based on PCP.", 5022 /* IDB_OBM1_PRI_MAP_PORT0_PIPE5 */ "Priority table based on PCP.", 5023 /* IDB_OBM1_PRI_MAP_PORT0_PIPE6 */ "Priority table based on PCP.", 5024 /* IDB_OBM1_PRI_MAP_PORT0_PIPE7 */ "Priority table based on PCP.", 5025 /* IDB_OBM1_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5026 /* IDB_OBM1_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5027 /* IDB_OBM1_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5028 /* IDB_OBM1_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5029 /* IDB_OBM1_PRI_MAP_PORT1_PIPE4 */ "Priority table based on PCP", 5030 /* IDB_OBM1_PRI_MAP_PORT1_PIPE5 */ "Priority table based on PCP", 5031 /* IDB_OBM1_PRI_MAP_PORT1_PIPE6 */ "Priority table based on PCP", 5032 /* IDB_OBM1_PRI_MAP_PORT1_PIPE7 */ "Priority table based on PCP", 5033 /* IDB_OBM1_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5034 /* IDB_OBM1_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5035 /* IDB_OBM1_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5036 /* IDB_OBM1_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5037 /* IDB_OBM1_PRI_MAP_PORT2_PIPE4 */ "Priority table based on PCP", 5038 /* IDB_OBM1_PRI_MAP_PORT2_PIPE5 */ "Priority table based on PCP", 5039 /* IDB_OBM1_PRI_MAP_PORT2_PIPE6 */ "Priority table based on PCP", 5040 /* IDB_OBM1_PRI_MAP_PORT2_PIPE7 */ "Priority table based on PCP", 5041 /* IDB_OBM1_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5042 /* IDB_OBM1_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5043 /* IDB_OBM1_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5044 /* IDB_OBM1_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5045 /* IDB_OBM1_PRI_MAP_PORT3_PIPE4 */ "Priority table based on PCP", 5046 /* IDB_OBM1_PRI_MAP_PORT3_PIPE5 */ "Priority table based on PCP", 5047 /* IDB_OBM1_PRI_MAP_PORT3_PIPE6 */ "Priority table based on PCP", 5048 /* IDB_OBM1_PRI_MAP_PORT3_PIPE7 */ "Priority table based on PCP", 5049 /* IDB_OBM1_PRI_MAP_PORT4_PIPE0 */ "Priority table based on PCP", 5050 /* IDB_OBM1_PRI_MAP_PORT4_PIPE1 */ "Priority table based on PCP", 5051 /* IDB_OBM1_PRI_MAP_PORT4_PIPE2 */ "Priority table based on PCP", 5052 /* IDB_OBM1_PRI_MAP_PORT4_PIPE3 */ "Priority table based on PCP", 5053 /* IDB_OBM1_PRI_MAP_PORT4_PIPE4 */ "Priority table based on PCP", 5054 /* IDB_OBM1_PRI_MAP_PORT4_PIPE5 */ "Priority table based on PCP", 5055 /* IDB_OBM1_PRI_MAP_PORT4_PIPE6 */ "Priority table based on PCP", 5056 /* IDB_OBM1_PRI_MAP_PORT4_PIPE7 */ "Priority table based on PCP", 5057 /* IDB_OBM1_PRI_MAP_PORT5_PIPE0 */ "Priority table based on PCP", 5058 /* IDB_OBM1_PRI_MAP_PORT5_PIPE1 */ "Priority table based on PCP", 5059 /* IDB_OBM1_PRI_MAP_PORT5_PIPE2 */ "Priority table based on PCP", 5060 /* IDB_OBM1_PRI_MAP_PORT5_PIPE3 */ "Priority table based on PCP", 5061 /* IDB_OBM1_PRI_MAP_PORT5_PIPE4 */ "Priority table based on PCP", 5062 /* IDB_OBM1_PRI_MAP_PORT5_PIPE5 */ "Priority table based on PCP", 5063 /* IDB_OBM1_PRI_MAP_PORT5_PIPE6 */ "Priority table based on PCP", 5064 /* IDB_OBM1_PRI_MAP_PORT5_PIPE7 */ "Priority table based on PCP", 5065 /* IDB_OBM1_PRI_MAP_PORT6_PIPE0 */ "Priority table based on PCP", 5066 /* IDB_OBM1_PRI_MAP_PORT6_PIPE1 */ "Priority table based on PCP", 5067 /* IDB_OBM1_PRI_MAP_PORT6_PIPE2 */ "Priority table based on PCP", 5068 /* IDB_OBM1_PRI_MAP_PORT6_PIPE3 */ "Priority table based on PCP", 5069 /* IDB_OBM1_PRI_MAP_PORT6_PIPE4 */ "Priority table based on PCP", 5070 /* IDB_OBM1_PRI_MAP_PORT6_PIPE5 */ "Priority table based on PCP", 5071 /* IDB_OBM1_PRI_MAP_PORT6_PIPE6 */ "Priority table based on PCP", 5072 /* IDB_OBM1_PRI_MAP_PORT6_PIPE7 */ "Priority table based on PCP", 5073 /* IDB_OBM1_PRI_MAP_PORT7_PIPE0 */ "Priority table based on PCP", 5074 /* IDB_OBM1_PRI_MAP_PORT7_PIPE1 */ "Priority table based on PCP", 5075 /* IDB_OBM1_PRI_MAP_PORT7_PIPE2 */ "Priority table based on PCP", 5076 /* IDB_OBM1_PRI_MAP_PORT7_PIPE3 */ "Priority table based on PCP", 5077 /* IDB_OBM1_PRI_MAP_PORT7_PIPE4 */ "Priority table based on PCP", 5078 /* IDB_OBM1_PRI_MAP_PORT7_PIPE5 */ "Priority table based on PCP", 5079 /* IDB_OBM1_PRI_MAP_PORT7_PIPE6 */ "Priority table based on PCP", 5080 /* IDB_OBM1_PRI_MAP_PORT7_PIPE7 */ "Priority table based on PCP", 5081 /* IDB_OBM1_Q_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5082 /* IDB_OBM1_Q_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5083 /* IDB_OBM1_Q_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5084 /* IDB_OBM1_Q_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5085 /* IDB_OBM1_Q_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5086 /* IDB_OBM1_Q_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5087 /* IDB_OBM1_Q_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5088 /* IDB_OBM1_Q_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5089 /* IDB_OBM1_Q_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5090 /* IDB_OBM1_Q_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5091 /* IDB_OBM1_Q_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5092 /* IDB_OBM1_Q_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5093 /* IDB_OBM1_Q_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5094 /* IDB_OBM1_Q_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5095 /* IDB_OBM1_Q_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5096 /* IDB_OBM1_Q_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5097 /* IDB_OBM1_Q_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5098 /* IDB_OBM1_Q_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5099 /* IDB_OBM1_Q_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5100 /* IDB_OBM1_Q_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5101 /* IDB_OBM1_Q_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5102 /* IDB_OBM1_Q_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5103 /* IDB_OBM1_Q_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5104 /* IDB_OBM1_Q_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5105 /* IDB_OBM2_48_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5106 /* IDB_OBM2_48_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5107 /* IDB_OBM2_48_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5108 /* IDB_OBM2_48_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5109 /* IDB_OBM2_48_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5110 /* IDB_OBM2_48_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5111 /* IDB_OBM2_48_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5112 /* IDB_OBM2_48_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5113 /* IDB_OBM2_48_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5114 /* IDB_OBM2_48_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5115 /* IDB_OBM2_48_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5116 /* IDB_OBM2_48_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5117 /* IDB_OBM2_48_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5118 /* IDB_OBM2_48_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5119 /* IDB_OBM2_48_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5120 /* IDB_OBM2_48_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5121 /* IDB_OBM2_48_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5122 /* IDB_OBM2_48_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5123 /* IDB_OBM2_48_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5124 /* IDB_OBM2_48_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5125 /* IDB_OBM2_48_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5126 /* IDB_OBM2_48_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5127 /* IDB_OBM2_48_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5128 /* IDB_OBM2_48_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5129 /* IDB_OBM2_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5130 /* IDB_OBM2_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5131 /* IDB_OBM2_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5132 /* IDB_OBM2_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5133 /* IDB_OBM2_DSCP_MAP_PORT4 */ "Priority table based on DSCP.", 5134 /* IDB_OBM2_DSCP_MAP_PORT5 */ "Priority table based on DSCP.", 5135 /* IDB_OBM2_DSCP_MAP_PORT6 */ "Priority table based on DSCP.", 5136 /* IDB_OBM2_DSCP_MAP_PORT7 */ "Priority table based on DSCP.", 5137 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5138 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5139 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5140 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5141 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE4 */ "Priority table based on DSCP.", 5142 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE5 */ "Priority table based on DSCP.", 5143 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE6 */ "Priority table based on DSCP.", 5144 /* IDB_OBM2_DSCP_MAP_PORT0_PIPE7 */ "Priority table based on DSCP.", 5145 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5146 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5147 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5148 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5149 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE4 */ "Priority table based on DSCP.", 5150 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE5 */ "Priority table based on DSCP.", 5151 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE6 */ "Priority table based on DSCP.", 5152 /* IDB_OBM2_DSCP_MAP_PORT1_PIPE7 */ "Priority table based on DSCP.", 5153 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5154 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5155 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5156 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5157 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE4 */ "Priority table based on DSCP.", 5158 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE5 */ "Priority table based on DSCP.", 5159 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE6 */ "Priority table based on DSCP.", 5160 /* IDB_OBM2_DSCP_MAP_PORT2_PIPE7 */ "Priority table based on DSCP.", 5161 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5162 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5163 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5164 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5165 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE4 */ "Priority table based on DSCP.", 5166 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE5 */ "Priority table based on DSCP.", 5167 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE6 */ "Priority table based on DSCP.", 5168 /* IDB_OBM2_DSCP_MAP_PORT3_PIPE7 */ "Priority table based on DSCP.", 5169 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE0 */ "Priority table based on DSCP.", 5170 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE1 */ "Priority table based on DSCP.", 5171 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE2 */ "Priority table based on DSCP.", 5172 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE3 */ "Priority table based on DSCP.", 5173 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE4 */ "Priority table based on DSCP.", 5174 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE5 */ "Priority table based on DSCP.", 5175 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE6 */ "Priority table based on DSCP.", 5176 /* IDB_OBM2_DSCP_MAP_PORT4_PIPE7 */ "Priority table based on DSCP.", 5177 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE0 */ "Priority table based on DSCP.", 5178 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE1 */ "Priority table based on DSCP.", 5179 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE2 */ "Priority table based on DSCP.", 5180 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE3 */ "Priority table based on DSCP.", 5181 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE4 */ "Priority table based on DSCP.", 5182 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE5 */ "Priority table based on DSCP.", 5183 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE6 */ "Priority table based on DSCP.", 5184 /* IDB_OBM2_DSCP_MAP_PORT5_PIPE7 */ "Priority table based on DSCP.", 5185 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE0 */ "Priority table based on DSCP.", 5186 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE1 */ "Priority table based on DSCP.", 5187 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE2 */ "Priority table based on DSCP.", 5188 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE3 */ "Priority table based on DSCP.", 5189 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE4 */ "Priority table based on DSCP.", 5190 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE5 */ "Priority table based on DSCP.", 5191 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE6 */ "Priority table based on DSCP.", 5192 /* IDB_OBM2_DSCP_MAP_PORT6_PIPE7 */ "Priority table based on DSCP.", 5193 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE0 */ "Priority table based on DSCP.", 5194 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE1 */ "Priority table based on DSCP.", 5195 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE2 */ "Priority table based on DSCP.", 5196 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE3 */ "Priority table based on DSCP.", 5197 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE4 */ "Priority table based on DSCP.", 5198 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE5 */ "Priority table based on DSCP.", 5199 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE6 */ "Priority table based on DSCP.", 5200 /* IDB_OBM2_DSCP_MAP_PORT7_PIPE7 */ "Priority table based on DSCP.", 5201 /* IDB_OBM2_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5202 /* IDB_OBM2_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5203 /* IDB_OBM2_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5204 /* IDB_OBM2_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5205 /* IDB_OBM2_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5206 /* IDB_OBM2_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5207 /* IDB_OBM2_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5208 /* IDB_OBM2_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5209 /* IDB_OBM2_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5210 /* IDB_OBM2_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5211 /* IDB_OBM2_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5212 /* IDB_OBM2_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5213 /* IDB_OBM2_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5214 /* IDB_OBM2_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5215 /* IDB_OBM2_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5216 /* IDB_OBM2_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5217 /* IDB_OBM2_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5218 /* IDB_OBM2_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5219 /* IDB_OBM2_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5220 /* IDB_OBM2_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5221 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5222 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE0 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5223 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE1 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5224 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE2 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5225 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE3 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5226 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE4 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5227 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE5 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5228 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE6 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5229 /* IDB_OBM2_IOM_STATS_WINDOW_RESULTS_PIPE7 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5230 /* IDB_OBM2_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 5231 /* IDB_OBM2_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 5232 /* IDB_OBM2_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 5233 /* IDB_OBM2_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 5234 /* IDB_OBM2_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5235 /* IDB_OBM2_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5236 /* IDB_OBM2_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5237 /* IDB_OBM2_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5238 /* IDB_OBM2_PRI_MAP_PORT4 */ "Priority table based on PCP", 5239 /* IDB_OBM2_PRI_MAP_PORT5 */ "Priority table based on PCP", 5240 /* IDB_OBM2_PRI_MAP_PORT6 */ "Priority table based on PCP", 5241 /* IDB_OBM2_PRI_MAP_PORT7 */ "Priority table based on PCP", 5242 /* IDB_OBM2_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5243 /* IDB_OBM2_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5244 /* IDB_OBM2_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5245 /* IDB_OBM2_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5246 /* IDB_OBM2_PRI_MAP_PORT0_PIPE4 */ "Priority table based on PCP.", 5247 /* IDB_OBM2_PRI_MAP_PORT0_PIPE5 */ "Priority table based on PCP.", 5248 /* IDB_OBM2_PRI_MAP_PORT0_PIPE6 */ "Priority table based on PCP.", 5249 /* IDB_OBM2_PRI_MAP_PORT0_PIPE7 */ "Priority table based on PCP.", 5250 /* IDB_OBM2_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5251 /* IDB_OBM2_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5252 /* IDB_OBM2_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5253 /* IDB_OBM2_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5254 /* IDB_OBM2_PRI_MAP_PORT1_PIPE4 */ "Priority table based on PCP", 5255 /* IDB_OBM2_PRI_MAP_PORT1_PIPE5 */ "Priority table based on PCP", 5256 /* IDB_OBM2_PRI_MAP_PORT1_PIPE6 */ "Priority table based on PCP", 5257 /* IDB_OBM2_PRI_MAP_PORT1_PIPE7 */ "Priority table based on PCP", 5258 /* IDB_OBM2_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5259 /* IDB_OBM2_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5260 /* IDB_OBM2_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5261 /* IDB_OBM2_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5262 /* IDB_OBM2_PRI_MAP_PORT2_PIPE4 */ "Priority table based on PCP", 5263 /* IDB_OBM2_PRI_MAP_PORT2_PIPE5 */ "Priority table based on PCP", 5264 /* IDB_OBM2_PRI_MAP_PORT2_PIPE6 */ "Priority table based on PCP", 5265 /* IDB_OBM2_PRI_MAP_PORT2_PIPE7 */ "Priority table based on PCP", 5266 /* IDB_OBM2_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5267 /* IDB_OBM2_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5268 /* IDB_OBM2_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5269 /* IDB_OBM2_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5270 /* IDB_OBM2_PRI_MAP_PORT3_PIPE4 */ "Priority table based on PCP", 5271 /* IDB_OBM2_PRI_MAP_PORT3_PIPE5 */ "Priority table based on PCP", 5272 /* IDB_OBM2_PRI_MAP_PORT3_PIPE6 */ "Priority table based on PCP", 5273 /* IDB_OBM2_PRI_MAP_PORT3_PIPE7 */ "Priority table based on PCP", 5274 /* IDB_OBM2_PRI_MAP_PORT4_PIPE0 */ "Priority table based on PCP", 5275 /* IDB_OBM2_PRI_MAP_PORT4_PIPE1 */ "Priority table based on PCP", 5276 /* IDB_OBM2_PRI_MAP_PORT4_PIPE2 */ "Priority table based on PCP", 5277 /* IDB_OBM2_PRI_MAP_PORT4_PIPE3 */ "Priority table based on PCP", 5278 /* IDB_OBM2_PRI_MAP_PORT4_PIPE4 */ "Priority table based on PCP", 5279 /* IDB_OBM2_PRI_MAP_PORT4_PIPE5 */ "Priority table based on PCP", 5280 /* IDB_OBM2_PRI_MAP_PORT4_PIPE6 */ "Priority table based on PCP", 5281 /* IDB_OBM2_PRI_MAP_PORT4_PIPE7 */ "Priority table based on PCP", 5282 /* IDB_OBM2_PRI_MAP_PORT5_PIPE0 */ "Priority table based on PCP", 5283 /* IDB_OBM2_PRI_MAP_PORT5_PIPE1 */ "Priority table based on PCP", 5284 /* IDB_OBM2_PRI_MAP_PORT5_PIPE2 */ "Priority table based on PCP", 5285 /* IDB_OBM2_PRI_MAP_PORT5_PIPE3 */ "Priority table based on PCP", 5286 /* IDB_OBM2_PRI_MAP_PORT5_PIPE4 */ "Priority table based on PCP", 5287 /* IDB_OBM2_PRI_MAP_PORT5_PIPE5 */ "Priority table based on PCP", 5288 /* IDB_OBM2_PRI_MAP_PORT5_PIPE6 */ "Priority table based on PCP", 5289 /* IDB_OBM2_PRI_MAP_PORT5_PIPE7 */ "Priority table based on PCP", 5290 /* IDB_OBM2_PRI_MAP_PORT6_PIPE0 */ "Priority table based on PCP", 5291 /* IDB_OBM2_PRI_MAP_PORT6_PIPE1 */ "Priority table based on PCP", 5292 /* IDB_OBM2_PRI_MAP_PORT6_PIPE2 */ "Priority table based on PCP", 5293 /* IDB_OBM2_PRI_MAP_PORT6_PIPE3 */ "Priority table based on PCP", 5294 /* IDB_OBM2_PRI_MAP_PORT6_PIPE4 */ "Priority table based on PCP", 5295 /* IDB_OBM2_PRI_MAP_PORT6_PIPE5 */ "Priority table based on PCP", 5296 /* IDB_OBM2_PRI_MAP_PORT6_PIPE6 */ "Priority table based on PCP", 5297 /* IDB_OBM2_PRI_MAP_PORT6_PIPE7 */ "Priority table based on PCP", 5298 /* IDB_OBM2_PRI_MAP_PORT7_PIPE0 */ "Priority table based on PCP", 5299 /* IDB_OBM2_PRI_MAP_PORT7_PIPE1 */ "Priority table based on PCP", 5300 /* IDB_OBM2_PRI_MAP_PORT7_PIPE2 */ "Priority table based on PCP", 5301 /* IDB_OBM2_PRI_MAP_PORT7_PIPE3 */ "Priority table based on PCP", 5302 /* IDB_OBM2_PRI_MAP_PORT7_PIPE4 */ "Priority table based on PCP", 5303 /* IDB_OBM2_PRI_MAP_PORT7_PIPE5 */ "Priority table based on PCP", 5304 /* IDB_OBM2_PRI_MAP_PORT7_PIPE6 */ "Priority table based on PCP", 5305 /* IDB_OBM2_PRI_MAP_PORT7_PIPE7 */ "Priority table based on PCP", 5306 /* IDB_OBM2_Q_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5307 /* IDB_OBM2_Q_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5308 /* IDB_OBM2_Q_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5309 /* IDB_OBM2_Q_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5310 /* IDB_OBM2_Q_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5311 /* IDB_OBM2_Q_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5312 /* IDB_OBM2_Q_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5313 /* IDB_OBM2_Q_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5314 /* IDB_OBM2_Q_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5315 /* IDB_OBM2_Q_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5316 /* IDB_OBM2_Q_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5317 /* IDB_OBM2_Q_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5318 /* IDB_OBM2_Q_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5319 /* IDB_OBM2_Q_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5320 /* IDB_OBM2_Q_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5321 /* IDB_OBM2_Q_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5322 /* IDB_OBM2_Q_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5323 /* IDB_OBM2_Q_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5324 /* IDB_OBM2_Q_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5325 /* IDB_OBM2_Q_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5326 /* IDB_OBM2_Q_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5327 /* IDB_OBM2_Q_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5328 /* IDB_OBM2_Q_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5329 /* IDB_OBM2_Q_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5330 /* IDB_OBM3_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5331 /* IDB_OBM3_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5332 /* IDB_OBM3_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5333 /* IDB_OBM3_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5334 /* IDB_OBM3_DSCP_MAP_PORT4 */ "Priority table based on DSCP.", 5335 /* IDB_OBM3_DSCP_MAP_PORT5 */ "Priority table based on DSCP.", 5336 /* IDB_OBM3_DSCP_MAP_PORT6 */ "Priority table based on DSCP.", 5337 /* IDB_OBM3_DSCP_MAP_PORT7 */ "Priority table based on DSCP.", 5338 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5339 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5340 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5341 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5342 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE4 */ "Priority table based on DSCP.", 5343 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE5 */ "Priority table based on DSCP.", 5344 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE6 */ "Priority table based on DSCP.", 5345 /* IDB_OBM3_DSCP_MAP_PORT0_PIPE7 */ "Priority table based on DSCP.", 5346 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5347 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5348 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5349 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5350 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE4 */ "Priority table based on DSCP.", 5351 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE5 */ "Priority table based on DSCP.", 5352 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE6 */ "Priority table based on DSCP.", 5353 /* IDB_OBM3_DSCP_MAP_PORT1_PIPE7 */ "Priority table based on DSCP.", 5354 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5355 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5356 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5357 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5358 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE4 */ "Priority table based on DSCP.", 5359 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE5 */ "Priority table based on DSCP.", 5360 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE6 */ "Priority table based on DSCP.", 5361 /* IDB_OBM3_DSCP_MAP_PORT2_PIPE7 */ "Priority table based on DSCP.", 5362 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5363 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5364 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5365 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5366 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE4 */ "Priority table based on DSCP.", 5367 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE5 */ "Priority table based on DSCP.", 5368 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE6 */ "Priority table based on DSCP.", 5369 /* IDB_OBM3_DSCP_MAP_PORT3_PIPE7 */ "Priority table based on DSCP.", 5370 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE0 */ "Priority table based on DSCP.", 5371 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE1 */ "Priority table based on DSCP.", 5372 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE2 */ "Priority table based on DSCP.", 5373 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE3 */ "Priority table based on DSCP.", 5374 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE4 */ "Priority table based on DSCP.", 5375 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE5 */ "Priority table based on DSCP.", 5376 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE6 */ "Priority table based on DSCP.", 5377 /* IDB_OBM3_DSCP_MAP_PORT4_PIPE7 */ "Priority table based on DSCP.", 5378 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE0 */ "Priority table based on DSCP.", 5379 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE1 */ "Priority table based on DSCP.", 5380 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE2 */ "Priority table based on DSCP.", 5381 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE3 */ "Priority table based on DSCP.", 5382 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE4 */ "Priority table based on DSCP.", 5383 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE5 */ "Priority table based on DSCP.", 5384 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE6 */ "Priority table based on DSCP.", 5385 /* IDB_OBM3_DSCP_MAP_PORT5_PIPE7 */ "Priority table based on DSCP.", 5386 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE0 */ "Priority table based on DSCP.", 5387 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE1 */ "Priority table based on DSCP.", 5388 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE2 */ "Priority table based on DSCP.", 5389 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE3 */ "Priority table based on DSCP.", 5390 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE4 */ "Priority table based on DSCP.", 5391 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE5 */ "Priority table based on DSCP.", 5392 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE6 */ "Priority table based on DSCP.", 5393 /* IDB_OBM3_DSCP_MAP_PORT6_PIPE7 */ "Priority table based on DSCP.", 5394 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE0 */ "Priority table based on DSCP.", 5395 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE1 */ "Priority table based on DSCP.", 5396 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE2 */ "Priority table based on DSCP.", 5397 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE3 */ "Priority table based on DSCP.", 5398 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE4 */ "Priority table based on DSCP.", 5399 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE5 */ "Priority table based on DSCP.", 5400 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE6 */ "Priority table based on DSCP.", 5401 /* IDB_OBM3_DSCP_MAP_PORT7_PIPE7 */ "Priority table based on DSCP.", 5402 /* IDB_OBM3_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5403 /* IDB_OBM3_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5404 /* IDB_OBM3_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5405 /* IDB_OBM3_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5406 /* IDB_OBM3_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5407 /* IDB_OBM3_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5408 /* IDB_OBM3_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5409 /* IDB_OBM3_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5410 /* IDB_OBM3_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5411 /* IDB_OBM3_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5412 /* IDB_OBM3_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5413 /* IDB_OBM3_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5414 /* IDB_OBM3_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5415 /* IDB_OBM3_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5416 /* IDB_OBM3_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5417 /* IDB_OBM3_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5418 /* IDB_OBM3_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5419 /* IDB_OBM3_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5420 /* IDB_OBM3_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5421 /* IDB_OBM3_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5422 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5423 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE0 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5424 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE1 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5425 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE2 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5426 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE3 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5427 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE4 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5428 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE5 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5429 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE6 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5430 /* IDB_OBM3_IOM_STATS_WINDOW_RESULTS_PIPE7 */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.\nEntry 64 to 79: Port 4 results epoch 0 to 15.\nEntry 80 to 95: Port 5 results epoch 0 to 15.\nEntry 96 to 111: Port 6 results epoch 0 to 15.\nEntry 112 to 127: Port 7 results epoch 0 to 15.", 5431 /* IDB_OBM3_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 5432 /* IDB_OBM3_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 5433 /* IDB_OBM3_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 5434 /* IDB_OBM3_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 5435 /* IDB_OBM3_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5436 /* IDB_OBM3_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5437 /* IDB_OBM3_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5438 /* IDB_OBM3_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5439 /* IDB_OBM3_PRI_MAP_PORT4 */ "Priority table based on PCP", 5440 /* IDB_OBM3_PRI_MAP_PORT5 */ "Priority table based on PCP", 5441 /* IDB_OBM3_PRI_MAP_PORT6 */ "Priority table based on PCP", 5442 /* IDB_OBM3_PRI_MAP_PORT7 */ "Priority table based on PCP", 5443 /* IDB_OBM3_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5444 /* IDB_OBM3_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5445 /* IDB_OBM3_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5446 /* IDB_OBM3_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5447 /* IDB_OBM3_PRI_MAP_PORT0_PIPE4 */ "Priority table based on PCP.", 5448 /* IDB_OBM3_PRI_MAP_PORT0_PIPE5 */ "Priority table based on PCP.", 5449 /* IDB_OBM3_PRI_MAP_PORT0_PIPE6 */ "Priority table based on PCP.", 5450 /* IDB_OBM3_PRI_MAP_PORT0_PIPE7 */ "Priority table based on PCP.", 5451 /* IDB_OBM3_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5452 /* IDB_OBM3_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5453 /* IDB_OBM3_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5454 /* IDB_OBM3_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5455 /* IDB_OBM3_PRI_MAP_PORT1_PIPE4 */ "Priority table based on PCP", 5456 /* IDB_OBM3_PRI_MAP_PORT1_PIPE5 */ "Priority table based on PCP", 5457 /* IDB_OBM3_PRI_MAP_PORT1_PIPE6 */ "Priority table based on PCP", 5458 /* IDB_OBM3_PRI_MAP_PORT1_PIPE7 */ "Priority table based on PCP", 5459 /* IDB_OBM3_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5460 /* IDB_OBM3_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5461 /* IDB_OBM3_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5462 /* IDB_OBM3_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5463 /* IDB_OBM3_PRI_MAP_PORT2_PIPE4 */ "Priority table based on PCP", 5464 /* IDB_OBM3_PRI_MAP_PORT2_PIPE5 */ "Priority table based on PCP", 5465 /* IDB_OBM3_PRI_MAP_PORT2_PIPE6 */ "Priority table based on PCP", 5466 /* IDB_OBM3_PRI_MAP_PORT2_PIPE7 */ "Priority table based on PCP", 5467 /* IDB_OBM3_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5468 /* IDB_OBM3_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5469 /* IDB_OBM3_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5470 /* IDB_OBM3_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5471 /* IDB_OBM3_PRI_MAP_PORT3_PIPE4 */ "Priority table based on PCP", 5472 /* IDB_OBM3_PRI_MAP_PORT3_PIPE5 */ "Priority table based on PCP", 5473 /* IDB_OBM3_PRI_MAP_PORT3_PIPE6 */ "Priority table based on PCP", 5474 /* IDB_OBM3_PRI_MAP_PORT3_PIPE7 */ "Priority table based on PCP", 5475 /* IDB_OBM3_PRI_MAP_PORT4_PIPE0 */ "Priority table based on PCP", 5476 /* IDB_OBM3_PRI_MAP_PORT4_PIPE1 */ "Priority table based on PCP", 5477 /* IDB_OBM3_PRI_MAP_PORT4_PIPE2 */ "Priority table based on PCP", 5478 /* IDB_OBM3_PRI_MAP_PORT4_PIPE3 */ "Priority table based on PCP", 5479 /* IDB_OBM3_PRI_MAP_PORT4_PIPE4 */ "Priority table based on PCP", 5480 /* IDB_OBM3_PRI_MAP_PORT4_PIPE5 */ "Priority table based on PCP", 5481 /* IDB_OBM3_PRI_MAP_PORT4_PIPE6 */ "Priority table based on PCP", 5482 /* IDB_OBM3_PRI_MAP_PORT4_PIPE7 */ "Priority table based on PCP", 5483 /* IDB_OBM3_PRI_MAP_PORT5_PIPE0 */ "Priority table based on PCP", 5484 /* IDB_OBM3_PRI_MAP_PORT5_PIPE1 */ "Priority table based on PCP", 5485 /* IDB_OBM3_PRI_MAP_PORT5_PIPE2 */ "Priority table based on PCP", 5486 /* IDB_OBM3_PRI_MAP_PORT5_PIPE3 */ "Priority table based on PCP", 5487 /* IDB_OBM3_PRI_MAP_PORT5_PIPE4 */ "Priority table based on PCP", 5488 /* IDB_OBM3_PRI_MAP_PORT5_PIPE5 */ "Priority table based on PCP", 5489 /* IDB_OBM3_PRI_MAP_PORT5_PIPE6 */ "Priority table based on PCP", 5490 /* IDB_OBM3_PRI_MAP_PORT5_PIPE7 */ "Priority table based on PCP", 5491 /* IDB_OBM3_PRI_MAP_PORT6_PIPE0 */ "Priority table based on PCP", 5492 /* IDB_OBM3_PRI_MAP_PORT6_PIPE1 */ "Priority table based on PCP", 5493 /* IDB_OBM3_PRI_MAP_PORT6_PIPE2 */ "Priority table based on PCP", 5494 /* IDB_OBM3_PRI_MAP_PORT6_PIPE3 */ "Priority table based on PCP", 5495 /* IDB_OBM3_PRI_MAP_PORT6_PIPE4 */ "Priority table based on PCP", 5496 /* IDB_OBM3_PRI_MAP_PORT6_PIPE5 */ "Priority table based on PCP", 5497 /* IDB_OBM3_PRI_MAP_PORT6_PIPE6 */ "Priority table based on PCP", 5498 /* IDB_OBM3_PRI_MAP_PORT6_PIPE7 */ "Priority table based on PCP", 5499 /* IDB_OBM3_PRI_MAP_PORT7_PIPE0 */ "Priority table based on PCP", 5500 /* IDB_OBM3_PRI_MAP_PORT7_PIPE1 */ "Priority table based on PCP", 5501 /* IDB_OBM3_PRI_MAP_PORT7_PIPE2 */ "Priority table based on PCP", 5502 /* IDB_OBM3_PRI_MAP_PORT7_PIPE3 */ "Priority table based on PCP", 5503 /* IDB_OBM3_PRI_MAP_PORT7_PIPE4 */ "Priority table based on PCP", 5504 /* IDB_OBM3_PRI_MAP_PORT7_PIPE5 */ "Priority table based on PCP", 5505 /* IDB_OBM3_PRI_MAP_PORT7_PIPE6 */ "Priority table based on PCP", 5506 /* IDB_OBM3_PRI_MAP_PORT7_PIPE7 */ "Priority table based on PCP", 5507 /* IDB_OBM4_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5508 /* IDB_OBM4_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5509 /* IDB_OBM4_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5510 /* IDB_OBM4_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5511 /* IDB_OBM4_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5512 /* IDB_OBM4_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5513 /* IDB_OBM4_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5514 /* IDB_OBM4_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5515 /* IDB_OBM4_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5516 /* IDB_OBM4_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5517 /* IDB_OBM4_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5518 /* IDB_OBM4_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5519 /* IDB_OBM4_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5520 /* IDB_OBM4_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5521 /* IDB_OBM4_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5522 /* IDB_OBM4_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5523 /* IDB_OBM4_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5524 /* IDB_OBM4_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5525 /* IDB_OBM4_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5526 /* IDB_OBM4_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5527 /* IDB_OBM4_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5528 /* IDB_OBM4_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5529 /* IDB_OBM4_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5530 /* IDB_OBM4_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5531 /* IDB_OBM4_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5532 /* IDB_OBM4_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5533 /* IDB_OBM4_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5534 /* IDB_OBM4_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5535 /* IDB_OBM4_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5536 /* IDB_OBM4_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5537 /* IDB_OBM4_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5538 /* IDB_OBM4_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5539 /* IDB_OBM4_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5540 /* IDB_OBM4_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5541 /* IDB_OBM4_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5542 /* IDB_OBM4_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5543 /* IDB_OBM4_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5544 /* IDB_OBM4_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5545 /* IDB_OBM4_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5546 /* IDB_OBM4_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5547 /* IDB_OBM4_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.", 5548 /* IDB_OBM4_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 5549 /* IDB_OBM4_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 5550 /* IDB_OBM4_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 5551 /* IDB_OBM4_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 5552 /* IDB_OBM4_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5553 /* IDB_OBM4_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5554 /* IDB_OBM4_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5555 /* IDB_OBM4_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5556 /* IDB_OBM4_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5557 /* IDB_OBM4_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5558 /* IDB_OBM4_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5559 /* IDB_OBM4_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5560 /* IDB_OBM4_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5561 /* IDB_OBM4_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5562 /* IDB_OBM4_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5563 /* IDB_OBM4_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5564 /* IDB_OBM4_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5565 /* IDB_OBM4_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5566 /* IDB_OBM4_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5567 /* IDB_OBM4_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5568 /* IDB_OBM4_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5569 /* IDB_OBM4_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5570 /* IDB_OBM4_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5571 /* IDB_OBM4_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5572 /* IDB_OBM5_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5573 /* IDB_OBM5_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5574 /* IDB_OBM5_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5575 /* IDB_OBM5_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5576 /* IDB_OBM5_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5577 /* IDB_OBM5_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5578 /* IDB_OBM5_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5579 /* IDB_OBM5_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5580 /* IDB_OBM5_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5581 /* IDB_OBM5_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5582 /* IDB_OBM5_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5583 /* IDB_OBM5_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5584 /* IDB_OBM5_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5585 /* IDB_OBM5_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5586 /* IDB_OBM5_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5587 /* IDB_OBM5_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5588 /* IDB_OBM5_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5589 /* IDB_OBM5_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5590 /* IDB_OBM5_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5591 /* IDB_OBM5_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5592 /* IDB_OBM5_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5593 /* IDB_OBM5_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5594 /* IDB_OBM5_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5595 /* IDB_OBM5_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5596 /* IDB_OBM5_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5597 /* IDB_OBM5_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5598 /* IDB_OBM5_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5599 /* IDB_OBM5_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5600 /* IDB_OBM5_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5601 /* IDB_OBM5_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5602 /* IDB_OBM5_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5603 /* IDB_OBM5_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5604 /* IDB_OBM5_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5605 /* IDB_OBM5_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5606 /* IDB_OBM5_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5607 /* IDB_OBM5_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5608 /* IDB_OBM5_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5609 /* IDB_OBM5_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5610 /* IDB_OBM5_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5611 /* IDB_OBM5_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5612 /* IDB_OBM5_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.", 5613 /* IDB_OBM5_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 5614 /* IDB_OBM5_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 5615 /* IDB_OBM5_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 5616 /* IDB_OBM5_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 5617 /* IDB_OBM5_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5618 /* IDB_OBM5_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5619 /* IDB_OBM5_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5620 /* IDB_OBM5_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5621 /* IDB_OBM5_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5622 /* IDB_OBM5_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5623 /* IDB_OBM5_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5624 /* IDB_OBM5_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5625 /* IDB_OBM5_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5626 /* IDB_OBM5_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5627 /* IDB_OBM5_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5628 /* IDB_OBM5_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5629 /* IDB_OBM5_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5630 /* IDB_OBM5_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5631 /* IDB_OBM5_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5632 /* IDB_OBM5_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5633 /* IDB_OBM5_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5634 /* IDB_OBM5_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5635 /* IDB_OBM5_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5636 /* IDB_OBM5_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5637 /* IDB_OBM6_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5638 /* IDB_OBM6_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5639 /* IDB_OBM6_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5640 /* IDB_OBM6_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5641 /* IDB_OBM6_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5642 /* IDB_OBM6_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5643 /* IDB_OBM6_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5644 /* IDB_OBM6_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5645 /* IDB_OBM6_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5646 /* IDB_OBM6_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5647 /* IDB_OBM6_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5648 /* IDB_OBM6_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5649 /* IDB_OBM6_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5650 /* IDB_OBM6_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5651 /* IDB_OBM6_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5652 /* IDB_OBM6_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5653 /* IDB_OBM6_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5654 /* IDB_OBM6_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5655 /* IDB_OBM6_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5656 /* IDB_OBM6_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5657 /* IDB_OBM6_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5658 /* IDB_OBM6_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5659 /* IDB_OBM6_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5660 /* IDB_OBM6_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5661 /* IDB_OBM6_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5662 /* IDB_OBM6_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5663 /* IDB_OBM6_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5664 /* IDB_OBM6_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5665 /* IDB_OBM6_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5666 /* IDB_OBM6_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5667 /* IDB_OBM6_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5668 /* IDB_OBM6_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5669 /* IDB_OBM6_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5670 /* IDB_OBM6_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5671 /* IDB_OBM6_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5672 /* IDB_OBM6_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5673 /* IDB_OBM6_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5674 /* IDB_OBM6_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5675 /* IDB_OBM6_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5676 /* IDB_OBM6_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5677 /* IDB_OBM6_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.", 5678 /* IDB_OBM6_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 5679 /* IDB_OBM6_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 5680 /* IDB_OBM6_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 5681 /* IDB_OBM6_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 5682 /* IDB_OBM6_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5683 /* IDB_OBM6_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5684 /* IDB_OBM6_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5685 /* IDB_OBM6_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5686 /* IDB_OBM6_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5687 /* IDB_OBM6_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5688 /* IDB_OBM6_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5689 /* IDB_OBM6_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5690 /* IDB_OBM6_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5691 /* IDB_OBM6_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5692 /* IDB_OBM6_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5693 /* IDB_OBM6_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5694 /* IDB_OBM6_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5695 /* IDB_OBM6_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5696 /* IDB_OBM6_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5697 /* IDB_OBM6_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5698 /* IDB_OBM6_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5699 /* IDB_OBM6_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5700 /* IDB_OBM6_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5701 /* IDB_OBM6_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5702 /* IDB_OBM7_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5703 /* IDB_OBM7_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5704 /* IDB_OBM7_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5705 /* IDB_OBM7_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5706 /* IDB_OBM7_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5707 /* IDB_OBM7_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5708 /* IDB_OBM7_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5709 /* IDB_OBM7_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5710 /* IDB_OBM7_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5711 /* IDB_OBM7_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5712 /* IDB_OBM7_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5713 /* IDB_OBM7_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5714 /* IDB_OBM7_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5715 /* IDB_OBM7_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5716 /* IDB_OBM7_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5717 /* IDB_OBM7_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5718 /* IDB_OBM7_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5719 /* IDB_OBM7_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5720 /* IDB_OBM7_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5721 /* IDB_OBM7_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5722 /* IDB_OBM7_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5723 /* IDB_OBM7_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5724 /* IDB_OBM7_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5725 /* IDB_OBM7_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5726 /* IDB_OBM7_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5727 /* IDB_OBM7_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5728 /* IDB_OBM7_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5729 /* IDB_OBM7_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5730 /* IDB_OBM7_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5731 /* IDB_OBM7_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5732 /* IDB_OBM7_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5733 /* IDB_OBM7_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5734 /* IDB_OBM7_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5735 /* IDB_OBM7_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5736 /* IDB_OBM7_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5737 /* IDB_OBM7_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5738 /* IDB_OBM7_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5739 /* IDB_OBM7_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5740 /* IDB_OBM7_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5741 /* IDB_OBM7_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5742 /* IDB_OBM7_IOM_STATS_WINDOW_RESULTS */ "Ingress Oversub Monitor Statistics Instrumentation Results.\nEntry 0 to 15: Port 0 results epoch 0 to 15.\nEntry 16 to 31: Port 1 results epoch 0 to 15.\nEntry 32 to 47: Port 2 results epoch 0 to 15.\nEntry 48 to 63: Port 3 results epoch 0 to 15.", 5743 /* IDB_OBM7_MPLS_MAP_PORT0 */ "Priority table based on MPLS TC.", 5744 /* IDB_OBM7_MPLS_MAP_PORT1 */ "Priority table based on MPLS TC.", 5745 /* IDB_OBM7_MPLS_MAP_PORT2 */ "Priority table based on MPLS TC.", 5746 /* IDB_OBM7_MPLS_MAP_PORT3 */ "Priority table based on MPLS TC.", 5747 /* IDB_OBM7_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5748 /* IDB_OBM7_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5749 /* IDB_OBM7_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5750 /* IDB_OBM7_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5751 /* IDB_OBM7_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5752 /* IDB_OBM7_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5753 /* IDB_OBM7_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5754 /* IDB_OBM7_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5755 /* IDB_OBM7_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5756 /* IDB_OBM7_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5757 /* IDB_OBM7_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5758 /* IDB_OBM7_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5759 /* IDB_OBM7_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5760 /* IDB_OBM7_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5761 /* IDB_OBM7_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5762 /* IDB_OBM7_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5763 /* IDB_OBM7_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5764 /* IDB_OBM7_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5765 /* IDB_OBM7_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5766 /* IDB_OBM7_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5767 /* IDB_OBM8_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5768 /* IDB_OBM8_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5769 /* IDB_OBM8_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5770 /* IDB_OBM8_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5771 /* IDB_OBM8_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5772 /* IDB_OBM8_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5773 /* IDB_OBM8_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5774 /* IDB_OBM8_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5775 /* IDB_OBM8_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5776 /* IDB_OBM8_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5777 /* IDB_OBM8_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5778 /* IDB_OBM8_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5779 /* IDB_OBM8_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5780 /* IDB_OBM8_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5781 /* IDB_OBM8_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5782 /* IDB_OBM8_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5783 /* IDB_OBM8_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5784 /* IDB_OBM8_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5785 /* IDB_OBM8_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5786 /* IDB_OBM8_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5787 /* IDB_OBM8_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5788 /* IDB_OBM8_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5789 /* IDB_OBM8_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5790 /* IDB_OBM8_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5791 /* IDB_OBM8_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5792 /* IDB_OBM8_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5793 /* IDB_OBM8_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5794 /* IDB_OBM8_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5795 /* IDB_OBM8_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5796 /* IDB_OBM8_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5797 /* IDB_OBM8_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5798 /* IDB_OBM8_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5799 /* IDB_OBM8_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5800 /* IDB_OBM8_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5801 /* IDB_OBM8_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5802 /* IDB_OBM8_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5803 /* IDB_OBM8_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5804 /* IDB_OBM8_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5805 /* IDB_OBM8_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5806 /* IDB_OBM8_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5807 /* IDB_OBM8_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5808 /* IDB_OBM8_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5809 /* IDB_OBM8_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5810 /* IDB_OBM8_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5811 /* IDB_OBM8_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5812 /* IDB_OBM8_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5813 /* IDB_OBM8_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5814 /* IDB_OBM8_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5815 /* IDB_OBM8_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5816 /* IDB_OBM8_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5817 /* IDB_OBM8_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5818 /* IDB_OBM8_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5819 /* IDB_OBM8_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5820 /* IDB_OBM8_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5821 /* IDB_OBM8_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5822 /* IDB_OBM8_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5823 /* IDB_OBM8_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5824 /* IDB_OBM8_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5825 /* IDB_OBM8_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5826 /* IDB_OBM8_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5827 /* IDB_OBM9_DSCP_MAP_PORT0 */ "Priority table based on DSCP.", 5828 /* IDB_OBM9_DSCP_MAP_PORT1 */ "Priority table based on DSCP.", 5829 /* IDB_OBM9_DSCP_MAP_PORT2 */ "Priority table based on DSCP.", 5830 /* IDB_OBM9_DSCP_MAP_PORT3 */ "Priority table based on DSCP.", 5831 /* IDB_OBM9_DSCP_MAP_PORT0_PIPE0 */ "Priority table based on DSCP.", 5832 /* IDB_OBM9_DSCP_MAP_PORT0_PIPE1 */ "Priority table based on DSCP.", 5833 /* IDB_OBM9_DSCP_MAP_PORT0_PIPE2 */ "Priority table based on DSCP.", 5834 /* IDB_OBM9_DSCP_MAP_PORT0_PIPE3 */ "Priority table based on DSCP.", 5835 /* IDB_OBM9_DSCP_MAP_PORT1_PIPE0 */ "Priority table based on DSCP.", 5836 /* IDB_OBM9_DSCP_MAP_PORT1_PIPE1 */ "Priority table based on DSCP.", 5837 /* IDB_OBM9_DSCP_MAP_PORT1_PIPE2 */ "Priority table based on DSCP.", 5838 /* IDB_OBM9_DSCP_MAP_PORT1_PIPE3 */ "Priority table based on DSCP.", 5839 /* IDB_OBM9_DSCP_MAP_PORT2_PIPE0 */ "Priority table based on DSCP.", 5840 /* IDB_OBM9_DSCP_MAP_PORT2_PIPE1 */ "Priority table based on DSCP.", 5841 /* IDB_OBM9_DSCP_MAP_PORT2_PIPE2 */ "Priority table based on DSCP.", 5842 /* IDB_OBM9_DSCP_MAP_PORT2_PIPE3 */ "Priority table based on DSCP.", 5843 /* IDB_OBM9_DSCP_MAP_PORT3_PIPE0 */ "Priority table based on DSCP.", 5844 /* IDB_OBM9_DSCP_MAP_PORT3_PIPE1 */ "Priority table based on DSCP.", 5845 /* IDB_OBM9_DSCP_MAP_PORT3_PIPE2 */ "Priority table based on DSCP.", 5846 /* IDB_OBM9_DSCP_MAP_PORT3_PIPE3 */ "Priority table based on DSCP.", 5847 /* IDB_OBM9_ETAG_MAP_PORT0 */ "Priority table based on ETAG PCP.", 5848 /* IDB_OBM9_ETAG_MAP_PORT1 */ "Priority table based on ETAG PCP.", 5849 /* IDB_OBM9_ETAG_MAP_PORT2 */ "Priority table based on ETAG PCP.", 5850 /* IDB_OBM9_ETAG_MAP_PORT3 */ "Priority table based on ETAG PCP.", 5851 /* IDB_OBM9_ETAG_MAP_PORT0_PIPE0 */ "Priority table based on ETAG PCP.", 5852 /* IDB_OBM9_ETAG_MAP_PORT0_PIPE1 */ "Priority table based on ETAG PCP.", 5853 /* IDB_OBM9_ETAG_MAP_PORT0_PIPE2 */ "Priority table based on ETAG PCP.", 5854 /* IDB_OBM9_ETAG_MAP_PORT0_PIPE3 */ "Priority table based on ETAG PCP.", 5855 /* IDB_OBM9_ETAG_MAP_PORT1_PIPE0 */ "Priority table based on ETAG PCP.", 5856 /* IDB_OBM9_ETAG_MAP_PORT1_PIPE1 */ "Priority table based on ETAG PCP.", 5857 /* IDB_OBM9_ETAG_MAP_PORT1_PIPE2 */ "Priority table based on ETAG PCP.", 5858 /* IDB_OBM9_ETAG_MAP_PORT1_PIPE3 */ "Priority table based on ETAG PCP.", 5859 /* IDB_OBM9_ETAG_MAP_PORT2_PIPE0 */ "Priority table based on ETAG PCP.", 5860 /* IDB_OBM9_ETAG_MAP_PORT2_PIPE1 */ "Priority table based on ETAG PCP.", 5861 /* IDB_OBM9_ETAG_MAP_PORT2_PIPE2 */ "Priority table based on ETAG PCP.", 5862 /* IDB_OBM9_ETAG_MAP_PORT2_PIPE3 */ "Priority table based on ETAG PCP.", 5863 /* IDB_OBM9_ETAG_MAP_PORT3_PIPE0 */ "Priority table based on ETAG PCP.", 5864 /* IDB_OBM9_ETAG_MAP_PORT3_PIPE1 */ "Priority table based on ETAG PCP.", 5865 /* IDB_OBM9_ETAG_MAP_PORT3_PIPE2 */ "Priority table based on ETAG PCP.", 5866 /* IDB_OBM9_ETAG_MAP_PORT3_PIPE3 */ "Priority table based on ETAG PCP.", 5867 /* IDB_OBM9_PRI_MAP_PORT0 */ "Priority table based on PCP or TC.", 5868 /* IDB_OBM9_PRI_MAP_PORT1 */ "Priority table based on PCP or TC.", 5869 /* IDB_OBM9_PRI_MAP_PORT2 */ "Priority table based on PCP or TC.", 5870 /* IDB_OBM9_PRI_MAP_PORT3 */ "Priority table based on PCP or TC.", 5871 /* IDB_OBM9_PRI_MAP_PORT0_PIPE0 */ "Priority table based on PCP or TC.", 5872 /* IDB_OBM9_PRI_MAP_PORT0_PIPE1 */ "Priority table based on PCP or TC.", 5873 /* IDB_OBM9_PRI_MAP_PORT0_PIPE2 */ "Priority table based on PCP or TC.", 5874 /* IDB_OBM9_PRI_MAP_PORT0_PIPE3 */ "Priority table based on PCP or TC.", 5875 /* IDB_OBM9_PRI_MAP_PORT1_PIPE0 */ "Priority table based on PCP or TC.", 5876 /* IDB_OBM9_PRI_MAP_PORT1_PIPE1 */ "Priority table based on PCP or TC.", 5877 /* IDB_OBM9_PRI_MAP_PORT1_PIPE2 */ "Priority table based on PCP or TC.", 5878 /* IDB_OBM9_PRI_MAP_PORT1_PIPE3 */ "Priority table based on PCP or TC.", 5879 /* IDB_OBM9_PRI_MAP_PORT2_PIPE0 */ "Priority table based on PCP or TC.", 5880 /* IDB_OBM9_PRI_MAP_PORT2_PIPE1 */ "Priority table based on PCP or TC.", 5881 /* IDB_OBM9_PRI_MAP_PORT2_PIPE2 */ "Priority table based on PCP or TC.", 5882 /* IDB_OBM9_PRI_MAP_PORT2_PIPE3 */ "Priority table based on PCP or TC.", 5883 /* IDB_OBM9_PRI_MAP_PORT3_PIPE0 */ "Priority table based on PCP or TC.", 5884 /* IDB_OBM9_PRI_MAP_PORT3_PIPE1 */ "Priority table based on PCP or TC.", 5885 /* IDB_OBM9_PRI_MAP_PORT3_PIPE2 */ "Priority table based on PCP or TC.", 5886 /* IDB_OBM9_PRI_MAP_PORT3_PIPE3 */ "Priority table based on PCP or TC.", 5887 /* IDR_COMPLETE_PC */ "Complete PC list. Interface is for debug only.", 5888 /* IDR_CONTEXT_COLOR */ "Color memory per context", 5889 /* IDR_CONTEXT_MRU */ "Maximum reception size for each reassembly context. Access this memory with Reassemblt-context", 5890 /* IDR_CONTEXT_SIZE */ "Packet size memory per context", 5891 /* IDR_COUNTERS */ "Counters per reassembly context.", 5892 /* IDR_DRAM_BUFFER_TYPE */ "Stores the DRAM-buffer-type to be taken (Mini-Multicast buffer or Full-Multicast buffer).\n The table is access with:\n fwd, snoop, mirror\n - fwd (2 bits):\n - 0- no fwd\n - 1- Unicast or Fabric-Multicast\n - 2- Ingress-MC <=8 copies\n - 3- Ingress-MC >8 copies\n - snoop/mirror (2 bits each):\n - 0-no snoop/mirror\n ...", 5893 /* IDR_DROP_PRECEDENCE_MAPPING */ "Maps dp-meter-cmd, incoming dp and meter-processor-dp to ingress-DP and egress-DP.\n Egress-DP is stamped to the FTMH and ingress-DP is forward to IQM.\n key to the table:\n dp-meter-cmd, incoming-dp, resolved-dp", 5894 /* IDR_ETHERNET_METER_CONFIG */ "Access to this table using pointers from PP that calculated according to:\n (PP port)*5+packet_type_value.\n\n Packet_type_value =\n Unknown Unicast = 0x0.\n Known Unicast=0x1.\n Unknown MC=0x2.\n Known MC=0x3.\n BC=0x4.\n\n Table size is 1300 entries.\n PP port value is 0-255, the maximal value can be reached by the calculation is 1280/\n ...", 5895 /* IDR_ETHERNET_METER_PROFILES */ "Each entry holds an Ethernet meter profile.\n Access to this table is according to profile number selected at Meter Configuration Table.\n Table size is 32 entries.\n Packets associated with this Meter profile might be marked as Red (drop precedence = 3) if the rate or the burst size exceeds the configured values.\n Calculations:\n\n BurstSize = (BurstMantissa)*2^BurstExp\n\n Rate = (RateMantissa) ...", 5896 /* IDR_GLOBAL_METER_PROFILES */ "Each entry holds a Global meter profile.\n Access to this table is according to profile number selected at Meter Configuration Table.\n Table size is 8 entries.\n Packets associated with this Meter profile might be marked as Red (drop precedence = 3) if the rate or the burst size exceeds the configured values.\n Calculations:\n BurstSize = (BurstMantissa)*2^BurstExp\n\n Rate = (RateMantissa)*2^Ra ...", 5897 /* IDR_GLOBAL_METER_STATUS */ "Stores the global meters status", 5898 /* IDR_IRDB */ "Ingress Replication Database.\n For each Multicast ID, this table indicates whether ingress replication is required and whether to use uc buffer for mc packet. If the mc is not ingress mc, the queue resolution is derived from the class field, and the packet is queued to one of the spatial multicast queues.\n Each line in the database holds the indication for 16 multicast IDs.", 5899 /* IDR_IRE_RXI_MEM_DATA */ "Fifo that holds the data received from IRE.", 5900 /* IDR_MCDA_DYNAMIC */ "MRPS - MCD-A - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simoultanouisly.\n - Table0 for meter indexes 0 - 16k-1, Table1 for meter indexes 16k - 32k-1", 5901 /* IDR_MCDA_PCUC */ "Update color memory per context", 5902 /* IDR_MCDA_PRFCFG_0 */ "MRPS - MCD-A - profile configuration.", 5903 /* IDR_MCDA_PRFCFG_FORMAT_0 */ "MRPS - MCD-A - profile configuration.\n This table define the profile config memory fields when the profile ShraingFlag is set.", 5904 /* IDR_MCDA_PRFCFG_FORMAT_1 */ "MRPS - MCD-A - profile configuration.\n This table define the profile config memory fields when the profile ShraingFlag is reset.", 5905 /* IDR_MCDA_PRFSEL */ "MRPS - MCD-A - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simoultanouisly.\n - Table0 for meter indexes 0 - 16k-1, Table1 for meter indexes 16k - 32k-1", 5906 /* IDR_MCDB_DYNAMIC */ "MRPS - MCD-B - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simoultanouisly.\n - Table0 for meter indexes 0 - 16k-1, Table1 for meter indexes 16k - 32k-1", 5907 /* IDR_MCDB_PCUC */ "Update color memory per context", 5908 /* IDR_MCDB_PRFCFG_0 */ "MRPS - MCD-B - profile configuration.", 5909 /* IDR_MCDB_PRFSEL */ "MRPS - MCD-B - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simoultanouisly.\n - Table0 for meter indexes 0 - 16k-1, Table1 for meter indexes 16k - 32k-1", 5910 /* IDR_MEM_00000 */ "INTERNAL", 5911 /* IDR_MEM_10000 */ "INTERNAL", 5912 /* IDR_MEM_30000 */ "INTERNAL", 5913 /* IDR_MEM_40000 */ "INTERNAL", 5914 /* IDR_MEM_50000 */ "INTERNAL", 5915 /* IDR_MEM_60000 */ "INTERNAL", 5916 /* IDR_MEM_100000 */ "INTERNAL", 5917 /* IDR_MEM_110000 */ "INTERNAL", 5918 /* IDR_MEM_120000 */ "INTERNAL", 5919 /* IDR_MEM_140000 */ "INTERNAL", 5920 /* IDR_MEM_180000 */ "INTERNAL", 5921 /* IDR_MEM_10_INTERNAL */ "INTERNAL", 5922 /* IDR_MEM_11_INTERNAL */ "INTERNAL", 5923 /* IDR_MEM_12_INTERNAL */ "INTERNAL", 5924 /* IDR_MEM_13_INTERNAL */ "INTERNAL", 5925 /* IDR_MEM_1B0000 */ "INTERNAL", 5926 /* IDR_MEM_1F0000 */ "INTERNAL", 5927 /* IDR_MEM_1_INTERNAL */ "INTERNAL", 5928 /* IDR_MEM_2_INTERNAL */ "INTERNAL", 5929 /* IDR_MEM_3_INTERNAL */ "INTERNAL", 5930 /* IDR_MEM_4_INTERNAL */ "INTERNAL", 5931 /* IDR_MEM_5_INTERNAL */ "INTERNAL", 5932 /* IDR_MEM_6_INTERNAL */ "INTERNAL", 5933 /* IDR_MEM_7_INTERNAL */ "INTERNAL", 5934 /* IDR_MEM_8_INTERNAL */ "INTERNAL", 5935 /* IDR_MEM_9_INTERNAL */ "INTERNAL", 5936 /* IDR_MRPS_0_IN_DP_MAPPING */ "Maps dp-meter-cmd, incoming dp, Ethernet-meter-dp and Ethernet-meter-invalid to MRPS in-DP and in-Drop.\n key to the table:\n dp-meter-cmd, incoming-dp, Ethernet-meter-dp, Ethernet-meter-invalid", 5937 /* IDR_MRPS_1_IN_DP_MAPPING */ "Maps dp-meter-cmd, incoming dp, Ethernet-meter-dp and Ethernet-meter-invalid to MRPS in-DP and in-Drop.\n key to the table:\n dp-meter-cmd, incoming-dp, Ethernet-meter-dp, Ethernet-meter-invalid", 5938 /* IDR_OCB_BUFFER_TYPE */ "Stores the ocb-buffer-type to be taken (unicast multicast buffer).\n The table is access with:\n fwd, snoop, mirror, queue-eligiblity, mcid-in-range\n fwd (3bits) - 0 - no fwd, 1 - UC, 2 - FMC, 3 Ing-MC 1 copy, 4 Ing-MC n copies\n snoop/mirror (2 bits each) - 0 - no snoop/mirror 1 - UC/FMC 2 - Ing-MC\n queue-eligibility (1 bit) is set if the queue is eligible\n mcid-in-range (1 bits) is set if ...", 5939 /* IDR_PCD_MAP */ "MRPS - MCD-B - parallel color decision mapping table (64 entries x 4)\n Address (6) to this table is:\n - bits 5:4 - MCD-B color decision\n - bits 3 - MCD-B other bucket has credits\n - bits 2:1 - MCD-A color decision\n - bits 0 - MCD-A other bucket has credits\n Notes:\n - If color decision is yellow -> other bucket is based on the CBL. Otherwise EBL.\n - This ...", 5940 /* IDR_QUEUE_IS_DRAM_ELIGIBLE */ "Stores1 bit per queue number (96k queues) which indicates if the queue is eligible for DRAM buffer.\n The two bits per queue QueueIsDramEligible,QueueIsOcbEligible are encoded as following:\n 0x3 - Queue is eligible for OCB\n 0x2 - Queue is eligible for DRAM\n 0x1 - Queue is dropping DRAM packets colored yellow/red (Partial Drop)\n 0x0 - Queue is dropping all DRAM packets (Full Drop)", 5941 /* IDR_QUEUE_IS_OCB_ELIGIBLE */ "Stores1 bit per queue number (96k queues) which indicates if the queue is eligible for OCB buffer.\n The two bits per queue QueueIsDramEligible,QueueIsOcbEligible are encoded as following:\n 0x3 - Queue is eligible for OCB\n 0x2 - Queue is eligible for DRAM\n 0x1 - Queue is dropping DRAM packets colored yellow/red (Partial Drop)\n 0x0 - Queue is dropping all DRAM packets (Full Drop)", 5942 /* IDR_WORDS */ "Word memory.", 5943 /* IEEE1588_TIME */ "Run-time value of NTP time", 5944 /* IEP_CONTEXT_COLOR */ "Color memory per context", 5945 /* IEP_CONTEXT_SIZE_HIGH */ "Packet size memory per context.\n Higher 138 values\n (total of 330 contexts in Jericho)", 5946 /* IEP_CONTEXT_SIZE_LOW */ "Packet size memory per context.\n Lower 192 values", 5947 /* IEP_MCDA_DYNAMIC */ "MCD-A - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (1280-1)", 5948 /* IEP_MCDA_HEADER_APPEND_SIZE_PTR_MAP */ "MCDA - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 5949 /* IEP_MCDA_IN_PP_PORT_MAP */ "MCDA - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 5950 /* IEP_MCDA_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDA - Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 5951 /* IEP_MCDA_PCUC */ "MCDA - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 5952 /* IEP_MCDA_PRFCFG_0 */ "MCD-A - profile configuration.\n First copy\n Both copies should be initialized the same", 5953 /* IEP_MCDA_PRFCFG_1 */ "MCD-A - profile configuration.\n Second copy\n Both copies should be initialized the same", 5954 /* IEP_MCDA_PRFCFG_SHARING_DIS */ "MCD-A - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is reset.", 5955 /* IEP_MCDA_PRFCFG_SHARING_EN */ "MCD-A - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is set.", 5956 /* IEP_MCDA_PRFSEL */ "MCD-A - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (1280-1)", 5957 /* IEP_MCDB_DYNAMIC */ "MCD-B - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (8-1)", 5958 /* IEP_MCDB_HEADER_APPEND_SIZE_PTR_MAP */ "MCDB - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 5959 /* IEP_MCDB_IN_PP_PORT_MAP */ "MCDB - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 5960 /* IEP_MCDB_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDB- Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 5961 /* IEP_MCDB_PCUC */ "MCDB - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 5962 /* IEP_MCDB_PRFCFG_0 */ "MCD-B - profile configuration.\n First copy\n Both copies should be initialized the same", 5963 /* IEP_MCDB_PRFCFG_1 */ "MCD-B - profile configuration.\n Second copy\n Both copies should be initialized the same", 5964 /* IEP_MCDB_PRFCFG_SHARING_DIS */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is reset.", 5965 /* IEP_MCDB_PRFCFG_SHARING_EN */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is set.", 5966 /* IEP_MCDB_PRFSEL */ "MCD-B - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (8-1)", 5967 /* IEP_PCD_MAP */ "Parallel color decision mapping table (64 entries x 4)\n Address (6) to this table is:\n On Dual mode:\n - bits 5:4 - MCD-B color decision\n - bits 3 - MCD-B other bucket has credits\n - bits 2:1 - MCD-A color decision\n - bits 0 - MCD-A other bucket has credits\n Notes:\n - If color decision is yellow -> other bucket is based on the CBL. Otherwise EBL.\n - This table is used in all configurations (parallel / serial) except for when both ptrs are invalid (=bypass)", 5968 /* IFP_AND_REDIRECTION_PROFILE */ "Provide AND bitmaps for FP redirection for multicast packets.", 5969 /* IFP_COS_MAP */ "index by IFP__PROFILE_IDX(from IFP policy table), INT_PRI", 5970 /* IFP_DROP_VECTOR_MASK */ "Action Priority associated with each logical table.", 5971 /* IFP_DROP_VECTOR_MASK_PIPE0 */ "Action Priority associated with each logical table.", 5972 /* IFP_DROP_VECTOR_MASK_PIPE1 */ "Action Priority associated with each logical table.", 5973 /* IFP_DROP_VECTOR_MASK_PIPE2 */ "Action Priority associated with each logical table.", 5974 /* IFP_DROP_VECTOR_MASK_PIPE3 */ "Action Priority associated with each logical table.", 5975 /* IFP_DROP_VECTOR_MASK_PIPE4 */ "Action Priority associated with each logical table.", 5976 /* IFP_DROP_VECTOR_MASK_PIPE5 */ "Action Priority associated with each logical table.", 5977 /* IFP_DROP_VECTOR_MASK_PIPE6 */ "Action Priority associated with each logical table.", 5978 /* IFP_DROP_VECTOR_MASK_PIPE7 */ "Action Priority associated with each logical table.", 5979 /* IFP_EGRESS_PORT_CHECK_FOR_DROP */ "Perform IFP delayed drop logic if PORT_BITMAP[EgressPort] = 1.", 5980 /* IFP_EGRESS_PORT_CHECK_FOR_REDIRECT */ "Perform IFP delayed redirect logic if PORT_BITMAP[EgressPort] = 1.", 5981 /* IFP_EM_DROP_VECTOR_MASK_PROFILE_0 */ "IFP/EM drop vector mask profile", 5982 /* IFP_EM_DROP_VECTOR_MASK_PROFILE_1 */ "IFP/EM drop vector mask profile", 5983 /* IFP_HG_CLASSID_SELECT */ "Controls classid selection into HG header.", 5984 /* IFP_I2E_CLASSID_SELECT */ "Selects one classid from IP tables to be passed to EP.", 5985 /* IFP_KEY_GEN_PROGRAM_PROFILE */ "Key Generator Profile Table that provides instructions for Key Generation", 5986 /* IFP_KEY_GEN_PROGRAM_PROFILE2 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5987 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE0 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5988 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE1 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5989 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE2 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5990 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE3 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5991 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE4 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5992 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE5 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5993 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE6 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5994 /* IFP_KEY_GEN_PROGRAM_PROFILE2_PIPE7 */ "Key Generator Profile Table that provides post muxing instructions for Key Generation.", 5995 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE0 */ "Key Generator Profile Table that provides instructions for Key Generation", 5996 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE1 */ "Key Generator Profile Table that provides instructions for Key Generation", 5997 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE2 */ "Key Generator Profile Table that provides instructions for Key Generation", 5998 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE3 */ "Key Generator Profile Table that provides instructions for Key Generation", 5999 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE4 */ "Key Generator Profile Table that provides instructions for Key Generation", 6000 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE5 */ "Key Generator Profile Table that provides instructions for Key Generation", 6001 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE6 */ "Key Generator Profile Table that provides instructions for Key Generation", 6002 /* IFP_KEY_GEN_PROGRAM_PROFILE_PIPE7 */ "Key Generator Profile Table that provides instructions for Key Generation", 6003 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY */ "Action Priority associated with each logical table.", 6004 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE0 */ "Action Priority associated with each logical table.", 6005 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE1 */ "Action Priority associated with each logical table.", 6006 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE2 */ "Action Priority associated with each logical table.", 6007 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE3 */ "Action Priority associated with each logical table.", 6008 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE4 */ "Action Priority associated with each logical table.", 6009 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE5 */ "Action Priority associated with each logical table.", 6010 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE6 */ "Action Priority associated with each logical table.", 6011 /* IFP_LOGICAL_TABLE_ACTION_PRIORITY_PIPE7 */ "Action Priority associated with each logical table.", 6012 /* IFP_LOGICAL_TABLE_CONFIG */ "IFP Logical Table Configuration Register. Helps to assign a priority to a logical table parition residing in a physical TCAM.", 6013 /* IFP_LOGICAL_TABLE_CONFIG_PIPE0 */ "IFP Logical Table Configuration Register. Helps to assign a priority to a logical table parition residing in a physical TCAM.", 6014 /* IFP_LOGICAL_TABLE_SELECT */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.32 entries are used per slice. It is legal to program only entries 0 to 383 in this TCAM.", 6015 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6016 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE0 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6017 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE1 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6018 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE2 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6019 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE3 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6020 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE4 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6021 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE5 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6022 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE6 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6023 /* IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE7 */ "Data ONLY view of IFP_LOGICAL_TABLE_SELECT", 6024 /* IFP_LOGICAL_TABLE_SELECT_PIPE0 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.32 entries are used per slice. It is legal to program only entries 0 to 383 in this TCAM.", 6025 /* IFP_LOGICAL_TABLE_SELECT_PIPE1 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.32 entries are used per slice. It is legal to program only entries 0 to 383 in this TCAM.", 6026 /* IFP_LOGICAL_TABLE_SELECT_PIPE2 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.32 entries are used per slice. It is legal to program only entries 0 to 383 in this TCAM.", 6027 /* IFP_LOGICAL_TABLE_SELECT_PIPE3 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.32 entries are used per slice. It is legal to program only entries 0 to 383 in this TCAM.", 6028 /* IFP_LOGICAL_TABLE_SELECT_PIPE4 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.16 entries are used per slice.", 6029 /* IFP_LOGICAL_TABLE_SELECT_PIPE5 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.16 entries are used per slice.", 6030 /* IFP_LOGICAL_TABLE_SELECT_PIPE6 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.16 entries are used per slice.", 6031 /* IFP_LOGICAL_TABLE_SELECT_PIPE7 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.16 entries are used per slice.", 6032 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.", 6033 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.", 6034 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.", 6035 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.", 6036 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3 */ "TCAM used to select the Key Generation Profile for the 12 IFP lookups.", 6037 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE4 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.", 6038 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE5 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.", 6039 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE6 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.", 6040 /* IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE7 */ "TCAM used to select the Key Generation Profile for the 9 IFP lookups.", 6041 /* IFP_METER_TABLE */ "METER TABLE STRUCTURES FOR THE FP.", 6042 /* IFP_METER_TABLE_PIPE0 */ "METER TABLE STRUCTURES FOR THE FP.", 6043 /* IFP_METER_TABLE_PIPE1 */ "METER TABLE STRUCTURES FOR THE FP.", 6044 /* IFP_METER_TABLE_PIPE2 */ "METER TABLE STRUCTURES FOR THE FP.", 6045 /* IFP_METER_TABLE_PIPE3 */ "METER TABLE STRUCTURES FOR THE FP.", 6046 /* IFP_METER_TABLE_PIPE4 */ "METER TABLE STRUCTURES FOR THE FP.", 6047 /* IFP_METER_TABLE_PIPE5 */ "METER TABLE STRUCTURES FOR THE FP.", 6048 /* IFP_METER_TABLE_PIPE6 */ "METER TABLE STRUCTURES FOR THE FP.", 6049 /* IFP_METER_TABLE_PIPE7 */ "METER TABLE STRUCTURES FOR THE FP.", 6050 /* IFP_OR_REDIRECTION_PROFILE */ "Provide OR bitmaps or REPLACE bitmaps for FP redirection for multicast packets.", 6051 /* IFP_POLICY_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table IFP_POLICY.", 6052 /* IFP_POLICY_ACTION_PROFILE_PIPE0 */ "Contains bitmap of the actions generated by the associated table IFP_POLICY.", 6053 /* IFP_POLICY_ACTION_PROFILE_PIPE1 */ "Contains bitmap of the actions generated by the associated table IFP_POLICY.", 6054 /* IFP_POLICY_TABLE */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6055 /* IFP_POLICY_TABLE_PIPE0 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6056 /* IFP_POLICY_TABLE_PIPE1 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6057 /* IFP_POLICY_TABLE_PIPE2 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6058 /* IFP_POLICY_TABLE_PIPE3 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6059 /* IFP_POLICY_TABLE_PIPE4 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6060 /* IFP_POLICY_TABLE_PIPE5 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6061 /* IFP_POLICY_TABLE_PIPE6 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6062 /* IFP_POLICY_TABLE_PIPE7 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6063 /* IFP_POLICY_TABLE_WIDE */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6064 /* IFP_POLICY_TABLE_WIDE_PIPE0 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6065 /* IFP_POLICY_TABLE_WIDE_PIPE1 */ "POLICY TABLE FOR DETERMINING ACTION_SETS IN THE IFP.", 6066 /* IFP_PORT_FIELD_SEL */ "FIELD SELECT VALUE FOR EACH SLICE IN THE FP", 6067 /* IFP_PORT_METER_MAP */ "Per port meter enabled setting.", 6068 /* IFP_RANGE_CHECK */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6069 /* IFP_RANGE_CHECK_MASK */ "mask for RANGE CHECK FOR Fields used as a part of the FP key.", 6070 /* IFP_RANGE_CHECK_MASK_A */ "Action Priority associated with each logical table.", 6071 /* IFP_RANGE_CHECK_MASK_A_PIPE0 */ "Action Priority associated with each logical table.", 6072 /* IFP_RANGE_CHECK_MASK_A_PIPE1 */ "Action Priority associated with each logical table.", 6073 /* IFP_RANGE_CHECK_MASK_A_PIPE2 */ "Action Priority associated with each logical table.", 6074 /* IFP_RANGE_CHECK_MASK_A_PIPE3 */ "Action Priority associated with each logical table.", 6075 /* IFP_RANGE_CHECK_MASK_A_PIPE4 */ "Action Priority associated with each logical table.", 6076 /* IFP_RANGE_CHECK_MASK_A_PIPE5 */ "Action Priority associated with each logical table.", 6077 /* IFP_RANGE_CHECK_MASK_A_PIPE6 */ "Action Priority associated with each logical table.", 6078 /* IFP_RANGE_CHECK_MASK_A_PIPE7 */ "Action Priority associated with each logical table.", 6079 /* IFP_RANGE_CHECK_MASK_B */ "Action Priority associated with each logical table.", 6080 /* IFP_RANGE_CHECK_MASK_B_PIPE0 */ "Action Priority associated with each logical table.", 6081 /* IFP_RANGE_CHECK_MASK_B_PIPE1 */ "Action Priority associated with each logical table.", 6082 /* IFP_RANGE_CHECK_MASK_B_PIPE2 */ "Action Priority associated with each logical table.", 6083 /* IFP_RANGE_CHECK_MASK_B_PIPE3 */ "Action Priority associated with each logical table.", 6084 /* IFP_RANGE_CHECK_MASK_B_PIPE4 */ "Action Priority associated with each logical table.", 6085 /* IFP_RANGE_CHECK_MASK_B_PIPE5 */ "Action Priority associated with each logical table.", 6086 /* IFP_RANGE_CHECK_MASK_B_PIPE6 */ "Action Priority associated with each logical table.", 6087 /* IFP_RANGE_CHECK_MASK_B_PIPE7 */ "Action Priority associated with each logical table.", 6088 /* IFP_RANGE_CHECK_MASK_PIPE0 */ "mask for RANGE CHECK FOR Fields used as a part of the FP key.", 6089 /* IFP_RANGE_CHECK_PIPE0 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6090 /* IFP_RANGE_CHECK_PIPE1 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6091 /* IFP_RANGE_CHECK_PIPE2 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6092 /* IFP_RANGE_CHECK_PIPE3 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6093 /* IFP_RANGE_CHECK_PIPE4 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6094 /* IFP_RANGE_CHECK_PIPE5 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6095 /* IFP_RANGE_CHECK_PIPE6 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6096 /* IFP_RANGE_CHECK_PIPE7 */ "RANGE CHECK VALUES FOR Fields used as a part of the FP key.", 6097 /* IFP_REDIRECTION_PROFILE */ "Contains the number of members in each ECMP group. Used with ECMP_POINTER to calulate index to L3_ECMP table", 6098 /* IFP_STORM_CONTROL_METERS */ "STORM CONTROL METER TABLE STRUCTURES FOR THE FP.", 6099 /* IFP_TCAM */ "TCAM FOR FP in the Narrow mode.", 6100 /* IFP_TCAM_PIPE0 */ "TCAM FOR FP in the Narrow mode.", 6101 /* IFP_TCAM_PIPE1 */ "TCAM FOR FP in the Narrow mode.", 6102 /* IFP_TCAM_PIPE2 */ "TCAM FOR FP in the Narrow mode.", 6103 /* IFP_TCAM_PIPE3 */ "TCAM FOR FP in the Narrow mode.", 6104 /* IFP_TCAM_PIPE4 */ "IFP TCAM in the 160b Search Mode.", 6105 /* IFP_TCAM_PIPE5 */ "IFP TCAM in the 160b Search Mode.", 6106 /* IFP_TCAM_PIPE6 */ "IFP TCAM in the 160b Search Mode.", 6107 /* IFP_TCAM_PIPE7 */ "IFP TCAM in the 160b Search Mode.", 6108 /* IFP_TCAM_WIDE */ "IFP TCAM in the 160b Search Mode.", 6109 /* IFP_TCAM_WIDE_PIPE0 */ "IFP TCAM in the 160b Search Mode.", 6110 /* IFP_TCAM_WIDE_PIPE1 */ "IFP TCAM in the 160b Search Mode.", 6111 /* IFP_TCAM_WIDE_PIPE2 */ "IFP TCAM in the 160b Search Mode.", 6112 /* IFP_TCAM_WIDE_PIPE3 */ "IFP TCAM in the 160b Search Mode.", 6113 /* IHB_COE_CHANNEL_ID */ "CoE Map PTC,VID to channel-id", 6114 /* IHB_CONSISTENT_HASHING_PROGRAM_SEL_TCAM */ "TCAM table for consistent hashing program selection. The following configurations also represent the key to search. If no rules match, program 0 will be selected as the default.", 6115 /* IHB_CONSISTENT_HASHING_PROGRAM_VARIABLES */ "this memory gather several valirables per consistent hashing program", 6116 /* IHB_CPU_TRAP_CODE_CTR */ "This table maps CPU trap code to a corresponding. The table has 256 entries, with the index being the CPU trap code, and the entrys value being its counters value.", 6117 /* IHB_DBG_LAST_FEM */ "Holds for each FEM the last inputs and outputs", 6118 /* IHB_DBG_LAST_FES */ "Holds for each FES the last inputs and outputs", 6119 /* IHB_DESTINATION_STATUS */ "This table holds a valid bit for eachsystem-port.", 6120 /* IHB_DSCP_EXP_MAP */ "This table is used to define a DSCP-EXP field based on routing protocol, terminated protocol and terminated DSCP-EXP. The table has 3K entries, with the index being Routing-Protocol, Terminated-Protocol , Terminted-DSCP-EXP. The routing protocol is encoded as follows:\n 0x0 IPv4\n 0x1 IPv6\n 0x2 MPLS\n Each entry contains a new temporary DSCP-EXP value.", 6121 /* IHB_DSCP_EXP_REMARK */ "This table is used to define a DSCP-EXP Remark field based on routing protocol, DSCP-EXP value before remark and CoS profile. The table has 8K entries, with the index being Routing-Protocol, In-DSCP-EXP-Before-Remark, CoS-Profile3:0. The routing protocol is encoded as follows:\n 0x0 IPv4\n 0x1 IPv6\n 0x2 MPLS\n Each entry contains a new DSCP-EXP Remark value.", 6122 /* IHB_ELK_PAYLOAD_FORMAT */ "per FLP program, sets ELK result payload format", 6123 /* IHB_ETHERNET_OAM_OPCODE_MAP */ "This table maps Y1731-Header opcode to an OAM opcode and offset configuration. The table has 256 entries, with the index being Y1731-Headers 8-bit Opcode. The value in each entry includes an 4-bit OAM opcode and an OAM offset, used to indicate OAM stamp location in the header.", 6124 /* IHB_FEC_ECMP */ "The FEC ECMP table contains ECMP information for the first 1K FECs. The table has 1K entries, with the index being the FEC pointer. Each entry has information on the corresponding FEC.", 6125 /* IHB_FEC_ECMP_IS_STATEFUL */ "The FEC ECMP is stateful table contains information for the first 1K FECs. This table has 256 entries and 4 bits per entry. Each bit is correspanding to an FEC ECMP.", 6126 /* IHB_FEC_ENTRY */ "The FEC entry table is accessed with a FEC pointer. The table has 16K entries, and it is divided to two identical tables, for FEC Entry0 and Entry1. The entry format is dependent on the application. The following registers (from FEC Entry General to FEC Entry Format C) describe the table format per application.", 6127 /* IHB_FEC_ENTRY_ACCESSED */ "This table maps a FEC entry to a Flag indicating if the entry was accessed. The table has 16K entries for FEC Entry 0 and 16K entries for FEC Entry 1. The index to the table is the FEC entry number, with every eight entries being stored in a single register line, meaning the register address is set by FEC number 13:3 and entry number in the register by FEC number 2:0. Each entry indicates if the entry was accessed and its content was used for forwarding the packet.", 6128 /* IHB_FEC_ENTRY_FORMAT_A */ "FEC entry tables Format A entry values, for the table described in FEC Entry register.\n This is a description of the fields used for unicast routing (IP or MPLS) into a link layer interface. In this scenario:\n Out-LIF = 4'h0, OutLif\n EEI = ARP-Ptr-Prefix, ArpPtr\n Expected-In-RIF = OutLif11:0", 6129 /* IHB_FEC_ENTRY_FORMAT_B */ "FEC entry tables Format B entry values, for the table described in FEC Entry register.\n Format B is used when the link layer interface is a composite object (in a composite object the Out-LIF points to an entry in the EEDB of type Out-RIF; which points in turn to a link layer entry) or when routing into a tunnel. This is a description of the fields used for Format B. In this scenario:\n Out-Lif = OutLif\n EEI = NULL\n Expect ...", 6130 /* IHB_FEC_ENTRY_FORMAT_C */ "FEC entry tables Format C entry values, for the table described in FEC Entry register.\n This is a description of the fields used for bridging into a TRILL tunnel. In this scenario:\n Out-Lif = NULL\n EEI = Eei\n Expected-In-RIF = NULL", 6131 /* IHB_FEC_ENTRY_FORMAT_NULL */ "FEC entry tables NULL entry values, for the table described in FEC Entry register.\n This is a description of the fields of a NULL entry. In this scenario:\n Out-LIF = NULL\n EEI = NULL\n Expected-In-RIF = NULL", 6132 /* IHB_FEC_ENTRY_GENERAL */ "FEC entry tables general entry values, for the table described in FEC Entry register.\n This is a description of the general fields that are commong to all FEC entry formats.", 6133 /* IHB_FEC_PATH_SELECT */ "This table maps a FEC entry to a protection path selection. The table has 64K . The index to the table is the FEC entry number, with every eight entries being stored in a single register line, meaning the register address is set by FEC number 16:4 and entry number in the register by FEC number 3:1. Each entry indicates if an odd or even protection path should be taken (in case of protection)", 6134 /* IHB_FEC_RPF_ECMP */ "The FEC ECMP table contains ECMP RPF information for the first 4K FECs. The table has 4K entries, with the index being the RPF FEC pointer. Each entry has information on the corresponding FEC.", 6135 /* IHB_FEC_SUPER_ENTRY */ "The FEC super entry table maps FEC pointer to protection pointer. The table has 8K entries, with the index being the FEC pointer13:1. Each entry holds a pointer to the protection path.", 6136 /* IHB_FEM_0_4B_MAP_TABLE */ "This table defines the action type and how to build the action.\n Table Address: MapIndex", 6137 /* IHB_FEM_10_16B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6138 /* IHB_FEM_10_19B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6139 /* IHB_FEM_11_16B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6140 /* IHB_FEM_11_19B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6141 /* IHB_FEM_12_16B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6142 /* IHB_FEM_12_19B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6143 /* IHB_FEM_13_19B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6144 /* IHB_FEM_14_19B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6145 /* IHB_FEM_14_24B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6146 /* IHB_FEM_15_19B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6147 /* IHB_FEM_15_24B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6148 /* IHB_FEM_1_4B_MAP_TABLE */ "Same as Fem0MapTable", 6149 /* IHB_FEM_2_16B_MAP_TABLE */ "For details, see Fem0_4bMapTable.", 6150 /* IHB_FEM_2_19B_MAP_TABLE */ "For details, see Fem0_4bMapTable.", 6151 /* IHB_FEM_3_16B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6152 /* IHB_FEM_3_19B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6153 /* IHB_FEM_4_16B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6154 /* IHB_FEM_4_19B_MAP_TABLE */ "Same as Fem2_16bMapTable", 6155 /* IHB_FEM_5_19B_MAP_TABLE */ "For details, see Fem0_4bMapTable.", 6156 /* IHB_FEM_6_19B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6157 /* IHB_FEM_6_24B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6158 /* IHB_FEM_7_19B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6159 /* IHB_FEM_7_24B_MAP_TABLE */ "Same as Fem5_19bMapTable", 6160 /* IHB_FEM_8_4B_MAP_TABLE */ "Same as Fem0_4bMapTable", 6161 /* IHB_FEM_9_4B_MAP_TABLE */ "Same as Fem0_4bMapTable", 6162 /* IHB_FEM_BIT_SELECT */ "This table holds the 4bits to be taken from the key, which are used to address MapIndexTable.\n Table Address: According to the FEM-Program", 6163 /* IHB_FEM_MAP_INDEX_TABLE */ "This table holds the FEM's Map-Data and Map-Index, which are used as an address to the Fem0..15MapTable.\n Table Address: FEM-Program(2b), Key-Selected-Bits(4b)", 6164 /* IHB_FERA_FIFO */ "FFC instructions and enable", 6165 /* IHB_FERA_LOAD_CHUNK_SELECTION */ "Load chunk selection instructions", 6166 /* IHB_FERA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "Load chunk selection instructions", 6167 /* IHB_FERA_LOAD_SELECT_CHUNK_LITERARY */ "Load chunk selection instructions", 6168 /* IHB_FERA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "Load chunk selection instructions", 6169 /* IHB_FERA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "Load chunk selection instructions", 6170 /* IHB_FERA_UPDATE_INSTRUCTIONS */ "update instructions\n instructions 0-4 are accessed from p0 and instructions 5-9 are accessed from p1", 6171 /* IHB_FER_PEM_PROGRAM_SELECTION_TCAM */ "Fer Pem Program Selection Tcam", 6172 /* IHB_FIFO_DSP */ "FIFO for data sample", 6173 /* IHB_FIFO_DSP_1 */ "FIFO for data sample", 6174 /* IHB_FIFO_DSP_2 */ "FIFO for data sample", 6175 /* IHB_FIFO_ELK_RX */ "FIFO for the elk results", 6176 /* IHB_FIFO_ELK_TX */ "FIFO for the elk requests", 6177 /* IHB_FIFO_FCR_PIPE_7 */ "FER pipe at clk7 (FEC entry pass1)", 6178 /* IHB_FIFO_FCR_PIPE_9 */ "FER pipe at clk9 (FEC entry pass2)", 6179 /* IHB_FIFO_KAPS_PASS_1 */ "FIFO for lpm 1st lookup result", 6180 /* IHB_FIFO_KAPS_PASS_2 */ "FIFO for lpm 2nd lookup result", 6181 /* IHB_FIFO_LEM */ "FIFO for lem lookup result", 6182 /* IHB_FIFO_OAMP_PASS_1 */ "FIFO for oamp 1st lookup result", 6183 /* IHB_FIFO_OAMP_PASS_2 */ "FIFO for oamp 2nd lookup result", 6184 /* IHB_FIFO_PARTIAL_LB */ "FER partial LB keys", 6185 /* IHB_FIFO_PIPE_40_TO_48 */ "FER pipe at clk40 to clk48 (DSP->FCR, LBP eq)", 6186 /* IHB_FIFO_PIPE_40_TO_50 */ "FER pipe at clk40 to clk50 (DSP->LBP eq2)", 6187 /* IHB_FIFO_PIPE_44_TO_50 */ "FER pipe at clk44 to clk50 (DSP -> LBP eq2)", 6188 /* IHB_FIFO_PIPE_8_TO_40 */ "FER pipe at clk8 to clk40 (DSP->DSP)", 6189 /* IHB_FIFO_TCAM_PASS_1 */ "FIFO for tcam 1st pass lookup result", 6190 /* IHB_FIFO_TCAM_PASS_2 */ "FIFO for tcam 2nd pass lookup result", 6191 /* IHB_FLP_CONSISTENT_HASHING_KEY_GEN */ "Program Instruction Table per program\n lines 0-7 : for instructions 0-7\n lines 8-15 : for instructions 8-15", 6192 /* IHB_FLP_KEY_CONSTRUCTION */ "Program Instruction Table\n lines 0-23 : for instructions 0-5\n lines 24-47 : for instructions 6-11", 6193 /* IHB_FLP_LOOKUPS */ "This table includes per Forwarding Lookup (FLP) Program, an instructions list. The table has 24 entries, with every entry corresponding to an FLP program. The values in each entry define the program operations.", 6194 /* IHB_FLP_PROCESS */ "This table includes per Forwarding Lookup (FLP) Program, an instructions list. The table has 24 entries, with every entry corresponding to an FLP program. The values in each entry define the program operations. The values of ResultA are used for forwarding-decision, while the values of ResultB are used for SA-Lookup and RPF.", 6195 /* IHB_FLP_PROGRAM_KEY_GEN_VAR */ "This table providers per program a general variable that can be used in the programmable keys. The tablehas 24 entries, one per Forwarding Lookup (FLP) program, with the value being the general valiable", 6196 /* IHB_FLP_PROGRAM_SELECTION_CAM */ "TCAM table for program-selection in Forwarding Lookup (FLP) unit. The following configurations also represent the key to search. If no rules match, program 0 will be selected as the default.", 6197 /* IHB_FLP_PTC_PROGRAM_SELECT */ "This table maps Port Termination Context (PTC, formerly known as TM port), to Forwarding Lookup profile and Tunnel Termination profile. The table contains 256 entries, one per PTC. Each register contains 8 entries, thus there are 32 configuration registers. Each entry contains the Forwarding Lookup profile used by this PTC.", 6198 /* IHB_FWD_ACT_PROFILE */ "This table defines the actions that need to be taken per forwarding action profile. Throughout the PP, various functions assign a forwarding action profile, while the actions of this profile are defined in this table. The table has 256 entries, with the index being the forwarding action profile, and the entrys value being the required actions", 6199 /* IHB_HEADER_PROFILE */ "Maps each of 16 possible Header profile table", 6200 /* IHB_IEEE_1588_ACTION */ "Accessed with IEEE-1588-Encapsulation (1), IEEE-1588-Address (2), IEEE-1588-Header.Message-Type (4), IEEE-1588-Header.Flag-Field9 In-PP-Port.IEEE-1588-Profile (2)", 6201 /* IHB_IEEE_1588_IDENTIFICATION_CAM */ "This table is used for IEEE1588-protocol identification.\n The table is searched for rules matching, and if all rules don't match then default values will be selected and PacketIsIeee1588 will be set to zero (non IEEE-1588 packet)", 6202 /* IHB_IN_PORT_KEY_GEN_VAR */ "This table provides per port a general variable that can be used in the programmable keys. The table has 256 entries, one per In-port, and the entrys value is the general variable.", 6203 /* IHB_IPP_LAG_TO_LAG_RANGE */ "LAG range memory table.\n Specifies for each LAG group its range and if it is stateful", 6204 /* IHB_ISEM_ACDT_AUX */ "INTERNAL", 6205 /* IHB_ISEM_ACDT_MASTER_H */ "INTERNAL", 6206 /* IHB_ISEM_ACDT_SLAVE_H */ "INTERNAL", 6207 /* IHB_ISEM_KEYT_AUX */ "INTERNAL", 6208 /* IHB_ISEM_KEYT_PLDT_H */ "INTERNAL", 6209 /* IHB_ISEM_MAA_CAM */ "INTERNAL", 6210 /* IHB_ISEM_MAA_CAM_PAYLOAD */ "INTERNAL", 6211 /* IHB_ISEM_MANAGEMENT_MEMORY_H */ "INTERNAL", 6212 /* IHB_ISEM_MANAGEMENT_REQUEST */ "Management requests", 6213 /* IHB_ISEM_PLDT_AUX */ "INTERNAL", 6214 /* IHB_ISEM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 6215 /* IHB_LB_PFC_PROFILE */ "This table provides Load Balancing (LB) Packet Format Code (PFC) profiles. The table has 256 entries, with the index to each entry being In-Port.Lb-Profile , Parser-Leaf-Context. LB-Profile, Packet-Format-Code . Each entry includes five load balancing vector profiles, one per header.", 6216 /* IHB_LB_VECTOR_PROGRAM_MAP */ "The Load Balancing (LB) vector may be configured either as 192-bit or 96-bit. It is built from from 24 chunks of 4-bit or 8-bit, with the value of each chunk being configured by the 2-bit entries in this table. The table has 15 lines, each for a different protocol type. Each line has 24 entries of 2-bit, configuring the contents of each corresponding chunk.\n The 15 lines are arranged as follows:\n Line 0x0: Value: 49'h0_0000_0000_0000 Mask: 49'h1_FFFF_FFFF_FFFF ...", 6217 /* IHB_LPM */ "Longest Prefix Match (LPM) level 1. This table defines the settings of LPM level 1.\n The table has 16K entries, with every entry defining a FEC pointer and related comparison configurations.\n The LPM algorithm uses 6 levels, each of them configured separately. This table defines level 1.", 6218 /* IHB_LPM_2 */ "Longest Prefix Match (LPM) level 2. This table defines the settings of LPM level 2.\n The table has 32K entries, with every entry defining a FEC pointer and related comparison configurations.\n The LPM algorithm uses 6 levels, each of them configured separately. This table defines level 2.", 6219 /* IHB_LPM_3 */ "Longest Prefix Match (LPM) level 3. This table defines the settings of LPM level 3.\n The table has 32K entries, with every entry defining a FEC pointer and related comparison configurations.\n The LPM algorithm uses 6 levels, each of them configured separately. This table defines level 3.", 6220 /* IHB_LPM_4 */ "Longest Prefix Match (LPM) level 4. This table defines the settings of LPM level 4.\n The table has 32K entries, with every entry defining a FEC pointer and related comparison configurations.\n The LPM algorithm uses 6 levels, each of them configured separately. This table defines level 4.", 6221 /* IHB_LPM_5 */ "1.8.2.771.7.2.64 Longest Prefix Match 5\n Longest Prefix Match (LPM) level 5. This table defines the settings of LPM level 5.\n The table has 32K entries, with every entry defining a FEC pointer and related comparison configurations.\n The LPM algorithm uses 6 levels, each of them configured separately. This table defines level 5.", 6222 /* IHB_LPM_6 */ "Longest Prefix Match (LPM) level 6. This table defines the settings of LPM level 6.\n The table has 32K entries, with every entry defining a FEC pointer and related comparison configurations.\n The LPM algorithm uses 6 levels, each of them configured separately. This table defines level 6.", 6223 /* IHB_L_4_OPS */ "Used to calculate L4Ops. The relevant bit of the L4Ops is set to '1' if:\n (source_port >= source_port_min ) &\n (source_port <= source_port_max ) &\n (destination_port >= destination_port_min ) &\n (destination_port <= destination_port_max )\n Reset Value:\n Value: 64'h0 Mask: 64'h0", 6224 /* IHB_MEM_230000 */ "INTERNAL", 6225 /* IHB_MEM_250000 */ "INTERNAL", 6226 /* IHB_MEM_260000 */ "INTERNAL", 6227 /* IHB_MEM_270000 */ "INTERNAL", 6228 /* IHB_MEM_1000000 */ "INTERNAL", 6229 /* IHB_MEM_1010000 */ "INTERNAL", 6230 /* IHB_MEM_1020000 */ "INTERNAL", 6231 /* IHB_MEM_1040000 */ "INTERNAL", 6232 /* IHB_MEM_1050000 */ "INTERNAL", 6233 /* IHB_MEM_1520000 */ "INTERNAL", 6234 /* IHB_MEM_1530000 */ "INTERNAL", 6235 /* IHB_MEM_1640000 */ "INTERNAL", 6236 /* IHB_MEM_1650000 */ "INTERNAL", 6237 /* IHB_MEM_10E0000 */ "INTERNAL", 6238 /* IHB_MEM_10F0000 */ "INTERNAL", 6239 /* IHB_MEM_14A0000 */ "INTERNAL", 6240 /* IHB_MEM_15B0000 */ "INTERNAL", 6241 /* IHB_MEM_15C0000 */ "INTERNAL", 6242 /* IHB_MEM_16E0000 */ "INTERNAL", 6243 /* IHB_MEM_16F0000 */ "INTERNAL", 6244 /* IHB_MEM_AD0000 */ "INTERNAL", 6245 /* IHB_MEM_AE0000 */ "INTERNAL", 6246 /* IHB_MEM_AF0000 */ "INTERNAL", 6247 /* IHB_MEM_B00000 */ "INTERNAL", 6248 /* IHB_MEM_B10000 */ "INTERNAL", 6249 /* IHB_MEM_B20000 */ "INTERNAL", 6250 /* IHB_MEM_B30000 */ "INTERNAL", 6251 /* IHB_MEM_B40000 */ "INTERNAL", 6252 /* IHB_MEM_E00000 */ "INTERNAL", 6253 /* IHB_MEM_E10000 */ "INTERNAL", 6254 /* IHB_MEM_EA0000 */ "INTERNAL", 6255 /* IHB_MEM_F20000 */ "INTERNAL", 6256 /* IHB_MEM_F30000 */ "INTERNAL", 6257 /* IHB_MEM_FB0000 */ "INTERNAL", 6258 /* IHB_MEM_FC0000 */ "INTERNAL", 6259 /* IHB_MRR_ACT_PROFILE */ "", 6260 /* IHB_MY_BFD_DIP */ "This table contains 16 IPv6-Destination-IPs. These IP addresses are compared to incoming destination IP to identify Multi-Hop BFD over IP.\n For IPv4 format, use default IPv4 extension: 0::FFFF:IPv4-DIP", 6261 /* IHB_OAMA */ "Map Inject(1), OAM-is-BFD (1), OAM-Opcode (4), Direction(1), MIP-MP-Type (2), MEP-MP-Type (2), My-CFM-MAC(1), OAM-1-Acc-MEP-Profile (2)", 6262 /* IHB_OAMB */ "Map Inject(1), My-CFM-MAC (1), OAM-is-BFD (1), OAM-Opcode (4), Direction(1), OAM-2-Prof (4)", 6263 /* IHB_OAM_CHANNEL_TYPE */ "This table is used to map Control-Words Channel-Type to OAM-Format. The table contains 16 entries, with the index being a control words channel type. The value in each entry contain sthe OAM format, including format type, format opcode and the result of OAM channel type lookup in the CAM.", 6264 /* IHB_OAM_COUNTER_FIFO */ "Fifo that samples the OAM Counter Value from the FLP and holds it until the relevant packet has arrived.", 6265 /* IHB_OAM_MY_CFM_MAC */ "My-CFM-MAC table. The table maps My-CFM-MAC address to OAM trap engine. The table contains 256 entries, one entry per PP port.\n The purpose of the register to decide if to trap a packet to the OAM engine. The field MacLsbsBitmap is a bitmap, with every bit corresponding to MAC DA7:0. If the bit corresponding with MAC DA7:0 is set and MacMsbs field in the the table is equal to MAC DA47:8 then OAM-My-CFM-MAC is set.", 6266 /* IHB_OEMA_MANAGEMENT_REQUEST */ "Management requests", 6267 /* IHB_OEMA_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 6268 /* IHB_OEMB_MANAGEMENT_REQUEST */ "Management requests", 6269 /* IHB_OEMB_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 6270 /* IHB_OPCODE_MAP_RX */ "opcode -> size, type", 6271 /* IHB_OPCODE_MAP_TX */ "opcode -> size, type", 6272 /* IHB_PATH_SELECT */ "This table maps a FEC entry to a protection path selection. The table has 16K . The index to the table is the FEC entry number, with every eight entries being stored in a single register line, meaning the register address is set by FEC number 13:3 and entry number in the register by FEC number 2:0. Each entry indicates if an odd or even protection path should be taken (in case of protection).", 6273 /* IHB_PFC_INFO */ "This table maps packet-format-code", 6274 /* IHB_PINFO_COUNTERS */ "This table maps In-Port to counters base address. The table has 256 entries, one per In-Port. Every entry contains the counters base address configuration.", 6275 /* IHB_PINFO_FER */ "This table provides port info for FEC Resolution (FER). The table has 256 entries, one per PP port, with the index being the port number. Every entry contains information used for FER decisions by the ingress packet processor.", 6276 /* IHB_PINFO_FLP */ "This table provides port info for the Forwarding Lookup (FLP) unit. The table has 256 entries, one per PP port, with the index being the port number. Every entry contains information used for forwarding loopup decisions by the ingress packet processor.", 6277 /* IHB_PINFO_LBP */ "General configuration per pp port.", 6278 /* IHB_PINFO_PMF */ "This table provides Port Termination Context (PTC, formerly known as TM port), info for Programmable Mapping and Filtering (PMF) unit. The table has 256 entries, one per PTC port, with the index being the port number. Every entry contains information used for PMF decisions by the ingress packet processor.", 6279 /* IHB_PMF_FEM_PROGRAM */ "This table contains the Programmable Mapping and Filtering (PMF) Field Extraction Macros (FES) program. The table has 64 entries, the first 32 entries dedicated to FEM 0-7, and the last 32 entries dedicated to FEM 8-15. Each entry contains a program and key selection for the FEM.", 6280 /* IHB_PMF_FES_PROGRAM */ "This table holds the Program and Key-Select for Field-Extraction-Macros.\n lines 0-31 : for FESs 0-15\n lines 32-63 : for instructions 16-31", 6281 /* IHB_PMF_INITIAL_KEY_2ND_PASS */ "This table maps program to initial key for the 2nd PMF pass. The table has 32 entries, one per program. Every entry contains the initial key to be used for the 2nd PMF pass.\n Used in conjunction with the previous PMF Pass Key Gen and PMF Pass lookup tables.", 6282 /* IHB_PMF_PASS_1_KEY_GEN_LSB */ "Program Instruction Table per program for all 4 keys LSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6283 /* IHB_PMF_PASS_1_KEY_GEN_MSB */ "Program Instruction Table per program for all 4 keys MSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6284 /* IHB_PMF_PASS_1_LOOKUP */ "This table maps program to program instruction. The table has 32 entries, one per program, and there are two tables: for first and second PMF lookup. Every entry contains a TCAM action profile per each one of four keys.", 6285 /* IHB_PMF_PASS_2_KEY_GEN_LSB */ "Program Instruction Table per program for all 4 keys LSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6286 /* IHB_PMF_PASS_2_KEY_GEN_MSB */ "Program Instruction Table per program for all 4 keys MSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6287 /* IHB_PMF_PASS_2_KEY_UPDATE */ "Updating the keys for the second pass lookup. At this stage only the second pass keys are available", 6288 /* IHB_PMF_PASS_2_LOOKUP */ "This table maps program to program instruction. The table has 32 entries, one per program, and there are two tables: for first and second PMF lookup. Every entry contains a TCAM action profile per each one of four keys.", 6289 /* IHB_PMF_PASS_2_PROGRAM_SELECTION_CAM */ "TCAM table for program-selection in Programmable Mapping and Filtering (PMF) unit. The table has 48 entries, with the 32 programs", 6290 /* IHB_PMF_PROGRAM_COUNTERS */ "This table maps program to counters. The table has 32 entries, one per program. Every entry contains the counters configuration.", 6291 /* IHB_PMF_PROGRAM_GENERAL */ "This table provides default values for PMF programs. The table has 32 entries, one per program. Every entry default values for this program.", 6292 /* IHB_PMF_PROGRAM_SELECTION_CAM */ "TCAM table for program-selection in Programmable Mapping and Filtering (PMF) unit. The table has 48 entries, with the 32 programs", 6293 /* IHB_PMF_UPDATE_KEY_GEN_LSB */ "Program Instruction Table per program for all 4 keys LSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6294 /* IHB_PMF_UPDATE_KEY_GEN_MSB */ "Program Instruction Table per program for all 4 keys LSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6295 /* IHB_PROGRAM_KEY_GEN_VAR */ "This table provides per PMF program a general variable that can be used in the programmable keys. The table has 32 entries, one per program, and the entrys value is the general variable.", 6296 /* IHB_PTC_INFO_PMF */ "Port-Termination-Context info", 6297 /* IHB_PTC_KEY_GEN_VAR */ "This table provides per Port Termination Context (PTC) a general variable that can be used in the programmable keys. The table has 256 entries, one per PTC, and the entrys value is the general variable.", 6298 /* IHB_SNOOP_ACTION */ "This table maps snoop command to a snoop action. The table has 256 entries, with the index being the snoop command, and the entrys value being the required snoop action.", 6299 /* IHB_SNP_ACT_PROFILE */ "", 6300 /* IHB_TCAM_ACCESS_PROFILE */ "This table maps TCAM query DB-profile to an access profile. The table has 48 entries, with the index being DB-profile. Each entry defines the access profile, including the memory to access, key size, access type (direct / lookup) and action on the prefix bits.", 6301 /* IHB_TCAM_ACTION */ "This table provides access to the TCAM Action banks. Each TCAM bank is associated with two 20-bit TCAM action memories, provided in this table. Each action table has 1K entries, and there are 24 such tables.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.", 6302 /* IHB_TCAM_ACTION_24 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 20-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 6303 /* IHB_TCAM_ACTION_25 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 20-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction25 belongs to TCAM BANK 12", 6304 /* IHB_TCAM_ACTION_26 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 20-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction26 belongs to TCAM BANK 13", 6305 /* IHB_TCAM_ACTION_27 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 20-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction27 belongs to TCAM BANK 13", 6306 /* IHB_TCAM_ACTION_HIT_INDICATION */ "This table provides a hit indication for each entry in each TCAM Action bank. Each TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 1K entries, divided to 128 register lines of 8-bit, and there are 12x2 such tables.", 6307 /* IHB_TCAM_ACTION_HIT_INDICATION_24 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 6308 /* IHB_TCAM_ACTION_HIT_INDICATION_25 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction25", 6309 /* IHB_TCAM_ACTION_HIT_INDICATION_26 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction26", 6310 /* IHB_TCAM_ACTION_HIT_INDICATION_27 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction27", 6311 /* IHB_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n The table has 12*2K + 2*256 entries, with every entry refering to a TCAM bank.\n First 2K entries belongs to TCAM BANK 0 and so on till BANK 11.\n The bottom 2*256 entries belongs to TCAM Bank 12 and 13.\n Note: The bank address is 11 bits. If the lsb is clear (even address) the entry is a key. If the lsb is set (odd address) the entry is a mask\n ...", 6312 /* IHB_TCAM_BANK_COMMAND */ "TCAM command:\n he command can be write/read/compare. In case of write and compare the Din is needed", 6313 /* IHB_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before", 6314 /* IHB_TCAM_ENTRY_PARITY */ "This table holds the parity bits for each 32-bit in the TCAM. The table is built from 12 tables,\n each of them with 2K entries. Each table represents Parity bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 6315 /* IHB_TCAM_ENTRY_PARITY_12 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 6316 /* IHB_TCAM_ENTRY_PARITY_13 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-13.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 6317 /* IHB_TCAM_PD_PROFILE */ "TCAM Priority Decoder profile.\n This table maps TCAM query DB-profile to a priority decoder profile. The table has 48 entries, with the index being DB-profile. Each entry defines the priority decoder profile through a bitmap selecting which TCAM banks action results will participate in the priority decoder.", 6318 /* IHB_TIME_STAMP_FIFO */ "Fifo that samples the Time stamp from the Parser and holds it until the relevant packet has arrived.", 6319 /* IHB_UNKNOWN_DA_MAP */ "This table is used to map an unknown Destination Address (DA) action profile to a destination address. The table has 24 entries, with the index being DA-Type0..2 In-LIF-DA-Not-Found-Profile, In-PP-Port.DA-Not-Found-Profile and the value being the default destination to use.\n DA-Type is defined as follows:\n 0x0 - Multicast\n 0x1: Broadcast\n 0x2: Unicast\n The reset Value for all lines is 0x0 with a mask value ...", 6320 /* IHB_VRF_CONFIG */ "This table is used to maps VRFto a Default-Destination. The table has 4K entries, with the index being 10-bit VRF, and the entry value being a default destination for IPv4 Unicast and Multicast.", 6321 /* IHP_ACTION_PROFILE_MPLS_VALUE */ "Action profile configuration for default MPLS label actions.", 6322 /* IHP_APPLET_MEMORY */ "Holds all the packets that will be injected in this applet transaction", 6323 /* IHP_BVD_CFG */ "This table assigns an In-LIF profile and a destination per B-VID, in case DA is not found. The table includes 4K entries, pointed by the B-VID. Each entry contains a Destination to be used if Destination Address is not found and an In-LIF profile to be used by the B-VID. This block is used by IRPP.", 6324 /* IHP_BVD_FID_CLASS */ "This table assigns an FID-Class per B-VID. The table includes 4K entries, pointed by the B-VID. Each entry contains an FID-Class to be used by the B-VID. Each register line contains four entries, matching four B-VID values. This block is used by several blocks in the IRPP.", 6325 /* IHP_BVD_TOPOLOGY_ID */ "This table assigns a topology ID per B-VID. The table includes 4K entries, pointed by the B-VID. Each entry contains a topology ID to be used by the B-VID. Each register line contains eight entries, matching eight B-VID values. Note that the entry sets the 4 lsb of the topology ID, and the upper 2-bit are set to zero. This block is used both by IRPP and ERPP.", 6326 /* IHP_CONSISTENT_HASHING_PROGRAM_SEL_TCAM */ "TCAM table for consistent hashing program selection. The following configurations also represent the key to search. If no rules match, program 0 will be selected as the default.", 6327 /* IHP_DEFAULT_COUNTER_SOURCE */ "each of the 4 LIFs is mapped to a 2b value according to range:\n 2'b00 - lif invalid\n 2'b01 - lif not in range\n 2'b10 - lif in range 0\n 2'b11 - lif in range 1\n 8b conactanted value of all LIFs is constrcuted, ordered according to usage order, MSB to LSB (bits 7:6 are always VT0 LIF).\n table is acccessed with the upper 5b. the lower 3b is used to select CounterSource pair from a line.", 6328 /* IHP_DESIGNATED_VLAN_TABLE */ "This table hold 8 designated VLANs, per pp-port designated-vlan index.", 6329 /* IHP_DSCP_EXP_MAP */ "This table is used to define a DSCP-EXP field based on routing protocol, terminated protocol and terminated DSCP-EXP. The table has 3K entries, with the index being Routing-Protocol, Terminated-Protocol , Terminted-DSCP-EXP. The routing protocol is encoded as follows:\n 0x0 IPv4\n 0x1 IPv6\n 0x2 MPLS\n Each entry contains a new temporary DSCP-EXP value.", 6330 /* IHP_DSCP_EXP_REMARK */ "This table is used to define a DSCP-EXP Remark field based on routing protocol, DSCP-EXP value before remark and CoS profile. The table has 8K entries, with the index being Routing-Protocol, In-DSCP-EXP-Before-Remark, CoS-Profile3:0. The routing protocol is encoded as follows:\n 0x0 IPv4\n 0x1 IPv6\n 0x2 MPLS\n Each entry contains a new DSCP-EXP Remark value.", 6331 /* IHP_ELK_PAYLOAD_FORMAT */ "per FLP program, sets ELK result payload format", 6332 /* IHP_ETHERNET_OAM_OPCODE_MAP */ "This table maps Y1731-Header opcode to an OAM opcode and offset configuration. The table has 256 entries, with the index being Y1731-Headers 8-bit Opcode. The value in each entry includes an 4-bit OAM opcode and an OAM offset, used to indicate OAM stamp location in the header.", 6333 /* IHP_FID_CLASS_2_FID */ "This table maps FID-Class to a 15bit Forwarding ID (FID). The table has seven entries, each pointed by an FID-Class. Each entry contains the FID value to be matched with the index FID-Class.", 6334 /* IHP_FIFO_10_TO_41 */ "FIFO for packet data waiting for the ELK results\n From pipe-clk 10 to pipe-clk 41", 6335 /* IHP_FIFO_8_TO_41 */ "FIFO for packet data waiting for the ELK results\n From pipe-clk 8 to pipe-clk 41", 6336 /* IHP_FIFO_LEM_1 */ "FIFO for lem 1st lookup result", 6337 /* IHP_FIFO_LEM_2 */ "FIFO for lem 2nd lookup result", 6338 /* IHP_FIFO_LPM_1 */ "FIFO for lpm 1st lookup result", 6339 /* IHP_FIFO_LPM_2 */ "FIFO for lpm 2nd lookup result", 6340 /* IHP_FIFO_LPM_PUBLIC_1 */ "FIFO for lpm public 1st lookup result", 6341 /* IHP_FIFO_LPM_PUBLIC_2 */ "FIFO for lpm public 2nd lookup result", 6342 /* IHP_FIFO_OAM */ "FIFO for oam trap engine results", 6343 /* IHP_FIFO_OID_1 */ "FIFO for oam identification", 6344 /* IHP_FIFO_OID_2 */ "FIFO for oam identification", 6345 /* IHP_FIFO_PROGRAM_ATTRIBUTES */ "FIFO for packet data waiting for the ELK results\n From pipe-clk 12", 6346 /* IHP_FIFO_TCAM */ "FIFO for tcam lookup result", 6347 /* IHP_FLPA_FIFO */ "FFC instructions and enable", 6348 /* IHP_FLPA_LOAD_CHUNK_SELECTION */ "Load chunk selection instructions", 6349 /* IHP_FLPA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "Load chunk selection instructions", 6350 /* IHP_FLPA_LOAD_SELECT_CHUNK_LITERARY */ "Load chunk selection instructions", 6351 /* IHP_FLPA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "Load chunk selection instructions", 6352 /* IHP_FLPA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "Load chunk selection instructions", 6353 /* IHP_FLPA_UPDATE_INSTRUCTIONS */ "update instructions\n instructions 0-4 are accessed from p0 and instructions 5-9 are accessed from p1", 6354 /* IHP_FLP_CONSISTENT_HASHING_KEY_GEN */ "Program Instruction Table per program\n lines 0-7 : for instructions 0-7\n lines 8-15 : for instructions 8-15", 6355 /* IHP_FLP_KEY_CONSTRUCTION_LSB */ "Program Instruction Table for keys LSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6356 /* IHP_FLP_KEY_CONSTRUCTION_MSB */ "Program Instruction Table for keys MSB\n lines 0-31 : for instructions 0-7\n lines 32-63 : for instructions 8-15", 6357 /* IHP_FLP_LOOKUPS */ "This table includes per Forwarding Lookup (FLP) Program, an instructions list. The table has 24 entries, with every entry corresponding to an FLP program. The values in each entry define the program operations.", 6358 /* IHP_FLP_PP_PORT_PROGRAM_SELECT */ "This table maps In PP Port to Forwarding Lookup profile", 6359 /* IHP_FLP_PROCESS */ "This table includes per Forwarding Lookup (FLP) Program, an instructions list. The table has 24 entries, with every entry corresponding to an FLP program. The values in each entry define the program operations. The values of ResultA are used for forwarding-decision, while the values of ResultB are used for SA-Lookup and RPF.", 6360 /* IHP_FLP_PROGRAM_KEY_GEN_VAR */ "This table providers per program a general variable that can be used in the programmable keys. The tablehas 24 entries, one per Forwarding Lookup (FLP) program, with the value being the general valiable", 6361 /* IHP_FLP_PROGRAM_SELECTION_CAM */ "TCAM table for program-selection in Forwarding Lookup (FLP) unit. The following configurations also represent the key to search. If no rules match, program 0 will be selected as the default.", 6362 /* IHP_FLP_PTC_PROGRAM_SELECT */ "This table maps Port Termination Context (PTC, formerly known as TM port), to Forwarding Lookup profile and Tunnel Termination profile. The table contains 256 entries, one per PTC. Each register contains 8 entries, thus there are 32 configuration registers. Each entry contains the Forwarding Lookup profile used by this PTC.", 6363 /* IHP_IEEE_1588_ACTION */ "Accessed with IEEE-1588-Encapsulation (1), IEEE-1588-Address (2), IEEE-1588-Header.Message-Type (4), IEEE-1588-Header.Flag-Field9 In-PP-Port.IEEE-1588-Profile (2)", 6364 /* IHP_IEEE_1588_IDENTIFICATION_CAM */ "This table is used for IEEE1588-protocol identification.\n The table is searched for rules matching, and if all rules don't match then default values will be selected and PacketIsIeee1588 will be set to zero (non IEEE-1588 packet)", 6365 /* IHP_INGRESS_VLAN_EDIT_COMMAND_TABLE */ "accessed with Packet-Is-MEF-L2CP(1), LLVP-Incoming-Tag-Structure (4), AC-VLAN-Edit-Profile (3)", 6366 /* IHP_IN_RIF_CONFIG_TABLE */ "In-Rif configuration table", 6367 /* IHP_ISA_MANAGEMENT_REQUEST */ "Management requests", 6368 /* IHP_ISA_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 6369 /* IHP_ISB_MANAGEMENT_REQUEST */ "Management requests", 6370 /* IHP_ISB_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 6371 /* IHP_LIF_0_ACCESSED */ "bit per SEM result table entry, if set, SEM result (LIF) accessed, holds VT0/TT0", 6372 /* IHP_LIF_1_ACCESSED */ "bit per SEM result table entry, if set, SEM result (LIF) accessed, holds VT1/TT1", 6373 /* IHP_LIF_ACCESSED */ "bit per SEM result tale entry, if set, SEM result (LIF) accessed.", 6374 /* IHP_LIF_TABLE */ "The Small-EM result table is accessed with the SEM-Index which is a result of the Small-EM lookup. The entry format is dependent on the key into the Small-EM and the application. The table contains 16K entries.", 6375 /* IHP_LIF_TABLE_AC_2_EEI */ "This is the format of a P2P AC that is connected to a PWE.", 6376 /* IHP_LIF_TABLE_AC_2_OUT_LIF */ "This is the format of a P2P AC that is connected to an AC.", 6377 /* IHP_LIF_TABLE_AC_MP */ "This is the format of a multipoint AC.", 6378 /* IHP_LIF_TABLE_AC_P2P_TO_AC */ "This is the format of a P2P AC that is connected to an AC.", 6379 /* IHP_LIF_TABLE_AC_P2P_TO_PBB */ "This is the format of a P2P AC that is connected to a PBP.", 6380 /* IHP_LIF_TABLE_AC_P2P_TO_PWE */ "This is the format of a P2P AC that is connected to a PWE.", 6381 /* IHP_LIF_TABLE_DOUBLE_DATA */ "Double Data Entry", 6382 /* IHP_LIF_TABLE_IP_TT */ "IP tunnels are terminated according to this entry.", 6383 /* IHP_LIF_TABLE_ISID_MP */ "This is the format of a PBP with a multipoint service.", 6384 /* IHP_LIF_TABLE_ISID_P2P */ "This is the format of a PBP with a P2P service.", 6385 /* IHP_LIF_TABLE_LABEL_PROTOCOL_OR_LSP */ "MPLS labels with an IP header above ther are terminated according to this entry.", 6386 /* IHP_LIF_TABLE_LABEL_PWE_MP */ "Multipoint service MPLS labels are terminated according to this entry.", 6387 /* IHP_LIF_TABLE_LABEL_PWE_P2P */ "P2P service MPLS labels are terminated according to this entry.", 6388 /* IHP_LIF_TABLE_TRILL */ "TRILL encapsulated packets are terminated according to this entry.", 6389 /* IHP_LLR_FIFO_P_14_PIPE */ "Store pipe after SA-Lookup in the LEM", 6390 /* IHP_LLR_LLVP */ "Link layer VLAN processing table. This table has 256 entries, and the index into the table is VLAN-Classification-Profile Outer-Tag, Outer-Tag-Is-Priority, Inner-Tag .\n Each entry includes information on the matcing VLAN tag and how it should be processed.", 6391 /* IHP_LL_MIRROR_PROFILE */ "Link layer Mirror profile table. This table has 2K entries, and the index into the table is VID-Index, In-PP-Port.Each entry contains the link layer mirror profile matching its index.", 6392 /* IHP_MACT_AGING_CONFIGURATION_TABLE */ "", 6393 /* IHP_MACT_FID_COUNTER_DB */ "Design Behaviour for Err: Countinue", 6394 /* IHP_MACT_FID_COUNTER_PROFILE_DB */ "", 6395 /* IHP_MACT_FID_PROFILE_DB */ "Design Behaviour for Err: Countinue", 6396 /* IHP_MACT_FLUSH_DB */ "Flush DB", 6397 /* IHP_MACT_FORMAT_1 */ "Large-EM Entry Format I B-MACT data (i.e. PBP)", 6398 /* IHP_MACT_FORMAT_2 */ "", 6399 /* IHP_MACT_FORMAT_0_TYPE_0 */ "The LargeEM has several formats. Format1 is used by the forwarding lookups block and its encoding is determined by the application. All encodings have the base format indicated here. Each application is elaborated in the subsequent sections.", 6400 /* IHP_MACT_FORMAT_0_TYPE_1 */ "Large-EM Entry Format I Transparent P2P data (applicable for AC and I-SID)", 6401 /* IHP_MACT_FORMAT_0_TYPE_2 */ "Large-EM Entry Format I B-MACT data (i.e. PBP)", 6402 /* IHP_MACT_FORMAT_3_TYPE_0 */ "", 6403 /* IHP_MACT_FORMAT_3_TYPE_1 */ "", 6404 /* IHP_MACT_PORT_MINE_TABLE_LAG_PORT */ "If set, Lag Port has at least one member this Device\n Design Behaviour for Err: Countinue (might result in deletion of entry an age-cycle earlier/later)", 6405 /* IHP_MACT_PORT_MINE_TABLE_PHYSICAL_PORT */ "If set, Physical Port is local to this Device,\n Each address contains 32 entries\n Design Behaviour for Err: Countinue (might result in deletion of entry an age-cycle earlier/later)", 6406 /* IHP_MACT_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 6407 /* IHP_MAP_RIF_PROFILE_TO_ROUTING_ENABLE */ "This table is accessed with the In-Rif-Profile. Each line holds bitmap vector which map Ethernet.Qualifier-Next-Protocol,IP-Qualifier.Is-Mc to enable bit.", 6408 /* IHP_MEM_300000 */ "INTERNAL", 6409 /* IHP_MEM_380000 */ "INTERNAL", 6410 /* IHP_MEM_420000 */ "INTERNAL", 6411 /* IHP_MEM_430000 */ "INTERNAL", 6412 /* IHP_MEM_500000 */ "INTERNAL", 6413 /* IHP_MEM_580000 */ "INTERNAL", 6414 /* IHP_MEM_590000 */ "INTERNAL", 6415 /* IHP_MEM_610000 */ "INTERNAL", 6416 /* IHP_MEM_620000 */ "INTERNAL", 6417 /* IHP_MEM_740000 */ "INTERNAL", 6418 /* IHP_MEM_750000 */ "INTERNAL", 6419 /* IHP_MEM_820000 */ "INTERNAL", 6420 /* IHP_MEM_830000 */ "INTERNAL", 6421 /* IHP_MEM_940000 */ "INTERNAL", 6422 /* IHP_MEM_950000 */ "INTERNAL", 6423 /* IHP_MEM_7000000 */ "INTERNAL", 6424 /* IHP_MEM_7100000 */ "INTERNAL", 6425 /* IHP_MEM_7110000 */ "INTERNAL", 6426 /* IHP_MEM_7120000 */ "INTERNAL", 6427 /* IHP_MEM_7200000 */ "INTERNAL", 6428 /* IHP_MEM_7210000 */ "INTERNAL", 6429 /* IHP_MEM_7220000 */ "INTERNAL", 6430 /* IHP_MEM_1F0000 */ "INTERNAL", 6431 /* IHP_MEM_6A0000 */ "INTERNAL", 6432 /* IHP_MEM_6B0000 */ "INTERNAL", 6433 /* IHP_MEM_7A0000 */ "INTERNAL", 6434 /* IHP_MEM_8B0000 */ "INTERNAL", 6435 /* IHP_MEM_8C0000 */ "INTERNAL", 6436 /* IHP_MEM_9E0000 */ "INTERNAL", 6437 /* IHP_MEM_9F0000 */ "INTERNAL", 6438 /* IHP_MEM_A10000 */ "INTERNAL", 6439 /* IHP_MEM_A90000 */ "INTERNAL", 6440 /* IHP_MEM_AA0000 */ "INTERNAL", 6441 /* IHP_MEM_B20000 */ "INTERNAL", 6442 /* IHP_MEM_B30000 */ "INTERNAL", 6443 /* IHP_MEM_BB0000 */ "INTERNAL", 6444 /* IHP_MEM_BC0000 */ "INTERNAL", 6445 /* IHP_MEM_C50000 */ "INTERNAL", 6446 /* IHP_MEM_C60000 */ "INTERNAL", 6447 /* IHP_MY_BFD_DIP */ "This table contains 16 IPv6-Destination-IPs. These IP addresses are compared to incoming destination IP to identify Multi-Hop BFD over IP.\n For IPv4 format, use default IPv4 extension: 0::FFFF:IPv4-DIP", 6448 /* IHP_OAMA */ "Map Inject(1), OAM-is-BFD (1), OAM-Opcode (4), Direction(1), MIP-MP-Type (2), MEP-MP-Type (2), My-CFM-MAC(1), OAM-1-Acc-MEP-Profile (2)", 6449 /* IHP_OAMB */ "Map Inject(1), My-CFM-MAC (1), OAM-is-BFD (1), OAM-Opcode (4), Direction(1), OAM-2-Prof (4)", 6450 /* IHP_OAM_CHANNEL_TYPE */ "This table is used to map Control-Words Channel-Type to OAM-Format. The table contains 16 entries, with the index being a control words channel type. The value in each entry contain sthe OAM format, including format type, format opcode and the result of OAM channel type lookup in the CAM.", 6451 /* IHP_OAM_MY_CFM_MAC */ "My-CFM-MAC table. The table maps My-CFM-MAC address to OAM trap engine. The table contains 256 entries, one entry per PP port.\n The purpose of the register to decide if to trap a packet to the OAM engine. The field MacLsbsBitmap is a bitmap, with every bit corresponding to MAC DA7:0. If the bit corresponding with MAC DA7:0 is set and MacMsbs field in the the table is equal to MAC DA47:8 then OAM-My-CFM-MAC is set.", 6452 /* IHP_PACKET_FORMAT_TABLE */ "This table maps the Parser-End-Leaf to Packet-Format-Code value, and Parser-Leaf-Context.", 6453 /* IHP_PARSER_CUSTOM_MACRO_PARAMETERS */ "Parser custom macro configuration parameters, 0-3 are for set 0, 4-7 are for set 1", 6454 /* IHP_PARSER_CUSTOM_MACRO_PROTOCOLS */ "Parser custom macro protocols. 15 shared by all macros", 6455 /* IHP_PARSER_CUSTOM_MACRO_WORD_MAP */ "Custom macro word map.", 6456 /* IHP_PARSER_ETH_PROTOCOLS */ "The parser identifies these Ethernet -Type and DSAP/SSAP values", 6457 /* IHP_PARSER_IPV4_NEXT_PROTOCOL_SIZE */ "Per IPv4 Next-protocol value, add up to 7B to header size.", 6458 /* IHP_PARSER_IPV6_NEXT_PROTOCOL_SIZE */ "Per IPv6 Next-protocol value, add up to 7B to header size.", 6459 /* IHP_PARSER_IP_PROTOCOLS */ "The parser identifes these IP protocol values", 6460 /* IHP_PARSER_MPLS_NEXT_PROTOCOL_SPECULATE_MAP */ "Maps of first nibble after MPLS BOS label to next protocol value.", 6461 /* IHP_PARSER_PEM_PROGRAM_SELECTION_TCAM */ "Fer Pem Program Selection Tcam", 6462 /* IHP_PARSER_PROGRAM */ "Parser program memory", 6463 /* IHP_PARSER_PROGRAM_POINTER_FEM_BIT_SELECT_TABLE */ "", 6464 /* IHP_PARSER_PROGRAM_POINTER_FEM_FIELD_SELECT_MAP */ "", 6465 /* IHP_PARSER_PROGRAM_POINTER_FEM_MAP_INDEX_TABLE */ "", 6466 /* IHP_PCP_MAP_TABLE */ "PCP map table.\n Accessed with Cos-Profile, Cos-Profile-Map-Key-Lsb, each line holds 4 values", 6467 /* IHP_PFQ_0_FEM_BIT_SELECT_TABLE */ "", 6468 /* IHP_PFQ_0_FEM_FIELD_SELECT_MAP */ "", 6469 /* IHP_PFQ_0_FEM_MAP_INDEX_TABLE */ "", 6470 /* IHP_PINFO_FLP_0 */ "This table provides port info for the Forwarding Lookup (FLP) unit. The table has 256 entries, one per PP port, with the index being the port number. Every entry contains information used for forwarding lookup decisions by the ingress packet processor.", 6471 /* IHP_PINFO_FLP_1 */ "This table provides port info for the Forwarding Lookup (FLP) unit. The table has 256 entries, one per PP port, with the index being the port number. Every entry contains information used for forwarding loopup decisions by the ingress packet processor.", 6472 /* IHP_PINFO_LLR */ "This register includes port information settings of the IHP link layer block. This table has 256 entries, one per port.", 6473 /* IHP_PORT_PROTOCOL */ "This table is used for port-protocol based Traffic-Class and Initial-VID resolution.\n It has 128 entries, and the index into the table is Ethernet-Type-Code, In-PP-Port.Port-Profile. Each entry contains the VLAN ID and Traffic Class matching its index.", 6474 /* IHP_PP_PORT_INFO */ "PP-Port parameters table.", 6475 /* IHP_PRSRA_FIFO */ "FFC instructions and enable", 6476 /* IHP_PRSRA_LOAD_CHUNK_SELECTION */ "Load chunk selection instructions", 6477 /* IHP_PRSRA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "Load chunk selection instructions", 6478 /* IHP_PRSRA_LOAD_SELECT_CHUNK_LITERARY */ "Load chunk selection instructions", 6479 /* IHP_PRSRA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "Load chunk selection instructions", 6480 /* IHP_PRSRA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "Load chunk selection instructions", 6481 /* IHP_PRSRA_UPDATE_INSTRUCTIONS */ "update instructions\n instructions 0-4 are accessed from p0 and instructions 5-9 are accessed from p1", 6482 /* IHP_PTC_INFO */ "Port-Termination-Context parameters.", 6483 /* IHP_PTC_PARSER_PROGRAM_POINTER_CONFIG */ "Values for Parser-Program-Pointer resolution. The FEM instruction is Profile. The FEM key is selected by Value-to-Use as follows:\n 00: Header-DataOffset, Header-DataValue5:0\n 01: Header-DataOffset, Value\n 10: Header-DataOffset In-PP-Port.Default-Parser-Program-Pointer", 6484 /* IHP_PTC_PFQ_0_CONFIG */ "Values for Packet-Format-Qualifier-0 resolution. The FEM instruction is Profile. The FEM key is selected by Value-to-Use as follows:\n 00: Header-DataOffset, Header-DataValue5:0\n 01: Header-DataOffset, Value\n 10: Header-DataOffset In-PP-Port.Default-PFQ0", 6485 /* IHP_PTC_SYS_PORT_CONFIG */ "Values for Src-System-Port-ID resolution. The FEM instruction is Profile. The FEM key is selected by Value-to-Use as follows:\n 00: Header-DataOffset, Header-DataValue5:0\n 01: Header-DataOffset, Value\n 10: Header-DataOffset Virtual-Port.Src-System-Port", 6486 /* IHP_PTC_VIRTUAL_PORT_CONFIG */ "Values for Virtual-Port resolution. The FEM instruction is Profile. The FEM key is selected by Value-to-Use as follows:\n 0: Header-DataOffset, Header-DataValue5:0\n 1: Header-DataOffset 2b0, Value", 6487 /* IHP_RECYCLE_COMMAND */ "RecycleCommand to CPU-Trap, Snoop and Mirror mapping table. This table has 32 entries, each entry pointed by a recycle command. Each entry contains a CPU trap code, forwading and snoop strength and a mirror profile, for the specific recycle command.", 6488 /* IHP_RESERVED_MC */ "This table is used to map PP-Port trap profile and DA to IEEE reserved multicast trap code.\n It has 256 entries, and the index into the table is In-PP-Port.Trap-Profile, DA5:0.\n Each entry contains the forwarding and snooping action strength and CPU trap code matching its index", 6489 /* IHP_SRC_SYSTEM_PORT_FEM_BIT_SELECT_TABLE */ "This table holds the bit select configuration for the Src-System-Port field extraction macro", 6490 /* IHP_SRC_SYSTEM_PORT_FEM_FIELD_SELECT_MAP */ "This table holds the field select configuration for the Src-System-Port field extraction macro. It contains all 4 maps.", 6491 /* IHP_SRC_SYSTEM_PORT_FEM_MAP_INDEX_TABLE */ "This table holds the action index configuration for the Src-System-Port field extraction macro", 6492 /* IHP_STP_TABLE */ "This table is accessed with the PP-Port. Each line holds the STP state per topology-ID.", 6493 /* IHP_SUBNET_CLASSIFY */ "Subnet based VLAN classification configuration. This table has 16 entries, and the index into the table is taken from port-property. The IPv4 source IP is compared to these values for subnet classification purposes.\n The reset value for all lines is 0x0 with a mask value of 0x20000000000000", 6494 /* IHP_TC_DP_MAP_TABLE */ "Traffic class and drop precedence map table.\n Accessed with Cos-Profile, Cos-Profile-Map-Key-Lsb, each line holds 4 values", 6495 /* IHP_TERMINATION_PROFILE_TABLE */ "", 6496 /* IHP_TOS_2_COS */ "This table is used to map TOS to Traffic Class and Drop Precedence.\n It has 1K entries, and the index into the table is IP-header.TOS. Each entry contains the Traffic Class and Drop Precedence matching its index.", 6497 /* IHP_UNKNOWN_DA_MAP */ "This table is used to map an unknown Destination Address (DA) action profile to a destination address. The table has 24 entries, with the index being DA-Type0..2 In-LIF-DA-Not-Found-Profile, In-PP-Port.DA-Not-Found-Profile and the value being the default destination to use.\n DA-Type is defined as follows:\n 0x0 - Multicast\n 0x1: Broadcast\n 0x2: Unicast\n The reset Value for all lines is 0x0 with a mask value ...", 6498 /* IHP_VIRTUAL_PORT_FEM_BIT_SELECT_TABLE */ "This table holds the bit select configuration for the PP-Port field extraction macro", 6499 /* IHP_VIRTUAL_PORT_FEM_FIELD_SELECT_MAP */ "This table holds the field select configuration for the PP-Port field extraction macro.", 6500 /* IHP_VIRTUAL_PORT_FEM_MAP_INDEX_TABLE */ "This table holds the action index configuration for the PP-Port field extraction macro", 6501 /* IHP_VIRTUAL_PORT_TABLE */ "Maps the Virtual-Port to an In-PP-Port and Src-System-Port-ID.", 6502 /* IHP_VLAN_EDIT_PCP_DEI_MAP */ "Accessed by VLAN-Edit-PCP-DEI-Profile, PCP-DEI-Map-Key.", 6503 /* IHP_VLAN_PORT_MEMBERSHIP_TABLE */ "This table holds a bit per Initial-VID, PP-Port for the VLAN-Port membership. Table is accessed with Initial-VID, and each line holds one bit per pp-port.", 6504 /* IHP_VLAN_RANGE_COMPRESSION_TABLE */ "32 VLAN compression ranges", 6505 /* IHP_VRID_MY_MAC_CAM */ "CAM interface for vrid based my-mac.", 6506 /* IHP_VRID_MY_MAC_MAP */ "Usage determined by VridMyMacMode.", 6507 /* IHP_VRID_MY_MAC_TCAM */ "TCAM interface for vrid based my-mac.", 6508 /* IHP_VRID_TO_VRF_MAP */ "", 6509 /* IHP_VSI_HIGH_CFG */ "This table assigns ProfileIndex and DaNotFoundDestination for high 16K VSIs - used by IRPP", 6510 /* IHP_VSI_HIGH_DA_NOT_FOUND_DESTINATION */ "This table assigns a destination per VSI, in case DA is not found, for VSIs above 4K. The table includes 28K entries, pointed by the high VSI. Each entry contains a Destination to be used if Destination Address is not found. This block is used by IRPP.", 6511 /* IHP_VSI_HIGH_MY_MAC */ "This table assigns My-MAC-Valid and In-RIF-Valid per VSI, for VSIs above 4K. The table includes 28K entries, pointed by the high VSI. Each entry contains a valid indication for My-MAC and In-RIF, with each line covering 8 High-VSI values. This block is used both by IRPP and ERPP.", 6512 /* IHP_VSI_HIGH_PROFILE */ "This table assigns My-MAC-Index per VSI, for VSIs above 4K. The table includes 28K entries, pointed by the high VSI. Each entry contains My-MAC index for High VSI (above 4K), which is used to map a My-MAC value to that VSI from the HighVsiMyMac table. This block is used by IRPP.", 6513 /* IHP_VSI_LOW_CFG_1 */ "his table assigns Topology-ID and My-MAC per VSI, for the low 4K VSIs. The table includes 4K entries, pointed by the low 4K VSI. Each entry contains the matching topology ID and My-MAC (the MAC address of this device). This block is used both by IRPP and ERPP.", 6514 /* IHP_VSI_LOW_CFG_2 */ "Contains VSI-Profile, FID-Class and DaNotFoundDestination for (VSI < 4K)\n Used by FLP", 6515 /* IHP_VSI_MY_MAC_VALID */ "This table assigns MyMacValid, accessed by VSI14:3 - used by IRPP", 6516 /* IHP_VSI_PORT_MEMBERSHIP */ "This table holds a bit per Initial-VID, PP-Port for the VLAN-Port membership. Table is accessed with Initial-VID, and each line holds one bit per pp-port.", 6517 /* IHP_VTT_1ST_KEY_PROG_SEL_TCAM */ "TCAM interface for 1st key program select.", 6518 /* IHP_VTT_1ST_LOOKUP_PROGRAM_0 */ "", 6519 /* IHP_VTT_1ST_LOOKUP_PROGRAM_1 */ "", 6520 /* IHP_VTT_2ND_KEY_PROG_SEL_TCAM */ "TCAM interface for 2nd key program select.", 6521 /* IHP_VTT_2ND_LOOKUP_PROGRAM_0 */ "", 6522 /* IHP_VTT_2ND_LOOKUP_PROGRAM_1 */ "", 6523 /* IHP_VTT_ETH_PACKET_FORMAT_ATTRIBUTES_TABLE */ "This table is accessed with inner Ethernet-Qualifer.Next-protocol\n and the result is Packet-format-code, Packet leaf-context and Next-protcol-size", 6524 /* IHP_VTT_FIFO_P_25_PIPE */ "FIFO for for Liftable lookup in the vlan translation stage", 6525 /* IHP_VTT_FIFO_P_40_P_50_PIPE */ "FIFO for packet data waiting for the DBs results\n From pipe-clk 40 to pipe-clk 50", 6526 /* IHP_VTT_FIFO_P_56_PIPE */ "FIFO for for Liftable lookup in the vlan translation stage", 6527 /* IHP_VTT_FIFO_P_8_P_18_PIPE */ "FIFO for packet data waiting for the DBs results\n From pipe-clk 8 to pipe-clk 18", 6528 /* IHP_VTT_FIFO_TT_ISA_RESULT */ "FIFO for for the results from ISA in tunnel termination stage", 6529 /* IHP_VTT_FIFO_TT_ISB_RESULT */ "FIFO for for the results from ISB intunnel termination stage", 6530 /* IHP_VTT_FIFO_TT_TCAM_RESULT */ "FIFO for for the results from TCAM in tunnel termination stage", 6531 /* IHP_VTT_FIFO_VT_ISA_RESULT */ "FIFO for for the results from ISA in vlan translation stage", 6532 /* IHP_VTT_FIFO_VT_ISB_RESULT */ "FIFO for for the results from ISB in vlan translation stage", 6533 /* IHP_VTT_FIFO_VT_TCAM_RESULT */ "FIFO for for the results from TCAM in vlan translation stage", 6534 /* IHP_VTT_IN_PP_PORT_CONFIG */ "This table holds VLAN translation and tunnel termination In-PP-Port configurations.", 6535 /* IHP_VTT_IN_PP_PORT_VLAN_CONFIG */ "This table hold the VLAN range compression selection per port.", 6536 /* IHP_VTT_IP_PACKET_FORMAT_ATTRIBUTES_TABLE */ "This table is accessed with Is-IPv4, inner IP-Qualifer.Next-protocol\n and the result is Packet-format-code, Packet leaf-context and Next-protcol-size", 6537 /* IHP_VTT_LLVP */ "VTT VLAN processing table. Entry into table is Parser-Leaf-Context (4), VLAN-Classification-Profile (3b), Packet-Format-Qualifier1.Ethernet-Tag-Format (5))", 6538 /* IHP_VTT_MPLS_LABEL_RANGE_TABLE */ "This table hold 8 Mpls Labels ranges and the range attributes.", 6539 /* IHP_VTT_MPLS_LABEL_TCAM */ "MPLS Label Type TCAM\n This is the register array which is used by all 13 MPLS-Hdr-Parser for label matching", 6540 /* IHP_VTT_PATH_SELECT */ "This table maps a In-LIF.Protection-Pointer and In-LIF.Protection-Path to a protection path selection. The table has 4K entries. The index to the table is the In-LIF.Protection-Pointer and In-LIF.Protection-Path, with every eight entries being stored in a single register line, meaning the register address is set by In-LIF.Protection-Pointer and In-LIF.Protection-Path, and entry number in the register by In-LIF.Protection-Pointer and In-LIF.Protection-Path 2:0. Each entry indicates if an o ...", 6541 /* IHP_VTT_PP_PORT_TT_KEY_VAR */ "Per port tunnel termiantion key variable", 6542 /* IHP_VTT_PP_PORT_VSI_PROFILES */ "", 6543 /* IHP_VTT_PP_PORT_VT_KEY_VAR */ "Per port Vlan translation key variable", 6544 /* IHP_VTT_PS_PACKET_FORMAT_CODE_MAP_TABLE */ "This table is accessed with packet-format-code\n and the result is a new Packet-format-code which used in Vlan translation and tunnel termination program selection stage", 6545 /* IHP_VTT_PTC_CONFIG */ "each line holds the values for 8 Port-Termination-Contexts.", 6546 /* ILB_BUFF_EXTEND */ "Shared memory to store extra data", 6547 /* ILB_FPC_MEM */ "Free Pointer Controller Memory", 6548 /* ILB_LBG_OUTPUT_FIFO */ "Fall through output FIFO for LBG traffic", 6549 /* ILB_MEM_20000 */ "INTERNAL", 6550 /* ILB_MODEMS_FIFO */ "Shared memory for all modems FIFOs", 6551 /* ILB_MODEMS_FIFO_LLM */ "Shared memory for all modems FIFOs pointers (LLM)", 6552 /* ILB_NIF_RXI_MEM */ "Fifo that holds the data received from NIF", 6553 /* ILB_PORT_CONFIG_TABLE */ "Per port configuration table for LBG traffic.\n Map NIF traffic to ILB logic or bypass, according to the LbType.", 6554 /* ILB_VLAN_CONFIG_TABLE */ "Map incoming Port and VLAN id to modems.\n Access this table using concatenation of the port with the 4 least significant bits of the VLAN id.\n Every entry packs 8 modems, to save on ECC bits", 6555 /* ILE_CORE_TX_FIFO_MEM */ "ILKN Tx data FIFO memory for core data segment n.", 6556 /* ILE_ILKN_CORE_RX_DESKEW_MEM */ "ILKN CORE - replacing flops with mems. For RX deskew per lane memory.", 6557 /* ILE_ILKN_FEC_RX_DECODER */ "ILKN FEC - RX decoder FIFO data", 6558 /* ILE_ILKN_FEC_RX_DECODER_VIRTUAL_LANE_DESKEW */ "ILKN FEC - RX decoder per lane deskew FIFO", 6559 /* ILE_PORT_0_CPU_ACCESS */ "This is NOT A MEMORY!!! This is the CPU access bus to ILKN port0 (the registers are implemented inside the core).", 6560 /* ILE_PORT_1_CPU_ACCESS */ "This is NOT A MEMORY!!! This is the CPU access bus to ILKN port1 (the registers are implemented inside the core).", 6561 /* ILE_RX_STATS_MEM_0 */ "Statistics memory for the ILKN RX port n. Entry per channel. Each entry includes bytes, packets and errors counter. The read must be done via the ILKN core, because some of the bits are held in FF in the code (1b MSB and lower lsbs).", 6562 /* ILE_TX_ELK_RXI */ "tx elk RXI memory", 6563 /* ILE_TX_STATS_MEM_0 */ "Statistics memory for the ILKN TX portn. Entry per channel. Each entry includes bytes, packets and errors counter. The read must be done via the ILKN core, because some of the bits are held in FF in the code (1b MSB and lower lsbs).", 6564 /* ILKN_PMH_CORE_TX_FIFO_MEM */ "ILKN Tx data FIFO memory for core data segment n.", 6565 /* ILKN_PMH_PORT_0_CPU_ACCESS */ "This is NOT A MEMORY!!!\n This is the CPU access bus to ILKN port0 (the registers are implemented inside the core).", 6566 /* ILKN_PMH_PORT_1_CPU_ACCESS */ "This is NOT A MEMORY!!!\n This is the CPU access bus to ILKN port1 (the registers are implemented inside the core).", 6567 /* ILKN_PMH_RX_STATS_MEM */ "Statistics memory for the ILKN RX port n. Entry per channel. Each entry includes bytes, packets and errors counter. The read must be done via the ILKN core, because some of the bits are held in FF in the code (1b MSB and lower lsbs).", 6568 /* ILKN_PMH_TX_STATS_MEM */ "Statistics memory for the ILKN TX portn. Entry per channel. Each entry includes bytes, packets and errors counter. The read must be done via the ILKN core, because some of the bits are held in FF in the code (1b MSB and lower lsbs).", 6569 /* ILKN_PML_CORE_TX_FIFO_MEM */ "ILKN Tx data FIFO memory for core data segment n.", 6570 /* ILKN_PML_PORT_0_CPU_ACCESS */ "This is NOT A MEMORY!!!\n This is the CPU access bus to ILKN port0 (the registers are implemented inside the core).", 6571 /* ILKN_PML_PORT_1_CPU_ACCESS */ "This is NOT A MEMORY!!!\n This is the CPU access bus to ILKN port1 (the registers are implemented inside the core).", 6572 /* ILKN_PML_RX_STATS_MEM */ "Statistics memory for the ILKN RX port n. Entry per channel. Each entry includes bytes, packets and errors counter. The read must be done via the ILKN core, because some of the bits are held in FF in the code (1b MSB and lower lsbs).", 6573 /* ILKN_PML_TX_STATS_MEM */ "Statistics memory for the ILKN TX portn. Entry per channel. Each entry includes bytes, packets and errors counter. The read must be done via the ILKN core, because some of the bits are held in FF in the code (1b MSB and lower lsbs).", 6574 /* IL_CHANNEL_REMAP0 */ "Maps Interlaken channels to source port IDs", 6575 /* IL_CHANNEL_REMAP1 */ "Maps Interlaken channels to source port IDs", 6576 /* IL_STAT_MEM_0 */ "RX Stat Mem0", 6577 /* IL_STAT_MEM_1 */ "RX Stat Mem1", 6578 /* IL_STAT_MEM_2 */ "RX Stat Mem 2", 6579 /* IL_STAT_MEM_3 */ "TX Stat Mem3", 6580 /* IL_STAT_MEM_4 */ "TX Stat Mem 4", 6581 /* IMIRROR_BITMAP */ "Alternate Bitmap/path to MTP for Mirroring, FeatureSpecific-Ethernet.", 6582 /* IMP_CONTEXT_COLOR */ "Color memory per context", 6583 /* IMP_CONTEXT_SIZE_HIGH */ "Packet size memory per context.\n Higher 138 values\n (total of 330 contexts in Jericho)", 6584 /* IMP_CONTEXT_SIZE_LOW */ "Packet size memory per context.\n Lower 192 values", 6585 /* IMP_MCDA_DYNAMIC */ "MCD-A - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 6586 /* IMP_MCDA_HEADER_APPEND_SIZE_PTR_MAP */ "MCDA - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 6587 /* IMP_MCDA_IN_PP_PORT_MAP */ "MCDA - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 6588 /* IMP_MCDA_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDA - Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 6589 /* IMP_MCDA_PCUC */ "MCDA - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 6590 /* IMP_MCDA_PRFCFG_0 */ "MCD-A - profile configuration.\n First copy\n Both copies should be initialized the same", 6591 /* IMP_MCDA_PRFCFG_1 */ "MCD-A - profile configuration.\n Second copy\n Both copies should be initialized the same", 6592 /* IMP_MCDA_PRFCFG_SHARING_DIS */ "MCD-A - profile configuration.\n This table defines the profile config memory fields when the profile Sharing Flag is reset.", 6593 /* IMP_MCDA_PRFCFG_SHARING_EN */ "MCD-A - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is set.", 6594 /* IMP_MCDA_PRFSEL */ "MCD-A - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 6595 /* IMP_MCDB_DYNAMIC */ "MCD-B - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 6596 /* IMP_MCDB_HEADER_APPEND_SIZE_PTR_MAP */ "MCDB - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 6597 /* IMP_MCDB_IN_PP_PORT_MAP */ "MCDB - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 6598 /* IMP_MCDB_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDB- Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 6599 /* IMP_MCDB_PCUC */ "MCDB - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 6600 /* IMP_MCDB_PRFCFG_0 */ "MCD-B - profile configuration.\n First copy\n Both copies should be initialized the same", 6601 /* IMP_MCDB_PRFCFG_1 */ "MCD-B - profile configuration.\n Second copy\n Both copies should be initialized the same", 6602 /* IMP_MCDB_PRFCFG_SHARING_DIS */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile Sharing Flag is reset.", 6603 /* IMP_MCDB_PRFCFG_SHARING_EN */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is set.", 6604 /* IMP_MCDB_PRFSEL */ "MCD-B - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 6605 /* IMP_PCD_MAP */ "Parallel color decision mapping table (64 entries x 4)\n Address (6) to this table is:\n On Dual mode:\n - bits 5:4 - MCD-B color decision\n - bits 3 - MCD-B other bucket has credits\n - bits 2:1 - MCD-A color decision\n - bits 0 - MCD-A other bucket has credits\n Notes:\n - If color decision is yellow -> other bucket is based on the CBL. Otherwise EBL.\n - This table is used in all configurations (parallel / serial) except for when both ptrs are invalid (=bypass)", 6606 /* IM_MTP_INDEX */ "Ingress Mirror to Port Table", 6607 /* INCTRLBCASTPKTS */ "Receive Broadcast Frame Counter - Implemented in RxPacketType Memory", 6608 /* INCTRLBYT */ "Receive Frame Octet Counter", 6609 /* INCTRLDISCPKTS */ "Receive Discarded Frame Counter - Implemented in isec_RxErrDscrdsPkts", 6610 /* INCTRLERRPKTS */ "Receive Error Frame Counter - Implemented in isec_RxErrDscrdsPkts", 6611 /* INCTRLMCASTPKTS */ "Receive Multicast Frame Counter - Implemented in RxPacketType Memory", 6612 /* INCTRLUCASTPKTS */ "Receive Unicast Frame Counter - Implemented in RxPacketType Memory", 6613 /* INGRESS_OAM_OPCODE_GROUP */ ".", 6614 /* ING_1588_INGRESS_CTRL */ "ING_1588_INGRESS_CTRL. Indicates various 1588 status messages for each ingress port.", 6615 /* ING_1588_TS_DISPOSITION_PROFILE_TABLE */ "", 6616 /* ING_ACTIVE_L3_IIF_PROFILE */ "Ingress Active L3_IIF Profile table.", 6617 /* ING_ACTIVE_L3_IIF_PROFILE_0 */ "Contains Controls assoc with the 4K VLANs.", 6618 /* ING_DEST_PORT_ENABLE */ "A last-stage master switch which can block packets from any traffic source including SOBMH. Works for all egress ports (including CPU port)", 6619 /* ING_DEVICE_PORT */ "Ingress Physical Port Table.", 6620 /* ING_DNAT_ADDRESS_TYPE */ "Ingress DNAT Address Type table.", 6621 /* ING_DNAT_ADDRESS_TYPE_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6622 /* ING_DNAT_ADDRESS_TYPE_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6623 /* ING_DNAT_ADDRESS_TYPE_DATA_ONLY */ "Ingress DNAT Address Type table.", 6624 /* ING_DNAT_ADDRESS_TYPE_ECC */ "ECC Table for Ingress DNAT Address Type Table.", 6625 /* ING_DNAT_ADDRESS_TYPE_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 6626 /* ING_DNAT_ADDRESS_TYPE_KEY_ATTRIBUTES */ "Key Attributes Table.", 6627 /* ING_DNAT_ADDRESS_TYPE_ONLY */ "Ingress DNAT Address Type TCAM only view.", 6628 /* ING_DNAT_ADDRESS_TYPE_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6629 /* ING_DNAT_ADDRESS_TYPE_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6630 /* ING_DOP_STORAGE_MEM */ "used to store DOP-data", 6631 /* ING_DOP_STORAGE_MEM_PIPE0 */ "used to store DOP-data", 6632 /* ING_DOP_STORAGE_MEM_PIPE1 */ "used to store DOP-data", 6633 /* ING_DVP_2_TABLE */ "Used to generate an ECMP_Group/NHI from the DVP value and other DVP properties.", 6634 /* ING_DVP_TABLE */ "Used to generte a NHI from the DVP value and other DVP properties.", 6635 /* ING_EGRMSKBMAP */ "Ingress Block Mask, FeatureSpecific-Ethernet.", 6636 /* ING_EN_EFILTER_BITMAP */ "Ingress Enable EFilter Bitmap Register.", 6637 /* ING_ETAG_PCP_MAPPING */ "Mapping table for Internal Priority and CNG to ETAG PCP/DE.", 6638 /* ING_EXP_TO_ECN_MAPPING_1 */ "Map MPLS EXP to IP ECN. Used in MPLS tunnel termination flows.", 6639 /* ING_EXP_TO_ECN_MAPPING_2 */ "Map MPLS EXP to IP ECN. Used in MPLS tunnel termination flows.", 6640 /* ING_EXP_TO_IP_ECN_MAPPING */ "Map MPLS EXP to IP ECN. Used in MPLS tunnel termination flows.", 6641 /* ING_FC_HEADER_TYPE */ "FCoE Header Type.", 6642 /* ING_FLEX_CTR_COUNTER_TABLE_0 */ "Counter Table for flexible counter updates", 6643 /* ING_FLEX_CTR_COUNTER_TABLE_1 */ "Counter Table for flexible counter updates", 6644 /* ING_FLEX_CTR_COUNTER_TABLE_2 */ "Counter Table for flexible counter updates", 6645 /* ING_FLEX_CTR_COUNTER_TABLE_3 */ "Counter Table for flexible counter updates", 6646 /* ING_FLEX_CTR_COUNTER_TABLE_4 */ "Counter Table for flexible counter updates", 6647 /* ING_FLEX_CTR_COUNTER_TABLE_5 */ "Counter Table for flexible counter updates", 6648 /* ING_FLEX_CTR_COUNTER_TABLE_6 */ "Counter Table for flexible counter updates", 6649 /* ING_FLEX_CTR_COUNTER_TABLE_7 */ "Counter Table for flexible counter updates", 6650 /* ING_FLEX_CTR_COUNTER_TABLE_8 */ "Counter Table for flexible counter updates", 6651 /* ING_FLEX_CTR_COUNTER_TABLE_9 */ "Counter Table for flexible counter updates", 6652 /* ING_FLEX_CTR_COUNTER_TABLE_10 */ "Counter Table for flexible counter updates", 6653 /* ING_FLEX_CTR_COUNTER_TABLE_11 */ "Counter Table for flexible counter updates", 6654 /* ING_FLEX_CTR_COUNTER_TABLE_12 */ "Counter Table for flexible counter updates", 6655 /* ING_FLEX_CTR_COUNTER_TABLE_13 */ "Counter Table for flexible counter updates", 6656 /* ING_FLEX_CTR_COUNTER_TABLE_14 */ "Counter Table for flexible counter updates", 6657 /* ING_FLEX_CTR_COUNTER_TABLE_15 */ "Counter Table for flexible counter updates", 6658 /* ING_FLEX_CTR_COUNTER_TABLE_16 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6659 /* ING_FLEX_CTR_COUNTER_TABLE_17 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6660 /* ING_FLEX_CTR_COUNTER_TABLE_18 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6661 /* ING_FLEX_CTR_COUNTER_TABLE_19 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6662 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6663 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6664 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6665 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6666 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6667 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6668 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6669 /* ING_FLEX_CTR_COUNTER_TABLE_0_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6670 /* ING_FLEX_CTR_COUNTER_TABLE_0_X */ "Counter Table for flexible counter updates", 6671 /* ING_FLEX_CTR_COUNTER_TABLE_0_Y */ "Counter Table for flexible counter updates", 6672 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6673 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6674 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6675 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6676 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6677 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6678 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6679 /* ING_FLEX_CTR_COUNTER_TABLE_10_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6680 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6681 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6682 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6683 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6684 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6685 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6686 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6687 /* ING_FLEX_CTR_COUNTER_TABLE_11_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6688 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6689 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6690 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6691 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6692 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6693 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6694 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6695 /* ING_FLEX_CTR_COUNTER_TABLE_12_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6696 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6697 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6698 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6699 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6700 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6701 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6702 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6703 /* ING_FLEX_CTR_COUNTER_TABLE_13_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6704 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6705 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6706 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6707 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6708 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6709 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6710 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6711 /* ING_FLEX_CTR_COUNTER_TABLE_14_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6712 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6713 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6714 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6715 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6716 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6717 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6718 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6719 /* ING_FLEX_CTR_COUNTER_TABLE_15_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6720 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6721 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6722 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6723 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6724 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6725 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6726 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6727 /* ING_FLEX_CTR_COUNTER_TABLE_16_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6728 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6729 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6730 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6731 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6732 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6733 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6734 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6735 /* ING_FLEX_CTR_COUNTER_TABLE_17_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6736 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6737 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6738 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6739 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6740 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6741 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6742 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6743 /* ING_FLEX_CTR_COUNTER_TABLE_18_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6744 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE0 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6745 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE1 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6746 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE2 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6747 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE3 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6748 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE4 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6749 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE5 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6750 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE6 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6751 /* ING_FLEX_CTR_COUNTER_TABLE_19_PIPE7 */ "Counter Table for flexible counter updates. These tables are dedicated for IFP Updates.", 6752 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6753 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6754 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6755 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6756 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6757 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6758 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6759 /* ING_FLEX_CTR_COUNTER_TABLE_1_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6760 /* ING_FLEX_CTR_COUNTER_TABLE_1_X */ "Counter Table for flexible counter updates", 6761 /* ING_FLEX_CTR_COUNTER_TABLE_1_Y */ "Counter Table for flexible counter updates", 6762 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6763 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6764 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6765 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6766 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6767 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6768 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6769 /* ING_FLEX_CTR_COUNTER_TABLE_2_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6770 /* ING_FLEX_CTR_COUNTER_TABLE_2_X */ "Counter Table for flexible counter updates", 6771 /* ING_FLEX_CTR_COUNTER_TABLE_2_Y */ "Counter Table for flexible counter updates", 6772 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6773 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6774 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6775 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6776 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6777 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6778 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6779 /* ING_FLEX_CTR_COUNTER_TABLE_3_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6780 /* ING_FLEX_CTR_COUNTER_TABLE_3_X */ "Counter Table for flexible counter updates", 6781 /* ING_FLEX_CTR_COUNTER_TABLE_3_Y */ "Counter Table for flexible counter updates", 6782 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6783 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6784 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6785 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6786 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6787 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6788 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6789 /* ING_FLEX_CTR_COUNTER_TABLE_4_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6790 /* ING_FLEX_CTR_COUNTER_TABLE_4_X */ "Counter Table for flexible counter updates", 6791 /* ING_FLEX_CTR_COUNTER_TABLE_4_Y */ "Counter Table for flexible counter updates", 6792 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6793 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6794 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6795 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6796 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6797 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6798 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6799 /* ING_FLEX_CTR_COUNTER_TABLE_5_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6800 /* ING_FLEX_CTR_COUNTER_TABLE_5_X */ "Counter Table for flexible counter updates", 6801 /* ING_FLEX_CTR_COUNTER_TABLE_5_Y */ "Counter Table for flexible counter updates", 6802 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6803 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6804 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6805 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6806 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6807 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6808 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6809 /* ING_FLEX_CTR_COUNTER_TABLE_6_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6810 /* ING_FLEX_CTR_COUNTER_TABLE_6_X */ "Counter Table for flexible counter updates", 6811 /* ING_FLEX_CTR_COUNTER_TABLE_6_Y */ "Counter Table for flexible counter updates", 6812 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6813 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6814 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6815 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6816 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6817 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6818 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6819 /* ING_FLEX_CTR_COUNTER_TABLE_7_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6820 /* ING_FLEX_CTR_COUNTER_TABLE_7_X */ "Counter Table for flexible counter updates", 6821 /* ING_FLEX_CTR_COUNTER_TABLE_7_Y */ "Counter Table for flexible counter updates", 6822 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6823 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6824 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6825 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6826 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6827 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6828 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6829 /* ING_FLEX_CTR_COUNTER_TABLE_8_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6830 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE0 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6831 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE1 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6832 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE2 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6833 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE3 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6834 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE4 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6835 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE5 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6836 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE6 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6837 /* ING_FLEX_CTR_COUNTER_TABLE_9_PIPE7 */ "Counter Table for flexible counter updates. All sources in the Ingress Pipeline including the IFP can update these counters.", 6838 /* ING_FLEX_CTR_OFFSET_TABLE_0 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6839 /* ING_FLEX_CTR_OFFSET_TABLE_1 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6840 /* ING_FLEX_CTR_OFFSET_TABLE_2 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6841 /* ING_FLEX_CTR_OFFSET_TABLE_3 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6842 /* ING_FLEX_CTR_OFFSET_TABLE_4 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6843 /* ING_FLEX_CTR_OFFSET_TABLE_5 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6844 /* ING_FLEX_CTR_OFFSET_TABLE_6 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6845 /* ING_FLEX_CTR_OFFSET_TABLE_7 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6846 /* ING_FLEX_CTR_OFFSET_TABLE_8 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6847 /* ING_FLEX_CTR_OFFSET_TABLE_9 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6848 /* ING_FLEX_CTR_OFFSET_TABLE_10 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6849 /* ING_FLEX_CTR_OFFSET_TABLE_11 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6850 /* ING_FLEX_CTR_OFFSET_TABLE_12 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6851 /* ING_FLEX_CTR_OFFSET_TABLE_13 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6852 /* ING_FLEX_CTR_OFFSET_TABLE_14 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6853 /* ING_FLEX_CTR_OFFSET_TABLE_15 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6854 /* ING_FLEX_CTR_OFFSET_TABLE_16 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6855 /* ING_FLEX_CTR_OFFSET_TABLE_17 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6856 /* ING_FLEX_CTR_OFFSET_TABLE_18 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6857 /* ING_FLEX_CTR_OFFSET_TABLE_19 */ "The actual offset used to index the counter table in the first counter pool is stored in this table", 6858 /* ING_FLEX_CTR_PKT_PRI_MAP */ "PKT PRI mapping function for ingress flex counters", 6859 /* ING_FLEX_CTR_PKT_RES_MAP */ "PKT_RES mapping function for ingress flex counters", 6860 /* ING_FLEX_CTR_PORT_MAP */ "PORT mapping function for ingress flex counters", 6861 /* ING_FLEX_CTR_PRI_CNG_MAP */ "PRI & CNG mapping function for ingress flex counters", 6862 /* ING_FLEX_CTR_TOS_MAP */ "TOS mapping function for ingress flex counters", 6863 /* ING_HIGIG_TRUNK_OVERRIDE_PROFILE */ "Higig Trunk Override Profile Pointer.", 6864 /* ING_IDB_TO_DEVICE_PORT_MAP */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6865 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE0 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6866 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE1 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6867 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE2 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6868 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE3 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6869 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE4 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6870 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE5 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6871 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE6 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6872 /* ING_IDB_TO_DEVICE_PORT_MAP_PIPE7 */ "Ingress IDB Port Number to Local Device Port Number Mapping Table. Indexed by the idb port number, and provides the corresponding local device port number.", 6873 /* ING_IDB_TO_DEVICE_PORT_NUMBER_MAPPING_TABLE */ "Ingress IDB to Device Port Number Mapping Table. Indexed by the IDB port number, and provides the corresponding device port number.", 6874 /* ING_IDB_TO_DEVICE_PORT_NUMBER_MAPPING_TABLE_PIPE0 */ "Ingress IDB to Device Port Number Mapping Table. Indexed by the IDB port number, and provides the corresponding device port number.", 6875 /* ING_IDB_TO_DEVICE_PORT_NUMBER_MAPPING_TABLE_PIPE1 */ "Ingress IDB to Device Port Number Mapping Table. Indexed by the IDB port number, and provides the corresponding device port number.", 6876 /* ING_IDB_TO_DEVICE_PORT_NUMBER_MAPPING_TABLE_PIPE2 */ "Ingress IDB to Device Port Number Mapping Table. Indexed by the IDB port number, and provides the corresponding device port number.", 6877 /* ING_IDB_TO_DEVICE_PORT_NUMBER_MAPPING_TABLE_PIPE3 */ "Ingress IDB to Device Port Number Mapping Table. Indexed by the IDB port number, and provides the corresponding device port number.", 6878 /* ING_IPFIX_DSCP_XLATE_TABLE */ "IPFIX DSCP Translation Table -- Address = {IP_DSCP_PROFILE[1:0], pkt_dscp[5:0]}", 6879 /* ING_IPFIX_EOP_BUFFER */ "IPFIX EOP BUFFER - to save info per-port from SOP cells to EOP cells.", 6880 /* ING_IPFIX_EXPORT_FIFO */ "Ingress IPFIX Export FIFO", 6881 /* ING_IPFIX_FLOW_RATE_METER_TABLE */ "IPFIX Flow Rate Meter Table", 6882 /* ING_IPFIX_IPV4_MASK_SET_A */ "IPFIX IPv4 Address Masks", 6883 /* ING_IPFIX_IPV4_MASK_SET_B */ "IPFIX IPv4 Address Masks", 6884 /* ING_IPFIX_IPV6_MASK_SET_A */ "IPFIX IPv6 Address Masks", 6885 /* ING_IPFIX_IPV6_MASK_SET_B */ "IPFIX IPv6 Address Masks", 6886 /* ING_IPFIX_PROFILE */ "Ingress IPFIX Per-Port Profile Pointers, FeatureSpecific-FP", 6887 /* ING_IPFIX_SESSION_TABLE */ "Ingress IPFIX Session Table", 6888 /* ING_IPV6_MC_RESERVED_ADDRESS */ "Ingress IPV6 Multicast Reserved Address table.", 6889 /* ING_L3_NEXT_HOP */ "Reduced version of L3_NEXT_HOP table. Used to provide just mod and port/TGID", 6890 /* ING_L3_NEXT_HOP_A */ "Physical view of first copy of ING_L3_NEXT_HOP - contains all fields.", 6891 /* ING_L3_NEXT_HOP_ATTRIBUTE_1 */ "index by ING_L3_NEXT_HOP_ATTRIBUTE_1_INDEX.INDEX or ING_L3_NEXT_HOP.DVP_ATTRIBUTE_1_INDEX .", 6892 /* ING_L3_NEXT_HOP_ATTRIBUTE_1_INDEX */ "index by ING_L3_NEXT_HOP.L3_OIF or ipmc_index or VID.", 6893 /* ING_L3_NEXT_HOP_B */ "Physical view of second copy of ING_L3_NEXT_HOP - contains a subset of fields.", 6894 /* ING_LM_COUNTER_CONTROL */ "Per opcode OAM LM packets counter control.", 6895 /* ING_LOOPBACK_DROP_VECTOR_MASK */ "mask for drop_vector.", 6896 /* ING_MOD_MAP_TABLE */ "Ingress Module Remapping Table", 6897 /* ING_MPLS_ENTRY_ACTION_TABLE_A */ "Remapping Table for Ingress MPLS_ENTRY Hash (Key+1).", 6898 /* ING_MPLS_ENTRY_ACTION_TABLE_B */ "Remapping Table for Ingress MPLS_ENTRY Hash (Key+1).", 6899 /* ING_MPLS_ENTRY_REMAP_TABLE_A */ "Remapping Table for Ingress MPLS Entry 0 Hash (Key+1).", 6900 /* ING_MPLS_ENTRY_REMAP_TABLE_B */ "Remapping Table for Ingress MPLS ENTRY 1 Hash (Key+1).", 6901 /* ING_MPLS_EXP_MAPPING */ "EXP to Internal Priority and Color Maping table. Address = {EXP_MAPPING_PTR, EXP}", 6902 /* ING_MPLS_EXP_MAPPING_1 */ "shows how the Label.PHB is derived from Label.EXP or MPLS.NEW_PRI for Uniform and Pipe model respectively.", 6903 /* ING_MPLS_INHERIT_TABLE */ "Copy-to-cpu and Drop Control for 1588 packets of different message types.", 6904 /* ING_MTU_CHECK_1 */ "TSN_CIRCUIT_ID MTU check mapping table.", 6905 /* ING_MTU_CHECK_2 */ "SR_FLOW_ID MTU check mapping table.", 6906 /* ING_NETWORK_PRUNE_CONTROL */ "ING_NETWORK_PRUNE_CONTROL Indexed by SVP NETWORK_GROUP.", 6907 /* ING_NLF_PORT_MAP */ "Map NLF ID to LOGICAL Port Number, index by LOOPBACK_PACKET_TYPE", 6908 /* ING_OAM_DGLP_PROFILE */ ".", 6909 /* ING_OAM_FLEXIBLE_DOMAIN_CONTROL */ "index:{INNER PRIORITY TAGGED,PRE VXLT IVID VALID,PRE VXLT OVID VALID,POST VXLT IVID VALID,POST VXLT OVID VALID,SVP VALID}", 6910 /* ING_OAM_LM_COUNTERS_0 */ "Packet counter for OAM Loss Measurement pool 0", 6911 /* ING_OAM_LM_COUNTERS_1 */ "Packet counter for OAM Loss Measurement pool 0", 6912 /* ING_OAM_LM_COUNTERS_2 */ "Packet counter for OAM Loss Measurement pool 0", 6913 /* ING_OUTER_DOT1P_MAPPING_TABLE */ "Outer Dot1p mapping table, used to mark traffic from non-QCN-aware sources with a dot1p value that does not map to QCN-aware queues. The PORT_TABLE/SVP/VFI tables select the profile, and the {cfi,got1p[2:0]} value selects one of 16 entries.", 6914 /* ING_PHYSICAL_PORT_TABLE */ "Port Table, FeatureSpecific-Ethernet.", 6915 /* ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLE */ "Ingress Physical to Logical Port Number Mapping Table. Indexed by the Physical port number, and provides the corresponding logical port number.", 6916 /* ING_PHY_TO_IDB_PORT_MAP */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the physical port number, and provides the corresponding idb port number.", 6917 /* ING_PHY_TO_IDB_PORT_MAP_PIPE0 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the physical port number, and provides the corresponding idb port number.", 6918 /* ING_PHY_TO_IDB_PORT_MAP_PIPE1 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the physical port number, and provides the corresponding idb port number.", 6919 /* ING_PHY_TO_IDB_PORT_MAP_PIPE2 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the physical port number, and provides the corresponding idb port number.", 6920 /* ING_PHY_TO_IDB_PORT_MAP_PIPE3 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the physical port number, and provides the corresponding idb port number.", 6921 /* ING_PHY_TO_IDB_PORT_MAP_PIPE4 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the {PM instance, offset}, and provides the corresponding idb port number.", 6922 /* ING_PHY_TO_IDB_PORT_MAP_PIPE5 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the {PM instance, offset}, and provides the corresponding idb port number.", 6923 /* ING_PHY_TO_IDB_PORT_MAP_PIPE6 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the {PM instance, offset}, and provides the corresponding idb port number.", 6924 /* ING_PHY_TO_IDB_PORT_MAP_PIPE7 */ "Ingress Physical to IDB Port Number Mapping Table. Indexed by the {PM instance, offset}, and provides the corresponding idb port number.", 6925 /* ING_PORT_THROTTLE_ENABLE */ "Table to enable Ingress Port Throttling on physical ports.", 6926 /* ING_PRI_CNG_MAP */ "Per port ingress priority/CFI mapping table", 6927 /* ING_PW_TERM_COUNTERS */ "Pseudo-wire Termination Byte counter - index by PW number", 6928 /* ING_PW_TERM_SEQ_NUM */ "Pseudo-wire Termination Sequence Number - index by PW number", 6929 /* ING_PW_TERM_SEQ_NUM_PIPE0 */ "Pseudo-wire Termination Sequence Number - index by PW number. Packets from X and Y ingress pipes are independent of each other.", 6930 /* ING_PW_TERM_SEQ_NUM_PIPE1 */ "Pseudo-wire Termination Sequence Number - index by PW number. Packets from X and Y ingress pipes are independent of each other.", 6931 /* ING_PW_TERM_SEQ_NUM_PIPE2 */ "Pseudo-wire Termination Sequence Number - index by PW number. Packets from X and Y ingress pipes are independent of each other.", 6932 /* ING_PW_TERM_SEQ_NUM_PIPE3 */ "Pseudo-wire Termination Sequence Number - index by PW number. Packets from X and Y ingress pipes are independent of each other.", 6933 /* ING_PW_TERM_SEQ_NUM_X */ "Pseudo-wire Termination Sequence Number - index by PW number.", 6934 /* ING_PW_TERM_SEQ_NUM_Y */ "Pseudo-wire Termination Sequence Number - index by PW number.", 6935 /* ING_QUEUE_MAP */ "New table for Flex Queueing", 6936 /* ING_QUEUE_OFFSET_MAPPING_TABLE */ "New table for Flex Queueing", 6937 /* ING_ROUTED_INT_PRI_MAPPING */ "Internal priority mapping table, used to steer traffic from non-QCN-aware sources away from QCN queues.", 6938 /* ING_RX_COUNTER */ "Counts number over this port, Index: Preemptable_frame, Ingress Port.", 6939 /* ING_SAT_SAMP_DATA */ "Service Activation Detection ACTION-DATA for DOWNMEPs", 6940 /* ING_SAT_SAMP_TCAM */ "Service Activation Detection TCAM for DOWNMEPs", 6941 /* ING_SERVICE_COUNTER_TABLE */ "Ingress Service Interface Counters", 6942 /* ING_SERVICE_COUNTER_TABLE_X */ "Ingress Service Interface Counters.", 6943 /* ING_SERVICE_COUNTER_TABLE_Y */ "Ingress Service Interface Counters.", 6944 /* ING_SERVICE_PRI_MAP */ "Ingress Class of Service instance priority value to OAM LM counter offset mapping table", 6945 /* ING_SERVICE_PRI_MAP_0 */ "Ingress Class of Service instance priority value to OAM LM counter offset mapping table", 6946 /* ING_SERVICE_PRI_MAP_1 */ "Ingress Class of Service instance priority value to OAM LM counter offset mapping table", 6947 /* ING_SERVICE_PRI_MAP_2 */ "Ingress Class of Service instance priority value to OAM LM counter offset mapping table", 6948 /* ING_SER_FIFO */ "ING SER FIFO. FIFO containing the parity error logging information in IPIPE.", 6949 /* ING_SER_FIFO_PIPE0 */ "ING SER FIFO", 6950 /* ING_SER_FIFO_PIPE1 */ "ING SER FIFO", 6951 /* ING_SER_FIFO_PIPE2 */ "ING SER FIFO", 6952 /* ING_SER_FIFO_PIPE3 */ "ING SER FIFO", 6953 /* ING_SER_FIFO_PIPE4 */ "ING SER FIFO", 6954 /* ING_SER_FIFO_PIPE5 */ "ING SER FIFO", 6955 /* ING_SER_FIFO_PIPE6 */ "ING SER FIFO", 6956 /* ING_SER_FIFO_PIPE7 */ "ING SER FIFO", 6957 /* ING_SER_FIFO_X */ "ING SER FIFO", 6958 /* ING_SER_FIFO_Y */ "ING SER FIFO", 6959 /* ING_SNAT */ "Ingress SNAT Lookup.", 6960 /* ING_SNAT_DATA_ONLY */ "ING_SNAT Data SRAM for ING_SNAT TCAM.", 6961 /* ING_SNAT_HIT_ONLY */ "hit bit for ING_SNAT TCAM.", 6962 /* ING_SNAT_HIT_ONLY_X */ "hit bit for ING_SNAT TCAM.", 6963 /* ING_SNAT_HIT_ONLY_Y */ "hit bit for ING_SNAT TCAM.", 6964 /* ING_SNAT_ONLY */ "ING_SNAT TCAM only view.", 6965 /* ING_SVM_PKT_PRI_MAP */ "PKT_PRI_MAP", 6966 /* ING_SVM_PKT_RES_MAP */ "PKT_RES_MAP", 6967 /* ING_SVM_PORT_MAP */ "PORT_MAP", 6968 /* ING_SVM_PRI_CNG_MAP */ "PRI_CNG_MAP", 6969 /* ING_SVM_TOS_MAP */ "TOS_MAP", 6970 /* ING_TRILL_ADJACENCY */ "Ingress TRILL Adjacency Register.", 6971 /* ING_TRILL_PARSE_CONTROL */ "Trill parse control.", 6972 /* ING_TRILL_PAYLOAD_PARSE_CONTROL */ "Trill parse control.", 6973 /* ING_TUNNEL_ECN_DECAP */ "Ingress ECN Tunnel Decap Control Register.", 6974 /* ING_TUNNEL_ECN_DECAP_2 */ "Ingress ECN Tunnel Decap Control Register #2.", 6975 /* ING_UNTAGGED_PHB */ "Table used to derive untagged packet's PHB.", 6976 /* ING_VFT_PRI_MAP */ "To derive the pri field of the VSAN tag.", 6977 /* ING_VINTF_COUNTER_TABLE */ "Ingress Virtual Port / Interface Counters", 6978 /* ING_VINTF_COUNTER_TABLE_X */ "Ingress Virtual Port / Interface Counters.", 6979 /* ING_VINTF_COUNTER_TABLE_Y */ "Ingress Virtual Port / Interface Counters.", 6980 /* ING_VLAN_COUNTER_PRI_COS_MAP */ "VLAN_COUNTER PRI_COS mapping.", 6981 /* ING_VLAN_COUNTER_TABLE */ "IVXLT action counter.", 6982 /* ING_VLAN_RANGE */ "vlan range match table", 6983 /* ING_VLAN_TAG_ACTION_PROFILE */ "ACTIONS for the VXLT stage", 6984 /* ING_VLAN_TAG_ACTION_PROFILE_1 */ "This table determins how VLAN tags are processed prior to forwarding lookup and specifies the actions for VP stage.", 6985 /* ING_VLAN_TAG_ACTION_PROFILE_2 */ "This table determins how VLAN tags are processed prior to forwarding lookup and specifies the actions for VXLT2 stage.", 6986 /* ING_VLAN_VFI_MEMBERSHIP */ "Ingress VLAN VFI member table.", 6987 /* ING_VP_VLAN_MEMBERSHIP */ "Ingress VP VLAN member table.", 6988 /* ING_VP_VLAN_MEMBERSHIP_ACTION_A */ "Action of whether to prepend/append data from remap table to the key into hash A of ING_VP_VLAN_MEMBERSHIP table.", 6989 /* ING_VP_VLAN_MEMBERSHIP_ACTION_B */ "Action of whether to prepend/append data from remap table to the key into hash B of ING_VP_VLAN_MEMBERSHIP table.", 6990 /* ING_VP_VLAN_MEMBERSHIP_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6991 /* ING_VP_VLAN_MEMBERSHIP_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6992 /* ING_VP_VLAN_MEMBERSHIP_ECC */ "ECC Table for Ingress VP VLAN Member Table.", 6993 /* ING_VP_VLAN_MEMBERSHIP_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 6994 /* ING_VP_VLAN_MEMBERSHIP_KEY_ATTRIBUTES */ "Key Attributes Table.", 6995 /* ING_VP_VLAN_MEMBERSHIP_REMAP_A */ "Remapping table for hash key into hash A of ING_VP_VLAN_MEMBERSHIP table.", 6996 /* ING_VP_VLAN_MEMBERSHIP_REMAP_B */ "Remapping table for hash key into hash B of ING_VP_VLAN_MEMBERSHIP table.", 6997 /* ING_VP_VLAN_MEMBERSHIP_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6998 /* ING_VP_VLAN_MEMBERSHIP_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 6999 /* ING_VSAN */ "VSAN attributes", 7000 /* ING_VXLAN_CLASS_ID_POLICY_TABLE */ "POLICY TABLE FOR ING_VXLAN_CLASS_ID_TCAM", 7001 /* ING_VXLAN_CLASS_ID_TCAM */ "TCAM FOR ING_VXLAN_CLASS_ID", 7002 /* ING_VXLT_ACTION_TABLE_A */ "Remapping Table for Ingress VXLT Hash (Key+1).", 7003 /* ING_VXLT_ACTION_TABLE_B */ "Remapping Table for Ingress VXLT Hash (Key+1).", 7004 /* ING_VXLT_REMAP_TABLE_A */ "Remapping Table for Ingress VXLT Hash (Key+1).", 7005 /* ING_VXLT_REMAP_TABLE_B */ "Remapping Table for Ingress VXLT Hash (Key+1).", 7006 /* INITIAL_ING_L3_NEXT_HOP */ "Reduced version of L3_NEXT_HOP table. Used to provide just mod and port/TGID", 7007 /* INITIAL_L3_ECMP */ "Initial L3 Equal Cost Multipath table", 7008 /* INITIAL_L3_ECMP_COUNT */ "Contains the number of members in each ECMP group. Used with ECMP_pointer Group Propertis - indexed by ECMP group number from LPM table", 7009 /* INITIAL_L3_ECMP_GROUP */ "Contains the number of members in each ECMP group and the ECMP base pointer. It is indexed by ECMP group number from LPM table.", 7010 /* INITIAL_L3_ECMP_X */ "Initial L3 Equal Cost Multipath table.", 7011 /* INITIAL_L3_ECMP_Y */ "Initial L3 Equal Cost Multipath table.", 7012 /* INITIAL_PROT_GROUP_TABLE */ "Protection Switching (backup path) Next Hop Table", 7013 /* INITIAL_PROT_NHI_DOUBLE_WIDE_TABLE */ "Protection Switching (backup path) Next Hop Table.", 7014 /* INITIAL_PROT_NHI_TABLE */ "Protection Switching (backup path) Next Hop Table", 7015 /* INITIAL_PROT_NHI_TABLE_1 */ "Protection Switching (backup path) Next Hop Table.", 7016 /* INITIAL_PROT_NHI_TABLE_1_DMA */ "DMA view of INITIAL_PROT_NHI_TABLE_1", 7017 /* INITIAL_PROT_OFFSET_TABLE */ "Protection Switching (backup path) Next Hop Table.", 7018 /* INSTRUMENTATION_TRIGGERS_ENABLE */ "Bitmap Enable for Instrumentation trigger", 7019 /* INT_CN_TO_MMUIF_MAPPING */ "Mapping for INT_CN to MMU CN.", 7020 /* INT_PRI_STRENGTH_PROFILE */ "INT_PRI Strength Profile.", 7021 /* INT_TURNAROUND_EN_BMAP */ "Enable INT turnaround if PORT_BITMAP[EgressPort] = 1.", 7022 /* IPMC_VLAN_TBL0 */ "First physical copy of MMU_IPMC_VLAN_TBL", 7023 /* IPMC_VLAN_TBL1 */ "Second physical copy of MMU_IPMC_VLAN_TBL", 7024 /* IPORT_TABLE */ "Port Table", 7025 /* IPPA_DESIGNATED_VLAN_TABLE */ "This table hold 8 designated VLANs, per pp-port designated-vlan index.\n Used twice, first for stage 1 and second for one of the stages 2B-3B", 7026 /* IPPA_FWD_DOMAIN_CS_PROFILE_MAP */ "map the vsi_profile to cs_vsi_profile", 7027 /* IPPA_INGRESS_VLAN_EDIT_COMMAND_TABLE_1 */ "accessed with Packet-Is-MEF-L2CP(1), LLVP-Incoming-Tag-Structure (5), AC-VLAN-Edit-Profile 5:3 and chose inside the entry with AC-VLAN-Edit-Profile2:0", 7028 /* IPPA_LEARN_PAYLOAD_CONTEXT_MAPPING */ "Used for learning procedure", 7029 /* IPPA_LIF_PROFILE_ATTRIBUTES_0 */ "Lif.Profile Attributes", 7030 /* IPPA_LIF_PROFILE_ATTRIBUTES_1 */ "Lif.Profile Attributes", 7031 /* IPPA_MAP_CTX_TO_SAVED_CONTEXT_PROFILE */ "Map Context to Saved Context profile", 7032 /* IPPA_MAP_PORT_TO_MEMBERSHIP_IF_VEC */ "This table hold Vlan-Member-Ship-Interface per port.", 7033 /* IPPA_MAP_RIF_PROFILE_TO_ROUTING_ENABLE */ "This table is accessed with the In-Rif-Profile. Each line holds bitmap vector which map Ethernet.Qualifier-Next-Protocol,IP-Qualifier.Is-Mc to enable bit.", 7034 /* IPPA_MAP_VSI_MAC_PREFIX_TO_DA_MSB_1 */ "Map VSI.My-Mac-Prefix(6) to My-Mac-Prefix 38 bits, By this way My-Vsi-Da is equla to My-Mac-Prefix 47:10 VSI.My-MAC-Lsb9:0", 7035 /* IPPA_MEM_AC40000 */ "INTERNAL", 7036 /* IPPA_MEM_AC60000 */ "INTERNAL", 7037 /* IPPA_MEM_F000000 */ "INTERNAL", 7038 /* IPPA_ROUTING_PROFILE_TABLE */ "This table is accessed with the In-Rif-Profile. Routing profile pointer", 7039 /* IPPA_TERMINATION_PROFILE_TABLE */ "Accessed with Lif.Terminaiton profile", 7040 /* IPPA_VD_TO_VLAN_CLASSIFICATION_PROFILE */ "Map Vlan Domain To vlan classifiaction profile which is used in the llvp table", 7041 /* IPPA_VLAN_EDIT_PCP_DEI_MAP */ "Accessed by PCP-DEI-Map-Profile3:0 Incoming-Tag.PCP-DEI(4).\n 6 Msb used for Table Address and 2 LSB for Entry resolution", 7042 /* IPPA_VLAN_MEMBERSHIP_IF_ATTR */ "Used for ethernet procedure", 7043 /* IPPA_VLAN_MEMBERSHIP_TABLE_1 */ "This table holds a bit per Initial-VID, VlanDomainIf for the VLAN-Port membership. Table is accessed with Initial-VID, and each line holds one bit per pp-port.\n Used twice, first for stage 1 and second for one of the stages 2B-3B", 7044 /* IPPA_VLAN_RANGE_COMPRESSION_TABLE_1 */ "Used twice, first for stage 1 and second for one of the stages 2B-3B", 7045 /* IPPA_VRID_DA_PROFILE_ATTR_1 */ "DA-Profile is mapped to Trap-Enable & Layer-Index-Offset(3) & Ethernet-offset(5) Internal-Offset(6) & Mask(32)", 7046 /* IPPA_VRID_MY_MAC_MAPPING_1 */ "DA-Profile is mapped to FFC, Kbr, FormatIdx", 7047 /* IPPA_VRID_MY_MAC_TCAM_1 */ "TCAM interface for vrid based my-mac.", 7048 /* IPPA_VSI_FORMAT_CONFIGURATION_TABLE_1 */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7049 /* IPPA_VSI_PREFIX_INDEX_TABLE_1 */ "A list of prefixes, each line is a possible prefix.", 7050 /* IPPA_VSI_PROFILE_ATTRIBUTES_0 */ "If VSI-Profile10 is unset then Map VSI-Profile(9) to Learn-Key-Context", 7051 /* IPPA_VSI_PROFILE_ATTRIBUTES_1 */ "If VSI-Profile10 is set then Map VSI-Profile(9) to Learn-Key-Context", 7052 /* IPPA_VTA_CONTEXT_SEL_TCAM */ "Context selection is relevant for first stage", 7053 /* IPPA_VTA_LIF_STATISTIC_DATA_FIFO */ "FIFO for packet data waiting for the Dbs results", 7054 /* IPPA_VTA_VSI_STATISTIC_DATA_FIFO */ "statistics fifo", 7055 /* IPPA_VTB_LIF_STATISTIC_DATA_FIFO */ "statistics fifo", 7056 /* IPPA_VTC_LIF_STATISTIC_DATA_FIFO */ "statistics fifo", 7057 /* IPPA_VTDCS_ACTION */ "VtdcsAction", 7058 /* IPPA_VTDCS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7059 /* IPPA_VTDCS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7060 /* IPPA_VTDCS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7061 /* IPPA_VTDCS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7062 /* IPPA_VTDCS_TCAM_HIT_INDICATION */ "VtdcsTcamHitIndication", 7063 /* IPPA_VTD_LIF_STATISTIC_DATA_FIFO */ "statistics fifo", 7064 /* IPPA_VTD_LOOKUP_ACCESS_LOOKUP_FIFO_0 */ "FIFO for packet data waiting for the Dbs results", 7065 /* IPPA_VTD_LOOKUP_ACCESS_LOOKUP_FIFO_1 */ "FIFO for packet data waiting for the Dbs results", 7066 /* IPPA_VTD_LOOKUP_ACCESS_LOOKUP_FIFO_2 */ "FIFO for packet data waiting for the Dbs results", 7067 /* IPPA_VTD_LOOKUP_ACCESS_LOOKUP_FIFO_3 */ "FIFO for packet data waiting for the Dbs results", 7068 /* IPPA_VTD_POST_GENERAL_DATA_FIFO */ "FIFO for packet data waiting for the Dbs results", 7069 /* IPPA_VTECS_ACTION */ "VtecsAction", 7070 /* IPPA_VTECS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7071 /* IPPA_VTECS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7072 /* IPPA_VTECS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7073 /* IPPA_VTECS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7074 /* IPPA_VTECS_TCAM_HIT_INDICATION */ "VtecsTcamHitIndication", 7075 /* IPPA_VTE_LIF_STATISTIC_DATA_FIFO */ "statistics fifo", 7076 /* IPPA_VTE_LOOKUP_ACCESS_LOOKUP_FIFO_0 */ "FIFO for packet data waiting for the Dbs results", 7077 /* IPPA_VTE_LOOKUP_ACCESS_LOOKUP_FIFO_1 */ "FIFO for packet data waiting for the Dbs results", 7078 /* IPPA_VTE_LOOKUP_ACCESS_LOOKUP_FIFO_2 */ "FIFO for packet data waiting for the Dbs results", 7079 /* IPPA_VTE_LOOKUP_ACCESS_LOOKUP_FIFO_3 */ "FIFO for packet data waiting for the Dbs results", 7080 /* IPPA_VTE_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 7081 /* IPPA_VTE_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 7082 /* IPPA_VTE_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 7083 /* IPPA_VTE_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 7084 /* IPPA_VTE_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 7085 /* IPPA_VTE_POST_GENERAL_DATA_FIFO */ "FIFO for packet data waiting for the Dbs results", 7086 /* IPPA_VTT_CONTEXT_SEL_TCAM */ "Context selection is relevant for 4 last stages", 7087 /* IPPA_VTT_CURRENT_CONTEXT_PROFILE_MAP */ "maps context to context profile", 7088 /* IPPA_VTT_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7089 /* IPPA_VTT_INIT_CONTEXT_ENABLERS */ "This table is accessed with the Current Context. Each line holds Enablers & profile", 7090 /* IPPA_VTT_IN_PP_PORT_CONFIG */ "This table holds VLAN translation and tunnel termination In-PP-Port configurations.\n Used twice, first for stage 1 and second for one of the stages 2A-2B", 7091 /* IPPA_VTT_LAYER_RECORDS_CRC_FIFO_0 */ "crc fifo", 7092 /* IPPA_VTT_LAYER_RECORDS_CRC_FIFO_1 */ "crc fifo", 7093 /* IPPA_VTT_LLVP */ "Link layer VLAN processing table. This table has 1024 entries, and the index into the table is In-PP-Port.VLAN-Classification-Profile (3b), Is-Priority, Packet-Format-Qualifier1.Ethernet-Tag-Format (6). Each entry includes information on the matcing VLAN tag and how it should be processed.", 7094 /* IPPA_VTT_MPLS_LABEL_RANGE_TABLE */ "This table hold 8 Mpls Labels ranges and the range attributes.", 7095 /* IPPA_VTT_PATH_SELECT */ "This table maps a In-LIF.Protection-Pointer to a protection path selection. The table has 4K entries. Each entry indicates if an odd or even protection path should be taken (in case of protection).\n If Path-SelectProtection-Pointeridx* is not equal Protection-Path then do trap", 7096 /* IPPA_VTT_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 7097 /* IPPA_VTT_RES_CONTEXT_ENABLERS */ "This table is accessed with the Current Context. Each line holds Enablers & profile", 7098 /* IPPA_VTT_ST_TH_LE_CONTEXT_CONSTANT_VALUES */ "Used for key constructions", 7099 /* IPPA_VTT_ST_TH_LE_CONTROL_MEM */ "FIFO for tcam lookup result", 7100 /* IPPA_VTT_ST_TH_LE_FFC_CMD_BITS_FROM_HEADER */ "Load chunk selection instructions", 7101 /* IPPA_VTT_ST_TH_LE_FFC_CMD_BITS_FROM_LAYER_RECORDS */ "Load chunk selection instructions", 7102 /* IPPA_VTT_ST_TH_LE_FFC_CMD_BITS_FROM_RELATIVE_HEADER */ "Load chunk selection instructions", 7103 /* IPPA_VTT_ST_TH_LE_FFC_CMD_LITERALLTY */ "Load chunk selection instructions", 7104 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_0_QUAD_0 */ "Group0 Quad0 configuration", 7105 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_0_QUAD_CONTEXT_SELECTOR */ "Indicates per 4 FSL what is the context that controls them", 7106 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_1_QUAD_0 */ "Group1 Quad0 configuration", 7107 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_1_QUAD_CONTEXT_SELECTOR */ "Indicates per 4 FSL what is the context that controls them", 7108 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_2_QUAD */ "Group2 Quad0 configuration", 7109 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_2_QUAD_CONTEXT_SELECTOR */ "Indicates per 4 FSL what is the context that controls them", 7110 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_3_QUAD_0 */ "Group3 Quad0 configuration", 7111 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_3_QUAD_1 */ "Group3 Quad1 configuration", 7112 /* IPPA_VTT_ST_TH_LE_FFC_GROUP_3_QUAD_CONTEXT_SELECTOR */ "Indicates per 4 FSL what is the context that controls them", 7113 /* IPPA_VTT_ST_TH_LE_KBR */ "kbr0: key0\n kbr1: key1\n kbr2: if0_isemc\n kbr3: if1_isemc\n kbr4: if2_sexem\n kbr5: if2_tcam", 7114 /* IPPA_VTT_ST_TH_LE_KEY_BUILDER_CONTEXT_SELECTOR */ "Indicates per Key-Builder what is the context that controls it", 7115 /* IPPA_VTT_ST_TH_LE_KLEAP_LKP_FFC_INSTRUCTION */ "Ffc instruction", 7116 /* IPPA_VTT_ST_TH_LE_LATENCY_FIFO_MEM */ "FIFO for tcam lookup result", 7117 /* IPPA_VTT_ST_TH_LE_LATENCY_FIFO_MEM_2 */ "FIFO for tcam lookup result", 7118 /* IPPA_VTT_ST_TH_LE_LATENCY_FIFO_MEM_3 */ "FIFO for tcam lookup result", 7119 /* IPPA_VTT_ST_TH_LE_LATENCY_FIFO_MEM_4 */ "FIFO for tcam lookup result", 7120 /* IPPA_VTT_ST_TH_LE_LATENCY_FIFO_MEM_5 */ "FIFO for tcam lookup result", 7121 /* IPPA_VTT_ST_TH_LE_PD_0 */ "Used as FPD1", 7122 /* IPPA_VTT_ST_TH_LE_PD_1 */ "Used as FPD0", 7123 /* IPPA_VTT_ST_TH_LE_PD_2 */ "Used as VTE priority_decoder_fwd_domain_result", 7124 /* IPPA_VTT_ST_TH_LE_PD_3 */ "Used as VTE priority_decoder_tt_result", 7125 /* IPPA_VTT_ST_TH_LE_PD_4 */ "Used as VTD priority_decoder_fwd_domain_result", 7126 /* IPPA_VTT_ST_TH_LE_PD_5 */ "Used as VTD priority_decoder_tt_result", 7127 /* IPPA_VTT_ST_TH_LE_PD_0_CONTEXT_TO_PROFILES_DATA */ "Used as FPD1", 7128 /* IPPA_VTT_ST_TH_LE_PD_1_CONTEXT_TO_PROFILES_DATA */ "Used as FPD0", 7129 /* IPPA_VTT_ST_TH_LE_PD_2_CONTEXT_TO_PROFILES_DATA */ "Used as VTE priority_decoder_fwd_domain_result", 7130 /* IPPA_VTT_ST_TH_LE_PD_3_CONTEXT_TO_PROFILES_DATA */ "Used as VTE priority_decoder_tt_result", 7131 /* IPPA_VTT_ST_TH_LE_PD_4_CONTEXT_TO_PROFILES_DATA */ "Used as VTD priority_decoder_fwd_domain_result", 7132 /* IPPA_VTT_ST_TH_LE_PD_5_CONTEXT_TO_PROFILES_DATA */ "Used as VTD priority_decoder_tt_result", 7133 /* IPPA_VTT_S_2A_VSI_LKUP_FIFO_PIPE */ "FIFO for packet data waiting for the Dbs results", 7134 /* IPPA_VTT_USER_GENERAL_CONTAINER_CFG */ "contains a 3b code per container:\n 3'd0: don't override\n 3'd1: override with PD0\n 3'd2: override with PD1\n 3'd3: override with FPD0\n 3'd4: override with FPD1\n 3'd5: override with DE0\n 3'd6: override with DE1\n Containers:\n 0,1 24b\n 2,3 40b\n 4 96b\n 5 160b", 7135 /* IPPA_VTT_VLAN_DOMAIN_ATTRIBUTES_1 */ "This table holds the VLAN range compression selection per vlan domain\n Used twice, first for stage 1 and second for one of the stages 2B-3B", 7136 /* IPPA_VTX_VSI_STATISTIC_DATA_FIFO */ "statistics fifo", 7137 /* IPPB_ACCEPTED_ARR_FORMAT_CONFIG */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7138 /* IPPB_APP_DB_MAP */ "maps app_db to context_type. Encoded with leading one.", 7139 /* IPPB_ELK_ACL_ALIGNER_MAPPING_MEM */ "contains 3 values for the size of the the 3 msb keys used in the ELK master key construction - byte aligned", 7140 /* IPPB_ELK_ALIGNER_MAPPING_MEM */ "contains 3 values for the size of the the 3 msb keys used in the ELK master key construction - byte aligned", 7141 /* IPPB_ELK_OPCODE_MAPPING_MEM */ "contains 4k eantris of 8 bit opcode - 4 entries per address in memory", 7142 /* IPPB_ETHERNET_OAM_OPCODE_MAP */ "This table maps Y1731-Header opcode to an OAM opcode and offset configuration. The table has 256 entries, with the index being Y1731-Headers 8-bit Opcode. The value in each entry includes an 4-bit OAM opcode and an OAM offset, used to indicate OAM stamp location in the header.", 7143 /* IPPB_EXPECTED_ARR_FORMAT_CONFIG */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7144 /* IPPB_FFC_CMD_BITS_FROM_HEADER */ "Load chunk selection instructions", 7145 /* IPPB_FFC_CMD_BITS_FROM_LAYER_RECORDS */ "Load chunk selection instructions", 7146 /* IPPB_FFC_CMD_BITS_FROM_RELATIVE_HEADER */ "Load chunk selection instructions", 7147 /* IPPB_FFC_CMD_LITERALLTY */ "Load chunk selection instructions", 7148 /* IPPB_FLPACS_ACTION */ "TCAM action", 7149 /* IPPB_FLPACS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7150 /* IPPB_FLPACS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7151 /* IPPB_FLPACS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7152 /* IPPB_FLPACS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7153 /* IPPB_FLPACS_TCAM_HIT_INDICATION */ "Hit indication memory", 7154 /* IPPB_FLPA_CURRENT_CONTEXT_PROFILE_MAP */ "maps the FWD2 context to a profile for ACL CS", 7155 /* IPPB_FLPA_INIT_CONTEXT_ENABLERS */ "bit per context enabling fixed initial processing logic", 7156 /* IPPB_FLPA_LOOKUP_ACCESS_LOOKUP_FIFO_2 */ "", 7157 /* IPPB_FLPA_LOOKUP_ACCESS_LOOKUP_FIFO_3 */ "", 7158 /* IPPB_FLPA_LOOKUP_ACCESS_LOOKUP_FIFO_4 */ "", 7159 /* IPPB_FLPA_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 7160 /* IPPB_FLPA_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 7161 /* IPPB_FLPA_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 7162 /* IPPB_FLPA_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 7163 /* IPPB_FLPA_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 7164 /* IPPB_FLPA_RES_CONTEXT_ENABLERS */ "FlpaResContextEnablers", 7165 /* IPPB_FLPA_USER_GENERAL_CONTAINER_CFG */ "contains a 3b code per container:\n 4'd0: don't override\n 4'd1: override with PD0\n 4'd2: override with PD1\n 4'd3: override with FPD0\n 4'd4: override with FPD1\n 4'd5: override with DE0\n 4'd6: override with DE1\n 4'd7: overide with PD0 result only\n 4'd8: overide with PD1 result only\n 4'd9: overide with FPD0 result only\n 4'd10: overide with FPD1 result only\n Containers:\n 0,1 24b\n 2,3 40b\n 4 96b\n 5 160b", 7166 /* IPPB_FLPBCS_ACTION */ "TCAM action", 7167 /* IPPB_FLPBCS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7168 /* IPPB_FLPBCS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7169 /* IPPB_FLPBCS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7170 /* IPPB_FLPBCS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7171 /* IPPB_FLPBCS_TCAM_HIT_INDICATION */ "Hit indication memory", 7172 /* IPPB_FLPB_CURRENT_CONTEXT_PROFILE_MAP */ "maps the FWD2 context to a profile for ACL CS", 7173 /* IPPB_FLPB_INIT_CONTEXT_ENABLERS */ "FlpbInitContextEnablers", 7174 /* IPPB_FLPB_LOOKUP_ACCESS_LOOKUP_FIFO_2 */ "", 7175 /* IPPB_FLPB_LOOKUP_ACCESS_LOOKUP_FIFO_3 */ "", 7176 /* IPPB_FLPB_LOOKUP_ACCESS_LOOKUP_FIFO_4 */ "", 7177 /* IPPB_FLPB_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 7178 /* IPPB_FLPB_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 7179 /* IPPB_FLPB_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 7180 /* IPPB_FLPB_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 7181 /* IPPB_FLPB_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 7182 /* IPPB_FLPB_RES_CONTEXT_ENABLERS */ "FlpbResContextEnablers", 7183 /* IPPB_FLPB_USER_GENERAL_CONTAINER_CFG */ "contains a 3b code per container:\n 4'd0: don't override\n 4'd1: override with PD0\n 4'd2: override with PD1\n 4'd3: override with FPD0\n 4'd4: override with FPD1\n 4'd5: override with DE0\n 4'd6: override with DE1\n 4'd7: overide with PD0 result only\n 4'd8: overide with PD1 result only\n 4'd9: overide with FPD0 result only\n 4'd10: overide with FPD1 result only\n Containers:\n 0,1 24b\n 2,3 40b\n 4 96b\n 5 160b", 7184 /* IPPB_FLPLE_CONTEXT_CONSTANT_VALUES */ "memory to map constants according to context", 7185 /* IPPB_FLPLE_CONTROL_MEM_0_FIFO */ "FIFO for tcam lookup result\n di = visibility bit,KBR error (mdb keys),bypass, context0, acl context0, valid key mask", 7186 /* IPPB_FLPLE_CONTROL_MEM_1_FIFO */ "FIFO for tcam lookup result\n di = visibility bit,KBR error (mdb keys),bypass, context0, acl context0, valid key mask", 7187 /* IPPB_FLPLE_FFC_GROUP_0_QUAD_0 */ "maps ffc instructions according to either fwd context or acl context per a group assign to a stage", 7188 /* IPPB_FLPLE_FFC_GROUP_0_QUAD_IS_ACL_CONTEXT */ "Indicates per 4 FSL what is the context that controls them", 7189 /* IPPB_FLPLE_FFC_GROUP_1_QUAD_0 */ "maps ffc instructions according to either fwd context or acl context per a group assign to a stage", 7190 /* IPPB_FLPLE_FFC_GROUP_1_QUAD_IS_ACL_CONTEXT */ "Indicates per 4 FSL what is the context that controls them", 7191 /* IPPB_FLPLE_FFC_GROUP_2_QUAD */ "maps ffc instructions according to either fwd context or acl context per a group assign to a stage", 7192 /* IPPB_FLPLE_FFC_GROUP_2_QUAD_IS_ACL_CONTEXT */ "Indicates per 4 FSL what is the context that controls them", 7193 /* IPPB_FLPLE_FFC_GROUP_3_QUAD */ "maps ffc instructions according to either fwd context or acl context per a group assign to a stage", 7194 /* IPPB_FLPLE_FFC_GROUP_3_QUAD_IS_ACL_CONTEXT */ "Indicates per 4 FSL what is the context that controls them", 7195 /* IPPB_FLPLE_FFC_GROUP_4_QUAD */ "maps ffc instructions according to either fwd context or acl context per a group assign to a stage", 7196 /* IPPB_FLPLE_FFC_GROUP_4_QUAD_IS_ACL_CONTEXT */ "Indicates per 4 FSL what is the context that controls them", 7197 /* IPPB_FLPLE_KBR */ "KBR memory with indication which FFCs to collect and what appdbs to assign them", 7198 /* IPPB_FLPLE_KEY_BUILDER_IS_ACL_CONTEXT */ "Indicates per Key-Builder what is the context that controls it", 7199 /* IPPB_FLPLE_LATENCY_FIFO_MEM_0 */ "TCAM 2 result(64),err(1),hit(1)", 7200 /* IPPB_FLPLE_LATENCY_FIFO_MEM_1 */ "TCAM 3 result(64),err(1),hit(1)", 7201 /* IPPB_FLPLE_LATENCY_FIFO_MEM_2 */ "ELK RPF result(64),err(1),hit(1)", 7202 /* IPPB_FLPLE_LATENCY_FIFO_MEM_3 */ "ELK FWD result(64),err(1),hit(1)", 7203 /* IPPB_FLPLE_LATENCY_FIFO_MEM_4 */ "LEM0 result(96),err(1),hit(1)", 7204 /* IPPB_FLPLE_LATENCY_FIFO_MEM_5 */ "EXEMB result(64),err(1),hit(1)", 7205 /* IPPB_FLPLE_LATENCY_FIFO_MEM_6 */ "EXEMA result(64),err(1),hit(1)", 7206 /* IPPB_FLPLE_LATENCY_FIFO_MEM_7 */ "LEM1 result(96),err(1),hit(1)", 7207 /* IPPB_FLPLE_LATENCY_FIFO_MEM_8 */ "TCAM0 traps result(64),err(1),hit(1)", 7208 /* IPPB_FLPLE_LATENCY_FIFO_MEM_9 */ "TCAM1 traps result(64),err(1),hit(1)", 7209 /* IPPB_FLPLE_LATENCY_FIFO_MEM_10 */ "KAPSA0 result(64),err(1),hit(1)", 7210 /* IPPB_FLPLE_LATENCY_FIFO_MEM_11 */ "KAPSA1 result(64),err(1),hit(1)", 7211 /* IPPB_FLPLE_LATENCY_FIFO_MEM_12 */ "KAPSB0 result(64),err(1),hit(1)", 7212 /* IPPB_FLPLE_LATENCY_FIFO_MEM_13 */ "KAPSB1 result(64),err(1),hit(1)", 7213 /* IPPB_FLPLE_LATENCY_FIFO_MEM_14 */ "IOEM0 result(48),err(1),hit(1)", 7214 /* IPPB_FLPLE_LATENCY_FIFO_MEM_15 */ "OEM1 result(48),err(1),hit(1)", 7215 /* IPPB_FLPLE_LATENCY_FIFO_MEM_16 */ "OEM2 result(48),err(1),hit(1)", 7216 /* IPPB_FLPLE_LATENCY_FIFO_MEM_17 */ "OEM3 result(48),err(1),hit(1)", 7217 /* IPPB_FLPLE_LATENCY_FIFO_MEM_19 */ "ELK ACL1 result(96),err(1),hit(1)", 7218 /* IPPB_FLPLE_LATENCY_FIFO_MEM_20 */ "Direct0 result(160),err(1),hit(1)", 7219 /* IPPB_FLPLE_LATENCY_FIFO_MEM_21 */ "Direct1 result(160),err(1),hit(1)", 7220 /* IPPB_FLPLE_PD_0 */ "FLPA - FWD PD", 7221 /* IPPB_FLPLE_PD_1 */ "FLPA RPF PD", 7222 /* IPPB_FLPLE_PD_2 */ "FLPB - FWD PD", 7223 /* IPPB_FLPLE_PD_3 */ "FLPB - RPF PD", 7224 /* IPPB_FLPLE_PD_4 */ "floating", 7225 /* IPPB_FLPLE_PD_5 */ "Floating", 7226 /* IPPB_FLPLE_PD_0_CONTEXT_TO_PROFILES_DATA */ "maps a profile per interface of the PD", 7227 /* IPPB_FLPLE_PD_1_CONTEXT_TO_PROFILES_DATA */ "maps a profile per interface of the PD", 7228 /* IPPB_FLPLE_PD_2_CONTEXT_TO_PROFILES_DATA */ "maps a profile per interface of the PD", 7229 /* IPPB_FLPLE_PD_3_CONTEXT_TO_PROFILES_DATA */ "maps a profile per interface of the PD", 7230 /* IPPB_FLPLE_PD_4_CONTEXT_TO_PROFILES_DATA */ "maps a profile per interface of the PD", 7231 /* IPPB_FLPLE_PD_5_CONTEXT_TO_PROFILES_DATA */ "maps a profile per interface of the PD", 7232 /* IPPB_FLP_ELK_FWD_STRENGTH_MAPPING_MEM */ "each memory is mapped by an 8b prefix and a strength is chosen according to deault bit", 7233 /* IPPB_FLP_ELK_RPF_STRENGTH_MAPPING_MEM */ "each memory is mapped by an 8b prefix and a strength is chosen according to deault bit", 7234 /* IPPB_FLP_FWD_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7235 /* IPPB_FLP_FWD_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 7236 /* IPPB_FLP_KAPS_STRENGTH_MAPPING_MEM */ "each memory is mapped by an 8b prefix and a strength is chosen according to deault bit", 7237 /* IPPB_FLP_PORT_PROFILE_MAP */ "maps port to port profile", 7238 /* IPPB_FLP_PTC_PROFILE_MAP */ "maps port to port profile", 7239 /* IPPB_FLP_RPF_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7240 /* IPPB_FLP_RPF_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 7241 /* IPPB_FORCE_LB_LAYER_MEM */ "a memory used for a CAM to implement Force LB Layer for the layer records according to type and qualifier", 7242 /* IPPB_ICMP_TYPE_COMPRESSION_TABLE */ "maps port to port profile", 7243 /* IPPB_IEEE_1588_ACTION */ "Accessed with IEEE-1588-Encapsulation (1), IEEE-1588-Address (2), IEEE-1588-Header.Message-Type (4), IEEE-1588-Header.Flag-Field9\n each action is selected according to In-PP-Port.IEEE-1588-Profile (2)", 7244 /* IPPB_IEEE_1588_IDENTIFICATION_CAM */ "This table is used for IEEE1588-protocol identification.\n The table is searched for rules matching, and if all rules don't match then default values will be selected and PacketIsIeee1588 will be set to zero (non IEEE-1588 packet)\n the lookup key is aligned to the FWD layer", 7245 /* IPPB_IPPB_FLP_BYPASS_FIFO */ "holds the statistics from VTT during the calculation of the FLP processing pipe", 7246 /* IPPB_KLEAP_LKP_FFC_INSTRUCTION */ "Ffc instruction", 7247 /* IPPB_LEARN_APPDB_MAP */ "maps the app_index generated in VTT into a 6b appdb used in the Learning Fixed Key lookup", 7248 /* IPPB_LOAD_BALANCING_CRC_SELECTION_CAM */ "maps destination and outlif0 into a configuration of which CRC16 to use per LB client", 7249 /* IPPB_MEM_100000 */ "INTERNAL", 7250 /* IPPB_MEM_120000 */ "INTERNAL", 7251 /* IPPB_MEM_1E00000 */ "INTERNAL", 7252 /* IPPB_MEM_1E10000 */ "INTERNAL", 7253 /* IPPB_MEM_1E20000 */ "INTERNAL", 7254 /* IPPB_MEM_A00000 */ "INTERNAL", 7255 /* IPPB_MEM_A20000 */ "INTERNAL", 7256 /* IPPB_MEM_F000000 */ "INTERNAL", 7257 /* IPPB_MPLS_LABEL_TYPES_CAM_0 */ "used for mpls labels identification and assignment for label types in the following table", 7258 /* IPPB_MPLS_LABEL_TYPES_CAM_1 */ "used for mpls labels identification and assignment for label types in the following table", 7259 /* IPPB_MY_BFD_DIP */ "This table contains 16 IPv6-Destination-IPs. These IP addresses are compared to incoming destination IP to identify Multi-Hop BFD over IP.\n For IPv4 format, use default IPv4 extension: 0::FFFF:IPv4-DIP", 7260 /* IPPB_OAMA */ "Map MP type (4b), Opcode (4b), MP Profile (4b), My CFM MAC (1b), Inject, DA is MC", 7261 /* IPPB_OAMB */ "Map PKT-IS-BFD(1), OAM-ACC-MEP-MP-Prof (4), OAM-Opcode (4), My-CFM-MAC (1), Inject(1), DA-IS-MC(1)", 7262 /* IPPB_OAM_CHANNEL_TYPE */ "This table is used to map Control-Words Channel-Type to OAM-Format. The table contains 16 entries, with the index being a control words channel type. The value in each entry contain sthe OAM format, including format type, format opcode and the result of OAM channel type lookup in the CAM.", 7263 /* IPPB_OAM_COUNTER_DISABLE_MAP */ "enable the counter per counter interface. A bitmap with a selector nof_valid_lm_lifs(2),oamb_dis_cnt(1),in_lif_valid_for_lm(1), mp_type(4)", 7264 /* IPPB_OAM_KEY_SEL_MEM */ "maps oam_your_discr, is_inlif_valid_for_lm, nof_valid_lm_lifs(2) into selector for the 3 OAM LIF DB key constructions", 7265 /* IPPB_OAM_MP_TYPE_MAP */ "MP Type Map used in MP type calculation oam_is_bfd(1),nof_mep_below_mdl(3),mdl_mp_type(2),nof_above_mdl(3)", 7266 /* IPPB_OAM_MY_CFM_MAC */ "control-Word.Channel-Type", 7267 /* IPPB_OAM_PDU_DS_TO_PCP_VEC */ "maps the PCP in cases of MPLS TP in OAM ID", 7268 /* IPPB_PHB_ECN_CONTEXT_ACTION_MEM */ "maps the inheritance action into key construction cfg and result selection", 7269 /* IPPB_PHB_ECN_CONTEXT_SELECTION_CAM */ "maps the results of the inheritance propagation pipe into a context action", 7270 /* IPPB_PHB_ECN_MAP_INDEX_EXPLICIT_VALUE_MEM */ "maps either the Explicit value or part of the key construction cfg according to the propagation profile and internal context", 7271 /* IPPB_PHB_ECN_PROFILE_RESOLUTION_MEM */ "maps the profile from the inheritance propagation pipe into the resolution profile", 7272 /* IPPB_PHB_ECN_RESULT_MEM */ "maps the constructed key into a final result", 7273 /* IPPB_PHB_TCDP_PROFILE_RESOLUTION_MEM */ "maps the profile from the inheritance propagation pipe into the resolution profile", 7274 /* IPPB_PHB_TC_DP_CONTEXT_ACTION_MEM */ "maps the inheritance action into key construction cfg and result selection", 7275 /* IPPB_PHB_TC_DP_CONTEXT_SELECTION_CAM */ "maps the results of the inheritance propagation pipe into a context action", 7276 /* IPPB_PHB_TC_DP_MAP_INDEX_EXPLICIT_VALUE_MEM */ "maps either the Explicit value or part of the key construction cfg according to the propagation profile and internal context", 7277 /* IPPB_PHB_TC_DP_RESULT_MEM */ "maps the constructed key into a final result", 7278 /* IPPB_PINFO_FLP_MEM */ "This table provides port info for the Forwarding Lookup (FLP) unit. The table has 256 entries, one per PP port, with the index being the port number. Every entry contains information used for forwarding lookup decisions by the ingress packet processor.", 7279 /* IPPB_REMARK_CONTEXT_ACTION_MEM */ "maps the inheritance action into key construction cfg and result selection", 7280 /* IPPB_REMARK_CONTEXT_SELECTION_CAM */ "maps the results of the inheritance propagation pipe into a context action", 7281 /* IPPB_REMARK_MAP_INDEX_EXPLICIT_VALUE_MEM */ "maps either the Explicit value or part of the key construction cfg according to the propagation profile and internal context", 7282 /* IPPB_REMARK_PROFILE_RESOLUTION_MEM */ "maps the propagation profile into resolution profile", 7283 /* IPPB_REMARK_RESULT_MEM */ "maps the constructed key into a final result", 7284 /* IPPB_TRAP_HANDLING_TABLE */ "maps trap properties for the detected trap", 7285 /* IPPB_TRAP_PROFILING_TABLE */ "mapped by either pp port, in lif profile0 or outlif profile into a small profile of each of the traps", 7286 /* IPPB_TTL_CONTEXT_ACTION_MEM */ "maps the inheritance action into key construction cfg and result selection", 7287 /* IPPB_TTL_CONTEXT_SELECTION_CAM */ "maps the results of the inheritance propagation pipe into a context action", 7288 /* IPPB_UNKNOWN_DA_PROFILE */ "This table is used to map an unknown Destination Address (DA) action profile to a destination address. The table has 24 entries, with the index being DA-Type0..2 In-LIF-DA-Not-Found-Profile, In-PP-Port.DA-Not-Found-Profile and the value being the default destination to use.\n DA-Type is defined as follows:\n 0x0 - Multicast\n 0x1: Broadcast\n 0x2: Unicast\n The reset Value for all lines is 0x0 with a mask value of 0x1F.", 7289 /* IPPB_VLAN_EDIT_PCP_DEI_MEM */ "the map uses address compression from 1K to 256.\n Use the pointer in the following format:\n address = pointer7:0\n data=mem_datapointer9:8*8+:8", 7290 /* IPPC_CS_INLIF_PROFILE_MAP_0 */ "In lif 0 porifle used in CS", 7291 /* IPPC_CS_INLIF_PROFILE_MAP_1 */ "In lif 0 porifle used in CS", 7292 /* IPPC_EFES_ACTION_MASK */ "Program Instruction Table per program for all 8 keys", 7293 /* IPPC_EVENTOR_FIFO */ "State Table used in key update keygen or acr", 7294 /* IPPC_FEM_0_4B_MAP_TABLE */ "This table defines the action type and how to build the action.\n Table Address: MapIndex", 7295 /* IPPC_FEM_10_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7296 /* IPPC_FEM_11_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7297 /* IPPC_FEM_12_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7298 /* IPPC_FEM_13_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7299 /* IPPC_FEM_14_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7300 /* IPPC_FEM_15_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7301 /* IPPC_FEM_1_4B_MAP_TABLE */ "Same as Fem0MapTable", 7302 /* IPPC_FEM_2_24B_MAP_TABLE */ "For details, see Fem0_4bMapTable.", 7303 /* IPPC_FEM_3_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7304 /* IPPC_FEM_4_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7305 /* IPPC_FEM_5_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7306 /* IPPC_FEM_6_24B_MAP_TABLE */ "For details, see Fem0_4bMapTable.", 7307 /* IPPC_FEM_7_24B_MAP_TABLE */ "For details, see Fem0_4bMapTable.", 7308 /* IPPC_FEM_8_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7309 /* IPPC_FEM_9_24B_MAP_TABLE */ "Same as Fem2_24bMapTable", 7310 /* IPPC_FEM_BIT_SELECT */ "This table holds the 4bits to be taken from the key, which are used to address MapIndexTable.\n Table Address: According to the FEM-Program", 7311 /* IPPC_FEM_MAP_INDEX_TABLE */ "This table holds the FEM's Map-Data and Map-Index, which are used as an address to the Fem0..15MapTable.\n Table Address: FEM-Program(2b), Key-Selected-Bits(4b)", 7312 /* IPPC_FES_2ND_INSTRUCTION */ "Program Instruction Table per program for all 32 FESs\n Fes_2ndInstruction mem 31-N is connected to FES N", 7313 /* IPPC_FIFO_DIRECT_EXTRACTION_PASS_1 */ "FIFO for lpm 2nd lookup result", 7314 /* IPPC_FIFO_DIRECT_EXTRACTION_PASS_2 */ "FIFO for lpm 2nd lookup result", 7315 /* IPPC_FIFO_DIRECT_PASS_1 */ "FIFO for lpm 1st lookup result", 7316 /* IPPC_FIFO_DIRECT_PASS_2 */ "FIFO for lpm 2nd lookup result", 7317 /* IPPC_FIFO_DSP */ "FIFO for data sample\n the fifo size is twice the db fifo size + 12", 7318 /* IPPC_FIFO_DSP_PASS_1 */ "FIFO for data sample", 7319 /* IPPC_FIFO_DSP_PASS_2 */ "FIFO for data sample", 7320 /* IPPC_FIFO_EXEM_PASS_1 */ "FIFO for lem lookup result", 7321 /* IPPC_FIFO_EXEM_PASS_2 */ "FIFO for lem lookup result", 7322 /* IPPC_FIFO_IP_DSP */ "FIFO for data sample\n the fifo size is twice the db fifo size + 12", 7323 /* IPPC_FIFO_STATE_TABLE_PASS_1 */ "FIFO for lem lookup result", 7324 /* IPPC_FIFO_STATE_TABLE_PASS_2 */ "FIFO for lem lookup result", 7325 /* IPPC_FIFO_TCAM_PASS_1 */ "FIFO for tcam 1st pass lookup result", 7326 /* IPPC_FIFO_TCAM_PASS_2 */ "FIFO for tcam 2nd pass lookup result", 7327 /* IPPC_L_4_OPS */ "Used to calculate L4Ops. The relevant bit of the L4Ops is set to '1' if:\n (source_port >= source_port_min ) &\n (source_port <= source_port_max ) &\n (destination_port >= destination_port_min ) &\n (destination_port <= destination_port_max )\n Reset Value:\n Value: 64'h0 Mask: 64'h0", 7328 /* IPPC_MAP_STATISTIC_OBJECT */ "this memory configures how will statistics object are mapped", 7329 /* IPPC_MEM_220000 */ "INTERNAL", 7330 /* IPPC_MEM_240000 */ "INTERNAL", 7331 /* IPPC_MEM_F000000 */ "INTERNAL", 7332 /* IPPC_PER_PORT_STATISTICS */ "Per port statistics will be mapped along other statistics to the adequate statistics interface using pmfa statistics mapping mechanism", 7333 /* IPPC_PINFO_PMF */ "port info", 7334 /* IPPC_PMFACSA_ACTION */ "PmfacsaAction", 7335 /* IPPC_PMFACSA_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7336 /* IPPC_PMFACSA_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7337 /* IPPC_PMFACSA_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7338 /* IPPC_PMFACSA_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7339 /* IPPC_PMFACSA_TCAM_HIT_INDICATION */ "PmfacsaTcamHitIndication", 7340 /* IPPC_PMFACSB_ACTION */ "PmfacsbAction", 7341 /* IPPC_PMFACSB_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7342 /* IPPC_PMFACSB_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7343 /* IPPC_PMFACSB_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7344 /* IPPC_PMFACSB_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7345 /* IPPC_PMFACSB_TCAM_HIT_INDICATION */ "PmfacsbTcamHitIndication", 7346 /* IPPC_PMFASOFT_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 7347 /* IPPC_PMFASOFT_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 7348 /* IPPC_PMFASOFT_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 7349 /* IPPC_PMFASOFT_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 7350 /* IPPC_PMFASOFT_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 7351 /* IPPC_PMF_FEM_PROGRAM */ "This table contains the Programmable Mapping and Filtering (PMF) Field Extraction Macros (FES) program. The table has 64 entries, Each entry contains a program and key selection for each FEM.", 7352 /* IPPC_PMF_FES_PROGRAM */ "This table holds the Program and Key-Select for Field-Extraction-Macros.\n lines 0-63 : for FES 0-31", 7353 /* IPPC_PMF_INITIAL_KEY_PASS_2 */ "This table maps program to initial key for the 2nd PMF pass. The table has 64 entries, one per program. Every entry contains the initial key to be used for the 2nd PMF pass.\n Used in conjunction with the previous PMF Pass Key Gen and PMF Pass lookup tables.", 7354 /* IPPC_PMF_KBR_PASS_1 */ "Program Instruction Table per program for all 10 keys", 7355 /* IPPC_PMF_KBR_PASS_2 */ "Program Instruction Table per program for all 5 keys", 7356 /* IPPC_PMF_KEY_GEN_PASS_1 */ "Program Instruction Table per program for all 64 FFCs", 7357 /* IPPC_PMF_KEY_GEN_PASS_2 */ "Program Instruction Table per program for all 32 second pass FFCs", 7358 /* IPPC_PMF_PROGRAM_GENERAL */ "This table provides default values for PMF programs. The table has 64 entries, one per program. Every entry default values for this program.", 7359 /* IPPC_PROGRAM_KEY_GEN_VAR */ "This table provides per PMF program a general variable that can be used in the programmable keys. The table has 64 entries, one per program, and the entrys value is the general variable.", 7360 /* IPPC_PTC_INFO_PMF */ "Port termination context info", 7361 /* IPPC_STATE_TABLE */ "State Table used in key update keygen or acr", 7362 /* IPPC_TRAJECTORY_CONFIGURATION */ "FIFO for lem lookup result", 7363 /* IPPD_CONTEXT_PROFILE_TABLE */ "This is of context", 7364 /* IPPD_DESTINATION_STATUS */ "This table holds a valid bit for each system-port.", 7365 /* IPPD_EFES_ACTION_MASK */ "Program Instruction Table per program for all 8 keys", 7366 /* IPPD_ELEPHANT_TRAP_CFG */ "Elephant trap configuration.\n The address to this table is 4 bits taken from elephant_trap_payload(32) starting from ElephantTrapLearnCfgStartBit.", 7367 /* IPPD_FEC_ARR_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 7368 /* IPPD_FEC_ECMP */ "The FEC ECMP table contains ECMP information for the ecmp FECs, each table is 2K", 7369 /* IPPD_FEC_ECMP_GROUP_PROFILE */ "Group profile containes info about the ecmp profiles", 7370 /* IPPD_FEC_ECMP_MEMBERS */ "The FEC ECMP table contains ECMP RPF information for the first 4K FECs. The table has 512K entries, with the index being the RPF FEC pointer. Each entry has information on the corresponding FEC.", 7371 /* IPPD_FEC_ECMP_RPF_MODE */ "Group profile containes info about the ecmp rpf mode", 7372 /* IPPD_FEC_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7373 /* IPPD_FEC_PATH_SELECT */ "This table maps a FEC entry to a protection path selection. The table has 64K . The index to the table is the FEC entry number, with every eight entries being stored in a single register line, meaning the register address is set by FEC number 16:4 and entry number in the register by FEC number 3:1. Each entry indicates if an odd or even protection path should be taken (in case of protection)", 7374 /* IPPD_FES_2ND_INSTRUCTION */ "Program Instruction Table per program for all 32 FESs\n Fes_2ndInstruction mem 15-N is connected to FES N", 7375 /* IPPD_FIFO_DIRECT_EXTRACTION */ "FIFO for lem lookup result", 7376 /* IPPD_FIFO_DIRECT_PASS */ "FIFO for lpm 1st lookup result", 7377 /* IPPD_FIFO_DSP */ "FIFO for data sample\n the fifo size is twice the db fifo size + 8", 7378 /* IPPD_FIFO_DSP_1 */ "FIFO for data sample", 7379 /* IPPD_FIFO_ELK_RX */ "FIFO for the elk results", 7380 /* IPPD_FIFO_ELK_TX */ "FIFO for the elk requests", 7381 /* IPPD_FIFO_EXEM */ "FIFO for lem lookup result", 7382 /* IPPD_FIFO_IP_DSP */ "FIFO for data sample\n the fifo size is twice the db fifo size + 8", 7383 /* IPPD_FIFO_PACKET_DATA */ "FER partial LB keys", 7384 /* IPPD_FIFO_PASS_1 */ "FER partial LB keys", 7385 /* IPPD_FIFO_PASS_2 */ "FER partial LB keys", 7386 /* IPPD_FIFO_PASS_3 */ "FER partial LB keys", 7387 /* IPPD_FIFO_PASS_4 */ "FER partial LB keys", 7388 /* IPPD_FIFO_PASS_5 */ "FER partial LB keys", 7389 /* IPPD_FIFO_PASS_6 */ "FER partial LB keys", 7390 /* IPPD_FIFO_TCAM_PASS_1 */ "FIFO for tcam 1st pass lookup result", 7391 /* IPPD_FORWARDING_STRENGTH_PROFILE */ "maps 4b forward strength to TM-profile(2b) and forward-strength(1b)", 7392 /* IPPD_FORWARDING_TYPE_TO_CODE */ "maps each forwarding_layer_type, forwarding_layer_qualifier0 to code", 7393 /* IPPD_FWD_ACT_PROFILE */ "This table defines the actions that need to be taken per forwarding action profile. Throughout the PP, various functions assign a forwarding action profile, while the actions of this profile are defined in this table. The table has 512 entries, with the index being the forwarding action profile, and the entrys value being the required actions.\n this table is used to trap resolution. if the packet is trap, the table indicates which fieldes should be overwriten and the new values. if there is no v ...", 7394 /* IPPD_FWD_DESTINATION_PROFILE */ "this table defines the actions that need to be taken per forwarding action profile", 7395 /* IPPD_HEADER_PROFILE */ "Maps each of 16 possible Header profile", 7396 /* IPPD_IN_LIF_PROFILE_TABLE */ "This is a map from in lif profile", 7397 /* IPPD_IN_PORT_PROFILE_TABLE */ "This is of in port", 7398 /* IPPD_LBP_PP_PORT_INFO */ "General configuration per pp port.", 7399 /* IPPD_LEARN_ARR_CONFIGURATION_TABLE */ "configuration for the ARR used for the learn trsanslation from Jericho2 to Jericho", 7400 /* IPPD_MAP_STATISTIC_OBJECT */ "this memory configures how will statistics object are mapped", 7401 /* IPPD_MEM_220000 */ "INTERNAL", 7402 /* IPPD_MEM_230000 */ "INTERNAL", 7403 /* IPPD_MEM_240000 */ "INTERNAL", 7404 /* IPPD_MEM_2010000 */ "INTERNAL", 7405 /* IPPD_MEM_230000_1 */ "INTERNAL", 7406 /* IPPD_MEM_230000_2 */ "INTERNAL", 7407 /* IPPD_MEM_230000_3 */ "INTERNAL", 7408 /* IPPD_MEM_230000_4 */ "INTERNAL", 7409 /* IPPD_MEM_F000000 */ "INTERNAL", 7410 /* IPPD_MIRROR_CODE_TO_CMD */ "Mapping of mirror_code(9) to mirror_command(5).\n This command is going to the TM on the TM-command.sniff1_cmd\n This command is also mapped to probability (MrrActProbability table).", 7411 /* IPPD_MRR_ACT_PROBABILITY */ "Probability of mirror execution per mirror-command.", 7412 /* IPPD_OPCODE_MAP_RX */ "opcode -> size, type", 7413 /* IPPD_OPCODE_MAP_TX */ "opcode -> size, type", 7414 /* IPPD_PER_TRAP_CONTEXT_ENABLE */ "This is a Trap per context enabler", 7415 /* IPPD_PINFO_PMF */ "Port info table", 7416 /* IPPD_PMFBCS_ACTION */ "PmfbcsAction", 7417 /* IPPD_PMFBCS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7418 /* IPPD_PMFBCS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7419 /* IPPD_PMFBCS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7420 /* IPPD_PMFBCS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7421 /* IPPD_PMFBCS_TCAM_HIT_INDICATION */ "PmfbcsTcamHitIndication", 7422 /* IPPD_PMFBSOFT_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 7423 /* IPPD_PMFBSOFT_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 7424 /* IPPD_PMFBSOFT_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 7425 /* IPPD_PMFBSOFT_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 7426 /* IPPD_PMFBSOFT_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 7427 /* IPPD_PMF_FES_PROGRAM */ "This table holds the Program and Key-Select for Field-Extraction-Macros.\n lines 0-31 : for FESs 0-15\n lines 32-63 : for instructions 16-31", 7428 /* IPPD_PMF_KBR_PASS */ "Program Instruction Table per program for all 8 keys", 7429 /* IPPD_PMF_PASS_KEY_GEN */ "Program Instruction Table per program for all 8 keys", 7430 /* IPPD_PMF_PROGRAM_GENERAL */ "This table provides default values for PMF programs. The table has 32 entries, one per program. Every entry default values for this program.", 7431 /* IPPD_PPH_ATTRIBUTES_BY_EEI */ "for each EEI identifier decide if a FHEI sohuld be created instead of EEI and determine it's type and size. This is for MPLS packets, for IP and ETHERNET these values are overriden.", 7432 /* IPPD_PROGRAM_KEY_GEN_VAR */ "This table provides per PMF program a general variable that can be used in the programmable keys. The table has 32 entries, one per program, and the entrys value is the general variable.", 7433 /* IPPD_PTC_INFO_PMF */ "Port-Termination-Context info", 7434 /* IPPD_RXI_ELK */ "FIFO for the FLP requests", 7435 /* IPPD_SAME_INTERFACE_MAP */ "This is a mapping of Context.Same_Interface_Filter_Index(2),In_LIF.Same_interface_Filter_Profile(2),\n In_Port.Same_interface_Filter_Profile(2)", 7436 /* IPPD_SLB_CFG */ "Slb trap configuration.\n The address to this table is 4 bits taken from slb_payload(32) starting from SlbLearnCfgStartBit.", 7437 /* IPPD_SNP_ACT_PROBABILITY */ "Probability of Snoop execution per snoop-command(4).\n Snoop_action(4) is a mapping of snoop_code(9) from the table SnoopAction.", 7438 /* IPPD_SNP_CODE_TO_CMD */ "Mapping of snoop_code(9) to snoop_command(5).\n This command is going to the TM on the TM-command.sniff0_cmd\n This command is also mapped to probability", 7439 /* IPPD_STATISTICAL_SAMPLE_ACT_PROBABILITY */ "Probability of Statistical-sampling execution per Statistical-sampling-command.", 7440 /* IPPD_STAT_SAMPLE_CODE_TO_CMD */ "Mapping of statistical_sampling_code(9) to statistical_sampling_command(5).\n This command is going to the TM on the TM-command.sniff2_cmd\n This command is also mapped to probability (StatisticalSampleActProbability)", 7441 /* IPPD_SUPER_ARR_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7442 /* IPPD_SUPER_ARR_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 7443 /* IPPD_TIME_STAMP_FIFO */ "Fifo that samples the Time stamp from the Parser and holds it until the relevant packet has arrived.", 7444 /* IPPD_WEAK_TM_MAP */ "This is a mapping between weak tm profile to Tm offset", 7445 /* IPPE_LLRCS_ACTION */ "LlrcsAction", 7446 /* IPPE_LLRCS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7447 /* IPPE_LLRCS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7448 /* IPPE_LLRCS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7449 /* IPPE_LLRCS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7450 /* IPPE_LLRCS_TCAM_HIT_INDICATION */ "LlrcsTcamHitIndication", 7451 /* IPPE_LLR_LLVP */ "Link layer VLAN processing table. This table has 1024 entries, and the index into the table is Cfg-Extend-VCP-En? VLAN-Classification-Profile (4b) : VLAN-Classification-Profile 2:0Is-Priority-Tag , Layer-Qualifier.First-TPID(3b) ,Layer-Qualifier.Second-TPID (3b).\n Each entry includes information on the matcing VLAN tag and how it should be processed.", 7452 /* IPPE_LLR_PTC_TABLE */ "Map ptc tp ptc profile", 7453 /* IPPE_LL_MIRROR_PROFILE */ "Link layer Mirror profile table. This table has 2K entries, and the index into the table is VID-Index, In-PP-Port.Each entry contains the link layer mirror profile matching its index.", 7454 /* IPPE_MEM_000000 */ "INTERNAL", 7455 /* IPPE_MEM_570000 */ "INTERNAL", 7456 /* IPPE_MEM_580000 */ "INTERNAL", 7457 /* IPPE_MEM_7000000 */ "INTERNAL", 7458 /* IPPE_MEM_1E0000 */ "INTERNAL", 7459 /* IPPE_MEM_2D0000 */ "INTERNAL", 7460 /* IPPE_MEM_3C0000 */ "INTERNAL", 7461 /* IPPE_MEM_B900000 */ "INTERNAL", 7462 /* IPPE_MEM_F0000 */ "INTERNAL", 7463 /* IPPE_PINFO_LLR */ "This register includes port information settings of the IHP link layer block. This table has 256 entries, one per port.", 7464 /* IPPE_PP_PORT_TO_QOS */ "Mapped Pp-Port to initial Qos information", 7465 /* IPPE_PP_PORT_TO_VD */ "Map PP port to vlan domain", 7466 /* IPPE_PRSE_LOAD_BALANCING_PROGRAM */ "PrseLoadBalancingProgram0..14", 7467 /* IPPE_PRTCAM_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7468 /* IPPE_PRTCAM_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7469 /* IPPE_PRTCAM_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7470 /* IPPE_PRTCAM_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7471 /* IPPE_PRTCAM_TCAM_HIT_INDICATION */ "PrtcamTcamHitIndication", 7472 /* IPPE_PRT_PP_PORT_INFO */ "default values for pp-port, src-sys-port, parsing-context and prt-qulifier0.\n per pp-port.", 7473 /* IPPE_PRT_PROFILE_INFO */ "The address to this table is ptc_profile, rcycle_profile", 7474 /* IPPE_PRT_PTC_INFO */ "thse values together with the values from RecycleInfo are concetrated to 32B from header to build the input to the FFCs: ptc, ptc.attributes, recycle, recycle.attributes, 32B header MSB", 7475 /* IPPE_PRT_PTC_PROFILE */ "address to ProfileInfo table is: ptc(8)", 7476 /* IPPE_PRT_RECYCLE_INFO */ "thse values together with the values from PtcInfo are concetrated to 32B from header to build the input to the FFCs: ptc, ptc.attributes, recycle, recycle.attributes, 32B header MSB", 7477 /* IPPE_PRT_RECYCLE_PROFILE */ "address to ProfileInfo table is: recycle_command.prt_profile", 7478 /* IPPE_VIRTUAL_PORT_AD */ "default values for pp-port and src-sys-port.", 7479 /* IPPF_COE_CHANNEL_ID */ "CoE Map PTC,VID to channel-id", 7480 /* IPPF_DESIGNATED_VLAN_TABLE */ "This table hold 8 designated VLANs, per pp-port designated-vlan index.\n Used twice, first for stage 1 and second for one of the stages 2B-3B", 7481 /* IPPF_FWD_DOMAIN_CS_PROFILE_MAP */ "map the vsi_profile to cs_vsi_profile", 7482 /* IPPF_INGRESS_VLAN_EDIT_COMMAND_TABLE */ "accessed with Packet-Is-MEF-L2CP(1), LLVP-Incoming-Tag-Structure (5), AC-VLAN-Edit-Profile 5:3 and chose inside the entry with AC-VLAN-Edit-Profile2:0", 7483 /* IPPF_LEARN_PAYLOAD_CONTEXT_MAPPING */ "Used for learning procedure", 7484 /* IPPF_LIF_PROFILE_ATTRIBUTES_0 */ "Lif.Profile Attributes", 7485 /* IPPF_LIF_PROFILE_ATTRIBUTES_1 */ "Lif.Profile Attributes", 7486 /* IPPF_MAP_CTX_TO_SAVED_CONTEXT_PROFILE */ "Map Context to Saved Context profile", 7487 /* IPPF_MAP_PORT_TO_MEMBERSHIP_IF_VEC */ "This table hold Vlan-Member-Ship-Interface per port.", 7488 /* IPPF_MAP_RIF_PROFILE_TO_ROUTING_ENABLE */ "This table is accessed with the In-Rif-Profile. Each line holds bitmap vector which map Ethernet.Qualifier-Next-Protocol,IP-Qualifier.Is-Mc to enable bit.", 7489 /* IPPF_MAP_VSI_MAC_PREFIX_TO_DA_MSB */ "Map VSI.My-Mac-Prefix(6) to My-Mac-Prefix 38 bits, By this way My-Vsi-Da is equla to My-Mac-Prefix 47:10 VSI.My-MAC-Lsb9:0", 7490 /* IPPF_MEM_AB00000 */ "INTERNAL", 7491 /* IPPF_MEM_AB20000 */ "INTERNAL", 7492 /* IPPF_MEM_ABA0000 */ "INTERNAL", 7493 /* IPPF_MEM_ABC0000 */ "INTERNAL", 7494 /* IPPF_MEM_F000000 */ "INTERNAL", 7495 /* IPPF_ROUTING_PROFILE_TABLE */ "This table is accessed with the In-Rif-Profile. Routing profile pointer", 7496 /* IPPF_STP_TABLE */ "This table is accessed with the PP-Port. Each line holds the STP state per topology-ID.", 7497 /* IPPF_TERMINATION_PROFILE_TABLE */ "Accessed with Lif.Termination profile", 7498 /* IPPF_VD_TO_VLAN_CLASSIFICATION_PROFILE */ "Map Vlan Domain To vlan classifiaction profile which is used in the llvp table", 7499 /* IPPF_VLAN_EDIT_PCP_DEI_MAP */ "Accessed by PCP-DEI-Map-Profile3:0 Incoming-Tag.PCP-DEI(4).\n 6 Msb used for Table Address and 2 LSB for Entry resolution", 7500 /* IPPF_VLAN_MEMBERSHIP_IF_ATTR */ "Used for ethernet procedure", 7501 /* IPPF_VLAN_MEMBERSHIP_TABLE */ "This table holds a bit per Initial-VID, VlanDomainIf for the VLAN-Port membership. Table is accessed with Initial-VID, and each line holds one bit per pp-port.\n Used twice, first for stage 1 and second for one of the stages 2B-3B", 7502 /* IPPF_VLAN_RANGE_COMPRESSION_TABLE */ "Used twice, first for stage 1 and second for one of the stages 2B-3B", 7503 /* IPPF_VRID_DA_PROFILE_ATTR */ "DA-Profile is mapped to Trap-Enable & Layer-Index-Offset(3) & Ethernet-offset(5) Internal-Offset(6) & Mask(32)", 7504 /* IPPF_VRID_MY_MAC_MAPPING */ "DA-Profile is mapped to FFC, Kbr, FormatIdx", 7505 /* IPPF_VRID_MY_MAC_TCAM */ "TCAM interface for vrid based my-mac.", 7506 /* IPPF_VSI_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7507 /* IPPF_VSI_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 7508 /* IPPF_VSI_PROFILE_ATTRIBUTES_0 */ "If VSI-Profile10 is unset then Map VSI-Profile(9) to Learn-Key-Context", 7509 /* IPPF_VSI_PROFILE_ATTRIBUTES_1 */ "If VSI-Profile10 is set then Map VSI-Profile(9) to Learn-Key-Context", 7510 /* IPPF_VTACS_ACTION */ "VtacsAction", 7511 /* IPPF_VTACS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7512 /* IPPF_VTACS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7513 /* IPPF_VTACS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7514 /* IPPF_VTACS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7515 /* IPPF_VTACS_TCAM_HIT_INDICATION */ "VtacsTcamHitIndication", 7516 /* IPPF_VTA_CONTEXT_SEL_TCAM */ "Context selection is relevant for first stage", 7517 /* IPPF_VTA_LOOKUP_ACCESS_LOOKUP_FIFO_0 */ "FIFO for packet data waiting for the Dbs results\n we are poping this fifo after the in-lit table returns an answer", 7518 /* IPPF_VTA_LOOKUP_ACCESS_LOOKUP_FIFO_1 */ "FIFO for packet data waiting for the Dbs results\n this fifo holds the header and we are using it for the VRID my mac key building", 7519 /* IPPF_VTA_LOOKUP_ACCESS_LOOKUP_FIFO_2 */ "FIFO for packet data waiting for the Dbs results", 7520 /* IPPF_VTA_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 7521 /* IPPF_VTA_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 7522 /* IPPF_VTA_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 7523 /* IPPF_VTA_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 7524 /* IPPF_VTA_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 7525 /* IPPF_VTA_POST_GENERAL_DATA_FIFO */ "FIFO for packet data waiting for the Dbs results", 7526 /* IPPF_VTBCS_ACTION */ "VtbcsAction", 7527 /* IPPF_VTBCS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7528 /* IPPF_VTBCS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7529 /* IPPF_VTBCS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7530 /* IPPF_VTBCS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7531 /* IPPF_VTBCS_TCAM_HIT_INDICATION */ "VtbcsTcamHitIndication", 7532 /* IPPF_VTB_LOOKUP_ACCESS_LOOKUP_FIFO_0 */ "FIFO for packet data waiting for the Dbs results", 7533 /* IPPF_VTB_LOOKUP_ACCESS_LOOKUP_FIFO_1 */ "FIFO for packet data waiting for the Dbs results", 7534 /* IPPF_VTB_LOOKUP_ACCESS_LOOKUP_FIFO_2 */ "FIFO for packet data waiting for the Dbs results", 7535 /* IPPF_VTB_LOOKUP_ACCESS_LOOKUP_FIFO_3 */ "FIFO for packet data waiting for the Dbs results", 7536 /* IPPF_VTB_POST_GENERAL_DATA_FIFO */ "FIFO for packet data waiting for the Dbs results", 7537 /* IPPF_VTCCS_ACTION */ "VtccsAction", 7538 /* IPPF_VTCCS_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n every entry refering to a TCAM bank.", 7539 /* IPPF_VTCCS_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 7540 /* IPPF_VTCCS_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 7541 /* IPPF_VTCCS_TCAM_ENTRY_PROTECTION */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 7542 /* IPPF_VTCCS_TCAM_HIT_INDICATION */ "VtccsTcamHitIndication", 7543 /* IPPF_VTC_LOOKUP_ACCESS_LOOKUP_FIFO_0 */ "FIFO for packet data waiting for the Dbs results", 7544 /* IPPF_VTC_LOOKUP_ACCESS_LOOKUP_FIFO_1 */ "FIFO for packet data waiting for the Dbs results", 7545 /* IPPF_VTC_LOOKUP_ACCESS_LOOKUP_FIFO_2 */ "FIFO for packet data waiting for the Dbs results", 7546 /* IPPF_VTC_LOOKUP_ACCESS_LOOKUP_FIFO_3 */ "FIFO for packet data waiting for the Dbs results", 7547 /* IPPF_VTC_PEMA_LOAD_CHUNK_SELECTION */ "INTERNAL", 7548 /* IPPF_VTC_PEMA_LOAD_SELECT_ARRAY_ENTRY_BY_VAR_INDEX */ "INTERNAL", 7549 /* IPPF_VTC_PEMA_LOAD_SELECT_CHUNK_LITERARY */ "INTERNAL", 7550 /* IPPF_VTC_PEMA_LOAD_SELECT_HEADER_BY_CONST_INDEX */ "INTERNAL", 7551 /* IPPF_VTC_PEMA_LOAD_SELECT_HEADER_BY_VAR_INDEX */ "INTERNAL", 7552 /* IPPF_VTC_POST_GENERAL_DATA_FIFO */ "FIFO for packet data waiting for the Dbs results", 7553 /* IPPF_VTT_CONTEXT_SEL_TCAM */ "Context selection is relevant for 4 last stages", 7554 /* IPPF_VTT_CURRENT_CONTEXT_PROFILE_MAP */ "maps context to context profile", 7555 /* IPPF_VTT_FORMAT_CONFIGURATION_TABLE */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 7556 /* IPPF_VTT_INIT_CONTEXT_ENABLERS */ "This table is accessed with the Current Context. Each line holds Enablers & profile", 7557 /* IPPF_VTT_IN_PP_PORT_CONFIG */ "This table holds VLAN translation and tunnel termination In-PP-Port configurations.\n Used twice, first for stage 1 and second for one of the stages 2A-2B", 7558 /* IPPF_VTT_IN_PP_PORT_CONFIG_0 */ "This table holds VLAN translation and tunnel termination In-PP-Port configurations.\n Used twice, first for stage 1 and second for one of the stages 2A-2B", 7559 /* IPPF_VTT_MPLS_LABEL_RANGE_TABLE */ "This table hold 8 Mpls Labels ranges and the range attributes.", 7560 /* IPPF_VTT_PREFIX_INDEX_TABLE */ "A list of prefixes, each line is a possible prefix.", 7561 /* IPPF_VTT_RES_CONTEXT_ENABLERS */ "Enablers for resolution stage", 7562 /* IPPF_VTT_ST_ONE_LE_CONTEXT_CONSTANT_VALUES */ "Used for key constructions", 7563 /* IPPF_VTT_ST_ONE_LE_CONTROL_MEM */ "FIFO for tcam lookup result", 7564 /* IPPF_VTT_ST_ONE_LE_FFC */ "Ffc configuration", 7565 /* IPPF_VTT_ST_ONE_LE_FFC_CMD_BITS_FROM_HEADER */ "Load chunk selection instructions", 7566 /* IPPF_VTT_ST_ONE_LE_FFC_CMD_BITS_FROM_LAYER_RECORDS */ "Load chunk selection instructions", 7567 /* IPPF_VTT_ST_ONE_LE_FFC_CMD_BITS_FROM_RELATIVE_HEADER */ "Load chunk selection instructions", 7568 /* IPPF_VTT_ST_ONE_LE_FFC_CMD_LITERALLTY */ "Load chunk selection instructions", 7569 /* IPPF_VTT_ST_ONE_LE_KBR */ "kbr0: key0\n kbr1: key1\n kbr2: if0_tcam\n kbr3: if0_isema\n kbr4: if1_isema\n kbr5: if0_sexem", 7570 /* IPPF_VTT_ST_ONE_LE_KLEAP_LKP_FFC_INSTRUCTION */ "Ffc instruction", 7571 /* IPPF_VTT_ST_ONE_LE_LATENCY_FIFO_MEM */ "FIFO for tcam lookup result", 7572 /* IPPF_VTT_ST_ONE_LE_LATENCY_FIFO_MEM_2 */ "FIFO for tcam lookup result", 7573 /* IPPF_VTT_ST_ONE_LE_LATENCY_FIFO_MEM_3 */ "FIFO for tcam lookup result", 7574 /* IPPF_VTT_ST_ONE_LE_LATENCY_FIFO_MEM_4 */ "FIFO for tcam lookup result", 7575 /* IPPF_VTT_ST_ONE_LE_LATENCY_FIFO_MEM_5 */ "FIFO for tcam lookup result", 7576 /* IPPF_VTT_ST_ONE_LE_PD */ "Used for vta_floating_pd & vta_pd_fwd_domain &\n vta_priority_decoder_vt_result", 7577 /* IPPF_VTT_ST_ONE_LE_PD_CONTEXT_TO_PROFILES_DATA */ "Used for vta_floating_pd & vta_pd_fwd_domain &\n vta_priority_decoder_vt_result", 7578 /* IPPF_VTT_ST_TWO_LE_CONTEXT_CONSTANT_VALUES */ "Used for key constructions", 7579 /* IPPF_VTT_ST_TWO_LE_CONTROL_MEM */ "FIFO for tcam lookup result", 7580 /* IPPF_VTT_ST_TWO_LE_FFC_CMD_BITS_FROM_HEADER */ "Load chunk selection instructions", 7581 /* IPPF_VTT_ST_TWO_LE_FFC_CMD_BITS_FROM_LAYER_RECORDS */ "Load chunk selection instructions", 7582 /* IPPF_VTT_ST_TWO_LE_FFC_CMD_BITS_FROM_RELATIVE_HEADER */ "Load chunk selection instructions", 7583 /* IPPF_VTT_ST_TWO_LE_FFC_CMD_LITERALLTY */ "Load chunk selection instructions", 7584 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_0_QUAD_0 */ "Group0 Quad0 configuration", 7585 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_0_QUAD_CONTEXT_SELECTOR */ "Group0 Quad0 configuration", 7586 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_1_QUAD_0 */ "Group1 Quad0 configuration", 7587 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_1_QUAD_CONTEXT_SELECTOR */ "Group1 Quad0 configuration", 7588 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_2_QUAD */ "Group2 Quad0 and Quad1 configuration", 7589 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_2_QUAD_CONTEXT_SELECTOR */ "Group2 Quad configuration", 7590 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_3_QUAD_0 */ "Group3 Quad0 configuration", 7591 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_3_QUAD_1 */ "Group3 Quad1 configuration", 7592 /* IPPF_VTT_ST_TWO_LE_FFC_GROUP_3_QUAD_CONTEXT_SELECTOR */ "Group3 configuration", 7593 /* IPPF_VTT_ST_TWO_LE_KBR */ "kbr0: key0\n kbr1: key1\n kbr2: if0_isemb\n kbr3: if1_isemb\n kbr4: if1_sexem\n kbr5: if0_tcam\n kbr5: if1_tcam", 7594 /* IPPF_VTT_ST_TWO_LE_KEY_BUILDER_CONTEXT_SELECTOR */ "Key Builder Context Selector configuration", 7595 /* IPPF_VTT_ST_TWO_LE_KLEAP_LKP_FFC_INSTRUCTION */ "Ffc instruction", 7596 /* IPPF_VTT_ST_TWO_LE_LATENCY_FIFO_MEM */ "FIFO for tcam lookup result", 7597 /* IPPF_VTT_ST_TWO_LE_LATENCY_FIFO_MEM_2 */ "FIFO for tcam lookup result", 7598 /* IPPF_VTT_ST_TWO_LE_LATENCY_FIFO_MEM_3 */ "FIFO for tcam lookup result", 7599 /* IPPF_VTT_ST_TWO_LE_LATENCY_FIFO_MEM_4 */ "FIFO for tcam lookup result", 7600 /* IPPF_VTT_ST_TWO_LE_LATENCY_FIFO_MEM_5 */ "FIFO for tcam lookup result", 7601 /* IPPF_VTT_ST_TWO_LE_LATENCY_FIFO_MEM_6 */ "FIFO for tcam lookup result", 7602 /* IPPF_VTT_ST_TWO_LE_PD_0 */ "Used as FPD1", 7603 /* IPPF_VTT_ST_TWO_LE_PD_1 */ "Used as FPD0", 7604 /* IPPF_VTT_ST_TWO_LE_PD_2 */ "Used as VTC priority_decoder_fwd_domain_result", 7605 /* IPPF_VTT_ST_TWO_LE_PD_3 */ "Used as VTC priority_decoder_tt_result", 7606 /* IPPF_VTT_ST_TWO_LE_PD_4 */ "Used as VTB priority_decoder_fwd_domain_result", 7607 /* IPPF_VTT_ST_TWO_LE_PD_5 */ "Used as VTB priority_decoder_tt_result", 7608 /* IPPF_VTT_ST_TWO_LE_PD_0_CONTEXT_TO_PROFILES_DATA */ "Used as FPD1", 7609 /* IPPF_VTT_ST_TWO_LE_PD_1_CONTEXT_TO_PROFILES_DATA */ "Used as FPD0", 7610 /* IPPF_VTT_ST_TWO_LE_PD_2_CONTEXT_TO_PROFILES_DATA */ "Used as VTC priority_decoder_fwd_domain_result", 7611 /* IPPF_VTT_ST_TWO_LE_PD_3_CONTEXT_TO_PROFILES_DATA */ "Used as VTC priority_decoder_tt_result", 7612 /* IPPF_VTT_ST_TWO_LE_PD_4_CONTEXT_TO_PROFILES_DATA */ "Used as VTB priority_decoder_fwd_domain_result", 7613 /* IPPF_VTT_ST_TWO_LE_PD_5_CONTEXT_TO_PROFILES_DATA */ "Used as VTB priority_decoder_tt_result", 7614 /* IPPF_VTT_S_1_VSI_LKUP_FIFO_PIPE */ "FIFO for packet data waiting for the Dbs results", 7615 /* IPPF_VTT_USER_GENERAL_CONTAINER_CFG */ "contains a 3b code per container:\n 3'd0: don't override\n 3'd1: override with PD0\n 3'd2: override with PD1\n 3'd3: override with FPD0\n 3'd4: override with FPD1\n 3'd5: override with DE0\n 3'd6: override with DE1\n Containers:\n 0,1 24b\n 2,3 40b\n 4 96b\n 5 160b", 7616 /* IPPF_VTT_VLAN_DOMAIN_ATTRIBUTES */ "This table holds the VLAN range compression selection per vlan domain\n Used twice, first for stage 1 and second for one of the stages 2B-3B", 7617 /* IPSEC_CONTEXTS_Q_SIZE */ "the size of each context queue", 7618 /* IPSEC_CONTEXTS_Q_START */ "the start of each context queue", 7619 /* IPSEC_CONTEXTS_Q_TH */ "the threshold of each context queue", 7620 /* IPSEC_ERROR_COUNTERS_MEMORY */ "holds a counter per tunnel and a profile to determine which error will be counted", 7621 /* IPSEC_LFEM_FIELD_SELECT_MAP */ "LFEM field selct map **make sure the defulat size is the total size of the memory!!**", 7622 /* IPSEC_POST_DATA */ "post processing data", 7623 /* IPSEC_POST_OUTPUT_FIFO_MEM */ "memories for the input fifos fo each spu wrapper", 7624 /* IPSEC_PRGE_DATA */ "Programmable editor data", 7625 /* IPSEC_PRGE_INSTRUCTION */ "Programmable Editor (PRGE) instructions", 7626 /* IPSEC_PRGE_PROGRAM_VARIABLES */ "holds several program variable needed for the dedicated logic for SPU headers. Accessed according to program.", 7627 /* IPSEC_PROGRAM_DATA */ "Program data memory with initial instruciotn index and two initial instructions", 7628 /* IPSEC_PROGRAM_INDEX_MEMORY */ "a program index memory mapped by tnnel id", 7629 /* IPSEC_REASSEMBLY_BYPASS_FIFO_MEM */ "memory for the bypass fifo in the reassembly block", 7630 /* IPSEC_REASSEMBLY_CONTEXT_NUM */ "Reassembly context number mapped to tunnel id", 7631 /* IPSEC_REASSEMBLY_PACKETS_MEMORY_0 */ "a memory for reassembled packets", 7632 /* IPSEC_REASSEMBLY_PACKETS_MEMORY_1 */ "a memory for reassembled packets", 7633 /* IPSEC_RX_ESN_PTR */ "a pointer to the msb of the ESN in an RX packet", 7634 /* IPSEC_SEQUENCE_VERIFICATION_MEMORY */ "holds sequence numbers for all tunnels", 7635 /* IPSEC_SEQUENCE_VERIFICATION_MEMORY_SLAVE */ "holds the same data as the sequence verification memory but read from the reassembly block in order to calculate ESN - updates with the master memory", 7636 /* IPSEC_SPU_BYPASS_FIFO_MEM */ "memroy for the bypass fifo in the spu control logic block", 7637 /* IPSEC_SPU_WRAPPER_TOP_SPU_INPUT_FIFO_MEM_H */ "memories for the input fifos fo each spu wrapper", 7638 /* IPSEC_SPU_WRAPPER_TOP_SPU_OUTPUT_FIFO_MEM_H */ "memories for the Output fifos fo each spu wrapper", 7639 /* IPSEC_STAMPING_SEQUENCE_NUMBER */ "holds sequence numbers for all tunnels", 7640 /* IPSEC_TUNNEL_DATA */ "Holds SPU header fields", 7641 /* IPSEC_TUNNEL_ID_TABLE */ "Tunnel Id table for PTCH , Dumy header and MTU", 7642 /* IPSEC_TUNNEL_SEQUENCE_NUMBER */ "holds sequence numbers for all tunnels", 7643 /* IPST_CRVS */ "Each source device is associated with one of two possible CreditValues.\n Each bit in this bitmap determines if CreditValue0 or CreditValue1 is to be used.\n This table is enabled by CrValSelEnable register.", 7644 /* IPST_IPS_0_CREDIT_ARBITER_FIFO */ "INTERNAL", 7645 /* IPST_IPS_1_CREDIT_ARBITER_FIFO */ "INTERNAL", 7646 /* IPS_AUTO_DOC_NAME_55 */ "INTERNAL", 7647 /* IPS_AUTO_DOC_NAME_56 */ "INTERNAL", 7648 /* IPS_AUTO_DOC_NAME_59 */ "INTERNAL", 7649 /* IPS_AUTO_DOC_NAME_69 */ "INTERNAL", 7650 /* IPS_AUTO_DOC_NAME_79 */ "INTERNAL", 7651 /* IPS_AUTO_DOC_NAME_87 */ "INTERNAL", 7652 /* IPS_AUTO_DOC_NAME_95 */ "INTERNAL", 7653 /* IPS_AUTO_DOC_NAME_98 */ "INTERNAL", 7654 /* IPS_CAM_FULL_THERSHOLD */ "IFC CamFull Memory.\n Threshold for DRAM/Fabric CAM full per Qtype. CAM maximum value is 'd127.", 7655 /* IPS_CFMEM */ "IFC CamFull Memory.\n Threshold for DRAM/Fabric CAM full per Qtype. CAM maximum value is 'd127.", 7656 /* IPS_CNT_DRAM_CAM */ "INTERNAL", 7657 /* IPS_CNT_DRAM_MEM */ "INTERNAL", 7658 /* IPS_CNT_FABRIC_CAM */ "INTERNAL", 7659 /* IPS_CNT_FABRIC_MEM */ "INTERNAL", 7660 /* IPS_CRBAL */ "This memory holds most of the Q descriptor variables.\n Caution: This table is for debug purposes and should be used with user discretion as it can effect the IPS operation. Special consideration should be given when writing to this table.", 7661 /* IPS_CRBALTH */ "The values in this table affect the credit request state (CRS) according to the credit balance (or the difference between it and the Q size). Values for all thresholds are given in terms of mantissa and exponent. The value of the threshold is (M x 2^E), where M=TH7:4 and E=TH3:0. All values are in 1B resolution.", 7662 /* IPS_CRBAL_TH */ "The values in this table affect the Credit-Request-State (CRS) according to the Credit-Balance or the difference between Queue-Size and the Credit-Balance. All values are in 1/2/4B resolution (according to CreditBalanceResolution) and possitive. Access to this table by using Queue-Type.", 7663 /* IPS_CRDT_VALUE_SEL */ "Each Destination-FAP is associated with one of two possible CreditValues. Each bit in this bitmap determines if CreditValue0 or CreditValue1 is to be used. This table is enabled by CrValSelEnable register. Access using Destination-FAP10:4", 7664 /* IPS_CRDT_WD_TH */ "The values in this table hold thresholds for the credit Watchdog, in case a long time passed since the last credit for an active Queue was received, a Flow-Status-Message can be sent or the queue can be marked to be deleted. Deleted queue will drop all the packets in the queue, in case a packet arrives when the queue is in delete state and there are still packets need to be dropped the new packet will also be dropped. Queue in delete state will return to normal state, when a new credit arrives f ...", 7665 /* IPS_CREDIT_BALANCE_BASED_THRESHOLDS_TABLE */ "The values in this table affect the credit request state (CRS) according to the credit balance (or the difference between it and the Q size). Values for all thresholds are given in terms of mantissa and exponent. The value of the threshold is (M x 2^E), where M=TH7:4 and E=TH3:0. All values are in 1B resolution. Access to this table is according to Queue Type.", 7666 /* IPS_CREDIT_WATCHDOG_THRESHOLDS_TABLE */ "The values in this table hold thresholds for the credit Watchdog, in case a long time passed since the last credit for an active Queue was received, a Flow Status Message can be sent or the queue can be marked to be deleted.\n Deleted queue will drop all the packets in the queue, in case a packet arrives when the queue is in delete state and there are still packets need to be dropped the new packet will also be dropped.\n Queue in delete state will return to normal state, when a new credit arrives ...", 7667 /* IPS_CRVS */ "Each source device is associated with one of two possible CreditValues.\n Each bit in this bitmap determines if CreditValue0 or CreditValue1 is to be used.\n This table is enabled by CrValSelEnable register.", 7668 /* IPS_CRWDTH */ "The values in this tables gives the thresholds for credit watchdog, in case a long time passed since the last credit for an active Q. the Values are given in WD full cycle units. A value of 0 disables the relevant TH.", 7669 /* IPS_CR_BAL_TABLE */ "This memory holds most of the Q descriptor variables.\n Caution: This table is for debug purposes and should be used with user discretion as it can effect the IPS operation. Special consideration should be given when writing to this table.", 7670 /* IPS_DQM_DEQ_CMD_PRMS */ "SQM DEQ command parameters. Accessed by eighter: - 3'b0, Queue-Type(5) (when DqmMaxDeqCmdPrms bit-0 is set) - DQM-DEQ-Command-Profile(2), Credit-Balance-Msbs(5) (when DqmMaxDeqCmdPrms bit-0 is reset)", 7671 /* IPS_DQM_DEQ_CMD_READ_WEIGHT_PROFILE_MAP */ "DQM-Read-Weight-Profile to DQM-Read-Weight mapping.", 7672 /* IPS_D_DQM_DQCQ_FIFO_MEMORY */ "INTERNAL", 7673 /* IPS_EMPTYQCRBAL */ "The values in this table relate to the credit balance of an empty Q, and affect its latency and credit waste.\n Note: Values given here are in 2's complement", 7674 /* IPS_EMPTY_QUEUE_CREDIT_BALANCE_TABLE */ "The values in this table relate to the credit balance of an empty Q, and affect its latency and credit waste. Access to this table is according to Queue Type.\n Note: Values given here are in 2's complement", 7675 /* IPS_EMPTY_Q_CRBAL_TH */ "The values in this table relate to the Credit-Balance of an empty Queue, and affect its latency and credit waste. All values are in 1/2/4B resolution (according to CreditBalanceResolution) and presented in 2's complement. Access to this table by using Queue-Type.", 7676 /* IPS_FLOW_ID_LOOKUP_TABLE */ "Queue to egress base flow mapping- Every 4 queues are mapped to a single base flow and subflow mode.\n Details are explained under InterdigitatedMode register.", 7677 /* IPS_FLWID */ "Queue to egress base flow mapping- Every 4 queues are mapped to a single base flow and subflow mode.\n Details are explained under InterdigitatedMode register.", 7678 /* IPS_FMSBYP */ "FMS may be bypassed if destination device supports Egress FMS function.\n Following table has 1b per Destination Device, set to 1 if FMS may be bypassed.\n This configuration is enabled by FmsEnableByp register.", 7679 /* IPS_FMS_BYPASS */ "FMS may be bypassed if Destination-FAP supports Egress FMS function. Following table has 1b per Destination-FAP. When set, FMS may be bypassed. This configuration is enabled by FmsEnableByp register. Access using Destination-FAP10:4", 7680 /* IPS_FSMRQ_FIFO_MEMORY */ "INTERNAL", 7681 /* IPS_MAXQSZ */ "Maximum queue size for system RED feature- One entry per system physical port reads the value received from credits.", 7682 /* IPS_MEM_180000 */ "INTERNAL", 7683 /* IPS_MEM_200000 */ "INTERNAL", 7684 /* IPS_MEM_220000 */ "INTERNAL", 7685 /* IPS_MEM_240000 */ "INTERNAL", 7686 /* IPS_MEM_260000 */ "INTERNAL", 7687 /* IPS_MEM_280000 */ "INTERNAL", 7688 /* IPS_MEM_1A0000 */ "INTERNAL", 7689 /* IPS_MEM_1C0000 */ "INTERNAL", 7690 /* IPS_MEM_1E0000 */ "INTERNAL", 7691 /* IPS_MEM_2A0000 */ "INTERNAL", 7692 /* IPS_MEM_2C0000 */ "INTERNAL", 7693 /* IPS_MEM_2E0000 */ "INTERNAL", 7694 /* IPS_QDESC */ "This memory holds most of the Q descriptor variables.\n Caution: This table is for debug purposes and should be used with user discretion as it can effect the IPS operation. Special consideration should be given when writing to this table.", 7695 /* IPS_QDESC_TABLE */ "This memory holds most of the Q descriptor variables.\n Caution: This table is for debug purposes and should be used with user discretion as it can effect the IPS operation. Special consideration should be given when writing to this table.", 7696 /* IPS_QFM */ "Queue-Number-Quartet to Flow-ID mapping table. Map queue quartet to a base flow and subflow mode. Note: for more details see InterdigitatedMode register.", 7697 /* IPS_QPM_1 */ "Queue port map 1 (under system red mode)", 7698 /* IPS_QPM_2 */ "Queue port map 2 (under no system red mode).\n In this mode, each entry holds the values for 4 consecutive queues.", 7699 /* IPS_QPM_1_NO_SYS_RED */ "Queue port map 1 (under no system red mode)", 7700 /* IPS_QPM_1_SYS_RED */ "Queue port map 1 (under system red mode)", 7701 /* IPS_QPM_2_NO_SYS_RED */ "Queue port map 2 (under no system red mode).\n In this mode, each entry holds the values for 4 consecutive queues.", 7702 /* IPS_QPM_2_SYS_RED */ "Queue port map 2 (under system red mode)", 7703 /* IPS_QPRI */ "The values in this table Determines if the Queue is High / Low priority and if it is OCB-Only (low latency).\n This affects the DQCQ context selection for this Q-type. Access to this table is according to Queue Type.", 7704 /* IPS_QPRISEL */ "Every 64 contiguous queues are assigned one of four 64-bit bitmaps.\n Each line holds the values for 16 groups.", 7705 /* IPS_QSIZE_TH */ "The values in this table affect the Credit-Request-State (CRS) according to the difference between Queue-Size and Credit-Balance. All values are in 1/2/4B resolution (according to CreditBalanceResolution) and presented in 2's complement. Access to this table by using Queue-Type.", 7706 /* IPS_QSPM */ "Quueue-Number-Quartet to System-Port mapping table", 7707 /* IPS_QSZ */ "Q size variable of the Q descriptor. The value is given in mantissa and exponent format, where M=q_size6:4 and E=q_size3:0. The value is (M x 2^E). A value of -1 (0xFF00 in the register) means that the Q size is over the maximum of the IPS. The queue size is given in 16B resolution.\n Caution: This table is for debug purposes and should be used with user discretion as it can effect the IPS operation. Special consideration should be given when writing to this table.", 7708 /* IPS_QSZTH */ "The values in this table affect the credit request state (CRS) according to the difference between Q size and credit balance. Values for all thresholds are given in terms of mantissa and exponent, with a sign bit. The value of the threshold is (M x 2^E), where M=TH6:4 ,E=TH3:0 and TH7 is the sign bit. All values are in 1B resolution", 7709 /* IPS_QTYPE */ "Each queue is mapped to a queue type, to determine various thresholds and parameters.", 7710 /* IPS_QUEUE_DESCRIPTOR_TABLE */ "This memory holds most of the Q descriptor variables.\n Caution: This table is for debug purposes and should be used with user discretion as it can effect the IPS operation. Special consideration should be given when writing to this table.", 7711 /* IPS_QUEUE_PRIORITY_TABLE */ "The values in this table Determines if the Queue is High / Low priority.\n This affects the DQCQ context selection for this Q-type. Access to this table is according to Queue Type.", 7712 /* IPS_QUEUE_SIZE_BASED_THRESHOLDS_TABLE */ "The values in this table affect the credit request state (CRS) according to the difference between Q size and credit balance. Values for all thresholds are given in terms of mantissa and exponent, with a sign bit. The value of the threshold is (M x 2^E), where M=TH9:4 ,E=TH3:0 and TH10 is the sign bit. All values are in 1B resolution. Access to this table is according to Queue Type.", 7713 /* IPS_QUEUE_SIZE_TABLE */ "Q size variable of the Q descriptor. The queue size is given in 16B resolution.\n Caution: This table is for debug purposes and should be used with user discretion as it can effect the IPS operation. Special consideration should be given when writing to this table.", 7714 /* IPS_QUEUE_TYPE_LOOKUP_TABLE */ "Each queue is mapped to a queue type, to determine various thresholds and parameters. Used as index to QPRI, QSZTH, SFTH, CRBALTH, EMPTYQCRBAL, CRWDTH tables.", 7715 /* IPS_Q_PRIORITY_BIT_MAP */ "The bit position in the bitmap corresponding to the queue determines the priority.", 7716 /* IPS_SFTH */ "Slow-Factor (SF) Thresholds.\n SlowFactor is used when exact scheduling is desired.\n When Flow Status is SLOW, the SCH is assumed to send SLOW rate that ensures only 1 credit is inflight. This allows the IPS to respond in time to stop the SCH such that no exess credits accumulate in the IPS once the Queue is emptied.\n The SlowFactor reflects the number of missing credits (Qsize-CrBal) and allows the SCH to use higher SLOW rates, such that more ...", 7717 /* IPS_SLOW_FACTOR_TH */ "Slow-Factor (SF) Thresholds. SlowFactor is used when exact scheduling is desired. When Flow Status is SLOW, the SCH is assumed to send SLOW rate that ensures only 1 credit is inflight. This allows the IPS to respond in time to stop the SCH such that no exess credits accumulate in the IPS once the Queue is emptied. The SlowFactor reflects the number of missing credits (Qsize-CrBal) and allows the SCH to use higher SLOW rates, such that more than 1 credit is inflight but not too many inflight cred ...", 7718 /* IPS_SLOW_FACTOR_THRESHOLDS_TABLE */ "Slow-Factor (SF) Thresholds.\n SlowFactor is used when exact scheduling is desired.\n When Flow Status is SLOW, the SCH is assumed to send SLOW rate that ensures only 1 credit is inflight. This allows the IPS to respond in time to stop the SCH such that no exess credits accumulate in the IPS once the Queue is emptied.\n The SlowFactor reflects the number of missing credits (Qsize-CrBal) and allows the SCH to use higher SLOW rates, such that more than 1 credit is inflight but not too many inflight c ...", 7719 /* IPS_SPM */ "System-Port mapping table Map System-Port to Dst-FAP and PP-DSP", 7720 /* IPS_SQM_DEQ_CMD_PRMS */ "SQM DEQ command parameters. Accessed by eighter: - Sram-To-Dram(1), 2'b0, Queue-Type(5) (when SqmMaxDeqCmdPrms bit-0 is set) - Sram-To-Dram(1), SQM-DEQ-Command-Profile(2), Credit-Balance-Msbs(5) (when SqmMaxDeqCmdPrms bit-0 is reset)", 7721 /* IPS_SQM_DEQ_CMD_READ_WEIGHT_PROFILE_MAP */ "SQM-Read-Weight-Profile to SQM-Read-Weight mapping.", 7722 /* IPS_S_DQCQ_FIFO_MEMORY */ "INTERNAL", 7723 /* IPS_TIME_STAMP_MEMORY */ "INTERNAL", 7724 /* IPT_ARAD_SNP_MIR_STAMP_EN */ "The IPT stamps for snoop or mirror packet the following fields according to the enable bits, per snoop/mirror command from the IQM's outlif field.\n The address of this table access is is_snoop(~mirror), snoop/mirror-cmd.\n Meaning that the first rows of the table are for mirror and the last rows are for snoop", 7725 /* IPT_ARAD_SNP_MIR_STAMP_VALUES */ "The IPT stamps for snoop or mirror packet the following fields according to the enable bits, per snoop/mirror command from the IQM's outlif field.\n The address of this table access is is_snoop(~mirror), snoop/mirror-cmd.\n Meaning that the first rows of the table are for mirror and the last rows are for snoop", 7726 /* IPT_BDQ */ "Data Buffer queue memory", 7727 /* IPT_CGM_S_2D_CMD_RXI */ "RXI memory.", 7728 /* IPT_CGM_TX_CMD_RXI */ "RXI memory.", 7729 /* IPT_DBLF */ "DBuff List FIFO: holds a packet list of Dram Buffer pointers (up to 40 buffer pointers per packet)", 7730 /* IPT_DDEL_EOBFIF */ "EOB/EOP FIFO", 7731 /* IPT_DQCF */ "DeQCmd FIFO: holds per a dequeue command from the dram/ocb per packet", 7732 /* IPT_DRAM_MIX_RET_BANK */ "The bank of the data returned from the dram, that was requested from the dram and ocb mixed context.\n Second bit is indication if we saw crc error in this segment in this buffer from this bank", 7733 /* IPT_DRAM_MIX_RET_DATA */ "Data returned from the dram, that was requested from the dram and ocb mixed context", 7734 /* IPT_EGQCTL */ "EGQ control FIFO", 7735 /* IPT_EGQDATA */ "EGQ DATA FIFO, PROTECTION ON HEADER BITS", 7736 /* IPT_EGQ_TXQ_RD_ADDR */ "EGQ TX FIFO read pointer.", 7737 /* IPT_EGQ_TXQ_WR_ADDR */ "EGQ TX FIFO write pointer.", 7738 /* IPT_FDTCTL */ "FDT control FIFO", 7739 /* IPT_FDTDATA */ "FDT DATA FIFO", 7740 /* IPT_FDT_TXQ_RD_ADDR */ "FDT TX FIFO read pointer (DTQs)", 7741 /* IPT_FDT_TXQ_WR_ADDR */ "FDT TX FIFO write pointer (DTQs)", 7742 /* IPT_GCI_BACKOFF_MASK */ "GciBackofMask table.\n Configure mask bits for timer period randomization, each 12 bits define a configurable mask per each backoff timer (entry 0 refers to timer1).\n Timer = LFSR17:6 & Mask11:0 LFSR5:0", 7743 /* IPT_IPT_0_DEST_PIPE_MAPPING_2_FDT */ "This table maps the incoming index, build from various packet parameters to the destination pipe send to the FDT.\n The fields building the input of the table are:\n iqm2ipt_hp, iqm2ipt_mc, ftmh2ipt_dp(2bits), ftmh2ipt_trfcls(3bits), is_pkt_tdm(q_sig).\n Per each key above the output is 2 bits of the destination context number (0,1,2).", 7744 /* IPT_IPT_1_DEST_PIPE_MAPPING_2_FDT */ "This table maps the incoming index, build from various packet parameters to the destination pipe send to the FDT.\n The fields building the input of the table are:\n iqm2ipt_hp, iqm2ipt_mc, ftmh2ipt_dp(2bits), ftmh2ipt_trfcls(3bits), is_pkt_tdm(q_sig).\n Per each key above the output is 2 bits of the destination context number (0,1,2).", 7745 /* IPT_ITE_FABRIC_PEF */ "Packet Edit FIFO", 7746 /* IPT_ITE_FABRIC_WDF */ "Word Data FIFO", 7747 /* IPT_ITM_TO_OTM_MAP */ "CNM: this tables maps either ITM port from the CNM FIFO or (src_sys_port from the DRAM - cfg_local_sys_port_base) to OTM/DSP that is inserted to the generated CNM FTMH.", 7748 /* IPT_MAX_LATENCY */ "The IPT measures latency from the packet OAM-TS extension.\n In this memory the 8 maximal latency's are kept, with the pointer associated with them", 7749 /* IPT_MEM_80000 */ "INTERNAL", 7750 /* IPT_MIX_MOP_DESC */ "MIX MOP DESC FIFO:\n Packet buffer pointer list\n This is context based, controls for traffic from pipe0 is in context0 and controls for pipe1 is in context 1.", 7751 /* IPT_MIX_OCB_REQ */ "MIX OCB read request: holds the interface to the mmu for mix-ocb requests from IPT 0&1.\n This is context based, controls for traffic from pipe0 is in context0 and controls for pipe1 is in context 1.", 7752 /* IPT_MIX_SOP_DESC */ "MIX SOP DESC FIFO:\n Memory contents look different for regular packet and CNM packet,\n for CNM they look like this:\n cnm data at 73:0 contains:\n iqm2ipt_cnm_eq_ifp 73:66 (8)\n iqm2ipt_cnm_eq_cpid 65:50 (16)\n iqm2ipt_cnm_eq_qntzd_fb 49:44 (6)\n iqm2ipt_cnm_eq_qoffset 43:28 (16)\n iqm2ipt_cnm_eq_qdelta 27:12 (16)\n ...", 7753 /* IPT_MOP_MIX_SELFIF */ "MOP Select FIFO (MIXS/MIXD)", 7754 /* IPT_MOP_MMU */ "MOP MMU FIFO", 7755 /* IPT_MOP_SELFIF */ "MOP Select FIFO (SRAM/MIX)", 7756 /* IPT_OCB_MIX_RET_DATA */ "Data returned from the ocb, that was requested from the dram and ocb mixed context\n This is context based, there are 2 contexts here, one for pipe0 traffic and one for pipe1.", 7757 /* IPT_OCB_MOP_DESC */ "OCB ONLY MOP DESC FIFO:\n Packet buffer pointer list", 7758 /* IPT_OCB_ONLY_OR_MIX_AND_IQ_MS_ARB */ "Ocb Only Or Mix context And IQMs arbiter: holds indication whether it was from OCB only context or from the MIX contexts", 7759 /* IPT_OCB_ONLY_RET_DATA */ "Data returned from the ocb, that was requested from the ocb only context", 7760 /* IPT_OCB_SOP_DESC */ "OCB ONLY SOP DESC FIFO:\n Memory contents look different for regular packet and CNM packet,\n for CNM they look like this:\n cnm data at 73:0 contains:\n iqm2ipt_cnm_eq_ifp 73:66 (8)\n iqm2ipt_cnm_eq_cpid 65:50 (16)\n iqm2ipt_cnm_eq_qntzd_fb 49:44 (6)\n iqm2ipt_cnm_eq_qoffset 43:28 (16)\n iqm2ipt_cnm_eq_qdelta 27:12 (16)\n ...", 7761 /* IPT_PCP_ACF */ "Aligner Control Fifo", 7762 /* IPT_PCP_ADF */ "Aligner Data Fifo", 7763 /* IPT_PCP_CFG */ "In fabric mode: Packing control. Address is destination device lsb (DestFap10:4). Output is 16 x 2b = 32b", 7764 /* IPT_PCQ */ "Start of packet queue memory", 7765 /* IPT_PEND_BUFF_FIFO */ "Hold start buffers pending for RPC", 7766 /* IPT_PER_DTQ_GIPT_CFG */ "Configurations per DTQ to FC the shapers Dtq0FcTh - Local-EGQ0. Dtq1FcTh - Local-EGQ1. Dtq2FcTh - Fabric-Dtq0. Dtq3FcTh - Fabric-Dtq1. Dtq4FcTh - Fabric-Dtq2. Dtq5FcTh - Total Fabric.", 7767 /* IPT_PER_GIPT_SHAPER_CFG */ "Configuration per IPT shaper, addr=0 : LOCAL-HP addr=1 : LOCAL-LP addr=2 : LOCAL", 7768 /* IPT_PER_SHAPER_CFG */ "Configuration per IPT shaper, addr=0 : LOCAL-HP addr=1 : LOCAL-LP addr=2 : LOCAL", 7769 /* IPT_PRIORITY_BITS_MAPPING_2_FDT */ "This table maps the incoming index, build form various packet parameter to 2 priority bits send to the FDT.\n The fields building the input of the table are:\n iqm2ipt_hp, iqm2ipt_mc, ftmh2ipt_dp(2bits), ftmh2ipt_trfcls(3bits), ftmh2ipt_tdm to 2 bits priority", 7770 /* IPT_PRIORITY_BITS_MAP_2_FDT */ "This table maps the incoming index, build form various packet parameter to 2 priority bits send to the FDT.\n The fields building the input of the table are:\n iqm2ipt_hp, 0 (1 bit reserved), ftmh2ipt_dp(2bits), ftmh2ipt_trfcls(3bits), ftmh2ipt_tdm to 2 bits priority", 7771 /* IPT_RDF_MIXD_FIFO */ "Dequeue Data FIFO", 7772 /* IPT_RDF_SRAM_FIFO */ "Dequeue Data FIFO (OCBO + SRAM + MIXS)", 7773 /* IPT_RRF_SELFIF */ "RRF Select FIFO (SRAM/MIX)", 7774 /* IPT_RRF_SRAM */ "Dequeue Request FIFO (OCBO + SRAM + MIXS)", 7775 /* IPT_SCS_EOBFIF_MIX */ "EOB/EOP FIFO 0-LOC0_HP 1-LOC0_LP 2-LOC1_HP 3-LOC1_LP 4-FUC_DEV1_HP 5-FUC_DEV1_LP 6-DEV2_HP 7-DEV2_LP 8-FMC_DEV3_HP 9-FMC_DEV3_LP", 7776 /* IPT_SCS_EOBFIF_SRM */ "EOB/EOP FIFO 0-LOC0_HP 1-LOC0_LP 2-LOC1_HP 3-LOC1_LP 4-FUC_DEV1_HP 5-FUC_DEV1_LP 6-DEV2_HP 7-DEV2_LP 8-FMC_DEV3_HP 9-FMC_DEV3_LP", 7777 /* IPT_SCS_OCB_EOBFIF */ "EOB/EOP FIFO", 7778 /* IPT_SCS_SELFIF */ "Select (MIX/SRAM) 0-LOC0_HP 1-LOC0_LP 2-LOC1_HP 3-LOC1_LP 4-FUC_DEV1_HP 5-FUC_DEV1_LP 6-DEV2_HP 7-DEV2_LP 8-FMC_DEV3_HP 9-FMC_DEV3_LP", 7779 /* IPT_SHAPER_FMC_CFG */ "Configurations for IPT fabric-MC shaper Index0 : FMC-HP Index1 : FMC-LP Index2 : FMC (total)", 7780 /* IPT_SNP_MIR_CMD_MAP */ "snoop/mirror command (taken from the CUD) mapped to outlif and dsp extension in the FTMH header\n Address to this table is\n mirror or snoop (1 bit), cmd4:0\n if snoop, addr msb = 1\n if mirror addr msb = 0", 7781 /* IPT_SOP_MMU */ "SOP MMU FIFO:\n memory contents look different for regular packet and CNM packet,\n for CNM they look like this:\n cnm data at 77:0 contains:\n iqm2ipt_cnm_eq_ifp 77:70\n iqm2ipt_cnm_eq_cpid 69:54\n iqm2ipt_cnm_eq_qntzd_fb 53:48\n iqm2ipt_cnm_eq_qoffset 47:32\n iqm2ipt_cnm_eq_qdelta 31:16\n cnm_cell_size ...", 7782 /* IPT_SRAM_DEL_Q */ "DRAM Delete PDQ", 7783 /* IPT_S_2D_DBLF */ "Dequeue Buffer List FIFO", 7784 /* IPT_S_2D_DQCF */ "Dequeue Command FIFO", 7785 /* IPT_S_2D_PEND_BUFF_FIFO */ "Hold start buffers pending for RPC", 7786 /* IPT_TDM_BIT_MAPPING_2_FDT */ "This table maps the incoming index, build from various packet parameters to 1 bit TDM send to the FDT.\n The fields building the input of the table are:\n iqm2ipt_hp, iqm2ipt_mc, ftmh2ipt_dp(2bits), ftmh2ipt_trfcls(3bits), is_pkt_tdm(q_sig)", 7787 /* IPV4_IN_IPV6_PREFIX_MATCH_TABLE */ "IPv6 in IPv6 Address Prefix Matching Memory", 7788 /* IPV6_PROXY_ENABLE_TABLE */ "Source Trunk Map Table", 7789 /* IP_MULTICAST_TCAM */ "IP Multicast TCAM..", 7790 /* IP_OPTION_CONTROL_PROFILE_TABLE */ "Actions on IP packets with options. Indexed by L3_IIF.IP_OPTION_PROFILE_INDEX(2 bits) + IP option number (8 bits)", 7791 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_0 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7792 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_1 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7793 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_2 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7794 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_3 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7795 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_4 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7796 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_5 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7797 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_6 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7798 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_7 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7799 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_8 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7800 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_9 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7801 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_10 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7802 /* IP_PARSER0_HFE_CONT_PROFILE_TABLE_11 */ "Parser IP_PARSER0 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7803 /* IP_PARSER0_HFE_POLICY_TABLE_0 */ "Parser IP_PARSER0 This table provides HFE commands for stage ITER_I", 7804 /* IP_PARSER0_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_0 */ "Parser IP_PARSER0 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7805 /* IP_PARSER0_HME_STAGE_TCAM_DATA_ONLY_0 */ "Parser IP_PARSER0 Primary policy associated with TCAM for data lookup", 7806 /* IP_PARSER0_HME_STAGE_TCAM_NARROW_ONLY_0 */ "Parser IP_PARSER0 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7807 /* IP_PARSER0_HME_STAGE_TCAM_ONLY_0 */ "Parser IP_PARSER0 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7808 /* IP_PARSER0_HVE_RC_PROFILE_0 */ "Parser IP_PARSER0 Range Comparator-ITER_I Profile Table Entry", 7809 /* IP_PARSER0_HVE_RC_PROFILE_1 */ "Parser IP_PARSER0 Range Comparator-ITER_I Profile Table Entry", 7810 /* IP_PARSER0_HVE_SCC_PROFILE_0 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7811 /* IP_PARSER0_HVE_SCC_PROFILE_1 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7812 /* IP_PARSER0_HVE_SCC_PROFILE_2 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7813 /* IP_PARSER0_HVE_SCC_PROFILE_3 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7814 /* IP_PARSER0_HVE_SCC_PROFILE_4 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7815 /* IP_PARSER0_HVE_SCC_PROFILE_5 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7816 /* IP_PARSER0_HVE_SCC_PROFILE_6 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7817 /* IP_PARSER0_HVE_SCC_PROFILE_7 */ "Parser IP_PARSER0 Semantic Check Config-ITER_I Profile Table Entry", 7818 /* IP_PARSER0_HVE_SCF_PROFILE_0 */ "Parser IP_PARSER0 Semantic Check Field-ITER_I Profile Table Entry", 7819 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_0 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7820 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_1 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7821 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_2 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7822 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_3 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7823 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_4 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7824 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_5 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7825 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_6 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7826 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_7 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7827 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_8 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7828 /* IP_PARSER1_HFE_CONT_PROFILE_TABLE_9 */ "Parser IP_PARSER1 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7829 /* IP_PARSER1_HFE_POLICY_TABLE_0 */ "Parser IP_PARSER1 This table provides HFE commands for stage ITER_I", 7830 /* IP_PARSER1_HFE_POLICY_TABLE_1 */ "Parser IP_PARSER1 This table provides HFE commands for stage ITER_I", 7831 /* IP_PARSER1_HFE_POLICY_TABLE_2 */ "Parser IP_PARSER1 This table provides HFE commands for stage ITER_I", 7832 /* IP_PARSER1_HFE_POLICY_TABLE_3 */ "Parser IP_PARSER1 This table provides HFE commands for stage ITER_I", 7833 /* IP_PARSER1_HFE_POLICY_TABLE_4 */ "Parser IP_PARSER1 This table provides HFE commands for stage ITER_I", 7834 /* IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_0 */ "Parser IP_PARSER1 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7835 /* IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_1 */ "Parser IP_PARSER1 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7836 /* IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_2 */ "Parser IP_PARSER1 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7837 /* IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_3 */ "Parser IP_PARSER1 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7838 /* IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_4 */ "Parser IP_PARSER1 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7839 /* IP_PARSER1_HME_STAGE_TCAM_DATA_ONLY_0 */ "Parser IP_PARSER1 Primary policy associated with TCAM for data lookup", 7840 /* IP_PARSER1_HME_STAGE_TCAM_DATA_ONLY_1 */ "Parser IP_PARSER1 Primary policy associated with TCAM for data lookup", 7841 /* IP_PARSER1_HME_STAGE_TCAM_DATA_ONLY_2 */ "Parser IP_PARSER1 Primary policy associated with TCAM for data lookup", 7842 /* IP_PARSER1_HME_STAGE_TCAM_DATA_ONLY_3 */ "Parser IP_PARSER1 Primary policy associated with TCAM for data lookup", 7843 /* IP_PARSER1_HME_STAGE_TCAM_DATA_ONLY_4 */ "Parser IP_PARSER1 Primary policy associated with TCAM for data lookup", 7844 /* IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_0 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7845 /* IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_1 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7846 /* IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_2 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7847 /* IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_3 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7848 /* IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_4 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7849 /* IP_PARSER1_HME_STAGE_TCAM_ONLY_0 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7850 /* IP_PARSER1_HME_STAGE_TCAM_ONLY_1 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7851 /* IP_PARSER1_HME_STAGE_TCAM_ONLY_2 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7852 /* IP_PARSER1_HME_STAGE_TCAM_ONLY_3 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7853 /* IP_PARSER1_HME_STAGE_TCAM_ONLY_4 */ "Parser IP_PARSER1 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7854 /* IP_PARSER1_HVE_RC_PROFILE_0 */ "Parser IP_PARSER1 Range Comparator-ITER_I Profile Table Entry", 7855 /* IP_PARSER1_HVE_RC_PROFILE_1 */ "Parser IP_PARSER1 Range Comparator-ITER_I Profile Table Entry", 7856 /* IP_PARSER1_HVE_SCC_PROFILE_0 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7857 /* IP_PARSER1_HVE_SCC_PROFILE_1 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7858 /* IP_PARSER1_HVE_SCC_PROFILE_2 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7859 /* IP_PARSER1_HVE_SCC_PROFILE_3 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7860 /* IP_PARSER1_HVE_SCC_PROFILE_4 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7861 /* IP_PARSER1_HVE_SCC_PROFILE_5 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7862 /* IP_PARSER1_HVE_SCC_PROFILE_6 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7863 /* IP_PARSER1_HVE_SCC_PROFILE_7 */ "Parser IP_PARSER1 Semantic Check Config-ITER_I Profile Table Entry", 7864 /* IP_PARSER1_HVE_SCF_PROFILE_0 */ "Parser IP_PARSER1 Semantic Check Field-ITER_I Profile Table Entry", 7865 /* IP_PARSER1_MICE_DEBUG_STATUS_0 */ "Parser IP_PARSER1", 7866 /* IP_PARSER1_MICE_DEBUG_STATUS_1 */ "Parser IP_PARSER1", 7867 /* IP_PARSER1_MICE_DEBUG_STATUS_0_PIPE0 */ "Parser IP_PARSER1", 7868 /* IP_PARSER1_MICE_DEBUG_STATUS_0_PIPE1 */ "Parser IP_PARSER1", 7869 /* IP_PARSER1_MICE_DEBUG_STATUS_1_PIPE0 */ "Parser IP_PARSER1", 7870 /* IP_PARSER1_MICE_DEBUG_STATUS_1_PIPE1 */ "Parser IP_PARSER1", 7871 /* IP_PARSER1_MICE_TCAM_0 */ "Parser IP_PARSER1 Primary TCAM for stage match id lookup", 7872 /* IP_PARSER1_MICE_TCAM_1 */ "Parser IP_PARSER1 Primary TCAM for stage match id lookup", 7873 /* IP_PARSER1_MICE_TCAM_DATA_ONLY_0 */ "Parser IP_PARSER1 Primary TCAM for stage match id lookup", 7874 /* IP_PARSER1_MICE_TCAM_DATA_ONLY_1 */ "Parser IP_PARSER1 Primary TCAM for stage match id lookup", 7875 /* IP_PARSER1_MICE_TCAM_ONLY_0 */ "Parser IP_PARSER1 Primary TCAM for stage match id lookup", 7876 /* IP_PARSER1_MICE_TCAM_ONLY_1 */ "Parser IP_PARSER1 Primary TCAM for stage match id lookup", 7877 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_0 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7878 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_1 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7879 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_2 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7880 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_3 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7881 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_4 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7882 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_5 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7883 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_6 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7884 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_7 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7885 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_8 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7886 /* IP_PARSER2_HFE_CONT_PROFILE_TABLE_9 */ "Parser IP_PARSER2 This table provides HFE Container Profile Data for container with profile ID ITER_I", 7887 /* IP_PARSER2_HFE_POLICY_TABLE_0 */ "Parser IP_PARSER2 This table provides HFE commands for stage ITER_I", 7888 /* IP_PARSER2_HFE_POLICY_TABLE_1 */ "Parser IP_PARSER2 This table provides HFE commands for stage ITER_I", 7889 /* IP_PARSER2_HFE_POLICY_TABLE_2 */ "Parser IP_PARSER2 This table provides HFE commands for stage ITER_I", 7890 /* IP_PARSER2_HFE_POLICY_TABLE_3 */ "Parser IP_PARSER2 This table provides HFE commands for stage ITER_I", 7891 /* IP_PARSER2_HFE_POLICY_TABLE_4 */ "Parser IP_PARSER2 This table provides HFE commands for stage ITER_I", 7892 /* IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_0 */ "Parser IP_PARSER2 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7893 /* IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_1 */ "Parser IP_PARSER2 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7894 /* IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_2 */ "Parser IP_PARSER2 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7895 /* IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_3 */ "Parser IP_PARSER2 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7896 /* IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE_4 */ "Parser IP_PARSER2 This memory provides bytes to be check for generation valid_byte_vector in HME key", 7897 /* IP_PARSER2_HME_STAGE_TCAM_DATA_ONLY_0 */ "Parser IP_PARSER2 Primary policy associated with TCAM for data lookup", 7898 /* IP_PARSER2_HME_STAGE_TCAM_DATA_ONLY_1 */ "Parser IP_PARSER2 Primary policy associated with TCAM for data lookup", 7899 /* IP_PARSER2_HME_STAGE_TCAM_DATA_ONLY_2 */ "Parser IP_PARSER2 Primary policy associated with TCAM for data lookup", 7900 /* IP_PARSER2_HME_STAGE_TCAM_DATA_ONLY_3 */ "Parser IP_PARSER2 Primary policy associated with TCAM for data lookup", 7901 /* IP_PARSER2_HME_STAGE_TCAM_DATA_ONLY_4 */ "Parser IP_PARSER2 Primary policy associated with TCAM for data lookup", 7902 /* IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_0 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7903 /* IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_1 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7904 /* IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_2 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7905 /* IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_3 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7906 /* IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_4 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses NARROW key. To use this veiw hme_stage_config.tcam_mode should be set to Deep.", 7907 /* IP_PARSER2_HME_STAGE_TCAM_ONLY_0 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7908 /* IP_PARSER2_HME_STAGE_TCAM_ONLY_1 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7909 /* IP_PARSER2_HME_STAGE_TCAM_ONLY_2 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7910 /* IP_PARSER2_HME_STAGE_TCAM_ONLY_3 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7911 /* IP_PARSER2_HME_STAGE_TCAM_ONLY_4 */ "Parser IP_PARSER2 Primary TCAM for data lookup. This uses full key. To use this veiw hme_stage_config.tcam_mode should be set to wide.", 7912 /* IP_PARSER2_HVE_RC_PROFILE_0 */ "Parser IP_PARSER2 Range Comparator-ITER_I Profile Table Entry", 7913 /* IP_PARSER2_HVE_RC_PROFILE_1 */ "Parser IP_PARSER2 Range Comparator-ITER_I Profile Table Entry", 7914 /* IP_PARSER2_HVE_SCC_PROFILE_0 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7915 /* IP_PARSER2_HVE_SCC_PROFILE_1 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7916 /* IP_PARSER2_HVE_SCC_PROFILE_2 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7917 /* IP_PARSER2_HVE_SCC_PROFILE_3 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7918 /* IP_PARSER2_HVE_SCC_PROFILE_4 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7919 /* IP_PARSER2_HVE_SCC_PROFILE_5 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7920 /* IP_PARSER2_HVE_SCC_PROFILE_6 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7921 /* IP_PARSER2_HVE_SCC_PROFILE_7 */ "Parser IP_PARSER2 Semantic Check Config-ITER_I Profile Table Entry", 7922 /* IP_PARSER2_HVE_SCF_PROFILE_0 */ "Parser IP_PARSER2 Semantic Check Field-ITER_I Profile Table Entry", 7923 /* IP_PARSER2_MICE_DEBUG_STATUS_0 */ "Parser IP_PARSER2", 7924 /* IP_PARSER2_MICE_DEBUG_STATUS_1 */ "Parser IP_PARSER2", 7925 /* IP_PARSER2_MICE_DEBUG_STATUS_0_PIPE0 */ "Parser IP_PARSER2", 7926 /* IP_PARSER2_MICE_DEBUG_STATUS_0_PIPE1 */ "Parser IP_PARSER2", 7927 /* IP_PARSER2_MICE_DEBUG_STATUS_1_PIPE0 */ "Parser IP_PARSER2", 7928 /* IP_PARSER2_MICE_DEBUG_STATUS_1_PIPE1 */ "Parser IP_PARSER2", 7929 /* IP_PARSER2_MICE_TCAM_0 */ "Parser IP_PARSER2 Primary TCAM for stage match id lookup", 7930 /* IP_PARSER2_MICE_TCAM_1 */ "Parser IP_PARSER2 Primary TCAM for stage match id lookup", 7931 /* IP_PARSER2_MICE_TCAM_DATA_ONLY_0 */ "Parser IP_PARSER2 Primary TCAM for stage match id lookup", 7932 /* IP_PARSER2_MICE_TCAM_DATA_ONLY_1 */ "Parser IP_PARSER2 Primary TCAM for stage match id lookup", 7933 /* IP_PARSER2_MICE_TCAM_ONLY_0 */ "Parser IP_PARSER2 Primary TCAM for stage match id lookup", 7934 /* IP_PARSER2_MICE_TCAM_ONLY_1 */ "Parser IP_PARSER2 Primary TCAM for stage match id lookup", 7935 /* IP_PROTO_MAP */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7936 /* IP_PROTO_MAP_PIPE0 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7937 /* IP_PROTO_MAP_PIPE1 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7938 /* IP_PROTO_MAP_PIPE2 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7939 /* IP_PROTO_MAP_PIPE3 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7940 /* IP_PROTO_MAP_PIPE4 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7941 /* IP_PROTO_MAP_PIPE5 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7942 /* IP_PROTO_MAP_PIPE6 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7943 /* IP_PROTO_MAP_PIPE7 */ "This Data Structure is used to compress the 8b IP Protocol field from the packet into a 4b field.", 7944 /* IP_TO_INT_CN_MAPPING */ "Mapping for IP ECN to INT_CN.", 7945 /* IP_UAT_16K_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 7946 /* IP_UAT_8K_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 7947 /* IP_UAT_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 7948 /* IQMT_BDBLL */ "BDB Link List\n BDB-ptr18:0", 7949 /* IQMT_EGR_RPT_CPM */ "CTR Header-Compensation:\n In-PP-Port-Profile(4) -> CTR-Header-Compensation", 7950 /* IQMT_EGR_RPT_HAPM */ "CTR Header-Compensation:\n Header-Append-Ptr -> Header-Apeend-Ptr-Compensation", 7951 /* IQMT_EGR_RPT_PCM */ "CTR Header-Compensation:\n In-PP-Port -> Ctr-Hdr-Cmp-Profile table", 7952 /* IQMT_FLUSCNT */ "Full Multicast User Count\n Number of duplications of the FullMulticast Dbuffs (UserCnt+1).", 7953 /* IQMT_ING_RPT_CPM */ "CTR Header-Compensation:\n In-PP-Port-Profile(4) -> CTR-Header-Compensation", 7954 /* IQMT_ING_RPT_HAPM */ "CTR Header-Compensation:\n Header-Append-Ptr -> Header-Apeend-Ptr-Compensation", 7955 /* IQMT_ING_RPT_PCM */ "CTR Header-Compensation:\n In-PP-Port -> Ctr-Hdr-Cmp-Profile table", 7956 /* IQMT_MEM_300000 */ "INTERNAL", 7957 /* IQMT_MNUSCNT */ "Mini Multicast User Count\n Number of duplications of the MiniMulticast Dbuffs (UserCnt+1).", 7958 /* IQMT_PDM_0 */ "Packet descriptor memory. Bank 0", 7959 /* IQMT_PDM_1 */ "Packet descriptor memory. Bank 1", 7960 /* IQMT_PDM_2 */ "Packet descriptor memory. Bank 2", 7961 /* IQMT_PDM_3 */ "Packet descriptor memory. Bank 3", 7962 /* IQMT_PDM_4 */ "Packet descriptor memory. Bank 4", 7963 /* IQMT_PDM_5 */ "Packet descriptor memory. Bank 5", 7964 /* IQM_AUTO_DOC_NAME_11 */ "INTERNAL", 7965 /* IQM_AUTO_DOC_NAME_12 */ "INTERNAL", 7966 /* IQM_AUTO_DOC_NAME_13 */ "INTERNAL", 7967 /* IQM_AUTO_DOC_NAME_14 */ "INTERNAL", 7968 /* IQM_AUTO_DOC_NAME_15 */ "INTERNAL", 7969 /* IQM_BDBLL */ "BDB Link List\n BDB-ptr17:0", 7970 /* IQM_CNG_QUE_SET */ "Congested Queue set (Dynamic)\n The array of 8 values presents the 8 most ocngested Queues and their Qsize.\n The array can be set to monitor Queues ocngestion based on buffers (Dbuffs or Bds) by asserting CngqOnBuffEn.\n Reading should start from offset 0 (freeze the 8 values, and end at offset 7, release the set for further updates).\n Note:\n - This is a status array.\n - during reading the ...", 7971 /* IQM_CNRED */ "CNI (Congestion Notification Indication) WRED and drop threshold table.\n Accessed by Q's Rate-Class during DEQUEUE process, to define the CNI indication of the packet.\n Note: the table does not define packet reject options.", 7972 /* IQM_CNTCMD_CPM */ "CTR Header-Compensation:\n In-PP-Port-Profile(4) -> CTR-Header-Compensation", 7973 /* IQM_CNTCMD_HAPM */ "CTR Header-Compensation:\n Header-Append-Ptr -> Header-Apeend-Ptr-Compensation", 7974 /* IQM_CNTCMD_PCM */ "CTR Header-Compensation:\n In-PP-Port -> Ctr-Hdr-Cmp-Profile table", 7975 /* IQM_CPDMD */ "Congestion point (CP) queue descriptor ( Dynamic )\n (per each CP Queue number out of 4K, CNM logic)\n updated by the CNM logic.", 7976 /* IQM_CPDMD_SMP_OFF */ "Congestion point (CP) queue descriptor ( Dynamic )\n (per each CP Queue number out of 4K, CNM logic)\n updated by the CNM logic.\n Table description for Sampling-Mode OFF", 7977 /* IQM_CPDMD_SMP_ON */ "Congestion point (CP) queue descriptor ( Dynamic )\n (per each CP Queue number out of 4K, CNM logic)\n updated by the CNM logic.\n Table description for Sampling-Mode ON", 7978 /* IQM_CPDMS */ "Congestion point (CP) queue descriptor ( static )\n (per each CP Queue number out of 4K, CNM logic)\n In Sampling mode, bit assignment is changed:\n Bit 0 - CpEn1\n Bits 3:1 - CpClass12:0\n Bit 4 - CpEn2\n Bits 7:5 - CpClass2:0", 7979 /* IQM_CPDMS_SMP_OFF */ "Congestion point (CP) queue descriptor ( static )\n (per each CP Queue number out of 4K, CNM logic)", 7980 /* IQM_CPDMS_SMP_ON */ "Congestion point (CP) queue descriptor ( static )\n (per each CP Queue number out of 4K, CNM logic)", 7981 /* IQM_CPPRM */ "Congestion point (CP) parameters table\n (per each CpClass , CNM logic )", 7982 /* IQM_CRDTDIS */ "Credit Discount\n A value that is discounted from the packet size on packet Dequeue (per Q's credit-class).", 7983 /* IQM_DBFFM */ "Dbuff FIFO memory", 7984 /* IQM_DELFFM */ "Delete Dbuff FIFO memory", 7985 /* IQM_DEQ_FRDB */ "IPT_FRDB_RXI", 7986 /* IQM_ENQ_FRDB */ "IRR_RXI_MEM", 7987 /* IQM_FADTT */ "Free resource VOQ max threshold. (VOQ max threshold based on free resources).\n FreeMax-Th = Parameter*(Free-Resource >> FrRsrcMaxTh)\n (per Q's Rate-Class and DP).", 7988 /* IQM_FLUSCNT */ "Full Multicast User Count\n Number of duplications of the FullMulticast Dbuffs (UserCnt+1).", 7989 /* IQM_FRDMT */ "Free resource VOQ max threshold. (VOQ max threshold based on free resources).\n FreeMax-Th = Parameter*(Free-Resource >> FrRsrcMaxTh)\n (per Q's Rate-Class and DP).", 7990 /* IQM_GRSPRM */ "Guaranteed Space Parameters (static)\n The table containes the guaranteed space defined for each Q, in Bytes, Buffers and Bdbs.\n Q bellow these thresholds will accept packets regardless to WRED decisions.\n (per each Q's Rate-class5:0)", 7991 /* IQM_IPPPM */ "In-PP-Port to NifPort (static)\n Maps incoming PP-Port7:0 to VSQs", 7992 /* IQM_IQM_READ_PENDING_FIFO */ "INTERNAL", 7993 /* IQM_IRPP_CNTCMD_CPM */ "IRPP-CTR Header-Compensation:\n In-PP-Port-Profile(4) -> CTR-Header-Compensation", 7994 /* IQM_IRPP_CNTCMD_HAPM */ "IRPP-CTR Header-Compensation:\n Header-Append-Ptr -> Header-Apeend-Ptr-Compensation", 7995 /* IQM_IRPP_CNTCMD_PCM */ "IRPP-CTR Header-Compensation:\n In-PP-Port -> Ctr-Hdr-Cmp-Profile table", 7996 /* IQM_IRR_RXI */ "IRR_RXI_MEM", 7997 /* IQM_ITMPM */ "ItmPort to NifPort (static)\n Maps incominf TM-port7:0 to Nif-Port4:0.\n This is needed to define the PFC-VSQ and LLFC-VSQ pointers, which are based on NIF-Port.", 7998 /* IQM_MC_FADTT */ "Fair adaptive dynamic threshold table.\n (VOQ dynamic threshold based on free resources).\n (per Q's Rate-Class and DP).\n\n Parameter = 2^(FadtExpSign*FadtExpVal)\n FADT-Threshold = Free-Resource*Parameter", 7999 /* IQM_MEM_1400000 */ "INTERNAL", 8000 /* IQM_MEM_1600000 */ "INTERNAL", 8001 /* IQM_MEM_1800000 */ "INTERNAL", 8002 /* IQM_MEM_8000000 */ "INTERNAL", 8003 /* IQM_MEM_9600000 */ "INTERNAL", 8004 /* IQM_MEM_9700000 */ "INTERNAL", 8005 /* IQM_MEM_7E00000 */ "INTERNAL", 8006 /* IQM_MNUSCNT */ "Mini Multicast User Count\n Number of duplications of the MiniMulticast Dbuffs (UserCnt+1).", 8007 /* IQM_NIFTCM */ "NifPort+TC mapping (static)\n Maps NifPort4:0TC2:0 to PFC-TC2:0\n The original TC is based on the Q's TC (from PQDMS), the mapped TC is used to define the PFC-VSQ (priority flow control).", 8008 /* IQM_OCBPRM */ "OCB Queue params table (static)\n Per Q-Category1:0,Q-RC5:0Q-TC2:0\n Defines per Q, OCB related parametrs.\n Used to define the report to the IDR on each Q's eligibility to use OCB buffers.", 8009 /* IQM_PACK_MODE */ "Packing mode (per destination ID).\n Note: Each entry holds packing mode of 16 devices.\n Access with dest_id11:4", 8010 /* IQM_PAKCET_DESCRIPTOR_MEMORY_A_DYNAMIC */ "Packet descriptor memory\n The memory is devided to continues ranges of buffer descriptors.\n Each buffer descriptor can hold Dbuff information or CUD of types\n ISP-CUD\n IPT-CUD\n Statistics\n Relevant for entries: 0 - 11FFFF", 8011 /* IQM_PAKCET_DESCRIPTOR_MEMORY_B_DYNAMIC */ "Packet descriptor memory\n The memory is devided to continues ranges of buffer descriptors.\n Each buffer descriptor can hold Dbuff information or CUD of types\n ISP-CUD\n IPT-CUD\n Statistics\n Relevant for entries: 0 - 11FFFF", 8012 /* IQM_PAKCET_DESCRIPTOR_MEMORY_ECC_DYNAMIC */ "Packet descriptor memory\n The memory is devided to continues ranges of buffer descriptors.\n Each buffer descriptor can hold Dbuff information or CUD of types\n ISP-CUD\n IPT-CUD\n Statistics\n Relevant for entries: 0 - 11FFFF", 8013 /* IQM_PDM */ "Packet descriptor memory\n The memory is devided to continues ranges of buffer descriptors.\n Each buffer descriptor can hold Dbuff information or CUD of types\n ISP-CUD\n IPT-CUD\n Statistics\n Relevant for entries: 0 - 11FFFF", 8014 /* IQM_PG_TC_BITMAP */ "Map IQM-TC to PG offset.\n Mapping of IPPPM.PgTcBitmapIndex, TC to VSQ-PG-TC.\n VSQ-PG = In-PP-Port.VSQ-Base + VSQ-PG-TC", 8015 /* IQM_PQDMD */ "Packet Queue Descriptor Dynamic fields", 8016 /* IQM_PQDMS */ "Packet Queue Descriptor Static bits", 8017 /* IQM_PQRED */ "Packet Queue Red parameters\n Per Q Rate Class and Drop-p.", 8018 /* IQM_PQWQ */ "Packet Queue Average Weight\n Accessed according to the Queue's Rate-Class5:0.", 8019 /* IQM_SCH_CCCP */ "SCH Header-Compensation:\n Credit-Class to Sch-Cmp-Profile table", 8020 /* IQM_SCH_CPM */ "SCH Header-Compensation:\n CcSchHdrCmpProfile(3), IppSchHdrCmpProfile(3) -> SCH-Header-Compensation", 8021 /* IQM_SCH_HAPM */ "SCH Header-Compensation:\n Header-Append-Ptr -> Header-Apeend-Ptr-Compensation", 8022 /* IQM_SCH_HCE */ "SCH Header-Compensation: Header-Compensation encoding table", 8023 /* IQM_SCH_PCM */ "SCH Header-Compensation:\n In-PP-Port -> SCH-Hdr-Cmp-Profile table", 8024 /* IQM_SCRBUFFTH */ "Scrubber buffer thresholds (Static)\n Each entry include buffer thresholds to be compared to occupied or free buffer counters, this defines the Global-Buffer-Consumption field in the scrubber statistics report (used in Qsize statistics report mode).\n The thresholds define 16 ranges of buffer occupancy.\n Each line coresponds to another level of thresholds.\n The IQM will present the worst result of the 3 buffers types.\n ...", 8025 /* IQM_SPRDPRM */ "System Red parameters: defines the reject test parameters (per Q rate-class and Drop-p).", 8026 /* IQM_SRCQRNG */ "Source Q size range thresholds.\n Defines 16 ranges of the instantaneous Qsizes that define the 4-bit System-Q-size value (per Q rate-class)\n Qsize below QszRngThN is defined with source-Q-size N.\n Note:Units of 16 bytes,the value is compared to the Qsize with maximal value of 2^2416 byte.", 8027 /* IQM_SRDPRB */ "System Red drop-probability values.", 8028 /* IQM_TAIL */ "Packet Queue Tail pointer\n This is the BDB,Offset where the last packet Dbuff has been written.", 8029 /* IQM_VQFCPR_MA */ "Flow Control parameters (Per Rate-Class3:0)\n\n VSQs: 0->3", 8030 /* IQM_VQFCPR_MB */ "Flow Control parameters (Per Rate-Class3:0)\n VSQs: 4->35\n The table should have the same values as VQFCPRMa.", 8031 /* IQM_VQFCPR_MC */ "Flow Control parameters (Per Rate-Class3:0)\n VSQs: 36->99\n The table should have the same values as VQFCPRMa.", 8032 /* IQM_VQFCPR_MD */ "Flow Control parameters (Per Rate-Class3:0)\n VSQs: 100->355\n The table should have the same values as VQFCPRMa.", 8033 /* IQM_VQFCPR_ME */ "Flow Control parameters (Per Rate-Class3:0)\n VSQs: 356->387\n The table should have the same values as VQFCPRMa.", 8034 /* IQM_VQFCPR_MF */ "Flow Control parameters (Per Rate-Class3:0)\n VSQs: 388->643\n The table should have the same values as VQFCPRMa.", 8035 /* IQM_VQPR_MA */ "Virtual Q parameters (Per Rate-Class3:0Drop-p1:0)\n Tail Drop thresholds &\n Red Parameters\n P-Drop(red) = (c1*AvgSize-c2)*PcktSize*c3\n VSQs: 0->3", 8036 /* IQM_VQPR_MB */ "Virtual Q parameters (Per Rate-Class3:0Drop-p1:0)\n MaxInstQsizeWords\n MaxInstQsizeBds\n Red Parameters\n VSQs: 4->35\n The table should have the same values as VQPRMa.", 8037 /* IQM_VQPR_MC */ "Virtual Q parameters (Per Rate-Class3:0Drop-p1:0)\n VSQs: 36->99\n The table should have the same values as VQPRMa.", 8038 /* IQM_VQPR_MD */ "Virtual Q parameters (Per Rate-Class3:0Drop-p1:0)\n VSQs: 100->355\n The table should have the same values as VQPRMa.", 8039 /* IQM_VQPR_ME */ "Virtual Q parameters (Per Rate-Class3:0Drop-p1:0)\n VSQs: 356->387\n The table should have the same values as VQPRMa.", 8040 /* IQM_VQPR_MF */ "Virtual Q parameters (Per Rate-Class3:0Drop-p1:0)\n VSQs: 388->643\n The table should have the same values as VQPRMa.", 8041 /* IQM_VSQA_AVRG */ "Average size memory.\n VSQs: 0 -> 3 (MIXED)\n VSQs: 4 -> 7 (OCB-Only)", 8042 /* IQM_VSQA_FC_PRM */ "Flow Control parameters for VSQA.\n (Per VSQ-Rate-Class4:0)", 8043 /* IQM_VSQA_MX_OC */ "VSQ-A Max occupancy level", 8044 /* IQM_VSQA_PQWQ */ "VSQ Red Weight table - Group A\n (Per Rate-Class4:0)", 8045 /* IQM_VSQA_PRM */ "VSQ reject parameters\n (Per Rate-Class4:0Drop-p1:0)", 8046 /* IQM_VSQA_QSZ */ "Instantaneous size memory.\n VSQs: 0 -> 3 (MIXED)\n VSQs: 4 -> 7 (OCB-Only)", 8047 /* IQM_VSQA_RC */ "Virtual Queue Descriptor Rate Class\n VSQs: 0->3", 8048 /* IQM_VSQB_AVRG */ "Average size memory.\n VSQs: 8 -> 39 (MIXED)\n VSQs: 40 -> 71 (OCB-Only)", 8049 /* IQM_VSQB_FC_PRM */ "Flow Control parameters for VSQB.\n (Per VSQ-Rate-Class4:0)", 8050 /* IQM_VSQB_MX_OC */ "VSQ-B Max occupancy level", 8051 /* IQM_VSQB_PQWQ */ "VSQ Red Weight table - Group B\n (Per Rate-Class4:0)", 8052 /* IQM_VSQB_PRM */ "VSQ reject parameters\n (Per Rate-Class4:0Drop-p1:0)", 8053 /* IQM_VSQB_QSZ */ "Instantaneous size memory.\n VSQs: 8 -> 39 (MIXED)\n VSQs: 40 -> 71 (OCB-Only)", 8054 /* IQM_VSQB_RC */ "Rate class.\n Used to access parameter tables.", 8055 /* IQM_VSQC_AVRG */ "Average size memory.\n VSQs: 72 -> 135 (MIXED)\n VSQs: 136 -> 199 (OCB-Only)", 8056 /* IQM_VSQC_FC_PRM */ "Flow Control parameters for VSQC.\n (Per VSQ-Rate-Class4:0)", 8057 /* IQM_VSQC_MX_OC */ "VSQ-C Max occupancy level", 8058 /* IQM_VSQC_PQWQ */ "VSQ Red Weight table - Group C\n (Per Rate-Class4:0)", 8059 /* IQM_VSQC_PRM */ "VSQ reject parameters\n (Per Rate-Class4:0Drop-p1:0)", 8060 /* IQM_VSQC_QSZ */ "Instantaneous size memory.\n VSQs: 72 -> 135 (MIXED)\n VSQs: 136 -> 199 (OCB-Only)", 8061 /* IQM_VSQC_RC */ "Virtual Queue Descriptor Rate Class", 8062 /* IQM_VSQDRC_A */ "Virtual Queue Descriptor Rate Class\n VSQs: 0->3", 8063 /* IQM_VSQDRC_B */ "Rate class.\n Used to access parameter tables.", 8064 /* IQM_VSQDRC_C */ "Virtual Queue Descriptor Rate Class", 8065 /* IQM_VSQDRC_D */ "Virtual Queue Descriptor Rate Class", 8066 /* IQM_VSQDRC_E */ "Virtual Queue Descriptor Rate Class", 8067 /* IQM_VSQDRC_F */ "Virtual Queue Descriptor Rate Class", 8068 /* IQM_VSQD_AVRG */ "Average size memory.\n VSQs: 200 -> 455 (MIXED)\n VSQs: 456 -> 711 (OCB-Only)", 8069 /* IQM_VSQD_FC_PRM */ "Flow Control parameters for VSQD.\n (Per VSQ-Rate-Class4:0)", 8070 /* IQM_VSQD_MX_OC */ "VSQ-D Max occupancy level", 8071 /* IQM_VSQD_PQWQ */ "VSQ Red Weight table - Group D\n (Per Rate-Class4:0)", 8072 /* IQM_VSQD_PRM */ "VSQ reject parameters\n (Per Rate-Class4:0Drop-p1:0)", 8073 /* IQM_VSQD_QSZ */ "Instantaneous size memory.\n VSQs: 200 -> 455 (MIXED)\n VSQs: 456 -> 711 (OCB-Only)", 8074 /* IQM_VSQD_RC */ "Virtual Queue Descriptor Rate Class", 8075 /* IQM_VSQE_AVRG */ "Average size memory.\n VSQs: 712 -> 839 (MIXED)\n VSQs: 840 -> 967 (OCB-Only)", 8076 /* IQM_VSQE_FC_PRM */ "Flow Control parameters for VSQE.\n (Per VSQ-Rate-Class4:0)\n Table-0 --> Shared-Pool-0\n Table-1 --> Shared-Pool-1", 8077 /* IQM_VSQE_MAP */ "Map VSQ-E to CFC LLFC index\n (Value must be 0-143)", 8078 /* IQM_VSQE_MX_OC */ "VSQ-E Max occupancy level", 8079 /* IQM_VSQE_PQWQ */ "VSQ Red Weight table - Group E\n (Per Rate-Class4:0)", 8080 /* IQM_VSQE_PRM */ "VSQ reject parameters\n (Per Rate-Class4:0Drop-p1:0)\n Table-0 --> Shared-Pool-0\n Table-1 --> Shared-Pool-1", 8081 /* IQM_VSQE_QSZ */ "Instantaneous size memory.\n VSQs: 712 -> 839 (MIXED)\n VSQs: 840 -> 967 (OCB-Only)", 8082 /* IQM_VSQE_RC */ "Virtual Queue Descriptor Rate Class", 8083 /* IQM_VSQF_AVRG */ "Average size memory.\n VSQs: 968 -> 1479 (MIXED/OCB)", 8084 /* IQM_VSQF_FC_PRM */ "Flow Control parameters for VSQF.\n (Per VSQ-Rate-Class4:0).\n Used only if VSQ FADT is disabled (VsqThModeSel is reset)..", 8085 /* IQM_VSQF_MAP */ "Map VSQ-F to CFC PFC index\n (Value must be 0-575)", 8086 /* IQM_VSQF_MX_OC */ "VSQ-F Max occupancy level", 8087 /* IQM_VSQF_PQWQ */ "VSQ Red Weight table - Group F\n (Per Rate-Class4:0)", 8088 /* IQM_VSQF_PRM */ "Virtual Q parameters (Per Rate-Class4:0Drop-p1:0)", 8089 /* IQM_VSQF_QSZ */ "Instantaneous size memory.\n VSQs: 968 -> 1479 (MIXED/OCB)", 8090 /* IQM_VSQF_RC */ "Virtual Queue Descriptor Rate Class", 8091 /* IQM_VSQ_A_MX_OC */ "VSQ-A Max occupancy level", 8092 /* IQM_VSQ_B_MX_OC */ "VSQ-B Max occupancy level", 8093 /* IQM_VSQ_C_MX_OC */ "VSQ-C Max occupancy level", 8094 /* IQM_VSQ_D_MX_OC */ "VSQ-D Max occupancy level", 8095 /* IQM_VSQ_E_MX_OC */ "VSQ-E Max occupancy level", 8096 /* IQM_VSQ_F_MX_OC */ "VSQ-F Max occupancy level", 8097 /* IQM_VSQ_PG_PRM */ "Virtual Q parameters (Per Rate-Class4:0)", 8098 /* IQM_VS_QA_AVG */ "VSQs: 0->3 ,Average Size in 16-bytes resolution.", 8099 /* IQM_VS_QA_QSZ */ "VSQs: 0->3, Instantaneous size memory.", 8100 /* IQM_VS_QB_AVG */ "VSQs: 4->35 ,Average Size in 16-bytes resolution.", 8101 /* IQM_VS_QB_QSZ */ "VSQs: 4->35, Instantaneous size memory.", 8102 /* IQM_VS_QC_AVG */ "VSQs: 36->99 ,Average Size in 16-bytes resolution.", 8103 /* IQM_VS_QC_QSZ */ "VSQs: 36->99, Instantaneous size memory.", 8104 /* IQM_VS_QD_AVG */ "VSQs: 100->355 ,Average Size in 16-bytes resolution.", 8105 /* IQM_VS_QD_QSZ */ "VSQs: 100->355, Instantaneous size memory.", 8106 /* IQM_VS_QE_AVG */ "VSQs: 356->387 ,Average Size in 16-bytes resolution.", 8107 /* IQM_VS_QE_QSZ */ "VSQs: 356->387, Instantaneous size memory.\n LLFC VSQs (NifPort based)", 8108 /* IQM_VS_QF_AVG */ "VSQs: 388->643 ,Average Size in 16-bytes resolution.", 8109 /* IQM_VS_QF_QSZ */ "VSQs: 388>643, Instantaneous size memory.\n PFC VSQs (Based on NifPort,Tc)", 8110 /* IRE_CPU_ARB_MEM */ "Fifo that holds the Data in the CPU arbiter", 8111 /* IRE_CPU_CTXT_MAP */ "CPU interface channel to incoming Context mapping.", 8112 /* IRE_CPU_RXI_MEM */ "Fifo that holds the data received from CPU", 8113 /* IRE_CPU_TDM_CTXT_MAP */ "Map incoming CPU channel to TDM contexts.", 8114 /* IRE_CTXT_MAP */ "Map incoming Port and Channel to contexts.\n Access this table using CtxtMapBaseAddress (the result from PortToBaseAddressMap) + incoming-channel.", 8115 /* IRE_CTXT_MEM_CONTROL */ "Holds the remainder and corresponding status on the alignment process.", 8116 /* IRE_CTXT_MEM_CTRL */ "Holds the remainder and corresponding status on the alignment process.", 8117 /* IRE_CTXT_MEM_DATA */ "Holds the remainder and corresponding status on the alignment process.", 8118 /* IRE_HPF_MEM */ "IHP FIFO memory", 8119 /* IRE_HPF_MEM_CONTROL */ "IHP FIFO memory", 8120 /* IRE_HPF_MEM_DATA */ "IHP FIFO memory", 8121 /* IRE_IPSEC_RXI_MEM */ "Fifo that holds the packet received from Ipsec", 8122 /* IRE_IPV6_SR_CFG */ "IPv6 Segement route configuration per Port Termination Context (PTC)", 8123 /* IRE_LAST_RECEIVED_PACKET */ "Hold the last packet data received on a configured Reassembly context", 8124 /* IRE_MEM_1_INTERNAL */ "INTERNAL", 8125 /* IRE_MEM_2_INTERNAL */ "INTERNAL", 8126 /* IRE_MEM_3_INTERNAL */ "INTERNAL", 8127 /* IRE_MEM_4_INTERNAL */ "INTERNAL", 8128 /* IRE_MEM_5_INTERNAL */ "INTERNAL", 8129 /* IRE_MEM_6_INTERNAL */ "INTERNAL", 8130 /* IRE_MEM_7_INTERNAL */ "INTERNAL", 8131 /* IRE_MEM_8_INTERNAL */ "INTERNAL", 8132 /* IRE_MEM_D0000 */ "INTERNAL", 8133 /* IRE_MEM_F0000 */ "INTERNAL", 8134 /* IRE_NIF_CTXT_MAP */ "Map incoming NIF port and Channel to contexts.\n Access this table using CtxtMapBaseAddress (the result from NifPortMap) + incoming-channel.", 8135 /* IRE_NIF_PORT_ATTR */ "Map incoming NIF port to base address. The NIF port is derived from the data on the NIF interface. Base address plus channel will access CtxtMap. NifPortToCtxtBitMapAddress will access NifPortToCtxtBitMap.", 8136 /* IRE_NIF_PORT_MAP */ "Map incoming nif port to base address. Base address plus nif channel will access nif-ctxt-map", 8137 /* IRE_NIF_PORT_TO_CTXT_BIT_MAP */ "Eight entries. Each entry represents, per MAC lane, a bit map of the associated Incoming FAP ports. Access this table with nif_port5:2", 8138 /* IRE_NIF_RXI_MEM */ "RXI memory", 8139 /* IRE_NIF_RXI_MEM_DATA */ "Fifo that holds the data received from NIF", 8140 /* IRE_NIF_TDM_CTXT_MAP */ "Map incoming NIF port and Channel to TDM contexts.\n Access this table using CtxtMapBaseAddress (the result from PortToBaseAddressMap) + incoming-channel.", 8141 /* IRE_NIF_TDM_RXI_MEM_CONTROL */ "Fifo that holds the data received from NIF", 8142 /* IRE_NIF_TDM_RXI_MEM_DATA */ "Fifo that holds the data received from NIF", 8143 /* IRE_PEF_MEM_CTRL */ "Packet edit FIFO Ctrl", 8144 /* IRE_PEF_MEM_DATA */ "Packet edit FIFO Data", 8145 /* IRE_PKT_SRC_TO_CHANNEL_MAP */ "Map incoming PktSrcId (from CPU interface) to CPU channel.\n Channel plus base address will access CtxtMap and CpuTdmCtxtMap.", 8146 /* IRE_PORT_TO_BASE_ADDRESS_MAP */ "Map incoming NIF/Recycle/CPU port to base address.\n The NIF port is derived from the data on the NIF interface.\n The Recycle ports (EGQ-0 and EGQ-1) are derived from register InterfaceEgqPort.\n The CPU port is derived from register InterfaceCpuPort.\n Base address plus channel will access CtxtMap and NifTdmCtxtMap.\n Address will access NifPortToCtxtBitMap.", 8147 /* IRE_PPLB_CFG */ "INTERNAL", 8148 /* IRE_PP_LOOPBACK_CONFIG */ "Header data and TM command loop-back value per PTC", 8149 /* IRE_RCY_CTXT_MAP */ "Egress Recycling channel to incoming Context mapping.\n Write 8'd255 to an invalid Recycling channel.", 8150 /* IRE_RCY_RXI_MEM */ "Fifo that holds the data received from EGQ", 8151 /* IRE_RCY_RXI_MEM_CONTROL */ "Fifo that holds the data received from EGQ", 8152 /* IRE_RCY_RXI_MEM_DATA */ "Fifo that holds the data received from EGQ", 8153 /* IRE_SAT_RXI_MEM */ "Fifo that holds the packet received from SAT", 8154 /* IRE_SAT_TDM_CTXT_MAP */ "Map incoming SAT channel to TDM contexts.", 8155 /* IRE_TAG_SWAP_0_CFG */ "Tag Swap configuration per Port Termination Context (PTC) for Pipe0", 8156 /* IRE_TAG_SWAP_1_CFG */ "Tag Swap configuration per Port Termination Context (PTC) for Pipe1", 8157 /* IRE_TAG_SWAP_CFG */ "Tag Swap configuration per Port Termination Context (PTC)", 8158 /* IRE_TDM_CONFIG */ "TDM configuration for each reassembly context", 8159 /* IRE_WDF_MEM_CONTROL */ "Word FIFO memory", 8160 /* IRE_WDF_MEM_CTRL */ "Word FIFO memory", 8161 /* IRE_WDF_MEM_DATA */ "Word FIFO memory", 8162 /* IRR_DESTINATION_TABLE */ "This memory maps a system port ID to a queue number and a traffic class profile", 8163 /* IRR_FLOW_TABLE */ "Flow profile per Folw.\n There are 96K flows. Profile per 4 flows.\n Access this table with flow16:4 and pick profile from the entry using flow3:2", 8164 /* IRR_FREE_PCB_MEMORY */ "Free PCB Pointers FIFO Memory", 8165 /* IRR_IRDB */ "Ingress Replication Database.\n For each Multicast ID, this table indicates whether ingress replication is required and whether to use uc buffer for mc packet. If the mc is not ingress mc, the queue resolution is derived from the class field, and the packet is queued to one of the spatial multicast queues.\n Each line in the database holds the indication for 16 multicast IDs.", 8166 /* IRR_ISF_MEMORY */ "Ingress Shaped FIFO Memory", 8167 /* IRR_IS_FREE_PCB_MEMORY */ "Ingress Shaped free PCB Pointers FIFO Memory", 8168 /* IRR_IS_PCB_LINK_TABLE */ "Ingress Shaped PCB Link Table", 8169 /* IRR_IS_PC_MEMORY */ "Ingress Shaped PC Memory", 8170 /* IRR_LAG_MAPPING */ "LAG mapping table.\n Given the LAG and its member specifies the destination.\n Entry into table is LAG, LAG-member.", 8171 /* IRR_LAG_NEXT_MEMBER */ "For LAG resolution, this memory is read, and if it is in round-robin load-balanced mode, the output received is the offset corresponding to the LAG. Note that in this case, the offset is incremented by one and written back to the memory", 8172 /* IRR_LAG_TO_LAG_RANGE */ "LAG range memory table.\n Specifies for each LAG its range", 8173 /* IRR_MCDB */ "128k Ingress Multicast Replication Data Base. (Physically shared with egress MLL table). Each multicast ID can result in up to 4k different copies of the incoming packet at the ingress FAP. Each copy is associated with a configurable Queue/destination System port and an OutLif. Each entry in this table can define 1 such copy, and points to the next entry in the linked list. The OutLif can be further used at the egress FOP as a key for Egress Multicast lookup and can be used by egress Packet Proc ...", 8174 /* IRR_MCDB_EGRESS_FORMAT_0 */ "Generate up to two copies, both having the same OutLIF but different PP-DSP.", 8175 /* IRR_MCDB_EGRESS_FORMAT_1 */ "Generate up to 256 copies, according to the bitmap that is pointed to by the Bitmap-Pointer. All copies get the OutLIF indicated in the entry.", 8176 /* IRR_MCDB_EGRESS_FORMAT_2 */ "Generate up to two copies, each with unique OutLIF and PP-DSP. The PP-DSP is generated by mapping the OutLIF (through a dedicated table). If OutLIF == 0 do not produce copy.", 8177 /* IRR_MCDB_EGRESS_FORMAT_3 */ "Generate up to two copies, each with unique OutLIF and PP-DSP. The PP-DSP is generated by mapping the OutLIF (through a dedicated table). If OutLIF == 0 do not produce copy.", 8178 /* IRR_MCDB_EGRESS_FORMAT_4 */ "Generate up to two copies, each with unique OutLIF and PP-DSP. This entry is end of list.", 8179 /* IRR_MCDB_EGRESS_FORMAT_5 */ "Generate up to two copies, each with unique OutLIF and PP-DSP. Link pointer is implicit to the next incrementing entry.", 8180 /* IRR_MCDB_EGRESS_FORMAT_6 */ "Generate up to three copies, each with unique OutLIF and PP-DSP. The PP-DSP is generated by mapping the OutLIF (through a dedicated table). This entry is end of list.", 8181 /* IRR_MCDB_EGRESS_FORMAT_7 */ "Generate up to three copies, each with unique OutLIF and PP-DSP. The PP-DSP is generated by mapping the OutLIF (through a dedicated table). Link pointer is implicit to the next incrementing entry.", 8182 /* IRR_MCDB_EGRESS_FORMAT_2_PP */ "Set OutRIF(CUD2) for the rest of the following Link List Entries (of type 3-7)", 8183 /* IRR_MCDB_EGRESS_SPECIAL_FORMAT */ "Special Format description.\n If SpecialMcMode register in EGQ is enabled, then the whole MCDB entries are in this format. Otherwise, the format of each entry is determined according to Entry-Format field in each entry.\n If SpecialMcMode is enabled, the access to the MCDB memory is according to the following method:\n 1. MC_ID18:3 is used to select a row from the second half of the MCDB table.\n 2. MC_ID2:0 is used as pointer t ...", 8184 /* IRR_MCDB_EGRESS_TDM_FORMAT */ "Egress TDM Format\n If TdmRepFormatEn is set and the multicast packet is TDM, then the entry pointed by TDM packet will be interpreted as TDM format (this format).", 8185 /* IRR_MCR_MEMORY */ "MCR Memory", 8186 /* IRR_MEM_300000 */ "INTERNAL", 8187 /* IRR_MEM_340000 */ "INTERNAL", 8188 /* IRR_MEM_3C0000 */ "INTERNAL", 8189 /* IRR_PCB_LINK_TABLE */ "PCB Link Table", 8190 /* IRR_PC_MEMORY */ "PC Memory.", 8191 /* IRR_QUEUE_IS_OCB_COMMITTED */ "Stores1 bit per queue number (96k queues) which indicates if the queue is committed to OCB buffers (cannot use DRAM buffers).", 8192 /* IRR_SMOOTH_DIVISION */ "Smooth division is used in lag resolution in case LagToLagRange.Mode == 0 and LagMode == 1024x16. Maps lag-range (from LagToLagRange) and Lag-Lb-Key to Member.\n Access this table with lag-range, lag-lb-key7:1", 8193 /* IRR_SNOOP_MIRROR_DEST_TABLE */ "Snoop and Mirror table. This memory maps the incoming snoop command or mirror command to a replication. The first half is for snoop; the second half is for mirror.\n This table is split into two parts.", 8194 /* IRR_SNOOP_MIRROR_TABLE_0 */ "Snoop and Mirror table. This memory maps the incoming snoop command or mirror command to a replication. The first half is for snoop; the second half is for mirror.\n This table is split into two parts.", 8195 /* IRR_SNOOP_MIRROR_TABLE_1 */ "Snoop and Mirror table. This memory maps the incoming snoop command or mirror command to a replication. First half is for mirror, second half is for snoop.\n This table is split into two parts.\n First line of this table must be set to all 0's.", 8196 /* IRR_SNOOP_MIRROR_TM_TABLE */ "Snoop and Mirror table. This memory maps the incoming snoop command or mirror command to a replication.\n This table is split into two parts: The first half is for mirror; the second half is for snoop.\n First line of this table must be set to all 0's.", 8197 /* IRR_STACK_FEC_RESOLVE */ "Access if UseStackResolve is set and destination is system port and resolved-queue16:6 == 11'h7ff.\n Access with resolved-queue5:0 lag-lb-key7:4\n The resolved StackLag is used to access StackTrunkResolve.", 8198 /* IRR_STACK_TRUNK_RESOLVE */ "Access if UseStackResolve is set and destination is system port and resolved-queue16:6 == 11'h7ff.\n Access with StackLag, lag-lb-key3:0.\n Resolved queue = BaseQueue + Traffic-Class", 8199 /* IRR_TRAFFIC_CLASS_MAPPING */ "The traffic class is mapped according to packet's source and destination. Table is accessed as follows:\n Before ingress shaping:\n line 0,2,4,6 - Destination is System-Port-ID with TC-Mapping-Profile equal to 0,1,2,3 Respectively\n line 8,10,12,14 - Destination is Flow with Flow-Profile equal to 0,1,2,3 Respectively\n line 16 - Destination is fabric or egress multicast\n After ingress shaping:\n ...", 8200 /* IRR_TRAFFIC_CLASS_MAPPING_0 */ "The traffic class is mapped according to packet's source and destination for pipe 0.\n Table is accessed with the following key key_msb,ingress_shape,orig_tc, where:\n * key_msb (4 bits):\n - 2'b00,TC-Mapping-Profile if Destination is System-Port-ID\n - 2'b01,Flow-Profile if Destination is Flow\n - 2'b10,2'b00 if Destination is fabric or egress multicast\n * ingress_shape (1 bit) is '0' be ...", 8201 /* IRR_TRAFFIC_CLASS_MAPPING_1 */ "The traffic class is mapped according to packet's source and destination for pipe 1.\n Table is accessed with the following key key_msb,ingress_shape,orig_tc, where:\n * key_msb (4 bits):\n - 2'b00,TC-Mapping-Profile if Destination is System-Port-ID\n - 2'b01,Flow-Profile if Destination is Flow\n - 2'b10,2'b00 if Destination is fabric or egress multicast\n * ingress_shape (1 bit) is '0' be ...", 8202 /* ISBS_PORT_TO_PIPE_MAPPING */ "SBS Port to Pipe Mapping table.", 8203 /* ISEC_BYPASS_FILTER_TABLE */ "traffic is de-multiplexed into controlled port and uncontrolled port using the filter table. This filter table allows traffic to be separated based on MAC_SA, MAC_DA, ranges of MAC_DA, ranges of MAC_SA or EtherType", 8204 /* ISEC_DEBUG_RAM */ "ISEC DEBUG RAM", 8205 /* ISEC_INMGMTPKTS_COUNT */ "ISEC_Inmgmtpkts Counter", 8206 /* ISEC_MIB0 */ "isec_mib0 ISEC MIB", 8207 /* ISEC_MIB1 */ "isec_mib1 ISEC MIB", 8208 /* ISEC_MIB2 */ "isec_mib2 ISEC MIB", 8209 /* ISEC_MIB0_B */ "isec_mib0_B ISEC MIB fields", 8210 /* ISEC_MISC_COUNTERS */ "ISEC_Debug Counters, per-port", 8211 /* ISEC_SA_KEY_TABLE */ "SA Key table", 8212 /* ISEC_SA_TABLE */ "SA attribute Table", 8213 /* ISEC_SCTCAM_HIT_COUNT */ "ISEC SC TCAM Hit Counter", 8214 /* ISEC_SC_TABLE */ "ISEC SC Index (SCI) Table", 8215 /* ISEC_SC_TCAM */ "ISEC_SC_TCAM", 8216 /* ISEC_SPTCAM_HIT_COUNT */ "ISEC SP TCAM Hit Counter", 8217 /* ISEC_SP_TCAM */ "ISEC_SP_TCAM", 8218 /* ISM_SER_FIFO */ "ISM SER FIFO", 8219 /* IS_TDM_CALENDAR0 */ "TDM Calendar 0,", 8220 /* IS_TDM_CALENDAR1 */ "TDM Calendar 1,", 8221 /* IS_TDM_CALENDAR0_PIPE0 */ "TDM Calendar 0,", 8222 /* IS_TDM_CALENDAR0_PIPE1 */ "TDM Calendar 0,", 8223 /* IS_TDM_CALENDAR0_PIPE2 */ "TDM Calendar 0,", 8224 /* IS_TDM_CALENDAR0_PIPE3 */ "TDM Calendar 0,", 8225 /* IS_TDM_CALENDAR1_PIPE0 */ "TDM Calendar 1,", 8226 /* IS_TDM_CALENDAR1_PIPE1 */ "TDM Calendar 1,", 8227 /* IS_TDM_CALENDAR1_PIPE2 */ "TDM Calendar 1,", 8228 /* IS_TDM_CALENDAR1_PIPE3 */ "TDM Calendar 1,", 8229 /* ITE_ACF */ "Aligner Control FIFO", 8230 /* ITE_BDM */ "Bypass Data Memory", 8231 /* ITE_MAX_LATENCY */ "The ITPP measures latency from the packet OAM-TS extension.\n In this memory the 8 maximal latency's are kept, with the pointer associated with them", 8232 /* ITE_SNP_MIRR_CMD_MAP */ "snoop/mirror command (taken from the CUD) mapped to outlif and dsp extension in the FTMH header\n Address to this table is\n mirror or snoop (1 bit), cmd3:0\n if snoop, addr msb = 1\n if mirror addr msb = 0\n NOTE: This should only be used when System headers are Petra Headers.\n For Arad / Jericho headers, should use AradSnpMirStampEn and AradSnpMirStampValues", 8233 /* ITE_SNP_MIRR_SYS_HEADER_INFO */ "The ITPP stamps for snoop or mirror packet the following fields according to the enable bits, per snoop/mirror command from the IQM's outlif field.\n The address of this table access is is_snoop(~mirror), snoop/mirror-cmd.\n Meaning that the first rows of the table are for mirror and the last rows are for snoop", 8234 /* ITPPD_MAX_LATENCY */ "The ITPP measures latency from the packet OAM-TS extension. In this memory the 8 maximal latency's are kept, with the pointer associated with them", 8235 /* ITPPD_PACKET_LATENCY_MEASUREMENT */ "ITPP measure latency between the packet TimeStamp stamped by the IPP, to the time of day reported to it. Latency is reported to the CRPS and the maximal value is kept., address is Flow Profile", 8236 /* ITPPD_SNIFF_SYS_HEADER_INFO */ "The ITPP stamps for snoop or mirror packet the following fields according to the enable bits, per snoop/mirror command from the IQM's outlif field. The address of this table access is IQM_Action_Type(2), Sniff_Profile(5) .", 8237 /* ITPPD_VOQ_QUARTET */ "", 8238 /* ITPP_MAX_LATENCY */ "The ITPP measures latency from the packet OAM-TS extension. In this memory the 8 maximal latency's are kept, with the pointer associated with them", 8239 /* ITPP_PACKET_LATENCY_MEASUREMENT */ "ITPP measure latency between the packet TimeStamp stamped by the IPP, to the time of day reported to it. Latency is reported to the CRPS and the maximal value is kept., address is Flow Profile", 8240 /* ITPP_SNIFF_SYS_HEADER_INFO */ "The ITPP stamps for snoop or mirror packet the following fields according to the enable bits, per snoop/mirror command from the IQM's outlif field. The address of this table access is IQM_Action_Type(2), Sniff_Profile(5) .", 8241 /* ITPP_VOQ_QUARTET */ "Mapping table for VOQ (QNUM) to receive the quartet profile", 8242 /* KAPS_BBS_BUCKET_MEMORY */ "Bucket memory", 8243 /* KAPS_BUCKET_MAP_MEMORY */ "Bucket mapping memory", 8244 /* KAPS_BUCKET_MEMORY */ "Bucket memory", 8245 /* KAPS_RPB_ADS */ "Context Memory for packet alignment control", 8246 /* KAPS_RPB_TCAM_CPU_CMD */ "TCAM command: The command can be write/read/compare/search. In case of write and compare the Din is needed.\n A command can be performed to addresses 0-4095, representing the 4K TCAM memory. There is one interface per RPB", 8247 /* KAPS_RPB_TCAM_CPU_COMMAND */ "RPB TCAM command: The command can be write/read/compare/search. In case of write and compare the Din is needed.\n A command can be performed to addresses 0-4095, representing the 4K TCAM memory (1 I/F per RPB)", 8248 /* KAPS_RPB_TCAM_CPU_REP */ "TCAM reply. The reply is based on the command entered before.", 8249 /* KAPS_RPB_TCAM_CPU_REPLY */ "TCAM reply. The reply is based on the command entered before.", 8250 /* KAPS_RPB_TCAM_HIT_INDICATION */ "hit indication memory", 8251 /* KAPS_TCAM_ECC_MEMORY */ "Tcam ECC Memory", 8252 /* KAPS_TCAM_HIT_INDICATION */ "tcam hit indication memory", 8253 /* KAPS_TCM */ "The R5s TCM. The host may DMA read and write this memory.", 8254 /* KEYGEN_HDR_VALID_CHECK_PROFILE_1 */ "Keygen Header Valid Check Profile Table 1.", 8255 /* KEYGEN_HDR_VALID_CHECK_PROFILE_2 */ "Keygen Header Valid Check Profile Table 1.", 8256 /* KNOWN_MCAST_BLOCK_MASK */ "Known Multicast Block Mask, FeatureSpecific-Ethernet.", 8257 /* L2MC */ "L2 Multicast table", 8258 /* L2X */ "Combined HW managed L2 entry table. Includes L2_ENTRY, L2_HITDA, and L2_HITSA", 8259 /* L2_BULK */ "L2_BULK_MATCH and L2_BULK_REPLACE fields. Addr 0: L2_BULK_MATCH_DATA\n Addr 1: L2_BULK_MATCH_MASK\n Addr 2: L2_BULK_REPLACE_DATA\n Addr 3: L2_BULK_REPLACE_MASK", 8260 /* L2_BULK_MATCH_DATA */ "L2 Bulk match enable.", 8261 /* L2_BULK_MATCH_MASK */ "L2 Bulk match enable.", 8262 /* L2_BULK_MATCH_VLANS_PORT_A */ "VLAN Membership bitmap for PORT_A for L2_BULK.", 8263 /* L2_BULK_MATCH_VLANS_PORT_B */ "VLAN Membership bitmap for PORT_B for L2_BULK.", 8264 /* L2_BULK_REPLACE_DATA */ "L2 Bulk match enable.", 8265 /* L2_BULK_REPLACE_MASK */ "L2 Bulk match enable.", 8266 /* L2_DESTINATION_STRENGTH_PROFILE */ "Packet Process Header Valid Check Profile Table 2.", 8267 /* L2_ENDPOINT_ID */ "L2 Endpoint ID table. REFER TO: L2_ENDPOINT_ID_HASH_CONTROL register.", 8268 /* L2_ENTRY_1 */ "L2_ENTRY_1, Single base entry views. FeatureSpecific-Ethernet.", 8269 /* L2_ENTRY_2 */ "L2_ENTRY_2, Double base entry views. FeatureSpecific-Ethernet.", 8270 /* L2_ENTRY_1_HIT_ONLY */ "L2_ENTRY_1_HIT_ONLY, Single base entry views. FeatureSpecific-Ethernet.", 8271 /* L2_ENTRY_2_HIT_ONLY */ "L2_ENTRY_2_HIT_ONLY, Double base entry views. FeatureSpecific-Ethernet.", 8272 /* L2_ENTRY_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8273 /* L2_ENTRY_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8274 /* L2_ENTRY_ECC */ "ECC Table.", 8275 /* L2_ENTRY_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 8276 /* L2_ENTRY_ISS_LP */ "L2_ENTRY LP Control Table.", 8277 /* L2_ENTRY_KEY_ATTRIBUTES */ "Key Attributes Table.", 8278 /* L2_ENTRY_KEY_BUFFER_0 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8279 /* L2_ENTRY_KEY_BUFFER_1 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8280 /* L2_ENTRY_KEY_BUFFER_0_PIPE0 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8281 /* L2_ENTRY_KEY_BUFFER_0_PIPE1 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8282 /* L2_ENTRY_KEY_BUFFER_0_PIPE2 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8283 /* L2_ENTRY_KEY_BUFFER_0_PIPE3 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8284 /* L2_ENTRY_KEY_BUFFER_0_PIPE4 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8285 /* L2_ENTRY_KEY_BUFFER_0_PIPE5 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8286 /* L2_ENTRY_KEY_BUFFER_0_PIPE6 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8287 /* L2_ENTRY_KEY_BUFFER_0_PIPE7 */ "Records first lookup key of L2_ENTRY lookup for visibility packets.", 8288 /* L2_ENTRY_KEY_BUFFER_1_PIPE0 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8289 /* L2_ENTRY_KEY_BUFFER_1_PIPE1 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8290 /* L2_ENTRY_KEY_BUFFER_1_PIPE2 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8291 /* L2_ENTRY_KEY_BUFFER_1_PIPE3 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8292 /* L2_ENTRY_KEY_BUFFER_1_PIPE4 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8293 /* L2_ENTRY_KEY_BUFFER_1_PIPE5 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8294 /* L2_ENTRY_KEY_BUFFER_1_PIPE6 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8295 /* L2_ENTRY_KEY_BUFFER_1_PIPE7 */ "Records second lookup key of L2_ENTRY lookup for visibility packets.", 8296 /* L2_ENTRY_LP */ "L2_ENTRY LP Control Table.", 8297 /* L2_ENTRY_ONLY */ "HW managed L2_ENTRY table only. Does not include L2_HITSA or L2_HITDA", 8298 /* L2_ENTRY_ONLY_ECC */ "ECC Table for L2_ENTRY_ONLY.", 8299 /* L2_ENTRY_ONLY_SINGLE */ "HW managed L2_ENTRY table only. Does not include L2_HITSA or L2_HITDA..", 8300 /* L2_ENTRY_ONLY_TILE */ "HW Managed L2_ENTRY Table Only. Does not include L2_HITSA or L2_HITDA.", 8301 /* L2_ENTRY_OVERFLOW */ "Small overflow for L2_ENTRY table. Treated as extra entries for all buckets.", 8302 /* L2_ENTRY_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8303 /* L2_ENTRY_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8304 /* L2_ENTRY_SCRATCH */ "Single L2_ENTRY that is usable by software - never written by h/w learn, etc. Fully usable L2 entry that is searched for every packet.", 8305 /* L2_ENTRY_SINGLE */ "HW managed L2_ENTRY table only. Does not include L2_HITSA or L2_HITDA..", 8306 /* L2_ENTRY_TILE */ "Combined HW Managed L2 Entry Table. Includes L2_ENTRY_TILE, L2_HITDA, and L2_HITSA.", 8307 /* L2_HITDA_ONLY */ "HW managed L2_HITDA_ONLY table. Just the DA hit bits.", 8308 /* L2_HITDA_ONLY_X */ "HW managed L2_HITDA_ONLY table. Just the DA hit bits.", 8309 /* L2_HITDA_ONLY_Y */ "HW managed L2_HITDA_ONLY table. Just the DA hit bits.", 8310 /* L2_HITSA_ONLY */ "HW managed L2_HITSA_ONLY table. Just the SA hit bits.", 8311 /* L2_HITSA_ONLY_X */ "HW managed L2_HITSA_ONLY table. Just the SA hit bits.", 8312 /* L2_HITSA_ONLY_Y */ "HW managed L2_HITSA_ONLY table. Just the SA hit bits.", 8313 /* L2_LEARN_CACHE */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8314 /* L2_LEARN_CACHE_PIPE0 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8315 /* L2_LEARN_CACHE_PIPE1 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8316 /* L2_LEARN_CACHE_PIPE2 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8317 /* L2_LEARN_CACHE_PIPE3 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8318 /* L2_LEARN_CACHE_PIPE4 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8319 /* L2_LEARN_CACHE_PIPE5 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8320 /* L2_LEARN_CACHE_PIPE6 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8321 /* L2_LEARN_CACHE_PIPE7 */ "L2 learn cache for each pipe. Note that HW only populates the following fields: VALID, MAC_ADDR, VLAN_ID, DEST_TYPE, and DESTINATION. All the other fields will be populated with zeroes.", 8322 /* L2_LEARN_INSERT_FAILURE */ "If L2_ENTRY hardware learning encounters a bucket full condition, the L2_ENTRY that was to be learned is recorded to this register. Software writes all zeros to this register to reset, allowing hardware to record again. An L2_LEARN_INSERT_FAILURE interrupt is generated when this register is non-zero.", 8323 /* L2_MGMT_SER_FIFO */ "L2_MGMT SER FIFO", 8324 /* L2_MOD_FIFO */ "FIFO for operations that MODify the L2_ENTRY table.", 8325 /* L2_USER_ENTRY */ "Combined L2_ENTRY TCAM/Data RAM for guaranteed L2 entries and BPDUs.", 8326 /* L2_USER_ENTRY_DATA_ONLY */ "Data SRAM for L2_USER_ENTRY TCAM.", 8327 /* L2_USER_ENTRY_ONLY */ "TCAM for guaranteed L2 entries and BPDUs.", 8328 /* L3_DEFIP */ "L3 Default IP Route (LPM) TCAM view with data and hit bits", 8329 /* L3_DEFIP_128 */ "L3 Default IP Route (LPM) TCAM view with data and hit bits. FeatureSpecific-Ethernet", 8330 /* L3_DEFIP_128_DATA_ONLY */ "L3 Default IP Route (LPM) Data SRAM for the L3_DEFIP_128 TCAM. FeatureSpecific-Ethernet", 8331 /* L3_DEFIP_128_HIT_ONLY */ "L3_DEFIP Hit bit table, FeatureSpecific-Ethernet", 8332 /* L3_DEFIP_128_HIT_ONLY_X */ "L3_DEFIP Hit bit table, FeatureSpecific-Ethernet.", 8333 /* L3_DEFIP_128_HIT_ONLY_Y */ "L3_DEFIP Hit bit table, FeatureSpecific-Ethernet.", 8334 /* L3_DEFIP_128_ONLY */ "L3 Default IP Route (LPM) TCAM only view. FeatureSpecific-Ethernet", 8335 /* L3_DEFIP_128_X */ "L3 Default IP Route (LPM) TCAM view with data and hit bits. FeatureSpecific-Ethernet.", 8336 /* L3_DEFIP_128_Y */ "L3 Default IP Route (LPM) TCAM view with data and hit bits. FeatureSpecific-Ethernet.", 8337 /* L3_DEFIP_ALPM_ECC */ "ECC table for L3_DEFIP_ALPM.", 8338 /* L3_DEFIP_ALPM_ECC_ADDR_XLATE */ "Translates the SBUS BANK and ENTRY to UFT for avoiding holes in adressing on SBUS side", 8339 /* L3_DEFIP_ALPM_HIT_ONLY */ "L3_DEFIP Hit bit table..", 8340 /* L3_DEFIP_ALPM_HIT_ONLY_X */ "L3_DEFIP Hit bit table..", 8341 /* L3_DEFIP_ALPM_HIT_ONLY_Y */ "L3_DEFIP Hit bit table..", 8342 /* L3_DEFIP_ALPM_IPV4 */ "(ALPM) SRAM Data for IPv4 view, no flex counters.", 8343 /* L3_DEFIP_ALPM_IPV4_1 */ "(ALPM) SRAM Data for IPv4 view with flex counters.", 8344 /* L3_DEFIP_ALPM_IPV4_1_ADDR_XLATE */ "Translates the SBUS BANK and ENTRY to UFT for avoiding holes in adressing on SBUS side", 8345 /* L3_DEFIP_ALPM_IPV4_ADDR_XLATE */ "Translates the SBUS BANK and ENTRY to UFT for avoiding holes in adressing on SBUS side", 8346 /* L3_DEFIP_ALPM_IPV6_64 */ "(ALPM) SRAM Data for IPv6(64b) view, no flex counters.", 8347 /* L3_DEFIP_ALPM_IPV6_128 */ "(ALPM) SRAM Data for IPv6(128b) view", 8348 /* L3_DEFIP_ALPM_IPV6_128_ADDR_XLATE */ "Translates the SBUS BANK and ENTRY to UFT for avoiding holes in adressing on SBUS side", 8349 /* L3_DEFIP_ALPM_IPV6_64_1 */ "(ALPM) SRAM Data for IPv6(64b) view, with flex counters.", 8350 /* L3_DEFIP_ALPM_IPV6_64_1_ADDR_XLATE */ "Translates the SBUS BANK and ENTRY to UFT for avoiding holes in adressing on SBUS side", 8351 /* L3_DEFIP_ALPM_IPV6_64_ADDR_XLATE */ "Translates the SBUS BANK and ENTRY to UFT for avoiding holes in adressing on SBUS side", 8352 /* L3_DEFIP_ALPM_LEVEL2 */ "L3_DEFIP_ALPM_LEVEL2 table.", 8353 /* L3_DEFIP_ALPM_LEVEL3 */ "L3_DEFIP_ALPM_LEVEL3 table.", 8354 /* L3_DEFIP_ALPM_LEVEL2_ECC */ "L3_DEFIP_ALPM_LEVEL2_ECC table.", 8355 /* L3_DEFIP_ALPM_LEVEL2_HIT_ONLY */ "L3_DEFIP Hit Bit Table.", 8356 /* L3_DEFIP_ALPM_LEVEL2_SINGLE */ "L3_DEFIP_ALPM_LEVEL2_SINGLE table.", 8357 /* L3_DEFIP_ALPM_LEVEL3_ECC */ "L3_DEFIP_ALPM_LEVEL3_ECC table.", 8358 /* L3_DEFIP_ALPM_LEVEL3_HIT_ONLY */ "L3_DEFIP Hit Bit Table.", 8359 /* L3_DEFIP_ALPM_LEVEL3_SINGLE */ "L3_DEFIP_ALPM_LEVEL3_SINGLE table.", 8360 /* L3_DEFIP_ALPM_RAW */ "L3_DEFIP_ALPM raw view to ISS memory", 8361 /* L3_DEFIP_ALPM_RAW_ADDR_XLATE */ "Translates the SBUS BANK and ENTRY to UFT for avoiding holes in adressing on SBUS side", 8362 /* L3_DEFIP_AUX_HITBIT_UPDATE */ "L3 DEFIP ALPM hitbit replacement configuration register", 8363 /* L3_DEFIP_AUX_SCRATCH */ "L3 Default IP Route (LPM) Data SRAM for the L3_DEFIP TCAM.", 8364 /* L3_DEFIP_AUX_TABLE */ "L3 Default IP Route (LPM) Data SRAM for the L3_DEFIP TCAM.", 8365 /* L3_DEFIP_DATA_LEVEL1 */ "L3_DEFIP_DATA_LEVEL1 table.", 8366 /* L3_DEFIP_DATA_ONLY */ "L3 Default IP Route (LPM) Data SRAM for the L3_DEFIP TCAM", 8367 /* L3_DEFIP_HIT_ONLY */ "L3_DEFIP Hit bit table", 8368 /* L3_DEFIP_HIT_ONLY_X */ "L3_DEFIP Hit bit table, FeatureSpecific-Ethernet.", 8369 /* L3_DEFIP_HIT_ONLY_Y */ "L3_DEFIP Hit bit table, FeatureSpecific-Ethernet.", 8370 /* L3_DEFIP_LEVEL1 */ "L3_DEFIP_LEVEL1 table.", 8371 /* L3_DEFIP_LEVEL1_HIT_ONLY */ "L3_DEFIP Hit Bit Table.", 8372 /* L3_DEFIP_ONLY */ "L3 Default IP Route (LPM) TCAM only view", 8373 /* L3_DEFIP_PAIR_128 */ "L3 Default IP Route (LPM) TCAM view with data and hit bits. FeatureSpecific-Ethernet.", 8374 /* L3_DEFIP_PAIR_128_DATA_ONLY */ "L3 Default IP Route (LPM) Data SRAM for the L3_DEFIP_128 TCAM. FeatureSpecific-Ethernet.", 8375 /* L3_DEFIP_PAIR_128_HIT_ONLY */ "L3_DEFIP Hit bit table, FeatureSpecific-Ethernet.", 8376 /* L3_DEFIP_PAIR_128_HIT_ONLY_X */ "L3_DEFIP Hit bit table..", 8377 /* L3_DEFIP_PAIR_128_HIT_ONLY_Y */ "L3_DEFIP Hit bit table..", 8378 /* L3_DEFIP_PAIR_128_ONLY */ "L3 Default IP Route (LPM) TCAM only view. FeatureSpecific-Ethernet.", 8379 /* L3_DEFIP_PAIR_LEVEL1 */ "L3_DEFIP_PAIR_LEVEL1 table.", 8380 /* L3_DEFIP_TCAM_LEVEL1 */ "L3_DEFIP_TCAM_LEVEL1 table.", 8381 /* L3_DEFIP_X */ "L3 Default IP Route (LPM) TCAM view with data and hit bits. FeatureSpecific-Ethernet.", 8382 /* L3_DEFIP_Y */ "L3 Default IP Route (LPM) TCAM view with data and hit bits. FeatureSpecific-Ethernet.", 8383 /* L3_ECMP */ "L3 Equal Cost Multipath table", 8384 /* L3_ECMP_COUNT */ "Contains the number of members in each ECMP group. Used with ECMP_POINTER to calulate index to L3_ECMP table", 8385 /* L3_ECMP_RRLB_CNT */ "Initial L3 Equal Cost Multipath Group Round Robin Count.", 8386 /* L3_ECMP_RRLB_CNT_PIPE0 */ "Initial L3 Equal Cost Multipath Group Round Robin Count.", 8387 /* L3_ECMP_RRLB_CNT_PIPE1 */ "Initial L3 Equal Cost Multipath Group Round Robin Count.", 8388 /* L3_ECMP_RRLB_CNT_PIPE2 */ "Initial L3 Equal Cost Multipath Group Round Robin Count.", 8389 /* L3_ECMP_RRLB_CNT_PIPE3 */ "Initial L3 Equal Cost Multipath Group Round Robin Count.", 8390 /* L3_ENTRY_1 */ "L3_ENTRY_1, Single base entry views. FeatureSpecific-Ethernet.", 8391 /* L3_ENTRY_2 */ "L3_ENTRY_2, Double base entry views. FeatureSpecific-Ethernet.", 8392 /* L3_ENTRY_4 */ "L3_ENTRY_4, Quad base entry views. FeatureSpecific-Ethernet.", 8393 /* L3_ENTRY_1_HIT_ONLY */ "L3_ENTRY_1_HIT_ONLY, Single base entry views. FeatureSpecific-Ethernet.", 8394 /* L3_ENTRY_2_HIT_ONLY */ "L3_ENTRY_2_HIT_ONLY, Double base entry views. FeatureSpecific-Ethernet.", 8395 /* L3_ENTRY_4_HIT_ONLY */ "L3_ENTRY_4_HIT_ONLY, Quad base entry views. FeatureSpecific-Ethernet.", 8396 /* L3_ENTRY_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8397 /* L3_ENTRY_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8398 /* L3_ENTRY_DOUBLE */ "L3 routing table with fb_regs arch view. No hit bits..", 8399 /* L3_ENTRY_ECC */ "ECC Table.", 8400 /* L3_ENTRY_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 8401 /* L3_ENTRY_HIT_ONLY */ "L3 Hit bit table", 8402 /* L3_ENTRY_HIT_ONLY_X */ "L3 Hit bit table, FeatureSpecific-Ethernet.", 8403 /* L3_ENTRY_HIT_ONLY_Y */ "L3 Hit bit table, FeatureSpecific-Ethernet.", 8404 /* L3_ENTRY_IPV4_MULTICAST */ "L3 routing table IPV4 MULTICAST view", 8405 /* L3_ENTRY_IPV4_MULTICAST_SCRATCH */ "L3 routing table IPV4 MULTICAST_SCRATCH view, FeatureSpecific-Ethernet", 8406 /* L3_ENTRY_IPV4_MULTICAST_X */ "L3 routing table IPV4 MULTICAST view, FeatureSpecific-Ethernet.", 8407 /* L3_ENTRY_IPV4_MULTICAST_Y */ "L3 routing table IPV4 MULTICAST view, FeatureSpecific-Ethernet.", 8408 /* L3_ENTRY_IPV4_UNICAST */ "L3 routing table IPV4 UNICAST view", 8409 /* L3_ENTRY_IPV4_UNICAST_SCRATCH */ "L3 routing table IPV4 UNICAST view, FeatureSpecific-Ethernet", 8410 /* L3_ENTRY_IPV4_UNICAST_X */ "L3 routing table IPV4 UNICAST view, FeatureSpecific-Ethernet.", 8411 /* L3_ENTRY_IPV4_UNICAST_Y */ "L3 routing table IPV4 UNICAST view, FeatureSpecific-Ethernet.", 8412 /* L3_ENTRY_IPV6_MULTICAST */ "L3 routing table IPV6 MULTICAST view", 8413 /* L3_ENTRY_IPV6_MULTICAST_SCRATCH */ "L3 routing table IPV6 MULTICAST_SCRATCH view, FeatureSpecific-Ethernet", 8414 /* L3_ENTRY_IPV6_MULTICAST_X */ "L3 routing table IPV6 MULTICAST view, FeatureSpecific-Ethernet.", 8415 /* L3_ENTRY_IPV6_MULTICAST_Y */ "L3 routing table IPV6 MULTICAST view, FeatureSpecific-Ethernet.", 8416 /* L3_ENTRY_IPV6_UNICAST */ "L3 routing table IPV6 UNICAST view", 8417 /* L3_ENTRY_IPV6_UNICAST_SCRATCH */ "L3 routing table IPV6 UNICAST view, FeatureSpecific-Ethernet", 8418 /* L3_ENTRY_IPV6_UNICAST_X */ "L3 routing table IPV6 UNICAST view, FeatureSpecific-Ethernet.", 8419 /* L3_ENTRY_IPV6_UNICAST_Y */ "L3 routing table IPV6 UNICAST view, FeatureSpecific-Ethernet.", 8420 /* L3_ENTRY_ISS_LP */ "L3_ENTRY LP Control Table.", 8421 /* L3_ENTRY_KEY_ATTRIBUTES */ "Key Attributes Table.", 8422 /* L3_ENTRY_KEY_BUFFER_0 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8423 /* L3_ENTRY_KEY_BUFFER_1 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8424 /* L3_ENTRY_KEY_BUFFER_0_PIPE0 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8425 /* L3_ENTRY_KEY_BUFFER_0_PIPE1 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8426 /* L3_ENTRY_KEY_BUFFER_0_PIPE2 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8427 /* L3_ENTRY_KEY_BUFFER_0_PIPE3 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8428 /* L3_ENTRY_KEY_BUFFER_0_PIPE4 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8429 /* L3_ENTRY_KEY_BUFFER_0_PIPE5 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8430 /* L3_ENTRY_KEY_BUFFER_0_PIPE6 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8431 /* L3_ENTRY_KEY_BUFFER_0_PIPE7 */ "Records first lookup key of L3_ENTRY lookup for visibility packets.", 8432 /* L3_ENTRY_KEY_BUFFER_1_PIPE0 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8433 /* L3_ENTRY_KEY_BUFFER_1_PIPE1 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8434 /* L3_ENTRY_KEY_BUFFER_1_PIPE2 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8435 /* L3_ENTRY_KEY_BUFFER_1_PIPE3 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8436 /* L3_ENTRY_KEY_BUFFER_1_PIPE4 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8437 /* L3_ENTRY_KEY_BUFFER_1_PIPE5 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8438 /* L3_ENTRY_KEY_BUFFER_1_PIPE6 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8439 /* L3_ENTRY_KEY_BUFFER_1_PIPE7 */ "Records second lookup key of L3_ENTRY lookup for visibility packets.", 8440 /* L3_ENTRY_LP */ "L3_ENTRY LP Control Table.", 8441 /* L3_ENTRY_ONLY */ "L3 routing table with fb_regs arch view. No hit bits", 8442 /* L3_ENTRY_ONLY_DOUBLE */ "L3 routing table with fb_regs arch view. No hit bits..", 8443 /* L3_ENTRY_ONLY_ECC */ "ECC Table for L3_ENTRY_ONLY.", 8444 /* L3_ENTRY_ONLY_QUAD */ "L3 routing table with fb_regs arch view. No hit bits..", 8445 /* L3_ENTRY_ONLY_SINGLE */ "L3 routing table with fb_regs arch view. No hit bits..", 8446 /* L3_ENTRY_QUAD */ "L3 routing table with fb_regs arch view. No hit bits..", 8447 /* L3_ENTRY_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8448 /* L3_ENTRY_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8449 /* L3_ENTRY_SINGLE */ "L3 routing table with fb_regs arch view. No hit bits..", 8450 /* L3_ENTRY_VALID_ONLY */ "L3 routing table Valid Bits only view. Organized into buckets", 8451 /* L3_IIF */ "Layer 3 Input Interface Properties", 8452 /* L3_IIF_ATTRS_1 */ "Layer 3 Input Interface Properties.", 8453 /* L3_IIF_CTRL_PROFILE_1 */ "L3_IIF Control Profile Table 1.", 8454 /* L3_IIF_PROFILE */ "Layer 3 Input Interface Properties. Indexed by L3_IIF.L3_IIF_PROFILE_INDEX.", 8455 /* L3_IPMC */ "L3 IPMC Table", 8456 /* L3_IPMC_1 */ "L3 IPMC Table (for source properties)", 8457 /* L3_IPMC_2 */ "L3 IPMC Table.", 8458 /* L3_IPMC_REMAP */ "L3 IPMC Remap Table", 8459 /* L3_MTU_VALUES */ "index by ING_L3_NEXT_HOP.L3_OIF or ipmc_index or VID", 8460 /* L3_TUNNEL */ "L3 Tunnel Table TCAM", 8461 /* L3_TUNNEL_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8462 /* L3_TUNNEL_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8463 /* L3_TUNNEL_DATA_ONLY */ "L3 Tunnel Table TCAM..", 8464 /* L3_TUNNEL_DEFAULT_VLAN_PROFILE */ "Protection Switching Drop Enable.", 8465 /* L3_TUNNEL_DOUBLE */ "L3_TUNNEL table.", 8466 /* L3_TUNNEL_ECC */ "ECC Table.", 8467 /* L3_TUNNEL_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 8468 /* L3_TUNNEL_KEY_ATTRIBUTES */ "Key Attributes Table.", 8469 /* L3_TUNNEL_KEY_BUFFER */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8470 /* L3_TUNNEL_KEY_BUFFER_PIPE0 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8471 /* L3_TUNNEL_KEY_BUFFER_PIPE1 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8472 /* L3_TUNNEL_KEY_BUFFER_PIPE2 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8473 /* L3_TUNNEL_KEY_BUFFER_PIPE3 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8474 /* L3_TUNNEL_KEY_BUFFER_PIPE4 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8475 /* L3_TUNNEL_KEY_BUFFER_PIPE5 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8476 /* L3_TUNNEL_KEY_BUFFER_PIPE6 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8477 /* L3_TUNNEL_KEY_BUFFER_PIPE7 */ "Records lookup key of L3_TUNNEL lookup for visibility packets.", 8478 /* L3_TUNNEL_ONLY */ "L3 Tunnel Table TCAM..", 8479 /* L3_TUNNEL_QUAD */ "L3_TUNNEL table.", 8480 /* L3_TUNNEL_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8481 /* L3_TUNNEL_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 8482 /* L3_TUNNEL_SINGLE */ "L3_TUNNEL table.", 8483 /* LAG_DLB_CONTROL */ "DLB Enables for LAG.", 8484 /* LCM_AUTO_DOC_NAME_15 */ "INTERNAL", 8485 /* LCM_AUTO_DOC_NAME_16 */ "INTERNAL", 8486 /* LCM_AUTO_DOC_NAME_17 */ "INTERNAL", 8487 /* LCM_AUTO_DOC_NAME_18 */ "INTERNAL", 8488 /* LCM_AUTO_DOC_NAME_19 */ "INTERNAL", 8489 /* LINK_LOCAL_MAC_ADDRESS */ "Multicast MAC address range reserved for 802.1.", 8490 /* LINK_STATUS */ "Link Status Indication Register.", 8491 /* LLS_L0_CHILD_STATE1 */ "L0 Child Status 1 Database", 8492 /* LLS_L0_CHILD_STATE1_A */ "L0 Child Status 1 Database", 8493 /* LLS_L0_CHILD_WEIGHT_CFG */ "L0 Child Weight Config Database", 8494 /* LLS_L0_CHILD_WEIGHT_CFG_CNT */ "L0 Child Weight Config and count Database", 8495 /* LLS_L0_CHILD_WEIGHT_WORKING */ "L0 Child Working Weight and Count Database", 8496 /* LLS_L0_CONFIG */ "L0 Configuration Database", 8497 /* LLS_L0_CONFIG_A */ "L0 Configuration Database", 8498 /* LLS_L0_EF_NEXT */ "L0 Child EF Linked List Next Database", 8499 /* LLS_L0_ERROR */ "L0 Error database containing difference between expected scheduling amount and actual scheduling amount", 8500 /* LLS_L0_ERROR_MIN */ "L0 Min Error database containing difference between expected scheduling amount and actual scheduling amount", 8501 /* LLS_L0_HEADS_TAILS */ "L0 Heads and Tails Database", 8502 /* LLS_L0_HEADS_TAILS_1 */ "L0 Heads and Tails Database", 8503 /* LLS_L0_HEADS_TAILS_2 */ "L0 Heads and Tails Database", 8504 /* LLS_L0_MIN_BUCKET_C */ "L0 Min Bucket Database for L0 child entities", 8505 /* LLS_L0_MIN_CONFIG_C */ "L0 Min Configuration Database for L0 child entities", 8506 /* LLS_L0_MIN_NEXT */ "L0 Child Min Linked List Next Database", 8507 /* LLS_L0_PARENT */ "L0 Parent Database", 8508 /* LLS_L0_PARENT_STATE */ "L0 Parent State Database", 8509 /* LLS_L0_PARENT_STATE_A */ "L0 Parent State Database", 8510 /* LLS_L0_SHAPER_BUCKET_C */ "L0 Shaper Bucket Database for L0 child entities", 8511 /* LLS_L0_SHAPER_CONFIG_C */ "L0 Shaper Configuration Database for L0 child entities", 8512 /* LLS_L0_WERR_MAX_SC */ "L0 Max Surplus Count Database", 8513 /* LLS_L0_WERR_NEXT */ "L0 Child WERR Linked List Next Database", 8514 /* LLS_L0_XOFF */ "Port XOFF Database", 8515 /* LLS_L1_ACT_MIN */ "L1 Activation Database database for reactivating shaped nodes", 8516 /* LLS_L1_ACT_SHAPER */ "L1 Activation Database database for reactivating shaped nodes", 8517 /* LLS_L1_ACT_XON */ "L1 Activation Database database for reactivating shaped nodes", 8518 /* LLS_L1_CHILD_STATE1 */ "L1 Child Status 1 Database 4 entries of 7 bits per line", 8519 /* LLS_L1_CHILD_STATE1_A */ "L1 Child Status 1 Database 4 entries of 7 bits per line", 8520 /* LLS_L1_CHILD_WEIGHT_CFG */ "L1 Child Weight Config Database", 8521 /* LLS_L1_CHILD_WEIGHT_CFG_CNT */ "L1 Child Weight Config and Count Database", 8522 /* LLS_L1_CHILD_WEIGHT_WORKING */ "L1 Child Working Weight and Count Database", 8523 /* LLS_L1_CONFIG */ "L1 Configuration Database", 8524 /* LLS_L1_CONFIG_A */ "L1 Configuration Database", 8525 /* LLS_L1_EF_NEXT */ "L1 Child EF Linked List Next Database", 8526 /* LLS_L1_ERROR */ "L1 Error database containing difference between expected scheduling amount and actual scheduling amount", 8527 /* LLS_L1_ERROR_MIN */ "L1 Min Error database containing difference between expected scheduling amount and actual scheduling amount", 8528 /* LLS_L1_HEADS_TAILS */ "L1 Heads Tails Database for non ef list", 8529 /* LLS_L1_HEADS_TAILS_1 */ "L1 Heads Tails Database", 8530 /* LLS_L1_HEADS_TAILS_2 */ "L1 Heads Tails Database", 8531 /* LLS_L1_MC_XOFF */ "Port XOFF Database", 8532 /* LLS_L1_MIN_BUCKET_C */ "L1 Min Bucket Database for L1 child entities", 8533 /* LLS_L1_MIN_CONFIG_C */ "L0 Min Configuration Database for L1 child entities", 8534 /* LLS_L1_MIN_NEXT */ "L1 Child Min Linked List Next Database", 8535 /* LLS_L1_PARENT */ "L1 Parent Database", 8536 /* LLS_L1_PARENT_STATE */ "L1 Parent State Database", 8537 /* LLS_L1_PARENT_STATE_A */ "L1 Parent State Database", 8538 /* LLS_L1_SHAPER_BUCKET_C */ "L1 Shaper Bucket Database for L1 child entities", 8539 /* LLS_L1_SHAPER_CONFIG_C */ "L1 Shaper Configuration Database for L1 child entities", 8540 /* LLS_L1_WERR_MAX_SC */ "L1 Max Surplus Count Database", 8541 /* LLS_L1_WERR_NEXT */ "L1 Child WERR Linked List Next Database", 8542 /* LLS_L1_XOFF */ "Port XOFF Database", 8543 /* LLS_L2_ACT_ENQ */ "L2 Activation Database database for reactivating enqueue unicast nodes", 8544 /* LLS_L2_ACT_MIN */ "L2 min activation table", 8545 /* LLS_L2_ACT_SHAPER */ "L2 shaper activation table", 8546 /* LLS_L2_ACT_XON */ "L2 xon activation table", 8547 /* LLS_L2_CHILD_STATE1 */ "L2 Child state database", 8548 /* LLS_L2_CHILD_STATE1_A */ "L2 Child state database", 8549 /* LLS_L2_CHILD_WEIGHT_CFG */ "L2 Child Weight Config and count Database", 8550 /* LLS_L2_CHILD_WEIGHT_CFG_CNT */ "L2 Child Weight Config and count Database", 8551 /* LLS_L2_CHILD_WEIGHT_WORKING */ "L2 Child Working Weight and count Database", 8552 /* LLS_L2_EMPTY_STATE */ "L2 EMPTY_STATE Database", 8553 /* LLS_L2_ERROR */ "L2 Error database containing difference between expected scheduling amount and actual scheduling amount", 8554 /* LLS_L2_ERROR_MIN */ "L2 Min Error database containing difference between expected scheduling amount and actual scheduling amount", 8555 /* LLS_L2_MC_CHILD_WEIGHT_CFG_CNT */ "L2 MC Child Weight Config and count Database", 8556 /* LLS_L2_MC_XOFF */ "L2 XOFF Database", 8557 /* LLS_L2_MIN_BUCKET_C */ "L2 Min Bucket Database for L2 child entities", 8558 /* LLS_L2_MIN_BUCKET_LOWER_C */ "L2 Min Bucket Database for L2 child entities", 8559 /* LLS_L2_MIN_BUCKET_UPPER_C */ "L2 Min Bucket Database for L2 child entities", 8560 /* LLS_L2_MIN_CONFIG_C */ "L2 Min Max Configuration Database for L2 child entities", 8561 /* LLS_L2_MIN_CONFIG_LOWER_C */ "L2 Min Configuration Database for L2 child entities", 8562 /* LLS_L2_MIN_CONFIG_UPPER_C */ "L2 Min Configuration Database for L2 child entities", 8563 /* LLS_L2_MIN_NEXT */ "L2 Child MIN Linked List Next Database", 8564 /* LLS_L2_PARENT */ "L2 Parent Database", 8565 /* LLS_L2_SHAPER_BUCKET */ "L2 Shaper Bucket Database 0 for L2 child entities", 8566 /* LLS_L2_SHAPER_BUCKET_LOWER */ "L2 Shaper Bucket Database 0 for L2 child entities", 8567 /* LLS_L2_SHAPER_BUCKET_UPPER */ "L2 Shaper Bucket Database 0 for L2 child entities", 8568 /* LLS_L2_SHAPER_CONFIG_C */ "L2 Max Configuration Database for L2 child entities", 8569 /* LLS_L2_SHAPER_CONFIG_LOWER */ "L2 Shaper Configuration Database for L2 child entities", 8570 /* LLS_L2_SHAPER_CONFIG_UPPER */ "L2 Shaper Configuration Database for L2 child entities", 8571 /* LLS_L2_SHAPER_STATE_MAX */ "L2 Max shaper state database", 8572 /* LLS_L2_SHAPER_STATE_MIN */ "L2 Min shaper state database", 8573 /* LLS_L2_WERR_NEXT */ "L2 Child WERR Linked List Next Database 4 entries per word", 8574 /* LLS_L2_XOFF */ "L2 XOFF Database", 8575 /* LLS_PORT_CONFIG */ "Port Configuration Database", 8576 /* LLS_PORT_CONFIG_A */ "Port Configuration Database. Implemented using flops, No ECC or Parity protection", 8577 /* LLS_PORT_ERROR */ "Port Error database containing difference between expected scheduling amount and actual scheduling amount", 8578 /* LLS_PORT_HEADS */ "Port Heads Database", 8579 /* LLS_PORT_PARENT_STATE */ "Port Parent State Database", 8580 /* LLS_PORT_PARENT_STATE_A */ "Port Parent State Database. Implemented using flops, No ECC or Parity protection", 8581 /* LLS_PORT_SEQ_NUM */ "Port Sequence Number Database : Working memory", 8582 /* LLS_PORT_SHAPER_BUCKET_C */ "Port Shaper Bucket Database", 8583 /* LLS_PORT_SHAPER_CONFIG_C */ "Port Shaper Configuration Database", 8584 /* LLS_PORT_TAILS */ "Port Tails Database", 8585 /* LLS_PORT_TDM */ "PORT TDM table", 8586 /* LLS_PORT_WERR_MAX_SC */ "Port Max Surplus Count Database", 8587 /* LLS_PORT_XOFF */ "Port XOFF Database", 8588 /* LLS_S0_ERROR */ "S0 Error database containing difference between expected scheduling amount and actual scheduling amount", 8589 /* LLS_S0_SHAPER_BUCKET_C */ "Port Shaper Bucket Database", 8590 /* LLS_S0_SHAPER_CONFIG_C */ "S0 Shaper Configuration Database", 8591 /* LLS_S1_CHILD_STATE */ "S1 Child State : Working memory", 8592 /* LLS_S1_CHILD_WEIGHT_CFG_CNT */ "L0 Child Weight Config and count Database", 8593 /* LLS_S1_CONFIG */ "S1 Configuration Database for S1s 0 to 127. S1s 128 to 255 do not require this database as those S1s map directly to an L0 with the same node ID. May be updated during traffic but only S1s that do not have any traffic to allow the setup of a new S1", 8594 /* LLS_S1_ERROR */ "S1 Error database containing difference between expected scheduling amount and actual scheduling amount", 8595 /* LLS_S1_HEADS */ "S1 Heads Database for S1s 0 to 127. S1s 128 to 255 do not require this database as those S1s map directly to an L0 with the same node ID : Working memory that cannot be accessed during traffic", 8596 /* LLS_S1_HEADS_TAILS */ "S1 Heads Database : Working memory that cannot be accessed during traffic", 8597 /* LLS_S1_L0_LOOKUP */ "S1 Max Surplus Count Database : NOLONGER HOST ACCESSIBLE", 8598 /* LLS_S1_NEXT */ "S1 Next Database : Working memory : THIS DATABASE IS READ ONLY", 8599 /* LLS_S1_PARENT */ "S1 Parent Database : Config memory", 8600 /* LLS_S1_PARENT_STATE */ "S1 Parent State Database for S1s 0 to 127. S1s 128 to 255 do not require this database as those S1s map directly to an L0 with the same node ID : Working memory that cannot be accessed during traffic", 8601 /* LLS_S1_SHAPER_BUCKET_C */ "Port Shaper Bucket Database", 8602 /* LLS_S1_SHAPER_CONFIG_C */ "S0 Shaper Configuration Database : Only Locations 0 to 127 should be configured. Locations 128 to 255 should be set to 0 as S1 128 to 255 is L0 128 to 255 so L0 shaping should be used for these", 8603 /* LLS_S1_TAILS */ "S1 Tails Database for S1s 0 to 127. S1s 128 to 255 do not require this database as those S1s map directly to an L0 with the same node ID", 8604 /* LLS_S1_WERR_MAX_SC */ "S1 Max Surplus Count Database", 8605 /* LLS_S1_XOFF */ "S1 XOFF Database", 8606 /* LMEP */ "", 8607 /* LMEP_1 */ "LMEP extension", 8608 /* LMEP_DA */ "Destination MAC Address for the LMEP_TX Packets.", 8609 /* LM_COUNTER_CONTROL */ "Per opcode OAM LM packets counter control.", 8610 /* LOCAL_SW_DISABLE_DEFAULT_PBM */ "Local switching disable default port bitmap, FeatureSpecific-Ethernet.", 8611 /* LOCAL_SW_DISABLE_DEFAULT_PBM_2 */ "Local switching disable default port bitmap - logically the same table as LOCAL_SW_DISABLE_DEFAULT_PBM. The field is separated for physical design purpose.", 8612 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR */ "Local switching disable default port bitmap for ingress mirror or egress mirror packets, FeatureSpecific-Ethernet.", 8613 /* LPM_IP_CONTROL */ "LPM_IP Configuration.", 8614 /* LPORT_TAB */ "LPort Table", 8615 /* LPORT_TAB_PIPE0 */ "LPort Profile Table.", 8616 /* LPORT_TAB_PIPE1 */ "LPort Profile Table.", 8617 /* LPORT_TAB_PIPE2 */ "LPort Profile Table.", 8618 /* LPORT_TAB_PIPE3 */ "LPort Profile Table.", 8619 /* LPORT_TAB_PIPE4 */ "LPort Profile Table.", 8620 /* LPORT_TAB_PIPE5 */ "LPort Profile Table.", 8621 /* LPORT_TAB_PIPE6 */ "LPort Profile Table.", 8622 /* LPORT_TAB_PIPE7 */ "LPort Profile Table.", 8623 /* MACSEC_DA_RANGE */ "Range for MAC-DA for MACSEC management packets", 8624 /* MACSEC_DA_RANGE_2 */ "Controls classid selection into HG header.", 8625 /* MACT_AGE_PROFILE_ARR_CFG */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix\n\n This ARR is used for aging profile in MACT aging.", 8626 /* MACT_APP_DB_MAP */ "maps app_db(6). Arr_profile is encoded with leading one.", 8627 /* MACT_CPU_MRQ_POP_INTERFACE */ "CPU interface for ARM accses to MRQ FIFO. This is not a real memory, it is here to create this interface.", 8628 /* MACT_CPU_REQUEST */ "CPU request. Interface to DMA.", 8629 /* MACT_FID_POINTER_INFO */ "configures how to take the FID-pointer from the entry.\n The adress to this table is entry_format_index(2), app_db_index(2).", 8630 /* MACT_FID_PROFILE_INFO */ "The adress to this table is profile from VsiProfiles", 8631 /* MACT_LARGE_EM_AGING_CONFIGURATION_TABLE */ "Logically:\n 4 Aging-Configuration-Table accessed table is chosen according to Aging-Configuration-Pointer(2)\n Each Aging-Configuration-Table has 16 Entries Access according to Entry.AGE(3), Entry.RBD(1), Owned-Entry\n Physically:\n strength(2), rbd(1), age(3) each line holds data for all age_profiles.\n age_profile(5)", 8632 /* MACT_LARGE_EM_EMC_RXI_FIFO */ "INTERNAL", 8633 /* MACT_LARGE_EM_EVENT_FIFO */ "INTERNAL", 8634 /* MACT_LARGE_EM_LELA_RXI_FIFO */ "INTERNAL", 8635 /* MACT_LARGE_EM_LELB_RXI_FIFO */ "INTERNAL", 8636 /* MACT_LARGE_EM_MANAGEMENT_REQUEST_FIFO */ "INTERNAL", 8637 /* MACT_LARGE_EM_REPLY_FIFO */ "INTERNAL", 8638 /* MACT_MRQ_ARR_CFG */ "A configuration table for the ARR, where each line represents a specific input format.\n Each line includes the configurartion data for each field in the incoming data.\n A general look of each line:\n f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 8639 /* MACT_VSI_COUNTERS */ "VSI counters", 8640 /* MACT_VSI_PROFILES */ "VSI profiles", 8641 /* MAC_BLOCK */ "Source Trunk Bitmap Table", 8642 /* MAC_LIMIT_PORT_MAP_TABLE */ "TABLE for mapping a INGRESS PORT to a index into MAC_LIMIT_COUNT_TABLE. Indexed using ingress port number", 8643 /* MAC_LIMIT_TRUNK_MAP_TABLE */ "TABLE for mapping a TRUNK group to a index into MAC_LIMIT_COUNT_TABLE. Indexed using the Src/Dst TGID.", 8644 /* MAID_REDUCTION */ "", 8645 /* MA_INDEX */ "", 8646 /* MA_STATE */ "", 8647 /* MCP_ENG_DB_A_EXT_MEM */ "Engine Data-Base-A-Extension. - Memory-0 - can be access by Ingress-Meter (profile mapping) - Memory-1 - can be access by Egress-Meter (profile mapping)", 8648 /* MCP_ENG_DB_A_MEM */ "Engine Data-Base-A. - Memory-0 - can be access by Ingress-Meter / CRPS (4k engines) - Memory-1 - can be access by Egress-Meter / CRPS (4k engines) - Memories-2-7 - can be access by CRPS (4k engines)", 8649 /* MCP_ENG_DB_B_MEM */ "Engine Data-Base-B. - Memories-0-7 - can be access by CRPS (8k engines)", 8650 /* MCP_ENG_DB_C_EXT_MEM */ "Engine Data-Base-C-Extension. If allocated to Meters, these are the profile mapping tables. If allocated to Counters, these are the data MSBs", 8651 /* MCP_ENG_DB_C_MEM */ "Engine Data-Base-C. Access definition see EngDb_Bank_Source. Note: - If allocated to CRPS, these are the data LSBs", 8652 /* MCT_MCT */ "8 x 32K x 194 multicast table. Provides direct access to table.", 8653 /* MDB_ARM_KAPS_TCM */ "The R5s TCM. The host may DMA read and write this memory.", 8654 /* MDB_ARM_MEM_0 */ "INTERNAL", 8655 /* MDB_ARM_MEM_10000 */ "INTERNAL", 8656 /* MDB_ARM_MEM_30000 */ "INTERNAL", 8657 /* MDB_EEDB_ABK_BANK */ "EEDB link list pointers or encapsulation Datas hit bit", 8658 /* MDB_EEDB_ENTRY_BANK */ "EEDB link list pointers or encapsulation Datas", 8659 /* MDB_EOEM_0 */ "Interface for accessing EM database (See EMC spec for more details)", 8660 /* MDB_EOEM_1 */ "Interface for accessing EM database (See EMC spec for more details)", 8661 /* MDB_EOEM_0_DELAY_LINE_0 */ "memory mag/rg delay lines", 8662 /* MDB_EOEM_1_DELAY_LINE_0 */ "memory mag/rg delay lines", 8663 /* MDB_ESEM */ "Interface for accessing EM database (See EMC spec for more details)", 8664 /* MDB_ESEM_DELAY_LINE_0 */ "memory mag/rg delay lines", 8665 /* MDB_EXEM_1 */ "Interface for accessing EM database (See EMC spec for more details)", 8666 /* MDB_EXEM_2 */ "Interface for accessing EM database (See EMC spec for more details)", 8667 /* MDB_EXEM_3 */ "Interface for accessing EM database (See EMC spec for more details)", 8668 /* MDB_EXEM_4 */ "Interface for accessing EM database (See EMC spec for more details)", 8669 /* MDB_EXEM_1_DELAY_LINE_0 */ "memory mag/rg delay lines", 8670 /* MDB_EXEM_2_DELAY_LINE_0 */ "memory mag/rg delay lines", 8671 /* MDB_EXEM_3_DELAY_LINE_0 */ "memory mag/rg delay lines", 8672 /* MDB_EXEM_3_DELAY_LINE_1 */ "memory mag/rg delay lines", 8673 /* MDB_EXEM_3_LEARNING_BUFFER */ "EXEM3 learning packets buffer", 8674 /* MDB_EXEM_4_AGING */ "Exem_4 Aging (aka big exem)", 8675 /* MDB_EXEM_4_DELAY_LINE_0 */ "memory mag/rg delay lines", 8676 /* MDB_EXEM_4_DELAY_LINE_1 */ "memory mag/rg delay lines", 8677 /* MDB_GLEM_0 */ "Interface for accessing EM database (See EMC spec for more details)", 8678 /* MDB_GLEM_1 */ "Interface for accessing EM database (See EMC spec for more details)", 8679 /* MDB_GLEM_0_DELAY_LINE_0 */ "memory mag/rg delay lines", 8680 /* MDB_GLEM_1_DELAY_LINE_0 */ "memory mag/rg delay lines", 8681 /* MDB_IOEM_0 */ "Interface for accessing EM database (See EMC spec for more details)", 8682 /* MDB_IOEM_1 */ "Interface for accessing EM database (See EMC spec for more details)", 8683 /* MDB_IOEM_0_DELAY_LINE_0 */ "memory mag/rg delay lines", 8684 /* MDB_IOEM_1_DELAY_LINE_0 */ "memory mag/rg delay lines", 8685 /* MDB_ISEM_1 */ "Interface for accessing EM database (See EMC spec for more details)", 8686 /* MDB_ISEM_2 */ "Interface for accessing EM database (See EMC spec for more details)", 8687 /* MDB_ISEM_3 */ "Interface for accessing EM database (See EMC spec for more details)", 8688 /* MDB_ISEM_1_DELAY_LINE_0 */ "memory mag/rg delay lines", 8689 /* MDB_ISEM_2_DELAY_LINE_0 */ "memory mag/rg delay lines", 8690 /* MDB_ISEM_3_DELAY_LINE_0 */ "memory mag/rg delay lines", 8691 /* MDB_KAPS_1_DELAY_LINE_0 */ "memory mag/rg delay lines", 8692 /* MDB_KAPS_1_DELAY_LINE_1 */ "memory mag/rg delay lines", 8693 /* MDB_KAPS_2_DELAY_LINE_0 */ "memory mag/rg delay lines", 8694 /* MDB_KAPS_2_DELAY_LINE_1 */ "memory mag/rg delay lines", 8695 /* MDB_LEM */ "Interface for accessing EM database (See EMC spec for more details)", 8696 /* MDB_LEM_DELAY_LINE_0 */ "memory mag/rg delay lines", 8697 /* MDB_LEM_DELAY_LINE_1 */ "memory mag/rg delay lines", 8698 /* MDB_MC_ID */ "Interface for accessing EM database (See EMC spec for more details)", 8699 /* MDB_MC_ID_DELAY_LINE_0 */ "memory mag/rg delay lines", 8700 /* MDB_MEM_0 */ "INTERNAL", 8701 /* MDB_MEM_1000 */ "INTERNAL", 8702 /* MDB_MEM_2000 */ "INTERNAL", 8703 /* MDB_MEM_3000 */ "INTERNAL", 8704 /* MDB_MEM_4000 */ "INTERNAL", 8705 /* MDB_MEM_6000 */ "INTERNAL", 8706 /* MDB_MEM_7000 */ "INTERNAL", 8707 /* MDB_MEM_8000 */ "INTERNAL", 8708 /* MDB_MEM_9000 */ "INTERNAL", 8709 /* MDB_MEM_10000 */ "INTERNAL", 8710 /* MDB_MEM_12000 */ "INTERNAL", 8711 /* MDB_MEM_13000 */ "INTERNAL", 8712 /* MDB_MEM_14000 */ "INTERNAL", 8713 /* MDB_MEM_15000 */ "INTERNAL", 8714 /* MDB_MEM_16000 */ "INTERNAL", 8715 /* MDB_MEM_18000 */ "INTERNAL", 8716 /* MDB_MEM_19000 */ "INTERNAL", 8717 /* MDB_MEM_20000 */ "INTERNAL", 8718 /* MDB_MEM_21000 */ "INTERNAL", 8719 /* MDB_MEM_22000 */ "INTERNAL", 8720 /* MDB_MEM_23000 */ "INTERNAL", 8721 /* MDB_MEM_24000 */ "INTERNAL", 8722 /* MDB_MEM_25000 */ "INTERNAL", 8723 /* MDB_MEM_26000 */ "INTERNAL", 8724 /* MDB_MEM_27000 */ "INTERNAL", 8725 /* MDB_MEM_28000 */ "INTERNAL", 8726 /* MDB_MEM_29000 */ "INTERNAL", 8727 /* MDB_MEM_30000 */ "INTERNAL", 8728 /* MDB_MEM_31000 */ "INTERNAL", 8729 /* MDB_MEM_32000 */ "INTERNAL", 8730 /* MDB_MEM_33000 */ "INTERNAL", 8731 /* MDB_MEM_34000 */ "INTERNAL", 8732 /* MDB_MEM_35000 */ "INTERNAL", 8733 /* MDB_MEM_36000 */ "INTERNAL", 8734 /* MDB_MEM_37000 */ "INTERNAL", 8735 /* MDB_MEM_38000 */ "INTERNAL", 8736 /* MDB_MEM_39000 */ "INTERNAL", 8737 /* MDB_MEM_40000 */ "INTERNAL", 8738 /* MDB_MEM_41000 */ "INTERNAL", 8739 /* MDB_MEM_42000 */ "INTERNAL", 8740 /* MDB_MEM_43000 */ "INTERNAL", 8741 /* MDB_MEM_44000 */ "INTERNAL", 8742 /* MDB_MEM_45000 */ "INTERNAL", 8743 /* MDB_MEM_46000 */ "INTERNAL", 8744 /* MDB_MEM_47000 */ "INTERNAL", 8745 /* MDB_MEM_48000 */ "INTERNAL", 8746 /* MDB_MEM_49000 */ "INTERNAL", 8747 /* MDB_MEM_50000 */ "INTERNAL", 8748 /* MDB_MEM_51000 */ "INTERNAL", 8749 /* MDB_MEM_52000 */ "INTERNAL", 8750 /* MDB_MEM_53000 */ "INTERNAL", 8751 /* MDB_MEM_54000 */ "INTERNAL", 8752 /* MDB_MEM_55000 */ "INTERNAL", 8753 /* MDB_MEM_56000 */ "INTERNAL", 8754 /* MDB_MEM_57000 */ "INTERNAL", 8755 /* MDB_MEM_58000 */ "INTERNAL", 8756 /* MDB_MEM_59000 */ "INTERNAL", 8757 /* MDB_MEM_60000 */ "INTERNAL", 8758 /* MDB_MEM_61000 */ "INTERNAL", 8759 /* MDB_MEM_62000 */ "INTERNAL", 8760 /* MDB_MEM_63000 */ "INTERNAL", 8761 /* MDB_MEM_64000 */ "INTERNAL", 8762 /* MDB_MEM_65000 */ "INTERNAL", 8763 /* MDB_MEM_66000 */ "INTERNAL", 8764 /* MDB_MEM_67000 */ "INTERNAL", 8765 /* MDB_MEM_68000 */ "INTERNAL", 8766 /* MDB_MEM_69000 */ "INTERNAL", 8767 /* MDB_MEM_70000 */ "INTERNAL", 8768 /* MDB_MEM_71000 */ "INTERNAL", 8769 /* MDB_MEM_72000 */ "INTERNAL", 8770 /* MDB_MEM_73000 */ "INTERNAL", 8771 /* MDB_MEM_74000 */ "INTERNAL", 8772 /* MDB_MEM_75000 */ "INTERNAL", 8773 /* MDB_MEM_76000 */ "INTERNAL", 8774 /* MDB_MEM_77000 */ "INTERNAL", 8775 /* MDB_MEM_78000 */ "INTERNAL", 8776 /* MDB_MEM_79000 */ "INTERNAL", 8777 /* MDB_MEM_80000 */ "INTERNAL", 8778 /* MDB_MEM_81000 */ "INTERNAL", 8779 /* MDB_MEM_82000 */ "INTERNAL", 8780 /* MDB_MEM_83000 */ "INTERNAL", 8781 /* MDB_MEM_84000 */ "INTERNAL", 8782 /* MDB_MEM_85000 */ "INTERNAL", 8783 /* MDB_MEM_86000 */ "INTERNAL", 8784 /* MDB_MEM_87000 */ "INTERNAL", 8785 /* MDB_MEM_88000 */ "INTERNAL", 8786 /* MDB_MEM_89000 */ "INTERNAL", 8787 /* MDB_MEM_90000 */ "INTERNAL", 8788 /* MDB_MEM_91000 */ "INTERNAL", 8789 /* MDB_MEM_92000 */ "INTERNAL", 8790 /* MDB_MEM_93000 */ "INTERNAL", 8791 /* MDB_MEM_94000 */ "INTERNAL", 8792 /* MDB_MEM_95000 */ "INTERNAL", 8793 /* MDB_MEM_96000 */ "INTERNAL", 8794 /* MDB_MEM_97000 */ "INTERNAL", 8795 /* MDB_MEM_98000 */ "INTERNAL", 8796 /* MDB_MEM_99000 */ "INTERNAL", 8797 /* MDB_MEM_100000 */ "INTERNAL", 8798 /* MDB_MEM_101000 */ "INTERNAL", 8799 /* MDB_MEM_102000 */ "INTERNAL", 8800 /* MDB_MEM_103000 */ "INTERNAL", 8801 /* MDB_MEM_104000 */ "INTERNAL", 8802 /* MDB_MEM_105000 */ "INTERNAL", 8803 /* MDB_MEM_106000 */ "INTERNAL", 8804 /* MDB_MEM_107000 */ "INTERNAL", 8805 /* MDB_MEM_108000 */ "INTERNAL", 8806 /* MDB_MEM_109000 */ "INTERNAL", 8807 /* MDB_MEM_110000 */ "INTERNAL", 8808 /* MDB_MEM_111000 */ "INTERNAL", 8809 /* MDB_MEM_112000 */ "INTERNAL", 8810 /* MDB_MEM_0200000 */ "INTERNAL", 8811 /* MDB_MEM_210000 */ "INTERNAL", 8812 /* MDB_MEM_220000 */ "INTERNAL", 8813 /* MDB_MEM_230000 */ "INTERNAL", 8814 /* MDB_MEM_250000 */ "INTERNAL", 8815 /* MDB_MEM_270000 */ "INTERNAL", 8816 /* MDB_MEM_280000 */ "INTERNAL", 8817 /* MDB_MEM_2600000 */ "INTERNAL", 8818 /* MDB_RMEP */ "Interface for accessing EM database (See EMC spec for more details)", 8819 /* MDB_RMEP_DELAY_LINE_0 */ "memory mag/rg delay lines", 8820 /* MINI_UFT_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 8821 /* MIRROR_CONTROL */ "Mirror control register, FeatureSpecific-Ethernet.", 8822 /* MMU_ADM_QUEUE_DB */ "", 8823 /* MMU_ADM_SRC_CTXT_DB */ "", 8824 /* MMU_AGING_CTR */ "Aging Counter RAM", 8825 /* MMU_AGING_CTR_EXT */ "External Aging Counter RAM", 8826 /* MMU_AGING_CTR_INT */ "Internal Aging Counter RAM", 8827 /* MMU_AGING_CTR_XPE0 */ "Aging Counter RAM, Only entries 0-5375 entries are valid, rest are RESERVED", 8828 /* MMU_AGING_EXP */ "Aging Expiration Status RAM", 8829 /* MMU_AGING_EXP_EXT */ "External Aging Expiration Status RAM", 8830 /* MMU_AGING_EXP_INT */ "Internal Aging Expiration Status RAM", 8831 /* MMU_AGING_EXP_XPE0 */ "Aging Expiration Status RAM, Only entries 0-5375 entries are valid, rest are RESERVED", 8832 /* MMU_AGING_LMT_EXT */ "External Aging Limit Lookup Table, one entry per 6-bit Port value. Used for Unicast, where Limit is a function of 6-bit Port and 4-bit PRI.", 8833 /* MMU_AGING_LMT_INT */ "Internal Aging Limit Lookup Table, one entry per 6-bit Port value. Used for Unicast, where Limit is a function of 6-bit Port and 4-bit PRI.", 8834 /* MMU_AGING_MASK_TBL_PIPE0 */ "replication state of the MCQS", 8835 /* MMU_AGING_MASK_TBL_PIPE1 */ "replication state of the MCQS", 8836 /* MMU_AGING_MSK_TBL */ "Table holding the per Queue Aging Mask bits", 8837 /* MMU_AGING_MSK_TBL_XPE0_PIPE0 */ "Table holding the per Queue Aging Mask bits", 8838 /* MMU_AGING_MSK_TBL_XPE0_PIPE1 */ "Table holding the per Queue Aging Mask bits", 8839 /* MMU_ARB_TDM_TABLE */ "MMU to EPIPE Arbiter TDM Table", 8840 /* MMU_CBPCELLHEADER */ "CBP Header RAM", 8841 /* MMU_CBPDATA0 */ "CBP Data RAM 0", 8842 /* MMU_CBPDATA1 */ "CBP Data RAM 1", 8843 /* MMU_CBPDATA2 */ "CBP Data RAM 2", 8844 /* MMU_CBPDATA3 */ "CBP Data RAM 3", 8845 /* MMU_CBPDATA4 */ "CBP Data RAM 4", 8846 /* MMU_CBPDATA5 */ "CBP Data RAM 5", 8847 /* MMU_CBPDATA6 */ "CBP Data RAM 6", 8848 /* MMU_CBPDATA7 */ "CBP Data RAM 7", 8849 /* MMU_CBPDATA8 */ "CBP Data RAM 8", 8850 /* MMU_CBPDATA9 */ "CBP Data RAM 9", 8851 /* MMU_CBPDATA10 */ "CBP Data RAM 10", 8852 /* MMU_CBPDATA11 */ "CBP Data RAM 11", 8853 /* MMU_CBPDATA12 */ "CBP Data RAM 12", 8854 /* MMU_CBPDATA13 */ "CBP Data RAM 13", 8855 /* MMU_CBPDATA14 */ "CBP Data RAM 14", 8856 /* MMU_CBPDATA15 */ "CBP Data RAM 15", 8857 /* MMU_CBPDATA16 */ "CBP Data RAM 16", 8858 /* MMU_CBPDATA17 */ "CBP Data RAM 17", 8859 /* MMU_CBPDATA18 */ "CBP Data RAM 18", 8860 /* MMU_CBPDATA19 */ "CBP Data RAM 19", 8861 /* MMU_CBPDATA20 */ "CBP Data RAM 20", 8862 /* MMU_CBPDATA21 */ "CBP Data RAM 21", 8863 /* MMU_CBPDATA22 */ "CBP Data RAM 22", 8864 /* MMU_CBPDATA23 */ "CBP Data RAM 23", 8865 /* MMU_CBPDATA24 */ "CBP Data RAM 24", 8866 /* MMU_CBPDATA25 */ "CBP Data RAM 25", 8867 /* MMU_CBPDATA26 */ "CBP Data RAM 26", 8868 /* MMU_CBPDATA27 */ "CBP Data RAM 27", 8869 /* MMU_CBPDATA28 */ "CBP Data RAM 28", 8870 /* MMU_CBPDATA29 */ "CBP Data RAM 29", 8871 /* MMU_CBPDATA30 */ "CBP Data RAM 30", 8872 /* MMU_CBPDATA31 */ "CBP Data RAM 31", 8873 /* MMU_CBPDATA32 */ "CBP Data RAM 32", 8874 /* MMU_CBPDATA33 */ "CBP Data RAM 33", 8875 /* MMU_CBPDATA34 */ "CBP Data RAM 34", 8876 /* MMU_CBPDATA35 */ "CBP Data RAM 35", 8877 /* MMU_CBPDATA36 */ "CBP Data RAM 36", 8878 /* MMU_CBPDATA37 */ "CBP Data RAM 37", 8879 /* MMU_CBPDATA38 */ "CBP Data RAM 38", 8880 /* MMU_CBPDATA39 */ "CBP Data RAM 39", 8881 /* MMU_CBPDATA40 */ "CBP Data RAM 40", 8882 /* MMU_CBPDATA41 */ "CBP Data RAM 41", 8883 /* MMU_CBPDATA42 */ "CBP Data RAM 42", 8884 /* MMU_CBPDATA43 */ "CBP Data RAM 43", 8885 /* MMU_CBPDATA44 */ "CBP Data RAM 44", 8886 /* MMU_CBPDATA45 */ "CBP Data RAM 45", 8887 /* MMU_CBPDATA46 */ "CBP Data RAM 46", 8888 /* MMU_CBPDATA47 */ "CBP Data RAM 47", 8889 /* MMU_CBPDATA48 */ "CBP Data RAM 48", 8890 /* MMU_CBPDATA49 */ "CBP Data RAM 49", 8891 /* MMU_CBPDATA50 */ "CBP Data RAM 50", 8892 /* MMU_CBPDATA51 */ "CBP Data RAM 51", 8893 /* MMU_CBPDATA52 */ "CBP Data RAM 52", 8894 /* MMU_CBPDATA53 */ "CBP Data RAM 53", 8895 /* MMU_CBPDATA54 */ "CBP Data RAM 54", 8896 /* MMU_CBPDATA55 */ "CBP Data RAM 55", 8897 /* MMU_CBPDATA56 */ "CBP Data RAM 56", 8898 /* MMU_CBPDATA57 */ "CBP Data RAM 57", 8899 /* MMU_CBPDATA58 */ "CBP Data RAM 58", 8900 /* MMU_CBPDATA59 */ "CBP Data RAM 59", 8901 /* MMU_CBPDATA60 */ "CBP Data RAM 60", 8902 /* MMU_CBPDATA61 */ "CBP Data RAM 61", 8903 /* MMU_CBPDATA62 */ "CBP Data RAM 62", 8904 /* MMU_CBPDATA63 */ "CBP Data RAM 63", 8905 /* MMU_CBPDATA64 */ "CBP Data RAM 64", 8906 /* MMU_CBPDATA65 */ "CBP Data RAM 65", 8907 /* MMU_CBPDATA66 */ "CBP Data RAM 66", 8908 /* MMU_CBPDATA67 */ "CBP Data RAM 67", 8909 /* MMU_CBPDATA68 */ "CBP Data RAM 68", 8910 /* MMU_CBPDATA69 */ "CBP Data RAM 69", 8911 /* MMU_CBPDATA70 */ "CBP Data RAM 70", 8912 /* MMU_CBPDATA71 */ "CBP Data RAM 71", 8913 /* MMU_CBPDATA72 */ "CBP Data RAM 72", 8914 /* MMU_CBPDATA73 */ "CBP Data RAM 73", 8915 /* MMU_CBPDATA74 */ "CBP Data RAM 74", 8916 /* MMU_CBPDATA75 */ "CBP Data RAM 75", 8917 /* MMU_CBPDATA76 */ "CBP Data RAM 76", 8918 /* MMU_CBPDATA77 */ "CBP Data RAM 77", 8919 /* MMU_CBPDATA78 */ "CBP Data RAM 78", 8920 /* MMU_CBPDATA79 */ "CBP Data RAM 79", 8921 /* MMU_CBPDATA80 */ "CBP Data RAM 80", 8922 /* MMU_CBPDATA81 */ "CBP Data RAM 81", 8923 /* MMU_CBPDATA82 */ "CBP Data RAM 82", 8924 /* MMU_CBPDATA83 */ "CBP Data RAM 83", 8925 /* MMU_CBPDATA84 */ "CBP Data RAM 84", 8926 /* MMU_CBPDATA85 */ "CBP Data RAM 85", 8927 /* MMU_CBPDATA86 */ "CBP Data RAM 86", 8928 /* MMU_CBPDATA87 */ "CBP Data RAM 87", 8929 /* MMU_CBPDATA88 */ "CBP Data RAM 88", 8930 /* MMU_CBPDATA89 */ "CBP Data RAM 89", 8931 /* MMU_CBPDATA90 */ "CBP Data RAM 90", 8932 /* MMU_CBPDATA91 */ "CBP Data RAM 91", 8933 /* MMU_CBPDATA92 */ "CBP Data RAM 92", 8934 /* MMU_CBPDATA93 */ "CBP Data RAM 93", 8935 /* MMU_CBPDATA94 */ "CBP Data RAM 94", 8936 /* MMU_CBPDATA95 */ "CBP Data RAM 95", 8937 /* MMU_CBPDATA96 */ "CBP Data RAM 96", 8938 /* MMU_CBPDATA97 */ "CBP Data RAM 97", 8939 /* MMU_CBPDATA98 */ "CBP Data RAM 98", 8940 /* MMU_CBPDATA99 */ "CBP Data RAM 99", 8941 /* MMU_CBPDATA100 */ "CBP Data RAM 100", 8942 /* MMU_CBPDATA101 */ "CBP Data RAM 101", 8943 /* MMU_CBPDATA102 */ "CBP Data RAM 102", 8944 /* MMU_CBPDATA103 */ "CBP Data RAM 103", 8945 /* MMU_CBPDATA104 */ "CBP Data RAM 104 (bank 13, slice 0).", 8946 /* MMU_CBPDATA105 */ "CBP Data RAM 105 (bank 13, slice 1).", 8947 /* MMU_CBPDATA106 */ "CBP Data RAM 106 (bank 13, slice 2).", 8948 /* MMU_CBPDATA107 */ "CBP Data RAM 107 (bank 13, slice 3).", 8949 /* MMU_CBPDATA108 */ "CBP Data RAM 108 (bank 13, slice 4).", 8950 /* MMU_CBPDATA109 */ "CBP Data RAM 109 (bank 13, slice 5).", 8951 /* MMU_CBPDATA110 */ "CBP Data RAM 110 (bank 13, slice 6).", 8952 /* MMU_CBPDATA111 */ "CBP Data RAM 111 (bank 13, slice 7).", 8953 /* MMU_CBPDATA112 */ "CBP Data RAM 112 (bank 16, slice 3).", 8954 /* MMU_CBPDATA113 */ "CBP Data RAM 113 (bank 17, slice 3).", 8955 /* MMU_CBPDATA114 */ "CBP Data RAM 114 (bank 18, slice 3).", 8956 /* MMU_CBPDATA115 */ "CBP Data RAM 115 (bank 19, slice 3).", 8957 /* MMU_CBPDATA116 */ "CBP Data RAM 116 (bank 20, slice 3).", 8958 /* MMU_CBPDATA117 */ "CBP Data RAM 117 (bank 21, slice 3).", 8959 /* MMU_CBPDATA118 */ "CBP Data RAM 118 (bank 22, slice 3).", 8960 /* MMU_CBPDATA119 */ "CBP Data RAM 119 (bank 23, slice 3).", 8961 /* MMU_CBPDATA120 */ "CBP Data RAM 120 (bank 24, slice 3).", 8962 /* MMU_CBPDATA121 */ "CBP Data RAM 121 (bank 25, slice 3).", 8963 /* MMU_CBPDATA122 */ "CBP Data RAM 122 (bank 26, slice 3).", 8964 /* MMU_CBPDATA123 */ "CBP Data RAM 123 (bank 27, slice 3).", 8965 /* MMU_CBPDATA124 */ "CBP Data RAM 124 (bank 28, slice 3).", 8966 /* MMU_CBPDATA125 */ "CBP Data RAM 125 (bank 29, slice 3).", 8967 /* MMU_CBPDATA126 */ "CBP Data RAM 126 (bank 30, slice 3).", 8968 /* MMU_CBPDATA127 */ "CBP Data RAM 127 (bank 31, slice 3).", 8969 /* MMU_CBPDATA128 */ "CBP Data RAM 128 (bank 0, slice 4).", 8970 /* MMU_CBPDATA129 */ "CBP Data RAM 129 (bank 1, slice 4).", 8971 /* MMU_CBPDATA130 */ "CBP Data RAM 130 (bank 2, slice 4).", 8972 /* MMU_CBPDATA131 */ "CBP Data RAM 131 (bank 3, slice 4).", 8973 /* MMU_CBPDATA132 */ "CBP Data RAM 132 (bank 4, slice 4).", 8974 /* MMU_CBPDATA133 */ "CBP Data RAM 133 (bank 5, slice 4).", 8975 /* MMU_CBPDATA134 */ "CBP Data RAM 134 (bank 6, slice 4).", 8976 /* MMU_CBPDATA135 */ "CBP Data RAM 135 (bank 7, slice 4).", 8977 /* MMU_CBPDATA136 */ "CBP Data RAM 136 (bank 8, slice 4).", 8978 /* MMU_CBPDATA137 */ "CBP Data RAM 137 (bank 9, slice 4).", 8979 /* MMU_CBPDATA138 */ "CBP Data RAM 138 (bank 10, slice 4).", 8980 /* MMU_CBPDATA139 */ "CBP Data RAM 139 (bank 11, slice 4).", 8981 /* MMU_CBPDATA140 */ "CBP Data RAM 140 (bank 12, slice 4).", 8982 /* MMU_CBPDATA141 */ "CBP Data RAM 141 (bank 13, slice 4).", 8983 /* MMU_CBPDATA142 */ "CBP Data RAM 142 (bank 14, slice 4).", 8984 /* MMU_CBPDATA143 */ "CBP Data RAM 143 (bank 15, slice 4).", 8985 /* MMU_CBPDATA144 */ "CBP Data RAM 144 (bank 16, slice 4).", 8986 /* MMU_CBPDATA145 */ "CBP Data RAM 145 (bank 17, slice 4).", 8987 /* MMU_CBPDATA146 */ "CBP Data RAM 146 (bank 18, slice 4).", 8988 /* MMU_CBPDATA147 */ "CBP Data RAM 147 (bank 19, slice 4).", 8989 /* MMU_CBPDATA148 */ "CBP Data RAM 148 (bank 20, slice 4).", 8990 /* MMU_CBPDATA149 */ "CBP Data RAM 149 (bank 21, slice 4).", 8991 /* MMU_CBPDATA150 */ "CBP Data RAM 150 (bank 22, slice 4).", 8992 /* MMU_CBPDATA151 */ "CBP Data RAM 151 (bank 23, slice 4).", 8993 /* MMU_CBPDATA152 */ "CBP Data RAM 152 (bank 24, slice 4).", 8994 /* MMU_CBPDATA153 */ "CBP Data RAM 153 (bank 25, slice 4).", 8995 /* MMU_CBPDATA154 */ "CBP Data RAM 154 (bank 26, slice 4).", 8996 /* MMU_CBPDATA155 */ "CBP Data RAM 155 (bank 27, slice 4).", 8997 /* MMU_CBPDATA156 */ "CBP Data RAM 156 (bank 28, slice 4).", 8998 /* MMU_CBPDATA157 */ "CBP Data RAM 157 (bank 29, slice 4).", 8999 /* MMU_CBPDATA158 */ "CBP Data RAM 158 (bank 30, slice 4).", 9000 /* MMU_CBPDATA159 */ "CBP Data RAM 159 (bank 31, slice 4).", 9001 /* MMU_CBPDATA160 */ "CBP Data RAM 160 (bank 0, slice 5).", 9002 /* MMU_CBPDATA161 */ "CBP Data RAM 161 (bank 1, slice 5).", 9003 /* MMU_CBPDATA162 */ "CBP Data RAM 162 (bank 2, slice 5).", 9004 /* MMU_CBPDATA163 */ "CBP Data RAM 163 (bank 3, slice 5).", 9005 /* MMU_CBPDATA164 */ "CBP Data RAM 164 (bank 4, slice 5).", 9006 /* MMU_CBPDATA165 */ "CBP Data RAM 165 (bank 5, slice 5).", 9007 /* MMU_CBPDATA166 */ "CBP Data RAM 166 (bank 6, slice 5).", 9008 /* MMU_CBPDATA167 */ "CBP Data RAM 167 (bank 7, slice 5).", 9009 /* MMU_CBPDATA168 */ "CBP Data RAM 168 (bank 8, slice 5).", 9010 /* MMU_CBPDATA169 */ "CBP Data RAM 169 (bank 9, slice 5).", 9011 /* MMU_CBPDATA170 */ "CBP Data RAM 170 (bank 10, slice 5).", 9012 /* MMU_CBPDATA171 */ "CBP Data RAM 171 (bank 11, slice 5).", 9013 /* MMU_CBPDATA172 */ "CBP Data RAM 172 (bank 12, slice 5).", 9014 /* MMU_CBPDATA173 */ "CBP Data RAM 173 (bank 13, slice 5).", 9015 /* MMU_CBPDATA174 */ "CBP Data RAM 174 (bank 14, slice 5).", 9016 /* MMU_CBPDATA175 */ "CBP Data RAM 175 (bank 15, slice 5).", 9017 /* MMU_CBPDATA176 */ "CBP Data RAM 176 (bank 16, slice 5).", 9018 /* MMU_CBPDATA177 */ "CBP Data RAM 177 (bank 17, slice 5).", 9019 /* MMU_CBPDATA178 */ "CBP Data RAM 178 (bank 18, slice 5).", 9020 /* MMU_CBPDATA179 */ "CBP Data RAM 179 (bank 19, slice 5).", 9021 /* MMU_CBPDATA180 */ "CBP Data RAM 180 (bank 20, slice 5).", 9022 /* MMU_CBPDATA181 */ "CBP Data RAM 181 (bank 21, slice 5).", 9023 /* MMU_CBPDATA182 */ "CBP Data RAM 182 (bank 22, slice 5).", 9024 /* MMU_CBPDATA183 */ "CBP Data RAM 183 (bank 23, slice 5).", 9025 /* MMU_CBPDATA184 */ "CBP Data RAM 184 (bank 24, slice 5).", 9026 /* MMU_CBPDATA185 */ "CBP Data RAM 185 (bank 25, slice 5).", 9027 /* MMU_CBPDATA186 */ "CBP Data RAM 186 (bank 26, slice 5).", 9028 /* MMU_CBPDATA187 */ "CBP Data RAM 187 (bank 27, slice 5).", 9029 /* MMU_CBPDATA188 */ "CBP Data RAM 188 (bank 28, slice 5).", 9030 /* MMU_CBPDATA189 */ "CBP Data RAM 189 (bank 29, slice 5).", 9031 /* MMU_CBPDATA190 */ "CBP Data RAM 190 (bank 30, slice 5).", 9032 /* MMU_CBPDATA191 */ "CBP Data RAM 191 (bank 31, slice 5).", 9033 /* MMU_CBPDATA192 */ "CBP Data RAM 192 (bank 0, slice 6).", 9034 /* MMU_CBPDATA193 */ "CBP Data RAM 193 (bank 1, slice 6).", 9035 /* MMU_CBPDATA194 */ "CBP Data RAM 194 (bank 2, slice 6).", 9036 /* MMU_CBPDATA195 */ "CBP Data RAM 195 (bank 3, slice 6).", 9037 /* MMU_CBPDATA196 */ "CBP Data RAM 196 (bank 4, slice 6).", 9038 /* MMU_CBPDATA197 */ "CBP Data RAM 197 (bank 5, slice 6).", 9039 /* MMU_CBPDATA198 */ "CBP Data RAM 198 (bank 6, slice 6).", 9040 /* MMU_CBPDATA199 */ "CBP Data RAM 199 (bank 7, slice 6).", 9041 /* MMU_CBPDATA200 */ "CBP Data RAM 200 (bank 8, slice 6).", 9042 /* MMU_CBPDATA201 */ "CBP Data RAM 201 (bank 9, slice 6).", 9043 /* MMU_CBPDATA202 */ "CBP Data RAM 202 (bank 10, slice 6).", 9044 /* MMU_CBPDATA203 */ "CBP Data RAM 203 (bank 11, slice 6).", 9045 /* MMU_CBPDATA204 */ "CBP Data RAM 204 (bank 12, slice 6).", 9046 /* MMU_CBPDATA205 */ "CBP Data RAM 205 (bank 13, slice 6).", 9047 /* MMU_CBPDATA206 */ "CBP Data RAM 206 (bank 14, slice 6).", 9048 /* MMU_CBPDATA207 */ "CBP Data RAM 207 (bank 15, slice 6).", 9049 /* MMU_CBPDATA208 */ "CBP Data RAM 208 (bank 16, slice 6).", 9050 /* MMU_CBPDATA209 */ "CBP Data RAM 209 (bank 17, slice 6).", 9051 /* MMU_CBPDATA210 */ "CBP Data RAM 210 (bank 18, slice 6).", 9052 /* MMU_CBPDATA211 */ "CBP Data RAM 211 (bank 19, slice 6).", 9053 /* MMU_CBPDATA212 */ "CBP Data RAM 212 (bank 20, slice 6).", 9054 /* MMU_CBPDATA213 */ "CBP Data RAM 213 (bank 21, slice 6).", 9055 /* MMU_CBPDATA214 */ "CBP Data RAM 214 (bank 22, slice 6).", 9056 /* MMU_CBPDATA215 */ "CBP Data RAM 215 (bank 23, slice 6).", 9057 /* MMU_CBPDATA216 */ "CBP Data RAM 216 (bank 24, slice 6).", 9058 /* MMU_CBPDATA217 */ "CBP Data RAM 217 (bank 25, slice 6).", 9059 /* MMU_CBPDATA218 */ "CBP Data RAM 218 (bank 26, slice 6).", 9060 /* MMU_CBPDATA219 */ "CBP Data RAM 219 (bank 27, slice 6).", 9061 /* MMU_CBPDATA220 */ "CBP Data RAM 220 (bank 28, slice 6).", 9062 /* MMU_CBPDATA221 */ "CBP Data RAM 221 (bank 29, slice 6).", 9063 /* MMU_CBPDATA222 */ "CBP Data RAM 222 (bank 30, slice 6).", 9064 /* MMU_CBPDATA223 */ "CBP Data RAM 223 (bank 31, slice 6).", 9065 /* MMU_CBPDATA224 */ "CBP Data RAM 224 (bank 0, slice 7).", 9066 /* MMU_CBPDATA225 */ "CBP Data RAM 225 (bank 1, slice 7).", 9067 /* MMU_CBPDATA226 */ "CBP Data RAM 226 (bank 2, slice 7).", 9068 /* MMU_CBPDATA227 */ "CBP Data RAM 227 (bank 3, slice 7).", 9069 /* MMU_CBPDATA228 */ "CBP Data RAM 228 (bank 4, slice 7).", 9070 /* MMU_CBPDATA229 */ "CBP Data RAM 229 (bank 5, slice 7).", 9071 /* MMU_CBPDATA230 */ "CBP Data RAM 230 (bank 6, slice 7).", 9072 /* MMU_CBPDATA231 */ "CBP Data RAM 231 (bank 7, slice 7).", 9073 /* MMU_CBPDATA232 */ "CBP Data RAM 232 (bank 8, slice 7).", 9074 /* MMU_CBPDATA233 */ "CBP Data RAM 233 (bank 9, slice 7).", 9075 /* MMU_CBPDATA234 */ "CBP Data RAM 234 (bank 10, slice 7).", 9076 /* MMU_CBPDATA235 */ "CBP Data RAM 235 (bank 11, slice 7).", 9077 /* MMU_CBPDATA236 */ "CBP Data RAM 236 (bank 12, slice 7).", 9078 /* MMU_CBPDATA237 */ "CBP Data RAM 237 (bank 13, slice 7).", 9079 /* MMU_CBPDATA238 */ "CBP Data RAM 238 (bank 14, slice 7).", 9080 /* MMU_CBPDATA239 */ "CBP Data RAM 239 (bank 15, slice 7).", 9081 /* MMU_CBPDATA240 */ "CBP Data RAM 240 (bank 16, slice 7).", 9082 /* MMU_CBPDATA241 */ "CBP Data RAM 241 (bank 17, slice 7).", 9083 /* MMU_CBPDATA242 */ "CBP Data RAM 242 (bank 18, slice 7).", 9084 /* MMU_CBPDATA243 */ "CBP Data RAM 243 (bank 19, slice 7).", 9085 /* MMU_CBPDATA244 */ "CBP Data RAM 244 (bank 20, slice 7).", 9086 /* MMU_CBPDATA245 */ "CBP Data RAM 245 (bank 21, slice 7).", 9087 /* MMU_CBPDATA246 */ "CBP Data RAM 246 (bank 22, slice 7).", 9088 /* MMU_CBPDATA247 */ "CBP Data RAM 247 (bank 23, slice 7).", 9089 /* MMU_CBPDATA248 */ "CBP Data RAM 248 (bank 24, slice 7).", 9090 /* MMU_CBPDATA249 */ "CBP Data RAM 249 (bank 25, slice 7).", 9091 /* MMU_CBPDATA250 */ "CBP Data RAM 250 (bank 26, slice 7).", 9092 /* MMU_CBPDATA251 */ "CBP Data RAM 251 (bank 27, slice 7).", 9093 /* MMU_CBPDATA252 */ "CBP Data RAM 252 (bank 28, slice 7).", 9094 /* MMU_CBPDATA253 */ "CBP Data RAM 253 (bank 29, slice 7).", 9095 /* MMU_CBPDATA254 */ "CBP Data RAM 254 (bank 30, slice 7).", 9096 /* MMU_CBPDATA255 */ "CBP Data RAM 255 (bank 31, slice 7).", 9097 /* MMU_CBPDATA256 */ "CBP Data RAM 256 (bank 0, slice 8).", 9098 /* MMU_CBPDATA257 */ "CBP Data RAM 257 (bank 1, slice 8).", 9099 /* MMU_CBPDATA258 */ "CBP Data RAM 258 (bank 2, slice 8).", 9100 /* MMU_CBPDATA259 */ "CBP Data RAM 259 (bank 3, slice 8).", 9101 /* MMU_CBPDATA260 */ "CBP Data RAM 260 (bank 4, slice 8).", 9102 /* MMU_CBPDATA261 */ "CBP Data RAM 261 (bank 5, slice 8).", 9103 /* MMU_CBPDATA262 */ "CBP Data RAM 262 (bank 6, slice 8).", 9104 /* MMU_CBPDATA263 */ "CBP Data RAM 263 (bank 7, slice 8).", 9105 /* MMU_CBPDATA264 */ "CBP Data RAM 264 (bank 8, slice 8).", 9106 /* MMU_CBPDATA265 */ "CBP Data RAM 265 (bank 9, slice 8).", 9107 /* MMU_CBPDATA266 */ "CBP Data RAM 266 (bank 10, slice 8).", 9108 /* MMU_CBPDATA267 */ "CBP Data RAM 267 (bank 11, slice 8).", 9109 /* MMU_CBPDATA268 */ "CBP Data RAM 268 (bank 12, slice 8).", 9110 /* MMU_CBPDATA269 */ "CBP Data RAM 269 (bank 13, slice 8).", 9111 /* MMU_CBPDATA270 */ "CBP Data RAM 270 (bank 14, slice 8).", 9112 /* MMU_CBPDATA271 */ "CBP Data RAM 271 (bank 15, slice 8).", 9113 /* MMU_CBPDATA272 */ "CBP Data RAM 272 (bank 16, slice 8).", 9114 /* MMU_CBPDATA273 */ "CBP Data RAM 273 (bank 17, slice 8).", 9115 /* MMU_CBPDATA274 */ "CBP Data RAM 274 (bank 18, slice 8).", 9116 /* MMU_CBPDATA275 */ "CBP Data RAM 275 (bank 19, slice 8).", 9117 /* MMU_CBPDATA276 */ "CBP Data RAM 276 (bank 20, slice 8).", 9118 /* MMU_CBPDATA277 */ "CBP Data RAM 277 (bank 21, slice 8).", 9119 /* MMU_CBPDATA278 */ "CBP Data RAM 278 (bank 22, slice 8).", 9120 /* MMU_CBPDATA279 */ "CBP Data RAM 279 (bank 23, slice 8).", 9121 /* MMU_CBPDATA280 */ "CBP Data RAM 280 (bank 24, slice 8).", 9122 /* MMU_CBPDATA281 */ "CBP Data RAM 281 (bank 25, slice 8).", 9123 /* MMU_CBPDATA282 */ "CBP Data RAM 282 (bank 26, slice 8).", 9124 /* MMU_CBPDATA283 */ "CBP Data RAM 283 (bank 27, slice 8).", 9125 /* MMU_CBPDATA284 */ "CBP Data RAM 284 (bank 28, slice 8).", 9126 /* MMU_CBPDATA285 */ "CBP Data RAM 285 (bank 29, slice 8).", 9127 /* MMU_CBPDATA286 */ "CBP Data RAM 286 (bank 30, slice 8).", 9128 /* MMU_CBPDATA287 */ "CBP Data RAM 287 (bank 31, slice 8).", 9129 /* MMU_CBPDATA288 */ "CBP Data RAM 288 (bank 0, slice 9).", 9130 /* MMU_CBPDATA289 */ "CBP Data RAM 289 (bank 1, slice 9).", 9131 /* MMU_CBPDATA290 */ "CBP Data RAM 290 (bank 2, slice 9).", 9132 /* MMU_CBPDATA291 */ "CBP Data RAM 291 (bank 3, slice 9).", 9133 /* MMU_CBPDATA292 */ "CBP Data RAM 292 (bank 4, slice 9).", 9134 /* MMU_CBPDATA293 */ "CBP Data RAM 293 (bank 5, slice 9).", 9135 /* MMU_CBPDATA294 */ "CBP Data RAM 294 (bank 6, slice 9).", 9136 /* MMU_CBPDATA295 */ "CBP Data RAM 295 (bank 7, slice 9).", 9137 /* MMU_CBPDATA296 */ "CBP Data RAM 296 (bank 8, slice 9).", 9138 /* MMU_CBPDATA297 */ "CBP Data RAM 297 (bank 9, slice 9).", 9139 /* MMU_CBPDATA298 */ "CBP Data RAM 298 (bank 10, slice 9).", 9140 /* MMU_CBPDATA299 */ "CBP Data RAM 299 (bank 11, slice 9).", 9141 /* MMU_CBPDATA300 */ "CBP Data RAM 300 (bank 12, slice 9).", 9142 /* MMU_CBPDATA301 */ "CBP Data RAM 301 (bank 13, slice 9).", 9143 /* MMU_CBPDATA302 */ "CBP Data RAM 302 (bank 14, slice 9).", 9144 /* MMU_CBPDATA303 */ "CBP Data RAM 303 (bank 15, slice 9).", 9145 /* MMU_CBPDATA304 */ "CBP Data RAM 304 (bank 16, slice 9).", 9146 /* MMU_CBPDATA305 */ "CBP Data RAM 305 (bank 17, slice 9).", 9147 /* MMU_CBPDATA306 */ "CBP Data RAM 306 (bank 18, slice 9).", 9148 /* MMU_CBPDATA307 */ "CBP Data RAM 307 (bank 19, slice 9).", 9149 /* MMU_CBPDATA308 */ "CBP Data RAM 308 (bank 20, slice 9).", 9150 /* MMU_CBPDATA309 */ "CBP Data RAM 309 (bank 21, slice 9).", 9151 /* MMU_CBPDATA310 */ "CBP Data RAM 310 (bank 22, slice 9).", 9152 /* MMU_CBPDATA311 */ "CBP Data RAM 311 (bank 23, slice 9).", 9153 /* MMU_CBPDATA312 */ "CBP Data RAM 312 (bank 24, slice 9).", 9154 /* MMU_CBPDATA313 */ "CBP Data RAM 313 (bank 25, slice 9).", 9155 /* MMU_CBPDATA314 */ "CBP Data RAM 314 (bank 26, slice 9).", 9156 /* MMU_CBPDATA315 */ "CBP Data RAM 315 (bank 27, slice 9).", 9157 /* MMU_CBPDATA316 */ "CBP Data RAM 316 (bank 28, slice 9).", 9158 /* MMU_CBPDATA317 */ "CBP Data RAM 317 (bank 29, slice 9).", 9159 /* MMU_CBPDATA318 */ "CBP Data RAM 318 (bank 30, slice 9).", 9160 /* MMU_CBPDATA319 */ "CBP Data RAM 319 (bank 31, slice 9).", 9161 /* MMU_CBPDATA0_XPE0 */ "Cell buffer RAM 0. Slice 0, bank 0.", 9162 /* MMU_CBPDATA0_XPE1 */ "Cell buffer RAM 0. Slice 0, bank 0.", 9163 /* MMU_CBPDATA0_XPE2 */ "Cell buffer RAM 0. Slice 0, bank 0.", 9164 /* MMU_CBPDATA0_XPE3 */ "Cell buffer RAM 0. Slice 0, bank 0.", 9165 /* MMU_CBPDATA100_XPE0 */ "CBP Data RAM 100 (bank 12, slice 4).", 9166 /* MMU_CBPDATA100_XPE1 */ "CBP Data RAM 100 (bank 12, slice 4).", 9167 /* MMU_CBPDATA100_XPE2 */ "CBP Data RAM 100 (bank 12, slice 4).", 9168 /* MMU_CBPDATA100_XPE3 */ "CBP Data RAM 100 (bank 12, slice 4).", 9169 /* MMU_CBPDATA101_XPE0 */ "CBP Data RAM 101 (bank 12, slice 5).", 9170 /* MMU_CBPDATA101_XPE1 */ "CBP Data RAM 101 (bank 12, slice 5).", 9171 /* MMU_CBPDATA101_XPE2 */ "CBP Data RAM 101 (bank 12, slice 5).", 9172 /* MMU_CBPDATA101_XPE3 */ "CBP Data RAM 101 (bank 12, slice 5).", 9173 /* MMU_CBPDATA102_XPE0 */ "CBP Data RAM 102 (bank 12, slice 6).", 9174 /* MMU_CBPDATA102_XPE1 */ "CBP Data RAM 102 (bank 12, slice 6).", 9175 /* MMU_CBPDATA102_XPE2 */ "CBP Data RAM 102 (bank 12, slice 6).", 9176 /* MMU_CBPDATA102_XPE3 */ "CBP Data RAM 102 (bank 12, slice 6).", 9177 /* MMU_CBPDATA103_XPE0 */ "CBP Data RAM 103 (bank 12, slice 7).", 9178 /* MMU_CBPDATA103_XPE1 */ "CBP Data RAM 103 (bank 12, slice 7).", 9179 /* MMU_CBPDATA103_XPE2 */ "CBP Data RAM 103 (bank 12, slice 7).", 9180 /* MMU_CBPDATA103_XPE3 */ "CBP Data RAM 103 (bank 12, slice 7).", 9181 /* MMU_CBPDATA104_XPE0 */ "CBP Data RAM 104 (bank 13, slice 0).", 9182 /* MMU_CBPDATA104_XPE1 */ "CBP Data RAM 104 (bank 13, slice 0).", 9183 /* MMU_CBPDATA104_XPE2 */ "CBP Data RAM 104 (bank 13, slice 0).", 9184 /* MMU_CBPDATA104_XPE3 */ "CBP Data RAM 104 (bank 13, slice 0).", 9185 /* MMU_CBPDATA105_XPE0 */ "CBP Data RAM 105 (bank 13, slice 1).", 9186 /* MMU_CBPDATA105_XPE1 */ "CBP Data RAM 105 (bank 13, slice 1).", 9187 /* MMU_CBPDATA105_XPE2 */ "CBP Data RAM 105 (bank 13, slice 1).", 9188 /* MMU_CBPDATA105_XPE3 */ "CBP Data RAM 105 (bank 13, slice 1).", 9189 /* MMU_CBPDATA106_XPE0 */ "CBP Data RAM 106 (bank 13, slice 2).", 9190 /* MMU_CBPDATA106_XPE1 */ "CBP Data RAM 106 (bank 13, slice 2).", 9191 /* MMU_CBPDATA106_XPE2 */ "CBP Data RAM 106 (bank 13, slice 2).", 9192 /* MMU_CBPDATA106_XPE3 */ "CBP Data RAM 106 (bank 13, slice 2).", 9193 /* MMU_CBPDATA107_XPE0 */ "CBP Data RAM 107 (bank 13, slice 3).", 9194 /* MMU_CBPDATA107_XPE1 */ "CBP Data RAM 107 (bank 13, slice 3).", 9195 /* MMU_CBPDATA107_XPE2 */ "CBP Data RAM 107 (bank 13, slice 3).", 9196 /* MMU_CBPDATA107_XPE3 */ "CBP Data RAM 107 (bank 13, slice 3).", 9197 /* MMU_CBPDATA108_XPE0 */ "CBP Data RAM 108 (bank 13, slice 4).", 9198 /* MMU_CBPDATA108_XPE1 */ "CBP Data RAM 108 (bank 13, slice 4).", 9199 /* MMU_CBPDATA108_XPE2 */ "CBP Data RAM 108 (bank 13, slice 4).", 9200 /* MMU_CBPDATA108_XPE3 */ "CBP Data RAM 108 (bank 13, slice 4).", 9201 /* MMU_CBPDATA109_XPE0 */ "CBP Data RAM 109 (bank 13, slice 5).", 9202 /* MMU_CBPDATA109_XPE1 */ "CBP Data RAM 109 (bank 13, slice 5).", 9203 /* MMU_CBPDATA109_XPE2 */ "CBP Data RAM 109 (bank 13, slice 5).", 9204 /* MMU_CBPDATA109_XPE3 */ "CBP Data RAM 109 (bank 13, slice 5).", 9205 /* MMU_CBPDATA10_XPE0 */ "Cell buffer RAM 10. Slice 0, bank 10", 9206 /* MMU_CBPDATA10_XPE1 */ "Cell buffer RAM 10. Slice 0, bank 10", 9207 /* MMU_CBPDATA10_XPE2 */ "Cell buffer RAM 10. Slice 0, bank 10", 9208 /* MMU_CBPDATA10_XPE3 */ "Cell buffer RAM 10. Slice 0, bank 10", 9209 /* MMU_CBPDATA110_XPE0 */ "CBP Data RAM 110 (bank 13, slice 6).", 9210 /* MMU_CBPDATA110_XPE1 */ "CBP Data RAM 110 (bank 13, slice 6).", 9211 /* MMU_CBPDATA110_XPE2 */ "CBP Data RAM 110 (bank 13, slice 6).", 9212 /* MMU_CBPDATA110_XPE3 */ "CBP Data RAM 110 (bank 13, slice 6).", 9213 /* MMU_CBPDATA111_XPE0 */ "CBP Data RAM 111 (bank 13, slice 7).", 9214 /* MMU_CBPDATA111_XPE1 */ "CBP Data RAM 111 (bank 13, slice 7).", 9215 /* MMU_CBPDATA111_XPE2 */ "CBP Data RAM 111 (bank 13, slice 7).", 9216 /* MMU_CBPDATA111_XPE3 */ "CBP Data RAM 111 (bank 13, slice 7).", 9217 /* MMU_CBPDATA112_XPE0 */ "CBP Data RAM 112 (bank 16, slice 3).", 9218 /* MMU_CBPDATA113_XPE0 */ "CBP Data RAM 113 (bank 17, slice 3).", 9219 /* MMU_CBPDATA114_XPE0 */ "CBP Data RAM 114 (bank 18, slice 3).", 9220 /* MMU_CBPDATA115_XPE0 */ "CBP Data RAM 115 (bank 19, slice 3).", 9221 /* MMU_CBPDATA116_XPE0 */ "CBP Data RAM 116 (bank 20, slice 3).", 9222 /* MMU_CBPDATA117_XPE0 */ "CBP Data RAM 117 (bank 21, slice 3).", 9223 /* MMU_CBPDATA118_XPE0 */ "CBP Data RAM 118 (bank 22, slice 3).", 9224 /* MMU_CBPDATA119_XPE0 */ "CBP Data RAM 119 (bank 23, slice 3).", 9225 /* MMU_CBPDATA11_XPE0 */ "Cell buffer RAM 11. Slice 0, bank 11", 9226 /* MMU_CBPDATA11_XPE1 */ "Cell buffer RAM 11. Slice 0, bank 11", 9227 /* MMU_CBPDATA11_XPE2 */ "Cell buffer RAM 11. Slice 0, bank 11", 9228 /* MMU_CBPDATA11_XPE3 */ "Cell buffer RAM 11. Slice 0, bank 11", 9229 /* MMU_CBPDATA120_XPE0 */ "CBP Data RAM 120 (bank 24, slice 3).", 9230 /* MMU_CBPDATA121_XPE0 */ "CBP Data RAM 121 (bank 25, slice 3).", 9231 /* MMU_CBPDATA122_XPE0 */ "CBP Data RAM 122 (bank 26, slice 3).", 9232 /* MMU_CBPDATA123_XPE0 */ "CBP Data RAM 123 (bank 27, slice 3).", 9233 /* MMU_CBPDATA124_XPE0 */ "CBP Data RAM 124 (bank 28, slice 3).", 9234 /* MMU_CBPDATA125_XPE0 */ "CBP Data RAM 125 (bank 29, slice 3).", 9235 /* MMU_CBPDATA126_XPE0 */ "CBP Data RAM 126 (bank 30, slice 3).", 9236 /* MMU_CBPDATA127_XPE0 */ "CBP Data RAM 127 (bank 31, slice 3).", 9237 /* MMU_CBPDATA128_XPE0 */ "CBP Data RAM 128 (bank 0, slice 4).", 9238 /* MMU_CBPDATA129_XPE0 */ "CBP Data RAM 129 (bank 1, slice 4).", 9239 /* MMU_CBPDATA12_XPE0 */ "Cell buffer RAM 12. Slice 0, bank 12", 9240 /* MMU_CBPDATA12_XPE1 */ "Cell buffer RAM 12. Slice 0, bank 12", 9241 /* MMU_CBPDATA12_XPE2 */ "Cell buffer RAM 12. Slice 0, bank 12", 9242 /* MMU_CBPDATA12_XPE3 */ "Cell buffer RAM 12. Slice 0, bank 12", 9243 /* MMU_CBPDATA130_XPE0 */ "CBP Data RAM 130 (bank 2, slice 4).", 9244 /* MMU_CBPDATA131_XPE0 */ "CBP Data RAM 131 (bank 3, slice 4).", 9245 /* MMU_CBPDATA132_XPE0 */ "CBP Data RAM 132 (bank 4, slice 4).", 9246 /* MMU_CBPDATA133_XPE0 */ "CBP Data RAM 133 (bank 5, slice 4).", 9247 /* MMU_CBPDATA134_XPE0 */ "CBP Data RAM 134 (bank 6, slice 4).", 9248 /* MMU_CBPDATA135_XPE0 */ "CBP Data RAM 135 (bank 7, slice 4).", 9249 /* MMU_CBPDATA136_XPE0 */ "CBP Data RAM 136 (bank 8, slice 4).", 9250 /* MMU_CBPDATA137_XPE0 */ "CBP Data RAM 137 (bank 9, slice 4).", 9251 /* MMU_CBPDATA138_XPE0 */ "CBP Data RAM 138 (bank 10, slice 4).", 9252 /* MMU_CBPDATA139_XPE0 */ "CBP Data RAM 139 (bank 11, slice 4).", 9253 /* MMU_CBPDATA13_XPE0 */ "Cell buffer RAM 13. Slice 0, bank 13", 9254 /* MMU_CBPDATA13_XPE1 */ "Cell buffer RAM 13. Slice 0, bank 13", 9255 /* MMU_CBPDATA13_XPE2 */ "Cell buffer RAM 13. Slice 0, bank 13", 9256 /* MMU_CBPDATA13_XPE3 */ "Cell buffer RAM 13. Slice 0, bank 13", 9257 /* MMU_CBPDATA140_XPE0 */ "CBP Data RAM 140 (bank 12, slice 4).", 9258 /* MMU_CBPDATA141_XPE0 */ "CBP Data RAM 141 (bank 13, slice 4).", 9259 /* MMU_CBPDATA142_XPE0 */ "CBP Data RAM 142 (bank 14, slice 4).", 9260 /* MMU_CBPDATA143_XPE0 */ "CBP Data RAM 143 (bank 15, slice 4).", 9261 /* MMU_CBPDATA144_XPE0 */ "CBP Data RAM 144 (bank 16, slice 4).", 9262 /* MMU_CBPDATA145_XPE0 */ "CBP Data RAM 145 (bank 17, slice 4).", 9263 /* MMU_CBPDATA146_XPE0 */ "CBP Data RAM 146 (bank 18, slice 4).", 9264 /* MMU_CBPDATA147_XPE0 */ "CBP Data RAM 147 (bank 19, slice 4).", 9265 /* MMU_CBPDATA148_XPE0 */ "CBP Data RAM 148 (bank 20, slice 4).", 9266 /* MMU_CBPDATA149_XPE0 */ "CBP Data RAM 149 (bank 21, slice 4).", 9267 /* MMU_CBPDATA14_XPE0 */ "Cell buffer RAM 14. Slice 0, bank 14", 9268 /* MMU_CBPDATA14_XPE1 */ "Cell buffer RAM 14. Slice 0, bank 14", 9269 /* MMU_CBPDATA14_XPE2 */ "Cell buffer RAM 14. Slice 0, bank 14", 9270 /* MMU_CBPDATA14_XPE3 */ "Cell buffer RAM 14. Slice 0, bank 14", 9271 /* MMU_CBPDATA150_XPE0 */ "CBP Data RAM 150 (bank 22, slice 4).", 9272 /* MMU_CBPDATA151_XPE0 */ "CBP Data RAM 151 (bank 23, slice 4).", 9273 /* MMU_CBPDATA152_XPE0 */ "CBP Data RAM 152 (bank 24, slice 4).", 9274 /* MMU_CBPDATA153_XPE0 */ "CBP Data RAM 153 (bank 25, slice 4).", 9275 /* MMU_CBPDATA154_XPE0 */ "CBP Data RAM 154 (bank 26, slice 4).", 9276 /* MMU_CBPDATA155_XPE0 */ "CBP Data RAM 155 (bank 27, slice 4).", 9277 /* MMU_CBPDATA156_XPE0 */ "CBP Data RAM 156 (bank 28, slice 4).", 9278 /* MMU_CBPDATA157_XPE0 */ "CBP Data RAM 157 (bank 29, slice 4).", 9279 /* MMU_CBPDATA158_XPE0 */ "CBP Data RAM 158 (bank 30, slice 4).", 9280 /* MMU_CBPDATA159_XPE0 */ "CBP Data RAM 159 (bank 31, slice 4).", 9281 /* MMU_CBPDATA15_XPE0 */ "Cell buffer RAM 15. Slice 1, bank 0", 9282 /* MMU_CBPDATA15_XPE1 */ "Cell buffer RAM 15. Slice 1, bank 0", 9283 /* MMU_CBPDATA15_XPE2 */ "Cell buffer RAM 15. Slice 1, bank 0", 9284 /* MMU_CBPDATA15_XPE3 */ "Cell buffer RAM 15. Slice 1, bank 0", 9285 /* MMU_CBPDATA160_XPE0 */ "CBP Data RAM 160 (bank 0, slice 5).", 9286 /* MMU_CBPDATA161_XPE0 */ "CBP Data RAM 161 (bank 1, slice 5).", 9287 /* MMU_CBPDATA162_XPE0 */ "CBP Data RAM 162 (bank 2, slice 5).", 9288 /* MMU_CBPDATA163_XPE0 */ "CBP Data RAM 163 (bank 3, slice 5).", 9289 /* MMU_CBPDATA164_XPE0 */ "CBP Data RAM 164 (bank 4, slice 5).", 9290 /* MMU_CBPDATA165_XPE0 */ "CBP Data RAM 165 (bank 5, slice 5).", 9291 /* MMU_CBPDATA166_XPE0 */ "CBP Data RAM 166 (bank 6, slice 5).", 9292 /* MMU_CBPDATA167_XPE0 */ "CBP Data RAM 167 (bank 7, slice 5).", 9293 /* MMU_CBPDATA168_XPE0 */ "CBP Data RAM 168 (bank 8, slice 5).", 9294 /* MMU_CBPDATA169_XPE0 */ "CBP Data RAM 169 (bank 9, slice 5).", 9295 /* MMU_CBPDATA16_XPE0 */ "Cell buffer RAM 16. Slice 1, bank 1", 9296 /* MMU_CBPDATA16_XPE1 */ "Cell buffer RAM 16. Slice 1, bank 1", 9297 /* MMU_CBPDATA16_XPE2 */ "Cell buffer RAM 16. Slice 1, bank 1", 9298 /* MMU_CBPDATA16_XPE3 */ "Cell buffer RAM 16. Slice 1, bank 1", 9299 /* MMU_CBPDATA170_XPE0 */ "CBP Data RAM 170 (bank 10, slice 5).", 9300 /* MMU_CBPDATA171_XPE0 */ "CBP Data RAM 171 (bank 11, slice 5).", 9301 /* MMU_CBPDATA172_XPE0 */ "CBP Data RAM 172 (bank 12, slice 5).", 9302 /* MMU_CBPDATA173_XPE0 */ "CBP Data RAM 173 (bank 13, slice 5).", 9303 /* MMU_CBPDATA174_XPE0 */ "CBP Data RAM 174 (bank 14, slice 5).", 9304 /* MMU_CBPDATA175_XPE0 */ "CBP Data RAM 175 (bank 15, slice 5).", 9305 /* MMU_CBPDATA176_XPE0 */ "CBP Data RAM 176 (bank 16, slice 5).", 9306 /* MMU_CBPDATA177_XPE0 */ "CBP Data RAM 177 (bank 17, slice 5).", 9307 /* MMU_CBPDATA178_XPE0 */ "CBP Data RAM 178 (bank 18, slice 5).", 9308 /* MMU_CBPDATA179_XPE0 */ "CBP Data RAM 179 (bank 19, slice 5).", 9309 /* MMU_CBPDATA17_XPE0 */ "Cell buffer RAM 17. Slice 1, bank 2", 9310 /* MMU_CBPDATA17_XPE1 */ "Cell buffer RAM 17. Slice 1, bank 2", 9311 /* MMU_CBPDATA17_XPE2 */ "Cell buffer RAM 17. Slice 1, bank 2", 9312 /* MMU_CBPDATA17_XPE3 */ "Cell buffer RAM 17. Slice 1, bank 2", 9313 /* MMU_CBPDATA180_XPE0 */ "CBP Data RAM 180 (bank 20, slice 5).", 9314 /* MMU_CBPDATA181_XPE0 */ "CBP Data RAM 181 (bank 21, slice 5).", 9315 /* MMU_CBPDATA182_XPE0 */ "CBP Data RAM 182 (bank 22, slice 5).", 9316 /* MMU_CBPDATA183_XPE0 */ "CBP Data RAM 183 (bank 23, slice 5).", 9317 /* MMU_CBPDATA184_XPE0 */ "CBP Data RAM 184 (bank 24, slice 5).", 9318 /* MMU_CBPDATA185_XPE0 */ "CBP Data RAM 185 (bank 25, slice 5).", 9319 /* MMU_CBPDATA186_XPE0 */ "CBP Data RAM 186 (bank 26, slice 5).", 9320 /* MMU_CBPDATA187_XPE0 */ "CBP Data RAM 187 (bank 27, slice 5).", 9321 /* MMU_CBPDATA188_XPE0 */ "CBP Data RAM 188 (bank 28, slice 5).", 9322 /* MMU_CBPDATA189_XPE0 */ "CBP Data RAM 189 (bank 29, slice 5).", 9323 /* MMU_CBPDATA18_XPE0 */ "Cell buffer RAM 18. Slice 1, bank 3", 9324 /* MMU_CBPDATA18_XPE1 */ "Cell buffer RAM 18. Slice 1, bank 3", 9325 /* MMU_CBPDATA18_XPE2 */ "Cell buffer RAM 18. Slice 1, bank 3", 9326 /* MMU_CBPDATA18_XPE3 */ "Cell buffer RAM 18. Slice 1, bank 3", 9327 /* MMU_CBPDATA190_XPE0 */ "CBP Data RAM 190 (bank 30, slice 5).", 9328 /* MMU_CBPDATA191_XPE0 */ "CBP Data RAM 191 (bank 31, slice 5).", 9329 /* MMU_CBPDATA192_XPE0 */ "CBP Data RAM 192 (bank 0, slice 6).", 9330 /* MMU_CBPDATA193_XPE0 */ "CBP Data RAM 193 (bank 1, slice 6).", 9331 /* MMU_CBPDATA194_XPE0 */ "CBP Data RAM 194 (bank 2, slice 6).", 9332 /* MMU_CBPDATA195_XPE0 */ "CBP Data RAM 195 (bank 3, slice 6).", 9333 /* MMU_CBPDATA196_XPE0 */ "CBP Data RAM 196 (bank 4, slice 6).", 9334 /* MMU_CBPDATA197_XPE0 */ "CBP Data RAM 197 (bank 5, slice 6).", 9335 /* MMU_CBPDATA198_XPE0 */ "CBP Data RAM 198 (bank 6, slice 6).", 9336 /* MMU_CBPDATA199_XPE0 */ "CBP Data RAM 199 (bank 7, slice 6).", 9337 /* MMU_CBPDATA19_XPE0 */ "Cell buffer RAM 19. Slice 1, bank 4", 9338 /* MMU_CBPDATA19_XPE1 */ "Cell buffer RAM 19. Slice 1, bank 4", 9339 /* MMU_CBPDATA19_XPE2 */ "Cell buffer RAM 19. Slice 1, bank 4", 9340 /* MMU_CBPDATA19_XPE3 */ "Cell buffer RAM 19. Slice 1, bank 4", 9341 /* MMU_CBPDATA1_XPE0 */ "Cell buffer RAM 1. Slice 0, bank 1.", 9342 /* MMU_CBPDATA1_XPE1 */ "Cell buffer RAM 1. Slice 0, bank 1.", 9343 /* MMU_CBPDATA1_XPE2 */ "Cell buffer RAM 1. Slice 0, bank 1.", 9344 /* MMU_CBPDATA1_XPE3 */ "Cell buffer RAM 1. Slice 0, bank 1.", 9345 /* MMU_CBPDATA200_XPE0 */ "CBP Data RAM 200 (bank 8, slice 6).", 9346 /* MMU_CBPDATA201_XPE0 */ "CBP Data RAM 201 (bank 9, slice 6).", 9347 /* MMU_CBPDATA202_XPE0 */ "CBP Data RAM 202 (bank 10, slice 6).", 9348 /* MMU_CBPDATA203_XPE0 */ "CBP Data RAM 203 (bank 11, slice 6).", 9349 /* MMU_CBPDATA204_XPE0 */ "CBP Data RAM 204 (bank 12, slice 6).", 9350 /* MMU_CBPDATA205_XPE0 */ "CBP Data RAM 205 (bank 13, slice 6).", 9351 /* MMU_CBPDATA206_XPE0 */ "CBP Data RAM 206 (bank 14, slice 6).", 9352 /* MMU_CBPDATA207_XPE0 */ "CBP Data RAM 207 (bank 15, slice 6).", 9353 /* MMU_CBPDATA208_XPE0 */ "CBP Data RAM 208 (bank 16, slice 6).", 9354 /* MMU_CBPDATA209_XPE0 */ "CBP Data RAM 209 (bank 17, slice 6).", 9355 /* MMU_CBPDATA20_XPE0 */ "Cell buffer RAM 20. Slice 1, bank 5", 9356 /* MMU_CBPDATA20_XPE1 */ "Cell buffer RAM 20. Slice 1, bank 5", 9357 /* MMU_CBPDATA20_XPE2 */ "Cell buffer RAM 20. Slice 1, bank 5", 9358 /* MMU_CBPDATA20_XPE3 */ "Cell buffer RAM 20. Slice 1, bank 5", 9359 /* MMU_CBPDATA210_XPE0 */ "CBP Data RAM 210 (bank 18, slice 6).", 9360 /* MMU_CBPDATA211_XPE0 */ "CBP Data RAM 211 (bank 19, slice 6).", 9361 /* MMU_CBPDATA212_XPE0 */ "CBP Data RAM 212 (bank 20, slice 6).", 9362 /* MMU_CBPDATA213_XPE0 */ "CBP Data RAM 213 (bank 21, slice 6).", 9363 /* MMU_CBPDATA214_XPE0 */ "CBP Data RAM 214 (bank 22, slice 6).", 9364 /* MMU_CBPDATA215_XPE0 */ "CBP Data RAM 215 (bank 23, slice 6).", 9365 /* MMU_CBPDATA216_XPE0 */ "CBP Data RAM 216 (bank 24, slice 6).", 9366 /* MMU_CBPDATA217_XPE0 */ "CBP Data RAM 217 (bank 25, slice 6).", 9367 /* MMU_CBPDATA218_XPE0 */ "CBP Data RAM 218 (bank 26, slice 6).", 9368 /* MMU_CBPDATA219_XPE0 */ "CBP Data RAM 219 (bank 27, slice 6).", 9369 /* MMU_CBPDATA21_XPE0 */ "Cell buffer RAM 21. Slice 1, bank 6", 9370 /* MMU_CBPDATA21_XPE1 */ "Cell buffer RAM 21. Slice 1, bank 6", 9371 /* MMU_CBPDATA21_XPE2 */ "Cell buffer RAM 21. Slice 1, bank 6", 9372 /* MMU_CBPDATA21_XPE3 */ "Cell buffer RAM 21. Slice 1, bank 6", 9373 /* MMU_CBPDATA220_XPE0 */ "CBP Data RAM 220 (bank 28, slice 6).", 9374 /* MMU_CBPDATA221_XPE0 */ "CBP Data RAM 221 (bank 29, slice 6).", 9375 /* MMU_CBPDATA222_XPE0 */ "CBP Data RAM 222 (bank 30, slice 6).", 9376 /* MMU_CBPDATA223_XPE0 */ "CBP Data RAM 223 (bank 31, slice 6).", 9377 /* MMU_CBPDATA224_XPE0 */ "CBP Data RAM 224 (bank 0, slice 7).", 9378 /* MMU_CBPDATA225_XPE0 */ "CBP Data RAM 225 (bank 1, slice 7).", 9379 /* MMU_CBPDATA226_XPE0 */ "CBP Data RAM 226 (bank 2, slice 7).", 9380 /* MMU_CBPDATA227_XPE0 */ "CBP Data RAM 227 (bank 3, slice 7).", 9381 /* MMU_CBPDATA228_XPE0 */ "CBP Data RAM 228 (bank 4, slice 7).", 9382 /* MMU_CBPDATA229_XPE0 */ "CBP Data RAM 229 (bank 5, slice 7).", 9383 /* MMU_CBPDATA22_XPE0 */ "Cell buffer RAM 22. Slice 1, bank 7", 9384 /* MMU_CBPDATA22_XPE1 */ "Cell buffer RAM 22. Slice 1, bank 7", 9385 /* MMU_CBPDATA22_XPE2 */ "Cell buffer RAM 22. Slice 1, bank 7", 9386 /* MMU_CBPDATA22_XPE3 */ "Cell buffer RAM 22. Slice 1, bank 7", 9387 /* MMU_CBPDATA230_XPE0 */ "CBP Data RAM 230 (bank 6, slice 7).", 9388 /* MMU_CBPDATA231_XPE0 */ "CBP Data RAM 231 (bank 7, slice 7).", 9389 /* MMU_CBPDATA232_XPE0 */ "CBP Data RAM 232 (bank 8, slice 7).", 9390 /* MMU_CBPDATA233_XPE0 */ "CBP Data RAM 233 (bank 9, slice 7).", 9391 /* MMU_CBPDATA234_XPE0 */ "CBP Data RAM 234 (bank 10, slice 7).", 9392 /* MMU_CBPDATA235_XPE0 */ "CBP Data RAM 235 (bank 11, slice 7).", 9393 /* MMU_CBPDATA236_XPE0 */ "CBP Data RAM 236 (bank 12, slice 7).", 9394 /* MMU_CBPDATA237_XPE0 */ "CBP Data RAM 237 (bank 13, slice 7).", 9395 /* MMU_CBPDATA238_XPE0 */ "CBP Data RAM 238 (bank 14, slice 7).", 9396 /* MMU_CBPDATA239_XPE0 */ "CBP Data RAM 239 (bank 15, slice 7).", 9397 /* MMU_CBPDATA23_XPE0 */ "Cell buffer RAM 23. Slice 1, bank 8", 9398 /* MMU_CBPDATA23_XPE1 */ "Cell buffer RAM 23. Slice 1, bank 8", 9399 /* MMU_CBPDATA23_XPE2 */ "Cell buffer RAM 23. Slice 1, bank 8", 9400 /* MMU_CBPDATA23_XPE3 */ "Cell buffer RAM 23. Slice 1, bank 8", 9401 /* MMU_CBPDATA240_XPE0 */ "CBP Data RAM 240 (bank 16, slice 7).", 9402 /* MMU_CBPDATA241_XPE0 */ "CBP Data RAM 241 (bank 17, slice 7).", 9403 /* MMU_CBPDATA242_XPE0 */ "CBP Data RAM 242 (bank 18, slice 7).", 9404 /* MMU_CBPDATA243_XPE0 */ "CBP Data RAM 243 (bank 19, slice 7).", 9405 /* MMU_CBPDATA244_XPE0 */ "CBP Data RAM 244 (bank 20, slice 7).", 9406 /* MMU_CBPDATA245_XPE0 */ "CBP Data RAM 245 (bank 21, slice 7).", 9407 /* MMU_CBPDATA246_XPE0 */ "CBP Data RAM 246 (bank 22, slice 7).", 9408 /* MMU_CBPDATA247_XPE0 */ "CBP Data RAM 247 (bank 23, slice 7).", 9409 /* MMU_CBPDATA248_XPE0 */ "CBP Data RAM 248 (bank 24, slice 7).", 9410 /* MMU_CBPDATA249_XPE0 */ "CBP Data RAM 249 (bank 25, slice 7).", 9411 /* MMU_CBPDATA24_XPE0 */ "Cell buffer RAM 24. Slice 1, bank 9", 9412 /* MMU_CBPDATA24_XPE1 */ "Cell buffer RAM 24. Slice 1, bank 9", 9413 /* MMU_CBPDATA24_XPE2 */ "Cell buffer RAM 24. Slice 1, bank 9", 9414 /* MMU_CBPDATA24_XPE3 */ "Cell buffer RAM 24. Slice 1, bank 9", 9415 /* MMU_CBPDATA250_XPE0 */ "CBP Data RAM 250 (bank 26, slice 7).", 9416 /* MMU_CBPDATA251_XPE0 */ "CBP Data RAM 251 (bank 27, slice 7).", 9417 /* MMU_CBPDATA252_XPE0 */ "CBP Data RAM 252 (bank 28, slice 7).", 9418 /* MMU_CBPDATA253_XPE0 */ "CBP Data RAM 253 (bank 29, slice 7).", 9419 /* MMU_CBPDATA254_XPE0 */ "CBP Data RAM 254 (bank 30, slice 7).", 9420 /* MMU_CBPDATA255_XPE0 */ "CBP Data RAM 255 (bank 31, slice 7).", 9421 /* MMU_CBPDATA256_XPE0 */ "CBP Data RAM 256 (bank 0, slice 8).", 9422 /* MMU_CBPDATA257_XPE0 */ "CBP Data RAM 257 (bank 1, slice 8).", 9423 /* MMU_CBPDATA258_XPE0 */ "CBP Data RAM 258 (bank 2, slice 8).", 9424 /* MMU_CBPDATA259_XPE0 */ "CBP Data RAM 259 (bank 3, slice 8).", 9425 /* MMU_CBPDATA25_XPE0 */ "Cell buffer RAM 25. Slice 1, bank 10", 9426 /* MMU_CBPDATA25_XPE1 */ "Cell buffer RAM 25. Slice 1, bank 10", 9427 /* MMU_CBPDATA25_XPE2 */ "Cell buffer RAM 25. Slice 1, bank 10", 9428 /* MMU_CBPDATA25_XPE3 */ "Cell buffer RAM 25. Slice 1, bank 10", 9429 /* MMU_CBPDATA260_XPE0 */ "CBP Data RAM 260 (bank 4, slice 8).", 9430 /* MMU_CBPDATA261_XPE0 */ "CBP Data RAM 261 (bank 5, slice 8).", 9431 /* MMU_CBPDATA262_XPE0 */ "CBP Data RAM 262 (bank 6, slice 8).", 9432 /* MMU_CBPDATA263_XPE0 */ "CBP Data RAM 263 (bank 7, slice 8).", 9433 /* MMU_CBPDATA264_XPE0 */ "CBP Data RAM 264 (bank 8, slice 8).", 9434 /* MMU_CBPDATA265_XPE0 */ "CBP Data RAM 265 (bank 9, slice 8).", 9435 /* MMU_CBPDATA266_XPE0 */ "CBP Data RAM 266 (bank 10, slice 8).", 9436 /* MMU_CBPDATA267_XPE0 */ "CBP Data RAM 267 (bank 11, slice 8).", 9437 /* MMU_CBPDATA268_XPE0 */ "CBP Data RAM 268 (bank 12, slice 8).", 9438 /* MMU_CBPDATA269_XPE0 */ "CBP Data RAM 269 (bank 13, slice 8).", 9439 /* MMU_CBPDATA26_XPE0 */ "Cell buffer RAM 26. Slice 1, bank 11", 9440 /* MMU_CBPDATA26_XPE1 */ "Cell buffer RAM 26. Slice 1, bank 11", 9441 /* MMU_CBPDATA26_XPE2 */ "Cell buffer RAM 26. Slice 1, bank 11", 9442 /* MMU_CBPDATA26_XPE3 */ "Cell buffer RAM 26. Slice 1, bank 11", 9443 /* MMU_CBPDATA270_XPE0 */ "CBP Data RAM 270 (bank 14, slice 8).", 9444 /* MMU_CBPDATA271_XPE0 */ "CBP Data RAM 271 (bank 15, slice 8).", 9445 /* MMU_CBPDATA272_XPE0 */ "CBP Data RAM 272 (bank 16, slice 8).", 9446 /* MMU_CBPDATA273_XPE0 */ "CBP Data RAM 273 (bank 17, slice 8).", 9447 /* MMU_CBPDATA274_XPE0 */ "CBP Data RAM 274 (bank 18, slice 8).", 9448 /* MMU_CBPDATA275_XPE0 */ "CBP Data RAM 275 (bank 19, slice 8).", 9449 /* MMU_CBPDATA276_XPE0 */ "CBP Data RAM 276 (bank 20, slice 8).", 9450 /* MMU_CBPDATA277_XPE0 */ "CBP Data RAM 277 (bank 21, slice 8).", 9451 /* MMU_CBPDATA278_XPE0 */ "CBP Data RAM 278 (bank 22, slice 8).", 9452 /* MMU_CBPDATA279_XPE0 */ "CBP Data RAM 279 (bank 23, slice 8).", 9453 /* MMU_CBPDATA27_XPE0 */ "Cell buffer RAM 27. Slice 1, bank 12", 9454 /* MMU_CBPDATA27_XPE1 */ "Cell buffer RAM 27. Slice 1, bank 12", 9455 /* MMU_CBPDATA27_XPE2 */ "Cell buffer RAM 27. Slice 1, bank 12", 9456 /* MMU_CBPDATA27_XPE3 */ "Cell buffer RAM 27. Slice 1, bank 12", 9457 /* MMU_CBPDATA280_XPE0 */ "CBP Data RAM 280 (bank 24, slice 8).", 9458 /* MMU_CBPDATA281_XPE0 */ "CBP Data RAM 281 (bank 25, slice 8).", 9459 /* MMU_CBPDATA282_XPE0 */ "CBP Data RAM 282 (bank 26, slice 8).", 9460 /* MMU_CBPDATA283_XPE0 */ "CBP Data RAM 283 (bank 27, slice 8).", 9461 /* MMU_CBPDATA284_XPE0 */ "CBP Data RAM 284 (bank 28, slice 8).", 9462 /* MMU_CBPDATA285_XPE0 */ "CBP Data RAM 285 (bank 29, slice 8).", 9463 /* MMU_CBPDATA286_XPE0 */ "CBP Data RAM 286 (bank 30, slice 8).", 9464 /* MMU_CBPDATA287_XPE0 */ "CBP Data RAM 287 (bank 31, slice 8).", 9465 /* MMU_CBPDATA288_XPE0 */ "CBP Data RAM 288 (bank 0, slice 9).", 9466 /* MMU_CBPDATA289_XPE0 */ "CBP Data RAM 289 (bank 1, slice 9).", 9467 /* MMU_CBPDATA28_XPE0 */ "Cell buffer RAM 28. Slice 1, bank 13", 9468 /* MMU_CBPDATA28_XPE1 */ "Cell buffer RAM 28. Slice 1, bank 13", 9469 /* MMU_CBPDATA28_XPE2 */ "Cell buffer RAM 28. Slice 1, bank 13", 9470 /* MMU_CBPDATA28_XPE3 */ "Cell buffer RAM 28. Slice 1, bank 13", 9471 /* MMU_CBPDATA290_XPE0 */ "CBP Data RAM 290 (bank 2, slice 9).", 9472 /* MMU_CBPDATA291_XPE0 */ "CBP Data RAM 291 (bank 3, slice 9).", 9473 /* MMU_CBPDATA292_XPE0 */ "CBP Data RAM 292 (bank 4, slice 9).", 9474 /* MMU_CBPDATA293_XPE0 */ "CBP Data RAM 293 (bank 5, slice 9).", 9475 /* MMU_CBPDATA294_XPE0 */ "CBP Data RAM 294 (bank 6, slice 9).", 9476 /* MMU_CBPDATA295_XPE0 */ "CBP Data RAM 295 (bank 7, slice 9).", 9477 /* MMU_CBPDATA296_XPE0 */ "CBP Data RAM 296 (bank 8, slice 9).", 9478 /* MMU_CBPDATA297_XPE0 */ "CBP Data RAM 297 (bank 9, slice 9).", 9479 /* MMU_CBPDATA298_XPE0 */ "CBP Data RAM 298 (bank 10, slice 9).", 9480 /* MMU_CBPDATA299_XPE0 */ "CBP Data RAM 299 (bank 11, slice 9).", 9481 /* MMU_CBPDATA29_XPE0 */ "Cell buffer RAM 29. Slice 1, bank 14", 9482 /* MMU_CBPDATA29_XPE1 */ "Cell buffer RAM 29. Slice 1, bank 14", 9483 /* MMU_CBPDATA29_XPE2 */ "Cell buffer RAM 29. Slice 1, bank 14", 9484 /* MMU_CBPDATA29_XPE3 */ "Cell buffer RAM 29. Slice 1, bank 14", 9485 /* MMU_CBPDATA2_XPE0 */ "Cell buffer RAM 2. Slice 0, bank 2", 9486 /* MMU_CBPDATA2_XPE1 */ "Cell buffer RAM 2. Slice 0, bank 2", 9487 /* MMU_CBPDATA2_XPE2 */ "Cell buffer RAM 2. Slice 0, bank 2", 9488 /* MMU_CBPDATA2_XPE3 */ "Cell buffer RAM 2. Slice 0, bank 2", 9489 /* MMU_CBPDATA300_XPE0 */ "CBP Data RAM 300 (bank 12, slice 9).", 9490 /* MMU_CBPDATA301_XPE0 */ "CBP Data RAM 301 (bank 13, slice 9).", 9491 /* MMU_CBPDATA302_XPE0 */ "CBP Data RAM 302 (bank 14, slice 9).", 9492 /* MMU_CBPDATA303_XPE0 */ "CBP Data RAM 303 (bank 15, slice 9).", 9493 /* MMU_CBPDATA304_XPE0 */ "CBP Data RAM 304 (bank 16, slice 9).", 9494 /* MMU_CBPDATA305_XPE0 */ "CBP Data RAM 305 (bank 17, slice 9).", 9495 /* MMU_CBPDATA306_XPE0 */ "CBP Data RAM 306 (bank 18, slice 9).", 9496 /* MMU_CBPDATA307_XPE0 */ "CBP Data RAM 307 (bank 19, slice 9).", 9497 /* MMU_CBPDATA308_XPE0 */ "CBP Data RAM 308 (bank 20, slice 9).", 9498 /* MMU_CBPDATA309_XPE0 */ "CBP Data RAM 309 (bank 21, slice 9).", 9499 /* MMU_CBPDATA30_XPE0 */ "Cell buffer RAM 30. Slice 2, bank 0", 9500 /* MMU_CBPDATA30_XPE1 */ "Cell buffer RAM 30. Slice 2, bank 0", 9501 /* MMU_CBPDATA30_XPE2 */ "Cell buffer RAM 30. Slice 2, bank 0", 9502 /* MMU_CBPDATA30_XPE3 */ "Cell buffer RAM 30. Slice 2, bank 0", 9503 /* MMU_CBPDATA310_XPE0 */ "CBP Data RAM 310 (bank 22, slice 9).", 9504 /* MMU_CBPDATA311_XPE0 */ "CBP Data RAM 311 (bank 23, slice 9).", 9505 /* MMU_CBPDATA312_XPE0 */ "CBP Data RAM 312 (bank 24, slice 9).", 9506 /* MMU_CBPDATA313_XPE0 */ "CBP Data RAM 313 (bank 25, slice 9).", 9507 /* MMU_CBPDATA314_XPE0 */ "CBP Data RAM 314 (bank 26, slice 9).", 9508 /* MMU_CBPDATA315_XPE0 */ "CBP Data RAM 315 (bank 27, slice 9).", 9509 /* MMU_CBPDATA316_XPE0 */ "CBP Data RAM 316 (bank 28, slice 9).", 9510 /* MMU_CBPDATA317_XPE0 */ "CBP Data RAM 317 (bank 29, slice 9).", 9511 /* MMU_CBPDATA318_XPE0 */ "CBP Data RAM 318 (bank 30, slice 9).", 9512 /* MMU_CBPDATA319_XPE0 */ "CBP Data RAM 319 (bank 31, slice 9).", 9513 /* MMU_CBPDATA31_XPE0 */ "Cell buffer RAM 31. Slice 2, bank 1", 9514 /* MMU_CBPDATA31_XPE1 */ "Cell buffer RAM 31. Slice 2, bank 1", 9515 /* MMU_CBPDATA31_XPE2 */ "Cell buffer RAM 31. Slice 2, bank 1", 9516 /* MMU_CBPDATA31_XPE3 */ "Cell buffer RAM 31. Slice 2, bank 1", 9517 /* MMU_CBPDATA32_XPE0 */ "Cell buffer RAM 32. Slice 2, bank 2", 9518 /* MMU_CBPDATA32_XPE1 */ "Cell buffer RAM 32. Slice 2, bank 2", 9519 /* MMU_CBPDATA32_XPE2 */ "Cell buffer RAM 32. Slice 2, bank 2", 9520 /* MMU_CBPDATA32_XPE3 */ "Cell buffer RAM 32. Slice 2, bank 2", 9521 /* MMU_CBPDATA33_XPE0 */ "Cell buffer RAM 33. Slice 2, bank 3", 9522 /* MMU_CBPDATA33_XPE1 */ "Cell buffer RAM 33. Slice 2, bank 3", 9523 /* MMU_CBPDATA33_XPE2 */ "Cell buffer RAM 33. Slice 2, bank 3", 9524 /* MMU_CBPDATA33_XPE3 */ "Cell buffer RAM 33. Slice 2, bank 3", 9525 /* MMU_CBPDATA34_XPE0 */ "Cell buffer RAM 34. Slice 2, bank 4", 9526 /* MMU_CBPDATA34_XPE1 */ "Cell buffer RAM 34. Slice 2, bank 4", 9527 /* MMU_CBPDATA34_XPE2 */ "Cell buffer RAM 34. Slice 2, bank 4", 9528 /* MMU_CBPDATA34_XPE3 */ "Cell buffer RAM 34. Slice 2, bank 4", 9529 /* MMU_CBPDATA35_XPE0 */ "Cell buffer RAM 35. Slice 2, bank 5", 9530 /* MMU_CBPDATA35_XPE1 */ "Cell buffer RAM 35. Slice 2, bank 5", 9531 /* MMU_CBPDATA35_XPE2 */ "Cell buffer RAM 35. Slice 2, bank 5", 9532 /* MMU_CBPDATA35_XPE3 */ "Cell buffer RAM 35. Slice 2, bank 5", 9533 /* MMU_CBPDATA36_XPE0 */ "Cell buffer RAM 36. Slice 2, bank 6", 9534 /* MMU_CBPDATA36_XPE1 */ "Cell buffer RAM 36. Slice 2, bank 6", 9535 /* MMU_CBPDATA36_XPE2 */ "Cell buffer RAM 36. Slice 2, bank 6", 9536 /* MMU_CBPDATA36_XPE3 */ "Cell buffer RAM 36. Slice 2, bank 6", 9537 /* MMU_CBPDATA37_XPE0 */ "Cell buffer RAM 37. Slice 2, bank 7", 9538 /* MMU_CBPDATA37_XPE1 */ "Cell buffer RAM 37. Slice 2, bank 7", 9539 /* MMU_CBPDATA37_XPE2 */ "Cell buffer RAM 37. Slice 2, bank 7", 9540 /* MMU_CBPDATA37_XPE3 */ "Cell buffer RAM 37. Slice 2, bank 7", 9541 /* MMU_CBPDATA38_XPE0 */ "Cell buffer RAM 38. Slice 2, bank 8", 9542 /* MMU_CBPDATA38_XPE1 */ "Cell buffer RAM 38. Slice 2, bank 8", 9543 /* MMU_CBPDATA38_XPE2 */ "Cell buffer RAM 38. Slice 2, bank 8", 9544 /* MMU_CBPDATA38_XPE3 */ "Cell buffer RAM 38. Slice 2, bank 8", 9545 /* MMU_CBPDATA39_XPE0 */ "Cell buffer RAM 39. Slice 2, bank 9", 9546 /* MMU_CBPDATA39_XPE1 */ "Cell buffer RAM 39. Slice 2, bank 9", 9547 /* MMU_CBPDATA39_XPE2 */ "Cell buffer RAM 39. Slice 2, bank 9", 9548 /* MMU_CBPDATA39_XPE3 */ "Cell buffer RAM 39. Slice 2, bank 9", 9549 /* MMU_CBPDATA3_XPE0 */ "Cell buffer RAM 3. Slice 0, bank 3", 9550 /* MMU_CBPDATA3_XPE1 */ "Cell buffer RAM 3. Slice 0, bank 3", 9551 /* MMU_CBPDATA3_XPE2 */ "Cell buffer RAM 3. Slice 0, bank 3", 9552 /* MMU_CBPDATA3_XPE3 */ "Cell buffer RAM 3. Slice 0, bank 3", 9553 /* MMU_CBPDATA40_XPE0 */ "Cell buffer RAM 40. Slice 2, bank 10", 9554 /* MMU_CBPDATA40_XPE1 */ "Cell buffer RAM 40. Slice 2, bank 10", 9555 /* MMU_CBPDATA40_XPE2 */ "Cell buffer RAM 40. Slice 2, bank 10", 9556 /* MMU_CBPDATA40_XPE3 */ "Cell buffer RAM 40. Slice 2, bank 10", 9557 /* MMU_CBPDATA41_XPE0 */ "Cell buffer RAM 41. Slice 2, bank 11", 9558 /* MMU_CBPDATA41_XPE1 */ "Cell buffer RAM 41. Slice 2, bank 11", 9559 /* MMU_CBPDATA41_XPE2 */ "Cell buffer RAM 41. Slice 2, bank 11", 9560 /* MMU_CBPDATA41_XPE3 */ "Cell buffer RAM 41. Slice 2, bank 11", 9561 /* MMU_CBPDATA42_XPE0 */ "Cell buffer RAM 42. Slice 2, bank 12", 9562 /* MMU_CBPDATA42_XPE1 */ "Cell buffer RAM 42. Slice 2, bank 12", 9563 /* MMU_CBPDATA42_XPE2 */ "Cell buffer RAM 42. Slice 2, bank 12", 9564 /* MMU_CBPDATA42_XPE3 */ "Cell buffer RAM 42. Slice 2, bank 12", 9565 /* MMU_CBPDATA43_XPE0 */ "Cell buffer RAM 43. Slice 2, bank 13", 9566 /* MMU_CBPDATA43_XPE1 */ "Cell buffer RAM 43. Slice 2, bank 13", 9567 /* MMU_CBPDATA43_XPE2 */ "Cell buffer RAM 43. Slice 2, bank 13", 9568 /* MMU_CBPDATA43_XPE3 */ "Cell buffer RAM 43. Slice 2, bank 13", 9569 /* MMU_CBPDATA44_XPE0 */ "Cell buffer RAM 44. Slice 2, bank 14", 9570 /* MMU_CBPDATA44_XPE1 */ "Cell buffer RAM 44. Slice 2, bank 14", 9571 /* MMU_CBPDATA44_XPE2 */ "Cell buffer RAM 44. Slice 2, bank 14", 9572 /* MMU_CBPDATA44_XPE3 */ "Cell buffer RAM 44. Slice 2, bank 14", 9573 /* MMU_CBPDATA45_XPE0 */ "Cell buffer RAM 45. Slice 3, bank 0", 9574 /* MMU_CBPDATA45_XPE1 */ "Cell buffer RAM 45. Slice 3, bank 0", 9575 /* MMU_CBPDATA45_XPE2 */ "Cell buffer RAM 45. Slice 3, bank 0", 9576 /* MMU_CBPDATA45_XPE3 */ "Cell buffer RAM 45. Slice 3, bank 0", 9577 /* MMU_CBPDATA46_XPE0 */ "Cell buffer RAM 46. Slice 3, bank 1", 9578 /* MMU_CBPDATA46_XPE1 */ "Cell buffer RAM 46. Slice 3, bank 1", 9579 /* MMU_CBPDATA46_XPE2 */ "Cell buffer RAM 46. Slice 3, bank 1", 9580 /* MMU_CBPDATA46_XPE3 */ "Cell buffer RAM 46. Slice 3, bank 1", 9581 /* MMU_CBPDATA47_XPE0 */ "Cell buffer RAM 47. Slice 3, bank 2", 9582 /* MMU_CBPDATA47_XPE1 */ "Cell buffer RAM 47. Slice 3, bank 2", 9583 /* MMU_CBPDATA47_XPE2 */ "Cell buffer RAM 47. Slice 3, bank 2", 9584 /* MMU_CBPDATA47_XPE3 */ "Cell buffer RAM 47. Slice 3, bank 2", 9585 /* MMU_CBPDATA48_XPE0 */ "Cell buffer RAM 48. Slice 3, bank 3", 9586 /* MMU_CBPDATA48_XPE1 */ "Cell buffer RAM 48. Slice 3, bank 3", 9587 /* MMU_CBPDATA48_XPE2 */ "Cell buffer RAM 48. Slice 3, bank 3", 9588 /* MMU_CBPDATA48_XPE3 */ "Cell buffer RAM 48. Slice 3, bank 3", 9589 /* MMU_CBPDATA49_XPE0 */ "Cell buffer RAM 49. Slice 3, bank 4", 9590 /* MMU_CBPDATA49_XPE1 */ "Cell buffer RAM 49. Slice 3, bank 4", 9591 /* MMU_CBPDATA49_XPE2 */ "Cell buffer RAM 49. Slice 3, bank 4", 9592 /* MMU_CBPDATA49_XPE3 */ "Cell buffer RAM 49. Slice 3, bank 4", 9593 /* MMU_CBPDATA4_XPE0 */ "Cell buffer RAM 4. Slice 0, bank 4", 9594 /* MMU_CBPDATA4_XPE1 */ "Cell buffer RAM 4. Slice 0, bank 4", 9595 /* MMU_CBPDATA4_XPE2 */ "Cell buffer RAM 4. Slice 0, bank 4", 9596 /* MMU_CBPDATA4_XPE3 */ "Cell buffer RAM 4. Slice 0, bank 4", 9597 /* MMU_CBPDATA50_XPE0 */ "Cell buffer RAM 50. Slice 3, bank 5", 9598 /* MMU_CBPDATA50_XPE1 */ "Cell buffer RAM 50. Slice 3, bank 5", 9599 /* MMU_CBPDATA50_XPE2 */ "Cell buffer RAM 50. Slice 3, bank 5", 9600 /* MMU_CBPDATA50_XPE3 */ "Cell buffer RAM 50. Slice 3, bank 5", 9601 /* MMU_CBPDATA51_XPE0 */ "Cell buffer RAM 51. Slice 3, bank 6", 9602 /* MMU_CBPDATA51_XPE1 */ "Cell buffer RAM 51. Slice 3, bank 6", 9603 /* MMU_CBPDATA51_XPE2 */ "Cell buffer RAM 51. Slice 3, bank 6", 9604 /* MMU_CBPDATA51_XPE3 */ "Cell buffer RAM 51. Slice 3, bank 6", 9605 /* MMU_CBPDATA52_XPE0 */ "Cell buffer RAM 52. Slice 3, bank 7", 9606 /* MMU_CBPDATA52_XPE1 */ "Cell buffer RAM 52. Slice 3, bank 7", 9607 /* MMU_CBPDATA52_XPE2 */ "Cell buffer RAM 52. Slice 3, bank 7", 9608 /* MMU_CBPDATA52_XPE3 */ "Cell buffer RAM 52. Slice 3, bank 7", 9609 /* MMU_CBPDATA53_XPE0 */ "Cell buffer RAM 53. Slice 3, bank 8", 9610 /* MMU_CBPDATA53_XPE1 */ "Cell buffer RAM 53. Slice 3, bank 8", 9611 /* MMU_CBPDATA53_XPE2 */ "Cell buffer RAM 53. Slice 3, bank 8", 9612 /* MMU_CBPDATA53_XPE3 */ "Cell buffer RAM 53. Slice 3, bank 8", 9613 /* MMU_CBPDATA54_XPE0 */ "Cell buffer RAM 54. Slice 3, bank 9", 9614 /* MMU_CBPDATA54_XPE1 */ "Cell buffer RAM 54. Slice 3, bank 9", 9615 /* MMU_CBPDATA54_XPE2 */ "Cell buffer RAM 54. Slice 3, bank 9", 9616 /* MMU_CBPDATA54_XPE3 */ "Cell buffer RAM 54. Slice 3, bank 9", 9617 /* MMU_CBPDATA55_XPE0 */ "Cell buffer RAM 55. Slice 3, bank 10", 9618 /* MMU_CBPDATA55_XPE1 */ "Cell buffer RAM 55. Slice 3, bank 10", 9619 /* MMU_CBPDATA55_XPE2 */ "Cell buffer RAM 55. Slice 3, bank 10", 9620 /* MMU_CBPDATA55_XPE3 */ "Cell buffer RAM 55. Slice 3, bank 10", 9621 /* MMU_CBPDATA56_XPE0 */ "Cell buffer RAM 56. Slice 3, bank 11", 9622 /* MMU_CBPDATA56_XPE1 */ "Cell buffer RAM 56. Slice 3, bank 11", 9623 /* MMU_CBPDATA56_XPE2 */ "Cell buffer RAM 56. Slice 3, bank 11", 9624 /* MMU_CBPDATA56_XPE3 */ "Cell buffer RAM 56. Slice 3, bank 11", 9625 /* MMU_CBPDATA57_XPE0 */ "Cell buffer RAM 57. Slice 3, bank 12", 9626 /* MMU_CBPDATA57_XPE1 */ "Cell buffer RAM 57. Slice 3, bank 12", 9627 /* MMU_CBPDATA57_XPE2 */ "Cell buffer RAM 57. Slice 3, bank 12", 9628 /* MMU_CBPDATA57_XPE3 */ "Cell buffer RAM 57. Slice 3, bank 12", 9629 /* MMU_CBPDATA58_XPE0 */ "Cell buffer RAM 58. Slice 3, bank 13", 9630 /* MMU_CBPDATA58_XPE1 */ "Cell buffer RAM 58. Slice 3, bank 13", 9631 /* MMU_CBPDATA58_XPE2 */ "Cell buffer RAM 58. Slice 3, bank 13", 9632 /* MMU_CBPDATA58_XPE3 */ "Cell buffer RAM 58. Slice 3, bank 13", 9633 /* MMU_CBPDATA59_XPE0 */ "Cell buffer RAM 59. Slice 3, bank 14", 9634 /* MMU_CBPDATA59_XPE1 */ "Cell buffer RAM 59. Slice 3, bank 14", 9635 /* MMU_CBPDATA59_XPE2 */ "Cell buffer RAM 59. Slice 3, bank 14", 9636 /* MMU_CBPDATA59_XPE3 */ "Cell buffer RAM 59. Slice 3, bank 14", 9637 /* MMU_CBPDATA5_XPE0 */ "Cell buffer RAM 5. Slice 0, bank 5", 9638 /* MMU_CBPDATA5_XPE1 */ "Cell buffer RAM 5. Slice 0, bank 5", 9639 /* MMU_CBPDATA5_XPE2 */ "Cell buffer RAM 5. Slice 0, bank 5", 9640 /* MMU_CBPDATA5_XPE3 */ "Cell buffer RAM 5. Slice 0, bank 5", 9641 /* MMU_CBPDATA60_XPE0 */ "Cell buffer RAM 60. Slice 3, bank 3.", 9642 /* MMU_CBPDATA60_XPE1 */ "Cell buffer RAM 60. Slice 3, bank 3.", 9643 /* MMU_CBPDATA60_XPE2 */ "Cell buffer RAM 60. Slice 3, bank 3.", 9644 /* MMU_CBPDATA60_XPE3 */ "Cell buffer RAM 60. Slice 3, bank 3.", 9645 /* MMU_CBPDATA61_XPE0 */ "Cell buffer RAM 61. Slice 3, bank 4.", 9646 /* MMU_CBPDATA61_XPE1 */ "Cell buffer RAM 61. Slice 3, bank 4.", 9647 /* MMU_CBPDATA61_XPE2 */ "Cell buffer RAM 61. Slice 3, bank 4.", 9648 /* MMU_CBPDATA61_XPE3 */ "Cell buffer RAM 61. Slice 3, bank 4.", 9649 /* MMU_CBPDATA62_XPE0 */ "Cell buffer RAM 62. Slice 3, bank 5.", 9650 /* MMU_CBPDATA62_XPE1 */ "Cell buffer RAM 62. Slice 3, bank 5.", 9651 /* MMU_CBPDATA62_XPE2 */ "Cell buffer RAM 62. Slice 3, bank 5.", 9652 /* MMU_CBPDATA62_XPE3 */ "Cell buffer RAM 62. Slice 3, bank 5.", 9653 /* MMU_CBPDATA63_XPE0 */ "Cell buffer RAM 63. Slice 3, bank 6.", 9654 /* MMU_CBPDATA63_XPE1 */ "Cell buffer RAM 63. Slice 3, bank 6.", 9655 /* MMU_CBPDATA63_XPE2 */ "Cell buffer RAM 63. Slice 3, bank 6.", 9656 /* MMU_CBPDATA63_XPE3 */ "Cell buffer RAM 63. Slice 3, bank 6.", 9657 /* MMU_CBPDATA64_XPE0 */ "Cell buffer RAM 64. Slice 3, bank 7.", 9658 /* MMU_CBPDATA64_XPE1 */ "Cell buffer RAM 64. Slice 3, bank 7.", 9659 /* MMU_CBPDATA64_XPE2 */ "Cell buffer RAM 64. Slice 3, bank 7.", 9660 /* MMU_CBPDATA64_XPE3 */ "Cell buffer RAM 64. Slice 3, bank 7.", 9661 /* MMU_CBPDATA65_XPE0 */ "Cell buffer RAM 65. Slice 3, bank 8.", 9662 /* MMU_CBPDATA65_XPE1 */ "Cell buffer RAM 65. Slice 3, bank 8.", 9663 /* MMU_CBPDATA65_XPE2 */ "Cell buffer RAM 65. Slice 3, bank 8.", 9664 /* MMU_CBPDATA65_XPE3 */ "Cell buffer RAM 65. Slice 3, bank 8.", 9665 /* MMU_CBPDATA66_XPE0 */ "Cell buffer RAM 66. Slice 3, bank 9.", 9666 /* MMU_CBPDATA66_XPE1 */ "Cell buffer RAM 66. Slice 3, bank 9.", 9667 /* MMU_CBPDATA66_XPE2 */ "Cell buffer RAM 66. Slice 3, bank 9.", 9668 /* MMU_CBPDATA66_XPE3 */ "Cell buffer RAM 66. Slice 3, bank 9.", 9669 /* MMU_CBPDATA67_XPE0 */ "Cell buffer RAM 67. Slice 3, bank 10.", 9670 /* MMU_CBPDATA67_XPE1 */ "Cell buffer RAM 67. Slice 3, bank 10.", 9671 /* MMU_CBPDATA67_XPE2 */ "Cell buffer RAM 67. Slice 3, bank 10.", 9672 /* MMU_CBPDATA67_XPE3 */ "Cell buffer RAM 67. Slice 3, bank 10.", 9673 /* MMU_CBPDATA68_XPE0 */ "Cell buffer RAM 68. Slice 3, bank 11.", 9674 /* MMU_CBPDATA68_XPE1 */ "Cell buffer RAM 68. Slice 3, bank 11.", 9675 /* MMU_CBPDATA68_XPE2 */ "Cell buffer RAM 68. Slice 3, bank 11.", 9676 /* MMU_CBPDATA68_XPE3 */ "Cell buffer RAM 68. Slice 3, bank 11.", 9677 /* MMU_CBPDATA69_XPE0 */ "Cell buffer RAM 69. Slice 3, bank 12.", 9678 /* MMU_CBPDATA69_XPE1 */ "Cell buffer RAM 69. Slice 3, bank 12.", 9679 /* MMU_CBPDATA69_XPE2 */ "Cell buffer RAM 69. Slice 3, bank 12.", 9680 /* MMU_CBPDATA69_XPE3 */ "Cell buffer RAM 69. Slice 3, bank 12.", 9681 /* MMU_CBPDATA6_XPE0 */ "Cell buffer RAM 6. Slice 0, bank 6", 9682 /* MMU_CBPDATA6_XPE1 */ "Cell buffer RAM 6. Slice 0, bank 6", 9683 /* MMU_CBPDATA6_XPE2 */ "Cell buffer RAM 6. Slice 0, bank 6", 9684 /* MMU_CBPDATA6_XPE3 */ "Cell buffer RAM 6. Slice 0, bank 6", 9685 /* MMU_CBPDATA70_XPE0 */ "Cell buffer RAM 70. Slice 3, bank 13.", 9686 /* MMU_CBPDATA70_XPE1 */ "Cell buffer RAM 70. Slice 3, bank 13.", 9687 /* MMU_CBPDATA70_XPE2 */ "Cell buffer RAM 70. Slice 3, bank 13.", 9688 /* MMU_CBPDATA70_XPE3 */ "Cell buffer RAM 70. Slice 3, bank 13.", 9689 /* MMU_CBPDATA71_XPE0 */ "Cell buffer RAM 71. Slice 3, bank 14.", 9690 /* MMU_CBPDATA71_XPE1 */ "Cell buffer RAM 71. Slice 3, bank 14.", 9691 /* MMU_CBPDATA71_XPE2 */ "Cell buffer RAM 71. Slice 3, bank 14.", 9692 /* MMU_CBPDATA71_XPE3 */ "Cell buffer RAM 71. Slice 3, bank 14.", 9693 /* MMU_CBPDATA72_XPE0 */ "Cell buffer RAM 72. Slice 3, bank 15.", 9694 /* MMU_CBPDATA72_XPE1 */ "Cell buffer RAM 72. Slice 3, bank 15.", 9695 /* MMU_CBPDATA72_XPE2 */ "Cell buffer RAM 72. Slice 3, bank 15.", 9696 /* MMU_CBPDATA72_XPE3 */ "Cell buffer RAM 72. Slice 3, bank 15.", 9697 /* MMU_CBPDATA73_XPE0 */ "Cell buffer RAM 73. Slice 3, bank 16.", 9698 /* MMU_CBPDATA73_XPE1 */ "Cell buffer RAM 73. Slice 3, bank 16.", 9699 /* MMU_CBPDATA73_XPE2 */ "Cell buffer RAM 73. Slice 3, bank 16.", 9700 /* MMU_CBPDATA73_XPE3 */ "Cell buffer RAM 73. Slice 3, bank 16.", 9701 /* MMU_CBPDATA74_XPE0 */ "Cell buffer RAM 74. Slice 3, bank 17.", 9702 /* MMU_CBPDATA74_XPE1 */ "Cell buffer RAM 74. Slice 3, bank 17.", 9703 /* MMU_CBPDATA74_XPE2 */ "Cell buffer RAM 74. Slice 3, bank 17.", 9704 /* MMU_CBPDATA74_XPE3 */ "Cell buffer RAM 74. Slice 3, bank 17.", 9705 /* MMU_CBPDATA75_XPE0 */ "Cell buffer RAM 75. Slice 3, bank 18.", 9706 /* MMU_CBPDATA75_XPE1 */ "Cell buffer RAM 75. Slice 3, bank 18.", 9707 /* MMU_CBPDATA75_XPE2 */ "Cell buffer RAM 75. Slice 3, bank 18.", 9708 /* MMU_CBPDATA75_XPE3 */ "Cell buffer RAM 75. Slice 3, bank 18.", 9709 /* MMU_CBPDATA76_XPE0 */ "CBP Data RAM 76 (bank 9, slice 4).", 9710 /* MMU_CBPDATA76_XPE1 */ "CBP Data RAM 76 (bank 9, slice 4).", 9711 /* MMU_CBPDATA76_XPE2 */ "CBP Data RAM 76 (bank 9, slice 4).", 9712 /* MMU_CBPDATA76_XPE3 */ "CBP Data RAM 76 (bank 9, slice 4).", 9713 /* MMU_CBPDATA77_XPE0 */ "CBP Data RAM 77 (bank 9, slice 5).", 9714 /* MMU_CBPDATA77_XPE1 */ "CBP Data RAM 77 (bank 9, slice 5).", 9715 /* MMU_CBPDATA77_XPE2 */ "CBP Data RAM 77 (bank 9, slice 5).", 9716 /* MMU_CBPDATA77_XPE3 */ "CBP Data RAM 77 (bank 9, slice 5).", 9717 /* MMU_CBPDATA78_XPE0 */ "CBP Data RAM 78 (bank 9, slice 6).", 9718 /* MMU_CBPDATA78_XPE1 */ "CBP Data RAM 78 (bank 9, slice 6).", 9719 /* MMU_CBPDATA78_XPE2 */ "CBP Data RAM 78 (bank 9, slice 6).", 9720 /* MMU_CBPDATA78_XPE3 */ "CBP Data RAM 78 (bank 9, slice 6).", 9721 /* MMU_CBPDATA79_XPE0 */ "CBP Data RAM 79 (bank 9, slice 7).", 9722 /* MMU_CBPDATA79_XPE1 */ "CBP Data RAM 79 (bank 9, slice 7).", 9723 /* MMU_CBPDATA79_XPE2 */ "CBP Data RAM 79 (bank 9, slice 7).", 9724 /* MMU_CBPDATA79_XPE3 */ "CBP Data RAM 79 (bank 9, slice 7).", 9725 /* MMU_CBPDATA7_XPE0 */ "Cell buffer RAM 7. Slice 0, bank 7", 9726 /* MMU_CBPDATA7_XPE1 */ "Cell buffer RAM 7. Slice 0, bank 7", 9727 /* MMU_CBPDATA7_XPE2 */ "Cell buffer RAM 7. Slice 0, bank 7", 9728 /* MMU_CBPDATA7_XPE3 */ "Cell buffer RAM 7. Slice 0, bank 7", 9729 /* MMU_CBPDATA80_XPE0 */ "CBP Data RAM 80 (bank 10, slice 0).", 9730 /* MMU_CBPDATA80_XPE1 */ "CBP Data RAM 80 (bank 10, slice 0).", 9731 /* MMU_CBPDATA80_XPE2 */ "CBP Data RAM 80 (bank 10, slice 0).", 9732 /* MMU_CBPDATA80_XPE3 */ "CBP Data RAM 80 (bank 10, slice 0).", 9733 /* MMU_CBPDATA81_XPE0 */ "CBP Data RAM 81 (bank 10, slice 1).", 9734 /* MMU_CBPDATA81_XPE1 */ "CBP Data RAM 81 (bank 10, slice 1).", 9735 /* MMU_CBPDATA81_XPE2 */ "CBP Data RAM 81 (bank 10, slice 1).", 9736 /* MMU_CBPDATA81_XPE3 */ "CBP Data RAM 81 (bank 10, slice 1).", 9737 /* MMU_CBPDATA82_XPE0 */ "CBP Data RAM 82 (bank 10, slice 2).", 9738 /* MMU_CBPDATA82_XPE1 */ "CBP Data RAM 82 (bank 10, slice 2).", 9739 /* MMU_CBPDATA82_XPE2 */ "CBP Data RAM 82 (bank 10, slice 2).", 9740 /* MMU_CBPDATA82_XPE3 */ "CBP Data RAM 82 (bank 10, slice 2).", 9741 /* MMU_CBPDATA83_XPE0 */ "CBP Data RAM 83 (bank 10, slice 3).", 9742 /* MMU_CBPDATA83_XPE1 */ "CBP Data RAM 83 (bank 10, slice 3).", 9743 /* MMU_CBPDATA83_XPE2 */ "CBP Data RAM 83 (bank 10, slice 3).", 9744 /* MMU_CBPDATA83_XPE3 */ "CBP Data RAM 83 (bank 10, slice 3).", 9745 /* MMU_CBPDATA84_XPE0 */ "CBP Data RAM 84 (bank 10, slice 4).", 9746 /* MMU_CBPDATA84_XPE1 */ "CBP Data RAM 84 (bank 10, slice 4).", 9747 /* MMU_CBPDATA84_XPE2 */ "CBP Data RAM 84 (bank 10, slice 4).", 9748 /* MMU_CBPDATA84_XPE3 */ "CBP Data RAM 84 (bank 10, slice 4).", 9749 /* MMU_CBPDATA85_XPE0 */ "CBP Data RAM 85 (bank 10, slice 5).", 9750 /* MMU_CBPDATA85_XPE1 */ "CBP Data RAM 85 (bank 10, slice 5).", 9751 /* MMU_CBPDATA85_XPE2 */ "CBP Data RAM 85 (bank 10, slice 5).", 9752 /* MMU_CBPDATA85_XPE3 */ "CBP Data RAM 85 (bank 10, slice 5).", 9753 /* MMU_CBPDATA86_XPE0 */ "CBP Data RAM 86 (bank 10, slice 6).", 9754 /* MMU_CBPDATA86_XPE1 */ "CBP Data RAM 86 (bank 10, slice 6).", 9755 /* MMU_CBPDATA86_XPE2 */ "CBP Data RAM 86 (bank 10, slice 6).", 9756 /* MMU_CBPDATA86_XPE3 */ "CBP Data RAM 86 (bank 10, slice 6).", 9757 /* MMU_CBPDATA87_XPE0 */ "CBP Data RAM 87 (bank 10, slice 7).", 9758 /* MMU_CBPDATA87_XPE1 */ "CBP Data RAM 87 (bank 10, slice 7).", 9759 /* MMU_CBPDATA87_XPE2 */ "CBP Data RAM 87 (bank 10, slice 7).", 9760 /* MMU_CBPDATA87_XPE3 */ "CBP Data RAM 87 (bank 10, slice 7).", 9761 /* MMU_CBPDATA88_XPE0 */ "CBP Data RAM 88 (bank 11, slice 0).", 9762 /* MMU_CBPDATA88_XPE1 */ "CBP Data RAM 88 (bank 11, slice 0).", 9763 /* MMU_CBPDATA88_XPE2 */ "CBP Data RAM 88 (bank 11, slice 0).", 9764 /* MMU_CBPDATA88_XPE3 */ "CBP Data RAM 88 (bank 11, slice 0).", 9765 /* MMU_CBPDATA89_XPE0 */ "CBP Data RAM 89 (bank 11, slice 1).", 9766 /* MMU_CBPDATA89_XPE1 */ "CBP Data RAM 89 (bank 11, slice 1).", 9767 /* MMU_CBPDATA89_XPE2 */ "CBP Data RAM 89 (bank 11, slice 1).", 9768 /* MMU_CBPDATA89_XPE3 */ "CBP Data RAM 89 (bank 11, slice 1).", 9769 /* MMU_CBPDATA8_XPE0 */ "Cell buffer RAM 8. Slice 0, bank 8", 9770 /* MMU_CBPDATA8_XPE1 */ "Cell buffer RAM 8. Slice 0, bank 8", 9771 /* MMU_CBPDATA8_XPE2 */ "Cell buffer RAM 8. Slice 0, bank 8", 9772 /* MMU_CBPDATA8_XPE3 */ "Cell buffer RAM 8. Slice 0, bank 8", 9773 /* MMU_CBPDATA90_XPE0 */ "CBP Data RAM 90 (bank 11, slice 2).", 9774 /* MMU_CBPDATA90_XPE1 */ "CBP Data RAM 90 (bank 11, slice 2).", 9775 /* MMU_CBPDATA90_XPE2 */ "CBP Data RAM 90 (bank 11, slice 2).", 9776 /* MMU_CBPDATA90_XPE3 */ "CBP Data RAM 90 (bank 11, slice 2).", 9777 /* MMU_CBPDATA91_XPE0 */ "CBP Data RAM 91 (bank 11, slice 3).", 9778 /* MMU_CBPDATA91_XPE1 */ "CBP Data RAM 91 (bank 11, slice 3).", 9779 /* MMU_CBPDATA91_XPE2 */ "CBP Data RAM 91 (bank 11, slice 3).", 9780 /* MMU_CBPDATA91_XPE3 */ "CBP Data RAM 91 (bank 11, slice 3).", 9781 /* MMU_CBPDATA92_XPE0 */ "CBP Data RAM 92 (bank 11, slice 4).", 9782 /* MMU_CBPDATA92_XPE1 */ "CBP Data RAM 92 (bank 11, slice 4).", 9783 /* MMU_CBPDATA92_XPE2 */ "CBP Data RAM 92 (bank 11, slice 4).", 9784 /* MMU_CBPDATA92_XPE3 */ "CBP Data RAM 92 (bank 11, slice 4).", 9785 /* MMU_CBPDATA93_XPE0 */ "CBP Data RAM 93 (bank 11, slice 5).", 9786 /* MMU_CBPDATA93_XPE1 */ "CBP Data RAM 93 (bank 11, slice 5).", 9787 /* MMU_CBPDATA93_XPE2 */ "CBP Data RAM 93 (bank 11, slice 5).", 9788 /* MMU_CBPDATA93_XPE3 */ "CBP Data RAM 93 (bank 11, slice 5).", 9789 /* MMU_CBPDATA94_XPE0 */ "CBP Data RAM 94 (bank 11, slice 6).", 9790 /* MMU_CBPDATA94_XPE1 */ "CBP Data RAM 94 (bank 11, slice 6).", 9791 /* MMU_CBPDATA94_XPE2 */ "CBP Data RAM 94 (bank 11, slice 6).", 9792 /* MMU_CBPDATA94_XPE3 */ "CBP Data RAM 94 (bank 11, slice 6).", 9793 /* MMU_CBPDATA95_XPE0 */ "CBP Data RAM 95 (bank 11, slice 7).", 9794 /* MMU_CBPDATA95_XPE1 */ "CBP Data RAM 95 (bank 11, slice 7).", 9795 /* MMU_CBPDATA95_XPE2 */ "CBP Data RAM 95 (bank 11, slice 7).", 9796 /* MMU_CBPDATA95_XPE3 */ "CBP Data RAM 95 (bank 11, slice 7).", 9797 /* MMU_CBPDATA96_XPE0 */ "CBP Data RAM 96 (bank 12, slice 0).", 9798 /* MMU_CBPDATA96_XPE1 */ "CBP Data RAM 96 (bank 12, slice 0).", 9799 /* MMU_CBPDATA96_XPE2 */ "CBP Data RAM 96 (bank 12, slice 0).", 9800 /* MMU_CBPDATA96_XPE3 */ "CBP Data RAM 96 (bank 12, slice 0).", 9801 /* MMU_CBPDATA97_XPE0 */ "CBP Data RAM 97 (bank 12, slice 1).", 9802 /* MMU_CBPDATA97_XPE1 */ "CBP Data RAM 97 (bank 12, slice 1).", 9803 /* MMU_CBPDATA97_XPE2 */ "CBP Data RAM 97 (bank 12, slice 1).", 9804 /* MMU_CBPDATA97_XPE3 */ "CBP Data RAM 97 (bank 12, slice 1).", 9805 /* MMU_CBPDATA98_XPE0 */ "CBP Data RAM 98 (bank 12, slice 2).", 9806 /* MMU_CBPDATA98_XPE1 */ "CBP Data RAM 98 (bank 12, slice 2).", 9807 /* MMU_CBPDATA98_XPE2 */ "CBP Data RAM 98 (bank 12, slice 2).", 9808 /* MMU_CBPDATA98_XPE3 */ "CBP Data RAM 98 (bank 12, slice 2).", 9809 /* MMU_CBPDATA99_XPE0 */ "CBP Data RAM 99 (bank 12, slice 3).", 9810 /* MMU_CBPDATA99_XPE1 */ "CBP Data RAM 99 (bank 12, slice 3).", 9811 /* MMU_CBPDATA99_XPE2 */ "CBP Data RAM 99 (bank 12, slice 3).", 9812 /* MMU_CBPDATA99_XPE3 */ "CBP Data RAM 99 (bank 12, slice 3).", 9813 /* MMU_CBPDATA9_XPE0 */ "Cell buffer RAM 9. Slice 0, bank 9", 9814 /* MMU_CBPDATA9_XPE1 */ "Cell buffer RAM 9. Slice 0, bank 9", 9815 /* MMU_CBPDATA9_XPE2 */ "Cell buffer RAM 9. Slice 0, bank 9", 9816 /* MMU_CBPDATA9_XPE3 */ "Cell buffer RAM 9. Slice 0, bank 9", 9817 /* MMU_CBPI_0 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 0", 9818 /* MMU_CBPI_1 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 1", 9819 /* MMU_CBPI_2 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 2", 9820 /* MMU_CBPI_3 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 3", 9821 /* MMU_CBPI_4 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 4", 9822 /* MMU_CBPI_5 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 5", 9823 /* MMU_CBPI_6 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 6", 9824 /* MMU_CBPI_7 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 7", 9825 /* MMU_CBPI_8 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 8", 9826 /* MMU_CBPI_9 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 9", 9827 /* MMU_CBPI_10 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 10", 9828 /* MMU_CBPI_11 */ "Internal Payload Memory, Address Range 0 to 10923, RAM 11", 9829 /* MMU_CBPPKTHEADER0 */ "CBP Packet Header RAM 0", 9830 /* MMU_CBPPKTHEADER1 */ "CBP Packet Header RAM 1", 9831 /* MMU_CBPPKTHEADER2 */ "CBP Packet Header RAM 1 MEM0", 9832 /* MMU_CBPPKTHEADER0_MEM0 */ "CBP Packet Header RAM 0", 9833 /* MMU_CBPPKTHEADER0_MEM1 */ "CBP Packet Header RAM 1", 9834 /* MMU_CBPPKTHEADER0_MEM2 */ "CBP Packet Header RAM 2", 9835 /* MMU_CBPPKTHEADER0_MEM3 */ "CBP Packet Header RAM 2", 9836 /* MMU_CBPPKTHEADER1_MEM0 */ "CBP Packet Header RAM 1 MEM0", 9837 /* MMU_CBPPKTHEADER1_MEM1 */ "CBP Packet Header RAM 1 MEM0", 9838 /* MMU_CBPPKTHEADER1_MEM2 */ "CBP Packet Header 1 RAM 2", 9839 /* MMU_CBPPKTHEADERCPU */ "CBP Packet Header CPU RAM", 9840 /* MMU_CBPPKTHEADER_EXT */ "CBP Packet Header RAM 2 - is written at EOP", 9841 /* MMU_CBPPKTLENGTH */ "CBP Packet Length RAM", 9842 /* MMU_CBP_CELL_LINK */ "CBP Cell link memory", 9843 /* MMU_CCP */ "Copy Count Pool RAM", 9844 /* MMU_CCP0_RESEQ_MEM */ "Copy Count Pool RAM", 9845 /* MMU_CCP1_RESEQ_MEM */ "Copy Count Pool RAM", 9846 /* MMU_CCPE_MEM */ "External Buffer Copy Count Pool RAM", 9847 /* MMU_CCPI_MEM */ "Internal Buffer Copy Count Pool RAM", 9848 /* MMU_CCP_COPY_COUNT_INFO */ "Logical view of the CCP COPY_COUNT_INFO table that maintains the copy count value of each cell pointer", 9849 /* MMU_CCP_COPY_COUNT_INFO_ITM0 */ "Logical view of the CCP COPY_COUNT_INFO table that maintains the copy count value of each cell pointer", 9850 /* MMU_CCP_COPY_COUNT_INFO_ITM1 */ "Logical view of the CCP COPY_COUNT_INFO table that maintains the copy count value of each cell pointer", 9851 /* MMU_CCP_MEM */ "Copy Count Pool RAM", 9852 /* MMU_CCP_MEM_XPE0 */ "Copy Count Pool RAM", 9853 /* MMU_CCP_MEM_XPE1 */ "Copy Count Pool RAM", 9854 /* MMU_CCP_MEM_XPE2 */ "Copy Count Pool RAM", 9855 /* MMU_CCP_MEM_XPE3 */ "Copy Count Pool RAM", 9856 /* MMU_CCP_RELEASE_FIFO */ "CCP Release FiFo", 9857 /* MMU_CCP_RESEQ_MEM */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9858 /* MMU_CCP_RESEQ_MEM_XPE0_PIPE0 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9859 /* MMU_CCP_RESEQ_MEM_XPE0_PIPE1 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9860 /* MMU_CCP_RESEQ_MEM_XPE1_PIPE2 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9861 /* MMU_CCP_RESEQ_MEM_XPE1_PIPE3 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9862 /* MMU_CCP_RESEQ_MEM_XPE2_PIPE0 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9863 /* MMU_CCP_RESEQ_MEM_XPE2_PIPE1 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9864 /* MMU_CCP_RESEQ_MEM_XPE3_PIPE2 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9865 /* MMU_CCP_RESEQ_MEM_XPE3_PIPE3 */ "This is a working memory maintained by hardware.\nThis memory contains the per port database of RESEQ information for delayed SOP cell return\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 9866 /* MMU_CELLCHK */ "Cell CRC Check", 9867 /* MMU_CELLCHK0 */ "Cell CRC Check", 9868 /* MMU_CELLCHK1 */ "Cell CRC Check", 9869 /* MMU_CELLCHK2 */ "Cell CRC Check", 9870 /* MMU_CELLCHK3 */ "Cell CRC Check", 9871 /* MMU_CELLLINK */ "CELLLINK", 9872 /* MMU_CELLLINKE */ "CELLLINK Database for External Buffers", 9873 /* MMU_CELLLINKI */ "CELLLINK Database for Internal Buffers", 9874 /* MMU_CELL_LINK */ "CELL_LINK", 9875 /* MMU_CELL_LINK_XPE0 */ "Cell link memory. This is a working FIFO maintained by hardware.", 9876 /* MMU_CELL_LINK_XPE1 */ "Cell link memory. This is a working FIFO maintained by hardware.", 9877 /* MMU_CELL_LINK_XPE2 */ "Cell link memory. This is a working FIFO maintained by hardware.", 9878 /* MMU_CELL_LINK_XPE3 */ "Cell link memory. This is a working FIFO maintained by hardware.", 9879 /* MMU_CFAP */ "CBP Free Address Pool RAM", 9880 /* MMU_CFAPE_BITMAP */ "External Free Address Pool Bitmap RAM", 9881 /* MMU_CFAPE_STACK */ "Internal Free Address Pool Stack RAM", 9882 /* MMU_CFAPI0_BITMAP */ "Internal Free Address Pool Bitmap RAM", 9883 /* MMU_CFAPI0_STACK */ "Internal Free Address Pool Stack RAM", 9884 /* MMU_CFAPI1_BITMAP */ "External Free Address Pool Bitmap RAM", 9885 /* MMU_CFAPI1_STACK */ "Internal Free Address Pool Stack RAM", 9886 /* MMU_CFAPI_BITMAP */ "Internal Free Address Pool Bitmap RAM", 9887 /* MMU_CFAPI_STACK */ "Internal Free Address Pool Stack RAM", 9888 /* MMU_CFAP_BANK0 */ "CBP Free Address Pool RAM", 9889 /* MMU_CFAP_BANK1 */ "CBP Free Address Pool RAM", 9890 /* MMU_CFAP_BANK2 */ "CBP Free Address Pool RAM", 9891 /* MMU_CFAP_BANK3 */ "CBP Free Address Pool RAM", 9892 /* MMU_CFAP_BANK4 */ "CBP Free Address Pool RAM", 9893 /* MMU_CFAP_BANK5 */ "CBP Free Address Pool RAM", 9894 /* MMU_CFAP_BANK6 */ "CBP Free Address Pool RAM", 9895 /* MMU_CFAP_BANK7 */ "CBP Free Address Pool RAM", 9896 /* MMU_CFAP_BANK8 */ "CBP Free Address Pool RAM", 9897 /* MMU_CFAP_BANK9 */ "CBP Free Address Pool RAM", 9898 /* MMU_CFAP_BANK10 */ "CBP Free Address Pool RAM", 9899 /* MMU_CFAP_BANK11 */ "CBP Free Address Pool RAM", 9900 /* MMU_CFAP_BANK12 */ "CBP Free Address Pool RAM", 9901 /* MMU_CFAP_BANK13 */ "CBP Free Address Pool RAM", 9902 /* MMU_CFAP_BANK14 */ "CBP Free Address Pool RAM", 9903 /* MMU_CFAP_BANK15 */ "CBP Free Address Pool RAM", 9904 /* MMU_CFAP_BANK16 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9905 /* MMU_CFAP_BANK17 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9906 /* MMU_CFAP_BANK18 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9907 /* MMU_CFAP_BANK19 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9908 /* MMU_CFAP_BANK20 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9909 /* MMU_CFAP_BANK21 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9910 /* MMU_CFAP_BANK22 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9911 /* MMU_CFAP_BANK23 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9912 /* MMU_CFAP_BANK24 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9913 /* MMU_CFAP_BANK25 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9914 /* MMU_CFAP_BANK26 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9915 /* MMU_CFAP_BANK27 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9916 /* MMU_CFAP_BANK28 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9917 /* MMU_CFAP_BANK29 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9918 /* MMU_CFAP_BANK30 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9919 /* MMU_CFAP_BANK31 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9920 /* MMU_CFAP_BANK32 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9921 /* MMU_CFAP_BANK33 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9922 /* MMU_CFAP_BANK0_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9923 /* MMU_CFAP_BANK0_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9924 /* MMU_CFAP_BANK0_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9925 /* MMU_CFAP_BANK0_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9926 /* MMU_CFAP_BANK0_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9927 /* MMU_CFAP_BANK0_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9928 /* MMU_CFAP_BANK10_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9929 /* MMU_CFAP_BANK10_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9930 /* MMU_CFAP_BANK10_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9931 /* MMU_CFAP_BANK10_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9932 /* MMU_CFAP_BANK10_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9933 /* MMU_CFAP_BANK10_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9934 /* MMU_CFAP_BANK11_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9935 /* MMU_CFAP_BANK11_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9936 /* MMU_CFAP_BANK11_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9937 /* MMU_CFAP_BANK11_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9938 /* MMU_CFAP_BANK11_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9939 /* MMU_CFAP_BANK11_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9940 /* MMU_CFAP_BANK12_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9941 /* MMU_CFAP_BANK12_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9942 /* MMU_CFAP_BANK12_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9943 /* MMU_CFAP_BANK12_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9944 /* MMU_CFAP_BANK12_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9945 /* MMU_CFAP_BANK12_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9946 /* MMU_CFAP_BANK13_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9947 /* MMU_CFAP_BANK13_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9948 /* MMU_CFAP_BANK13_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9949 /* MMU_CFAP_BANK13_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9950 /* MMU_CFAP_BANK13_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9951 /* MMU_CFAP_BANK13_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9952 /* MMU_CFAP_BANK14_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9953 /* MMU_CFAP_BANK14_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9954 /* MMU_CFAP_BANK14_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9955 /* MMU_CFAP_BANK14_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9956 /* MMU_CFAP_BANK14_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9957 /* MMU_CFAP_BANK14_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9958 /* MMU_CFAP_BANK15_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9959 /* MMU_CFAP_BANK15_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9960 /* MMU_CFAP_BANK15_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9961 /* MMU_CFAP_BANK15_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9962 /* MMU_CFAP_BANK15_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9963 /* MMU_CFAP_BANK15_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9964 /* MMU_CFAP_BANK16_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9965 /* MMU_CFAP_BANK16_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9966 /* MMU_CFAP_BANK16_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9967 /* MMU_CFAP_BANK16_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9968 /* MMU_CFAP_BANK16_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9969 /* MMU_CFAP_BANK16_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9970 /* MMU_CFAP_BANK17_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9971 /* MMU_CFAP_BANK17_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9972 /* MMU_CFAP_BANK17_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9973 /* MMU_CFAP_BANK17_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9974 /* MMU_CFAP_BANK17_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9975 /* MMU_CFAP_BANK17_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9976 /* MMU_CFAP_BANK18_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9977 /* MMU_CFAP_BANK18_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9978 /* MMU_CFAP_BANK18_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9979 /* MMU_CFAP_BANK18_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9980 /* MMU_CFAP_BANK18_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9981 /* MMU_CFAP_BANK18_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9982 /* MMU_CFAP_BANK19_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9983 /* MMU_CFAP_BANK19_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9984 /* MMU_CFAP_BANK19_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9985 /* MMU_CFAP_BANK1_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9986 /* MMU_CFAP_BANK1_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9987 /* MMU_CFAP_BANK1_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9988 /* MMU_CFAP_BANK1_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9989 /* MMU_CFAP_BANK1_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9990 /* MMU_CFAP_BANK1_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9991 /* MMU_CFAP_BANK20_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9992 /* MMU_CFAP_BANK20_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9993 /* MMU_CFAP_BANK20_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9994 /* MMU_CFAP_BANK21_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9995 /* MMU_CFAP_BANK21_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9996 /* MMU_CFAP_BANK21_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 9997 /* MMU_CFAP_BANK22_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9998 /* MMU_CFAP_BANK22_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 9999 /* MMU_CFAP_BANK22_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10000 /* MMU_CFAP_BANK23_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10001 /* MMU_CFAP_BANK23_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10002 /* MMU_CFAP_BANK23_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10003 /* MMU_CFAP_BANK24_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10004 /* MMU_CFAP_BANK24_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10005 /* MMU_CFAP_BANK24_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10006 /* MMU_CFAP_BANK25_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10007 /* MMU_CFAP_BANK25_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10008 /* MMU_CFAP_BANK25_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10009 /* MMU_CFAP_BANK26_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10010 /* MMU_CFAP_BANK26_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10011 /* MMU_CFAP_BANK26_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10012 /* MMU_CFAP_BANK27_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10013 /* MMU_CFAP_BANK27_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10014 /* MMU_CFAP_BANK27_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10015 /* MMU_CFAP_BANK28_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10016 /* MMU_CFAP_BANK28_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10017 /* MMU_CFAP_BANK28_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10018 /* MMU_CFAP_BANK29_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10019 /* MMU_CFAP_BANK29_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10020 /* MMU_CFAP_BANK29_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10021 /* MMU_CFAP_BANK2_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10022 /* MMU_CFAP_BANK2_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10023 /* MMU_CFAP_BANK2_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10024 /* MMU_CFAP_BANK2_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10025 /* MMU_CFAP_BANK2_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10026 /* MMU_CFAP_BANK2_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10027 /* MMU_CFAP_BANK30_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10028 /* MMU_CFAP_BANK30_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10029 /* MMU_CFAP_BANK30_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10030 /* MMU_CFAP_BANK31_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10031 /* MMU_CFAP_BANK31_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10032 /* MMU_CFAP_BANK31_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10033 /* MMU_CFAP_BANK32_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10034 /* MMU_CFAP_BANK32_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10035 /* MMU_CFAP_BANK33_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10036 /* MMU_CFAP_BANK33_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10037 /* MMU_CFAP_BANK3_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10038 /* MMU_CFAP_BANK3_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10039 /* MMU_CFAP_BANK3_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10040 /* MMU_CFAP_BANK3_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10041 /* MMU_CFAP_BANK3_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10042 /* MMU_CFAP_BANK3_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10043 /* MMU_CFAP_BANK4_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10044 /* MMU_CFAP_BANK4_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10045 /* MMU_CFAP_BANK4_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10046 /* MMU_CFAP_BANK4_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10047 /* MMU_CFAP_BANK4_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10048 /* MMU_CFAP_BANK4_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10049 /* MMU_CFAP_BANK5_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10050 /* MMU_CFAP_BANK5_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10051 /* MMU_CFAP_BANK5_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10052 /* MMU_CFAP_BANK5_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10053 /* MMU_CFAP_BANK5_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10054 /* MMU_CFAP_BANK5_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10055 /* MMU_CFAP_BANK6_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10056 /* MMU_CFAP_BANK6_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10057 /* MMU_CFAP_BANK6_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10058 /* MMU_CFAP_BANK6_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10059 /* MMU_CFAP_BANK6_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10060 /* MMU_CFAP_BANK6_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10061 /* MMU_CFAP_BANK7_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10062 /* MMU_CFAP_BANK7_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10063 /* MMU_CFAP_BANK7_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10064 /* MMU_CFAP_BANK7_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10065 /* MMU_CFAP_BANK7_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10066 /* MMU_CFAP_BANK7_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10067 /* MMU_CFAP_BANK8_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10068 /* MMU_CFAP_BANK8_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10069 /* MMU_CFAP_BANK8_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10070 /* MMU_CFAP_BANK8_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10071 /* MMU_CFAP_BANK8_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10072 /* MMU_CFAP_BANK8_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10073 /* MMU_CFAP_BANK9_ITM0 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10074 /* MMU_CFAP_BANK9_ITM1 */ "Depth = 2048. Free Address Pool of cell pointers for bank 0 where each entry holds 2 cell pointers. This memory should not be accessed by SW during normal operation.\nPhysically made up of eight 512 deep x 2 cell pointer wide SRFs, and the 4 sub-banks have the addresses interleaved.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Cell Ptr 1,0 Cell Ptr 1,0 Cell Ptr 1,0 Cell ...", 10075 /* MMU_CFAP_BANK9_XPE0 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10076 /* MMU_CFAP_BANK9_XPE1 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10077 /* MMU_CFAP_BANK9_XPE2 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10078 /* MMU_CFAP_BANK9_XPE3 */ "CBP Free Address Pool RAM. This memory should not be accessed by SW during normal operation.", 10079 /* MMU_CFAP_MEM */ "CBP Free Address Pool RAM", 10080 /* MMU_CHFC_SYSPORT_MAPPING */ "Mapping from channel Flow Control Byte number to System port number", 10081 /* MMU_CPQLINK */ "CPQLINK", 10082 /* MMU_CRB_CT_DELAY_LINE_IP_MEM */ "CT Delay line for the cells received from IP. CCBI data which is used by THDI, THDR, SCB and RL needs to be stored till the CT decision is known. Data from all 4 IPs is stored in this memory.", 10083 /* MMU_CRB_CT_DELAY_LINE_IP_MEM_ITM0 */ "CT Delay line for the cells received from IP. CCBI data which is used by THDI, THDR, SCB and RL needs to be stored till the CT decision is known. Data from all 4 IPs is stored in this memory.", 10084 /* MMU_CRB_CT_DELAY_LINE_IP_MEM_ITM1 */ "CT Delay line for the cells received from IP. CCBI data which is used by THDI, THDR, SCB and RL needs to be stored till the CT decision is known. Data from all 4 IPs is stored in this memory.", 10085 /* MMU_CRB_CT_DELAY_LINE_RQE_MEM */ "CT delay line for the cells received from RQE. It is stored till the CT decision is known.", 10086 /* MMU_CRB_CT_DELAY_LINE_RQE_MEM_ITM0 */ "CT delay line for the cells received from RQE. It is stored till the CT decision is known.", 10087 /* MMU_CRB_CT_DELAY_LINE_RQE_MEM_ITM1 */ "CT delay line for the cells received from RQE. It is stored till the CT decision is known.", 10088 /* MMU_CTR_COLOR_DROP_MEM */ "Unicast WRED Color drop counter ,and\nUnicast/Multicast Color drop counter.\n0x0 - 0x41 : Port0 - Port65 Unicast WRED Red Color drop count\n0x42 - 0x83 : Port0 - Port65 Unicast WRED Yellow Color drop count\n0x84 - 0xC5 : Port0 - Port65 Unicast WRED Greeen Color drop count\n0xC6 - 0x107: Port0 - Port65 Red Color drop count\n0x108 - 0x149: Port0 - Port65 Yellow Color drop count\n--\n|0x0\n| Unicast WRED Red Drop CNT\n|\n--\n|0x42\n| Unicast WRED Yellow Drop CNT\n|\n-\n|0x84\n| Unicast WRED Gre ...", 10089 /* MMU_CTR_COLOR_DROP_MEM_XPE0 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port64 - Port97 Unicast WRED Red Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x66 - 0x87 : Port64 - Port97 Unicast WRED Yellow Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Unicast WRED Green Color drop count\n 0xAA - 0xCB : Port64 - Port97 Unicast ...", 10090 /* MMU_CTR_COLOR_DROP_MEM_XPE1 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port64 - Port97 Unicast WRED Red Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x66 - 0x87 : Port64 - Port97 Unicast WRED Yellow Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Unicast WRED Green Color drop count\n 0xAA - 0xCB : Port64 - Port97 Unicast ...", 10091 /* MMU_CTR_COLOR_DROP_MEM_XPE2 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port64 - Port97 Unicast WRED Red Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x66 - 0x87 : Port64 - Port97 Unicast WRED Yellow Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Unicast WRED Green Color drop count\n 0xAA - 0xCB : Port64 - Port97 Unicast ...", 10092 /* MMU_CTR_COLOR_DROP_MEM_XPE3 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port64 - Port97 Unicast WRED Red Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x66 - 0x87 : Port64 - Port97 Unicast WRED Yellow Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Unicast WRED Green Color drop count\n 0xAA - 0xCB : Port64 - Port97 Unicast ...", 10093 /* MMU_CTR_COLOR_DROP_MEM_XPE0_PIPE0 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10094 /* MMU_CTR_COLOR_DROP_MEM_XPE0_PIPE1 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10095 /* MMU_CTR_COLOR_DROP_MEM_XPE1_PIPE2 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10096 /* MMU_CTR_COLOR_DROP_MEM_XPE1_PIPE3 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10097 /* MMU_CTR_COLOR_DROP_MEM_XPE2_PIPE0 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10098 /* MMU_CTR_COLOR_DROP_MEM_XPE2_PIPE1 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10099 /* MMU_CTR_COLOR_DROP_MEM_XPE3_PIPE2 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10100 /* MMU_CTR_COLOR_DROP_MEM_XPE3_PIPE3 */ "MMU Color Drop Counter Memory:\nUnicast WRED Color drop counter and Unicast/Multicast Color drop counter.\n 0x0 - 0x21 : Port0 - Port33 Unicast WRED Red Color drop count\n 0x22 - 0x43 : Port0 - Port33 Unicast WRED Yellow Color drop count\n 0x44 - 0x65 : Port0 - Port33 Unicast WRED Green Color drop count\n 0x66 - 0x87 : Port0 - Port33 Red Color drop count\n 0x88 - 0xA9 : Port0 - Port33 Yellow Color drop count", 10101 /* MMU_CTR_ING_DROP_MEM */ "Per ingress port drop counter, due to THDI drop.\nentries 0 - 52 : PIPEx Ingress port 0 - 52\nentries 64 - 116 : PIPEy Ingress port 64 - 116", 10102 /* MMU_CTR_ING_DROP_MEM_XPE0_PIPE0 */ "Per ingress port drop counter, due to THDI drop. (XPE0)\n Entries 0 - 33 : XPE 0 PIPE 0 Ingress port 0 - 33", 10103 /* MMU_CTR_ING_DROP_MEM_XPE0_PIPE1 */ "Per ingress port drop counter, due to THDI drop.\n Entries 0 - 65 : Ingress PIPE port 0 - 65", 10104 /* MMU_CTR_ING_DROP_MEM_XPE0_PIPE3 */ "Per ingress port drop counter, due to THDI drop. (XPE0)\n Entries 0 - 33 : XPE 0 PIPE 3 Ingress port 0 - 33", 10105 /* MMU_CTR_ING_DROP_MEM_XPE1_PIPE0 */ "Per ingress port drop counter, due to THDI drop. (XPE1)\n Entries 0 - 33 : XPE 1 PIPE 0 Ingress port 0 - 33", 10106 /* MMU_CTR_ING_DROP_MEM_XPE1_PIPE3 */ "Per ingress port drop counter, due to THDI drop. (XPE1)\n Entries 0 - 33 : XPE 1 PIPE 3 Ingress port 0 - 33", 10107 /* MMU_CTR_ING_DROP_MEM_XPE2_PIPE1 */ "Per ingress port drop counter, due to THDI drop. (XPE2)\n Entries 0 - 33 : XPE 2 PIPE 1 Ingress port 0 - 33", 10108 /* MMU_CTR_ING_DROP_MEM_XPE2_PIPE2 */ "Per ingress port drop counter, due to THDI drop. (XPE2)\n Entries 0 - 33 : XPE 2 PIPE 2 Ingress port 0 - 33", 10109 /* MMU_CTR_ING_DROP_MEM_XPE3_PIPE1 */ "Per ingress port drop counter, due to THDI drop. (XPE3)\n Entries 0 - 33 : XPE 3 PIPE 1 Ingress port 0 - 33", 10110 /* MMU_CTR_ING_DROP_MEM_XPE3_PIPE2 */ "Per ingress port drop counter, due to THDI drop. (XPE3)\n Entries 0 - 33 : XPE 3 PIPE 2 Ingress port 0 - 33", 10111 /* MMU_CTR_MC_DROP_MEM */ "Unicast drop counter mmeory.\nPORT0 - has 48 entries, map to CPU_COS0 - CPU_COS47\nPORT1 - PORT65 have 5 entries per port: 0-4 map to COS0-COS4;\nPort0: 0x0 <= addr <= 0x2F 48 entries\nPort1: 0x30 <= addr <= 0x34 10 entries\nPort2: 0x35 <= addr <= 0x39 10 entries\n... 10 entries\nport65: 0x170 <= addr <= 0x174 10 entries", 10112 /* MMU_CTR_MC_DROP_MEM0 */ "Multicast drop counter mmeory for PIPEx.\nPORT0 - PORT51 : 10 entries each port: 0 - 519\nPORT52 (CPU Port): 48 entries : 520-567", 10113 /* MMU_CTR_MC_DROP_MEM1 */ "Multicast drop counter mmeory for PIPEx.\nPORT64 - PORT115 : 10 entries per port : 0 - 519\nport116 (loopback port) : 8 entries : 520 - 527", 10114 /* MMU_CTR_MC_DROP_MEM_XPE0_PIPE0 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10115 /* MMU_CTR_MC_DROP_MEM_XPE0_PIPE1 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10116 /* MMU_CTR_MC_DROP_MEM_XPE1_PIPE2 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10117 /* MMU_CTR_MC_DROP_MEM_XPE1_PIPE3 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10118 /* MMU_CTR_MC_DROP_MEM_XPE2_PIPE0 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10119 /* MMU_CTR_MC_DROP_MEM_XPE2_PIPE1 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10120 /* MMU_CTR_MC_DROP_MEM_XPE3_PIPE2 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10121 /* MMU_CTR_MC_DROP_MEM_XPE3_PIPE3 */ "MMU Multicast Counter Drop Memory:\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (LBP): 10 entries : 320 - 329\n PORT33 (CPU Port): 48 entries : 330-377", 10122 /* MMU_CTR_MTRI_DROP_MEM */ "Per ingress port drop counter, due to MTRI drop ONLY.\nentries 0 - 52 : PIPEx Ingress port 0 - 52\nentries 64 - 116 : PIPEy Ingress port 64 - 116", 10123 /* MMU_CTR_UC_DROP_MEM */ "Unicast drop counter mmeory.\nDrop Counters for MMU PORT1 - PORT32,PORT34 - PORT65.\nDrop Counters for CPU & LBP port are in \"MMU_CTR_MC_DROP_MEM\"\nPORT1 - PORT4 have 74 entries per port: 64-73 map to COS0-COS9, 0-63 map to VOQ 64-127\nPORT34 - PORT37 have 74 entries per port: 64-73 map to COS0-COS9, 0-63 map to VOQ 64-127\nPORT5 - PORT32 have 10 entries per port: 0-9 map to COS0-COS9.\nPORT38 - PORT65 have 10 entries per port: 0-9 map to COS0-COS9.\nPort1: 0x0 <= addr <= 0x49 74 entries\nPort2 ...", 10124 /* MMU_CTR_UC_DROP_MEM_XPE0_PIPE0 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10125 /* MMU_CTR_UC_DROP_MEM_XPE0_PIPE1 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10126 /* MMU_CTR_UC_DROP_MEM_XPE1_PIPE2 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10127 /* MMU_CTR_UC_DROP_MEM_XPE1_PIPE3 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10128 /* MMU_CTR_UC_DROP_MEM_XPE2_PIPE0 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10129 /* MMU_CTR_UC_DROP_MEM_XPE2_PIPE1 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10130 /* MMU_CTR_UC_DROP_MEM_XPE3_PIPE2 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10131 /* MMU_CTR_UC_DROP_MEM_XPE3_PIPE3 */ "MMU Unicast Counter Drop Memory\n PORT0 - PORT31 : 10 entries each port: 0 - 319\n PORT32 (MANAGEMENT): 10 entries : 320 - 329", 10132 /* MMU_CTR_WRED_DROP_MEM */ "MMU WRED Drop Memory", 10133 /* MMU_CTR_WRED_DROP_MEM_XPE0_PIPE0 */ "MMU WRED Drop Memory", 10134 /* MMU_CTR_WRED_DROP_MEM_XPE0_PIPE1 */ "MMU WRED Drop Memory", 10135 /* MMU_CTR_WRED_DROP_MEM_XPE1_PIPE2 */ "MMU WRED Drop Memory", 10136 /* MMU_CTR_WRED_DROP_MEM_XPE1_PIPE3 */ "MMU WRED Drop Memory", 10137 /* MMU_CTR_WRED_DROP_MEM_XPE2_PIPE0 */ "MMU WRED Drop Memory", 10138 /* MMU_CTR_WRED_DROP_MEM_XPE2_PIPE1 */ "MMU WRED Drop Memory", 10139 /* MMU_CTR_WRED_DROP_MEM_XPE3_PIPE2 */ "MMU WRED Drop Memory", 10140 /* MMU_CTR_WRED_DROP_MEM_XPE3_PIPE3 */ "MMU WRED Drop Memory", 10141 /* MMU_DEQ_AGING_MASK_LOOKUP_TABLE_MEM */ "Aging Mask Memory, Address Range 0 to 63, RAM Instance 0", 10142 /* MMU_DEQ_RDE_DESCP_MEM */ "Redirect Descriptor RAM", 10143 /* MMU_DRAM_ADDRESS_SPACE */ "Data written to /read from the external DRAM.\n Address should be calculated in the following manner:\n row (X bits), column (X bits), dram number (3 bits), bank number (3 bits)\n Address should be calculated in the following manner:\n If DRAM has 8 column bits (256 Columns), mapping is:\n row 13:0,column7:4,dram_i/f2:0,bank2:0\n If DRAM has 9 column bits (512 Columns), mapping is:\n ...", 10144 /* MMU_EBCFG_MEM_FAIL_ADDR_64 */ "Memory ECC/Parity Failure info FIFO", 10145 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE0 */ "Memory ECC/Parity Failure info FIFO", 10146 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE1 */ "Memory ECC/Parity Failure info FIFO", 10147 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE2 */ "Memory ECC/Parity Failure info FIFO", 10148 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE3 */ "Memory ECC/Parity Failure info FIFO", 10149 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE4 */ "Memory ECC/Parity Failure info FIFO", 10150 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE5 */ "Memory ECC/Parity Failure info FIFO", 10151 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE6 */ "Memory ECC/Parity Failure info FIFO", 10152 /* MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE7 */ "Memory ECC/Parity Failure info FIFO", 10153 /* MMU_EBCFP_FAP_BITMAP_MEM */ "FAP-IP Bitmap memory to store mapping information.", 10154 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE0 */ "FAP-IP Bitmap memory to store mapping information.", 10155 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE1 */ "FAP-IP Bitmap memory to store mapping information.", 10156 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE2 */ "FAP-IP Bitmap memory to store mapping information.", 10157 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE3 */ "FAP-IP Bitmap memory to store mapping information.", 10158 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE4 */ "FAP-IP Bitmap memory to store mapping information.", 10159 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE5 */ "FAP-IP Bitmap memory to store mapping information.", 10160 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE6 */ "FAP-IP Bitmap memory to store mapping information.", 10161 /* MMU_EBCFP_FAP_BITMAP_MEM_PIPE7 */ "FAP-IP Bitmap memory to store mapping information.", 10162 /* MMU_EBCFP_LAT_ABS_FIFO */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10163 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE0 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10164 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE1 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10165 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE2 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10166 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE3 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10167 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE4 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10168 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE5 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10169 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE6 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10170 /* MMU_EBCFP_LAT_ABS_FIFO_PIPE7 */ "Latency Absorption FIFO to match the latency between cell-data and cell-control paths to EBMB.", 10171 /* MMU_EBCFP_MXM_TAG_MEM */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10172 /* MMU_EBCFP_MXM_TAG_MEM_PIPE0 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10173 /* MMU_EBCFP_MXM_TAG_MEM_PIPE1 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10174 /* MMU_EBCFP_MXM_TAG_MEM_PIPE2 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10175 /* MMU_EBCFP_MXM_TAG_MEM_PIPE3 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10176 /* MMU_EBCFP_MXM_TAG_MEM_PIPE4 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10177 /* MMU_EBCFP_MXM_TAG_MEM_PIPE5 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10178 /* MMU_EBCFP_MXM_TAG_MEM_PIPE6 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10179 /* MMU_EBCFP_MXM_TAG_MEM_PIPE7 */ "Stores tag information associated with each EBMB pointer.\nSoftware task:\nAfter hardware memory initialization, Write 1 to address 0.", 10180 /* MMU_EBCR_CELL_INFO_TILE0 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10181 /* MMU_EBCR_CELL_INFO_TILE1 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10182 /* MMU_EBCR_CELL_INFO_TILE0_PIPE0 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10183 /* MMU_EBCR_CELL_INFO_TILE0_PIPE1 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10184 /* MMU_EBCR_CELL_INFO_TILE0_PIPE2 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10185 /* MMU_EBCR_CELL_INFO_TILE0_PIPE3 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10186 /* MMU_EBCR_CELL_INFO_TILE0_PIPE4 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10187 /* MMU_EBCR_CELL_INFO_TILE0_PIPE5 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10188 /* MMU_EBCR_CELL_INFO_TILE0_PIPE6 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10189 /* MMU_EBCR_CELL_INFO_TILE0_PIPE7 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10190 /* MMU_EBCR_CELL_INFO_TILE1_PIPE0 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10191 /* MMU_EBCR_CELL_INFO_TILE1_PIPE1 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10192 /* MMU_EBCR_CELL_INFO_TILE1_PIPE2 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10193 /* MMU_EBCR_CELL_INFO_TILE1_PIPE3 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10194 /* MMU_EBCR_CELL_INFO_TILE1_PIPE4 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10195 /* MMU_EBCR_CELL_INFO_TILE1_PIPE5 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10196 /* MMU_EBCR_CELL_INFO_TILE1_PIPE6 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10197 /* MMU_EBCR_CELL_INFO_TILE1_PIPE7 */ "Stores the Cell pointer and control information for SAF cells received by EBCR", 10198 /* MMU_EBMB_CCBE_SER */ "Used for SER event reporting for CCBE slice reads", 10199 /* MMU_EBMB_CCBE_SER_PIPE0 */ "Used for SER event reporting for CCBE slice reads", 10200 /* MMU_EBMB_CCBE_SER_PIPE1 */ "Used for SER event reporting for CCBE slice reads", 10201 /* MMU_EBMB_CCBE_SER_PIPE2 */ "Used for SER event reporting for CCBE slice reads", 10202 /* MMU_EBMB_CCBE_SER_PIPE3 */ "Used for SER event reporting for CCBE slice reads", 10203 /* MMU_EBMB_CCBE_SER_PIPE4 */ "Used for SER event reporting for CCBE slice reads", 10204 /* MMU_EBMB_CCBE_SER_PIPE5 */ "Used for SER event reporting for CCBE slice reads", 10205 /* MMU_EBMB_CCBE_SER_PIPE6 */ "Used for SER event reporting for CCBE slice reads", 10206 /* MMU_EBMB_CCBE_SER_PIPE7 */ "Used for SER event reporting for CCBE slice reads", 10207 /* MMU_EBMB_CCBE_SLICE */ "Egress Buffer CCBE slice memory", 10208 /* MMU_EBMB_CCBE_SLICE_CPU */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10209 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE0 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10210 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE1 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10211 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE2 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10212 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE3 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10213 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE4 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10214 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE5 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10215 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE6 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10216 /* MMU_EBMB_CCBE_SLICE_CPU_PIPE7 */ "Address space used for CPU access to CCBE memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10217 /* MMU_EBMB_CCBE_SLICE_PIPE0 */ "Egress Buffer CCBE slice memory", 10218 /* MMU_EBMB_CCBE_SLICE_PIPE1 */ "Egress Buffer CCBE slice memory", 10219 /* MMU_EBMB_CCBE_SLICE_PIPE2 */ "Egress Buffer CCBE slice memory", 10220 /* MMU_EBMB_CCBE_SLICE_PIPE3 */ "Egress Buffer CCBE slice memory", 10221 /* MMU_EBMB_CCBE_SLICE_PIPE4 */ "Egress Buffer CCBE slice memory", 10222 /* MMU_EBMB_CCBE_SLICE_PIPE5 */ "Egress Buffer CCBE slice memory", 10223 /* MMU_EBMB_CCBE_SLICE_PIPE6 */ "Egress Buffer CCBE slice memory", 10224 /* MMU_EBMB_CCBE_SLICE_PIPE7 */ "Egress Buffer CCBE slice memory", 10225 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10226 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE0 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10227 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE1 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10228 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE2 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10229 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE3 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10230 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE4 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10231 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE5 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10232 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE6 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10233 /* MMU_EBMB_PAYLOAD_ITM0_CH0_SER_PIPE7 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel0", 10234 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10235 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE0 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10236 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE1 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10237 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE2 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10238 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE3 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10239 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE4 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10240 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE5 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10241 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE6 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10242 /* MMU_EBMB_PAYLOAD_ITM0_CH1_SER_PIPE7 */ "Used for SER event reporting for PAYLOAD cells comming from ITM0, Channel1", 10243 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10244 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE0 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10245 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE1 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10246 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE2 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10247 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE3 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10248 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE4 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10249 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE5 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10250 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE6 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10251 /* MMU_EBMB_PAYLOAD_ITM1_CH0_SER_PIPE7 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel0", 10252 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10253 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE0 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10254 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE1 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10255 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE2 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10256 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE3 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10257 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE4 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10258 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE5 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10259 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE6 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10260 /* MMU_EBMB_PAYLOAD_ITM1_CH1_SER_PIPE7 */ "Used for SER event reporting for PAYLOAD cells comming from ITM1, Channel1", 10261 /* MMU_EBMB_PAYLOAD_SLICE */ "Egress Buffer payload slice memory", 10262 /* MMU_EBMB_PAYLOAD_SLICE0_CPU */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10263 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10264 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10265 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10266 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10267 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10268 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10269 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10270 /* MMU_EBMB_PAYLOAD_SLICE0_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice0 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10271 /* MMU_EBMB_PAYLOAD_SLICE1_CPU */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10272 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10273 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10274 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10275 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10276 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10277 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10278 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10279 /* MMU_EBMB_PAYLOAD_SLICE1_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice1 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10280 /* MMU_EBMB_PAYLOAD_SLICE2_CPU */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10281 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10282 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10283 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10284 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10285 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10286 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10287 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10288 /* MMU_EBMB_PAYLOAD_SLICE2_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice2 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10289 /* MMU_EBMB_PAYLOAD_SLICE3_CPU */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10290 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10291 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10292 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10293 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10294 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10295 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10296 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10297 /* MMU_EBMB_PAYLOAD_SLICE3_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice3 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10298 /* MMU_EBMB_PAYLOAD_SLICE4_CPU */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10299 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10300 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10301 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10302 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10303 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10304 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10305 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10306 /* MMU_EBMB_PAYLOAD_SLICE4_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice4 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10307 /* MMU_EBMB_PAYLOAD_SLICE5_CPU */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10308 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10309 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10310 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10311 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10312 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10313 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10314 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10315 /* MMU_EBMB_PAYLOAD_SLICE5_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice5 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10316 /* MMU_EBMB_PAYLOAD_SLICE6_CPU */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10317 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10318 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10319 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10320 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10321 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10322 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10323 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10324 /* MMU_EBMB_PAYLOAD_SLICE6_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice6 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10325 /* MMU_EBMB_PAYLOAD_SLICE7_CPU */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10326 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE0 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10327 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE1 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10328 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE2 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10329 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE3 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10330 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE4 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10331 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE5 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10332 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE6 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10333 /* MMU_EBMB_PAYLOAD_SLICE7_CPU_PIPE7 */ "Address space used for CPU access to Payload Slice7 Memories. CPU access is not possible during traffic. In addition, Null slot timer has to be disable by writing 0 to MMU_EBPTS_CBMG_VALUE before accessing EBMB memories", 10334 /* MMU_EBMB_PAYLOAD_SLICE_PIPE0 */ "Egress Buffer payload slice memory", 10335 /* MMU_EBMB_PAYLOAD_SLICE_PIPE1 */ "Egress Buffer payload slice memory", 10336 /* MMU_EBMB_PAYLOAD_SLICE_PIPE2 */ "Egress Buffer payload slice memory", 10337 /* MMU_EBMB_PAYLOAD_SLICE_PIPE3 */ "Egress Buffer payload slice memory", 10338 /* MMU_EBMB_PAYLOAD_SLICE_PIPE4 */ "Egress Buffer payload slice memory", 10339 /* MMU_EBMB_PAYLOAD_SLICE_PIPE5 */ "Egress Buffer payload slice memory", 10340 /* MMU_EBMB_PAYLOAD_SLICE_PIPE6 */ "Egress Buffer payload slice memory", 10341 /* MMU_EBMB_PAYLOAD_SLICE_PIPE7 */ "Egress Buffer payload slice memory", 10342 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO */ "Shape bus Latency FIFO.", 10343 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE0 */ "Shape bus Latency FIFO.", 10344 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE1 */ "Shape bus Latency FIFO.", 10345 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE2 */ "Shape bus Latency FIFO.", 10346 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE3 */ "Shape bus Latency FIFO.", 10347 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE4 */ "Shape bus Latency FIFO.", 10348 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE5 */ "Shape bus Latency FIFO.", 10349 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE6 */ "Shape bus Latency FIFO.", 10350 /* MMU_EBPTS_EBSHP_SHAPE_BUS_LATENCY_FIFO_PIPE7 */ "Shape bus Latency FIFO.", 10351 /* MMU_EBTOQ_CB */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10352 /* MMU_EBTOQ_CBN */ "Cell block next memory.Each address covers block of 4 CB address.", 10353 /* MMU_EBTOQ_CBN_PIPE0 */ "Cell block next memory.Each address covers block of 4 CB address.", 10354 /* MMU_EBTOQ_CBN_PIPE1 */ "Cell block next memory.Each address covers block of 4 CB address.", 10355 /* MMU_EBTOQ_CBN_PIPE2 */ "Cell block next memory.Each address covers block of 4 CB address.", 10356 /* MMU_EBTOQ_CBN_PIPE3 */ "Cell block next memory.Each address covers block of 4 CB address.", 10357 /* MMU_EBTOQ_CBN_PIPE4 */ "Cell block next memory.Each address covers block of 4 CB address.", 10358 /* MMU_EBTOQ_CBN_PIPE5 */ "Cell block next memory.Each address covers block of 4 CB address.", 10359 /* MMU_EBTOQ_CBN_PIPE6 */ "Cell block next memory.Each address covers block of 4 CB address.", 10360 /* MMU_EBTOQ_CBN_PIPE7 */ "Cell block next memory.Each address covers block of 4 CB address.", 10361 /* MMU_EBTOQ_CB_PIPE0 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10362 /* MMU_EBTOQ_CB_PIPE1 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10363 /* MMU_EBTOQ_CB_PIPE2 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10364 /* MMU_EBTOQ_CB_PIPE3 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10365 /* MMU_EBTOQ_CB_PIPE4 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10366 /* MMU_EBTOQ_CB_PIPE5 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10367 /* MMU_EBTOQ_CB_PIPE6 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10368 /* MMU_EBTOQ_CB_PIPE7 */ "Cell block memory. Store EBMB cell ptr and encoded cell size", 10369 /* MMU_EBTOQ_CFP */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10370 /* MMU_EBTOQ_CFP_PIPE0 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10371 /* MMU_EBTOQ_CFP_PIPE1 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10372 /* MMU_EBTOQ_CFP_PIPE2 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10373 /* MMU_EBTOQ_CFP_PIPE3 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10374 /* MMU_EBTOQ_CFP_PIPE4 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10375 /* MMU_EBTOQ_CFP_PIPE5 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10376 /* MMU_EBTOQ_CFP_PIPE6 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10377 /* MMU_EBTOQ_CFP_PIPE7 */ "Cell block free pool memory. provide free ptrs to CBN and QDB memoires.2 CBN ptrs per entry", 10378 /* MMU_EBTOQ_QDB */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10379 /* MMU_EBTOQ_QDB_PIPE0 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10380 /* MMU_EBTOQ_QDB_PIPE1 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10381 /* MMU_EBTOQ_QDB_PIPE2 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10382 /* MMU_EBTOQ_QDB_PIPE3 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10383 /* MMU_EBTOQ_QDB_PIPE4 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10384 /* MMU_EBTOQ_QDB_PIPE5 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10385 /* MMU_EBTOQ_QDB_PIPE6 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10386 /* MMU_EBTOQ_QDB_PIPE7 */ "Virtual EBQueue Database. Store cell link and EOP information per VEBQ", 10387 /* MMU_ENQS_CT_FIFO */ "Per port ASF Cell FIFO", 10388 /* MMU_ENQS_CT_FIFO_PIPE0 */ "Per port ASF Cell FIFO", 10389 /* MMU_ENQS_CT_FIFO_PIPE1 */ "Per port ASF Cell FIFO", 10390 /* MMU_ENQS_CT_FIFO_PIPE2 */ "Per port ASF Cell FIFO", 10391 /* MMU_ENQS_CT_FIFO_PIPE3 */ "Per port ASF Cell FIFO", 10392 /* MMU_ENQS_PBI_DB */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10393 /* MMU_ENQS_PBI_DB_SC0_PIPE0 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10394 /* MMU_ENQS_PBI_DB_SC0_PIPE1 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10395 /* MMU_ENQS_PBI_DB_SC0_PIPE2 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10396 /* MMU_ENQS_PBI_DB_SC0_PIPE3 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10397 /* MMU_ENQS_PBI_DB_SC1_PIPE0 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10398 /* MMU_ENQS_PBI_DB_SC1_PIPE1 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10399 /* MMU_ENQS_PBI_DB_SC1_PIPE2 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10400 /* MMU_ENQS_PBI_DB_SC1_PIPE3 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10401 /* MMU_ENQS_PBI_DB_SED0_PIPE0 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10402 /* MMU_ENQS_PBI_DB_SED0_PIPE1 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10403 /* MMU_ENQS_PBI_DB_SED0_PIPE2 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10404 /* MMU_ENQS_PBI_DB_SED0_PIPE3 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10405 /* MMU_ENQS_PBI_DB_SED1_PIPE0 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10406 /* MMU_ENQS_PBI_DB_SED1_PIPE1 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10407 /* MMU_ENQS_PBI_DB_SED1_PIPE2 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10408 /* MMU_ENQS_PBI_DB_SED1_PIPE3 */ "ENQS memory for storage of PBI information at SOP. This is a working memory maintained by hardware.", 10409 /* MMU_ENQX_EARLY_PIPEMEM_0 */ "Pipeline memory for early stages of ENQX pipeline low word", 10410 /* MMU_ENQX_EARLY_PIPEMEM_1 */ "Pipeline memory for early stages of ENQX pipeline low word", 10411 /* MMU_ENQX_EARLY_PIPEMEM_2 */ "Pipeline memory for early stages of ENQX pipeline low word", 10412 /* MMU_ENQX_EARLY_PIPEMEM_3 */ "Pipeline memory for early stages of ENQX pipeline high word", 10413 /* MMU_ENQX_EARLY_PIPEMEM_0_XPE0_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline low word", 10414 /* MMU_ENQX_EARLY_PIPEMEM_0_XPE0_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline low word", 10415 /* MMU_ENQX_EARLY_PIPEMEM_1_XPE0_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline low word", 10416 /* MMU_ENQX_EARLY_PIPEMEM_1_XPE0_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline low word", 10417 /* MMU_ENQX_EARLY_PIPEMEM_2_XPE0_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline low word", 10418 /* MMU_ENQX_EARLY_PIPEMEM_2_XPE0_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline low word", 10419 /* MMU_ENQX_EARLY_PIPEMEM_3_XPE0_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline high word", 10420 /* MMU_ENQX_EARLY_PIPEMEM_3_XPE0_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline high word", 10421 /* MMU_ENQX_EARLY_PIPEMEM_HI */ "Pipeline memory for early stages of ENQX pipeline high word", 10422 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE0_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline high word", 10423 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE0_PIPE3 */ "Pipeline memory for early stages of ENQX pipeline high word", 10424 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE1_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline high word", 10425 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE1_PIPE3 */ "Pipeline memory for early stages of ENQX pipeline high word", 10426 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE2_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline high word", 10427 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE2_PIPE2 */ "Pipeline memory for early stages of ENQX pipeline high word", 10428 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE3_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline high word", 10429 /* MMU_ENQX_EARLY_PIPEMEM_HI_XPE3_PIPE2 */ "Pipeline memory for early stages of ENQX pipeline high word", 10430 /* MMU_ENQX_EARLY_PIPEMEM_LO */ "Pipeline memory for early stages of ENQX pipeline low word", 10431 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE0_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline low word", 10432 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE0_PIPE3 */ "Pipeline memory for early stages of ENQX pipeline low word", 10433 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE1_PIPE0 */ "Pipeline memory for early stages of ENQX pipeline low word", 10434 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE1_PIPE3 */ "Pipeline memory for early stages of ENQX pipeline low word", 10435 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE2_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline low word", 10436 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE2_PIPE2 */ "Pipeline memory for early stages of ENQX pipeline low word", 10437 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE3_PIPE1 */ "Pipeline memory for early stages of ENQX pipeline low word", 10438 /* MMU_ENQX_EARLY_PIPEMEM_LO_XPE3_PIPE2 */ "Pipeline memory for early stages of ENQX pipeline low word", 10439 /* MMU_ENQX_PIPEMEM_HI */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10440 /* MMU_ENQX_PIPEMEM_HI_XPE0_PIPE0 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10441 /* MMU_ENQX_PIPEMEM_HI_XPE0_PIPE3 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10442 /* MMU_ENQX_PIPEMEM_HI_XPE1_PIPE0 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10443 /* MMU_ENQX_PIPEMEM_HI_XPE1_PIPE3 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10444 /* MMU_ENQX_PIPEMEM_HI_XPE2_PIPE1 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10445 /* MMU_ENQX_PIPEMEM_HI_XPE2_PIPE2 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10446 /* MMU_ENQX_PIPEMEM_HI_XPE3_PIPE1 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10447 /* MMU_ENQX_PIPEMEM_HI_XPE3_PIPE2 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, high word", 10448 /* MMU_ENQX_PIPEMEM_LO */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10449 /* MMU_ENQX_PIPEMEM_LO_XPE0_PIPE0 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10450 /* MMU_ENQX_PIPEMEM_LO_XPE0_PIPE3 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10451 /* MMU_ENQX_PIPEMEM_LO_XPE1_PIPE0 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10452 /* MMU_ENQX_PIPEMEM_LO_XPE1_PIPE3 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10453 /* MMU_ENQX_PIPEMEM_LO_XPE2_PIPE1 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10454 /* MMU_ENQX_PIPEMEM_LO_XPE2_PIPE2 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10455 /* MMU_ENQX_PIPEMEM_LO_XPE3_PIPE1 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10456 /* MMU_ENQX_PIPEMEM_LO_XPE3_PIPE2 */ "Pipeline memory for Packet header and RQE data waiting for remote THDO drop, low word", 10457 /* MMU_ENQ_CBP_32B_WR_STORE_0 */ "Temporary store of SOP/EOP data - CPU readable only", 10458 /* MMU_ENQ_CBP_32B_WR_STORE_1 */ "Temporary store of SOP/EOP data - CPU readable only", 10459 /* MMU_ENQ_CBP_32B_WR_STORE_2 */ "Temporary store of SOP/EOP data - CPU readable only", 10460 /* MMU_ENQ_CFAPI_INTERNAL_RECYCLE */ "Internal Pointer Cache", 10461 /* MMU_ENQ_FAP_BITMAP */ "ENQ FAP BITMAP", 10462 /* MMU_ENQ_FAP_STACK */ "ENQ FAP STACK", 10463 /* MMU_ENQ_PACKING_CTXT_FIFOS_FP_LL */ "ENQ PAcking per Ctxt Reasembly FIFOs Free Pool and Linked List", 10464 /* MMU_ENQ_PBI_DB */ "ENQ memory for storage of PBI information at SOP.", 10465 /* MMU_ENQ_RQE_WR_COMPLETE_0 */ "Write complete information needed for write complete message to TOQ and/or RQE", 10466 /* MMU_ENQ_RQE_WR_COMPLETE_1 */ "Write complete information needed for write complete message to TOQ and/or RQE", 10467 /* MMU_ENQ_RQE_WR_COMPLETE_2 */ "Write complete information needed for write complete message to TOQ and/or RQE", 10468 /* MMU_ENQ_RQE_WR_COMPLETE_3 */ "Write complete information needed for write complete message to TOQ and/or RQE", 10469 /* MMU_ENQ_RQE_WR_COMPLETE_4 */ "Write complete information needed for write complete message to TOQ and/or RQE", 10470 /* MMU_ENQ_RQE_WR_COMPLETE_5 */ "Write complete information needed for write complete message to TOQ and/or RQE", 10471 /* MMU_ENQ_SRC_PORT_STATE_0 */ "ENQ SRC PORT STATE 0", 10472 /* MMU_ENQ_SRC_PORT_STATE_1 */ "ENQ SRC PORT STATE 1", 10473 /* MMU_ENQ_SRC_PORT_STATE_2 */ "ENQ SRC PORT STATE 2", 10474 /* MMU_ENQ_SRC_PPP_TO_S1_LOOKUP */ "MPB.SRC_PPP to Destination Channel lookup for COE Pause Frames", 10475 /* MMU_EPRG_MEM */ "Egress purge queue memory", 10476 /* MMU_EPRG_MEM_XPE0 */ "Egress purge queue memory", 10477 /* MMU_EPRG_MEM_XPE1 */ "Egress purge queue memory", 10478 /* MMU_EPRG_MEM_XPE2 */ "Egress purge queue memory", 10479 /* MMU_EPRG_MEM_XPE3 */ "Egress purge queue memory", 10480 /* MMU_EXT_MC_GROUP_MAP */ "Extended MC group mapping table", 10481 /* MMU_EXT_MC_QUEUE_LIST0 */ "Extended MC group mapping table", 10482 /* MMU_EXT_MC_QUEUE_LIST1 */ "Extended MC group mapping table", 10483 /* MMU_EXT_MC_QUEUE_LIST4 */ "Extended MC group mapping table", 10484 /* MMU_FDF */ "FDF Indirect Mechanism.", 10485 /* MMU_GATE_CTL_TBL0_P2 */ "TAS control list table", 10486 /* MMU_GATE_CTL_TBL0_P3 */ "TAS control list table", 10487 /* MMU_GATE_CTL_TBL0_P4 */ "TAS control list table", 10488 /* MMU_GATE_CTL_TBL0_P5 */ "TAS control list table", 10489 /* MMU_GATE_CTL_TBL0_P6 */ "TAS control list table", 10490 /* MMU_GATE_CTL_TBL0_P7 */ "TAS control list table", 10491 /* MMU_GATE_CTL_TBL0_P8 */ "TAS control list table", 10492 /* MMU_GATE_CTL_TBL0_P9 */ "TAS control list table", 10493 /* MMU_GATE_CTL_TBL0_P10 */ "TAS control list table", 10494 /* MMU_GATE_CTL_TBL0_P11 */ "TAS control list table", 10495 /* MMU_GATE_CTL_TBL0_P12 */ "TAS control list table", 10496 /* MMU_GATE_CTL_TBL0_P13 */ "TAS control list table", 10497 /* MMU_GATE_CTL_TBL0_P14 */ "TAS control list table", 10498 /* MMU_GATE_CTL_TBL0_P15 */ "TAS control list table", 10499 /* MMU_GATE_CTL_TBL0_P16 */ "TAS control list table", 10500 /* MMU_GATE_CTL_TBL0_P17 */ "TAS control list table", 10501 /* MMU_GATE_CTL_TBL0_P18 */ "TAS control list table", 10502 /* MMU_GATE_CTL_TBL0_P19 */ "TAS control list table", 10503 /* MMU_GATE_CTL_TBL0_P20 */ "TAS control list table", 10504 /* MMU_GATE_CTL_TBL0_P21 */ "TAS control list table", 10505 /* MMU_GATE_CTL_TBL0_P22 */ "TAS control list table", 10506 /* MMU_GATE_CTL_TBL0_P23 */ "TAS control list table", 10507 /* MMU_GATE_CTL_TBL0_P24 */ "TAS control list table", 10508 /* MMU_GATE_CTL_TBL0_P25 */ "TAS control list table", 10509 /* MMU_GATE_CTL_TBL0_P26 */ "TAS control list table", 10510 /* MMU_GATE_CTL_TBL0_P27 */ "TAS control list table", 10511 /* MMU_GATE_CTL_TBL0_P28 */ "TAS control list table", 10512 /* MMU_GATE_CTL_TBL0_P29 */ "TAS control list table", 10513 /* MMU_GATE_CTL_TBL0_P30 */ "TAS control list table", 10514 /* MMU_GATE_CTL_TBL0_P31 */ "TAS control list table", 10515 /* MMU_GATE_CTL_TBL0_P32 */ "TAS control list table", 10516 /* MMU_GATE_CTL_TBL0_P33 */ "TAS control list table", 10517 /* MMU_GATE_CTL_TBL0_P34 */ "TAS control list table", 10518 /* MMU_GATE_CTL_TBL0_P35 */ "TAS control list table", 10519 /* MMU_GATE_CTL_TBL0_P36 */ "TAS control list table", 10520 /* MMU_GATE_CTL_TBL0_P37 */ "TAS control list table", 10521 /* MMU_GATE_CTL_TBL0_P38 */ "TAS control list table", 10522 /* MMU_GATE_CTL_TBL0_P39 */ "TAS control list table", 10523 /* MMU_GATE_CTL_TBL0_P40 */ "TAS control list table", 10524 /* MMU_GATE_CTL_TBL0_P41 */ "TAS control list table", 10525 /* MMU_GATE_CTL_TBL0_P42 */ "TAS control list table", 10526 /* MMU_GATE_CTL_TBL0_P43 */ "TAS control list table", 10527 /* MMU_GATE_CTL_TBL0_P44 */ "TAS control list table", 10528 /* MMU_GATE_CTL_TBL0_P45 */ "TAS control list table", 10529 /* MMU_GATE_CTL_TBL0_P46 */ "TAS control list table", 10530 /* MMU_GATE_CTL_TBL0_P47 */ "TAS control list table", 10531 /* MMU_GATE_CTL_TBL0_P48 */ "TAS control list table", 10532 /* MMU_GATE_CTL_TBL0_P49 */ "TAS control list table", 10533 /* MMU_GATE_CTL_TBL0_P50 */ "TAS control list table", 10534 /* MMU_GATE_CTL_TBL0_P51 */ "TAS control list table", 10535 /* MMU_GATE_CTL_TBL0_P52 */ "TAS control list table", 10536 /* MMU_GATE_CTL_TBL0_P53 */ "TAS control list table", 10537 /* MMU_GATE_CTL_TBL0_P54 */ "TAS control list table", 10538 /* MMU_GATE_CTL_TBL0_P55 */ "TAS control list table", 10539 /* MMU_GATE_CTL_TBL0_P56 */ "TAS control list table", 10540 /* MMU_GATE_CTL_TBL0_P57 */ "TAS control list table", 10541 /* MMU_GATE_CTL_TBL0_P58 */ "TAS control list table", 10542 /* MMU_GATE_CTL_TBL0_P59 */ "TAS control list table", 10543 /* MMU_GATE_CTL_TBL0_P60 */ "TAS control list table", 10544 /* MMU_GATE_CTL_TBL0_P61 */ "TAS control list table", 10545 /* MMU_GATE_CTL_TBL0_P62 */ "TAS control list table", 10546 /* MMU_GATE_CTL_TBL0_P63 */ "TAS control list table", 10547 /* MMU_GATE_CTL_TBL0_P64 */ "TAS control list table", 10548 /* MMU_GATE_CTL_TBL0_P65 */ "TAS control list table", 10549 /* MMU_GATE_CTL_TBL1_P2 */ "TAS control list table", 10550 /* MMU_GATE_CTL_TBL1_P3 */ "TAS control list table", 10551 /* MMU_GATE_CTL_TBL1_P4 */ "TAS control list table", 10552 /* MMU_GATE_CTL_TBL1_P5 */ "TAS control list table", 10553 /* MMU_GATE_CTL_TBL1_P6 */ "TAS control list table", 10554 /* MMU_GATE_CTL_TBL1_P7 */ "TAS control list table", 10555 /* MMU_GATE_CTL_TBL1_P8 */ "TAS control list table", 10556 /* MMU_GATE_CTL_TBL1_P9 */ "TAS control list table", 10557 /* MMU_GATE_CTL_TBL1_P10 */ "TAS control list table", 10558 /* MMU_GATE_CTL_TBL1_P11 */ "TAS control list table", 10559 /* MMU_GATE_CTL_TBL1_P12 */ "TAS control list table", 10560 /* MMU_GATE_CTL_TBL1_P13 */ "TAS control list table", 10561 /* MMU_GATE_CTL_TBL1_P14 */ "TAS control list table", 10562 /* MMU_GATE_CTL_TBL1_P15 */ "TAS control list table", 10563 /* MMU_GATE_CTL_TBL1_P16 */ "TAS control list table", 10564 /* MMU_GATE_CTL_TBL1_P17 */ "TAS control list table", 10565 /* MMU_GATE_CTL_TBL1_P18 */ "TAS control list table", 10566 /* MMU_GATE_CTL_TBL1_P19 */ "TAS control list table", 10567 /* MMU_GATE_CTL_TBL1_P20 */ "TAS control list table", 10568 /* MMU_GATE_CTL_TBL1_P21 */ "TAS control list table", 10569 /* MMU_GATE_CTL_TBL1_P22 */ "TAS control list table", 10570 /* MMU_GATE_CTL_TBL1_P23 */ "TAS control list table", 10571 /* MMU_GATE_CTL_TBL1_P24 */ "TAS control list table", 10572 /* MMU_GATE_CTL_TBL1_P25 */ "TAS control list table", 10573 /* MMU_GATE_CTL_TBL1_P26 */ "TAS control list table", 10574 /* MMU_GATE_CTL_TBL1_P27 */ "TAS control list table", 10575 /* MMU_GATE_CTL_TBL1_P28 */ "TAS control list table", 10576 /* MMU_GATE_CTL_TBL1_P29 */ "TAS control list table", 10577 /* MMU_GATE_CTL_TBL1_P30 */ "TAS control list table", 10578 /* MMU_GATE_CTL_TBL1_P31 */ "TAS control list table", 10579 /* MMU_GATE_CTL_TBL1_P32 */ "TAS control list table", 10580 /* MMU_GATE_CTL_TBL1_P33 */ "TAS control list table", 10581 /* MMU_GATE_CTL_TBL1_P34 */ "TAS control list table", 10582 /* MMU_GATE_CTL_TBL1_P35 */ "TAS control list table", 10583 /* MMU_GATE_CTL_TBL1_P36 */ "TAS control list table", 10584 /* MMU_GATE_CTL_TBL1_P37 */ "TAS control list table", 10585 /* MMU_GATE_CTL_TBL1_P38 */ "TAS control list table", 10586 /* MMU_GATE_CTL_TBL1_P39 */ "TAS control list table", 10587 /* MMU_GATE_CTL_TBL1_P40 */ "TAS control list table", 10588 /* MMU_GATE_CTL_TBL1_P41 */ "TAS control list table", 10589 /* MMU_GATE_CTL_TBL1_P42 */ "TAS control list table", 10590 /* MMU_GATE_CTL_TBL1_P43 */ "TAS control list table", 10591 /* MMU_GATE_CTL_TBL1_P44 */ "TAS control list table", 10592 /* MMU_GATE_CTL_TBL1_P45 */ "TAS control list table", 10593 /* MMU_GATE_CTL_TBL1_P46 */ "TAS control list table", 10594 /* MMU_GATE_CTL_TBL1_P47 */ "TAS control list table", 10595 /* MMU_GATE_CTL_TBL1_P48 */ "TAS control list table", 10596 /* MMU_GATE_CTL_TBL1_P49 */ "TAS control list table", 10597 /* MMU_GATE_CTL_TBL1_P50 */ "TAS control list table", 10598 /* MMU_GATE_CTL_TBL1_P51 */ "TAS control list table", 10599 /* MMU_GATE_CTL_TBL1_P52 */ "TAS control list table", 10600 /* MMU_GATE_CTL_TBL1_P53 */ "TAS control list table", 10601 /* MMU_GATE_CTL_TBL1_P54 */ "TAS control list table", 10602 /* MMU_GATE_CTL_TBL1_P55 */ "TAS control list table", 10603 /* MMU_GATE_CTL_TBL1_P56 */ "TAS control list table", 10604 /* MMU_GATE_CTL_TBL1_P57 */ "TAS control list table", 10605 /* MMU_GATE_CTL_TBL1_P58 */ "TAS control list table", 10606 /* MMU_GATE_CTL_TBL1_P59 */ "TAS control list table", 10607 /* MMU_GATE_CTL_TBL1_P60 */ "TAS control list table", 10608 /* MMU_GATE_CTL_TBL1_P61 */ "TAS control list table", 10609 /* MMU_GATE_CTL_TBL1_P62 */ "TAS control list table", 10610 /* MMU_GATE_CTL_TBL1_P63 */ "TAS control list table", 10611 /* MMU_GATE_CTL_TBL1_P64 */ "TAS control list table", 10612 /* MMU_GATE_CTL_TBL1_P65 */ "TAS control list table", 10613 /* MMU_GCFG_MEM_FAIL_ADDR_64 */ "Memory Fail address FIFO", 10614 /* MMU_GLBCFG_MEM_FAIL_ADDR_64 */ "Memory ECC/Parity Failure info FIFO", 10615 /* MMU_GLBCFG_TOD_TIMESTAMP */ "Time of Day values to be stored by host process for MMU Packet stats UTC conversion from local 1588 timestamp", 10616 /* MMU_IDF */ "IDF Indirect Mechanism.", 10617 /* MMU_IDR_RXI_MEM_DATA */ "Fifo that hold the data received from IDR", 10618 /* MMU_INITIAL_NHOP_TBL */ "MMU_INITIAL_NHOP_TBL arranged as 4 entries per 1 word indexed by L3_REPL_PTR0[12:2]", 10619 /* MMU_INTFI_BASE_INDEX_TBL */ "Base Index Table in Mapping and Storage", 10620 /* MMU_INTFI_BASE_TBL */ "Flow Control Base Table", 10621 /* MMU_INTFI_DEBUG_MEM */ "Flow Control Debug Memory", 10622 /* MMU_INTFI_FC_MAP_TBL0 */ "FC Map Table for Level 0 in Mapping and Storage", 10623 /* MMU_INTFI_FC_MAP_TBL1 */ "FC Map Table for Level 1 in Mapping and Storage", 10624 /* MMU_INTFI_FC_MAP_TBL2 */ "FC Map Table for Level 2 in Mapping and Storage", 10625 /* MMU_INTFI_FC_STATE_TBL */ "Flow Control State Table", 10626 /* MMU_INTFI_FC_ST_TBL0 */ "FC State Table for Level 0 in Mapping and Storage", 10627 /* MMU_INTFI_FC_ST_TBL1 */ "FC State Table for Level 1 in Mapping and Storage", 10628 /* MMU_INTFI_FC_ST_TBL2 */ "FC State Table for Level 2 in Mapping and Storage", 10629 /* MMU_INTFI_MAP_TBL */ "Flow Control Map Table", 10630 /* MMU_INTFI_MERGE_ST_TBL */ "Merge State Table in DMVOQ merge block maintained by hardware", 10631 /* MMU_INTFI_OFFSET_MAP_TBL */ "Offset Map Table in DMVOQ merge block", 10632 /* MMU_INTFI_PFC_ST_TBL */ "PFC State Table in Mapping and Storage", 10633 /* MMU_INTFI_PORT_COEFC_TB */ "COE-FC PORT STATE Table", 10634 /* MMU_INTFI_S1_ST_TB */ "FC S1 STATE Table", 10635 /* MMU_INTFI_ST_TRANS_TBL */ "State Translation Table in Mapping and Storage", 10636 /* MMU_INTFI_XLATE_TBL */ "Status Translation Table. XLATE_TBL0 = 0-255, XLATE_TBL1 = 256-511", 10637 /* MMU_INTFI_XPIPE_FC_MAP_TBL0 */ "FC Map Table for Level 0 in Mapping and Storage", 10638 /* MMU_INTFI_XPIPE_FC_MAP_TBL1 */ "FC Map Table for Level 1 in Mapping and Storage", 10639 /* MMU_INTFI_XPIPE_FC_MAP_TBL2 */ "FC Map Table for Level 2 in Mapping and Storage", 10640 /* MMU_INTFI_XPIPE_FC_MAP_TBS1 */ "S1 Map Table for Level S1 in Mapping and Storage", 10641 /* MMU_INTFI_YPIPE_FC_MAP_TBL0 */ "FC Map Table for Level 0 in Mapping and Storage", 10642 /* MMU_INTFI_YPIPE_FC_MAP_TBL1 */ "FC Map Table for Level 1 in Mapping and Storage", 10643 /* MMU_INTFI_YPIPE_FC_MAP_TBL2 */ "FC Map Table for Level 2 in Mapping and Storage", 10644 /* MMU_INTFO_ENG_CONGST_ST */ "Stores the Egress congestion states received from THDO on a per OOB port basis", 10645 /* MMU_INTFO_ING_CONGST_ST */ "Stores the Ingress congestion states received from THDI on a per OOB port basis", 10646 /* MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDI */ "This mapping table maps the MMU global port to OOB port for congestion state received from THDI.\nThe MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDI and the MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDO0/1 tables have to be configured\nwith the same mmu port to oob port mapping", 10647 /* MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDO0 */ "This mapping table maps the MMU global port to OOB port for congestion state received from THDO.\nThe MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDI and the MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDO0/1 tables have to be configured\nwith the same mmu port to oob port mapping", 10648 /* MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDO1 */ "This mapping table maps the MMU global port to OOB port for congestion state received from THDO.\nThe MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDI and the MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDO0/1 tables have to be configured\nwith the same mmu port to oob port mapping", 10649 /* MMU_INTFO_OOBFC_ENG_PORT_PSEL */ "The 2 bits in this table specifies the profile to use to map MMU Queues to OOB bit offsets for each chip port", 10650 /* MMU_INTFO_QCN_CNM_RVD_TBL */ "number of received QCN CNM which triggered PRP PFC/PAUSE", 10651 /* MMU_INTFO_QCN_CNM_TIMER_TBL */ "Timer for triggered PRP PFC/PAUSE", 10652 /* MMU_INTFO_QCN_TBID_TBL */ "table ID for QCN_TIMEOUT_VALUE map table, addressed by dst_port[5:0]", 10653 /* MMU_INTFO_QCN_TOV_TBL */ "QCN_TIMEOUT_VALUE table", 10654 /* MMU_INTFO_TC2PRI_MAPPING */ "Channel TC state to Priority mapping", 10655 /* MMU_INTFO_TC2PRI_MAPPING0 */ "Channel TC state to Priority mapping, instance 0", 10656 /* MMU_INTFO_TC2PRI_MAPPING1 */ "Channel TC state to Priority mapping, instance 1", 10657 /* MMU_INTFO_TC2PRI_MAPPING2 */ "Channel TC state to Priority mapping, instance 2", 10658 /* MMU_INTFO_TC2PRI_MAPPING3 */ "Channel TC state to Priority mapping, instance 3", 10659 /* MMU_INTFO_TIMESTAMP */ "local 1588 timestamp received by INTFO", 10660 /* MMU_INTFO_TOD_TIMESTAMP */ "Time of Day values to be stored by host process for MMU Packet stats UTC conversion from local 1588 timestamp", 10661 /* MMU_INTFO_UTC_TIMESTAMP */ "Converted UTC Timestamp", 10662 /* MMU_IPCTR_CTXT_COUNTER_0 */ "IPCTR CTXT COUNTER 0", 10663 /* MMU_IPCTR_PG_COUNTER_0 */ "IPCTR PG COUNTER 0", 10664 /* MMU_IPCTR_PG_COUNTER_1 */ "IPCTR PG COUNTER 1", 10665 /* MMU_IPMC_GROUP_TBL */ "IPMC VLAN Group Table 0 for PPP#1-32", 10666 /* MMU_IPMC_GROUP_TBL0 */ "IPMC VLAN Group Table 0", 10667 /* MMU_IPMC_GROUP_TBL1 */ "IPMC VLAN Group Table 1", 10668 /* MMU_IPMC_GROUP_TBL2 */ "IPMC VLAN Group Table 2", 10669 /* MMU_IPMC_GROUP_TBL3 */ "IPMC VLAN Group Table 3", 10670 /* MMU_IPMC_GROUP_TBL4 */ "IPMC VLAN Group Table 4", 10671 /* MMU_IPMC_GROUP_TBL5 */ "IPMC VLAN Group Table 5", 10672 /* MMU_IPMC_GROUP_TBL6 */ "IPMC VLAN Group Table 6", 10673 /* MMU_IPMC_GROUP_TBL7 */ "IPMC VLAN Group Table 7", 10674 /* MMU_IPMC_GROUP_TBL8 */ "IPMC VLAN Group Table 8", 10675 /* MMU_IPMC_GROUP_TBL9 */ "IPMC VLAN Group Table 9", 10676 /* MMU_IPMC_GROUP_TBL10 */ "IPMC VLAN Group Table 10", 10677 /* MMU_IPMC_GROUP_TBL11 */ "IPMC VLAN Group Table 11", 10678 /* MMU_IPMC_GROUP_TBL12 */ "IPMC VLAN Group Table 12", 10679 /* MMU_IPMC_GROUP_TBL13 */ "IPMC VLAN Group Table 13", 10680 /* MMU_IPMC_GROUP_TBL14 */ "IPMC VLAN Group Table 14", 10681 /* MMU_IPMC_GROUP_TBL15 */ "IPMC VLAN Group Table 15", 10682 /* MMU_IPMC_GROUP_TBL16 */ "IPMC VLAN Group Table 16", 10683 /* MMU_IPMC_GROUP_TBL17 */ "IPMC VLAN Group Table 17", 10684 /* MMU_IPMC_GROUP_TBL18 */ "IPMC VLAN Group Table 18", 10685 /* MMU_IPMC_GROUP_TBL19 */ "IPMC VLAN Group Table 19", 10686 /* MMU_IPMC_GROUP_TBL20 */ "IPMC VLAN Group Table 20", 10687 /* MMU_IPMC_GROUP_TBL21 */ "IPMC VLAN Group Table 21", 10688 /* MMU_IPMC_GROUP_TBL22 */ "IPMC VLAN Group Table 22", 10689 /* MMU_IPMC_GROUP_TBL23 */ "IPMC VLAN Group Table 23", 10690 /* MMU_IPMC_GROUP_TBL24 */ "IPMC VLAN Group Table 24", 10691 /* MMU_IPMC_GROUP_TBL25 */ "IPMC VLAN Group Table 25", 10692 /* MMU_IPMC_GROUP_TBL26 */ "IPMC VLAN Group Table 26", 10693 /* MMU_IPMC_GROUP_TBL27 */ "IPMC VLAN Group Table 27", 10694 /* MMU_IPMC_GROUP_TBL28 */ "IPMC VLAN Group Table 28", 10695 /* MMU_IPMC_GROUP_TBL29 */ "IPMC VLAN Group Table 29", 10696 /* MMU_IPMC_GROUP_TBL30 */ "IPMC VLAN Group Table 30", 10697 /* MMU_IPMC_GROUP_TBL31 */ "IPMC VLAN Group Table 31", 10698 /* MMU_IPMC_GROUP_TBL32 */ "IPMC VLAN Group Table 32", 10699 /* MMU_IPMC_GROUP_TBL33 */ "IPMC VLAN Group Table 33", 10700 /* MMU_IPMC_GROUP_TBL34 */ "IPMC VLAN Group Table 34", 10701 /* MMU_IPMC_GROUP_TBL35 */ "IPMC VLAN Group Table 35", 10702 /* MMU_IPMC_GROUP_TBL36 */ "IPMC VLAN Group Table 36", 10703 /* MMU_IPMC_GROUP_TBL37 */ "IPMC VLAN Group Table 37", 10704 /* MMU_IPMC_GROUP_TBL38 */ "IPMC VLAN Group Table 38", 10705 /* MMU_IPMC_GROUP_TBL39 */ "IPMC VLAN Group Table 39", 10706 /* MMU_IPMC_GROUP_TBL40 */ "IPMC VLAN Group Table 40", 10707 /* MMU_IPMC_GROUP_TBL41 */ "IPMC VLAN Group Table 41", 10708 /* MMU_IPMC_GROUP_TBL42 */ "IPMC VLAN Group Table 42", 10709 /* MMU_IPMC_GROUP_TBL43 */ "IPMC VLAN Group Table 43", 10710 /* MMU_IPMC_GROUP_TBL44 */ "IPMC VLAN Group Table 44", 10711 /* MMU_IPMC_GROUP_TBL45 */ "IPMC VLAN Group Table 45", 10712 /* MMU_IPMC_GROUP_TBL46 */ "IPMC VLAN Group Table 46", 10713 /* MMU_IPMC_GROUP_TBL47 */ "IPMC VLAN Group Table 47", 10714 /* MMU_IPMC_GROUP_TBL48 */ "IPMC VLAN Group Table 48", 10715 /* MMU_IPMC_GROUP_TBL49 */ "IPMC VLAN Group Table 49", 10716 /* MMU_IPMC_GROUP_TBL50 */ "IPMC VLAN Group Table 50", 10717 /* MMU_IPMC_GROUP_TBL51 */ "IPMC VLAN Group Table 51", 10718 /* MMU_IPMC_GROUP_TBL52 */ "IPMC VLAN Group Table 52", 10719 /* MMU_IPMC_GROUP_TBL53 */ "IPMC VLAN Group Table 53", 10720 /* MMU_IPMC_GROUP_TBL54 */ "IPMC VLAN Group Table 54", 10721 /* MMU_IPMC_GROUP_TBL55 */ "IPMC VLAN Group Table 55", 10722 /* MMU_IPMC_GROUP_TBL56 */ "IPMC VLAN Group Table 56", 10723 /* MMU_IPMC_GROUP_TBL57 */ "IPMC VLAN Group Table 57", 10724 /* MMU_IPMC_GROUP_TBL58 */ "IPMC VLAN Group Table 58", 10725 /* MMU_IPMC_GROUP_TBL59 */ "IPMC VLAN Group Table 59", 10726 /* MMU_IPMC_GROUP_TBL60 */ "IPMC VLAN Group Table 60", 10727 /* MMU_IPMC_GROUP_TBL61 */ "IPMC VLAN Group Table 61", 10728 /* MMU_IPMC_GROUP_TBL62 */ "IPMC VLAN Group Table 62", 10729 /* MMU_IPMC_GROUP_TBL63 */ "IPMC VLAN Group Table 63", 10730 /* MMU_IPMC_GROUP_TBL64 */ "IPMC VLAN Group Table 64", 10731 /* MMU_IPMC_GROUP_TBL65 */ "IPMC VLAN Group Table 65", 10732 /* MMU_IPMC_VLAN_TBL */ "IPMC VLAN LSB Bitmap Table RAM", 10733 /* MMU_IPMC_VLAN_TBL_MEM0 */ "IPMC VLAN LSB Bitmap Table RAM 0", 10734 /* MMU_IPMC_VLAN_TBL_MEM1 */ "IPMC VLAN LSB Bitmap Table RAM 0", 10735 /* MMU_ITE_CTRL_0 */ "ITE Control used for write complete information", 10736 /* MMU_ITE_CTRL_1 */ "ITE Control used for write complete information", 10737 /* MMU_ITE_PACKET_PTR_STORE */ "", 10738 /* MMU_ITE_QMGR_FLL */ "EMA FIFO Free Pointer Linked List", 10739 /* MMU_ITE_QMGR_QLL */ "EMA FIFO Queue Block Linked List", 10740 /* MMU_ITE_WORK_QUEUE_0 */ "EMA FIFO Working memory 0", 10741 /* MMU_ITE_WORK_QUEUE_1 */ "EMA FIFO Working memory 1", 10742 /* MMU_ITE_WORK_QUEUE_2 */ "EMA FIFO Working memory 2", 10743 /* MMU_ITMCFG_MEM_FAIL_ADDR_64 */ "Memory ECC/Parity Failure info FIFO", 10744 /* MMU_ITMCFG_MEM_FAIL_ADDR_64_ITM0 */ "Memory ECC/Parity Failure info FIFO", 10745 /* MMU_ITMCFG_MEM_FAIL_ADDR_64_ITM1 */ "Memory ECC/Parity Failure info FIFO", 10746 /* MMU_LBM */ "Last buffer memory", 10747 /* MMU_LINK_MEM */ "Packet link memory. This is a working FIFO maintained by hardware.", 10748 /* MMU_LINK_MEM_SC0 */ "Packet link memory. This is a working FIFO maintained by hardware.", 10749 /* MMU_LINK_MEM_XPE0 */ "Packet link memory. This is a working FIFO maintained by hardware.", 10750 /* MMU_LINK_MEM_XPE1 */ "Packet link memory. This is a working FIFO maintained by hardware.", 10751 /* MMU_LINK_MEM_XPE2 */ "Packet link memory. This is a working FIFO maintained by hardware.", 10752 /* MMU_LINK_MEM_XPE3 */ "Packet link memory. This is a working FIFO maintained by hardware.", 10753 /* MMU_MAPPER_X_LSB */ "MMU_MAPPER_X_LSB", 10754 /* MMU_MAPPER_Y_LSB */ "MMU_MAPPER_Y_LSB", 10755 /* MMU_MAX_BUCKET_EVEN */ "For port 0,2,4,6,...\nport/cos to MEM idx mapping: idx = {port/2, cos[2:0]}", 10756 /* MMU_MAX_BUCKET_GPORT */ "MMU_MAX_BUCKET_GPORT", 10757 /* MMU_MAX_BUCKET_ODD */ "For port 1,3,5,7,...\nport/cos to MEM idx mapping: idx = {(port-1)/2, cos[2:0]}", 10758 /* MMU_MAX_BUCKET_PGRP0 */ "MMU_MAX_BUCKET_PGRP0 - port 2 ~ 15\nport/cos to MEM idx mapping: idx = {port - 2, cos[2:0]}", 10759 /* MMU_MAX_BUCKET_PGRP1 */ "MMU_MAX_BUCKET_PGRP1 - port 0, 16 ~ 29\nport/cos to MEM idx mapping:\n1. port=0, idx = {0, cos[2:0]}\n2. port!=0, idx = {port - 15, cos[2:0]} (port 16~29)", 10760 /* MMU_MAX_BUCKET_QGROUP */ "port/QG to MEM idx mapping: only for(port >= 58) idx = {port-58, QG[2:0]}", 10761 /* MMU_MAX_BUCKET_QLAYER */ "port/cos to MEM idx mapping:\n if(port <=57) idx = {port, cos[2:0]}\n else idx = {(port-58), cos[5:0]}+ 58*8", 10762 /* MMU_MB_PAYLOAD_SER_CH0 */ "Dummy memory used for PAYLOAD SER reporting on Channel0.", 10763 /* MMU_MB_PAYLOAD_SER_CH1 */ "Dummy memory used for PAYLOAD SER reporting on Channel1.", 10764 /* MMU_MB_PAYLOAD_SER_CH2 */ "Dummy memory used for PAYLOAD SER reporting on Channel2.", 10765 /* MMU_MB_PAYLOAD_SER_CH3 */ "Dummy memory used for PAYLOAD SER reporting on Channel3.", 10766 /* MMU_MB_PAYLOAD_SER_CH0_ITM0 */ "Dummy memory used for PAYLOAD SER reporting on Channel0.", 10767 /* MMU_MB_PAYLOAD_SER_CH0_ITM1 */ "Dummy memory used for PAYLOAD SER reporting on Channel0.", 10768 /* MMU_MB_PAYLOAD_SER_CH1_ITM0 */ "Dummy memory used for PAYLOAD SER reporting on Channel1.", 10769 /* MMU_MB_PAYLOAD_SER_CH1_ITM1 */ "Dummy memory used for PAYLOAD SER reporting on Channel1.", 10770 /* MMU_MB_PAYLOAD_SER_CH2_ITM0 */ "Dummy memory used for PAYLOAD SER reporting on Channel2.", 10771 /* MMU_MB_PAYLOAD_SER_CH2_ITM1 */ "Dummy memory used for PAYLOAD SER reporting on Channel2.", 10772 /* MMU_MB_PAYLOAD_SER_CH3_ITM0 */ "Dummy memory used for PAYLOAD SER reporting on Channel3.", 10773 /* MMU_MB_PAYLOAD_SER_CH3_ITM1 */ "Dummy memory used for PAYLOAD SER reporting on Channel3.", 10774 /* MMU_MB_PAYLOAD_SLICE0_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice0. CPU access is not possible during traffic.", 10775 /* MMU_MB_PAYLOAD_SLICE0_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice0. CPU access is not possible during traffic.", 10776 /* MMU_MB_PAYLOAD_SLICE0_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice0. CPU access is not possible during traffic.", 10777 /* MMU_MB_PAYLOAD_SLICE1_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice1. CPU access is not possible during traffic.", 10778 /* MMU_MB_PAYLOAD_SLICE1_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice1. CPU access is not possible during traffic.", 10779 /* MMU_MB_PAYLOAD_SLICE1_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice1. CPU access is not possible during traffic.", 10780 /* MMU_MB_PAYLOAD_SLICE2_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice2. CPU access is not possible during traffic.", 10781 /* MMU_MB_PAYLOAD_SLICE2_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice2. CPU access is not possible during traffic.", 10782 /* MMU_MB_PAYLOAD_SLICE2_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice2. CPU access is not possible during traffic.", 10783 /* MMU_MB_PAYLOAD_SLICE3_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice3. CPU access is not possible during traffic.", 10784 /* MMU_MB_PAYLOAD_SLICE3_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice3. CPU access is not possible during traffic.", 10785 /* MMU_MB_PAYLOAD_SLICE3_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice3. CPU access is not possible during traffic.", 10786 /* MMU_MB_PAYLOAD_SLICE4_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice4. CPU access is not possible during traffic.", 10787 /* MMU_MB_PAYLOAD_SLICE4_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice4. CPU access is not possible during traffic.", 10788 /* MMU_MB_PAYLOAD_SLICE4_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice4. CPU access is not possible during traffic.", 10789 /* MMU_MB_PAYLOAD_SLICE5_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice5. CPU access is not possible during traffic.", 10790 /* MMU_MB_PAYLOAD_SLICE5_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice5. CPU access is not possible during traffic.", 10791 /* MMU_MB_PAYLOAD_SLICE5_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice5. CPU access is not possible during traffic.", 10792 /* MMU_MB_PAYLOAD_SLICE6_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice6. CPU access is not possible during traffic.", 10793 /* MMU_MB_PAYLOAD_SLICE6_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice6. CPU access is not possible during traffic.", 10794 /* MMU_MB_PAYLOAD_SLICE6_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice6. CPU access is not possible during traffic.", 10795 /* MMU_MB_PAYLOAD_SLICE7_CPU */ "Dummy memory used for PAYLOAD CPU acces only to Slice7. CPU access is not possible during traffic.", 10796 /* MMU_MB_PAYLOAD_SLICE7_CPU_ITM0 */ "Dummy memory used for PAYLOAD CPU acces only to Slice7. CPU access is not possible during traffic.", 10797 /* MMU_MB_PAYLOAD_SLICE7_CPU_ITM1 */ "Dummy memory used for PAYLOAD CPU acces only to Slice7. CPU access is not possible during traffic.", 10798 /* MMU_MCFP */ "MCFP", 10799 /* MMU_MCFP_XPE0 */ "Multicast queue entry free pool. This is a working FIFO maintained by hardware.", 10800 /* MMU_MCFP_XPE1 */ "Multicast queue entry free pool. This is a working FIFO maintained by hardware.", 10801 /* MMU_MCFP_XPE2 */ "Multicast queue entry free pool. This is a working FIFO maintained by hardware.", 10802 /* MMU_MCFP_XPE3 */ "Multicast queue entry free pool. This is a working FIFO maintained by hardware.", 10803 /* MMU_MCQDB0 */ "MCQDB0", 10804 /* MMU_MCQDB1 */ "MCQDB1", 10805 /* MMU_MCQDB_X */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10806 /* MMU_MCQDB_X_A */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10807 /* MMU_MCQDB_X_A_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10808 /* MMU_MCQDB_X_A_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10809 /* MMU_MCQDB_X_A_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10810 /* MMU_MCQDB_X_A_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10811 /* MMU_MCQDB_X_B */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10812 /* MMU_MCQDB_X_B_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10813 /* MMU_MCQDB_X_B_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10814 /* MMU_MCQDB_X_B_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10815 /* MMU_MCQDB_X_B_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10816 /* MMU_MCQDB_X_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10817 /* MMU_MCQDB_X_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10818 /* MMU_MCQDB_X_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10819 /* MMU_MCQDB_X_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10820 /* MMU_MCQDB_Y */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10821 /* MMU_MCQDB_Y_A */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10822 /* MMU_MCQDB_Y_A_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10823 /* MMU_MCQDB_Y_A_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10824 /* MMU_MCQDB_Y_A_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10825 /* MMU_MCQDB_Y_A_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10826 /* MMU_MCQDB_Y_B */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10827 /* MMU_MCQDB_Y_B_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10828 /* MMU_MCQDB_Y_B_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10829 /* MMU_MCQDB_Y_B_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10830 /* MMU_MCQDB_Y_B_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10831 /* MMU_MCQDB_Y_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10832 /* MMU_MCQDB_Y_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10833 /* MMU_MCQDB_Y_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10834 /* MMU_MCQDB_Y_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10835 /* MMU_MCQE */ "MCQE", 10836 /* MMU_MCQE_MAPPER */ "MCQE mapper memory", 10837 /* MMU_MCQE_PREFETCH_X */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10838 /* MMU_MCQE_PREFETCH_X_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10839 /* MMU_MCQE_PREFETCH_X_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10840 /* MMU_MCQE_PREFETCH_X_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10841 /* MMU_MCQE_PREFETCH_X_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10842 /* MMU_MCQE_PREFETCH_Y */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10843 /* MMU_MCQE_PREFETCH_Y_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10844 /* MMU_MCQE_PREFETCH_Y_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10845 /* MMU_MCQE_PREFETCH_Y_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10846 /* MMU_MCQE_PREFETCH_Y_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 10847 /* MMU_MCQE_XPE0 */ "Multicast queue entry. This is a working FIFO maintained by hardware.", 10848 /* MMU_MCQE_XPE1 */ "Multicast queue entry. This is a working FIFO maintained by hardware.", 10849 /* MMU_MCQE_XPE2 */ "Multicast queue entry. This is a working FIFO maintained by hardware.", 10850 /* MMU_MCQE_XPE3 */ "Multicast queue entry. This is a working FIFO maintained by hardware.", 10851 /* MMU_MCQN */ "MCQN", 10852 /* MMU_MCQN_XPE0 */ "Multicast queue entry next pointer. This is a working FIFO maintained by hardware.", 10853 /* MMU_MCQN_XPE1 */ "Multicast queue entry next pointer. This is a working FIFO maintained by hardware.", 10854 /* MMU_MCQN_XPE2 */ "Multicast queue entry next pointer. This is a working FIFO maintained by hardware.", 10855 /* MMU_MCQN_XPE3 */ "Multicast queue entry next pointer. This is a working FIFO maintained by hardware.", 10856 /* MMU_MC_FIFO0 */ "MC_FIFO", 10857 /* MMU_MC_FIFO1 */ "MC_FIFO1", 10858 /* MMU_MC_FIFO2 */ "MC_FIFO1", 10859 /* MMU_MC_FIFO3 */ "MC_FIFO1", 10860 /* MMU_MC_FIFO4 */ "MC_FIFO1", 10861 /* MMU_MC_FIFO5 */ "MC_FIFO1", 10862 /* MMU_MC_FIFO6 */ "MC_FIFO1", 10863 /* MMU_MC_FIFO7 */ "MC_FIFO1", 10864 /* MMU_MC_FIFO8 */ "MC_FIFO1", 10865 /* MMU_MC_FIFO9 */ "MC_FIFO1", 10866 /* MMU_MC_FIFO10 */ "MC_FIFO1", 10867 /* MMU_MC_FIFO11 */ "MC_FIFO1", 10868 /* MMU_MC_FIFO12 */ "MC_FIFO1", 10869 /* MMU_MC_FIFO13 */ "MC_FIFO1", 10870 /* MMU_MC_FIFO14 */ "MC_FIFO1", 10871 /* MMU_MC_FIFO15 */ "MC_FIFO1", 10872 /* MMU_MC_FIFO16 */ "MC_FIFO1", 10873 /* MMU_MC_FIFO17 */ "MC_FIFO1", 10874 /* MMU_MC_FIFO18 */ "MC_FIFO1", 10875 /* MMU_MC_FIFO19 */ "MC_FIFO1", 10876 /* MMU_MC_FIFO20 */ "MC_FIFO1", 10877 /* MMU_MC_FIFO21 */ "MC_FIFO1", 10878 /* MMU_MC_FIFO22 */ "MC_FIFO1", 10879 /* MMU_MC_FIFO23 */ "MC_FIFO1", 10880 /* MMU_MC_FIFO24 */ "MC_FIFO1", 10881 /* MMU_MC_FIFO25 */ "MC_FIFO1", 10882 /* MMU_MC_FIFO26 */ "MC_FIFO1", 10883 /* MMU_MC_FIFO27 */ "MC_FIFO1", 10884 /* MMU_MC_FIFO28 */ "MC_FIFO1", 10885 /* MMU_MC_FIFO29 */ "MC_FIFO1", 10886 /* MMU_MC_FIFO30 */ "MC_FIFO1", 10887 /* MMU_MC_FIFO31 */ "MC_FIFO1", 10888 /* MMU_MC_FIFO32 */ "MC_FIFO1", 10889 /* MMU_MC_FIFO33 */ "MC_FIFO1", 10890 /* MMU_MC_FIFO34 */ "MC_FIFO1", 10891 /* MMU_MC_FIFO35 */ "MC_FIFO1", 10892 /* MMU_MC_FIFO36 */ "MC_FIFO1", 10893 /* MMU_MC_FIFO37 */ "MC_FIFO1", 10894 /* MMU_MC_FIFO38 */ "MC_FIFO1", 10895 /* MMU_MC_FIFO39 */ "MC_FIFO1", 10896 /* MMU_MC_FIFO40 */ "MC_FIFO1", 10897 /* MMU_MC_FIFO41 */ "MC_FIFO1", 10898 /* MMU_MC_FIFO42 */ "MC_FIFO1", 10899 /* MMU_MC_FIFO43 */ "MC_FIFO1", 10900 /* MMU_MC_FIFO44 */ "MC_FIFO1", 10901 /* MMU_MC_FIFO45 */ "MC_FIFO1", 10902 /* MMU_MC_FIFO46 */ "MC_FIFO1", 10903 /* MMU_MC_FIFO47 */ "MC_FIFO1", 10904 /* MMU_MC_FIFO48 */ "MC_FIFO1", 10905 /* MMU_MC_FIFO49 */ "MC_FIFO1", 10906 /* MMU_MC_FIFO50 */ "MC_FIFO1", 10907 /* MMU_MC_FIFO51 */ "MC_FIFO1", 10908 /* MMU_MC_FIFO52 */ "MC_FIFO1", 10909 /* MMU_MC_FIFO53 */ "MC_FIFO1", 10910 /* MMU_MC_FIFO54 */ "MC_FIFO1", 10911 /* MMU_MC_FIFO55 */ "MC_FIFO1", 10912 /* MMU_MC_FIFO56 */ "MC_FIFO1", 10913 /* MMU_MC_FIFO57 */ "MC_FIFO1", 10914 /* MMU_MC_FIFO58 */ "MC_FIFO1", 10915 /* MMU_MC_FIFO59 */ "MC_FIFO1", 10916 /* MMU_MC_FIFO60 */ "MC_FIFO1", 10917 /* MMU_MC_FIFO61 */ "MC_FIFO1", 10918 /* MMU_MC_FIFO62 */ "MC_FIFO1", 10919 /* MMU_MC_FIFO63 */ "MC_FIFO1", 10920 /* MMU_MC_FIFO64 */ "MC_FIFO1", 10921 /* MMU_MC_FIFO65 */ "MC_FIFO1", 10922 /* MMU_MC_FIFO48_1 */ "MC_FIFO", 10923 /* MMU_MC_FIFO49_1 */ "MC_FIFO", 10924 /* MMU_MC_FIFO50_1 */ "MC_FIFO", 10925 /* MMU_MC_FIFO51_1 */ "MC_FIFO", 10926 /* MMU_MC_FIFO52_1 */ "MC_FIFO", 10927 /* MMU_MC_FIFO53_1 */ "MC_FIFO", 10928 /* MMU_MC_FIFO54_1 */ "MC_FIFO", 10929 /* MMU_MC_FIFO55_1 */ "MC_FIFO", 10930 /* MMU_MC_FIFO57_1 */ "MC_FIFO", 10931 /* MMU_MC_FIFO57_2 */ "MC_FIFO", 10932 /* MMU_MC_FIFO57_3 */ "MC_FIFO", 10933 /* MMU_MC_FIFO59_1 */ "MC_FIFO", 10934 /* MMU_MC_FIFO59_2 */ "MC_FIFO", 10935 /* MMU_MIN_BUCKET_EVEN */ "For port 0,2,4,6,...\nport/cos to MEM idx mapping: idx = {port/2, cos[2:0]}", 10936 /* MMU_MIN_BUCKET_GPORT */ "MMU_MIN_BUCKET_GPORT", 10937 /* MMU_MIN_BUCKET_ODD */ "For port 1,3,5,7,...\nport/cos to MEM idx mapping: idx = {(port-1)/2, cos[2:0]}", 10938 /* MMU_MIN_BUCKET_PGRP0 */ "MMU_MIN_BUCKET_PGRP0 - port 2 ~ 15\nport/cos to MEM idx mapping: idx = {port - 2, cos[2:0]}", 10939 /* MMU_MIN_BUCKET_PGRP1 */ "MMU_MIN_BUCKET_PGRP1 - port 0, 16 ~ 29\nport/cos to MEM idx mapping:\n1. port=0, idx = {0, cos[2:0]}\n2. port!=0, idx = {port - 15, cos[2:0]} (port 16~29)", 10940 /* MMU_MIN_BUCKET_QGROUP */ "port/QG to MEM idx mapping: only for(port >= 58) idx = {port-58, QG[2:0]}", 10941 /* MMU_MIN_BUCKET_QLAYER */ "port/cos to MEM idx mapping:\n if(port <=57) idx = {port, cos[2:0]}\n else idx = {(port-58), cos[5:0]}+ 58*8", 10942 /* MMU_MTRI_BKPMETERINGBUCKET_MEM_0 */ "Back-pressure Metering Bucket", 10943 /* MMU_MTRI_BKPMETERINGBUCKET_MEM_1 */ "Back-pressure Metering Bucket", 10944 /* MMU_MTRI_BKPMETERINGCONFIG_MEM_0 */ "Back-pressure Metering Config", 10945 /* MMU_MTRI_BKPMETERINGCONFIG_MEM_1 */ "Back-pressure Metering Config", 10946 /* MMU_MTRO_BUCKET_CPU_L1 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10947 /* MMU_MTRO_BUCKET_CPU_L1_PIPE0 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10948 /* MMU_MTRO_BUCKET_CPU_L1_PIPE1 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10949 /* MMU_MTRO_BUCKET_CPU_L1_PIPE2 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10950 /* MMU_MTRO_BUCKET_CPU_L1_PIPE3 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10951 /* MMU_MTRO_BUCKET_CPU_L1_PIPE4 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10952 /* MMU_MTRO_BUCKET_CPU_L1_PIPE5 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10953 /* MMU_MTRO_BUCKET_CPU_L1_PIPE6 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10954 /* MMU_MTRO_BUCKET_CPU_L1_PIPE7 */ "L1 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10955 /* MMU_MTRO_BUCKET_L0 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10956 /* MMU_MTRO_BUCKET_L0_MEM */ "L0 nodes min/max bucket. This cannot be written to, and is used by the shaping logic to store the bucket count/status", 10957 /* MMU_MTRO_BUCKET_L0_MEM_0 */ "L0 nodes min/max bucket", 10958 /* MMU_MTRO_BUCKET_L0_MEM_1 */ "L0 nodes min/max bucket", 10959 /* MMU_MTRO_BUCKET_L0_MEM_PIPE0 */ "L0 nodes min/max bucket. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 10960 /* MMU_MTRO_BUCKET_L0_MEM_PIPE1 */ "L0 nodes min/max bucket. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 10961 /* MMU_MTRO_BUCKET_L0_MEM_PIPE2 */ "L0 nodes min/max bucket. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 10962 /* MMU_MTRO_BUCKET_L0_MEM_PIPE3 */ "L0 nodes min/max bucket. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 10963 /* MMU_MTRO_BUCKET_L0_PIPE0 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10964 /* MMU_MTRO_BUCKET_L0_PIPE1 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10965 /* MMU_MTRO_BUCKET_L0_PIPE2 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10966 /* MMU_MTRO_BUCKET_L0_PIPE3 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10967 /* MMU_MTRO_BUCKET_L0_PIPE4 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10968 /* MMU_MTRO_BUCKET_L0_PIPE5 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10969 /* MMU_MTRO_BUCKET_L0_PIPE6 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10970 /* MMU_MTRO_BUCKET_L0_PIPE7 */ "L0 nodes min/max bucket.Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10971 /* MMU_MTRO_BUCKET_L1_MEM */ "L1 nodes min/max bucket. This cannot be written to, and is used by the shaping logic to store the bucket count/status", 10972 /* MMU_MTRO_BUCKET_L1_MEM_0 */ "L1 nodes min/max bucket", 10973 /* MMU_MTRO_BUCKET_L1_MEM_1 */ "L1 nodes min/max bucket", 10974 /* MMU_MTRO_BUCKET_L1_MEM_PIPE0 */ "L1 nodes min/max bucket. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 10975 /* MMU_MTRO_BUCKET_L1_MEM_PIPE1 */ "L1 nodes min/max bucket. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 10976 /* MMU_MTRO_BUCKET_L1_MEM_PIPE2 */ "L1 nodes min/max bucket. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 10977 /* MMU_MTRO_BUCKET_L1_MEM_PIPE3 */ "L1 nodes min/max bucket. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 10978 /* MMU_MTRO_BUCKET_L2_MEM */ "L2 nodes min/max bucket. This cannot be written to, and is used by the shaping logic to store the bucket count/status", 10979 /* MMU_MTRO_BUCKET_L2_MEM_0 */ "L2 nodes min/max bucket", 10980 /* MMU_MTRO_BUCKET_L2_MEM_1 */ "L2 nodes min/max bucket", 10981 /* MMU_MTRO_BUCKET_L2_MEM_2 */ "L2 nodes min/max bucket", 10982 /* MMU_MTRO_BUCKET_L2_MEM_3 */ "L2 nodes min/max bucket", 10983 /* MMU_MTRO_BUCKET_L2_MEM_4 */ "L2 nodes min/max bucket", 10984 /* MMU_MTRO_BUCKET_L2_MEM_5 */ "L2 nodes min/max bucket", 10985 /* MMU_MTRO_BUCKET_L2_MEM_6 */ "L2 nodes min/max bucket", 10986 /* MMU_MTRO_BUCKET_L2_MEM_7 */ "L2 nodes min/max bucket", 10987 /* MMU_MTRO_BUCKET_L2_MEM_PIPE0 */ "L2 nodes min/max bucket. The index to this memory is the L2 number of this pipe, ranging from 0 to 1299. The extra entries outside of the range are not used.", 10988 /* MMU_MTRO_BUCKET_L3_MEM */ "L3 nodes min/max bucket. The index to this memory is the L3 number of this pipe, ranging from 0 to 659. The extra entries outside of the range are not used.", 10989 /* MMU_MTRO_BUCKET_L3_MEM_PIPE0 */ "L3 nodes min/max bucket. The index to this memory is the L3 number of this pipe, ranging from 0 to 659. The extra entries outside of the range are not used.", 10990 /* MMU_MTRO_BUCKET_S1_MEM_0 */ "S1 level metering configuration", 10991 /* MMU_MTRO_CPU_L1_A */ "L1 nodes min/max configuration.", 10992 /* MMU_MTRO_CPU_L1_B */ "L1 nodes min/max configuration.", 10993 /* MMU_MTRO_CPU_L1_C */ "L1 nodes min/max configuration.", 10994 /* MMU_MTRO_EGRMETERINGBUCKET */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 10995 /* MMU_MTRO_EGRMETERINGBUCKET_MEM */ "Port level metering status", 10996 /* MMU_MTRO_EGRMETERINGBUCKET_MEM_0 */ "Port level metering configuration", 10997 /* MMU_MTRO_EGRMETERINGBUCKET_MEM_1 */ "Port level metering configuration", 10998 /* MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE0 */ "Port level metering status", 10999 /* MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE1 */ "Port level metering status", 11000 /* MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE2 */ "Port level metering status", 11001 /* MMU_MTRO_EGRMETERINGBUCKET_MEM_PIPE3 */ "Port level metering status", 11002 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE0 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11003 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE1 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11004 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE2 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11005 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE3 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11006 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE4 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11007 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE5 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11008 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE6 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11009 /* MMU_MTRO_EGRMETERINGBUCKET_PIPE7 */ "Port level metering status. Note memory should not be accessed by CPU while the corresponding entries has refresh enabled", 11010 /* MMU_MTRO_EGRMETERINGCONFIG */ "Port level metering configuration.", 11011 /* MMU_MTRO_EGRMETERINGCONFIG_MEM */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used.", 11012 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_0 */ "Port level metering configuration", 11013 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_1 */ "Port level metering configuration", 11014 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_A */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11015 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE0 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11016 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE1 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11017 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE2 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11018 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE3 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11019 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_B */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11020 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE0 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11021 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE1 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11022 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE2 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11023 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE3 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_EGRMETERINGCONFIG_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11024 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE0 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used.", 11025 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE1 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used.", 11026 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE2 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used.", 11027 /* MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE3 */ "Port level metering configuration. The index to this memory is the MMU port number, ranging from 0 to 33. The extra entries outside of the range are not used.", 11028 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE0 */ "Port level metering configuration.", 11029 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE1 */ "Port level metering configuration.", 11030 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE2 */ "Port level metering configuration.", 11031 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE3 */ "Port level metering configuration.", 11032 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE4 */ "Port level metering configuration.", 11033 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE5 */ "Port level metering configuration.", 11034 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE6 */ "Port level metering configuration.", 11035 /* MMU_MTRO_EGRMETERINGCONFIG_PIPE7 */ "Port level metering configuration.", 11036 /* MMU_MTRO_L0_A */ "L0 nodes min/max configuration.", 11037 /* MMU_MTRO_L0_A_PIPE0 */ "L0 nodes min/max configuration.", 11038 /* MMU_MTRO_L0_A_PIPE1 */ "L0 nodes min/max configuration.", 11039 /* MMU_MTRO_L0_A_PIPE2 */ "L0 nodes min/max configuration.", 11040 /* MMU_MTRO_L0_A_PIPE3 */ "L0 nodes min/max configuration.", 11041 /* MMU_MTRO_L0_A_PIPE4 */ "L0 nodes min/max configuration.", 11042 /* MMU_MTRO_L0_A_PIPE5 */ "L0 nodes min/max configuration.", 11043 /* MMU_MTRO_L0_A_PIPE6 */ "L0 nodes min/max configuration.", 11044 /* MMU_MTRO_L0_A_PIPE7 */ "L0 nodes min/max configuration.", 11045 /* MMU_MTRO_L0_B */ "L0 nodes min/max configuration.", 11046 /* MMU_MTRO_L0_B_PIPE0 */ "L0 nodes min/max configuration.", 11047 /* MMU_MTRO_L0_B_PIPE1 */ "L0 nodes min/max configuration.", 11048 /* MMU_MTRO_L0_B_PIPE2 */ "L0 nodes min/max configuration.", 11049 /* MMU_MTRO_L0_B_PIPE3 */ "L0 nodes min/max configuration.", 11050 /* MMU_MTRO_L0_B_PIPE4 */ "L0 nodes min/max configuration.", 11051 /* MMU_MTRO_L0_B_PIPE5 */ "L0 nodes min/max configuration.", 11052 /* MMU_MTRO_L0_B_PIPE6 */ "L0 nodes min/max configuration.", 11053 /* MMU_MTRO_L0_B_PIPE7 */ "L0 nodes min/max configuration.", 11054 /* MMU_MTRO_L0_C */ "L0 nodes min/max configuration.", 11055 /* MMU_MTRO_L0_C_PIPE0 */ "L0 nodes min/max configuration.", 11056 /* MMU_MTRO_L0_C_PIPE1 */ "L0 nodes min/max configuration.", 11057 /* MMU_MTRO_L0_C_PIPE2 */ "L0 nodes min/max configuration.", 11058 /* MMU_MTRO_L0_C_PIPE3 */ "L0 nodes min/max configuration.", 11059 /* MMU_MTRO_L0_C_PIPE4 */ "L0 nodes min/max configuration.", 11060 /* MMU_MTRO_L0_C_PIPE5 */ "L0 nodes min/max configuration.", 11061 /* MMU_MTRO_L0_C_PIPE6 */ "L0 nodes min/max configuration.", 11062 /* MMU_MTRO_L0_C_PIPE7 */ "L0 nodes min/max configuration.", 11063 /* MMU_MTRO_L0_MEM */ "L0 nodes min/max configuration", 11064 /* MMU_MTRO_L0_MEM_0 */ "L0 nodes min/max configuration", 11065 /* MMU_MTRO_L0_MEM_1 */ "L0 nodes min/max configuration", 11066 /* MMU_MTRO_L0_MEM_A */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11067 /* MMU_MTRO_L0_MEM_A_PIPE0 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11068 /* MMU_MTRO_L0_MEM_A_PIPE1 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11069 /* MMU_MTRO_L0_MEM_A_PIPE2 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11070 /* MMU_MTRO_L0_MEM_A_PIPE3 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11071 /* MMU_MTRO_L0_MEM_B */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11072 /* MMU_MTRO_L0_MEM_B_PIPE0 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11073 /* MMU_MTRO_L0_MEM_B_PIPE1 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11074 /* MMU_MTRO_L0_MEM_B_PIPE2 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11075 /* MMU_MTRO_L0_MEM_B_PIPE3 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11076 /* MMU_MTRO_L0_MEM_PIPE0 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11077 /* MMU_MTRO_L0_MEM_PIPE1 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11078 /* MMU_MTRO_L0_MEM_PIPE2 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11079 /* MMU_MTRO_L0_MEM_PIPE3 */ "L0 nodes min/max configuration. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. The extra entries outside of the range are not used.", 11080 /* MMU_MTRO_L1_MEM */ "L1 nodes min/max configuration", 11081 /* MMU_MTRO_L1_MEM_0 */ "L1 nodes min/max configuration", 11082 /* MMU_MTRO_L1_MEM_1 */ "L1 nodes min/max configuration", 11083 /* MMU_MTRO_L1_MEM_A */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11084 /* MMU_MTRO_L1_MEM_A_PIPE0 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11085 /* MMU_MTRO_L1_MEM_A_PIPE1 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11086 /* MMU_MTRO_L1_MEM_A_PIPE2 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11087 /* MMU_MTRO_L1_MEM_A_PIPE3 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11088 /* MMU_MTRO_L1_MEM_B */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11089 /* MMU_MTRO_L1_MEM_B_PIPE0 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11090 /* MMU_MTRO_L1_MEM_B_PIPE1 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11091 /* MMU_MTRO_L1_MEM_B_PIPE2 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11092 /* MMU_MTRO_L1_MEM_B_PIPE3 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11093 /* MMU_MTRO_L1_MEM_PIPE0 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11094 /* MMU_MTRO_L1_MEM_PIPE1 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11095 /* MMU_MTRO_L1_MEM_PIPE2 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11096 /* MMU_MTRO_L1_MEM_PIPE3 */ "L1 nodes min/max configuration. The index to this memory is the logical queue number of this pipe, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used.", 11097 /* MMU_MTRO_L2_MEM */ "L2 nodes min/max configuration", 11098 /* MMU_MTRO_L2_MEM_0 */ "L2 nodes min/max configuration", 11099 /* MMU_MTRO_L2_MEM_1 */ "L2 nodes min/max configuration", 11100 /* MMU_MTRO_L2_MEM_2 */ "L2 nodes min/max configuration", 11101 /* MMU_MTRO_L2_MEM_3 */ "L2 nodes min/max configuration", 11102 /* MMU_MTRO_L2_MEM_4 */ "L2 nodes min/max configuration", 11103 /* MMU_MTRO_L2_MEM_5 */ "L2 nodes min/max configuration", 11104 /* MMU_MTRO_L2_MEM_6 */ "L2 nodes min/max configuration", 11105 /* MMU_MTRO_L2_MEM_7 */ "L2 nodes min/max configuration", 11106 /* MMU_MTRO_L2_MEM_A */ "L2 nodes min/max configuration. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_L2_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11107 /* MMU_MTRO_L2_MEM_A_PIPE0 */ "L2 nodes min/max configuration. The index to this memory is the L2 number of this pipe, ranging from 0 to 1299. The extra entries outside of the range are not used.", 11108 /* MMU_MTRO_L2_MEM_B */ "L2 nodes min/max configuration. NOTE: This is a replicated database for testing only. Use the MMU_MTRO_L2_MEM for normal operation. Accessing this memory is only allowed when traffic is idle.", 11109 /* MMU_MTRO_L2_MEM_B_PIPE0 */ "L2 nodes min/max configuration. The index to this memory is the L2 number of this pipe, ranging from 0 to 1299. The extra entries outside of the range are not used.", 11110 /* MMU_MTRO_L2_MEM_PIPE0 */ "L2 nodes min/max configuration. The index to this memory is the L2 number of this pipe, ranging from 0 to 1299. The extra entries outside of the range are not used.", 11111 /* MMU_MTRO_L3_MEM */ "L3 nodes min/max configuration. The index to this memory is the L3 number of this pipe, ranging from 0 to 2617. The extra entries outside of the range are not used.", 11112 /* MMU_MTRO_L3_MEM_A */ "L3 nodes min/max configuration. The index to this memory is the L3 number of this pipe, ranging from 0 to 2617. The extra entries outside of the range are not used.", 11113 /* MMU_MTRO_L3_MEM_A_PIPE0 */ "L3 nodes min/max configuration. The index to this memory is the L3 number of this pipe, ranging from 0 to 2617. The extra entries outside of the range are not used.", 11114 /* MMU_MTRO_L3_MEM_B */ "L3 nodes min/max configuration. The index to this memory is the L3 number of this pipe, ranging from 0 to 2617. The extra entries outside of the range are not used.", 11115 /* MMU_MTRO_L3_MEM_B_PIPE0 */ "L3 nodes min/max configuration. The index to this memory is the L3 number of this pipe, ranging from 0 to 2617. The extra entries outside of the range are not used.", 11116 /* MMU_MTRO_L3_MEM_PIPE0 */ "L3 nodes min/max configuration. The index to this memory is the L3 number of this pipe, ranging from 0 to 2617. The extra entries outside of the range are not used.", 11117 /* MMU_MTRO_S1_MEM_0 */ "S1 level metering configuration", 11118 /* MMU_OQS_RECEPTION_FIFO */ "OQS Reception Fifo", 11119 /* MMU_OQS_RECEPTION_FIFO_ITM0 */ "OQS Reception Fifo", 11120 /* MMU_OQS_RECEPTION_FIFO_ITM1 */ "OQS Reception Fifo", 11121 /* MMU_OQS_SEG0_BANK0_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11122 /* MMU_OQS_SEG0_BANK0_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11123 /* MMU_OQS_SEG0_BANK0_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11124 /* MMU_OQS_SEG0_BANK1_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11125 /* MMU_OQS_SEG0_BANK1_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11126 /* MMU_OQS_SEG0_BANK1_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11127 /* MMU_OQS_SEG0_BANK2_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11128 /* MMU_OQS_SEG0_BANK2_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11129 /* MMU_OQS_SEG0_BANK2_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11130 /* MMU_OQS_SEG0_BANK3_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11131 /* MMU_OQS_SEG0_BANK3_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11132 /* MMU_OQS_SEG0_BANK3_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11133 /* MMU_OQS_SEG0_BANK4_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11134 /* MMU_OQS_SEG0_BANK4_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11135 /* MMU_OQS_SEG0_BANK4_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11136 /* MMU_OQS_SEG0_BANK5_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11137 /* MMU_OQS_SEG0_BANK5_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11138 /* MMU_OQS_SEG0_BANK5_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11139 /* MMU_OQS_SEG1_BANK0_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11140 /* MMU_OQS_SEG1_BANK0_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11141 /* MMU_OQS_SEG1_BANK0_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11142 /* MMU_OQS_SEG1_BANK1_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11143 /* MMU_OQS_SEG1_BANK1_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11144 /* MMU_OQS_SEG1_BANK1_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11145 /* MMU_OQS_SEG1_BANK2_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11146 /* MMU_OQS_SEG1_BANK2_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11147 /* MMU_OQS_SEG1_BANK2_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11148 /* MMU_OQS_SEG1_BANK3_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11149 /* MMU_OQS_SEG1_BANK3_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11150 /* MMU_OQS_SEG1_BANK3_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11151 /* MMU_OQS_SEG1_BANK4_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11152 /* MMU_OQS_SEG1_BANK4_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11153 /* MMU_OQS_SEG1_BANK4_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11154 /* MMU_OQS_SEG1_BANK5_FIFO_MEM */ "Per Orthogonal Queue Set Cell Fifo", 11155 /* MMU_OQS_SEG1_BANK5_FIFO_MEM_ITM0 */ "Per Orthogonal Queue Set Cell Fifo", 11156 /* MMU_OQS_SEG1_BANK5_FIFO_MEM_ITM1 */ "Per Orthogonal Queue Set Cell Fifo", 11157 /* MMU_OVQ_BANK0_MEM0 */ "OVQ BANK0 MEM0", 11158 /* MMU_OVQ_BANK0_MEM1 */ "OVQ BANK0 MEM1", 11159 /* MMU_OVQ_BANK0_MEM2 */ "OVQ BANK0 MEM2", 11160 /* MMU_OVQ_BANK0_MEM3 */ "OVQ BANK0 MEM3", 11161 /* MMU_OVQ_BANK1_MEM0 */ "OVQ BANK1 MEM0", 11162 /* MMU_OVQ_BANK1_MEM1 */ "OVQ BANK1 MEM1", 11163 /* MMU_OVQ_BANK1_MEM2 */ "OVQ BANK1 MEM2", 11164 /* MMU_OVQ_BANK1_MEM3 */ "OVQ BANK0 MEM3", 11165 /* MMU_OVQ_BANK2_MEM0 */ "OVQ BANK2 MEM0", 11166 /* MMU_OVQ_BANK2_MEM1 */ "OVQ BANK2 MEM1", 11167 /* MMU_OVQ_BANK2_MEM2 */ "OVQ BANK2 MEM2", 11168 /* MMU_OVQ_BANK2_MEM3 */ "OVQ BANK2 MEM3", 11169 /* MMU_OVQ_BANK3_MEM0 */ "OVQ BANK3 MEM0", 11170 /* MMU_OVQ_BANK3_MEM1 */ "OVQ BANK3 MEM1", 11171 /* MMU_OVQ_BANK3_MEM2 */ "OVQ BANK0 MEM2", 11172 /* MMU_OVQ_BANK3_MEM3 */ "OVQ BANK3 MEM3", 11173 /* MMU_OVQ_DISTRIBUTOR_MEM0 */ "OVQ_DISTRIBUTOR_MEM0", 11174 /* MMU_OVQ_DISTRIBUTOR_MEM1 */ "OVQ_DISTRIBUTOR_MEM1", 11175 /* MMU_OVQ_DISTRIBUTOR_MEM2 */ "OVQ Distributor MEM2", 11176 /* MMU_OVQ_DISTRIBUTOR_MEM3 */ "OVQ DISTRIBUTOR MEM3", 11177 /* MMU_PDB0 */ "PDB0", 11178 /* MMU_PDB1 */ "PDB1", 11179 /* MMU_PDB_X */ "This memory contains the per port database of PDB_X for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11180 /* MMU_PDB_X_XPE0 */ "This memory contains the per port database of PDB_X for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11181 /* MMU_PDB_X_XPE1 */ "This memory contains the per port database of PDB_X for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11182 /* MMU_PDB_X_XPE2 */ "This memory contains the per port database of PDB_X for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11183 /* MMU_PDB_X_XPE3 */ "This memory contains the per port database of PDB_X for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11184 /* MMU_PDB_Y */ "This memory contains the per port database of PDB_Y for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11185 /* MMU_PDB_Y_XPE0 */ "This memory contains the per port database of PDB_Y for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11186 /* MMU_PDB_Y_XPE1 */ "This memory contains the per port database of PDB_Y for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11187 /* MMU_PDB_Y_XPE2 */ "This memory contains the per port database of PDB_Y for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11188 /* MMU_PDB_Y_XPE3 */ "This memory contains the per port database of PDB_Y for ongoing packet information and enables traversal through the cell-link structrure.\nThe index to this table are MMU port numbers as below :\n0-31 : General Ports (Ethernet/HiGig)\n32 : CPU port\n33 : Loopback port\n34-35 : Unused\n36-39 : MMU internal purge ports", 11189 /* MMU_PFAP_MEM */ "Packet Pointer Free Address Pool RAM", 11190 /* MMU_PKTHDR */ "CBP Packet Header RAM", 11191 /* MMU_PKTHDR_XPE0 */ "The Packet Header memory is used to store certain packet information that is generated by the MMU, and is needed when the packet is dequeued.", 11192 /* MMU_PKTHDR_XPE1 */ "The Packet Header memory is used to store certain packet information that is generated by the MMU, and is needed when the packet is dequeued.", 11193 /* MMU_PKTHDR_XPE2 */ "The Packet Header memory is used to store certain packet information that is generated by the MMU, and is needed when the packet is dequeued.", 11194 /* MMU_PKTHDR_XPE3 */ "The Packet Header memory is used to store certain packet information that is generated by the MMU, and is needed when the packet is dequeued.", 11195 /* MMU_PKTLINK */ "PKTLINK", 11196 /* MMU_PKTLINK0 */ "PKTLINK0", 11197 /* MMU_PKTLINK1 */ "PKTLINK1", 11198 /* MMU_PKTLINK2 */ "PKTLINK2", 11199 /* MMU_PKTLINK3 */ "PKTLINK3", 11200 /* MMU_PKTLINK4 */ "PKTLINK4", 11201 /* MMU_PKTLINK5 */ "PKTLINK5", 11202 /* MMU_PKTLINK6 */ "PKTLINK6", 11203 /* MMU_PKTLINK7 */ "PKTLINK7", 11204 /* MMU_PKTLINK8 */ "PKTLINK8", 11205 /* MMU_PKTLINK9 */ "PKTLINK9", 11206 /* MMU_PKTLINK10 */ "PKTLINK10", 11207 /* MMU_PKTLINK11 */ "PKTLINK11", 11208 /* MMU_PKTLINK12 */ "PKTLINK12", 11209 /* MMU_PKTLINK13 */ "PKTLINK13", 11210 /* MMU_PKTLINK14 */ "PKTLINK14", 11211 /* MMU_PKTLINK15 */ "PKTLINK15", 11212 /* MMU_PKTLINK16 */ "PKTLINK16", 11213 /* MMU_PKTLINK17 */ "PKTLINK17", 11214 /* MMU_PKTLINK18 */ "PKTLINK18", 11215 /* MMU_PKTLINK19 */ "PKTLINK19", 11216 /* MMU_PKTLINK20 */ "PKTLINK20", 11217 /* MMU_PKTLINK21 */ "PKTLINK21", 11218 /* MMU_PKTLINK22 */ "PKTLINK22", 11219 /* MMU_PKTLINK23 */ "PKTLINK23", 11220 /* MMU_PKTLINK24 */ "PKTLINK24", 11221 /* MMU_PKTLINK25 */ "PKTLINK25", 11222 /* MMU_PKTLINK26 */ "PKTLINK26", 11223 /* MMU_PKTLINK27 */ "PKTLINK27", 11224 /* MMU_PKTLINK28 */ "PKTLINK28", 11225 /* MMU_PKTLINK29 */ "PKTLINK29", 11226 /* MMU_PKTLINK30 */ "PKTLINK30", 11227 /* MMU_PKTLINK31 */ "PKTLINK31", 11228 /* MMU_PKTLINK32 */ "PKTLINK32", 11229 /* MMU_PKTLINK33 */ "PKTLINK33", 11230 /* MMU_PKTLINK34 */ "PKTLINK34", 11231 /* MMU_PKTLINK35 */ "PKTLINK35", 11232 /* MMU_PKTLINK36 */ "PKTLINK36", 11233 /* MMU_PKTLINK37 */ "PKTLINK37", 11234 /* MMU_PKTLINK38 */ "PKTLINK38", 11235 /* MMU_PKTLINK39 */ "PKTLINK39", 11236 /* MMU_PKTLINK40 */ "PKTLINK40", 11237 /* MMU_PKTLINK41 */ "PKTLINK41", 11238 /* MMU_PKTLINK42 */ "PKTLINK42", 11239 /* MMU_PKTLINK43 */ "PKTLINK43", 11240 /* MMU_PKTLINK44 */ "PKTLINK44", 11241 /* MMU_PKTLINK45 */ "PKTLINK45", 11242 /* MMU_PKTLINK46 */ "PKTLINK46", 11243 /* MMU_PKTLINK47 */ "PKTLINK47", 11244 /* MMU_PKTLINK48 */ "PKTLINK48", 11245 /* MMU_PKTLINK49 */ "PKTLINK49", 11246 /* MMU_PKTLINK50 */ "PKTLINK50", 11247 /* MMU_PKTLINK51 */ "PKTLINK51", 11248 /* MMU_PKTLINK52 */ "PKTLINK52", 11249 /* MMU_PKTLINK53 */ "PKTLINK53", 11250 /* MMU_PKTLINK54 */ "PKTLINK54", 11251 /* MMU_PKT_LINK */ "PKT_LINK", 11252 /* MMU_PKT_LINK_XPE0 */ "Packet link memory. This is a working FIFO maintained by hardware.", 11253 /* MMU_PKT_LINK_XPE1 */ "Packet link memory. This is a working FIFO maintained by hardware.", 11254 /* MMU_PKT_LINK_XPE2 */ "Packet link memory. This is a working FIFO maintained by hardware.", 11255 /* MMU_PKT_LINK_XPE3 */ "Packet link memory. This is a working FIFO maintained by hardware.", 11256 /* MMU_PORTCNT */ "", 11257 /* MMU_PORTCNT_XPE0 */ "The Port Count memory is used to store certain packet information that is computed by the MMU, and is needed when the packet is dequeued.", 11258 /* MMU_PORTCNT_XPE1 */ "The Port Count memory is used to store certain packet information that is computed by the MMU, and is needed when the packet is dequeued.", 11259 /* MMU_PORTCNT_XPE2 */ "The Port Count memory is used to store certain packet information that is computed by the MMU, and is needed when the packet is dequeued.", 11260 /* MMU_PORTCNT_XPE3 */ "The Port Count memory is used to store certain packet information that is computed by the MMU, and is needed when the packet is dequeued.", 11261 /* MMU_PQE0_MEM */ "Central Purge Queue RAM", 11262 /* MMU_PQE0_MEM_XPE0 */ "Central Purge Queue RAM", 11263 /* MMU_PQE0_MEM_XPE1 */ "Central Purge Queue RAM", 11264 /* MMU_PQE0_MEM_XPE2 */ "Central Purge Queue RAM", 11265 /* MMU_PQE0_MEM_XPE3 */ "Central Purge Queue RAM", 11266 /* MMU_PQE1_MEM */ "Central Purge Queue RAM", 11267 /* MMU_PQE1_MEM_XPE0 */ "Central Purge Queue RAM", 11268 /* MMU_PQE1_MEM_XPE1 */ "Central Purge Queue RAM", 11269 /* MMU_PQE1_MEM_XPE2 */ "Central Purge Queue RAM", 11270 /* MMU_PQE1_MEM_XPE3 */ "Central Purge Queue RAM", 11271 /* MMU_PQE_MEM */ "Central Purge Queue RAM", 11272 /* MMU_PQE_MEM0 */ "Central Purge Queue RAM", 11273 /* MMU_PQE_MEM1 */ "Central Purge Queue RAM", 11274 /* MMU_PROT_GROUP_TABLE */ "MMU_PROT_GROUP_TABLE arranged as 32 entries per 1 word indexed by MMU_INITIAL_NHOP_TBL.PROT_GRP_IDX0[9:5]", 11275 /* MMU_QCN_CNM_COUNTER */ "QCN CNM Counter per CP Queue.", 11276 /* MMU_QCN_CNM_QUEUE */ "QCN CNM queue memory", 11277 /* MMU_QCN_CNM_QUEUE0 */ "QCN CNM queue.", 11278 /* MMU_QCN_CNM_QUEUE1 */ "QCN CNM queue.", 11279 /* MMU_QCN_CPQCFG */ "Memory address = dest_port_num\nCPQ configuration", 11280 /* MMU_QCN_CPQST_QLEN */ "Per CPQ state memory for Q length and jitter.", 11281 /* MMU_QCN_CPQST_TSSLS */ "Per CPQ state memory for TSSLS.", 11282 /* MMU_QCN_ENABLE */ "Memory address = dest_port_num\nto enable or disable QCN on per cos queue basis,\nand assign CPQ_index to each QCN enalbed queue (0 or 1).\nOnly up to two CPQs enalbed per egress port.", 11283 /* MMU_QCN_ENABLE_0 */ "Memory address = unicast queue number (11bits)\n0-1479 unicast queues on PIPEx\nEnable or disable QCN on per unicast queue basis,\nand assign CPQ_ID to each QCN enalbed queue .\nOnly support up to 1480 CPQs per chip.", 11284 /* MMU_QCN_ENABLE_1 */ "Memory address = unicast queue number (11bits)\n0-1479 unicast queues on PIPEy\nEnable or disable QCN on per unicast queue basis,\nand assign CPQ_ID to each QCN enalbed queue .\nOnly support up to 1480 CPQs per chip.", 11285 /* MMU_QCN_QFBTB */ "The Table to map QuantizedFb[5:0] from PreQntzFb[6:0].\nThere are eight different choices per PreQntzFb.", 11286 /* MMU_QCN_QLEN_SHADOW */ "Shadow copy of ThDO Unicast queue length in QCN block.", 11287 /* MMU_QCN_QLEN_SHADOW0 */ "Unicast queue length PIPEx.", 11288 /* MMU_QCN_QLEN_SHADOW1 */ "Unicast queue length PIPEy.", 11289 /* MMU_QCN_SITB */ "Sample Interval Table.\nTwo Tables, each has 64 entries.", 11290 /* MMU_QSCH_L0_ACCUM_COMP_MEM */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11291 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE0 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11292 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE1 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11293 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE2 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11294 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE3 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11295 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE4 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11296 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE5 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11297 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE6 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11298 /* MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE7 */ "Internal working memory for hardware to track packet length delta of each L0 (COS) node due to packet modifications. The index to this memory is the L0 node number of this pipe, ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). Extra entries outside of the range are not used", 11299 /* MMU_QSCH_L0_CREDIT_MEM */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11300 /* MMU_QSCH_L0_CREDIT_MEM_PIPE0 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11301 /* MMU_QSCH_L0_CREDIT_MEM_PIPE1 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11302 /* MMU_QSCH_L0_CREDIT_MEM_PIPE2 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11303 /* MMU_QSCH_L0_CREDIT_MEM_PIPE3 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11304 /* MMU_QSCH_L0_CREDIT_MEM_PIPE4 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11305 /* MMU_QSCH_L0_CREDIT_MEM_PIPE5 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11306 /* MMU_QSCH_L0_CREDIT_MEM_PIPE6 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11307 /* MMU_QSCH_L0_CREDIT_MEM_PIPE7 */ "Internal working memory for hardware to track each L0 (COS) node running credits. The index to this memory is the L0 node number of this pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11308 /* MMU_QSCH_L0_FIRST_MEM */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11309 /* MMU_QSCH_L0_FIRST_MEM_PIPE0 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11310 /* MMU_QSCH_L0_FIRST_MEM_PIPE1 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11311 /* MMU_QSCH_L0_FIRST_MEM_PIPE2 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11312 /* MMU_QSCH_L0_FIRST_MEM_PIPE3 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11313 /* MMU_QSCH_L0_FIRST_MEM_PIPE4 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11314 /* MMU_QSCH_L0_FIRST_MEM_PIPE5 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11315 /* MMU_QSCH_L0_FIRST_MEM_PIPE6 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11316 /* MMU_QSCH_L0_FIRST_MEM_PIPE7 */ "Internal hardare working memory that holds each L0 (COS) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L0 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11317 /* MMU_QSCH_L0_WEIGHT_MEM */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11318 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE0 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11319 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE1 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11320 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE2 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11321 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE3 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11322 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE4 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11323 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE5 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11324 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE6 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11325 /* MMU_QSCH_L0_WEIGHT_MEM_PIPE7 */ "This memory holds the weight of each L0 (COS) node. The index to this memory is the L0 node number in the pipe ranging from 0 to 275 (e.g. nodes of port 0 take entries 0-11, nodes of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11326 /* MMU_QSCH_L1_ACCUM_COMP_MEM */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11327 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE0 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11328 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE1 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11329 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE2 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11330 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE3 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11331 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE4 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11332 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE5 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11333 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE6 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11334 /* MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE7 */ "Internal working memory for hardware to track packet length delta of each L1 (queue) node due to packet modifications. The index to this memory is the scheduler queue number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11335 /* MMU_QSCH_L1_CREDIT_MEM */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11336 /* MMU_QSCH_L1_CREDIT_MEM_PIPE0 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11337 /* MMU_QSCH_L1_CREDIT_MEM_PIPE1 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11338 /* MMU_QSCH_L1_CREDIT_MEM_PIPE2 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11339 /* MMU_QSCH_L1_CREDIT_MEM_PIPE3 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11340 /* MMU_QSCH_L1_CREDIT_MEM_PIPE4 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11341 /* MMU_QSCH_L1_CREDIT_MEM_PIPE5 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11342 /* MMU_QSCH_L1_CREDIT_MEM_PIPE6 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11343 /* MMU_QSCH_L1_CREDIT_MEM_PIPE7 */ "Internal working memory for hardware to track each L1 (scheduler queue) node running credits used in weighted round-robin. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11344 /* MMU_QSCH_L1_FIRST_MEM */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11345 /* MMU_QSCH_L1_FIRST_MEM_PIPE0 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11346 /* MMU_QSCH_L1_FIRST_MEM_PIPE1 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11347 /* MMU_QSCH_L1_FIRST_MEM_PIPE2 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11348 /* MMU_QSCH_L1_FIRST_MEM_PIPE3 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11349 /* MMU_QSCH_L1_FIRST_MEM_PIPE4 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11350 /* MMU_QSCH_L1_FIRST_MEM_PIPE5 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11351 /* MMU_QSCH_L1_FIRST_MEM_PIPE6 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11352 /* MMU_QSCH_L1_FIRST_MEM_PIPE7 */ "Internal hardare working memory that holds each L1 (queue) node miscellaneous counts and states for weighted round-robin computations. The index to this memory is the L1 node number of this pipe ranging from 0 to 275. The extra entries outside of the range are not used", 11353 /* MMU_QSCH_L1_WEIGHT_MEM */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11354 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE0 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11355 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE1 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11356 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE2 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11357 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE3 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11358 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE4 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11359 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE5 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11360 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE6 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11361 /* MMU_QSCH_L1_WEIGHT_MEM_PIPE7 */ "This memory holds the weight of each L1 (scheduler queue) node. The index to this memory is the L1 (scheduler queue) node number ranging from 0 to 275 (e.g. queues of port 0 take entries 0-11, queues of port 1 take entries 12-23, etc). The extra entries outside of the range are not used", 11362 /* MMU_QSCH_L2_ACCUM_COMP_MEM */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11363 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE0 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11364 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE1 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11365 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE2 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11366 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE3 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11367 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE4 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11368 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE5 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11369 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE6 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11370 /* MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE7 */ "Internal working memory for hardware to track packet length delta of each VOQ due to packet modifications. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and hence 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside of range of 0 to 551 are not used", 11371 /* MMU_QSCH_L2_CREDIT_MEM */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11372 /* MMU_QSCH_L2_CREDIT_MEM_PIPE0 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11373 /* MMU_QSCH_L2_CREDIT_MEM_PIPE1 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11374 /* MMU_QSCH_L2_CREDIT_MEM_PIPE2 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11375 /* MMU_QSCH_L2_CREDIT_MEM_PIPE3 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11376 /* MMU_QSCH_L2_CREDIT_MEM_PIPE4 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11377 /* MMU_QSCH_L2_CREDIT_MEM_PIPE5 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11378 /* MMU_QSCH_L2_CREDIT_MEM_PIPE6 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11379 /* MMU_QSCH_L2_CREDIT_MEM_PIPE7 */ "Internal working memory for hardware to track each VOQ running credits used in weighted round-robin. The memory is indexed as the following: all VOQs from ITM0 are in even addresses (0, 2, .., 550) and all VOQs from ITM1 are in odd addresses (1,3, ..,551). Each port has 24 VOQs and therefore holds 24 entries, Port 0 occupies addresses 0 to 23, port 1 24 to 47, etc. Extra entries outside the range of 0-551 are not used", 11380 /* MMU_QSCH_L2_WEIGHT_MEM */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11381 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE0 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11382 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE1 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11383 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE2 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11384 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE3 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11385 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE4 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11386 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE5 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11387 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE6 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11388 /* MMU_QSCH_L2_WEIGHT_MEM_PIPE7 */ "The memory holds weight values of VOQs. The memory entry is indexed by the L1 (scheduler queue) node number. Each entry holds the two weights for the two VOQs of the same scheduler queue.", 11389 /* MMU_QSTRUCT_QBLOCK_BM_0 */ "QBLOCK_BM DATABASE", 11390 /* MMU_QSTRUCT_QBLOCK_BM_1 */ "QBLOCK_BM DATABASE", 11391 /* MMU_QSTRUCT_QBLOCK_BM_2 */ "QBLOCK_BM DATABASE", 11392 /* MMU_QSTRUCT_QBLOCK_BM_3 */ "QBLOCK_BM DATABASE", 11393 /* MMU_QSTRUCT_QBLOCK_BM_FIFO_0 */ "QBLOCK_BM_FIFO DATABASE", 11394 /* MMU_QSTRUCT_QBLOCK_BM_FIFO_1 */ "QBLOCK_BM_FIFO DATABASE", 11395 /* MMU_QSTRUCT_QBLOCK_BM_FIFO_2 */ "QBLOCK_BM_FIFO DATABASE", 11396 /* MMU_QSTRUCT_QBLOCK_BM_FIFO_3 */ "QBLOCK_BM_FIFO DATABASE", 11397 /* MMU_QSTRUCT_QBLOCK_NEXT */ "QBLOCK_NEXT DATABASE", 11398 /* MMU_QSTRUCT_QBLOCK_NEXT_0 */ "QBLOCK_NEXT DATABASE", 11399 /* MMU_QSTRUCT_QBLOCK_NEXT_1 */ "QBLOCK_NEXT DATABASE", 11400 /* MMU_QSTRUCT_QBLOCK_NEXT_2 */ "QBLOCK_NEXT DATABASE", 11401 /* MMU_QSTRUCT_QBLOCK_NEXT_3 */ "QBLOCK_NEXT DATABASE", 11402 /* MMU_QSTRUCT_QBLOCK_NEXT_4 */ "QBLOCK_NEXT DATABASE", 11403 /* MMU_QSTRUCT_QBLOCK_NEXT_5 */ "QBLOCK_NEXT DATABASE", 11404 /* MMU_QSTRUCT_QBLOCK_NEXT_6 */ "QBLOCK_NEXT DATABASE", 11405 /* MMU_QSTRUCT_QBLOCK_NEXT_7 */ "QBLOCK_NEXT DATABASE", 11406 /* MMU_QSTRUCT_QENTRY */ "QENTRY DATABASE", 11407 /* MMU_QSTRUCT_QENTRY_LOWER_0 */ "QENTRY DATABASE", 11408 /* MMU_QSTRUCT_QENTRY_LOWER_1 */ "QENTRY DATABASE", 11409 /* MMU_QSTRUCT_QENTRY_LOWER_2 */ "QENTRY DATABASE", 11410 /* MMU_QSTRUCT_QENTRY_LOWER_3 */ "QENTRY DATABASE", 11411 /* MMU_QSTRUCT_QENTRY_LOWER_4 */ "QENTRY DATABASE", 11412 /* MMU_QSTRUCT_QENTRY_LOWER_5 */ "QENTRY DATABASE", 11413 /* MMU_QSTRUCT_QENTRY_LOWER_6 */ "QENTRY DATABASE", 11414 /* MMU_QSTRUCT_QENTRY_LOWER_7 */ "QENTRY DATABASE", 11415 /* MMU_QSTRUCT_QENTRY_UPPER_0 */ "QENTRY_UPPER DATABASE", 11416 /* MMU_QSTRUCT_QENTRY_UPPER_1 */ "QENTRY_UPPER DATABASE", 11417 /* MMU_QSTRUCT_QENTRY_UPPER_2 */ "QENTRY_UPPER DATABASE", 11418 /* MMU_QSTRUCT_QENTRY_UPPER_3 */ "QENTRY_UPPER DATABASE", 11419 /* MMU_QSTRUCT_QENTRY_UPPER_4 */ "QENTRY_UPPER DATABASE", 11420 /* MMU_QSTRUCT_QENTRY_UPPER_5 */ "QENTRY_UPPER DATABASE", 11421 /* MMU_QSTRUCT_QENTRY_UPPER_6 */ "QENTRY_UPPER DATABASE", 11422 /* MMU_QSTRUCT_QENTRY_UPPER_7 */ "QENTRY_UPPER DATABASE", 11423 /* MMU_RAFA */ "RAFA", 11424 /* MMU_RAFA_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11425 /* MMU_RAFB */ "RAFB", 11426 /* MMU_RAFB_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11427 /* MMU_RAFC */ "RAFC", 11428 /* MMU_RAFC_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11429 /* MMU_RAFD_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11430 /* MMU_RAFE_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11431 /* MMU_RAFF_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11432 /* MMU_RAFG_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11433 /* MMU_RAFH_RADDR_STATUS */ "RAF RADDR + STATUS Indirect Mechanism.", 11434 /* MMU_RAF_WADDR */ "RAF WADDR Indirect Mechanism.", 11435 /* MMU_RDEHEADER_MEM0 */ "Re-direct Packet Pass-Through Header MEM0", 11436 /* MMU_RDEHEADER_MEM1 */ "Re-direct Packet Pass-Through Header MEM1", 11437 /* MMU_RDE_ADM_DPC_STORE_MEM */ "RDE ADM needs to store some info per DPC", 11438 /* MMU_RDE_CFIFO_MEM0 */ "DEQ to RDE Cell deallocation info", 11439 /* MMU_RDE_CFIFO_MEM1 */ "DEQ to RDE cell deallocation info", 11440 /* MMU_RDE_COSPCP_MEM */ "Per PG_CoS Packet Redirect Count Table", 11441 /* MMU_RDE_DESCP_MEM */ "Redirect Packet Descriptor", 11442 /* MMU_RDE_FREEDESCPLIST_MEM */ "Redirect FREE List", 11443 /* MMU_RDE_FREELIST_MEM */ "Redirect FREE List", 11444 /* MMU_RDE_FREEPKTLIST_MEM */ "Redirect FREE List", 11445 /* MMU_RDE_ITE_REL_FIFO_MEM */ "DEQ to RDE Cell deallocation info", 11446 /* MMU_RDE_PKTLINK_MEM */ "Redirect Packet Link", 11447 /* MMU_RDE_PQE_FIFO_MEM */ "DEQ to RDE Cell deallocation info", 11448 /* MMU_RDE_PRCP_MEM */ "Packet Redirect Copy Count Table", 11449 /* MMU_RDE_REAL_CELL_FIFO_MEM */ "DEQ to RDE Cell deallocation info", 11450 /* MMU_RDE_TXQ_FLL */ "Free Pointer Block Link List", 11451 /* MMU_RDE_TXQ_QLL */ "Queue Pointer Block Link List", 11452 /* MMU_RDE_TXQ_STATE */ "Store the packet details from ENQ", 11453 /* MMU_RDFA */ "RDFA", 11454 /* MMU_RDFA_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11455 /* MMU_RDFB */ "RDFB", 11456 /* MMU_RDFB_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11457 /* MMU_RDFC */ "RDFC", 11458 /* MMU_RDFC_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11459 /* MMU_RDFD_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11460 /* MMU_RDFE_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11461 /* MMU_RDFF_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11462 /* MMU_RDFG_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11463 /* MMU_RDFH_WADDR_STATUS */ "RDF WADDR + STATUS Indirect Mechanism.", 11464 /* MMU_RDF_RADDR */ "RDF RADDR Indirect Mechanism.", 11465 /* MMU_RD_DATA_MEM */ "Memory to store the Data after the async fifo on the read data path", 11466 /* MMU_RD_FBC_DATA_MEM */ "Memory to store the Fbc Data after the async fifo on the read data path", 11467 /* MMU_REPL_GROUP */ "Replication group table", 11468 /* MMU_REPL_GROUP_INFO0 */ "REPL_GROUP_INFO0", 11469 /* MMU_REPL_GROUP_INFO1 */ "REPL_GROUP_INFO1", 11470 /* MMU_REPL_GROUP_INFO_TBL */ "REPL_GROUP_INFO_TBL", 11471 /* MMU_REPL_GROUP_INFO_TBL0 */ "Shadow memory of MMU_REPL_GROUP_INFO_TBL.\nPlease refer to MMU_REPL_GROUP_INFO_TBLdescription for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11472 /* MMU_REPL_GROUP_INFO_TBL1 */ "Shadow memory of MMU_REPL_GROUP_INFO_TBL.\nPlease refer to MMU_REPL_GROUP_INFO_TBLdescription for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11473 /* MMU_REPL_GROUP_INFO_TBL2 */ "Shadow memory of MMU_REPL_GROUP_INFO_TBL.\nPlease refer to MMU_REPL_GROUP_INFO_TBLdescription for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11474 /* MMU_REPL_GROUP_INFO_TBL3 */ "Shadow memory of MMU_REPL_GROUP_INFO_TBL.\nPlease refer to MMU_REPL_GROUP_INFO_TBLdescription for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11475 /* MMU_REPL_GROUP_INFO_TBL_PIPE0 */ "REPL_GROUP_INFO_TBL", 11476 /* MMU_REPL_GROUP_INFO_TBL_PIPE1 */ "REPL_GROUP_INFO_TBL", 11477 /* MMU_REPL_GROUP_INFO_TBL_PIPE2 */ "REPL_GROUP_INFO_TBL", 11478 /* MMU_REPL_GROUP_INFO_TBL_PIPE3 */ "REPL_GROUP_INFO_TBL", 11479 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11480 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT0 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11481 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT1 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11482 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC0 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11483 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC1 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11484 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC0 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11485 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC1 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11486 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC0 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11487 /* MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC1 */ "Replication Group Initial Copy Count. Values are in physical port domain.", 11488 /* MMU_REPL_GRP_TBL */ "IPMC Replication Group Table", 11489 /* MMU_REPL_GRP_TBL0 */ "IPMC Replication Group Table 0", 11490 /* MMU_REPL_GRP_TBL1 */ "IPMC Replication Group Table 1", 11491 /* MMU_REPL_GRP_TBL2 */ "IPMC Replication Group Table 2", 11492 /* MMU_REPL_HEAD_TBL */ "IPMC Replication Head Table", 11493 /* MMU_REPL_HEAD_TBL_PIPE0 */ "REPL_HEAD_PIPE0", 11494 /* MMU_REPL_HEAD_TBL_PIPE1 */ "REPL_HEAD_PIPE1", 11495 /* MMU_REPL_HEAD_TBL_PIPE2 */ "REPL_HEAD", 11496 /* MMU_REPL_HEAD_TBL_PIPE3 */ "REPL_HEAD", 11497 /* MMU_REPL_HEAD_TBL_SPLIT0 */ "REPL_HEAD_TBL_SPLIT0", 11498 /* MMU_REPL_HEAD_TBL_SPLIT1 */ "REPL_HEAD_TBL_SPLIT1", 11499 /* MMU_REPL_HEAD_TBL_SPLIT0_PIPE0 */ "REPL_HEAD_TBL_SPLIT0", 11500 /* MMU_REPL_HEAD_TBL_SPLIT0_PIPE1 */ "REPL_HEAD_TBL_SPLIT0", 11501 /* MMU_REPL_HEAD_TBL_SPLIT1_PIPE0 */ "REPL_HEAD_TBL_SPLIT1", 11502 /* MMU_REPL_HEAD_TBL_SPLIT1_PIPE1 */ "REPL_HEAD_TBL_SPLIT1", 11503 /* MMU_REPL_LIST_TBL */ "IPMC Replication List LSB Bitmap Table", 11504 /* MMU_REPL_LIST_TBL_PIPE0 */ "IPMC Replication List LSB Bitmap Table", 11505 /* MMU_REPL_LIST_TBL_PIPE1 */ "IPMC Replication List LSB Bitmap Table", 11506 /* MMU_REPL_LIST_TBL_PIPE2 */ "IPMC Replication List LSB Bitmap Table", 11507 /* MMU_REPL_LIST_TBL_PIPE3 */ "IPMC Replication List LSB Bitmap Table", 11508 /* MMU_REPL_MAP_TBL */ "TOQ REPL_MAP Database, memory : Configuration database for mapping DEQ_PKT_CONTEXT to DEST_PPP", 11509 /* MMU_REPL_MEMBER_ICC */ "Logical Depth = 4K ICC entries per ITM. Replication Initial Copy Count for all the REPL_HEAD entries.\nREPL_GROUP members are in the REPL_HEAD table and pointed to by the REPL_GROUP_INFO.base_ptr.\nADDRESS 16 x 4 = 64 entries of 64 ICC values = 6 bit address\nThis view is a logical view of that entire wide memory of 256 ICC entries with a depth of 16 and how it maps\nto bank's and icc values w/ in banks.\nNote: ADDR[1:0] = bank number 0-3, ie. bank's are interleaved\nADDR[5:2] BANK 3 BANK 2 ...", 11510 /* MMU_REPL_MEMBER_ICC_SC0 */ "Replication Initial Copy count Shadow memory of MMU_REPL_MEMBER_ICC.\nPlease refer to MMU_REPL_MEMBER_ICC description for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11511 /* MMU_REPL_MEMBER_ICC_SC1 */ "Replication Initial Copy count Shadow memory of MMU_REPL_MEMBER_ICC.\nPlease refer to MMU_REPL_MEMBER_ICC description for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11512 /* MMU_REPL_MEMBER_ICC_SC2 */ "Replication Initial Copy count Shadow memory of MMU_REPL_MEMBER_ICC.\nPlease refer to MMU_REPL_MEMBER_ICC description for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11513 /* MMU_REPL_MEMBER_ICC_SC3 */ "Replication Initial Copy count Shadow memory of MMU_REPL_MEMBER_ICC.\nPlease refer to MMU_REPL_MEMBER_ICC description for details.\nUser should not directly program this memory for functional purposes but only for debug purposes.", 11514 /* MMU_REPL_STATE_TBL */ "replication state of the MCQS", 11515 /* MMU_REPL_STATE_TBL_ITM0 */ "(Logical Depth = 9 per ITM) Replication state of the MCQS, Addressed by RQE gueue", 11516 /* MMU_REPL_STATE_TBL_ITM1 */ "(Logical Depth = 9 per ITM) Replication state of the MCQS, Addressed by RQE gueue", 11517 /* MMU_REPL_STATE_TBL_PIPE0 */ "replication state of the MCQS", 11518 /* MMU_REPL_STATE_TBL_PIPE1 */ "replication state of the MCQS", 11519 /* MMU_REPL_STATE_TBL_PIPE2 */ "replication state of the MCQS, Addressed per physical multicast gueue, (384 mc queues per layer) x (2 layers) = 768 entries per pipe. There are actually 378 mc queues per layer, however the physical memory used is 384 entries. Address 0-383 is for layer A, address 384-767 is for layer B", 11520 /* MMU_REPL_STATE_TBL_PIPE3 */ "replication state of the MCQS, Addressed per physical multicast gueue, (384 mc queues per layer) x (2 layers) = 768 entries per pipe. There are actually 378 mc queues per layer, however the physical memory used is 384 entries. Address 0-383 is for layer A, address 384-767 is for layer B", 11521 /* MMU_RFAFA */ "RFAFA", 11522 /* MMU_RFAFB */ "RFAFB", 11523 /* MMU_RFAFC */ "RFAFC", 11524 /* MMU_RFDFA */ "RFDFA", 11525 /* MMU_RFDFB */ "RFDFB", 11526 /* MMU_RFDFC */ "RFDFC", 11527 /* MMU_RL_FBANK0 */ "MMU RL EB Queue fifo bank", 11528 /* MMU_RL_FBANK1 */ "MMU RL EB Queue fifo bank", 11529 /* MMU_RL_FBANK2 */ "MMU RL EB Queue fifo bank", 11530 /* MMU_RL_FBANK3 */ "MMU RL EB Queue fifo bank", 11531 /* MMU_RL_FBANK4 */ "MMU RL EB Queue fifo bank", 11532 /* MMU_RL_FBANK5 */ "MMU RL EB Queue fifo bank", 11533 /* MMU_RL_FBANK6 */ "MMU RL EB Queue fifo bank", 11534 /* MMU_RL_FBANK7 */ "MMU RL EB Queue fifo bank", 11535 /* MMU_RL_FBANK8 */ "MMU RL EB Queue fifo bank", 11536 /* MMU_RL_FBANK9 */ "MMU RL EB Queue fifo bank", 11537 /* MMU_RL_FBANK10 */ "MMU RL EB Queue fifo bank", 11538 /* MMU_RL_FBANK11 */ "MMU RL EB Queue fifo bank", 11539 /* MMU_RL_FBANK12 */ "MMU RL EB Queue fifo bank", 11540 /* MMU_RL_FBANK13 */ "MMU RL EB Queue fifo bank", 11541 /* MMU_RL_FBANK14 */ "MMU RL EB Queue fifo bank", 11542 /* MMU_RL_FBANK15 */ "MMU RL EB Queue fifo bank", 11543 /* MMU_RL_FBANK0_ITM0 */ "MMU RL EB Queue fifo bank", 11544 /* MMU_RL_FBANK0_ITM1 */ "MMU RL EB Queue fifo bank", 11545 /* MMU_RL_FBANK10_ITM0 */ "MMU RL EB Queue fifo bank", 11546 /* MMU_RL_FBANK10_ITM1 */ "MMU RL EB Queue fifo bank", 11547 /* MMU_RL_FBANK11_ITM0 */ "MMU RL EB Queue fifo bank", 11548 /* MMU_RL_FBANK11_ITM1 */ "MMU RL EB Queue fifo bank", 11549 /* MMU_RL_FBANK12_ITM0 */ "MMU RL EB Queue fifo bank", 11550 /* MMU_RL_FBANK12_ITM1 */ "MMU RL EB Queue fifo bank", 11551 /* MMU_RL_FBANK13_ITM0 */ "MMU RL EB Queue fifo bank", 11552 /* MMU_RL_FBANK13_ITM1 */ "MMU RL EB Queue fifo bank", 11553 /* MMU_RL_FBANK14_ITM0 */ "MMU RL EB Queue fifo bank", 11554 /* MMU_RL_FBANK14_ITM1 */ "MMU RL EB Queue fifo bank", 11555 /* MMU_RL_FBANK15_ITM0 */ "MMU RL EB Queue fifo bank", 11556 /* MMU_RL_FBANK15_ITM1 */ "MMU RL EB Queue fifo bank", 11557 /* MMU_RL_FBANK1_ITM0 */ "MMU RL EB Queue fifo bank", 11558 /* MMU_RL_FBANK1_ITM1 */ "MMU RL EB Queue fifo bank", 11559 /* MMU_RL_FBANK2_ITM0 */ "MMU RL EB Queue fifo bank", 11560 /* MMU_RL_FBANK2_ITM1 */ "MMU RL EB Queue fifo bank", 11561 /* MMU_RL_FBANK3_ITM0 */ "MMU RL EB Queue fifo bank", 11562 /* MMU_RL_FBANK3_ITM1 */ "MMU RL EB Queue fifo bank", 11563 /* MMU_RL_FBANK4_ITM0 */ "MMU RL EB Queue fifo bank", 11564 /* MMU_RL_FBANK4_ITM1 */ "MMU RL EB Queue fifo bank", 11565 /* MMU_RL_FBANK5_ITM0 */ "MMU RL EB Queue fifo bank", 11566 /* MMU_RL_FBANK5_ITM1 */ "MMU RL EB Queue fifo bank", 11567 /* MMU_RL_FBANK6_ITM0 */ "MMU RL EB Queue fifo bank", 11568 /* MMU_RL_FBANK6_ITM1 */ "MMU RL EB Queue fifo bank", 11569 /* MMU_RL_FBANK7_ITM0 */ "MMU RL EB Queue fifo bank", 11570 /* MMU_RL_FBANK7_ITM1 */ "MMU RL EB Queue fifo bank", 11571 /* MMU_RL_FBANK8_ITM0 */ "MMU RL EB Queue fifo bank", 11572 /* MMU_RL_FBANK8_ITM1 */ "MMU RL EB Queue fifo bank", 11573 /* MMU_RL_FBANK9_ITM0 */ "MMU RL EB Queue fifo bank", 11574 /* MMU_RL_FBANK9_ITM1 */ "MMU RL EB Queue fifo bank", 11575 /* MMU_RL_RQE_FIFO_MEM */ "RQE copy count requests fifo", 11576 /* MMU_RL_RQE_FIFO_MEM_ITM0 */ "RQE copy count requests fifo", 11577 /* MMU_RL_RQE_FIFO_MEM_ITM1 */ "RQE copy count requests fifo", 11578 /* MMU_RPFAP_BITMAP */ "Redirect Packet-header Free Address Pool Bitmap", 11579 /* MMU_RPFAP_STACK */ "Redirect Packet-header Free Address Pool Stack", 11580 /* MMU_RQE_CELL_FREE_LIST */ "RQE Packet Queue FREE LIST, 3K/8=384 deep", 11581 /* MMU_RQE_CELL_FREE_LIST_ITM0 */ "RQE Packet Queue FREE LIST, 3K/8=384 deep", 11582 /* MMU_RQE_CELL_FREE_LIST_ITM1 */ "RQE Packet Queue FREE LIST, 3K/8=384 deep", 11583 /* MMU_RQE_CELL_LINK_LIST */ "RQE Packet Queue LINK LIST, 3K/8=384 deep", 11584 /* MMU_RQE_CELL_LINK_LIST_ITM0 */ "RQE Packet Queue LINK LIST, 3K/8=384 deep", 11585 /* MMU_RQE_CELL_LINK_LIST_ITM1 */ "RQE Packet Queue LINK LIST, 3K/8=384 deep", 11586 /* MMU_RQE_CELL_QUEUE */ "RQE Cell Queue, 3K/8=384 deep", 11587 /* MMU_RQE_CELL_QUEUE_ITM0 */ "RQE Cell Queue, 3K/8=384 deep", 11588 /* MMU_RQE_CELL_QUEUE_ITM1 */ "RQE Cell Queue, 3K/8=384 deep", 11589 /* MMU_RQE_DEVICE_TO_MMU_PORT_MAPPING */ "Maps ports arrving into the RQE in the Device port domain to the MMU port domain. This memory is addressed by Device port number\nand the contents are MMU port numbers", 11590 /* MMU_RQE_INFOTBL_FREE_LIST */ "Number of total pointers = 3x1024+4x40 = 3232 entries\nFree Address Pool of pointers for RQE INFO Table where each entry holds 2 pointers. So the address space is 3232/2=1616\nThis memory should not be accessed by SW during normal operation.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Ptr 1,0 Ptr 1,0 Ptr 1,0 Ptr 1,0\n========= ================ ======== ...", 11591 /* MMU_RQE_INFOTBL_FREE_LIST_ITM0 */ "Number of total pointers = 3x1024+4x40 = 3232 entries\nFree Address Pool of pointers for RQE INFO Table where each entry holds 2 pointers. So the address space is 3232/2=1616\nThis memory should not be accessed by SW during normal operation.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Ptr 1,0 Ptr 1,0 Ptr 1,0 Ptr 1,0\n========= ================ ======== ...", 11592 /* MMU_RQE_INFOTBL_FREE_LIST_ITM1 */ "Number of total pointers = 3x1024+4x40 = 3232 entries\nFree Address Pool of pointers for RQE INFO Table where each entry holds 2 pointers. So the address space is 3232/2=1616\nThis memory should not be accessed by SW during normal operation.\nNote: ADDR[1:0] = sub-bank number 0-3, bank's are interleaved\nADDR[10:2] SUB-BANK 3 SUB-BANK 1 SUB-BANK 1 SUB-BANK 0\n Ptr 1,0 Ptr 1,0 Ptr 1,0 Ptr 1,0\n========= ================ ======== ...", 11593 /* MMU_RQE_INFO_TABLE */ "RQE Info table, stores MC information received by the CRB and when THDR accepts packet", 11594 /* MMU_RQE_INFO_TABLE_ITM0 */ "RQE Info table, stores MC information received by the CRB and when THDR accepts packet", 11595 /* MMU_RQE_INFO_TABLE_ITM1 */ "RQE Info table, stores MC information received by the CRB and when THDR accepts packet", 11596 /* MMU_RQE_LAST_ACCEPT */ "This table is a working memory used by the RQE to store last accepted copy state information for a given RQE Queues head packet.\nThe table will need to support up to 1 write and 1 read at the same time. Software should not write to this memory during traffic. Table depth is RQE queue depth of 9", 11597 /* MMU_RQE_LAST_ACCEPT_ITM0 */ "This table is a working memory used by the RQE to store last accepted copy state information for a given RQE Queues head packet.\nThe table will need to support up to 1 write and 1 read at the same time. Software should not write to this memory during traffic. Table depth is RQE queue depth of 9", 11598 /* MMU_RQE_LAST_ACCEPT_ITM1 */ "This table is a working memory used by the RQE to store last accepted copy state information for a given RQE Queues head packet.\nThe table will need to support up to 1 write and 1 read at the same time. Software should not write to this memory during traffic. Table depth is RQE queue depth of 9", 11599 /* MMU_RQE_PIPELINE_FCFIFO */ "RQE working memory to hold RQE pipeline data when flow controlled by the SCB", 11600 /* MMU_RQE_PIPELINE_FCFIFO_ITM0 */ "RQE working memory to hold RQE pipeline data when flow controlled by the SCB", 11601 /* MMU_RQE_PIPELINE_FCFIFO_ITM1 */ "RQE working memory to hold RQE pipeline data when flow controlled by the SCB", 11602 /* MMU_RQE_PKTQ_FREE_LIST */ "RQE Packet Queue FREE LIST, 3K/8=384 deep", 11603 /* MMU_RQE_PKTQ_FREE_LIST_ITM0 */ "RQE Packet Queue FREE LIST, 3K/8=384 deep", 11604 /* MMU_RQE_PKTQ_FREE_LIST_ITM1 */ "RQE Packet Queue FREE LIST, 3K/8=384 deep", 11605 /* MMU_RQE_PKTQ_LINK_LIST */ "RQE Packet Queue LINK LIST, 3K/8=384 deep", 11606 /* MMU_RQE_PKTQ_LINK_LIST_ITM0 */ "RQE Packet Queue LINK LIST, 3K/8=384 deep", 11607 /* MMU_RQE_PKTQ_LINK_LIST_ITM1 */ "RQE Packet Queue LINK LIST, 3K/8=384 deep", 11608 /* MMU_RQE_PKT_QUEUE */ "RQE Packet Queue, 3K/8=384 deep", 11609 /* MMU_RQE_PKT_QUEUE_ITM0 */ "RQE Packet Queue, 3K/8=384 deep", 11610 /* MMU_RQE_PKT_QUEUE_ITM1 */ "RQE Packet Queue, 3K/8=384 deep", 11611 /* MMU_RQE_PKT_STATE */ "RQE working memory to track state of each packet replication state - depth is number of RQE queues (9)", 11612 /* MMU_RQE_PKT_STATE_ITM0 */ "RQE working memory to track state of each packet replication state - depth is number of RQE queues (9)", 11613 /* MMU_RQE_PKT_STATE_ITM1 */ "RQE working memory to track state of each packet replication state - depth is number of RQE queues (9)", 11614 /* MMU_RQE_QMGR_FLL */ "Free+Queue Block Link List", 11615 /* MMU_RQE_QMGR_QLL */ "Free+Queue Block Link List", 11616 /* MMU_RQE_QUEUE_OP_NODE_MAP */ "Queue to OP NODE mapping table", 11617 /* MMU_RQE_WORK_QUEUE */ "Store the packet details from ENQ", 11618 /* MMU_SCB_MSCFIFO_BANK0 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11619 /* MMU_SCB_MSCFIFO_BANK1 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11620 /* MMU_SCB_MSCFIFO_BANK2 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11621 /* MMU_SCB_MSCFIFO_BANK3 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11622 /* MMU_SCB_MSCFIFO_BANK4 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11623 /* MMU_SCB_MSCFIFO_BANK5 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11624 /* MMU_SCB_MSCFIFO_BANK0_ITM0 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11625 /* MMU_SCB_MSCFIFO_BANK0_ITM1 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11626 /* MMU_SCB_MSCFIFO_BANK1_ITM0 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11627 /* MMU_SCB_MSCFIFO_BANK1_ITM1 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11628 /* MMU_SCB_MSCFIFO_BANK2_ITM0 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11629 /* MMU_SCB_MSCFIFO_BANK2_ITM1 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11630 /* MMU_SCB_MSCFIFO_BANK3_ITM0 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11631 /* MMU_SCB_MSCFIFO_BANK3_ITM1 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11632 /* MMU_SCB_MSCFIFO_BANK4_ITM0 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11633 /* MMU_SCB_MSCFIFO_BANK4_ITM1 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11634 /* MMU_SCB_MSCFIFO_BANK5_ITM0 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11635 /* MMU_SCB_MSCFIFO_BANK5_ITM1 */ "Memory Bank0 per IPIPE for MSCFIFO shared storage", 11636 /* MMU_SCB_PDB */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11637 /* MMU_SCB_PDB_PIPE0 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11638 /* MMU_SCB_PDB_PIPE1 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11639 /* MMU_SCB_PDB_PIPE2 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11640 /* MMU_SCB_PDB_PIPE3 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11641 /* MMU_SCB_PDB_PIPE4 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11642 /* MMU_SCB_PDB_PIPE5 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11643 /* MMU_SCB_PDB_PIPE6 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11644 /* MMU_SCB_PDB_PIPE7 */ "This memory contains the head and tail pointer information for thd Source Context FIFO of each source port.\nMemory address = port_num[0..19]\nEach Entry contains:\n sop_loc: The location of the SOP cell\n scfifo_tail_offset: The tail offset of each port's source context FIFO\n scfifo_tail_block: The tail block pointer of each port's source context FIFO\n scqentry_tail: The tail pointer of each source context queue entry link list\n scqentry_head: The head pointer of each sou ...", 11645 /* MMU_SCB_SCFIFO_BANK0 */ "Memory Bank0 per IP for SCFIFO shared storage", 11646 /* MMU_SCB_SCFIFO_BANK1 */ "Memory Bank1 per IP for SCFIFO shared storage", 11647 /* MMU_SCB_SCFIFO_BANK2 */ "Memory Bank2 per IP for SCFIFO shared storage", 11648 /* MMU_SCB_SCFIFO_BANK3 */ "Memory Bank3 per IP for SCFIFO shared storage", 11649 /* MMU_SCB_SCFIFO_BANK4 */ "Memory Bank4 per IP for SCFIFO shared storage", 11650 /* MMU_SCB_SCFIFO_BANK5 */ "Memory Bank5 per IP for SCFIFO shared storage", 11651 /* MMU_SCB_SCFIFO_BANK0_PIPE0 */ "Memory Bank0 per IP for SCFIFO shared storage", 11652 /* MMU_SCB_SCFIFO_BANK0_PIPE1 */ "Memory Bank0 per IP for SCFIFO shared storage", 11653 /* MMU_SCB_SCFIFO_BANK0_PIPE2 */ "Memory Bank0 per IP for SCFIFO shared storage", 11654 /* MMU_SCB_SCFIFO_BANK0_PIPE3 */ "Memory Bank0 per IP for SCFIFO shared storage", 11655 /* MMU_SCB_SCFIFO_BANK0_PIPE4 */ "Memory Bank0 per IP for SCFIFO shared storage", 11656 /* MMU_SCB_SCFIFO_BANK0_PIPE5 */ "Memory Bank0 per IP for SCFIFO shared storage", 11657 /* MMU_SCB_SCFIFO_BANK0_PIPE6 */ "Memory Bank0 per IP for SCFIFO shared storage", 11658 /* MMU_SCB_SCFIFO_BANK0_PIPE7 */ "Memory Bank0 per IP for SCFIFO shared storage", 11659 /* MMU_SCB_SCFIFO_BANK1_PIPE0 */ "Memory Bank1 per IP for SCFIFO shared storage", 11660 /* MMU_SCB_SCFIFO_BANK1_PIPE1 */ "Memory Bank1 per IP for SCFIFO shared storage", 11661 /* MMU_SCB_SCFIFO_BANK1_PIPE2 */ "Memory Bank1 per IP for SCFIFO shared storage", 11662 /* MMU_SCB_SCFIFO_BANK1_PIPE3 */ "Memory Bank1 per IP for SCFIFO shared storage", 11663 /* MMU_SCB_SCFIFO_BANK1_PIPE4 */ "Memory Bank1 per IP for SCFIFO shared storage", 11664 /* MMU_SCB_SCFIFO_BANK1_PIPE5 */ "Memory Bank1 per IP for SCFIFO shared storage", 11665 /* MMU_SCB_SCFIFO_BANK1_PIPE6 */ "Memory Bank1 per IP for SCFIFO shared storage", 11666 /* MMU_SCB_SCFIFO_BANK1_PIPE7 */ "Memory Bank1 per IP for SCFIFO shared storage", 11667 /* MMU_SCB_SCFIFO_BANK2_PIPE0 */ "Memory Bank2 per IP for SCFIFO shared storage", 11668 /* MMU_SCB_SCFIFO_BANK2_PIPE1 */ "Memory Bank2 per IP for SCFIFO shared storage", 11669 /* MMU_SCB_SCFIFO_BANK2_PIPE2 */ "Memory Bank2 per IP for SCFIFO shared storage", 11670 /* MMU_SCB_SCFIFO_BANK2_PIPE3 */ "Memory Bank2 per IP for SCFIFO shared storage", 11671 /* MMU_SCB_SCFIFO_BANK2_PIPE4 */ "Memory Bank2 per IP for SCFIFO shared storage", 11672 /* MMU_SCB_SCFIFO_BANK2_PIPE5 */ "Memory Bank2 per IP for SCFIFO shared storage", 11673 /* MMU_SCB_SCFIFO_BANK2_PIPE6 */ "Memory Bank2 per IP for SCFIFO shared storage", 11674 /* MMU_SCB_SCFIFO_BANK2_PIPE7 */ "Memory Bank2 per IP for SCFIFO shared storage", 11675 /* MMU_SCB_SCFIFO_BANK3_PIPE0 */ "Memory Bank3 per IP for SCFIFO shared storage", 11676 /* MMU_SCB_SCFIFO_BANK3_PIPE1 */ "Memory Bank3 per IP for SCFIFO shared storage", 11677 /* MMU_SCB_SCFIFO_BANK3_PIPE2 */ "Memory Bank3 per IP for SCFIFO shared storage", 11678 /* MMU_SCB_SCFIFO_BANK3_PIPE3 */ "Memory Bank3 per IP for SCFIFO shared storage", 11679 /* MMU_SCB_SCFIFO_BANK3_PIPE4 */ "Memory Bank3 per IP for SCFIFO shared storage", 11680 /* MMU_SCB_SCFIFO_BANK3_PIPE5 */ "Memory Bank3 per IP for SCFIFO shared storage", 11681 /* MMU_SCB_SCFIFO_BANK3_PIPE6 */ "Memory Bank3 per IP for SCFIFO shared storage", 11682 /* MMU_SCB_SCFIFO_BANK3_PIPE7 */ "Memory Bank3 per IP for SCFIFO shared storage", 11683 /* MMU_SCB_SCFIFO_BANK4_PIPE0 */ "Memory Bank4 per IP for SCFIFO shared storage", 11684 /* MMU_SCB_SCFIFO_BANK4_PIPE1 */ "Memory Bank4 per IP for SCFIFO shared storage", 11685 /* MMU_SCB_SCFIFO_BANK4_PIPE2 */ "Memory Bank4 per IP for SCFIFO shared storage", 11686 /* MMU_SCB_SCFIFO_BANK4_PIPE3 */ "Memory Bank4 per IP for SCFIFO shared storage", 11687 /* MMU_SCB_SCFIFO_BANK4_PIPE4 */ "Memory Bank4 per IP for SCFIFO shared storage", 11688 /* MMU_SCB_SCFIFO_BANK4_PIPE5 */ "Memory Bank4 per IP for SCFIFO shared storage", 11689 /* MMU_SCB_SCFIFO_BANK4_PIPE6 */ "Memory Bank4 per IP for SCFIFO shared storage", 11690 /* MMU_SCB_SCFIFO_BANK4_PIPE7 */ "Memory Bank4 per IP for SCFIFO shared storage", 11691 /* MMU_SCB_SCFIFO_BANK5_PIPE0 */ "Memory Bank5 per IP for SCFIFO shared storage", 11692 /* MMU_SCB_SCFIFO_BANK5_PIPE1 */ "Memory Bank5 per IP for SCFIFO shared storage", 11693 /* MMU_SCB_SCFIFO_BANK5_PIPE2 */ "Memory Bank5 per IP for SCFIFO shared storage", 11694 /* MMU_SCB_SCFIFO_BANK5_PIPE3 */ "Memory Bank5 per IP for SCFIFO shared storage", 11695 /* MMU_SCB_SCFIFO_BANK5_PIPE4 */ "Memory Bank5 per IP for SCFIFO shared storage", 11696 /* MMU_SCB_SCFIFO_BANK5_PIPE5 */ "Memory Bank5 per IP for SCFIFO shared storage", 11697 /* MMU_SCB_SCFIFO_BANK5_PIPE6 */ "Memory Bank5 per IP for SCFIFO shared storage", 11698 /* MMU_SCB_SCFIFO_BANK5_PIPE7 */ "Memory Bank5 per IP for SCFIFO shared storage", 11699 /* MMU_SCB_SCLL */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11700 /* MMU_SCB_SCLL_PIPE0 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11701 /* MMU_SCB_SCLL_PIPE1 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11702 /* MMU_SCB_SCLL_PIPE2 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11703 /* MMU_SCB_SCLL_PIPE3 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11704 /* MMU_SCB_SCLL_PIPE4 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11705 /* MMU_SCB_SCLL_PIPE5 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11706 /* MMU_SCB_SCLL_PIPE6 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11707 /* MMU_SCB_SCLL_PIPE7 */ "This memory contains the next pointer for the source context queue entry of each source context FIFO\nMemory address = port_num[0..63]\nEach Entry contains:\n next_ptr: The next source context queue entry pointer\n ecc: SECDED across data in this row\n parity: Even partiy across ecc0 and data", 11708 /* MMU_SCB_SCQENTRY */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11709 /* MMU_SCB_SCQENTRY_PIPE0 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11710 /* MMU_SCB_SCQENTRY_PIPE1 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11711 /* MMU_SCB_SCQENTRY_PIPE2 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11712 /* MMU_SCB_SCQENTRY_PIPE3 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11713 /* MMU_SCB_SCQENTRY_PIPE4 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11714 /* MMU_SCB_SCQENTRY_PIPE5 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11715 /* MMU_SCB_SCQENTRY_PIPE6 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11716 /* MMU_SCB_SCQENTRY_PIPE7 */ "This memory contains four contiguous source context FIFO pointers in each memory location\nMemory address = port_num[0..19]\nEach Entry contains:\n scfifo_ptr0: The first of four contiguous source context FIFO pointers\n scfifo_ptr1: The second of four contiguous source context FIFO pointers\n scfifo_ptr2: The third of four contiguous source context FIFO pointers\n scfifo_ptr3: The last of four contiguous source context FIFO pointers\n ecc: ...", 11717 /* MMU_SCB_SCQE_FL */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11718 /* MMU_SCB_SCQE_FL_PIPE0 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11719 /* MMU_SCB_SCQE_FL_PIPE1 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11720 /* MMU_SCB_SCQE_FL_PIPE2 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11721 /* MMU_SCB_SCQE_FL_PIPE3 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11722 /* MMU_SCB_SCQE_FL_PIPE4 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11723 /* MMU_SCB_SCQE_FL_PIPE5 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11724 /* MMU_SCB_SCQE_FL_PIPE6 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11725 /* MMU_SCB_SCQE_FL_PIPE7 */ "This memory contains the bitmap of available Source Context Queue Entry Pointers\nMemory address = port_num[0..7]\nEach Entry contains:\n scqentry_ptr: A bitmap of available Source Context Queue Entry Pointers", 11726 /* MMU_SCB_SCQ_FL */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11727 /* MMU_SCB_SCQ_FL_PIPE0 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11728 /* MMU_SCB_SCQ_FL_PIPE1 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11729 /* MMU_SCB_SCQ_FL_PIPE2 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11730 /* MMU_SCB_SCQ_FL_PIPE3 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11731 /* MMU_SCB_SCQ_FL_PIPE4 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11732 /* MMU_SCB_SCQ_FL_PIPE5 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11733 /* MMU_SCB_SCQ_FL_PIPE6 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11734 /* MMU_SCB_SCQ_FL_PIPE7 */ "This memory contains the bitmap of available Source Context FIFO Block Pointers.\nMemory address = port_num[0..28]\nEach Entry contains:\n scfifo_blk_ptr: A bitmap of available Source Context FIFO Block Pointers", 11735 /* MMU_SCB_SOPSS_BANK0 */ "Memory Bank0 per IP for SOP Supplemental storage", 11736 /* MMU_SCB_SOPSS_BANK1 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11737 /* MMU_SCB_SOPSS_BANK2 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11738 /* MMU_SCB_SOPSS_BANK3 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11739 /* MMU_SCB_SOPSS_BANK4 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11740 /* MMU_SCB_SOPSS_BANK5 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11741 /* MMU_SCB_SOPSS_BANK0_PIPE0 */ "Memory Bank0 per IP for SOP Supplemental storage", 11742 /* MMU_SCB_SOPSS_BANK0_PIPE1 */ "Memory Bank0 per IP for SOP Supplemental storage", 11743 /* MMU_SCB_SOPSS_BANK0_PIPE2 */ "Memory Bank0 per IP for SOP Supplemental storage", 11744 /* MMU_SCB_SOPSS_BANK0_PIPE3 */ "Memory Bank0 per IP for SOP Supplemental storage", 11745 /* MMU_SCB_SOPSS_BANK0_PIPE4 */ "Memory Bank0 per IP for SOP Supplemental storage", 11746 /* MMU_SCB_SOPSS_BANK0_PIPE5 */ "Memory Bank0 per IP for SOP Supplemental storage", 11747 /* MMU_SCB_SOPSS_BANK0_PIPE6 */ "Memory Bank0 per IP for SOP Supplemental storage", 11748 /* MMU_SCB_SOPSS_BANK0_PIPE7 */ "Memory Bank0 per IP for SOP Supplemental storage", 11749 /* MMU_SCB_SOPSS_BANK1_PIPE0 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11750 /* MMU_SCB_SOPSS_BANK1_PIPE1 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11751 /* MMU_SCB_SOPSS_BANK1_PIPE2 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11752 /* MMU_SCB_SOPSS_BANK1_PIPE3 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11753 /* MMU_SCB_SOPSS_BANK1_PIPE4 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11754 /* MMU_SCB_SOPSS_BANK1_PIPE5 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11755 /* MMU_SCB_SOPSS_BANK1_PIPE6 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11756 /* MMU_SCB_SOPSS_BANK1_PIPE7 */ "Memory Bank1 per IP for SOP Supplemental Storage", 11757 /* MMU_SCB_SOPSS_BANK2_PIPE0 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11758 /* MMU_SCB_SOPSS_BANK2_PIPE1 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11759 /* MMU_SCB_SOPSS_BANK2_PIPE2 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11760 /* MMU_SCB_SOPSS_BANK2_PIPE3 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11761 /* MMU_SCB_SOPSS_BANK2_PIPE4 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11762 /* MMU_SCB_SOPSS_BANK2_PIPE5 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11763 /* MMU_SCB_SOPSS_BANK2_PIPE6 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11764 /* MMU_SCB_SOPSS_BANK2_PIPE7 */ "Memory Bank2 per IP for SOP Supplemental Storage", 11765 /* MMU_SCB_SOPSS_BANK3_PIPE0 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11766 /* MMU_SCB_SOPSS_BANK3_PIPE1 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11767 /* MMU_SCB_SOPSS_BANK3_PIPE2 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11768 /* MMU_SCB_SOPSS_BANK3_PIPE3 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11769 /* MMU_SCB_SOPSS_BANK3_PIPE4 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11770 /* MMU_SCB_SOPSS_BANK3_PIPE5 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11771 /* MMU_SCB_SOPSS_BANK3_PIPE6 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11772 /* MMU_SCB_SOPSS_BANK3_PIPE7 */ "Memory Bank3 per IP for SOP Supplemental Storage", 11773 /* MMU_SCB_SOPSS_BANK4_PIPE0 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11774 /* MMU_SCB_SOPSS_BANK4_PIPE1 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11775 /* MMU_SCB_SOPSS_BANK4_PIPE2 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11776 /* MMU_SCB_SOPSS_BANK4_PIPE3 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11777 /* MMU_SCB_SOPSS_BANK4_PIPE4 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11778 /* MMU_SCB_SOPSS_BANK4_PIPE5 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11779 /* MMU_SCB_SOPSS_BANK4_PIPE6 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11780 /* MMU_SCB_SOPSS_BANK4_PIPE7 */ "Memory Bank4 per IP for SOP Supplemental Storage", 11781 /* MMU_SCB_SOPSS_BANK5_PIPE0 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11782 /* MMU_SCB_SOPSS_BANK5_PIPE1 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11783 /* MMU_SCB_SOPSS_BANK5_PIPE2 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11784 /* MMU_SCB_SOPSS_BANK5_PIPE3 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11785 /* MMU_SCB_SOPSS_BANK5_PIPE4 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11786 /* MMU_SCB_SOPSS_BANK5_PIPE5 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11787 /* MMU_SCB_SOPSS_BANK5_PIPE6 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11788 /* MMU_SCB_SOPSS_BANK5_PIPE7 */ "Memory Bank5 per IP for SOP Supplemental Storage", 11789 /* MMU_SCB_SRAF_BANK0 */ "Memory Bank0 of SRAF", 11790 /* MMU_SCB_SRAF_BANK1 */ "Memory Bank1 of SRAF", 11791 /* MMU_SCB_SRAF_BANK2 */ "Memory Bank2 of SRAF", 11792 /* MMU_SCB_SRAF_BANK3 */ "Memory Bank3 of SRAF", 11793 /* MMU_SCB_SRAF_BANK4 */ "Memory Bank4 of SRAF", 11794 /* MMU_SCB_SRAF_BANK5 */ "Memory Bank5 of SRAF", 11795 /* MMU_SCB_SRAF_BANK0_ITM0 */ "Memory Bank0 of SRAF", 11796 /* MMU_SCB_SRAF_BANK0_ITM1 */ "Memory Bank0 of SRAF", 11797 /* MMU_SCB_SRAF_BANK1_ITM0 */ "Memory Bank1 of SRAF", 11798 /* MMU_SCB_SRAF_BANK1_ITM1 */ "Memory Bank1 of SRAF", 11799 /* MMU_SCB_SRAF_BANK2_ITM0 */ "Memory Bank2 of SRAF", 11800 /* MMU_SCB_SRAF_BANK2_ITM1 */ "Memory Bank2 of SRAF", 11801 /* MMU_SCB_SRAF_BANK3_ITM0 */ "Memory Bank3 of SRAF", 11802 /* MMU_SCB_SRAF_BANK3_ITM1 */ "Memory Bank3 of SRAF", 11803 /* MMU_SCB_SRAF_BANK4_ITM0 */ "Memory Bank4 of SRAF", 11804 /* MMU_SCB_SRAF_BANK4_ITM1 */ "Memory Bank4 of SRAF", 11805 /* MMU_SCB_SRAF_BANK5_ITM0 */ "Memory Bank5 of SRAF", 11806 /* MMU_SCB_SRAF_BANK5_ITM1 */ "Memory Bank5 of SRAF", 11807 /* MMU_SCFG_MEM_FAIL_ADDR_64 */ "Memory Fail address FIFO", 11808 /* MMU_SCFG_MEM_FAIL_ADDR_64_SC0 */ "Memory Fail address FIFO", 11809 /* MMU_SCFG_MEM_FAIL_ADDR_64_SC1 */ "Memory Fail address FIFO", 11810 /* MMU_SEDCFG_MEM_FAIL_ADDR_64 */ "Memory Fail address FIFO", 11811 /* MMU_SEDCFG_MEM_FAIL_ADDR_64_SC0 */ "Memory Fail address FIFO", 11812 /* MMU_SEDCFG_MEM_FAIL_ADDR_64_SC1 */ "Memory Fail address FIFO", 11813 /* MMU_SM */ "Signature Matching RAM", 11814 /* MMU_TCB_BUFFER_CELL_DATA_LOWER */ "Transient Capture Buffer lower 220b", 11815 /* MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE0 */ "Transient Capture Buffer lower 220b", 11816 /* MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE1 */ "Transient Capture Buffer lower 220b", 11817 /* MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE2 */ "Transient Capture Buffer lower 220b", 11818 /* MMU_TCB_BUFFER_CELL_DATA_LOWER_XPE3 */ "Transient Capture Buffer lower 220b", 11819 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER */ "Transient Capture Buffer 80B", 11820 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE0 */ "Transient Capture Buffer 80B", 11821 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE1 */ "Transient Capture Buffer 80B", 11822 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE2 */ "Transient Capture Buffer 80B", 11823 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED0_PIPE3 */ "Transient Capture Buffer 80B", 11824 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE0 */ "Transient Capture Buffer 80B", 11825 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE1 */ "Transient Capture Buffer 80B", 11826 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE2 */ "Transient Capture Buffer 80B", 11827 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_LOWER_SED1_PIPE3 */ "Transient Capture Buffer 80B", 11828 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER */ "Transient Capture Buffer 80B", 11829 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE0 */ "Transient Capture Buffer 80B", 11830 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE1 */ "Transient Capture Buffer 80B", 11831 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE2 */ "Transient Capture Buffer 80B", 11832 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED0_PIPE3 */ "Transient Capture Buffer 80B", 11833 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE0 */ "Transient Capture Buffer 80B", 11834 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE1 */ "Transient Capture Buffer 80B", 11835 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE2 */ "Transient Capture Buffer 80B", 11836 /* MMU_TCB_BUFFER_CELL_DATA_SCRATCH_UPPER_SED1_PIPE3 */ "Transient Capture Buffer 80B", 11837 /* MMU_TCB_BUFFER_CELL_DATA_UPPER */ "Transient Capture Buffer upper 420b", 11838 /* MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE0 */ "Transient Capture Buffer upper 420b", 11839 /* MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE1 */ "Transient Capture Buffer upper 420b", 11840 /* MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE2 */ "Transient Capture Buffer upper 420b", 11841 /* MMU_TCB_BUFFER_CELL_DATA_UPPER_XPE3 */ "Transient Capture Buffer upper 420b", 11842 /* MMU_THDI_PORTSP_BST */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11843 /* MMU_THDI_PORTSP_BST_PIPE0 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11844 /* MMU_THDI_PORTSP_BST_PIPE1 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11845 /* MMU_THDI_PORTSP_BST_PIPE2 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11846 /* MMU_THDI_PORTSP_BST_PIPE3 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11847 /* MMU_THDI_PORTSP_BST_PIPE4 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11848 /* MMU_THDI_PORTSP_BST_PIPE5 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11849 /* MMU_THDI_PORTSP_BST_PIPE6 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11850 /* MMU_THDI_PORTSP_BST_PIPE7 */ "This memory contains shadow copies or maximum values of the shared counts that are updated in the Per Port per SP memory array.\nAfter CPU reads a memory location in High Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nEach Entry contains:\n PORTSP0_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP0\n PORTSP1_BST_STAT: Shadow copy or maximum value of shared cells used by Port SP1\n PORTSP2_BST_STAT: Shado ...", 11851 /* MMU_THDI_PORTSP_CONFIG */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11852 /* MMU_THDI_PORTSP_CONFIG1 */ "PORTSP Configuration Shadow Memory1", 11853 /* MMU_THDI_PORTSP_CONFIG1_PIPE0 */ "PORTSP Configuration Shadow Memory1", 11854 /* MMU_THDI_PORTSP_CONFIG1_PIPE1 */ "PORTSP Configuration Shadow Memory1", 11855 /* MMU_THDI_PORTSP_CONFIG1_PIPE2 */ "PORTSP Configuration Shadow Memory1", 11856 /* MMU_THDI_PORTSP_CONFIG1_PIPE3 */ "PORTSP Configuration Shadow Memory1", 11857 /* MMU_THDI_PORTSP_CONFIG1_PIPE4 */ "PORTSP Configuration Shadow Memory1", 11858 /* MMU_THDI_PORTSP_CONFIG1_PIPE5 */ "PORTSP Configuration Shadow Memory1", 11859 /* MMU_THDI_PORTSP_CONFIG1_PIPE6 */ "PORTSP Configuration Shadow Memory1", 11860 /* MMU_THDI_PORTSP_CONFIG1_PIPE7 */ "PORTSP Configuration Shadow Memory1", 11861 /* MMU_THDI_PORTSP_CONFIG_PIPE0 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11862 /* MMU_THDI_PORTSP_CONFIG_PIPE1 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11863 /* MMU_THDI_PORTSP_CONFIG_PIPE2 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11864 /* MMU_THDI_PORTSP_CONFIG_PIPE3 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11865 /* MMU_THDI_PORTSP_CONFIG_PIPE4 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11866 /* MMU_THDI_PORTSP_CONFIG_PIPE5 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11867 /* MMU_THDI_PORTSP_CONFIG_PIPE6 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11868 /* MMU_THDI_PORTSP_CONFIG_PIPE7 */ "This memory contains the per-PortSP buffer configuration parameters for all 4 Service Pools.\nEach Entry contains:\n sp0_min_limit: No. of minimum guaranteed cells in Service Pool-0 that this port is allowed to use\n sp0_share_limit: No. of shared cells in Service Pool-0 that this port is allowed to use\n sp0_resume_limit: Servie Pool-0 static buffer resume limit for this port\n sp1_min_limit: No. of minimum guaranteed ce ...", 11869 /* MMU_THDI_PORTSP_COUNTER */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11870 /* MMU_THDI_PORTSP_COUNTER_PIPE0 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11871 /* MMU_THDI_PORTSP_COUNTER_PIPE1 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11872 /* MMU_THDI_PORTSP_COUNTER_PIPE2 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11873 /* MMU_THDI_PORTSP_COUNTER_PIPE3 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11874 /* MMU_THDI_PORTSP_COUNTER_PIPE4 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11875 /* MMU_THDI_PORTSP_COUNTER_PIPE5 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11876 /* MMU_THDI_PORTSP_COUNTER_PIPE6 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11877 /* MMU_THDI_PORTSP_COUNTER_PIPE7 */ "This memory contains the PortSP Min and PortSP Share counts for all 4 Service Pools.\nEach Entry contains:\n sp0_min_count: No. of minimum guaranteed cells in Service Pool-0 currently used by this port\n sp0_share_count: No. of shared cells in Service Pool-0 currently used by this port\n sp1_min_count: No. of minimum guaranteed cells in Service Pool-1 currently used by this port\n sp1_share_count: No. of shared cells in Service Pool-1 currently used by ...", 11878 /* MMU_THDI_PORT_BST_CONFIG */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11879 /* MMU_THDI_PORT_BST_CONFIG_PIPE0 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11880 /* MMU_THDI_PORT_BST_CONFIG_PIPE1 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11881 /* MMU_THDI_PORT_BST_CONFIG_PIPE2 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11882 /* MMU_THDI_PORT_BST_CONFIG_PIPE3 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11883 /* MMU_THDI_PORT_BST_CONFIG_PIPE4 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11884 /* MMU_THDI_PORT_BST_CONFIG_PIPE5 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11885 /* MMU_THDI_PORT_BST_CONFIG_PIPE6 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11886 /* MMU_THDI_PORT_BST_CONFIG_PIPE7 */ "This memory contains the per-PortPG and per-PortSP BST configurations.\nEach Entry contains:\n pg0_bst_profile_share: BST profile selection for PG0's BST Shared Threshold\n pg0_bst_profile_hdrm: BST profile selection for PG0's BST Headroom Threshold\n pg1_bst_profile_share: BST profile selection for PG1's BST Shared Threshold\n pg1_bst_profile_hdrm: BST profile selection for PG1's BST Headroom Threshold\n pg2_bst_profile_share: BST profile selection for PG2's BST Shared Threshold ...", 11887 /* MMU_THDI_PORT_PG_HDRM_BST */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11888 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE0 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11889 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE1 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11890 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE2 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11891 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE3 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11892 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE4 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11893 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE5 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11894 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE6 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11895 /* MMU_THDI_PORT_PG_HDRM_BST_PIPE7 */ "This memory contains shadow copies or maximum values of the headroom usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG0\n pg1_bst_stat_hdrm: Shadow copy or maximum value of the headroom usage for Port PG1\n pg2_bst_sta ...", 11896 /* MMU_THDI_PORT_PG_HDRM_CONFIG */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11897 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE0 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11898 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE1 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11899 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE2 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11900 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE3 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11901 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE4 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11902 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE5 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11903 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE6 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11904 /* MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE7 */ "This memory contains the per-Port PG Headroom configurations for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_limit: No. of headroom cells reserved for PG0\n pg1_hdrm_limit: No. of headroom cells reserved for PG1\n pg2_hdrm_limit: No. of headroom cells reserved for PG2\n pg3_hdrm_limit: No. of headroom cells reserved for PG3\n pg4_hdrm_limit: No. of headroom cells reserved for PG4\n pg5_hdrm_limit: No. of headroom cells reserved for PG5\n ...", 11905 /* MMU_THDI_PORT_PG_HDRM_COUNTER */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11906 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE0 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11907 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE1 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11908 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE2 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11909 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE3 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11910 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE4 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11911 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE5 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11912 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE6 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11913 /* MMU_THDI_PORT_PG_HDRM_COUNTER_PIPE7 */ "This memory contains the headroom cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_hdrm_count: No. of cells in the local reserved headroom used by PG0\n pg1_hdrm_count: No. of cells in the local reserved headroom used by PG1\n pg2_hdrm_count: No. of cells in the local reserved headroom used by PG2\n pg3_hdrm_count: No. of cells in the local reserved headroom used by PG3\n pg4_hdrm_count: No. of cells in the local reserved he ...", 11914 /* MMU_THDI_PORT_PG_MIN_CONFIG */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11915 /* MMU_THDI_PORT_PG_MIN_CONFIG1 */ "PORT PG Min Configuration Shadow Memory1", 11916 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE0 */ "PORT PG Min Configuration Shadow Memory1", 11917 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE1 */ "PORT PG Min Configuration Shadow Memory1", 11918 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE2 */ "PORT PG Min Configuration Shadow Memory1", 11919 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE3 */ "PORT PG Min Configuration Shadow Memory1", 11920 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE4 */ "PORT PG Min Configuration Shadow Memory1", 11921 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE5 */ "PORT PG Min Configuration Shadow Memory1", 11922 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE6 */ "PORT PG Min Configuration Shadow Memory1", 11923 /* MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE7 */ "PORT PG Min Configuration Shadow Memory1", 11924 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE0 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11925 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE1 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11926 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE2 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11927 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE3 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11928 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE4 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11929 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE5 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11930 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE6 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11931 /* MMU_THDI_PORT_PG_MIN_CONFIG_PIPE7 */ "This memory contains the per-Port PG Min configurations for PG0-PG7.\nEach Entry contains:\n pg0_min_limit: No. of minimum guaranteed cells reserved for PG0\n pg0_use_portsp_min: Use PortSP Min space instead of PG Min space for PG0\n pg1_min_limit: No. of minimum guaranteed cells reserved for PG1\n pg1_use_portsp_min: Use PortSP Min space instead of PG Min space for PG1\n pg2_min_limit: No. of minimum guaranteed cells reserved for PG2\n pg2_use_portsp_min: Use PortSP Min spac ...", 11932 /* MMU_THDI_PORT_PG_MIN_COUNTER */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11933 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE0 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11934 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE1 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11935 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE2 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11936 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE3 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11937 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE4 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11938 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE5 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11939 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE6 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11940 /* MMU_THDI_PORT_PG_MIN_COUNTER_PIPE7 */ "This memory contains the minimum guaranteed cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_min_count: No. of minimum guaranteed cells used by PG0\n pg1_min_count: No. of minimum guaranteed cells used by PG1\n pg2_min_count: No. of minimum guaranteed cells used by PG2\n pg3_min_count: No. of minimum guaranteed cells used by PG3\n pg4_min_count: No. of minimum guaranteed cells used by PG4\n pg5_min_count: No. of ...", 11941 /* MMU_THDI_PORT_PG_RESUME_CONFIG */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11942 /* MMU_THDI_PORT_PG_RESUME_CONFIG1 */ "PORT PG Resume Configuration Shadow Memory1", 11943 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE0 */ "PORT PG Resume Configuration Shadow Memory1", 11944 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE1 */ "PORT PG Resume Configuration Shadow Memory1", 11945 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE2 */ "PORT PG Resume Configuration Shadow Memory1", 11946 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE3 */ "PORT PG Resume Configuration Shadow Memory1", 11947 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE4 */ "PORT PG Resume Configuration Shadow Memory1", 11948 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE5 */ "PORT PG Resume Configuration Shadow Memory1", 11949 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE6 */ "PORT PG Resume Configuration Shadow Memory1", 11950 /* MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE7 */ "PORT PG Resume Configuration Shadow Memory1", 11951 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE0 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11952 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE1 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11953 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE2 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11954 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE3 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11955 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE4 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11956 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE5 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11957 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE6 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11958 /* MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE7 */ "This memory contains the per-Port PG Reset configurations for PG0-PG7.\nEach Entry contains:\n pg0_reset_offset: The value to be subtracted from the XOFF threshold for PG0 before allowing XON control state to resume\n pg0_reset_floor: The floor at which the pg_reset_value for PG0 cannot drop below\n pg1_reset_offset: The value to be subtracted from the XOFF threshold for PG1 before allowing XON control state to resume\n pg1_reset_floor: The floor at which the pg_reset_value for ...", 11959 /* MMU_THDI_PORT_PG_SHARED_BST */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11960 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE0 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11961 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE1 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11962 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE2 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11963 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE3 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11964 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE4 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11965 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE5 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11966 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE6 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11967 /* MMU_THDI_PORT_PG_SHARED_BST_PIPE7 */ "This memory contains shadow copies or maximum values of the shared usage counts that are updated in the Per Port per PG memory array.\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in the config block.\nEach Entry contains:\n pg0_bst_stat_shared: Cells occupied in the shared space for Port PG0\n pg1_bst_stat_shared: Cells occupied in the shared space for Port PG1\n pg2_bst_stat_shared: Cells occupied in the ...", 11968 /* MMU_THDI_PORT_PG_SHARED_CONFIG */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11969 /* MMU_THDI_PORT_PG_SHARED_CONFIG1 */ "PORT PG Shared Configuration Shadow Memory1", 11970 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE0 */ "PORT PG Shared Configuration Shadow Memory1", 11971 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE1 */ "PORT PG Shared Configuration Shadow Memory1", 11972 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE2 */ "PORT PG Shared Configuration Shadow Memory1", 11973 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE3 */ "PORT PG Shared Configuration Shadow Memory1", 11974 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE4 */ "PORT PG Shared Configuration Shadow Memory1", 11975 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE5 */ "PORT PG Shared Configuration Shadow Memory1", 11976 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE6 */ "PORT PG Shared Configuration Shadow Memory1", 11977 /* MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE7 */ "PORT PG Shared Configuration Shadow Memory1", 11978 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE0 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11979 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE1 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11980 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE2 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11981 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE3 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11982 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE4 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11983 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE5 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11984 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE6 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11985 /* MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE7 */ "This memory contains the per-Port PG Share configurations for PG0-PG7.\nEach Entry contains:\n pg0_share_limit: No. of share cells allowed to be consumed by PG0\n pg0_share_dyanmic: Enable dynamic shared limit for PG0\n pg1_share_limit: No. of share cells allowed to be consumed by PG1\n pg1_share_dyanmic: Enable dynamic shared limit for PG1\n pg2_share_limit: No. of share cells allowed to be consumed by PG2\n pg2_share_dyanmic: Enable dynamic shared ...", 11986 /* MMU_THDI_PORT_PG_SHARED_COUNTER */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11987 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE0 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11988 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE1 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11989 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE2 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11990 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE3 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11991 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE4 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11992 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE5 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11993 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE6 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11994 /* MMU_THDI_PORT_PG_SHARED_COUNTER_PIPE7 */ "This memory contains the shared cell use counts for PG0-PG7.\nEach Entry contains:\n pg0_share_count: No. of shared cells used by PG0\n pg1_share_count: No. of shared cells used by PG1\n pg2_share_count: No. of shared cells used by PG2\n pg3_share_count: No. of shared cells used by PG3\n pg4_share_count: No. of shared cells used by PG4\n pg5_share_count: No. of shared cells used by PG5\n pg6_share_count: No ...", 11995 /* MMU_THDM_DB_POOL_MCUC_PKSTAT */ "PKSTAT Stat for shared use count of each service pool.", 11996 /* MMU_THDM_DB_POOL_MCUC_PKSTAT_XPE0 */ "PKSTAT Stat for shared use count of each service pool.", 11997 /* MMU_THDM_DB_POOL_MCUC_PKSTAT_XPE1 */ "PKSTAT Stat for shared use count of each service pool.", 11998 /* MMU_THDM_DB_POOL_MCUC_PKSTAT_XPE2 */ "PKSTAT Stat for shared use count of each service pool.", 11999 /* MMU_THDM_DB_POOL_MCUC_PKSTAT_XPE3 */ "PKSTAT Stat for shared use count of each service pool.", 12000 /* MMU_THDM_DB_PORTSP_BST */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12001 /* MMU_THDM_DB_PORTSP_BST_0 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12002 /* MMU_THDM_DB_PORTSP_BST_1 */ "THDO BST counters for UC queues.", 12003 /* MMU_THDM_DB_PORTSP_BST_XPE0_PIPE0 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12004 /* MMU_THDM_DB_PORTSP_BST_XPE0_PIPE1 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12005 /* MMU_THDM_DB_PORTSP_BST_XPE1_PIPE2 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12006 /* MMU_THDM_DB_PORTSP_BST_XPE1_PIPE3 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12007 /* MMU_THDM_DB_PORTSP_BST_XPE2_PIPE0 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12008 /* MMU_THDM_DB_PORTSP_BST_XPE2_PIPE1 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12009 /* MMU_THDM_DB_PORTSP_BST_XPE3_PIPE2 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12010 /* MMU_THDM_DB_PORTSP_BST_XPE3_PIPE3 */ "THDM BST counters for per port per pool count. Ports 0-33 and 4 service pool. Organization would", 12011 /* MMU_THDM_DB_PORTSP_CONFIG */ "THDO configuration for MC Port Pool.", 12012 /* MMU_THDM_DB_PORTSP_CONFIG_0 */ "THDO configuration for MC Port Pool.", 12013 /* MMU_THDM_DB_PORTSP_CONFIG_1 */ "THDO configuration for MC Port Pool.", 12014 /* MMU_THDM_DB_PORTSP_CONFIG_0A */ "THDO configuration for MC Port Pool.", 12015 /* MMU_THDM_DB_PORTSP_CONFIG_0B */ "THDO configuration for MC Port Pool.", 12016 /* MMU_THDM_DB_PORTSP_CONFIG_0C */ "THDO configuration for MC Port Pool.", 12017 /* MMU_THDM_DB_PORTSP_CONFIG_1A */ "THDO configuration for MC Port Pool.", 12018 /* MMU_THDM_DB_PORTSP_CONFIG_1B */ "THDO configuration for MC Port Pool.", 12019 /* MMU_THDM_DB_PORTSP_CONFIG_1C */ "THDO configuration for MC Port Pool.", 12020 /* MMU_THDM_DB_PORTSP_CONFIG_A */ "THDO configuration for MC Port Pool.", 12021 /* MMU_THDM_DB_PORTSP_CONFIG_A_PIPE0 */ "THDO configuration for MC Port Pool.", 12022 /* MMU_THDM_DB_PORTSP_CONFIG_A_PIPE1 */ "THDO configuration for MC Port Pool.", 12023 /* MMU_THDM_DB_PORTSP_CONFIG_A_PIPE2 */ "THDO configuration for MC Port Pool.", 12024 /* MMU_THDM_DB_PORTSP_CONFIG_A_PIPE3 */ "THDO configuration for MC Port Pool.", 12025 /* MMU_THDM_DB_PORTSP_CONFIG_B */ "THDO configuration for MC Port Pool.", 12026 /* MMU_THDM_DB_PORTSP_CONFIG_B_PIPE0 */ "THDO configuration for MC Port Pool.", 12027 /* MMU_THDM_DB_PORTSP_CONFIG_B_PIPE1 */ "THDO configuration for MC Port Pool.", 12028 /* MMU_THDM_DB_PORTSP_CONFIG_B_PIPE2 */ "THDO configuration for MC Port Pool.", 12029 /* MMU_THDM_DB_PORTSP_CONFIG_B_PIPE3 */ "THDO configuration for MC Port Pool.", 12030 /* MMU_THDM_DB_PORTSP_CONFIG_C */ "THDO configuration for MC Port Pool.", 12031 /* MMU_THDM_DB_PORTSP_CONFIG_C_PIPE0 */ "THDO configuration for MC Port Pool.", 12032 /* MMU_THDM_DB_PORTSP_CONFIG_C_PIPE1 */ "THDO configuration for MC Port Pool.", 12033 /* MMU_THDM_DB_PORTSP_CONFIG_C_PIPE2 */ "THDO configuration for MC Port Pool.", 12034 /* MMU_THDM_DB_PORTSP_CONFIG_C_PIPE3 */ "THDO configuration for MC Port Pool.", 12035 /* MMU_THDM_DB_PORTSP_CONFIG_PIPE0 */ "THDO configuration for MC Port Pool.", 12036 /* MMU_THDM_DB_PORTSP_CONFIG_PIPE1 */ "THDO configuration for MC Port Pool.", 12037 /* MMU_THDM_DB_PORTSP_CONFIG_PIPE2 */ "THDO configuration for MC Port Pool.", 12038 /* MMU_THDM_DB_PORTSP_CONFIG_PIPE3 */ "THDO configuration for MC Port Pool.", 12039 /* MMU_THDM_DB_QUEUE_BST */ "THDO BST counters for UC queues.", 12040 /* MMU_THDM_DB_QUEUE_BST_0 */ "THDO BST counters for UC queues.", 12041 /* MMU_THDM_DB_QUEUE_BST_1 */ "THDO BST counters for UC queues.", 12042 /* MMU_THDM_DB_QUEUE_BST_XPE0_PIPE0 */ "THDO BST counters for UC queues.", 12043 /* MMU_THDM_DB_QUEUE_BST_XPE0_PIPE1 */ "THDO BST counters for UC queues.", 12044 /* MMU_THDM_DB_QUEUE_BST_XPE1_PIPE2 */ "THDO BST counters for UC queues.", 12045 /* MMU_THDM_DB_QUEUE_BST_XPE1_PIPE3 */ "THDO BST counters for UC queues.", 12046 /* MMU_THDM_DB_QUEUE_BST_XPE2_PIPE0 */ "THDO BST counters for UC queues.", 12047 /* MMU_THDM_DB_QUEUE_BST_XPE2_PIPE1 */ "THDO BST counters for UC queues.", 12048 /* MMU_THDM_DB_QUEUE_BST_XPE3_PIPE2 */ "THDO BST counters for UC queues.", 12049 /* MMU_THDM_DB_QUEUE_BST_XPE3_PIPE3 */ "THDO BST counters for UC queues.", 12050 /* MMU_THDM_DB_QUEUE_CONFIG */ "THDO configuration for MC queues.", 12051 /* MMU_THDM_DB_QUEUE_CONFIG_0 */ "THDO configuration for MC queues.", 12052 /* MMU_THDM_DB_QUEUE_CONFIG_1 */ "THDO configuration for MC queues.", 12053 /* MMU_THDM_DB_QUEUE_CONFIG_0A */ "THDM queue configuration for MC queues.", 12054 /* MMU_THDM_DB_QUEUE_CONFIG_0B */ "THDM queue configuration for MC queues.", 12055 /* MMU_THDM_DB_QUEUE_CONFIG_0C */ "THDM queue configuration for MC queues.", 12056 /* MMU_THDM_DB_QUEUE_CONFIG_1A */ "THDM queue configuration for MC queues.", 12057 /* MMU_THDM_DB_QUEUE_CONFIG_1B */ "THDM queue configuration for MC queues.", 12058 /* MMU_THDM_DB_QUEUE_CONFIG_1C */ "THDM queue configuration for MC queues.", 12059 /* MMU_THDM_DB_QUEUE_CONFIG_A */ "THDM queue configuration for MC queues.", 12060 /* MMU_THDM_DB_QUEUE_CONFIG_A_PIPE0 */ "THDM queue configuration for MC queues.", 12061 /* MMU_THDM_DB_QUEUE_CONFIG_A_PIPE1 */ "THDM queue configuration for MC queues.", 12062 /* MMU_THDM_DB_QUEUE_CONFIG_A_PIPE2 */ "THDM queue configuration for MC queues.", 12063 /* MMU_THDM_DB_QUEUE_CONFIG_A_PIPE3 */ "THDM queue configuration for MC queues.", 12064 /* MMU_THDM_DB_QUEUE_CONFIG_B */ "THDM queue configuration for MC queues.", 12065 /* MMU_THDM_DB_QUEUE_CONFIG_B_PIPE0 */ "THDM queue configuration for MC queues.", 12066 /* MMU_THDM_DB_QUEUE_CONFIG_B_PIPE1 */ "THDM queue configuration for MC queues.", 12067 /* MMU_THDM_DB_QUEUE_CONFIG_B_PIPE2 */ "THDM queue configuration for MC queues.", 12068 /* MMU_THDM_DB_QUEUE_CONFIG_B_PIPE3 */ "THDM queue configuration for MC queues.", 12069 /* MMU_THDM_DB_QUEUE_CONFIG_C */ "THDM queue configuration for MC queues.", 12070 /* MMU_THDM_DB_QUEUE_CONFIG_C_PIPE0 */ "THDM queue configuration for MC queues.", 12071 /* MMU_THDM_DB_QUEUE_CONFIG_C_PIPE1 */ "THDM queue configuration for MC queues.", 12072 /* MMU_THDM_DB_QUEUE_CONFIG_C_PIPE2 */ "THDM queue configuration for MC queues.", 12073 /* MMU_THDM_DB_QUEUE_CONFIG_C_PIPE3 */ "THDM queue configuration for MC queues.", 12074 /* MMU_THDM_DB_QUEUE_CONFIG_PIPE0 */ "THDO configuration for MC queues.", 12075 /* MMU_THDM_DB_QUEUE_CONFIG_PIPE1 */ "THDO configuration for MC queues.", 12076 /* MMU_THDM_DB_QUEUE_CONFIG_PIPE2 */ "THDO configuration for MC queues.", 12077 /* MMU_THDM_DB_QUEUE_CONFIG_PIPE3 */ "THDO configuration for MC queues.", 12078 /* MMU_THDM_DB_QUEUE_COUNT */ "THDO counters for UC queues.", 12079 /* MMU_THDM_DB_QUEUE_COUNT_0 */ "THDO counters for UC queues.", 12080 /* MMU_THDM_DB_QUEUE_COUNT_1 */ "THDO counters for MC queues.", 12081 /* MMU_THDM_DB_QUEUE_COUNT_XPE0_PIPE0 */ "THDO counters for UC queues.", 12082 /* MMU_THDM_DB_QUEUE_COUNT_XPE0_PIPE1 */ "THDO counters for UC queues.", 12083 /* MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE2 */ "THDO counters for UC queues.", 12084 /* MMU_THDM_DB_QUEUE_COUNT_XPE1_PIPE3 */ "THDO counters for UC queues.", 12085 /* MMU_THDM_DB_QUEUE_COUNT_XPE2_PIPE0 */ "THDO counters for UC queues.", 12086 /* MMU_THDM_DB_QUEUE_COUNT_XPE2_PIPE1 */ "THDO counters for UC queues.", 12087 /* MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE2 */ "THDO counters for UC queues.", 12088 /* MMU_THDM_DB_QUEUE_COUNT_XPE3_PIPE3 */ "THDO counters for UC queues.", 12089 /* MMU_THDM_DB_QUEUE_OFFSET */ "THDO queue offset for UC queues.", 12090 /* MMU_THDM_DB_QUEUE_OFFSET_0 */ "THDO queue offset for UC queues.", 12091 /* MMU_THDM_DB_QUEUE_OFFSET_1 */ "THDO queue offset for UC queues.", 12092 /* MMU_THDM_DB_QUEUE_OFFSET_0A */ "THDM queue offset config for MC queues.", 12093 /* MMU_THDM_DB_QUEUE_OFFSET_0B */ "THDM queue offset config for MC queues.", 12094 /* MMU_THDM_DB_QUEUE_OFFSET_0C */ "THDM queue offset config for MC queues.", 12095 /* MMU_THDM_DB_QUEUE_OFFSET_1A */ "THDM queue offset config for MC queues.", 12096 /* MMU_THDM_DB_QUEUE_OFFSET_1B */ "THDM queue offset config for MC queues.", 12097 /* MMU_THDM_DB_QUEUE_OFFSET_1C */ "THDM queue offset config for MC queues.", 12098 /* MMU_THDM_DB_QUEUE_OFFSET_A */ "THDM queue offset config for MC queues.", 12099 /* MMU_THDM_DB_QUEUE_OFFSET_A_PIPE0 */ "THDM queue offset config for MC queues.", 12100 /* MMU_THDM_DB_QUEUE_OFFSET_A_PIPE1 */ "THDM queue offset config for MC queues.", 12101 /* MMU_THDM_DB_QUEUE_OFFSET_A_PIPE2 */ "THDM queue offset config for MC queues.", 12102 /* MMU_THDM_DB_QUEUE_OFFSET_A_PIPE3 */ "THDM queue offset config for MC queues.", 12103 /* MMU_THDM_DB_QUEUE_OFFSET_B */ "THDM queue offset config for MC queues.", 12104 /* MMU_THDM_DB_QUEUE_OFFSET_B_PIPE0 */ "THDM queue offset config for MC queues.", 12105 /* MMU_THDM_DB_QUEUE_OFFSET_B_PIPE1 */ "THDM queue offset config for MC queues.", 12106 /* MMU_THDM_DB_QUEUE_OFFSET_B_PIPE2 */ "THDM queue offset config for MC queues.", 12107 /* MMU_THDM_DB_QUEUE_OFFSET_B_PIPE3 */ "THDM queue offset config for MC queues.", 12108 /* MMU_THDM_DB_QUEUE_OFFSET_C */ "THDM queue offset config for MC queues.", 12109 /* MMU_THDM_DB_QUEUE_OFFSET_C_PIPE0 */ "THDM queue offset config for MC queues.", 12110 /* MMU_THDM_DB_QUEUE_OFFSET_C_PIPE1 */ "THDM queue offset config for MC queues.", 12111 /* MMU_THDM_DB_QUEUE_OFFSET_C_PIPE2 */ "THDM queue offset config for MC queues.", 12112 /* MMU_THDM_DB_QUEUE_OFFSET_C_PIPE3 */ "THDM queue offset config for MC queues.", 12113 /* MMU_THDM_DB_QUEUE_OFFSET_PIPE0 */ "THDO queue offset for UC queues.", 12114 /* MMU_THDM_DB_QUEUE_OFFSET_PIPE1 */ "THDO queue offset for UC queues.", 12115 /* MMU_THDM_DB_QUEUE_OFFSET_PIPE2 */ "THDO queue offset for UC queues.", 12116 /* MMU_THDM_DB_QUEUE_OFFSET_PIPE3 */ "THDO queue offset for UC queues.", 12117 /* MMU_THDM_DB_QUEUE_RESUME */ "THDO queue reset value for UC queues.", 12118 /* MMU_THDM_DB_QUEUE_RESUME_0 */ "THDO queue reset value for UC queues.", 12119 /* MMU_THDM_DB_QUEUE_RESUME_1 */ "THDO queue reset value for UC queues.", 12120 /* MMU_THDM_DB_QUEUE_RESUME_XPE0_PIPE0 */ "THDO queue reset value for UC queues.", 12121 /* MMU_THDM_DB_QUEUE_RESUME_XPE0_PIPE1 */ "THDO queue reset value for UC queues.", 12122 /* MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE2 */ "THDO queue reset value for UC queues.", 12123 /* MMU_THDM_DB_QUEUE_RESUME_XPE1_PIPE3 */ "THDO queue reset value for UC queues.", 12124 /* MMU_THDM_DB_QUEUE_RESUME_XPE2_PIPE0 */ "THDO queue reset value for UC queues.", 12125 /* MMU_THDM_DB_QUEUE_RESUME_XPE2_PIPE1 */ "THDO queue reset value for UC queues.", 12126 /* MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE2 */ "THDO queue reset value for UC queues.", 12127 /* MMU_THDM_DB_QUEUE_RESUME_XPE3_PIPE3 */ "THDO queue reset value for UC queues.", 12128 /* MMU_THDM_MCQE_PORTSP_BST */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12129 /* MMU_THDM_MCQE_PORTSP_BST_0 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12130 /* MMU_THDM_MCQE_PORTSP_BST_1 */ "THDO BST counters for UC queues.", 12131 /* MMU_THDM_MCQE_PORTSP_BST_XPE0_PIPE0 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12132 /* MMU_THDM_MCQE_PORTSP_BST_XPE0_PIPE1 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12133 /* MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE2 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12134 /* MMU_THDM_MCQE_PORTSP_BST_XPE1_PIPE3 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12135 /* MMU_THDM_MCQE_PORTSP_BST_XPE2_PIPE0 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12136 /* MMU_THDM_MCQE_PORTSP_BST_XPE2_PIPE1 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12137 /* MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE2 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12138 /* MMU_THDM_MCQE_PORTSP_BST_XPE3_PIPE3 */ "THDM BST counters for per port per pool count. Ports 0-53 and 4 service pool. Organization would", 12139 /* MMU_THDM_MCQE_PORTSP_CONFIG */ "THDO configuration for MC Port Pool.", 12140 /* MMU_THDM_MCQE_PORTSP_CONFIG_0 */ "THDO configuration for MC Port Pool.", 12141 /* MMU_THDM_MCQE_PORTSP_CONFIG_1 */ "THDO configuration for MC Port Pool.", 12142 /* MMU_THDM_MCQE_PORTSP_CONFIG_0A */ "THDO configuration for MC Port Pool.", 12143 /* MMU_THDM_MCQE_PORTSP_CONFIG_0B */ "THDO configuration for MC Port Pool.", 12144 /* MMU_THDM_MCQE_PORTSP_CONFIG_0C */ "THDO configuration for MC Port Pool.", 12145 /* MMU_THDM_MCQE_PORTSP_CONFIG_1A */ "THDO configuration for MC Port Pool.", 12146 /* MMU_THDM_MCQE_PORTSP_CONFIG_1B */ "THDO configuration for MC Port Pool.", 12147 /* MMU_THDM_MCQE_PORTSP_CONFIG_A */ "THDO configuration for MC Port Pool.", 12148 /* MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE0 */ "THDO configuration for MC Port Pool.", 12149 /* MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE1 */ "THDO configuration for MC Port Pool.", 12150 /* MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE2 */ "THDO configuration for MC Port Pool.", 12151 /* MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE3 */ "THDO configuration for MC Port Pool.", 12152 /* MMU_THDM_MCQE_PORTSP_CONFIG_B */ "THDO configuration for MC Port Pool.", 12153 /* MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE0 */ "THDO configuration for MC Port Pool.", 12154 /* MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE1 */ "THDO configuration for MC Port Pool.", 12155 /* MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE2 */ "THDO configuration for MC Port Pool.", 12156 /* MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE3 */ "THDO configuration for MC Port Pool.", 12157 /* MMU_THDM_MCQE_PORTSP_CONFIG_C */ "THDO configuration for MC Port Pool.", 12158 /* MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE0 */ "THDO configuration for MC Port Pool.", 12159 /* MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE1 */ "THDO configuration for MC Port Pool.", 12160 /* MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE2 */ "THDO configuration for MC Port Pool.", 12161 /* MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE3 */ "THDO configuration for MC Port Pool.", 12162 /* MMU_THDM_MCQE_PORTSP_CONFIG_PIPE0 */ "THDO configuration for MC Port Pool.", 12163 /* MMU_THDM_MCQE_PORTSP_CONFIG_PIPE1 */ "THDO configuration for MC Port Pool.", 12164 /* MMU_THDM_MCQE_PORTSP_CONFIG_PIPE2 */ "THDO configuration for MC Port Pool.", 12165 /* MMU_THDM_MCQE_PORTSP_CONFIG_PIPE3 */ "THDO configuration for MC Port Pool.", 12166 /* MMU_THDM_MCQE_QUEUE_BST */ "THDO BST counters for UC queues.", 12167 /* MMU_THDM_MCQE_QUEUE_BST_0 */ "THDO BST counters for UC queues.", 12168 /* MMU_THDM_MCQE_QUEUE_BST_1 */ "THDO BST counters for UC queues.", 12169 /* MMU_THDM_MCQE_QUEUE_BST_XPE0_PIPE0 */ "THDO BST counters for UC queues.", 12170 /* MMU_THDM_MCQE_QUEUE_BST_XPE0_PIPE1 */ "THDO BST counters for UC queues.", 12171 /* MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE2 */ "THDO BST counters for UC queues.", 12172 /* MMU_THDM_MCQE_QUEUE_BST_XPE1_PIPE3 */ "THDO BST counters for UC queues.", 12173 /* MMU_THDM_MCQE_QUEUE_BST_XPE2_PIPE0 */ "THDO BST counters for UC queues.", 12174 /* MMU_THDM_MCQE_QUEUE_BST_XPE2_PIPE1 */ "THDO BST counters for UC queues.", 12175 /* MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE2 */ "THDO BST counters for UC queues.", 12176 /* MMU_THDM_MCQE_QUEUE_BST_XPE3_PIPE3 */ "THDO BST counters for UC queues.", 12177 /* MMU_THDM_MCQE_QUEUE_CONFIG */ "THDO configuration for MC queues.", 12178 /* MMU_THDM_MCQE_QUEUE_CONFIG_0 */ "THDO configuration for MC queues.", 12179 /* MMU_THDM_MCQE_QUEUE_CONFIG_1 */ "THDO configuration for MC queues.", 12180 /* MMU_THDM_MCQE_QUEUE_CONFIG_0A */ "THDM queue configuration for MC queues.", 12181 /* MMU_THDM_MCQE_QUEUE_CONFIG_0B */ "THDM queue configuration for MC queues.", 12182 /* MMU_THDM_MCQE_QUEUE_CONFIG_0C */ "THDM queue configuration for MC queues.", 12183 /* MMU_THDM_MCQE_QUEUE_CONFIG_1A */ "THDM queue configuration for MC queues.", 12184 /* MMU_THDM_MCQE_QUEUE_CONFIG_1B */ "THDM queue configuration for MC queues.", 12185 /* MMU_THDM_MCQE_QUEUE_CONFIG_1C */ "THDM queue configuration for MC queues.", 12186 /* MMU_THDM_MCQE_QUEUE_CONFIG_A */ "THDM queue configuration for MC queues.", 12187 /* MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE0 */ "THDM queue configuration for MC queues.", 12188 /* MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE1 */ "THDM queue configuration for MC queues.", 12189 /* MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE2 */ "THDM queue configuration for MC queues.", 12190 /* MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE3 */ "THDM queue configuration for MC queues.", 12191 /* MMU_THDM_MCQE_QUEUE_CONFIG_B */ "THDM queue configuration for MC queues.", 12192 /* MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE0 */ "THDM queue configuration for MC queues.", 12193 /* MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE1 */ "THDM queue configuration for MC queues.", 12194 /* MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE2 */ "THDM queue configuration for MC queues.", 12195 /* MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE3 */ "THDM queue configuration for MC queues.", 12196 /* MMU_THDM_MCQE_QUEUE_CONFIG_C */ "THDM queue configuration for MC queues.", 12197 /* MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE0 */ "THDM queue configuration for MC queues.", 12198 /* MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE1 */ "THDM queue configuration for MC queues.", 12199 /* MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE2 */ "THDM queue configuration for MC queues.", 12200 /* MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE3 */ "THDM queue configuration for MC queues.", 12201 /* MMU_THDM_MCQE_QUEUE_CONFIG_PIPE0 */ "THDO configuration for MC queues.", 12202 /* MMU_THDM_MCQE_QUEUE_CONFIG_PIPE1 */ "THDO configuration for MC queues.", 12203 /* MMU_THDM_MCQE_QUEUE_CONFIG_PIPE2 */ "THDO configuration for MC queues.", 12204 /* MMU_THDM_MCQE_QUEUE_CONFIG_PIPE3 */ "THDO configuration for MC queues.", 12205 /* MMU_THDM_MCQE_QUEUE_COUNT */ "THDO counters for UC queues.", 12206 /* MMU_THDM_MCQE_QUEUE_COUNT_0 */ "THDO counters for UC queues.", 12207 /* MMU_THDM_MCQE_QUEUE_COUNT_1 */ "THDO counters for UC queues.", 12208 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE0_PIPE0 */ "THDO counters for UC queues.", 12209 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE0_PIPE1 */ "THDO counters for UC queues.", 12210 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE2 */ "THDO counters for UC queues.", 12211 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE1_PIPE3 */ "THDO counters for UC queues.", 12212 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE2_PIPE0 */ "THDO counters for UC queues.", 12213 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE2_PIPE1 */ "THDO counters for UC queues.", 12214 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE2 */ "THDO counters for UC queues.", 12215 /* MMU_THDM_MCQE_QUEUE_COUNT_XPE3_PIPE3 */ "THDO counters for UC queues.", 12216 /* MMU_THDM_MCQE_QUEUE_OFFSET */ "THDO queue offset for UC queues.", 12217 /* MMU_THDM_MCQE_QUEUE_OFFSET_0 */ "THDO queue offset for UC queues.", 12218 /* MMU_THDM_MCQE_QUEUE_OFFSET_1 */ "THDO queue offset for UC queues.", 12219 /* MMU_THDM_MCQE_QUEUE_OFFSET_0A */ "THDM queue offset config for MC queues.", 12220 /* MMU_THDM_MCQE_QUEUE_OFFSET_0B */ "THDM queue offset config for MC queues.", 12221 /* MMU_THDM_MCQE_QUEUE_OFFSET_0C */ "THDM queue offset config for MC queues.", 12222 /* MMU_THDM_MCQE_QUEUE_OFFSET_1A */ "THDM queue offset config for MC queues.", 12223 /* MMU_THDM_MCQE_QUEUE_OFFSET_1B */ "THDM queue offset config for MC queues.", 12224 /* MMU_THDM_MCQE_QUEUE_OFFSET_1C */ "THDM queue offset config for MC queues.", 12225 /* MMU_THDM_MCQE_QUEUE_OFFSET_A */ "THDM queue offset config for MC queues.", 12226 /* MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE0 */ "THDM queue offset config for MC queues.", 12227 /* MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE1 */ "THDM queue offset config for MC queues.", 12228 /* MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE2 */ "THDM queue offset config for MC queues.", 12229 /* MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE3 */ "THDM queue offset config for MC queues.", 12230 /* MMU_THDM_MCQE_QUEUE_OFFSET_B */ "THDM queue offset config for MC queues.", 12231 /* MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE0 */ "THDM queue offset config for MC queues.", 12232 /* MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE1 */ "THDM queue offset config for MC queues.", 12233 /* MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE2 */ "THDM queue offset config for MC queues.", 12234 /* MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE3 */ "THDM queue offset config for MC queues.", 12235 /* MMU_THDM_MCQE_QUEUE_OFFSET_C */ "THDM queue offset config for MC queues.", 12236 /* MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE0 */ "THDM queue offset config for MC queues.", 12237 /* MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE1 */ "THDM queue offset config for MC queues.", 12238 /* MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE2 */ "THDM queue offset config for MC queues.", 12239 /* MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE3 */ "THDM queue offset config for MC queues.", 12240 /* MMU_THDM_MCQE_QUEUE_OFFSET_PIPE0 */ "THDO queue offset for UC queues.", 12241 /* MMU_THDM_MCQE_QUEUE_OFFSET_PIPE1 */ "THDO queue offset for UC queues.", 12242 /* MMU_THDM_MCQE_QUEUE_OFFSET_PIPE2 */ "THDO queue offset for UC queues.", 12243 /* MMU_THDM_MCQE_QUEUE_OFFSET_PIPE3 */ "THDO queue offset for UC queues.", 12244 /* MMU_THDM_MCQE_QUEUE_RESUME */ "THDO queue reset value for UC queues.", 12245 /* MMU_THDM_MCQE_QUEUE_RESUME_0 */ "THDO queue reset value for UC queues.", 12246 /* MMU_THDM_MCQE_QUEUE_RESUME_1 */ "THDO queue reset value for UC queues.", 12247 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE0_PIPE0 */ "THDO queue reset value for UC queues.", 12248 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE0_PIPE1 */ "THDO queue reset value for UC queues.", 12249 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE2 */ "THDO queue reset value for UC queues.", 12250 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE1_PIPE3 */ "THDO queue reset value for UC queues.", 12251 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE2_PIPE0 */ "THDO queue reset value for UC queues.", 12252 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE2_PIPE1 */ "THDO queue reset value for UC queues.", 12253 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE2 */ "THDO queue reset value for UC queues.", 12254 /* MMU_THDM_MCQE_QUEUE_RESUME_XPE3_PIPE3 */ "THDO queue reset value for UC queues.", 12255 /* MMU_THDO_BST_PORT */ "THDO BST counters for UC ports.", 12256 /* MMU_THDO_BST_QGROUP */ "THDO BST counters for UC queue group.", 12257 /* MMU_THDO_BST_QUEUE */ "THDO BST counters for UC queues.", 12258 /* MMU_THDO_BST_SHARED_PORT */ "THDO shared use counters for UC Port SP BST. Indicates instantaneous or high watermark use count for each Ports SPs shared region", 12259 /* MMU_THDO_BST_SHARED_PORTSP_MC */ "THDO shared use counters for MC Port SP BST. Indicates instantaneous or high watermark use count for each MC Ports SPs shared region", 12260 /* MMU_THDO_BST_SHARED_PORTSP_MC_ITM0 */ "THDO shared use counters for MC Port SP BST. Indicates instantaneous or high watermark use count for each MC Ports SPs shared region", 12261 /* MMU_THDO_BST_SHARED_PORTSP_MC_ITM1 */ "THDO shared use counters for MC Port SP BST. Indicates instantaneous or high watermark use count for each MC Ports SPs shared region", 12262 /* MMU_THDO_BST_SHARED_PORTSP_MC_PKTSTAT */ "The MMU_THDO_BST_SHARED_PORTSP_MC counts in packetized stats format 4 locations per address.\nThis memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout.\nCPU writes to the contents of this memory can be done by accessing the MMU_THDO_BST_SHARED_PORTSP_MC memory instead.\nA DMA read to this memory will return four consecutive MMU_THDO_BST_SHARED_PORTSP_MC counts begining with the memory location that is on a boundary of 4.\nFor example, a DMA ...", 12263 /* MMU_THDO_BST_SHARED_PORTSP_MC_PKTSTAT_ITM0 */ "The MMU_THDO_BST_SHARED_PORTSP_MC counts in packetized stats format 4 locations per address.\nThis memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout.\nCPU writes to the contents of this memory can be done by accessing the MMU_THDO_BST_SHARED_PORTSP_MC memory instead.\nA DMA read to this memory will return four consecutive MMU_THDO_BST_SHARED_PORTSP_MC counts begining with the memory location that is on a boundary of 4.\nFor example, a DMA ...", 12264 /* MMU_THDO_BST_SHARED_PORTSP_MC_PKTSTAT_ITM1 */ "The MMU_THDO_BST_SHARED_PORTSP_MC counts in packetized stats format 4 locations per address.\nThis memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout.\nCPU writes to the contents of this memory can be done by accessing the MMU_THDO_BST_SHARED_PORTSP_MC memory instead.\nA DMA read to this memory will return four consecutive MMU_THDO_BST_SHARED_PORTSP_MC counts begining with the memory location that is on a boundary of 4.\nFor example, a DMA ...", 12265 /* MMU_THDO_BST_SHARED_PORT_ITM0 */ "THDO shared use counters for UC Port SP BST. Indicates instantaneous or high watermark use count for each Ports SPs shared region", 12266 /* MMU_THDO_BST_SHARED_PORT_ITM1 */ "THDO shared use counters for UC Port SP BST. Indicates instantaneous or high watermark use count for each Ports SPs shared region", 12267 /* MMU_THDO_BST_TOTAL_QUEUE */ "THDO Queue BST total counts. Indicates instantaneous or high watermark use count for each queue", 12268 /* MMU_THDO_BST_TOTAL_QUEUE_ITM0 */ "THDO Queue BST total counts. Indicates instantaneous or high watermark use count for each queue", 12269 /* MMU_THDO_BST_TOTAL_QUEUE_ITM1 */ "THDO Queue BST total counts. Indicates instantaneous or high watermark use count for each queue", 12270 /* MMU_THDO_BST_TOTAL_QUEUE_PKTSTAT */ "The MMU_THDO_BST_TOTAL_QUEUE counts in packetized stats format 4 locations per address.\nThis memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout.\nCPU writes to the contents of this memory can be done by accessing the MMU_THDO_BST_TOTAL_QUEUE memory instead.\nA DMA read to this memory will return four consecutive MMU_THDO_BST_TOTAL_QUEUE counts begining with the memory location that is on a boundary of 4.\nFor example, a DMA read access to ...", 12271 /* MMU_THDO_BST_TOTAL_QUEUE_PKTSTAT_ITM0 */ "The MMU_THDO_BST_TOTAL_QUEUE counts in packetized stats format 4 locations per address.\nThis memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout.\nCPU writes to the contents of this memory can be done by accessing the MMU_THDO_BST_TOTAL_QUEUE memory instead.\nA DMA read to this memory will return four consecutive MMU_THDO_BST_TOTAL_QUEUE counts begining with the memory location that is on a boundary of 4.\nFor example, a DMA read access to ...", 12272 /* MMU_THDO_BST_TOTAL_QUEUE_PKTSTAT_ITM1 */ "The MMU_THDO_BST_TOTAL_QUEUE counts in packetized stats format 4 locations per address.\nThis memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout.\nCPU writes to the contents of this memory can be done by accessing the MMU_THDO_BST_TOTAL_QUEUE memory instead.\nA DMA read to this memory will return four consecutive MMU_THDO_BST_TOTAL_QUEUE counts begining with the memory location that is on a boundary of 4.\nFor example, a DMA read access to ...", 12273 /* MMU_THDO_CONFIG_0 */ "THDO configuration for UC queues in normal (non-VOQ) ports, MMU ports 5 - 32. Address index = ( port_num - 5 ) * 10 + cos_num.", 12274 /* MMU_THDO_CONFIG_1 */ "THDO configuration for UC queues in normal (non-VOQ) ports, MMU ports 38 - 65. Address index = ( port_num - 38 ) * 10 + cos_num.", 12275 /* MMU_THDO_CONFIG_EX_0 */ "THDO configuration for UC extended queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 74 + ext_queue_num.", 12276 /* MMU_THDO_CONFIG_EX_1 */ "THDO configuration for UC extended queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 74 + ext_queue_num.", 12277 /* MMU_THDO_CONFIG_MC_QGROUP */ "THDO configuration for MC queue groups.", 12278 /* MMU_THDO_CONFIG_PORT */ "THDO configuration for UC queue groups.", 12279 /* MMU_THDO_CONFIG_PORTSP_MC */ "THDO Multicast configuration for egress ports. The table is addressed with a concatenation of MMU_PORT_NUM and service pool with the 2 bit service pool in the lowest 2 bits of the address", 12280 /* MMU_THDO_CONFIG_PORT_UC0 */ "THDO configuration for egress ports. This database should be programmed the same as MMU_THDO_CONFIG_PORT_UC1 and MMU_THDO_CONFIG_PORT_UC2", 12281 /* MMU_THDO_CONFIG_PORT_UC1 */ "THDO configuration for egress ports. This database should be programmed the same as MMU_THDO_CONFIG_PORT_UC0 and MMU_THDO_CONFIG_PORT_UC2. A write to MMU_THDO_CONFIG_PORT_UC0 should automatically update MMU_THDO_CONFIG_PORT_UC1 and MMU_THDO_CONFIG_PORT_UC2", 12282 /* MMU_THDO_CONFIG_PORT_UC2 */ "THDO configuration for egress ports. This database should be programmed the same as MMU_THDO_CONFIG_PORT_UC0 and MMU_THDO_CONFIG_PORT_UC1. A write to MMU_THDO_CONFIG_PORT_UC0 should automatically update MMU_THDO_CONFIG_PORT_UC1 and MMU_THDO_CONFIG_PORT_UC2", 12283 /* MMU_THDO_CONFIG_QGROUP */ "THDO configuration for UC queue groups.", 12284 /* MMU_THDO_CONFIG_QUEUE */ "THDO configuration for UC queues.", 12285 /* MMU_THDO_CONFIG_SP_0 */ "THDO configuration for UC COS queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 10 + cos_num.", 12286 /* MMU_THDO_CONFIG_SP_1 */ "THDO configuration for UC COS queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 10 + cos_num.", 12287 /* MMU_THDO_CONFIG_UC_QGROUP0 */ "THDO configuration for UC queue groups. MMU_THDO_CONFIG_UC_QGROUP0 entries must match MMU_THDO_CONFIG_UC_QGROUP1 and MMU_THDO_CONFIG_UC_QGROUP2 entries", 12288 /* MMU_THDO_CONFIG_UC_QGROUP1 */ "THDO configuration for UC queue groups. MMU_THDO_CONFIG_UC_QGROUP0 entries must match MMU_THDO_CONFIG_UC_QGROUP1 and MMU_THDO_CONFIG_UC_QGROUP2 entries. A write to MMU_THDO_CONFIG_UC_QGROUP0 should automatically update MMU_THDO_CONFIG_UC_QGROUP1 and MMU_THDO_CONFIG_UC_QGROUP2", 12289 /* MMU_THDO_CONFIG_UC_QGROUP2 */ "THDO configuration for UC queue groups. MMU_THDO_CONFIG_UC_QGROUP0 entries must match MMU_THDO_CONFIG_UC_QGROUP1 and MMU_THDO_CONFIG_UC_QGROUP2 entries. A write to MMU_THDO_CONFIG_UC_QGROUP0 should automatically update MMU_THDO_CONFIG_UC_QGROUP1 and MMU_THDO_CONFIG_UC_QGROUP2", 12290 /* MMU_THDO_COUNTER_MC_QGROUP */ "THDO counters for MC queue groups.", 12291 /* MMU_THDO_COUNTER_MC_QGROUP_ITM0 */ "THDO counters for MC queue groups.", 12292 /* MMU_THDO_COUNTER_MC_QGROUP_ITM1 */ "THDO counters for MC queue groups.", 12293 /* MMU_THDO_COUNTER_PORT */ "THDO counters for UC queue groups.", 12294 /* MMU_THDO_COUNTER_PORTSP_MC */ "THDO counters for MC PORTSP shared usage.", 12295 /* MMU_THDO_COUNTER_PORTSP_MC_ITM0 */ "THDO counters for MC PORTSP shared usage.", 12296 /* MMU_THDO_COUNTER_PORTSP_MC_ITM1 */ "THDO counters for MC PORTSP shared usage.", 12297 /* MMU_THDO_COUNTER_PORT_UC */ "THDO Unicast Port SP counters. Shared and total counters per port for each Port SP", 12298 /* MMU_THDO_COUNTER_PORT_UC_ITM0 */ "THDO Unicast Port SP counters. Shared and total counters per port for each Port SP", 12299 /* MMU_THDO_COUNTER_PORT_UC_ITM1 */ "THDO Unicast Port SP counters. Shared and total counters per port for each Port SP", 12300 /* MMU_THDO_COUNTER_QGROUP */ "THDO counters for UC queue groups.", 12301 /* MMU_THDO_COUNTER_QUEUE */ "THDO counters for UC queues.", 12302 /* MMU_THDO_COUNTER_QUEUE_ITM0 */ "THDO counters for queues : Min, shared and total counts", 12303 /* MMU_THDO_COUNTER_QUEUE_ITM1 */ "THDO counters for queues : Min, shared and total counts", 12304 /* MMU_THDO_COUNTER_UC_QGROUP */ "THDO counters for UC queue groups for Min usage", 12305 /* MMU_THDO_COUNTER_UC_QGROUP_ITM0 */ "THDO counters for UC queue groups for Min usage", 12306 /* MMU_THDO_COUNTER_UC_QGROUP_ITM1 */ "THDO counters for UC queue groups for Min usage", 12307 /* MMU_THDO_CTRO_UC_DTYPE */ "THDO CTRO stores UC packet drop_level & drop_resources to be used for reporting to CTRO i/f, on per SRC_CONTEXT basis.", 12308 /* MMU_THDO_CTRO_UC_PKT_STORE */ "THDO CTRO stores UC packet information from SOP to be used for reporting to CTRO i/f, on per SRC_CONTEXT basis.", 12309 /* MMU_THDO_DEVICE_PORT_MAP */ "THDO Device Port Mapping table. Used when passing the Dynamic Load Balancing message", 12310 /* MMU_THDO_OFFSET_0 */ "THDO configuration for UC queues in normal (non-VOQ) ports, MMU ports 5 - 32. Address index = ( port_num - 5 ) * 10 + cos_num.", 12311 /* MMU_THDO_OFFSET_1 */ "THDO configuration for UC queues in normal (non-VOQ) ports, MMU ports 38 - 65. Address index = ( port_num - 38 ) * 10 + cos_num.", 12312 /* MMU_THDO_OFFSET_EX_0 */ "THDO configuration for UC extended queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 74 + ext_queue_num.", 12313 /* MMU_THDO_OFFSET_EX_1 */ "THDO configuration for UC extended queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 74 + ext_queue_num.", 12314 /* MMU_THDO_OFFSET_QGROUP */ "THDO offset for UC queue groups.", 12315 /* MMU_THDO_OFFSET_QUEUE */ "THDO queue offset for UC queues.", 12316 /* MMU_THDO_OFFSET_SP_0 */ "THDO offset configuration for UC COS queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 10 + cos_num.", 12317 /* MMU_THDO_OFFSET_SP_1 */ "THDO offset configuration for UC COS queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 10 + cos_num.", 12318 /* MMU_THDO_OPNCONFIG_CELL */ "THDO configuration for o/p nodes", 12319 /* MMU_THDO_OPNCONFIG_QENTRY */ "THDO configuration for o/p nodes", 12320 /* MMU_THDO_OPNCOUNT_CELL */ "THDO Op-Node total count shadow storage for WRED access for op-node in the range of 0-511", 12321 /* MMU_THDO_OPNOFFSET_CELL */ "THDO configuration for output nodes", 12322 /* MMU_THDO_OPNOFFSET_QENTRY */ "THDO configuration for output nodes", 12323 /* MMU_THDO_OPNSTATUS_CELL */ "THDO Output Node cell count and other status info for output nodes", 12324 /* MMU_THDO_OPNSTATUS_QENTRY */ "THDO Output Node qentry count and other status info for output nodes", 12325 /* MMU_THDO_PORT_DROP_COUNT_MC */ "THDO Multicast Port Drop Counts", 12326 /* MMU_THDO_PORT_DROP_COUNT_MC_ITM0 */ "THDO Multicast Port Drop Counts", 12327 /* MMU_THDO_PORT_DROP_COUNT_MC_ITM1 */ "THDO Multicast Port Drop Counts", 12328 /* MMU_THDO_PORT_DROP_COUNT_UC */ "THDO Unicast Port Drop Counts", 12329 /* MMU_THDO_PORT_DROP_COUNT_UC_ITM0 */ "THDO Unicast Port Drop Counts", 12330 /* MMU_THDO_PORT_DROP_COUNT_UC_ITM1 */ "THDO Unicast Port Drop Counts", 12331 /* MMU_THDO_PORT_QUEUE_SERVICE_POOL */ "Service pools for all queues within a port, required for INTFO message generation", 12332 /* MMU_THDO_PORT_Q_DROP_STATE */ "THDO Drop State for all queues on Port. Min green yellow and red drop states", 12333 /* MMU_THDO_PORT_Q_DROP_STATE_ITM0 */ "THDO Drop State for all queues on Port. Min green yellow and red drop states", 12334 /* MMU_THDO_PORT_Q_DROP_STATE_ITM1 */ "THDO Drop State for all queues on Port. Min green yellow and red drop states", 12335 /* MMU_THDO_PORT_Q_DROP_STATE_MC */ "THDO Drop States for Multicast Queues for Min red yellow and green.", 12336 /* MMU_THDO_PORT_Q_DROP_STATE_MC_ITM0 */ "THDO Drop States for Multicast Queues for Min red yellow and green.", 12337 /* MMU_THDO_PORT_Q_DROP_STATE_MC_ITM1 */ "THDO Drop States for Multicast Queues for Min red yellow and green.", 12338 /* MMU_THDO_PORT_Q_DROP_STATE_MC_SH */ "THDO Drop States for Multicast Queues for min red yellow and green. Shadow memory.", 12339 /* MMU_THDO_PORT_Q_DROP_STATE_MC_SH_ITM0 */ "THDO Drop States for Multicast Queues for min red yellow and green. Shadow memory.", 12340 /* MMU_THDO_PORT_Q_DROP_STATE_MC_SH_ITM1 */ "THDO Drop States for Multicast Queues for min red yellow and green. Shadow memory.", 12341 /* MMU_THDO_PORT_Q_DROP_STATE_SH */ "THDO Drop State for all Unicast queues on Port. Shadow memory", 12342 /* MMU_THDO_PORT_Q_DROP_STATE_SH_ITM0 */ "THDO Drop State for all Unicast queues on Port. Shadow memory", 12343 /* MMU_THDO_PORT_Q_DROP_STATE_SH_ITM1 */ "THDO Drop State for all Unicast queues on Port. Shadow memory", 12344 /* MMU_THDO_PORT_SP_DROP_STATE_MC */ "THDO Drop States for multicast Port-SPs. for green yellow and red", 12345 /* MMU_THDO_PORT_SP_DROP_STATE_MC_ITM0 */ "THDO Drop States for multicast Port-SPs. for green yellow and red", 12346 /* MMU_THDO_PORT_SP_DROP_STATE_MC_ITM1 */ "THDO Drop States for multicast Port-SPs. for green yellow and red", 12347 /* MMU_THDO_PORT_SP_DROP_STATE_MC_SH */ "THDO Drop States for multicast Port-SPs for green yellow and red. Shadow copy", 12348 /* MMU_THDO_PORT_SP_DROP_STATE_MC_SH_ITM0 */ "THDO Drop States for multicast Port-SPs for green yellow and red. Shadow copy", 12349 /* MMU_THDO_PORT_SP_DROP_STATE_MC_SH_ITM1 */ "THDO Drop States for multicast Port-SPs for green yellow and red. Shadow copy", 12350 /* MMU_THDO_PORT_SP_DROP_STATE_UC */ "THDO Drop States for Unicast Port-SPs for green yellow and red", 12351 /* MMU_THDO_PORT_SP_DROP_STATE_UC_ITM0 */ "THDO Drop States for Unicast Port-SPs for green yellow and red", 12352 /* MMU_THDO_PORT_SP_DROP_STATE_UC_ITM1 */ "THDO Drop States for Unicast Port-SPs for green yellow and red", 12353 /* MMU_THDO_QCONFIG_CELL */ "THDO configuration for queues", 12354 /* MMU_THDO_QCONFIG_QENTRY */ "THDO configuration for queues", 12355 /* MMU_THDO_QCOUNT_CELL */ "THDO Queue total count shadow storage for WRED access for queue in the range [0...2047]", 12356 /* MMU_THDO_QCOUNT_CELL_0 */ "THDO Queue total count shadow storage for WRED access for queue in the range [0...2047]", 12357 /* MMU_THDO_QDRPRST_0 */ "THDO cos_queue_drop_state_cell reset value for UC queues in normal (non-VOQ) ports, MMU ports 5 - 32. Address index = ( port_num - 5 ) * 10 + cos_num.", 12358 /* MMU_THDO_QDRPRST_1 */ "THDO cos_queue_drop_state_cell reset value for UC queues in normal (non-VOQ) ports, MMU ports 38 - 65. Address index = ( port_num - 38 ) * 10 + cos_num.", 12359 /* MMU_THDO_QDRPRST_EX_0 */ "THDO cos_queue_drop_state_cell reset value for UC extended queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 74 + ext_queue_num.", 12360 /* MMU_THDO_QDRPRST_EX_1 */ "THDO cos_queue_drop_state_cell reset value for UC extended queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 74 + ext_queue_num.", 12361 /* MMU_THDO_QDRPRST_SP_0 */ "THDO cos_queue_drop_state_cell reset value for UC COS queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 10 + cos_num.", 12362 /* MMU_THDO_QDRPRST_SP_1 */ "THDO cos_queue_drop_state_cell reset value for UC COS queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 10 + cos_num.", 12363 /* MMU_THDO_QOFFSET_CELL */ "THDO reset offset config for queues", 12364 /* MMU_THDO_QOFFSET_QENTRY */ "THDO reset offset config for queues", 12365 /* MMU_THDO_QREDRST_0 */ "THDO cos_red_ds_cell reset value for UC queues in normal (non-VOQ) ports, MMU ports 5 - 32. Address index = ( port_num - 5 ) * 10 + cos_num.", 12366 /* MMU_THDO_QREDRST_1 */ "THDO cos_red_ds_cell reset value for UC queues in normal (non-VOQ) ports, MMU ports 38 - 65. Address index = ( port_num - 38 ) * 10 + cos_num.", 12367 /* MMU_THDO_QREDRST_EX_0 */ "THDO cos_red_ds_cell reset value for UC extended queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 74 + ext_queue_num.", 12368 /* MMU_THDO_QREDRST_EX_1 */ "THDO cos_red_ds_cell reset value for UC extended queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 74 + ext_queue_num.", 12369 /* MMU_THDO_QREDRST_SP_0 */ "THDO cos_red_ds_cell reset value for UC COS queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 10 + cos_num.", 12370 /* MMU_THDO_QREDRST_SP_1 */ "THDO cos_red_ds_cell reset value for UC COS queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 10 + cos_num.", 12371 /* MMU_THDO_QRESET_VALUE_CELL */ "THDO green, yellow and red buffer reset values for queues in the range 0-2047. Used for status collection for diagnostic purposes only.\nCPU read during traffic is guaranteed, but CPU write is opportunistic.", 12372 /* MMU_THDO_QRESET_VALUE_CELL_0 */ "THDO green, yellow and red buffer reset values for queues in the range 0-2047. Used for status collection for diagnostic purposes only.", 12373 /* MMU_THDO_QRESET_VALUE_QENTRY */ "THDO green, yellow and red buffer reset values for queues in the range 0-2047. Used for status collection for diagnostic purposes only.\nCPU read during traffic is guaranteed, but CPU write is opportunistic.", 12374 /* MMU_THDO_QRESET_VALUE_QENTRY_0 */ "THDO green, yellow and red buffer reset values for queues in the range 0-2047. Used for status collection for diagnostic purposes only.", 12375 /* MMU_THDO_QSTATUS_CELL */ "THDO queue cell count and other status info for queues in the range 0-2047',\nCPU read during traffic is guaranteed, but CPU write is opportunistic.", 12376 /* MMU_THDO_QSTATUS_CELL_0 */ "THDO queue cell count and other status info for queues in the range 0-2047", 12377 /* MMU_THDO_QSTATUS_QENTRY */ "THDO queue qentry count and other status info for queues in the range 0-2047\nCPU read during traffic is guaranteed, but CPU write is opportunistic.", 12378 /* MMU_THDO_QSTATUS_QENTRY_0 */ "THDO queue qentry count and other status info for queues in the range 0-2047", 12379 /* MMU_THDO_QUEUE_AVG_ARRIVAL_COUNT */ "THDO Queue average counts for VOQ Fairness", 12380 /* MMU_THDO_QUEUE_AVG_ARRIVAL_COUNT_ITM0 */ "THDO Queue average counts for VOQ Fairness", 12381 /* MMU_THDO_QUEUE_AVG_ARRIVAL_COUNT_ITM1 */ "THDO Queue average counts for VOQ Fairness", 12382 /* MMU_THDO_QUEUE_CONFIG */ "THDO configuration for queues", 12383 /* MMU_THDO_QUEUE_CONFIG1 */ "THDO configuration for queues", 12384 /* MMU_THDO_QUEUE_DROP_COUNT */ "Queue drop counts for packets dropped due to WRED and non WRED plus total bytes dropped", 12385 /* MMU_THDO_QUEUE_DROP_COUNT_ITM0 */ "Queue drop counts for packets dropped due to WRED and non WRED plus total bytes dropped", 12386 /* MMU_THDO_QUEUE_DROP_COUNT_ITM1 */ "Queue drop counts for packets dropped due to WRED and non WRED plus total bytes dropped", 12387 /* MMU_THDO_QUEUE_INST_ARRIVAL_COUNT */ "THDO Queue Instantaneous counts for VOQ Fairness", 12388 /* MMU_THDO_QUEUE_INST_ARRIVAL_COUNT_ITM0 */ "THDO Queue Instantaneous counts for VOQ Fairness", 12389 /* MMU_THDO_QUEUE_INST_ARRIVAL_COUNT_ITM1 */ "THDO Queue Instantaneous counts for VOQ Fairness", 12390 /* MMU_THDO_QUEUE_RESUME_OFFSET */ "THDO configuration for queues. Defines the distance from the threshold to the resume for hysteresis", 12391 /* MMU_THDO_QUEUE_RESUME_OFFSET1 */ "THDO configuration for queues. Defines the distance from the threshold to the resume for hysteresis. Contains the same data as MMU_THDO_QUEUE_RESUME_OFFSET", 12392 /* MMU_THDO_QYELRST_0 */ "THDO cos_yellow_ds_cell reset value for UC queues in normal (non-VOQ) ports, MMU ports 5 - 32. Address index = ( port_num - 5 ) * 10 + cos_num.", 12393 /* MMU_THDO_QYELRST_1 */ "THDO cos_yellow_ds_cell reset value for UC queues in normal (non-VOQ) ports, MMU ports 38 - 65. Address index = ( port_num - 38 ) * 10 + cos_num.", 12394 /* MMU_THDO_QYELRST_EX_0 */ "THDO cos_yellow_ds_cell reset value for UC extended queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 74 + ext_queue_num.", 12395 /* MMU_THDO_QYELRST_EX_1 */ "THDO cos_yellow_ds_cell reset value for UC extended queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 74 + ext_queue_num.", 12396 /* MMU_THDO_QYELRST_SP_0 */ "THDO cos_yellow_ds_cell reset value for UC COS queues in VOQ ports, MMU ports 1 - 4. Address index = ( port_num - 1 ) * 10 + cos_num.", 12397 /* MMU_THDO_QYELRST_SP_1 */ "THDO cos_yellow_ds_cell reset value for UC COS queues in VOQ ports, MMU ports 34 - 37. Address index = ( port_num - 34 ) * 10 + cos_num.", 12398 /* MMU_THDO_Q_TO_QGRP_MAP */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12399 /* MMU_THDO_Q_TO_QGRP_MAPD0 */ "Queue to queue group mapping. Address index = Chip Queue Num. MMU_THDO_Q_TO_QGRP_MAPD2 and MMU_THDO_Q_TO_QGRP_MAPD1 must match MMU_THDO_Q_TO_QGRP_MAPD0", 12400 /* MMU_THDO_Q_TO_QGRP_MAPD1 */ "UC queue to queue group mapping. Address index = Queue. MMU_THDO_Q_TO_QGRP_MAPD0 and MMU_THDO_Q_TO_QGRP_MAPD1 must match", 12401 /* MMU_THDO_Q_TO_QGRP_MAPD2 */ "UC queue to queue group mapping. Address index = Queue. MMU_THDO_Q_TO_QGRP_MAPD0 and MMU_THDO_Q_TO_QGRP_MAPD2 must match", 12402 /* MMU_THDO_RESUME_PORT_MC0 */ "THDO resume configuration for Multiicast egress ports for red yellow and green thresholds.", 12403 /* MMU_THDO_RESUME_PORT_MC1 */ "THDO resume configuration for Multiicast egress ports for red yellow and green thresholds. A write to MMU_THDO_RESUME_PORT_MC0 should automatically update MMU_THDO_RESUME_PORT_MC1 and MMU_THDO_RESUME_PORT_MC2", 12404 /* MMU_THDO_RESUME_PORT_MC2 */ "THDO resume configuration for Multiicast egress ports for red yellow and green thresholds. A write to MMU_THDO_RESUME_PORT_MC0 should automatically update MMU_THDO_RESUME_PORT_MC1 and MMU_THDO_RESUME_PORT_MC2", 12405 /* MMU_THDO_RESUME_PORT_UC0 */ "THDO resume configuration for Unicast egress ports for red yellow and green thresholds.", 12406 /* MMU_THDO_RESUME_PORT_UC1 */ "THDO resume configuration for Unicast egress ports for red yellow and green thresholds. A write to MMU_THDO_RESUME_PORT_UC0 should automatically update MMU_THDO_RESUME_PORT_UC1", 12407 /* MMU_THDO_RESUME_PORT_UC2 */ "THDO resume configuration for Unicast egress ports for red yellow and green thresholds. A write to MMU_THDO_RESUME_PORT_UC0 should automatically update MMU_THDO_RESUME_PORT_UC2", 12408 /* MMU_THDO_RESUME_QGROUP */ "THDO queue reset value for UC queue groups.", 12409 /* MMU_THDO_RESUME_QUEUE */ "THDO queue reset value for UC queues.", 12410 /* MMU_THDO_RESUME_QUEUE_ITM0 */ "Working queue resume thresholds for hysteresis", 12411 /* MMU_THDO_RESUME_QUEUE_ITM1 */ "Working queue resume thresholds for hysteresis", 12412 /* MMU_THDO_SRC_PORT_DROP_COUNT */ "Source Port drop counts in packets", 12413 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE0 */ "Source Port drop counts in packets", 12414 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE1 */ "Source Port drop counts in packets", 12415 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE2 */ "Source Port drop counts in packets", 12416 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE3 */ "Source Port drop counts in packets", 12417 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE4 */ "Source Port drop counts in packets", 12418 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE5 */ "Source Port drop counts in packets", 12419 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE6 */ "Source Port drop counts in packets", 12420 /* MMU_THDO_SRC_PORT_DROP_COUNT_PIPE7 */ "Source Port drop counts in packets", 12421 /* MMU_THDO_TOTAL_COUNTER_QUEUE_SH */ "THDO total counters for queues. shadow copy", 12422 /* MMU_THDO_TOTAL_COUNTER_QUEUE_SH_ITM0 */ "THDO total counters for queues. shadow copy", 12423 /* MMU_THDO_TOTAL_COUNTER_QUEUE_SH_ITM1 */ "THDO total counters for queues. shadow copy", 12424 /* MMU_THDO_TOTAL_PORT_COUNTER */ "THDO counters for UC Ports. Total occupancy for DLB.", 12425 /* MMU_THDO_TOTAL_PORT_COUNTER_ITM0 */ "THDO counters for UC Ports. Total occupancy for DLB.", 12426 /* MMU_THDO_TOTAL_PORT_COUNTER_ITM1 */ "THDO counters for UC Ports. Total occupancy for DLB.", 12427 /* MMU_THDO_TOTAL_PORT_COUNTER_MC */ "THDO counters for MC total port count for DLB.", 12428 /* MMU_THDO_TOTAL_PORT_COUNTER_MC_ITM0 */ "THDO counters for MC total port count for DLB.", 12429 /* MMU_THDO_TOTAL_PORT_COUNTER_MC_ITM1 */ "THDO counters for MC total port count for DLB.", 12430 /* MMU_THDO_TOTAL_PORT_COUNTER_MC_SH */ "THDO counters for MC total port count for DLB.", 12431 /* MMU_THDO_TOTAL_PORT_COUNTER_MC_SH_ITM0 */ "THDO counters for MC total port count for DLB.", 12432 /* MMU_THDO_TOTAL_PORT_COUNTER_MC_SH_ITM1 */ "THDO counters for MC total port count for DLB.", 12433 /* MMU_THDO_TOTAL_PORT_COUNTER_SH */ "THDO counters for UC Ports. Total occupancy for DLB.", 12434 /* MMU_THDO_TOTAL_PORT_COUNTER_SH_ITM0 */ "THDO counters for UC Ports. Total occupancy for DLB.", 12435 /* MMU_THDO_TOTAL_PORT_COUNTER_SH_ITM1 */ "THDO counters for UC Ports. Total occupancy for DLB.", 12436 /* MMU_THDO_WRED_SH_COUNTER_PORT_UC */ "THDO Unicast Port SP shared usage counters, used for WRED calculation", 12437 /* MMU_THDO_WRED_SH_COUNTER_PORT_UC_ITM0 */ "THDO Unicast Port SP shared usage counters, used for WRED calculation", 12438 /* MMU_THDO_WRED_SH_COUNTER_PORT_UC_ITM1 */ "THDO Unicast Port SP shared usage counters, used for WRED calculation", 12439 /* MMU_THDU_BST_PORT */ "THDU BST counters for UC ports.", 12440 /* MMU_THDU_BST_PORT_XPE0_PIPE0 */ "THDU BST counters for UC ports.", 12441 /* MMU_THDU_BST_PORT_XPE0_PIPE1 */ "THDU BST counters for UC ports.", 12442 /* MMU_THDU_BST_PORT_XPE1_PIPE2 */ "THDU BST counters for UC ports.", 12443 /* MMU_THDU_BST_PORT_XPE1_PIPE3 */ "THDU BST counters for UC ports.", 12444 /* MMU_THDU_BST_PORT_XPE2_PIPE0 */ "THDU BST counters for UC ports.", 12445 /* MMU_THDU_BST_PORT_XPE2_PIPE1 */ "THDU BST counters for UC ports.", 12446 /* MMU_THDU_BST_PORT_XPE3_PIPE2 */ "THDU BST counters for UC ports.", 12447 /* MMU_THDU_BST_PORT_XPE3_PIPE3 */ "THDU BST counters for UC ports.", 12448 /* MMU_THDU_BST_QGROUP */ "THDU BST counters for UC queue group.", 12449 /* MMU_THDU_BST_QGROUP_XPE0_PIPE0 */ "THDU BST counters for UC queue group.", 12450 /* MMU_THDU_BST_QGROUP_XPE0_PIPE1 */ "THDU BST counters for UC queue group.", 12451 /* MMU_THDU_BST_QGROUP_XPE1_PIPE2 */ "THDU BST counters for UC queue group.", 12452 /* MMU_THDU_BST_QGROUP_XPE1_PIPE3 */ "THDU BST counters for UC queue group.", 12453 /* MMU_THDU_BST_QGROUP_XPE2_PIPE0 */ "THDU BST counters for UC queue group.", 12454 /* MMU_THDU_BST_QGROUP_XPE2_PIPE1 */ "THDU BST counters for UC queue group.", 12455 /* MMU_THDU_BST_QGROUP_XPE3_PIPE2 */ "THDU BST counters for UC queue group.", 12456 /* MMU_THDU_BST_QGROUP_XPE3_PIPE3 */ "THDU BST counters for UC queue group.", 12457 /* MMU_THDU_BST_QUEUE */ "THDU BST counters for UC queues.", 12458 /* MMU_THDU_BST_QUEUE_XPE0_PIPE0 */ "THDU BST counters for UC queues.", 12459 /* MMU_THDU_BST_QUEUE_XPE0_PIPE1 */ "THDU BST counters for UC queues.", 12460 /* MMU_THDU_BST_QUEUE_XPE1_PIPE2 */ "THDU BST counters for UC queues.", 12461 /* MMU_THDU_BST_QUEUE_XPE1_PIPE3 */ "THDU BST counters for UC queues.", 12462 /* MMU_THDU_BST_QUEUE_XPE2_PIPE0 */ "THDU BST counters for UC queues.", 12463 /* MMU_THDU_BST_QUEUE_XPE2_PIPE1 */ "THDU BST counters for UC queues.", 12464 /* MMU_THDU_BST_QUEUE_XPE3_PIPE2 */ "THDU BST counters for UC queues.", 12465 /* MMU_THDU_BST_QUEUE_XPE3_PIPE3 */ "THDU BST counters for UC queues.", 12466 /* MMU_THDU_CONFIG_PORT */ "THDU configuration for egress ports.", 12467 /* MMU_THDU_CONFIG_PORT0 */ "THDU configuration for egress ports.", 12468 /* MMU_THDU_CONFIG_PORT1 */ "THDU configuration for egress ports.", 12469 /* MMU_THDU_CONFIG_PORT0_PIPE0 */ "THDU configuration for egress ports.", 12470 /* MMU_THDU_CONFIG_PORT0_PIPE1 */ "THDU configuration for egress ports.", 12471 /* MMU_THDU_CONFIG_PORT0_PIPE2 */ "THDU configuration for egress ports.", 12472 /* MMU_THDU_CONFIG_PORT0_PIPE3 */ "THDU configuration for egress ports.", 12473 /* MMU_THDU_CONFIG_PORT1_PIPE0 */ "THDU configuration for egress ports.", 12474 /* MMU_THDU_CONFIG_PORT1_PIPE1 */ "THDU configuration for egress ports.", 12475 /* MMU_THDU_CONFIG_PORT1_PIPE2 */ "THDU configuration for egress ports.", 12476 /* MMU_THDU_CONFIG_PORT1_PIPE3 */ "THDU configuration for egress ports.", 12477 /* MMU_THDU_CONFIG_PORT_PIPE0 */ "THDU configuration for egress ports.", 12478 /* MMU_THDU_CONFIG_PORT_PIPE1 */ "THDU configuration for egress ports.", 12479 /* MMU_THDU_CONFIG_PORT_PIPE2 */ "THDU configuration for egress ports.", 12480 /* MMU_THDU_CONFIG_PORT_PIPE3 */ "THDU configuration for egress ports.", 12481 /* MMU_THDU_CONFIG_QGROUP */ "THDU configuration for UC queue groups.", 12482 /* MMU_THDU_CONFIG_QGROUP0 */ "THDU configuration for UC queue groups.", 12483 /* MMU_THDU_CONFIG_QGROUP1 */ "THDU configuration for UC queue groups.", 12484 /* MMU_THDU_CONFIG_QGROUP0_PIPE0 */ "THDU configuration for UC queue groups.", 12485 /* MMU_THDU_CONFIG_QGROUP0_PIPE1 */ "THDU configuration for UC queue groups.", 12486 /* MMU_THDU_CONFIG_QGROUP0_PIPE2 */ "THDU configuration for UC queue groups.", 12487 /* MMU_THDU_CONFIG_QGROUP0_PIPE3 */ "THDU configuration for UC queue groups.", 12488 /* MMU_THDU_CONFIG_QGROUP1_PIPE0 */ "THDU configuration for UC queue groups.", 12489 /* MMU_THDU_CONFIG_QGROUP1_PIPE1 */ "THDU configuration for UC queue groups.", 12490 /* MMU_THDU_CONFIG_QGROUP1_PIPE2 */ "THDU configuration for UC queue groups.", 12491 /* MMU_THDU_CONFIG_QGROUP1_PIPE3 */ "THDU configuration for UC queue groups.", 12492 /* MMU_THDU_CONFIG_QGROUP_PIPE0 */ "THDU configuration for UC queue groups.", 12493 /* MMU_THDU_CONFIG_QGROUP_PIPE1 */ "THDU configuration for UC queue groups.", 12494 /* MMU_THDU_CONFIG_QGROUP_PIPE2 */ "THDU configuration for UC queue groups.", 12495 /* MMU_THDU_CONFIG_QGROUP_PIPE3 */ "THDU configuration for UC queue groups.", 12496 /* MMU_THDU_CONFIG_QUEUE */ "THDU configuration for UC queues.", 12497 /* MMU_THDU_CONFIG_QUEUE0 */ "THDU configuration for UC queues.", 12498 /* MMU_THDU_CONFIG_QUEUE1 */ "THDU configuration for UC queues.", 12499 /* MMU_THDU_CONFIG_QUEUE0_PIPE0 */ "THDU configuration for UC queues.", 12500 /* MMU_THDU_CONFIG_QUEUE0_PIPE1 */ "THDU configuration for UC queues.", 12501 /* MMU_THDU_CONFIG_QUEUE0_PIPE2 */ "THDU configuration for UC queues.", 12502 /* MMU_THDU_CONFIG_QUEUE0_PIPE3 */ "THDU configuration for UC queues.", 12503 /* MMU_THDU_CONFIG_QUEUE1_PIPE0 */ "THDU configuration for UC queues.", 12504 /* MMU_THDU_CONFIG_QUEUE1_PIPE1 */ "THDU configuration for UC queues.", 12505 /* MMU_THDU_CONFIG_QUEUE1_PIPE2 */ "THDU configuration for UC queues.", 12506 /* MMU_THDU_CONFIG_QUEUE1_PIPE3 */ "THDU configuration for UC queues.", 12507 /* MMU_THDU_CONFIG_QUEUE_PIPE0 */ "THDU configuration for UC queues.", 12508 /* MMU_THDU_CONFIG_QUEUE_PIPE1 */ "THDU configuration for UC queues.", 12509 /* MMU_THDU_CONFIG_QUEUE_PIPE2 */ "THDU configuration for UC queues.", 12510 /* MMU_THDU_CONFIG_QUEUE_PIPE3 */ "THDU configuration for UC queues.", 12511 /* MMU_THDU_COUNTER_PORT */ "THDU counters for UC queue groups.", 12512 /* MMU_THDU_COUNTER_PORT_XPE0_PIPE0 */ "THDU counters for UC queue groups.", 12513 /* MMU_THDU_COUNTER_PORT_XPE0_PIPE1 */ "THDU counters for UC queue groups.", 12514 /* MMU_THDU_COUNTER_PORT_XPE1_PIPE2 */ "THDU counters for UC queue groups.", 12515 /* MMU_THDU_COUNTER_PORT_XPE1_PIPE3 */ "THDU counters for UC queue groups.", 12516 /* MMU_THDU_COUNTER_PORT_XPE2_PIPE0 */ "THDU counters for UC queue groups.", 12517 /* MMU_THDU_COUNTER_PORT_XPE2_PIPE1 */ "THDU counters for UC queue groups.", 12518 /* MMU_THDU_COUNTER_PORT_XPE3_PIPE2 */ "THDU counters for UC queue groups.", 12519 /* MMU_THDU_COUNTER_PORT_XPE3_PIPE3 */ "THDU counters for UC queue groups.", 12520 /* MMU_THDU_COUNTER_QGROUP */ "THDU counters for UC queue groups.", 12521 /* MMU_THDU_COUNTER_QGROUP_XPE0_PIPE0 */ "THDU counters for UC queue groups.", 12522 /* MMU_THDU_COUNTER_QGROUP_XPE0_PIPE1 */ "THDU counters for UC queue groups.", 12523 /* MMU_THDU_COUNTER_QGROUP_XPE1_PIPE2 */ "THDU counters for UC queue groups.", 12524 /* MMU_THDU_COUNTER_QGROUP_XPE1_PIPE3 */ "THDU counters for UC queue groups.", 12525 /* MMU_THDU_COUNTER_QGROUP_XPE2_PIPE0 */ "THDU counters for UC queue groups.", 12526 /* MMU_THDU_COUNTER_QGROUP_XPE2_PIPE1 */ "THDU counters for UC queue groups.", 12527 /* MMU_THDU_COUNTER_QGROUP_XPE3_PIPE2 */ "THDU counters for UC queue groups.", 12528 /* MMU_THDU_COUNTER_QGROUP_XPE3_PIPE3 */ "THDU counters for UC queue groups.", 12529 /* MMU_THDU_COUNTER_QUEUE */ "THDU counters for UC queues.", 12530 /* MMU_THDU_COUNTER_QUEUE_XPE0_PIPE0 */ "THDU counters for UC queues.", 12531 /* MMU_THDU_COUNTER_QUEUE_XPE0_PIPE1 */ "THDU counters for UC queues.", 12532 /* MMU_THDU_COUNTER_QUEUE_XPE1_PIPE2 */ "THDU counters for UC queues.", 12533 /* MMU_THDU_COUNTER_QUEUE_XPE1_PIPE3 */ "THDU counters for UC queues.", 12534 /* MMU_THDU_COUNTER_QUEUE_XPE2_PIPE0 */ "THDU counters for UC queues.", 12535 /* MMU_THDU_COUNTER_QUEUE_XPE2_PIPE1 */ "THDU counters for UC queues.", 12536 /* MMU_THDU_COUNTER_QUEUE_XPE3_PIPE2 */ "THDU counters for UC queues.", 12537 /* MMU_THDU_COUNTER_QUEUE_XPE3_PIPE3 */ "THDU counters for UC queues.", 12538 /* MMU_THDU_OFFSET_QGROUP */ "THDU offset for UC queue groups.", 12539 /* MMU_THDU_OFFSET_QGROUP0 */ "THDU offset for UC queue groups.", 12540 /* MMU_THDU_OFFSET_QGROUP1 */ "THDU offset for UC queue groups.", 12541 /* MMU_THDU_OFFSET_QGROUP0_PIPE0 */ "THDU offset for UC queue groups.", 12542 /* MMU_THDU_OFFSET_QGROUP0_PIPE1 */ "THDU offset for UC queue groups.", 12543 /* MMU_THDU_OFFSET_QGROUP0_PIPE2 */ "THDU offset for UC queue groups.", 12544 /* MMU_THDU_OFFSET_QGROUP0_PIPE3 */ "THDU offset for UC queue groups.", 12545 /* MMU_THDU_OFFSET_QGROUP1_PIPE0 */ "THDU offset for UC queue groups.", 12546 /* MMU_THDU_OFFSET_QGROUP1_PIPE1 */ "THDU offset for UC queue groups.", 12547 /* MMU_THDU_OFFSET_QGROUP1_PIPE2 */ "THDU offset for UC queue groups.", 12548 /* MMU_THDU_OFFSET_QGROUP1_PIPE3 */ "THDU offset for UC queue groups.", 12549 /* MMU_THDU_OFFSET_QGROUP_PIPE0 */ "THDU offset for UC queue groups.", 12550 /* MMU_THDU_OFFSET_QGROUP_PIPE1 */ "THDU offset for UC queue groups.", 12551 /* MMU_THDU_OFFSET_QGROUP_PIPE2 */ "THDU offset for UC queue groups.", 12552 /* MMU_THDU_OFFSET_QGROUP_PIPE3 */ "THDU offset for UC queue groups.", 12553 /* MMU_THDU_OFFSET_QUEUE */ "THDU queue offset for UC queues.", 12554 /* MMU_THDU_OFFSET_QUEUE0 */ "THDU queue offset for UC queues.", 12555 /* MMU_THDU_OFFSET_QUEUE1 */ "THDU queue offset for UC queues.", 12556 /* MMU_THDU_OFFSET_QUEUE0_PIPE0 */ "THDU queue offset for UC queues.", 12557 /* MMU_THDU_OFFSET_QUEUE0_PIPE1 */ "THDU queue offset for UC queues.", 12558 /* MMU_THDU_OFFSET_QUEUE0_PIPE2 */ "THDU queue offset for UC queues.", 12559 /* MMU_THDU_OFFSET_QUEUE0_PIPE3 */ "THDU queue offset for UC queues.", 12560 /* MMU_THDU_OFFSET_QUEUE1_PIPE0 */ "THDU queue offset for UC queues.", 12561 /* MMU_THDU_OFFSET_QUEUE1_PIPE1 */ "THDU queue offset for UC queues.", 12562 /* MMU_THDU_OFFSET_QUEUE1_PIPE2 */ "THDU queue offset for UC queues.", 12563 /* MMU_THDU_OFFSET_QUEUE1_PIPE3 */ "THDU queue offset for UC queues.", 12564 /* MMU_THDU_OFFSET_QUEUE_PIPE0 */ "THDU queue offset for UC queues.", 12565 /* MMU_THDU_OFFSET_QUEUE_PIPE1 */ "THDU queue offset for UC queues.", 12566 /* MMU_THDU_OFFSET_QUEUE_PIPE2 */ "THDU queue offset for UC queues.", 12567 /* MMU_THDU_OFFSET_QUEUE_PIPE3 */ "THDU queue offset for UC queues.", 12568 /* MMU_THDU_QGROUP_TICKET */ "Unicast queue group ticket memory.", 12569 /* MMU_THDU_QUEUE_TICKET */ "Unicast queue ticket memory.", 12570 /* MMU_THDU_Q_TO_QGRP_MAP */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12571 /* MMU_THDU_Q_TO_QGRP_MAP0 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12572 /* MMU_THDU_Q_TO_QGRP_MAP1 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12573 /* MMU_THDU_Q_TO_QGRP_MAP2 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12574 /* MMU_THDU_Q_TO_QGRP_MAP0_PIPE0 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12575 /* MMU_THDU_Q_TO_QGRP_MAP0_PIPE1 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12576 /* MMU_THDU_Q_TO_QGRP_MAP0_PIPE2 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12577 /* MMU_THDU_Q_TO_QGRP_MAP0_PIPE3 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12578 /* MMU_THDU_Q_TO_QGRP_MAP1_PIPE0 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12579 /* MMU_THDU_Q_TO_QGRP_MAP1_PIPE1 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12580 /* MMU_THDU_Q_TO_QGRP_MAP1_PIPE2 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12581 /* MMU_THDU_Q_TO_QGRP_MAP1_PIPE3 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12582 /* MMU_THDU_Q_TO_QGRP_MAP2_PIPE0 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12583 /* MMU_THDU_Q_TO_QGRP_MAP2_PIPE1 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12584 /* MMU_THDU_Q_TO_QGRP_MAP2_PIPE2 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12585 /* MMU_THDU_Q_TO_QGRP_MAP2_PIPE3 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12586 /* MMU_THDU_Q_TO_QGRP_MAP_PIPE0 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12587 /* MMU_THDU_Q_TO_QGRP_MAP_PIPE1 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12588 /* MMU_THDU_Q_TO_QGRP_MAP_PIPE2 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12589 /* MMU_THDU_Q_TO_QGRP_MAP_PIPE3 */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12590 /* MMU_THDU_RESUME_PORT */ "THDU resume configuration for egress ports.", 12591 /* MMU_THDU_RESUME_PORT0 */ "THDU resume configuration for egress ports.", 12592 /* MMU_THDU_RESUME_PORT1 */ "THDU resume configuration for egress ports.", 12593 /* MMU_THDU_RESUME_PORT2 */ "THDU resume configuration for egress ports.", 12594 /* MMU_THDU_RESUME_PORT0_PIPE0 */ "THDU resume configuration for egress ports.", 12595 /* MMU_THDU_RESUME_PORT0_PIPE1 */ "THDU resume configuration for egress ports.", 12596 /* MMU_THDU_RESUME_PORT0_PIPE2 */ "THDU resume configuration for egress ports.", 12597 /* MMU_THDU_RESUME_PORT0_PIPE3 */ "THDU resume configuration for egress ports.", 12598 /* MMU_THDU_RESUME_PORT1_PIPE0 */ "THDU resume configuration for egress ports.", 12599 /* MMU_THDU_RESUME_PORT1_PIPE1 */ "THDU resume configuration for egress ports.", 12600 /* MMU_THDU_RESUME_PORT1_PIPE2 */ "THDU resume configuration for egress ports.", 12601 /* MMU_THDU_RESUME_PORT1_PIPE3 */ "THDU resume configuration for egress ports.", 12602 /* MMU_THDU_RESUME_PORT2_PIPE0 */ "THDU resume configuration for egress ports.", 12603 /* MMU_THDU_RESUME_PORT2_PIPE1 */ "THDU resume configuration for egress ports.", 12604 /* MMU_THDU_RESUME_PORT2_PIPE2 */ "THDU resume configuration for egress ports.", 12605 /* MMU_THDU_RESUME_PORT2_PIPE3 */ "THDU resume configuration for egress ports.", 12606 /* MMU_THDU_RESUME_PORT_PIPE0 */ "THDU resume configuration for egress ports.", 12607 /* MMU_THDU_RESUME_PORT_PIPE1 */ "THDU resume configuration for egress ports.", 12608 /* MMU_THDU_RESUME_PORT_PIPE2 */ "THDU resume configuration for egress ports.", 12609 /* MMU_THDU_RESUME_PORT_PIPE3 */ "THDU resume configuration for egress ports.", 12610 /* MMU_THDU_RESUME_QGROUP */ "THDU queue reset value for UC queue groups.", 12611 /* MMU_THDU_RESUME_QGROUP_XPE0_PIPE0 */ "THDU queue reset value for UC queue groups.", 12612 /* MMU_THDU_RESUME_QGROUP_XPE0_PIPE1 */ "THDU queue reset value for UC queue groups.", 12613 /* MMU_THDU_RESUME_QGROUP_XPE1_PIPE2 */ "THDU queue reset value for UC queue groups.", 12614 /* MMU_THDU_RESUME_QGROUP_XPE1_PIPE3 */ "THDU queue reset value for UC queue groups.", 12615 /* MMU_THDU_RESUME_QGROUP_XPE2_PIPE0 */ "THDU queue reset value for UC queue groups.", 12616 /* MMU_THDU_RESUME_QGROUP_XPE2_PIPE1 */ "THDU queue reset value for UC queue groups.", 12617 /* MMU_THDU_RESUME_QGROUP_XPE3_PIPE2 */ "THDU queue reset value for UC queue groups.", 12618 /* MMU_THDU_RESUME_QGROUP_XPE3_PIPE3 */ "THDU queue reset value for UC queue groups.", 12619 /* MMU_THDU_RESUME_QUEUE */ "THDU queue reset value for UC queues.", 12620 /* MMU_THDU_RESUME_QUEUE_XPE0_PIPE0 */ "THDU queue reset value for UC queues.", 12621 /* MMU_THDU_RESUME_QUEUE_XPE0_PIPE1 */ "THDU queue reset value for UC queues.", 12622 /* MMU_THDU_RESUME_QUEUE_XPE1_PIPE2 */ "THDU queue reset value for UC queues.", 12623 /* MMU_THDU_RESUME_QUEUE_XPE1_PIPE3 */ "THDU queue reset value for UC queues.", 12624 /* MMU_THDU_RESUME_QUEUE_XPE2_PIPE0 */ "THDU queue reset value for UC queues.", 12625 /* MMU_THDU_RESUME_QUEUE_XPE2_PIPE1 */ "THDU queue reset value for UC queues.", 12626 /* MMU_THDU_RESUME_QUEUE_XPE3_PIPE2 */ "THDU queue reset value for UC queues.", 12627 /* MMU_THDU_RESUME_QUEUE_XPE3_PIPE3 */ "THDU queue reset value for UC queues.", 12628 /* MMU_THDU_UCQ_STATS */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12629 /* MMU_THDU_UCQ_STATS_TABLE */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12630 /* MMU_THDU_UCQ_STATS_TABLE_XPE0_PIPE0 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12631 /* MMU_THDU_UCQ_STATS_TABLE_XPE0_PIPE1 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12632 /* MMU_THDU_UCQ_STATS_TABLE_XPE1_PIPE2 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12633 /* MMU_THDU_UCQ_STATS_TABLE_XPE1_PIPE3 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12634 /* MMU_THDU_UCQ_STATS_TABLE_XPE2_PIPE0 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12635 /* MMU_THDU_UCQ_STATS_TABLE_XPE2_PIPE1 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12636 /* MMU_THDU_UCQ_STATS_TABLE_XPE3_PIPE2 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12637 /* MMU_THDU_UCQ_STATS_TABLE_XPE3_PIPE3 */ "This memory is intended for DMA read accesses only. Attempting to write to this memory will result in a SBUS Timeout. CPU writes to the contents of this memory can be done by accessing the MMU_THDU_UCQ_STATS memory instead. A DMA read to this memory will return four consecutive UCQ counts begining with the memory location that is on a boundary of 4. For example, a DMA read access to any of the following addresses (0x11 or 0x12 or 0x13) will return the UCQ counts at locations 0x10,0x11,0x12,0 ...", 12638 /* MMU_THDU_UCQ_STATS_XPE0_PIPE0 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12639 /* MMU_THDU_UCQ_STATS_XPE0_PIPE1 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12640 /* MMU_THDU_UCQ_STATS_XPE1_PIPE2 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12641 /* MMU_THDU_UCQ_STATS_XPE1_PIPE3 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12642 /* MMU_THDU_UCQ_STATS_XPE2_PIPE0 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12643 /* MMU_THDU_UCQ_STATS_XPE2_PIPE1 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12644 /* MMU_THDU_UCQ_STATS_XPE3_PIPE2 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12645 /* MMU_THDU_UCQ_STATS_XPE3_PIPE3 */ "This memory is intended for accesses to the packetized statistics memory for debugging purposes. Both CPU reads and CPU writes to the packetized statistics memory can be achieved by issuing CPU read or write operations to this memory.", 12646 /* MMU_THDU_XPIPE_BST_PORT */ "THDU BST counters for UC ports. This is for ports in X pipe.", 12647 /* MMU_THDU_XPIPE_BST_QGROUP */ "THDU BST counters for UC queue group. This is for queue groups in X pipe.", 12648 /* MMU_THDU_XPIPE_BST_QUEUE */ "THDU BST counters for UC queues. This is for queues in X pipe.", 12649 /* MMU_THDU_XPIPE_CONFIG_PORT */ "THDU configuration for UC queue groups. This is for ports in X pipe.", 12650 /* MMU_THDU_XPIPE_CONFIG_QGROUP */ "THDU configuration for UC queue groups. This is for queue groups in X pipe.", 12651 /* MMU_THDU_XPIPE_CONFIG_QUEUE */ "THDU configuration for UC queues. This is for queues in X pipe.", 12652 /* MMU_THDU_XPIPE_COUNTER_PORT */ "THDU counters for UC queue groups. This is for ports in X pipe.", 12653 /* MMU_THDU_XPIPE_COUNTER_QGROUP */ "THDU counters for UC queue groups. This is for queue groups in X pipe.", 12654 /* MMU_THDU_XPIPE_COUNTER_QUEUE */ "THDU counters for UC queues. This is for queues in X pipe.", 12655 /* MMU_THDU_XPIPE_OFFSET_QGROUP */ "THDU offset for UC queue groups. This is for queue groups in X pipe.", 12656 /* MMU_THDU_XPIPE_OFFSET_QUEUE */ "THDU queue offset for UC queues. This is for queues in X pipe.", 12657 /* MMU_THDU_XPIPE_Q_TO_QGRP_MAP */ "UC queue to queue group mapping. Address index = uc_queue_num. This is for queues in X pipe.", 12658 /* MMU_THDU_XPIPE_Q_TO_QGRP_MAP_0 */ "First physical copy of MMU_THDU_Q_TO_QGRP_MAP", 12659 /* MMU_THDU_XPIPE_Q_TO_QGRP_MAP_1 */ "Second physical copy of MMU_THDU_Q_TO_QGRP_MAP", 12660 /* MMU_THDU_XPIPE_RESUME_PORT */ "THDU configuration for UC queue groups. This is for ports in X pipe.", 12661 /* MMU_THDU_XPIPE_RESUME_PORT_0 */ "First physical copy of MMU_THDU_RESUME_PORT", 12662 /* MMU_THDU_XPIPE_RESUME_PORT_1 */ "Second physical copy of MMU_THDU_RESUME_PORT", 12663 /* MMU_THDU_XPIPE_RESUME_QGROUP */ "THDU queue reset value for UC queue groups. This is for queue groups in X pipe.", 12664 /* MMU_THDU_XPIPE_RESUME_QUEUE */ "THDU queue reset value for UC queues. This is for queues in X pipe.", 12665 /* MMU_THDU_YPIPE_BST_PORT */ "THDU BST counters for UC ports.", 12666 /* MMU_THDU_YPIPE_BST_QGROUP */ "THDU BST counters for UC queue group.", 12667 /* MMU_THDU_YPIPE_BST_QUEUE */ "THDU BST counters for UC queues.", 12668 /* MMU_THDU_YPIPE_CONFIG_PORT */ "THDU configuration for UC queue groups.", 12669 /* MMU_THDU_YPIPE_CONFIG_QGROUP */ "THDU configuration for UC queue groups.", 12670 /* MMU_THDU_YPIPE_CONFIG_QUEUE */ "THDU configuration for UC queues.", 12671 /* MMU_THDU_YPIPE_COUNTER_PORT */ "THDU counters for UC queue groups.", 12672 /* MMU_THDU_YPIPE_COUNTER_QGROUP */ "THDU counters for UC queue groups.", 12673 /* MMU_THDU_YPIPE_COUNTER_QUEUE */ "THDU counters for UC queues.", 12674 /* MMU_THDU_YPIPE_OFFSET_QGROUP */ "THDU offset for UC queue groups.", 12675 /* MMU_THDU_YPIPE_OFFSET_QUEUE */ "THDU queue offset for UC queues.", 12676 /* MMU_THDU_YPIPE_Q_TO_QGRP_MAP */ "UC queue to queue group mapping. Address index = uc_queue_num.", 12677 /* MMU_THDU_YPIPE_Q_TO_QGRP_MAP_0 */ "First physical copy of MMU_THDU_YPIPE_Q_TO_QGRP_MAP", 12678 /* MMU_THDU_YPIPE_Q_TO_QGRP_MAP_1 */ "Second physical copy of MMU_THDU_YPIPE_Q_TO_QGRP_MAP", 12679 /* MMU_THDU_YPIPE_RESUME_PORT */ "THDU configuration for UC queue groups.", 12680 /* MMU_THDU_YPIPE_RESUME_PORT_0 */ "First physical copy of MMU_THDU_YPIPE_RESUME_PORT", 12681 /* MMU_THDU_YPIPE_RESUME_PORT_1 */ "Second physical copy of MMU_THDU_YPIPE_RESUME_PORT", 12682 /* MMU_THDU_YPIPE_RESUME_QGROUP */ "THDU queue reset value for UC queue groups.", 12683 /* MMU_THDU_YPIPE_RESUME_QUEUE */ "THDU queue reset value for UC queues.", 12684 /* MMU_TOQRDE */ "TOQRDE", 12685 /* MMU_TOQ_CQEB0 */ "Block of 4 CQEBentries (CQE), each CQE holding one cell/packet descriptor in the list of packets in a queue , DEQ0 copy", 12686 /* MMU_TOQ_CQEB1 */ "Block of 4 CQEBentries (CQE), each CQE holding one cell/packet descriptor in the list of packets in a queue, DEQ1 COPY", 12687 /* MMU_TOQ_CQEB0_ITM0 */ "Block of 4 CQEBentries (CQE), each CQE holding one cell/packet descriptor in the list of packets in a queue , DEQ0 copy", 12688 /* MMU_TOQ_CQEB0_ITM1 */ "Block of 4 CQEBentries (CQE), each CQE holding one cell/packet descriptor in the list of packets in a queue , DEQ0 copy", 12689 /* MMU_TOQ_CQEB1_ITM0 */ "Block of 4 CQEBentries (CQE), each CQE holding one cell/packet descriptor in the list of packets in a queue, DEQ1 COPY", 12690 /* MMU_TOQ_CQEB1_ITM1 */ "Block of 4 CQEBentries (CQE), each CQE holding one cell/packet descriptor in the list of packets in a queue, DEQ1 COPY", 12691 /* MMU_TOQ_CQEBN */ "Linking structure that stitch the linked list of CQEB blocks", 12692 /* MMU_TOQ_CQEBN_ITM0 */ "Linking structure that stitch the linked list of CQEB blocks", 12693 /* MMU_TOQ_CQEBN_ITM1 */ "Linking structure that stitch the linked list of CQEB blocks", 12694 /* MMU_TOQ_CQEB_FAP */ "Maintain Free Pool of pointers per CQEB bank", 12695 /* MMU_TOQ_CQEB_FAP_ITM0 */ "Maintain Free Pool of pointers per CQEB bank", 12696 /* MMU_TOQ_CQEB_FAP_ITM1 */ "Maintain Free Pool of pointers per CQEB bank", 12697 /* MMU_TOQ_EOPE_TBL */ "TOQ EOPE Database, memory : Hold EOPE state for external buffer usage tracking. No CPU access in traffic", 12698 /* MMU_TOQ_IPMC_GROUP_TBL0 */ "TOQ IPMC VLAN Group Table 0 for port#1-5", 12699 /* MMU_TOQ_IPMC_GROUP_TBL1 */ "TOQ IPMC VLAN Group Table 1 for port#6-10", 12700 /* MMU_TOQ_IPMC_GROUP_TBL2 */ "TOQ IPMC VLAN Group Table 2 for port#11-15", 12701 /* MMU_TOQ_IPMC_GROUP_TBL3 */ "TOQ IPMC VLAN Group Table 3 for port#16-20", 12702 /* MMU_TOQ_IPMC_GROUP_TBL4 */ "TOQ IPMC VLAN Group Table 4 for port#21-25", 12703 /* MMU_TOQ_IPMC_GROUP_TBL5 */ "TOQ IPMC VLAN Group Table 5 for port#26-30", 12704 /* MMU_TOQ_IPMC_GROUP_TBL6 */ "TOQ IPMC VLAN Group Table 6 for port#31-35", 12705 /* MMU_TOQ_OQS_RECEPTION_FIFO */ "OQS Reception FIFO in TOQ", 12706 /* MMU_TOQ_OQS_RECEPTION_FIFO_ITM0 */ "OQS Reception FIFO in TOQ", 12707 /* MMU_TOQ_OQS_RECEPTION_FIFO_ITM1 */ "OQS Reception FIFO in TOQ", 12708 /* MMU_TOQ_OQS_STAGING_MEM */ "OQS Staging Memory in TOQ", 12709 /* MMU_TOQ_OQS_STAGING_MEM_ITM0 */ "OQS Staging Memory in TOQ", 12710 /* MMU_TOQ_OQS_STAGING_MEM_ITM1 */ "OQS Staging Memory in TOQ", 12711 /* MMU_TOQ_PORT_STATE_MEM */ "TOQ PORT_STATE Database, memory : Dbug access only for 4K queues midpacket state info. No access in traffic", 12712 /* MMU_TOQ_QPACK_MODE */ "TOQ QPACK_MODE. Per queue configuration, 16 Queues per address, so memory is addressed by QID[11:4] and bits within memory by QID[3:0]", 12713 /* MMU_TOQ_STATE_MEM0 */ "TOQ STATE Database, mem0", 12714 /* MMU_TOQ_STATE_MEM1 */ "TOQ STATE Database, mem1", 12715 /* MMU_TOQ_VOQDB */ "VOQ Database storing the queue management head-tail context", 12716 /* MMU_TOQ_VOQDB_HEAD_PARTIAL */ "Stores Up to 3 CQE cell information for the head of the queue", 12717 /* MMU_TOQ_VOQDB_HEAD_PARTIAL_ITM0 */ "Stores Up to 3 CQE cell information for the head of the queue", 12718 /* MMU_TOQ_VOQDB_HEAD_PARTIAL_ITM1 */ "Stores Up to 3 CQE cell information for the head of the queue", 12719 /* MMU_TOQ_VOQDB_ITM0 */ "VOQ Database storing the queue management head-tail context", 12720 /* MMU_TOQ_VOQDB_ITM1 */ "VOQ Database storing the queue management head-tail context", 12721 /* MMU_TOQ_VOQDB_TAIL_PARTIAL */ "Stores Up to 3 CQE cell information for the tail of the queue", 12722 /* MMU_TOQ_VOQDB_TAIL_PARTIAL_ITM0 */ "Stores Up to 3 CQE cell information for the tail of the queue", 12723 /* MMU_TOQ_VOQDB_TAIL_PARTIAL_ITM1 */ "Stores Up to 3 CQE cell information for the tail of the queue", 12724 /* MMU_TOQ_VOQ_HEAD_DB */ "Store 16 EOP bitmap and 4 CQEB addresses corresponding to head 16 cells of every VoQ", 12725 /* MMU_TOQ_VOQ_HEAD_DB_ITM0 */ "Store 16 EOP bitmap and 4 CQEB addresses corresponding to head 16 cells of every VoQ", 12726 /* MMU_TOQ_VOQ_HEAD_DB_ITM1 */ "Store 16 EOP bitmap and 4 CQEB addresses corresponding to head 16 cells of every VoQ", 12727 /* MMU_UCQDB0 */ "UCQDB0", 12728 /* MMU_UCQDB1 */ "UCQDB1", 12729 /* MMU_UCQDB_X */ "Unicast queue database. This is a working FIFO maintained by hardware.", 12730 /* MMU_UCQDB_X_XPE0 */ "Unicast queue database. This is a working FIFO maintained by hardware.", 12731 /* MMU_UCQDB_X_XPE1 */ "Unicast queue database. This is a working FIFO maintained by hardware.", 12732 /* MMU_UCQDB_X_XPE2 */ "Unicast queue database. This is a working FIFO maintained by hardware.", 12733 /* MMU_UCQDB_X_XPE3 */ "Unicast queue database. This is a working FIFO maintained by hardware.", 12734 /* MMU_UCQDB_Y */ "Multicast queue database. This is a working FIFO maintained by hardware.", 12735 /* MMU_UCQDB_Y_XPE0 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 12736 /* MMU_UCQDB_Y_XPE1 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 12737 /* MMU_UCQDB_Y_XPE2 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 12738 /* MMU_UCQDB_Y_XPE3 */ "Multicast queue database. This is a working FIFO maintained by hardware.", 12739 /* MMU_UCQ_RP */ "UCQ_RP", 12740 /* MMU_UCQ_WP */ "UCQ_WP", 12741 /* MMU_UC_QDB */ "UC_QDB", 12742 /* MMU_WAFAA */ "WAFAA", 12743 /* MMU_WAFAB */ "WAFAB", 12744 /* MMU_WAFAC */ "WAFAC", 12745 /* MMU_WAFA_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12746 /* MMU_WAFA_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12747 /* MMU_WAFBA */ "WAFBA", 12748 /* MMU_WAFBB */ "WAFBB", 12749 /* MMU_WAFBC */ "WAFBC", 12750 /* MMU_WAFB_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12751 /* MMU_WAFB_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12752 /* MMU_WAFC_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12753 /* MMU_WAFC_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12754 /* MMU_WAFD_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12755 /* MMU_WAFD_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12756 /* MMU_WAFE_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12757 /* MMU_WAFE_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12758 /* MMU_WAFF_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12759 /* MMU_WAFF_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12760 /* MMU_WAFG_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12761 /* MMU_WAFG_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12762 /* MMU_WAFH_HALFA_RADDR_STATUS */ "WAF HALFA RADDR + STATUS Indirect Mechanism.", 12763 /* MMU_WAFH_HALFB_RADDR_STATUS */ "WAF HALFB RADDR + STATUS Indirect Mechanism.", 12764 /* MMU_WAF_HALFA_WADDR */ "WAF HALFA WADDR Indirect Mechanism.", 12765 /* MMU_WAF_HALFB_WADDR */ "WAF HALFB WADDR Indirect Mechanism.", 12766 /* MMU_WAMULINK */ "WAMULINK", 12767 /* MMU_WAMU_MEM0 */ "Wireless Reassembly Context Table RAM", 12768 /* MMU_WAMU_MEM1 */ "Wireless Reassembly Context Table RAM", 12769 /* MMU_WAMU_MEM2 */ "Wireless Reassembly Context Table RAM", 12770 /* MMU_WAMU_MEM3 */ "Wireless Reassembly Context Table RAM", 12771 /* MMU_WDFAA */ "WDFAA", 12772 /* MMU_WDFAB */ "WDFAB", 12773 /* MMU_WDFAC */ "WDFAC", 12774 /* MMU_WDFBA */ "WDFBA", 12775 /* MMU_WDFBB */ "WDFBB", 12776 /* MMU_WDFBC */ "WDFBC", 12777 /* MMU_WFAFA */ "WFAFA", 12778 /* MMU_WFAFB */ "WFAFB", 12779 /* MMU_WFAFC */ "WFAFC", 12780 /* MMU_WFDFA */ "WFDFA", 12781 /* MMU_WFDFB */ "WFDFB", 12782 /* MMU_WFDFC */ "WFDFC", 12783 /* MMU_WRED_AVG_PORTSP_SIZE */ "WRED Average Queue Size Memory for PortSPs and SPs.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12784 /* MMU_WRED_AVG_PORTSP_SIZE_ITM0 */ "WRED Average Queue Size Memory for PortSPs and SPs.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12785 /* MMU_WRED_AVG_PORTSP_SIZE_ITM1 */ "WRED Average Queue Size Memory for PortSPs and SPs.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12786 /* MMU_WRED_AVG_QSIZE */ "WRED Average Queue Size Memory for Unicast Queue, Queue Group and Port service Pool.\nThe range:\n1023 ~ 0: Unicast Queue\n1279 ~ 1024: Queue Group\n1531 ~ 1280: Port Service Pool (port 0 to 62)\n Address = { 1, PortID[5:0], SPID[1:0]}\n Each Port's service pool is addressed by Address[1:0] of this memory address .\n1535 ~ 1532: Global Service Pool\n 1532: Global Service Pool 0\n 1533: Global Service Pool 1\n 1534: Global Service Pool 2\n 1535: Global Service ...", 12787 /* MMU_WRED_AVG_QSIZE_ITM0 */ "WRED Average Queue Size Memory for Unicast Queue.\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\netc ...", 12788 /* MMU_WRED_AVG_QSIZE_ITM1 */ "WRED Average Queue Size Memory for Unicast Queue.\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\netc ...", 12789 /* MMU_WRED_AVG_QSIZE_QGROUP */ "WRED Average Queue Size Memory for All Queues of Network Ports\nif(port_number = 58~65) MEM_ADDR[5:0]= { (port_number-58)*8+ QUEUE_GROUP_ID[2:0]}\nQUEUE_GROUP_ID[2:0] = 0~7", 12790 /* MMU_WRED_AVG_QSIZE_XPE0_PIPE0 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12791 /* MMU_WRED_AVG_QSIZE_XPE0_PIPE1 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12792 /* MMU_WRED_AVG_QSIZE_XPE1_PIPE2 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12793 /* MMU_WRED_AVG_QSIZE_XPE1_PIPE3 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12794 /* MMU_WRED_AVG_QSIZE_XPE2_PIPE0 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12795 /* MMU_WRED_AVG_QSIZE_XPE2_PIPE1 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12796 /* MMU_WRED_AVG_QSIZE_XPE3_PIPE2 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12797 /* MMU_WRED_AVG_QSIZE_XPE3_PIPE3 */ "WRED Average Queue Size Memory for Unicast Queue, and Port service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nThe physcial memory spans from 0 t ...", 12798 /* MMU_WRED_AVG_QSIZE_X_PIPE */ "WRED Average Queue Size Memory for Unicast Queue, Queue Group and Port service Pool.\nThe range:\n1479 ~ 0: Unicast Queue\n1487 ~ 1480: Not Used\n1615 - 1488: Queue Group\n Address = 1488 + {QGROUPID[6:0]}\n1823 ~ 1616: Port Service Pool (port 0 to 51)\n Address = 1616 + {PortID[5:0], SPID[1:0]}\n Each Port's service pool is addressed by Address[1:0] of this memory address .\n1839 ~ 1824: Not Used\n1843 ~ 1840: Global Service Pool\n 1840: Global Service Pool 0\n ...", 12799 /* MMU_WRED_AVG_QSIZE_Y_PIPE */ "WRED Average Queue Size Memory for Unicast Queue, Queue Group and Port service Pool.\nThe range:\n1479 ~ 0: Unicast Queue\n1487 ~ 1480: Not Used\n1615 - 1488: Queue Group\n Address = 1488 + {QGROUPID[6:0]}\n1823 ~ 1616: Port Service Pool (port 0 to 51)\n Address = 1616 + {PortID[5:0], SPID[1:0]}\n Each Port's service pool is addressed by Address[1:0] of this memory address .\n1839 ~ 1824: Not Used\n1843 ~ 1840: Global Service Pool\n 1840: Global Service Pool 0\n ...", 12800 /* MMU_WRED_CFG_CELL */ "WRED Configuartion and Average Qsize Memory for Cell", 12801 /* MMU_WRED_CFG_PACKET */ "WRED Configuartion and Average Qsize Memory for Packet", 12802 /* MMU_WRED_CONFIG */ "WRED Config Memory for Unicast Queue, Queue Group and Port service Pool.\nThe range:\n1023 ~ 0: Unicast Queue\n1279 ~ 1024: Queue Group\n1531 ~ 1280: Port Service Pool (port 0 to 62)\n Address = { 1, PortID[5:0], SPID[1:0]}\n Each Port's service pool is addressed by Address[1:0] of this memory address .\n1535 ~ 1532: Global Service Pool\n 1532: Global Service Pool 0\n 1533: Global Service Pool 1\n 1534: Global Service Pool 2\n 1535: Global Service Pool 3\nQGROU ...", 12803 /* MMU_WRED_CONFIG_PIPE0 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n649 ~ 0: Unicast Queue\n909 ~ 650: Port Service Pool (port 0 to 64)\n Address = 650 + {PORTID[6:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n913 ~ 910: Global Service Pool\n 910: Global Service Pool 0\n 911: Global Service Pool 1\n 912: Global Service Pool 2\n 913: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12804 /* MMU_WRED_CONFIG_PIPE1 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n649 ~ 0: Unicast Queue\n909 ~ 650: Port Service Pool (port 0 to 64)\n Address = 650 + {PORTID[6:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n913 ~ 910: Global Service Pool\n 910: Global Service Pool 0\n 911: Global Service Pool 1\n 912: Global Service Pool 2\n 913: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12805 /* MMU_WRED_CONFIG_QGROUP */ "WRED Config Memory for all queue group of network ports.\nNote: the QG \"ECN_MARKING_EN\" won't have any effect on hardware!! Hardware will honor\nper-Q's setting.\n\nif(port_number = 58~65) MEM_ADDR[5:0]= { (port_number-58)*8+ QUEUE_GROUP_ID[2:0]}\nQUEUE_GROUP_ID[2:0] = 0~7", 12806 /* MMU_WRED_CONFIG_XPE0_PIPE0 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12807 /* MMU_WRED_CONFIG_XPE0_PIPE1 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12808 /* MMU_WRED_CONFIG_XPE1_PIPE2 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12809 /* MMU_WRED_CONFIG_XPE1_PIPE3 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12810 /* MMU_WRED_CONFIG_XPE2_PIPE0 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12811 /* MMU_WRED_CONFIG_XPE2_PIPE1 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12812 /* MMU_WRED_CONFIG_XPE3_PIPE2 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12813 /* MMU_WRED_CONFIG_XPE3_PIPE3 */ "WRED Config Memory for Unicast Queue, PortSP and service Pool.\nThe range:\n329 ~ 0: Unicast Queue\n461 ~ 330: Port Service Pool (port 0 to 32)\n Address = 330 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address.\n465 ~ 462: Global Service Pool\n 462: Global Service Pool 0\n 463: Global Service Pool 1\n 464: Global Service Pool 2\n 465: Global Service Pool 3\nECN_MARKING_EN, LOGICAL_Q_TRACK_ENABLE, QG_E ...", 12814 /* MMU_WRED_CONFIG_X_PIPE */ "WRED Config Memory for Unicast Queue, Queue Group and Port service Pool.\nThe range:\n1479 ~ 0: Unicast Queue\n1487 ~ 1480: Not used.\n1615 - 1488: Queue Group per PIPE\n Address = 1488 + QGROUPID[6:0] per PIPE\n1823 ~ 1616: Port Service Pool (port 0 to 52)\n Address = 1616 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address .\n1843 ~ 1840: Global Service Pool\n 1840: Global Service Pool 0\n 1841: ...", 12815 /* MMU_WRED_CONFIG_Y_PIPE */ "WRED Config Memory for Unicast Queue, Queue Group and Port service Pool.\nThe range:\n1479 ~ 0: Unicast Queue\n1487 ~ 1480: Not used.\n1615 - 1488: Queue Group per PIPE\n Address = 1488 + QGROUPID[6:0] per PIPE\n1823 ~ 1616: Port Service Pool (port 0 to 52)\n Address = 1616 + {PORTID[5:0], SPID[1:0]} per PIPE\n Each Port's service pool is addressed by Address[1:0] of this memory address .\n1843 ~ 1840: Global Service Pool\n 1840: Global Service Pool 0\n 18 ...", 12816 /* MMU_WRED_DROP_CURVE_PROFILE_0 */ "WRED Drop Curve Profile for TCP Green Traffic", 12817 /* MMU_WRED_DROP_CURVE_PROFILE_1 */ "WRED Drop Curve Profile for TCP Yellow Traffic", 12818 /* MMU_WRED_DROP_CURVE_PROFILE_2 */ "WRED Drop Curve Profile For TCP Red Traffic", 12819 /* MMU_WRED_DROP_CURVE_PROFILE_3 */ "WRED Drop Curve Profile For Non-TCP Green Traffic", 12820 /* MMU_WRED_DROP_CURVE_PROFILE_4 */ "WRED Drop Curve Profile For Non-TCP Yellow Traffic", 12821 /* MMU_WRED_DROP_CURVE_PROFILE_5 */ "WRED Drop Curve Profile For Non-TCP Red Traffic", 12822 /* MMU_WRED_DROP_CURVE_PROFILE_6 */ "WRED Drop Curve Profile For ECN Marking Green packets", 12823 /* MMU_WRED_DROP_CURVE_PROFILE_7 */ "WRED Drop Curve Profile For ECN Marking Yellow packets", 12824 /* MMU_WRED_DROP_CURVE_PROFILE_8 */ "WRED Drop Curve Profile For ECN Marking Red packets", 12825 /* MMU_WRED_DROP_CURVE_PROFILE_0_0 */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic", 12826 /* MMU_WRED_DROP_CURVE_PROFILE_0_1 */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic", 12827 /* MMU_WRED_DROP_CURVE_PROFILE_0_2 */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic", 12828 /* MMU_WRED_DROP_CURVE_PROFILE_0_3 */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic", 12829 /* MMU_WRED_DROP_CURVE_PROFILE_0_4 */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic", 12830 /* MMU_WRED_DROP_CURVE_PROFILE_0_5 */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic", 12831 /* MMU_WRED_DROP_CURVE_PROFILE_0_A */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic, single view", 12832 /* MMU_WRED_DROP_CURVE_PROFILE_0_B */ "WRED Drop Curve Profile for Responsive Dropping Green Traffic, single view", 12833 /* MMU_WRED_DROP_CURVE_PROFILE_0_X_PIPE */ "WRED Drop Curve Profile for TCP Green Traffic", 12834 /* MMU_WRED_DROP_CURVE_PROFILE_0_Y_PIPE */ "WRED Drop Curve Profile for TCP Green Traffic", 12835 /* MMU_WRED_DROP_CURVE_PROFILE_1_0 */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic", 12836 /* MMU_WRED_DROP_CURVE_PROFILE_1_1 */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic", 12837 /* MMU_WRED_DROP_CURVE_PROFILE_1_2 */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic", 12838 /* MMU_WRED_DROP_CURVE_PROFILE_1_3 */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic", 12839 /* MMU_WRED_DROP_CURVE_PROFILE_1_4 */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic", 12840 /* MMU_WRED_DROP_CURVE_PROFILE_1_5 */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic", 12841 /* MMU_WRED_DROP_CURVE_PROFILE_1_A */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic, single view", 12842 /* MMU_WRED_DROP_CURVE_PROFILE_1_B */ "WRED Drop Curve Profile for Responsive Dropping Yellow Traffic, single view", 12843 /* MMU_WRED_DROP_CURVE_PROFILE_1_X_PIPE */ "WRED Drop Curve Profile for TCP Yellow Traffic", 12844 /* MMU_WRED_DROP_CURVE_PROFILE_1_Y_PIPE */ "WRED Drop Curve Profile for TCP Yellow Traffic", 12845 /* MMU_WRED_DROP_CURVE_PROFILE_2_0 */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic", 12846 /* MMU_WRED_DROP_CURVE_PROFILE_2_1 */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic", 12847 /* MMU_WRED_DROP_CURVE_PROFILE_2_2 */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic", 12848 /* MMU_WRED_DROP_CURVE_PROFILE_2_3 */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic", 12849 /* MMU_WRED_DROP_CURVE_PROFILE_2_4 */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic", 12850 /* MMU_WRED_DROP_CURVE_PROFILE_2_5 */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic", 12851 /* MMU_WRED_DROP_CURVE_PROFILE_2_A */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic, single view", 12852 /* MMU_WRED_DROP_CURVE_PROFILE_2_B */ "WRED Drop Curve Profile for Responsive Dropping Red Traffic, single view", 12853 /* MMU_WRED_DROP_CURVE_PROFILE_2_X_PIPE */ "WRED Drop Curve Profile For TCP Red Traffic", 12854 /* MMU_WRED_DROP_CURVE_PROFILE_2_Y_PIPE */ "WRED Drop Curve Profile For TCP Red Traffic", 12855 /* MMU_WRED_DROP_CURVE_PROFILE_3_0 */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic", 12856 /* MMU_WRED_DROP_CURVE_PROFILE_3_1 */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic", 12857 /* MMU_WRED_DROP_CURVE_PROFILE_3_2 */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic", 12858 /* MMU_WRED_DROP_CURVE_PROFILE_3_3 */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic", 12859 /* MMU_WRED_DROP_CURVE_PROFILE_3_4 */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic", 12860 /* MMU_WRED_DROP_CURVE_PROFILE_3_5 */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic", 12861 /* MMU_WRED_DROP_CURVE_PROFILE_3_A */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic, single view", 12862 /* MMU_WRED_DROP_CURVE_PROFILE_3_B */ "WRED Drop Curve Profile for Non-Responsive Dropping Green Traffic, single view", 12863 /* MMU_WRED_DROP_CURVE_PROFILE_3_X_PIPE */ "WRED Drop Curve Profile For Non-TCP Green Traffic", 12864 /* MMU_WRED_DROP_CURVE_PROFILE_3_Y_PIPE */ "WRED Drop Curve Profile For Non-TCP Green Traffic", 12865 /* MMU_WRED_DROP_CURVE_PROFILE_4_0 */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic", 12866 /* MMU_WRED_DROP_CURVE_PROFILE_4_1 */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic", 12867 /* MMU_WRED_DROP_CURVE_PROFILE_4_2 */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic", 12868 /* MMU_WRED_DROP_CURVE_PROFILE_4_3 */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic", 12869 /* MMU_WRED_DROP_CURVE_PROFILE_4_4 */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic", 12870 /* MMU_WRED_DROP_CURVE_PROFILE_4_5 */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic", 12871 /* MMU_WRED_DROP_CURVE_PROFILE_4_A */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic, single view", 12872 /* MMU_WRED_DROP_CURVE_PROFILE_4_B */ "WRED Drop Curve Profile for Non-Responsive Dropping Yellow Traffic, single view", 12873 /* MMU_WRED_DROP_CURVE_PROFILE_4_X_PIPE */ "WRED Drop Curve Profile For Non-TCP Yellow Traffic", 12874 /* MMU_WRED_DROP_CURVE_PROFILE_4_Y_PIPE */ "WRED Drop Curve Profile For Non-TCP Yellow Traffic", 12875 /* MMU_WRED_DROP_CURVE_PROFILE_5_0 */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic", 12876 /* MMU_WRED_DROP_CURVE_PROFILE_5_1 */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic", 12877 /* MMU_WRED_DROP_CURVE_PROFILE_5_2 */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic", 12878 /* MMU_WRED_DROP_CURVE_PROFILE_5_3 */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic", 12879 /* MMU_WRED_DROP_CURVE_PROFILE_5_4 */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic", 12880 /* MMU_WRED_DROP_CURVE_PROFILE_5_5 */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic", 12881 /* MMU_WRED_DROP_CURVE_PROFILE_5_A */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic, single view", 12882 /* MMU_WRED_DROP_CURVE_PROFILE_5_B */ "WRED Drop Curve Profile for Non-Responsive Dropping Red Traffic, single view", 12883 /* MMU_WRED_DROP_CURVE_PROFILE_5_X_PIPE */ "WRED Drop Curve Profile For Non-TCP Red Traffic", 12884 /* MMU_WRED_DROP_CURVE_PROFILE_5_Y_PIPE */ "WRED Drop Curve Profile For Non-TCP Red Traffic", 12885 /* MMU_WRED_DROP_CURVE_PROFILE_6_0 */ "WRED Drop Curve Profile for ECN Marking Green Traffic", 12886 /* MMU_WRED_DROP_CURVE_PROFILE_6_1 */ "WRED Drop Curve Profile for ECN Marking Green Traffic", 12887 /* MMU_WRED_DROP_CURVE_PROFILE_6_2 */ "WRED Drop Curve Profile for ECN Marking Green Traffic", 12888 /* MMU_WRED_DROP_CURVE_PROFILE_6_3 */ "WRED Drop Curve Profile for ECN Marking Green Traffic", 12889 /* MMU_WRED_DROP_CURVE_PROFILE_6_4 */ "WRED Drop Curve Profile for ECN Marking Green Traffic", 12890 /* MMU_WRED_DROP_CURVE_PROFILE_6_5 */ "WRED Drop Curve Profile for ECN Marking Green Traffic", 12891 /* MMU_WRED_DROP_CURVE_PROFILE_6_A */ "WRED Drop Curve Profile for ECN Marking Green Traffic, single view", 12892 /* MMU_WRED_DROP_CURVE_PROFILE_6_B */ "WRED Drop Curve Profile for ECN Marking Green Traffic, single view", 12893 /* MMU_WRED_DROP_CURVE_PROFILE_7_0 */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic", 12894 /* MMU_WRED_DROP_CURVE_PROFILE_7_1 */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic", 12895 /* MMU_WRED_DROP_CURVE_PROFILE_7_2 */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic", 12896 /* MMU_WRED_DROP_CURVE_PROFILE_7_3 */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic", 12897 /* MMU_WRED_DROP_CURVE_PROFILE_7_4 */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic", 12898 /* MMU_WRED_DROP_CURVE_PROFILE_7_5 */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic", 12899 /* MMU_WRED_DROP_CURVE_PROFILE_7_A */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic, single view", 12900 /* MMU_WRED_DROP_CURVE_PROFILE_7_B */ "WRED Drop Curve Profile for ECN Marking Yellow Traffic, single view", 12901 /* MMU_WRED_DROP_CURVE_PROFILE_8_0 */ "WRED Drop Curve Profile for ECN Marking Red Traffic", 12902 /* MMU_WRED_DROP_CURVE_PROFILE_8_1 */ "WRED Drop Curve Profile for ECN Marking Red Traffic", 12903 /* MMU_WRED_DROP_CURVE_PROFILE_8_2 */ "WRED Drop Curve Profile for ECN Marking Red Traffic", 12904 /* MMU_WRED_DROP_CURVE_PROFILE_8_3 */ "WRED Drop Curve Profile for ECN Marking Red Traffic", 12905 /* MMU_WRED_DROP_CURVE_PROFILE_8_4 */ "WRED Drop Curve Profile for ECN Marking Red Traffic", 12906 /* MMU_WRED_DROP_CURVE_PROFILE_8_5 */ "WRED Drop Curve Profile for ECN Marking Red Traffic", 12907 /* MMU_WRED_DROP_CURVE_PROFILE_8_A */ "WRED Drop Curve Profile for ECN Marking Red Traffic, single view", 12908 /* MMU_WRED_DROP_CURVE_PROFILE_8_B */ "WRED Drop Curve Profile for ECN Marking Red Traffic, single view", 12909 /* MMU_WRED_DROP_PROFILE_GREEN */ "WRED Responsive Drop Curve Profile for Green Packet", 12910 /* MMU_WRED_DROP_PROFILE_RED */ "WRED Responsive Drop Curve Profile for RED Packet", 12911 /* MMU_WRED_DROP_PROFILE_YELLOW */ "WRED Responsive Drop Curve Profile for Yellow Packet", 12912 /* MMU_WRED_DROP_THD_UC_DEQ0 */ "WRED Unicast Drop Threshold Memory for Deq pipe 0", 12913 /* MMU_WRED_DROP_THD_UC_DEQ1 */ "WRED Unicast Drop Threshold Memory for Deq pipe 1", 12914 /* MMU_WRED_DROP_THD_UC_ENQ0 */ "WRED Unicast Drop Threshold Memory for Enq pipe 0", 12915 /* MMU_WRED_DROP_THD_UC_ENQ1 */ "WRED Unicast Drop Threshold Memory for Enq pipe 1", 12916 /* MMU_WRED_MARK_PROFILE_GREEN */ "WRED Mark Curve Profile for Green Packet", 12917 /* MMU_WRED_MARK_PROFILE_RED */ "WRED Mark Curve Profile for Red Packet", 12918 /* MMU_WRED_MARK_PROFILE_YELLOW */ "WRED Mark Curve Profile for Yellow Packet", 12919 /* MMU_WRED_MARK_THD */ "WRED Mark Threshold Memory\nMEM_ADDR[7:0]={PORT_ID[4:0], QUEUE_ID[2:0]}\nPORT_ID[4:0] = 0, PORT 2,\nPORT_ID[4:0] = 1, PORT 3,\n...\nPORT_ID[4:0] = 27, PORT 29,\nPORT_ID[4:0] = 28, Invalid,\n...\nPORT_ID[4:0] = 31, Invalid.\nQUEUE_ID[2:0] = 0, Queue 0,\nQUEUE_ID[2:0] = 1, Queue 1,\n...\nQUEUE_ID[2:0] = 7, Queue 7.", 12920 /* MMU_WRED_OPN_AVG_QSIZE_BUFFER */ "WRED O/P Node Avg Q Size memory - will be split in 8 banks", 12921 /* MMU_WRED_OPN_AVG_QSIZE_QENTRY */ "WRED O/P Node Avg Q Size memory - will be split in 8 banks", 12922 /* MMU_WRED_OPN_CONFIG_BUFFER */ "WRED Output Node Config Memory - will be split in 8 banks", 12923 /* MMU_WRED_OPN_CONFIG_QENTRY */ "WRED Output Node Config Memory - will be split in 8 banks", 12924 /* MMU_WRED_OPN_DROP_THD_DEQ */ "WRED Unicast Drop Threshold Memory for Deq", 12925 /* MMU_WRED_OPN_DROP_THD_ENQ */ "WRED Unicast Drop Threshold Memory for Enq", 12926 /* MMU_WRED_PORTSP_CONFIG */ "WRED Config Memory for PortSP.\nConfig for Global Service Pool is stored in registers.\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-319\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\netc\nAddress 320-639\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\netc", 12927 /* MMU_WRED_PORT_CFG_CELL */ "WRED Port Configuartion and Average Qsize Memory for Cell", 12928 /* MMU_WRED_PORT_CFG_PACKET */ "WRED Port Configuartion and Average Qsize Memory for Packet", 12929 /* MMU_WRED_PORT_SP_DROP_THD */ "WRED Unicast Drop Threshold Memory for Port Service Pool", 12930 /* MMU_WRED_PORT_SP_DROP_THD_0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12931 /* MMU_WRED_PORT_SP_DROP_THD_1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12932 /* MMU_WRED_PORT_SP_DROP_THD_2 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12933 /* MMU_WRED_PORT_SP_DROP_THD_3 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12934 /* MMU_WRED_PORT_SP_DROP_THD_0_ITM0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12935 /* MMU_WRED_PORT_SP_DROP_THD_0_ITM1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12936 /* MMU_WRED_PORT_SP_DROP_THD_1_ITM0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12937 /* MMU_WRED_PORT_SP_DROP_THD_1_ITM1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12938 /* MMU_WRED_PORT_SP_DROP_THD_2_ITM0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12939 /* MMU_WRED_PORT_SP_DROP_THD_2_ITM1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12940 /* MMU_WRED_PORT_SP_DROP_THD_3_ITM0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12941 /* MMU_WRED_PORT_SP_DROP_THD_3_ITM1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12942 /* MMU_WRED_PORT_SP_DROP_THD_MARK */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12943 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE0_PIPE0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12944 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE0_PIPE1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12945 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE2 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12946 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE1_PIPE3 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12947 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE2_PIPE0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12948 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE2_PIPE1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12949 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE2 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12950 /* MMU_WRED_PORT_SP_DROP_THD_MARK_XPE3_PIPE3 */ "WRED Unicast Drop Threshold Memory for Port Service Pool ECN Marking,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12951 /* MMU_WRED_PORT_SP_DROP_THD_XPE0_PIPE0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12952 /* MMU_WRED_PORT_SP_DROP_THD_XPE0_PIPE1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12953 /* MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE2 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12954 /* MMU_WRED_PORT_SP_DROP_THD_XPE1_PIPE3 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12955 /* MMU_WRED_PORT_SP_DROP_THD_XPE2_PIPE0 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12956 /* MMU_WRED_PORT_SP_DROP_THD_XPE2_PIPE1 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12957 /* MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE2 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12958 /* MMU_WRED_PORT_SP_DROP_THD_XPE3_PIPE3 */ "WRED Unicast Drop Threshold Memory for Port Service Pool,\nThe physcial memory spans from 0 to 143, while the functional entries are from 0 to 131.", 12959 /* MMU_WRED_PORT_SP_DROP_THD_X_PIPE */ "WRED Unicast Drop Threshold Memory for Port Service Pool X PIPE", 12960 /* MMU_WRED_PORT_SP_DROP_THD_Y_PIPE */ "WRED Unicast Drop Threshold Memory for Port Service Pool Y PIPE", 12961 /* MMU_WRED_PORT_SP_SHARED_COUNT */ "WRED Port Service Pool Total Count Shadow Copy Memory", 12962 /* MMU_WRED_PORT_SP_SHARED_COUNT_ITM0 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12963 /* MMU_WRED_PORT_SP_SHARED_COUNT_ITM1 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from port 0 to 159 service pool 0 and 2 ,Addressed per {OQS, SP[1]}.\nOrganisad as:\nAddress 0-321\n port 0 : sp 0\n port 0 : sp 2\n port 1 : sp 0\n port 1 : sp 2\n port 2 : sp 0\n port 2 : sp 2\n 320 = sp0\n 321 = sp2\netc\nAddress 322-643\n port 0 : sp 1\n port 0 : sp 3\n port 1 : sp 1\n port 1 : sp 3\n port 2 : sp 1\n port 2 : sp 3\n 642 = sp1\n 643 = sp3\netc", 12964 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE0 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12965 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12966 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE2 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12967 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12968 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE0 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12969 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12970 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE2 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12971 /* MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3 */ "WRED Port Service Pool Shared Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 135, while the functional entries are from 0 to 131.", 12972 /* MMU_WRED_PORT_SP_SHARED_COUNT_X_PIPE */ "WRED Port Service Pool Shared Count Shadow Copy Memory X PIPE", 12973 /* MMU_WRED_PORT_SP_SHARED_COUNT_Y_PIPE */ "WRED Port Service Pool Shared Count Shadow Copy Memory Y PIPE", 12974 /* MMU_WRED_PORT_THD_0_CELL */ "WRED Port Green and Yellow Threshold Memory for Cell", 12975 /* MMU_WRED_PORT_THD_0_PACKET */ "WRED Port Green and Yellow Threshold Memory for Packet", 12976 /* MMU_WRED_PORT_THD_1_CELL */ "WRED Port Green and Yellow Threshold Memory for Cell", 12977 /* MMU_WRED_PORT_THD_1_PACKET */ "WRED Red and Nontcp Threshold Memory for Packet", 12978 /* MMU_WRED_QGROUP_DROP_THD */ "WRED Unicast Drop Threshold Memory for Queue Group", 12979 /* MMU_WRED_QGROUP_DROP_THD_X_PIPE */ "WRED Unicast Drop Threshold Memory for Queue Group X PIPE", 12980 /* MMU_WRED_QGROUP_DROP_THD_Y_PIPE */ "WRED Unicast Drop Threshold Memory for Queue Group Y PIPE", 12981 /* MMU_WRED_QGROUP_SHARED_COUNT */ "WRED Queue Group Shared Count Shadow Copy Memory", 12982 /* MMU_WRED_QGROUP_SHARED_COUNT_X_PIPE */ "WRED Queue Group Shared Count Shadow Copy Memory X PIPE", 12983 /* MMU_WRED_QGROUP_SHARED_COUNT_Y_PIPE */ "WRED Queue Group Shared Count Shadow Copy Memory Y PIPE", 12984 /* MMU_WRED_QUEUE_AVG_QSIZE_BUFFER */ "WRED Queue Avg Q Size Memory - will be split in 8 banks", 12985 /* MMU_WRED_QUEUE_AVG_QSIZE_QENTRY */ "WRED Queue Avg Q Size Memory - will be split in 8 banks", 12986 /* MMU_WRED_QUEUE_CONFIG */ "WRED Config Memory for Unicast Queue, .\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\netc\nAddress 1 ...", 12987 /* MMU_WRED_QUEUE_CONFIG_BUFFER */ "WRED Queue Config Memory - will be split in 8 banks", 12988 /* MMU_WRED_QUEUE_CONFIG_QENTRY */ "WRED Queue Config Memory - will be split in 8 banks", 12989 /* MMU_WRED_QUEUE_DROP_THD_DEQ */ "WRED Unicast Drop Threshold Memory for Deq", 12990 /* MMU_WRED_QUEUE_DROP_THD_ENQ */ "WRED Unicast Drop Threshold Memory for Enq", 12991 /* MMU_WRED_QUEUE_DROP_THD_ENQ_0 */ "WRED Unicast Drop Threshold Memory for Enq", 12992 /* MMU_WRED_QUEUE_DROP_THD_ENQ_1 */ "WRED Unicast Drop Threshold Memory for Enq", 12993 /* MMU_WRED_QUEUE_OP_NODE_MAP */ "Queue to OP NODE mapping table", 12994 /* MMU_WRED_THD_0_CELL */ "WRED Green and Yellow Threshold Memory for Cell", 12995 /* MMU_WRED_THD_0_PACKET */ "WRED Green and Yellow Threshold Memory for Packet", 12996 /* MMU_WRED_THD_1_CELL */ "WRED Green and Yellow Threshold Memory for Cell", 12997 /* MMU_WRED_THD_1_PACKET */ "WRED Red and Nontcp Threshold Memory for Packet", 12998 /* MMU_WRED_UC_QUEUE_DROP_THD */ "WRED Unicast Drop Threshold Memory for WRED Dropping,", 12999 /* MMU_WRED_UC_QUEUE_DROP_THD_0 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13000 /* MMU_WRED_UC_QUEUE_DROP_THD_1 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13001 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE0_PIPE0 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13002 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE0_PIPE1 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13003 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE2 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13004 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE1_PIPE3 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13005 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE2_PIPE0 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13006 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE2_PIPE1 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13007 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE2 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13008 /* MMU_WRED_UC_QUEUE_DROP_THD_0_XPE3_PIPE3 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13009 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE0_PIPE0 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13010 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE0_PIPE1 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13011 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE2 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13012 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE1_PIPE3 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13013 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE2_PIPE0 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13014 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE2_PIPE1 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13015 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE2 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13016 /* MMU_WRED_UC_QUEUE_DROP_THD_1_XPE3_PIPE3 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13017 /* MMU_WRED_UC_QUEUE_DROP_THD_DEQ */ "WRED Unicast Drop Threshold Memory for Deq", 13018 /* MMU_WRED_UC_QUEUE_DROP_THD_DEQ_X_PIPE_0 */ "WRED Unicast Drop Threshold Memory for Deq", 13019 /* MMU_WRED_UC_QUEUE_DROP_THD_DEQ_Y_PIPE_1 */ "WRED Unicast Drop Threshold Memory for Deq", 13020 /* MMU_WRED_UC_QUEUE_DROP_THD_ENQ */ "WRED Unicast Drop Threshold Memory for Enq", 13021 /* MMU_WRED_UC_QUEUE_DROP_THD_ENQ_X_PIPE_0 */ "WRED Unicast Drop Threshold Memory for Enq", 13022 /* MMU_WRED_UC_QUEUE_DROP_THD_ENQ_X_PIPE_1 */ "WRED Unicast Drop Threshold Memory for Deq", 13023 /* MMU_WRED_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_0 */ "WRED Unicast Drop Threshold Memory for Deq", 13024 /* MMU_WRED_UC_QUEUE_DROP_THD_ENQ_Y_PIPE_1 */ "WRED Unicast Drop Threshold Memory for Deq", 13025 /* MMU_WRED_UC_QUEUE_DROP_THD_ITM0 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,", 13026 /* MMU_WRED_UC_QUEUE_DROP_THD_ITM1 */ "WRED Unicast Drop Threshold Memory for WRED Dropping,", 13027 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13028 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_0 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\ne ...", 13029 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_1 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\ne ...", 13030 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_0_ITM0 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\ne ...", 13031 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_0_ITM1 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\ne ...", 13032 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_1_ITM0 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\ne ...", 13033 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_1_ITM1 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3\netc\nAddress 960-1439\n port 0 : qbank 6\n port 0 : qbank 7\n port 0 : qbank 8\n port 1 : qbank 6\n port 1 : qbank 7\n port 1 : qbank 8\n port 2 : qbank 6\ne ...", 13034 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE0_PIPE0 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13035 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE0_PIPE1 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13036 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE2 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13037 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE1_PIPE3 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13038 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE2_PIPE0 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13039 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE2_PIPE1 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13040 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE2 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13041 /* MMU_WRED_UC_QUEUE_DROP_THD_MARK_XPE3_PIPE3 */ "WRED Unicast Drop Threshold Memory for ECN Marking,\nThe physcial memory spans from 0 to 351, while the functional entries are from 0 to 329.", 13042 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT */ "WRED UC Queue Total Count Shadow Copy Memory", 13043 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13044 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE0_PIPE0 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13045 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE0_PIPE1 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13046 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE2 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13047 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE1_PIPE3 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13048 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE2_PIPE0 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13049 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE2_PIPE1 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13050 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE2 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13051 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_FROM_REMOTE_XPE3_PIPE3 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13052 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_ITM0 */ "WRED Average Queue Size Memory for Unicast Queue.\nBefore writing into this memory,\nMMU_WRED_CONFIG_READY.WRED_READY must be set to 0 and\nMMU_THDO_ENGINE_ENABLES_CFG.RESET_WRED_ENGINE must be set to 1.\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3 ...", 13053 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_ITM1 */ "WRED Average Queue Size Memory for Unicast Queue.\nBefore writing into this memory,\nMMU_WRED_CONFIG_READY.WRED_READY must be set to 0 and\nMMU_THDO_ENGINE_ENABLES_CFG.RESET_WRED_ENGINE must be set to 1.\nOrganisad as:\nAddress 0-479\n port 0 : qbank 0\n port 0 : qbank 1\n port 0 : qbank 2\n port 1 : qbank 0\n port 1 : qbank 1\n port 1 : qbank 2\n port 2 : qbank 0\netc\nAddress 480-959\n port 0 : qbank 3\n port 0 : qbank 4\n port 0 : qbank 5\n port 1 : qbank 3\n port 1 : qbank 4\n port 1 : qbank 5\n port 2 : qbank 3 ...", 13054 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE0_PIPE0 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13055 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE0_PIPE1 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13056 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE2 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13057 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE1_PIPE3 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13058 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE2_PIPE0 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13059 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE2_PIPE1 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13060 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE2 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13061 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_XPE3_PIPE3 */ "WRED UC Queue Total Count Shadow Copy Memory,\nThe physcial memory spans from 0 to 335, while the functional entries are from 0 to 329.", 13062 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_X_PIPE */ "WRED UC Queue Total Count Shadow Copy Memory X PIPE", 13063 /* MMU_WRED_UC_QUEUE_TOTAL_COUNT_Y_PIPE */ "WRED UC Queue Total Count Shadow Copy Memory Y PIPE", 13064 /* MMU_WR_DATA_MEM */ "Memory to store the Data after the async fifo on thew write path", 13065 /* MMU_WR_FBC_DATA_MEM */ "Memory to store the Fbc Data after the async fifo on the write path", 13066 /* MMU_XCFG_MEM_FAIL_ADDR_64 */ "Memory Fail address FIFO", 13067 /* MMU_XCFG_MEM_FAIL_ADDR_64_XPE0 */ "Memory Fail address FIFO", 13068 /* MMU_XCFG_MEM_FAIL_ADDR_64_XPE1 */ "Memory Fail address FIFO", 13069 /* MMU_XCFG_MEM_FAIL_ADDR_64_XPE2 */ "Memory Fail address FIFO", 13070 /* MMU_XCFG_MEM_FAIL_ADDR_64_XPE3 */ "Memory Fail address FIFO", 13071 /* MMU_XQ0 */ "XQ0", 13072 /* MMU_XQ1 */ "XQ1", 13073 /* MMU_XQ2 */ "XQ2", 13074 /* MMU_XQ3 */ "XQ3", 13075 /* MMU_XQ4 */ "XQ4", 13076 /* MMU_XQ5 */ "XQ5", 13077 /* MMU_XQ6 */ "XQ6", 13078 /* MMU_XQ7 */ "XQ7", 13079 /* MMU_XQ8 */ "XQ8", 13080 /* MMU_XQ9 */ "XQ9", 13081 /* MMU_XQ10 */ "XQ10", 13082 /* MMU_XQ11 */ "XQ11", 13083 /* MMU_XQ12 */ "XQ12", 13084 /* MMU_XQ13 */ "XQ13", 13085 /* MMU_XQ14 */ "XQ14", 13086 /* MMU_XQ15 */ "XQ15", 13087 /* MMU_XQ16 */ "XQ16", 13088 /* MMU_XQ17 */ "XQ17", 13089 /* MMU_XQ18 */ "XQ18", 13090 /* MMU_XQ19 */ "XQ19", 13091 /* MMU_XQ20 */ "XQ20", 13092 /* MMU_XQ21 */ "XQ21", 13093 /* MMU_XQ22 */ "XQ22", 13094 /* MMU_XQ23 */ "XQ23", 13095 /* MMU_XQ24 */ "XQ24", 13096 /* MMU_XQ25 */ "XQ25", 13097 /* MMU_XQ26 */ "XQ26", 13098 /* MMU_XQ27 */ "XQ27", 13099 /* MMU_XQ28 */ "XQ28", 13100 /* MMU_XQ29 */ "XQ29", 13101 /* MMU_XQ30 */ "XQ30", 13102 /* MMU_XQ31 */ "XQ31", 13103 /* MMU_XQ32 */ "XQ32", 13104 /* MMU_XQ33 */ "XQ33", 13105 /* MMU_XQ34 */ "XQ34", 13106 /* MMU_XQ35 */ "XQ35", 13107 /* MMU_XQ36 */ "XQ36", 13108 /* MMU_XQ37 */ "XQ37", 13109 /* MMU_XQ38 */ "XQ38", 13110 /* MMU_XQ39 */ "XQ39", 13111 /* MMU_XQ40 */ "XQ40", 13112 /* MMU_XQ41 */ "XQ41", 13113 /* MMU_XQ42 */ "XQ42", 13114 /* MMU_XQ43 */ "XQ43", 13115 /* MMU_XQ44 */ "XQ44", 13116 /* MMU_XQ45 */ "XQ45", 13117 /* MMU_XQ46 */ "XQ46", 13118 /* MMU_XQ47 */ "XQ47", 13119 /* MMU_XQ48 */ "XQ48", 13120 /* MMU_XQ49 */ "XQ49", 13121 /* MMU_XQ50 */ "XQ50", 13122 /* MMU_XQ51 */ "XQ51", 13123 /* MMU_XQ52 */ "XQ52", 13124 /* MMU_XQ53 */ "XQ53", 13125 /* MMU_XQ54 */ "XQ54", 13126 /* MMU_XQ55 */ "XQ55", 13127 /* MMU_XQ56 */ "XQ56", 13128 /* MMU_XQ57 */ "XQ57", 13129 /* MMU_XQ58 */ "XQ58", 13130 /* MMU_XQ59 */ "XQ59", 13131 /* MMU_XQ60 */ "XQ60", 13132 /* MMU_XQ61 */ "XQ61", 13133 /* MMU_XQ62 */ "XQ62", 13134 /* MMU_XQ63 */ "XQ63", 13135 /* MMU_XQ64 */ "XQ64", 13136 /* MMU_XQ65 */ "XQ65", 13137 /* MMU_XQFLL0 */ "XQFLL0", 13138 /* MMU_XQFLL2 */ "XQFLL2", 13139 /* MMU_XQFLL3 */ "XQFLL3", 13140 /* MMU_XQFLL4 */ "XQFLL4", 13141 /* MMU_XQFLL5 */ "XQFLL5", 13142 /* MMU_XQFLL6 */ "XQFLL6", 13143 /* MMU_XQFLL7 */ "XQFLL7", 13144 /* MMU_XQFLL8 */ "XQFLL8", 13145 /* MMU_XQFLL9 */ "XQFLL9", 13146 /* MMU_XQFLL10 */ "XQFLL10", 13147 /* MMU_XQFLL11 */ "XQFLL11", 13148 /* MMU_XQFLL12 */ "XQFLL12", 13149 /* MMU_XQFLL13 */ "XQFLL13", 13150 /* MMU_XQFLL14 */ "XQFLL14", 13151 /* MMU_XQFLL15 */ "XQFLL15", 13152 /* MMU_XQFLL16 */ "XQFLL16", 13153 /* MMU_XQFLL17 */ "XQFLL17", 13154 /* MMU_XQFLL18 */ "XQFLL18", 13155 /* MMU_XQFLL19 */ "XQFLL19", 13156 /* MMU_XQFLL20 */ "XQFLL20", 13157 /* MMU_XQFLL21 */ "XQFLL21", 13158 /* MMU_XQFLL22 */ "XQFLL22", 13159 /* MMU_XQFLL23 */ "XQFLL23", 13160 /* MMU_XQFLL24 */ "XQFLL24", 13161 /* MMU_XQFLL25 */ "XQFLL25", 13162 /* MMU_XQFLL26 */ "XQFLL26", 13163 /* MMU_XQFLL27 */ "XQFLL27", 13164 /* MMU_XQFLL28 */ "XQFLL28", 13165 /* MMU_XQFLL29 */ "XQFLL29", 13166 /* MMU_XQFLL30 */ "XQFLL30", 13167 /* MMU_XQFLL31 */ "XQFLL31", 13168 /* MMU_XQFLL32 */ "XQFLL32", 13169 /* MMU_XQFLL33 */ "XQFLL33", 13170 /* MMU_XQFLL34 */ "XQFLL34", 13171 /* MMU_XQFLL35 */ "XQFLL35", 13172 /* MMU_XQFLL36 */ "XQFLL36", 13173 /* MMU_XQFLL37 */ "XQFLL37", 13174 /* MMU_XQFLL38 */ "XQFLL38", 13175 /* MMU_XQFLL39 */ "XQFLL39", 13176 /* MMU_XQFLL40 */ "XQFLL40", 13177 /* MMU_XQFLL41 */ "XQFLL41", 13178 /* MMU_XQFLL42 */ "XQFLL42", 13179 /* MMU_XQFLL43 */ "XQFLL43", 13180 /* MMU_XQFLL44 */ "XQFLL44", 13181 /* MMU_XQFLL45 */ "XQFLL45", 13182 /* MMU_XQFLL46 */ "XQFLL46", 13183 /* MMU_XQFLL47 */ "XQFLL47", 13184 /* MMU_XQFLL48 */ "XQFLL48", 13185 /* MMU_XQFLL49 */ "XQFLL49", 13186 /* MMU_XQFLL50 */ "XQFLL50", 13187 /* MMU_XQFLL51 */ "XQFLL51", 13188 /* MMU_XQFLL52 */ "XQFLL52", 13189 /* MMU_XQFLL53 */ "XQFLL53", 13190 /* MMU_XQFLL54 */ "XQFLL54", 13191 /* MMU_XQFLL55 */ "XQFLL55", 13192 /* MMU_XQFLL56 */ "XQFLL56", 13193 /* MMU_XQFLL57 */ "XQFLL57", 13194 /* MMU_XQFLL58 */ "XQFLL58", 13195 /* MMU_XQFLL59 */ "XQFLL59", 13196 /* MMU_XQFLL60 */ "XQFLL60", 13197 /* MMU_XQFLL61 */ "XQFLL61", 13198 /* MMU_XQFLL62 */ "XQFLL62", 13199 /* MMU_XQFLL63 */ "XQFLL63", 13200 /* MMU_XQFLL64 */ "XQFLL64", 13201 /* MMU_XQFLL65 */ "XQFLL65", 13202 /* MODID_BASE_PTR */ "Maps DST_MODID to a base pointer in the MODPORT_MAP_SUBPORT table.", 13203 /* MODPORT_MAP */ "Module Port Mapping Table", 13204 /* MODPORT_MAP_EM */ "Third physical copy of Module Port Mapping Table - used for mapping the egress mirrored copy of a packet", 13205 /* MODPORT_MAP_IM */ "Second physical copy of Module Port Mapping Table - used for mapping the ingress mirrored copy of a packet", 13206 /* MODPORT_MAP_M0 */ "First physical copy of Module Port Mapping Table - used for mapping the M0 copy of a packet.", 13207 /* MODPORT_MAP_M1 */ "First physical copy of Module Port Mapping Table - used for mapping the M1 copy of a packet.", 13208 /* MODPORT_MAP_M2 */ "First physical copy of Module Port Mapping Table - used for mapping the M2 copy of a packet.", 13209 /* MODPORT_MAP_M3 */ "First physical copy of Module Port Mapping Table - used for mapping the M3 copy of a packet.", 13210 /* MODPORT_MAP_MIRROR */ "Second physical copy of Module Port Mapping Table - used for mapping the ingress mirrored copy of a packet", 13211 /* MODPORT_MAP_MIRROR_1 */ "Third physical copy of Module Port Mapping Table - used for mapping the egress mirrored copy of a packet", 13212 /* MODPORT_MAP_SUBPORT */ "This table is used to determine the necessary cascaded egress port or cascaded egress trunk that a switched packet must use in order to reach the subtending port.", 13213 /* MODPORT_MAP_SUBPORT_M0 */ "Physical copy of Module Port to front panel port or COE Subtending Port Mapping Table - used for mapping the M0 copy of a packet.", 13214 /* MODPORT_MAP_SUBPORT_M1 */ "Physical copy of Module Port to front panel port or COE Subtending Port Mapping Table - used for mapping the M1 copy of a packet.", 13215 /* MODPORT_MAP_SUBPORT_M2 */ "Physical copy of Module Port to front panel port or COE Subtending Port Mapping Table - used for mapping the M2 copy of a packet.", 13216 /* MODPORT_MAP_SUBPORT_M3 */ "Physical copy of Module Port to front panel port or COE Subtending Port Mapping Table - used for mapping the M3 copy of a packet.", 13217 /* MODPORT_MAP_SUBPORT_MIRROR */ "Module Port to front panel port or COE Subtending Port Mapping Table - Mirror Copy. Writing this view writes all four physical copies.", 13218 /* MODPORT_MAP_SW */ "First physical copy of Module Port Mapping Table - used for mapping the switched copy of a packet", 13219 /* MPLS_EDIT_CTRL_ID_MAP */ "MPLS EDIT_CTRL_ID mapping table.", 13220 /* MPLS_ENTROPY_LABEL_DATA */ "The fields in this table should be an alias of all the fields in the MPLS_ENTRY table.", 13221 /* MPLS_ENTRY */ "MPLS Label Lookup. Dual-Hash table with Keys and Data", 13222 /* MPLS_ENTRY_1 */ "", 13223 /* MPLS_ENTRY_1_HIT_ONLY */ "MPLS_ENTRY_1_HIT_ONLY, Single base entry views. FeatureSpecific-Ethernet.", 13224 /* MPLS_ENTRY_2_HIT_ONLY */ "MPLS_ENTRY_2_HIT_ONLY, Double base entry views. FeatureSpecific-Ethernet.", 13225 /* MPLS_ENTRY_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 13226 /* MPLS_ENTRY_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 13227 /* MPLS_ENTRY_ECC */ "ECC Table for MPLS_ENTRY.", 13228 /* MPLS_ENTRY_EXTD */ "MPLS_ENTRY_2, Double base entry views. FeatureSpecific-Ethernet.", 13229 /* MPLS_ENTRY_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 13230 /* MPLS_ENTRY_KEY_ATTRIBUTES */ "Key Attributes Table.", 13231 /* MPLS_ENTRY_KEY_BUFFER_0 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13232 /* MPLS_ENTRY_KEY_BUFFER_1 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13233 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE0 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13234 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE1 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13235 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE2 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13236 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE3 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13237 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE4 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13238 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE5 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13239 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE6 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13240 /* MPLS_ENTRY_KEY_BUFFER_0_PIPE7 */ "Records first lookup key of MPLS_ENTRY lookup for visibility packets.", 13241 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE0 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13242 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE1 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13243 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE2 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13244 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE3 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13245 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE4 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13246 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE5 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13247 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE6 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13248 /* MPLS_ENTRY_KEY_BUFFER_1_PIPE7 */ "Records second lookup key of MPLS_ENTRY lookup for visibility packets.", 13249 /* MPLS_ENTRY_LP */ "ECC Table.", 13250 /* MPLS_ENTRY_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 13251 /* MPLS_ENTRY_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 13252 /* MPLS_ENTRY_SCRATCH */ "Single MPLS_ENTRY entry that is usable by software.when shifting MPLS_ENTRY entries across the dual hash. Fully usable entry that is searched for every packet. Acts like a fully-associative 9th entry (for every bucket.)", 13253 /* MPLS_ENTRY_SINGLE */ "Holds key & data for L2-VLAN, VIF, L2GRE_DIP and VXLAN_DIP based VLAN substitutions.", 13254 /* MPLS_OAM_ACH_TYPE_CONFIG */ "This table is used to configure the ACH types associated with MPLS LM/DM, BHH-OAM, and any GAL_ACH messages. Note that for MPLS LM/DM the OPCOD_VALID = 1, but for BHH-OAM the OPCODE_VLAID =0. Also note that this table is not used for BFD and BFD has its own dedicated registers for ACH configuration.", 13255 /* MPLS_PARSER2_CONTEXT_PROFILE */ "MPLS parsing Profile.", 13256 /* MPLS_STATION_TCAM */ "TCAM for MPLS My Station lookups - no associated data", 13257 /* MP_GROUP */ "MEP lookup table in ingress direction. No hit bits, FeatureSpecific-OAM.", 13258 /* MRPS_AUTO_DOC_NAME_39 */ "INTERNAL", 13259 /* MRPS_CONTEXT_COLOR */ "Color memory per context", 13260 /* MRPS_CONTEXT_SIZE_HIGH */ "Packet size memory per context.\n Higher 138 values\n (total of 330 contexts in Jericho)", 13261 /* MRPS_CONTEXT_SIZE_LOW */ "Packet size memory per context.\n Lower 192 values", 13262 /* MRPS_EGR_ENG_PRFCFG */ "MCD-A - profile configuration. First copy Both copies should be initialized the same", 13263 /* MRPS_EGR_ENG_PTR_MAP */ "Egress engines pointer map. Map meter pointer MSBs (from TM command) to new pointer MSBs which are used for bank selection. Mapping of 8 bits to 8 bits", 13264 /* MRPS_EGR_FINAL_RSLV_COLOR */ "Ingress Final-Resolution-Color-Table. Address to this table: - bits 3:0 - DP-Command - bits 5:4 - In-Color - bits 7:6 - Resolved Color (from EgrColorRslvTable)", 13265 /* MRPS_EGR_RSLV_COLOR */ "Ingress Resolution-Color-Table. Address to this table: - bits 1:0 - Engine-0 Color - bits 2 - Engine-0 Other-Bucket-Level - bits 4:3 - Engine-1 Color - bits 5 - Engine-1 Other-Bucket-Level - bits 6 - Engine-0-Profile / Dp-Command0 - bits 7 - Engine-1-Profile / Dp-Command1 - bits 8 - Dp-Command2 - bits 9 - Dp-Command3", 13266 /* MRPS_ING_ENG_HAPM */ "Ingress Engines Header-Append-Pointer mapping table. Map Header-Append-Pointer to Packet-Delta.", 13267 /* MRPS_ING_ENG_HCPM */ "Ingress Engines Header-Compensation-Profile mapping table. Map Header-Compensation-Profile to Packet-Delta.", 13268 /* MRPS_ING_ENG_PP_PORT_MAP */ "Ingress Engines PP-Port mapping table. Map PP-Port to Packet-Delta.", 13269 /* MRPS_ING_ENG_PRFCFG */ "Ingress Engines profile config memory", 13270 /* MRPS_ING_ENG_PTR_MAP */ "Ingress engines pointer map. Map meter pointer MSBs (from TM command) to new pointer MSBs which are used for bank selection. Mapping of 8 bits to 8 bits", 13271 /* MRPS_ING_FINAL_RSLV_COLOR */ "Ingress Final-Resolution-Color-Table. Address to this table: - bits 3:0 - DP-Command - bits 5:4 - In-Color - bits 7:6 - Resolved Color (from EgrColorRslvTable) - bits 8 - Global-Engine-Color (1'b0 - GREEN, 1'b1 - RED)", 13272 /* MRPS_ING_GLBL_ENG_DB */ "Ingress Global-Engine data base", 13273 /* MRPS_ING_GLBL_ENG_HAPM */ "Ingress Global-Engine Header-Append-Pointer mapping table. Map Header-Append-Pointer to Packet-Delta.", 13274 /* MRPS_ING_GLBL_ENG_HCPM */ "Ingress Global-Engine Header-Compensation-Profile mapping table. Map Header-Compensation-Profile to Packet-Delta.", 13275 /* MRPS_ING_GLBL_ENG_PP_PORT_MAP */ "Ingress Global-Engine PP-Port mapping table. Map PP-Port to Packet-Delta.", 13276 /* MRPS_ING_GLBL_ENG_PRFCFG */ "Ingress Global-Engine profile config memory", 13277 /* MRPS_ING_RSLV_COLOR */ "Ingress Resolution-Color-Table. Address to this table: - bits 1:0 - Engine-0 Color - bits 2 - Engine-0 Other-Bucket-Level - bits 4:3 - Engine-1 Color - bits 5 - Engine-1 Other-Bucket-Level - bits 7:6 - Engine-2 Color - bits 8 - Engine-2 Other-Bucket-Level - bits 9 - Engine-0-Profile / Dp-Command0 - bits 10 - Engine-1-Profile / Dp-Command1 - bits 11 - Engine-2-Profile / Dp-Command2 - bits 12 - Dp-Command3", 13278 /* MRPS_MCDA_DYNAMIC */ "MCD-A - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 13279 /* MRPS_MCDA_HEADER_APPEND_SIZE_PTR_MAP */ "MCDA - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13280 /* MRPS_MCDA_IN_PP_PORT_MAP */ "MCDA - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13281 /* MRPS_MCDA_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDA - Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13282 /* MRPS_MCDA_PCUC */ "MCDA - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 13283 /* MRPS_MCDA_PRFCFG_0 */ "MCD-A - profile configuration.\n First copy\n Both copies should be initialized the same", 13284 /* MRPS_MCDA_PRFCFG_1 */ "MCD-A - profile configuration.\n Second copy\n Both copies should be initialized the same", 13285 /* MRPS_MCDA_PRFCFG_SHARING_DIS */ "MRPS - MCD-A - profile configuration.\n This table define the profile config memory fields when the profile ShraingFlag is reset.", 13286 /* MRPS_MCDA_PRFCFG_SHARING_EN */ "MRPS - MCD-A - profile configuration.\n This table define the profile config memory fields when the profile ShraingFlag is set.", 13287 /* MRPS_MCDA_PRFSEL */ "MCD-A - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 13288 /* MRPS_MCDB_DYNAMIC */ "MCD-B - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 13289 /* MRPS_MCDB_HEADER_APPEND_SIZE_PTR_MAP */ "MCDB - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13290 /* MRPS_MCDB_IN_PP_PORT_MAP */ "MCDB - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13291 /* MRPS_MCDB_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDB- Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13292 /* MRPS_MCDB_PCUC */ "MCDB - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 13293 /* MRPS_MCDB_PRFCFG_0 */ "MCD-B - profile configuration.\n First copy\n Both copies should be initialized the same", 13294 /* MRPS_MCDB_PRFCFG_1 */ "MCD-B - profile configuration.\n Second copy\n Both copies should be initialized the same", 13295 /* MRPS_MCDB_PRFCFG_SHARING_DIS */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile Sharing Flag is reset.", 13296 /* MRPS_MCDB_PRFCFG_SHARING_EN */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is set.", 13297 /* MRPS_MCDB_PRFSEL */ "MCD-B - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - 32k-1", 13298 /* MRPS_MEM_220000 */ "INTERNAL", 13299 /* MRPS_PCD_MAP */ "Parallel color decision mapping table (64 entries x 4)\n Address (6) to this table is:\n On Dual mode:\n - bits 5:4 - MCD-B color decision\n - bits 3 - MCD-B other bucket has credits\n - bits 2:1 - MCD-A color decision\n - bits 0 - MCD-A other bucket has credits\n On Single mode:\n - bits 5:4 - MRPS1 color decision\n - bits 3 - MRPS1 other bucke ...", 13300 /* MTM_EGR_0_MCH_REP_REQ_RXI */ "Egress MC High Replication Request Rxi memory", 13301 /* MTM_EGR_0_MCL_REP_REQ_RXI */ "Egress MC Low Replication Request Rxi memory", 13302 /* MTM_EGR_0_TDM_REP_REQ_RXI */ "Egress TDM Replication Request Rxi memory", 13303 /* MTM_EGR_0_UC_REP_REQ_RXI */ "Egress UC Replication Request Rxi memory", 13304 /* MTM_EGR_1_MCH_REP_REQ_RXI */ "Egress MC High Replication Request Rxi memory", 13305 /* MTM_EGR_1_MCL_REP_REQ_RXI */ "Egress MC Low Replication Request Rxi memory", 13306 /* MTM_EGR_1_TDM_REP_REQ_RXI */ "Egress TDM Replication Request Rxi memory", 13307 /* MTM_EGR_1_UC_REP_REQ_RXI */ "Egress UC Replication Request Rxi memory", 13308 /* MTM_EGR_BITMAP_MAPPING_TABLE_A */ "Core0 Bitmap mapping table. Map Offset (3), Index(5) to destination.", 13309 /* MTM_EGR_BITMAP_MAPPING_TABLE_B */ "Core1 Bitmap mapping table. Map Offset (3), Index(5) to destination.", 13310 /* MTM_ING_0_MCH_REP_REQ_RXI */ "Ingress MC High Replication Request Rxi memory", 13311 /* MTM_ING_0_MCL_REP_REQ_RXI */ "Ingress MC Low Replication Request Rxi memory", 13312 /* MTM_ING_1_MCH_REP_REQ_RXI */ "Ingress MC High Replication Request Rxi memory", 13313 /* MTM_ING_1_MCL_REP_REQ_RXI */ "Ingress MC Low Replication Request Rxi memory", 13314 /* MTM_ING_BITMAP_MAPPING_TABLE */ "Bitmap mapping table. Map Offset (4), Index(5) to destination.", 13315 /* MTM_MCDB */ "Multicas Data Base", 13316 /* MTM_MCDB_FORMAT_BIER_EGR_INFO */ "MCDB egress BIER additional information", 13317 /* MTM_MCDB_FORMAT_BIER_ING_INFO */ "MCDB ingress BIER additional information", 13318 /* MTM_MCDB_FORMAT_BITMAP */ "MCDB Bitmap Format entry. Can be used by ingress and egress Note: - This entry holds the bitmap for copy generation.Each set bit in the bitmap, together with Offset, is mapped to a destination. Destination mapping is configured in MTM_ING_BITMAP_MAPPING_TABLE for ingress and MTM_EGR_BITMAP_MAPPING_TABLEs for egress.", 13319 /* MTM_MCDB_FORMAT_BITMAP_PTR */ "MCDB Bitmap-Pointer Format entry. Can be used by ingress and egress Note: - This entry holds the pointer to the first bitmap and the CUD which will be used on all copies", 13320 /* MTM_MCDB_FORMAT_DOUBLE */ "MCDB Double Format entry. (used by egress only)", 13321 /* MTM_MCDB_FORMAT_LINK_LIST */ "MCDB Link-List entry. Can be used by ingress and egress Note: - This entry holds a pointer to a link-list and a pointer for the next link-list", 13322 /* MTM_MCDB_FORMAT_SINGLE */ "MCDB Single Format entry", 13323 /* MTM_MCDB_FORMAT_TDM */ "MCDB egress TDM format", 13324 /* MTM_MCDB_FORMAT_X_4_BITMAP */ "Holds 4 bitmaps of 16 bits each. MC-ID1:0 is used to select one of the bitmaps. Offset used for destination mapping is 0x0. This format is enabled by setting MTM_X_4_BITMAP_FORMAT register, and cannot coexist with any other format.", 13325 /* MTRPS_EM_CONTEXT_COLOR */ "Color memory per context", 13326 /* MTRPS_EM_CONTEXT_SIZE_HIGH */ "Packet size memory per context.\n Higher 138 values\n (total of 330 contexts in Jericho)", 13327 /* MTRPS_EM_CONTEXT_SIZE_LOW */ "Packet size memory per context.\n Lower 192 values", 13328 /* MTRPS_EM_MCDA_DYNAMIC */ "MCD-A - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (1280-1)", 13329 /* MTRPS_EM_MCDA_HEADER_APPEND_SIZE_PTR_MAP */ "MCDA - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13330 /* MTRPS_EM_MCDA_IN_PP_PORT_MAP */ "MCDA - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13331 /* MTRPS_EM_MCDA_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDA - Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13332 /* MTRPS_EM_MCDA_PCUC */ "MCDA - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 13333 /* MTRPS_EM_MCDA_PRFCFG_0 */ "MCD-A - profile configuration.\n First copy\n Both copies should be initialized the same", 13334 /* MTRPS_EM_MCDA_PRFCFG_1 */ "MCD-A - profile configuration.\n Second copy\n Both copies should be initialized the same", 13335 /* MTRPS_EM_MCDA_PRFCFG_SHARING_DIS */ "MCD-A - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is reset.", 13336 /* MTRPS_EM_MCDA_PRFCFG_SHARING_EN */ "MCD-A - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is set.", 13337 /* MTRPS_EM_MCDA_PRFSEL */ "MCD-A - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (1280-1)", 13338 /* MTRPS_EM_MCDB_DYNAMIC */ "MCD-B - dynamic data\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (8-1)", 13339 /* MTRPS_EM_MCDB_HEADER_APPEND_SIZE_PTR_MAP */ "MCDB - Mapping Header Append Size Ptr (Out LIF Adjust Profile).\n Value = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13340 /* MTRPS_EM_MCDB_IN_PP_PORT_MAP */ "MCDB - Mapping In-PP-Port(8) into In-PP-Port-Profile(3)\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13341 /* MTRPS_EM_MCDB_IN_PP_PORT_MAP_AND_MTR_PRF_MAP */ "MCDB- Mapping In-PP-Port-Profile(6) into In-PP-Port-Size-Delta(8)\n Values = -128, +127\n Notes:\n - Each entry has 4 mappings\n - Indexes 0 - 256-1", 13342 /* MTRPS_EM_MCDB_PCUC */ "MCDB - Update color memory per context.\n Holds the LB (color) that was updated on SOP.", 13343 /* MTRPS_EM_MCDB_PRFCFG_0 */ "MCD-B - profile configuration.\n First copy\n Both copies should be initialized the same", 13344 /* MTRPS_EM_MCDB_PRFCFG_1 */ "MCD-B - profile configuration.\n Second copy\n Both copies should be initialized the same", 13345 /* MTRPS_EM_MCDB_PRFCFG_SHARING_DIS */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is reset.", 13346 /* MTRPS_EM_MCDB_PRFCFG_SHARING_EN */ "MCD-B - profile configuration.\n This table defines the profile config memory fields when the profile SharingFlag is set.", 13347 /* MTRPS_EM_MCDB_PRFSEL */ "MCD-B - index to profile mapping.\n Notes:\n - Each entry map 4 meters to profiles which are processed simultaneously.\n - Indexes 0 - (8-1)", 13348 /* MTRPS_EM_PCD_MAP */ "Parallel color decision mapping table (64 entries x 4)\n Address (6) to this table is:\n On Dual mode:\n - bits 5:4 - MCD-B color decision\n - bits 3 - MCD-B other bucket has credits\n - bits 2:1 - MCD-A color decision\n - bits 0 - MCD-A other bucket has credits\n On Single mode:\n - bits 5:4 - MRPS1 color decision\n - bits 3 - MRPS1 other bucke ...", 13349 /* MTU_PROFILE */ "MTU check table, Indexed by MTU_PROFILE_INDEX (5 bits)", 13350 /* MULTIPASS_LOOPBACK_BITMAP */ "Multipass Loopback Bitmap Register.", 13351 /* MULTIPASS_LOOPBACK_BITMAP_PIPE0 */ "Multipass Loopback Bitmap Register. This table contains a bitmap indicating the port(s) that are used for multipass processing (MiM, TRILL, etc.). It is a programming requirement that this bitmap only contains the internal loopback port.", 13352 /* MULTIPASS_LOOPBACK_BITMAP_PIPE1 */ "Multipass Loopback Bitmap Register. This table contains a bitmap indicating the port(s) that are used for multipass processing (MiM, TRILL, etc.). It is a programming requirement that this bitmap only contains the internal loopback port.", 13353 /* MULTIPASS_LOOPBACK_BITMAP_PIPE2 */ "Multipass Loopback Bitmap Register. This table contains a bitmap indicating the port(s) that are used for multipass processing (MiM, TRILL, etc.). It is a programming requirement that this bitmap only contains the internal loopback port.", 13354 /* MULTIPASS_LOOPBACK_BITMAP_PIPE3 */ "Multipass Loopback Bitmap Register. This table contains a bitmap indicating the port(s) that are used for multipass processing (MiM, TRILL, etc.). It is a programming requirement that this bitmap only contains the internal loopback port.", 13355 /* MY_STATION_PROFILE_1 */ "My Station Protocol Enable Profile 1.", 13356 /* MY_STATION_PROFILE_2 */ "My Station Protocol Enable Profile 1.", 13357 /* MY_STATION_TCAM */ "TCAM for MPLS My Station lookups - no associated data.", 13358 /* MY_STATION_TCAM_2 */ "TCAM for My Station 2 lookups - no associated data.", 13359 /* MY_STATION_TCAM_2_DATA_ONLY */ "Alias for data portion of MY_STATION_TCAM.", 13360 /* MY_STATION_TCAM_2_ENTRY_ONLY */ "Alias for TCAM portion of MY_STATION_TCAM_2.", 13361 /* MY_STATION_TCAM_DATA_ONLY */ "TCAM for MPLS My Station lookups - no associated data.", 13362 /* MY_STATION_TCAM_ENTRY_ONLY */ "TCAM for MPLS My Station lookups - no associated data.", 13363 /* NBIH_RX_DATA_HRF_MEMA_CTRL */ "rx CTRL memory n for ILKN ports - Data Hrf", 13364 /* NBIH_RX_DATA_HRF_MEMA_DATA */ "Rx DATA memory n for ILKN ports - Data Hrf", 13365 /* NBIH_RX_DATA_HRF_MEMB_CTRL */ "rx CTRL memory n for ILKN ports - Data Hrf", 13366 /* NBIH_RX_DATA_HRF_MEMB_DATA */ "Rx DATA memory n for ILKN ports - Data Hrf", 13367 /* NBIH_RX_DATA_HRF_MEMC_CTRL */ "rx CTRL memory n for ILKN ports - Data Hrf", 13368 /* NBIH_RX_DATA_HRF_MEMC_DATA */ "Rx DATA memory n for ILKN ports - Data Hrf", 13369 /* NBIH_RX_DATA_HRF_MEMD_CTRL */ "rx CTRL memory n for ILKN ports - Data Hrf", 13370 /* NBIH_RX_DATA_HRF_MEMD_DATA */ "Rx DATA memory n for ILKN ports - Data Hrf", 13371 /* NBIH_RX_MEMA_0_QMLF */ "rx memory a n", 13372 /* NBIH_RX_MEMA_1_QMLF */ "rx memory a n", 13373 /* NBIH_RX_MEMA_2_QMLF */ "rx memory a n", 13374 /* NBIH_RX_MEMA_3_QMLF */ "rx memory a n", 13375 /* NBIH_RX_MEMA_4_QMLF */ "rx memory a n", 13376 /* NBIH_RX_MEMB_0_QMLF */ "rx memory b n", 13377 /* NBIH_RX_MEMB_1_QMLF */ "rx memory b n", 13378 /* NBIH_RX_MEMB_2_QMLF */ "rx memory b n", 13379 /* NBIH_RX_MEMB_3_QMLF */ "rx memory b n", 13380 /* NBIH_RX_MEMB_4_QMLF */ "rx memory b n", 13381 /* NBIH_RX_MEMC_0_QMLF */ "rx memory c n", 13382 /* NBIH_RX_MEMC_1_QMLF */ "rx memory c n", 13383 /* NBIH_RX_MEMC_2_QMLF */ "rx memory c n", 13384 /* NBIH_RX_MEMC_3_QMLF */ "rx memory c n", 13385 /* NBIH_RX_MEMC_4_QMLF */ "rx memory c n", 13386 /* NBIH_RX_MEMD_0_QMLF */ "rx memory d n", 13387 /* NBIH_RX_MEMD_1_QMLF */ "rx memory d n", 13388 /* NBIH_RX_MEMD_2_QMLF */ "rx memory d n", 13389 /* NBIH_RX_MEMD_3_QMLF */ "rx memory d n", 13390 /* NBIH_RX_MEMD_4_QMLF */ "rx memory d n", 13391 /* NBIH_RX_TDM_HRF_MEMA_CTRL */ "rx CTRL memory n for ILKN ports - tdm Hrf", 13392 /* NBIH_RX_TDM_HRF_MEMA_DATA */ "Rx DATA memory n for ILKN ports - tdm Hrf", 13393 /* NBIH_RX_TDM_HRF_MEMB_CTRL */ "rx CTRL memory n for ILKN ports - tdm Hrf", 13394 /* NBIH_RX_TDM_HRF_MEMB_DATA */ "Rx DATA memory n for ILKN ports - tdm Hrf", 13395 /* NBIH_RX_TDM_HRF_MEMC_CTRL */ "rx CTRL memory n for ILKN ports - tdm Hrf", 13396 /* NBIH_RX_TDM_HRF_MEMC_DATA */ "Rx DATA memory n for ILKN ports - tdm Hrf", 13397 /* NBIH_RX_TDM_HRF_MEMD_CTRL */ "rx CTRL memory n for ILKN ports - tdm Hrf", 13398 /* NBIH_RX_TDM_HRF_MEMD_DATA */ "Rx DATA memory n for ILKN ports - tdm Hrf", 13399 /* NBIH_TX_ELK_RXI */ "tx elk RXI memory n", 13400 /* NBIH_TX_HRF_MEMA_CTRL */ "tx CTRL memory n for ILKN ports", 13401 /* NBIH_TX_HRF_MEMA_DATA */ "tx DATA memory n for ILKN ports", 13402 /* NBIH_TX_HRF_MEMB_CTRL */ "tx CTRL memory n for ILKN ports", 13403 /* NBIH_TX_HRF_MEMB_DATA */ "tx DATA memory n for ILKN ports", 13404 /* NBIH_TX_MEMA_CTRL */ "tx CTRL memory n for PML ports (12.5G SerDes)", 13405 /* NBIH_TX_MEMA_DATA */ "tx DATA memory n for PML ports (12.5G SerDes)", 13406 /* NBIH_TX_MEMB_CTRL */ "tx CTRL memory n for PML ports (12.5G SerDes)", 13407 /* NBIH_TX_MEMB_DATA */ "tx DATA memory n for PML ports (12.5G SerDes)", 13408 /* NBIH_TX_SIF_RXI */ "tx SIF RXI memory n", 13409 /* NBIL_RX_DATA_HRF_MEMA_CTRL */ "rx CTRL memory for ILKN ports - Data Hrf", 13410 /* NBIL_RX_DATA_HRF_MEMA_DATA */ "Rx DATA memory n for ILKN ports - Data Hrf", 13411 /* NBIL_RX_DATA_HRF_MEMB_CTRL */ "rx CTRL memory for ILKN ports - Data Hrf", 13412 /* NBIL_RX_DATA_HRF_MEMB_DATA */ "Rx DATA memory for ILKN ports - Data Hrf", 13413 /* NBIL_RX_DATA_HRF_MEMC_CTRL */ "rx CTRL memory for ILKN ports - Data Hrf", 13414 /* NBIL_RX_DATA_HRF_MEMC_DATA */ "Rx DATA memory for ILKN ports - Data Hrf", 13415 /* NBIL_RX_DATA_HRF_MEMD_CTRL */ "rx CTRL memory for ILKN ports - Data Hrf", 13416 /* NBIL_RX_DATA_HRF_MEMD_DATA */ "Rx DATA memory for ILKN ports - Data Hrf", 13417 /* NBIL_RX_MEMA_0_QMLF */ "rx memory a n", 13418 /* NBIL_RX_MEMA_1_QMLF */ "rx memory a n", 13419 /* NBIL_RX_MEMA_2_QMLF */ "rx memory a n", 13420 /* NBIL_RX_MEMA_3_QMLF */ "rx memory a n", 13421 /* NBIL_RX_MEMA_4_QMLF */ "rx memory a n", 13422 /* NBIL_RX_MEMB_0_QMLF */ "rx memory b n", 13423 /* NBIL_RX_MEMB_1_QMLF */ "rx memory b n", 13424 /* NBIL_RX_MEMB_2_QMLF */ "rx memory b n", 13425 /* NBIL_RX_MEMB_3_QMLF */ "rx memory b n", 13426 /* NBIL_RX_MEMB_4_QMLF */ "rx memory b n", 13427 /* NBIL_RX_MEMC_0_QMLF */ "rx memory c n", 13428 /* NBIL_RX_MEMC_1_QMLF */ "rx memory c n", 13429 /* NBIL_RX_MEMC_2_QMLF */ "rx memory c n", 13430 /* NBIL_RX_MEMC_3_QMLF */ "rx memory c n", 13431 /* NBIL_RX_MEMC_4_QMLF */ "rx memory c n", 13432 /* NBIL_RX_MEMD_0_QMLF */ "rx memory d n", 13433 /* NBIL_RX_MEMD_1_QMLF */ "rx memory d n", 13434 /* NBIL_RX_MEMD_2_QMLF */ "rx memory d n", 13435 /* NBIL_RX_MEMD_3_QMLF */ "rx memory d n", 13436 /* NBIL_RX_MEMD_4_QMLF */ "rx memory d n", 13437 /* NBIL_RX_TDM_HRF_MEMA_CTRL */ "rx CTRL memory for ILKN ports - tdm Hrf", 13438 /* NBIL_RX_TDM_HRF_MEMA_DATA */ "Rx DATA memory for ILKN ports - tdm Hrf", 13439 /* NBIL_RX_TDM_HRF_MEMB_CTRL */ "rx CTRL memory for ILKN ports - tdm Hrf", 13440 /* NBIL_RX_TDM_HRF_MEMB_DATA */ "Rx DATA memory for ILKN ports - tdm Hrf", 13441 /* NBIL_RX_TDM_HRF_MEMC_CTRL */ "rx CTRL memory for ILKN ports - tdm Hrf", 13442 /* NBIL_RX_TDM_HRF_MEMC_DATA */ "Rx DATA memory for ILKN ports - tdm Hrf", 13443 /* NBIL_RX_TDM_HRF_MEMD_CTRL */ "rx CTRL memory for ILKN ports - tdm Hrf", 13444 /* NBIL_RX_TDM_HRF_MEMD_DATA */ "Rx DATA memory for ILKN ports - tdm Hrf", 13445 /* NBIL_TX_ELK_RXI */ "tx elk RXI memory n", 13446 /* NBIL_TX_HRF_MEMA_CTRL */ "tx CTRL memory for ILKN ports", 13447 /* NBIL_TX_HRF_MEMA_DATA */ "tx DATA memory for ILKN ports", 13448 /* NBIL_TX_HRF_MEMB_CTRL */ "tx CTRL memory for ILKN ports", 13449 /* NBIL_TX_HRF_MEMB_DATA */ "tx DATA memory for ILKN ports", 13450 /* NBIL_TX_MEMA_CTRL */ "tx CTRL memory n for PML ports (12.5G SerDes)", 13451 /* NBIL_TX_MEMA_DATA */ "tx DATA memory n for PML ports (12.5G SerDes)", 13452 /* NBIL_TX_MEMB_CTRL */ "tx CTRL memory n for PML ports (12.5G SerDes)", 13453 /* NBIL_TX_MEMB_DATA */ "tx DATA memory n for PML ports (12.5G SerDes)", 13454 /* NBIL_TX_SIF_RXI */ "tx SIF RXI memory n", 13455 /* NBI_EGR_MEM_CTRL */ "tx ctrl memory", 13456 /* NBI_EGR_MEM_DATA */ "tx data memory", 13457 /* NBI_ING_MEM_CTRL */ "rx ctrl memory", 13458 /* NBI_ING_MEM_DATA */ "rx data memory", 13459 /* NBI_MEM_92000 */ "INTERNAL", 13460 /* NBI_MEM_93000 */ "INTERNAL", 13461 /* NBI_MEM_94000 */ "INTERNAL", 13462 /* NBI_MEM_95000 */ "INTERNAL", 13463 /* NBI_MLF_RX_MEM_A_CTRL */ "rxn controls memory a", 13464 /* NBI_MLF_RX_MEM_B_CTRL */ "rxn controls memory b", 13465 /* NBI_MLF_TX_MEM_CTRL */ "txn controls memory", 13466 /* NBI_RBINS_MEM */ "Statistics memory for the RX bins. Each memory index refers to a port from 0-27. Each port has 14 bins (described at StatReadCntId). This memory can be read via the special Statistics mechanism.", 13467 /* NBI_RLENG_MEM */ "Statistics memory for the RX octets. Each NIF port has 1 entry.", 13468 /* NBI_RPKTS_MEM */ "Statistics memory for the RX BURSTS count. Each NIF port has 2 entries; the first is for good bursts count and the second is for error bursts count.", 13469 /* NBI_RTYPE_MEM */ "Statistics memory for the RX MCAST and BCAST. Each NIF port has 2 entries; the first is its BCAST count and the second is its MCAST count.", 13470 /* NBI_TBINS_MEM */ "Statistics memory for the TX bins. Each memory index refers to a port from 0-27. Each port has 14 bins (described at StatReadCntId). This memory can be read via the special Statistics mechanism.", 13471 /* NBI_TLENG_MEM */ "Statistics memory for the TX octets. Each NIF port has 1 entry.", 13472 /* NBI_TPKTS_MEM */ "Statistics memory for the TX BURSTS count. Each NIF port has 2 entries; the first is for good bursts count and the second is for error bursts count.", 13473 /* NBI_TTYPE_MEM */ "Statistics memory for the TX MCAST and BCAST. Each NIF port has 2 entries; the first is its BCAST count and the second is its MCAST count.", 13474 /* NETID_BITMAP */ "NET_ID indication mapping. Index: PKT.NET_ID.", 13475 /* NHI_GROUP_TC_PROFILE */ "NHI group offset based on {tc_profile_index, int_pri}", 13476 /* NIF_PML_RX_MEMA_0_QMLF */ "rx memory a n", 13477 /* NIF_PML_RX_MEMA_1_QMLF */ "rx memory a n", 13478 /* NIF_PML_RX_MEMA_2_QMLF */ "rx memory a n", 13479 /* NIF_PML_RX_MEMA_3_QMLF */ "rx memory a n", 13480 /* NIF_PML_RX_MEMA_4_QMLF */ "rx memory a n", 13481 /* NIF_PML_RX_MEMB_0_QMLF */ "rx memory b n", 13482 /* NIF_PML_RX_MEMB_1_QMLF */ "rx memory b n", 13483 /* NIF_PML_RX_MEMB_2_QMLF */ "rx memory b n", 13484 /* NIF_PML_RX_MEMB_3_QMLF */ "rx memory b n", 13485 /* NIF_PML_RX_MEMB_4_QMLF */ "rx memory b n", 13486 /* NIF_PML_RX_MEMC_0_QMLF */ "rx memory c n", 13487 /* NIF_PML_RX_MEMC_1_QMLF */ "rx memory c n", 13488 /* NIF_PML_RX_MEMC_2_QMLF */ "rx memory c n", 13489 /* NIF_PML_RX_MEMC_3_QMLF */ "rx memory c n", 13490 /* NIF_PML_RX_MEMC_4_QMLF */ "rx memory c n", 13491 /* NIF_PML_RX_MEMD_0_QMLF */ "rx memory d n", 13492 /* NIF_PML_RX_MEMD_1_QMLF */ "rx memory d n", 13493 /* NIF_PML_RX_MEMD_2_QMLF */ "rx memory d n", 13494 /* NIF_PML_RX_MEMD_3_QMLF */ "rx memory d n", 13495 /* NIF_PML_RX_MEMD_4_QMLF */ "rx memory d n", 13496 /* NIF_PML_TX_MEMA_CTRL */ "tx CTRL memory n for PML ports (12.5G SerDes)", 13497 /* NIF_PML_TX_MEMA_DATA */ "tx DATA memory n for PML ports (12.5G SerDes)", 13498 /* NIF_PML_TX_MEMB_CTRL */ "tx CTRL memory n for PML ports (12.5G SerDes)", 13499 /* NIF_PML_TX_MEMB_DATA */ "tx DATA memory n for PML ports (12.5G SerDes)", 13500 /* NIF_PMX_RX_MEMA_0_QMLF_2 */ "rx memory a n", 13501 /* NIF_PMX_RX_MEMA_0_QMLF_3 */ "rx memory a n", 13502 /* NIF_PMX_RX_MEMA_0_QMLF_4 */ "rx memory a n", 13503 /* NIF_PMX_RX_MEMA_0_QMLF_5 */ "rx memory a n", 13504 /* NIF_PMX_RX_MEMA_0_QMLF_6 */ "rx memory a n", 13505 /* NIF_PMX_RX_MEMA_0_QMLF_7 */ "rx memory a n", 13506 /* NIF_PMX_RX_MEMA_0_QMLF_8 */ "rx memory a n", 13507 /* NIF_PMX_RX_MEMA_1_QMLF_2 */ "rx memory a n", 13508 /* NIF_PMX_RX_MEMA_1_QMLF_3 */ "rx memory a n", 13509 /* NIF_PMX_RX_MEMA_1_QMLF_4 */ "rx memory a n", 13510 /* NIF_PMX_RX_MEMA_1_QMLF_5 */ "rx memory a n", 13511 /* NIF_PMX_RX_MEMA_1_QMLF_6 */ "rx memory a n", 13512 /* NIF_PMX_RX_MEMA_1_QMLF_7 */ "rx memory a n", 13513 /* NIF_PMX_RX_MEMA_1_QMLF_8 */ "rx memory a n", 13514 /* NIF_PMX_RX_MEMA_2_QMLF_2 */ "rx memory a n", 13515 /* NIF_PMX_RX_MEMA_2_QMLF_3 */ "rx memory a n", 13516 /* NIF_PMX_RX_MEMA_2_QMLF_4 */ "rx memory a n", 13517 /* NIF_PMX_RX_MEMA_2_QMLF_5 */ "rx memory a n", 13518 /* NIF_PMX_RX_MEMA_2_QMLF_6 */ "rx memory a n", 13519 /* NIF_PMX_RX_MEMA_2_QMLF_7 */ "rx memory a n", 13520 /* NIF_PMX_RX_MEMA_2_QMLF_8 */ "rx memory a n", 13521 /* NIF_PMX_RX_MEMA_3_QMLF_2 */ "rx memory a n", 13522 /* NIF_PMX_RX_MEMA_3_QMLF_3 */ "rx memory a n", 13523 /* NIF_PMX_RX_MEMA_3_QMLF_4 */ "rx memory a n", 13524 /* NIF_PMX_RX_MEMA_3_QMLF_5 */ "rx memory a n", 13525 /* NIF_PMX_RX_MEMA_3_QMLF_6 */ "rx memory a n", 13526 /* NIF_PMX_RX_MEMA_3_QMLF_7 */ "rx memory a n", 13527 /* NIF_PMX_RX_MEMA_3_QMLF_8 */ "rx memory a n", 13528 /* NIF_PMX_RX_MEMA_4_QMLF_2 */ "rx memory a n", 13529 /* NIF_PMX_RX_MEMA_4_QMLF_3 */ "rx memory a n", 13530 /* NIF_PMX_RX_MEMA_4_QMLF_4 */ "rx memory a n", 13531 /* NIF_PMX_RX_MEMA_4_QMLF_5 */ "rx memory a n", 13532 /* NIF_PMX_RX_MEMA_4_QMLF_6 */ "rx memory a n", 13533 /* NIF_PMX_RX_MEMA_4_QMLF_7 */ "rx memory a n", 13534 /* NIF_PMX_RX_MEMA_4_QMLF_8 */ "rx memory a n", 13535 /* NIF_PMX_RX_MEMB_0_QMLF_2 */ "rx memory b n", 13536 /* NIF_PMX_RX_MEMB_0_QMLF_3 */ "rx memory b n", 13537 /* NIF_PMX_RX_MEMB_0_QMLF_4 */ "rx memory b n", 13538 /* NIF_PMX_RX_MEMB_0_QMLF_5 */ "rx memory b n", 13539 /* NIF_PMX_RX_MEMB_0_QMLF_6 */ "rx memory b n", 13540 /* NIF_PMX_RX_MEMB_0_QMLF_7 */ "rx memory b n", 13541 /* NIF_PMX_RX_MEMB_0_QMLF_8 */ "rx memory b n", 13542 /* NIF_PMX_RX_MEMB_1_QMLF_2 */ "rx memory b n", 13543 /* NIF_PMX_RX_MEMB_1_QMLF_3 */ "rx memory b n", 13544 /* NIF_PMX_RX_MEMB_1_QMLF_4 */ "rx memory b n", 13545 /* NIF_PMX_RX_MEMB_1_QMLF_5 */ "rx memory b n", 13546 /* NIF_PMX_RX_MEMB_1_QMLF_6 */ "rx memory b n", 13547 /* NIF_PMX_RX_MEMB_1_QMLF_7 */ "rx memory b n", 13548 /* NIF_PMX_RX_MEMB_1_QMLF_8 */ "rx memory b n", 13549 /* NIF_PMX_RX_MEMB_2_QMLF_2 */ "rx memory b n", 13550 /* NIF_PMX_RX_MEMB_2_QMLF_3 */ "rx memory b n", 13551 /* NIF_PMX_RX_MEMB_2_QMLF_4 */ "rx memory b n", 13552 /* NIF_PMX_RX_MEMB_2_QMLF_5 */ "rx memory b n", 13553 /* NIF_PMX_RX_MEMB_2_QMLF_6 */ "rx memory b n", 13554 /* NIF_PMX_RX_MEMB_2_QMLF_7 */ "rx memory b n", 13555 /* NIF_PMX_RX_MEMB_2_QMLF_8 */ "rx memory b n", 13556 /* NIF_PMX_RX_MEMB_3_QMLF_2 */ "rx memory b n", 13557 /* NIF_PMX_RX_MEMB_3_QMLF_3 */ "rx memory b n", 13558 /* NIF_PMX_RX_MEMB_3_QMLF_4 */ "rx memory b n", 13559 /* NIF_PMX_RX_MEMB_3_QMLF_5 */ "rx memory b n", 13560 /* NIF_PMX_RX_MEMB_3_QMLF_6 */ "rx memory b n", 13561 /* NIF_PMX_RX_MEMB_3_QMLF_7 */ "rx memory b n", 13562 /* NIF_PMX_RX_MEMB_3_QMLF_8 */ "rx memory b n", 13563 /* NIF_PMX_RX_MEMB_4_QMLF_2 */ "rx memory b n", 13564 /* NIF_PMX_RX_MEMB_4_QMLF_3 */ "rx memory b n", 13565 /* NIF_PMX_RX_MEMB_4_QMLF_4 */ "rx memory b n", 13566 /* NIF_PMX_RX_MEMB_4_QMLF_5 */ "rx memory b n", 13567 /* NIF_PMX_RX_MEMB_4_QMLF_6 */ "rx memory b n", 13568 /* NIF_PMX_RX_MEMB_4_QMLF_7 */ "rx memory b n", 13569 /* NIF_PMX_RX_MEMB_4_QMLF_8 */ "rx memory b n", 13570 /* NIF_PMX_RX_MEMC_0_QMLF_2 */ "rx memory c n", 13571 /* NIF_PMX_RX_MEMC_0_QMLF_3 */ "rx memory c n", 13572 /* NIF_PMX_RX_MEMC_0_QMLF_4 */ "rx memory c n", 13573 /* NIF_PMX_RX_MEMC_0_QMLF_5 */ "rx memory c n", 13574 /* NIF_PMX_RX_MEMC_0_QMLF_6 */ "rx memory c n", 13575 /* NIF_PMX_RX_MEMC_0_QMLF_7 */ "rx memory c n", 13576 /* NIF_PMX_RX_MEMC_0_QMLF_8 */ "rx memory c n", 13577 /* NIF_PMX_RX_MEMC_1_QMLF_2 */ "rx memory c n", 13578 /* NIF_PMX_RX_MEMC_1_QMLF_3 */ "rx memory c n", 13579 /* NIF_PMX_RX_MEMC_1_QMLF_4 */ "rx memory c n", 13580 /* NIF_PMX_RX_MEMC_1_QMLF_5 */ "rx memory c n", 13581 /* NIF_PMX_RX_MEMC_1_QMLF_6 */ "rx memory c n", 13582 /* NIF_PMX_RX_MEMC_1_QMLF_7 */ "rx memory c n", 13583 /* NIF_PMX_RX_MEMC_1_QMLF_8 */ "rx memory c n", 13584 /* NIF_PMX_RX_MEMC_2_QMLF_2 */ "rx memory c n", 13585 /* NIF_PMX_RX_MEMC_2_QMLF_3 */ "rx memory c n", 13586 /* NIF_PMX_RX_MEMC_2_QMLF_4 */ "rx memory c n", 13587 /* NIF_PMX_RX_MEMC_2_QMLF_5 */ "rx memory c n", 13588 /* NIF_PMX_RX_MEMC_2_QMLF_6 */ "rx memory c n", 13589 /* NIF_PMX_RX_MEMC_2_QMLF_7 */ "rx memory c n", 13590 /* NIF_PMX_RX_MEMC_2_QMLF_8 */ "rx memory c n", 13591 /* NIF_PMX_RX_MEMC_3_QMLF_2 */ "rx memory c n", 13592 /* NIF_PMX_RX_MEMC_3_QMLF_3 */ "rx memory c n", 13593 /* NIF_PMX_RX_MEMC_3_QMLF_4 */ "rx memory c n", 13594 /* NIF_PMX_RX_MEMC_3_QMLF_5 */ "rx memory c n", 13595 /* NIF_PMX_RX_MEMC_3_QMLF_6 */ "rx memory c n", 13596 /* NIF_PMX_RX_MEMC_3_QMLF_7 */ "rx memory c n", 13597 /* NIF_PMX_RX_MEMC_3_QMLF_8 */ "rx memory c n", 13598 /* NIF_PMX_RX_MEMC_4_QMLF_2 */ "rx memory c n", 13599 /* NIF_PMX_RX_MEMC_4_QMLF_3 */ "rx memory c n", 13600 /* NIF_PMX_RX_MEMC_4_QMLF_4 */ "rx memory c n", 13601 /* NIF_PMX_RX_MEMC_4_QMLF_5 */ "rx memory c n", 13602 /* NIF_PMX_RX_MEMC_4_QMLF_6 */ "rx memory c n", 13603 /* NIF_PMX_RX_MEMC_4_QMLF_7 */ "rx memory c n", 13604 /* NIF_PMX_RX_MEMC_4_QMLF_8 */ "rx memory c n", 13605 /* NIF_PMX_RX_MEMD_0_QMLF_2 */ "rx memory d n", 13606 /* NIF_PMX_RX_MEMD_0_QMLF_3 */ "rx memory d n", 13607 /* NIF_PMX_RX_MEMD_0_QMLF_4 */ "rx memory d n", 13608 /* NIF_PMX_RX_MEMD_0_QMLF_5 */ "rx memory d n", 13609 /* NIF_PMX_RX_MEMD_0_QMLF_6 */ "rx memory d n", 13610 /* NIF_PMX_RX_MEMD_0_QMLF_7 */ "rx memory d n", 13611 /* NIF_PMX_RX_MEMD_0_QMLF_8 */ "rx memory d n", 13612 /* NIF_PMX_RX_MEMD_1_QMLF_2 */ "rx memory d n", 13613 /* NIF_PMX_RX_MEMD_1_QMLF_3 */ "rx memory d n", 13614 /* NIF_PMX_RX_MEMD_1_QMLF_4 */ "rx memory d n", 13615 /* NIF_PMX_RX_MEMD_1_QMLF_5 */ "rx memory d n", 13616 /* NIF_PMX_RX_MEMD_1_QMLF_6 */ "rx memory d n", 13617 /* NIF_PMX_RX_MEMD_1_QMLF_7 */ "rx memory d n", 13618 /* NIF_PMX_RX_MEMD_1_QMLF_8 */ "rx memory d n", 13619 /* NIF_PMX_RX_MEMD_2_QMLF_2 */ "rx memory d n", 13620 /* NIF_PMX_RX_MEMD_2_QMLF_3 */ "rx memory d n", 13621 /* NIF_PMX_RX_MEMD_2_QMLF_4 */ "rx memory d n", 13622 /* NIF_PMX_RX_MEMD_2_QMLF_5 */ "rx memory d n", 13623 /* NIF_PMX_RX_MEMD_2_QMLF_6 */ "rx memory d n", 13624 /* NIF_PMX_RX_MEMD_2_QMLF_7 */ "rx memory d n", 13625 /* NIF_PMX_RX_MEMD_2_QMLF_8 */ "rx memory d n", 13626 /* NIF_PMX_RX_MEMD_3_QMLF_2 */ "rx memory d n", 13627 /* NIF_PMX_RX_MEMD_3_QMLF_3 */ "rx memory d n", 13628 /* NIF_PMX_RX_MEMD_3_QMLF_4 */ "rx memory d n", 13629 /* NIF_PMX_RX_MEMD_3_QMLF_5 */ "rx memory d n", 13630 /* NIF_PMX_RX_MEMD_3_QMLF_6 */ "rx memory d n", 13631 /* NIF_PMX_RX_MEMD_3_QMLF_7 */ "rx memory d n", 13632 /* NIF_PMX_RX_MEMD_3_QMLF_8 */ "rx memory d n", 13633 /* NIF_PMX_RX_MEMD_4_QMLF_2 */ "rx memory d n", 13634 /* NIF_PMX_RX_MEMD_4_QMLF_3 */ "rx memory d n", 13635 /* NIF_PMX_RX_MEMD_4_QMLF_4 */ "rx memory d n", 13636 /* NIF_PMX_RX_MEMD_4_QMLF_5 */ "rx memory d n", 13637 /* NIF_PMX_RX_MEMD_4_QMLF_6 */ "rx memory d n", 13638 /* NIF_PMX_RX_MEMD_4_QMLF_7 */ "rx memory d n", 13639 /* NIF_PMX_RX_MEMD_4_QMLF_8 */ "rx memory d n", 13640 /* NIF_PMX_TX_MEMA_2_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13641 /* NIF_PMX_TX_MEMA_2_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13642 /* NIF_PMX_TX_MEMA_3_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13643 /* NIF_PMX_TX_MEMA_3_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13644 /* NIF_PMX_TX_MEMA_4_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13645 /* NIF_PMX_TX_MEMA_4_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13646 /* NIF_PMX_TX_MEMA_5_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13647 /* NIF_PMX_TX_MEMA_5_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13648 /* NIF_PMX_TX_MEMA_6_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13649 /* NIF_PMX_TX_MEMA_6_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13650 /* NIF_PMX_TX_MEMA_7_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13651 /* NIF_PMX_TX_MEMA_7_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13652 /* NIF_PMX_TX_MEMA_8_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13653 /* NIF_PMX_TX_MEMA_8_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13654 /* NIF_PMX_TX_MEMB_2_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13655 /* NIF_PMX_TX_MEMB_2_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13656 /* NIF_PMX_TX_MEMB_3_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13657 /* NIF_PMX_TX_MEMB_3_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13658 /* NIF_PMX_TX_MEMB_4_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13659 /* NIF_PMX_TX_MEMB_4_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13660 /* NIF_PMX_TX_MEMB_5_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13661 /* NIF_PMX_TX_MEMB_5_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13662 /* NIF_PMX_TX_MEMB_6_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13663 /* NIF_PMX_TX_MEMB_6_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13664 /* NIF_PMX_TX_MEMB_7_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13665 /* NIF_PMX_TX_MEMB_7_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13666 /* NIF_PMX_TX_MEMB_8_CTRL */ "tx CTRL memory n for PMX ports (12.5G SerDes)", 13667 /* NIF_PMX_TX_MEMB_8_DATA */ "tx DATA memory n for PMX ports (12.5G SerDes)", 13668 /* NIF_TX_SIF_RXI */ "tx SIF RXI memory", 13669 /* NONUCAST_TRUNK_BLOCK_MASK */ "Multicast and Broadcast Trunk Block Mask Table", 13670 /* NTP_TIME */ "Run-time value of NTP time", 13671 /* NUM_QCN_CNM_RECEIVED */ "Counts the number of QCN CNMs that are destined to egress on the associated (Egress Port, Priority)HG-Trunk DLB Control.", 13672 /* OAMP_CLS_FLEX_CRC_TCAM */ "Map Trap Code and Opcode/channel to mask on first 128 bytes of OAM pdu for CRC claculation", 13673 /* OAMP_CLS_TRAP_CODE_TCAM */ "Map Trap Code and Opcode/channel to mask on first 128 bytes of OAM pdu for CRC claculation", 13674 /* OAMP_DM_TRIGER */ "", 13675 /* OAMP_FLEX_VER_MASK_TEMP */ "", 13676 /* OAMP_FLOW_STAT_10_SEC_ENTRY_1 */ "Flow statistics for 10 seconds, occupy entries 128-255, each flow occupies four entries.", 13677 /* OAMP_FLOW_STAT_10_SEC_ENTRY_2 */ "Flow statistics for 10 seconds, occupy entries 128-255, each flow occupies four entries.", 13678 /* OAMP_FLOW_STAT_10_SEC_ENTRY_3 */ "Flow statistics for 10 seconds, occupy entries 128-255, each flow occupies four entries.", 13679 /* OAMP_FLOW_STAT_1_SEC_ENTRY_1 */ "Flow statistics for 1 second, occupy entries 0-127, each flow occupies four entries.", 13680 /* OAMP_FLOW_STAT_1_SEC_ENTRY_2 */ "Flow statistics for 1 second, occupy entries 0-127, each flow occupies four entries.", 13681 /* OAMP_FLOW_STAT_1_SEC_ENTRY_3 */ "Flow statistics for 1 second, occupy entries 0-127, each flow occupies four entries.", 13682 /* OAMP_FLOW_STAT_ACCUM_ENTRY_1 */ "Flow accumulated statistics, occupy entries 256-383, each flow occupies four entries.", 13683 /* OAMP_FLOW_STAT_ACCUM_ENTRY_2 */ "Flow accumulated statistics, occupy entries 256-383, each flow occupies four entries.", 13684 /* OAMP_FLOW_STAT_ACCUM_ENTRY_3 */ "Flow accumulated statistics, occupy entries 256-383, each flow occupies four entries.", 13685 /* OAMP_FLOW_STAT_ACCUM_ENTRY_4 */ "", 13686 /* OAMP_FLOW_STAT_ACCUM_ENTRY_34 */ "Flow accumulated statistics, occupy entries 256-383, each flow occupies four entries.", 13687 /* OAMP_ITR_DATA_FIFO */ "INTERNAL", 13688 /* OAMP_ITR_PKT_FIFO */ "INTERNAL", 13689 /* OAMP_LMM_DA_NIC_TABLE */ "Translate LmmDaNicProfile to LmmDaNic - 3 leaset significant bytes of the LMM o ETH , mac DA", 13690 /* OAMP_LOCAL_PORT_2_SYSTEM_PORT */ "Map local port to system port", 13691 /* OAMP_MEM_20000 */ "INTERNAL", 13692 /* OAMP_MEM_40000 */ "INTERNAL", 13693 /* OAMP_MEM_50000 */ "INTERNAL", 13694 /* OAMP_MEM_60000 */ "INTERNAL", 13695 /* OAMP_MEM_70000 */ "INTERNAL", 13696 /* OAMP_MEM_80000 */ "INTERNAL", 13697 /* OAMP_MEM_90000 */ "INTERNAL", 13698 /* OAMP_MEM_100000 */ "INTERNAL", 13699 /* OAMP_MEM_150000 */ "INTERNAL", 13700 /* OAMP_MEM_180000 */ "INTERNAL", 13701 /* OAMP_MEM_190000 */ "INTERNAL", 13702 /* OAMP_MEM_210000 */ "INTERNAL", 13703 /* OAMP_MEM_220000 */ "INTERNAL", 13704 /* OAMP_MEM_270000 */ "INTERNAL", 13705 /* OAMP_MEM_290000 */ "INTERNAL", 13706 /* OAMP_MEM_340000 */ "INTERNAL", 13707 /* OAMP_MEM_350000 */ "INTERNAL", 13708 /* OAMP_MEM_430000 */ "INTERNAL", 13709 /* OAMP_MEM_440000 */ "INTERNAL", 13710 /* OAMP_MEM_450000 */ "INTERNAL", 13711 /* OAMP_MEM_460000 */ "INTERNAL", 13712 /* OAMP_MEM_470000 */ "INTERNAL", 13713 /* OAMP_MEM_480000 */ "INTERNAL", 13714 /* OAMP_MEM_490000 */ "INTERNAL", 13715 /* OAMP_MEM_500000 */ "INTERNAL", 13716 /* OAMP_MEM_510000 */ "INTERNAL", 13717 /* OAMP_MEM_520000 */ "INTERNAL", 13718 /* OAMP_MEM_1C0000 */ "INTERNAL", 13719 /* OAMP_MEM_2A0000 */ "INTERNAL", 13720 /* OAMP_MEM_2B0000 */ "INTERNAL", 13721 /* OAMP_MEM_4A0000 */ "INTERNAL", 13722 /* OAMP_MEM_4B0000 */ "INTERNAL", 13723 /* OAMP_MEM_4C0000 */ "INTERNAL", 13724 /* OAMP_MEM_4D0000 */ "INTERNAL", 13725 /* OAMP_MEM_4E0000 */ "INTERNAL", 13726 /* OAMP_MEM_4F0000 */ "INTERNAL", 13727 /* OAMP_MEM_B0000 */ "INTERNAL", 13728 /* OAMP_MEM_C0000 */ "INTERNAL", 13729 /* OAMP_MEM_D0000 */ "INTERNAL", 13730 /* OAMP_MEP_DB */ "MEP DB (eth)", 13731 /* OAMP_MEP_DB_BFD_CC_ON_MPLSTP */ "MEP DB (BFDCC over MPLSTP)", 13732 /* OAMP_MEP_DB_BFD_CV_ON_MPLSTP */ "MEP DB (BFDCV over MPLSTP)", 13733 /* OAMP_MEP_DB_BFD_ON_IPV4_MULTI_HOP */ "MEP DB (BFD over IPv4 multi hop)", 13734 /* OAMP_MEP_DB_BFD_ON_IPV4_MULTI_HOP_SHORT_STATIC_MDB_FORMAT */ "MEP DB (BFD over IPv4 multi hop) static parameters in MDB (complementing the short format)", 13735 /* OAMP_MEP_DB_BFD_ON_IPV4_ONE_HOP */ "MEP DB (BFD over IPv4 one hop)", 13736 /* OAMP_MEP_DB_BFD_ON_IPV4_ONE_HOP_SHORT_STATIC_MDB_FORMAT */ "MEP DB (BFD over IPv4 one hop) static parameters in MDB (complementing the short format)", 13737 /* OAMP_MEP_DB_BFD_ON_MPLS */ "MEP DB (BFD over MPLS)", 13738 /* OAMP_MEP_DB_BFD_ON_MPLS_SHORT_STATIC_MDB_FORMAT */ "MEP DB (BFD over MPLS) static parameters in MDB (complementing the short format)", 13739 /* OAMP_MEP_DB_BFD_ON_PWE */ "MEP DB (BFD over PWE)", 13740 /* OAMP_MEP_DB_BFD_ON_PWE_SHORT_STATIC_MDB_FORMAT */ "MEP DB (BFD over MPLS) static parameters in MDB (complementing the short format)", 13741 /* OAMP_MEP_DB_BFD_ON_PWE_STATIC_MDB_FORMAT_PART_1 */ "MEP DB (BFD on PWE) static parameters in MDB (complementing the offloaded format), part1", 13742 /* OAMP_MEP_DB_BFD_ON_PWE_STATIC_MDB_FORMAT_PART_2 */ "MEP DB (BFD on PWE) static parameters in MDB (complementing the offloaded format), part2", 13743 /* OAMP_MEP_DB_BFD_SHORT_FORMAT */ "MEP DB (All BFD formats) short format, with static parameters in MDB", 13744 /* OAMP_MEP_DB_CCM_ETH */ "MEP DB (eth)", 13745 /* OAMP_MEP_DB_CCM_ETH_SHORT_STATIC_MDB_FORMAT */ "MEP DB (eth) static parameters in MDB (complementing the short format)", 13746 /* OAMP_MEP_DB_CCM_ETH_STATIC_MDB_FORMAT_PART_1 */ "MEP DB (eth) static parameters in MDB (complementing the offloaded format), part1", 13747 /* OAMP_MEP_DB_CCM_ETH_STATIC_MDB_FORMAT_PART_2 */ "MEP DB (eth) static parameters in MDB (complementing the offloaded format), part2", 13748 /* OAMP_MEP_DB_CCM_Y_1731_SHORT_FORMAT */ "MEP DB (eth/Y1731oMPLSTP/Y1731oPWE) short format, with static parameters in MDB", 13749 /* OAMP_MEP_DB_DM_STAT */ "MEP DB (DM Stat entry)", 13750 /* OAMP_MEP_DB_DM_STAT_ONE_WAY */ "MEP DB (DM Stat entry one way delay)", 13751 /* OAMP_MEP_DB_DM_STAT_TWO_WAY */ "MEP DB (DM Stat entry twp way delay)", 13752 /* OAMP_MEP_DB_EXTRA_DATA_IN_MDB_HEADER */ "MEP DB Extra Data Format, when stored in MDB", 13753 /* OAMP_MEP_DB_EXTRA_DATA_IN_MDB_PAYLOAD */ "MEP DB Extra Data Format, when stored in MDB", 13754 /* OAMP_MEP_DB_EXT_DATA_HDR */ "MEP DB Extra data header", 13755 /* OAMP_MEP_DB_EXT_DATA_PLD */ "MEP DB Extra data", 13756 /* OAMP_MEP_DB_LM_DB */ "MEP DB (LM DB entry)", 13757 /* OAMP_MEP_DB_LM_STAT */ "MEP DB (LM Stat entry)", 13758 /* OAMP_MEP_DB_OFFLOADED_FORMAT_PART_1 */ "MEP DB (eth/Y1731oMPLSTP/Y1731oPWE/BFDoPWE) with static fields offloaded to MDB", 13759 /* OAMP_MEP_DB_OFFLOADED_FORMAT_PART_2 */ "MEP DB with static fields offloaded to MDB, part2", 13760 /* OAMP_MEP_DB_RFC_6374_ON_MPLSTP */ "MEP DB (rfc 6374)", 13761 /* OAMP_MEP_DB_Y_1731_ON_MPLSTP */ "MEP DB (Y1731 over MPLSTP)", 13762 /* OAMP_MEP_DB_Y_1731_ON_MPLSTP_SHORT_STATIC_MDB_FORMAT */ "MEP DB (Y1731 on MPLS-TP) static parameters in MDB (complementing the short format)", 13763 /* OAMP_MEP_DB_Y_1731_ON_MPLSTP_STATIC_MDB_FORMAT_PART_1 */ "MEP DB (Y1731 on MPLS-TP) static parameters in MDB (complementing the offloaded format), part1", 13764 /* OAMP_MEP_DB_Y_1731_ON_MPLSTP_STATIC_MDB_FORMAT_PART_2 */ "MEP DB (Y1731 on MPLS-TP) static parameters in MDB (complementing the offloaded format), part2", 13765 /* OAMP_MEP_DB_Y_1731_ON_PWE */ "MEP DB (Y1731 over PWE)", 13766 /* OAMP_MEP_DB_Y_1731_ON_PWE_SHORT_STATIC_MDB_FORMAT */ "MEP DB (Y1731 on PWE) static parameters in MDB (complementing the short format)", 13767 /* OAMP_MEP_DB_Y_1731_ON_PWE_STATIC_MDB_FORMAT_PART_1 */ "MEP DB (Y1731 on PWE) static parameters in MDB (complementing the offloaded format), part1", 13768 /* OAMP_MEP_DB_Y_1731_ON_PWE_STATIC_MDB_FORMAT_PART_2 */ "MEP DB (Y1731 on PWE) static parameters in MDB (complementing the offloaded format), part2", 13769 /* OAMP_MEP_PROFILE */ "", 13770 /* OAMP_MEP_SCAN_PROFILE */ "", 13771 /* OAMP_MMUX_MEP_DB_CACHE_OFFLOADED */ "Mmux Mep Database write cache data. Edited by specified blocks:", 13772 /* OAMP_MMUX_MEP_DB_CACHE_SELF_CONTAINED */ "Mmux Mep Database write cache data. Edited by specified blocks:", 13773 /* OAMP_MMUX_MEP_DB_CACHE_SELF_CONTAINED_LM_DB */ "Mmux Mep Database write cache data. Edited by specified blocks:", 13774 /* OAMP_MMUX_MEP_DB_CACHE_SHORT_FORMAT */ "Mmux Mep Database write cache data. Edited by specified blocks:", 13775 /* OAMP_MMUX_RMEP_DB_CACHE */ "Mmux Rmep Database write cache data. Edited by specified blocks:", 13776 /* OAMP_PE_0_FDBK_FIFO */ "INTERNAL", 13777 /* OAMP_PE_0_PROG_TCAM */ "", 13778 /* OAMP_PE_1_FDBK_FIFO */ "INTERNAL", 13779 /* OAMP_PE_1_PROG_TCAM */ "", 13780 /* OAMP_PE_GEN_MEM */ "OAMP Programmable Editor gen mem", 13781 /* OAMP_PE_PROGRAM */ "OAMP Programmable Editor program mem", 13782 /* OAMP_PE_PROG_TCAM */ "", 13783 /* OAMP_PROG_TCAM_PUNT_KEY */ "", 13784 /* OAMP_PROG_TCAM_TX_KEY */ "", 13785 /* OAMP_REMOTE_MEP_EXACT_MATCH_ACDT_AUX */ "INTERNAL", 13786 /* OAMP_REMOTE_MEP_EXACT_MATCH_ACDT_H */ "INTERNAL", 13787 /* OAMP_REMOTE_MEP_EXACT_MATCH_KEYT_AUX */ "INTERNAL", 13788 /* OAMP_REMOTE_MEP_EXACT_MATCH_KEYT_PLDT_H */ "INTERNAL", 13789 /* OAMP_REMOTE_MEP_EXACT_MATCH_MAA_CAM */ "INTERNAL", 13790 /* OAMP_REMOTE_MEP_EXACT_MATCH_MAA_CAM_PAYLOAD */ "INTERNAL", 13791 /* OAMP_REMOTE_MEP_EXACT_MATCH_MANAGEMENT_MEMORY_H */ "INTERNAL", 13792 /* OAMP_REMOTE_MEP_EXACT_MATCH_PLDT_AUX */ "INTERNAL", 13793 /* OAMP_REMOTE_MEP_EXACT_MATCH_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 13794 /* OAMP_RFC_FILTER */ "", 13795 /* OAMP_RMAPEM_MANAGEMENT_REQUEST */ "Management requests", 13796 /* OAMP_RMAPEM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 13797 /* OAMP_RMEP_DATABASE */ "Remote MEP DB", 13798 /* OAMP_RMEP_DB */ "Remote MEP DB", 13799 /* OAMP_RMEP_DB_EXT */ "Remote MEP DB extension", 13800 /* OAMP_RMEP_DB_EXTERNAL */ "Remote MEP DB (External)", 13801 /* OAMP_RMEP_INDEX_ACC */ "Enable lookup of RMEP ID for a combination of opcode(8), MEP-Type(4)\n MEP-Type is the index to the bit within the entry,\n opcode is the address to the table", 13802 /* OAMP_RSP_FIRST_DATA_FIFO */ "INTERNAL", 13803 /* OAMP_RSP_OUT_DATA_FIFO */ "INTERNAL", 13804 /* OAMP_RSP_TCAM */ "", 13805 /* OAMP_RXB_INPUT_DATA_FIFO */ "INTERNAL", 13806 /* OAMP_RXB_OUTPUT_DATA_FIFO */ "INTERNAL", 13807 /* OAMP_RXI_CORE_0_MEM */ "OAMP RXI Core0 fifo", 13808 /* OAMP_RXI_CORE_1_MEM */ "OAMP RXI Core1 fifo", 13809 /* OAMP_RXP_LMM_DA_NIC_TBL_FIFO */ "Rxp Lmm Da Nic Table FIFO", 13810 /* OAMP_RXP_LOCAL_R_MEP_PART_1_FIFO */ "Rxp Local RMEP Part1 FIFO", 13811 /* OAMP_RXP_LOCAL_R_MEP_PART_2_FIFO */ "Rxp Local RMEP Part2 FIFO", 13812 /* OAMP_RXP_LOC_2_SYS_PORT_TBL_FIFO */ "Rxp Loc2Sys Port table FIFO", 13813 /* OAMP_RXP_MDB_R_MEP_PART_2_FIFO */ "Rxp MDB RMEP Part2 FIFO", 13814 /* OAMP_RXP_MEP_PROFILE_TBL_FIFO */ "Rxp MEP Profile table FIFO", 13815 /* OAMP_RXP_R_MEP_INDEX_FIFO */ "Rxp RMEP Index FIFO", 13816 /* OAMP_RXP_UMC_TBL_FIFO */ "Rxp UMC Table FIFO", 13817 /* OAMP_RX_OAM_ID_TCAM */ "", 13818 /* OAMP_SAT_DATA_FIFO_MEM */ "SAT Data FIFO", 13819 /* OAMP_SAT_EVENT_FIFO_MEM */ "INTERNAL", 13820 /* OAMP_SAT_RXI_CORE_0_MEM */ "SAT RXI Core 0 FIFO", 13821 /* OAMP_SAT_RXI_CORE_1_MEM */ "SAT RXI Core 1 FIFO", 13822 /* OAMP_SAT_RX_FLOW_1_SEC_ACCUM_STATS */ "Flow statistics for 1 second", 13823 /* OAMP_SAT_RX_FLOW_1_SEC_ACCUM_STATS_EVEN */ "Flow statistics for 1 second, for Even Flow Id's", 13824 /* OAMP_SAT_RX_FLOW_1_SEC_ACCUM_STATS_ODD */ "Flow statistics for 1 second, for Odd Flow Id's", 13825 /* OAMP_SAT_RX_FLOW_1_SEC_BIN_STATS */ "Flow statistics for 1 second", 13826 /* OAMP_SAT_RX_FLOW_1_SEC_BIN_STATS_EVEN */ "Flow statistics for 1 second, for Even Flow Id's", 13827 /* OAMP_SAT_RX_FLOW_1_SEC_BIN_STATS_ODD */ "Flow statistics for 1 second, for Odd Flow Id's", 13828 /* OAMP_SAT_RX_FLOW_1_SEC_STATS */ "Flow statistics for 1 second", 13829 /* OAMP_SAT_RX_FLOW_1_SEC_STATS_EVEN */ "Flow statistics for 1 secon , for even Flow Id's", 13830 /* OAMP_SAT_RX_FLOW_1_SEC_STATS_ODD */ "Flow statistics for 1 second, for odd Flow Id's", 13831 /* OAMP_SAT_RX_FLOW_ACCUM_STATS_1 */ "Flow accumulated statistics", 13832 /* OAMP_SAT_RX_FLOW_ACCUM_STATS_2 */ "Flow accumulated statistics", 13833 /* OAMP_SAT_RX_FLOW_ACCUM_STATS_3 */ "Flow accumulated statistics", 13834 /* OAMP_SAT_RX_FLOW_ACCUM_STATS_4 */ "Flow accumulated statistics", 13835 /* OAMP_SAT_RX_FLOW_ID */ "", 13836 /* OAMP_SAT_RX_FLOW_PARAMS */ "", 13837 /* OAMP_SAT_RX_FLOW_PARAMS_EVEN */ "SAT RX Flow Params for Even Flow Id's", 13838 /* OAMP_SAT_RX_FLOW_PARAMS_ODD */ "SAT RX Flow Params for Odd Flow Id's", 13839 /* OAMP_SAT_RX_FLOW_STATS */ "", 13840 /* OAMP_SAT_TX */ "", 13841 /* OAMP_SAT_TX_EVC_PARAMS_ENTRY_1 */ "Per evc parameters, two memory entries are needed. Occupy entries 0-15 (even entries)", 13842 /* OAMP_SAT_TX_EVC_PARAMS_ENTRY_2 */ "Per evc parameters, two memory entries are needed. Occupy entries 0-15 (odd entries)", 13843 /* OAMP_SAT_TX_EVC_PRM */ "", 13844 /* OAMP_SAT_TX_EVC_PRM_ENTRY_1 */ "Per evc parameters, two memory entries are needed. Occupy entries 0-15, even addresses", 13845 /* OAMP_SAT_TX_EVC_PRM_ENTRY_2 */ "Per evc parameters, two memory entries are needed. Occupy entries 0-15, odd addresses", 13846 /* OAMP_SAT_TX_GEN_PARAMS */ "Per generator parameters, occupy entries 16-31", 13847 /* OAMP_SAT_TX_GEN_PKT_HEADER */ "SAT Tx Per Flow Packet Header", 13848 /* OAMP_SAT_TX_GEN_PKT_PARAMS_1_EVEN */ "SAT TX Flow Packet Params 1 (even)", 13849 /* OAMP_SAT_TX_GEN_PKT_PARAMS_1_ODD */ "SAT TX Flow Packet Params 1 (odd)", 13850 /* OAMP_SAT_TX_GEN_PRM */ "", 13851 /* OAMP_SAT_TX_GEN_PRM_ENTRY_1 */ "Per generator parameters, entry 1", 13852 /* OAMP_SAT_TX_GEN_PRM_ENTRY_2 */ "Per generator parameters entry 2", 13853 /* OAMP_SD_SF_DB_1 */ "SdSf database, keeping the sliding window and sd sf indications", 13854 /* OAMP_SD_SF_DB_2 */ "SdSf DB, splitted part", 13855 /* OAMP_SD_SF_DB_Y_1711 */ "Remote MEP DB", 13856 /* OAMP_SD_SF_PROFILE */ "Remote MEP DB", 13857 /* OAMP_TXM_DATA_FIFO_MEMORY */ "INTERNAL", 13858 /* OAMP_TXM_LENGTH_FIFO_MEMORY */ "INTERNAL", 13859 /* OAMP_TXO_DATA_FIFO_MEMORY */ "INTERNAL", 13860 /* OAMP_TXO_REQ_FIFO_MEMORY */ "INTERNAL", 13861 /* OAMP_UMC_TABLE */ "UMC table for ICC based MAID", 13862 /* OAM_DGLP_PROFILE */ ".", 13863 /* OAM_FLEXIBLE_DOMAIN_CONTROL */ "index:{INNER PRIORITY TAGGED,PRE VXLT IVID VALID,PRE VXLT OVID VALID,POST VXLT IVID VALID,POST VXLT OVID VALID,SVP VALID}", 13864 /* OAM_FLEX_COUNTER_OFFSET */ "Provides offset to be added to flex counter base ID.", 13865 /* OAM_LM_COUNTERS */ "Packet counter for OAM Loss Measurement", 13866 /* OAM_LM_COUNTERS_0 */ "Packet counter for OAM Loss Measurement pool 0", 13867 /* OAM_LM_COUNTERS_1 */ "Packet counter for OAM Loss Measurement pool 1", 13868 /* OAM_OPCODE_CONTROL_PROFILE */ ".", 13869 /* OAM_OPCODE_GROUP */ ".", 13870 /* OCB_FBM_BANK_MEM */ "Free pointer memory. per bankn two memories n and n+32.", 13871 /* OCB_OCBM_BANK */ "OCB Memory. Address field and access mode are empty because we dont want CPU to access directly to OCB memory.", 13872 /* OCB_OCBM_EVEN */ "OCB Even Memory", 13873 /* OCB_OCBM_ODD */ "OCB Odd Memory", 13874 /* OCB_OCB_ADDRESS_SPACE */ "OCB memory space, addressable by CPU.\n Address should be logical (i.e. represent duff pointer).", 13875 /* OCB_OCB_CPU_ACCESS */ "Cpu access to all Ocb memory. When making a write request, Data2 is unused, The design generate wide Ecc on the data. When making a read request, the data returns with Ecc, to extract the data without ecc use: data238:0,data12047:1792, data11782:1536, data11525:1024,data11013:512 data1501:0", 13876 /* OCB_WRITE_RXI_MEM */ "write rxi.", 13877 /* OLP_APP_DB_MAP */ "maps app_db(6) to ARR Profile and Strength Size .", 13878 /* OLP_AUTO_DOC_NAME_4 */ "INTERNAL", 13879 /* OLP_AUTO_DOC_NAME_5 */ "INTERNAL", 13880 /* OLP_DSPG_EVR_EVENT_FIFO */ "DSPG.EVR Event Fifo Memory", 13881 /* OLP_DSPR_DMT_EVENT_FIFO */ "DSPR.EVR Event Fifo Memory", 13882 /* OLP_DSP_EVENT_ROUTE */ "Determines destination of the event read. The vector is accessed with the following fields of the event: Key-DB-Profile(2), Command(3), Part-of-Lag(1), FID-DB-Profile(2). Each entry contains 3-bits indicating whether to push the event to FIFO0, FIFO1 or the loopback, respectively (i.e. lsb is the loopback indication), Each line at this memory contains 8 entries.\n Only lower 32 lines are actually accessed", 13883 /* OLP_LEARN_ARR_CONFIGURATION_TABLE */ "configuration for the ARR used for the learn trsanslation from Jericho2 to Jericho", 13884 /* OLP_MEM_00000 */ "INTERNAL", 13885 /* OLP_MEM_20000 */ "INTERNAL", 13886 /* OLP_MRQ_ARR_CFG */ "A configuration table for the ARR, where each line represents a specific input format. Each line includes the configurartion data for each field in the incoming data. A general look of each line: f_1.size , f_1.position , f_1.prefix , f_2.size , f_2.position , f_2.prefix , ... , f_n.size , f_n.position , f_n.prefix", 13887 /* OP_UC_QGROUP_DROP_STATE */ "THDU UC queue group drop state.", 13888 /* OP_UC_QGROUP_MINOK */ "THDU UC queue group drop state.", 13889 /* OP_UC_QUEUE_DROP_STATE */ "THDU UC queue drop state.", 13890 /* OP_UC_QUEUE_MINOK */ "THDU UC queue drop state.", 13891 /* OUTCTRLBCASTPKTS */ "Controlled Port Transmit Broadcast Frame Counter", 13892 /* OUTCTRLBYT */ "Controlled Port Transmit Frame Octet Counter", 13893 /* OUTCTRLERRPKTS */ "Controlled Port Transmit Error Frame Counter", 13894 /* OUTCTRLMCASTPKTS */ "Controlled Port Transmit Multicast Frame Counter", 13895 /* OUTCTRLUCASTPKTS */ "Controlled Port Transmit Unicast Frame Counter", 13896 /* OUTUNCTRLBCASTPKTS */ "Uncontrolled Port Transmit Broadcast Frame Counter", 13897 /* OUTUNCTRLBYT */ "Uncontrolled Port Transmit Frame Octet Counter", 13898 /* OUTUNCTRLERRPKTS */ "Uncontrolled Port Transmit Error Frame Counter", 13899 /* OUTUNCTRLMCASTPKTS */ "Uncontrolled Port Transmit Multicast Frame Counter", 13900 /* OUTUNCTRLUCASTPKTS */ "Uncontrolled Port Transmit Unicast Frame Counter", 13901 /* PARSER1_BFD_DIP_V4_LOOPBACK */ "Ingress IPV4 BFD loopback check.", 13902 /* PARSER1_BFD_DIP_V6_LOOPBACK */ "Ingress IPV6 BFD loopback check.", 13903 /* PARSER1_ING_FC_HEADER_TYPE */ "FCoE Header Type.", 13904 /* PARSER1_ING_IPV6_MC_RESERVED_ADDRESS */ "Ingress IPV6 Multicast Reserved Address Table.", 13905 /* PARSER1_IPV4_IN_IPV6_PREFIX_MATCH_TABLE */ "IPv4 in IPv6 Address Prefix Matching Memory.", 13906 /* PARSER2_BFD_DIP_V4_LOOPBACK */ "Ingress IPV4 BFD loopback check.", 13907 /* PARSER2_BFD_DIP_V6_LOOPBACK */ "Ingress IPV6 BFD loopback check.", 13908 /* PARSER2_ING_FC_HEADER_TYPE */ "FCoE Header Type.", 13909 /* PARSER2_ING_IPV6_MC_RESERVED_ADDRESS */ "Ingress IPV6 Multicast Reserved Address Table.", 13910 /* PARSER2_IPV4_IN_IPV6_PREFIX_MATCH_TABLE */ "IPv4 in IPv6 Address Prefix Matching Memory.", 13911 /* PAYLOAD_TOS_FN */ "TOS function table to map the TOS value to any value for filtering with the ContentAware Engine This table is indexed by payload TOS", 13912 /* PBI_DEBUG_TABLE */ "PBI Debug Table", 13913 /* PDM_PDB_FBM */ "Free pointer memory for SQM-PDB", 13914 /* PDM_PDM */ "Packet descriptor memory for SQM-PDM", 13915 /* PEM_ALU_0_OPERATION */ "Alu0Operation", 13916 /* PEM_ALU_0_VAR_CONSTRUCTION_0 */ "Alu0VarConstruction0", 13917 /* PEM_ALU_0_VAR_CONSTRUCTION_1 */ "Alu0VarConstruction1", 13918 /* PEM_ALU_1_OPERATION */ "Alu1Operation", 13919 /* PEM_ALU_1_VAR_CONSTRUCTION_0 */ "Alu1VarConstruction0", 13920 /* PEM_ALU_1_VAR_CONSTRUCTION_1 */ "Alu1VarConstruction1", 13921 /* PEM_ALU_2_OPERATION */ "Alu2Operation", 13922 /* PEM_ALU_2_VAR_CONSTRUCTION_0 */ "Alu2VarConstruction0", 13923 /* PEM_ALU_2_VAR_CONSTRUCTION_1 */ "Alu2VarConstruction1", 13924 /* PEM_ALU_3_OPERATION */ "Alu3Operation", 13925 /* PEM_ALU_3_VAR_CONSTRUCTION_0 */ "Alu3VarConstruction0", 13926 /* PEM_ALU_3_VAR_CONSTRUCTION_1 */ "Alu3VarConstruction1", 13927 /* PEM_ALU_4_OPERATION */ "Alu4Operation", 13928 /* PEM_ALU_4_VAR_CONSTRUCTION_0 */ "Alu4VarConstruction0", 13929 /* PEM_ALU_4_VAR_CONSTRUCTION_1 */ "Alu4VarConstruction1", 13930 /* PEM_ALU_5_OPERATION */ "Alu5Operation", 13931 /* PEM_ALU_5_VAR_CONSTRUCTION_0 */ "Alu5VarConstruction0", 13932 /* PEM_ALU_5_VAR_CONSTRUCTION_1 */ "Alu5VarConstruction1", 13933 /* PEM_ALU_6_OPERATION */ "Alu6Operation", 13934 /* PEM_ALU_6_VAR_CONSTRUCTION_0 */ "Alu6VarConstruction0", 13935 /* PEM_ALU_6_VAR_CONSTRUCTION_1 */ "Alu6VarConstruction1", 13936 /* PEM_ALU_7_OPERATION */ "Alu7Operation", 13937 /* PEM_ALU_7_VAR_CONSTRUCTION_0 */ "Alu7VarConstruction0", 13938 /* PEM_ALU_7_VAR_CONSTRUCTION_1 */ "Alu7VarConstruction1", 13939 /* PEM_ALU_8_OPERATION */ "Alu8Operation", 13940 /* PEM_ALU_8_VAR_CONSTRUCTION_0 */ "Alu8VarConstruction0", 13941 /* PEM_ALU_8_VAR_CONSTRUCTION_1 */ "Alu8VarConstruction1", 13942 /* PEM_ALU_9_OPERATION */ "Alu9Operation", 13943 /* PEM_ALU_9_VAR_CONSTRUCTION_0 */ "Alu9VarConstruction0", 13944 /* PEM_ALU_9_VAR_CONSTRUCTION_1 */ "Alu9VarConstruction1", 13945 /* PEM_CAM_0_PROGRAM */ "Cam0Program", 13946 /* PEM_CAM_0_SRAM_0 */ "tcam associated data", 13947 /* PEM_CAM_0_SRAM_1 */ "tcam associated data", 13948 /* PEM_CAM_0_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13949 /* PEM_CAM_0_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13950 /* PEM_CAM_0_TCAM_MASTER */ "", 13951 /* PEM_CAM_1_PROGRAM */ "Cam1Program", 13952 /* PEM_CAM_1_SRAM_0 */ "tcam associated data", 13953 /* PEM_CAM_1_SRAM_1 */ "tcam associated data", 13954 /* PEM_CAM_1_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13955 /* PEM_CAM_1_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13956 /* PEM_CAM_1_TCAM_MASTER */ "", 13957 /* PEM_CAM_2_PROGRAM */ "Cam2Program", 13958 /* PEM_CAM_2_SRAM_0 */ "tcam associated data", 13959 /* PEM_CAM_2_SRAM_1 */ "tcam associated data", 13960 /* PEM_CAM_2_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13961 /* PEM_CAM_2_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13962 /* PEM_CAM_2_TCAM_MASTER */ "", 13963 /* PEM_CAM_3_PROGRAM */ "Cam3Program", 13964 /* PEM_CAM_3_SRAM_0 */ "tcam associated data", 13965 /* PEM_CAM_3_SRAM_1 */ "tcam associated data", 13966 /* PEM_CAM_3_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13967 /* PEM_CAM_3_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13968 /* PEM_CAM_3_TCAM_MASTER */ "", 13969 /* PEM_CAM_4_PROGRAM */ "Cam4Program", 13970 /* PEM_CAM_4_SRAM_0 */ "tcam associated data", 13971 /* PEM_CAM_4_SRAM_1 */ "tcam associated data", 13972 /* PEM_CAM_4_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13973 /* PEM_CAM_4_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13974 /* PEM_CAM_4_TCAM_MASTER */ "", 13975 /* PEM_CAM_5_PROGRAM */ "Cam5Program", 13976 /* PEM_CAM_5_SRAM_0 */ "tcam associated data", 13977 /* PEM_CAM_5_SRAM_1 */ "tcam associated data", 13978 /* PEM_CAM_5_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13979 /* PEM_CAM_5_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13980 /* PEM_CAM_5_TCAM_MASTER */ "", 13981 /* PEM_CAM_6_PROGRAM */ "Cam6Program", 13982 /* PEM_CAM_6_SRAM_0 */ "tcam associated data", 13983 /* PEM_CAM_6_SRAM_1 */ "tcam associated data", 13984 /* PEM_CAM_6_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13985 /* PEM_CAM_6_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13986 /* PEM_CAM_6_TCAM_MASTER */ "", 13987 /* PEM_CAM_7_PROGRAM */ "Cam7Program", 13988 /* PEM_CAM_7_SRAM_0 */ "tcam associated data", 13989 /* PEM_CAM_7_SRAM_1 */ "tcam associated data", 13990 /* PEM_CAM_7_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13991 /* PEM_CAM_7_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13992 /* PEM_CAM_7_TCAM_MASTER */ "", 13993 /* PEM_CAM_8_PROGRAM */ "Cam8Program", 13994 /* PEM_CAM_8_SRAM_0 */ "tcam associated data", 13995 /* PEM_CAM_8_SRAM_1 */ "tcam associated data", 13996 /* PEM_CAM_8_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 13997 /* PEM_CAM_8_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 13998 /* PEM_CAM_8_TCAM_MASTER */ "", 13999 /* PEM_CAM_9_PROGRAM */ "Cam9Program", 14000 /* PEM_CAM_9_SRAM_0 */ "tcam associated data", 14001 /* PEM_CAM_9_SRAM_1 */ "tcam associated data", 14002 /* PEM_CAM_9_STD_TCAM_0 */ "TCAM. We have 2 instances of this CAM each one for quarter of the PE-CAM key", 14003 /* PEM_CAM_9_STD_TCAM_1 */ "TCAM. We have 4 instances of this CAM each one for quarter of the PE-CAM key", 14004 /* PEM_CAM_9_TCAM_MASTER */ "", 14005 /* PEM_MAP_0_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14006 /* PEM_MAP_0_SRAM_0 */ "Map sram memory", 14007 /* PEM_MAP_0_SRAM_1 */ "Map sram memory", 14008 /* PEM_MAP_0_SRAM_2 */ "Map sram memory", 14009 /* PEM_MAP_0_SRAM_3 */ "Map sram memory", 14010 /* PEM_MAP_0_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14011 /* PEM_MAP_1_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14012 /* PEM_MAP_1_SRAM_0 */ "Map sram memory", 14013 /* PEM_MAP_1_SRAM_1 */ "Map sram memory", 14014 /* PEM_MAP_1_SRAM_2 */ "Map sram memory", 14015 /* PEM_MAP_1_SRAM_3 */ "Map sram memory", 14016 /* PEM_MAP_1_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14017 /* PEM_MAP_2_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14018 /* PEM_MAP_2_SRAM_0 */ "Map sram memory", 14019 /* PEM_MAP_2_SRAM_1 */ "Map sram memory", 14020 /* PEM_MAP_2_SRAM_2 */ "Map sram memory", 14021 /* PEM_MAP_2_SRAM_3 */ "Map sram memory", 14022 /* PEM_MAP_2_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14023 /* PEM_MAP_3_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14024 /* PEM_MAP_3_SRAM_0 */ "Map sram memory", 14025 /* PEM_MAP_3_SRAM_1 */ "Map sram memory", 14026 /* PEM_MAP_3_SRAM_2 */ "Map sram memory", 14027 /* PEM_MAP_3_SRAM_3 */ "Map sram memory", 14028 /* PEM_MAP_3_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14029 /* PEM_MAP_4_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14030 /* PEM_MAP_4_SRAM_0 */ "Map sram memory", 14031 /* PEM_MAP_4_SRAM_1 */ "Map sram memory", 14032 /* PEM_MAP_4_SRAM_2 */ "Map sram memory", 14033 /* PEM_MAP_4_SRAM_3 */ "Map sram memory", 14034 /* PEM_MAP_4_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14035 /* PEM_MAP_5_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14036 /* PEM_MAP_5_SRAM_0 */ "Map sram memory", 14037 /* PEM_MAP_5_SRAM_1 */ "Map sram memory", 14038 /* PEM_MAP_5_SRAM_2 */ "Map sram memory", 14039 /* PEM_MAP_5_SRAM_3 */ "Map sram memory", 14040 /* PEM_MAP_5_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14041 /* PEM_MAP_6_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14042 /* PEM_MAP_6_SRAM_0 */ "Map sram memory", 14043 /* PEM_MAP_6_SRAM_1 */ "Map sram memory", 14044 /* PEM_MAP_6_SRAM_2 */ "Map sram memory", 14045 /* PEM_MAP_6_SRAM_3 */ "Map sram memory", 14046 /* PEM_MAP_6_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14047 /* PEM_MAP_7_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14048 /* PEM_MAP_7_SRAM_0 */ "Map sram memory", 14049 /* PEM_MAP_7_SRAM_1 */ "Map sram memory", 14050 /* PEM_MAP_7_SRAM_2 */ "Map sram memory", 14051 /* PEM_MAP_7_SRAM_3 */ "Map sram memory", 14052 /* PEM_MAP_7_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14053 /* PEM_MAP_8_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14054 /* PEM_MAP_8_SRAM_0 */ "Map sram memory", 14055 /* PEM_MAP_8_SRAM_1 */ "Map sram memory", 14056 /* PEM_MAP_8_SRAM_2 */ "Map sram memory", 14057 /* PEM_MAP_8_SRAM_3 */ "Map sram memory", 14058 /* PEM_MAP_8_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14059 /* PEM_MAP_9_PHYSICAL_ADDR_CONSTRUCTION */ "32 FFC instructions. Each instruction is composed from:\n Dbus-offset(9b), field-width(4b), key-offset(4b)", 14060 /* PEM_MAP_9_SRAM_0 */ "Map sram memory", 14061 /* PEM_MAP_9_SRAM_1 */ "Map sram memory", 14062 /* PEM_MAP_9_SRAM_2 */ "Map sram memory", 14063 /* PEM_MAP_9_SRAM_3 */ "Map sram memory", 14064 /* PEM_MAP_9_VIRTUAL_ADDR_CONSTRUCTION */ "FFC instructions and enable", 14065 /* PEM_MEM_840000 */ "INTERNAL", 14066 /* PEM_MEM_880000 */ "INTERNAL", 14067 /* PEM_MEM_900000 */ "INTERNAL", 14068 /* PEM_MEM_940000 */ "INTERNAL", 14069 /* PEM_MEM_980000 */ "INTERNAL", 14070 /* PEM_MEM_1040000 */ "INTERNAL", 14071 /* PEM_MEM_1080000 */ "INTERNAL", 14072 /* PEM_MEM_1100000 */ "INTERNAL", 14073 /* PEM_MEM_1140000 */ "INTERNAL", 14074 /* PEM_MEM_1840000 */ "INTERNAL", 14075 /* PEM_MEM_1880000 */ "INTERNAL", 14076 /* PEM_MEM_1900000 */ "INTERNAL", 14077 /* PEM_MEM_1940000 */ "INTERNAL", 14078 /* PEM_MEM_1980000 */ "INTERNAL", 14079 /* PEM_MEM_2040000 */ "INTERNAL", 14080 /* PEM_MEM_2080000 */ "INTERNAL", 14081 /* PEM_MEM_10C0000 */ "INTERNAL", 14082 /* PEM_MEM_18C0000 */ "INTERNAL", 14083 /* PEM_MEM_20C0000 */ "INTERNAL", 14084 /* PEM_MEM_8C0000 */ "INTERNAL", 14085 /* PEM_MEM_9C0000 */ "INTERNAL", 14086 /* PEM_PRIO_0_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14087 /* PEM_PRIO_0_OPERATION */ "Priority operation configuration", 14088 /* PEM_PRIO_0_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14089 /* PEM_PRIO_1_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14090 /* PEM_PRIO_1_OPERATION */ "Priority operation configuration", 14091 /* PEM_PRIO_1_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14092 /* PEM_PRIO_2_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14093 /* PEM_PRIO_2_OPERATION */ "Priority operation configuration", 14094 /* PEM_PRIO_2_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14095 /* PEM_PRIO_3_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14096 /* PEM_PRIO_3_OPERATION */ "Priority operation configuration", 14097 /* PEM_PRIO_3_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14098 /* PEM_PRIO_4_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14099 /* PEM_PRIO_4_OPERATION */ "Priority operation configuration", 14100 /* PEM_PRIO_4_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14101 /* PEM_PRIO_5_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14102 /* PEM_PRIO_5_OPERATION */ "Priority operation configuration", 14103 /* PEM_PRIO_5_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14104 /* PEM_PRIO_6_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14105 /* PEM_PRIO_6_OPERATION */ "Priority operation configuration", 14106 /* PEM_PRIO_6_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14107 /* PEM_PRIO_7_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14108 /* PEM_PRIO_7_OPERATION */ "Priority operation configuration", 14109 /* PEM_PRIO_7_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14110 /* PEM_PRIO_8_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14111 /* PEM_PRIO_8_OPERATION */ "Priority operation configuration", 14112 /* PEM_PRIO_8_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14113 /* PEM_PRIO_9_INITIAL_VALUES */ "Priority select configuration includes the dbus enablers and per select module and the initial values", 14114 /* PEM_PRIO_9_OPERATION */ "Priority operation configuration", 14115 /* PEM_PRIO_9_PROGRAM */ "Priority key construction. This memory contains the GFC instructions", 14116 /* PFS_PACKET_TYPE_OFFSET */ "Provide index offset to FP_PORT_FIELD_SEL table based on L3 types of the packet", 14117 /* PHB2_COS_MAP */ "index by PHB2_DOT1P_MAPPING_PTR(4-bit), 802.1 priority(3-bit), CFI/DE", 14118 /* PHB2_STRENGTH_PROFILE */ "PHB2 Strength Profile.", 14119 /* PHB_MAPPING_TBL_1 */ "PHB Mapping table 1.", 14120 /* PHB_MAPPING_TBL_2 */ "PHB Mapping table 2.", 14121 /* PHB_MAPPING_TBL_3 */ "PHB Mapping table 3.", 14122 /* PHB_MAPPING_TBL_4 */ "PHB Mapping table 4.", 14123 /* PHB_MAPPING_TBL_1_STRENGTH_PROFILE */ "PHB Mapping Table 1 Strength Profile.", 14124 /* PHB_MAPPING_TBL_2_STRENGTH_PROFILE */ "PHB Mapping Table 2 Strength Profile.", 14125 /* PHB_MAPPING_TBL_3_STRENGTH_PROFILE */ "PHB Mapping Table 3 Strength Profile.", 14126 /* PHB_MAPPING_TBL_4_STRENGTH_PROFILE */ "PHB Mapping Table 4 Strength Profile.", 14127 /* PHB_SELECT_TCAM */ "L3 Tunnel Table TCAM.", 14128 /* PHB_SELECT_TCAM_DATA_ONLY */ "L3 Tunnel Table TCAM.", 14129 /* PHB_SELECT_TCAM_ONLY */ "L3 Tunnel Table TCAM.", 14130 /* PHYSICAL_PORT_BASE_QUEUE */ "", 14131 /* PKT_ECN_TO_INT_CN_MAPPING */ "Mapping for IP ECN to INT_CN.", 14132 /* PKT_FLOW_CTRL_PROFILE_0 */ "Packet Flow Control Profile 0 Table.", 14133 /* PKT_FLOW_CTRL_STRENGTH_PROFILE_0 */ "Packet Flow Control Strength Profile Table 0.", 14134 /* PKT_FLOW_CTRL_STRENGTH_PROFILE_1 */ "Packet Flow Control Strength Profile 1.", 14135 /* PKT_FLOW_EXTRACTION_CTRL_ID_STRENGTH_PROFILE */ "Packet Flow Inherit Object Strength Profile.", 14136 /* PKT_FLOW_L3_IIF_STRENGTH_PROFILE_1_A */ "Packet Flow L3 IIF Object Strength Profile 1A.", 14137 /* PKT_FLOW_L3_IIF_STRENGTH_PROFILE_1_B */ "Packet Flow L3IIF Object Strength Profile 1B.", 14138 /* PKT_FLOW_OPAQUE_1_STRENGTH_PROFILE_1_A */ "Packet Flow Opaque 2 Object Strength Profile 1A.", 14139 /* PKT_FLOW_OPAQUE_1_STRENGTH_PROFILE_1_B */ "Copy-to-cpu and Drop Control for 1588 packets of different message types.", 14140 /* PKT_FLOW_OPAQUE_2_STRENGTH_PROFILE_1_A */ "Packet Flow Opaque 2 Object Strength Profile 1A.", 14141 /* PKT_FLOW_OPAQUE_2_STRENGTH_PROFILE_1_B */ "Copy-to-cpu and Drop Control for 1588 packets of different message types.", 14142 /* PKT_FLOW_OPAQUE_3_STRENGTH_PROFILE_1_A */ "Packet Flow Opaque 2 Object Strength Profile 1A.", 14143 /* PKT_FLOW_OPAQUE_3_STRENGTH_PROFILE_1_B */ "Copy-to-cpu and Drop Control for 1588 packets of different message types.", 14144 /* PKT_FLOW_OPAQUE_4_STRENGTH_PROFILE_1_A */ "Packet Flow Opaque 2 Object Strength Profile 1A.", 14145 /* PKT_FLOW_OPAQUE_4_STRENGTH_PROFILE_1_B */ "Copy-to-cpu and Drop Control for 1588 packets of different message types.", 14146 /* PKT_FLOW_SELECT_HVE_CONTROL_0 */ "Controls the bit position on the HVE output bus ( SYSTEM_HVE_OUTPUT_BUS format) for BIT_[0-7] fields to be sent for key generation.", 14147 /* PKT_FLOW_SELECT_HVE_CONTROL_1 */ "Controls the bit position on the HVE output bus ( HVE_RESULTS_FORMAT) for BIT_[0-7] fields to be sent for key generation.", 14148 /* PKT_FLOW_SELECT_HVE_CONTROL_2 */ "Controls the bit position on the HVE output bus ( HVE_RESULTS_FORMAT) for BIT_[0-7] fields to be sent for key generation.", 14149 /* PKT_FLOW_SELECT_MY_STATION_PROFILE_1 */ "My Station Protocol Enable Profile 1.", 14150 /* PKT_FLOW_SELECT_MY_STATION_PROFILE_2 */ "My Station Protocol Enable Profile 1.", 14151 /* PKT_FLOW_SELECT_TCAM_0 */ "Parser 1 Packet Flow Selection TCAM.", 14152 /* PKT_FLOW_SELECT_TCAM_1 */ "Parser 1 Packet Flow Selection TCAM.", 14153 /* PKT_FLOW_SELECT_TCAM_2 */ "Parser 2 Packet Flow Selection TCAM.", 14154 /* PKT_FLOW_SELECT_TCAM_0_DATA_ONLY */ "Parser 1 Packet Flow Selection TCAM.", 14155 /* PKT_FLOW_SELECT_TCAM_0_ONLY */ "Parser 1 Packet Flow Selection TCAM.", 14156 /* PKT_FLOW_SELECT_TCAM_1_DATA_ONLY */ "Parser 1 Packet Flow Selection TCAM.", 14157 /* PKT_FLOW_SELECT_TCAM_1_ONLY */ "Parser 1 Packet Flow Selection TCAM.", 14158 /* PKT_FLOW_SELECT_TCAM_2_DATA_ONLY */ "Parser 1 Packet Flow Selection TCAM.", 14159 /* PKT_FLOW_SELECT_TCAM_2_ONLY */ "Parser 1 Packet Flow Selection TCAM.", 14160 /* PKT_FLOW_SVP_STRENGTH_PROFILE_1_A */ "Packet Flow SVP Strength Profile 1A.", 14161 /* PKT_FLOW_VFI_STRENGTH_PROFILE_1_A */ "Packet Flow VFI Object Strength Profile 1A.", 14162 /* PKT_FLOW_VFI_STRENGTH_PROFILE_1_B */ "Packet Flow VFI Object Strength Profile 1B.", 14163 /* PKT_FLOW_VLAN_STRENGTH_PROFILE_1_A */ "Packet Flow VLAN Object Strength Profile 1A.", 14164 /* PKT_FLOW_VLAN_STRENGTH_PROFILE_1_B */ "Packet Flow VLAN Object Strength Profile 1B.", 14165 /* PKT_FLOW_VRF_STRENGTH_PROFILE_1_A */ "Packet Flow VRF Object Strength Profile 1A.", 14166 /* PKT_FLOW_VRF_STRENGTH_PROFILE_1_B */ "Packet Flow VRF Object Strength Profile 1B.", 14167 /* PKT_FLOW_VSAN_STRENGTH_PROFILE_1 */ "VSAN Policy Strength Profile.", 14168 /* PKT_PROC_HDR_VALID_CHECK_PROFILE_2 */ "Packet Process Header Valid Check Profile Table 2.", 14169 /* PKT_PROC_HDR_VALID_CHECK_PROFILE_1_MASK */ "Packet Process Header Valid Check Profile Table 1.", 14170 /* PKT_PROC_HDR_VALID_CHECK_PROFILE_1_VALUE */ "Packet Process Header Valid Check Profile Table 1.", 14171 /* PKT_SCH_CALENDAR0 */ "Packet Shaping block packet scheduler Calendar 0 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 0),", 14172 /* PKT_SCH_CALENDAR1 */ "Packet Shaping block packet scheduler Calendar 1 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 1),", 14173 /* PKT_SCH_CALENDAR0_PIPE0 */ "Packet Shaping block packet scheduler Calendar 0 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 0),", 14174 /* PKT_SCH_CALENDAR0_PIPE1 */ "Packet Shaping block packet scheduler Calendar 0 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 0),", 14175 /* PKT_SCH_CALENDAR0_PIPE2 */ "Packet Shaping block packet scheduler Calendar 0 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 0),", 14176 /* PKT_SCH_CALENDAR0_PIPE3 */ "Packet Shaping block packet scheduler Calendar 0 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 0),", 14177 /* PKT_SCH_CALENDAR1_PIPE0 */ "Packet Shaping block packet scheduler Calendar 1 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 1),", 14178 /* PKT_SCH_CALENDAR1_PIPE1 */ "Packet Shaping block packet scheduler Calendar 1 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 1),", 14179 /* PKT_SCH_CALENDAR1_PIPE2 */ "Packet Shaping block packet scheduler Calendar 1 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 1),", 14180 /* PKT_SCH_CALENDAR1_PIPE3 */ "Packet Shaping block packet scheduler Calendar 1 (Each pipe has two half-pipe packet schedulers, this is for the half-pipe 1),", 14181 /* PMQPORT_WC_UCMEM_DATA */ "PSC to PMD External Memory Interface to program micro-controller memory", 14182 /* PORT_BITMAP_PROFILE */ "Egress port bitmaps for vlan. Indexed by a profile pointer from the VLAN_2 table.", 14183 /* PORT_BRIDGE_BMAP */ "Bitmap of ports with port_bridge enabled.", 14184 /* PORT_BRIDGE_MIRROR_BMAP */ "Bitmap of ports with port_bridge enabled for mirror packets.", 14185 /* PORT_CBL_TABLE */ "Port Class Based Learning Attribute Table for class based station movement. Direct index table, address = {mod[6:0], port[5:0]} or address = virtual_port_num", 14186 /* PORT_CBL_TABLE_MODBASE */ "Specifies the port(s) that is (are) CPU.", 14187 /* PORT_COS_MAP */ "index by COS_MAP_SEL.SELECT(2-bit), ingress port internal priority(4-bit)", 14188 /* PORT_EHG_RX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 14189 /* PORT_EHG_RX_TUNNEL_MASK */ "Embedded Higig Rx tunnel mask memory", 14190 /* PORT_EHG_TX_TUNNEL_DATA */ "Embedded Higig Tx tunnel data memory", 14191 /* PORT_LAG_FAILOVER_SET */ "Port LAG Failover Set Table", 14192 /* PORT_OR_TRUNK_MAC_ACTION */ "Contains actions for Mac Limit Feature. Indexed with the indicies from MAC_LIMIT_TRUNK_MAP_TABLE or MAC_LIMIT_PORT_MAP_TABLE", 14193 /* PORT_OR_TRUNK_MAC_COUNT */ "Port or trunk MAC limit counters", 14194 /* PORT_OR_TRUNK_MAC_LIMIT */ "Port or trunk MAC limit counters", 14195 /* PORT_TAB */ "Port Table", 14196 /* PORT_WC_UCMEM_DATA */ "Warpcore External Memory Interface to program micro-controller memory", 14197 /* PPDB_A_FEC_ENTRY_FORMAT_A */ "FEC entry tables Format A entry values, for the table described in FEC Entry register.\n This is a description of the fields used for unicast routing (IP or MPLS) into a link layer interface. In this scenario:\n Out-LIF = 3'h0, OutLif\n EEI = ARP-Ptr-Prefix, ArpPtr\n Expected-In-RIF = OutLif14:0", 14198 /* PPDB_A_FEC_ENTRY_FORMAT_B */ "FEC entry tables Format B entry values, for the table described in FEC Entry register.\n Format B is used when the link layer interface is a composite object (in a composite object the Out-LIF points to an entry in the EEDB of type Out-RIF; which points in turn to a link layer entry) or when routing into a tunnel. This is a description of the fields used for Format B. In this scenario:\n Out-Lif = OutLif\n EEI = NULL\n Expect ...", 14199 /* PPDB_A_FEC_ENTRY_FORMAT_C */ "FEC entry tables Format C entry values, for the table described in FEC Entry register.\n This is a description of the fields used for bridging into a TRILL tunnel. In this scenario:\n Out-Lif = NULL\n EEI = Eei\n Expected-In-RIF = NULL", 14200 /* PPDB_A_FEC_ENTRY_FORMAT_NULL */ "FEC entry tables NULL entry values, for the table described in FEC Entry register.\n This is a description of the fields of a NULL entry. In this scenario:\n Out-LIF = NULL\n EEI = NULL\n Expected-In-RIF = NULL", 14201 /* PPDB_A_FEC_ENTRY_GENERAL */ "FEC entry tables general entry values, for the table described in FEC Entry register.\n This is a description of the general fields that are commong to all FEC entry formats.", 14202 /* PPDB_A_FEC_SUPER_ENTRY_BANK */ "The FEC entry table is accessed with a FEC pointer. The table has 16K entries, and it is divided to two identical tables, for FEC Entry0 and Entry1. The entry format is dependent on the application. The following registers (from FEC Entry General to FEC Entry Format C) describe the table format per application.", 14203 /* PPDB_A_ISEM_ACDT_AUX */ "INTERNAL", 14204 /* PPDB_A_ISEM_ACDT_H */ "INTERNAL", 14205 /* PPDB_A_ISEM_KEYT_AUX */ "INTERNAL", 14206 /* PPDB_A_ISEM_KEYT_PLDT_H */ "INTERNAL", 14207 /* PPDB_A_ISEM_MAA_CAM */ "INTERNAL", 14208 /* PPDB_A_ISEM_MAA_CAM_PAYLOAD */ "INTERNAL", 14209 /* PPDB_A_ISEM_MANAGEMENT_MEMORY_H */ "INTERNAL", 14210 /* PPDB_A_ISEM_MANAGEMENT_REQUEST */ "Management requests", 14211 /* PPDB_A_ISEM_PLDT_AUX */ "INTERNAL", 14212 /* PPDB_A_ISEM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 14213 /* PPDB_A_OEMA_ACDT_AUX */ "INTERNAL", 14214 /* PPDB_A_OEMA_ACDT_MASTER_H */ "INTERNAL", 14215 /* PPDB_A_OEMA_ACDT_SLAVE_H */ "INTERNAL", 14216 /* PPDB_A_OEMA_KEYT_AUX */ "INTERNAL", 14217 /* PPDB_A_OEMA_KEYT_PLDT_H */ "INTERNAL", 14218 /* PPDB_A_OEMA_MAA_CAM */ "INTERNAL", 14219 /* PPDB_A_OEMA_MAA_CAM_PAYLOAD */ "INTERNAL", 14220 /* PPDB_A_OEMA_MANAGEMENT_MEMORY_H */ "INTERNAL", 14221 /* PPDB_A_OEMA_MANAGEMENT_REQUEST */ "Management requests", 14222 /* PPDB_A_OEMA_PLDT_AUX */ "INTERNAL", 14223 /* PPDB_A_OEMA_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 14224 /* PPDB_A_OEMB_ACDT_AUX */ "INTERNAL", 14225 /* PPDB_A_OEMB_ACDT_MASTER_H */ "INTERNAL", 14226 /* PPDB_A_OEMB_ACDT_SLAVE_H */ "INTERNAL", 14227 /* PPDB_A_OEMB_KEYT_AUX */ "INTERNAL", 14228 /* PPDB_A_OEMB_KEYT_PLDT_H */ "INTERNAL", 14229 /* PPDB_A_OEMB_MAA_CAM */ "INTERNAL", 14230 /* PPDB_A_OEMB_MAA_CAM_PAYLOAD */ "INTERNAL", 14231 /* PPDB_A_OEMB_MANAGEMENT_MEMORY_H */ "INTERNAL", 14232 /* PPDB_A_OEMB_MANAGEMENT_REQUEST */ "Management requests", 14233 /* PPDB_A_OEMB_PLDT_AUX */ "INTERNAL", 14234 /* PPDB_A_OEMB_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 14235 /* PPDB_A_TCAM_ACCESS_PROFILE */ "This table maps TCAM query DB-profile to an access profile. The table has 48 entries, with the index being DB-profile. Each entry defines the access profile, including the memory to access, key size, access type (direct / lookup) and action on the prefix bits.", 14236 /* PPDB_A_TCAM_ACTION */ "This table provides access to the TCAM Action banks. Each TCAM bank is associated with two 20-bit TCAM action memories, provided in this table. Each action table has 1K entries, and there are 24 such tables.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.", 14237 /* PPDB_A_TCAM_ACTION_HIT_INDICATION */ "This table provides a hit indication for each entry in each TCAM Action bank. Each TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 1K entries, divided to 128 register lines of 8-bit, and there are 12x2 such tables.", 14238 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_16 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14239 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_17 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14240 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_18 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14241 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_19 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14242 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_20 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14243 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_21 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14244 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_22 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14245 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_23 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14246 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_24 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14247 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_25 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14248 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_26 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14249 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_27 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14250 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_28 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14251 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_29 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14252 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_30 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14253 /* PPDB_A_TCAM_ACTION_HIT_INDICATION_SMALL_31 */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 14254 /* PPDB_A_TCAM_ACTION_SMALL_16 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14255 /* PPDB_A_TCAM_ACTION_SMALL_17 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14256 /* PPDB_A_TCAM_ACTION_SMALL_18 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14257 /* PPDB_A_TCAM_ACTION_SMALL_19 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14258 /* PPDB_A_TCAM_ACTION_SMALL_20 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14259 /* PPDB_A_TCAM_ACTION_SMALL_21 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14260 /* PPDB_A_TCAM_ACTION_SMALL_22 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14261 /* PPDB_A_TCAM_ACTION_SMALL_23 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14262 /* PPDB_A_TCAM_ACTION_SMALL_24 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14263 /* PPDB_A_TCAM_ACTION_SMALL_25 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14264 /* PPDB_A_TCAM_ACTION_SMALL_26 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14265 /* PPDB_A_TCAM_ACTION_SMALL_27 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14266 /* PPDB_A_TCAM_ACTION_SMALL_28 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14267 /* PPDB_A_TCAM_ACTION_SMALL_29 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14268 /* PPDB_A_TCAM_ACTION_SMALL_30 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14269 /* PPDB_A_TCAM_ACTION_SMALL_31 */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 14270 /* PPDB_A_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n The table has 12*2K + 2*256 entries, with every entry refering to a TCAM bank.\n First 2K entries belongs to TCAM BANK 0 and so on till BANK 11.\n The bottom 2*256 entries belongs to TCAM Bank 12 and 13.\n Note: The bank address is 11 bits. If the lsb is clear (even address) the entry is a key. If the lsb is set (odd address) the entry is a mask\n ...", 14271 /* PPDB_A_TCAM_BANK_COMMAND */ "TCAM command:\n he command can be write/read/compare. In case of write and compare the Din is needed", 14272 /* PPDB_A_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before", 14273 /* PPDB_A_TCAM_ENTRY_PARITY */ "This table holds the parity bits for each 32-bit in the TCAM. The table is built from 12 tables,\n each of them with 2K entries. Each table represents Parity bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14274 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_8 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14275 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_9 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14276 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_10 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14277 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_11 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14278 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_12 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14279 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_13 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14280 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_14 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14281 /* PPDB_A_TCAM_ENTRY_PARITY_SMALL_15 */ "This table holds the parity bits for each 32-bit in the TCAM.\n The table is with 2K entries, each entry contain the parity bits for the matched entry in TCAM-12.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 14282 /* PPDB_A_TCAM_PD_PROFILE */ "TCAM Priority Decoder profile.\n This table maps TCAM query DB-profile to a priority decoder profile. The table has 48 entries, with the index being DB-profile. Each entry defines the priority decoder profile through a bitmap selecting which TCAM banks action results will participate in the priority decoder.", 14283 /* PPDB_B_ISEM_ACDT_AUX */ "INTERNAL", 14284 /* PPDB_B_ISEM_ACDT_H */ "INTERNAL", 14285 /* PPDB_B_ISEM_KEYT_AUX */ "INTERNAL", 14286 /* PPDB_B_ISEM_KEYT_PLDT_H */ "INTERNAL", 14287 /* PPDB_B_ISEM_MAA_CAM */ "INTERNAL", 14288 /* PPDB_B_ISEM_MAA_CAM_PAYLOAD */ "INTERNAL", 14289 /* PPDB_B_ISEM_MANAGEMENT_MEMORY_H */ "INTERNAL", 14290 /* PPDB_B_ISEM_MANAGEMENT_REQUEST */ "Management requests", 14291 /* PPDB_B_ISEM_PLDT_AUX */ "INTERNAL", 14292 /* PPDB_B_ISEM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 14293 /* PPDB_B_LARGE_EM_ACDT_AUX */ "INTERNAL", 14294 /* PPDB_B_LARGE_EM_ACDT_H */ "INTERNAL", 14295 /* PPDB_B_LARGE_EM_ACDT_MASTER_H */ "INTERNAL", 14296 /* PPDB_B_LARGE_EM_AGET_AUX */ "INTERNAL", 14297 /* PPDB_B_LARGE_EM_AGET_H */ "INTERNAL", 14298 /* PPDB_B_LARGE_EM_AGING_CONFIGURATION_TABLE */ "", 14299 /* PPDB_B_LARGE_EM_AMSG_FIFO */ "INTERNAL", 14300 /* PPDB_B_LARGE_EM_FID_COUNTER_DB */ "Design Behaviour for Err: Countinue", 14301 /* PPDB_B_LARGE_EM_FID_COUNTER_PROFILE_DB */ "", 14302 /* PPDB_B_LARGE_EM_FID_PROFILE_DB */ "Design Behaviour for Err: Countinue", 14303 /* PPDB_B_LARGE_EM_FLUSH_DB */ "Flush DB", 14304 /* PPDB_B_LARGE_EM_FMSG_FIFO */ "INTERNAL", 14305 /* PPDB_B_LARGE_EM_FORMAT_1 */ "Large-EM Entry Format I B-MACT data (i.e. PBP)", 14306 /* PPDB_B_LARGE_EM_FORMAT_2 */ "", 14307 /* PPDB_B_LARGE_EM_FORMAT_0_TYPE_0 */ "The LargeEM has several formats. Format1 is used by the forwarding lookups block and its encoding is determined by the application. All encodings have the base format indicated here. Each application is elaborated in the subsequent sections.", 14308 /* PPDB_B_LARGE_EM_FORMAT_3_TYPE_0 */ "", 14309 /* PPDB_B_LARGE_EM_FORMAT_3_TYPE_1 */ "", 14310 /* PPDB_B_LARGE_EM_FORMAT_SLB_COUNTER */ "", 14311 /* PPDB_B_LARGE_EM_KEYT_AUX */ "INTERNAL", 14312 /* PPDB_B_LARGE_EM_KEYT_PLDT_H */ "INTERNAL", 14313 /* PPDB_B_LARGE_EM_LEARN_FORMAT */ "The LargeEM has several formats. Format1 is used by the forwarding lookups block and its encoding is determined by the application. All encodings have the base format indicated here. Each application is elaborated in the subsequent sections.", 14314 /* PPDB_B_LARGE_EM_LOOKUP_BURST_FIFO */ "INTERNAL", 14315 /* PPDB_B_LARGE_EM_MAA_CAM */ "INTERNAL", 14316 /* PPDB_B_LARGE_EM_MAA_CAM_PAYLOAD */ "INTERNAL", 14317 /* PPDB_B_LARGE_EM_MANAGEMENT_EVENT */ "INTERNAL", 14318 /* PPDB_B_LARGE_EM_MANAGEMENT_MEMORY_H */ "INTERNAL", 14319 /* PPDB_B_LARGE_EM_MANAGEMENT_REPLY */ "INTERNAL", 14320 /* PPDB_B_LARGE_EM_MASTER_LOOKUP_BURST_FIFO */ "INTERNAL", 14321 /* PPDB_B_LARGE_EM_MASTER_MANAGEMENT_EVENT */ "INTERNAL", 14322 /* PPDB_B_LARGE_EM_PLDT_AUX */ "INTERNAL", 14323 /* PPDB_B_LARGE_EM_PORT_MINE_TABLE_LAG_PORT */ "If set, Lag Port has at least one member this Device\n Design Behaviour for Err: Countinue (might result in deletion of entry an age-cycle earlier/later)", 14324 /* PPDB_B_LARGE_EM_PORT_MINE_TABLE_PHYSICAL_PORT */ "If set, Physical Port is local to this Device,\n Each address contains 32 entries\n Design Behaviour for Err: Countinue (might result in deletion of entry an age-cycle earlier/later)", 14325 /* PPDB_B_LARGE_EM_REQUEST_FIFO */ "INTERNAL", 14326 /* PPDB_B_LARGE_EM_SLAVE_LOOKUP_BURST_FIFO */ "INTERNAL", 14327 /* PPDB_B_LARGE_EM_SLAVE_MANAGEMENT_EVENT */ "INTERNAL", 14328 /* PPDB_B_LARGE_EM_STEP_TABLE */ "Step Table\n (The Item bit ordering matches must emc_include.v)", 14329 /* PPDB_B_LEARN_FEC_POINTER */ "Large-EM Entry Format I B-MACT data (i.e. PBP)", 14330 /* PPDB_B_LIF_TABLE */ "The Small-EM result table is accessed with the SEM-Index which is a result of the Small-EM lookup. The entry format is dependent on the key into the Small-EM and the application. The table contains 16K entries.", 14331 /* PPDB_B_LIF_TABLE_AC_2_EEI */ "This is the format of a P2P AC that is connected to a PWE or PBB.", 14332 /* PPDB_B_LIF_TABLE_AC_2_OUT_LIF */ "This is the format of a P2P AC that is connected to an AC.", 14333 /* PPDB_B_LIF_TABLE_AC_MP */ "This is the format of a multipoint AC.", 14334 /* PPDB_B_LIF_TABLE_DOUBLE_DATA */ "Double Data Entry", 14335 /* PPDB_B_LIF_TABLE_IP_TT */ "IP tunnels are terminated according to this entry.", 14336 /* PPDB_B_LIF_TABLE_ISID_MP */ "This is the format of a PBP with a multipoint service.", 14337 /* PPDB_B_LIF_TABLE_ISID_P2P */ "This is the format of a PBP with a P2P service.", 14338 /* PPDB_B_LIF_TABLE_LABEL_DOUBLE_DATA */ "Double Data Entry", 14339 /* PPDB_B_LIF_TABLE_LABEL_PROTOCOL_OR_LSP */ "MPLS labels with an IP header above ther are terminated according to this entry.", 14340 /* PPDB_B_LIF_TABLE_LABEL_PWE_MP */ "Multipoint service MPLS labels are terminated according to this entry.", 14341 /* PPDB_B_LIF_TABLE_LABEL_PWE_P2P */ "P2P service MPLS labels are terminated according to this entry.", 14342 /* PPDB_B_LIF_TABLE_TRILL */ "TRILL encapsulated packets are terminated according to this entry.", 14343 /* PPDB_B_MACT_ACDT_SLAVE_H */ "INTERNAL", 14344 /* PPDB_B_SYSTEM_PORT_LAG */ "", 14345 /* PPDB_B_TYPE */ "Large-EM Entry Format I Transparent P2P data (applicable for AC and I-SID)", 14346 /* PP_PORT_GPP_TRANSLATION_1 */ "Port Table, FeatureSpecific-Ethernet.", 14347 /* PP_PORT_GPP_TRANSLATION_2 */ "Port Table, FeatureSpecific-Ethernet.", 14348 /* PP_PORT_GPP_TRANSLATION_3 */ "", 14349 /* PP_PORT_GPP_TRANSLATION_4 */ "Port Table, FeatureSpecific-Ethernet.", 14350 /* PP_PORT_TO_PHYSICAL_PORT_MAP */ "", 14351 /* PQP_DCM */ "This table contains the number of descriptors stored in each queue in PQP. Index to the table is queue number in range 0 to 511.", 14352 /* PQP_DFM */ "Delete Queue FIFO", 14353 /* PQP_DFM_TDM */ "TDM Delete Queue FIFO", 14354 /* PQP_FDM */ "Represents the dynamic status of the EGQ 72K Descriptors. Each entry represents a bitmap of 256 packet descriptors indicating, per descriptor, whether it is free or occupied.", 14355 /* PQP_LCD */ "Last copy discard FIFO", 14356 /* PQP_LCD_TDM */ "Last copy discard FIFO", 14357 /* PQP_OTM_ATTRIBUTES_TABLE_DEQ */ "Represents the OTM attributes used in dequeue pipeline.", 14358 /* PQP_OTM_ATTRIBUTES_TABLE_ENQ */ "Represents the OTM attributes used in enqueue pipeline.", 14359 /* PQP_PDM_1 */ "packet descriptors memory for range 0 - 32K-1", 14360 /* PQP_PDM_2 */ "packet descriptors memory for range 32K - 68K-1", 14361 /* PQP_RDM */ "read desc memory", 14362 /* PQP_TC_DP_MAP */ "Lookup table used to map Port-COS-Map-Profile(4), Egress-MC(1), SYS-TC(3),SYS-DP(2) to the following parameters: Egress-TC(3) and CGM-MC-DP(2).\n The Egress-TC + Base-Queue-Num determines the final queue number the packet will be enqueued to it.", 14363 /* PQP_WDM */ "write desc memory", 14364 /* PROT_NHI_TABLE_1 */ "Protection Switching (backup path) Next Hop Table.", 14365 /* PTP_LABEL_RANGE_PROFILE_TABLE */ "", 14366 /* PTR_RESULTS_BUFFER_IADAPT */ "Visibility packet result capture in IADAPT.", 14367 /* PTR_RESULTS_BUFFER_IADAPT_PIPE0 */ "Visibility packet result capture in IADAPT.", 14368 /* PTR_RESULTS_BUFFER_IADAPT_PIPE1 */ "Visibility packet result capture in IADAPT.", 14369 /* PTR_RESULTS_BUFFER_IADAPT_PIPE2 */ "Visibility packet result capture in IADAPT.", 14370 /* PTR_RESULTS_BUFFER_IADAPT_PIPE3 */ "Visibility packet result capture in IADAPT.", 14371 /* PTR_RESULTS_BUFFER_IADAPT_PIPE4 */ "Visibility packet result capture in IADAPT.", 14372 /* PTR_RESULTS_BUFFER_IADAPT_PIPE5 */ "Visibility packet result capture in IADAPT.", 14373 /* PTR_RESULTS_BUFFER_IADAPT_PIPE6 */ "Visibility packet result capture in IADAPT.", 14374 /* PTR_RESULTS_BUFFER_IADAPT_PIPE7 */ "Visibility packet result capture in IADAPT.", 14375 /* PTR_RESULTS_BUFFER_IFWD */ "Visibility packet result capture in IFWD.", 14376 /* PTR_RESULTS_BUFFER_IFWD_PIPE0 */ "Visibility packet result capture in IFWD.", 14377 /* PTR_RESULTS_BUFFER_IFWD_PIPE1 */ "Visibility packet result capture in IFWD.", 14378 /* PTR_RESULTS_BUFFER_IFWD_PIPE2 */ "Visibility packet result capture in IFWD.", 14379 /* PTR_RESULTS_BUFFER_IFWD_PIPE3 */ "Visibility packet result capture in IFWD.", 14380 /* PTR_RESULTS_BUFFER_IFWD_PIPE4 */ "Visibility packet result capture in IFWD.", 14381 /* PTR_RESULTS_BUFFER_IFWD_PIPE5 */ "Visibility packet result capture in IFWD.", 14382 /* PTR_RESULTS_BUFFER_IFWD_PIPE6 */ "Visibility packet result capture in IFWD.", 14383 /* PTR_RESULTS_BUFFER_IFWD_PIPE7 */ "Visibility packet result capture in IFWD.", 14384 /* PTR_RESULTS_BUFFER_IPARS */ "Visibility packet result capture in IPARS.", 14385 /* PTR_RESULTS_BUFFER_IPARS_PIPE0 */ "Visibility packet result capture in IPARS.", 14386 /* PTR_RESULTS_BUFFER_IPARS_PIPE1 */ "Visibility packet result capture in IPARS.", 14387 /* PTR_RESULTS_BUFFER_IPARS_PIPE2 */ "Visibility packet result capture in IPARS.", 14388 /* PTR_RESULTS_BUFFER_IPARS_PIPE3 */ "Visibility packet result capture in IPARS.", 14389 /* PTR_RESULTS_BUFFER_IPARS_PIPE4 */ "Visibility packet result capture in IPARS.", 14390 /* PTR_RESULTS_BUFFER_IPARS_PIPE5 */ "Visibility packet result capture in IPARS.", 14391 /* PTR_RESULTS_BUFFER_IPARS_PIPE6 */ "Visibility packet result capture in IPARS.", 14392 /* PTR_RESULTS_BUFFER_IPARS_PIPE7 */ "Visibility packet result capture in IPARS.", 14393 /* PTR_RESULTS_BUFFER_ISW */ "Visibility packet result capture in ISW.", 14394 /* PTR_RESULTS_BUFFER_ISW1 */ "Visibility packet result capture in ISW1.", 14395 /* PTR_RESULTS_BUFFER_ISW2 */ "Visibility packet result capture in ISW2.", 14396 /* PTR_RESULTS_BUFFER_ISW1_PIPE0 */ "Visibility packet result capture in ISW1.", 14397 /* PTR_RESULTS_BUFFER_ISW1_PIPE1 */ "Visibility packet result capture in ISW1.", 14398 /* PTR_RESULTS_BUFFER_ISW1_PIPE2 */ "Visibility packet result capture in ISW1.", 14399 /* PTR_RESULTS_BUFFER_ISW1_PIPE3 */ "Visibility packet result capture in ISW1.", 14400 /* PTR_RESULTS_BUFFER_ISW2_PIPE0 */ "Visibility packet result capture in ISW2.", 14401 /* PTR_RESULTS_BUFFER_ISW2_PIPE1 */ "Visibility packet result capture in ISW2.", 14402 /* PTR_RESULTS_BUFFER_ISW2_PIPE2 */ "Visibility packet result capture in ISW2.", 14403 /* PTR_RESULTS_BUFFER_ISW2_PIPE3 */ "Visibility packet result capture in ISW2.", 14404 /* PTR_RESULTS_BUFFER_ISW_PIPE0 */ "Visibility packet result capture in ISW.", 14405 /* PTR_RESULTS_BUFFER_ISW_PIPE1 */ "Visibility packet result capture in ISW.", 14406 /* PTR_RESULTS_BUFFER_ISW_PIPE2 */ "Visibility packet result capture in ISW.", 14407 /* PTR_RESULTS_BUFFER_ISW_PIPE3 */ "Visibility packet result capture in ISW.", 14408 /* PTR_RESULTS_BUFFER_ISW_PIPE4 */ "Visibility packet result capture in ISW.", 14409 /* PTR_RESULTS_BUFFER_ISW_PIPE5 */ "Visibility packet result capture in ISW.", 14410 /* PTR_RESULTS_BUFFER_ISW_PIPE6 */ "Visibility packet result capture in ISW.", 14411 /* PTR_RESULTS_BUFFER_ISW_PIPE7 */ "Visibility packet result capture in ISW.", 14412 /* PTR_RESULTS_BUFFER_IVP */ "Visibility packet result capture in IVP.", 14413 /* PTR_RESULTS_BUFFER_IVP_PIPE0 */ "Visibility packet result capture in IVP.", 14414 /* PTR_RESULTS_BUFFER_IVP_PIPE1 */ "Visibility packet result capture in IVP.", 14415 /* PTR_RESULTS_BUFFER_IVP_PIPE2 */ "Visibility packet result capture in IVP.", 14416 /* PTR_RESULTS_BUFFER_IVP_PIPE3 */ "Visibility packet result capture in IVP.", 14417 /* PTS_DRAM_DBLF */ "DRAM Dequeue Buffer List FIFO", 14418 /* PTS_DRAM_DQCF */ "DRAM Dequeue Command FIFO", 14419 /* PTS_PDQ_BLOCK_MATRIX */ "Configuration per queue of PDQ.", 14420 /* PTS_PER_PDQ_CFG */ "Configuration per queue of PDQ (DQCF and DBLF).", 14421 /* PTS_PER_SHAPER_CFG */ "Configuration per PTS shaper,\n addr=0 : LOCAL-HP\n addr=1 : LOCAL-LP\n addr=2 : LOCAL", 14422 /* PTS_PER_WFQ_CFG */ "Configuration per PTS WFQ\n addr=0 : SRAM:DRAM - LOCAL-HP\n addr=1 : SRAM:DRAM - LOCAL-LP\n addr=2 : SRAM:DRAM - FUC-HP\n\n All the WFQs arbitrates between 2 contexts, each one has its weight.", 14423 /* PTS_PER_WFQ_MESH_CFG */ "Configuration per PTS Mesh-WFQ\n addr=0 : LOCAL:DEV1:DEV2 - HP\n addr=1 : LOCAL:DEV1:DEV2 - LP\n The WFQs arbitrates between 3 contexts, each one has its weight.", 14424 /* PTS_SHAPER_FMC_CFG */ "Configurations for PTS fabric-MC shaper\n Index0 : FMC-HP\n Index1 : FMC-LP\n Index2 : FMC (total)", 14425 /* PTS_SRAM_DQCF */ "SRAM Dequeue Command FIFO", 14426 /* QL_TABLE0 */ "Average Queue Length Table 0", 14427 /* QL_TABLE1 */ "Average Queue Length Table 1", 14428 /* QRH_CUCT */ "2Kx192 CRH unicast routing and distribution table. Provides direct access to table.", 14429 /* QRH_DLLU */ "192x10x4 DRH last link used table. Information is kept per link bundle.", 14430 /* QRH_DUCT */ "2Kx192 DRH unicast routing and distribution table. Provides direct access to table.", 14431 /* QRH_FFLB */ "Fault FAPS load balancing. Maps each FAP to load balancing context. There are total 4 contexts. By default all FAPs maps to context 0. Address is bits 10:4 of FAP ID. Data for each FAP contaion 2 bits. 4 LSBs of FAP ID is offset in units of 2 bits. For example in address 15, bits 1:0 are FAP 240, bits 3:2 are FAP 241, up to bits 31:30 which are FAP 255.", 14432 /* QRH_MCLBT */ "192x192 DRH multicast load balancing table. Provides direct access to table . All tables should be written with the same values for proper operation.", 14433 /* QRH_MCSFF */ "MultiCase Source Fap Filter - filtering out replication which were originated in the same FAP Address: List of FAPS - FAP-ID List Of Links - group-ID (similar to MCLBT index). Data itself is as following: Bit 11: enable (if set enables this feature for this link-group ID) Bit 10:0: FAP-ID connected to this link group Note this works only in FE2 single stage and FE3", 14434 /* QRH_MNOL */ "Minimum number of link", 14435 /* QRH_RESERVED_21 */ "INTERNAL", 14436 /* QRH_RESERVED_22 */ "INTERNAL", 14437 /* QRH_RESERVED_23 */ "INTERNAL", 14438 /* Q_SCHED_L0_ACCUM_COMP_MEM */ "Internal working memory for hardware to track the per node cell length error. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14439 /* Q_SCHED_L0_ACCUM_COMP_MEM_PIPE0 */ "Internal working memory for hardware to track the per node cell length error. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14440 /* Q_SCHED_L0_ACCUM_COMP_MEM_PIPE1 */ "Internal working memory for hardware to track the per node cell length error. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14441 /* Q_SCHED_L0_ACCUM_COMP_MEM_PIPE2 */ "Internal working memory for hardware to track the per node cell length error. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14442 /* Q_SCHED_L0_ACCUM_COMP_MEM_PIPE3 */ "Internal working memory for hardware to track the per node cell length error. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14443 /* Q_SCHED_L0_CREDIT_MEM */ "Internal working memory for hardware to trackthe per node running credit. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14444 /* Q_SCHED_L0_CREDIT_MEM_PIPE0 */ "Internal working memory for hardware to trackthe per node running credit. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14445 /* Q_SCHED_L0_CREDIT_MEM_PIPE1 */ "Internal working memory for hardware to trackthe per node running credit. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14446 /* Q_SCHED_L0_CREDIT_MEM_PIPE2 */ "Internal working memory for hardware to trackthe per node running credit. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14447 /* Q_SCHED_L0_CREDIT_MEM_PIPE3 */ "Internal working memory for hardware to trackthe per node running credit. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14448 /* Q_SCHED_L0_WEIGHT_MEM */ "Memory to keep the per L0 node weight information. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14449 /* Q_SCHED_L0_WEIGHT_MEM_PIPE0 */ "Memory to keep the per L0 node weight information. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14450 /* Q_SCHED_L0_WEIGHT_MEM_PIPE1 */ "Memory to keep the per L0 node weight information. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14451 /* Q_SCHED_L0_WEIGHT_MEM_PIPE2 */ "Memory to keep the per L0 node weight information. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14452 /* Q_SCHED_L0_WEIGHT_MEM_PIPE3 */ "Memory to keep the per L0 node weight information. The index to this memory is the L0 number of this pipe, ranging from 0 to 339. Extra entries outside of the range are not used", 14453 /* Q_SCHED_L1_ACCUM_COMP_MEM */ "Internal working memory for hardware to track the per queue cell length error. The index to this memory is the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14454 /* Q_SCHED_L1_ACCUM_COMP_MEM_PIPE0 */ "Internal working memory for hardware to track the per queue cell length error. The index to this memory is the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14455 /* Q_SCHED_L1_ACCUM_COMP_MEM_PIPE1 */ "Internal working memory for hardware to track the per queue cell length error. The index to this memory is the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14456 /* Q_SCHED_L1_ACCUM_COMP_MEM_PIPE2 */ "Internal working memory for hardware to track the per queue cell length error. The index to this memory is the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14457 /* Q_SCHED_L1_ACCUM_COMP_MEM_PIPE3 */ "Internal working memory for hardware to track the per queue cell length error. The index to this memory is the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14458 /* Q_SCHED_L1_CREDIT_MEM */ "Internal working memory for hardware to track the per queue running credit. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14459 /* Q_SCHED_L1_CREDIT_MEM_PIPE0 */ "Internal working memory for hardware to track the per queue running credit. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14460 /* Q_SCHED_L1_CREDIT_MEM_PIPE1 */ "Internal working memory for hardware to track the per queue running credit. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14461 /* Q_SCHED_L1_CREDIT_MEM_PIPE2 */ "Internal working memory for hardware to track the per queue running credit. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14462 /* Q_SCHED_L1_CREDIT_MEM_PIPE3 */ "Internal working memory for hardware to track the per queue running credit. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14463 /* Q_SCHED_L1_WEIGHT_MEM */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14464 /* Q_SCHED_L1_WEIGHT_MEM_PIPE0 */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14465 /* Q_SCHED_L1_WEIGHT_MEM_PIPE1 */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14466 /* Q_SCHED_L1_WEIGHT_MEM_PIPE2 */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14467 /* Q_SCHED_L1_WEIGHT_MEM_PIPE3 */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 707. Of this range, 0 to 329 are for UC queues and 330 to 707 are for MC queues. The extra entries outside of the range are not used", 14468 /* Q_SCHED_L2_ACCUM_COMP_MEM */ "Internal working memory for hardware to track the per queue cell length error. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14469 /* Q_SCHED_L2_ACCUM_COMP_MEM_PIPE0 */ "Internal working memory for hardware to track the per queue cell length error. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14470 /* Q_SCHED_L2_ACCUM_COMP_MEM_PIPE1 */ "Internal working memory for hardware to track the per queue cell length error. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14471 /* Q_SCHED_L2_ACCUM_COMP_MEM_PIPE2 */ "Internal working memory for hardware to track the per queue cell length error. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14472 /* Q_SCHED_L2_ACCUM_COMP_MEM_PIPE3 */ "Internal working memory for hardware to track the per queue cell length error. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14473 /* Q_SCHED_L2_CREDIT_MEM */ "Internal working memory for hardware to track the running credit. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14474 /* Q_SCHED_L2_CREDIT_MEM_PIPE0 */ "Internal working memory for hardware to track the running credit. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14475 /* Q_SCHED_L2_CREDIT_MEM_PIPE1 */ "Internal working memory for hardware to track the running credit. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14476 /* Q_SCHED_L2_CREDIT_MEM_PIPE2 */ "Internal working memory for hardware to track the running credit. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14477 /* Q_SCHED_L2_CREDIT_MEM_PIPE3 */ "Internal working memory for hardware to track the running credit. The memory is organized into two sections: the first section ranging from 0 to 707 is used to track errors for queues in ToQ_A, the second section ranging from 708 to 1415 is used to track errors for queues in ToQ_B. Extra entries outside of these two sections are not used", 14478 /* Q_SCHED_L2_WEIGHT_MEM */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 1299. The extra entries outside of the range are not used", 14479 /* Q_SCHED_L2_WEIGHT_MEM_PIPE0 */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 1299. The extra entries outside of the range are not used", 14480 /* Q_SCHED_L3_ACCUM_COMP_MEM */ "Internal working memory for hardware to track the per queue cell length error. The index to this memory is the logical queue number, ranging from 0 to 2617. Of this range, 0 to 1279 are for UC queues and 1280 to 2617 are for MC queues. The extra entries outside of the range are not used", 14481 /* Q_SCHED_L3_ACCUM_COMP_MEM_PIPE0 */ "Internal working memory for hardware to track the per queue cell length error. The index to this memory is the logical queue number, ranging from 0 to 2617. Of this range, 0 to 1279 are for UC queues and 1280 to 2617 are for MC queues. The extra entries outside of the range are not used", 14482 /* Q_SCHED_L3_CREDIT_MEM */ "Internal working memory for hardware to track the per queue running credit. The index to this memory comes from the logical queue number, ranging from 0 to 2617. Of this range, 0 to 1279 are for UC queues and 1280 to 2617 are for MC queues. The extra entries outside of the range are not used", 14483 /* Q_SCHED_L3_CREDIT_MEM_PIPE0 */ "Internal working memory for hardware to track the per queue running credit. The index to this memory comes from the logical queue number, ranging from 0 to 2617. Of this range, 0 to 1279 are for UC queues and 1280 to 2617 are for MC queues. The extra entries outside of the range are not used", 14484 /* Q_SCHED_L3_WEIGHT_MEM */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 2617. Of this range, 0 to 1279 are for UC queues and 1280 to 2617 are for MC queues. The extra entries outside of the range are not used", 14485 /* Q_SCHED_L3_WEIGHT_MEM_PIPE0 */ "Memory to keep the per queue weight infomation. The index to this memory comes from the logical queue number, ranging from 0 to 2617. Of this range, 0 to 1279 are for UC queues and 1280 to 2617 are for MC queues. The extra entries outside of the range are not used", 14486 /* RANDOM_RRLB_HG_TRUNK_MEMBER */ "Contains the list of all HG Trunk members.", 14487 /* RAW_ENTRY_TABLE */ "Raw physical access to the Search Bank Memories.", 14488 /* RAW_HITBIT_TABLE */ "Raw physical access to the Hitbit Search Bank Memories.", 14489 /* RDB_BANK_0_0 */ "RDB Data Buffer 0 Part 0.", 14490 /* RDB_BANK_0_1 */ "RDB Data Buffer 0 Part 1.", 14491 /* RDB_BANK_1_0 */ "RDB Data Buffer 1 Part 0.", 14492 /* RDB_BANK_1_1 */ "RDB Data Buffer 1 Part 1.", 14493 /* RDB_BANK_2_0 */ "RDB Data Buffer 2 Part 0.", 14494 /* RDB_BANK_2_1 */ "RDB Data Buffer 2 Part 1.", 14495 /* RDB_BANK_3_0 */ "RDB Data Buffer 3 Part 0.", 14496 /* RDB_BANK_3_1 */ "RDB Data Buffer 3 Part 1.", 14497 /* RDB_CEL */ "RDB Cell Link.", 14498 /* RDB_CONTEXT */ "RDB context debug.", 14499 /* RDB_CXT_AB */ "RDB Descriptors AB.", 14500 /* RDB_CXT_CD */ "RDB Descriptors CD.", 14501 /* RDB_FCP_0 */ "RDB Free Pointer FIFO for Bank 0.", 14502 /* RDB_FCP_1 */ "RDB Free Pointer FIFO for Bank 1.", 14503 /* RDB_FCP_2 */ "RDB Free Pointer FIFO for Bank 2.", 14504 /* RDB_FCP_3 */ "RDB Free Pointer FIFO for Bank 3.", 14505 /* RDB_PKT */ "RDB Packet Link.", 14506 /* RDB_QUEUE */ "RDB queue debug.", 14507 /* REPLICATION_FIFO_BANK0 */ "Bank0 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14508 /* REPLICATION_FIFO_BANK1 */ "Bank1 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14509 /* REPLICATION_FIFO_BANK2 */ "Bank1 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14510 /* REPLICATION_FIFO_BANK0_XPE0 */ "Bank0 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14511 /* REPLICATION_FIFO_BANK0_XPE1 */ "Bank0 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14512 /* REPLICATION_FIFO_BANK0_XPE2 */ "Bank0 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14513 /* REPLICATION_FIFO_BANK0_XPE3 */ "Bank0 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14514 /* REPLICATION_FIFO_BANK1_XPE0 */ "Bank1 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14515 /* REPLICATION_FIFO_BANK1_XPE1 */ "Bank1 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14516 /* REPLICATION_FIFO_BANK1_XPE2 */ "Bank1 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14517 /* REPLICATION_FIFO_BANK1_XPE3 */ "Bank1 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14518 /* REPLICATION_FIFO_BANK2_XPE0 */ "Bank1 of Replication FIFO. This memory should not be accessed by CPU during traffic", 14519 /* RESPONSIVE_PROTOCOL_MATCH */ "Responsive protocol match register set.", 14520 /* RH_ECMP_DROPS */ "RH_ECMP drop counter.", 14521 /* RH_ECMP_DROPS_X */ "RH_ECMP drop counter.", 14522 /* RH_ECMP_DROPS_Y */ "RH_ECMP drop counter.", 14523 /* RH_ECMP_ETHERTYPE_ELIGIBILITY_MAP */ "A list of ethertype within which RH ECMP can be applied (or excluded).", 14524 /* RH_ECMP_FLOWSET */ "RH_ECMP Flow Set Assigned Member.", 14525 /* RH_ECMP_FLOWSET_PIPE0 */ "DLB_ECMP Flow Set Assigned Port Member.", 14526 /* RH_ECMP_FLOWSET_PIPE1 */ "DLB_ECMP Flow Set Assigned Port Member.", 14527 /* RH_HGT_DROPS */ "RH_HGT Group Member Statistic.", 14528 /* RH_HGT_DROPS_X */ "RH_HGT Group Member Statistic.", 14529 /* RH_HGT_DROPS_Y */ "RH_HGT Group Member Statistic.", 14530 /* RH_HGT_ETHERTYPE_ELIGIBILITY_MAP */ "A list of ethertype within which RH HGT can be applied (or excluded).", 14531 /* RH_HGT_FLOWSET */ "RH_HGT Flow Set Assigned Member.", 14532 /* RH_HGT_FLOWSET_PIPE0 */ "DLB Flow Set Assigned Port Member.", 14533 /* RH_HGT_FLOWSET_PIPE1 */ "DLB Flow Set Assigned Port Member.", 14534 /* RH_HGT_GROUP_CONTROL */ "RH_HGT Group Parameters.", 14535 /* RH_LAG_DROPS */ "RH_LAG drop counter.", 14536 /* RH_LAG_DROPS_X */ "RH_LAG drop counter.", 14537 /* RH_LAG_DROPS_Y */ "RH_LAG drop counter.", 14538 /* RH_LAG_ETHERTYPE_ELIGIBILITY_MAP */ "A list of ethertype within which RH LAG can be applied (or excluded).", 14539 /* RH_LAG_FLOWSET */ "RH_LAG Flow Set Assigned Member.", 14540 /* RH_LAG_FLOWSET_PIPE0 */ "DLB Flow Set Assigned Port Member.", 14541 /* RH_LAG_FLOWSET_PIPE1 */ "DLB Flow Set Assigned Port Member.", 14542 /* RMEP */ "", 14543 /* RQE_FREE_LIST */ "RQE FREE LIST", 14544 /* RQE_FREE_LIST_XPE0 */ "RQE FREE LIST", 14545 /* RQE_FREE_LIST_XPE1 */ "RQE FREE LIST", 14546 /* RQE_FREE_LIST_XPE2 */ "RQE FREE LIST", 14547 /* RQE_FREE_LIST_XPE3 */ "RQE FREE LIST", 14548 /* RQE_LINK_LIST */ "RQE LINK LIST", 14549 /* RQE_LINK_LIST_XPE0 */ "RQE LINK LIST", 14550 /* RQE_LINK_LIST_XPE1 */ "RQE LINK LIST", 14551 /* RQE_LINK_LIST_XPE2 */ "RQE LINK LIST", 14552 /* RQE_LINK_LIST_XPE3 */ "RQE LINK LIST", 14553 /* RQP_CMS */ "RQP context mapping to Source ID and Fabric Pipe", 14554 /* RQP_CRM */ "CRC16 Reminder Memory", 14555 /* RQP_FCM */ "RCM Free Context Memory", 14556 /* RQP_FRM */ "FDA RXI Memory", 14557 /* RQP_HDR_FIFO */ "Packet header FIFO for DBF write latency in PRP", 14558 /* RQP_MBYPASS */ "Multicast Bypass memory", 14559 /* RQP_MC_SP_TC_MAP */ "RQP should drop MC packets based on data buffers consumption. The decision whether to drop a packet or forward it is resolved by the CGM block that passes the indication to the RQP. The RQP map SYS-TC2:0SYS-DP1:0 to CGM-SP(1),CGM-SE(2),CGM-TC(3) and forward them to the CGM.", 14560 /* RQP_MSC */ "Multicast shared contexts", 14561 /* RQP_PCM */ "Packed Cell Memory", 14562 /* RQP_PRD */ "Pre Reassemblly database", 14563 /* RQP_PRF */ "Pre Reassemblly FIFO", 14564 /* RQP_PRT */ "Pre Reassemblly Table", 14565 /* RQP_RCM */ "Reassembly contexts memory allocation used for fabric primary pipe traffic. Index to this memory is FAB_PIPE_ID1:0 & FAP ID10:0\n The reassembly contexts allocation mode in the Fabric primary interface, may be one from the following options, according to RcmPrimaryMode register:\n 0 - Static allocation mode, in this mode reassembly context is feagured from the FAP_ID9:0 and context mask + base address.\n 1 - Semi-dynamic allocation mode, RQP context is detrmined by mapping of FAB_PIPE_ID1:0 & FAP I ...", 14566 /* RQP_RPDM */ "RQP Packet reassembly descriptors (PRP)", 14567 /* RQP_RPDMHDR */ "Packet reassembly descriptors for packet header(PRP)", 14568 /* RQP_RSM */ "Cell Unpack Reassembly Memory (state)", 14569 /* RQP_SEGM */ "Segment Memory for EGQ0.", 14570 /* RQP_SEGM_BANK */ "Segment Memory banks 0 until 8 for EGQ0.", 14571 /* RQP_SEGM_BANK_9 */ "Segment Memory bank 9 for EGQ0.", 14572 /* RQP_TSM */ "TDM (in PRP) Segment Memory", 14573 /* RQP_USM */ "Unpacked Segment Memory", 14574 /* RTAG7_FLOW_BASED_HASH */ "RTAG7 Flow-based Hash table.", 14575 /* RTAG7_PORT_BASED_HASH */ ". FeatureSpecific-Ethernet.", 14576 /* RTP_CRMA */ "Each address corresponds to two consecutive Destination-ID and contains a bitmap. Each bit corresponds to a physical link.\n 1 : Destination is accessible through the link.\n 0 : Destination is not accessible through the link.\n Control cells exit the FAP only on valid links.\n Note: this table is updated automatically by a hardware process and normally should not be modified by the user.\n Note: This memory i ...", 14577 /* RTP_CUCT */ "", 14578 /* RTP_DLLUP */ "", 14579 /* RTP_DLLUS */ "", 14580 /* RTP_DRMA */ "Each address corresponds to two consecutive Destination-ID and contains a bitmap. Each bit corresponds to a physical link.\n 1 : Destination is accessible through the link.\n 0 : Destination is not accessible through the link.\n Data cells destined for a destination exit the FAP only on valid links.\n Note, this table is updated automatically by a hardware process and normally should not be modified by the user.\n ...", 14581 /* RTP_DUCTP */ "", 14582 /* RTP_DUCTS */ "", 14583 /* RTP_FFLBP */ "", 14584 /* RTP_FFLBS */ "", 14585 /* RTP_FLGM */ "2048x8 FAP Link Group Mapping. This table mapped for each FAP the link group number that the FAP belongs to. This table should be inialized by SW according to system connectivity (as read from RMHMT). For easy use: the first active link for each FAP will be the group number.", 14586 /* RTP_GCILBT */ "192x192 load balancing table for reachability GCI masking. Used when detected a group with low number of links (below MNOLG) to know which links should mask from GCI generation. Should be initialized to the same values as DRH MCLBT tables.", 14587 /* RTP_MCLBTP */ "", 14588 /* RTP_MCLBTS */ "", 14589 /* RTP_MCSFFP */ "", 14590 /* RTP_MCT */ "", 14591 /* RTP_MEM_800000 */ "", 14592 /* RTP_MEM_900000 */ "", 14593 /* RTP_MEM_1100000 */ "", 14594 /* RTP_MEM_A00000 */ "", 14595 /* RTP_MEM_C00000 */ "", 14596 /* RTP_MEM_D00000 */ "", 14597 /* RTP_MNOLG */ "Minimum number of link for GCI masking", 14598 /* RTP_MNOLP */ "Minimum number of link", 14599 /* RTP_MNOLR */ "192x8 minimun number of links for group reachbility. If number of links the valid for group in below this TH, the group reported as non-reachable. Relevent for FE1, to know which groups are valid for local-route", 14600 /* RTP_MULTI_CAST_TABLE_UPDATE */ "", 14601 /* RTP_MULTI_TB */ "", 14602 /* RTP_RCGLBT */ "", 14603 /* RTP_RESERVED_21 */ "INTERNAL", 14604 /* RTP_RESERVED_22 */ "INTERNAL", 14605 /* RTP_RESERVED_23 */ "INTERNAL", 14606 /* RTP_RMHMT */ "", 14607 /* RTP_RRMA */ "Each address corresponds to two consecutive Destination-ID and contains a bitmap. Each bit corresponds to a physical link.\n 1 : Destination is accessible through the link.\n 0 : Destination is not accessible through the link.\n Control cells exit the FAP only on valid links.\n Note: this table is updated automatically by a hardware process and normally should not be modified by the user.\n Note: This memory i ...", 14608 /* RTP_SCTINC */ "", 14609 /* RTP_SGR */ "192x192 Stabilize group reachability Table. The 64 copies of this table used for routing of MC queries in DRH (64 MCLBT's) . Each entry of this table can be static by write 1 in the coresponding bit in MclbtGroupStaticConfig. Else the entry will update according to connectivity of all FAP's that related to this group in FLGM table.", 14610 /* RTP_SLSCT */ "", 14611 /* RTP_TOTSF */ "", 14612 /* RTP_UNICAST_DISTRIBUTION_MEMORY */ "Each address corresponds to two consecutive Destination-ID and contains a bitmap. Each bit corresponds to a physical link.\n 1 : Destination is accessible through the link.\n 0 : Destination is not accessible through the link.\n Control cells exit the FAP only on valid links.\n Note: this table is updated automatically by a hardware process and normally should not be modified by the user.\n Note: This memory i ...", 14613 /* RTP_UNICAST_DISTRIBUTION_MEMORY_FOR_CTRL_CELLS */ "Each address corresponds to two consecutive Destination-ID and contains a bitmap. Each bit corresponds to a physical link.\n 1 : Destination is accessible through the link.\n 0 : Destination is not accessible through the link.\n Control cells exit the FAP only on valid links.\n Note: this table is updated automatically by a hardware process and normally should not be modified by the user.\n Note: This memory i ...", 14614 /* RTP_UNICAST_DISTRIBUTION_MEMORY_FOR_DATA_CELLS */ "Each address corresponds to two consecutive Destination-ID and contains a bitmap. Each bit corresponds to a physical link.\n 1 : Destination is accessible through the link.\n 0 : Destination is not accessible through the link.\n Data cells destined for a destination exit the FAP only on valid links.\n Note, this table is updated automatically by a hardware process and normally should not be modified by the user.\n ...", 14615 /* RXBADTAGPKTS */ "Receive Bad Tag Frame Counter - Implemented in isec_RxTagUntagNoneBad", 14616 /* RXLP_CHANNEL_CONTROL_BUFFER */ "", 14617 /* RXLP_DEBUG_COUNTER0 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER0_TRIGGER_SELECT register", 14618 /* RXLP_DEBUG_COUNTER1 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER1_TRIGGER_SELECT register", 14619 /* RXLP_DEBUG_COUNTER2 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER2_TRIGGER_SELECT register", 14620 /* RXLP_DEBUG_COUNTER3 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER3_TRIGGER_SELECT register", 14621 /* RXLP_DEBUG_COUNTER4 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER4_TRIGGER_SELECT register", 14622 /* RXLP_DEBUG_COUNTER5 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER5_TRIGGER_SELECT register", 14623 /* RXLP_DEBUG_COUNTER6 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER6_TRIGGER_SELECT register", 14624 /* RXLP_DEBUG_COUNTER7 */ "This table counts the triggers set in RXLP_DEBUG_COUNTER7_TRIGGER_SELECT register", 14625 /* RXLP_DEBUG_COUNTER8 */ "This table counts the number of Fragment-Bytes/stream transmitted by RXLP", 14626 /* RXLP_DEBUG_COUNTER9 */ "This table counts the number of Fragments/stream transmitted by RXLP", 14627 /* RXLP_DEBUG_COUNTER10 */ "This table counts the number of Frame-Bytes/stream transmitted by RXLP", 14628 /* RXLP_DEBUG_COUNTER11 */ "This table counts the number of Frames/stream transmitted by RXLP", 14629 /* RXLP_DFC_MSG_BIT_REMAP_PORT_0 */ "External -> Remapped translation table", 14630 /* RXLP_DFC_MSG_BIT_REMAP_PORT_1 */ "External -> Remapped translation table", 14631 /* RXLP_DFC_MSG_BIT_REMAP_PORT_2 */ "External -> Remapped translation table", 14632 /* RXLP_DFC_MSG_BIT_REMAP_PORT_3 */ "External -> Remapped translation table", 14633 /* RXLP_ERROR_ACTION_MAP_DATA */ "", 14634 /* RXLP_ERROR_ACTION_MAP_TCAM */ "Interrupt Data Log Memory that stores the fragment information corresponding to an error case log", 14635 /* RXLP_INTERNAL_STREAM_MAP_PORT_0 */ "Maps (External Stream ID - RXLP_PORT_STREAM_ID_BASE) to internal stream ID in the range 0-127. There is one copy of this table for each port. The internal stream IDs configured in this table should be unique across the four ports associated with the RXLP slice.", 14636 /* RXLP_INTERNAL_STREAM_MAP_PORT_1 */ "Maps (External Stream ID - RXLP_PORT_STREAM_ID_BASE) to internal stream ID in the range 0-127. There is one copy of this table for each port. The internal stream IDs configured in this table should be unique across the four ports associated with the RXLP slice.", 14637 /* RXLP_INTERNAL_STREAM_MAP_PORT_2 */ "Maps (External Stream ID - RXLP_PORT_STREAM_ID_BASE) to internal stream ID in the range 0-127. There is one copy of this table for each port. The internal stream IDs configured in this table should be unique across the four ports associated with the RXLP slice.", 14638 /* RXLP_INTERNAL_STREAM_MAP_PORT_3 */ "Maps (External Stream ID - RXLP_PORT_STREAM_ID_BASE) to internal stream ID in the range 0-127. There is one copy of this table for each port. The internal stream IDs configured in this table should be unique across the four ports associated with the RXLP slice.", 14639 /* RXLP_INTR_DATA_MEM */ "Interrupt Data Log Memory that stores the fragment information corresponding to an error case log", 14640 /* RXLP_MAX_FRAME_SIZE */ "External -> Remapped translation table", 14641 /* RXNOSCIPKTS */ "Receive Unknown SCI Discarded Frame Counter - Implemented in isec_RxSCIUnknownNonePkts", 14642 /* RXNOTAGPKTS */ "Receive No Tag Frame Counter - Implemented in isec_RxTagUntagNoneBad", 14643 /* RXSAINVLDPKTS */ "Receive SA Invalid Frame Counter", 14644 /* RXSANOTUSINGSAPKTS */ "Receive Unused SA Discarded Encrypted Frame Counter", 14645 /* RXSANOTVLDPKTS */ "Receive SA Invalid Frame Counter", 14646 /* RXSAOKPKTS */ "Receive SA Valid Frame Counter", 14647 /* RXSAUNUSEDSAPKTS */ "Receive Unused SA Unencrypted Frame Counter", 14648 /* RXSCDCRPTBYT */ "Receive Encrypted Frame Octet Count for each SC", 14649 /* RXSCDLYPKTS */ "Receive PN Violation Frame Counter for SC", 14650 /* RXSCINVLDPKTS */ "Summation of Receive SA Invalid Frame Counter for SC", 14651 /* RXSCLATEPKTS */ "Receive PN Violation Discarded Frame Counter for SC", 14652 /* RXSCNOTUSINGSAPKTS */ "Summation of Receive Unused SA Encrypted Frame Counter for SC", 14653 /* RXSCNOTVLDPKTS */ "Summation of Receive SA Not Valid Frame Counter for SC", 14654 /* RXSCOKPKTS */ "Summation of Receive SA Valid Frame Counter for SC", 14655 /* RXSCUNCHKPKTS */ "Receive Unchecked Frame Counter for SC", 14656 /* RXSCUNUSEDSAPKTS */ "Summation of Receive Unused SA Unencrypted Frame Counter for SC", 14657 /* RXSCVLDTBYT */ "Receive Authentication Only Frame Octet Count for SC", 14658 /* RXUNKNOWNSCIPKTS */ "Receive Unknown SCI Frame Counter - Implemented in isec_RxSCIUnknownNonePkts", 14659 /* RXUNTAGPKTS */ "Receive Untagged Frame Counter - Implemented in isec_RxTagUntagNoneBad", 14660 /* RX_LKUP_1588_MEM_400G */ "PM8x50 RX 1588 Lookup Memory for 400G", 14661 /* RX_LKUP_1588_MEM_MPP0 */ "PM8x50 RX 1588 Lookup Memory for MPP0", 14662 /* RX_LKUP_1588_MEM_MPP1 */ "PM8x50 RX 1588 Lookup Memory for MPP1", 14663 /* RX_PROT_GROUP_TABLE */ "Protection Switching Drop Enable.", 14664 /* RX_PROT_GROUP_TABLE2 */ "Protection Switching Drop Enable.", 14665 /* RX_PROT_GROUP_TABLE_1 */ "Protection Switching Drop Enable.", 14666 /* RX_PROT_GROUP_TABLE_1_DMA */ "Protection Switching Drop Enable DMA view-1.", 14667 /* RX_PROT_GROUP_TABLE_DMA */ "Protection Switching Drop Enable DMA view-1.", 14668 /* SCH_BFC_FLOW_BULK_DESCRIPTOR_BFBD */ "(Backdoor flow-control) Maps flow-bulk to flow QOS and Base Q-Pair, which are used for flow-fc. Each entry is for a bulk of 16 flows", 14669 /* SCH_BFC_FLOW_MAPPING_RULES_BFMR */ "(Backdoor flow-control) Maps flow's QOS and flow_id3:0 (TC) to Q-pair offset in Q-Pair FC vector. Entry 15 of this table is not valid, since QOS==0xf means no FC on the bulk", 14670 /* SCH_BUCKET_DEFICIT_BDF */ "Holds the value of token bucket deficit", 14671 /* SCH_BUCKET_DEFICIT__BDF */ "Holds the value of token bucket deficit", 14672 /* SCH_CH_NIF_CALENDAR_CONFIGURATION_CNCC */ "", 14673 /* SCH_CH_NIF_CALENDAR_CONFIGURATION__CNCC */ "", 14674 /* SCH_CH_NIF_RATES_CONFIGURATION_CNRC */ "", 14675 /* SCH_CH_NIF_RATES_CONFIGURATION__CNRC */ "", 14676 /* SCH_CIR_SHAPERS_DYNAMIC_TABEL_CSDT */ "INTERNAL", 14677 /* SCH_CIR_SHAPERS_STATIC_TABEL_CSST */ "Shaper define per each PG. holds Quanta to add and max-burst per each PG", 14678 /* SCH_CIR_SHAPERS_STATIC_TABEL__CSST */ "Shaper define per each PG. holds Quanta to add and max-burst per each PG", 14679 /* SCH_CIR_SHAPER_CALENDAR_CSC */ "Holds pointer to CSST", 14680 /* SCH_CIR_SHAPER_CALENDAR__CSC */ "Holds pointer to CSST", 14681 /* SCH_CL_SCHEDULERS_CONFIGURATION_SCC */ "The SCC is an 16k-entry memory. This memory allocates to each of the 16k class schedulers one of 256 types. (See memory SCT).\n Entry i relates to class scheduler i.", 14682 /* SCH_CL_SCHEDULERS_CONFIGURATION__SCC */ "The SCC is an 16k-entry memory. This memory allocates to each of the 16k class schedulers one of 256 types. (See memory SCT).\n Entry i relates to class scheduler i.", 14683 /* SCH_CL_SCHEDULERS_TYPE_SCT */ "The SCT is a 256-entry memory. This memory defines for each class type exactly how the class scheduler will be configured. In the table below, n relates to set of values, while X relates to a range, as it is configured by the WFQ mode.", 14684 /* SCH_CL_SCHEDULERS_TYPE__SCT */ "The SCT is a 256-entry memory. This memory defines for each class type exactly how the class scheduler will be configured. In the table below, n relates to set of values, while X relates to a range, as it is configured by the WFQ mode.", 14685 /* SCH_DEVICE_RATE_MEMORY_DRM */ "The selection of the current active rate is determined by the number of current active links (0 36) and the current status of fabric congestion, as reflected in the RCI bucket level (0 7). The address is a concatenation of NumActiveLinks and RCILevel.", 14686 /* SCH_DEVICE_RATE_MEMORY__DRM */ "The DRM is a 296-entry memory. The selection of the current active rate is determined by the number of current active links (0 36) and the current status of fabric congestion, as reflected in the RCI bucket level (0 7). The address is a concatenation of NumActiveLinks and RCILevel.", 14687 /* SCH_DSP_2_PORT_MAP_DSPP */ "Maps each of the 256 DSPs to each of the 256 HR schedulers.", 14688 /* SCH_DSP_2_PORT_MAP__DSPP */ "Maps each of the 256 DSPs to each of the 256 HR schedulers.", 14689 /* SCH_DUAL_SHAPER_MEMORY_DSM */ "The DSM is a 1K-entry memory. Each entry contains data for 16 dual bucket schedulers.", 14690 /* SCH_DUAL_SHAPER_MEMORY__DSM */ "The DSM is a 1K-entry memory. Each entry contains data for 16 dual bucket schedulers.", 14691 /* SCH_FC_MAP_FCM */ "Maps each of the 32 EGQ interface FC to each of 32 Scheduler interface FC, If more than one EGQ interface FC is mapped to one scheduer interface FC then they are bit-wise ORed", 14692 /* SCH_FC_MAP__FCM */ "Maps each of the 32 EGQ interface FC to each of 32 Scheduler interface FC, If more than one EGQ interface FC is mapped to one scheduer interface FC then they are bit-wise ORed", 14693 /* SCH_FLOW_DESCRIPTOR_MEMORY_STATIC_FDMS */ "The FDMS is a 128k-entry memory. This memory contains the Flow-Attributes. There is one entry per sub-flow. Both Schedulers and flows share this memory context.\n The Flow-Attributes are set by the user. The Flow-Attributes depend on the type of scheduler this flow is attached to.", 14694 /* SCH_FLOW_DESCRIPTOR_MEMORY_STATIC__FDMS */ "The FDMS is a 128k-entry memory. This memory contains the Flow-Attributes. There is one entry per sub-flow. Both Schedulers and flows share this memory context.\n The Flow-Attributes are set by the user. The Flow-Attributes depend on the type of scheduler this flow is attached to.", 14695 /* SCH_FLOW_GROUP_MEMORY_FGM */ "Each entry holds the group of eight schedulers, indicating the group (0-2) assigned to the scheduler. The flows belonging to a scheduler are attached to the group of the scheduler in the shaper according to this memory.", 14696 /* SCH_FLOW_GROUP_MEMORY__FGM */ "Each entry holds the group of eight schedulers, indicating the group (0-2) assigned to the scheduler. The flows belonging to a scheduler are attached to the group of the scheduler in the shaper according to this memory.", 14697 /* SCH_FLOW_INSTALLED_MEMORY_FIM */ "Each entry holds the data of 16 flows.", 14698 /* SCH_FLOW_INSTALLED_MEMORY__FIM */ "The FIM is 8192 entry memory. Each entry holds the data of 16 flows.", 14699 /* SCH_FLOW_STATUS_MEMORY_FSM */ "Each entry contains 8 bits which states the status of 4 flows. This memory holds the status of flows/schedulers. For a flow the entry reflects the status of the ingress queue. For a scheduler the entry reflects wether it has a flow attached.\n A flow may be at one of 3 states: OFF, ON-SLOW and ON-NORMAL", 14700 /* SCH_FLOW_STATUS_MEMORY_FSM_B */ "Duplication for FSM memory", 14701 /* SCH_FLOW_STATUS_MEMORY__FSM */ "The FSM is 32k entry Memory. Each entry contains 8 bits which\n states the status of 4 flows. This memory holds the status of flows/schedulers. For a flow the entry reflects the status of the ingress queue. For a scheduler the entry reflects wether it has a flow attached.\n A flow may be at one of 3 states: OFF, ON-SLOW and ON-NORMAL", 14702 /* SCH_FLOW_SUB_FLOW_FSF */ "The FSF states whether a flow is a regular or composite flow.\n One bit is allocated for every two flows.\n If the bit is not set, both odd and even flows are regular flows.\n If the Bit is set, then the Even flow is a composite flow and the odd flow is not valid.\n Each entry holds the data for 16 composite flows.", 14703 /* SCH_FLOW_SUB_FLOW__FSF */ "The FSF states whether a flow is a regular or composite flow.\n One bit is allocated for every two flows.\n If the bit is not set, both odd and even flows are regular flows.\n If the Bit is set, then the Even flow is a composite flow and the odd flow is not valid.\n Each entry holds the data for 16 composite flows.", 14704 /* SCH_FLOW_TO_FIP_MAPPING_FFM */ "The FFM is an 16K-entry memory. Each entry maps a block of eight local flow-IDs to the source-FAP. (When reading each of these eight flows, the same source FAP id will be received. For writing the DeviceNumber associated with flow x, you need to access address x13:3. Entries are meaningful only for mapping flows (And not for aggregates).", 14705 /* SCH_FLOW_TO_FIP_MAPPING__FFM */ "The FFM is an 16K-entry memory. Each entry maps a block of eight local flow-IDs to the source-FAP. (When reading each of these eight flows, the same source FAP id will be received. For writing the DeviceNumber associated with flow x, you need to access address x13:3. Entries are meaningful only for mapping flows (And not for aggregates).", 14706 /* SCH_FLOW_TO_QUEUE_MAPPING_FQM */ "The FQM is a 32k-entry memory. Each entry relates Four flows to one Base Queue, Based on SubFlowMode. If SubFlowMode is set, then four queues are mapped to four even flows. Base_flow15:2 is the address to the table.\n The mapping between the flow and the base queue is done\n Per four flows.", 14707 /* SCH_FLOW_TO_QUEUE_MAPPING__FQM */ "The FQM is a 32k-entry memory. Each entry relates Four flows to one Base Queue, Based on SubFlowMode. If SubFlowMode is set, then four queues are mapped to four even flows. Base_flow15:2 is the address to the table.\n The mapping between the flow and the base queue is done\n Per four flows.", 14708 /* SCH_FORCE_STATUS_MESSAGE */ "This register enables the CPU to emulate a Flow Status Message.\n One application of this is for CBR/TDM traffic types. As a result, a steady stream of credit is guaranteed to the flow, eliminating the delay and jitter associated with the scheduling. The Write value contains the two fields of the status message. This message is not authenticated with the FFQ; hence there is no need for the other values. This address is Write only. To check if the operation has finished, read add ...", 14709 /* SCH_HR_SCHEDULER_CONFIGURATION_SHC */ "The SHC is a 256-entry memory. This memory describes an HR scheduler operating in single, dual, or Enhanced mode. It also holds the High/Low flow-control mode to be applied for the HR.", 14710 /* SCH_HR_SCHEDULER_CONFIGURATION__SHC */ "The SHC is a 256-entry memory. This memory describes an HR scheduler operating in single, dual, or Enhanced mode. It also holds the High/Low flow-control mode to be applied for the HR.", 14711 /* SCH_MAX_PORT_QUEUE_SIZE_MPQS */ "INTERNAL", 14712 /* SCH_MEM_01300000 */ "INTERNAL", 14713 /* SCH_MEM_01400000 */ "INTERNAL", 14714 /* SCH_MEM_01500000 */ "INTERNAL", 14715 /* SCH_MEM_01600000 */ "INTERNAL", 14716 /* SCH_MEM_01700000 */ "INTERNAL", 14717 /* SCH_MEM_01800000 */ "INTERNAL", 14718 /* SCH_MEM_01900000 */ "INTERNAL", 14719 /* SCH_MEM_03000000 */ "INTERNAL", 14720 /* SCH_MEM_03100000 */ "INTERNAL", 14721 /* SCH_MEM_03200000 */ "INTERNAL", 14722 /* SCH_MEM_03300000 */ "INTERNAL", 14723 /* SCH_MEM_03400000 */ "INTERNAL", 14724 /* SCH_MEM_03500000 */ "INTERNAL", 14725 /* SCH_MEM_04700000 */ "INTERNAL", 14726 /* SCH_MEM_07100000 */ "INTERNAL", 14727 /* SCH_MEM_07300000 */ "INTERNAL", 14728 /* SCH_MEM_07500000 */ "INTERNAL", 14729 /* SCH_MEM_30000000 */ "INTERNAL", 14730 /* SCH_MEM_01A00000 */ "INTERNAL", 14731 /* SCH_MEM_01B00000 */ "INTERNAL", 14732 /* SCH_MEM_01C00000 */ "INTERNAL", 14733 /* SCH_MEM_01F00000 */ "INTERNAL", 14734 /* SCH_MEM_03A00000 */ "INTERNAL", 14735 /* SCH_MEM_03B00000 */ "INTERNAL", 14736 /* SCH_MEM_03C00000 */ "INTERNAL", 14737 /* SCH_MEM_03D00000 */ "INTERNAL", 14738 /* SCH_MEM_03E00000 */ "INTERNAL", 14739 /* SCH_MEM_03F00000 */ "INTERNAL", 14740 /* SCH_MEM_04A00000 */ "INTERNAL", 14741 /* SCH_MEM_04D00000 */ "INTERNAL", 14742 /* SCH_ONE_PORT_NIF_CONFIGURATION_OPNC */ "", 14743 /* SCH_ONE_PORT_NIF_CONFIGURATION__OPNC */ "", 14744 /* SCH_PIR_SHAPERS_DYNAMIC_TABEL_PSDT */ "INTERNAL", 14745 /* SCH_PIR_SHAPERS_STATIC_TABEL_PSST */ "Shaper define per each TC (HR). holds Quanta to add and max-burst per each HR", 14746 /* SCH_PIR_SHAPERS_STATIC_TABEL__PSST */ "Shaper define per each TC (HR). holds Quanta to add and max-burst per each HR", 14747 /* SCH_PIR_SHAPER_CALENDAR_PSC */ "Holds pointer to PSST", 14748 /* SCH_PIR_SHAPER_CALENDAR__PSC */ "Holds pointer to PSST", 14749 /* SCH_PORT_ENABLE_PORTEN */ "Enables HR scheduler to function as Scheduler-Port.", 14750 /* SCH_PORT_ENABLE__PORTEN */ "Enables HR scheduler to function as Scheduler-Port.", 14751 /* SCH_PORT_GROUP_PFGM */ "Holds Port to Group mappings", 14752 /* SCH_PORT_GROUP__PFGM */ "Holds Port to Group mappings", 14753 /* SCH_PORT_QUEUE_SIZE_PQS */ "(Pqs) - The PQS is an 256-entry memory. Each entry holds the data relevant for system RED.\n Each read returns the data of PQS and MPQS", 14754 /* SCH_PORT_QUEUE_SIZE__PQS */ "The PQS is an 256-entry memory. Each entry holds the data relevant for system RED.\n Each read returns the data of PQS and MPQS", 14755 /* SCH_PORT_SCHEDULER_MAP_PSM */ "Holds the mapping of each of the 8 HR schedulers to each of the 8PGs and WFQ of the Port-Scheduler (PS)", 14756 /* SCH_PORT_SCHEDULER_MAP__PSM */ "Holds the mapping of each of the 8 HR schedulers to each of the 8PGs and WFQ of the Port-Scheduler (PS)", 14757 /* SCH_PORT_SCHEDULER_WEIGHTS_PSW */ "Holds the weight of each PG, the weight is valid only if the relevant bit in the field PSM.PgWfqValid is set", 14758 /* SCH_PORT_SCHEDULER_WEIGHTS__PSW */ "Holds the weight of each PG, the weight is valid only if the relevant bit in the field PSM.PgWfqValid is set", 14759 /* SCH_PS_8P_RATES_PSR */ "Sets 8p-port-scheduler rate, used for dvs priority propagation", 14760 /* SCH_QPAIR_TO_PORT_MAP_QPM */ "(Backdoor flow-control) Maps each qpair from egq (both cores) to Port (HR) index. If valid bit is reset, the qpair is not mapped to any port.", 14761 /* SCH_RCI_CREDIT_JITTER_HIGH_MAP */ "Threshold is according to the fields per flow in FDMS memory concatenated with fabric RCI level\n CrdtJtrLowThXY:\n X is for HighOrLowFlow\n Y is for FabricOrLocalFlow", 14762 /* SCH_RCI_CREDIT_JITTER_LOW_MAP */ "Threshold is according to the fields per flow in FDMS memory concatenated with fabric RCI level\n CrdtJtrLowThXY:\n X is for HighOrLowFlow\n Y is for FabricOrLocalFlow", 14763 /* SCH_RCI_UNLINK_FLOW_TH_MAP */ "Threshold is according to the fields per flow in FDMS memory concatenated with fabric RCI level\n If lfsr is less than threshold, the flow will be unlinked", 14764 /* SCH_RESERVED_26 */ "INTERNAL", 14765 /* SCH_RESERVED_27 */ "INTERNAL", 14766 /* SCH_RESERVED_28 */ "INTERNAL", 14767 /* SCH_RESERVED_29 */ "INTERNAL", 14768 /* SCH_RESERVED_30 */ "INTERNAL", 14769 /* SCH_RESERVED_31 */ "INTERNAL", 14770 /* SCH_RESERVED_32 */ "INTERNAL", 14771 /* SCH_RESERVED_33 */ "INTERNAL", 14772 /* SCH_RESERVED_34 */ "INTERNAL", 14773 /* SCH_RESERVED_35 */ "INTERNAL", 14774 /* SCH_RESERVED_36 */ "INTERNAL", 14775 /* SCH_RESERVED_37 */ "INTERNAL", 14776 /* SCH_RESERVED_38 */ "INTERNAL", 14777 /* SCH_RESERVED_40 */ "INTERNAL", 14778 /* SCH_RESERVED_41 */ "INTERNAL", 14779 /* SCH_RESERVED_42 */ "INTERNAL", 14780 /* SCH_RESERVED_43 */ "INTERNAL", 14781 /* SCH_RESERVED_44 */ "INTERNAL", 14782 /* SCH_RESERVED_45 */ "INTERNAL", 14783 /* SCH_RESERVED_46 */ "INTERNAL", 14784 /* SCH_RESERVED_47 */ "INTERNAL", 14785 /* SCH_RESERVED_48 */ "INTERNAL", 14786 /* SCH_RESERVED_49 */ "INTERNAL", 14787 /* SCH_RESERVED_50 */ "INTERNAL", 14788 /* SCH_RESERVED_52 */ "INTERNAL", 14789 /* SCH_RESERVED_53 */ "INTERNAL", 14790 /* SCH_RESERVED_54 */ "INTERNAL", 14791 /* SCH_RESERVED_55 */ "INTERNAL", 14792 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_0 */ "Each of the ChNIFs maintain two calendars. Passive and Active. 4 interfaces has 1k calendar length and the rest have 256 entries calendar. The length of each calendar is configured using the variables CALALen and CALBLen for each of the Channelized NIFs. Each calendar entry specifies one Port-Scheduler. A Port-Scheduler with n occurrences in the calendar is awarded n CALxLen of its interface rate. At a single point in time, one calendar is designated as Active, and the other as Standby. The conf ...", 14793 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_1 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14794 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_2 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14795 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_3 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14796 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_4 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14797 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_5 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14798 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_6 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14799 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_7 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14800 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_8 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14801 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_9 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14802 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_10 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14803 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_11 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14804 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_12 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14805 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_13 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14806 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_14 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14807 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_15 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14808 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_16 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14809 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_17 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14810 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_18 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14811 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_19 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14812 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_20 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14813 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_21 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14814 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_22 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14815 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_23 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14816 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_24 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14817 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_25 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14818 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_26 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14819 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_27 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14820 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_28 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14821 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_29 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14822 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_30 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14823 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR_CAL_31 */ "See description of SchedulerCreditGenerationCalendar_cal0", 14824 /* SCH_SCHEDULER_CREDIT_GENERATION_CALENDAR__CAL */ "The CAL is a 20k-entry memory. Each of the eight NIFs, the CPU, and the recycle interfaces maintain two calendars. Passive and Active. In total there are 20 calendars (10 Interfaces x 2 Calendars). Each calendar has 1k entries. The length of each calendar is configured using the variables CALALen and CALBLen for each of the 8 Channelized NIFs, the CPU, and the Recycle. Each calendar entry specifies one HR-Scheduler. An HR-Scheduler with n occurrences in the calendar is awarded n CALxLen of its i ...", 14825 /* SCH_SCHEDULER_ENABLE_MEMORY_SEM */ "The SEM is a 4k-entry memoryeach entry holds data for eight schedulers.\n The Scheduler-Enable-Memory has one bit per scheduler. If a bit is set, this indicates that the corresponding scheduler is in fact used as a scheduler; if not set this indicates that the scheduler is not used and the flow that feeds credits to the scheduler is free to be used for other purposes.\n There are a total of 16k schedulers:\n 8192 Class schedulers (In entries 0-1 ...", 14826 /* SCH_SCHEDULER_ENABLE_MEMORY_SEM_B */ "INTERNAL", 14827 /* SCH_SCHEDULER_ENABLE_MEMORY__SEM */ "The SEM is a 4k-entry memoryeach entry holds data for eight schedulers.\n The Scheduler-Enable-Memory has one bit per scheduler. If a bit is set, this indicates that the corresponding scheduler is in fact used as a scheduler; if not set this indicates that the scheduler is not used and the flow that feeds credits to the scheduler is free to be used for other purposes.\n There are a total of 16k schedulers:\n 8192 Class schedulers (In entries 0-1 ...", 14828 /* SCH_SCHEDULER_INIT */ "Initialization of the scheduler is done in order to initialize all dynamic structures. The user should initialize the scheduler in the start up sequence by writing to the bit below. This is done by an indirect write to the address below, which will start a process that initializes the internal structures of the scheduler. The initialization process takes approximately 56K core clocks to complete. To check if it is finished, read the register 040. Wait until the trigger is reset.", 14829 /* SCH_SCH_FCR_RXI */ "SMP RXI memory", 14830 /* SCH_SHAPER_DESCRIPTOR_MEMORY_STATIC_SHDS */ "The SHDS is a 64k-entry memory. This memory contains the Shaper-Flow-Attributes. Each entry contains the data for two flows. For each flow, this memory holds the Shaper-Flow-Attributes. The Flow-Attributes are set by the user and are never modified by the logic.\n The Shaper receives a credit every four clocks. The bandwidth given to a flow is the Rate (see calculation below) multiplied by the shaper bandwidth.", 14831 /* SCH_SHAPER_DESCRIPTOR_MEMORY_STATIC__SHDS */ "The SHDS is a 64k-entry memory. This memory contains the Shaper-Flow-Attributes. Each entry contains the data for two flows. For each flow, this memory holds the Shaper-Flow-Attributes. The Flow-Attributes are set by the user and are never modified by the logic.\n The Shaper receives a credit every four clocks. The bandwidth given to a flow is the Rate (see calculation below) multiplied by the shaper bandwidth.", 14832 /* SCH_SHARED_DEVICE_RATE_SHARED_DRM */ "The DRM is a 296-entry memory. The selection of the current active rate is determined by the number of current active links (0 36) and the current status of fabric congestion, as reflected in the RCI bucket level (0 7). The address is a concatenation of NumActiveLinks and RCILevel.", 14833 /* SCH_SLOW_FACTOR_MEMORY_SFM */ "Slow Factor Memory", 14834 /* SCH_SLOW_SCALE_A_SSA */ "Slow factor from the IPS defines the entry to this table.", 14835 /* SCH_SLOW_SCALE_B_SSB */ "Slow factor from the IPS defines the entry to this table.", 14836 /* SCH_TOKEN_MEMORY_CONTROLLER_TMC */ "The token memory holds the number of tokens currently available for a sub-flow/flow/scheduler.\n Updating the initial token count is done by updating the field MaxBurst and MaxBurstUpdate in the SHDS. (Please consult API regarding update of initial values in this memory).", 14837 /* SCH_TOKEN_MEMORY_CONTROLLER_TMC_MSB */ "The token memory holds the number of tokens currently available for a sub-flow/flow/scheduler.\n Updating the initial token count is done by updating the field MaxBurst and MaxBurstUpdate in the SHDS. (Please consult API regarding update of initial values in this memory).", 14838 /* SCH_TOKEN_MEMORY_CONTROLLER__TMC */ "The TMC is a 128k-entry memory. The token memory holds the number of tokens currently available for a sub-flow/flow/scheduler.\n Updating the initial token count is done by updating the field MaxBurst and MaxBurstUpdate in the SHDS. (Please consult API regarding update of initial values in this memory).", 14839 /* SERVICE_COS_MAP */ "index by {service_cos_profile_idx[1:0], int_pri[3:0]", 14840 /* SERVICE_PORT_MAP */ "index by {service_port_profile_idx[2:0], local_dst_port[6:0]", 14841 /* SERVICE_QUEUE_MAP */ "index by {0, vid[11:0] or {1, vfi[11:0]}", 14842 /* SER_ACC_TYPE_MAP */ "Maps the ACC_TYPE to an offset to the SER_RANGE_RESULT.START_ADDR, so as to separate parity information for different pipes", 14843 /* SER_MEMORY */ "ECC/Parity bits", 14844 /* SER_RESULT_0 */ "Error information", 14845 /* SER_RESULT_1 */ "Error information", 14846 /* SER_RESULT_DATA_0 */ "Corrected SBUS data if SER_CONFIG.CORRECT_1B set and ECC mode is used, else raw SBUS data. Should be considered invalid if corresponding ERROR_0_VAL register bit is not set", 14847 /* SER_RESULT_DATA_1 */ "Corrected SBUS data if SER_CONFIG.CORRECT_1B set and ECC mode is used, else raw SBUS data. Should be considered invalid if corresponding ERROR_0_VAL register bit is not set", 14848 /* SER_RESULT_EXPECTED_0 */ "Expected ECC. In parity mode, its not updated. Valid only if SER_RESULT_CTL.ERROR_0_VAL is set", 14849 /* SER_RESULT_EXPECTED_1 */ "Expected ECC. In parity mode, its not updated. Valid only if SER_RESULT_CTL.ERROR_1_VAL is set", 14850 /* SFLOW_ING_DATA_SOURCE */ "Ingress Sflow Data Table.", 14851 /* SFLOW_ING_FLEX_DATA_SOURCE */ "Ingress Flex Sflow Data Table.", 14852 /* SGPP_CTRL_PROFILE_0 */ "SGPP Control Profile 0 Table.", 14853 /* SGPP_CTRL_PROFILE_1 */ "SGPP Control Profile 1 Table.", 14854 /* SGPP_TO_PIPE_MAPPING */ "Map SGPP to x- or y-pipe for OAM UPMEP TX packet", 14855 /* SIF_BILLING_CGM_INPUT_MEM */ "Input fifo mem", 14856 /* SIF_BILLING_EGR_INPUT_MEM */ "Input fifo mem", 14857 /* SIF_QSIZE_CGM_INPUT_MEM */ "Input fifo mem", 14858 /* SIF_ST_PORT_MEM */ "Statistics-Port data FIFO. Access to this FIFO is forbidden.", 14859 /* SOURCE_MOD_PROXY_TABLE */ "Source MODID table for Higig Lookup", 14860 /* SOURCE_TRUNK_MAP_MODBASE */ "Specifies the port(s) that is (are) CPU.", 14861 /* SOURCE_TRUNK_MAP_TABLE */ "Source Trunk Map Table", 14862 /* SOURCE_VP */ "Source Virtual Port Properties", 14863 /* SOURCE_VP_2 */ "TPID parse control for 2nd parser", 14864 /* SOURCE_VP_ATTRIBUTES_2 */ "Attributes associated with Looped back WLAN Packets.", 14865 /* SPB_BUF_LINK */ "Buffers link memory", 14866 /* SPB_CONTEXT_MRU */ "Maximum reception size for each reassembly context. Access this memory with Reassembly-context", 14867 /* SPB_CONTEXT_PROFILE_MAP */ "Map reassembly context to context profile, used for packet reject logic.", 14868 /* SPB_COUNTERS */ "Counters per reassembly context", 14869 /* SPB_COUNTERS_SHADOW */ "Counters per reassembly context, read from here also clear the counters.\n Write is not working, ignored.", 14870 /* SPB_DEL_CMD_RXI */ "Delete command RXI from IPT", 14871 /* SPB_DFM */ "Delete FIFO memory", 14872 /* SPB_FBM_0 */ "Free Buffer Memory Num0", 14873 /* SPB_FBM_1 */ "Free Buffer Memory Num1", 14874 /* SPB_IRE_RXI_CTRL */ "IRE RXI memory", 14875 /* SPB_IRE_RXI_DATA */ "IRE RXI memory", 14876 /* SPB_IRE_RXI_MEM */ "IRE RXI memory", 14877 /* SPB_PACKET_REJECT_CFG */ "Per packet profile ContextProfile2,TC3DP2 a configuration of reject or not when SPB is almost full (amount of free buffer is below a configurable TH).\n Because TH should maintain TH1 =< TH2 =< TH3 the first TH (TH1) is low priority and TH2 is high priority. for high pririty TC-DP set the RejectOnTh2 and for low priority set RejectOnTh1 or both RejectOnTh1 and RejectOnTh2.", 14878 /* SPB_PKT_RLS_RXI */ "CGM Packet Release RXI memory", 14879 /* SPB_PSF */ "PEC Pointer State FIFO", 14880 /* SPB_PSF_CTRL */ "PEC Pointer State FIFO", 14881 /* SPB_PSF_DATA */ "PEC Pointer State FIFO", 14882 /* SPB_PSM */ "PEC Pointer State Memory", 14883 /* SPB_RCNT */ "Read Counter Memory.\n Every row has 4 counters of 12b (up to 4k copies).", 14884 /* SPB_REL_BUFF_FIFO */ "Release Buffer FIFO 0-S2F 1-S2D", 14885 /* SPB_REL_RPRT_FIFO */ "Release report FIFO 0-S2F 1-S2D", 14886 /* SPB_RSM */ "PEC Reassembly State Memory", 14887 /* SPB_SRAM_ADDRESS_SPACE */ "SRAM memory space, addressable by CPU.\n Address should be logical (i.e. represent duff pointer).", 14888 /* SPB_S_2D_PDQ_RXI */ "S2D-Packet Dequeue Command RXI", 14889 /* SPB_S_2D_RPC_SORT_FIFO */ "RPC Sort FIFO", 14890 /* SPB_S_2D_TCF */ "S2D TCF", 14891 /* SPB_S_2F_PDQ_RXI */ "S2F-Packet Dequeue Command RXI", 14892 /* SPB_S_2F_RPC_SORT_FIFO */ "RPC Sort FIFO", 14893 /* SPB_S_2F_TCF */ "S2F TCF", 14894 /* SPB_TX_CMD_RPRT */ "non LCD Reports Fifo", 14895 /* SPECIAL_LABEL_CONTROL */ "My Station Protocol Enable Profile 1.", 14896 /* SPEED_ID_TABLE */ "TSC External Memory Interface to program SPEED_ID_TABLE", 14897 /* SPEED_PRIORITY_MAP_TBL */ "PM8x50 Speed Prority Mapping Table", 14898 /* SPORT_EHG_RX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 14899 /* SPORT_EHG_RX_TUNNEL_MASK */ "Embedded Higig Rx tunnel data memory", 14900 /* SPORT_EHG_TX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 14901 /* SP_GLB_EGRESS_SA_EXPIRE_STATUS */ "A status vector indicates which ingress SA has soft expired. \n\n If enabled (Ingress_SA_Expire_INT_En =1 in SP_GLB_INTR_EN register),\n an interrupt will be generated if any of the status bits is 1. Read clear.\n Offset 0 is SA 127:0, Offset 1 is SA 256:128, etc.", 14902 /* SP_GLB_EGRESS_SA_SOFT_EXPIRE_STATUS */ "A status vector indicates which ingress SA has soft expired. \n\n If enabled (Ingress_SA_Expire_INT_En =1 in SP_GLB_INTR_EN register),\n an interrupt will be generated if any of the status bits is 1. Read clear.\n Offset 0 is SA 127:0, Offset 1 is SA 256:128, etc.", 14903 /* SP_GLB_INGRESS_SA_EXPIRE_STATUS */ "A status vector indicates which ingress SA has hard expired. \n\n If enabled (Ingress_SA_Expire_INT_En =1 in SP_GLB_INTR_EN register),\n an interrupt will be generated if any of the status bits is 1. Read clear.\n Offset 0 is SA 127:0, Offset 1 is SA 256:128, etc.", 14904 /* SP_GLB_INGRESS_SA_SOFT_EXPIRE_STATUS */ "A status vector indicates which ingress SA has soft expired. \n\n If enabled (Ingress_SA_Expire_INT_En =1 in SP_GLB_INTR_EN register),\n an interrupt will be generated if any of the status bits is 1. Read clear.\n Offset 0 is SA 127:0, Offset 1 is SA 256:128, etc.", 14905 /* SQM_DEQ_QSTATE_PENDING_FIFO */ "INTERNAL", 14906 /* SQM_ENQ_COMMAND_RXI */ "INTERNAL", 14907 /* SQM_FREE_PDB_MEMORY */ "Free PDB", 14908 /* SQM_PACKET_DESCRIPTOR_MEMORY */ "Full Multicast User Count\n Number of duplications of the FullMulticast Dbuffs (UserCnt+1).", 14909 /* SQM_PDB_LINK_LIST */ "PDBLL - PDB link list", 14910 /* SQM_PDM */ "Indirect acces to Packet-Descriptor memory", 14911 /* SQM_QUEUE_DATA_MEMORY */ "Free PDB", 14912 /* SQM_TX_BUNDLE_MEMORY */ "INTERNAL", 14913 /* SQM_TX_PACKET_DESCRIPTOR_FIFOS_MEMORY */ "INTERNAL", 14914 /* SRC_COMPRESSION */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14915 /* SRC_COMPRESSION_DATA_ONLY */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14916 /* SRC_COMPRESSION_DATA_ONLY_PIPE0 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14917 /* SRC_COMPRESSION_DATA_ONLY_PIPE1 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14918 /* SRC_COMPRESSION_DATA_ONLY_PIPE2 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14919 /* SRC_COMPRESSION_DATA_ONLY_PIPE3 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14920 /* SRC_COMPRESSION_PIPE0 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14921 /* SRC_COMPRESSION_PIPE1 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14922 /* SRC_COMPRESSION_PIPE2 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14923 /* SRC_COMPRESSION_PIPE3 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14924 /* SRC_COMPRESSION_TCAM_ONLY */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14925 /* SRC_COMPRESSION_TCAM_ONLY_PIPE0 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14926 /* SRC_COMPRESSION_TCAM_ONLY_PIPE1 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14927 /* SRC_COMPRESSION_TCAM_ONLY_PIPE2 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14928 /* SRC_COMPRESSION_TCAM_ONLY_PIPE3 */ "Compresses the IPv6 SIPs. Remaps IPv4 SIPs.", 14929 /* SRC_MODID_BLOCK */ "Source Modid based blocking mask table", 14930 /* SRC_MODID_EGRESS */ "Source Modid based blocking mask table", 14931 /* SRC_MODID_INGRESS_BLOCK */ "Source Modid based blocking mask table", 14932 /* SR_EGR_COUNTER_PROFILE */ "SR Ingress Counter Profile table, Index: SR_FLOW_EGR_COUNTER_CONTROL.SR_EGR_COUNTER_PROFILE", 14933 /* SR_EGR_ING_PORT */ "SR ingress port setting table in egress pipeline. Index: SGPP.", 14934 /* SR_EGR_PORT */ "SR Egress Port configuration table.", 14935 /* SR_ETHERTYPES */ "Supervisory frame identify Ethertype setting register.", 14936 /* SR_FLOW_COUNT_POOL0 */ "Counts number over this flow.", 14937 /* SR_FLOW_COUNT_POOL1 */ "Counts number over this flow.", 14938 /* SR_FLOW_COUNT_POOL2 */ "Counts number over this flow.", 14939 /* SR_FLOW_COUNT_POOL3 */ "Counts number over this flow.", 14940 /* SR_FLOW_COUNT_POOL4 */ "Counts number over this flow.", 14941 /* SR_FLOW_COUNT_POOL5 */ "Counts number over this flow.", 14942 /* SR_FLOW_COUNT_POOL6 */ "Counts number over this flow.", 14943 /* SR_FLOW_COUNT_POOL7 */ "Counts number over this flow.", 14944 /* SR_FLOW_EGR_COUNTER_CONTROL */ "SR counter pool control table, Index: FLOWID.", 14945 /* SR_FLOW_ING_COUNTER_CONTROL */ "SR counter pool control table, Index: FLOWID.", 14946 /* SR_ING_COUNTER_PROFILE */ "SR Ingress Counter Profile table, Index: SR_FLOW_ING_COUNTER_CONTROL.SR_ING_COUNTER_PROFILE", 14947 /* SR_ING_EGR_PORT */ "Egress port SR configuration table.\nThis table is used to provide control setting per egress ports. Need to be in-sync with SR_EGR_PORT table", 14948 /* SR_ING_EGR_TRUNK */ "Egress port SR configuration table.\nThis table is used to provide control setting per egress trunk ports. Need to be in-sync with SR_EGR_PORT table", 14949 /* SR_L2_ENTRY */ "HW managed SR_L2_ENTRY table, all SR setting is included.", 14950 /* SR_LPORT_TAB */ "SR LOOPBACK Port Profile Table", 14951 /* SR_MAC_LEARNING */ "Per Port based L2 entry table. This table is indexed by logical port.", 14952 /* SR_MAC_LEARNING_VALID */ "Per Port based L2 entry table. This table is indexed by logical port.", 14953 /* SR_MAC_PROXY_PROFILE */ "table_description", 14954 /* SR_PORT_COUNT_OWN_RX */ "Number of SR frames received on this flow, where MAC-SA is a proxy MAC.", 14955 /* SR_PORT_COUNT_RX */ "Counts all SR-Tagged and normal Ethernet frames excluding link-local frames received on this port.", 14956 /* SR_PORT_COUNT_RX_DUPLICATES */ "Number of Duplicate SR frames received on this port.", 14957 /* SR_PORT_COUNT_RX_ERROR */ "Number of SR frames received on this port with Error.", 14958 /* SR_PORT_COUNT_RX_OUTOFORDER */ "Number of SR frames that were received out of order on this port (PKT.SN != Previous PKT.SN + 1)", 14959 /* SR_PORT_COUNT_RX_PASSED */ "Number of SR frames that are accepted and pass the duplicate discard mechanism.", 14960 /* SR_PORT_COUNT_RX_TAGGED */ "Counts number of frames transmitted over this port that with SR Tag.", 14961 /* SR_PORT_COUNT_RX_TAG_ERROR */ "Number of SR frames received on this port with Tag Error such as Wrong Length.", 14962 /* SR_PORT_COUNT_RX_WRONG_LAN */ "Number of SR-tagged frames received on this port with wrong LAN_ID where (Applies only to PRP ports)(Applies only to PRP ports).", 14963 /* SR_PORT_COUNT_TX */ "Count all SR-Tagged and normal Ethernet frames excluding link-local frames transmitted on this port.", 14964 /* SR_PORT_COUNT_TX_TAGGED */ "Counts number of frames transmitted over this port that with SR Tag.", 14965 /* SR_PORT_COUNT_UNEXPECTED_FRAME */ "Counts number of frames received on this port with wrong SR encapsulation. Such as receiving HSR frames from a PRP port.", 14966 /* SR_PORT_MTU_ERROR */ "Counts number of packets that exceed MTU size of this ingress port.", 14967 /* SR_PORT_PROXY_MAC_ERROR */ "Counts the number of packets dropped due to MAC-SA proxy error.", 14968 /* SR_PORT_SN_WINDOW_RESET */ "Counts number of times HW has reset the SN_WINDOW.", 14969 /* SR_PORT_STU_ERROR */ "Counts number of packets that exceed STU size of this ingress port.", 14970 /* SR_PORT_TABLE */ "SR feature Port Configuration Table.i\nThis table is used to control SR basic setting on per port based. The port number corresponds to the index.\nLOOPBACK port should refer to SR_LPORT_TABLE.", 14971 /* SR_PORT_TX_MTU_ERROR */ "Counts number of packets that exceed MTU size of this egress port.", 14972 /* SR_PORT_TX_STU_ERROR */ "Counts number of packets that exceed STU size of this egress port.", 14973 /* SR_PRI_OFFSET */ "New priority/ FLOWID OFFSET mapping table.", 14974 /* SR_RX */ "SR_RX setting table: All the main RX path attribution setting table.", 14975 /* SR_RX_FLOW_ID_POOL */ "HW SR RX FLOWID identify Poll table.", 14976 /* SR_SN_HISTORY_0 */ "SR serence number history table, Index by SN_HISTORY_INDEX_X + SN_WINDOW_OFFSET_X (SR_RX table)", 14977 /* SR_SN_HISTORY_1 */ "Counts number over this flow.", 14978 /* SR_SN_HISTORY_2 */ "Counts number over this flow.", 14979 /* SR_SN_HISTORY_3 */ "Counts number over this flow.", 14980 /* SR_SN_HISTORY_4 */ "Counts number over this flow.", 14981 /* SR_SN_HISTORY_5 */ "Counts number over this flow.", 14982 /* SR_SN_HISTORY_6 */ "Counts number over this flow.", 14983 /* SR_SN_HISTORY_7 */ "Counts number over this flow.", 14984 /* SR_SN_HISTORY_8 */ "Counts number over this flow.", 14985 /* SR_SN_HISTORY_9 */ "Counts number over this flow.", 14986 /* SR_SN_HISTORY_10 */ "Counts number over this flow.", 14987 /* SR_SN_HISTORY_11 */ "Counts number over this flow.", 14988 /* SR_SN_HISTORY_12 */ "Counts number over this flow.", 14989 /* SR_SN_HISTORY_13 */ "Counts number over this flow.", 14990 /* SR_SN_HISTORY_14 */ "Counts number over this flow.", 14991 /* SR_SN_HISTORY_15 */ "Counts number over this flow.", 14992 /* SR_SUPERVISORY_MAC_ADDRESS */ "PRP/ HSR Supervisory frames identify MAC address setting register.", 14993 /* SR_SUPERVISORY_MAC_ADDRESS_DOT1CB */ "802.1CB Supervisory frames identify MAC address setting register.", 14994 /* SR_TX */ "SR TX table: Index: FLOW_ID", 14995 /* SR_TX_FLOW_ID_POOL */ "HW SR TX FLOWID identify Poll table.", 14996 /* STATS_INTF_QUEUE_LIST */ "Statistics Logic Queue Reporting List", 14997 /* STATS_INTF_SERVPOOL_LIST */ "Statistics Service Pool Reporting List", 14998 /* STG_TAB */ "Spanning Tree Group state table", 14999 /* STG_TAB_2 */ "Spanning Tree Group State Table 2.", 15000 /* STU_PROFILE */ "STU check table, Indexed by STU_PROFILE_INDEX (5 bits)", 15001 /* SUBPORT_ID_TO_SGPP_MAP */ "Subport id to Sgpp table.", 15002 /* SUBPORT_ID_TO_SGPP_MAP_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15003 /* SUBPORT_ID_TO_SGPP_MAP_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15004 /* SUBPORT_ID_TO_SGPP_MAP_ECC */ "ECC Table.", 15005 /* SUBPORT_ID_TO_SGPP_MAP_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 15006 /* SUBPORT_ID_TO_SGPP_MAP_KEY_ATTRIBUTES */ "Key Attributes Table.", 15007 /* SUBPORT_ID_TO_SGPP_MAP_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15008 /* SUBPORT_ID_TO_SGPP_MAP_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15009 /* SUBPORT_TAG_SGPP_MAP */ "Used for mapping COE subtending port to SGPP.", 15010 /* SUBPORT_TAG_SGPP_MAP_DATA_ONLY */ "SUBPORT_TAG_SGPP_MAP data only view.", 15011 /* SUBPORT_TAG_SGPP_MAP_ONLY */ "SUBPORT_TAG_SGPP_MAP TCAM only view", 15012 /* SUBPORT_TAG_TO_PP_PORT_MAP */ "SPVID to SGPP conversion table for Triple Vlan Application.\nThis table is looked up if PORT_TABLE.PORT_TYPE=4 i.e., CASCADED_FOR_TRIPLE_VLAN", 15013 /* SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY */ "SPVID to SGPP conversion table for Triple Vlan Application.\nThis table is looked up if PORT_TABLE.PORT_TYPE=4 i.e., CASCADED_FOR_TRIPLE_VLAN", 15014 /* SUBPORT_TAG_TO_PP_PORT_MAP_ONLY */ "Subport Tag to ingress Packet Processing Port conversion table for Triple Vlan Application.\nThis table is looked up if PORT_TABLE.PORT_TYPE=4 i.e., CASCADED_FOR_TRIPLE_VLAN", 15015 /* SUB_PORT_DATA */ "SUB_PORT_DATA", 15016 /* SUB_PORT_POLICY_TABLE */ "SUB_PORT_POLICY_TABLE", 15017 /* SVC_METER_OFFSET_POLICY_TABLE */ "POLICY TABLE FOR SVC_METER_OFFSET_TCAM", 15018 /* SVC_METER_OFFSET_TCAM */ "TCAM FOR SVC_METER_OFFSET_TCAM", 15019 /* SVM_DBG_01 */ "Used for determining the final outgoing color for all modes except hierarchial mode", 15020 /* SVM_DBG_02 */ "Used for determining the final outgoing color for all modes except hierarchial mode", 15021 /* SVM_DBG_03 */ "Used for determining the updates of Micro and macro committed buckets in Hierarchial mode", 15022 /* SVM_MACROFLOW_INDEX_TABLE */ "Used for computing the final meter index from the base meter index", 15023 /* SVM_METER_TABLE */ "Used for computing the final meter index from the base meter index", 15024 /* SVM_OFFSET_TABLE */ "Used for computing the final meter index from the base meter index", 15025 /* SVM_POLICY_TABLE */ "Used for computing the final meter index from the base meter index", 15026 /* SVP_ATTRS_1 */ "Source Virtual Port Properties.", 15027 /* SVP_CTRL_PROFILE_0 */ "Source Virtual Port Properties required earlier in processing", 15028 /* SVP_CTRL_PROFILE_1 */ "SVP Control profile Table 1.", 15029 /* SVP_DISABLE_VLAN_CHECKS_TAB */ "Contains cntrls assoc with the 4K VLANs.", 15030 /* SVP_PROFILE */ "Source VP Properties. Indexed by SVP_ATTRS_2.SVP_PROFILE", 15031 /* SYSTEM_CONFIG_TABLE */ "System Port Table. Holds fields necessary to futher parse a higig packet, address = {src_modid[6:0], src_port[5:0]} FeatureSpecific-Ethernet", 15032 /* SYSTEM_CONFIG_TABLE_MODBASE */ "Specifies the port(s) that is (are) CPU.", 15033 /* SYS_PORTMAP */ "System Port Mapping Table (maps local system port number to a local physical port number)", 15034 /* TABLE0_LOG_TO_PHY_MAP */ "Table 0 (VLAN_XLATE) Logical to Physical address mapping. Maps upper 6 bits of the address.", 15035 /* TABLE1_LOG_TO_PHY_MAP */ "Table 1 (L2_ENTRY) Logical to Physical address mapping. Maps upper 6 bits of the address.", 15036 /* TABLE2_LOG_TO_PHY_MAP */ "Table 2 (L3_ENTRY) Logical to Physical address mapping. Maps upper 6 bits of the address.", 15037 /* TABLE3_LOG_TO_PHY_MAP */ "Table 3 (EP_VLAN_XLATE) Logical to Physical address mapping. Maps upper 6 bits of the address.", 15038 /* TABLE4_LOG_TO_PHY_MAP */ "Table 4 (MPLS_ENTRY) Logical to Physical address mapping. Maps upper 6 bits of the address.", 15039 /* TAF_GATE_BYTES_LEFT */ "Gate Control register.", 15040 /* TAF_GATE_CONTROL */ "Gate Control register.", 15041 /* TAF_GATE_CTL_TBL0_P0 */ "TAF control list table", 15042 /* TAF_GATE_CTL_TBL0_P1 */ "TAF control list table", 15043 /* TAF_GATE_CTL_TBL0_P2 */ "TAF control list table", 15044 /* TAF_GATE_CTL_TBL0_P3 */ "TAF control list table", 15045 /* TAF_GATE_CTL_TBL0_P4 */ "TAF control list table", 15046 /* TAF_GATE_CTL_TBL0_P5 */ "TAF control list table", 15047 /* TAF_GATE_CTL_TBL0_P6 */ "TAF control list table", 15048 /* TAF_GATE_CTL_TBL0_P7 */ "TAF control list table", 15049 /* TAF_GATE_CTL_TBL0_P8 */ "TAF control list table", 15050 /* TAF_GATE_CTL_TBL0_P9 */ "TAF control list table", 15051 /* TAF_GATE_CTL_TBL0_P10 */ "TAF control list table", 15052 /* TAF_GATE_CTL_TBL0_P11 */ "TAF control list table", 15053 /* TAF_GATE_CTL_TBL0_P12 */ "TAF control list table", 15054 /* TAF_GATE_CTL_TBL0_P13 */ "TAF control list table", 15055 /* TAF_GATE_CTL_TBL0_P14 */ "TAF control list table", 15056 /* TAF_GATE_CTL_TBL0_P15 */ "TAF control list table", 15057 /* TAF_GATE_CTL_TBL0_P16 */ "TAF control list table", 15058 /* TAF_GATE_CTL_TBL0_P17 */ "TAF control list table", 15059 /* TAF_GATE_CTL_TBL0_P18 */ "TAF control list table", 15060 /* TAF_GATE_CTL_TBL0_P19 */ "TAF control list table", 15061 /* TAF_GATE_CTL_TBL0_P20 */ "TAF control list table", 15062 /* TAF_GATE_CTL_TBL0_P21 */ "TAF control list table", 15063 /* TAF_GATE_CTL_TBL0_P22 */ "TAF control list table", 15064 /* TAF_GATE_CTL_TBL0_P23 */ "TAF control list table", 15065 /* TAF_GATE_CTL_TBL0_P24 */ "TAF control list table", 15066 /* TAF_GATE_CTL_TBL0_P25 */ "TAF control list table", 15067 /* TAF_GATE_CTL_TBL0_P26 */ "TAF control list table", 15068 /* TAF_GATE_CTL_TBL0_P27 */ "TAF control list table", 15069 /* TAF_GATE_CTL_TBL0_P28 */ "TAF control list table", 15070 /* TAF_GATE_CTL_TBL0_P29 */ "TAF control list table", 15071 /* TAF_GATE_CTL_TBL0_P30 */ "TAF control list table", 15072 /* TAF_GATE_CTL_TBL0_P31 */ "TAF control list table", 15073 /* TAF_GATE_CTL_TBL0_P32 */ "TAF control list table", 15074 /* TAF_GATE_CTL_TBL0_P33 */ "TAF control list table", 15075 /* TAF_GATE_CTL_TBL0_P34 */ "TAF control list table", 15076 /* TAF_GATE_CTL_TBL0_P35 */ "TAF control list table", 15077 /* TAF_GATE_CTL_TBL0_P36 */ "TAF control list table", 15078 /* TAF_GATE_CTL_TBL0_P37 */ "TAF control list table", 15079 /* TAF_GATE_CTL_TBL0_P38 */ "TAF control list table", 15080 /* TAF_GATE_CTL_TBL0_P39 */ "TAF control list table", 15081 /* TAF_GATE_CTL_TBL0_P40 */ "TAF control list table", 15082 /* TAF_GATE_CTL_TBL0_P41 */ "TAF control list table", 15083 /* TAF_GATE_CTL_TBL0_P42 */ "TAF control list table", 15084 /* TAF_GATE_CTL_TBL0_P43 */ "TAF control list table", 15085 /* TAF_GATE_CTL_TBL0_P44 */ "TAF control list table", 15086 /* TAF_GATE_CTL_TBL0_P45 */ "TAF control list table", 15087 /* TAF_GATE_CTL_TBL0_P46 */ "TAF control list table", 15088 /* TAF_GATE_CTL_TBL0_P47 */ "TAF control list table", 15089 /* TAF_GATE_CTL_TBL0_P48 */ "TAF control list table", 15090 /* TAF_GATE_CTL_TBL0_P49 */ "TAF control list table", 15091 /* TAF_GATE_CTL_TBL0_P50 */ "TAF control list table", 15092 /* TAF_GATE_CTL_TBL0_P51 */ "TAF control list table", 15093 /* TAF_GATE_CTL_TBL0_P52 */ "TAF control list table", 15094 /* TAF_GATE_CTL_TBL0_P53 */ "TAF control list table", 15095 /* TAF_GATE_CTL_TBL0_P54 */ "TAF control list table", 15096 /* TAF_GATE_CTL_TBL0_P55 */ "TAF control list table", 15097 /* TAF_GATE_CTL_TBL0_P56 */ "TAF control list table", 15098 /* TAF_GATE_CTL_TBL0_P57 */ "TAF control list table", 15099 /* TAF_GATE_CTL_TBL0_P58 */ "TAF control list table", 15100 /* TAF_GATE_CTL_TBL0_P59 */ "TAF control list table", 15101 /* TAF_GATE_CTL_TBL0_P60 */ "TAF control list table", 15102 /* TAF_GATE_CTL_TBL0_P61 */ "TAF control list table", 15103 /* TAF_GATE_CTL_TBL0_P62 */ "TAF control list table", 15104 /* TAF_GATE_CTL_TBL0_P63 */ "TAF control list table", 15105 /* TAF_GATE_CTL_TBL0_P64 */ "TAF control list table", 15106 /* TAF_GATE_CTL_TBL0_P65 */ "TAF control list table", 15107 /* TAF_GATE_CTL_TBL0_P66 */ "TAF control list table", 15108 /* TAF_GATE_CTL_TBL0_P67 */ "TAF control list table", 15109 /* TAF_GATE_CTL_TBL0_P68 */ "TAF control list table", 15110 /* TAF_GATE_CTL_TBL0_P69 */ "TAF control list table", 15111 /* TAF_GATE_CTL_TBL0_P70 */ "TAF control list table", 15112 /* TAF_GATE_CTL_TBL0_P71 */ "TAF control list table", 15113 /* TAF_GATE_CTL_TBL0_P72 */ "TAF control list table", 15114 /* TAF_GATE_CTL_TBL0_P73 */ "TAF control list table", 15115 /* TAF_GATE_CTL_TBL0_P74 */ "TAF control list table", 15116 /* TAF_GATE_CTL_TBL0_P75 */ "TAF control list table", 15117 /* TAF_GATE_CTL_TBL0_P76 */ "TAF control list table", 15118 /* TAF_GATE_CTL_TBL0_P77 */ "TAF control list table", 15119 /* TAF_GATE_CTL_TBL0_P78 */ "TAF control list table", 15120 /* TAF_GATE_CTL_TBL0_P79 */ "TAF control list table", 15121 /* TAF_GATE_CTL_TBL0_P80 */ "TAF control list table", 15122 /* TAF_GATE_CTL_TBL0_P81 */ "TAF control list table", 15123 /* TAF_GATE_CTL_TBL0_P82 */ "TAF control list table", 15124 /* TAF_GATE_CTL_TBL0_P83 */ "TAF control list table", 15125 /* TAF_GATE_CTL_TBL0_P84 */ "TAF control list table", 15126 /* TAF_GATE_CTL_TBL0_P85 */ "TAF control list table", 15127 /* TAF_GATE_CTL_TBL0_P86 */ "TAF control list table", 15128 /* TAF_GATE_CTL_TBL0_P87 */ "TAF control list table", 15129 /* TAF_GATE_CTL_TBL0_P88 */ "TAF control list table", 15130 /* TAF_GATE_CTL_TBL0_P89 */ "TAF control list table", 15131 /* TAF_GATE_CTL_TBL0_P90 */ "TAF control list table", 15132 /* TAF_GATE_CTL_TBL0_P91 */ "TAF control list table", 15133 /* TAF_GATE_CTL_TBL0_P92 */ "TAF control list table", 15134 /* TAF_GATE_CTL_TBL0_P93 */ "TAF control list table", 15135 /* TAF_GATE_CTL_TBL0_P94 */ "TAF control list table", 15136 /* TAF_GATE_CTL_TBL0_P95 */ "TAF control list table", 15137 /* TAF_GATE_CTL_TBL0_P96 */ "TAF control list table", 15138 /* TAF_GATE_CTL_TBL0_P97 */ "TAF control list table", 15139 /* TAF_GATE_CTL_TBL0_P98 */ "TAF control list table", 15140 /* TAF_GATE_CTL_TBL0_P99 */ "TAF control list table", 15141 /* TAF_GATE_CTL_TBL0_P100 */ "TAF control list table", 15142 /* TAF_GATE_CTL_TBL0_P101 */ "TAF control list table", 15143 /* TAF_GATE_CTL_TBL0_P102 */ "TAF control list table", 15144 /* TAF_GATE_CTL_TBL0_P103 */ "TAF control list table", 15145 /* TAF_GATE_CTL_TBL0_P104 */ "TAF control list table", 15146 /* TAF_GATE_CTL_TBL0_P105 */ "TAF control list table", 15147 /* TAF_GATE_CTL_TBL0_P106 */ "TAF control list table", 15148 /* TAF_GATE_CTL_TBL0_P107 */ "TAF control list table", 15149 /* TAF_GATE_CTL_TBL0_P108 */ "TAF control list table", 15150 /* TAF_GATE_CTL_TBL0_P109 */ "TAF control list table", 15151 /* TAF_GATE_CTL_TBL0_P110 */ "TAF control list table", 15152 /* TAF_GATE_CTL_TBL0_P111 */ "TAF control list table", 15153 /* TAF_GATE_CTL_TBL0_P112 */ "TAF control list table", 15154 /* TAF_GATE_CTL_TBL0_P113 */ "TAF control list table", 15155 /* TAF_GATE_CTL_TBL0_P114 */ "TAF control list table", 15156 /* TAF_GATE_CTL_TBL0_P115 */ "TAF control list table", 15157 /* TAF_GATE_CTL_TBL0_P116 */ "TAF control list table", 15158 /* TAF_GATE_CTL_TBL0_P117 */ "TAF control list table", 15159 /* TAF_GATE_CTL_TBL0_P118 */ "TAF control list table", 15160 /* TAF_GATE_CTL_TBL0_P119 */ "TAF control list table", 15161 /* TAF_GATE_CTL_TBL0_P120 */ "TAF control list table", 15162 /* TAF_GATE_CTL_TBL0_P121 */ "TAF control list table", 15163 /* TAF_GATE_CTL_TBL0_P122 */ "TAF control list table", 15164 /* TAF_GATE_CTL_TBL0_P123 */ "TAF control list table", 15165 /* TAF_GATE_CTL_TBL0_P124 */ "TAF control list table", 15166 /* TAF_GATE_CTL_TBL0_P125 */ "TAF control list table", 15167 /* TAF_GATE_CTL_TBL0_P126 */ "TAF control list table", 15168 /* TAF_GATE_CTL_TBL0_P127 */ "TAF control list table", 15169 /* TAF_GATE_CTL_TBL1_P0 */ "TAF control list table", 15170 /* TAF_GATE_CTL_TBL1_P1 */ "TAF control list table", 15171 /* TAF_GATE_CTL_TBL1_P2 */ "TAF control list table", 15172 /* TAF_GATE_CTL_TBL1_P3 */ "TAF control list table", 15173 /* TAF_GATE_CTL_TBL1_P4 */ "TAF control list table", 15174 /* TAF_GATE_CTL_TBL1_P5 */ "TAF control list table", 15175 /* TAF_GATE_CTL_TBL1_P6 */ "TAF control list table", 15176 /* TAF_GATE_CTL_TBL1_P7 */ "TAF control list table", 15177 /* TAF_GATE_CTL_TBL1_P8 */ "TAF control list table", 15178 /* TAF_GATE_CTL_TBL1_P9 */ "TAF control list table", 15179 /* TAF_GATE_CTL_TBL1_P10 */ "TAF control list table", 15180 /* TAF_GATE_CTL_TBL1_P11 */ "TAF control list table", 15181 /* TAF_GATE_CTL_TBL1_P12 */ "TAF control list table", 15182 /* TAF_GATE_CTL_TBL1_P13 */ "TAF control list table", 15183 /* TAF_GATE_CTL_TBL1_P14 */ "TAF control list table", 15184 /* TAF_GATE_CTL_TBL1_P15 */ "TAF control list table", 15185 /* TAF_GATE_CTL_TBL1_P16 */ "TAF control list table", 15186 /* TAF_GATE_CTL_TBL1_P17 */ "TAF control list table", 15187 /* TAF_GATE_CTL_TBL1_P18 */ "TAF control list table", 15188 /* TAF_GATE_CTL_TBL1_P19 */ "TAF control list table", 15189 /* TAF_GATE_CTL_TBL1_P20 */ "TAF control list table", 15190 /* TAF_GATE_CTL_TBL1_P21 */ "TAF control list table", 15191 /* TAF_GATE_CTL_TBL1_P22 */ "TAF control list table", 15192 /* TAF_GATE_CTL_TBL1_P23 */ "TAF control list table", 15193 /* TAF_GATE_CTL_TBL1_P24 */ "TAF control list table", 15194 /* TAF_GATE_CTL_TBL1_P25 */ "TAF control list table", 15195 /* TAF_GATE_CTL_TBL1_P26 */ "TAF control list table", 15196 /* TAF_GATE_CTL_TBL1_P27 */ "TAF control list table", 15197 /* TAF_GATE_CTL_TBL1_P28 */ "TAF control list table", 15198 /* TAF_GATE_CTL_TBL1_P29 */ "TAF control list table", 15199 /* TAF_GATE_CTL_TBL1_P30 */ "TAF control list table", 15200 /* TAF_GATE_CTL_TBL1_P31 */ "TAF control list table", 15201 /* TAF_GATE_CTL_TBL1_P32 */ "TAF control list table", 15202 /* TAF_GATE_CTL_TBL1_P33 */ "TAF control list table", 15203 /* TAF_GATE_CTL_TBL1_P34 */ "TAF control list table", 15204 /* TAF_GATE_CTL_TBL1_P35 */ "TAF control list table", 15205 /* TAF_GATE_CTL_TBL1_P36 */ "TAF control list table", 15206 /* TAF_GATE_CTL_TBL1_P37 */ "TAF control list table", 15207 /* TAF_GATE_CTL_TBL1_P38 */ "TAF control list table", 15208 /* TAF_GATE_CTL_TBL1_P39 */ "TAF control list table", 15209 /* TAF_GATE_CTL_TBL1_P40 */ "TAF control list table", 15210 /* TAF_GATE_CTL_TBL1_P41 */ "TAF control list table", 15211 /* TAF_GATE_CTL_TBL1_P42 */ "TAF control list table", 15212 /* TAF_GATE_CTL_TBL1_P43 */ "TAF control list table", 15213 /* TAF_GATE_CTL_TBL1_P44 */ "TAF control list table", 15214 /* TAF_GATE_CTL_TBL1_P45 */ "TAF control list table", 15215 /* TAF_GATE_CTL_TBL1_P46 */ "TAF control list table", 15216 /* TAF_GATE_CTL_TBL1_P47 */ "TAF control list table", 15217 /* TAF_GATE_CTL_TBL1_P48 */ "TAF control list table", 15218 /* TAF_GATE_CTL_TBL1_P49 */ "TAF control list table", 15219 /* TAF_GATE_CTL_TBL1_P50 */ "TAF control list table", 15220 /* TAF_GATE_CTL_TBL1_P51 */ "TAF control list table", 15221 /* TAF_GATE_CTL_TBL1_P52 */ "TAF control list table", 15222 /* TAF_GATE_CTL_TBL1_P53 */ "TAF control list table", 15223 /* TAF_GATE_CTL_TBL1_P54 */ "TAF control list table", 15224 /* TAF_GATE_CTL_TBL1_P55 */ "TAF control list table", 15225 /* TAF_GATE_CTL_TBL1_P56 */ "TAF control list table", 15226 /* TAF_GATE_CTL_TBL1_P57 */ "TAF control list table", 15227 /* TAF_GATE_CTL_TBL1_P58 */ "TAF control list table", 15228 /* TAF_GATE_CTL_TBL1_P59 */ "TAF control list table", 15229 /* TAF_GATE_CTL_TBL1_P60 */ "TAF control list table", 15230 /* TAF_GATE_CTL_TBL1_P61 */ "TAF control list table", 15231 /* TAF_GATE_CTL_TBL1_P62 */ "TAF control list table", 15232 /* TAF_GATE_CTL_TBL1_P63 */ "TAF control list table", 15233 /* TAF_GATE_CTL_TBL1_P64 */ "TAF control list table", 15234 /* TAF_GATE_CTL_TBL1_P65 */ "TAF control list table", 15235 /* TAF_GATE_CTL_TBL1_P66 */ "TAF control list table", 15236 /* TAF_GATE_CTL_TBL1_P67 */ "TAF control list table", 15237 /* TAF_GATE_CTL_TBL1_P68 */ "TAF control list table", 15238 /* TAF_GATE_CTL_TBL1_P69 */ "TAF control list table", 15239 /* TAF_GATE_CTL_TBL1_P70 */ "TAF control list table", 15240 /* TAF_GATE_CTL_TBL1_P71 */ "TAF control list table", 15241 /* TAF_GATE_CTL_TBL1_P72 */ "TAF control list table", 15242 /* TAF_GATE_CTL_TBL1_P73 */ "TAF control list table", 15243 /* TAF_GATE_CTL_TBL1_P74 */ "TAF control list table", 15244 /* TAF_GATE_CTL_TBL1_P75 */ "TAF control list table", 15245 /* TAF_GATE_CTL_TBL1_P76 */ "TAF control list table", 15246 /* TAF_GATE_CTL_TBL1_P77 */ "TAF control list table", 15247 /* TAF_GATE_CTL_TBL1_P78 */ "TAF control list table", 15248 /* TAF_GATE_CTL_TBL1_P79 */ "TAF control list table", 15249 /* TAF_GATE_CTL_TBL1_P80 */ "TAF control list table", 15250 /* TAF_GATE_CTL_TBL1_P81 */ "TAF control list table", 15251 /* TAF_GATE_CTL_TBL1_P82 */ "TAF control list table", 15252 /* TAF_GATE_CTL_TBL1_P83 */ "TAF control list table", 15253 /* TAF_GATE_CTL_TBL1_P84 */ "TAF control list table", 15254 /* TAF_GATE_CTL_TBL1_P85 */ "TAF control list table", 15255 /* TAF_GATE_CTL_TBL1_P86 */ "TAF control list table", 15256 /* TAF_GATE_CTL_TBL1_P87 */ "TAF control list table", 15257 /* TAF_GATE_CTL_TBL1_P88 */ "TAF control list table", 15258 /* TAF_GATE_CTL_TBL1_P89 */ "TAF control list table", 15259 /* TAF_GATE_CTL_TBL1_P90 */ "TAF control list table", 15260 /* TAF_GATE_CTL_TBL1_P91 */ "TAF control list table", 15261 /* TAF_GATE_CTL_TBL1_P92 */ "TAF control list table", 15262 /* TAF_GATE_CTL_TBL1_P93 */ "TAF control list table", 15263 /* TAF_GATE_CTL_TBL1_P94 */ "TAF control list table", 15264 /* TAF_GATE_CTL_TBL1_P95 */ "TAF control list table", 15265 /* TAF_GATE_CTL_TBL1_P96 */ "TAF control list table", 15266 /* TAF_GATE_CTL_TBL1_P97 */ "TAF control list table", 15267 /* TAF_GATE_CTL_TBL1_P98 */ "TAF control list table", 15268 /* TAF_GATE_CTL_TBL1_P99 */ "TAF control list table", 15269 /* TAF_GATE_CTL_TBL1_P100 */ "TAF control list table", 15270 /* TAF_GATE_CTL_TBL1_P101 */ "TAF control list table", 15271 /* TAF_GATE_CTL_TBL1_P102 */ "TAF control list table", 15272 /* TAF_GATE_CTL_TBL1_P103 */ "TAF control list table", 15273 /* TAF_GATE_CTL_TBL1_P104 */ "TAF control list table", 15274 /* TAF_GATE_CTL_TBL1_P105 */ "TAF control list table", 15275 /* TAF_GATE_CTL_TBL1_P106 */ "TAF control list table", 15276 /* TAF_GATE_CTL_TBL1_P107 */ "TAF control list table", 15277 /* TAF_GATE_CTL_TBL1_P108 */ "TAF control list table", 15278 /* TAF_GATE_CTL_TBL1_P109 */ "TAF control list table", 15279 /* TAF_GATE_CTL_TBL1_P110 */ "TAF control list table", 15280 /* TAF_GATE_CTL_TBL1_P111 */ "TAF control list table", 15281 /* TAF_GATE_CTL_TBL1_P112 */ "TAF control list table", 15282 /* TAF_GATE_CTL_TBL1_P113 */ "TAF control list table", 15283 /* TAF_GATE_CTL_TBL1_P114 */ "TAF control list table", 15284 /* TAF_GATE_CTL_TBL1_P115 */ "TAF control list table", 15285 /* TAF_GATE_CTL_TBL1_P116 */ "TAF control list table", 15286 /* TAF_GATE_CTL_TBL1_P117 */ "TAF control list table", 15287 /* TAF_GATE_CTL_TBL1_P118 */ "TAF control list table", 15288 /* TAF_GATE_CTL_TBL1_P119 */ "TAF control list table", 15289 /* TAF_GATE_CTL_TBL1_P120 */ "TAF control list table", 15290 /* TAF_GATE_CTL_TBL1_P121 */ "TAF control list table", 15291 /* TAF_GATE_CTL_TBL1_P122 */ "TAF control list table", 15292 /* TAF_GATE_CTL_TBL1_P123 */ "TAF control list table", 15293 /* TAF_GATE_CTL_TBL1_P124 */ "TAF control list table", 15294 /* TAF_GATE_CTL_TBL1_P125 */ "TAF control list table", 15295 /* TAF_GATE_CTL_TBL1_P126 */ "TAF control list table", 15296 /* TAF_GATE_CTL_TBL1_P127 */ "TAF control list table", 15297 /* TAF_GATE_DROP_PACKET_COUNTER */ "The counter for packets marked TAF_DROP/TAF_PURGE through the GATE. Index by TAF_GATE_ID", 15298 /* TAF_GATE_ID_LOOKUP */ "A 4K deep table is looked up using the index {PREEMPTABLE_CELL, PRE_L2L3_INT_PRI [3:0], TAF_GATE_ID_PROFILE[6:0]} to get the final TAF_GATE_ID.", 15299 /* TAF_GATE_PASSED_PACKET_COUNTER */ "The counter for packets passed through the GATE. Index by TAF_GATE_ID", 15300 /* TAR_BITMAP_MAPPING_TABLE */ "Bitmap mapping table.\n Map Offset (2), Index(6) to destination.", 15301 /* TAR_DESTINATION_TABLE */ "This memory maps a system port ID to a queue number and a traffic class profile", 15302 /* TAR_FLOW_AGR_MAP */ "Flow-Aggregate mapping table\n Map Flow-Aggregate-ID12:0 to Flow-Quartet and Lag-Group.", 15303 /* TAR_FLOW_TABLE */ "Flow profile per Folw.\n There are 16K flows. Profile per 4 flows.\n Access this table with flow14:4 and pick profile from the entry using flow3:2", 15304 /* TAR_LAG_MAPPING */ "LAG mapping table.\n Given the LAG and its member specifies the destination.\n Entry into table is LAG, LAG-member.", 15305 /* TAR_LAG_NEXT_MEMBER */ "For LAG resolution, this memory is read, and if it is in round-robin load-balanced mode, the output received is the offset corresponding to the LAG. Note that in this case, the offset is incremented by one and written back to the memory", 15306 /* TAR_LAG_TO_LAG_RANGE */ "LAG range memory table.\n Specifies for each LAG its range", 15307 /* TAR_MCDB */ "96k Ingress Multicast Replication Data Base. (Physically shared with egress MLL table). Each multicast ID can result in up to 4k different copies of the incoming packet at the ingress FAP. Each copy is associated with a configurable Queue/destination System port and an OutLif.\n Ingress - each entry in this table can either:\n - Single copy pointed to the next entry in the linked list. The OutLif can be further used at the egress FOP as a key for Egress Multicast lookup and can be used by egress ...", 15308 /* TAR_MCDB_BITMAP_REPLICATION_ENTRY */ "Ingress\n Pointer to Bitmap replication with Outlif to use on all bitmap copies", 15309 /* TAR_MCDB_BITMAP_REPLICATION_VECTOR */ "Ingress\n Bitmap replication vector", 15310 /* TAR_MCDB_DOUBLE_REPLICATION */ "Ingress\n Double replication pointed to the next entry in the table. Each copy has dedicated Outlif. The OutLif can be further used at the egress FOP as a key for Egress Multicast lookup and can be used by egress Packet Processor.", 15311 /* TAR_MCDB_EGRESS_BITMAP_FORMAT */ "Egress:\n Generate up to 64 copies. All having the same OutLIF.", 15312 /* TAR_MCDB_EGRESS_BITMAP_POINTER_FORMAT */ "Egress:\n Generate up to 256 copies, according to the bitmap that is pointed to by the Bitmap-Pointer. All copies get the OutLIF indicated in the entry.", 15313 /* TAR_MCDB_EGRESS_DOUBLE_CUD_FORMAT */ "Egress:\n Generate up to two copies, both having the same OutLIF(36 bits) but different PP-DSP.", 15314 /* TAR_MCDB_EGRESS_TDM_FORMAT */ "Egress:\n Egress TDM Format", 15315 /* TAR_MCDB_EGRESS_TWO_COPIES_FORMAT */ "Egress:\n Generate up to two copies, each copy has its OutLIF.", 15316 /* TAR_MCDB_SINGLE_REPLICATION */ "Ingress\n Single copy pointed to the next entry in the linked list. The OutLif can be further used at the egress FOP as a key for Egress Multicast lookup and can be used by egress Packet Processor.", 15317 /* TAR_SMOOTH_DIVISION */ "Smooth division is used in lag resolution in case LagToLagRange.Mode == 2.\n Maps lag-range (from LagToLagRange) and Lag-Lb-Key to Member.\n Access this table with lag-range, lag-lb-key7:1", 15318 /* TAR_SMOOTH_DIVISION_GROUP_SIZE */ "", 15319 /* TAR_SNOOP_MIRROR_DEST_TABLE */ "Snoop and Mirror table. This memory maps the incoming snoop command or mirror command to a replication. The first half is for mirror; the second half is for snoop.\n This table is split into two parts.", 15320 /* TAR_STACK_FEC_RESOLVE */ "Access if UseStackResolve is set and destination is system port and resolved-queue16:6 == 11'h7ff.\n Access with resolved-queue5:0 lag-lb-key7:4\n The resolved StackLag is used to access StackTrunkResolve.", 15321 /* TAR_STACK_TRUNK_RESOLVE */ "Access if UseStackResolve is set and destination is system port and resolved-queue16:6 == 11'h7ff.\n Access with StackLag, lag-lb-key5:0.\n Resolved queue = BaseQueue + Traffic-Class", 15322 /* TAR_TRAFFIC_CLASS_MAPPING */ "The traffic class is mapped according to packet's source and destination.\n Table is accessed with the following key key_msb,orig_tc, where:\n * key_msb (4 bits):\n - 2'b00,TC-Mapping-Profile if Destination is System-Port-ID\n - 2'b01,Flow-Profile if Destination is Flow\n - 2'b10,2'b00 if Destination is fabric or egress multicast\n * ingress_shape (1 bit) is '0' before ingress shaping, and '1' after ingress shaping\n * orig_tc (3 bits) is the original traffic class", 15323 /* TCAM_TCAM_ACCESS_PROFILE */ "This table maps TCAM query APP-DB to an access profile. The table has 64 entries, with the index being APP-DB. Each entry defines the access profile, including the memory to access, key size, access type (direct / lookup) and action on the prefix bits.", 15324 /* TCAM_TCAM_ACTION */ "This table provides access to the TCAM Action banks. Each TCAM bank is associated with two 24-bit TCAM action memories, provided in this table. Each action table has 2K entries, and there are 24 such tables.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.", 15325 /* TCAM_TCAM_ACTION_HIT_INDICATION */ "This table provides a hit indication for each entry in each TCAM Action bank. Each TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 1K entries, divided to 128 register lines of 8-bit, and there are 12x2 such tables.", 15326 /* TCAM_TCAM_ACTION_HIT_INDICATION_SMALL */ "This table provides a hit indication for each entry in each small TCAM Action bank. Each small TCAM bank is associated with two 20-bit TCAM action memories, for which the hit indication is provided. Each action table has 128K entries, divided to 16 register lines of 8-bit, and there are 4 such tables.\n This table belongs to TcamAction24", 15327 /* TCAM_TCAM_ACTION_SMALL */ "This table provides access to the small TCAM Action banks. Each small TCAM bank is associated with two 24-bit small TCAM action memories, provided in this table. Each action table has 128 entries.\n The TCAM action table is valid for PP units ERPP, PMF, FLP and VTT.\n TcamAction24 belongs to TCAM BANK 12", 15328 /* TCAM_TCAM_BANK */ "This table provides access to the TCAM banks through read and write commands.\n The table has 12*2K*2 + 4*128*2 entries, with every entry refering to a TCAM bank.\n First 4K entries belongs to TCAM BANK 0 and so on till BANK 11.\n The bottom 4*256 entries belongs to TCAM Bank 12, 13, 14 and 15.\n Note: The bank address is 12 bits. If the lsb is clear (even address) the entry is a key. If the lsb is set (odd address) the entry is a mask\n The address msbs (bits 16:13) defines the TCAM bank the acti ...", 15329 /* TCAM_TCAM_BANK_COMMAND */ "TCAM command:\n The command can be write/read/compare. In case of write and compare the Din is needed", 15330 /* TCAM_TCAM_BANK_REPLY */ "TCAM reply. The reply is based on the command entered before.", 15331 /* TCAM_TCAM_ENTRY_ECC */ "This table holds the ECC bits for each entry in the TCAM. The table is built from 12 tables,\n Each of them with 2K entries. Each table represents ECC bits for one corressponding TCAM.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 15332 /* TCAM_TCAM_ENTRY_ECC_SMALL */ "This table holds the ECC bits for each TCAM Bank.\n The table is with 2K entries, each entry contain the ECC bits for the matched entry in TCAM-12 through 15.\n Note: If the addresss lsb is clear (even address) the entry is a key. If the addresss lsb is set (odd address) the entry is a mask.", 15333 /* TCAM_TCAM_PD_PROFILE */ "TCAM Priority Decoder profile.\n This table maps TCAM query APP-DB to a priority decoder profile. The table has 64 entries, with the index being APP-DB. Each entry defines the priority decoder profile through a bitmap selecting which TCAM banks action results will participate in the priority decoder.", 15334 /* TCB_BUFFER_METADATA */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each packet. It should be only read in frozen phase", 15335 /* TCB_BUFFER_METADATA_XPE0 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each packet. It should be only read in frozen phase", 15336 /* TCB_BUFFER_METADATA_XPE1 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each packet. It should be only read in frozen phase", 15337 /* TCB_BUFFER_METADATA_XPE2 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each packet. It should be only read in frozen phase", 15338 /* TCB_BUFFER_METADATA_XPE3 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each packet. It should be only read in frozen phase", 15339 /* TCB_EVENT_BUFFER */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each event trigger packet. It should be only read in frozen phase", 15340 /* TCB_EVENT_BUFFER_XPE0 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each event trigger packet. It should be only read in frozen phase", 15341 /* TCB_EVENT_BUFFER_XPE1 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each event trigger packet. It should be only read in frozen phase", 15342 /* TCB_EVENT_BUFFER_XPE2 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each event trigger packet. It should be only read in frozen phase", 15343 /* TCB_EVENT_BUFFER_XPE3 */ "TCB circular FIFO. It is used to store timestamp and MPB related data of each event trigger packet. It should be only read in frozen phase", 15344 /* TCB_SCRATCH_BUFFER */ "It is used to store timestamp and MPB related data of each packet", 15345 /* TCB_SCRATCH_BUFFER_XPE0_PIPE0 */ "It is used to store timestamp and MPB related data of each packet", 15346 /* TCB_SCRATCH_BUFFER_XPE0_PIPE1 */ "It is used to store timestamp and MPB related data of each packet", 15347 /* TCB_SCRATCH_BUFFER_XPE0_PIPE3 */ "It is used to store timestamp and MPB related data of each packet", 15348 /* TCB_SCRATCH_BUFFER_XPE1_PIPE0 */ "It is used to store timestamp and MPB related data of each packet", 15349 /* TCB_SCRATCH_BUFFER_XPE1_PIPE3 */ "It is used to store timestamp and MPB related data of each packet", 15350 /* TCB_SCRATCH_BUFFER_XPE2_PIPE1 */ "It is used to store timestamp and MPB related data of each packet", 15351 /* TCB_SCRATCH_BUFFER_XPE2_PIPE2 */ "It is used to store timestamp and MPB related data of each packet", 15352 /* TCB_SCRATCH_BUFFER_XPE3_PIPE1 */ "It is used to store timestamp and MPB related data of each packet", 15353 /* TCB_SCRATCH_BUFFER_XPE3_PIPE2 */ "It is used to store timestamp and MPB related data of each packet", 15354 /* TCB_THRESHOLD_PROFILE_MAP */ "It is used to store profile_ptr", 15355 /* TCB_THRESHOLD_PROFILE_MAP_A */ "It is used to store profile_ptr", 15356 /* TCB_THRESHOLD_PROFILE_MAP_A_XPE0 */ "It is used to store profile_ptr", 15357 /* TCB_THRESHOLD_PROFILE_MAP_A_XPE1 */ "It is used to store profile_ptr", 15358 /* TCB_THRESHOLD_PROFILE_MAP_A_XPE2 */ "It is used to store profile_ptr", 15359 /* TCB_THRESHOLD_PROFILE_MAP_A_XPE3 */ "It is used to store profile_ptr", 15360 /* TCB_THRESHOLD_PROFILE_MAP_B */ "It is used to store profile_ptr", 15361 /* TCB_THRESHOLD_PROFILE_MAP_B_XPE0 */ "It is used to store profile_ptr", 15362 /* TCB_THRESHOLD_PROFILE_MAP_B_XPE1 */ "It is used to store profile_ptr", 15363 /* TCB_THRESHOLD_PROFILE_MAP_B_XPE2 */ "It is used to store profile_ptr", 15364 /* TCB_THRESHOLD_PROFILE_MAP_B_XPE3 */ "It is used to store profile_ptr", 15365 /* TCB_THRESHOLD_PROFILE_MAP_XPE0 */ "It is used to store profile_ptr", 15366 /* TCB_THRESHOLD_PROFILE_MAP_XPE1 */ "It is used to store profile_ptr", 15367 /* TCB_THRESHOLD_PROFILE_MAP_XPE2 */ "It is used to store profile_ptr", 15368 /* TCB_THRESHOLD_PROFILE_MAP_XPE3 */ "It is used to store profile_ptr", 15369 /* TCP_FN */ "TCP function table to map TCP Flags to any value for an IFP key, FeatureSpecific-Ethernet", 15370 /* TCP_FN_PIPE0 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15371 /* TCP_FN_PIPE1 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15372 /* TCP_FN_PIPE2 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15373 /* TCP_FN_PIPE3 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15374 /* TCP_FN_PIPE4 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15375 /* TCP_FN_PIPE5 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15376 /* TCP_FN_PIPE6 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15377 /* TCP_FN_PIPE7 */ "TCP function table to map TCP Flags to any value for an IFP key.", 15378 /* TDM_CALENDAR0 */ "TDM Calendar 0,", 15379 /* TDM_CALENDAR1 */ "TDM Calendar 1,", 15380 /* TDM_CALENDAR0_PIPE0 */ "TDM Calendar 0,", 15381 /* TDM_CALENDAR0_PIPE1 */ "TDM Calendar 0,", 15382 /* TDM_CALENDAR0_PIPE2 */ "TDM Calendar 0,", 15383 /* TDM_CALENDAR0_PIPE3 */ "TDM Calendar 0,", 15384 /* TDM_CALENDAR1_PIPE0 */ "TDM Calendar 1,", 15385 /* TDM_CALENDAR1_PIPE1 */ "TDM Calendar 1,", 15386 /* TDM_CALENDAR1_PIPE2 */ "TDM Calendar 1,", 15387 /* TDM_CALENDAR1_PIPE3 */ "TDM Calendar 1,", 15388 /* TDU_DS_CHANNEL_ORDER_FIFO */ "Read Channel order fifo", 15389 /* TDU_DS_READ_REQ_RXI */ "Read request rxi memory", 15390 /* TDU_DS_WRITE_DATA_RXI */ "Write data rxi memory", 15391 /* TDU_DS_WRITE_REQ_RXI */ "Write request rxi memory", 15392 /* THDIEMA_THDI_PORT_PG_CNTRS */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41] * 8 + pg[0..7]. Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min count: No. of cells in PG min space\n* pg_sp_min_count No. of cells in the min space for th ...", 15393 /* THDIEMA_THDI_PORT_PG_CONFIG */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..62] * 8 + pg[0..7].Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min_limit: No. of cells reserved f ...", 15394 /* THDIEMA_THDI_PORT_SP_CNTRS */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_shared_count: No. of cells current used by this port in this service pool\n* ecc: SECDED across the other bits in this row.", 15395 /* THDIEMA_THDI_PORT_SP_CONFIG */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_port_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* sp_port_max_limit: No. of cells allowed to be used by this port in this service pool - includes the minimum allocation ...", 15396 /* THDIEXT_THDI_PORT_PG_CNTRS */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41] * 8 + pg[0..7]. Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min count: No. of cells in PG min space\n* pg_sp_min_count No. of cells in the min space for th ...", 15397 /* THDIEXT_THDI_PORT_PG_CONFIG */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..62] * 8 + pg[0..7].Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min_limit: No. of cells reserved f ...", 15398 /* THDIEXT_THDI_PORT_SP_CNTRS */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_shared_count: No. of cells current used by this port in this service pool\n* ecc: SECDED across the other bits in this row.", 15399 /* THDIEXT_THDI_PORT_SP_CONFIG */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_port_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* sp_port_max_limit: No. of cells allowed to be used by this port in this service pool - includes the minimum allocation ...", 15400 /* THDIQEN_THDI_PORT_PG_CNTRS */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41] * 8 + pg[0..7]. Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min count: No. of cells in PG min space\n* pg_sp_min_count No. of cells in the min space for th ...", 15401 /* THDIQEN_THDI_PORT_PG_CONFIG */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..62] * 8 + pg[0..7].Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min_limit: No. of cells reserved f ...", 15402 /* THDIQEN_THDI_PORT_SP_CNTRS */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_shared_count: No. of cells current used by this port in this service pool\n* ecc: SECDED across the other bits in this row.", 15403 /* THDIQEN_THDI_PORT_SP_CONFIG */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_port_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* sp_port_max_limit: No. of cells allowed to be used by this port in this service pool - includes the minimum allocation ...", 15404 /* THDIRQE_THDI_PORT_PG_CNTRS */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41] * 8 + pg[0..7]. Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min count: No. of cells in PG min space\n* pg_sp_min_count No. of cells in the min space for th ...", 15405 /* THDIRQE_THDI_PORT_PG_CONFIG */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..62] * 8 + pg[0..7].Please note that for ports supporting only one PG, there is only one location on the memory,\neg. Port 6, Pg[0..7] will all point to a same location in the memory\nEach Entry contains:\n* pg_min_limit: No. of cells reserved f ...", 15406 /* THDIRQE_THDI_PORT_SP_CNTRS */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_shared_count: No. of cells current used by this port in this service pool\n* ecc: SECDED across the other bits in this row.", 15407 /* THDIRQE_THDI_PORT_SP_CONFIG */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..41]\nEach Entry contains:\n* sp_port_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* sp_port_max_limit: No. of cells allowed to be used by this port in this service pool - includes the minimum allocation ...", 15408 /* THDI_PKT_STAT_SP_SHARED_COUNT */ "", 15409 /* THDI_PKT_STAT_SP_SHARED_COUNT_XPE0 */ "", 15410 /* THDI_PKT_STAT_SP_SHARED_COUNT_XPE1 */ "", 15411 /* THDI_PKT_STAT_SP_SHARED_COUNT_XPE2 */ "", 15412 /* THDI_PKT_STAT_SP_SHARED_COUNT_XPE3 */ "", 15413 /* THDI_PORT_PG_BST */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Threshold_Profile_Shared: Which ...", 15414 /* THDI_PORT_PG_BST_X */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15415 /* THDI_PORT_PG_BST_XPE0_PIPE0 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15416 /* THDI_PORT_PG_BST_XPE0_PIPE1 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nMemory address = port_num[0..65] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: ...", 15417 /* THDI_PORT_PG_BST_XPE0_PIPE3 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15418 /* THDI_PORT_PG_BST_XPE1_PIPE0 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15419 /* THDI_PORT_PG_BST_XPE1_PIPE3 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15420 /* THDI_PORT_PG_BST_XPE2_PIPE1 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15421 /* THDI_PORT_PG_BST_XPE2_PIPE2 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15422 /* THDI_PORT_PG_BST_XPE3_PIPE1 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15423 /* THDI_PORT_PG_BST_XPE3_PIPE2 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15424 /* THDI_PORT_PG_BST_Y */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Stat_HDRM: ...", 15425 /* THDI_PORT_PG_CNTRS */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min count: No. of cells in PG min space\n* pg_sp_min_count No. of cells in the min space for the service pool that contains this PG\n* pg_shared_count No. of cells in the shared space for this PG\n* pg_hdrm_count No. of cells in the local rese ...", 15426 /* THDI_PORT_PG_CNTRS_RT1 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15427 /* THDI_PORT_PG_CNTRS_RT2 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15428 /* THDI_PORT_PG_CNTRS_RT1_X */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15429 /* THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE0 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15430 /* THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE1 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..65] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15431 /* THDI_PORT_PG_CNTRS_RT1_XPE0_PIPE3 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15432 /* THDI_PORT_PG_CNTRS_RT1_XPE1_PIPE0 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15433 /* THDI_PORT_PG_CNTRS_RT1_XPE1_PIPE3 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15434 /* THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE1 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15435 /* THDI_PORT_PG_CNTRS_RT1_XPE2_PIPE2 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15436 /* THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE1 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15437 /* THDI_PORT_PG_CNTRS_RT1_XPE3_PIPE2 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that contains ...", 15438 /* THDI_PORT_PG_CNTRS_RT1_Y */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count No. of cells in the min space for the service pool that contai ...", 15439 /* THDI_PORT_PG_CNTRS_RT2_X */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15440 /* THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE0 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15441 /* THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE1 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..65] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15442 /* THDI_PORT_PG_CNTRS_RT2_XPE0_PIPE3 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15443 /* THDI_PORT_PG_CNTRS_RT2_XPE1_PIPE0 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15444 /* THDI_PORT_PG_CNTRS_RT2_XPE1_PIPE3 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15445 /* THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE1 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15446 /* THDI_PORT_PG_CNTRS_RT2_XPE2_PIPE2 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15447 /* THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE1 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15448 /* THDI_PORT_PG_CNTRS_RT2_XPE3_PIPE2 */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is gre ...", 15449 /* THDI_PORT_PG_CNTRS_RT2_Y */ "This memory contains the counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG is g ...", 15450 /* THDI_PORT_PG_CNTRS_SH1 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15451 /* THDI_PORT_PG_CNTRS_SH2 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15452 /* THDI_PORT_PG_CNTRS_SH1_X */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15453 /* THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE0 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15454 /* THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE1 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..65] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15455 /* THDI_PORT_PG_CNTRS_SH1_XPE0_PIPE3 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15456 /* THDI_PORT_PG_CNTRS_SH1_XPE1_PIPE0 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15457 /* THDI_PORT_PG_CNTRS_SH1_XPE1_PIPE3 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15458 /* THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE1 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15459 /* THDI_PORT_PG_CNTRS_SH1_XPE2_PIPE2 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15460 /* THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE1 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15461 /* THDI_PORT_PG_CNTRS_SH1_XPE3_PIPE2 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that c ...", 15462 /* THDI_PORT_PG_CNTRS_SH1_Y */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_count: No. of cells in PG min space\n* pg_min_count_g1: No. of cells in PG min space is greater than 1\n* pg_min_count_g0: No. of cells in PG min space is greater than 0\n* pg_sp_min_count: No. of cells in the min space for the service pool that ...", 15463 /* THDI_PORT_PG_CNTRS_SH2_X */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15464 /* THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE0 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15465 /* THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE1 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..65] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15466 /* THDI_PORT_PG_CNTRS_SH2_XPE0_PIPE3 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15467 /* THDI_PORT_PG_CNTRS_SH2_XPE1_PIPE0 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15468 /* THDI_PORT_PG_CNTRS_SH2_XPE1_PIPE3 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15469 /* THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE1 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15470 /* THDI_PORT_PG_CNTRS_SH2_XPE2_PIPE2 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15471 /* THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE1 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15472 /* THDI_PORT_PG_CNTRS_SH2_XPE3_PIPE2 */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this PG ...", 15473 /* THDI_PORT_PG_CNTRS_SH2_Y */ "This memory contains the shadow counters that need to be stored on a per port per PG basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_hdrm_count: No. of cells in the local reserved headroom for this PG.\n* pg_hdrm_count_g1: No. of cells in the local reserved headroom for this PG is greater than 1.\n* pg_hdrm_count_g0: No. of cells in the local reserved headroom for this ...", 15474 /* THDI_PORT_PG_CONFIG */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_dynamic Is the shared limit for this PG static or dynamic?\n* pg_shared_limit No. of cells allowed to be consumed in the s ...", 15475 /* THDI_PORT_PG_CONFIG0_X */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for th ...", 15476 /* THDI_PORT_PG_CONFIG0_Y */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared spac ...", 15477 /* THDI_PORT_PG_CONFIG1_X */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for th ...", 15478 /* THDI_PORT_PG_CONFIG1_Y */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared spac ...", 15479 /* THDI_PORT_PG_CONFIG2_X */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for th ...", 15480 /* THDI_PORT_PG_CONFIG2_Y */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared spac ...", 15481 /* THDI_PORT_PG_CONFIG_PIPE0 */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for ...", 15482 /* THDI_PORT_PG_CONFIG_PIPE1 */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for ...", 15483 /* THDI_PORT_PG_CONFIG_PIPE2 */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for ...", 15484 /* THDI_PORT_PG_CONFIG_PIPE3 */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for ...", 15485 /* THDI_PORT_PG_CONFIG_X */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared space for ...", 15486 /* THDI_PORT_PG_CONFIG_Y */ "This memory contains the configuration for those counters that need to be stored on a per port per PG basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* pg_min_limit: No. of cells reserved for PG min space\n* pg_shared_limit: No. of cells allowed to be consumed in the shared spac ...", 15487 /* THDI_PORT_SP_BST */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* Ing_Port_SP_BST_Threshold_Profile: Which of the eight compare profiles should be used to force a trigger.", 15488 /* THDI_PORT_SP_BST_X */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: SE ...", 15489 /* THDI_PORT_SP_BST_XPE0_PIPE0 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15490 /* THDI_PORT_SP_BST_XPE0_PIPE1 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nAfter CPU reads a memory location in Watermark mode, Hardware clears the memory location if Clear-on-read functionality is enabled in config block.\nMemory address = port_num[0..65] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: ...", 15491 /* THDI_PORT_SP_BST_XPE0_PIPE3 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15492 /* THDI_PORT_SP_BST_XPE1_PIPE0 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15493 /* THDI_PORT_SP_BST_XPE1_PIPE3 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15494 /* THDI_PORT_SP_BST_XPE2_PIPE1 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15495 /* THDI_PORT_SP_BST_XPE2_PIPE2 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15496 /* THDI_PORT_SP_BST_XPE3_PIPE1 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15497 /* THDI_PORT_SP_BST_XPE3_PIPE2 */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per SP memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..33] * 4 + spid[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* ecc: ...", 15498 /* THDI_PORT_SP_BST_Y */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[64..115] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP", 15499 /* THDI_PORT_SP_CNTRS */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* sp_shared_count: No. of cells current used by this port in this service pool\n* ecc: SECDED across the other bits in this row.", 15500 /* THDI_PORT_SP_CNTRS_RT */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15501 /* THDI_PORT_SP_CNTRS_RT_X */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..52] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15502 /* THDI_PORT_SP_CNTRS_RT_XPE0_PIPE0 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15503 /* THDI_PORT_SP_CNTRS_RT_XPE0_PIPE1 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..65] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15504 /* THDI_PORT_SP_CNTRS_RT_XPE0_PIPE3 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15505 /* THDI_PORT_SP_CNTRS_RT_XPE1_PIPE0 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15506 /* THDI_PORT_SP_CNTRS_RT_XPE1_PIPE3 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15507 /* THDI_PORT_SP_CNTRS_RT_XPE2_PIPE1 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15508 /* THDI_PORT_SP_CNTRS_RT_XPE2_PIPE2 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15509 /* THDI_PORT_SP_CNTRS_RT_XPE3_PIPE1 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15510 /* THDI_PORT_SP_CNTRS_RT_XPE3_PIPE2 */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_coun ...", 15511 /* THDI_PORT_SP_CNTRS_RT_Y */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[64..115] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_min_co ...", 15512 /* THDI_PORT_SP_CNTRS_SH */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15513 /* THDI_PORT_SP_CNTRS_SH_X */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..52] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15514 /* THDI_PORT_SP_CNTRS_SH_XPE0_PIPE0 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15515 /* THDI_PORT_SP_CNTRS_SH_XPE0_PIPE1 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..65] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15516 /* THDI_PORT_SP_CNTRS_SH_XPE0_PIPE3 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15517 /* THDI_PORT_SP_CNTRS_SH_XPE1_PIPE0 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15518 /* THDI_PORT_SP_CNTRS_SH_XPE1_PIPE3 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15519 /* THDI_PORT_SP_CNTRS_SH_XPE2_PIPE1 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15520 /* THDI_PORT_SP_CNTRS_SH_XPE2_PIPE2 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15521 /* THDI_PORT_SP_CNTRS_SH_XPE3_PIPE1 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15522 /* THDI_PORT_SP_CNTRS_SH_XPE3_PIPE2 */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp_m ...", 15523 /* THDI_PORT_SP_CNTRS_SH_Y */ "This memory contains the shadow counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to three entries will be updated via a RMW operation.\nMemory address = port_num[64..115] * 4 + sp[0..3].\nEach Entry contains:\n* sp_min_count: No. of minimum guaranteed cells current used by this port in this service pool\n* sp_min_count_g1: No. of minimum guaranteed cells current used by this port in this service pool is greater than 1\n* sp ...", 15524 /* THDI_PORT_SP_CONFIG */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* sp_port_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* sp_port_max_limit: No. of cells allowed to be used by this port in this service pool - includes the mi ...", 15525 /* THDI_PORT_SP_CONFIG0 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15526 /* THDI_PORT_SP_CONFIG1 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15527 /* THDI_PORT_SP_CONFIG2 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15528 /* THDI_PORT_SP_CONFIG0_PIPE0 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15529 /* THDI_PORT_SP_CONFIG0_PIPE1 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15530 /* THDI_PORT_SP_CONFIG0_PIPE2 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15531 /* THDI_PORT_SP_CONFIG0_PIPE3 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15532 /* THDI_PORT_SP_CONFIG0_X */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15533 /* THDI_PORT_SP_CONFIG0_Y */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15534 /* THDI_PORT_SP_CONFIG1_PIPE0 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15535 /* THDI_PORT_SP_CONFIG1_PIPE1 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15536 /* THDI_PORT_SP_CONFIG1_PIPE2 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15537 /* THDI_PORT_SP_CONFIG1_PIPE3 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15538 /* THDI_PORT_SP_CONFIG1_X */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15539 /* THDI_PORT_SP_CONFIG1_Y */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15540 /* THDI_PORT_SP_CONFIG2_PIPE0 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15541 /* THDI_PORT_SP_CONFIG2_PIPE1 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15542 /* THDI_PORT_SP_CONFIG2_PIPE2 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15543 /* THDI_PORT_SP_CONFIG2_PIPE3 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15544 /* THDI_PORT_SP_CONFIG2_X */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15545 /* THDI_PORT_SP_CONFIG2_Y */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15546 /* THDI_PORT_SP_CONFIG_PIPE0 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15547 /* THDI_PORT_SP_CONFIG_PIPE1 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15548 /* THDI_PORT_SP_CONFIG_PIPE2 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15549 /* THDI_PORT_SP_CONFIG_PIPE3 */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the equivalent row that is in the counter memory.\nMemory address = port_num[0..33] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15550 /* THDI_PORT_SP_CONFIG_X */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[0..52] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15551 /* THDI_PORT_SP_CONFIG_Y */ "This memory contains the configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be read and compared with the euqivalent row that is in the counter memory.\nMemory address = port_num[64..115] * 4 + sp[0..3].\nEach Entry contains:\n* port_sp_min_limit: No. of cells to be reserved for this port in this service pool. These are in addition to the normal pool allocation.\n* port_sp_max_limit: ...", 15552 /* THDO_CONFIG_0A */ "First physical copy of MMU_THDO_CONFIG_0", 15553 /* THDO_CONFIG_0B */ "Second physical copy of MMU_THDO_CONFIG_0", 15554 /* THDO_CONFIG_1A */ "First physical copy of MMU_THDO_CONFIG_1", 15555 /* THDO_CONFIG_1B */ "Second physical copy of MMU_THDO_CONFIG_1", 15556 /* THDO_CONFIG_EX_0A */ "First physical copy of MMU_THDO_CONFIG_EX_0", 15557 /* THDO_CONFIG_EX_0B */ "Second physical copy of MMU_THDO_CONFIG_EX_0", 15558 /* THDO_CONFIG_EX_1A */ "First physical copy of MMU_THDO_CONFIG_EX_1", 15559 /* THDO_CONFIG_EX_1B */ "Second physical copy of MMU_THDO_CONFIG_EX_1", 15560 /* THDO_OFFSET_0A */ "First physical copy of MMU_THDO_OFFSET_0", 15561 /* THDO_OFFSET_0B */ "Second physical copy of MMU_THDO_OFFSET_0", 15562 /* THDO_OFFSET_1A */ "First physical copy of MMU_THDO_OFFSET_1", 15563 /* THDO_OFFSET_1B */ "Second physical copy of MMU_THDO_OFFSET_1", 15564 /* THDO_OFFSET_EX_0A */ "First physical copy of MMU_THDO_OFFSET_EX_0", 15565 /* THDO_OFFSET_EX_0B */ "Second physical copy of MMU_THDO_OFFSET_EX_0", 15566 /* THDO_OFFSET_EX_1A */ "First physical copy of MMU_THDO_OFFSET_EX_1", 15567 /* THDO_OFFSET_EX_1B */ "Second physical copy of MMU_THDO_OFFSET_EX_1", 15568 /* THDO_OPNCOUNT_QENTRY */ "THDO Op-Node total count shadow storage for WRED access in the range 0-511", 15569 /* THDO_QCOUNT_CELL_1 */ "copy of MMU_THDO_QCOUNT_CELL_0 for queues in the range [2048...4095]", 15570 /* THDO_QCOUNT_QENTRY */ "THDO Queue total count shadow storage for WRED access for queues in the range 0-2047", 15571 /* THDO_QCOUNT_QENTRY_0 */ "THDO Queue total count shadow storage for WRED access for queues in the range 0-2047", 15572 /* THDO_QCOUNT_QENTRY_1 */ "copy of MMU_THDO_QCOUNT_QENTRY_0 for queues in the range 2048-4095", 15573 /* THDO_QRESET_VALUE_CELL_1 */ "copy of MMU_THDO_QRESET_VALUE_CELL_0 for queues > 2047", 15574 /* THDO_QRESET_VALUE_QENTRY_1 */ "copy of MMU_THDO_QRESET_VALUE_QENTRY_0 for queues in the range 2048-4095", 15575 /* THDO_QSTATUS_CELL_1 */ "copy of MMU_THDO_QSTATUS_CELL_0 for queues in the range 2048-4095", 15576 /* THDO_QSTATUS_QENTRY_1 */ "copy of MMU_THDO_QSTATUS_QENTRY_0 for queues in the range 2048-4095", 15577 /* TOS_FN */ "TOS FUNCTION TABLE FOR IFP, FeatureSpecific-Ethernet", 15578 /* TOS_FN_PIPE0 */ "TOS FUNCTION TABLE FOR IFP.", 15579 /* TOS_FN_PIPE1 */ "TOS FUNCTION TABLE FOR IFP.", 15580 /* TOS_FN_PIPE2 */ "TOS FUNCTION TABLE FOR IFP.", 15581 /* TOS_FN_PIPE3 */ "TOS FUNCTION TABLE FOR IFP.", 15582 /* TOS_FN_PIPE4 */ "TOS FUNCTION TABLE FOR IFP.", 15583 /* TOS_FN_PIPE5 */ "TOS FUNCTION TABLE FOR IFP.", 15584 /* TOS_FN_PIPE6 */ "TOS FUNCTION TABLE FOR IFP.", 15585 /* TOS_FN_PIPE7 */ "TOS FUNCTION TABLE FOR IFP.", 15586 /* TRILL_DROP_STATS */ "TRILL_DROP_STATS table.", 15587 /* TRILL_DROP_STATS_PIPE0 */ "TRILL_DROP_STATS Table. Counts the number of dropped Trill frames due to various conditions. X and Y ingress pipe are countered independently.", 15588 /* TRILL_DROP_STATS_PIPE1 */ "TRILL_DROP_STATS Table. Counts the number of dropped Trill frames due to various conditions. X and Y ingress pipe are countered independently.", 15589 /* TRILL_DROP_STATS_PIPE2 */ "TRILL_DROP_STATS Table. Counts the number of dropped Trill frames due to various conditions. X and Y ingress pipe are countered independently.", 15590 /* TRILL_DROP_STATS_PIPE3 */ "TRILL_DROP_STATS Table. Counts the number of dropped Trill frames due to various conditions. X and Y ingress pipe are countered independently.", 15591 /* TRILL_DROP_STATS_X */ "TRILL_DROP_STATS table.", 15592 /* TRILL_DROP_STATS_Y */ "TRILL_DROP_STATS table.", 15593 /* TRUNK32_CONFIG_TABLE */ "TRUNK32_CONFIG_TABLE holds fields necessary to futher parse a higig packet when the source is a TrunkID (no src_modid/port are present), address=TGID[4:0], FeatureSpecific-Ethernet", 15594 /* TRUNK32_PORT_TABLE */ "HG port PWE_PROFILE_INDEX lookup in Trunk32 mode", 15595 /* TRUNK_BITMAP */ "Source Trunk Bitmap Table", 15596 /* TRUNK_CBL_TABLE */ "Trunk (LAG) Class Based Learning Attribute Table for class based station movement. Direct index table, address = TGID[6:0]", 15597 /* TRUNK_EGR_MASK */ "Trunk Egress Block Mask Table", 15598 /* TRUNK_GROUP */ "Egress Mask Table", 15599 /* TRUNK_MEMBER */ "Contains the members in each LAG group.", 15600 /* TRUNK_RR_CNT */ "Trunk Group Round Robin Count.", 15601 /* TRUNK_RR_CNT_PIPE0 */ "Trunk Group Round Robin Count.", 15602 /* TRUNK_RR_CNT_PIPE1 */ "Trunk Group Round Robin Count.", 15603 /* TRUNK_RR_CNT_PIPE2 */ "Trunk Group Round Robin Count.", 15604 /* TRUNK_RR_CNT_PIPE3 */ "Trunk Group Round Robin Count.", 15605 /* TSN_PRI_OFFSET */ "New priority/ TSN_CIRCUIT_ID OFFSET mapping table.", 15606 /* TTL_FN */ "TTL FUNCTION TABLE FOR IFP, FeatureSpecific-Ethernet", 15607 /* TTL_FN_PIPE0 */ "TTL FUNCTION TABLE FOR IFP.", 15608 /* TTL_FN_PIPE1 */ "TTL FUNCTION TABLE FOR IFP.", 15609 /* TTL_FN_PIPE2 */ "TTL FUNCTION TABLE FOR IFP.", 15610 /* TTL_FN_PIPE3 */ "TTL FUNCTION TABLE FOR IFP.", 15611 /* TTL_FN_PIPE4 */ "TTL FUNCTION TABLE FOR IFP.", 15612 /* TTL_FN_PIPE5 */ "TTL FUNCTION TABLE FOR IFP.", 15613 /* TTL_FN_PIPE6 */ "TTL FUNCTION TABLE FOR IFP.", 15614 /* TTL_FN_PIPE7 */ "TTL FUNCTION TABLE FOR IFP.", 15615 /* TUNNEL_ADAPT_1_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table TUNNEL_ADAPT_1.", 15616 /* TUNNEL_ADAPT_1_FIXED_KEY_TABLE_ATTRS */ "VLAN_XLATE_1 Fixed Key Table Attributes.", 15617 /* TUNNEL_ADAPT_1_KEY_GEN_1_MASK */ "VLAN_XLATE_1 : Lookup1 key Mask", 15618 /* TUNNEL_ADAPT_1_KEY_GEN_1_MASK_PIPE0 */ "VLAN_XLATE_1 : Lookup1 key Mask", 15619 /* TUNNEL_ADAPT_1_KEY_GEN_1_MUX_CTRL */ "VLAN_XLATE_1 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 15620 /* TUNNEL_ADAPT_1_KEY_GEN_1_MUX_CTRL_PIPE0 */ "VLAN_XLATE_1 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 15621 /* TUNNEL_ADAPT_1_KEY_GEN_2_MASK */ "VLAN_XLATE_2 : Lookup2 key mask", 15622 /* TUNNEL_ADAPT_1_KEY_GEN_2_MASK_PIPE0 */ "VLAN_XLATE_2 : Lookup2 key mask", 15623 /* TUNNEL_ADAPT_1_KEY_GEN_2_MUX_CTRL */ "VLAN_XLATE_1 : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 15624 /* TUNNEL_ADAPT_1_KEY_GEN_2_MUX_CTRL_PIPE0 */ "VLAN_XLATE_1 : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 15625 /* TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_SRAM */ "VLAN_XLATE_1 : Flex key lookup control sram.", 15626 /* TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "VLAN_XLATE_1 : Flex key lookup control sram.", 15627 /* TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM */ "VLAN_XLATE_1 : Key Selection TCAM", 15628 /* TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "VLAN_XLATE_1 : Key Selection TCAM", 15629 /* TUNNEL_ADAPT_1_MISS_POLICY */ "VLAN_XLATE_1 Table Miss Policy.", 15630 /* TUNNEL_ADAPT_1_POLICY_STRENGTH_PROFILE */ "VLAN_XLATE_1 Table Policy Strength Profile.", 15631 /* TUNNEL_ADAPT_2_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table TUNNEL_ADAPT_2.", 15632 /* TUNNEL_ADAPT_2_FIXED_KEY_TABLE_ATTRS */ "TUNNEL_ADAPT_2 Fixed Key Table Attributes.", 15633 /* TUNNEL_ADAPT_2_KEY_GEN_1_MASK */ "MPLS_ENTRY Lookup1 key mask", 15634 /* TUNNEL_ADAPT_2_KEY_GEN_1_MASK_PIPE0 */ "MPLS_ENTRY Lookup1 key mask", 15635 /* TUNNEL_ADAPT_2_KEY_GEN_1_MUX_CTRL */ "MPLS_ENTRY : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 15636 /* TUNNEL_ADAPT_2_KEY_GEN_1_MUX_CTRL_PIPE0 */ "MPLS_ENTRY : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 15637 /* TUNNEL_ADAPT_2_KEY_GEN_2_MASK */ "MPLS_ENTRY : Lookup2 key mask", 15638 /* TUNNEL_ADAPT_2_KEY_GEN_2_MASK_PIPE0 */ "MPLS_ENTRY : Lookup2 key mask", 15639 /* TUNNEL_ADAPT_2_KEY_GEN_2_MUX_CTRL */ "MPLS_ENTRY : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 15640 /* TUNNEL_ADAPT_2_KEY_GEN_2_MUX_CTRL_PIPE0 */ "MPLS_ENTRY : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 15641 /* TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_SRAM */ "MPLS_ENTRY : Flex key lookup control sram", 15642 /* TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "MPLS_ENTRY : Flex key lookup control sram", 15643 /* TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM */ "MPLS_ENTRY : Key Selection TCAM", 15644 /* TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "MPLS_ENTRY : Key Selection TCAM", 15645 /* TUNNEL_ADAPT_2_MISS_POLICY */ "VLAN_XLATE_1 Table Miss Policy.", 15646 /* TUNNEL_ADAPT_2_POLICY_STRENGTH_PROFILE */ "VLAN_XLATE_1 Table Policy Strength Profile.", 15647 /* TUNNEL_ADAPT_3_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table TUNNEL_ADAPT_3.", 15648 /* TUNNEL_ADAPT_3_FIXED_KEY_TABLE_ATTRS */ "TUNNEL_ADAPT_3 Fixed Key Table Attributes.", 15649 /* TUNNEL_ADAPT_3_KEY_GEN_1_MASK */ "L3_TUNNEL : Lookup key[127:0] mask", 15650 /* TUNNEL_ADAPT_3_KEY_GEN_1_MASK_PIPE0 */ "L3_TUNNEL : Lookup key[127:0] mask", 15651 /* TUNNEL_ADAPT_3_KEY_GEN_1_MUX_CTRL */ "L3_TUNNEL : key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 15652 /* TUNNEL_ADAPT_3_KEY_GEN_1_MUX_CTRL_PIPE0 */ "L3_TUNNEL : key [127:0] Key Generator Profile Table that provides instructions for Key Generation", 15653 /* TUNNEL_ADAPT_3_KEY_GEN_2_MASK */ "L3 TUNNEL : Lookup key[255:128] mask", 15654 /* TUNNEL_ADAPT_3_KEY_GEN_2_MASK_PIPE0 */ "L3 TUNNEL : Lookup key[255:128] mask", 15655 /* TUNNEL_ADAPT_3_KEY_GEN_2_MUX_CTRL */ "L3_TUNNEL : key[255:128] Key Generator Profile Table that provides instructions for Key Generation", 15656 /* TUNNEL_ADAPT_3_KEY_GEN_2_MUX_CTRL_PIPE0 */ "L3_TUNNEL : key[255:128] Key Generator Profile Table that provides instructions for Key Generation", 15657 /* TUNNEL_ADAPT_3_KEY_GEN_3_MASK */ "L3_TUNNEL : Lookup key[383:256] mask", 15658 /* TUNNEL_ADAPT_3_KEY_GEN_3_MASK_PIPE0 */ "L3_TUNNEL : Lookup key[383:256] mask", 15659 /* TUNNEL_ADAPT_3_KEY_GEN_3_MUX_CTRL */ "L3_TUNNEL : key[383:256] Key Generator Profile Table that provides instructions for Key Generation", 15660 /* TUNNEL_ADAPT_3_KEY_GEN_3_MUX_CTRL_PIPE0 */ "L3_TUNNEL : key[383:256] Key Generator Profile Table that provides instructions for Key Generation", 15661 /* TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_SRAM */ "L3_TUNNEL : Flex key lookup control sram", 15662 /* TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "L3_TUNNEL : Flex key lookup control sram", 15663 /* TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM */ "L3 TUNNEL : Key Selection TCAM", 15664 /* TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "L3 TUNNEL : Key Selection TCAM", 15665 /* TUNNEL_ADAPT_3_MISS_POLICY */ "VLAN_XLATE_1 Table Miss Policy.", 15666 /* TUNNEL_ADAPT_3_POLICY_STRENGTH_PROFILE */ "VLAN_XLATE_1 Table Policy Strength Profile.", 15667 /* TUNNEL_ADAPT_4_ACTION_PROFILE */ "Contains bitmap of the actions generated by the associated table TUNNEL_ADAPT_4.", 15668 /* TUNNEL_ADAPT_4_FIXED_KEY_TABLE_ATTRS */ "VLAN_XLATE_2 Fixed Key Table Attributes.", 15669 /* TUNNEL_ADAPT_4_KEY_GEN_1_MASK */ "VLAN_XLATE_2 : Lookup1 key mask", 15670 /* TUNNEL_ADAPT_4_KEY_GEN_1_MASK_PIPE0 */ "VLAN_XLATE_2 : Lookup1 key mask", 15671 /* TUNNEL_ADAPT_4_KEY_GEN_1_MUX_CTRL */ "VLAN_XLATE_2 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 15672 /* TUNNEL_ADAPT_4_KEY_GEN_1_MUX_CTRL_PIPE0 */ "VLAN_XLATE_2 : Lookup 1 Key Generator Profile Table that provides instructions for Key Generation", 15673 /* TUNNEL_ADAPT_4_KEY_GEN_2_MASK */ "VLAN_XLATE_2 : Lookup2 key mask", 15674 /* TUNNEL_ADAPT_4_KEY_GEN_2_MASK_PIPE0 */ "VLAN_XLATE_2 : Lookup2 key mask", 15675 /* TUNNEL_ADAPT_4_KEY_GEN_2_MUX_CTRL */ "VLAN_XLATE_2 : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 15676 /* TUNNEL_ADAPT_4_KEY_GEN_2_MUX_CTRL_PIPE0 */ "VLAN_XLATE_2 : Lookup 2 Key Generator Profile Table that provides instructions for Key Generation", 15677 /* TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_SRAM */ "VLAN_XLATE_2 : Flex key lookup control sram", 15678 /* TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_SRAM_PIPE0 */ "VLAN_XLATE_2 : Flex key lookup control sram", 15679 /* TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM */ "VLAN_XLATE_2: Key Selection TCAM", 15680 /* TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAM_PIPE0 */ "VLAN_XLATE_2: Key Selection TCAM", 15681 /* TUNNEL_ADAPT_4_MISS_POLICY */ "VLAN_XLATE_1 Table Miss Policy.", 15682 /* TUNNEL_ADAPT_4_POLICY_STRENGTH_PROFILE */ "VLAN_XLATE_2 Table Policy Strength Profile.", 15683 /* TXLP_DEBUG_COUNTER0 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT0 register", 15684 /* TXLP_DEBUG_COUNTER1 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT1 register", 15685 /* TXLP_DEBUG_COUNTER2 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT2 register", 15686 /* TXLP_DEBUG_COUNTER3 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT3 register", 15687 /* TXLP_DEBUG_COUNTER4 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT4 register", 15688 /* TXLP_DEBUG_COUNTER5 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT5 register", 15689 /* TXLP_DEBUG_COUNTER6 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT6 register", 15690 /* TXLP_DEBUG_COUNTER7 */ "This table counts the triggers set in TXLP_DEBUG_COUNTER_SELECT7 register", 15691 /* TXLP_DEBUG_COUNTER8 */ "This table counts the number of Fragment-Bytes/stream transmitted by TXLP", 15692 /* TXLP_DEBUG_COUNTER9 */ "This table counts the number of Fragments/stream transmitted by TXLP", 15693 /* TXLP_DEBUG_COUNTER10 */ "This table counts the number of Frame-Bytes/stream transmitted by TXLP", 15694 /* TXLP_DEBUG_COUNTER11 */ "This table counts the number of Frames/stream transmitted by TXLP", 15695 /* TXLP_INT2EXT_STREAM_MAP_TABLE */ "Used for mapping the Internal-SID(7b) to External-SID(10b)", 15696 /* TXLP_PORT_ADDR_MAP_TABLE */ "-----------------------------------------------------------------------\nNOTE::\nTHIS TABLE HAS TO BE PROGRAMMED ONLY WHEN ATLEAST ONE OR MORE PORTS IS\nRUNNING IN NON-LP-MODE.\nWHEN ALL-PORTS ARE RUNNING IN LP MODE, DONOT PROGRAM THIS TABLE.\n-----------------------------------------------------------------------\nThis table governs the buffer allocation for the NON-LP PORTS.(4-sub-ports).\nThere is a total of 856-cell worth of storage in the TXL-DATA-BUFFER.\n856 cells have to be distributed across:\n ...", 15697 /* TXLP_PORT_MMU_REQUESTS */ "This table contains buffer-utilization information on per-port basis for the NON-LP-Ports.\nThis is READ_ONLY for s/w\",", 15698 /* TXLP_PORT_REQUESTS */ "This table contains the cell requests asserted by the port-block.", 15699 /* TXLP_PORT_STREAM_BITMAP_TABLE */ "Indicates what are the valid streams on a sub-port of a port-interface in a bitmap format.\nEach bit set indicates that SID being part of that port.\nNote that same stream cannot be enabled on more than one sub-port.\nWhen the port is in LP-mode, then Stream-ID for that sub-port is in Range [0-127] only.\nIn LP-Mode:\n===========\nSub-port | SID range\n 0 | [0-127]\n 1 | [0-127]\n 2 | [0-127]\n 3 | [0-127]\n\nHowever,When it is in Non-LP Mode following ...", 15700 /* TXLP_PORT_USED_ENTRIES */ "This table contains the entires (each 96B) occupied in the buffer on per-stream basis\non a NON-LP-PORT.", 15701 /* TXLP_STREAM_ADDR_MAP_TABLE */ "-----------------------------------------------------------------------\nNOTE::\nTHIS TABLE HAS TO BE PROGRAMMED ONLY WHEN ATLEAST ONE OR MORE PORTS IS\nRUNNING IN LP-MODE.\nWHEN ALL-PORTS ARE RUNNING IN NON-LP MODE, DONOT PROGRAM THIS TABLE.\n-----------------------------------------------------------------------\nThis table governs the buffer allocation for the streams across all LP-ENABLED ports.\nThere is a total of 856-cell worth of storage in the TXL-DATA-BUFFER.\n856 cells have to be distributed ...", 15702 /* TXLP_STREAM_MMU_REQUESTS */ "This table contains buffer-utilization information on per-stream basis for the LP-ENABLED Ports.\nThis is READ_ONLY for s/w\",", 15703 /* TXLP_STREAM_USED_ENTRIES */ "This table contains the entires (each 96B) occupied in the buffer on per-stream basis\non a LP-ENABLED-PORT.", 15704 /* TXQ_DDP_RXI_MEM */ "RXI memory", 15705 /* TXQ_DRAM_CTQ */ "", 15706 /* TXQ_DRAM_DTQ */ "", 15707 /* TXQ_DRAM_EGQC */ "", 15708 /* TXQ_DRAM_EGQD */ "", 15709 /* TXQ_ITE_RXI_MEM */ "RXI memory", 15710 /* TXQ_PER_DTQ_CFG */ "Configuration per queue of PDQ (DQCF and DBLF).", 15711 /* TXQ_PER_WFQ_CFG */ "Configuration per PTS WFQ\n addr=0 : SRAM:DRAM - DTQ0\n addr=1 : SRAM:DRAM - DTQ1\n addr=2 : SRAM:DRAM - DTQ2\n addr=4 : SRAM: DRAM - EGQ\n All the WFQs arbitrates between 2 contexts, wach on has its weight.", 15712 /* TXQ_PRIORITY_BITS_MAPPING_2_FDT */ "This table maps the incoming index, build from various packet parameters to 2 priority bits send to the FDT.\n The fields building the input of the table are:\n hp, mc, dp2 trfcls3", 15713 /* TXQ_SRAM_CTQ */ "", 15714 /* TXQ_SRAM_DTQ */ "", 15715 /* TXQ_SRAM_EGQC */ "", 15716 /* TXQ_SRAM_EGQD */ "", 15717 /* TXSACRPTPKTS */ "Transmit SA Encrypted Frame Counter", 15718 /* TXSAPRTCPKTS */ "Transmit SA Authentication Only Frame Counter", 15719 /* TXSCCRPTBYT */ "Transmit Encrypted Frame Octet Counter for SC", 15720 /* TXSCCRPTPKTS */ "Transmit Encrypted Frame Counter for SC", 15721 /* TXSCPRTCBYT */ "Transmit Authentication Only Frame Octet Counter for SC", 15722 /* TXSCPRTCPKTS */ "Transmit Authentication Only Frame Counter for SC", 15723 /* TXUNTAGPKTS */ "Transmit Untagged Frame Counter", 15724 /* TX_INITIAL_PROT_GROUP_TABLE */ "Protection Switching (backup path) Next Hop Table.", 15725 /* TX_LKUP_1588_MEM_400G */ "PM8x50 TX 1588 Lookup Memory for 400G", 15726 /* TX_LKUP_1588_MEM_MPP0 */ "PM8x50 TX 1588 Lookup Memory for MPP0", 15727 /* TX_LKUP_1588_MEM_MPP1 */ "PM8x50 TX 1588 Lookup Memory for MPP1", 15728 /* TX_PROT_GROUP_1_1_TABLE */ "Protection Switching (backup path) Next Hop Table.", 15729 /* TX_PROT_GROUP_1_TABLE */ "Protection Switching (backup path) Next Hop Table.", 15730 /* UAT_EXTRACTION_CTRL_ID_PROFILE */ "Copy-to-cpu and Drop Control for 1588 packets of different message types.", 15731 /* UDF_CONDITIONAL_CHECK_TABLE_CAM */ "Flexible Hashing Scheme conditional check matching TCAM.", 15732 /* UDF_CONDITIONAL_CHECK_TABLE_RAM */ "Flexible Hashing Scheme conditional check offsets. and masks.", 15733 /* UDF_CONDITIONAL_CHECK_TABLE_RAM_1 */ "Flexible Hashing Scheme conditional masks.", 15734 /* UDF_OFFSET */ "UDF offset table", 15735 /* UFLOW_A */ "Flow table A", 15736 /* UFLOW_B */ "UFLOW table B", 15737 /* UFT_EXTRACTION_CTRL_ID_PROFILE */ "Copy-to-cpu and Drop Control for 1588 packets of different message types.", 15738 /* UFT_SHARED_BANKS_CONTROL */ "Hash Table control register (implemented as sbus table).", 15739 /* UM_TABLE */ "TSC External Memory Interface to program UM_TABLE", 15740 /* UNKNOWN_HGI_BITMAP */ "Forwarding bitmap for unknown HGI.", 15741 /* UNKNOWN_MCAST_BLOCK_MASK */ "Unknown Multicast Block Mask, FeatureSpecific-Ethernet.", 15742 /* UNKNOWN_UCAST_BLOCK_MASK */ "Unknown Unicast Block Mask, FeatureSpecific-Ethernet.", 15743 /* VFI */ "VFI Properties - address is VFI value.", 15744 /* VFI_1 */ "VFI-1 Table (used for MAC-in-MAC and HG ports) - address is VFI value.", 15745 /* VFI_ATTRS_1 */ "VFI Properties - address is VFI value.", 15746 /* VFI_CTRL_PROFILE_1 */ "VFI Control Profile Table 1.", 15747 /* VFI_PROFILE */ "VFI profile table.", 15748 /* VFI_PROFILE_2 */ "VFI Profile Table 2. Contains sets of block masks that can be enabled depending on the packet type (UC/MC/BC).", 15749 /* VFP_HASH_FIELD_BMAP_TABLE_A */ "VFP_HASH_FIELD_BMAP_TABLE_A.", 15750 /* VFP_HASH_FIELD_BMAP_TABLE_B */ "VFP_HASH_FIELD_BMAP_TABLE_B.", 15751 /* VFP_POLICY_TABLE */ "POLICY TABLE FOR DETERMINING ACTIONS IN THE VFP", 15752 /* VFP_POLICY_TABLE_PIPE0 */ "Policy Table for determining actions in the VFP.", 15753 /* VFP_POLICY_TABLE_PIPE1 */ "Policy Table for determining actions in the VFP.", 15754 /* VFP_POLICY_TABLE_PIPE2 */ "Policy Table for determining actions in the VFP.", 15755 /* VFP_POLICY_TABLE_PIPE3 */ "Policy Table for determining actions in the VFP.", 15756 /* VFP_POLICY_TABLE_PIPE4 */ "Policy Table for determining actions in the VFP.", 15757 /* VFP_POLICY_TABLE_PIPE5 */ "Policy Table for determining actions in the VFP.", 15758 /* VFP_POLICY_TABLE_PIPE6 */ "Policy Table for determining actions in the VFP.", 15759 /* VFP_POLICY_TABLE_PIPE7 */ "Policy Table for determining actions in the VFP.", 15760 /* VFP_TCAM */ "TCAM FOR VFP", 15761 /* VFP_TCAM_PIPE0 */ "TCAM Table for Matching VFP Rules.", 15762 /* VFP_TCAM_PIPE1 */ "TCAM Table for Matching VFP Rules.", 15763 /* VFP_TCAM_PIPE2 */ "TCAM Table for Matching VFP Rules.", 15764 /* VFP_TCAM_PIPE3 */ "TCAM Table for Matching VFP Rules.", 15765 /* VFP_TCAM_PIPE4 */ "TCAM Table for Matching VFP Rules.", 15766 /* VFP_TCAM_PIPE5 */ "TCAM Table for Matching VFP Rules.", 15767 /* VFP_TCAM_PIPE6 */ "TCAM Table for Matching VFP Rules.", 15768 /* VFP_TCAM_PIPE7 */ "TCAM Table for Matching VFP Rules.", 15769 /* VLAN_2_TAB */ "Contains Controls assoc with the 4K VLANs.", 15770 /* VLAN_ATTRS_1 */ "Contains Controls assoc with the 4K VLANs.", 15771 /* VLAN_COS_MAP */ "index by vid", 15772 /* VLAN_MAC */ "Holds key & data for MAC-based VLAN substitution", 15773 /* VLAN_MAC_OVERFLOW */ "Holds key & data for MAC-based VLAN substitution. Overflow Table to populate entries if regular table is full. FeatureSpecific-Ethernet.", 15774 /* VLAN_MAC_SCRATCH */ "Single VLAN_MAC entry that is usable by software when shifting VLAN_MAC entries across the dual hash. Fully usable entry that is searched for every packet. Acts like a fully-associative 9th entry (for every bucket.)", 15775 /* VLAN_MPLS */ "Contains MPLS cntrls assoc with the 4K VLANs.", 15776 /* VLAN_OR_VFI_MAC_COUNT */ "Vlan MAC limit counters", 15777 /* VLAN_OR_VFI_MAC_LIMIT */ "Vlan MAC limit counters", 15778 /* VLAN_PROFILE_2 */ "Vlan Profile Table 2", 15779 /* VLAN_PROFILE_TAB */ "VLAN profile table", 15780 /* VLAN_PROTOCOL */ "Holds data for Protocol-based VLAN substitution. Just the VLAN_PROTOCOL RAM.", 15781 /* VLAN_PROTOCOL_DATA */ "Holds data for Protocol-based VLAN substitution", 15782 /* VLAN_SUBNET */ "TCAM for IP subnet based VLAN substitution", 15783 /* VLAN_SUBNET_DATA_ONLY */ "Holds data for IP Subnet-based VLAN substitution", 15784 /* VLAN_SUBNET_ONLY */ "TCAM for IP subnet based VLAN substitution", 15785 /* VLAN_TAB */ "Contains cntrls assoc with the 4K VLANs.", 15786 /* VLAN_XLATE */ "BCAM for VLAN trans of tagged pkts.", 15787 /* VLAN_XLATE_1 */ "", 15788 /* VLAN_XLATE_1_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15789 /* VLAN_XLATE_1_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15790 /* VLAN_XLATE_1_DOUBLE */ "Holds key & data for L2-VLAN, VIF, L2GRE_DIP and VXLAN_DIP based VLAN substitutions.", 15791 /* VLAN_XLATE_1_ECC */ "ECC Table.", 15792 /* VLAN_XLATE_1_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 15793 /* VLAN_XLATE_1_HIT_ONLY */ "VLAN_XLATE_1_HIT_ONLY, Single base entry views. FeatureSpecific-Ethernet.", 15794 /* VLAN_XLATE_1_KEY_ATTRIBUTES */ "Key Attributes Table.", 15795 /* VLAN_XLATE_1_LP */ "ECC Table.", 15796 /* VLAN_XLATE_1_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15797 /* VLAN_XLATE_1_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15798 /* VLAN_XLATE_1_SINGLE */ "Holds key & data for L2-VLAN, VIF, L2GRE_DIP and VXLAN_DIP based VLAN substitutions.", 15799 /* VLAN_XLATE_2_ACTION_TABLE_A */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15800 /* VLAN_XLATE_2_ACTION_TABLE_B */ "Robust Hash Action Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15801 /* VLAN_XLATE_2_DOUBLE */ "Holds key & data for L2-VLAN, VIF, L2GRE_DIP and VXLAN_DIP based VLAN substitutions.", 15802 /* VLAN_XLATE_2_ECC */ "ECC Table.", 15803 /* VLAN_XLATE_2_HASH_CONTROL */ "Hash Table control register (implemented as sbus table).", 15804 /* VLAN_XLATE_2_HIT_ONLY */ "VLAN_XLATE_2_HIT_ONLY, Double base entry views. FeatureSpecific-Ethernet.", 15805 /* VLAN_XLATE_2_KEY_ATTRIBUTES */ "Key Attributes Table.", 15806 /* VLAN_XLATE_2_LP */ "ECC Table.", 15807 /* VLAN_XLATE_2_REMAP_TABLE_A */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15808 /* VLAN_XLATE_2_REMAP_TABLE_B */ "Robust Hash Remap Table. Index[7:0] (0-255) to this table is derived from the hash table key.", 15809 /* VLAN_XLATE_2_SINGLE */ "Holds key & data for L2-VLAN, VIF, L2GRE_DIP and VXLAN_DIP based VLAN substitutions.", 15810 /* VLAN_XLATE_DATA_ONLY */ "Data SRAM for VLAN_XLATE BCAM.", 15811 /* VLAN_XLATE_ECC */ "ECC Table for VLAN_XLATE.", 15812 /* VLAN_XLATE_EXTD */ "VLAN_XLATE_2, Double base entry views. FeatureSpecific-Ethernet.", 15813 /* VLAN_XLATE_LP */ "VLAN_XLATE LP Control Table.", 15814 /* VLAN_XLATE_MASK */ "View of CAM and RAM, with the mask bits visible and readable and writable. FeatureSpecific-Ethernet", 15815 /* VLAN_XLATE_ONLY */ "BCAM for VLAN trans of tagged pkts.", 15816 /* VLAN_XLATE_OVERFLOW */ "This table is shared with the VLAN_MAC_OVERFLOW table. View of CAM and RAM for overflow table, which is used if entry can not be inserted in the Normal Vlan Xlate Table. FeatureSpecific-Ethernet.", 15817 /* VLAN_XLATE_SCRATCH */ "Single VLAN_XLATE entry that is usable by software.when shifting VLAN_XLATE entries across the dual hash. Fully usable entry that is searched for every packet. Acts like a fully-associative 9th entry (for every bucket.)", 15818 /* VOQ_COS_MAP */ "VOQ Mapping table.", 15819 /* VOQ_MOD_MAP */ "VOQ MODID Mapping table. index by dest_ModID[7:0]", 15820 /* VOQ_PORT_MAP */ "VOQ PORTID Mapping table. index by {voq_port_profile_index[1:0], Dest_Port[6:0]", 15821 /* VRF */ "VRF Properties - address is VRF value.", 15822 /* VRF_ATTRS_2 */ "VRF Properties - address is VRF value.", 15823 /* VRF_PROFILE */ "VRF profile table.", 15824 /* WLAN_SVP_TABLE */ "Holds fields specific to WLAN SVPs for second pass processing. FeatureSpecific-Wireless", 15825 /* XLPORT_WC_UCMEM_DATA */ "Warpcore External Memory Interface to program micro-controller memory", 15826 /* XPORT_EHG_RX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 15827 /* XPORT_EHG_RX_TUNNEL_MASK */ "Embedded Higig Rx tunnel data memory", 15828 /* XPORT_EHG_TX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 15829 /* XPORT_WC_UCMEM_DATA */ "Warpcore External Memory Interface to program micro-controller memory", 15830 /* XQPORT_EHG_RX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 15831 /* XQPORT_EHG_RX_TUNNEL_MASK */ "Embedded Higig Rx tunnel data memory", 15832 /* XQPORT_EHG_TX_TUNNEL_DATA */ "Embedded Higig Rx tunnel data memory", 15833 /* X_ARB_TDM_TABLE */ "MMU to X_EPIPE Arbiter TDM Table", 15834 /* Y_ARB_TDM_TABLE */ "MMU to X_EPIPE Arbiter TDM Table",