allformats_v.i (297348B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_v.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56860_A0) 16 { /* SOC_FORMAT_INT_VFI_SOURCEfmt */ 17 /* format VFI_SOURCEfmt */ 18 /* nFields */ 1, 19 /* *fields */ soc_VFI_SOURCEfmt_fields, 20 /* bits */ 3, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_56560_A0) 26 { /* SOC_FORMAT_INT_VFI_SOURCE_BCM56560_A0fmt */ 27 /* format VFI_SOURCEfmt */ 28 /* nFields */ 1, 29 /* *fields */ soc_VFI_SOURCE_BCM56560_A0fmt_fields, 30 /* bits */ 3, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_56560_B0) 36 { /* SOC_FORMAT_INT_VFI_SOURCE_BCM56560_B0fmt */ 37 /* format VFI_SOURCEfmt */ 38 /* nFields */ 1, 39 /* *fields */ soc_VFI_SOURCE_BCM56560_A0fmt_fields, 40 /* bits */ 3, 41 /* flags */ 0, 42 }, 43 #endif /* chips */ 44 45 #if defined(BCM_56670_A0) 46 { /* SOC_FORMAT_INT_VFI_SOURCE_BCM56670_A0fmt */ 47 /* format VFI_SOURCEfmt */ 48 /* nFields */ 1, 49 /* *fields */ soc_VFI_SOURCE_BCM56560_A0fmt_fields, 50 /* bits */ 3, 51 /* flags */ 0, 52 }, 53 #endif /* chips */ 54 55 #if defined(BCM_56670_B0) 56 { /* SOC_FORMAT_INT_VFI_SOURCE_BCM56670_B0fmt */ 57 /* format VFI_SOURCEfmt */ 58 /* nFields */ 1, 59 /* *fields */ soc_VFI_SOURCE_BCM56560_A0fmt_fields, 60 /* bits */ 3, 61 /* flags */ 0, 62 }, 63 #endif /* chips */ 64 65 #if defined(BCM_56514_A0) 66 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1fmt */ 67 /* format VFP_DOUBLE_WIDE_F1fmt */ 68 /* nFields */ 3, 69 /* *fields */ soc_VFP_DOUBLE_WIDE_F1fmt_fields, 70 /* bits */ 32, 71 /* flags */ 0, 72 }, 73 #endif /* chips */ 74 75 #if defined(BCM_56514_A0) 76 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3fmt */ 77 /* format VFP_DOUBLE_WIDE_F3fmt */ 78 /* nFields */ 2, 79 /* *fields */ soc_VFP_DOUBLE_WIDE_F3fmt_fields, 80 /* bits */ 24, 81 /* flags */ 0, 82 }, 83 #endif /* chips */ 84 85 #if defined(BCM_56142_A0) 86 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56142_A0fmt */ 87 /* format VFP_DOUBLE_WIDE_F1fmt */ 88 /* nFields */ 5, 89 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 90 /* bits */ 54, 91 /* flags */ 0, 92 }, 93 #endif /* chips */ 94 95 #if defined(BCM_56260_A0) 96 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56260_A0fmt */ 97 /* format VFP_DOUBLE_WIDE_F1fmt */ 98 /* nFields */ 6, 99 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56260_A0fmt_fields, 100 /* bits */ 74, 101 /* flags */ 0, 102 }, 103 #endif /* chips */ 104 105 #if defined(BCM_56260_B0) 106 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56260_B0fmt */ 107 /* format VFP_DOUBLE_WIDE_F1fmt */ 108 /* nFields */ 6, 109 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56260_A0fmt_fields, 110 /* bits */ 74, 111 /* flags */ 0, 112 }, 113 #endif /* chips */ 114 115 #if defined(BCM_56270_A0) 116 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56270_A0fmt */ 117 /* format VFP_DOUBLE_WIDE_F1fmt */ 118 /* nFields */ 6, 119 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56260_A0fmt_fields, 120 /* bits */ 74, 121 /* flags */ 0, 122 }, 123 #endif /* chips */ 124 125 #if defined(BCM_56334_A0) 126 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56334_A0fmt */ 127 /* format VFP_DOUBLE_WIDE_F1fmt */ 128 /* nFields */ 5, 129 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 130 /* bits */ 54, 131 /* flags */ 0, 132 }, 133 #endif /* chips */ 134 135 #if defined(BCM_56334_B0) 136 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56334_B0fmt */ 137 /* format VFP_DOUBLE_WIDE_F1fmt */ 138 /* nFields */ 5, 139 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 140 /* bits */ 54, 141 /* flags */ 0, 142 }, 143 #endif /* chips */ 144 145 #if defined(BCM_56340_A0) 146 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56340_A0fmt */ 147 /* format VFP_DOUBLE_WIDE_F1fmt */ 148 /* nFields */ 6, 149 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56640_A0fmt_fields, 150 /* bits */ 70, 151 /* flags */ 0, 152 }, 153 #endif /* chips */ 154 155 #if defined(BCM_56370_A0) 156 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56370_A0fmt */ 157 /* format VFP_DOUBLE_WIDE_F1fmt */ 158 /* nFields */ 5, 159 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56870_A0fmt_fields, 160 /* bits */ 70, 161 /* flags */ 0, 162 }, 163 #endif /* chips */ 164 165 #if defined(BCM_56440_A0) 166 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56440_A0fmt */ 167 /* format VFP_DOUBLE_WIDE_F1fmt */ 168 /* nFields */ 5, 169 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56840_A0fmt_fields, 170 /* bits */ 74, 171 /* flags */ 0, 172 }, 173 #endif /* chips */ 174 175 #if defined(BCM_56440_B0) 176 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56440_B0fmt */ 177 /* format VFP_DOUBLE_WIDE_F1fmt */ 178 /* nFields */ 5, 179 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56840_A0fmt_fields, 180 /* bits */ 74, 181 /* flags */ 0, 182 }, 183 #endif /* chips */ 184 185 #if defined(BCM_56450_A0) 186 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56450_A0fmt */ 187 /* format VFP_DOUBLE_WIDE_F1fmt */ 188 /* nFields */ 6, 189 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56450_A0fmt_fields, 190 /* bits */ 74, 191 /* flags */ 0, 192 }, 193 #endif /* chips */ 194 195 #if defined(BCM_56450_B0) 196 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56450_B0fmt */ 197 /* format VFP_DOUBLE_WIDE_F1fmt */ 198 /* nFields */ 6, 199 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56450_A0fmt_fields, 200 /* bits */ 74, 201 /* flags */ 0, 202 }, 203 #endif /* chips */ 204 205 #if defined(BCM_56450_B1) 206 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56450_B1fmt */ 207 /* format VFP_DOUBLE_WIDE_F1fmt */ 208 /* nFields */ 6, 209 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56450_A0fmt_fields, 210 /* bits */ 74, 211 /* flags */ 0, 212 }, 213 #endif /* chips */ 214 215 #if defined(BCM_56524_A0) 216 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56524_A0fmt */ 217 /* format VFP_DOUBLE_WIDE_F1fmt */ 218 /* nFields */ 5, 219 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 220 /* bits */ 54, 221 /* flags */ 0, 222 }, 223 #endif /* chips */ 224 225 #if defined(BCM_56524_B0) 226 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56524_B0fmt */ 227 /* format VFP_DOUBLE_WIDE_F1fmt */ 228 /* nFields */ 5, 229 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 230 /* bits */ 54, 231 /* flags */ 0, 232 }, 233 #endif /* chips */ 234 235 #if defined(BCM_56560_A0) 236 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56560_A0fmt */ 237 /* format VFP_DOUBLE_WIDE_F1fmt */ 238 /* nFields */ 6, 239 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56560_A0fmt_fields, 240 /* bits */ 72, 241 /* flags */ 0, 242 }, 243 #endif /* chips */ 244 245 #if defined(BCM_56560_B0) 246 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56560_B0fmt */ 247 /* format VFP_DOUBLE_WIDE_F1fmt */ 248 /* nFields */ 6, 249 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56560_A0fmt_fields, 250 /* bits */ 72, 251 /* flags */ 0, 252 }, 253 #endif /* chips */ 254 255 #if defined(BCM_56624_A0) 256 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt */ 257 /* format VFP_DOUBLE_WIDE_F1fmt */ 258 /* nFields */ 5, 259 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 260 /* bits */ 54, 261 /* flags */ 0, 262 }, 263 #endif /* chips */ 264 265 #if defined(BCM_56624_B0) 266 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56624_B0fmt */ 267 /* format VFP_DOUBLE_WIDE_F1fmt */ 268 /* nFields */ 5, 269 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 270 /* bits */ 54, 271 /* flags */ 0, 272 }, 273 #endif /* chips */ 274 275 #if defined(BCM_56634_A0) 276 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56634_A0fmt */ 277 /* format VFP_DOUBLE_WIDE_F1fmt */ 278 /* nFields */ 5, 279 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 280 /* bits */ 54, 281 /* flags */ 0, 282 }, 283 #endif /* chips */ 284 285 #if defined(BCM_56634_B0) 286 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56634_B0fmt */ 287 /* format VFP_DOUBLE_WIDE_F1fmt */ 288 /* nFields */ 5, 289 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 290 /* bits */ 54, 291 /* flags */ 0, 292 }, 293 #endif /* chips */ 294 295 #if defined(BCM_56640_A0) 296 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56640_A0fmt */ 297 /* format VFP_DOUBLE_WIDE_F1fmt */ 298 /* nFields */ 6, 299 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56640_A0fmt_fields, 300 /* bits */ 70, 301 /* flags */ 0, 302 }, 303 #endif /* chips */ 304 305 #if defined(BCM_56670_A0) 306 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56670_A0fmt */ 307 /* format VFP_DOUBLE_WIDE_F1fmt */ 308 /* nFields */ 6, 309 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56560_A0fmt_fields, 310 /* bits */ 72, 311 /* flags */ 0, 312 }, 313 #endif /* chips */ 314 315 #if defined(BCM_56670_B0) 316 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56670_B0fmt */ 317 /* format VFP_DOUBLE_WIDE_F1fmt */ 318 /* nFields */ 6, 319 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56560_A0fmt_fields, 320 /* bits */ 72, 321 /* flags */ 0, 322 }, 323 #endif /* chips */ 324 325 #if defined(BCM_56680_A0) 326 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56680_A0fmt */ 327 /* format VFP_DOUBLE_WIDE_F1fmt */ 328 /* nFields */ 5, 329 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 330 /* bits */ 54, 331 /* flags */ 0, 332 }, 333 #endif /* chips */ 334 335 #if defined(BCM_56680_B0) 336 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56680_B0fmt */ 337 /* format VFP_DOUBLE_WIDE_F1fmt */ 338 /* nFields */ 5, 339 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 340 /* bits */ 54, 341 /* flags */ 0, 342 }, 343 #endif /* chips */ 344 345 #if defined(BCM_56685_A0) 346 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56685_A0fmt */ 347 /* format VFP_DOUBLE_WIDE_F1fmt */ 348 /* nFields */ 5, 349 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 350 /* bits */ 54, 351 /* flags */ 0, 352 }, 353 #endif /* chips */ 354 355 #if defined(BCM_56685_B0) 356 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56685_B0fmt */ 357 /* format VFP_DOUBLE_WIDE_F1fmt */ 358 /* nFields */ 5, 359 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56624_A0fmt_fields, 360 /* bits */ 54, 361 /* flags */ 0, 362 }, 363 #endif /* chips */ 364 365 #if defined(BCM_56725_A0) 366 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56725_A0fmt */ 367 /* format VFP_DOUBLE_WIDE_F1fmt */ 368 /* nFields */ 5, 369 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56820_A0fmt_fields, 370 /* bits */ 50, 371 /* flags */ 0, 372 }, 373 #endif /* chips */ 374 375 #if defined(BCM_56770_A0) 376 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56770_A0fmt */ 377 /* format VFP_DOUBLE_WIDE_F1fmt */ 378 /* nFields */ 5, 379 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56870_A0fmt_fields, 380 /* bits */ 70, 381 /* flags */ 0, 382 }, 383 #endif /* chips */ 384 385 #if defined(BCM_56820_A0) 386 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56820_A0fmt */ 387 /* format VFP_DOUBLE_WIDE_F1fmt */ 388 /* nFields */ 5, 389 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56820_A0fmt_fields, 390 /* bits */ 50, 391 /* flags */ 0, 392 }, 393 #endif /* chips */ 394 395 #if defined(BCM_56840_A0) 396 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56840_A0fmt */ 397 /* format VFP_DOUBLE_WIDE_F1fmt */ 398 /* nFields */ 5, 399 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56840_A0fmt_fields, 400 /* bits */ 74, 401 /* flags */ 0, 402 }, 403 #endif /* chips */ 404 405 #if defined(BCM_56840_B0) 406 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56840_B0fmt */ 407 /* format VFP_DOUBLE_WIDE_F1fmt */ 408 /* nFields */ 5, 409 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56840_A0fmt_fields, 410 /* bits */ 74, 411 /* flags */ 0, 412 }, 413 #endif /* chips */ 414 415 #if defined(BCM_56850_A0) 416 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56850_A0fmt */ 417 /* format VFP_DOUBLE_WIDE_F1fmt */ 418 /* nFields */ 6, 419 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56850_A0fmt_fields, 420 /* bits */ 70, 421 /* flags */ 0, 422 }, 423 #endif /* chips */ 424 425 #if defined(BCM_56860_A0) 426 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56860_A0fmt */ 427 /* format VFP_DOUBLE_WIDE_F1fmt */ 428 /* nFields */ 6, 429 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56860_A0fmt_fields, 430 /* bits */ 72, 431 /* flags */ 0, 432 }, 433 #endif /* chips */ 434 435 #if defined(BCM_56870_A0) 436 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56870_A0fmt */ 437 /* format VFP_DOUBLE_WIDE_F1fmt */ 438 /* nFields */ 5, 439 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56870_A0fmt_fields, 440 /* bits */ 70, 441 /* flags */ 0, 442 }, 443 #endif /* chips */ 444 445 #if defined(BCM_56960_A0) 446 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56960_A0fmt */ 447 /* format VFP_DOUBLE_WIDE_F1fmt */ 448 /* nFields */ 6, 449 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56960_A0fmt_fields, 450 /* bits */ 70, 451 /* flags */ 0, 452 }, 453 #endif /* chips */ 454 455 #if defined(BCM_56965_A0) 456 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56965_A0fmt */ 457 /* format VFP_DOUBLE_WIDE_F1fmt */ 458 /* nFields */ 6, 459 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56960_A0fmt_fields, 460 /* bits */ 70, 461 /* flags */ 0, 462 }, 463 #endif /* chips */ 464 465 #if defined(BCM_56970_A0) 466 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56970_A0fmt */ 467 /* format VFP_DOUBLE_WIDE_F1fmt */ 468 /* nFields */ 6, 469 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56970_A0fmt_fields, 470 /* bits */ 70, 471 /* flags */ 0, 472 }, 473 #endif /* chips */ 474 475 #if defined(BCM_56980_A0) 476 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56980_A0fmt */ 477 /* format VFP_DOUBLE_WIDE_F1fmt */ 478 /* nFields */ 6, 479 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56970_A0fmt_fields, 480 /* bits */ 70, 481 /* flags */ 0, 482 }, 483 #endif /* chips */ 484 485 #if defined(BCM_56980_B0) 486 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F1_BCM56980_B0fmt */ 487 /* format VFP_DOUBLE_WIDE_F1fmt */ 488 /* nFields */ 6, 489 /* *fields */ soc_VFP_DOUBLE_WIDE_F1_BCM56970_A0fmt_fields, 490 /* bits */ 70, 491 /* flags */ 0, 492 }, 493 #endif /* chips */ 494 495 #if defined(BCM_56514_A0) 496 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0fmt */ 497 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 498 /* nFields */ 9, 499 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0fmt_fields, 500 /* bits */ 128, 501 /* flags */ 0, 502 }, 503 #endif /* chips */ 504 505 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 506 defined(BCM_56334_B0) || defined(BCM_56514_A0) || \ 507 defined(BCM_56680_B0) || defined(BCM_56685_B0) || \ 508 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 509 defined(BCM_56840_A0) || defined(BCM_56840_B0) 510 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1fmt */ 511 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 512 /* nFields */ 1, 513 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 514 /* bits */ 128, 515 /* flags */ 0, 516 }, 517 #endif /* chips */ 518 519 #if defined(BCM_56640_A0) 520 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2fmt */ 521 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 522 /* nFields */ 1, 523 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 524 /* bits */ 128, 525 /* flags */ 0, 526 }, 527 #endif /* chips */ 528 529 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 530 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_3fmt */ 531 /* format VFP_DOUBLE_WIDE_F2_3fmt */ 532 /* nFields */ 3, 533 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_3fmt_fields, 534 /* bits */ 128, 535 /* flags */ 0, 536 }, 537 #endif /* chips */ 538 539 #if defined(BCM_56142_A0) 540 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56142_A0fmt */ 541 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 542 /* nFields */ 9, 543 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 544 /* bits */ 128, 545 /* flags */ 0, 546 }, 547 #endif /* chips */ 548 549 #if defined(BCM_56260_A0) 550 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56260_A0fmt */ 551 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 552 /* nFields */ 9, 553 /* *fields */ soc_VFP_F2_0fmt_fields, 554 /* bits */ 128, 555 /* flags */ 0, 556 }, 557 #endif /* chips */ 558 559 #if defined(BCM_56260_B0) 560 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56260_B0fmt */ 561 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 562 /* nFields */ 9, 563 /* *fields */ soc_VFP_F2_0fmt_fields, 564 /* bits */ 128, 565 /* flags */ 0, 566 }, 567 #endif /* chips */ 568 569 #if defined(BCM_56270_A0) 570 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56270_A0fmt */ 571 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 572 /* nFields */ 9, 573 /* *fields */ soc_VFP_F2_0fmt_fields, 574 /* bits */ 128, 575 /* flags */ 0, 576 }, 577 #endif /* chips */ 578 579 #if defined(BCM_56334_A0) 580 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56334_A0fmt */ 581 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 582 /* nFields */ 9, 583 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 584 /* bits */ 128, 585 /* flags */ 0, 586 }, 587 #endif /* chips */ 588 589 #if defined(BCM_56334_B0) 590 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56334_B0fmt */ 591 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 592 /* nFields */ 9, 593 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 594 /* bits */ 128, 595 /* flags */ 0, 596 }, 597 #endif /* chips */ 598 599 #if defined(BCM_56340_A0) 600 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56340_A0fmt */ 601 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 602 /* nFields */ 9, 603 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 604 /* bits */ 128, 605 /* flags */ 0, 606 }, 607 #endif /* chips */ 608 609 #if defined(BCM_56370_A0) 610 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56370_A0fmt */ 611 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 612 /* nFields */ 9, 613 /* *fields */ soc_VFP_F2_0fmt_fields, 614 /* bits */ 128, 615 /* flags */ 0, 616 }, 617 #endif /* chips */ 618 619 #if defined(BCM_56440_A0) 620 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56440_A0fmt */ 621 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 622 /* nFields */ 9, 623 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 624 /* bits */ 128, 625 /* flags */ 0, 626 }, 627 #endif /* chips */ 628 629 #if defined(BCM_56440_B0) 630 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56440_B0fmt */ 631 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 632 /* nFields */ 9, 633 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 634 /* bits */ 128, 635 /* flags */ 0, 636 }, 637 #endif /* chips */ 638 639 #if defined(BCM_56450_A0) 640 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56450_A0fmt */ 641 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 642 /* nFields */ 9, 643 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 644 /* bits */ 128, 645 /* flags */ 0, 646 }, 647 #endif /* chips */ 648 649 #if defined(BCM_56450_B0) 650 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56450_B0fmt */ 651 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 652 /* nFields */ 9, 653 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 654 /* bits */ 128, 655 /* flags */ 0, 656 }, 657 #endif /* chips */ 658 659 #if defined(BCM_56450_B1) 660 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56450_B1fmt */ 661 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 662 /* nFields */ 9, 663 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 664 /* bits */ 128, 665 /* flags */ 0, 666 }, 667 #endif /* chips */ 668 669 #if defined(BCM_56524_A0) 670 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56524_A0fmt */ 671 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 672 /* nFields */ 9, 673 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 674 /* bits */ 128, 675 /* flags */ 0, 676 }, 677 #endif /* chips */ 678 679 #if defined(BCM_56524_B0) 680 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56524_B0fmt */ 681 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 682 /* nFields */ 9, 683 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 684 /* bits */ 128, 685 /* flags */ 0, 686 }, 687 #endif /* chips */ 688 689 #if defined(BCM_56560_A0) 690 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56560_A0fmt */ 691 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 692 /* nFields */ 9, 693 /* *fields */ soc_VFP_F2_0fmt_fields, 694 /* bits */ 128, 695 /* flags */ 0, 696 }, 697 #endif /* chips */ 698 699 #if defined(BCM_56560_B0) 700 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56560_B0fmt */ 701 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 702 /* nFields */ 9, 703 /* *fields */ soc_VFP_F2_0fmt_fields, 704 /* bits */ 128, 705 /* flags */ 0, 706 }, 707 #endif /* chips */ 708 709 #if defined(BCM_56624_A0) 710 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt */ 711 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 712 /* nFields */ 9, 713 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 714 /* bits */ 128, 715 /* flags */ 0, 716 }, 717 #endif /* chips */ 718 719 #if defined(BCM_56624_B0) 720 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56624_B0fmt */ 721 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 722 /* nFields */ 9, 723 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 724 /* bits */ 128, 725 /* flags */ 0, 726 }, 727 #endif /* chips */ 728 729 #if defined(BCM_56634_A0) 730 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt */ 731 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 732 /* nFields */ 9, 733 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 734 /* bits */ 128, 735 /* flags */ 0, 736 }, 737 #endif /* chips */ 738 739 #if defined(BCM_56634_B0) 740 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56634_B0fmt */ 741 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 742 /* nFields */ 9, 743 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 744 /* bits */ 128, 745 /* flags */ 0, 746 }, 747 #endif /* chips */ 748 749 #if defined(BCM_56640_A0) 750 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt */ 751 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 752 /* nFields */ 9, 753 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 754 /* bits */ 128, 755 /* flags */ 0, 756 }, 757 #endif /* chips */ 758 759 #if defined(BCM_56670_A0) 760 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56670_A0fmt */ 761 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 762 /* nFields */ 9, 763 /* *fields */ soc_VFP_F2_0fmt_fields, 764 /* bits */ 128, 765 /* flags */ 0, 766 }, 767 #endif /* chips */ 768 769 #if defined(BCM_56670_B0) 770 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56670_B0fmt */ 771 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 772 /* nFields */ 9, 773 /* *fields */ soc_VFP_F2_0fmt_fields, 774 /* bits */ 128, 775 /* flags */ 0, 776 }, 777 #endif /* chips */ 778 779 #if defined(BCM_56680_A0) 780 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56680_A0fmt */ 781 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 782 /* nFields */ 9, 783 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 784 /* bits */ 128, 785 /* flags */ 0, 786 }, 787 #endif /* chips */ 788 789 #if defined(BCM_56680_B0) 790 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56680_B0fmt */ 791 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 792 /* nFields */ 9, 793 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 794 /* bits */ 128, 795 /* flags */ 0, 796 }, 797 #endif /* chips */ 798 799 #if defined(BCM_56685_A0) 800 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56685_A0fmt */ 801 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 802 /* nFields */ 9, 803 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 804 /* bits */ 128, 805 /* flags */ 0, 806 }, 807 #endif /* chips */ 808 809 #if defined(BCM_56685_B0) 810 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56685_B0fmt */ 811 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 812 /* nFields */ 9, 813 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 814 /* bits */ 128, 815 /* flags */ 0, 816 }, 817 #endif /* chips */ 818 819 #if defined(BCM_56725_A0) 820 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56725_A0fmt */ 821 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 822 /* nFields */ 9, 823 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 824 /* bits */ 128, 825 /* flags */ 0, 826 }, 827 #endif /* chips */ 828 829 #if defined(BCM_56770_A0) 830 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56770_A0fmt */ 831 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 832 /* nFields */ 9, 833 /* *fields */ soc_VFP_F2_0fmt_fields, 834 /* bits */ 128, 835 /* flags */ 0, 836 }, 837 #endif /* chips */ 838 839 #if defined(BCM_56820_A0) 840 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56820_A0fmt */ 841 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 842 /* nFields */ 9, 843 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 844 /* bits */ 128, 845 /* flags */ 0, 846 }, 847 #endif /* chips */ 848 849 #if defined(BCM_56840_A0) 850 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56840_A0fmt */ 851 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 852 /* nFields */ 9, 853 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 854 /* bits */ 128, 855 /* flags */ 0, 856 }, 857 #endif /* chips */ 858 859 #if defined(BCM_56840_B0) 860 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56840_B0fmt */ 861 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 862 /* nFields */ 9, 863 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 864 /* bits */ 128, 865 /* flags */ 0, 866 }, 867 #endif /* chips */ 868 869 #if defined(BCM_56850_A0) 870 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56850_A0fmt */ 871 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 872 /* nFields */ 9, 873 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 874 /* bits */ 128, 875 /* flags */ 0, 876 }, 877 #endif /* chips */ 878 879 #if defined(BCM_56860_A0) 880 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56860_A0fmt */ 881 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 882 /* nFields */ 11, 883 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56860_A0fmt_fields, 884 /* bits */ 128, 885 /* flags */ 0, 886 }, 887 #endif /* chips */ 888 889 #if defined(BCM_56870_A0) 890 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56870_A0fmt */ 891 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 892 /* nFields */ 9, 893 /* *fields */ soc_VFP_F2_0fmt_fields, 894 /* bits */ 128, 895 /* flags */ 0, 896 }, 897 #endif /* chips */ 898 899 #if defined(BCM_56960_A0) 900 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56960_A0fmt */ 901 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 902 /* nFields */ 9, 903 /* *fields */ soc_VFP_F2_0fmt_fields, 904 /* bits */ 128, 905 /* flags */ 0, 906 }, 907 #endif /* chips */ 908 909 #if defined(BCM_56965_A0) 910 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56965_A0fmt */ 911 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 912 /* nFields */ 9, 913 /* *fields */ soc_VFP_F2_0fmt_fields, 914 /* bits */ 128, 915 /* flags */ 0, 916 }, 917 #endif /* chips */ 918 919 #if defined(BCM_56970_A0) 920 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56970_A0fmt */ 921 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 922 /* nFields */ 9, 923 /* *fields */ soc_VFP_F2_0fmt_fields, 924 /* bits */ 128, 925 /* flags */ 0, 926 }, 927 #endif /* chips */ 928 929 #if defined(BCM_56980_A0) 930 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56980_A0fmt */ 931 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 932 /* nFields */ 9, 933 /* *fields */ soc_VFP_F2_0fmt_fields, 934 /* bits */ 128, 935 /* flags */ 0, 936 }, 937 #endif /* chips */ 938 939 #if defined(BCM_56980_B0) 940 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_0_BCM56980_B0fmt */ 941 /* format VFP_DOUBLE_WIDE_F2_0fmt */ 942 /* nFields */ 9, 943 /* *fields */ soc_VFP_F2_0fmt_fields, 944 /* bits */ 128, 945 /* flags */ 0, 946 }, 947 #endif /* chips */ 948 949 #if defined(BCM_56260_A0) 950 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56260_A0fmt */ 951 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 952 /* nFields */ 1, 953 /* *fields */ soc_VFP_F2_1fmt_fields, 954 /* bits */ 128, 955 /* flags */ 0, 956 }, 957 #endif /* chips */ 958 959 #if defined(BCM_56260_B0) 960 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56260_B0fmt */ 961 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 962 /* nFields */ 1, 963 /* *fields */ soc_VFP_F2_1fmt_fields, 964 /* bits */ 128, 965 /* flags */ 0, 966 }, 967 #endif /* chips */ 968 969 #if defined(BCM_56270_A0) 970 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56270_A0fmt */ 971 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 972 /* nFields */ 1, 973 /* *fields */ soc_VFP_F2_1fmt_fields, 974 /* bits */ 128, 975 /* flags */ 0, 976 }, 977 #endif /* chips */ 978 979 #if defined(BCM_56340_A0) 980 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56340_A0fmt */ 981 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 982 /* nFields */ 1, 983 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 984 /* bits */ 128, 985 /* flags */ 0, 986 }, 987 #endif /* chips */ 988 989 #if defined(BCM_56370_A0) 990 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56370_A0fmt */ 991 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 992 /* nFields */ 1, 993 /* *fields */ soc_VFP_F2_1fmt_fields, 994 /* bits */ 128, 995 /* flags */ 0, 996 }, 997 #endif /* chips */ 998 999 #if defined(BCM_56440_A0) 1000 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56440_A0fmt */ 1001 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1002 /* nFields */ 1, 1003 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1004 /* bits */ 128, 1005 /* flags */ 0, 1006 }, 1007 #endif /* chips */ 1008 1009 #if defined(BCM_56440_B0) 1010 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56440_B0fmt */ 1011 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1012 /* nFields */ 1, 1013 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1014 /* bits */ 128, 1015 /* flags */ 0, 1016 }, 1017 #endif /* chips */ 1018 1019 #if defined(BCM_56450_A0) 1020 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56450_A0fmt */ 1021 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1022 /* nFields */ 1, 1023 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 1024 /* bits */ 128, 1025 /* flags */ 0, 1026 }, 1027 #endif /* chips */ 1028 1029 #if defined(BCM_56450_B0) 1030 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56450_B0fmt */ 1031 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1032 /* nFields */ 1, 1033 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 1034 /* bits */ 128, 1035 /* flags */ 0, 1036 }, 1037 #endif /* chips */ 1038 1039 #if defined(BCM_56450_B1) 1040 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56450_B1fmt */ 1041 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1042 /* nFields */ 1, 1043 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 1044 /* bits */ 128, 1045 /* flags */ 0, 1046 }, 1047 #endif /* chips */ 1048 1049 #if defined(BCM_56524_A0) 1050 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56524_A0fmt */ 1051 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1052 /* nFields */ 1, 1053 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1054 /* bits */ 128, 1055 /* flags */ 0, 1056 }, 1057 #endif /* chips */ 1058 1059 #if defined(BCM_56524_B0) 1060 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56524_B0fmt */ 1061 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1062 /* nFields */ 1, 1063 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1064 /* bits */ 128, 1065 /* flags */ 0, 1066 }, 1067 #endif /* chips */ 1068 1069 #if defined(BCM_56560_A0) 1070 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56560_A0fmt */ 1071 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1072 /* nFields */ 1, 1073 /* *fields */ soc_VFP_F2_1fmt_fields, 1074 /* bits */ 128, 1075 /* flags */ 0, 1076 }, 1077 #endif /* chips */ 1078 1079 #if defined(BCM_56560_B0) 1080 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56560_B0fmt */ 1081 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1082 /* nFields */ 1, 1083 /* *fields */ soc_VFP_F2_1fmt_fields, 1084 /* bits */ 128, 1085 /* flags */ 0, 1086 }, 1087 #endif /* chips */ 1088 1089 #if defined(BCM_56624_A0) 1090 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56624_A0fmt */ 1091 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1092 /* nFields */ 1, 1093 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1094 /* bits */ 128, 1095 /* flags */ 0, 1096 }, 1097 #endif /* chips */ 1098 1099 #if defined(BCM_56624_B0) 1100 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56624_B0fmt */ 1101 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1102 /* nFields */ 1, 1103 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1104 /* bits */ 128, 1105 /* flags */ 0, 1106 }, 1107 #endif /* chips */ 1108 1109 #if defined(BCM_56634_A0) 1110 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56634_A0fmt */ 1111 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1112 /* nFields */ 1, 1113 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1114 /* bits */ 128, 1115 /* flags */ 0, 1116 }, 1117 #endif /* chips */ 1118 1119 #if defined(BCM_56634_B0) 1120 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56634_B0fmt */ 1121 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1122 /* nFields */ 1, 1123 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1124 /* bits */ 128, 1125 /* flags */ 0, 1126 }, 1127 #endif /* chips */ 1128 1129 #if defined(BCM_56640_A0) 1130 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt */ 1131 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1132 /* nFields */ 1, 1133 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 1134 /* bits */ 128, 1135 /* flags */ 0, 1136 }, 1137 #endif /* chips */ 1138 1139 #if defined(BCM_56670_A0) 1140 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56670_A0fmt */ 1141 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1142 /* nFields */ 1, 1143 /* *fields */ soc_VFP_F2_1fmt_fields, 1144 /* bits */ 128, 1145 /* flags */ 0, 1146 }, 1147 #endif /* chips */ 1148 1149 #if defined(BCM_56670_B0) 1150 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56670_B0fmt */ 1151 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1152 /* nFields */ 1, 1153 /* *fields */ soc_VFP_F2_1fmt_fields, 1154 /* bits */ 128, 1155 /* flags */ 0, 1156 }, 1157 #endif /* chips */ 1158 1159 #if defined(BCM_56680_A0) 1160 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56680_A0fmt */ 1161 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1162 /* nFields */ 1, 1163 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1164 /* bits */ 128, 1165 /* flags */ 0, 1166 }, 1167 #endif /* chips */ 1168 1169 #if defined(BCM_56685_A0) 1170 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56685_A0fmt */ 1171 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1172 /* nFields */ 1, 1173 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 1174 /* bits */ 128, 1175 /* flags */ 0, 1176 }, 1177 #endif /* chips */ 1178 1179 #if defined(BCM_56770_A0) 1180 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56770_A0fmt */ 1181 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1182 /* nFields */ 1, 1183 /* *fields */ soc_VFP_F2_1fmt_fields, 1184 /* bits */ 128, 1185 /* flags */ 0, 1186 }, 1187 #endif /* chips */ 1188 1189 #if defined(BCM_56850_A0) 1190 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56850_A0fmt */ 1191 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1192 /* nFields */ 1, 1193 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 1194 /* bits */ 128, 1195 /* flags */ 0, 1196 }, 1197 #endif /* chips */ 1198 1199 #if defined(BCM_56860_A0) 1200 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56860_A0fmt */ 1201 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1202 /* nFields */ 1, 1203 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 1204 /* bits */ 128, 1205 /* flags */ 0, 1206 }, 1207 #endif /* chips */ 1208 1209 #if defined(BCM_56870_A0) 1210 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56870_A0fmt */ 1211 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1212 /* nFields */ 1, 1213 /* *fields */ soc_VFP_F2_1fmt_fields, 1214 /* bits */ 128, 1215 /* flags */ 0, 1216 }, 1217 #endif /* chips */ 1218 1219 #if defined(BCM_56960_A0) 1220 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56960_A0fmt */ 1221 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1222 /* nFields */ 1, 1223 /* *fields */ soc_VFP_F2_1fmt_fields, 1224 /* bits */ 128, 1225 /* flags */ 0, 1226 }, 1227 #endif /* chips */ 1228 1229 #if defined(BCM_56965_A0) 1230 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56965_A0fmt */ 1231 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1232 /* nFields */ 1, 1233 /* *fields */ soc_VFP_F2_1fmt_fields, 1234 /* bits */ 128, 1235 /* flags */ 0, 1236 }, 1237 #endif /* chips */ 1238 1239 #if defined(BCM_56970_A0) 1240 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56970_A0fmt */ 1241 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1242 /* nFields */ 1, 1243 /* *fields */ soc_VFP_F2_1fmt_fields, 1244 /* bits */ 128, 1245 /* flags */ 0, 1246 }, 1247 #endif /* chips */ 1248 1249 #if defined(BCM_56980_A0) 1250 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56980_A0fmt */ 1251 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1252 /* nFields */ 1, 1253 /* *fields */ soc_VFP_F2_1fmt_fields, 1254 /* bits */ 128, 1255 /* flags */ 0, 1256 }, 1257 #endif /* chips */ 1258 1259 #if defined(BCM_56980_B0) 1260 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_1_BCM56980_B0fmt */ 1261 /* format VFP_DOUBLE_WIDE_F2_1fmt */ 1262 /* nFields */ 1, 1263 /* *fields */ soc_VFP_F2_1fmt_fields, 1264 /* bits */ 128, 1265 /* flags */ 0, 1266 }, 1267 #endif /* chips */ 1268 1269 #if defined(BCM_56260_A0) 1270 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56260_A0fmt */ 1271 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1272 /* nFields */ 1, 1273 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1274 /* bits */ 128, 1275 /* flags */ 0, 1276 }, 1277 #endif /* chips */ 1278 1279 #if defined(BCM_56260_B0) 1280 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56260_B0fmt */ 1281 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1282 /* nFields */ 1, 1283 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1284 /* bits */ 128, 1285 /* flags */ 0, 1286 }, 1287 #endif /* chips */ 1288 1289 #if defined(BCM_56270_A0) 1290 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56270_A0fmt */ 1291 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1292 /* nFields */ 1, 1293 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1294 /* bits */ 128, 1295 /* flags */ 0, 1296 }, 1297 #endif /* chips */ 1298 1299 #if defined(BCM_56340_A0) 1300 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56340_A0fmt */ 1301 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1302 /* nFields */ 1, 1303 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 1304 /* bits */ 128, 1305 /* flags */ 0, 1306 }, 1307 #endif /* chips */ 1308 1309 #if defined(BCM_56370_A0) 1310 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56370_A0fmt */ 1311 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1312 /* nFields */ 1, 1313 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1314 /* bits */ 128, 1315 /* flags */ 0, 1316 }, 1317 #endif /* chips */ 1318 1319 #if defined(BCM_56450_A0) 1320 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56450_A0fmt */ 1321 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1322 /* nFields */ 1, 1323 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 1324 /* bits */ 128, 1325 /* flags */ 0, 1326 }, 1327 #endif /* chips */ 1328 1329 #if defined(BCM_56450_B0) 1330 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56450_B0fmt */ 1331 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1332 /* nFields */ 1, 1333 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 1334 /* bits */ 128, 1335 /* flags */ 0, 1336 }, 1337 #endif /* chips */ 1338 1339 #if defined(BCM_56450_B1) 1340 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56450_B1fmt */ 1341 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1342 /* nFields */ 1, 1343 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 1344 /* bits */ 128, 1345 /* flags */ 0, 1346 }, 1347 #endif /* chips */ 1348 1349 #if defined(BCM_56560_A0) 1350 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56560_A0fmt */ 1351 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1352 /* nFields */ 1, 1353 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1354 /* bits */ 128, 1355 /* flags */ 0, 1356 }, 1357 #endif /* chips */ 1358 1359 #if defined(BCM_56560_B0) 1360 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56560_B0fmt */ 1361 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1362 /* nFields */ 1, 1363 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1364 /* bits */ 128, 1365 /* flags */ 0, 1366 }, 1367 #endif /* chips */ 1368 1369 #if defined(BCM_56670_A0) 1370 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56670_A0fmt */ 1371 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1372 /* nFields */ 1, 1373 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1374 /* bits */ 128, 1375 /* flags */ 0, 1376 }, 1377 #endif /* chips */ 1378 1379 #if defined(BCM_56670_B0) 1380 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56670_B0fmt */ 1381 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1382 /* nFields */ 1, 1383 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1384 /* bits */ 128, 1385 /* flags */ 0, 1386 }, 1387 #endif /* chips */ 1388 1389 #if defined(BCM_56770_A0) 1390 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56770_A0fmt */ 1391 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1392 /* nFields */ 1, 1393 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1394 /* bits */ 128, 1395 /* flags */ 0, 1396 }, 1397 #endif /* chips */ 1398 1399 #if defined(BCM_56850_A0) 1400 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56850_A0fmt */ 1401 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1402 /* nFields */ 1, 1403 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 1404 /* bits */ 128, 1405 /* flags */ 0, 1406 }, 1407 #endif /* chips */ 1408 1409 #if defined(BCM_56860_A0) 1410 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56860_A0fmt */ 1411 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1412 /* nFields */ 1, 1413 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 1414 /* bits */ 128, 1415 /* flags */ 0, 1416 }, 1417 #endif /* chips */ 1418 1419 #if defined(BCM_56870_A0) 1420 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56870_A0fmt */ 1421 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1422 /* nFields */ 1, 1423 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1424 /* bits */ 128, 1425 /* flags */ 0, 1426 }, 1427 #endif /* chips */ 1428 1429 #if defined(BCM_56960_A0) 1430 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56960_A0fmt */ 1431 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1432 /* nFields */ 1, 1433 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1434 /* bits */ 128, 1435 /* flags */ 0, 1436 }, 1437 #endif /* chips */ 1438 1439 #if defined(BCM_56965_A0) 1440 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56965_A0fmt */ 1441 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1442 /* nFields */ 1, 1443 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1444 /* bits */ 128, 1445 /* flags */ 0, 1446 }, 1447 #endif /* chips */ 1448 1449 #if defined(BCM_56970_A0) 1450 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56970_A0fmt */ 1451 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1452 /* nFields */ 1, 1453 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1454 /* bits */ 128, 1455 /* flags */ 0, 1456 }, 1457 #endif /* chips */ 1458 1459 #if defined(BCM_56980_A0) 1460 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56980_A0fmt */ 1461 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1462 /* nFields */ 1, 1463 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1464 /* bits */ 128, 1465 /* flags */ 0, 1466 }, 1467 #endif /* chips */ 1468 1469 #if defined(BCM_56980_B0) 1470 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F2_2_BCM56980_B0fmt */ 1471 /* format VFP_DOUBLE_WIDE_F2_2fmt */ 1472 /* nFields */ 1, 1473 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 1474 /* bits */ 128, 1475 /* flags */ 0, 1476 }, 1477 #endif /* chips */ 1478 1479 #if defined(BCM_56142_A0) 1480 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56142_A0fmt */ 1481 /* format VFP_DOUBLE_WIDE_F3fmt */ 1482 /* nFields */ 5, 1483 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1484 /* bits */ 32, 1485 /* flags */ 0, 1486 }, 1487 #endif /* chips */ 1488 1489 #if defined(BCM_56260_A0) 1490 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56260_A0fmt */ 1491 /* format VFP_DOUBLE_WIDE_F3fmt */ 1492 /* nFields */ 5, 1493 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56260_A0fmt_fields, 1494 /* bits */ 32, 1495 /* flags */ 0, 1496 }, 1497 #endif /* chips */ 1498 1499 #if defined(BCM_56260_B0) 1500 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56260_B0fmt */ 1501 /* format VFP_DOUBLE_WIDE_F3fmt */ 1502 /* nFields */ 5, 1503 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56260_A0fmt_fields, 1504 /* bits */ 32, 1505 /* flags */ 0, 1506 }, 1507 #endif /* chips */ 1508 1509 #if defined(BCM_56270_A0) 1510 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56270_A0fmt */ 1511 /* format VFP_DOUBLE_WIDE_F3fmt */ 1512 /* nFields */ 5, 1513 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56260_A0fmt_fields, 1514 /* bits */ 32, 1515 /* flags */ 0, 1516 }, 1517 #endif /* chips */ 1518 1519 #if defined(BCM_56334_A0) 1520 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56334_A0fmt */ 1521 /* format VFP_DOUBLE_WIDE_F3fmt */ 1522 /* nFields */ 5, 1523 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1524 /* bits */ 32, 1525 /* flags */ 0, 1526 }, 1527 #endif /* chips */ 1528 1529 #if defined(BCM_56334_B0) 1530 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56334_B0fmt */ 1531 /* format VFP_DOUBLE_WIDE_F3fmt */ 1532 /* nFields */ 5, 1533 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1534 /* bits */ 32, 1535 /* flags */ 0, 1536 }, 1537 #endif /* chips */ 1538 1539 #if defined(BCM_56340_A0) 1540 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56340_A0fmt */ 1541 /* format VFP_DOUBLE_WIDE_F3fmt */ 1542 /* nFields */ 6, 1543 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56640_A0fmt_fields, 1544 /* bits */ 36, 1545 /* flags */ 0, 1546 }, 1547 #endif /* chips */ 1548 1549 #if defined(BCM_56370_A0) 1550 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56370_A0fmt */ 1551 /* format VFP_DOUBLE_WIDE_F3fmt */ 1552 /* nFields */ 6, 1553 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1554 /* bits */ 36, 1555 /* flags */ 0, 1556 }, 1557 #endif /* chips */ 1558 1559 #if defined(BCM_56440_A0) 1560 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56440_A0fmt */ 1561 /* format VFP_DOUBLE_WIDE_F3fmt */ 1562 /* nFields */ 5, 1563 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1564 /* bits */ 32, 1565 /* flags */ 0, 1566 }, 1567 #endif /* chips */ 1568 1569 #if defined(BCM_56440_B0) 1570 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56440_B0fmt */ 1571 /* format VFP_DOUBLE_WIDE_F3fmt */ 1572 /* nFields */ 5, 1573 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1574 /* bits */ 32, 1575 /* flags */ 0, 1576 }, 1577 #endif /* chips */ 1578 1579 #if defined(BCM_56450_A0) 1580 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56450_A0fmt */ 1581 /* format VFP_DOUBLE_WIDE_F3fmt */ 1582 /* nFields */ 5, 1583 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56450_A0fmt_fields, 1584 /* bits */ 32, 1585 /* flags */ 0, 1586 }, 1587 #endif /* chips */ 1588 1589 #if defined(BCM_56450_B0) 1590 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56450_B0fmt */ 1591 /* format VFP_DOUBLE_WIDE_F3fmt */ 1592 /* nFields */ 5, 1593 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56450_A0fmt_fields, 1594 /* bits */ 32, 1595 /* flags */ 0, 1596 }, 1597 #endif /* chips */ 1598 1599 #if defined(BCM_56450_B1) 1600 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56450_B1fmt */ 1601 /* format VFP_DOUBLE_WIDE_F3fmt */ 1602 /* nFields */ 5, 1603 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56450_A0fmt_fields, 1604 /* bits */ 32, 1605 /* flags */ 0, 1606 }, 1607 #endif /* chips */ 1608 1609 #if defined(BCM_56524_A0) 1610 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56524_A0fmt */ 1611 /* format VFP_DOUBLE_WIDE_F3fmt */ 1612 /* nFields */ 5, 1613 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1614 /* bits */ 32, 1615 /* flags */ 0, 1616 }, 1617 #endif /* chips */ 1618 1619 #if defined(BCM_56524_B0) 1620 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56524_B0fmt */ 1621 /* format VFP_DOUBLE_WIDE_F3fmt */ 1622 /* nFields */ 5, 1623 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1624 /* bits */ 32, 1625 /* flags */ 0, 1626 }, 1627 #endif /* chips */ 1628 1629 #if defined(BCM_56560_A0) 1630 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56560_A0fmt */ 1631 /* format VFP_DOUBLE_WIDE_F3fmt */ 1632 /* nFields */ 6, 1633 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1634 /* bits */ 36, 1635 /* flags */ 0, 1636 }, 1637 #endif /* chips */ 1638 1639 #if defined(BCM_56560_B0) 1640 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56560_B0fmt */ 1641 /* format VFP_DOUBLE_WIDE_F3fmt */ 1642 /* nFields */ 6, 1643 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1644 /* bits */ 36, 1645 /* flags */ 0, 1646 }, 1647 #endif /* chips */ 1648 1649 #if defined(BCM_56624_A0) 1650 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt */ 1651 /* format VFP_DOUBLE_WIDE_F3fmt */ 1652 /* nFields */ 5, 1653 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1654 /* bits */ 32, 1655 /* flags */ 0, 1656 }, 1657 #endif /* chips */ 1658 1659 #if defined(BCM_56624_B0) 1660 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56624_B0fmt */ 1661 /* format VFP_DOUBLE_WIDE_F3fmt */ 1662 /* nFields */ 5, 1663 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1664 /* bits */ 32, 1665 /* flags */ 0, 1666 }, 1667 #endif /* chips */ 1668 1669 #if defined(BCM_56634_A0) 1670 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56634_A0fmt */ 1671 /* format VFP_DOUBLE_WIDE_F3fmt */ 1672 /* nFields */ 5, 1673 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1674 /* bits */ 32, 1675 /* flags */ 0, 1676 }, 1677 #endif /* chips */ 1678 1679 #if defined(BCM_56634_B0) 1680 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56634_B0fmt */ 1681 /* format VFP_DOUBLE_WIDE_F3fmt */ 1682 /* nFields */ 5, 1683 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1684 /* bits */ 32, 1685 /* flags */ 0, 1686 }, 1687 #endif /* chips */ 1688 1689 #if defined(BCM_56640_A0) 1690 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56640_A0fmt */ 1691 /* format VFP_DOUBLE_WIDE_F3fmt */ 1692 /* nFields */ 6, 1693 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56640_A0fmt_fields, 1694 /* bits */ 36, 1695 /* flags */ 0, 1696 }, 1697 #endif /* chips */ 1698 1699 #if defined(BCM_56670_A0) 1700 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56670_A0fmt */ 1701 /* format VFP_DOUBLE_WIDE_F3fmt */ 1702 /* nFields */ 6, 1703 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1704 /* bits */ 36, 1705 /* flags */ 0, 1706 }, 1707 #endif /* chips */ 1708 1709 #if defined(BCM_56670_B0) 1710 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56670_B0fmt */ 1711 /* format VFP_DOUBLE_WIDE_F3fmt */ 1712 /* nFields */ 6, 1713 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1714 /* bits */ 36, 1715 /* flags */ 0, 1716 }, 1717 #endif /* chips */ 1718 1719 #if defined(BCM_56680_A0) 1720 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56680_A0fmt */ 1721 /* format VFP_DOUBLE_WIDE_F3fmt */ 1722 /* nFields */ 5, 1723 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1724 /* bits */ 32, 1725 /* flags */ 0, 1726 }, 1727 #endif /* chips */ 1728 1729 #if defined(BCM_56680_B0) 1730 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56680_B0fmt */ 1731 /* format VFP_DOUBLE_WIDE_F3fmt */ 1732 /* nFields */ 5, 1733 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1734 /* bits */ 32, 1735 /* flags */ 0, 1736 }, 1737 #endif /* chips */ 1738 1739 #if defined(BCM_56685_A0) 1740 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56685_A0fmt */ 1741 /* format VFP_DOUBLE_WIDE_F3fmt */ 1742 /* nFields */ 5, 1743 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1744 /* bits */ 32, 1745 /* flags */ 0, 1746 }, 1747 #endif /* chips */ 1748 1749 #if defined(BCM_56685_B0) 1750 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56685_B0fmt */ 1751 /* format VFP_DOUBLE_WIDE_F3fmt */ 1752 /* nFields */ 5, 1753 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1754 /* bits */ 32, 1755 /* flags */ 0, 1756 }, 1757 #endif /* chips */ 1758 1759 #if defined(BCM_56725_A0) 1760 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56725_A0fmt */ 1761 /* format VFP_DOUBLE_WIDE_F3fmt */ 1762 /* nFields */ 5, 1763 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1764 /* bits */ 32, 1765 /* flags */ 0, 1766 }, 1767 #endif /* chips */ 1768 1769 #if defined(BCM_56770_A0) 1770 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56770_A0fmt */ 1771 /* format VFP_DOUBLE_WIDE_F3fmt */ 1772 /* nFields */ 6, 1773 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1774 /* bits */ 36, 1775 /* flags */ 0, 1776 }, 1777 #endif /* chips */ 1778 1779 #if defined(BCM_56820_A0) 1780 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56820_A0fmt */ 1781 /* format VFP_DOUBLE_WIDE_F3fmt */ 1782 /* nFields */ 5, 1783 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1784 /* bits */ 32, 1785 /* flags */ 0, 1786 }, 1787 #endif /* chips */ 1788 1789 #if defined(BCM_56840_A0) 1790 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56840_A0fmt */ 1791 /* format VFP_DOUBLE_WIDE_F3fmt */ 1792 /* nFields */ 5, 1793 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1794 /* bits */ 32, 1795 /* flags */ 0, 1796 }, 1797 #endif /* chips */ 1798 1799 #if defined(BCM_56840_B0) 1800 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56840_B0fmt */ 1801 /* format VFP_DOUBLE_WIDE_F3fmt */ 1802 /* nFields */ 5, 1803 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56624_A0fmt_fields, 1804 /* bits */ 32, 1805 /* flags */ 0, 1806 }, 1807 #endif /* chips */ 1808 1809 #if defined(BCM_56850_A0) 1810 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56850_A0fmt */ 1811 /* format VFP_DOUBLE_WIDE_F3fmt */ 1812 /* nFields */ 6, 1813 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56640_A0fmt_fields, 1814 /* bits */ 36, 1815 /* flags */ 0, 1816 }, 1817 #endif /* chips */ 1818 1819 #if defined(BCM_56860_A0) 1820 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56860_A0fmt */ 1821 /* format VFP_DOUBLE_WIDE_F3fmt */ 1822 /* nFields */ 6, 1823 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56640_A0fmt_fields, 1824 /* bits */ 36, 1825 /* flags */ 0, 1826 }, 1827 #endif /* chips */ 1828 1829 #if defined(BCM_56870_A0) 1830 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56870_A0fmt */ 1831 /* format VFP_DOUBLE_WIDE_F3fmt */ 1832 /* nFields */ 6, 1833 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1834 /* bits */ 36, 1835 /* flags */ 0, 1836 }, 1837 #endif /* chips */ 1838 1839 #if defined(BCM_56960_A0) 1840 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt */ 1841 /* format VFP_DOUBLE_WIDE_F3fmt */ 1842 /* nFields */ 6, 1843 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1844 /* bits */ 36, 1845 /* flags */ 0, 1846 }, 1847 #endif /* chips */ 1848 1849 #if defined(BCM_56965_A0) 1850 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56965_A0fmt */ 1851 /* format VFP_DOUBLE_WIDE_F3fmt */ 1852 /* nFields */ 6, 1853 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1854 /* bits */ 36, 1855 /* flags */ 0, 1856 }, 1857 #endif /* chips */ 1858 1859 #if defined(BCM_56970_A0) 1860 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56970_A0fmt */ 1861 /* format VFP_DOUBLE_WIDE_F3fmt */ 1862 /* nFields */ 6, 1863 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1864 /* bits */ 36, 1865 /* flags */ 0, 1866 }, 1867 #endif /* chips */ 1868 1869 #if defined(BCM_56980_A0) 1870 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56980_A0fmt */ 1871 /* format VFP_DOUBLE_WIDE_F3fmt */ 1872 /* nFields */ 6, 1873 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1874 /* bits */ 36, 1875 /* flags */ 0, 1876 }, 1877 #endif /* chips */ 1878 1879 #if defined(BCM_56980_B0) 1880 { /* SOC_FORMAT_INT_VFP_DOUBLE_WIDE_F3_BCM56980_B0fmt */ 1881 /* format VFP_DOUBLE_WIDE_F3fmt */ 1882 /* nFields */ 6, 1883 /* *fields */ soc_VFP_DOUBLE_WIDE_F3_BCM56960_A0fmt_fields, 1884 /* bits */ 36, 1885 /* flags */ 0, 1886 }, 1887 #endif /* chips */ 1888 1889 #if defined(BCM_56514_A0) 1890 { /* SOC_FORMAT_INT_VFP_F1fmt */ 1891 /* format VFP_F1fmt */ 1892 /* nFields */ 8, 1893 /* *fields */ soc_VFP_F1fmt_fields, 1894 /* bits */ 32, 1895 /* flags */ 0, 1896 }, 1897 #endif /* chips */ 1898 1899 #if defined(BCM_53400_A0) 1900 { /* SOC_FORMAT_INT_VFP_F1_BCM53400_A0fmt */ 1901 /* format VFP_F1fmt */ 1902 /* nFields */ 15, 1903 /* *fields */ soc_VFP_F1_BCM53400_A0fmt_fields, 1904 /* bits */ 54, 1905 /* flags */ 0, 1906 }, 1907 #endif /* chips */ 1908 1909 #if defined(BCM_53540_A0) 1910 { /* SOC_FORMAT_INT_VFP_F1_BCM53540_A0fmt */ 1911 /* format VFP_F1fmt */ 1912 /* nFields */ 15, 1913 /* *fields */ soc_VFP_F1_BCM53400_A0fmt_fields, 1914 /* bits */ 54, 1915 /* flags */ 0, 1916 }, 1917 #endif /* chips */ 1918 1919 #if defined(BCM_53570_A0) 1920 { /* SOC_FORMAT_INT_VFP_F1_BCM53570_A0fmt */ 1921 /* format VFP_F1fmt */ 1922 /* nFields */ 15, 1923 /* *fields */ soc_VFP_F1_BCM53570_A0fmt_fields, 1924 /* bits */ 54, 1925 /* flags */ 0, 1926 }, 1927 #endif /* chips */ 1928 1929 #if defined(BCM_53570_B0) 1930 { /* SOC_FORMAT_INT_VFP_F1_BCM53570_B0fmt */ 1931 /* format VFP_F1fmt */ 1932 /* nFields */ 16, 1933 /* *fields */ soc_VFP_F1_BCM53570_B0fmt_fields, 1934 /* bits */ 54, 1935 /* flags */ 0, 1936 }, 1937 #endif /* chips */ 1938 1939 #if defined(BCM_56142_A0) 1940 { /* SOC_FORMAT_INT_VFP_F1_BCM56142_A0fmt */ 1941 /* format VFP_F1fmt */ 1942 /* nFields */ 15, 1943 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 1944 /* bits */ 54, 1945 /* flags */ 0, 1946 }, 1947 #endif /* chips */ 1948 1949 #if defined(BCM_56150_A0) 1950 { /* SOC_FORMAT_INT_VFP_F1_BCM56150_A0fmt */ 1951 /* format VFP_F1fmt */ 1952 /* nFields */ 15, 1953 /* *fields */ soc_VFP_F1_BCM56150_A0fmt_fields, 1954 /* bits */ 54, 1955 /* flags */ 0, 1956 }, 1957 #endif /* chips */ 1958 1959 #if defined(BCM_56160_A0) 1960 { /* SOC_FORMAT_INT_VFP_F1_BCM56160_A0fmt */ 1961 /* format VFP_F1fmt */ 1962 /* nFields */ 15, 1963 /* *fields */ soc_VFP_F1_BCM53400_A0fmt_fields, 1964 /* bits */ 54, 1965 /* flags */ 0, 1966 }, 1967 #endif /* chips */ 1968 1969 #if defined(BCM_56260_A0) 1970 { /* SOC_FORMAT_INT_VFP_F1_BCM56260_A0fmt */ 1971 /* format VFP_F1fmt */ 1972 /* nFields */ 20, 1973 /* *fields */ soc_VFP_F1_BCM56260_A0fmt_fields, 1974 /* bits */ 74, 1975 /* flags */ 0, 1976 }, 1977 #endif /* chips */ 1978 1979 #if defined(BCM_56260_B0) 1980 { /* SOC_FORMAT_INT_VFP_F1_BCM56260_B0fmt */ 1981 /* format VFP_F1fmt */ 1982 /* nFields */ 20, 1983 /* *fields */ soc_VFP_F1_BCM56260_A0fmt_fields, 1984 /* bits */ 74, 1985 /* flags */ 0, 1986 }, 1987 #endif /* chips */ 1988 1989 #if defined(BCM_56270_A0) 1990 { /* SOC_FORMAT_INT_VFP_F1_BCM56270_A0fmt */ 1991 /* format VFP_F1fmt */ 1992 /* nFields */ 20, 1993 /* *fields */ soc_VFP_F1_BCM56260_A0fmt_fields, 1994 /* bits */ 74, 1995 /* flags */ 0, 1996 }, 1997 #endif /* chips */ 1998 1999 #if defined(BCM_56334_A0) 2000 { /* SOC_FORMAT_INT_VFP_F1_BCM56334_A0fmt */ 2001 /* format VFP_F1fmt */ 2002 /* nFields */ 15, 2003 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2004 /* bits */ 54, 2005 /* flags */ 0, 2006 }, 2007 #endif /* chips */ 2008 2009 #if defined(BCM_56334_B0) 2010 { /* SOC_FORMAT_INT_VFP_F1_BCM56334_B0fmt */ 2011 /* format VFP_F1fmt */ 2012 /* nFields */ 15, 2013 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2014 /* bits */ 54, 2015 /* flags */ 0, 2016 }, 2017 #endif /* chips */ 2018 2019 #if defined(BCM_56340_A0) 2020 { /* SOC_FORMAT_INT_VFP_F1_BCM56340_A0fmt */ 2021 /* format VFP_F1fmt */ 2022 /* nFields */ 18, 2023 /* *fields */ soc_VFP_F1_BCM56640_A0fmt_fields, 2024 /* bits */ 70, 2025 /* flags */ 0, 2026 }, 2027 #endif /* chips */ 2028 2029 #if defined(BCM_56370_A0) 2030 { /* SOC_FORMAT_INT_VFP_F1_BCM56370_A0fmt */ 2031 /* format VFP_F1fmt */ 2032 /* nFields */ 18, 2033 /* *fields */ soc_VFP_F1_BCM56370_A0fmt_fields, 2034 /* bits */ 70, 2035 /* flags */ 0, 2036 }, 2037 #endif /* chips */ 2038 2039 #if defined(BCM_56440_A0) 2040 { /* SOC_FORMAT_INT_VFP_F1_BCM56440_A0fmt */ 2041 /* format VFP_F1fmt */ 2042 /* nFields */ 17, 2043 /* *fields */ soc_VFP_F1_BCM56440_A0fmt_fields, 2044 /* bits */ 74, 2045 /* flags */ 0, 2046 }, 2047 #endif /* chips */ 2048 2049 #if defined(BCM_56440_B0) 2050 { /* SOC_FORMAT_INT_VFP_F1_BCM56440_B0fmt */ 2051 /* format VFP_F1fmt */ 2052 /* nFields */ 17, 2053 /* *fields */ soc_VFP_F1_BCM56440_A0fmt_fields, 2054 /* bits */ 74, 2055 /* flags */ 0, 2056 }, 2057 #endif /* chips */ 2058 2059 #if defined(BCM_56450_A0) 2060 { /* SOC_FORMAT_INT_VFP_F1_BCM56450_A0fmt */ 2061 /* format VFP_F1fmt */ 2062 /* nFields */ 19, 2063 /* *fields */ soc_VFP_F1_BCM56450_A0fmt_fields, 2064 /* bits */ 74, 2065 /* flags */ 0, 2066 }, 2067 #endif /* chips */ 2068 2069 #if defined(BCM_56450_B0) 2070 { /* SOC_FORMAT_INT_VFP_F1_BCM56450_B0fmt */ 2071 /* format VFP_F1fmt */ 2072 /* nFields */ 19, 2073 /* *fields */ soc_VFP_F1_BCM56450_A0fmt_fields, 2074 /* bits */ 74, 2075 /* flags */ 0, 2076 }, 2077 #endif /* chips */ 2078 2079 #if defined(BCM_56450_B1) 2080 { /* SOC_FORMAT_INT_VFP_F1_BCM56450_B1fmt */ 2081 /* format VFP_F1fmt */ 2082 /* nFields */ 19, 2083 /* *fields */ soc_VFP_F1_BCM56450_A0fmt_fields, 2084 /* bits */ 74, 2085 /* flags */ 0, 2086 }, 2087 #endif /* chips */ 2088 2089 #if defined(BCM_56524_A0) 2090 { /* SOC_FORMAT_INT_VFP_F1_BCM56524_A0fmt */ 2091 /* format VFP_F1fmt */ 2092 /* nFields */ 15, 2093 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2094 /* bits */ 54, 2095 /* flags */ 0, 2096 }, 2097 #endif /* chips */ 2098 2099 #if defined(BCM_56524_B0) 2100 { /* SOC_FORMAT_INT_VFP_F1_BCM56524_B0fmt */ 2101 /* format VFP_F1fmt */ 2102 /* nFields */ 15, 2103 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2104 /* bits */ 54, 2105 /* flags */ 0, 2106 }, 2107 #endif /* chips */ 2108 2109 #if defined(BCM_56560_A0) 2110 { /* SOC_FORMAT_INT_VFP_F1_BCM56560_A0fmt */ 2111 /* format VFP_F1fmt */ 2112 /* nFields */ 18, 2113 /* *fields */ soc_VFP_F1_BCM56560_A0fmt_fields, 2114 /* bits */ 72, 2115 /* flags */ 0, 2116 }, 2117 #endif /* chips */ 2118 2119 #if defined(BCM_56560_B0) 2120 { /* SOC_FORMAT_INT_VFP_F1_BCM56560_B0fmt */ 2121 /* format VFP_F1fmt */ 2122 /* nFields */ 18, 2123 /* *fields */ soc_VFP_F1_BCM56560_A0fmt_fields, 2124 /* bits */ 72, 2125 /* flags */ 0, 2126 }, 2127 #endif /* chips */ 2128 2129 #if defined(BCM_56624_A0) 2130 { /* SOC_FORMAT_INT_VFP_F1_BCM56624_A0fmt */ 2131 /* format VFP_F1fmt */ 2132 /* nFields */ 15, 2133 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2134 /* bits */ 54, 2135 /* flags */ 0, 2136 }, 2137 #endif /* chips */ 2138 2139 #if defined(BCM_56624_B0) 2140 { /* SOC_FORMAT_INT_VFP_F1_BCM56624_B0fmt */ 2141 /* format VFP_F1fmt */ 2142 /* nFields */ 15, 2143 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2144 /* bits */ 54, 2145 /* flags */ 0, 2146 }, 2147 #endif /* chips */ 2148 2149 #if defined(BCM_56634_A0) 2150 { /* SOC_FORMAT_INT_VFP_F1_BCM56634_A0fmt */ 2151 /* format VFP_F1fmt */ 2152 /* nFields */ 15, 2153 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2154 /* bits */ 54, 2155 /* flags */ 0, 2156 }, 2157 #endif /* chips */ 2158 2159 #if defined(BCM_56634_B0) 2160 { /* SOC_FORMAT_INT_VFP_F1_BCM56634_B0fmt */ 2161 /* format VFP_F1fmt */ 2162 /* nFields */ 15, 2163 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2164 /* bits */ 54, 2165 /* flags */ 0, 2166 }, 2167 #endif /* chips */ 2168 2169 #if defined(BCM_56640_A0) 2170 { /* SOC_FORMAT_INT_VFP_F1_BCM56640_A0fmt */ 2171 /* format VFP_F1fmt */ 2172 /* nFields */ 18, 2173 /* *fields */ soc_VFP_F1_BCM56640_A0fmt_fields, 2174 /* bits */ 70, 2175 /* flags */ 0, 2176 }, 2177 #endif /* chips */ 2178 2179 #if defined(BCM_56670_A0) 2180 { /* SOC_FORMAT_INT_VFP_F1_BCM56670_A0fmt */ 2181 /* format VFP_F1fmt */ 2182 /* nFields */ 19, 2183 /* *fields */ soc_VFP_F1_BCM56670_A0fmt_fields, 2184 /* bits */ 72, 2185 /* flags */ 0, 2186 }, 2187 #endif /* chips */ 2188 2189 #if defined(BCM_56670_B0) 2190 { /* SOC_FORMAT_INT_VFP_F1_BCM56670_B0fmt */ 2191 /* format VFP_F1fmt */ 2192 /* nFields */ 19, 2193 /* *fields */ soc_VFP_F1_BCM56670_A0fmt_fields, 2194 /* bits */ 72, 2195 /* flags */ 0, 2196 }, 2197 #endif /* chips */ 2198 2199 #if defined(BCM_56680_A0) 2200 { /* SOC_FORMAT_INT_VFP_F1_BCM56680_A0fmt */ 2201 /* format VFP_F1fmt */ 2202 /* nFields */ 15, 2203 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2204 /* bits */ 54, 2205 /* flags */ 0, 2206 }, 2207 #endif /* chips */ 2208 2209 #if defined(BCM_56680_B0) 2210 { /* SOC_FORMAT_INT_VFP_F1_BCM56680_B0fmt */ 2211 /* format VFP_F1fmt */ 2212 /* nFields */ 15, 2213 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2214 /* bits */ 54, 2215 /* flags */ 0, 2216 }, 2217 #endif /* chips */ 2218 2219 #if defined(BCM_56685_A0) 2220 { /* SOC_FORMAT_INT_VFP_F1_BCM56685_A0fmt */ 2221 /* format VFP_F1fmt */ 2222 /* nFields */ 15, 2223 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2224 /* bits */ 54, 2225 /* flags */ 0, 2226 }, 2227 #endif /* chips */ 2228 2229 #if defined(BCM_56685_B0) 2230 { /* SOC_FORMAT_INT_VFP_F1_BCM56685_B0fmt */ 2231 /* format VFP_F1fmt */ 2232 /* nFields */ 15, 2233 /* *fields */ soc_VFP_F1_BCM56624_A0fmt_fields, 2234 /* bits */ 54, 2235 /* flags */ 0, 2236 }, 2237 #endif /* chips */ 2238 2239 #if defined(BCM_56725_A0) 2240 { /* SOC_FORMAT_INT_VFP_F1_BCM56725_A0fmt */ 2241 /* format VFP_F1fmt */ 2242 /* nFields */ 14, 2243 /* *fields */ soc_VFP_F1_BCM56820_A0fmt_fields, 2244 /* bits */ 50, 2245 /* flags */ 0, 2246 }, 2247 #endif /* chips */ 2248 2249 #if defined(BCM_56770_A0) 2250 { /* SOC_FORMAT_INT_VFP_F1_BCM56770_A0fmt */ 2251 /* format VFP_F1fmt */ 2252 /* nFields */ 18, 2253 /* *fields */ soc_VFP_F1_BCM56960_A0fmt_fields, 2254 /* bits */ 70, 2255 /* flags */ 0, 2256 }, 2257 #endif /* chips */ 2258 2259 #if defined(BCM_56820_A0) 2260 { /* SOC_FORMAT_INT_VFP_F1_BCM56820_A0fmt */ 2261 /* format VFP_F1fmt */ 2262 /* nFields */ 14, 2263 /* *fields */ soc_VFP_F1_BCM56820_A0fmt_fields, 2264 /* bits */ 50, 2265 /* flags */ 0, 2266 }, 2267 #endif /* chips */ 2268 2269 #if defined(BCM_56840_A0) 2270 { /* SOC_FORMAT_INT_VFP_F1_BCM56840_A0fmt */ 2271 /* format VFP_F1fmt */ 2272 /* nFields */ 15, 2273 /* *fields */ soc_VFP_F1_BCM56840_A0fmt_fields, 2274 /* bits */ 74, 2275 /* flags */ 0, 2276 }, 2277 #endif /* chips */ 2278 2279 #if defined(BCM_56840_B0) 2280 { /* SOC_FORMAT_INT_VFP_F1_BCM56840_B0fmt */ 2281 /* format VFP_F1fmt */ 2282 /* nFields */ 15, 2283 /* *fields */ soc_VFP_F1_BCM56840_A0fmt_fields, 2284 /* bits */ 74, 2285 /* flags */ 0, 2286 }, 2287 #endif /* chips */ 2288 2289 #if defined(BCM_56850_A0) 2290 { /* SOC_FORMAT_INT_VFP_F1_BCM56850_A0fmt */ 2291 /* format VFP_F1fmt */ 2292 /* nFields */ 18, 2293 /* *fields */ soc_VFP_F1_BCM56850_A0fmt_fields, 2294 /* bits */ 70, 2295 /* flags */ 0, 2296 }, 2297 #endif /* chips */ 2298 2299 #if defined(BCM_56860_A0) 2300 { /* SOC_FORMAT_INT_VFP_F1_BCM56860_A0fmt */ 2301 /* format VFP_F1fmt */ 2302 /* nFields */ 18, 2303 /* *fields */ soc_VFP_F1_BCM56860_A0fmt_fields, 2304 /* bits */ 72, 2305 /* flags */ 0, 2306 }, 2307 #endif /* chips */ 2308 2309 #if defined(BCM_56870_A0) 2310 { /* SOC_FORMAT_INT_VFP_F1_BCM56870_A0fmt */ 2311 /* format VFP_F1fmt */ 2312 /* nFields */ 18, 2313 /* *fields */ soc_VFP_F1_BCM56960_A0fmt_fields, 2314 /* bits */ 70, 2315 /* flags */ 0, 2316 }, 2317 #endif /* chips */ 2318 2319 #if defined(BCM_56960_A0) 2320 { /* SOC_FORMAT_INT_VFP_F1_BCM56960_A0fmt */ 2321 /* format VFP_F1fmt */ 2322 /* nFields */ 18, 2323 /* *fields */ soc_VFP_F1_BCM56960_A0fmt_fields, 2324 /* bits */ 70, 2325 /* flags */ 0, 2326 }, 2327 #endif /* chips */ 2328 2329 #if defined(BCM_56965_A0) 2330 { /* SOC_FORMAT_INT_VFP_F1_BCM56965_A0fmt */ 2331 /* format VFP_F1fmt */ 2332 /* nFields */ 18, 2333 /* *fields */ soc_VFP_F1_BCM56960_A0fmt_fields, 2334 /* bits */ 70, 2335 /* flags */ 0, 2336 }, 2337 #endif /* chips */ 2338 2339 #if defined(BCM_56970_A0) 2340 { /* SOC_FORMAT_INT_VFP_F1_BCM56970_A0fmt */ 2341 /* format VFP_F1fmt */ 2342 /* nFields */ 18, 2343 /* *fields */ soc_VFP_F1_BCM56960_A0fmt_fields, 2344 /* bits */ 70, 2345 /* flags */ 0, 2346 }, 2347 #endif /* chips */ 2348 2349 #if defined(BCM_56980_A0) 2350 { /* SOC_FORMAT_INT_VFP_F1_BCM56980_A0fmt */ 2351 /* format VFP_F1fmt */ 2352 /* nFields */ 20, 2353 /* *fields */ soc_VFP_F1_BCM56980_A0fmt_fields, 2354 /* bits */ 70, 2355 /* flags */ 0, 2356 }, 2357 #endif /* chips */ 2358 2359 #if defined(BCM_56980_B0) 2360 { /* SOC_FORMAT_INT_VFP_F1_BCM56980_B0fmt */ 2361 /* format VFP_F1fmt */ 2362 /* nFields */ 20, 2363 /* *fields */ soc_VFP_F1_BCM56980_A0fmt_fields, 2364 /* bits */ 70, 2365 /* flags */ 0, 2366 }, 2367 #endif /* chips */ 2368 2369 #if defined(BCM_56514_A0) 2370 { /* SOC_FORMAT_INT_VFP_F2_0fmt */ 2371 /* format VFP_F2_0fmt */ 2372 /* nFields */ 9, 2373 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0fmt_fields, 2374 /* bits */ 128, 2375 /* flags */ 0, 2376 }, 2377 #endif /* chips */ 2378 2379 #if defined(BCM_56514_A0) 2380 { /* SOC_FORMAT_INT_VFP_F2_1fmt */ 2381 /* format VFP_F2_1fmt */ 2382 /* nFields */ 1, 2383 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 2384 /* bits */ 128, 2385 /* flags */ 0, 2386 }, 2387 #endif /* chips */ 2388 2389 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 2390 defined(BCM_56334_B0) || defined(BCM_56514_A0) || \ 2391 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 2392 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 2393 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 2394 defined(BCM_56840_A0) || defined(BCM_56840_B0) 2395 { /* SOC_FORMAT_INT_VFP_F2_2fmt */ 2396 /* format VFP_F2_2fmt */ 2397 /* nFields */ 1, 2398 /* *fields */ soc_VFP_F2_2fmt_fields, 2399 /* bits */ 128, 2400 /* flags */ 0, 2401 }, 2402 #endif /* chips */ 2403 2404 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 2405 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 2406 defined(BCM_56514_A0) || defined(BCM_56524_B0) || \ 2407 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 2408 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 2409 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 2410 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 2411 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 2412 defined(BCM_56840_B0) 2413 { /* SOC_FORMAT_INT_VFP_F2_3fmt */ 2414 /* format VFP_F2_3fmt */ 2415 /* nFields */ 4, 2416 /* *fields */ soc_VFP_F2_3fmt_fields, 2417 /* bits */ 128, 2418 /* flags */ 0, 2419 }, 2420 #endif /* chips */ 2421 2422 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 2423 defined(BCM_56334_B0) || defined(BCM_56440_B0) || \ 2424 defined(BCM_56514_A0) || defined(BCM_56680_A0) || \ 2425 defined(BCM_56680_B0) || defined(BCM_56685_B0) || \ 2426 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 2427 defined(BCM_56840_A0) || defined(BCM_56840_B0) 2428 { /* SOC_FORMAT_INT_VFP_F2_4fmt */ 2429 /* format VFP_F2_4fmt */ 2430 /* nFields */ 5, 2431 /* *fields */ soc_VFP_F2_4fmt_fields, 2432 /* bits */ 128, 2433 /* flags */ 0, 2434 }, 2435 #endif /* chips */ 2436 2437 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 2438 defined(BCM_56334_B0) || defined(BCM_56440_B0) || \ 2439 defined(BCM_56514_A0) || defined(BCM_56680_A0) || \ 2440 defined(BCM_56680_B0) || defined(BCM_56685_B0) || \ 2441 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 2442 defined(BCM_56840_A0) || defined(BCM_56840_B0) 2443 { /* SOC_FORMAT_INT_VFP_F2_5fmt */ 2444 /* format VFP_F2_5fmt */ 2445 /* nFields */ 5, 2446 /* *fields */ soc_VFP_F2_5fmt_fields, 2447 /* bits */ 128, 2448 /* flags */ 0, 2449 }, 2450 #endif /* chips */ 2451 2452 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 2453 defined(BCM_56334_B0) || defined(BCM_56440_B0) || \ 2454 defined(BCM_56514_A0) || defined(BCM_56680_A0) || \ 2455 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 2456 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 2457 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 2458 defined(BCM_56840_B0) 2459 { /* SOC_FORMAT_INT_VFP_F2_6fmt */ 2460 /* format VFP_F2_6fmt */ 2461 /* nFields */ 2, 2462 /* *fields */ soc_VFP_F2_6fmt_fields, 2463 /* bits */ 128, 2464 /* flags */ 0, 2465 }, 2466 #endif /* chips */ 2467 2468 #if defined(BCM_56514_A0) || defined(BCM_56624_B0) || \ 2469 defined(BCM_56634_A0) || defined(BCM_56634_B0) 2470 { /* SOC_FORMAT_INT_VFP_F2_7fmt */ 2471 /* format VFP_F2_7fmt */ 2472 /* nFields */ 3, 2473 /* *fields */ soc_VFP_F2_7fmt_fields, 2474 /* bits */ 128, 2475 /* flags */ 0, 2476 }, 2477 #endif /* chips */ 2478 2479 #if defined(BCM_56640_A0) 2480 { /* SOC_FORMAT_INT_VFP_F2_8fmt */ 2481 /* format VFP_F2_8fmt */ 2482 /* nFields */ 1, 2483 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 2484 /* bits */ 128, 2485 /* flags */ 0, 2486 }, 2487 #endif /* chips */ 2488 2489 #if defined(BCM_56640_A0) 2490 { /* SOC_FORMAT_INT_VFP_F2_9fmt */ 2491 /* format VFP_F2_9fmt */ 2492 /* nFields */ 1, 2493 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 2494 /* bits */ 128, 2495 /* flags */ 0, 2496 }, 2497 #endif /* chips */ 2498 2499 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 2500 { /* SOC_FORMAT_INT_VFP_F2_10fmt */ 2501 /* format VFP_F2_10fmt */ 2502 /* nFields */ 11, 2503 /* *fields */ soc_VFP_F2_10fmt_fields, 2504 /* bits */ 128, 2505 /* flags */ 0, 2506 }, 2507 #endif /* chips */ 2508 2509 #if defined(BCM_53400_A0) 2510 { /* SOC_FORMAT_INT_VFP_F2_0_BCM53400_A0fmt */ 2511 /* format VFP_F2_0fmt */ 2512 /* nFields */ 9, 2513 /* *fields */ soc_VFP_F2_0fmt_fields, 2514 /* bits */ 128, 2515 /* flags */ 0, 2516 }, 2517 #endif /* chips */ 2518 2519 #if defined(BCM_53540_A0) 2520 { /* SOC_FORMAT_INT_VFP_F2_0_BCM53540_A0fmt */ 2521 /* format VFP_F2_0fmt */ 2522 /* nFields */ 9, 2523 /* *fields */ soc_VFP_F2_0fmt_fields, 2524 /* bits */ 128, 2525 /* flags */ 0, 2526 }, 2527 #endif /* chips */ 2528 2529 #if defined(BCM_53570_A0) 2530 { /* SOC_FORMAT_INT_VFP_F2_0_BCM53570_A0fmt */ 2531 /* format VFP_F2_0fmt */ 2532 /* nFields */ 9, 2533 /* *fields */ soc_VFP_F2_0fmt_fields, 2534 /* bits */ 128, 2535 /* flags */ 0, 2536 }, 2537 #endif /* chips */ 2538 2539 #if defined(BCM_53570_B0) 2540 { /* SOC_FORMAT_INT_VFP_F2_0_BCM53570_B0fmt */ 2541 /* format VFP_F2_0fmt */ 2542 /* nFields */ 9, 2543 /* *fields */ soc_VFP_F2_0fmt_fields, 2544 /* bits */ 128, 2545 /* flags */ 0, 2546 }, 2547 #endif /* chips */ 2548 2549 #if defined(BCM_56142_A0) 2550 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56142_A0fmt */ 2551 /* format VFP_F2_0fmt */ 2552 /* nFields */ 9, 2553 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2554 /* bits */ 128, 2555 /* flags */ 0, 2556 }, 2557 #endif /* chips */ 2558 2559 #if defined(BCM_56150_A0) 2560 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56150_A0fmt */ 2561 /* format VFP_F2_0fmt */ 2562 /* nFields */ 9, 2563 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 2564 /* bits */ 128, 2565 /* flags */ 0, 2566 }, 2567 #endif /* chips */ 2568 2569 #if defined(BCM_56160_A0) 2570 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56160_A0fmt */ 2571 /* format VFP_F2_0fmt */ 2572 /* nFields */ 9, 2573 /* *fields */ soc_VFP_F2_0fmt_fields, 2574 /* bits */ 128, 2575 /* flags */ 0, 2576 }, 2577 #endif /* chips */ 2578 2579 #if defined(BCM_56260_A0) 2580 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56260_A0fmt */ 2581 /* format VFP_F2_0fmt */ 2582 /* nFields */ 9, 2583 /* *fields */ soc_VFP_F2_0fmt_fields, 2584 /* bits */ 128, 2585 /* flags */ 0, 2586 }, 2587 #endif /* chips */ 2588 2589 #if defined(BCM_56260_B0) 2590 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56260_B0fmt */ 2591 /* format VFP_F2_0fmt */ 2592 /* nFields */ 9, 2593 /* *fields */ soc_VFP_F2_0fmt_fields, 2594 /* bits */ 128, 2595 /* flags */ 0, 2596 }, 2597 #endif /* chips */ 2598 2599 #if defined(BCM_56270_A0) 2600 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56270_A0fmt */ 2601 /* format VFP_F2_0fmt */ 2602 /* nFields */ 9, 2603 /* *fields */ soc_VFP_F2_0fmt_fields, 2604 /* bits */ 128, 2605 /* flags */ 0, 2606 }, 2607 #endif /* chips */ 2608 2609 #if defined(BCM_56334_A0) 2610 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56334_A0fmt */ 2611 /* format VFP_F2_0fmt */ 2612 /* nFields */ 9, 2613 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2614 /* bits */ 128, 2615 /* flags */ 0, 2616 }, 2617 #endif /* chips */ 2618 2619 #if defined(BCM_56334_B0) 2620 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56334_B0fmt */ 2621 /* format VFP_F2_0fmt */ 2622 /* nFields */ 9, 2623 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2624 /* bits */ 128, 2625 /* flags */ 0, 2626 }, 2627 #endif /* chips */ 2628 2629 #if defined(BCM_56340_A0) 2630 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56340_A0fmt */ 2631 /* format VFP_F2_0fmt */ 2632 /* nFields */ 9, 2633 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 2634 /* bits */ 128, 2635 /* flags */ 0, 2636 }, 2637 #endif /* chips */ 2638 2639 #if defined(BCM_56370_A0) 2640 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56370_A0fmt */ 2641 /* format VFP_F2_0fmt */ 2642 /* nFields */ 9, 2643 /* *fields */ soc_VFP_F2_0fmt_fields, 2644 /* bits */ 128, 2645 /* flags */ 0, 2646 }, 2647 #endif /* chips */ 2648 2649 #if defined(BCM_56440_A0) 2650 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56440_A0fmt */ 2651 /* format VFP_F2_0fmt */ 2652 /* nFields */ 9, 2653 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2654 /* bits */ 128, 2655 /* flags */ 0, 2656 }, 2657 #endif /* chips */ 2658 2659 #if defined(BCM_56440_B0) 2660 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56440_B0fmt */ 2661 /* format VFP_F2_0fmt */ 2662 /* nFields */ 9, 2663 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2664 /* bits */ 128, 2665 /* flags */ 0, 2666 }, 2667 #endif /* chips */ 2668 2669 #if defined(BCM_56450_A0) 2670 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56450_A0fmt */ 2671 /* format VFP_F2_0fmt */ 2672 /* nFields */ 9, 2673 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 2674 /* bits */ 128, 2675 /* flags */ 0, 2676 }, 2677 #endif /* chips */ 2678 2679 #if defined(BCM_56450_B0) 2680 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56450_B0fmt */ 2681 /* format VFP_F2_0fmt */ 2682 /* nFields */ 9, 2683 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 2684 /* bits */ 128, 2685 /* flags */ 0, 2686 }, 2687 #endif /* chips */ 2688 2689 #if defined(BCM_56450_B1) 2690 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56450_B1fmt */ 2691 /* format VFP_F2_0fmt */ 2692 /* nFields */ 9, 2693 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 2694 /* bits */ 128, 2695 /* flags */ 0, 2696 }, 2697 #endif /* chips */ 2698 2699 #if defined(BCM_56524_A0) 2700 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56524_A0fmt */ 2701 /* format VFP_F2_0fmt */ 2702 /* nFields */ 9, 2703 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2704 /* bits */ 128, 2705 /* flags */ 0, 2706 }, 2707 #endif /* chips */ 2708 2709 #if defined(BCM_56524_B0) 2710 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56524_B0fmt */ 2711 /* format VFP_F2_0fmt */ 2712 /* nFields */ 9, 2713 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2714 /* bits */ 128, 2715 /* flags */ 0, 2716 }, 2717 #endif /* chips */ 2718 2719 #if defined(BCM_56560_A0) 2720 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56560_A0fmt */ 2721 /* format VFP_F2_0fmt */ 2722 /* nFields */ 9, 2723 /* *fields */ soc_VFP_F2_0fmt_fields, 2724 /* bits */ 128, 2725 /* flags */ 0, 2726 }, 2727 #endif /* chips */ 2728 2729 #if defined(BCM_56560_B0) 2730 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56560_B0fmt */ 2731 /* format VFP_F2_0fmt */ 2732 /* nFields */ 9, 2733 /* *fields */ soc_VFP_F2_0fmt_fields, 2734 /* bits */ 128, 2735 /* flags */ 0, 2736 }, 2737 #endif /* chips */ 2738 2739 #if defined(BCM_56624_A0) 2740 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56624_A0fmt */ 2741 /* format VFP_F2_0fmt */ 2742 /* nFields */ 9, 2743 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2744 /* bits */ 128, 2745 /* flags */ 0, 2746 }, 2747 #endif /* chips */ 2748 2749 #if defined(BCM_56624_B0) 2750 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56624_B0fmt */ 2751 /* format VFP_F2_0fmt */ 2752 /* nFields */ 9, 2753 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2754 /* bits */ 128, 2755 /* flags */ 0, 2756 }, 2757 #endif /* chips */ 2758 2759 #if defined(BCM_56634_A0) 2760 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56634_A0fmt */ 2761 /* format VFP_F2_0fmt */ 2762 /* nFields */ 9, 2763 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2764 /* bits */ 128, 2765 /* flags */ 0, 2766 }, 2767 #endif /* chips */ 2768 2769 #if defined(BCM_56634_B0) 2770 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56634_B0fmt */ 2771 /* format VFP_F2_0fmt */ 2772 /* nFields */ 9, 2773 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2774 /* bits */ 128, 2775 /* flags */ 0, 2776 }, 2777 #endif /* chips */ 2778 2779 #if defined(BCM_56640_A0) 2780 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56640_A0fmt */ 2781 /* format VFP_F2_0fmt */ 2782 /* nFields */ 9, 2783 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 2784 /* bits */ 128, 2785 /* flags */ 0, 2786 }, 2787 #endif /* chips */ 2788 2789 #if defined(BCM_56670_A0) 2790 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56670_A0fmt */ 2791 /* format VFP_F2_0fmt */ 2792 /* nFields */ 9, 2793 /* *fields */ soc_VFP_F2_0fmt_fields, 2794 /* bits */ 128, 2795 /* flags */ 0, 2796 }, 2797 #endif /* chips */ 2798 2799 #if defined(BCM_56670_B0) 2800 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56670_B0fmt */ 2801 /* format VFP_F2_0fmt */ 2802 /* nFields */ 9, 2803 /* *fields */ soc_VFP_F2_0fmt_fields, 2804 /* bits */ 128, 2805 /* flags */ 0, 2806 }, 2807 #endif /* chips */ 2808 2809 #if defined(BCM_56680_A0) 2810 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56680_A0fmt */ 2811 /* format VFP_F2_0fmt */ 2812 /* nFields */ 9, 2813 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2814 /* bits */ 128, 2815 /* flags */ 0, 2816 }, 2817 #endif /* chips */ 2818 2819 #if defined(BCM_56680_B0) 2820 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56680_B0fmt */ 2821 /* format VFP_F2_0fmt */ 2822 /* nFields */ 9, 2823 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2824 /* bits */ 128, 2825 /* flags */ 0, 2826 }, 2827 #endif /* chips */ 2828 2829 #if defined(BCM_56685_A0) 2830 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56685_A0fmt */ 2831 /* format VFP_F2_0fmt */ 2832 /* nFields */ 9, 2833 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2834 /* bits */ 128, 2835 /* flags */ 0, 2836 }, 2837 #endif /* chips */ 2838 2839 #if defined(BCM_56685_B0) 2840 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56685_B0fmt */ 2841 /* format VFP_F2_0fmt */ 2842 /* nFields */ 9, 2843 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2844 /* bits */ 128, 2845 /* flags */ 0, 2846 }, 2847 #endif /* chips */ 2848 2849 #if defined(BCM_56725_A0) 2850 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56725_A0fmt */ 2851 /* format VFP_F2_0fmt */ 2852 /* nFields */ 9, 2853 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2854 /* bits */ 128, 2855 /* flags */ 0, 2856 }, 2857 #endif /* chips */ 2858 2859 #if defined(BCM_56770_A0) 2860 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56770_A0fmt */ 2861 /* format VFP_F2_0fmt */ 2862 /* nFields */ 9, 2863 /* *fields */ soc_VFP_F2_0fmt_fields, 2864 /* bits */ 128, 2865 /* flags */ 0, 2866 }, 2867 #endif /* chips */ 2868 2869 #if defined(BCM_56820_A0) 2870 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56820_A0fmt */ 2871 /* format VFP_F2_0fmt */ 2872 /* nFields */ 9, 2873 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2874 /* bits */ 128, 2875 /* flags */ 0, 2876 }, 2877 #endif /* chips */ 2878 2879 #if defined(BCM_56840_A0) 2880 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56840_A0fmt */ 2881 /* format VFP_F2_0fmt */ 2882 /* nFields */ 9, 2883 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2884 /* bits */ 128, 2885 /* flags */ 0, 2886 }, 2887 #endif /* chips */ 2888 2889 #if defined(BCM_56840_B0) 2890 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56840_B0fmt */ 2891 /* format VFP_F2_0fmt */ 2892 /* nFields */ 9, 2893 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56624_A0fmt_fields, 2894 /* bits */ 128, 2895 /* flags */ 0, 2896 }, 2897 #endif /* chips */ 2898 2899 #if defined(BCM_56850_A0) 2900 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56850_A0fmt */ 2901 /* format VFP_F2_0fmt */ 2902 /* nFields */ 9, 2903 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 2904 /* bits */ 128, 2905 /* flags */ 0, 2906 }, 2907 #endif /* chips */ 2908 2909 #if defined(BCM_56860_A0) 2910 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56860_A0fmt */ 2911 /* format VFP_F2_0fmt */ 2912 /* nFields */ 11, 2913 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_0_BCM56860_A0fmt_fields, 2914 /* bits */ 128, 2915 /* flags */ 0, 2916 }, 2917 #endif /* chips */ 2918 2919 #if defined(BCM_56870_A0) 2920 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56870_A0fmt */ 2921 /* format VFP_F2_0fmt */ 2922 /* nFields */ 9, 2923 /* *fields */ soc_VFP_F2_0fmt_fields, 2924 /* bits */ 128, 2925 /* flags */ 0, 2926 }, 2927 #endif /* chips */ 2928 2929 #if defined(BCM_56960_A0) 2930 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56960_A0fmt */ 2931 /* format VFP_F2_0fmt */ 2932 /* nFields */ 9, 2933 /* *fields */ soc_VFP_F2_0fmt_fields, 2934 /* bits */ 128, 2935 /* flags */ 0, 2936 }, 2937 #endif /* chips */ 2938 2939 #if defined(BCM_56965_A0) 2940 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56965_A0fmt */ 2941 /* format VFP_F2_0fmt */ 2942 /* nFields */ 9, 2943 /* *fields */ soc_VFP_F2_0fmt_fields, 2944 /* bits */ 128, 2945 /* flags */ 0, 2946 }, 2947 #endif /* chips */ 2948 2949 #if defined(BCM_56970_A0) 2950 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56970_A0fmt */ 2951 /* format VFP_F2_0fmt */ 2952 /* nFields */ 9, 2953 /* *fields */ soc_VFP_F2_0fmt_fields, 2954 /* bits */ 128, 2955 /* flags */ 0, 2956 }, 2957 #endif /* chips */ 2958 2959 #if defined(BCM_56980_A0) 2960 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56980_A0fmt */ 2961 /* format VFP_F2_0fmt */ 2962 /* nFields */ 9, 2963 /* *fields */ soc_VFP_F2_0fmt_fields, 2964 /* bits */ 128, 2965 /* flags */ 0, 2966 }, 2967 #endif /* chips */ 2968 2969 #if defined(BCM_56980_B0) 2970 { /* SOC_FORMAT_INT_VFP_F2_0_BCM56980_B0fmt */ 2971 /* format VFP_F2_0fmt */ 2972 /* nFields */ 9, 2973 /* *fields */ soc_VFP_F2_0fmt_fields, 2974 /* bits */ 128, 2975 /* flags */ 0, 2976 }, 2977 #endif /* chips */ 2978 2979 #if defined(BCM_56370_A0) 2980 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56370_A0fmt */ 2981 /* format VFP_F2_10fmt */ 2982 /* nFields */ 11, 2983 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 2984 /* bits */ 128, 2985 /* flags */ 0, 2986 }, 2987 #endif /* chips */ 2988 2989 #if defined(BCM_56560_A0) 2990 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56560_A0fmt */ 2991 /* format VFP_F2_10fmt */ 2992 /* nFields */ 11, 2993 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 2994 /* bits */ 128, 2995 /* flags */ 0, 2996 }, 2997 #endif /* chips */ 2998 2999 #if defined(BCM_56560_B0) 3000 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56560_B0fmt */ 3001 /* format VFP_F2_10fmt */ 3002 /* nFields */ 11, 3003 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3004 /* bits */ 128, 3005 /* flags */ 0, 3006 }, 3007 #endif /* chips */ 3008 3009 #if defined(BCM_56670_A0) 3010 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56670_A0fmt */ 3011 /* format VFP_F2_10fmt */ 3012 /* nFields */ 11, 3013 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3014 /* bits */ 128, 3015 /* flags */ 0, 3016 }, 3017 #endif /* chips */ 3018 3019 #if defined(BCM_56670_B0) 3020 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56670_B0fmt */ 3021 /* format VFP_F2_10fmt */ 3022 /* nFields */ 11, 3023 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3024 /* bits */ 128, 3025 /* flags */ 0, 3026 }, 3027 #endif /* chips */ 3028 3029 #if defined(BCM_56770_A0) 3030 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56770_A0fmt */ 3031 /* format VFP_F2_10fmt */ 3032 /* nFields */ 11, 3033 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3034 /* bits */ 128, 3035 /* flags */ 0, 3036 }, 3037 #endif /* chips */ 3038 3039 #if defined(BCM_56870_A0) 3040 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56870_A0fmt */ 3041 /* format VFP_F2_10fmt */ 3042 /* nFields */ 11, 3043 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3044 /* bits */ 128, 3045 /* flags */ 0, 3046 }, 3047 #endif /* chips */ 3048 3049 #if defined(BCM_56960_A0) 3050 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56960_A0fmt */ 3051 /* format VFP_F2_10fmt */ 3052 /* nFields */ 11, 3053 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3054 /* bits */ 128, 3055 /* flags */ 0, 3056 }, 3057 #endif /* chips */ 3058 3059 #if defined(BCM_56965_A0) 3060 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56965_A0fmt */ 3061 /* format VFP_F2_10fmt */ 3062 /* nFields */ 11, 3063 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3064 /* bits */ 128, 3065 /* flags */ 0, 3066 }, 3067 #endif /* chips */ 3068 3069 #if defined(BCM_56970_A0) 3070 { /* SOC_FORMAT_INT_VFP_F2_10_BCM56970_A0fmt */ 3071 /* format VFP_F2_10fmt */ 3072 /* nFields */ 11, 3073 /* *fields */ soc_VFP_F2_10_BCM56960_A0fmt_fields, 3074 /* bits */ 128, 3075 /* flags */ 0, 3076 }, 3077 #endif /* chips */ 3078 3079 #if defined(BCM_53400_A0) 3080 { /* SOC_FORMAT_INT_VFP_F2_1_BCM53400_A0fmt */ 3081 /* format VFP_F2_1fmt */ 3082 /* nFields */ 1, 3083 /* *fields */ soc_VFP_F2_1fmt_fields, 3084 /* bits */ 128, 3085 /* flags */ 0, 3086 }, 3087 #endif /* chips */ 3088 3089 #if defined(BCM_53540_A0) 3090 { /* SOC_FORMAT_INT_VFP_F2_1_BCM53540_A0fmt */ 3091 /* format VFP_F2_1fmt */ 3092 /* nFields */ 1, 3093 /* *fields */ soc_VFP_F2_1fmt_fields, 3094 /* bits */ 128, 3095 /* flags */ 0, 3096 }, 3097 #endif /* chips */ 3098 3099 #if defined(BCM_53570_A0) 3100 { /* SOC_FORMAT_INT_VFP_F2_1_BCM53570_A0fmt */ 3101 /* format VFP_F2_1fmt */ 3102 /* nFields */ 1, 3103 /* *fields */ soc_VFP_F2_1fmt_fields, 3104 /* bits */ 128, 3105 /* flags */ 0, 3106 }, 3107 #endif /* chips */ 3108 3109 #if defined(BCM_53570_B0) 3110 { /* SOC_FORMAT_INT_VFP_F2_1_BCM53570_B0fmt */ 3111 /* format VFP_F2_1fmt */ 3112 /* nFields */ 1, 3113 /* *fields */ soc_VFP_F2_1fmt_fields, 3114 /* bits */ 128, 3115 /* flags */ 0, 3116 }, 3117 #endif /* chips */ 3118 3119 #if defined(BCM_56142_A0) 3120 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56142_A0fmt */ 3121 /* format VFP_F2_1fmt */ 3122 /* nFields */ 1, 3123 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3124 /* bits */ 128, 3125 /* flags */ 0, 3126 }, 3127 #endif /* chips */ 3128 3129 #if defined(BCM_56150_A0) 3130 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56150_A0fmt */ 3131 /* format VFP_F2_1fmt */ 3132 /* nFields */ 1, 3133 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3134 /* bits */ 128, 3135 /* flags */ 0, 3136 }, 3137 #endif /* chips */ 3138 3139 #if defined(BCM_56160_A0) 3140 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56160_A0fmt */ 3141 /* format VFP_F2_1fmt */ 3142 /* nFields */ 1, 3143 /* *fields */ soc_VFP_F2_1fmt_fields, 3144 /* bits */ 128, 3145 /* flags */ 0, 3146 }, 3147 #endif /* chips */ 3148 3149 #if defined(BCM_56260_A0) 3150 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56260_A0fmt */ 3151 /* format VFP_F2_1fmt */ 3152 /* nFields */ 1, 3153 /* *fields */ soc_VFP_F2_1fmt_fields, 3154 /* bits */ 128, 3155 /* flags */ 0, 3156 }, 3157 #endif /* chips */ 3158 3159 #if defined(BCM_56260_B0) 3160 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56260_B0fmt */ 3161 /* format VFP_F2_1fmt */ 3162 /* nFields */ 1, 3163 /* *fields */ soc_VFP_F2_1fmt_fields, 3164 /* bits */ 128, 3165 /* flags */ 0, 3166 }, 3167 #endif /* chips */ 3168 3169 #if defined(BCM_56270_A0) 3170 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56270_A0fmt */ 3171 /* format VFP_F2_1fmt */ 3172 /* nFields */ 1, 3173 /* *fields */ soc_VFP_F2_1fmt_fields, 3174 /* bits */ 128, 3175 /* flags */ 0, 3176 }, 3177 #endif /* chips */ 3178 3179 #if defined(BCM_56334_A0) 3180 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56334_A0fmt */ 3181 /* format VFP_F2_1fmt */ 3182 /* nFields */ 1, 3183 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3184 /* bits */ 128, 3185 /* flags */ 0, 3186 }, 3187 #endif /* chips */ 3188 3189 #if defined(BCM_56334_B0) 3190 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56334_B0fmt */ 3191 /* format VFP_F2_1fmt */ 3192 /* nFields */ 1, 3193 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3194 /* bits */ 128, 3195 /* flags */ 0, 3196 }, 3197 #endif /* chips */ 3198 3199 #if defined(BCM_56340_A0) 3200 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56340_A0fmt */ 3201 /* format VFP_F2_1fmt */ 3202 /* nFields */ 1, 3203 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3204 /* bits */ 128, 3205 /* flags */ 0, 3206 }, 3207 #endif /* chips */ 3208 3209 #if defined(BCM_56370_A0) 3210 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56370_A0fmt */ 3211 /* format VFP_F2_1fmt */ 3212 /* nFields */ 1, 3213 /* *fields */ soc_VFP_F2_1fmt_fields, 3214 /* bits */ 128, 3215 /* flags */ 0, 3216 }, 3217 #endif /* chips */ 3218 3219 #if defined(BCM_56440_A0) 3220 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56440_A0fmt */ 3221 /* format VFP_F2_1fmt */ 3222 /* nFields */ 1, 3223 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3224 /* bits */ 128, 3225 /* flags */ 0, 3226 }, 3227 #endif /* chips */ 3228 3229 #if defined(BCM_56440_B0) 3230 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56440_B0fmt */ 3231 /* format VFP_F2_1fmt */ 3232 /* nFields */ 1, 3233 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3234 /* bits */ 128, 3235 /* flags */ 0, 3236 }, 3237 #endif /* chips */ 3238 3239 #if defined(BCM_56450_A0) 3240 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56450_A0fmt */ 3241 /* format VFP_F2_1fmt */ 3242 /* nFields */ 1, 3243 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3244 /* bits */ 128, 3245 /* flags */ 0, 3246 }, 3247 #endif /* chips */ 3248 3249 #if defined(BCM_56450_B0) 3250 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56450_B0fmt */ 3251 /* format VFP_F2_1fmt */ 3252 /* nFields */ 1, 3253 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3254 /* bits */ 128, 3255 /* flags */ 0, 3256 }, 3257 #endif /* chips */ 3258 3259 #if defined(BCM_56450_B1) 3260 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56450_B1fmt */ 3261 /* format VFP_F2_1fmt */ 3262 /* nFields */ 1, 3263 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3264 /* bits */ 128, 3265 /* flags */ 0, 3266 }, 3267 #endif /* chips */ 3268 3269 #if defined(BCM_56524_A0) 3270 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56524_A0fmt */ 3271 /* format VFP_F2_1fmt */ 3272 /* nFields */ 1, 3273 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3274 /* bits */ 128, 3275 /* flags */ 0, 3276 }, 3277 #endif /* chips */ 3278 3279 #if defined(BCM_56524_B0) 3280 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56524_B0fmt */ 3281 /* format VFP_F2_1fmt */ 3282 /* nFields */ 1, 3283 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3284 /* bits */ 128, 3285 /* flags */ 0, 3286 }, 3287 #endif /* chips */ 3288 3289 #if defined(BCM_56560_A0) 3290 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56560_A0fmt */ 3291 /* format VFP_F2_1fmt */ 3292 /* nFields */ 1, 3293 /* *fields */ soc_VFP_F2_1fmt_fields, 3294 /* bits */ 128, 3295 /* flags */ 0, 3296 }, 3297 #endif /* chips */ 3298 3299 #if defined(BCM_56560_B0) 3300 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56560_B0fmt */ 3301 /* format VFP_F2_1fmt */ 3302 /* nFields */ 1, 3303 /* *fields */ soc_VFP_F2_1fmt_fields, 3304 /* bits */ 128, 3305 /* flags */ 0, 3306 }, 3307 #endif /* chips */ 3308 3309 #if defined(BCM_56624_A0) 3310 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56624_A0fmt */ 3311 /* format VFP_F2_1fmt */ 3312 /* nFields */ 1, 3313 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3314 /* bits */ 128, 3315 /* flags */ 0, 3316 }, 3317 #endif /* chips */ 3318 3319 #if defined(BCM_56624_B0) 3320 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56624_B0fmt */ 3321 /* format VFP_F2_1fmt */ 3322 /* nFields */ 1, 3323 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3324 /* bits */ 128, 3325 /* flags */ 0, 3326 }, 3327 #endif /* chips */ 3328 3329 #if defined(BCM_56634_A0) 3330 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56634_A0fmt */ 3331 /* format VFP_F2_1fmt */ 3332 /* nFields */ 1, 3333 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3334 /* bits */ 128, 3335 /* flags */ 0, 3336 }, 3337 #endif /* chips */ 3338 3339 #if defined(BCM_56634_B0) 3340 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56634_B0fmt */ 3341 /* format VFP_F2_1fmt */ 3342 /* nFields */ 1, 3343 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3344 /* bits */ 128, 3345 /* flags */ 0, 3346 }, 3347 #endif /* chips */ 3348 3349 #if defined(BCM_56640_A0) 3350 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56640_A0fmt */ 3351 /* format VFP_F2_1fmt */ 3352 /* nFields */ 1, 3353 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3354 /* bits */ 128, 3355 /* flags */ 0, 3356 }, 3357 #endif /* chips */ 3358 3359 #if defined(BCM_56670_A0) 3360 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56670_A0fmt */ 3361 /* format VFP_F2_1fmt */ 3362 /* nFields */ 1, 3363 /* *fields */ soc_VFP_F2_1fmt_fields, 3364 /* bits */ 128, 3365 /* flags */ 0, 3366 }, 3367 #endif /* chips */ 3368 3369 #if defined(BCM_56670_B0) 3370 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56670_B0fmt */ 3371 /* format VFP_F2_1fmt */ 3372 /* nFields */ 1, 3373 /* *fields */ soc_VFP_F2_1fmt_fields, 3374 /* bits */ 128, 3375 /* flags */ 0, 3376 }, 3377 #endif /* chips */ 3378 3379 #if defined(BCM_56680_A0) 3380 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56680_A0fmt */ 3381 /* format VFP_F2_1fmt */ 3382 /* nFields */ 1, 3383 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3384 /* bits */ 128, 3385 /* flags */ 0, 3386 }, 3387 #endif /* chips */ 3388 3389 #if defined(BCM_56680_B0) 3390 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56680_B0fmt */ 3391 /* format VFP_F2_1fmt */ 3392 /* nFields */ 1, 3393 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3394 /* bits */ 128, 3395 /* flags */ 0, 3396 }, 3397 #endif /* chips */ 3398 3399 #if defined(BCM_56685_A0) 3400 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56685_A0fmt */ 3401 /* format VFP_F2_1fmt */ 3402 /* nFields */ 1, 3403 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3404 /* bits */ 128, 3405 /* flags */ 0, 3406 }, 3407 #endif /* chips */ 3408 3409 #if defined(BCM_56685_B0) 3410 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56685_B0fmt */ 3411 /* format VFP_F2_1fmt */ 3412 /* nFields */ 1, 3413 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3414 /* bits */ 128, 3415 /* flags */ 0, 3416 }, 3417 #endif /* chips */ 3418 3419 #if defined(BCM_56725_A0) 3420 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56725_A0fmt */ 3421 /* format VFP_F2_1fmt */ 3422 /* nFields */ 1, 3423 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3424 /* bits */ 128, 3425 /* flags */ 0, 3426 }, 3427 #endif /* chips */ 3428 3429 #if defined(BCM_56770_A0) 3430 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56770_A0fmt */ 3431 /* format VFP_F2_1fmt */ 3432 /* nFields */ 1, 3433 /* *fields */ soc_VFP_F2_1fmt_fields, 3434 /* bits */ 128, 3435 /* flags */ 0, 3436 }, 3437 #endif /* chips */ 3438 3439 #if defined(BCM_56820_A0) 3440 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56820_A0fmt */ 3441 /* format VFP_F2_1fmt */ 3442 /* nFields */ 1, 3443 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3444 /* bits */ 128, 3445 /* flags */ 0, 3446 }, 3447 #endif /* chips */ 3448 3449 #if defined(BCM_56840_A0) 3450 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56840_A0fmt */ 3451 /* format VFP_F2_1fmt */ 3452 /* nFields */ 1, 3453 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3454 /* bits */ 128, 3455 /* flags */ 0, 3456 }, 3457 #endif /* chips */ 3458 3459 #if defined(BCM_56840_B0) 3460 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56840_B0fmt */ 3461 /* format VFP_F2_1fmt */ 3462 /* nFields */ 1, 3463 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1fmt_fields, 3464 /* bits */ 128, 3465 /* flags */ 0, 3466 }, 3467 #endif /* chips */ 3468 3469 #if defined(BCM_56850_A0) 3470 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56850_A0fmt */ 3471 /* format VFP_F2_1fmt */ 3472 /* nFields */ 1, 3473 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3474 /* bits */ 128, 3475 /* flags */ 0, 3476 }, 3477 #endif /* chips */ 3478 3479 #if defined(BCM_56860_A0) 3480 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56860_A0fmt */ 3481 /* format VFP_F2_1fmt */ 3482 /* nFields */ 1, 3483 /* *fields */ soc_VFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 3484 /* bits */ 128, 3485 /* flags */ 0, 3486 }, 3487 #endif /* chips */ 3488 3489 #if defined(BCM_56870_A0) 3490 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56870_A0fmt */ 3491 /* format VFP_F2_1fmt */ 3492 /* nFields */ 1, 3493 /* *fields */ soc_VFP_F2_1fmt_fields, 3494 /* bits */ 128, 3495 /* flags */ 0, 3496 }, 3497 #endif /* chips */ 3498 3499 #if defined(BCM_56960_A0) 3500 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56960_A0fmt */ 3501 /* format VFP_F2_1fmt */ 3502 /* nFields */ 1, 3503 /* *fields */ soc_VFP_F2_1fmt_fields, 3504 /* bits */ 128, 3505 /* flags */ 0, 3506 }, 3507 #endif /* chips */ 3508 3509 #if defined(BCM_56965_A0) 3510 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56965_A0fmt */ 3511 /* format VFP_F2_1fmt */ 3512 /* nFields */ 1, 3513 /* *fields */ soc_VFP_F2_1fmt_fields, 3514 /* bits */ 128, 3515 /* flags */ 0, 3516 }, 3517 #endif /* chips */ 3518 3519 #if defined(BCM_56970_A0) 3520 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56970_A0fmt */ 3521 /* format VFP_F2_1fmt */ 3522 /* nFields */ 1, 3523 /* *fields */ soc_VFP_F2_1fmt_fields, 3524 /* bits */ 128, 3525 /* flags */ 0, 3526 }, 3527 #endif /* chips */ 3528 3529 #if defined(BCM_56980_A0) 3530 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56980_A0fmt */ 3531 /* format VFP_F2_1fmt */ 3532 /* nFields */ 1, 3533 /* *fields */ soc_VFP_F2_1fmt_fields, 3534 /* bits */ 128, 3535 /* flags */ 0, 3536 }, 3537 #endif /* chips */ 3538 3539 #if defined(BCM_56980_B0) 3540 { /* SOC_FORMAT_INT_VFP_F2_1_BCM56980_B0fmt */ 3541 /* format VFP_F2_1fmt */ 3542 /* nFields */ 1, 3543 /* *fields */ soc_VFP_F2_1fmt_fields, 3544 /* bits */ 128, 3545 /* flags */ 0, 3546 }, 3547 #endif /* chips */ 3548 3549 #if defined(BCM_53400_A0) 3550 { /* SOC_FORMAT_INT_VFP_F2_2_BCM53400_A0fmt */ 3551 /* format VFP_F2_2fmt */ 3552 /* nFields */ 1, 3553 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3554 /* bits */ 128, 3555 /* flags */ 0, 3556 }, 3557 #endif /* chips */ 3558 3559 #if defined(BCM_53540_A0) 3560 { /* SOC_FORMAT_INT_VFP_F2_2_BCM53540_A0fmt */ 3561 /* format VFP_F2_2fmt */ 3562 /* nFields */ 1, 3563 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3564 /* bits */ 128, 3565 /* flags */ 0, 3566 }, 3567 #endif /* chips */ 3568 3569 #if defined(BCM_53570_A0) 3570 { /* SOC_FORMAT_INT_VFP_F2_2_BCM53570_A0fmt */ 3571 /* format VFP_F2_2fmt */ 3572 /* nFields */ 1, 3573 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3574 /* bits */ 128, 3575 /* flags */ 0, 3576 }, 3577 #endif /* chips */ 3578 3579 #if defined(BCM_53570_B0) 3580 { /* SOC_FORMAT_INT_VFP_F2_2_BCM53570_B0fmt */ 3581 /* format VFP_F2_2fmt */ 3582 /* nFields */ 1, 3583 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3584 /* bits */ 128, 3585 /* flags */ 0, 3586 }, 3587 #endif /* chips */ 3588 3589 #if defined(BCM_56150_A0) 3590 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56150_A0fmt */ 3591 /* format VFP_F2_2fmt */ 3592 /* nFields */ 1, 3593 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3594 /* bits */ 128, 3595 /* flags */ 0, 3596 }, 3597 #endif /* chips */ 3598 3599 #if defined(BCM_56160_A0) 3600 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56160_A0fmt */ 3601 /* format VFP_F2_2fmt */ 3602 /* nFields */ 1, 3603 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3604 /* bits */ 128, 3605 /* flags */ 0, 3606 }, 3607 #endif /* chips */ 3608 3609 #if defined(BCM_56260_A0) 3610 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56260_A0fmt */ 3611 /* format VFP_F2_2fmt */ 3612 /* nFields */ 1, 3613 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3614 /* bits */ 128, 3615 /* flags */ 0, 3616 }, 3617 #endif /* chips */ 3618 3619 #if defined(BCM_56260_B0) 3620 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56260_B0fmt */ 3621 /* format VFP_F2_2fmt */ 3622 /* nFields */ 1, 3623 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3624 /* bits */ 128, 3625 /* flags */ 0, 3626 }, 3627 #endif /* chips */ 3628 3629 #if defined(BCM_56270_A0) 3630 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56270_A0fmt */ 3631 /* format VFP_F2_2fmt */ 3632 /* nFields */ 1, 3633 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3634 /* bits */ 128, 3635 /* flags */ 0, 3636 }, 3637 #endif /* chips */ 3638 3639 #if defined(BCM_56340_A0) 3640 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56340_A0fmt */ 3641 /* format VFP_F2_2fmt */ 3642 /* nFields */ 1, 3643 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3644 /* bits */ 128, 3645 /* flags */ 0, 3646 }, 3647 #endif /* chips */ 3648 3649 #if defined(BCM_56370_A0) 3650 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56370_A0fmt */ 3651 /* format VFP_F2_2fmt */ 3652 /* nFields */ 1, 3653 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3654 /* bits */ 128, 3655 /* flags */ 0, 3656 }, 3657 #endif /* chips */ 3658 3659 #if defined(BCM_56440_A0) 3660 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56440_A0fmt */ 3661 /* format VFP_F2_2fmt */ 3662 /* nFields */ 1, 3663 /* *fields */ soc_VFP_F2_2fmt_fields, 3664 /* bits */ 128, 3665 /* flags */ 0, 3666 }, 3667 #endif /* chips */ 3668 3669 #if defined(BCM_56440_B0) 3670 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56440_B0fmt */ 3671 /* format VFP_F2_2fmt */ 3672 /* nFields */ 1, 3673 /* *fields */ soc_VFP_F2_2fmt_fields, 3674 /* bits */ 128, 3675 /* flags */ 0, 3676 }, 3677 #endif /* chips */ 3678 3679 #if defined(BCM_56450_A0) 3680 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56450_A0fmt */ 3681 /* format VFP_F2_2fmt */ 3682 /* nFields */ 1, 3683 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3684 /* bits */ 128, 3685 /* flags */ 0, 3686 }, 3687 #endif /* chips */ 3688 3689 #if defined(BCM_56450_B0) 3690 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56450_B0fmt */ 3691 /* format VFP_F2_2fmt */ 3692 /* nFields */ 1, 3693 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3694 /* bits */ 128, 3695 /* flags */ 0, 3696 }, 3697 #endif /* chips */ 3698 3699 #if defined(BCM_56450_B1) 3700 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56450_B1fmt */ 3701 /* format VFP_F2_2fmt */ 3702 /* nFields */ 1, 3703 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3704 /* bits */ 128, 3705 /* flags */ 0, 3706 }, 3707 #endif /* chips */ 3708 3709 #if defined(BCM_56524_A0) 3710 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56524_A0fmt */ 3711 /* format VFP_F2_2fmt */ 3712 /* nFields */ 1, 3713 /* *fields */ soc_VFP_F2_2fmt_fields, 3714 /* bits */ 128, 3715 /* flags */ 0, 3716 }, 3717 #endif /* chips */ 3718 3719 #if defined(BCM_56524_B0) 3720 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56524_B0fmt */ 3721 /* format VFP_F2_2fmt */ 3722 /* nFields */ 1, 3723 /* *fields */ soc_VFP_F2_2fmt_fields, 3724 /* bits */ 128, 3725 /* flags */ 0, 3726 }, 3727 #endif /* chips */ 3728 3729 #if defined(BCM_56560_A0) 3730 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56560_A0fmt */ 3731 /* format VFP_F2_2fmt */ 3732 /* nFields */ 1, 3733 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3734 /* bits */ 128, 3735 /* flags */ 0, 3736 }, 3737 #endif /* chips */ 3738 3739 #if defined(BCM_56560_B0) 3740 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56560_B0fmt */ 3741 /* format VFP_F2_2fmt */ 3742 /* nFields */ 1, 3743 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3744 /* bits */ 128, 3745 /* flags */ 0, 3746 }, 3747 #endif /* chips */ 3748 3749 #if defined(BCM_56624_A0) 3750 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56624_A0fmt */ 3751 /* format VFP_F2_2fmt */ 3752 /* nFields */ 1, 3753 /* *fields */ soc_VFP_F2_2fmt_fields, 3754 /* bits */ 128, 3755 /* flags */ 0, 3756 }, 3757 #endif /* chips */ 3758 3759 #if defined(BCM_56624_B0) 3760 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56624_B0fmt */ 3761 /* format VFP_F2_2fmt */ 3762 /* nFields */ 1, 3763 /* *fields */ soc_VFP_F2_2fmt_fields, 3764 /* bits */ 128, 3765 /* flags */ 0, 3766 }, 3767 #endif /* chips */ 3768 3769 #if defined(BCM_56634_A0) 3770 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56634_A0fmt */ 3771 /* format VFP_F2_2fmt */ 3772 /* nFields */ 1, 3773 /* *fields */ soc_VFP_F2_2fmt_fields, 3774 /* bits */ 128, 3775 /* flags */ 0, 3776 }, 3777 #endif /* chips */ 3778 3779 #if defined(BCM_56634_B0) 3780 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56634_B0fmt */ 3781 /* format VFP_F2_2fmt */ 3782 /* nFields */ 1, 3783 /* *fields */ soc_VFP_F2_2fmt_fields, 3784 /* bits */ 128, 3785 /* flags */ 0, 3786 }, 3787 #endif /* chips */ 3788 3789 #if defined(BCM_56640_A0) 3790 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56640_A0fmt */ 3791 /* format VFP_F2_2fmt */ 3792 /* nFields */ 1, 3793 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3794 /* bits */ 128, 3795 /* flags */ 0, 3796 }, 3797 #endif /* chips */ 3798 3799 #if defined(BCM_56670_A0) 3800 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56670_A0fmt */ 3801 /* format VFP_F2_2fmt */ 3802 /* nFields */ 1, 3803 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3804 /* bits */ 128, 3805 /* flags */ 0, 3806 }, 3807 #endif /* chips */ 3808 3809 #if defined(BCM_56670_B0) 3810 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56670_B0fmt */ 3811 /* format VFP_F2_2fmt */ 3812 /* nFields */ 1, 3813 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3814 /* bits */ 128, 3815 /* flags */ 0, 3816 }, 3817 #endif /* chips */ 3818 3819 #if defined(BCM_56770_A0) 3820 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56770_A0fmt */ 3821 /* format VFP_F2_2fmt */ 3822 /* nFields */ 1, 3823 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3824 /* bits */ 128, 3825 /* flags */ 0, 3826 }, 3827 #endif /* chips */ 3828 3829 #if defined(BCM_56850_A0) 3830 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56850_A0fmt */ 3831 /* format VFP_F2_2fmt */ 3832 /* nFields */ 1, 3833 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3834 /* bits */ 128, 3835 /* flags */ 0, 3836 }, 3837 #endif /* chips */ 3838 3839 #if defined(BCM_56860_A0) 3840 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56860_A0fmt */ 3841 /* format VFP_F2_2fmt */ 3842 /* nFields */ 1, 3843 /* *fields */ soc_VFP_F2_2_BCM56640_A0fmt_fields, 3844 /* bits */ 128, 3845 /* flags */ 0, 3846 }, 3847 #endif /* chips */ 3848 3849 #if defined(BCM_56870_A0) 3850 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56870_A0fmt */ 3851 /* format VFP_F2_2fmt */ 3852 /* nFields */ 1, 3853 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3854 /* bits */ 128, 3855 /* flags */ 0, 3856 }, 3857 #endif /* chips */ 3858 3859 #if defined(BCM_56960_A0) 3860 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56960_A0fmt */ 3861 /* format VFP_F2_2fmt */ 3862 /* nFields */ 1, 3863 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3864 /* bits */ 128, 3865 /* flags */ 0, 3866 }, 3867 #endif /* chips */ 3868 3869 #if defined(BCM_56965_A0) 3870 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56965_A0fmt */ 3871 /* format VFP_F2_2fmt */ 3872 /* nFields */ 1, 3873 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3874 /* bits */ 128, 3875 /* flags */ 0, 3876 }, 3877 #endif /* chips */ 3878 3879 #if defined(BCM_56970_A0) 3880 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56970_A0fmt */ 3881 /* format VFP_F2_2fmt */ 3882 /* nFields */ 1, 3883 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3884 /* bits */ 128, 3885 /* flags */ 0, 3886 }, 3887 #endif /* chips */ 3888 3889 #if defined(BCM_56980_A0) 3890 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56980_A0fmt */ 3891 /* format VFP_F2_2fmt */ 3892 /* nFields */ 1, 3893 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3894 /* bits */ 128, 3895 /* flags */ 0, 3896 }, 3897 #endif /* chips */ 3898 3899 #if defined(BCM_56980_B0) 3900 { /* SOC_FORMAT_INT_VFP_F2_2_BCM56980_B0fmt */ 3901 /* format VFP_F2_2fmt */ 3902 /* nFields */ 1, 3903 /* *fields */ soc_VFP_F2_2_BCM53400_A0fmt_fields, 3904 /* bits */ 128, 3905 /* flags */ 0, 3906 }, 3907 #endif /* chips */ 3908 3909 #if defined(BCM_53400_A0) 3910 { /* SOC_FORMAT_INT_VFP_F2_3_BCM53400_A0fmt */ 3911 /* format VFP_F2_3fmt */ 3912 /* nFields */ 4, 3913 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3914 /* bits */ 128, 3915 /* flags */ 0, 3916 }, 3917 #endif /* chips */ 3918 3919 #if defined(BCM_53540_A0) 3920 { /* SOC_FORMAT_INT_VFP_F2_3_BCM53540_A0fmt */ 3921 /* format VFP_F2_3fmt */ 3922 /* nFields */ 4, 3923 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3924 /* bits */ 128, 3925 /* flags */ 0, 3926 }, 3927 #endif /* chips */ 3928 3929 #if defined(BCM_53570_A0) 3930 { /* SOC_FORMAT_INT_VFP_F2_3_BCM53570_A0fmt */ 3931 /* format VFP_F2_3fmt */ 3932 /* nFields */ 4, 3933 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3934 /* bits */ 128, 3935 /* flags */ 0, 3936 }, 3937 #endif /* chips */ 3938 3939 #if defined(BCM_53570_B0) 3940 { /* SOC_FORMAT_INT_VFP_F2_3_BCM53570_B0fmt */ 3941 /* format VFP_F2_3fmt */ 3942 /* nFields */ 4, 3943 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3944 /* bits */ 128, 3945 /* flags */ 0, 3946 }, 3947 #endif /* chips */ 3948 3949 #if defined(BCM_56150_A0) 3950 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56150_A0fmt */ 3951 /* format VFP_F2_3fmt */ 3952 /* nFields */ 4, 3953 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 3954 /* bits */ 128, 3955 /* flags */ 0, 3956 }, 3957 #endif /* chips */ 3958 3959 #if defined(BCM_56160_A0) 3960 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56160_A0fmt */ 3961 /* format VFP_F2_3fmt */ 3962 /* nFields */ 4, 3963 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3964 /* bits */ 128, 3965 /* flags */ 0, 3966 }, 3967 #endif /* chips */ 3968 3969 #if defined(BCM_56260_A0) 3970 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56260_A0fmt */ 3971 /* format VFP_F2_3fmt */ 3972 /* nFields */ 4, 3973 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3974 /* bits */ 128, 3975 /* flags */ 0, 3976 }, 3977 #endif /* chips */ 3978 3979 #if defined(BCM_56260_B0) 3980 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56260_B0fmt */ 3981 /* format VFP_F2_3fmt */ 3982 /* nFields */ 4, 3983 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3984 /* bits */ 128, 3985 /* flags */ 0, 3986 }, 3987 #endif /* chips */ 3988 3989 #if defined(BCM_56270_A0) 3990 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56270_A0fmt */ 3991 /* format VFP_F2_3fmt */ 3992 /* nFields */ 4, 3993 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 3994 /* bits */ 128, 3995 /* flags */ 0, 3996 }, 3997 #endif /* chips */ 3998 3999 #if defined(BCM_56340_A0) 4000 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56340_A0fmt */ 4001 /* format VFP_F2_3fmt */ 4002 /* nFields */ 4, 4003 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 4004 /* bits */ 128, 4005 /* flags */ 0, 4006 }, 4007 #endif /* chips */ 4008 4009 #if defined(BCM_56370_A0) 4010 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56370_A0fmt */ 4011 /* format VFP_F2_3fmt */ 4012 /* nFields */ 4, 4013 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4014 /* bits */ 128, 4015 /* flags */ 0, 4016 }, 4017 #endif /* chips */ 4018 4019 #if defined(BCM_56440_B0) 4020 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56440_B0fmt */ 4021 /* format VFP_F2_3fmt */ 4022 /* nFields */ 4, 4023 /* *fields */ soc_VFP_F2_3fmt_fields, 4024 /* bits */ 128, 4025 /* flags */ 0, 4026 }, 4027 #endif /* chips */ 4028 4029 #if defined(BCM_56450_A0) 4030 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56450_A0fmt */ 4031 /* format VFP_F2_3fmt */ 4032 /* nFields */ 4, 4033 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 4034 /* bits */ 128, 4035 /* flags */ 0, 4036 }, 4037 #endif /* chips */ 4038 4039 #if defined(BCM_56450_B0) 4040 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56450_B0fmt */ 4041 /* format VFP_F2_3fmt */ 4042 /* nFields */ 4, 4043 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 4044 /* bits */ 128, 4045 /* flags */ 0, 4046 }, 4047 #endif /* chips */ 4048 4049 #if defined(BCM_56450_B1) 4050 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56450_B1fmt */ 4051 /* format VFP_F2_3fmt */ 4052 /* nFields */ 4, 4053 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 4054 /* bits */ 128, 4055 /* flags */ 0, 4056 }, 4057 #endif /* chips */ 4058 4059 #if defined(BCM_56524_A0) 4060 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56524_A0fmt */ 4061 /* format VFP_F2_3fmt */ 4062 /* nFields */ 4, 4063 /* *fields */ soc_VFP_F2_3fmt_fields, 4064 /* bits */ 128, 4065 /* flags */ 0, 4066 }, 4067 #endif /* chips */ 4068 4069 #if defined(BCM_56560_A0) 4070 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56560_A0fmt */ 4071 /* format VFP_F2_3fmt */ 4072 /* nFields */ 4, 4073 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4074 /* bits */ 128, 4075 /* flags */ 0, 4076 }, 4077 #endif /* chips */ 4078 4079 #if defined(BCM_56560_B0) 4080 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56560_B0fmt */ 4081 /* format VFP_F2_3fmt */ 4082 /* nFields */ 4, 4083 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4084 /* bits */ 128, 4085 /* flags */ 0, 4086 }, 4087 #endif /* chips */ 4088 4089 #if defined(BCM_56640_A0) 4090 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56640_A0fmt */ 4091 /* format VFP_F2_3fmt */ 4092 /* nFields */ 4, 4093 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 4094 /* bits */ 128, 4095 /* flags */ 0, 4096 }, 4097 #endif /* chips */ 4098 4099 #if defined(BCM_56670_A0) 4100 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56670_A0fmt */ 4101 /* format VFP_F2_3fmt */ 4102 /* nFields */ 4, 4103 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4104 /* bits */ 128, 4105 /* flags */ 0, 4106 }, 4107 #endif /* chips */ 4108 4109 #if defined(BCM_56670_B0) 4110 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56670_B0fmt */ 4111 /* format VFP_F2_3fmt */ 4112 /* nFields */ 4, 4113 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4114 /* bits */ 128, 4115 /* flags */ 0, 4116 }, 4117 #endif /* chips */ 4118 4119 #if defined(BCM_56685_A0) 4120 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56685_A0fmt */ 4121 /* format VFP_F2_3fmt */ 4122 /* nFields */ 4, 4123 /* *fields */ soc_VFP_F2_3fmt_fields, 4124 /* bits */ 128, 4125 /* flags */ 0, 4126 }, 4127 #endif /* chips */ 4128 4129 #if defined(BCM_56770_A0) 4130 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56770_A0fmt */ 4131 /* format VFP_F2_3fmt */ 4132 /* nFields */ 4, 4133 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4134 /* bits */ 128, 4135 /* flags */ 0, 4136 }, 4137 #endif /* chips */ 4138 4139 #if defined(BCM_56850_A0) 4140 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56850_A0fmt */ 4141 /* format VFP_F2_3fmt */ 4142 /* nFields */ 4, 4143 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 4144 /* bits */ 128, 4145 /* flags */ 0, 4146 }, 4147 #endif /* chips */ 4148 4149 #if defined(BCM_56860_A0) 4150 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56860_A0fmt */ 4151 /* format VFP_F2_3fmt */ 4152 /* nFields */ 4, 4153 /* *fields */ soc_VFP_F2_3_BCM56640_A0fmt_fields, 4154 /* bits */ 128, 4155 /* flags */ 0, 4156 }, 4157 #endif /* chips */ 4158 4159 #if defined(BCM_56870_A0) 4160 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56870_A0fmt */ 4161 /* format VFP_F2_3fmt */ 4162 /* nFields */ 4, 4163 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4164 /* bits */ 128, 4165 /* flags */ 0, 4166 }, 4167 #endif /* chips */ 4168 4169 #if defined(BCM_56960_A0) 4170 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56960_A0fmt */ 4171 /* format VFP_F2_3fmt */ 4172 /* nFields */ 4, 4173 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4174 /* bits */ 128, 4175 /* flags */ 0, 4176 }, 4177 #endif /* chips */ 4178 4179 #if defined(BCM_56965_A0) 4180 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56965_A0fmt */ 4181 /* format VFP_F2_3fmt */ 4182 /* nFields */ 4, 4183 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4184 /* bits */ 128, 4185 /* flags */ 0, 4186 }, 4187 #endif /* chips */ 4188 4189 #if defined(BCM_56970_A0) 4190 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56970_A0fmt */ 4191 /* format VFP_F2_3fmt */ 4192 /* nFields */ 4, 4193 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4194 /* bits */ 128, 4195 /* flags */ 0, 4196 }, 4197 #endif /* chips */ 4198 4199 #if defined(BCM_56980_A0) 4200 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56980_A0fmt */ 4201 /* format VFP_F2_3fmt */ 4202 /* nFields */ 4, 4203 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4204 /* bits */ 128, 4205 /* flags */ 0, 4206 }, 4207 #endif /* chips */ 4208 4209 #if defined(BCM_56980_B0) 4210 { /* SOC_FORMAT_INT_VFP_F2_3_BCM56980_B0fmt */ 4211 /* format VFP_F2_3fmt */ 4212 /* nFields */ 4, 4213 /* *fields */ soc_VFP_F2_3_BCM53400_A0fmt_fields, 4214 /* bits */ 128, 4215 /* flags */ 0, 4216 }, 4217 #endif /* chips */ 4218 4219 #if defined(BCM_53400_A0) 4220 { /* SOC_FORMAT_INT_VFP_F2_4_BCM53400_A0fmt */ 4221 /* format VFP_F2_4fmt */ 4222 /* nFields */ 5, 4223 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4224 /* bits */ 128, 4225 /* flags */ 0, 4226 }, 4227 #endif /* chips */ 4228 4229 #if defined(BCM_53540_A0) 4230 { /* SOC_FORMAT_INT_VFP_F2_4_BCM53540_A0fmt */ 4231 /* format VFP_F2_4fmt */ 4232 /* nFields */ 5, 4233 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4234 /* bits */ 128, 4235 /* flags */ 0, 4236 }, 4237 #endif /* chips */ 4238 4239 #if defined(BCM_53570_A0) 4240 { /* SOC_FORMAT_INT_VFP_F2_4_BCM53570_A0fmt */ 4241 /* format VFP_F2_4fmt */ 4242 /* nFields */ 5, 4243 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4244 /* bits */ 128, 4245 /* flags */ 0, 4246 }, 4247 #endif /* chips */ 4248 4249 #if defined(BCM_53570_B0) 4250 { /* SOC_FORMAT_INT_VFP_F2_4_BCM53570_B0fmt */ 4251 /* format VFP_F2_4fmt */ 4252 /* nFields */ 5, 4253 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4254 /* bits */ 128, 4255 /* flags */ 0, 4256 }, 4257 #endif /* chips */ 4258 4259 #if defined(BCM_56150_A0) 4260 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56150_A0fmt */ 4261 /* format VFP_F2_4fmt */ 4262 /* nFields */ 5, 4263 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4264 /* bits */ 128, 4265 /* flags */ 0, 4266 }, 4267 #endif /* chips */ 4268 4269 #if defined(BCM_56160_A0) 4270 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56160_A0fmt */ 4271 /* format VFP_F2_4fmt */ 4272 /* nFields */ 5, 4273 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4274 /* bits */ 128, 4275 /* flags */ 0, 4276 }, 4277 #endif /* chips */ 4278 4279 #if defined(BCM_56260_A0) 4280 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56260_A0fmt */ 4281 /* format VFP_F2_4fmt */ 4282 /* nFields */ 5, 4283 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4284 /* bits */ 128, 4285 /* flags */ 0, 4286 }, 4287 #endif /* chips */ 4288 4289 #if defined(BCM_56260_B0) 4290 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56260_B0fmt */ 4291 /* format VFP_F2_4fmt */ 4292 /* nFields */ 5, 4293 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4294 /* bits */ 128, 4295 /* flags */ 0, 4296 }, 4297 #endif /* chips */ 4298 4299 #if defined(BCM_56270_A0) 4300 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56270_A0fmt */ 4301 /* format VFP_F2_4fmt */ 4302 /* nFields */ 5, 4303 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4304 /* bits */ 128, 4305 /* flags */ 0, 4306 }, 4307 #endif /* chips */ 4308 4309 #if defined(BCM_56340_A0) 4310 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56340_A0fmt */ 4311 /* format VFP_F2_4fmt */ 4312 /* nFields */ 5, 4313 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4314 /* bits */ 128, 4315 /* flags */ 0, 4316 }, 4317 #endif /* chips */ 4318 4319 #if defined(BCM_56370_A0) 4320 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56370_A0fmt */ 4321 /* format VFP_F2_4fmt */ 4322 /* nFields */ 5, 4323 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4324 /* bits */ 128, 4325 /* flags */ 0, 4326 }, 4327 #endif /* chips */ 4328 4329 #if defined(BCM_56440_A0) 4330 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56440_A0fmt */ 4331 /* format VFP_F2_4fmt */ 4332 /* nFields */ 5, 4333 /* *fields */ soc_VFP_F2_4fmt_fields, 4334 /* bits */ 128, 4335 /* flags */ 0, 4336 }, 4337 #endif /* chips */ 4338 4339 #if defined(BCM_56450_A0) 4340 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56450_A0fmt */ 4341 /* format VFP_F2_4fmt */ 4342 /* nFields */ 5, 4343 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4344 /* bits */ 128, 4345 /* flags */ 0, 4346 }, 4347 #endif /* chips */ 4348 4349 #if defined(BCM_56450_B0) 4350 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56450_B0fmt */ 4351 /* format VFP_F2_4fmt */ 4352 /* nFields */ 5, 4353 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4354 /* bits */ 128, 4355 /* flags */ 0, 4356 }, 4357 #endif /* chips */ 4358 4359 #if defined(BCM_56450_B1) 4360 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56450_B1fmt */ 4361 /* format VFP_F2_4fmt */ 4362 /* nFields */ 5, 4363 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4364 /* bits */ 128, 4365 /* flags */ 0, 4366 }, 4367 #endif /* chips */ 4368 4369 #if defined(BCM_56524_A0) 4370 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56524_A0fmt */ 4371 /* format VFP_F2_4fmt */ 4372 /* nFields */ 5, 4373 /* *fields */ soc_VFP_F2_4fmt_fields, 4374 /* bits */ 128, 4375 /* flags */ 0, 4376 }, 4377 #endif /* chips */ 4378 4379 #if defined(BCM_56524_B0) 4380 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56524_B0fmt */ 4381 /* format VFP_F2_4fmt */ 4382 /* nFields */ 5, 4383 /* *fields */ soc_VFP_F2_4fmt_fields, 4384 /* bits */ 128, 4385 /* flags */ 0, 4386 }, 4387 #endif /* chips */ 4388 4389 #if defined(BCM_56560_A0) 4390 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56560_A0fmt */ 4391 /* format VFP_F2_4fmt */ 4392 /* nFields */ 5, 4393 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4394 /* bits */ 128, 4395 /* flags */ 0, 4396 }, 4397 #endif /* chips */ 4398 4399 #if defined(BCM_56560_B0) 4400 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56560_B0fmt */ 4401 /* format VFP_F2_4fmt */ 4402 /* nFields */ 5, 4403 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4404 /* bits */ 128, 4405 /* flags */ 0, 4406 }, 4407 #endif /* chips */ 4408 4409 #if defined(BCM_56624_A0) 4410 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56624_A0fmt */ 4411 /* format VFP_F2_4fmt */ 4412 /* nFields */ 5, 4413 /* *fields */ soc_VFP_F2_4fmt_fields, 4414 /* bits */ 128, 4415 /* flags */ 0, 4416 }, 4417 #endif /* chips */ 4418 4419 #if defined(BCM_56624_B0) 4420 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56624_B0fmt */ 4421 /* format VFP_F2_4fmt */ 4422 /* nFields */ 5, 4423 /* *fields */ soc_VFP_F2_4fmt_fields, 4424 /* bits */ 128, 4425 /* flags */ 0, 4426 }, 4427 #endif /* chips */ 4428 4429 #if defined(BCM_56634_A0) 4430 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56634_A0fmt */ 4431 /* format VFP_F2_4fmt */ 4432 /* nFields */ 5, 4433 /* *fields */ soc_VFP_F2_4fmt_fields, 4434 /* bits */ 128, 4435 /* flags */ 0, 4436 }, 4437 #endif /* chips */ 4438 4439 #if defined(BCM_56634_B0) 4440 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56634_B0fmt */ 4441 /* format VFP_F2_4fmt */ 4442 /* nFields */ 5, 4443 /* *fields */ soc_VFP_F2_4fmt_fields, 4444 /* bits */ 128, 4445 /* flags */ 0, 4446 }, 4447 #endif /* chips */ 4448 4449 #if defined(BCM_56640_A0) 4450 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56640_A0fmt */ 4451 /* format VFP_F2_4fmt */ 4452 /* nFields */ 5, 4453 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4454 /* bits */ 128, 4455 /* flags */ 0, 4456 }, 4457 #endif /* chips */ 4458 4459 #if defined(BCM_56670_A0) 4460 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56670_A0fmt */ 4461 /* format VFP_F2_4fmt */ 4462 /* nFields */ 5, 4463 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4464 /* bits */ 128, 4465 /* flags */ 0, 4466 }, 4467 #endif /* chips */ 4468 4469 #if defined(BCM_56670_B0) 4470 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56670_B0fmt */ 4471 /* format VFP_F2_4fmt */ 4472 /* nFields */ 5, 4473 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4474 /* bits */ 128, 4475 /* flags */ 0, 4476 }, 4477 #endif /* chips */ 4478 4479 #if defined(BCM_56685_A0) 4480 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56685_A0fmt */ 4481 /* format VFP_F2_4fmt */ 4482 /* nFields */ 5, 4483 /* *fields */ soc_VFP_F2_4fmt_fields, 4484 /* bits */ 128, 4485 /* flags */ 0, 4486 }, 4487 #endif /* chips */ 4488 4489 #if defined(BCM_56770_A0) 4490 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56770_A0fmt */ 4491 /* format VFP_F2_4fmt */ 4492 /* nFields */ 5, 4493 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4494 /* bits */ 128, 4495 /* flags */ 0, 4496 }, 4497 #endif /* chips */ 4498 4499 #if defined(BCM_56850_A0) 4500 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56850_A0fmt */ 4501 /* format VFP_F2_4fmt */ 4502 /* nFields */ 5, 4503 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4504 /* bits */ 128, 4505 /* flags */ 0, 4506 }, 4507 #endif /* chips */ 4508 4509 #if defined(BCM_56860_A0) 4510 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56860_A0fmt */ 4511 /* format VFP_F2_4fmt */ 4512 /* nFields */ 5, 4513 /* *fields */ soc_VFP_F2_4_BCM56640_A0fmt_fields, 4514 /* bits */ 128, 4515 /* flags */ 0, 4516 }, 4517 #endif /* chips */ 4518 4519 #if defined(BCM_56870_A0) 4520 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56870_A0fmt */ 4521 /* format VFP_F2_4fmt */ 4522 /* nFields */ 5, 4523 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4524 /* bits */ 128, 4525 /* flags */ 0, 4526 }, 4527 #endif /* chips */ 4528 4529 #if defined(BCM_56960_A0) 4530 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56960_A0fmt */ 4531 /* format VFP_F2_4fmt */ 4532 /* nFields */ 5, 4533 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4534 /* bits */ 128, 4535 /* flags */ 0, 4536 }, 4537 #endif /* chips */ 4538 4539 #if defined(BCM_56965_A0) 4540 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56965_A0fmt */ 4541 /* format VFP_F2_4fmt */ 4542 /* nFields */ 5, 4543 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4544 /* bits */ 128, 4545 /* flags */ 0, 4546 }, 4547 #endif /* chips */ 4548 4549 #if defined(BCM_56970_A0) 4550 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56970_A0fmt */ 4551 /* format VFP_F2_4fmt */ 4552 /* nFields */ 5, 4553 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4554 /* bits */ 128, 4555 /* flags */ 0, 4556 }, 4557 #endif /* chips */ 4558 4559 #if defined(BCM_56980_A0) 4560 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56980_A0fmt */ 4561 /* format VFP_F2_4fmt */ 4562 /* nFields */ 5, 4563 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4564 /* bits */ 128, 4565 /* flags */ 0, 4566 }, 4567 #endif /* chips */ 4568 4569 #if defined(BCM_56980_B0) 4570 { /* SOC_FORMAT_INT_VFP_F2_4_BCM56980_B0fmt */ 4571 /* format VFP_F2_4fmt */ 4572 /* nFields */ 5, 4573 /* *fields */ soc_VFP_F2_4_BCM53400_A0fmt_fields, 4574 /* bits */ 128, 4575 /* flags */ 0, 4576 }, 4577 #endif /* chips */ 4578 4579 #if defined(BCM_53400_A0) 4580 { /* SOC_FORMAT_INT_VFP_F2_5_BCM53400_A0fmt */ 4581 /* format VFP_F2_5fmt */ 4582 /* nFields */ 5, 4583 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4584 /* bits */ 128, 4585 /* flags */ 0, 4586 }, 4587 #endif /* chips */ 4588 4589 #if defined(BCM_53540_A0) 4590 { /* SOC_FORMAT_INT_VFP_F2_5_BCM53540_A0fmt */ 4591 /* format VFP_F2_5fmt */ 4592 /* nFields */ 5, 4593 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4594 /* bits */ 128, 4595 /* flags */ 0, 4596 }, 4597 #endif /* chips */ 4598 4599 #if defined(BCM_53570_A0) 4600 { /* SOC_FORMAT_INT_VFP_F2_5_BCM53570_A0fmt */ 4601 /* format VFP_F2_5fmt */ 4602 /* nFields */ 5, 4603 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4604 /* bits */ 128, 4605 /* flags */ 0, 4606 }, 4607 #endif /* chips */ 4608 4609 #if defined(BCM_53570_B0) 4610 { /* SOC_FORMAT_INT_VFP_F2_5_BCM53570_B0fmt */ 4611 /* format VFP_F2_5fmt */ 4612 /* nFields */ 5, 4613 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4614 /* bits */ 128, 4615 /* flags */ 0, 4616 }, 4617 #endif /* chips */ 4618 4619 #if defined(BCM_56150_A0) 4620 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56150_A0fmt */ 4621 /* format VFP_F2_5fmt */ 4622 /* nFields */ 5, 4623 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4624 /* bits */ 128, 4625 /* flags */ 0, 4626 }, 4627 #endif /* chips */ 4628 4629 #if defined(BCM_56160_A0) 4630 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56160_A0fmt */ 4631 /* format VFP_F2_5fmt */ 4632 /* nFields */ 5, 4633 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4634 /* bits */ 128, 4635 /* flags */ 0, 4636 }, 4637 #endif /* chips */ 4638 4639 #if defined(BCM_56260_A0) 4640 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56260_A0fmt */ 4641 /* format VFP_F2_5fmt */ 4642 /* nFields */ 5, 4643 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4644 /* bits */ 128, 4645 /* flags */ 0, 4646 }, 4647 #endif /* chips */ 4648 4649 #if defined(BCM_56260_B0) 4650 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56260_B0fmt */ 4651 /* format VFP_F2_5fmt */ 4652 /* nFields */ 5, 4653 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4654 /* bits */ 128, 4655 /* flags */ 0, 4656 }, 4657 #endif /* chips */ 4658 4659 #if defined(BCM_56270_A0) 4660 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56270_A0fmt */ 4661 /* format VFP_F2_5fmt */ 4662 /* nFields */ 5, 4663 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4664 /* bits */ 128, 4665 /* flags */ 0, 4666 }, 4667 #endif /* chips */ 4668 4669 #if defined(BCM_56340_A0) 4670 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56340_A0fmt */ 4671 /* format VFP_F2_5fmt */ 4672 /* nFields */ 5, 4673 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4674 /* bits */ 128, 4675 /* flags */ 0, 4676 }, 4677 #endif /* chips */ 4678 4679 #if defined(BCM_56370_A0) 4680 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56370_A0fmt */ 4681 /* format VFP_F2_5fmt */ 4682 /* nFields */ 5, 4683 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4684 /* bits */ 128, 4685 /* flags */ 0, 4686 }, 4687 #endif /* chips */ 4688 4689 #if defined(BCM_56440_A0) 4690 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56440_A0fmt */ 4691 /* format VFP_F2_5fmt */ 4692 /* nFields */ 5, 4693 /* *fields */ soc_VFP_F2_5fmt_fields, 4694 /* bits */ 128, 4695 /* flags */ 0, 4696 }, 4697 #endif /* chips */ 4698 4699 #if defined(BCM_56450_A0) 4700 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56450_A0fmt */ 4701 /* format VFP_F2_5fmt */ 4702 /* nFields */ 5, 4703 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4704 /* bits */ 128, 4705 /* flags */ 0, 4706 }, 4707 #endif /* chips */ 4708 4709 #if defined(BCM_56450_B0) 4710 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56450_B0fmt */ 4711 /* format VFP_F2_5fmt */ 4712 /* nFields */ 5, 4713 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4714 /* bits */ 128, 4715 /* flags */ 0, 4716 }, 4717 #endif /* chips */ 4718 4719 #if defined(BCM_56450_B1) 4720 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56450_B1fmt */ 4721 /* format VFP_F2_5fmt */ 4722 /* nFields */ 5, 4723 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4724 /* bits */ 128, 4725 /* flags */ 0, 4726 }, 4727 #endif /* chips */ 4728 4729 #if defined(BCM_56524_A0) 4730 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56524_A0fmt */ 4731 /* format VFP_F2_5fmt */ 4732 /* nFields */ 5, 4733 /* *fields */ soc_VFP_F2_5fmt_fields, 4734 /* bits */ 128, 4735 /* flags */ 0, 4736 }, 4737 #endif /* chips */ 4738 4739 #if defined(BCM_56524_B0) 4740 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56524_B0fmt */ 4741 /* format VFP_F2_5fmt */ 4742 /* nFields */ 5, 4743 /* *fields */ soc_VFP_F2_5fmt_fields, 4744 /* bits */ 128, 4745 /* flags */ 0, 4746 }, 4747 #endif /* chips */ 4748 4749 #if defined(BCM_56560_A0) 4750 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56560_A0fmt */ 4751 /* format VFP_F2_5fmt */ 4752 /* nFields */ 5, 4753 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4754 /* bits */ 128, 4755 /* flags */ 0, 4756 }, 4757 #endif /* chips */ 4758 4759 #if defined(BCM_56560_B0) 4760 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56560_B0fmt */ 4761 /* format VFP_F2_5fmt */ 4762 /* nFields */ 5, 4763 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4764 /* bits */ 128, 4765 /* flags */ 0, 4766 }, 4767 #endif /* chips */ 4768 4769 #if defined(BCM_56624_A0) 4770 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56624_A0fmt */ 4771 /* format VFP_F2_5fmt */ 4772 /* nFields */ 5, 4773 /* *fields */ soc_VFP_F2_5fmt_fields, 4774 /* bits */ 128, 4775 /* flags */ 0, 4776 }, 4777 #endif /* chips */ 4778 4779 #if defined(BCM_56624_B0) 4780 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56624_B0fmt */ 4781 /* format VFP_F2_5fmt */ 4782 /* nFields */ 5, 4783 /* *fields */ soc_VFP_F2_5fmt_fields, 4784 /* bits */ 128, 4785 /* flags */ 0, 4786 }, 4787 #endif /* chips */ 4788 4789 #if defined(BCM_56634_A0) 4790 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56634_A0fmt */ 4791 /* format VFP_F2_5fmt */ 4792 /* nFields */ 5, 4793 /* *fields */ soc_VFP_F2_5fmt_fields, 4794 /* bits */ 128, 4795 /* flags */ 0, 4796 }, 4797 #endif /* chips */ 4798 4799 #if defined(BCM_56634_B0) 4800 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56634_B0fmt */ 4801 /* format VFP_F2_5fmt */ 4802 /* nFields */ 5, 4803 /* *fields */ soc_VFP_F2_5fmt_fields, 4804 /* bits */ 128, 4805 /* flags */ 0, 4806 }, 4807 #endif /* chips */ 4808 4809 #if defined(BCM_56640_A0) 4810 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56640_A0fmt */ 4811 /* format VFP_F2_5fmt */ 4812 /* nFields */ 5, 4813 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4814 /* bits */ 128, 4815 /* flags */ 0, 4816 }, 4817 #endif /* chips */ 4818 4819 #if defined(BCM_56670_A0) 4820 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56670_A0fmt */ 4821 /* format VFP_F2_5fmt */ 4822 /* nFields */ 5, 4823 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4824 /* bits */ 128, 4825 /* flags */ 0, 4826 }, 4827 #endif /* chips */ 4828 4829 #if defined(BCM_56670_B0) 4830 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56670_B0fmt */ 4831 /* format VFP_F2_5fmt */ 4832 /* nFields */ 5, 4833 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4834 /* bits */ 128, 4835 /* flags */ 0, 4836 }, 4837 #endif /* chips */ 4838 4839 #if defined(BCM_56685_A0) 4840 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56685_A0fmt */ 4841 /* format VFP_F2_5fmt */ 4842 /* nFields */ 5, 4843 /* *fields */ soc_VFP_F2_5fmt_fields, 4844 /* bits */ 128, 4845 /* flags */ 0, 4846 }, 4847 #endif /* chips */ 4848 4849 #if defined(BCM_56770_A0) 4850 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56770_A0fmt */ 4851 /* format VFP_F2_5fmt */ 4852 /* nFields */ 5, 4853 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4854 /* bits */ 128, 4855 /* flags */ 0, 4856 }, 4857 #endif /* chips */ 4858 4859 #if defined(BCM_56850_A0) 4860 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56850_A0fmt */ 4861 /* format VFP_F2_5fmt */ 4862 /* nFields */ 5, 4863 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4864 /* bits */ 128, 4865 /* flags */ 0, 4866 }, 4867 #endif /* chips */ 4868 4869 #if defined(BCM_56860_A0) 4870 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56860_A0fmt */ 4871 /* format VFP_F2_5fmt */ 4872 /* nFields */ 5, 4873 /* *fields */ soc_VFP_F2_5_BCM56640_A0fmt_fields, 4874 /* bits */ 128, 4875 /* flags */ 0, 4876 }, 4877 #endif /* chips */ 4878 4879 #if defined(BCM_56870_A0) 4880 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56870_A0fmt */ 4881 /* format VFP_F2_5fmt */ 4882 /* nFields */ 5, 4883 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4884 /* bits */ 128, 4885 /* flags */ 0, 4886 }, 4887 #endif /* chips */ 4888 4889 #if defined(BCM_56960_A0) 4890 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56960_A0fmt */ 4891 /* format VFP_F2_5fmt */ 4892 /* nFields */ 5, 4893 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4894 /* bits */ 128, 4895 /* flags */ 0, 4896 }, 4897 #endif /* chips */ 4898 4899 #if defined(BCM_56965_A0) 4900 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56965_A0fmt */ 4901 /* format VFP_F2_5fmt */ 4902 /* nFields */ 5, 4903 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4904 /* bits */ 128, 4905 /* flags */ 0, 4906 }, 4907 #endif /* chips */ 4908 4909 #if defined(BCM_56970_A0) 4910 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56970_A0fmt */ 4911 /* format VFP_F2_5fmt */ 4912 /* nFields */ 5, 4913 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4914 /* bits */ 128, 4915 /* flags */ 0, 4916 }, 4917 #endif /* chips */ 4918 4919 #if defined(BCM_56980_A0) 4920 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56980_A0fmt */ 4921 /* format VFP_F2_5fmt */ 4922 /* nFields */ 5, 4923 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4924 /* bits */ 128, 4925 /* flags */ 0, 4926 }, 4927 #endif /* chips */ 4928 4929 #if defined(BCM_56980_B0) 4930 { /* SOC_FORMAT_INT_VFP_F2_5_BCM56980_B0fmt */ 4931 /* format VFP_F2_5fmt */ 4932 /* nFields */ 5, 4933 /* *fields */ soc_VFP_F2_5_BCM53400_A0fmt_fields, 4934 /* bits */ 128, 4935 /* flags */ 0, 4936 }, 4937 #endif /* chips */ 4938 4939 #if defined(BCM_53400_A0) 4940 { /* SOC_FORMAT_INT_VFP_F2_6_BCM53400_A0fmt */ 4941 /* format VFP_F2_6fmt */ 4942 /* nFields */ 2, 4943 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 4944 /* bits */ 128, 4945 /* flags */ 0, 4946 }, 4947 #endif /* chips */ 4948 4949 #if defined(BCM_53540_A0) 4950 { /* SOC_FORMAT_INT_VFP_F2_6_BCM53540_A0fmt */ 4951 /* format VFP_F2_6fmt */ 4952 /* nFields */ 2, 4953 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 4954 /* bits */ 128, 4955 /* flags */ 0, 4956 }, 4957 #endif /* chips */ 4958 4959 #if defined(BCM_53570_A0) 4960 { /* SOC_FORMAT_INT_VFP_F2_6_BCM53570_A0fmt */ 4961 /* format VFP_F2_6fmt */ 4962 /* nFields */ 2, 4963 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 4964 /* bits */ 128, 4965 /* flags */ 0, 4966 }, 4967 #endif /* chips */ 4968 4969 #if defined(BCM_53570_B0) 4970 { /* SOC_FORMAT_INT_VFP_F2_6_BCM53570_B0fmt */ 4971 /* format VFP_F2_6fmt */ 4972 /* nFields */ 2, 4973 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 4974 /* bits */ 128, 4975 /* flags */ 0, 4976 }, 4977 #endif /* chips */ 4978 4979 #if defined(BCM_56150_A0) 4980 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56150_A0fmt */ 4981 /* format VFP_F2_6fmt */ 4982 /* nFields */ 2, 4983 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 4984 /* bits */ 128, 4985 /* flags */ 0, 4986 }, 4987 #endif /* chips */ 4988 4989 #if defined(BCM_56160_A0) 4990 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56160_A0fmt */ 4991 /* format VFP_F2_6fmt */ 4992 /* nFields */ 2, 4993 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 4994 /* bits */ 128, 4995 /* flags */ 0, 4996 }, 4997 #endif /* chips */ 4998 4999 #if defined(BCM_56260_A0) 5000 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56260_A0fmt */ 5001 /* format VFP_F2_6fmt */ 5002 /* nFields */ 2, 5003 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5004 /* bits */ 128, 5005 /* flags */ 0, 5006 }, 5007 #endif /* chips */ 5008 5009 #if defined(BCM_56260_B0) 5010 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56260_B0fmt */ 5011 /* format VFP_F2_6fmt */ 5012 /* nFields */ 2, 5013 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5014 /* bits */ 128, 5015 /* flags */ 0, 5016 }, 5017 #endif /* chips */ 5018 5019 #if defined(BCM_56270_A0) 5020 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56270_A0fmt */ 5021 /* format VFP_F2_6fmt */ 5022 /* nFields */ 2, 5023 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5024 /* bits */ 128, 5025 /* flags */ 0, 5026 }, 5027 #endif /* chips */ 5028 5029 #if defined(BCM_56340_A0) 5030 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56340_A0fmt */ 5031 /* format VFP_F2_6fmt */ 5032 /* nFields */ 2, 5033 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 5034 /* bits */ 128, 5035 /* flags */ 0, 5036 }, 5037 #endif /* chips */ 5038 5039 #if defined(BCM_56370_A0) 5040 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56370_A0fmt */ 5041 /* format VFP_F2_6fmt */ 5042 /* nFields */ 2, 5043 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5044 /* bits */ 128, 5045 /* flags */ 0, 5046 }, 5047 #endif /* chips */ 5048 5049 #if defined(BCM_56440_A0) 5050 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56440_A0fmt */ 5051 /* format VFP_F2_6fmt */ 5052 /* nFields */ 2, 5053 /* *fields */ soc_VFP_F2_6fmt_fields, 5054 /* bits */ 128, 5055 /* flags */ 0, 5056 }, 5057 #endif /* chips */ 5058 5059 #if defined(BCM_56450_A0) 5060 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56450_A0fmt */ 5061 /* format VFP_F2_6fmt */ 5062 /* nFields */ 2, 5063 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 5064 /* bits */ 128, 5065 /* flags */ 0, 5066 }, 5067 #endif /* chips */ 5068 5069 #if defined(BCM_56450_B0) 5070 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56450_B0fmt */ 5071 /* format VFP_F2_6fmt */ 5072 /* nFields */ 2, 5073 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 5074 /* bits */ 128, 5075 /* flags */ 0, 5076 }, 5077 #endif /* chips */ 5078 5079 #if defined(BCM_56450_B1) 5080 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56450_B1fmt */ 5081 /* format VFP_F2_6fmt */ 5082 /* nFields */ 2, 5083 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 5084 /* bits */ 128, 5085 /* flags */ 0, 5086 }, 5087 #endif /* chips */ 5088 5089 #if defined(BCM_56524_A0) 5090 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56524_A0fmt */ 5091 /* format VFP_F2_6fmt */ 5092 /* nFields */ 2, 5093 /* *fields */ soc_VFP_F2_6fmt_fields, 5094 /* bits */ 128, 5095 /* flags */ 0, 5096 }, 5097 #endif /* chips */ 5098 5099 #if defined(BCM_56524_B0) 5100 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56524_B0fmt */ 5101 /* format VFP_F2_6fmt */ 5102 /* nFields */ 2, 5103 /* *fields */ soc_VFP_F2_6fmt_fields, 5104 /* bits */ 128, 5105 /* flags */ 0, 5106 }, 5107 #endif /* chips */ 5108 5109 #if defined(BCM_56560_A0) 5110 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56560_A0fmt */ 5111 /* format VFP_F2_6fmt */ 5112 /* nFields */ 2, 5113 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5114 /* bits */ 128, 5115 /* flags */ 0, 5116 }, 5117 #endif /* chips */ 5118 5119 #if defined(BCM_56560_B0) 5120 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56560_B0fmt */ 5121 /* format VFP_F2_6fmt */ 5122 /* nFields */ 2, 5123 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5124 /* bits */ 128, 5125 /* flags */ 0, 5126 }, 5127 #endif /* chips */ 5128 5129 #if defined(BCM_56624_A0) 5130 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56624_A0fmt */ 5131 /* format VFP_F2_6fmt */ 5132 /* nFields */ 2, 5133 /* *fields */ soc_VFP_F2_6fmt_fields, 5134 /* bits */ 128, 5135 /* flags */ 0, 5136 }, 5137 #endif /* chips */ 5138 5139 #if defined(BCM_56624_B0) 5140 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56624_B0fmt */ 5141 /* format VFP_F2_6fmt */ 5142 /* nFields */ 2, 5143 /* *fields */ soc_VFP_F2_6fmt_fields, 5144 /* bits */ 128, 5145 /* flags */ 0, 5146 }, 5147 #endif /* chips */ 5148 5149 #if defined(BCM_56634_A0) 5150 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56634_A0fmt */ 5151 /* format VFP_F2_6fmt */ 5152 /* nFields */ 2, 5153 /* *fields */ soc_VFP_F2_6fmt_fields, 5154 /* bits */ 128, 5155 /* flags */ 0, 5156 }, 5157 #endif /* chips */ 5158 5159 #if defined(BCM_56634_B0) 5160 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56634_B0fmt */ 5161 /* format VFP_F2_6fmt */ 5162 /* nFields */ 2, 5163 /* *fields */ soc_VFP_F2_6fmt_fields, 5164 /* bits */ 128, 5165 /* flags */ 0, 5166 }, 5167 #endif /* chips */ 5168 5169 #if defined(BCM_56640_A0) 5170 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56640_A0fmt */ 5171 /* format VFP_F2_6fmt */ 5172 /* nFields */ 2, 5173 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 5174 /* bits */ 128, 5175 /* flags */ 0, 5176 }, 5177 #endif /* chips */ 5178 5179 #if defined(BCM_56670_A0) 5180 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56670_A0fmt */ 5181 /* format VFP_F2_6fmt */ 5182 /* nFields */ 2, 5183 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5184 /* bits */ 128, 5185 /* flags */ 0, 5186 }, 5187 #endif /* chips */ 5188 5189 #if defined(BCM_56670_B0) 5190 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56670_B0fmt */ 5191 /* format VFP_F2_6fmt */ 5192 /* nFields */ 2, 5193 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5194 /* bits */ 128, 5195 /* flags */ 0, 5196 }, 5197 #endif /* chips */ 5198 5199 #if defined(BCM_56770_A0) 5200 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56770_A0fmt */ 5201 /* format VFP_F2_6fmt */ 5202 /* nFields */ 2, 5203 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5204 /* bits */ 128, 5205 /* flags */ 0, 5206 }, 5207 #endif /* chips */ 5208 5209 #if defined(BCM_56850_A0) 5210 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56850_A0fmt */ 5211 /* format VFP_F2_6fmt */ 5212 /* nFields */ 2, 5213 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 5214 /* bits */ 128, 5215 /* flags */ 0, 5216 }, 5217 #endif /* chips */ 5218 5219 #if defined(BCM_56860_A0) 5220 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56860_A0fmt */ 5221 /* format VFP_F2_6fmt */ 5222 /* nFields */ 2, 5223 /* *fields */ soc_VFP_F2_6_BCM56640_A0fmt_fields, 5224 /* bits */ 128, 5225 /* flags */ 0, 5226 }, 5227 #endif /* chips */ 5228 5229 #if defined(BCM_56870_A0) 5230 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56870_A0fmt */ 5231 /* format VFP_F2_6fmt */ 5232 /* nFields */ 2, 5233 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5234 /* bits */ 128, 5235 /* flags */ 0, 5236 }, 5237 #endif /* chips */ 5238 5239 #if defined(BCM_56960_A0) 5240 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56960_A0fmt */ 5241 /* format VFP_F2_6fmt */ 5242 /* nFields */ 2, 5243 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5244 /* bits */ 128, 5245 /* flags */ 0, 5246 }, 5247 #endif /* chips */ 5248 5249 #if defined(BCM_56965_A0) 5250 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56965_A0fmt */ 5251 /* format VFP_F2_6fmt */ 5252 /* nFields */ 2, 5253 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5254 /* bits */ 128, 5255 /* flags */ 0, 5256 }, 5257 #endif /* chips */ 5258 5259 #if defined(BCM_56970_A0) 5260 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56970_A0fmt */ 5261 /* format VFP_F2_6fmt */ 5262 /* nFields */ 2, 5263 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5264 /* bits */ 128, 5265 /* flags */ 0, 5266 }, 5267 #endif /* chips */ 5268 5269 #if defined(BCM_56980_A0) 5270 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56980_A0fmt */ 5271 /* format VFP_F2_6fmt */ 5272 /* nFields */ 2, 5273 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5274 /* bits */ 128, 5275 /* flags */ 0, 5276 }, 5277 #endif /* chips */ 5278 5279 #if defined(BCM_56980_B0) 5280 { /* SOC_FORMAT_INT_VFP_F2_6_BCM56980_B0fmt */ 5281 /* format VFP_F2_6fmt */ 5282 /* nFields */ 2, 5283 /* *fields */ soc_VFP_F2_6_BCM53400_A0fmt_fields, 5284 /* bits */ 128, 5285 /* flags */ 0, 5286 }, 5287 #endif /* chips */ 5288 5289 #if defined(BCM_53400_A0) 5290 { /* SOC_FORMAT_INT_VFP_F2_7_BCM53400_A0fmt */ 5291 /* format VFP_F2_7fmt */ 5292 /* nFields */ 5, 5293 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5294 /* bits */ 128, 5295 /* flags */ 0, 5296 }, 5297 #endif /* chips */ 5298 5299 #if defined(BCM_53540_A0) 5300 { /* SOC_FORMAT_INT_VFP_F2_7_BCM53540_A0fmt */ 5301 /* format VFP_F2_7fmt */ 5302 /* nFields */ 5, 5303 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5304 /* bits */ 128, 5305 /* flags */ 0, 5306 }, 5307 #endif /* chips */ 5308 5309 #if defined(BCM_53570_A0) 5310 { /* SOC_FORMAT_INT_VFP_F2_7_BCM53570_A0fmt */ 5311 /* format VFP_F2_7fmt */ 5312 /* nFields */ 5, 5313 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5314 /* bits */ 128, 5315 /* flags */ 0, 5316 }, 5317 #endif /* chips */ 5318 5319 #if defined(BCM_53570_B0) 5320 { /* SOC_FORMAT_INT_VFP_F2_7_BCM53570_B0fmt */ 5321 /* format VFP_F2_7fmt */ 5322 /* nFields */ 5, 5323 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5324 /* bits */ 128, 5325 /* flags */ 0, 5326 }, 5327 #endif /* chips */ 5328 5329 #if defined(BCM_56142_A0) 5330 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56142_A0fmt */ 5331 /* format VFP_F2_7fmt */ 5332 /* nFields */ 3, 5333 /* *fields */ soc_VFP_F2_7fmt_fields, 5334 /* bits */ 128, 5335 /* flags */ 0, 5336 }, 5337 #endif /* chips */ 5338 5339 #if defined(BCM_56150_A0) 5340 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56150_A0fmt */ 5341 /* format VFP_F2_7fmt */ 5342 /* nFields */ 3, 5343 /* *fields */ soc_VFP_F2_7_BCM56150_A0fmt_fields, 5344 /* bits */ 128, 5345 /* flags */ 0, 5346 }, 5347 #endif /* chips */ 5348 5349 #if defined(BCM_56160_A0) 5350 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56160_A0fmt */ 5351 /* format VFP_F2_7fmt */ 5352 /* nFields */ 5, 5353 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5354 /* bits */ 128, 5355 /* flags */ 0, 5356 }, 5357 #endif /* chips */ 5358 5359 #if defined(BCM_56260_A0) 5360 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56260_A0fmt */ 5361 /* format VFP_F2_7fmt */ 5362 /* nFields */ 7, 5363 /* *fields */ soc_VFP_F2_7_BCM56260_A0fmt_fields, 5364 /* bits */ 128, 5365 /* flags */ 0, 5366 }, 5367 #endif /* chips */ 5368 5369 #if defined(BCM_56260_B0) 5370 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56260_B0fmt */ 5371 /* format VFP_F2_7fmt */ 5372 /* nFields */ 7, 5373 /* *fields */ soc_VFP_F2_7_BCM56260_A0fmt_fields, 5374 /* bits */ 128, 5375 /* flags */ 0, 5376 }, 5377 #endif /* chips */ 5378 5379 #if defined(BCM_56270_A0) 5380 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56270_A0fmt */ 5381 /* format VFP_F2_7fmt */ 5382 /* nFields */ 7, 5383 /* *fields */ soc_VFP_F2_7_BCM56260_A0fmt_fields, 5384 /* bits */ 128, 5385 /* flags */ 0, 5386 }, 5387 #endif /* chips */ 5388 5389 #if defined(BCM_56334_A0) 5390 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56334_A0fmt */ 5391 /* format VFP_F2_7fmt */ 5392 /* nFields */ 3, 5393 /* *fields */ soc_VFP_F2_7fmt_fields, 5394 /* bits */ 128, 5395 /* flags */ 0, 5396 }, 5397 #endif /* chips */ 5398 5399 #if defined(BCM_56334_B0) 5400 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56334_B0fmt */ 5401 /* format VFP_F2_7fmt */ 5402 /* nFields */ 3, 5403 /* *fields */ soc_VFP_F2_7fmt_fields, 5404 /* bits */ 128, 5405 /* flags */ 0, 5406 }, 5407 #endif /* chips */ 5408 5409 #if defined(BCM_56340_A0) 5410 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56340_A0fmt */ 5411 /* format VFP_F2_7fmt */ 5412 /* nFields */ 5, 5413 /* *fields */ soc_VFP_F2_7_BCM56640_A0fmt_fields, 5414 /* bits */ 128, 5415 /* flags */ 0, 5416 }, 5417 #endif /* chips */ 5418 5419 #if defined(BCM_56370_A0) 5420 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56370_A0fmt */ 5421 /* format VFP_F2_7fmt */ 5422 /* nFields */ 5, 5423 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5424 /* bits */ 128, 5425 /* flags */ 0, 5426 }, 5427 #endif /* chips */ 5428 5429 #if defined(BCM_56440_A0) 5430 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56440_A0fmt */ 5431 /* format VFP_F2_7fmt */ 5432 /* nFields */ 5, 5433 /* *fields */ soc_VFP_F2_7_BCM56840_A0fmt_fields, 5434 /* bits */ 128, 5435 /* flags */ 0, 5436 }, 5437 #endif /* chips */ 5438 5439 #if defined(BCM_56440_B0) 5440 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56440_B0fmt */ 5441 /* format VFP_F2_7fmt */ 5442 /* nFields */ 5, 5443 /* *fields */ soc_VFP_F2_7_BCM56840_A0fmt_fields, 5444 /* bits */ 128, 5445 /* flags */ 0, 5446 }, 5447 #endif /* chips */ 5448 5449 #if defined(BCM_56450_A0) 5450 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56450_A0fmt */ 5451 /* format VFP_F2_7fmt */ 5452 /* nFields */ 7, 5453 /* *fields */ soc_VFP_F2_7_BCM56450_A0fmt_fields, 5454 /* bits */ 128, 5455 /* flags */ 0, 5456 }, 5457 #endif /* chips */ 5458 5459 #if defined(BCM_56450_B0) 5460 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56450_B0fmt */ 5461 /* format VFP_F2_7fmt */ 5462 /* nFields */ 7, 5463 /* *fields */ soc_VFP_F2_7_BCM56450_A0fmt_fields, 5464 /* bits */ 128, 5465 /* flags */ 0, 5466 }, 5467 #endif /* chips */ 5468 5469 #if defined(BCM_56450_B1) 5470 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56450_B1fmt */ 5471 /* format VFP_F2_7fmt */ 5472 /* nFields */ 7, 5473 /* *fields */ soc_VFP_F2_7_BCM56450_A0fmt_fields, 5474 /* bits */ 128, 5475 /* flags */ 0, 5476 }, 5477 #endif /* chips */ 5478 5479 #if defined(BCM_56524_A0) 5480 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56524_A0fmt */ 5481 /* format VFP_F2_7fmt */ 5482 /* nFields */ 3, 5483 /* *fields */ soc_VFP_F2_7fmt_fields, 5484 /* bits */ 128, 5485 /* flags */ 0, 5486 }, 5487 #endif /* chips */ 5488 5489 #if defined(BCM_56524_B0) 5490 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56524_B0fmt */ 5491 /* format VFP_F2_7fmt */ 5492 /* nFields */ 3, 5493 /* *fields */ soc_VFP_F2_7fmt_fields, 5494 /* bits */ 128, 5495 /* flags */ 0, 5496 }, 5497 #endif /* chips */ 5498 5499 #if defined(BCM_56560_A0) 5500 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56560_A0fmt */ 5501 /* format VFP_F2_7fmt */ 5502 /* nFields */ 5, 5503 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5504 /* bits */ 128, 5505 /* flags */ 0, 5506 }, 5507 #endif /* chips */ 5508 5509 #if defined(BCM_56560_B0) 5510 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56560_B0fmt */ 5511 /* format VFP_F2_7fmt */ 5512 /* nFields */ 5, 5513 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5514 /* bits */ 128, 5515 /* flags */ 0, 5516 }, 5517 #endif /* chips */ 5518 5519 #if defined(BCM_56624_A0) 5520 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56624_A0fmt */ 5521 /* format VFP_F2_7fmt */ 5522 /* nFields */ 3, 5523 /* *fields */ soc_VFP_F2_7fmt_fields, 5524 /* bits */ 128, 5525 /* flags */ 0, 5526 }, 5527 #endif /* chips */ 5528 5529 #if defined(BCM_56640_A0) 5530 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56640_A0fmt */ 5531 /* format VFP_F2_7fmt */ 5532 /* nFields */ 5, 5533 /* *fields */ soc_VFP_F2_7_BCM56640_A0fmt_fields, 5534 /* bits */ 128, 5535 /* flags */ 0, 5536 }, 5537 #endif /* chips */ 5538 5539 #if defined(BCM_56670_A0) 5540 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56670_A0fmt */ 5541 /* format VFP_F2_7fmt */ 5542 /* nFields */ 5, 5543 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5544 /* bits */ 128, 5545 /* flags */ 0, 5546 }, 5547 #endif /* chips */ 5548 5549 #if defined(BCM_56670_B0) 5550 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56670_B0fmt */ 5551 /* format VFP_F2_7fmt */ 5552 /* nFields */ 5, 5553 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5554 /* bits */ 128, 5555 /* flags */ 0, 5556 }, 5557 #endif /* chips */ 5558 5559 #if defined(BCM_56680_A0) 5560 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56680_A0fmt */ 5561 /* format VFP_F2_7fmt */ 5562 /* nFields */ 3, 5563 /* *fields */ soc_VFP_F2_7fmt_fields, 5564 /* bits */ 128, 5565 /* flags */ 0, 5566 }, 5567 #endif /* chips */ 5568 5569 #if defined(BCM_56680_B0) 5570 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56680_B0fmt */ 5571 /* format VFP_F2_7fmt */ 5572 /* nFields */ 3, 5573 /* *fields */ soc_VFP_F2_7fmt_fields, 5574 /* bits */ 128, 5575 /* flags */ 0, 5576 }, 5577 #endif /* chips */ 5578 5579 #if defined(BCM_56685_A0) 5580 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56685_A0fmt */ 5581 /* format VFP_F2_7fmt */ 5582 /* nFields */ 3, 5583 /* *fields */ soc_VFP_F2_7fmt_fields, 5584 /* bits */ 128, 5585 /* flags */ 0, 5586 }, 5587 #endif /* chips */ 5588 5589 #if defined(BCM_56685_B0) 5590 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56685_B0fmt */ 5591 /* format VFP_F2_7fmt */ 5592 /* nFields */ 3, 5593 /* *fields */ soc_VFP_F2_7fmt_fields, 5594 /* bits */ 128, 5595 /* flags */ 0, 5596 }, 5597 #endif /* chips */ 5598 5599 #if defined(BCM_56725_A0) 5600 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56725_A0fmt */ 5601 /* format VFP_F2_7fmt */ 5602 /* nFields */ 3, 5603 /* *fields */ soc_VFP_F2_7fmt_fields, 5604 /* bits */ 128, 5605 /* flags */ 0, 5606 }, 5607 #endif /* chips */ 5608 5609 #if defined(BCM_56770_A0) 5610 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56770_A0fmt */ 5611 /* format VFP_F2_7fmt */ 5612 /* nFields */ 5, 5613 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5614 /* bits */ 128, 5615 /* flags */ 0, 5616 }, 5617 #endif /* chips */ 5618 5619 #if defined(BCM_56820_A0) 5620 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56820_A0fmt */ 5621 /* format VFP_F2_7fmt */ 5622 /* nFields */ 3, 5623 /* *fields */ soc_VFP_F2_7fmt_fields, 5624 /* bits */ 128, 5625 /* flags */ 0, 5626 }, 5627 #endif /* chips */ 5628 5629 #if defined(BCM_56840_A0) 5630 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56840_A0fmt */ 5631 /* format VFP_F2_7fmt */ 5632 /* nFields */ 5, 5633 /* *fields */ soc_VFP_F2_7_BCM56840_A0fmt_fields, 5634 /* bits */ 128, 5635 /* flags */ 0, 5636 }, 5637 #endif /* chips */ 5638 5639 #if defined(BCM_56840_B0) 5640 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56840_B0fmt */ 5641 /* format VFP_F2_7fmt */ 5642 /* nFields */ 5, 5643 /* *fields */ soc_VFP_F2_7_BCM56840_A0fmt_fields, 5644 /* bits */ 128, 5645 /* flags */ 0, 5646 }, 5647 #endif /* chips */ 5648 5649 #if defined(BCM_56850_A0) 5650 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56850_A0fmt */ 5651 /* format VFP_F2_7fmt */ 5652 /* nFields */ 5, 5653 /* *fields */ soc_VFP_F2_7_BCM56640_A0fmt_fields, 5654 /* bits */ 128, 5655 /* flags */ 0, 5656 }, 5657 #endif /* chips */ 5658 5659 #if defined(BCM_56860_A0) 5660 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56860_A0fmt */ 5661 /* format VFP_F2_7fmt */ 5662 /* nFields */ 5, 5663 /* *fields */ soc_VFP_F2_7_BCM56640_A0fmt_fields, 5664 /* bits */ 128, 5665 /* flags */ 0, 5666 }, 5667 #endif /* chips */ 5668 5669 #if defined(BCM_56870_A0) 5670 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56870_A0fmt */ 5671 /* format VFP_F2_7fmt */ 5672 /* nFields */ 5, 5673 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5674 /* bits */ 128, 5675 /* flags */ 0, 5676 }, 5677 #endif /* chips */ 5678 5679 #if defined(BCM_56960_A0) 5680 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56960_A0fmt */ 5681 /* format VFP_F2_7fmt */ 5682 /* nFields */ 5, 5683 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5684 /* bits */ 128, 5685 /* flags */ 0, 5686 }, 5687 #endif /* chips */ 5688 5689 #if defined(BCM_56965_A0) 5690 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56965_A0fmt */ 5691 /* format VFP_F2_7fmt */ 5692 /* nFields */ 5, 5693 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5694 /* bits */ 128, 5695 /* flags */ 0, 5696 }, 5697 #endif /* chips */ 5698 5699 #if defined(BCM_56970_A0) 5700 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56970_A0fmt */ 5701 /* format VFP_F2_7fmt */ 5702 /* nFields */ 5, 5703 /* *fields */ soc_VFP_F2_7_BCM53400_A0fmt_fields, 5704 /* bits */ 128, 5705 /* flags */ 0, 5706 }, 5707 #endif /* chips */ 5708 5709 #if defined(BCM_56980_A0) 5710 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56980_A0fmt */ 5711 /* format VFP_F2_7fmt */ 5712 /* nFields */ 3, 5713 /* *fields */ soc_VFP_F2_7_BCM56980_A0fmt_fields, 5714 /* bits */ 128, 5715 /* flags */ 0, 5716 }, 5717 #endif /* chips */ 5718 5719 #if defined(BCM_56980_B0) 5720 { /* SOC_FORMAT_INT_VFP_F2_7_BCM56980_B0fmt */ 5721 /* format VFP_F2_7fmt */ 5722 /* nFields */ 3, 5723 /* *fields */ soc_VFP_F2_7_BCM56980_A0fmt_fields, 5724 /* bits */ 128, 5725 /* flags */ 0, 5726 }, 5727 #endif /* chips */ 5728 5729 #if defined(BCM_56260_A0) 5730 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56260_A0fmt */ 5731 /* format VFP_F2_8fmt */ 5732 /* nFields */ 1, 5733 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5734 /* bits */ 128, 5735 /* flags */ 0, 5736 }, 5737 #endif /* chips */ 5738 5739 #if defined(BCM_56260_B0) 5740 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56260_B0fmt */ 5741 /* format VFP_F2_8fmt */ 5742 /* nFields */ 1, 5743 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5744 /* bits */ 128, 5745 /* flags */ 0, 5746 }, 5747 #endif /* chips */ 5748 5749 #if defined(BCM_56270_A0) 5750 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56270_A0fmt */ 5751 /* format VFP_F2_8fmt */ 5752 /* nFields */ 1, 5753 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5754 /* bits */ 128, 5755 /* flags */ 0, 5756 }, 5757 #endif /* chips */ 5758 5759 #if defined(BCM_56340_A0) 5760 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56340_A0fmt */ 5761 /* format VFP_F2_8fmt */ 5762 /* nFields */ 1, 5763 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 5764 /* bits */ 128, 5765 /* flags */ 0, 5766 }, 5767 #endif /* chips */ 5768 5769 #if defined(BCM_56370_A0) 5770 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56370_A0fmt */ 5771 /* format VFP_F2_8fmt */ 5772 /* nFields */ 1, 5773 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5774 /* bits */ 128, 5775 /* flags */ 0, 5776 }, 5777 #endif /* chips */ 5778 5779 #if defined(BCM_56450_A0) 5780 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56450_A0fmt */ 5781 /* format VFP_F2_8fmt */ 5782 /* nFields */ 1, 5783 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 5784 /* bits */ 128, 5785 /* flags */ 0, 5786 }, 5787 #endif /* chips */ 5788 5789 #if defined(BCM_56450_B0) 5790 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56450_B0fmt */ 5791 /* format VFP_F2_8fmt */ 5792 /* nFields */ 1, 5793 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 5794 /* bits */ 128, 5795 /* flags */ 0, 5796 }, 5797 #endif /* chips */ 5798 5799 #if defined(BCM_56450_B1) 5800 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56450_B1fmt */ 5801 /* format VFP_F2_8fmt */ 5802 /* nFields */ 1, 5803 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 5804 /* bits */ 128, 5805 /* flags */ 0, 5806 }, 5807 #endif /* chips */ 5808 5809 #if defined(BCM_56560_A0) 5810 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56560_A0fmt */ 5811 /* format VFP_F2_8fmt */ 5812 /* nFields */ 1, 5813 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5814 /* bits */ 128, 5815 /* flags */ 0, 5816 }, 5817 #endif /* chips */ 5818 5819 #if defined(BCM_56560_B0) 5820 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56560_B0fmt */ 5821 /* format VFP_F2_8fmt */ 5822 /* nFields */ 1, 5823 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5824 /* bits */ 128, 5825 /* flags */ 0, 5826 }, 5827 #endif /* chips */ 5828 5829 #if defined(BCM_56670_A0) 5830 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56670_A0fmt */ 5831 /* format VFP_F2_8fmt */ 5832 /* nFields */ 1, 5833 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5834 /* bits */ 128, 5835 /* flags */ 0, 5836 }, 5837 #endif /* chips */ 5838 5839 #if defined(BCM_56670_B0) 5840 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56670_B0fmt */ 5841 /* format VFP_F2_8fmt */ 5842 /* nFields */ 1, 5843 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5844 /* bits */ 128, 5845 /* flags */ 0, 5846 }, 5847 #endif /* chips */ 5848 5849 #if defined(BCM_56770_A0) 5850 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56770_A0fmt */ 5851 /* format VFP_F2_8fmt */ 5852 /* nFields */ 1, 5853 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5854 /* bits */ 128, 5855 /* flags */ 0, 5856 }, 5857 #endif /* chips */ 5858 5859 #if defined(BCM_56850_A0) 5860 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56850_A0fmt */ 5861 /* format VFP_F2_8fmt */ 5862 /* nFields */ 1, 5863 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 5864 /* bits */ 128, 5865 /* flags */ 0, 5866 }, 5867 #endif /* chips */ 5868 5869 #if defined(BCM_56860_A0) 5870 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56860_A0fmt */ 5871 /* format VFP_F2_8fmt */ 5872 /* nFields */ 1, 5873 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 5874 /* bits */ 128, 5875 /* flags */ 0, 5876 }, 5877 #endif /* chips */ 5878 5879 #if defined(BCM_56870_A0) 5880 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56870_A0fmt */ 5881 /* format VFP_F2_8fmt */ 5882 /* nFields */ 1, 5883 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5884 /* bits */ 128, 5885 /* flags */ 0, 5886 }, 5887 #endif /* chips */ 5888 5889 #if defined(BCM_56960_A0) 5890 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56960_A0fmt */ 5891 /* format VFP_F2_8fmt */ 5892 /* nFields */ 1, 5893 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5894 /* bits */ 128, 5895 /* flags */ 0, 5896 }, 5897 #endif /* chips */ 5898 5899 #if defined(BCM_56965_A0) 5900 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56965_A0fmt */ 5901 /* format VFP_F2_8fmt */ 5902 /* nFields */ 1, 5903 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5904 /* bits */ 128, 5905 /* flags */ 0, 5906 }, 5907 #endif /* chips */ 5908 5909 #if defined(BCM_56970_A0) 5910 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56970_A0fmt */ 5911 /* format VFP_F2_8fmt */ 5912 /* nFields */ 1, 5913 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5914 /* bits */ 128, 5915 /* flags */ 0, 5916 }, 5917 #endif /* chips */ 5918 5919 #if defined(BCM_56980_A0) 5920 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56980_A0fmt */ 5921 /* format VFP_F2_8fmt */ 5922 /* nFields */ 1, 5923 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5924 /* bits */ 128, 5925 /* flags */ 0, 5926 }, 5927 #endif /* chips */ 5928 5929 #if defined(BCM_56980_B0) 5930 { /* SOC_FORMAT_INT_VFP_F2_8_BCM56980_B0fmt */ 5931 /* format VFP_F2_8fmt */ 5932 /* nFields */ 1, 5933 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 5934 /* bits */ 128, 5935 /* flags */ 0, 5936 }, 5937 #endif /* chips */ 5938 5939 #if defined(BCM_56260_A0) 5940 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56260_A0fmt */ 5941 /* format VFP_F2_9fmt */ 5942 /* nFields */ 1, 5943 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 5944 /* bits */ 128, 5945 /* flags */ 0, 5946 }, 5947 #endif /* chips */ 5948 5949 #if defined(BCM_56260_B0) 5950 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56260_B0fmt */ 5951 /* format VFP_F2_9fmt */ 5952 /* nFields */ 1, 5953 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 5954 /* bits */ 128, 5955 /* flags */ 0, 5956 }, 5957 #endif /* chips */ 5958 5959 #if defined(BCM_56270_A0) 5960 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56270_A0fmt */ 5961 /* format VFP_F2_9fmt */ 5962 /* nFields */ 1, 5963 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 5964 /* bits */ 128, 5965 /* flags */ 0, 5966 }, 5967 #endif /* chips */ 5968 5969 #if defined(BCM_56340_A0) 5970 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56340_A0fmt */ 5971 /* format VFP_F2_9fmt */ 5972 /* nFields */ 1, 5973 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 5974 /* bits */ 128, 5975 /* flags */ 0, 5976 }, 5977 #endif /* chips */ 5978 5979 #if defined(BCM_56370_A0) 5980 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56370_A0fmt */ 5981 /* format VFP_F2_9fmt */ 5982 /* nFields */ 1, 5983 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 5984 /* bits */ 128, 5985 /* flags */ 0, 5986 }, 5987 #endif /* chips */ 5988 5989 #if defined(BCM_56450_A0) 5990 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56450_A0fmt */ 5991 /* format VFP_F2_9fmt */ 5992 /* nFields */ 1, 5993 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 5994 /* bits */ 128, 5995 /* flags */ 0, 5996 }, 5997 #endif /* chips */ 5998 5999 #if defined(BCM_56450_B0) 6000 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56450_B0fmt */ 6001 /* format VFP_F2_9fmt */ 6002 /* nFields */ 1, 6003 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 6004 /* bits */ 128, 6005 /* flags */ 0, 6006 }, 6007 #endif /* chips */ 6008 6009 #if defined(BCM_56450_B1) 6010 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56450_B1fmt */ 6011 /* format VFP_F2_9fmt */ 6012 /* nFields */ 1, 6013 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 6014 /* bits */ 128, 6015 /* flags */ 0, 6016 }, 6017 #endif /* chips */ 6018 6019 #if defined(BCM_56560_A0) 6020 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56560_A0fmt */ 6021 /* format VFP_F2_9fmt */ 6022 /* nFields */ 1, 6023 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6024 /* bits */ 128, 6025 /* flags */ 0, 6026 }, 6027 #endif /* chips */ 6028 6029 #if defined(BCM_56560_B0) 6030 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56560_B0fmt */ 6031 /* format VFP_F2_9fmt */ 6032 /* nFields */ 1, 6033 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6034 /* bits */ 128, 6035 /* flags */ 0, 6036 }, 6037 #endif /* chips */ 6038 6039 #if defined(BCM_56670_A0) 6040 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56670_A0fmt */ 6041 /* format VFP_F2_9fmt */ 6042 /* nFields */ 1, 6043 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6044 /* bits */ 128, 6045 /* flags */ 0, 6046 }, 6047 #endif /* chips */ 6048 6049 #if defined(BCM_56670_B0) 6050 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56670_B0fmt */ 6051 /* format VFP_F2_9fmt */ 6052 /* nFields */ 1, 6053 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6054 /* bits */ 128, 6055 /* flags */ 0, 6056 }, 6057 #endif /* chips */ 6058 6059 #if defined(BCM_56770_A0) 6060 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56770_A0fmt */ 6061 /* format VFP_F2_9fmt */ 6062 /* nFields */ 1, 6063 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6064 /* bits */ 128, 6065 /* flags */ 0, 6066 }, 6067 #endif /* chips */ 6068 6069 #if defined(BCM_56850_A0) 6070 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56850_A0fmt */ 6071 /* format VFP_F2_9fmt */ 6072 /* nFields */ 1, 6073 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 6074 /* bits */ 128, 6075 /* flags */ 0, 6076 }, 6077 #endif /* chips */ 6078 6079 #if defined(BCM_56860_A0) 6080 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56860_A0fmt */ 6081 /* format VFP_F2_9fmt */ 6082 /* nFields */ 1, 6083 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 6084 /* bits */ 128, 6085 /* flags */ 0, 6086 }, 6087 #endif /* chips */ 6088 6089 #if defined(BCM_56870_A0) 6090 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56870_A0fmt */ 6091 /* format VFP_F2_9fmt */ 6092 /* nFields */ 1, 6093 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6094 /* bits */ 128, 6095 /* flags */ 0, 6096 }, 6097 #endif /* chips */ 6098 6099 #if defined(BCM_56960_A0) 6100 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56960_A0fmt */ 6101 /* format VFP_F2_9fmt */ 6102 /* nFields */ 1, 6103 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6104 /* bits */ 128, 6105 /* flags */ 0, 6106 }, 6107 #endif /* chips */ 6108 6109 #if defined(BCM_56965_A0) 6110 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56965_A0fmt */ 6111 /* format VFP_F2_9fmt */ 6112 /* nFields */ 1, 6113 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6114 /* bits */ 128, 6115 /* flags */ 0, 6116 }, 6117 #endif /* chips */ 6118 6119 #if defined(BCM_56970_A0) 6120 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56970_A0fmt */ 6121 /* format VFP_F2_9fmt */ 6122 /* nFields */ 1, 6123 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6124 /* bits */ 128, 6125 /* flags */ 0, 6126 }, 6127 #endif /* chips */ 6128 6129 #if defined(BCM_56980_A0) 6130 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56980_A0fmt */ 6131 /* format VFP_F2_9fmt */ 6132 /* nFields */ 1, 6133 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6134 /* bits */ 128, 6135 /* flags */ 0, 6136 }, 6137 #endif /* chips */ 6138 6139 #if defined(BCM_56980_B0) 6140 { /* SOC_FORMAT_INT_VFP_F2_9_BCM56980_B0fmt */ 6141 /* format VFP_F2_9fmt */ 6142 /* nFields */ 1, 6143 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 6144 /* bits */ 128, 6145 /* flags */ 0, 6146 }, 6147 #endif /* chips */ 6148 6149 #if defined(BCM_56514_A0) 6150 { /* SOC_FORMAT_INT_VFP_F3_0fmt */ 6151 /* format VFP_F3_0fmt */ 6152 /* nFields */ 6, 6153 /* *fields */ soc_VFP_F3_0fmt_fields, 6154 /* bits */ 24, 6155 /* flags */ 0, 6156 }, 6157 #endif /* chips */ 6158 6159 #if defined(BCM_56514_A0) 6160 { /* SOC_FORMAT_INT_VFP_F3_1fmt */ 6161 /* format VFP_F3_1fmt */ 6162 /* nFields */ 6, 6163 /* *fields */ soc_VFP_F3_1fmt_fields, 6164 /* bits */ 24, 6165 /* flags */ 0, 6166 }, 6167 #endif /* chips */ 6168 6169 #if defined(BCM_56514_A0) 6170 { /* SOC_FORMAT_INT_VFP_F3_2fmt */ 6171 /* format VFP_F3_2fmt */ 6172 /* nFields */ 6, 6173 /* *fields */ soc_VFP_F3_2fmt_fields, 6174 /* bits */ 24, 6175 /* flags */ 0, 6176 }, 6177 #endif /* chips */ 6178 6179 #if defined(BCM_56514_A0) 6180 { /* SOC_FORMAT_INT_VFP_F3_3fmt */ 6181 /* format VFP_F3_3fmt */ 6182 /* nFields */ 8, 6183 /* *fields */ soc_VFP_F3_3fmt_fields, 6184 /* bits */ 24, 6185 /* flags */ 0, 6186 }, 6187 #endif /* chips */ 6188 6189 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 6190 defined(BCM_56850_A0) || defined(BCM_56860_A0) 6191 { /* SOC_FORMAT_INT_VFP_F3_4fmt */ 6192 /* format VFP_F3_4fmt */ 6193 /* nFields */ 3, 6194 /* *fields */ soc_VFP_F3_4fmt_fields, 6195 /* bits */ 36, 6196 /* flags */ 0, 6197 }, 6198 #endif /* chips */ 6199 6200 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 6201 { /* SOC_FORMAT_INT_VFP_F3_5fmt */ 6202 /* format VFP_F3_5fmt */ 6203 /* nFields */ 5, 6204 /* *fields */ soc_VFP_F3_5fmt_fields, 6205 /* bits */ 36, 6206 /* flags */ 0, 6207 }, 6208 #endif /* chips */ 6209 6210 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 6211 { /* SOC_FORMAT_INT_VFP_F3_6fmt */ 6212 /* format VFP_F3_6fmt */ 6213 /* nFields */ 5, 6214 /* *fields */ soc_VFP_F3_6fmt_fields, 6215 /* bits */ 36, 6216 /* flags */ 0, 6217 }, 6218 #endif /* chips */ 6219 6220 #if defined(BCM_53400_A0) 6221 { /* SOC_FORMAT_INT_VFP_F3_0_BCM53400_A0fmt */ 6222 /* format VFP_F3_0fmt */ 6223 /* nFields */ 2, 6224 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6225 /* bits */ 32, 6226 /* flags */ 0, 6227 }, 6228 #endif /* chips */ 6229 6230 #if defined(BCM_53540_A0) 6231 { /* SOC_FORMAT_INT_VFP_F3_0_BCM53540_A0fmt */ 6232 /* format VFP_F3_0fmt */ 6233 /* nFields */ 2, 6234 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6235 /* bits */ 32, 6236 /* flags */ 0, 6237 }, 6238 #endif /* chips */ 6239 6240 #if defined(BCM_53570_A0) 6241 { /* SOC_FORMAT_INT_VFP_F3_0_BCM53570_A0fmt */ 6242 /* format VFP_F3_0fmt */ 6243 /* nFields */ 2, 6244 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6245 /* bits */ 32, 6246 /* flags */ 0, 6247 }, 6248 #endif /* chips */ 6249 6250 #if defined(BCM_53570_B0) 6251 { /* SOC_FORMAT_INT_VFP_F3_0_BCM53570_B0fmt */ 6252 /* format VFP_F3_0fmt */ 6253 /* nFields */ 2, 6254 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6255 /* bits */ 32, 6256 /* flags */ 0, 6257 }, 6258 #endif /* chips */ 6259 6260 #if defined(BCM_56142_A0) 6261 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56142_A0fmt */ 6262 /* format VFP_F3_0fmt */ 6263 /* nFields */ 2, 6264 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6265 /* bits */ 32, 6266 /* flags */ 0, 6267 }, 6268 #endif /* chips */ 6269 6270 #if defined(BCM_56150_A0) 6271 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56150_A0fmt */ 6272 /* format VFP_F3_0fmt */ 6273 /* nFields */ 2, 6274 /* *fields */ soc_VFP_F3_0_BCM56450_A0fmt_fields, 6275 /* bits */ 32, 6276 /* flags */ 0, 6277 }, 6278 #endif /* chips */ 6279 6280 #if defined(BCM_56160_A0) 6281 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56160_A0fmt */ 6282 /* format VFP_F3_0fmt */ 6283 /* nFields */ 2, 6284 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6285 /* bits */ 32, 6286 /* flags */ 0, 6287 }, 6288 #endif /* chips */ 6289 6290 #if defined(BCM_56260_A0) 6291 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56260_A0fmt */ 6292 /* format VFP_F3_0fmt */ 6293 /* nFields */ 2, 6294 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6295 /* bits */ 32, 6296 /* flags */ 0, 6297 }, 6298 #endif /* chips */ 6299 6300 #if defined(BCM_56260_B0) 6301 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56260_B0fmt */ 6302 /* format VFP_F3_0fmt */ 6303 /* nFields */ 2, 6304 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6305 /* bits */ 32, 6306 /* flags */ 0, 6307 }, 6308 #endif /* chips */ 6309 6310 #if defined(BCM_56270_A0) 6311 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56270_A0fmt */ 6312 /* format VFP_F3_0fmt */ 6313 /* nFields */ 2, 6314 /* *fields */ soc_VFP_F3_0_BCM53400_A0fmt_fields, 6315 /* bits */ 32, 6316 /* flags */ 0, 6317 }, 6318 #endif /* chips */ 6319 6320 #if defined(BCM_56334_A0) 6321 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56334_A0fmt */ 6322 /* format VFP_F3_0fmt */ 6323 /* nFields */ 2, 6324 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6325 /* bits */ 32, 6326 /* flags */ 0, 6327 }, 6328 #endif /* chips */ 6329 6330 #if defined(BCM_56334_B0) 6331 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56334_B0fmt */ 6332 /* format VFP_F3_0fmt */ 6333 /* nFields */ 2, 6334 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6335 /* bits */ 32, 6336 /* flags */ 0, 6337 }, 6338 #endif /* chips */ 6339 6340 #if defined(BCM_56340_A0) 6341 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56340_A0fmt */ 6342 /* format VFP_F3_0fmt */ 6343 /* nFields */ 3, 6344 /* *fields */ soc_VFP_F3_0_BCM56640_A0fmt_fields, 6345 /* bits */ 36, 6346 /* flags */ 0, 6347 }, 6348 #endif /* chips */ 6349 6350 #if defined(BCM_56370_A0) 6351 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56370_A0fmt */ 6352 /* format VFP_F3_0fmt */ 6353 /* nFields */ 3, 6354 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6355 /* bits */ 36, 6356 /* flags */ 0, 6357 }, 6358 #endif /* chips */ 6359 6360 #if defined(BCM_56440_A0) 6361 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56440_A0fmt */ 6362 /* format VFP_F3_0fmt */ 6363 /* nFields */ 2, 6364 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6365 /* bits */ 32, 6366 /* flags */ 0, 6367 }, 6368 #endif /* chips */ 6369 6370 #if defined(BCM_56440_B0) 6371 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56440_B0fmt */ 6372 /* format VFP_F3_0fmt */ 6373 /* nFields */ 2, 6374 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6375 /* bits */ 32, 6376 /* flags */ 0, 6377 }, 6378 #endif /* chips */ 6379 6380 #if defined(BCM_56450_A0) 6381 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56450_A0fmt */ 6382 /* format VFP_F3_0fmt */ 6383 /* nFields */ 2, 6384 /* *fields */ soc_VFP_F3_0_BCM56450_A0fmt_fields, 6385 /* bits */ 32, 6386 /* flags */ 0, 6387 }, 6388 #endif /* chips */ 6389 6390 #if defined(BCM_56450_B0) 6391 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56450_B0fmt */ 6392 /* format VFP_F3_0fmt */ 6393 /* nFields */ 2, 6394 /* *fields */ soc_VFP_F3_0_BCM56450_A0fmt_fields, 6395 /* bits */ 32, 6396 /* flags */ 0, 6397 }, 6398 #endif /* chips */ 6399 6400 #if defined(BCM_56450_B1) 6401 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56450_B1fmt */ 6402 /* format VFP_F3_0fmt */ 6403 /* nFields */ 2, 6404 /* *fields */ soc_VFP_F3_0_BCM56450_A0fmt_fields, 6405 /* bits */ 32, 6406 /* flags */ 0, 6407 }, 6408 #endif /* chips */ 6409 6410 #if defined(BCM_56524_A0) 6411 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56524_A0fmt */ 6412 /* format VFP_F3_0fmt */ 6413 /* nFields */ 2, 6414 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6415 /* bits */ 32, 6416 /* flags */ 0, 6417 }, 6418 #endif /* chips */ 6419 6420 #if defined(BCM_56524_B0) 6421 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56524_B0fmt */ 6422 /* format VFP_F3_0fmt */ 6423 /* nFields */ 2, 6424 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6425 /* bits */ 32, 6426 /* flags */ 0, 6427 }, 6428 #endif /* chips */ 6429 6430 #if defined(BCM_56560_A0) 6431 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56560_A0fmt */ 6432 /* format VFP_F3_0fmt */ 6433 /* nFields */ 3, 6434 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6435 /* bits */ 36, 6436 /* flags */ 0, 6437 }, 6438 #endif /* chips */ 6439 6440 #if defined(BCM_56560_B0) 6441 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56560_B0fmt */ 6442 /* format VFP_F3_0fmt */ 6443 /* nFields */ 3, 6444 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6445 /* bits */ 36, 6446 /* flags */ 0, 6447 }, 6448 #endif /* chips */ 6449 6450 #if defined(BCM_56624_A0) 6451 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56624_A0fmt */ 6452 /* format VFP_F3_0fmt */ 6453 /* nFields */ 2, 6454 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6455 /* bits */ 32, 6456 /* flags */ 0, 6457 }, 6458 #endif /* chips */ 6459 6460 #if defined(BCM_56624_B0) 6461 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56624_B0fmt */ 6462 /* format VFP_F3_0fmt */ 6463 /* nFields */ 2, 6464 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6465 /* bits */ 32, 6466 /* flags */ 0, 6467 }, 6468 #endif /* chips */ 6469 6470 #if defined(BCM_56634_A0) 6471 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56634_A0fmt */ 6472 /* format VFP_F3_0fmt */ 6473 /* nFields */ 2, 6474 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6475 /* bits */ 32, 6476 /* flags */ 0, 6477 }, 6478 #endif /* chips */ 6479 6480 #if defined(BCM_56634_B0) 6481 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56634_B0fmt */ 6482 /* format VFP_F3_0fmt */ 6483 /* nFields */ 2, 6484 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6485 /* bits */ 32, 6486 /* flags */ 0, 6487 }, 6488 #endif /* chips */ 6489 6490 #if defined(BCM_56640_A0) 6491 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56640_A0fmt */ 6492 /* format VFP_F3_0fmt */ 6493 /* nFields */ 3, 6494 /* *fields */ soc_VFP_F3_0_BCM56640_A0fmt_fields, 6495 /* bits */ 36, 6496 /* flags */ 0, 6497 }, 6498 #endif /* chips */ 6499 6500 #if defined(BCM_56670_A0) 6501 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56670_A0fmt */ 6502 /* format VFP_F3_0fmt */ 6503 /* nFields */ 3, 6504 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6505 /* bits */ 36, 6506 /* flags */ 0, 6507 }, 6508 #endif /* chips */ 6509 6510 #if defined(BCM_56670_B0) 6511 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56670_B0fmt */ 6512 /* format VFP_F3_0fmt */ 6513 /* nFields */ 3, 6514 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6515 /* bits */ 36, 6516 /* flags */ 0, 6517 }, 6518 #endif /* chips */ 6519 6520 #if defined(BCM_56680_A0) 6521 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56680_A0fmt */ 6522 /* format VFP_F3_0fmt */ 6523 /* nFields */ 2, 6524 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6525 /* bits */ 32, 6526 /* flags */ 0, 6527 }, 6528 #endif /* chips */ 6529 6530 #if defined(BCM_56680_B0) 6531 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56680_B0fmt */ 6532 /* format VFP_F3_0fmt */ 6533 /* nFields */ 2, 6534 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6535 /* bits */ 32, 6536 /* flags */ 0, 6537 }, 6538 #endif /* chips */ 6539 6540 #if defined(BCM_56685_A0) 6541 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56685_A0fmt */ 6542 /* format VFP_F3_0fmt */ 6543 /* nFields */ 2, 6544 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6545 /* bits */ 32, 6546 /* flags */ 0, 6547 }, 6548 #endif /* chips */ 6549 6550 #if defined(BCM_56685_B0) 6551 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56685_B0fmt */ 6552 /* format VFP_F3_0fmt */ 6553 /* nFields */ 2, 6554 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6555 /* bits */ 32, 6556 /* flags */ 0, 6557 }, 6558 #endif /* chips */ 6559 6560 #if defined(BCM_56725_A0) 6561 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56725_A0fmt */ 6562 /* format VFP_F3_0fmt */ 6563 /* nFields */ 2, 6564 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6565 /* bits */ 32, 6566 /* flags */ 0, 6567 }, 6568 #endif /* chips */ 6569 6570 #if defined(BCM_56770_A0) 6571 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56770_A0fmt */ 6572 /* format VFP_F3_0fmt */ 6573 /* nFields */ 3, 6574 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6575 /* bits */ 36, 6576 /* flags */ 0, 6577 }, 6578 #endif /* chips */ 6579 6580 #if defined(BCM_56820_A0) 6581 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56820_A0fmt */ 6582 /* format VFP_F3_0fmt */ 6583 /* nFields */ 2, 6584 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6585 /* bits */ 32, 6586 /* flags */ 0, 6587 }, 6588 #endif /* chips */ 6589 6590 #if defined(BCM_56840_A0) 6591 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56840_A0fmt */ 6592 /* format VFP_F3_0fmt */ 6593 /* nFields */ 2, 6594 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6595 /* bits */ 32, 6596 /* flags */ 0, 6597 }, 6598 #endif /* chips */ 6599 6600 #if defined(BCM_56840_B0) 6601 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56840_B0fmt */ 6602 /* format VFP_F3_0fmt */ 6603 /* nFields */ 2, 6604 /* *fields */ soc_VFP_F3_0_BCM56624_A0fmt_fields, 6605 /* bits */ 32, 6606 /* flags */ 0, 6607 }, 6608 #endif /* chips */ 6609 6610 #if defined(BCM_56850_A0) 6611 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56850_A0fmt */ 6612 /* format VFP_F3_0fmt */ 6613 /* nFields */ 3, 6614 /* *fields */ soc_VFP_F3_0_BCM56640_A0fmt_fields, 6615 /* bits */ 36, 6616 /* flags */ 0, 6617 }, 6618 #endif /* chips */ 6619 6620 #if defined(BCM_56860_A0) 6621 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56860_A0fmt */ 6622 /* format VFP_F3_0fmt */ 6623 /* nFields */ 3, 6624 /* *fields */ soc_VFP_F3_0_BCM56640_A0fmt_fields, 6625 /* bits */ 36, 6626 /* flags */ 0, 6627 }, 6628 #endif /* chips */ 6629 6630 #if defined(BCM_56870_A0) 6631 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56870_A0fmt */ 6632 /* format VFP_F3_0fmt */ 6633 /* nFields */ 3, 6634 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6635 /* bits */ 36, 6636 /* flags */ 0, 6637 }, 6638 #endif /* chips */ 6639 6640 #if defined(BCM_56960_A0) 6641 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56960_A0fmt */ 6642 /* format VFP_F3_0fmt */ 6643 /* nFields */ 3, 6644 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6645 /* bits */ 36, 6646 /* flags */ 0, 6647 }, 6648 #endif /* chips */ 6649 6650 #if defined(BCM_56965_A0) 6651 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56965_A0fmt */ 6652 /* format VFP_F3_0fmt */ 6653 /* nFields */ 3, 6654 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6655 /* bits */ 36, 6656 /* flags */ 0, 6657 }, 6658 #endif /* chips */ 6659 6660 #if defined(BCM_56970_A0) 6661 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56970_A0fmt */ 6662 /* format VFP_F3_0fmt */ 6663 /* nFields */ 3, 6664 /* *fields */ soc_VFP_F3_0_BCM56960_A0fmt_fields, 6665 /* bits */ 36, 6666 /* flags */ 0, 6667 }, 6668 #endif /* chips */ 6669 6670 #if defined(BCM_56980_A0) 6671 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56980_A0fmt */ 6672 /* format VFP_F3_0fmt */ 6673 /* nFields */ 2, 6674 /* *fields */ soc_VFP_F3_0_BCM56980_A0fmt_fields, 6675 /* bits */ 36, 6676 /* flags */ 0, 6677 }, 6678 #endif /* chips */ 6679 6680 #if defined(BCM_56980_B0) 6681 { /* SOC_FORMAT_INT_VFP_F3_0_BCM56980_B0fmt */ 6682 /* format VFP_F3_0fmt */ 6683 /* nFields */ 2, 6684 /* *fields */ soc_VFP_F3_0_BCM56980_A0fmt_fields, 6685 /* bits */ 36, 6686 /* flags */ 0, 6687 }, 6688 #endif /* chips */ 6689 6690 #if defined(BCM_53400_A0) 6691 { /* SOC_FORMAT_INT_VFP_F3_1_BCM53400_A0fmt */ 6692 /* format VFP_F3_1fmt */ 6693 /* nFields */ 2, 6694 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6695 /* bits */ 32, 6696 /* flags */ 0, 6697 }, 6698 #endif /* chips */ 6699 6700 #if defined(BCM_53540_A0) 6701 { /* SOC_FORMAT_INT_VFP_F3_1_BCM53540_A0fmt */ 6702 /* format VFP_F3_1fmt */ 6703 /* nFields */ 2, 6704 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6705 /* bits */ 32, 6706 /* flags */ 0, 6707 }, 6708 #endif /* chips */ 6709 6710 #if defined(BCM_53570_A0) 6711 { /* SOC_FORMAT_INT_VFP_F3_1_BCM53570_A0fmt */ 6712 /* format VFP_F3_1fmt */ 6713 /* nFields */ 2, 6714 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6715 /* bits */ 32, 6716 /* flags */ 0, 6717 }, 6718 #endif /* chips */ 6719 6720 #if defined(BCM_53570_B0) 6721 { /* SOC_FORMAT_INT_VFP_F3_1_BCM53570_B0fmt */ 6722 /* format VFP_F3_1fmt */ 6723 /* nFields */ 2, 6724 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6725 /* bits */ 32, 6726 /* flags */ 0, 6727 }, 6728 #endif /* chips */ 6729 6730 #if defined(BCM_56142_A0) 6731 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56142_A0fmt */ 6732 /* format VFP_F3_1fmt */ 6733 /* nFields */ 2, 6734 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6735 /* bits */ 32, 6736 /* flags */ 0, 6737 }, 6738 #endif /* chips */ 6739 6740 #if defined(BCM_56150_A0) 6741 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56150_A0fmt */ 6742 /* format VFP_F3_1fmt */ 6743 /* nFields */ 2, 6744 /* *fields */ soc_VFP_F3_1_BCM56450_A0fmt_fields, 6745 /* bits */ 32, 6746 /* flags */ 0, 6747 }, 6748 #endif /* chips */ 6749 6750 #if defined(BCM_56160_A0) 6751 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56160_A0fmt */ 6752 /* format VFP_F3_1fmt */ 6753 /* nFields */ 2, 6754 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6755 /* bits */ 32, 6756 /* flags */ 0, 6757 }, 6758 #endif /* chips */ 6759 6760 #if defined(BCM_56260_A0) 6761 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56260_A0fmt */ 6762 /* format VFP_F3_1fmt */ 6763 /* nFields */ 2, 6764 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6765 /* bits */ 32, 6766 /* flags */ 0, 6767 }, 6768 #endif /* chips */ 6769 6770 #if defined(BCM_56260_B0) 6771 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56260_B0fmt */ 6772 /* format VFP_F3_1fmt */ 6773 /* nFields */ 2, 6774 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6775 /* bits */ 32, 6776 /* flags */ 0, 6777 }, 6778 #endif /* chips */ 6779 6780 #if defined(BCM_56270_A0) 6781 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56270_A0fmt */ 6782 /* format VFP_F3_1fmt */ 6783 /* nFields */ 2, 6784 /* *fields */ soc_VFP_F3_1_BCM53400_A0fmt_fields, 6785 /* bits */ 32, 6786 /* flags */ 0, 6787 }, 6788 #endif /* chips */ 6789 6790 #if defined(BCM_56334_A0) 6791 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56334_A0fmt */ 6792 /* format VFP_F3_1fmt */ 6793 /* nFields */ 2, 6794 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6795 /* bits */ 32, 6796 /* flags */ 0, 6797 }, 6798 #endif /* chips */ 6799 6800 #if defined(BCM_56334_B0) 6801 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56334_B0fmt */ 6802 /* format VFP_F3_1fmt */ 6803 /* nFields */ 2, 6804 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6805 /* bits */ 32, 6806 /* flags */ 0, 6807 }, 6808 #endif /* chips */ 6809 6810 #if defined(BCM_56340_A0) 6811 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56340_A0fmt */ 6812 /* format VFP_F3_1fmt */ 6813 /* nFields */ 3, 6814 /* *fields */ soc_VFP_F3_1_BCM56640_A0fmt_fields, 6815 /* bits */ 36, 6816 /* flags */ 0, 6817 }, 6818 #endif /* chips */ 6819 6820 #if defined(BCM_56370_A0) 6821 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56370_A0fmt */ 6822 /* format VFP_F3_1fmt */ 6823 /* nFields */ 3, 6824 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 6825 /* bits */ 36, 6826 /* flags */ 0, 6827 }, 6828 #endif /* chips */ 6829 6830 #if defined(BCM_56440_A0) 6831 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56440_A0fmt */ 6832 /* format VFP_F3_1fmt */ 6833 /* nFields */ 2, 6834 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6835 /* bits */ 32, 6836 /* flags */ 0, 6837 }, 6838 #endif /* chips */ 6839 6840 #if defined(BCM_56440_B0) 6841 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56440_B0fmt */ 6842 /* format VFP_F3_1fmt */ 6843 /* nFields */ 2, 6844 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6845 /* bits */ 32, 6846 /* flags */ 0, 6847 }, 6848 #endif /* chips */ 6849 6850 #if defined(BCM_56450_A0) 6851 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56450_A0fmt */ 6852 /* format VFP_F3_1fmt */ 6853 /* nFields */ 2, 6854 /* *fields */ soc_VFP_F3_1_BCM56450_A0fmt_fields, 6855 /* bits */ 32, 6856 /* flags */ 0, 6857 }, 6858 #endif /* chips */ 6859 6860 #if defined(BCM_56450_B0) 6861 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56450_B0fmt */ 6862 /* format VFP_F3_1fmt */ 6863 /* nFields */ 2, 6864 /* *fields */ soc_VFP_F3_1_BCM56450_A0fmt_fields, 6865 /* bits */ 32, 6866 /* flags */ 0, 6867 }, 6868 #endif /* chips */ 6869 6870 #if defined(BCM_56450_B1) 6871 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56450_B1fmt */ 6872 /* format VFP_F3_1fmt */ 6873 /* nFields */ 2, 6874 /* *fields */ soc_VFP_F3_1_BCM56450_A0fmt_fields, 6875 /* bits */ 32, 6876 /* flags */ 0, 6877 }, 6878 #endif /* chips */ 6879 6880 #if defined(BCM_56524_A0) 6881 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56524_A0fmt */ 6882 /* format VFP_F3_1fmt */ 6883 /* nFields */ 2, 6884 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6885 /* bits */ 32, 6886 /* flags */ 0, 6887 }, 6888 #endif /* chips */ 6889 6890 #if defined(BCM_56524_B0) 6891 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56524_B0fmt */ 6892 /* format VFP_F3_1fmt */ 6893 /* nFields */ 2, 6894 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6895 /* bits */ 32, 6896 /* flags */ 0, 6897 }, 6898 #endif /* chips */ 6899 6900 #if defined(BCM_56560_A0) 6901 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56560_A0fmt */ 6902 /* format VFP_F3_1fmt */ 6903 /* nFields */ 3, 6904 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 6905 /* bits */ 36, 6906 /* flags */ 0, 6907 }, 6908 #endif /* chips */ 6909 6910 #if defined(BCM_56560_B0) 6911 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56560_B0fmt */ 6912 /* format VFP_F3_1fmt */ 6913 /* nFields */ 3, 6914 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 6915 /* bits */ 36, 6916 /* flags */ 0, 6917 }, 6918 #endif /* chips */ 6919 6920 #if defined(BCM_56624_A0) 6921 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56624_A0fmt */ 6922 /* format VFP_F3_1fmt */ 6923 /* nFields */ 2, 6924 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6925 /* bits */ 32, 6926 /* flags */ 0, 6927 }, 6928 #endif /* chips */ 6929 6930 #if defined(BCM_56624_B0) 6931 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56624_B0fmt */ 6932 /* format VFP_F3_1fmt */ 6933 /* nFields */ 2, 6934 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6935 /* bits */ 32, 6936 /* flags */ 0, 6937 }, 6938 #endif /* chips */ 6939 6940 #if defined(BCM_56634_A0) 6941 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56634_A0fmt */ 6942 /* format VFP_F3_1fmt */ 6943 /* nFields */ 2, 6944 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6945 /* bits */ 32, 6946 /* flags */ 0, 6947 }, 6948 #endif /* chips */ 6949 6950 #if defined(BCM_56634_B0) 6951 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56634_B0fmt */ 6952 /* format VFP_F3_1fmt */ 6953 /* nFields */ 2, 6954 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6955 /* bits */ 32, 6956 /* flags */ 0, 6957 }, 6958 #endif /* chips */ 6959 6960 #if defined(BCM_56640_A0) 6961 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56640_A0fmt */ 6962 /* format VFP_F3_1fmt */ 6963 /* nFields */ 3, 6964 /* *fields */ soc_VFP_F3_1_BCM56640_A0fmt_fields, 6965 /* bits */ 36, 6966 /* flags */ 0, 6967 }, 6968 #endif /* chips */ 6969 6970 #if defined(BCM_56670_A0) 6971 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56670_A0fmt */ 6972 /* format VFP_F3_1fmt */ 6973 /* nFields */ 3, 6974 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 6975 /* bits */ 36, 6976 /* flags */ 0, 6977 }, 6978 #endif /* chips */ 6979 6980 #if defined(BCM_56670_B0) 6981 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56670_B0fmt */ 6982 /* format VFP_F3_1fmt */ 6983 /* nFields */ 3, 6984 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 6985 /* bits */ 36, 6986 /* flags */ 0, 6987 }, 6988 #endif /* chips */ 6989 6990 #if defined(BCM_56680_A0) 6991 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56680_A0fmt */ 6992 /* format VFP_F3_1fmt */ 6993 /* nFields */ 2, 6994 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 6995 /* bits */ 32, 6996 /* flags */ 0, 6997 }, 6998 #endif /* chips */ 6999 7000 #if defined(BCM_56680_B0) 7001 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56680_B0fmt */ 7002 /* format VFP_F3_1fmt */ 7003 /* nFields */ 2, 7004 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 7005 /* bits */ 32, 7006 /* flags */ 0, 7007 }, 7008 #endif /* chips */ 7009 7010 #if defined(BCM_56685_A0) 7011 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56685_A0fmt */ 7012 /* format VFP_F3_1fmt */ 7013 /* nFields */ 2, 7014 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 7015 /* bits */ 32, 7016 /* flags */ 0, 7017 }, 7018 #endif /* chips */ 7019 7020 #if defined(BCM_56685_B0) 7021 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56685_B0fmt */ 7022 /* format VFP_F3_1fmt */ 7023 /* nFields */ 2, 7024 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 7025 /* bits */ 32, 7026 /* flags */ 0, 7027 }, 7028 #endif /* chips */ 7029 7030 #if defined(BCM_56725_A0) 7031 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56725_A0fmt */ 7032 /* format VFP_F3_1fmt */ 7033 /* nFields */ 2, 7034 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 7035 /* bits */ 32, 7036 /* flags */ 0, 7037 }, 7038 #endif /* chips */ 7039 7040 #if defined(BCM_56770_A0) 7041 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56770_A0fmt */ 7042 /* format VFP_F3_1fmt */ 7043 /* nFields */ 3, 7044 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 7045 /* bits */ 36, 7046 /* flags */ 0, 7047 }, 7048 #endif /* chips */ 7049 7050 #if defined(BCM_56820_A0) 7051 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56820_A0fmt */ 7052 /* format VFP_F3_1fmt */ 7053 /* nFields */ 2, 7054 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 7055 /* bits */ 32, 7056 /* flags */ 0, 7057 }, 7058 #endif /* chips */ 7059 7060 #if defined(BCM_56840_A0) 7061 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56840_A0fmt */ 7062 /* format VFP_F3_1fmt */ 7063 /* nFields */ 2, 7064 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 7065 /* bits */ 32, 7066 /* flags */ 0, 7067 }, 7068 #endif /* chips */ 7069 7070 #if defined(BCM_56840_B0) 7071 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56840_B0fmt */ 7072 /* format VFP_F3_1fmt */ 7073 /* nFields */ 2, 7074 /* *fields */ soc_VFP_F3_1_BCM56624_A0fmt_fields, 7075 /* bits */ 32, 7076 /* flags */ 0, 7077 }, 7078 #endif /* chips */ 7079 7080 #if defined(BCM_56850_A0) 7081 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56850_A0fmt */ 7082 /* format VFP_F3_1fmt */ 7083 /* nFields */ 3, 7084 /* *fields */ soc_VFP_F3_1_BCM56640_A0fmt_fields, 7085 /* bits */ 36, 7086 /* flags */ 0, 7087 }, 7088 #endif /* chips */ 7089 7090 #if defined(BCM_56860_A0) 7091 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56860_A0fmt */ 7092 /* format VFP_F3_1fmt */ 7093 /* nFields */ 5, 7094 /* *fields */ soc_VFP_F3_1_BCM56860_A0fmt_fields, 7095 /* bits */ 36, 7096 /* flags */ 0, 7097 }, 7098 #endif /* chips */ 7099 7100 #if defined(BCM_56870_A0) 7101 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56870_A0fmt */ 7102 /* format VFP_F3_1fmt */ 7103 /* nFields */ 3, 7104 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 7105 /* bits */ 36, 7106 /* flags */ 0, 7107 }, 7108 #endif /* chips */ 7109 7110 #if defined(BCM_56960_A0) 7111 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56960_A0fmt */ 7112 /* format VFP_F3_1fmt */ 7113 /* nFields */ 3, 7114 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 7115 /* bits */ 36, 7116 /* flags */ 0, 7117 }, 7118 #endif /* chips */ 7119 7120 #if defined(BCM_56965_A0) 7121 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56965_A0fmt */ 7122 /* format VFP_F3_1fmt */ 7123 /* nFields */ 3, 7124 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 7125 /* bits */ 36, 7126 /* flags */ 0, 7127 }, 7128 #endif /* chips */ 7129 7130 #if defined(BCM_56970_A0) 7131 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56970_A0fmt */ 7132 /* format VFP_F3_1fmt */ 7133 /* nFields */ 3, 7134 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 7135 /* bits */ 36, 7136 /* flags */ 0, 7137 }, 7138 #endif /* chips */ 7139 7140 #if defined(BCM_56980_A0) 7141 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56980_A0fmt */ 7142 /* format VFP_F3_1fmt */ 7143 /* nFields */ 3, 7144 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 7145 /* bits */ 36, 7146 /* flags */ 0, 7147 }, 7148 #endif /* chips */ 7149 7150 #if defined(BCM_56980_B0) 7151 { /* SOC_FORMAT_INT_VFP_F3_1_BCM56980_B0fmt */ 7152 /* format VFP_F3_1fmt */ 7153 /* nFields */ 3, 7154 /* *fields */ soc_VFP_F3_1_BCM56960_A0fmt_fields, 7155 /* bits */ 36, 7156 /* flags */ 0, 7157 }, 7158 #endif /* chips */ 7159 7160 #if defined(BCM_53400_A0) 7161 { /* SOC_FORMAT_INT_VFP_F3_2_BCM53400_A0fmt */ 7162 /* format VFP_F3_2fmt */ 7163 /* nFields */ 4, 7164 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7165 /* bits */ 32, 7166 /* flags */ 0, 7167 }, 7168 #endif /* chips */ 7169 7170 #if defined(BCM_53540_A0) 7171 { /* SOC_FORMAT_INT_VFP_F3_2_BCM53540_A0fmt */ 7172 /* format VFP_F3_2fmt */ 7173 /* nFields */ 4, 7174 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7175 /* bits */ 32, 7176 /* flags */ 0, 7177 }, 7178 #endif /* chips */ 7179 7180 #if defined(BCM_53570_A0) 7181 { /* SOC_FORMAT_INT_VFP_F3_2_BCM53570_A0fmt */ 7182 /* format VFP_F3_2fmt */ 7183 /* nFields */ 4, 7184 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7185 /* bits */ 32, 7186 /* flags */ 0, 7187 }, 7188 #endif /* chips */ 7189 7190 #if defined(BCM_53570_B0) 7191 { /* SOC_FORMAT_INT_VFP_F3_2_BCM53570_B0fmt */ 7192 /* format VFP_F3_2fmt */ 7193 /* nFields */ 4, 7194 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7195 /* bits */ 32, 7196 /* flags */ 0, 7197 }, 7198 #endif /* chips */ 7199 7200 #if defined(BCM_56142_A0) 7201 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56142_A0fmt */ 7202 /* format VFP_F3_2fmt */ 7203 /* nFields */ 4, 7204 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7205 /* bits */ 32, 7206 /* flags */ 0, 7207 }, 7208 #endif /* chips */ 7209 7210 #if defined(BCM_56150_A0) 7211 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56150_A0fmt */ 7212 /* format VFP_F3_2fmt */ 7213 /* nFields */ 4, 7214 /* *fields */ soc_VFP_F3_2_BCM56450_A0fmt_fields, 7215 /* bits */ 32, 7216 /* flags */ 0, 7217 }, 7218 #endif /* chips */ 7219 7220 #if defined(BCM_56160_A0) 7221 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56160_A0fmt */ 7222 /* format VFP_F3_2fmt */ 7223 /* nFields */ 4, 7224 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7225 /* bits */ 32, 7226 /* flags */ 0, 7227 }, 7228 #endif /* chips */ 7229 7230 #if defined(BCM_56260_A0) 7231 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56260_A0fmt */ 7232 /* format VFP_F3_2fmt */ 7233 /* nFields */ 4, 7234 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7235 /* bits */ 32, 7236 /* flags */ 0, 7237 }, 7238 #endif /* chips */ 7239 7240 #if defined(BCM_56260_B0) 7241 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56260_B0fmt */ 7242 /* format VFP_F3_2fmt */ 7243 /* nFields */ 4, 7244 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7245 /* bits */ 32, 7246 /* flags */ 0, 7247 }, 7248 #endif /* chips */ 7249 7250 #if defined(BCM_56270_A0) 7251 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56270_A0fmt */ 7252 /* format VFP_F3_2fmt */ 7253 /* nFields */ 4, 7254 /* *fields */ soc_VFP_F3_2_BCM53400_A0fmt_fields, 7255 /* bits */ 32, 7256 /* flags */ 0, 7257 }, 7258 #endif /* chips */ 7259 7260 #if defined(BCM_56334_A0) 7261 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56334_A0fmt */ 7262 /* format VFP_F3_2fmt */ 7263 /* nFields */ 4, 7264 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7265 /* bits */ 32, 7266 /* flags */ 0, 7267 }, 7268 #endif /* chips */ 7269 7270 #if defined(BCM_56334_B0) 7271 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56334_B0fmt */ 7272 /* format VFP_F3_2fmt */ 7273 /* nFields */ 4, 7274 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7275 /* bits */ 32, 7276 /* flags */ 0, 7277 }, 7278 #endif /* chips */ 7279 7280 #if defined(BCM_56340_A0) 7281 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56340_A0fmt */ 7282 /* format VFP_F3_2fmt */ 7283 /* nFields */ 5, 7284 /* *fields */ soc_VFP_F3_2_BCM56640_A0fmt_fields, 7285 /* bits */ 36, 7286 /* flags */ 0, 7287 }, 7288 #endif /* chips */ 7289 7290 #if defined(BCM_56370_A0) 7291 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56370_A0fmt */ 7292 /* format VFP_F3_2fmt */ 7293 /* nFields */ 5, 7294 /* *fields */ soc_VFP_F3_2_BCM56870_A0fmt_fields, 7295 /* bits */ 36, 7296 /* flags */ 0, 7297 }, 7298 #endif /* chips */ 7299 7300 #if defined(BCM_56440_A0) 7301 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56440_A0fmt */ 7302 /* format VFP_F3_2fmt */ 7303 /* nFields */ 4, 7304 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7305 /* bits */ 32, 7306 /* flags */ 0, 7307 }, 7308 #endif /* chips */ 7309 7310 #if defined(BCM_56440_B0) 7311 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56440_B0fmt */ 7312 /* format VFP_F3_2fmt */ 7313 /* nFields */ 4, 7314 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7315 /* bits */ 32, 7316 /* flags */ 0, 7317 }, 7318 #endif /* chips */ 7319 7320 #if defined(BCM_56450_A0) 7321 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56450_A0fmt */ 7322 /* format VFP_F3_2fmt */ 7323 /* nFields */ 4, 7324 /* *fields */ soc_VFP_F3_2_BCM56450_A0fmt_fields, 7325 /* bits */ 32, 7326 /* flags */ 0, 7327 }, 7328 #endif /* chips */ 7329 7330 #if defined(BCM_56450_B0) 7331 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56450_B0fmt */ 7332 /* format VFP_F3_2fmt */ 7333 /* nFields */ 4, 7334 /* *fields */ soc_VFP_F3_2_BCM56450_A0fmt_fields, 7335 /* bits */ 32, 7336 /* flags */ 0, 7337 }, 7338 #endif /* chips */ 7339 7340 #if defined(BCM_56450_B1) 7341 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56450_B1fmt */ 7342 /* format VFP_F3_2fmt */ 7343 /* nFields */ 4, 7344 /* *fields */ soc_VFP_F3_2_BCM56450_A0fmt_fields, 7345 /* bits */ 32, 7346 /* flags */ 0, 7347 }, 7348 #endif /* chips */ 7349 7350 #if defined(BCM_56524_A0) 7351 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56524_A0fmt */ 7352 /* format VFP_F3_2fmt */ 7353 /* nFields */ 4, 7354 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7355 /* bits */ 32, 7356 /* flags */ 0, 7357 }, 7358 #endif /* chips */ 7359 7360 #if defined(BCM_56524_B0) 7361 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56524_B0fmt */ 7362 /* format VFP_F3_2fmt */ 7363 /* nFields */ 4, 7364 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7365 /* bits */ 32, 7366 /* flags */ 0, 7367 }, 7368 #endif /* chips */ 7369 7370 #if defined(BCM_56560_A0) 7371 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56560_A0fmt */ 7372 /* format VFP_F3_2fmt */ 7373 /* nFields */ 5, 7374 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7375 /* bits */ 36, 7376 /* flags */ 0, 7377 }, 7378 #endif /* chips */ 7379 7380 #if defined(BCM_56560_B0) 7381 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56560_B0fmt */ 7382 /* format VFP_F3_2fmt */ 7383 /* nFields */ 5, 7384 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7385 /* bits */ 36, 7386 /* flags */ 0, 7387 }, 7388 #endif /* chips */ 7389 7390 #if defined(BCM_56624_A0) 7391 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56624_A0fmt */ 7392 /* format VFP_F3_2fmt */ 7393 /* nFields */ 4, 7394 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7395 /* bits */ 32, 7396 /* flags */ 0, 7397 }, 7398 #endif /* chips */ 7399 7400 #if defined(BCM_56624_B0) 7401 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56624_B0fmt */ 7402 /* format VFP_F3_2fmt */ 7403 /* nFields */ 4, 7404 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7405 /* bits */ 32, 7406 /* flags */ 0, 7407 }, 7408 #endif /* chips */ 7409 7410 #if defined(BCM_56634_A0) 7411 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56634_A0fmt */ 7412 /* format VFP_F3_2fmt */ 7413 /* nFields */ 4, 7414 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7415 /* bits */ 32, 7416 /* flags */ 0, 7417 }, 7418 #endif /* chips */ 7419 7420 #if defined(BCM_56634_B0) 7421 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56634_B0fmt */ 7422 /* format VFP_F3_2fmt */ 7423 /* nFields */ 4, 7424 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7425 /* bits */ 32, 7426 /* flags */ 0, 7427 }, 7428 #endif /* chips */ 7429 7430 #if defined(BCM_56640_A0) 7431 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56640_A0fmt */ 7432 /* format VFP_F3_2fmt */ 7433 /* nFields */ 5, 7434 /* *fields */ soc_VFP_F3_2_BCM56640_A0fmt_fields, 7435 /* bits */ 36, 7436 /* flags */ 0, 7437 }, 7438 #endif /* chips */ 7439 7440 #if defined(BCM_56670_A0) 7441 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56670_A0fmt */ 7442 /* format VFP_F3_2fmt */ 7443 /* nFields */ 5, 7444 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7445 /* bits */ 36, 7446 /* flags */ 0, 7447 }, 7448 #endif /* chips */ 7449 7450 #if defined(BCM_56670_B0) 7451 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56670_B0fmt */ 7452 /* format VFP_F3_2fmt */ 7453 /* nFields */ 5, 7454 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7455 /* bits */ 36, 7456 /* flags */ 0, 7457 }, 7458 #endif /* chips */ 7459 7460 #if defined(BCM_56680_A0) 7461 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56680_A0fmt */ 7462 /* format VFP_F3_2fmt */ 7463 /* nFields */ 4, 7464 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7465 /* bits */ 32, 7466 /* flags */ 0, 7467 }, 7468 #endif /* chips */ 7469 7470 #if defined(BCM_56680_B0) 7471 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56680_B0fmt */ 7472 /* format VFP_F3_2fmt */ 7473 /* nFields */ 4, 7474 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7475 /* bits */ 32, 7476 /* flags */ 0, 7477 }, 7478 #endif /* chips */ 7479 7480 #if defined(BCM_56685_A0) 7481 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56685_A0fmt */ 7482 /* format VFP_F3_2fmt */ 7483 /* nFields */ 4, 7484 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7485 /* bits */ 32, 7486 /* flags */ 0, 7487 }, 7488 #endif /* chips */ 7489 7490 #if defined(BCM_56685_B0) 7491 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56685_B0fmt */ 7492 /* format VFP_F3_2fmt */ 7493 /* nFields */ 4, 7494 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7495 /* bits */ 32, 7496 /* flags */ 0, 7497 }, 7498 #endif /* chips */ 7499 7500 #if defined(BCM_56725_A0) 7501 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56725_A0fmt */ 7502 /* format VFP_F3_2fmt */ 7503 /* nFields */ 4, 7504 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7505 /* bits */ 32, 7506 /* flags */ 0, 7507 }, 7508 #endif /* chips */ 7509 7510 #if defined(BCM_56770_A0) 7511 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56770_A0fmt */ 7512 /* format VFP_F3_2fmt */ 7513 /* nFields */ 5, 7514 /* *fields */ soc_VFP_F3_2_BCM56870_A0fmt_fields, 7515 /* bits */ 36, 7516 /* flags */ 0, 7517 }, 7518 #endif /* chips */ 7519 7520 #if defined(BCM_56820_A0) 7521 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56820_A0fmt */ 7522 /* format VFP_F3_2fmt */ 7523 /* nFields */ 4, 7524 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7525 /* bits */ 32, 7526 /* flags */ 0, 7527 }, 7528 #endif /* chips */ 7529 7530 #if defined(BCM_56840_A0) 7531 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56840_A0fmt */ 7532 /* format VFP_F3_2fmt */ 7533 /* nFields */ 4, 7534 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7535 /* bits */ 32, 7536 /* flags */ 0, 7537 }, 7538 #endif /* chips */ 7539 7540 #if defined(BCM_56840_B0) 7541 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56840_B0fmt */ 7542 /* format VFP_F3_2fmt */ 7543 /* nFields */ 4, 7544 /* *fields */ soc_VFP_F3_2_BCM56624_A0fmt_fields, 7545 /* bits */ 32, 7546 /* flags */ 0, 7547 }, 7548 #endif /* chips */ 7549 7550 #if defined(BCM_56850_A0) 7551 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56850_A0fmt */ 7552 /* format VFP_F3_2fmt */ 7553 /* nFields */ 5, 7554 /* *fields */ soc_VFP_F3_2_BCM56640_A0fmt_fields, 7555 /* bits */ 36, 7556 /* flags */ 0, 7557 }, 7558 #endif /* chips */ 7559 7560 #if defined(BCM_56860_A0) 7561 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56860_A0fmt */ 7562 /* format VFP_F3_2fmt */ 7563 /* nFields */ 5, 7564 /* *fields */ soc_VFP_F3_2_BCM56640_A0fmt_fields, 7565 /* bits */ 36, 7566 /* flags */ 0, 7567 }, 7568 #endif /* chips */ 7569 7570 #if defined(BCM_56870_A0) 7571 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56870_A0fmt */ 7572 /* format VFP_F3_2fmt */ 7573 /* nFields */ 5, 7574 /* *fields */ soc_VFP_F3_2_BCM56870_A0fmt_fields, 7575 /* bits */ 36, 7576 /* flags */ 0, 7577 }, 7578 #endif /* chips */ 7579 7580 #if defined(BCM_56960_A0) 7581 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56960_A0fmt */ 7582 /* format VFP_F3_2fmt */ 7583 /* nFields */ 5, 7584 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7585 /* bits */ 36, 7586 /* flags */ 0, 7587 }, 7588 #endif /* chips */ 7589 7590 #if defined(BCM_56965_A0) 7591 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56965_A0fmt */ 7592 /* format VFP_F3_2fmt */ 7593 /* nFields */ 5, 7594 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7595 /* bits */ 36, 7596 /* flags */ 0, 7597 }, 7598 #endif /* chips */ 7599 7600 #if defined(BCM_56970_A0) 7601 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56970_A0fmt */ 7602 /* format VFP_F3_2fmt */ 7603 /* nFields */ 5, 7604 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7605 /* bits */ 36, 7606 /* flags */ 0, 7607 }, 7608 #endif /* chips */ 7609 7610 #if defined(BCM_56980_A0) 7611 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56980_A0fmt */ 7612 /* format VFP_F3_2fmt */ 7613 /* nFields */ 5, 7614 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7615 /* bits */ 36, 7616 /* flags */ 0, 7617 }, 7618 #endif /* chips */ 7619 7620 #if defined(BCM_56980_B0) 7621 { /* SOC_FORMAT_INT_VFP_F3_2_BCM56980_B0fmt */ 7622 /* format VFP_F3_2fmt */ 7623 /* nFields */ 5, 7624 /* *fields */ soc_VFP_F3_2_BCM56960_A0fmt_fields, 7625 /* bits */ 36, 7626 /* flags */ 0, 7627 }, 7628 #endif /* chips */ 7629 7630 #if defined(BCM_53400_A0) 7631 { /* SOC_FORMAT_INT_VFP_F3_3_BCM53400_A0fmt */ 7632 /* format VFP_F3_3fmt */ 7633 /* nFields */ 4, 7634 /* *fields */ soc_VFP_F3_3_BCM53400_A0fmt_fields, 7635 /* bits */ 32, 7636 /* flags */ 0, 7637 }, 7638 #endif /* chips */ 7639 7640 #if defined(BCM_53540_A0) 7641 { /* SOC_FORMAT_INT_VFP_F3_3_BCM53540_A0fmt */ 7642 /* format VFP_F3_3fmt */ 7643 /* nFields */ 3, 7644 /* *fields */ soc_VFP_F3_3_BCM56260_A0fmt_fields, 7645 /* bits */ 32, 7646 /* flags */ 0, 7647 }, 7648 #endif /* chips */ 7649 7650 #if defined(BCM_53570_A0) 7651 { /* SOC_FORMAT_INT_VFP_F3_3_BCM53570_A0fmt */ 7652 /* format VFP_F3_3fmt */ 7653 /* nFields */ 3, 7654 /* *fields */ soc_VFP_F3_3_BCM56260_A0fmt_fields, 7655 /* bits */ 32, 7656 /* flags */ 0, 7657 }, 7658 #endif /* chips */ 7659 7660 #if defined(BCM_53570_B0) 7661 { /* SOC_FORMAT_INT_VFP_F3_3_BCM53570_B0fmt */ 7662 /* format VFP_F3_3fmt */ 7663 /* nFields */ 3, 7664 /* *fields */ soc_VFP_F3_3_BCM56260_A0fmt_fields, 7665 /* bits */ 32, 7666 /* flags */ 0, 7667 }, 7668 #endif /* chips */ 7669 7670 #if defined(BCM_56142_A0) 7671 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56142_A0fmt */ 7672 /* format VFP_F3_3fmt */ 7673 /* nFields */ 4, 7674 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7675 /* bits */ 32, 7676 /* flags */ 0, 7677 }, 7678 #endif /* chips */ 7679 7680 #if defined(BCM_56150_A0) 7681 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56150_A0fmt */ 7682 /* format VFP_F3_3fmt */ 7683 /* nFields */ 4, 7684 /* *fields */ soc_VFP_F3_3_BCM56150_A0fmt_fields, 7685 /* bits */ 32, 7686 /* flags */ 0, 7687 }, 7688 #endif /* chips */ 7689 7690 #if defined(BCM_56160_A0) 7691 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56160_A0fmt */ 7692 /* format VFP_F3_3fmt */ 7693 /* nFields */ 3, 7694 /* *fields */ soc_VFP_F3_3_BCM56260_A0fmt_fields, 7695 /* bits */ 32, 7696 /* flags */ 0, 7697 }, 7698 #endif /* chips */ 7699 7700 #if defined(BCM_56260_A0) 7701 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56260_A0fmt */ 7702 /* format VFP_F3_3fmt */ 7703 /* nFields */ 3, 7704 /* *fields */ soc_VFP_F3_3_BCM56260_A0fmt_fields, 7705 /* bits */ 32, 7706 /* flags */ 0, 7707 }, 7708 #endif /* chips */ 7709 7710 #if defined(BCM_56260_B0) 7711 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56260_B0fmt */ 7712 /* format VFP_F3_3fmt */ 7713 /* nFields */ 3, 7714 /* *fields */ soc_VFP_F3_3_BCM56260_A0fmt_fields, 7715 /* bits */ 32, 7716 /* flags */ 0, 7717 }, 7718 #endif /* chips */ 7719 7720 #if defined(BCM_56270_A0) 7721 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56270_A0fmt */ 7722 /* format VFP_F3_3fmt */ 7723 /* nFields */ 4, 7724 /* *fields */ soc_VFP_F3_3_BCM56270_A0fmt_fields, 7725 /* bits */ 32, 7726 /* flags */ 0, 7727 }, 7728 #endif /* chips */ 7729 7730 #if defined(BCM_56334_A0) 7731 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56334_A0fmt */ 7732 /* format VFP_F3_3fmt */ 7733 /* nFields */ 4, 7734 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7735 /* bits */ 32, 7736 /* flags */ 0, 7737 }, 7738 #endif /* chips */ 7739 7740 #if defined(BCM_56334_B0) 7741 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56334_B0fmt */ 7742 /* format VFP_F3_3fmt */ 7743 /* nFields */ 4, 7744 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7745 /* bits */ 32, 7746 /* flags */ 0, 7747 }, 7748 #endif /* chips */ 7749 7750 #if defined(BCM_56340_A0) 7751 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56340_A0fmt */ 7752 /* format VFP_F3_3fmt */ 7753 /* nFields */ 3, 7754 /* *fields */ soc_VFP_F3_3_BCM56640_A0fmt_fields, 7755 /* bits */ 36, 7756 /* flags */ 0, 7757 }, 7758 #endif /* chips */ 7759 7760 #if defined(BCM_56370_A0) 7761 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56370_A0fmt */ 7762 /* format VFP_F3_3fmt */ 7763 /* nFields */ 3, 7764 /* *fields */ soc_VFP_F3_3_BCM56870_A0fmt_fields, 7765 /* bits */ 36, 7766 /* flags */ 0, 7767 }, 7768 #endif /* chips */ 7769 7770 #if defined(BCM_56440_A0) 7771 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56440_A0fmt */ 7772 /* format VFP_F3_3fmt */ 7773 /* nFields */ 3, 7774 /* *fields */ soc_VFP_F3_3_BCM56840_A0fmt_fields, 7775 /* bits */ 32, 7776 /* flags */ 0, 7777 }, 7778 #endif /* chips */ 7779 7780 #if defined(BCM_56440_B0) 7781 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56440_B0fmt */ 7782 /* format VFP_F3_3fmt */ 7783 /* nFields */ 3, 7784 /* *fields */ soc_VFP_F3_3_BCM56840_A0fmt_fields, 7785 /* bits */ 32, 7786 /* flags */ 0, 7787 }, 7788 #endif /* chips */ 7789 7790 #if defined(BCM_56450_A0) 7791 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56450_A0fmt */ 7792 /* format VFP_F3_3fmt */ 7793 /* nFields */ 3, 7794 /* *fields */ soc_VFP_F3_3_BCM56450_A0fmt_fields, 7795 /* bits */ 32, 7796 /* flags */ 0, 7797 }, 7798 #endif /* chips */ 7799 7800 #if defined(BCM_56450_B0) 7801 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56450_B0fmt */ 7802 /* format VFP_F3_3fmt */ 7803 /* nFields */ 3, 7804 /* *fields */ soc_VFP_F3_3_BCM56450_A0fmt_fields, 7805 /* bits */ 32, 7806 /* flags */ 0, 7807 }, 7808 #endif /* chips */ 7809 7810 #if defined(BCM_56450_B1) 7811 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56450_B1fmt */ 7812 /* format VFP_F3_3fmt */ 7813 /* nFields */ 3, 7814 /* *fields */ soc_VFP_F3_3_BCM56450_A0fmt_fields, 7815 /* bits */ 32, 7816 /* flags */ 0, 7817 }, 7818 #endif /* chips */ 7819 7820 #if defined(BCM_56524_A0) 7821 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56524_A0fmt */ 7822 /* format VFP_F3_3fmt */ 7823 /* nFields */ 4, 7824 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7825 /* bits */ 32, 7826 /* flags */ 0, 7827 }, 7828 #endif /* chips */ 7829 7830 #if defined(BCM_56524_B0) 7831 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56524_B0fmt */ 7832 /* format VFP_F3_3fmt */ 7833 /* nFields */ 4, 7834 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7835 /* bits */ 32, 7836 /* flags */ 0, 7837 }, 7838 #endif /* chips */ 7839 7840 #if defined(BCM_56560_A0) 7841 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56560_A0fmt */ 7842 /* format VFP_F3_3fmt */ 7843 /* nFields */ 4, 7844 /* *fields */ soc_VFP_F3_3_BCM56960_A0fmt_fields, 7845 /* bits */ 36, 7846 /* flags */ 0, 7847 }, 7848 #endif /* chips */ 7849 7850 #if defined(BCM_56560_B0) 7851 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56560_B0fmt */ 7852 /* format VFP_F3_3fmt */ 7853 /* nFields */ 4, 7854 /* *fields */ soc_VFP_F3_3_BCM56960_A0fmt_fields, 7855 /* bits */ 36, 7856 /* flags */ 0, 7857 }, 7858 #endif /* chips */ 7859 7860 #if defined(BCM_56624_A0) 7861 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56624_A0fmt */ 7862 /* format VFP_F3_3fmt */ 7863 /* nFields */ 3, 7864 /* *fields */ soc_VFP_F3_3_BCM56624_A0fmt_fields, 7865 /* bits */ 32, 7866 /* flags */ 0, 7867 }, 7868 #endif /* chips */ 7869 7870 #if defined(BCM_56624_B0) 7871 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56624_B0fmt */ 7872 /* format VFP_F3_3fmt */ 7873 /* nFields */ 3, 7874 /* *fields */ soc_VFP_F3_3_BCM56624_A0fmt_fields, 7875 /* bits */ 32, 7876 /* flags */ 0, 7877 }, 7878 #endif /* chips */ 7879 7880 #if defined(BCM_56634_A0) 7881 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56634_A0fmt */ 7882 /* format VFP_F3_3fmt */ 7883 /* nFields */ 4, 7884 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7885 /* bits */ 32, 7886 /* flags */ 0, 7887 }, 7888 #endif /* chips */ 7889 7890 #if defined(BCM_56634_B0) 7891 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56634_B0fmt */ 7892 /* format VFP_F3_3fmt */ 7893 /* nFields */ 4, 7894 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7895 /* bits */ 32, 7896 /* flags */ 0, 7897 }, 7898 #endif /* chips */ 7899 7900 #if defined(BCM_56640_A0) 7901 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56640_A0fmt */ 7902 /* format VFP_F3_3fmt */ 7903 /* nFields */ 3, 7904 /* *fields */ soc_VFP_F3_3_BCM56640_A0fmt_fields, 7905 /* bits */ 36, 7906 /* flags */ 0, 7907 }, 7908 #endif /* chips */ 7909 7910 #if defined(BCM_56670_A0) 7911 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56670_A0fmt */ 7912 /* format VFP_F3_3fmt */ 7913 /* nFields */ 4, 7914 /* *fields */ soc_VFP_F3_3_BCM56960_A0fmt_fields, 7915 /* bits */ 36, 7916 /* flags */ 0, 7917 }, 7918 #endif /* chips */ 7919 7920 #if defined(BCM_56670_B0) 7921 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56670_B0fmt */ 7922 /* format VFP_F3_3fmt */ 7923 /* nFields */ 4, 7924 /* *fields */ soc_VFP_F3_3_BCM56960_A0fmt_fields, 7925 /* bits */ 36, 7926 /* flags */ 0, 7927 }, 7928 #endif /* chips */ 7929 7930 #if defined(BCM_56680_A0) 7931 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56680_A0fmt */ 7932 /* format VFP_F3_3fmt */ 7933 /* nFields */ 3, 7934 /* *fields */ soc_VFP_F3_3_BCM56624_A0fmt_fields, 7935 /* bits */ 32, 7936 /* flags */ 0, 7937 }, 7938 #endif /* chips */ 7939 7940 #if defined(BCM_56680_B0) 7941 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56680_B0fmt */ 7942 /* format VFP_F3_3fmt */ 7943 /* nFields */ 3, 7944 /* *fields */ soc_VFP_F3_3_BCM56624_A0fmt_fields, 7945 /* bits */ 32, 7946 /* flags */ 0, 7947 }, 7948 #endif /* chips */ 7949 7950 #if defined(BCM_56685_A0) 7951 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56685_A0fmt */ 7952 /* format VFP_F3_3fmt */ 7953 /* nFields */ 4, 7954 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7955 /* bits */ 32, 7956 /* flags */ 0, 7957 }, 7958 #endif /* chips */ 7959 7960 #if defined(BCM_56685_B0) 7961 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56685_B0fmt */ 7962 /* format VFP_F3_3fmt */ 7963 /* nFields */ 4, 7964 /* *fields */ soc_VFP_F3_3_BCM56634_A0fmt_fields, 7965 /* bits */ 32, 7966 /* flags */ 0, 7967 }, 7968 #endif /* chips */ 7969 7970 #if defined(BCM_56725_A0) 7971 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56725_A0fmt */ 7972 /* format VFP_F3_3fmt */ 7973 /* nFields */ 3, 7974 /* *fields */ soc_VFP_F3_3_BCM56624_A0fmt_fields, 7975 /* bits */ 32, 7976 /* flags */ 0, 7977 }, 7978 #endif /* chips */ 7979 7980 #if defined(BCM_56770_A0) 7981 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56770_A0fmt */ 7982 /* format VFP_F3_3fmt */ 7983 /* nFields */ 3, 7984 /* *fields */ soc_VFP_F3_3_BCM56870_A0fmt_fields, 7985 /* bits */ 36, 7986 /* flags */ 0, 7987 }, 7988 #endif /* chips */ 7989 7990 #if defined(BCM_56820_A0) 7991 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56820_A0fmt */ 7992 /* format VFP_F3_3fmt */ 7993 /* nFields */ 3, 7994 /* *fields */ soc_VFP_F3_3_BCM56624_A0fmt_fields, 7995 /* bits */ 32, 7996 /* flags */ 0, 7997 }, 7998 #endif /* chips */ 7999 8000 #if defined(BCM_56840_A0) 8001 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56840_A0fmt */ 8002 /* format VFP_F3_3fmt */ 8003 /* nFields */ 3, 8004 /* *fields */ soc_VFP_F3_3_BCM56840_A0fmt_fields, 8005 /* bits */ 32, 8006 /* flags */ 0, 8007 }, 8008 #endif /* chips */ 8009 8010 #if defined(BCM_56840_B0) 8011 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56840_B0fmt */ 8012 /* format VFP_F3_3fmt */ 8013 /* nFields */ 3, 8014 /* *fields */ soc_VFP_F3_3_BCM56840_A0fmt_fields, 8015 /* bits */ 32, 8016 /* flags */ 0, 8017 }, 8018 #endif /* chips */ 8019 8020 #if defined(BCM_56850_A0) 8021 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56850_A0fmt */ 8022 /* format VFP_F3_3fmt */ 8023 /* nFields */ 4, 8024 /* *fields */ soc_VFP_F3_3_BCM56850_A0fmt_fields, 8025 /* bits */ 36, 8026 /* flags */ 0, 8027 }, 8028 #endif /* chips */ 8029 8030 #if defined(BCM_56860_A0) 8031 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56860_A0fmt */ 8032 /* format VFP_F3_3fmt */ 8033 /* nFields */ 4, 8034 /* *fields */ soc_VFP_F3_3_BCM56850_A0fmt_fields, 8035 /* bits */ 36, 8036 /* flags */ 0, 8037 }, 8038 #endif /* chips */ 8039 8040 #if defined(BCM_56870_A0) 8041 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56870_A0fmt */ 8042 /* format VFP_F3_3fmt */ 8043 /* nFields */ 3, 8044 /* *fields */ soc_VFP_F3_3_BCM56870_A0fmt_fields, 8045 /* bits */ 36, 8046 /* flags */ 0, 8047 }, 8048 #endif /* chips */ 8049 8050 #if defined(BCM_56960_A0) 8051 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56960_A0fmt */ 8052 /* format VFP_F3_3fmt */ 8053 /* nFields */ 4, 8054 /* *fields */ soc_VFP_F3_3_BCM56960_A0fmt_fields, 8055 /* bits */ 36, 8056 /* flags */ 0, 8057 }, 8058 #endif /* chips */ 8059 8060 #if defined(BCM_56965_A0) 8061 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56965_A0fmt */ 8062 /* format VFP_F3_3fmt */ 8063 /* nFields */ 4, 8064 /* *fields */ soc_VFP_F3_3_BCM56960_A0fmt_fields, 8065 /* bits */ 36, 8066 /* flags */ 0, 8067 }, 8068 #endif /* chips */ 8069 8070 #if defined(BCM_56970_A0) 8071 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56970_A0fmt */ 8072 /* format VFP_F3_3fmt */ 8073 /* nFields */ 3, 8074 /* *fields */ soc_VFP_F3_3_BCM56970_A0fmt_fields, 8075 /* bits */ 36, 8076 /* flags */ 0, 8077 }, 8078 #endif /* chips */ 8079 8080 #if defined(BCM_56980_A0) 8081 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56980_A0fmt */ 8082 /* format VFP_F3_3fmt */ 8083 /* nFields */ 2, 8084 /* *fields */ soc_VFP_F3_3_BCM56980_A0fmt_fields, 8085 /* bits */ 36, 8086 /* flags */ 0, 8087 }, 8088 #endif /* chips */ 8089 8090 #if defined(BCM_56980_B0) 8091 { /* SOC_FORMAT_INT_VFP_F3_3_BCM56980_B0fmt */ 8092 /* format VFP_F3_3fmt */ 8093 /* nFields */ 2, 8094 /* *fields */ soc_VFP_F3_3_BCM56980_A0fmt_fields, 8095 /* bits */ 36, 8096 /* flags */ 0, 8097 }, 8098 #endif /* chips */ 8099 8100 #if defined(BCM_53570_B0) 8101 { /* SOC_FORMAT_INT_VFP_F3_4_BCM53570_B0fmt */ 8102 /* format VFP_F3_4fmt */ 8103 /* nFields */ 3, 8104 /* *fields */ soc_VFP_F3_4_BCM53570_B0fmt_fields, 8105 /* bits */ 32, 8106 /* flags */ 0, 8107 }, 8108 #endif /* chips */ 8109 8110 #if defined(BCM_56260_A0) 8111 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56260_A0fmt */ 8112 /* format VFP_F3_4fmt */ 8113 /* nFields */ 3, 8114 /* *fields */ soc_VFP_F3_4_BCM56260_A0fmt_fields, 8115 /* bits */ 32, 8116 /* flags */ 0, 8117 }, 8118 #endif /* chips */ 8119 8120 #if defined(BCM_56260_B0) 8121 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56260_B0fmt */ 8122 /* format VFP_F3_4fmt */ 8123 /* nFields */ 3, 8124 /* *fields */ soc_VFP_F3_4_BCM56260_A0fmt_fields, 8125 /* bits */ 32, 8126 /* flags */ 0, 8127 }, 8128 #endif /* chips */ 8129 8130 #if defined(BCM_56270_A0) 8131 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56270_A0fmt */ 8132 /* format VFP_F3_4fmt */ 8133 /* nFields */ 3, 8134 /* *fields */ soc_VFP_F3_4_BCM56260_A0fmt_fields, 8135 /* bits */ 32, 8136 /* flags */ 0, 8137 }, 8138 #endif /* chips */ 8139 8140 #if defined(BCM_56370_A0) 8141 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56370_A0fmt */ 8142 /* format VFP_F3_4fmt */ 8143 /* nFields */ 3, 8144 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8145 /* bits */ 36, 8146 /* flags */ 0, 8147 }, 8148 #endif /* chips */ 8149 8150 #if defined(BCM_56450_A0) 8151 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56450_A0fmt */ 8152 /* format VFP_F3_4fmt */ 8153 /* nFields */ 3, 8154 /* *fields */ soc_VFP_F3_4_BCM56450_A0fmt_fields, 8155 /* bits */ 32, 8156 /* flags */ 0, 8157 }, 8158 #endif /* chips */ 8159 8160 #if defined(BCM_56450_B0) 8161 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56450_B0fmt */ 8162 /* format VFP_F3_4fmt */ 8163 /* nFields */ 3, 8164 /* *fields */ soc_VFP_F3_4_BCM56450_A0fmt_fields, 8165 /* bits */ 32, 8166 /* flags */ 0, 8167 }, 8168 #endif /* chips */ 8169 8170 #if defined(BCM_56450_B1) 8171 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56450_B1fmt */ 8172 /* format VFP_F3_4fmt */ 8173 /* nFields */ 3, 8174 /* *fields */ soc_VFP_F3_4_BCM56450_A0fmt_fields, 8175 /* bits */ 32, 8176 /* flags */ 0, 8177 }, 8178 #endif /* chips */ 8179 8180 #if defined(BCM_56560_A0) 8181 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56560_A0fmt */ 8182 /* format VFP_F3_4fmt */ 8183 /* nFields */ 3, 8184 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8185 /* bits */ 36, 8186 /* flags */ 0, 8187 }, 8188 #endif /* chips */ 8189 8190 #if defined(BCM_56560_B0) 8191 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56560_B0fmt */ 8192 /* format VFP_F3_4fmt */ 8193 /* nFields */ 3, 8194 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8195 /* bits */ 36, 8196 /* flags */ 0, 8197 }, 8198 #endif /* chips */ 8199 8200 #if defined(BCM_56670_A0) 8201 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56670_A0fmt */ 8202 /* format VFP_F3_4fmt */ 8203 /* nFields */ 3, 8204 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8205 /* bits */ 36, 8206 /* flags */ 0, 8207 }, 8208 #endif /* chips */ 8209 8210 #if defined(BCM_56670_B0) 8211 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56670_B0fmt */ 8212 /* format VFP_F3_4fmt */ 8213 /* nFields */ 3, 8214 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8215 /* bits */ 36, 8216 /* flags */ 0, 8217 }, 8218 #endif /* chips */ 8219 8220 #if defined(BCM_56770_A0) 8221 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56770_A0fmt */ 8222 /* format VFP_F3_4fmt */ 8223 /* nFields */ 3, 8224 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8225 /* bits */ 36, 8226 /* flags */ 0, 8227 }, 8228 #endif /* chips */ 8229 8230 #if defined(BCM_56870_A0) 8231 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56870_A0fmt */ 8232 /* format VFP_F3_4fmt */ 8233 /* nFields */ 3, 8234 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8235 /* bits */ 36, 8236 /* flags */ 0, 8237 }, 8238 #endif /* chips */ 8239 8240 #if defined(BCM_56960_A0) 8241 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56960_A0fmt */ 8242 /* format VFP_F3_4fmt */ 8243 /* nFields */ 3, 8244 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8245 /* bits */ 36, 8246 /* flags */ 0, 8247 }, 8248 #endif /* chips */ 8249 8250 #if defined(BCM_56965_A0) 8251 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56965_A0fmt */ 8252 /* format VFP_F3_4fmt */ 8253 /* nFields */ 3, 8254 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8255 /* bits */ 36, 8256 /* flags */ 0, 8257 }, 8258 #endif /* chips */ 8259 8260 #if defined(BCM_56970_A0) 8261 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56970_A0fmt */ 8262 /* format VFP_F3_4fmt */ 8263 /* nFields */ 3, 8264 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8265 /* bits */ 36, 8266 /* flags */ 0, 8267 }, 8268 #endif /* chips */ 8269 8270 #if defined(BCM_56980_A0) 8271 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56980_A0fmt */ 8272 /* format VFP_F3_4fmt */ 8273 /* nFields */ 3, 8274 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8275 /* bits */ 36, 8276 /* flags */ 0, 8277 }, 8278 #endif /* chips */ 8279 8280 #if defined(BCM_56980_B0) 8281 { /* SOC_FORMAT_INT_VFP_F3_4_BCM56980_B0fmt */ 8282 /* format VFP_F3_4fmt */ 8283 /* nFields */ 3, 8284 /* *fields */ soc_VFP_F3_4_BCM56960_A0fmt_fields, 8285 /* bits */ 36, 8286 /* flags */ 0, 8287 }, 8288 #endif /* chips */ 8289 8290 #if defined(BCM_56370_A0) 8291 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56370_A0fmt */ 8292 /* format VFP_F3_5fmt */ 8293 /* nFields */ 5, 8294 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8295 /* bits */ 36, 8296 /* flags */ 0, 8297 }, 8298 #endif /* chips */ 8299 8300 #if defined(BCM_56560_A0) 8301 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56560_A0fmt */ 8302 /* format VFP_F3_5fmt */ 8303 /* nFields */ 5, 8304 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8305 /* bits */ 36, 8306 /* flags */ 0, 8307 }, 8308 #endif /* chips */ 8309 8310 #if defined(BCM_56560_B0) 8311 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56560_B0fmt */ 8312 /* format VFP_F3_5fmt */ 8313 /* nFields */ 5, 8314 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8315 /* bits */ 36, 8316 /* flags */ 0, 8317 }, 8318 #endif /* chips */ 8319 8320 #if defined(BCM_56670_A0) 8321 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56670_A0fmt */ 8322 /* format VFP_F3_5fmt */ 8323 /* nFields */ 5, 8324 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8325 /* bits */ 36, 8326 /* flags */ 0, 8327 }, 8328 #endif /* chips */ 8329 8330 #if defined(BCM_56670_B0) 8331 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56670_B0fmt */ 8332 /* format VFP_F3_5fmt */ 8333 /* nFields */ 5, 8334 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8335 /* bits */ 36, 8336 /* flags */ 0, 8337 }, 8338 #endif /* chips */ 8339 8340 #if defined(BCM_56770_A0) 8341 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56770_A0fmt */ 8342 /* format VFP_F3_5fmt */ 8343 /* nFields */ 5, 8344 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8345 /* bits */ 36, 8346 /* flags */ 0, 8347 }, 8348 #endif /* chips */ 8349 8350 #if defined(BCM_56870_A0) 8351 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56870_A0fmt */ 8352 /* format VFP_F3_5fmt */ 8353 /* nFields */ 5, 8354 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8355 /* bits */ 36, 8356 /* flags */ 0, 8357 }, 8358 #endif /* chips */ 8359 8360 #if defined(BCM_56960_A0) 8361 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56960_A0fmt */ 8362 /* format VFP_F3_5fmt */ 8363 /* nFields */ 5, 8364 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8365 /* bits */ 36, 8366 /* flags */ 0, 8367 }, 8368 #endif /* chips */ 8369 8370 #if defined(BCM_56965_A0) 8371 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56965_A0fmt */ 8372 /* format VFP_F3_5fmt */ 8373 /* nFields */ 5, 8374 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8375 /* bits */ 36, 8376 /* flags */ 0, 8377 }, 8378 #endif /* chips */ 8379 8380 #if defined(BCM_56970_A0) 8381 { /* SOC_FORMAT_INT_VFP_F3_5_BCM56970_A0fmt */ 8382 /* format VFP_F3_5fmt */ 8383 /* nFields */ 5, 8384 /* *fields */ soc_VFP_F3_5_BCM56960_A0fmt_fields, 8385 /* bits */ 36, 8386 /* flags */ 0, 8387 }, 8388 #endif /* chips */ 8389 8390 #if defined(BCM_56370_A0) 8391 { /* SOC_FORMAT_INT_VFP_F3_6_BCM56370_A0fmt */ 8392 /* format VFP_F3_6fmt */ 8393 /* nFields */ 5, 8394 /* *fields */ soc_VFP_F3_6_BCM56560_A0fmt_fields, 8395 /* bits */ 36, 8396 /* flags */ 0, 8397 }, 8398 #endif /* chips */ 8399 8400 #if defined(BCM_56560_A0) 8401 { /* SOC_FORMAT_INT_VFP_F3_6_BCM56560_A0fmt */ 8402 /* format VFP_F3_6fmt */ 8403 /* nFields */ 5, 8404 /* *fields */ soc_VFP_F3_6_BCM56560_A0fmt_fields, 8405 /* bits */ 36, 8406 /* flags */ 0, 8407 }, 8408 #endif /* chips */ 8409 8410 #if defined(BCM_56560_B0) 8411 { /* SOC_FORMAT_INT_VFP_F3_6_BCM56560_B0fmt */ 8412 /* format VFP_F3_6fmt */ 8413 /* nFields */ 5, 8414 /* *fields */ soc_VFP_F3_6_BCM56560_A0fmt_fields, 8415 /* bits */ 36, 8416 /* flags */ 0, 8417 }, 8418 #endif /* chips */ 8419 8420 #if defined(BCM_56670_A0) 8421 { /* SOC_FORMAT_INT_VFP_F3_6_BCM56670_A0fmt */ 8422 /* format VFP_F3_6fmt */ 8423 /* nFields */ 5, 8424 /* *fields */ soc_VFP_F3_6_BCM56560_A0fmt_fields, 8425 /* bits */ 36, 8426 /* flags */ 0, 8427 }, 8428 #endif /* chips */ 8429 8430 #if defined(BCM_56670_B0) 8431 { /* SOC_FORMAT_INT_VFP_F3_6_BCM56670_B0fmt */ 8432 /* format VFP_F3_6fmt */ 8433 /* nFields */ 5, 8434 /* *fields */ soc_VFP_F3_6_BCM56560_A0fmt_fields, 8435 /* bits */ 36, 8436 /* flags */ 0, 8437 }, 8438 #endif /* chips */ 8439 8440 #if defined(BCM_56770_A0) 8441 { /* SOC_FORMAT_INT_VFP_F3_6_BCM56770_A0fmt */ 8442 /* format VFP_F3_6fmt */ 8443 /* nFields */ 5, 8444 /* *fields */ soc_VFP_F3_6_BCM56560_A0fmt_fields, 8445 /* bits */ 36, 8446 /* flags */ 0, 8447 }, 8448 #endif /* chips */ 8449 8450 #if defined(BCM_56870_A0) 8451 { /* SOC_FORMAT_INT_VFP_F3_6_BCM56870_A0fmt */ 8452 /* format VFP_F3_6fmt */ 8453 /* nFields */ 5, 8454 /* *fields */ soc_VFP_F3_6_BCM56560_A0fmt_fields, 8455 /* bits */ 36, 8456 /* flags */ 0, 8457 }, 8458 #endif /* chips */ 8459 8460 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8461 { /* SOC_FORMAT_INT_VFP_KEY_0_DOPfmt */ 8462 /* format VFP_KEY_0_DOPfmt */ 8463 /* nFields */ 3, 8464 /* *fields */ soc_VFP_KEY_0_DOPfmt_fields, 8465 /* bits */ 256, 8466 /* flags */ 0, 8467 }, 8468 #endif /* chips */ 8469 8470 #if defined(BCM_56370_A0) 8471 { /* SOC_FORMAT_INT_VFP_KEY_0_DOP_BCM56370_A0fmt */ 8472 /* format VFP_KEY_0_DOPfmt */ 8473 /* nFields */ 3, 8474 /* *fields */ soc_VFP_KEY_0_DOP_BCM56370_A0fmt_fields, 8475 /* bits */ 256, 8476 /* flags */ 0, 8477 }, 8478 #endif /* chips */ 8479 8480 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8481 { /* SOC_FORMAT_INT_VFP_KEY_1_DOPfmt */ 8482 /* format VFP_KEY_1_DOPfmt */ 8483 /* nFields */ 3, 8484 /* *fields */ soc_VFP_KEY_1_DOPfmt_fields, 8485 /* bits */ 256, 8486 /* flags */ 0, 8487 }, 8488 #endif /* chips */ 8489 8490 #if defined(BCM_56370_A0) 8491 { /* SOC_FORMAT_INT_VFP_KEY_1_DOP_BCM56370_A0fmt */ 8492 /* format VFP_KEY_1_DOPfmt */ 8493 /* nFields */ 3, 8494 /* *fields */ soc_VFP_KEY_1_DOP_BCM56370_A0fmt_fields, 8495 /* bits */ 256, 8496 /* flags */ 0, 8497 }, 8498 #endif /* chips */ 8499 8500 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8501 { /* SOC_FORMAT_INT_VFP_KEY_2_DOPfmt */ 8502 /* format VFP_KEY_2_DOPfmt */ 8503 /* nFields */ 3, 8504 /* *fields */ soc_VFP_KEY_2_DOPfmt_fields, 8505 /* bits */ 256, 8506 /* flags */ 0, 8507 }, 8508 #endif /* chips */ 8509 8510 #if defined(BCM_56370_A0) 8511 { /* SOC_FORMAT_INT_VFP_KEY_2_DOP_BCM56370_A0fmt */ 8512 /* format VFP_KEY_2_DOPfmt */ 8513 /* nFields */ 3, 8514 /* *fields */ soc_VFP_KEY_2_DOP_BCM56370_A0fmt_fields, 8515 /* bits */ 256, 8516 /* flags */ 0, 8517 }, 8518 #endif /* chips */ 8519 8520 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8521 { /* SOC_FORMAT_INT_VFP_KEY_3_DOPfmt */ 8522 /* format VFP_KEY_3_DOPfmt */ 8523 /* nFields */ 3, 8524 /* *fields */ soc_VFP_KEY_3_DOPfmt_fields, 8525 /* bits */ 256, 8526 /* flags */ 0, 8527 }, 8528 #endif /* chips */ 8529 8530 #if defined(BCM_56370_A0) 8531 { /* SOC_FORMAT_INT_VFP_KEY_3_DOP_BCM56370_A0fmt */ 8532 /* format VFP_KEY_3_DOPfmt */ 8533 /* nFields */ 3, 8534 /* *fields */ soc_VFP_KEY_3_DOP_BCM56370_A0fmt_fields, 8535 /* bits */ 256, 8536 /* flags */ 0, 8537 }, 8538 #endif /* chips */ 8539 8540 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8541 { /* SOC_FORMAT_INT_VFP_KEY_4_DOPfmt */ 8542 /* format VFP_KEY_4_DOPfmt */ 8543 /* nFields */ 3, 8544 /* *fields */ soc_VFP_KEY_4_DOPfmt_fields, 8545 /* bits */ 256, 8546 /* flags */ 0, 8547 }, 8548 #endif /* chips */ 8549 8550 #if defined(BCM_56370_A0) 8551 { /* SOC_FORMAT_INT_VFP_KEY_4_DOP_BCM56370_A0fmt */ 8552 /* format VFP_KEY_4_DOPfmt */ 8553 /* nFields */ 3, 8554 /* *fields */ soc_VFP_KEY_4_DOP_BCM56370_A0fmt_fields, 8555 /* bits */ 256, 8556 /* flags */ 0, 8557 }, 8558 #endif /* chips */ 8559 8560 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8561 { /* SOC_FORMAT_INT_VFP_KEY_5_DOPfmt */ 8562 /* format VFP_KEY_5_DOPfmt */ 8563 /* nFields */ 3, 8564 /* *fields */ soc_VFP_KEY_5_DOPfmt_fields, 8565 /* bits */ 256, 8566 /* flags */ 0, 8567 }, 8568 #endif /* chips */ 8569 8570 #if defined(BCM_56370_A0) 8571 { /* SOC_FORMAT_INT_VFP_KEY_5_DOP_BCM56370_A0fmt */ 8572 /* format VFP_KEY_5_DOPfmt */ 8573 /* nFields */ 3, 8574 /* *fields */ soc_VFP_KEY_5_DOP_BCM56370_A0fmt_fields, 8575 /* bits */ 256, 8576 /* flags */ 0, 8577 }, 8578 #endif /* chips */ 8579 8580 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8581 { /* SOC_FORMAT_INT_VFP_KEY_6_DOPfmt */ 8582 /* format VFP_KEY_6_DOPfmt */ 8583 /* nFields */ 3, 8584 /* *fields */ soc_VFP_KEY_6_DOPfmt_fields, 8585 /* bits */ 256, 8586 /* flags */ 0, 8587 }, 8588 #endif /* chips */ 8589 8590 #if defined(BCM_56370_A0) 8591 { /* SOC_FORMAT_INT_VFP_KEY_6_DOP_BCM56370_A0fmt */ 8592 /* format VFP_KEY_6_DOPfmt */ 8593 /* nFields */ 3, 8594 /* *fields */ soc_VFP_KEY_6_DOP_BCM56370_A0fmt_fields, 8595 /* bits */ 256, 8596 /* flags */ 0, 8597 }, 8598 #endif /* chips */ 8599 8600 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8601 { /* SOC_FORMAT_INT_VFP_KEY_7_DOPfmt */ 8602 /* format VFP_KEY_7_DOPfmt */ 8603 /* nFields */ 3, 8604 /* *fields */ soc_VFP_KEY_7_DOPfmt_fields, 8605 /* bits */ 256, 8606 /* flags */ 0, 8607 }, 8608 #endif /* chips */ 8609 8610 #if defined(BCM_56370_A0) 8611 { /* SOC_FORMAT_INT_VFP_KEY_7_DOP_BCM56370_A0fmt */ 8612 /* format VFP_KEY_7_DOPfmt */ 8613 /* nFields */ 3, 8614 /* *fields */ soc_VFP_KEY_7_DOP_BCM56370_A0fmt_fields, 8615 /* bits */ 256, 8616 /* flags */ 0, 8617 }, 8618 #endif /* chips */ 8619 8620 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8621 { /* SOC_FORMAT_INT_VFP_TCAM_DOPfmt */ 8622 /* format VFP_TCAM_DOPfmt */ 8623 /* nFields */ 18, 8624 /* *fields */ soc_VFP_TCAM_DOPfmt_fields, 8625 /* bits */ 96, 8626 /* flags */ 0, 8627 }, 8628 #endif /* chips */ 8629 8630 #if defined(BCM_56370_A0) 8631 { /* SOC_FORMAT_INT_VFP_TCAM_DOP_BCM56370_A0fmt */ 8632 /* format VFP_TCAM_DOPfmt */ 8633 /* nFields */ 17, 8634 /* *fields */ soc_VFP_TCAM_DOP_BCM56370_A0fmt_fields, 8635 /* bits */ 96, 8636 /* flags */ 0, 8637 }, 8638 #endif /* chips */ 8639 8640 #if defined(BCM_56840_A0) 8641 { /* SOC_FORMAT_INT_VLAN_0fmt */ 8642 /* format VLAN_0fmt */ 8643 /* nFields */ 19, 8644 /* *fields */ soc_VLAN_0fmt_fields, 8645 /* bits */ 107, 8646 /* flags */ 0, 8647 }, 8648 #endif /* chips */ 8649 8650 #if defined(BCM_56840_A0) 8651 { /* SOC_FORMAT_INT_VLAN_1fmt */ 8652 /* format VLAN_1fmt */ 8653 /* nFields */ 8, 8654 /* *fields */ soc_VLAN_1fmt_fields, 8655 /* bits */ 93, 8656 /* flags */ 0, 8657 }, 8658 #endif /* chips */ 8659 8660 #if defined(BCM_56260_A0) 8661 { /* SOC_FORMAT_INT_VLAN_0_BCM56260_A0fmt */ 8662 /* format VLAN_0fmt */ 8663 /* nFields */ 31, 8664 /* *fields */ soc_VLAN_0_BCM56260_A0fmt_fields, 8665 /* bits */ 240, 8666 /* flags */ 0, 8667 }, 8668 #endif /* chips */ 8669 8670 #if defined(BCM_56260_B0) 8671 { /* SOC_FORMAT_INT_VLAN_0_BCM56260_B0fmt */ 8672 /* format VLAN_0fmt */ 8673 /* nFields */ 31, 8674 /* *fields */ soc_VLAN_0_BCM56260_A0fmt_fields, 8675 /* bits */ 240, 8676 /* flags */ 0, 8677 }, 8678 #endif /* chips */ 8679 8680 #if defined(BCM_56270_A0) 8681 { /* SOC_FORMAT_INT_VLAN_0_BCM56270_A0fmt */ 8682 /* format VLAN_0fmt */ 8683 /* nFields */ 32, 8684 /* *fields */ soc_VLAN_0_BCM56270_A0fmt_fields, 8685 /* bits */ 160, 8686 /* flags */ 0, 8687 }, 8688 #endif /* chips */ 8689 8690 #if defined(BCM_56340_A0) 8691 { /* SOC_FORMAT_INT_VLAN_0_BCM56340_A0fmt */ 8692 /* format VLAN_0fmt */ 8693 /* nFields */ 25, 8694 /* *fields */ soc_VLAN_0_BCM56340_A0fmt_fields, 8695 /* bits */ 138, 8696 /* flags */ 0, 8697 }, 8698 #endif /* chips */ 8699 8700 #if defined(BCM_56370_A0) 8701 { /* SOC_FORMAT_INT_VLAN_0_BCM56370_A0fmt */ 8702 /* format VLAN_0fmt */ 8703 /* nFields */ 23, 8704 /* *fields */ soc_VLAN_0_BCM56370_A0fmt_fields, 8705 /* bits */ 133, 8706 /* flags */ 0, 8707 }, 8708 #endif /* chips */ 8709 8710 #if defined(BCM_56440_A0) 8711 { /* SOC_FORMAT_INT_VLAN_0_BCM56440_A0fmt */ 8712 /* format VLAN_0fmt */ 8713 /* nFields */ 18, 8714 /* *fields */ soc_VLAN_0_BCM56440_A0fmt_fields, 8715 /* bits */ 110, 8716 /* flags */ 0, 8717 }, 8718 #endif /* chips */ 8719 8720 #if defined(BCM_56440_B0) 8721 { /* SOC_FORMAT_INT_VLAN_0_BCM56440_B0fmt */ 8722 /* format VLAN_0fmt */ 8723 /* nFields */ 18, 8724 /* *fields */ soc_VLAN_0_BCM56440_A0fmt_fields, 8725 /* bits */ 110, 8726 /* flags */ 0, 8727 }, 8728 #endif /* chips */ 8729 8730 #if defined(BCM_56450_A0) 8731 { /* SOC_FORMAT_INT_VLAN_0_BCM56450_A0fmt */ 8732 /* format VLAN_0fmt */ 8733 /* nFields */ 41, 8734 /* *fields */ soc_VLAN_0_BCM56450_A0fmt_fields, 8735 /* bits */ 322, 8736 /* flags */ 0, 8737 }, 8738 #endif /* chips */ 8739 8740 #if defined(BCM_56450_B0) 8741 { /* SOC_FORMAT_INT_VLAN_0_BCM56450_B0fmt */ 8742 /* format VLAN_0fmt */ 8743 /* nFields */ 41, 8744 /* *fields */ soc_VLAN_0_BCM56450_A0fmt_fields, 8745 /* bits */ 322, 8746 /* flags */ 0, 8747 }, 8748 #endif /* chips */ 8749 8750 #if defined(BCM_56450_B1) 8751 { /* SOC_FORMAT_INT_VLAN_0_BCM56450_B1fmt */ 8752 /* format VLAN_0fmt */ 8753 /* nFields */ 41, 8754 /* *fields */ soc_VLAN_0_BCM56450_A0fmt_fields, 8755 /* bits */ 322, 8756 /* flags */ 0, 8757 }, 8758 #endif /* chips */ 8759 8760 #if defined(BCM_56560_A0) 8761 { /* SOC_FORMAT_INT_VLAN_0_BCM56560_A0fmt */ 8762 /* format VLAN_0fmt */ 8763 /* nFields */ 28, 8764 /* *fields */ soc_VLAN_0_BCM56560_A0fmt_fields, 8765 /* bits */ 148, 8766 /* flags */ 0, 8767 }, 8768 #endif /* chips */ 8769 8770 #if defined(BCM_56560_B0) 8771 { /* SOC_FORMAT_INT_VLAN_0_BCM56560_B0fmt */ 8772 /* format VLAN_0fmt */ 8773 /* nFields */ 28, 8774 /* *fields */ soc_VLAN_0_BCM56560_A0fmt_fields, 8775 /* bits */ 148, 8776 /* flags */ 0, 8777 }, 8778 #endif /* chips */ 8779 8780 #if defined(BCM_56640_A0) 8781 { /* SOC_FORMAT_INT_VLAN_0_BCM56640_A0fmt */ 8782 /* format VLAN_0fmt */ 8783 /* nFields */ 29, 8784 /* *fields */ soc_VLAN_0_BCM56640_A0fmt_fields, 8785 /* bits */ 166, 8786 /* flags */ 0, 8787 }, 8788 #endif /* chips */ 8789 8790 #if defined(BCM_56670_A0) 8791 { /* SOC_FORMAT_INT_VLAN_0_BCM56670_A0fmt */ 8792 /* format VLAN_0fmt */ 8793 /* nFields */ 28, 8794 /* *fields */ soc_VLAN_0_BCM56560_A0fmt_fields, 8795 /* bits */ 148, 8796 /* flags */ 0, 8797 }, 8798 #endif /* chips */ 8799 8800 #if defined(BCM_56670_B0) 8801 { /* SOC_FORMAT_INT_VLAN_0_BCM56670_B0fmt */ 8802 /* format VLAN_0fmt */ 8803 /* nFields */ 28, 8804 /* *fields */ soc_VLAN_0_BCM56560_A0fmt_fields, 8805 /* bits */ 148, 8806 /* flags */ 0, 8807 }, 8808 #endif /* chips */ 8809 8810 #if defined(BCM_56770_A0) 8811 { /* SOC_FORMAT_INT_VLAN_0_BCM56770_A0fmt */ 8812 /* format VLAN_0fmt */ 8813 /* nFields */ 22, 8814 /* *fields */ soc_VLAN_0_BCM56870_A0fmt_fields, 8815 /* bits */ 133, 8816 /* flags */ 0, 8817 }, 8818 #endif /* chips */ 8819 8820 #if defined(BCM_56840_B0) 8821 { /* SOC_FORMAT_INT_VLAN_0_BCM56840_B0fmt */ 8822 /* format VLAN_0fmt */ 8823 /* nFields */ 21, 8824 /* *fields */ soc_VLAN_0_BCM56840_B0fmt_fields, 8825 /* bits */ 111, 8826 /* flags */ 0, 8827 }, 8828 #endif /* chips */ 8829 8830 #if defined(BCM_56850_A0) 8831 { /* SOC_FORMAT_INT_VLAN_0_BCM56850_A0fmt */ 8832 /* format VLAN_0fmt */ 8833 /* nFields */ 30, 8834 /* *fields */ soc_VLAN_0_BCM56850_A0fmt_fields, 8835 /* bits */ 134, 8836 /* flags */ 0, 8837 }, 8838 #endif /* chips */ 8839 8840 #if defined(BCM_56860_A0) 8841 { /* SOC_FORMAT_INT_VLAN_0_BCM56860_A0fmt */ 8842 /* format VLAN_0fmt */ 8843 /* nFields */ 27, 8844 /* *fields */ soc_VLAN_0_BCM56860_A0fmt_fields, 8845 /* bits */ 134, 8846 /* flags */ 0, 8847 }, 8848 #endif /* chips */ 8849 8850 #if defined(BCM_56870_A0) 8851 { /* SOC_FORMAT_INT_VLAN_0_BCM56870_A0fmt */ 8852 /* format VLAN_0fmt */ 8853 /* nFields */ 22, 8854 /* *fields */ soc_VLAN_0_BCM56870_A0fmt_fields, 8855 /* bits */ 133, 8856 /* flags */ 0, 8857 }, 8858 #endif /* chips */ 8859 8860 #if defined(BCM_56960_A0) 8861 { /* SOC_FORMAT_INT_VLAN_0_BCM56960_A0fmt */ 8862 /* format VLAN_0fmt */ 8863 /* nFields */ 29, 8864 /* *fields */ soc_VLAN_0_BCM56960_A0fmt_fields, 8865 /* bits */ 133, 8866 /* flags */ 0, 8867 }, 8868 #endif /* chips */ 8869 8870 #if defined(BCM_56965_A0) 8871 { /* SOC_FORMAT_INT_VLAN_0_BCM56965_A0fmt */ 8872 /* format VLAN_0fmt */ 8873 /* nFields */ 29, 8874 /* *fields */ soc_VLAN_0_BCM56960_A0fmt_fields, 8875 /* bits */ 133, 8876 /* flags */ 0, 8877 }, 8878 #endif /* chips */ 8879 8880 #if defined(BCM_56260_A0) 8881 { /* SOC_FORMAT_INT_VLAN_1_BCM56260_A0fmt */ 8882 /* format VLAN_1fmt */ 8883 /* nFields */ 6, 8884 /* *fields */ soc_VLAN_1_BCM56260_A0fmt_fields, 8885 /* bits */ 128, 8886 /* flags */ 0, 8887 }, 8888 #endif /* chips */ 8889 8890 #if defined(BCM_56260_B0) 8891 { /* SOC_FORMAT_INT_VLAN_1_BCM56260_B0fmt */ 8892 /* format VLAN_1fmt */ 8893 /* nFields */ 6, 8894 /* *fields */ soc_VLAN_1_BCM56260_A0fmt_fields, 8895 /* bits */ 128, 8896 /* flags */ 0, 8897 }, 8898 #endif /* chips */ 8899 8900 #if defined(BCM_56270_A0) 8901 { /* SOC_FORMAT_INT_VLAN_1_BCM56270_A0fmt */ 8902 /* format VLAN_1fmt */ 8903 /* nFields */ 6, 8904 /* *fields */ soc_VLAN_1_BCM56270_A0fmt_fields, 8905 /* bits */ 64, 8906 /* flags */ 0, 8907 }, 8908 #endif /* chips */ 8909 8910 #if defined(BCM_56340_A0) 8911 { /* SOC_FORMAT_INT_VLAN_1_BCM56340_A0fmt */ 8912 /* format VLAN_1fmt */ 8913 /* nFields */ 10, 8914 /* *fields */ soc_VLAN_1_BCM56640_A0fmt_fields, 8915 /* bits */ 201, 8916 /* flags */ 0, 8917 }, 8918 #endif /* chips */ 8919 8920 #if defined(BCM_56440_A0) 8921 { /* SOC_FORMAT_INT_VLAN_1_BCM56440_A0fmt */ 8922 /* format VLAN_1fmt */ 8923 /* nFields */ 7, 8924 /* *fields */ soc_VLAN_1_BCM56440_A0fmt_fields, 8925 /* bits */ 50, 8926 /* flags */ 0, 8927 }, 8928 #endif /* chips */ 8929 8930 #if defined(BCM_56440_B0) 8931 { /* SOC_FORMAT_INT_VLAN_1_BCM56440_B0fmt */ 8932 /* format VLAN_1fmt */ 8933 /* nFields */ 7, 8934 /* *fields */ soc_VLAN_1_BCM56440_A0fmt_fields, 8935 /* bits */ 50, 8936 /* flags */ 0, 8937 }, 8938 #endif /* chips */ 8939 8940 #if defined(BCM_56450_A0) 8941 { /* SOC_FORMAT_INT_VLAN_1_BCM56450_A0fmt */ 8942 /* format VLAN_1fmt */ 8943 /* nFields */ 6, 8944 /* *fields */ soc_VLAN_1_BCM56450_A0fmt_fields, 8945 /* bits */ 180, 8946 /* flags */ 0, 8947 }, 8948 #endif /* chips */ 8949 8950 #if defined(BCM_56450_B0) 8951 { /* SOC_FORMAT_INT_VLAN_1_BCM56450_B0fmt */ 8952 /* format VLAN_1fmt */ 8953 /* nFields */ 6, 8954 /* *fields */ soc_VLAN_1_BCM56450_A0fmt_fields, 8955 /* bits */ 180, 8956 /* flags */ 0, 8957 }, 8958 #endif /* chips */ 8959 8960 #if defined(BCM_56450_B1) 8961 { /* SOC_FORMAT_INT_VLAN_1_BCM56450_B1fmt */ 8962 /* format VLAN_1fmt */ 8963 /* nFields */ 6, 8964 /* *fields */ soc_VLAN_1_BCM56450_A0fmt_fields, 8965 /* bits */ 180, 8966 /* flags */ 0, 8967 }, 8968 #endif /* chips */ 8969 8970 #if defined(BCM_56560_A0) 8971 { /* SOC_FORMAT_INT_VLAN_1_BCM56560_A0fmt */ 8972 /* format VLAN_1fmt */ 8973 /* nFields */ 5, 8974 /* *fields */ soc_VLAN_1_BCM56560_A0fmt_fields, 8975 /* bits */ 88, 8976 /* flags */ 0, 8977 }, 8978 #endif /* chips */ 8979 8980 #if defined(BCM_56560_B0) 8981 { /* SOC_FORMAT_INT_VLAN_1_BCM56560_B0fmt */ 8982 /* format VLAN_1fmt */ 8983 /* nFields */ 5, 8984 /* *fields */ soc_VLAN_1_BCM56560_A0fmt_fields, 8985 /* bits */ 88, 8986 /* flags */ 0, 8987 }, 8988 #endif /* chips */ 8989 8990 #if defined(BCM_56640_A0) 8991 { /* SOC_FORMAT_INT_VLAN_1_BCM56640_A0fmt */ 8992 /* format VLAN_1fmt */ 8993 /* nFields */ 10, 8994 /* *fields */ soc_VLAN_1_BCM56640_A0fmt_fields, 8995 /* bits */ 201, 8996 /* flags */ 0, 8997 }, 8998 #endif /* chips */ 8999 9000 #if defined(BCM_56670_A0) 9001 { /* SOC_FORMAT_INT_VLAN_1_BCM56670_A0fmt */ 9002 /* format VLAN_1fmt */ 9003 /* nFields */ 5, 9004 /* *fields */ soc_VLAN_1_BCM56670_A0fmt_fields, 9005 /* bits */ 88, 9006 /* flags */ 0, 9007 }, 9008 #endif /* chips */ 9009 9010 #if defined(BCM_56670_B0) 9011 { /* SOC_FORMAT_INT_VLAN_1_BCM56670_B0fmt */ 9012 /* format VLAN_1fmt */ 9013 /* nFields */ 5, 9014 /* *fields */ soc_VLAN_1_BCM56670_A0fmt_fields, 9015 /* bits */ 88, 9016 /* flags */ 0, 9017 }, 9018 #endif /* chips */ 9019 9020 #if defined(BCM_56840_B0) 9021 { /* SOC_FORMAT_INT_VLAN_1_BCM56840_B0fmt */ 9022 /* format VLAN_1fmt */ 9023 /* nFields */ 12, 9024 /* *fields */ soc_VLAN_1_BCM56840_B0fmt_fields, 9025 /* bits */ 207, 9026 /* flags */ 0, 9027 }, 9028 #endif /* chips */ 9029 9030 #if defined(BCM_56850_A0) 9031 { /* SOC_FORMAT_INT_VLAN_1_BCM56850_A0fmt */ 9032 /* format VLAN_1fmt */ 9033 /* nFields */ 6, 9034 /* *fields */ soc_VLAN_1_BCM56850_A0fmt_fields, 9035 /* bits */ 287, 9036 /* flags */ 0, 9037 }, 9038 #endif /* chips */ 9039 9040 #if defined(BCM_56860_A0) 9041 { /* SOC_FORMAT_INT_VLAN_1_BCM56860_A0fmt */ 9042 /* format VLAN_1fmt */ 9043 /* nFields */ 5, 9044 /* *fields */ soc_VLAN_1_BCM56860_A0fmt_fields, 9045 /* bits */ 118, 9046 /* flags */ 0, 9047 }, 9048 #endif /* chips */ 9049 9050 #if defined(BCM_56960_A0) 9051 { /* SOC_FORMAT_INT_VLAN_1_BCM56960_A0fmt */ 9052 /* format VLAN_1fmt */ 9053 /* nFields */ 14, 9054 /* *fields */ soc_VLAN_1_BCM56960_A0fmt_fields, 9055 /* bits */ 351, 9056 /* flags */ 0, 9057 }, 9058 #endif /* chips */ 9059 9060 #if defined(BCM_56965_A0) 9061 { /* SOC_FORMAT_INT_VLAN_1_BCM56965_A0fmt */ 9062 /* format VLAN_1fmt */ 9063 /* nFields */ 14, 9064 /* *fields */ soc_VLAN_1_BCM56960_A0fmt_fields, 9065 /* bits */ 351, 9066 /* flags */ 0, 9067 }, 9068 #endif /* chips */ 9069 9070 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 9071 defined(BCM_56524_B0) || defined(BCM_56634_A0) || \ 9072 defined(BCM_56634_B0) || defined(BCM_56685_A0) || \ 9073 defined(BCM_56840_A0) || defined(BCM_56840_B0) 9074 { /* SOC_FORMAT_INT_VLAN_DROPfmt */ 9075 /* format VLAN_DROPfmt */ 9076 /* nFields */ 3, 9077 /* *fields */ soc_VLAN_DROPfmt_fields, 9078 /* bits */ 3, 9079 /* flags */ 0, 9080 }, 9081 #endif /* chips */ 9082 9083 #if defined(BCM_56260_A0) 9084 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56260_A0fmt */ 9085 /* format VLAN_DROPfmt */ 9086 /* nFields */ 3, 9087 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9088 /* bits */ 3, 9089 /* flags */ 0, 9090 }, 9091 #endif /* chips */ 9092 9093 #if defined(BCM_56260_B0) 9094 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56260_B0fmt */ 9095 /* format VLAN_DROPfmt */ 9096 /* nFields */ 3, 9097 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9098 /* bits */ 3, 9099 /* flags */ 0, 9100 }, 9101 #endif /* chips */ 9102 9103 #if defined(BCM_56270_A0) 9104 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56270_A0fmt */ 9105 /* format VLAN_DROPfmt */ 9106 /* nFields */ 3, 9107 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9108 /* bits */ 3, 9109 /* flags */ 0, 9110 }, 9111 #endif /* chips */ 9112 9113 #if defined(BCM_56340_A0) 9114 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56340_A0fmt */ 9115 /* format VLAN_DROPfmt */ 9116 /* nFields */ 4, 9117 /* *fields */ soc_VLAN_DROP_BCM56640_A0fmt_fields, 9118 /* bits */ 3, 9119 /* flags */ 0, 9120 }, 9121 #endif /* chips */ 9122 9123 #if defined(BCM_56450_A0) 9124 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56450_A0fmt */ 9125 /* format VLAN_DROPfmt */ 9126 /* nFields */ 3, 9127 /* *fields */ soc_VLAN_DROP_BCM56850_A0fmt_fields, 9128 /* bits */ 3, 9129 /* flags */ 0, 9130 }, 9131 #endif /* chips */ 9132 9133 #if defined(BCM_56450_B0) 9134 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56450_B0fmt */ 9135 /* format VLAN_DROPfmt */ 9136 /* nFields */ 3, 9137 /* *fields */ soc_VLAN_DROP_BCM56850_A0fmt_fields, 9138 /* bits */ 3, 9139 /* flags */ 0, 9140 }, 9141 #endif /* chips */ 9142 9143 #if defined(BCM_56450_B1) 9144 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56450_B1fmt */ 9145 /* format VLAN_DROPfmt */ 9146 /* nFields */ 3, 9147 /* *fields */ soc_VLAN_DROP_BCM56850_A0fmt_fields, 9148 /* bits */ 3, 9149 /* flags */ 0, 9150 }, 9151 #endif /* chips */ 9152 9153 #if defined(BCM_56524_A0) 9154 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56524_A0fmt */ 9155 /* format VLAN_DROPfmt */ 9156 /* nFields */ 3, 9157 /* *fields */ soc_VLAN_DROPfmt_fields, 9158 /* bits */ 3, 9159 /* flags */ 0, 9160 }, 9161 #endif /* chips */ 9162 9163 #if defined(BCM_56560_A0) 9164 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56560_A0fmt */ 9165 /* format VLAN_DROPfmt */ 9166 /* nFields */ 3, 9167 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9168 /* bits */ 3, 9169 /* flags */ 0, 9170 }, 9171 #endif /* chips */ 9172 9173 #if defined(BCM_56560_B0) 9174 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56560_B0fmt */ 9175 /* format VLAN_DROPfmt */ 9176 /* nFields */ 3, 9177 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9178 /* bits */ 3, 9179 /* flags */ 0, 9180 }, 9181 #endif /* chips */ 9182 9183 #if defined(BCM_56640_A0) 9184 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56640_A0fmt */ 9185 /* format VLAN_DROPfmt */ 9186 /* nFields */ 4, 9187 /* *fields */ soc_VLAN_DROP_BCM56640_A0fmt_fields, 9188 /* bits */ 3, 9189 /* flags */ 0, 9190 }, 9191 #endif /* chips */ 9192 9193 #if defined(BCM_56670_A0) 9194 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56670_A0fmt */ 9195 /* format VLAN_DROPfmt */ 9196 /* nFields */ 3, 9197 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9198 /* bits */ 3, 9199 /* flags */ 0, 9200 }, 9201 #endif /* chips */ 9202 9203 #if defined(BCM_56670_B0) 9204 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56670_B0fmt */ 9205 /* format VLAN_DROPfmt */ 9206 /* nFields */ 3, 9207 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9208 /* bits */ 3, 9209 /* flags */ 0, 9210 }, 9211 #endif /* chips */ 9212 9213 #if defined(BCM_56685_B0) 9214 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56685_B0fmt */ 9215 /* format VLAN_DROPfmt */ 9216 /* nFields */ 3, 9217 /* *fields */ soc_VLAN_DROPfmt_fields, 9218 /* bits */ 3, 9219 /* flags */ 0, 9220 }, 9221 #endif /* chips */ 9222 9223 #if defined(BCM_56850_A0) 9224 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56850_A0fmt */ 9225 /* format VLAN_DROPfmt */ 9226 /* nFields */ 3, 9227 /* *fields */ soc_VLAN_DROP_BCM56850_A0fmt_fields, 9228 /* bits */ 3, 9229 /* flags */ 0, 9230 }, 9231 #endif /* chips */ 9232 9233 #if defined(BCM_56860_A0) 9234 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56860_A0fmt */ 9235 /* format VLAN_DROPfmt */ 9236 /* nFields */ 3, 9237 /* *fields */ soc_VLAN_DROP_BCM56850_A0fmt_fields, 9238 /* bits */ 3, 9239 /* flags */ 0, 9240 }, 9241 #endif /* chips */ 9242 9243 #if defined(BCM_56960_A0) 9244 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56960_A0fmt */ 9245 /* format VLAN_DROPfmt */ 9246 /* nFields */ 3, 9247 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9248 /* bits */ 3, 9249 /* flags */ 0, 9250 }, 9251 #endif /* chips */ 9252 9253 #if defined(BCM_56965_A0) 9254 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56965_A0fmt */ 9255 /* format VLAN_DROPfmt */ 9256 /* nFields */ 3, 9257 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9258 /* bits */ 3, 9259 /* flags */ 0, 9260 }, 9261 #endif /* chips */ 9262 9263 #if defined(BCM_56970_A0) 9264 { /* SOC_FORMAT_INT_VLAN_DROP_BCM56970_A0fmt */ 9265 /* format VLAN_DROPfmt */ 9266 /* nFields */ 3, 9267 /* *fields */ soc_VLAN_DROP_BCM56960_A0fmt_fields, 9268 /* bits */ 3, 9269 /* flags */ 0, 9270 }, 9271 #endif /* chips */ 9272 9273 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9274 defined(BCM_56870_A0) 9275 { /* SOC_FORMAT_INT_VLAN_DROP_VECTORfmt */ 9276 /* format VLAN_DROP_VECTORfmt */ 9277 /* nFields */ 4, 9278 /* *fields */ soc_VLAN_DROP_VECTORfmt_fields, 9279 /* bits */ 4, 9280 /* flags */ 0, 9281 }, 9282 #endif /* chips */ 9283 9284 #if defined(BCM_56980_A0) 9285 { /* SOC_FORMAT_INT_VLAN_DROP_VECTOR_BCM56980_A0fmt */ 9286 /* format VLAN_DROP_VECTORfmt */ 9287 /* nFields */ 4, 9288 /* *fields */ soc_VLAN_DROP_VECTOR_BCM56980_A0fmt_fields, 9289 /* bits */ 4, 9290 /* flags */ 0, 9291 }, 9292 #endif /* chips */ 9293 9294 #if defined(BCM_56980_B0) 9295 { /* SOC_FORMAT_INT_VLAN_DROP_VECTOR_BCM56980_B0fmt */ 9296 /* format VLAN_DROP_VECTORfmt */ 9297 /* nFields */ 4, 9298 /* *fields */ soc_VLAN_DROP_VECTOR_BCM56980_A0fmt_fields, 9299 /* bits */ 4, 9300 /* flags */ 0, 9301 }, 9302 #endif /* chips */ 9303 9304 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9305 defined(BCM_56870_A0) 9306 { /* SOC_FORMAT_INT_VLAN_HDRfmt */ 9307 /* format VLAN_HDRfmt */ 9308 /* nFields */ 1, 9309 /* *fields */ soc_VLAN_HDRfmt_fields, 9310 /* bits */ 16, 9311 /* flags */ 0, 9312 }, 9313 #endif /* chips */ 9314 9315 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9316 defined(BCM_56870_A0) 9317 { /* SOC_FORMAT_INT_VLAN_TAG_COMPOSITESfmt */ 9318 /* format VLAN_TAG_COMPOSITESfmt */ 9319 /* nFields */ 8, 9320 /* *fields */ soc_VLAN_TAG_COMPOSITESfmt_fields, 9321 /* bits */ 30, 9322 /* flags */ 0, 9323 }, 9324 #endif /* chips */ 9325 9326 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9327 defined(BCM_56870_A0) 9328 { /* SOC_FORMAT_INT_VLAN_TAG_HDRfmt */ 9329 /* format VLAN_TAG_HDRfmt */ 9330 /* nFields */ 3, 9331 /* *fields */ soc_VLAN_TAG_HDRfmt_fields, 9332 /* bits */ 16, 9333 /* flags */ 0, 9334 }, 9335 #endif /* chips */ 9336 9337 #if defined(BCM_56640_A0) 9338 { /* SOC_FORMAT_INT_VLAN_XLATE_1_DATAfmt */ 9339 /* format VLAN_XLATE_1_DATAfmt */ 9340 /* nFields */ 38, 9341 /* *fields */ soc_VLAN_XLATE_1_DATAfmt_fields, 9342 /* bits */ 58, 9343 /* flags */ 0, 9344 }, 9345 #endif /* chips */ 9346 9347 #if defined(BCM_56340_A0) 9348 { /* SOC_FORMAT_INT_VLAN_XLATE_1_DATA_BCM56340_A0fmt */ 9349 /* format VLAN_XLATE_1_DATAfmt */ 9350 /* nFields */ 41, 9351 /* *fields */ soc_VLAN_XLATE_1_DATA_BCM56340_A0fmt_fields, 9352 /* bits */ 58, 9353 /* flags */ 0, 9354 }, 9355 #endif /* chips */ 9356 9357 #if defined(BCM_56640_A0) 9358 { /* SOC_FORMAT_INT_VLAN_XLATE_2_DATAfmt */ 9359 /* format VLAN_XLATE_2_DATAfmt */ 9360 /* nFields */ 32, 9361 /* *fields */ soc_VLAN_XLATE_2_DATAfmt_fields, 9362 /* bits */ 105, 9363 /* flags */ 0, 9364 }, 9365 #endif /* chips */ 9366 9367 #if defined(BCM_56340_A0) 9368 { /* SOC_FORMAT_INT_VLAN_XLATE_2_DATA_BCM56340_A0fmt */ 9369 /* format VLAN_XLATE_2_DATAfmt */ 9370 /* nFields */ 34, 9371 /* *fields */ soc_VLAN_XLATE_2_DATA_BCM56340_A0fmt_fields, 9372 /* bits */ 105, 9373 /* flags */ 0, 9374 }, 9375 #endif /* chips */ 9376 9377 #if defined(BCM_56640_A0) 9378 { /* SOC_FORMAT_INT_VLAN_XLATE_KEYfmt */ 9379 /* format VLAN_XLATE_KEYfmt */ 9380 /* nFields */ 41, 9381 /* *fields */ soc_VLAN_XLATE_KEYfmt_fields, 9382 /* bits */ 53, 9383 /* flags */ 0, 9384 }, 9385 #endif /* chips */ 9386 9387 #if defined(BCM_56340_A0) 9388 { /* SOC_FORMAT_INT_VLAN_XLATE_KEY_BCM56340_A0fmt */ 9389 /* format VLAN_XLATE_KEYfmt */ 9390 /* nFields */ 41, 9391 /* *fields */ soc_VLAN_XLATE_KEY_BCM56340_A0fmt_fields, 9392 /* bits */ 53, 9393 /* flags */ 0, 9394 }, 9395 #endif /* chips */ 9396 9397 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9398 defined(BCM_56870_A0) 9399 { /* SOC_FORMAT_INT_VNTAG_ETAG_ACTION_SETfmt */ 9400 /* format VNTAG_ETAG_ACTION_SETfmt */ 9401 /* nFields */ 16, 9402 /* *fields */ soc_VNTAG_ETAG_ACTION_SETfmt_fields, 9403 /* bits */ 24, 9404 /* flags */ 0, 9405 }, 9406 #endif /* chips */ 9407 9408 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9409 defined(BCM_56870_A0) 9410 { /* SOC_FORMAT_INT_VNTAG_ETAG_ASSIGN_ACTION_SETfmt */ 9411 /* format VNTAG_ETAG_ASSIGN_ACTION_SETfmt */ 9412 /* nFields */ 5, 9413 /* *fields */ soc_VNTAG_ETAG_ASSIGN_ACTION_SETfmt_fields, 9414 /* bits */ 50, 9415 /* flags */ 0, 9416 }, 9417 #endif /* chips */ 9418 9419 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 9420 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 9421 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 9422 defined(BCM_56850_A0) || defined(BCM_56860_A0) 9423 { /* SOC_FORMAT_INT_VNTAG_HDRfmt */ 9424 /* format VNTAG_HDRfmt */ 9425 /* nFields */ 7, 9426 /* *fields */ soc_VNTAG_HDRfmt_fields, 9427 /* bits */ 32, 9428 /* flags */ 0, 9429 }, 9430 #endif /* chips */ 9431 9432 #if defined(BCM_53400_A0) 9433 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM53400_A0fmt */ 9434 /* format VNTAG_HDRfmt */ 9435 /* nFields */ 7, 9436 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9437 /* bits */ 32, 9438 /* flags */ 0, 9439 }, 9440 #endif /* chips */ 9441 9442 #if defined(BCM_53540_A0) 9443 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM53540_A0fmt */ 9444 /* format VNTAG_HDRfmt */ 9445 /* nFields */ 7, 9446 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9447 /* bits */ 32, 9448 /* flags */ 0, 9449 }, 9450 #endif /* chips */ 9451 9452 #if defined(BCM_53570_A0) 9453 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM53570_A0fmt */ 9454 /* format VNTAG_HDRfmt */ 9455 /* nFields */ 7, 9456 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9457 /* bits */ 32, 9458 /* flags */ 0, 9459 }, 9460 #endif /* chips */ 9461 9462 #if defined(BCM_53570_B0) 9463 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM53570_B0fmt */ 9464 /* format VNTAG_HDRfmt */ 9465 /* nFields */ 7, 9466 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9467 /* bits */ 32, 9468 /* flags */ 0, 9469 }, 9470 #endif /* chips */ 9471 9472 #if defined(BCM_56160_A0) 9473 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56160_A0fmt */ 9474 /* format VNTAG_HDRfmt */ 9475 /* nFields */ 7, 9476 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9477 /* bits */ 32, 9478 /* flags */ 0, 9479 }, 9480 #endif /* chips */ 9481 9482 #if defined(BCM_56260_A0) 9483 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56260_A0fmt */ 9484 /* format VNTAG_HDRfmt */ 9485 /* nFields */ 7, 9486 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9487 /* bits */ 32, 9488 /* flags */ 0, 9489 }, 9490 #endif /* chips */ 9491 9492 #if defined(BCM_56260_B0) 9493 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56260_B0fmt */ 9494 /* format VNTAG_HDRfmt */ 9495 /* nFields */ 7, 9496 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9497 /* bits */ 32, 9498 /* flags */ 0, 9499 }, 9500 #endif /* chips */ 9501 9502 #if defined(BCM_56270_A0) 9503 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56270_A0fmt */ 9504 /* format VNTAG_HDRfmt */ 9505 /* nFields */ 7, 9506 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9507 /* bits */ 32, 9508 /* flags */ 0, 9509 }, 9510 #endif /* chips */ 9511 9512 #if defined(BCM_56370_A0) 9513 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56370_A0fmt */ 9514 /* format VNTAG_HDRfmt */ 9515 /* nFields */ 7, 9516 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9517 /* bits */ 32, 9518 /* flags */ 0, 9519 }, 9520 #endif /* chips */ 9521 9522 #if defined(BCM_56560_A0) 9523 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56560_A0fmt */ 9524 /* format VNTAG_HDRfmt */ 9525 /* nFields */ 7, 9526 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9527 /* bits */ 32, 9528 /* flags */ 0, 9529 }, 9530 #endif /* chips */ 9531 9532 #if defined(BCM_56560_B0) 9533 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56560_B0fmt */ 9534 /* format VNTAG_HDRfmt */ 9535 /* nFields */ 7, 9536 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9537 /* bits */ 32, 9538 /* flags */ 0, 9539 }, 9540 #endif /* chips */ 9541 9542 #if defined(BCM_56670_A0) 9543 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56670_A0fmt */ 9544 /* format VNTAG_HDRfmt */ 9545 /* nFields */ 7, 9546 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9547 /* bits */ 32, 9548 /* flags */ 0, 9549 }, 9550 #endif /* chips */ 9551 9552 #if defined(BCM_56670_B0) 9553 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56670_B0fmt */ 9554 /* format VNTAG_HDRfmt */ 9555 /* nFields */ 7, 9556 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9557 /* bits */ 32, 9558 /* flags */ 0, 9559 }, 9560 #endif /* chips */ 9561 9562 #if defined(BCM_56770_A0) 9563 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56770_A0fmt */ 9564 /* format VNTAG_HDRfmt */ 9565 /* nFields */ 7, 9566 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9567 /* bits */ 32, 9568 /* flags */ 0, 9569 }, 9570 #endif /* chips */ 9571 9572 #if defined(BCM_56870_A0) 9573 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56870_A0fmt */ 9574 /* format VNTAG_HDRfmt */ 9575 /* nFields */ 7, 9576 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9577 /* bits */ 32, 9578 /* flags */ 0, 9579 }, 9580 #endif /* chips */ 9581 9582 #if defined(BCM_56960_A0) 9583 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56960_A0fmt */ 9584 /* format VNTAG_HDRfmt */ 9585 /* nFields */ 7, 9586 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9587 /* bits */ 32, 9588 /* flags */ 0, 9589 }, 9590 #endif /* chips */ 9591 9592 #if defined(BCM_56965_A0) 9593 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56965_A0fmt */ 9594 /* format VNTAG_HDRfmt */ 9595 /* nFields */ 7, 9596 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9597 /* bits */ 32, 9598 /* flags */ 0, 9599 }, 9600 #endif /* chips */ 9601 9602 #if defined(BCM_56970_A0) 9603 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56970_A0fmt */ 9604 /* format VNTAG_HDRfmt */ 9605 /* nFields */ 7, 9606 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9607 /* bits */ 32, 9608 /* flags */ 0, 9609 }, 9610 #endif /* chips */ 9611 9612 #if defined(BCM_56980_A0) 9613 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56980_A0fmt */ 9614 /* format VNTAG_HDRfmt */ 9615 /* nFields */ 7, 9616 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9617 /* bits */ 32, 9618 /* flags */ 0, 9619 }, 9620 #endif /* chips */ 9621 9622 #if defined(BCM_56980_B0) 9623 { /* SOC_FORMAT_INT_VNTAG_HDR_BCM56980_B0fmt */ 9624 /* format VNTAG_HDRfmt */ 9625 /* nFields */ 7, 9626 /* *fields */ soc_VNTAG_HDR_BCM53400_A0fmt_fields, 9627 /* bits */ 32, 9628 /* flags */ 0, 9629 }, 9630 #endif /* chips */ 9631 9632 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9633 defined(BCM_56870_A0) 9634 { /* SOC_FORMAT_INT_VPLAG_CONTROLS_ACTION_SETfmt */ 9635 /* format VPLAG_CONTROLS_ACTION_SETfmt */ 9636 /* nFields */ 3, 9637 /* *fields */ soc_VPLAG_CONTROLS_ACTION_SETfmt_fields, 9638 /* bits */ 10, 9639 /* flags */ 0, 9640 }, 9641 #endif /* chips */ 9642 9643 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9644 defined(BCM_56870_A0) 9645 { /* SOC_FORMAT_INT_VSAN_ACTION_SETfmt */ 9646 /* format VSAN_ACTION_SETfmt */ 9647 /* nFields */ 2, 9648 /* *fields */ soc_VSAN_ACTION_SETfmt_fields, 9649 /* bits */ 15, 9650 /* flags */ 0, 9651 }, 9652 #endif /* chips */ 9653 9654 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9655 defined(BCM_56870_A0) 9656 { /* SOC_FORMAT_INT_VXLAN_HDRfmt */ 9657 /* format VXLAN_HDRfmt */ 9658 /* nFields */ 5, 9659 /* *fields */ soc_VXLAN_HDRfmt_fields, 9660 /* bits */ 64, 9661 /* flags */ 0, 9662 }, 9663 #endif /* chips */ 9664 9665 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 9666 { /* SOC_FORMAT_INT_VXLT2_ASSIGNED_TAGS_L3_TYPE_DOPfmt */ 9667 /* format VXLT2_ASSIGNED_TAGS_L3_TYPE_DOPfmt */ 9668 /* nFields */ 8, 9669 /* *fields */ soc_VXLT2_ASSIGNED_TAGS_L3_TYPE_DOPfmt_fields, 9670 /* bits */ 64, 9671 /* flags */ 0, 9672 }, 9673 #endif /* chips */ 9674 9675 #if defined(BCM_56370_A0) 9676 { /* SOC_FORMAT_INT_VXLT2_ASSIGNED_TAGS_L3_TYPE_DOP_BCM56370_A0fmt */ 9677 /* format VXLT2_ASSIGNED_TAGS_L3_TYPE_DOPfmt */ 9678 /* nFields */ 8, 9679 /* *fields */ soc_VXLT2_ASSIGNED_TAGS_L3_TYPE_DOP_BCM56370_A0fmt_fields, 9680 /* bits */ 64, 9681 /* flags */ 0, 9682 }, 9683 #endif /* chips */ 9684 9685 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9686 defined(BCM_56870_A0) 9687 { /* SOC_FORMAT_INT_VXLT_ACTION_SETfmt */ 9688 /* format VXLT_ACTION_SETfmt */ 9689 /* nFields */ 2, 9690 /* *fields */ soc_VXLT_ACTION_SETfmt_fields, 9691 /* bits */ 16, 9692 /* flags */ 0, 9693 }, 9694 #endif /* chips */ 9695 9696 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9697 defined(BCM_56870_A0) 9698 { /* SOC_FORMAT_INT_VXLT_CTRL_ID_SEL_ENCODING_FORMATfmt */ 9699 /* format VXLT_CTRL_ID_SEL_ENCODING_FORMATfmt */ 9700 /* nFields */ 1, 9701 /* *fields */ soc_VXLT_CTRL_ID_SEL_ENCODING_FORMATfmt_fields, 9702 /* bits */ 4, 9703 /* flags */ 0, 9704 }, 9705 #endif /* chips */ 9706 9707 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9708 defined(BCM_56870_A0) 9709 { /* SOC_FORMAT_INT_VXLT_DROP_VECTORfmt */ 9710 /* format VXLT_DROP_VECTORfmt */ 9711 /* nFields */ 6, 9712 /* *fields */ soc_VXLT_DROP_VECTORfmt_fields, 9713 /* bits */ 6, 9714 /* flags */ 0, 9715 }, 9716 #endif /* chips */ 9717