allformats_u.i (17094B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_u.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56840_A0) 16 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODINGfmt */ 17 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 18 /* nFields */ 1, 19 /* *fields */ soc_UDF_BASE_OFFSET_ENCODINGfmt_fields, 20 /* bits */ 3, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_56260_A0) 26 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56260_A0fmt */ 27 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 28 /* nFields */ 1, 29 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 30 /* bits */ 3, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_56260_B0) 36 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56260_B0fmt */ 37 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 38 /* nFields */ 1, 39 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 40 /* bits */ 3, 41 /* flags */ 0, 42 }, 43 #endif /* chips */ 44 45 #if defined(BCM_56270_A0) 46 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56270_A0fmt */ 47 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 48 /* nFields */ 1, 49 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 50 /* bits */ 3, 51 /* flags */ 0, 52 }, 53 #endif /* chips */ 54 55 #if defined(BCM_56340_A0) 56 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56340_A0fmt */ 57 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 58 /* nFields */ 1, 59 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields, 60 /* bits */ 3, 61 /* flags */ 0, 62 }, 63 #endif /* chips */ 64 65 #if defined(BCM_56370_A0) 66 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56370_A0fmt */ 67 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 68 /* nFields */ 1, 69 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 70 /* bits */ 3, 71 /* flags */ 0, 72 }, 73 #endif /* chips */ 74 75 #if defined(BCM_56440_A0) 76 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56440_A0fmt */ 77 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 78 /* nFields */ 1, 79 /* *fields */ soc_UDF_BASE_OFFSET_ENCODINGfmt_fields, 80 /* bits */ 3, 81 /* flags */ 0, 82 }, 83 #endif /* chips */ 84 85 #if defined(BCM_56440_B0) 86 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56440_B0fmt */ 87 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 88 /* nFields */ 1, 89 /* *fields */ soc_UDF_BASE_OFFSET_ENCODINGfmt_fields, 90 /* bits */ 3, 91 /* flags */ 0, 92 }, 93 #endif /* chips */ 94 95 #if defined(BCM_56450_A0) 96 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56450_A0fmt */ 97 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 98 /* nFields */ 1, 99 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields, 100 /* bits */ 3, 101 /* flags */ 0, 102 }, 103 #endif /* chips */ 104 105 #if defined(BCM_56450_B0) 106 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56450_B0fmt */ 107 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 108 /* nFields */ 1, 109 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields, 110 /* bits */ 3, 111 /* flags */ 0, 112 }, 113 #endif /* chips */ 114 115 #if defined(BCM_56450_B1) 116 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56450_B1fmt */ 117 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 118 /* nFields */ 1, 119 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields, 120 /* bits */ 3, 121 /* flags */ 0, 122 }, 123 #endif /* chips */ 124 125 #if defined(BCM_56560_A0) 126 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56560_A0fmt */ 127 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 128 /* nFields */ 1, 129 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 130 /* bits */ 3, 131 /* flags */ 0, 132 }, 133 #endif /* chips */ 134 135 #if defined(BCM_56560_B0) 136 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56560_B0fmt */ 137 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 138 /* nFields */ 1, 139 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 140 /* bits */ 3, 141 /* flags */ 0, 142 }, 143 #endif /* chips */ 144 145 #if defined(BCM_56640_A0) 146 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt */ 147 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 148 /* nFields */ 1, 149 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields, 150 /* bits */ 3, 151 /* flags */ 0, 152 }, 153 #endif /* chips */ 154 155 #if defined(BCM_56670_A0) 156 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56670_A0fmt */ 157 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 158 /* nFields */ 1, 159 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 160 /* bits */ 3, 161 /* flags */ 0, 162 }, 163 #endif /* chips */ 164 165 #if defined(BCM_56670_B0) 166 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56670_B0fmt */ 167 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 168 /* nFields */ 1, 169 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 170 /* bits */ 3, 171 /* flags */ 0, 172 }, 173 #endif /* chips */ 174 175 #if defined(BCM_56770_A0) 176 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56770_A0fmt */ 177 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 178 /* nFields */ 1, 179 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 180 /* bits */ 3, 181 /* flags */ 0, 182 }, 183 #endif /* chips */ 184 185 #if defined(BCM_56840_B0) 186 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56840_B0fmt */ 187 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 188 /* nFields */ 1, 189 /* *fields */ soc_UDF_BASE_OFFSET_ENCODINGfmt_fields, 190 /* bits */ 3, 191 /* flags */ 0, 192 }, 193 #endif /* chips */ 194 195 #if defined(BCM_56850_A0) 196 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56850_A0fmt */ 197 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 198 /* nFields */ 1, 199 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields, 200 /* bits */ 3, 201 /* flags */ 0, 202 }, 203 #endif /* chips */ 204 205 #if defined(BCM_56860_A0) 206 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56860_A0fmt */ 207 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 208 /* nFields */ 1, 209 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56640_A0fmt_fields, 210 /* bits */ 3, 211 /* flags */ 0, 212 }, 213 #endif /* chips */ 214 215 #if defined(BCM_56870_A0) 216 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56870_A0fmt */ 217 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 218 /* nFields */ 1, 219 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 220 /* bits */ 3, 221 /* flags */ 0, 222 }, 223 #endif /* chips */ 224 225 #if defined(BCM_56960_A0) 226 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt */ 227 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 228 /* nFields */ 1, 229 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 230 /* bits */ 3, 231 /* flags */ 0, 232 }, 233 #endif /* chips */ 234 235 #if defined(BCM_56965_A0) 236 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56965_A0fmt */ 237 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 238 /* nFields */ 1, 239 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 240 /* bits */ 3, 241 /* flags */ 0, 242 }, 243 #endif /* chips */ 244 245 #if defined(BCM_56970_A0) 246 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56970_A0fmt */ 247 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 248 /* nFields */ 1, 249 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 250 /* bits */ 3, 251 /* flags */ 0, 252 }, 253 #endif /* chips */ 254 255 #if defined(BCM_56980_A0) 256 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56980_A0fmt */ 257 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 258 /* nFields */ 1, 259 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 260 /* bits */ 3, 261 /* flags */ 0, 262 }, 263 #endif /* chips */ 264 265 #if defined(BCM_56980_B0) 266 { /* SOC_FORMAT_INT_UDF_BASE_OFFSET_ENCODING_BCM56980_B0fmt */ 267 /* format UDF_BASE_OFFSET_ENCODINGfmt */ 268 /* nFields */ 1, 269 /* *fields */ soc_UDF_BASE_OFFSET_ENCODING_BCM56960_A0fmt_fields, 270 /* bits */ 3, 271 /* flags */ 0, 272 }, 273 #endif /* chips */ 274 275 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 276 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 277 defined(BCM_56970_A0) 278 { /* SOC_FORMAT_INT_UDF_TCAM_KEYfmt */ 279 /* format UDF_TCAM_KEYfmt */ 280 /* nFields */ 15, 281 /* *fields */ soc_UDF_TCAM_KEYfmt_fields, 282 /* bits */ 80, 283 /* flags */ 0, 284 }, 285 #endif /* chips */ 286 287 #if defined(BCM_56370_A0) 288 { /* SOC_FORMAT_INT_UDF_TCAM_KEY_BCM56370_A0fmt */ 289 /* format UDF_TCAM_KEYfmt */ 290 /* nFields */ 16, 291 /* *fields */ soc_UDF_TCAM_KEY_BCM56370_A0fmt_fields, 292 /* bits */ 134, 293 /* flags */ 0, 294 }, 295 #endif /* chips */ 296 297 #if defined(BCM_56980_A0) 298 { /* SOC_FORMAT_INT_UDF_TCAM_KEY_BCM56980_A0fmt */ 299 /* format UDF_TCAM_KEYfmt */ 300 /* nFields */ 13, 301 /* *fields */ soc_UDF_TCAM_KEY_BCM56980_A0fmt_fields, 302 /* bits */ 80, 303 /* flags */ 0, 304 }, 305 #endif /* chips */ 306 307 #if defined(BCM_56980_B0) 308 { /* SOC_FORMAT_INT_UDF_TCAM_KEY_BCM56980_B0fmt */ 309 /* format UDF_TCAM_KEYfmt */ 310 /* nFields */ 13, 311 /* *fields */ soc_UDF_TCAM_KEY_BCM56980_A0fmt_fields, 312 /* bits */ 80, 313 /* flags */ 0, 314 }, 315 #endif /* chips */ 316 317 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 318 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 319 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 320 defined(BCM_56850_A0) || defined(BCM_56860_A0) 321 { /* SOC_FORMAT_INT_UDP_HDRfmt */ 322 /* format UDP_HDRfmt */ 323 /* nFields */ 4, 324 /* *fields */ soc_UDP_HDRfmt_fields, 325 /* bits */ 64, 326 /* flags */ 0, 327 }, 328 #endif /* chips */ 329 330 #if defined(BCM_53400_A0) 331 { /* SOC_FORMAT_INT_UDP_HDR_BCM53400_A0fmt */ 332 /* format UDP_HDRfmt */ 333 /* nFields */ 4, 334 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 335 /* bits */ 64, 336 /* flags */ 0, 337 }, 338 #endif /* chips */ 339 340 #if defined(BCM_53540_A0) 341 { /* SOC_FORMAT_INT_UDP_HDR_BCM53540_A0fmt */ 342 /* format UDP_HDRfmt */ 343 /* nFields */ 4, 344 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 345 /* bits */ 64, 346 /* flags */ 0, 347 }, 348 #endif /* chips */ 349 350 #if defined(BCM_53570_A0) 351 { /* SOC_FORMAT_INT_UDP_HDR_BCM53570_A0fmt */ 352 /* format UDP_HDRfmt */ 353 /* nFields */ 4, 354 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 355 /* bits */ 64, 356 /* flags */ 0, 357 }, 358 #endif /* chips */ 359 360 #if defined(BCM_53570_B0) 361 { /* SOC_FORMAT_INT_UDP_HDR_BCM53570_B0fmt */ 362 /* format UDP_HDRfmt */ 363 /* nFields */ 4, 364 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 365 /* bits */ 64, 366 /* flags */ 0, 367 }, 368 #endif /* chips */ 369 370 #if defined(BCM_56160_A0) 371 { /* SOC_FORMAT_INT_UDP_HDR_BCM56160_A0fmt */ 372 /* format UDP_HDRfmt */ 373 /* nFields */ 4, 374 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 375 /* bits */ 64, 376 /* flags */ 0, 377 }, 378 #endif /* chips */ 379 380 #if defined(BCM_56260_A0) 381 { /* SOC_FORMAT_INT_UDP_HDR_BCM56260_A0fmt */ 382 /* format UDP_HDRfmt */ 383 /* nFields */ 4, 384 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 385 /* bits */ 64, 386 /* flags */ 0, 387 }, 388 #endif /* chips */ 389 390 #if defined(BCM_56260_B0) 391 { /* SOC_FORMAT_INT_UDP_HDR_BCM56260_B0fmt */ 392 /* format UDP_HDRfmt */ 393 /* nFields */ 4, 394 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 395 /* bits */ 64, 396 /* flags */ 0, 397 }, 398 #endif /* chips */ 399 400 #if defined(BCM_56270_A0) 401 { /* SOC_FORMAT_INT_UDP_HDR_BCM56270_A0fmt */ 402 /* format UDP_HDRfmt */ 403 /* nFields */ 4, 404 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 405 /* bits */ 64, 406 /* flags */ 0, 407 }, 408 #endif /* chips */ 409 410 #if defined(BCM_56370_A0) 411 { /* SOC_FORMAT_INT_UDP_HDR_BCM56370_A0fmt */ 412 /* format UDP_HDRfmt */ 413 /* nFields */ 4, 414 /* *fields */ soc_UDP_HDR_BCM56870_A0fmt_fields, 415 /* bits */ 64, 416 /* flags */ 0, 417 }, 418 #endif /* chips */ 419 420 #if defined(BCM_56560_A0) 421 { /* SOC_FORMAT_INT_UDP_HDR_BCM56560_A0fmt */ 422 /* format UDP_HDRfmt */ 423 /* nFields */ 4, 424 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 425 /* bits */ 64, 426 /* flags */ 0, 427 }, 428 #endif /* chips */ 429 430 #if defined(BCM_56560_B0) 431 { /* SOC_FORMAT_INT_UDP_HDR_BCM56560_B0fmt */ 432 /* format UDP_HDRfmt */ 433 /* nFields */ 4, 434 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 435 /* bits */ 64, 436 /* flags */ 0, 437 }, 438 #endif /* chips */ 439 440 #if defined(BCM_56670_A0) 441 { /* SOC_FORMAT_INT_UDP_HDR_BCM56670_A0fmt */ 442 /* format UDP_HDRfmt */ 443 /* nFields */ 4, 444 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 445 /* bits */ 64, 446 /* flags */ 0, 447 }, 448 #endif /* chips */ 449 450 #if defined(BCM_56670_B0) 451 { /* SOC_FORMAT_INT_UDP_HDR_BCM56670_B0fmt */ 452 /* format UDP_HDRfmt */ 453 /* nFields */ 4, 454 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 455 /* bits */ 64, 456 /* flags */ 0, 457 }, 458 #endif /* chips */ 459 460 #if defined(BCM_56770_A0) 461 { /* SOC_FORMAT_INT_UDP_HDR_BCM56770_A0fmt */ 462 /* format UDP_HDRfmt */ 463 /* nFields */ 4, 464 /* *fields */ soc_UDP_HDR_BCM56870_A0fmt_fields, 465 /* bits */ 64, 466 /* flags */ 0, 467 }, 468 #endif /* chips */ 469 470 #if defined(BCM_56870_A0) 471 { /* SOC_FORMAT_INT_UDP_HDR_BCM56870_A0fmt */ 472 /* format UDP_HDRfmt */ 473 /* nFields */ 4, 474 /* *fields */ soc_UDP_HDR_BCM56870_A0fmt_fields, 475 /* bits */ 64, 476 /* flags */ 0, 477 }, 478 #endif /* chips */ 479 480 #if defined(BCM_56960_A0) 481 { /* SOC_FORMAT_INT_UDP_HDR_BCM56960_A0fmt */ 482 /* format UDP_HDRfmt */ 483 /* nFields */ 4, 484 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 485 /* bits */ 64, 486 /* flags */ 0, 487 }, 488 #endif /* chips */ 489 490 #if defined(BCM_56965_A0) 491 { /* SOC_FORMAT_INT_UDP_HDR_BCM56965_A0fmt */ 492 /* format UDP_HDRfmt */ 493 /* nFields */ 4, 494 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 495 /* bits */ 64, 496 /* flags */ 0, 497 }, 498 #endif /* chips */ 499 500 #if defined(BCM_56970_A0) 501 { /* SOC_FORMAT_INT_UDP_HDR_BCM56970_A0fmt */ 502 /* format UDP_HDRfmt */ 503 /* nFields */ 4, 504 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 505 /* bits */ 64, 506 /* flags */ 0, 507 }, 508 #endif /* chips */ 509 510 #if defined(BCM_56980_A0) 511 { /* SOC_FORMAT_INT_UDP_HDR_BCM56980_A0fmt */ 512 /* format UDP_HDRfmt */ 513 /* nFields */ 4, 514 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 515 /* bits */ 64, 516 /* flags */ 0, 517 }, 518 #endif /* chips */ 519 520 #if defined(BCM_56980_B0) 521 { /* SOC_FORMAT_INT_UDP_HDR_BCM56980_B0fmt */ 522 /* format UDP_HDRfmt */ 523 /* nFields */ 4, 524 /* *fields */ soc_UDP_HDR_BCM53400_A0fmt_fields, 525 /* bits */ 64, 526 /* flags */ 0, 527 }, 528 #endif /* chips */ 529