allformats_r.i (180037B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_r.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56504_A0) 16 { /* SOC_FORMAT_INT_RDBGC_TRIGGERSfmt */ 17 /* format RDBGC_TRIGGERSfmt */ 18 /* nFields */ 27, 19 /* *fields */ soc_RDBGC_TRIGGERSfmt_fields, 20 /* bits */ 27, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_53314_A0) 26 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM53314_A0fmt */ 27 /* format RDBGC_TRIGGERSfmt */ 28 /* nFields */ 31, 29 /* *fields */ soc_RDBGC_TRIGGERS_BCM56224_A0fmt_fields, 30 /* bits */ 31, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_53324_A0) 36 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM53324_A0fmt */ 37 /* format RDBGC_TRIGGERSfmt */ 38 /* nFields */ 31, 39 /* *fields */ soc_RDBGC_TRIGGERS_BCM56224_A0fmt_fields, 40 /* bits */ 31, 41 /* flags */ 0, 42 }, 43 #endif /* chips */ 44 45 #if defined(BCM_53400_A0) 46 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM53400_A0fmt */ 47 /* format RDBGC_TRIGGERSfmt */ 48 /* nFields */ 45, 49 /* *fields */ soc_RDBGC_TRIGGERS_BCM53400_A0fmt_fields, 50 /* bits */ 43, 51 /* flags */ 0, 52 }, 53 #endif /* chips */ 54 55 #if defined(BCM_53540_A0) 56 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM53540_A0fmt */ 57 /* format RDBGC_TRIGGERSfmt */ 58 /* nFields */ 46, 59 /* *fields */ soc_RDBGC_TRIGGERS_BCM56160_A0fmt_fields, 60 /* bits */ 44, 61 /* flags */ 0, 62 }, 63 #endif /* chips */ 64 65 #if defined(BCM_53570_A0) 66 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM53570_A0fmt */ 67 /* format RDBGC_TRIGGERSfmt */ 68 /* nFields */ 46, 69 /* *fields */ soc_RDBGC_TRIGGERS_BCM56160_A0fmt_fields, 70 /* bits */ 44, 71 /* flags */ 0, 72 }, 73 #endif /* chips */ 74 75 #if defined(BCM_53570_B0) 76 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM53570_B0fmt */ 77 /* format RDBGC_TRIGGERSfmt */ 78 /* nFields */ 46, 79 /* *fields */ soc_RDBGC_TRIGGERS_BCM56160_A0fmt_fields, 80 /* bits */ 44, 81 /* flags */ 0, 82 }, 83 #endif /* chips */ 84 85 #if defined(BCM_56142_A0) 86 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56142_A0fmt */ 87 /* format RDBGC_TRIGGERSfmt */ 88 /* nFields */ 43, 89 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 90 /* bits */ 41, 91 /* flags */ 0, 92 }, 93 #endif /* chips */ 94 95 #if defined(BCM_56150_A0) 96 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56150_A0fmt */ 97 /* format RDBGC_TRIGGERSfmt */ 98 /* nFields */ 43, 99 /* *fields */ soc_RDBGC_TRIGGERS_BCM56150_A0fmt_fields, 100 /* bits */ 41, 101 /* flags */ 0, 102 }, 103 #endif /* chips */ 104 105 #if defined(BCM_56160_A0) 106 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56160_A0fmt */ 107 /* format RDBGC_TRIGGERSfmt */ 108 /* nFields */ 46, 109 /* *fields */ soc_RDBGC_TRIGGERS_BCM56160_A0fmt_fields, 110 /* bits */ 44, 111 /* flags */ 0, 112 }, 113 #endif /* chips */ 114 115 #if defined(BCM_56224_A0) 116 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56224_A0fmt */ 117 /* format RDBGC_TRIGGERSfmt */ 118 /* nFields */ 31, 119 /* *fields */ soc_RDBGC_TRIGGERS_BCM56224_A0fmt_fields, 120 /* bits */ 31, 121 /* flags */ 0, 122 }, 123 #endif /* chips */ 124 125 #if defined(BCM_56224_B0) 126 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56224_B0fmt */ 127 /* format RDBGC_TRIGGERSfmt */ 128 /* nFields */ 31, 129 /* *fields */ soc_RDBGC_TRIGGERS_BCM56224_A0fmt_fields, 130 /* bits */ 31, 131 /* flags */ 0, 132 }, 133 #endif /* chips */ 134 135 #if defined(BCM_56260_A0) 136 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56260_A0fmt */ 137 /* format RDBGC_TRIGGERSfmt */ 138 /* nFields */ 66, 139 /* *fields */ soc_RDBGC_TRIGGERS_BCM56260_A0fmt_fields, 140 /* bits */ 64, 141 /* flags */ 0, 142 }, 143 #endif /* chips */ 144 145 #if defined(BCM_56260_B0) 146 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56260_B0fmt */ 147 /* format RDBGC_TRIGGERSfmt */ 148 /* nFields */ 66, 149 /* *fields */ soc_RDBGC_TRIGGERS_BCM56260_A0fmt_fields, 150 /* bits */ 64, 151 /* flags */ 0, 152 }, 153 #endif /* chips */ 154 155 #if defined(BCM_56270_A0) 156 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56270_A0fmt */ 157 /* format RDBGC_TRIGGERSfmt */ 158 /* nFields */ 66, 159 /* *fields */ soc_RDBGC_TRIGGERS_BCM56260_A0fmt_fields, 160 /* bits */ 64, 161 /* flags */ 0, 162 }, 163 #endif /* chips */ 164 165 #if defined(BCM_56314_A0) 166 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56314_A0fmt */ 167 /* format RDBGC_TRIGGERSfmt */ 168 /* nFields */ 29, 169 /* *fields */ soc_RDBGC_TRIGGERS_BCM56504_B0fmt_fields, 170 /* bits */ 29, 171 /* flags */ 0, 172 }, 173 #endif /* chips */ 174 175 #if defined(BCM_56334_A0) 176 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56334_A0fmt */ 177 /* format RDBGC_TRIGGERSfmt */ 178 /* nFields */ 43, 179 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 180 /* bits */ 41, 181 /* flags */ 0, 182 }, 183 #endif /* chips */ 184 185 #if defined(BCM_56334_B0) 186 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56334_B0fmt */ 187 /* format RDBGC_TRIGGERSfmt */ 188 /* nFields */ 43, 189 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 190 /* bits */ 41, 191 /* flags */ 0, 192 }, 193 #endif /* chips */ 194 195 #if defined(BCM_56340_A0) 196 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56340_A0fmt */ 197 /* format RDBGC_TRIGGERSfmt */ 198 /* nFields */ 61, 199 /* *fields */ soc_RDBGC_TRIGGERS_BCM56640_A0fmt_fields, 200 /* bits */ 59, 201 /* flags */ 0, 202 }, 203 #endif /* chips */ 204 205 #if defined(BCM_56440_A0) 206 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56440_A0fmt */ 207 /* format RDBGC_TRIGGERSfmt */ 208 /* nFields */ 56, 209 /* *fields */ soc_RDBGC_TRIGGERS_BCM56440_A0fmt_fields, 210 /* bits */ 54, 211 /* flags */ 0, 212 }, 213 #endif /* chips */ 214 215 #if defined(BCM_56440_B0) 216 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56440_B0fmt */ 217 /* format RDBGC_TRIGGERSfmt */ 218 /* nFields */ 56, 219 /* *fields */ soc_RDBGC_TRIGGERS_BCM56440_A0fmt_fields, 220 /* bits */ 54, 221 /* flags */ 0, 222 }, 223 #endif /* chips */ 224 225 #if defined(BCM_56450_A0) 226 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56450_A0fmt */ 227 /* format RDBGC_TRIGGERSfmt */ 228 /* nFields */ 65, 229 /* *fields */ soc_RDBGC_TRIGGERS_BCM56450_A0fmt_fields, 230 /* bits */ 63, 231 /* flags */ 0, 232 }, 233 #endif /* chips */ 234 235 #if defined(BCM_56450_B0) 236 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56450_B0fmt */ 237 /* format RDBGC_TRIGGERSfmt */ 238 /* nFields */ 65, 239 /* *fields */ soc_RDBGC_TRIGGERS_BCM56450_A0fmt_fields, 240 /* bits */ 63, 241 /* flags */ 0, 242 }, 243 #endif /* chips */ 244 245 #if defined(BCM_56450_B1) 246 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56450_B1fmt */ 247 /* format RDBGC_TRIGGERSfmt */ 248 /* nFields */ 65, 249 /* *fields */ soc_RDBGC_TRIGGERS_BCM56450_A0fmt_fields, 250 /* bits */ 63, 251 /* flags */ 0, 252 }, 253 #endif /* chips */ 254 255 #if defined(BCM_56504_B0) 256 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56504_B0fmt */ 257 /* format RDBGC_TRIGGERSfmt */ 258 /* nFields */ 29, 259 /* *fields */ soc_RDBGC_TRIGGERS_BCM56504_B0fmt_fields, 260 /* bits */ 29, 261 /* flags */ 0, 262 }, 263 #endif /* chips */ 264 265 #if defined(BCM_56514_A0) 266 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56514_A0fmt */ 267 /* format RDBGC_TRIGGERSfmt */ 268 /* nFields */ 32, 269 /* *fields */ soc_RDBGC_TRIGGERS_BCM56514_A0fmt_fields, 270 /* bits */ 32, 271 /* flags */ 0, 272 }, 273 #endif /* chips */ 274 275 #if defined(BCM_56524_A0) 276 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56524_A0fmt */ 277 /* format RDBGC_TRIGGERSfmt */ 278 /* nFields */ 45, 279 /* *fields */ soc_RDBGC_TRIGGERS_BCM56634_A0fmt_fields, 280 /* bits */ 43, 281 /* flags */ 0, 282 }, 283 #endif /* chips */ 284 285 #if defined(BCM_56524_B0) 286 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56524_B0fmt */ 287 /* format RDBGC_TRIGGERSfmt */ 288 /* nFields */ 45, 289 /* *fields */ soc_RDBGC_TRIGGERS_BCM56634_A0fmt_fields, 290 /* bits */ 43, 291 /* flags */ 0, 292 }, 293 #endif /* chips */ 294 295 #if defined(BCM_56560_A0) 296 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56560_A0fmt */ 297 /* format RDBGC_TRIGGERSfmt */ 298 /* nFields */ 67, 299 /* *fields */ soc_RDBGC_TRIGGERS_BCM56560_A0fmt_fields, 300 /* bits */ 65, 301 /* flags */ 0, 302 }, 303 #endif /* chips */ 304 305 #if defined(BCM_56560_B0) 306 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56560_B0fmt */ 307 /* format RDBGC_TRIGGERSfmt */ 308 /* nFields */ 67, 309 /* *fields */ soc_RDBGC_TRIGGERS_BCM56560_A0fmt_fields, 310 /* bits */ 65, 311 /* flags */ 0, 312 }, 313 #endif /* chips */ 314 315 #if defined(BCM_56624_A0) 316 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56624_A0fmt */ 317 /* format RDBGC_TRIGGERSfmt */ 318 /* nFields */ 43, 319 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 320 /* bits */ 41, 321 /* flags */ 0, 322 }, 323 #endif /* chips */ 324 325 #if defined(BCM_56624_B0) 326 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56624_B0fmt */ 327 /* format RDBGC_TRIGGERSfmt */ 328 /* nFields */ 43, 329 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 330 /* bits */ 41, 331 /* flags */ 0, 332 }, 333 #endif /* chips */ 334 335 #if defined(BCM_56634_A0) 336 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56634_A0fmt */ 337 /* format RDBGC_TRIGGERSfmt */ 338 /* nFields */ 45, 339 /* *fields */ soc_RDBGC_TRIGGERS_BCM56634_A0fmt_fields, 340 /* bits */ 43, 341 /* flags */ 0, 342 }, 343 #endif /* chips */ 344 345 #if defined(BCM_56634_B0) 346 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56634_B0fmt */ 347 /* format RDBGC_TRIGGERSfmt */ 348 /* nFields */ 45, 349 /* *fields */ soc_RDBGC_TRIGGERS_BCM56634_A0fmt_fields, 350 /* bits */ 43, 351 /* flags */ 0, 352 }, 353 #endif /* chips */ 354 355 #if defined(BCM_56640_A0) 356 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56640_A0fmt */ 357 /* format RDBGC_TRIGGERSfmt */ 358 /* nFields */ 61, 359 /* *fields */ soc_RDBGC_TRIGGERS_BCM56640_A0fmt_fields, 360 /* bits */ 59, 361 /* flags */ 0, 362 }, 363 #endif /* chips */ 364 365 #if defined(BCM_56670_A0) 366 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56670_A0fmt */ 367 /* format RDBGC_TRIGGERSfmt */ 368 /* nFields */ 67, 369 /* *fields */ soc_RDBGC_TRIGGERS_BCM56560_A0fmt_fields, 370 /* bits */ 65, 371 /* flags */ 0, 372 }, 373 #endif /* chips */ 374 375 #if defined(BCM_56670_B0) 376 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56670_B0fmt */ 377 /* format RDBGC_TRIGGERSfmt */ 378 /* nFields */ 67, 379 /* *fields */ soc_RDBGC_TRIGGERS_BCM56560_A0fmt_fields, 380 /* bits */ 65, 381 /* flags */ 0, 382 }, 383 #endif /* chips */ 384 385 #if defined(BCM_56680_A0) 386 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56680_A0fmt */ 387 /* format RDBGC_TRIGGERSfmt */ 388 /* nFields */ 43, 389 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 390 /* bits */ 41, 391 /* flags */ 0, 392 }, 393 #endif /* chips */ 394 395 #if defined(BCM_56680_B0) 396 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56680_B0fmt */ 397 /* format RDBGC_TRIGGERSfmt */ 398 /* nFields */ 43, 399 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 400 /* bits */ 41, 401 /* flags */ 0, 402 }, 403 #endif /* chips */ 404 405 #if defined(BCM_56685_A0) 406 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56685_A0fmt */ 407 /* format RDBGC_TRIGGERSfmt */ 408 /* nFields */ 45, 409 /* *fields */ soc_RDBGC_TRIGGERS_BCM56634_A0fmt_fields, 410 /* bits */ 43, 411 /* flags */ 0, 412 }, 413 #endif /* chips */ 414 415 #if defined(BCM_56685_B0) 416 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56685_B0fmt */ 417 /* format RDBGC_TRIGGERSfmt */ 418 /* nFields */ 45, 419 /* *fields */ soc_RDBGC_TRIGGERS_BCM56634_A0fmt_fields, 420 /* bits */ 43, 421 /* flags */ 0, 422 }, 423 #endif /* chips */ 424 425 #if defined(BCM_56725_A0) 426 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56725_A0fmt */ 427 /* format RDBGC_TRIGGERSfmt */ 428 /* nFields */ 43, 429 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 430 /* bits */ 41, 431 /* flags */ 0, 432 }, 433 #endif /* chips */ 434 435 #if defined(BCM_56800_A0) 436 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56800_A0fmt */ 437 /* format RDBGC_TRIGGERSfmt */ 438 /* nFields */ 34, 439 /* *fields */ soc_RDBGC_TRIGGERS_BCM56800_A0fmt_fields, 440 /* bits */ 32, 441 /* flags */ 0, 442 }, 443 #endif /* chips */ 444 445 #if defined(BCM_56820_A0) 446 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56820_A0fmt */ 447 /* format RDBGC_TRIGGERSfmt */ 448 /* nFields */ 43, 449 /* *fields */ soc_RDBGC_TRIGGERS_BCM56624_A0fmt_fields, 450 /* bits */ 41, 451 /* flags */ 0, 452 }, 453 #endif /* chips */ 454 455 #if defined(BCM_56840_A0) 456 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56840_A0fmt */ 457 /* format RDBGC_TRIGGERSfmt */ 458 /* nFields */ 52, 459 /* *fields */ soc_RDBGC_TRIGGERS_BCM56840_A0fmt_fields, 460 /* bits */ 51, 461 /* flags */ 0, 462 }, 463 #endif /* chips */ 464 465 #if defined(BCM_56840_B0) 466 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56840_B0fmt */ 467 /* format RDBGC_TRIGGERSfmt */ 468 /* nFields */ 53, 469 /* *fields */ soc_RDBGC_TRIGGERS_BCM56840_B0fmt_fields, 470 /* bits */ 52, 471 /* flags */ 0, 472 }, 473 #endif /* chips */ 474 475 #if defined(BCM_56850_A0) 476 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56850_A0fmt */ 477 /* format RDBGC_TRIGGERSfmt */ 478 /* nFields */ 62, 479 /* *fields */ soc_RDBGC_TRIGGERS_BCM56850_A0fmt_fields, 480 /* bits */ 64, 481 /* flags */ 0, 482 }, 483 #endif /* chips */ 484 485 #if defined(BCM_56860_A0) 486 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56860_A0fmt */ 487 /* format RDBGC_TRIGGERSfmt */ 488 /* nFields */ 66, 489 /* *fields */ soc_RDBGC_TRIGGERS_BCM56860_A0fmt_fields, 490 /* bits */ 64, 491 /* flags */ 0, 492 }, 493 #endif /* chips */ 494 495 #if defined(BCM_56960_A0) 496 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56960_A0fmt */ 497 /* format RDBGC_TRIGGERSfmt */ 498 /* nFields */ 58, 499 /* *fields */ soc_RDBGC_TRIGGERS_BCM56960_A0fmt_fields, 500 /* bits */ 64, 501 /* flags */ 0, 502 }, 503 #endif /* chips */ 504 505 #if defined(BCM_56965_A0) 506 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56965_A0fmt */ 507 /* format RDBGC_TRIGGERSfmt */ 508 /* nFields */ 58, 509 /* *fields */ soc_RDBGC_TRIGGERS_BCM56960_A0fmt_fields, 510 /* bits */ 64, 511 /* flags */ 0, 512 }, 513 #endif /* chips */ 514 515 #if defined(BCM_56970_A0) 516 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM56970_A0fmt */ 517 /* format RDBGC_TRIGGERSfmt */ 518 /* nFields */ 59, 519 /* *fields */ soc_RDBGC_TRIGGERS_BCM56970_A0fmt_fields, 520 /* bits */ 64, 521 /* flags */ 0, 522 }, 523 #endif /* chips */ 524 525 #if defined(BCM_88732_A0) 526 { /* SOC_FORMAT_INT_RDBGC_TRIGGERS_BCM88732_A0fmt */ 527 /* format RDBGC_TRIGGERSfmt */ 528 /* nFields */ 35, 529 /* *fields */ soc_RDBGC_TRIGGERS_BCM88732_A0fmt_fields, 530 /* bits */ 62, 531 /* flags */ 0, 532 }, 533 #endif /* chips */ 534 535 #if defined(BCM_56634_A0) 536 { /* SOC_FORMAT_INT_RDEHDR_S_RFfmt */ 537 /* format RDEHDR_S_RFfmt */ 538 /* nFields */ 1, 539 /* *fields */ soc_RDEHDR_S_RFfmt_fields, 540 /* bits */ 16, 541 /* flags */ 0, 542 }, 543 #endif /* chips */ 544 545 #if defined(BCM_56524_A0) 546 { /* SOC_FORMAT_INT_RDEHDR_S_RF_BCM56524_A0fmt */ 547 /* format RDEHDR_S_RFfmt */ 548 /* nFields */ 1, 549 /* *fields */ soc_RDEHDR_S_RFfmt_fields, 550 /* bits */ 16, 551 /* flags */ 0, 552 }, 553 #endif /* chips */ 554 555 #if defined(BCM_56524_B0) 556 { /* SOC_FORMAT_INT_RDEHDR_S_RF_BCM56524_B0fmt */ 557 /* format RDEHDR_S_RFfmt */ 558 /* nFields */ 1, 559 /* *fields */ soc_RDEHDR_S_RFfmt_fields, 560 /* bits */ 16, 561 /* flags */ 0, 562 }, 563 #endif /* chips */ 564 565 #if defined(BCM_56634_B0) 566 { /* SOC_FORMAT_INT_RDEHDR_S_RF_BCM56634_B0fmt */ 567 /* format RDEHDR_S_RFfmt */ 568 /* nFields */ 1, 569 /* *fields */ soc_RDEHDR_S_RFfmt_fields, 570 /* bits */ 16, 571 /* flags */ 0, 572 }, 573 #endif /* chips */ 574 575 #if defined(BCM_56685_A0) 576 { /* SOC_FORMAT_INT_RDEHDR_S_RF_BCM56685_A0fmt */ 577 /* format RDEHDR_S_RFfmt */ 578 /* nFields */ 1, 579 /* *fields */ soc_RDEHDR_S_RFfmt_fields, 580 /* bits */ 16, 581 /* flags */ 0, 582 }, 583 #endif /* chips */ 584 585 #if defined(BCM_56685_B0) 586 { /* SOC_FORMAT_INT_RDEHDR_S_RF_BCM56685_B0fmt */ 587 /* format RDEHDR_S_RFfmt */ 588 /* nFields */ 1, 589 /* *fields */ soc_RDEHDR_S_RFfmt_fields, 590 /* bits */ 16, 591 /* flags */ 0, 592 }, 593 #endif /* chips */ 594 595 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 596 defined(BCM_56450_B1) 597 { /* SOC_FORMAT_INT_RDE_ADM_TO_TXQ_INFOfmt */ 598 /* format RDE_ADM_TO_TXQ_INFOfmt */ 599 /* nFields */ 13, 600 /* *fields */ soc_RDE_ADM_TO_TXQ_INFOfmt_fields, 601 /* bits */ 54, 602 /* flags */ 0, 603 }, 604 #endif /* chips */ 605 606 #if defined(BCM_56260_A0) 607 { /* SOC_FORMAT_INT_RDE_ADM_TO_TXQ_INFO_BCM56260_A0fmt */ 608 /* format RDE_ADM_TO_TXQ_INFOfmt */ 609 /* nFields */ 14, 610 /* *fields */ soc_RDE_ADM_TO_TXQ_INFO_BCM56260_A0fmt_fields, 611 /* bits */ 51, 612 /* flags */ 0, 613 }, 614 #endif /* chips */ 615 616 #if defined(BCM_56260_B0) 617 { /* SOC_FORMAT_INT_RDE_ADM_TO_TXQ_INFO_BCM56260_B0fmt */ 618 /* format RDE_ADM_TO_TXQ_INFOfmt */ 619 /* nFields */ 14, 620 /* *fields */ soc_RDE_ADM_TO_TXQ_INFO_BCM56260_A0fmt_fields, 621 /* bits */ 51, 622 /* flags */ 0, 623 }, 624 #endif /* chips */ 625 626 #if defined(BCM_56270_A0) 627 { /* SOC_FORMAT_INT_RDE_ADM_TO_TXQ_INFO_BCM56270_A0fmt */ 628 /* format RDE_ADM_TO_TXQ_INFOfmt */ 629 /* nFields */ 12, 630 /* *fields */ soc_RDE_ADM_TO_TXQ_INFO_BCM56270_A0fmt_fields, 631 /* bits */ 41, 632 /* flags */ 0, 633 }, 634 #endif /* chips */ 635 636 #if defined(BCM_56440_A0) || defined(BCM_56524_A0) || \ 637 defined(BCM_56634_A0) || defined(BCM_56840_B0) 638 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RFfmt */ 639 /* format RDE_COSPCP_S_RFfmt */ 640 /* nFields */ 1, 641 /* *fields */ soc_RDE_COSPCP_S_RFfmt_fields, 642 /* bits */ 128, 643 /* flags */ 0, 644 }, 645 #endif /* chips */ 646 647 #if defined(BCM_56260_A0) 648 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56260_A0fmt */ 649 /* format RDE_COSPCP_S_RFfmt */ 650 /* nFields */ 1, 651 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 652 /* bits */ 128, 653 /* flags */ 0, 654 }, 655 #endif /* chips */ 656 657 #if defined(BCM_56260_B0) 658 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56260_B0fmt */ 659 /* format RDE_COSPCP_S_RFfmt */ 660 /* nFields */ 1, 661 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 662 /* bits */ 128, 663 /* flags */ 0, 664 }, 665 #endif /* chips */ 666 667 #if defined(BCM_56270_A0) 668 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56270_A0fmt */ 669 /* format RDE_COSPCP_S_RFfmt */ 670 /* nFields */ 1, 671 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 672 /* bits */ 128, 673 /* flags */ 0, 674 }, 675 #endif /* chips */ 676 677 #if defined(BCM_56340_A0) 678 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56340_A0fmt */ 679 /* format RDE_COSPCP_S_RFfmt */ 680 /* nFields */ 1, 681 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56640_A0fmt_fields, 682 /* bits */ 128, 683 /* flags */ 0, 684 }, 685 #endif /* chips */ 686 687 #if defined(BCM_56440_B0) 688 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56440_B0fmt */ 689 /* format RDE_COSPCP_S_RFfmt */ 690 /* nFields */ 1, 691 /* *fields */ soc_RDE_COSPCP_S_RFfmt_fields, 692 /* bits */ 128, 693 /* flags */ 0, 694 }, 695 #endif /* chips */ 696 697 #if defined(BCM_56450_A0) 698 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56450_A0fmt */ 699 /* format RDE_COSPCP_S_RFfmt */ 700 /* nFields */ 1, 701 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56640_A0fmt_fields, 702 /* bits */ 128, 703 /* flags */ 0, 704 }, 705 #endif /* chips */ 706 707 #if defined(BCM_56450_B0) 708 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56450_B0fmt */ 709 /* format RDE_COSPCP_S_RFfmt */ 710 /* nFields */ 1, 711 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56640_A0fmt_fields, 712 /* bits */ 128, 713 /* flags */ 0, 714 }, 715 #endif /* chips */ 716 717 #if defined(BCM_56450_B1) 718 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56450_B1fmt */ 719 /* format RDE_COSPCP_S_RFfmt */ 720 /* nFields */ 1, 721 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56640_A0fmt_fields, 722 /* bits */ 128, 723 /* flags */ 0, 724 }, 725 #endif /* chips */ 726 727 #if defined(BCM_56524_B0) 728 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56524_B0fmt */ 729 /* format RDE_COSPCP_S_RFfmt */ 730 /* nFields */ 1, 731 /* *fields */ soc_RDE_COSPCP_S_RFfmt_fields, 732 /* bits */ 128, 733 /* flags */ 0, 734 }, 735 #endif /* chips */ 736 737 #if defined(BCM_56560_A0) 738 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56560_A0fmt */ 739 /* format RDE_COSPCP_S_RFfmt */ 740 /* nFields */ 1, 741 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 742 /* bits */ 128, 743 /* flags */ 0, 744 }, 745 #endif /* chips */ 746 747 #if defined(BCM_56560_B0) 748 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56560_B0fmt */ 749 /* format RDE_COSPCP_S_RFfmt */ 750 /* nFields */ 1, 751 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 752 /* bits */ 128, 753 /* flags */ 0, 754 }, 755 #endif /* chips */ 756 757 #if defined(BCM_56634_B0) 758 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56634_B0fmt */ 759 /* format RDE_COSPCP_S_RFfmt */ 760 /* nFields */ 1, 761 /* *fields */ soc_RDE_COSPCP_S_RFfmt_fields, 762 /* bits */ 128, 763 /* flags */ 0, 764 }, 765 #endif /* chips */ 766 767 #if defined(BCM_56640_A0) 768 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56640_A0fmt */ 769 /* format RDE_COSPCP_S_RFfmt */ 770 /* nFields */ 1, 771 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56640_A0fmt_fields, 772 /* bits */ 128, 773 /* flags */ 0, 774 }, 775 #endif /* chips */ 776 777 #if defined(BCM_56670_A0) 778 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56670_A0fmt */ 779 /* format RDE_COSPCP_S_RFfmt */ 780 /* nFields */ 1, 781 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 782 /* bits */ 128, 783 /* flags */ 0, 784 }, 785 #endif /* chips */ 786 787 #if defined(BCM_56670_B0) 788 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56670_B0fmt */ 789 /* format RDE_COSPCP_S_RFfmt */ 790 /* nFields */ 1, 791 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 792 /* bits */ 128, 793 /* flags */ 0, 794 }, 795 #endif /* chips */ 796 797 #if defined(BCM_56685_A0) 798 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56685_A0fmt */ 799 /* format RDE_COSPCP_S_RFfmt */ 800 /* nFields */ 1, 801 /* *fields */ soc_RDE_COSPCP_S_RFfmt_fields, 802 /* bits */ 128, 803 /* flags */ 0, 804 }, 805 #endif /* chips */ 806 807 #if defined(BCM_56685_B0) 808 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56685_B0fmt */ 809 /* format RDE_COSPCP_S_RFfmt */ 810 /* nFields */ 1, 811 /* *fields */ soc_RDE_COSPCP_S_RFfmt_fields, 812 /* bits */ 128, 813 /* flags */ 0, 814 }, 815 #endif /* chips */ 816 817 #if defined(BCM_56840_A0) 818 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56840_A0fmt */ 819 /* format RDE_COSPCP_S_RFfmt */ 820 /* nFields */ 1, 821 /* *fields */ soc_RDE_COSPCP_S_RFfmt_fields, 822 /* bits */ 128, 823 /* flags */ 0, 824 }, 825 #endif /* chips */ 826 827 #if defined(BCM_56850_A0) 828 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56850_A0fmt */ 829 /* format RDE_COSPCP_S_RFfmt */ 830 /* nFields */ 1, 831 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56640_A0fmt_fields, 832 /* bits */ 128, 833 /* flags */ 0, 834 }, 835 #endif /* chips */ 836 837 #if defined(BCM_56860_A0) 838 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56860_A0fmt */ 839 /* format RDE_COSPCP_S_RFfmt */ 840 /* nFields */ 1, 841 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56640_A0fmt_fields, 842 /* bits */ 128, 843 /* flags */ 0, 844 }, 845 #endif /* chips */ 846 847 #if defined(BCM_56960_A0) 848 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56960_A0fmt */ 849 /* format RDE_COSPCP_S_RFfmt */ 850 /* nFields */ 1, 851 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 852 /* bits */ 128, 853 /* flags */ 0, 854 }, 855 #endif /* chips */ 856 857 #if defined(BCM_56965_A0) 858 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56965_A0fmt */ 859 /* format RDE_COSPCP_S_RFfmt */ 860 /* nFields */ 1, 861 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 862 /* bits */ 128, 863 /* flags */ 0, 864 }, 865 #endif /* chips */ 866 867 #if defined(BCM_56970_A0) 868 { /* SOC_FORMAT_INT_RDE_COSPCP_S_RF_BCM56970_A0fmt */ 869 /* format RDE_COSPCP_S_RFfmt */ 870 /* nFields */ 1, 871 /* *fields */ soc_RDE_COSPCP_S_RF_BCM56960_A0fmt_fields, 872 /* bits */ 128, 873 /* flags */ 0, 874 }, 875 #endif /* chips */ 876 877 #if defined(BCM_56634_A0) 878 { /* SOC_FORMAT_INT_RDE_DESCP_S_RFfmt */ 879 /* format RDE_DESCP_S_RFfmt */ 880 /* nFields */ 1, 881 /* *fields */ soc_RDE_DESCP_S_RFfmt_fields, 882 /* bits */ 24, 883 /* flags */ 0, 884 }, 885 #endif /* chips */ 886 887 #if defined(BCM_56524_A0) 888 { /* SOC_FORMAT_INT_RDE_DESCP_S_RF_BCM56524_A0fmt */ 889 /* format RDE_DESCP_S_RFfmt */ 890 /* nFields */ 1, 891 /* *fields */ soc_RDE_DESCP_S_RFfmt_fields, 892 /* bits */ 24, 893 /* flags */ 0, 894 }, 895 #endif /* chips */ 896 897 #if defined(BCM_56524_B0) 898 { /* SOC_FORMAT_INT_RDE_DESCP_S_RF_BCM56524_B0fmt */ 899 /* format RDE_DESCP_S_RFfmt */ 900 /* nFields */ 1, 901 /* *fields */ soc_RDE_DESCP_S_RFfmt_fields, 902 /* bits */ 24, 903 /* flags */ 0, 904 }, 905 #endif /* chips */ 906 907 #if defined(BCM_56634_B0) 908 { /* SOC_FORMAT_INT_RDE_DESCP_S_RF_BCM56634_B0fmt */ 909 /* format RDE_DESCP_S_RFfmt */ 910 /* nFields */ 1, 911 /* *fields */ soc_RDE_DESCP_S_RFfmt_fields, 912 /* bits */ 24, 913 /* flags */ 0, 914 }, 915 #endif /* chips */ 916 917 #if defined(BCM_56685_A0) 918 { /* SOC_FORMAT_INT_RDE_DESCP_S_RF_BCM56685_A0fmt */ 919 /* format RDE_DESCP_S_RFfmt */ 920 /* nFields */ 1, 921 /* *fields */ soc_RDE_DESCP_S_RFfmt_fields, 922 /* bits */ 24, 923 /* flags */ 0, 924 }, 925 #endif /* chips */ 926 927 #if defined(BCM_56685_B0) 928 { /* SOC_FORMAT_INT_RDE_DESCP_S_RF_BCM56685_B0fmt */ 929 /* format RDE_DESCP_S_RFfmt */ 930 /* nFields */ 1, 931 /* *fields */ soc_RDE_DESCP_S_RFfmt_fields, 932 /* bits */ 24, 933 /* flags */ 0, 934 }, 935 #endif /* chips */ 936 937 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 938 defined(BCM_56450_B1) 939 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REAL_PIPE_INFOfmt */ 940 /* format RDE_FIFO_TO_ADM_REAL_PIPE_INFOfmt */ 941 /* nFields */ 40, 942 /* *fields */ soc_RDE_FIFO_TO_ADM_REAL_PIPE_INFOfmt_fields, 943 /* bits */ 139, 944 /* flags */ 0, 945 }, 946 #endif /* chips */ 947 948 #if defined(BCM_56260_A0) 949 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REAL_PIPE_INFO_BCM56260_A0fmt */ 950 /* format RDE_FIFO_TO_ADM_REAL_PIPE_INFOfmt */ 951 /* nFields */ 40, 952 /* *fields */ soc_RDE_FIFO_TO_ADM_REAL_PIPE_INFO_BCM56260_A0fmt_fields, 953 /* bits */ 128, 954 /* flags */ 0, 955 }, 956 #endif /* chips */ 957 958 #if defined(BCM_56260_B0) 959 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REAL_PIPE_INFO_BCM56260_B0fmt */ 960 /* format RDE_FIFO_TO_ADM_REAL_PIPE_INFOfmt */ 961 /* nFields */ 40, 962 /* *fields */ soc_RDE_FIFO_TO_ADM_REAL_PIPE_INFO_BCM56260_A0fmt_fields, 963 /* bits */ 128, 964 /* flags */ 0, 965 }, 966 #endif /* chips */ 967 968 #if defined(BCM_56270_A0) 969 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REAL_PIPE_INFO_BCM56270_A0fmt */ 970 /* format RDE_FIFO_TO_ADM_REAL_PIPE_INFOfmt */ 971 /* nFields */ 34, 972 /* *fields */ soc_RDE_FIFO_TO_ADM_REAL_PIPE_INFO_BCM56270_A0fmt_fields, 973 /* bits */ 107, 974 /* flags */ 0, 975 }, 976 #endif /* chips */ 977 978 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 979 defined(BCM_56450_B1) 980 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REL_PIPE_INFOfmt */ 981 /* format RDE_FIFO_TO_ADM_REL_PIPE_INFOfmt */ 982 /* nFields */ 22, 983 /* *fields */ soc_RDE_FIFO_TO_ADM_REL_PIPE_INFOfmt_fields, 984 /* bits */ 84, 985 /* flags */ 0, 986 }, 987 #endif /* chips */ 988 989 #if defined(BCM_56260_A0) 990 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REL_PIPE_INFO_BCM56260_A0fmt */ 991 /* format RDE_FIFO_TO_ADM_REL_PIPE_INFOfmt */ 992 /* nFields */ 21, 993 /* *fields */ soc_RDE_FIFO_TO_ADM_REL_PIPE_INFO_BCM56260_A0fmt_fields, 994 /* bits */ 79, 995 /* flags */ 0, 996 }, 997 #endif /* chips */ 998 999 #if defined(BCM_56260_B0) 1000 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REL_PIPE_INFO_BCM56260_B0fmt */ 1001 /* format RDE_FIFO_TO_ADM_REL_PIPE_INFOfmt */ 1002 /* nFields */ 21, 1003 /* *fields */ soc_RDE_FIFO_TO_ADM_REL_PIPE_INFO_BCM56260_A0fmt_fields, 1004 /* bits */ 79, 1005 /* flags */ 0, 1006 }, 1007 #endif /* chips */ 1008 1009 #if defined(BCM_56270_A0) 1010 { /* SOC_FORMAT_INT_RDE_FIFO_TO_ADM_REL_PIPE_INFO_BCM56270_A0fmt */ 1011 /* format RDE_FIFO_TO_ADM_REL_PIPE_INFOfmt */ 1012 /* nFields */ 18, 1013 /* *fields */ soc_RDE_FIFO_TO_ADM_REL_PIPE_INFO_BCM56270_A0fmt_fields, 1014 /* bits */ 72, 1015 /* flags */ 0, 1016 }, 1017 #endif /* chips */ 1018 1019 #if defined(BCM_56634_A0) 1020 { /* SOC_FORMAT_INT_RDE_FLST_S_RFfmt */ 1021 /* format RDE_FLST_S_RFfmt */ 1022 /* nFields */ 1, 1023 /* *fields */ soc_RDE_FLST_S_RFfmt_fields, 1024 /* bits */ 14, 1025 /* flags */ 0, 1026 }, 1027 #endif /* chips */ 1028 1029 #if defined(BCM_56524_A0) 1030 { /* SOC_FORMAT_INT_RDE_FLST_S_RF_BCM56524_A0fmt */ 1031 /* format RDE_FLST_S_RFfmt */ 1032 /* nFields */ 1, 1033 /* *fields */ soc_RDE_FLST_S_RFfmt_fields, 1034 /* bits */ 14, 1035 /* flags */ 0, 1036 }, 1037 #endif /* chips */ 1038 1039 #if defined(BCM_56524_B0) 1040 { /* SOC_FORMAT_INT_RDE_FLST_S_RF_BCM56524_B0fmt */ 1041 /* format RDE_FLST_S_RFfmt */ 1042 /* nFields */ 1, 1043 /* *fields */ soc_RDE_FLST_S_RFfmt_fields, 1044 /* bits */ 14, 1045 /* flags */ 0, 1046 }, 1047 #endif /* chips */ 1048 1049 #if defined(BCM_56634_B0) 1050 { /* SOC_FORMAT_INT_RDE_FLST_S_RF_BCM56634_B0fmt */ 1051 /* format RDE_FLST_S_RFfmt */ 1052 /* nFields */ 1, 1053 /* *fields */ soc_RDE_FLST_S_RFfmt_fields, 1054 /* bits */ 14, 1055 /* flags */ 0, 1056 }, 1057 #endif /* chips */ 1058 1059 #if defined(BCM_56685_A0) 1060 { /* SOC_FORMAT_INT_RDE_FLST_S_RF_BCM56685_A0fmt */ 1061 /* format RDE_FLST_S_RFfmt */ 1062 /* nFields */ 1, 1063 /* *fields */ soc_RDE_FLST_S_RFfmt_fields, 1064 /* bits */ 14, 1065 /* flags */ 0, 1066 }, 1067 #endif /* chips */ 1068 1069 #if defined(BCM_56685_B0) 1070 { /* SOC_FORMAT_INT_RDE_FLST_S_RF_BCM56685_B0fmt */ 1071 /* format RDE_FLST_S_RFfmt */ 1072 /* nFields */ 1, 1073 /* *fields */ soc_RDE_FLST_S_RFfmt_fields, 1074 /* bits */ 14, 1075 /* flags */ 0, 1076 }, 1077 #endif /* chips */ 1078 1079 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) 1080 { /* SOC_FORMAT_INT_RDE_HEADER_INFOfmt */ 1081 /* format RDE_HEADER_INFOfmt */ 1082 /* nFields */ 15, 1083 /* *fields */ soc_RDE_HEADER_INFOfmt_fields, 1084 /* bits */ 156, 1085 /* flags */ 0, 1086 }, 1087 #endif /* chips */ 1088 1089 #if defined(BCM_56340_A0) 1090 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56340_A0fmt */ 1091 /* format RDE_HEADER_INFOfmt */ 1092 /* nFields */ 14, 1093 /* *fields */ soc_RDE_HEADER_INFO_BCM56640_A0fmt_fields, 1094 /* bits */ 141, 1095 /* flags */ 0, 1096 }, 1097 #endif /* chips */ 1098 1099 #if defined(BCM_56524_B0) 1100 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56524_B0fmt */ 1101 /* format RDE_HEADER_INFOfmt */ 1102 /* nFields */ 15, 1103 /* *fields */ soc_RDE_HEADER_INFOfmt_fields, 1104 /* bits */ 156, 1105 /* flags */ 0, 1106 }, 1107 #endif /* chips */ 1108 1109 #if defined(BCM_56560_A0) 1110 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56560_A0fmt */ 1111 /* format RDE_HEADER_INFOfmt */ 1112 /* nFields */ 14, 1113 /* *fields */ soc_RDE_HEADER_INFO_BCM56560_A0fmt_fields, 1114 /* bits */ 141, 1115 /* flags */ 0, 1116 }, 1117 #endif /* chips */ 1118 1119 #if defined(BCM_56560_B0) 1120 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56560_B0fmt */ 1121 /* format RDE_HEADER_INFOfmt */ 1122 /* nFields */ 14, 1123 /* *fields */ soc_RDE_HEADER_INFO_BCM56560_A0fmt_fields, 1124 /* bits */ 141, 1125 /* flags */ 0, 1126 }, 1127 #endif /* chips */ 1128 1129 #if defined(BCM_56634_B0) 1130 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56634_B0fmt */ 1131 /* format RDE_HEADER_INFOfmt */ 1132 /* nFields */ 15, 1133 /* *fields */ soc_RDE_HEADER_INFOfmt_fields, 1134 /* bits */ 156, 1135 /* flags */ 0, 1136 }, 1137 #endif /* chips */ 1138 1139 #if defined(BCM_56640_A0) 1140 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56640_A0fmt */ 1141 /* format RDE_HEADER_INFOfmt */ 1142 /* nFields */ 14, 1143 /* *fields */ soc_RDE_HEADER_INFO_BCM56640_A0fmt_fields, 1144 /* bits */ 141, 1145 /* flags */ 0, 1146 }, 1147 #endif /* chips */ 1148 1149 #if defined(BCM_56670_A0) 1150 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56670_A0fmt */ 1151 /* format RDE_HEADER_INFOfmt */ 1152 /* nFields */ 14, 1153 /* *fields */ soc_RDE_HEADER_INFO_BCM56560_A0fmt_fields, 1154 /* bits */ 141, 1155 /* flags */ 0, 1156 }, 1157 #endif /* chips */ 1158 1159 #if defined(BCM_56670_B0) 1160 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56670_B0fmt */ 1161 /* format RDE_HEADER_INFOfmt */ 1162 /* nFields */ 14, 1163 /* *fields */ soc_RDE_HEADER_INFO_BCM56560_A0fmt_fields, 1164 /* bits */ 141, 1165 /* flags */ 0, 1166 }, 1167 #endif /* chips */ 1168 1169 #if defined(BCM_56685_A0) 1170 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56685_A0fmt */ 1171 /* format RDE_HEADER_INFOfmt */ 1172 /* nFields */ 15, 1173 /* *fields */ soc_RDE_HEADER_INFOfmt_fields, 1174 /* bits */ 156, 1175 /* flags */ 0, 1176 }, 1177 #endif /* chips */ 1178 1179 #if defined(BCM_56685_B0) 1180 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56685_B0fmt */ 1181 /* format RDE_HEADER_INFOfmt */ 1182 /* nFields */ 15, 1183 /* *fields */ soc_RDE_HEADER_INFOfmt_fields, 1184 /* bits */ 156, 1185 /* flags */ 0, 1186 }, 1187 #endif /* chips */ 1188 1189 #if defined(BCM_56850_A0) 1190 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56850_A0fmt */ 1191 /* format RDE_HEADER_INFOfmt */ 1192 /* nFields */ 14, 1193 /* *fields */ soc_RDE_HEADER_INFO_BCM56640_A0fmt_fields, 1194 /* bits */ 141, 1195 /* flags */ 0, 1196 }, 1197 #endif /* chips */ 1198 1199 #if defined(BCM_56860_A0) 1200 { /* SOC_FORMAT_INT_RDE_HEADER_INFO_BCM56860_A0fmt */ 1201 /* format RDE_HEADER_INFOfmt */ 1202 /* nFields */ 14, 1203 /* *fields */ soc_RDE_HEADER_INFO_BCM56640_A0fmt_fields, 1204 /* bits */ 141, 1205 /* flags */ 0, 1206 }, 1207 #endif /* chips */ 1208 1209 #if defined(BCM_56634_A0) 1210 { /* SOC_FORMAT_INT_RDE_PLNK_S_RFfmt */ 1211 /* format RDE_PLNK_S_RFfmt */ 1212 /* nFields */ 1, 1213 /* *fields */ soc_RDE_PLNK_S_RFfmt_fields, 1214 /* bits */ 14, 1215 /* flags */ 0, 1216 }, 1217 #endif /* chips */ 1218 1219 #if defined(BCM_56524_A0) 1220 { /* SOC_FORMAT_INT_RDE_PLNK_S_RF_BCM56524_A0fmt */ 1221 /* format RDE_PLNK_S_RFfmt */ 1222 /* nFields */ 1, 1223 /* *fields */ soc_RDE_PLNK_S_RFfmt_fields, 1224 /* bits */ 14, 1225 /* flags */ 0, 1226 }, 1227 #endif /* chips */ 1228 1229 #if defined(BCM_56524_B0) 1230 { /* SOC_FORMAT_INT_RDE_PLNK_S_RF_BCM56524_B0fmt */ 1231 /* format RDE_PLNK_S_RFfmt */ 1232 /* nFields */ 1, 1233 /* *fields */ soc_RDE_PLNK_S_RFfmt_fields, 1234 /* bits */ 14, 1235 /* flags */ 0, 1236 }, 1237 #endif /* chips */ 1238 1239 #if defined(BCM_56634_B0) 1240 { /* SOC_FORMAT_INT_RDE_PLNK_S_RF_BCM56634_B0fmt */ 1241 /* format RDE_PLNK_S_RFfmt */ 1242 /* nFields */ 1, 1243 /* *fields */ soc_RDE_PLNK_S_RFfmt_fields, 1244 /* bits */ 14, 1245 /* flags */ 0, 1246 }, 1247 #endif /* chips */ 1248 1249 #if defined(BCM_56685_A0) 1250 { /* SOC_FORMAT_INT_RDE_PLNK_S_RF_BCM56685_A0fmt */ 1251 /* format RDE_PLNK_S_RFfmt */ 1252 /* nFields */ 1, 1253 /* *fields */ soc_RDE_PLNK_S_RFfmt_fields, 1254 /* bits */ 14, 1255 /* flags */ 0, 1256 }, 1257 #endif /* chips */ 1258 1259 #if defined(BCM_56685_B0) 1260 { /* SOC_FORMAT_INT_RDE_PLNK_S_RF_BCM56685_B0fmt */ 1261 /* format RDE_PLNK_S_RFfmt */ 1262 /* nFields */ 1, 1263 /* *fields */ soc_RDE_PLNK_S_RFfmt_fields, 1264 /* bits */ 14, 1265 /* flags */ 0, 1266 }, 1267 #endif /* chips */ 1268 1269 #if defined(BCM_56634_A0) 1270 { /* SOC_FORMAT_INT_RDE_PRCP_S_RFfmt */ 1271 /* format RDE_PRCP_S_RFfmt */ 1272 /* nFields */ 1, 1273 /* *fields */ soc_RDE_PRCP_S_RFfmt_fields, 1274 /* bits */ 112, 1275 /* flags */ 0, 1276 }, 1277 #endif /* chips */ 1278 1279 #if defined(BCM_56524_A0) 1280 { /* SOC_FORMAT_INT_RDE_PRCP_S_RF_BCM56524_A0fmt */ 1281 /* format RDE_PRCP_S_RFfmt */ 1282 /* nFields */ 1, 1283 /* *fields */ soc_RDE_PRCP_S_RFfmt_fields, 1284 /* bits */ 112, 1285 /* flags */ 0, 1286 }, 1287 #endif /* chips */ 1288 1289 #if defined(BCM_56524_B0) 1290 { /* SOC_FORMAT_INT_RDE_PRCP_S_RF_BCM56524_B0fmt */ 1291 /* format RDE_PRCP_S_RFfmt */ 1292 /* nFields */ 1, 1293 /* *fields */ soc_RDE_PRCP_S_RFfmt_fields, 1294 /* bits */ 112, 1295 /* flags */ 0, 1296 }, 1297 #endif /* chips */ 1298 1299 #if defined(BCM_56634_B0) 1300 { /* SOC_FORMAT_INT_RDE_PRCP_S_RF_BCM56634_B0fmt */ 1301 /* format RDE_PRCP_S_RFfmt */ 1302 /* nFields */ 1, 1303 /* *fields */ soc_RDE_PRCP_S_RFfmt_fields, 1304 /* bits */ 112, 1305 /* flags */ 0, 1306 }, 1307 #endif /* chips */ 1308 1309 #if defined(BCM_56685_A0) 1310 { /* SOC_FORMAT_INT_RDE_PRCP_S_RF_BCM56685_A0fmt */ 1311 /* format RDE_PRCP_S_RFfmt */ 1312 /* nFields */ 1, 1313 /* *fields */ soc_RDE_PRCP_S_RFfmt_fields, 1314 /* bits */ 112, 1315 /* flags */ 0, 1316 }, 1317 #endif /* chips */ 1318 1319 #if defined(BCM_56685_B0) 1320 { /* SOC_FORMAT_INT_RDE_PRCP_S_RF_BCM56685_B0fmt */ 1321 /* format RDE_PRCP_S_RFfmt */ 1322 /* nFields */ 1, 1323 /* *fields */ soc_RDE_PRCP_S_RFfmt_fields, 1324 /* bits */ 112, 1325 /* flags */ 0, 1326 }, 1327 #endif /* chips */ 1328 1329 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1330 { /* SOC_FORMAT_INT_RDE_TO_CCP_INFOfmt */ 1331 /* format RDE_TO_CCP_INFOfmt */ 1332 /* nFields */ 29, 1333 /* *fields */ soc_RDE_TO_CCP_INFOfmt_fields, 1334 /* bits */ 106, 1335 /* flags */ 0, 1336 }, 1337 #endif /* chips */ 1338 1339 #if defined(BCM_56260_A0) 1340 { /* SOC_FORMAT_INT_RDE_TO_CCP_INFO_BCM56260_A0fmt */ 1341 /* format RDE_TO_CCP_INFOfmt */ 1342 /* nFields */ 27, 1343 /* *fields */ soc_RDE_TO_CCP_INFO_BCM56260_A0fmt_fields, 1344 /* bits */ 85, 1345 /* flags */ 0, 1346 }, 1347 #endif /* chips */ 1348 1349 #if defined(BCM_56260_B0) 1350 { /* SOC_FORMAT_INT_RDE_TO_CCP_INFO_BCM56260_B0fmt */ 1351 /* format RDE_TO_CCP_INFOfmt */ 1352 /* nFields */ 27, 1353 /* *fields */ soc_RDE_TO_CCP_INFO_BCM56260_A0fmt_fields, 1354 /* bits */ 85, 1355 /* flags */ 0, 1356 }, 1357 #endif /* chips */ 1358 1359 #if defined(BCM_56270_A0) 1360 { /* SOC_FORMAT_INT_RDE_TO_CCP_INFO_BCM56270_A0fmt */ 1361 /* format RDE_TO_CCP_INFOfmt */ 1362 /* nFields */ 22, 1363 /* *fields */ soc_RDE_TO_CCP_INFO_BCM56270_A0fmt_fields, 1364 /* bits */ 68, 1365 /* flags */ 0, 1366 }, 1367 #endif /* chips */ 1368 1369 #if defined(BCM_56450_A0) 1370 { /* SOC_FORMAT_INT_RDE_TO_CCP_INFO_BCM56450_A0fmt */ 1371 /* format RDE_TO_CCP_INFOfmt */ 1372 /* nFields */ 27, 1373 /* *fields */ soc_RDE_TO_CCP_INFO_BCM56450_A0fmt_fields, 1374 /* bits */ 93, 1375 /* flags */ 0, 1376 }, 1377 #endif /* chips */ 1378 1379 #if defined(BCM_56450_B0) 1380 { /* SOC_FORMAT_INT_RDE_TO_CCP_INFO_BCM56450_B0fmt */ 1381 /* format RDE_TO_CCP_INFOfmt */ 1382 /* nFields */ 27, 1383 /* *fields */ soc_RDE_TO_CCP_INFO_BCM56450_A0fmt_fields, 1384 /* bits */ 93, 1385 /* flags */ 0, 1386 }, 1387 #endif /* chips */ 1388 1389 #if defined(BCM_56450_B1) 1390 { /* SOC_FORMAT_INT_RDE_TO_CCP_INFO_BCM56450_B1fmt */ 1391 /* format RDE_TO_CCP_INFOfmt */ 1392 /* nFields */ 27, 1393 /* *fields */ soc_RDE_TO_CCP_INFO_BCM56450_A0fmt_fields, 1394 /* bits */ 93, 1395 /* flags */ 0, 1396 }, 1397 #endif /* chips */ 1398 1399 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1400 { /* SOC_FORMAT_INT_RDE_TO_DEQ_INFOfmt */ 1401 /* format RDE_TO_DEQ_INFOfmt */ 1402 /* nFields */ 2, 1403 /* *fields */ soc_RDE_TO_DEQ_INFOfmt_fields, 1404 /* bits */ 151, 1405 /* flags */ 0, 1406 }, 1407 #endif /* chips */ 1408 1409 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1410 defined(BCM_56450_B1) 1411 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEE_INFOfmt */ 1412 /* format RDE_TO_THDO_RDEE_INFOfmt */ 1413 /* nFields */ 3, 1414 /* *fields */ soc_RDE_TO_THDO_RDEE_INFOfmt_fields, 1415 /* bits */ 12, 1416 /* flags */ 0, 1417 }, 1418 #endif /* chips */ 1419 1420 #if defined(BCM_56260_A0) 1421 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEE_INFO_BCM56260_A0fmt */ 1422 /* format RDE_TO_THDO_RDEE_INFOfmt */ 1423 /* nFields */ 3, 1424 /* *fields */ soc_RDE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 1425 /* bits */ 12, 1426 /* flags */ 0, 1427 }, 1428 #endif /* chips */ 1429 1430 #if defined(BCM_56260_B0) 1431 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEE_INFO_BCM56260_B0fmt */ 1432 /* format RDE_TO_THDO_RDEE_INFOfmt */ 1433 /* nFields */ 3, 1434 /* *fields */ soc_RDE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 1435 /* bits */ 12, 1436 /* flags */ 0, 1437 }, 1438 #endif /* chips */ 1439 1440 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1441 defined(BCM_56450_B1) 1442 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEE_REL_INFOfmt */ 1443 /* format RDE_TO_THDO_RDEE_REL_INFOfmt */ 1444 /* nFields */ 3, 1445 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFOfmt_fields, 1446 /* bits */ 11, 1447 /* flags */ 0, 1448 }, 1449 #endif /* chips */ 1450 1451 #if defined(BCM_56260_A0) 1452 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEE_REL_INFO_BCM56260_A0fmt */ 1453 /* format RDE_TO_THDO_RDEE_REL_INFOfmt */ 1454 /* nFields */ 3, 1455 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFO_BCM56260_A0fmt_fields, 1456 /* bits */ 11, 1457 /* flags */ 0, 1458 }, 1459 #endif /* chips */ 1460 1461 #if defined(BCM_56260_B0) 1462 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEE_REL_INFO_BCM56260_B0fmt */ 1463 /* format RDE_TO_THDO_RDEE_REL_INFOfmt */ 1464 /* nFields */ 3, 1465 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFO_BCM56260_A0fmt_fields, 1466 /* bits */ 11, 1467 /* flags */ 0, 1468 }, 1469 #endif /* chips */ 1470 1471 #if defined(BCM_56450_A0) 1472 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_INFOfmt */ 1473 /* format RDE_TO_THDO_RDEI_INFOfmt */ 1474 /* nFields */ 3, 1475 /* *fields */ soc_RDE_TO_THDO_RDEE_INFOfmt_fields, 1476 /* bits */ 12, 1477 /* flags */ 0, 1478 }, 1479 #endif /* chips */ 1480 1481 #if defined(BCM_56260_A0) 1482 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_INFO_BCM56260_A0fmt */ 1483 /* format RDE_TO_THDO_RDEI_INFOfmt */ 1484 /* nFields */ 3, 1485 /* *fields */ soc_RDE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 1486 /* bits */ 12, 1487 /* flags */ 0, 1488 }, 1489 #endif /* chips */ 1490 1491 #if defined(BCM_56260_B0) 1492 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_INFO_BCM56260_B0fmt */ 1493 /* format RDE_TO_THDO_RDEI_INFOfmt */ 1494 /* nFields */ 3, 1495 /* *fields */ soc_RDE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 1496 /* bits */ 12, 1497 /* flags */ 0, 1498 }, 1499 #endif /* chips */ 1500 1501 #if defined(BCM_56270_A0) 1502 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_INFO_BCM56270_A0fmt */ 1503 /* format RDE_TO_THDO_RDEI_INFOfmt */ 1504 /* nFields */ 3, 1505 /* *fields */ soc_RDE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 1506 /* bits */ 12, 1507 /* flags */ 0, 1508 }, 1509 #endif /* chips */ 1510 1511 #if defined(BCM_56450_B0) 1512 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_INFO_BCM56450_B0fmt */ 1513 /* format RDE_TO_THDO_RDEI_INFOfmt */ 1514 /* nFields */ 3, 1515 /* *fields */ soc_RDE_TO_THDO_RDEE_INFOfmt_fields, 1516 /* bits */ 12, 1517 /* flags */ 0, 1518 }, 1519 #endif /* chips */ 1520 1521 #if defined(BCM_56450_B1) 1522 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_INFO_BCM56450_B1fmt */ 1523 /* format RDE_TO_THDO_RDEI_INFOfmt */ 1524 /* nFields */ 3, 1525 /* *fields */ soc_RDE_TO_THDO_RDEE_INFOfmt_fields, 1526 /* bits */ 12, 1527 /* flags */ 0, 1528 }, 1529 #endif /* chips */ 1530 1531 #if defined(BCM_56450_A0) 1532 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_REL_INFOfmt */ 1533 /* format RDE_TO_THDO_RDEI_REL_INFOfmt */ 1534 /* nFields */ 3, 1535 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFOfmt_fields, 1536 /* bits */ 11, 1537 /* flags */ 0, 1538 }, 1539 #endif /* chips */ 1540 1541 #if defined(BCM_56260_A0) 1542 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_REL_INFO_BCM56260_A0fmt */ 1543 /* format RDE_TO_THDO_RDEI_REL_INFOfmt */ 1544 /* nFields */ 3, 1545 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFO_BCM56260_A0fmt_fields, 1546 /* bits */ 11, 1547 /* flags */ 0, 1548 }, 1549 #endif /* chips */ 1550 1551 #if defined(BCM_56260_B0) 1552 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_REL_INFO_BCM56260_B0fmt */ 1553 /* format RDE_TO_THDO_RDEI_REL_INFOfmt */ 1554 /* nFields */ 3, 1555 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFO_BCM56260_A0fmt_fields, 1556 /* bits */ 11, 1557 /* flags */ 0, 1558 }, 1559 #endif /* chips */ 1560 1561 #if defined(BCM_56270_A0) 1562 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_REL_INFO_BCM56270_A0fmt */ 1563 /* format RDE_TO_THDO_RDEI_REL_INFOfmt */ 1564 /* nFields */ 3, 1565 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFO_BCM56260_A0fmt_fields, 1566 /* bits */ 11, 1567 /* flags */ 0, 1568 }, 1569 #endif /* chips */ 1570 1571 #if defined(BCM_56450_B0) 1572 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_REL_INFO_BCM56450_B0fmt */ 1573 /* format RDE_TO_THDO_RDEI_REL_INFOfmt */ 1574 /* nFields */ 3, 1575 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFOfmt_fields, 1576 /* bits */ 11, 1577 /* flags */ 0, 1578 }, 1579 #endif /* chips */ 1580 1581 #if defined(BCM_56450_B1) 1582 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEI_REL_INFO_BCM56450_B1fmt */ 1583 /* format RDE_TO_THDO_RDEI_REL_INFOfmt */ 1584 /* nFields */ 3, 1585 /* *fields */ soc_RDE_TO_THDO_RDEE_REL_INFOfmt_fields, 1586 /* bits */ 11, 1587 /* flags */ 0, 1588 }, 1589 #endif /* chips */ 1590 1591 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1592 defined(BCM_56450_B1) 1593 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_DEQ_INFOfmt */ 1594 /* format RDE_TO_THDO_RDEQ_DEQ_INFOfmt */ 1595 /* nFields */ 3, 1596 /* *fields */ soc_RDE_TO_THDO_RDEQ_DEQ_INFOfmt_fields, 1597 /* bits */ 6, 1598 /* flags */ 0, 1599 }, 1600 #endif /* chips */ 1601 1602 #if defined(BCM_56260_A0) 1603 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_DEQ_INFO_BCM56260_A0fmt */ 1604 /* format RDE_TO_THDO_RDEQ_DEQ_INFOfmt */ 1605 /* nFields */ 3, 1606 /* *fields */ soc_RDE_TO_THDO_RDEQ_DEQ_INFO_BCM56260_A0fmt_fields, 1607 /* bits */ 6, 1608 /* flags */ 0, 1609 }, 1610 #endif /* chips */ 1611 1612 #if defined(BCM_56260_B0) 1613 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_DEQ_INFO_BCM56260_B0fmt */ 1614 /* format RDE_TO_THDO_RDEQ_DEQ_INFOfmt */ 1615 /* nFields */ 3, 1616 /* *fields */ soc_RDE_TO_THDO_RDEQ_DEQ_INFO_BCM56260_A0fmt_fields, 1617 /* bits */ 6, 1618 /* flags */ 0, 1619 }, 1620 #endif /* chips */ 1621 1622 #if defined(BCM_56270_A0) 1623 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_DEQ_INFO_BCM56270_A0fmt */ 1624 /* format RDE_TO_THDO_RDEQ_DEQ_INFOfmt */ 1625 /* nFields */ 3, 1626 /* *fields */ soc_RQE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 1627 /* bits */ 5, 1628 /* flags */ 0, 1629 }, 1630 #endif /* chips */ 1631 1632 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1633 defined(BCM_56450_B1) 1634 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_INFOfmt */ 1635 /* format RDE_TO_THDO_RDEQ_INFOfmt */ 1636 /* nFields */ 2, 1637 /* *fields */ soc_RDE_TO_THDO_RDEQ_INFOfmt_fields, 1638 /* bits */ 6, 1639 /* flags */ 0, 1640 }, 1641 #endif /* chips */ 1642 1643 #if defined(BCM_56260_A0) 1644 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_INFO_BCM56260_A0fmt */ 1645 /* format RDE_TO_THDO_RDEQ_INFOfmt */ 1646 /* nFields */ 2, 1647 /* *fields */ soc_RDE_TO_THDO_RDEQ_INFO_BCM56260_A0fmt_fields, 1648 /* bits */ 6, 1649 /* flags */ 0, 1650 }, 1651 #endif /* chips */ 1652 1653 #if defined(BCM_56260_B0) 1654 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_INFO_BCM56260_B0fmt */ 1655 /* format RDE_TO_THDO_RDEQ_INFOfmt */ 1656 /* nFields */ 2, 1657 /* *fields */ soc_RDE_TO_THDO_RDEQ_INFO_BCM56260_A0fmt_fields, 1658 /* bits */ 6, 1659 /* flags */ 0, 1660 }, 1661 #endif /* chips */ 1662 1663 #if defined(BCM_56270_A0) 1664 { /* SOC_FORMAT_INT_RDE_TO_THDO_RDEQ_INFO_BCM56270_A0fmt */ 1665 /* format RDE_TO_THDO_RDEQ_INFOfmt */ 1666 /* nFields */ 2, 1667 /* *fields */ soc_RDE_TO_THDO_RDEQ_INFO_BCM56270_A0fmt_fields, 1668 /* bits */ 5, 1669 /* flags */ 0, 1670 }, 1671 #endif /* chips */ 1672 1673 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1674 defined(BCM_56450_B1) 1675 { /* SOC_FORMAT_INT_RDE_TO_TOQ_FIFO_MEMfmt */ 1676 /* format RDE_TO_TOQ_FIFO_MEMfmt */ 1677 /* nFields */ 9, 1678 /* *fields */ soc_RDE_TO_TOQ_FIFO_MEMfmt_fields, 1679 /* bits */ 142, 1680 /* flags */ 0, 1681 }, 1682 #endif /* chips */ 1683 1684 #if defined(BCM_56260_A0) 1685 { /* SOC_FORMAT_INT_RDE_TO_TOQ_FIFO_MEM_BCM56260_A0fmt */ 1686 /* format RDE_TO_TOQ_FIFO_MEMfmt */ 1687 /* nFields */ 9, 1688 /* *fields */ soc_RDE_TO_TOQ_FIFO_MEM_BCM56260_A0fmt_fields, 1689 /* bits */ 132, 1690 /* flags */ 0, 1691 }, 1692 #endif /* chips */ 1693 1694 #if defined(BCM_56260_B0) 1695 { /* SOC_FORMAT_INT_RDE_TO_TOQ_FIFO_MEM_BCM56260_B0fmt */ 1696 /* format RDE_TO_TOQ_FIFO_MEMfmt */ 1697 /* nFields */ 9, 1698 /* *fields */ soc_RDE_TO_TOQ_FIFO_MEM_BCM56260_A0fmt_fields, 1699 /* bits */ 132, 1700 /* flags */ 0, 1701 }, 1702 #endif /* chips */ 1703 1704 #if defined(BCM_56270_A0) 1705 { /* SOC_FORMAT_INT_RDE_TO_TOQ_FIFO_MEM_BCM56270_A0fmt */ 1706 /* format RDE_TO_TOQ_FIFO_MEMfmt */ 1707 /* nFields */ 9, 1708 /* *fields */ soc_RDE_TO_TOQ_FIFO_MEM_BCM56270_A0fmt_fields, 1709 /* bits */ 112, 1710 /* flags */ 0, 1711 }, 1712 #endif /* chips */ 1713 1714 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) 1715 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFOfmt */ 1716 /* format RDE_TO_TOQ_INFOfmt */ 1717 /* nFields */ 7, 1718 /* *fields */ soc_RDE_TO_TOQ_INFOfmt_fields, 1719 /* bits */ 45, 1720 /* flags */ 0, 1721 }, 1722 #endif /* chips */ 1723 1724 #if defined(BCM_56260_A0) 1725 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56260_A0fmt */ 1726 /* format RDE_TO_TOQ_INFOfmt */ 1727 /* nFields */ 12, 1728 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56260_A0fmt_fields, 1729 /* bits */ 60, 1730 /* flags */ 0, 1731 }, 1732 #endif /* chips */ 1733 1734 #if defined(BCM_56260_B0) 1735 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56260_B0fmt */ 1736 /* format RDE_TO_TOQ_INFOfmt */ 1737 /* nFields */ 12, 1738 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56260_A0fmt_fields, 1739 /* bits */ 60, 1740 /* flags */ 0, 1741 }, 1742 #endif /* chips */ 1743 1744 #if defined(BCM_56270_A0) 1745 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56270_A0fmt */ 1746 /* format RDE_TO_TOQ_INFOfmt */ 1747 /* nFields */ 11, 1748 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56270_A0fmt_fields, 1749 /* bits */ 50, 1750 /* flags */ 0, 1751 }, 1752 #endif /* chips */ 1753 1754 #if defined(BCM_56340_A0) 1755 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56340_A0fmt */ 1756 /* format RDE_TO_TOQ_INFOfmt */ 1757 /* nFields */ 5, 1758 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56640_A0fmt_fields, 1759 /* bits */ 31, 1760 /* flags */ 0, 1761 }, 1762 #endif /* chips */ 1763 1764 #if defined(BCM_56450_A0) 1765 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56450_A0fmt */ 1766 /* format RDE_TO_TOQ_INFOfmt */ 1767 /* nFields */ 12, 1768 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56450_A0fmt_fields, 1769 /* bits */ 65, 1770 /* flags */ 0, 1771 }, 1772 #endif /* chips */ 1773 1774 #if defined(BCM_56450_B0) 1775 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56450_B0fmt */ 1776 /* format RDE_TO_TOQ_INFOfmt */ 1777 /* nFields */ 12, 1778 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56450_A0fmt_fields, 1779 /* bits */ 65, 1780 /* flags */ 0, 1781 }, 1782 #endif /* chips */ 1783 1784 #if defined(BCM_56450_B1) 1785 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56450_B1fmt */ 1786 /* format RDE_TO_TOQ_INFOfmt */ 1787 /* nFields */ 12, 1788 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56450_A0fmt_fields, 1789 /* bits */ 65, 1790 /* flags */ 0, 1791 }, 1792 #endif /* chips */ 1793 1794 #if defined(BCM_56524_B0) 1795 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56524_B0fmt */ 1796 /* format RDE_TO_TOQ_INFOfmt */ 1797 /* nFields */ 7, 1798 /* *fields */ soc_RDE_TO_TOQ_INFOfmt_fields, 1799 /* bits */ 45, 1800 /* flags */ 0, 1801 }, 1802 #endif /* chips */ 1803 1804 #if defined(BCM_56634_B0) 1805 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56634_B0fmt */ 1806 /* format RDE_TO_TOQ_INFOfmt */ 1807 /* nFields */ 7, 1808 /* *fields */ soc_RDE_TO_TOQ_INFOfmt_fields, 1809 /* bits */ 45, 1810 /* flags */ 0, 1811 }, 1812 #endif /* chips */ 1813 1814 #if defined(BCM_56640_A0) 1815 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56640_A0fmt */ 1816 /* format RDE_TO_TOQ_INFOfmt */ 1817 /* nFields */ 5, 1818 /* *fields */ soc_RDE_TO_TOQ_INFO_BCM56640_A0fmt_fields, 1819 /* bits */ 31, 1820 /* flags */ 0, 1821 }, 1822 #endif /* chips */ 1823 1824 #if defined(BCM_56685_A0) 1825 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56685_A0fmt */ 1826 /* format RDE_TO_TOQ_INFOfmt */ 1827 /* nFields */ 7, 1828 /* *fields */ soc_RDE_TO_TOQ_INFOfmt_fields, 1829 /* bits */ 45, 1830 /* flags */ 0, 1831 }, 1832 #endif /* chips */ 1833 1834 #if defined(BCM_56685_B0) 1835 { /* SOC_FORMAT_INT_RDE_TO_TOQ_INFO_BCM56685_B0fmt */ 1836 /* format RDE_TO_TOQ_INFOfmt */ 1837 /* nFields */ 7, 1838 /* *fields */ soc_RDE_TO_TOQ_INFOfmt_fields, 1839 /* bits */ 45, 1840 /* flags */ 0, 1841 }, 1842 #endif /* chips */ 1843 1844 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1845 defined(BCM_56450_B1) 1846 { /* SOC_FORMAT_INT_RDE_TXQ_WR_FIFO_INFOfmt */ 1847 /* format RDE_TXQ_WR_FIFO_INFOfmt */ 1848 /* nFields */ 2, 1849 /* *fields */ soc_RDE_TXQ_WR_FIFO_INFOfmt_fields, 1850 /* bits */ 110, 1851 /* flags */ 0, 1852 }, 1853 #endif /* chips */ 1854 1855 #if defined(BCM_56260_A0) 1856 { /* SOC_FORMAT_INT_RDE_TXQ_WR_FIFO_INFO_BCM56260_A0fmt */ 1857 /* format RDE_TXQ_WR_FIFO_INFOfmt */ 1858 /* nFields */ 2, 1859 /* *fields */ soc_RDE_TXQ_WR_FIFO_INFO_BCM56260_A0fmt_fields, 1860 /* bits */ 103, 1861 /* flags */ 0, 1862 }, 1863 #endif /* chips */ 1864 1865 #if defined(BCM_56260_B0) 1866 { /* SOC_FORMAT_INT_RDE_TXQ_WR_FIFO_INFO_BCM56260_B0fmt */ 1867 /* format RDE_TXQ_WR_FIFO_INFOfmt */ 1868 /* nFields */ 2, 1869 /* *fields */ soc_RDE_TXQ_WR_FIFO_INFO_BCM56260_A0fmt_fields, 1870 /* bits */ 103, 1871 /* flags */ 0, 1872 }, 1873 #endif /* chips */ 1874 1875 #if defined(BCM_56270_A0) 1876 { /* SOC_FORMAT_INT_RDE_TXQ_WR_FIFO_INFO_BCM56270_A0fmt */ 1877 /* format RDE_TXQ_WR_FIFO_INFOfmt */ 1878 /* nFields */ 2, 1879 /* *fields */ soc_RDE_TXQ_WR_FIFO_INFO_BCM56270_A0fmt_fields, 1880 /* bits */ 85, 1881 /* flags */ 0, 1882 }, 1883 #endif /* chips */ 1884 1885 #if defined(BCM_56634_A0) 1886 { /* SOC_FORMAT_INT_REDIRECT_TO_CCP_INFOfmt */ 1887 /* format REDIRECT_TO_CCP_INFOfmt */ 1888 /* nFields */ 2, 1889 /* *fields */ soc_REDIRECT_TO_CCP_INFOfmt_fields, 1890 /* bits */ 16, 1891 /* flags */ 0, 1892 }, 1893 #endif /* chips */ 1894 1895 #if defined(BCM_56524_A0) 1896 { /* SOC_FORMAT_INT_REDIRECT_TO_CCP_INFO_BCM56524_A0fmt */ 1897 /* format REDIRECT_TO_CCP_INFOfmt */ 1898 /* nFields */ 2, 1899 /* *fields */ soc_REDIRECT_TO_CCP_INFOfmt_fields, 1900 /* bits */ 16, 1901 /* flags */ 0, 1902 }, 1903 #endif /* chips */ 1904 1905 #if defined(BCM_56524_B0) 1906 { /* SOC_FORMAT_INT_REDIRECT_TO_CCP_INFO_BCM56524_B0fmt */ 1907 /* format REDIRECT_TO_CCP_INFOfmt */ 1908 /* nFields */ 2, 1909 /* *fields */ soc_REDIRECT_TO_CCP_INFOfmt_fields, 1910 /* bits */ 16, 1911 /* flags */ 0, 1912 }, 1913 #endif /* chips */ 1914 1915 #if defined(BCM_56634_B0) 1916 { /* SOC_FORMAT_INT_REDIRECT_TO_CCP_INFO_BCM56634_B0fmt */ 1917 /* format REDIRECT_TO_CCP_INFOfmt */ 1918 /* nFields */ 2, 1919 /* *fields */ soc_REDIRECT_TO_CCP_INFOfmt_fields, 1920 /* bits */ 16, 1921 /* flags */ 0, 1922 }, 1923 #endif /* chips */ 1924 1925 #if defined(BCM_56685_A0) 1926 { /* SOC_FORMAT_INT_REDIRECT_TO_CCP_INFO_BCM56685_A0fmt */ 1927 /* format REDIRECT_TO_CCP_INFOfmt */ 1928 /* nFields */ 2, 1929 /* *fields */ soc_REDIRECT_TO_CCP_INFOfmt_fields, 1930 /* bits */ 16, 1931 /* flags */ 0, 1932 }, 1933 #endif /* chips */ 1934 1935 #if defined(BCM_56685_B0) 1936 { /* SOC_FORMAT_INT_REDIRECT_TO_CCP_INFO_BCM56685_B0fmt */ 1937 /* format REDIRECT_TO_CCP_INFOfmt */ 1938 /* nFields */ 2, 1939 /* *fields */ soc_REDIRECT_TO_CCP_INFOfmt_fields, 1940 /* bits */ 16, 1941 /* flags */ 0, 1942 }, 1943 #endif /* chips */ 1944 1945 #if defined(BCM_56634_A0) 1946 { /* SOC_FORMAT_INT_REDIRECT_TO_THDI_INFOfmt */ 1947 /* format REDIRECT_TO_THDI_INFOfmt */ 1948 /* nFields */ 6, 1949 /* *fields */ soc_REDIRECT_TO_THDI_INFOfmt_fields, 1950 /* bits */ 13, 1951 /* flags */ 0, 1952 }, 1953 #endif /* chips */ 1954 1955 #if defined(BCM_56524_A0) 1956 { /* SOC_FORMAT_INT_REDIRECT_TO_THDI_INFO_BCM56524_A0fmt */ 1957 /* format REDIRECT_TO_THDI_INFOfmt */ 1958 /* nFields */ 6, 1959 /* *fields */ soc_REDIRECT_TO_THDI_INFOfmt_fields, 1960 /* bits */ 13, 1961 /* flags */ 0, 1962 }, 1963 #endif /* chips */ 1964 1965 #if defined(BCM_56524_B0) 1966 { /* SOC_FORMAT_INT_REDIRECT_TO_THDI_INFO_BCM56524_B0fmt */ 1967 /* format REDIRECT_TO_THDI_INFOfmt */ 1968 /* nFields */ 6, 1969 /* *fields */ soc_REDIRECT_TO_THDI_INFOfmt_fields, 1970 /* bits */ 13, 1971 /* flags */ 0, 1972 }, 1973 #endif /* chips */ 1974 1975 #if defined(BCM_56634_B0) 1976 { /* SOC_FORMAT_INT_REDIRECT_TO_THDI_INFO_BCM56634_B0fmt */ 1977 /* format REDIRECT_TO_THDI_INFOfmt */ 1978 /* nFields */ 6, 1979 /* *fields */ soc_REDIRECT_TO_THDI_INFOfmt_fields, 1980 /* bits */ 13, 1981 /* flags */ 0, 1982 }, 1983 #endif /* chips */ 1984 1985 #if defined(BCM_56685_A0) 1986 { /* SOC_FORMAT_INT_REDIRECT_TO_THDI_INFO_BCM56685_A0fmt */ 1987 /* format REDIRECT_TO_THDI_INFOfmt */ 1988 /* nFields */ 6, 1989 /* *fields */ soc_REDIRECT_TO_THDI_INFOfmt_fields, 1990 /* bits */ 13, 1991 /* flags */ 0, 1992 }, 1993 #endif /* chips */ 1994 1995 #if defined(BCM_56685_B0) 1996 { /* SOC_FORMAT_INT_REDIRECT_TO_THDI_INFO_BCM56685_B0fmt */ 1997 /* format REDIRECT_TO_THDI_INFOfmt */ 1998 /* nFields */ 6, 1999 /* *fields */ soc_REDIRECT_TO_THDI_INFOfmt_fields, 2000 /* bits */ 13, 2001 /* flags */ 0, 2002 }, 2003 #endif /* chips */ 2004 2005 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 2006 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO3_INFOfmt */ 2007 /* format REDIRECT_TO_THDO3_INFOfmt */ 2008 /* nFields */ 4, 2009 /* *fields */ soc_REDIRECT_TO_THDO3_INFOfmt_fields, 2010 /* bits */ 13, 2011 /* flags */ 0, 2012 }, 2013 #endif /* chips */ 2014 2015 #if defined(BCM_56524_A0) 2016 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO3_INFO_BCM56524_A0fmt */ 2017 /* format REDIRECT_TO_THDO3_INFOfmt */ 2018 /* nFields */ 4, 2019 /* *fields */ soc_REDIRECT_TO_THDO3_INFOfmt_fields, 2020 /* bits */ 13, 2021 /* flags */ 0, 2022 }, 2023 #endif /* chips */ 2024 2025 #if defined(BCM_56524_B0) 2026 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO3_INFO_BCM56524_B0fmt */ 2027 /* format REDIRECT_TO_THDO3_INFOfmt */ 2028 /* nFields */ 4, 2029 /* *fields */ soc_REDIRECT_TO_THDO3_INFOfmt_fields, 2030 /* bits */ 13, 2031 /* flags */ 0, 2032 }, 2033 #endif /* chips */ 2034 2035 #if defined(BCM_56685_A0) 2036 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO3_INFO_BCM56685_A0fmt */ 2037 /* format REDIRECT_TO_THDO3_INFOfmt */ 2038 /* nFields */ 4, 2039 /* *fields */ soc_REDIRECT_TO_THDO3_INFOfmt_fields, 2040 /* bits */ 13, 2041 /* flags */ 0, 2042 }, 2043 #endif /* chips */ 2044 2045 #if defined(BCM_56685_B0) 2046 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO3_INFO_BCM56685_B0fmt */ 2047 /* format REDIRECT_TO_THDO3_INFOfmt */ 2048 /* nFields */ 4, 2049 /* *fields */ soc_REDIRECT_TO_THDO3_INFOfmt_fields, 2050 /* bits */ 13, 2051 /* flags */ 0, 2052 }, 2053 #endif /* chips */ 2054 2055 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 2056 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO_INFOfmt */ 2057 /* format REDIRECT_TO_THDO_INFOfmt */ 2058 /* nFields */ 5, 2059 /* *fields */ soc_REDIRECT_TO_THDO_INFOfmt_fields, 2060 /* bits */ 7, 2061 /* flags */ 0, 2062 }, 2063 #endif /* chips */ 2064 2065 #if defined(BCM_56524_A0) 2066 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO_INFO_BCM56524_A0fmt */ 2067 /* format REDIRECT_TO_THDO_INFOfmt */ 2068 /* nFields */ 5, 2069 /* *fields */ soc_REDIRECT_TO_THDO_INFOfmt_fields, 2070 /* bits */ 7, 2071 /* flags */ 0, 2072 }, 2073 #endif /* chips */ 2074 2075 #if defined(BCM_56524_B0) 2076 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO_INFO_BCM56524_B0fmt */ 2077 /* format REDIRECT_TO_THDO_INFOfmt */ 2078 /* nFields */ 5, 2079 /* *fields */ soc_REDIRECT_TO_THDO_INFOfmt_fields, 2080 /* bits */ 7, 2081 /* flags */ 0, 2082 }, 2083 #endif /* chips */ 2084 2085 #if defined(BCM_56685_A0) 2086 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO_INFO_BCM56685_A0fmt */ 2087 /* format REDIRECT_TO_THDO_INFOfmt */ 2088 /* nFields */ 5, 2089 /* *fields */ soc_REDIRECT_TO_THDO_INFOfmt_fields, 2090 /* bits */ 7, 2091 /* flags */ 0, 2092 }, 2093 #endif /* chips */ 2094 2095 #if defined(BCM_56685_B0) 2096 { /* SOC_FORMAT_INT_REDIRECT_TO_THDO_INFO_BCM56685_B0fmt */ 2097 /* format REDIRECT_TO_THDO_INFOfmt */ 2098 /* nFields */ 5, 2099 /* *fields */ soc_REDIRECT_TO_THDO_INFOfmt_fields, 2100 /* bits */ 7, 2101 /* flags */ 0, 2102 }, 2103 #endif /* chips */ 2104 2105 #if defined(BCM_56640_A0) 2106 { /* SOC_FORMAT_INT_REFRESH_BITMAPfmt */ 2107 /* format REFRESH_BITMAPfmt */ 2108 /* nFields */ 7, 2109 /* *fields */ soc_REFRESH_BITMAPfmt_fields, 2110 /* bits */ 7, 2111 /* flags */ 0, 2112 }, 2113 #endif /* chips */ 2114 2115 #if defined(BCM_56340_A0) 2116 { /* SOC_FORMAT_INT_REFRESH_BITMAP_BCM56340_A0fmt */ 2117 /* format REFRESH_BITMAPfmt */ 2118 /* nFields */ 6, 2119 /* *fields */ soc_REFRESH_BITMAP_BCM56340_A0fmt_fields, 2120 /* bits */ 6, 2121 /* flags */ 0, 2122 }, 2123 #endif /* chips */ 2124 2125 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2126 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 2127 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 2128 defined(BCM_56980_A0) || defined(BCM_56980_B0) 2129 { /* SOC_FORMAT_INT_REGADDRfmt */ 2130 /* format REGADDRfmt */ 2131 /* nFields */ 4, 2132 /* *fields */ soc_REGADDRfmt_fields, 2133 /* bits */ 32, 2134 /* flags */ 0, 2135 }, 2136 #endif /* chips */ 2137 2138 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2139 defined(BCM_56870_A0) || defined(BCM_56980_A0) || \ 2140 defined(BCM_56980_B0) 2141 { /* SOC_FORMAT_INT_REMAP_TABLEfmt */ 2142 /* format REMAP_TABLEfmt */ 2143 /* nFields */ 1, 2144 /* *fields */ soc_REMAP_TABLEfmt_fields, 2145 /* bits */ 12, 2146 /* flags */ 0, 2147 }, 2148 #endif /* chips */ 2149 2150 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2151 defined(BCM_56870_A0) || defined(BCM_56980_A0) || \ 2152 defined(BCM_56980_B0) 2153 { /* SOC_FORMAT_INT_REMAP_TABLE_ECCfmt */ 2154 /* format REMAP_TABLE_ECCfmt */ 2155 /* nFields */ 5, 2156 /* *fields */ soc_REMAP_TABLE_ECCfmt_fields, 2157 /* bits */ 18, 2158 /* flags */ 0, 2159 }, 2160 #endif /* chips */ 2161 2162 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2163 { /* SOC_FORMAT_INT_REQ_BUS_CPfmt */ 2164 /* format REQ_BUS_CPfmt */ 2165 /* nFields */ 14, 2166 /* *fields */ soc_REQ_BUS_CPfmt_fields, 2167 /* bits */ 480, 2168 /* flags */ 0, 2169 }, 2170 #endif /* chips */ 2171 2172 #if defined(BCM_56370_A0) 2173 { /* SOC_FORMAT_INT_REQ_BUS_CP_BCM56370_A0fmt */ 2174 /* format REQ_BUS_CPfmt */ 2175 /* nFields */ 7, 2176 /* *fields */ soc_REQ_BUS_CP_BCM56870_A0fmt_fields, 2177 /* bits */ 144, 2178 /* flags */ 0, 2179 }, 2180 #endif /* chips */ 2181 2182 #if defined(BCM_56770_A0) 2183 { /* SOC_FORMAT_INT_REQ_BUS_CP_BCM56770_A0fmt */ 2184 /* format REQ_BUS_CPfmt */ 2185 /* nFields */ 7, 2186 /* *fields */ soc_REQ_BUS_CP_BCM56870_A0fmt_fields, 2187 /* bits */ 144, 2188 /* flags */ 0, 2189 }, 2190 #endif /* chips */ 2191 2192 #if defined(BCM_56870_A0) 2193 { /* SOC_FORMAT_INT_REQ_BUS_CP_BCM56870_A0fmt */ 2194 /* format REQ_BUS_CPfmt */ 2195 /* nFields */ 7, 2196 /* *fields */ soc_REQ_BUS_CP_BCM56870_A0fmt_fields, 2197 /* bits */ 144, 2198 /* flags */ 0, 2199 }, 2200 #endif /* chips */ 2201 2202 #if defined(BCM_56960_A0) 2203 { /* SOC_FORMAT_INT_REQ_BUS_CP_BCM56960_A0fmt */ 2204 /* format REQ_BUS_CPfmt */ 2205 /* nFields */ 9, 2206 /* *fields */ soc_REQ_BUS_CP_BCM56960_A0fmt_fields, 2207 /* bits */ 139, 2208 /* flags */ 0, 2209 }, 2210 #endif /* chips */ 2211 2212 #if defined(BCM_56965_A0) 2213 { /* SOC_FORMAT_INT_REQ_BUS_CP_BCM56965_A0fmt */ 2214 /* format REQ_BUS_CPfmt */ 2215 /* nFields */ 9, 2216 /* *fields */ soc_REQ_BUS_CP_BCM56960_A0fmt_fields, 2217 /* bits */ 139, 2218 /* flags */ 0, 2219 }, 2220 #endif /* chips */ 2221 2222 #if defined(BCM_56970_A0) 2223 { /* SOC_FORMAT_INT_REQ_BUS_CP_BCM56970_A0fmt */ 2224 /* format REQ_BUS_CPfmt */ 2225 /* nFields */ 9, 2226 /* *fields */ soc_REQ_BUS_CP_BCM56970_A0fmt_fields, 2227 /* bits */ 140, 2228 /* flags */ 0, 2229 }, 2230 #endif /* chips */ 2231 2232 #if defined(BCM_56640_A0) 2233 { /* SOC_FORMAT_INT_REQ_BUS_EXT_ADfmt */ 2234 /* format REQ_BUS_EXT_ADfmt */ 2235 /* nFields */ 5, 2236 /* *fields */ soc_REQ_BUS_EXT_ADfmt_fields, 2237 /* bits */ 32, 2238 /* flags */ 0, 2239 }, 2240 #endif /* chips */ 2241 2242 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2243 { /* SOC_FORMAT_INT_REQ_BUS_HITBITfmt */ 2244 /* format REQ_BUS_HITBITfmt */ 2245 /* nFields */ 3, 2246 /* *fields */ soc_REQ_BUS_HITBITfmt_fields, 2247 /* bits */ 21, 2248 /* flags */ 0, 2249 }, 2250 #endif /* chips */ 2251 2252 #if defined(BCM_56640_A0) 2253 { /* SOC_FORMAT_INT_REQ_BUS_MAC_LIMITfmt */ 2254 /* format REQ_BUS_MAC_LIMITfmt */ 2255 /* nFields */ 3, 2256 /* *fields */ soc_REQ_BUS_MAC_LIMITfmt_fields, 2257 /* bits */ 27, 2258 /* flags */ 0, 2259 }, 2260 #endif /* chips */ 2261 2262 #if defined(BCM_56340_A0) 2263 { /* SOC_FORMAT_INT_REQ_BUS_MAC_LIMIT_BCM56340_A0fmt */ 2264 /* format REQ_BUS_MAC_LIMITfmt */ 2265 /* nFields */ 4, 2266 /* *fields */ soc_REQ_BUS_MAC_LIMIT_BCM56340_A0fmt_fields, 2267 /* bits */ 27, 2268 /* flags */ 0, 2269 }, 2270 #endif /* chips */ 2271 2272 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2273 { /* SOC_FORMAT_INT_REQ_BUS_MAC_LIMIT_CPfmt */ 2274 /* format REQ_BUS_MAC_LIMIT_CPfmt */ 2275 /* nFields */ 12, 2276 /* *fields */ soc_REQ_BUS_MAC_LIMIT_CPfmt_fields, 2277 /* bits */ 47, 2278 /* flags */ 0, 2279 }, 2280 #endif /* chips */ 2281 2282 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2283 { /* SOC_FORMAT_INT_REQ_BUS_MOD_FIFO_CPfmt */ 2284 /* format REQ_BUS_MOD_FIFO_CPfmt */ 2285 /* nFields */ 4, 2286 /* *fields */ soc_REQ_BUS_MOD_FIFO_CPfmt_fields, 2287 /* bits */ 324, 2288 /* flags */ 0, 2289 }, 2290 #endif /* chips */ 2291 2292 #if defined(BCM_56370_A0) 2293 { /* SOC_FORMAT_INT_REQ_BUS_MOD_FIFO_CP_BCM56370_A0fmt */ 2294 /* format REQ_BUS_MOD_FIFO_CPfmt */ 2295 /* nFields */ 4, 2296 /* *fields */ soc_REQ_BUS_MOD_FIFO_CP_BCM56960_A0fmt_fields, 2297 /* bits */ 324, 2298 /* flags */ 0, 2299 }, 2300 #endif /* chips */ 2301 2302 #if defined(BCM_56770_A0) 2303 { /* SOC_FORMAT_INT_REQ_BUS_MOD_FIFO_CP_BCM56770_A0fmt */ 2304 /* format REQ_BUS_MOD_FIFO_CPfmt */ 2305 /* nFields */ 4, 2306 /* *fields */ soc_REQ_BUS_MOD_FIFO_CP_BCM56960_A0fmt_fields, 2307 /* bits */ 324, 2308 /* flags */ 0, 2309 }, 2310 #endif /* chips */ 2311 2312 #if defined(BCM_56870_A0) 2313 { /* SOC_FORMAT_INT_REQ_BUS_MOD_FIFO_CP_BCM56870_A0fmt */ 2314 /* format REQ_BUS_MOD_FIFO_CPfmt */ 2315 /* nFields */ 4, 2316 /* *fields */ soc_REQ_BUS_MOD_FIFO_CP_BCM56960_A0fmt_fields, 2317 /* bits */ 324, 2318 /* flags */ 0, 2319 }, 2320 #endif /* chips */ 2321 2322 #if defined(BCM_56960_A0) 2323 { /* SOC_FORMAT_INT_REQ_BUS_MOD_FIFO_CP_BCM56960_A0fmt */ 2324 /* format REQ_BUS_MOD_FIFO_CPfmt */ 2325 /* nFields */ 4, 2326 /* *fields */ soc_REQ_BUS_MOD_FIFO_CP_BCM56960_A0fmt_fields, 2327 /* bits */ 324, 2328 /* flags */ 0, 2329 }, 2330 #endif /* chips */ 2331 2332 #if defined(BCM_56965_A0) 2333 { /* SOC_FORMAT_INT_REQ_BUS_MOD_FIFO_CP_BCM56965_A0fmt */ 2334 /* format REQ_BUS_MOD_FIFO_CPfmt */ 2335 /* nFields */ 4, 2336 /* *fields */ soc_REQ_BUS_MOD_FIFO_CP_BCM56960_A0fmt_fields, 2337 /* bits */ 324, 2338 /* flags */ 0, 2339 }, 2340 #endif /* chips */ 2341 2342 #if defined(BCM_56970_A0) 2343 { /* SOC_FORMAT_INT_REQ_BUS_MOD_FIFO_CP_BCM56970_A0fmt */ 2344 /* format REQ_BUS_MOD_FIFO_CPfmt */ 2345 /* nFields */ 4, 2346 /* *fields */ soc_REQ_BUS_MOD_FIFO_CP_BCM56960_A0fmt_fields, 2347 /* bits */ 324, 2348 /* flags */ 0, 2349 }, 2350 #endif /* chips */ 2351 2352 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2353 { /* SOC_FORMAT_INT_REQ_BUS_PIPE_TBL0fmt */ 2354 /* format REQ_BUS_PIPE_TBL0fmt */ 2355 /* nFields */ 4, 2356 /* *fields */ soc_REQ_BUS_PIPE_TBL0fmt_fields, 2357 /* bits */ 60, 2358 /* flags */ 0, 2359 }, 2360 #endif /* chips */ 2361 2362 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2363 { /* SOC_FORMAT_INT_REQ_BUS_PIPE_TBL1fmt */ 2364 /* format REQ_BUS_PIPE_TBL1fmt */ 2365 /* nFields */ 4, 2366 /* *fields */ soc_REQ_BUS_PIPE_TBL1fmt_fields, 2367 /* bits */ 75, 2368 /* flags */ 0, 2369 }, 2370 #endif /* chips */ 2371 2372 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2373 { /* SOC_FORMAT_INT_REQ_BUS_PIPE_TBL2fmt */ 2374 /* format REQ_BUS_PIPE_TBL2fmt */ 2375 /* nFields */ 4, 2376 /* *fields */ soc_REQ_BUS_PIPE_TBL2fmt_fields, 2377 /* bits */ 152, 2378 /* flags */ 0, 2379 }, 2380 #endif /* chips */ 2381 2382 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2383 { /* SOC_FORMAT_INT_REQ_BUS_PIPE_TBL3fmt */ 2384 /* format REQ_BUS_PIPE_TBL3fmt */ 2385 /* nFields */ 4, 2386 /* *fields */ soc_REQ_BUS_PIPE_TBL3fmt_fields, 2387 /* bits */ 50, 2388 /* flags */ 0, 2389 }, 2390 #endif /* chips */ 2391 2392 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2393 { /* SOC_FORMAT_INT_REQ_BUS_PIPE_TBL4fmt */ 2394 /* format REQ_BUS_PIPE_TBL4fmt */ 2395 /* nFields */ 4, 2396 /* *fields */ soc_REQ_BUS_PIPE_TBL4fmt_fields, 2397 /* bits */ 96, 2398 /* flags */ 0, 2399 }, 2400 #endif /* chips */ 2401 2402 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2403 { /* SOC_FORMAT_INT_REQ_BUS_PIPE_TBL2_LOGICALfmt */ 2404 /* format REQ_BUS_PIPE_TBL2_LOGICALfmt */ 2405 /* nFields */ 3, 2406 /* *fields */ soc_REQ_BUS_PIPE_TBL2_LOGICALfmt_fields, 2407 /* bits */ 282, 2408 /* flags */ 0, 2409 }, 2410 #endif /* chips */ 2411 2412 #if defined(BCM_56640_A0) 2413 { /* SOC_FORMAT_INT_REQ_DATA_EXT_AD_CPfmt */ 2414 /* format REQ_DATA_EXT_AD_CPfmt */ 2415 /* nFields */ 11, 2416 /* *fields */ soc_REQ_DATA_EXT_AD_CPfmt_fields, 2417 /* bits */ 245, 2418 /* flags */ 0, 2419 }, 2420 #endif /* chips */ 2421 2422 #if defined(BCM_56640_A0) 2423 { /* SOC_FORMAT_INT_REQ_DATA_EXT_L2fmt */ 2424 /* format REQ_DATA_EXT_L2fmt */ 2425 /* nFields */ 13, 2426 /* *fields */ soc_REQ_DATA_EXT_L2fmt_fields, 2427 /* bits */ 172, 2428 /* flags */ 0, 2429 }, 2430 #endif /* chips */ 2431 2432 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2433 defined(BCM_56870_A0) 2434 { /* SOC_FORMAT_INT_RESPONSIVE_PROTOCOL_MATCH_INDEXfmt */ 2435 /* format RESPONSIVE_PROTOCOL_MATCH_INDEXfmt */ 2436 /* nFields */ 2, 2437 /* *fields */ soc_RESPONSIVE_PROTOCOL_MATCH_INDEXfmt_fields, 2438 /* bits */ 3, 2439 /* flags */ 0, 2440 }, 2441 #endif /* chips */ 2442 2443 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2444 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 2445 defined(BCM_56965_A0) || defined(BCM_56970_A0) 2446 { /* SOC_FORMAT_INT_RIL_TO_DQS_INFOfmt */ 2447 /* format RIL_TO_DQS_INFOfmt */ 2448 /* nFields */ 2, 2449 /* *fields */ soc_RIL_TO_DQS_INFOfmt_fields, 2450 /* bits */ 17, 2451 /* flags */ 0, 2452 }, 2453 #endif /* chips */ 2454 2455 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 2456 defined(BCM_56850_A0) || defined(BCM_56860_A0) 2457 { /* SOC_FORMAT_INT_RMEP_COV_DEFSfmt */ 2458 /* format RMEP_COV_DEFSfmt */ 2459 /* nFields */ 7, 2460 /* *fields */ soc_RMEP_COV_DEFSfmt_fields, 2461 /* bits */ 23, 2462 /* flags */ 0, 2463 }, 2464 #endif /* chips */ 2465 2466 #if defined(BCM_53400_A0) 2467 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM53400_A0fmt */ 2468 /* format RMEP_COV_DEFSfmt */ 2469 /* nFields */ 7, 2470 /* *fields */ soc_RMEP_COV_DEFS_BCM53400_A0fmt_fields, 2471 /* bits */ 21, 2472 /* flags */ 0, 2473 }, 2474 #endif /* chips */ 2475 2476 #if defined(BCM_53540_A0) 2477 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM53540_A0fmt */ 2478 /* format RMEP_COV_DEFSfmt */ 2479 /* nFields */ 7, 2480 /* *fields */ soc_RMEP_COV_DEFS_BCM53400_A0fmt_fields, 2481 /* bits */ 21, 2482 /* flags */ 0, 2483 }, 2484 #endif /* chips */ 2485 2486 #if defined(BCM_53570_A0) 2487 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM53570_A0fmt */ 2488 /* format RMEP_COV_DEFSfmt */ 2489 /* nFields */ 7, 2490 /* *fields */ soc_RMEP_COV_DEFS_BCM53400_A0fmt_fields, 2491 /* bits */ 21, 2492 /* flags */ 0, 2493 }, 2494 #endif /* chips */ 2495 2496 #if defined(BCM_53570_B0) 2497 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM53570_B0fmt */ 2498 /* format RMEP_COV_DEFSfmt */ 2499 /* nFields */ 7, 2500 /* *fields */ soc_RMEP_COV_DEFS_BCM53400_A0fmt_fields, 2501 /* bits */ 21, 2502 /* flags */ 0, 2503 }, 2504 #endif /* chips */ 2505 2506 #if defined(BCM_56150_A0) 2507 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM56150_A0fmt */ 2508 /* format RMEP_COV_DEFSfmt */ 2509 /* nFields */ 7, 2510 /* *fields */ soc_RMEP_COV_DEFS_BCM56150_A0fmt_fields, 2511 /* bits */ 21, 2512 /* flags */ 0, 2513 }, 2514 #endif /* chips */ 2515 2516 #if defined(BCM_56160_A0) 2517 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM56160_A0fmt */ 2518 /* format RMEP_COV_DEFSfmt */ 2519 /* nFields */ 7, 2520 /* *fields */ soc_RMEP_COV_DEFS_BCM53400_A0fmt_fields, 2521 /* bits */ 21, 2522 /* flags */ 0, 2523 }, 2524 #endif /* chips */ 2525 2526 #if defined(BCM_56560_A0) 2527 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM56560_A0fmt */ 2528 /* format RMEP_COV_DEFSfmt */ 2529 /* nFields */ 7, 2530 /* *fields */ soc_RMEP_COV_DEFS_BCM56560_A0fmt_fields, 2531 /* bits */ 23, 2532 /* flags */ 0, 2533 }, 2534 #endif /* chips */ 2535 2536 #if defined(BCM_56560_B0) 2537 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM56560_B0fmt */ 2538 /* format RMEP_COV_DEFSfmt */ 2539 /* nFields */ 7, 2540 /* *fields */ soc_RMEP_COV_DEFS_BCM56560_A0fmt_fields, 2541 /* bits */ 23, 2542 /* flags */ 0, 2543 }, 2544 #endif /* chips */ 2545 2546 #if defined(BCM_56670_A0) 2547 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM56670_A0fmt */ 2548 /* format RMEP_COV_DEFSfmt */ 2549 /* nFields */ 7, 2550 /* *fields */ soc_RMEP_COV_DEFS_BCM56560_A0fmt_fields, 2551 /* bits */ 23, 2552 /* flags */ 0, 2553 }, 2554 #endif /* chips */ 2555 2556 #if defined(BCM_56670_B0) 2557 { /* SOC_FORMAT_INT_RMEP_COV_DEFS_BCM56670_B0fmt */ 2558 /* format RMEP_COV_DEFSfmt */ 2559 /* nFields */ 7, 2560 /* *fields */ soc_RMEP_COV_DEFS_BCM56560_A0fmt_fields, 2561 /* bits */ 23, 2562 /* flags */ 0, 2563 }, 2564 #endif /* chips */ 2565 2566 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 2567 { /* SOC_FORMAT_INT_RQE_QCON_FIFO_INFOfmt */ 2568 /* format RQE_QCON_FIFO_INFOfmt */ 2569 /* nFields */ 9, 2570 /* *fields */ soc_RQE_QCON_FIFO_INFOfmt_fields, 2571 /* bits */ 259, 2572 /* flags */ 0, 2573 }, 2574 #endif /* chips */ 2575 2576 #if defined(BCM_56260_A0) 2577 { /* SOC_FORMAT_INT_RQE_QCON_FIFO_INFO_BCM56260_A0fmt */ 2578 /* format RQE_QCON_FIFO_INFOfmt */ 2579 /* nFields */ 3, 2580 /* *fields */ soc_RQE_QCON_FIFO_INFO_BCM56260_A0fmt_fields, 2581 /* bits */ 141, 2582 /* flags */ 0, 2583 }, 2584 #endif /* chips */ 2585 2586 #if defined(BCM_56260_B0) 2587 { /* SOC_FORMAT_INT_RQE_QCON_FIFO_INFO_BCM56260_B0fmt */ 2588 /* format RQE_QCON_FIFO_INFOfmt */ 2589 /* nFields */ 3, 2590 /* *fields */ soc_RQE_QCON_FIFO_INFO_BCM56260_A0fmt_fields, 2591 /* bits */ 141, 2592 /* flags */ 0, 2593 }, 2594 #endif /* chips */ 2595 2596 #if defined(BCM_56270_A0) 2597 { /* SOC_FORMAT_INT_RQE_QCON_FIFO_INFO_BCM56270_A0fmt */ 2598 /* format RQE_QCON_FIFO_INFOfmt */ 2599 /* nFields */ 3, 2600 /* *fields */ soc_RQE_QCON_FIFO_INFO_BCM56270_A0fmt_fields, 2601 /* bits */ 116, 2602 /* flags */ 0, 2603 }, 2604 #endif /* chips */ 2605 2606 #if defined(BCM_56450_A0) 2607 { /* SOC_FORMAT_INT_RQE_QCON_FIFO_INFO_BCM56450_A0fmt */ 2608 /* format RQE_QCON_FIFO_INFOfmt */ 2609 /* nFields */ 9, 2610 /* *fields */ soc_RQE_QCON_FIFO_INFO_BCM56450_A0fmt_fields, 2611 /* bits */ 274, 2612 /* flags */ 0, 2613 }, 2614 #endif /* chips */ 2615 2616 #if defined(BCM_56450_B0) 2617 { /* SOC_FORMAT_INT_RQE_QCON_FIFO_INFO_BCM56450_B0fmt */ 2618 /* format RQE_QCON_FIFO_INFOfmt */ 2619 /* nFields */ 9, 2620 /* *fields */ soc_RQE_QCON_FIFO_INFO_BCM56450_A0fmt_fields, 2621 /* bits */ 274, 2622 /* flags */ 0, 2623 }, 2624 #endif /* chips */ 2625 2626 #if defined(BCM_56450_B1) 2627 { /* SOC_FORMAT_INT_RQE_QCON_FIFO_INFO_BCM56450_B1fmt */ 2628 /* format RQE_QCON_FIFO_INFOfmt */ 2629 /* nFields */ 9, 2630 /* *fields */ soc_RQE_QCON_FIFO_INFO_BCM56450_A0fmt_fields, 2631 /* bits */ 274, 2632 /* flags */ 0, 2633 }, 2634 #endif /* chips */ 2635 2636 #if defined(BCM_56440_A0) 2637 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2638 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2639 /* nFields */ 9, 2640 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt_fields, 2641 /* bits */ 49, 2642 /* flags */ 0, 2643 }, 2644 #endif /* chips */ 2645 2646 #if defined(BCM_56260_A0) 2647 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56260_A0fmt */ 2648 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2649 /* nFields */ 13, 2650 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56260_A0fmt_fields, 2651 /* bits */ 48, 2652 /* flags */ 0, 2653 }, 2654 #endif /* chips */ 2655 2656 #if defined(BCM_56260_B0) 2657 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56260_B0fmt */ 2658 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2659 /* nFields */ 13, 2660 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56260_A0fmt_fields, 2661 /* bits */ 48, 2662 /* flags */ 0, 2663 }, 2664 #endif /* chips */ 2665 2666 #if defined(BCM_56270_A0) 2667 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56270_A0fmt */ 2668 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2669 /* nFields */ 12, 2670 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56270_A0fmt_fields, 2671 /* bits */ 44, 2672 /* flags */ 0, 2673 }, 2674 #endif /* chips */ 2675 2676 #if defined(BCM_56440_B0) 2677 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56440_B0fmt */ 2678 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2679 /* nFields */ 9, 2680 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt_fields, 2681 /* bits */ 49, 2682 /* flags */ 0, 2683 }, 2684 #endif /* chips */ 2685 2686 #if defined(BCM_56450_A0) 2687 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56450_A0fmt */ 2688 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2689 /* nFields */ 13, 2690 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56450_A0fmt_fields, 2691 /* bits */ 52, 2692 /* flags */ 0, 2693 }, 2694 #endif /* chips */ 2695 2696 #if defined(BCM_56450_B0) 2697 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56450_B0fmt */ 2698 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2699 /* nFields */ 13, 2700 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56450_A0fmt_fields, 2701 /* bits */ 52, 2702 /* flags */ 0, 2703 }, 2704 #endif /* chips */ 2705 2706 #if defined(BCM_56450_B1) 2707 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56450_B1fmt */ 2708 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_LANEfmt */ 2709 /* nFields */ 13, 2710 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_LANE_BCM56450_A0fmt_fields, 2711 /* bits */ 52, 2712 /* flags */ 0, 2713 }, 2714 #endif /* chips */ 2715 2716 #if defined(BCM_56440_A0) 2717 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2718 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2719 /* nFields */ 20, 2720 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt_fields, 2721 /* bits */ 59, 2722 /* flags */ 0, 2723 }, 2724 #endif /* chips */ 2725 2726 #if defined(BCM_56260_A0) 2727 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56260_A0fmt */ 2728 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2729 /* nFields */ 24, 2730 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56260_A0fmt_fields, 2731 /* bits */ 92, 2732 /* flags */ 0, 2733 }, 2734 #endif /* chips */ 2735 2736 #if defined(BCM_56260_B0) 2737 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56260_B0fmt */ 2738 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2739 /* nFields */ 24, 2740 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56260_A0fmt_fields, 2741 /* bits */ 92, 2742 /* flags */ 0, 2743 }, 2744 #endif /* chips */ 2745 2746 #if defined(BCM_56270_A0) 2747 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56270_A0fmt */ 2748 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2749 /* nFields */ 20, 2750 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56270_A0fmt_fields, 2751 /* bits */ 71, 2752 /* flags */ 0, 2753 }, 2754 #endif /* chips */ 2755 2756 #if defined(BCM_56440_B0) 2757 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56440_B0fmt */ 2758 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2759 /* nFields */ 20, 2760 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt_fields, 2761 /* bits */ 59, 2762 /* flags */ 0, 2763 }, 2764 #endif /* chips */ 2765 2766 #if defined(BCM_56450_A0) 2767 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56450_A0fmt */ 2768 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2769 /* nFields */ 20, 2770 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56450_A0fmt_fields, 2771 /* bits */ 62, 2772 /* flags */ 0, 2773 }, 2774 #endif /* chips */ 2775 2776 #if defined(BCM_56450_B0) 2777 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56450_B0fmt */ 2778 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2779 /* nFields */ 20, 2780 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56450_A0fmt_fields, 2781 /* bits */ 62, 2782 /* flags */ 0, 2783 }, 2784 #endif /* chips */ 2785 2786 #if defined(BCM_56450_B1) 2787 { /* SOC_FORMAT_INT_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56450_B1fmt */ 2788 /* format RQE_QID_TO_QCONFLICT_PKT_INFO_SHAREDfmt */ 2789 /* nFields */ 20, 2790 /* *fields */ soc_RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED_BCM56450_A0fmt_fields, 2791 /* bits */ 62, 2792 /* flags */ 0, 2793 }, 2794 #endif /* chips */ 2795 2796 #if defined(BCM_56440_A0) 2797 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFOfmt */ 2798 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2799 /* nFields */ 3, 2800 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFOfmt_fields, 2801 /* bits */ 29, 2802 /* flags */ 0, 2803 }, 2804 #endif /* chips */ 2805 2806 #if defined(BCM_56260_A0) 2807 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFO_BCM56260_A0fmt */ 2808 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2809 /* nFields */ 3, 2810 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFO_BCM56260_A0fmt_fields, 2811 /* bits */ 28, 2812 /* flags */ 0, 2813 }, 2814 #endif /* chips */ 2815 2816 #if defined(BCM_56260_B0) 2817 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFO_BCM56260_B0fmt */ 2818 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2819 /* nFields */ 3, 2820 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFO_BCM56260_A0fmt_fields, 2821 /* bits */ 28, 2822 /* flags */ 0, 2823 }, 2824 #endif /* chips */ 2825 2826 #if defined(BCM_56270_A0) 2827 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFO_BCM56270_A0fmt */ 2828 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2829 /* nFields */ 3, 2830 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFO_BCM56270_A0fmt_fields, 2831 /* bits */ 23, 2832 /* flags */ 0, 2833 }, 2834 #endif /* chips */ 2835 2836 #if defined(BCM_56440_B0) 2837 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFO_BCM56440_B0fmt */ 2838 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2839 /* nFields */ 3, 2840 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFOfmt_fields, 2841 /* bits */ 29, 2842 /* flags */ 0, 2843 }, 2844 #endif /* chips */ 2845 2846 #if defined(BCM_56450_A0) 2847 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFO_BCM56450_A0fmt */ 2848 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2849 /* nFields */ 3, 2850 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFO_BCM56450_A0fmt_fields, 2851 /* bits */ 29, 2852 /* flags */ 0, 2853 }, 2854 #endif /* chips */ 2855 2856 #if defined(BCM_56450_B0) 2857 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFO_BCM56450_B0fmt */ 2858 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2859 /* nFields */ 3, 2860 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFO_BCM56450_A0fmt_fields, 2861 /* bits */ 29, 2862 /* flags */ 0, 2863 }, 2864 #endif /* chips */ 2865 2866 #if defined(BCM_56450_B1) 2867 { /* SOC_FORMAT_INT_RQE_QMGR_TO_QID_PKT_INFO_BCM56450_B1fmt */ 2868 /* format RQE_QMGR_TO_QID_PKT_INFOfmt */ 2869 /* nFields */ 3, 2870 /* *fields */ soc_RQE_QMGR_TO_QID_PKT_INFO_BCM56450_A0fmt_fields, 2871 /* bits */ 29, 2872 /* flags */ 0, 2873 }, 2874 #endif /* chips */ 2875 2876 #if defined(BCM_56440_A0) 2877 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFOfmt */ 2878 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2879 /* nFields */ 2, 2880 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFOfmt_fields, 2881 /* bits */ 62, 2882 /* flags */ 0, 2883 }, 2884 #endif /* chips */ 2885 2886 #if defined(BCM_56260_A0) 2887 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFO_BCM56260_A0fmt */ 2888 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2889 /* nFields */ 2, 2890 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFO_BCM56260_A0fmt_fields, 2891 /* bits */ 59, 2892 /* flags */ 0, 2893 }, 2894 #endif /* chips */ 2895 2896 #if defined(BCM_56260_B0) 2897 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFO_BCM56260_B0fmt */ 2898 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2899 /* nFields */ 2, 2900 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFO_BCM56260_A0fmt_fields, 2901 /* bits */ 59, 2902 /* flags */ 0, 2903 }, 2904 #endif /* chips */ 2905 2906 #if defined(BCM_56270_A0) 2907 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFO_BCM56270_A0fmt */ 2908 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2909 /* nFields */ 2, 2910 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFO_BCM56270_A0fmt_fields, 2911 /* bits */ 48, 2912 /* flags */ 0, 2913 }, 2914 #endif /* chips */ 2915 2916 #if defined(BCM_56440_B0) 2917 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFO_BCM56440_B0fmt */ 2918 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2919 /* nFields */ 2, 2920 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFOfmt_fields, 2921 /* bits */ 62, 2922 /* flags */ 0, 2923 }, 2924 #endif /* chips */ 2925 2926 #if defined(BCM_56450_A0) 2927 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFO_BCM56450_A0fmt */ 2928 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2929 /* nFields */ 2, 2930 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFO_BCM56450_A0fmt_fields, 2931 /* bits */ 62, 2932 /* flags */ 0, 2933 }, 2934 #endif /* chips */ 2935 2936 #if defined(BCM_56450_B0) 2937 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFO_BCM56450_B0fmt */ 2938 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2939 /* nFields */ 2, 2940 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFO_BCM56450_A0fmt_fields, 2941 /* bits */ 62, 2942 /* flags */ 0, 2943 }, 2944 #endif /* chips */ 2945 2946 #if defined(BCM_56450_B1) 2947 { /* SOC_FORMAT_INT_RQE_QMGR_WR_FIFO_INFO_BCM56450_B1fmt */ 2948 /* format RQE_QMGR_WR_FIFO_INFOfmt */ 2949 /* nFields */ 2, 2950 /* *fields */ soc_RQE_QMGR_WR_FIFO_INFO_BCM56450_A0fmt_fields, 2951 /* bits */ 62, 2952 /* flags */ 0, 2953 }, 2954 #endif /* chips */ 2955 2956 #if defined(BCM_56440_A0) 2957 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFOfmt */ 2958 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 2959 /* nFields */ 2, 2960 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFOfmt_fields, 2961 /* bits */ 16, 2962 /* flags */ 0, 2963 }, 2964 #endif /* chips */ 2965 2966 #if defined(BCM_56260_A0) 2967 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFO_BCM56260_A0fmt */ 2968 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 2969 /* nFields */ 2, 2970 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFO_BCM56260_A0fmt_fields, 2971 /* bits */ 15, 2972 /* flags */ 0, 2973 }, 2974 #endif /* chips */ 2975 2976 #if defined(BCM_56260_B0) 2977 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFO_BCM56260_B0fmt */ 2978 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 2979 /* nFields */ 2, 2980 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFO_BCM56260_A0fmt_fields, 2981 /* bits */ 15, 2982 /* flags */ 0, 2983 }, 2984 #endif /* chips */ 2985 2986 #if defined(BCM_56270_A0) 2987 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFO_BCM56270_A0fmt */ 2988 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 2989 /* nFields */ 2, 2990 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFO_BCM56270_A0fmt_fields, 2991 /* bits */ 14, 2992 /* flags */ 0, 2993 }, 2994 #endif /* chips */ 2995 2996 #if defined(BCM_56440_B0) 2997 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFO_BCM56440_B0fmt */ 2998 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 2999 /* nFields */ 2, 3000 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFOfmt_fields, 3001 /* bits */ 16, 3002 /* flags */ 0, 3003 }, 3004 #endif /* chips */ 3005 3006 #if defined(BCM_56450_A0) 3007 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFO_BCM56450_A0fmt */ 3008 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 3009 /* nFields */ 2, 3010 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFO_BCM56450_A0fmt_fields, 3011 /* bits */ 16, 3012 /* flags */ 0, 3013 }, 3014 #endif /* chips */ 3015 3016 #if defined(BCM_56450_B0) 3017 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFO_BCM56450_B0fmt */ 3018 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 3019 /* nFields */ 2, 3020 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFO_BCM56450_A0fmt_fields, 3021 /* bits */ 16, 3022 /* flags */ 0, 3023 }, 3024 #endif /* chips */ 3025 3026 #if defined(BCM_56450_B1) 3027 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_QEN_INFO_BCM56450_B1fmt */ 3028 /* format RQE_TO_E2EFC_QEN_INFOfmt */ 3029 /* nFields */ 2, 3030 /* *fields */ soc_RQE_TO_E2EFC_QEN_INFO_BCM56450_A0fmt_fields, 3031 /* bits */ 16, 3032 /* flags */ 0, 3033 }, 3034 #endif /* chips */ 3035 3036 #if defined(BCM_56440_A0) 3037 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFOfmt */ 3038 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3039 /* nFields */ 1, 3040 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFOfmt_fields, 3041 /* bits */ 6, 3042 /* flags */ 0, 3043 }, 3044 #endif /* chips */ 3045 3046 #if defined(BCM_56260_A0) 3047 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFO_BCM56260_A0fmt */ 3048 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3049 /* nFields */ 1, 3050 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFO_BCM56260_A0fmt_fields, 3051 /* bits */ 5, 3052 /* flags */ 0, 3053 }, 3054 #endif /* chips */ 3055 3056 #if defined(BCM_56260_B0) 3057 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFO_BCM56260_B0fmt */ 3058 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3059 /* nFields */ 1, 3060 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFO_BCM56260_A0fmt_fields, 3061 /* bits */ 5, 3062 /* flags */ 0, 3063 }, 3064 #endif /* chips */ 3065 3066 #if defined(BCM_56270_A0) 3067 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFO_BCM56270_A0fmt */ 3068 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3069 /* nFields */ 1, 3070 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFO_BCM56260_A0fmt_fields, 3071 /* bits */ 5, 3072 /* flags */ 0, 3073 }, 3074 #endif /* chips */ 3075 3076 #if defined(BCM_56440_B0) 3077 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFO_BCM56440_B0fmt */ 3078 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3079 /* nFields */ 1, 3080 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFOfmt_fields, 3081 /* bits */ 6, 3082 /* flags */ 0, 3083 }, 3084 #endif /* chips */ 3085 3086 #if defined(BCM_56450_A0) 3087 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFO_BCM56450_A0fmt */ 3088 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3089 /* nFields */ 1, 3090 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFO_BCM56450_A0fmt_fields, 3091 /* bits */ 6, 3092 /* flags */ 0, 3093 }, 3094 #endif /* chips */ 3095 3096 #if defined(BCM_56450_B0) 3097 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFO_BCM56450_B0fmt */ 3098 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3099 /* nFields */ 1, 3100 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFO_BCM56450_A0fmt_fields, 3101 /* bits */ 6, 3102 /* flags */ 0, 3103 }, 3104 #endif /* chips */ 3105 3106 #if defined(BCM_56450_B1) 3107 { /* SOC_FORMAT_INT_RQE_TO_E2EFC_RQE_INFO_BCM56450_B1fmt */ 3108 /* format RQE_TO_E2EFC_RQE_INFOfmt */ 3109 /* nFields */ 1, 3110 /* *fields */ soc_RQE_TO_E2EFC_RQE_INFO_BCM56450_A0fmt_fields, 3111 /* bits */ 6, 3112 /* flags */ 0, 3113 }, 3114 #endif /* chips */ 3115 3116 #if defined(BCM_56440_A0) 3117 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFOfmt */ 3118 /* format RQE_TO_THDIQEN_INFOfmt */ 3119 /* nFields */ 3, 3120 /* *fields */ soc_RQE_TO_THDIQEN_INFOfmt_fields, 3121 /* bits */ 19, 3122 /* flags */ 0, 3123 }, 3124 #endif /* chips */ 3125 3126 #if defined(BCM_56260_A0) 3127 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFO_BCM56260_A0fmt */ 3128 /* format RQE_TO_THDIQEN_INFOfmt */ 3129 /* nFields */ 3, 3130 /* *fields */ soc_RQE_TO_THDIQEN_INFO_BCM56260_A0fmt_fields, 3131 /* bits */ 18, 3132 /* flags */ 0, 3133 }, 3134 #endif /* chips */ 3135 3136 #if defined(BCM_56260_B0) 3137 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFO_BCM56260_B0fmt */ 3138 /* format RQE_TO_THDIQEN_INFOfmt */ 3139 /* nFields */ 3, 3140 /* *fields */ soc_RQE_TO_THDIQEN_INFO_BCM56260_A0fmt_fields, 3141 /* bits */ 18, 3142 /* flags */ 0, 3143 }, 3144 #endif /* chips */ 3145 3146 #if defined(BCM_56270_A0) 3147 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFO_BCM56270_A0fmt */ 3148 /* format RQE_TO_THDIQEN_INFOfmt */ 3149 /* nFields */ 3, 3150 /* *fields */ soc_RQE_TO_THDIQEN_INFO_BCM56270_A0fmt_fields, 3151 /* bits */ 17, 3152 /* flags */ 0, 3153 }, 3154 #endif /* chips */ 3155 3156 #if defined(BCM_56440_B0) 3157 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFO_BCM56440_B0fmt */ 3158 /* format RQE_TO_THDIQEN_INFOfmt */ 3159 /* nFields */ 3, 3160 /* *fields */ soc_RQE_TO_THDIQEN_INFOfmt_fields, 3161 /* bits */ 19, 3162 /* flags */ 0, 3163 }, 3164 #endif /* chips */ 3165 3166 #if defined(BCM_56450_A0) 3167 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFO_BCM56450_A0fmt */ 3168 /* format RQE_TO_THDIQEN_INFOfmt */ 3169 /* nFields */ 3, 3170 /* *fields */ soc_RQE_TO_THDIQEN_INFO_BCM56450_A0fmt_fields, 3171 /* bits */ 19, 3172 /* flags */ 0, 3173 }, 3174 #endif /* chips */ 3175 3176 #if defined(BCM_56450_B0) 3177 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFO_BCM56450_B0fmt */ 3178 /* format RQE_TO_THDIQEN_INFOfmt */ 3179 /* nFields */ 3, 3180 /* *fields */ soc_RQE_TO_THDIQEN_INFO_BCM56450_A0fmt_fields, 3181 /* bits */ 19, 3182 /* flags */ 0, 3183 }, 3184 #endif /* chips */ 3185 3186 #if defined(BCM_56450_B1) 3187 { /* SOC_FORMAT_INT_RQE_TO_THDIQEN_INFO_BCM56450_B1fmt */ 3188 /* format RQE_TO_THDIQEN_INFOfmt */ 3189 /* nFields */ 3, 3190 /* *fields */ soc_RQE_TO_THDIQEN_INFO_BCM56450_A0fmt_fields, 3191 /* bits */ 19, 3192 /* flags */ 0, 3193 }, 3194 #endif /* chips */ 3195 3196 #if defined(BCM_56440_A0) 3197 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFOfmt */ 3198 /* format RQE_TO_THDIRQE_INFOfmt */ 3199 /* nFields */ 2, 3200 /* *fields */ soc_RQE_TO_THDIRQE_INFOfmt_fields, 3201 /* bits */ 9, 3202 /* flags */ 0, 3203 }, 3204 #endif /* chips */ 3205 3206 #if defined(BCM_56260_A0) 3207 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFO_BCM56260_A0fmt */ 3208 /* format RQE_TO_THDIRQE_INFOfmt */ 3209 /* nFields */ 2, 3210 /* *fields */ soc_RQE_TO_THDIRQE_INFO_BCM56260_A0fmt_fields, 3211 /* bits */ 8, 3212 /* flags */ 0, 3213 }, 3214 #endif /* chips */ 3215 3216 #if defined(BCM_56260_B0) 3217 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFO_BCM56260_B0fmt */ 3218 /* format RQE_TO_THDIRQE_INFOfmt */ 3219 /* nFields */ 2, 3220 /* *fields */ soc_RQE_TO_THDIRQE_INFO_BCM56260_A0fmt_fields, 3221 /* bits */ 8, 3222 /* flags */ 0, 3223 }, 3224 #endif /* chips */ 3225 3226 #if defined(BCM_56270_A0) 3227 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFO_BCM56270_A0fmt */ 3228 /* format RQE_TO_THDIRQE_INFOfmt */ 3229 /* nFields */ 2, 3230 /* *fields */ soc_RQE_TO_THDIRQE_INFO_BCM56270_A0fmt_fields, 3231 /* bits */ 7, 3232 /* flags */ 0, 3233 }, 3234 #endif /* chips */ 3235 3236 #if defined(BCM_56440_B0) 3237 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFO_BCM56440_B0fmt */ 3238 /* format RQE_TO_THDIRQE_INFOfmt */ 3239 /* nFields */ 2, 3240 /* *fields */ soc_RQE_TO_THDIRQE_INFOfmt_fields, 3241 /* bits */ 9, 3242 /* flags */ 0, 3243 }, 3244 #endif /* chips */ 3245 3246 #if defined(BCM_56450_A0) 3247 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFO_BCM56450_A0fmt */ 3248 /* format RQE_TO_THDIRQE_INFOfmt */ 3249 /* nFields */ 2, 3250 /* *fields */ soc_RQE_TO_THDIRQE_INFO_BCM56450_A0fmt_fields, 3251 /* bits */ 9, 3252 /* flags */ 0, 3253 }, 3254 #endif /* chips */ 3255 3256 #if defined(BCM_56450_B0) 3257 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFO_BCM56450_B0fmt */ 3258 /* format RQE_TO_THDIRQE_INFOfmt */ 3259 /* nFields */ 2, 3260 /* *fields */ soc_RQE_TO_THDIRQE_INFO_BCM56450_A0fmt_fields, 3261 /* bits */ 9, 3262 /* flags */ 0, 3263 }, 3264 #endif /* chips */ 3265 3266 #if defined(BCM_56450_B1) 3267 { /* SOC_FORMAT_INT_RQE_TO_THDIRQE_INFO_BCM56450_B1fmt */ 3268 /* format RQE_TO_THDIRQE_INFOfmt */ 3269 /* nFields */ 2, 3270 /* *fields */ soc_RQE_TO_THDIRQE_INFO_BCM56450_A0fmt_fields, 3271 /* bits */ 9, 3272 /* flags */ 0, 3273 }, 3274 #endif /* chips */ 3275 3276 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 3277 { /* SOC_FORMAT_INT_RQE_TO_THDMfmt */ 3278 /* format RQE_TO_THDMfmt */ 3279 /* nFields */ 6, 3280 /* *fields */ soc_RQE_TO_THDMfmt_fields, 3281 /* bits */ 45, 3282 /* flags */ 0, 3283 }, 3284 #endif /* chips */ 3285 3286 #if defined(BCM_56370_A0) 3287 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56370_A0fmt */ 3288 /* format RQE_TO_THDMfmt */ 3289 /* nFields */ 7, 3290 /* *fields */ soc_RQE_TO_THDM_BCM56370_A0fmt_fields, 3291 /* bits */ 45, 3292 /* flags */ 0, 3293 }, 3294 #endif /* chips */ 3295 3296 #if defined(BCM_56560_A0) 3297 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56560_A0fmt */ 3298 /* format RQE_TO_THDMfmt */ 3299 /* nFields */ 6, 3300 /* *fields */ soc_RQE_TO_THDM_BCM56560_A0fmt_fields, 3301 /* bits */ 49, 3302 /* flags */ 0, 3303 }, 3304 #endif /* chips */ 3305 3306 #if defined(BCM_56560_B0) 3307 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56560_B0fmt */ 3308 /* format RQE_TO_THDMfmt */ 3309 /* nFields */ 6, 3310 /* *fields */ soc_RQE_TO_THDM_BCM56560_A0fmt_fields, 3311 /* bits */ 49, 3312 /* flags */ 0, 3313 }, 3314 #endif /* chips */ 3315 3316 #if defined(BCM_56670_A0) 3317 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56670_A0fmt */ 3318 /* format RQE_TO_THDMfmt */ 3319 /* nFields */ 6, 3320 /* *fields */ soc_RQE_TO_THDM_BCM56670_A0fmt_fields, 3321 /* bits */ 43, 3322 /* flags */ 0, 3323 }, 3324 #endif /* chips */ 3325 3326 #if defined(BCM_56670_B0) 3327 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56670_B0fmt */ 3328 /* format RQE_TO_THDMfmt */ 3329 /* nFields */ 6, 3330 /* *fields */ soc_RQE_TO_THDM_BCM56670_A0fmt_fields, 3331 /* bits */ 43, 3332 /* flags */ 0, 3333 }, 3334 #endif /* chips */ 3335 3336 #if defined(BCM_56770_A0) 3337 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56770_A0fmt */ 3338 /* format RQE_TO_THDMfmt */ 3339 /* nFields */ 7, 3340 /* *fields */ soc_RQE_TO_THDM_BCM56870_A0fmt_fields, 3341 /* bits */ 48, 3342 /* flags */ 0, 3343 }, 3344 #endif /* chips */ 3345 3346 #if defined(BCM_56870_A0) 3347 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56870_A0fmt */ 3348 /* format RQE_TO_THDMfmt */ 3349 /* nFields */ 7, 3350 /* *fields */ soc_RQE_TO_THDM_BCM56870_A0fmt_fields, 3351 /* bits */ 48, 3352 /* flags */ 0, 3353 }, 3354 #endif /* chips */ 3355 3356 #if defined(BCM_56960_A0) 3357 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56960_A0fmt */ 3358 /* format RQE_TO_THDMfmt */ 3359 /* nFields */ 7, 3360 /* *fields */ soc_RQE_TO_THDM_BCM56960_A0fmt_fields, 3361 /* bits */ 43, 3362 /* flags */ 0, 3363 }, 3364 #endif /* chips */ 3365 3366 #if defined(BCM_56965_A0) 3367 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56965_A0fmt */ 3368 /* format RQE_TO_THDMfmt */ 3369 /* nFields */ 7, 3370 /* *fields */ soc_RQE_TO_THDM_BCM56960_A0fmt_fields, 3371 /* bits */ 43, 3372 /* flags */ 0, 3373 }, 3374 #endif /* chips */ 3375 3376 #if defined(BCM_56970_A0) 3377 { /* SOC_FORMAT_INT_RQE_TO_THDM_BCM56970_A0fmt */ 3378 /* format RQE_TO_THDMfmt */ 3379 /* nFields */ 7, 3380 /* *fields */ soc_RQE_TO_THDM_BCM56970_A0fmt_fields, 3381 /* bits */ 44, 3382 /* flags */ 0, 3383 }, 3384 #endif /* chips */ 3385 3386 #if defined(BCM_56440_A0) 3387 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFOfmt */ 3388 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3389 /* nFields */ 5, 3390 /* *fields */ soc_RQE_TO_THDO_DEQ_INFOfmt_fields, 3391 /* bits */ 5, 3392 /* flags */ 0, 3393 }, 3394 #endif /* chips */ 3395 3396 #if defined(BCM_56260_A0) 3397 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFO_BCM56260_A0fmt */ 3398 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3399 /* nFields */ 10, 3400 /* *fields */ soc_RQE_TO_THDO_DEQ_INFO_BCM56260_A0fmt_fields, 3401 /* bits */ 10, 3402 /* flags */ 0, 3403 }, 3404 #endif /* chips */ 3405 3406 #if defined(BCM_56260_B0) 3407 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFO_BCM56260_B0fmt */ 3408 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3409 /* nFields */ 10, 3410 /* *fields */ soc_RQE_TO_THDO_DEQ_INFO_BCM56260_A0fmt_fields, 3411 /* bits */ 10, 3412 /* flags */ 0, 3413 }, 3414 #endif /* chips */ 3415 3416 #if defined(BCM_56270_A0) 3417 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFO_BCM56270_A0fmt */ 3418 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3419 /* nFields */ 7, 3420 /* *fields */ soc_RQE_TO_THDO_DEQ_INFO_BCM56270_A0fmt_fields, 3421 /* bits */ 7, 3422 /* flags */ 0, 3423 }, 3424 #endif /* chips */ 3425 3426 #if defined(BCM_56440_B0) 3427 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFO_BCM56440_B0fmt */ 3428 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3429 /* nFields */ 5, 3430 /* *fields */ soc_RQE_TO_THDO_DEQ_INFOfmt_fields, 3431 /* bits */ 5, 3432 /* flags */ 0, 3433 }, 3434 #endif /* chips */ 3435 3436 #if defined(BCM_56450_A0) 3437 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFO_BCM56450_A0fmt */ 3438 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3439 /* nFields */ 10, 3440 /* *fields */ soc_RQE_TO_THDO_DEQ_INFO_BCM56450_A0fmt_fields, 3441 /* bits */ 10, 3442 /* flags */ 0, 3443 }, 3444 #endif /* chips */ 3445 3446 #if defined(BCM_56450_B0) 3447 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFO_BCM56450_B0fmt */ 3448 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3449 /* nFields */ 10, 3450 /* *fields */ soc_RQE_TO_THDO_DEQ_INFO_BCM56450_A0fmt_fields, 3451 /* bits */ 10, 3452 /* flags */ 0, 3453 }, 3454 #endif /* chips */ 3455 3456 #if defined(BCM_56450_B1) 3457 { /* SOC_FORMAT_INT_RQE_TO_THDO_DEQ_INFO_BCM56450_B1fmt */ 3458 /* format RQE_TO_THDO_DEQ_INFOfmt */ 3459 /* nFields */ 10, 3460 /* *fields */ soc_RQE_TO_THDO_DEQ_INFO_BCM56450_A0fmt_fields, 3461 /* bits */ 10, 3462 /* flags */ 0, 3463 }, 3464 #endif /* chips */ 3465 3466 #if defined(BCM_56440_A0) 3467 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFOfmt */ 3468 /* format RQE_TO_THDO_INFOfmt */ 3469 /* nFields */ 7, 3470 /* *fields */ soc_RQE_TO_THDO_INFOfmt_fields, 3471 /* bits */ 166, 3472 /* flags */ 0, 3473 }, 3474 #endif /* chips */ 3475 3476 #if defined(BCM_56260_A0) 3477 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFO_BCM56260_A0fmt */ 3478 /* format RQE_TO_THDO_INFOfmt */ 3479 /* nFields */ 5, 3480 /* *fields */ soc_RQE_TO_THDO_INFO_BCM56260_A0fmt_fields, 3481 /* bits */ 112, 3482 /* flags */ 0, 3483 }, 3484 #endif /* chips */ 3485 3486 #if defined(BCM_56260_B0) 3487 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFO_BCM56260_B0fmt */ 3488 /* format RQE_TO_THDO_INFOfmt */ 3489 /* nFields */ 5, 3490 /* *fields */ soc_RQE_TO_THDO_INFO_BCM56260_A0fmt_fields, 3491 /* bits */ 112, 3492 /* flags */ 0, 3493 }, 3494 #endif /* chips */ 3495 3496 #if defined(BCM_56270_A0) 3497 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFO_BCM56270_A0fmt */ 3498 /* format RQE_TO_THDO_INFOfmt */ 3499 /* nFields */ 5, 3500 /* *fields */ soc_RQE_TO_THDO_INFO_BCM56270_A0fmt_fields, 3501 /* bits */ 102, 3502 /* flags */ 0, 3503 }, 3504 #endif /* chips */ 3505 3506 #if defined(BCM_56440_B0) 3507 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFO_BCM56440_B0fmt */ 3508 /* format RQE_TO_THDO_INFOfmt */ 3509 /* nFields */ 7, 3510 /* *fields */ soc_RQE_TO_THDO_INFOfmt_fields, 3511 /* bits */ 166, 3512 /* flags */ 0, 3513 }, 3514 #endif /* chips */ 3515 3516 #if defined(BCM_56450_A0) 3517 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFO_BCM56450_A0fmt */ 3518 /* format RQE_TO_THDO_INFOfmt */ 3519 /* nFields */ 7, 3520 /* *fields */ soc_RQE_TO_THDO_INFO_BCM56450_A0fmt_fields, 3521 /* bits */ 189, 3522 /* flags */ 0, 3523 }, 3524 #endif /* chips */ 3525 3526 #if defined(BCM_56450_B0) 3527 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFO_BCM56450_B0fmt */ 3528 /* format RQE_TO_THDO_INFOfmt */ 3529 /* nFields */ 7, 3530 /* *fields */ soc_RQE_TO_THDO_INFO_BCM56450_A0fmt_fields, 3531 /* bits */ 189, 3532 /* flags */ 0, 3533 }, 3534 #endif /* chips */ 3535 3536 #if defined(BCM_56450_B1) 3537 { /* SOC_FORMAT_INT_RQE_TO_THDO_INFO_BCM56450_B1fmt */ 3538 /* format RQE_TO_THDO_INFOfmt */ 3539 /* nFields */ 7, 3540 /* *fields */ soc_RQE_TO_THDO_INFO_BCM56450_A0fmt_fields, 3541 /* bits */ 189, 3542 /* flags */ 0, 3543 }, 3544 #endif /* chips */ 3545 3546 #if defined(BCM_56440_A0) 3547 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFOfmt */ 3548 /* format RQE_TO_THDO_LANE_INFOfmt */ 3549 /* nFields */ 6, 3550 /* *fields */ soc_RQE_TO_THDO_LANE_INFOfmt_fields, 3551 /* bits */ 31, 3552 /* flags */ 0, 3553 }, 3554 #endif /* chips */ 3555 3556 #if defined(BCM_56260_A0) 3557 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFO_BCM56260_A0fmt */ 3558 /* format RQE_TO_THDO_LANE_INFOfmt */ 3559 /* nFields */ 7, 3560 /* *fields */ soc_RQE_TO_THDO_LANE_INFO_BCM56260_A0fmt_fields, 3561 /* bits */ 29, 3562 /* flags */ 0, 3563 }, 3564 #endif /* chips */ 3565 3566 #if defined(BCM_56260_B0) 3567 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFO_BCM56260_B0fmt */ 3568 /* format RQE_TO_THDO_LANE_INFOfmt */ 3569 /* nFields */ 7, 3570 /* *fields */ soc_RQE_TO_THDO_LANE_INFO_BCM56260_A0fmt_fields, 3571 /* bits */ 29, 3572 /* flags */ 0, 3573 }, 3574 #endif /* chips */ 3575 3576 #if defined(BCM_56270_A0) 3577 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFO_BCM56270_A0fmt */ 3578 /* format RQE_TO_THDO_LANE_INFOfmt */ 3579 /* nFields */ 6, 3580 /* *fields */ soc_RQE_TO_THDO_LANE_INFO_BCM56270_A0fmt_fields, 3581 /* bits */ 26, 3582 /* flags */ 0, 3583 }, 3584 #endif /* chips */ 3585 3586 #if defined(BCM_56440_B0) 3587 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFO_BCM56440_B0fmt */ 3588 /* format RQE_TO_THDO_LANE_INFOfmt */ 3589 /* nFields */ 6, 3590 /* *fields */ soc_RQE_TO_THDO_LANE_INFOfmt_fields, 3591 /* bits */ 31, 3592 /* flags */ 0, 3593 }, 3594 #endif /* chips */ 3595 3596 #if defined(BCM_56450_A0) 3597 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFO_BCM56450_A0fmt */ 3598 /* format RQE_TO_THDO_LANE_INFOfmt */ 3599 /* nFields */ 7, 3600 /* *fields */ soc_RQE_TO_THDO_LANE_INFO_BCM56450_A0fmt_fields, 3601 /* bits */ 33, 3602 /* flags */ 0, 3603 }, 3604 #endif /* chips */ 3605 3606 #if defined(BCM_56450_B0) 3607 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFO_BCM56450_B0fmt */ 3608 /* format RQE_TO_THDO_LANE_INFOfmt */ 3609 /* nFields */ 7, 3610 /* *fields */ soc_RQE_TO_THDO_LANE_INFO_BCM56450_A0fmt_fields, 3611 /* bits */ 33, 3612 /* flags */ 0, 3613 }, 3614 #endif /* chips */ 3615 3616 #if defined(BCM_56450_B1) 3617 { /* SOC_FORMAT_INT_RQE_TO_THDO_LANE_INFO_BCM56450_B1fmt */ 3618 /* format RQE_TO_THDO_LANE_INFOfmt */ 3619 /* nFields */ 7, 3620 /* *fields */ soc_RQE_TO_THDO_LANE_INFO_BCM56450_A0fmt_fields, 3621 /* bits */ 33, 3622 /* flags */ 0, 3623 }, 3624 #endif /* chips */ 3625 3626 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 3627 defined(BCM_56450_B1) 3628 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEE_INFOfmt */ 3629 /* format RQE_TO_THDO_RDEE_INFOfmt */ 3630 /* nFields */ 3, 3631 /* *fields */ soc_RQE_TO_THDO_RDEE_INFOfmt_fields, 3632 /* bits */ 5, 3633 /* flags */ 0, 3634 }, 3635 #endif /* chips */ 3636 3637 #if defined(BCM_56260_A0) 3638 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEE_INFO_BCM56260_A0fmt */ 3639 /* format RQE_TO_THDO_RDEE_INFOfmt */ 3640 /* nFields */ 3, 3641 /* *fields */ soc_RQE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 3642 /* bits */ 5, 3643 /* flags */ 0, 3644 }, 3645 #endif /* chips */ 3646 3647 #if defined(BCM_56260_B0) 3648 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEE_INFO_BCM56260_B0fmt */ 3649 /* format RQE_TO_THDO_RDEE_INFOfmt */ 3650 /* nFields */ 3, 3651 /* *fields */ soc_RQE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 3652 /* bits */ 5, 3653 /* flags */ 0, 3654 }, 3655 #endif /* chips */ 3656 3657 #if defined(BCM_56450_A0) 3658 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEI_INFOfmt */ 3659 /* format RQE_TO_THDO_RDEI_INFOfmt */ 3660 /* nFields */ 3, 3661 /* *fields */ soc_RQE_TO_THDO_RDEE_INFOfmt_fields, 3662 /* bits */ 5, 3663 /* flags */ 0, 3664 }, 3665 #endif /* chips */ 3666 3667 #if defined(BCM_56260_A0) 3668 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEI_INFO_BCM56260_A0fmt */ 3669 /* format RQE_TO_THDO_RDEI_INFOfmt */ 3670 /* nFields */ 3, 3671 /* *fields */ soc_RQE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 3672 /* bits */ 5, 3673 /* flags */ 0, 3674 }, 3675 #endif /* chips */ 3676 3677 #if defined(BCM_56260_B0) 3678 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEI_INFO_BCM56260_B0fmt */ 3679 /* format RQE_TO_THDO_RDEI_INFOfmt */ 3680 /* nFields */ 3, 3681 /* *fields */ soc_RQE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 3682 /* bits */ 5, 3683 /* flags */ 0, 3684 }, 3685 #endif /* chips */ 3686 3687 #if defined(BCM_56270_A0) 3688 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEI_INFO_BCM56270_A0fmt */ 3689 /* format RQE_TO_THDO_RDEI_INFOfmt */ 3690 /* nFields */ 3, 3691 /* *fields */ soc_RQE_TO_THDO_RDEE_INFO_BCM56260_A0fmt_fields, 3692 /* bits */ 5, 3693 /* flags */ 0, 3694 }, 3695 #endif /* chips */ 3696 3697 #if defined(BCM_56450_B0) 3698 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEI_INFO_BCM56450_B0fmt */ 3699 /* format RQE_TO_THDO_RDEI_INFOfmt */ 3700 /* nFields */ 3, 3701 /* *fields */ soc_RQE_TO_THDO_RDEE_INFOfmt_fields, 3702 /* bits */ 5, 3703 /* flags */ 0, 3704 }, 3705 #endif /* chips */ 3706 3707 #if defined(BCM_56450_B1) 3708 { /* SOC_FORMAT_INT_RQE_TO_THDO_RDEI_INFO_BCM56450_B1fmt */ 3709 /* format RQE_TO_THDO_RDEI_INFOfmt */ 3710 /* nFields */ 3, 3711 /* *fields */ soc_RQE_TO_THDO_RDEE_INFOfmt_fields, 3712 /* bits */ 5, 3713 /* flags */ 0, 3714 }, 3715 #endif /* chips */ 3716 3717 #if defined(BCM_56440_A0) 3718 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFOfmt */ 3719 /* format RQE_TO_THDO_REPL_INFOfmt */ 3720 /* nFields */ 9, 3721 /* *fields */ soc_RQE_TO_THDO_REPL_INFOfmt_fields, 3722 /* bits */ 24, 3723 /* flags */ 0, 3724 }, 3725 #endif /* chips */ 3726 3727 #if defined(BCM_56260_A0) 3728 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFO_BCM56260_A0fmt */ 3729 /* format RQE_TO_THDO_REPL_INFOfmt */ 3730 /* nFields */ 9, 3731 /* *fields */ soc_RQE_TO_THDO_REPL_INFO_BCM56260_A0fmt_fields, 3732 /* bits */ 24, 3733 /* flags */ 0, 3734 }, 3735 #endif /* chips */ 3736 3737 #if defined(BCM_56260_B0) 3738 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFO_BCM56260_B0fmt */ 3739 /* format RQE_TO_THDO_REPL_INFOfmt */ 3740 /* nFields */ 9, 3741 /* *fields */ soc_RQE_TO_THDO_REPL_INFO_BCM56260_A0fmt_fields, 3742 /* bits */ 24, 3743 /* flags */ 0, 3744 }, 3745 #endif /* chips */ 3746 3747 #if defined(BCM_56270_A0) 3748 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFO_BCM56270_A0fmt */ 3749 /* format RQE_TO_THDO_REPL_INFOfmt */ 3750 /* nFields */ 8, 3751 /* *fields */ soc_RQE_TO_THDO_REPL_INFO_BCM56270_A0fmt_fields, 3752 /* bits */ 23, 3753 /* flags */ 0, 3754 }, 3755 #endif /* chips */ 3756 3757 #if defined(BCM_56440_B0) 3758 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFO_BCM56440_B0fmt */ 3759 /* format RQE_TO_THDO_REPL_INFOfmt */ 3760 /* nFields */ 9, 3761 /* *fields */ soc_RQE_TO_THDO_REPL_INFOfmt_fields, 3762 /* bits */ 24, 3763 /* flags */ 0, 3764 }, 3765 #endif /* chips */ 3766 3767 #if defined(BCM_56450_A0) 3768 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFO_BCM56450_A0fmt */ 3769 /* format RQE_TO_THDO_REPL_INFOfmt */ 3770 /* nFields */ 9, 3771 /* *fields */ soc_RQE_TO_THDO_REPL_INFO_BCM56450_A0fmt_fields, 3772 /* bits */ 24, 3773 /* flags */ 0, 3774 }, 3775 #endif /* chips */ 3776 3777 #if defined(BCM_56450_B0) 3778 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFO_BCM56450_B0fmt */ 3779 /* format RQE_TO_THDO_REPL_INFOfmt */ 3780 /* nFields */ 9, 3781 /* *fields */ soc_RQE_TO_THDO_REPL_INFO_BCM56450_A0fmt_fields, 3782 /* bits */ 24, 3783 /* flags */ 0, 3784 }, 3785 #endif /* chips */ 3786 3787 #if defined(BCM_56450_B1) 3788 { /* SOC_FORMAT_INT_RQE_TO_THDO_REPL_INFO_BCM56450_B1fmt */ 3789 /* format RQE_TO_THDO_REPL_INFOfmt */ 3790 /* nFields */ 9, 3791 /* *fields */ soc_RQE_TO_THDO_REPL_INFO_BCM56450_A0fmt_fields, 3792 /* bits */ 24, 3793 /* flags */ 0, 3794 }, 3795 #endif /* chips */ 3796 3797 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 3798 defined(BCM_56450_B1) 3799 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_DEQ_INFOfmt */ 3800 /* format RQE_TO_THDO_RQEE_DEQ_INFOfmt */ 3801 /* nFields */ 3, 3802 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFOfmt_fields, 3803 /* bits */ 6, 3804 /* flags */ 0, 3805 }, 3806 #endif /* chips */ 3807 3808 #if defined(BCM_56260_A0) 3809 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt */ 3810 /* format RQE_TO_THDO_RQEE_DEQ_INFOfmt */ 3811 /* nFields */ 3, 3812 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 3813 /* bits */ 6, 3814 /* flags */ 0, 3815 }, 3816 #endif /* chips */ 3817 3818 #if defined(BCM_56260_B0) 3819 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_B0fmt */ 3820 /* format RQE_TO_THDO_RQEE_DEQ_INFOfmt */ 3821 /* nFields */ 3, 3822 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 3823 /* bits */ 6, 3824 /* flags */ 0, 3825 }, 3826 #endif /* chips */ 3827 3828 #if defined(BCM_56440_A0) 3829 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_INFOfmt */ 3830 /* format RQE_TO_THDO_RQEE_INFOfmt */ 3831 /* nFields */ 5, 3832 /* *fields */ soc_RQE_TO_THDO_RQEE_INFOfmt_fields, 3833 /* bits */ 14, 3834 /* flags */ 0, 3835 }, 3836 #endif /* chips */ 3837 3838 #if defined(BCM_56260_A0) 3839 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_INFO_BCM56260_A0fmt */ 3840 /* format RQE_TO_THDO_RQEE_INFOfmt */ 3841 /* nFields */ 5, 3842 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 3843 /* bits */ 14, 3844 /* flags */ 0, 3845 }, 3846 #endif /* chips */ 3847 3848 #if defined(BCM_56260_B0) 3849 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_INFO_BCM56260_B0fmt */ 3850 /* format RQE_TO_THDO_RQEE_INFOfmt */ 3851 /* nFields */ 5, 3852 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 3853 /* bits */ 14, 3854 /* flags */ 0, 3855 }, 3856 #endif /* chips */ 3857 3858 #if defined(BCM_56440_B0) 3859 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_INFO_BCM56440_B0fmt */ 3860 /* format RQE_TO_THDO_RQEE_INFOfmt */ 3861 /* nFields */ 5, 3862 /* *fields */ soc_RQE_TO_THDO_RQEE_INFOfmt_fields, 3863 /* bits */ 14, 3864 /* flags */ 0, 3865 }, 3866 #endif /* chips */ 3867 3868 #if defined(BCM_56450_A0) 3869 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_INFO_BCM56450_A0fmt */ 3870 /* format RQE_TO_THDO_RQEE_INFOfmt */ 3871 /* nFields */ 5, 3872 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 3873 /* bits */ 14, 3874 /* flags */ 0, 3875 }, 3876 #endif /* chips */ 3877 3878 #if defined(BCM_56450_B0) 3879 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_INFO_BCM56450_B0fmt */ 3880 /* format RQE_TO_THDO_RQEE_INFOfmt */ 3881 /* nFields */ 5, 3882 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 3883 /* bits */ 14, 3884 /* flags */ 0, 3885 }, 3886 #endif /* chips */ 3887 3888 #if defined(BCM_56450_B1) 3889 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEE_INFO_BCM56450_B1fmt */ 3890 /* format RQE_TO_THDO_RQEE_INFOfmt */ 3891 /* nFields */ 5, 3892 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 3893 /* bits */ 14, 3894 /* flags */ 0, 3895 }, 3896 #endif /* chips */ 3897 3898 #if defined(BCM_56450_A0) 3899 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_DEQ_INFOfmt */ 3900 /* format RQE_TO_THDO_RQEI_DEQ_INFOfmt */ 3901 /* nFields */ 3, 3902 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFOfmt_fields, 3903 /* bits */ 6, 3904 /* flags */ 0, 3905 }, 3906 #endif /* chips */ 3907 3908 #if defined(BCM_56260_A0) 3909 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_DEQ_INFO_BCM56260_A0fmt */ 3910 /* format RQE_TO_THDO_RQEI_DEQ_INFOfmt */ 3911 /* nFields */ 3, 3912 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 3913 /* bits */ 6, 3914 /* flags */ 0, 3915 }, 3916 #endif /* chips */ 3917 3918 #if defined(BCM_56260_B0) 3919 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_DEQ_INFO_BCM56260_B0fmt */ 3920 /* format RQE_TO_THDO_RQEI_DEQ_INFOfmt */ 3921 /* nFields */ 3, 3922 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 3923 /* bits */ 6, 3924 /* flags */ 0, 3925 }, 3926 #endif /* chips */ 3927 3928 #if defined(BCM_56270_A0) 3929 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_DEQ_INFO_BCM56270_A0fmt */ 3930 /* format RQE_TO_THDO_RQEI_DEQ_INFOfmt */ 3931 /* nFields */ 3, 3932 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 3933 /* bits */ 6, 3934 /* flags */ 0, 3935 }, 3936 #endif /* chips */ 3937 3938 #if defined(BCM_56450_B0) 3939 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_DEQ_INFO_BCM56450_B0fmt */ 3940 /* format RQE_TO_THDO_RQEI_DEQ_INFOfmt */ 3941 /* nFields */ 3, 3942 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFOfmt_fields, 3943 /* bits */ 6, 3944 /* flags */ 0, 3945 }, 3946 #endif /* chips */ 3947 3948 #if defined(BCM_56450_B1) 3949 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_DEQ_INFO_BCM56450_B1fmt */ 3950 /* format RQE_TO_THDO_RQEI_DEQ_INFOfmt */ 3951 /* nFields */ 3, 3952 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFOfmt_fields, 3953 /* bits */ 6, 3954 /* flags */ 0, 3955 }, 3956 #endif /* chips */ 3957 3958 #if defined(BCM_56440_A0) 3959 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFOfmt */ 3960 /* format RQE_TO_THDO_RQEI_INFOfmt */ 3961 /* nFields */ 5, 3962 /* *fields */ soc_RQE_TO_THDO_RQEE_INFOfmt_fields, 3963 /* bits */ 14, 3964 /* flags */ 0, 3965 }, 3966 #endif /* chips */ 3967 3968 #if defined(BCM_56260_A0) 3969 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFO_BCM56260_A0fmt */ 3970 /* format RQE_TO_THDO_RQEI_INFOfmt */ 3971 /* nFields */ 5, 3972 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 3973 /* bits */ 14, 3974 /* flags */ 0, 3975 }, 3976 #endif /* chips */ 3977 3978 #if defined(BCM_56260_B0) 3979 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFO_BCM56260_B0fmt */ 3980 /* format RQE_TO_THDO_RQEI_INFOfmt */ 3981 /* nFields */ 5, 3982 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 3983 /* bits */ 14, 3984 /* flags */ 0, 3985 }, 3986 #endif /* chips */ 3987 3988 #if defined(BCM_56270_A0) 3989 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFO_BCM56270_A0fmt */ 3990 /* format RQE_TO_THDO_RQEI_INFOfmt */ 3991 /* nFields */ 5, 3992 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 3993 /* bits */ 14, 3994 /* flags */ 0, 3995 }, 3996 #endif /* chips */ 3997 3998 #if defined(BCM_56440_B0) 3999 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFO_BCM56440_B0fmt */ 4000 /* format RQE_TO_THDO_RQEI_INFOfmt */ 4001 /* nFields */ 5, 4002 /* *fields */ soc_RQE_TO_THDO_RQEE_INFOfmt_fields, 4003 /* bits */ 14, 4004 /* flags */ 0, 4005 }, 4006 #endif /* chips */ 4007 4008 #if defined(BCM_56450_A0) 4009 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFO_BCM56450_A0fmt */ 4010 /* format RQE_TO_THDO_RQEI_INFOfmt */ 4011 /* nFields */ 5, 4012 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 4013 /* bits */ 14, 4014 /* flags */ 0, 4015 }, 4016 #endif /* chips */ 4017 4018 #if defined(BCM_56450_B0) 4019 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFO_BCM56450_B0fmt */ 4020 /* format RQE_TO_THDO_RQEI_INFOfmt */ 4021 /* nFields */ 5, 4022 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 4023 /* bits */ 14, 4024 /* flags */ 0, 4025 }, 4026 #endif /* chips */ 4027 4028 #if defined(BCM_56450_B1) 4029 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEI_INFO_BCM56450_B1fmt */ 4030 /* format RQE_TO_THDO_RQEI_INFOfmt */ 4031 /* nFields */ 5, 4032 /* *fields */ soc_RQE_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 4033 /* bits */ 14, 4034 /* flags */ 0, 4035 }, 4036 #endif /* chips */ 4037 4038 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 4039 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEQ_INFOfmt */ 4040 /* format RQE_TO_THDO_RQEQ_INFOfmt */ 4041 /* nFields */ 3, 4042 /* *fields */ soc_RQE_TO_THDO_RQEQ_INFOfmt_fields, 4043 /* bits */ 6, 4044 /* flags */ 0, 4045 }, 4046 #endif /* chips */ 4047 4048 #if defined(BCM_56260_A0) 4049 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEQ_INFO_BCM56260_A0fmt */ 4050 /* format RQE_TO_THDO_RQEQ_INFOfmt */ 4051 /* nFields */ 3, 4052 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 4053 /* bits */ 6, 4054 /* flags */ 0, 4055 }, 4056 #endif /* chips */ 4057 4058 #if defined(BCM_56260_B0) 4059 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEQ_INFO_BCM56260_B0fmt */ 4060 /* format RQE_TO_THDO_RQEQ_INFOfmt */ 4061 /* nFields */ 3, 4062 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 4063 /* bits */ 6, 4064 /* flags */ 0, 4065 }, 4066 #endif /* chips */ 4067 4068 #if defined(BCM_56270_A0) 4069 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEQ_INFO_BCM56270_A0fmt */ 4070 /* format RQE_TO_THDO_RQEQ_INFOfmt */ 4071 /* nFields */ 3, 4072 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFO_BCM56260_A0fmt_fields, 4073 /* bits */ 6, 4074 /* flags */ 0, 4075 }, 4076 #endif /* chips */ 4077 4078 #if defined(BCM_56450_A0) 4079 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEQ_INFO_BCM56450_A0fmt */ 4080 /* format RQE_TO_THDO_RQEQ_INFOfmt */ 4081 /* nFields */ 3, 4082 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFOfmt_fields, 4083 /* bits */ 6, 4084 /* flags */ 0, 4085 }, 4086 #endif /* chips */ 4087 4088 #if defined(BCM_56450_B0) 4089 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEQ_INFO_BCM56450_B0fmt */ 4090 /* format RQE_TO_THDO_RQEQ_INFOfmt */ 4091 /* nFields */ 3, 4092 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFOfmt_fields, 4093 /* bits */ 6, 4094 /* flags */ 0, 4095 }, 4096 #endif /* chips */ 4097 4098 #if defined(BCM_56450_B1) 4099 { /* SOC_FORMAT_INT_RQE_TO_THDO_RQEQ_INFO_BCM56450_B1fmt */ 4100 /* format RQE_TO_THDO_RQEQ_INFOfmt */ 4101 /* nFields */ 3, 4102 /* *fields */ soc_RQE_TO_THDO_RQEE_DEQ_INFOfmt_fields, 4103 /* bits */ 6, 4104 /* flags */ 0, 4105 }, 4106 #endif /* chips */ 4107 4108 #if defined(BCM_56440_A0) 4109 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFOfmt */ 4110 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4111 /* nFields */ 6, 4112 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFOfmt_fields, 4113 /* bits */ 13, 4114 /* flags */ 0, 4115 }, 4116 #endif /* chips */ 4117 4118 #if defined(BCM_56260_A0) 4119 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFO_BCM56260_A0fmt */ 4120 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4121 /* nFields */ 7, 4122 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFO_BCM56260_A0fmt_fields, 4123 /* bits */ 20, 4124 /* flags */ 0, 4125 }, 4126 #endif /* chips */ 4127 4128 #if defined(BCM_56260_B0) 4129 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFO_BCM56260_B0fmt */ 4130 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4131 /* nFields */ 7, 4132 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFO_BCM56260_A0fmt_fields, 4133 /* bits */ 20, 4134 /* flags */ 0, 4135 }, 4136 #endif /* chips */ 4137 4138 #if defined(BCM_56270_A0) 4139 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFO_BCM56270_A0fmt */ 4140 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4141 /* nFields */ 7, 4142 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFO_BCM56260_A0fmt_fields, 4143 /* bits */ 20, 4144 /* flags */ 0, 4145 }, 4146 #endif /* chips */ 4147 4148 #if defined(BCM_56440_B0) 4149 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFO_BCM56440_B0fmt */ 4150 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4151 /* nFields */ 6, 4152 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFOfmt_fields, 4153 /* bits */ 13, 4154 /* flags */ 0, 4155 }, 4156 #endif /* chips */ 4157 4158 #if defined(BCM_56450_A0) 4159 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFO_BCM56450_A0fmt */ 4160 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4161 /* nFields */ 7, 4162 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFO_BCM56450_A0fmt_fields, 4163 /* bits */ 23, 4164 /* flags */ 0, 4165 }, 4166 #endif /* chips */ 4167 4168 #if defined(BCM_56450_B0) 4169 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFO_BCM56450_B0fmt */ 4170 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4171 /* nFields */ 7, 4172 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFO_BCM56450_A0fmt_fields, 4173 /* bits */ 23, 4174 /* flags */ 0, 4175 }, 4176 #endif /* chips */ 4177 4178 #if defined(BCM_56450_B1) 4179 { /* SOC_FORMAT_INT_RQE_TO_THDO_UC_ENQ_INFO_BCM56450_B1fmt */ 4180 /* format RQE_TO_THDO_UC_ENQ_INFOfmt */ 4181 /* nFields */ 7, 4182 /* *fields */ soc_RQE_TO_THDO_UC_ENQ_INFO_BCM56450_A0fmt_fields, 4183 /* bits */ 23, 4184 /* flags */ 0, 4185 }, 4186 #endif /* chips */ 4187 4188 #if defined(BCM_56440_A0) 4189 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFOfmt */ 4190 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4191 /* nFields */ 15, 4192 /* *fields */ soc_RQE_TO_TOQ_PKT_INFOfmt_fields, 4193 /* bits */ 59, 4194 /* flags */ 0, 4195 }, 4196 #endif /* chips */ 4197 4198 #if defined(BCM_56260_A0) 4199 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFO_BCM56260_A0fmt */ 4200 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4201 /* nFields */ 16, 4202 /* *fields */ soc_RQE_TO_TOQ_PKT_INFO_BCM56260_A0fmt_fields, 4203 /* bits */ 56, 4204 /* flags */ 0, 4205 }, 4206 #endif /* chips */ 4207 4208 #if defined(BCM_56260_B0) 4209 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFO_BCM56260_B0fmt */ 4210 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4211 /* nFields */ 16, 4212 /* *fields */ soc_RQE_TO_TOQ_PKT_INFO_BCM56260_A0fmt_fields, 4213 /* bits */ 56, 4214 /* flags */ 0, 4215 }, 4216 #endif /* chips */ 4217 4218 #if defined(BCM_56270_A0) 4219 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFO_BCM56270_A0fmt */ 4220 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4221 /* nFields */ 15, 4222 /* *fields */ soc_RQE_TO_TOQ_PKT_INFO_BCM56270_A0fmt_fields, 4223 /* bits */ 52, 4224 /* flags */ 0, 4225 }, 4226 #endif /* chips */ 4227 4228 #if defined(BCM_56440_B0) 4229 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFO_BCM56440_B0fmt */ 4230 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4231 /* nFields */ 15, 4232 /* *fields */ soc_RQE_TO_TOQ_PKT_INFOfmt_fields, 4233 /* bits */ 59, 4234 /* flags */ 0, 4235 }, 4236 #endif /* chips */ 4237 4238 #if defined(BCM_56450_A0) 4239 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFO_BCM56450_A0fmt */ 4240 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4241 /* nFields */ 16, 4242 /* *fields */ soc_RQE_TO_TOQ_PKT_INFO_BCM56450_A0fmt_fields, 4243 /* bits */ 60, 4244 /* flags */ 0, 4245 }, 4246 #endif /* chips */ 4247 4248 #if defined(BCM_56450_B0) 4249 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFO_BCM56450_B0fmt */ 4250 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4251 /* nFields */ 16, 4252 /* *fields */ soc_RQE_TO_TOQ_PKT_INFO_BCM56450_A0fmt_fields, 4253 /* bits */ 60, 4254 /* flags */ 0, 4255 }, 4256 #endif /* chips */ 4257 4258 #if defined(BCM_56450_B1) 4259 { /* SOC_FORMAT_INT_RQE_TO_TOQ_PKT_INFO_BCM56450_B1fmt */ 4260 /* format RQE_TO_TOQ_PKT_INFOfmt */ 4261 /* nFields */ 16, 4262 /* *fields */ soc_RQE_TO_TOQ_PKT_INFO_BCM56450_A0fmt_fields, 4263 /* bits */ 60, 4264 /* flags */ 0, 4265 }, 4266 #endif /* chips */ 4267 4268 #if defined(BCM_56440_A0) 4269 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFOfmt */ 4270 /* format RQE_TO_WRED_LANE_INFOfmt */ 4271 /* nFields */ 12, 4272 /* *fields */ soc_RQE_TO_WRED_LANE_INFOfmt_fields, 4273 /* bits */ 36, 4274 /* flags */ 0, 4275 }, 4276 #endif /* chips */ 4277 4278 #if defined(BCM_56260_A0) 4279 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFO_BCM56260_A0fmt */ 4280 /* format RQE_TO_WRED_LANE_INFOfmt */ 4281 /* nFields */ 12, 4282 /* *fields */ soc_RQE_TO_WRED_LANE_INFO_BCM56260_A0fmt_fields, 4283 /* bits */ 32, 4284 /* flags */ 0, 4285 }, 4286 #endif /* chips */ 4287 4288 #if defined(BCM_56260_B0) 4289 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFO_BCM56260_B0fmt */ 4290 /* format RQE_TO_WRED_LANE_INFOfmt */ 4291 /* nFields */ 12, 4292 /* *fields */ soc_RQE_TO_WRED_LANE_INFO_BCM56260_A0fmt_fields, 4293 /* bits */ 32, 4294 /* flags */ 0, 4295 }, 4296 #endif /* chips */ 4297 4298 #if defined(BCM_56270_A0) 4299 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFO_BCM56270_A0fmt */ 4300 /* format RQE_TO_WRED_LANE_INFOfmt */ 4301 /* nFields */ 11, 4302 /* *fields */ soc_RQE_TO_WRED_LANE_INFO_BCM56270_A0fmt_fields, 4303 /* bits */ 29, 4304 /* flags */ 0, 4305 }, 4306 #endif /* chips */ 4307 4308 #if defined(BCM_56440_B0) 4309 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFO_BCM56440_B0fmt */ 4310 /* format RQE_TO_WRED_LANE_INFOfmt */ 4311 /* nFields */ 12, 4312 /* *fields */ soc_RQE_TO_WRED_LANE_INFOfmt_fields, 4313 /* bits */ 36, 4314 /* flags */ 0, 4315 }, 4316 #endif /* chips */ 4317 4318 #if defined(BCM_56450_A0) 4319 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFO_BCM56450_A0fmt */ 4320 /* format RQE_TO_WRED_LANE_INFOfmt */ 4321 /* nFields */ 12, 4322 /* *fields */ soc_RQE_TO_WRED_LANE_INFO_BCM56450_A0fmt_fields, 4323 /* bits */ 36, 4324 /* flags */ 0, 4325 }, 4326 #endif /* chips */ 4327 4328 #if defined(BCM_56450_B0) 4329 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFO_BCM56450_B0fmt */ 4330 /* format RQE_TO_WRED_LANE_INFOfmt */ 4331 /* nFields */ 12, 4332 /* *fields */ soc_RQE_TO_WRED_LANE_INFO_BCM56450_A0fmt_fields, 4333 /* bits */ 36, 4334 /* flags */ 0, 4335 }, 4336 #endif /* chips */ 4337 4338 #if defined(BCM_56450_B1) 4339 { /* SOC_FORMAT_INT_RQE_TO_WRED_LANE_INFO_BCM56450_B1fmt */ 4340 /* format RQE_TO_WRED_LANE_INFOfmt */ 4341 /* nFields */ 12, 4342 /* *fields */ soc_RQE_TO_WRED_LANE_INFO_BCM56450_A0fmt_fields, 4343 /* bits */ 36, 4344 /* flags */ 0, 4345 }, 4346 #endif /* chips */ 4347 4348 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 4349 { /* SOC_FORMAT_INT_RQE_WF_ENTRY_INFOfmt */ 4350 /* format RQE_WF_ENTRY_INFOfmt */ 4351 /* nFields */ 22, 4352 /* *fields */ soc_RQE_WF_ENTRY_INFOfmt_fields, 4353 /* bits */ 337, 4354 /* flags */ 0, 4355 }, 4356 #endif /* chips */ 4357 4358 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4359 { /* SOC_FORMAT_INT_RSEL1_0_DOPfmt */ 4360 /* format RSEL1_0_DOPfmt */ 4361 /* nFields */ 8, 4362 /* *fields */ soc_RSEL1_0_DOPfmt_fields, 4363 /* bits */ 32, 4364 /* flags */ 0, 4365 }, 4366 #endif /* chips */ 4367 4368 #if defined(BCM_56370_A0) 4369 { /* SOC_FORMAT_INT_RSEL1_0_DOP_BCM56370_A0fmt */ 4370 /* format RSEL1_0_DOPfmt */ 4371 /* nFields */ 8, 4372 /* *fields */ soc_RSEL1_0_DOP_BCM56370_A0fmt_fields, 4373 /* bits */ 32, 4374 /* flags */ 0, 4375 }, 4376 #endif /* chips */ 4377 4378 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4379 defined(BCM_56870_A0) 4380 { /* SOC_FORMAT_INT_RSEL1_1_DOPfmt */ 4381 /* format RSEL1_1_DOPfmt */ 4382 /* nFields */ 11, 4383 /* *fields */ soc_RSEL1_1_DOPfmt_fields, 4384 /* bits */ 32, 4385 /* flags */ 0, 4386 }, 4387 #endif /* chips */ 4388 4389 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4390 defined(BCM_56870_A0) 4391 { /* SOC_FORMAT_INT_RSEL1_2_DOPfmt */ 4392 /* format RSEL1_2_DOPfmt */ 4393 /* nFields */ 10, 4394 /* *fields */ soc_RSEL1_2_DOPfmt_fields, 4395 /* bits */ 32, 4396 /* flags */ 0, 4397 }, 4398 #endif /* chips */ 4399 4400 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4401 defined(BCM_56870_A0) 4402 { /* SOC_FORMAT_INT_RSEL1_3_DOPfmt */ 4403 /* format RSEL1_3_DOPfmt */ 4404 /* nFields */ 10, 4405 /* *fields */ soc_RSEL1_3_DOPfmt_fields, 4406 /* bits */ 32, 4407 /* flags */ 0, 4408 }, 4409 #endif /* chips */ 4410 4411 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4412 defined(BCM_56870_A0) 4413 { /* SOC_FORMAT_INT_RSEL1_FIRST_DVP_NHI_DOPfmt */ 4414 /* format RSEL1_FIRST_DVP_NHI_DOPfmt */ 4415 /* nFields */ 4, 4416 /* *fields */ soc_RSEL1_FIRST_DVP_NHI_DOPfmt_fields, 4417 /* bits */ 32, 4418 /* flags */ 0, 4419 }, 4420 #endif /* chips */ 4421 4422 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4423 { /* SOC_FORMAT_INT_RSEL1_FIRST_ECMP_DOPfmt */ 4424 /* format RSEL1_FIRST_ECMP_DOPfmt */ 4425 /* nFields */ 7, 4426 /* *fields */ soc_RSEL1_FIRST_ECMP_DOPfmt_fields, 4427 /* bits */ 64, 4428 /* flags */ 0, 4429 }, 4430 #endif /* chips */ 4431 4432 #if defined(BCM_56370_A0) 4433 { /* SOC_FORMAT_INT_RSEL1_FIRST_ECMP_DOP_BCM56370_A0fmt */ 4434 /* format RSEL1_FIRST_ECMP_DOPfmt */ 4435 /* nFields */ 7, 4436 /* *fields */ soc_RSEL1_FIRST_ECMP_DOP_BCM56370_A0fmt_fields, 4437 /* bits */ 64, 4438 /* flags */ 0, 4439 }, 4440 #endif /* chips */ 4441 4442 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4443 defined(BCM_56870_A0) 4444 { /* SOC_FORMAT_INT_RSEL1_SECOND_DVP_NHI_DOPfmt */ 4445 /* format RSEL1_SECOND_DVP_NHI_DOPfmt */ 4446 /* nFields */ 4, 4447 /* *fields */ soc_RSEL1_SECOND_DVP_NHI_DOPfmt_fields, 4448 /* bits */ 32, 4449 /* flags */ 0, 4450 }, 4451 #endif /* chips */ 4452 4453 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4454 { /* SOC_FORMAT_INT_RSEL1_SECOND_ECMP_DOPfmt */ 4455 /* format RSEL1_SECOND_ECMP_DOPfmt */ 4456 /* nFields */ 7, 4457 /* *fields */ soc_RSEL1_SECOND_ECMP_DOPfmt_fields, 4458 /* bits */ 64, 4459 /* flags */ 0, 4460 }, 4461 #endif /* chips */ 4462 4463 #if defined(BCM_56370_A0) 4464 { /* SOC_FORMAT_INT_RSEL1_SECOND_ECMP_DOP_BCM56370_A0fmt */ 4465 /* format RSEL1_SECOND_ECMP_DOPfmt */ 4466 /* nFields */ 7, 4467 /* *fields */ soc_RSEL1_SECOND_ECMP_DOP_BCM56370_A0fmt_fields, 4468 /* bits */ 64, 4469 /* flags */ 0, 4470 }, 4471 #endif /* chips */ 4472 4473 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4474 defined(BCM_56870_A0) 4475 { /* SOC_FORMAT_INT_RSEL2_0_DOPfmt */ 4476 /* format RSEL2_0_DOPfmt */ 4477 /* nFields */ 10, 4478 /* *fields */ soc_RSEL2_0_DOPfmt_fields, 4479 /* bits */ 32, 4480 /* flags */ 0, 4481 }, 4482 #endif /* chips */ 4483 4484 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4485 defined(BCM_56870_A0) 4486 { /* SOC_FORMAT_INT_RSEL2_1_DOPfmt */ 4487 /* format RSEL2_1_DOPfmt */ 4488 /* nFields */ 6, 4489 /* *fields */ soc_RSEL2_1_DOPfmt_fields, 4490 /* bits */ 32, 4491 /* flags */ 0, 4492 }, 4493 #endif /* chips */ 4494 4495 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4496 defined(BCM_56870_A0) 4497 { /* SOC_FORMAT_INT_RSEL2_2_DOPfmt */ 4498 /* format RSEL2_2_DOPfmt */ 4499 /* nFields */ 9, 4500 /* *fields */ soc_RSEL2_2_DOPfmt_fields, 4501 /* bits */ 32, 4502 /* flags */ 0, 4503 }, 4504 #endif /* chips */ 4505 4506 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4507 { /* SOC_FORMAT_INT_RSEL2_3_DOPfmt */ 4508 /* format RSEL2_3_DOPfmt */ 4509 /* nFields */ 10, 4510 /* *fields */ soc_RSEL2_3_DOPfmt_fields, 4511 /* bits */ 32, 4512 /* flags */ 0, 4513 }, 4514 #endif /* chips */ 4515 4516 #if defined(BCM_56370_A0) 4517 { /* SOC_FORMAT_INT_RSEL2_3_DOP_BCM56370_A0fmt */ 4518 /* format RSEL2_3_DOPfmt */ 4519 /* nFields */ 10, 4520 /* *fields */ soc_RSEL2_3_DOP_BCM56370_A0fmt_fields, 4521 /* bits */ 32, 4522 /* flags */ 0, 4523 }, 4524 #endif /* chips */ 4525 4526 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4527 defined(BCM_56870_A0) 4528 { /* SOC_FORMAT_INT_RSEL2_DROP_VECTORfmt */ 4529 /* format RSEL2_DROP_VECTORfmt */ 4530 /* nFields */ 12, 4531 /* *fields */ soc_RSEL2_DROP_VECTORfmt_fields, 4532 /* bits */ 13, 4533 /* flags */ 0, 4534 }, 4535 #endif /* chips */ 4536 4537 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4538 { /* SOC_FORMAT_INT_RSEL2_FIRST_DVP_NHI_DOPfmt */ 4539 /* format RSEL2_FIRST_DVP_NHI_DOPfmt */ 4540 /* nFields */ 4, 4541 /* *fields */ soc_RSEL2_FIRST_DVP_NHI_DOPfmt_fields, 4542 /* bits */ 32, 4543 /* flags */ 0, 4544 }, 4545 #endif /* chips */ 4546 4547 #if defined(BCM_56370_A0) 4548 { /* SOC_FORMAT_INT_RSEL2_FIRST_DVP_NHI_DOP_BCM56370_A0fmt */ 4549 /* format RSEL2_FIRST_DVP_NHI_DOPfmt */ 4550 /* nFields */ 4, 4551 /* *fields */ soc_RSEL2_FIRST_DVP_NHI_DOP_BCM56370_A0fmt_fields, 4552 /* bits */ 32, 4553 /* flags */ 0, 4554 }, 4555 #endif /* chips */ 4556 4557 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4558 { /* SOC_FORMAT_INT_RSEL2_FIRST_ECMP_DOPfmt */ 4559 /* format RSEL2_FIRST_ECMP_DOPfmt */ 4560 /* nFields */ 6, 4561 /* *fields */ soc_RSEL2_FIRST_ECMP_DOPfmt_fields, 4562 /* bits */ 64, 4563 /* flags */ 0, 4564 }, 4565 #endif /* chips */ 4566 4567 #if defined(BCM_56370_A0) 4568 { /* SOC_FORMAT_INT_RSEL2_FIRST_ECMP_DOP_BCM56370_A0fmt */ 4569 /* format RSEL2_FIRST_ECMP_DOPfmt */ 4570 /* nFields */ 6, 4571 /* *fields */ soc_RSEL2_FIRST_ECMP_DOP_BCM56370_A0fmt_fields, 4572 /* bits */ 64, 4573 /* flags */ 0, 4574 }, 4575 #endif /* chips */ 4576 4577 #if defined(BCM_56870_A0) 4578 { /* SOC_FORMAT_INT_RSEL2_SECOND_DVP_NHI_DOPfmt */ 4579 /* format RSEL2_SECOND_DVP_NHI_DOPfmt */ 4580 /* nFields */ 4, 4581 /* *fields */ soc_RSEL2_FIRST_DVP_NHI_DOPfmt_fields, 4582 /* bits */ 32, 4583 /* flags */ 0, 4584 }, 4585 #endif /* chips */ 4586 4587 #if defined(BCM_56370_A0) 4588 { /* SOC_FORMAT_INT_RSEL2_SECOND_DVP_NHI_DOP_BCM56370_A0fmt */ 4589 /* format RSEL2_SECOND_DVP_NHI_DOPfmt */ 4590 /* nFields */ 4, 4591 /* *fields */ soc_RSEL2_FIRST_DVP_NHI_DOP_BCM56370_A0fmt_fields, 4592 /* bits */ 32, 4593 /* flags */ 0, 4594 }, 4595 #endif /* chips */ 4596 4597 #if defined(BCM_56770_A0) 4598 { /* SOC_FORMAT_INT_RSEL2_SECOND_DVP_NHI_DOP_BCM56770_A0fmt */ 4599 /* format RSEL2_SECOND_DVP_NHI_DOPfmt */ 4600 /* nFields */ 4, 4601 /* *fields */ soc_RSEL2_FIRST_DVP_NHI_DOPfmt_fields, 4602 /* bits */ 32, 4603 /* flags */ 0, 4604 }, 4605 #endif /* chips */ 4606 4607 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4608 { /* SOC_FORMAT_INT_RSEL2_SECOND_ECMP_DOPfmt */ 4609 /* format RSEL2_SECOND_ECMP_DOPfmt */ 4610 /* nFields */ 6, 4611 /* *fields */ soc_RSEL2_SECOND_ECMP_DOPfmt_fields, 4612 /* bits */ 64, 4613 /* flags */ 0, 4614 }, 4615 #endif /* chips */ 4616 4617 #if defined(BCM_56370_A0) 4618 { /* SOC_FORMAT_INT_RSEL2_SECOND_ECMP_DOP_BCM56370_A0fmt */ 4619 /* format RSEL2_SECOND_ECMP_DOPfmt */ 4620 /* nFields */ 6, 4621 /* *fields */ soc_RSEL2_SECOND_ECMP_DOP_BCM56370_A0fmt_fields, 4622 /* bits */ 64, 4623 /* flags */ 0, 4624 }, 4625 #endif /* chips */ 4626 4627 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4628 { /* SOC_FORMAT_INT_RSEL_DROP_VECTORfmt */ 4629 /* format RSEL_DROP_VECTORfmt */ 4630 /* nFields */ 7, 4631 /* *fields */ soc_RSEL_DROP_VECTORfmt_fields, 4632 /* bits */ 12, 4633 /* flags */ 0, 4634 }, 4635 #endif /* chips */ 4636 4637 #if defined(BCM_56640_A0) 4638 { /* SOC_FORMAT_INT_RSP_WORDfmt */ 4639 /* format RSP_WORDfmt */ 4640 /* nFields */ 4, 4641 /* *fields */ soc_ISM_RSP_WORDfmt_fields, 4642 /* bits */ 32, 4643 /* flags */ 0, 4644 }, 4645 #endif /* chips */ 4646 4647 #if defined(BCM_56440_A0) || defined(BCM_56524_A0) || \ 4648 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 4649 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 4650 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 4651 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 4652 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 4653 defined(BCM_88732_A0) 4654 { /* SOC_FORMAT_INT_RSP_WORD_0fmt */ 4655 /* format RSP_WORD_0fmt */ 4656 /* nFields */ 6, 4657 /* *fields */ soc_RSP_WORD_0fmt_fields, 4658 /* bits */ 32, 4659 /* flags */ 0, 4660 }, 4661 #endif /* chips */ 4662 4663 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 4664 defined(BCM_56680_A0) 4665 { /* SOC_FORMAT_INT_RSP_WORD_1fmt */ 4666 /* format RSP_WORD_1fmt */ 4667 /* nFields */ 8, 4668 /* *fields */ soc_RSP_WORD_1fmt_fields, 4669 /* bits */ 32, 4670 /* flags */ 0, 4671 }, 4672 #endif /* chips */ 4673 4674 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) 4675 { /* SOC_FORMAT_INT_RSP_WORD_2fmt */ 4676 /* format RSP_WORD_2fmt */ 4677 /* nFields */ 4, 4678 /* *fields */ soc_RSP_WORD_2fmt_fields, 4679 /* bits */ 32, 4680 /* flags */ 0, 4681 }, 4682 #endif /* chips */ 4683 4684 #if defined(BCM_53400_A0) 4685 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM53400_A0fmt */ 4686 /* format RSP_WORD_0fmt */ 4687 /* nFields */ 6, 4688 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4689 /* bits */ 32, 4690 /* flags */ 0, 4691 }, 4692 #endif /* chips */ 4693 4694 #if defined(BCM_53540_A0) 4695 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM53540_A0fmt */ 4696 /* format RSP_WORD_0fmt */ 4697 /* nFields */ 6, 4698 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4699 /* bits */ 32, 4700 /* flags */ 0, 4701 }, 4702 #endif /* chips */ 4703 4704 #if defined(BCM_53570_A0) 4705 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM53570_A0fmt */ 4706 /* format RSP_WORD_0fmt */ 4707 /* nFields */ 6, 4708 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4709 /* bits */ 32, 4710 /* flags */ 0, 4711 }, 4712 #endif /* chips */ 4713 4714 #if defined(BCM_53570_B0) 4715 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM53570_B0fmt */ 4716 /* format RSP_WORD_0fmt */ 4717 /* nFields */ 6, 4718 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4719 /* bits */ 32, 4720 /* flags */ 0, 4721 }, 4722 #endif /* chips */ 4723 4724 #if defined(BCM_56142_A0) 4725 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56142_A0fmt */ 4726 /* format RSP_WORD_0fmt */ 4727 /* nFields */ 6, 4728 /* *fields */ soc_RSP_WORD_0fmt_fields, 4729 /* bits */ 32, 4730 /* flags */ 0, 4731 }, 4732 #endif /* chips */ 4733 4734 #if defined(BCM_56150_A0) 4735 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56150_A0fmt */ 4736 /* format RSP_WORD_0fmt */ 4737 /* nFields */ 6, 4738 /* *fields */ soc_RSP_WORD_0_BCM56450_A0fmt_fields, 4739 /* bits */ 32, 4740 /* flags */ 0, 4741 }, 4742 #endif /* chips */ 4743 4744 #if defined(BCM_56160_A0) 4745 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56160_A0fmt */ 4746 /* format RSP_WORD_0fmt */ 4747 /* nFields */ 6, 4748 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4749 /* bits */ 32, 4750 /* flags */ 0, 4751 }, 4752 #endif /* chips */ 4753 4754 #if defined(BCM_56260_A0) 4755 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56260_A0fmt */ 4756 /* format RSP_WORD_0fmt */ 4757 /* nFields */ 6, 4758 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4759 /* bits */ 32, 4760 /* flags */ 0, 4761 }, 4762 #endif /* chips */ 4763 4764 #if defined(BCM_56260_B0) 4765 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56260_B0fmt */ 4766 /* format RSP_WORD_0fmt */ 4767 /* nFields */ 6, 4768 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4769 /* bits */ 32, 4770 /* flags */ 0, 4771 }, 4772 #endif /* chips */ 4773 4774 #if defined(BCM_56270_A0) 4775 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56270_A0fmt */ 4776 /* format RSP_WORD_0fmt */ 4777 /* nFields */ 6, 4778 /* *fields */ soc_RSP_WORD_0_BCM53400_A0fmt_fields, 4779 /* bits */ 32, 4780 /* flags */ 0, 4781 }, 4782 #endif /* chips */ 4783 4784 #if defined(BCM_56334_A0) 4785 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56334_A0fmt */ 4786 /* format RSP_WORD_0fmt */ 4787 /* nFields */ 6, 4788 /* *fields */ soc_RSP_WORD_0fmt_fields, 4789 /* bits */ 32, 4790 /* flags */ 0, 4791 }, 4792 #endif /* chips */ 4793 4794 #if defined(BCM_56334_B0) 4795 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56334_B0fmt */ 4796 /* format RSP_WORD_0fmt */ 4797 /* nFields */ 6, 4798 /* *fields */ soc_RSP_WORD_0fmt_fields, 4799 /* bits */ 32, 4800 /* flags */ 0, 4801 }, 4802 #endif /* chips */ 4803 4804 #if defined(BCM_56440_B0) 4805 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56440_B0fmt */ 4806 /* format RSP_WORD_0fmt */ 4807 /* nFields */ 6, 4808 /* *fields */ soc_RSP_WORD_0fmt_fields, 4809 /* bits */ 32, 4810 /* flags */ 0, 4811 }, 4812 #endif /* chips */ 4813 4814 #if defined(BCM_56450_A0) 4815 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56450_A0fmt */ 4816 /* format RSP_WORD_0fmt */ 4817 /* nFields */ 6, 4818 /* *fields */ soc_RSP_WORD_0_BCM56450_A0fmt_fields, 4819 /* bits */ 32, 4820 /* flags */ 0, 4821 }, 4822 #endif /* chips */ 4823 4824 #if defined(BCM_56450_B0) 4825 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56450_B0fmt */ 4826 /* format RSP_WORD_0fmt */ 4827 /* nFields */ 6, 4828 /* *fields */ soc_RSP_WORD_0_BCM56450_A0fmt_fields, 4829 /* bits */ 32, 4830 /* flags */ 0, 4831 }, 4832 #endif /* chips */ 4833 4834 #if defined(BCM_56450_B1) 4835 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56450_B1fmt */ 4836 /* format RSP_WORD_0fmt */ 4837 /* nFields */ 6, 4838 /* *fields */ soc_RSP_WORD_0_BCM56450_A0fmt_fields, 4839 /* bits */ 32, 4840 /* flags */ 0, 4841 }, 4842 #endif /* chips */ 4843 4844 #if defined(BCM_56524_B0) 4845 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56524_B0fmt */ 4846 /* format RSP_WORD_0fmt */ 4847 /* nFields */ 6, 4848 /* *fields */ soc_RSP_WORD_0fmt_fields, 4849 /* bits */ 32, 4850 /* flags */ 0, 4851 }, 4852 #endif /* chips */ 4853 4854 #if defined(BCM_56685_A0) 4855 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56685_A0fmt */ 4856 /* format RSP_WORD_0fmt */ 4857 /* nFields */ 6, 4858 /* *fields */ soc_RSP_WORD_0fmt_fields, 4859 /* bits */ 32, 4860 /* flags */ 0, 4861 }, 4862 #endif /* chips */ 4863 4864 #if defined(BCM_56685_B0) 4865 { /* SOC_FORMAT_INT_RSP_WORD_0_BCM56685_B0fmt */ 4866 /* format RSP_WORD_0fmt */ 4867 /* nFields */ 6, 4868 /* *fields */ soc_RSP_WORD_0fmt_fields, 4869 /* bits */ 32, 4870 /* flags */ 0, 4871 }, 4872 #endif /* chips */ 4873 4874 #if defined(BCM_53400_A0) 4875 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM53400_A0fmt */ 4876 /* format RSP_WORD_1fmt */ 4877 /* nFields */ 8, 4878 /* *fields */ soc_RSP_WORD_1_BCM53400_A0fmt_fields, 4879 /* bits */ 32, 4880 /* flags */ 0, 4881 }, 4882 #endif /* chips */ 4883 4884 #if defined(BCM_53540_A0) 4885 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM53540_A0fmt */ 4886 /* format RSP_WORD_1fmt */ 4887 /* nFields */ 8, 4888 /* *fields */ soc_RSP_WORD_1_BCM53400_A0fmt_fields, 4889 /* bits */ 32, 4890 /* flags */ 0, 4891 }, 4892 #endif /* chips */ 4893 4894 #if defined(BCM_53570_A0) 4895 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM53570_A0fmt */ 4896 /* format RSP_WORD_1fmt */ 4897 /* nFields */ 8, 4898 /* *fields */ soc_RSP_WORD_1_BCM53570_A0fmt_fields, 4899 /* bits */ 32, 4900 /* flags */ 0, 4901 }, 4902 #endif /* chips */ 4903 4904 #if defined(BCM_53570_B0) 4905 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM53570_B0fmt */ 4906 /* format RSP_WORD_1fmt */ 4907 /* nFields */ 8, 4908 /* *fields */ soc_RSP_WORD_1_BCM53570_B0fmt_fields, 4909 /* bits */ 32, 4910 /* flags */ 0, 4911 }, 4912 #endif /* chips */ 4913 4914 #if defined(BCM_56142_A0) 4915 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56142_A0fmt */ 4916 /* format RSP_WORD_1fmt */ 4917 /* nFields */ 8, 4918 /* *fields */ soc_RSP_WORD_1_BCM56142_A0fmt_fields, 4919 /* bits */ 32, 4920 /* flags */ 0, 4921 }, 4922 #endif /* chips */ 4923 4924 #if defined(BCM_56150_A0) 4925 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56150_A0fmt */ 4926 /* format RSP_WORD_1fmt */ 4927 /* nFields */ 8, 4928 /* *fields */ soc_RSP_WORD_1_BCM56150_A0fmt_fields, 4929 /* bits */ 32, 4930 /* flags */ 0, 4931 }, 4932 #endif /* chips */ 4933 4934 #if defined(BCM_56160_A0) 4935 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56160_A0fmt */ 4936 /* format RSP_WORD_1fmt */ 4937 /* nFields */ 8, 4938 /* *fields */ soc_RSP_WORD_1_BCM56160_A0fmt_fields, 4939 /* bits */ 32, 4940 /* flags */ 0, 4941 }, 4942 #endif /* chips */ 4943 4944 #if defined(BCM_56260_A0) 4945 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56260_A0fmt */ 4946 /* format RSP_WORD_1fmt */ 4947 /* nFields */ 12, 4948 /* *fields */ soc_RSP_WORD_1_BCM56260_A0fmt_fields, 4949 /* bits */ 32, 4950 /* flags */ 0, 4951 }, 4952 #endif /* chips */ 4953 4954 #if defined(BCM_56260_B0) 4955 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56260_B0fmt */ 4956 /* format RSP_WORD_1fmt */ 4957 /* nFields */ 12, 4958 /* *fields */ soc_RSP_WORD_1_BCM56260_A0fmt_fields, 4959 /* bits */ 32, 4960 /* flags */ 0, 4961 }, 4962 #endif /* chips */ 4963 4964 #if defined(BCM_56270_A0) 4965 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56270_A0fmt */ 4966 /* format RSP_WORD_1fmt */ 4967 /* nFields */ 12, 4968 /* *fields */ soc_RSP_WORD_1_BCM56260_A0fmt_fields, 4969 /* bits */ 32, 4970 /* flags */ 0, 4971 }, 4972 #endif /* chips */ 4973 4974 #if defined(BCM_56334_A0) 4975 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56334_A0fmt */ 4976 /* format RSP_WORD_1fmt */ 4977 /* nFields */ 8, 4978 /* *fields */ soc_RSP_WORD_1fmt_fields, 4979 /* bits */ 32, 4980 /* flags */ 0, 4981 }, 4982 #endif /* chips */ 4983 4984 #if defined(BCM_56334_B0) 4985 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56334_B0fmt */ 4986 /* format RSP_WORD_1fmt */ 4987 /* nFields */ 8, 4988 /* *fields */ soc_RSP_WORD_1fmt_fields, 4989 /* bits */ 32, 4990 /* flags */ 0, 4991 }, 4992 #endif /* chips */ 4993 4994 #if defined(BCM_56440_A0) 4995 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56440_A0fmt */ 4996 /* format RSP_WORD_1fmt */ 4997 /* nFields */ 12, 4998 /* *fields */ soc_RSP_WORD_1_BCM56840_A0fmt_fields, 4999 /* bits */ 32, 5000 /* flags */ 0, 5001 }, 5002 #endif /* chips */ 5003 5004 #if defined(BCM_56440_B0) 5005 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56440_B0fmt */ 5006 /* format RSP_WORD_1fmt */ 5007 /* nFields */ 12, 5008 /* *fields */ soc_RSP_WORD_1_BCM56840_A0fmt_fields, 5009 /* bits */ 32, 5010 /* flags */ 0, 5011 }, 5012 #endif /* chips */ 5013 5014 #if defined(BCM_56450_A0) 5015 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56450_A0fmt */ 5016 /* format RSP_WORD_1fmt */ 5017 /* nFields */ 12, 5018 /* *fields */ soc_RSP_WORD_1_BCM56450_A0fmt_fields, 5019 /* bits */ 32, 5020 /* flags */ 0, 5021 }, 5022 #endif /* chips */ 5023 5024 #if defined(BCM_56450_B0) 5025 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56450_B0fmt */ 5026 /* format RSP_WORD_1fmt */ 5027 /* nFields */ 12, 5028 /* *fields */ soc_RSP_WORD_1_BCM56450_A0fmt_fields, 5029 /* bits */ 32, 5030 /* flags */ 0, 5031 }, 5032 #endif /* chips */ 5033 5034 #if defined(BCM_56450_B1) 5035 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56450_B1fmt */ 5036 /* format RSP_WORD_1fmt */ 5037 /* nFields */ 12, 5038 /* *fields */ soc_RSP_WORD_1_BCM56450_A0fmt_fields, 5039 /* bits */ 32, 5040 /* flags */ 0, 5041 }, 5042 #endif /* chips */ 5043 5044 #if defined(BCM_56524_A0) 5045 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56524_A0fmt */ 5046 /* format RSP_WORD_1fmt */ 5047 /* nFields */ 10, 5048 /* *fields */ soc_RSP_WORD_1_BCM56634_A0fmt_fields, 5049 /* bits */ 32, 5050 /* flags */ 0, 5051 }, 5052 #endif /* chips */ 5053 5054 #if defined(BCM_56524_B0) 5055 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56524_B0fmt */ 5056 /* format RSP_WORD_1fmt */ 5057 /* nFields */ 10, 5058 /* *fields */ soc_RSP_WORD_1_BCM56634_A0fmt_fields, 5059 /* bits */ 32, 5060 /* flags */ 0, 5061 }, 5062 #endif /* chips */ 5063 5064 #if defined(BCM_56634_A0) 5065 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56634_A0fmt */ 5066 /* format RSP_WORD_1fmt */ 5067 /* nFields */ 10, 5068 /* *fields */ soc_RSP_WORD_1_BCM56634_A0fmt_fields, 5069 /* bits */ 32, 5070 /* flags */ 0, 5071 }, 5072 #endif /* chips */ 5073 5074 #if defined(BCM_56634_B0) 5075 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56634_B0fmt */ 5076 /* format RSP_WORD_1fmt */ 5077 /* nFields */ 10, 5078 /* *fields */ soc_RSP_WORD_1_BCM56634_A0fmt_fields, 5079 /* bits */ 32, 5080 /* flags */ 0, 5081 }, 5082 #endif /* chips */ 5083 5084 #if defined(BCM_56680_B0) 5085 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56680_B0fmt */ 5086 /* format RSP_WORD_1fmt */ 5087 /* nFields */ 8, 5088 /* *fields */ soc_RSP_WORD_1fmt_fields, 5089 /* bits */ 32, 5090 /* flags */ 0, 5091 }, 5092 #endif /* chips */ 5093 5094 #if defined(BCM_56685_A0) 5095 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56685_A0fmt */ 5096 /* format RSP_WORD_1fmt */ 5097 /* nFields */ 10, 5098 /* *fields */ soc_RSP_WORD_1_BCM56634_A0fmt_fields, 5099 /* bits */ 32, 5100 /* flags */ 0, 5101 }, 5102 #endif /* chips */ 5103 5104 #if defined(BCM_56685_B0) 5105 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56685_B0fmt */ 5106 /* format RSP_WORD_1fmt */ 5107 /* nFields */ 10, 5108 /* *fields */ soc_RSP_WORD_1_BCM56634_A0fmt_fields, 5109 /* bits */ 32, 5110 /* flags */ 0, 5111 }, 5112 #endif /* chips */ 5113 5114 #if defined(BCM_56725_A0) 5115 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56725_A0fmt */ 5116 /* format RSP_WORD_1fmt */ 5117 /* nFields */ 8, 5118 /* *fields */ soc_RSP_WORD_1fmt_fields, 5119 /* bits */ 32, 5120 /* flags */ 0, 5121 }, 5122 #endif /* chips */ 5123 5124 #if defined(BCM_56820_A0) 5125 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56820_A0fmt */ 5126 /* format RSP_WORD_1fmt */ 5127 /* nFields */ 8, 5128 /* *fields */ soc_RSP_WORD_1fmt_fields, 5129 /* bits */ 32, 5130 /* flags */ 0, 5131 }, 5132 #endif /* chips */ 5133 5134 #if defined(BCM_56840_A0) 5135 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56840_A0fmt */ 5136 /* format RSP_WORD_1fmt */ 5137 /* nFields */ 12, 5138 /* *fields */ soc_RSP_WORD_1_BCM56840_A0fmt_fields, 5139 /* bits */ 32, 5140 /* flags */ 0, 5141 }, 5142 #endif /* chips */ 5143 5144 #if defined(BCM_56840_B0) 5145 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM56840_B0fmt */ 5146 /* format RSP_WORD_1fmt */ 5147 /* nFields */ 12, 5148 /* *fields */ soc_RSP_WORD_1_BCM56840_B0fmt_fields, 5149 /* bits */ 32, 5150 /* flags */ 0, 5151 }, 5152 #endif /* chips */ 5153 5154 #if defined(BCM_88732_A0) 5155 { /* SOC_FORMAT_INT_RSP_WORD_1_BCM88732_A0fmt */ 5156 /* format RSP_WORD_1fmt */ 5157 /* nFields */ 2, 5158 /* *fields */ soc_RSP_WORD_1_BCM88732_A0fmt_fields, 5159 /* bits */ 32, 5160 /* flags */ 0, 5161 }, 5162 #endif /* chips */ 5163 5164 #if defined(BCM_53400_A0) 5165 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM53400_A0fmt */ 5166 /* format RSP_WORD_2fmt */ 5167 /* nFields */ 4, 5168 /* *fields */ soc_RSP_WORD_2_BCM53400_A0fmt_fields, 5169 /* bits */ 32, 5170 /* flags */ 0, 5171 }, 5172 #endif /* chips */ 5173 5174 #if defined(BCM_53540_A0) 5175 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM53540_A0fmt */ 5176 /* format RSP_WORD_2fmt */ 5177 /* nFields */ 4, 5178 /* *fields */ soc_RSP_WORD_2_BCM53400_A0fmt_fields, 5179 /* bits */ 32, 5180 /* flags */ 0, 5181 }, 5182 #endif /* chips */ 5183 5184 #if defined(BCM_53570_A0) 5185 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM53570_A0fmt */ 5186 /* format RSP_WORD_2fmt */ 5187 /* nFields */ 4, 5188 /* *fields */ soc_RSP_WORD_2_BCM53400_A0fmt_fields, 5189 /* bits */ 32, 5190 /* flags */ 0, 5191 }, 5192 #endif /* chips */ 5193 5194 #if defined(BCM_53570_B0) 5195 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM53570_B0fmt */ 5196 /* format RSP_WORD_2fmt */ 5197 /* nFields */ 4, 5198 /* *fields */ soc_RSP_WORD_2_BCM53400_A0fmt_fields, 5199 /* bits */ 32, 5200 /* flags */ 0, 5201 }, 5202 #endif /* chips */ 5203 5204 #if defined(BCM_56142_A0) 5205 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56142_A0fmt */ 5206 /* format RSP_WORD_2fmt */ 5207 /* nFields */ 4, 5208 /* *fields */ soc_RSP_WORD_2fmt_fields, 5209 /* bits */ 32, 5210 /* flags */ 0, 5211 }, 5212 #endif /* chips */ 5213 5214 #if defined(BCM_56150_A0) 5215 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56150_A0fmt */ 5216 /* format RSP_WORD_2fmt */ 5217 /* nFields */ 4, 5218 /* *fields */ soc_RSP_WORD_2_BCM56150_A0fmt_fields, 5219 /* bits */ 32, 5220 /* flags */ 0, 5221 }, 5222 #endif /* chips */ 5223 5224 #if defined(BCM_56160_A0) 5225 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56160_A0fmt */ 5226 /* format RSP_WORD_2fmt */ 5227 /* nFields */ 4, 5228 /* *fields */ soc_RSP_WORD_2_BCM53400_A0fmt_fields, 5229 /* bits */ 32, 5230 /* flags */ 0, 5231 }, 5232 #endif /* chips */ 5233 5234 #if defined(BCM_56260_A0) 5235 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56260_A0fmt */ 5236 /* format RSP_WORD_2fmt */ 5237 /* nFields */ 5, 5238 /* *fields */ soc_RSP_WORD_2_BCM56260_A0fmt_fields, 5239 /* bits */ 32, 5240 /* flags */ 0, 5241 }, 5242 #endif /* chips */ 5243 5244 #if defined(BCM_56260_B0) 5245 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56260_B0fmt */ 5246 /* format RSP_WORD_2fmt */ 5247 /* nFields */ 5, 5248 /* *fields */ soc_RSP_WORD_2_BCM56260_A0fmt_fields, 5249 /* bits */ 32, 5250 /* flags */ 0, 5251 }, 5252 #endif /* chips */ 5253 5254 #if defined(BCM_56270_A0) 5255 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56270_A0fmt */ 5256 /* format RSP_WORD_2fmt */ 5257 /* nFields */ 5, 5258 /* *fields */ soc_RSP_WORD_2_BCM56260_A0fmt_fields, 5259 /* bits */ 32, 5260 /* flags */ 0, 5261 }, 5262 #endif /* chips */ 5263 5264 #if defined(BCM_56334_A0) 5265 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56334_A0fmt */ 5266 /* format RSP_WORD_2fmt */ 5267 /* nFields */ 4, 5268 /* *fields */ soc_RSP_WORD_2fmt_fields, 5269 /* bits */ 32, 5270 /* flags */ 0, 5271 }, 5272 #endif /* chips */ 5273 5274 #if defined(BCM_56334_B0) 5275 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56334_B0fmt */ 5276 /* format RSP_WORD_2fmt */ 5277 /* nFields */ 4, 5278 /* *fields */ soc_RSP_WORD_2fmt_fields, 5279 /* bits */ 32, 5280 /* flags */ 0, 5281 }, 5282 #endif /* chips */ 5283 5284 #if defined(BCM_56440_A0) 5285 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56440_A0fmt */ 5286 /* format RSP_WORD_2fmt */ 5287 /* nFields */ 5, 5288 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5289 /* bits */ 32, 5290 /* flags */ 0, 5291 }, 5292 #endif /* chips */ 5293 5294 #if defined(BCM_56440_B0) 5295 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56440_B0fmt */ 5296 /* format RSP_WORD_2fmt */ 5297 /* nFields */ 5, 5298 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5299 /* bits */ 32, 5300 /* flags */ 0, 5301 }, 5302 #endif /* chips */ 5303 5304 #if defined(BCM_56450_A0) 5305 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56450_A0fmt */ 5306 /* format RSP_WORD_2fmt */ 5307 /* nFields */ 5, 5308 /* *fields */ soc_RSP_WORD_2_BCM56450_A0fmt_fields, 5309 /* bits */ 32, 5310 /* flags */ 0, 5311 }, 5312 #endif /* chips */ 5313 5314 #if defined(BCM_56450_B0) 5315 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56450_B0fmt */ 5316 /* format RSP_WORD_2fmt */ 5317 /* nFields */ 5, 5318 /* *fields */ soc_RSP_WORD_2_BCM56450_A0fmt_fields, 5319 /* bits */ 32, 5320 /* flags */ 0, 5321 }, 5322 #endif /* chips */ 5323 5324 #if defined(BCM_56450_B1) 5325 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56450_B1fmt */ 5326 /* format RSP_WORD_2fmt */ 5327 /* nFields */ 5, 5328 /* *fields */ soc_RSP_WORD_2_BCM56450_A0fmt_fields, 5329 /* bits */ 32, 5330 /* flags */ 0, 5331 }, 5332 #endif /* chips */ 5333 5334 #if defined(BCM_56524_A0) 5335 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56524_A0fmt */ 5336 /* format RSP_WORD_2fmt */ 5337 /* nFields */ 5, 5338 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5339 /* bits */ 32, 5340 /* flags */ 0, 5341 }, 5342 #endif /* chips */ 5343 5344 #if defined(BCM_56524_B0) 5345 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56524_B0fmt */ 5346 /* format RSP_WORD_2fmt */ 5347 /* nFields */ 5, 5348 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5349 /* bits */ 32, 5350 /* flags */ 0, 5351 }, 5352 #endif /* chips */ 5353 5354 #if defined(BCM_56634_A0) 5355 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56634_A0fmt */ 5356 /* format RSP_WORD_2fmt */ 5357 /* nFields */ 5, 5358 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5359 /* bits */ 32, 5360 /* flags */ 0, 5361 }, 5362 #endif /* chips */ 5363 5364 #if defined(BCM_56634_B0) 5365 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56634_B0fmt */ 5366 /* format RSP_WORD_2fmt */ 5367 /* nFields */ 5, 5368 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5369 /* bits */ 32, 5370 /* flags */ 0, 5371 }, 5372 #endif /* chips */ 5373 5374 #if defined(BCM_56680_A0) 5375 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56680_A0fmt */ 5376 /* format RSP_WORD_2fmt */ 5377 /* nFields */ 4, 5378 /* *fields */ soc_RSP_WORD_2fmt_fields, 5379 /* bits */ 32, 5380 /* flags */ 0, 5381 }, 5382 #endif /* chips */ 5383 5384 #if defined(BCM_56680_B0) 5385 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56680_B0fmt */ 5386 /* format RSP_WORD_2fmt */ 5387 /* nFields */ 4, 5388 /* *fields */ soc_RSP_WORD_2fmt_fields, 5389 /* bits */ 32, 5390 /* flags */ 0, 5391 }, 5392 #endif /* chips */ 5393 5394 #if defined(BCM_56685_A0) 5395 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56685_A0fmt */ 5396 /* format RSP_WORD_2fmt */ 5397 /* nFields */ 5, 5398 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5399 /* bits */ 32, 5400 /* flags */ 0, 5401 }, 5402 #endif /* chips */ 5403 5404 #if defined(BCM_56685_B0) 5405 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56685_B0fmt */ 5406 /* format RSP_WORD_2fmt */ 5407 /* nFields */ 5, 5408 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5409 /* bits */ 32, 5410 /* flags */ 0, 5411 }, 5412 #endif /* chips */ 5413 5414 #if defined(BCM_56725_A0) 5415 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56725_A0fmt */ 5416 /* format RSP_WORD_2fmt */ 5417 /* nFields */ 4, 5418 /* *fields */ soc_RSP_WORD_2_BCM56820_A0fmt_fields, 5419 /* bits */ 32, 5420 /* flags */ 0, 5421 }, 5422 #endif /* chips */ 5423 5424 #if defined(BCM_56820_A0) 5425 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56820_A0fmt */ 5426 /* format RSP_WORD_2fmt */ 5427 /* nFields */ 4, 5428 /* *fields */ soc_RSP_WORD_2_BCM56820_A0fmt_fields, 5429 /* bits */ 32, 5430 /* flags */ 0, 5431 }, 5432 #endif /* chips */ 5433 5434 #if defined(BCM_56840_A0) 5435 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56840_A0fmt */ 5436 /* format RSP_WORD_2fmt */ 5437 /* nFields */ 5, 5438 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5439 /* bits */ 32, 5440 /* flags */ 0, 5441 }, 5442 #endif /* chips */ 5443 5444 #if defined(BCM_56840_B0) 5445 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM56840_B0fmt */ 5446 /* format RSP_WORD_2fmt */ 5447 /* nFields */ 5, 5448 /* *fields */ soc_RSP_WORD_2_BCM56634_A0fmt_fields, 5449 /* bits */ 32, 5450 /* flags */ 0, 5451 }, 5452 #endif /* chips */ 5453 5454 #if defined(BCM_88732_A0) 5455 { /* SOC_FORMAT_INT_RSP_WORD_2_BCM88732_A0fmt */ 5456 /* format RSP_WORD_2fmt */ 5457 /* nFields */ 2, 5458 /* *fields */ soc_RSP_WORD_2_BCM88732_A0fmt_fields, 5459 /* bits */ 32, 5460 /* flags */ 0, 5461 }, 5462 #endif /* chips */ 5463 5464 #if defined(BCM_56340_A0) 5465 { /* SOC_FORMAT_INT_RSP_WORD_BCM56340_A0fmt */ 5466 /* format RSP_WORDfmt */ 5467 /* nFields */ 4, 5468 /* *fields */ soc_ISM_RSP_WORDfmt_fields, 5469 /* bits */ 32, 5470 /* flags */ 0, 5471 }, 5472 #endif /* chips */ 5473 5474 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5475 defined(BCM_56870_A0) 5476 { /* SOC_FORMAT_INT_RTAG7_HASH_VALUES_DOPfmt */ 5477 /* format RTAG7_HASH_VALUES_DOPfmt */ 5478 /* nFields */ 5, 5479 /* *fields */ soc_RTAG7_HASH_VALUES_DOPfmt_fields, 5480 /* bits */ 64, 5481 /* flags */ 0, 5482 }, 5483 #endif /* chips */ 5484 5485 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 5486 { /* SOC_FORMAT_INT_RTS_INTERRUPTSfmt */ 5487 /* format RTS_INTERRUPTSfmt */ 5488 /* nFields */ 37, 5489 /* *fields */ soc_RTS_INTERRUPTSfmt_fields, 5490 /* bits */ 256, 5491 /* flags */ 0, 5492 }, 5493 #endif /* chips */ 5494 5495 #if defined(BCM_56640_A0) 5496 { /* SOC_FORMAT_INT_RXDP_ASMfmt */ 5497 /* format RXDP_ASMfmt */ 5498 /* nFields */ 13, 5499 /* *fields */ soc_RXDP_ASMfmt_fields, 5500 /* bits */ 504, 5501 /* flags */ 0, 5502 }, 5503 #endif /* chips */ 5504 5505 #if defined(BCM_56640_A0) 5506 { /* SOC_FORMAT_INT_RXDP_LBUSfmt */ 5507 /* format RXDP_LBUSfmt */ 5508 /* nFields */ 8, 5509 /* *fields */ soc_RXDP_LBUSfmt_fields, 5510 /* bits */ 336, 5511 /* flags */ 0, 5512 }, 5513 #endif /* chips */ 5514 5515 #if defined(BCM_56640_A0) 5516 { /* SOC_FORMAT_INT_RXDP_RSP_CW_FMTfmt */ 5517 /* format RXDP_RSP_CW_FMTfmt */ 5518 /* nFields */ 12, 5519 /* *fields */ soc_RXDP_RSP_CW_FMTfmt_fields, 5520 /* bits */ 40, 5521 /* flags */ 0, 5522 }, 5523 #endif /* chips */ 5524 5525 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 5526 defined(BCM_56450_B1) 5527 { /* SOC_FORMAT_INT_RXLP_DEBUG_TRIGGERSfmt */ 5528 /* format RXLP_DEBUG_TRIGGERSfmt */ 5529 /* nFields */ 9, 5530 /* *fields */ soc_RXLP_DEBUG_TRIGGERSfmt_fields, 5531 /* bits */ 9, 5532 /* flags */ 0, 5533 }, 5534 #endif /* chips */ 5535 5536 #if defined(BCM_56260_A0) 5537 { /* SOC_FORMAT_INT_RXLP_DEBUG_TRIGGERS_BCM56260_A0fmt */ 5538 /* format RXLP_DEBUG_TRIGGERSfmt */ 5539 /* nFields */ 9, 5540 /* *fields */ soc_RXLP_DEBUG_TRIGGERS_BCM56260_A0fmt_fields, 5541 /* bits */ 9, 5542 /* flags */ 0, 5543 }, 5544 #endif /* chips */ 5545 5546 #if defined(BCM_56260_B0) 5547 { /* SOC_FORMAT_INT_RXLP_DEBUG_TRIGGERS_BCM56260_B0fmt */ 5548 /* format RXLP_DEBUG_TRIGGERSfmt */ 5549 /* nFields */ 9, 5550 /* *fields */ soc_RXLP_DEBUG_TRIGGERS_BCM56260_A0fmt_fields, 5551 /* bits */ 9, 5552 /* flags */ 0, 5553 }, 5554 #endif /* chips */ 5555 5556 #if defined(BCM_56270_A0) 5557 { /* SOC_FORMAT_INT_RXLP_DEBUG_TRIGGERS_BCM56270_A0fmt */ 5558 /* format RXLP_DEBUG_TRIGGERSfmt */ 5559 /* nFields */ 9, 5560 /* *fields */ soc_RXLP_DEBUG_TRIGGERS_BCM56260_A0fmt_fields, 5561 /* bits */ 9, 5562 /* flags */ 0, 5563 }, 5564 #endif /* chips */ 5565