allformats_p.i (178963B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_p.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56800_A0) 16 { /* SOC_FORMAT_INT_PACKED_SOBMHfmt */ 17 /* format PACKED_SOBMHfmt */ 18 /* nFields */ 8, 19 /* *fields */ soc_PACKED_SOBMHfmt_fields, 20 /* bits */ 32, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_53314_A0) 26 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM53314_A0fmt */ 27 /* format PACKED_SOBMHfmt */ 28 /* nFields */ 9, 29 /* *fields */ soc_PACKED_SOBMH_BCM53314_A0fmt_fields, 30 /* bits */ 34, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_53324_A0) 36 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM53324_A0fmt */ 37 /* format PACKED_SOBMHfmt */ 38 /* nFields */ 9, 39 /* *fields */ soc_PACKED_SOBMH_BCM53314_A0fmt_fields, 40 /* bits */ 34, 41 /* flags */ 0, 42 }, 43 #endif /* chips */ 44 45 #if defined(BCM_56142_A0) 46 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56142_A0fmt */ 47 /* format PACKED_SOBMHfmt */ 48 /* nFields */ 9, 49 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 50 /* bits */ 42, 51 /* flags */ 0, 52 }, 53 #endif /* chips */ 54 55 #if defined(BCM_56224_A0) 56 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56224_A0fmt */ 57 /* format PACKED_SOBMHfmt */ 58 /* nFields */ 8, 59 /* *fields */ soc_PACKED_SOBMH_BCM56224_A0fmt_fields, 60 /* bits */ 33, 61 /* flags */ 0, 62 }, 63 #endif /* chips */ 64 65 #if defined(BCM_56224_B0) 66 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56224_B0fmt */ 67 /* format PACKED_SOBMHfmt */ 68 /* nFields */ 8, 69 /* *fields */ soc_PACKED_SOBMH_BCM56224_A0fmt_fields, 70 /* bits */ 33, 71 /* flags */ 0, 72 }, 73 #endif /* chips */ 74 75 #if defined(BCM_56334_A0) 76 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56334_A0fmt */ 77 /* format PACKED_SOBMHfmt */ 78 /* nFields */ 9, 79 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 80 /* bits */ 42, 81 /* flags */ 0, 82 }, 83 #endif /* chips */ 84 85 #if defined(BCM_56334_B0) 86 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56334_B0fmt */ 87 /* format PACKED_SOBMHfmt */ 88 /* nFields */ 9, 89 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 90 /* bits */ 42, 91 /* flags */ 0, 92 }, 93 #endif /* chips */ 94 95 #if defined(BCM_56440_A0) 96 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56440_A0fmt */ 97 /* format PACKED_SOBMHfmt */ 98 /* nFields */ 20, 99 /* *fields */ soc_PACKED_SOBMH_BCM56440_A0fmt_fields, 100 /* bits */ 81, 101 /* flags */ 0, 102 }, 103 #endif /* chips */ 104 105 #if defined(BCM_56440_B0) 106 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56440_B0fmt */ 107 /* format PACKED_SOBMHfmt */ 108 /* nFields */ 20, 109 /* *fields */ soc_PACKED_SOBMH_BCM56440_A0fmt_fields, 110 /* bits */ 81, 111 /* flags */ 0, 112 }, 113 #endif /* chips */ 114 115 #if defined(BCM_56524_A0) 116 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56524_A0fmt */ 117 /* format PACKED_SOBMHfmt */ 118 /* nFields */ 9, 119 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 120 /* bits */ 42, 121 /* flags */ 0, 122 }, 123 #endif /* chips */ 124 125 #if defined(BCM_56524_B0) 126 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56524_B0fmt */ 127 /* format PACKED_SOBMHfmt */ 128 /* nFields */ 9, 129 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 130 /* bits */ 42, 131 /* flags */ 0, 132 }, 133 #endif /* chips */ 134 135 #if defined(BCM_56624_A0) 136 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56624_A0fmt */ 137 /* format PACKED_SOBMHfmt */ 138 /* nFields */ 8, 139 /* *fields */ soc_PACKED_SOBMH_BCM56624_A0fmt_fields, 140 /* bits */ 41, 141 /* flags */ 0, 142 }, 143 #endif /* chips */ 144 145 #if defined(BCM_56624_B0) 146 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56624_B0fmt */ 147 /* format PACKED_SOBMHfmt */ 148 /* nFields */ 8, 149 /* *fields */ soc_PACKED_SOBMH_BCM56624_A0fmt_fields, 150 /* bits */ 41, 151 /* flags */ 0, 152 }, 153 #endif /* chips */ 154 155 #if defined(BCM_56634_A0) 156 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56634_A0fmt */ 157 /* format PACKED_SOBMHfmt */ 158 /* nFields */ 9, 159 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 160 /* bits */ 42, 161 /* flags */ 0, 162 }, 163 #endif /* chips */ 164 165 #if defined(BCM_56634_B0) 166 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56634_B0fmt */ 167 /* format PACKED_SOBMHfmt */ 168 /* nFields */ 9, 169 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 170 /* bits */ 42, 171 /* flags */ 0, 172 }, 173 #endif /* chips */ 174 175 #if defined(BCM_56680_A0) 176 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56680_A0fmt */ 177 /* format PACKED_SOBMHfmt */ 178 /* nFields */ 8, 179 /* *fields */ soc_PACKED_SOBMH_BCM56624_A0fmt_fields, 180 /* bits */ 41, 181 /* flags */ 0, 182 }, 183 #endif /* chips */ 184 185 #if defined(BCM_56680_B0) 186 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56680_B0fmt */ 187 /* format PACKED_SOBMHfmt */ 188 /* nFields */ 8, 189 /* *fields */ soc_PACKED_SOBMH_BCM56624_A0fmt_fields, 190 /* bits */ 41, 191 /* flags */ 0, 192 }, 193 #endif /* chips */ 194 195 #if defined(BCM_56685_A0) 196 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56685_A0fmt */ 197 /* format PACKED_SOBMHfmt */ 198 /* nFields */ 9, 199 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 200 /* bits */ 42, 201 /* flags */ 0, 202 }, 203 #endif /* chips */ 204 205 #if defined(BCM_56685_B0) 206 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56685_B0fmt */ 207 /* format PACKED_SOBMHfmt */ 208 /* nFields */ 9, 209 /* *fields */ soc_PACKED_SOBMH_BCM56634_A0fmt_fields, 210 /* bits */ 42, 211 /* flags */ 0, 212 }, 213 #endif /* chips */ 214 215 #if defined(BCM_56725_A0) 216 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56725_A0fmt */ 217 /* format PACKED_SOBMHfmt */ 218 /* nFields */ 8, 219 /* *fields */ soc_PACKED_SOBMH_BCM56820_A0fmt_fields, 220 /* bits */ 39, 221 /* flags */ 0, 222 }, 223 #endif /* chips */ 224 225 #if defined(BCM_56820_A0) 226 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56820_A0fmt */ 227 /* format PACKED_SOBMHfmt */ 228 /* nFields */ 8, 229 /* *fields */ soc_PACKED_SOBMH_BCM56820_A0fmt_fields, 230 /* bits */ 39, 231 /* flags */ 0, 232 }, 233 #endif /* chips */ 234 235 #if defined(BCM_56840_A0) 236 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56840_A0fmt */ 237 /* format PACKED_SOBMHfmt */ 238 /* nFields */ 16, 239 /* *fields */ soc_PACKED_SOBMH_BCM56840_A0fmt_fields, 240 /* bits */ 63, 241 /* flags */ 0, 242 }, 243 #endif /* chips */ 244 245 #if defined(BCM_56840_B0) 246 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56840_B0fmt */ 247 /* format PACKED_SOBMHfmt */ 248 /* nFields */ 16, 249 /* *fields */ soc_PACKED_SOBMH_BCM56840_A0fmt_fields, 250 /* bits */ 63, 251 /* flags */ 0, 252 }, 253 #endif /* chips */ 254 255 #if defined(BCM_56850_A0) 256 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56850_A0fmt */ 257 /* format PACKED_SOBMHfmt */ 258 /* nFields */ 16, 259 /* *fields */ soc_PACKED_SOBMH_BCM56850_A0fmt_fields, 260 /* bits */ 63, 261 /* flags */ 0, 262 }, 263 #endif /* chips */ 264 265 #if defined(BCM_56960_A0) 266 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56960_A0fmt */ 267 /* format PACKED_SOBMHfmt */ 268 /* nFields */ 16, 269 /* *fields */ soc_PACKED_SOBMH_BCM56960_A0fmt_fields, 270 /* bits */ 64, 271 /* flags */ 0, 272 }, 273 #endif /* chips */ 274 275 #if defined(BCM_56965_A0) 276 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56965_A0fmt */ 277 /* format PACKED_SOBMHfmt */ 278 /* nFields */ 16, 279 /* *fields */ soc_PACKED_SOBMH_BCM56960_A0fmt_fields, 280 /* bits */ 64, 281 /* flags */ 0, 282 }, 283 #endif /* chips */ 284 285 #if defined(BCM_56980_A0) 286 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56980_A0fmt */ 287 /* format PACKED_SOBMHfmt */ 288 /* nFields */ 8, 289 /* *fields */ soc_PACKED_SOBMH_BCM56980_A0fmt_fields, 290 /* bits */ 39, 291 /* flags */ 0, 292 }, 293 #endif /* chips */ 294 295 #if defined(BCM_56980_B0) 296 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM56980_B0fmt */ 297 /* format PACKED_SOBMHfmt */ 298 /* nFields */ 8, 299 /* *fields */ soc_PACKED_SOBMH_BCM56980_A0fmt_fields, 300 /* bits */ 39, 301 /* flags */ 0, 302 }, 303 #endif /* chips */ 304 305 #if defined(BCM_88732_A0) 306 { /* SOC_FORMAT_INT_PACKED_SOBMH_BCM88732_A0fmt */ 307 /* format PACKED_SOBMHfmt */ 308 /* nFields */ 8, 309 /* *fields */ soc_PACKED_SOBMH_BCM56820_A0fmt_fields, 310 /* bits */ 39, 311 /* flags */ 0, 312 }, 313 #endif /* chips */ 314 315 #if defined(BCM_56504_A0) 316 { /* SOC_FORMAT_INT_PBEfmt */ 317 /* format PBEfmt */ 318 /* nFields */ 45, 319 /* *fields */ soc_PBEfmt_fields, 320 /* bits */ 180, 321 /* flags */ 0, 322 }, 323 #endif /* chips */ 324 325 #if defined(BCM_53314_A0) 326 { /* SOC_FORMAT_INT_PBE_BCM53314_A0fmt */ 327 /* format PBEfmt */ 328 /* nFields */ 35, 329 /* *fields */ soc_PBE_BCM53314_A0fmt_fields, 330 /* bits */ 121, 331 /* flags */ 0, 332 }, 333 #endif /* chips */ 334 335 #if defined(BCM_53324_A0) 336 { /* SOC_FORMAT_INT_PBE_BCM53324_A0fmt */ 337 /* format PBEfmt */ 338 /* nFields */ 35, 339 /* *fields */ soc_PBE_BCM53314_A0fmt_fields, 340 /* bits */ 121, 341 /* flags */ 0, 342 }, 343 #endif /* chips */ 344 345 #if defined(BCM_53400_A0) 346 { /* SOC_FORMAT_INT_PBE_BCM53400_A0fmt */ 347 /* format PBEfmt */ 348 /* nFields */ 100, 349 /* *fields */ soc_PBE_BCM53400_A0fmt_fields, 350 /* bits */ 417, 351 /* flags */ 0, 352 }, 353 #endif /* chips */ 354 355 #if defined(BCM_53540_A0) 356 { /* SOC_FORMAT_INT_PBE_BCM53540_A0fmt */ 357 /* format PBEfmt */ 358 /* nFields */ 104, 359 /* *fields */ soc_PBE_BCM53540_A0fmt_fields, 360 /* bits */ 417, 361 /* flags */ 0, 362 }, 363 #endif /* chips */ 364 365 #if defined(BCM_53570_A0) 366 { /* SOC_FORMAT_INT_PBE_BCM53570_A0fmt */ 367 /* format PBEfmt */ 368 /* nFields */ 127, 369 /* *fields */ soc_PBE_BCM53570_A0fmt_fields, 370 /* bits */ 529, 371 /* flags */ 0, 372 }, 373 #endif /* chips */ 374 375 #if defined(BCM_53570_B0) 376 { /* SOC_FORMAT_INT_PBE_BCM53570_B0fmt */ 377 /* format PBEfmt */ 378 /* nFields */ 130, 379 /* *fields */ soc_PBE_BCM53570_B0fmt_fields, 380 /* bits */ 529, 381 /* flags */ 0, 382 }, 383 #endif /* chips */ 384 385 #if defined(BCM_56142_A0) 386 { /* SOC_FORMAT_INT_PBE_BCM56142_A0fmt */ 387 /* format PBEfmt */ 388 /* nFields */ 75, 389 /* *fields */ soc_PBE_BCM56142_A0fmt_fields, 390 /* bits */ 358, 391 /* flags */ 0, 392 }, 393 #endif /* chips */ 394 395 #if defined(BCM_56150_A0) 396 { /* SOC_FORMAT_INT_PBE_BCM56150_A0fmt */ 397 /* format PBEfmt */ 398 /* nFields */ 92, 399 /* *fields */ soc_PBE_BCM56150_A0fmt_fields, 400 /* bits */ 405, 401 /* flags */ 0, 402 }, 403 #endif /* chips */ 404 405 #if defined(BCM_56160_A0) 406 { /* SOC_FORMAT_INT_PBE_BCM56160_A0fmt */ 407 /* format PBEfmt */ 408 /* nFields */ 103, 409 /* *fields */ soc_PBE_BCM56160_A0fmt_fields, 410 /* bits */ 417, 411 /* flags */ 0, 412 }, 413 #endif /* chips */ 414 415 #if defined(BCM_56224_A0) 416 { /* SOC_FORMAT_INT_PBE_BCM56224_A0fmt */ 417 /* format PBEfmt */ 418 /* nFields */ 51, 419 /* *fields */ soc_PBE_BCM56224_A0fmt_fields, 420 /* bits */ 244, 421 /* flags */ 0, 422 }, 423 #endif /* chips */ 424 425 #if defined(BCM_56224_B0) 426 { /* SOC_FORMAT_INT_PBE_BCM56224_B0fmt */ 427 /* format PBEfmt */ 428 /* nFields */ 51, 429 /* *fields */ soc_PBE_BCM56224_A0fmt_fields, 430 /* bits */ 244, 431 /* flags */ 0, 432 }, 433 #endif /* chips */ 434 435 #if defined(BCM_56260_A0) 436 { /* SOC_FORMAT_INT_PBE_BCM56260_A0fmt */ 437 /* format PBEfmt */ 438 /* nFields */ 2, 439 /* *fields */ soc_PBE_BCM56260_A0fmt_fields, 440 /* bits */ 849, 441 /* flags */ 0, 442 }, 443 #endif /* chips */ 444 445 #if defined(BCM_56260_B0) 446 { /* SOC_FORMAT_INT_PBE_BCM56260_B0fmt */ 447 /* format PBEfmt */ 448 /* nFields */ 2, 449 /* *fields */ soc_PBE_BCM56260_A0fmt_fields, 450 /* bits */ 849, 451 /* flags */ 0, 452 }, 453 #endif /* chips */ 454 455 #if defined(BCM_56270_A0) 456 { /* SOC_FORMAT_INT_PBE_BCM56270_A0fmt */ 457 /* format PBEfmt */ 458 /* nFields */ 2, 459 /* *fields */ soc_PBE_BCM56260_A0fmt_fields, 460 /* bits */ 849, 461 /* flags */ 0, 462 }, 463 #endif /* chips */ 464 465 #if defined(BCM_56314_A0) 466 { /* SOC_FORMAT_INT_PBE_BCM56314_A0fmt */ 467 /* format PBEfmt */ 468 /* nFields */ 52, 469 /* *fields */ soc_PBE_BCM56504_B0fmt_fields, 470 /* bits */ 211, 471 /* flags */ 0, 472 }, 473 #endif /* chips */ 474 475 #if defined(BCM_56334_A0) 476 { /* SOC_FORMAT_INT_PBE_BCM56334_A0fmt */ 477 /* format PBEfmt */ 478 /* nFields */ 89, 479 /* *fields */ soc_PBE_BCM56334_A0fmt_fields, 480 /* bits */ 373, 481 /* flags */ 0, 482 }, 483 #endif /* chips */ 484 485 #if defined(BCM_56334_B0) 486 { /* SOC_FORMAT_INT_PBE_BCM56334_B0fmt */ 487 /* format PBEfmt */ 488 /* nFields */ 89, 489 /* *fields */ soc_PBE_BCM56334_A0fmt_fields, 490 /* bits */ 373, 491 /* flags */ 0, 492 }, 493 #endif /* chips */ 494 495 #if defined(BCM_56340_A0) 496 { /* SOC_FORMAT_INT_PBE_BCM56340_A0fmt */ 497 /* format PBEfmt */ 498 /* nFields */ 2, 499 /* *fields */ soc_PBE_BCM56640_A0fmt_fields, 500 /* bits */ 821, 501 /* flags */ 0, 502 }, 503 #endif /* chips */ 504 505 #if defined(BCM_56370_A0) 506 { /* SOC_FORMAT_INT_PBE_BCM56370_A0fmt */ 507 /* format PBEfmt */ 508 /* nFields */ 2, 509 /* *fields */ soc_PBE_BCM56960_A0fmt_fields, 510 /* bits */ 613, 511 /* flags */ 0, 512 }, 513 #endif /* chips */ 514 515 #if defined(BCM_56440_A0) 516 { /* SOC_FORMAT_INT_PBE_BCM56440_A0fmt */ 517 /* format PBEfmt */ 518 /* nFields */ 2, 519 /* *fields */ soc_PBE_BCM56440_A0fmt_fields, 520 /* bits */ 509, 521 /* flags */ 0, 522 }, 523 #endif /* chips */ 524 525 #if defined(BCM_56440_B0) 526 { /* SOC_FORMAT_INT_PBE_BCM56440_B0fmt */ 527 /* format PBEfmt */ 528 /* nFields */ 2, 529 /* *fields */ soc_PBE_BCM56440_A0fmt_fields, 530 /* bits */ 509, 531 /* flags */ 0, 532 }, 533 #endif /* chips */ 534 535 #if defined(BCM_56450_A0) 536 { /* SOC_FORMAT_INT_PBE_BCM56450_A0fmt */ 537 /* format PBEfmt */ 538 /* nFields */ 2, 539 /* *fields */ soc_PBE_BCM56450_A0fmt_fields, 540 /* bits */ 849, 541 /* flags */ 0, 542 }, 543 #endif /* chips */ 544 545 #if defined(BCM_56450_B0) 546 { /* SOC_FORMAT_INT_PBE_BCM56450_B0fmt */ 547 /* format PBEfmt */ 548 /* nFields */ 2, 549 /* *fields */ soc_PBE_BCM56450_A0fmt_fields, 550 /* bits */ 849, 551 /* flags */ 0, 552 }, 553 #endif /* chips */ 554 555 #if defined(BCM_56450_B1) 556 { /* SOC_FORMAT_INT_PBE_BCM56450_B1fmt */ 557 /* format PBEfmt */ 558 /* nFields */ 2, 559 /* *fields */ soc_PBE_BCM56450_A0fmt_fields, 560 /* bits */ 849, 561 /* flags */ 0, 562 }, 563 #endif /* chips */ 564 565 #if defined(BCM_56504_B0) 566 { /* SOC_FORMAT_INT_PBE_BCM56504_B0fmt */ 567 /* format PBEfmt */ 568 /* nFields */ 52, 569 /* *fields */ soc_PBE_BCM56504_B0fmt_fields, 570 /* bits */ 211, 571 /* flags */ 0, 572 }, 573 #endif /* chips */ 574 575 #if defined(BCM_56514_A0) 576 { /* SOC_FORMAT_INT_PBE_BCM56514_A0fmt */ 577 /* format PBEfmt */ 578 /* nFields */ 52, 579 /* *fields */ soc_PBE_BCM56504_B0fmt_fields, 580 /* bits */ 211, 581 /* flags */ 0, 582 }, 583 #endif /* chips */ 584 585 #if defined(BCM_56524_A0) 586 { /* SOC_FORMAT_INT_PBE_BCM56524_A0fmt */ 587 /* format PBEfmt */ 588 /* nFields */ 110, 589 /* *fields */ soc_PBE_BCM56634_A0fmt_fields, 590 /* bits */ 512, 591 /* flags */ 0, 592 }, 593 #endif /* chips */ 594 595 #if defined(BCM_56524_B0) 596 { /* SOC_FORMAT_INT_PBE_BCM56524_B0fmt */ 597 /* format PBEfmt */ 598 /* nFields */ 110, 599 /* *fields */ soc_PBE_BCM56634_A0fmt_fields, 600 /* bits */ 512, 601 /* flags */ 0, 602 }, 603 #endif /* chips */ 604 605 #if defined(BCM_56560_A0) 606 { /* SOC_FORMAT_INT_PBE_BCM56560_A0fmt */ 607 /* format PBEfmt */ 608 /* nFields */ 2, 609 /* *fields */ soc_PBE_BCM56560_A0fmt_fields, 610 /* bits */ 712, 611 /* flags */ 0, 612 }, 613 #endif /* chips */ 614 615 #if defined(BCM_56560_B0) 616 { /* SOC_FORMAT_INT_PBE_BCM56560_B0fmt */ 617 /* format PBEfmt */ 618 /* nFields */ 2, 619 /* *fields */ soc_PBE_BCM56560_A0fmt_fields, 620 /* bits */ 712, 621 /* flags */ 0, 622 }, 623 #endif /* chips */ 624 625 #if defined(BCM_56624_A0) 626 { /* SOC_FORMAT_INT_PBE_BCM56624_A0fmt */ 627 /* format PBEfmt */ 628 /* nFields */ 75, 629 /* *fields */ soc_PBE_BCM56624_A0fmt_fields, 630 /* bits */ 337, 631 /* flags */ 0, 632 }, 633 #endif /* chips */ 634 635 #if defined(BCM_56624_B0) 636 { /* SOC_FORMAT_INT_PBE_BCM56624_B0fmt */ 637 /* format PBEfmt */ 638 /* nFields */ 75, 639 /* *fields */ soc_PBE_BCM56624_A0fmt_fields, 640 /* bits */ 337, 641 /* flags */ 0, 642 }, 643 #endif /* chips */ 644 645 #if defined(BCM_56634_A0) 646 { /* SOC_FORMAT_INT_PBE_BCM56634_A0fmt */ 647 /* format PBEfmt */ 648 /* nFields */ 110, 649 /* *fields */ soc_PBE_BCM56634_A0fmt_fields, 650 /* bits */ 512, 651 /* flags */ 0, 652 }, 653 #endif /* chips */ 654 655 #if defined(BCM_56634_B0) 656 { /* SOC_FORMAT_INT_PBE_BCM56634_B0fmt */ 657 /* format PBEfmt */ 658 /* nFields */ 110, 659 /* *fields */ soc_PBE_BCM56634_A0fmt_fields, 660 /* bits */ 512, 661 /* flags */ 0, 662 }, 663 #endif /* chips */ 664 665 #if defined(BCM_56640_A0) 666 { /* SOC_FORMAT_INT_PBE_BCM56640_A0fmt */ 667 /* format PBEfmt */ 668 /* nFields */ 2, 669 /* *fields */ soc_PBE_BCM56640_A0fmt_fields, 670 /* bits */ 821, 671 /* flags */ 0, 672 }, 673 #endif /* chips */ 674 675 #if defined(BCM_56670_A0) 676 { /* SOC_FORMAT_INT_PBE_BCM56670_A0fmt */ 677 /* format PBEfmt */ 678 /* nFields */ 2, 679 /* *fields */ soc_PBE_BCM56560_A0fmt_fields, 680 /* bits */ 712, 681 /* flags */ 0, 682 }, 683 #endif /* chips */ 684 685 #if defined(BCM_56670_B0) 686 { /* SOC_FORMAT_INT_PBE_BCM56670_B0fmt */ 687 /* format PBEfmt */ 688 /* nFields */ 2, 689 /* *fields */ soc_PBE_BCM56560_A0fmt_fields, 690 /* bits */ 712, 691 /* flags */ 0, 692 }, 693 #endif /* chips */ 694 695 #if defined(BCM_56680_A0) 696 { /* SOC_FORMAT_INT_PBE_BCM56680_A0fmt */ 697 /* format PBEfmt */ 698 /* nFields */ 75, 699 /* *fields */ soc_PBE_BCM56624_A0fmt_fields, 700 /* bits */ 337, 701 /* flags */ 0, 702 }, 703 #endif /* chips */ 704 705 #if defined(BCM_56680_B0) 706 { /* SOC_FORMAT_INT_PBE_BCM56680_B0fmt */ 707 /* format PBEfmt */ 708 /* nFields */ 75, 709 /* *fields */ soc_PBE_BCM56624_A0fmt_fields, 710 /* bits */ 337, 711 /* flags */ 0, 712 }, 713 #endif /* chips */ 714 715 #if defined(BCM_56685_A0) 716 { /* SOC_FORMAT_INT_PBE_BCM56685_A0fmt */ 717 /* format PBEfmt */ 718 /* nFields */ 110, 719 /* *fields */ soc_PBE_BCM56634_A0fmt_fields, 720 /* bits */ 512, 721 /* flags */ 0, 722 }, 723 #endif /* chips */ 724 725 #if defined(BCM_56685_B0) 726 { /* SOC_FORMAT_INT_PBE_BCM56685_B0fmt */ 727 /* format PBEfmt */ 728 /* nFields */ 110, 729 /* *fields */ soc_PBE_BCM56634_A0fmt_fields, 730 /* bits */ 512, 731 /* flags */ 0, 732 }, 733 #endif /* chips */ 734 735 #if defined(BCM_56725_A0) 736 { /* SOC_FORMAT_INT_PBE_BCM56725_A0fmt */ 737 /* format PBEfmt */ 738 /* nFields */ 61, 739 /* *fields */ soc_PBE_BCM56820_A0fmt_fields, 740 /* bits */ 287, 741 /* flags */ 0, 742 }, 743 #endif /* chips */ 744 745 #if defined(BCM_56770_A0) 746 { /* SOC_FORMAT_INT_PBE_BCM56770_A0fmt */ 747 /* format PBEfmt */ 748 /* nFields */ 2, 749 /* *fields */ soc_PBE_BCM56870_A0fmt_fields, 750 /* bits */ 617, 751 /* flags */ 0, 752 }, 753 #endif /* chips */ 754 755 #if defined(BCM_56800_A0) 756 { /* SOC_FORMAT_INT_PBE_BCM56800_A0fmt */ 757 /* format PBEfmt */ 758 /* nFields */ 53, 759 /* *fields */ soc_PBE_BCM56800_A0fmt_fields, 760 /* bits */ 253, 761 /* flags */ 0, 762 }, 763 #endif /* chips */ 764 765 #if defined(BCM_56820_A0) 766 { /* SOC_FORMAT_INT_PBE_BCM56820_A0fmt */ 767 /* format PBEfmt */ 768 /* nFields */ 61, 769 /* *fields */ soc_PBE_BCM56820_A0fmt_fields, 770 /* bits */ 287, 771 /* flags */ 0, 772 }, 773 #endif /* chips */ 774 775 #if defined(BCM_56840_A0) 776 { /* SOC_FORMAT_INT_PBE_BCM56840_A0fmt */ 777 /* format PBEfmt */ 778 /* nFields */ 2, 779 /* *fields */ soc_PBE_BCM56840_A0fmt_fields, 780 /* bits */ 618, 781 /* flags */ 0, 782 }, 783 #endif /* chips */ 784 785 #if defined(BCM_56840_B0) 786 { /* SOC_FORMAT_INT_PBE_BCM56840_B0fmt */ 787 /* format PBEfmt */ 788 /* nFields */ 2, 789 /* *fields */ soc_PBE_BCM56840_A0fmt_fields, 790 /* bits */ 618, 791 /* flags */ 0, 792 }, 793 #endif /* chips */ 794 795 #if defined(BCM_56850_A0) 796 { /* SOC_FORMAT_INT_PBE_BCM56850_A0fmt */ 797 /* format PBEfmt */ 798 /* nFields */ 2, 799 /* *fields */ soc_PBE_BCM56850_A0fmt_fields, 800 /* bits */ 693, 801 /* flags */ 0, 802 }, 803 #endif /* chips */ 804 805 #if defined(BCM_56860_A0) 806 { /* SOC_FORMAT_INT_PBE_BCM56860_A0fmt */ 807 /* format PBEfmt */ 808 /* nFields */ 2, 809 /* *fields */ soc_PBE_BCM56860_A0fmt_fields, 810 /* bits */ 699, 811 /* flags */ 0, 812 }, 813 #endif /* chips */ 814 815 #if defined(BCM_56870_A0) 816 { /* SOC_FORMAT_INT_PBE_BCM56870_A0fmt */ 817 /* format PBEfmt */ 818 /* nFields */ 2, 819 /* *fields */ soc_PBE_BCM56870_A0fmt_fields, 820 /* bits */ 617, 821 /* flags */ 0, 822 }, 823 #endif /* chips */ 824 825 #if defined(BCM_56960_A0) 826 { /* SOC_FORMAT_INT_PBE_BCM56960_A0fmt */ 827 /* format PBEfmt */ 828 /* nFields */ 2, 829 /* *fields */ soc_PBE_BCM56960_A0fmt_fields, 830 /* bits */ 613, 831 /* flags */ 0, 832 }, 833 #endif /* chips */ 834 835 #if defined(BCM_56965_A0) 836 { /* SOC_FORMAT_INT_PBE_BCM56965_A0fmt */ 837 /* format PBEfmt */ 838 /* nFields */ 2, 839 /* *fields */ soc_PBE_BCM56960_A0fmt_fields, 840 /* bits */ 613, 841 /* flags */ 0, 842 }, 843 #endif /* chips */ 844 845 #if defined(BCM_56970_A0) 846 { /* SOC_FORMAT_INT_PBE_BCM56970_A0fmt */ 847 /* format PBEfmt */ 848 /* nFields */ 2, 849 /* *fields */ soc_PBE_BCM56970_A0fmt_fields, 850 /* bits */ 619, 851 /* flags */ 0, 852 }, 853 #endif /* chips */ 854 855 #if defined(BCM_56980_A0) 856 { /* SOC_FORMAT_INT_PBE_BCM56980_A0fmt */ 857 /* format PBEfmt */ 858 /* nFields */ 2, 859 /* *fields */ soc_PBE_BCM56980_A0fmt_fields, 860 /* bits */ 413, 861 /* flags */ 0, 862 }, 863 #endif /* chips */ 864 865 #if defined(BCM_56980_B0) 866 { /* SOC_FORMAT_INT_PBE_BCM56980_B0fmt */ 867 /* format PBEfmt */ 868 /* nFields */ 2, 869 /* *fields */ soc_PBE_BCM56980_A0fmt_fields, 870 /* bits */ 413, 871 /* flags */ 0, 872 }, 873 #endif /* chips */ 874 875 #if defined(BCM_88732_A0) 876 { /* SOC_FORMAT_INT_PBE_BCM88732_A0fmt */ 877 /* format PBEfmt */ 878 /* nFields */ 80, 879 /* *fields */ soc_PBE_BCM88732_A0fmt_fields, 880 /* bits */ 251, 881 /* flags */ 0, 882 }, 883 #endif /* chips */ 884 885 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 886 { /* SOC_FORMAT_INT_PBE_POINTERSfmt */ 887 /* format PBE_POINTERSfmt */ 888 /* nFields */ 9, 889 /* *fields */ soc_PBE_POINTERSfmt_fields, 890 /* bits */ 109, 891 /* flags */ 0, 892 }, 893 #endif /* chips */ 894 895 #if defined(BCM_56370_A0) 896 { /* SOC_FORMAT_INT_PBE_POINTERS_BCM56370_A0fmt */ 897 /* format PBE_POINTERSfmt */ 898 /* nFields */ 14, 899 /* *fields */ soc_PBE_POINTERS_BCM56370_A0fmt_fields, 900 /* bits */ 109, 901 /* flags */ 0, 902 }, 903 #endif /* chips */ 904 905 #if defined(BCM_56504_A0) 906 { /* SOC_FORMAT_INT_PBIfmt */ 907 /* format PBIfmt */ 908 /* nFields */ 45, 909 /* *fields */ soc_PBIfmt_fields, 910 /* bits */ 229, 911 /* flags */ 0, 912 }, 913 #endif /* chips */ 914 915 #if defined(BCM_53314_A0) 916 { /* SOC_FORMAT_INT_PBI_BCM53314_A0fmt */ 917 /* format PBIfmt */ 918 /* nFields */ 36, 919 /* *fields */ soc_PBI_BCM53314_A0fmt_fields, 920 /* bits */ 151, 921 /* flags */ 0, 922 }, 923 #endif /* chips */ 924 925 #if defined(BCM_53324_A0) 926 { /* SOC_FORMAT_INT_PBI_BCM53324_A0fmt */ 927 /* format PBIfmt */ 928 /* nFields */ 36, 929 /* *fields */ soc_PBI_BCM53314_A0fmt_fields, 930 /* bits */ 151, 931 /* flags */ 0, 932 }, 933 #endif /* chips */ 934 935 #if defined(BCM_53400_A0) 936 { /* SOC_FORMAT_INT_PBI_BCM53400_A0fmt */ 937 /* format PBIfmt */ 938 /* nFields */ 91, 939 /* *fields */ soc_PBI_BCM53400_A0fmt_fields, 940 /* bits */ 449, 941 /* flags */ 0, 942 }, 943 #endif /* chips */ 944 945 #if defined(BCM_53540_A0) 946 { /* SOC_FORMAT_INT_PBI_BCM53540_A0fmt */ 947 /* format PBIfmt */ 948 /* nFields */ 97, 949 /* *fields */ soc_PBI_BCM53540_A0fmt_fields, 950 /* bits */ 454, 951 /* flags */ 0, 952 }, 953 #endif /* chips */ 954 955 #if defined(BCM_53570_A0) 956 { /* SOC_FORMAT_INT_PBI_BCM53570_A0fmt */ 957 /* format PBIfmt */ 958 /* nFields */ 122, 959 /* *fields */ soc_PBI_BCM53570_A0fmt_fields, 960 /* bits */ 637, 961 /* flags */ 0, 962 }, 963 #endif /* chips */ 964 965 #if defined(BCM_53570_B0) 966 { /* SOC_FORMAT_INT_PBI_BCM53570_B0fmt */ 967 /* format PBIfmt */ 968 /* nFields */ 125, 969 /* *fields */ soc_PBI_BCM53570_B0fmt_fields, 970 /* bits */ 637, 971 /* flags */ 0, 972 }, 973 #endif /* chips */ 974 975 #if defined(BCM_56142_A0) 976 { /* SOC_FORMAT_INT_PBI_BCM56142_A0fmt */ 977 /* format PBIfmt */ 978 /* nFields */ 71, 979 /* *fields */ soc_PBI_BCM56142_A0fmt_fields, 980 /* bits */ 462, 981 /* flags */ 0, 982 }, 983 #endif /* chips */ 984 985 #if defined(BCM_56150_A0) 986 { /* SOC_FORMAT_INT_PBI_BCM56150_A0fmt */ 987 /* format PBIfmt */ 988 /* nFields */ 83, 989 /* *fields */ soc_PBI_BCM56150_A0fmt_fields, 990 /* bits */ 434, 991 /* flags */ 0, 992 }, 993 #endif /* chips */ 994 995 #if defined(BCM_56160_A0) 996 { /* SOC_FORMAT_INT_PBI_BCM56160_A0fmt */ 997 /* format PBIfmt */ 998 /* nFields */ 97, 999 /* *fields */ soc_PBI_BCM56160_A0fmt_fields, 1000 /* bits */ 454, 1001 /* flags */ 0, 1002 }, 1003 #endif /* chips */ 1004 1005 #if defined(BCM_56224_A0) 1006 { /* SOC_FORMAT_INT_PBI_BCM56224_A0fmt */ 1007 /* format PBIfmt */ 1008 /* nFields */ 50, 1009 /* *fields */ soc_PBI_BCM56224_A0fmt_fields, 1010 /* bits */ 295, 1011 /* flags */ 0, 1012 }, 1013 #endif /* chips */ 1014 1015 #if defined(BCM_56224_B0) 1016 { /* SOC_FORMAT_INT_PBI_BCM56224_B0fmt */ 1017 /* format PBIfmt */ 1018 /* nFields */ 50, 1019 /* *fields */ soc_PBI_BCM56224_A0fmt_fields, 1020 /* bits */ 295, 1021 /* flags */ 0, 1022 }, 1023 #endif /* chips */ 1024 1025 #if defined(BCM_56260_A0) 1026 { /* SOC_FORMAT_INT_PBI_BCM56260_A0fmt */ 1027 /* format PBIfmt */ 1028 /* nFields */ 2, 1029 /* *fields */ soc_PBI_BCM56260_A0fmt_fields, 1030 /* bits */ 908, 1031 /* flags */ 0, 1032 }, 1033 #endif /* chips */ 1034 1035 #if defined(BCM_56260_B0) 1036 { /* SOC_FORMAT_INT_PBI_BCM56260_B0fmt */ 1037 /* format PBIfmt */ 1038 /* nFields */ 2, 1039 /* *fields */ soc_PBI_BCM56260_A0fmt_fields, 1040 /* bits */ 908, 1041 /* flags */ 0, 1042 }, 1043 #endif /* chips */ 1044 1045 #if defined(BCM_56270_A0) 1046 { /* SOC_FORMAT_INT_PBI_BCM56270_A0fmt */ 1047 /* format PBIfmt */ 1048 /* nFields */ 2, 1049 /* *fields */ soc_PBI_BCM56270_A0fmt_fields, 1050 /* bits */ 755, 1051 /* flags */ 0, 1052 }, 1053 #endif /* chips */ 1054 1055 #if defined(BCM_56314_A0) 1056 { /* SOC_FORMAT_INT_PBI_BCM56314_A0fmt */ 1057 /* format PBIfmt */ 1058 /* nFields */ 52, 1059 /* *fields */ soc_PBI_BCM56504_B0fmt_fields, 1060 /* bits */ 260, 1061 /* flags */ 0, 1062 }, 1063 #endif /* chips */ 1064 1065 #if defined(BCM_56334_A0) 1066 { /* SOC_FORMAT_INT_PBI_BCM56334_A0fmt */ 1067 /* format PBIfmt */ 1068 /* nFields */ 100, 1069 /* *fields */ soc_PBI_BCM56334_A0fmt_fields, 1070 /* bits */ 550, 1071 /* flags */ 0, 1072 }, 1073 #endif /* chips */ 1074 1075 #if defined(BCM_56334_B0) 1076 { /* SOC_FORMAT_INT_PBI_BCM56334_B0fmt */ 1077 /* format PBIfmt */ 1078 /* nFields */ 100, 1079 /* *fields */ soc_PBI_BCM56334_A0fmt_fields, 1080 /* bits */ 550, 1081 /* flags */ 0, 1082 }, 1083 #endif /* chips */ 1084 1085 #if defined(BCM_56340_A0) 1086 { /* SOC_FORMAT_INT_PBI_BCM56340_A0fmt */ 1087 /* format PBIfmt */ 1088 /* nFields */ 2, 1089 /* *fields */ soc_PBI_BCM56640_A0fmt_fields, 1090 /* bits */ 822, 1091 /* flags */ 0, 1092 }, 1093 #endif /* chips */ 1094 1095 #if defined(BCM_56370_A0) 1096 { /* SOC_FORMAT_INT_PBI_BCM56370_A0fmt */ 1097 /* format PBIfmt */ 1098 /* nFields */ 2, 1099 /* *fields */ soc_PBI_BCM56870_A0fmt_fields, 1100 /* bits */ 976, 1101 /* flags */ 0, 1102 }, 1103 #endif /* chips */ 1104 1105 #if defined(BCM_56440_A0) 1106 { /* SOC_FORMAT_INT_PBI_BCM56440_A0fmt */ 1107 /* format PBIfmt */ 1108 /* nFields */ 2, 1109 /* *fields */ soc_PBI_BCM56440_A0fmt_fields, 1110 /* bits */ 623, 1111 /* flags */ 0, 1112 }, 1113 #endif /* chips */ 1114 1115 #if defined(BCM_56440_B0) 1116 { /* SOC_FORMAT_INT_PBI_BCM56440_B0fmt */ 1117 /* format PBIfmt */ 1118 /* nFields */ 2, 1119 /* *fields */ soc_PBI_BCM56440_A0fmt_fields, 1120 /* bits */ 623, 1121 /* flags */ 0, 1122 }, 1123 #endif /* chips */ 1124 1125 #if defined(BCM_56450_A0) 1126 { /* SOC_FORMAT_INT_PBI_BCM56450_A0fmt */ 1127 /* format PBIfmt */ 1128 /* nFields */ 2, 1129 /* *fields */ soc_PBI_BCM56450_A0fmt_fields, 1130 /* bits */ 1059, 1131 /* flags */ 0, 1132 }, 1133 #endif /* chips */ 1134 1135 #if defined(BCM_56450_B0) 1136 { /* SOC_FORMAT_INT_PBI_BCM56450_B0fmt */ 1137 /* format PBIfmt */ 1138 /* nFields */ 2, 1139 /* *fields */ soc_PBI_BCM56450_A0fmt_fields, 1140 /* bits */ 1059, 1141 /* flags */ 0, 1142 }, 1143 #endif /* chips */ 1144 1145 #if defined(BCM_56450_B1) 1146 { /* SOC_FORMAT_INT_PBI_BCM56450_B1fmt */ 1147 /* format PBIfmt */ 1148 /* nFields */ 2, 1149 /* *fields */ soc_PBI_BCM56450_A0fmt_fields, 1150 /* bits */ 1059, 1151 /* flags */ 0, 1152 }, 1153 #endif /* chips */ 1154 1155 #if defined(BCM_56504_B0) 1156 { /* SOC_FORMAT_INT_PBI_BCM56504_B0fmt */ 1157 /* format PBIfmt */ 1158 /* nFields */ 52, 1159 /* *fields */ soc_PBI_BCM56504_B0fmt_fields, 1160 /* bits */ 260, 1161 /* flags */ 0, 1162 }, 1163 #endif /* chips */ 1164 1165 #if defined(BCM_56514_A0) 1166 { /* SOC_FORMAT_INT_PBI_BCM56514_A0fmt */ 1167 /* format PBIfmt */ 1168 /* nFields */ 52, 1169 /* *fields */ soc_PBI_BCM56504_B0fmt_fields, 1170 /* bits */ 260, 1171 /* flags */ 0, 1172 }, 1173 #endif /* chips */ 1174 1175 #if defined(BCM_56524_A0) 1176 { /* SOC_FORMAT_INT_PBI_BCM56524_A0fmt */ 1177 /* format PBIfmt */ 1178 /* nFields */ 107, 1179 /* *fields */ soc_PBI_BCM56634_A0fmt_fields, 1180 /* bits */ 597, 1181 /* flags */ 0, 1182 }, 1183 #endif /* chips */ 1184 1185 #if defined(BCM_56524_B0) 1186 { /* SOC_FORMAT_INT_PBI_BCM56524_B0fmt */ 1187 /* format PBIfmt */ 1188 /* nFields */ 107, 1189 /* *fields */ soc_PBI_BCM56634_A0fmt_fields, 1190 /* bits */ 597, 1191 /* flags */ 0, 1192 }, 1193 #endif /* chips */ 1194 1195 #if defined(BCM_56560_A0) 1196 { /* SOC_FORMAT_INT_PBI_BCM56560_A0fmt */ 1197 /* format PBIfmt */ 1198 /* nFields */ 2, 1199 /* *fields */ soc_PBI_BCM56560_A0fmt_fields, 1200 /* bits */ 1018, 1201 /* flags */ 0, 1202 }, 1203 #endif /* chips */ 1204 1205 #if defined(BCM_56560_B0) 1206 { /* SOC_FORMAT_INT_PBI_BCM56560_B0fmt */ 1207 /* format PBIfmt */ 1208 /* nFields */ 2, 1209 /* *fields */ soc_PBI_BCM56560_A0fmt_fields, 1210 /* bits */ 1018, 1211 /* flags */ 0, 1212 }, 1213 #endif /* chips */ 1214 1215 #if defined(BCM_56624_A0) 1216 { /* SOC_FORMAT_INT_PBI_BCM56624_A0fmt */ 1217 /* format PBIfmt */ 1218 /* nFields */ 83, 1219 /* *fields */ soc_PBI_BCM56624_A0fmt_fields, 1220 /* bits */ 514, 1221 /* flags */ 0, 1222 }, 1223 #endif /* chips */ 1224 1225 #if defined(BCM_56624_B0) 1226 { /* SOC_FORMAT_INT_PBI_BCM56624_B0fmt */ 1227 /* format PBIfmt */ 1228 /* nFields */ 83, 1229 /* *fields */ soc_PBI_BCM56624_A0fmt_fields, 1230 /* bits */ 514, 1231 /* flags */ 0, 1232 }, 1233 #endif /* chips */ 1234 1235 #if defined(BCM_56634_A0) 1236 { /* SOC_FORMAT_INT_PBI_BCM56634_A0fmt */ 1237 /* format PBIfmt */ 1238 /* nFields */ 107, 1239 /* *fields */ soc_PBI_BCM56634_A0fmt_fields, 1240 /* bits */ 597, 1241 /* flags */ 0, 1242 }, 1243 #endif /* chips */ 1244 1245 #if defined(BCM_56634_B0) 1246 { /* SOC_FORMAT_INT_PBI_BCM56634_B0fmt */ 1247 /* format PBIfmt */ 1248 /* nFields */ 107, 1249 /* *fields */ soc_PBI_BCM56634_A0fmt_fields, 1250 /* bits */ 597, 1251 /* flags */ 0, 1252 }, 1253 #endif /* chips */ 1254 1255 #if defined(BCM_56640_A0) 1256 { /* SOC_FORMAT_INT_PBI_BCM56640_A0fmt */ 1257 /* format PBIfmt */ 1258 /* nFields */ 2, 1259 /* *fields */ soc_PBI_BCM56640_A0fmt_fields, 1260 /* bits */ 822, 1261 /* flags */ 0, 1262 }, 1263 #endif /* chips */ 1264 1265 #if defined(BCM_56670_A0) 1266 { /* SOC_FORMAT_INT_PBI_BCM56670_A0fmt */ 1267 /* format PBIfmt */ 1268 /* nFields */ 2, 1269 /* *fields */ soc_PBI_BCM56670_A0fmt_fields, 1270 /* bits */ 892, 1271 /* flags */ 0, 1272 }, 1273 #endif /* chips */ 1274 1275 #if defined(BCM_56670_B0) 1276 { /* SOC_FORMAT_INT_PBI_BCM56670_B0fmt */ 1277 /* format PBIfmt */ 1278 /* nFields */ 2, 1279 /* *fields */ soc_PBI_BCM56670_A0fmt_fields, 1280 /* bits */ 892, 1281 /* flags */ 0, 1282 }, 1283 #endif /* chips */ 1284 1285 #if defined(BCM_56680_A0) 1286 { /* SOC_FORMAT_INT_PBI_BCM56680_A0fmt */ 1287 /* format PBIfmt */ 1288 /* nFields */ 83, 1289 /* *fields */ soc_PBI_BCM56624_A0fmt_fields, 1290 /* bits */ 514, 1291 /* flags */ 0, 1292 }, 1293 #endif /* chips */ 1294 1295 #if defined(BCM_56680_B0) 1296 { /* SOC_FORMAT_INT_PBI_BCM56680_B0fmt */ 1297 /* format PBIfmt */ 1298 /* nFields */ 83, 1299 /* *fields */ soc_PBI_BCM56624_A0fmt_fields, 1300 /* bits */ 514, 1301 /* flags */ 0, 1302 }, 1303 #endif /* chips */ 1304 1305 #if defined(BCM_56685_A0) 1306 { /* SOC_FORMAT_INT_PBI_BCM56685_A0fmt */ 1307 /* format PBIfmt */ 1308 /* nFields */ 107, 1309 /* *fields */ soc_PBI_BCM56634_A0fmt_fields, 1310 /* bits */ 597, 1311 /* flags */ 0, 1312 }, 1313 #endif /* chips */ 1314 1315 #if defined(BCM_56685_B0) 1316 { /* SOC_FORMAT_INT_PBI_BCM56685_B0fmt */ 1317 /* format PBIfmt */ 1318 /* nFields */ 107, 1319 /* *fields */ soc_PBI_BCM56634_A0fmt_fields, 1320 /* bits */ 597, 1321 /* flags */ 0, 1322 }, 1323 #endif /* chips */ 1324 1325 #if defined(BCM_56725_A0) 1326 { /* SOC_FORMAT_INT_PBI_BCM56725_A0fmt */ 1327 /* format PBIfmt */ 1328 /* nFields */ 70, 1329 /* *fields */ soc_PBI_BCM56820_A0fmt_fields, 1330 /* bits */ 391, 1331 /* flags */ 0, 1332 }, 1333 #endif /* chips */ 1334 1335 #if defined(BCM_56770_A0) 1336 { /* SOC_FORMAT_INT_PBI_BCM56770_A0fmt */ 1337 /* format PBIfmt */ 1338 /* nFields */ 2, 1339 /* *fields */ soc_PBI_BCM56870_A0fmt_fields, 1340 /* bits */ 976, 1341 /* flags */ 0, 1342 }, 1343 #endif /* chips */ 1344 1345 #if defined(BCM_56800_A0) 1346 { /* SOC_FORMAT_INT_PBI_BCM56800_A0fmt */ 1347 /* format PBIfmt */ 1348 /* nFields */ 52, 1349 /* *fields */ soc_PBI_BCM56800_A0fmt_fields, 1350 /* bits */ 287, 1351 /* flags */ 0, 1352 }, 1353 #endif /* chips */ 1354 1355 #if defined(BCM_56820_A0) 1356 { /* SOC_FORMAT_INT_PBI_BCM56820_A0fmt */ 1357 /* format PBIfmt */ 1358 /* nFields */ 70, 1359 /* *fields */ soc_PBI_BCM56820_A0fmt_fields, 1360 /* bits */ 391, 1361 /* flags */ 0, 1362 }, 1363 #endif /* chips */ 1364 1365 #if defined(BCM_56840_A0) 1366 { /* SOC_FORMAT_INT_PBI_BCM56840_A0fmt */ 1367 /* format PBIfmt */ 1368 /* nFields */ 2, 1369 /* *fields */ soc_PBI_BCM56840_A0fmt_fields, 1370 /* bits */ 751, 1371 /* flags */ 0, 1372 }, 1373 #endif /* chips */ 1374 1375 #if defined(BCM_56840_B0) 1376 { /* SOC_FORMAT_INT_PBI_BCM56840_B0fmt */ 1377 /* format PBIfmt */ 1378 /* nFields */ 2, 1379 /* *fields */ soc_PBI_BCM56840_A0fmt_fields, 1380 /* bits */ 751, 1381 /* flags */ 0, 1382 }, 1383 #endif /* chips */ 1384 1385 #if defined(BCM_56850_A0) 1386 { /* SOC_FORMAT_INT_PBI_BCM56850_A0fmt */ 1387 /* format PBIfmt */ 1388 /* nFields */ 2, 1389 /* *fields */ soc_PBI_BCM56850_A0fmt_fields, 1390 /* bits */ 1000, 1391 /* flags */ 0, 1392 }, 1393 #endif /* chips */ 1394 1395 #if defined(BCM_56860_A0) 1396 { /* SOC_FORMAT_INT_PBI_BCM56860_A0fmt */ 1397 /* format PBIfmt */ 1398 /* nFields */ 2, 1399 /* *fields */ soc_PBI_BCM56860_A0fmt_fields, 1400 /* bits */ 1018, 1401 /* flags */ 0, 1402 }, 1403 #endif /* chips */ 1404 1405 #if defined(BCM_56870_A0) 1406 { /* SOC_FORMAT_INT_PBI_BCM56870_A0fmt */ 1407 /* format PBIfmt */ 1408 /* nFields */ 2, 1409 /* *fields */ soc_PBI_BCM56870_A0fmt_fields, 1410 /* bits */ 976, 1411 /* flags */ 0, 1412 }, 1413 #endif /* chips */ 1414 1415 #if defined(BCM_56960_A0) 1416 { /* SOC_FORMAT_INT_PBI_BCM56960_A0fmt */ 1417 /* format PBIfmt */ 1418 /* nFields */ 2, 1419 /* *fields */ soc_PBI_BCM56960_A0fmt_fields, 1420 /* bits */ 935, 1421 /* flags */ 0, 1422 }, 1423 #endif /* chips */ 1424 1425 #if defined(BCM_56965_A0) 1426 { /* SOC_FORMAT_INT_PBI_BCM56965_A0fmt */ 1427 /* format PBIfmt */ 1428 /* nFields */ 2, 1429 /* *fields */ soc_PBI_BCM56960_A0fmt_fields, 1430 /* bits */ 935, 1431 /* flags */ 0, 1432 }, 1433 #endif /* chips */ 1434 1435 #if defined(BCM_56970_A0) 1436 { /* SOC_FORMAT_INT_PBI_BCM56970_A0fmt */ 1437 /* format PBIfmt */ 1438 /* nFields */ 2, 1439 /* *fields */ soc_PBI_BCM56970_A0fmt_fields, 1440 /* bits */ 975, 1441 /* flags */ 0, 1442 }, 1443 #endif /* chips */ 1444 1445 #if defined(BCM_56980_A0) 1446 { /* SOC_FORMAT_INT_PBI_BCM56980_A0fmt */ 1447 /* format PBIfmt */ 1448 /* nFields */ 2, 1449 /* *fields */ soc_PBI_BCM56980_A0fmt_fields, 1450 /* bits */ 766, 1451 /* flags */ 0, 1452 }, 1453 #endif /* chips */ 1454 1455 #if defined(BCM_56980_B0) 1456 { /* SOC_FORMAT_INT_PBI_BCM56980_B0fmt */ 1457 /* format PBIfmt */ 1458 /* nFields */ 2, 1459 /* *fields */ soc_PBI_BCM56980_A0fmt_fields, 1460 /* bits */ 766, 1461 /* flags */ 0, 1462 }, 1463 #endif /* chips */ 1464 1465 #if defined(BCM_88732_A0) 1466 { /* SOC_FORMAT_INT_PBI_BCM88732_A0fmt */ 1467 /* format PBIfmt */ 1468 /* nFields */ 77, 1469 /* *fields */ soc_PBI_BCM88732_A0fmt_fields, 1470 /* bits */ 247, 1471 /* flags */ 0, 1472 }, 1473 #endif /* chips */ 1474 1475 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1476 defined(BCM_56870_A0) 1477 { /* SOC_FORMAT_INT_PDD_IN_BUSfmt */ 1478 /* format PDD_IN_BUSfmt */ 1479 /* nFields */ 2, 1480 /* *fields */ soc_PDD_IN_BUSfmt_fields, 1481 /* bits */ 141, 1482 /* flags */ 0, 1483 }, 1484 #endif /* chips */ 1485 1486 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1487 defined(BCM_56870_A0) 1488 { /* SOC_FORMAT_INT_PDD_OUT_BUSfmt */ 1489 /* format PDD_OUT_BUSfmt */ 1490 /* nFields */ 68, 1491 /* *fields */ soc_PDD_OUT_BUSfmt_fields, 1492 /* bits */ 136, 1493 /* flags */ 0, 1494 }, 1495 #endif /* chips */ 1496 1497 #if defined(BCM_88732_A0) 1498 { /* SOC_FORMAT_INT_PD_TO_MS_IFfmt */ 1499 /* format PD_TO_MS_IFfmt */ 1500 /* nFields */ 2, 1501 /* *fields */ soc_PD_TO_MS_IFfmt_fields, 1502 /* bits */ 6, 1503 /* flags */ 0, 1504 }, 1505 #endif /* chips */ 1506 1507 #if defined(BCM_88732_A0) 1508 { /* SOC_FORMAT_INT_PD_TO_PORT_IFfmt */ 1509 /* format PD_TO_PORT_IFfmt */ 1510 /* nFields */ 8, 1511 /* *fields */ soc_PD_TO_PORT_IFfmt_fields, 1512 /* bits */ 22, 1513 /* flags */ 0, 1514 }, 1515 #endif /* chips */ 1516 1517 #if defined(BCM_88732_A0) 1518 { /* SOC_FORMAT_INT_PE_DROPfmt */ 1519 /* format PE_DROPfmt */ 1520 /* nFields */ 17, 1521 /* *fields */ soc_PE_DROPfmt_fields, 1522 /* bits */ 27, 1523 /* flags */ 0, 1524 }, 1525 #endif /* chips */ 1526 1527 #if defined(BCM_56524_A0) || defined(BCM_56624_A0) || \ 1528 defined(BCM_56634_A0) || defined(BCM_56634_B0) 1529 { /* SOC_FORMAT_INT_PFAP_S_RFfmt */ 1530 /* format PFAP_S_RFfmt */ 1531 /* nFields */ 1, 1532 /* *fields */ soc_PFAP_S_RFfmt_fields, 1533 /* bits */ 36, 1534 /* flags */ 0, 1535 }, 1536 #endif /* chips */ 1537 1538 #if defined(BCM_56334_A0) 1539 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56334_A0fmt */ 1540 /* format PFAP_S_RFfmt */ 1541 /* nFields */ 1, 1542 /* *fields */ soc_PFAP_S_RFfmt_fields, 1543 /* bits */ 36, 1544 /* flags */ 0, 1545 }, 1546 #endif /* chips */ 1547 1548 #if defined(BCM_56334_B0) 1549 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56334_B0fmt */ 1550 /* format PFAP_S_RFfmt */ 1551 /* nFields */ 1, 1552 /* *fields */ soc_PFAP_S_RFfmt_fields, 1553 /* bits */ 36, 1554 /* flags */ 0, 1555 }, 1556 #endif /* chips */ 1557 1558 #if defined(BCM_56524_B0) 1559 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56524_B0fmt */ 1560 /* format PFAP_S_RFfmt */ 1561 /* nFields */ 1, 1562 /* *fields */ soc_PFAP_S_RFfmt_fields, 1563 /* bits */ 36, 1564 /* flags */ 0, 1565 }, 1566 #endif /* chips */ 1567 1568 #if defined(BCM_56624_B0) 1569 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56624_B0fmt */ 1570 /* format PFAP_S_RFfmt */ 1571 /* nFields */ 1, 1572 /* *fields */ soc_PFAP_S_RFfmt_fields, 1573 /* bits */ 36, 1574 /* flags */ 0, 1575 }, 1576 #endif /* chips */ 1577 1578 #if defined(BCM_56680_A0) 1579 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56680_A0fmt */ 1580 /* format PFAP_S_RFfmt */ 1581 /* nFields */ 1, 1582 /* *fields */ soc_PFAP_S_RFfmt_fields, 1583 /* bits */ 36, 1584 /* flags */ 0, 1585 }, 1586 #endif /* chips */ 1587 1588 #if defined(BCM_56680_B0) 1589 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56680_B0fmt */ 1590 /* format PFAP_S_RFfmt */ 1591 /* nFields */ 1, 1592 /* *fields */ soc_PFAP_S_RFfmt_fields, 1593 /* bits */ 36, 1594 /* flags */ 0, 1595 }, 1596 #endif /* chips */ 1597 1598 #if defined(BCM_56685_A0) 1599 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56685_A0fmt */ 1600 /* format PFAP_S_RFfmt */ 1601 /* nFields */ 1, 1602 /* *fields */ soc_PFAP_S_RFfmt_fields, 1603 /* bits */ 36, 1604 /* flags */ 0, 1605 }, 1606 #endif /* chips */ 1607 1608 #if defined(BCM_56685_B0) 1609 { /* SOC_FORMAT_INT_PFAP_S_RF_BCM56685_B0fmt */ 1610 /* format PFAP_S_RFfmt */ 1611 /* nFields */ 1, 1612 /* *fields */ soc_PFAP_S_RFfmt_fields, 1613 /* bits */ 36, 1614 /* flags */ 0, 1615 }, 1616 #endif /* chips */ 1617 1618 #if defined(BCM_56850_A0) 1619 { /* SOC_FORMAT_INT_PGW_OBM_DATAfmt */ 1620 /* format PGW_OBM_DATAfmt */ 1621 /* nFields */ 17, 1622 /* *fields */ soc_PGW_OBM_DATAfmt_fields, 1623 /* bits */ 192, 1624 /* flags */ 0, 1625 }, 1626 #endif /* chips */ 1627 1628 #if defined(BCM_56860_A0) 1629 { /* SOC_FORMAT_INT_PGW_OBM_DATA_BCM56860_A0fmt */ 1630 /* format PGW_OBM_DATAfmt */ 1631 /* nFields */ 17, 1632 /* *fields */ soc_PGW_OBM_DATA_BCM56860_A0fmt_fields, 1633 /* bits */ 192, 1634 /* flags */ 0, 1635 }, 1636 #endif /* chips */ 1637 1638 #if defined(BCM_56840_A0) 1639 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORDfmt */ 1640 /* format PG_TO_IP_CONTROL_WORDfmt */ 1641 /* nFields */ 11, 1642 /* *fields */ soc_PG_TO_IP_CONTROL_WORDfmt_fields, 1643 /* bits */ 32, 1644 /* flags */ 0, 1645 }, 1646 #endif /* chips */ 1647 1648 #if defined(BCM_56370_A0) 1649 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56370_A0fmt */ 1650 /* format PG_TO_IP_CONTROL_WORDfmt */ 1651 /* nFields */ 14, 1652 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56370_A0fmt_fields, 1653 /* bits */ 32, 1654 /* flags */ 0, 1655 }, 1656 #endif /* chips */ 1657 1658 #if defined(BCM_56560_A0) 1659 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56560_A0fmt */ 1660 /* format PG_TO_IP_CONTROL_WORDfmt */ 1661 /* nFields */ 11, 1662 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56560_A0fmt_fields, 1663 /* bits */ 32, 1664 /* flags */ 0, 1665 }, 1666 #endif /* chips */ 1667 1668 #if defined(BCM_56560_B0) 1669 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56560_B0fmt */ 1670 /* format PG_TO_IP_CONTROL_WORDfmt */ 1671 /* nFields */ 11, 1672 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56560_A0fmt_fields, 1673 /* bits */ 32, 1674 /* flags */ 0, 1675 }, 1676 #endif /* chips */ 1677 1678 #if defined(BCM_56670_A0) 1679 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56670_A0fmt */ 1680 /* format PG_TO_IP_CONTROL_WORDfmt */ 1681 /* nFields */ 12, 1682 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56670_A0fmt_fields, 1683 /* bits */ 32, 1684 /* flags */ 0, 1685 }, 1686 #endif /* chips */ 1687 1688 #if defined(BCM_56670_B0) 1689 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56670_B0fmt */ 1690 /* format PG_TO_IP_CONTROL_WORDfmt */ 1691 /* nFields */ 12, 1692 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56670_A0fmt_fields, 1693 /* bits */ 32, 1694 /* flags */ 0, 1695 }, 1696 #endif /* chips */ 1697 1698 #if defined(BCM_56770_A0) 1699 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56770_A0fmt */ 1700 /* format PG_TO_IP_CONTROL_WORDfmt */ 1701 /* nFields */ 11, 1702 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt_fields, 1703 /* bits */ 32, 1704 /* flags */ 0, 1705 }, 1706 #endif /* chips */ 1707 1708 #if defined(BCM_56840_B0) 1709 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56840_B0fmt */ 1710 /* format PG_TO_IP_CONTROL_WORDfmt */ 1711 /* nFields */ 11, 1712 /* *fields */ soc_PG_TO_IP_CONTROL_WORDfmt_fields, 1713 /* bits */ 32, 1714 /* flags */ 0, 1715 }, 1716 #endif /* chips */ 1717 1718 #if defined(BCM_56850_A0) 1719 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56850_A0fmt */ 1720 /* format PG_TO_IP_CONTROL_WORDfmt */ 1721 /* nFields */ 11, 1722 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56850_A0fmt_fields, 1723 /* bits */ 32, 1724 /* flags */ 0, 1725 }, 1726 #endif /* chips */ 1727 1728 #if defined(BCM_56860_A0) 1729 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56860_A0fmt */ 1730 /* format PG_TO_IP_CONTROL_WORDfmt */ 1731 /* nFields */ 11, 1732 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56860_A0fmt_fields, 1733 /* bits */ 32, 1734 /* flags */ 0, 1735 }, 1736 #endif /* chips */ 1737 1738 #if defined(BCM_56870_A0) 1739 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56870_A0fmt */ 1740 /* format PG_TO_IP_CONTROL_WORDfmt */ 1741 /* nFields */ 11, 1742 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt_fields, 1743 /* bits */ 32, 1744 /* flags */ 0, 1745 }, 1746 #endif /* chips */ 1747 1748 #if defined(BCM_56960_A0) 1749 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt */ 1750 /* format PG_TO_IP_CONTROL_WORDfmt */ 1751 /* nFields */ 11, 1752 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt_fields, 1753 /* bits */ 32, 1754 /* flags */ 0, 1755 }, 1756 #endif /* chips */ 1757 1758 #if defined(BCM_56965_A0) 1759 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56965_A0fmt */ 1760 /* format PG_TO_IP_CONTROL_WORDfmt */ 1761 /* nFields */ 11, 1762 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt_fields, 1763 /* bits */ 32, 1764 /* flags */ 0, 1765 }, 1766 #endif /* chips */ 1767 1768 #if defined(BCM_56970_A0) 1769 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56970_A0fmt */ 1770 /* format PG_TO_IP_CONTROL_WORDfmt */ 1771 /* nFields */ 11, 1772 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt_fields, 1773 /* bits */ 32, 1774 /* flags */ 0, 1775 }, 1776 #endif /* chips */ 1777 1778 #if defined(BCM_56980_A0) 1779 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56980_A0fmt */ 1780 /* format PG_TO_IP_CONTROL_WORDfmt */ 1781 /* nFields */ 11, 1782 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt_fields, 1783 /* bits */ 32, 1784 /* flags */ 0, 1785 }, 1786 #endif /* chips */ 1787 1788 #if defined(BCM_56980_B0) 1789 { /* SOC_FORMAT_INT_PG_TO_IP_CONTROL_WORD_BCM56980_B0fmt */ 1790 /* format PG_TO_IP_CONTROL_WORDfmt */ 1791 /* nFields */ 11, 1792 /* *fields */ soc_PG_TO_IP_CONTROL_WORD_BCM56960_A0fmt_fields, 1793 /* bits */ 32, 1794 /* flags */ 0, 1795 }, 1796 #endif /* chips */ 1797 1798 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 1799 { /* SOC_FORMAT_INT_PHB2_COS_MAP_INDEXfmt */ 1800 /* format PHB2_COS_MAP_INDEXfmt */ 1801 /* nFields */ 3, 1802 /* *fields */ soc_PHB2_COS_MAP_INDEXfmt_fields, 1803 /* bits */ 9, 1804 /* flags */ 0, 1805 }, 1806 #endif /* chips */ 1807 1808 #if defined(BCM_56370_A0) 1809 { /* SOC_FORMAT_INT_PHB2_COS_MAP_INDEX_BCM56370_A0fmt */ 1810 /* format PHB2_COS_MAP_INDEXfmt */ 1811 /* nFields */ 4, 1812 /* *fields */ soc_PHB2_COS_MAP_INDEX_BCM56370_A0fmt_fields, 1813 /* bits */ 10, 1814 /* flags */ 0, 1815 }, 1816 #endif /* chips */ 1817 1818 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 1819 { /* SOC_FORMAT_INT_PHB_MAPPING_TBL_INDEXfmt */ 1820 /* format PHB_MAPPING_TBL_INDEXfmt */ 1821 /* nFields */ 2, 1822 /* *fields */ soc_PHB_MAPPING_TBL_INDEXfmt_fields, 1823 /* bits */ 14, 1824 /* flags */ 0, 1825 }, 1826 #endif /* chips */ 1827 1828 #if defined(BCM_56370_A0) 1829 { /* SOC_FORMAT_INT_PHB_MAPPING_TBL_INDEX_BCM56370_A0fmt */ 1830 /* format PHB_MAPPING_TBL_INDEXfmt */ 1831 /* nFields */ 2, 1832 /* *fields */ soc_PHB_MAPPING_TBL_INDEX_BCM56370_A0fmt_fields, 1833 /* bits */ 13, 1834 /* flags */ 0, 1835 }, 1836 #endif /* chips */ 1837 1838 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1839 defined(BCM_56870_A0) 1840 { /* SOC_FORMAT_INT_PIM_BIDIR_ACTION_SETfmt */ 1841 /* format PIM_BIDIR_ACTION_SETfmt */ 1842 /* nFields */ 3, 1843 /* *fields */ soc_PIM_BIDIR_ACTION_SETfmt_fields, 1844 /* bits */ 8, 1845 /* flags */ 0, 1846 }, 1847 #endif /* chips */ 1848 1849 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 1850 { /* SOC_FORMAT_INT_PIM_SM_ACTION_SETfmt */ 1851 /* format PIM_SM_ACTION_SETfmt */ 1852 /* nFields */ 3, 1853 /* *fields */ soc_PIM_SM_ACTION_SETfmt_fields, 1854 /* bits */ 16, 1855 /* flags */ 0, 1856 }, 1857 #endif /* chips */ 1858 1859 #if defined(BCM_56370_A0) 1860 { /* SOC_FORMAT_INT_PIM_SM_ACTION_SET_BCM56370_A0fmt */ 1861 /* format PIM_SM_ACTION_SETfmt */ 1862 /* nFields */ 4, 1863 /* *fields */ soc_PIM_SM_ACTION_SET_BCM56370_A0fmt_fields, 1864 /* bits */ 16, 1865 /* flags */ 0, 1866 }, 1867 #endif /* chips */ 1868 1869 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 1870 { /* SOC_FORMAT_INT_PIPE_DATA_OUT_INFOfmt */ 1871 /* format PIPE_DATA_OUT_INFOfmt */ 1872 /* nFields */ 22, 1873 /* *fields */ soc_PIPE_DATA_OUT_INFOfmt_fields, 1874 /* bits */ 89, 1875 /* flags */ 0, 1876 }, 1877 #endif /* chips */ 1878 1879 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 1880 { /* SOC_FORMAT_INT_PKTHDR0_MEM0_S_RFfmt */ 1881 /* format PKTHDR0_MEM0_S_RFfmt */ 1882 /* nFields */ 1, 1883 /* *fields */ soc_PKTHDR0_MEM0_S_RFfmt_fields, 1884 /* bits */ 112, 1885 /* flags */ 0, 1886 }, 1887 #endif /* chips */ 1888 1889 #if defined(BCM_88732_A0) 1890 { /* SOC_FORMAT_INT_PKTHDR0_MEM0_S_RF_BCM88732_A0fmt */ 1891 /* format PKTHDR0_MEM0_S_RFfmt */ 1892 /* nFields */ 1, 1893 /* *fields */ soc_PKTHDR0_MEM0_S_RF_BCM88732_A0fmt_fields, 1894 /* bits */ 128, 1895 /* flags */ 0, 1896 }, 1897 #endif /* chips */ 1898 1899 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 1900 { /* SOC_FORMAT_INT_PKTHDR0_MEM1_S_RFfmt */ 1901 /* format PKTHDR0_MEM1_S_RFfmt */ 1902 /* nFields */ 1, 1903 /* *fields */ soc_PKTHDR0_MEM1_S_RFfmt_fields, 1904 /* bits */ 112, 1905 /* flags */ 0, 1906 }, 1907 #endif /* chips */ 1908 1909 #if defined(BCM_88732_A0) 1910 { /* SOC_FORMAT_INT_PKTHDR0_MEM1_S_RF_BCM88732_A0fmt */ 1911 /* format PKTHDR0_MEM1_S_RFfmt */ 1912 /* nFields */ 1, 1913 /* *fields */ soc_PKTHDR0_MEM1_S_RF_BCM88732_A0fmt_fields, 1914 /* bits */ 128, 1915 /* flags */ 0, 1916 }, 1917 #endif /* chips */ 1918 1919 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 1920 { /* SOC_FORMAT_INT_PKTHDR0_MEM2_S_RFfmt */ 1921 /* format PKTHDR0_MEM2_S_RFfmt */ 1922 /* nFields */ 1, 1923 /* *fields */ soc_PKTHDR0_MEM2_S_RFfmt_fields, 1924 /* bits */ 112, 1925 /* flags */ 0, 1926 }, 1927 #endif /* chips */ 1928 1929 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 1930 { /* SOC_FORMAT_INT_PKTHDR0_MEM3_S_RFfmt */ 1931 /* format PKTHDR0_MEM3_S_RFfmt */ 1932 /* nFields */ 1, 1933 /* *fields */ soc_PKTHDR0_MEM3_S_RFfmt_fields, 1934 /* bits */ 112, 1935 /* flags */ 0, 1936 }, 1937 #endif /* chips */ 1938 1939 #if defined(BCM_56800_A0) 1940 { /* SOC_FORMAT_INT_PKTHDR0_S_RFfmt */ 1941 /* format PKTHDR0_S_RFfmt */ 1942 /* nFields */ 1, 1943 /* *fields */ soc_PKTHDR0_S_RFfmt_fields, 1944 /* bits */ 84, 1945 /* flags */ 0, 1946 }, 1947 #endif /* chips */ 1948 1949 #if defined(BCM_56142_A0) 1950 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56142_A0fmt */ 1951 /* format PKTHDR0_S_RFfmt */ 1952 /* nFields */ 1, 1953 /* *fields */ soc_PKTHDR0_S_RF_BCM56142_A0fmt_fields, 1954 /* bits */ 96, 1955 /* flags */ 0, 1956 }, 1957 #endif /* chips */ 1958 1959 #if defined(BCM_56260_A0) 1960 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56260_A0fmt */ 1961 /* format PKTHDR0_S_RFfmt */ 1962 /* nFields */ 1, 1963 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 1964 /* bits */ 128, 1965 /* flags */ 0, 1966 }, 1967 #endif /* chips */ 1968 1969 #if defined(BCM_56260_B0) 1970 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56260_B0fmt */ 1971 /* format PKTHDR0_S_RFfmt */ 1972 /* nFields */ 1, 1973 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 1974 /* bits */ 128, 1975 /* flags */ 0, 1976 }, 1977 #endif /* chips */ 1978 1979 #if defined(BCM_56270_A0) 1980 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56270_A0fmt */ 1981 /* format PKTHDR0_S_RFfmt */ 1982 /* nFields */ 1, 1983 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 1984 /* bits */ 128, 1985 /* flags */ 0, 1986 }, 1987 #endif /* chips */ 1988 1989 #if defined(BCM_56334_A0) 1990 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56334_A0fmt */ 1991 /* format PKTHDR0_S_RFfmt */ 1992 /* nFields */ 1, 1993 /* *fields */ soc_PKTHDR0_S_RF_BCM56334_A0fmt_fields, 1994 /* bits */ 54, 1995 /* flags */ 0, 1996 }, 1997 #endif /* chips */ 1998 1999 #if defined(BCM_56334_B0) 2000 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56334_B0fmt */ 2001 /* format PKTHDR0_S_RFfmt */ 2002 /* nFields */ 1, 2003 /* *fields */ soc_PKTHDR0_S_RF_BCM56334_A0fmt_fields, 2004 /* bits */ 54, 2005 /* flags */ 0, 2006 }, 2007 #endif /* chips */ 2008 2009 #if defined(BCM_56340_A0) 2010 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56340_A0fmt */ 2011 /* format PKTHDR0_S_RFfmt */ 2012 /* nFields */ 1, 2013 /* *fields */ soc_PKTHDR0_S_RF_BCM56640_A0fmt_fields, 2014 /* bits */ 128, 2015 /* flags */ 0, 2016 }, 2017 #endif /* chips */ 2018 2019 #if defined(BCM_56440_A0) 2020 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56440_A0fmt */ 2021 /* format PKTHDR0_S_RFfmt */ 2022 /* nFields */ 1, 2023 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2024 /* bits */ 128, 2025 /* flags */ 0, 2026 }, 2027 #endif /* chips */ 2028 2029 #if defined(BCM_56440_B0) 2030 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56440_B0fmt */ 2031 /* format PKTHDR0_S_RFfmt */ 2032 /* nFields */ 1, 2033 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2034 /* bits */ 128, 2035 /* flags */ 0, 2036 }, 2037 #endif /* chips */ 2038 2039 #if defined(BCM_56450_A0) 2040 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56450_A0fmt */ 2041 /* format PKTHDR0_S_RFfmt */ 2042 /* nFields */ 1, 2043 /* *fields */ soc_PKTHDR0_S_RF_BCM56640_A0fmt_fields, 2044 /* bits */ 128, 2045 /* flags */ 0, 2046 }, 2047 #endif /* chips */ 2048 2049 #if defined(BCM_56450_B0) 2050 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56450_B0fmt */ 2051 /* format PKTHDR0_S_RFfmt */ 2052 /* nFields */ 1, 2053 /* *fields */ soc_PKTHDR0_S_RF_BCM56640_A0fmt_fields, 2054 /* bits */ 128, 2055 /* flags */ 0, 2056 }, 2057 #endif /* chips */ 2058 2059 #if defined(BCM_56450_B1) 2060 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56450_B1fmt */ 2061 /* format PKTHDR0_S_RFfmt */ 2062 /* nFields */ 1, 2063 /* *fields */ soc_PKTHDR0_S_RF_BCM56640_A0fmt_fields, 2064 /* bits */ 128, 2065 /* flags */ 0, 2066 }, 2067 #endif /* chips */ 2068 2069 #if defined(BCM_56524_A0) 2070 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56524_A0fmt */ 2071 /* format PKTHDR0_S_RFfmt */ 2072 /* nFields */ 1, 2073 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2074 /* bits */ 128, 2075 /* flags */ 0, 2076 }, 2077 #endif /* chips */ 2078 2079 #if defined(BCM_56524_B0) 2080 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56524_B0fmt */ 2081 /* format PKTHDR0_S_RFfmt */ 2082 /* nFields */ 1, 2083 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2084 /* bits */ 128, 2085 /* flags */ 0, 2086 }, 2087 #endif /* chips */ 2088 2089 #if defined(BCM_56560_A0) 2090 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56560_A0fmt */ 2091 /* format PKTHDR0_S_RFfmt */ 2092 /* nFields */ 1, 2093 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 2094 /* bits */ 128, 2095 /* flags */ 0, 2096 }, 2097 #endif /* chips */ 2098 2099 #if defined(BCM_56560_B0) 2100 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56560_B0fmt */ 2101 /* format PKTHDR0_S_RFfmt */ 2102 /* nFields */ 1, 2103 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 2104 /* bits */ 128, 2105 /* flags */ 0, 2106 }, 2107 #endif /* chips */ 2108 2109 #if defined(BCM_56624_A0) 2110 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56624_A0fmt */ 2111 /* format PKTHDR0_S_RFfmt */ 2112 /* nFields */ 1, 2113 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2114 /* bits */ 128, 2115 /* flags */ 0, 2116 }, 2117 #endif /* chips */ 2118 2119 #if defined(BCM_56624_B0) 2120 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56624_B0fmt */ 2121 /* format PKTHDR0_S_RFfmt */ 2122 /* nFields */ 1, 2123 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2124 /* bits */ 128, 2125 /* flags */ 0, 2126 }, 2127 #endif /* chips */ 2128 2129 #if defined(BCM_56634_A0) 2130 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56634_A0fmt */ 2131 /* format PKTHDR0_S_RFfmt */ 2132 /* nFields */ 1, 2133 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2134 /* bits */ 128, 2135 /* flags */ 0, 2136 }, 2137 #endif /* chips */ 2138 2139 #if defined(BCM_56634_B0) 2140 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56634_B0fmt */ 2141 /* format PKTHDR0_S_RFfmt */ 2142 /* nFields */ 1, 2143 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2144 /* bits */ 128, 2145 /* flags */ 0, 2146 }, 2147 #endif /* chips */ 2148 2149 #if defined(BCM_56640_A0) 2150 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56640_A0fmt */ 2151 /* format PKTHDR0_S_RFfmt */ 2152 /* nFields */ 1, 2153 /* *fields */ soc_PKTHDR0_S_RF_BCM56640_A0fmt_fields, 2154 /* bits */ 128, 2155 /* flags */ 0, 2156 }, 2157 #endif /* chips */ 2158 2159 #if defined(BCM_56670_A0) 2160 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56670_A0fmt */ 2161 /* format PKTHDR0_S_RFfmt */ 2162 /* nFields */ 1, 2163 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 2164 /* bits */ 128, 2165 /* flags */ 0, 2166 }, 2167 #endif /* chips */ 2168 2169 #if defined(BCM_56670_B0) 2170 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56670_B0fmt */ 2171 /* format PKTHDR0_S_RFfmt */ 2172 /* nFields */ 1, 2173 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 2174 /* bits */ 128, 2175 /* flags */ 0, 2176 }, 2177 #endif /* chips */ 2178 2179 #if defined(BCM_56680_A0) 2180 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56680_A0fmt */ 2181 /* format PKTHDR0_S_RFfmt */ 2182 /* nFields */ 1, 2183 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2184 /* bits */ 128, 2185 /* flags */ 0, 2186 }, 2187 #endif /* chips */ 2188 2189 #if defined(BCM_56680_B0) 2190 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56680_B0fmt */ 2191 /* format PKTHDR0_S_RFfmt */ 2192 /* nFields */ 1, 2193 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2194 /* bits */ 128, 2195 /* flags */ 0, 2196 }, 2197 #endif /* chips */ 2198 2199 #if defined(BCM_56685_A0) 2200 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56685_A0fmt */ 2201 /* format PKTHDR0_S_RFfmt */ 2202 /* nFields */ 1, 2203 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2204 /* bits */ 128, 2205 /* flags */ 0, 2206 }, 2207 #endif /* chips */ 2208 2209 #if defined(BCM_56685_B0) 2210 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56685_B0fmt */ 2211 /* format PKTHDR0_S_RFfmt */ 2212 /* nFields */ 1, 2213 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2214 /* bits */ 128, 2215 /* flags */ 0, 2216 }, 2217 #endif /* chips */ 2218 2219 #if defined(BCM_56840_A0) 2220 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56840_A0fmt */ 2221 /* format PKTHDR0_S_RFfmt */ 2222 /* nFields */ 1, 2223 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2224 /* bits */ 128, 2225 /* flags */ 0, 2226 }, 2227 #endif /* chips */ 2228 2229 #if defined(BCM_56840_B0) 2230 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56840_B0fmt */ 2231 /* format PKTHDR0_S_RFfmt */ 2232 /* nFields */ 1, 2233 /* *fields */ soc_PKTHDR0_S_RF_BCM56624_A0fmt_fields, 2234 /* bits */ 128, 2235 /* flags */ 0, 2236 }, 2237 #endif /* chips */ 2238 2239 #if defined(BCM_56850_A0) 2240 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56850_A0fmt */ 2241 /* format PKTHDR0_S_RFfmt */ 2242 /* nFields */ 1, 2243 /* *fields */ soc_PKTHDR0_S_RF_BCM56640_A0fmt_fields, 2244 /* bits */ 128, 2245 /* flags */ 0, 2246 }, 2247 #endif /* chips */ 2248 2249 #if defined(BCM_56860_A0) 2250 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56860_A0fmt */ 2251 /* format PKTHDR0_S_RFfmt */ 2252 /* nFields */ 1, 2253 /* *fields */ soc_PKTHDR0_S_RF_BCM56640_A0fmt_fields, 2254 /* bits */ 128, 2255 /* flags */ 0, 2256 }, 2257 #endif /* chips */ 2258 2259 #if defined(BCM_56960_A0) 2260 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56960_A0fmt */ 2261 /* format PKTHDR0_S_RFfmt */ 2262 /* nFields */ 1, 2263 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 2264 /* bits */ 128, 2265 /* flags */ 0, 2266 }, 2267 #endif /* chips */ 2268 2269 #if defined(BCM_56965_A0) 2270 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56965_A0fmt */ 2271 /* format PKTHDR0_S_RFfmt */ 2272 /* nFields */ 1, 2273 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 2274 /* bits */ 128, 2275 /* flags */ 0, 2276 }, 2277 #endif /* chips */ 2278 2279 #if defined(BCM_56970_A0) 2280 { /* SOC_FORMAT_INT_PKTHDR0_S_RF_BCM56970_A0fmt */ 2281 /* format PKTHDR0_S_RFfmt */ 2282 /* nFields */ 1, 2283 /* *fields */ soc_PKTHDR0_S_RF_BCM56960_A0fmt_fields, 2284 /* bits */ 128, 2285 /* flags */ 0, 2286 }, 2287 #endif /* chips */ 2288 2289 #if defined(BCM_56800_A0) 2290 { /* SOC_FORMAT_INT_PKTHDR1_S_RFfmt */ 2291 /* format PKTHDR1_S_RFfmt */ 2292 /* nFields */ 1, 2293 /* *fields */ soc_PKTHDR1_S_RFfmt_fields, 2294 /* bits */ 84, 2295 /* flags */ 0, 2296 }, 2297 #endif /* chips */ 2298 2299 #if defined(BCM_56142_A0) 2300 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56142_A0fmt */ 2301 /* format PKTHDR1_S_RFfmt */ 2302 /* nFields */ 1, 2303 /* *fields */ soc_PKTHDR0_S_RF_BCM56142_A0fmt_fields, 2304 /* bits */ 96, 2305 /* flags */ 0, 2306 }, 2307 #endif /* chips */ 2308 2309 #if defined(BCM_56260_A0) 2310 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56260_A0fmt */ 2311 /* format PKTHDR1_S_RFfmt */ 2312 /* nFields */ 1, 2313 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2314 /* bits */ 128, 2315 /* flags */ 0, 2316 }, 2317 #endif /* chips */ 2318 2319 #if defined(BCM_56260_B0) 2320 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56260_B0fmt */ 2321 /* format PKTHDR1_S_RFfmt */ 2322 /* nFields */ 1, 2323 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2324 /* bits */ 128, 2325 /* flags */ 0, 2326 }, 2327 #endif /* chips */ 2328 2329 #if defined(BCM_56270_A0) 2330 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56270_A0fmt */ 2331 /* format PKTHDR1_S_RFfmt */ 2332 /* nFields */ 1, 2333 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2334 /* bits */ 128, 2335 /* flags */ 0, 2336 }, 2337 #endif /* chips */ 2338 2339 #if defined(BCM_56334_A0) 2340 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56334_A0fmt */ 2341 /* format PKTHDR1_S_RFfmt */ 2342 /* nFields */ 1, 2343 /* *fields */ soc_PKTHDR1_S_RF_BCM56334_A0fmt_fields, 2344 /* bits */ 54, 2345 /* flags */ 0, 2346 }, 2347 #endif /* chips */ 2348 2349 #if defined(BCM_56334_B0) 2350 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56334_B0fmt */ 2351 /* format PKTHDR1_S_RFfmt */ 2352 /* nFields */ 1, 2353 /* *fields */ soc_PKTHDR1_S_RF_BCM56334_A0fmt_fields, 2354 /* bits */ 54, 2355 /* flags */ 0, 2356 }, 2357 #endif /* chips */ 2358 2359 #if defined(BCM_56340_A0) 2360 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56340_A0fmt */ 2361 /* format PKTHDR1_S_RFfmt */ 2362 /* nFields */ 1, 2363 /* *fields */ soc_PKTHDR1_S_RF_BCM56640_A0fmt_fields, 2364 /* bits */ 128, 2365 /* flags */ 0, 2366 }, 2367 #endif /* chips */ 2368 2369 #if defined(BCM_56440_A0) 2370 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56440_A0fmt */ 2371 /* format PKTHDR1_S_RFfmt */ 2372 /* nFields */ 1, 2373 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2374 /* bits */ 128, 2375 /* flags */ 0, 2376 }, 2377 #endif /* chips */ 2378 2379 #if defined(BCM_56440_B0) 2380 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56440_B0fmt */ 2381 /* format PKTHDR1_S_RFfmt */ 2382 /* nFields */ 1, 2383 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2384 /* bits */ 128, 2385 /* flags */ 0, 2386 }, 2387 #endif /* chips */ 2388 2389 #if defined(BCM_56450_A0) 2390 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56450_A0fmt */ 2391 /* format PKTHDR1_S_RFfmt */ 2392 /* nFields */ 1, 2393 /* *fields */ soc_PKTHDR1_S_RF_BCM56640_A0fmt_fields, 2394 /* bits */ 128, 2395 /* flags */ 0, 2396 }, 2397 #endif /* chips */ 2398 2399 #if defined(BCM_56450_B0) 2400 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56450_B0fmt */ 2401 /* format PKTHDR1_S_RFfmt */ 2402 /* nFields */ 1, 2403 /* *fields */ soc_PKTHDR1_S_RF_BCM56640_A0fmt_fields, 2404 /* bits */ 128, 2405 /* flags */ 0, 2406 }, 2407 #endif /* chips */ 2408 2409 #if defined(BCM_56450_B1) 2410 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56450_B1fmt */ 2411 /* format PKTHDR1_S_RFfmt */ 2412 /* nFields */ 1, 2413 /* *fields */ soc_PKTHDR1_S_RF_BCM56640_A0fmt_fields, 2414 /* bits */ 128, 2415 /* flags */ 0, 2416 }, 2417 #endif /* chips */ 2418 2419 #if defined(BCM_56524_A0) 2420 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56524_A0fmt */ 2421 /* format PKTHDR1_S_RFfmt */ 2422 /* nFields */ 1, 2423 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2424 /* bits */ 128, 2425 /* flags */ 0, 2426 }, 2427 #endif /* chips */ 2428 2429 #if defined(BCM_56524_B0) 2430 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56524_B0fmt */ 2431 /* format PKTHDR1_S_RFfmt */ 2432 /* nFields */ 1, 2433 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2434 /* bits */ 128, 2435 /* flags */ 0, 2436 }, 2437 #endif /* chips */ 2438 2439 #if defined(BCM_56560_A0) 2440 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56560_A0fmt */ 2441 /* format PKTHDR1_S_RFfmt */ 2442 /* nFields */ 1, 2443 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2444 /* bits */ 128, 2445 /* flags */ 0, 2446 }, 2447 #endif /* chips */ 2448 2449 #if defined(BCM_56560_B0) 2450 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56560_B0fmt */ 2451 /* format PKTHDR1_S_RFfmt */ 2452 /* nFields */ 1, 2453 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2454 /* bits */ 128, 2455 /* flags */ 0, 2456 }, 2457 #endif /* chips */ 2458 2459 #if defined(BCM_56624_A0) 2460 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56624_A0fmt */ 2461 /* format PKTHDR1_S_RFfmt */ 2462 /* nFields */ 1, 2463 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2464 /* bits */ 128, 2465 /* flags */ 0, 2466 }, 2467 #endif /* chips */ 2468 2469 #if defined(BCM_56624_B0) 2470 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56624_B0fmt */ 2471 /* format PKTHDR1_S_RFfmt */ 2472 /* nFields */ 1, 2473 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2474 /* bits */ 128, 2475 /* flags */ 0, 2476 }, 2477 #endif /* chips */ 2478 2479 #if defined(BCM_56634_A0) 2480 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56634_A0fmt */ 2481 /* format PKTHDR1_S_RFfmt */ 2482 /* nFields */ 1, 2483 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2484 /* bits */ 128, 2485 /* flags */ 0, 2486 }, 2487 #endif /* chips */ 2488 2489 #if defined(BCM_56634_B0) 2490 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56634_B0fmt */ 2491 /* format PKTHDR1_S_RFfmt */ 2492 /* nFields */ 1, 2493 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2494 /* bits */ 128, 2495 /* flags */ 0, 2496 }, 2497 #endif /* chips */ 2498 2499 #if defined(BCM_56640_A0) 2500 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56640_A0fmt */ 2501 /* format PKTHDR1_S_RFfmt */ 2502 /* nFields */ 1, 2503 /* *fields */ soc_PKTHDR1_S_RF_BCM56640_A0fmt_fields, 2504 /* bits */ 128, 2505 /* flags */ 0, 2506 }, 2507 #endif /* chips */ 2508 2509 #if defined(BCM_56670_A0) 2510 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56670_A0fmt */ 2511 /* format PKTHDR1_S_RFfmt */ 2512 /* nFields */ 1, 2513 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2514 /* bits */ 128, 2515 /* flags */ 0, 2516 }, 2517 #endif /* chips */ 2518 2519 #if defined(BCM_56670_B0) 2520 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56670_B0fmt */ 2521 /* format PKTHDR1_S_RFfmt */ 2522 /* nFields */ 1, 2523 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2524 /* bits */ 128, 2525 /* flags */ 0, 2526 }, 2527 #endif /* chips */ 2528 2529 #if defined(BCM_56680_A0) 2530 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56680_A0fmt */ 2531 /* format PKTHDR1_S_RFfmt */ 2532 /* nFields */ 1, 2533 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2534 /* bits */ 128, 2535 /* flags */ 0, 2536 }, 2537 #endif /* chips */ 2538 2539 #if defined(BCM_56680_B0) 2540 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56680_B0fmt */ 2541 /* format PKTHDR1_S_RFfmt */ 2542 /* nFields */ 1, 2543 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2544 /* bits */ 128, 2545 /* flags */ 0, 2546 }, 2547 #endif /* chips */ 2548 2549 #if defined(BCM_56685_A0) 2550 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56685_A0fmt */ 2551 /* format PKTHDR1_S_RFfmt */ 2552 /* nFields */ 1, 2553 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2554 /* bits */ 128, 2555 /* flags */ 0, 2556 }, 2557 #endif /* chips */ 2558 2559 #if defined(BCM_56685_B0) 2560 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56685_B0fmt */ 2561 /* format PKTHDR1_S_RFfmt */ 2562 /* nFields */ 1, 2563 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2564 /* bits */ 128, 2565 /* flags */ 0, 2566 }, 2567 #endif /* chips */ 2568 2569 #if defined(BCM_56725_A0) 2570 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56725_A0fmt */ 2571 /* format PKTHDR1_S_RFfmt */ 2572 /* nFields */ 1, 2573 /* *fields */ soc_PKTHDR1_S_RF_BCM56820_A0fmt_fields, 2574 /* bits */ 112, 2575 /* flags */ 0, 2576 }, 2577 #endif /* chips */ 2578 2579 #if defined(BCM_56820_A0) 2580 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56820_A0fmt */ 2581 /* format PKTHDR1_S_RFfmt */ 2582 /* nFields */ 1, 2583 /* *fields */ soc_PKTHDR1_S_RF_BCM56820_A0fmt_fields, 2584 /* bits */ 112, 2585 /* flags */ 0, 2586 }, 2587 #endif /* chips */ 2588 2589 #if defined(BCM_56840_A0) 2590 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56840_A0fmt */ 2591 /* format PKTHDR1_S_RFfmt */ 2592 /* nFields */ 1, 2593 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2594 /* bits */ 128, 2595 /* flags */ 0, 2596 }, 2597 #endif /* chips */ 2598 2599 #if defined(BCM_56840_B0) 2600 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56840_B0fmt */ 2601 /* format PKTHDR1_S_RFfmt */ 2602 /* nFields */ 1, 2603 /* *fields */ soc_PKTHDR1_S_RF_BCM56624_A0fmt_fields, 2604 /* bits */ 128, 2605 /* flags */ 0, 2606 }, 2607 #endif /* chips */ 2608 2609 #if defined(BCM_56850_A0) 2610 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56850_A0fmt */ 2611 /* format PKTHDR1_S_RFfmt */ 2612 /* nFields */ 1, 2613 /* *fields */ soc_PKTHDR1_S_RF_BCM56640_A0fmt_fields, 2614 /* bits */ 128, 2615 /* flags */ 0, 2616 }, 2617 #endif /* chips */ 2618 2619 #if defined(BCM_56860_A0) 2620 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56860_A0fmt */ 2621 /* format PKTHDR1_S_RFfmt */ 2622 /* nFields */ 1, 2623 /* *fields */ soc_PKTHDR1_S_RF_BCM56640_A0fmt_fields, 2624 /* bits */ 128, 2625 /* flags */ 0, 2626 }, 2627 #endif /* chips */ 2628 2629 #if defined(BCM_56960_A0) 2630 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56960_A0fmt */ 2631 /* format PKTHDR1_S_RFfmt */ 2632 /* nFields */ 1, 2633 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2634 /* bits */ 128, 2635 /* flags */ 0, 2636 }, 2637 #endif /* chips */ 2638 2639 #if defined(BCM_56965_A0) 2640 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56965_A0fmt */ 2641 /* format PKTHDR1_S_RFfmt */ 2642 /* nFields */ 1, 2643 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2644 /* bits */ 128, 2645 /* flags */ 0, 2646 }, 2647 #endif /* chips */ 2648 2649 #if defined(BCM_56970_A0) 2650 { /* SOC_FORMAT_INT_PKTHDR1_S_RF_BCM56970_A0fmt */ 2651 /* format PKTHDR1_S_RFfmt */ 2652 /* nFields */ 1, 2653 /* *fields */ soc_PKTHDR1_S_RF_BCM56960_A0fmt_fields, 2654 /* bits */ 128, 2655 /* flags */ 0, 2656 }, 2657 #endif /* chips */ 2658 2659 #if defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 2660 defined(BCM_56634_B0) 2661 { /* SOC_FORMAT_INT_PKTHDR2_S_RFfmt */ 2662 /* format PKTHDR2_S_RFfmt */ 2663 /* nFields */ 1, 2664 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2665 /* bits */ 112, 2666 /* flags */ 0, 2667 }, 2668 #endif /* chips */ 2669 2670 #if defined(BCM_56334_A0) 2671 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56334_A0fmt */ 2672 /* format PKTHDR2_S_RFfmt */ 2673 /* nFields */ 1, 2674 /* *fields */ soc_PKTHDR2_S_RF_BCM56334_A0fmt_fields, 2675 /* bits */ 36, 2676 /* flags */ 0, 2677 }, 2678 #endif /* chips */ 2679 2680 #if defined(BCM_56334_B0) 2681 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56334_B0fmt */ 2682 /* format PKTHDR2_S_RFfmt */ 2683 /* nFields */ 1, 2684 /* *fields */ soc_PKTHDR2_S_RF_BCM56334_A0fmt_fields, 2685 /* bits */ 36, 2686 /* flags */ 0, 2687 }, 2688 #endif /* chips */ 2689 2690 #if defined(BCM_56524_A0) 2691 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56524_A0fmt */ 2692 /* format PKTHDR2_S_RFfmt */ 2693 /* nFields */ 1, 2694 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2695 /* bits */ 112, 2696 /* flags */ 0, 2697 }, 2698 #endif /* chips */ 2699 2700 #if defined(BCM_56524_B0) 2701 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56524_B0fmt */ 2702 /* format PKTHDR2_S_RFfmt */ 2703 /* nFields */ 1, 2704 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2705 /* bits */ 112, 2706 /* flags */ 0, 2707 }, 2708 #endif /* chips */ 2709 2710 #if defined(BCM_56624_B0) 2711 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56624_B0fmt */ 2712 /* format PKTHDR2_S_RFfmt */ 2713 /* nFields */ 1, 2714 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2715 /* bits */ 112, 2716 /* flags */ 0, 2717 }, 2718 #endif /* chips */ 2719 2720 #if defined(BCM_56680_A0) 2721 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56680_A0fmt */ 2722 /* format PKTHDR2_S_RFfmt */ 2723 /* nFields */ 1, 2724 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2725 /* bits */ 112, 2726 /* flags */ 0, 2727 }, 2728 #endif /* chips */ 2729 2730 #if defined(BCM_56680_B0) 2731 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56680_B0fmt */ 2732 /* format PKTHDR2_S_RFfmt */ 2733 /* nFields */ 1, 2734 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2735 /* bits */ 112, 2736 /* flags */ 0, 2737 }, 2738 #endif /* chips */ 2739 2740 #if defined(BCM_56685_A0) 2741 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56685_A0fmt */ 2742 /* format PKTHDR2_S_RFfmt */ 2743 /* nFields */ 1, 2744 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2745 /* bits */ 112, 2746 /* flags */ 0, 2747 }, 2748 #endif /* chips */ 2749 2750 #if defined(BCM_56685_B0) 2751 { /* SOC_FORMAT_INT_PKTHDR2_S_RF_BCM56685_B0fmt */ 2752 /* format PKTHDR2_S_RFfmt */ 2753 /* nFields */ 1, 2754 /* *fields */ soc_PKTHDR2_S_RFfmt_fields, 2755 /* bits */ 112, 2756 /* flags */ 0, 2757 }, 2758 #endif /* chips */ 2759 2760 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 2761 { /* SOC_FORMAT_INT_PKTHDR_CPU0_S_RFfmt */ 2762 /* format PKTHDR_CPU0_S_RFfmt */ 2763 /* nFields */ 1, 2764 /* *fields */ soc_PKTHDR_CPU0_S_RFfmt_fields, 2765 /* bits */ 112, 2766 /* flags */ 0, 2767 }, 2768 #endif /* chips */ 2769 2770 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 2771 { /* SOC_FORMAT_INT_PKTHDR_CPU1_S_RFfmt */ 2772 /* format PKTHDR_CPU1_S_RFfmt */ 2773 /* nFields */ 1, 2774 /* *fields */ soc_PKTHDR_CPU1_S_RFfmt_fields, 2775 /* bits */ 56, 2776 /* flags */ 0, 2777 }, 2778 #endif /* chips */ 2779 2780 #if defined(BCM_56800_A0) 2781 { /* SOC_FORMAT_INT_PKTHDR_CPU_S_RFfmt */ 2782 /* format PKTHDR_CPU_S_RFfmt */ 2783 /* nFields */ 1, 2784 /* *fields */ soc_PKTHDR_CPU_S_RFfmt_fields, 2785 /* bits */ 84, 2786 /* flags */ 0, 2787 }, 2788 #endif /* chips */ 2789 2790 #if defined(BCM_56334_A0) 2791 { /* SOC_FORMAT_INT_PKTHDR_CPU_S_RF_BCM56334_A0fmt */ 2792 /* format PKTHDR_CPU_S_RFfmt */ 2793 /* nFields */ 1, 2794 /* *fields */ soc_PKTHDR_CPU_S_RF_BCM56334_A0fmt_fields, 2795 /* bits */ 54, 2796 /* flags */ 0, 2797 }, 2798 #endif /* chips */ 2799 2800 #if defined(BCM_56334_B0) 2801 { /* SOC_FORMAT_INT_PKTHDR_CPU_S_RF_BCM56334_B0fmt */ 2802 /* format PKTHDR_CPU_S_RFfmt */ 2803 /* nFields */ 1, 2804 /* *fields */ soc_PKTHDR_CPU_S_RF_BCM56334_A0fmt_fields, 2805 /* bits */ 54, 2806 /* flags */ 0, 2807 }, 2808 #endif /* chips */ 2809 2810 #if defined(BCM_56624_A0) 2811 { /* SOC_FORMAT_INT_PKTHDR_CPU_S_RF_BCM56624_A0fmt */ 2812 /* format PKTHDR_CPU_S_RFfmt */ 2813 /* nFields */ 1, 2814 /* *fields */ soc_PKTHDR_CPU_S_RF_BCM56624_A0fmt_fields, 2815 /* bits */ 128, 2816 /* flags */ 0, 2817 }, 2818 #endif /* chips */ 2819 2820 #if defined(BCM_56624_B0) 2821 { /* SOC_FORMAT_INT_PKTHDR_CPU_S_RF_BCM56624_B0fmt */ 2822 /* format PKTHDR_CPU_S_RFfmt */ 2823 /* nFields */ 1, 2824 /* *fields */ soc_PKTHDR_CPU_S_RF_BCM56624_A0fmt_fields, 2825 /* bits */ 128, 2826 /* flags */ 0, 2827 }, 2828 #endif /* chips */ 2829 2830 #if defined(BCM_56680_A0) 2831 { /* SOC_FORMAT_INT_PKTHDR_CPU_S_RF_BCM56680_A0fmt */ 2832 /* format PKTHDR_CPU_S_RFfmt */ 2833 /* nFields */ 1, 2834 /* *fields */ soc_PKTHDR_CPU_S_RF_BCM56624_A0fmt_fields, 2835 /* bits */ 128, 2836 /* flags */ 0, 2837 }, 2838 #endif /* chips */ 2839 2840 #if defined(BCM_56680_B0) 2841 { /* SOC_FORMAT_INT_PKTHDR_CPU_S_RF_BCM56680_B0fmt */ 2842 /* format PKTHDR_CPU_S_RFfmt */ 2843 /* nFields */ 1, 2844 /* *fields */ soc_PKTHDR_CPU_S_RF_BCM56624_A0fmt_fields, 2845 /* bits */ 128, 2846 /* flags */ 0, 2847 }, 2848 #endif /* chips */ 2849 2850 #if defined(BCM_56142_A0) 2851 { /* SOC_FORMAT_INT_PKTHDR_EXT_S_RFfmt */ 2852 /* format PKTHDR_EXT_S_RFfmt */ 2853 /* nFields */ 1, 2854 /* *fields */ soc_CELLDATA_S_RF_BCM56142_A0fmt_fields, 2855 /* bits */ 54, 2856 /* flags */ 0, 2857 }, 2858 #endif /* chips */ 2859 2860 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 2861 { /* SOC_FORMAT_INT_PKTLENGTH_S_RFfmt */ 2862 /* format PKTLENGTH_S_RFfmt */ 2863 /* nFields */ 1, 2864 /* *fields */ soc_PKTLENGTH_S_RFfmt_fields, 2865 /* bits */ 56, 2866 /* flags */ 0, 2867 }, 2868 #endif /* chips */ 2869 2870 #if defined(BCM_88732_A0) 2871 { /* SOC_FORMAT_INT_PKTLENGTH_S_RF_BCM88732_A0fmt */ 2872 /* format PKTLENGTH_S_RFfmt */ 2873 /* nFields */ 1, 2874 /* *fields */ soc_PKTLENGTH_S_RF_BCM88732_A0fmt_fields, 2875 /* bits */ 128, 2876 /* flags */ 0, 2877 }, 2878 #endif /* chips */ 2879 2880 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 2881 { /* SOC_FORMAT_INT_PKTLINK54_S_RFfmt */ 2882 /* format PKTLINK54_S_RFfmt */ 2883 /* nFields */ 1, 2884 /* *fields */ soc_PKTLINK54_S_RFfmt_fields, 2885 /* bits */ 128, 2886 /* flags */ 0, 2887 }, 2888 #endif /* chips */ 2889 2890 #if defined(BCM_56524_A0) 2891 { /* SOC_FORMAT_INT_PKTLINK54_S_RF_BCM56524_A0fmt */ 2892 /* format PKTLINK54_S_RFfmt */ 2893 /* nFields */ 1, 2894 /* *fields */ soc_PKTLINK54_S_RFfmt_fields, 2895 /* bits */ 128, 2896 /* flags */ 0, 2897 }, 2898 #endif /* chips */ 2899 2900 #if defined(BCM_56524_B0) 2901 { /* SOC_FORMAT_INT_PKTLINK54_S_RF_BCM56524_B0fmt */ 2902 /* format PKTLINK54_S_RFfmt */ 2903 /* nFields */ 1, 2904 /* *fields */ soc_PKTLINK54_S_RFfmt_fields, 2905 /* bits */ 128, 2906 /* flags */ 0, 2907 }, 2908 #endif /* chips */ 2909 2910 #if defined(BCM_56685_A0) 2911 { /* SOC_FORMAT_INT_PKTLINK54_S_RF_BCM56685_A0fmt */ 2912 /* format PKTLINK54_S_RFfmt */ 2913 /* nFields */ 1, 2914 /* *fields */ soc_PKTLINK54_S_RFfmt_fields, 2915 /* bits */ 128, 2916 /* flags */ 0, 2917 }, 2918 #endif /* chips */ 2919 2920 #if defined(BCM_56685_B0) 2921 { /* SOC_FORMAT_INT_PKTLINK54_S_RF_BCM56685_B0fmt */ 2922 /* format PKTLINK54_S_RFfmt */ 2923 /* nFields */ 1, 2924 /* *fields */ soc_PKTLINK54_S_RFfmt_fields, 2925 /* bits */ 128, 2926 /* flags */ 0, 2927 }, 2928 #endif /* chips */ 2929 2930 #if defined(BCM_56800_A0) 2931 { /* SOC_FORMAT_INT_PKTLINK_S_RFfmt */ 2932 /* format PKTLINK_S_RFfmt */ 2933 /* nFields */ 1, 2934 /* *fields */ soc_PKTLINK_S_RFfmt_fields, 2935 /* bits */ 84, 2936 /* flags */ 0, 2937 }, 2938 #endif /* chips */ 2939 2940 #if defined(BCM_56334_A0) 2941 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56334_A0fmt */ 2942 /* format PKTLINK_S_RFfmt */ 2943 /* nFields */ 1, 2944 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 2945 /* bits */ 36, 2946 /* flags */ 0, 2947 }, 2948 #endif /* chips */ 2949 2950 #if defined(BCM_56334_B0) 2951 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56334_B0fmt */ 2952 /* format PKTLINK_S_RFfmt */ 2953 /* nFields */ 1, 2954 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 2955 /* bits */ 36, 2956 /* flags */ 0, 2957 }, 2958 #endif /* chips */ 2959 2960 #if defined(BCM_56524_A0) 2961 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56524_A0fmt */ 2962 /* format PKTLINK_S_RFfmt */ 2963 /* nFields */ 1, 2964 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 2965 /* bits */ 36, 2966 /* flags */ 0, 2967 }, 2968 #endif /* chips */ 2969 2970 #if defined(BCM_56524_B0) 2971 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56524_B0fmt */ 2972 /* format PKTLINK_S_RFfmt */ 2973 /* nFields */ 1, 2974 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 2975 /* bits */ 36, 2976 /* flags */ 0, 2977 }, 2978 #endif /* chips */ 2979 2980 #if defined(BCM_56624_A0) 2981 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56624_A0fmt */ 2982 /* format PKTLINK_S_RFfmt */ 2983 /* nFields */ 1, 2984 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 2985 /* bits */ 36, 2986 /* flags */ 0, 2987 }, 2988 #endif /* chips */ 2989 2990 #if defined(BCM_56624_B0) 2991 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56624_B0fmt */ 2992 /* format PKTLINK_S_RFfmt */ 2993 /* nFields */ 1, 2994 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 2995 /* bits */ 36, 2996 /* flags */ 0, 2997 }, 2998 #endif /* chips */ 2999 3000 #if defined(BCM_56634_A0) 3001 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56634_A0fmt */ 3002 /* format PKTLINK_S_RFfmt */ 3003 /* nFields */ 1, 3004 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 3005 /* bits */ 36, 3006 /* flags */ 0, 3007 }, 3008 #endif /* chips */ 3009 3010 #if defined(BCM_56634_B0) 3011 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56634_B0fmt */ 3012 /* format PKTLINK_S_RFfmt */ 3013 /* nFields */ 1, 3014 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 3015 /* bits */ 36, 3016 /* flags */ 0, 3017 }, 3018 #endif /* chips */ 3019 3020 #if defined(BCM_56680_A0) 3021 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56680_A0fmt */ 3022 /* format PKTLINK_S_RFfmt */ 3023 /* nFields */ 1, 3024 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 3025 /* bits */ 36, 3026 /* flags */ 0, 3027 }, 3028 #endif /* chips */ 3029 3030 #if defined(BCM_56680_B0) 3031 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56680_B0fmt */ 3032 /* format PKTLINK_S_RFfmt */ 3033 /* nFields */ 1, 3034 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 3035 /* bits */ 36, 3036 /* flags */ 0, 3037 }, 3038 #endif /* chips */ 3039 3040 #if defined(BCM_56685_A0) 3041 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56685_A0fmt */ 3042 /* format PKTLINK_S_RFfmt */ 3043 /* nFields */ 1, 3044 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 3045 /* bits */ 36, 3046 /* flags */ 0, 3047 }, 3048 #endif /* chips */ 3049 3050 #if defined(BCM_56685_B0) 3051 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56685_B0fmt */ 3052 /* format PKTLINK_S_RFfmt */ 3053 /* nFields */ 1, 3054 /* *fields */ soc_PKTLINK_S_RF_BCM56624_A0fmt_fields, 3055 /* bits */ 36, 3056 /* flags */ 0, 3057 }, 3058 #endif /* chips */ 3059 3060 #if defined(BCM_56725_A0) 3061 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56725_A0fmt */ 3062 /* format PKTLINK_S_RFfmt */ 3063 /* nFields */ 1, 3064 /* *fields */ soc_PKTLINK_S_RF_BCM56820_A0fmt_fields, 3065 /* bits */ 112, 3066 /* flags */ 0, 3067 }, 3068 #endif /* chips */ 3069 3070 #if defined(BCM_56820_A0) 3071 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM56820_A0fmt */ 3072 /* format PKTLINK_S_RFfmt */ 3073 /* nFields */ 1, 3074 /* *fields */ soc_PKTLINK_S_RF_BCM56820_A0fmt_fields, 3075 /* bits */ 112, 3076 /* flags */ 0, 3077 }, 3078 #endif /* chips */ 3079 3080 #if defined(BCM_88732_A0) 3081 { /* SOC_FORMAT_INT_PKTLINK_S_RF_BCM88732_A0fmt */ 3082 /* format PKTLINK_S_RFfmt */ 3083 /* nFields */ 1, 3084 /* *fields */ soc_PKTLINK_S_RF_BCM88732_A0fmt_fields, 3085 /* bits */ 72, 3086 /* flags */ 0, 3087 }, 3088 #endif /* chips */ 3089 3090 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3091 defined(BCM_56870_A0) 3092 { /* SOC_FORMAT_INT_PKT_ECN_TO_INT_CN_MAPPING_INDEXfmt */ 3093 /* format PKT_ECN_TO_INT_CN_MAPPING_INDEXfmt */ 3094 /* nFields */ 3, 3095 /* *fields */ soc_PKT_ECN_TO_INT_CN_MAPPING_INDEXfmt_fields, 3096 /* bits */ 6, 3097 /* flags */ 0, 3098 }, 3099 #endif /* chips */ 3100 3101 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3102 defined(BCM_56870_A0) 3103 { /* SOC_FORMAT_INT_PKT_FLOW_ID_0_FORMATfmt */ 3104 /* format PKT_FLOW_ID_0_FORMATfmt */ 3105 /* nFields */ 7, 3106 /* *fields */ soc_PKT_FLOW_ID_0_FORMATfmt_fields, 3107 /* bits */ 12, 3108 /* flags */ 0, 3109 }, 3110 #endif /* chips */ 3111 3112 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3113 defined(BCM_56870_A0) 3114 { /* SOC_FORMAT_INT_PKT_FLOW_ID_1_FORMATfmt */ 3115 /* format PKT_FLOW_ID_1_FORMATfmt */ 3116 /* nFields */ 7, 3117 /* *fields */ soc_PKT_FLOW_ID_1_FORMATfmt_fields, 3118 /* bits */ 14, 3119 /* flags */ 0, 3120 }, 3121 #endif /* chips */ 3122 3123 #if defined(BCM_56870_A0) 3124 { /* SOC_FORMAT_INT_PKT_FLOW_ID_2_FORMATfmt */ 3125 /* format PKT_FLOW_ID_2_FORMATfmt */ 3126 /* nFields */ 7, 3127 /* *fields */ soc_PKT_FLOW_ID_1_FORMATfmt_fields, 3128 /* bits */ 14, 3129 /* flags */ 0, 3130 }, 3131 #endif /* chips */ 3132 3133 #if defined(BCM_56370_A0) 3134 { /* SOC_FORMAT_INT_PKT_FLOW_ID_2_FORMAT_BCM56370_A0fmt */ 3135 /* format PKT_FLOW_ID_2_FORMATfmt */ 3136 /* nFields */ 7, 3137 /* *fields */ soc_PKT_FLOW_ID_1_FORMATfmt_fields, 3138 /* bits */ 14, 3139 /* flags */ 0, 3140 }, 3141 #endif /* chips */ 3142 3143 #if defined(BCM_56770_A0) 3144 { /* SOC_FORMAT_INT_PKT_FLOW_ID_2_FORMAT_BCM56770_A0fmt */ 3145 /* format PKT_FLOW_ID_2_FORMATfmt */ 3146 /* nFields */ 7, 3147 /* *fields */ soc_PKT_FLOW_ID_1_FORMATfmt_fields, 3148 /* bits */ 14, 3149 /* flags */ 0, 3150 }, 3151 #endif /* chips */ 3152 3153 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3154 defined(BCM_56870_A0) 3155 { /* SOC_FORMAT_INT_PKT_FLOW_SELECT_CTRL_ID_1_FORMATfmt */ 3156 /* format PKT_FLOW_SELECT_CTRL_ID_1_FORMATfmt */ 3157 /* nFields */ 9, 3158 /* *fields */ soc_PKT_FLOW_SELECT_CTRL_ID_1_FORMATfmt_fields, 3159 /* bits */ 16, 3160 /* flags */ 0, 3161 }, 3162 #endif /* chips */ 3163 3164 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3165 defined(BCM_56870_A0) 3166 { /* SOC_FORMAT_INT_PKT_FLOW_SELECT_TCAM_0_DOPfmt */ 3167 /* format PKT_FLOW_SELECT_TCAM_0_DOPfmt */ 3168 /* nFields */ 3, 3169 /* *fields */ soc_PKT_FLOW_SELECT_TCAM_0_DOPfmt_fields, 3170 /* bits */ 32, 3171 /* flags */ 0, 3172 }, 3173 #endif /* chips */ 3174 3175 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3176 defined(BCM_56870_A0) 3177 { /* SOC_FORMAT_INT_PKT_FLOW_SELECT_TCAM_1_DOP_DOPfmt */ 3178 /* format PKT_FLOW_SELECT_TCAM_1_DOP_DOPfmt */ 3179 /* nFields */ 5, 3180 /* *fields */ soc_PKT_FLOW_SELECT_TCAM_1_DOP_DOPfmt_fields, 3181 /* bits */ 32, 3182 /* flags */ 0, 3183 }, 3184 #endif /* chips */ 3185 3186 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 3187 { /* SOC_FORMAT_INT_PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOPfmt */ 3188 /* format PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOPfmt */ 3189 /* nFields */ 7, 3190 /* *fields */ soc_PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOPfmt_fields, 3191 /* bits */ 64, 3192 /* flags */ 0, 3193 }, 3194 #endif /* chips */ 3195 3196 #if defined(BCM_56370_A0) 3197 { /* SOC_FORMAT_INT_PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOP_BCM56370_A0fmt */ 3198 /* format PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOPfmt */ 3199 /* nFields */ 7, 3200 /* *fields */ soc_PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOP_BCM56370_A0fmt_fields, 3201 /* bits */ 64, 3202 /* flags */ 0, 3203 }, 3204 #endif /* chips */ 3205 3206 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3207 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 3208 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 3209 defined(BCM_56980_A0) || defined(BCM_56980_B0) 3210 { /* SOC_FORMAT_INT_PKT_FORWARDING_TYPEfmt */ 3211 /* format PKT_FORWARDING_TYPEfmt */ 3212 /* nFields */ 1, 3213 /* *fields */ soc_PKT_FORWARDING_TYPEfmt_fields, 3214 /* bits */ 4, 3215 /* flags */ 0, 3216 }, 3217 #endif /* chips */ 3218 3219 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3220 defined(BCM_56870_A0) 3221 { /* SOC_FORMAT_INT_PKT_PROC_DROP_VECTORfmt */ 3222 /* format PKT_PROC_DROP_VECTORfmt */ 3223 /* nFields */ 41, 3224 /* *fields */ soc_PKT_PROC_DROP_VECTORfmt_fields, 3225 /* bits */ 96, 3226 /* flags */ 0, 3227 }, 3228 #endif /* chips */ 3229 3230 #if defined(BCM_56980_A0) 3231 { /* SOC_FORMAT_INT_PKT_PROC_DROP_VECTOR_BCM56980_A0fmt */ 3232 /* format PKT_PROC_DROP_VECTORfmt */ 3233 /* nFields */ 33, 3234 /* *fields */ soc_PKT_PROC_DROP_VECTOR_BCM56980_A0fmt_fields, 3235 /* bits */ 64, 3236 /* flags */ 0, 3237 }, 3238 #endif /* chips */ 3239 3240 #if defined(BCM_56980_B0) 3241 { /* SOC_FORMAT_INT_PKT_PROC_DROP_VECTOR_BCM56980_B0fmt */ 3242 /* format PKT_PROC_DROP_VECTORfmt */ 3243 /* nFields */ 33, 3244 /* *fields */ soc_PKT_PROC_DROP_VECTOR_BCM56980_A0fmt_fields, 3245 /* bits */ 64, 3246 /* flags */ 0, 3247 }, 3248 #endif /* chips */ 3249 3250 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3251 { /* SOC_FORMAT_INT_PM_TO_EDB_TO_PM_PORT_MODEfmt */ 3252 /* format PM_TO_EDB_TO_PM_PORT_MODEfmt */ 3253 /* nFields */ 1, 3254 /* *fields */ soc_PM_TO_EDB_TO_PM_PORT_MODEfmt_fields, 3255 /* bits */ 4, 3256 /* flags */ 0, 3257 }, 3258 #endif /* chips */ 3259 3260 #if defined(BCM_56970_A0) 3261 { /* SOC_FORMAT_INT_PORT_AVG_QUALITY_MEASURE_COV_DEFSfmt */ 3262 /* format PORT_AVG_QUALITY_MEASURE_COV_DEFSfmt */ 3263 /* nFields */ 6, 3264 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 3265 /* bits */ 14, 3266 /* flags */ 0, 3267 }, 3268 #endif /* chips */ 3269 3270 #if defined(BCM_56370_A0) 3271 { /* SOC_FORMAT_INT_PORT_AVG_QUALITY_MEASURE_COV_DEFS_BCM56370_A0fmt */ 3272 /* format PORT_AVG_QUALITY_MEASURE_COV_DEFSfmt */ 3273 /* nFields */ 6, 3274 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 3275 /* bits */ 14, 3276 /* flags */ 0, 3277 }, 3278 #endif /* chips */ 3279 3280 #if defined(BCM_56770_A0) 3281 { /* SOC_FORMAT_INT_PORT_AVG_QUALITY_MEASURE_COV_DEFS_BCM56770_A0fmt */ 3282 /* format PORT_AVG_QUALITY_MEASURE_COV_DEFSfmt */ 3283 /* nFields */ 6, 3284 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 3285 /* bits */ 14, 3286 /* flags */ 0, 3287 }, 3288 #endif /* chips */ 3289 3290 #if defined(BCM_56870_A0) 3291 { /* SOC_FORMAT_INT_PORT_AVG_QUALITY_MEASURE_COV_DEFS_BCM56870_A0fmt */ 3292 /* format PORT_AVG_QUALITY_MEASURE_COV_DEFSfmt */ 3293 /* nFields */ 6, 3294 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 3295 /* bits */ 14, 3296 /* flags */ 0, 3297 }, 3298 #endif /* chips */ 3299 3300 #if defined(BCM_56980_A0) 3301 { /* SOC_FORMAT_INT_PORT_AVG_QUALITY_MEASURE_COV_DEFS_BCM56980_A0fmt */ 3302 /* format PORT_AVG_QUALITY_MEASURE_COV_DEFSfmt */ 3303 /* nFields */ 6, 3304 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 3305 /* bits */ 14, 3306 /* flags */ 0, 3307 }, 3308 #endif /* chips */ 3309 3310 #if defined(BCM_56980_B0) 3311 { /* SOC_FORMAT_INT_PORT_AVG_QUALITY_MEASURE_COV_DEFS_BCM56980_B0fmt */ 3312 /* format PORT_AVG_QUALITY_MEASURE_COV_DEFSfmt */ 3313 /* nFields */ 6, 3314 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 3315 /* bits */ 14, 3316 /* flags */ 0, 3317 }, 3318 #endif /* chips */ 3319 3320 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 3321 defined(BCM_56970_A0) 3322 { /* SOC_FORMAT_INT_PORT_DEMAND_STATEfmt */ 3323 /* format PORT_DEMAND_STATEfmt */ 3324 /* nFields */ 3, 3325 /* *fields */ soc_PORT_DEMAND_STATEfmt_fields, 3326 /* bits */ 6, 3327 /* flags */ 0, 3328 }, 3329 #endif /* chips */ 3330 3331 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 3332 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1fmt */ 3333 /* format PORT_FC_BEAT_1fmt */ 3334 /* nFields */ 3, 3335 /* *fields */ soc_PORT_FC_BEAT_1fmt_fields, 3336 /* bits */ 16, 3337 /* flags */ 0, 3338 }, 3339 #endif /* chips */ 3340 3341 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 3342 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2fmt */ 3343 /* format PORT_FC_BEAT_2fmt */ 3344 /* nFields */ 2, 3345 /* *fields */ soc_PORT_FC_BEAT_2fmt_fields, 3346 /* bits */ 12, 3347 /* flags */ 0, 3348 }, 3349 #endif /* chips */ 3350 3351 #if defined(BCM_56370_A0) 3352 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56370_A0fmt */ 3353 /* format PORT_FC_BEAT_1fmt */ 3354 /* nFields */ 3, 3355 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3356 /* bits */ 16, 3357 /* flags */ 0, 3358 }, 3359 #endif /* chips */ 3360 3361 #if defined(BCM_56560_A0) 3362 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56560_A0fmt */ 3363 /* format PORT_FC_BEAT_1fmt */ 3364 /* nFields */ 3, 3365 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3366 /* bits */ 16, 3367 /* flags */ 0, 3368 }, 3369 #endif /* chips */ 3370 3371 #if defined(BCM_56560_B0) 3372 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56560_B0fmt */ 3373 /* format PORT_FC_BEAT_1fmt */ 3374 /* nFields */ 3, 3375 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3376 /* bits */ 16, 3377 /* flags */ 0, 3378 }, 3379 #endif /* chips */ 3380 3381 #if defined(BCM_56670_A0) 3382 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56670_A0fmt */ 3383 /* format PORT_FC_BEAT_1fmt */ 3384 /* nFields */ 3, 3385 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3386 /* bits */ 16, 3387 /* flags */ 0, 3388 }, 3389 #endif /* chips */ 3390 3391 #if defined(BCM_56670_B0) 3392 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56670_B0fmt */ 3393 /* format PORT_FC_BEAT_1fmt */ 3394 /* nFields */ 3, 3395 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3396 /* bits */ 16, 3397 /* flags */ 0, 3398 }, 3399 #endif /* chips */ 3400 3401 #if defined(BCM_56770_A0) 3402 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56770_A0fmt */ 3403 /* format PORT_FC_BEAT_1fmt */ 3404 /* nFields */ 3, 3405 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3406 /* bits */ 16, 3407 /* flags */ 0, 3408 }, 3409 #endif /* chips */ 3410 3411 #if defined(BCM_56870_A0) 3412 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56870_A0fmt */ 3413 /* format PORT_FC_BEAT_1fmt */ 3414 /* nFields */ 3, 3415 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3416 /* bits */ 16, 3417 /* flags */ 0, 3418 }, 3419 #endif /* chips */ 3420 3421 #if defined(BCM_56960_A0) 3422 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56960_A0fmt */ 3423 /* format PORT_FC_BEAT_1fmt */ 3424 /* nFields */ 3, 3425 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3426 /* bits */ 16, 3427 /* flags */ 0, 3428 }, 3429 #endif /* chips */ 3430 3431 #if defined(BCM_56965_A0) 3432 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56965_A0fmt */ 3433 /* format PORT_FC_BEAT_1fmt */ 3434 /* nFields */ 3, 3435 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3436 /* bits */ 16, 3437 /* flags */ 0, 3438 }, 3439 #endif /* chips */ 3440 3441 #if defined(BCM_56970_A0) 3442 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56970_A0fmt */ 3443 /* format PORT_FC_BEAT_1fmt */ 3444 /* nFields */ 3, 3445 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3446 /* bits */ 16, 3447 /* flags */ 0, 3448 }, 3449 #endif /* chips */ 3450 3451 #if defined(BCM_56980_A0) 3452 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56980_A0fmt */ 3453 /* format PORT_FC_BEAT_1fmt */ 3454 /* nFields */ 3, 3455 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3456 /* bits */ 16, 3457 /* flags */ 0, 3458 }, 3459 #endif /* chips */ 3460 3461 #if defined(BCM_56980_B0) 3462 { /* SOC_FORMAT_INT_PORT_FC_BEAT_1_BCM56980_B0fmt */ 3463 /* format PORT_FC_BEAT_1fmt */ 3464 /* nFields */ 3, 3465 /* *fields */ soc_PORT_FC_BEAT_1_BCM56960_A0fmt_fields, 3466 /* bits */ 16, 3467 /* flags */ 0, 3468 }, 3469 #endif /* chips */ 3470 3471 #if defined(BCM_56370_A0) 3472 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56370_A0fmt */ 3473 /* format PORT_FC_BEAT_2fmt */ 3474 /* nFields */ 2, 3475 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3476 /* bits */ 12, 3477 /* flags */ 0, 3478 }, 3479 #endif /* chips */ 3480 3481 #if defined(BCM_56560_A0) 3482 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56560_A0fmt */ 3483 /* format PORT_FC_BEAT_2fmt */ 3484 /* nFields */ 2, 3485 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3486 /* bits */ 12, 3487 /* flags */ 0, 3488 }, 3489 #endif /* chips */ 3490 3491 #if defined(BCM_56560_B0) 3492 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56560_B0fmt */ 3493 /* format PORT_FC_BEAT_2fmt */ 3494 /* nFields */ 2, 3495 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3496 /* bits */ 12, 3497 /* flags */ 0, 3498 }, 3499 #endif /* chips */ 3500 3501 #if defined(BCM_56670_A0) 3502 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56670_A0fmt */ 3503 /* format PORT_FC_BEAT_2fmt */ 3504 /* nFields */ 2, 3505 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3506 /* bits */ 12, 3507 /* flags */ 0, 3508 }, 3509 #endif /* chips */ 3510 3511 #if defined(BCM_56670_B0) 3512 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56670_B0fmt */ 3513 /* format PORT_FC_BEAT_2fmt */ 3514 /* nFields */ 2, 3515 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3516 /* bits */ 12, 3517 /* flags */ 0, 3518 }, 3519 #endif /* chips */ 3520 3521 #if defined(BCM_56770_A0) 3522 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56770_A0fmt */ 3523 /* format PORT_FC_BEAT_2fmt */ 3524 /* nFields */ 2, 3525 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3526 /* bits */ 12, 3527 /* flags */ 0, 3528 }, 3529 #endif /* chips */ 3530 3531 #if defined(BCM_56870_A0) 3532 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56870_A0fmt */ 3533 /* format PORT_FC_BEAT_2fmt */ 3534 /* nFields */ 2, 3535 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3536 /* bits */ 12, 3537 /* flags */ 0, 3538 }, 3539 #endif /* chips */ 3540 3541 #if defined(BCM_56960_A0) 3542 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56960_A0fmt */ 3543 /* format PORT_FC_BEAT_2fmt */ 3544 /* nFields */ 2, 3545 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3546 /* bits */ 12, 3547 /* flags */ 0, 3548 }, 3549 #endif /* chips */ 3550 3551 #if defined(BCM_56965_A0) 3552 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56965_A0fmt */ 3553 /* format PORT_FC_BEAT_2fmt */ 3554 /* nFields */ 2, 3555 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3556 /* bits */ 12, 3557 /* flags */ 0, 3558 }, 3559 #endif /* chips */ 3560 3561 #if defined(BCM_56970_A0) 3562 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56970_A0fmt */ 3563 /* format PORT_FC_BEAT_2fmt */ 3564 /* nFields */ 2, 3565 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3566 /* bits */ 12, 3567 /* flags */ 0, 3568 }, 3569 #endif /* chips */ 3570 3571 #if defined(BCM_56980_A0) 3572 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56980_A0fmt */ 3573 /* format PORT_FC_BEAT_2fmt */ 3574 /* nFields */ 2, 3575 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3576 /* bits */ 12, 3577 /* flags */ 0, 3578 }, 3579 #endif /* chips */ 3580 3581 #if defined(BCM_56980_B0) 3582 { /* SOC_FORMAT_INT_PORT_FC_BEAT_2_BCM56980_B0fmt */ 3583 /* format PORT_FC_BEAT_2fmt */ 3584 /* nFields */ 2, 3585 /* *fields */ soc_PORT_FC_BEAT_2_BCM56960_A0fmt_fields, 3586 /* bits */ 12, 3587 /* flags */ 0, 3588 }, 3589 #endif /* chips */ 3590 3591 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 3592 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPEfmt */ 3593 /* format PORT_FC_MSGTYPEfmt */ 3594 /* nFields */ 1, 3595 /* *fields */ soc_PORT_FC_MSGTYPEfmt_fields, 3596 /* bits */ 2, 3597 /* flags */ 0, 3598 }, 3599 #endif /* chips */ 3600 3601 #if defined(BCM_56370_A0) 3602 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56370_A0fmt */ 3603 /* format PORT_FC_MSGTYPEfmt */ 3604 /* nFields */ 1, 3605 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3606 /* bits */ 2, 3607 /* flags */ 0, 3608 }, 3609 #endif /* chips */ 3610 3611 #if defined(BCM_56560_A0) 3612 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56560_A0fmt */ 3613 /* format PORT_FC_MSGTYPEfmt */ 3614 /* nFields */ 1, 3615 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3616 /* bits */ 2, 3617 /* flags */ 0, 3618 }, 3619 #endif /* chips */ 3620 3621 #if defined(BCM_56560_B0) 3622 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56560_B0fmt */ 3623 /* format PORT_FC_MSGTYPEfmt */ 3624 /* nFields */ 1, 3625 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3626 /* bits */ 2, 3627 /* flags */ 0, 3628 }, 3629 #endif /* chips */ 3630 3631 #if defined(BCM_56670_A0) 3632 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56670_A0fmt */ 3633 /* format PORT_FC_MSGTYPEfmt */ 3634 /* nFields */ 1, 3635 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3636 /* bits */ 2, 3637 /* flags */ 0, 3638 }, 3639 #endif /* chips */ 3640 3641 #if defined(BCM_56670_B0) 3642 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56670_B0fmt */ 3643 /* format PORT_FC_MSGTYPEfmt */ 3644 /* nFields */ 1, 3645 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3646 /* bits */ 2, 3647 /* flags */ 0, 3648 }, 3649 #endif /* chips */ 3650 3651 #if defined(BCM_56770_A0) 3652 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56770_A0fmt */ 3653 /* format PORT_FC_MSGTYPEfmt */ 3654 /* nFields */ 1, 3655 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3656 /* bits */ 2, 3657 /* flags */ 0, 3658 }, 3659 #endif /* chips */ 3660 3661 #if defined(BCM_56870_A0) 3662 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56870_A0fmt */ 3663 /* format PORT_FC_MSGTYPEfmt */ 3664 /* nFields */ 1, 3665 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3666 /* bits */ 2, 3667 /* flags */ 0, 3668 }, 3669 #endif /* chips */ 3670 3671 #if defined(BCM_56960_A0) 3672 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56960_A0fmt */ 3673 /* format PORT_FC_MSGTYPEfmt */ 3674 /* nFields */ 1, 3675 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3676 /* bits */ 2, 3677 /* flags */ 0, 3678 }, 3679 #endif /* chips */ 3680 3681 #if defined(BCM_56965_A0) 3682 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56965_A0fmt */ 3683 /* format PORT_FC_MSGTYPEfmt */ 3684 /* nFields */ 1, 3685 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3686 /* bits */ 2, 3687 /* flags */ 0, 3688 }, 3689 #endif /* chips */ 3690 3691 #if defined(BCM_56970_A0) 3692 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56970_A0fmt */ 3693 /* format PORT_FC_MSGTYPEfmt */ 3694 /* nFields */ 1, 3695 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3696 /* bits */ 2, 3697 /* flags */ 0, 3698 }, 3699 #endif /* chips */ 3700 3701 #if defined(BCM_56980_A0) 3702 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56980_A0fmt */ 3703 /* format PORT_FC_MSGTYPEfmt */ 3704 /* nFields */ 1, 3705 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3706 /* bits */ 2, 3707 /* flags */ 0, 3708 }, 3709 #endif /* chips */ 3710 3711 #if defined(BCM_56980_B0) 3712 { /* SOC_FORMAT_INT_PORT_FC_MSGTYPE_BCM56980_B0fmt */ 3713 /* format PORT_FC_MSGTYPEfmt */ 3714 /* nFields */ 1, 3715 /* *fields */ soc_PORT_FC_MSGTYPE_BCM56960_A0fmt_fields, 3716 /* bits */ 2, 3717 /* flags */ 0, 3718 }, 3719 #endif /* chips */ 3720 3721 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 3722 { /* SOC_FORMAT_INT_PORT_META_DATA_IN_INFOfmt */ 3723 /* format PORT_META_DATA_IN_INFOfmt */ 3724 /* nFields */ 18, 3725 /* *fields */ soc_PORT_META_DATA_IN_INFOfmt_fields, 3726 /* bits */ 77, 3727 /* flags */ 0, 3728 }, 3729 #endif /* chips */ 3730 3731 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 3732 { /* SOC_FORMAT_INT_PORT_META_DATA_OUT_INFOfmt */ 3733 /* format PORT_META_DATA_OUT_INFOfmt */ 3734 /* nFields */ 17, 3735 /* *fields */ soc_PORT_META_DATA_OUT_INFOfmt_fields, 3736 /* bits */ 81, 3737 /* flags */ 0, 3738 }, 3739 #endif /* chips */ 3740 3741 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 3742 defined(BCM_56504_B0) || defined(BCM_56514_A0) 3743 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORDfmt */ 3744 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3745 /* nFields */ 9, 3746 /* *fields */ soc_PORT_TO_IP_CONTROL_WORDfmt_fields, 3747 /* bits */ 256, 3748 /* flags */ 0, 3749 }, 3750 #endif /* chips */ 3751 3752 #if defined(BCM_53314_A0) 3753 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM53314_A0fmt */ 3754 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3755 /* nFields */ 10, 3756 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM53314_A0fmt_fields, 3757 /* bits */ 256, 3758 /* flags */ 0, 3759 }, 3760 #endif /* chips */ 3761 3762 #if defined(BCM_53324_A0) 3763 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM53324_A0fmt */ 3764 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3765 /* nFields */ 10, 3766 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM53314_A0fmt_fields, 3767 /* bits */ 256, 3768 /* flags */ 0, 3769 }, 3770 #endif /* chips */ 3771 3772 #if defined(BCM_53400_A0) 3773 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM53400_A0fmt */ 3774 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3775 /* nFields */ 10, 3776 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM53400_A0fmt_fields, 3777 /* bits */ 32, 3778 /* flags */ 0, 3779 }, 3780 #endif /* chips */ 3781 3782 #if defined(BCM_53540_A0) 3783 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM53540_A0fmt */ 3784 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3785 /* nFields */ 11, 3786 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56160_A0fmt_fields, 3787 /* bits */ 48, 3788 /* flags */ 0, 3789 }, 3790 #endif /* chips */ 3791 3792 #if defined(BCM_53570_A0) 3793 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM53570_A0fmt */ 3794 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3795 /* nFields */ 12, 3796 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM53570_A0fmt_fields, 3797 /* bits */ 48, 3798 /* flags */ 0, 3799 }, 3800 #endif /* chips */ 3801 3802 #if defined(BCM_53570_B0) 3803 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM53570_B0fmt */ 3804 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3805 /* nFields */ 12, 3806 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM53570_A0fmt_fields, 3807 /* bits */ 48, 3808 /* flags */ 0, 3809 }, 3810 #endif /* chips */ 3811 3812 #if defined(BCM_56142_A0) 3813 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56142_A0fmt */ 3814 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3815 /* nFields */ 10, 3816 /* *fields */ soc_XGPORT_TO_IP_CONTROL_WORD_BCM56634_A0fmt_fields, 3817 /* bits */ 32, 3818 /* flags */ 0, 3819 }, 3820 #endif /* chips */ 3821 3822 #if defined(BCM_56150_A0) 3823 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56150_A0fmt */ 3824 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3825 /* nFields */ 10, 3826 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56150_A0fmt_fields, 3827 /* bits */ 32, 3828 /* flags */ 0, 3829 }, 3830 #endif /* chips */ 3831 3832 #if defined(BCM_56160_A0) 3833 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56160_A0fmt */ 3834 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3835 /* nFields */ 11, 3836 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56160_A0fmt_fields, 3837 /* bits */ 48, 3838 /* flags */ 0, 3839 }, 3840 #endif /* chips */ 3841 3842 #if defined(BCM_56224_A0) 3843 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56224_A0fmt */ 3844 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3845 /* nFields */ 9, 3846 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56224_A0fmt_fields, 3847 /* bits */ 256, 3848 /* flags */ 0, 3849 }, 3850 #endif /* chips */ 3851 3852 #if defined(BCM_56224_B0) 3853 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56224_B0fmt */ 3854 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3855 /* nFields */ 9, 3856 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56224_A0fmt_fields, 3857 /* bits */ 256, 3858 /* flags */ 0, 3859 }, 3860 #endif /* chips */ 3861 3862 #if defined(BCM_56260_A0) 3863 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56260_A0fmt */ 3864 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3865 /* nFields */ 13, 3866 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56260_A0fmt_fields, 3867 /* bits */ 32, 3868 /* flags */ 0, 3869 }, 3870 #endif /* chips */ 3871 3872 #if defined(BCM_56260_B0) 3873 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56260_B0fmt */ 3874 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3875 /* nFields */ 13, 3876 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56260_A0fmt_fields, 3877 /* bits */ 32, 3878 /* flags */ 0, 3879 }, 3880 #endif /* chips */ 3881 3882 #if defined(BCM_56270_A0) 3883 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56270_A0fmt */ 3884 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3885 /* nFields */ 13, 3886 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56260_A0fmt_fields, 3887 /* bits */ 32, 3888 /* flags */ 0, 3889 }, 3890 #endif /* chips */ 3891 3892 #if defined(BCM_56334_A0) 3893 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56334_A0fmt */ 3894 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3895 /* nFields */ 10, 3896 /* *fields */ soc_XGPORT_TO_IP_CONTROL_WORD_BCM56634_A0fmt_fields, 3897 /* bits */ 32, 3898 /* flags */ 0, 3899 }, 3900 #endif /* chips */ 3901 3902 #if defined(BCM_56334_B0) 3903 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56334_B0fmt */ 3904 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3905 /* nFields */ 10, 3906 /* *fields */ soc_XGPORT_TO_IP_CONTROL_WORD_BCM56634_A0fmt_fields, 3907 /* bits */ 32, 3908 /* flags */ 0, 3909 }, 3910 #endif /* chips */ 3911 3912 #if defined(BCM_56440_A0) 3913 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56440_A0fmt */ 3914 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3915 /* nFields */ 10, 3916 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56440_A0fmt_fields, 3917 /* bits */ 32, 3918 /* flags */ 0, 3919 }, 3920 #endif /* chips */ 3921 3922 #if defined(BCM_56440_B0) 3923 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56440_B0fmt */ 3924 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3925 /* nFields */ 10, 3926 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56440_A0fmt_fields, 3927 /* bits */ 32, 3928 /* flags */ 0, 3929 }, 3930 #endif /* chips */ 3931 3932 #if defined(BCM_56450_A0) 3933 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56450_A0fmt */ 3934 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3935 /* nFields */ 13, 3936 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56450_A0fmt_fields, 3937 /* bits */ 32, 3938 /* flags */ 0, 3939 }, 3940 #endif /* chips */ 3941 3942 #if defined(BCM_56450_B0) 3943 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56450_B0fmt */ 3944 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3945 /* nFields */ 13, 3946 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56450_A0fmt_fields, 3947 /* bits */ 32, 3948 /* flags */ 0, 3949 }, 3950 #endif /* chips */ 3951 3952 #if defined(BCM_56450_B1) 3953 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56450_B1fmt */ 3954 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3955 /* nFields */ 13, 3956 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56450_A0fmt_fields, 3957 /* bits */ 32, 3958 /* flags */ 0, 3959 }, 3960 #endif /* chips */ 3961 3962 #if defined(BCM_56725_A0) 3963 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56725_A0fmt */ 3964 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3965 /* nFields */ 8, 3966 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56820_A0fmt_fields, 3967 /* bits */ 160, 3968 /* flags */ 0, 3969 }, 3970 #endif /* chips */ 3971 3972 #if defined(BCM_56800_A0) 3973 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56800_A0fmt */ 3974 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3975 /* nFields */ 6, 3976 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56800_A0fmt_fields, 3977 /* bits */ 13, 3978 /* flags */ 0, 3979 }, 3980 #endif /* chips */ 3981 3982 #if defined(BCM_56820_A0) 3983 { /* SOC_FORMAT_INT_PORT_TO_IP_CONTROL_WORD_BCM56820_A0fmt */ 3984 /* format PORT_TO_IP_CONTROL_WORDfmt */ 3985 /* nFields */ 8, 3986 /* *fields */ soc_PORT_TO_IP_CONTROL_WORD_BCM56820_A0fmt_fields, 3987 /* bits */ 160, 3988 /* flags */ 0, 3989 }, 3990 #endif /* chips */ 3991 3992 #if defined(BCM_88732_A0) 3993 { /* SOC_FORMAT_INT_PORT_TO_PE_IFfmt */ 3994 /* format PORT_TO_PE_IFfmt */ 3995 /* nFields */ 11, 3996 /* *fields */ soc_PORT_TO_PE_IFfmt_fields, 3997 /* bits */ 54, 3998 /* flags */ 0, 3999 }, 4000 #endif /* chips */ 4001 4002 #if defined(BCM_56524_A0) || defined(BCM_56624_A0) || \ 4003 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 4004 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 4005 defined(BCM_56685_A0) || defined(BCM_56685_B0) 4006 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDSfmt */ 4007 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4008 /* nFields */ 8, 4009 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDSfmt_fields, 4010 /* bits */ 62, 4011 /* flags */ 0, 4012 }, 4013 #endif /* chips */ 4014 4015 #if defined(BCM_56334_A0) 4016 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDS_BCM56334_A0fmt */ 4017 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4018 /* nFields */ 8, 4019 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDS_BCM56820_A0fmt_fields, 4020 /* bits */ 58, 4021 /* flags */ 0, 4022 }, 4023 #endif /* chips */ 4024 4025 #if defined(BCM_56334_B0) 4026 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDS_BCM56334_B0fmt */ 4027 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4028 /* nFields */ 8, 4029 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDS_BCM56820_A0fmt_fields, 4030 /* bits */ 58, 4031 /* flags */ 0, 4032 }, 4033 #endif /* chips */ 4034 4035 #if defined(BCM_56524_B0) 4036 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDS_BCM56524_B0fmt */ 4037 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4038 /* nFields */ 8, 4039 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDSfmt_fields, 4040 /* bits */ 62, 4041 /* flags */ 0, 4042 }, 4043 #endif /* chips */ 4044 4045 #if defined(BCM_56680_B0) 4046 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDS_BCM56680_B0fmt */ 4047 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4048 /* nFields */ 8, 4049 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDSfmt_fields, 4050 /* bits */ 62, 4051 /* flags */ 0, 4052 }, 4053 #endif /* chips */ 4054 4055 #if defined(BCM_56725_A0) 4056 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDS_BCM56725_A0fmt */ 4057 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4058 /* nFields */ 8, 4059 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDS_BCM56820_A0fmt_fields, 4060 /* bits */ 58, 4061 /* flags */ 0, 4062 }, 4063 #endif /* chips */ 4064 4065 #if defined(BCM_56820_A0) 4066 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDS_BCM56820_A0fmt */ 4067 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4068 /* nFields */ 8, 4069 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDS_BCM56820_A0fmt_fields, 4070 /* bits */ 58, 4071 /* flags */ 0, 4072 }, 4073 #endif /* chips */ 4074 4075 #if defined(BCM_88732_A0) 4076 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_0_FIELDS_BCM88732_A0fmt */ 4077 /* format PORT_WRED_CELL_THD_0_FIELDSfmt */ 4078 /* nFields */ 13, 4079 /* *fields */ soc_PORT_WRED_CELL_THD_0_FIELDS_BCM88732_A0fmt_fields, 4080 /* bits */ 76, 4081 /* flags */ 0, 4082 }, 4083 #endif /* chips */ 4084 4085 #if defined(BCM_56524_A0) || defined(BCM_56624_A0) || \ 4086 defined(BCM_56634_A0) || defined(BCM_56634_B0) 4087 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDSfmt */ 4088 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4089 /* nFields */ 8, 4090 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDSfmt_fields, 4091 /* bits */ 62, 4092 /* flags */ 0, 4093 }, 4094 #endif /* chips */ 4095 4096 #if defined(BCM_56334_A0) 4097 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56334_A0fmt */ 4098 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4099 /* nFields */ 8, 4100 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDS_BCM56820_A0fmt_fields, 4101 /* bits */ 58, 4102 /* flags */ 0, 4103 }, 4104 #endif /* chips */ 4105 4106 #if defined(BCM_56334_B0) 4107 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56334_B0fmt */ 4108 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4109 /* nFields */ 8, 4110 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDS_BCM56820_A0fmt_fields, 4111 /* bits */ 58, 4112 /* flags */ 0, 4113 }, 4114 #endif /* chips */ 4115 4116 #if defined(BCM_56524_B0) 4117 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56524_B0fmt */ 4118 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4119 /* nFields */ 8, 4120 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDSfmt_fields, 4121 /* bits */ 62, 4122 /* flags */ 0, 4123 }, 4124 #endif /* chips */ 4125 4126 #if defined(BCM_56624_B0) 4127 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56624_B0fmt */ 4128 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4129 /* nFields */ 8, 4130 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDSfmt_fields, 4131 /* bits */ 62, 4132 /* flags */ 0, 4133 }, 4134 #endif /* chips */ 4135 4136 #if defined(BCM_56680_A0) 4137 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56680_A0fmt */ 4138 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4139 /* nFields */ 8, 4140 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDSfmt_fields, 4141 /* bits */ 62, 4142 /* flags */ 0, 4143 }, 4144 #endif /* chips */ 4145 4146 #if defined(BCM_56680_B0) 4147 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56680_B0fmt */ 4148 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4149 /* nFields */ 8, 4150 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDSfmt_fields, 4151 /* bits */ 62, 4152 /* flags */ 0, 4153 }, 4154 #endif /* chips */ 4155 4156 #if defined(BCM_56685_A0) 4157 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56685_A0fmt */ 4158 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4159 /* nFields */ 8, 4160 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDSfmt_fields, 4161 /* bits */ 62, 4162 /* flags */ 0, 4163 }, 4164 #endif /* chips */ 4165 4166 #if defined(BCM_56685_B0) 4167 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56685_B0fmt */ 4168 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4169 /* nFields */ 8, 4170 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDSfmt_fields, 4171 /* bits */ 62, 4172 /* flags */ 0, 4173 }, 4174 #endif /* chips */ 4175 4176 #if defined(BCM_56725_A0) 4177 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56725_A0fmt */ 4178 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4179 /* nFields */ 8, 4180 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDS_BCM56820_A0fmt_fields, 4181 /* bits */ 58, 4182 /* flags */ 0, 4183 }, 4184 #endif /* chips */ 4185 4186 #if defined(BCM_56820_A0) 4187 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM56820_A0fmt */ 4188 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4189 /* nFields */ 8, 4190 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDS_BCM56820_A0fmt_fields, 4191 /* bits */ 58, 4192 /* flags */ 0, 4193 }, 4194 #endif /* chips */ 4195 4196 #if defined(BCM_88732_A0) 4197 { /* SOC_FORMAT_INT_PORT_WRED_CELL_THD_1_FIELDS_BCM88732_A0fmt */ 4198 /* format PORT_WRED_CELL_THD_1_FIELDSfmt */ 4199 /* nFields */ 13, 4200 /* *fields */ soc_PORT_WRED_CELL_THD_1_FIELDS_BCM88732_A0fmt_fields, 4201 /* bits */ 76, 4202 /* flags */ 0, 4203 }, 4204 #endif /* chips */ 4205 4206 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) 4207 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDSfmt */ 4208 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4209 /* nFields */ 12, 4210 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4211 /* bits */ 54, 4212 /* flags */ 0, 4213 }, 4214 #endif /* chips */ 4215 4216 #if defined(BCM_56334_A0) 4217 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56334_A0fmt */ 4218 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4219 /* nFields */ 12, 4220 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4221 /* bits */ 54, 4222 /* flags */ 0, 4223 }, 4224 #endif /* chips */ 4225 4226 #if defined(BCM_56334_B0) 4227 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56334_B0fmt */ 4228 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4229 /* nFields */ 12, 4230 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4231 /* bits */ 54, 4232 /* flags */ 0, 4233 }, 4234 #endif /* chips */ 4235 4236 #if defined(BCM_56524_A0) 4237 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56524_A0fmt */ 4238 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4239 /* nFields */ 12, 4240 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4241 /* bits */ 54, 4242 /* flags */ 0, 4243 }, 4244 #endif /* chips */ 4245 4246 #if defined(BCM_56524_B0) 4247 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56524_B0fmt */ 4248 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4249 /* nFields */ 12, 4250 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4251 /* bits */ 54, 4252 /* flags */ 0, 4253 }, 4254 #endif /* chips */ 4255 4256 #if defined(BCM_56634_A0) 4257 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56634_A0fmt */ 4258 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4259 /* nFields */ 12, 4260 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4261 /* bits */ 54, 4262 /* flags */ 0, 4263 }, 4264 #endif /* chips */ 4265 4266 #if defined(BCM_56634_B0) 4267 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56634_B0fmt */ 4268 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4269 /* nFields */ 12, 4270 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4271 /* bits */ 54, 4272 /* flags */ 0, 4273 }, 4274 #endif /* chips */ 4275 4276 #if defined(BCM_56680_A0) 4277 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56680_A0fmt */ 4278 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4279 /* nFields */ 12, 4280 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4281 /* bits */ 54, 4282 /* flags */ 0, 4283 }, 4284 #endif /* chips */ 4285 4286 #if defined(BCM_56680_B0) 4287 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56680_B0fmt */ 4288 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4289 /* nFields */ 12, 4290 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4291 /* bits */ 54, 4292 /* flags */ 0, 4293 }, 4294 #endif /* chips */ 4295 4296 #if defined(BCM_56685_A0) 4297 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56685_A0fmt */ 4298 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4299 /* nFields */ 12, 4300 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4301 /* bits */ 54, 4302 /* flags */ 0, 4303 }, 4304 #endif /* chips */ 4305 4306 #if defined(BCM_56685_B0) 4307 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56685_B0fmt */ 4308 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4309 /* nFields */ 12, 4310 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4311 /* bits */ 54, 4312 /* flags */ 0, 4313 }, 4314 #endif /* chips */ 4315 4316 #if defined(BCM_56725_A0) 4317 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56725_A0fmt */ 4318 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4319 /* nFields */ 12, 4320 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4321 /* bits */ 54, 4322 /* flags */ 0, 4323 }, 4324 #endif /* chips */ 4325 4326 #if defined(BCM_56820_A0) 4327 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM56820_A0fmt */ 4328 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4329 /* nFields */ 12, 4330 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDSfmt_fields, 4331 /* bits */ 54, 4332 /* flags */ 0, 4333 }, 4334 #endif /* chips */ 4335 4336 #if defined(BCM_88732_A0) 4337 { /* SOC_FORMAT_INT_PORT_WRED_CFG_CELL_FIELDS_BCM88732_A0fmt */ 4338 /* format PORT_WRED_CFG_CELL_FIELDSfmt */ 4339 /* nFields */ 21, 4340 /* *fields */ soc_PORT_WRED_CFG_CELL_FIELDS_BCM88732_A0fmt_fields, 4341 /* bits */ 102, 4342 /* flags */ 0, 4343 }, 4344 #endif /* chips */ 4345 4346 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 4347 defined(BCM_56685_A0) 4348 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDSfmt */ 4349 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4350 /* nFields */ 12, 4351 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4352 /* bits */ 54, 4353 /* flags */ 0, 4354 }, 4355 #endif /* chips */ 4356 4357 #if defined(BCM_56334_A0) 4358 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56334_A0fmt */ 4359 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4360 /* nFields */ 12, 4361 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4362 /* bits */ 54, 4363 /* flags */ 0, 4364 }, 4365 #endif /* chips */ 4366 4367 #if defined(BCM_56334_B0) 4368 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56334_B0fmt */ 4369 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4370 /* nFields */ 12, 4371 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4372 /* bits */ 54, 4373 /* flags */ 0, 4374 }, 4375 #endif /* chips */ 4376 4377 #if defined(BCM_56524_A0) 4378 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56524_A0fmt */ 4379 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4380 /* nFields */ 12, 4381 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4382 /* bits */ 54, 4383 /* flags */ 0, 4384 }, 4385 #endif /* chips */ 4386 4387 #if defined(BCM_56524_B0) 4388 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56524_B0fmt */ 4389 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4390 /* nFields */ 12, 4391 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4392 /* bits */ 54, 4393 /* flags */ 0, 4394 }, 4395 #endif /* chips */ 4396 4397 #if defined(BCM_56634_A0) 4398 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56634_A0fmt */ 4399 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4400 /* nFields */ 12, 4401 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4402 /* bits */ 54, 4403 /* flags */ 0, 4404 }, 4405 #endif /* chips */ 4406 4407 #if defined(BCM_56634_B0) 4408 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56634_B0fmt */ 4409 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4410 /* nFields */ 12, 4411 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4412 /* bits */ 54, 4413 /* flags */ 0, 4414 }, 4415 #endif /* chips */ 4416 4417 #if defined(BCM_56680_A0) 4418 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56680_A0fmt */ 4419 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4420 /* nFields */ 12, 4421 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4422 /* bits */ 54, 4423 /* flags */ 0, 4424 }, 4425 #endif /* chips */ 4426 4427 #if defined(BCM_56680_B0) 4428 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56680_B0fmt */ 4429 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4430 /* nFields */ 12, 4431 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4432 /* bits */ 54, 4433 /* flags */ 0, 4434 }, 4435 #endif /* chips */ 4436 4437 #if defined(BCM_56685_B0) 4438 { /* SOC_FORMAT_INT_PORT_WRED_CFG_PACKET_FIELDS_BCM56685_B0fmt */ 4439 /* format PORT_WRED_CFG_PACKET_FIELDSfmt */ 4440 /* nFields */ 12, 4441 /* *fields */ soc_PORT_WRED_CFG_PACKET_FIELDSfmt_fields, 4442 /* bits */ 54, 4443 /* flags */ 0, 4444 }, 4445 #endif /* chips */ 4446 4447 #if defined(BCM_56524_A0) || defined(BCM_56624_A0) || \ 4448 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 4449 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 4450 defined(BCM_56685_A0) 4451 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_0_FIELDSfmt */ 4452 /* format PORT_WRED_PACKET_THD_0_FIELDSfmt */ 4453 /* nFields */ 8, 4454 /* *fields */ soc_PORT_WRED_PACKET_THD_0_FIELDSfmt_fields, 4455 /* bits */ 58, 4456 /* flags */ 0, 4457 }, 4458 #endif /* chips */ 4459 4460 #if defined(BCM_56334_A0) 4461 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_0_FIELDS_BCM56334_A0fmt */ 4462 /* format PORT_WRED_PACKET_THD_0_FIELDSfmt */ 4463 /* nFields */ 8, 4464 /* *fields */ soc_PORT_WRED_PACKET_THD_0_FIELDS_BCM56334_A0fmt_fields, 4465 /* bits */ 54, 4466 /* flags */ 0, 4467 }, 4468 #endif /* chips */ 4469 4470 #if defined(BCM_56334_B0) 4471 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_0_FIELDS_BCM56334_B0fmt */ 4472 /* format PORT_WRED_PACKET_THD_0_FIELDSfmt */ 4473 /* nFields */ 8, 4474 /* *fields */ soc_PORT_WRED_PACKET_THD_0_FIELDS_BCM56334_A0fmt_fields, 4475 /* bits */ 54, 4476 /* flags */ 0, 4477 }, 4478 #endif /* chips */ 4479 4480 #if defined(BCM_56524_B0) 4481 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_0_FIELDS_BCM56524_B0fmt */ 4482 /* format PORT_WRED_PACKET_THD_0_FIELDSfmt */ 4483 /* nFields */ 8, 4484 /* *fields */ soc_PORT_WRED_PACKET_THD_0_FIELDSfmt_fields, 4485 /* bits */ 58, 4486 /* flags */ 0, 4487 }, 4488 #endif /* chips */ 4489 4490 #if defined(BCM_56680_B0) 4491 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_0_FIELDS_BCM56680_B0fmt */ 4492 /* format PORT_WRED_PACKET_THD_0_FIELDSfmt */ 4493 /* nFields */ 8, 4494 /* *fields */ soc_PORT_WRED_PACKET_THD_0_FIELDSfmt_fields, 4495 /* bits */ 58, 4496 /* flags */ 0, 4497 }, 4498 #endif /* chips */ 4499 4500 #if defined(BCM_56685_B0) 4501 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_0_FIELDS_BCM56685_B0fmt */ 4502 /* format PORT_WRED_PACKET_THD_0_FIELDSfmt */ 4503 /* nFields */ 8, 4504 /* *fields */ soc_PORT_WRED_PACKET_THD_0_FIELDSfmt_fields, 4505 /* bits */ 58, 4506 /* flags */ 0, 4507 }, 4508 #endif /* chips */ 4509 4510 #if defined(BCM_56524_A0) || defined(BCM_56624_A0) || \ 4511 defined(BCM_56634_A0) || defined(BCM_56634_B0) 4512 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4513 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4514 /* nFields */ 8, 4515 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDSfmt_fields, 4516 /* bits */ 58, 4517 /* flags */ 0, 4518 }, 4519 #endif /* chips */ 4520 4521 #if defined(BCM_56334_A0) 4522 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56334_A0fmt */ 4523 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4524 /* nFields */ 8, 4525 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDS_BCM56334_A0fmt_fields, 4526 /* bits */ 54, 4527 /* flags */ 0, 4528 }, 4529 #endif /* chips */ 4530 4531 #if defined(BCM_56334_B0) 4532 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56334_B0fmt */ 4533 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4534 /* nFields */ 8, 4535 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDS_BCM56334_A0fmt_fields, 4536 /* bits */ 54, 4537 /* flags */ 0, 4538 }, 4539 #endif /* chips */ 4540 4541 #if defined(BCM_56524_B0) 4542 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56524_B0fmt */ 4543 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4544 /* nFields */ 8, 4545 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDSfmt_fields, 4546 /* bits */ 58, 4547 /* flags */ 0, 4548 }, 4549 #endif /* chips */ 4550 4551 #if defined(BCM_56624_B0) 4552 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56624_B0fmt */ 4553 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4554 /* nFields */ 8, 4555 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDSfmt_fields, 4556 /* bits */ 58, 4557 /* flags */ 0, 4558 }, 4559 #endif /* chips */ 4560 4561 #if defined(BCM_56680_A0) 4562 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56680_A0fmt */ 4563 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4564 /* nFields */ 8, 4565 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDSfmt_fields, 4566 /* bits */ 58, 4567 /* flags */ 0, 4568 }, 4569 #endif /* chips */ 4570 4571 #if defined(BCM_56680_B0) 4572 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56680_B0fmt */ 4573 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4574 /* nFields */ 8, 4575 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDSfmt_fields, 4576 /* bits */ 58, 4577 /* flags */ 0, 4578 }, 4579 #endif /* chips */ 4580 4581 #if defined(BCM_56685_A0) 4582 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56685_A0fmt */ 4583 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4584 /* nFields */ 8, 4585 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDSfmt_fields, 4586 /* bits */ 58, 4587 /* flags */ 0, 4588 }, 4589 #endif /* chips */ 4590 4591 #if defined(BCM_56685_B0) 4592 { /* SOC_FORMAT_INT_PORT_WRED_PACKET_THD_1_FIELDS_BCM56685_B0fmt */ 4593 /* format PORT_WRED_PACKET_THD_1_FIELDSfmt */ 4594 /* nFields */ 8, 4595 /* *fields */ soc_PORT_WRED_PACKET_THD_1_FIELDSfmt_fields, 4596 /* bits */ 58, 4597 /* flags */ 0, 4598 }, 4599 #endif /* chips */ 4600 4601 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 4602 defined(BCM_56634_B0) 4603 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINERfmt */ 4604 /* format PPD3_DATA_CONTAINERfmt */ 4605 /* nFields */ 8, 4606 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4607 /* bits */ 32, 4608 /* flags */ 0, 4609 }, 4610 #endif /* chips */ 4611 4612 #if defined(BCM_56260_A0) 4613 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56260_A0fmt */ 4614 /* format PPD3_DATA_CONTAINERfmt */ 4615 /* nFields */ 8, 4616 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4617 /* bits */ 32, 4618 /* flags */ 0, 4619 }, 4620 #endif /* chips */ 4621 4622 #if defined(BCM_56260_B0) 4623 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56260_B0fmt */ 4624 /* format PPD3_DATA_CONTAINERfmt */ 4625 /* nFields */ 8, 4626 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4627 /* bits */ 32, 4628 /* flags */ 0, 4629 }, 4630 #endif /* chips */ 4631 4632 #if defined(BCM_56270_A0) 4633 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56270_A0fmt */ 4634 /* format PPD3_DATA_CONTAINERfmt */ 4635 /* nFields */ 8, 4636 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4637 /* bits */ 32, 4638 /* flags */ 0, 4639 }, 4640 #endif /* chips */ 4641 4642 #if defined(BCM_56340_A0) 4643 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56340_A0fmt */ 4644 /* format PPD3_DATA_CONTAINERfmt */ 4645 /* nFields */ 8, 4646 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56640_A0fmt_fields, 4647 /* bits */ 32, 4648 /* flags */ 0, 4649 }, 4650 #endif /* chips */ 4651 4652 #if defined(BCM_56370_A0) 4653 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56370_A0fmt */ 4654 /* format PPD3_DATA_CONTAINERfmt */ 4655 /* nFields */ 8, 4656 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4657 /* bits */ 32, 4658 /* flags */ 0, 4659 }, 4660 #endif /* chips */ 4661 4662 #if defined(BCM_56440_A0) 4663 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56440_A0fmt */ 4664 /* format PPD3_DATA_CONTAINERfmt */ 4665 /* nFields */ 8, 4666 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4667 /* bits */ 32, 4668 /* flags */ 0, 4669 }, 4670 #endif /* chips */ 4671 4672 #if defined(BCM_56440_B0) 4673 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56440_B0fmt */ 4674 /* format PPD3_DATA_CONTAINERfmt */ 4675 /* nFields */ 8, 4676 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4677 /* bits */ 32, 4678 /* flags */ 0, 4679 }, 4680 #endif /* chips */ 4681 4682 #if defined(BCM_56450_A0) 4683 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56450_A0fmt */ 4684 /* format PPD3_DATA_CONTAINERfmt */ 4685 /* nFields */ 8, 4686 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56640_A0fmt_fields, 4687 /* bits */ 32, 4688 /* flags */ 0, 4689 }, 4690 #endif /* chips */ 4691 4692 #if defined(BCM_56450_B0) 4693 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56450_B0fmt */ 4694 /* format PPD3_DATA_CONTAINERfmt */ 4695 /* nFields */ 8, 4696 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56640_A0fmt_fields, 4697 /* bits */ 32, 4698 /* flags */ 0, 4699 }, 4700 #endif /* chips */ 4701 4702 #if defined(BCM_56450_B1) 4703 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56450_B1fmt */ 4704 /* format PPD3_DATA_CONTAINERfmt */ 4705 /* nFields */ 8, 4706 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56640_A0fmt_fields, 4707 /* bits */ 32, 4708 /* flags */ 0, 4709 }, 4710 #endif /* chips */ 4711 4712 #if defined(BCM_56524_B0) 4713 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56524_B0fmt */ 4714 /* format PPD3_DATA_CONTAINERfmt */ 4715 /* nFields */ 8, 4716 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4717 /* bits */ 32, 4718 /* flags */ 0, 4719 }, 4720 #endif /* chips */ 4721 4722 #if defined(BCM_56560_A0) 4723 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56560_A0fmt */ 4724 /* format PPD3_DATA_CONTAINERfmt */ 4725 /* nFields */ 8, 4726 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4727 /* bits */ 32, 4728 /* flags */ 0, 4729 }, 4730 #endif /* chips */ 4731 4732 #if defined(BCM_56560_B0) 4733 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56560_B0fmt */ 4734 /* format PPD3_DATA_CONTAINERfmt */ 4735 /* nFields */ 8, 4736 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4737 /* bits */ 32, 4738 /* flags */ 0, 4739 }, 4740 #endif /* chips */ 4741 4742 #if defined(BCM_56640_A0) 4743 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56640_A0fmt */ 4744 /* format PPD3_DATA_CONTAINERfmt */ 4745 /* nFields */ 8, 4746 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56640_A0fmt_fields, 4747 /* bits */ 32, 4748 /* flags */ 0, 4749 }, 4750 #endif /* chips */ 4751 4752 #if defined(BCM_56670_A0) 4753 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56670_A0fmt */ 4754 /* format PPD3_DATA_CONTAINERfmt */ 4755 /* nFields */ 8, 4756 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4757 /* bits */ 32, 4758 /* flags */ 0, 4759 }, 4760 #endif /* chips */ 4761 4762 #if defined(BCM_56670_B0) 4763 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56670_B0fmt */ 4764 /* format PPD3_DATA_CONTAINERfmt */ 4765 /* nFields */ 8, 4766 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4767 /* bits */ 32, 4768 /* flags */ 0, 4769 }, 4770 #endif /* chips */ 4771 4772 #if defined(BCM_56685_A0) 4773 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56685_A0fmt */ 4774 /* format PPD3_DATA_CONTAINERfmt */ 4775 /* nFields */ 8, 4776 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4777 /* bits */ 32, 4778 /* flags */ 0, 4779 }, 4780 #endif /* chips */ 4781 4782 #if defined(BCM_56685_B0) 4783 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56685_B0fmt */ 4784 /* format PPD3_DATA_CONTAINERfmt */ 4785 /* nFields */ 8, 4786 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4787 /* bits */ 32, 4788 /* flags */ 0, 4789 }, 4790 #endif /* chips */ 4791 4792 #if defined(BCM_56770_A0) 4793 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56770_A0fmt */ 4794 /* format PPD3_DATA_CONTAINERfmt */ 4795 /* nFields */ 8, 4796 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4797 /* bits */ 32, 4798 /* flags */ 0, 4799 }, 4800 #endif /* chips */ 4801 4802 #if defined(BCM_56840_A0) 4803 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56840_A0fmt */ 4804 /* format PPD3_DATA_CONTAINERfmt */ 4805 /* nFields */ 8, 4806 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4807 /* bits */ 32, 4808 /* flags */ 0, 4809 }, 4810 #endif /* chips */ 4811 4812 #if defined(BCM_56840_B0) 4813 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56840_B0fmt */ 4814 /* format PPD3_DATA_CONTAINERfmt */ 4815 /* nFields */ 8, 4816 /* *fields */ soc_PPD3_DATA_CONTAINERfmt_fields, 4817 /* bits */ 32, 4818 /* flags */ 0, 4819 }, 4820 #endif /* chips */ 4821 4822 #if defined(BCM_56850_A0) 4823 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56850_A0fmt */ 4824 /* format PPD3_DATA_CONTAINERfmt */ 4825 /* nFields */ 8, 4826 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56640_A0fmt_fields, 4827 /* bits */ 32, 4828 /* flags */ 0, 4829 }, 4830 #endif /* chips */ 4831 4832 #if defined(BCM_56860_A0) 4833 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56860_A0fmt */ 4834 /* format PPD3_DATA_CONTAINERfmt */ 4835 /* nFields */ 8, 4836 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56640_A0fmt_fields, 4837 /* bits */ 32, 4838 /* flags */ 0, 4839 }, 4840 #endif /* chips */ 4841 4842 #if defined(BCM_56870_A0) 4843 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56870_A0fmt */ 4844 /* format PPD3_DATA_CONTAINERfmt */ 4845 /* nFields */ 8, 4846 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4847 /* bits */ 32, 4848 /* flags */ 0, 4849 }, 4850 #endif /* chips */ 4851 4852 #if defined(BCM_56960_A0) 4853 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56960_A0fmt */ 4854 /* format PPD3_DATA_CONTAINERfmt */ 4855 /* nFields */ 8, 4856 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4857 /* bits */ 32, 4858 /* flags */ 0, 4859 }, 4860 #endif /* chips */ 4861 4862 #if defined(BCM_56965_A0) 4863 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56965_A0fmt */ 4864 /* format PPD3_DATA_CONTAINERfmt */ 4865 /* nFields */ 8, 4866 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4867 /* bits */ 32, 4868 /* flags */ 0, 4869 }, 4870 #endif /* chips */ 4871 4872 #if defined(BCM_56970_A0) 4873 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56970_A0fmt */ 4874 /* format PPD3_DATA_CONTAINERfmt */ 4875 /* nFields */ 8, 4876 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4877 /* bits */ 32, 4878 /* flags */ 0, 4879 }, 4880 #endif /* chips */ 4881 4882 #if defined(BCM_56980_A0) 4883 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56980_A0fmt */ 4884 /* format PPD3_DATA_CONTAINERfmt */ 4885 /* nFields */ 8, 4886 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4887 /* bits */ 32, 4888 /* flags */ 0, 4889 }, 4890 #endif /* chips */ 4891 4892 #if defined(BCM_56980_B0) 4893 { /* SOC_FORMAT_INT_PPD3_DATA_CONTAINER_BCM56980_B0fmt */ 4894 /* format PPD3_DATA_CONTAINERfmt */ 4895 /* nFields */ 8, 4896 /* *fields */ soc_PPD3_DATA_CONTAINER_BCM56960_A0fmt_fields, 4897 /* bits */ 32, 4898 /* flags */ 0, 4899 }, 4900 #endif /* chips */ 4901 4902 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 4903 { /* SOC_FORMAT_INT_PQE_REG_DATAfmt */ 4904 /* format PQE_REG_DATAfmt */ 4905 /* nFields */ 1, 4906 /* *fields */ soc_PQE_REG_DATAfmt_fields, 4907 /* bits */ 64, 4908 /* flags */ 0, 4909 }, 4910 #endif /* chips */ 4911 4912 #if defined(BCM_56340_A0) 4913 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56340_A0fmt */ 4914 /* format PQE_REG_DATAfmt */ 4915 /* nFields */ 1, 4916 /* *fields */ soc_PQE_REG_DATA_BCM56640_A0fmt_fields, 4917 /* bits */ 64, 4918 /* flags */ 0, 4919 }, 4920 #endif /* chips */ 4921 4922 #if defined(BCM_56370_A0) 4923 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56370_A0fmt */ 4924 /* format PQE_REG_DATAfmt */ 4925 /* nFields */ 1, 4926 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 4927 /* bits */ 64, 4928 /* flags */ 0, 4929 }, 4930 #endif /* chips */ 4931 4932 #if defined(BCM_56524_A0) 4933 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56524_A0fmt */ 4934 /* format PQE_REG_DATAfmt */ 4935 /* nFields */ 1, 4936 /* *fields */ soc_PQE_REG_DATAfmt_fields, 4937 /* bits */ 64, 4938 /* flags */ 0, 4939 }, 4940 #endif /* chips */ 4941 4942 #if defined(BCM_56524_B0) 4943 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56524_B0fmt */ 4944 /* format PQE_REG_DATAfmt */ 4945 /* nFields */ 1, 4946 /* *fields */ soc_PQE_REG_DATAfmt_fields, 4947 /* bits */ 64, 4948 /* flags */ 0, 4949 }, 4950 #endif /* chips */ 4951 4952 #if defined(BCM_56560_A0) 4953 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56560_A0fmt */ 4954 /* format PQE_REG_DATAfmt */ 4955 /* nFields */ 1, 4956 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 4957 /* bits */ 64, 4958 /* flags */ 0, 4959 }, 4960 #endif /* chips */ 4961 4962 #if defined(BCM_56560_B0) 4963 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56560_B0fmt */ 4964 /* format PQE_REG_DATAfmt */ 4965 /* nFields */ 1, 4966 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 4967 /* bits */ 64, 4968 /* flags */ 0, 4969 }, 4970 #endif /* chips */ 4971 4972 #if defined(BCM_56640_A0) 4973 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56640_A0fmt */ 4974 /* format PQE_REG_DATAfmt */ 4975 /* nFields */ 1, 4976 /* *fields */ soc_PQE_REG_DATA_BCM56640_A0fmt_fields, 4977 /* bits */ 64, 4978 /* flags */ 0, 4979 }, 4980 #endif /* chips */ 4981 4982 #if defined(BCM_56670_A0) 4983 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56670_A0fmt */ 4984 /* format PQE_REG_DATAfmt */ 4985 /* nFields */ 1, 4986 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 4987 /* bits */ 64, 4988 /* flags */ 0, 4989 }, 4990 #endif /* chips */ 4991 4992 #if defined(BCM_56670_B0) 4993 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56670_B0fmt */ 4994 /* format PQE_REG_DATAfmt */ 4995 /* nFields */ 1, 4996 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 4997 /* bits */ 64, 4998 /* flags */ 0, 4999 }, 5000 #endif /* chips */ 5001 5002 #if defined(BCM_56685_A0) 5003 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56685_A0fmt */ 5004 /* format PQE_REG_DATAfmt */ 5005 /* nFields */ 1, 5006 /* *fields */ soc_PQE_REG_DATAfmt_fields, 5007 /* bits */ 64, 5008 /* flags */ 0, 5009 }, 5010 #endif /* chips */ 5011 5012 #if defined(BCM_56685_B0) 5013 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56685_B0fmt */ 5014 /* format PQE_REG_DATAfmt */ 5015 /* nFields */ 1, 5016 /* *fields */ soc_PQE_REG_DATAfmt_fields, 5017 /* bits */ 64, 5018 /* flags */ 0, 5019 }, 5020 #endif /* chips */ 5021 5022 #if defined(BCM_56770_A0) 5023 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56770_A0fmt */ 5024 /* format PQE_REG_DATAfmt */ 5025 /* nFields */ 1, 5026 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 5027 /* bits */ 64, 5028 /* flags */ 0, 5029 }, 5030 #endif /* chips */ 5031 5032 #if defined(BCM_56840_A0) 5033 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56840_A0fmt */ 5034 /* format PQE_REG_DATAfmt */ 5035 /* nFields */ 1, 5036 /* *fields */ soc_PQE_REG_DATAfmt_fields, 5037 /* bits */ 64, 5038 /* flags */ 0, 5039 }, 5040 #endif /* chips */ 5041 5042 #if defined(BCM_56840_B0) 5043 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56840_B0fmt */ 5044 /* format PQE_REG_DATAfmt */ 5045 /* nFields */ 1, 5046 /* *fields */ soc_PQE_REG_DATAfmt_fields, 5047 /* bits */ 64, 5048 /* flags */ 0, 5049 }, 5050 #endif /* chips */ 5051 5052 #if defined(BCM_56850_A0) 5053 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56850_A0fmt */ 5054 /* format PQE_REG_DATAfmt */ 5055 /* nFields */ 1, 5056 /* *fields */ soc_PQE_REG_DATA_BCM56640_A0fmt_fields, 5057 /* bits */ 64, 5058 /* flags */ 0, 5059 }, 5060 #endif /* chips */ 5061 5062 #if defined(BCM_56860_A0) 5063 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56860_A0fmt */ 5064 /* format PQE_REG_DATAfmt */ 5065 /* nFields */ 1, 5066 /* *fields */ soc_PQE_REG_DATA_BCM56640_A0fmt_fields, 5067 /* bits */ 64, 5068 /* flags */ 0, 5069 }, 5070 #endif /* chips */ 5071 5072 #if defined(BCM_56870_A0) 5073 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56870_A0fmt */ 5074 /* format PQE_REG_DATAfmt */ 5075 /* nFields */ 1, 5076 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 5077 /* bits */ 64, 5078 /* flags */ 0, 5079 }, 5080 #endif /* chips */ 5081 5082 #if defined(BCM_56960_A0) 5083 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56960_A0fmt */ 5084 /* format PQE_REG_DATAfmt */ 5085 /* nFields */ 1, 5086 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 5087 /* bits */ 64, 5088 /* flags */ 0, 5089 }, 5090 #endif /* chips */ 5091 5092 #if defined(BCM_56965_A0) 5093 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56965_A0fmt */ 5094 /* format PQE_REG_DATAfmt */ 5095 /* nFields */ 1, 5096 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 5097 /* bits */ 64, 5098 /* flags */ 0, 5099 }, 5100 #endif /* chips */ 5101 5102 #if defined(BCM_56970_A0) 5103 { /* SOC_FORMAT_INT_PQE_REG_DATA_BCM56970_A0fmt */ 5104 /* format PQE_REG_DATAfmt */ 5105 /* nFields */ 1, 5106 /* *fields */ soc_PQE_REG_DATA_BCM56960_A0fmt_fields, 5107 /* bits */ 64, 5108 /* flags */ 0, 5109 }, 5110 #endif /* chips */ 5111 5112 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 5113 { /* SOC_FORMAT_INT_PQE_S_RFfmt */ 5114 /* format PQE_S_RFfmt */ 5115 /* nFields */ 1, 5116 /* *fields */ soc_PQE_S_RFfmt_fields, 5117 /* bits */ 112, 5118 /* flags */ 0, 5119 }, 5120 #endif /* chips */ 5121 5122 #if defined(BCM_56340_A0) 5123 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56340_A0fmt */ 5124 /* format PQE_S_RFfmt */ 5125 /* nFields */ 1, 5126 /* *fields */ soc_PQE_S_RF_BCM56640_A0fmt_fields, 5127 /* bits */ 36, 5128 /* flags */ 0, 5129 }, 5130 #endif /* chips */ 5131 5132 #if defined(BCM_56370_A0) 5133 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56370_A0fmt */ 5134 /* format PQE_S_RFfmt */ 5135 /* nFields */ 1, 5136 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5137 /* bits */ 36, 5138 /* flags */ 0, 5139 }, 5140 #endif /* chips */ 5141 5142 #if defined(BCM_56524_A0) 5143 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56524_A0fmt */ 5144 /* format PQE_S_RFfmt */ 5145 /* nFields */ 1, 5146 /* *fields */ soc_PQE_S_RFfmt_fields, 5147 /* bits */ 112, 5148 /* flags */ 0, 5149 }, 5150 #endif /* chips */ 5151 5152 #if defined(BCM_56524_B0) 5153 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56524_B0fmt */ 5154 /* format PQE_S_RFfmt */ 5155 /* nFields */ 1, 5156 /* *fields */ soc_PQE_S_RFfmt_fields, 5157 /* bits */ 112, 5158 /* flags */ 0, 5159 }, 5160 #endif /* chips */ 5161 5162 #if defined(BCM_56560_A0) 5163 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56560_A0fmt */ 5164 /* format PQE_S_RFfmt */ 5165 /* nFields */ 1, 5166 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5167 /* bits */ 36, 5168 /* flags */ 0, 5169 }, 5170 #endif /* chips */ 5171 5172 #if defined(BCM_56560_B0) 5173 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56560_B0fmt */ 5174 /* format PQE_S_RFfmt */ 5175 /* nFields */ 1, 5176 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5177 /* bits */ 36, 5178 /* flags */ 0, 5179 }, 5180 #endif /* chips */ 5181 5182 #if defined(BCM_56640_A0) 5183 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56640_A0fmt */ 5184 /* format PQE_S_RFfmt */ 5185 /* nFields */ 1, 5186 /* *fields */ soc_PQE_S_RF_BCM56640_A0fmt_fields, 5187 /* bits */ 36, 5188 /* flags */ 0, 5189 }, 5190 #endif /* chips */ 5191 5192 #if defined(BCM_56670_A0) 5193 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56670_A0fmt */ 5194 /* format PQE_S_RFfmt */ 5195 /* nFields */ 1, 5196 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5197 /* bits */ 36, 5198 /* flags */ 0, 5199 }, 5200 #endif /* chips */ 5201 5202 #if defined(BCM_56670_B0) 5203 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56670_B0fmt */ 5204 /* format PQE_S_RFfmt */ 5205 /* nFields */ 1, 5206 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5207 /* bits */ 36, 5208 /* flags */ 0, 5209 }, 5210 #endif /* chips */ 5211 5212 #if defined(BCM_56685_A0) 5213 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56685_A0fmt */ 5214 /* format PQE_S_RFfmt */ 5215 /* nFields */ 1, 5216 /* *fields */ soc_PQE_S_RFfmt_fields, 5217 /* bits */ 112, 5218 /* flags */ 0, 5219 }, 5220 #endif /* chips */ 5221 5222 #if defined(BCM_56685_B0) 5223 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56685_B0fmt */ 5224 /* format PQE_S_RFfmt */ 5225 /* nFields */ 1, 5226 /* *fields */ soc_PQE_S_RFfmt_fields, 5227 /* bits */ 112, 5228 /* flags */ 0, 5229 }, 5230 #endif /* chips */ 5231 5232 #if defined(BCM_56770_A0) 5233 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56770_A0fmt */ 5234 /* format PQE_S_RFfmt */ 5235 /* nFields */ 1, 5236 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5237 /* bits */ 36, 5238 /* flags */ 0, 5239 }, 5240 #endif /* chips */ 5241 5242 #if defined(BCM_56840_A0) 5243 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56840_A0fmt */ 5244 /* format PQE_S_RFfmt */ 5245 /* nFields */ 1, 5246 /* *fields */ soc_PQE_S_RF_BCM56840_A0fmt_fields, 5247 /* bits */ 36, 5248 /* flags */ 0, 5249 }, 5250 #endif /* chips */ 5251 5252 #if defined(BCM_56840_B0) 5253 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56840_B0fmt */ 5254 /* format PQE_S_RFfmt */ 5255 /* nFields */ 1, 5256 /* *fields */ soc_PQE_S_RF_BCM56840_A0fmt_fields, 5257 /* bits */ 36, 5258 /* flags */ 0, 5259 }, 5260 #endif /* chips */ 5261 5262 #if defined(BCM_56850_A0) 5263 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56850_A0fmt */ 5264 /* format PQE_S_RFfmt */ 5265 /* nFields */ 1, 5266 /* *fields */ soc_PQE_S_RF_BCM56640_A0fmt_fields, 5267 /* bits */ 36, 5268 /* flags */ 0, 5269 }, 5270 #endif /* chips */ 5271 5272 #if defined(BCM_56860_A0) 5273 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56860_A0fmt */ 5274 /* format PQE_S_RFfmt */ 5275 /* nFields */ 1, 5276 /* *fields */ soc_PQE_S_RF_BCM56640_A0fmt_fields, 5277 /* bits */ 36, 5278 /* flags */ 0, 5279 }, 5280 #endif /* chips */ 5281 5282 #if defined(BCM_56870_A0) 5283 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56870_A0fmt */ 5284 /* format PQE_S_RFfmt */ 5285 /* nFields */ 1, 5286 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5287 /* bits */ 36, 5288 /* flags */ 0, 5289 }, 5290 #endif /* chips */ 5291 5292 #if defined(BCM_56960_A0) 5293 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56960_A0fmt */ 5294 /* format PQE_S_RFfmt */ 5295 /* nFields */ 1, 5296 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5297 /* bits */ 36, 5298 /* flags */ 0, 5299 }, 5300 #endif /* chips */ 5301 5302 #if defined(BCM_56965_A0) 5303 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56965_A0fmt */ 5304 /* format PQE_S_RFfmt */ 5305 /* nFields */ 1, 5306 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5307 /* bits */ 36, 5308 /* flags */ 0, 5309 }, 5310 #endif /* chips */ 5311 5312 #if defined(BCM_56970_A0) 5313 { /* SOC_FORMAT_INT_PQE_S_RF_BCM56970_A0fmt */ 5314 /* format PQE_S_RFfmt */ 5315 /* nFields */ 1, 5316 /* *fields */ soc_PQE_S_RF_BCM56960_A0fmt_fields, 5317 /* bits */ 36, 5318 /* flags */ 0, 5319 }, 5320 #endif /* chips */ 5321 5322 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 5323 { /* SOC_FORMAT_INT_PQE_TO_E2EFC_INFO_BUSfmt */ 5324 /* format PQE_TO_E2EFC_INFO_BUSfmt */ 5325 /* nFields */ 5, 5326 /* *fields */ soc_PQE_TO_E2EFC_INFO_BUSfmt_fields, 5327 /* bits */ 16, 5328 /* flags */ 0, 5329 }, 5330 #endif /* chips */ 5331 5332 #if defined(BCM_56524_A0) 5333 { /* SOC_FORMAT_INT_PQE_TO_E2EFC_INFO_BUS_BCM56524_A0fmt */ 5334 /* format PQE_TO_E2EFC_INFO_BUSfmt */ 5335 /* nFields */ 5, 5336 /* *fields */ soc_PQE_TO_E2EFC_INFO_BUSfmt_fields, 5337 /* bits */ 16, 5338 /* flags */ 0, 5339 }, 5340 #endif /* chips */ 5341 5342 #if defined(BCM_56524_B0) 5343 { /* SOC_FORMAT_INT_PQE_TO_E2EFC_INFO_BUS_BCM56524_B0fmt */ 5344 /* format PQE_TO_E2EFC_INFO_BUSfmt */ 5345 /* nFields */ 5, 5346 /* *fields */ soc_PQE_TO_E2EFC_INFO_BUSfmt_fields, 5347 /* bits */ 16, 5348 /* flags */ 0, 5349 }, 5350 #endif /* chips */ 5351 5352 #if defined(BCM_56685_A0) 5353 { /* SOC_FORMAT_INT_PQE_TO_E2EFC_INFO_BUS_BCM56685_A0fmt */ 5354 /* format PQE_TO_E2EFC_INFO_BUSfmt */ 5355 /* nFields */ 5, 5356 /* *fields */ soc_PQE_TO_E2EFC_INFO_BUSfmt_fields, 5357 /* bits */ 16, 5358 /* flags */ 0, 5359 }, 5360 #endif /* chips */ 5361 5362 #if defined(BCM_56685_B0) 5363 { /* SOC_FORMAT_INT_PQE_TO_E2EFC_INFO_BUS_BCM56685_B0fmt */ 5364 /* format PQE_TO_E2EFC_INFO_BUSfmt */ 5365 /* nFields */ 5, 5366 /* *fields */ soc_PQE_TO_E2EFC_INFO_BUSfmt_fields, 5367 /* bits */ 16, 5368 /* flags */ 0, 5369 }, 5370 #endif /* chips */ 5371 5372 #if defined(BCM_56634_A0) 5373 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFOfmt */ 5374 /* format PQE_TO_THDI_INFOfmt */ 5375 /* nFields */ 6, 5376 /* *fields */ soc_PQE_TO_THDI_INFOfmt_fields, 5377 /* bits */ 15, 5378 /* flags */ 0, 5379 }, 5380 #endif /* chips */ 5381 5382 #if defined(BCM_56524_A0) 5383 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFO_BCM56524_A0fmt */ 5384 /* format PQE_TO_THDI_INFOfmt */ 5385 /* nFields */ 6, 5386 /* *fields */ soc_PQE_TO_THDI_INFOfmt_fields, 5387 /* bits */ 15, 5388 /* flags */ 0, 5389 }, 5390 #endif /* chips */ 5391 5392 #if defined(BCM_56524_B0) 5393 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFO_BCM56524_B0fmt */ 5394 /* format PQE_TO_THDI_INFOfmt */ 5395 /* nFields */ 6, 5396 /* *fields */ soc_PQE_TO_THDI_INFOfmt_fields, 5397 /* bits */ 15, 5398 /* flags */ 0, 5399 }, 5400 #endif /* chips */ 5401 5402 #if defined(BCM_56634_B0) 5403 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFO_BCM56634_B0fmt */ 5404 /* format PQE_TO_THDI_INFOfmt */ 5405 /* nFields */ 6, 5406 /* *fields */ soc_PQE_TO_THDI_INFOfmt_fields, 5407 /* bits */ 15, 5408 /* flags */ 0, 5409 }, 5410 #endif /* chips */ 5411 5412 #if defined(BCM_56685_A0) 5413 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFO_BCM56685_A0fmt */ 5414 /* format PQE_TO_THDI_INFOfmt */ 5415 /* nFields */ 6, 5416 /* *fields */ soc_PQE_TO_THDI_INFOfmt_fields, 5417 /* bits */ 15, 5418 /* flags */ 0, 5419 }, 5420 #endif /* chips */ 5421 5422 #if defined(BCM_56685_B0) 5423 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFO_BCM56685_B0fmt */ 5424 /* format PQE_TO_THDI_INFOfmt */ 5425 /* nFields */ 6, 5426 /* *fields */ soc_PQE_TO_THDI_INFOfmt_fields, 5427 /* bits */ 15, 5428 /* flags */ 0, 5429 }, 5430 #endif /* chips */ 5431 5432 #if defined(BCM_56840_A0) 5433 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFO_BCM56840_A0fmt */ 5434 /* format PQE_TO_THDI_INFOfmt */ 5435 /* nFields */ 4, 5436 /* *fields */ soc_PQE_TO_THDI_INFO_BCM56840_A0fmt_fields, 5437 /* bits */ 15, 5438 /* flags */ 0, 5439 }, 5440 #endif /* chips */ 5441 5442 #if defined(BCM_56840_B0) 5443 { /* SOC_FORMAT_INT_PQE_TO_THDI_INFO_BCM56840_B0fmt */ 5444 /* format PQE_TO_THDI_INFOfmt */ 5445 /* nFields */ 4, 5446 /* *fields */ soc_PQE_TO_THDI_INFO_BCM56840_A0fmt_fields, 5447 /* bits */ 15, 5448 /* flags */ 0, 5449 }, 5450 #endif /* chips */ 5451 5452 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 5453 defined(BCM_56634_B0) 5454 { /* SOC_FORMAT_INT_PQE_TO_THDO4_INFOfmt */ 5455 /* format PQE_TO_THDO4_INFOfmt */ 5456 /* nFields */ 6, 5457 /* *fields */ soc_PQE_TO_THDO4_INFOfmt_fields, 5458 /* bits */ 75, 5459 /* flags */ 0, 5460 }, 5461 #endif /* chips */ 5462 5463 #if defined(BCM_56524_B0) 5464 { /* SOC_FORMAT_INT_PQE_TO_THDO4_INFO_BCM56524_B0fmt */ 5465 /* format PQE_TO_THDO4_INFOfmt */ 5466 /* nFields */ 6, 5467 /* *fields */ soc_PQE_TO_THDO4_INFOfmt_fields, 5468 /* bits */ 75, 5469 /* flags */ 0, 5470 }, 5471 #endif /* chips */ 5472 5473 #if defined(BCM_56685_A0) 5474 { /* SOC_FORMAT_INT_PQE_TO_THDO4_INFO_BCM56685_A0fmt */ 5475 /* format PQE_TO_THDO4_INFOfmt */ 5476 /* nFields */ 6, 5477 /* *fields */ soc_PQE_TO_THDO4_INFOfmt_fields, 5478 /* bits */ 75, 5479 /* flags */ 0, 5480 }, 5481 #endif /* chips */ 5482 5483 #if defined(BCM_56685_B0) 5484 { /* SOC_FORMAT_INT_PQE_TO_THDO4_INFO_BCM56685_B0fmt */ 5485 /* format PQE_TO_THDO4_INFOfmt */ 5486 /* nFields */ 6, 5487 /* *fields */ soc_PQE_TO_THDO4_INFOfmt_fields, 5488 /* bits */ 75, 5489 /* flags */ 0, 5490 }, 5491 #endif /* chips */ 5492 5493 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 5494 defined(BCM_56634_B0) 5495 { /* SOC_FORMAT_INT_PQE_TO_THDO_INFOfmt */ 5496 /* format PQE_TO_THDO_INFOfmt */ 5497 /* nFields */ 9, 5498 /* *fields */ soc_PQE_TO_THDO_INFOfmt_fields, 5499 /* bits */ 90, 5500 /* flags */ 0, 5501 }, 5502 #endif /* chips */ 5503 5504 #if defined(BCM_56524_B0) 5505 { /* SOC_FORMAT_INT_PQE_TO_THDO_INFO_BCM56524_B0fmt */ 5506 /* format PQE_TO_THDO_INFOfmt */ 5507 /* nFields */ 9, 5508 /* *fields */ soc_PQE_TO_THDO_INFOfmt_fields, 5509 /* bits */ 90, 5510 /* flags */ 0, 5511 }, 5512 #endif /* chips */ 5513 5514 #if defined(BCM_56685_A0) 5515 { /* SOC_FORMAT_INT_PQE_TO_THDO_INFO_BCM56685_A0fmt */ 5516 /* format PQE_TO_THDO_INFOfmt */ 5517 /* nFields */ 9, 5518 /* *fields */ soc_PQE_TO_THDO_INFOfmt_fields, 5519 /* bits */ 90, 5520 /* flags */ 0, 5521 }, 5522 #endif /* chips */ 5523 5524 #if defined(BCM_56685_B0) 5525 { /* SOC_FORMAT_INT_PQE_TO_THDO_INFO_BCM56685_B0fmt */ 5526 /* format PQE_TO_THDO_INFOfmt */ 5527 /* nFields */ 9, 5528 /* *fields */ soc_PQE_TO_THDO_INFOfmt_fields, 5529 /* bits */ 90, 5530 /* flags */ 0, 5531 }, 5532 #endif /* chips */ 5533 5534 #if defined(BCM_56840_A0) 5535 { /* SOC_FORMAT_INT_PQE_TO_THDO_INFO_BCM56840_A0fmt */ 5536 /* format PQE_TO_THDO_INFOfmt */ 5537 /* nFields */ 15, 5538 /* *fields */ soc_PQE_TO_THDO_INFO_BCM56840_A0fmt_fields, 5539 /* bits */ 143, 5540 /* flags */ 0, 5541 }, 5542 #endif /* chips */ 5543 5544 #if defined(BCM_56840_B0) 5545 { /* SOC_FORMAT_INT_PQE_TO_THDO_INFO_BCM56840_B0fmt */ 5546 /* format PQE_TO_THDO_INFOfmt */ 5547 /* nFields */ 15, 5548 /* *fields */ soc_PQE_TO_THDO_INFO_BCM56840_A0fmt_fields, 5549 /* bits */ 143, 5550 /* flags */ 0, 5551 }, 5552 #endif /* chips */ 5553 5554 #if defined(BCM_56870_A0) 5555 { /* SOC_FORMAT_INT_PRE_COUNTER_UPDATE_VECTORfmt */ 5556 /* format PRE_COUNTER_UPDATE_VECTORfmt */ 5557 /* nFields */ 30, 5558 /* *fields */ soc_PRE_COUNTER_UPDATE_VECTORfmt_fields, 5559 /* bits */ 32, 5560 /* flags */ 0, 5561 }, 5562 #endif /* chips */ 5563 5564 #if defined(BCM_56370_A0) 5565 { /* SOC_FORMAT_INT_PRE_COUNTER_UPDATE_VECTOR_BCM56370_A0fmt */ 5566 /* format PRE_COUNTER_UPDATE_VECTORfmt */ 5567 /* nFields */ 35, 5568 /* *fields */ soc_PRE_COUNTER_UPDATE_VECTOR_BCM56370_A0fmt_fields, 5569 /* bits */ 35, 5570 /* flags */ 0, 5571 }, 5572 #endif /* chips */ 5573 5574 #if defined(BCM_56770_A0) 5575 { /* SOC_FORMAT_INT_PRE_COUNTER_UPDATE_VECTOR_BCM56770_A0fmt */ 5576 /* format PRE_COUNTER_UPDATE_VECTORfmt */ 5577 /* nFields */ 31, 5578 /* *fields */ soc_PRE_COUNTER_UPDATE_VECTOR_BCM56770_A0fmt_fields, 5579 /* bits */ 32, 5580 /* flags */ 0, 5581 }, 5582 #endif /* chips */ 5583 5584 #if defined(BCM_56980_A0) 5585 { /* SOC_FORMAT_INT_PRE_COUNTER_UPDATE_VECTOR_BCM56980_A0fmt */ 5586 /* format PRE_COUNTER_UPDATE_VECTORfmt */ 5587 /* nFields */ 29, 5588 /* *fields */ soc_PRE_COUNTER_UPDATE_VECTOR_BCM56980_A0fmt_fields, 5589 /* bits */ 32, 5590 /* flags */ 0, 5591 }, 5592 #endif /* chips */ 5593 5594 #if defined(BCM_56980_B0) 5595 { /* SOC_FORMAT_INT_PRE_COUNTER_UPDATE_VECTOR_BCM56980_B0fmt */ 5596 /* format PRE_COUNTER_UPDATE_VECTORfmt */ 5597 /* nFields */ 29, 5598 /* *fields */ soc_PRE_COUNTER_UPDATE_VECTOR_BCM56980_A0fmt_fields, 5599 /* bits */ 32, 5600 /* flags */ 0, 5601 }, 5602 #endif /* chips */ 5603 5604 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5605 defined(BCM_56870_A0) 5606 { /* SOC_FORMAT_INT_PROTECTION_ACTION_SETfmt */ 5607 /* format PROTECTION_ACTION_SETfmt */ 5608 /* nFields */ 4, 5609 /* *fields */ soc_PROTECTION_ACTION_SETfmt_fields, 5610 /* bits */ 15, 5611 /* flags */ 0, 5612 }, 5613 #endif /* chips */ 5614 5615 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5616 defined(BCM_56870_A0) 5617 { /* SOC_FORMAT_INT_PROTECTION_GROUP_ACTION_SETfmt */ 5618 /* format PROTECTION_GROUP_ACTION_SETfmt */ 5619 /* nFields */ 1, 5620 /* *fields */ soc_PROTECTION_GROUP_ACTION_SETfmt_fields, 5621 /* bits */ 11, 5622 /* flags */ 0, 5623 }, 5624 #endif /* chips */ 5625 5626 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5627 defined(BCM_56870_A0) 5628 { /* SOC_FORMAT_INT_PROTECTION_NHI_ACTION_SETfmt */ 5629 /* format PROTECTION_NHI_ACTION_SETfmt */ 5630 /* nFields */ 1, 5631 /* *fields */ soc_PROTECTION_NHI_ACTION_SETfmt_fields, 5632 /* bits */ 1, 5633 /* flags */ 0, 5634 }, 5635 #endif /* chips */ 5636 5637 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5638 { /* SOC_FORMAT_INT_PTP_1588_SIGNALS_TO_PMfmt */ 5639 /* format PTP_1588_SIGNALS_TO_PMfmt */ 5640 /* nFields */ 6, 5641 /* *fields */ soc_PTP_1588_SIGNALS_TO_PMfmt_fields, 5642 /* bits */ 13, 5643 /* flags */ 0, 5644 }, 5645 #endif /* chips */ 5646 5647 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5648 defined(BCM_56870_A0) 5649 { /* SOC_FORMAT_INT_PTP_HDRfmt */ 5650 /* format PTP_HDRfmt */ 5651 /* nFields */ 11, 5652 /* *fields */ soc_PTP_HDRfmt_fields, 5653 /* bits */ 128, 5654 /* flags */ 0, 5655 }, 5656 #endif /* chips */ 5657 5658 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5659 defined(BCM_56870_A0) 5660 { /* SOC_FORMAT_INT_PWCW_HDRfmt */ 5661 /* format PWCW_HDRfmt */ 5662 /* nFields */ 4, 5663 /* *fields */ soc_PWCW_HDRfmt_fields, 5664 /* bits */ 32, 5665 /* flags */ 0, 5666 }, 5667 #endif /* chips */ 5668