allformats_n.i (16526B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_n.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 16 defined(BCM_56870_A0) 17 { /* SOC_FORMAT_INT_NAT_ACTION_SETfmt */ 18 /* format NAT_ACTION_SETfmt */ 19 /* nFields */ 2, 20 /* *fields */ soc_NAT_ACTION_SETfmt_fields, 21 /* bits */ 11, 22 /* flags */ 0, 23 }, 24 #endif /* chips */ 25 26 #if defined(BCM_56850_A0) 27 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODINGfmt */ 28 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 29 /* nFields */ 1, 30 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 31 /* bits */ 3, 32 /* flags */ 0, 33 }, 34 #endif /* chips */ 35 36 #if defined(BCM_56560_A0) 37 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56560_A0fmt */ 38 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 39 /* nFields */ 1, 40 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 41 /* bits */ 3, 42 /* flags */ 0, 43 }, 44 #endif /* chips */ 45 46 #if defined(BCM_56560_B0) 47 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56560_B0fmt */ 48 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 49 /* nFields */ 1, 50 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 51 /* bits */ 3, 52 /* flags */ 0, 53 }, 54 #endif /* chips */ 55 56 #if defined(BCM_56670_A0) 57 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56670_A0fmt */ 58 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 59 /* nFields */ 1, 60 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 61 /* bits */ 3, 62 /* flags */ 0, 63 }, 64 #endif /* chips */ 65 66 #if defined(BCM_56670_B0) 67 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56670_B0fmt */ 68 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 69 /* nFields */ 1, 70 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 71 /* bits */ 3, 72 /* flags */ 0, 73 }, 74 #endif /* chips */ 75 76 #if defined(BCM_56860_A0) 77 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56860_A0fmt */ 78 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 79 /* nFields */ 1, 80 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 81 /* bits */ 3, 82 /* flags */ 0, 83 }, 84 #endif /* chips */ 85 86 #if defined(BCM_56960_A0) 87 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56960_A0fmt */ 88 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 89 /* nFields */ 1, 90 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 91 /* bits */ 3, 92 /* flags */ 0, 93 }, 94 #endif /* chips */ 95 96 #if defined(BCM_56965_A0) 97 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56965_A0fmt */ 98 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 99 /* nFields */ 1, 100 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 101 /* bits */ 3, 102 /* flags */ 0, 103 }, 104 #endif /* chips */ 105 106 #if defined(BCM_56970_A0) 107 { /* SOC_FORMAT_INT_NAT_CPU_OPCODE_ENCODING_BCM56970_A0fmt */ 108 /* format NAT_CPU_OPCODE_ENCODINGfmt */ 109 /* nFields */ 1, 110 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 111 /* bits */ 3, 112 /* flags */ 0, 113 }, 114 #endif /* chips */ 115 116 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 117 { /* SOC_FORMAT_INT_NETWORK_HVE_OUTPUT_BUSfmt */ 118 /* format NETWORK_HVE_OUTPUT_BUSfmt */ 119 /* nFields */ 114, 120 /* *fields */ soc_NETWORK_HVE_OUTPUT_BUSfmt_fields, 121 /* bits */ 168, 122 /* flags */ 0, 123 }, 124 #endif /* chips */ 125 126 #if defined(BCM_56370_A0) 127 { /* SOC_FORMAT_INT_NETWORK_HVE_OUTPUT_BUS_BCM56370_A0fmt */ 128 /* format NETWORK_HVE_OUTPUT_BUSfmt */ 129 /* nFields */ 128, 130 /* *fields */ soc_NETWORK_HVE_OUTPUT_BUS_BCM56370_A0fmt_fields, 131 /* bits */ 182, 132 /* flags */ 0, 133 }, 134 #endif /* chips */ 135 136 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 137 defined(BCM_56870_A0) 138 { /* SOC_FORMAT_INT_NETWORK_HVE_TRIGGERS_FORMATfmt */ 139 /* format NETWORK_HVE_TRIGGERS_FORMATfmt */ 140 /* nFields */ 29, 141 /* *fields */ soc_NETWORK_HVE_TRIGGERS_FORMATfmt_fields, 142 /* bits */ 32, 143 /* flags */ 0, 144 }, 145 #endif /* chips */ 146 147 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 148 defined(BCM_56870_A0) 149 { /* SOC_FORMAT_INT_NEXT_PTR_ACTION_SETfmt */ 150 /* format NEXT_PTR_ACTION_SETfmt */ 151 /* nFields */ 2, 152 /* *fields */ soc_NEXT_PTR_ACTION_SETfmt_fields, 153 /* bits */ 19, 154 /* flags */ 0, 155 }, 156 #endif /* chips */ 157 158 #if defined(BCM_56440_A0) || defined(BCM_56840_A0) || \ 159 defined(BCM_56840_B0) 160 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODINGfmt */ 161 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 162 /* nFields */ 1, 163 /* *fields */ soc_NIV_CPU_OPCODE_ENCODINGfmt_fields, 164 /* bits */ 3, 165 /* flags */ 0, 166 }, 167 #endif /* chips */ 168 169 #if defined(BCM_53400_A0) 170 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt */ 171 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 172 /* nFields */ 1, 173 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 174 /* bits */ 3, 175 /* flags */ 0, 176 }, 177 #endif /* chips */ 178 179 #if defined(BCM_53540_A0) 180 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM53540_A0fmt */ 181 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 182 /* nFields */ 1, 183 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 184 /* bits */ 3, 185 /* flags */ 0, 186 }, 187 #endif /* chips */ 188 189 #if defined(BCM_53570_A0) 190 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM53570_A0fmt */ 191 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 192 /* nFields */ 1, 193 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 194 /* bits */ 3, 195 /* flags */ 0, 196 }, 197 #endif /* chips */ 198 199 #if defined(BCM_53570_B0) 200 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM53570_B0fmt */ 201 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 202 /* nFields */ 1, 203 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 204 /* bits */ 3, 205 /* flags */ 0, 206 }, 207 #endif /* chips */ 208 209 #if defined(BCM_56160_A0) 210 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56160_A0fmt */ 211 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 212 /* nFields */ 1, 213 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 214 /* bits */ 3, 215 /* flags */ 0, 216 }, 217 #endif /* chips */ 218 219 #if defined(BCM_56260_A0) 220 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56260_A0fmt */ 221 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 222 /* nFields */ 1, 223 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 224 /* bits */ 3, 225 /* flags */ 0, 226 }, 227 #endif /* chips */ 228 229 #if defined(BCM_56260_B0) 230 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56260_B0fmt */ 231 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 232 /* nFields */ 1, 233 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 234 /* bits */ 3, 235 /* flags */ 0, 236 }, 237 #endif /* chips */ 238 239 #if defined(BCM_56270_A0) 240 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56270_A0fmt */ 241 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 242 /* nFields */ 1, 243 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 244 /* bits */ 3, 245 /* flags */ 0, 246 }, 247 #endif /* chips */ 248 249 #if defined(BCM_56440_B0) 250 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56440_B0fmt */ 251 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 252 /* nFields */ 1, 253 /* *fields */ soc_NIV_CPU_OPCODE_ENCODINGfmt_fields, 254 /* bits */ 3, 255 /* flags */ 0, 256 }, 257 #endif /* chips */ 258 259 #if defined(BCM_56450_A0) 260 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56450_A0fmt */ 261 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 262 /* nFields */ 1, 263 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 264 /* bits */ 3, 265 /* flags */ 0, 266 }, 267 #endif /* chips */ 268 269 #if defined(BCM_56450_B0) 270 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56450_B0fmt */ 271 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 272 /* nFields */ 1, 273 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 274 /* bits */ 3, 275 /* flags */ 0, 276 }, 277 #endif /* chips */ 278 279 #if defined(BCM_56450_B1) 280 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56450_B1fmt */ 281 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 282 /* nFields */ 1, 283 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 284 /* bits */ 3, 285 /* flags */ 0, 286 }, 287 #endif /* chips */ 288 289 #if defined(BCM_56560_A0) 290 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56560_A0fmt */ 291 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 292 /* nFields */ 1, 293 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 294 /* bits */ 3, 295 /* flags */ 0, 296 }, 297 #endif /* chips */ 298 299 #if defined(BCM_56560_B0) 300 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56560_B0fmt */ 301 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 302 /* nFields */ 1, 303 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 304 /* bits */ 3, 305 /* flags */ 0, 306 }, 307 #endif /* chips */ 308 309 #if defined(BCM_56670_A0) 310 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56670_A0fmt */ 311 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 312 /* nFields */ 1, 313 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 314 /* bits */ 3, 315 /* flags */ 0, 316 }, 317 #endif /* chips */ 318 319 #if defined(BCM_56670_B0) 320 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56670_B0fmt */ 321 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 322 /* nFields */ 1, 323 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 324 /* bits */ 3, 325 /* flags */ 0, 326 }, 327 #endif /* chips */ 328 329 #if defined(BCM_56850_A0) 330 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56850_A0fmt */ 331 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 332 /* nFields */ 1, 333 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 334 /* bits */ 3, 335 /* flags */ 0, 336 }, 337 #endif /* chips */ 338 339 #if defined(BCM_56860_A0) 340 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56860_A0fmt */ 341 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 342 /* nFields */ 1, 343 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 344 /* bits */ 3, 345 /* flags */ 0, 346 }, 347 #endif /* chips */ 348 349 #if defined(BCM_56960_A0) 350 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56960_A0fmt */ 351 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 352 /* nFields */ 1, 353 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 354 /* bits */ 3, 355 /* flags */ 0, 356 }, 357 #endif /* chips */ 358 359 #if defined(BCM_56965_A0) 360 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56965_A0fmt */ 361 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 362 /* nFields */ 1, 363 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 364 /* bits */ 3, 365 /* flags */ 0, 366 }, 367 #endif /* chips */ 368 369 #if defined(BCM_56970_A0) 370 { /* SOC_FORMAT_INT_NIV_CPU_OPCODE_ENCODING_BCM56970_A0fmt */ 371 /* format NIV_CPU_OPCODE_ENCODINGfmt */ 372 /* nFields */ 1, 373 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 374 /* bits */ 3, 375 /* flags */ 0, 376 }, 377 #endif /* chips */ 378 379 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 380 { /* SOC_FORMAT_INT_NLF_CPU_OPCODESfmt */ 381 /* format NLF_CPU_OPCODESfmt */ 382 /* nFields */ 7, 383 /* *fields */ soc_NLF_CPU_OPCODESfmt_fields, 384 /* bits */ 7, 385 /* flags */ 0, 386 }, 387 #endif /* chips */ 388 389 #if defined(BCM_56640_A0) 390 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 391 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 392 /* nFields */ 6, 393 /* *fields */ soc_ISC_HG_STATS_COV_DEFSfmt_fields, 394 /* bits */ 16, 395 /* flags */ 0, 396 }, 397 #endif /* chips */ 398 399 #if defined(BCM_56340_A0) 400 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56340_A0fmt */ 401 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 402 /* nFields */ 6, 403 /* *fields */ soc_ISC_HG_STATS_COV_DEFSfmt_fields, 404 /* bits */ 16, 405 /* flags */ 0, 406 }, 407 #endif /* chips */ 408 409 #if defined(BCM_56560_A0) 410 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56560_A0fmt */ 411 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 412 /* nFields */ 7, 413 /* *fields */ soc_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56560_A0fmt_fields, 414 /* bits */ 17, 415 /* flags */ 0, 416 }, 417 #endif /* chips */ 418 419 #if defined(BCM_56560_B0) 420 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56560_B0fmt */ 421 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 422 /* nFields */ 7, 423 /* *fields */ soc_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56560_A0fmt_fields, 424 /* bits */ 17, 425 /* flags */ 0, 426 }, 427 #endif /* chips */ 428 429 #if defined(BCM_56670_A0) 430 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56670_A0fmt */ 431 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 432 /* nFields */ 7, 433 /* *fields */ soc_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56560_A0fmt_fields, 434 /* bits */ 17, 435 /* flags */ 0, 436 }, 437 #endif /* chips */ 438 439 #if defined(BCM_56670_B0) 440 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56670_B0fmt */ 441 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 442 /* nFields */ 7, 443 /* *fields */ soc_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56560_A0fmt_fields, 444 /* bits */ 17, 445 /* flags */ 0, 446 }, 447 #endif /* chips */ 448 449 #if defined(BCM_56850_A0) 450 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56850_A0fmt */ 451 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 452 /* nFields */ 6, 453 /* *fields */ soc_ISC_HG_STATS_COV_DEFSfmt_fields, 454 /* bits */ 16, 455 /* flags */ 0, 456 }, 457 #endif /* chips */ 458 459 #if defined(BCM_56860_A0) 460 { /* SOC_FORMAT_INT_NUM_QCN_CNM_RECEIVED_COV_DEFS_BCM56860_A0fmt */ 461 /* format NUM_QCN_CNM_RECEIVED_COV_DEFSfmt */ 462 /* nFields */ 7, 463 /* *fields */ soc_NUM_QCN_CNM_RECEIVED_COV_DEFSfmt_fields, 464 /* bits */ 17, 465 /* flags */ 0, 466 }, 467 #endif /* chips */ 468 469 #if defined(BCM_56440_A0) || defined(BCM_56840_A0) || \ 470 defined(BCM_56840_B0) 471 { /* SOC_FORMAT_INT_NVOQFC_DATAfmt */ 472 /* format NVOQFC_DATAfmt */ 473 /* nFields */ 3, 474 /* *fields */ soc_NVOQFC_DATAfmt_fields, 475 /* bits */ 512, 476 /* flags */ 0, 477 }, 478 #endif /* chips */ 479 480 #if defined(BCM_56440_B0) 481 { /* SOC_FORMAT_INT_NVOQFC_DATA_BCM56440_B0fmt */ 482 /* format NVOQFC_DATAfmt */ 483 /* nFields */ 3, 484 /* *fields */ soc_NVOQFC_DATAfmt_fields, 485 /* bits */ 512, 486 /* flags */ 0, 487 }, 488 #endif /* chips */ 489