allformats_m.i (442540B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_m.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 16 defined(BCM_56870_A0) 17 { /* SOC_FORMAT_INT_MAC_BLOCK_ACTION_SETfmt */ 18 /* format MAC_BLOCK_ACTION_SETfmt */ 19 /* nFields */ 2, 20 /* *fields */ soc_MAC_BLOCK_ACTION_SETfmt_fields, 21 /* bits */ 6, 22 /* flags */ 0, 23 }, 24 #endif /* chips */ 25 26 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 27 defined(BCM_56870_A0) 28 { /* SOC_FORMAT_INT_MAC_HDRfmt */ 29 /* format MAC_HDRfmt */ 30 /* nFields */ 3, 31 /* *fields */ soc_MAC_HDRfmt_fields, 32 /* bits */ 112, 33 /* flags */ 0, 34 }, 35 #endif /* chips */ 36 37 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 38 defined(BCM_56870_A0) 39 { /* SOC_FORMAT_INT_MAC_IP_BIND_ACTION_SETfmt */ 40 /* format MAC_IP_BIND_ACTION_SETfmt */ 41 /* nFields */ 4, 42 /* *fields */ soc_MAC_IP_BIND_ACTION_SETfmt_fields, 43 /* bits */ 65, 44 /* flags */ 0, 45 }, 46 #endif /* chips */ 47 48 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 49 { /* SOC_FORMAT_INT_MAC_RRSVfmt */ 50 /* format MAC_RRSVfmt */ 51 /* nFields */ 4, 52 /* *fields */ soc_MAC_RRSVfmt_fields, 53 /* bits */ 26, 54 /* flags */ 0, 55 }, 56 #endif /* chips */ 57 58 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 59 { /* SOC_FORMAT_INT_MAC_RSVfmt */ 60 /* format MAC_RSVfmt */ 61 /* nFields */ 20, 62 /* *fields */ soc_MAC_RSVfmt_fields, 63 /* bits */ 35, 64 /* flags */ 0, 65 }, 66 #endif /* chips */ 67 68 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 69 { /* SOC_FORMAT_INT_MAC_RSV_PFCfmt */ 70 /* format MAC_RSV_PFCfmt */ 71 /* nFields */ 2, 72 /* *fields */ soc_MAC_RSV_PFCfmt_fields, 73 /* bits */ 16, 74 /* flags */ 0, 75 }, 76 #endif /* chips */ 77 78 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 79 { /* SOC_FORMAT_INT_MAC_TSVfmt */ 80 /* format MAC_TSVfmt */ 81 /* nFields */ 16, 82 /* *fields */ soc_MAC_TSVfmt_fields, 83 /* bits */ 46, 84 /* flags */ 0, 85 }, 86 #endif /* chips */ 87 88 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 89 { /* SOC_FORMAT_INT_MATCH_ID_DOPfmt */ 90 /* format MATCH_ID_DOPfmt */ 91 /* nFields */ 3, 92 /* *fields */ soc_MATCH_ID_DOPfmt_fields, 93 /* bits */ 64, 94 /* flags */ 0, 95 }, 96 #endif /* chips */ 97 98 #if defined(BCM_56370_A0) 99 { /* SOC_FORMAT_INT_MATCH_ID_DOP_BCM56370_A0fmt */ 100 /* format MATCH_ID_DOPfmt */ 101 /* nFields */ 3, 102 /* *fields */ soc_MATCH_ID_DOP_BCM56370_A0fmt_fields, 103 /* bits */ 64, 104 /* flags */ 0, 105 }, 106 #endif /* chips */ 107 108 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 109 { /* SOC_FORMAT_INT_MATCH_ID_DOP_DOPfmt */ 110 /* format MATCH_ID_DOP_DOPfmt */ 111 /* nFields */ 7, 112 /* *fields */ soc_MATCH_ID_DOP_DOPfmt_fields, 113 /* bits */ 64, 114 /* flags */ 0, 115 }, 116 #endif /* chips */ 117 118 #if defined(BCM_56370_A0) 119 { /* SOC_FORMAT_INT_MATCH_ID_DOP_DOP_BCM56370_A0fmt */ 120 /* format MATCH_ID_DOP_DOPfmt */ 121 /* nFields */ 7, 122 /* *fields */ soc_MATCH_ID_DOP_DOP_BCM56370_A0fmt_fields, 123 /* bits */ 64, 124 /* flags */ 0, 125 }, 126 #endif /* chips */ 127 128 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 129 defined(BCM_56850_A0) || defined(BCM_56860_A0) 130 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFSfmt */ 131 /* format MA_STATE_COV_DEFSfmt */ 132 /* nFields */ 7, 133 /* *fields */ soc_MA_STATE_COV_DEFSfmt_fields, 134 /* bits */ 19, 135 /* flags */ 0, 136 }, 137 #endif /* chips */ 138 139 #if defined(BCM_53400_A0) 140 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM53400_A0fmt */ 141 /* format MA_STATE_COV_DEFSfmt */ 142 /* nFields */ 7, 143 /* *fields */ soc_MA_STATE_COV_DEFS_BCM53400_A0fmt_fields, 144 /* bits */ 18, 145 /* flags */ 0, 146 }, 147 #endif /* chips */ 148 149 #if defined(BCM_53540_A0) 150 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM53540_A0fmt */ 151 /* format MA_STATE_COV_DEFSfmt */ 152 /* nFields */ 7, 153 /* *fields */ soc_MA_STATE_COV_DEFS_BCM53400_A0fmt_fields, 154 /* bits */ 18, 155 /* flags */ 0, 156 }, 157 #endif /* chips */ 158 159 #if defined(BCM_53570_A0) 160 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM53570_A0fmt */ 161 /* format MA_STATE_COV_DEFSfmt */ 162 /* nFields */ 7, 163 /* *fields */ soc_MA_STATE_COV_DEFS_BCM53400_A0fmt_fields, 164 /* bits */ 18, 165 /* flags */ 0, 166 }, 167 #endif /* chips */ 168 169 #if defined(BCM_53570_B0) 170 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM53570_B0fmt */ 171 /* format MA_STATE_COV_DEFSfmt */ 172 /* nFields */ 7, 173 /* *fields */ soc_MA_STATE_COV_DEFS_BCM53400_A0fmt_fields, 174 /* bits */ 18, 175 /* flags */ 0, 176 }, 177 #endif /* chips */ 178 179 #if defined(BCM_56150_A0) 180 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM56150_A0fmt */ 181 /* format MA_STATE_COV_DEFSfmt */ 182 /* nFields */ 7, 183 /* *fields */ soc_MA_STATE_COV_DEFS_BCM56150_A0fmt_fields, 184 /* bits */ 18, 185 /* flags */ 0, 186 }, 187 #endif /* chips */ 188 189 #if defined(BCM_56160_A0) 190 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM56160_A0fmt */ 191 /* format MA_STATE_COV_DEFSfmt */ 192 /* nFields */ 7, 193 /* *fields */ soc_MA_STATE_COV_DEFS_BCM53400_A0fmt_fields, 194 /* bits */ 18, 195 /* flags */ 0, 196 }, 197 #endif /* chips */ 198 199 #if defined(BCM_56560_A0) 200 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM56560_A0fmt */ 201 /* format MA_STATE_COV_DEFSfmt */ 202 /* nFields */ 7, 203 /* *fields */ soc_MA_STATE_COV_DEFS_BCM56560_A0fmt_fields, 204 /* bits */ 19, 205 /* flags */ 0, 206 }, 207 #endif /* chips */ 208 209 #if defined(BCM_56560_B0) 210 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM56560_B0fmt */ 211 /* format MA_STATE_COV_DEFSfmt */ 212 /* nFields */ 7, 213 /* *fields */ soc_MA_STATE_COV_DEFS_BCM56560_A0fmt_fields, 214 /* bits */ 19, 215 /* flags */ 0, 216 }, 217 #endif /* chips */ 218 219 #if defined(BCM_56670_A0) 220 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM56670_A0fmt */ 221 /* format MA_STATE_COV_DEFSfmt */ 222 /* nFields */ 7, 223 /* *fields */ soc_MA_STATE_COV_DEFS_BCM56560_A0fmt_fields, 224 /* bits */ 19, 225 /* flags */ 0, 226 }, 227 #endif /* chips */ 228 229 #if defined(BCM_56670_B0) 230 { /* SOC_FORMAT_INT_MA_STATE_COV_DEFS_BCM56670_B0fmt */ 231 /* format MA_STATE_COV_DEFSfmt */ 232 /* nFields */ 7, 233 /* *fields */ soc_MA_STATE_COV_DEFS_BCM56560_A0fmt_fields, 234 /* bits */ 19, 235 /* flags */ 0, 236 }, 237 #endif /* chips */ 238 239 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 240 defined(BCM_56970_A0) 241 { /* SOC_FORMAT_INT_MB_TCB_TO_DEQ_ECC_INFOfmt */ 242 /* format MB_TCB_TO_DEQ_ECC_INFOfmt */ 243 /* nFields */ 18, 244 /* *fields */ soc_MB_TCB_TO_DEQ_ECC_INFOfmt_fields, 245 /* bits */ 56, 246 /* flags */ 0, 247 }, 248 #endif /* chips */ 249 250 #if defined(BCM_56370_A0) 251 { /* SOC_FORMAT_INT_MB_TCB_TO_DEQ_ECC_INFO_BCM56370_A0fmt */ 252 /* format MB_TCB_TO_DEQ_ECC_INFOfmt */ 253 /* nFields */ 12, 254 /* *fields */ soc_MB_TCB_TO_DEQ_ECC_INFO_BCM56370_A0fmt_fields, 255 /* bits */ 42, 256 /* flags */ 0, 257 }, 258 #endif /* chips */ 259 260 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 261 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 262 defined(BCM_56965_A0) || defined(BCM_56970_A0) 263 { /* SOC_FORMAT_INT_MB_TO_DQX_HDRMISC_INFOfmt */ 264 /* format MB_TO_DQX_HDRMISC_INFOfmt */ 265 /* nFields */ 5, 266 /* *fields */ soc_MB_TO_DQX_HDRMISC_INFOfmt_fields, 267 /* bits */ 13, 268 /* flags */ 0, 269 }, 270 #endif /* chips */ 271 272 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 273 { /* SOC_FORMAT_INT_MCQ_QDBfmt */ 274 /* format MCQ_QDBfmt */ 275 /* nFields */ 20, 276 /* *fields */ soc_MCQ_QDBfmt_fields, 277 /* bits */ 53, 278 /* flags */ 0, 279 }, 280 #endif /* chips */ 281 282 #if defined(BCM_56340_A0) 283 { /* SOC_FORMAT_INT_MCQ_QDB_BCM56340_A0fmt */ 284 /* format MCQ_QDBfmt */ 285 /* nFields */ 22, 286 /* *fields */ soc_MCQ_QDB_BCM56640_A0fmt_fields, 287 /* bits */ 53, 288 /* flags */ 0, 289 }, 290 #endif /* chips */ 291 292 #if defined(BCM_56640_A0) 293 { /* SOC_FORMAT_INT_MCQ_QDB_BCM56640_A0fmt */ 294 /* format MCQ_QDBfmt */ 295 /* nFields */ 22, 296 /* *fields */ soc_MCQ_QDB_BCM56640_A0fmt_fields, 297 /* bits */ 53, 298 /* flags */ 0, 299 }, 300 #endif /* chips */ 301 302 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 303 { /* SOC_FORMAT_INT_MC_INDICES_DOPfmt */ 304 /* format MC_INDICES_DOPfmt */ 305 /* nFields */ 4, 306 /* *fields */ soc_MC_INDICES_DOPfmt_fields, 307 /* bits */ 32, 308 /* flags */ 0, 309 }, 310 #endif /* chips */ 311 312 #if defined(BCM_56370_A0) 313 { /* SOC_FORMAT_INT_MC_INDICES_DOP_BCM56370_A0fmt */ 314 /* format MC_INDICES_DOPfmt */ 315 /* nFields */ 4, 316 /* *fields */ soc_MC_INDICES_DOP_BCM56370_A0fmt_fields, 317 /* bits */ 32, 318 /* flags */ 0, 319 }, 320 #endif /* chips */ 321 322 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 323 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 324 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 325 defined(BCM_56980_A0) || defined(BCM_56980_B0) 326 { /* SOC_FORMAT_INT_MEMADDRfmt */ 327 /* format MEMADDRfmt */ 328 /* nFields */ 3, 329 /* *fields */ soc_MEMADDRfmt_fields, 330 /* bits */ 32, 331 /* flags */ 0, 332 }, 333 #endif /* chips */ 334 335 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 336 { /* SOC_FORMAT_INT_MEMADR_EGR_FLEX_PREEMPT_LOOKUPfmt */ 337 /* format MEMADR_EGR_FLEX_PREEMPT_LOOKUPfmt */ 338 /* nFields */ 1, 339 /* *fields */ soc_MEMADR_EGR_FLEX_PREEMPT_LOOKUPfmt_fields, 340 /* bits */ 5, 341 /* flags */ 0, 342 }, 343 #endif /* chips */ 344 345 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 346 { /* SOC_FORMAT_INT_MEMADR_EGR_FLEX_PREEMPT_XFR_COUNTfmt */ 347 /* format MEMADR_EGR_FLEX_PREEMPT_XFR_COUNTfmt */ 348 /* nFields */ 1, 349 /* *fields */ soc_MEMADR_EGR_FLEX_PREEMPT_XFR_COUNTfmt_fields, 350 /* bits */ 7, 351 /* flags */ 0, 352 }, 353 #endif /* chips */ 354 355 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 356 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW0fmt */ 357 /* format MIB_MEMORY_ROW0fmt */ 358 /* nFields */ 8, 359 /* *fields */ soc_MIB_MEMORY_ROW0fmt_fields, 360 /* bits */ 488, 361 /* flags */ 0, 362 }, 363 #endif /* chips */ 364 365 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 366 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW1fmt */ 367 /* format MIB_MEMORY_ROW1fmt */ 368 /* nFields */ 8, 369 /* *fields */ soc_MIB_MEMORY_ROW1fmt_fields, 370 /* bits */ 488, 371 /* flags */ 0, 372 }, 373 #endif /* chips */ 374 375 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 376 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW2fmt */ 377 /* format MIB_MEMORY_ROW2fmt */ 378 /* nFields */ 8, 379 /* *fields */ soc_MIB_MEMORY_ROW2fmt_fields, 380 /* bits */ 488, 381 /* flags */ 0, 382 }, 383 #endif /* chips */ 384 385 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 386 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW3fmt */ 387 /* format MIB_MEMORY_ROW3fmt */ 388 /* nFields */ 8, 389 /* *fields */ soc_MIB_MEMORY_ROW3fmt_fields, 390 /* bits */ 488, 391 /* flags */ 0, 392 }, 393 #endif /* chips */ 394 395 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 396 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW4fmt */ 397 /* format MIB_MEMORY_ROW4fmt */ 398 /* nFields */ 8, 399 /* *fields */ soc_MIB_MEMORY_ROW4fmt_fields, 400 /* bits */ 488, 401 /* flags */ 0, 402 }, 403 #endif /* chips */ 404 405 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 406 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW5fmt */ 407 /* format MIB_MEMORY_ROW5fmt */ 408 /* nFields */ 8, 409 /* *fields */ soc_MIB_MEMORY_ROW5fmt_fields, 410 /* bits */ 488, 411 /* flags */ 0, 412 }, 413 #endif /* chips */ 414 415 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 416 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW6fmt */ 417 /* format MIB_MEMORY_ROW6fmt */ 418 /* nFields */ 8, 419 /* *fields */ soc_MIB_MEMORY_ROW6fmt_fields, 420 /* bits */ 488, 421 /* flags */ 0, 422 }, 423 #endif /* chips */ 424 425 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 426 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW7fmt */ 427 /* format MIB_MEMORY_ROW7fmt */ 428 /* nFields */ 8, 429 /* *fields */ soc_MIB_MEMORY_ROW7fmt_fields, 430 /* bits */ 488, 431 /* flags */ 0, 432 }, 433 #endif /* chips */ 434 435 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 436 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW8fmt */ 437 /* format MIB_MEMORY_ROW8fmt */ 438 /* nFields */ 8, 439 /* *fields */ soc_MIB_MEMORY_ROW8fmt_fields, 440 /* bits */ 488, 441 /* flags */ 0, 442 }, 443 #endif /* chips */ 444 445 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 446 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW9fmt */ 447 /* format MIB_MEMORY_ROW9fmt */ 448 /* nFields */ 8, 449 /* *fields */ soc_MIB_MEMORY_ROW9fmt_fields, 450 /* bits */ 488, 451 /* flags */ 0, 452 }, 453 #endif /* chips */ 454 455 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 456 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW10fmt */ 457 /* format MIB_MEMORY_ROW10fmt */ 458 /* nFields */ 8, 459 /* *fields */ soc_MIB_MEMORY_ROW10fmt_fields, 460 /* bits */ 488, 461 /* flags */ 0, 462 }, 463 #endif /* chips */ 464 465 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 466 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW11fmt */ 467 /* format MIB_MEMORY_ROW11fmt */ 468 /* nFields */ 8, 469 /* *fields */ soc_MIB_MEMORY_ROW11fmt_fields, 470 /* bits */ 488, 471 /* flags */ 0, 472 }, 473 #endif /* chips */ 474 475 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 476 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW12fmt */ 477 /* format MIB_MEMORY_ROW12fmt */ 478 /* nFields */ 8, 479 /* *fields */ soc_MIB_MEMORY_ROW12fmt_fields, 480 /* bits */ 488, 481 /* flags */ 0, 482 }, 483 #endif /* chips */ 484 485 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 486 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW13fmt */ 487 /* format MIB_MEMORY_ROW13fmt */ 488 /* nFields */ 1, 489 /* *fields */ soc_MIB_MEMORY_ROW13fmt_fields, 490 /* bits */ 512, 491 /* flags */ 0, 492 }, 493 #endif /* chips */ 494 495 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 496 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW14fmt */ 497 /* format MIB_MEMORY_ROW14fmt */ 498 /* nFields */ 1, 499 /* *fields */ soc_MIB_MEMORY_ROW14fmt_fields, 500 /* bits */ 512, 501 /* flags */ 0, 502 }, 503 #endif /* chips */ 504 505 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 506 { /* SOC_FORMAT_INT_MIB_MEMORY_ROW15fmt */ 507 /* format MIB_MEMORY_ROW15fmt */ 508 /* nFields */ 1, 509 /* *fields */ soc_MIB_MEMORY_ROW15fmt_fields, 510 /* bits */ 512, 511 /* flags */ 0, 512 }, 513 #endif /* chips */ 514 515 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 516 defined(BCM_56870_A0) 517 { /* SOC_FORMAT_INT_MIM_TUNNEL_TERM_ACTION_SETfmt */ 518 /* format MIM_TUNNEL_TERM_ACTION_SETfmt */ 519 /* nFields */ 1, 520 /* *fields */ soc_MIM_TUNNEL_TERM_ACTION_SETfmt_fields, 521 /* bits */ 1, 522 /* flags */ 0, 523 }, 524 #endif /* chips */ 525 526 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 527 { /* SOC_FORMAT_INT_MIRROR_DOPfmt */ 528 /* format MIRROR_DOPfmt */ 529 /* nFields */ 8, 530 /* *fields */ soc_MIRROR_DOPfmt_fields, 531 /* bits */ 64, 532 /* flags */ 0, 533 }, 534 #endif /* chips */ 535 536 #if defined(BCM_56370_A0) 537 { /* SOC_FORMAT_INT_MIRROR_DOP_BCM56370_A0fmt */ 538 /* format MIRROR_DOPfmt */ 539 /* nFields */ 8, 540 /* *fields */ soc_MIRROR_DOP_BCM56370_A0fmt_fields, 541 /* bits */ 64, 542 /* flags */ 0, 543 }, 544 #endif /* chips */ 545 546 #if defined(BCM_56504_A0) 547 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADERfmt */ 548 /* format MMU_CBPPACKETHEADERfmt */ 549 /* nFields */ 21, 550 /* *fields */ soc_MMU_CBPPACKETHEADERfmt_fields, 551 /* bits */ 78, 552 /* flags */ 0, 553 }, 554 #endif /* chips */ 555 556 #if defined(BCM_53314_A0) 557 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM53314_A0fmt */ 558 /* format MMU_CBPPACKETHEADERfmt */ 559 /* nFields */ 22, 560 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM53314_A0fmt_fields, 561 /* bits */ 68, 562 /* flags */ 0, 563 }, 564 #endif /* chips */ 565 566 #if defined(BCM_53324_A0) 567 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM53324_A0fmt */ 568 /* format MMU_CBPPACKETHEADERfmt */ 569 /* nFields */ 22, 570 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM53314_A0fmt_fields, 571 /* bits */ 68, 572 /* flags */ 0, 573 }, 574 #endif /* chips */ 575 576 #if defined(BCM_53400_A0) 577 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM53400_A0fmt */ 578 /* format MMU_CBPPACKETHEADERfmt */ 579 /* nFields */ 72, 580 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM53400_A0fmt_fields, 581 /* bits */ 315, 582 /* flags */ 0, 583 }, 584 #endif /* chips */ 585 586 #if defined(BCM_53540_A0) 587 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM53540_A0fmt */ 588 /* format MMU_CBPPACKETHEADERfmt */ 589 /* nFields */ 71, 590 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56160_A0fmt_fields, 591 /* bits */ 315, 592 /* flags */ 0, 593 }, 594 #endif /* chips */ 595 596 #if defined(BCM_53570_A0) 597 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM53570_A0fmt */ 598 /* format MMU_CBPPACKETHEADERfmt */ 599 /* nFields */ 82, 600 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM53570_A0fmt_fields, 601 /* bits */ 363, 602 /* flags */ 0, 603 }, 604 #endif /* chips */ 605 606 #if defined(BCM_53570_B0) 607 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM53570_B0fmt */ 608 /* format MMU_CBPPACKETHEADERfmt */ 609 /* nFields */ 83, 610 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM53570_B0fmt_fields, 611 /* bits */ 363, 612 /* flags */ 0, 613 }, 614 #endif /* chips */ 615 616 #if defined(BCM_56142_A0) 617 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56142_A0fmt */ 618 /* format MMU_CBPPACKETHEADERfmt */ 619 /* nFields */ 56, 620 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56142_A0fmt_fields, 621 /* bits */ 240, 622 /* flags */ 0, 623 }, 624 #endif /* chips */ 625 626 #if defined(BCM_56150_A0) 627 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56150_A0fmt */ 628 /* format MMU_CBPPACKETHEADERfmt */ 629 /* nFields */ 60, 630 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56150_A0fmt_fields, 631 /* bits */ 293, 632 /* flags */ 0, 633 }, 634 #endif /* chips */ 635 636 #if defined(BCM_56160_A0) 637 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56160_A0fmt */ 638 /* format MMU_CBPPACKETHEADERfmt */ 639 /* nFields */ 71, 640 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56160_A0fmt_fields, 641 /* bits */ 315, 642 /* flags */ 0, 643 }, 644 #endif /* chips */ 645 646 #if defined(BCM_56224_A0) 647 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56224_A0fmt */ 648 /* format MMU_CBPPACKETHEADERfmt */ 649 /* nFields */ 27, 650 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56224_A0fmt_fields, 651 /* bits */ 94, 652 /* flags */ 0, 653 }, 654 #endif /* chips */ 655 656 #if defined(BCM_56224_B0) 657 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56224_B0fmt */ 658 /* format MMU_CBPPACKETHEADERfmt */ 659 /* nFields */ 27, 660 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56224_A0fmt_fields, 661 /* bits */ 94, 662 /* flags */ 0, 663 }, 664 #endif /* chips */ 665 666 #if defined(BCM_56314_A0) 667 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56314_A0fmt */ 668 /* format MMU_CBPPACKETHEADERfmt */ 669 /* nFields */ 26, 670 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56504_B0fmt_fields, 671 /* bits */ 86, 672 /* flags */ 0, 673 }, 674 #endif /* chips */ 675 676 #if defined(BCM_56504_B0) 677 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56504_B0fmt */ 678 /* format MMU_CBPPACKETHEADERfmt */ 679 /* nFields */ 26, 680 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56504_B0fmt_fields, 681 /* bits */ 86, 682 /* flags */ 0, 683 }, 684 #endif /* chips */ 685 686 #if defined(BCM_56514_A0) 687 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56514_A0fmt */ 688 /* format MMU_CBPPACKETHEADERfmt */ 689 /* nFields */ 26, 690 /* *fields */ soc_MMU_CBPPACKETHEADER_BCM56504_B0fmt_fields, 691 /* bits */ 86, 692 /* flags */ 0, 693 }, 694 #endif /* chips */ 695 696 #if defined(BCM_56800_A0) 697 { /* SOC_FORMAT_INT_MMU_CBPPACKETHEADER_BCM56800_A0fmt */ 698 /* format MMU_CBPPACKETHEADERfmt */ 699 /* nFields */ 21, 700 /* *fields */ soc_MMU_CBPPACKETHEADERfmt_fields, 701 /* bits */ 78, 702 /* flags */ 0, 703 }, 704 #endif /* chips */ 705 706 #if defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 707 defined(BCM_56800_A0) 708 { /* SOC_FORMAT_INT_MMU_CCPHEADERfmt */ 709 /* format MMU_CCPHEADERfmt */ 710 /* nFields */ 8, 711 /* *fields */ soc_MMU_CCPHEADERfmt_fields, 712 /* bits */ 45, 713 /* flags */ 0, 714 }, 715 #endif /* chips */ 716 717 #if defined(BCM_53314_A0) 718 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM53314_A0fmt */ 719 /* format MMU_CCPHEADERfmt */ 720 /* nFields */ 8, 721 /* *fields */ soc_MMU_CCPHEADER_BCM53314_A0fmt_fields, 722 /* bits */ 45, 723 /* flags */ 0, 724 }, 725 #endif /* chips */ 726 727 #if defined(BCM_53324_A0) 728 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM53324_A0fmt */ 729 /* format MMU_CCPHEADERfmt */ 730 /* nFields */ 8, 731 /* *fields */ soc_MMU_CCPHEADER_BCM53314_A0fmt_fields, 732 /* bits */ 45, 733 /* flags */ 0, 734 }, 735 #endif /* chips */ 736 737 #if defined(BCM_53400_A0) 738 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM53400_A0fmt */ 739 /* format MMU_CCPHEADERfmt */ 740 /* nFields */ 12, 741 /* *fields */ soc_MMU_CCPHEADER_BCM53400_A0fmt_fields, 742 /* bits */ 58, 743 /* flags */ 0, 744 }, 745 #endif /* chips */ 746 747 #if defined(BCM_53540_A0) 748 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM53540_A0fmt */ 749 /* format MMU_CCPHEADERfmt */ 750 /* nFields */ 12, 751 /* *fields */ soc_MMU_CCPHEADER_BCM53540_A0fmt_fields, 752 /* bits */ 56, 753 /* flags */ 0, 754 }, 755 #endif /* chips */ 756 757 #if defined(BCM_53570_A0) 758 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM53570_A0fmt */ 759 /* format MMU_CCPHEADERfmt */ 760 /* nFields */ 14, 761 /* *fields */ soc_MMU_CCPHEADER_BCM53570_A0fmt_fields, 762 /* bits */ 65, 763 /* flags */ 0, 764 }, 765 #endif /* chips */ 766 767 #if defined(BCM_53570_B0) 768 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM53570_B0fmt */ 769 /* format MMU_CCPHEADERfmt */ 770 /* nFields */ 14, 771 /* *fields */ soc_MMU_CCPHEADER_BCM53570_A0fmt_fields, 772 /* bits */ 65, 773 /* flags */ 0, 774 }, 775 #endif /* chips */ 776 777 #if defined(BCM_56142_A0) 778 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM56142_A0fmt */ 779 /* format MMU_CCPHEADERfmt */ 780 /* nFields */ 11, 781 /* *fields */ soc_MMU_CCPHEADER_BCM56142_A0fmt_fields, 782 /* bits */ 55, 783 /* flags */ 0, 784 }, 785 #endif /* chips */ 786 787 #if defined(BCM_56150_A0) 788 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM56150_A0fmt */ 789 /* format MMU_CCPHEADERfmt */ 790 /* nFields */ 11, 791 /* *fields */ soc_MMU_CCPHEADER_BCM56150_A0fmt_fields, 792 /* bits */ 55, 793 /* flags */ 0, 794 }, 795 #endif /* chips */ 796 797 #if defined(BCM_56160_A0) 798 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM56160_A0fmt */ 799 /* format MMU_CCPHEADERfmt */ 800 /* nFields */ 12, 801 /* *fields */ soc_MMU_CCPHEADER_BCM53400_A0fmt_fields, 802 /* bits */ 58, 803 /* flags */ 0, 804 }, 805 #endif /* chips */ 806 807 #if defined(BCM_56224_A0) 808 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM56224_A0fmt */ 809 /* format MMU_CCPHEADERfmt */ 810 /* nFields */ 7, 811 /* *fields */ soc_MMU_CCPHEADER_BCM56224_A0fmt_fields, 812 /* bits */ 45, 813 /* flags */ 0, 814 }, 815 #endif /* chips */ 816 817 #if defined(BCM_56224_B0) 818 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM56224_B0fmt */ 819 /* format MMU_CCPHEADERfmt */ 820 /* nFields */ 8, 821 /* *fields */ soc_MMU_CCPHEADER_BCM56224_B0fmt_fields, 822 /* bits */ 45, 823 /* flags */ 0, 824 }, 825 #endif /* chips */ 826 827 #if defined(BCM_56314_A0) 828 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM56314_A0fmt */ 829 /* format MMU_CCPHEADERfmt */ 830 /* nFields */ 8, 831 /* *fields */ soc_MMU_CCPHEADERfmt_fields, 832 /* bits */ 45, 833 /* flags */ 0, 834 }, 835 #endif /* chips */ 836 837 #if defined(BCM_56514_A0) 838 { /* SOC_FORMAT_INT_MMU_CCPHEADER_BCM56514_A0fmt */ 839 /* format MMU_CCPHEADERfmt */ 840 /* nFields */ 8, 841 /* *fields */ soc_MMU_CCPHEADERfmt_fields, 842 /* bits */ 45, 843 /* flags */ 0, 844 }, 845 #endif /* chips */ 846 847 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 848 { /* SOC_FORMAT_INT_MMU_CCP_TO_CFAP_CELL_INFOfmt */ 849 /* format MMU_CCP_TO_CFAP_CELL_INFOfmt */ 850 /* nFields */ 10, 851 /* *fields */ soc_MMU_CCP_TO_CFAP_CELL_INFOfmt_fields, 852 /* bits */ 39, 853 /* flags */ 0, 854 }, 855 #endif /* chips */ 856 857 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) 858 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRUfmt */ 859 /* format MMU_CELLHDR_2_CRRUfmt */ 860 /* nFields */ 7, 861 /* *fields */ soc_MMU_CELLHDR_2_CRRUfmt_fields, 862 /* bits */ 33, 863 /* flags */ 0, 864 }, 865 #endif /* chips */ 866 867 #if defined(BCM_53314_A0) 868 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM53314_A0fmt */ 869 /* format MMU_CELLHDR_2_CRRUfmt */ 870 /* nFields */ 7, 871 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM53314_A0fmt_fields, 872 /* bits */ 33, 873 /* flags */ 0, 874 }, 875 #endif /* chips */ 876 877 #if defined(BCM_53324_A0) 878 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM53324_A0fmt */ 879 /* format MMU_CELLHDR_2_CRRUfmt */ 880 /* nFields */ 7, 881 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM53314_A0fmt_fields, 882 /* bits */ 33, 883 /* flags */ 0, 884 }, 885 #endif /* chips */ 886 887 #if defined(BCM_53400_A0) 888 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM53400_A0fmt */ 889 /* format MMU_CELLHDR_2_CRRUfmt */ 890 /* nFields */ 7, 891 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM53400_A0fmt_fields, 892 /* bits */ 33, 893 /* flags */ 0, 894 }, 895 #endif /* chips */ 896 897 #if defined(BCM_53540_A0) 898 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM53540_A0fmt */ 899 /* format MMU_CELLHDR_2_CRRUfmt */ 900 /* nFields */ 7, 901 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM53540_A0fmt_fields, 902 /* bits */ 31, 903 /* flags */ 0, 904 }, 905 #endif /* chips */ 906 907 #if defined(BCM_53570_A0) 908 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM53570_A0fmt */ 909 /* format MMU_CELLHDR_2_CRRUfmt */ 910 /* nFields */ 8, 911 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM53570_A0fmt_fields, 912 /* bits */ 28, 913 /* flags */ 0, 914 }, 915 #endif /* chips */ 916 917 #if defined(BCM_53570_B0) 918 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM53570_B0fmt */ 919 /* format MMU_CELLHDR_2_CRRUfmt */ 920 /* nFields */ 8, 921 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM53570_A0fmt_fields, 922 /* bits */ 28, 923 /* flags */ 0, 924 }, 925 #endif /* chips */ 926 927 #if defined(BCM_56142_A0) 928 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM56142_A0fmt */ 929 /* format MMU_CELLHDR_2_CRRUfmt */ 930 /* nFields */ 7, 931 /* *fields */ soc_MMU_CELLHDR_2_CRRUfmt_fields, 932 /* bits */ 33, 933 /* flags */ 0, 934 }, 935 #endif /* chips */ 936 937 #if defined(BCM_56150_A0) 938 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM56150_A0fmt */ 939 /* format MMU_CELLHDR_2_CRRUfmt */ 940 /* nFields */ 7, 941 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM56150_A0fmt_fields, 942 /* bits */ 33, 943 /* flags */ 0, 944 }, 945 #endif /* chips */ 946 947 #if defined(BCM_56160_A0) 948 { /* SOC_FORMAT_INT_MMU_CELLHDR_2_CRRU_BCM56160_A0fmt */ 949 /* format MMU_CELLHDR_2_CRRUfmt */ 950 /* nFields */ 7, 951 /* *fields */ soc_MMU_CELLHDR_2_CRRU_BCM53400_A0fmt_fields, 952 /* bits */ 33, 953 /* flags */ 0, 954 }, 955 #endif /* chips */ 956 957 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 958 defined(BCM_56870_A0) || defined(BCM_56970_A0) 959 { /* SOC_FORMAT_INT_MMU_CFAP_MSBUSfmt */ 960 /* format MMU_CFAP_MSBUSfmt */ 961 /* nFields */ 15, 962 /* *fields */ soc_MMU_CFAP_MSBUSfmt_fields, 963 /* bits */ 138, 964 /* flags */ 0, 965 }, 966 #endif /* chips */ 967 968 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 969 { /* SOC_FORMAT_INT_MMU_CFAP_TO_CRB_ENQ_INFOfmt */ 970 /* format MMU_CFAP_TO_CRB_ENQ_INFOfmt */ 971 /* nFields */ 2, 972 /* *fields */ soc_MMU_CFAP_TO_CRB_ENQ_INFOfmt_fields, 973 /* bits */ 19, 974 /* flags */ 0, 975 }, 976 #endif /* chips */ 977 978 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 979 { /* SOC_FORMAT_INT_MMU_CFAP_TO_MB_CELL_INFOfmt */ 980 /* format MMU_CFAP_TO_MB_CELL_INFOfmt */ 981 /* nFields */ 2, 982 /* *fields */ soc_MMU_CFAP_TO_MB_CELL_INFOfmt_fields, 983 /* bits */ 19, 984 /* flags */ 0, 985 }, 986 #endif /* chips */ 987 988 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 989 { /* SOC_FORMAT_INT_MMU_CFAP_TO_THDI_REL_INFOfmt */ 990 /* format MMU_CFAP_TO_THDI_REL_INFOfmt */ 991 /* nFields */ 9, 992 /* *fields */ soc_MMU_CFAP_TO_THDI_REL_INFOfmt_fields, 993 /* bits */ 21, 994 /* flags */ 0, 995 }, 996 #endif /* chips */ 997 998 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 999 { /* SOC_FORMAT_INT_MMU_CFAP_TO_THDO_DEQCHK_INFOfmt */ 1000 /* format MMU_CFAP_TO_THDO_DEQCHK_INFOfmt */ 1001 /* nFields */ 4, 1002 /* *fields */ soc_MMU_CFAP_TO_THDO_DEQCHK_INFOfmt_fields, 1003 /* bits */ 8, 1004 /* flags */ 0, 1005 }, 1006 #endif /* chips */ 1007 1008 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1009 { /* SOC_FORMAT_INT_MMU_CLSCH_TO_PKSCH_PICK_INFOfmt */ 1010 /* format MMU_CLSCH_TO_PKSCH_PICK_INFOfmt */ 1011 /* nFields */ 3, 1012 /* *fields */ soc_MMU_CLSCH_TO_PKSCH_PICK_INFOfmt_fields, 1013 /* bits */ 8, 1014 /* flags */ 0, 1015 }, 1016 #endif /* chips */ 1017 1018 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1019 { /* SOC_FORMAT_INT_MMU_CLSCH_TO_SHP_DEQ_INFOfmt */ 1020 /* format MMU_CLSCH_TO_SHP_DEQ_INFOfmt */ 1021 /* nFields */ 4, 1022 /* *fields */ soc_MMU_CLSCH_TO_SHP_DEQ_INFOfmt_fields, 1023 /* bits */ 8, 1024 /* flags */ 0, 1025 }, 1026 #endif /* chips */ 1027 1028 #if defined(BCM_53400_A0) || defined(BCM_56160_A0) 1029 { /* SOC_FORMAT_INT_MMU_CMICXQHEADERfmt */ 1030 /* format MMU_CMICXQHEADERfmt */ 1031 /* nFields */ 9, 1032 /* *fields */ soc_MMU_CMICXQHEADERfmt_fields, 1033 /* bits */ 81, 1034 /* flags */ 0, 1035 }, 1036 #endif /* chips */ 1037 1038 #if defined(BCM_53540_A0) 1039 { /* SOC_FORMAT_INT_MMU_CMICXQHEADER_BCM53540_A0fmt */ 1040 /* format MMU_CMICXQHEADERfmt */ 1041 /* nFields */ 9, 1042 /* *fields */ soc_MMU_CMICXQHEADER_BCM53540_A0fmt_fields, 1043 /* bits */ 79, 1044 /* flags */ 0, 1045 }, 1046 #endif /* chips */ 1047 1048 #if defined(BCM_53570_A0) 1049 { /* SOC_FORMAT_INT_MMU_CMICXQHEADER_BCM53570_A0fmt */ 1050 /* format MMU_CMICXQHEADERfmt */ 1051 /* nFields */ 9, 1052 /* *fields */ soc_MMU_CMICXQHEADER_BCM53570_A0fmt_fields, 1053 /* bits */ 91, 1054 /* flags */ 0, 1055 }, 1056 #endif /* chips */ 1057 1058 #if defined(BCM_53570_B0) 1059 { /* SOC_FORMAT_INT_MMU_CMICXQHEADER_BCM53570_B0fmt */ 1060 /* format MMU_CMICXQHEADERfmt */ 1061 /* nFields */ 9, 1062 /* *fields */ soc_MMU_CMICXQHEADER_BCM53570_A0fmt_fields, 1063 /* bits */ 91, 1064 /* flags */ 0, 1065 }, 1066 #endif /* chips */ 1067 1068 #if defined(BCM_56860_A0) 1069 { /* SOC_FORMAT_INT_MMU_COEFC_INDEXfmt */ 1070 /* format MMU_COEFC_INDEXfmt */ 1071 /* nFields */ 3, 1072 /* *fields */ soc_MMU_COEFC_INDEXfmt_fields, 1073 /* bits */ 16, 1074 /* flags */ 0, 1075 }, 1076 #endif /* chips */ 1077 1078 #if defined(BCM_56560_A0) 1079 { /* SOC_FORMAT_INT_MMU_COEFC_INDEX_BCM56560_A0fmt */ 1080 /* format MMU_COEFC_INDEXfmt */ 1081 /* nFields */ 3, 1082 /* *fields */ soc_MMU_COEFC_INDEX_BCM56560_A0fmt_fields, 1083 /* bits */ 16, 1084 /* flags */ 0, 1085 }, 1086 #endif /* chips */ 1087 1088 #if defined(BCM_56560_B0) 1089 { /* SOC_FORMAT_INT_MMU_COEFC_INDEX_BCM56560_B0fmt */ 1090 /* format MMU_COEFC_INDEXfmt */ 1091 /* nFields */ 3, 1092 /* *fields */ soc_MMU_COEFC_INDEX_BCM56560_A0fmt_fields, 1093 /* bits */ 16, 1094 /* flags */ 0, 1095 }, 1096 #endif /* chips */ 1097 1098 #if defined(BCM_56670_A0) 1099 { /* SOC_FORMAT_INT_MMU_COEFC_INDEX_BCM56670_A0fmt */ 1100 /* format MMU_COEFC_INDEXfmt */ 1101 /* nFields */ 3, 1102 /* *fields */ soc_MMU_COEFC_INDEX_BCM56670_A0fmt_fields, 1103 /* bits */ 14, 1104 /* flags */ 0, 1105 }, 1106 #endif /* chips */ 1107 1108 #if defined(BCM_56670_B0) 1109 { /* SOC_FORMAT_INT_MMU_COEFC_INDEX_BCM56670_B0fmt */ 1110 /* format MMU_COEFC_INDEXfmt */ 1111 /* nFields */ 3, 1112 /* *fields */ soc_MMU_COEFC_INDEX_BCM56670_A0fmt_fields, 1113 /* bits */ 14, 1114 /* flags */ 0, 1115 }, 1116 #endif /* chips */ 1117 1118 #if defined(BCM_56504_A0) 1119 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATHfmt */ 1120 /* format MMU_CPATH_TO_DPATHfmt */ 1121 /* nFields */ 52, 1122 /* *fields */ soc_MMU_CPATH_TO_DPATHfmt_fields, 1123 /* bits */ 427, 1124 /* flags */ 0, 1125 }, 1126 #endif /* chips */ 1127 1128 #if defined(BCM_53314_A0) 1129 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM53314_A0fmt */ 1130 /* format MMU_CPATH_TO_DPATHfmt */ 1131 /* nFields */ 54, 1132 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM53314_A0fmt_fields, 1133 /* bits */ 425, 1134 /* flags */ 0, 1135 }, 1136 #endif /* chips */ 1137 1138 #if defined(BCM_53324_A0) 1139 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM53324_A0fmt */ 1140 /* format MMU_CPATH_TO_DPATHfmt */ 1141 /* nFields */ 54, 1142 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM53314_A0fmt_fields, 1143 /* bits */ 425, 1144 /* flags */ 0, 1145 }, 1146 #endif /* chips */ 1147 1148 #if defined(BCM_56142_A0) 1149 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56142_A0fmt */ 1150 /* format MMU_CPATH_TO_DPATHfmt */ 1151 /* nFields */ 74, 1152 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56142_A0fmt_fields, 1153 /* bits */ 642, 1154 /* flags */ 0, 1155 }, 1156 #endif /* chips */ 1157 1158 #if defined(BCM_56150_A0) 1159 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56150_A0fmt */ 1160 /* format MMU_CPATH_TO_DPATHfmt */ 1161 /* nFields */ 75, 1162 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56150_A0fmt_fields, 1163 /* bits */ 659, 1164 /* flags */ 0, 1165 }, 1166 #endif /* chips */ 1167 1168 #if defined(BCM_56224_A0) 1169 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56224_A0fmt */ 1170 /* format MMU_CPATH_TO_DPATHfmt */ 1171 /* nFields */ 61, 1172 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56224_A0fmt_fields, 1173 /* bits */ 549, 1174 /* flags */ 0, 1175 }, 1176 #endif /* chips */ 1177 1178 #if defined(BCM_56224_B0) 1179 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56224_B0fmt */ 1180 /* format MMU_CPATH_TO_DPATHfmt */ 1181 /* nFields */ 61, 1182 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56224_A0fmt_fields, 1183 /* bits */ 549, 1184 /* flags */ 0, 1185 }, 1186 #endif /* chips */ 1187 1188 #if defined(BCM_56314_A0) 1189 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56314_A0fmt */ 1190 /* format MMU_CPATH_TO_DPATHfmt */ 1191 /* nFields */ 52, 1192 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56504_B0fmt_fields, 1193 /* bits */ 438, 1194 /* flags */ 0, 1195 }, 1196 #endif /* chips */ 1197 1198 #if defined(BCM_56504_B0) 1199 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56504_B0fmt */ 1200 /* format MMU_CPATH_TO_DPATHfmt */ 1201 /* nFields */ 52, 1202 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56504_B0fmt_fields, 1203 /* bits */ 438, 1204 /* flags */ 0, 1205 }, 1206 #endif /* chips */ 1207 1208 #if defined(BCM_56514_A0) 1209 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56514_A0fmt */ 1210 /* format MMU_CPATH_TO_DPATHfmt */ 1211 /* nFields */ 54, 1212 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56514_A0fmt_fields, 1213 /* bits */ 455, 1214 /* flags */ 0, 1215 }, 1216 #endif /* chips */ 1217 1218 #if defined(BCM_56800_A0) 1219 { /* SOC_FORMAT_INT_MMU_CPATH_TO_DPATH_BCM56800_A0fmt */ 1220 /* format MMU_CPATH_TO_DPATHfmt */ 1221 /* nFields */ 53, 1222 /* *fields */ soc_MMU_CPATH_TO_DPATH_BCM56800_A0fmt_fields, 1223 /* bits */ 455, 1224 /* flags */ 0, 1225 }, 1226 #endif /* chips */ 1227 1228 #if defined(BCM_56504_A0) || defined(BCM_56800_A0) 1229 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADERfmt */ 1230 /* format MMU_CPUCRRUHEADERfmt */ 1231 /* nFields */ 3, 1232 /* *fields */ soc_MMU_CPUCRRUHEADERfmt_fields, 1233 /* bits */ 95, 1234 /* flags */ 0, 1235 }, 1236 #endif /* chips */ 1237 1238 #if defined(BCM_53314_A0) 1239 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM53314_A0fmt */ 1240 /* format MMU_CPUCRRUHEADERfmt */ 1241 /* nFields */ 3, 1242 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53314_A0fmt_fields, 1243 /* bits */ 96, 1244 /* flags */ 0, 1245 }, 1246 #endif /* chips */ 1247 1248 #if defined(BCM_53324_A0) 1249 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM53324_A0fmt */ 1250 /* format MMU_CPUCRRUHEADERfmt */ 1251 /* nFields */ 3, 1252 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53314_A0fmt_fields, 1253 /* bits */ 96, 1254 /* flags */ 0, 1255 }, 1256 #endif /* chips */ 1257 1258 #if defined(BCM_53400_A0) 1259 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM53400_A0fmt */ 1260 /* format MMU_CPUCRRUHEADERfmt */ 1261 /* nFields */ 3, 1262 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53400_A0fmt_fields, 1263 /* bits */ 62, 1264 /* flags */ 0, 1265 }, 1266 #endif /* chips */ 1267 1268 #if defined(BCM_53540_A0) 1269 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM53540_A0fmt */ 1270 /* format MMU_CPUCRRUHEADERfmt */ 1271 /* nFields */ 3, 1272 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53400_A0fmt_fields, 1273 /* bits */ 62, 1274 /* flags */ 0, 1275 }, 1276 #endif /* chips */ 1277 1278 #if defined(BCM_53570_A0) 1279 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM53570_A0fmt */ 1280 /* format MMU_CPUCRRUHEADERfmt */ 1281 /* nFields */ 3, 1282 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53570_A0fmt_fields, 1283 /* bits */ 71, 1284 /* flags */ 0, 1285 }, 1286 #endif /* chips */ 1287 1288 #if defined(BCM_53570_B0) 1289 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM53570_B0fmt */ 1290 /* format MMU_CPUCRRUHEADERfmt */ 1291 /* nFields */ 3, 1292 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53570_A0fmt_fields, 1293 /* bits */ 71, 1294 /* flags */ 0, 1295 }, 1296 #endif /* chips */ 1297 1298 #if defined(BCM_56142_A0) 1299 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56142_A0fmt */ 1300 /* format MMU_CPUCRRUHEADERfmt */ 1301 /* nFields */ 3, 1302 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56142_A0fmt_fields, 1303 /* bits */ 62, 1304 /* flags */ 0, 1305 }, 1306 #endif /* chips */ 1307 1308 #if defined(BCM_56150_A0) 1309 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56150_A0fmt */ 1310 /* format MMU_CPUCRRUHEADERfmt */ 1311 /* nFields */ 3, 1312 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56150_A0fmt_fields, 1313 /* bits */ 62, 1314 /* flags */ 0, 1315 }, 1316 #endif /* chips */ 1317 1318 #if defined(BCM_56160_A0) 1319 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56160_A0fmt */ 1320 /* format MMU_CPUCRRUHEADERfmt */ 1321 /* nFields */ 3, 1322 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53400_A0fmt_fields, 1323 /* bits */ 62, 1324 /* flags */ 0, 1325 }, 1326 #endif /* chips */ 1327 1328 #if defined(BCM_56224_A0) 1329 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56224_A0fmt */ 1330 /* format MMU_CPUCRRUHEADERfmt */ 1331 /* nFields */ 3, 1332 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56224_A0fmt_fields, 1333 /* bits */ 96, 1334 /* flags */ 0, 1335 }, 1336 #endif /* chips */ 1337 1338 #if defined(BCM_56224_B0) 1339 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56224_B0fmt */ 1340 /* format MMU_CPUCRRUHEADERfmt */ 1341 /* nFields */ 3, 1342 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56224_A0fmt_fields, 1343 /* bits */ 96, 1344 /* flags */ 0, 1345 }, 1346 #endif /* chips */ 1347 1348 #if defined(BCM_56314_A0) 1349 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56314_A0fmt */ 1350 /* format MMU_CPUCRRUHEADERfmt */ 1351 /* nFields */ 3, 1352 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1353 /* bits */ 39, 1354 /* flags */ 0, 1355 }, 1356 #endif /* chips */ 1357 1358 #if defined(BCM_56504_B0) 1359 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56504_B0fmt */ 1360 /* format MMU_CPUCRRUHEADERfmt */ 1361 /* nFields */ 3, 1362 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1363 /* bits */ 39, 1364 /* flags */ 0, 1365 }, 1366 #endif /* chips */ 1367 1368 #if defined(BCM_56514_A0) 1369 { /* SOC_FORMAT_INT_MMU_CPUCRRUHEADER_BCM56514_A0fmt */ 1370 /* format MMU_CPUCRRUHEADERfmt */ 1371 /* nFields */ 3, 1372 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1373 /* bits */ 39, 1374 /* flags */ 0, 1375 }, 1376 #endif /* chips */ 1377 1378 #if defined(BCM_56504_A0) || defined(BCM_56800_A0) 1379 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADERfmt */ 1380 /* format MMU_CPUHGCRRUHEADERfmt */ 1381 /* nFields */ 6, 1382 /* *fields */ soc_MMU_CPUHGCRRUHEADERfmt_fields, 1383 /* bits */ 56, 1384 /* flags */ 0, 1385 }, 1386 #endif /* chips */ 1387 1388 #if defined(BCM_53314_A0) 1389 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM53314_A0fmt */ 1390 /* format MMU_CPUHGCRRUHEADERfmt */ 1391 /* nFields */ 6, 1392 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56224_A0fmt_fields, 1393 /* bits */ 61, 1394 /* flags */ 0, 1395 }, 1396 #endif /* chips */ 1397 1398 #if defined(BCM_53324_A0) 1399 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM53324_A0fmt */ 1400 /* format MMU_CPUHGCRRUHEADERfmt */ 1401 /* nFields */ 6, 1402 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56224_A0fmt_fields, 1403 /* bits */ 61, 1404 /* flags */ 0, 1405 }, 1406 #endif /* chips */ 1407 1408 #if defined(BCM_53400_A0) 1409 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt */ 1410 /* format MMU_CPUHGCRRUHEADERfmt */ 1411 /* nFields */ 2, 1412 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1413 /* bits */ 24, 1414 /* flags */ 0, 1415 }, 1416 #endif /* chips */ 1417 1418 #if defined(BCM_53540_A0) 1419 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM53540_A0fmt */ 1420 /* format MMU_CPUHGCRRUHEADERfmt */ 1421 /* nFields */ 2, 1422 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1423 /* bits */ 24, 1424 /* flags */ 0, 1425 }, 1426 #endif /* chips */ 1427 1428 #if defined(BCM_56142_A0) 1429 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56142_A0fmt */ 1430 /* format MMU_CPUHGCRRUHEADERfmt */ 1431 /* nFields */ 2, 1432 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56142_A0fmt_fields, 1433 /* bits */ 24, 1434 /* flags */ 0, 1435 }, 1436 #endif /* chips */ 1437 1438 #if defined(BCM_56150_A0) 1439 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56150_A0fmt */ 1440 /* format MMU_CPUHGCRRUHEADERfmt */ 1441 /* nFields */ 2, 1442 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56150_A0fmt_fields, 1443 /* bits */ 24, 1444 /* flags */ 0, 1445 }, 1446 #endif /* chips */ 1447 1448 #if defined(BCM_56160_A0) 1449 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56160_A0fmt */ 1450 /* format MMU_CPUHGCRRUHEADERfmt */ 1451 /* nFields */ 2, 1452 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1453 /* bits */ 24, 1454 /* flags */ 0, 1455 }, 1456 #endif /* chips */ 1457 1458 #if defined(BCM_56224_A0) 1459 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56224_A0fmt */ 1460 /* format MMU_CPUHGCRRUHEADERfmt */ 1461 /* nFields */ 6, 1462 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56224_A0fmt_fields, 1463 /* bits */ 61, 1464 /* flags */ 0, 1465 }, 1466 #endif /* chips */ 1467 1468 #if defined(BCM_56224_B0) 1469 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56224_B0fmt */ 1470 /* format MMU_CPUHGCRRUHEADERfmt */ 1471 /* nFields */ 6, 1472 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56224_A0fmt_fields, 1473 /* bits */ 61, 1474 /* flags */ 0, 1475 }, 1476 #endif /* chips */ 1477 1478 #if defined(BCM_56314_A0) 1479 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56314_A0fmt */ 1480 /* format MMU_CPUHGCRRUHEADERfmt */ 1481 /* nFields */ 4, 1482 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1483 /* bits */ 23, 1484 /* flags */ 0, 1485 }, 1486 #endif /* chips */ 1487 1488 #if defined(BCM_56504_B0) 1489 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt */ 1490 /* format MMU_CPUHGCRRUHEADERfmt */ 1491 /* nFields */ 4, 1492 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1493 /* bits */ 23, 1494 /* flags */ 0, 1495 }, 1496 #endif /* chips */ 1497 1498 #if defined(BCM_56514_A0) 1499 { /* SOC_FORMAT_INT_MMU_CPUHGCRRUHEADER_BCM56514_A0fmt */ 1500 /* format MMU_CPUHGCRRUHEADERfmt */ 1501 /* nFields */ 4, 1502 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1503 /* bits */ 23, 1504 /* flags */ 0, 1505 }, 1506 #endif /* chips */ 1507 1508 #if defined(BCM_56504_A0) || defined(BCM_56800_A0) 1509 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADERfmt */ 1510 /* format MMU_CPUHGPPPHEADERfmt */ 1511 /* nFields */ 6, 1512 /* *fields */ soc_MMU_CPUHGPPPHEADERfmt_fields, 1513 /* bits */ 51, 1514 /* flags */ 0, 1515 }, 1516 #endif /* chips */ 1517 1518 #if defined(BCM_53314_A0) 1519 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADER_BCM53314_A0fmt */ 1520 /* format MMU_CPUHGPPPHEADERfmt */ 1521 /* nFields */ 6, 1522 /* *fields */ soc_MMU_CPUHGPPPHEADER_BCM56224_A0fmt_fields, 1523 /* bits */ 51, 1524 /* flags */ 0, 1525 }, 1526 #endif /* chips */ 1527 1528 #if defined(BCM_53324_A0) 1529 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADER_BCM53324_A0fmt */ 1530 /* format MMU_CPUHGPPPHEADERfmt */ 1531 /* nFields */ 6, 1532 /* *fields */ soc_MMU_CPUHGPPPHEADER_BCM56224_A0fmt_fields, 1533 /* bits */ 51, 1534 /* flags */ 0, 1535 }, 1536 #endif /* chips */ 1537 1538 #if defined(BCM_56224_A0) 1539 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADER_BCM56224_A0fmt */ 1540 /* format MMU_CPUHGPPPHEADERfmt */ 1541 /* nFields */ 6, 1542 /* *fields */ soc_MMU_CPUHGPPPHEADER_BCM56224_A0fmt_fields, 1543 /* bits */ 51, 1544 /* flags */ 0, 1545 }, 1546 #endif /* chips */ 1547 1548 #if defined(BCM_56224_B0) 1549 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADER_BCM56224_B0fmt */ 1550 /* format MMU_CPUHGPPPHEADERfmt */ 1551 /* nFields */ 6, 1552 /* *fields */ soc_MMU_CPUHGPPPHEADER_BCM56224_A0fmt_fields, 1553 /* bits */ 51, 1554 /* flags */ 0, 1555 }, 1556 #endif /* chips */ 1557 1558 #if defined(BCM_56314_A0) 1559 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADER_BCM56314_A0fmt */ 1560 /* format MMU_CPUHGPPPHEADERfmt */ 1561 /* nFields */ 4, 1562 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1563 /* bits */ 23, 1564 /* flags */ 0, 1565 }, 1566 #endif /* chips */ 1567 1568 #if defined(BCM_56504_B0) 1569 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADER_BCM56504_B0fmt */ 1570 /* format MMU_CPUHGPPPHEADERfmt */ 1571 /* nFields */ 4, 1572 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1573 /* bits */ 23, 1574 /* flags */ 0, 1575 }, 1576 #endif /* chips */ 1577 1578 #if defined(BCM_56514_A0) 1579 { /* SOC_FORMAT_INT_MMU_CPUHGPPPHEADER_BCM56514_A0fmt */ 1580 /* format MMU_CPUHGPPPHEADERfmt */ 1581 /* nFields */ 4, 1582 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1583 /* bits */ 23, 1584 /* flags */ 0, 1585 }, 1586 #endif /* chips */ 1587 1588 #if defined(BCM_56504_A0) || defined(BCM_56800_A0) 1589 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADERfmt */ 1590 /* format MMU_CPUHGXQHEADERfmt */ 1591 /* nFields */ 6, 1592 /* *fields */ soc_MMU_CPUHGXQHEADERfmt_fields, 1593 /* bits */ 48, 1594 /* flags */ 0, 1595 }, 1596 #endif /* chips */ 1597 1598 #if defined(BCM_53314_A0) 1599 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM53314_A0fmt */ 1600 /* format MMU_CPUHGXQHEADERfmt */ 1601 /* nFields */ 6, 1602 /* *fields */ soc_MMU_CPUHGXQHEADER_BCM56224_A0fmt_fields, 1603 /* bits */ 53, 1604 /* flags */ 0, 1605 }, 1606 #endif /* chips */ 1607 1608 #if defined(BCM_53324_A0) 1609 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM53324_A0fmt */ 1610 /* format MMU_CPUHGXQHEADERfmt */ 1611 /* nFields */ 6, 1612 /* *fields */ soc_MMU_CPUHGXQHEADER_BCM56224_A0fmt_fields, 1613 /* bits */ 53, 1614 /* flags */ 0, 1615 }, 1616 #endif /* chips */ 1617 1618 #if defined(BCM_53400_A0) 1619 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM53400_A0fmt */ 1620 /* format MMU_CPUHGXQHEADERfmt */ 1621 /* nFields */ 2, 1622 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1623 /* bits */ 24, 1624 /* flags */ 0, 1625 }, 1626 #endif /* chips */ 1627 1628 #if defined(BCM_53540_A0) 1629 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM53540_A0fmt */ 1630 /* format MMU_CPUHGXQHEADERfmt */ 1631 /* nFields */ 2, 1632 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1633 /* bits */ 24, 1634 /* flags */ 0, 1635 }, 1636 #endif /* chips */ 1637 1638 #if defined(BCM_53570_A0) 1639 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM53570_A0fmt */ 1640 /* format MMU_CPUHGXQHEADERfmt */ 1641 /* nFields */ 2, 1642 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1643 /* bits */ 24, 1644 /* flags */ 0, 1645 }, 1646 #endif /* chips */ 1647 1648 #if defined(BCM_53570_B0) 1649 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM53570_B0fmt */ 1650 /* format MMU_CPUHGXQHEADERfmt */ 1651 /* nFields */ 2, 1652 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1653 /* bits */ 24, 1654 /* flags */ 0, 1655 }, 1656 #endif /* chips */ 1657 1658 #if defined(BCM_56142_A0) 1659 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56142_A0fmt */ 1660 /* format MMU_CPUHGXQHEADERfmt */ 1661 /* nFields */ 2, 1662 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56142_A0fmt_fields, 1663 /* bits */ 24, 1664 /* flags */ 0, 1665 }, 1666 #endif /* chips */ 1667 1668 #if defined(BCM_56150_A0) 1669 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56150_A0fmt */ 1670 /* format MMU_CPUHGXQHEADERfmt */ 1671 /* nFields */ 2, 1672 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56150_A0fmt_fields, 1673 /* bits */ 24, 1674 /* flags */ 0, 1675 }, 1676 #endif /* chips */ 1677 1678 #if defined(BCM_56160_A0) 1679 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56160_A0fmt */ 1680 /* format MMU_CPUHGXQHEADERfmt */ 1681 /* nFields */ 2, 1682 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM53400_A0fmt_fields, 1683 /* bits */ 24, 1684 /* flags */ 0, 1685 }, 1686 #endif /* chips */ 1687 1688 #if defined(BCM_56224_A0) 1689 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56224_A0fmt */ 1690 /* format MMU_CPUHGXQHEADERfmt */ 1691 /* nFields */ 6, 1692 /* *fields */ soc_MMU_CPUHGXQHEADER_BCM56224_A0fmt_fields, 1693 /* bits */ 53, 1694 /* flags */ 0, 1695 }, 1696 #endif /* chips */ 1697 1698 #if defined(BCM_56224_B0) 1699 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56224_B0fmt */ 1700 /* format MMU_CPUHGXQHEADERfmt */ 1701 /* nFields */ 6, 1702 /* *fields */ soc_MMU_CPUHGXQHEADER_BCM56224_A0fmt_fields, 1703 /* bits */ 53, 1704 /* flags */ 0, 1705 }, 1706 #endif /* chips */ 1707 1708 #if defined(BCM_56314_A0) 1709 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56314_A0fmt */ 1710 /* format MMU_CPUHGXQHEADERfmt */ 1711 /* nFields */ 4, 1712 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1713 /* bits */ 23, 1714 /* flags */ 0, 1715 }, 1716 #endif /* chips */ 1717 1718 #if defined(BCM_56504_B0) 1719 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56504_B0fmt */ 1720 /* format MMU_CPUHGXQHEADERfmt */ 1721 /* nFields */ 4, 1722 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1723 /* bits */ 23, 1724 /* flags */ 0, 1725 }, 1726 #endif /* chips */ 1727 1728 #if defined(BCM_56514_A0) 1729 { /* SOC_FORMAT_INT_MMU_CPUHGXQHEADER_BCM56514_A0fmt */ 1730 /* format MMU_CPUHGXQHEADERfmt */ 1731 /* nFields */ 4, 1732 /* *fields */ soc_MMU_CPUHGCRRUHEADER_BCM56504_B0fmt_fields, 1733 /* bits */ 23, 1734 /* flags */ 0, 1735 }, 1736 #endif /* chips */ 1737 1738 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1739 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1740 defined(BCM_56504_A0) || defined(BCM_56800_A0) 1741 { /* SOC_FORMAT_INT_MMU_CPUPPPHEADERfmt */ 1742 /* format MMU_CPUPPPHEADERfmt */ 1743 /* nFields */ 3, 1744 /* *fields */ soc_MMU_CPUPPPHEADERfmt_fields, 1745 /* bits */ 90, 1746 /* flags */ 0, 1747 }, 1748 #endif /* chips */ 1749 1750 #if defined(BCM_56314_A0) 1751 { /* SOC_FORMAT_INT_MMU_CPUPPPHEADER_BCM56314_A0fmt */ 1752 /* format MMU_CPUPPPHEADERfmt */ 1753 /* nFields */ 3, 1754 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1755 /* bits */ 39, 1756 /* flags */ 0, 1757 }, 1758 #endif /* chips */ 1759 1760 #if defined(BCM_56504_B0) 1761 { /* SOC_FORMAT_INT_MMU_CPUPPPHEADER_BCM56504_B0fmt */ 1762 /* format MMU_CPUPPPHEADERfmt */ 1763 /* nFields */ 3, 1764 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1765 /* bits */ 39, 1766 /* flags */ 0, 1767 }, 1768 #endif /* chips */ 1769 1770 #if defined(BCM_56514_A0) 1771 { /* SOC_FORMAT_INT_MMU_CPUPPPHEADER_BCM56514_A0fmt */ 1772 /* format MMU_CPUPPPHEADERfmt */ 1773 /* nFields */ 3, 1774 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1775 /* bits */ 39, 1776 /* flags */ 0, 1777 }, 1778 #endif /* chips */ 1779 1780 #if defined(BCM_56504_A0) || defined(BCM_56800_A0) 1781 { /* SOC_FORMAT_INT_MMU_CPUXQHEADERfmt */ 1782 /* format MMU_CPUXQHEADERfmt */ 1783 /* nFields */ 4, 1784 /* *fields */ soc_MMU_CPUXQHEADERfmt_fields, 1785 /* bits */ 88, 1786 /* flags */ 0, 1787 }, 1788 #endif /* chips */ 1789 1790 #if defined(BCM_53314_A0) 1791 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM53314_A0fmt */ 1792 /* format MMU_CPUXQHEADERfmt */ 1793 /* nFields */ 3, 1794 /* *fields */ soc_MMU_CPUXQHEADER_BCM53314_A0fmt_fields, 1795 /* bits */ 95, 1796 /* flags */ 0, 1797 }, 1798 #endif /* chips */ 1799 1800 #if defined(BCM_53324_A0) 1801 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM53324_A0fmt */ 1802 /* format MMU_CPUXQHEADERfmt */ 1803 /* nFields */ 3, 1804 /* *fields */ soc_MMU_CPUXQHEADER_BCM53314_A0fmt_fields, 1805 /* bits */ 95, 1806 /* flags */ 0, 1807 }, 1808 #endif /* chips */ 1809 1810 #if defined(BCM_53400_A0) 1811 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM53400_A0fmt */ 1812 /* format MMU_CPUXQHEADERfmt */ 1813 /* nFields */ 3, 1814 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53400_A0fmt_fields, 1815 /* bits */ 62, 1816 /* flags */ 0, 1817 }, 1818 #endif /* chips */ 1819 1820 #if defined(BCM_53540_A0) 1821 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM53540_A0fmt */ 1822 /* format MMU_CPUXQHEADERfmt */ 1823 /* nFields */ 3, 1824 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53400_A0fmt_fields, 1825 /* bits */ 62, 1826 /* flags */ 0, 1827 }, 1828 #endif /* chips */ 1829 1830 #if defined(BCM_53570_A0) 1831 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM53570_A0fmt */ 1832 /* format MMU_CPUXQHEADERfmt */ 1833 /* nFields */ 3, 1834 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53570_A0fmt_fields, 1835 /* bits */ 71, 1836 /* flags */ 0, 1837 }, 1838 #endif /* chips */ 1839 1840 #if defined(BCM_53570_B0) 1841 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM53570_B0fmt */ 1842 /* format MMU_CPUXQHEADERfmt */ 1843 /* nFields */ 3, 1844 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53570_A0fmt_fields, 1845 /* bits */ 71, 1846 /* flags */ 0, 1847 }, 1848 #endif /* chips */ 1849 1850 #if defined(BCM_56142_A0) 1851 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56142_A0fmt */ 1852 /* format MMU_CPUXQHEADERfmt */ 1853 /* nFields */ 3, 1854 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56142_A0fmt_fields, 1855 /* bits */ 62, 1856 /* flags */ 0, 1857 }, 1858 #endif /* chips */ 1859 1860 #if defined(BCM_56150_A0) 1861 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56150_A0fmt */ 1862 /* format MMU_CPUXQHEADERfmt */ 1863 /* nFields */ 3, 1864 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56150_A0fmt_fields, 1865 /* bits */ 62, 1866 /* flags */ 0, 1867 }, 1868 #endif /* chips */ 1869 1870 #if defined(BCM_56160_A0) 1871 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56160_A0fmt */ 1872 /* format MMU_CPUXQHEADERfmt */ 1873 /* nFields */ 3, 1874 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM53400_A0fmt_fields, 1875 /* bits */ 62, 1876 /* flags */ 0, 1877 }, 1878 #endif /* chips */ 1879 1880 #if defined(BCM_56224_A0) 1881 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56224_A0fmt */ 1882 /* format MMU_CPUXQHEADERfmt */ 1883 /* nFields */ 3, 1884 /* *fields */ soc_MMU_CPUXQHEADER_BCM56224_A0fmt_fields, 1885 /* bits */ 93, 1886 /* flags */ 0, 1887 }, 1888 #endif /* chips */ 1889 1890 #if defined(BCM_56224_B0) 1891 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56224_B0fmt */ 1892 /* format MMU_CPUXQHEADERfmt */ 1893 /* nFields */ 3, 1894 /* *fields */ soc_MMU_CPUXQHEADER_BCM56224_A0fmt_fields, 1895 /* bits */ 93, 1896 /* flags */ 0, 1897 }, 1898 #endif /* chips */ 1899 1900 #if defined(BCM_56314_A0) 1901 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56314_A0fmt */ 1902 /* format MMU_CPUXQHEADERfmt */ 1903 /* nFields */ 3, 1904 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1905 /* bits */ 39, 1906 /* flags */ 0, 1907 }, 1908 #endif /* chips */ 1909 1910 #if defined(BCM_56504_B0) 1911 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56504_B0fmt */ 1912 /* format MMU_CPUXQHEADERfmt */ 1913 /* nFields */ 3, 1914 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1915 /* bits */ 39, 1916 /* flags */ 0, 1917 }, 1918 #endif /* chips */ 1919 1920 #if defined(BCM_56514_A0) 1921 { /* SOC_FORMAT_INT_MMU_CPUXQHEADER_BCM56514_A0fmt */ 1922 /* format MMU_CPUXQHEADERfmt */ 1923 /* nFields */ 3, 1924 /* *fields */ soc_MMU_CPUCRRUHEADER_BCM56504_B0fmt_fields, 1925 /* bits */ 39, 1926 /* flags */ 0, 1927 }, 1928 #endif /* chips */ 1929 1930 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1931 { /* SOC_FORMAT_INT_MMU_CRB_TO_CFAP_ENQ_INFOfmt */ 1932 /* format MMU_CRB_TO_CFAP_ENQ_INFOfmt */ 1933 /* nFields */ 3, 1934 /* *fields */ soc_MMU_CRB_TO_CFAP_ENQ_INFOfmt_fields, 1935 /* bits */ 7, 1936 /* flags */ 0, 1937 }, 1938 #endif /* chips */ 1939 1940 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1941 { /* SOC_FORMAT_INT_MMU_CRB_TO_EBCTM_ENQ_CT_REQ_INFOfmt */ 1942 /* format MMU_CRB_TO_EBCTM_ENQ_CT_REQ_INFOfmt */ 1943 /* nFields */ 9, 1944 /* *fields */ soc_MMU_CRB_TO_EBCTM_ENQ_CT_REQ_INFOfmt_fields, 1945 /* bits */ 24, 1946 /* flags */ 0, 1947 }, 1948 #endif /* chips */ 1949 1950 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1951 { /* SOC_FORMAT_INT_MMU_CRB_TO_EBCTM_RQE_CT_REQ_INFOfmt */ 1952 /* format MMU_CRB_TO_EBCTM_RQE_CT_REQ_INFOfmt */ 1953 /* nFields */ 5, 1954 /* *fields */ soc_MMU_CRB_TO_EBCTM_RQE_CT_REQ_INFOfmt_fields, 1955 /* bits */ 11, 1956 /* flags */ 0, 1957 }, 1958 #endif /* chips */ 1959 1960 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1961 { /* SOC_FORMAT_INT_MMU_CRB_TO_RL_ENQ_CT_CELL_INFOfmt */ 1962 /* format MMU_CRB_TO_RL_ENQ_CT_CELL_INFOfmt */ 1963 /* nFields */ 9, 1964 /* *fields */ soc_MMU_CRB_TO_RL_ENQ_CT_CELL_INFOfmt_fields, 1965 /* bits */ 50, 1966 /* flags */ 0, 1967 }, 1968 #endif /* chips */ 1969 1970 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1971 { /* SOC_FORMAT_INT_MMU_CRB_TO_RL_MULTI_COPY_INFOfmt */ 1972 /* format MMU_CRB_TO_RL_MULTI_COPY_INFOfmt */ 1973 /* nFields */ 2, 1974 /* *fields */ soc_MMU_CRB_TO_RL_MULTI_COPY_INFOfmt_fields, 1975 /* bits */ 2, 1976 /* flags */ 0, 1977 }, 1978 #endif /* chips */ 1979 1980 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1981 { /* SOC_FORMAT_INT_MMU_CRB_TO_RQE_PKTHDR_INFOfmt */ 1982 /* format MMU_CRB_TO_RQE_PKTHDR_INFOfmt */ 1983 /* nFields */ 16, 1984 /* *fields */ soc_MMU_CRB_TO_RQE_PKTHDR_INFOfmt_fields, 1985 /* bits */ 386, 1986 /* flags */ 0, 1987 }, 1988 #endif /* chips */ 1989 1990 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1991 { /* SOC_FORMAT_INT_MMU_CRB_TO_SCB_IP_INFOfmt */ 1992 /* format MMU_CRB_TO_SCB_IP_INFOfmt */ 1993 /* nFields */ 28, 1994 /* *fields */ soc_MMU_CRB_TO_SCB_IP_INFOfmt_fields, 1995 /* bits */ 109, 1996 /* flags */ 0, 1997 }, 1998 #endif /* chips */ 1999 2000 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2001 { /* SOC_FORMAT_INT_MMU_CRB_TO_SCB_RQE_CELL_INFOfmt */ 2002 /* format MMU_CRB_TO_SCB_RQE_CELL_INFOfmt */ 2003 /* nFields */ 1, 2004 /* *fields */ soc_MMU_CRB_TO_SCB_RQE_CELL_INFOfmt_fields, 2005 /* bits */ 23, 2006 /* flags */ 0, 2007 }, 2008 #endif /* chips */ 2009 2010 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2011 { /* SOC_FORMAT_INT_MMU_CRB_TO_SCB_RQE_PKT_INFOfmt */ 2012 /* format MMU_CRB_TO_SCB_RQE_PKT_INFOfmt */ 2013 /* nFields */ 21, 2014 /* *fields */ soc_MMU_CRB_TO_SCB_RQE_PKT_INFOfmt_fields, 2015 /* bits */ 75, 2016 /* flags */ 0, 2017 }, 2018 #endif /* chips */ 2019 2020 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2021 { /* SOC_FORMAT_INT_MMU_CRB_TO_THDI_ENQ_INFOfmt */ 2022 /* format MMU_CRB_TO_THDI_ENQ_INFOfmt */ 2023 /* nFields */ 16, 2024 /* *fields */ soc_MMU_CRB_TO_THDI_ENQ_INFOfmt_fields, 2025 /* bits */ 26, 2026 /* flags */ 0, 2027 }, 2028 #endif /* chips */ 2029 2030 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2031 { /* SOC_FORMAT_INT_MMU_CRB_TO_THDR_ENQ_CELL_INFOfmt */ 2032 /* format MMU_CRB_TO_THDR_ENQ_CELL_INFOfmt */ 2033 /* nFields */ 10, 2034 /* *fields */ soc_MMU_CRB_TO_THDR_ENQ_CELL_INFOfmt_fields, 2035 /* bits */ 42, 2036 /* flags */ 0, 2037 }, 2038 #endif /* chips */ 2039 2040 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 2041 defined(BCM_56504_B0) || defined(BCM_56514_A0) || \ 2042 defined(BCM_56800_A0) 2043 { /* SOC_FORMAT_INT_MMU_CRRUHEADERfmt */ 2044 /* format MMU_CRRUHEADERfmt */ 2045 /* nFields */ 10, 2046 /* *fields */ soc_MMU_CRRUHEADERfmt_fields, 2047 /* bits */ 29, 2048 /* flags */ 0, 2049 }, 2050 #endif /* chips */ 2051 2052 #if defined(BCM_53314_A0) 2053 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM53314_A0fmt */ 2054 /* format MMU_CRRUHEADERfmt */ 2055 /* nFields */ 10, 2056 /* *fields */ soc_MMU_CRRUHEADER_BCM53314_A0fmt_fields, 2057 /* bits */ 28, 2058 /* flags */ 0, 2059 }, 2060 #endif /* chips */ 2061 2062 #if defined(BCM_53324_A0) 2063 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM53324_A0fmt */ 2064 /* format MMU_CRRUHEADERfmt */ 2065 /* nFields */ 10, 2066 /* *fields */ soc_MMU_CRRUHEADER_BCM53314_A0fmt_fields, 2067 /* bits */ 28, 2068 /* flags */ 0, 2069 }, 2070 #endif /* chips */ 2071 2072 #if defined(BCM_53400_A0) 2073 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM53400_A0fmt */ 2074 /* format MMU_CRRUHEADERfmt */ 2075 /* nFields */ 10, 2076 /* *fields */ soc_MMU_CRRUHEADER_BCM53400_A0fmt_fields, 2077 /* bits */ 30, 2078 /* flags */ 0, 2079 }, 2080 #endif /* chips */ 2081 2082 #if defined(BCM_53540_A0) 2083 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM53540_A0fmt */ 2084 /* format MMU_CRRUHEADERfmt */ 2085 /* nFields */ 10, 2086 /* *fields */ soc_MMU_CRRUHEADER_BCM53540_A0fmt_fields, 2087 /* bits */ 28, 2088 /* flags */ 0, 2089 }, 2090 #endif /* chips */ 2091 2092 #if defined(BCM_53570_A0) 2093 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM53570_A0fmt */ 2094 /* format MMU_CRRUHEADERfmt */ 2095 /* nFields */ 13, 2096 /* *fields */ soc_MMU_CRRUHEADER_BCM53570_A0fmt_fields, 2097 /* bits */ 36, 2098 /* flags */ 0, 2099 }, 2100 #endif /* chips */ 2101 2102 #if defined(BCM_53570_B0) 2103 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM53570_B0fmt */ 2104 /* format MMU_CRRUHEADERfmt */ 2105 /* nFields */ 13, 2106 /* *fields */ soc_MMU_CRRUHEADER_BCM53570_A0fmt_fields, 2107 /* bits */ 36, 2108 /* flags */ 0, 2109 }, 2110 #endif /* chips */ 2111 2112 #if defined(BCM_56142_A0) 2113 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM56142_A0fmt */ 2114 /* format MMU_CRRUHEADERfmt */ 2115 /* nFields */ 10, 2116 /* *fields */ soc_MMU_CRRUHEADER_BCM56224_A0fmt_fields, 2117 /* bits */ 30, 2118 /* flags */ 0, 2119 }, 2120 #endif /* chips */ 2121 2122 #if defined(BCM_56150_A0) 2123 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM56150_A0fmt */ 2124 /* format MMU_CRRUHEADERfmt */ 2125 /* nFields */ 10, 2126 /* *fields */ soc_MMU_CRRUHEADER_BCM56150_A0fmt_fields, 2127 /* bits */ 30, 2128 /* flags */ 0, 2129 }, 2130 #endif /* chips */ 2131 2132 #if defined(BCM_56160_A0) 2133 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM56160_A0fmt */ 2134 /* format MMU_CRRUHEADERfmt */ 2135 /* nFields */ 10, 2136 /* *fields */ soc_MMU_CRRUHEADER_BCM53400_A0fmt_fields, 2137 /* bits */ 30, 2138 /* flags */ 0, 2139 }, 2140 #endif /* chips */ 2141 2142 #if defined(BCM_56224_A0) 2143 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM56224_A0fmt */ 2144 /* format MMU_CRRUHEADERfmt */ 2145 /* nFields */ 10, 2146 /* *fields */ soc_MMU_CRRUHEADER_BCM56224_A0fmt_fields, 2147 /* bits */ 30, 2148 /* flags */ 0, 2149 }, 2150 #endif /* chips */ 2151 2152 #if defined(BCM_56224_B0) 2153 { /* SOC_FORMAT_INT_MMU_CRRUHEADER_BCM56224_B0fmt */ 2154 /* format MMU_CRRUHEADERfmt */ 2155 /* nFields */ 10, 2156 /* *fields */ soc_MMU_CRRUHEADER_BCM56224_A0fmt_fields, 2157 /* bits */ 30, 2158 /* flags */ 0, 2159 }, 2160 #endif /* chips */ 2161 2162 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2163 defined(BCM_56870_A0) || defined(BCM_56970_A0) 2164 { /* SOC_FORMAT_INT_MMU_CTR_TO_RQE_DATAfmt */ 2165 /* format MMU_CTR_TO_RQE_DATAfmt */ 2166 /* nFields */ 1, 2167 /* *fields */ soc_MMU_CTR_TO_RQE_DATAfmt_fields, 2168 /* bits */ 1, 2169 /* flags */ 0, 2170 }, 2171 #endif /* chips */ 2172 2173 #if defined(BCM_56504_A0) 2174 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATHfmt */ 2175 /* format MMU_DPATH_TO_CPATHfmt */ 2176 /* nFields */ 51, 2177 /* *fields */ soc_MMU_DPATH_TO_CPATHfmt_fields, 2178 /* bits */ 603, 2179 /* flags */ 0, 2180 }, 2181 #endif /* chips */ 2182 2183 #if defined(BCM_53314_A0) 2184 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM53314_A0fmt */ 2185 /* format MMU_DPATH_TO_CPATHfmt */ 2186 /* nFields */ 48, 2187 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM53314_A0fmt_fields, 2188 /* bits */ 538, 2189 /* flags */ 0, 2190 }, 2191 #endif /* chips */ 2192 2193 #if defined(BCM_53324_A0) 2194 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM53324_A0fmt */ 2195 /* format MMU_DPATH_TO_CPATHfmt */ 2196 /* nFields */ 48, 2197 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM53314_A0fmt_fields, 2198 /* bits */ 538, 2199 /* flags */ 0, 2200 }, 2201 #endif /* chips */ 2202 2203 #if defined(BCM_56142_A0) 2204 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56142_A0fmt */ 2205 /* format MMU_DPATH_TO_CPATHfmt */ 2206 /* nFields */ 59, 2207 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56142_A0fmt_fields, 2208 /* bits */ 668, 2209 /* flags */ 0, 2210 }, 2211 #endif /* chips */ 2212 2213 #if defined(BCM_56150_A0) 2214 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56150_A0fmt */ 2215 /* format MMU_DPATH_TO_CPATHfmt */ 2216 /* nFields */ 59, 2217 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56150_A0fmt_fields, 2218 /* bits */ 669, 2219 /* flags */ 0, 2220 }, 2221 #endif /* chips */ 2222 2223 #if defined(BCM_56224_A0) 2224 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56224_A0fmt */ 2225 /* format MMU_DPATH_TO_CPATHfmt */ 2226 /* nFields */ 58, 2227 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56224_A0fmt_fields, 2228 /* bits */ 651, 2229 /* flags */ 0, 2230 }, 2231 #endif /* chips */ 2232 2233 #if defined(BCM_56224_B0) 2234 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56224_B0fmt */ 2235 /* format MMU_DPATH_TO_CPATHfmt */ 2236 /* nFields */ 58, 2237 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56224_A0fmt_fields, 2238 /* bits */ 651, 2239 /* flags */ 0, 2240 }, 2241 #endif /* chips */ 2242 2243 #if defined(BCM_56314_A0) 2244 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56314_A0fmt */ 2245 /* format MMU_DPATH_TO_CPATHfmt */ 2246 /* nFields */ 52, 2247 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56504_B0fmt_fields, 2248 /* bits */ 616, 2249 /* flags */ 0, 2250 }, 2251 #endif /* chips */ 2252 2253 #if defined(BCM_56504_B0) 2254 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56504_B0fmt */ 2255 /* format MMU_DPATH_TO_CPATHfmt */ 2256 /* nFields */ 52, 2257 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56504_B0fmt_fields, 2258 /* bits */ 616, 2259 /* flags */ 0, 2260 }, 2261 #endif /* chips */ 2262 2263 #if defined(BCM_56514_A0) 2264 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56514_A0fmt */ 2265 /* format MMU_DPATH_TO_CPATHfmt */ 2266 /* nFields */ 50, 2267 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56514_A0fmt_fields, 2268 /* bits */ 592, 2269 /* flags */ 0, 2270 }, 2271 #endif /* chips */ 2272 2273 #if defined(BCM_56800_A0) 2274 { /* SOC_FORMAT_INT_MMU_DPATH_TO_CPATH_BCM56800_A0fmt */ 2275 /* format MMU_DPATH_TO_CPATHfmt */ 2276 /* nFields */ 51, 2277 /* *fields */ soc_MMU_DPATH_TO_CPATH_BCM56800_A0fmt_fields, 2278 /* bits */ 607, 2279 /* flags */ 0, 2280 }, 2281 #endif /* chips */ 2282 2283 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2284 { /* SOC_FORMAT_INT_MMU_EBCFP_TO_EBCR_CELL_INFOfmt */ 2285 /* format MMU_EBCFP_TO_EBCR_CELL_INFOfmt */ 2286 /* nFields */ 11, 2287 /* *fields */ soc_MMU_EBCFP_TO_EBCR_CELL_INFOfmt_fields, 2288 /* bits */ 39, 2289 /* flags */ 0, 2290 }, 2291 #endif /* chips */ 2292 2293 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2294 { /* SOC_FORMAT_INT_MMU_EBCFP_TO_EBMB_CELL_INFOfmt */ 2295 /* format MMU_EBCFP_TO_EBMB_CELL_INFOfmt */ 2296 /* nFields */ 27, 2297 /* *fields */ soc_MMU_EBCFP_TO_EBMB_CELL_INFOfmt_fields, 2298 /* bits */ 95, 2299 /* flags */ 0, 2300 }, 2301 #endif /* chips */ 2302 2303 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2304 { /* SOC_FORMAT_INT_MMU_EBCFP_TO_EBMB_DEQ_CELL_INFOfmt */ 2305 /* format MMU_EBCFP_TO_EBMB_DEQ_CELL_INFOfmt */ 2306 /* nFields */ 7, 2307 /* *fields */ soc_MMU_EBCFP_TO_EBMB_DEQ_CELL_INFOfmt_fields, 2308 /* bits */ 32, 2309 /* flags */ 0, 2310 }, 2311 #endif /* chips */ 2312 2313 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2314 { /* SOC_FORMAT_INT_MMU_EBCR_TO_EBTOQ_ENQ_CELL_INFOfmt */ 2315 /* format MMU_EBCR_TO_EBTOQ_ENQ_CELL_INFOfmt */ 2316 /* nFields */ 10, 2317 /* *fields */ soc_MMU_EBCR_TO_EBTOQ_ENQ_CELL_INFOfmt_fields, 2318 /* bits */ 31, 2319 /* flags */ 0, 2320 }, 2321 #endif /* chips */ 2322 2323 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2324 { /* SOC_FORMAT_INT_MMU_EBCTM_STG1_BUS_FORMATfmt */ 2325 /* format MMU_EBCTM_STG1_BUS_FORMATfmt */ 2326 /* nFields */ 74, 2327 /* *fields */ soc_MMU_EBCTM_STG1_BUS_FORMATfmt_fields, 2328 /* bits */ 170, 2329 /* flags */ 0, 2330 }, 2331 #endif /* chips */ 2332 2333 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2334 { /* SOC_FORMAT_INT_MMU_EBCTM_STG2_BUS_FORMATfmt */ 2335 /* format MMU_EBCTM_STG2_BUS_FORMATfmt */ 2336 /* nFields */ 85, 2337 /* *fields */ soc_MMU_EBCTM_STG2_BUS_FORMATfmt_fields, 2338 /* bits */ 183, 2339 /* flags */ 0, 2340 }, 2341 #endif /* chips */ 2342 2343 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2344 { /* SOC_FORMAT_INT_MMU_EBCTM_STG5_BUS_FORMATfmt */ 2345 /* format MMU_EBCTM_STG5_BUS_FORMATfmt */ 2346 /* nFields */ 75, 2347 /* *fields */ soc_MMU_EBCTM_STG5_BUS_FORMATfmt_fields, 2348 /* bits */ 155, 2349 /* flags */ 0, 2350 }, 2351 #endif /* chips */ 2352 2353 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2354 { /* SOC_FORMAT_INT_MMU_EBCTM_STG6_BUS_FORMATfmt */ 2355 /* format MMU_EBCTM_STG6_BUS_FORMATfmt */ 2356 /* nFields */ 19, 2357 /* *fields */ soc_MMU_EBCTM_STG6_BUS_FORMATfmt_fields, 2358 /* bits */ 19, 2359 /* flags */ 0, 2360 }, 2361 #endif /* chips */ 2362 2363 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2364 { /* SOC_FORMAT_INT_MMU_EBCTM_TO_CRB_ENQ_CT_DECISION_INFOfmt */ 2365 /* format MMU_EBCTM_TO_CRB_ENQ_CT_DECISION_INFOfmt */ 2366 /* nFields */ 3, 2367 /* *fields */ soc_MMU_EBCTM_TO_CRB_ENQ_CT_DECISION_INFOfmt_fields, 2368 /* bits */ 3, 2369 /* flags */ 0, 2370 }, 2371 #endif /* chips */ 2372 2373 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2374 { /* SOC_FORMAT_INT_MMU_EBCTM_TO_CRB_RQE_CT_DECISION_INFOfmt */ 2375 /* format MMU_EBCTM_TO_CRB_RQE_CT_DECISION_INFOfmt */ 2376 /* nFields */ 2, 2377 /* *fields */ soc_MMU_EBCTM_TO_CRB_RQE_CT_DECISION_INFOfmt_fields, 2378 /* bits */ 2, 2379 /* flags */ 0, 2380 }, 2381 #endif /* chips */ 2382 2383 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2384 { /* SOC_FORMAT_INT_MMU_EBCTM_TO_EBPCC_CT_FSM_STATEfmt */ 2385 /* format MMU_EBCTM_TO_EBPCC_CT_FSM_STATEfmt */ 2386 /* nFields */ 1, 2387 /* *fields */ soc_MMU_EBCTM_TO_EBPCC_CT_FSM_STATEfmt_fields, 2388 /* bits */ 4, 2389 /* flags */ 0, 2390 }, 2391 #endif /* chips */ 2392 2393 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2394 { /* SOC_FORMAT_INT_MMU_EBCTM_TO_EBQS_CT_FSM_STATE_INFOfmt */ 2395 /* format MMU_EBCTM_TO_EBQS_CT_FSM_STATE_INFOfmt */ 2396 /* nFields */ 1, 2397 /* *fields */ soc_MMU_EBCTM_TO_EBQS_CT_FSM_STATE_INFOfmt_fields, 2398 /* bits */ 3, 2399 /* flags */ 0, 2400 }, 2401 #endif /* chips */ 2402 2403 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2404 { /* SOC_FORMAT_INT_MMU_EBCTM_TO_PTSCH_PRETCT_INFOfmt */ 2405 /* format MMU_EBCTM_TO_PTSCH_PRETCT_INFOfmt */ 2406 /* nFields */ 2, 2407 /* *fields */ soc_MMU_EBCTM_TO_PTSCH_PRETCT_INFOfmt_fields, 2408 /* bits */ 6, 2409 /* flags */ 0, 2410 }, 2411 #endif /* chips */ 2412 2413 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2414 { /* SOC_FORMAT_INT_MMU_EBCTM_TO_RL_ENQ_CT_DECISION_INFOfmt */ 2415 /* format MMU_EBCTM_TO_RL_ENQ_CT_DECISION_INFOfmt */ 2416 /* nFields */ 2, 2417 /* *fields */ soc_MMU_EBCTM_TO_RL_ENQ_CT_DECISION_INFOfmt_fields, 2418 /* bits */ 2, 2419 /* flags */ 0, 2420 }, 2421 #endif /* chips */ 2422 2423 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2424 { /* SOC_FORMAT_INT_MMU_EBMB_TO_EBPTS_DEQ_INFOfmt */ 2425 /* format MMU_EBMB_TO_EBPTS_DEQ_INFOfmt */ 2426 /* nFields */ 5, 2427 /* *fields */ soc_MMU_EBMB_TO_EBPTS_DEQ_INFOfmt_fields, 2428 /* bits */ 16, 2429 /* flags */ 0, 2430 }, 2431 #endif /* chips */ 2432 2433 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2434 { /* SOC_FORMAT_INT_MMU_EBMB_TO_EP_CELL_DATAfmt */ 2435 /* format MMU_EBMB_TO_EP_CELL_DATAfmt */ 2436 /* nFields */ 2, 2437 /* *fields */ soc_MMU_EBMB_TO_EP_CELL_DATAfmt_fields, 2438 /* bits */ 2044, 2439 /* flags */ 0, 2440 }, 2441 #endif /* chips */ 2442 2443 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2444 { /* SOC_FORMAT_INT_MMU_EBPCC_TO_EBCTM_TCT_INFOfmt */ 2445 /* format MMU_EBPCC_TO_EBCTM_TCT_INFOfmt */ 2446 /* nFields */ 3, 2447 /* *fields */ soc_MMU_EBPCC_TO_EBCTM_TCT_INFOfmt_fields, 2448 /* bits */ 7, 2449 /* flags */ 0, 2450 }, 2451 #endif /* chips */ 2452 2453 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2454 { /* SOC_FORMAT_INT_MMU_EBPCC_TO_PTSCH_DEQ_INC_INFOfmt */ 2455 /* format MMU_EBPCC_TO_PTSCH_DEQ_INC_INFOfmt */ 2456 /* nFields */ 2, 2457 /* *fields */ soc_MMU_EBPCC_TO_PTSCH_DEQ_INC_INFOfmt_fields, 2458 /* bits */ 6, 2459 /* flags */ 0, 2460 }, 2461 #endif /* chips */ 2462 2463 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2464 { /* SOC_FORMAT_INT_MMU_EBPCC_TO_PTSCH_PFC_CREDIT_INFOfmt */ 2465 /* format MMU_EBPCC_TO_PTSCH_PFC_CREDIT_INFOfmt */ 2466 /* nFields */ 4, 2467 /* *fields */ soc_MMU_EBPCC_TO_PTSCH_PFC_CREDIT_INFOfmt_fields, 2468 /* bits */ 20, 2469 /* flags */ 0, 2470 }, 2471 #endif /* chips */ 2472 2473 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2474 { /* SOC_FORMAT_INT_MMU_EBPCC_TO_PTSCH_PFC_ENQ_INC_INFOfmt */ 2475 /* format MMU_EBPCC_TO_PTSCH_PFC_ENQ_INC_INFOfmt */ 2476 /* nFields */ 2, 2477 /* *fields */ soc_MMU_EBPCC_TO_PTSCH_PFC_ENQ_INC_INFOfmt_fields, 2478 /* bits */ 6, 2479 /* flags */ 0, 2480 }, 2481 #endif /* chips */ 2482 2483 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2484 { /* SOC_FORMAT_INT_MMU_EBPCC_TO_QSCH_QUEUE_XOFF_INFOfmt */ 2485 /* format MMU_EBPCC_TO_QSCH_QUEUE_XOFF_INFOfmt */ 2486 /* nFields */ 3, 2487 /* *fields */ soc_MMU_EBPCC_TO_QSCH_QUEUE_XOFF_INFOfmt_fields, 2488 /* bits */ 18, 2489 /* flags */ 0, 2490 }, 2491 #endif /* chips */ 2492 2493 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2494 { /* SOC_FORMAT_INT_MMU_EBPR_TO_EBCFP_CELL_INFOfmt */ 2495 /* format MMU_EBPR_TO_EBCFP_CELL_INFOfmt */ 2496 /* nFields */ 1, 2497 /* *fields */ soc_MMU_EBPR_TO_EBCFP_CELL_INFOfmt_fields, 2498 /* bits */ 104, 2499 /* flags */ 0, 2500 }, 2501 #endif /* chips */ 2502 2503 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2504 { /* SOC_FORMAT_INT_MMU_EBPTS_TO_EBQS_PICK_INFOfmt */ 2505 /* format MMU_EBPTS_TO_EBQS_PICK_INFOfmt */ 2506 /* nFields */ 4, 2507 /* *fields */ soc_MMU_EBPTS_TO_EBQS_PICK_INFOfmt_fields, 2508 /* bits */ 9, 2509 /* flags */ 0, 2510 }, 2511 #endif /* chips */ 2512 2513 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2514 { /* SOC_FORMAT_INT_MMU_EBPTS_TO_EBQS_PORT_CREDITS_AVLBLfmt */ 2515 /* format MMU_EBPTS_TO_EBQS_PORT_CREDITS_AVLBLfmt */ 2516 /* nFields */ 1, 2517 /* *fields */ soc_MMU_EBPTS_TO_EBQS_PORT_CREDITS_AVLBLfmt_fields, 2518 /* bits */ 8, 2519 /* flags */ 0, 2520 }, 2521 #endif /* chips */ 2522 2523 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2524 { /* SOC_FORMAT_INT_MMU_EBP_TO_EBMB_CELL_DATAfmt */ 2525 /* format MMU_EBP_TO_EBMB_CELL_DATAfmt */ 2526 /* nFields */ 4, 2527 /* *fields */ soc_MMU_EBP_TO_EBMB_CELL_DATAfmt_fields, 2528 /* bits */ 2049, 2529 /* flags */ 0, 2530 }, 2531 #endif /* chips */ 2532 2533 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2534 { /* SOC_FORMAT_INT_MMU_EBP_TO_EBMB_SLICE_DATAfmt */ 2535 /* format MMU_EBP_TO_EBMB_SLICE_DATAfmt */ 2536 /* nFields */ 2, 2537 /* *fields */ soc_MMU_EBP_TO_EBMB_SLICE_DATAfmt_fields, 2538 /* bits */ 257, 2539 /* flags */ 0, 2540 }, 2541 #endif /* chips */ 2542 2543 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2544 { /* SOC_FORMAT_INT_MMU_EBQS_ADV_PICK_INFOfmt */ 2545 /* format MMU_EBQS_ADV_PICK_INFOfmt */ 2546 /* nFields */ 4, 2547 /* *fields */ soc_MMU_EBQS_ADV_PICK_INFOfmt_fields, 2548 /* bits */ 7, 2549 /* flags */ 0, 2550 }, 2551 #endif /* chips */ 2552 2553 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2554 { /* SOC_FORMAT_INT_MMU_EBQS_ENQ_TO_PORT_INFOfmt */ 2555 /* format MMU_EBQS_ENQ_TO_PORT_INFOfmt */ 2556 /* nFields */ 6, 2557 /* *fields */ soc_MMU_EBQS_ENQ_TO_PORT_INFOfmt_fields, 2558 /* bits */ 9, 2559 /* flags */ 0, 2560 }, 2561 #endif /* chips */ 2562 2563 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2564 { /* SOC_FORMAT_INT_MMU_EBQS_TO_EBPCC_PFC_XOFF_STATE_PORTfmt */ 2565 /* format MMU_EBQS_TO_EBPCC_PFC_XOFF_STATE_PORTfmt */ 2566 /* nFields */ 1, 2567 /* *fields */ soc_MMU_EBQS_TO_EBPCC_PFC_XOFF_STATE_PORTfmt_fields, 2568 /* bits */ 9, 2569 /* flags */ 0, 2570 }, 2571 #endif /* chips */ 2572 2573 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2574 { /* SOC_FORMAT_INT_MMU_EBQS_TO_EBPTS_PREFETCH_INFOfmt */ 2575 /* format MMU_EBQS_TO_EBPTS_PREFETCH_INFOfmt */ 2576 /* nFields */ 3, 2577 /* *fields */ soc_MMU_EBQS_TO_EBPTS_PREFETCH_INFOfmt_fields, 2578 /* bits */ 4, 2579 /* flags */ 0, 2580 }, 2581 #endif /* chips */ 2582 2583 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2584 { /* SOC_FORMAT_INT_MMU_EBQS_TO_EBTOQ_DEQ_CELL_INFOfmt */ 2585 /* format MMU_EBQS_TO_EBTOQ_DEQ_CELL_INFOfmt */ 2586 /* nFields */ 6, 2587 /* *fields */ soc_MMU_EBQS_TO_EBTOQ_DEQ_CELL_INFOfmt_fields, 2588 /* bits */ 13, 2589 /* flags */ 0, 2590 }, 2591 #endif /* chips */ 2592 2593 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2594 { /* SOC_FORMAT_INT_MMU_EBTOQ_TO_EBCFP_DEQ_CELL_INFOfmt */ 2595 /* format MMU_EBTOQ_TO_EBCFP_DEQ_CELL_INFOfmt */ 2596 /* nFields */ 5, 2597 /* *fields */ soc_MMU_EBTOQ_TO_EBCFP_DEQ_CELL_INFOfmt_fields, 2598 /* bits */ 26, 2599 /* flags */ 0, 2600 }, 2601 #endif /* chips */ 2602 2603 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2604 { /* SOC_FORMAT_INT_MMU_EBTOQ_TO_EBCTM_DEQ_CELL_INFOfmt */ 2605 /* format MMU_EBTOQ_TO_EBCTM_DEQ_CELL_INFOfmt */ 2606 /* nFields */ 4, 2607 /* *fields */ soc_MMU_EBTOQ_TO_EBCTM_DEQ_CELL_INFOfmt_fields, 2608 /* bits */ 8, 2609 /* flags */ 0, 2610 }, 2611 #endif /* chips */ 2612 2613 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2614 { /* SOC_FORMAT_INT_MMU_EBTOQ_TO_EBCTM_ENQ_CELL_INFOfmt */ 2615 /* format MMU_EBTOQ_TO_EBCTM_ENQ_CELL_INFOfmt */ 2616 /* nFields */ 5, 2617 /* *fields */ soc_MMU_EBTOQ_TO_EBCTM_ENQ_CELL_INFOfmt_fields, 2618 /* bits */ 9, 2619 /* flags */ 0, 2620 }, 2621 #endif /* chips */ 2622 2623 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2624 { /* SOC_FORMAT_INT_MMU_EBTOQ_TO_EBPCC_DEQ_CELL_INFOfmt */ 2625 /* format MMU_EBTOQ_TO_EBPCC_DEQ_CELL_INFOfmt */ 2626 /* nFields */ 3, 2627 /* *fields */ soc_MMU_EBTOQ_TO_EBPCC_DEQ_CELL_INFOfmt_fields, 2628 /* bits */ 10, 2629 /* flags */ 0, 2630 }, 2631 #endif /* chips */ 2632 2633 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2634 { /* SOC_FORMAT_INT_MMU_EBTOQ_TO_EBPCC_ENQ_CELL_INFOfmt */ 2635 /* format MMU_EBTOQ_TO_EBPCC_ENQ_CELL_INFOfmt */ 2636 /* nFields */ 4, 2637 /* *fields */ soc_MMU_EBTOQ_TO_EBPCC_ENQ_CELL_INFOfmt_fields, 2638 /* bits */ 11, 2639 /* flags */ 0, 2640 }, 2641 #endif /* chips */ 2642 2643 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2644 { /* SOC_FORMAT_INT_MMU_EBTOQ_TO_EBQS_DEQ_CELL_INFOfmt */ 2645 /* format MMU_EBTOQ_TO_EBQS_DEQ_CELL_INFOfmt */ 2646 /* nFields */ 7, 2647 /* *fields */ soc_MMU_EBTOQ_TO_EBQS_DEQ_CELL_INFOfmt_fields, 2648 /* bits */ 14, 2649 /* flags */ 0, 2650 }, 2651 #endif /* chips */ 2652 2653 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2654 { /* SOC_FORMAT_INT_MMU_EBTOQ_TO_EBQS_ENQ_CELL_INFOfmt */ 2655 /* format MMU_EBTOQ_TO_EBQS_ENQ_CELL_INFOfmt */ 2656 /* nFields */ 8, 2657 /* *fields */ soc_MMU_EBTOQ_TO_EBQS_ENQ_CELL_INFOfmt_fields, 2658 /* bits */ 15, 2659 /* flags */ 0, 2660 }, 2661 #endif /* chips */ 2662 2663 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2664 { /* SOC_FORMAT_INT_MMU_EB_MIN_DEQUEUE_DELAYfmt */ 2665 /* format MMU_EB_MIN_DEQUEUE_DELAYfmt */ 2666 /* nFields */ 1, 2667 /* *fields */ soc_MMU_EB_MIN_DEQUEUE_DELAYfmt_fields, 2668 /* bits */ 6, 2669 /* flags */ 0, 2670 }, 2671 #endif /* chips */ 2672 2673 #if defined(BCM_56970_A0) 2674 { /* SOC_FORMAT_INT_MMU_ENQ_RQE_DATAfmt */ 2675 /* format MMU_ENQ_RQE_DATAfmt */ 2676 /* nFields */ 19, 2677 /* *fields */ soc_MMU_ENQ_RQE_DATAfmt_fields, 2678 /* bits */ 245, 2679 /* flags */ 0, 2680 }, 2681 #endif /* chips */ 2682 2683 #if defined(BCM_56370_A0) 2684 { /* SOC_FORMAT_INT_MMU_ENQ_RQE_DATA_BCM56370_A0fmt */ 2685 /* format MMU_ENQ_RQE_DATAfmt */ 2686 /* nFields */ 21, 2687 /* *fields */ soc_MMU_ENQ_RQE_DATA_BCM56370_A0fmt_fields, 2688 /* bits */ 249, 2689 /* flags */ 0, 2690 }, 2691 #endif /* chips */ 2692 2693 #if defined(BCM_56770_A0) 2694 { /* SOC_FORMAT_INT_MMU_ENQ_RQE_DATA_BCM56770_A0fmt */ 2695 /* format MMU_ENQ_RQE_DATAfmt */ 2696 /* nFields */ 20, 2697 /* *fields */ soc_MMU_ENQ_RQE_DATA_BCM56870_A0fmt_fields, 2698 /* bits */ 384, 2699 /* flags */ 0, 2700 }, 2701 #endif /* chips */ 2702 2703 #if defined(BCM_56870_A0) 2704 { /* SOC_FORMAT_INT_MMU_ENQ_RQE_DATA_BCM56870_A0fmt */ 2705 /* format MMU_ENQ_RQE_DATAfmt */ 2706 /* nFields */ 20, 2707 /* *fields */ soc_MMU_ENQ_RQE_DATA_BCM56870_A0fmt_fields, 2708 /* bits */ 384, 2709 /* flags */ 0, 2710 }, 2711 #endif /* chips */ 2712 2713 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 2714 defined(BCM_56450_B1) 2715 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_0fmt */ 2716 /* format MMU_ENQ_SOP_STORE_0fmt */ 2717 /* nFields */ 6, 2718 /* *fields */ soc_MMU_ENQ_SOP_STORE_0fmt_fields, 2719 /* bits */ 192, 2720 /* flags */ 0, 2721 }, 2722 #endif /* chips */ 2723 2724 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 2725 defined(BCM_56450_B1) 2726 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_1fmt */ 2727 /* format MMU_ENQ_SOP_STORE_1fmt */ 2728 /* nFields */ 7, 2729 /* *fields */ soc_MMU_ENQ_SOP_STORE_1fmt_fields, 2730 /* bits */ 195, 2731 /* flags */ 0, 2732 }, 2733 #endif /* chips */ 2734 2735 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 2736 defined(BCM_56450_B1) 2737 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_2fmt */ 2738 /* format MMU_ENQ_SOP_STORE_2fmt */ 2739 /* nFields */ 39, 2740 /* *fields */ soc_MMU_ENQ_SOP_STORE_2fmt_fields, 2741 /* bits */ 191, 2742 /* flags */ 0, 2743 }, 2744 #endif /* chips */ 2745 2746 #if defined(BCM_56260_A0) 2747 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_0_BCM56260_A0fmt */ 2748 /* format MMU_ENQ_SOP_STORE_0fmt */ 2749 /* nFields */ 7, 2750 /* *fields */ soc_MMU_ENQ_SOP_STORE_0_BCM56260_A0fmt_fields, 2751 /* bits */ 118, 2752 /* flags */ 0, 2753 }, 2754 #endif /* chips */ 2755 2756 #if defined(BCM_56260_B0) 2757 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_0_BCM56260_B0fmt */ 2758 /* format MMU_ENQ_SOP_STORE_0fmt */ 2759 /* nFields */ 7, 2760 /* *fields */ soc_MMU_ENQ_SOP_STORE_0_BCM56260_A0fmt_fields, 2761 /* bits */ 118, 2762 /* flags */ 0, 2763 }, 2764 #endif /* chips */ 2765 2766 #if defined(BCM_56270_A0) 2767 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_0_BCM56270_A0fmt */ 2768 /* format MMU_ENQ_SOP_STORE_0fmt */ 2769 /* nFields */ 7, 2770 /* *fields */ soc_MMU_ENQ_SOP_STORE_0_BCM56270_A0fmt_fields, 2771 /* bits */ 53, 2772 /* flags */ 0, 2773 }, 2774 #endif /* chips */ 2775 2776 #if defined(BCM_56260_A0) 2777 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_1_BCM56260_A0fmt */ 2778 /* format MMU_ENQ_SOP_STORE_1fmt */ 2779 /* nFields */ 7, 2780 /* *fields */ soc_MMU_ENQ_SOP_STORE_1_BCM56260_A0fmt_fields, 2781 /* bits */ 120, 2782 /* flags */ 0, 2783 }, 2784 #endif /* chips */ 2785 2786 #if defined(BCM_56260_B0) 2787 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_1_BCM56260_B0fmt */ 2788 /* format MMU_ENQ_SOP_STORE_1fmt */ 2789 /* nFields */ 7, 2790 /* *fields */ soc_MMU_ENQ_SOP_STORE_1_BCM56260_A0fmt_fields, 2791 /* bits */ 120, 2792 /* flags */ 0, 2793 }, 2794 #endif /* chips */ 2795 2796 #if defined(BCM_56270_A0) 2797 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_1_BCM56270_A0fmt */ 2798 /* format MMU_ENQ_SOP_STORE_1fmt */ 2799 /* nFields */ 7, 2800 /* *fields */ soc_MMU_ENQ_SOP_STORE_1_BCM56270_A0fmt_fields, 2801 /* bits */ 54, 2802 /* flags */ 0, 2803 }, 2804 #endif /* chips */ 2805 2806 #if defined(BCM_56260_A0) 2807 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_2_BCM56260_A0fmt */ 2808 /* format MMU_ENQ_SOP_STORE_2fmt */ 2809 /* nFields */ 39, 2810 /* *fields */ soc_MMU_ENQ_SOP_STORE_2_BCM56260_A0fmt_fields, 2811 /* bits */ 178, 2812 /* flags */ 0, 2813 }, 2814 #endif /* chips */ 2815 2816 #if defined(BCM_56260_B0) 2817 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_2_BCM56260_B0fmt */ 2818 /* format MMU_ENQ_SOP_STORE_2fmt */ 2819 /* nFields */ 39, 2820 /* *fields */ soc_MMU_ENQ_SOP_STORE_2_BCM56260_A0fmt_fields, 2821 /* bits */ 178, 2822 /* flags */ 0, 2823 }, 2824 #endif /* chips */ 2825 2826 #if defined(BCM_56270_A0) 2827 { /* SOC_FORMAT_INT_MMU_ENQ_SOP_STORE_2_BCM56270_A0fmt */ 2828 /* format MMU_ENQ_SOP_STORE_2fmt */ 2829 /* nFields */ 34, 2830 /* *fields */ soc_MMU_ENQ_SOP_STORE_2_BCM56270_A0fmt_fields, 2831 /* bits */ 159, 2832 /* flags */ 0, 2833 }, 2834 #endif /* chips */ 2835 2836 #if defined(BCM_56970_A0) 2837 { /* SOC_FORMAT_INT_MMU_ENQ_TO_RQE_DATAfmt */ 2838 /* format MMU_ENQ_TO_RQE_DATAfmt */ 2839 /* nFields */ 16, 2840 /* *fields */ soc_MMU_ENQ_TO_RQE_DATAfmt_fields, 2841 /* bits */ 229, 2842 /* flags */ 0, 2843 }, 2844 #endif /* chips */ 2845 2846 #if defined(BCM_56370_A0) 2847 { /* SOC_FORMAT_INT_MMU_ENQ_TO_RQE_DATA_BCM56370_A0fmt */ 2848 /* format MMU_ENQ_TO_RQE_DATAfmt */ 2849 /* nFields */ 17, 2850 /* *fields */ soc_MMU_ENQ_TO_RQE_DATA_BCM56370_A0fmt_fields, 2851 /* bits */ 245, 2852 /* flags */ 0, 2853 }, 2854 #endif /* chips */ 2855 2856 #if defined(BCM_56770_A0) 2857 { /* SOC_FORMAT_INT_MMU_ENQ_TO_RQE_DATA_BCM56770_A0fmt */ 2858 /* format MMU_ENQ_TO_RQE_DATAfmt */ 2859 /* nFields */ 16, 2860 /* *fields */ soc_MMU_ENQ_TO_RQE_DATA_BCM56870_A0fmt_fields, 2861 /* bits */ 364, 2862 /* flags */ 0, 2863 }, 2864 #endif /* chips */ 2865 2866 #if defined(BCM_56870_A0) 2867 { /* SOC_FORMAT_INT_MMU_ENQ_TO_RQE_DATA_BCM56870_A0fmt */ 2868 /* format MMU_ENQ_TO_RQE_DATAfmt */ 2869 /* nFields */ 16, 2870 /* *fields */ soc_MMU_ENQ_TO_RQE_DATA_BCM56870_A0fmt_fields, 2871 /* bits */ 364, 2872 /* flags */ 0, 2873 }, 2874 #endif /* chips */ 2875 2876 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 2877 defined(BCM_56870_A0) || defined(BCM_56970_A0) 2878 { /* SOC_FORMAT_INT_MMU_ES_TO_RQE_DATAfmt */ 2879 /* format MMU_ES_TO_RQE_DATAfmt */ 2880 /* nFields */ 2, 2881 /* *fields */ soc_MMU_ES_TO_RQE_DATAfmt_fields, 2882 /* bits */ 2, 2883 /* flags */ 0, 2884 }, 2885 #endif /* chips */ 2886 2887 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 2888 { /* SOC_FORMAT_INT_MMU_EXT_MC_QUEUE_LISTfmt */ 2889 /* format MMU_EXT_MC_QUEUE_LISTfmt */ 2890 /* nFields */ 11, 2891 /* *fields */ soc_MMU_EXT_MC_QUEUE_LISTfmt_fields, 2892 /* bits */ 164, 2893 /* flags */ 0, 2894 }, 2895 #endif /* chips */ 2896 2897 #if defined(BCM_56260_A0) 2898 { /* SOC_FORMAT_INT_MMU_EXT_MC_QUEUE_LIST_BCM56260_A0fmt */ 2899 /* format MMU_EXT_MC_QUEUE_LISTfmt */ 2900 /* nFields */ 10, 2901 /* *fields */ soc_MMU_EXT_MC_QUEUE_LIST_BCM56260_A0fmt_fields, 2902 /* bits */ 97, 2903 /* flags */ 0, 2904 }, 2905 #endif /* chips */ 2906 2907 #if defined(BCM_56260_B0) 2908 { /* SOC_FORMAT_INT_MMU_EXT_MC_QUEUE_LIST_BCM56260_B0fmt */ 2909 /* format MMU_EXT_MC_QUEUE_LISTfmt */ 2910 /* nFields */ 10, 2911 /* *fields */ soc_MMU_EXT_MC_QUEUE_LIST_BCM56260_A0fmt_fields, 2912 /* bits */ 97, 2913 /* flags */ 0, 2914 }, 2915 #endif /* chips */ 2916 2917 #if defined(BCM_56270_A0) 2918 { /* SOC_FORMAT_INT_MMU_EXT_MC_QUEUE_LIST_BCM56270_A0fmt */ 2919 /* format MMU_EXT_MC_QUEUE_LISTfmt */ 2920 /* nFields */ 10, 2921 /* *fields */ soc_MMU_EXT_MC_QUEUE_LIST_BCM56270_A0fmt_fields, 2922 /* bits */ 85, 2923 /* flags */ 0, 2924 }, 2925 #endif /* chips */ 2926 2927 #if defined(BCM_56450_A0) 2928 { /* SOC_FORMAT_INT_MMU_EXT_MC_QUEUE_LIST_BCM56450_A0fmt */ 2929 /* format MMU_EXT_MC_QUEUE_LISTfmt */ 2930 /* nFields */ 11, 2931 /* *fields */ soc_MMU_EXT_MC_QUEUE_LIST_BCM56450_A0fmt_fields, 2932 /* bits */ 164, 2933 /* flags */ 0, 2934 }, 2935 #endif /* chips */ 2936 2937 #if defined(BCM_56450_B0) 2938 { /* SOC_FORMAT_INT_MMU_EXT_MC_QUEUE_LIST_BCM56450_B0fmt */ 2939 /* format MMU_EXT_MC_QUEUE_LISTfmt */ 2940 /* nFields */ 11, 2941 /* *fields */ soc_MMU_EXT_MC_QUEUE_LIST_BCM56450_A0fmt_fields, 2942 /* bits */ 164, 2943 /* flags */ 0, 2944 }, 2945 #endif /* chips */ 2946 2947 #if defined(BCM_56450_B1) 2948 { /* SOC_FORMAT_INT_MMU_EXT_MC_QUEUE_LIST_BCM56450_B1fmt */ 2949 /* format MMU_EXT_MC_QUEUE_LISTfmt */ 2950 /* nFields */ 11, 2951 /* *fields */ soc_MMU_EXT_MC_QUEUE_LIST_BCM56450_A0fmt_fields, 2952 /* bits */ 164, 2953 /* flags */ 0, 2954 }, 2955 #endif /* chips */ 2956 2957 #if defined(BCM_56224_A0) || defined(BCM_56504_B0) || \ 2958 defined(BCM_56514_A0) || defined(BCM_56800_A0) 2959 { /* SOC_FORMAT_INT_MMU_HGCRRUHEADER_EXTfmt */ 2960 /* format MMU_HGCRRUHEADER_EXTfmt */ 2961 /* nFields */ 1, 2962 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 2963 /* bits */ 28, 2964 /* flags */ 0, 2965 }, 2966 #endif /* chips */ 2967 2968 #if defined(BCM_53314_A0) 2969 { /* SOC_FORMAT_INT_MMU_HGCRRUHEADER_EXT_BCM53314_A0fmt */ 2970 /* format MMU_HGCRRUHEADER_EXTfmt */ 2971 /* nFields */ 1, 2972 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 2973 /* bits */ 28, 2974 /* flags */ 0, 2975 }, 2976 #endif /* chips */ 2977 2978 #if defined(BCM_53324_A0) 2979 { /* SOC_FORMAT_INT_MMU_HGCRRUHEADER_EXT_BCM53324_A0fmt */ 2980 /* format MMU_HGCRRUHEADER_EXTfmt */ 2981 /* nFields */ 1, 2982 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 2983 /* bits */ 28, 2984 /* flags */ 0, 2985 }, 2986 #endif /* chips */ 2987 2988 #if defined(BCM_56224_B0) 2989 { /* SOC_FORMAT_INT_MMU_HGCRRUHEADER_EXT_BCM56224_B0fmt */ 2990 /* format MMU_HGCRRUHEADER_EXTfmt */ 2991 /* nFields */ 1, 2992 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 2993 /* bits */ 28, 2994 /* flags */ 0, 2995 }, 2996 #endif /* chips */ 2997 2998 #if defined(BCM_56314_A0) 2999 { /* SOC_FORMAT_INT_MMU_HGCRRUHEADER_EXT_BCM56314_A0fmt */ 3000 /* format MMU_HGCRRUHEADER_EXTfmt */ 3001 /* nFields */ 1, 3002 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3003 /* bits */ 28, 3004 /* flags */ 0, 3005 }, 3006 #endif /* chips */ 3007 3008 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 3009 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 3010 defined(BCM_56504_A0) 3011 { /* SOC_FORMAT_INT_MMU_HGPPPHEADERfmt */ 3012 /* format MMU_HGPPPHEADERfmt */ 3013 /* nFields */ 1, 3014 /* *fields */ soc_MMU_HGPPPHEADERfmt_fields, 3015 /* bits */ 62, 3016 /* flags */ 0, 3017 }, 3018 #endif /* chips */ 3019 3020 #if defined(BCM_56314_A0) 3021 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_BCM56314_A0fmt */ 3022 /* format MMU_HGPPPHEADERfmt */ 3023 /* nFields */ 1, 3024 /* *fields */ soc_MMU_HGPPPHEADER_BCM56504_B0fmt_fields, 3025 /* bits */ 11, 3026 /* flags */ 0, 3027 }, 3028 #endif /* chips */ 3029 3030 #if defined(BCM_56504_B0) 3031 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_BCM56504_B0fmt */ 3032 /* format MMU_HGPPPHEADERfmt */ 3033 /* nFields */ 1, 3034 /* *fields */ soc_MMU_HGPPPHEADER_BCM56504_B0fmt_fields, 3035 /* bits */ 11, 3036 /* flags */ 0, 3037 }, 3038 #endif /* chips */ 3039 3040 #if defined(BCM_56514_A0) 3041 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_BCM56514_A0fmt */ 3042 /* format MMU_HGPPPHEADERfmt */ 3043 /* nFields */ 1, 3044 /* *fields */ soc_MMU_HGPPPHEADER_BCM56514_A0fmt_fields, 3045 /* bits */ 12, 3046 /* flags */ 0, 3047 }, 3048 #endif /* chips */ 3049 3050 #if defined(BCM_56800_A0) 3051 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_BCM56800_A0fmt */ 3052 /* format MMU_HGPPPHEADERfmt */ 3053 /* nFields */ 1, 3054 /* *fields */ soc_MMU_HGPPPHEADERfmt_fields, 3055 /* bits */ 62, 3056 /* flags */ 0, 3057 }, 3058 #endif /* chips */ 3059 3060 #if defined(BCM_56504_B0) 3061 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXTfmt */ 3062 /* format MMU_HGPPPHEADER_EXTfmt */ 3063 /* nFields */ 1, 3064 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3065 /* bits */ 28, 3066 /* flags */ 0, 3067 }, 3068 #endif /* chips */ 3069 3070 #if defined(BCM_53314_A0) 3071 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXT_BCM53314_A0fmt */ 3072 /* format MMU_HGPPPHEADER_EXTfmt */ 3073 /* nFields */ 1, 3074 /* *fields */ soc_MMU_HGPPPHEADER_EXTfmt_fields, 3075 /* bits */ 63, 3076 /* flags */ 0, 3077 }, 3078 #endif /* chips */ 3079 3080 #if defined(BCM_53324_A0) 3081 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXT_BCM53324_A0fmt */ 3082 /* format MMU_HGPPPHEADER_EXTfmt */ 3083 /* nFields */ 1, 3084 /* *fields */ soc_MMU_HGPPPHEADER_EXTfmt_fields, 3085 /* bits */ 63, 3086 /* flags */ 0, 3087 }, 3088 #endif /* chips */ 3089 3090 #if defined(BCM_56224_A0) 3091 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXT_BCM56224_A0fmt */ 3092 /* format MMU_HGPPPHEADER_EXTfmt */ 3093 /* nFields */ 1, 3094 /* *fields */ soc_MMU_HGPPPHEADER_EXTfmt_fields, 3095 /* bits */ 63, 3096 /* flags */ 0, 3097 }, 3098 #endif /* chips */ 3099 3100 #if defined(BCM_56224_B0) 3101 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXT_BCM56224_B0fmt */ 3102 /* format MMU_HGPPPHEADER_EXTfmt */ 3103 /* nFields */ 1, 3104 /* *fields */ soc_MMU_HGPPPHEADER_EXTfmt_fields, 3105 /* bits */ 63, 3106 /* flags */ 0, 3107 }, 3108 #endif /* chips */ 3109 3110 #if defined(BCM_56314_A0) 3111 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXT_BCM56314_A0fmt */ 3112 /* format MMU_HGPPPHEADER_EXTfmt */ 3113 /* nFields */ 1, 3114 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3115 /* bits */ 28, 3116 /* flags */ 0, 3117 }, 3118 #endif /* chips */ 3119 3120 #if defined(BCM_56514_A0) 3121 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXT_BCM56514_A0fmt */ 3122 /* format MMU_HGPPPHEADER_EXTfmt */ 3123 /* nFields */ 1, 3124 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3125 /* bits */ 28, 3126 /* flags */ 0, 3127 }, 3128 #endif /* chips */ 3129 3130 #if defined(BCM_56800_A0) 3131 { /* SOC_FORMAT_INT_MMU_HGPPPHEADER_EXT_BCM56800_A0fmt */ 3132 /* format MMU_HGPPPHEADER_EXTfmt */ 3133 /* nFields */ 1, 3134 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3135 /* bits */ 28, 3136 /* flags */ 0, 3137 }, 3138 #endif /* chips */ 3139 3140 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 3141 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 3142 defined(BCM_56224_B0) || defined(BCM_56504_A0) 3143 { /* SOC_FORMAT_INT_MMU_HGXQHEADERfmt */ 3144 /* format MMU_HGXQHEADERfmt */ 3145 /* nFields */ 2, 3146 /* *fields */ soc_MMU_HGXQHEADERfmt_fields, 3147 /* bits */ 59, 3148 /* flags */ 0, 3149 }, 3150 #endif /* chips */ 3151 3152 #if defined(BCM_53400_A0) 3153 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM53400_A0fmt */ 3154 /* format MMU_HGXQHEADERfmt */ 3155 /* nFields */ 2, 3156 /* *fields */ soc_MMU_HGXQHEADER_BCM53400_A0fmt_fields, 3157 /* bits */ 59, 3158 /* flags */ 0, 3159 }, 3160 #endif /* chips */ 3161 3162 #if defined(BCM_53540_A0) 3163 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM53540_A0fmt */ 3164 /* format MMU_HGXQHEADERfmt */ 3165 /* nFields */ 1, 3166 /* *fields */ soc_MMU_HGXQHEADER_BCM53540_A0fmt_fields, 3167 /* bits */ 6, 3168 /* flags */ 0, 3169 }, 3170 #endif /* chips */ 3171 3172 #if defined(BCM_53570_A0) 3173 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM53570_A0fmt */ 3174 /* format MMU_HGXQHEADERfmt */ 3175 /* nFields */ 1, 3176 /* *fields */ soc_MMU_HGXQHEADER_BCM56160_A0fmt_fields, 3177 /* bits */ 10, 3178 /* flags */ 0, 3179 }, 3180 #endif /* chips */ 3181 3182 #if defined(BCM_53570_B0) 3183 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM53570_B0fmt */ 3184 /* format MMU_HGXQHEADERfmt */ 3185 /* nFields */ 1, 3186 /* *fields */ soc_MMU_HGXQHEADER_BCM53570_B0fmt_fields, 3187 /* bits */ 12, 3188 /* flags */ 0, 3189 }, 3190 #endif /* chips */ 3191 3192 #if defined(BCM_56150_A0) 3193 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM56150_A0fmt */ 3194 /* format MMU_HGXQHEADERfmt */ 3195 /* nFields */ 2, 3196 /* *fields */ soc_MMU_HGXQHEADER_BCM56150_A0fmt_fields, 3197 /* bits */ 59, 3198 /* flags */ 0, 3199 }, 3200 #endif /* chips */ 3201 3202 #if defined(BCM_56160_A0) 3203 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM56160_A0fmt */ 3204 /* format MMU_HGXQHEADERfmt */ 3205 /* nFields */ 1, 3206 /* *fields */ soc_MMU_HGXQHEADER_BCM56160_A0fmt_fields, 3207 /* bits */ 10, 3208 /* flags */ 0, 3209 }, 3210 #endif /* chips */ 3211 3212 #if defined(BCM_56314_A0) 3213 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM56314_A0fmt */ 3214 /* format MMU_HGXQHEADERfmt */ 3215 /* nFields */ 1, 3216 /* *fields */ soc_MMU_HGXQHEADER_BCM56504_B0fmt_fields, 3217 /* bits */ 10, 3218 /* flags */ 0, 3219 }, 3220 #endif /* chips */ 3221 3222 #if defined(BCM_56504_B0) 3223 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM56504_B0fmt */ 3224 /* format MMU_HGXQHEADERfmt */ 3225 /* nFields */ 1, 3226 /* *fields */ soc_MMU_HGXQHEADER_BCM56504_B0fmt_fields, 3227 /* bits */ 10, 3228 /* flags */ 0, 3229 }, 3230 #endif /* chips */ 3231 3232 #if defined(BCM_56514_A0) 3233 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM56514_A0fmt */ 3234 /* format MMU_HGXQHEADERfmt */ 3235 /* nFields */ 1, 3236 /* *fields */ soc_MMU_HGXQHEADER_BCM56514_A0fmt_fields, 3237 /* bits */ 11, 3238 /* flags */ 0, 3239 }, 3240 #endif /* chips */ 3241 3242 #if defined(BCM_56800_A0) 3243 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_BCM56800_A0fmt */ 3244 /* format MMU_HGXQHEADERfmt */ 3245 /* nFields */ 2, 3246 /* *fields */ soc_MMU_HGXQHEADERfmt_fields, 3247 /* bits */ 59, 3248 /* flags */ 0, 3249 }, 3250 #endif /* chips */ 3251 3252 #if defined(BCM_56504_B0) 3253 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXTfmt */ 3254 /* format MMU_HGXQHEADER_EXTfmt */ 3255 /* nFields */ 1, 3256 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3257 /* bits */ 28, 3258 /* flags */ 0, 3259 }, 3260 #endif /* chips */ 3261 3262 #if defined(BCM_53314_A0) 3263 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM53314_A0fmt */ 3264 /* format MMU_HGXQHEADER_EXTfmt */ 3265 /* nFields */ 9, 3266 /* *fields */ soc_MMU_HGXQHEADER_EXTfmt_fields, 3267 /* bits */ 55, 3268 /* flags */ 0, 3269 }, 3270 #endif /* chips */ 3271 3272 #if defined(BCM_53324_A0) 3273 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM53324_A0fmt */ 3274 /* format MMU_HGXQHEADER_EXTfmt */ 3275 /* nFields */ 9, 3276 /* *fields */ soc_MMU_HGXQHEADER_EXTfmt_fields, 3277 /* bits */ 55, 3278 /* flags */ 0, 3279 }, 3280 #endif /* chips */ 3281 3282 #if defined(BCM_53400_A0) 3283 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM53400_A0fmt */ 3284 /* format MMU_HGXQHEADER_EXTfmt */ 3285 /* nFields */ 10, 3286 /* *fields */ soc_MMU_HGXQHEADER_EXT_BCM53400_A0fmt_fields, 3287 /* bits */ 68, 3288 /* flags */ 0, 3289 }, 3290 #endif /* chips */ 3291 3292 #if defined(BCM_53540_A0) 3293 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM53540_A0fmt */ 3294 /* format MMU_HGXQHEADER_EXTfmt */ 3295 /* nFields */ 10, 3296 /* *fields */ soc_MMU_HGXQHEADER_EXT_BCM53400_A0fmt_fields, 3297 /* bits */ 68, 3298 /* flags */ 0, 3299 }, 3300 #endif /* chips */ 3301 3302 #if defined(BCM_53570_A0) 3303 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM53570_A0fmt */ 3304 /* format MMU_HGXQHEADER_EXTfmt */ 3305 /* nFields */ 10, 3306 /* *fields */ soc_MMU_HGXQHEADER_EXT_BCM53400_A0fmt_fields, 3307 /* bits */ 68, 3308 /* flags */ 0, 3309 }, 3310 #endif /* chips */ 3311 3312 #if defined(BCM_53570_B0) 3313 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM53570_B0fmt */ 3314 /* format MMU_HGXQHEADER_EXTfmt */ 3315 /* nFields */ 10, 3316 /* *fields */ soc_MMU_HGXQHEADER_EXT_BCM53400_A0fmt_fields, 3317 /* bits */ 68, 3318 /* flags */ 0, 3319 }, 3320 #endif /* chips */ 3321 3322 #if defined(BCM_56142_A0) 3323 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56142_A0fmt */ 3324 /* format MMU_HGXQHEADER_EXTfmt */ 3325 /* nFields */ 10, 3326 /* *fields */ soc_MMU_HGXQHEADER_EXT_BCM56142_A0fmt_fields, 3327 /* bits */ 68, 3328 /* flags */ 0, 3329 }, 3330 #endif /* chips */ 3331 3332 #if defined(BCM_56150_A0) 3333 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56150_A0fmt */ 3334 /* format MMU_HGXQHEADER_EXTfmt */ 3335 /* nFields */ 10, 3336 /* *fields */ soc_MMU_HGXQHEADER_EXT_BCM56150_A0fmt_fields, 3337 /* bits */ 68, 3338 /* flags */ 0, 3339 }, 3340 #endif /* chips */ 3341 3342 #if defined(BCM_56160_A0) 3343 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56160_A0fmt */ 3344 /* format MMU_HGXQHEADER_EXTfmt */ 3345 /* nFields */ 10, 3346 /* *fields */ soc_MMU_HGXQHEADER_EXT_BCM53400_A0fmt_fields, 3347 /* bits */ 68, 3348 /* flags */ 0, 3349 }, 3350 #endif /* chips */ 3351 3352 #if defined(BCM_56224_A0) 3353 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56224_A0fmt */ 3354 /* format MMU_HGXQHEADER_EXTfmt */ 3355 /* nFields */ 9, 3356 /* *fields */ soc_MMU_HGXQHEADER_EXTfmt_fields, 3357 /* bits */ 55, 3358 /* flags */ 0, 3359 }, 3360 #endif /* chips */ 3361 3362 #if defined(BCM_56224_B0) 3363 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56224_B0fmt */ 3364 /* format MMU_HGXQHEADER_EXTfmt */ 3365 /* nFields */ 9, 3366 /* *fields */ soc_MMU_HGXQHEADER_EXTfmt_fields, 3367 /* bits */ 55, 3368 /* flags */ 0, 3369 }, 3370 #endif /* chips */ 3371 3372 #if defined(BCM_56314_A0) 3373 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56314_A0fmt */ 3374 /* format MMU_HGXQHEADER_EXTfmt */ 3375 /* nFields */ 1, 3376 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3377 /* bits */ 28, 3378 /* flags */ 0, 3379 }, 3380 #endif /* chips */ 3381 3382 #if defined(BCM_56514_A0) 3383 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56514_A0fmt */ 3384 /* format MMU_HGXQHEADER_EXTfmt */ 3385 /* nFields */ 1, 3386 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3387 /* bits */ 28, 3388 /* flags */ 0, 3389 }, 3390 #endif /* chips */ 3391 3392 #if defined(BCM_56800_A0) 3393 { /* SOC_FORMAT_INT_MMU_HGXQHEADER_EXT_BCM56800_A0fmt */ 3394 /* format MMU_HGXQHEADER_EXTfmt */ 3395 /* nFields */ 1, 3396 /* *fields */ soc_MMU_HGCRRUHEADER_EXTfmt_fields, 3397 /* bits */ 28, 3398 /* flags */ 0, 3399 }, 3400 #endif /* chips */ 3401 3402 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 3403 defined(BCM_56504_B0) || defined(BCM_56514_A0) 3404 { /* SOC_FORMAT_INT_MMU_IDMHEADERfmt */ 3405 /* format MMU_IDMHEADERfmt */ 3406 /* nFields */ 21, 3407 /* *fields */ soc_MMU_IDMHEADERfmt_fields, 3408 /* bits */ 139, 3409 /* flags */ 0, 3410 }, 3411 #endif /* chips */ 3412 3413 #if defined(BCM_53314_A0) 3414 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM53314_A0fmt */ 3415 /* format MMU_IDMHEADERfmt */ 3416 /* nFields */ 21, 3417 /* *fields */ soc_MMU_IDMHEADER_BCM53314_A0fmt_fields, 3418 /* bits */ 139, 3419 /* flags */ 0, 3420 }, 3421 #endif /* chips */ 3422 3423 #if defined(BCM_53324_A0) 3424 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM53324_A0fmt */ 3425 /* format MMU_IDMHEADERfmt */ 3426 /* nFields */ 21, 3427 /* *fields */ soc_MMU_IDMHEADER_BCM53314_A0fmt_fields, 3428 /* bits */ 139, 3429 /* flags */ 0, 3430 }, 3431 #endif /* chips */ 3432 3433 #if defined(BCM_53400_A0) 3434 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM53400_A0fmt */ 3435 /* format MMU_IDMHEADERfmt */ 3436 /* nFields */ 21, 3437 /* *fields */ soc_MMU_IDMHEADER_BCM53400_A0fmt_fields, 3438 /* bits */ 139, 3439 /* flags */ 0, 3440 }, 3441 #endif /* chips */ 3442 3443 #if defined(BCM_53540_A0) 3444 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM53540_A0fmt */ 3445 /* format MMU_IDMHEADERfmt */ 3446 /* nFields */ 21, 3447 /* *fields */ soc_MMU_IDMHEADER_BCM56160_A0fmt_fields, 3448 /* bits */ 143, 3449 /* flags */ 0, 3450 }, 3451 #endif /* chips */ 3452 3453 #if defined(BCM_53570_A0) 3454 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM53570_A0fmt */ 3455 /* format MMU_IDMHEADERfmt */ 3456 /* nFields */ 22, 3457 /* *fields */ soc_MMU_IDMHEADER_BCM53570_A0fmt_fields, 3458 /* bits */ 195, 3459 /* flags */ 0, 3460 }, 3461 #endif /* chips */ 3462 3463 #if defined(BCM_53570_B0) 3464 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM53570_B0fmt */ 3465 /* format MMU_IDMHEADERfmt */ 3466 /* nFields */ 22, 3467 /* *fields */ soc_MMU_IDMHEADER_BCM53570_A0fmt_fields, 3468 /* bits */ 195, 3469 /* flags */ 0, 3470 }, 3471 #endif /* chips */ 3472 3473 #if defined(BCM_56142_A0) 3474 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM56142_A0fmt */ 3475 /* format MMU_IDMHEADERfmt */ 3476 /* nFields */ 20, 3477 /* *fields */ soc_MMU_IDMHEADER_BCM56142_A0fmt_fields, 3478 /* bits */ 139, 3479 /* flags */ 0, 3480 }, 3481 #endif /* chips */ 3482 3483 #if defined(BCM_56150_A0) 3484 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM56150_A0fmt */ 3485 /* format MMU_IDMHEADERfmt */ 3486 /* nFields */ 20, 3487 /* *fields */ soc_MMU_IDMHEADER_BCM56150_A0fmt_fields, 3488 /* bits */ 139, 3489 /* flags */ 0, 3490 }, 3491 #endif /* chips */ 3492 3493 #if defined(BCM_56160_A0) 3494 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM56160_A0fmt */ 3495 /* format MMU_IDMHEADERfmt */ 3496 /* nFields */ 21, 3497 /* *fields */ soc_MMU_IDMHEADER_BCM56160_A0fmt_fields, 3498 /* bits */ 143, 3499 /* flags */ 0, 3500 }, 3501 #endif /* chips */ 3502 3503 #if defined(BCM_56224_A0) 3504 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM56224_A0fmt */ 3505 /* format MMU_IDMHEADERfmt */ 3506 /* nFields */ 20, 3507 /* *fields */ soc_MMU_IDMHEADER_BCM56224_A0fmt_fields, 3508 /* bits */ 139, 3509 /* flags */ 0, 3510 }, 3511 #endif /* chips */ 3512 3513 #if defined(BCM_56224_B0) 3514 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM56224_B0fmt */ 3515 /* format MMU_IDMHEADERfmt */ 3516 /* nFields */ 20, 3517 /* *fields */ soc_MMU_IDMHEADER_BCM56224_A0fmt_fields, 3518 /* bits */ 139, 3519 /* flags */ 0, 3520 }, 3521 #endif /* chips */ 3522 3523 #if defined(BCM_56800_A0) 3524 { /* SOC_FORMAT_INT_MMU_IDMHEADER_BCM56800_A0fmt */ 3525 /* format MMU_IDMHEADERfmt */ 3526 /* nFields */ 21, 3527 /* *fields */ soc_MMU_IDMHEADERfmt_fields, 3528 /* bits */ 139, 3529 /* flags */ 0, 3530 }, 3531 #endif /* chips */ 3532 3533 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3534 { /* SOC_FORMAT_INT_MMU_INTFI_TO_EBCFP_QUEUES_PURGE_INFOfmt */ 3535 /* format MMU_INTFI_TO_EBCFP_QUEUES_PURGE_INFOfmt */ 3536 /* nFields */ 4, 3537 /* *fields */ soc_MMU_INTFI_TO_EBCFP_QUEUES_PURGE_INFOfmt_fields, 3538 /* bits */ 27, 3539 /* flags */ 0, 3540 }, 3541 #endif /* chips */ 3542 3543 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3544 { /* SOC_FORMAT_INT_MMU_INTFI_TO_EBCTM_PORT_FC_INFOfmt */ 3545 /* format MMU_INTFI_TO_EBCTM_PORT_FC_INFOfmt */ 3546 /* nFields */ 3, 3547 /* *fields */ soc_MMU_INTFI_TO_EBCTM_PORT_FC_INFOfmt_fields, 3548 /* bits */ 7, 3549 /* flags */ 0, 3550 }, 3551 #endif /* chips */ 3552 3553 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3554 { /* SOC_FORMAT_INT_MMU_INTFI_TO_EBPCC_QUEUES_FC_INFOfmt */ 3555 /* format MMU_INTFI_TO_EBPCC_QUEUES_FC_INFOfmt */ 3556 /* nFields */ 4, 3557 /* *fields */ soc_MMU_INTFI_TO_EBPCC_QUEUES_FC_INFOfmt_fields, 3558 /* bits */ 27, 3559 /* flags */ 0, 3560 }, 3561 #endif /* chips */ 3562 3563 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3564 { /* SOC_FORMAT_INT_MMU_INTFI_TO_EBQS_EB_QUEUES_FC_INFOfmt */ 3565 /* format MMU_INTFI_TO_EBQS_EB_QUEUES_FC_INFOfmt */ 3566 /* nFields */ 3, 3567 /* *fields */ soc_MMU_INTFI_TO_EBQS_EB_QUEUES_FC_INFOfmt_fields, 3568 /* bits */ 15, 3569 /* flags */ 0, 3570 }, 3571 #endif /* chips */ 3572 3573 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 3574 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 3575 defined(BCM_56504_B0) 3576 { /* SOC_FORMAT_INT_MMU_IPMCGROUPTABLEfmt */ 3577 /* format MMU_IPMCGROUPTABLEfmt */ 3578 /* nFields */ 12, 3579 /* *fields */ soc_MMU_IPMCGROUPTABLEfmt_fields, 3580 /* bits */ 132, 3581 /* flags */ 0, 3582 }, 3583 #endif /* chips */ 3584 3585 #if defined(BCM_56800_A0) 3586 { /* SOC_FORMAT_INT_MMU_IPMCGROUPTABLE_BCM56800_A0fmt */ 3587 /* format MMU_IPMCGROUPTABLEfmt */ 3588 /* nFields */ 12, 3589 /* *fields */ soc_MMU_IPMCGROUPTABLEfmt_fields, 3590 /* bits */ 132, 3591 /* flags */ 0, 3592 }, 3593 #endif /* chips */ 3594 3595 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 3596 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 3597 defined(BCM_56504_B0) || defined(BCM_56800_A0) 3598 { /* SOC_FORMAT_INT_MMU_IPMCHEADERfmt */ 3599 /* format MMU_IPMCHEADERfmt */ 3600 /* nFields */ 3, 3601 /* *fields */ soc_MMU_IPMCHEADERfmt_fields, 3602 /* bits */ 6, 3603 /* flags */ 0, 3604 }, 3605 #endif /* chips */ 3606 3607 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 3608 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 3609 defined(BCM_56504_B0) 3610 { /* SOC_FORMAT_INT_MMU_IPMCVLANTABLEfmt */ 3611 /* format MMU_IPMCVLANTABLEfmt */ 3612 /* nFields */ 3, 3613 /* *fields */ soc_MMU_IPMCVLANTABLEfmt_fields, 3614 /* bits */ 81, 3615 /* flags */ 0, 3616 }, 3617 #endif /* chips */ 3618 3619 #if defined(BCM_56142_A0) 3620 { /* SOC_FORMAT_INT_MMU_IPMCVLANTABLE_BCM56142_A0fmt */ 3621 /* format MMU_IPMCVLANTABLEfmt */ 3622 /* nFields */ 3, 3623 /* *fields */ soc_MMU_IPMCVLANTABLE_BCM56142_A0fmt_fields, 3624 /* bits */ 74, 3625 /* flags */ 0, 3626 }, 3627 #endif /* chips */ 3628 3629 #if defined(BCM_56150_A0) 3630 { /* SOC_FORMAT_INT_MMU_IPMCVLANTABLE_BCM56150_A0fmt */ 3631 /* format MMU_IPMCVLANTABLEfmt */ 3632 /* nFields */ 3, 3633 /* *fields */ soc_MMU_IPMCVLANTABLE_BCM56150_A0fmt_fields, 3634 /* bits */ 74, 3635 /* flags */ 0, 3636 }, 3637 #endif /* chips */ 3638 3639 #if defined(BCM_56800_A0) 3640 { /* SOC_FORMAT_INT_MMU_IPMCVLANTABLE_BCM56800_A0fmt */ 3641 /* format MMU_IPMCVLANTABLEfmt */ 3642 /* nFields */ 3, 3643 /* *fields */ soc_MMU_IPMCVLANTABLEfmt_fields, 3644 /* bits */ 81, 3645 /* flags */ 0, 3646 }, 3647 #endif /* chips */ 3648 3649 #if defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 3650 defined(BCM_56634_B0) 3651 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALLfmt */ 3652 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3653 /* nFields */ 53, 3654 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3655 /* bits */ 742, 3656 /* flags */ 0, 3657 }, 3658 #endif /* chips */ 3659 3660 #if defined(BCM_56334_A0) 3661 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56334_A0fmt */ 3662 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3663 /* nFields */ 28, 3664 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALL_BCM56334_A0fmt_fields, 3665 /* bits */ 364, 3666 /* flags */ 0, 3667 }, 3668 #endif /* chips */ 3669 3670 #if defined(BCM_56334_B0) 3671 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56334_B0fmt */ 3672 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3673 /* nFields */ 28, 3674 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALL_BCM56334_A0fmt_fields, 3675 /* bits */ 364, 3676 /* flags */ 0, 3677 }, 3678 #endif /* chips */ 3679 3680 #if defined(BCM_56524_A0) 3681 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56524_A0fmt */ 3682 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3683 /* nFields */ 53, 3684 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3685 /* bits */ 742, 3686 /* flags */ 0, 3687 }, 3688 #endif /* chips */ 3689 3690 #if defined(BCM_56524_B0) 3691 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56524_B0fmt */ 3692 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3693 /* nFields */ 53, 3694 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3695 /* bits */ 742, 3696 /* flags */ 0, 3697 }, 3698 #endif /* chips */ 3699 3700 #if defined(BCM_56624_B0) 3701 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56624_B0fmt */ 3702 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3703 /* nFields */ 53, 3704 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3705 /* bits */ 742, 3706 /* flags */ 0, 3707 }, 3708 #endif /* chips */ 3709 3710 #if defined(BCM_56680_A0) 3711 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56680_A0fmt */ 3712 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3713 /* nFields */ 53, 3714 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3715 /* bits */ 742, 3716 /* flags */ 0, 3717 }, 3718 #endif /* chips */ 3719 3720 #if defined(BCM_56680_B0) 3721 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56680_B0fmt */ 3722 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3723 /* nFields */ 53, 3724 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3725 /* bits */ 742, 3726 /* flags */ 0, 3727 }, 3728 #endif /* chips */ 3729 3730 #if defined(BCM_56685_A0) 3731 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56685_A0fmt */ 3732 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3733 /* nFields */ 53, 3734 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3735 /* bits */ 742, 3736 /* flags */ 0, 3737 }, 3738 #endif /* chips */ 3739 3740 #if defined(BCM_56685_B0) 3741 { /* SOC_FORMAT_INT_MMU_IPMC_GRP_TBL_ALL_BCM56685_B0fmt */ 3742 /* format MMU_IPMC_GRP_TBL_ALLfmt */ 3743 /* nFields */ 53, 3744 /* *fields */ soc_MMU_IPMC_GRP_TBL_ALLfmt_fields, 3745 /* bits */ 742, 3746 /* flags */ 0, 3747 }, 3748 #endif /* chips */ 3749 3750 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 3751 defined(BCM_56450_B1) 3752 { /* SOC_FORMAT_INT_MMU_ITE_CTRL_0fmt */ 3753 /* format MMU_ITE_CTRL_0fmt */ 3754 /* nFields */ 24, 3755 /* *fields */ soc_MMU_ITE_CTRL_0fmt_fields, 3756 /* bits */ 131, 3757 /* flags */ 0, 3758 }, 3759 #endif /* chips */ 3760 3761 #if defined(BCM_56260_A0) 3762 { /* SOC_FORMAT_INT_MMU_ITE_CTRL_0_BCM56260_A0fmt */ 3763 /* format MMU_ITE_CTRL_0fmt */ 3764 /* nFields */ 25, 3765 /* *fields */ soc_MMU_ITE_CTRL_0_BCM56260_A0fmt_fields, 3766 /* bits */ 122, 3767 /* flags */ 0, 3768 }, 3769 #endif /* chips */ 3770 3771 #if defined(BCM_56260_B0) 3772 { /* SOC_FORMAT_INT_MMU_ITE_CTRL_0_BCM56260_B0fmt */ 3773 /* format MMU_ITE_CTRL_0fmt */ 3774 /* nFields */ 25, 3775 /* *fields */ soc_MMU_ITE_CTRL_0_BCM56260_A0fmt_fields, 3776 /* bits */ 122, 3777 /* flags */ 0, 3778 }, 3779 #endif /* chips */ 3780 3781 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 3782 { /* SOC_FORMAT_INT_MMU_ITE_WORK_QUEUEfmt */ 3783 /* format MMU_ITE_WORK_QUEUEfmt */ 3784 /* nFields */ 28, 3785 /* *fields */ soc_MMU_ITE_WORK_QUEUEfmt_fields, 3786 /* bits */ 114, 3787 /* flags */ 0, 3788 }, 3789 #endif /* chips */ 3790 3791 #if defined(BCM_56970_A0) 3792 { /* SOC_FORMAT_INT_MMU_MB_BANK_ADDRfmt */ 3793 /* format MMU_MB_BANK_ADDRfmt */ 3794 /* nFields */ 3, 3795 /* *fields */ soc_MMU_MB_BANK_ADDRfmt_fields, 3796 /* bits */ 8, 3797 /* flags */ 0, 3798 }, 3799 #endif /* chips */ 3800 3801 #if defined(BCM_56370_A0) 3802 { /* SOC_FORMAT_INT_MMU_MB_BANK_ADDR_BCM56370_A0fmt */ 3803 /* format MMU_MB_BANK_ADDRfmt */ 3804 /* nFields */ 3, 3805 /* *fields */ soc_MMU_MB_BANK_ADDR_BCM56870_A0fmt_fields, 3806 /* bits */ 10, 3807 /* flags */ 0, 3808 }, 3809 #endif /* chips */ 3810 3811 #if defined(BCM_56770_A0) 3812 { /* SOC_FORMAT_INT_MMU_MB_BANK_ADDR_BCM56770_A0fmt */ 3813 /* format MMU_MB_BANK_ADDRfmt */ 3814 /* nFields */ 3, 3815 /* *fields */ soc_MMU_MB_BANK_ADDR_BCM56870_A0fmt_fields, 3816 /* bits */ 10, 3817 /* flags */ 0, 3818 }, 3819 #endif /* chips */ 3820 3821 #if defined(BCM_56870_A0) 3822 { /* SOC_FORMAT_INT_MMU_MB_BANK_ADDR_BCM56870_A0fmt */ 3823 /* format MMU_MB_BANK_ADDRfmt */ 3824 /* nFields */ 3, 3825 /* *fields */ soc_MMU_MB_BANK_ADDR_BCM56870_A0fmt_fields, 3826 /* bits */ 10, 3827 /* flags */ 0, 3828 }, 3829 #endif /* chips */ 3830 3831 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3832 { /* SOC_FORMAT_INT_MMU_MB_REMOTE_IFfmt */ 3833 /* format MMU_MB_REMOTE_IFfmt */ 3834 /* nFields */ 4, 3835 /* *fields */ soc_MMU_MB_REMOTE_IFfmt_fields, 3836 /* bits */ 6, 3837 /* flags */ 0, 3838 }, 3839 #endif /* chips */ 3840 3841 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3842 { /* SOC_FORMAT_INT_MMU_MB_TO_EBP_EB_INFOfmt */ 3843 /* format MMU_MB_TO_EBP_EB_INFOfmt */ 3844 /* nFields */ 2, 3845 /* *fields */ soc_MMU_MB_TO_EBP_EB_INFOfmt_fields, 3846 /* bits */ 4, 3847 /* flags */ 0, 3848 }, 3849 #endif /* chips */ 3850 3851 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3852 { /* SOC_FORMAT_INT_MMU_MB_TO_EBP_SLICE_DATAfmt */ 3853 /* format MMU_MB_TO_EBP_SLICE_DATAfmt */ 3854 /* nFields */ 2, 3855 /* *fields */ soc_MMU_MB_TO_EBP_SLICE_DATAfmt_fields, 3856 /* bits */ 257, 3857 /* flags */ 0, 3858 }, 3859 #endif /* chips */ 3860 3861 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 3862 { /* SOC_FORMAT_INT_MMU_MEM_ADDRfmt */ 3863 /* format MMU_MEM_ADDRfmt */ 3864 /* nFields */ 4, 3865 /* *fields */ soc_MMU_MEM_ADDRfmt_fields, 3866 /* bits */ 26, 3867 /* flags */ 0, 3868 }, 3869 #endif /* chips */ 3870 3871 #if defined(BCM_56370_A0) 3872 { /* SOC_FORMAT_INT_MMU_MEM_ADDR_BCM56370_A0fmt */ 3873 /* format MMU_MEM_ADDRfmt */ 3874 /* nFields */ 4, 3875 /* *fields */ soc_MMU_MEM_ADDR_BCM56970_A0fmt_fields, 3876 /* bits */ 26, 3877 /* flags */ 0, 3878 }, 3879 #endif /* chips */ 3880 3881 #if defined(BCM_56770_A0) 3882 { /* SOC_FORMAT_INT_MMU_MEM_ADDR_BCM56770_A0fmt */ 3883 /* format MMU_MEM_ADDRfmt */ 3884 /* nFields */ 4, 3885 /* *fields */ soc_MMU_MEM_ADDR_BCM56970_A0fmt_fields, 3886 /* bits */ 26, 3887 /* flags */ 0, 3888 }, 3889 #endif /* chips */ 3890 3891 #if defined(BCM_56870_A0) 3892 { /* SOC_FORMAT_INT_MMU_MEM_ADDR_BCM56870_A0fmt */ 3893 /* format MMU_MEM_ADDRfmt */ 3894 /* nFields */ 4, 3895 /* *fields */ soc_MMU_MEM_ADDR_BCM56970_A0fmt_fields, 3896 /* bits */ 26, 3897 /* flags */ 0, 3898 }, 3899 #endif /* chips */ 3900 3901 #if defined(BCM_56970_A0) 3902 { /* SOC_FORMAT_INT_MMU_MEM_ADDR_BCM56970_A0fmt */ 3903 /* format MMU_MEM_ADDRfmt */ 3904 /* nFields */ 4, 3905 /* *fields */ soc_MMU_MEM_ADDR_BCM56970_A0fmt_fields, 3906 /* bits */ 26, 3907 /* flags */ 0, 3908 }, 3909 #endif /* chips */ 3910 3911 #if defined(BCM_56980_A0) 3912 { /* SOC_FORMAT_INT_MMU_MEM_ADDR_BCM56980_A0fmt */ 3913 /* format MMU_MEM_ADDRfmt */ 3914 /* nFields */ 5, 3915 /* *fields */ soc_MMU_MEM_ADDR_BCM56980_A0fmt_fields, 3916 /* bits */ 32, 3917 /* flags */ 0, 3918 }, 3919 #endif /* chips */ 3920 3921 #if defined(BCM_56980_B0) 3922 { /* SOC_FORMAT_INT_MMU_MEM_ADDR_BCM56980_B0fmt */ 3923 /* format MMU_MEM_ADDRfmt */ 3924 /* nFields */ 5, 3925 /* *fields */ soc_MMU_MEM_ADDR_BCM56980_A0fmt_fields, 3926 /* bits */ 32, 3927 /* flags */ 0, 3928 }, 3929 #endif /* chips */ 3930 3931 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3932 { /* SOC_FORMAT_INT_MMU_MTRO_TO_QSCH_EP_SHAPE_BUS_INFOfmt */ 3933 /* format MMU_MTRO_TO_QSCH_EP_SHAPE_BUS_INFOfmt */ 3934 /* nFields */ 10, 3935 /* *fields */ soc_MMU_MTRO_TO_QSCH_EP_SHAPE_BUS_INFOfmt_fields, 3936 /* bits */ 30, 3937 /* flags */ 0, 3938 }, 3939 #endif /* chips */ 3940 3941 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3942 { /* SOC_FORMAT_INT_MMU_MTRO_TO_QSCH_L0_PROFILING_UPDATE_INFOfmt */ 3943 /* format MMU_MTRO_TO_QSCH_L0_PROFILING_UPDATE_INFOfmt */ 3944 /* nFields */ 4, 3945 /* *fields */ soc_MMU_MTRO_TO_QSCH_L0_PROFILING_UPDATE_INFOfmt_fields, 3946 /* bits */ 11, 3947 /* flags */ 0, 3948 }, 3949 #endif /* chips */ 3950 3951 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3952 { /* SOC_FORMAT_INT_MMU_MTRO_TO_QSCH_L1_PROFILING_UPDATE_INFOfmt */ 3953 /* format MMU_MTRO_TO_QSCH_L1_PROFILING_UPDATE_INFOfmt */ 3954 /* nFields */ 4, 3955 /* *fields */ soc_MMU_MTRO_TO_QSCH_L1_PROFILING_UPDATE_INFOfmt_fields, 3956 /* bits */ 9, 3957 /* flags */ 0, 3958 }, 3959 #endif /* chips */ 3960 3961 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3962 { /* SOC_FORMAT_INT_MMU_MTRO_TO_QSCH_PORT_PROFILING_UPDATE_INFOfmt */ 3963 /* format MMU_MTRO_TO_QSCH_PORT_PROFILING_UPDATE_INFOfmt */ 3964 /* nFields */ 3, 3965 /* *fields */ soc_MMU_MTRO_TO_QSCH_PORT_PROFILING_UPDATE_INFOfmt_fields, 3966 /* bits */ 7, 3967 /* flags */ 0, 3968 }, 3969 #endif /* chips */ 3970 3971 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 3972 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 3973 defined(BCM_56504_B0) || defined(BCM_56514_A0) 3974 { /* SOC_FORMAT_INT_MMU_NCPHEADERfmt */ 3975 /* format MMU_NCPHEADERfmt */ 3976 /* nFields */ 8, 3977 /* *fields */ soc_MMU_NCPHEADERfmt_fields, 3978 /* bits */ 20, 3979 /* flags */ 0, 3980 }, 3981 #endif /* chips */ 3982 3983 #if defined(BCM_56224_A0) 3984 { /* SOC_FORMAT_INT_MMU_NCPHEADER_BCM56224_A0fmt */ 3985 /* format MMU_NCPHEADERfmt */ 3986 /* nFields */ 8, 3987 /* *fields */ soc_MMU_NCPHEADERfmt_fields, 3988 /* bits */ 20, 3989 /* flags */ 0, 3990 }, 3991 #endif /* chips */ 3992 3993 #if defined(BCM_56224_B0) 3994 { /* SOC_FORMAT_INT_MMU_NCPHEADER_BCM56224_B0fmt */ 3995 /* format MMU_NCPHEADERfmt */ 3996 /* nFields */ 8, 3997 /* *fields */ soc_MMU_NCPHEADERfmt_fields, 3998 /* bits */ 20, 3999 /* flags */ 0, 4000 }, 4001 #endif /* chips */ 4002 4003 #if defined(BCM_56800_A0) 4004 { /* SOC_FORMAT_INT_MMU_NCPHEADER_BCM56800_A0fmt */ 4005 /* format MMU_NCPHEADERfmt */ 4006 /* nFields */ 8, 4007 /* *fields */ soc_MMU_NCPHEADERfmt_fields, 4008 /* bits */ 20, 4009 /* flags */ 0, 4010 }, 4011 #endif /* chips */ 4012 4013 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4014 { /* SOC_FORMAT_INT_MMU_OQS_TO_TOQ_CELL_INFOfmt */ 4015 /* format MMU_OQS_TO_TOQ_CELL_INFOfmt */ 4016 /* nFields */ 39, 4017 /* *fields */ soc_MMU_OQS_TO_TOQ_CELL_INFOfmt_fields, 4018 /* bits */ 97, 4019 /* flags */ 0, 4020 }, 4021 #endif /* chips */ 4022 4023 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 4024 defined(BCM_56680_A0) 4025 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALLfmt */ 4026 /* format MMU_PKTHEADER1_ALLfmt */ 4027 /* nFields */ 10, 4028 /* *fields */ soc_MMU_PKTHEADER1_ALLfmt_fields, 4029 /* bits */ 168, 4030 /* flags */ 0, 4031 }, 4032 #endif /* chips */ 4033 4034 #if defined(BCM_56334_A0) 4035 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56334_A0fmt */ 4036 /* format MMU_PKTHEADER1_ALLfmt */ 4037 /* nFields */ 11, 4038 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56334_A0fmt_fields, 4039 /* bits */ 120, 4040 /* flags */ 0, 4041 }, 4042 #endif /* chips */ 4043 4044 #if defined(BCM_56334_B0) 4045 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56334_B0fmt */ 4046 /* format MMU_PKTHEADER1_ALLfmt */ 4047 /* nFields */ 11, 4048 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56334_A0fmt_fields, 4049 /* bits */ 120, 4050 /* flags */ 0, 4051 }, 4052 #endif /* chips */ 4053 4054 #if defined(BCM_56524_A0) 4055 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56524_A0fmt */ 4056 /* format MMU_PKTHEADER1_ALLfmt */ 4057 /* nFields */ 12, 4058 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56634_A0fmt_fields, 4059 /* bits */ 171, 4060 /* flags */ 0, 4061 }, 4062 #endif /* chips */ 4063 4064 #if defined(BCM_56524_B0) 4065 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56524_B0fmt */ 4066 /* format MMU_PKTHEADER1_ALLfmt */ 4067 /* nFields */ 12, 4068 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56634_A0fmt_fields, 4069 /* bits */ 171, 4070 /* flags */ 0, 4071 }, 4072 #endif /* chips */ 4073 4074 #if defined(BCM_56634_A0) 4075 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56634_A0fmt */ 4076 /* format MMU_PKTHEADER1_ALLfmt */ 4077 /* nFields */ 12, 4078 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56634_A0fmt_fields, 4079 /* bits */ 171, 4080 /* flags */ 0, 4081 }, 4082 #endif /* chips */ 4083 4084 #if defined(BCM_56634_B0) 4085 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56634_B0fmt */ 4086 /* format MMU_PKTHEADER1_ALLfmt */ 4087 /* nFields */ 12, 4088 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56634_A0fmt_fields, 4089 /* bits */ 171, 4090 /* flags */ 0, 4091 }, 4092 #endif /* chips */ 4093 4094 #if defined(BCM_56680_B0) 4095 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56680_B0fmt */ 4096 /* format MMU_PKTHEADER1_ALLfmt */ 4097 /* nFields */ 10, 4098 /* *fields */ soc_MMU_PKTHEADER1_ALLfmt_fields, 4099 /* bits */ 168, 4100 /* flags */ 0, 4101 }, 4102 #endif /* chips */ 4103 4104 #if defined(BCM_56685_A0) 4105 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56685_A0fmt */ 4106 /* format MMU_PKTHEADER1_ALLfmt */ 4107 /* nFields */ 12, 4108 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56634_A0fmt_fields, 4109 /* bits */ 171, 4110 /* flags */ 0, 4111 }, 4112 #endif /* chips */ 4113 4114 #if defined(BCM_56685_B0) 4115 { /* SOC_FORMAT_INT_MMU_PKTHEADER1_ALL_BCM56685_B0fmt */ 4116 /* format MMU_PKTHEADER1_ALLfmt */ 4117 /* nFields */ 12, 4118 /* *fields */ soc_MMU_PKTHEADER1_ALL_BCM56634_A0fmt_fields, 4119 /* bits */ 171, 4120 /* flags */ 0, 4121 }, 4122 #endif /* chips */ 4123 4124 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 4125 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 4126 defined(BCM_56504_B0) || defined(BCM_56514_A0) || \ 4127 defined(BCM_56800_A0) 4128 { /* SOC_FORMAT_INT_MMU_PPPHEADERfmt */ 4129 /* format MMU_PPPHEADERfmt */ 4130 /* nFields */ 8, 4131 /* *fields */ soc_MMU_PPPHEADERfmt_fields, 4132 /* bits */ 23, 4133 /* flags */ 0, 4134 }, 4135 #endif /* chips */ 4136 4137 #if defined(BCM_53314_A0) 4138 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM53314_A0fmt */ 4139 /* format MMU_PPPHEADERfmt */ 4140 /* nFields */ 8, 4141 /* *fields */ soc_MMU_PPPHEADER_BCM53314_A0fmt_fields, 4142 /* bits */ 21, 4143 /* flags */ 0, 4144 }, 4145 #endif /* chips */ 4146 4147 #if defined(BCM_53324_A0) 4148 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM53324_A0fmt */ 4149 /* format MMU_PPPHEADERfmt */ 4150 /* nFields */ 8, 4151 /* *fields */ soc_MMU_PPPHEADER_BCM53314_A0fmt_fields, 4152 /* bits */ 21, 4153 /* flags */ 0, 4154 }, 4155 #endif /* chips */ 4156 4157 #if defined(BCM_53400_A0) 4158 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM53400_A0fmt */ 4159 /* format MMU_PPPHEADERfmt */ 4160 /* nFields */ 8, 4161 /* *fields */ soc_MMU_PPPHEADER_BCM53400_A0fmt_fields, 4162 /* bits */ 23, 4163 /* flags */ 0, 4164 }, 4165 #endif /* chips */ 4166 4167 #if defined(BCM_53540_A0) 4168 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM53540_A0fmt */ 4169 /* format MMU_PPPHEADERfmt */ 4170 /* nFields */ 10, 4171 /* *fields */ soc_MMU_PPPHEADER_BCM53540_A0fmt_fields, 4172 /* bits */ 21, 4173 /* flags */ 0, 4174 }, 4175 #endif /* chips */ 4176 4177 #if defined(BCM_53570_A0) 4178 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM53570_A0fmt */ 4179 /* format MMU_PPPHEADERfmt */ 4180 /* nFields */ 10, 4181 /* *fields */ soc_MMU_PPPHEADER_BCM53570_A0fmt_fields, 4182 /* bits */ 27, 4183 /* flags */ 0, 4184 }, 4185 #endif /* chips */ 4186 4187 #if defined(BCM_53570_B0) 4188 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM53570_B0fmt */ 4189 /* format MMU_PPPHEADERfmt */ 4190 /* nFields */ 10, 4191 /* *fields */ soc_MMU_PPPHEADER_BCM53570_A0fmt_fields, 4192 /* bits */ 27, 4193 /* flags */ 0, 4194 }, 4195 #endif /* chips */ 4196 4197 #if defined(BCM_56142_A0) 4198 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM56142_A0fmt */ 4199 /* format MMU_PPPHEADERfmt */ 4200 /* nFields */ 8, 4201 /* *fields */ soc_MMU_PPPHEADERfmt_fields, 4202 /* bits */ 23, 4203 /* flags */ 0, 4204 }, 4205 #endif /* chips */ 4206 4207 #if defined(BCM_56150_A0) 4208 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM56150_A0fmt */ 4209 /* format MMU_PPPHEADERfmt */ 4210 /* nFields */ 8, 4211 /* *fields */ soc_MMU_PPPHEADER_BCM56150_A0fmt_fields, 4212 /* bits */ 23, 4213 /* flags */ 0, 4214 }, 4215 #endif /* chips */ 4216 4217 #if defined(BCM_56160_A0) 4218 { /* SOC_FORMAT_INT_MMU_PPPHEADER_BCM56160_A0fmt */ 4219 /* format MMU_PPPHEADERfmt */ 4220 /* nFields */ 10, 4221 /* *fields */ soc_MMU_PPPHEADER_BCM56160_A0fmt_fields, 4222 /* bits */ 23, 4223 /* flags */ 0, 4224 }, 4225 #endif /* chips */ 4226 4227 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4228 { /* SOC_FORMAT_INT_MMU_PPSCH_TO_PTSCH_PICK_INFOfmt */ 4229 /* format MMU_PPSCH_TO_PTSCH_PICK_INFOfmt */ 4230 /* nFields */ 5, 4231 /* *fields */ soc_MMU_PPSCH_TO_PTSCH_PICK_INFOfmt_fields, 4232 /* bits */ 16, 4233 /* flags */ 0, 4234 }, 4235 #endif /* chips */ 4236 4237 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4238 { /* SOC_FORMAT_INT_MMU_PPSCH_TO_QSCH_PICK_INFOfmt */ 4239 /* format MMU_PPSCH_TO_QSCH_PICK_INFOfmt */ 4240 /* nFields */ 3, 4241 /* *fields */ soc_MMU_PPSCH_TO_QSCH_PICK_INFOfmt_fields, 4242 /* bits */ 5, 4243 /* flags */ 0, 4244 }, 4245 #endif /* chips */ 4246 4247 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4248 { /* SOC_FORMAT_INT_MMU_PPSCH_TO_QSCH_Q_MAP_INFOfmt */ 4249 /* format MMU_PPSCH_TO_QSCH_Q_MAP_INFOfmt */ 4250 /* nFields */ 4, 4251 /* *fields */ soc_MMU_PPSCH_TO_QSCH_Q_MAP_INFOfmt_fields, 4252 /* bits */ 13, 4253 /* flags */ 0, 4254 }, 4255 #endif /* chips */ 4256 4257 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4258 { /* SOC_FORMAT_INT_MMU_PPSCH_TO_TOQ_DEQ_INFOfmt */ 4259 /* format MMU_PPSCH_TO_TOQ_DEQ_INFOfmt */ 4260 /* nFields */ 7, 4261 /* *fields */ soc_MMU_PPSCH_TO_TOQ_DEQ_INFOfmt_fields, 4262 /* bits */ 20, 4263 /* flags */ 0, 4264 }, 4265 #endif /* chips */ 4266 4267 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4268 { /* SOC_FORMAT_INT_MMU_PTSCH_TO_PPSCH_PICK_INFOfmt */ 4269 /* format MMU_PTSCH_TO_PPSCH_PICK_INFOfmt */ 4270 /* nFields */ 19, 4271 /* *fields */ soc_MMU_PTSCH_TO_PPSCH_PICK_INFOfmt_fields, 4272 /* bits */ 42, 4273 /* flags */ 0, 4274 }, 4275 #endif /* chips */ 4276 4277 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4278 { /* SOC_FORMAT_INT_MMU_QSCH_TO_PTSCH_PORT_DEQ_STATEfmt */ 4279 /* format MMU_QSCH_TO_PTSCH_PORT_DEQ_STATEfmt */ 4280 /* nFields */ 2, 4281 /* *fields */ soc_MMU_QSCH_TO_PTSCH_PORT_DEQ_STATEfmt_fields, 4282 /* bits */ 38, 4283 /* flags */ 0, 4284 }, 4285 #endif /* chips */ 4286 4287 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4288 { /* SOC_FORMAT_INT_MMU_QSCH_TO_PTSCH_QUEUE_PICK_INFOfmt */ 4289 /* format MMU_QSCH_TO_PTSCH_QUEUE_PICK_INFOfmt */ 4290 /* nFields */ 16, 4291 /* *fields */ soc_MMU_QSCH_TO_PTSCH_QUEUE_PICK_INFOfmt_fields, 4292 /* bits */ 33, 4293 /* flags */ 0, 4294 }, 4295 #endif /* chips */ 4296 4297 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4298 { /* SOC_FORMAT_INT_MMU_QSCH_TO_THDO_VOQ_FAIRNESS_INFOfmt */ 4299 /* format MMU_QSCH_TO_THDO_VOQ_FAIRNESS_INFOfmt */ 4300 /* nFields */ 4, 4301 /* *fields */ soc_MMU_QSCH_TO_THDO_VOQ_FAIRNESS_INFOfmt_fields, 4302 /* bits */ 15, 4303 /* flags */ 0, 4304 }, 4305 #endif /* chips */ 4306 4307 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 4308 defined(BCM_56450_B1) 4309 { /* SOC_FORMAT_INT_MMU_QSTRUCT_EOP_BLOCKfmt */ 4310 /* format MMU_QSTRUCT_EOP_BLOCKfmt */ 4311 /* nFields */ 12, 4312 /* *fields */ soc_MMU_QSTRUCT_EOP_BLOCKfmt_fields, 4313 /* bits */ 48, 4314 /* flags */ 0, 4315 }, 4316 #endif /* chips */ 4317 4318 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 4319 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QBLOCK_NEXTfmt */ 4320 /* format MMU_QSTRUCT_QBLOCK_NEXTfmt */ 4321 /* nFields */ 5, 4322 /* *fields */ soc_MMU_QSTRUCT_QBLOCK_NEXTfmt_fields, 4323 /* bits */ 23, 4324 /* flags */ 0, 4325 }, 4326 #endif /* chips */ 4327 4328 #if defined(BCM_56450_A0) 4329 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QBLOCK_NEXT_BCM56450_A0fmt */ 4330 /* format MMU_QSTRUCT_QBLOCK_NEXTfmt */ 4331 /* nFields */ 5, 4332 /* *fields */ soc_MMU_QSTRUCT_QBLOCK_NEXT_BCM56450_A0fmt_fields, 4333 /* bits */ 23, 4334 /* flags */ 0, 4335 }, 4336 #endif /* chips */ 4337 4338 #if defined(BCM_56450_B0) 4339 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QBLOCK_NEXT_BCM56450_B0fmt */ 4340 /* format MMU_QSTRUCT_QBLOCK_NEXTfmt */ 4341 /* nFields */ 5, 4342 /* *fields */ soc_MMU_QSTRUCT_QBLOCK_NEXT_BCM56450_A0fmt_fields, 4343 /* bits */ 23, 4344 /* flags */ 0, 4345 }, 4346 #endif /* chips */ 4347 4348 #if defined(BCM_56450_B1) 4349 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QBLOCK_NEXT_BCM56450_B1fmt */ 4350 /* format MMU_QSTRUCT_QBLOCK_NEXTfmt */ 4351 /* nFields */ 5, 4352 /* *fields */ soc_MMU_QSTRUCT_QBLOCK_NEXT_BCM56450_A0fmt_fields, 4353 /* bits */ 23, 4354 /* flags */ 0, 4355 }, 4356 #endif /* chips */ 4357 4358 #if defined(BCM_56440_A0) 4359 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QENTRYfmt */ 4360 /* format MMU_QSTRUCT_QENTRYfmt */ 4361 /* nFields */ 20, 4362 /* *fields */ soc_MMU_QSTRUCT_QENTRYfmt_fields, 4363 /* bits */ 52, 4364 /* flags */ 0, 4365 }, 4366 #endif /* chips */ 4367 4368 #if defined(BCM_56440_B0) 4369 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QENTRY_BCM56440_B0fmt */ 4370 /* format MMU_QSTRUCT_QENTRYfmt */ 4371 /* nFields */ 20, 4372 /* *fields */ soc_MMU_QSTRUCT_QENTRYfmt_fields, 4373 /* bits */ 52, 4374 /* flags */ 0, 4375 }, 4376 #endif /* chips */ 4377 4378 #if defined(BCM_56450_A0) 4379 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QENTRY_BCM56450_A0fmt */ 4380 /* format MMU_QSTRUCT_QENTRYfmt */ 4381 /* nFields */ 19, 4382 /* *fields */ soc_MMU_QSTRUCT_QENTRY_BCM56450_A0fmt_fields, 4383 /* bits */ 43, 4384 /* flags */ 0, 4385 }, 4386 #endif /* chips */ 4387 4388 #if defined(BCM_56450_B0) 4389 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QENTRY_BCM56450_B0fmt */ 4390 /* format MMU_QSTRUCT_QENTRYfmt */ 4391 /* nFields */ 19, 4392 /* *fields */ soc_MMU_QSTRUCT_QENTRY_BCM56450_A0fmt_fields, 4393 /* bits */ 43, 4394 /* flags */ 0, 4395 }, 4396 #endif /* chips */ 4397 4398 #if defined(BCM_56450_B1) 4399 { /* SOC_FORMAT_INT_MMU_QSTRUCT_QENTRY_BCM56450_B1fmt */ 4400 /* format MMU_QSTRUCT_QENTRYfmt */ 4401 /* nFields */ 19, 4402 /* *fields */ soc_MMU_QSTRUCT_QENTRY_BCM56450_A0fmt_fields, 4403 /* bits */ 43, 4404 /* flags */ 0, 4405 }, 4406 #endif /* chips */ 4407 4408 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4409 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4410 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 4411 defined(BCM_56980_A0) || defined(BCM_56980_B0) 4412 { /* SOC_FORMAT_INT_MMU_REG_ADDRfmt */ 4413 /* format MMU_REG_ADDRfmt */ 4414 /* nFields */ 3, 4415 /* *fields */ soc_MMU_REG_ADDRfmt_fields, 4416 /* bits */ 26, 4417 /* flags */ 0, 4418 }, 4419 #endif /* chips */ 4420 4421 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4422 { /* SOC_FORMAT_INT_MMU_RL_TO_CCP_CELL_INFOfmt */ 4423 /* format MMU_RL_TO_CCP_CELL_INFOfmt */ 4424 /* nFields */ 12, 4425 /* *fields */ soc_MMU_RL_TO_CCP_CELL_INFOfmt_fields, 4426 /* bits */ 44, 4427 /* flags */ 0, 4428 }, 4429 #endif /* chips */ 4430 4431 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4432 { /* SOC_FORMAT_INT_MMU_RL_TO_CCP_RQE_INFOfmt */ 4433 /* format MMU_RL_TO_CCP_RQE_INFOfmt */ 4434 /* nFields */ 1, 4435 /* *fields */ soc_MMU_RL_TO_CCP_RQE_INFOfmt_fields, 4436 /* bits */ 50, 4437 /* flags */ 0, 4438 }, 4439 #endif /* chips */ 4440 4441 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4442 { /* SOC_FORMAT_INT_MMU_RL_TO_CFAP_CELL_INFOfmt */ 4443 /* format MMU_RL_TO_CFAP_CELL_INFOfmt */ 4444 /* nFields */ 3, 4445 /* *fields */ soc_MMU_RL_TO_CFAP_CELL_INFOfmt_fields, 4446 /* bits */ 8, 4447 /* flags */ 0, 4448 }, 4449 #endif /* chips */ 4450 4451 #if defined(BCM_56980_A0) 4452 { /* SOC_FORMAT_INT_MMU_RL_TO_EBCFP_CTRL_DELAYfmt */ 4453 /* format MMU_RL_TO_EBCFP_CTRL_DELAYfmt */ 4454 /* nFields */ 1, 4455 /* *fields */ soc_MMU_EB_MIN_DEQUEUE_DELAYfmt_fields, 4456 /* bits */ 6, 4457 /* flags */ 0, 4458 }, 4459 #endif /* chips */ 4460 4461 #if defined(BCM_56980_B0) 4462 { /* SOC_FORMAT_INT_MMU_RL_TO_EBCFP_CTRL_DELAY_BCM56980_B0fmt */ 4463 /* format MMU_RL_TO_EBCFP_CTRL_DELAYfmt */ 4464 /* nFields */ 1, 4465 /* *fields */ soc_MMU_EB_MIN_DEQUEUE_DELAYfmt_fields, 4466 /* bits */ 6, 4467 /* flags */ 0, 4468 }, 4469 #endif /* chips */ 4470 4471 #if defined(BCM_56980_A0) 4472 { /* SOC_FORMAT_INT_MMU_RL_TO_EBMB_DATA_DELAYfmt */ 4473 /* format MMU_RL_TO_EBMB_DATA_DELAYfmt */ 4474 /* nFields */ 1, 4475 /* *fields */ soc_MMU_EB_MIN_DEQUEUE_DELAYfmt_fields, 4476 /* bits */ 6, 4477 /* flags */ 0, 4478 }, 4479 #endif /* chips */ 4480 4481 #if defined(BCM_56980_B0) 4482 { /* SOC_FORMAT_INT_MMU_RL_TO_EBMB_DATA_DELAY_BCM56980_B0fmt */ 4483 /* format MMU_RL_TO_EBMB_DATA_DELAYfmt */ 4484 /* nFields */ 1, 4485 /* *fields */ soc_MMU_EB_MIN_DEQUEUE_DELAYfmt_fields, 4486 /* bits */ 6, 4487 /* flags */ 0, 4488 }, 4489 #endif /* chips */ 4490 4491 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4492 { /* SOC_FORMAT_INT_MMU_RL_TO_EBPR_CCBE_INFOfmt */ 4493 /* format MMU_RL_TO_EBPR_CCBE_INFOfmt */ 4494 /* nFields */ 3, 4495 /* *fields */ soc_MMU_RL_TO_EBPR_CCBE_INFOfmt_fields, 4496 /* bits */ 104, 4497 /* flags */ 0, 4498 }, 4499 #endif /* chips */ 4500 4501 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4502 { /* SOC_FORMAT_INT_MMU_RL_TO_MB_CELL_INFOfmt */ 4503 /* format MMU_RL_TO_MB_CELL_INFOfmt */ 4504 /* nFields */ 5, 4505 /* *fields */ soc_MMU_RL_TO_MB_CELL_INFOfmt_fields, 4506 /* bits */ 31, 4507 /* flags */ 0, 4508 }, 4509 #endif /* chips */ 4510 4511 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4512 { /* SOC_FORMAT_INT_MMU_RL_TO_PPSCH_CREDIT_RTN_INFOfmt */ 4513 /* format MMU_RL_TO_PPSCH_CREDIT_RTN_INFOfmt */ 4514 /* nFields */ 2, 4515 /* *fields */ soc_MMU_RL_TO_PPSCH_CREDIT_RTN_INFOfmt_fields, 4516 /* bits */ 2, 4517 /* flags */ 0, 4518 }, 4519 #endif /* chips */ 4520 4521 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4522 { /* SOC_FORMAT_INT_MMU_RL_TO_RQE_CREDIT_RTN_INFOfmt */ 4523 /* format MMU_RL_TO_RQE_CREDIT_RTN_INFOfmt */ 4524 /* nFields */ 2, 4525 /* *fields */ soc_MMU_RL_TO_RQE_CREDIT_RTN_INFOfmt_fields, 4526 /* bits */ 3, 4527 /* flags */ 0, 4528 }, 4529 #endif /* chips */ 4530 4531 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4532 { /* SOC_FORMAT_INT_MMU_RQE_CELLQ_FIELDfmt */ 4533 /* format MMU_RQE_CELLQ_FIELDfmt */ 4534 /* nFields */ 4, 4535 /* *fields */ soc_MMU_RQE_CELLQ_FIELDfmt_fields, 4536 /* bits */ 22, 4537 /* flags */ 0, 4538 }, 4539 #endif /* chips */ 4540 4541 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4542 { /* SOC_FORMAT_INT_MMU_RQE_INFOTBL_FP_INIT_STATEfmt */ 4543 /* format MMU_RQE_INFOTBL_FP_INIT_STATEfmt */ 4544 /* nFields */ 2, 4545 /* *fields */ soc_MMU_RQE_INFOTBL_FP_INIT_STATEfmt_fields, 4546 /* bits */ 3, 4547 /* flags */ 0, 4548 }, 4549 #endif /* chips */ 4550 4551 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4552 { /* SOC_FORMAT_INT_MMU_RQE_META_DATA_INfmt */ 4553 /* format MMU_RQE_META_DATA_INfmt */ 4554 /* nFields */ 19, 4555 /* *fields */ soc_MMU_RQE_META_DATA_INfmt_fields, 4556 /* bits */ 85, 4557 /* flags */ 0, 4558 }, 4559 #endif /* chips */ 4560 4561 #if defined(BCM_56370_A0) 4562 { /* SOC_FORMAT_INT_MMU_RQE_META_DATA_IN_BCM56370_A0fmt */ 4563 /* format MMU_RQE_META_DATA_INfmt */ 4564 /* nFields */ 20, 4565 /* *fields */ soc_MMU_RQE_META_DATA_IN_BCM56370_A0fmt_fields, 4566 /* bits */ 88, 4567 /* flags */ 0, 4568 }, 4569 #endif /* chips */ 4570 4571 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4572 { /* SOC_FORMAT_INT_MMU_RQE_META_DATA_OUTfmt */ 4573 /* format MMU_RQE_META_DATA_OUTfmt */ 4574 /* nFields */ 18, 4575 /* *fields */ soc_MMU_RQE_META_DATA_OUTfmt_fields, 4576 /* bits */ 90, 4577 /* flags */ 0, 4578 }, 4579 #endif /* chips */ 4580 4581 #if defined(BCM_56370_A0) 4582 { /* SOC_FORMAT_INT_MMU_RQE_META_DATA_OUT_BCM56370_A0fmt */ 4583 /* format MMU_RQE_META_DATA_OUTfmt */ 4584 /* nFields */ 18, 4585 /* *fields */ soc_MMU_RQE_META_DATA_OUT_BCM56370_A0fmt_fields, 4586 /* bits */ 85, 4587 /* flags */ 0, 4588 }, 4589 #endif /* chips */ 4590 4591 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4592 { /* SOC_FORMAT_INT_MMU_RQE_NEW_BMfmt */ 4593 /* format MMU_RQE_NEW_BMfmt */ 4594 /* nFields */ 6, 4595 /* *fields */ soc_MMU_RQE_NEW_BMfmt_fields, 4596 /* bits */ 134, 4597 /* flags */ 0, 4598 }, 4599 #endif /* chips */ 4600 4601 #if defined(BCM_56370_A0) 4602 { /* SOC_FORMAT_INT_MMU_RQE_NEW_BM_BCM56370_A0fmt */ 4603 /* format MMU_RQE_NEW_BMfmt */ 4604 /* nFields */ 6, 4605 /* *fields */ soc_MMU_RQE_NEW_BM_BCM56370_A0fmt_fields, 4606 /* bits */ 73, 4607 /* flags */ 0, 4608 }, 4609 #endif /* chips */ 4610 4611 #if defined(BCM_56970_A0) 4612 { /* SOC_FORMAT_INT_MMU_RQE_PIPE_OUT_DATAfmt */ 4613 /* format MMU_RQE_PIPE_OUT_DATAfmt */ 4614 /* nFields */ 23, 4615 /* *fields */ soc_MMU_RQE_PIPE_OUT_DATAfmt_fields, 4616 /* bits */ 91, 4617 /* flags */ 0, 4618 }, 4619 #endif /* chips */ 4620 4621 #if defined(BCM_56370_A0) 4622 { /* SOC_FORMAT_INT_MMU_RQE_PIPE_OUT_DATA_BCM56370_A0fmt */ 4623 /* format MMU_RQE_PIPE_OUT_DATAfmt */ 4624 /* nFields */ 23, 4625 /* *fields */ soc_MMU_RQE_PIPE_OUT_DATA_BCM56370_A0fmt_fields, 4626 /* bits */ 93, 4627 /* flags */ 0, 4628 }, 4629 #endif /* chips */ 4630 4631 #if defined(BCM_56770_A0) 4632 { /* SOC_FORMAT_INT_MMU_RQE_PIPE_OUT_DATA_BCM56770_A0fmt */ 4633 /* format MMU_RQE_PIPE_OUT_DATAfmt */ 4634 /* nFields */ 23, 4635 /* *fields */ soc_MMU_RQE_PIPE_OUT_DATA_BCM56870_A0fmt_fields, 4636 /* bits */ 98, 4637 /* flags */ 0, 4638 }, 4639 #endif /* chips */ 4640 4641 #if defined(BCM_56870_A0) 4642 { /* SOC_FORMAT_INT_MMU_RQE_PIPE_OUT_DATA_BCM56870_A0fmt */ 4643 /* format MMU_RQE_PIPE_OUT_DATAfmt */ 4644 /* nFields */ 23, 4645 /* *fields */ soc_MMU_RQE_PIPE_OUT_DATA_BCM56870_A0fmt_fields, 4646 /* bits */ 98, 4647 /* flags */ 0, 4648 }, 4649 #endif /* chips */ 4650 4651 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4652 { /* SOC_FORMAT_INT_MMU_RQE_PKTQ_FIELDfmt */ 4653 /* format MMU_RQE_PKTQ_FIELDfmt */ 4654 /* nFields */ 17, 4655 /* *fields */ soc_MMU_RQE_PKTQ_FIELDfmt_fields, 4656 /* bits */ 73, 4657 /* flags */ 0, 4658 }, 4659 #endif /* chips */ 4660 4661 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4662 { /* SOC_FORMAT_INT_MMU_RQE_REPENG_DATAfmt */ 4663 /* format MMU_RQE_REPENG_DATAfmt */ 4664 /* nFields */ 4, 4665 /* *fields */ soc_MMU_RQE_REPENG_DATAfmt_fields, 4666 /* bits */ 374, 4667 /* flags */ 0, 4668 }, 4669 #endif /* chips */ 4670 4671 #if defined(BCM_56370_A0) 4672 { /* SOC_FORMAT_INT_MMU_RQE_REPENG_DATA_BCM56370_A0fmt */ 4673 /* format MMU_RQE_REPENG_DATAfmt */ 4674 /* nFields */ 4, 4675 /* *fields */ soc_MMU_RQE_REPENG_DATA_BCM56370_A0fmt_fields, 4676 /* bits */ 253, 4677 /* flags */ 0, 4678 }, 4679 #endif /* chips */ 4680 4681 #if defined(BCM_56970_A0) 4682 { /* SOC_FORMAT_INT_MMU_RQE_TOQ_DATAfmt */ 4683 /* format MMU_RQE_TOQ_DATAfmt */ 4684 /* nFields */ 14, 4685 /* *fields */ soc_MMU_RQE_TOQ_DATAfmt_fields, 4686 /* bits */ 58, 4687 /* flags */ 0, 4688 }, 4689 #endif /* chips */ 4690 4691 #if defined(BCM_56370_A0) 4692 { /* SOC_FORMAT_INT_MMU_RQE_TOQ_DATA_BCM56370_A0fmt */ 4693 /* format MMU_RQE_TOQ_DATAfmt */ 4694 /* nFields */ 14, 4695 /* *fields */ soc_MMU_RQE_TOQ_DATA_BCM56370_A0fmt_fields, 4696 /* bits */ 59, 4697 /* flags */ 0, 4698 }, 4699 #endif /* chips */ 4700 4701 #if defined(BCM_56770_A0) 4702 { /* SOC_FORMAT_INT_MMU_RQE_TOQ_DATA_BCM56770_A0fmt */ 4703 /* format MMU_RQE_TOQ_DATAfmt */ 4704 /* nFields */ 14, 4705 /* *fields */ soc_MMU_RQE_TOQ_DATA_BCM56870_A0fmt_fields, 4706 /* bits */ 63, 4707 /* flags */ 0, 4708 }, 4709 #endif /* chips */ 4710 4711 #if defined(BCM_56870_A0) 4712 { /* SOC_FORMAT_INT_MMU_RQE_TOQ_DATA_BCM56870_A0fmt */ 4713 /* format MMU_RQE_TOQ_DATAfmt */ 4714 /* nFields */ 14, 4715 /* *fields */ soc_MMU_RQE_TOQ_DATA_BCM56870_A0fmt_fields, 4716 /* bits */ 63, 4717 /* flags */ 0, 4718 }, 4719 #endif /* chips */ 4720 4721 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4722 { /* SOC_FORMAT_INT_MMU_RQE_TO_CRB_CELL_INFOfmt */ 4723 /* format MMU_RQE_TO_CRB_CELL_INFOfmt */ 4724 /* nFields */ 4, 4725 /* *fields */ soc_MMU_RQE_TO_CRB_CELL_INFOfmt_fields, 4726 /* bits */ 23, 4727 /* flags */ 0, 4728 }, 4729 #endif /* chips */ 4730 4731 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4732 { /* SOC_FORMAT_INT_MMU_RQE_TO_CRB_ICC_INFOfmt */ 4733 /* format MMU_RQE_TO_CRB_ICC_INFOfmt */ 4734 /* nFields */ 3, 4735 /* *fields */ soc_MMU_RQE_TO_CRB_ICC_INFOfmt_fields, 4736 /* bits */ 18, 4737 /* flags */ 0, 4738 }, 4739 #endif /* chips */ 4740 4741 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4742 { /* SOC_FORMAT_INT_MMU_RQE_TO_CRB_PKT_INFOfmt */ 4743 /* format MMU_RQE_TO_CRB_PKT_INFOfmt */ 4744 /* nFields */ 20, 4745 /* *fields */ soc_MMU_RQE_TO_CRB_PKT_INFOfmt_fields, 4746 /* bits */ 74, 4747 /* flags */ 0, 4748 }, 4749 #endif /* chips */ 4750 4751 #if defined(BCM_56970_A0) 4752 { /* SOC_FORMAT_INT_MMU_RQE_TO_CTR_DATAfmt */ 4753 /* format MMU_RQE_TO_CTR_DATAfmt */ 4754 /* nFields */ 5, 4755 /* *fields */ soc_MMU_RQE_TO_CTR_DATAfmt_fields, 4756 /* bits */ 32, 4757 /* flags */ 0, 4758 }, 4759 #endif /* chips */ 4760 4761 #if defined(BCM_56370_A0) 4762 { /* SOC_FORMAT_INT_MMU_RQE_TO_CTR_DATA_BCM56370_A0fmt */ 4763 /* format MMU_RQE_TO_CTR_DATAfmt */ 4764 /* nFields */ 5, 4765 /* *fields */ soc_MMU_RQE_TO_CTR_DATA_BCM56870_A0fmt_fields, 4766 /* bits */ 34, 4767 /* flags */ 0, 4768 }, 4769 #endif /* chips */ 4770 4771 #if defined(BCM_56770_A0) 4772 { /* SOC_FORMAT_INT_MMU_RQE_TO_CTR_DATA_BCM56770_A0fmt */ 4773 /* format MMU_RQE_TO_CTR_DATAfmt */ 4774 /* nFields */ 5, 4775 /* *fields */ soc_MMU_RQE_TO_CTR_DATA_BCM56870_A0fmt_fields, 4776 /* bits */ 34, 4777 /* flags */ 0, 4778 }, 4779 #endif /* chips */ 4780 4781 #if defined(BCM_56870_A0) 4782 { /* SOC_FORMAT_INT_MMU_RQE_TO_CTR_DATA_BCM56870_A0fmt */ 4783 /* format MMU_RQE_TO_CTR_DATAfmt */ 4784 /* nFields */ 5, 4785 /* *fields */ soc_MMU_RQE_TO_CTR_DATA_BCM56870_A0fmt_fields, 4786 /* bits */ 34, 4787 /* flags */ 0, 4788 }, 4789 #endif /* chips */ 4790 4791 #if defined(BCM_56970_A0) 4792 { /* SOC_FORMAT_INT_MMU_RQE_TO_ENQ_DATAfmt */ 4793 /* format MMU_RQE_TO_ENQ_DATAfmt */ 4794 /* nFields */ 2, 4795 /* *fields */ soc_MMU_RQE_TO_ENQ_DATAfmt_fields, 4796 /* bits */ 7, 4797 /* flags */ 0, 4798 }, 4799 #endif /* chips */ 4800 4801 #if defined(BCM_56370_A0) 4802 { /* SOC_FORMAT_INT_MMU_RQE_TO_ENQ_DATA_BCM56370_A0fmt */ 4803 /* format MMU_RQE_TO_ENQ_DATAfmt */ 4804 /* nFields */ 4, 4805 /* *fields */ soc_MMU_RQE_TO_ENQ_DATA_BCM56870_A0fmt_fields, 4806 /* bits */ 13, 4807 /* flags */ 0, 4808 }, 4809 #endif /* chips */ 4810 4811 #if defined(BCM_56770_A0) 4812 { /* SOC_FORMAT_INT_MMU_RQE_TO_ENQ_DATA_BCM56770_A0fmt */ 4813 /* format MMU_RQE_TO_ENQ_DATAfmt */ 4814 /* nFields */ 4, 4815 /* *fields */ soc_MMU_RQE_TO_ENQ_DATA_BCM56870_A0fmt_fields, 4816 /* bits */ 13, 4817 /* flags */ 0, 4818 }, 4819 #endif /* chips */ 4820 4821 #if defined(BCM_56870_A0) 4822 { /* SOC_FORMAT_INT_MMU_RQE_TO_ENQ_DATA_BCM56870_A0fmt */ 4823 /* format MMU_RQE_TO_ENQ_DATAfmt */ 4824 /* nFields */ 4, 4825 /* *fields */ soc_MMU_RQE_TO_ENQ_DATA_BCM56870_A0fmt_fields, 4826 /* bits */ 13, 4827 /* flags */ 0, 4828 }, 4829 #endif /* chips */ 4830 4831 #if defined(BCM_56370_A0) || defined(BCM_56970_A0) 4832 { /* SOC_FORMAT_INT_MMU_RQE_TO_EPRG_DATAfmt */ 4833 /* format MMU_RQE_TO_EPRG_DATAfmt */ 4834 /* nFields */ 4, 4835 /* *fields */ soc_MMU_RQE_TO_EPRG_DATAfmt_fields, 4836 /* bits */ 22, 4837 /* flags */ 0, 4838 }, 4839 #endif /* chips */ 4840 4841 #if defined(BCM_56770_A0) 4842 { /* SOC_FORMAT_INT_MMU_RQE_TO_EPRG_DATA_BCM56770_A0fmt */ 4843 /* format MMU_RQE_TO_EPRG_DATAfmt */ 4844 /* nFields */ 4, 4845 /* *fields */ soc_MMU_RQE_TO_EPRG_DATA_BCM56870_A0fmt_fields, 4846 /* bits */ 24, 4847 /* flags */ 0, 4848 }, 4849 #endif /* chips */ 4850 4851 #if defined(BCM_56870_A0) 4852 { /* SOC_FORMAT_INT_MMU_RQE_TO_EPRG_DATA_BCM56870_A0fmt */ 4853 /* format MMU_RQE_TO_EPRG_DATAfmt */ 4854 /* nFields */ 4, 4855 /* *fields */ soc_MMU_RQE_TO_EPRG_DATA_BCM56870_A0fmt_fields, 4856 /* bits */ 24, 4857 /* flags */ 0, 4858 }, 4859 #endif /* chips */ 4860 4861 #if defined(BCM_56970_A0) 4862 { /* SOC_FORMAT_INT_MMU_RQE_TO_PORTCNT_DATAfmt */ 4863 /* format MMU_RQE_TO_PORTCNT_DATAfmt */ 4864 /* nFields */ 3, 4865 /* *fields */ soc_MMU_RQE_TO_PORTCNT_DATAfmt_fields, 4866 /* bits */ 28, 4867 /* flags */ 0, 4868 }, 4869 #endif /* chips */ 4870 4871 #if defined(BCM_56370_A0) 4872 { /* SOC_FORMAT_INT_MMU_RQE_TO_PORTCNT_DATA_BCM56370_A0fmt */ 4873 /* format MMU_RQE_TO_PORTCNT_DATAfmt */ 4874 /* nFields */ 3, 4875 /* *fields */ soc_MMU_RQE_TO_PORTCNT_DATA_BCM56870_A0fmt_fields, 4876 /* bits */ 31, 4877 /* flags */ 0, 4878 }, 4879 #endif /* chips */ 4880 4881 #if defined(BCM_56770_A0) 4882 { /* SOC_FORMAT_INT_MMU_RQE_TO_PORTCNT_DATA_BCM56770_A0fmt */ 4883 /* format MMU_RQE_TO_PORTCNT_DATAfmt */ 4884 /* nFields */ 3, 4885 /* *fields */ soc_MMU_RQE_TO_PORTCNT_DATA_BCM56870_A0fmt_fields, 4886 /* bits */ 31, 4887 /* flags */ 0, 4888 }, 4889 #endif /* chips */ 4890 4891 #if defined(BCM_56870_A0) 4892 { /* SOC_FORMAT_INT_MMU_RQE_TO_PORTCNT_DATA_BCM56870_A0fmt */ 4893 /* format MMU_RQE_TO_PORTCNT_DATAfmt */ 4894 /* nFields */ 3, 4895 /* *fields */ soc_MMU_RQE_TO_PORTCNT_DATA_BCM56870_A0fmt_fields, 4896 /* bits */ 31, 4897 /* flags */ 0, 4898 }, 4899 #endif /* chips */ 4900 4901 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4902 { /* SOC_FORMAT_INT_MMU_RQE_TO_RL_COPYCNT_INFOfmt */ 4903 /* format MMU_RQE_TO_RL_COPYCNT_INFOfmt */ 4904 /* nFields */ 12, 4905 /* *fields */ soc_MMU_RQE_TO_RL_COPYCNT_INFOfmt_fields, 4906 /* bits */ 50, 4907 /* flags */ 0, 4908 }, 4909 #endif /* chips */ 4910 4911 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4912 { /* SOC_FORMAT_INT_MMU_RQE_TO_THDO_ENQCHK_PKT_INFOfmt */ 4913 /* format MMU_RQE_TO_THDO_ENQCHK_PKT_INFOfmt */ 4914 /* nFields */ 17, 4915 /* *fields */ soc_MMU_RQE_TO_THDO_ENQCHK_PKT_INFOfmt_fields, 4916 /* bits */ 68, 4917 /* flags */ 0, 4918 }, 4919 #endif /* chips */ 4920 4921 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4922 defined(BCM_56870_A0) || defined(BCM_56970_A0) 4923 { /* SOC_FORMAT_INT_MMU_RQE_TO_THDR_DATAfmt */ 4924 /* format MMU_RQE_TO_THDR_DATAfmt */ 4925 /* nFields */ 5, 4926 /* *fields */ soc_MMU_RQE_TO_THDR_DATAfmt_fields, 4927 /* bits */ 17, 4928 /* flags */ 0, 4929 }, 4930 #endif /* chips */ 4931 4932 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4933 { /* SOC_FORMAT_INT_MMU_RQE_TO_THDR_QUE_RELEASEfmt */ 4934 /* format MMU_RQE_TO_THDR_QUE_RELEASEfmt */ 4935 /* nFields */ 3, 4936 /* *fields */ soc_MMU_RQE_TO_THDR_QUE_RELEASEfmt_fields, 4937 /* bits */ 7, 4938 /* flags */ 0, 4939 }, 4940 #endif /* chips */ 4941 4942 #if defined(BCM_56970_A0) 4943 { /* SOC_FORMAT_INT_MMU_RQE_WF_DATAfmt */ 4944 /* format MMU_RQE_WF_DATAfmt */ 4945 /* nFields */ 11, 4946 /* *fields */ soc_MMU_RQE_WF_DATAfmt_fields, 4947 /* bits */ 345, 4948 /* flags */ 0, 4949 }, 4950 #endif /* chips */ 4951 4952 #if defined(BCM_56370_A0) 4953 { /* SOC_FORMAT_INT_MMU_RQE_WF_DATA_BCM56370_A0fmt */ 4954 /* format MMU_RQE_WF_DATAfmt */ 4955 /* nFields */ 13, 4956 /* *fields */ soc_MMU_RQE_WF_DATA_BCM56370_A0fmt_fields, 4957 /* bits */ 348, 4958 /* flags */ 0, 4959 }, 4960 #endif /* chips */ 4961 4962 #if defined(BCM_56770_A0) 4963 { /* SOC_FORMAT_INT_MMU_RQE_WF_DATA_BCM56770_A0fmt */ 4964 /* format MMU_RQE_WF_DATAfmt */ 4965 /* nFields */ 13, 4966 /* *fields */ soc_MMU_RQE_WF_DATA_BCM56870_A0fmt_fields, 4967 /* bits */ 552, 4968 /* flags */ 0, 4969 }, 4970 #endif /* chips */ 4971 4972 #if defined(BCM_56870_A0) 4973 { /* SOC_FORMAT_INT_MMU_RQE_WF_DATA_BCM56870_A0fmt */ 4974 /* format MMU_RQE_WF_DATAfmt */ 4975 /* nFields */ 13, 4976 /* *fields */ soc_MMU_RQE_WF_DATA_BCM56870_A0fmt_fields, 4977 /* bits */ 552, 4978 /* flags */ 0, 4979 }, 4980 #endif /* chips */ 4981 4982 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4983 { /* SOC_FORMAT_INT_MMU_SBUS_SB_INFOfmt */ 4984 /* format MMU_SBUS_SB_INFOfmt */ 4985 /* nFields */ 2, 4986 /* *fields */ soc_MMU_SBUS_SB_INFOfmt_fields, 4987 /* bits */ 33, 4988 /* flags */ 0, 4989 }, 4990 #endif /* chips */ 4991 4992 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4993 { /* SOC_FORMAT_INT_MMU_SCB_SOPSS_DATAfmt */ 4994 /* format MMU_SCB_SOPSS_DATAfmt */ 4995 /* nFields */ 7, 4996 /* *fields */ soc_MMU_SCB_SOPSS_DATAfmt_fields, 4997 /* bits */ 35, 4998 /* flags */ 0, 4999 }, 5000 #endif /* chips */ 5001 5002 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5003 { /* SOC_FORMAT_INT_MMU_SCB_TO_CRB_CREDIT_RETfmt */ 5004 /* format MMU_SCB_TO_CRB_CREDIT_RETfmt */ 5005 /* nFields */ 2, 5006 /* *fields */ soc_MMU_SCB_TO_CRB_CREDIT_RETfmt_fields, 5007 /* bits */ 4, 5008 /* flags */ 0, 5009 }, 5010 #endif /* chips */ 5011 5012 #if defined(BCM_56980_A0) 5013 { /* SOC_FORMAT_INT_MMU_SCB_TO_OQS_CELL_INFOfmt */ 5014 /* format MMU_SCB_TO_OQS_CELL_INFOfmt */ 5015 /* nFields */ 39, 5016 /* *fields */ soc_MMU_OQS_TO_TOQ_CELL_INFOfmt_fields, 5017 /* bits */ 97, 5018 /* flags */ 0, 5019 }, 5020 #endif /* chips */ 5021 5022 #if defined(BCM_56980_B0) 5023 { /* SOC_FORMAT_INT_MMU_SCB_TO_OQS_CELL_INFO_BCM56980_B0fmt */ 5024 /* format MMU_SCB_TO_OQS_CELL_INFOfmt */ 5025 /* nFields */ 39, 5026 /* *fields */ soc_MMU_OQS_TO_TOQ_CELL_INFOfmt_fields, 5027 /* bits */ 97, 5028 /* flags */ 0, 5029 }, 5030 #endif /* chips */ 5031 5032 #if defined(BCM_56980_A0) 5033 { /* SOC_FORMAT_INT_MMU_SCB_TO_RQE_CELL_CREDIT_RTNfmt */ 5034 /* format MMU_SCB_TO_RQE_CELL_CREDIT_RTNfmt */ 5035 /* nFields */ 2, 5036 /* *fields */ soc_MMU_SCB_TO_CRB_CREDIT_RETfmt_fields, 5037 /* bits */ 4, 5038 /* flags */ 0, 5039 }, 5040 #endif /* chips */ 5041 5042 #if defined(BCM_56980_B0) 5043 { /* SOC_FORMAT_INT_MMU_SCB_TO_RQE_CELL_CREDIT_RTN_BCM56980_B0fmt */ 5044 /* format MMU_SCB_TO_RQE_CELL_CREDIT_RTNfmt */ 5045 /* nFields */ 2, 5046 /* *fields */ soc_MMU_SCB_TO_CRB_CREDIT_RETfmt_fields, 5047 /* bits */ 4, 5048 /* flags */ 0, 5049 }, 5050 #endif /* chips */ 5051 5052 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5053 { /* SOC_FORMAT_INT_MMU_SCB_TO_RQE_CELL_INFOfmt */ 5054 /* format MMU_SCB_TO_RQE_CELL_INFOfmt */ 5055 /* nFields */ 19, 5056 /* *fields */ soc_MMU_SCB_TO_RQE_CELL_INFOfmt_fields, 5057 /* bits */ 75, 5058 /* flags */ 0, 5059 }, 5060 #endif /* chips */ 5061 5062 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 5063 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUSfmt */ 5064 /* format MMU_SER_STATUS_BUSfmt */ 5065 /* nFields */ 7, 5066 /* *fields */ soc_MMU_SER_STATUS_BUSfmt_fields, 5067 /* bits */ 44, 5068 /* flags */ 0, 5069 }, 5070 #endif /* chips */ 5071 5072 #if defined(BCM_56370_A0) 5073 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56370_A0fmt */ 5074 /* format MMU_SER_STATUS_BUSfmt */ 5075 /* nFields */ 7, 5076 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5077 /* bits */ 44, 5078 /* flags */ 0, 5079 }, 5080 #endif /* chips */ 5081 5082 #if defined(BCM_56560_A0) 5083 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56560_A0fmt */ 5084 /* format MMU_SER_STATUS_BUSfmt */ 5085 /* nFields */ 7, 5086 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5087 /* bits */ 44, 5088 /* flags */ 0, 5089 }, 5090 #endif /* chips */ 5091 5092 #if defined(BCM_56560_B0) 5093 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56560_B0fmt */ 5094 /* format MMU_SER_STATUS_BUSfmt */ 5095 /* nFields */ 7, 5096 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5097 /* bits */ 44, 5098 /* flags */ 0, 5099 }, 5100 #endif /* chips */ 5101 5102 #if defined(BCM_56670_A0) 5103 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56670_A0fmt */ 5104 /* format MMU_SER_STATUS_BUSfmt */ 5105 /* nFields */ 7, 5106 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5107 /* bits */ 44, 5108 /* flags */ 0, 5109 }, 5110 #endif /* chips */ 5111 5112 #if defined(BCM_56670_B0) 5113 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56670_B0fmt */ 5114 /* format MMU_SER_STATUS_BUSfmt */ 5115 /* nFields */ 7, 5116 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5117 /* bits */ 44, 5118 /* flags */ 0, 5119 }, 5120 #endif /* chips */ 5121 5122 #if defined(BCM_56770_A0) 5123 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56770_A0fmt */ 5124 /* format MMU_SER_STATUS_BUSfmt */ 5125 /* nFields */ 7, 5126 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5127 /* bits */ 44, 5128 /* flags */ 0, 5129 }, 5130 #endif /* chips */ 5131 5132 #if defined(BCM_56870_A0) 5133 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56870_A0fmt */ 5134 /* format MMU_SER_STATUS_BUSfmt */ 5135 /* nFields */ 7, 5136 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5137 /* bits */ 44, 5138 /* flags */ 0, 5139 }, 5140 #endif /* chips */ 5141 5142 #if defined(BCM_56960_A0) 5143 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56960_A0fmt */ 5144 /* format MMU_SER_STATUS_BUSfmt */ 5145 /* nFields */ 7, 5146 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5147 /* bits */ 44, 5148 /* flags */ 0, 5149 }, 5150 #endif /* chips */ 5151 5152 #if defined(BCM_56965_A0) 5153 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56965_A0fmt */ 5154 /* format MMU_SER_STATUS_BUSfmt */ 5155 /* nFields */ 7, 5156 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5157 /* bits */ 44, 5158 /* flags */ 0, 5159 }, 5160 #endif /* chips */ 5161 5162 #if defined(BCM_56970_A0) 5163 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56970_A0fmt */ 5164 /* format MMU_SER_STATUS_BUSfmt */ 5165 /* nFields */ 7, 5166 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5167 /* bits */ 44, 5168 /* flags */ 0, 5169 }, 5170 #endif /* chips */ 5171 5172 #if defined(BCM_56980_A0) 5173 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56980_A0fmt */ 5174 /* format MMU_SER_STATUS_BUSfmt */ 5175 /* nFields */ 7, 5176 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5177 /* bits */ 44, 5178 /* flags */ 0, 5179 }, 5180 #endif /* chips */ 5181 5182 #if defined(BCM_56980_B0) 5183 { /* SOC_FORMAT_INT_MMU_SER_STATUS_BUS_BCM56980_B0fmt */ 5184 /* format MMU_SER_STATUS_BUSfmt */ 5185 /* nFields */ 7, 5186 /* *fields */ soc_MMU_SER_STATUS_BUS_BCM56960_A0fmt_fields, 5187 /* bits */ 44, 5188 /* flags */ 0, 5189 }, 5190 #endif /* chips */ 5191 5192 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) 5193 { /* SOC_FORMAT_INT_MMU_SHAPE_PASSTHRU_INFOfmt */ 5194 /* format MMU_SHAPE_PASSTHRU_INFOfmt */ 5195 /* nFields */ 12, 5196 /* *fields */ soc_MMU_SHAPE_PASSTHRU_INFOfmt_fields, 5197 /* bits */ 57, 5198 /* flags */ 0, 5199 }, 5200 #endif /* chips */ 5201 5202 #if defined(BCM_56260_A0) 5203 { /* SOC_FORMAT_INT_MMU_SHAPE_PASSTHRU_INFO_BCM56260_A0fmt */ 5204 /* format MMU_SHAPE_PASSTHRU_INFOfmt */ 5205 /* nFields */ 6, 5206 /* *fields */ soc_MMU_SHAPE_PASSTHRU_INFO_BCM56260_A0fmt_fields, 5207 /* bits */ 28, 5208 /* flags */ 0, 5209 }, 5210 #endif /* chips */ 5211 5212 #if defined(BCM_56260_B0) 5213 { /* SOC_FORMAT_INT_MMU_SHAPE_PASSTHRU_INFO_BCM56260_B0fmt */ 5214 /* format MMU_SHAPE_PASSTHRU_INFOfmt */ 5215 /* nFields */ 6, 5216 /* *fields */ soc_MMU_SHAPE_PASSTHRU_INFO_BCM56260_A0fmt_fields, 5217 /* bits */ 28, 5218 /* flags */ 0, 5219 }, 5220 #endif /* chips */ 5221 5222 #if defined(BCM_56270_A0) 5223 { /* SOC_FORMAT_INT_MMU_SHAPE_PASSTHRU_INFO_BCM56270_A0fmt */ 5224 /* format MMU_SHAPE_PASSTHRU_INFOfmt */ 5225 /* nFields */ 7, 5226 /* *fields */ soc_MMU_SHAPE_PASSTHRU_INFO_BCM56270_A0fmt_fields, 5227 /* bits */ 28, 5228 /* flags */ 0, 5229 }, 5230 #endif /* chips */ 5231 5232 #if defined(BCM_56670_A0) 5233 { /* SOC_FORMAT_INT_MMU_SHAPE_PASSTHRU_INFO_BCM56670_A0fmt */ 5234 /* format MMU_SHAPE_PASSTHRU_INFOfmt */ 5235 /* nFields */ 13, 5236 /* *fields */ soc_MMU_SHAPE_PASSTHRU_INFO_BCM56670_A0fmt_fields, 5237 /* bits */ 57, 5238 /* flags */ 0, 5239 }, 5240 #endif /* chips */ 5241 5242 #if defined(BCM_56670_B0) 5243 { /* SOC_FORMAT_INT_MMU_SHAPE_PASSTHRU_INFO_BCM56670_B0fmt */ 5244 /* format MMU_SHAPE_PASSTHRU_INFOfmt */ 5245 /* nFields */ 13, 5246 /* *fields */ soc_MMU_SHAPE_PASSTHRU_INFO_BCM56670_A0fmt_fields, 5247 /* bits */ 57, 5248 /* flags */ 0, 5249 }, 5250 #endif /* chips */ 5251 5252 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5253 { /* SOC_FORMAT_INT_MMU_THDI_PACKET_TYPEfmt */ 5254 /* format MMU_THDI_PACKET_TYPEfmt */ 5255 /* nFields */ 3, 5256 /* *fields */ soc_MMU_THDI_PACKET_TYPEfmt_fields, 5257 /* bits */ 3, 5258 /* flags */ 0, 5259 }, 5260 #endif /* chips */ 5261 5262 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5263 { /* SOC_FORMAT_INT_MMU_THDI_SPAPfmt */ 5264 /* format MMU_THDI_SPAPfmt */ 5265 /* nFields */ 2, 5266 /* *fields */ soc_MMU_THDI_SPAPfmt_fields, 5267 /* bits */ 2, 5268 /* flags */ 0, 5269 }, 5270 #endif /* chips */ 5271 5272 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5273 { /* SOC_FORMAT_INT_MMU_THDI_TO_CRB_ENQ_INFOfmt */ 5274 /* format MMU_THDI_TO_CRB_ENQ_INFOfmt */ 5275 /* nFields */ 10, 5276 /* *fields */ soc_MMU_THDI_TO_CRB_ENQ_INFOfmt_fields, 5277 /* bits */ 14, 5278 /* flags */ 0, 5279 }, 5280 #endif /* chips */ 5281 5282 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5283 { /* SOC_FORMAT_INT_MMU_THDI_TO_INTFO_OOBFC_INFOfmt */ 5284 /* format MMU_THDI_TO_INTFO_OOBFC_INFOfmt */ 5285 /* nFields */ 7, 5286 /* *fields */ soc_MMU_THDI_TO_INTFO_OOBFC_INFOfmt_fields, 5287 /* bits */ 25, 5288 /* flags */ 0, 5289 }, 5290 #endif /* chips */ 5291 5292 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5293 { /* SOC_FORMAT_INT_MMU_THDI_TO_INTFO_PFC_INFOfmt */ 5294 /* format MMU_THDI_TO_INTFO_PFC_INFOfmt */ 5295 /* nFields */ 4, 5296 /* *fields */ soc_MMU_THDI_TO_INTFO_PFC_INFOfmt_fields, 5297 /* bits */ 15, 5298 /* flags */ 0, 5299 }, 5300 #endif /* chips */ 5301 5302 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5303 { /* SOC_FORMAT_INT_MMU_THDI_TO_THDO_LOSSLESS_SP_INFOfmt */ 5304 /* format MMU_THDI_TO_THDO_LOSSLESS_SP_INFOfmt */ 5305 /* nFields */ 5, 5306 /* *fields */ soc_MMU_THDI_TO_THDO_LOSSLESS_SP_INFOfmt_fields, 5307 /* bits */ 33, 5308 /* flags */ 0, 5309 }, 5310 #endif /* chips */ 5311 5312 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5313 { /* SOC_FORMAT_INT_MMU_THDI_TYPEfmt */ 5314 /* format MMU_THDI_TYPEfmt */ 5315 /* nFields */ 2, 5316 /* *fields */ soc_MMU_THDI_TYPEfmt_fields, 5317 /* bits */ 2, 5318 /* flags */ 0, 5319 }, 5320 #endif /* chips */ 5321 5322 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5323 { /* SOC_FORMAT_INT_MMU_THDO_TO_EBCTM_INFOfmt */ 5324 /* format MMU_THDO_TO_EBCTM_INFOfmt */ 5325 /* nFields */ 6, 5326 /* *fields */ soc_MMU_THDO_TO_EBCTM_INFOfmt_fields, 5327 /* bits */ 18, 5328 /* flags */ 0, 5329 }, 5330 #endif /* chips */ 5331 5332 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5333 { /* SOC_FORMAT_INT_MMU_THDO_TO_INTFO_FC_INFOfmt */ 5334 /* format MMU_THDO_TO_INTFO_FC_INFOfmt */ 5335 /* nFields */ 11, 5336 /* *fields */ soc_MMU_THDO_TO_INTFO_FC_INFOfmt_fields, 5337 /* bits */ 37, 5338 /* flags */ 0, 5339 }, 5340 #endif /* chips */ 5341 5342 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5343 { /* SOC_FORMAT_INT_MMU_THDO_TO_IP_DLB_INFOfmt */ 5344 /* format MMU_THDO_TO_IP_DLB_INFOfmt */ 5345 /* nFields */ 3, 5346 /* *fields */ soc_MMU_THDO_TO_IP_DLB_INFOfmt_fields, 5347 /* bits */ 27, 5348 /* flags */ 0, 5349 }, 5350 #endif /* chips */ 5351 5352 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5353 { /* SOC_FORMAT_INT_MMU_THDO_TO_QSCH_VOQ_FAIRNESS_INFOfmt */ 5354 /* format MMU_THDO_TO_QSCH_VOQ_FAIRNESS_INFOfmt */ 5355 /* nFields */ 5, 5356 /* *fields */ soc_MMU_THDO_TO_QSCH_VOQ_FAIRNESS_INFOfmt_fields, 5357 /* bits */ 41, 5358 /* flags */ 0, 5359 }, 5360 #endif /* chips */ 5361 5362 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5363 { /* SOC_FORMAT_INT_MMU_THDO_TO_RQE_ENQCHK_PKT_INFOfmt */ 5364 /* format MMU_THDO_TO_RQE_ENQCHK_PKT_INFOfmt */ 5365 /* nFields */ 3, 5366 /* *fields */ soc_MMU_THDO_TO_RQE_ENQCHK_PKT_INFOfmt_fields, 5367 /* bits */ 8, 5368 /* flags */ 0, 5369 }, 5370 #endif /* chips */ 5371 5372 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5373 { /* SOC_FORMAT_INT_MMU_THDO_TO_TOQ_ENQCHK_INFOfmt */ 5374 /* format MMU_THDO_TO_TOQ_ENQCHK_INFOfmt */ 5375 /* nFields */ 6, 5376 /* *fields */ soc_MMU_THDO_TO_TOQ_ENQCHK_INFOfmt_fields, 5377 /* bits */ 8, 5378 /* flags */ 0, 5379 }, 5380 #endif /* chips */ 5381 5382 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5383 { /* SOC_FORMAT_INT_MMU_THDO_TO_WRED_ENQ_ACCEPT_INFOfmt */ 5384 /* format MMU_THDO_TO_WRED_ENQ_ACCEPT_INFOfmt */ 5385 /* nFields */ 7, 5386 /* *fields */ soc_MMU_THDO_TO_WRED_ENQ_ACCEPT_INFOfmt_fields, 5387 /* bits */ 18, 5388 /* flags */ 0, 5389 }, 5390 #endif /* chips */ 5391 5392 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5393 { /* SOC_FORMAT_INT_MMU_THDO_TO_WRED_PORTSP_LEN_STATUS_INFOfmt */ 5394 /* format MMU_THDO_TO_WRED_PORTSP_LEN_STATUS_INFOfmt */ 5395 /* nFields */ 4, 5396 /* *fields */ soc_MMU_THDO_TO_WRED_PORTSP_LEN_STATUS_INFOfmt_fields, 5397 /* bits */ 46, 5398 /* flags */ 0, 5399 }, 5400 #endif /* chips */ 5401 5402 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5403 { /* SOC_FORMAT_INT_MMU_THDO_TO_WRED_QLEN_STATUS_INFOfmt */ 5404 /* format MMU_THDO_TO_WRED_QLEN_STATUS_INFOfmt */ 5405 /* nFields */ 6, 5406 /* *fields */ soc_MMU_THDO_TO_WRED_QLEN_STATUS_INFOfmt_fields, 5407 /* bits */ 82, 5408 /* flags */ 0, 5409 }, 5410 #endif /* chips */ 5411 5412 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5413 { /* SOC_FORMAT_INT_MMU_THDO_TO_WRED_Q_MIN_STATE_INFOfmt */ 5414 /* format MMU_THDO_TO_WRED_Q_MIN_STATE_INFOfmt */ 5415 /* nFields */ 6, 5416 /* *fields */ soc_MMU_THDO_TO_WRED_Q_MIN_STATE_INFOfmt_fields, 5417 /* bits */ 55, 5418 /* flags */ 0, 5419 }, 5420 #endif /* chips */ 5421 5422 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5423 { /* SOC_FORMAT_INT_MMU_THDO_TO_WRED_SP_LEN_STATUS_INFOfmt */ 5424 /* format MMU_THDO_TO_WRED_SP_LEN_STATUS_INFOfmt */ 5425 /* nFields */ 5, 5426 /* *fields */ soc_MMU_THDO_TO_WRED_SP_LEN_STATUS_INFOfmt_fields, 5427 /* bits */ 73, 5428 /* flags */ 0, 5429 }, 5430 #endif /* chips */ 5431 5432 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5433 { /* SOC_FORMAT_INT_MMU_THDR_TO_CRB_ACCEPT_INFOfmt */ 5434 /* format MMU_THDR_TO_CRB_ACCEPT_INFOfmt */ 5435 /* nFields */ 2, 5436 /* *fields */ soc_MMU_THDR_TO_CRB_ACCEPT_INFOfmt_fields, 5437 /* bits */ 2, 5438 /* flags */ 0, 5439 }, 5440 #endif /* chips */ 5441 5442 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5443 { /* SOC_FORMAT_INT_MMU_THDR_TO_INTFO_DROP_STATUSfmt */ 5444 /* format MMU_THDR_TO_INTFO_DROP_STATUSfmt */ 5445 /* nFields */ 1, 5446 /* *fields */ soc_MMU_THDR_TO_INTFO_DROP_STATUSfmt_fields, 5447 /* bits */ 2, 5448 /* flags */ 0, 5449 }, 5450 #endif /* chips */ 5451 5452 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5453 { /* SOC_FORMAT_INT_MMU_THDR_TO_RQE_ACCEPT_INFOfmt */ 5454 /* format MMU_THDR_TO_RQE_ACCEPT_INFOfmt */ 5455 /* nFields */ 3, 5456 /* *fields */ soc_MMU_THDR_TO_RQE_ACCEPT_INFOfmt_fields, 5457 /* bits */ 14, 5458 /* flags */ 0, 5459 }, 5460 #endif /* chips */ 5461 5462 #if defined(BCM_56980_A0) 5463 { /* SOC_FORMAT_INT_MMU_THDR_TO_THDI_ACCEPT_INFOfmt */ 5464 /* format MMU_THDR_TO_THDI_ACCEPT_INFOfmt */ 5465 /* nFields */ 2, 5466 /* *fields */ soc_MMU_THDR_TO_CRB_ACCEPT_INFOfmt_fields, 5467 /* bits */ 2, 5468 /* flags */ 0, 5469 }, 5470 #endif /* chips */ 5471 5472 #if defined(BCM_56980_B0) 5473 { /* SOC_FORMAT_INT_MMU_THDR_TO_THDI_ACCEPT_INFO_BCM56980_B0fmt */ 5474 /* format MMU_THDR_TO_THDI_ACCEPT_INFOfmt */ 5475 /* nFields */ 2, 5476 /* *fields */ soc_MMU_THDR_TO_CRB_ACCEPT_INFOfmt_fields, 5477 /* bits */ 2, 5478 /* flags */ 0, 5479 }, 5480 #endif /* chips */ 5481 5482 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5483 { /* SOC_FORMAT_INT_MMU_TOQ_CQEfmt */ 5484 /* format MMU_TOQ_CQEfmt */ 5485 /* nFields */ 18, 5486 /* *fields */ soc_MMU_TOQ_CQEfmt_fields, 5487 /* bits */ 79, 5488 /* flags */ 0, 5489 }, 5490 #endif /* chips */ 5491 5492 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 5493 { /* SOC_FORMAT_INT_MMU_TOQ_EOPE_TBLfmt */ 5494 /* format MMU_TOQ_EOPE_TBLfmt */ 5495 /* nFields */ 17, 5496 /* *fields */ soc_MMU_TOQ_EOPE_TBLfmt_fields, 5497 /* bits */ 56, 5498 /* flags */ 0, 5499 }, 5500 #endif /* chips */ 5501 5502 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5503 { /* SOC_FORMAT_INT_MMU_TOQ_TO_CFAP_ENQRETURN_INFOfmt */ 5504 /* format MMU_TOQ_TO_CFAP_ENQRETURN_INFOfmt */ 5505 /* nFields */ 1, 5506 /* *fields */ soc_MMU_TOQ_TO_CFAP_ENQRETURN_INFOfmt_fields, 5507 /* bits */ 39, 5508 /* flags */ 0, 5509 }, 5510 #endif /* chips */ 5511 5512 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5513 { /* SOC_FORMAT_INT_MMU_TOQ_TO_MTRO_DEQ_RESP_INFOfmt */ 5514 /* format MMU_TOQ_TO_MTRO_DEQ_RESP_INFOfmt */ 5515 /* nFields */ 7, 5516 /* *fields */ soc_MMU_TOQ_TO_MTRO_DEQ_RESP_INFOfmt_fields, 5517 /* bits */ 25, 5518 /* flags */ 0, 5519 }, 5520 #endif /* chips */ 5521 5522 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5523 { /* SOC_FORMAT_INT_MMU_TOQ_TO_QSCH_DEQ_RESP_INFOfmt */ 5524 /* format MMU_TOQ_TO_QSCH_DEQ_RESP_INFOfmt */ 5525 /* nFields */ 8, 5526 /* *fields */ soc_MMU_TOQ_TO_QSCH_DEQ_RESP_INFOfmt_fields, 5527 /* bits */ 28, 5528 /* flags */ 0, 5529 }, 5530 #endif /* chips */ 5531 5532 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5533 { /* SOC_FORMAT_INT_MMU_TOQ_TO_QSCH_UPDATE_INFOfmt */ 5534 /* format MMU_TOQ_TO_QSCH_UPDATE_INFOfmt */ 5535 /* nFields */ 7, 5536 /* *fields */ soc_MMU_TOQ_TO_QSCH_UPDATE_INFOfmt_fields, 5537 /* bits */ 36, 5538 /* flags */ 0, 5539 }, 5540 #endif /* chips */ 5541 5542 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5543 { /* SOC_FORMAT_INT_MMU_TOQ_TO_RL_INFOfmt */ 5544 /* format MMU_TOQ_TO_RL_INFOfmt */ 5545 /* nFields */ 31, 5546 /* *fields */ soc_MMU_TOQ_TO_RL_INFOfmt_fields, 5547 /* bits */ 101, 5548 /* flags */ 0, 5549 }, 5550 #endif /* chips */ 5551 5552 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5553 { /* SOC_FORMAT_INT_MMU_TOQ_TO_RQE_CELL_INFOfmt */ 5554 /* format MMU_TOQ_TO_RQE_CELL_INFOfmt */ 5555 /* nFields */ 4, 5556 /* *fields */ soc_MMU_TOQ_TO_RQE_CELL_INFOfmt_fields, 5557 /* bits */ 78, 5558 /* flags */ 0, 5559 }, 5560 #endif /* chips */ 5561 5562 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5563 { /* SOC_FORMAT_INT_MMU_TOQ_TO_THDO_DEQ_INFOfmt */ 5564 /* format MMU_TOQ_TO_THDO_DEQ_INFOfmt */ 5565 /* nFields */ 10, 5566 /* *fields */ soc_MMU_TOQ_TO_THDO_DEQ_INFOfmt_fields, 5567 /* bits */ 36, 5568 /* flags */ 0, 5569 }, 5570 #endif /* chips */ 5571 5572 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5573 { /* SOC_FORMAT_INT_MMU_TOQ_TO_THDO_ENQCHK_INFOfmt */ 5574 /* format MMU_TOQ_TO_THDO_ENQCHK_INFOfmt */ 5575 /* nFields */ 21, 5576 /* *fields */ soc_MMU_TOQ_TO_THDO_ENQCHK_INFOfmt_fields, 5577 /* bits */ 57, 5578 /* flags */ 0, 5579 }, 5580 #endif /* chips */ 5581 5582 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5583 { /* SOC_FORMAT_INT_MMU_TOQ_TO_WRED_DEQ_INFOfmt */ 5584 /* format MMU_TOQ_TO_WRED_DEQ_INFOfmt */ 5585 /* nFields */ 3, 5586 /* *fields */ soc_MMU_TOQ_TO_WRED_DEQ_INFOfmt_fields, 5587 /* bits */ 13, 5588 /* flags */ 0, 5589 }, 5590 #endif /* chips */ 5591 5592 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \ 5593 defined(BCM_56820_A0) 5594 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COSfmt */ 5595 /* format MMU_TO_IP_HOL_COSfmt */ 5596 /* nFields */ 1, 5597 /* *fields */ soc_MMU_TO_IP_HOL_COSfmt_fields, 5598 /* bits */ 4, 5599 /* flags */ 0, 5600 }, 5601 #endif /* chips */ 5602 5603 #if defined(BCM_53400_A0) 5604 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM53400_A0fmt */ 5605 /* format MMU_TO_IP_HOL_COSfmt */ 5606 /* nFields */ 1, 5607 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5608 /* bits */ 3, 5609 /* flags */ 0, 5610 }, 5611 #endif /* chips */ 5612 5613 #if defined(BCM_53540_A0) 5614 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM53540_A0fmt */ 5615 /* format MMU_TO_IP_HOL_COSfmt */ 5616 /* nFields */ 1, 5617 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5618 /* bits */ 3, 5619 /* flags */ 0, 5620 }, 5621 #endif /* chips */ 5622 5623 #if defined(BCM_53570_A0) 5624 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM53570_A0fmt */ 5625 /* format MMU_TO_IP_HOL_COSfmt */ 5626 /* nFields */ 1, 5627 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5628 /* bits */ 3, 5629 /* flags */ 0, 5630 }, 5631 #endif /* chips */ 5632 5633 #if defined(BCM_53570_B0) 5634 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM53570_B0fmt */ 5635 /* format MMU_TO_IP_HOL_COSfmt */ 5636 /* nFields */ 1, 5637 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5638 /* bits */ 3, 5639 /* flags */ 0, 5640 }, 5641 #endif /* chips */ 5642 5643 #if defined(BCM_56142_A0) 5644 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56142_A0fmt */ 5645 /* format MMU_TO_IP_HOL_COSfmt */ 5646 /* nFields */ 1, 5647 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5648 /* bits */ 3, 5649 /* flags */ 0, 5650 }, 5651 #endif /* chips */ 5652 5653 #if defined(BCM_56150_A0) 5654 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56150_A0fmt */ 5655 /* format MMU_TO_IP_HOL_COSfmt */ 5656 /* nFields */ 1, 5657 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5658 /* bits */ 3, 5659 /* flags */ 0, 5660 }, 5661 #endif /* chips */ 5662 5663 #if defined(BCM_56160_A0) 5664 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56160_A0fmt */ 5665 /* format MMU_TO_IP_HOL_COSfmt */ 5666 /* nFields */ 1, 5667 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5668 /* bits */ 3, 5669 /* flags */ 0, 5670 }, 5671 #endif /* chips */ 5672 5673 #if defined(BCM_56260_A0) 5674 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56260_A0fmt */ 5675 /* format MMU_TO_IP_HOL_COSfmt */ 5676 /* nFields */ 1, 5677 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5678 /* bits */ 3, 5679 /* flags */ 0, 5680 }, 5681 #endif /* chips */ 5682 5683 #if defined(BCM_56260_B0) 5684 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56260_B0fmt */ 5685 /* format MMU_TO_IP_HOL_COSfmt */ 5686 /* nFields */ 1, 5687 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5688 /* bits */ 3, 5689 /* flags */ 0, 5690 }, 5691 #endif /* chips */ 5692 5693 #if defined(BCM_56270_A0) 5694 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56270_A0fmt */ 5695 /* format MMU_TO_IP_HOL_COSfmt */ 5696 /* nFields */ 1, 5697 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5698 /* bits */ 3, 5699 /* flags */ 0, 5700 }, 5701 #endif /* chips */ 5702 5703 #if defined(BCM_56334_A0) 5704 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56334_A0fmt */ 5705 /* format MMU_TO_IP_HOL_COSfmt */ 5706 /* nFields */ 1, 5707 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5708 /* bits */ 3, 5709 /* flags */ 0, 5710 }, 5711 #endif /* chips */ 5712 5713 #if defined(BCM_56334_B0) 5714 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56334_B0fmt */ 5715 /* format MMU_TO_IP_HOL_COSfmt */ 5716 /* nFields */ 1, 5717 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5718 /* bits */ 3, 5719 /* flags */ 0, 5720 }, 5721 #endif /* chips */ 5722 5723 #if defined(BCM_56340_A0) 5724 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56340_A0fmt */ 5725 /* format MMU_TO_IP_HOL_COSfmt */ 5726 /* nFields */ 1, 5727 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5728 /* bits */ 3, 5729 /* flags */ 0, 5730 }, 5731 #endif /* chips */ 5732 5733 #if defined(BCM_56440_A0) 5734 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56440_A0fmt */ 5735 /* format MMU_TO_IP_HOL_COSfmt */ 5736 /* nFields */ 1, 5737 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5738 /* bits */ 3, 5739 /* flags */ 0, 5740 }, 5741 #endif /* chips */ 5742 5743 #if defined(BCM_56440_B0) 5744 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56440_B0fmt */ 5745 /* format MMU_TO_IP_HOL_COSfmt */ 5746 /* nFields */ 1, 5747 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5748 /* bits */ 3, 5749 /* flags */ 0, 5750 }, 5751 #endif /* chips */ 5752 5753 #if defined(BCM_56450_A0) 5754 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56450_A0fmt */ 5755 /* format MMU_TO_IP_HOL_COSfmt */ 5756 /* nFields */ 1, 5757 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5758 /* bits */ 3, 5759 /* flags */ 0, 5760 }, 5761 #endif /* chips */ 5762 5763 #if defined(BCM_56450_B0) 5764 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56450_B0fmt */ 5765 /* format MMU_TO_IP_HOL_COSfmt */ 5766 /* nFields */ 1, 5767 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5768 /* bits */ 3, 5769 /* flags */ 0, 5770 }, 5771 #endif /* chips */ 5772 5773 #if defined(BCM_56450_B1) 5774 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56450_B1fmt */ 5775 /* format MMU_TO_IP_HOL_COSfmt */ 5776 /* nFields */ 1, 5777 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5778 /* bits */ 3, 5779 /* flags */ 0, 5780 }, 5781 #endif /* chips */ 5782 5783 #if defined(BCM_56524_A0) 5784 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56524_A0fmt */ 5785 /* format MMU_TO_IP_HOL_COSfmt */ 5786 /* nFields */ 1, 5787 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5788 /* bits */ 3, 5789 /* flags */ 0, 5790 }, 5791 #endif /* chips */ 5792 5793 #if defined(BCM_56524_B0) 5794 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56524_B0fmt */ 5795 /* format MMU_TO_IP_HOL_COSfmt */ 5796 /* nFields */ 1, 5797 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5798 /* bits */ 3, 5799 /* flags */ 0, 5800 }, 5801 #endif /* chips */ 5802 5803 #if defined(BCM_56560_A0) 5804 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56560_A0fmt */ 5805 /* format MMU_TO_IP_HOL_COSfmt */ 5806 /* nFields */ 1, 5807 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5808 /* bits */ 3, 5809 /* flags */ 0, 5810 }, 5811 #endif /* chips */ 5812 5813 #if defined(BCM_56560_B0) 5814 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56560_B0fmt */ 5815 /* format MMU_TO_IP_HOL_COSfmt */ 5816 /* nFields */ 1, 5817 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5818 /* bits */ 3, 5819 /* flags */ 0, 5820 }, 5821 #endif /* chips */ 5822 5823 #if defined(BCM_56624_A0) 5824 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56624_A0fmt */ 5825 /* format MMU_TO_IP_HOL_COSfmt */ 5826 /* nFields */ 1, 5827 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5828 /* bits */ 3, 5829 /* flags */ 0, 5830 }, 5831 #endif /* chips */ 5832 5833 #if defined(BCM_56624_B0) 5834 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56624_B0fmt */ 5835 /* format MMU_TO_IP_HOL_COSfmt */ 5836 /* nFields */ 1, 5837 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5838 /* bits */ 3, 5839 /* flags */ 0, 5840 }, 5841 #endif /* chips */ 5842 5843 #if defined(BCM_56634_A0) 5844 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56634_A0fmt */ 5845 /* format MMU_TO_IP_HOL_COSfmt */ 5846 /* nFields */ 1, 5847 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5848 /* bits */ 3, 5849 /* flags */ 0, 5850 }, 5851 #endif /* chips */ 5852 5853 #if defined(BCM_56634_B0) 5854 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56634_B0fmt */ 5855 /* format MMU_TO_IP_HOL_COSfmt */ 5856 /* nFields */ 1, 5857 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5858 /* bits */ 3, 5859 /* flags */ 0, 5860 }, 5861 #endif /* chips */ 5862 5863 #if defined(BCM_56640_A0) 5864 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56640_A0fmt */ 5865 /* format MMU_TO_IP_HOL_COSfmt */ 5866 /* nFields */ 1, 5867 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5868 /* bits */ 3, 5869 /* flags */ 0, 5870 }, 5871 #endif /* chips */ 5872 5873 #if defined(BCM_56670_A0) 5874 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56670_A0fmt */ 5875 /* format MMU_TO_IP_HOL_COSfmt */ 5876 /* nFields */ 1, 5877 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5878 /* bits */ 3, 5879 /* flags */ 0, 5880 }, 5881 #endif /* chips */ 5882 5883 #if defined(BCM_56670_B0) 5884 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56670_B0fmt */ 5885 /* format MMU_TO_IP_HOL_COSfmt */ 5886 /* nFields */ 1, 5887 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5888 /* bits */ 3, 5889 /* flags */ 0, 5890 }, 5891 #endif /* chips */ 5892 5893 #if defined(BCM_56680_A0) 5894 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56680_A0fmt */ 5895 /* format MMU_TO_IP_HOL_COSfmt */ 5896 /* nFields */ 1, 5897 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5898 /* bits */ 3, 5899 /* flags */ 0, 5900 }, 5901 #endif /* chips */ 5902 5903 #if defined(BCM_56680_B0) 5904 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56680_B0fmt */ 5905 /* format MMU_TO_IP_HOL_COSfmt */ 5906 /* nFields */ 1, 5907 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5908 /* bits */ 3, 5909 /* flags */ 0, 5910 }, 5911 #endif /* chips */ 5912 5913 #if defined(BCM_56685_A0) 5914 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56685_A0fmt */ 5915 /* format MMU_TO_IP_HOL_COSfmt */ 5916 /* nFields */ 1, 5917 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5918 /* bits */ 3, 5919 /* flags */ 0, 5920 }, 5921 #endif /* chips */ 5922 5923 #if defined(BCM_56685_B0) 5924 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56685_B0fmt */ 5925 /* format MMU_TO_IP_HOL_COSfmt */ 5926 /* nFields */ 1, 5927 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5928 /* bits */ 3, 5929 /* flags */ 0, 5930 }, 5931 #endif /* chips */ 5932 5933 #if defined(BCM_56840_A0) 5934 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56840_A0fmt */ 5935 /* format MMU_TO_IP_HOL_COSfmt */ 5936 /* nFields */ 1, 5937 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5938 /* bits */ 3, 5939 /* flags */ 0, 5940 }, 5941 #endif /* chips */ 5942 5943 #if defined(BCM_56840_B0) 5944 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56840_B0fmt */ 5945 /* format MMU_TO_IP_HOL_COSfmt */ 5946 /* nFields */ 1, 5947 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56624_A0fmt_fields, 5948 /* bits */ 3, 5949 /* flags */ 0, 5950 }, 5951 #endif /* chips */ 5952 5953 #if defined(BCM_56850_A0) 5954 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56850_A0fmt */ 5955 /* format MMU_TO_IP_HOL_COSfmt */ 5956 /* nFields */ 1, 5957 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5958 /* bits */ 3, 5959 /* flags */ 0, 5960 }, 5961 #endif /* chips */ 5962 5963 #if defined(BCM_56860_A0) 5964 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56860_A0fmt */ 5965 /* format MMU_TO_IP_HOL_COSfmt */ 5966 /* nFields */ 1, 5967 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM56640_A0fmt_fields, 5968 /* bits */ 3, 5969 /* flags */ 0, 5970 }, 5971 #endif /* chips */ 5972 5973 #if defined(BCM_56960_A0) 5974 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56960_A0fmt */ 5975 /* format MMU_TO_IP_HOL_COSfmt */ 5976 /* nFields */ 1, 5977 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5978 /* bits */ 3, 5979 /* flags */ 0, 5980 }, 5981 #endif /* chips */ 5982 5983 #if defined(BCM_56965_A0) 5984 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56965_A0fmt */ 5985 /* format MMU_TO_IP_HOL_COSfmt */ 5986 /* nFields */ 1, 5987 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5988 /* bits */ 3, 5989 /* flags */ 0, 5990 }, 5991 #endif /* chips */ 5992 5993 #if defined(BCM_56970_A0) 5994 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_COS_BCM56970_A0fmt */ 5995 /* format MMU_TO_IP_HOL_COSfmt */ 5996 /* nFields */ 1, 5997 /* *fields */ soc_MMU_TO_IP_HOL_COS_BCM53400_A0fmt_fields, 5998 /* bits */ 3, 5999 /* flags */ 0, 6000 }, 6001 #endif /* chips */ 6002 6003 #if defined(BCM_56800_A0) 6004 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUSfmt */ 6005 /* format MMU_TO_IP_HOL_STATUSfmt */ 6006 /* nFields */ 1, 6007 /* *fields */ soc_MMU_TO_IP_HOL_STATUSfmt_fields, 6008 /* bits */ 21, 6009 /* flags */ 0, 6010 }, 6011 #endif /* chips */ 6012 6013 #if defined(BCM_53400_A0) 6014 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM53400_A0fmt */ 6015 /* format MMU_TO_IP_HOL_STATUSfmt */ 6016 /* nFields */ 1, 6017 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM53400_A0fmt_fields, 6018 /* bits */ 30, 6019 /* flags */ 0, 6020 }, 6021 #endif /* chips */ 6022 6023 #if defined(BCM_53540_A0) 6024 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM53540_A0fmt */ 6025 /* format MMU_TO_IP_HOL_STATUSfmt */ 6026 /* nFields */ 1, 6027 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 6028 /* bits */ 32, 6029 /* flags */ 0, 6030 }, 6031 #endif /* chips */ 6032 6033 #if defined(BCM_53570_A0) 6034 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM53570_A0fmt */ 6035 /* format MMU_TO_IP_HOL_STATUSfmt */ 6036 /* nFields */ 1, 6037 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 6038 /* bits */ 32, 6039 /* flags */ 0, 6040 }, 6041 #endif /* chips */ 6042 6043 #if defined(BCM_53570_B0) 6044 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM53570_B0fmt */ 6045 /* format MMU_TO_IP_HOL_STATUSfmt */ 6046 /* nFields */ 1, 6047 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 6048 /* bits */ 32, 6049 /* flags */ 0, 6050 }, 6051 #endif /* chips */ 6052 6053 #if defined(BCM_56142_A0) 6054 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56142_A0fmt */ 6055 /* format MMU_TO_IP_HOL_STATUSfmt */ 6056 /* nFields */ 1, 6057 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56334_A0fmt_fields, 6058 /* bits */ 30, 6059 /* flags */ 0, 6060 }, 6061 #endif /* chips */ 6062 6063 #if defined(BCM_56150_A0) 6064 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56150_A0fmt */ 6065 /* format MMU_TO_IP_HOL_STATUSfmt */ 6066 /* nFields */ 1, 6067 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56150_A0fmt_fields, 6068 /* bits */ 30, 6069 /* flags */ 0, 6070 }, 6071 #endif /* chips */ 6072 6073 #if defined(BCM_56160_A0) 6074 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt */ 6075 /* format MMU_TO_IP_HOL_STATUSfmt */ 6076 /* nFields */ 1, 6077 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 6078 /* bits */ 32, 6079 /* flags */ 0, 6080 }, 6081 #endif /* chips */ 6082 6083 #if defined(BCM_56260_A0) 6084 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56260_A0fmt */ 6085 /* format MMU_TO_IP_HOL_STATUSfmt */ 6086 /* nFields */ 1, 6087 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6088 /* bits */ 54, 6089 /* flags */ 0, 6090 }, 6091 #endif /* chips */ 6092 6093 #if defined(BCM_56260_B0) 6094 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56260_B0fmt */ 6095 /* format MMU_TO_IP_HOL_STATUSfmt */ 6096 /* nFields */ 1, 6097 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6098 /* bits */ 54, 6099 /* flags */ 0, 6100 }, 6101 #endif /* chips */ 6102 6103 #if defined(BCM_56270_A0) 6104 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56270_A0fmt */ 6105 /* format MMU_TO_IP_HOL_STATUSfmt */ 6106 /* nFields */ 1, 6107 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6108 /* bits */ 54, 6109 /* flags */ 0, 6110 }, 6111 #endif /* chips */ 6112 6113 #if defined(BCM_56334_A0) 6114 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56334_A0fmt */ 6115 /* format MMU_TO_IP_HOL_STATUSfmt */ 6116 /* nFields */ 1, 6117 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56334_A0fmt_fields, 6118 /* bits */ 30, 6119 /* flags */ 0, 6120 }, 6121 #endif /* chips */ 6122 6123 #if defined(BCM_56334_B0) 6124 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56334_B0fmt */ 6125 /* format MMU_TO_IP_HOL_STATUSfmt */ 6126 /* nFields */ 1, 6127 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56334_A0fmt_fields, 6128 /* bits */ 30, 6129 /* flags */ 0, 6130 }, 6131 #endif /* chips */ 6132 6133 #if defined(BCM_56340_A0) 6134 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56340_A0fmt */ 6135 /* format MMU_TO_IP_HOL_STATUSfmt */ 6136 /* nFields */ 1, 6137 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 6138 /* bits */ 54, 6139 /* flags */ 0, 6140 }, 6141 #endif /* chips */ 6142 6143 #if defined(BCM_56440_A0) 6144 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56440_A0fmt */ 6145 /* format MMU_TO_IP_HOL_STATUSfmt */ 6146 /* nFields */ 1, 6147 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6148 /* bits */ 54, 6149 /* flags */ 0, 6150 }, 6151 #endif /* chips */ 6152 6153 #if defined(BCM_56440_B0) 6154 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56440_B0fmt */ 6155 /* format MMU_TO_IP_HOL_STATUSfmt */ 6156 /* nFields */ 1, 6157 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6158 /* bits */ 54, 6159 /* flags */ 0, 6160 }, 6161 #endif /* chips */ 6162 6163 #if defined(BCM_56450_A0) 6164 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56450_A0fmt */ 6165 /* format MMU_TO_IP_HOL_STATUSfmt */ 6166 /* nFields */ 1, 6167 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 6168 /* bits */ 54, 6169 /* flags */ 0, 6170 }, 6171 #endif /* chips */ 6172 6173 #if defined(BCM_56450_B0) 6174 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56450_B0fmt */ 6175 /* format MMU_TO_IP_HOL_STATUSfmt */ 6176 /* nFields */ 1, 6177 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 6178 /* bits */ 54, 6179 /* flags */ 0, 6180 }, 6181 #endif /* chips */ 6182 6183 #if defined(BCM_56450_B1) 6184 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56450_B1fmt */ 6185 /* format MMU_TO_IP_HOL_STATUSfmt */ 6186 /* nFields */ 1, 6187 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 6188 /* bits */ 54, 6189 /* flags */ 0, 6190 }, 6191 #endif /* chips */ 6192 6193 #if defined(BCM_56524_A0) 6194 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56524_A0fmt */ 6195 /* format MMU_TO_IP_HOL_STATUSfmt */ 6196 /* nFields */ 1, 6197 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6198 /* bits */ 54, 6199 /* flags */ 0, 6200 }, 6201 #endif /* chips */ 6202 6203 #if defined(BCM_56524_B0) 6204 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56524_B0fmt */ 6205 /* format MMU_TO_IP_HOL_STATUSfmt */ 6206 /* nFields */ 1, 6207 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6208 /* bits */ 54, 6209 /* flags */ 0, 6210 }, 6211 #endif /* chips */ 6212 6213 #if defined(BCM_56560_A0) 6214 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56560_A0fmt */ 6215 /* format MMU_TO_IP_HOL_STATUSfmt */ 6216 /* nFields */ 1, 6217 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6218 /* bits */ 54, 6219 /* flags */ 0, 6220 }, 6221 #endif /* chips */ 6222 6223 #if defined(BCM_56560_B0) 6224 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56560_B0fmt */ 6225 /* format MMU_TO_IP_HOL_STATUSfmt */ 6226 /* nFields */ 1, 6227 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6228 /* bits */ 54, 6229 /* flags */ 0, 6230 }, 6231 #endif /* chips */ 6232 6233 #if defined(BCM_56624_A0) 6234 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt */ 6235 /* format MMU_TO_IP_HOL_STATUSfmt */ 6236 /* nFields */ 1, 6237 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6238 /* bits */ 54, 6239 /* flags */ 0, 6240 }, 6241 #endif /* chips */ 6242 6243 #if defined(BCM_56624_B0) 6244 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56624_B0fmt */ 6245 /* format MMU_TO_IP_HOL_STATUSfmt */ 6246 /* nFields */ 1, 6247 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6248 /* bits */ 54, 6249 /* flags */ 0, 6250 }, 6251 #endif /* chips */ 6252 6253 #if defined(BCM_56634_A0) 6254 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56634_A0fmt */ 6255 /* format MMU_TO_IP_HOL_STATUSfmt */ 6256 /* nFields */ 1, 6257 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6258 /* bits */ 54, 6259 /* flags */ 0, 6260 }, 6261 #endif /* chips */ 6262 6263 #if defined(BCM_56634_B0) 6264 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56634_B0fmt */ 6265 /* format MMU_TO_IP_HOL_STATUSfmt */ 6266 /* nFields */ 1, 6267 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6268 /* bits */ 54, 6269 /* flags */ 0, 6270 }, 6271 #endif /* chips */ 6272 6273 #if defined(BCM_56640_A0) 6274 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt */ 6275 /* format MMU_TO_IP_HOL_STATUSfmt */ 6276 /* nFields */ 1, 6277 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 6278 /* bits */ 54, 6279 /* flags */ 0, 6280 }, 6281 #endif /* chips */ 6282 6283 #if defined(BCM_56670_A0) 6284 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56670_A0fmt */ 6285 /* format MMU_TO_IP_HOL_STATUSfmt */ 6286 /* nFields */ 1, 6287 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6288 /* bits */ 54, 6289 /* flags */ 0, 6290 }, 6291 #endif /* chips */ 6292 6293 #if defined(BCM_56670_B0) 6294 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56670_B0fmt */ 6295 /* format MMU_TO_IP_HOL_STATUSfmt */ 6296 /* nFields */ 1, 6297 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6298 /* bits */ 54, 6299 /* flags */ 0, 6300 }, 6301 #endif /* chips */ 6302 6303 #if defined(BCM_56680_A0) 6304 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56680_A0fmt */ 6305 /* format MMU_TO_IP_HOL_STATUSfmt */ 6306 /* nFields */ 1, 6307 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6308 /* bits */ 54, 6309 /* flags */ 0, 6310 }, 6311 #endif /* chips */ 6312 6313 #if defined(BCM_56680_B0) 6314 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56680_B0fmt */ 6315 /* format MMU_TO_IP_HOL_STATUSfmt */ 6316 /* nFields */ 1, 6317 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6318 /* bits */ 54, 6319 /* flags */ 0, 6320 }, 6321 #endif /* chips */ 6322 6323 #if defined(BCM_56685_A0) 6324 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56685_A0fmt */ 6325 /* format MMU_TO_IP_HOL_STATUSfmt */ 6326 /* nFields */ 1, 6327 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6328 /* bits */ 54, 6329 /* flags */ 0, 6330 }, 6331 #endif /* chips */ 6332 6333 #if defined(BCM_56685_B0) 6334 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56685_B0fmt */ 6335 /* format MMU_TO_IP_HOL_STATUSfmt */ 6336 /* nFields */ 1, 6337 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6338 /* bits */ 54, 6339 /* flags */ 0, 6340 }, 6341 #endif /* chips */ 6342 6343 #if defined(BCM_56725_A0) 6344 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56725_A0fmt */ 6345 /* format MMU_TO_IP_HOL_STATUSfmt */ 6346 /* nFields */ 1, 6347 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56820_A0fmt_fields, 6348 /* bits */ 29, 6349 /* flags */ 0, 6350 }, 6351 #endif /* chips */ 6352 6353 #if defined(BCM_56820_A0) 6354 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56820_A0fmt */ 6355 /* format MMU_TO_IP_HOL_STATUSfmt */ 6356 /* nFields */ 1, 6357 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56820_A0fmt_fields, 6358 /* bits */ 29, 6359 /* flags */ 0, 6360 }, 6361 #endif /* chips */ 6362 6363 #if defined(BCM_56840_A0) 6364 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56840_A0fmt */ 6365 /* format MMU_TO_IP_HOL_STATUSfmt */ 6366 /* nFields */ 1, 6367 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6368 /* bits */ 54, 6369 /* flags */ 0, 6370 }, 6371 #endif /* chips */ 6372 6373 #if defined(BCM_56840_B0) 6374 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56840_B0fmt */ 6375 /* format MMU_TO_IP_HOL_STATUSfmt */ 6376 /* nFields */ 1, 6377 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 6378 /* bits */ 54, 6379 /* flags */ 0, 6380 }, 6381 #endif /* chips */ 6382 6383 #if defined(BCM_56850_A0) 6384 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56850_A0fmt */ 6385 /* format MMU_TO_IP_HOL_STATUSfmt */ 6386 /* nFields */ 1, 6387 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 6388 /* bits */ 54, 6389 /* flags */ 0, 6390 }, 6391 #endif /* chips */ 6392 6393 #if defined(BCM_56860_A0) 6394 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56860_A0fmt */ 6395 /* format MMU_TO_IP_HOL_STATUSfmt */ 6396 /* nFields */ 1, 6397 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 6398 /* bits */ 54, 6399 /* flags */ 0, 6400 }, 6401 #endif /* chips */ 6402 6403 #if defined(BCM_56960_A0) 6404 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt */ 6405 /* format MMU_TO_IP_HOL_STATUSfmt */ 6406 /* nFields */ 1, 6407 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6408 /* bits */ 54, 6409 /* flags */ 0, 6410 }, 6411 #endif /* chips */ 6412 6413 #if defined(BCM_56965_A0) 6414 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56965_A0fmt */ 6415 /* format MMU_TO_IP_HOL_STATUSfmt */ 6416 /* nFields */ 1, 6417 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6418 /* bits */ 54, 6419 /* flags */ 0, 6420 }, 6421 #endif /* chips */ 6422 6423 #if defined(BCM_56970_A0) 6424 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_BCM56970_A0fmt */ 6425 /* format MMU_TO_IP_HOL_STATUSfmt */ 6426 /* nFields */ 1, 6427 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 6428 /* bits */ 54, 6429 /* flags */ 0, 6430 }, 6431 #endif /* chips */ 6432 6433 #if defined(BCM_56624_A0) 6434 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6435 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6436 /* nFields */ 1, 6437 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16fmt_fields, 6438 /* bits */ 13, 6439 /* flags */ 0, 6440 }, 6441 #endif /* chips */ 6442 6443 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 6444 defined(BCM_56680_A0) || defined(BCM_56680_B0) 6445 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6446 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6447 /* nFields */ 1, 6448 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16fmt_fields, 6449 /* bits */ 13, 6450 /* flags */ 0, 6451 }, 6452 #endif /* chips */ 6453 6454 #if defined(BCM_53400_A0) 6455 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt */ 6456 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6457 /* nFields */ 1, 6458 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6459 /* bits */ 5, 6460 /* flags */ 0, 6461 }, 6462 #endif /* chips */ 6463 6464 #if defined(BCM_53540_A0) 6465 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM53540_A0fmt */ 6466 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6467 /* nFields */ 1, 6468 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6469 /* bits */ 5, 6470 /* flags */ 0, 6471 }, 6472 #endif /* chips */ 6473 6474 #if defined(BCM_53570_A0) 6475 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM53570_A0fmt */ 6476 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6477 /* nFields */ 1, 6478 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6479 /* bits */ 5, 6480 /* flags */ 0, 6481 }, 6482 #endif /* chips */ 6483 6484 #if defined(BCM_53570_B0) 6485 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM53570_B0fmt */ 6486 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6487 /* nFields */ 1, 6488 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6489 /* bits */ 5, 6490 /* flags */ 0, 6491 }, 6492 #endif /* chips */ 6493 6494 #if defined(BCM_56142_A0) 6495 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56142_A0fmt */ 6496 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6497 /* nFields */ 1, 6498 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_A0fmt_fields, 6499 /* bits */ 5, 6500 /* flags */ 0, 6501 }, 6502 #endif /* chips */ 6503 6504 #if defined(BCM_56150_A0) 6505 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56150_A0fmt */ 6506 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6507 /* nFields */ 1, 6508 /* *fields */ soc_TRILLfmt_fields, 6509 /* bits */ 5, 6510 /* flags */ 0, 6511 }, 6512 #endif /* chips */ 6513 6514 #if defined(BCM_56160_A0) 6515 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56160_A0fmt */ 6516 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6517 /* nFields */ 1, 6518 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6519 /* bits */ 5, 6520 /* flags */ 0, 6521 }, 6522 #endif /* chips */ 6523 6524 #if defined(BCM_56260_A0) 6525 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56260_A0fmt */ 6526 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6527 /* nFields */ 1, 6528 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6529 /* bits */ 15, 6530 /* flags */ 0, 6531 }, 6532 #endif /* chips */ 6533 6534 #if defined(BCM_56260_B0) 6535 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56260_B0fmt */ 6536 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6537 /* nFields */ 1, 6538 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6539 /* bits */ 15, 6540 /* flags */ 0, 6541 }, 6542 #endif /* chips */ 6543 6544 #if defined(BCM_56270_A0) 6545 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56270_A0fmt */ 6546 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6547 /* nFields */ 1, 6548 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6549 /* bits */ 15, 6550 /* flags */ 0, 6551 }, 6552 #endif /* chips */ 6553 6554 #if defined(BCM_56334_A0) 6555 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_A0fmt */ 6556 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6557 /* nFields */ 1, 6558 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_A0fmt_fields, 6559 /* bits */ 5, 6560 /* flags */ 0, 6561 }, 6562 #endif /* chips */ 6563 6564 #if defined(BCM_56334_B0) 6565 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_B0fmt */ 6566 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6567 /* nFields */ 1, 6568 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_A0fmt_fields, 6569 /* bits */ 5, 6570 /* flags */ 0, 6571 }, 6572 #endif /* chips */ 6573 6574 #if defined(BCM_56340_A0) 6575 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56340_A0fmt */ 6576 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6577 /* nFields */ 1, 6578 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6579 /* bits */ 15, 6580 /* flags */ 0, 6581 }, 6582 #endif /* chips */ 6583 6584 #if defined(BCM_56440_A0) 6585 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56440_A0fmt */ 6586 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6587 /* nFields */ 1, 6588 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6589 /* bits */ 15, 6590 /* flags */ 0, 6591 }, 6592 #endif /* chips */ 6593 6594 #if defined(BCM_56440_B0) 6595 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56440_B0fmt */ 6596 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6597 /* nFields */ 1, 6598 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6599 /* bits */ 15, 6600 /* flags */ 0, 6601 }, 6602 #endif /* chips */ 6603 6604 #if defined(BCM_56450_A0) 6605 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56450_A0fmt */ 6606 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6607 /* nFields */ 1, 6608 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6609 /* bits */ 15, 6610 /* flags */ 0, 6611 }, 6612 #endif /* chips */ 6613 6614 #if defined(BCM_56450_B0) 6615 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56450_B0fmt */ 6616 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6617 /* nFields */ 1, 6618 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6619 /* bits */ 15, 6620 /* flags */ 0, 6621 }, 6622 #endif /* chips */ 6623 6624 #if defined(BCM_56450_B1) 6625 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56450_B1fmt */ 6626 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6627 /* nFields */ 1, 6628 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6629 /* bits */ 15, 6630 /* flags */ 0, 6631 }, 6632 #endif /* chips */ 6633 6634 #if defined(BCM_56524_A0) 6635 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56524_A0fmt */ 6636 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6637 /* nFields */ 1, 6638 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6639 /* bits */ 15, 6640 /* flags */ 0, 6641 }, 6642 #endif /* chips */ 6643 6644 #if defined(BCM_56524_B0) 6645 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56524_B0fmt */ 6646 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6647 /* nFields */ 1, 6648 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6649 /* bits */ 15, 6650 /* flags */ 0, 6651 }, 6652 #endif /* chips */ 6653 6654 #if defined(BCM_56560_A0) 6655 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56560_A0fmt */ 6656 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6657 /* nFields */ 1, 6658 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6659 /* bits */ 15, 6660 /* flags */ 0, 6661 }, 6662 #endif /* chips */ 6663 6664 #if defined(BCM_56560_B0) 6665 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56560_B0fmt */ 6666 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6667 /* nFields */ 1, 6668 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6669 /* bits */ 15, 6670 /* flags */ 0, 6671 }, 6672 #endif /* chips */ 6673 6674 #if defined(BCM_56634_A0) 6675 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt */ 6676 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6677 /* nFields */ 1, 6678 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6679 /* bits */ 15, 6680 /* flags */ 0, 6681 }, 6682 #endif /* chips */ 6683 6684 #if defined(BCM_56634_B0) 6685 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_B0fmt */ 6686 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6687 /* nFields */ 1, 6688 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6689 /* bits */ 15, 6690 /* flags */ 0, 6691 }, 6692 #endif /* chips */ 6693 6694 #if defined(BCM_56640_A0) 6695 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt */ 6696 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6697 /* nFields */ 1, 6698 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6699 /* bits */ 15, 6700 /* flags */ 0, 6701 }, 6702 #endif /* chips */ 6703 6704 #if defined(BCM_56670_A0) 6705 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56670_A0fmt */ 6706 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6707 /* nFields */ 1, 6708 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6709 /* bits */ 15, 6710 /* flags */ 0, 6711 }, 6712 #endif /* chips */ 6713 6714 #if defined(BCM_56670_B0) 6715 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56670_B0fmt */ 6716 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6717 /* nFields */ 1, 6718 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6719 /* bits */ 15, 6720 /* flags */ 0, 6721 }, 6722 #endif /* chips */ 6723 6724 #if defined(BCM_56685_A0) 6725 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56685_A0fmt */ 6726 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6727 /* nFields */ 1, 6728 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6729 /* bits */ 15, 6730 /* flags */ 0, 6731 }, 6732 #endif /* chips */ 6733 6734 #if defined(BCM_56685_B0) 6735 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56685_B0fmt */ 6736 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6737 /* nFields */ 1, 6738 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6739 /* bits */ 15, 6740 /* flags */ 0, 6741 }, 6742 #endif /* chips */ 6743 6744 #if defined(BCM_56840_A0) 6745 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56840_A0fmt */ 6746 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6747 /* nFields */ 1, 6748 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6749 /* bits */ 15, 6750 /* flags */ 0, 6751 }, 6752 #endif /* chips */ 6753 6754 #if defined(BCM_56840_B0) 6755 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56840_B0fmt */ 6756 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6757 /* nFields */ 1, 6758 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6759 /* bits */ 15, 6760 /* flags */ 0, 6761 }, 6762 #endif /* chips */ 6763 6764 #if defined(BCM_56850_A0) 6765 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56850_A0fmt */ 6766 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6767 /* nFields */ 1, 6768 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6769 /* bits */ 15, 6770 /* flags */ 0, 6771 }, 6772 #endif /* chips */ 6773 6774 #if defined(BCM_56860_A0) 6775 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56860_A0fmt */ 6776 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6777 /* nFields */ 1, 6778 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6779 /* bits */ 15, 6780 /* flags */ 0, 6781 }, 6782 #endif /* chips */ 6783 6784 #if defined(BCM_56960_A0) 6785 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt */ 6786 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6787 /* nFields */ 1, 6788 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6789 /* bits */ 15, 6790 /* flags */ 0, 6791 }, 6792 #endif /* chips */ 6793 6794 #if defined(BCM_56965_A0) 6795 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56965_A0fmt */ 6796 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6797 /* nFields */ 1, 6798 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6799 /* bits */ 15, 6800 /* flags */ 0, 6801 }, 6802 #endif /* chips */ 6803 6804 #if defined(BCM_56970_A0) 6805 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT16_BCM56970_A0fmt */ 6806 /* format MMU_TO_IP_HOL_STATUS_EXT16fmt */ 6807 /* nFields */ 1, 6808 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6809 /* bits */ 15, 6810 /* flags */ 0, 6811 }, 6812 #endif /* chips */ 6813 6814 #if defined(BCM_53400_A0) 6815 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM53400_A0fmt */ 6816 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6817 /* nFields */ 1, 6818 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6819 /* bits */ 5, 6820 /* flags */ 0, 6821 }, 6822 #endif /* chips */ 6823 6824 #if defined(BCM_53540_A0) 6825 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM53540_A0fmt */ 6826 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6827 /* nFields */ 1, 6828 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6829 /* bits */ 5, 6830 /* flags */ 0, 6831 }, 6832 #endif /* chips */ 6833 6834 #if defined(BCM_53570_A0) 6835 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM53570_A0fmt */ 6836 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6837 /* nFields */ 1, 6838 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6839 /* bits */ 5, 6840 /* flags */ 0, 6841 }, 6842 #endif /* chips */ 6843 6844 #if defined(BCM_53570_B0) 6845 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM53570_B0fmt */ 6846 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6847 /* nFields */ 1, 6848 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6849 /* bits */ 5, 6850 /* flags */ 0, 6851 }, 6852 #endif /* chips */ 6853 6854 #if defined(BCM_56142_A0) 6855 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56142_A0fmt */ 6856 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6857 /* nFields */ 1, 6858 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_A0fmt_fields, 6859 /* bits */ 5, 6860 /* flags */ 0, 6861 }, 6862 #endif /* chips */ 6863 6864 #if defined(BCM_56150_A0) 6865 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56150_A0fmt */ 6866 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6867 /* nFields */ 1, 6868 /* *fields */ soc_TRILLfmt_fields, 6869 /* bits */ 5, 6870 /* flags */ 0, 6871 }, 6872 #endif /* chips */ 6873 6874 #if defined(BCM_56160_A0) 6875 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56160_A0fmt */ 6876 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6877 /* nFields */ 1, 6878 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM53400_A0fmt_fields, 6879 /* bits */ 5, 6880 /* flags */ 0, 6881 }, 6882 #endif /* chips */ 6883 6884 #if defined(BCM_56260_A0) 6885 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56260_A0fmt */ 6886 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6887 /* nFields */ 1, 6888 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6889 /* bits */ 15, 6890 /* flags */ 0, 6891 }, 6892 #endif /* chips */ 6893 6894 #if defined(BCM_56260_B0) 6895 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56260_B0fmt */ 6896 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6897 /* nFields */ 1, 6898 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6899 /* bits */ 15, 6900 /* flags */ 0, 6901 }, 6902 #endif /* chips */ 6903 6904 #if defined(BCM_56270_A0) 6905 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56270_A0fmt */ 6906 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6907 /* nFields */ 1, 6908 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 6909 /* bits */ 15, 6910 /* flags */ 0, 6911 }, 6912 #endif /* chips */ 6913 6914 #if defined(BCM_56334_A0) 6915 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56334_A0fmt */ 6916 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6917 /* nFields */ 1, 6918 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_A0fmt_fields, 6919 /* bits */ 5, 6920 /* flags */ 0, 6921 }, 6922 #endif /* chips */ 6923 6924 #if defined(BCM_56334_B0) 6925 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56334_B0fmt */ 6926 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6927 /* nFields */ 1, 6928 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56334_A0fmt_fields, 6929 /* bits */ 5, 6930 /* flags */ 0, 6931 }, 6932 #endif /* chips */ 6933 6934 #if defined(BCM_56340_A0) 6935 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56340_A0fmt */ 6936 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6937 /* nFields */ 1, 6938 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6939 /* bits */ 15, 6940 /* flags */ 0, 6941 }, 6942 #endif /* chips */ 6943 6944 #if defined(BCM_56440_A0) 6945 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56440_A0fmt */ 6946 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6947 /* nFields */ 1, 6948 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6949 /* bits */ 15, 6950 /* flags */ 0, 6951 }, 6952 #endif /* chips */ 6953 6954 #if defined(BCM_56440_B0) 6955 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56440_B0fmt */ 6956 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6957 /* nFields */ 1, 6958 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6959 /* bits */ 15, 6960 /* flags */ 0, 6961 }, 6962 #endif /* chips */ 6963 6964 #if defined(BCM_56450_A0) 6965 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56450_A0fmt */ 6966 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6967 /* nFields */ 1, 6968 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6969 /* bits */ 15, 6970 /* flags */ 0, 6971 }, 6972 #endif /* chips */ 6973 6974 #if defined(BCM_56450_B0) 6975 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56450_B0fmt */ 6976 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6977 /* nFields */ 1, 6978 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6979 /* bits */ 15, 6980 /* flags */ 0, 6981 }, 6982 #endif /* chips */ 6983 6984 #if defined(BCM_56450_B1) 6985 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56450_B1fmt */ 6986 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6987 /* nFields */ 1, 6988 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 6989 /* bits */ 15, 6990 /* flags */ 0, 6991 }, 6992 #endif /* chips */ 6993 6994 #if defined(BCM_56524_A0) 6995 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56524_A0fmt */ 6996 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 6997 /* nFields */ 1, 6998 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 6999 /* bits */ 15, 7000 /* flags */ 0, 7001 }, 7002 #endif /* chips */ 7003 7004 #if defined(BCM_56524_B0) 7005 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56524_B0fmt */ 7006 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7007 /* nFields */ 1, 7008 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 7009 /* bits */ 15, 7010 /* flags */ 0, 7011 }, 7012 #endif /* chips */ 7013 7014 #if defined(BCM_56560_A0) 7015 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56560_A0fmt */ 7016 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7017 /* nFields */ 1, 7018 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 7019 /* bits */ 15, 7020 /* flags */ 0, 7021 }, 7022 #endif /* chips */ 7023 7024 #if defined(BCM_56560_B0) 7025 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56560_B0fmt */ 7026 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7027 /* nFields */ 1, 7028 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 7029 /* bits */ 15, 7030 /* flags */ 0, 7031 }, 7032 #endif /* chips */ 7033 7034 #if defined(BCM_56624_B0) 7035 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56624_B0fmt */ 7036 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7037 /* nFields */ 1, 7038 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16fmt_fields, 7039 /* bits */ 13, 7040 /* flags */ 0, 7041 }, 7042 #endif /* chips */ 7043 7044 #if defined(BCM_56634_A0) 7045 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56634_A0fmt */ 7046 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7047 /* nFields */ 1, 7048 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 7049 /* bits */ 15, 7050 /* flags */ 0, 7051 }, 7052 #endif /* chips */ 7053 7054 #if defined(BCM_56634_B0) 7055 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56634_B0fmt */ 7056 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7057 /* nFields */ 1, 7058 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 7059 /* bits */ 15, 7060 /* flags */ 0, 7061 }, 7062 #endif /* chips */ 7063 7064 #if defined(BCM_56640_A0) 7065 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56640_A0fmt */ 7066 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7067 /* nFields */ 1, 7068 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 7069 /* bits */ 15, 7070 /* flags */ 0, 7071 }, 7072 #endif /* chips */ 7073 7074 #if defined(BCM_56670_A0) 7075 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56670_A0fmt */ 7076 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7077 /* nFields */ 1, 7078 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 7079 /* bits */ 15, 7080 /* flags */ 0, 7081 }, 7082 #endif /* chips */ 7083 7084 #if defined(BCM_56670_B0) 7085 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56670_B0fmt */ 7086 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7087 /* nFields */ 1, 7088 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 7089 /* bits */ 15, 7090 /* flags */ 0, 7091 }, 7092 #endif /* chips */ 7093 7094 #if defined(BCM_56680_A0) 7095 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56680_A0fmt */ 7096 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7097 /* nFields */ 1, 7098 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16fmt_fields, 7099 /* bits */ 13, 7100 /* flags */ 0, 7101 }, 7102 #endif /* chips */ 7103 7104 #if defined(BCM_56680_B0) 7105 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56680_B0fmt */ 7106 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7107 /* nFields */ 1, 7108 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16fmt_fields, 7109 /* bits */ 13, 7110 /* flags */ 0, 7111 }, 7112 #endif /* chips */ 7113 7114 #if defined(BCM_56685_A0) 7115 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56685_A0fmt */ 7116 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7117 /* nFields */ 1, 7118 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 7119 /* bits */ 15, 7120 /* flags */ 0, 7121 }, 7122 #endif /* chips */ 7123 7124 #if defined(BCM_56685_B0) 7125 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56685_B0fmt */ 7126 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7127 /* nFields */ 1, 7128 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 7129 /* bits */ 15, 7130 /* flags */ 0, 7131 }, 7132 #endif /* chips */ 7133 7134 #if defined(BCM_56840_A0) 7135 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56840_A0fmt */ 7136 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7137 /* nFields */ 1, 7138 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 7139 /* bits */ 15, 7140 /* flags */ 0, 7141 }, 7142 #endif /* chips */ 7143 7144 #if defined(BCM_56840_B0) 7145 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56840_B0fmt */ 7146 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7147 /* nFields */ 1, 7148 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56634_A0fmt_fields, 7149 /* bits */ 15, 7150 /* flags */ 0, 7151 }, 7152 #endif /* chips */ 7153 7154 #if defined(BCM_56850_A0) 7155 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56850_A0fmt */ 7156 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7157 /* nFields */ 1, 7158 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 7159 /* bits */ 15, 7160 /* flags */ 0, 7161 }, 7162 #endif /* chips */ 7163 7164 #if defined(BCM_56860_A0) 7165 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56860_A0fmt */ 7166 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7167 /* nFields */ 1, 7168 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56640_A0fmt_fields, 7169 /* bits */ 15, 7170 /* flags */ 0, 7171 }, 7172 #endif /* chips */ 7173 7174 #if defined(BCM_56960_A0) 7175 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56960_A0fmt */ 7176 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7177 /* nFields */ 1, 7178 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 7179 /* bits */ 15, 7180 /* flags */ 0, 7181 }, 7182 #endif /* chips */ 7183 7184 #if defined(BCM_56965_A0) 7185 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56965_A0fmt */ 7186 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7187 /* nFields */ 1, 7188 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 7189 /* bits */ 15, 7190 /* flags */ 0, 7191 }, 7192 #endif /* chips */ 7193 7194 #if defined(BCM_56970_A0) 7195 { /* SOC_FORMAT_INT_MMU_TO_IP_HOL_STATUS_EXT8_BCM56970_A0fmt */ 7196 /* format MMU_TO_IP_HOL_STATUS_EXT8fmt */ 7197 /* nFields */ 1, 7198 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_EXT16_BCM56960_A0fmt_fields, 7199 /* bits */ 15, 7200 /* flags */ 0, 7201 }, 7202 #endif /* chips */ 7203 7204 #if defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 7205 defined(BCM_56634_B0) || defined(BCM_56800_A0) 7206 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRIfmt */ 7207 /* format MMU_TO_IP_IBP_PRIfmt */ 7208 /* nFields */ 1, 7209 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7210 /* bits */ 4, 7211 /* flags */ 0, 7212 }, 7213 #endif /* chips */ 7214 7215 #if defined(BCM_53400_A0) 7216 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt */ 7217 /* format MMU_TO_IP_IBP_PRIfmt */ 7218 /* nFields */ 1, 7219 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7220 /* bits */ 4, 7221 /* flags */ 0, 7222 }, 7223 #endif /* chips */ 7224 7225 #if defined(BCM_53540_A0) 7226 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM53540_A0fmt */ 7227 /* format MMU_TO_IP_IBP_PRIfmt */ 7228 /* nFields */ 1, 7229 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7230 /* bits */ 4, 7231 /* flags */ 0, 7232 }, 7233 #endif /* chips */ 7234 7235 #if defined(BCM_53570_A0) 7236 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM53570_A0fmt */ 7237 /* format MMU_TO_IP_IBP_PRIfmt */ 7238 /* nFields */ 1, 7239 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7240 /* bits */ 4, 7241 /* flags */ 0, 7242 }, 7243 #endif /* chips */ 7244 7245 #if defined(BCM_53570_B0) 7246 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM53570_B0fmt */ 7247 /* format MMU_TO_IP_IBP_PRIfmt */ 7248 /* nFields */ 1, 7249 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7250 /* bits */ 4, 7251 /* flags */ 0, 7252 }, 7253 #endif /* chips */ 7254 7255 #if defined(BCM_56142_A0) 7256 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56142_A0fmt */ 7257 /* format MMU_TO_IP_IBP_PRIfmt */ 7258 /* nFields */ 1, 7259 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7260 /* bits */ 4, 7261 /* flags */ 0, 7262 }, 7263 #endif /* chips */ 7264 7265 #if defined(BCM_56150_A0) 7266 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56150_A0fmt */ 7267 /* format MMU_TO_IP_IBP_PRIfmt */ 7268 /* nFields */ 1, 7269 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7270 /* bits */ 4, 7271 /* flags */ 0, 7272 }, 7273 #endif /* chips */ 7274 7275 #if defined(BCM_56160_A0) 7276 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56160_A0fmt */ 7277 /* format MMU_TO_IP_IBP_PRIfmt */ 7278 /* nFields */ 1, 7279 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7280 /* bits */ 4, 7281 /* flags */ 0, 7282 }, 7283 #endif /* chips */ 7284 7285 #if defined(BCM_56260_A0) 7286 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56260_A0fmt */ 7287 /* format MMU_TO_IP_IBP_PRIfmt */ 7288 /* nFields */ 1, 7289 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7290 /* bits */ 4, 7291 /* flags */ 0, 7292 }, 7293 #endif /* chips */ 7294 7295 #if defined(BCM_56260_B0) 7296 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56260_B0fmt */ 7297 /* format MMU_TO_IP_IBP_PRIfmt */ 7298 /* nFields */ 1, 7299 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7300 /* bits */ 4, 7301 /* flags */ 0, 7302 }, 7303 #endif /* chips */ 7304 7305 #if defined(BCM_56270_A0) 7306 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56270_A0fmt */ 7307 /* format MMU_TO_IP_IBP_PRIfmt */ 7308 /* nFields */ 1, 7309 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7310 /* bits */ 4, 7311 /* flags */ 0, 7312 }, 7313 #endif /* chips */ 7314 7315 #if defined(BCM_56334_A0) 7316 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56334_A0fmt */ 7317 /* format MMU_TO_IP_IBP_PRIfmt */ 7318 /* nFields */ 1, 7319 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7320 /* bits */ 4, 7321 /* flags */ 0, 7322 }, 7323 #endif /* chips */ 7324 7325 #if defined(BCM_56334_B0) 7326 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56334_B0fmt */ 7327 /* format MMU_TO_IP_IBP_PRIfmt */ 7328 /* nFields */ 1, 7329 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7330 /* bits */ 4, 7331 /* flags */ 0, 7332 }, 7333 #endif /* chips */ 7334 7335 #if defined(BCM_56340_A0) 7336 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56340_A0fmt */ 7337 /* format MMU_TO_IP_IBP_PRIfmt */ 7338 /* nFields */ 1, 7339 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7340 /* bits */ 4, 7341 /* flags */ 0, 7342 }, 7343 #endif /* chips */ 7344 7345 #if defined(BCM_56440_A0) 7346 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56440_A0fmt */ 7347 /* format MMU_TO_IP_IBP_PRIfmt */ 7348 /* nFields */ 1, 7349 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7350 /* bits */ 4, 7351 /* flags */ 0, 7352 }, 7353 #endif /* chips */ 7354 7355 #if defined(BCM_56440_B0) 7356 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56440_B0fmt */ 7357 /* format MMU_TO_IP_IBP_PRIfmt */ 7358 /* nFields */ 1, 7359 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7360 /* bits */ 4, 7361 /* flags */ 0, 7362 }, 7363 #endif /* chips */ 7364 7365 #if defined(BCM_56450_A0) 7366 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56450_A0fmt */ 7367 /* format MMU_TO_IP_IBP_PRIfmt */ 7368 /* nFields */ 1, 7369 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7370 /* bits */ 4, 7371 /* flags */ 0, 7372 }, 7373 #endif /* chips */ 7374 7375 #if defined(BCM_56450_B0) 7376 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56450_B0fmt */ 7377 /* format MMU_TO_IP_IBP_PRIfmt */ 7378 /* nFields */ 1, 7379 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7380 /* bits */ 4, 7381 /* flags */ 0, 7382 }, 7383 #endif /* chips */ 7384 7385 #if defined(BCM_56450_B1) 7386 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56450_B1fmt */ 7387 /* format MMU_TO_IP_IBP_PRIfmt */ 7388 /* nFields */ 1, 7389 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7390 /* bits */ 4, 7391 /* flags */ 0, 7392 }, 7393 #endif /* chips */ 7394 7395 #if defined(BCM_56524_A0) 7396 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56524_A0fmt */ 7397 /* format MMU_TO_IP_IBP_PRIfmt */ 7398 /* nFields */ 1, 7399 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7400 /* bits */ 4, 7401 /* flags */ 0, 7402 }, 7403 #endif /* chips */ 7404 7405 #if defined(BCM_56524_B0) 7406 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56524_B0fmt */ 7407 /* format MMU_TO_IP_IBP_PRIfmt */ 7408 /* nFields */ 1, 7409 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7410 /* bits */ 4, 7411 /* flags */ 0, 7412 }, 7413 #endif /* chips */ 7414 7415 #if defined(BCM_56560_A0) 7416 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56560_A0fmt */ 7417 /* format MMU_TO_IP_IBP_PRIfmt */ 7418 /* nFields */ 1, 7419 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7420 /* bits */ 4, 7421 /* flags */ 0, 7422 }, 7423 #endif /* chips */ 7424 7425 #if defined(BCM_56560_B0) 7426 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56560_B0fmt */ 7427 /* format MMU_TO_IP_IBP_PRIfmt */ 7428 /* nFields */ 1, 7429 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7430 /* bits */ 4, 7431 /* flags */ 0, 7432 }, 7433 #endif /* chips */ 7434 7435 #if defined(BCM_56624_B0) 7436 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56624_B0fmt */ 7437 /* format MMU_TO_IP_IBP_PRIfmt */ 7438 /* nFields */ 1, 7439 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7440 /* bits */ 4, 7441 /* flags */ 0, 7442 }, 7443 #endif /* chips */ 7444 7445 #if defined(BCM_56640_A0) 7446 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt */ 7447 /* format MMU_TO_IP_IBP_PRIfmt */ 7448 /* nFields */ 1, 7449 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7450 /* bits */ 4, 7451 /* flags */ 0, 7452 }, 7453 #endif /* chips */ 7454 7455 #if defined(BCM_56670_A0) 7456 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56670_A0fmt */ 7457 /* format MMU_TO_IP_IBP_PRIfmt */ 7458 /* nFields */ 1, 7459 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7460 /* bits */ 4, 7461 /* flags */ 0, 7462 }, 7463 #endif /* chips */ 7464 7465 #if defined(BCM_56670_B0) 7466 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56670_B0fmt */ 7467 /* format MMU_TO_IP_IBP_PRIfmt */ 7468 /* nFields */ 1, 7469 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7470 /* bits */ 4, 7471 /* flags */ 0, 7472 }, 7473 #endif /* chips */ 7474 7475 #if defined(BCM_56680_A0) 7476 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56680_A0fmt */ 7477 /* format MMU_TO_IP_IBP_PRIfmt */ 7478 /* nFields */ 1, 7479 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7480 /* bits */ 4, 7481 /* flags */ 0, 7482 }, 7483 #endif /* chips */ 7484 7485 #if defined(BCM_56680_B0) 7486 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56680_B0fmt */ 7487 /* format MMU_TO_IP_IBP_PRIfmt */ 7488 /* nFields */ 1, 7489 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7490 /* bits */ 4, 7491 /* flags */ 0, 7492 }, 7493 #endif /* chips */ 7494 7495 #if defined(BCM_56685_A0) 7496 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56685_A0fmt */ 7497 /* format MMU_TO_IP_IBP_PRIfmt */ 7498 /* nFields */ 1, 7499 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7500 /* bits */ 4, 7501 /* flags */ 0, 7502 }, 7503 #endif /* chips */ 7504 7505 #if defined(BCM_56685_B0) 7506 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56685_B0fmt */ 7507 /* format MMU_TO_IP_IBP_PRIfmt */ 7508 /* nFields */ 1, 7509 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7510 /* bits */ 4, 7511 /* flags */ 0, 7512 }, 7513 #endif /* chips */ 7514 7515 #if defined(BCM_56725_A0) 7516 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56725_A0fmt */ 7517 /* format MMU_TO_IP_IBP_PRIfmt */ 7518 /* nFields */ 1, 7519 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7520 /* bits */ 4, 7521 /* flags */ 0, 7522 }, 7523 #endif /* chips */ 7524 7525 #if defined(BCM_56820_A0) 7526 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56820_A0fmt */ 7527 /* format MMU_TO_IP_IBP_PRIfmt */ 7528 /* nFields */ 1, 7529 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7530 /* bits */ 4, 7531 /* flags */ 0, 7532 }, 7533 #endif /* chips */ 7534 7535 #if defined(BCM_56840_A0) 7536 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56840_A0fmt */ 7537 /* format MMU_TO_IP_IBP_PRIfmt */ 7538 /* nFields */ 1, 7539 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7540 /* bits */ 4, 7541 /* flags */ 0, 7542 }, 7543 #endif /* chips */ 7544 7545 #if defined(BCM_56840_B0) 7546 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56840_B0fmt */ 7547 /* format MMU_TO_IP_IBP_PRIfmt */ 7548 /* nFields */ 1, 7549 /* *fields */ soc_MMU_TO_IP_IBP_PRIfmt_fields, 7550 /* bits */ 4, 7551 /* flags */ 0, 7552 }, 7553 #endif /* chips */ 7554 7555 #if defined(BCM_56850_A0) 7556 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56850_A0fmt */ 7557 /* format MMU_TO_IP_IBP_PRIfmt */ 7558 /* nFields */ 1, 7559 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7560 /* bits */ 4, 7561 /* flags */ 0, 7562 }, 7563 #endif /* chips */ 7564 7565 #if defined(BCM_56860_A0) 7566 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56860_A0fmt */ 7567 /* format MMU_TO_IP_IBP_PRIfmt */ 7568 /* nFields */ 1, 7569 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM56640_A0fmt_fields, 7570 /* bits */ 4, 7571 /* flags */ 0, 7572 }, 7573 #endif /* chips */ 7574 7575 #if defined(BCM_56960_A0) 7576 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56960_A0fmt */ 7577 /* format MMU_TO_IP_IBP_PRIfmt */ 7578 /* nFields */ 1, 7579 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7580 /* bits */ 4, 7581 /* flags */ 0, 7582 }, 7583 #endif /* chips */ 7584 7585 #if defined(BCM_56965_A0) 7586 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56965_A0fmt */ 7587 /* format MMU_TO_IP_IBP_PRIfmt */ 7588 /* nFields */ 1, 7589 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7590 /* bits */ 4, 7591 /* flags */ 0, 7592 }, 7593 #endif /* chips */ 7594 7595 #if defined(BCM_56970_A0) 7596 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_PRI_BCM56970_A0fmt */ 7597 /* format MMU_TO_IP_IBP_PRIfmt */ 7598 /* nFields */ 1, 7599 /* *fields */ soc_MMU_TO_IP_IBP_PRI_BCM53400_A0fmt_fields, 7600 /* bits */ 4, 7601 /* flags */ 0, 7602 }, 7603 #endif /* chips */ 7604 7605 #if defined(BCM_56800_A0) 7606 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUSfmt */ 7607 /* format MMU_TO_IP_IBP_STATUSfmt */ 7608 /* nFields */ 1, 7609 /* *fields */ soc_MMU_TO_IP_HOL_STATUSfmt_fields, 7610 /* bits */ 21, 7611 /* flags */ 0, 7612 }, 7613 #endif /* chips */ 7614 7615 #if defined(BCM_53400_A0) 7616 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM53400_A0fmt */ 7617 /* format MMU_TO_IP_IBP_STATUSfmt */ 7618 /* nFields */ 1, 7619 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM53400_A0fmt_fields, 7620 /* bits */ 30, 7621 /* flags */ 0, 7622 }, 7623 #endif /* chips */ 7624 7625 #if defined(BCM_53540_A0) 7626 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM53540_A0fmt */ 7627 /* format MMU_TO_IP_IBP_STATUSfmt */ 7628 /* nFields */ 1, 7629 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 7630 /* bits */ 32, 7631 /* flags */ 0, 7632 }, 7633 #endif /* chips */ 7634 7635 #if defined(BCM_53570_A0) 7636 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM53570_A0fmt */ 7637 /* format MMU_TO_IP_IBP_STATUSfmt */ 7638 /* nFields */ 1, 7639 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 7640 /* bits */ 32, 7641 /* flags */ 0, 7642 }, 7643 #endif /* chips */ 7644 7645 #if defined(BCM_53570_B0) 7646 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM53570_B0fmt */ 7647 /* format MMU_TO_IP_IBP_STATUSfmt */ 7648 /* nFields */ 1, 7649 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 7650 /* bits */ 32, 7651 /* flags */ 0, 7652 }, 7653 #endif /* chips */ 7654 7655 #if defined(BCM_56142_A0) 7656 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56142_A0fmt */ 7657 /* format MMU_TO_IP_IBP_STATUSfmt */ 7658 /* nFields */ 1, 7659 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56334_A0fmt_fields, 7660 /* bits */ 30, 7661 /* flags */ 0, 7662 }, 7663 #endif /* chips */ 7664 7665 #if defined(BCM_56150_A0) 7666 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56150_A0fmt */ 7667 /* format MMU_TO_IP_IBP_STATUSfmt */ 7668 /* nFields */ 1, 7669 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56150_A0fmt_fields, 7670 /* bits */ 30, 7671 /* flags */ 0, 7672 }, 7673 #endif /* chips */ 7674 7675 #if defined(BCM_56160_A0) 7676 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56160_A0fmt */ 7677 /* format MMU_TO_IP_IBP_STATUSfmt */ 7678 /* nFields */ 1, 7679 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56160_A0fmt_fields, 7680 /* bits */ 32, 7681 /* flags */ 0, 7682 }, 7683 #endif /* chips */ 7684 7685 #if defined(BCM_56260_A0) 7686 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56260_A0fmt */ 7687 /* format MMU_TO_IP_IBP_STATUSfmt */ 7688 /* nFields */ 1, 7689 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 7690 /* bits */ 54, 7691 /* flags */ 0, 7692 }, 7693 #endif /* chips */ 7694 7695 #if defined(BCM_56260_B0) 7696 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56260_B0fmt */ 7697 /* format MMU_TO_IP_IBP_STATUSfmt */ 7698 /* nFields */ 1, 7699 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 7700 /* bits */ 54, 7701 /* flags */ 0, 7702 }, 7703 #endif /* chips */ 7704 7705 #if defined(BCM_56270_A0) 7706 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56270_A0fmt */ 7707 /* format MMU_TO_IP_IBP_STATUSfmt */ 7708 /* nFields */ 1, 7709 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 7710 /* bits */ 54, 7711 /* flags */ 0, 7712 }, 7713 #endif /* chips */ 7714 7715 #if defined(BCM_56334_A0) 7716 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56334_A0fmt */ 7717 /* format MMU_TO_IP_IBP_STATUSfmt */ 7718 /* nFields */ 1, 7719 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56334_A0fmt_fields, 7720 /* bits */ 30, 7721 /* flags */ 0, 7722 }, 7723 #endif /* chips */ 7724 7725 #if defined(BCM_56334_B0) 7726 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56334_B0fmt */ 7727 /* format MMU_TO_IP_IBP_STATUSfmt */ 7728 /* nFields */ 1, 7729 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56334_A0fmt_fields, 7730 /* bits */ 30, 7731 /* flags */ 0, 7732 }, 7733 #endif /* chips */ 7734 7735 #if defined(BCM_56340_A0) 7736 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56340_A0fmt */ 7737 /* format MMU_TO_IP_IBP_STATUSfmt */ 7738 /* nFields */ 1, 7739 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 7740 /* bits */ 54, 7741 /* flags */ 0, 7742 }, 7743 #endif /* chips */ 7744 7745 #if defined(BCM_56440_A0) 7746 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56440_A0fmt */ 7747 /* format MMU_TO_IP_IBP_STATUSfmt */ 7748 /* nFields */ 1, 7749 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7750 /* bits */ 54, 7751 /* flags */ 0, 7752 }, 7753 #endif /* chips */ 7754 7755 #if defined(BCM_56440_B0) 7756 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56440_B0fmt */ 7757 /* format MMU_TO_IP_IBP_STATUSfmt */ 7758 /* nFields */ 1, 7759 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7760 /* bits */ 54, 7761 /* flags */ 0, 7762 }, 7763 #endif /* chips */ 7764 7765 #if defined(BCM_56450_A0) 7766 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56450_A0fmt */ 7767 /* format MMU_TO_IP_IBP_STATUSfmt */ 7768 /* nFields */ 1, 7769 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 7770 /* bits */ 54, 7771 /* flags */ 0, 7772 }, 7773 #endif /* chips */ 7774 7775 #if defined(BCM_56450_B0) 7776 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56450_B0fmt */ 7777 /* format MMU_TO_IP_IBP_STATUSfmt */ 7778 /* nFields */ 1, 7779 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 7780 /* bits */ 54, 7781 /* flags */ 0, 7782 }, 7783 #endif /* chips */ 7784 7785 #if defined(BCM_56450_B1) 7786 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56450_B1fmt */ 7787 /* format MMU_TO_IP_IBP_STATUSfmt */ 7788 /* nFields */ 1, 7789 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 7790 /* bits */ 54, 7791 /* flags */ 0, 7792 }, 7793 #endif /* chips */ 7794 7795 #if defined(BCM_56524_A0) 7796 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56524_A0fmt */ 7797 /* format MMU_TO_IP_IBP_STATUSfmt */ 7798 /* nFields */ 1, 7799 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7800 /* bits */ 54, 7801 /* flags */ 0, 7802 }, 7803 #endif /* chips */ 7804 7805 #if defined(BCM_56524_B0) 7806 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56524_B0fmt */ 7807 /* format MMU_TO_IP_IBP_STATUSfmt */ 7808 /* nFields */ 1, 7809 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7810 /* bits */ 54, 7811 /* flags */ 0, 7812 }, 7813 #endif /* chips */ 7814 7815 #if defined(BCM_56560_A0) 7816 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56560_A0fmt */ 7817 /* format MMU_TO_IP_IBP_STATUSfmt */ 7818 /* nFields */ 1, 7819 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 7820 /* bits */ 54, 7821 /* flags */ 0, 7822 }, 7823 #endif /* chips */ 7824 7825 #if defined(BCM_56560_B0) 7826 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56560_B0fmt */ 7827 /* format MMU_TO_IP_IBP_STATUSfmt */ 7828 /* nFields */ 1, 7829 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 7830 /* bits */ 54, 7831 /* flags */ 0, 7832 }, 7833 #endif /* chips */ 7834 7835 #if defined(BCM_56624_A0) 7836 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56624_A0fmt */ 7837 /* format MMU_TO_IP_IBP_STATUSfmt */ 7838 /* nFields */ 1, 7839 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7840 /* bits */ 54, 7841 /* flags */ 0, 7842 }, 7843 #endif /* chips */ 7844 7845 #if defined(BCM_56624_B0) 7846 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56624_B0fmt */ 7847 /* format MMU_TO_IP_IBP_STATUSfmt */ 7848 /* nFields */ 1, 7849 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7850 /* bits */ 54, 7851 /* flags */ 0, 7852 }, 7853 #endif /* chips */ 7854 7855 #if defined(BCM_56634_A0) 7856 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56634_A0fmt */ 7857 /* format MMU_TO_IP_IBP_STATUSfmt */ 7858 /* nFields */ 1, 7859 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7860 /* bits */ 54, 7861 /* flags */ 0, 7862 }, 7863 #endif /* chips */ 7864 7865 #if defined(BCM_56634_B0) 7866 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56634_B0fmt */ 7867 /* format MMU_TO_IP_IBP_STATUSfmt */ 7868 /* nFields */ 1, 7869 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7870 /* bits */ 54, 7871 /* flags */ 0, 7872 }, 7873 #endif /* chips */ 7874 7875 #if defined(BCM_56640_A0) 7876 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56640_A0fmt */ 7877 /* format MMU_TO_IP_IBP_STATUSfmt */ 7878 /* nFields */ 1, 7879 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 7880 /* bits */ 54, 7881 /* flags */ 0, 7882 }, 7883 #endif /* chips */ 7884 7885 #if defined(BCM_56670_A0) 7886 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56670_A0fmt */ 7887 /* format MMU_TO_IP_IBP_STATUSfmt */ 7888 /* nFields */ 1, 7889 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 7890 /* bits */ 54, 7891 /* flags */ 0, 7892 }, 7893 #endif /* chips */ 7894 7895 #if defined(BCM_56670_B0) 7896 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56670_B0fmt */ 7897 /* format MMU_TO_IP_IBP_STATUSfmt */ 7898 /* nFields */ 1, 7899 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 7900 /* bits */ 54, 7901 /* flags */ 0, 7902 }, 7903 #endif /* chips */ 7904 7905 #if defined(BCM_56680_A0) 7906 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56680_A0fmt */ 7907 /* format MMU_TO_IP_IBP_STATUSfmt */ 7908 /* nFields */ 1, 7909 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7910 /* bits */ 54, 7911 /* flags */ 0, 7912 }, 7913 #endif /* chips */ 7914 7915 #if defined(BCM_56680_B0) 7916 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56680_B0fmt */ 7917 /* format MMU_TO_IP_IBP_STATUSfmt */ 7918 /* nFields */ 1, 7919 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7920 /* bits */ 54, 7921 /* flags */ 0, 7922 }, 7923 #endif /* chips */ 7924 7925 #if defined(BCM_56685_A0) 7926 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56685_A0fmt */ 7927 /* format MMU_TO_IP_IBP_STATUSfmt */ 7928 /* nFields */ 1, 7929 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7930 /* bits */ 54, 7931 /* flags */ 0, 7932 }, 7933 #endif /* chips */ 7934 7935 #if defined(BCM_56685_B0) 7936 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56685_B0fmt */ 7937 /* format MMU_TO_IP_IBP_STATUSfmt */ 7938 /* nFields */ 1, 7939 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7940 /* bits */ 54, 7941 /* flags */ 0, 7942 }, 7943 #endif /* chips */ 7944 7945 #if defined(BCM_56725_A0) 7946 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56725_A0fmt */ 7947 /* format MMU_TO_IP_IBP_STATUSfmt */ 7948 /* nFields */ 1, 7949 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56820_A0fmt_fields, 7950 /* bits */ 29, 7951 /* flags */ 0, 7952 }, 7953 #endif /* chips */ 7954 7955 #if defined(BCM_56820_A0) 7956 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56820_A0fmt */ 7957 /* format MMU_TO_IP_IBP_STATUSfmt */ 7958 /* nFields */ 1, 7959 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56820_A0fmt_fields, 7960 /* bits */ 29, 7961 /* flags */ 0, 7962 }, 7963 #endif /* chips */ 7964 7965 #if defined(BCM_56840_A0) 7966 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56840_A0fmt */ 7967 /* format MMU_TO_IP_IBP_STATUSfmt */ 7968 /* nFields */ 1, 7969 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7970 /* bits */ 54, 7971 /* flags */ 0, 7972 }, 7973 #endif /* chips */ 7974 7975 #if defined(BCM_56840_B0) 7976 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56840_B0fmt */ 7977 /* format MMU_TO_IP_IBP_STATUSfmt */ 7978 /* nFields */ 1, 7979 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56624_A0fmt_fields, 7980 /* bits */ 54, 7981 /* flags */ 0, 7982 }, 7983 #endif /* chips */ 7984 7985 #if defined(BCM_56850_A0) 7986 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56850_A0fmt */ 7987 /* format MMU_TO_IP_IBP_STATUSfmt */ 7988 /* nFields */ 1, 7989 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 7990 /* bits */ 54, 7991 /* flags */ 0, 7992 }, 7993 #endif /* chips */ 7994 7995 #if defined(BCM_56860_A0) 7996 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56860_A0fmt */ 7997 /* format MMU_TO_IP_IBP_STATUSfmt */ 7998 /* nFields */ 1, 7999 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56640_A0fmt_fields, 8000 /* bits */ 54, 8001 /* flags */ 0, 8002 }, 8003 #endif /* chips */ 8004 8005 #if defined(BCM_56960_A0) 8006 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56960_A0fmt */ 8007 /* format MMU_TO_IP_IBP_STATUSfmt */ 8008 /* nFields */ 1, 8009 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 8010 /* bits */ 54, 8011 /* flags */ 0, 8012 }, 8013 #endif /* chips */ 8014 8015 #if defined(BCM_56965_A0) 8016 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56965_A0fmt */ 8017 /* format MMU_TO_IP_IBP_STATUSfmt */ 8018 /* nFields */ 1, 8019 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 8020 /* bits */ 54, 8021 /* flags */ 0, 8022 }, 8023 #endif /* chips */ 8024 8025 #if defined(BCM_56970_A0) 8026 { /* SOC_FORMAT_INT_MMU_TO_IP_IBP_STATUS_BCM56970_A0fmt */ 8027 /* format MMU_TO_IP_IBP_STATUSfmt */ 8028 /* nFields */ 1, 8029 /* *fields */ soc_MMU_TO_IP_HOL_STATUS_BCM56960_A0fmt_fields, 8030 /* bits */ 54, 8031 /* flags */ 0, 8032 }, 8033 #endif /* chips */ 8034 8035 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 8036 { /* SOC_FORMAT_INT_MMU_TO_IP_OAM_LM_BUSfmt */ 8037 /* format MMU_TO_IP_OAM_LM_BUSfmt */ 8038 /* nFields */ 5, 8039 /* *fields */ soc_MMU_TO_IP_OAM_LM_BUSfmt_fields, 8040 /* bits */ 16, 8041 /* flags */ 0, 8042 }, 8043 #endif /* chips */ 8044 8045 #if defined(BCM_56624_A0) 8046 { /* SOC_FORMAT_INT_MMU_TO_XGP_BKPfmt */ 8047 /* format MMU_TO_XGP_BKPfmt */ 8048 /* nFields */ 1, 8049 /* *fields */ soc_MMU_TO_XGP_BKPfmt_fields, 8050 /* bits */ 12, 8051 /* flags */ 0, 8052 }, 8053 #endif /* chips */ 8054 8055 #if defined(BCM_56334_A0) 8056 { /* SOC_FORMAT_INT_MMU_TO_XGP_BKP_BCM56334_A0fmt */ 8057 /* format MMU_TO_XGP_BKPfmt */ 8058 /* nFields */ 1, 8059 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8060 /* bits */ 8, 8061 /* flags */ 0, 8062 }, 8063 #endif /* chips */ 8064 8065 #if defined(BCM_56334_B0) 8066 { /* SOC_FORMAT_INT_MMU_TO_XGP_BKP_BCM56334_B0fmt */ 8067 /* format MMU_TO_XGP_BKPfmt */ 8068 /* nFields */ 1, 8069 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8070 /* bits */ 8, 8071 /* flags */ 0, 8072 }, 8073 #endif /* chips */ 8074 8075 #if defined(BCM_56624_B0) 8076 { /* SOC_FORMAT_INT_MMU_TO_XGP_BKP_BCM56624_B0fmt */ 8077 /* format MMU_TO_XGP_BKPfmt */ 8078 /* nFields */ 1, 8079 /* *fields */ soc_MMU_TO_XGP_BKPfmt_fields, 8080 /* bits */ 12, 8081 /* flags */ 0, 8082 }, 8083 #endif /* chips */ 8084 8085 #if defined(BCM_56680_A0) 8086 { /* SOC_FORMAT_INT_MMU_TO_XGP_BKP_BCM56680_A0fmt */ 8087 /* format MMU_TO_XGP_BKPfmt */ 8088 /* nFields */ 1, 8089 /* *fields */ soc_MMU_TO_XGP_BKPfmt_fields, 8090 /* bits */ 12, 8091 /* flags */ 0, 8092 }, 8093 #endif /* chips */ 8094 8095 #if defined(BCM_56680_B0) 8096 { /* SOC_FORMAT_INT_MMU_TO_XGP_BKP_BCM56680_B0fmt */ 8097 /* format MMU_TO_XGP_BKPfmt */ 8098 /* nFields */ 1, 8099 /* *fields */ soc_MMU_TO_XGP_BKPfmt_fields, 8100 /* bits */ 12, 8101 /* flags */ 0, 8102 }, 8103 #endif /* chips */ 8104 8105 #if defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 8106 defined(BCM_56634_B0) 8107 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUSfmt */ 8108 /* format MMU_TO_XGP_E2E_BUSfmt */ 8109 /* nFields */ 1, 8110 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8111 /* bits */ 8, 8112 /* flags */ 0, 8113 }, 8114 #endif /* chips */ 8115 8116 #if defined(BCM_56260_A0) 8117 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt */ 8118 /* format MMU_TO_XGP_E2E_BUSfmt */ 8119 /* nFields */ 1, 8120 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8121 /* bits */ 16, 8122 /* flags */ 0, 8123 }, 8124 #endif /* chips */ 8125 8126 #if defined(BCM_56260_B0) 8127 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56260_B0fmt */ 8128 /* format MMU_TO_XGP_E2E_BUSfmt */ 8129 /* nFields */ 1, 8130 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8131 /* bits */ 16, 8132 /* flags */ 0, 8133 }, 8134 #endif /* chips */ 8135 8136 #if defined(BCM_56270_A0) 8137 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56270_A0fmt */ 8138 /* format MMU_TO_XGP_E2E_BUSfmt */ 8139 /* nFields */ 1, 8140 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8141 /* bits */ 16, 8142 /* flags */ 0, 8143 }, 8144 #endif /* chips */ 8145 8146 #if defined(BCM_56334_A0) 8147 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56334_A0fmt */ 8148 /* format MMU_TO_XGP_E2E_BUSfmt */ 8149 /* nFields */ 1, 8150 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8151 /* bits */ 8, 8152 /* flags */ 0, 8153 }, 8154 #endif /* chips */ 8155 8156 #if defined(BCM_56334_B0) 8157 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56334_B0fmt */ 8158 /* format MMU_TO_XGP_E2E_BUSfmt */ 8159 /* nFields */ 1, 8160 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8161 /* bits */ 8, 8162 /* flags */ 0, 8163 }, 8164 #endif /* chips */ 8165 8166 #if defined(BCM_56340_A0) 8167 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56340_A0fmt */ 8168 /* format MMU_TO_XGP_E2E_BUSfmt */ 8169 /* nFields */ 1, 8170 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8171 /* bits */ 8, 8172 /* flags */ 0, 8173 }, 8174 #endif /* chips */ 8175 8176 #if defined(BCM_56440_A0) 8177 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56440_A0fmt */ 8178 /* format MMU_TO_XGP_E2E_BUSfmt */ 8179 /* nFields */ 1, 8180 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8181 /* bits */ 8, 8182 /* flags */ 0, 8183 }, 8184 #endif /* chips */ 8185 8186 #if defined(BCM_56440_B0) 8187 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56440_B0fmt */ 8188 /* format MMU_TO_XGP_E2E_BUSfmt */ 8189 /* nFields */ 1, 8190 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8191 /* bits */ 8, 8192 /* flags */ 0, 8193 }, 8194 #endif /* chips */ 8195 8196 #if defined(BCM_56450_A0) 8197 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56450_A0fmt */ 8198 /* format MMU_TO_XGP_E2E_BUSfmt */ 8199 /* nFields */ 1, 8200 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8201 /* bits */ 8, 8202 /* flags */ 0, 8203 }, 8204 #endif /* chips */ 8205 8206 #if defined(BCM_56450_B0) 8207 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56450_B0fmt */ 8208 /* format MMU_TO_XGP_E2E_BUSfmt */ 8209 /* nFields */ 1, 8210 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8211 /* bits */ 8, 8212 /* flags */ 0, 8213 }, 8214 #endif /* chips */ 8215 8216 #if defined(BCM_56450_B1) 8217 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56450_B1fmt */ 8218 /* format MMU_TO_XGP_E2E_BUSfmt */ 8219 /* nFields */ 1, 8220 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8221 /* bits */ 8, 8222 /* flags */ 0, 8223 }, 8224 #endif /* chips */ 8225 8226 #if defined(BCM_56524_A0) 8227 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56524_A0fmt */ 8228 /* format MMU_TO_XGP_E2E_BUSfmt */ 8229 /* nFields */ 1, 8230 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8231 /* bits */ 8, 8232 /* flags */ 0, 8233 }, 8234 #endif /* chips */ 8235 8236 #if defined(BCM_56524_B0) 8237 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56524_B0fmt */ 8238 /* format MMU_TO_XGP_E2E_BUSfmt */ 8239 /* nFields */ 1, 8240 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8241 /* bits */ 8, 8242 /* flags */ 0, 8243 }, 8244 #endif /* chips */ 8245 8246 #if defined(BCM_56560_A0) 8247 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56560_A0fmt */ 8248 /* format MMU_TO_XGP_E2E_BUSfmt */ 8249 /* nFields */ 1, 8250 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8251 /* bits */ 8, 8252 /* flags */ 0, 8253 }, 8254 #endif /* chips */ 8255 8256 #if defined(BCM_56560_B0) 8257 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56560_B0fmt */ 8258 /* format MMU_TO_XGP_E2E_BUSfmt */ 8259 /* nFields */ 1, 8260 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8261 /* bits */ 8, 8262 /* flags */ 0, 8263 }, 8264 #endif /* chips */ 8265 8266 #if defined(BCM_56624_B0) 8267 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56624_B0fmt */ 8268 /* format MMU_TO_XGP_E2E_BUSfmt */ 8269 /* nFields */ 1, 8270 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8271 /* bits */ 8, 8272 /* flags */ 0, 8273 }, 8274 #endif /* chips */ 8275 8276 #if defined(BCM_56640_A0) 8277 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt */ 8278 /* format MMU_TO_XGP_E2E_BUSfmt */ 8279 /* nFields */ 1, 8280 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8281 /* bits */ 8, 8282 /* flags */ 0, 8283 }, 8284 #endif /* chips */ 8285 8286 #if defined(BCM_56670_A0) 8287 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56670_A0fmt */ 8288 /* format MMU_TO_XGP_E2E_BUSfmt */ 8289 /* nFields */ 1, 8290 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8291 /* bits */ 8, 8292 /* flags */ 0, 8293 }, 8294 #endif /* chips */ 8295 8296 #if defined(BCM_56670_B0) 8297 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56670_B0fmt */ 8298 /* format MMU_TO_XGP_E2E_BUSfmt */ 8299 /* nFields */ 1, 8300 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8301 /* bits */ 8, 8302 /* flags */ 0, 8303 }, 8304 #endif /* chips */ 8305 8306 #if defined(BCM_56680_A0) 8307 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56680_A0fmt */ 8308 /* format MMU_TO_XGP_E2E_BUSfmt */ 8309 /* nFields */ 1, 8310 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8311 /* bits */ 8, 8312 /* flags */ 0, 8313 }, 8314 #endif /* chips */ 8315 8316 #if defined(BCM_56680_B0) 8317 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56680_B0fmt */ 8318 /* format MMU_TO_XGP_E2E_BUSfmt */ 8319 /* nFields */ 1, 8320 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8321 /* bits */ 8, 8322 /* flags */ 0, 8323 }, 8324 #endif /* chips */ 8325 8326 #if defined(BCM_56685_A0) 8327 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56685_A0fmt */ 8328 /* format MMU_TO_XGP_E2E_BUSfmt */ 8329 /* nFields */ 1, 8330 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8331 /* bits */ 8, 8332 /* flags */ 0, 8333 }, 8334 #endif /* chips */ 8335 8336 #if defined(BCM_56685_B0) 8337 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56685_B0fmt */ 8338 /* format MMU_TO_XGP_E2E_BUSfmt */ 8339 /* nFields */ 1, 8340 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8341 /* bits */ 8, 8342 /* flags */ 0, 8343 }, 8344 #endif /* chips */ 8345 8346 #if defined(BCM_56840_A0) 8347 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56840_A0fmt */ 8348 /* format MMU_TO_XGP_E2E_BUSfmt */ 8349 /* nFields */ 1, 8350 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8351 /* bits */ 8, 8352 /* flags */ 0, 8353 }, 8354 #endif /* chips */ 8355 8356 #if defined(BCM_56840_B0) 8357 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56840_B0fmt */ 8358 /* format MMU_TO_XGP_E2E_BUSfmt */ 8359 /* nFields */ 1, 8360 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8361 /* bits */ 8, 8362 /* flags */ 0, 8363 }, 8364 #endif /* chips */ 8365 8366 #if defined(BCM_56850_A0) 8367 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56850_A0fmt */ 8368 /* format MMU_TO_XGP_E2E_BUSfmt */ 8369 /* nFields */ 1, 8370 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8371 /* bits */ 8, 8372 /* flags */ 0, 8373 }, 8374 #endif /* chips */ 8375 8376 #if defined(BCM_56860_A0) 8377 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56860_A0fmt */ 8378 /* format MMU_TO_XGP_E2E_BUSfmt */ 8379 /* nFields */ 1, 8380 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8381 /* bits */ 8, 8382 /* flags */ 0, 8383 }, 8384 #endif /* chips */ 8385 8386 #if defined(BCM_56960_A0) 8387 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56960_A0fmt */ 8388 /* format MMU_TO_XGP_E2E_BUSfmt */ 8389 /* nFields */ 1, 8390 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8391 /* bits */ 8, 8392 /* flags */ 0, 8393 }, 8394 #endif /* chips */ 8395 8396 #if defined(BCM_56965_A0) 8397 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56965_A0fmt */ 8398 /* format MMU_TO_XGP_E2E_BUSfmt */ 8399 /* nFields */ 1, 8400 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8401 /* bits */ 8, 8402 /* flags */ 0, 8403 }, 8404 #endif /* chips */ 8405 8406 #if defined(BCM_56970_A0) 8407 { /* SOC_FORMAT_INT_MMU_TO_XGP_E2E_BUS_BCM56970_A0fmt */ 8408 /* format MMU_TO_XGP_E2E_BUSfmt */ 8409 /* nFields */ 1, 8410 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8411 /* bits */ 8, 8412 /* flags */ 0, 8413 }, 8414 #endif /* chips */ 8415 8416 #if defined(BCM_56624_A0) 8417 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUSfmt */ 8418 /* format MMU_TO_XP_E2E_BUSfmt */ 8419 /* nFields */ 1, 8420 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8421 /* bits */ 8, 8422 /* flags */ 0, 8423 }, 8424 #endif /* chips */ 8425 8426 #if defined(BCM_53400_A0) 8427 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM53400_A0fmt */ 8428 /* format MMU_TO_XP_E2E_BUSfmt */ 8429 /* nFields */ 1, 8430 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8431 /* bits */ 8, 8432 /* flags */ 0, 8433 }, 8434 #endif /* chips */ 8435 8436 #if defined(BCM_53540_A0) 8437 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM53540_A0fmt */ 8438 /* format MMU_TO_XP_E2E_BUSfmt */ 8439 /* nFields */ 1, 8440 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8441 /* bits */ 8, 8442 /* flags */ 0, 8443 }, 8444 #endif /* chips */ 8445 8446 #if defined(BCM_56142_A0) 8447 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56142_A0fmt */ 8448 /* format MMU_TO_XP_E2E_BUSfmt */ 8449 /* nFields */ 1, 8450 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8451 /* bits */ 8, 8452 /* flags */ 0, 8453 }, 8454 #endif /* chips */ 8455 8456 #if defined(BCM_56150_A0) 8457 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56150_A0fmt */ 8458 /* format MMU_TO_XP_E2E_BUSfmt */ 8459 /* nFields */ 1, 8460 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8461 /* bits */ 8, 8462 /* flags */ 0, 8463 }, 8464 #endif /* chips */ 8465 8466 #if defined(BCM_56160_A0) 8467 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56160_A0fmt */ 8468 /* format MMU_TO_XP_E2E_BUSfmt */ 8469 /* nFields */ 1, 8470 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8471 /* bits */ 8, 8472 /* flags */ 0, 8473 }, 8474 #endif /* chips */ 8475 8476 #if defined(BCM_56260_A0) 8477 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56260_A0fmt */ 8478 /* format MMU_TO_XP_E2E_BUSfmt */ 8479 /* nFields */ 1, 8480 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8481 /* bits */ 16, 8482 /* flags */ 0, 8483 }, 8484 #endif /* chips */ 8485 8486 #if defined(BCM_56260_B0) 8487 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56260_B0fmt */ 8488 /* format MMU_TO_XP_E2E_BUSfmt */ 8489 /* nFields */ 1, 8490 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8491 /* bits */ 16, 8492 /* flags */ 0, 8493 }, 8494 #endif /* chips */ 8495 8496 #if defined(BCM_56270_A0) 8497 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56270_A0fmt */ 8498 /* format MMU_TO_XP_E2E_BUSfmt */ 8499 /* nFields */ 1, 8500 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8501 /* bits */ 16, 8502 /* flags */ 0, 8503 }, 8504 #endif /* chips */ 8505 8506 #if defined(BCM_56334_A0) 8507 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56334_A0fmt */ 8508 /* format MMU_TO_XP_E2E_BUSfmt */ 8509 /* nFields */ 1, 8510 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8511 /* bits */ 8, 8512 /* flags */ 0, 8513 }, 8514 #endif /* chips */ 8515 8516 #if defined(BCM_56334_B0) 8517 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56334_B0fmt */ 8518 /* format MMU_TO_XP_E2E_BUSfmt */ 8519 /* nFields */ 1, 8520 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8521 /* bits */ 8, 8522 /* flags */ 0, 8523 }, 8524 #endif /* chips */ 8525 8526 #if defined(BCM_56340_A0) 8527 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56340_A0fmt */ 8528 /* format MMU_TO_XP_E2E_BUSfmt */ 8529 /* nFields */ 1, 8530 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8531 /* bits */ 8, 8532 /* flags */ 0, 8533 }, 8534 #endif /* chips */ 8535 8536 #if defined(BCM_56440_A0) 8537 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56440_A0fmt */ 8538 /* format MMU_TO_XP_E2E_BUSfmt */ 8539 /* nFields */ 1, 8540 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8541 /* bits */ 8, 8542 /* flags */ 0, 8543 }, 8544 #endif /* chips */ 8545 8546 #if defined(BCM_56440_B0) 8547 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56440_B0fmt */ 8548 /* format MMU_TO_XP_E2E_BUSfmt */ 8549 /* nFields */ 1, 8550 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8551 /* bits */ 8, 8552 /* flags */ 0, 8553 }, 8554 #endif /* chips */ 8555 8556 #if defined(BCM_56450_A0) 8557 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56450_A0fmt */ 8558 /* format MMU_TO_XP_E2E_BUSfmt */ 8559 /* nFields */ 1, 8560 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8561 /* bits */ 8, 8562 /* flags */ 0, 8563 }, 8564 #endif /* chips */ 8565 8566 #if defined(BCM_56450_B0) 8567 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56450_B0fmt */ 8568 /* format MMU_TO_XP_E2E_BUSfmt */ 8569 /* nFields */ 1, 8570 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8571 /* bits */ 8, 8572 /* flags */ 0, 8573 }, 8574 #endif /* chips */ 8575 8576 #if defined(BCM_56450_B1) 8577 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56450_B1fmt */ 8578 /* format MMU_TO_XP_E2E_BUSfmt */ 8579 /* nFields */ 1, 8580 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8581 /* bits */ 8, 8582 /* flags */ 0, 8583 }, 8584 #endif /* chips */ 8585 8586 #if defined(BCM_56524_A0) 8587 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56524_A0fmt */ 8588 /* format MMU_TO_XP_E2E_BUSfmt */ 8589 /* nFields */ 1, 8590 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8591 /* bits */ 8, 8592 /* flags */ 0, 8593 }, 8594 #endif /* chips */ 8595 8596 #if defined(BCM_56524_B0) 8597 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56524_B0fmt */ 8598 /* format MMU_TO_XP_E2E_BUSfmt */ 8599 /* nFields */ 1, 8600 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8601 /* bits */ 8, 8602 /* flags */ 0, 8603 }, 8604 #endif /* chips */ 8605 8606 #if defined(BCM_56560_A0) 8607 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56560_A0fmt */ 8608 /* format MMU_TO_XP_E2E_BUSfmt */ 8609 /* nFields */ 1, 8610 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8611 /* bits */ 8, 8612 /* flags */ 0, 8613 }, 8614 #endif /* chips */ 8615 8616 #if defined(BCM_56560_B0) 8617 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56560_B0fmt */ 8618 /* format MMU_TO_XP_E2E_BUSfmt */ 8619 /* nFields */ 1, 8620 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8621 /* bits */ 8, 8622 /* flags */ 0, 8623 }, 8624 #endif /* chips */ 8625 8626 #if defined(BCM_56624_B0) 8627 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56624_B0fmt */ 8628 /* format MMU_TO_XP_E2E_BUSfmt */ 8629 /* nFields */ 1, 8630 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8631 /* bits */ 8, 8632 /* flags */ 0, 8633 }, 8634 #endif /* chips */ 8635 8636 #if defined(BCM_56634_A0) 8637 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56634_A0fmt */ 8638 /* format MMU_TO_XP_E2E_BUSfmt */ 8639 /* nFields */ 1, 8640 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8641 /* bits */ 8, 8642 /* flags */ 0, 8643 }, 8644 #endif /* chips */ 8645 8646 #if defined(BCM_56634_B0) 8647 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56634_B0fmt */ 8648 /* format MMU_TO_XP_E2E_BUSfmt */ 8649 /* nFields */ 1, 8650 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8651 /* bits */ 8, 8652 /* flags */ 0, 8653 }, 8654 #endif /* chips */ 8655 8656 #if defined(BCM_56640_A0) 8657 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56640_A0fmt */ 8658 /* format MMU_TO_XP_E2E_BUSfmt */ 8659 /* nFields */ 1, 8660 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8661 /* bits */ 8, 8662 /* flags */ 0, 8663 }, 8664 #endif /* chips */ 8665 8666 #if defined(BCM_56670_A0) 8667 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56670_A0fmt */ 8668 /* format MMU_TO_XP_E2E_BUSfmt */ 8669 /* nFields */ 1, 8670 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8671 /* bits */ 8, 8672 /* flags */ 0, 8673 }, 8674 #endif /* chips */ 8675 8676 #if defined(BCM_56670_B0) 8677 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56670_B0fmt */ 8678 /* format MMU_TO_XP_E2E_BUSfmt */ 8679 /* nFields */ 1, 8680 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8681 /* bits */ 8, 8682 /* flags */ 0, 8683 }, 8684 #endif /* chips */ 8685 8686 #if defined(BCM_56680_A0) 8687 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56680_A0fmt */ 8688 /* format MMU_TO_XP_E2E_BUSfmt */ 8689 /* nFields */ 1, 8690 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8691 /* bits */ 8, 8692 /* flags */ 0, 8693 }, 8694 #endif /* chips */ 8695 8696 #if defined(BCM_56680_B0) 8697 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56680_B0fmt */ 8698 /* format MMU_TO_XP_E2E_BUSfmt */ 8699 /* nFields */ 1, 8700 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8701 /* bits */ 8, 8702 /* flags */ 0, 8703 }, 8704 #endif /* chips */ 8705 8706 #if defined(BCM_56685_A0) 8707 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56685_A0fmt */ 8708 /* format MMU_TO_XP_E2E_BUSfmt */ 8709 /* nFields */ 1, 8710 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8711 /* bits */ 8, 8712 /* flags */ 0, 8713 }, 8714 #endif /* chips */ 8715 8716 #if defined(BCM_56685_B0) 8717 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56685_B0fmt */ 8718 /* format MMU_TO_XP_E2E_BUSfmt */ 8719 /* nFields */ 1, 8720 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8721 /* bits */ 8, 8722 /* flags */ 0, 8723 }, 8724 #endif /* chips */ 8725 8726 #if defined(BCM_56840_A0) 8727 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56840_A0fmt */ 8728 /* format MMU_TO_XP_E2E_BUSfmt */ 8729 /* nFields */ 1, 8730 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8731 /* bits */ 8, 8732 /* flags */ 0, 8733 }, 8734 #endif /* chips */ 8735 8736 #if defined(BCM_56840_B0) 8737 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56840_B0fmt */ 8738 /* format MMU_TO_XP_E2E_BUSfmt */ 8739 /* nFields */ 1, 8740 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8741 /* bits */ 8, 8742 /* flags */ 0, 8743 }, 8744 #endif /* chips */ 8745 8746 #if defined(BCM_56850_A0) 8747 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56850_A0fmt */ 8748 /* format MMU_TO_XP_E2E_BUSfmt */ 8749 /* nFields */ 1, 8750 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8751 /* bits */ 8, 8752 /* flags */ 0, 8753 }, 8754 #endif /* chips */ 8755 8756 #if defined(BCM_56860_A0) 8757 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56860_A0fmt */ 8758 /* format MMU_TO_XP_E2E_BUSfmt */ 8759 /* nFields */ 1, 8760 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8761 /* bits */ 8, 8762 /* flags */ 0, 8763 }, 8764 #endif /* chips */ 8765 8766 #if defined(BCM_56960_A0) 8767 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56960_A0fmt */ 8768 /* format MMU_TO_XP_E2E_BUSfmt */ 8769 /* nFields */ 1, 8770 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8771 /* bits */ 8, 8772 /* flags */ 0, 8773 }, 8774 #endif /* chips */ 8775 8776 #if defined(BCM_56965_A0) 8777 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56965_A0fmt */ 8778 /* format MMU_TO_XP_E2E_BUSfmt */ 8779 /* nFields */ 1, 8780 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8781 /* bits */ 8, 8782 /* flags */ 0, 8783 }, 8784 #endif /* chips */ 8785 8786 #if defined(BCM_56970_A0) 8787 { /* SOC_FORMAT_INT_MMU_TO_XP_E2E_BUS_BCM56970_A0fmt */ 8788 /* format MMU_TO_XP_E2E_BUSfmt */ 8789 /* nFields */ 1, 8790 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8791 /* bits */ 8, 8792 /* flags */ 0, 8793 }, 8794 #endif /* chips */ 8795 8796 #if defined(BCM_56634_A0) 8797 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUSfmt */ 8798 /* format MMU_TO_XQP_E2E_BUSfmt */ 8799 /* nFields */ 1, 8800 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8801 /* bits */ 8, 8802 /* flags */ 0, 8803 }, 8804 #endif /* chips */ 8805 8806 #if defined(BCM_56260_A0) 8807 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56260_A0fmt */ 8808 /* format MMU_TO_XQP_E2E_BUSfmt */ 8809 /* nFields */ 1, 8810 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8811 /* bits */ 16, 8812 /* flags */ 0, 8813 }, 8814 #endif /* chips */ 8815 8816 #if defined(BCM_56260_B0) 8817 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56260_B0fmt */ 8818 /* format MMU_TO_XQP_E2E_BUSfmt */ 8819 /* nFields */ 1, 8820 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8821 /* bits */ 16, 8822 /* flags */ 0, 8823 }, 8824 #endif /* chips */ 8825 8826 #if defined(BCM_56270_A0) 8827 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56270_A0fmt */ 8828 /* format MMU_TO_XQP_E2E_BUSfmt */ 8829 /* nFields */ 1, 8830 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56260_A0fmt_fields, 8831 /* bits */ 16, 8832 /* flags */ 0, 8833 }, 8834 #endif /* chips */ 8835 8836 #if defined(BCM_56340_A0) 8837 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56340_A0fmt */ 8838 /* format MMU_TO_XQP_E2E_BUSfmt */ 8839 /* nFields */ 1, 8840 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8841 /* bits */ 8, 8842 /* flags */ 0, 8843 }, 8844 #endif /* chips */ 8845 8846 #if defined(BCM_56440_A0) 8847 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56440_A0fmt */ 8848 /* format MMU_TO_XQP_E2E_BUSfmt */ 8849 /* nFields */ 1, 8850 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8851 /* bits */ 8, 8852 /* flags */ 0, 8853 }, 8854 #endif /* chips */ 8855 8856 #if defined(BCM_56440_B0) 8857 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56440_B0fmt */ 8858 /* format MMU_TO_XQP_E2E_BUSfmt */ 8859 /* nFields */ 1, 8860 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8861 /* bits */ 8, 8862 /* flags */ 0, 8863 }, 8864 #endif /* chips */ 8865 8866 #if defined(BCM_56450_A0) 8867 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56450_A0fmt */ 8868 /* format MMU_TO_XQP_E2E_BUSfmt */ 8869 /* nFields */ 1, 8870 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8871 /* bits */ 8, 8872 /* flags */ 0, 8873 }, 8874 #endif /* chips */ 8875 8876 #if defined(BCM_56450_B0) 8877 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56450_B0fmt */ 8878 /* format MMU_TO_XQP_E2E_BUSfmt */ 8879 /* nFields */ 1, 8880 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8881 /* bits */ 8, 8882 /* flags */ 0, 8883 }, 8884 #endif /* chips */ 8885 8886 #if defined(BCM_56450_B1) 8887 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56450_B1fmt */ 8888 /* format MMU_TO_XQP_E2E_BUSfmt */ 8889 /* nFields */ 1, 8890 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8891 /* bits */ 8, 8892 /* flags */ 0, 8893 }, 8894 #endif /* chips */ 8895 8896 #if defined(BCM_56524_A0) 8897 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56524_A0fmt */ 8898 /* format MMU_TO_XQP_E2E_BUSfmt */ 8899 /* nFields */ 1, 8900 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8901 /* bits */ 8, 8902 /* flags */ 0, 8903 }, 8904 #endif /* chips */ 8905 8906 #if defined(BCM_56524_B0) 8907 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56524_B0fmt */ 8908 /* format MMU_TO_XQP_E2E_BUSfmt */ 8909 /* nFields */ 1, 8910 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8911 /* bits */ 8, 8912 /* flags */ 0, 8913 }, 8914 #endif /* chips */ 8915 8916 #if defined(BCM_56560_A0) 8917 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56560_A0fmt */ 8918 /* format MMU_TO_XQP_E2E_BUSfmt */ 8919 /* nFields */ 1, 8920 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8921 /* bits */ 8, 8922 /* flags */ 0, 8923 }, 8924 #endif /* chips */ 8925 8926 #if defined(BCM_56560_B0) 8927 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56560_B0fmt */ 8928 /* format MMU_TO_XQP_E2E_BUSfmt */ 8929 /* nFields */ 1, 8930 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8931 /* bits */ 8, 8932 /* flags */ 0, 8933 }, 8934 #endif /* chips */ 8935 8936 #if defined(BCM_56634_B0) 8937 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56634_B0fmt */ 8938 /* format MMU_TO_XQP_E2E_BUSfmt */ 8939 /* nFields */ 1, 8940 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8941 /* bits */ 8, 8942 /* flags */ 0, 8943 }, 8944 #endif /* chips */ 8945 8946 #if defined(BCM_56640_A0) 8947 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56640_A0fmt */ 8948 /* format MMU_TO_XQP_E2E_BUSfmt */ 8949 /* nFields */ 1, 8950 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 8951 /* bits */ 8, 8952 /* flags */ 0, 8953 }, 8954 #endif /* chips */ 8955 8956 #if defined(BCM_56670_A0) 8957 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56670_A0fmt */ 8958 /* format MMU_TO_XQP_E2E_BUSfmt */ 8959 /* nFields */ 1, 8960 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8961 /* bits */ 8, 8962 /* flags */ 0, 8963 }, 8964 #endif /* chips */ 8965 8966 #if defined(BCM_56670_B0) 8967 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56670_B0fmt */ 8968 /* format MMU_TO_XQP_E2E_BUSfmt */ 8969 /* nFields */ 1, 8970 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 8971 /* bits */ 8, 8972 /* flags */ 0, 8973 }, 8974 #endif /* chips */ 8975 8976 #if defined(BCM_56685_A0) 8977 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56685_A0fmt */ 8978 /* format MMU_TO_XQP_E2E_BUSfmt */ 8979 /* nFields */ 1, 8980 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8981 /* bits */ 8, 8982 /* flags */ 0, 8983 }, 8984 #endif /* chips */ 8985 8986 #if defined(BCM_56685_B0) 8987 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56685_B0fmt */ 8988 /* format MMU_TO_XQP_E2E_BUSfmt */ 8989 /* nFields */ 1, 8990 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 8991 /* bits */ 8, 8992 /* flags */ 0, 8993 }, 8994 #endif /* chips */ 8995 8996 #if defined(BCM_56840_A0) 8997 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56840_A0fmt */ 8998 /* format MMU_TO_XQP_E2E_BUSfmt */ 8999 /* nFields */ 1, 9000 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 9001 /* bits */ 8, 9002 /* flags */ 0, 9003 }, 9004 #endif /* chips */ 9005 9006 #if defined(BCM_56840_B0) 9007 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56840_B0fmt */ 9008 /* format MMU_TO_XQP_E2E_BUSfmt */ 9009 /* nFields */ 1, 9010 /* *fields */ soc_MMU_TO_XGP_E2E_BUSfmt_fields, 9011 /* bits */ 8, 9012 /* flags */ 0, 9013 }, 9014 #endif /* chips */ 9015 9016 #if defined(BCM_56850_A0) 9017 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56850_A0fmt */ 9018 /* format MMU_TO_XQP_E2E_BUSfmt */ 9019 /* nFields */ 1, 9020 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 9021 /* bits */ 8, 9022 /* flags */ 0, 9023 }, 9024 #endif /* chips */ 9025 9026 #if defined(BCM_56860_A0) 9027 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56860_A0fmt */ 9028 /* format MMU_TO_XQP_E2E_BUSfmt */ 9029 /* nFields */ 1, 9030 /* *fields */ soc_MMU_TO_XGP_E2E_BUS_BCM56640_A0fmt_fields, 9031 /* bits */ 8, 9032 /* flags */ 0, 9033 }, 9034 #endif /* chips */ 9035 9036 #if defined(BCM_56960_A0) 9037 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56960_A0fmt */ 9038 /* format MMU_TO_XQP_E2E_BUSfmt */ 9039 /* nFields */ 1, 9040 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 9041 /* bits */ 8, 9042 /* flags */ 0, 9043 }, 9044 #endif /* chips */ 9045 9046 #if defined(BCM_56965_A0) 9047 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56965_A0fmt */ 9048 /* format MMU_TO_XQP_E2E_BUSfmt */ 9049 /* nFields */ 1, 9050 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 9051 /* bits */ 8, 9052 /* flags */ 0, 9053 }, 9054 #endif /* chips */ 9055 9056 #if defined(BCM_56970_A0) 9057 { /* SOC_FORMAT_INT_MMU_TO_XQP_E2E_BUS_BCM56970_A0fmt */ 9058 /* format MMU_TO_XQP_E2E_BUSfmt */ 9059 /* nFields */ 1, 9060 /* *fields */ soc_MMU_TO_XP_E2E_BUSfmt_fields, 9061 /* bits */ 8, 9062 /* flags */ 0, 9063 }, 9064 #endif /* chips */ 9065 9066 #if defined(BCM_56980_A0) 9067 { /* SOC_FORMAT_INT_MMU_WRED_TO_THDO_ENQ_ACCEPT_INFOfmt */ 9068 /* format MMU_WRED_TO_THDO_ENQ_ACCEPT_INFOfmt */ 9069 /* nFields */ 2, 9070 /* *fields */ soc_MMU_THDR_TO_CRB_ACCEPT_INFOfmt_fields, 9071 /* bits */ 2, 9072 /* flags */ 0, 9073 }, 9074 #endif /* chips */ 9075 9076 #if defined(BCM_56980_B0) 9077 { /* SOC_FORMAT_INT_MMU_WRED_TO_THDO_ENQ_ACCEPT_INFO_BCM56980_B0fmt */ 9078 /* format MMU_WRED_TO_THDO_ENQ_ACCEPT_INFOfmt */ 9079 /* nFields */ 2, 9080 /* *fields */ soc_MMU_THDR_TO_CRB_ACCEPT_INFOfmt_fields, 9081 /* bits */ 2, 9082 /* flags */ 0, 9083 }, 9084 #endif /* chips */ 9085 9086 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 9087 { /* SOC_FORMAT_INT_MMU_WRED_TO_TOQ_DEQ_FEEDBACKfmt */ 9088 /* format MMU_WRED_TO_TOQ_DEQ_FEEDBACKfmt */ 9089 /* nFields */ 13, 9090 /* *fields */ soc_MMU_WRED_TO_TOQ_DEQ_FEEDBACKfmt_fields, 9091 /* bits */ 13, 9092 /* flags */ 0, 9093 }, 9094 #endif /* chips */ 9095 9096 #if defined(BCM_56504_A0) 9097 { /* SOC_FORMAT_INT_MMU_XQHEADERfmt */ 9098 /* format MMU_XQHEADERfmt */ 9099 /* nFields */ 7, 9100 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9101 /* bits */ 20, 9102 /* flags */ 0, 9103 }, 9104 #endif /* chips */ 9105 9106 #if defined(BCM_53314_A0) 9107 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM53314_A0fmt */ 9108 /* format MMU_XQHEADERfmt */ 9109 /* nFields */ 7, 9110 /* *fields */ soc_MMU_XQHEADER_BCM53314_A0fmt_fields, 9111 /* bits */ 18, 9112 /* flags */ 0, 9113 }, 9114 #endif /* chips */ 9115 9116 #if defined(BCM_53324_A0) 9117 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM53324_A0fmt */ 9118 /* format MMU_XQHEADERfmt */ 9119 /* nFields */ 7, 9120 /* *fields */ soc_MMU_XQHEADER_BCM53314_A0fmt_fields, 9121 /* bits */ 18, 9122 /* flags */ 0, 9123 }, 9124 #endif /* chips */ 9125 9126 #if defined(BCM_53400_A0) 9127 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM53400_A0fmt */ 9128 /* format MMU_XQHEADERfmt */ 9129 /* nFields */ 7, 9130 /* *fields */ soc_MMU_XQHEADER_BCM53400_A0fmt_fields, 9131 /* bits */ 27, 9132 /* flags */ 0, 9133 }, 9134 #endif /* chips */ 9135 9136 #if defined(BCM_53540_A0) 9137 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM53540_A0fmt */ 9138 /* format MMU_XQHEADERfmt */ 9139 /* nFields */ 7, 9140 /* *fields */ soc_MMU_XQHEADER_BCM53540_A0fmt_fields, 9141 /* bits */ 23, 9142 /* flags */ 0, 9143 }, 9144 #endif /* chips */ 9145 9146 #if defined(BCM_53570_A0) 9147 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM53570_A0fmt */ 9148 /* format MMU_XQHEADERfmt */ 9149 /* nFields */ 7, 9150 /* *fields */ soc_MMU_XQHEADER_BCM53570_A0fmt_fields, 9151 /* bits */ 30, 9152 /* flags */ 0, 9153 }, 9154 #endif /* chips */ 9155 9156 #if defined(BCM_53570_B0) 9157 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM53570_B0fmt */ 9158 /* format MMU_XQHEADERfmt */ 9159 /* nFields */ 7, 9160 /* *fields */ soc_MMU_XQHEADER_BCM53570_B0fmt_fields, 9161 /* bits */ 32, 9162 /* flags */ 0, 9163 }, 9164 #endif /* chips */ 9165 9166 #if defined(BCM_56142_A0) 9167 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56142_A0fmt */ 9168 /* format MMU_XQHEADERfmt */ 9169 /* nFields */ 7, 9170 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9171 /* bits */ 20, 9172 /* flags */ 0, 9173 }, 9174 #endif /* chips */ 9175 9176 #if defined(BCM_56150_A0) 9177 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56150_A0fmt */ 9178 /* format MMU_XQHEADERfmt */ 9179 /* nFields */ 7, 9180 /* *fields */ soc_MMU_XQHEADER_BCM56150_A0fmt_fields, 9181 /* bits */ 20, 9182 /* flags */ 0, 9183 }, 9184 #endif /* chips */ 9185 9186 #if defined(BCM_56160_A0) 9187 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56160_A0fmt */ 9188 /* format MMU_XQHEADERfmt */ 9189 /* nFields */ 7, 9190 /* *fields */ soc_MMU_XQHEADER_BCM56160_A0fmt_fields, 9191 /* bits */ 29, 9192 /* flags */ 0, 9193 }, 9194 #endif /* chips */ 9195 9196 #if defined(BCM_56224_A0) 9197 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56224_A0fmt */ 9198 /* format MMU_XQHEADERfmt */ 9199 /* nFields */ 7, 9200 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9201 /* bits */ 20, 9202 /* flags */ 0, 9203 }, 9204 #endif /* chips */ 9205 9206 #if defined(BCM_56224_B0) 9207 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56224_B0fmt */ 9208 /* format MMU_XQHEADERfmt */ 9209 /* nFields */ 7, 9210 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9211 /* bits */ 20, 9212 /* flags */ 0, 9213 }, 9214 #endif /* chips */ 9215 9216 #if defined(BCM_56314_A0) 9217 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56314_A0fmt */ 9218 /* format MMU_XQHEADERfmt */ 9219 /* nFields */ 7, 9220 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9221 /* bits */ 20, 9222 /* flags */ 0, 9223 }, 9224 #endif /* chips */ 9225 9226 #if defined(BCM_56504_B0) 9227 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56504_B0fmt */ 9228 /* format MMU_XQHEADERfmt */ 9229 /* nFields */ 7, 9230 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9231 /* bits */ 20, 9232 /* flags */ 0, 9233 }, 9234 #endif /* chips */ 9235 9236 #if defined(BCM_56514_A0) 9237 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56514_A0fmt */ 9238 /* format MMU_XQHEADERfmt */ 9239 /* nFields */ 7, 9240 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9241 /* bits */ 20, 9242 /* flags */ 0, 9243 }, 9244 #endif /* chips */ 9245 9246 #if defined(BCM_56800_A0) 9247 { /* SOC_FORMAT_INT_MMU_XQHEADER_BCM56800_A0fmt */ 9248 /* format MMU_XQHEADERfmt */ 9249 /* nFields */ 7, 9250 /* *fields */ soc_MMU_XQHEADERfmt_fields, 9251 /* bits */ 20, 9252 /* flags */ 0, 9253 }, 9254 #endif /* chips */ 9255 9256 #if defined(BCM_56142_A0) 9257 { /* SOC_FORMAT_INT_MMU_XQ_HDR_ONLY_CPUfmt */ 9258 /* format MMU_XQ_HDR_ONLY_CPUfmt */ 9259 /* nFields */ 11, 9260 /* *fields */ soc_MMU_XQ_HDR_ONLY_CPUfmt_fields, 9261 /* bits */ 106, 9262 /* flags */ 0, 9263 }, 9264 #endif /* chips */ 9265 9266 #if defined(BCM_56150_A0) 9267 { /* SOC_FORMAT_INT_MMU_XQ_HDR_ONLY_CPU_BCM56150_A0fmt */ 9268 /* format MMU_XQ_HDR_ONLY_CPUfmt */ 9269 /* nFields */ 11, 9270 /* *fields */ soc_MMU_XQ_HDR_ONLY_CPU_BCM56150_A0fmt_fields, 9271 /* bits */ 106, 9272 /* flags */ 0, 9273 }, 9274 #endif /* chips */ 9275 9276 #if defined(BCM_56142_A0) 9277 { /* SOC_FORMAT_INT_MMU_XQ_HDR_ONLY_GPORTfmt */ 9278 /* format MMU_XQ_HDR_ONLY_GPORTfmt */ 9279 /* nFields */ 6, 9280 /* *fields */ soc_MMU_XQ_HDR_ONLY_GPORTfmt_fields, 9281 /* bits */ 20, 9282 /* flags */ 0, 9283 }, 9284 #endif /* chips */ 9285 9286 #if defined(BCM_56150_A0) 9287 { /* SOC_FORMAT_INT_MMU_XQ_HDR_ONLY_GPORT_BCM56150_A0fmt */ 9288 /* format MMU_XQ_HDR_ONLY_GPORTfmt */ 9289 /* nFields */ 6, 9290 /* *fields */ soc_MMU_XQ_HDR_ONLY_GPORT_BCM56150_A0fmt_fields, 9291 /* bits */ 20, 9292 /* flags */ 0, 9293 }, 9294 #endif /* chips */ 9295 9296 #if defined(BCM_56142_A0) 9297 { /* SOC_FORMAT_INT_MMU_XQ_HDR_ONLY_XPORTfmt */ 9298 /* format MMU_XQ_HDR_ONLY_XPORTfmt */ 9299 /* nFields */ 9, 9300 /* *fields */ soc_MMU_XQ_HDR_ONLY_XPORTfmt_fields, 9301 /* bits */ 54, 9302 /* flags */ 0, 9303 }, 9304 #endif /* chips */ 9305 9306 #if defined(BCM_56150_A0) 9307 { /* SOC_FORMAT_INT_MMU_XQ_HDR_ONLY_XPORT_BCM56150_A0fmt */ 9308 /* format MMU_XQ_HDR_ONLY_XPORTfmt */ 9309 /* nFields */ 9, 9310 /* *fields */ soc_MMU_XQ_HDR_ONLY_XPORT_BCM56150_A0fmt_fields, 9311 /* bits */ 54, 9312 /* flags */ 0, 9313 }, 9314 #endif /* chips */ 9315 9316 #if defined(BCM_56504_A0) 9317 { /* SOC_FORMAT_INT_MODULE_HEADERfmt */ 9318 /* format MODULE_HEADERfmt */ 9319 /* nFields */ 24, 9320 /* *fields */ soc_MODULE_HEADERfmt_fields, 9321 /* bits */ 96, 9322 /* flags */ 0, 9323 }, 9324 #endif /* chips */ 9325 9326 #if defined(BCM_53314_A0) 9327 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM53314_A0fmt */ 9328 /* format MODULE_HEADERfmt */ 9329 /* nFields */ 33, 9330 /* *fields */ soc_MODULE_HEADER_BCM56224_A0fmt_fields, 9331 /* bits */ 128, 9332 /* flags */ 0, 9333 }, 9334 #endif /* chips */ 9335 9336 #if defined(BCM_53324_A0) 9337 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM53324_A0fmt */ 9338 /* format MODULE_HEADERfmt */ 9339 /* nFields */ 33, 9340 /* *fields */ soc_MODULE_HEADER_BCM56224_A0fmt_fields, 9341 /* bits */ 128, 9342 /* flags */ 0, 9343 }, 9344 #endif /* chips */ 9345 9346 #if defined(BCM_53400_A0) 9347 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM53400_A0fmt */ 9348 /* format MODULE_HEADERfmt */ 9349 /* nFields */ 30, 9350 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9351 /* bits */ 96, 9352 /* flags */ 0, 9353 }, 9354 #endif /* chips */ 9355 9356 #if defined(BCM_53540_A0) 9357 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM53540_A0fmt */ 9358 /* format MODULE_HEADERfmt */ 9359 /* nFields */ 30, 9360 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9361 /* bits */ 96, 9362 /* flags */ 0, 9363 }, 9364 #endif /* chips */ 9365 9366 #if defined(BCM_53570_A0) 9367 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM53570_A0fmt */ 9368 /* format MODULE_HEADERfmt */ 9369 /* nFields */ 30, 9370 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9371 /* bits */ 96, 9372 /* flags */ 0, 9373 }, 9374 #endif /* chips */ 9375 9376 #if defined(BCM_53570_B0) 9377 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM53570_B0fmt */ 9378 /* format MODULE_HEADERfmt */ 9379 /* nFields */ 30, 9380 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9381 /* bits */ 96, 9382 /* flags */ 0, 9383 }, 9384 #endif /* chips */ 9385 9386 #if defined(BCM_56142_A0) 9387 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56142_A0fmt */ 9388 /* format MODULE_HEADERfmt */ 9389 /* nFields */ 30, 9390 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9391 /* bits */ 96, 9392 /* flags */ 0, 9393 }, 9394 #endif /* chips */ 9395 9396 #if defined(BCM_56150_A0) 9397 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56150_A0fmt */ 9398 /* format MODULE_HEADERfmt */ 9399 /* nFields */ 30, 9400 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9401 /* bits */ 96, 9402 /* flags */ 0, 9403 }, 9404 #endif /* chips */ 9405 9406 #if defined(BCM_56160_A0) 9407 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56160_A0fmt */ 9408 /* format MODULE_HEADERfmt */ 9409 /* nFields */ 30, 9410 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9411 /* bits */ 96, 9412 /* flags */ 0, 9413 }, 9414 #endif /* chips */ 9415 9416 #if defined(BCM_56224_A0) 9417 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56224_A0fmt */ 9418 /* format MODULE_HEADERfmt */ 9419 /* nFields */ 33, 9420 /* *fields */ soc_MODULE_HEADER_BCM56224_A0fmt_fields, 9421 /* bits */ 128, 9422 /* flags */ 0, 9423 }, 9424 #endif /* chips */ 9425 9426 #if defined(BCM_56224_B0) 9427 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56224_B0fmt */ 9428 /* format MODULE_HEADERfmt */ 9429 /* nFields */ 33, 9430 /* *fields */ soc_MODULE_HEADER_BCM56224_A0fmt_fields, 9431 /* bits */ 128, 9432 /* flags */ 0, 9433 }, 9434 #endif /* chips */ 9435 9436 #if defined(BCM_56260_A0) 9437 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56260_A0fmt */ 9438 /* format MODULE_HEADERfmt */ 9439 /* nFields */ 30, 9440 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9441 /* bits */ 96, 9442 /* flags */ 0, 9443 }, 9444 #endif /* chips */ 9445 9446 #if defined(BCM_56260_B0) 9447 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56260_B0fmt */ 9448 /* format MODULE_HEADERfmt */ 9449 /* nFields */ 30, 9450 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9451 /* bits */ 96, 9452 /* flags */ 0, 9453 }, 9454 #endif /* chips */ 9455 9456 #if defined(BCM_56270_A0) 9457 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56270_A0fmt */ 9458 /* format MODULE_HEADERfmt */ 9459 /* nFields */ 30, 9460 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9461 /* bits */ 96, 9462 /* flags */ 0, 9463 }, 9464 #endif /* chips */ 9465 9466 #if defined(BCM_56314_A0) 9467 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56314_A0fmt */ 9468 /* format MODULE_HEADERfmt */ 9469 /* nFields */ 26, 9470 /* *fields */ soc_MODULE_HEADER_BCM56504_B0fmt_fields, 9471 /* bits */ 96, 9472 /* flags */ 0, 9473 }, 9474 #endif /* chips */ 9475 9476 #if defined(BCM_56334_A0) 9477 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56334_A0fmt */ 9478 /* format MODULE_HEADERfmt */ 9479 /* nFields */ 30, 9480 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9481 /* bits */ 96, 9482 /* flags */ 0, 9483 }, 9484 #endif /* chips */ 9485 9486 #if defined(BCM_56334_B0) 9487 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56334_B0fmt */ 9488 /* format MODULE_HEADERfmt */ 9489 /* nFields */ 30, 9490 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9491 /* bits */ 96, 9492 /* flags */ 0, 9493 }, 9494 #endif /* chips */ 9495 9496 #if defined(BCM_56340_A0) 9497 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56340_A0fmt */ 9498 /* format MODULE_HEADERfmt */ 9499 /* nFields */ 30, 9500 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9501 /* bits */ 96, 9502 /* flags */ 0, 9503 }, 9504 #endif /* chips */ 9505 9506 #if defined(BCM_56370_A0) 9507 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56370_A0fmt */ 9508 /* format MODULE_HEADERfmt */ 9509 /* nFields */ 30, 9510 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9511 /* bits */ 96, 9512 /* flags */ 0, 9513 }, 9514 #endif /* chips */ 9515 9516 #if defined(BCM_56440_A0) 9517 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56440_A0fmt */ 9518 /* format MODULE_HEADERfmt */ 9519 /* nFields */ 30, 9520 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9521 /* bits */ 96, 9522 /* flags */ 0, 9523 }, 9524 #endif /* chips */ 9525 9526 #if defined(BCM_56440_B0) 9527 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56440_B0fmt */ 9528 /* format MODULE_HEADERfmt */ 9529 /* nFields */ 30, 9530 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9531 /* bits */ 96, 9532 /* flags */ 0, 9533 }, 9534 #endif /* chips */ 9535 9536 #if defined(BCM_56450_A0) 9537 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56450_A0fmt */ 9538 /* format MODULE_HEADERfmt */ 9539 /* nFields */ 30, 9540 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9541 /* bits */ 96, 9542 /* flags */ 0, 9543 }, 9544 #endif /* chips */ 9545 9546 #if defined(BCM_56450_B0) 9547 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56450_B0fmt */ 9548 /* format MODULE_HEADERfmt */ 9549 /* nFields */ 30, 9550 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9551 /* bits */ 96, 9552 /* flags */ 0, 9553 }, 9554 #endif /* chips */ 9555 9556 #if defined(BCM_56450_B1) 9557 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56450_B1fmt */ 9558 /* format MODULE_HEADERfmt */ 9559 /* nFields */ 30, 9560 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9561 /* bits */ 96, 9562 /* flags */ 0, 9563 }, 9564 #endif /* chips */ 9565 9566 #if defined(BCM_56504_B0) 9567 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56504_B0fmt */ 9568 /* format MODULE_HEADERfmt */ 9569 /* nFields */ 26, 9570 /* *fields */ soc_MODULE_HEADER_BCM56504_B0fmt_fields, 9571 /* bits */ 96, 9572 /* flags */ 0, 9573 }, 9574 #endif /* chips */ 9575 9576 #if defined(BCM_56514_A0) 9577 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56514_A0fmt */ 9578 /* format MODULE_HEADERfmt */ 9579 /* nFields */ 26, 9580 /* *fields */ soc_MODULE_HEADER_BCM56504_B0fmt_fields, 9581 /* bits */ 96, 9582 /* flags */ 0, 9583 }, 9584 #endif /* chips */ 9585 9586 #if defined(BCM_56524_A0) 9587 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56524_A0fmt */ 9588 /* format MODULE_HEADERfmt */ 9589 /* nFields */ 30, 9590 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9591 /* bits */ 96, 9592 /* flags */ 0, 9593 }, 9594 #endif /* chips */ 9595 9596 #if defined(BCM_56524_B0) 9597 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56524_B0fmt */ 9598 /* format MODULE_HEADERfmt */ 9599 /* nFields */ 30, 9600 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9601 /* bits */ 96, 9602 /* flags */ 0, 9603 }, 9604 #endif /* chips */ 9605 9606 #if defined(BCM_56560_A0) 9607 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56560_A0fmt */ 9608 /* format MODULE_HEADERfmt */ 9609 /* nFields */ 30, 9610 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9611 /* bits */ 96, 9612 /* flags */ 0, 9613 }, 9614 #endif /* chips */ 9615 9616 #if defined(BCM_56560_B0) 9617 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56560_B0fmt */ 9618 /* format MODULE_HEADERfmt */ 9619 /* nFields */ 30, 9620 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9621 /* bits */ 96, 9622 /* flags */ 0, 9623 }, 9624 #endif /* chips */ 9625 9626 #if defined(BCM_56624_A0) 9627 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56624_A0fmt */ 9628 /* format MODULE_HEADERfmt */ 9629 /* nFields */ 30, 9630 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9631 /* bits */ 96, 9632 /* flags */ 0, 9633 }, 9634 #endif /* chips */ 9635 9636 #if defined(BCM_56624_B0) 9637 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56624_B0fmt */ 9638 /* format MODULE_HEADERfmt */ 9639 /* nFields */ 30, 9640 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9641 /* bits */ 96, 9642 /* flags */ 0, 9643 }, 9644 #endif /* chips */ 9645 9646 #if defined(BCM_56634_A0) 9647 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56634_A0fmt */ 9648 /* format MODULE_HEADERfmt */ 9649 /* nFields */ 30, 9650 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9651 /* bits */ 96, 9652 /* flags */ 0, 9653 }, 9654 #endif /* chips */ 9655 9656 #if defined(BCM_56634_B0) 9657 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56634_B0fmt */ 9658 /* format MODULE_HEADERfmt */ 9659 /* nFields */ 30, 9660 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9661 /* bits */ 96, 9662 /* flags */ 0, 9663 }, 9664 #endif /* chips */ 9665 9666 #if defined(BCM_56640_A0) 9667 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56640_A0fmt */ 9668 /* format MODULE_HEADERfmt */ 9669 /* nFields */ 30, 9670 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9671 /* bits */ 96, 9672 /* flags */ 0, 9673 }, 9674 #endif /* chips */ 9675 9676 #if defined(BCM_56670_A0) 9677 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56670_A0fmt */ 9678 /* format MODULE_HEADERfmt */ 9679 /* nFields */ 30, 9680 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9681 /* bits */ 96, 9682 /* flags */ 0, 9683 }, 9684 #endif /* chips */ 9685 9686 #if defined(BCM_56670_B0) 9687 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56670_B0fmt */ 9688 /* format MODULE_HEADERfmt */ 9689 /* nFields */ 30, 9690 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9691 /* bits */ 96, 9692 /* flags */ 0, 9693 }, 9694 #endif /* chips */ 9695 9696 #if defined(BCM_56680_A0) 9697 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56680_A0fmt */ 9698 /* format MODULE_HEADERfmt */ 9699 /* nFields */ 30, 9700 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9701 /* bits */ 96, 9702 /* flags */ 0, 9703 }, 9704 #endif /* chips */ 9705 9706 #if defined(BCM_56680_B0) 9707 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56680_B0fmt */ 9708 /* format MODULE_HEADERfmt */ 9709 /* nFields */ 30, 9710 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9711 /* bits */ 96, 9712 /* flags */ 0, 9713 }, 9714 #endif /* chips */ 9715 9716 #if defined(BCM_56685_A0) 9717 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56685_A0fmt */ 9718 /* format MODULE_HEADERfmt */ 9719 /* nFields */ 30, 9720 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9721 /* bits */ 96, 9722 /* flags */ 0, 9723 }, 9724 #endif /* chips */ 9725 9726 #if defined(BCM_56685_B0) 9727 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56685_B0fmt */ 9728 /* format MODULE_HEADERfmt */ 9729 /* nFields */ 30, 9730 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9731 /* bits */ 96, 9732 /* flags */ 0, 9733 }, 9734 #endif /* chips */ 9735 9736 #if defined(BCM_56725_A0) 9737 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56725_A0fmt */ 9738 /* format MODULE_HEADERfmt */ 9739 /* nFields */ 30, 9740 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9741 /* bits */ 96, 9742 /* flags */ 0, 9743 }, 9744 #endif /* chips */ 9745 9746 #if defined(BCM_56770_A0) 9747 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56770_A0fmt */ 9748 /* format MODULE_HEADERfmt */ 9749 /* nFields */ 30, 9750 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9751 /* bits */ 96, 9752 /* flags */ 0, 9753 }, 9754 #endif /* chips */ 9755 9756 #if defined(BCM_56800_A0) 9757 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56800_A0fmt */ 9758 /* format MODULE_HEADERfmt */ 9759 /* nFields */ 30, 9760 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9761 /* bits */ 96, 9762 /* flags */ 0, 9763 }, 9764 #endif /* chips */ 9765 9766 #if defined(BCM_56820_A0) 9767 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56820_A0fmt */ 9768 /* format MODULE_HEADERfmt */ 9769 /* nFields */ 30, 9770 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9771 /* bits */ 96, 9772 /* flags */ 0, 9773 }, 9774 #endif /* chips */ 9775 9776 #if defined(BCM_56840_A0) 9777 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56840_A0fmt */ 9778 /* format MODULE_HEADERfmt */ 9779 /* nFields */ 30, 9780 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9781 /* bits */ 96, 9782 /* flags */ 0, 9783 }, 9784 #endif /* chips */ 9785 9786 #if defined(BCM_56840_B0) 9787 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56840_B0fmt */ 9788 /* format MODULE_HEADERfmt */ 9789 /* nFields */ 30, 9790 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9791 /* bits */ 96, 9792 /* flags */ 0, 9793 }, 9794 #endif /* chips */ 9795 9796 #if defined(BCM_56850_A0) 9797 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56850_A0fmt */ 9798 /* format MODULE_HEADERfmt */ 9799 /* nFields */ 30, 9800 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9801 /* bits */ 96, 9802 /* flags */ 0, 9803 }, 9804 #endif /* chips */ 9805 9806 #if defined(BCM_56860_A0) 9807 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56860_A0fmt */ 9808 /* format MODULE_HEADERfmt */ 9809 /* nFields */ 30, 9810 /* *fields */ soc_MODULE_HEADER_BCM56640_A0fmt_fields, 9811 /* bits */ 96, 9812 /* flags */ 0, 9813 }, 9814 #endif /* chips */ 9815 9816 #if defined(BCM_56870_A0) 9817 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56870_A0fmt */ 9818 /* format MODULE_HEADERfmt */ 9819 /* nFields */ 30, 9820 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9821 /* bits */ 96, 9822 /* flags */ 0, 9823 }, 9824 #endif /* chips */ 9825 9826 #if defined(BCM_56960_A0) 9827 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56960_A0fmt */ 9828 /* format MODULE_HEADERfmt */ 9829 /* nFields */ 30, 9830 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9831 /* bits */ 96, 9832 /* flags */ 0, 9833 }, 9834 #endif /* chips */ 9835 9836 #if defined(BCM_56965_A0) 9837 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56965_A0fmt */ 9838 /* format MODULE_HEADERfmt */ 9839 /* nFields */ 30, 9840 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9841 /* bits */ 96, 9842 /* flags */ 0, 9843 }, 9844 #endif /* chips */ 9845 9846 #if defined(BCM_56970_A0) 9847 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56970_A0fmt */ 9848 /* format MODULE_HEADERfmt */ 9849 /* nFields */ 30, 9850 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9851 /* bits */ 96, 9852 /* flags */ 0, 9853 }, 9854 #endif /* chips */ 9855 9856 #if defined(BCM_56980_A0) 9857 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56980_A0fmt */ 9858 /* format MODULE_HEADERfmt */ 9859 /* nFields */ 30, 9860 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9861 /* bits */ 96, 9862 /* flags */ 0, 9863 }, 9864 #endif /* chips */ 9865 9866 #if defined(BCM_56980_B0) 9867 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM56980_B0fmt */ 9868 /* format MODULE_HEADERfmt */ 9869 /* nFields */ 30, 9870 /* *fields */ soc_MODULE_HEADER_BCM53400_A0fmt_fields, 9871 /* bits */ 96, 9872 /* flags */ 0, 9873 }, 9874 #endif /* chips */ 9875 9876 #if defined(BCM_88732_A0) 9877 { /* SOC_FORMAT_INT_MODULE_HEADER_BCM88732_A0fmt */ 9878 /* format MODULE_HEADERfmt */ 9879 /* nFields */ 30, 9880 /* *fields */ soc_MODULE_HEADER_BCM56800_A0fmt_fields, 9881 /* bits */ 96, 9882 /* flags */ 0, 9883 }, 9884 #endif /* chips */ 9885 9886 #if defined(BCM_56440_A0) || defined(BCM_56624_A0) || \ 9887 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 9888 defined(BCM_56680_A0) || defined(BCM_56685_B0) || \ 9889 defined(BCM_56725_A0) || defined(BCM_56800_A0) || \ 9890 defined(BCM_56820_A0) || defined(BCM_56840_B0) || \ 9891 defined(BCM_88732_A0) 9892 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFTfmt */ 9893 /* format MODULE_HEADER_SHIFTfmt */ 9894 /* nFields */ 30, 9895 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 9896 /* bits */ 128, 9897 /* flags */ 0, 9898 }, 9899 #endif /* chips */ 9900 9901 #if defined(BCM_53400_A0) 9902 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM53400_A0fmt */ 9903 /* format MODULE_HEADER_SHIFTfmt */ 9904 /* nFields */ 30, 9905 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9906 /* bits */ 128, 9907 /* flags */ 0, 9908 }, 9909 #endif /* chips */ 9910 9911 #if defined(BCM_53540_A0) 9912 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM53540_A0fmt */ 9913 /* format MODULE_HEADER_SHIFTfmt */ 9914 /* nFields */ 30, 9915 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9916 /* bits */ 128, 9917 /* flags */ 0, 9918 }, 9919 #endif /* chips */ 9920 9921 #if defined(BCM_53570_A0) 9922 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM53570_A0fmt */ 9923 /* format MODULE_HEADER_SHIFTfmt */ 9924 /* nFields */ 30, 9925 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9926 /* bits */ 128, 9927 /* flags */ 0, 9928 }, 9929 #endif /* chips */ 9930 9931 #if defined(BCM_53570_B0) 9932 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM53570_B0fmt */ 9933 /* format MODULE_HEADER_SHIFTfmt */ 9934 /* nFields */ 30, 9935 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9936 /* bits */ 128, 9937 /* flags */ 0, 9938 }, 9939 #endif /* chips */ 9940 9941 #if defined(BCM_56142_A0) 9942 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56142_A0fmt */ 9943 /* format MODULE_HEADER_SHIFTfmt */ 9944 /* nFields */ 30, 9945 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 9946 /* bits */ 128, 9947 /* flags */ 0, 9948 }, 9949 #endif /* chips */ 9950 9951 #if defined(BCM_56150_A0) 9952 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56150_A0fmt */ 9953 /* format MODULE_HEADER_SHIFTfmt */ 9954 /* nFields */ 30, 9955 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 9956 /* bits */ 128, 9957 /* flags */ 0, 9958 }, 9959 #endif /* chips */ 9960 9961 #if defined(BCM_56160_A0) 9962 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56160_A0fmt */ 9963 /* format MODULE_HEADER_SHIFTfmt */ 9964 /* nFields */ 30, 9965 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9966 /* bits */ 128, 9967 /* flags */ 0, 9968 }, 9969 #endif /* chips */ 9970 9971 #if defined(BCM_56260_A0) 9972 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56260_A0fmt */ 9973 /* format MODULE_HEADER_SHIFTfmt */ 9974 /* nFields */ 30, 9975 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9976 /* bits */ 128, 9977 /* flags */ 0, 9978 }, 9979 #endif /* chips */ 9980 9981 #if defined(BCM_56260_B0) 9982 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56260_B0fmt */ 9983 /* format MODULE_HEADER_SHIFTfmt */ 9984 /* nFields */ 30, 9985 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9986 /* bits */ 128, 9987 /* flags */ 0, 9988 }, 9989 #endif /* chips */ 9990 9991 #if defined(BCM_56270_A0) 9992 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56270_A0fmt */ 9993 /* format MODULE_HEADER_SHIFTfmt */ 9994 /* nFields */ 30, 9995 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 9996 /* bits */ 128, 9997 /* flags */ 0, 9998 }, 9999 #endif /* chips */ 10000 10001 #if defined(BCM_56334_A0) 10002 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56334_A0fmt */ 10003 /* format MODULE_HEADER_SHIFTfmt */ 10004 /* nFields */ 30, 10005 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10006 /* bits */ 128, 10007 /* flags */ 0, 10008 }, 10009 #endif /* chips */ 10010 10011 #if defined(BCM_56334_B0) 10012 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56334_B0fmt */ 10013 /* format MODULE_HEADER_SHIFTfmt */ 10014 /* nFields */ 30, 10015 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10016 /* bits */ 128, 10017 /* flags */ 0, 10018 }, 10019 #endif /* chips */ 10020 10021 #if defined(BCM_56340_A0) 10022 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56340_A0fmt */ 10023 /* format MODULE_HEADER_SHIFTfmt */ 10024 /* nFields */ 30, 10025 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 10026 /* bits */ 128, 10027 /* flags */ 0, 10028 }, 10029 #endif /* chips */ 10030 10031 #if defined(BCM_56370_A0) 10032 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56370_A0fmt */ 10033 /* format MODULE_HEADER_SHIFTfmt */ 10034 /* nFields */ 30, 10035 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10036 /* bits */ 128, 10037 /* flags */ 0, 10038 }, 10039 #endif /* chips */ 10040 10041 #if defined(BCM_56440_B0) 10042 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56440_B0fmt */ 10043 /* format MODULE_HEADER_SHIFTfmt */ 10044 /* nFields */ 30, 10045 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10046 /* bits */ 128, 10047 /* flags */ 0, 10048 }, 10049 #endif /* chips */ 10050 10051 #if defined(BCM_56450_A0) 10052 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56450_A0fmt */ 10053 /* format MODULE_HEADER_SHIFTfmt */ 10054 /* nFields */ 30, 10055 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 10056 /* bits */ 128, 10057 /* flags */ 0, 10058 }, 10059 #endif /* chips */ 10060 10061 #if defined(BCM_56450_B0) 10062 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56450_B0fmt */ 10063 /* format MODULE_HEADER_SHIFTfmt */ 10064 /* nFields */ 30, 10065 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 10066 /* bits */ 128, 10067 /* flags */ 0, 10068 }, 10069 #endif /* chips */ 10070 10071 #if defined(BCM_56450_B1) 10072 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56450_B1fmt */ 10073 /* format MODULE_HEADER_SHIFTfmt */ 10074 /* nFields */ 30, 10075 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 10076 /* bits */ 128, 10077 /* flags */ 0, 10078 }, 10079 #endif /* chips */ 10080 10081 #if defined(BCM_56524_A0) 10082 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56524_A0fmt */ 10083 /* format MODULE_HEADER_SHIFTfmt */ 10084 /* nFields */ 30, 10085 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10086 /* bits */ 128, 10087 /* flags */ 0, 10088 }, 10089 #endif /* chips */ 10090 10091 #if defined(BCM_56524_B0) 10092 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56524_B0fmt */ 10093 /* format MODULE_HEADER_SHIFTfmt */ 10094 /* nFields */ 30, 10095 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10096 /* bits */ 128, 10097 /* flags */ 0, 10098 }, 10099 #endif /* chips */ 10100 10101 #if defined(BCM_56560_A0) 10102 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56560_A0fmt */ 10103 /* format MODULE_HEADER_SHIFTfmt */ 10104 /* nFields */ 30, 10105 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10106 /* bits */ 128, 10107 /* flags */ 0, 10108 }, 10109 #endif /* chips */ 10110 10111 #if defined(BCM_56560_B0) 10112 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56560_B0fmt */ 10113 /* format MODULE_HEADER_SHIFTfmt */ 10114 /* nFields */ 30, 10115 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10116 /* bits */ 128, 10117 /* flags */ 0, 10118 }, 10119 #endif /* chips */ 10120 10121 #if defined(BCM_56634_B0) 10122 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56634_B0fmt */ 10123 /* format MODULE_HEADER_SHIFTfmt */ 10124 /* nFields */ 30, 10125 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10126 /* bits */ 128, 10127 /* flags */ 0, 10128 }, 10129 #endif /* chips */ 10130 10131 #if defined(BCM_56640_A0) 10132 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56640_A0fmt */ 10133 /* format MODULE_HEADER_SHIFTfmt */ 10134 /* nFields */ 30, 10135 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 10136 /* bits */ 128, 10137 /* flags */ 0, 10138 }, 10139 #endif /* chips */ 10140 10141 #if defined(BCM_56670_A0) 10142 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56670_A0fmt */ 10143 /* format MODULE_HEADER_SHIFTfmt */ 10144 /* nFields */ 30, 10145 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10146 /* bits */ 128, 10147 /* flags */ 0, 10148 }, 10149 #endif /* chips */ 10150 10151 #if defined(BCM_56670_B0) 10152 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56670_B0fmt */ 10153 /* format MODULE_HEADER_SHIFTfmt */ 10154 /* nFields */ 30, 10155 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10156 /* bits */ 128, 10157 /* flags */ 0, 10158 }, 10159 #endif /* chips */ 10160 10161 #if defined(BCM_56680_B0) 10162 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56680_B0fmt */ 10163 /* format MODULE_HEADER_SHIFTfmt */ 10164 /* nFields */ 30, 10165 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10166 /* bits */ 128, 10167 /* flags */ 0, 10168 }, 10169 #endif /* chips */ 10170 10171 #if defined(BCM_56685_A0) 10172 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56685_A0fmt */ 10173 /* format MODULE_HEADER_SHIFTfmt */ 10174 /* nFields */ 30, 10175 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10176 /* bits */ 128, 10177 /* flags */ 0, 10178 }, 10179 #endif /* chips */ 10180 10181 #if defined(BCM_56770_A0) 10182 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56770_A0fmt */ 10183 /* format MODULE_HEADER_SHIFTfmt */ 10184 /* nFields */ 30, 10185 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10186 /* bits */ 128, 10187 /* flags */ 0, 10188 }, 10189 #endif /* chips */ 10190 10191 #if defined(BCM_56840_A0) 10192 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56840_A0fmt */ 10193 /* format MODULE_HEADER_SHIFTfmt */ 10194 /* nFields */ 30, 10195 /* *fields */ soc_MODULE_HEADER_SHIFTfmt_fields, 10196 /* bits */ 128, 10197 /* flags */ 0, 10198 }, 10199 #endif /* chips */ 10200 10201 #if defined(BCM_56850_A0) 10202 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56850_A0fmt */ 10203 /* format MODULE_HEADER_SHIFTfmt */ 10204 /* nFields */ 30, 10205 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 10206 /* bits */ 128, 10207 /* flags */ 0, 10208 }, 10209 #endif /* chips */ 10210 10211 #if defined(BCM_56860_A0) 10212 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56860_A0fmt */ 10213 /* format MODULE_HEADER_SHIFTfmt */ 10214 /* nFields */ 30, 10215 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM56640_A0fmt_fields, 10216 /* bits */ 128, 10217 /* flags */ 0, 10218 }, 10219 #endif /* chips */ 10220 10221 #if defined(BCM_56870_A0) 10222 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56870_A0fmt */ 10223 /* format MODULE_HEADER_SHIFTfmt */ 10224 /* nFields */ 30, 10225 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10226 /* bits */ 128, 10227 /* flags */ 0, 10228 }, 10229 #endif /* chips */ 10230 10231 #if defined(BCM_56960_A0) 10232 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56960_A0fmt */ 10233 /* format MODULE_HEADER_SHIFTfmt */ 10234 /* nFields */ 30, 10235 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10236 /* bits */ 128, 10237 /* flags */ 0, 10238 }, 10239 #endif /* chips */ 10240 10241 #if defined(BCM_56965_A0) 10242 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56965_A0fmt */ 10243 /* format MODULE_HEADER_SHIFTfmt */ 10244 /* nFields */ 30, 10245 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10246 /* bits */ 128, 10247 /* flags */ 0, 10248 }, 10249 #endif /* chips */ 10250 10251 #if defined(BCM_56970_A0) 10252 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56970_A0fmt */ 10253 /* format MODULE_HEADER_SHIFTfmt */ 10254 /* nFields */ 30, 10255 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10256 /* bits */ 128, 10257 /* flags */ 0, 10258 }, 10259 #endif /* chips */ 10260 10261 #if defined(BCM_56980_A0) 10262 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56980_A0fmt */ 10263 /* format MODULE_HEADER_SHIFTfmt */ 10264 /* nFields */ 30, 10265 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10266 /* bits */ 128, 10267 /* flags */ 0, 10268 }, 10269 #endif /* chips */ 10270 10271 #if defined(BCM_56980_B0) 10272 { /* SOC_FORMAT_INT_MODULE_HEADER_SHIFT_BCM56980_B0fmt */ 10273 /* format MODULE_HEADER_SHIFTfmt */ 10274 /* nFields */ 30, 10275 /* *fields */ soc_MODULE_HEADER_SHIFT_BCM53400_A0fmt_fields, 10276 /* bits */ 128, 10277 /* flags */ 0, 10278 }, 10279 #endif /* chips */ 10280 10281 #if defined(BCM_56840_A0) 10282 { /* SOC_FORMAT_INT_MPBfmt */ 10283 /* format MPBfmt */ 10284 /* nFields */ 78, 10285 /* *fields */ soc_MPBfmt_fields, 10286 /* bits */ 455, 10287 /* flags */ 0, 10288 }, 10289 #endif /* chips */ 10290 10291 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 10292 { /* SOC_FORMAT_INT_MPB_BASE_FORWARD_FORMATfmt */ 10293 /* format MPB_BASE_FORWARD_FORMATfmt */ 10294 /* nFields */ 9, 10295 /* *fields */ soc_MPB_BASE_FORWARD_FORMATfmt_fields, 10296 /* bits */ 34, 10297 /* flags */ 0, 10298 }, 10299 #endif /* chips */ 10300 10301 #if defined(BCM_56370_A0) 10302 { /* SOC_FORMAT_INT_MPB_BASE_FORWARD_FORMAT_BCM56370_A0fmt */ 10303 /* format MPB_BASE_FORWARD_FORMATfmt */ 10304 /* nFields */ 9, 10305 /* *fields */ soc_MPB_BASE_FORWARD_FORMAT_BCM56370_A0fmt_fields, 10306 /* bits */ 34, 10307 /* flags */ 0, 10308 }, 10309 #endif /* chips */ 10310 10311 #if defined(BCM_56260_A0) 10312 { /* SOC_FORMAT_INT_MPB_BCM56260_A0fmt */ 10313 /* format MPBfmt */ 10314 /* nFields */ 139, 10315 /* *fields */ soc_MPB_BCM56260_A0fmt_fields, 10316 /* bits */ 496, 10317 /* flags */ 0, 10318 }, 10319 #endif /* chips */ 10320 10321 #if defined(BCM_56260_B0) 10322 { /* SOC_FORMAT_INT_MPB_BCM56260_B0fmt */ 10323 /* format MPBfmt */ 10324 /* nFields */ 139, 10325 /* *fields */ soc_MPB_BCM56260_A0fmt_fields, 10326 /* bits */ 496, 10327 /* flags */ 0, 10328 }, 10329 #endif /* chips */ 10330 10331 #if defined(BCM_56270_A0) 10332 { /* SOC_FORMAT_INT_MPB_BCM56270_A0fmt */ 10333 /* format MPBfmt */ 10334 /* nFields */ 142, 10335 /* *fields */ soc_MPB_BCM56270_A0fmt_fields, 10336 /* bits */ 496, 10337 /* flags */ 0, 10338 }, 10339 #endif /* chips */ 10340 10341 #if defined(BCM_56340_A0) 10342 { /* SOC_FORMAT_INT_MPB_BCM56340_A0fmt */ 10343 /* format MPBfmt */ 10344 /* nFields */ 132, 10345 /* *fields */ soc_MPB_BCM56340_A0fmt_fields, 10346 /* bits */ 512, 10347 /* flags */ 0, 10348 }, 10349 #endif /* chips */ 10350 10351 #if defined(BCM_56370_A0) 10352 { /* SOC_FORMAT_INT_MPB_BCM56370_A0fmt */ 10353 /* format MPBfmt */ 10354 /* nFields */ 89, 10355 /* *fields */ soc_MPB_BCM56370_A0fmt_fields, 10356 /* bits */ 512, 10357 /* flags */ 0, 10358 }, 10359 #endif /* chips */ 10360 10361 #if defined(BCM_56440_A0) 10362 { /* SOC_FORMAT_INT_MPB_BCM56440_A0fmt */ 10363 /* format MPBfmt */ 10364 /* nFields */ 86, 10365 /* *fields */ soc_MPB_BCM56440_A0fmt_fields, 10366 /* bits */ 400, 10367 /* flags */ 0, 10368 }, 10369 #endif /* chips */ 10370 10371 #if defined(BCM_56440_B0) 10372 { /* SOC_FORMAT_INT_MPB_BCM56440_B0fmt */ 10373 /* format MPBfmt */ 10374 /* nFields */ 86, 10375 /* *fields */ soc_MPB_BCM56440_A0fmt_fields, 10376 /* bits */ 400, 10377 /* flags */ 0, 10378 }, 10379 #endif /* chips */ 10380 10381 #if defined(BCM_56450_A0) 10382 { /* SOC_FORMAT_INT_MPB_BCM56450_A0fmt */ 10383 /* format MPBfmt */ 10384 /* nFields */ 117, 10385 /* *fields */ soc_MPB_BCM56450_A0fmt_fields, 10386 /* bits */ 496, 10387 /* flags */ 0, 10388 }, 10389 #endif /* chips */ 10390 10391 #if defined(BCM_56450_B0) 10392 { /* SOC_FORMAT_INT_MPB_BCM56450_B0fmt */ 10393 /* format MPBfmt */ 10394 /* nFields */ 117, 10395 /* *fields */ soc_MPB_BCM56450_A0fmt_fields, 10396 /* bits */ 496, 10397 /* flags */ 0, 10398 }, 10399 #endif /* chips */ 10400 10401 #if defined(BCM_56450_B1) 10402 { /* SOC_FORMAT_INT_MPB_BCM56450_B1fmt */ 10403 /* format MPBfmt */ 10404 /* nFields */ 117, 10405 /* *fields */ soc_MPB_BCM56450_A0fmt_fields, 10406 /* bits */ 496, 10407 /* flags */ 0, 10408 }, 10409 #endif /* chips */ 10410 10411 #if defined(BCM_56560_A0) 10412 { /* SOC_FORMAT_INT_MPB_BCM56560_A0fmt */ 10413 /* format MPBfmt */ 10414 /* nFields */ 161, 10415 /* *fields */ soc_MPB_BCM56560_A0fmt_fields, 10416 /* bits */ 512, 10417 /* flags */ 0, 10418 }, 10419 #endif /* chips */ 10420 10421 #if defined(BCM_56560_B0) 10422 { /* SOC_FORMAT_INT_MPB_BCM56560_B0fmt */ 10423 /* format MPBfmt */ 10424 /* nFields */ 161, 10425 /* *fields */ soc_MPB_BCM56560_A0fmt_fields, 10426 /* bits */ 512, 10427 /* flags */ 0, 10428 }, 10429 #endif /* chips */ 10430 10431 #if defined(BCM_56640_A0) 10432 { /* SOC_FORMAT_INT_MPB_BCM56640_A0fmt */ 10433 /* format MPBfmt */ 10434 /* nFields */ 131, 10435 /* *fields */ soc_MPB_BCM56640_A0fmt_fields, 10436 /* bits */ 512, 10437 /* flags */ 0, 10438 }, 10439 #endif /* chips */ 10440 10441 #if defined(BCM_56670_A0) 10442 { /* SOC_FORMAT_INT_MPB_BCM56670_A0fmt */ 10443 /* format MPBfmt */ 10444 /* nFields */ 171, 10445 /* *fields */ soc_MPB_BCM56670_A0fmt_fields, 10446 /* bits */ 512, 10447 /* flags */ 0, 10448 }, 10449 #endif /* chips */ 10450 10451 #if defined(BCM_56670_B0) 10452 { /* SOC_FORMAT_INT_MPB_BCM56670_B0fmt */ 10453 /* format MPBfmt */ 10454 /* nFields */ 171, 10455 /* *fields */ soc_MPB_BCM56670_A0fmt_fields, 10456 /* bits */ 512, 10457 /* flags */ 0, 10458 }, 10459 #endif /* chips */ 10460 10461 #if defined(BCM_56770_A0) 10462 { /* SOC_FORMAT_INT_MPB_BCM56770_A0fmt */ 10463 /* format MPBfmt */ 10464 /* nFields */ 89, 10465 /* *fields */ soc_MPB_BCM56870_A0fmt_fields, 10466 /* bits */ 512, 10467 /* flags */ 0, 10468 }, 10469 #endif /* chips */ 10470 10471 #if defined(BCM_56840_B0) 10472 { /* SOC_FORMAT_INT_MPB_BCM56840_B0fmt */ 10473 /* format MPBfmt */ 10474 /* nFields */ 79, 10475 /* *fields */ soc_MPB_BCM56840_B0fmt_fields, 10476 /* bits */ 455, 10477 /* flags */ 0, 10478 }, 10479 #endif /* chips */ 10480 10481 #if defined(BCM_56850_A0) 10482 { /* SOC_FORMAT_INT_MPB_BCM56850_A0fmt */ 10483 /* format MPBfmt */ 10484 /* nFields */ 131, 10485 /* *fields */ soc_MPB_BCM56850_A0fmt_fields, 10486 /* bits */ 512, 10487 /* flags */ 0, 10488 }, 10489 #endif /* chips */ 10490 10491 #if defined(BCM_56860_A0) 10492 { /* SOC_FORMAT_INT_MPB_BCM56860_A0fmt */ 10493 /* format MPBfmt */ 10494 /* nFields */ 156, 10495 /* *fields */ soc_MPB_BCM56860_A0fmt_fields, 10496 /* bits */ 512, 10497 /* flags */ 0, 10498 }, 10499 #endif /* chips */ 10500 10501 #if defined(BCM_56870_A0) 10502 { /* SOC_FORMAT_INT_MPB_BCM56870_A0fmt */ 10503 /* format MPBfmt */ 10504 /* nFields */ 89, 10505 /* *fields */ soc_MPB_BCM56870_A0fmt_fields, 10506 /* bits */ 512, 10507 /* flags */ 0, 10508 }, 10509 #endif /* chips */ 10510 10511 #if defined(BCM_56960_A0) 10512 { /* SOC_FORMAT_INT_MPB_BCM56960_A0fmt */ 10513 /* format MPBfmt */ 10514 /* nFields */ 123, 10515 /* *fields */ soc_MPB_BCM56960_A0fmt_fields, 10516 /* bits */ 512, 10517 /* flags */ 0, 10518 }, 10519 #endif /* chips */ 10520 10521 #if defined(BCM_56965_A0) 10522 { /* SOC_FORMAT_INT_MPB_BCM56965_A0fmt */ 10523 /* format MPBfmt */ 10524 /* nFields */ 123, 10525 /* *fields */ soc_MPB_BCM56960_A0fmt_fields, 10526 /* bits */ 512, 10527 /* flags */ 0, 10528 }, 10529 #endif /* chips */ 10530 10531 #if defined(BCM_56970_A0) 10532 { /* SOC_FORMAT_INT_MPB_BCM56970_A0fmt */ 10533 /* format MPBfmt */ 10534 /* nFields */ 126, 10535 /* *fields */ soc_MPB_BCM56970_A0fmt_fields, 10536 /* bits */ 512, 10537 /* flags */ 0, 10538 }, 10539 #endif /* chips */ 10540 10541 #if defined(BCM_56980_A0) 10542 { /* SOC_FORMAT_INT_MPB_BCM56980_A0fmt */ 10543 /* format MPBfmt */ 10544 /* nFields */ 72, 10545 /* *fields */ soc_MPB_BCM56980_A0fmt_fields, 10546 /* bits */ 320, 10547 /* flags */ 0, 10548 }, 10549 #endif /* chips */ 10550 10551 #if defined(BCM_56980_B0) 10552 { /* SOC_FORMAT_INT_MPB_BCM56980_B0fmt */ 10553 /* format MPBfmt */ 10554 /* nFields */ 72, 10555 /* *fields */ soc_MPB_BCM56980_A0fmt_fields, 10556 /* bits */ 320, 10557 /* flags */ 0, 10558 }, 10559 #endif /* chips */ 10560 10561 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10562 defined(BCM_56870_A0) 10563 { /* SOC_FORMAT_INT_MPB_CLASSID_FORMATfmt */ 10564 /* format MPB_CLASSID_FORMATfmt */ 10565 /* nFields */ 3, 10566 /* *fields */ soc_MPB_CLASSID_FORMATfmt_fields, 10567 /* bits */ 16, 10568 /* flags */ 0, 10569 }, 10570 #endif /* chips */ 10571 10572 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10573 defined(BCM_56870_A0) 10574 { /* SOC_FORMAT_INT_MPB_COPY_TO_CPU_FORMATfmt */ 10575 /* format MPB_COPY_TO_CPU_FORMATfmt */ 10576 /* nFields */ 6, 10577 /* *fields */ soc_MPB_COPY_TO_CPU_FORMATfmt_fields, 10578 /* bits */ 23, 10579 /* flags */ 0, 10580 }, 10581 #endif /* chips */ 10582 10583 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10584 defined(BCM_56870_A0) 10585 { /* SOC_FORMAT_INT_MPB_ENTROPY_FORMATfmt */ 10586 /* format MPB_ENTROPY_FORMATfmt */ 10587 /* nFields */ 1, 10588 /* *fields */ soc_MPB_ENTROPY_FORMATfmt_fields, 10589 /* bits */ 20, 10590 /* flags */ 0, 10591 }, 10592 #endif /* chips */ 10593 10594 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 10595 { /* SOC_FORMAT_INT_MPB_FORWARD_EXT_FORMATfmt */ 10596 /* format MPB_FORWARD_EXT_FORMATfmt */ 10597 /* nFields */ 2, 10598 /* *fields */ soc_MPB_FORWARD_EXT_FORMATfmt_fields, 10599 /* bits */ 17, 10600 /* flags */ 0, 10601 }, 10602 #endif /* chips */ 10603 10604 #if defined(BCM_56370_A0) 10605 { /* SOC_FORMAT_INT_MPB_FORWARD_EXT_FORMAT_BCM56370_A0fmt */ 10606 /* format MPB_FORWARD_EXT_FORMATfmt */ 10607 /* nFields */ 3, 10608 /* *fields */ soc_MPB_FORWARD_EXT_FORMAT_BCM56370_A0fmt_fields, 10609 /* bits */ 17, 10610 /* flags */ 0, 10611 }, 10612 #endif /* chips */ 10613 10614 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10615 defined(BCM_56870_A0) 10616 { /* SOC_FORMAT_INT_MPB_FP_HGPRXY_DATA_DECODER_OUT_BUSfmt */ 10617 /* format MPB_FP_HGPRXY_DATA_DECODER_OUT_BUSfmt */ 10618 /* nFields */ 106, 10619 /* *fields */ soc_MPB_FP_HGPRXY_DATA_DECODER_OUT_BUSfmt_fields, 10620 /* bits */ 399, 10621 /* flags */ 0, 10622 }, 10623 #endif /* chips */ 10624 10625 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10626 defined(BCM_56870_A0) 10627 { /* SOC_FORMAT_INT_MPB_HG2_EXT_FORMATfmt */ 10628 /* format MPB_HG2_EXT_FORMATfmt */ 10629 /* nFields */ 1, 10630 /* *fields */ soc_MPB_HG2_EXT_FORMATfmt_fields, 10631 /* bits */ 32, 10632 /* flags */ 0, 10633 }, 10634 #endif /* chips */ 10635 10636 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10637 defined(BCM_56870_A0) 10638 { /* SOC_FORMAT_INT_MPB_HIGIG_DATA_DECODER_OUT_BUSfmt */ 10639 /* format MPB_HIGIG_DATA_DECODER_OUT_BUSfmt */ 10640 /* nFields */ 96, 10641 /* *fields */ soc_MPB_HIGIG_DATA_DECODER_OUT_BUSfmt_fields, 10642 /* bits */ 209, 10643 /* flags */ 0, 10644 }, 10645 #endif /* chips */ 10646 10647 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10648 defined(BCM_56870_A0) 10649 { /* SOC_FORMAT_INT_MPB_ING_EDIT_EXTRACT_CTRL_ID_FORMATfmt */ 10650 /* format MPB_ING_EDIT_EXTRACT_CTRL_ID_FORMATfmt */ 10651 /* nFields */ 2, 10652 /* *fields */ soc_MPB_ING_EDIT_EXTRACT_CTRL_ID_FORMATfmt_fields, 10653 /* bits */ 16, 10654 /* flags */ 0, 10655 }, 10656 #endif /* chips */ 10657 10658 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10659 defined(BCM_56870_A0) 10660 { /* SOC_FORMAT_INT_MPB_L2_ETAG_FORMATfmt */ 10661 /* format MPB_L2_ETAG_FORMATfmt */ 10662 /* nFields */ 3, 10663 /* *fields */ soc_MPB_L2_ETAG_FORMATfmt_fields, 10664 /* bits */ 6, 10665 /* flags */ 0, 10666 }, 10667 #endif /* chips */ 10668 10669 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10670 defined(BCM_56870_A0) 10671 { /* SOC_FORMAT_INT_MPB_L2_EXT_FORMATfmt */ 10672 /* format MPB_L2_EXT_FORMATfmt */ 10673 /* nFields */ 5, 10674 /* *fields */ soc_MPB_L2_EXT_FORMATfmt_fields, 10675 /* bits */ 21, 10676 /* flags */ 0, 10677 }, 10678 #endif /* chips */ 10679 10680 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10681 defined(BCM_56870_A0) 10682 { /* SOC_FORMAT_INT_MPB_L2_ITAG_FORMATfmt */ 10683 /* format MPB_L2_ITAG_FORMATfmt */ 10684 /* nFields */ 2, 10685 /* *fields */ soc_MPB_L2_ITAG_FORMATfmt_fields, 10686 /* bits */ 18, 10687 /* flags */ 0, 10688 }, 10689 #endif /* chips */ 10690 10691 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 10692 { /* SOC_FORMAT_INT_MPB_L2_SVP_FORMATfmt */ 10693 /* format MPB_L2_SVP_FORMATfmt */ 10694 /* nFields */ 2, 10695 /* *fields */ soc_MPB_L2_SVP_FORMATfmt_fields, 10696 /* bits */ 17, 10697 /* flags */ 0, 10698 }, 10699 #endif /* chips */ 10700 10701 #if defined(BCM_56370_A0) 10702 { /* SOC_FORMAT_INT_MPB_L2_SVP_FORMAT_BCM56370_A0fmt */ 10703 /* format MPB_L2_SVP_FORMATfmt */ 10704 /* nFields */ 3, 10705 /* *fields */ soc_MPB_L2_SVP_FORMAT_BCM56370_A0fmt_fields, 10706 /* bits */ 17, 10707 /* flags */ 0, 10708 }, 10709 #endif /* chips */ 10710 10711 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 10712 { /* SOC_FORMAT_INT_MPB_L2_VFI_FORMATfmt */ 10713 /* format MPB_L2_VFI_FORMATfmt */ 10714 /* nFields */ 1, 10715 /* *fields */ soc_MPB_L2_VFI_FORMATfmt_fields, 10716 /* bits */ 14, 10717 /* flags */ 0, 10718 }, 10719 #endif /* chips */ 10720 10721 #if defined(BCM_56370_A0) 10722 { /* SOC_FORMAT_INT_MPB_L2_VFI_FORMAT_BCM56370_A0fmt */ 10723 /* format MPB_L2_VFI_FORMATfmt */ 10724 /* nFields */ 2, 10725 /* *fields */ soc_MPB_L2_VFI_FORMAT_BCM56370_A0fmt_fields, 10726 /* bits */ 14, 10727 /* flags */ 0, 10728 }, 10729 #endif /* chips */ 10730 10731 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 10732 { /* SOC_FORMAT_INT_MPB_L3_IIF_FORMATfmt */ 10733 /* format MPB_L3_IIF_FORMATfmt */ 10734 /* nFields */ 2, 10735 /* *fields */ soc_MPB_L3_IIF_FORMATfmt_fields, 10736 /* bits */ 15, 10737 /* flags */ 0, 10738 }, 10739 #endif /* chips */ 10740 10741 #if defined(BCM_56370_A0) 10742 { /* SOC_FORMAT_INT_MPB_L3_IIF_FORMAT_BCM56370_A0fmt */ 10743 /* format MPB_L3_IIF_FORMATfmt */ 10744 /* nFields */ 3, 10745 /* *fields */ soc_MPB_L3_IIF_FORMAT_BCM56370_A0fmt_fields, 10746 /* bits */ 15, 10747 /* flags */ 0, 10748 }, 10749 #endif /* chips */ 10750 10751 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10752 defined(BCM_56870_A0) 10753 { /* SOC_FORMAT_INT_MPB_L3_VRF_FORMATfmt */ 10754 /* format MPB_L3_VRF_FORMATfmt */ 10755 /* nFields */ 1, 10756 /* *fields */ soc_MPB_L3_VRF_FORMATfmt_fields, 10757 /* bits */ 12, 10758 /* flags */ 0, 10759 }, 10760 #endif /* chips */ 10761 10762 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10763 defined(BCM_56870_A0) 10764 { /* SOC_FORMAT_INT_MPB_MIRROR_FORMATfmt */ 10765 /* format MPB_MIRROR_FORMATfmt */ 10766 /* nFields */ 2, 10767 /* *fields */ soc_MPB_MIRROR_FORMATfmt_fields, 10768 /* bits */ 10, 10769 /* flags */ 0, 10770 }, 10771 #endif /* chips */ 10772 10773 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10774 defined(BCM_56870_A0) 10775 { /* SOC_FORMAT_INT_MPB_NAT_FORMATfmt */ 10776 /* format MPB_NAT_FORMATfmt */ 10777 /* nFields */ 2, 10778 /* *fields */ soc_MPB_NAT_FORMATfmt_fields, 10779 /* bits */ 11, 10780 /* flags */ 0, 10781 }, 10782 #endif /* chips */ 10783 10784 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 10785 { /* SOC_FORMAT_INT_MPB_NEXT_HOP_DATA_FORMATfmt */ 10786 /* format MPB_NEXT_HOP_DATA_FORMATfmt */ 10787 /* nFields */ 8, 10788 /* *fields */ soc_MPB_NEXT_HOP_DATA_FORMATfmt_fields, 10789 /* bits */ 64, 10790 /* flags */ 0, 10791 }, 10792 #endif /* chips */ 10793 10794 #if defined(BCM_56370_A0) 10795 { /* SOC_FORMAT_INT_MPB_NEXT_HOP_DATA_FORMAT_BCM56370_A0fmt */ 10796 /* format MPB_NEXT_HOP_DATA_FORMATfmt */ 10797 /* nFields */ 9, 10798 /* *fields */ soc_MPB_NEXT_HOP_DATA_FORMAT_BCM56370_A0fmt_fields, 10799 /* bits */ 64, 10800 /* flags */ 0, 10801 }, 10802 #endif /* chips */ 10803 10804 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10805 defined(BCM_56870_A0) 10806 { /* SOC_FORMAT_INT_MPB_OPAQUE_OBJECT_FORMATfmt */ 10807 /* format MPB_OPAQUE_OBJECT_FORMATfmt */ 10808 /* nFields */ 1, 10809 /* *fields */ soc_MPB_OPAQUE_OBJECT_FORMATfmt_fields, 10810 /* bits */ 16, 10811 /* flags */ 0, 10812 }, 10813 #endif /* chips */ 10814 10815 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10816 defined(BCM_56870_A0) 10817 { /* SOC_FORMAT_INT_MPB_QOS_FORMATfmt */ 10818 /* format MPB_QOS_FORMATfmt */ 10819 /* nFields */ 4, 10820 /* *fields */ soc_MPB_QOS_FORMATfmt_fields, 10821 /* bits */ 10, 10822 /* flags */ 0, 10823 }, 10824 #endif /* chips */ 10825 10826 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10827 defined(BCM_56870_A0) 10828 { /* SOC_FORMAT_INT_MPB_QUEUE_TAG_FORMATfmt */ 10829 /* format MPB_QUEUE_TAG_FORMATfmt */ 10830 /* nFields */ 2, 10831 /* *fields */ soc_MPB_QUEUE_TAG_FORMATfmt_fields, 10832 /* bits */ 18, 10833 /* flags */ 0, 10834 }, 10835 #endif /* chips */ 10836 10837 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10838 defined(BCM_56870_A0) 10839 { /* SOC_FORMAT_INT_MPB_TIMESTAMP_FORMATfmt */ 10840 /* format MPB_TIMESTAMP_FORMATfmt */ 10841 /* nFields */ 1, 10842 /* *fields */ soc_MPB_TIMESTAMP_FORMATfmt_fields, 10843 /* bits */ 32, 10844 /* flags */ 0, 10845 }, 10846 #endif /* chips */ 10847 10848 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10849 defined(BCM_56870_A0) 10850 { /* SOC_FORMAT_INT_MPLS_ACTIONfmt */ 10851 /* format MPLS_ACTIONfmt */ 10852 /* nFields */ 1, 10853 /* *fields */ soc_MPLS_ACTIONfmt_fields, 10854 /* bits */ 4, 10855 /* flags */ 0, 10856 }, 10857 #endif /* chips */ 10858 10859 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10860 defined(BCM_56870_A0) 10861 { /* SOC_FORMAT_INT_MPLS_ACTION_SETfmt */ 10862 /* format MPLS_ACTION_SETfmt */ 10863 /* nFields */ 18, 10864 /* *fields */ soc_MPLS_ACTION_SETfmt_fields, 10865 /* bits */ 36, 10866 /* flags */ 0, 10867 }, 10868 #endif /* chips */ 10869 10870 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 10871 { /* SOC_FORMAT_INT_MPLS_CONTROL_SIGNALS_DOPfmt */ 10872 /* format MPLS_CONTROL_SIGNALS_DOPfmt */ 10873 /* nFields */ 8, 10874 /* *fields */ soc_MPLS_CONTROL_SIGNALS_DOPfmt_fields, 10875 /* bits */ 64, 10876 /* flags */ 0, 10877 }, 10878 #endif /* chips */ 10879 10880 #if defined(BCM_56370_A0) 10881 { /* SOC_FORMAT_INT_MPLS_CONTROL_SIGNALS_DOP_BCM56370_A0fmt */ 10882 /* format MPLS_CONTROL_SIGNALS_DOPfmt */ 10883 /* nFields */ 8, 10884 /* *fields */ soc_MPLS_CONTROL_SIGNALS_DOP_BCM56370_A0fmt_fields, 10885 /* bits */ 64, 10886 /* flags */ 0, 10887 }, 10888 #endif /* chips */ 10889 10890 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 10891 defined(BCM_56870_A0) 10892 { /* SOC_FORMAT_INT_MPLS_CW_ACTION_SETfmt */ 10893 /* format MPLS_CW_ACTION_SETfmt */ 10894 /* nFields */ 1, 10895 /* *fields */ soc_MPLS_CW_ACTION_SETfmt_fields, 10896 /* bits */ 2, 10897 /* flags */ 0, 10898 }, 10899 #endif /* chips */ 10900 10901 #if defined(BCM_56624_A0) 10902 { /* SOC_FORMAT_INT_MPLS_DROPfmt */ 10903 /* format MPLS_DROPfmt */ 10904 /* nFields */ 4, 10905 /* *fields */ soc_MPLS_DROPfmt_fields, 10906 /* bits */ 4, 10907 /* flags */ 0, 10908 }, 10909 #endif /* chips */ 10910 10911 #if defined(BCM_53400_A0) 10912 { /* SOC_FORMAT_INT_MPLS_DROP_BCM53400_A0fmt */ 10913 /* format MPLS_DROPfmt */ 10914 /* nFields */ 5, 10915 /* *fields */ soc_MPLS_DROP_BCM53400_A0fmt_fields, 10916 /* bits */ 8, 10917 /* flags */ 0, 10918 }, 10919 #endif /* chips */ 10920 10921 #if defined(BCM_53540_A0) 10922 { /* SOC_FORMAT_INT_MPLS_DROP_BCM53540_A0fmt */ 10923 /* format MPLS_DROPfmt */ 10924 /* nFields */ 5, 10925 /* *fields */ soc_MPLS_DROP_BCM53400_A0fmt_fields, 10926 /* bits */ 8, 10927 /* flags */ 0, 10928 }, 10929 #endif /* chips */ 10930 10931 #if defined(BCM_53570_A0) 10932 { /* SOC_FORMAT_INT_MPLS_DROP_BCM53570_A0fmt */ 10933 /* format MPLS_DROPfmt */ 10934 /* nFields */ 5, 10935 /* *fields */ soc_MPLS_DROP_BCM53400_A0fmt_fields, 10936 /* bits */ 8, 10937 /* flags */ 0, 10938 }, 10939 #endif /* chips */ 10940 10941 #if defined(BCM_53570_B0) 10942 { /* SOC_FORMAT_INT_MPLS_DROP_BCM53570_B0fmt */ 10943 /* format MPLS_DROPfmt */ 10944 /* nFields */ 5, 10945 /* *fields */ soc_MPLS_DROP_BCM53400_A0fmt_fields, 10946 /* bits */ 8, 10947 /* flags */ 0, 10948 }, 10949 #endif /* chips */ 10950 10951 #if defined(BCM_56142_A0) 10952 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56142_A0fmt */ 10953 /* format MPLS_DROPfmt */ 10954 /* nFields */ 5, 10955 /* *fields */ soc_MPLS_DROP_BCM56334_A0fmt_fields, 10956 /* bits */ 8, 10957 /* flags */ 0, 10958 }, 10959 #endif /* chips */ 10960 10961 #if defined(BCM_56150_A0) 10962 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56150_A0fmt */ 10963 /* format MPLS_DROPfmt */ 10964 /* nFields */ 5, 10965 /* *fields */ soc_MPLS_DROP_BCM56150_A0fmt_fields, 10966 /* bits */ 8, 10967 /* flags */ 0, 10968 }, 10969 #endif /* chips */ 10970 10971 #if defined(BCM_56160_A0) 10972 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56160_A0fmt */ 10973 /* format MPLS_DROPfmt */ 10974 /* nFields */ 5, 10975 /* *fields */ soc_MPLS_DROP_BCM53400_A0fmt_fields, 10976 /* bits */ 8, 10977 /* flags */ 0, 10978 }, 10979 #endif /* chips */ 10980 10981 #if defined(BCM_56260_A0) 10982 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56260_A0fmt */ 10983 /* format MPLS_DROPfmt */ 10984 /* nFields */ 8, 10985 /* *fields */ soc_MPLS_DROP_BCM56260_A0fmt_fields, 10986 /* bits */ 8, 10987 /* flags */ 0, 10988 }, 10989 #endif /* chips */ 10990 10991 #if defined(BCM_56260_B0) 10992 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56260_B0fmt */ 10993 /* format MPLS_DROPfmt */ 10994 /* nFields */ 8, 10995 /* *fields */ soc_MPLS_DROP_BCM56260_A0fmt_fields, 10996 /* bits */ 8, 10997 /* flags */ 0, 10998 }, 10999 #endif /* chips */ 11000 11001 #if defined(BCM_56270_A0) 11002 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56270_A0fmt */ 11003 /* format MPLS_DROPfmt */ 11004 /* nFields */ 8, 11005 /* *fields */ soc_MPLS_DROP_BCM56260_A0fmt_fields, 11006 /* bits */ 8, 11007 /* flags */ 0, 11008 }, 11009 #endif /* chips */ 11010 11011 #if defined(BCM_56334_A0) 11012 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56334_A0fmt */ 11013 /* format MPLS_DROPfmt */ 11014 /* nFields */ 5, 11015 /* *fields */ soc_MPLS_DROP_BCM56334_A0fmt_fields, 11016 /* bits */ 8, 11017 /* flags */ 0, 11018 }, 11019 #endif /* chips */ 11020 11021 #if defined(BCM_56334_B0) 11022 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56334_B0fmt */ 11023 /* format MPLS_DROPfmt */ 11024 /* nFields */ 5, 11025 /* *fields */ soc_MPLS_DROP_BCM56334_A0fmt_fields, 11026 /* bits */ 8, 11027 /* flags */ 0, 11028 }, 11029 #endif /* chips */ 11030 11031 #if defined(BCM_56340_A0) 11032 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56340_A0fmt */ 11033 /* format MPLS_DROPfmt */ 11034 /* nFields */ 12, 11035 /* *fields */ soc_MPLS_DROP_BCM56640_A0fmt_fields, 11036 /* bits */ 11, 11037 /* flags */ 0, 11038 }, 11039 #endif /* chips */ 11040 11041 #if defined(BCM_56440_A0) 11042 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56440_A0fmt */ 11043 /* format MPLS_DROPfmt */ 11044 /* nFields */ 8, 11045 /* *fields */ soc_MPLS_DROP_BCM56440_A0fmt_fields, 11046 /* bits */ 8, 11047 /* flags */ 0, 11048 }, 11049 #endif /* chips */ 11050 11051 #if defined(BCM_56440_B0) 11052 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56440_B0fmt */ 11053 /* format MPLS_DROPfmt */ 11054 /* nFields */ 8, 11055 /* *fields */ soc_MPLS_DROP_BCM56440_A0fmt_fields, 11056 /* bits */ 8, 11057 /* flags */ 0, 11058 }, 11059 #endif /* chips */ 11060 11061 #if defined(BCM_56450_A0) 11062 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56450_A0fmt */ 11063 /* format MPLS_DROPfmt */ 11064 /* nFields */ 8, 11065 /* *fields */ soc_MPLS_DROP_BCM56450_A0fmt_fields, 11066 /* bits */ 8, 11067 /* flags */ 0, 11068 }, 11069 #endif /* chips */ 11070 11071 #if defined(BCM_56450_B0) 11072 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56450_B0fmt */ 11073 /* format MPLS_DROPfmt */ 11074 /* nFields */ 8, 11075 /* *fields */ soc_MPLS_DROP_BCM56450_A0fmt_fields, 11076 /* bits */ 8, 11077 /* flags */ 0, 11078 }, 11079 #endif /* chips */ 11080 11081 #if defined(BCM_56450_B1) 11082 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56450_B1fmt */ 11083 /* format MPLS_DROPfmt */ 11084 /* nFields */ 8, 11085 /* *fields */ soc_MPLS_DROP_BCM56450_A0fmt_fields, 11086 /* bits */ 8, 11087 /* flags */ 0, 11088 }, 11089 #endif /* chips */ 11090 11091 #if defined(BCM_56524_A0) 11092 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56524_A0fmt */ 11093 /* format MPLS_DROPfmt */ 11094 /* nFields */ 8, 11095 /* *fields */ soc_MPLS_DROP_BCM56634_A0fmt_fields, 11096 /* bits */ 8, 11097 /* flags */ 0, 11098 }, 11099 #endif /* chips */ 11100 11101 #if defined(BCM_56524_B0) 11102 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56524_B0fmt */ 11103 /* format MPLS_DROPfmt */ 11104 /* nFields */ 8, 11105 /* *fields */ soc_MPLS_DROP_BCM56634_A0fmt_fields, 11106 /* bits */ 8, 11107 /* flags */ 0, 11108 }, 11109 #endif /* chips */ 11110 11111 #if defined(BCM_56560_A0) 11112 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56560_A0fmt */ 11113 /* format MPLS_DROPfmt */ 11114 /* nFields */ 18, 11115 /* *fields */ soc_MPLS_DROP_BCM56560_A0fmt_fields, 11116 /* bits */ 18, 11117 /* flags */ 0, 11118 }, 11119 #endif /* chips */ 11120 11121 #if defined(BCM_56560_B0) 11122 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56560_B0fmt */ 11123 /* format MPLS_DROPfmt */ 11124 /* nFields */ 18, 11125 /* *fields */ soc_MPLS_DROP_BCM56560_A0fmt_fields, 11126 /* bits */ 18, 11127 /* flags */ 0, 11128 }, 11129 #endif /* chips */ 11130 11131 #if defined(BCM_56624_B0) 11132 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56624_B0fmt */ 11133 /* format MPLS_DROPfmt */ 11134 /* nFields */ 4, 11135 /* *fields */ soc_MPLS_DROPfmt_fields, 11136 /* bits */ 4, 11137 /* flags */ 0, 11138 }, 11139 #endif /* chips */ 11140 11141 #if defined(BCM_56634_A0) 11142 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56634_A0fmt */ 11143 /* format MPLS_DROPfmt */ 11144 /* nFields */ 8, 11145 /* *fields */ soc_MPLS_DROP_BCM56634_A0fmt_fields, 11146 /* bits */ 8, 11147 /* flags */ 0, 11148 }, 11149 #endif /* chips */ 11150 11151 #if defined(BCM_56634_B0) 11152 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56634_B0fmt */ 11153 /* format MPLS_DROPfmt */ 11154 /* nFields */ 8, 11155 /* *fields */ soc_MPLS_DROP_BCM56634_A0fmt_fields, 11156 /* bits */ 8, 11157 /* flags */ 0, 11158 }, 11159 #endif /* chips */ 11160 11161 #if defined(BCM_56640_A0) 11162 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56640_A0fmt */ 11163 /* format MPLS_DROPfmt */ 11164 /* nFields */ 12, 11165 /* *fields */ soc_MPLS_DROP_BCM56640_A0fmt_fields, 11166 /* bits */ 11, 11167 /* flags */ 0, 11168 }, 11169 #endif /* chips */ 11170 11171 #if defined(BCM_56670_A0) 11172 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56670_A0fmt */ 11173 /* format MPLS_DROPfmt */ 11174 /* nFields */ 18, 11175 /* *fields */ soc_MPLS_DROP_BCM56560_A0fmt_fields, 11176 /* bits */ 18, 11177 /* flags */ 0, 11178 }, 11179 #endif /* chips */ 11180 11181 #if defined(BCM_56670_B0) 11182 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56670_B0fmt */ 11183 /* format MPLS_DROPfmt */ 11184 /* nFields */ 18, 11185 /* *fields */ soc_MPLS_DROP_BCM56560_A0fmt_fields, 11186 /* bits */ 18, 11187 /* flags */ 0, 11188 }, 11189 #endif /* chips */ 11190 11191 #if defined(BCM_56680_A0) 11192 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56680_A0fmt */ 11193 /* format MPLS_DROPfmt */ 11194 /* nFields */ 4, 11195 /* *fields */ soc_MPLS_DROPfmt_fields, 11196 /* bits */ 4, 11197 /* flags */ 0, 11198 }, 11199 #endif /* chips */ 11200 11201 #if defined(BCM_56680_B0) 11202 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56680_B0fmt */ 11203 /* format MPLS_DROPfmt */ 11204 /* nFields */ 4, 11205 /* *fields */ soc_MPLS_DROPfmt_fields, 11206 /* bits */ 4, 11207 /* flags */ 0, 11208 }, 11209 #endif /* chips */ 11210 11211 #if defined(BCM_56685_A0) 11212 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56685_A0fmt */ 11213 /* format MPLS_DROPfmt */ 11214 /* nFields */ 8, 11215 /* *fields */ soc_MPLS_DROP_BCM56634_A0fmt_fields, 11216 /* bits */ 8, 11217 /* flags */ 0, 11218 }, 11219 #endif /* chips */ 11220 11221 #if defined(BCM_56685_B0) 11222 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56685_B0fmt */ 11223 /* format MPLS_DROPfmt */ 11224 /* nFields */ 8, 11225 /* *fields */ soc_MPLS_DROP_BCM56634_A0fmt_fields, 11226 /* bits */ 8, 11227 /* flags */ 0, 11228 }, 11229 #endif /* chips */ 11230 11231 #if defined(BCM_56840_A0) 11232 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56840_A0fmt */ 11233 /* format MPLS_DROPfmt */ 11234 /* nFields */ 8, 11235 /* *fields */ soc_MPLS_DROP_BCM56840_A0fmt_fields, 11236 /* bits */ 8, 11237 /* flags */ 0, 11238 }, 11239 #endif /* chips */ 11240 11241 #if defined(BCM_56840_B0) 11242 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56840_B0fmt */ 11243 /* format MPLS_DROPfmt */ 11244 /* nFields */ 8, 11245 /* *fields */ soc_MPLS_DROP_BCM56840_A0fmt_fields, 11246 /* bits */ 8, 11247 /* flags */ 0, 11248 }, 11249 #endif /* chips */ 11250 11251 #if defined(BCM_56850_A0) 11252 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56850_A0fmt */ 11253 /* format MPLS_DROPfmt */ 11254 /* nFields */ 16, 11255 /* *fields */ soc_MPLS_DROP_BCM56850_A0fmt_fields, 11256 /* bits */ 16, 11257 /* flags */ 0, 11258 }, 11259 #endif /* chips */ 11260 11261 #if defined(BCM_56860_A0) 11262 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56860_A0fmt */ 11263 /* format MPLS_DROPfmt */ 11264 /* nFields */ 16, 11265 /* *fields */ soc_MPLS_DROP_BCM56850_A0fmt_fields, 11266 /* bits */ 16, 11267 /* flags */ 0, 11268 }, 11269 #endif /* chips */ 11270 11271 #if defined(BCM_56960_A0) 11272 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56960_A0fmt */ 11273 /* format MPLS_DROPfmt */ 11274 /* nFields */ 12, 11275 /* *fields */ soc_MPLS_DROP_BCM56960_A0fmt_fields, 11276 /* bits */ 12, 11277 /* flags */ 0, 11278 }, 11279 #endif /* chips */ 11280 11281 #if defined(BCM_56965_A0) 11282 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56965_A0fmt */ 11283 /* format MPLS_DROPfmt */ 11284 /* nFields */ 12, 11285 /* *fields */ soc_MPLS_DROP_BCM56960_A0fmt_fields, 11286 /* bits */ 12, 11287 /* flags */ 0, 11288 }, 11289 #endif /* chips */ 11290 11291 #if defined(BCM_56970_A0) 11292 { /* SOC_FORMAT_INT_MPLS_DROP_BCM56970_A0fmt */ 11293 /* format MPLS_DROPfmt */ 11294 /* nFields */ 12, 11295 /* *fields */ soc_MPLS_DROP_BCM56960_A0fmt_fields, 11296 /* bits */ 12, 11297 /* flags */ 0, 11298 }, 11299 #endif /* chips */ 11300 11301 #if defined(BCM_56640_A0) 11302 { /* SOC_FORMAT_INT_MPLS_ENTRY_1_DATAfmt */ 11303 /* format MPLS_ENTRY_1_DATAfmt */ 11304 /* nFields */ 29, 11305 /* *fields */ soc_MPLS_ENTRY_1_DATAfmt_fields, 11306 /* bits */ 59, 11307 /* flags */ 0, 11308 }, 11309 #endif /* chips */ 11310 11311 #if defined(BCM_56340_A0) 11312 { /* SOC_FORMAT_INT_MPLS_ENTRY_1_DATA_BCM56340_A0fmt */ 11313 /* format MPLS_ENTRY_1_DATAfmt */ 11314 /* nFields */ 31, 11315 /* *fields */ soc_MPLS_ENTRY_1_DATA_BCM56340_A0fmt_fields, 11316 /* bits */ 59, 11317 /* flags */ 0, 11318 }, 11319 #endif /* chips */ 11320 11321 #if defined(BCM_56640_A0) 11322 { /* SOC_FORMAT_INT_MPLS_ENTRY_2_DATAfmt */ 11323 /* format MPLS_ENTRY_2_DATAfmt */ 11324 /* nFields */ 70, 11325 /* *fields */ soc_MPLS_ENTRY_2_DATAfmt_fields, 11326 /* bits */ 91, 11327 /* flags */ 0, 11328 }, 11329 #endif /* chips */ 11330 11331 #if defined(BCM_56340_A0) 11332 { /* SOC_FORMAT_INT_MPLS_ENTRY_2_DATA_BCM56340_A0fmt */ 11333 /* format MPLS_ENTRY_2_DATAfmt */ 11334 /* nFields */ 79, 11335 /* *fields */ soc_MPLS_ENTRY_2_DATA_BCM56340_A0fmt_fields, 11336 /* bits */ 91, 11337 /* flags */ 0, 11338 }, 11339 #endif /* chips */ 11340 11341 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 11342 defined(BCM_56870_A0) 11343 { /* SOC_FORMAT_INT_MPLS_ENTRY_ACTION_SETfmt */ 11344 /* format MPLS_ENTRY_ACTION_SETfmt */ 11345 /* nFields */ 19, 11346 /* *fields */ soc_MPLS_ENTRY_ACTION_SETfmt_fields, 11347 /* bits */ 55, 11348 /* flags */ 0, 11349 }, 11350 #endif /* chips */ 11351 11352 #if defined(BCM_56860_A0) 11353 { /* SOC_FORMAT_INT_MPLS_ENTRY_COV_DEFSfmt */ 11354 /* format MPLS_ENTRY_COV_DEFSfmt */ 11355 /* nFields */ 7, 11356 /* *fields */ soc_MPLS_ENTRY_COV_DEFSfmt_fields, 11357 /* bits */ 31, 11358 /* flags */ 0, 11359 }, 11360 #endif /* chips */ 11361 11362 #if defined(BCM_56560_A0) 11363 { /* SOC_FORMAT_INT_MPLS_ENTRY_COV_DEFS_BCM56560_A0fmt */ 11364 /* format MPLS_ENTRY_COV_DEFSfmt */ 11365 /* nFields */ 7, 11366 /* *fields */ soc_MPLS_ENTRY_COV_DEFS_BCM56560_A0fmt_fields, 11367 /* bits */ 31, 11368 /* flags */ 0, 11369 }, 11370 #endif /* chips */ 11371 11372 #if defined(BCM_56560_B0) 11373 { /* SOC_FORMAT_INT_MPLS_ENTRY_COV_DEFS_BCM56560_B0fmt */ 11374 /* format MPLS_ENTRY_COV_DEFSfmt */ 11375 /* nFields */ 7, 11376 /* *fields */ soc_MPLS_ENTRY_COV_DEFS_BCM56560_A0fmt_fields, 11377 /* bits */ 31, 11378 /* flags */ 0, 11379 }, 11380 #endif /* chips */ 11381 11382 #if defined(BCM_56670_A0) 11383 { /* SOC_FORMAT_INT_MPLS_ENTRY_COV_DEFS_BCM56670_A0fmt */ 11384 /* format MPLS_ENTRY_COV_DEFSfmt */ 11385 /* nFields */ 7, 11386 /* *fields */ soc_MPLS_ENTRY_COV_DEFS_BCM56560_A0fmt_fields, 11387 /* bits */ 31, 11388 /* flags */ 0, 11389 }, 11390 #endif /* chips */ 11391 11392 #if defined(BCM_56670_B0) 11393 { /* SOC_FORMAT_INT_MPLS_ENTRY_COV_DEFS_BCM56670_B0fmt */ 11394 /* format MPLS_ENTRY_COV_DEFSfmt */ 11395 /* nFields */ 7, 11396 /* *fields */ soc_MPLS_ENTRY_COV_DEFS_BCM56560_A0fmt_fields, 11397 /* bits */ 31, 11398 /* flags */ 0, 11399 }, 11400 #endif /* chips */ 11401 11402 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 11403 { /* SOC_FORMAT_INT_MPLS_ENTRY_KEYfmt */ 11404 /* format MPLS_ENTRY_KEYfmt */ 11405 /* nFields */ 34, 11406 /* *fields */ soc_MPLS_ENTRY_KEYfmt_fields, 11407 /* bits */ 89, 11408 /* flags */ 0, 11409 }, 11410 #endif /* chips */ 11411 11412 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 11413 defined(BCM_56870_A0) 11414 { /* SOC_FORMAT_INT_MPLS_HDRfmt */ 11415 /* format MPLS_HDRfmt */ 11416 /* nFields */ 4, 11417 /* *fields */ soc_MPLS_HDRfmt_fields, 11418 /* bits */ 32, 11419 /* flags */ 0, 11420 }, 11421 #endif /* chips */ 11422 11423 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 11424 defined(BCM_56870_A0) 11425 { /* SOC_FORMAT_INT_MPLS_PW_TERM_CTR_ACTION_SETfmt */ 11426 /* format MPLS_PW_TERM_CTR_ACTION_SETfmt */ 11427 /* nFields */ 2, 11428 /* *fields */ soc_MPLS_PW_TERM_CTR_ACTION_SETfmt_fields, 11429 /* bits */ 15, 11430 /* flags */ 0, 11431 }, 11432 #endif /* chips */ 11433 11434 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 11435 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 11436 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 11437 defined(BCM_56850_A0) || defined(BCM_56860_A0) 11438 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABELfmt */ 11439 /* format MPLS_RESERVED_LABELfmt */ 11440 /* nFields */ 1, 11441 /* *fields */ soc_MPLS_RESERVED_LABELfmt_fields, 11442 /* bits */ 20, 11443 /* flags */ 0, 11444 }, 11445 #endif /* chips */ 11446 11447 #if defined(BCM_53400_A0) 11448 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM53400_A0fmt */ 11449 /* format MPLS_RESERVED_LABELfmt */ 11450 /* nFields */ 1, 11451 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11452 /* bits */ 20, 11453 /* flags */ 0, 11454 }, 11455 #endif /* chips */ 11456 11457 #if defined(BCM_53540_A0) 11458 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM53540_A0fmt */ 11459 /* format MPLS_RESERVED_LABELfmt */ 11460 /* nFields */ 1, 11461 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11462 /* bits */ 20, 11463 /* flags */ 0, 11464 }, 11465 #endif /* chips */ 11466 11467 #if defined(BCM_53570_A0) 11468 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM53570_A0fmt */ 11469 /* format MPLS_RESERVED_LABELfmt */ 11470 /* nFields */ 1, 11471 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11472 /* bits */ 20, 11473 /* flags */ 0, 11474 }, 11475 #endif /* chips */ 11476 11477 #if defined(BCM_53570_B0) 11478 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM53570_B0fmt */ 11479 /* format MPLS_RESERVED_LABELfmt */ 11480 /* nFields */ 1, 11481 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11482 /* bits */ 20, 11483 /* flags */ 0, 11484 }, 11485 #endif /* chips */ 11486 11487 #if defined(BCM_56160_A0) 11488 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56160_A0fmt */ 11489 /* format MPLS_RESERVED_LABELfmt */ 11490 /* nFields */ 1, 11491 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11492 /* bits */ 20, 11493 /* flags */ 0, 11494 }, 11495 #endif /* chips */ 11496 11497 #if defined(BCM_56260_A0) 11498 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56260_A0fmt */ 11499 /* format MPLS_RESERVED_LABELfmt */ 11500 /* nFields */ 1, 11501 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11502 /* bits */ 20, 11503 /* flags */ 0, 11504 }, 11505 #endif /* chips */ 11506 11507 #if defined(BCM_56260_B0) 11508 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56260_B0fmt */ 11509 /* format MPLS_RESERVED_LABELfmt */ 11510 /* nFields */ 1, 11511 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11512 /* bits */ 20, 11513 /* flags */ 0, 11514 }, 11515 #endif /* chips */ 11516 11517 #if defined(BCM_56270_A0) 11518 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56270_A0fmt */ 11519 /* format MPLS_RESERVED_LABELfmt */ 11520 /* nFields */ 1, 11521 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11522 /* bits */ 20, 11523 /* flags */ 0, 11524 }, 11525 #endif /* chips */ 11526 11527 #if defined(BCM_56370_A0) 11528 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56370_A0fmt */ 11529 /* format MPLS_RESERVED_LABELfmt */ 11530 /* nFields */ 1, 11531 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11532 /* bits */ 20, 11533 /* flags */ 0, 11534 }, 11535 #endif /* chips */ 11536 11537 #if defined(BCM_56560_A0) 11538 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56560_A0fmt */ 11539 /* format MPLS_RESERVED_LABELfmt */ 11540 /* nFields */ 1, 11541 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11542 /* bits */ 20, 11543 /* flags */ 0, 11544 }, 11545 #endif /* chips */ 11546 11547 #if defined(BCM_56560_B0) 11548 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56560_B0fmt */ 11549 /* format MPLS_RESERVED_LABELfmt */ 11550 /* nFields */ 1, 11551 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11552 /* bits */ 20, 11553 /* flags */ 0, 11554 }, 11555 #endif /* chips */ 11556 11557 #if defined(BCM_56670_A0) 11558 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56670_A0fmt */ 11559 /* format MPLS_RESERVED_LABELfmt */ 11560 /* nFields */ 1, 11561 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11562 /* bits */ 20, 11563 /* flags */ 0, 11564 }, 11565 #endif /* chips */ 11566 11567 #if defined(BCM_56670_B0) 11568 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56670_B0fmt */ 11569 /* format MPLS_RESERVED_LABELfmt */ 11570 /* nFields */ 1, 11571 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11572 /* bits */ 20, 11573 /* flags */ 0, 11574 }, 11575 #endif /* chips */ 11576 11577 #if defined(BCM_56770_A0) 11578 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56770_A0fmt */ 11579 /* format MPLS_RESERVED_LABELfmt */ 11580 /* nFields */ 1, 11581 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11582 /* bits */ 20, 11583 /* flags */ 0, 11584 }, 11585 #endif /* chips */ 11586 11587 #if defined(BCM_56870_A0) 11588 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56870_A0fmt */ 11589 /* format MPLS_RESERVED_LABELfmt */ 11590 /* nFields */ 1, 11591 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11592 /* bits */ 20, 11593 /* flags */ 0, 11594 }, 11595 #endif /* chips */ 11596 11597 #if defined(BCM_56960_A0) 11598 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56960_A0fmt */ 11599 /* format MPLS_RESERVED_LABELfmt */ 11600 /* nFields */ 1, 11601 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11602 /* bits */ 20, 11603 /* flags */ 0, 11604 }, 11605 #endif /* chips */ 11606 11607 #if defined(BCM_56965_A0) 11608 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56965_A0fmt */ 11609 /* format MPLS_RESERVED_LABELfmt */ 11610 /* nFields */ 1, 11611 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11612 /* bits */ 20, 11613 /* flags */ 0, 11614 }, 11615 #endif /* chips */ 11616 11617 #if defined(BCM_56970_A0) 11618 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56970_A0fmt */ 11619 /* format MPLS_RESERVED_LABELfmt */ 11620 /* nFields */ 1, 11621 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11622 /* bits */ 20, 11623 /* flags */ 0, 11624 }, 11625 #endif /* chips */ 11626 11627 #if defined(BCM_56980_A0) 11628 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56980_A0fmt */ 11629 /* format MPLS_RESERVED_LABELfmt */ 11630 /* nFields */ 1, 11631 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11632 /* bits */ 20, 11633 /* flags */ 0, 11634 }, 11635 #endif /* chips */ 11636 11637 #if defined(BCM_56980_B0) 11638 { /* SOC_FORMAT_INT_MPLS_RESERVED_LABEL_BCM56980_B0fmt */ 11639 /* format MPLS_RESERVED_LABELfmt */ 11640 /* nFields */ 1, 11641 /* *fields */ soc_MPLS_RESERVED_LABEL_BCM53400_A0fmt_fields, 11642 /* bits */ 20, 11643 /* flags */ 0, 11644 }, 11645 #endif /* chips */ 11646 11647 #if defined(BCM_56800_A0) 11648 { /* SOC_FORMAT_INT_MSBUS_32fmt */ 11649 /* format MSBUS_32fmt */ 11650 /* nFields */ 14, 11651 /* *fields */ soc_MSBUS_32fmt_fields, 11652 /* bits */ 64, 11653 /* flags */ 0, 11654 }, 11655 #endif /* chips */ 11656 11657 #if defined(BCM_56800_A0) 11658 { /* SOC_FORMAT_INT_MSBUS_96fmt */ 11659 /* format MSBUS_96fmt */ 11660 /* nFields */ 15, 11661 /* *fields */ soc_MSBUS_96fmt_fields, 11662 /* bits */ 130, 11663 /* flags */ 0, 11664 }, 11665 #endif /* chips */ 11666 11667 #if defined(BCM_56440_A0) 11668 { /* SOC_FORMAT_INT_MSBUS_128fmt */ 11669 /* format MSBUS_128fmt */ 11670 /* nFields */ 15, 11671 /* *fields */ soc_MSBUS_128fmt_fields, 11672 /* bits */ 163, 11673 /* flags */ 0, 11674 }, 11675 #endif /* chips */ 11676 11677 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 11678 { /* SOC_FORMAT_INT_MSBUS_160fmt */ 11679 /* format MSBUS_160fmt */ 11680 /* nFields */ 15, 11681 /* *fields */ soc_MSBUS_160fmt_fields, 11682 /* bits */ 201, 11683 /* flags */ 0, 11684 }, 11685 #endif /* chips */ 11686 11687 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 11688 defined(BCM_56870_A0) 11689 { /* SOC_FORMAT_INT_MSBUS_192fmt */ 11690 /* format MSBUS_192fmt */ 11691 /* nFields */ 15, 11692 /* *fields */ soc_MSBUS_192fmt_fields, 11693 /* bits */ 234, 11694 /* flags */ 0, 11695 }, 11696 #endif /* chips */ 11697 11698 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 11699 { /* SOC_FORMAT_INT_MSBUS_256fmt */ 11700 /* format MSBUS_256fmt */ 11701 /* nFields */ 15, 11702 /* *fields */ soc_MSBUS_256fmt_fields, 11703 /* bits */ 298, 11704 /* flags */ 0, 11705 }, 11706 #endif /* chips */ 11707 11708 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 11709 defined(BCM_56870_A0) || defined(BCM_56970_A0) 11710 { /* SOC_FORMAT_INT_MSBUS_288fmt */ 11711 /* format MSBUS_288fmt */ 11712 /* nFields */ 15, 11713 /* *fields */ soc_MSBUS_288fmt_fields, 11714 /* bits */ 330, 11715 /* flags */ 0, 11716 }, 11717 #endif /* chips */ 11718 11719 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 11720 { /* SOC_FORMAT_INT_MSBUS_448fmt */ 11721 /* format MSBUS_448fmt */ 11722 /* nFields */ 15, 11723 /* *fields */ soc_MSBUS_448fmt_fields, 11724 /* bits */ 490, 11725 /* flags */ 0, 11726 }, 11727 #endif /* chips */ 11728 11729 #if defined(BCM_56260_A0) 11730 { /* SOC_FORMAT_INT_MSBUS_128_BCM56260_A0fmt */ 11731 /* format MSBUS_128fmt */ 11732 /* nFields */ 15, 11733 /* *fields */ soc_MSBUS_128_BCM56260_A0fmt_fields, 11734 /* bits */ 169, 11735 /* flags */ 0, 11736 }, 11737 #endif /* chips */ 11738 11739 #if defined(BCM_56260_B0) 11740 { /* SOC_FORMAT_INT_MSBUS_128_BCM56260_B0fmt */ 11741 /* format MSBUS_128fmt */ 11742 /* nFields */ 15, 11743 /* *fields */ soc_MSBUS_128_BCM56260_A0fmt_fields, 11744 /* bits */ 169, 11745 /* flags */ 0, 11746 }, 11747 #endif /* chips */ 11748 11749 #if defined(BCM_56270_A0) 11750 { /* SOC_FORMAT_INT_MSBUS_128_BCM56270_A0fmt */ 11751 /* format MSBUS_128fmt */ 11752 /* nFields */ 15, 11753 /* *fields */ soc_MSBUS_128_BCM56260_A0fmt_fields, 11754 /* bits */ 169, 11755 /* flags */ 0, 11756 }, 11757 #endif /* chips */ 11758 11759 #if defined(BCM_56370_A0) 11760 { /* SOC_FORMAT_INT_MSBUS_128_BCM56370_A0fmt */ 11761 /* format MSBUS_128fmt */ 11762 /* nFields */ 15, 11763 /* *fields */ soc_MSBUS_128_BCM56970_A0fmt_fields, 11764 /* bits */ 170, 11765 /* flags */ 0, 11766 }, 11767 #endif /* chips */ 11768 11769 #if defined(BCM_56440_B0) 11770 { /* SOC_FORMAT_INT_MSBUS_128_BCM56440_B0fmt */ 11771 /* format MSBUS_128fmt */ 11772 /* nFields */ 15, 11773 /* *fields */ soc_MSBUS_128fmt_fields, 11774 /* bits */ 163, 11775 /* flags */ 0, 11776 }, 11777 #endif /* chips */ 11778 11779 #if defined(BCM_56450_A0) 11780 { /* SOC_FORMAT_INT_MSBUS_128_BCM56450_A0fmt */ 11781 /* format MSBUS_128fmt */ 11782 /* nFields */ 15, 11783 /* *fields */ soc_MSBUS_128_BCM56450_A0fmt_fields, 11784 /* bits */ 169, 11785 /* flags */ 0, 11786 }, 11787 #endif /* chips */ 11788 11789 #if defined(BCM_56450_B0) 11790 { /* SOC_FORMAT_INT_MSBUS_128_BCM56450_B0fmt */ 11791 /* format MSBUS_128fmt */ 11792 /* nFields */ 15, 11793 /* *fields */ soc_MSBUS_128_BCM56450_A0fmt_fields, 11794 /* bits */ 169, 11795 /* flags */ 0, 11796 }, 11797 #endif /* chips */ 11798 11799 #if defined(BCM_56450_B1) 11800 { /* SOC_FORMAT_INT_MSBUS_128_BCM56450_B1fmt */ 11801 /* format MSBUS_128fmt */ 11802 /* nFields */ 15, 11803 /* *fields */ soc_MSBUS_128_BCM56450_A0fmt_fields, 11804 /* bits */ 169, 11805 /* flags */ 0, 11806 }, 11807 #endif /* chips */ 11808 11809 #if defined(BCM_56770_A0) 11810 { /* SOC_FORMAT_INT_MSBUS_128_BCM56770_A0fmt */ 11811 /* format MSBUS_128fmt */ 11812 /* nFields */ 15, 11813 /* *fields */ soc_MSBUS_128_BCM56970_A0fmt_fields, 11814 /* bits */ 170, 11815 /* flags */ 0, 11816 }, 11817 #endif /* chips */ 11818 11819 #if defined(BCM_56870_A0) 11820 { /* SOC_FORMAT_INT_MSBUS_128_BCM56870_A0fmt */ 11821 /* format MSBUS_128fmt */ 11822 /* nFields */ 15, 11823 /* *fields */ soc_MSBUS_128_BCM56970_A0fmt_fields, 11824 /* bits */ 170, 11825 /* flags */ 0, 11826 }, 11827 #endif /* chips */ 11828 11829 #if defined(BCM_56960_A0) 11830 { /* SOC_FORMAT_INT_MSBUS_128_BCM56960_A0fmt */ 11831 /* format MSBUS_128fmt */ 11832 /* nFields */ 15, 11833 /* *fields */ soc_MSBUS_128_BCM56960_A0fmt_fields, 11834 /* bits */ 170, 11835 /* flags */ 0, 11836 }, 11837 #endif /* chips */ 11838 11839 #if defined(BCM_56965_A0) 11840 { /* SOC_FORMAT_INT_MSBUS_128_BCM56965_A0fmt */ 11841 /* format MSBUS_128fmt */ 11842 /* nFields */ 15, 11843 /* *fields */ soc_MSBUS_128_BCM56960_A0fmt_fields, 11844 /* bits */ 170, 11845 /* flags */ 0, 11846 }, 11847 #endif /* chips */ 11848 11849 #if defined(BCM_56970_A0) 11850 { /* SOC_FORMAT_INT_MSBUS_128_BCM56970_A0fmt */ 11851 /* format MSBUS_128fmt */ 11852 /* nFields */ 15, 11853 /* *fields */ soc_MSBUS_128_BCM56970_A0fmt_fields, 11854 /* bits */ 170, 11855 /* flags */ 0, 11856 }, 11857 #endif /* chips */ 11858 11859 #if defined(BCM_56560_A0) 11860 { /* SOC_FORMAT_INT_MSBUS_160_BCM56560_A0fmt */ 11861 /* format MSBUS_160fmt */ 11862 /* nFields */ 15, 11863 /* *fields */ soc_MSBUS_160_BCM56560_A0fmt_fields, 11864 /* bits */ 201, 11865 /* flags */ 0, 11866 }, 11867 #endif /* chips */ 11868 11869 #if defined(BCM_56560_B0) 11870 { /* SOC_FORMAT_INT_MSBUS_160_BCM56560_B0fmt */ 11871 /* format MSBUS_160fmt */ 11872 /* nFields */ 15, 11873 /* *fields */ soc_MSBUS_160_BCM56560_A0fmt_fields, 11874 /* bits */ 201, 11875 /* flags */ 0, 11876 }, 11877 #endif /* chips */ 11878 11879 #if defined(BCM_56670_A0) 11880 { /* SOC_FORMAT_INT_MSBUS_160_BCM56670_A0fmt */ 11881 /* format MSBUS_160fmt */ 11882 /* nFields */ 15, 11883 /* *fields */ soc_MSBUS_160_BCM56560_A0fmt_fields, 11884 /* bits */ 201, 11885 /* flags */ 0, 11886 }, 11887 #endif /* chips */ 11888 11889 #if defined(BCM_56670_B0) 11890 { /* SOC_FORMAT_INT_MSBUS_160_BCM56670_B0fmt */ 11891 /* format MSBUS_160fmt */ 11892 /* nFields */ 15, 11893 /* *fields */ soc_MSBUS_160_BCM56560_A0fmt_fields, 11894 /* bits */ 201, 11895 /* flags */ 0, 11896 }, 11897 #endif /* chips */ 11898 11899 #if defined(BCM_56850_A0) 11900 { /* SOC_FORMAT_INT_MSBUS_160_BCM56850_A0fmt */ 11901 /* format MSBUS_160fmt */ 11902 /* nFields */ 15, 11903 /* *fields */ soc_MSBUS_160_BCM56850_A0fmt_fields, 11904 /* bits */ 201, 11905 /* flags */ 0, 11906 }, 11907 #endif /* chips */ 11908 11909 #if defined(BCM_56860_A0) 11910 { /* SOC_FORMAT_INT_MSBUS_160_BCM56860_A0fmt */ 11911 /* format MSBUS_160fmt */ 11912 /* nFields */ 15, 11913 /* *fields */ soc_MSBUS_160_BCM56850_A0fmt_fields, 11914 /* bits */ 201, 11915 /* flags */ 0, 11916 }, 11917 #endif /* chips */ 11918 11919 #if defined(BCM_56960_A0) 11920 { /* SOC_FORMAT_INT_MSBUS_160_BCM56960_A0fmt */ 11921 /* format MSBUS_160fmt */ 11922 /* nFields */ 15, 11923 /* *fields */ soc_MSBUS_160_BCM56960_A0fmt_fields, 11924 /* bits */ 202, 11925 /* flags */ 0, 11926 }, 11927 #endif /* chips */ 11928 11929 #if defined(BCM_56965_A0) 11930 { /* SOC_FORMAT_INT_MSBUS_160_BCM56965_A0fmt */ 11931 /* format MSBUS_160fmt */ 11932 /* nFields */ 15, 11933 /* *fields */ soc_MSBUS_160_BCM56960_A0fmt_fields, 11934 /* bits */ 202, 11935 /* flags */ 0, 11936 }, 11937 #endif /* chips */ 11938 11939 #if defined(BCM_56970_A0) 11940 { /* SOC_FORMAT_INT_MSBUS_160_BCM56970_A0fmt */ 11941 /* format MSBUS_160fmt */ 11942 /* nFields */ 15, 11943 /* *fields */ soc_MSBUS_160_BCM56970_A0fmt_fields, 11944 /* bits */ 202, 11945 /* flags */ 0, 11946 }, 11947 #endif /* chips */ 11948 11949 #if defined(BCM_56370_A0) 11950 { /* SOC_FORMAT_INT_MSBUS_256_BCM56370_A0fmt */ 11951 /* format MSBUS_256fmt */ 11952 /* nFields */ 15, 11953 /* *fields */ soc_MSBUS_256_BCM56970_A0fmt_fields, 11954 /* bits */ 298, 11955 /* flags */ 0, 11956 }, 11957 #endif /* chips */ 11958 11959 #if defined(BCM_56560_A0) 11960 { /* SOC_FORMAT_INT_MSBUS_256_BCM56560_A0fmt */ 11961 /* format MSBUS_256fmt */ 11962 /* nFields */ 15, 11963 /* *fields */ soc_MSBUS_256_BCM56560_A0fmt_fields, 11964 /* bits */ 298, 11965 /* flags */ 0, 11966 }, 11967 #endif /* chips */ 11968 11969 #if defined(BCM_56560_B0) 11970 { /* SOC_FORMAT_INT_MSBUS_256_BCM56560_B0fmt */ 11971 /* format MSBUS_256fmt */ 11972 /* nFields */ 15, 11973 /* *fields */ soc_MSBUS_256_BCM56560_A0fmt_fields, 11974 /* bits */ 298, 11975 /* flags */ 0, 11976 }, 11977 #endif /* chips */ 11978 11979 #if defined(BCM_56670_A0) 11980 { /* SOC_FORMAT_INT_MSBUS_256_BCM56670_A0fmt */ 11981 /* format MSBUS_256fmt */ 11982 /* nFields */ 15, 11983 /* *fields */ soc_MSBUS_256_BCM56560_A0fmt_fields, 11984 /* bits */ 298, 11985 /* flags */ 0, 11986 }, 11987 #endif /* chips */ 11988 11989 #if defined(BCM_56670_B0) 11990 { /* SOC_FORMAT_INT_MSBUS_256_BCM56670_B0fmt */ 11991 /* format MSBUS_256fmt */ 11992 /* nFields */ 15, 11993 /* *fields */ soc_MSBUS_256_BCM56560_A0fmt_fields, 11994 /* bits */ 298, 11995 /* flags */ 0, 11996 }, 11997 #endif /* chips */ 11998 11999 #if defined(BCM_56770_A0) 12000 { /* SOC_FORMAT_INT_MSBUS_256_BCM56770_A0fmt */ 12001 /* format MSBUS_256fmt */ 12002 /* nFields */ 15, 12003 /* *fields */ soc_MSBUS_256_BCM56970_A0fmt_fields, 12004 /* bits */ 298, 12005 /* flags */ 0, 12006 }, 12007 #endif /* chips */ 12008 12009 #if defined(BCM_56870_A0) 12010 { /* SOC_FORMAT_INT_MSBUS_256_BCM56870_A0fmt */ 12011 /* format MSBUS_256fmt */ 12012 /* nFields */ 15, 12013 /* *fields */ soc_MSBUS_256_BCM56970_A0fmt_fields, 12014 /* bits */ 298, 12015 /* flags */ 0, 12016 }, 12017 #endif /* chips */ 12018 12019 #if defined(BCM_56960_A0) 12020 { /* SOC_FORMAT_INT_MSBUS_256_BCM56960_A0fmt */ 12021 /* format MSBUS_256fmt */ 12022 /* nFields */ 15, 12023 /* *fields */ soc_MSBUS_256_BCM56960_A0fmt_fields, 12024 /* bits */ 298, 12025 /* flags */ 0, 12026 }, 12027 #endif /* chips */ 12028 12029 #if defined(BCM_56965_A0) 12030 { /* SOC_FORMAT_INT_MSBUS_256_BCM56965_A0fmt */ 12031 /* format MSBUS_256fmt */ 12032 /* nFields */ 15, 12033 /* *fields */ soc_MSBUS_256_BCM56960_A0fmt_fields, 12034 /* bits */ 298, 12035 /* flags */ 0, 12036 }, 12037 #endif /* chips */ 12038 12039 #if defined(BCM_56970_A0) 12040 { /* SOC_FORMAT_INT_MSBUS_256_BCM56970_A0fmt */ 12041 /* format MSBUS_256fmt */ 12042 /* nFields */ 15, 12043 /* *fields */ soc_MSBUS_256_BCM56970_A0fmt_fields, 12044 /* bits */ 298, 12045 /* flags */ 0, 12046 }, 12047 #endif /* chips */ 12048 12049 #if defined(BCM_56260_A0) 12050 { /* SOC_FORMAT_INT_MSBUS_32_BCM56260_A0fmt */ 12051 /* format MSBUS_32fmt */ 12052 /* nFields */ 14, 12053 /* *fields */ soc_MSBUS_32_BCM56260_A0fmt_fields, 12054 /* bits */ 70, 12055 /* flags */ 0, 12056 }, 12057 #endif /* chips */ 12058 12059 #if defined(BCM_56260_B0) 12060 { /* SOC_FORMAT_INT_MSBUS_32_BCM56260_B0fmt */ 12061 /* format MSBUS_32fmt */ 12062 /* nFields */ 14, 12063 /* *fields */ soc_MSBUS_32_BCM56260_A0fmt_fields, 12064 /* bits */ 70, 12065 /* flags */ 0, 12066 }, 12067 #endif /* chips */ 12068 12069 #if defined(BCM_56270_A0) 12070 { /* SOC_FORMAT_INT_MSBUS_32_BCM56270_A0fmt */ 12071 /* format MSBUS_32fmt */ 12072 /* nFields */ 14, 12073 /* *fields */ soc_MSBUS_32_BCM56260_A0fmt_fields, 12074 /* bits */ 70, 12075 /* flags */ 0, 12076 }, 12077 #endif /* chips */ 12078 12079 #if defined(BCM_56334_A0) 12080 { /* SOC_FORMAT_INT_MSBUS_32_BCM56334_A0fmt */ 12081 /* format MSBUS_32fmt */ 12082 /* nFields */ 14, 12083 /* *fields */ soc_MSBUS_32fmt_fields, 12084 /* bits */ 64, 12085 /* flags */ 0, 12086 }, 12087 #endif /* chips */ 12088 12089 #if defined(BCM_56334_B0) 12090 { /* SOC_FORMAT_INT_MSBUS_32_BCM56334_B0fmt */ 12091 /* format MSBUS_32fmt */ 12092 /* nFields */ 14, 12093 /* *fields */ soc_MSBUS_32fmt_fields, 12094 /* bits */ 64, 12095 /* flags */ 0, 12096 }, 12097 #endif /* chips */ 12098 12099 #if defined(BCM_56440_A0) 12100 { /* SOC_FORMAT_INT_MSBUS_32_BCM56440_A0fmt */ 12101 /* format MSBUS_32fmt */ 12102 /* nFields */ 14, 12103 /* *fields */ soc_MSBUS_32_BCM56840_A0fmt_fields, 12104 /* bits */ 64, 12105 /* flags */ 0, 12106 }, 12107 #endif /* chips */ 12108 12109 #if defined(BCM_56440_B0) 12110 { /* SOC_FORMAT_INT_MSBUS_32_BCM56440_B0fmt */ 12111 /* format MSBUS_32fmt */ 12112 /* nFields */ 14, 12113 /* *fields */ soc_MSBUS_32_BCM56840_A0fmt_fields, 12114 /* bits */ 64, 12115 /* flags */ 0, 12116 }, 12117 #endif /* chips */ 12118 12119 #if defined(BCM_56450_A0) 12120 { /* SOC_FORMAT_INT_MSBUS_32_BCM56450_A0fmt */ 12121 /* format MSBUS_32fmt */ 12122 /* nFields */ 14, 12123 /* *fields */ soc_MSBUS_32_BCM56450_A0fmt_fields, 12124 /* bits */ 70, 12125 /* flags */ 0, 12126 }, 12127 #endif /* chips */ 12128 12129 #if defined(BCM_56450_B0) 12130 { /* SOC_FORMAT_INT_MSBUS_32_BCM56450_B0fmt */ 12131 /* format MSBUS_32fmt */ 12132 /* nFields */ 14, 12133 /* *fields */ soc_MSBUS_32_BCM56450_A0fmt_fields, 12134 /* bits */ 70, 12135 /* flags */ 0, 12136 }, 12137 #endif /* chips */ 12138 12139 #if defined(BCM_56450_B1) 12140 { /* SOC_FORMAT_INT_MSBUS_32_BCM56450_B1fmt */ 12141 /* format MSBUS_32fmt */ 12142 /* nFields */ 14, 12143 /* *fields */ soc_MSBUS_32_BCM56450_A0fmt_fields, 12144 /* bits */ 70, 12145 /* flags */ 0, 12146 }, 12147 #endif /* chips */ 12148 12149 #if defined(BCM_56524_A0) 12150 { /* SOC_FORMAT_INT_MSBUS_32_BCM56524_A0fmt */ 12151 /* format MSBUS_32fmt */ 12152 /* nFields */ 14, 12153 /* *fields */ soc_MSBUS_32fmt_fields, 12154 /* bits */ 64, 12155 /* flags */ 0, 12156 }, 12157 #endif /* chips */ 12158 12159 #if defined(BCM_56524_B0) 12160 { /* SOC_FORMAT_INT_MSBUS_32_BCM56524_B0fmt */ 12161 /* format MSBUS_32fmt */ 12162 /* nFields */ 14, 12163 /* *fields */ soc_MSBUS_32fmt_fields, 12164 /* bits */ 64, 12165 /* flags */ 0, 12166 }, 12167 #endif /* chips */ 12168 12169 #if defined(BCM_56624_A0) 12170 { /* SOC_FORMAT_INT_MSBUS_32_BCM56624_A0fmt */ 12171 /* format MSBUS_32fmt */ 12172 /* nFields */ 14, 12173 /* *fields */ soc_MSBUS_32fmt_fields, 12174 /* bits */ 64, 12175 /* flags */ 0, 12176 }, 12177 #endif /* chips */ 12178 12179 #if defined(BCM_56624_B0) 12180 { /* SOC_FORMAT_INT_MSBUS_32_BCM56624_B0fmt */ 12181 /* format MSBUS_32fmt */ 12182 /* nFields */ 14, 12183 /* *fields */ soc_MSBUS_32fmt_fields, 12184 /* bits */ 64, 12185 /* flags */ 0, 12186 }, 12187 #endif /* chips */ 12188 12189 #if defined(BCM_56634_A0) 12190 { /* SOC_FORMAT_INT_MSBUS_32_BCM56634_A0fmt */ 12191 /* format MSBUS_32fmt */ 12192 /* nFields */ 14, 12193 /* *fields */ soc_MSBUS_32fmt_fields, 12194 /* bits */ 64, 12195 /* flags */ 0, 12196 }, 12197 #endif /* chips */ 12198 12199 #if defined(BCM_56634_B0) 12200 { /* SOC_FORMAT_INT_MSBUS_32_BCM56634_B0fmt */ 12201 /* format MSBUS_32fmt */ 12202 /* nFields */ 14, 12203 /* *fields */ soc_MSBUS_32fmt_fields, 12204 /* bits */ 64, 12205 /* flags */ 0, 12206 }, 12207 #endif /* chips */ 12208 12209 #if defined(BCM_56680_A0) 12210 { /* SOC_FORMAT_INT_MSBUS_32_BCM56680_A0fmt */ 12211 /* format MSBUS_32fmt */ 12212 /* nFields */ 14, 12213 /* *fields */ soc_MSBUS_32fmt_fields, 12214 /* bits */ 64, 12215 /* flags */ 0, 12216 }, 12217 #endif /* chips */ 12218 12219 #if defined(BCM_56680_B0) 12220 { /* SOC_FORMAT_INT_MSBUS_32_BCM56680_B0fmt */ 12221 /* format MSBUS_32fmt */ 12222 /* nFields */ 14, 12223 /* *fields */ soc_MSBUS_32fmt_fields, 12224 /* bits */ 64, 12225 /* flags */ 0, 12226 }, 12227 #endif /* chips */ 12228 12229 #if defined(BCM_56685_A0) 12230 { /* SOC_FORMAT_INT_MSBUS_32_BCM56685_A0fmt */ 12231 /* format MSBUS_32fmt */ 12232 /* nFields */ 14, 12233 /* *fields */ soc_MSBUS_32fmt_fields, 12234 /* bits */ 64, 12235 /* flags */ 0, 12236 }, 12237 #endif /* chips */ 12238 12239 #if defined(BCM_56685_B0) 12240 { /* SOC_FORMAT_INT_MSBUS_32_BCM56685_B0fmt */ 12241 /* format MSBUS_32fmt */ 12242 /* nFields */ 14, 12243 /* *fields */ soc_MSBUS_32fmt_fields, 12244 /* bits */ 64, 12245 /* flags */ 0, 12246 }, 12247 #endif /* chips */ 12248 12249 #if defined(BCM_56725_A0) 12250 { /* SOC_FORMAT_INT_MSBUS_32_BCM56725_A0fmt */ 12251 /* format MSBUS_32fmt */ 12252 /* nFields */ 14, 12253 /* *fields */ soc_MSBUS_32fmt_fields, 12254 /* bits */ 64, 12255 /* flags */ 0, 12256 }, 12257 #endif /* chips */ 12258 12259 #if defined(BCM_56820_A0) 12260 { /* SOC_FORMAT_INT_MSBUS_32_BCM56820_A0fmt */ 12261 /* format MSBUS_32fmt */ 12262 /* nFields */ 14, 12263 /* *fields */ soc_MSBUS_32fmt_fields, 12264 /* bits */ 64, 12265 /* flags */ 0, 12266 }, 12267 #endif /* chips */ 12268 12269 #if defined(BCM_56840_A0) 12270 { /* SOC_FORMAT_INT_MSBUS_32_BCM56840_A0fmt */ 12271 /* format MSBUS_32fmt */ 12272 /* nFields */ 14, 12273 /* *fields */ soc_MSBUS_32_BCM56840_A0fmt_fields, 12274 /* bits */ 64, 12275 /* flags */ 0, 12276 }, 12277 #endif /* chips */ 12278 12279 #if defined(BCM_56840_B0) 12280 { /* SOC_FORMAT_INT_MSBUS_32_BCM56840_B0fmt */ 12281 /* format MSBUS_32fmt */ 12282 /* nFields */ 14, 12283 /* *fields */ soc_MSBUS_32_BCM56840_A0fmt_fields, 12284 /* bits */ 64, 12285 /* flags */ 0, 12286 }, 12287 #endif /* chips */ 12288 12289 #if defined(BCM_88732_A0) 12290 { /* SOC_FORMAT_INT_MSBUS_32_BCM88732_A0fmt */ 12291 /* format MSBUS_32fmt */ 12292 /* nFields */ 14, 12293 /* *fields */ soc_MSBUS_32fmt_fields, 12294 /* bits */ 64, 12295 /* flags */ 0, 12296 }, 12297 #endif /* chips */ 12298 12299 #if defined(BCM_56370_A0) 12300 { /* SOC_FORMAT_INT_MSBUS_448_BCM56370_A0fmt */ 12301 /* format MSBUS_448fmt */ 12302 /* nFields */ 15, 12303 /* *fields */ soc_MSBUS_448_BCM56970_A0fmt_fields, 12304 /* bits */ 490, 12305 /* flags */ 0, 12306 }, 12307 #endif /* chips */ 12308 12309 #if defined(BCM_56560_A0) 12310 { /* SOC_FORMAT_INT_MSBUS_448_BCM56560_A0fmt */ 12311 /* format MSBUS_448fmt */ 12312 /* nFields */ 15, 12313 /* *fields */ soc_MSBUS_448_BCM56560_A0fmt_fields, 12314 /* bits */ 490, 12315 /* flags */ 0, 12316 }, 12317 #endif /* chips */ 12318 12319 #if defined(BCM_56560_B0) 12320 { /* SOC_FORMAT_INT_MSBUS_448_BCM56560_B0fmt */ 12321 /* format MSBUS_448fmt */ 12322 /* nFields */ 15, 12323 /* *fields */ soc_MSBUS_448_BCM56560_A0fmt_fields, 12324 /* bits */ 490, 12325 /* flags */ 0, 12326 }, 12327 #endif /* chips */ 12328 12329 #if defined(BCM_56670_A0) 12330 { /* SOC_FORMAT_INT_MSBUS_448_BCM56670_A0fmt */ 12331 /* format MSBUS_448fmt */ 12332 /* nFields */ 15, 12333 /* *fields */ soc_MSBUS_448_BCM56560_A0fmt_fields, 12334 /* bits */ 490, 12335 /* flags */ 0, 12336 }, 12337 #endif /* chips */ 12338 12339 #if defined(BCM_56670_B0) 12340 { /* SOC_FORMAT_INT_MSBUS_448_BCM56670_B0fmt */ 12341 /* format MSBUS_448fmt */ 12342 /* nFields */ 15, 12343 /* *fields */ soc_MSBUS_448_BCM56560_A0fmt_fields, 12344 /* bits */ 490, 12345 /* flags */ 0, 12346 }, 12347 #endif /* chips */ 12348 12349 #if defined(BCM_56770_A0) 12350 { /* SOC_FORMAT_INT_MSBUS_448_BCM56770_A0fmt */ 12351 /* format MSBUS_448fmt */ 12352 /* nFields */ 15, 12353 /* *fields */ soc_MSBUS_448_BCM56970_A0fmt_fields, 12354 /* bits */ 490, 12355 /* flags */ 0, 12356 }, 12357 #endif /* chips */ 12358 12359 #if defined(BCM_56870_A0) 12360 { /* SOC_FORMAT_INT_MSBUS_448_BCM56870_A0fmt */ 12361 /* format MSBUS_448fmt */ 12362 /* nFields */ 15, 12363 /* *fields */ soc_MSBUS_448_BCM56970_A0fmt_fields, 12364 /* bits */ 490, 12365 /* flags */ 0, 12366 }, 12367 #endif /* chips */ 12368 12369 #if defined(BCM_56960_A0) 12370 { /* SOC_FORMAT_INT_MSBUS_448_BCM56960_A0fmt */ 12371 /* format MSBUS_448fmt */ 12372 /* nFields */ 15, 12373 /* *fields */ soc_MSBUS_448_BCM56960_A0fmt_fields, 12374 /* bits */ 490, 12375 /* flags */ 0, 12376 }, 12377 #endif /* chips */ 12378 12379 #if defined(BCM_56965_A0) 12380 { /* SOC_FORMAT_INT_MSBUS_448_BCM56965_A0fmt */ 12381 /* format MSBUS_448fmt */ 12382 /* nFields */ 15, 12383 /* *fields */ soc_MSBUS_448_BCM56960_A0fmt_fields, 12384 /* bits */ 490, 12385 /* flags */ 0, 12386 }, 12387 #endif /* chips */ 12388 12389 #if defined(BCM_56970_A0) 12390 { /* SOC_FORMAT_INT_MSBUS_448_BCM56970_A0fmt */ 12391 /* format MSBUS_448fmt */ 12392 /* nFields */ 15, 12393 /* *fields */ soc_MSBUS_448_BCM56970_A0fmt_fields, 12394 /* bits */ 490, 12395 /* flags */ 0, 12396 }, 12397 #endif /* chips */ 12398 12399 #if defined(BCM_56260_A0) 12400 { /* SOC_FORMAT_INT_MSBUS_96_BCM56260_A0fmt */ 12401 /* format MSBUS_96fmt */ 12402 /* nFields */ 18, 12403 /* *fields */ soc_MSBUS_96_BCM56260_A0fmt_fields, 12404 /* bits */ 136, 12405 /* flags */ 0, 12406 }, 12407 #endif /* chips */ 12408 12409 #if defined(BCM_56260_B0) 12410 { /* SOC_FORMAT_INT_MSBUS_96_BCM56260_B0fmt */ 12411 /* format MSBUS_96fmt */ 12412 /* nFields */ 18, 12413 /* *fields */ soc_MSBUS_96_BCM56260_A0fmt_fields, 12414 /* bits */ 136, 12415 /* flags */ 0, 12416 }, 12417 #endif /* chips */ 12418 12419 #if defined(BCM_56270_A0) 12420 { /* SOC_FORMAT_INT_MSBUS_96_BCM56270_A0fmt */ 12421 /* format MSBUS_96fmt */ 12422 /* nFields */ 18, 12423 /* *fields */ soc_MSBUS_96_BCM56260_A0fmt_fields, 12424 /* bits */ 136, 12425 /* flags */ 0, 12426 }, 12427 #endif /* chips */ 12428 12429 #if defined(BCM_56334_A0) 12430 { /* SOC_FORMAT_INT_MSBUS_96_BCM56334_A0fmt */ 12431 /* format MSBUS_96fmt */ 12432 /* nFields */ 15, 12433 /* *fields */ soc_MSBUS_96fmt_fields, 12434 /* bits */ 130, 12435 /* flags */ 0, 12436 }, 12437 #endif /* chips */ 12438 12439 #if defined(BCM_56334_B0) 12440 { /* SOC_FORMAT_INT_MSBUS_96_BCM56334_B0fmt */ 12441 /* format MSBUS_96fmt */ 12442 /* nFields */ 15, 12443 /* *fields */ soc_MSBUS_96fmt_fields, 12444 /* bits */ 130, 12445 /* flags */ 0, 12446 }, 12447 #endif /* chips */ 12448 12449 #if defined(BCM_56340_A0) 12450 { /* SOC_FORMAT_INT_MSBUS_96_BCM56340_A0fmt */ 12451 /* format MSBUS_96fmt */ 12452 /* nFields */ 15, 12453 /* *fields */ soc_MSBUS_96_BCM56640_A0fmt_fields, 12454 /* bits */ 136, 12455 /* flags */ 0, 12456 }, 12457 #endif /* chips */ 12458 12459 #if defined(BCM_56370_A0) 12460 { /* SOC_FORMAT_INT_MSBUS_96_BCM56370_A0fmt */ 12461 /* format MSBUS_96fmt */ 12462 /* nFields */ 15, 12463 /* *fields */ soc_MMU_CFAP_MSBUSfmt_fields, 12464 /* bits */ 138, 12465 /* flags */ 0, 12466 }, 12467 #endif /* chips */ 12468 12469 #if defined(BCM_56440_A0) 12470 { /* SOC_FORMAT_INT_MSBUS_96_BCM56440_A0fmt */ 12471 /* format MSBUS_96fmt */ 12472 /* nFields */ 18, 12473 /* *fields */ soc_MSBUS_96_BCM56440_A0fmt_fields, 12474 /* bits */ 130, 12475 /* flags */ 0, 12476 }, 12477 #endif /* chips */ 12478 12479 #if defined(BCM_56440_B0) 12480 { /* SOC_FORMAT_INT_MSBUS_96_BCM56440_B0fmt */ 12481 /* format MSBUS_96fmt */ 12482 /* nFields */ 18, 12483 /* *fields */ soc_MSBUS_96_BCM56440_A0fmt_fields, 12484 /* bits */ 130, 12485 /* flags */ 0, 12486 }, 12487 #endif /* chips */ 12488 12489 #if defined(BCM_56450_A0) 12490 { /* SOC_FORMAT_INT_MSBUS_96_BCM56450_A0fmt */ 12491 /* format MSBUS_96fmt */ 12492 /* nFields */ 18, 12493 /* *fields */ soc_MSBUS_96_BCM56450_A0fmt_fields, 12494 /* bits */ 136, 12495 /* flags */ 0, 12496 }, 12497 #endif /* chips */ 12498 12499 #if defined(BCM_56450_B0) 12500 { /* SOC_FORMAT_INT_MSBUS_96_BCM56450_B0fmt */ 12501 /* format MSBUS_96fmt */ 12502 /* nFields */ 18, 12503 /* *fields */ soc_MSBUS_96_BCM56450_A0fmt_fields, 12504 /* bits */ 136, 12505 /* flags */ 0, 12506 }, 12507 #endif /* chips */ 12508 12509 #if defined(BCM_56450_B1) 12510 { /* SOC_FORMAT_INT_MSBUS_96_BCM56450_B1fmt */ 12511 /* format MSBUS_96fmt */ 12512 /* nFields */ 18, 12513 /* *fields */ soc_MSBUS_96_BCM56450_A0fmt_fields, 12514 /* bits */ 136, 12515 /* flags */ 0, 12516 }, 12517 #endif /* chips */ 12518 12519 #if defined(BCM_56524_A0) 12520 { /* SOC_FORMAT_INT_MSBUS_96_BCM56524_A0fmt */ 12521 /* format MSBUS_96fmt */ 12522 /* nFields */ 15, 12523 /* *fields */ soc_MSBUS_96fmt_fields, 12524 /* bits */ 130, 12525 /* flags */ 0, 12526 }, 12527 #endif /* chips */ 12528 12529 #if defined(BCM_56524_B0) 12530 { /* SOC_FORMAT_INT_MSBUS_96_BCM56524_B0fmt */ 12531 /* format MSBUS_96fmt */ 12532 /* nFields */ 15, 12533 /* *fields */ soc_MSBUS_96fmt_fields, 12534 /* bits */ 130, 12535 /* flags */ 0, 12536 }, 12537 #endif /* chips */ 12538 12539 #if defined(BCM_56560_A0) 12540 { /* SOC_FORMAT_INT_MSBUS_96_BCM56560_A0fmt */ 12541 /* format MSBUS_96fmt */ 12542 /* nFields */ 15, 12543 /* *fields */ soc_MSBUS_96_BCM56560_A0fmt_fields, 12544 /* bits */ 136, 12545 /* flags */ 0, 12546 }, 12547 #endif /* chips */ 12548 12549 #if defined(BCM_56560_B0) 12550 { /* SOC_FORMAT_INT_MSBUS_96_BCM56560_B0fmt */ 12551 /* format MSBUS_96fmt */ 12552 /* nFields */ 15, 12553 /* *fields */ soc_MSBUS_96_BCM56560_A0fmt_fields, 12554 /* bits */ 136, 12555 /* flags */ 0, 12556 }, 12557 #endif /* chips */ 12558 12559 #if defined(BCM_56624_A0) 12560 { /* SOC_FORMAT_INT_MSBUS_96_BCM56624_A0fmt */ 12561 /* format MSBUS_96fmt */ 12562 /* nFields */ 15, 12563 /* *fields */ soc_MSBUS_96fmt_fields, 12564 /* bits */ 130, 12565 /* flags */ 0, 12566 }, 12567 #endif /* chips */ 12568 12569 #if defined(BCM_56624_B0) 12570 { /* SOC_FORMAT_INT_MSBUS_96_BCM56624_B0fmt */ 12571 /* format MSBUS_96fmt */ 12572 /* nFields */ 15, 12573 /* *fields */ soc_MSBUS_96fmt_fields, 12574 /* bits */ 130, 12575 /* flags */ 0, 12576 }, 12577 #endif /* chips */ 12578 12579 #if defined(BCM_56634_A0) 12580 { /* SOC_FORMAT_INT_MSBUS_96_BCM56634_A0fmt */ 12581 /* format MSBUS_96fmt */ 12582 /* nFields */ 15, 12583 /* *fields */ soc_MSBUS_96fmt_fields, 12584 /* bits */ 130, 12585 /* flags */ 0, 12586 }, 12587 #endif /* chips */ 12588 12589 #if defined(BCM_56634_B0) 12590 { /* SOC_FORMAT_INT_MSBUS_96_BCM56634_B0fmt */ 12591 /* format MSBUS_96fmt */ 12592 /* nFields */ 15, 12593 /* *fields */ soc_MSBUS_96fmt_fields, 12594 /* bits */ 130, 12595 /* flags */ 0, 12596 }, 12597 #endif /* chips */ 12598 12599 #if defined(BCM_56640_A0) 12600 { /* SOC_FORMAT_INT_MSBUS_96_BCM56640_A0fmt */ 12601 /* format MSBUS_96fmt */ 12602 /* nFields */ 15, 12603 /* *fields */ soc_MSBUS_96_BCM56640_A0fmt_fields, 12604 /* bits */ 136, 12605 /* flags */ 0, 12606 }, 12607 #endif /* chips */ 12608 12609 #if defined(BCM_56670_A0) 12610 { /* SOC_FORMAT_INT_MSBUS_96_BCM56670_A0fmt */ 12611 /* format MSBUS_96fmt */ 12612 /* nFields */ 15, 12613 /* *fields */ soc_MSBUS_96_BCM56560_A0fmt_fields, 12614 /* bits */ 136, 12615 /* flags */ 0, 12616 }, 12617 #endif /* chips */ 12618 12619 #if defined(BCM_56670_B0) 12620 { /* SOC_FORMAT_INT_MSBUS_96_BCM56670_B0fmt */ 12621 /* format MSBUS_96fmt */ 12622 /* nFields */ 15, 12623 /* *fields */ soc_MSBUS_96_BCM56560_A0fmt_fields, 12624 /* bits */ 136, 12625 /* flags */ 0, 12626 }, 12627 #endif /* chips */ 12628 12629 #if defined(BCM_56680_A0) 12630 { /* SOC_FORMAT_INT_MSBUS_96_BCM56680_A0fmt */ 12631 /* format MSBUS_96fmt */ 12632 /* nFields */ 15, 12633 /* *fields */ soc_MSBUS_96fmt_fields, 12634 /* bits */ 130, 12635 /* flags */ 0, 12636 }, 12637 #endif /* chips */ 12638 12639 #if defined(BCM_56680_B0) 12640 { /* SOC_FORMAT_INT_MSBUS_96_BCM56680_B0fmt */ 12641 /* format MSBUS_96fmt */ 12642 /* nFields */ 15, 12643 /* *fields */ soc_MSBUS_96fmt_fields, 12644 /* bits */ 130, 12645 /* flags */ 0, 12646 }, 12647 #endif /* chips */ 12648 12649 #if defined(BCM_56685_A0) 12650 { /* SOC_FORMAT_INT_MSBUS_96_BCM56685_A0fmt */ 12651 /* format MSBUS_96fmt */ 12652 /* nFields */ 15, 12653 /* *fields */ soc_MSBUS_96fmt_fields, 12654 /* bits */ 130, 12655 /* flags */ 0, 12656 }, 12657 #endif /* chips */ 12658 12659 #if defined(BCM_56685_B0) 12660 { /* SOC_FORMAT_INT_MSBUS_96_BCM56685_B0fmt */ 12661 /* format MSBUS_96fmt */ 12662 /* nFields */ 15, 12663 /* *fields */ soc_MSBUS_96fmt_fields, 12664 /* bits */ 130, 12665 /* flags */ 0, 12666 }, 12667 #endif /* chips */ 12668 12669 #if defined(BCM_56725_A0) 12670 { /* SOC_FORMAT_INT_MSBUS_96_BCM56725_A0fmt */ 12671 /* format MSBUS_96fmt */ 12672 /* nFields */ 15, 12673 /* *fields */ soc_MSBUS_96fmt_fields, 12674 /* bits */ 130, 12675 /* flags */ 0, 12676 }, 12677 #endif /* chips */ 12678 12679 #if defined(BCM_56770_A0) 12680 { /* SOC_FORMAT_INT_MSBUS_96_BCM56770_A0fmt */ 12681 /* format MSBUS_96fmt */ 12682 /* nFields */ 15, 12683 /* *fields */ soc_MMU_CFAP_MSBUSfmt_fields, 12684 /* bits */ 138, 12685 /* flags */ 0, 12686 }, 12687 #endif /* chips */ 12688 12689 #if defined(BCM_56820_A0) 12690 { /* SOC_FORMAT_INT_MSBUS_96_BCM56820_A0fmt */ 12691 /* format MSBUS_96fmt */ 12692 /* nFields */ 15, 12693 /* *fields */ soc_MSBUS_96fmt_fields, 12694 /* bits */ 130, 12695 /* flags */ 0, 12696 }, 12697 #endif /* chips */ 12698 12699 #if defined(BCM_56840_A0) 12700 { /* SOC_FORMAT_INT_MSBUS_96_BCM56840_A0fmt */ 12701 /* format MSBUS_96fmt */ 12702 /* nFields */ 15, 12703 /* *fields */ soc_MSBUS_96_BCM56840_A0fmt_fields, 12704 /* bits */ 130, 12705 /* flags */ 0, 12706 }, 12707 #endif /* chips */ 12708 12709 #if defined(BCM_56840_B0) 12710 { /* SOC_FORMAT_INT_MSBUS_96_BCM56840_B0fmt */ 12711 /* format MSBUS_96fmt */ 12712 /* nFields */ 15, 12713 /* *fields */ soc_MSBUS_96_BCM56840_A0fmt_fields, 12714 /* bits */ 130, 12715 /* flags */ 0, 12716 }, 12717 #endif /* chips */ 12718 12719 #if defined(BCM_56850_A0) 12720 { /* SOC_FORMAT_INT_MSBUS_96_BCM56850_A0fmt */ 12721 /* format MSBUS_96fmt */ 12722 /* nFields */ 15, 12723 /* *fields */ soc_MSBUS_96_BCM56850_A0fmt_fields, 12724 /* bits */ 136, 12725 /* flags */ 0, 12726 }, 12727 #endif /* chips */ 12728 12729 #if defined(BCM_56860_A0) 12730 { /* SOC_FORMAT_INT_MSBUS_96_BCM56860_A0fmt */ 12731 /* format MSBUS_96fmt */ 12732 /* nFields */ 15, 12733 /* *fields */ soc_MSBUS_96_BCM56850_A0fmt_fields, 12734 /* bits */ 136, 12735 /* flags */ 0, 12736 }, 12737 #endif /* chips */ 12738 12739 #if defined(BCM_56870_A0) 12740 { /* SOC_FORMAT_INT_MSBUS_96_BCM56870_A0fmt */ 12741 /* format MSBUS_96fmt */ 12742 /* nFields */ 15, 12743 /* *fields */ soc_MMU_CFAP_MSBUSfmt_fields, 12744 /* bits */ 138, 12745 /* flags */ 0, 12746 }, 12747 #endif /* chips */ 12748 12749 #if defined(BCM_56960_A0) 12750 { /* SOC_FORMAT_INT_MSBUS_96_BCM56960_A0fmt */ 12751 /* format MSBUS_96fmt */ 12752 /* nFields */ 15, 12753 /* *fields */ soc_MSBUS_96_BCM56960_A0fmt_fields, 12754 /* bits */ 138, 12755 /* flags */ 0, 12756 }, 12757 #endif /* chips */ 12758 12759 #if defined(BCM_56965_A0) 12760 { /* SOC_FORMAT_INT_MSBUS_96_BCM56965_A0fmt */ 12761 /* format MSBUS_96fmt */ 12762 /* nFields */ 15, 12763 /* *fields */ soc_MSBUS_96_BCM56960_A0fmt_fields, 12764 /* bits */ 138, 12765 /* flags */ 0, 12766 }, 12767 #endif /* chips */ 12768 12769 #if defined(BCM_56970_A0) 12770 { /* SOC_FORMAT_INT_MSBUS_96_BCM56970_A0fmt */ 12771 /* format MSBUS_96fmt */ 12772 /* nFields */ 15, 12773 /* *fields */ soc_MMU_CFAP_MSBUSfmt_fields, 12774 /* bits */ 138, 12775 /* flags */ 0, 12776 }, 12777 #endif /* chips */ 12778 12779 #if defined(BCM_88732_A0) 12780 { /* SOC_FORMAT_INT_MSBUS_96_BCM88732_A0fmt */ 12781 /* format MSBUS_96fmt */ 12782 /* nFields */ 15, 12783 /* *fields */ soc_MSBUS_96fmt_fields, 12784 /* bits */ 130, 12785 /* flags */ 0, 12786 }, 12787 #endif /* chips */ 12788 12789 #if defined(BCM_56440_A0) 12790 { /* SOC_FORMAT_INT_MSBUS_96_REDUCEDfmt */ 12791 /* format MSBUS_96_REDUCEDfmt */ 12792 /* nFields */ 3, 12793 /* *fields */ soc_MSBUS_96_REDUCEDfmt_fields, 12794 /* bits */ 70, 12795 /* flags */ 0, 12796 }, 12797 #endif /* chips */ 12798 12799 #if defined(BCM_56260_A0) 12800 { /* SOC_FORMAT_INT_MSBUS_96_REDUCED_BCM56260_A0fmt */ 12801 /* format MSBUS_96_REDUCEDfmt */ 12802 /* nFields */ 3, 12803 /* *fields */ soc_MSBUS_96_REDUCED_BCM56260_A0fmt_fields, 12804 /* bits */ 76, 12805 /* flags */ 0, 12806 }, 12807 #endif /* chips */ 12808 12809 #if defined(BCM_56260_B0) 12810 { /* SOC_FORMAT_INT_MSBUS_96_REDUCED_BCM56260_B0fmt */ 12811 /* format MSBUS_96_REDUCEDfmt */ 12812 /* nFields */ 3, 12813 /* *fields */ soc_MSBUS_96_REDUCED_BCM56260_A0fmt_fields, 12814 /* bits */ 76, 12815 /* flags */ 0, 12816 }, 12817 #endif /* chips */ 12818 12819 #if defined(BCM_56270_A0) 12820 { /* SOC_FORMAT_INT_MSBUS_96_REDUCED_BCM56270_A0fmt */ 12821 /* format MSBUS_96_REDUCEDfmt */ 12822 /* nFields */ 3, 12823 /* *fields */ soc_MSBUS_96_REDUCED_BCM56260_A0fmt_fields, 12824 /* bits */ 76, 12825 /* flags */ 0, 12826 }, 12827 #endif /* chips */ 12828 12829 #if defined(BCM_56440_B0) 12830 { /* SOC_FORMAT_INT_MSBUS_96_REDUCED_BCM56440_B0fmt */ 12831 /* format MSBUS_96_REDUCEDfmt */ 12832 /* nFields */ 3, 12833 /* *fields */ soc_MSBUS_96_REDUCEDfmt_fields, 12834 /* bits */ 70, 12835 /* flags */ 0, 12836 }, 12837 #endif /* chips */ 12838 12839 #if defined(BCM_56450_A0) 12840 { /* SOC_FORMAT_INT_MSBUS_96_REDUCED_BCM56450_A0fmt */ 12841 /* format MSBUS_96_REDUCEDfmt */ 12842 /* nFields */ 3, 12843 /* *fields */ soc_MSBUS_96_REDUCED_BCM56450_A0fmt_fields, 12844 /* bits */ 76, 12845 /* flags */ 0, 12846 }, 12847 #endif /* chips */ 12848 12849 #if defined(BCM_56450_B0) 12850 { /* SOC_FORMAT_INT_MSBUS_96_REDUCED_BCM56450_B0fmt */ 12851 /* format MSBUS_96_REDUCEDfmt */ 12852 /* nFields */ 3, 12853 /* *fields */ soc_MSBUS_96_REDUCED_BCM56450_A0fmt_fields, 12854 /* bits */ 76, 12855 /* flags */ 0, 12856 }, 12857 #endif /* chips */ 12858 12859 #if defined(BCM_56450_B1) 12860 { /* SOC_FORMAT_INT_MSBUS_96_REDUCED_BCM56450_B1fmt */ 12861 /* format MSBUS_96_REDUCEDfmt */ 12862 /* nFields */ 3, 12863 /* *fields */ soc_MSBUS_96_REDUCED_BCM56450_A0fmt_fields, 12864 /* bits */ 76, 12865 /* flags */ 0, 12866 }, 12867 #endif /* chips */ 12868 12869 #if defined(BCM_88732_A0) 12870 { /* SOC_FORMAT_INT_MS_TO_IARB_IFfmt */ 12871 /* format MS_TO_IARB_IFfmt */ 12872 /* nFields */ 15, 12873 /* *fields */ soc_MS_TO_IARB_IFfmt_fields, 12874 /* bits */ 22, 12875 /* flags */ 0, 12876 }, 12877 #endif /* chips */ 12878 12879 #if defined(BCM_88732_A0) 12880 { /* SOC_FORMAT_INT_MS_TO_PE_IFfmt */ 12881 /* format MS_TO_PE_IFfmt */ 12882 /* nFields */ 14, 12883 /* *fields */ soc_MS_TO_PE_IFfmt_fields, 12884 /* bits */ 27, 12885 /* flags */ 0, 12886 }, 12887 #endif /* chips */ 12888 12889 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 12890 { /* SOC_FORMAT_INT_MTRO_BUCKET_RF_FIELDSfmt */ 12891 /* format MTRO_BUCKET_RF_FIELDSfmt */ 12892 /* nFields */ 6, 12893 /* *fields */ soc_MTRO_BUCKET_RF_FIELDSfmt_fields, 12894 /* bits */ 60, 12895 /* flags */ 0, 12896 }, 12897 #endif /* chips */ 12898 12899 #if defined(BCM_88732_A0) 12900 { /* SOC_FORMAT_INT_MTRO_BUCKET_RF_FIELDS_BCM88732_A0fmt */ 12901 /* format MTRO_BUCKET_RF_FIELDSfmt */ 12902 /* nFields */ 6, 12903 /* *fields */ soc_MTRO_BUCKET_RF_FIELDS_BCM88732_A0fmt_fields, 12904 /* bits */ 66, 12905 /* flags */ 0, 12906 }, 12907 #endif /* chips */ 12908 12909 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 12910 { /* SOC_FORMAT_INT_MTRO_CONFIG_RF_FIELDSfmt */ 12911 /* format MTRO_CONFIG_RF_FIELDSfmt */ 12912 /* nFields */ 14, 12913 /* *fields */ soc_MTRO_CONFIG_RF_FIELDSfmt_fields, 12914 /* bits */ 70, 12915 /* flags */ 0, 12916 }, 12917 #endif /* chips */ 12918 12919 #if defined(BCM_88732_A0) 12920 { /* SOC_FORMAT_INT_MTRO_CONFIG_RF_FIELDS_BCM88732_A0fmt */ 12921 /* format MTRO_CONFIG_RF_FIELDSfmt */ 12922 /* nFields */ 14, 12923 /* *fields */ soc_MTRO_CONFIG_RF_FIELDS_BCM88732_A0fmt_fields, 12924 /* bits */ 74, 12925 /* flags */ 0, 12926 }, 12927 #endif /* chips */ 12928 12929 #if defined(BCM_56334_A0) 12930 { /* SOC_FORMAT_INT_MTRO_CPU_METER_RF_FIELDSfmt */ 12931 /* format MTRO_CPU_METER_RF_FIELDSfmt */ 12932 /* nFields */ 10, 12933 /* *fields */ soc_MTRO_CPU_METER_RF_FIELDSfmt_fields, 12934 /* bits */ 66, 12935 /* flags */ 0, 12936 }, 12937 #endif /* chips */ 12938 12939 #if defined(BCM_56334_B0) 12940 { /* SOC_FORMAT_INT_MTRO_CPU_METER_RF_FIELDS_BCM56334_B0fmt */ 12941 /* format MTRO_CPU_METER_RF_FIELDSfmt */ 12942 /* nFields */ 10, 12943 /* *fields */ soc_MTRO_CPU_METER_RF_FIELDSfmt_fields, 12944 /* bits */ 66, 12945 /* flags */ 0, 12946 }, 12947 #endif /* chips */ 12948 12949 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 12950 { /* SOC_FORMAT_INT_MTRO_PD_FIELDSfmt */ 12951 /* format MTRO_PD_FIELDSfmt */ 12952 /* nFields */ 14, 12953 /* *fields */ soc_MTRO_PD_FIELDSfmt_fields, 12954 /* bits */ 70, 12955 /* flags */ 0, 12956 }, 12957 #endif /* chips */ 12958 12959 #if defined(BCM_56370_A0) 12960 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56370_A0fmt */ 12961 /* format MTRO_PD_FIELDSfmt */ 12962 /* nFields */ 13, 12963 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 12964 /* bits */ 76, 12965 /* flags */ 0, 12966 }, 12967 #endif /* chips */ 12968 12969 #if defined(BCM_56560_A0) 12970 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56560_A0fmt */ 12971 /* format MTRO_PD_FIELDSfmt */ 12972 /* nFields */ 13, 12973 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 12974 /* bits */ 76, 12975 /* flags */ 0, 12976 }, 12977 #endif /* chips */ 12978 12979 #if defined(BCM_56560_B0) 12980 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56560_B0fmt */ 12981 /* format MTRO_PD_FIELDSfmt */ 12982 /* nFields */ 13, 12983 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 12984 /* bits */ 76, 12985 /* flags */ 0, 12986 }, 12987 #endif /* chips */ 12988 12989 #if defined(BCM_56670_A0) 12990 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56670_A0fmt */ 12991 /* format MTRO_PD_FIELDSfmt */ 12992 /* nFields */ 13, 12993 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 12994 /* bits */ 76, 12995 /* flags */ 0, 12996 }, 12997 #endif /* chips */ 12998 12999 #if defined(BCM_56670_B0) 13000 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56670_B0fmt */ 13001 /* format MTRO_PD_FIELDSfmt */ 13002 /* nFields */ 13, 13003 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 13004 /* bits */ 76, 13005 /* flags */ 0, 13006 }, 13007 #endif /* chips */ 13008 13009 #if defined(BCM_56770_A0) 13010 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56770_A0fmt */ 13011 /* format MTRO_PD_FIELDSfmt */ 13012 /* nFields */ 13, 13013 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 13014 /* bits */ 76, 13015 /* flags */ 0, 13016 }, 13017 #endif /* chips */ 13018 13019 #if defined(BCM_56850_A0) 13020 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56850_A0fmt */ 13021 /* format MTRO_PD_FIELDSfmt */ 13022 /* nFields */ 14, 13023 /* *fields */ soc_MTRO_PD_FIELDS_BCM56850_A0fmt_fields, 13024 /* bits */ 70, 13025 /* flags */ 0, 13026 }, 13027 #endif /* chips */ 13028 13029 #if defined(BCM_56860_A0) 13030 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56860_A0fmt */ 13031 /* format MTRO_PD_FIELDSfmt */ 13032 /* nFields */ 13, 13033 /* *fields */ soc_MTRO_PD_FIELDS_BCM56860_A0fmt_fields, 13034 /* bits */ 76, 13035 /* flags */ 0, 13036 }, 13037 #endif /* chips */ 13038 13039 #if defined(BCM_56870_A0) 13040 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56870_A0fmt */ 13041 /* format MTRO_PD_FIELDSfmt */ 13042 /* nFields */ 13, 13043 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 13044 /* bits */ 76, 13045 /* flags */ 0, 13046 }, 13047 #endif /* chips */ 13048 13049 #if defined(BCM_56960_A0) 13050 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56960_A0fmt */ 13051 /* format MTRO_PD_FIELDSfmt */ 13052 /* nFields */ 13, 13053 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 13054 /* bits */ 76, 13055 /* flags */ 0, 13056 }, 13057 #endif /* chips */ 13058 13059 #if defined(BCM_56965_A0) 13060 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56965_A0fmt */ 13061 /* format MTRO_PD_FIELDSfmt */ 13062 /* nFields */ 13, 13063 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 13064 /* bits */ 76, 13065 /* flags */ 0, 13066 }, 13067 #endif /* chips */ 13068 13069 #if defined(BCM_56970_A0) 13070 { /* SOC_FORMAT_INT_MTRO_PD_FIELDS_BCM56970_A0fmt */ 13071 /* format MTRO_PD_FIELDSfmt */ 13072 /* nFields */ 13, 13073 /* *fields */ soc_MTRO_PD_FIELDS_BCM56960_A0fmt_fields, 13074 /* bits */ 76, 13075 /* flags */ 0, 13076 }, 13077 #endif /* chips */ 13078 13079 #if defined(BCM_56524_A0) || defined(BCM_56624_A0) || \ 13080 defined(BCM_56634_A0) || defined(BCM_56634_B0) 13081 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDSfmt */ 13082 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13083 /* nFields */ 7, 13084 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13085 /* bits */ 56, 13086 /* flags */ 0, 13087 }, 13088 #endif /* chips */ 13089 13090 #if defined(BCM_56340_A0) 13091 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56340_A0fmt */ 13092 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13093 /* nFields */ 7, 13094 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDS_BCM56640_A0fmt_fields, 13095 /* bits */ 56, 13096 /* flags */ 0, 13097 }, 13098 #endif /* chips */ 13099 13100 #if defined(BCM_56524_B0) 13101 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56524_B0fmt */ 13102 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13103 /* nFields */ 7, 13104 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13105 /* bits */ 56, 13106 /* flags */ 0, 13107 }, 13108 #endif /* chips */ 13109 13110 #if defined(BCM_56624_B0) 13111 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56624_B0fmt */ 13112 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13113 /* nFields */ 7, 13114 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13115 /* bits */ 56, 13116 /* flags */ 0, 13117 }, 13118 #endif /* chips */ 13119 13120 #if defined(BCM_56640_A0) 13121 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56640_A0fmt */ 13122 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13123 /* nFields */ 7, 13124 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDS_BCM56640_A0fmt_fields, 13125 /* bits */ 56, 13126 /* flags */ 0, 13127 }, 13128 #endif /* chips */ 13129 13130 #if defined(BCM_56680_A0) 13131 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56680_A0fmt */ 13132 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13133 /* nFields */ 7, 13134 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13135 /* bits */ 56, 13136 /* flags */ 0, 13137 }, 13138 #endif /* chips */ 13139 13140 #if defined(BCM_56680_B0) 13141 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56680_B0fmt */ 13142 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13143 /* nFields */ 7, 13144 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13145 /* bits */ 56, 13146 /* flags */ 0, 13147 }, 13148 #endif /* chips */ 13149 13150 #if defined(BCM_56685_A0) 13151 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56685_A0fmt */ 13152 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13153 /* nFields */ 7, 13154 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13155 /* bits */ 56, 13156 /* flags */ 0, 13157 }, 13158 #endif /* chips */ 13159 13160 #if defined(BCM_56685_B0) 13161 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56685_B0fmt */ 13162 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13163 /* nFields */ 7, 13164 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13165 /* bits */ 56, 13166 /* flags */ 0, 13167 }, 13168 #endif /* chips */ 13169 13170 #if defined(BCM_56725_A0) 13171 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56725_A0fmt */ 13172 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13173 /* nFields */ 7, 13174 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13175 /* bits */ 56, 13176 /* flags */ 0, 13177 }, 13178 #endif /* chips */ 13179 13180 #if defined(BCM_56820_A0) 13181 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56820_A0fmt */ 13182 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13183 /* nFields */ 7, 13184 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13185 /* bits */ 56, 13186 /* flags */ 0, 13187 }, 13188 #endif /* chips */ 13189 13190 #if defined(BCM_56840_A0) 13191 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56840_A0fmt */ 13192 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13193 /* nFields */ 7, 13194 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13195 /* bits */ 56, 13196 /* flags */ 0, 13197 }, 13198 #endif /* chips */ 13199 13200 #if defined(BCM_56840_B0) 13201 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM56840_B0fmt */ 13202 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13203 /* nFields */ 7, 13204 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDSfmt_fields, 13205 /* bits */ 56, 13206 /* flags */ 0, 13207 }, 13208 #endif /* chips */ 13209 13210 #if defined(BCM_88732_A0) 13211 { /* SOC_FORMAT_INT_MTRO_PKT_METER_RF_FIELDS_BCM88732_A0fmt */ 13212 /* format MTRO_PKT_METER_RF_FIELDSfmt */ 13213 /* nFields */ 10, 13214 /* *fields */ soc_MTRO_PKT_METER_RF_FIELDS_BCM88732_A0fmt_fields, 13215 /* bits */ 62, 13216 /* flags */ 0, 13217 }, 13218 #endif /* chips */ 13219 13220 #if defined(BCM_56800_A0) 13221 { /* SOC_FORMAT_INT_MTRO_RF_FIELDSfmt */ 13222 /* format MTRO_RF_FIELDSfmt */ 13223 /* nFields */ 15, 13224 /* *fields */ soc_MTRO_RF_FIELDSfmt_fields, 13225 /* bits */ 110, 13226 /* flags */ 0, 13227 }, 13228 #endif /* chips */ 13229 13230 #if defined(BCM_56334_A0) 13231 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56334_A0fmt */ 13232 /* format MTRO_RF_FIELDSfmt */ 13233 /* nFields */ 16, 13234 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13235 /* bits */ 128, 13236 /* flags */ 0, 13237 }, 13238 #endif /* chips */ 13239 13240 #if defined(BCM_56334_B0) 13241 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56334_B0fmt */ 13242 /* format MTRO_RF_FIELDSfmt */ 13243 /* nFields */ 16, 13244 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13245 /* bits */ 128, 13246 /* flags */ 0, 13247 }, 13248 #endif /* chips */ 13249 13250 #if defined(BCM_56340_A0) 13251 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56340_A0fmt */ 13252 /* format MTRO_RF_FIELDSfmt */ 13253 /* nFields */ 6, 13254 /* *fields */ soc_MTRO_RF_FIELDS_BCM56640_A0fmt_fields, 13255 /* bits */ 60, 13256 /* flags */ 0, 13257 }, 13258 #endif /* chips */ 13259 13260 #if defined(BCM_56370_A0) 13261 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56370_A0fmt */ 13262 /* format MTRO_RF_FIELDSfmt */ 13263 /* nFields */ 7, 13264 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13265 /* bits */ 68, 13266 /* flags */ 0, 13267 }, 13268 #endif /* chips */ 13269 13270 #if defined(BCM_56524_A0) 13271 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56524_A0fmt */ 13272 /* format MTRO_RF_FIELDSfmt */ 13273 /* nFields */ 16, 13274 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13275 /* bits */ 128, 13276 /* flags */ 0, 13277 }, 13278 #endif /* chips */ 13279 13280 #if defined(BCM_56524_B0) 13281 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56524_B0fmt */ 13282 /* format MTRO_RF_FIELDSfmt */ 13283 /* nFields */ 16, 13284 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13285 /* bits */ 128, 13286 /* flags */ 0, 13287 }, 13288 #endif /* chips */ 13289 13290 #if defined(BCM_56560_A0) 13291 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56560_A0fmt */ 13292 /* format MTRO_RF_FIELDSfmt */ 13293 /* nFields */ 7, 13294 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13295 /* bits */ 68, 13296 /* flags */ 0, 13297 }, 13298 #endif /* chips */ 13299 13300 #if defined(BCM_56560_B0) 13301 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56560_B0fmt */ 13302 /* format MTRO_RF_FIELDSfmt */ 13303 /* nFields */ 7, 13304 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13305 /* bits */ 68, 13306 /* flags */ 0, 13307 }, 13308 #endif /* chips */ 13309 13310 #if defined(BCM_56624_A0) 13311 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56624_A0fmt */ 13312 /* format MTRO_RF_FIELDSfmt */ 13313 /* nFields */ 16, 13314 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13315 /* bits */ 128, 13316 /* flags */ 0, 13317 }, 13318 #endif /* chips */ 13319 13320 #if defined(BCM_56624_B0) 13321 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56624_B0fmt */ 13322 /* format MTRO_RF_FIELDSfmt */ 13323 /* nFields */ 16, 13324 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13325 /* bits */ 128, 13326 /* flags */ 0, 13327 }, 13328 #endif /* chips */ 13329 13330 #if defined(BCM_56634_A0) 13331 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56634_A0fmt */ 13332 /* format MTRO_RF_FIELDSfmt */ 13333 /* nFields */ 16, 13334 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13335 /* bits */ 128, 13336 /* flags */ 0, 13337 }, 13338 #endif /* chips */ 13339 13340 #if defined(BCM_56634_B0) 13341 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56634_B0fmt */ 13342 /* format MTRO_RF_FIELDSfmt */ 13343 /* nFields */ 16, 13344 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13345 /* bits */ 128, 13346 /* flags */ 0, 13347 }, 13348 #endif /* chips */ 13349 13350 #if defined(BCM_56640_A0) 13351 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56640_A0fmt */ 13352 /* format MTRO_RF_FIELDSfmt */ 13353 /* nFields */ 6, 13354 /* *fields */ soc_MTRO_RF_FIELDS_BCM56640_A0fmt_fields, 13355 /* bits */ 60, 13356 /* flags */ 0, 13357 }, 13358 #endif /* chips */ 13359 13360 #if defined(BCM_56670_A0) 13361 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56670_A0fmt */ 13362 /* format MTRO_RF_FIELDSfmt */ 13363 /* nFields */ 7, 13364 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13365 /* bits */ 68, 13366 /* flags */ 0, 13367 }, 13368 #endif /* chips */ 13369 13370 #if defined(BCM_56670_B0) 13371 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56670_B0fmt */ 13372 /* format MTRO_RF_FIELDSfmt */ 13373 /* nFields */ 7, 13374 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13375 /* bits */ 68, 13376 /* flags */ 0, 13377 }, 13378 #endif /* chips */ 13379 13380 #if defined(BCM_56680_A0) 13381 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56680_A0fmt */ 13382 /* format MTRO_RF_FIELDSfmt */ 13383 /* nFields */ 16, 13384 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13385 /* bits */ 128, 13386 /* flags */ 0, 13387 }, 13388 #endif /* chips */ 13389 13390 #if defined(BCM_56680_B0) 13391 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56680_B0fmt */ 13392 /* format MTRO_RF_FIELDSfmt */ 13393 /* nFields */ 16, 13394 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13395 /* bits */ 128, 13396 /* flags */ 0, 13397 }, 13398 #endif /* chips */ 13399 13400 #if defined(BCM_56685_A0) 13401 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56685_A0fmt */ 13402 /* format MTRO_RF_FIELDSfmt */ 13403 /* nFields */ 16, 13404 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13405 /* bits */ 128, 13406 /* flags */ 0, 13407 }, 13408 #endif /* chips */ 13409 13410 #if defined(BCM_56685_B0) 13411 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56685_B0fmt */ 13412 /* format MTRO_RF_FIELDSfmt */ 13413 /* nFields */ 16, 13414 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13415 /* bits */ 128, 13416 /* flags */ 0, 13417 }, 13418 #endif /* chips */ 13419 13420 #if defined(BCM_56770_A0) 13421 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56770_A0fmt */ 13422 /* format MTRO_RF_FIELDSfmt */ 13423 /* nFields */ 7, 13424 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13425 /* bits */ 68, 13426 /* flags */ 0, 13427 }, 13428 #endif /* chips */ 13429 13430 #if defined(BCM_56840_A0) 13431 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56840_A0fmt */ 13432 /* format MTRO_RF_FIELDSfmt */ 13433 /* nFields */ 16, 13434 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13435 /* bits */ 128, 13436 /* flags */ 0, 13437 }, 13438 #endif /* chips */ 13439 13440 #if defined(BCM_56840_B0) 13441 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56840_B0fmt */ 13442 /* format MTRO_RF_FIELDSfmt */ 13443 /* nFields */ 16, 13444 /* *fields */ soc_MTRO_RF_FIELDS_BCM56624_A0fmt_fields, 13445 /* bits */ 128, 13446 /* flags */ 0, 13447 }, 13448 #endif /* chips */ 13449 13450 #if defined(BCM_56850_A0) 13451 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56850_A0fmt */ 13452 /* format MTRO_RF_FIELDSfmt */ 13453 /* nFields */ 8, 13454 /* *fields */ soc_MTRO_RF_FIELDS_BCM56850_A0fmt_fields, 13455 /* bits */ 64, 13456 /* flags */ 0, 13457 }, 13458 #endif /* chips */ 13459 13460 #if defined(BCM_56860_A0) 13461 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56860_A0fmt */ 13462 /* format MTRO_RF_FIELDSfmt */ 13463 /* nFields */ 7, 13464 /* *fields */ soc_MTRO_RF_FIELDS_BCM56860_A0fmt_fields, 13465 /* bits */ 68, 13466 /* flags */ 0, 13467 }, 13468 #endif /* chips */ 13469 13470 #if defined(BCM_56870_A0) 13471 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56870_A0fmt */ 13472 /* format MTRO_RF_FIELDSfmt */ 13473 /* nFields */ 7, 13474 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13475 /* bits */ 68, 13476 /* flags */ 0, 13477 }, 13478 #endif /* chips */ 13479 13480 #if defined(BCM_56960_A0) 13481 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56960_A0fmt */ 13482 /* format MTRO_RF_FIELDSfmt */ 13483 /* nFields */ 7, 13484 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13485 /* bits */ 68, 13486 /* flags */ 0, 13487 }, 13488 #endif /* chips */ 13489 13490 #if defined(BCM_56965_A0) 13491 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56965_A0fmt */ 13492 /* format MTRO_RF_FIELDSfmt */ 13493 /* nFields */ 7, 13494 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13495 /* bits */ 68, 13496 /* flags */ 0, 13497 }, 13498 #endif /* chips */ 13499 13500 #if defined(BCM_56970_A0) 13501 { /* SOC_FORMAT_INT_MTRO_RF_FIELDS_BCM56970_A0fmt */ 13502 /* format MTRO_RF_FIELDSfmt */ 13503 /* nFields */ 7, 13504 /* *fields */ soc_MTRO_RF_FIELDS_BCM56960_A0fmt_fields, 13505 /* bits */ 68, 13506 /* flags */ 0, 13507 }, 13508 #endif /* chips */ 13509 13510 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 13511 defined(BCM_56870_A0) 13512 { /* SOC_FORMAT_INT_MTU_CONTROLS_ACTION_SETfmt */ 13513 /* format MTU_CONTROLS_ACTION_SETfmt */ 13514 /* nFields */ 2, 13515 /* *fields */ soc_MTU_CONTROLS_ACTION_SETfmt_fields, 13516 /* bits */ 15, 13517 /* flags */ 0, 13518 }, 13519 #endif /* chips */ 13520 13521 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 13522 defined(BCM_56870_A0) || defined(BCM_56980_A0) || \ 13523 defined(BCM_56980_B0) 13524 { /* SOC_FORMAT_INT_MXE_TABLE_KEYfmt */ 13525 /* format MXE_TABLE_KEYfmt */ 13526 /* nFields */ 4, 13527 /* *fields */ soc_MXE_TABLE_KEYfmt_fields, 13528 /* bits */ 51, 13529 /* flags */ 0, 13530 }, 13531 #endif /* chips */ 13532 13533 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 13534 { /* SOC_FORMAT_INT_MY_STATION_DATA_FORMATfmt */ 13535 /* format MY_STATION_DATA_FORMATfmt */ 13536 /* nFields */ 12, 13537 /* *fields */ soc_MY_STATION_DATA_FORMATfmt_fields, 13538 /* bits */ 13, 13539 /* flags */ 0, 13540 }, 13541 #endif /* chips */ 13542 13543 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 13544 { /* SOC_FORMAT_INT_MY_STATION_TCAM_FORMATfmt */ 13545 /* format MY_STATION_TCAM_FORMATfmt */ 13546 /* nFields */ 21, 13547 /* *fields */ soc_MY_STATION_TCAM_FORMATfmt_fields, 13548 /* bits */ 169, 13549 /* flags */ 0, 13550 }, 13551 #endif /* chips */ 13552 13553 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 13554 defined(BCM_56870_A0) 13555 { /* SOC_FORMAT_INT_MY_STATION_TCAM_VAL_DOPfmt */ 13556 /* format MY_STATION_TCAM_VAL_DOPfmt */ 13557 /* nFields */ 4, 13558 /* *fields */ soc_MY_STATION_TCAM_VAL_DOPfmt_fields, 13559 /* bits */ 32, 13560 /* flags */ 0, 13561 }, 13562 #endif /* chips */ 13563