allformats_l.i (185725B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_l.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 16 { /* SOC_FORMAT_INT_L2_BITMAP_DOPfmt */ 17 /* format L2_BITMAP_DOPfmt */ 18 /* nFields */ 3, 19 /* *fields */ soc_L2_BITMAP_DOPfmt_fields, 20 /* bits */ 160, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_56370_A0) 26 { /* SOC_FORMAT_INT_L2_BITMAP_DOP_BCM56370_A0fmt */ 27 /* format L2_BITMAP_DOPfmt */ 28 /* nFields */ 3, 29 /* *fields */ soc_L2_BITMAP_DOP_BCM56370_A0fmt_fields, 30 /* bits */ 96, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 36 defined(BCM_56870_A0) 37 { /* SOC_FORMAT_INT_L2_EDIT_CONTROLS_ACTION_SETfmt */ 38 /* format L2_EDIT_CONTROLS_ACTION_SETfmt */ 39 /* nFields */ 5, 40 /* *fields */ soc_L2_EDIT_CONTROLS_ACTION_SETfmt_fields, 41 /* bits */ 5, 42 /* flags */ 0, 43 }, 44 #endif /* chips */ 45 46 #if defined(BCM_56640_A0) 47 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATAfmt */ 48 /* format L2_ENTRY_1_DATAfmt */ 49 /* nFields */ 106, 50 /* *fields */ soc_L2_ENTRY_1_DATAfmt_fields, 51 /* bits */ 58, 52 /* flags */ 0, 53 }, 54 #endif /* chips */ 55 56 #if defined(BCM_56260_A0) 57 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56260_A0fmt */ 58 /* format L2_ENTRY_1_DATAfmt */ 59 /* nFields */ 118, 60 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56960_A0fmt_fields, 61 /* bits */ 54, 62 /* flags */ 0, 63 }, 64 #endif /* chips */ 65 66 #if defined(BCM_56260_B0) 67 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56260_B0fmt */ 68 /* format L2_ENTRY_1_DATAfmt */ 69 /* nFields */ 118, 70 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56960_A0fmt_fields, 71 /* bits */ 54, 72 /* flags */ 0, 73 }, 74 #endif /* chips */ 75 76 #if defined(BCM_56270_A0) 77 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56270_A0fmt */ 78 /* format L2_ENTRY_1_DATAfmt */ 79 /* nFields */ 118, 80 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56960_A0fmt_fields, 81 /* bits */ 54, 82 /* flags */ 0, 83 }, 84 #endif /* chips */ 85 86 #if defined(BCM_56340_A0) 87 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56340_A0fmt */ 88 /* format L2_ENTRY_1_DATAfmt */ 89 /* nFields */ 107, 90 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56340_A0fmt_fields, 91 /* bits */ 58, 92 /* flags */ 0, 93 }, 94 #endif /* chips */ 95 96 #if defined(BCM_56560_A0) 97 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56560_A0fmt */ 98 /* format L2_ENTRY_1_DATAfmt */ 99 /* nFields */ 139, 100 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56560_A0fmt_fields, 101 /* bits */ 52, 102 /* flags */ 0, 103 }, 104 #endif /* chips */ 105 106 #if defined(BCM_56560_B0) 107 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56560_B0fmt */ 108 /* format L2_ENTRY_1_DATAfmt */ 109 /* nFields */ 139, 110 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56560_B0fmt_fields, 111 /* bits */ 52, 112 /* flags */ 0, 113 }, 114 #endif /* chips */ 115 116 #if defined(BCM_56670_A0) 117 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56670_A0fmt */ 118 /* format L2_ENTRY_1_DATAfmt */ 119 /* nFields */ 143, 120 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56670_A0fmt_fields, 121 /* bits */ 52, 122 /* flags */ 0, 123 }, 124 #endif /* chips */ 125 126 #if defined(BCM_56670_B0) 127 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56670_B0fmt */ 128 /* format L2_ENTRY_1_DATAfmt */ 129 /* nFields */ 143, 130 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56670_A0fmt_fields, 131 /* bits */ 52, 132 /* flags */ 0, 133 }, 134 #endif /* chips */ 135 136 #if defined(BCM_56850_A0) 137 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56850_A0fmt */ 138 /* format L2_ENTRY_1_DATAfmt */ 139 /* nFields */ 128, 140 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56850_A0fmt_fields, 141 /* bits */ 52, 142 /* flags */ 0, 143 }, 144 #endif /* chips */ 145 146 #if defined(BCM_56860_A0) 147 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56860_A0fmt */ 148 /* format L2_ENTRY_1_DATAfmt */ 149 /* nFields */ 133, 150 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56860_A0fmt_fields, 151 /* bits */ 52, 152 /* flags */ 0, 153 }, 154 #endif /* chips */ 155 156 #if defined(BCM_56960_A0) 157 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56960_A0fmt */ 158 /* format L2_ENTRY_1_DATAfmt */ 159 /* nFields */ 118, 160 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56960_A0fmt_fields, 161 /* bits */ 54, 162 /* flags */ 0, 163 }, 164 #endif /* chips */ 165 166 #if defined(BCM_56965_A0) 167 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56965_A0fmt */ 168 /* format L2_ENTRY_1_DATAfmt */ 169 /* nFields */ 118, 170 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56960_A0fmt_fields, 171 /* bits */ 54, 172 /* flags */ 0, 173 }, 174 #endif /* chips */ 175 176 #if defined(BCM_56970_A0) 177 { /* SOC_FORMAT_INT_L2_ENTRY_1_DATA_BCM56970_A0fmt */ 178 /* format L2_ENTRY_1_DATAfmt */ 179 /* nFields */ 118, 180 /* *fields */ soc_L2_ENTRY_1_DATA_BCM56960_A0fmt_fields, 181 /* bits */ 54, 182 /* flags */ 0, 183 }, 184 #endif /* chips */ 185 186 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 187 { /* SOC_FORMAT_INT_L2_ENTRY_2_DATAfmt */ 188 /* format L2_ENTRY_2_DATAfmt */ 189 /* nFields */ 29, 190 /* *fields */ soc_L2_ENTRY_2_DATAfmt_fields, 191 /* bits */ 62, 192 /* flags */ 0, 193 }, 194 #endif /* chips */ 195 196 #if defined(BCM_56640_A0) 197 { /* SOC_FORMAT_INT_L2_ENTRY_KEYfmt */ 198 /* format L2_ENTRY_KEYfmt */ 199 /* nFields */ 40, 200 /* *fields */ soc_L2_ENTRY_KEYfmt_fields, 201 /* bits */ 68, 202 /* flags */ 0, 203 }, 204 #endif /* chips */ 205 206 #if defined(BCM_56260_A0) 207 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56260_A0fmt */ 208 /* format L2_ENTRY_KEYfmt */ 209 /* nFields */ 35, 210 /* *fields */ soc_L2_ENTRY_KEY_BCM56960_A0fmt_fields, 211 /* bits */ 68, 212 /* flags */ 0, 213 }, 214 #endif /* chips */ 215 216 #if defined(BCM_56260_B0) 217 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56260_B0fmt */ 218 /* format L2_ENTRY_KEYfmt */ 219 /* nFields */ 35, 220 /* *fields */ soc_L2_ENTRY_KEY_BCM56960_A0fmt_fields, 221 /* bits */ 68, 222 /* flags */ 0, 223 }, 224 #endif /* chips */ 225 226 #if defined(BCM_56270_A0) 227 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56270_A0fmt */ 228 /* format L2_ENTRY_KEYfmt */ 229 /* nFields */ 35, 230 /* *fields */ soc_L2_ENTRY_KEY_BCM56960_A0fmt_fields, 231 /* bits */ 68, 232 /* flags */ 0, 233 }, 234 #endif /* chips */ 235 236 #if defined(BCM_56340_A0) 237 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56340_A0fmt */ 238 /* format L2_ENTRY_KEYfmt */ 239 /* nFields */ 41, 240 /* *fields */ soc_L2_ENTRY_KEY_BCM56340_A0fmt_fields, 241 /* bits */ 68, 242 /* flags */ 0, 243 }, 244 #endif /* chips */ 245 246 #if defined(BCM_56560_A0) 247 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56560_A0fmt */ 248 /* format L2_ENTRY_KEYfmt */ 249 /* nFields */ 47, 250 /* *fields */ soc_L2_ENTRY_KEY_BCM56560_A0fmt_fields, 251 /* bits */ 68, 252 /* flags */ 0, 253 }, 254 #endif /* chips */ 255 256 #if defined(BCM_56560_B0) 257 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56560_B0fmt */ 258 /* format L2_ENTRY_KEYfmt */ 259 /* nFields */ 47, 260 /* *fields */ soc_L2_ENTRY_KEY_BCM56560_A0fmt_fields, 261 /* bits */ 68, 262 /* flags */ 0, 263 }, 264 #endif /* chips */ 265 266 #if defined(BCM_56670_A0) 267 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56670_A0fmt */ 268 /* format L2_ENTRY_KEYfmt */ 269 /* nFields */ 47, 270 /* *fields */ soc_L2_ENTRY_KEY_BCM56670_A0fmt_fields, 271 /* bits */ 68, 272 /* flags */ 0, 273 }, 274 #endif /* chips */ 275 276 #if defined(BCM_56670_B0) 277 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56670_B0fmt */ 278 /* format L2_ENTRY_KEYfmt */ 279 /* nFields */ 47, 280 /* *fields */ soc_L2_ENTRY_KEY_BCM56670_A0fmt_fields, 281 /* bits */ 68, 282 /* flags */ 0, 283 }, 284 #endif /* chips */ 285 286 #if defined(BCM_56850_A0) 287 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56850_A0fmt */ 288 /* format L2_ENTRY_KEYfmt */ 289 /* nFields */ 47, 290 /* *fields */ soc_L2_ENTRY_KEY_BCM56850_A0fmt_fields, 291 /* bits */ 68, 292 /* flags */ 0, 293 }, 294 #endif /* chips */ 295 296 #if defined(BCM_56860_A0) 297 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56860_A0fmt */ 298 /* format L2_ENTRY_KEYfmt */ 299 /* nFields */ 47, 300 /* *fields */ soc_L2_ENTRY_KEY_BCM56850_A0fmt_fields, 301 /* bits */ 68, 302 /* flags */ 0, 303 }, 304 #endif /* chips */ 305 306 #if defined(BCM_56960_A0) 307 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56960_A0fmt */ 308 /* format L2_ENTRY_KEYfmt */ 309 /* nFields */ 35, 310 /* *fields */ soc_L2_ENTRY_KEY_BCM56960_A0fmt_fields, 311 /* bits */ 68, 312 /* flags */ 0, 313 }, 314 #endif /* chips */ 315 316 #if defined(BCM_56965_A0) 317 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56965_A0fmt */ 318 /* format L2_ENTRY_KEYfmt */ 319 /* nFields */ 35, 320 /* *fields */ soc_L2_ENTRY_KEY_BCM56960_A0fmt_fields, 321 /* bits */ 68, 322 /* flags */ 0, 323 }, 324 #endif /* chips */ 325 326 #if defined(BCM_56970_A0) 327 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_BCM56970_A0fmt */ 328 /* format L2_ENTRY_KEYfmt */ 329 /* nFields */ 35, 330 /* *fields */ soc_L2_ENTRY_KEY_BCM56960_A0fmt_fields, 331 /* bits */ 68, 332 /* flags */ 0, 333 }, 334 #endif /* chips */ 335 336 #if defined(BCM_56142_A0) 337 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_TYPEfmt */ 338 /* format L2_ENTRY_KEY_TYPEfmt */ 339 /* nFields */ 18, 340 /* *fields */ soc_L2_ENTRY_KEY_TYPEfmt_fields, 341 /* bits */ 62, 342 /* flags */ 0, 343 }, 344 #endif /* chips */ 345 346 #if defined(BCM_53400_A0) 347 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_TYPE_BCM53400_A0fmt */ 348 /* format L2_ENTRY_KEY_TYPEfmt */ 349 /* nFields */ 29, 350 /* *fields */ soc_L2_ENTRY_KEY_TYPE_BCM53400_A0fmt_fields, 351 /* bits */ 63, 352 /* flags */ 0, 353 }, 354 #endif /* chips */ 355 356 #if defined(BCM_53540_A0) 357 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_TYPE_BCM53540_A0fmt */ 358 /* format L2_ENTRY_KEY_TYPEfmt */ 359 /* nFields */ 29, 360 /* *fields */ soc_L2_ENTRY_KEY_TYPE_BCM53400_A0fmt_fields, 361 /* bits */ 63, 362 /* flags */ 0, 363 }, 364 #endif /* chips */ 365 366 #if defined(BCM_53570_A0) 367 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_TYPE_BCM53570_A0fmt */ 368 /* format L2_ENTRY_KEY_TYPEfmt */ 369 /* nFields */ 28, 370 /* *fields */ soc_L2_ENTRY_KEY_TYPE_BCM53570_A0fmt_fields, 371 /* bits */ 63, 372 /* flags */ 0, 373 }, 374 #endif /* chips */ 375 376 #if defined(BCM_53570_B0) 377 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_TYPE_BCM53570_B0fmt */ 378 /* format L2_ENTRY_KEY_TYPEfmt */ 379 /* nFields */ 28, 380 /* *fields */ soc_L2_ENTRY_KEY_TYPE_BCM53570_A0fmt_fields, 381 /* bits */ 63, 382 /* flags */ 0, 383 }, 384 #endif /* chips */ 385 386 #if defined(BCM_56150_A0) 387 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_TYPE_BCM56150_A0fmt */ 388 /* format L2_ENTRY_KEY_TYPEfmt */ 389 /* nFields */ 18, 390 /* *fields */ soc_L2_ENTRY_KEY_TYPE_BCM56150_A0fmt_fields, 391 /* bits */ 62, 392 /* flags */ 0, 393 }, 394 #endif /* chips */ 395 396 #if defined(BCM_56160_A0) 397 { /* SOC_FORMAT_INT_L2_ENTRY_KEY_TYPE_BCM56160_A0fmt */ 398 /* format L2_ENTRY_KEY_TYPEfmt */ 399 /* nFields */ 29, 400 /* *fields */ soc_L2_ENTRY_KEY_TYPE_BCM53400_A0fmt_fields, 401 /* bits */ 63, 402 /* flags */ 0, 403 }, 404 #endif /* chips */ 405 406 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 407 { /* SOC_FORMAT_INT_L2_FWD_TABLE_ATTRIBUTESfmt */ 408 /* format L2_FWD_TABLE_ATTRIBUTESfmt */ 409 /* nFields */ 28, 410 /* *fields */ soc_L2_FWD_TABLE_ATTRIBUTESfmt_fields, 411 /* bits */ 116, 412 /* flags */ 0, 413 }, 414 #endif /* chips */ 415 416 #if defined(BCM_56370_A0) 417 { /* SOC_FORMAT_INT_L2_FWD_TABLE_ATTRIBUTES_BCM56370_A0fmt */ 418 /* format L2_FWD_TABLE_ATTRIBUTESfmt */ 419 /* nFields */ 29, 420 /* *fields */ soc_L2_FWD_TABLE_ATTRIBUTES_BCM56370_A0fmt_fields, 421 /* bits */ 116, 422 /* flags */ 0, 423 }, 424 #endif /* chips */ 425 426 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 427 defined(BCM_56870_A0) 428 { /* SOC_FORMAT_INT_L2_GRE_HDRfmt */ 429 /* format L2_GRE_HDRfmt */ 430 /* nFields */ 10, 431 /* *fields */ soc_L2_GRE_HDRfmt_fields, 432 /* bits */ 64, 433 /* flags */ 0, 434 }, 435 #endif /* chips */ 436 437 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 438 defined(BCM_56870_A0) 439 { /* SOC_FORMAT_INT_L2_MEMBERSHIP_CONTROLS_ACTION_SETfmt */ 440 /* format L2_MEMBERSHIP_CONTROLS_ACTION_SETfmt */ 441 /* nFields */ 3, 442 /* *fields */ soc_L2_MEMBERSHIP_CONTROLS_ACTION_SETfmt_fields, 443 /* bits */ 9, 444 /* flags */ 0, 445 }, 446 #endif /* chips */ 447 448 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 449 { /* SOC_FORMAT_INT_L2_MGMT_TO_IARB_REQfmt */ 450 /* format L2_MGMT_TO_IARB_REQfmt */ 451 /* nFields */ 7, 452 /* *fields */ soc_L2_MGMT_TO_IARB_REQfmt_fields, 453 /* bits */ 136, 454 /* flags */ 0, 455 }, 456 #endif /* chips */ 457 458 #if defined(BCM_56370_A0) 459 { /* SOC_FORMAT_INT_L2_MGMT_TO_IARB_REQ_BCM56370_A0fmt */ 460 /* format L2_MGMT_TO_IARB_REQfmt */ 461 /* nFields */ 6, 462 /* *fields */ soc_L2_MGMT_TO_IARB_REQ_BCM56870_A0fmt_fields, 463 /* bits */ 141, 464 /* flags */ 0, 465 }, 466 #endif /* chips */ 467 468 #if defined(BCM_56770_A0) 469 { /* SOC_FORMAT_INT_L2_MGMT_TO_IARB_REQ_BCM56770_A0fmt */ 470 /* format L2_MGMT_TO_IARB_REQfmt */ 471 /* nFields */ 6, 472 /* *fields */ soc_L2_MGMT_TO_IARB_REQ_BCM56870_A0fmt_fields, 473 /* bits */ 141, 474 /* flags */ 0, 475 }, 476 #endif /* chips */ 477 478 #if defined(BCM_56870_A0) 479 { /* SOC_FORMAT_INT_L2_MGMT_TO_IARB_REQ_BCM56870_A0fmt */ 480 /* format L2_MGMT_TO_IARB_REQfmt */ 481 /* nFields */ 6, 482 /* *fields */ soc_L2_MGMT_TO_IARB_REQ_BCM56870_A0fmt_fields, 483 /* bits */ 141, 484 /* flags */ 0, 485 }, 486 #endif /* chips */ 487 488 #if defined(BCM_56970_A0) 489 { /* SOC_FORMAT_INT_L2_MGMT_TO_IARB_REQ_BCM56970_A0fmt */ 490 /* format L2_MGMT_TO_IARB_REQfmt */ 491 /* nFields */ 7, 492 /* *fields */ soc_L2_MGMT_TO_IARB_REQ_BCM56970_A0fmt_fields, 493 /* bits */ 137, 494 /* flags */ 0, 495 }, 496 #endif /* chips */ 497 498 #if defined(BCM_56980_A0) 499 { /* SOC_FORMAT_INT_L2_MGMT_TO_IARB_REQ_BCM56980_A0fmt */ 500 /* format L2_MGMT_TO_IARB_REQfmt */ 501 /* nFields */ 5, 502 /* *fields */ soc_L2_MGMT_TO_IARB_REQ_BCM56980_A0fmt_fields, 503 /* bits */ 141, 504 /* flags */ 0, 505 }, 506 #endif /* chips */ 507 508 #if defined(BCM_56980_B0) 509 { /* SOC_FORMAT_INT_L2_MGMT_TO_IARB_REQ_BCM56980_B0fmt */ 510 /* format L2_MGMT_TO_IARB_REQfmt */ 511 /* nFields */ 5, 512 /* *fields */ soc_L2_MGMT_TO_IARB_REQ_BCM56980_A0fmt_fields, 513 /* bits */ 141, 514 /* flags */ 0, 515 }, 516 #endif /* chips */ 517 518 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 519 defined(BCM_56870_A0) 520 { /* SOC_FORMAT_INT_L2_TAG_INHERIT_ACTION_FORMATfmt */ 521 /* format L2_TAG_INHERIT_ACTION_FORMATfmt */ 522 /* nFields */ 6, 523 /* *fields */ soc_L2_TAG_INHERIT_ACTION_FORMATfmt_fields, 524 /* bits */ 48, 525 /* flags */ 0, 526 }, 527 #endif /* chips */ 528 529 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 530 { /* SOC_FORMAT_INT_L2_USER_ENTRY_DATA_FORMATfmt */ 531 /* format L2_USER_ENTRY_DATA_FORMATfmt */ 532 /* nFields */ 16, 533 /* *fields */ soc_L2_USER_ENTRY_DATA_FORMATfmt_fields, 534 /* bits */ 36, 535 /* flags */ 0, 536 }, 537 #endif /* chips */ 538 539 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 540 defined(BCM_56870_A0) 541 { /* SOC_FORMAT_INT_L2_USER_ENTRY_DOPfmt */ 542 /* format L2_USER_ENTRY_DOPfmt */ 543 /* nFields */ 4, 544 /* *fields */ soc_L2_USER_ENTRY_DOPfmt_fields, 545 /* bits */ 32, 546 /* flags */ 0, 547 }, 548 #endif /* chips */ 549 550 #if defined(BCM_56142_A0) 551 { /* SOC_FORMAT_INT_L2_USER_ENTRY_KEY_TYPEfmt */ 552 /* format L2_USER_ENTRY_KEY_TYPEfmt */ 553 /* nFields */ 9, 554 /* *fields */ soc_L2_USER_ENTRY_KEY_TYPEfmt_fields, 555 /* bits */ 61, 556 /* flags */ 0, 557 }, 558 #endif /* chips */ 559 560 #if defined(BCM_53400_A0) 561 { /* SOC_FORMAT_INT_L2_USER_ENTRY_KEY_TYPE_BCM53400_A0fmt */ 562 /* format L2_USER_ENTRY_KEY_TYPEfmt */ 563 /* nFields */ 11, 564 /* *fields */ soc_L2_USER_ENTRY_KEY_TYPE_BCM53400_A0fmt_fields, 565 /* bits */ 69, 566 /* flags */ 0, 567 }, 568 #endif /* chips */ 569 570 #if defined(BCM_53540_A0) 571 { /* SOC_FORMAT_INT_L2_USER_ENTRY_KEY_TYPE_BCM53540_A0fmt */ 572 /* format L2_USER_ENTRY_KEY_TYPEfmt */ 573 /* nFields */ 11, 574 /* *fields */ soc_L2_USER_ENTRY_KEY_TYPE_BCM53400_A0fmt_fields, 575 /* bits */ 69, 576 /* flags */ 0, 577 }, 578 #endif /* chips */ 579 580 #if defined(BCM_53570_A0) 581 { /* SOC_FORMAT_INT_L2_USER_ENTRY_KEY_TYPE_BCM53570_A0fmt */ 582 /* format L2_USER_ENTRY_KEY_TYPEfmt */ 583 /* nFields */ 10, 584 /* *fields */ soc_L2_USER_ENTRY_KEY_TYPE_BCM53570_A0fmt_fields, 585 /* bits */ 69, 586 /* flags */ 0, 587 }, 588 #endif /* chips */ 589 590 #if defined(BCM_53570_B0) 591 { /* SOC_FORMAT_INT_L2_USER_ENTRY_KEY_TYPE_BCM53570_B0fmt */ 592 /* format L2_USER_ENTRY_KEY_TYPEfmt */ 593 /* nFields */ 10, 594 /* *fields */ soc_L2_USER_ENTRY_KEY_TYPE_BCM53570_A0fmt_fields, 595 /* bits */ 69, 596 /* flags */ 0, 597 }, 598 #endif /* chips */ 599 600 #if defined(BCM_56150_A0) 601 { /* SOC_FORMAT_INT_L2_USER_ENTRY_KEY_TYPE_BCM56150_A0fmt */ 602 /* format L2_USER_ENTRY_KEY_TYPEfmt */ 603 /* nFields */ 11, 604 /* *fields */ soc_L2_USER_ENTRY_KEY_TYPE_BCM56150_A0fmt_fields, 605 /* bits */ 69, 606 /* flags */ 0, 607 }, 608 #endif /* chips */ 609 610 #if defined(BCM_56160_A0) 611 { /* SOC_FORMAT_INT_L2_USER_ENTRY_KEY_TYPE_BCM56160_A0fmt */ 612 /* format L2_USER_ENTRY_KEY_TYPEfmt */ 613 /* nFields */ 11, 614 /* *fields */ soc_L2_USER_ENTRY_KEY_TYPE_BCM53400_A0fmt_fields, 615 /* bits */ 69, 616 /* flags */ 0, 617 }, 618 #endif /* chips */ 619 620 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 621 { /* SOC_FORMAT_INT_L2_USER_ENTRY_TCAM_FORMATfmt */ 622 /* format L2_USER_ENTRY_TCAM_FORMATfmt */ 623 /* nFields */ 12, 624 /* *fields */ soc_L2_USER_ENTRY_TCAM_FORMATfmt_fields, 625 /* bits */ 169, 626 /* flags */ 0, 627 }, 628 #endif /* chips */ 629 630 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 631 defined(BCM_56870_A0) 632 { /* SOC_FORMAT_INT_L3MC_MAC_DA_UPDATE_ACTION_SETfmt */ 633 /* format L3MC_MAC_DA_UPDATE_ACTION_SETfmt */ 634 /* nFields */ 1, 635 /* *fields */ soc_L3MC_MAC_DA_UPDATE_ACTION_SETfmt_fields, 636 /* bits */ 1, 637 /* flags */ 0, 638 }, 639 #endif /* chips */ 640 641 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 642 { /* SOC_FORMAT_INT_L3_BITMAP_DOPfmt */ 643 /* format L3_BITMAP_DOPfmt */ 644 /* nFields */ 3, 645 /* *fields */ soc_L3_BITMAP_DOPfmt_fields, 646 /* bits */ 160, 647 /* flags */ 0, 648 }, 649 #endif /* chips */ 650 651 #if defined(BCM_56370_A0) 652 { /* SOC_FORMAT_INT_L3_BITMAP_DOP_BCM56370_A0fmt */ 653 /* format L3_BITMAP_DOPfmt */ 654 /* nFields */ 3, 655 /* *fields */ soc_L3_BITMAP_DOP_BCM56370_A0fmt_fields, 656 /* bits */ 96, 657 /* flags */ 0, 658 }, 659 #endif /* chips */ 660 661 #if defined(BCM_56860_A0) 662 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 663 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 664 /* nFields */ 5, 665 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt_fields, 666 /* bits */ 30, 667 /* flags */ 0, 668 }, 669 #endif /* chips */ 670 671 #if defined(BCM_56370_A0) 672 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56370_A0fmt */ 673 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 674 /* nFields */ 6, 675 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 676 /* bits */ 30, 677 /* flags */ 0, 678 }, 679 #endif /* chips */ 680 681 #if defined(BCM_56560_A0) 682 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt */ 683 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 684 /* nFields */ 5, 685 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 686 /* bits */ 30, 687 /* flags */ 0, 688 }, 689 #endif /* chips */ 690 691 #if defined(BCM_56560_B0) 692 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_B0fmt */ 693 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 694 /* nFields */ 5, 695 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 696 /* bits */ 30, 697 /* flags */ 0, 698 }, 699 #endif /* chips */ 700 701 #if defined(BCM_56670_A0) 702 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56670_A0fmt */ 703 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 704 /* nFields */ 5, 705 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 706 /* bits */ 30, 707 /* flags */ 0, 708 }, 709 #endif /* chips */ 710 711 #if defined(BCM_56670_B0) 712 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56670_B0fmt */ 713 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 714 /* nFields */ 5, 715 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 716 /* bits */ 30, 717 /* flags */ 0, 718 }, 719 #endif /* chips */ 720 721 #if defined(BCM_56770_A0) 722 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56770_A0fmt */ 723 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 724 /* nFields */ 6, 725 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 726 /* bits */ 30, 727 /* flags */ 0, 728 }, 729 #endif /* chips */ 730 731 #if defined(BCM_56870_A0) 732 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56870_A0fmt */ 733 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 734 /* nFields */ 6, 735 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 736 /* bits */ 30, 737 /* flags */ 0, 738 }, 739 #endif /* chips */ 740 741 #if defined(BCM_56970_A0) 742 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt */ 743 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 744 /* nFields */ 6, 745 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 746 /* bits */ 30, 747 /* flags */ 0, 748 }, 749 #endif /* chips */ 750 751 #if defined(BCM_56980_A0) 752 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56980_A0fmt */ 753 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 754 /* nFields */ 6, 755 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 756 /* bits */ 30, 757 /* flags */ 0, 758 }, 759 #endif /* chips */ 760 761 #if defined(BCM_56980_B0) 762 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56980_B0fmt */ 763 /* format L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt */ 764 /* nFields */ 6, 765 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 766 /* bits */ 30, 767 /* flags */ 0, 768 }, 769 #endif /* chips */ 770 771 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 772 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT1fmt */ 773 /* format L3_DEFIP_ALPM_PIVOT_FMT1fmt */ 774 /* nFields */ 3, 775 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT1fmt_fields, 776 /* bits */ 80, 777 /* flags */ 0, 778 }, 779 #endif /* chips */ 780 781 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 782 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT2fmt */ 783 /* format L3_DEFIP_ALPM_PIVOT_FMT2fmt */ 784 /* nFields */ 3, 785 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT2fmt_fields, 786 /* bits */ 96, 787 /* flags */ 0, 788 }, 789 #endif /* chips */ 790 791 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 792 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT3fmt */ 793 /* format L3_DEFIP_ALPM_PIVOT_FMT3fmt */ 794 /* nFields */ 3, 795 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3fmt_fields, 796 /* bits */ 120, 797 /* flags */ 0, 798 }, 799 #endif /* chips */ 800 801 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 802 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT4fmt */ 803 /* format L3_DEFIP_ALPM_PIVOT_FMT4fmt */ 804 /* nFields */ 3, 805 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT4fmt_fields, 806 /* bits */ 160, 807 /* flags */ 0, 808 }, 809 #endif /* chips */ 810 811 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 812 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT5fmt */ 813 /* format L3_DEFIP_ALPM_PIVOT_FMT5fmt */ 814 /* nFields */ 4, 815 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT5fmt_fields, 816 /* bits */ 208, 817 /* flags */ 0, 818 }, 819 #endif /* chips */ 820 821 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 822 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT6fmt */ 823 /* format L3_DEFIP_ALPM_PIVOT_FMT6fmt */ 824 /* nFields */ 3, 825 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT6fmt_fields, 826 /* bits */ 120, 827 /* flags */ 0, 828 }, 829 #endif /* chips */ 830 831 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 832 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT7fmt */ 833 /* format L3_DEFIP_ALPM_PIVOT_FMT7fmt */ 834 /* nFields */ 3, 835 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT7fmt_fields, 836 /* bits */ 160, 837 /* flags */ 0, 838 }, 839 #endif /* chips */ 840 841 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 842 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT8fmt */ 843 /* format L3_DEFIP_ALPM_PIVOT_FMT8fmt */ 844 /* nFields */ 4, 845 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT8fmt_fields, 846 /* bits */ 232, 847 /* flags */ 0, 848 }, 849 #endif /* chips */ 850 851 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 852 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT1_FULLfmt */ 853 /* format L3_DEFIP_ALPM_PIVOT_FMT1_FULLfmt */ 854 /* nFields */ 6, 855 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT1_FULLfmt_fields, 856 /* bits */ 480, 857 /* flags */ 0, 858 }, 859 #endif /* chips */ 860 861 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 862 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT2_FULLfmt */ 863 /* format L3_DEFIP_ALPM_PIVOT_FMT2_FULLfmt */ 864 /* nFields */ 5, 865 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT2_FULLfmt_fields, 866 /* bits */ 480, 867 /* flags */ 0, 868 }, 869 #endif /* chips */ 870 871 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 872 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt */ 873 /* format L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt */ 874 /* nFields */ 4, 875 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt_fields, 876 /* bits */ 480, 877 /* flags */ 0, 878 }, 879 #endif /* chips */ 880 881 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 882 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT4_FULLfmt */ 883 /* format L3_DEFIP_ALPM_PIVOT_FMT4_FULLfmt */ 884 /* nFields */ 3, 885 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT4_FULLfmt_fields, 886 /* bits */ 480, 887 /* flags */ 0, 888 }, 889 #endif /* chips */ 890 891 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 892 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT5_FULLfmt */ 893 /* format L3_DEFIP_ALPM_PIVOT_FMT5_FULLfmt */ 894 /* nFields */ 3, 895 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT5_FULLfmt_fields, 896 /* bits */ 480, 897 /* flags */ 0, 898 }, 899 #endif /* chips */ 900 901 #if defined(BCM_56980_A0) 902 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT6_FULLfmt */ 903 /* format L3_DEFIP_ALPM_PIVOT_FMT6_FULLfmt */ 904 /* nFields */ 4, 905 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt_fields, 906 /* bits */ 480, 907 /* flags */ 0, 908 }, 909 #endif /* chips */ 910 911 #if defined(BCM_56980_B0) 912 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT6_FULL_BCM56980_B0fmt */ 913 /* format L3_DEFIP_ALPM_PIVOT_FMT6_FULLfmt */ 914 /* nFields */ 4, 915 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt_fields, 916 /* bits */ 480, 917 /* flags */ 0, 918 }, 919 #endif /* chips */ 920 921 #if defined(BCM_56980_A0) 922 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT7_FULLfmt */ 923 /* format L3_DEFIP_ALPM_PIVOT_FMT7_FULLfmt */ 924 /* nFields */ 3, 925 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT4_FULLfmt_fields, 926 /* bits */ 480, 927 /* flags */ 0, 928 }, 929 #endif /* chips */ 930 931 #if defined(BCM_56980_B0) 932 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT7_FULL_BCM56980_B0fmt */ 933 /* format L3_DEFIP_ALPM_PIVOT_FMT7_FULLfmt */ 934 /* nFields */ 3, 935 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT4_FULLfmt_fields, 936 /* bits */ 480, 937 /* flags */ 0, 938 }, 939 #endif /* chips */ 940 941 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 942 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_PIVOT_FMT8_FULLfmt */ 943 /* format L3_DEFIP_ALPM_PIVOT_FMT8_FULLfmt */ 944 /* nFields */ 3, 945 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT8_FULLfmt_fields, 946 /* bits */ 480, 947 /* flags */ 0, 948 }, 949 #endif /* chips */ 950 951 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 952 defined(BCM_56870_A0) 953 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT1fmt */ 954 /* format L3_DEFIP_ALPM_ROUTE_FMT1fmt */ 955 /* nFields */ 13, 956 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT1fmt_fields, 957 /* bits */ 72, 958 /* flags */ 0, 959 }, 960 #endif /* chips */ 961 962 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 963 defined(BCM_56870_A0) 964 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT2fmt */ 965 /* format L3_DEFIP_ALPM_ROUTE_FMT2fmt */ 966 /* nFields */ 13, 967 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2fmt_fields, 968 /* bits */ 108, 969 /* flags */ 0, 970 }, 971 #endif /* chips */ 972 973 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 974 defined(BCM_56870_A0) 975 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT3fmt */ 976 /* format L3_DEFIP_ALPM_ROUTE_FMT3fmt */ 977 /* nFields */ 16, 978 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT3fmt_fields, 979 /* bits */ 216, 980 /* flags */ 0, 981 }, 982 #endif /* chips */ 983 984 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 985 defined(BCM_56870_A0) 986 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4fmt */ 987 /* format L3_DEFIP_ALPM_ROUTE_FMT4fmt */ 988 /* nFields */ 16, 989 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT4fmt_fields, 990 /* bits */ 108, 991 /* flags */ 0, 992 }, 993 #endif /* chips */ 994 995 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 996 defined(BCM_56870_A0) 997 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT5fmt */ 998 /* format L3_DEFIP_ALPM_ROUTE_FMT5fmt */ 999 /* nFields */ 16, 1000 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT5fmt_fields, 1001 /* bits */ 144, 1002 /* flags */ 0, 1003 }, 1004 #endif /* chips */ 1005 1006 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1007 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT6fmt */ 1008 /* format L3_DEFIP_ALPM_ROUTE_FMT6fmt */ 1009 /* nFields */ 2, 1010 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT6fmt_fields, 1011 /* bits */ 80, 1012 /* flags */ 0, 1013 }, 1014 #endif /* chips */ 1015 1016 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1017 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT7fmt */ 1018 /* format L3_DEFIP_ALPM_ROUTE_FMT7fmt */ 1019 /* nFields */ 2, 1020 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT7fmt_fields, 1021 /* bits */ 96, 1022 /* flags */ 0, 1023 }, 1024 #endif /* chips */ 1025 1026 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1027 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT8fmt */ 1028 /* format L3_DEFIP_ALPM_ROUTE_FMT8fmt */ 1029 /* nFields */ 2, 1030 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT8fmt_fields, 1031 /* bits */ 120, 1032 /* flags */ 0, 1033 }, 1034 #endif /* chips */ 1035 1036 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1037 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT9fmt */ 1038 /* format L3_DEFIP_ALPM_ROUTE_FMT9fmt */ 1039 /* nFields */ 3, 1040 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT9fmt_fields, 1041 /* bits */ 152, 1042 /* flags */ 0, 1043 }, 1044 #endif /* chips */ 1045 1046 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1047 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT10fmt */ 1048 /* format L3_DEFIP_ALPM_ROUTE_FMT10fmt */ 1049 /* nFields */ 2, 1050 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT10fmt_fields, 1051 /* bits */ 80, 1052 /* flags */ 0, 1053 }, 1054 #endif /* chips */ 1055 1056 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1057 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT11fmt */ 1058 /* format L3_DEFIP_ALPM_ROUTE_FMT11fmt */ 1059 /* nFields */ 2, 1060 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT11fmt_fields, 1061 /* bits */ 120, 1062 /* flags */ 0, 1063 }, 1064 #endif /* chips */ 1065 1066 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1067 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT12fmt */ 1068 /* format L3_DEFIP_ALPM_ROUTE_FMT12fmt */ 1069 /* nFields */ 3, 1070 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT12fmt_fields, 1071 /* bits */ 176, 1072 /* flags */ 0, 1073 }, 1074 #endif /* chips */ 1075 1076 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1077 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT13fmt */ 1078 /* format L3_DEFIP_ALPM_ROUTE_FMT13fmt */ 1079 /* nFields */ 2, 1080 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT13fmt_fields, 1081 /* bits */ 24, 1082 /* flags */ 0, 1083 }, 1084 #endif /* chips */ 1085 1086 #if defined(BCM_56980_A0) 1087 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT10_FULLfmt */ 1088 /* format L3_DEFIP_ALPM_ROUTE_FMT10_FULLfmt */ 1089 /* nFields */ 6, 1090 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT1_FULLfmt_fields, 1091 /* bits */ 480, 1092 /* flags */ 0, 1093 }, 1094 #endif /* chips */ 1095 1096 #if defined(BCM_56980_B0) 1097 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT10_FULL_BCM56980_B0fmt */ 1098 /* format L3_DEFIP_ALPM_ROUTE_FMT10_FULLfmt */ 1099 /* nFields */ 6, 1100 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT1_FULLfmt_fields, 1101 /* bits */ 480, 1102 /* flags */ 0, 1103 }, 1104 #endif /* chips */ 1105 1106 #if defined(BCM_56980_A0) 1107 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT11_FULLfmt */ 1108 /* format L3_DEFIP_ALPM_ROUTE_FMT11_FULLfmt */ 1109 /* nFields */ 4, 1110 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt_fields, 1111 /* bits */ 480, 1112 /* flags */ 0, 1113 }, 1114 #endif /* chips */ 1115 1116 #if defined(BCM_56980_B0) 1117 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT11_FULL_BCM56980_B0fmt */ 1118 /* format L3_DEFIP_ALPM_ROUTE_FMT11_FULLfmt */ 1119 /* nFields */ 4, 1120 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt_fields, 1121 /* bits */ 480, 1122 /* flags */ 0, 1123 }, 1124 #endif /* chips */ 1125 1126 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1127 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT12_FULLfmt */ 1128 /* format L3_DEFIP_ALPM_ROUTE_FMT12_FULLfmt */ 1129 /* nFields */ 3, 1130 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT12_FULLfmt_fields, 1131 /* bits */ 480, 1132 /* flags */ 0, 1133 }, 1134 #endif /* chips */ 1135 1136 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1137 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT13_FULLfmt */ 1138 /* format L3_DEFIP_ALPM_ROUTE_FMT13_FULLfmt */ 1139 /* nFields */ 20, 1140 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT13_FULLfmt_fields, 1141 /* bits */ 480, 1142 /* flags */ 0, 1143 }, 1144 #endif /* chips */ 1145 1146 #if defined(BCM_56980_A0) 1147 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT1_BCM56980_A0fmt */ 1148 /* format L3_DEFIP_ALPM_ROUTE_FMT1fmt */ 1149 /* nFields */ 2, 1150 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT1_BCM56980_A0fmt_fields, 1151 /* bits */ 32, 1152 /* flags */ 0, 1153 }, 1154 #endif /* chips */ 1155 1156 #if defined(BCM_56980_B0) 1157 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT1_BCM56980_B0fmt */ 1158 /* format L3_DEFIP_ALPM_ROUTE_FMT1fmt */ 1159 /* nFields */ 2, 1160 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT1_BCM56980_A0fmt_fields, 1161 /* bits */ 32, 1162 /* flags */ 0, 1163 }, 1164 #endif /* chips */ 1165 1166 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1167 defined(BCM_56870_A0) 1168 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT1_FULLfmt */ 1169 /* format L3_DEFIP_ALPM_ROUTE_FMT1_FULLfmt */ 1170 /* nFields */ 6, 1171 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT1_FULLfmt_fields, 1172 /* bits */ 432, 1173 /* flags */ 0, 1174 }, 1175 #endif /* chips */ 1176 1177 #if defined(BCM_56980_A0) 1178 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT1_FULL_BCM56980_A0fmt */ 1179 /* format L3_DEFIP_ALPM_ROUTE_FMT1_FULLfmt */ 1180 /* nFields */ 15, 1181 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT1_FULL_BCM56980_A0fmt_fields, 1182 /* bits */ 480, 1183 /* flags */ 0, 1184 }, 1185 #endif /* chips */ 1186 1187 #if defined(BCM_56980_B0) 1188 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT1_FULL_BCM56980_B0fmt */ 1189 /* format L3_DEFIP_ALPM_ROUTE_FMT1_FULLfmt */ 1190 /* nFields */ 15, 1191 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT1_FULL_BCM56980_A0fmt_fields, 1192 /* bits */ 480, 1193 /* flags */ 0, 1194 }, 1195 #endif /* chips */ 1196 1197 #if defined(BCM_56980_A0) 1198 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT2_BCM56980_A0fmt */ 1199 /* format L3_DEFIP_ALPM_ROUTE_FMT2fmt */ 1200 /* nFields */ 2, 1201 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_BCM56980_A0fmt_fields, 1202 /* bits */ 40, 1203 /* flags */ 0, 1204 }, 1205 #endif /* chips */ 1206 1207 #if defined(BCM_56980_B0) 1208 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT2_BCM56980_B0fmt */ 1209 /* format L3_DEFIP_ALPM_ROUTE_FMT2fmt */ 1210 /* nFields */ 2, 1211 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_BCM56980_A0fmt_fields, 1212 /* bits */ 40, 1213 /* flags */ 0, 1214 }, 1215 #endif /* chips */ 1216 1217 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1218 defined(BCM_56870_A0) 1219 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt */ 1220 /* format L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt */ 1221 /* nFields */ 4, 1222 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt_fields, 1223 /* bits */ 432, 1224 /* flags */ 0, 1225 }, 1226 #endif /* chips */ 1227 1228 #if defined(BCM_56980_A0) 1229 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT2_FULL_BCM56980_A0fmt */ 1230 /* format L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt */ 1231 /* nFields */ 12, 1232 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_FULL_BCM56980_A0fmt_fields, 1233 /* bits */ 480, 1234 /* flags */ 0, 1235 }, 1236 #endif /* chips */ 1237 1238 #if defined(BCM_56980_B0) 1239 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT2_FULL_BCM56980_B0fmt */ 1240 /* format L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt */ 1241 /* nFields */ 12, 1242 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_FULL_BCM56980_A0fmt_fields, 1243 /* bits */ 480, 1244 /* flags */ 0, 1245 }, 1246 #endif /* chips */ 1247 1248 #if defined(BCM_56980_A0) 1249 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT3_BCM56980_A0fmt */ 1250 /* format L3_DEFIP_ALPM_ROUTE_FMT3fmt */ 1251 /* nFields */ 2, 1252 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT3_BCM56980_A0fmt_fields, 1253 /* bits */ 48, 1254 /* flags */ 0, 1255 }, 1256 #endif /* chips */ 1257 1258 #if defined(BCM_56980_B0) 1259 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT3_BCM56980_B0fmt */ 1260 /* format L3_DEFIP_ALPM_ROUTE_FMT3fmt */ 1261 /* nFields */ 2, 1262 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT3_BCM56980_A0fmt_fields, 1263 /* bits */ 48, 1264 /* flags */ 0, 1265 }, 1266 #endif /* chips */ 1267 1268 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1269 defined(BCM_56870_A0) 1270 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT3_FULLfmt */ 1271 /* format L3_DEFIP_ALPM_ROUTE_FMT3_FULLfmt */ 1272 /* nFields */ 2, 1273 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT3_FULLfmt_fields, 1274 /* bits */ 432, 1275 /* flags */ 0, 1276 }, 1277 #endif /* chips */ 1278 1279 #if defined(BCM_56980_A0) 1280 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT3_FULL_BCM56980_A0fmt */ 1281 /* format L3_DEFIP_ALPM_ROUTE_FMT3_FULLfmt */ 1282 /* nFields */ 10, 1283 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT3_FULL_BCM56980_A0fmt_fields, 1284 /* bits */ 480, 1285 /* flags */ 0, 1286 }, 1287 #endif /* chips */ 1288 1289 #if defined(BCM_56980_B0) 1290 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT3_FULL_BCM56980_B0fmt */ 1291 /* format L3_DEFIP_ALPM_ROUTE_FMT3_FULLfmt */ 1292 /* nFields */ 10, 1293 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT3_FULL_BCM56980_A0fmt_fields, 1294 /* bits */ 480, 1295 /* flags */ 0, 1296 }, 1297 #endif /* chips */ 1298 1299 #if defined(BCM_56980_A0) 1300 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4_BCM56980_A0fmt */ 1301 /* format L3_DEFIP_ALPM_ROUTE_FMT4fmt */ 1302 /* nFields */ 2, 1303 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT4_BCM56980_A0fmt_fields, 1304 /* bits */ 56, 1305 /* flags */ 0, 1306 }, 1307 #endif /* chips */ 1308 1309 #if defined(BCM_56980_B0) 1310 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4_BCM56980_B0fmt */ 1311 /* format L3_DEFIP_ALPM_ROUTE_FMT4fmt */ 1312 /* nFields */ 2, 1313 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT4_BCM56980_A0fmt_fields, 1314 /* bits */ 56, 1315 /* flags */ 0, 1316 }, 1317 #endif /* chips */ 1318 1319 #if defined(BCM_56870_A0) 1320 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt */ 1321 /* format L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt */ 1322 /* nFields */ 4, 1323 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt_fields, 1324 /* bits */ 432, 1325 /* flags */ 0, 1326 }, 1327 #endif /* chips */ 1328 1329 #if defined(BCM_56370_A0) 1330 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4_FULL_BCM56370_A0fmt */ 1331 /* format L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt */ 1332 /* nFields */ 4, 1333 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt_fields, 1334 /* bits */ 432, 1335 /* flags */ 0, 1336 }, 1337 #endif /* chips */ 1338 1339 #if defined(BCM_56770_A0) 1340 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4_FULL_BCM56770_A0fmt */ 1341 /* format L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt */ 1342 /* nFields */ 4, 1343 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT2_FULLfmt_fields, 1344 /* bits */ 432, 1345 /* flags */ 0, 1346 }, 1347 #endif /* chips */ 1348 1349 #if defined(BCM_56980_A0) 1350 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4_FULL_BCM56980_A0fmt */ 1351 /* format L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt */ 1352 /* nFields */ 9, 1353 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt_fields, 1354 /* bits */ 480, 1355 /* flags */ 0, 1356 }, 1357 #endif /* chips */ 1358 1359 #if defined(BCM_56980_B0) 1360 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT4_FULL_BCM56980_B0fmt */ 1361 /* format L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt */ 1362 /* nFields */ 9, 1363 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT4_FULLfmt_fields, 1364 /* bits */ 480, 1365 /* flags */ 0, 1366 }, 1367 #endif /* chips */ 1368 1369 #if defined(BCM_56980_A0) 1370 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT5_BCM56980_A0fmt */ 1371 /* format L3_DEFIP_ALPM_ROUTE_FMT5fmt */ 1372 /* nFields */ 2, 1373 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT5_BCM56980_A0fmt_fields, 1374 /* bits */ 64, 1375 /* flags */ 0, 1376 }, 1377 #endif /* chips */ 1378 1379 #if defined(BCM_56980_B0) 1380 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT5_BCM56980_B0fmt */ 1381 /* format L3_DEFIP_ALPM_ROUTE_FMT5fmt */ 1382 /* nFields */ 2, 1383 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT5_BCM56980_A0fmt_fields, 1384 /* bits */ 64, 1385 /* flags */ 0, 1386 }, 1387 #endif /* chips */ 1388 1389 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1390 defined(BCM_56870_A0) 1391 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT5_FULLfmt */ 1392 /* format L3_DEFIP_ALPM_ROUTE_FMT5_FULLfmt */ 1393 /* nFields */ 3, 1394 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT5_FULLfmt_fields, 1395 /* bits */ 432, 1396 /* flags */ 0, 1397 }, 1398 #endif /* chips */ 1399 1400 #if defined(BCM_56980_A0) 1401 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT5_FULL_BCM56980_A0fmt */ 1402 /* format L3_DEFIP_ALPM_ROUTE_FMT5_FULLfmt */ 1403 /* nFields */ 8, 1404 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT5_FULL_BCM56980_A0fmt_fields, 1405 /* bits */ 480, 1406 /* flags */ 0, 1407 }, 1408 #endif /* chips */ 1409 1410 #if defined(BCM_56980_B0) 1411 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT5_FULL_BCM56980_B0fmt */ 1412 /* format L3_DEFIP_ALPM_ROUTE_FMT5_FULLfmt */ 1413 /* nFields */ 8, 1414 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT5_FULL_BCM56980_A0fmt_fields, 1415 /* bits */ 480, 1416 /* flags */ 0, 1417 }, 1418 #endif /* chips */ 1419 1420 #if defined(BCM_56980_A0) 1421 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT6_FULLfmt */ 1422 /* format L3_DEFIP_ALPM_ROUTE_FMT6_FULLfmt */ 1423 /* nFields */ 6, 1424 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT1_FULLfmt_fields, 1425 /* bits */ 480, 1426 /* flags */ 0, 1427 }, 1428 #endif /* chips */ 1429 1430 #if defined(BCM_56980_B0) 1431 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT6_FULL_BCM56980_B0fmt */ 1432 /* format L3_DEFIP_ALPM_ROUTE_FMT6_FULLfmt */ 1433 /* nFields */ 6, 1434 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT1_FULLfmt_fields, 1435 /* bits */ 480, 1436 /* flags */ 0, 1437 }, 1438 #endif /* chips */ 1439 1440 #if defined(BCM_56980_A0) 1441 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT7_FULLfmt */ 1442 /* format L3_DEFIP_ALPM_ROUTE_FMT7_FULLfmt */ 1443 /* nFields */ 5, 1444 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT2_FULLfmt_fields, 1445 /* bits */ 480, 1446 /* flags */ 0, 1447 }, 1448 #endif /* chips */ 1449 1450 #if defined(BCM_56980_B0) 1451 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT7_FULL_BCM56980_B0fmt */ 1452 /* format L3_DEFIP_ALPM_ROUTE_FMT7_FULLfmt */ 1453 /* nFields */ 5, 1454 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT2_FULLfmt_fields, 1455 /* bits */ 480, 1456 /* flags */ 0, 1457 }, 1458 #endif /* chips */ 1459 1460 #if defined(BCM_56980_A0) 1461 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT8_FULLfmt */ 1462 /* format L3_DEFIP_ALPM_ROUTE_FMT8_FULLfmt */ 1463 /* nFields */ 4, 1464 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt_fields, 1465 /* bits */ 480, 1466 /* flags */ 0, 1467 }, 1468 #endif /* chips */ 1469 1470 #if defined(BCM_56980_B0) 1471 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT8_FULL_BCM56980_B0fmt */ 1472 /* format L3_DEFIP_ALPM_ROUTE_FMT8_FULLfmt */ 1473 /* nFields */ 4, 1474 /* *fields */ soc_L3_DEFIP_ALPM_PIVOT_FMT3_FULLfmt_fields, 1475 /* bits */ 480, 1476 /* flags */ 0, 1477 }, 1478 #endif /* chips */ 1479 1480 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1481 { /* SOC_FORMAT_INT_L3_DEFIP_ALPM_ROUTE_FMT9_FULLfmt */ 1482 /* format L3_DEFIP_ALPM_ROUTE_FMT9_FULLfmt */ 1483 /* nFields */ 4, 1484 /* *fields */ soc_L3_DEFIP_ALPM_ROUTE_FMT9_FULLfmt_fields, 1485 /* bits */ 480, 1486 /* flags */ 0, 1487 }, 1488 #endif /* chips */ 1489 1490 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 1491 defined(BCM_56670_A0) || defined(BCM_56670_B0) || \ 1492 defined(BCM_56960_A0) || defined(BCM_56965_A0) 1493 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_0_COV_DEFSfmt */ 1494 /* format L3_DEFIP_DATA_0_COV_DEFSfmt */ 1495 /* nFields */ 6, 1496 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1497 /* bits */ 23, 1498 /* flags */ 0, 1499 }, 1500 #endif /* chips */ 1501 1502 #if defined(BCM_56370_A0) 1503 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_0_COV_DEFS_BCM56370_A0fmt */ 1504 /* format L3_DEFIP_DATA_0_COV_DEFSfmt */ 1505 /* nFields */ 9, 1506 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1507 /* bits */ 28, 1508 /* flags */ 0, 1509 }, 1510 #endif /* chips */ 1511 1512 #if defined(BCM_56770_A0) 1513 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_0_COV_DEFS_BCM56770_A0fmt */ 1514 /* format L3_DEFIP_DATA_0_COV_DEFSfmt */ 1515 /* nFields */ 9, 1516 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1517 /* bits */ 28, 1518 /* flags */ 0, 1519 }, 1520 #endif /* chips */ 1521 1522 #if defined(BCM_56860_A0) 1523 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt */ 1524 /* format L3_DEFIP_DATA_0_COV_DEFSfmt */ 1525 /* nFields */ 6, 1526 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 1527 /* bits */ 23, 1528 /* flags */ 0, 1529 }, 1530 #endif /* chips */ 1531 1532 #if defined(BCM_56870_A0) 1533 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_0_COV_DEFS_BCM56870_A0fmt */ 1534 /* format L3_DEFIP_DATA_0_COV_DEFSfmt */ 1535 /* nFields */ 9, 1536 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1537 /* bits */ 28, 1538 /* flags */ 0, 1539 }, 1540 #endif /* chips */ 1541 1542 #if defined(BCM_56970_A0) 1543 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt */ 1544 /* format L3_DEFIP_DATA_0_COV_DEFSfmt */ 1545 /* nFields */ 9, 1546 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1547 /* bits */ 28, 1548 /* flags */ 0, 1549 }, 1550 #endif /* chips */ 1551 1552 #if defined(BCM_56960_A0) 1553 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFSfmt */ 1554 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1555 /* nFields */ 6, 1556 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1557 /* bits */ 23, 1558 /* flags */ 0, 1559 }, 1560 #endif /* chips */ 1561 1562 #if defined(BCM_56370_A0) 1563 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56370_A0fmt */ 1564 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1565 /* nFields */ 9, 1566 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1567 /* bits */ 28, 1568 /* flags */ 0, 1569 }, 1570 #endif /* chips */ 1571 1572 #if defined(BCM_56560_A0) 1573 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56560_A0fmt */ 1574 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1575 /* nFields */ 6, 1576 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1577 /* bits */ 23, 1578 /* flags */ 0, 1579 }, 1580 #endif /* chips */ 1581 1582 #if defined(BCM_56560_B0) 1583 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56560_B0fmt */ 1584 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1585 /* nFields */ 6, 1586 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1587 /* bits */ 23, 1588 /* flags */ 0, 1589 }, 1590 #endif /* chips */ 1591 1592 #if defined(BCM_56670_A0) 1593 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56670_A0fmt */ 1594 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1595 /* nFields */ 6, 1596 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1597 /* bits */ 23, 1598 /* flags */ 0, 1599 }, 1600 #endif /* chips */ 1601 1602 #if defined(BCM_56670_B0) 1603 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56670_B0fmt */ 1604 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1605 /* nFields */ 6, 1606 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1607 /* bits */ 23, 1608 /* flags */ 0, 1609 }, 1610 #endif /* chips */ 1611 1612 #if defined(BCM_56770_A0) 1613 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56770_A0fmt */ 1614 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1615 /* nFields */ 9, 1616 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1617 /* bits */ 28, 1618 /* flags */ 0, 1619 }, 1620 #endif /* chips */ 1621 1622 #if defined(BCM_56860_A0) 1623 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56860_A0fmt */ 1624 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1625 /* nFields */ 6, 1626 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 1627 /* bits */ 23, 1628 /* flags */ 0, 1629 }, 1630 #endif /* chips */ 1631 1632 #if defined(BCM_56870_A0) 1633 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56870_A0fmt */ 1634 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1635 /* nFields */ 9, 1636 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1637 /* bits */ 28, 1638 /* flags */ 0, 1639 }, 1640 #endif /* chips */ 1641 1642 #if defined(BCM_56965_A0) 1643 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56965_A0fmt */ 1644 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1645 /* nFields */ 6, 1646 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1647 /* bits */ 23, 1648 /* flags */ 0, 1649 }, 1650 #endif /* chips */ 1651 1652 #if defined(BCM_56970_A0) 1653 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_1_COV_DEFS_BCM56970_A0fmt */ 1654 /* format L3_DEFIP_DATA_1_COV_DEFSfmt */ 1655 /* nFields */ 9, 1656 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1657 /* bits */ 28, 1658 /* flags */ 0, 1659 }, 1660 #endif /* chips */ 1661 1662 #if defined(BCM_56960_A0) 1663 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFSfmt */ 1664 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1665 /* nFields */ 6, 1666 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1667 /* bits */ 23, 1668 /* flags */ 0, 1669 }, 1670 #endif /* chips */ 1671 1672 #if defined(BCM_56370_A0) 1673 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56370_A0fmt */ 1674 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1675 /* nFields */ 9, 1676 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1677 /* bits */ 28, 1678 /* flags */ 0, 1679 }, 1680 #endif /* chips */ 1681 1682 #if defined(BCM_56560_A0) 1683 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56560_A0fmt */ 1684 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1685 /* nFields */ 6, 1686 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1687 /* bits */ 23, 1688 /* flags */ 0, 1689 }, 1690 #endif /* chips */ 1691 1692 #if defined(BCM_56560_B0) 1693 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56560_B0fmt */ 1694 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1695 /* nFields */ 6, 1696 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1697 /* bits */ 23, 1698 /* flags */ 0, 1699 }, 1700 #endif /* chips */ 1701 1702 #if defined(BCM_56670_A0) 1703 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56670_A0fmt */ 1704 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1705 /* nFields */ 6, 1706 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1707 /* bits */ 23, 1708 /* flags */ 0, 1709 }, 1710 #endif /* chips */ 1711 1712 #if defined(BCM_56670_B0) 1713 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56670_B0fmt */ 1714 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1715 /* nFields */ 6, 1716 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1717 /* bits */ 23, 1718 /* flags */ 0, 1719 }, 1720 #endif /* chips */ 1721 1722 #if defined(BCM_56770_A0) 1723 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56770_A0fmt */ 1724 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1725 /* nFields */ 9, 1726 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1727 /* bits */ 28, 1728 /* flags */ 0, 1729 }, 1730 #endif /* chips */ 1731 1732 #if defined(BCM_56860_A0) 1733 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56860_A0fmt */ 1734 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1735 /* nFields */ 6, 1736 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 1737 /* bits */ 23, 1738 /* flags */ 0, 1739 }, 1740 #endif /* chips */ 1741 1742 #if defined(BCM_56870_A0) 1743 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56870_A0fmt */ 1744 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1745 /* nFields */ 9, 1746 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1747 /* bits */ 28, 1748 /* flags */ 0, 1749 }, 1750 #endif /* chips */ 1751 1752 #if defined(BCM_56965_A0) 1753 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56965_A0fmt */ 1754 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1755 /* nFields */ 6, 1756 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1757 /* bits */ 23, 1758 /* flags */ 0, 1759 }, 1760 #endif /* chips */ 1761 1762 #if defined(BCM_56970_A0) 1763 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_2_COV_DEFS_BCM56970_A0fmt */ 1764 /* format L3_DEFIP_DATA_2_COV_DEFSfmt */ 1765 /* nFields */ 9, 1766 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1767 /* bits */ 28, 1768 /* flags */ 0, 1769 }, 1770 #endif /* chips */ 1771 1772 #if defined(BCM_56960_A0) 1773 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFSfmt */ 1774 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1775 /* nFields */ 6, 1776 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1777 /* bits */ 23, 1778 /* flags */ 0, 1779 }, 1780 #endif /* chips */ 1781 1782 #if defined(BCM_56370_A0) 1783 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56370_A0fmt */ 1784 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1785 /* nFields */ 9, 1786 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1787 /* bits */ 28, 1788 /* flags */ 0, 1789 }, 1790 #endif /* chips */ 1791 1792 #if defined(BCM_56560_A0) 1793 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56560_A0fmt */ 1794 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1795 /* nFields */ 6, 1796 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1797 /* bits */ 23, 1798 /* flags */ 0, 1799 }, 1800 #endif /* chips */ 1801 1802 #if defined(BCM_56560_B0) 1803 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56560_B0fmt */ 1804 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1805 /* nFields */ 6, 1806 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1807 /* bits */ 23, 1808 /* flags */ 0, 1809 }, 1810 #endif /* chips */ 1811 1812 #if defined(BCM_56670_A0) 1813 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56670_A0fmt */ 1814 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1815 /* nFields */ 6, 1816 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1817 /* bits */ 23, 1818 /* flags */ 0, 1819 }, 1820 #endif /* chips */ 1821 1822 #if defined(BCM_56670_B0) 1823 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56670_B0fmt */ 1824 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1825 /* nFields */ 6, 1826 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1827 /* bits */ 23, 1828 /* flags */ 0, 1829 }, 1830 #endif /* chips */ 1831 1832 #if defined(BCM_56770_A0) 1833 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56770_A0fmt */ 1834 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1835 /* nFields */ 9, 1836 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1837 /* bits */ 28, 1838 /* flags */ 0, 1839 }, 1840 #endif /* chips */ 1841 1842 #if defined(BCM_56860_A0) 1843 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56860_A0fmt */ 1844 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1845 /* nFields */ 6, 1846 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 1847 /* bits */ 23, 1848 /* flags */ 0, 1849 }, 1850 #endif /* chips */ 1851 1852 #if defined(BCM_56870_A0) 1853 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56870_A0fmt */ 1854 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1855 /* nFields */ 9, 1856 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1857 /* bits */ 28, 1858 /* flags */ 0, 1859 }, 1860 #endif /* chips */ 1861 1862 #if defined(BCM_56965_A0) 1863 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56965_A0fmt */ 1864 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1865 /* nFields */ 6, 1866 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1867 /* bits */ 23, 1868 /* flags */ 0, 1869 }, 1870 #endif /* chips */ 1871 1872 #if defined(BCM_56970_A0) 1873 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_3_COV_DEFS_BCM56970_A0fmt */ 1874 /* format L3_DEFIP_DATA_3_COV_DEFSfmt */ 1875 /* nFields */ 9, 1876 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1877 /* bits */ 28, 1878 /* flags */ 0, 1879 }, 1880 #endif /* chips */ 1881 1882 #if defined(BCM_56960_A0) 1883 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFSfmt */ 1884 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1885 /* nFields */ 6, 1886 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1887 /* bits */ 23, 1888 /* flags */ 0, 1889 }, 1890 #endif /* chips */ 1891 1892 #if defined(BCM_56370_A0) 1893 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56370_A0fmt */ 1894 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1895 /* nFields */ 9, 1896 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1897 /* bits */ 28, 1898 /* flags */ 0, 1899 }, 1900 #endif /* chips */ 1901 1902 #if defined(BCM_56560_A0) 1903 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56560_A0fmt */ 1904 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1905 /* nFields */ 6, 1906 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1907 /* bits */ 23, 1908 /* flags */ 0, 1909 }, 1910 #endif /* chips */ 1911 1912 #if defined(BCM_56560_B0) 1913 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56560_B0fmt */ 1914 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1915 /* nFields */ 6, 1916 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1917 /* bits */ 23, 1918 /* flags */ 0, 1919 }, 1920 #endif /* chips */ 1921 1922 #if defined(BCM_56670_A0) 1923 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56670_A0fmt */ 1924 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1925 /* nFields */ 6, 1926 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1927 /* bits */ 23, 1928 /* flags */ 0, 1929 }, 1930 #endif /* chips */ 1931 1932 #if defined(BCM_56670_B0) 1933 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56670_B0fmt */ 1934 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1935 /* nFields */ 6, 1936 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1937 /* bits */ 23, 1938 /* flags */ 0, 1939 }, 1940 #endif /* chips */ 1941 1942 #if defined(BCM_56770_A0) 1943 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56770_A0fmt */ 1944 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1945 /* nFields */ 9, 1946 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1947 /* bits */ 28, 1948 /* flags */ 0, 1949 }, 1950 #endif /* chips */ 1951 1952 #if defined(BCM_56860_A0) 1953 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56860_A0fmt */ 1954 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1955 /* nFields */ 6, 1956 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 1957 /* bits */ 23, 1958 /* flags */ 0, 1959 }, 1960 #endif /* chips */ 1961 1962 #if defined(BCM_56870_A0) 1963 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56870_A0fmt */ 1964 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1965 /* nFields */ 9, 1966 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1967 /* bits */ 28, 1968 /* flags */ 0, 1969 }, 1970 #endif /* chips */ 1971 1972 #if defined(BCM_56965_A0) 1973 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56965_A0fmt */ 1974 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1975 /* nFields */ 6, 1976 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1977 /* bits */ 23, 1978 /* flags */ 0, 1979 }, 1980 #endif /* chips */ 1981 1982 #if defined(BCM_56970_A0) 1983 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_4_COV_DEFS_BCM56970_A0fmt */ 1984 /* format L3_DEFIP_DATA_4_COV_DEFSfmt */ 1985 /* nFields */ 9, 1986 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 1987 /* bits */ 28, 1988 /* flags */ 0, 1989 }, 1990 #endif /* chips */ 1991 1992 #if defined(BCM_56960_A0) 1993 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFSfmt */ 1994 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 1995 /* nFields */ 6, 1996 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 1997 /* bits */ 23, 1998 /* flags */ 0, 1999 }, 2000 #endif /* chips */ 2001 2002 #if defined(BCM_56370_A0) 2003 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56370_A0fmt */ 2004 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2005 /* nFields */ 9, 2006 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2007 /* bits */ 28, 2008 /* flags */ 0, 2009 }, 2010 #endif /* chips */ 2011 2012 #if defined(BCM_56560_A0) 2013 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56560_A0fmt */ 2014 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2015 /* nFields */ 6, 2016 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2017 /* bits */ 23, 2018 /* flags */ 0, 2019 }, 2020 #endif /* chips */ 2021 2022 #if defined(BCM_56560_B0) 2023 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56560_B0fmt */ 2024 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2025 /* nFields */ 6, 2026 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2027 /* bits */ 23, 2028 /* flags */ 0, 2029 }, 2030 #endif /* chips */ 2031 2032 #if defined(BCM_56670_A0) 2033 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56670_A0fmt */ 2034 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2035 /* nFields */ 6, 2036 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2037 /* bits */ 23, 2038 /* flags */ 0, 2039 }, 2040 #endif /* chips */ 2041 2042 #if defined(BCM_56670_B0) 2043 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56670_B0fmt */ 2044 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2045 /* nFields */ 6, 2046 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2047 /* bits */ 23, 2048 /* flags */ 0, 2049 }, 2050 #endif /* chips */ 2051 2052 #if defined(BCM_56770_A0) 2053 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56770_A0fmt */ 2054 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2055 /* nFields */ 9, 2056 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2057 /* bits */ 28, 2058 /* flags */ 0, 2059 }, 2060 #endif /* chips */ 2061 2062 #if defined(BCM_56860_A0) 2063 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56860_A0fmt */ 2064 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2065 /* nFields */ 6, 2066 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 2067 /* bits */ 23, 2068 /* flags */ 0, 2069 }, 2070 #endif /* chips */ 2071 2072 #if defined(BCM_56870_A0) 2073 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56870_A0fmt */ 2074 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2075 /* nFields */ 9, 2076 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2077 /* bits */ 28, 2078 /* flags */ 0, 2079 }, 2080 #endif /* chips */ 2081 2082 #if defined(BCM_56965_A0) 2083 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56965_A0fmt */ 2084 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2085 /* nFields */ 6, 2086 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2087 /* bits */ 23, 2088 /* flags */ 0, 2089 }, 2090 #endif /* chips */ 2091 2092 #if defined(BCM_56970_A0) 2093 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_5_COV_DEFS_BCM56970_A0fmt */ 2094 /* format L3_DEFIP_DATA_5_COV_DEFSfmt */ 2095 /* nFields */ 9, 2096 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2097 /* bits */ 28, 2098 /* flags */ 0, 2099 }, 2100 #endif /* chips */ 2101 2102 #if defined(BCM_56960_A0) 2103 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFSfmt */ 2104 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2105 /* nFields */ 6, 2106 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2107 /* bits */ 23, 2108 /* flags */ 0, 2109 }, 2110 #endif /* chips */ 2111 2112 #if defined(BCM_56370_A0) 2113 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56370_A0fmt */ 2114 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2115 /* nFields */ 9, 2116 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2117 /* bits */ 28, 2118 /* flags */ 0, 2119 }, 2120 #endif /* chips */ 2121 2122 #if defined(BCM_56560_A0) 2123 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56560_A0fmt */ 2124 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2125 /* nFields */ 6, 2126 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2127 /* bits */ 23, 2128 /* flags */ 0, 2129 }, 2130 #endif /* chips */ 2131 2132 #if defined(BCM_56560_B0) 2133 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56560_B0fmt */ 2134 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2135 /* nFields */ 6, 2136 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2137 /* bits */ 23, 2138 /* flags */ 0, 2139 }, 2140 #endif /* chips */ 2141 2142 #if defined(BCM_56670_A0) 2143 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56670_A0fmt */ 2144 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2145 /* nFields */ 6, 2146 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2147 /* bits */ 23, 2148 /* flags */ 0, 2149 }, 2150 #endif /* chips */ 2151 2152 #if defined(BCM_56670_B0) 2153 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56670_B0fmt */ 2154 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2155 /* nFields */ 6, 2156 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2157 /* bits */ 23, 2158 /* flags */ 0, 2159 }, 2160 #endif /* chips */ 2161 2162 #if defined(BCM_56770_A0) 2163 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56770_A0fmt */ 2164 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2165 /* nFields */ 9, 2166 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2167 /* bits */ 28, 2168 /* flags */ 0, 2169 }, 2170 #endif /* chips */ 2171 2172 #if defined(BCM_56860_A0) 2173 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56860_A0fmt */ 2174 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2175 /* nFields */ 6, 2176 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 2177 /* bits */ 23, 2178 /* flags */ 0, 2179 }, 2180 #endif /* chips */ 2181 2182 #if defined(BCM_56870_A0) 2183 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56870_A0fmt */ 2184 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2185 /* nFields */ 9, 2186 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2187 /* bits */ 28, 2188 /* flags */ 0, 2189 }, 2190 #endif /* chips */ 2191 2192 #if defined(BCM_56965_A0) 2193 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56965_A0fmt */ 2194 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2195 /* nFields */ 6, 2196 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2197 /* bits */ 23, 2198 /* flags */ 0, 2199 }, 2200 #endif /* chips */ 2201 2202 #if defined(BCM_56970_A0) 2203 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_6_COV_DEFS_BCM56970_A0fmt */ 2204 /* format L3_DEFIP_DATA_6_COV_DEFSfmt */ 2205 /* nFields */ 9, 2206 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2207 /* bits */ 28, 2208 /* flags */ 0, 2209 }, 2210 #endif /* chips */ 2211 2212 #if defined(BCM_56960_A0) 2213 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFSfmt */ 2214 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2215 /* nFields */ 6, 2216 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2217 /* bits */ 23, 2218 /* flags */ 0, 2219 }, 2220 #endif /* chips */ 2221 2222 #if defined(BCM_56370_A0) 2223 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56370_A0fmt */ 2224 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2225 /* nFields */ 9, 2226 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2227 /* bits */ 28, 2228 /* flags */ 0, 2229 }, 2230 #endif /* chips */ 2231 2232 #if defined(BCM_56560_A0) 2233 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56560_A0fmt */ 2234 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2235 /* nFields */ 6, 2236 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2237 /* bits */ 23, 2238 /* flags */ 0, 2239 }, 2240 #endif /* chips */ 2241 2242 #if defined(BCM_56560_B0) 2243 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56560_B0fmt */ 2244 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2245 /* nFields */ 6, 2246 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2247 /* bits */ 23, 2248 /* flags */ 0, 2249 }, 2250 #endif /* chips */ 2251 2252 #if defined(BCM_56670_A0) 2253 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56670_A0fmt */ 2254 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2255 /* nFields */ 6, 2256 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2257 /* bits */ 23, 2258 /* flags */ 0, 2259 }, 2260 #endif /* chips */ 2261 2262 #if defined(BCM_56670_B0) 2263 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56670_B0fmt */ 2264 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2265 /* nFields */ 6, 2266 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2267 /* bits */ 23, 2268 /* flags */ 0, 2269 }, 2270 #endif /* chips */ 2271 2272 #if defined(BCM_56770_A0) 2273 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56770_A0fmt */ 2274 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2275 /* nFields */ 9, 2276 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2277 /* bits */ 28, 2278 /* flags */ 0, 2279 }, 2280 #endif /* chips */ 2281 2282 #if defined(BCM_56860_A0) 2283 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56860_A0fmt */ 2284 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2285 /* nFields */ 6, 2286 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56860_A0fmt_fields, 2287 /* bits */ 23, 2288 /* flags */ 0, 2289 }, 2290 #endif /* chips */ 2291 2292 #if defined(BCM_56870_A0) 2293 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56870_A0fmt */ 2294 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2295 /* nFields */ 9, 2296 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2297 /* bits */ 28, 2298 /* flags */ 0, 2299 }, 2300 #endif /* chips */ 2301 2302 #if defined(BCM_56965_A0) 2303 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56965_A0fmt */ 2304 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2305 /* nFields */ 6, 2306 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFSfmt_fields, 2307 /* bits */ 23, 2308 /* flags */ 0, 2309 }, 2310 #endif /* chips */ 2311 2312 #if defined(BCM_56970_A0) 2313 { /* SOC_FORMAT_INT_L3_DEFIP_DATA_7_COV_DEFS_BCM56970_A0fmt */ 2314 /* format L3_DEFIP_DATA_7_COV_DEFSfmt */ 2315 /* nFields */ 9, 2316 /* *fields */ soc_L3_DEFIP_DATA_0_COV_DEFS_BCM56970_A0fmt_fields, 2317 /* bits */ 28, 2318 /* flags */ 0, 2319 }, 2320 #endif /* chips */ 2321 2322 #if defined(BCM_56860_A0) 2323 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2324 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2325 /* nFields */ 5, 2326 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFSfmt_fields, 2327 /* bits */ 24, 2328 /* flags */ 0, 2329 }, 2330 #endif /* chips */ 2331 2332 #if defined(BCM_56370_A0) 2333 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56370_A0fmt */ 2334 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2335 /* nFields */ 6, 2336 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 2337 /* bits */ 24, 2338 /* flags */ 0, 2339 }, 2340 #endif /* chips */ 2341 2342 #if defined(BCM_56560_A0) 2343 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56560_A0fmt */ 2344 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2345 /* nFields */ 5, 2346 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 2347 /* bits */ 24, 2348 /* flags */ 0, 2349 }, 2350 #endif /* chips */ 2351 2352 #if defined(BCM_56560_B0) 2353 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56560_B0fmt */ 2354 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2355 /* nFields */ 5, 2356 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 2357 /* bits */ 24, 2358 /* flags */ 0, 2359 }, 2360 #endif /* chips */ 2361 2362 #if defined(BCM_56670_A0) 2363 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56670_A0fmt */ 2364 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2365 /* nFields */ 5, 2366 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 2367 /* bits */ 24, 2368 /* flags */ 0, 2369 }, 2370 #endif /* chips */ 2371 2372 #if defined(BCM_56670_B0) 2373 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56670_B0fmt */ 2374 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2375 /* nFields */ 5, 2376 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 2377 /* bits */ 24, 2378 /* flags */ 0, 2379 }, 2380 #endif /* chips */ 2381 2382 #if defined(BCM_56770_A0) 2383 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56770_A0fmt */ 2384 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2385 /* nFields */ 6, 2386 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 2387 /* bits */ 24, 2388 /* flags */ 0, 2389 }, 2390 #endif /* chips */ 2391 2392 #if defined(BCM_56870_A0) 2393 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56870_A0fmt */ 2394 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2395 /* nFields */ 6, 2396 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 2397 /* bits */ 24, 2398 /* flags */ 0, 2399 }, 2400 #endif /* chips */ 2401 2402 #if defined(BCM_56970_A0) 2403 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56970_A0fmt */ 2404 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2405 /* nFields */ 6, 2406 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 2407 /* bits */ 24, 2408 /* flags */ 0, 2409 }, 2410 #endif /* chips */ 2411 2412 #if defined(BCM_56980_A0) 2413 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56980_A0fmt */ 2414 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2415 /* nFields */ 6, 2416 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 2417 /* bits */ 24, 2418 /* flags */ 0, 2419 }, 2420 #endif /* chips */ 2421 2422 #if defined(BCM_56980_B0) 2423 { /* SOC_FORMAT_INT_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56980_B0fmt */ 2424 /* format L3_DEFIP_HIT_ONLY_COV_DEFSfmt */ 2425 /* nFields */ 6, 2426 /* *fields */ soc_L3_DEFIP_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 2427 /* bits */ 24, 2428 /* flags */ 0, 2429 }, 2430 #endif /* chips */ 2431 2432 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 2433 { /* SOC_FORMAT_INT_L3_DEFIP_TCAM_KEYfmt */ 2434 /* format L3_DEFIP_TCAM_KEYfmt */ 2435 /* nFields */ 5, 2436 /* *fields */ soc_L3_DEFIP_TCAM_KEYfmt_fields, 2437 /* bits */ 48, 2438 /* flags */ 0, 2439 }, 2440 #endif /* chips */ 2441 2442 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 2443 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 2444 defined(BCM_56980_B0) 2445 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt */ 2446 /* format L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt */ 2447 /* nFields */ 6, 2448 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 2449 /* bits */ 18, 2450 /* flags */ 0, 2451 }, 2452 #endif /* chips */ 2453 2454 #if defined(BCM_56960_A0) 2455 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFSfmt */ 2456 /* format L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFSfmt */ 2457 /* nFields */ 6, 2458 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 2459 /* bits */ 18, 2460 /* flags */ 0, 2461 }, 2462 #endif /* chips */ 2463 2464 #if defined(BCM_56965_A0) 2465 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFS_BCM56965_A0fmt */ 2466 /* format L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFSfmt */ 2467 /* nFields */ 6, 2468 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 2469 /* bits */ 18, 2470 /* flags */ 0, 2471 }, 2472 #endif /* chips */ 2473 2474 #if defined(BCM_56970_A0) 2475 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFS_BCM56970_A0fmt */ 2476 /* format L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFSfmt */ 2477 /* nFields */ 6, 2478 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 2479 /* bits */ 18, 2480 /* flags */ 0, 2481 }, 2482 #endif /* chips */ 2483 2484 #if defined(BCM_56980_A0) 2485 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFS_BCM56980_A0fmt */ 2486 /* format L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFSfmt */ 2487 /* nFields */ 6, 2488 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 2489 /* bits */ 18, 2490 /* flags */ 0, 2491 }, 2492 #endif /* chips */ 2493 2494 #if defined(BCM_56980_B0) 2495 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFS_BCM56980_B0fmt */ 2496 /* format L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFSfmt */ 2497 /* nFields */ 6, 2498 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 2499 /* bits */ 18, 2500 /* flags */ 0, 2501 }, 2502 #endif /* chips */ 2503 2504 #if defined(BCM_56870_A0) 2505 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_0_COV_DEFSfmt */ 2506 /* format L3_ECMP_GROUP_RRLB_CNT_0_COV_DEFSfmt */ 2507 /* nFields */ 6, 2508 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2509 /* bits */ 15, 2510 /* flags */ 0, 2511 }, 2512 #endif /* chips */ 2513 2514 #if defined(BCM_56370_A0) 2515 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_0_COV_DEFS_BCM56370_A0fmt */ 2516 /* format L3_ECMP_GROUP_RRLB_CNT_0_COV_DEFSfmt */ 2517 /* nFields */ 6, 2518 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2519 /* bits */ 15, 2520 /* flags */ 0, 2521 }, 2522 #endif /* chips */ 2523 2524 #if defined(BCM_56770_A0) 2525 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_0_COV_DEFS_BCM56770_A0fmt */ 2526 /* format L3_ECMP_GROUP_RRLB_CNT_0_COV_DEFSfmt */ 2527 /* nFields */ 6, 2528 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2529 /* bits */ 15, 2530 /* flags */ 0, 2531 }, 2532 #endif /* chips */ 2533 2534 #if defined(BCM_56870_A0) 2535 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_1_COV_DEFSfmt */ 2536 /* format L3_ECMP_GROUP_RRLB_CNT_1_COV_DEFSfmt */ 2537 /* nFields */ 6, 2538 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2539 /* bits */ 15, 2540 /* flags */ 0, 2541 }, 2542 #endif /* chips */ 2543 2544 #if defined(BCM_56370_A0) 2545 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_1_COV_DEFS_BCM56370_A0fmt */ 2546 /* format L3_ECMP_GROUP_RRLB_CNT_1_COV_DEFSfmt */ 2547 /* nFields */ 6, 2548 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2549 /* bits */ 15, 2550 /* flags */ 0, 2551 }, 2552 #endif /* chips */ 2553 2554 #if defined(BCM_56770_A0) 2555 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_1_COV_DEFS_BCM56770_A0fmt */ 2556 /* format L3_ECMP_GROUP_RRLB_CNT_1_COV_DEFSfmt */ 2557 /* nFields */ 6, 2558 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2559 /* bits */ 15, 2560 /* flags */ 0, 2561 }, 2562 #endif /* chips */ 2563 2564 #if defined(BCM_56870_A0) 2565 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_2_COV_DEFSfmt */ 2566 /* format L3_ECMP_GROUP_RRLB_CNT_2_COV_DEFSfmt */ 2567 /* nFields */ 6, 2568 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2569 /* bits */ 15, 2570 /* flags */ 0, 2571 }, 2572 #endif /* chips */ 2573 2574 #if defined(BCM_56370_A0) 2575 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_2_COV_DEFS_BCM56370_A0fmt */ 2576 /* format L3_ECMP_GROUP_RRLB_CNT_2_COV_DEFSfmt */ 2577 /* nFields */ 6, 2578 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2579 /* bits */ 15, 2580 /* flags */ 0, 2581 }, 2582 #endif /* chips */ 2583 2584 #if defined(BCM_56770_A0) 2585 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_2_COV_DEFS_BCM56770_A0fmt */ 2586 /* format L3_ECMP_GROUP_RRLB_CNT_2_COV_DEFSfmt */ 2587 /* nFields */ 6, 2588 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2589 /* bits */ 15, 2590 /* flags */ 0, 2591 }, 2592 #endif /* chips */ 2593 2594 #if defined(BCM_56870_A0) 2595 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_3_COV_DEFSfmt */ 2596 /* format L3_ECMP_GROUP_RRLB_CNT_3_COV_DEFSfmt */ 2597 /* nFields */ 6, 2598 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2599 /* bits */ 15, 2600 /* flags */ 0, 2601 }, 2602 #endif /* chips */ 2603 2604 #if defined(BCM_56370_A0) 2605 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_3_COV_DEFS_BCM56370_A0fmt */ 2606 /* format L3_ECMP_GROUP_RRLB_CNT_3_COV_DEFSfmt */ 2607 /* nFields */ 6, 2608 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2609 /* bits */ 15, 2610 /* flags */ 0, 2611 }, 2612 #endif /* chips */ 2613 2614 #if defined(BCM_56770_A0) 2615 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_3_COV_DEFS_BCM56770_A0fmt */ 2616 /* format L3_ECMP_GROUP_RRLB_CNT_3_COV_DEFSfmt */ 2617 /* nFields */ 6, 2618 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2619 /* bits */ 15, 2620 /* flags */ 0, 2621 }, 2622 #endif /* chips */ 2623 2624 #if defined(BCM_56870_A0) 2625 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_4_COV_DEFSfmt */ 2626 /* format L3_ECMP_GROUP_RRLB_CNT_4_COV_DEFSfmt */ 2627 /* nFields */ 6, 2628 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2629 /* bits */ 15, 2630 /* flags */ 0, 2631 }, 2632 #endif /* chips */ 2633 2634 #if defined(BCM_56370_A0) 2635 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_4_COV_DEFS_BCM56370_A0fmt */ 2636 /* format L3_ECMP_GROUP_RRLB_CNT_4_COV_DEFSfmt */ 2637 /* nFields */ 6, 2638 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2639 /* bits */ 15, 2640 /* flags */ 0, 2641 }, 2642 #endif /* chips */ 2643 2644 #if defined(BCM_56770_A0) 2645 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_4_COV_DEFS_BCM56770_A0fmt */ 2646 /* format L3_ECMP_GROUP_RRLB_CNT_4_COV_DEFSfmt */ 2647 /* nFields */ 6, 2648 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2649 /* bits */ 15, 2650 /* flags */ 0, 2651 }, 2652 #endif /* chips */ 2653 2654 #if defined(BCM_56870_A0) 2655 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_5_COV_DEFSfmt */ 2656 /* format L3_ECMP_GROUP_RRLB_CNT_5_COV_DEFSfmt */ 2657 /* nFields */ 6, 2658 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2659 /* bits */ 15, 2660 /* flags */ 0, 2661 }, 2662 #endif /* chips */ 2663 2664 #if defined(BCM_56370_A0) 2665 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_5_COV_DEFS_BCM56370_A0fmt */ 2666 /* format L3_ECMP_GROUP_RRLB_CNT_5_COV_DEFSfmt */ 2667 /* nFields */ 6, 2668 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2669 /* bits */ 15, 2670 /* flags */ 0, 2671 }, 2672 #endif /* chips */ 2673 2674 #if defined(BCM_56770_A0) 2675 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_5_COV_DEFS_BCM56770_A0fmt */ 2676 /* format L3_ECMP_GROUP_RRLB_CNT_5_COV_DEFSfmt */ 2677 /* nFields */ 6, 2678 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2679 /* bits */ 15, 2680 /* flags */ 0, 2681 }, 2682 #endif /* chips */ 2683 2684 #if defined(BCM_56870_A0) 2685 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_6_COV_DEFSfmt */ 2686 /* format L3_ECMP_GROUP_RRLB_CNT_6_COV_DEFSfmt */ 2687 /* nFields */ 6, 2688 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2689 /* bits */ 15, 2690 /* flags */ 0, 2691 }, 2692 #endif /* chips */ 2693 2694 #if defined(BCM_56370_A0) 2695 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_6_COV_DEFS_BCM56370_A0fmt */ 2696 /* format L3_ECMP_GROUP_RRLB_CNT_6_COV_DEFSfmt */ 2697 /* nFields */ 6, 2698 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2699 /* bits */ 15, 2700 /* flags */ 0, 2701 }, 2702 #endif /* chips */ 2703 2704 #if defined(BCM_56770_A0) 2705 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_6_COV_DEFS_BCM56770_A0fmt */ 2706 /* format L3_ECMP_GROUP_RRLB_CNT_6_COV_DEFSfmt */ 2707 /* nFields */ 6, 2708 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2709 /* bits */ 15, 2710 /* flags */ 0, 2711 }, 2712 #endif /* chips */ 2713 2714 #if defined(BCM_56870_A0) 2715 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_7_COV_DEFSfmt */ 2716 /* format L3_ECMP_GROUP_RRLB_CNT_7_COV_DEFSfmt */ 2717 /* nFields */ 6, 2718 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2719 /* bits */ 15, 2720 /* flags */ 0, 2721 }, 2722 #endif /* chips */ 2723 2724 #if defined(BCM_56370_A0) 2725 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_7_COV_DEFS_BCM56370_A0fmt */ 2726 /* format L3_ECMP_GROUP_RRLB_CNT_7_COV_DEFSfmt */ 2727 /* nFields */ 6, 2728 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2729 /* bits */ 15, 2730 /* flags */ 0, 2731 }, 2732 #endif /* chips */ 2733 2734 #if defined(BCM_56770_A0) 2735 { /* SOC_FORMAT_INT_L3_ECMP_GROUP_RRLB_CNT_7_COV_DEFS_BCM56770_A0fmt */ 2736 /* format L3_ECMP_GROUP_RRLB_CNT_7_COV_DEFSfmt */ 2737 /* nFields */ 6, 2738 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 2739 /* bits */ 15, 2740 /* flags */ 0, 2741 }, 2742 #endif /* chips */ 2743 2744 #if defined(BCM_56640_A0) 2745 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATAfmt */ 2746 /* format L3_ENTRY_1_DATAfmt */ 2747 /* nFields */ 21, 2748 /* *fields */ soc_L3_ENTRY_1_DATAfmt_fields, 2749 /* bits */ 36, 2750 /* flags */ 0, 2751 }, 2752 #endif /* chips */ 2753 2754 #if defined(BCM_56260_A0) 2755 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56260_A0fmt */ 2756 /* format L3_ENTRY_1_DATAfmt */ 2757 /* nFields */ 16, 2758 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56960_A0fmt_fields, 2759 /* bits */ 32, 2760 /* flags */ 0, 2761 }, 2762 #endif /* chips */ 2763 2764 #if defined(BCM_56260_B0) 2765 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56260_B0fmt */ 2766 /* format L3_ENTRY_1_DATAfmt */ 2767 /* nFields */ 16, 2768 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56960_A0fmt_fields, 2769 /* bits */ 32, 2770 /* flags */ 0, 2771 }, 2772 #endif /* chips */ 2773 2774 #if defined(BCM_56270_A0) 2775 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56270_A0fmt */ 2776 /* format L3_ENTRY_1_DATAfmt */ 2777 /* nFields */ 16, 2778 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56960_A0fmt_fields, 2779 /* bits */ 32, 2780 /* flags */ 0, 2781 }, 2782 #endif /* chips */ 2783 2784 #if defined(BCM_56340_A0) 2785 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56340_A0fmt */ 2786 /* format L3_ENTRY_1_DATAfmt */ 2787 /* nFields */ 23, 2788 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56340_A0fmt_fields, 2789 /* bits */ 36, 2790 /* flags */ 0, 2791 }, 2792 #endif /* chips */ 2793 2794 #if defined(BCM_56560_A0) 2795 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56560_A0fmt */ 2796 /* format L3_ENTRY_1_DATAfmt */ 2797 /* nFields */ 27, 2798 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56560_A0fmt_fields, 2799 /* bits */ 32, 2800 /* flags */ 0, 2801 }, 2802 #endif /* chips */ 2803 2804 #if defined(BCM_56560_B0) 2805 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56560_B0fmt */ 2806 /* format L3_ENTRY_1_DATAfmt */ 2807 /* nFields */ 27, 2808 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56560_A0fmt_fields, 2809 /* bits */ 32, 2810 /* flags */ 0, 2811 }, 2812 #endif /* chips */ 2813 2814 #if defined(BCM_56670_A0) 2815 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56670_A0fmt */ 2816 /* format L3_ENTRY_1_DATAfmt */ 2817 /* nFields */ 30, 2818 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56670_A0fmt_fields, 2819 /* bits */ 33, 2820 /* flags */ 0, 2821 }, 2822 #endif /* chips */ 2823 2824 #if defined(BCM_56670_B0) 2825 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56670_B0fmt */ 2826 /* format L3_ENTRY_1_DATAfmt */ 2827 /* nFields */ 30, 2828 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56670_A0fmt_fields, 2829 /* bits */ 33, 2830 /* flags */ 0, 2831 }, 2832 #endif /* chips */ 2833 2834 #if defined(BCM_56850_A0) 2835 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56850_A0fmt */ 2836 /* format L3_ENTRY_1_DATAfmt */ 2837 /* nFields */ 27, 2838 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56850_A0fmt_fields, 2839 /* bits */ 32, 2840 /* flags */ 0, 2841 }, 2842 #endif /* chips */ 2843 2844 #if defined(BCM_56860_A0) 2845 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56860_A0fmt */ 2846 /* format L3_ENTRY_1_DATAfmt */ 2847 /* nFields */ 27, 2848 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56860_A0fmt_fields, 2849 /* bits */ 32, 2850 /* flags */ 0, 2851 }, 2852 #endif /* chips */ 2853 2854 #if defined(BCM_56960_A0) 2855 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56960_A0fmt */ 2856 /* format L3_ENTRY_1_DATAfmt */ 2857 /* nFields */ 16, 2858 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56960_A0fmt_fields, 2859 /* bits */ 32, 2860 /* flags */ 0, 2861 }, 2862 #endif /* chips */ 2863 2864 #if defined(BCM_56965_A0) 2865 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56965_A0fmt */ 2866 /* format L3_ENTRY_1_DATAfmt */ 2867 /* nFields */ 16, 2868 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56960_A0fmt_fields, 2869 /* bits */ 32, 2870 /* flags */ 0, 2871 }, 2872 #endif /* chips */ 2873 2874 #if defined(BCM_56970_A0) 2875 { /* SOC_FORMAT_INT_L3_ENTRY_1_DATA_BCM56970_A0fmt */ 2876 /* format L3_ENTRY_1_DATAfmt */ 2877 /* nFields */ 16, 2878 /* *fields */ soc_L3_ENTRY_1_DATA_BCM56970_A0fmt_fields, 2879 /* bits */ 32, 2880 /* flags */ 0, 2881 }, 2882 #endif /* chips */ 2883 2884 #if defined(BCM_56640_A0) 2885 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATAfmt */ 2886 /* format L3_ENTRY_2_DATAfmt */ 2887 /* nFields */ 39, 2888 /* *fields */ soc_L3_ENTRY_2_DATAfmt_fields, 2889 /* bits */ 148, 2890 /* flags */ 0, 2891 }, 2892 #endif /* chips */ 2893 2894 #if defined(BCM_56260_A0) 2895 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56260_A0fmt */ 2896 /* format L3_ENTRY_2_DATAfmt */ 2897 /* nFields */ 77, 2898 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56960_A0fmt_fields, 2899 /* bits */ 132, 2900 /* flags */ 0, 2901 }, 2902 #endif /* chips */ 2903 2904 #if defined(BCM_56260_B0) 2905 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56260_B0fmt */ 2906 /* format L3_ENTRY_2_DATAfmt */ 2907 /* nFields */ 77, 2908 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56960_A0fmt_fields, 2909 /* bits */ 132, 2910 /* flags */ 0, 2911 }, 2912 #endif /* chips */ 2913 2914 #if defined(BCM_56270_A0) 2915 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56270_A0fmt */ 2916 /* format L3_ENTRY_2_DATAfmt */ 2917 /* nFields */ 77, 2918 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56960_A0fmt_fields, 2919 /* bits */ 132, 2920 /* flags */ 0, 2921 }, 2922 #endif /* chips */ 2923 2924 #if defined(BCM_56340_A0) 2925 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56340_A0fmt */ 2926 /* format L3_ENTRY_2_DATAfmt */ 2927 /* nFields */ 42, 2928 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56340_A0fmt_fields, 2929 /* bits */ 149, 2930 /* flags */ 0, 2931 }, 2932 #endif /* chips */ 2933 2934 #if defined(BCM_56560_A0) 2935 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56560_A0fmt */ 2936 /* format L3_ENTRY_2_DATAfmt */ 2937 /* nFields */ 98, 2938 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56560_A0fmt_fields, 2939 /* bits */ 134, 2940 /* flags */ 0, 2941 }, 2942 #endif /* chips */ 2943 2944 #if defined(BCM_56560_B0) 2945 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56560_B0fmt */ 2946 /* format L3_ENTRY_2_DATAfmt */ 2947 /* nFields */ 98, 2948 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56560_A0fmt_fields, 2949 /* bits */ 134, 2950 /* flags */ 0, 2951 }, 2952 #endif /* chips */ 2953 2954 #if defined(BCM_56670_A0) 2955 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56670_A0fmt */ 2956 /* format L3_ENTRY_2_DATAfmt */ 2957 /* nFields */ 89, 2958 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56670_A0fmt_fields, 2959 /* bits */ 116, 2960 /* flags */ 0, 2961 }, 2962 #endif /* chips */ 2963 2964 #if defined(BCM_56670_B0) 2965 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56670_B0fmt */ 2966 /* format L3_ENTRY_2_DATAfmt */ 2967 /* nFields */ 89, 2968 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56670_A0fmt_fields, 2969 /* bits */ 116, 2970 /* flags */ 0, 2971 }, 2972 #endif /* chips */ 2973 2974 #if defined(BCM_56850_A0) 2975 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56850_A0fmt */ 2976 /* format L3_ENTRY_2_DATAfmt */ 2977 /* nFields */ 93, 2978 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56850_A0fmt_fields, 2979 /* bits */ 131, 2980 /* flags */ 0, 2981 }, 2982 #endif /* chips */ 2983 2984 #if defined(BCM_56860_A0) 2985 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56860_A0fmt */ 2986 /* format L3_ENTRY_2_DATAfmt */ 2987 /* nFields */ 98, 2988 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56860_A0fmt_fields, 2989 /* bits */ 134, 2990 /* flags */ 0, 2991 }, 2992 #endif /* chips */ 2993 2994 #if defined(BCM_56960_A0) 2995 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56960_A0fmt */ 2996 /* format L3_ENTRY_2_DATAfmt */ 2997 /* nFields */ 77, 2998 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56960_A0fmt_fields, 2999 /* bits */ 132, 3000 /* flags */ 0, 3001 }, 3002 #endif /* chips */ 3003 3004 #if defined(BCM_56965_A0) 3005 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56965_A0fmt */ 3006 /* format L3_ENTRY_2_DATAfmt */ 3007 /* nFields */ 77, 3008 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56965_A0fmt_fields, 3009 /* bits */ 133, 3010 /* flags */ 0, 3011 }, 3012 #endif /* chips */ 3013 3014 #if defined(BCM_56970_A0) 3015 { /* SOC_FORMAT_INT_L3_ENTRY_2_DATA_BCM56970_A0fmt */ 3016 /* format L3_ENTRY_2_DATAfmt */ 3017 /* nFields */ 75, 3018 /* *fields */ soc_L3_ENTRY_2_DATA_BCM56970_A0fmt_fields, 3019 /* bits */ 133, 3020 /* flags */ 0, 3021 }, 3022 #endif /* chips */ 3023 3024 #if defined(BCM_56640_A0) 3025 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATAfmt */ 3026 /* format L3_ENTRY_4_DATAfmt */ 3027 /* nFields */ 32, 3028 /* *fields */ soc_L3_ENTRY_4_DATAfmt_fields, 3029 /* bits */ 148, 3030 /* flags */ 0, 3031 }, 3032 #endif /* chips */ 3033 3034 #if defined(BCM_56260_A0) 3035 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56260_A0fmt */ 3036 /* format L3_ENTRY_4_DATAfmt */ 3037 /* nFields */ 53, 3038 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56960_A0fmt_fields, 3039 /* bits */ 132, 3040 /* flags */ 0, 3041 }, 3042 #endif /* chips */ 3043 3044 #if defined(BCM_56260_B0) 3045 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56260_B0fmt */ 3046 /* format L3_ENTRY_4_DATAfmt */ 3047 /* nFields */ 53, 3048 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56960_A0fmt_fields, 3049 /* bits */ 132, 3050 /* flags */ 0, 3051 }, 3052 #endif /* chips */ 3053 3054 #if defined(BCM_56270_A0) 3055 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56270_A0fmt */ 3056 /* format L3_ENTRY_4_DATAfmt */ 3057 /* nFields */ 53, 3058 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56960_A0fmt_fields, 3059 /* bits */ 132, 3060 /* flags */ 0, 3061 }, 3062 #endif /* chips */ 3063 3064 #if defined(BCM_56340_A0) 3065 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56340_A0fmt */ 3066 /* format L3_ENTRY_4_DATAfmt */ 3067 /* nFields */ 35, 3068 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56340_A0fmt_fields, 3069 /* bits */ 149, 3070 /* flags */ 0, 3071 }, 3072 #endif /* chips */ 3073 3074 #if defined(BCM_56560_A0) 3075 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56560_A0fmt */ 3076 /* format L3_ENTRY_4_DATAfmt */ 3077 /* nFields */ 52, 3078 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56560_A0fmt_fields, 3079 /* bits */ 134, 3080 /* flags */ 0, 3081 }, 3082 #endif /* chips */ 3083 3084 #if defined(BCM_56560_B0) 3085 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56560_B0fmt */ 3086 /* format L3_ENTRY_4_DATAfmt */ 3087 /* nFields */ 52, 3088 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56560_A0fmt_fields, 3089 /* bits */ 134, 3090 /* flags */ 0, 3091 }, 3092 #endif /* chips */ 3093 3094 #if defined(BCM_56670_A0) 3095 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56670_A0fmt */ 3096 /* format L3_ENTRY_4_DATAfmt */ 3097 /* nFields */ 44, 3098 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56670_A0fmt_fields, 3099 /* bits */ 113, 3100 /* flags */ 0, 3101 }, 3102 #endif /* chips */ 3103 3104 #if defined(BCM_56670_B0) 3105 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56670_B0fmt */ 3106 /* format L3_ENTRY_4_DATAfmt */ 3107 /* nFields */ 44, 3108 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56670_A0fmt_fields, 3109 /* bits */ 113, 3110 /* flags */ 0, 3111 }, 3112 #endif /* chips */ 3113 3114 #if defined(BCM_56850_A0) 3115 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56850_A0fmt */ 3116 /* format L3_ENTRY_4_DATAfmt */ 3117 /* nFields */ 45, 3118 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56850_A0fmt_fields, 3119 /* bits */ 131, 3120 /* flags */ 0, 3121 }, 3122 #endif /* chips */ 3123 3124 #if defined(BCM_56860_A0) 3125 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56860_A0fmt */ 3126 /* format L3_ENTRY_4_DATAfmt */ 3127 /* nFields */ 51, 3128 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56860_A0fmt_fields, 3129 /* bits */ 134, 3130 /* flags */ 0, 3131 }, 3132 #endif /* chips */ 3133 3134 #if defined(BCM_56960_A0) 3135 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56960_A0fmt */ 3136 /* format L3_ENTRY_4_DATAfmt */ 3137 /* nFields */ 53, 3138 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56960_A0fmt_fields, 3139 /* bits */ 132, 3140 /* flags */ 0, 3141 }, 3142 #endif /* chips */ 3143 3144 #if defined(BCM_56965_A0) 3145 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56965_A0fmt */ 3146 /* format L3_ENTRY_4_DATAfmt */ 3147 /* nFields */ 53, 3148 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56965_A0fmt_fields, 3149 /* bits */ 133, 3150 /* flags */ 0, 3151 }, 3152 #endif /* chips */ 3153 3154 #if defined(BCM_56970_A0) 3155 { /* SOC_FORMAT_INT_L3_ENTRY_4_DATA_BCM56970_A0fmt */ 3156 /* format L3_ENTRY_4_DATAfmt */ 3157 /* nFields */ 51, 3158 /* *fields */ soc_L3_ENTRY_4_DATA_BCM56970_A0fmt_fields, 3159 /* bits */ 133, 3160 /* flags */ 0, 3161 }, 3162 #endif /* chips */ 3163 3164 #if defined(BCM_56860_A0) 3165 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3166 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3167 /* nFields */ 5, 3168 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFSfmt_fields, 3169 /* bits */ 30, 3170 /* flags */ 0, 3171 }, 3172 #endif /* chips */ 3173 3174 #if defined(BCM_56370_A0) 3175 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56370_A0fmt */ 3176 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3177 /* nFields */ 6, 3178 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 3179 /* bits */ 30, 3180 /* flags */ 0, 3181 }, 3182 #endif /* chips */ 3183 3184 #if defined(BCM_56560_A0) 3185 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56560_A0fmt */ 3186 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3187 /* nFields */ 5, 3188 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 3189 /* bits */ 30, 3190 /* flags */ 0, 3191 }, 3192 #endif /* chips */ 3193 3194 #if defined(BCM_56560_B0) 3195 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56560_B0fmt */ 3196 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3197 /* nFields */ 5, 3198 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 3199 /* bits */ 30, 3200 /* flags */ 0, 3201 }, 3202 #endif /* chips */ 3203 3204 #if defined(BCM_56670_A0) 3205 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56670_A0fmt */ 3206 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3207 /* nFields */ 5, 3208 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 3209 /* bits */ 30, 3210 /* flags */ 0, 3211 }, 3212 #endif /* chips */ 3213 3214 #if defined(BCM_56670_B0) 3215 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56670_B0fmt */ 3216 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3217 /* nFields */ 5, 3218 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56560_A0fmt_fields, 3219 /* bits */ 30, 3220 /* flags */ 0, 3221 }, 3222 #endif /* chips */ 3223 3224 #if defined(BCM_56770_A0) 3225 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56770_A0fmt */ 3226 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3227 /* nFields */ 6, 3228 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 3229 /* bits */ 30, 3230 /* flags */ 0, 3231 }, 3232 #endif /* chips */ 3233 3234 #if defined(BCM_56870_A0) 3235 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56870_A0fmt */ 3236 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3237 /* nFields */ 6, 3238 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 3239 /* bits */ 30, 3240 /* flags */ 0, 3241 }, 3242 #endif /* chips */ 3243 3244 #if defined(BCM_56970_A0) 3245 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56970_A0fmt */ 3246 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3247 /* nFields */ 6, 3248 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 3249 /* bits */ 30, 3250 /* flags */ 0, 3251 }, 3252 #endif /* chips */ 3253 3254 #if defined(BCM_56980_A0) 3255 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56980_A0fmt */ 3256 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3257 /* nFields */ 6, 3258 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 3259 /* bits */ 30, 3260 /* flags */ 0, 3261 }, 3262 #endif /* chips */ 3263 3264 #if defined(BCM_56980_B0) 3265 { /* SOC_FORMAT_INT_L3_ENTRY_HIT_ONLY_COV_DEFS_BCM56980_B0fmt */ 3266 /* format L3_ENTRY_HIT_ONLY_COV_DEFSfmt */ 3267 /* nFields */ 6, 3268 /* *fields */ soc_L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS_BCM56970_A0fmt_fields, 3269 /* bits */ 30, 3270 /* flags */ 0, 3271 }, 3272 #endif /* chips */ 3273 3274 #if defined(BCM_56640_A0) 3275 { /* SOC_FORMAT_INT_L3_ENTRY_KEYfmt */ 3276 /* format L3_ENTRY_KEYfmt */ 3277 /* nFields */ 57, 3278 /* *fields */ soc_L3_ENTRY_KEYfmt_fields, 3279 /* bits */ 279, 3280 /* flags */ 0, 3281 }, 3282 #endif /* chips */ 3283 3284 #if defined(BCM_56260_A0) 3285 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56260_A0fmt */ 3286 /* format L3_ENTRY_KEYfmt */ 3287 /* nFields */ 69, 3288 /* *fields */ soc_L3_ENTRY_KEY_BCM56960_A0fmt_fields, 3289 /* bits */ 278, 3290 /* flags */ 0, 3291 }, 3292 #endif /* chips */ 3293 3294 #if defined(BCM_56260_B0) 3295 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56260_B0fmt */ 3296 /* format L3_ENTRY_KEYfmt */ 3297 /* nFields */ 69, 3298 /* *fields */ soc_L3_ENTRY_KEY_BCM56960_A0fmt_fields, 3299 /* bits */ 278, 3300 /* flags */ 0, 3301 }, 3302 #endif /* chips */ 3303 3304 #if defined(BCM_56270_A0) 3305 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56270_A0fmt */ 3306 /* format L3_ENTRY_KEYfmt */ 3307 /* nFields */ 69, 3308 /* *fields */ soc_L3_ENTRY_KEY_BCM56960_A0fmt_fields, 3309 /* bits */ 278, 3310 /* flags */ 0, 3311 }, 3312 #endif /* chips */ 3313 3314 #if defined(BCM_56340_A0) 3315 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56340_A0fmt */ 3316 /* format L3_ENTRY_KEYfmt */ 3317 /* nFields */ 57, 3318 /* *fields */ soc_L3_ENTRY_KEY_BCM56340_A0fmt_fields, 3319 /* bits */ 279, 3320 /* flags */ 0, 3321 }, 3322 #endif /* chips */ 3323 3324 #if defined(BCM_56560_A0) 3325 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56560_A0fmt */ 3326 /* format L3_ENTRY_KEYfmt */ 3327 /* nFields */ 88, 3328 /* *fields */ soc_L3_ENTRY_KEY_BCM56560_A0fmt_fields, 3329 /* bits */ 279, 3330 /* flags */ 0, 3331 }, 3332 #endif /* chips */ 3333 3334 #if defined(BCM_56560_B0) 3335 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56560_B0fmt */ 3336 /* format L3_ENTRY_KEYfmt */ 3337 /* nFields */ 88, 3338 /* *fields */ soc_L3_ENTRY_KEY_BCM56560_A0fmt_fields, 3339 /* bits */ 279, 3340 /* flags */ 0, 3341 }, 3342 #endif /* chips */ 3343 3344 #if defined(BCM_56670_A0) 3345 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56670_A0fmt */ 3346 /* format L3_ENTRY_KEYfmt */ 3347 /* nFields */ 97, 3348 /* *fields */ soc_L3_ENTRY_KEY_BCM56670_A0fmt_fields, 3349 /* bits */ 279, 3350 /* flags */ 0, 3351 }, 3352 #endif /* chips */ 3353 3354 #if defined(BCM_56670_B0) 3355 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56670_B0fmt */ 3356 /* format L3_ENTRY_KEYfmt */ 3357 /* nFields */ 97, 3358 /* *fields */ soc_L3_ENTRY_KEY_BCM56670_A0fmt_fields, 3359 /* bits */ 279, 3360 /* flags */ 0, 3361 }, 3362 #endif /* chips */ 3363 3364 #if defined(BCM_56850_A0) 3365 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56850_A0fmt */ 3366 /* format L3_ENTRY_KEYfmt */ 3367 /* nFields */ 96, 3368 /* *fields */ soc_L3_ENTRY_KEY_BCM56850_A0fmt_fields, 3369 /* bits */ 278, 3370 /* flags */ 0, 3371 }, 3372 #endif /* chips */ 3373 3374 #if defined(BCM_56860_A0) 3375 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56860_A0fmt */ 3376 /* format L3_ENTRY_KEYfmt */ 3377 /* nFields */ 88, 3378 /* *fields */ soc_L3_ENTRY_KEY_BCM56860_A0fmt_fields, 3379 /* bits */ 279, 3380 /* flags */ 0, 3381 }, 3382 #endif /* chips */ 3383 3384 #if defined(BCM_56960_A0) 3385 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56960_A0fmt */ 3386 /* format L3_ENTRY_KEYfmt */ 3387 /* nFields */ 69, 3388 /* *fields */ soc_L3_ENTRY_KEY_BCM56960_A0fmt_fields, 3389 /* bits */ 278, 3390 /* flags */ 0, 3391 }, 3392 #endif /* chips */ 3393 3394 #if defined(BCM_56965_A0) 3395 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56965_A0fmt */ 3396 /* format L3_ENTRY_KEYfmt */ 3397 /* nFields */ 69, 3398 /* *fields */ soc_L3_ENTRY_KEY_BCM56960_A0fmt_fields, 3399 /* bits */ 278, 3400 /* flags */ 0, 3401 }, 3402 #endif /* chips */ 3403 3404 #if defined(BCM_56970_A0) 3405 { /* SOC_FORMAT_INT_L3_ENTRY_KEY_BCM56970_A0fmt */ 3406 /* format L3_ENTRY_KEYfmt */ 3407 /* nFields */ 69, 3408 /* *fields */ soc_L3_ENTRY_KEY_BCM56960_A0fmt_fields, 3409 /* bits */ 278, 3410 /* flags */ 0, 3411 }, 3412 #endif /* chips */ 3413 3414 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 3415 { /* SOC_FORMAT_INT_L3_FWD_TABLE_ATTRIBUTESfmt */ 3416 /* format L3_FWD_TABLE_ATTRIBUTESfmt */ 3417 /* nFields */ 41, 3418 /* *fields */ soc_L3_FWD_TABLE_ATTRIBUTESfmt_fields, 3419 /* bits */ 215, 3420 /* flags */ 0, 3421 }, 3422 #endif /* chips */ 3423 3424 #if defined(BCM_56370_A0) 3425 { /* SOC_FORMAT_INT_L3_FWD_TABLE_ATTRIBUTES_BCM56370_A0fmt */ 3426 /* format L3_FWD_TABLE_ATTRIBUTESfmt */ 3427 /* nFields */ 43, 3428 /* *fields */ soc_L3_FWD_TABLE_ATTRIBUTES_BCM56370_A0fmt_fields, 3429 /* bits */ 215, 3430 /* flags */ 0, 3431 }, 3432 #endif /* chips */ 3433 3434 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3435 defined(BCM_56870_A0) 3436 { /* SOC_FORMAT_INT_L3_GRE_HDRfmt */ 3437 /* format L3_GRE_HDRfmt */ 3438 /* nFields */ 9, 3439 /* *fields */ soc_L3_GRE_HDRfmt_fields, 3440 /* bits */ 32, 3441 /* flags */ 0, 3442 }, 3443 #endif /* chips */ 3444 3445 #if defined(BCM_56860_A0) 3446 { /* SOC_FORMAT_INT_L3_IIF_SOURCEfmt */ 3447 /* format L3_IIF_SOURCEfmt */ 3448 /* nFields */ 1, 3449 /* *fields */ soc_L3_IIF_SOURCEfmt_fields, 3450 /* bits */ 3, 3451 /* flags */ 0, 3452 }, 3453 #endif /* chips */ 3454 3455 #if defined(BCM_56560_A0) 3456 { /* SOC_FORMAT_INT_L3_IIF_SOURCE_BCM56560_A0fmt */ 3457 /* format L3_IIF_SOURCEfmt */ 3458 /* nFields */ 1, 3459 /* *fields */ soc_L3_IIF_SOURCE_BCM56560_A0fmt_fields, 3460 /* bits */ 3, 3461 /* flags */ 0, 3462 }, 3463 #endif /* chips */ 3464 3465 #if defined(BCM_56560_B0) 3466 { /* SOC_FORMAT_INT_L3_IIF_SOURCE_BCM56560_B0fmt */ 3467 /* format L3_IIF_SOURCEfmt */ 3468 /* nFields */ 1, 3469 /* *fields */ soc_L3_IIF_SOURCE_BCM56560_A0fmt_fields, 3470 /* bits */ 3, 3471 /* flags */ 0, 3472 }, 3473 #endif /* chips */ 3474 3475 #if defined(BCM_56670_A0) 3476 { /* SOC_FORMAT_INT_L3_IIF_SOURCE_BCM56670_A0fmt */ 3477 /* format L3_IIF_SOURCEfmt */ 3478 /* nFields */ 1, 3479 /* *fields */ soc_L3_IIF_SOURCE_BCM56560_A0fmt_fields, 3480 /* bits */ 3, 3481 /* flags */ 0, 3482 }, 3483 #endif /* chips */ 3484 3485 #if defined(BCM_56670_B0) 3486 { /* SOC_FORMAT_INT_L3_IIF_SOURCE_BCM56670_B0fmt */ 3487 /* format L3_IIF_SOURCEfmt */ 3488 /* nFields */ 1, 3489 /* *fields */ soc_L3_IIF_SOURCE_BCM56560_A0fmt_fields, 3490 /* bits */ 3, 3491 /* flags */ 0, 3492 }, 3493 #endif /* chips */ 3494 3495 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3496 defined(BCM_56870_A0) 3497 { /* SOC_FORMAT_INT_L3_TUNNEL_DEFAULT_VLAN_ACTION_SETfmt */ 3498 /* format L3_TUNNEL_DEFAULT_VLAN_ACTION_SETfmt */ 3499 /* nFields */ 1, 3500 /* *fields */ soc_L3_TUNNEL_DEFAULT_VLAN_ACTION_SETfmt_fields, 3501 /* bits */ 3, 3502 /* flags */ 0, 3503 }, 3504 #endif /* chips */ 3505 3506 #if defined(BCM_56840_A0) 3507 { /* SOC_FORMAT_INT_L3_TYPEfmt */ 3508 /* format L3_TYPEfmt */ 3509 /* nFields */ 1, 3510 /* *fields */ soc_FP_RESOLUTIONfmt_fields, 3511 /* bits */ 4, 3512 /* flags */ 0, 3513 }, 3514 #endif /* chips */ 3515 3516 #if defined(BCM_56260_A0) 3517 { /* SOC_FORMAT_INT_L3_TYPE_BCM56260_A0fmt */ 3518 /* format L3_TYPEfmt */ 3519 /* nFields */ 1, 3520 /* *fields */ soc_L3_TYPE_BCM56260_A0fmt_fields, 3521 /* bits */ 4, 3522 /* flags */ 0, 3523 }, 3524 #endif /* chips */ 3525 3526 #if defined(BCM_56260_B0) 3527 { /* SOC_FORMAT_INT_L3_TYPE_BCM56260_B0fmt */ 3528 /* format L3_TYPEfmt */ 3529 /* nFields */ 1, 3530 /* *fields */ soc_L3_TYPE_BCM56260_A0fmt_fields, 3531 /* bits */ 4, 3532 /* flags */ 0, 3533 }, 3534 #endif /* chips */ 3535 3536 #if defined(BCM_56270_A0) 3537 { /* SOC_FORMAT_INT_L3_TYPE_BCM56270_A0fmt */ 3538 /* format L3_TYPEfmt */ 3539 /* nFields */ 1, 3540 /* *fields */ soc_L3_TYPE_BCM56260_A0fmt_fields, 3541 /* bits */ 4, 3542 /* flags */ 0, 3543 }, 3544 #endif /* chips */ 3545 3546 #if defined(BCM_56340_A0) 3547 { /* SOC_FORMAT_INT_L3_TYPE_BCM56340_A0fmt */ 3548 /* format L3_TYPEfmt */ 3549 /* nFields */ 1, 3550 /* *fields */ soc_L3_TYPEfmt_fields, 3551 /* bits */ 4, 3552 /* flags */ 0, 3553 }, 3554 #endif /* chips */ 3555 3556 #if defined(BCM_56370_A0) 3557 { /* SOC_FORMAT_INT_L3_TYPE_BCM56370_A0fmt */ 3558 /* format L3_TYPEfmt */ 3559 /* nFields */ 1, 3560 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3561 /* bits */ 5, 3562 /* flags */ 0, 3563 }, 3564 #endif /* chips */ 3565 3566 #if defined(BCM_56440_A0) 3567 { /* SOC_FORMAT_INT_L3_TYPE_BCM56440_A0fmt */ 3568 /* format L3_TYPEfmt */ 3569 /* nFields */ 1, 3570 /* *fields */ soc_FP_RESOLUTIONfmt_fields, 3571 /* bits */ 4, 3572 /* flags */ 0, 3573 }, 3574 #endif /* chips */ 3575 3576 #if defined(BCM_56440_B0) 3577 { /* SOC_FORMAT_INT_L3_TYPE_BCM56440_B0fmt */ 3578 /* format L3_TYPEfmt */ 3579 /* nFields */ 1, 3580 /* *fields */ soc_FP_RESOLUTIONfmt_fields, 3581 /* bits */ 4, 3582 /* flags */ 0, 3583 }, 3584 #endif /* chips */ 3585 3586 #if defined(BCM_56450_A0) 3587 { /* SOC_FORMAT_INT_L3_TYPE_BCM56450_A0fmt */ 3588 /* format L3_TYPEfmt */ 3589 /* nFields */ 1, 3590 /* *fields */ soc_L3_TYPEfmt_fields, 3591 /* bits */ 4, 3592 /* flags */ 0, 3593 }, 3594 #endif /* chips */ 3595 3596 #if defined(BCM_56450_B0) 3597 { /* SOC_FORMAT_INT_L3_TYPE_BCM56450_B0fmt */ 3598 /* format L3_TYPEfmt */ 3599 /* nFields */ 1, 3600 /* *fields */ soc_L3_TYPEfmt_fields, 3601 /* bits */ 4, 3602 /* flags */ 0, 3603 }, 3604 #endif /* chips */ 3605 3606 #if defined(BCM_56450_B1) 3607 { /* SOC_FORMAT_INT_L3_TYPE_BCM56450_B1fmt */ 3608 /* format L3_TYPEfmt */ 3609 /* nFields */ 1, 3610 /* *fields */ soc_L3_TYPEfmt_fields, 3611 /* bits */ 4, 3612 /* flags */ 0, 3613 }, 3614 #endif /* chips */ 3615 3616 #if defined(BCM_56560_A0) 3617 { /* SOC_FORMAT_INT_L3_TYPE_BCM56560_A0fmt */ 3618 /* format L3_TYPEfmt */ 3619 /* nFields */ 1, 3620 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3621 /* bits */ 5, 3622 /* flags */ 0, 3623 }, 3624 #endif /* chips */ 3625 3626 #if defined(BCM_56560_B0) 3627 { /* SOC_FORMAT_INT_L3_TYPE_BCM56560_B0fmt */ 3628 /* format L3_TYPEfmt */ 3629 /* nFields */ 1, 3630 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3631 /* bits */ 5, 3632 /* flags */ 0, 3633 }, 3634 #endif /* chips */ 3635 3636 #if defined(BCM_56640_A0) 3637 { /* SOC_FORMAT_INT_L3_TYPE_BCM56640_A0fmt */ 3638 /* format L3_TYPEfmt */ 3639 /* nFields */ 1, 3640 /* *fields */ soc_L3_TYPEfmt_fields, 3641 /* bits */ 4, 3642 /* flags */ 0, 3643 }, 3644 #endif /* chips */ 3645 3646 #if defined(BCM_56670_A0) 3647 { /* SOC_FORMAT_INT_L3_TYPE_BCM56670_A0fmt */ 3648 /* format L3_TYPEfmt */ 3649 /* nFields */ 1, 3650 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3651 /* bits */ 5, 3652 /* flags */ 0, 3653 }, 3654 #endif /* chips */ 3655 3656 #if defined(BCM_56670_B0) 3657 { /* SOC_FORMAT_INT_L3_TYPE_BCM56670_B0fmt */ 3658 /* format L3_TYPEfmt */ 3659 /* nFields */ 1, 3660 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3661 /* bits */ 5, 3662 /* flags */ 0, 3663 }, 3664 #endif /* chips */ 3665 3666 #if defined(BCM_56770_A0) 3667 { /* SOC_FORMAT_INT_L3_TYPE_BCM56770_A0fmt */ 3668 /* format L3_TYPEfmt */ 3669 /* nFields */ 1, 3670 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3671 /* bits */ 5, 3672 /* flags */ 0, 3673 }, 3674 #endif /* chips */ 3675 3676 #if defined(BCM_56840_B0) 3677 { /* SOC_FORMAT_INT_L3_TYPE_BCM56840_B0fmt */ 3678 /* format L3_TYPEfmt */ 3679 /* nFields */ 1, 3680 /* *fields */ soc_FP_RESOLUTIONfmt_fields, 3681 /* bits */ 4, 3682 /* flags */ 0, 3683 }, 3684 #endif /* chips */ 3685 3686 #if defined(BCM_56850_A0) 3687 { /* SOC_FORMAT_INT_L3_TYPE_BCM56850_A0fmt */ 3688 /* format L3_TYPEfmt */ 3689 /* nFields */ 1, 3690 /* *fields */ soc_TUNNEL_TYPE_LOOPBACK_TYPEfmt_fields, 3691 /* bits */ 5, 3692 /* flags */ 0, 3693 }, 3694 #endif /* chips */ 3695 3696 #if defined(BCM_56860_A0) 3697 { /* SOC_FORMAT_INT_L3_TYPE_BCM56860_A0fmt */ 3698 /* format L3_TYPEfmt */ 3699 /* nFields */ 1, 3700 /* *fields */ soc_TUNNEL_TYPE_LOOPBACK_TYPEfmt_fields, 3701 /* bits */ 5, 3702 /* flags */ 0, 3703 }, 3704 #endif /* chips */ 3705 3706 #if defined(BCM_56870_A0) 3707 { /* SOC_FORMAT_INT_L3_TYPE_BCM56870_A0fmt */ 3708 /* format L3_TYPEfmt */ 3709 /* nFields */ 1, 3710 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3711 /* bits */ 5, 3712 /* flags */ 0, 3713 }, 3714 #endif /* chips */ 3715 3716 #if defined(BCM_56960_A0) 3717 { /* SOC_FORMAT_INT_L3_TYPE_BCM56960_A0fmt */ 3718 /* format L3_TYPEfmt */ 3719 /* nFields */ 1, 3720 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3721 /* bits */ 5, 3722 /* flags */ 0, 3723 }, 3724 #endif /* chips */ 3725 3726 #if defined(BCM_56965_A0) 3727 { /* SOC_FORMAT_INT_L3_TYPE_BCM56965_A0fmt */ 3728 /* format L3_TYPEfmt */ 3729 /* nFields */ 1, 3730 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3731 /* bits */ 5, 3732 /* flags */ 0, 3733 }, 3734 #endif /* chips */ 3735 3736 #if defined(BCM_56970_A0) 3737 { /* SOC_FORMAT_INT_L3_TYPE_BCM56970_A0fmt */ 3738 /* format L3_TYPEfmt */ 3739 /* nFields */ 1, 3740 /* *fields */ soc_FP_RESOLUTION_BCM53400_A0fmt_fields, 3741 /* bits */ 5, 3742 /* flags */ 0, 3743 }, 3744 #endif /* chips */ 3745 3746 #if defined(BCM_56980_A0) 3747 { /* SOC_FORMAT_INT_L3_TYPE_BCM56980_A0fmt */ 3748 /* format L3_TYPEfmt */ 3749 /* nFields */ 1, 3750 /* *fields */ soc_L3_TYPE_BCM56260_A0fmt_fields, 3751 /* bits */ 4, 3752 /* flags */ 0, 3753 }, 3754 #endif /* chips */ 3755 3756 #if defined(BCM_56980_B0) 3757 { /* SOC_FORMAT_INT_L3_TYPE_BCM56980_B0fmt */ 3758 /* format L3_TYPEfmt */ 3759 /* nFields */ 1, 3760 /* *fields */ soc_L3_TYPE_BCM56260_A0fmt_fields, 3761 /* bits */ 4, 3762 /* flags */ 0, 3763 }, 3764 #endif /* chips */ 3765 3766 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 3767 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 3768 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 3769 defined(BCM_56850_A0) || defined(BCM_56860_A0) 3770 { /* SOC_FORMAT_INT_L4_PORTfmt */ 3771 /* format L4_PORTfmt */ 3772 /* nFields */ 1, 3773 /* *fields */ soc_L4_PORTfmt_fields, 3774 /* bits */ 16, 3775 /* flags */ 0, 3776 }, 3777 #endif /* chips */ 3778 3779 #if defined(BCM_53400_A0) 3780 { /* SOC_FORMAT_INT_L4_PORT_BCM53400_A0fmt */ 3781 /* format L4_PORTfmt */ 3782 /* nFields */ 1, 3783 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3784 /* bits */ 16, 3785 /* flags */ 0, 3786 }, 3787 #endif /* chips */ 3788 3789 #if defined(BCM_53540_A0) 3790 { /* SOC_FORMAT_INT_L4_PORT_BCM53540_A0fmt */ 3791 /* format L4_PORTfmt */ 3792 /* nFields */ 1, 3793 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3794 /* bits */ 16, 3795 /* flags */ 0, 3796 }, 3797 #endif /* chips */ 3798 3799 #if defined(BCM_53570_A0) 3800 { /* SOC_FORMAT_INT_L4_PORT_BCM53570_A0fmt */ 3801 /* format L4_PORTfmt */ 3802 /* nFields */ 1, 3803 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3804 /* bits */ 16, 3805 /* flags */ 0, 3806 }, 3807 #endif /* chips */ 3808 3809 #if defined(BCM_53570_B0) 3810 { /* SOC_FORMAT_INT_L4_PORT_BCM53570_B0fmt */ 3811 /* format L4_PORTfmt */ 3812 /* nFields */ 1, 3813 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3814 /* bits */ 16, 3815 /* flags */ 0, 3816 }, 3817 #endif /* chips */ 3818 3819 #if defined(BCM_56160_A0) 3820 { /* SOC_FORMAT_INT_L4_PORT_BCM56160_A0fmt */ 3821 /* format L4_PORTfmt */ 3822 /* nFields */ 1, 3823 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3824 /* bits */ 16, 3825 /* flags */ 0, 3826 }, 3827 #endif /* chips */ 3828 3829 #if defined(BCM_56260_A0) 3830 { /* SOC_FORMAT_INT_L4_PORT_BCM56260_A0fmt */ 3831 /* format L4_PORTfmt */ 3832 /* nFields */ 1, 3833 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3834 /* bits */ 16, 3835 /* flags */ 0, 3836 }, 3837 #endif /* chips */ 3838 3839 #if defined(BCM_56260_B0) 3840 { /* SOC_FORMAT_INT_L4_PORT_BCM56260_B0fmt */ 3841 /* format L4_PORTfmt */ 3842 /* nFields */ 1, 3843 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3844 /* bits */ 16, 3845 /* flags */ 0, 3846 }, 3847 #endif /* chips */ 3848 3849 #if defined(BCM_56270_A0) 3850 { /* SOC_FORMAT_INT_L4_PORT_BCM56270_A0fmt */ 3851 /* format L4_PORTfmt */ 3852 /* nFields */ 1, 3853 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3854 /* bits */ 16, 3855 /* flags */ 0, 3856 }, 3857 #endif /* chips */ 3858 3859 #if defined(BCM_56370_A0) 3860 { /* SOC_FORMAT_INT_L4_PORT_BCM56370_A0fmt */ 3861 /* format L4_PORTfmt */ 3862 /* nFields */ 1, 3863 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3864 /* bits */ 16, 3865 /* flags */ 0, 3866 }, 3867 #endif /* chips */ 3868 3869 #if defined(BCM_56560_A0) 3870 { /* SOC_FORMAT_INT_L4_PORT_BCM56560_A0fmt */ 3871 /* format L4_PORTfmt */ 3872 /* nFields */ 1, 3873 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3874 /* bits */ 16, 3875 /* flags */ 0, 3876 }, 3877 #endif /* chips */ 3878 3879 #if defined(BCM_56560_B0) 3880 { /* SOC_FORMAT_INT_L4_PORT_BCM56560_B0fmt */ 3881 /* format L4_PORTfmt */ 3882 /* nFields */ 1, 3883 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3884 /* bits */ 16, 3885 /* flags */ 0, 3886 }, 3887 #endif /* chips */ 3888 3889 #if defined(BCM_56670_A0) 3890 { /* SOC_FORMAT_INT_L4_PORT_BCM56670_A0fmt */ 3891 /* format L4_PORTfmt */ 3892 /* nFields */ 1, 3893 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3894 /* bits */ 16, 3895 /* flags */ 0, 3896 }, 3897 #endif /* chips */ 3898 3899 #if defined(BCM_56670_B0) 3900 { /* SOC_FORMAT_INT_L4_PORT_BCM56670_B0fmt */ 3901 /* format L4_PORTfmt */ 3902 /* nFields */ 1, 3903 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3904 /* bits */ 16, 3905 /* flags */ 0, 3906 }, 3907 #endif /* chips */ 3908 3909 #if defined(BCM_56770_A0) 3910 { /* SOC_FORMAT_INT_L4_PORT_BCM56770_A0fmt */ 3911 /* format L4_PORTfmt */ 3912 /* nFields */ 1, 3913 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3914 /* bits */ 16, 3915 /* flags */ 0, 3916 }, 3917 #endif /* chips */ 3918 3919 #if defined(BCM_56870_A0) 3920 { /* SOC_FORMAT_INT_L4_PORT_BCM56870_A0fmt */ 3921 /* format L4_PORTfmt */ 3922 /* nFields */ 1, 3923 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3924 /* bits */ 16, 3925 /* flags */ 0, 3926 }, 3927 #endif /* chips */ 3928 3929 #if defined(BCM_56960_A0) 3930 { /* SOC_FORMAT_INT_L4_PORT_BCM56960_A0fmt */ 3931 /* format L4_PORTfmt */ 3932 /* nFields */ 1, 3933 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3934 /* bits */ 16, 3935 /* flags */ 0, 3936 }, 3937 #endif /* chips */ 3938 3939 #if defined(BCM_56965_A0) 3940 { /* SOC_FORMAT_INT_L4_PORT_BCM56965_A0fmt */ 3941 /* format L4_PORTfmt */ 3942 /* nFields */ 1, 3943 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3944 /* bits */ 16, 3945 /* flags */ 0, 3946 }, 3947 #endif /* chips */ 3948 3949 #if defined(BCM_56970_A0) 3950 { /* SOC_FORMAT_INT_L4_PORT_BCM56970_A0fmt */ 3951 /* format L4_PORTfmt */ 3952 /* nFields */ 1, 3953 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3954 /* bits */ 16, 3955 /* flags */ 0, 3956 }, 3957 #endif /* chips */ 3958 3959 #if defined(BCM_56980_A0) 3960 { /* SOC_FORMAT_INT_L4_PORT_BCM56980_A0fmt */ 3961 /* format L4_PORTfmt */ 3962 /* nFields */ 1, 3963 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3964 /* bits */ 16, 3965 /* flags */ 0, 3966 }, 3967 #endif /* chips */ 3968 3969 #if defined(BCM_56980_B0) 3970 { /* SOC_FORMAT_INT_L4_PORT_BCM56980_B0fmt */ 3971 /* format L4_PORTfmt */ 3972 /* nFields */ 1, 3973 /* *fields */ soc_L4_PORT_BCM53400_A0fmt_fields, 3974 /* bits */ 16, 3975 /* flags */ 0, 3976 }, 3977 #endif /* chips */ 3978 3979 #if defined(BCM_56870_A0) 3980 { /* SOC_FORMAT_INT_LAG_RH_ACTION_SETfmt */ 3981 /* format LAG_RH_ACTION_SETfmt */ 3982 /* nFields */ 2, 3983 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 3984 /* bits */ 2, 3985 /* flags */ 0, 3986 }, 3987 #endif /* chips */ 3988 3989 #if defined(BCM_56370_A0) 3990 { /* SOC_FORMAT_INT_LAG_RH_ACTION_SET_BCM56370_A0fmt */ 3991 /* format LAG_RH_ACTION_SETfmt */ 3992 /* nFields */ 2, 3993 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 3994 /* bits */ 2, 3995 /* flags */ 0, 3996 }, 3997 #endif /* chips */ 3998 3999 #if defined(BCM_56770_A0) 4000 { /* SOC_FORMAT_INT_LAG_RH_ACTION_SET_BCM56770_A0fmt */ 4001 /* format LAG_RH_ACTION_SETfmt */ 4002 /* nFields */ 2, 4003 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 4004 /* bits */ 2, 4005 /* flags */ 0, 4006 }, 4007 #endif /* chips */ 4008 4009 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 4010 defined(BCM_56634_A0) || defined(BCM_56685_A0) || \ 4011 defined(BCM_56685_B0) 4012 { /* SOC_FORMAT_INT_LB_MH_BASEfmt */ 4013 /* format LB_MH_BASEfmt */ 4014 /* nFields */ 6, 4015 /* *fields */ soc_LB_MH_BASEfmt_fields, 4016 /* bits */ 128, 4017 /* flags */ 0, 4018 }, 4019 #endif /* chips */ 4020 4021 #if defined(BCM_53400_A0) 4022 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM53400_A0fmt */ 4023 /* format LB_MH_BASEfmt */ 4024 /* nFields */ 6, 4025 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4026 /* bits */ 128, 4027 /* flags */ 0, 4028 }, 4029 #endif /* chips */ 4030 4031 #if defined(BCM_53540_A0) 4032 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM53540_A0fmt */ 4033 /* format LB_MH_BASEfmt */ 4034 /* nFields */ 6, 4035 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4036 /* bits */ 128, 4037 /* flags */ 0, 4038 }, 4039 #endif /* chips */ 4040 4041 #if defined(BCM_53570_A0) 4042 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM53570_A0fmt */ 4043 /* format LB_MH_BASEfmt */ 4044 /* nFields */ 6, 4045 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4046 /* bits */ 128, 4047 /* flags */ 0, 4048 }, 4049 #endif /* chips */ 4050 4051 #if defined(BCM_53570_B0) 4052 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM53570_B0fmt */ 4053 /* format LB_MH_BASEfmt */ 4054 /* nFields */ 6, 4055 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4056 /* bits */ 128, 4057 /* flags */ 0, 4058 }, 4059 #endif /* chips */ 4060 4061 #if defined(BCM_56142_A0) 4062 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM56142_A0fmt */ 4063 /* format LB_MH_BASEfmt */ 4064 /* nFields */ 6, 4065 /* *fields */ soc_LB_MH_BASEfmt_fields, 4066 /* bits */ 128, 4067 /* flags */ 0, 4068 }, 4069 #endif /* chips */ 4070 4071 #if defined(BCM_56150_A0) 4072 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM56150_A0fmt */ 4073 /* format LB_MH_BASEfmt */ 4074 /* nFields */ 6, 4075 /* *fields */ soc_LB_MH_BASE_BCM56150_A0fmt_fields, 4076 /* bits */ 128, 4077 /* flags */ 0, 4078 }, 4079 #endif /* chips */ 4080 4081 #if defined(BCM_56160_A0) 4082 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM56160_A0fmt */ 4083 /* format LB_MH_BASEfmt */ 4084 /* nFields */ 6, 4085 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4086 /* bits */ 128, 4087 /* flags */ 0, 4088 }, 4089 #endif /* chips */ 4090 4091 #if defined(BCM_56334_A0) 4092 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM56334_A0fmt */ 4093 /* format LB_MH_BASEfmt */ 4094 /* nFields */ 6, 4095 /* *fields */ soc_LB_MH_BASEfmt_fields, 4096 /* bits */ 128, 4097 /* flags */ 0, 4098 }, 4099 #endif /* chips */ 4100 4101 #if defined(BCM_56334_B0) 4102 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM56334_B0fmt */ 4103 /* format LB_MH_BASEfmt */ 4104 /* nFields */ 6, 4105 /* *fields */ soc_LB_MH_BASEfmt_fields, 4106 /* bits */ 128, 4107 /* flags */ 0, 4108 }, 4109 #endif /* chips */ 4110 4111 #if defined(BCM_56634_B0) 4112 { /* SOC_FORMAT_INT_LB_MH_BASE_BCM56634_B0fmt */ 4113 /* format LB_MH_BASEfmt */ 4114 /* nFields */ 6, 4115 /* *fields */ soc_LB_MH_BASEfmt_fields, 4116 /* bits */ 128, 4117 /* flags */ 0, 4118 }, 4119 #endif /* chips */ 4120 4121 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 4122 defined(BCM_56685_A0) || defined(BCM_56685_B0) 4123 { /* SOC_FORMAT_INT_LB_MH_EP_REDIRECTfmt */ 4124 /* format LB_MH_EP_REDIRECTfmt */ 4125 /* nFields */ 13, 4126 /* *fields */ soc_LB_MH_EP_REDIRECTfmt_fields, 4127 /* bits */ 128, 4128 /* flags */ 0, 4129 }, 4130 #endif /* chips */ 4131 4132 #if defined(BCM_56524_B0) 4133 { /* SOC_FORMAT_INT_LB_MH_EP_REDIRECT_BCM56524_B0fmt */ 4134 /* format LB_MH_EP_REDIRECTfmt */ 4135 /* nFields */ 13, 4136 /* *fields */ soc_LB_MH_EP_REDIRECTfmt_fields, 4137 /* bits */ 128, 4138 /* flags */ 0, 4139 }, 4140 #endif /* chips */ 4141 4142 #if defined(BCM_56634_B0) 4143 { /* SOC_FORMAT_INT_LB_MH_EP_REDIRECT_BCM56634_B0fmt */ 4144 /* format LB_MH_EP_REDIRECTfmt */ 4145 /* nFields */ 13, 4146 /* *fields */ soc_LB_MH_EP_REDIRECTfmt_fields, 4147 /* bits */ 128, 4148 /* flags */ 0, 4149 }, 4150 #endif /* chips */ 4151 4152 #if defined(BCM_56634_A0) 4153 { /* SOC_FORMAT_INT_LB_MH_MIMfmt */ 4154 /* format LB_MH_MIMfmt */ 4155 /* nFields */ 6, 4156 /* *fields */ soc_LB_MH_BASEfmt_fields, 4157 /* bits */ 128, 4158 /* flags */ 0, 4159 }, 4160 #endif /* chips */ 4161 4162 #if defined(BCM_53400_A0) 4163 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM53400_A0fmt */ 4164 /* format LB_MH_MIMfmt */ 4165 /* nFields */ 6, 4166 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4167 /* bits */ 128, 4168 /* flags */ 0, 4169 }, 4170 #endif /* chips */ 4171 4172 #if defined(BCM_53540_A0) 4173 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM53540_A0fmt */ 4174 /* format LB_MH_MIMfmt */ 4175 /* nFields */ 6, 4176 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4177 /* bits */ 128, 4178 /* flags */ 0, 4179 }, 4180 #endif /* chips */ 4181 4182 #if defined(BCM_53570_A0) 4183 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM53570_A0fmt */ 4184 /* format LB_MH_MIMfmt */ 4185 /* nFields */ 6, 4186 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4187 /* bits */ 128, 4188 /* flags */ 0, 4189 }, 4190 #endif /* chips */ 4191 4192 #if defined(BCM_53570_B0) 4193 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM53570_B0fmt */ 4194 /* format LB_MH_MIMfmt */ 4195 /* nFields */ 6, 4196 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4197 /* bits */ 128, 4198 /* flags */ 0, 4199 }, 4200 #endif /* chips */ 4201 4202 #if defined(BCM_56142_A0) 4203 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56142_A0fmt */ 4204 /* format LB_MH_MIMfmt */ 4205 /* nFields */ 6, 4206 /* *fields */ soc_LB_MH_BASEfmt_fields, 4207 /* bits */ 128, 4208 /* flags */ 0, 4209 }, 4210 #endif /* chips */ 4211 4212 #if defined(BCM_56150_A0) 4213 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56150_A0fmt */ 4214 /* format LB_MH_MIMfmt */ 4215 /* nFields */ 6, 4216 /* *fields */ soc_LB_MH_BASE_BCM56150_A0fmt_fields, 4217 /* bits */ 128, 4218 /* flags */ 0, 4219 }, 4220 #endif /* chips */ 4221 4222 #if defined(BCM_56160_A0) 4223 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56160_A0fmt */ 4224 /* format LB_MH_MIMfmt */ 4225 /* nFields */ 6, 4226 /* *fields */ soc_LB_MH_BASE_BCM53400_A0fmt_fields, 4227 /* bits */ 128, 4228 /* flags */ 0, 4229 }, 4230 #endif /* chips */ 4231 4232 #if defined(BCM_56334_A0) 4233 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56334_A0fmt */ 4234 /* format LB_MH_MIMfmt */ 4235 /* nFields */ 6, 4236 /* *fields */ soc_LB_MH_BASEfmt_fields, 4237 /* bits */ 128, 4238 /* flags */ 0, 4239 }, 4240 #endif /* chips */ 4241 4242 #if defined(BCM_56334_B0) 4243 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56334_B0fmt */ 4244 /* format LB_MH_MIMfmt */ 4245 /* nFields */ 6, 4246 /* *fields */ soc_LB_MH_BASEfmt_fields, 4247 /* bits */ 128, 4248 /* flags */ 0, 4249 }, 4250 #endif /* chips */ 4251 4252 #if defined(BCM_56524_A0) 4253 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56524_A0fmt */ 4254 /* format LB_MH_MIMfmt */ 4255 /* nFields */ 6, 4256 /* *fields */ soc_LB_MH_BASEfmt_fields, 4257 /* bits */ 128, 4258 /* flags */ 0, 4259 }, 4260 #endif /* chips */ 4261 4262 #if defined(BCM_56524_B0) 4263 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56524_B0fmt */ 4264 /* format LB_MH_MIMfmt */ 4265 /* nFields */ 6, 4266 /* *fields */ soc_LB_MH_BASEfmt_fields, 4267 /* bits */ 128, 4268 /* flags */ 0, 4269 }, 4270 #endif /* chips */ 4271 4272 #if defined(BCM_56634_B0) 4273 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56634_B0fmt */ 4274 /* format LB_MH_MIMfmt */ 4275 /* nFields */ 6, 4276 /* *fields */ soc_LB_MH_BASEfmt_fields, 4277 /* bits */ 128, 4278 /* flags */ 0, 4279 }, 4280 #endif /* chips */ 4281 4282 #if defined(BCM_56685_A0) 4283 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56685_A0fmt */ 4284 /* format LB_MH_MIMfmt */ 4285 /* nFields */ 6, 4286 /* *fields */ soc_LB_MH_BASEfmt_fields, 4287 /* bits */ 128, 4288 /* flags */ 0, 4289 }, 4290 #endif /* chips */ 4291 4292 #if defined(BCM_56685_B0) 4293 { /* SOC_FORMAT_INT_LB_MH_MIM_BCM56685_B0fmt */ 4294 /* format LB_MH_MIMfmt */ 4295 /* nFields */ 6, 4296 /* *fields */ soc_LB_MH_BASEfmt_fields, 4297 /* bits */ 128, 4298 /* flags */ 0, 4299 }, 4300 #endif /* chips */ 4301 4302 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 4303 defined(BCM_56634_B0) || defined(BCM_56685_A0) || \ 4304 defined(BCM_56685_B0) 4305 { /* SOC_FORMAT_INT_LB_MH_WLANfmt */ 4306 /* format LB_MH_WLANfmt */ 4307 /* nFields */ 17, 4308 /* *fields */ soc_LB_MH_WLANfmt_fields, 4309 /* bits */ 128, 4310 /* flags */ 0, 4311 }, 4312 #endif /* chips */ 4313 4314 #if defined(BCM_56524_B0) 4315 { /* SOC_FORMAT_INT_LB_MH_WLAN_BCM56524_B0fmt */ 4316 /* format LB_MH_WLANfmt */ 4317 /* nFields */ 17, 4318 /* *fields */ soc_LB_MH_WLANfmt_fields, 4319 /* bits */ 128, 4320 /* flags */ 0, 4321 }, 4322 #endif /* chips */ 4323 4324 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 4325 defined(BCM_56504_B0) || defined(BCM_56514_A0) 4326 { /* SOC_FORMAT_INT_LEARN_BUSfmt */ 4327 /* format LEARN_BUSfmt */ 4328 /* nFields */ 8, 4329 /* *fields */ soc_LEARN_BUSfmt_fields, 4330 /* bits */ 80, 4331 /* flags */ 0, 4332 }, 4333 #endif /* chips */ 4334 4335 #if defined(BCM_53314_A0) 4336 { /* SOC_FORMAT_INT_LEARN_BUS_BCM53314_A0fmt */ 4337 /* format LEARN_BUSfmt */ 4338 /* nFields */ 8, 4339 /* *fields */ soc_LEARN_BUS_BCM56224_A0fmt_fields, 4340 /* bits */ 80, 4341 /* flags */ 0, 4342 }, 4343 #endif /* chips */ 4344 4345 #if defined(BCM_53324_A0) 4346 { /* SOC_FORMAT_INT_LEARN_BUS_BCM53324_A0fmt */ 4347 /* format LEARN_BUSfmt */ 4348 /* nFields */ 8, 4349 /* *fields */ soc_LEARN_BUS_BCM56224_A0fmt_fields, 4350 /* bits */ 80, 4351 /* flags */ 0, 4352 }, 4353 #endif /* chips */ 4354 4355 #if defined(BCM_53400_A0) 4356 { /* SOC_FORMAT_INT_LEARN_BUS_BCM53400_A0fmt */ 4357 /* format LEARN_BUSfmt */ 4358 /* nFields */ 14, 4359 /* *fields */ soc_LEARN_BUS_BCM53400_A0fmt_fields, 4360 /* bits */ 90, 4361 /* flags */ 0, 4362 }, 4363 #endif /* chips */ 4364 4365 #if defined(BCM_53540_A0) 4366 { /* SOC_FORMAT_INT_LEARN_BUS_BCM53540_A0fmt */ 4367 /* format LEARN_BUSfmt */ 4368 /* nFields */ 14, 4369 /* *fields */ soc_LEARN_BUS_BCM56160_A0fmt_fields, 4370 /* bits */ 91, 4371 /* flags */ 0, 4372 }, 4373 #endif /* chips */ 4374 4375 #if defined(BCM_53570_A0) 4376 { /* SOC_FORMAT_INT_LEARN_BUS_BCM53570_A0fmt */ 4377 /* format LEARN_BUSfmt */ 4378 /* nFields */ 27, 4379 /* *fields */ soc_LEARN_BUS_BCM53570_A0fmt_fields, 4380 /* bits */ 151, 4381 /* flags */ 0, 4382 }, 4383 #endif /* chips */ 4384 4385 #if defined(BCM_53570_B0) 4386 { /* SOC_FORMAT_INT_LEARN_BUS_BCM53570_B0fmt */ 4387 /* format LEARN_BUSfmt */ 4388 /* nFields */ 30, 4389 /* *fields */ soc_LEARN_BUS_BCM53570_B0fmt_fields, 4390 /* bits */ 153, 4391 /* flags */ 0, 4392 }, 4393 #endif /* chips */ 4394 4395 #if defined(BCM_56142_A0) 4396 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56142_A0fmt */ 4397 /* format LEARN_BUSfmt */ 4398 /* nFields */ 14, 4399 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4400 /* bits */ 89, 4401 /* flags */ 0, 4402 }, 4403 #endif /* chips */ 4404 4405 #if defined(BCM_56150_A0) 4406 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56150_A0fmt */ 4407 /* format LEARN_BUSfmt */ 4408 /* nFields */ 14, 4409 /* *fields */ soc_LEARN_BUS_BCM56150_A0fmt_fields, 4410 /* bits */ 89, 4411 /* flags */ 0, 4412 }, 4413 #endif /* chips */ 4414 4415 #if defined(BCM_56160_A0) 4416 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56160_A0fmt */ 4417 /* format LEARN_BUSfmt */ 4418 /* nFields */ 14, 4419 /* *fields */ soc_LEARN_BUS_BCM56160_A0fmt_fields, 4420 /* bits */ 91, 4421 /* flags */ 0, 4422 }, 4423 #endif /* chips */ 4424 4425 #if defined(BCM_56224_A0) 4426 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56224_A0fmt */ 4427 /* format LEARN_BUSfmt */ 4428 /* nFields */ 8, 4429 /* *fields */ soc_LEARN_BUS_BCM56224_A0fmt_fields, 4430 /* bits */ 80, 4431 /* flags */ 0, 4432 }, 4433 #endif /* chips */ 4434 4435 #if defined(BCM_56224_B0) 4436 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56224_B0fmt */ 4437 /* format LEARN_BUSfmt */ 4438 /* nFields */ 8, 4439 /* *fields */ soc_LEARN_BUS_BCM56224_A0fmt_fields, 4440 /* bits */ 80, 4441 /* flags */ 0, 4442 }, 4443 #endif /* chips */ 4444 4445 #if defined(BCM_56260_A0) 4446 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56260_A0fmt */ 4447 /* format LEARN_BUSfmt */ 4448 /* nFields */ 18, 4449 /* *fields */ soc_LEARN_BUS_BCM56260_A0fmt_fields, 4450 /* bits */ 105, 4451 /* flags */ 0, 4452 }, 4453 #endif /* chips */ 4454 4455 #if defined(BCM_56260_B0) 4456 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56260_B0fmt */ 4457 /* format LEARN_BUSfmt */ 4458 /* nFields */ 18, 4459 /* *fields */ soc_LEARN_BUS_BCM56260_A0fmt_fields, 4460 /* bits */ 105, 4461 /* flags */ 0, 4462 }, 4463 #endif /* chips */ 4464 4465 #if defined(BCM_56270_A0) 4466 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56270_A0fmt */ 4467 /* format LEARN_BUSfmt */ 4468 /* nFields */ 18, 4469 /* *fields */ soc_LEARN_BUS_BCM56260_A0fmt_fields, 4470 /* bits */ 105, 4471 /* flags */ 0, 4472 }, 4473 #endif /* chips */ 4474 4475 #if defined(BCM_56334_A0) 4476 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56334_A0fmt */ 4477 /* format LEARN_BUSfmt */ 4478 /* nFields */ 14, 4479 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4480 /* bits */ 89, 4481 /* flags */ 0, 4482 }, 4483 #endif /* chips */ 4484 4485 #if defined(BCM_56334_B0) 4486 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56334_B0fmt */ 4487 /* format LEARN_BUSfmt */ 4488 /* nFields */ 14, 4489 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4490 /* bits */ 89, 4491 /* flags */ 0, 4492 }, 4493 #endif /* chips */ 4494 4495 #if defined(BCM_56440_A0) 4496 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56440_A0fmt */ 4497 /* format LEARN_BUSfmt */ 4498 /* nFields */ 15, 4499 /* *fields */ soc_LEARN_BUS_BCM56440_A0fmt_fields, 4500 /* bits */ 92, 4501 /* flags */ 0, 4502 }, 4503 #endif /* chips */ 4504 4505 #if defined(BCM_56440_B0) 4506 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56440_B0fmt */ 4507 /* format LEARN_BUSfmt */ 4508 /* nFields */ 15, 4509 /* *fields */ soc_LEARN_BUS_BCM56440_A0fmt_fields, 4510 /* bits */ 92, 4511 /* flags */ 0, 4512 }, 4513 #endif /* chips */ 4514 4515 #if defined(BCM_56450_A0) 4516 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56450_A0fmt */ 4517 /* format LEARN_BUSfmt */ 4518 /* nFields */ 19, 4519 /* *fields */ soc_LEARN_BUS_BCM56450_A0fmt_fields, 4520 /* bits */ 110, 4521 /* flags */ 0, 4522 }, 4523 #endif /* chips */ 4524 4525 #if defined(BCM_56450_B0) 4526 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56450_B0fmt */ 4527 /* format LEARN_BUSfmt */ 4528 /* nFields */ 19, 4529 /* *fields */ soc_LEARN_BUS_BCM56450_A0fmt_fields, 4530 /* bits */ 110, 4531 /* flags */ 0, 4532 }, 4533 #endif /* chips */ 4534 4535 #if defined(BCM_56450_B1) 4536 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56450_B1fmt */ 4537 /* format LEARN_BUSfmt */ 4538 /* nFields */ 19, 4539 /* *fields */ soc_LEARN_BUS_BCM56450_A0fmt_fields, 4540 /* bits */ 110, 4541 /* flags */ 0, 4542 }, 4543 #endif /* chips */ 4544 4545 #if defined(BCM_56524_A0) 4546 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56524_A0fmt */ 4547 /* format LEARN_BUSfmt */ 4548 /* nFields */ 14, 4549 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4550 /* bits */ 89, 4551 /* flags */ 0, 4552 }, 4553 #endif /* chips */ 4554 4555 #if defined(BCM_56524_B0) 4556 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56524_B0fmt */ 4557 /* format LEARN_BUSfmt */ 4558 /* nFields */ 14, 4559 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4560 /* bits */ 89, 4561 /* flags */ 0, 4562 }, 4563 #endif /* chips */ 4564 4565 #if defined(BCM_56560_A0) 4566 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56560_A0fmt */ 4567 /* format LEARN_BUSfmt */ 4568 /* nFields */ 17, 4569 /* *fields */ soc_LEARN_BUS_BCM56560_A0fmt_fields, 4570 /* bits */ 93, 4571 /* flags */ 0, 4572 }, 4573 #endif /* chips */ 4574 4575 #if defined(BCM_56560_B0) 4576 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56560_B0fmt */ 4577 /* format LEARN_BUSfmt */ 4578 /* nFields */ 17, 4579 /* *fields */ soc_LEARN_BUS_BCM56560_A0fmt_fields, 4580 /* bits */ 93, 4581 /* flags */ 0, 4582 }, 4583 #endif /* chips */ 4584 4585 #if defined(BCM_56624_A0) 4586 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56624_A0fmt */ 4587 /* format LEARN_BUSfmt */ 4588 /* nFields */ 14, 4589 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4590 /* bits */ 89, 4591 /* flags */ 0, 4592 }, 4593 #endif /* chips */ 4594 4595 #if defined(BCM_56624_B0) 4596 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56624_B0fmt */ 4597 /* format LEARN_BUSfmt */ 4598 /* nFields */ 14, 4599 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4600 /* bits */ 89, 4601 /* flags */ 0, 4602 }, 4603 #endif /* chips */ 4604 4605 #if defined(BCM_56634_A0) 4606 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56634_A0fmt */ 4607 /* format LEARN_BUSfmt */ 4608 /* nFields */ 14, 4609 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4610 /* bits */ 89, 4611 /* flags */ 0, 4612 }, 4613 #endif /* chips */ 4614 4615 #if defined(BCM_56634_B0) 4616 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56634_B0fmt */ 4617 /* format LEARN_BUSfmt */ 4618 /* nFields */ 14, 4619 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4620 /* bits */ 89, 4621 /* flags */ 0, 4622 }, 4623 #endif /* chips */ 4624 4625 #if defined(BCM_56670_A0) 4626 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56670_A0fmt */ 4627 /* format LEARN_BUSfmt */ 4628 /* nFields */ 18, 4629 /* *fields */ soc_LEARN_BUS_BCM56670_A0fmt_fields, 4630 /* bits */ 93, 4631 /* flags */ 0, 4632 }, 4633 #endif /* chips */ 4634 4635 #if defined(BCM_56670_B0) 4636 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56670_B0fmt */ 4637 /* format LEARN_BUSfmt */ 4638 /* nFields */ 18, 4639 /* *fields */ soc_LEARN_BUS_BCM56670_A0fmt_fields, 4640 /* bits */ 93, 4641 /* flags */ 0, 4642 }, 4643 #endif /* chips */ 4644 4645 #if defined(BCM_56680_A0) 4646 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56680_A0fmt */ 4647 /* format LEARN_BUSfmt */ 4648 /* nFields */ 14, 4649 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4650 /* bits */ 89, 4651 /* flags */ 0, 4652 }, 4653 #endif /* chips */ 4654 4655 #if defined(BCM_56680_B0) 4656 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56680_B0fmt */ 4657 /* format LEARN_BUSfmt */ 4658 /* nFields */ 14, 4659 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4660 /* bits */ 89, 4661 /* flags */ 0, 4662 }, 4663 #endif /* chips */ 4664 4665 #if defined(BCM_56685_A0) 4666 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56685_A0fmt */ 4667 /* format LEARN_BUSfmt */ 4668 /* nFields */ 14, 4669 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4670 /* bits */ 89, 4671 /* flags */ 0, 4672 }, 4673 #endif /* chips */ 4674 4675 #if defined(BCM_56685_B0) 4676 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56685_B0fmt */ 4677 /* format LEARN_BUSfmt */ 4678 /* nFields */ 14, 4679 /* *fields */ soc_LEARN_BUS_BCM56624_A0fmt_fields, 4680 /* bits */ 89, 4681 /* flags */ 0, 4682 }, 4683 #endif /* chips */ 4684 4685 #if defined(BCM_56725_A0) 4686 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56725_A0fmt */ 4687 /* format LEARN_BUSfmt */ 4688 /* nFields */ 14, 4689 /* *fields */ soc_LEARN_BUS_BCM56820_A0fmt_fields, 4690 /* bits */ 89, 4691 /* flags */ 0, 4692 }, 4693 #endif /* chips */ 4694 4695 #if defined(BCM_56800_A0) 4696 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56800_A0fmt */ 4697 /* format LEARN_BUSfmt */ 4698 /* nFields */ 8, 4699 /* *fields */ soc_LEARN_BUS_BCM56800_A0fmt_fields, 4700 /* bits */ 81, 4701 /* flags */ 0, 4702 }, 4703 #endif /* chips */ 4704 4705 #if defined(BCM_56820_A0) 4706 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56820_A0fmt */ 4707 /* format LEARN_BUSfmt */ 4708 /* nFields */ 14, 4709 /* *fields */ soc_LEARN_BUS_BCM56820_A0fmt_fields, 4710 /* bits */ 89, 4711 /* flags */ 0, 4712 }, 4713 #endif /* chips */ 4714 4715 #if defined(BCM_56840_A0) 4716 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56840_A0fmt */ 4717 /* format LEARN_BUSfmt */ 4718 /* nFields */ 13, 4719 /* *fields */ soc_LEARN_BUS_BCM56840_A0fmt_fields, 4720 /* bits */ 91, 4721 /* flags */ 0, 4722 }, 4723 #endif /* chips */ 4724 4725 #if defined(BCM_56840_B0) 4726 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56840_B0fmt */ 4727 /* format LEARN_BUSfmt */ 4728 /* nFields */ 13, 4729 /* *fields */ soc_LEARN_BUS_BCM56840_A0fmt_fields, 4730 /* bits */ 91, 4731 /* flags */ 0, 4732 }, 4733 #endif /* chips */ 4734 4735 #if defined(BCM_56850_A0) 4736 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56850_A0fmt */ 4737 /* format LEARN_BUSfmt */ 4738 /* nFields */ 17, 4739 /* *fields */ soc_LEARN_BUS_BCM56850_A0fmt_fields, 4740 /* bits */ 93, 4741 /* flags */ 0, 4742 }, 4743 #endif /* chips */ 4744 4745 #if defined(BCM_56860_A0) 4746 { /* SOC_FORMAT_INT_LEARN_BUS_BCM56860_A0fmt */ 4747 /* format LEARN_BUSfmt */ 4748 /* nFields */ 17, 4749 /* *fields */ soc_LEARN_BUS_BCM56860_A0fmt_fields, 4750 /* bits */ 93, 4751 /* flags */ 0, 4752 }, 4753 #endif /* chips */ 4754 4755 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4756 defined(BCM_56970_A0) 4757 { /* SOC_FORMAT_INT_LEARN_DATAfmt */ 4758 /* format LEARN_DATAfmt */ 4759 /* nFields */ 11, 4760 /* *fields */ soc_LEARN_DATAfmt_fields, 4761 /* bits */ 106, 4762 /* flags */ 0, 4763 }, 4764 #endif /* chips */ 4765 4766 #if defined(BCM_56370_A0) 4767 { /* SOC_FORMAT_INT_LEARN_DATA_BCM56370_A0fmt */ 4768 /* format LEARN_DATAfmt */ 4769 /* nFields */ 9, 4770 /* *fields */ soc_LEARN_DATA_BCM56370_A0fmt_fields, 4771 /* bits */ 109, 4772 /* flags */ 0, 4773 }, 4774 #endif /* chips */ 4775 4776 #if defined(BCM_56770_A0) 4777 { /* SOC_FORMAT_INT_LEARN_DATA_BCM56770_A0fmt */ 4778 /* format LEARN_DATAfmt */ 4779 /* nFields */ 8, 4780 /* *fields */ soc_LEARN_DATA_BCM56870_A0fmt_fields, 4781 /* bits */ 109, 4782 /* flags */ 0, 4783 }, 4784 #endif /* chips */ 4785 4786 #if defined(BCM_56870_A0) 4787 { /* SOC_FORMAT_INT_LEARN_DATA_BCM56870_A0fmt */ 4788 /* format LEARN_DATAfmt */ 4789 /* nFields */ 8, 4790 /* *fields */ soc_LEARN_DATA_BCM56870_A0fmt_fields, 4791 /* bits */ 109, 4792 /* flags */ 0, 4793 }, 4794 #endif /* chips */ 4795 4796 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4797 { /* SOC_FORMAT_INT_LEVEL1_DATA_REQ_BUSfmt */ 4798 /* format LEVEL1_DATA_REQ_BUSfmt */ 4799 /* nFields */ 2, 4800 /* *fields */ soc_LEVEL1_DATA_REQ_BUSfmt_fields, 4801 /* bits */ 11, 4802 /* flags */ 0, 4803 }, 4804 #endif /* chips */ 4805 4806 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4807 { /* SOC_FORMAT_INT_LEVEL1_DATA_RST_BUSfmt */ 4808 /* format LEVEL1_DATA_RST_BUSfmt */ 4809 /* nFields */ 2, 4810 /* *fields */ soc_LEVEL1_DATA_RST_BUSfmt_fields, 4811 /* bits */ 2, 4812 /* flags */ 0, 4813 }, 4814 #endif /* chips */ 4815 4816 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4817 { /* SOC_FORMAT_INT_LEVEL1_REQ_BUSfmt */ 4818 /* format LEVEL1_REQ_BUSfmt */ 4819 /* nFields */ 1, 4820 /* *fields */ soc_LEVEL1_REQ_BUSfmt_fields, 4821 /* bits */ 2, 4822 /* flags */ 0, 4823 }, 4824 #endif /* chips */ 4825 4826 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4827 { /* SOC_FORMAT_INT_LEVEL1_RST_BUSfmt */ 4828 /* format LEVEL1_RST_BUSfmt */ 4829 /* nFields */ 4, 4830 /* *fields */ soc_LEVEL1_RST_BUSfmt_fields, 4831 /* bits */ 4, 4832 /* flags */ 0, 4833 }, 4834 #endif /* chips */ 4835 4836 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4837 { /* SOC_FORMAT_INT_LEVEL1_TCAM_REQ_BUSfmt */ 4838 /* format LEVEL1_TCAM_REQ_BUSfmt */ 4839 /* nFields */ 4, 4840 /* *fields */ soc_LEVEL1_TCAM_REQ_BUSfmt_fields, 4841 /* bits */ 15, 4842 /* flags */ 0, 4843 }, 4844 #endif /* chips */ 4845 4846 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4847 { /* SOC_FORMAT_INT_LEVEL1_TCAM_RST_BUSfmt */ 4848 /* format LEVEL1_TCAM_RST_BUSfmt */ 4849 /* nFields */ 3, 4850 /* *fields */ soc_LEVEL1_TCAM_RST_BUSfmt_fields, 4851 /* bits */ 4, 4852 /* flags */ 0, 4853 }, 4854 #endif /* chips */ 4855 4856 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4857 defined(BCM_56870_A0) 4858 { /* SOC_FORMAT_INT_LLC_HDRfmt */ 4859 /* format LLC_HDRfmt */ 4860 /* nFields */ 3, 4861 /* *fields */ soc_LLC_HDRfmt_fields, 4862 /* bits */ 24, 4863 /* flags */ 0, 4864 }, 4865 #endif /* chips */ 4866 4867 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 4868 { /* SOC_FORMAT_INT_LMFC_COMMON_BUSfmt */ 4869 /* format LMFC_COMMON_BUSfmt */ 4870 /* nFields */ 13, 4871 /* *fields */ soc_LMFC_COMMON_BUSfmt_fields, 4872 /* bits */ 52, 4873 /* flags */ 0, 4874 }, 4875 #endif /* chips */ 4876 4877 #if defined(BCM_56270_A0) 4878 { /* SOC_FORMAT_INT_LMFC_COMMON_BUS_BCM56270_A0fmt */ 4879 /* format LMFC_COMMON_BUSfmt */ 4880 /* nFields */ 14, 4881 /* *fields */ soc_LMFC_COMMON_BUS_BCM56270_A0fmt_fields, 4882 /* bits */ 53, 4883 /* flags */ 0, 4884 }, 4885 #endif /* chips */ 4886 4887 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 4888 { /* SOC_FORMAT_INT_LMFC_COUNTER_POOL_BUSfmt */ 4889 /* format LMFC_COUNTER_POOL_BUSfmt */ 4890 /* nFields */ 10, 4891 /* *fields */ soc_LMFC_COUNTER_POOL_BUSfmt_fields, 4892 /* bits */ 31, 4893 /* flags */ 0, 4894 }, 4895 #endif /* chips */ 4896 4897 #if defined(BCM_56270_A0) 4898 { /* SOC_FORMAT_INT_LMFC_COUNTER_POOL_BUS_BCM56270_A0fmt */ 4899 /* format LMFC_COUNTER_POOL_BUSfmt */ 4900 /* nFields */ 10, 4901 /* *fields */ soc_LMFC_COUNTER_POOL_BUS_BCM56270_A0fmt_fields, 4902 /* bits */ 29, 4903 /* flags */ 0, 4904 }, 4905 #endif /* chips */ 4906 4907 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 4908 { /* SOC_FORMAT_INT_LMFC_EOP_BUFFERfmt */ 4909 /* format LMFC_EOP_BUFFERfmt */ 4910 /* nFields */ 5, 4911 /* *fields */ soc_LMFC_EOP_BUFFERfmt_fields, 4912 /* bits */ 19, 4913 /* flags */ 0, 4914 }, 4915 #endif /* chips */ 4916 4917 #if defined(BCM_56270_A0) 4918 { /* SOC_FORMAT_INT_LMFC_EOP_BUFFER_BCM56270_A0fmt */ 4919 /* format LMFC_EOP_BUFFERfmt */ 4920 /* nFields */ 4, 4921 /* *fields */ soc_LMFC_EOP_BUFFER_BCM56270_A0fmt_fields, 4922 /* bits */ 16, 4923 /* flags */ 0, 4924 }, 4925 #endif /* chips */ 4926 4927 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 4928 { /* SOC_FORMAT_INT_LMFC_INT_CNTR_BUSfmt */ 4929 /* format LMFC_INT_CNTR_BUSfmt */ 4930 /* nFields */ 18, 4931 /* *fields */ soc_LMFC_INT_CNTR_BUSfmt_fields, 4932 /* bits */ 59, 4933 /* flags */ 0, 4934 }, 4935 #endif /* chips */ 4936 4937 #if defined(BCM_56270_A0) 4938 { /* SOC_FORMAT_INT_LMFC_INT_CNTR_BUS_BCM56270_A0fmt */ 4939 /* format LMFC_INT_CNTR_BUSfmt */ 4940 /* nFields */ 18, 4941 /* *fields */ soc_LMFC_INT_CNTR_BUS_BCM56270_A0fmt_fields, 4942 /* bits */ 57, 4943 /* flags */ 0, 4944 }, 4945 #endif /* chips */ 4946 4947 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 4948 { /* SOC_FORMAT_INT_LMFC_IN_BUSfmt */ 4949 /* format LMFC_IN_BUSfmt */ 4950 /* nFields */ 4, 4951 /* *fields */ soc_LMFC_IN_BUSfmt_fields, 4952 /* bits */ 352, 4953 /* flags */ 0, 4954 }, 4955 #endif /* chips */ 4956 4957 #if defined(BCM_56270_A0) 4958 { /* SOC_FORMAT_INT_LMFC_IN_BUS_BCM56270_A0fmt */ 4959 /* format LMFC_IN_BUSfmt */ 4960 /* nFields */ 4, 4961 /* *fields */ soc_LMFC_IN_BUS_BCM56270_A0fmt_fields, 4962 /* bits */ 335, 4963 /* flags */ 0, 4964 }, 4965 #endif /* chips */ 4966 4967 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4968 defined(BCM_56270_A0) 4969 { /* SOC_FORMAT_INT_LMFC_OUT_BUSfmt */ 4970 /* format LMFC_OUT_BUSfmt */ 4971 /* nFields */ 3, 4972 /* *fields */ soc_LMFC_OUT_BUSfmt_fields, 4973 /* bits */ 228, 4974 /* flags */ 0, 4975 }, 4976 #endif /* chips */ 4977 4978 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4979 defined(BCM_56270_A0) 4980 { /* SOC_FORMAT_INT_LMFC_PARITY_STATUS_BUSfmt */ 4981 /* format LMFC_PARITY_STATUS_BUSfmt */ 4982 /* nFields */ 6, 4983 /* *fields */ soc_LMFC_PARITY_STATUS_BUSfmt_fields, 4984 /* bits */ 6, 4985 /* flags */ 0, 4986 }, 4987 #endif /* chips */ 4988 4989 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 4990 defined(BCM_56270_A0) 4991 { /* SOC_FORMAT_INT_LMFC_SAMPLE_DATAfmt */ 4992 /* format LMFC_SAMPLE_DATAfmt */ 4993 /* nFields */ 6, 4994 /* *fields */ soc_LMFC_SAMPLE_DATAfmt_fields, 4995 /* bits */ 76, 4996 /* flags */ 0, 4997 }, 4998 #endif /* chips */ 4999 5000 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 5001 { /* SOC_FORMAT_INT_LMFC_SRC_INTF_BUSfmt */ 5002 /* format LMFC_SRC_INTF_BUSfmt */ 5003 /* nFields */ 4, 5004 /* *fields */ soc_LMFC_SRC_INTF_BUSfmt_fields, 5005 /* bits */ 100, 5006 /* flags */ 0, 5007 }, 5008 #endif /* chips */ 5009 5010 #if defined(BCM_56270_A0) 5011 { /* SOC_FORMAT_INT_LMFC_SRC_INTF_BUS_BCM56270_A0fmt */ 5012 /* format LMFC_SRC_INTF_BUSfmt */ 5013 /* nFields */ 4, 5014 /* *fields */ soc_LMFC_SRC_INTF_BUS_BCM56270_A0fmt_fields, 5015 /* bits */ 94, 5016 /* flags */ 0, 5017 }, 5018 #endif /* chips */ 5019 5020 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 5021 defined(BCM_56270_A0) 5022 { /* SOC_FORMAT_INT_LMFC_SRC_INTF_COMMON_BUSfmt */ 5023 /* format LMFC_SRC_INTF_COMMON_BUSfmt */ 5024 /* nFields */ 4, 5025 /* *fields */ soc_LMFC_SRC_INTF_COMMON_BUSfmt_fields, 5026 /* bits */ 7, 5027 /* flags */ 0, 5028 }, 5029 #endif /* chips */ 5030 5031 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 5032 defined(BCM_56634_B0) || defined(BCM_56685_A0) || \ 5033 defined(BCM_56685_B0) 5034 { /* SOC_FORMAT_INT_LOOPBACK_MHfmt */ 5035 /* format LOOPBACK_MHfmt */ 5036 /* nFields */ 26, 5037 /* *fields */ soc_LOOPBACK_MHfmt_fields, 5038 /* bits */ 128, 5039 /* flags */ 0, 5040 }, 5041 #endif /* chips */ 5042 5043 #if defined(BCM_53400_A0) 5044 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM53400_A0fmt */ 5045 /* format LOOPBACK_MHfmt */ 5046 /* nFields */ 6, 5047 /* *fields */ soc_LOOPBACK_MH_BCM53400_A0fmt_fields, 5048 /* bits */ 128, 5049 /* flags */ 0, 5050 }, 5051 #endif /* chips */ 5052 5053 #if defined(BCM_53540_A0) 5054 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM53540_A0fmt */ 5055 /* format LOOPBACK_MHfmt */ 5056 /* nFields */ 6, 5057 /* *fields */ soc_LOOPBACK_MH_BCM53400_A0fmt_fields, 5058 /* bits */ 128, 5059 /* flags */ 0, 5060 }, 5061 #endif /* chips */ 5062 5063 #if defined(BCM_53570_A0) 5064 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM53570_A0fmt */ 5065 /* format LOOPBACK_MHfmt */ 5066 /* nFields */ 6, 5067 /* *fields */ soc_LOOPBACK_MH_BCM53400_A0fmt_fields, 5068 /* bits */ 128, 5069 /* flags */ 0, 5070 }, 5071 #endif /* chips */ 5072 5073 #if defined(BCM_53570_B0) 5074 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM53570_B0fmt */ 5075 /* format LOOPBACK_MHfmt */ 5076 /* nFields */ 6, 5077 /* *fields */ soc_LOOPBACK_MH_BCM53400_A0fmt_fields, 5078 /* bits */ 128, 5079 /* flags */ 0, 5080 }, 5081 #endif /* chips */ 5082 5083 #if defined(BCM_56142_A0) 5084 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56142_A0fmt */ 5085 /* format LOOPBACK_MHfmt */ 5086 /* nFields */ 6, 5087 /* *fields */ soc_LOOPBACK_MH_BCM56334_A0fmt_fields, 5088 /* bits */ 128, 5089 /* flags */ 0, 5090 }, 5091 #endif /* chips */ 5092 5093 #if defined(BCM_56150_A0) 5094 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56150_A0fmt */ 5095 /* format LOOPBACK_MHfmt */ 5096 /* nFields */ 6, 5097 /* *fields */ soc_LOOPBACK_MH_BCM56150_A0fmt_fields, 5098 /* bits */ 128, 5099 /* flags */ 0, 5100 }, 5101 #endif /* chips */ 5102 5103 #if defined(BCM_56160_A0) 5104 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56160_A0fmt */ 5105 /* format LOOPBACK_MHfmt */ 5106 /* nFields */ 6, 5107 /* *fields */ soc_LOOPBACK_MH_BCM53400_A0fmt_fields, 5108 /* bits */ 128, 5109 /* flags */ 0, 5110 }, 5111 #endif /* chips */ 5112 5113 #if defined(BCM_56260_A0) 5114 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56260_A0fmt */ 5115 /* format LOOPBACK_MHfmt */ 5116 /* nFields */ 26, 5117 /* *fields */ soc_LOOPBACK_MH_BCM56260_A0fmt_fields, 5118 /* bits */ 128, 5119 /* flags */ 0, 5120 }, 5121 #endif /* chips */ 5122 5123 #if defined(BCM_56260_B0) 5124 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56260_B0fmt */ 5125 /* format LOOPBACK_MHfmt */ 5126 /* nFields */ 26, 5127 /* *fields */ soc_LOOPBACK_MH_BCM56260_A0fmt_fields, 5128 /* bits */ 128, 5129 /* flags */ 0, 5130 }, 5131 #endif /* chips */ 5132 5133 #if defined(BCM_56270_A0) 5134 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56270_A0fmt */ 5135 /* format LOOPBACK_MHfmt */ 5136 /* nFields */ 27, 5137 /* *fields */ soc_LOOPBACK_MH_BCM56270_A0fmt_fields, 5138 /* bits */ 128, 5139 /* flags */ 0, 5140 }, 5141 #endif /* chips */ 5142 5143 #if defined(BCM_56334_A0) 5144 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56334_A0fmt */ 5145 /* format LOOPBACK_MHfmt */ 5146 /* nFields */ 6, 5147 /* *fields */ soc_LOOPBACK_MH_BCM56334_A0fmt_fields, 5148 /* bits */ 128, 5149 /* flags */ 0, 5150 }, 5151 #endif /* chips */ 5152 5153 #if defined(BCM_56334_B0) 5154 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56334_B0fmt */ 5155 /* format LOOPBACK_MHfmt */ 5156 /* nFields */ 6, 5157 /* *fields */ soc_LOOPBACK_MH_BCM56334_A0fmt_fields, 5158 /* bits */ 128, 5159 /* flags */ 0, 5160 }, 5161 #endif /* chips */ 5162 5163 #if defined(BCM_56370_A0) 5164 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56370_A0fmt */ 5165 /* format LOOPBACK_MHfmt */ 5166 /* nFields */ 11, 5167 /* *fields */ soc_LOOPBACK_MH_BCM56870_A0fmt_fields, 5168 /* bits */ 128, 5169 /* flags */ 0, 5170 }, 5171 #endif /* chips */ 5172 5173 #if defined(BCM_56440_A0) 5174 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56440_A0fmt */ 5175 /* format LOOPBACK_MHfmt */ 5176 /* nFields */ 24, 5177 /* *fields */ soc_LOOPBACK_MH_BCM56840_B0fmt_fields, 5178 /* bits */ 128, 5179 /* flags */ 0, 5180 }, 5181 #endif /* chips */ 5182 5183 #if defined(BCM_56440_B0) 5184 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56440_B0fmt */ 5185 /* format LOOPBACK_MHfmt */ 5186 /* nFields */ 24, 5187 /* *fields */ soc_LOOPBACK_MH_BCM56840_B0fmt_fields, 5188 /* bits */ 128, 5189 /* flags */ 0, 5190 }, 5191 #endif /* chips */ 5192 5193 #if defined(BCM_56450_A0) 5194 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56450_A0fmt */ 5195 /* format LOOPBACK_MHfmt */ 5196 /* nFields */ 25, 5197 /* *fields */ soc_LOOPBACK_MH_BCM56450_A0fmt_fields, 5198 /* bits */ 128, 5199 /* flags */ 0, 5200 }, 5201 #endif /* chips */ 5202 5203 #if defined(BCM_56450_B0) 5204 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56450_B0fmt */ 5205 /* format LOOPBACK_MHfmt */ 5206 /* nFields */ 25, 5207 /* *fields */ soc_LOOPBACK_MH_BCM56450_A0fmt_fields, 5208 /* bits */ 128, 5209 /* flags */ 0, 5210 }, 5211 #endif /* chips */ 5212 5213 #if defined(BCM_56450_B1) 5214 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56450_B1fmt */ 5215 /* format LOOPBACK_MHfmt */ 5216 /* nFields */ 25, 5217 /* *fields */ soc_LOOPBACK_MH_BCM56450_A0fmt_fields, 5218 /* bits */ 128, 5219 /* flags */ 0, 5220 }, 5221 #endif /* chips */ 5222 5223 #if defined(BCM_56524_B0) 5224 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56524_B0fmt */ 5225 /* format LOOPBACK_MHfmt */ 5226 /* nFields */ 26, 5227 /* *fields */ soc_LOOPBACK_MHfmt_fields, 5228 /* bits */ 128, 5229 /* flags */ 0, 5230 }, 5231 #endif /* chips */ 5232 5233 #if defined(BCM_56560_A0) 5234 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56560_A0fmt */ 5235 /* format LOOPBACK_MHfmt */ 5236 /* nFields */ 42, 5237 /* *fields */ soc_LOOPBACK_MH_BCM56560_A0fmt_fields, 5238 /* bits */ 128, 5239 /* flags */ 0, 5240 }, 5241 #endif /* chips */ 5242 5243 #if defined(BCM_56560_B0) 5244 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56560_B0fmt */ 5245 /* format LOOPBACK_MHfmt */ 5246 /* nFields */ 42, 5247 /* *fields */ soc_LOOPBACK_MH_BCM56560_A0fmt_fields, 5248 /* bits */ 128, 5249 /* flags */ 0, 5250 }, 5251 #endif /* chips */ 5252 5253 #if defined(BCM_56670_A0) 5254 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56670_A0fmt */ 5255 /* format LOOPBACK_MHfmt */ 5256 /* nFields */ 42, 5257 /* *fields */ soc_LOOPBACK_MH_BCM56560_A0fmt_fields, 5258 /* bits */ 128, 5259 /* flags */ 0, 5260 }, 5261 #endif /* chips */ 5262 5263 #if defined(BCM_56670_B0) 5264 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56670_B0fmt */ 5265 /* format LOOPBACK_MHfmt */ 5266 /* nFields */ 42, 5267 /* *fields */ soc_LOOPBACK_MH_BCM56560_A0fmt_fields, 5268 /* bits */ 128, 5269 /* flags */ 0, 5270 }, 5271 #endif /* chips */ 5272 5273 #if defined(BCM_56770_A0) 5274 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56770_A0fmt */ 5275 /* format LOOPBACK_MHfmt */ 5276 /* nFields */ 11, 5277 /* *fields */ soc_LOOPBACK_MH_BCM56870_A0fmt_fields, 5278 /* bits */ 128, 5279 /* flags */ 0, 5280 }, 5281 #endif /* chips */ 5282 5283 #if defined(BCM_56840_A0) 5284 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56840_A0fmt */ 5285 /* format LOOPBACK_MHfmt */ 5286 /* nFields */ 24, 5287 /* *fields */ soc_LOOPBACK_MH_BCM56840_A0fmt_fields, 5288 /* bits */ 128, 5289 /* flags */ 0, 5290 }, 5291 #endif /* chips */ 5292 5293 #if defined(BCM_56840_B0) 5294 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56840_B0fmt */ 5295 /* format LOOPBACK_MHfmt */ 5296 /* nFields */ 24, 5297 /* *fields */ soc_LOOPBACK_MH_BCM56840_B0fmt_fields, 5298 /* bits */ 128, 5299 /* flags */ 0, 5300 }, 5301 #endif /* chips */ 5302 5303 #if defined(BCM_56850_A0) 5304 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56850_A0fmt */ 5305 /* format LOOPBACK_MHfmt */ 5306 /* nFields */ 26, 5307 /* *fields */ soc_LOOPBACK_MH_BCM56850_A0fmt_fields, 5308 /* bits */ 128, 5309 /* flags */ 0, 5310 }, 5311 #endif /* chips */ 5312 5313 #if defined(BCM_56860_A0) 5314 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56860_A0fmt */ 5315 /* format LOOPBACK_MHfmt */ 5316 /* nFields */ 29, 5317 /* *fields */ soc_LOOPBACK_MH_BCM56860_A0fmt_fields, 5318 /* bits */ 128, 5319 /* flags */ 0, 5320 }, 5321 #endif /* chips */ 5322 5323 #if defined(BCM_56870_A0) 5324 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56870_A0fmt */ 5325 /* format LOOPBACK_MHfmt */ 5326 /* nFields */ 11, 5327 /* *fields */ soc_LOOPBACK_MH_BCM56870_A0fmt_fields, 5328 /* bits */ 128, 5329 /* flags */ 0, 5330 }, 5331 #endif /* chips */ 5332 5333 #if defined(BCM_56960_A0) 5334 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56960_A0fmt */ 5335 /* format LOOPBACK_MHfmt */ 5336 /* nFields */ 25, 5337 /* *fields */ soc_LOOPBACK_MH_BCM56960_A0fmt_fields, 5338 /* bits */ 128, 5339 /* flags */ 0, 5340 }, 5341 #endif /* chips */ 5342 5343 #if defined(BCM_56965_A0) 5344 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56965_A0fmt */ 5345 /* format LOOPBACK_MHfmt */ 5346 /* nFields */ 25, 5347 /* *fields */ soc_LOOPBACK_MH_BCM56960_A0fmt_fields, 5348 /* bits */ 128, 5349 /* flags */ 0, 5350 }, 5351 #endif /* chips */ 5352 5353 #if defined(BCM_56970_A0) 5354 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56970_A0fmt */ 5355 /* format LOOPBACK_MHfmt */ 5356 /* nFields */ 25, 5357 /* *fields */ soc_LOOPBACK_MH_BCM56960_A0fmt_fields, 5358 /* bits */ 128, 5359 /* flags */ 0, 5360 }, 5361 #endif /* chips */ 5362 5363 #if defined(BCM_56980_A0) 5364 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56980_A0fmt */ 5365 /* format LOOPBACK_MHfmt */ 5366 /* nFields */ 37, 5367 /* *fields */ soc_LOOPBACK_MH_BCM56980_A0fmt_fields, 5368 /* bits */ 128, 5369 /* flags */ 0, 5370 }, 5371 #endif /* chips */ 5372 5373 #if defined(BCM_56980_B0) 5374 { /* SOC_FORMAT_INT_LOOPBACK_MH_BCM56980_B0fmt */ 5375 /* format LOOPBACK_MHfmt */ 5376 /* nFields */ 37, 5377 /* *fields */ soc_LOOPBACK_MH_BCM56980_A0fmt_fields, 5378 /* bits */ 128, 5379 /* flags */ 0, 5380 }, 5381 #endif /* chips */ 5382 5383 #if defined(BCM_56850_A0) 5384 { /* SOC_FORMAT_INT_LPM_IN_BUSfmt */ 5385 /* format LPM_IN_BUSfmt */ 5386 /* nFields */ 27, 5387 /* *fields */ soc_LPM_IN_BUSfmt_fields, 5388 /* bits */ 351, 5389 /* flags */ 0, 5390 }, 5391 #endif /* chips */ 5392 5393 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5394 defined(BCM_56970_A0) 5395 { /* SOC_FORMAT_INT_LPM_IN_BUS_2fmt */ 5396 /* format LPM_IN_BUS_2fmt */ 5397 /* nFields */ 6, 5398 /* *fields */ soc_LPM_IN_BUS_2fmt_fields, 5399 /* bits */ 25, 5400 /* flags */ 0, 5401 }, 5402 #endif /* chips */ 5403 5404 #if defined(BCM_56560_A0) 5405 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56560_A0fmt */ 5406 /* format LPM_IN_BUSfmt */ 5407 /* nFields */ 31, 5408 /* *fields */ soc_LPM_IN_BUS_BCM56560_A0fmt_fields, 5409 /* bits */ 374, 5410 /* flags */ 0, 5411 }, 5412 #endif /* chips */ 5413 5414 #if defined(BCM_56560_B0) 5415 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56560_B0fmt */ 5416 /* format LPM_IN_BUSfmt */ 5417 /* nFields */ 31, 5418 /* *fields */ soc_LPM_IN_BUS_BCM56560_A0fmt_fields, 5419 /* bits */ 374, 5420 /* flags */ 0, 5421 }, 5422 #endif /* chips */ 5423 5424 #if defined(BCM_56670_A0) 5425 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56670_A0fmt */ 5426 /* format LPM_IN_BUSfmt */ 5427 /* nFields */ 31, 5428 /* *fields */ soc_LPM_IN_BUS_BCM56560_A0fmt_fields, 5429 /* bits */ 374, 5430 /* flags */ 0, 5431 }, 5432 #endif /* chips */ 5433 5434 #if defined(BCM_56670_B0) 5435 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56670_B0fmt */ 5436 /* format LPM_IN_BUSfmt */ 5437 /* nFields */ 31, 5438 /* *fields */ soc_LPM_IN_BUS_BCM56560_A0fmt_fields, 5439 /* bits */ 374, 5440 /* flags */ 0, 5441 }, 5442 #endif /* chips */ 5443 5444 #if defined(BCM_56860_A0) 5445 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56860_A0fmt */ 5446 /* format LPM_IN_BUSfmt */ 5447 /* nFields */ 31, 5448 /* *fields */ soc_LPM_IN_BUS_BCM56860_A0fmt_fields, 5449 /* bits */ 372, 5450 /* flags */ 0, 5451 }, 5452 #endif /* chips */ 5453 5454 #if defined(BCM_56960_A0) 5455 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56960_A0fmt */ 5456 /* format LPM_IN_BUSfmt */ 5457 /* nFields */ 16, 5458 /* *fields */ soc_LPM_IN_BUS_BCM56960_A0fmt_fields, 5459 /* bits */ 295, 5460 /* flags */ 0, 5461 }, 5462 #endif /* chips */ 5463 5464 #if defined(BCM_56965_A0) 5465 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56965_A0fmt */ 5466 /* format LPM_IN_BUSfmt */ 5467 /* nFields */ 16, 5468 /* *fields */ soc_LPM_IN_BUS_BCM56960_A0fmt_fields, 5469 /* bits */ 295, 5470 /* flags */ 0, 5471 }, 5472 #endif /* chips */ 5473 5474 #if defined(BCM_56970_A0) 5475 { /* SOC_FORMAT_INT_LPM_IN_BUS_BCM56970_A0fmt */ 5476 /* format LPM_IN_BUSfmt */ 5477 /* nFields */ 16, 5478 /* *fields */ soc_LPM_IN_BUS_BCM56960_A0fmt_fields, 5479 /* bits */ 295, 5480 /* flags */ 0, 5481 }, 5482 #endif /* chips */ 5483 5484 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5485 { /* SOC_FORMAT_INT_LPM_IP_BUS_L1L2_TO_L3fmt */ 5486 /* format LPM_IP_BUS_L1L2_TO_L3fmt */ 5487 /* nFields */ 49, 5488 /* *fields */ soc_LPM_IP_BUS_L1L2_TO_L3fmt_fields, 5489 /* bits */ 818, 5490 /* flags */ 0, 5491 }, 5492 #endif /* chips */ 5493 5494 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5495 { /* SOC_FORMAT_INT_LPM_IP_CONTROL_FULL_SETfmt */ 5496 /* format LPM_IP_CONTROL_FULL_SETfmt */ 5497 /* nFields */ 41, 5498 /* *fields */ soc_LPM_IP_CONTROL_FULL_SETfmt_fields, 5499 /* bits */ 158, 5500 /* flags */ 0, 5501 }, 5502 #endif /* chips */ 5503 5504 #if defined(BCM_56850_A0) 5505 { /* SOC_FORMAT_INT_LPM_OUT_BUSfmt */ 5506 /* format LPM_OUT_BUSfmt */ 5507 /* nFields */ 38, 5508 /* *fields */ soc_LPM_OUT_BUSfmt_fields, 5509 /* bits */ 164, 5510 /* flags */ 0, 5511 }, 5512 #endif /* chips */ 5513 5514 #if defined(BCM_56560_A0) 5515 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56560_A0fmt */ 5516 /* format LPM_OUT_BUSfmt */ 5517 /* nFields */ 45, 5518 /* *fields */ soc_LPM_OUT_BUS_BCM56560_A0fmt_fields, 5519 /* bits */ 187, 5520 /* flags */ 0, 5521 }, 5522 #endif /* chips */ 5523 5524 #if defined(BCM_56560_B0) 5525 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56560_B0fmt */ 5526 /* format LPM_OUT_BUSfmt */ 5527 /* nFields */ 45, 5528 /* *fields */ soc_LPM_OUT_BUS_BCM56560_A0fmt_fields, 5529 /* bits */ 187, 5530 /* flags */ 0, 5531 }, 5532 #endif /* chips */ 5533 5534 #if defined(BCM_56670_A0) 5535 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56670_A0fmt */ 5536 /* format LPM_OUT_BUSfmt */ 5537 /* nFields */ 45, 5538 /* *fields */ soc_LPM_OUT_BUS_BCM56670_A0fmt_fields, 5539 /* bits */ 184, 5540 /* flags */ 0, 5541 }, 5542 #endif /* chips */ 5543 5544 #if defined(BCM_56670_B0) 5545 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56670_B0fmt */ 5546 /* format LPM_OUT_BUSfmt */ 5547 /* nFields */ 45, 5548 /* *fields */ soc_LPM_OUT_BUS_BCM56670_A0fmt_fields, 5549 /* bits */ 184, 5550 /* flags */ 0, 5551 }, 5552 #endif /* chips */ 5553 5554 #if defined(BCM_56860_A0) 5555 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56860_A0fmt */ 5556 /* format LPM_OUT_BUSfmt */ 5557 /* nFields */ 45, 5558 /* *fields */ soc_LPM_OUT_BUS_BCM56860_A0fmt_fields, 5559 /* bits */ 191, 5560 /* flags */ 0, 5561 }, 5562 #endif /* chips */ 5563 5564 #if defined(BCM_56960_A0) 5565 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56960_A0fmt */ 5566 /* format LPM_OUT_BUSfmt */ 5567 /* nFields */ 29, 5568 /* *fields */ soc_LPM_OUT_BUS_BCM56960_A0fmt_fields, 5569 /* bits */ 132, 5570 /* flags */ 0, 5571 }, 5572 #endif /* chips */ 5573 5574 #if defined(BCM_56965_A0) 5575 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56965_A0fmt */ 5576 /* format LPM_OUT_BUSfmt */ 5577 /* nFields */ 29, 5578 /* *fields */ soc_LPM_OUT_BUS_BCM56960_A0fmt_fields, 5579 /* bits */ 132, 5580 /* flags */ 0, 5581 }, 5582 #endif /* chips */ 5583 5584 #if defined(BCM_56970_A0) 5585 { /* SOC_FORMAT_INT_LPM_OUT_BUS_BCM56970_A0fmt */ 5586 /* format LPM_OUT_BUSfmt */ 5587 /* nFields */ 29, 5588 /* *fields */ soc_LPM_OUT_BUS_BCM56970_A0fmt_fields, 5589 /* bits */ 134, 5590 /* flags */ 0, 5591 }, 5592 #endif /* chips */ 5593 5594 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 5595 defined(BCM_56450_B1) 5596 { /* SOC_FORMAT_INT_LP_HEADER_ETH_MODEfmt */ 5597 /* format LP_HEADER_ETH_MODEfmt */ 5598 /* nFields */ 9, 5599 /* *fields */ soc_LP_HEADER_ETH_MODEfmt_fields, 5600 /* bits */ 144, 5601 /* flags */ 0, 5602 }, 5603 #endif /* chips */ 5604 5605 #if defined(BCM_56260_A0) 5606 { /* SOC_FORMAT_INT_LP_HEADER_ETH_MODE_BCM56260_A0fmt */ 5607 /* format LP_HEADER_ETH_MODEfmt */ 5608 /* nFields */ 9, 5609 /* *fields */ soc_LP_HEADER_ETH_MODE_BCM56260_A0fmt_fields, 5610 /* bits */ 144, 5611 /* flags */ 0, 5612 }, 5613 #endif /* chips */ 5614 5615 #if defined(BCM_56260_B0) 5616 { /* SOC_FORMAT_INT_LP_HEADER_ETH_MODE_BCM56260_B0fmt */ 5617 /* format LP_HEADER_ETH_MODEfmt */ 5618 /* nFields */ 9, 5619 /* *fields */ soc_LP_HEADER_ETH_MODE_BCM56260_A0fmt_fields, 5620 /* bits */ 144, 5621 /* flags */ 0, 5622 }, 5623 #endif /* chips */ 5624 5625 #if defined(BCM_56270_A0) 5626 { /* SOC_FORMAT_INT_LP_HEADER_ETH_MODE_BCM56270_A0fmt */ 5627 /* format LP_HEADER_ETH_MODEfmt */ 5628 /* nFields */ 9, 5629 /* *fields */ soc_LP_HEADER_ETH_MODE_BCM56260_A0fmt_fields, 5630 /* bits */ 144, 5631 /* flags */ 0, 5632 }, 5633 #endif /* chips */ 5634 5635 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 5636 defined(BCM_56450_B1) 5637 { /* SOC_FORMAT_INT_LP_HEADER_TCI_LENGTH_MODEfmt */ 5638 /* format LP_HEADER_TCI_LENGTH_MODEfmt */ 5639 /* nFields */ 6, 5640 /* *fields */ soc_LP_HEADER_TCI_LENGTH_MODEfmt_fields, 5641 /* bits */ 32, 5642 /* flags */ 0, 5643 }, 5644 #endif /* chips */ 5645 5646 #if defined(BCM_56260_A0) 5647 { /* SOC_FORMAT_INT_LP_HEADER_TCI_LENGTH_MODE_BCM56260_A0fmt */ 5648 /* format LP_HEADER_TCI_LENGTH_MODEfmt */ 5649 /* nFields */ 6, 5650 /* *fields */ soc_LP_HEADER_TCI_LENGTH_MODE_BCM56260_A0fmt_fields, 5651 /* bits */ 32, 5652 /* flags */ 0, 5653 }, 5654 #endif /* chips */ 5655 5656 #if defined(BCM_56260_B0) 5657 { /* SOC_FORMAT_INT_LP_HEADER_TCI_LENGTH_MODE_BCM56260_B0fmt */ 5658 /* format LP_HEADER_TCI_LENGTH_MODEfmt */ 5659 /* nFields */ 6, 5660 /* *fields */ soc_LP_HEADER_TCI_LENGTH_MODE_BCM56260_A0fmt_fields, 5661 /* bits */ 32, 5662 /* flags */ 0, 5663 }, 5664 #endif /* chips */ 5665 5666 #if defined(BCM_56270_A0) 5667 { /* SOC_FORMAT_INT_LP_HEADER_TCI_LENGTH_MODE_BCM56270_A0fmt */ 5668 /* format LP_HEADER_TCI_LENGTH_MODEfmt */ 5669 /* nFields */ 6, 5670 /* *fields */ soc_LP_HEADER_TCI_LENGTH_MODE_BCM56260_A0fmt_fields, 5671 /* bits */ 32, 5672 /* flags */ 0, 5673 }, 5674 #endif /* chips */ 5675